1 ;; GCC machine description for CRIS cpu cores.
2 ;; Copyright (C)
1998,
1999,
2000,
2001,
2002,
2003,
2004,
2005,
2006,
2007,
3 ;;
2008,
2009,
2010 Free Software Foundation, Inc.
4 ;; Contributed by Axis Communications.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version
3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; The original PO technology requires these to be ordered by speed,
23 ;; so that assigner will pick the fastest.
25 ;; See files "md.texi" and "rtl.def" for documentation on define_insn,
28 ;; The function cris_notice_update_cc in cris.c handles condition code
29 ;; updates for most instructions, helped by the "cc" attribute.
31 ;; There are several instructions that are orthogonal in size, and seems
32 ;; they could be matched by a single pattern without a specified size
33 ;; for the operand that is orthogonal. However, this did not work on
34 ;; gcc-
2.7.2 (and probably not on gcc-
2.8.1), relating to that when a
35 ;; constant is substituted into an operand, the actual mode must be
36 ;; deduced from the pattern. There is reasonable hope that that has been
37 ;; fixed, so FIXME: try again.
39 ;; You will notice that three-operand alternatives ("=r", "r", "!To")
40 ;; are marked with a "!" constraint modifier to avoid being reloaded
41 ;; into. This is because gcc would otherwise prefer to use the constant
42 ;; pool and its offsettable address instead of reloading to an
43 ;; ("=r", "
0", "i") alternative. Also, the constant-pool support was not
44 ;; only suboptimal but also buggy in
2.7.2, ??? maybe only in
2.6.3.
46 ;; All insns that look like (set (...) (plus (...) (reg:SI
8)))
47 ;; get problems when reloading r8 (frame pointer) to r14 + offs (stack
48 ;; pointer). Thus the instructions that get into trouble have specific
49 ;; checks against matching frame_pointer_rtx.
50 ;; ??? But it should be re-checked for gcc >
2.7.2
51 ;; FIXME: This changed some time ago (from
2000-
03-
16) for gcc-
2.9x.
53 ;; FIXME: When PIC, all [rX=rY+S] could be enabled to match
54 ;; [rX=gotless_symbol].
55 ;; The movsi for a gotless symbol could be split (post reload).
60 ;; PLT reference from call expansion: operand
0 is the address,
61 ;; the mode is VOIDmode. Always wrapped in CONST.
62 ;; The value is relative to the GOT.
63 (CRIS_UNSPEC_PLT_GOTREL
0)
65 ;; PLT reference from call expansion: operand
0 is the address,
66 ;; the mode is VOIDmode. Always wrapped in CONST.
67 ;; The value is relative to the PC. It's arch-dependent whether
68 ;; the offset counts from the start or the end of the current item.
69 (CRIS_UNSPEC_PLT_PCREL
1)
71 ;; The address of the global offset table as a source operand.
74 ;; The offset from the global offset table to the operand.
75 (CRIS_UNSPEC_GOTREL
3)
77 ;; The PC-relative offset to the operand. It's arch-dependent whether
78 ;; the offset counts from the start or the end of the current item.
81 ;; The index into the global offset table of a symbol, while
82 ;; also generating a GOT entry for the symbol.
83 (CRIS_UNSPEC_GOTREAD
5)
85 ;; Similar to CRIS_UNSPEC_GOTREAD, but also generating a PLT entry.
86 (CRIS_UNSPEC_PLTGOTREAD
6)
88 ;; Condition for v32 casesi jump, since it needs to have if_then_else
89 ;; form with register as one branch and default label as other.
90 ;; Operand
0 is const_int
0.
91 (CRIS_UNSPEC_CASESI
7)
93 ;; Stack frame deallocation barrier.
94 (CRIS_UNSPEC_FRAME_DEALLOC
8)
96 ;; Swap all
32 bits of the operand;
31 <=>
0,
30 <=>
1...
97 (CRIS_UNSPEC_SWAP_BITS
9)
103 (CRIS_STATIC_CHAIN_REGNUM
7)
110 (CRIS_CC0_REGNUM
19)]
113 ;; We need an attribute to define whether an instruction can be put in
114 ;; a branch-delay slot or not, and whether it has a delay slot.
116 ;; Branches and return instructions have a delay slot, and cannot
117 ;; themselves be put in a delay slot. This has changed *for short
118 ;; branches only* between architecture variants, but the possible win
119 ;; is presumed negligible compared to the added complexity of the machine
120 ;; description: one would have to add always-correct infrastructure to
121 ;; distinguish short branches.
123 ;; Whether an instruction can be put in a delay slot depends on the
124 ;; instruction (all short instructions except jumps and branches)
125 ;; and the addressing mode (must not be prefixed or referring to pc).
126 ;; In short, any "slottable" instruction must be
16 bit and not refer
127 ;; to pc, or alter it.
129 ;; The possible values are "yes", "no", "has_slot", "has_return_slot"
130 ;; and "has_call_slot".
131 ;; Yes/no tells whether the insn is slottable or not. Has_call_slot means
132 ;; that the insn is a call insn, which for CRIS v32 has a delay-slot.
133 ;; Of special concern is that no RTX_FRAME_RELATED insn must go in that
134 ;; call delay slot, as it's located in the address *after* the call insn,
135 ;; and the unwind machinery doesn't know about delay slots.
136 ;; Has_slot means that the insn is a branch insn (which are
137 ;; not considered slottable since that is generally true). Having the
138 ;; seemingly illogical value "has_slot" means we do not have to add
139 ;; another attribute just to say that an insn has a delay-slot, since it
140 ;; also infers that it is not slottable. Better names for the attribute
141 ;; were found to be longer and not add readability to the machine
143 ;; Has_return_slot is similar, for the return insn.
145 ;; The default that is defined here for this attribute is "no", not
146 ;; slottable, not having a delay-slot, so there's no need to worry about
147 ;; it being wrong for non-branch and return instructions.
148 ;; The default could depend on the kind of insn and the addressing
149 ;; mode, but that would need more attributes and hairier, more error
152 ;; There is an extra memory constraint, 'Q', which recognizes an indirect
153 ;; register. The constraints 'Q' and '>' together match all possible
154 ;; memory operands that are slottable.
155 ;; For other operands, you need to check if it has a valid "slottable"
156 ;; quick-immediate operand, where the particular signedness-variation
157 ;; may match the constraints 'I' or 'J'.), and include it in the
158 ;; constraint pattern for the slottable pattern. An alternative using
159 ;; only "r" constraints is most often slottable.
161 (define_attr "slottable" "no,yes,has_slot,has_return_slot,has_call_slot"
164 ;; We also need attributes to sanely determine the condition code
165 ;; state. See cris_notice_update_cc for how this is used.
167 (define_attr "cc" "none,clobber,normal,noov32,rev" (const_string "normal"))
169 ;; At the moment, this attribute is just used to help bb-reorder do its
170 ;; work; the default
0 doesn't help it. Many insns have other lengths,
171 ;; though none are shorter.
172 (define_attr "length" "" (const_int
2))
174 ;; A branch has one delay-slot. The instruction in the
175 ;; delay-slot is always executed, independent of whether the branch is
176 ;; taken or not. Note that besides setting "slottable" to "has_slot",
177 ;; there also has to be a "%#" at the end of a "delayed" instruction
178 ;; output pattern (for "jump" this means "ba %l0%#"), so print_operand can
179 ;; catch it and print a "nop" if necessary. This method was stolen from
182 (define_delay (eq_attr "slottable" "has_slot")
183 [(eq_attr "slottable" "yes") (nil) (nil)])
185 ;; We can't put prologue insns in call-insn delay-slots when
186 ;; DWARF2 unwind info is emitted, because the unwinder matches the
187 ;; address after the insn. It must see the return address of a call at
188 ;; a position at least *one byte after* the insn, or it'll think that
189 ;; the insn hasn't been executed. If the insn is in a delay-slot of a
190 ;; call, it's just *exactly* after the insn.
192 (define_delay (eq_attr "slottable" "has_call_slot")
193 [(and (eq_attr "slottable" "yes")
194 (ior (not (match_test "RTX_FRAME_RELATED_P (insn)"))
195 (not (match_test "flag_exceptions"))))
198 ;; The insn in the return insn slot must not be the
199 ;; return-address-register restore. FIXME: Use has_slot and express
200 ;; as a parallel with a use of the return-address-register (currently
201 ;; only SRP). However, this requires an amount of fixing tests for
202 ;; naked RETURN in middle-end.
203 (define_delay (eq_attr "slottable" "has_return_slot")
204 [(and (eq_attr "slottable" "yes")
205 (not (match_test "dead_or_set_regno_p (insn, CRIS_SRP_REGNUM)")))
209 ;; Iterator definitions.
211 ;; For the "usual" pattern size alternatives.
212 (define_mode_iterator BWD [SI HI QI])
213 (define_mode_iterator WD [SI HI])
214 (define_mode_iterator BW [HI QI])
215 (define_mode_attr S [(SI "HI") (HI "QI")])
216 (define_mode_attr s [(SI "hi") (HI "qi")])
217 (define_mode_attr m [(SI ".d") (HI ".w") (QI ".b")])
218 (define_mode_attr mm [(SI ".w") (HI ".b")])
219 (define_mode_attr nbitsm1 [(SI "
31") (HI "
15") (QI "
7")])
221 ;; For the sign_extend+zero_extend variants.
222 (define_code_iterator szext [sign_extend zero_extend])
223 (define_code_attr u [(sign_extend "") (zero_extend "u")])
224 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
226 ;; For the shift variants.
227 (define_code_iterator shift [ashiftrt lshiftrt ashift])
228 (define_code_iterator shiftrt [ashiftrt lshiftrt])
229 (define_code_attr shlr [(ashiftrt "ashr") (lshiftrt "lshr") (ashift "ashl")])
230 (define_code_attr slr [(ashiftrt "asr") (lshiftrt "lsr") (ashift "lsl")])
232 (define_code_iterator ncond [eq ne gtu ltu geu leu])
233 (define_code_iterator ocond [gt le])
234 (define_code_iterator rcond [lt ge])
235 (define_code_attr CC [(eq "eq") (ne "ne") (gt "gt") (gtu "hi") (lt "lt")
236 (ltu "lo") (ge "ge") (geu "hs") (le "le") (leu "ls")])
237 (define_code_attr rCC [(eq "ne") (ne "eq") (gt "le") (gtu "ls") (lt "ge")
238 (ltu "hs") (ge "lt") (geu "lo") (le "gt") (leu "hi")])
239 (define_code_attr oCC [(lt "mi") (ge "pl")])
240 (define_code_attr roCC [(lt "pl") (ge "mi")])
242 ;; Operand and operator predicates.
244 (include "predicates.md")
245 (include "constraints.md")
249 ;; No test insns with side-effect on the mem addressing.
251 ;; See note on cmp-insns with side-effects (or lack of them)
253 ;; Normal named test patterns from SI on.
255 (define_insn "*tstsi"
257 (compare (match_operand:SI
0 "nonimmediate_operand" "r,Q>,m")
261 if (which_alternative ==
0 && TARGET_V32)
265 [(set_attr "slottable" "yes,yes,no")])
267 (define_insn "*tst<mode>_cmp"
269 (compare (match_operand:BW
0 "nonimmediate_operand" "r,Q>,m")
271 "cris_cc0_user_requires_cmp (insn)"
276 [(set_attr "slottable" "no,yes,no")])
278 (define_insn "*tst<mode>_non_cmp"
280 (compare (match_operand:BW
0 "nonimmediate_operand" "r,Q>,m")
282 "!cris_cc0_user_requires_cmp (insn)"
287 [(set_attr "slottable" "yes,yes,no")
288 (set_attr "cc" "noov32,*,*")])
290 ;; It seems that the position of the sign-bit and the fact that
0.0 is
291 ;; all
0-bits would make "tstsf" a straight-forward implementation;
292 ;; either "test.d" it for positive/negative or "btstq
30,r" it for
295 ;; FIXME: Do that some time; check next_cc0_user to determine if
296 ;; zero or negative is tested for.
300 ;; We could optimize the sizes of the immediate operands for various
301 ;; cases, but that is not worth it because of the very little usage of
302 ;; DImode for anything else but a structure/block-mode. Just do the
303 ;; obvious stuff for the straight-forward constraint letters.
305 (define_insn "*cmpdi_non_v32"
307 (compare (match_operand:DI
0 "nonimmediate_operand" "rm,r,r,r,r,r,r,o")
308 (match_operand:DI
1 "general_operand" "M,Kc,I,P,n,r,o,r")))]
311 test.d %M0\;ax\;test.d %H0
312 cmpq %
1,%M0\;ax\;cmpq
0,%H0
313 cmpq %
1,%M0\;ax\;cmpq -
1,%H0
314 cmp%e1.%z1 %
1,%M0\;ax\;cmpq %H1,%H0
315 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
316 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
317 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
318 cmp.d %M0,%M1\;ax\;cmp.d %H0,%H1")
320 (define_insn "*cmpdi_v32"
322 (compare (match_operand:DI
0 "register_operand" "r,r,r,r,r")
323 (match_operand:DI
1 "nonmemory_operand" "Kc,I,P,n,r")))]
326 cmpq %
1,%M0\;ax\;cmpq
0,%H0
327 cmpq %
1,%M0\;ax\;cmpq -
1,%H0
328 cmp%e1.%z1 %
1,%M0\;ax\;cmpq %H1,%H0
329 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
330 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0")
332 ;; Note that compare insns with side effect addressing mode (e.g.):
334 ;; cmp.S [rx=ry+i],rz;
335 ;; cmp.S [%
3=%
1+%
2],%
0
337 ;; are *not* usable for gcc since the reloader *does not accept*
338 ;; cc0-changing insns with side-effects other than setting the condition
339 ;; codes. The reason is that the reload stage *may* cause another insn to
340 ;; be output after the main instruction, in turn invalidating cc0 for the
341 ;; insn using the test. (This does not apply to the CRIS case, since a
342 ;; reload for output -- move to memory -- does not change the condition
343 ;; code. Unfortunately we have no way to describe that at the moment. I
344 ;; think code would improve being in the order of one percent faster.
346 ;; We have cmps and cmpu (compare reg w. sign/zero extended mem).
347 ;; These are mostly useful for compares in SImode, using
8 or
16-bit
348 ;; constants, but sometimes gcc will find its way to use it for other
349 ;; (memory) operands. Avoid side-effect patterns, though (see above).
351 (define_insn "*cmp_ext<mode>"
354 (match_operand:SI
0 "register_operand" "r,r")
355 (match_operator:SI
2 "cris_extend_operator"
356 [(match_operand:BW
1 "memory_operand" "Q>,m")])))]
359 [(set_attr "slottable" "yes,no")])
361 ;; Swap operands; it seems the canonical look (if any) is not enforced.
363 ;; FIXME: Investigate that.
365 (define_insn "*cmp_swapext<mode>"
368 (match_operator:SI
2 "cris_extend_operator"
369 [(match_operand:BW
0 "memory_operand" "Q>,m")])
370 (match_operand:SI
1 "register_operand" "r,r")))]
373 [(set_attr "slottable" "yes,no")
374 (set_attr "cc" "rev")])
376 ;; The "normal" compare patterns, from SI on. Special-cases with zero
377 ;; are covered above.
379 (define_insn "*cmpsi"
382 (match_operand:SI
0 "nonimmediate_operand" "r,r,r, Q>,r,r,m")
383 (match_operand:SI
1 "general_operand" "I,r,Q>,r, P,g,r")))]
393 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")
394 (set_attr "cc" "normal,normal,normal,rev,normal,normal,rev")])
396 (define_insn "*cmp<mode>"
398 (compare (match_operand:BW
0 "nonimmediate_operand" "r,r, Q>,r,m")
399 (match_operand:BW
1 "general_operand" "r,Q>,r, g,r")))]
407 [(set_attr "slottable" "yes,yes,yes,no,no")
408 (set_attr "cc" "normal,normal,rev,normal,rev")])
410 ;; Pattern matching the BTST insn.
411 ;; It is useful for "if (i & val)" constructs, where val is an exact
412 ;; power of
2, or if val +
1 is a power of two, where we check for a bunch
413 ;; of zeros starting at bit
0).
415 ;; SImode. This mode is the only one needed, since gcc automatically
416 ;; extends subregs for lower-size modes. FIXME: Add testcase.
421 (match_operand:SI
0 "nonmemory_operand" "r, r,r, r,r, r,Kp")
422 (match_operand:SI
1 "const_int_operand" "Kc,n,Kc,n,Kc,n,n")
423 (match_operand:SI
2 "nonmemory_operand" "M, M,Kc,n,r, r,r"))
425 ;; Either it is a single bit, or consecutive ones starting at
0.
426 ;; The btst ones depend on stuff in NOTICE_UPDATE_CC.
427 "CONST_INT_P (operands[
1])
428 && (operands[
1] == const1_rtx || operands[
2] == const0_rtx)
429 && (REG_S_P (operands[
0])
430 || (operands[
1] == const1_rtx
431 && REG_S_P (operands[
2])
432 && CONST_INT_P (operands[
0])
433 && exact_log2 (INTVAL (operands[
0])) >=
0))
436 ;; The next-to-last "&&" condition above should be caught by some kind of
437 ;; canonicalization in gcc, but we can easily help with it here.
438 ;; It results from expressions of the type
439 ;; "power_of_2_value & (
1 << y)".
441 ;; Since there may be codes with tests in on bits (in constant position)
442 ;; beyond the size of a word, handle that by assuming those bits are
0.
443 ;; GCC should handle that, but it's a matter of easily-added belts while
444 ;; having suspenders.
454 [(set_attr "slottable" "yes")
455 (set_attr "cc" "noov32")])
459 ;; The whole mandatory movdi family is here; expander, "anonymous"
460 ;; recognizer and splitter. We're forced to have a movdi pattern,
461 ;; although GCC should be able to split it up itself. Normally it can,
462 ;; but if other insns have DI operands (as is the case here), reload
463 ;; must be able to generate or match a movdi. many testcases fail at
464 ;; -O3 or -fssa if we don't have this. FIXME: Fix GCC... See
465 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/
2000-
04/msg00104.html>.
466 ;; However, a patch from Richard Kenner (similar to the cause of
467 ;; discussion at the URL above), indicates otherwise. See
468 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/
2000-
04/msg00554.html>.
469 ;; The truth has IMO is not been decided yet, so check from time to
470 ;; time by disabling the movdi patterns.
472 ;; To appease testcase gcc.c-torture/execute/
920501-
2.c (and others) at
473 ;; -O0, we need a movdi as a temporary measure. Here's how things fail:
474 ;; A cmpdi RTX needs reloading (global):
475 ;; (insn
185 326 186 (set (cc0)
476 ;; (compare (mem/f:DI (reg/v:SI
22)
0)
477 ;; (const_int
1 [
0x1])))
4 {cmpdi} (nil)
479 ;; Now, reg
22 is reloaded for input address, and the mem is also moved
480 ;; out of the instruction (into a register), since one of the operands
481 ;; must be a register. Reg
22 is reloaded (into reg
10), and the mem is
482 ;; moved out and synthesized in SImode parts (reg
9, reg
10 - should be ok
483 ;; wrt. overlap). The bad things happen with the synthesis in
484 ;; emit_move_insn_1; the location where to substitute reg
10 is lost into
485 ;; two new RTX:es, both still having reg
22. Later on, the left-over reg
486 ;;
22 is recognized to have an equivalent in memory which is substituted
487 ;; straight in, and we end up with an unrecognizable insn:
488 ;; (insn
325 324 326 (set (reg:SI
9 r9)
489 ;; (mem/f:SI (mem:SI (plus:SI (reg:SI
8 r8)
490 ;; (const_int -
84 [
0xffffffac]))
0)
0)) -
1 (nil)
492 ;; which is the first part of the reloaded synthesized "movdi".
493 ;; The right thing would be to add equivalent replacement locations for
494 ;; insn with pseudos that need more reloading. The question is where.
496 (define_expand "movdi"
497 [(set (match_operand:DI
0 "nonimmediate_operand" "")
498 (match_operand:DI
1 "general_operand" ""))]
501 if (MEM_P (operands[
0])
502 && operands[
1] != const0_rtx
503 && (!TARGET_V32 || (!REG_P (operands[
1]) && can_create_pseudo_p ())))
504 operands[
1] = copy_to_mode_reg (DImode, operands[
1]);
506 /* Some other ports (as of
2001-
09-
10 for example mcore and romp) also
507 prefer to split up constants early, like this. The testcase in
508 gcc.c-torture/execute/
961213-
1.c shows that CSE2 gets confused by the
509 resulting subreg sets when using the construct from mcore (as of FSF
510 CVS, version -r
1.5), and it believes that the high part (the last one
511 emitted) is the final value. */
512 if ((CONST_INT_P (operands[
1]) || GET_CODE (operands[
1]) == CONST_DOUBLE)
513 && ! reload_completed
514 && ! reload_in_progress)
517 rtx op0 = operands[
0];
518 rtx op1 = operands[
1];
521 emit_move_insn (operand_subword (op0,
0,
1, DImode),
522 operand_subword (op1,
0,
1, DImode));
523 emit_move_insn (operand_subword (op0,
1,
1, DImode),
524 operand_subword (op1,
1,
1, DImode));
525 insns = get_insns ();
533 (define_insn_and_split "*movdi_insn_non_v32"
534 [(set (match_operand:DI
0 "nonimmediate_operand" "=r,rx,m")
535 (match_operand:DI
1 "general_operand" "rx,g,rxM"))]
536 "(register_operand (operands[
0], DImode)
537 || register_operand (operands[
1], DImode)
538 || operands[
1] == const0_rtx)
541 "&& reload_completed"
543 "operands[
2] = cris_split_movdx (operands);")
545 ;; Overlapping (but non-identical) source memory address and destination
546 ;; register would be a compiler bug, so we don't have to specify that.
547 (define_insn "*movdi_v32"
549 (match_operand:DI
0 "nonimmediate_operand" "=r,rx,&r,>, m,r,x,m")
550 (match_operand:DI
1 "general_operand" "rxi,r>,m, rx,r,m,m,x"))]
553 switch (which_alternative)
555 /* FIXME:
1) Use autoincrement where possible.
2) Have peephole2,
556 particularly for cases where the address register is dead. */
558 if (REGNO (operands[
0]) == REGNO (XEXP (operands[
1],
0)))
559 return "addq
4,%L1\;move.d %
1,%H0\;subq
4,%L1\;move.d %
1,%M0";
560 gcc_assert (REGNO (operands[
0]) +
1 == REGNO (XEXP (operands[
1],
0)));
561 return "move.d [%L1+],%M0\;move.d [%L1],%H0";
563 /* We could do away with the addq if we knew the address-register
564 isn't ACR. If we knew the address-register is dead, we could do
565 away with the subq too. */
566 return "move.d [%L1],%M0\;addq
4,%L1\;move.d [%L1],%H0\;subq
4,%L1";
568 return "move.d %M1,[%L0]\;addq
4,%L0\;move.d %H1,[%L0]\;subq
4,%L0";
570 return "move [%L1],%M0\;addq
4,%L1\;move [%L1],%H0\;subq
4,%L1";
572 return "move %M1,[%L0]\;addq
4,%L0\;move %H1,[%L0]\;subq
4,%L0";
578 ;; The non-split cases clobber cc0 because of their adds and subs.
579 ;; Beware that NOTICE_UPDATE_CC is called before the forced split happens.
580 [(set_attr "cc" "*,*,clobber,*,clobber,clobber,*,*")])
582 ;; Much like "*movdi_insn_non_v32". Overlapping registers and constants
583 ;; is handled so much better in cris_split_movdx.
585 [(set (match_operand:DI
0 "nonimmediate_operand" "")
586 (match_operand:DI
1 "general_operand" ""))]
589 && (!MEM_P (operands[
0]) || !REG_P (XEXP (operands[
0],
0)))
590 && (!MEM_P (operands[
1]) || !REG_P (XEXP (operands[
1],
0)))"
592 "operands[
2] = cris_split_movdx (operands);")
594 ;; Side-effect patterns for move.S1 [rx=ry+rx.S2],rw
595 ;; and move.S1 [rx=ry+i],rz
596 ;; Then movs.S1 and movu.S1 for both modes.
598 ;; move.S1 [rx=ry+rz.S],rw avoiding when rx is ry, or rw is rx
599 ;; FIXME: These could have anonymous mode for operand
0.
600 ;; FIXME: Special registers' alternatives too.
602 (define_insn "*mov_side<mode>_biap"
603 [(set (match_operand:BW
0 "register_operand" "=r,r")
605 (mult:SI (match_operand:SI
1 "register_operand" "r,r")
606 (match_operand:SI
2 "const_int_operand" "n,n"))
607 (match_operand:SI
3 "register_operand" "r,r"))))
608 (set (match_operand:SI
4 "register_operand" "=*
3,r")
609 (plus:SI (mult:SI (match_dup
1)
612 "cris_side_effect_mode_ok (MULT, operands,
4,
3,
1,
2,
0)"
615 move<m> [%
4=%
3+%
1%T2],%
0")
617 (define_insn "*mov_sidesisf_biap"
618 [(set (match_operand
0 "register_operand" "=r,r,x,x")
620 (mult:SI (match_operand:SI
1 "register_operand" "r,r,r,r")
621 (match_operand:SI
2 "const_int_operand" "n,n,n,n"))
622 (match_operand:SI
3 "register_operand" "r,r,r,r"))))
623 (set (match_operand:SI
4 "register_operand" "=*
3,r,*
3,r")
624 (plus:SI (mult:SI (match_dup
1)
627 "GET_MODE_SIZE (GET_MODE (operands[
0])) == UNITS_PER_WORD
628 && cris_side_effect_mode_ok (MULT, operands,
4,
3,
1,
2,
0)"
631 move.%s0 [%
4=%
3+%
1%T2],%
0
633 move [%
4=%
3+%
1%T2],%
0")
635 ;; move.S1 [rx=ry+i],rz
636 ;; avoiding move.S1 [ry=ry+i],rz
637 ;; and move.S1 [rz=ry+i],rz
638 ;; Note that "i" is allowed to be a register.
640 (define_insn "*mov_side<mode>"
641 [(set (match_operand:BW
0 "register_operand" "=r,r,r,r,r")
643 (plus:SI (match_operand:SI
1 "cris_bdap_operand" "%r,r,r,R,R")
644 (match_operand:SI
2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r"))))
645 (set (match_operand:SI
3 "register_operand" "=*
1,r,r,*
2,r")
646 (plus:SI (match_dup
1)
648 "cris_side_effect_mode_ok (PLUS, operands,
3,
1,
2, -
1,
0)"
650 if ((which_alternative ==
0 || which_alternative ==
3)
651 && (!CONST_INT_P (operands[
2])
652 || INTVAL (operands[
2]) >
127
653 || INTVAL (operands[
2]) < -
128
654 || satisfies_constraint_N (operands[
2])
655 || satisfies_constraint_J (operands[
2])))
657 if (which_alternative ==
4)
658 return "move<m> [%
3=%
2%S1],%
0";
659 return "move<m> [%
3=%
1%S2],%
0";
662 (define_insn "*mov_sidesisf"
663 [(set (match_operand
0 "register_operand" "=r,r,r,x,x,x,r,r,x,x")
666 (match_operand:SI
1 "cris_bdap_operand" "%r,r,r,r,r,r,R,R,R,R")
667 (match_operand:SI
2 "cris_bdap_operand" "r>Rn,r,>Rn,r>Rn,r,>Rn,r,r,r,r"))))
668 (set (match_operand:SI
3 "register_operand" "=*
1,r,r,*
1,r,r,*
2,r,*
2,r")
669 (plus:SI (match_dup
1)
671 "GET_MODE_SIZE (GET_MODE (operands[
0])) == UNITS_PER_WORD
672 && cris_side_effect_mode_ok (PLUS, operands,
3,
1,
2, -
1,
0)"
674 if ((which_alternative ==
0
675 || which_alternative ==
3
676 || which_alternative ==
6
677 || which_alternative ==
8)
678 && (!CONST_INT_P (operands[
2])
679 || INTVAL (operands[
2]) >
127
680 || INTVAL (operands[
2]) < -
128
681 || satisfies_constraint_N (operands[
2])
682 || satisfies_constraint_J (operands[
2])))
684 if (which_alternative <
3)
685 return "move.%s0 [%
3=%
1%S2],%
0";
686 if (which_alternative ==
7)
687 return "move.%s0 [%
3=%
2%S1],%
0";
688 if (which_alternative ==
9)
689 return "move [%
3=%
2%S1],%
0";
690 return "move [%
3=%
1%S2],%
0";
693 ;; Other way around; move to memory.
695 ;; Note that the condition (which for side-effect patterns is usually a
696 ;; call to cris_side_effect_mode_ok), isn't consulted for register
697 ;; allocation preferences -- constraints is the method for that. The
698 ;; drawback is that we can't exclude register allocation to cause
699 ;; "move.s rw,[rx=ry+rz.S]" when rw==rx without also excluding rx==ry or
700 ;; rx==rz if we use an earlyclobber modifier for the constraint for rx.
701 ;; Instead of that, we recognize and split the cases where dangerous
702 ;; register combinations are spotted: where a register is set in the
703 ;; side-effect, and used in the main insn. We don't handle the case where
704 ;; the set in the main insn overlaps the set in the side-effect; that case
705 ;; must be handled in gcc. We handle just the case where the set in the
706 ;; side-effect overlaps the input operand of the main insn (i.e. just
710 ;; move.s rz,[ry=rx+rw.S]
712 (define_insn "*mov_side<mode>_biap_mem"
713 [(set (mem:BW (plus:SI
714 (mult:SI (match_operand:SI
0 "register_operand" "r,r,r")
715 (match_operand:SI
1 "const_int_operand" "n,n,n"))
716 (match_operand:SI
2 "register_operand" "r,r,r")))
717 (match_operand:BW
3 "register_operand" "r,r,r"))
718 (set (match_operand:SI
4 "register_operand" "=*
2,!
3,r")
719 (plus:SI (mult:SI (match_dup
0)
722 "cris_side_effect_mode_ok (MULT, operands,
4,
2,
0,
1,
3)"
726 move<m> %
3,[%
4=%
2+%
0%T1]")
728 (define_insn "*mov_sidesisf_biap_mem"
730 (mult:SI (match_operand:SI
0 "register_operand" "r,r,r,r,r,r")
731 (match_operand:SI
1 "const_int_operand" "n,n,n,n,n,n"))
732 (match_operand:SI
2 "register_operand" "r,r,r,r,r,r")))
733 (match_operand
3 "register_operand" "r,r,r,x,x,x"))
734 (set (match_operand:SI
4 "register_operand" "=*
2,!
3,r,*
2,!
3,r")
735 (plus:SI (mult:SI (match_dup
0)
738 "GET_MODE_SIZE (GET_MODE (operands[
3])) == UNITS_PER_WORD
739 && cris_side_effect_mode_ok (MULT, operands,
4,
2,
0,
1,
3)"
743 move.%s3 %
3,[%
4=%
2+%
0%T1]
746 move %
3,[%
4=%
2+%
0%T1]")
748 ;; Split for the case above where we're out of luck with register
749 ;; allocation (again, the condition isn't checked for that), and we end up
750 ;; with the set in the side-effect getting the same register as the input
755 [(set (match_operator
758 (mult:SI (match_operand:SI
0 "register_operand" "")
759 (match_operand:SI
1 "const_int_operand" ""))
760 (match_operand:SI
2 "register_operand" ""))])
761 (match_operand
3 "register_operand" ""))
762 (set (match_operand:SI
4 "register_operand" "")
763 (plus:SI (mult:SI (match_dup
0)
766 "reload_completed && reg_overlap_mentioned_p (operands[
4], operands[
3])"
767 [(set (match_dup
5) (match_dup
3))
768 (set (match_dup
4) (match_dup
2))
770 (plus:SI (mult:SI (match_dup
0)
774 = replace_equiv_address (operands[
6],
775 gen_rtx_PLUS (SImode,
776 gen_rtx_MULT (SImode,
781 ;; move.s rx,[ry=rz+i]
782 ;; FIXME: These could have anonymous mode for operand
2.
786 (define_insn "*mov_side<mode>_mem"
788 (plus:SI (match_operand:SI
0 "cris_bdap_operand" "%r,r,r,r,R,R,R")
789 (match_operand:SI
1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn,r,r,r")))
790 (match_operand:BW
2 "register_operand" "r,r,r,r,r,r,r"))
791 (set (match_operand:SI
3 "register_operand" "=*
0,!*
2,r,r,*
1,!*
2,r")
792 (plus:SI (match_dup
0)
794 "cris_side_effect_mode_ok (PLUS, operands,
3,
0,
1, -
1,
2)"
796 if ((which_alternative ==
0 || which_alternative ==
4)
797 && (!CONST_INT_P (operands[
1])
798 || INTVAL (operands[
1]) >
127
799 || INTVAL (operands[
1]) < -
128
800 || satisfies_constraint_N (operands[
1])
801 || satisfies_constraint_J (operands[
1])))
803 if (which_alternative ==
1 || which_alternative ==
5)
805 if (which_alternative ==
6)
806 return "move.%s2 %
2,[%
3=%
1%S0]";
807 return "move<m> %
2,[%
3=%
0%S1]";
812 (define_insn "*mov_sidesisf_mem"
816 0 "cris_bdap_operand"
817 "%r, r, r,r, r, r,r, R,R, R,R, R")
819 1 "cris_bdap_operand"
820 "r>Rn,r>Rn,r,>Rn,r>Rn,r,>Rn,r,r, r,r, r")))
821 (match_operand
2 "register_operand"
822 "r, r, r,r, x, x,x, r,r, r,x, x"))
823 (set (match_operand:SI
3 "register_operand"
824 "=*
0,!
2, r,r, *
0, r,r, *
1,!*
2,r,*
1,r")
825 (plus:SI (match_dup
0)
827 "GET_MODE_SIZE (GET_MODE (operands[
2])) == UNITS_PER_WORD
828 && cris_side_effect_mode_ok (PLUS, operands,
3,
0,
1, -
1,
2)"
830 if ((which_alternative ==
0 || which_alternative ==
4)
831 && (!CONST_INT_P (operands[
1])
832 || INTVAL (operands[
1]) >
127
833 || INTVAL (operands[
1]) < -
128
834 || satisfies_constraint_N (operands[
1])
835 || satisfies_constraint_J (operands[
1])))
837 if (which_alternative ==
1
838 || which_alternative ==
7
839 || which_alternative ==
8
840 || which_alternative ==
10)
842 if (which_alternative <
4)
843 return "move.%s2 %
2,[%
3=%
0%S1]";
844 if (which_alternative ==
9)
845 return "move.%s2 %
2,[%
3=%
1%S0]";
846 if (which_alternative ==
11)
847 return "move %
2,[%
3=%
1%S0]";
848 return "move %
2,[%
3=%
0%S1]";
851 ;; Like the biap case, a split where the set in the side-effect gets the
852 ;; same register as the input register to the main insn, since the
853 ;; condition isn't checked at register allocation.
857 [(set (match_operator
860 (match_operand:SI
0 "cris_bdap_operand" "")
861 (match_operand:SI
1 "cris_bdap_operand" ""))])
862 (match_operand
2 "register_operand" ""))
863 (set (match_operand:SI
3 "register_operand" "")
864 (plus:SI (match_dup
0) (match_dup
1)))])]
865 "reload_completed && reg_overlap_mentioned_p (operands[
3], operands[
2])"
866 [(set (match_dup
4) (match_dup
2))
867 (set (match_dup
3) (match_dup
0))
868 (set (match_dup
3) (plus:SI (match_dup
3) (match_dup
1)))]
871 ;; Clear memory side-effect patterns. It is hard to get to the mode if
872 ;; the MEM was anonymous, so there will be one for each mode.
874 ;; clear.[bwd] [ry=rx+rw.s2]
876 (define_insn "*clear_side<mode>_biap"
877 [(set (mem:BWD (plus:SI
878 (mult:SI (match_operand:SI
0 "register_operand" "r,r")
879 (match_operand:SI
1 "const_int_operand" "n,n"))
880 (match_operand:SI
2 "register_operand" "r,r")))
882 (set (match_operand:SI
3 "register_operand" "=*
2,r")
883 (plus:SI (mult:SI (match_dup
0)
886 "cris_side_effect_mode_ok (MULT, operands,
3,
2,
0,
1, -
1)"
889 clear<m> [%
3=%
2+%
0%T1]")
891 ;; clear.[bwd] [ry=rz+i]
893 (define_insn "*clear_side<mode>"
895 (plus:SI (match_operand:SI
0 "cris_bdap_operand" "%r,r,r,R,R")
896 (match_operand:SI
1 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))
898 (set (match_operand:SI
2 "register_operand" "=*
0,r,r,*
1,r")
899 (plus:SI (match_dup
0)
901 "cris_side_effect_mode_ok (PLUS, operands,
2,
0,
1, -
1, -
1)"
903 if ((which_alternative ==
0 || which_alternative ==
3)
904 && (!CONST_INT_P (operands[
1])
905 || INTVAL (operands[
1]) >
127
906 || INTVAL (operands[
1]) < -
128
907 || satisfies_constraint_N (operands[
1])
908 || satisfies_constraint_J (operands[
1])))
910 if (which_alternative ==
4)
911 return "clear<m> [%
2=%
1%S0]";
912 return "clear<m> [%
2=%
0%S1]";
915 ;; Normal move patterns from SI on.
917 (define_expand "movsi"
919 (match_operand:SI
0 "nonimmediate_operand" "")
920 (match_operand:SI
1 "cris_general_operand_or_symbol" ""))]
923 /* If the output goes to a MEM, make sure we have zero or a register as
925 if (MEM_P (operands[
0])
926 && ! REG_S_P (operands[
1])
927 && operands[
1] != const0_rtx
928 && can_create_pseudo_p ())
929 operands[
1] = force_reg (SImode, operands[
1]);
931 /* If we're generating PIC and have an incoming symbol, validize it to a
932 general operand or something that will match a special pattern.
934 FIXME: Do we *have* to recognize anything that would normally be a
935 valid symbol? Can we exclude global PIC addresses with an added
938 && CONSTANT_ADDRESS_P (operands[
1])
939 && !cris_valid_pic_const (operands[
1], false))
941 enum cris_pic_symbol_type t = cris_pic_symbol_type_of (operands[
1]);
943 gcc_assert (t != cris_no_symbol);
945 if (! REG_S_P (operands[
0]))
947 /* We must have a register as destination for what we're about to
948 do, and for the patterns we generate. */
949 CRIS_ASSERT (can_create_pseudo_p ());
950 operands[
1] = force_reg (SImode, operands[
1]);
954 /* FIXME: add a REG_EQUAL (or is it REG_EQUIV) note to the
955 destination register for the symbol. It might not be
956 worth it. Measure. */
957 crtl->uses_pic_offset_table =
1;
958 if (t == cris_rel_symbol)
960 /* Change a "move.d sym(+offs),rN" into (allocate register rM)
962 "move.d (const (plus (unspec [sym]
963 CRIS_UNSPEC_GOTREL) offs)),rM" "add.d rPIC,rM,rN"
965 "move.d (const (plus (unspec [sym]
966 CRIS_UNSPEC_PCREL) offs)),rN". */
967 rtx tem, rm, rn = operands[
0];
968 rtx sym = GET_CODE (operands[
1]) != CONST
969 ? operands[
1] : get_related_value (operands[
1]);
970 HOST_WIDE_INT offs = get_integer_term (operands[
1]);
972 gcc_assert (can_create_pseudo_p ());
976 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (
1, sym),
979 tem = plus_constant (Pmode, tem, offs);
981 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
985 /* We still uses GOT-relative addressing for
987 crtl->uses_pic_offset_table =
1;
988 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (
1, sym),
991 tem = plus_constant (Pmode, tem, offs);
992 rm = gen_reg_rtx (Pmode);
993 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
994 if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx,
995 rn,
0, OPTAB_LIB_WIDEN) != rn)
996 internal_error ("expand_binop failed in movsi gotrel");
1000 else if (t == cris_got_symbol)
1002 /* Change a "move.d sym,rN" into (allocate register rM, rO)
1003 "move.d (const (unspec [sym] CRIS_UNSPEC_GOTREAD)),rM"
1004 "add.d rPIC,rM,rO", "move.d [rO],rN" with
1005 the memory access marked as read-only. */
1006 rtx tem, mem, rm, ro, rn = operands[
0];
1007 gcc_assert (can_create_pseudo_p ());
1008 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (
1, operands[
1]),
1009 CRIS_UNSPEC_GOTREAD);
1010 rm = gen_reg_rtx (Pmode);
1011 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
1012 ro = gen_reg_rtx (Pmode);
1013 if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx,
1014 ro,
0, OPTAB_LIB_WIDEN) != ro)
1015 internal_error ("expand_binop failed in movsi got");
1016 mem = gen_rtx_MEM (Pmode, ro);
1018 /* This MEM doesn't alias anything. Whether it
1019 aliases other same symbols is unimportant. */
1020 set_mem_alias_set (mem, new_alias_set ());
1021 MEM_NOTRAP_P (mem) =
1;
1023 /* We can set the GOT memory read of a non-called symbol
1024 to readonly, but not that of a call symbol, as those
1025 are subject to lazy evaluation and usually have the value
1026 changed from the first call to the second (but
1027 constant thereafter). */
1028 MEM_READONLY_P (mem) =
1;
1029 emit_move_insn (rn, mem);
1034 /* We get here when we have to change something that would
1035 be recognizable if it wasn't PIC. A
``sym'' is ok for
1036 PIC symbols both with and without a GOT entry. And
``sym
1037 + offset'' is ok for local symbols, so the only thing it
1038 could be, is a global symbol with an offset. Check and
1040 rtx reg = gen_reg_rtx (Pmode);
1041 rtx sym = get_related_value (operands[
1]);
1042 HOST_WIDE_INT offs = get_integer_term (operands[
1]);
1044 gcc_assert (can_create_pseudo_p ()
1045 && t == cris_got_symbol_needing_fixup
1046 && sym != NULL_RTX && offs !=
0);
1048 emit_move_insn (reg, sym);
1049 if (expand_binop (SImode, add_optab, reg,
1050 GEN_INT (offs), operands[
0],
0,
1051 OPTAB_LIB_WIDEN) != operands[
0])
1052 internal_error ("expand_binop failed in movsi got+offs");
1059 (define_insn "*movsi_got_load"
1060 [(set (reg:SI CRIS_GOT_REGNUM) (unspec:SI [(const_int
0)] CRIS_UNSPEC_GOT))]
1064 ? "lapc _GLOBAL_OFFSET_TABLE_,%:"
1065 : "move.d $pc,%:\;sub.d .:GOTOFF,%:";
1067 [(set_attr "cc" "clobber")])
1069 (define_insn "*movsi_internal"
1071 (match_operand:SI
0 "nonimmediate_operand"
1072 "=r,r, r,Q>,r,Q>,g,r,r, r,g,rQ>,x, m,x")
1073 (match_operand:SI
1 "cris_general_operand_or_pic_source"
1074 "r,Q>,M,M, I,r, M,n,!S,g,r,x, rQ>,x,gi"))]
1075 ;; Note that we prefer not to use the S alternative (if for some reason
1076 ;; it competes with others) above, but g matches S.
1079 /* Better to have c-switch here; it is worth it to optimize the size of
1080 move insns. The alternative would be to try to find more constraint
1081 letters. FIXME: Check again. It seems this could shrink a bit. */
1082 switch (which_alternative)
1088 && (GET_CODE (operands[
1]) == SYMBOL_REF
1089 || GET_CODE (operands[
1]) == LABEL_REF
1090 || GET_CODE (operands[
1]) == CONST))
1092 /* FIXME: Express this through (set_attr cc none) instead,
1093 since we can't express the
``none'' at this point. FIXME:
1094 Use lapc for everything except const_int and when next cc0
1095 user would want the flag setting. */
1097 return "lapc %
1,%
0";
1100 && GET_CODE (operands[
1]) == CONST
1101 && GET_CODE (XEXP (operands[
1],
0)) == UNSPEC
1102 && XINT (XEXP (operands[
1],
0),
1) == CRIS_UNSPEC_GOTREAD)
1103 return "movu.w %
1,%
0";
1110 return "move.d %
1,%
0";
1116 return "move %d1,%
0";
1121 return "clear.d %
0";
1123 /* Constants -
32.
.31 except
0. */
1125 return "moveq %
1,%
0";
1127 /* We can win a little on constants -
32768..-
33,
32.
.65535. */
1129 if (INTVAL (operands[
1]) >
0 && INTVAL (operands[
1]) <
65536)
1131 if (INTVAL (operands[
1]) <
256)
1132 return "movu.b %
1,%
0";
1133 return "movu.w %
1,%
0";
1135 else if (INTVAL (operands[
1]) >= -
32768 && INTVAL (operands[
1]) <
32768)
1137 if (INTVAL (operands[
1]) >= -
128 && INTVAL (operands[
1]) <
128)
1138 return "movs.b %
1,%
0";
1139 return "movs.w %
1,%
0";
1141 return "move.d %
1,%
0";
1145 rtx tem = operands[
1];
1146 gcc_assert (GET_CODE (tem) == CONST);
1147 tem = XEXP (tem,
0);
1148 if (GET_CODE (tem) == PLUS
1149 && GET_CODE (XEXP (tem,
0)) == UNSPEC
1150 && (XINT (XEXP (tem,
0),
1) == CRIS_UNSPEC_GOTREL
1151 || XINT (XEXP (tem,
0),
1) == CRIS_UNSPEC_PCREL)
1152 && CONST_INT_P (XEXP (tem,
1)))
1153 tem = XEXP (tem,
0);
1154 gcc_assert (GET_CODE (tem) == UNSPEC);
1155 switch (XINT (tem,
1))
1157 case CRIS_UNSPEC_GOTREAD:
1158 case CRIS_UNSPEC_PLTGOTREAD:
1159 /* Using sign-extend mostly to be consistent with the
1160 indexed addressing mode. */
1162 return "movs.w %
1,%
0";
1163 return "move.d %
1,%
0";
1165 case CRIS_UNSPEC_GOTREL:
1166 case CRIS_UNSPEC_PLT_GOTREL:
1167 gcc_assert (!TARGET_V32);
1168 return "move.d %
1,%
0";
1170 case CRIS_UNSPEC_PCREL:
1171 case CRIS_UNSPEC_PLT_PCREL:
1172 gcc_assert (TARGET_V32);
1173 return "lapc %
1,%
0";
1180 return "BOGUS: %
1 to %
0";
1183 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,no,yes,yes,no,no")
1184 (set_attr "cc" "*,*,*,*,*,*,*,*,*,*,*,none,none,none,none")])
1186 ;; Extend operations with side-effect from mem to register, using
1187 ;; MOVS/MOVU. These are from mem to register only.
1193 ;; FIXME: Can we omit extend to HImode, since GCC should truncate for
1194 ;; HImode by itself? Perhaps use only anonymous modes?
1196 (define_insn "*ext_sideqihi_biap"
1197 [(set (match_operand:HI
0 "register_operand" "=r,r")
1199 5 "cris_extend_operator"
1201 (mult:SI (match_operand:SI
1 "register_operand" "r,r")
1202 (match_operand:SI
2 "const_int_operand" "n,n"))
1203 (match_operand:SI
3 "register_operand" "r,r")))]))
1204 (set (match_operand:SI
4 "register_operand" "=*
3,r")
1205 (plus:SI (mult:SI (match_dup
1)
1208 "cris_side_effect_mode_ok (MULT, operands,
4,
3,
1,
2,
0)"
1211 mov%e5.%m5 [%
4=%
3+%
1%T2],%
0")
1213 (define_insn "*ext_side<mode>si_biap"
1214 [(set (match_operand:SI
0 "register_operand" "=r,r")
1216 5 "cris_extend_operator"
1218 (mult:SI (match_operand:SI
1 "register_operand" "r,r")
1219 (match_operand:SI
2 "const_int_operand" "n,n"))
1220 (match_operand:SI
3 "register_operand" "r,r")))]))
1221 (set (match_operand:SI
4 "register_operand" "=*
3,r")
1222 (plus:SI (mult:SI (match_dup
1)
1225 "cris_side_effect_mode_ok (MULT, operands,
4,
3,
1,
2,
0)"
1228 mov%e5<m> [%
4=%
3+%
1%T2],%
0")
1230 ;; Same but [rx=ry+i]
1234 (define_insn "*ext_sideqihi"
1235 [(set (match_operand:HI
0 "register_operand" "=r,r,r,r,r")
1237 4 "cris_extend_operator"
1239 (match_operand:SI
1 "cris_bdap_operand" "%r,r,r,R,R")
1240 (match_operand:SI
2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1241 (set (match_operand:SI
3 "register_operand" "=*
1,r,r,*
2,r")
1242 (plus:SI (match_dup
1)
1244 "cris_side_effect_mode_ok (PLUS, operands,
3,
1,
2, -
1,
0)"
1246 if ((which_alternative ==
0 || which_alternative ==
3)
1247 && (!CONST_INT_P (operands[
2])
1248 || INTVAL (operands[
2]) >
127
1249 || INTVAL (operands[
2]) < -
128
1250 || satisfies_constraint_N (operands[
2])
1251 || satisfies_constraint_J (operands[
2])))
1253 if (which_alternative ==
4)
1254 return "mov%e4.%m4 [%
3=%
2%S1],%
0";
1255 return "mov%e4.%m4 [%
3=%
1%S2],%
0";
1258 (define_insn "*ext_side<mode>si"
1259 [(set (match_operand:SI
0 "register_operand" "=r,r,r,r,r")
1261 4 "cris_extend_operator"
1263 (match_operand:SI
1 "cris_bdap_operand" "%r,r,r,R,R")
1264 (match_operand:SI
2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1265 (set (match_operand:SI
3 "register_operand" "=*
1,r,r,*
2,r")
1266 (plus:SI (match_dup
1)
1268 "cris_side_effect_mode_ok (PLUS, operands,
3,
1,
2, -
1,
0)"
1270 if ((which_alternative ==
0 || which_alternative ==
3)
1271 && (!CONST_INT_P (operands[
2])
1272 || INTVAL (operands[
2]) >
127
1273 || INTVAL (operands[
2]) < -
128
1274 || satisfies_constraint_N (operands[
2])
1275 || satisfies_constraint_J (operands[
2])))
1277 if (which_alternative ==
4)
1278 return "mov%e4<m> [%
3=%
2%S1],%
0";
1279 return "mov%e4<m> [%
3=%
1%S2],%
0";
1282 ;; FIXME: See movsi.
1284 (define_insn "movhi"
1286 (match_operand:HI
0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,r,r,r,g,g,r,r,x")
1287 (match_operand:HI
1 "general_operand" "r,Q>,M,M, I,r, L,O,n,M,r,g,x,r"))]
1290 switch (which_alternative)
1297 return "move.w %
1,%
0";
1300 return "move %
1,%
0";
1304 return "clear.w %
0";
1306 return "moveq %
1,%
0";
1309 if (INTVAL (operands[
1]) <
256 && INTVAL (operands[
1]) >= -
128)
1311 if (INTVAL (operands[
1]) >
0)
1312 return "movu.b %
1,%
0";
1313 return "movs.b %
1,%
0";
1315 return "move.w %
1,%
0";
1317 return "movEq %b1,%
0";
1319 return "BOGUS: %
1 to %
0";
1322 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,yes,no,no,no,no,yes,yes")
1323 (set_attr "cc" "*,*,none,none,*,none,*,clobber,*,none,none,*,none,none")])
1325 (define_insn "movstricthi"
1328 (match_operand:HI
0 "nonimmediate_operand" "+r,r, r,Q>,Q>,g,r,g"))
1329 (match_operand:HI
1 "general_operand" "r,Q>,M,M, r, M,g,r"))]
1340 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1342 (define_expand "reload_in<mode>"
1343 [(set (match_operand:BW
2 "register_operand" "=r")
1344 (match_operand:BW
1 "memory_operand" "m"))
1345 (set (match_operand:BW
0 "register_operand" "=x")
1350 (define_expand "reload_out<mode>"
1351 [(set (match_operand:BW
2 "register_operand" "=&r")
1352 (match_operand:BW
1 "register_operand" "x"))
1353 (set (match_operand:BW
0 "memory_operand" "=m")
1358 (define_insn "movqi"
1359 [(set (match_operand:QI
0 "nonimmediate_operand" "=r,Q>,r, r,Q>,r,g,g,r,r,r,x")
1360 (match_operand:QI
1 "general_operand" "r,r, Q>,M,M, I,M,r,O,g,x,r"))]
1375 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,yes,no,yes,yes")
1376 (set_attr "cc" "*,*,*,*,*,*,*,*,clobber,*,none,none")])
1378 (define_insn "movstrictqi"
1379 [(set (strict_low_part
1380 (match_operand:QI
0 "nonimmediate_operand" "+r,Q>,r, r,Q>,g,g,r"))
1381 (match_operand:QI
1 "general_operand" "r,r, Q>,M,M, M,r,g"))]
1392 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1394 ;; The valid "quick" bit-patterns are, except for
0.0, denormalized
1395 ;; values REALLY close to
0, and some NaN:s (I think; their exponent is
1396 ;; all ones); the worthwhile one is "
0.0".
1397 ;; It will use clear, so we know ALL types of immediate
0 never change cc.
1399 (define_insn "movsf"
1400 [(set (match_operand:SF
0 "nonimmediate_operand" "=r,Q>,r, r,Q>,g,g,r,r,x,Q>,m,x, x")
1401 (match_operand:SF
1 "general_operand" "r,r, Q>,G,G, G,r,g,x,r,x, x,Q>,g"))]
1418 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no,yes,yes,yes,no,yes,no")])
1420 ;; Movem patterns. Primarily for use in function prologue and epilogue.
1421 ;; The V32 variants have an ordering matching the expectations of the
1422 ;; standard names "load_multiple" and "store_multiple"; pre-v32 movem
1423 ;; store R0 in the highest memory location.
1425 (define_expand "load_multiple"
1426 [(match_operand:SI
0 "register_operand" "")
1427 (match_operand:SI
1 "memory_operand" "")
1428 (match_operand:SI
2 "const_int_operand" "")]
1433 /* Apparently the predicate isn't checked, so we need to do so
1434 manually. Once happened for libstdc++-v3 locale_facets.tcc. */
1435 if (!MEM_P (operands[
1]))
1438 indreg = XEXP (operands[
1],
0);
1440 if (GET_CODE (indreg) == POST_INC)
1441 indreg = XEXP (indreg,
0);
1443 || GET_CODE (operands[
2]) != CONST_INT
1444 || !REG_P (operands[
0])
1445 || REGNO (operands[
0]) !=
0
1446 || INTVAL (operands[
2]) > CRIS_SP_REGNUM
1447 || (int) REGNO (indreg) < INTVAL (operands[
2]))
1450 emit_insn (cris_gen_movem_load (operands[
1], operands[
2],
0));
1454 (define_expand "store_multiple"
1455 [(match_operand:SI
0 "memory_operand" "")
1456 (match_operand:SI
1 "register_operand" "")
1457 (match_operand:SI
2 "const_int_operand" "")]
1462 /* See load_multiple. */
1463 if (!MEM_P (operands[
0]))
1466 indreg = XEXP (operands[
0],
0);
1468 if (GET_CODE (indreg) == POST_INC)
1469 indreg = XEXP (indreg,
0);
1471 || GET_CODE (operands[
2]) != CONST_INT
1472 || !REG_P (operands[
1])
1473 || REGNO (operands[
1]) !=
0
1474 || INTVAL (operands[
2]) > CRIS_SP_REGNUM
1475 || (int) REGNO (indreg) < INTVAL (operands[
2]))
1478 cris_emit_movem_store (operands[
0], operands[
2],
0, false);
1482 (define_insn "*cris_load_multiple"
1483 [(match_parallel
0 "cris_load_multiple_op"
1484 [(set (match_operand:SI
1 "register_operand" "=r,r")
1485 (match_operand:SI
2 "memory_operand" "Q,m"))])]
1488 [(set_attr "cc" "none")
1489 (set_attr "slottable" "yes,no")
1490 ;; Not true, but setting the length to
0 causes return sequences (ret
1491 ;; movem) to have the cost they had when (return) included the movem
1492 ;; and reduces the performance penalty taken for needing to emit an
1493 ;; epilogue (in turn copied by bb-reorder) instead of return patterns.
1494 ;; FIXME: temporary change until all insn lengths are correctly
1495 ;; described. FIXME: have better target control over bb-reorder.
1496 (set_attr "length" "
0")])
1498 (define_insn "*cris_store_multiple"
1499 [(match_parallel
0 "cris_store_multiple_op"
1500 [(set (match_operand:SI
2 "memory_operand" "=Q,m")
1501 (match_operand:SI
1 "register_operand" "r,r"))])]
1504 [(set_attr "cc" "none")
1505 (set_attr "slottable" "yes,no")])
1508 ;; Sign- and zero-extend insns with standard names.
1509 ;; Those for integer source operand are ordered with the widest source
1514 (define_insn "extendsidi2"
1515 [(set (match_operand:DI
0 "register_operand" "=r")
1516 (sign_extend:DI (match_operand:SI
1 "general_operand" "g")))]
1518 "move.d %
1,%M0\;smi %H0\;neg.d %H0,%H0")
1520 (define_insn "extend<mode>di2"
1521 [(set (match_operand:DI
0 "register_operand" "=r")
1522 (sign_extend:DI (match_operand:BW
1 "general_operand" "g")))]
1524 "movs<m> %
1,%M0\;smi %H0\;neg.d %H0,%H0")
1526 (define_insn "extend<mode>si2"
1527 [(set (match_operand:SI
0 "register_operand" "=r,r,r")
1528 (sign_extend:SI (match_operand:BW
1 "general_operand" "r,Q>,g")))]
1531 [(set_attr "slottable" "yes,yes,no")])
1533 ;; To do a byte->word extension, extend to dword, except that the top half
1534 ;; of the register will be clobbered. FIXME: Perhaps this is not needed.
1536 (define_insn "extendqihi2"
1537 [(set (match_operand:HI
0 "register_operand" "=r,r,r")
1538 (sign_extend:HI (match_operand:QI
1 "general_operand" "r,Q>,g")))]
1541 [(set_attr "slottable" "yes,yes,no")])
1544 ;; Zero-extend. The DImode ones are synthesized by gcc, so we don't
1545 ;; specify them here.
1547 (define_insn "zero_extend<mode>si2"
1548 [(set (match_operand:SI
0 "register_operand" "=r,r,r")
1550 (match_operand:BW
1 "nonimmediate_operand" "r,Q>,m")))]
1553 [(set_attr "slottable" "yes,yes,no")])
1555 ;; Same comment as sign-extend QImode to HImode above applies.
1557 (define_insn "zero_extendqihi2"
1558 [(set (match_operand:HI
0 "register_operand" "=r,r,r")
1560 (match_operand:QI
1 "nonimmediate_operand" "r,Q>,m")))]
1563 [(set_attr "slottable" "yes,yes,no")])
1565 ;; All kinds of arithmetic and logical instructions.
1567 ;; First, anonymous patterns to match addressing modes with
1570 ;; op.S [rx=ry+I],rz; (add, sub, or, and, bound).
1574 (define_insn "*op_side<mode>_biap"
1575 [(set (match_operand:BWD
0 "register_operand" "=r,r")
1577 6 "cris_orthogonal_operator"
1578 [(match_operand:BWD
1 "register_operand" "
0,
0")
1580 (mult:SI (match_operand:SI
2 "register_operand" "r,r")
1581 (match_operand:SI
3 "const_int_operand" "n,n"))
1582 (match_operand:SI
4 "register_operand" "r,r")))]))
1583 (set (match_operand:SI
5 "register_operand" "=*
4,r")
1584 (plus:SI (mult:SI (match_dup
2)
1587 "cris_side_effect_mode_ok (MULT, operands,
5,
4,
2,
3,
0)"
1590 %x6<m> [%
5=%
4+%
2%T3],%
0")
1592 ;; [rx=ry+i] ([%
4=%
2+%
3])
1594 (define_insn "*op_side<mode>"
1595 [(set (match_operand:BWD
0 "register_operand" "=r,r,r,r,r")
1597 5 "cris_orthogonal_operator"
1598 [(match_operand:BWD
1 "register_operand" "
0,
0,
0,
0,
0")
1600 (match_operand:SI
2 "cris_bdap_operand" "%r,r,r,R,R")
1601 (match_operand:SI
3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1602 (set (match_operand:SI
4 "register_operand" "=*
2,r,r,*
3,r")
1603 (plus:SI (match_dup
2)
1605 "cris_side_effect_mode_ok (PLUS, operands,
4,
2,
3, -
1,
0)"
1607 if ((which_alternative ==
0 || which_alternative ==
3)
1608 && (!CONST_INT_P (operands[
3])
1609 || INTVAL (operands[
3]) >
127
1610 || INTVAL (operands[
3]) < -
128
1611 || satisfies_constraint_N (operands[
3])
1612 || satisfies_constraint_J (operands[
3])))
1614 if (which_alternative ==
4)
1615 return "%x5.%s0 [%
4=%
3%S2],%
0";
1616 return "%x5<m> [%
4=%
2%S3],%
0";
1619 ;; To match all cases for commutative operations we may have to have the
1620 ;; following pattern for add, or & and. I do not know really, but it does
1621 ;; not break anything.
1623 ;; FIXME: This really ought to be checked.
1625 ;; op.S [rx=ry+I],rz;
1629 (define_insn "*op_swap_side<mode>_biap"
1630 [(set (match_operand:BWD
0 "register_operand" "=r,r")
1632 6 "cris_commutative_orth_op"
1634 (mult:SI (match_operand:SI
2 "register_operand" "r,r")
1635 (match_operand:SI
3 "const_int_operand" "n,n"))
1636 (match_operand:SI
4 "register_operand" "r,r")))
1637 (match_operand:BWD
1 "register_operand" "
0,
0")]))
1638 (set (match_operand:SI
5 "register_operand" "=*
4,r")
1639 (plus:SI (mult:SI (match_dup
2)
1642 "cris_side_effect_mode_ok (MULT, operands,
5,
4,
2,
3,
0)"
1645 %x6<m> [%
5=%
4+%
2%T3],%
0")
1647 ;; [rx=ry+i] ([%
4=%
2+%
3])
1648 ;; FIXME: These could have anonymous mode for operand
0.
1652 (define_insn "*op_swap_side<mode>"
1653 [(set (match_operand:BWD
0 "register_operand" "=r,r,r,r,r")
1655 5 "cris_commutative_orth_op"
1657 (plus:SI (match_operand:SI
2 "cris_bdap_operand" "%r,r,r,R,R")
1658 (match_operand:SI
3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))
1659 (match_operand:BWD
1 "register_operand" "
0,
0,
0,
0,
0")]))
1660 (set (match_operand:SI
4 "register_operand" "=*
2,r,r,*
3,r")
1661 (plus:SI (match_dup
2)
1663 "cris_side_effect_mode_ok (PLUS, operands,
4,
2,
3, -
1,
0)"
1665 if ((which_alternative ==
0 || which_alternative ==
3)
1666 && (!CONST_INT_P (operands[
3])
1667 || INTVAL (operands[
3]) >
127
1668 || INTVAL (operands[
3]) < -
128
1669 || satisfies_constraint_N (operands[
3])
1670 || satisfies_constraint_J (operands[
3])))
1672 if (which_alternative ==
4)
1673 return "%x5<m> [%
4=%
3%S2],%
0";
1674 return "%x5<m> [%
4=%
2%S3],%
0";
1677 ;; Add operations, standard names.
1679 ;; Note that for the 'P' constraint, the high part can be -
1 or
0. We
1680 ;; output the insn through the 'A' output modifier as "adds.w" and "addq",
1682 (define_expand "adddi3"
1683 [(set (match_operand:DI
0 "register_operand")
1684 (plus:DI (match_operand:DI
1 "register_operand")
1685 (match_operand:DI
2 "general_operand")))]
1688 if (MEM_P (operands[
2]) && TARGET_V32)
1689 operands[
2] = force_reg (DImode, operands[
2]);
1692 (define_insn "*adddi3_non_v32"
1693 [(set (match_operand:DI
0 "register_operand" "=r,r,r,&r,&r")
1694 (plus:DI (match_operand:DI
1 "register_operand" "%
0,
0,
0,
0,r")
1695 (match_operand:DI
2 "general_operand" "J,N,P,g,!To")))]
1698 addq %
2,%M0\;ax\;addq
0,%H0
1699 subq %n2,%M0\;ax\;subq
0,%H0
1700 add%e2.%z2 %
2,%M0\;ax\;%A2 %H2,%H0
1701 add.d %M2,%M0\;ax\;add.d %H2,%H0
1702 add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0")
1704 ; It seems no use allowing a memory operand for this one, because we'd
1705 ; need a scratch register for incrementing the address.
1706 (define_insn "*adddi3_v32"
1707 [(set (match_operand:DI
0 "register_operand" "=r,r,r,r,r")
1708 (plus:DI (match_operand:DI
1 "register_operand" "%
0,
0,
0,
0,
0")
1709 (match_operand:DI
2 "nonmemory_operand" "J,N,P,r,n")))]
1712 addq %
2,%M0\;addc
0,%H0
1713 subq %n2,%M0\;ax\;subq
0,%H0
1714 add%e2.%z2 %
2,%M0\;addc %H2,%H0
1715 add.d %M2,%M0\;addc %H2,%H0
1716 add.d %M2,%M0\;addc %H2,%H0")
1718 (define_expand "add<mode>
3"
1719 [(set (match_operand:BWD
0 "register_operand")
1721 (match_operand:BWD
1 "register_operand")
1722 (match_operand:BWD
2 "general_operand")))]
1726 (define_insn "*addsi3_non_v32"
1727 [(set (match_operand:SI
0 "register_operand" "=r,r, r,r,r,r, r,r, r")
1729 (match_operand:SI
1 "register_operand" "%
0,
0,
0,
0,
0,
0,
0,r, r")
1730 (match_operand:SI
2 "general_operand" "r,Q>,J,N,n,!S,g,!To,
0")))]
1732 ;; The last constraint is due to that after reload, the '%' is not
1733 ;; honored, and canonicalization doesn't care about keeping the same
1734 ;; register as in destination. This will happen after insn splitting.
1735 ;; gcc <=
2.7.2. FIXME: Check for gcc-
2.9x
1739 switch (which_alternative)
1743 return "add.d %
2,%
0";
1745 return "addq %
2,%
0";
1747 return "subq %n2,%
0";
1749 /* 'Known value', but not in -
63.
.63.
1750 Check if addu/subu may be used. */
1751 if (INTVAL (operands[
2]) >
0)
1753 if (INTVAL (operands[
2]) <
256)
1754 return "addu.b %
2,%
0";
1755 if (INTVAL (operands[
2]) <
65536)
1756 return "addu.w %
2,%
0";
1760 if (INTVAL (operands[
2]) >= -
255)
1761 return "subu.b %n2,%
0";
1762 if (INTVAL (operands[
2]) >= -
65535)
1763 return "subu.w %n2,%
0";
1765 return "add.d %
2,%
0";
1768 rtx tem = operands[
2];
1769 gcc_assert (GET_CODE (tem) == CONST);
1770 tem = XEXP (tem,
0);
1771 if (GET_CODE (tem) == PLUS
1772 && GET_CODE (XEXP (tem,
0)) == UNSPEC
1773 /* We don't allow CRIS_UNSPEC_PCREL here; we can't have a
1774 pc-relative operand in an add insn. */
1775 && XINT (XEXP (tem,
0),
1) == CRIS_UNSPEC_GOTREL
1776 && CONST_INT_P (XEXP (tem,
1)))
1777 tem = XEXP (tem,
0);
1778 gcc_assert (GET_CODE (tem) == UNSPEC);
1779 switch (XINT (tem,
1))
1781 case CRIS_UNSPEC_GOTREAD:
1782 case CRIS_UNSPEC_PLTGOTREAD:
1783 /* Using sign-extend mostly to be consistent with the
1784 indexed addressing mode. */
1786 return "adds.w %
2,%
0";
1787 return "add.d %
2,%
0";
1789 case CRIS_UNSPEC_PLT_GOTREL:
1790 case CRIS_UNSPEC_GOTREL:
1791 return "add.d %
2,%
0";
1797 return "add%u2 %
2,%
0";
1799 return "add.d %
2,%
1,%
0";
1801 return "add.d %
1,%
0";
1803 return "BOGUS addsi %
2+%
1 to %
0";
1806 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no,yes")])
1808 ; FIXME: Check what's best: having the three-operand ACR alternative
1809 ; before or after the corresponding-operand2 alternative. Check for
1810 ; *all* insns. FIXME: constant constraint letter for -
128.
.127.
1811 (define_insn "*addsi3_v32"
1812 [(set (match_operand:SI
0 "register_operand" "=r,!a,r,!a, r,r,!a,r,!a,r,r,r,!a")
1814 (match_operand:SI
1 "register_operand" "%
0,r,
0, r,
0,
0,r,
0,r,
0,
0,
0,r")
1815 (match_operand:SI
2 "general_operand" "r, r, Q>,Q>,J,N,NJ,L,L, P,n,g,g")))]
1831 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,no,no,no,no,no,no")
1832 (set_attr "cc" "*,none,*,none,*,*,none,*,none,*,*,*,none")])
1834 (define_insn "*addhi3_non_v32"
1835 [(set (match_operand:HI
0 "register_operand" "=r,r, r,r,r,r")
1836 (plus:HI (match_operand:HI
1 "register_operand" "%
0,
0,
0,
0,
0,r")
1837 (match_operand:HI
2 "general_operand" "r,Q>,J,N,g,!To")))]
1846 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1847 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1849 (define_insn "*addhi3_v32"
1850 [(set (match_operand:HI
0 "register_operand" "=r, !a,r,!a, r,r,!a,r,!a")
1852 (match_operand:HI
1 "register_operand" "%
0,r,
0, r,
0,
0,r,
0,r")
1853 (match_operand:HI
2 "general_operand" "r, r, Q>,Q>,J,N,NJ,g,g")))]
1865 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,no,no")
1866 (set_attr "cc" "*,none,*,none,clobber,clobber,none,*,none")])
1868 (define_insn "*addqi3_non_v32"
1869 [(set (match_operand:QI
0 "register_operand" "=r,r, r,r,r,r,r")
1870 (plus:QI (match_operand:QI
1 "register_operand" "%
0,
0,
0,
0,
0,
0,r")
1871 (match_operand:QI
2 "general_operand" "r,Q>,J,N,O,g,!To")))]
1881 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no")
1882 (set_attr "cc" "normal,normal,clobber,clobber,clobber,normal,normal")])
1884 (define_insn "*addqi3_v32"
1885 [(set (match_operand:QI
0 "register_operand" "=r,!a,r,!a, r,r,!a,r,r,!a")
1887 (match_operand:QI
1 "register_operand" "%
0,r,
0, r,
0,
0,r,
0,
0,r")
1888 (match_operand:QI
2 "general_operand" "r,r, Q>,Q>,J,N,NJ,O,g,g")))]
1901 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,yes,no,no")
1902 (set_attr "cc" "*,none,*,none,clobber,clobber,none,clobber,*,none")])
1906 ;; Note that because of insn canonicalization these will *seldom* but
1907 ;; rarely be used with a known constant as an operand.
1909 ;; Note that for the 'P' constraint, the high part can be -
1 or
0. We
1910 ;; output the insn through the 'D' output modifier as "subs.w" and "subq",
1912 (define_expand "subdi3"
1913 [(set (match_operand:DI
0 "register_operand")
1914 (minus:DI (match_operand:DI
1 "register_operand")
1915 (match_operand:DI
2 "general_operand")))]
1918 if (TARGET_V32 && MEM_P (operands[
2]))
1919 operands[
2] = force_reg (DImode, operands[
2]);
1922 (define_insn "*subdi3_non_v32"
1923 [(set (match_operand:DI
0 "register_operand" "=r,r,r,&r,&r")
1924 (minus:DI (match_operand:DI
1 "register_operand" "
0,
0,
0,
0,r")
1925 (match_operand:DI
2 "general_operand" "J,N,P,g,!To")))]
1928 subq %
2,%M0\;ax\;subq
0,%H0
1929 addq %n2,%M0\;ax\;addq
0,%H0
1930 sub%e2.%z2 %
2,%M0\;ax\;%D2 %H2,%H0
1931 sub.d %M2,%M0\;ax\;sub.d %H2,%H0
1932 sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0")
1934 (define_insn "*subdi3_v32"
1935 [(set (match_operand:DI
0 "register_operand" "=r,r,r,&r")
1936 (minus:DI (match_operand:DI
1 "register_operand" "
0,
0,
0,
0")
1937 (match_operand:DI
2 "nonmemory_operand" "J,N,P,r")))]
1940 subq %
2,%M0\;ax\;subq
0,%H0
1941 addq %n2,%M0\;ax\;addq
0,%H0
1942 sub%e2.%z2 %
2,%M0\;ax\;%D2 %H2,%H0
1943 sub.d %M2,%M0\;ax\;sub.d %H2,%H0")
1945 (define_expand "sub<mode>
3"
1946 [(set (match_operand:BWD
0 "register_operand")
1948 (match_operand:BWD
1 "register_operand")
1949 (match_operand:BWD
2 "general_operand")))]
1953 (define_insn "*subsi3_non_v32"
1954 [(set (match_operand:SI
0 "register_operand" "=r,r, r,r,r,r,r,r")
1956 (match_operand:SI
1 "register_operand" "
0,
0,
0,
0,
0,
0,
0,r")
1957 (match_operand:SI
2 "general_operand" "r,Q>,J,N,P,n,g,!To")))]
1960 ;; This does not do the optimal: "addu.w
65535,r0" when %
2 is negative.
1961 ;; But then again, %
2 should not be negative.
1972 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")])
1974 (define_insn "*subsi3_v32"
1975 [(set (match_operand:SI
0 "register_operand" "=r,r,r,r,r,r,r")
1977 (match_operand:SI
1 "register_operand" "
0,
0,
0,
0,
0,
0,
0")
1978 (match_operand:SI
2 "general_operand" "r,Q>,J,N,P,n,g")))]
1988 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")])
1990 (define_insn "*sub<mode>
3_nonv32"
1991 [(set (match_operand:BW
0 "register_operand" "=r,r, r,r,r,r")
1992 (minus:BW (match_operand:BW
1 "register_operand" "
0,
0,
0,
0,
0,r")
1993 (match_operand:BW
2 "general_operand" "r,Q>,J,N,g,!To")))]
2002 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2003 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
2005 (define_insn "*sub<mode>
3_v32"
2006 [(set (match_operand:BW
0 "register_operand" "=r,r,r,r,r")
2007 (minus:BW (match_operand:BW
1 "register_operand" "
0,
0,
0,
0,
0")
2008 (match_operand:BW
2 "general_operand" "r,Q>,J,N,g")))]
2016 [(set_attr "slottable" "yes,yes,yes,yes,no")
2017 (set_attr "cc" "normal,normal,clobber,clobber,normal")])
2019 ;; CRIS has some add/sub-with-sign/zero-extend instructions.
2020 ;; Although these perform sign/zero-extension to SImode, they are
2021 ;; equally applicable for the HImode case.
2022 ;; FIXME: Check; GCC should handle the widening.
2023 ;; Note that these must be located after the normal add/sub patterns,
2024 ;; so not to get constants into any less specific operands.
2026 ;; Extend with add/sub and side-effect.
2028 ;; ADDS/SUBS/ADDU/SUBU and BOUND, which needs a check for zero_extend
2030 ;; adds/subs/addu/subu bound [rx=ry+rz.S]
2033 ;; FIXME: GCC should widen.
2035 (define_insn "*extopqihi_side_biap"
2036 [(set (match_operand:HI
0 "register_operand" "=r,r")
2038 6 "cris_additive_operand_extend_operator"
2039 [(match_operand:HI
1 "register_operand" "
0,
0")
2041 7 "cris_extend_operator"
2043 (mult:SI (match_operand:SI
2 "register_operand" "r,r")
2044 (match_operand:SI
3 "const_int_operand" "n,n"))
2045 (match_operand:SI
4 "register_operand" "r,r")))])]))
2046 (set (match_operand:SI
5 "register_operand" "=*
4,r")
2047 (plus:SI (mult:SI (match_dup
2)
2050 "cris_side_effect_mode_ok (MULT, operands,
5,
4,
2,
3,
0)"
2053 %x6%e7.%m7 [%
5=%
4+%
2%T3],%
0")
2055 (define_insn "*extop<mode>si_side_biap"
2056 [(set (match_operand:SI
0 "register_operand" "=r,r")
2058 6 "cris_operand_extend_operator"
2059 [(match_operand:SI
1 "register_operand" "
0,
0")
2061 7 "cris_extend_operator"
2063 (mult:SI (match_operand:SI
2 "register_operand" "r,r")
2064 (match_operand:SI
3 "const_int_operand" "n,n"))
2065 (match_operand:SI
4 "register_operand" "r,r")))])]))
2066 (set (match_operand:SI
5 "register_operand" "=*
4,r")
2067 (plus:SI (mult:SI (match_dup
2)
2070 "(GET_CODE (operands[
6]) != UMIN || GET_CODE (operands[
7]) == ZERO_EXTEND)
2071 && cris_side_effect_mode_ok (MULT, operands,
5,
4,
2,
3,
0)"
2074 %x6%e7<m> [%
5=%
4+%
2%T3],%
0")
2081 (define_insn "*extopqihi_side"
2082 [(set (match_operand:HI
0 "register_operand" "=r,r,r,r,r")
2084 5 "cris_additive_operand_extend_operator"
2085 [(match_operand:HI
1 "register_operand" "
0,
0,
0,
0,
0")
2087 6 "cris_extend_operator"
2089 (plus:SI (match_operand:SI
2 "cris_bdap_operand" "%r,r,r,R,R")
2090 (match_operand:SI
3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")
2092 (set (match_operand:SI
4 "register_operand" "=*
2,r,r,*
3,r")
2093 (plus:SI (match_dup
2)
2095 "cris_side_effect_mode_ok (PLUS, operands,
4,
2,
3, -
1,
0)"
2097 if ((which_alternative ==
0 || which_alternative ==
3)
2098 && (!CONST_INT_P (operands[
3])
2099 || INTVAL (operands[
3]) >
127
2100 || INTVAL (operands[
3]) < -
128
2101 || satisfies_constraint_N (operands[
3])
2102 || satisfies_constraint_J (operands[
3])))
2104 if (which_alternative ==
4)
2105 return "%x5%E6.%m6 [%
4=%
3%S2],%
0";
2106 return "%x5%E6.%m6 [%
4=%
2%S3],%
0";
2109 (define_insn "*extop<mode>si_side"
2110 [(set (match_operand:SI
0 "register_operand" "=r,r,r,r,r")
2112 5 "cris_operand_extend_operator"
2113 [(match_operand:SI
1 "register_operand" "
0,
0,
0,
0,
0")
2115 6 "cris_extend_operator"
2117 (plus:SI (match_operand:SI
2 "cris_bdap_operand" "%r,r,r,R,R")
2118 (match_operand:SI
3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")
2120 (set (match_operand:SI
4 "register_operand" "=*
2,r,r,*
3,r")
2121 (plus:SI (match_dup
2)
2123 "(GET_CODE (operands[
5]) != UMIN || GET_CODE (operands[
6]) == ZERO_EXTEND)
2124 && cris_side_effect_mode_ok (PLUS, operands,
4,
2,
3, -
1,
0)"
2126 if ((which_alternative ==
0 || which_alternative ==
3)
2127 && (!CONST_INT_P (operands[
3])
2128 || INTVAL (operands[
3]) >
127
2129 || INTVAL (operands[
3]) < -
128
2130 || satisfies_constraint_N (operands[
3])
2131 || satisfies_constraint_J (operands[
3])))
2133 if (which_alternative ==
4)
2134 return "%x5%E6<m> [%
4=%
3%S2],%
0";
2135 return "%x5%E6<m> [%
4=%
2%S3],%
0";
2139 ;; As with op.S we may have to add special pattern to match commuted
2140 ;; operands to adds/addu and bound
2142 ;; adds/addu/bound [rx=ry+rz.S]
2145 ;; FIXME: GCC should widen.
2147 (define_insn "*extopqihi_swap_side_biap"
2148 [(set (match_operand:HI
0 "register_operand" "=r,r")
2151 6 "cris_extend_operator"
2153 (mult:SI (match_operand:SI
2 "register_operand" "r,r")
2154 (match_operand:SI
3 "const_int_operand" "n,n"))
2155 (match_operand:SI
4 "register_operand" "r,r")))])
2156 (match_operand:HI
1 "register_operand" "
0,
0")))
2157 (set (match_operand:SI
5 "register_operand" "=*
4,r")
2158 (plus:SI (mult:SI (match_dup
2)
2161 "cris_side_effect_mode_ok (MULT, operands,
5,
4,
2,
3,
0)"
2164 add%e6.b [%
5=%
4+%
2%T3],%
0")
2166 (define_insn "*extop<mode>si_swap_side_biap"
2167 [(set (match_operand:SI
0 "register_operand" "=r,r")
2169 7 "cris_plus_or_bound_operator"
2171 6 "cris_extend_operator"
2173 (mult:SI (match_operand:SI
2 "register_operand" "r,r")
2174 (match_operand:SI
3 "const_int_operand" "n,n"))
2175 (match_operand:SI
4 "register_operand" "r,r")))])
2176 (match_operand:SI
1 "register_operand" "
0,
0")]))
2177 (set (match_operand:SI
5 "register_operand" "=*
4,r")
2178 (plus:SI (mult:SI (match_dup
2)
2181 "(GET_CODE (operands[
7]) != UMIN || GET_CODE (operands[
6]) == ZERO_EXTEND)
2182 && cris_side_effect_mode_ok (MULT, operands,
5,
4,
2,
3,
0)"
2185 %x7%E6<m> [%
5=%
4+%
2%T3],%
0")
2188 ;; FIXME: GCC should widen.
2192 (define_insn "*extopqihi_swap_side"
2193 [(set (match_operand:HI
0 "register_operand" "=r,r,r,r,r")
2196 5 "cris_extend_operator"
2198 (match_operand:SI
2 "cris_bdap_operand" "%r,r,r,R,R")
2199 (match_operand:SI
3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])
2200 (match_operand:HI
1 "register_operand" "
0,
0,
0,
0,
0")))
2201 (set (match_operand:SI
4 "register_operand" "=*
2,r,r,*
3,r")
2202 (plus:SI (match_dup
2)
2204 "cris_side_effect_mode_ok (PLUS, operands,
4,
2,
3, -
1,
0)"
2206 if ((which_alternative ==
0 || which_alternative ==
3)
2207 && (!CONST_INT_P (operands[
3])
2208 || INTVAL (operands[
3]) >
127
2209 || INTVAL (operands[
3]) < -
128
2210 || satisfies_constraint_N (operands[
3])
2211 || satisfies_constraint_J (operands[
3])))
2213 if (which_alternative ==
4)
2214 return "add%e5.b [%
4=%
3%S2],%
0";
2215 return "add%e5.b [%
4=%
2%S3],%
0";
2218 (define_insn "*extop<mode>si_swap_side"
2219 [(set (match_operand:SI
0 "register_operand" "=r,r,r,r,r")
2221 6 "cris_plus_or_bound_operator"
2223 5 "cris_extend_operator"
2225 (match_operand:SI
2 "cris_bdap_operand" "%r,r,r,R,R")
2226 (match_operand:SI
3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])
2227 (match_operand:SI
1 "register_operand" "
0,
0,
0,
0,
0")]))
2228 (set (match_operand:SI
4 "register_operand" "=*
2,r,r,*
3,r")
2229 (plus:SI (match_dup
2)
2231 "(GET_CODE (operands[
6]) != UMIN || GET_CODE (operands[
5]) == ZERO_EXTEND)
2232 && cris_side_effect_mode_ok (PLUS, operands,
4,
2,
3, -
1,
0)"
2234 if ((which_alternative ==
0 || which_alternative ==
3)
2235 && (!CONST_INT_P (operands[
3])
2236 || INTVAL (operands[
3]) >
127
2237 || INTVAL (operands[
3]) < -
128
2238 || satisfies_constraint_N (operands[
3])
2239 || satisfies_constraint_J (operands[
3])))
2241 if (which_alternative ==
4)
2242 return
\"%x6%E5.%m5 [%
4=%
3%S2],%
0\";
2243 return "%x6%E5<m> [%
4=%
2%S3],%
0";
2246 ;; Extend versions (zero/sign) of normal add/sub (no side-effects).
2249 ;; FIXME: GCC should widen.
2251 (define_insn "*extopqihi_non_v32"
2252 [(set (match_operand:HI
0 "register_operand" "=r,r,r,r")
2254 3 "cris_additive_operand_extend_operator"
2255 [(match_operand:HI
1 "register_operand" "
0,
0,
0,r")
2257 4 "cris_extend_operator"
2258 [(match_operand:QI
2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2259 "!TARGET_V32 && GET_MODE_SIZE (GET_MODE (operands[
0])) <= UNITS_PER_WORD
2260 && (operands[
1] != frame_pointer_rtx || GET_CODE (operands[
3]) != PLUS)"
2265 %x3%E4.%m4 %
2,%
1,%
0"
2266 [(set_attr "slottable" "yes,yes,no,no")
2267 (set_attr "cc" "clobber")])
2269 (define_insn "*extopqihi_v32"
2270 [(set (match_operand:HI
0 "register_operand" "=r,r")
2272 3 "cris_additive_operand_extend_operator"
2273 [(match_operand:HI
1 "register_operand" "
0,
0")
2275 4 "cris_extend_operator"
2276 [(match_operand:QI
2 "nonimmediate_operand" "r,m")])]))]
2279 [(set_attr "slottable" "yes")
2280 (set_attr "cc" "clobber")])
2284 (define_insn "*extop<mode>si_non_v32"
2285 [(set (match_operand:SI
0 "register_operand" "=r,r,r,r")
2287 3 "cris_operand_extend_operator"
2288 [(match_operand:SI
1 "register_operand" "
0,
0,
0,r")
2290 4 "cris_extend_operator"
2291 [(match_operand:BW
2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2293 && (GET_CODE (operands[
3]) != UMIN || GET_CODE (operands[
4]) == ZERO_EXTEND)
2294 && GET_MODE_SIZE (GET_MODE (operands[
0])) <= UNITS_PER_WORD
2295 && (operands[
1] != frame_pointer_rtx || GET_CODE (operands[
3]) != PLUS)"
2301 [(set_attr "slottable" "yes,yes,no,no")])
2303 (define_insn "*extop<mode>si_v32"
2304 [(set (match_operand:SI
0 "register_operand" "=r,r")
2306 3 "cris_additive_operand_extend_operator"
2307 [(match_operand:SI
1 "register_operand" "
0,
0")
2309 4 "cris_extend_operator"
2310 [(match_operand:BW
2 "nonimmediate_operand" "r,m")])]))]
2313 [(set_attr "slottable" "yes")])
2315 ;; As with the side-effect patterns, may have to have swapped operands for add.
2316 ;; For commutative operands, these are the canonical forms.
2320 (define_insn "*addxqihi_swap_non_v32"
2321 [(set (match_operand:HI
0 "register_operand" "=r,r,r,r")
2324 3 "cris_extend_operator"
2325 [(match_operand:QI
2 "nonimmediate_operand" "r,Q>,m,!To")])
2326 (match_operand:HI
1 "register_operand" "
0,
0,
0,r")))]
2327 "!TARGET_V32 && operands[
1] != frame_pointer_rtx"
2333 [(set_attr "slottable" "yes,yes,no,no")
2334 (set_attr "cc" "clobber")])
2336 ;; A case for v32, to catch the "addo" insn in addition to "adds". We
2337 ;; only care to match the canonical form; there should be no other.
2339 (define_insn "*addsbw_v32"
2340 [(set (match_operand:HI
0 "register_operand" "=r,r,!a")
2343 (match_operand:QI
2 "nonimmediate_operand" "r,m,m"))
2344 (match_operand:HI
1 "register_operand" "
0,
0,r")))]
2350 [(set_attr "slottable" "yes")
2351 (set_attr "cc" "clobber,clobber,none")])
2353 (define_insn "*addubw_v32"
2354 [(set (match_operand:HI
0 "register_operand" "=r,r")
2357 (match_operand:QI
2 "nonimmediate_operand" "r,m"))
2358 (match_operand:HI
1 "register_operand" "
0,
0")))]
2361 [(set_attr "slottable" "yes")
2362 (set_attr "cc" "clobber")])
2364 (define_insn "*extop<mode>si_swap_non_v32"
2365 [(set (match_operand:SI
0 "register_operand" "=r,r,r,r")
2367 4 "cris_plus_or_bound_operator"
2369 3 "cris_extend_operator"
2370 [(match_operand:BW
2 "nonimmediate_operand" "r,Q>,m,!To")])
2371 (match_operand:SI
1 "register_operand" "
0,
0,
0,r")]))]
2373 && (GET_CODE (operands[
4]) != UMIN || GET_CODE (operands[
3]) == ZERO_EXTEND)
2374 && operands[
1] != frame_pointer_rtx"
2380 [(set_attr "slottable" "yes,yes,no,no")])
2382 (define_insn "*adds<mode>_v32"
2383 [(set (match_operand:SI
0 "register_operand" "=r,r,!a")
2386 (match_operand:BW
2 "nonimmediate_operand" "r,m,m"))
2387 (match_operand:SI
1 "register_operand" "
0,
0,r")))]
2393 [(set_attr "slottable" "yes")
2394 (set_attr "cc" "*,*,none")])
2396 (define_insn "*addu<mode>_v32"
2397 [(set (match_operand:SI
0 "register_operand" "=r,r")
2400 (match_operand:BW
2 "nonimmediate_operand" "r,m"))
2401 (match_operand:SI
1 "register_operand" "
0,
0")))]
2402 "TARGET_V32 && operands[
1] != frame_pointer_rtx"
2404 [(set_attr "slottable" "yes")])
2406 (define_insn "*bound<mode>_v32"
2407 [(set (match_operand:SI
0 "register_operand" "=r")
2410 (match_operand:BW
2 "register_operand" "r"))
2411 (match_operand:SI
1 "register_operand" "
0")))]
2412 "TARGET_V32 && operands[
1] != frame_pointer_rtx"
2414 [(set_attr "slottable" "yes")])
2416 ;; This is the special case when we use what corresponds to the
2417 ;; instruction above in "casesi". Do *not* change it to use the generic
2418 ;; pattern and "REG
15" as pc; I did that and it led to madness and
2419 ;; maintenance problems: Instead of (as imagined) recognizing and removing
2420 ;; or replacing this pattern with something simpler, other variant
2421 ;; patterns were recognized or combined, including some prefix variants
2422 ;; where the value in pc is not that of the next instruction (which means
2423 ;; this instruction actually *is* special and *should* be marked as such).
2424 ;; When switching from the "generic pattern match" approach to this simpler
2425 ;; approach, there were insignificant differences in gcc, ipps and
2426 ;; product code, somehow due to scratching reload behind the ear or
2427 ;; something. Testcase "gcc" looked
.01% slower and
4 bytes bigger;
2428 ;; product code became
.001% smaller but "looked better". The testcase
2429 ;; "ipps" was just different at register allocation).
2431 ;; Assumptions in the jump optimizer forces us to use IF_THEN_ELSE in this
2432 ;; pattern with the default-label as the else, with the "if" being
2433 ;; index-is-less-than the max number of cases plus one. The default-label
2434 ;; is attached to the end of the case-table at time of output.
2436 (define_insn "*casesi_adds_w"
2439 (ltu (match_operand:SI
0 "register_operand" "r")
2440 (match_operand:SI
1 "const_int_operand" "n"))
2441 (plus:SI (sign_extend:SI
2443 (plus:SI (mult:SI (match_dup
0) (const_int
2))
2446 (label_ref (match_operand
2 "" ""))))
2447 (use (label_ref (match_operand
3 "" "")))]
2448 "!TARGET_V32 && operands[
0] != frame_pointer_rtx"
2449 "adds.w [$pc+%
0.w],$pc"
2450 [(set_attr "cc" "clobber")])
2452 ;; For V32, we just have a jump, but we need to mark the table as used,
2453 ;; and the jump insn must have the if_then_else form expected by core
2454 ;; GCC. Since we don't want to prolong the lifetime of the original
2455 ;; index value, we compare against "unspec
0". It's a pity we have to
2456 ;; jump through to get the default label in place and to keep the jump
2457 ;; table around. FIXME: Look into it some time.
2459 (define_insn "*casesi_jump_v32"
2462 (ltu (unspec [(const_int
0)] CRIS_UNSPEC_CASESI)
2463 (match_operand:SI
0 "const_int_operand" "n"))
2464 (match_operand:SI
1 "register_operand" "r")
2465 (label_ref (match_operand
2 "" ""))))
2466 (use (label_ref (match_operand
3 "" "")))]
2469 [(set_attr "cc" "clobber")
2470 (set_attr "slottable" "has_slot")])
2472 ;; Multiply instructions.
2474 ;; Sometimes powers of
2 (which are normally canonicalized to a
2475 ;; left-shift) appear here, as a result of address reloading.
2476 ;; As a special, for values
3 and
5, we can match with an addi, so add those.
2478 ;; FIXME: This may be unnecessary now.
2479 ;; Explicitly named for convenience of having a gen_... function.
2481 (define_insn "addi_mul"
2482 [(set (match_operand:SI
0 "register_operand" "=r")
2484 (match_operand:SI
1 "register_operand" "%
0")
2485 (match_operand:SI
2 "const_int_operand" "n")))]
2486 "operands[
0] != frame_pointer_rtx
2487 && operands[
1] != frame_pointer_rtx
2488 && CONST_INT_P (operands[
2])
2489 && (INTVAL (operands[
2]) ==
2
2490 || INTVAL (operands[
2]) ==
4 || INTVAL (operands[
2]) ==
3
2491 || INTVAL (operands[
2]) ==
5)"
2493 if (INTVAL (operands[
2]) ==
2)
2495 else if (INTVAL (operands[
2]) ==
4)
2497 else if (INTVAL (operands[
2]) ==
3)
2498 return "addi %
0.w,%
0";
2499 else if (INTVAL (operands[
2]) ==
5)
2500 return "addi %
0.d,%
0";
2501 return "BAD: adr_mulsi: %
0=%
1*%
2";
2503 [(set_attr "slottable" "yes")
2504 ;; No flags are changed if this insn is "addi", but it does not seem
2505 ;; worth the trouble to distinguish that to the lslq cases.
2506 (set_attr "cc" "clobber")])
2508 ;; The addi insn as it is normally used.
2510 ;; Make the ACR alternative taste bad enough to not choose it as a
2511 ;; preference to avoid spilling problems (unwind-dw2-fde.c at build).
2512 ;; FIXME: Revisit for new register allocator.
2514 (define_insn "*addi"
2515 [(set (match_operand:SI
0 "register_operand" "=r,!a")
2517 (mult:SI (match_operand:SI
2 "register_operand" "r,r")
2518 (match_operand:SI
3 "const_int_operand" "n,n"))
2519 (match_operand:SI
1 "register_operand" "
0,r")))]
2520 "operands[
0] != frame_pointer_rtx
2521 && operands[
1] != frame_pointer_rtx
2522 && CONST_INT_P (operands[
3])
2523 && (INTVAL (operands[
3]) ==
1
2524 || INTVAL (operands[
3]) ==
2 || INTVAL (operands[
3]) ==
4)"
2528 [(set_attr "slottable" "yes")
2529 (set_attr "cc" "none")])
2531 ;; The mstep instruction. Probably not useful by itself; it's to
2532 ;; non-linear wrt. the other insns. We used to expand to it, so at least
2535 (define_insn "mstep_shift"
2536 [(set (match_operand:SI
0 "register_operand" "=r")
2538 (lt:SI (cc0) (const_int
0))
2539 (plus:SI (ashift:SI (match_operand:SI
1 "register_operand" "
0")
2541 (match_operand:SI
2 "register_operand" "r"))
2542 (ashift:SI (match_operand:SI
3 "register_operand" "
0")
2546 [(set_attr "slottable" "yes")])
2548 ;; When illegitimate addresses are legitimized, sometimes gcc forgets
2549 ;; to canonicalize the multiplications.
2551 ;; FIXME: Check gcc >
2.7.2, remove and possibly fix in gcc.
2553 (define_insn "mstep_mul"
2554 [(set (match_operand:SI
0 "register_operand" "=r")
2556 (lt:SI (cc0) (const_int
0))
2557 (plus:SI (mult:SI (match_operand:SI
1 "register_operand" "
0")
2559 (match_operand:SI
2 "register_operand" "r"))
2560 (mult:SI (match_operand:SI
3 "register_operand" "
0")
2563 && operands[
0] != frame_pointer_rtx
2564 && operands[
1] != frame_pointer_rtx
2565 && operands[
2] != frame_pointer_rtx
2566 && operands[
3] != frame_pointer_rtx"
2568 [(set_attr "slottable" "yes")])
2570 (define_insn "<u>mul<s><mode>
3"
2571 [(set (match_operand:WD
0 "register_operand" "=r")
2573 (szext:WD (match_operand:<S>
1 "register_operand" "%
0"))
2574 (szext:WD (match_operand:<S>
2 "register_operand" "r"))))
2575 (clobber (match_scratch:SI
3 "=h"))]
2576 "TARGET_HAS_MUL_INSNS"
2577 "%!mul<su><mm> %
2,%
0"
2578 [(set (attr "slottable")
2579 (if_then_else (match_test "TARGET_MUL_BUG")
2581 (const_string "yes")))
2582 ;; For umuls.[bwd] it's just N unusable here, but let's be safe.
2583 ;; For muls.b, this really extends to SImode, so cc should be
2584 ;; considered clobbered.
2585 ;; For muls.w, it's just N unusable here, but let's be safe.
2586 (set_attr "cc" "clobber")])
2588 ;; Note that gcc does not make use of such a thing as umulqisi3. It gets
2589 ;; confused and will erroneously use it instead of umulhisi3, failing (at
2590 ;; least) gcc.c-torture/execute/arith-rand.c at all optimization levels.
2591 ;; Inspection of optab code shows that there must be only one widening
2592 ;; multiplication per mode widened to.
2594 (define_insn "mulsi3"
2595 [(set (match_operand:SI
0 "register_operand" "=r")
2596 (mult:SI (match_operand:SI
1 "register_operand" "%
0")
2597 (match_operand:SI
2 "register_operand" "r")))
2598 (clobber (match_scratch:SI
3 "=h"))]
2599 "TARGET_HAS_MUL_INSNS"
2601 [(set (attr "slottable")
2602 (if_then_else (match_test "TARGET_MUL_BUG")
2604 (const_string "yes")))
2605 ;; Just N unusable here, but let's be safe.
2606 (set_attr "cc" "clobber")])
2608 ;; A few multiply variations.
2610 ;; When needed, we can get the high
32 bits from the overflow
2611 ;; register. We don't care to split and optimize these.
2613 ;; Note that cc0 is still valid after the move-from-overflow-register
2614 ;; insn; no special precaution need to be taken in cris_notice_update_cc.
2616 (define_insn "<u>mulsidi3"
2617 [(set (match_operand:DI
0 "register_operand" "=r")
2619 (szext:DI (match_operand:SI
1 "register_operand" "%
0"))
2620 (szext:DI (match_operand:SI
2 "register_operand" "r"))))
2621 (clobber (match_scratch:SI
3 "=h"))]
2622 "TARGET_HAS_MUL_INSNS"
2623 "%!mul<su>.d %
2,%M0\;move $mof,%H0")
2625 ;; These two patterns may be expressible by other means, perhaps by making
2626 ;; [u]?mulsidi3 a define_expand.
2628 ;; Due to register allocation braindamage, the clobber
1,
2 alternatives
2629 ;; cause a move into the clobbered register *before* the insn, then
2630 ;; after the insn, mof is moved too, rather than the clobber assigned
2631 ;; the last mof target. This became apparent when making MOF and SRP
2632 ;; visible registers, with the necessary tweak to smulsi3_highpart.
2633 ;; Because these patterns are used in division by constants, that damage
2634 ;; is visible (ipps regression tests). Therefore the last two
2635 ;; alternatives, "helping" reload to avoid an unnecessary move, but
2636 ;; punished by force of one "?". Check code from "int d (int a) {return
2637 ;; a /
1000;}" and unsigned. FIXME: Comment above was for
3.2, revisit.
2639 (define_insn "<su>mulsi3_highpart"
2640 [(set (match_operand:SI
0 "register_operand" "=h,h,?r,?r")
2644 (szext:DI (match_operand:SI
1 "register_operand" "r,r,
0,r"))
2645 (szext:DI (match_operand:SI
2 "register_operand" "r,r,r,
0")))
2647 (clobber (match_scratch:SI
3 "=
1,
2,h,h"))]
2648 "TARGET_HAS_MUL_INSNS"
2652 %!mul<su>.d %
2,%
1\;move $mof,%
0
2653 %!mul<su>.d %
1,%
2\;move $mof,%
0"
2654 [(set_attr "slottable" "yes,yes,no,no")
2655 (set_attr "cc" "clobber")])
2657 ;; Divide and modulus instructions. CRIS only has a step instruction.
2659 (define_insn "dstep_shift"
2660 [(set (match_operand:SI
0 "register_operand" "=r")
2662 (geu:SI (ashift:SI (match_operand:SI
1 "register_operand" "
0")
2664 (match_operand:SI
2 "register_operand" "r"))
2665 (minus:SI (ashift:SI (match_operand:SI
3 "register_operand" "
0")
2667 (match_operand:SI
4 "register_operand" "
2"))
2668 (ashift:SI (match_operand:SI
5 "register_operand" "
0")
2672 [(set_attr "slottable" "yes")
2673 (set_attr "cc" "noov32")])
2675 ;; Here's a variant with mult instead of ashift.
2677 ;; FIXME: This should be investigated. Which one matches through combination?
2679 (define_insn "dstep_mul"
2680 [(set (match_operand:SI
0 "register_operand" "=r")
2682 (geu:SI (mult:SI (match_operand:SI
1 "register_operand" "
0")
2684 (match_operand:SI
2 "register_operand" "r"))
2685 (minus:SI (mult:SI (match_operand:SI
3 "register_operand" "
0")
2687 (match_operand:SI
4 "register_operand" "
2"))
2688 (mult:SI (match_operand:SI
5 "register_operand" "
0")
2690 "operands[
0] != frame_pointer_rtx
2691 && operands[
1] != frame_pointer_rtx
2692 && operands[
2] != frame_pointer_rtx
2693 && operands[
3] != frame_pointer_rtx"
2695 [(set_attr "slottable" "yes")
2696 (set_attr "cc" "noov32")])
2698 ;; Logical operators.
2702 ;; There is no use in defining "anddi3", because gcc can expand this by
2703 ;; itself, and make reasonable code without interference.
2705 ;; If the first operand is memory or a register and is the same as the
2706 ;; second operand, and the third operand is -
256 or -
65536, we can use
2707 ;; CLEAR instead. Or, if the first operand is a register, and the third
2708 ;; operand is
255 or
65535, we can zero_extend.
2709 ;; GCC isn't smart enough to recognize these cases (yet), and they seem
2710 ;; to be common enough to be worthwhile.
2711 ;; FIXME: This should be made obsolete.
2713 (define_expand "andsi3"
2714 [(set (match_operand:SI
0 "nonimmediate_operand" "")
2715 (and:SI (match_operand:SI
1 "nonimmediate_operand" "")
2716 (match_operand:SI
2 "general_operand" "")))]
2719 if (! (CONST_INT_P (operands[
2])
2720 && (((INTVAL (operands[
2]) == -
256
2721 || INTVAL (operands[
2]) == -
65536)
2722 && rtx_equal_p (operands[
1], operands[
0]))
2723 || ((INTVAL (operands[
2]) ==
255
2724 || INTVAL (operands[
2]) ==
65535)
2725 && REG_P (operands[
0])))))
2727 /* Make intermediate steps if operand0 is not a register or
2728 operand1 is not a register, and hope that the reload pass will
2729 make something useful out of it. Note that the operands are
2730 *not* canonicalized. For the moment, I chicken out on this,
2731 because all or most ports do not describe 'and' with
2732 canonicalized operands, and I seem to remember magic in reload,
2733 checking that operand1 has constraint '%
0', in which case
2734 operand0 and operand1 must have similar predicates.
2735 FIXME: Investigate. */
2736 rtx reg0 = REG_P (operands[
0]) ? operands[
0] : gen_reg_rtx (SImode);
2737 rtx reg1 = operands[
1];
2741 emit_move_insn (reg0, reg1);
2745 emit_insn (gen_rtx_SET (SImode, reg0,
2746 gen_rtx_AND (SImode, reg1, operands[
2])));
2748 /* Make sure we get the right *final* destination. */
2749 if (! REG_P (operands[
0]))
2750 emit_move_insn (operands[
0], reg0);
2756 ;; Some special cases of andsi3.
2758 (define_insn "*andsi_movu"
2759 [(set (match_operand:SI
0 "register_operand" "=r,r,r")
2760 (and:SI (match_operand:SI
1 "nonimmediate_operand" "%r,Q,To")
2761 (match_operand:SI
2 "const_int_operand" "n,n,n")))]
2762 "(INTVAL (operands[
2]) ==
255 || INTVAL (operands[
2]) ==
65535)
2763 && !side_effects_p (operands[
1])"
2765 [(set_attr "slottable" "yes,yes,no")])
2767 (define_insn "*andsi_clear"
2768 [(set (match_operand:SI
0 "nonimmediate_operand" "=r,r,Q,Q,To,To")
2769 (and:SI (match_operand:SI
1 "nonimmediate_operand" "%
0,
0,
0,
0,
0,
0")
2770 (match_operand:SI
2 "const_int_operand" "P,n,P,n,P,n")))]
2771 "(INTVAL (operands[
2]) == -
65536 || INTVAL (operands[
2]) == -
256)
2772 && !side_effects_p (operands[
0])"
2780 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2781 (set_attr "cc" "none")])
2783 ;; This is a catch-all pattern, taking care of everything that was not
2784 ;; matched in the insns above.
2786 ;; Sidenote: the tightening from "nonimmediate_operand" to
2787 ;; "register_operand" for operand
1 actually increased the register
2788 ;; pressure (worse code). That will hopefully change with an
2789 ;; improved reload pass.
2791 (define_insn "*expanded_andsi_non_v32"
2792 [(set (match_operand:SI
0 "register_operand" "=r,r,r, r,r")
2793 (and:SI (match_operand:SI
1 "register_operand" "%
0,
0,
0,
0,r")
2794 (match_operand:SI
2 "general_operand" "I,r,Q>,g,!To")))]
2802 [(set_attr "slottable" "yes,yes,yes,no,no")])
2804 (define_insn "*expanded_andsi_v32"
2805 [(set (match_operand:SI
0 "register_operand" "=r,r,r,r")
2806 (and:SI (match_operand:SI
1 "register_operand" "%
0,
0,
0,
0")
2807 (match_operand:SI
2 "general_operand" "I,r,Q>,g")))]
2814 [(set_attr "slottable" "yes,yes,yes,no")
2815 (set_attr "cc" "noov32")])
2817 ;; For both QI and HI we may use the quick patterns. This results in
2818 ;; useless condition codes, but that is used rarely enough for it to
2819 ;; normally be a win (could check ahead for use of cc0, but seems to be
2820 ;; more pain than win).
2822 ;; FIXME: See note for andsi3
2824 (define_expand "andhi3"
2825 [(set (match_operand:HI
0 "nonimmediate_operand" "")
2826 (and:HI (match_operand:HI
1 "nonimmediate_operand" "")
2827 (match_operand:HI
2 "general_operand" "")))]
2830 if (! (CONST_INT_P (operands[
2])
2831 && (((INTVAL (operands[
2]) == -
256
2832 || INTVAL (operands[
2]) ==
65280)
2833 && rtx_equal_p (operands[
1], operands[
0]))
2834 || (INTVAL (operands[
2]) ==
255
2835 && REG_P (operands[
0])))))
2837 /* See comment for andsi3. */
2838 rtx reg0 = REG_P (operands[
0]) ? operands[
0] : gen_reg_rtx (HImode);
2839 rtx reg1 = operands[
1];
2843 emit_move_insn (reg0, reg1);
2847 emit_insn (gen_rtx_SET (HImode, reg0,
2848 gen_rtx_AND (HImode, reg1, operands[
2])));
2850 /* Make sure we get the right destination. */
2851 if (! REG_P (operands[
0]))
2852 emit_move_insn (operands[
0], reg0);
2858 ;; Some fast andhi3 special cases.
2860 (define_insn "*andhi_movu"
2861 [(set (match_operand:HI
0 "register_operand" "=r,r,r")
2862 (and:HI (match_operand:HI
1 "nonimmediate_operand" "r,Q,To")
2864 "!side_effects_p (operands[
1])"
2866 [(set_attr "slottable" "yes,yes,no")])
2868 (define_insn "*andhi_clear"
2869 [(set (match_operand:HI
0 "nonimmediate_operand" "=r,Q,To")
2870 (and:HI (match_operand:HI
1 "nonimmediate_operand" "
0,
0,
0")
2872 "!side_effects_p (operands[
0])"
2874 [(set_attr "slottable" "yes,yes,no")
2875 (set_attr "cc" "none")])
2877 ;; Catch-all andhi3 pattern.
2879 (define_insn "*expanded_andhi_non_v32"
2880 [(set (match_operand:HI
0 "register_operand" "=r,r,r, r,r,r,r")
2881 (and:HI (match_operand:HI
1 "register_operand" "%
0,
0,
0,
0,
0,
0,r")
2882 (match_operand:HI
2 "general_operand" "I,r,Q>,L,O,g,!To")))]
2884 ;; Sidenote: the tightening from "general_operand" to
2885 ;; "register_operand" for operand
1 actually increased the register
2886 ;; pressure (worse code). That will hopefully change with an
2887 ;; improved reload pass.
2898 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
2899 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
2901 (define_insn "*expanded_andhi_v32"
2902 [(set (match_operand:HI
0 "register_operand" "=r,r,r,r,r,r")
2903 (and:HI (match_operand:HI
1 "register_operand" "%
0,
0,
0,
0,
0,
0")
2904 (match_operand:HI
2 "general_operand" "I,r,Q>,L,O,g")))]
2913 [(set_attr "slottable" "yes,yes,yes,no,yes,no")
2914 (set_attr "cc" "clobber,noov32,noov32,noov32,clobber,noov32")])
2916 ;; A strict_low_part pattern.
2918 ;; Note the use of (match_dup
0) for the first operand of the operation
2919 ;; here. Reload can't handle an operand pair where one is read-write
2920 ;; and must match a read, like in:
2922 ;; (set (strict_low_part
2923 ;; (subreg:QI (reg/v:SI
0 r0 [orig:
36 data ] [
36])
0))
2925 ;; (subreg:QI (reg:SI
15 acr [orig:
27 D
.7531 ] [
27])
0)
2926 ;; (const_int -
64 [
0xf..fc0]))) x.c:
126 147 {*andqi_lowpart_v32}
2928 ;; In theory, it could reload this as a movstrictqi of the register
2929 ;; operand at the and:QI to the destination register and change the
2930 ;; and:QI operand to the same as the read-write output operand and the
2931 ;; result would be recognized, but it doesn't recognize that's a valid
2932 ;; reload for a strict_low_part-destination; it just sees a "+" at the
2933 ;; destination constraints. Better than adding complexity to reload is
2934 ;; to follow the lead of m68k (see comment that begins with "These insns
2935 ;; must use MATCH_DUP") since prehistoric times and make it just a
2936 ;; match_dup. FIXME: a sanity-check in gen* to refuse an insn with
2937 ;; input-constraints matching input-output-constraints, e.g. "+r" <- "
0".
2939 (define_insn "*andhi_lowpart_non_v32"
2940 [(set (strict_low_part
2941 (match_operand:HI
0 "register_operand" "+r,r,r"))
2942 (and:HI (match_dup
0)
2943 (match_operand:HI
1 "general_operand" "r,Q>,g")))]
2949 [(set_attr "slottable" "yes,yes,no")])
2951 (define_insn "*andhi_lowpart_v32"
2952 [(set (strict_low_part
2953 (match_operand:HI
0 "register_operand" "+r,r,r"))
2954 (and:HI (match_dup
0)
2955 (match_operand:HI
1 "general_operand" "r,Q>,g")))]
2961 [(set_attr "slottable" "yes,yes,no")
2962 (set_attr "cc" "noov32")])
2964 (define_expand "andqi3"
2965 [(set (match_operand:QI
0 "register_operand")
2966 (and:QI (match_operand:QI
1 "register_operand")
2967 (match_operand:QI
2 "general_operand")))]
2971 (define_insn "*andqi3_non_v32"
2972 [(set (match_operand:QI
0 "register_operand" "=r,r,r, r,r,r")
2973 (and:QI (match_operand:QI
1 "register_operand" "%
0,
0,
0,
0,
0,r")
2974 (match_operand:QI
2 "general_operand" "I,r,Q>,O,g,!To")))]
2983 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2984 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
2986 (define_insn "*andqi3_v32"
2987 [(set (match_operand:QI
0 "register_operand" "=r,r,r,r,r")
2988 (and:QI (match_operand:QI
1 "register_operand" "%
0,
0,
0,
0,
0")
2989 (match_operand:QI
2 "general_operand" "I,r,Q>,O,g")))]
2997 [(set_attr "slottable" "yes,yes,yes,yes,no")
2998 (set_attr "cc" "clobber,noov32,noov32,clobber,noov32")])
3000 (define_insn "*andqi_lowpart_non_v32"
3001 [(set (strict_low_part
3002 (match_operand:QI
0 "register_operand" "+r,r,r"))
3003 (and:QI (match_dup
0)
3004 (match_operand:QI
1 "general_operand" "r,Q>,g")))]
3010 [(set_attr "slottable" "yes,yes,no")])
3012 (define_insn "*andqi_lowpart_v32"
3013 [(set (strict_low_part
3014 (match_operand:QI
0 "register_operand" "+r,r,r"))
3015 (and:QI (match_dup
0)
3016 (match_operand:QI
1 "general_operand" "r,Q>,g")))]
3022 [(set_attr "slottable" "yes,yes,no")
3023 (set_attr "cc" "noov32")])
3027 ;; Same comment as anddi3 applies here - no need for such a pattern.
3029 ;; It seems there's no need to jump through hoops to get good code such as
3032 (define_expand "ior<mode>
3"
3033 [(set (match_operand:BWD
0 "register_operand")
3034 (ior:BWD (match_operand:BWD
1 "register_operand")
3035 (match_operand:BWD
2 "general_operand")))]
3039 (define_insn "*iorsi3_non_v32"
3040 [(set (match_operand:SI
0 "register_operand" "=r,r,r, r,r,r")
3041 (ior:SI (match_operand:SI
1 "register_operand" "%
0,
0,
0,
0,
0,r")
3042 (match_operand:SI
2 "general_operand" "I, r,Q>,n,g,!To")))]
3051 [(set_attr "slottable" "yes,yes,yes,no,no,no")
3052 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
3054 (define_insn "*iorsi3_v32"
3055 [(set (match_operand:SI
0 "register_operand" "=r,r,r,r,r")
3056 (ior:SI (match_operand:SI
1 "register_operand" "%
0,
0,
0,
0,
0")
3057 (match_operand:SI
2 "general_operand" "I,r,Q>,n,g")))]
3065 [(set_attr "slottable" "yes,yes,yes,no,no")
3066 (set_attr "cc" "noov32,noov32,noov32,clobber,noov32")])
3068 (define_insn "*iorhi3_non_v32"
3069 [(set (match_operand:HI
0 "register_operand" "=r,r,r, r,r,r,r")
3070 (ior:HI (match_operand:HI
1 "register_operand" "%
0,
0,
0,
0,
0,
0,r")
3071 (match_operand:HI
2 "general_operand" "I,r,Q>,L,O,g,!To")))]
3081 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
3082 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
3084 (define_insn "*iorhi3_v32"
3085 [(set (match_operand:HI
0 "register_operand" "=r,r,r,r,r,r")
3086 (ior:HI (match_operand:HI
1 "register_operand" "%
0,
0,
0,
0,
0,
0")
3087 (match_operand:HI
2 "general_operand" "I,r,Q>,L,O,g")))]
3096 [(set_attr "slottable" "yes,yes,yes,no,yes,no")
3097 (set_attr "cc" "clobber,noov32,noov32,noov32,clobber,noov32")])
3099 (define_insn "*iorqi3_non_v32"
3100 [(set (match_operand:QI
0 "register_operand" "=r,r,r, r,r,r")
3101 (ior:QI (match_operand:QI
1 "register_operand" "%
0,
0,
0,
0,
0,r")
3102 (match_operand:QI
2 "general_operand" "I,r,Q>,O,g,!To")))]
3111 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
3112 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
3114 (define_insn "*iorqi3_v32"
3115 [(set (match_operand:QI
0 "register_operand" "=r,r,r,r,r")
3116 (ior:QI (match_operand:QI
1 "register_operand" "%
0,
0,
0,
0,
0")
3117 (match_operand:QI
2 "general_operand" "I,r,Q>,O,g")))]
3125 [(set_attr "slottable" "yes,yes,yes,yes,no")
3126 (set_attr "cc" "clobber,noov32,noov32,clobber,noov32")])
3130 ;; See comment about "anddi3" for xordi3 - no need for such a pattern.
3131 ;; FIXME: Do we really need the shorter variants?
3133 (define_insn "xorsi3"
3134 [(set (match_operand:SI
0 "register_operand" "=r")
3135 (xor:SI (match_operand:SI
1 "register_operand" "%
0")
3136 (match_operand:SI
2 "register_operand" "r")))]
3139 [(set_attr "slottable" "yes")
3140 (set_attr "cc" "noov32")])
3142 (define_insn "xor<mode>
3"
3143 [(set (match_operand:BW
0 "register_operand" "=r")
3144 (xor:BW (match_operand:BW
1 "register_operand" "%
0")
3145 (match_operand:BW
2 "register_operand" "r")))]
3148 [(set_attr "slottable" "yes")
3149 (set_attr "cc" "clobber")])
3153 ;; Questionable use, here mostly as a (slightly usable) define_expand
3156 (define_expand "negsf2"
3159 (parallel [(set (match_operand:SF
0 "register_operand" "=r")
3160 (neg:SF (match_operand:SF
1
3161 "register_operand" "
0")))
3162 (use (match_dup
2))])]
3165 operands[
2] = gen_reg_rtx (SImode);
3166 operands[
3] = GEN_INT (
1 <<
31);
3169 (define_insn "*expanded_negsf2"
3170 [(set (match_operand:SF
0 "register_operand" "=r")
3171 (neg:SF (match_operand:SF
1 "register_operand" "
0")))
3172 (use (match_operand:SI
2 "register_operand" "r"))]
3175 [(set_attr "slottable" "yes")])
3177 ;; No "negdi2" although we could make one up that may be faster than
3178 ;; the one in libgcc.
3180 (define_insn "neg<mode>
2"
3181 [(set (match_operand:BWD
0 "register_operand" "=r")
3182 (neg:BWD (match_operand:BWD
1 "register_operand" "r")))]
3185 [(set_attr "slottable" "yes")])
3189 ;; See comment on anddi3 - no need for a DImode pattern.
3190 ;; See also xor comment.
3192 (define_insn "one_cmplsi2"
3193 [(set (match_operand:SI
0 "register_operand" "=r")
3194 (not:SI (match_operand:SI
1 "register_operand" "
0")))]
3197 [(set_attr "slottable" "yes")
3198 (set_attr "cc" "noov32")])
3200 (define_insn "one_cmpl<mode>
2"
3201 [(set (match_operand:BW
0 "register_operand" "=r")
3202 (not:BW (match_operand:BW
1 "register_operand" "
0")))]
3205 [(set_attr "slottable" "yes")
3206 (set_attr "cc" "clobber")])
3208 ;; Arithmetic/Logical shift right (and SI left).
3210 (define_insn "<shlr>si3"
3211 [(set (match_operand:SI
0 "register_operand" "=r")
3212 (shift:SI (match_operand:SI
1 "register_operand" "
0")
3213 (match_operand:SI
2 "nonmemory_operand" "Kcr")))]
3216 if (REG_S_P (operands[
2]))
3217 return "<slr>.d %
2,%
0";
3219 return "<slr>q %
2,%
0";
3221 [(set_attr "slottable" "yes")
3222 (set_attr "cc" "noov32")])
3224 ;; Since gcc gets lost, and forgets to zero-extend the source (or mask
3225 ;; the destination) when it changes shifts of lower modes into SImode,
3226 ;; it is better to make these expands an anonymous patterns instead of
3227 ;; the more correct define_insns. This occurs when gcc thinks that is
3228 ;; is better to widen to SImode and use immediate shift count.
3230 ;; FIXME: Is this legacy or still true for gcc >=
2.7.2?
3232 ;; FIXME: Can't parametrize sign_extend and zero_extend (before
3233 ;; mentioning "shiftrt"), so we need two patterns.
3234 (define_expand "ashr<mode>
3"
3236 (sign_extend:SI (match_operand:BW
1 "nonimmediate_operand" "")))
3238 (zero_extend:SI (match_operand:BW
2 "nonimmediate_operand" "")))
3239 (set (match_dup
5) (ashiftrt:SI (match_dup
3) (match_dup
4)))
3240 (set (match_operand:BW
0 "general_operand" "")
3241 (subreg:BW (match_dup
5)
0))]
3246 for (i =
3; i <
6; i++)
3247 operands[i] = gen_reg_rtx (SImode);
3250 (define_expand "lshr<mode>
3"
3252 (zero_extend:SI (match_operand:BW
1 "nonimmediate_operand" "")))
3254 (zero_extend:SI (match_operand:BW
2 "nonimmediate_operand" "")))
3255 (set (match_dup
5) (lshiftrt:SI (match_dup
3) (match_dup
4)))
3256 (set (match_operand:BW
0 "general_operand" "")
3257 (subreg:BW (match_dup
5)
0))]
3262 for (i =
3; i <
6; i++)
3263 operands[i] = gen_reg_rtx (SImode);
3266 (define_insn "*expanded_<shlr><mode>"
3267 [(set (match_operand:BW
0 "register_operand" "=r")
3268 (shiftrt:BW (match_operand:BW
1 "register_operand" "
0")
3269 (match_operand:BW
2 "register_operand" "r")))]
3272 [(set_attr "slottable" "yes")
3273 (set_attr "cc" "noov32")])
3275 (define_insn "*<shlr><mode>_lowpart"
3276 [(set (strict_low_part (match_operand:BW
0 "register_operand" "+r"))
3277 (shiftrt:BW (match_dup
0)
3278 (match_operand:BW
1 "register_operand" "r")))]
3281 [(set_attr "slottable" "yes")
3282 (set_attr "cc" "noov32")])
3284 ;; Arithmetic/logical shift left.
3286 ;; For narrower modes than SI, we can use lslq although it makes cc
3287 ;; unusable. The win is that we do not have to reload the shift-count
3290 (define_insn "ashl<mode>
3"
3291 [(set (match_operand:BW
0 "register_operand" "=r,r")
3292 (ashift:BW (match_operand:BW
1 "register_operand" "
0,
0")
3293 (match_operand:BW
2 "nonmemory_operand" "r,Kc")))]
3297 (CONST_INT_P (operands[
2]) && INTVAL (operands[
2]) > <nbitsm1>)
3299 : (CONSTANT_P (operands[
2])
3300 ? "lslq %
2,%
0" : "lsl<m> %
2,%
0");
3302 [(set_attr "slottable" "yes")
3303 (set_attr "cc" "noov32,clobber")])
3305 ;; A strict_low_part matcher.
3307 (define_insn "*ashl<mode>_lowpart"
3308 [(set (strict_low_part (match_operand:BW
0 "register_operand" "+r"))
3309 (ashift:BW (match_dup
0)
3310 (match_operand:HI
1 "register_operand" "r")))]
3313 [(set_attr "slottable" "yes")
3314 (set_attr "cc" "noov32")])
3316 ;; Various strange insns that gcc likes.
3318 ;; Fortunately, it is simple to construct an abssf (although it may not
3319 ;; be very much used in practice).
3321 (define_insn "abssf2"
3322 [(set (match_operand:SF
0 "register_operand" "=r")
3323 (abs:SF (match_operand:SF
1 "register_operand" "
0")))]
3325 "lslq
1,%
0\;lsrq
1,%
0")
3327 (define_insn "abssi2"
3328 [(set (match_operand:SI
0 "register_operand" "=r")
3329 (abs:SI (match_operand:SI
1 "register_operand" "r")))]
3332 [(set_attr "slottable" "yes")
3333 (set_attr "cc" "noov32")])
3335 ;; FIXME: GCC should be able to do these expansions itself.
3337 (define_expand "abs<mode>
2"
3339 (sign_extend:SI (match_operand:BW
1 "general_operand" "")))
3340 (set (match_dup
3) (abs:SI (match_dup
2)))
3341 (set (match_operand:BW
0 "register_operand" "")
3342 (subreg:BW (match_dup
3)
0))]
3344 "operands[
2] = gen_reg_rtx (SImode); operands[
3] = gen_reg_rtx (SImode);")
3346 (define_insn "clzsi2"
3347 [(set (match_operand:SI
0 "register_operand" "=r")
3348 (clz:SI (match_operand:SI
1 "register_operand" "r")))]
3351 [(set_attr "slottable" "yes")
3352 (set_attr "cc" "noov32")])
3354 (define_insn "bswapsi2"
3355 [(set (match_operand:SI
0 "register_operand" "=r")
3356 (bswap:SI (match_operand:SI
1 "register_operand" "
0")))]
3359 [(set_attr "slottable" "yes")
3360 (set_attr "cc" "noov32")])
3362 ;; This instruction swaps all bits in a register.
3363 ;; That means that the most significant bit is put in the place
3364 ;; of the least significant bit, and so on.
3366 (define_insn "cris_swap_bits"
3367 [(set (match_operand:SI
0 "register_operand" "=r")
3368 (unspec:SI [(match_operand:SI
1 "register_operand" "
0")]
3369 CRIS_UNSPEC_SWAP_BITS))]
3372 [(set_attr "slottable" "yes")
3373 (set_attr "cc" "noov32")])
3375 ;; Implement ctz using two instructions, one for bit swap and one for clz.
3376 ;; Defines a scratch register to avoid clobbering input.
3378 (define_expand "ctzsi2"
3380 (match_operand:SI
1 "register_operand"))
3382 (unspec:SI [(match_dup
2)] CRIS_UNSPEC_SWAP_BITS))
3383 (set (match_operand:SI
0 "register_operand")
3384 (clz:SI (match_dup
2)))]
3385 "TARGET_HAS_LZ && TARGET_HAS_SWAP"
3386 "operands[
2] = gen_reg_rtx (SImode);")
3388 ;; Bound-insn. Defined to be the same as an unsigned minimum, which is an
3389 ;; operation supported by gcc. Used in casesi, but used now and then in
3392 (define_expand "uminsi3"
3393 [(set (match_operand:SI
0 "register_operand" "")
3394 (umin:SI (match_operand:SI
1 "register_operand" "")
3395 (match_operand:SI
2 "general_operand" "")))]
3398 if (MEM_P (operands[
2]) && TARGET_V32)
3399 operands[
2] = force_reg (SImode, operands[
2]);
3402 (define_insn "*uminsi3_non_v32"
3403 [(set (match_operand:SI
0 "register_operand" "=r,r, r,r")
3404 (umin:SI (match_operand:SI
1 "register_operand" "%
0,
0,
0,r")
3405 (match_operand:SI
2 "general_operand" "r,Q>,g,!To")))]
3408 if (CONST_INT_P (operands[
2]))
3410 /* Constant operands are zero-extended, so only
32-bit operands
3412 if (INTVAL (operands[
2]) >=
0)
3414 if (INTVAL (operands[
2]) <
256)
3415 return "bound.b %
2,%
0";
3417 if (INTVAL (operands[
2]) <
65536)
3418 return "bound.w %
2,%
0";
3421 else if (which_alternative ==
3)
3422 return "bound.d %
2,%
1,%
0";
3424 return "bound.d %
2,%
0";
3426 [(set_attr "slottable" "yes,yes,no,no")])
3428 (define_insn "*uminsi3_v32"
3429 [(set (match_operand:SI
0 "register_operand" "=r,r")
3430 (umin:SI (match_operand:SI
1 "register_operand" "%
0,
0")
3431 (match_operand:SI
2 "nonmemory_operand" "r,i")))]
3434 if (GET_CODE (operands[
2]) == CONST_INT)
3436 /* Constant operands are zero-extended, so only
32-bit operands
3438 if (INTVAL (operands[
2]) >=
0)
3440 if (INTVAL (operands[
2]) <
256)
3441 return "bound.b %
2,%
0";
3443 if (INTVAL (operands[
2]) <
65536)
3444 return "bound.w %
2,%
0";
3448 return "bound.d %
2,%
0";
3450 [(set_attr "slottable" "yes,no")])
3452 ;; Jump and branch insns.
3456 (label_ref (match_operand
0 "" "")))]
3459 [(set_attr "slottable" "has_slot")])
3461 ;; Testcase gcc.c-torture/compile/
991213-
3.c fails if we allow a constant
3462 ;; here, since the insn is not recognized as an indirect jump by
3463 ;; jmp_uses_reg_or_mem used by computed_jump_p. Perhaps it is a kludge to
3464 ;; change from general_operand to nonimmediate_operand (at least the docs
3465 ;; should be changed), but then again the pattern is called indirect_jump.
3466 (define_expand "indirect_jump"
3467 [(set (pc) (match_operand:SI
0 "nonimmediate_operand"))]
3470 if (TARGET_V32 && MEM_P (operands[
0]))
3471 operands[
0] = force_reg (SImode, operands[
0]);
3474 (define_insn "*indirect_jump_non_v32"
3475 [(set (pc) (match_operand:SI
0 "nonimmediate_operand" "rm"))]
3479 (define_insn "*indirect_jump_v32"
3480 [(set (pc) (match_operand:SI
0 "register_operand" "r"))]
3483 [(set_attr "slottable" "has_slot")])
3485 ;; Return insn. Used whenever the epilogue is very simple; if it is only
3486 ;; a single ret or jump [sp+]. No allocated stack space or saved
3487 ;; registers are allowed.
3488 ;; Note that for this pattern, although named, it is ok to check the
3489 ;; context of the insn in the test, not only compiler switches.
3491 (define_expand "return"
3493 "cris_simple_epilogue ()"
3494 "cris_expand_return (cris_return_address_on_stack ()); DONE;")
3496 (define_insn "*return_expanded"
3500 return cris_return_address_on_stack_for_return ()
3501 ? "jump [$sp+]" : "ret%#";
3503 [(set (attr "slottable")
3505 (match_test "cris_return_address_on_stack_for_return ()")
3507 (const_string "has_return_slot")))])
3509 (define_expand "prologue"
3511 "TARGET_PROLOGUE_EPILOGUE"
3512 "cris_expand_prologue (); DONE;")
3514 ;; Note that the (return) from the expander itself is always the last
3515 ;; insn in the epilogue.
3516 (define_expand "epilogue"
3518 "TARGET_PROLOGUE_EPILOGUE"
3519 "cris_expand_epilogue (); DONE;")
3521 ;; Conditional branches.
3523 (define_expand "cbranch<mode>
4"
3524 [(set (cc0) (compare
3525 (match_operand:BWD
1 "nonimmediate_operand")
3526 (match_operand:BWD
2 "general_operand")))
3528 (if_then_else (match_operator
0 "ordered_comparison_operator"
3529 [(cc0) (const_int
0)])
3530 (label_ref (match_operand
3 "" ""))
3535 (define_expand "cbranchdi4"
3537 (compare (match_operand:DI
1 "nonimmediate_operand" "")
3538 (match_operand:DI
2 "general_operand" "")))
3540 (if_then_else (match_operator
0 "ordered_comparison_operator"
3541 [(cc0) (const_int
0)])
3542 (label_ref (match_operand
3 "" ""))
3546 if (TARGET_V32 && !REG_P (operands[
1]))
3547 operands[
1] = force_reg (DImode, operands[
1]);
3548 if (TARGET_V32 && MEM_P (operands[
2]))
3549 operands[
2] = force_reg (DImode, operands[
2]);
3553 ;; We suffer from the same overflow-bit-gets-in-the-way problem as
3554 ;; e.g. m68k, so we have to check if overflow bit is set on all "signed"
3557 (define_insn "b<ncond:code>"
3559 (if_then_else (ncond (cc0)
3561 (label_ref (match_operand
0 "" ""))
3565 [(set_attr "slottable" "has_slot")])
3567 (define_insn "b<ocond:code>"
3569 (if_then_else (ocond (cc0)
3571 (label_ref (match_operand
0 "" ""))
3576 (cc_prev_status.flags & CC_NO_OVERFLOW)
3577 ?
0 : "b<CC> %l0%#";
3579 [(set_attr "slottable" "has_slot")])
3581 (define_insn "b<rcond:code>"
3583 (if_then_else (rcond (cc0)
3585 (label_ref (match_operand
0 "" ""))
3590 (cc_prev_status.flags & CC_NO_OVERFLOW)
3591 ? "b<oCC> %l0%#" : "b<CC> %l0%#";
3593 [(set_attr "slottable" "has_slot")])
3595 ;; Reversed anonymous patterns to the ones above, as mandated.
3597 (define_insn "*b<ncond:code>_reversed"
3599 (if_then_else (ncond (cc0)
3602 (label_ref (match_operand
0 "" ""))))]
3605 [(set_attr "slottable" "has_slot")])
3607 (define_insn "*b<ocond:code>_reversed"
3609 (if_then_else (ocond (cc0)
3612 (label_ref (match_operand
0 "" ""))))]
3616 (cc_prev_status.flags & CC_NO_OVERFLOW)
3617 ?
0 : "b<rCC> %l0%#";
3619 [(set_attr "slottable" "has_slot")])
3621 (define_insn "*b<rcond:code>_reversed"
3623 (if_then_else (rcond (cc0)
3626 (label_ref (match_operand
0 "" ""))))]
3630 (cc_prev_status.flags & CC_NO_OVERFLOW)
3631 ? "b<roCC> %l0%#" : "b<rCC> %l0%#";
3633 [(set_attr "slottable" "has_slot")])
3635 ;; Set on condition: sCC.
3637 (define_expand "cstoredi4"
3638 [(set (cc0) (compare
3639 (match_operand:DI
2 "nonimmediate_operand")
3640 (match_operand:DI
3 "general_operand")))
3641 (set (match_operand:SI
0 "register_operand")
3642 (match_operator:SI
1 "ordered_comparison_operator"
3643 [(cc0) (const_int
0)]))]
3646 if (TARGET_V32 && !REG_P (operands[
2]))
3647 operands[
2] = force_reg (DImode, operands[
2]);
3648 if (TARGET_V32 && MEM_P (operands[
3]))
3649 operands[
3] = force_reg (DImode, operands[
3]);
3652 (define_expand "cstore<mode>
4"
3653 [(set (cc0) (compare
3654 (match_operand:BWD
2 "nonimmediate_operand")
3655 (match_operand:BWD
3 "general_operand")))
3656 (set (match_operand:SI
0 "register_operand")
3657 (match_operator:SI
1 "ordered_comparison_operator"
3658 [(cc0) (const_int
0)]))]
3662 ;; Like bCC, we have to check the overflow bit for
3663 ;; signed conditions.
3665 (define_insn "s<ncond:code>"
3666 [(set (match_operand:SI
0 "register_operand" "=r")
3667 (ncond:SI (cc0) (const_int
0)))]
3670 [(set_attr "slottable" "yes")
3671 (set_attr "cc" "none")])
3673 (define_insn "s<rcond:code>"
3674 [(set (match_operand:SI
0 "register_operand" "=r")
3675 (rcond:SI (cc0) (const_int
0)))]
3679 (cc_prev_status.flags & CC_NO_OVERFLOW)
3680 ? "s<oCC> %
0" : "s<CC> %
0";
3682 [(set_attr "slottable" "yes")
3683 (set_attr "cc" "none")])
3685 (define_insn "s<ocond:code>"
3686 [(set (match_operand:SI
0 "register_operand" "=r")
3687 (ocond:SI (cc0) (const_int
0)))]
3691 (cc_prev_status.flags & CC_NO_OVERFLOW)
3694 [(set_attr "slottable" "yes")
3695 (set_attr "cc" "none")])
3699 ;; We need to make these patterns "expand", since the real operand is
3700 ;; hidden in a (mem:QI ) inside operand[
0] (call_value: operand[
1]),
3701 ;; and cannot be checked if it were a "normal" pattern.
3702 ;; Note that "call" and "call_value" are *always* called with a
3703 ;; mem-operand for operand
0 and
1 respective. What happens for combined
3704 ;; instructions is a different issue.
3706 (define_expand "call"
3707 [(parallel [(call (match_operand:QI
0 "cris_mem_call_operand" "")
3708 (match_operand
1 "general_operand" ""))
3709 (clobber (reg:SI CRIS_SRP_REGNUM))])]
3712 gcc_assert (MEM_P (operands[
0]));
3714 cris_expand_pic_call_address (&operands[
0]);
3717 ;; Accept *anything* as operand
1. Accept operands for operand
0 in
3718 ;; order of preference.
3720 (define_insn "*expanded_call_non_v32"
3721 [(call (mem:QI (match_operand:SI
0 "general_operand" "r,Q>,g"))
3722 (match_operand
1 "" ""))
3723 (clobber (reg:SI CRIS_SRP_REGNUM))]
3727 (define_insn "*expanded_call_v32"
3730 (match_operand:SI
0 "cris_nonmemory_operand_or_callable_symbol" "n,r,U,i"))
3731 (match_operand
1 "" ""))
3732 (clobber (reg:SI CRIS_SRP_REGNUM))]
3739 [(set_attr "slottable" "has_call_slot")])
3741 ;; Parallel when calculating and reusing address of indirect pointer
3742 ;; with simple offset. (Makes most sense with PIC.) It looks a bit
3743 ;; wrong not to have the clobber last, but that's the way combine
3744 ;; generates it (except it doesn' look into the *inner* mem, so this
3745 ;; just matches a peephole2). FIXME: investigate that.
3746 (define_insn "*expanded_call_side"
3749 (plus:SI (match_operand:SI
0 "cris_bdap_operand" "%r, r,r")
3750 (match_operand:SI
1 "cris_bdap_operand" "r>Rn,r,>Rn"))))
3751 (match_operand
2 "" ""))
3752 (clobber (reg:SI CRIS_SRP_REGNUM))
3753 (set (match_operand:SI
3 "register_operand" "=*
0,r,r")
3754 (plus:SI (match_dup
0)
3756 "!TARGET_AVOID_GOTPLT && !TARGET_V32"
3759 (define_expand "call_value"
3760 [(parallel [(set (match_operand
0 "" "")
3761 (call (match_operand:QI
1 "cris_mem_call_operand" "")
3762 (match_operand
2 "" "")))
3763 (clobber (reg:SI CRIS_SRP_REGNUM))])]
3766 gcc_assert (MEM_P (operands[
1]));
3768 cris_expand_pic_call_address (&operands[
1]);
3771 ;; Accept *anything* as operand
2. The validity other than "general" of
3772 ;; operand
0 will be checked elsewhere. Accept operands for operand
1 in
3773 ;; order of preference (Q includes r, but r is shorter, faster).
3774 ;; We also accept a PLT symbol. We output it as [rPIC+sym:GOTPLT] rather
3775 ;; than requiring getting rPIC + sym:PLT into a register.
3777 (define_insn "*expanded_call_value_non_v32"
3778 [(set (match_operand
0 "nonimmediate_operand" "=g,g,g")
3779 (call (mem:QI (match_operand:SI
1 "general_operand" "r,Q>,g"))
3780 (match_operand
2 "" "")))
3781 (clobber (reg:SI CRIS_SRP_REGNUM))]
3784 [(set_attr "cc" "clobber")])
3786 ;; See similar call special-case.
3787 (define_insn "*expanded_call_value_side"
3788 [(set (match_operand
0 "nonimmediate_operand" "=g,g,g")
3792 (plus:SI (match_operand:SI
1 "cris_bdap_operand" "%r, r,r")
3793 (match_operand:SI
2 "cris_bdap_operand" "r>Rn,r,>Rn"))))
3794 (match_operand
3 "" "")))
3795 (clobber (reg:SI CRIS_SRP_REGNUM))
3796 (set (match_operand:SI
4 "register_operand" "=*
1,r,r")
3797 (plus:SI (match_dup
1)
3799 "!TARGET_AVOID_GOTPLT && !TARGET_V32"
3801 [(set_attr "cc" "clobber")])
3803 (define_insn "*expanded_call_value_v32"
3805 (match_operand
0 "nonimmediate_operand" "=g,g,g,g")
3808 (match_operand:SI
1 "cris_nonmemory_operand_or_callable_symbol" "n,r,U,i"))
3809 (match_operand
2 "" "")))
3810 (clobber (reg:SI
16))]
3817 [(set_attr "cc" "clobber")
3818 (set_attr "slottable" "has_call_slot")])
3820 ;; Used in debugging. No use for the direct pattern; unfilled
3821 ;; delayed-branches are taken care of by other means.
3827 [(set_attr "cc" "none")])
3829 ;; Same as the gdb trap breakpoint, will cause a SIGTRAP for
3830 ;; cris-linux* and crisv32-linux*, as intended. Will work in
3831 ;; freestanding environments with sufficient framework.
3833 [(trap_if (const_int
1) (const_int
8))]
3834 "TARGET_TRAP_USING_BREAK8"
3837 ;; We need to stop accesses to the stack after the memory is
3838 ;; deallocated. Unfortunately, reorg doesn't look at naked clobbers,
3839 ;; e.g. (insn ... (clobber (mem:BLK (stack_pointer_rtx)))) and we don't
3840 ;; want to use a naked (unspec_volatile) as that would stop any
3841 ;; scheduling in the epilogue. Hence we model it as a "real" insn that
3842 ;; sets the memory in an unspecified manner. FIXME: Unfortunately it
3843 ;; still has the effect of an unspec_volatile.
3844 (define_insn "cris_frame_deallocated_barrier"
3845 [(set (mem:BLK (reg:SI CRIS_SP_REGNUM))
3846 (unspec:BLK [(const_int
0)] CRIS_UNSPEC_FRAME_DEALLOC))]
3849 [(set_attr "length" "
0")])
3851 ;; We expand on casesi so we can use "bound" and "add offset fetched from
3852 ;; a table to pc" (adds.w [pc+%
0.w],pc).
3854 ;; Note: if you change the "parallel" (or add anything after it) in
3855 ;; this expansion, you must change the macro ASM_OUTPUT_CASE_END
3856 ;; accordingly, to add the default case at the end of the jump-table.
3858 (define_expand "cris_casesi_non_v32"
3859 [(set (match_dup
5) (match_operand:SI
0 "general_operand" ""))
3861 (minus:SI (match_dup
5)
3862 (match_operand:SI
1 "const_int_operand" "n")))
3864 (umin:SI (match_dup
6)
3865 (match_operand:SI
2 "const_int_operand" "n")))
3869 (ltu (match_dup
7) (match_dup
2))
3870 (plus:SI (sign_extend:SI
3872 (plus:SI (mult:SI (match_dup
7) (const_int
2))
3875 (label_ref (match_operand
4 "" ""))))
3876 (use (label_ref (match_operand
3 "" "")))])]
3879 operands[
2] = plus_constant (SImode, operands[
2],
1);
3880 operands[
5] = gen_reg_rtx (SImode);
3881 operands[
6] = gen_reg_rtx (SImode);
3882 operands[
7] = gen_reg_rtx (SImode);
3885 ;; FIXME: Check effect of not JUMP_TABLES_IN_TEXT_SECTION.
3886 (define_expand "cris_casesi_v32"
3887 [(set (match_dup
5) (match_operand:SI
0 "general_operand"))
3889 (minus:SI (match_dup
5)
3890 (match_operand:SI
1 "const_int_operand")))
3892 (umin:SI (match_dup
6)
3893 (match_operand:SI
2 "const_int_operand")))
3894 (set (match_dup
8) (match_dup
11))
3896 (plus:SI (mult:SI (match_dup
7) (const_int
2))
3899 (plus:SI (sign_extend:SI (mem:HI (match_dup
9)))
3904 (ltu (unspec [(const_int
0)] CRIS_UNSPEC_CASESI) (match_dup
2))
3906 (label_ref (match_operand
4 "" ""))))
3907 (use (label_ref (match_dup
3)))])]
3911 rtx xlabel = gen_rtx_LABEL_REF (VOIDmode, operands[
3]);
3912 for (i =
5; i <=
10; i++)
3913 operands[i] = gen_reg_rtx (SImode);
3914 operands[
2] = plus_constant (SImode, operands[
2],
1);
3916 /* Don't forget to decorate labels too, for PIC. */
3917 operands[
11] = flag_pic
3918 ? gen_rtx_CONST (Pmode,
3919 gen_rtx_UNSPEC (Pmode, gen_rtvec (
1, xlabel),
3924 (define_expand "casesi"
3925 [(match_operand:SI
0 "general_operand")
3926 (match_operand:SI
1 "const_int_operand")
3927 (match_operand:SI
2 "const_int_operand")
3928 (match_operand
3 "" "")
3929 (match_operand
4 "" "")]
3933 emit_insn (gen_cris_casesi_v32 (operands[
0], operands[
1], operands[
2],
3934 operands[
3], operands[
4]));
3936 emit_insn (gen_cris_casesi_non_v32 (operands[
0], operands[
1], operands[
2],
3937 operands[
3], operands[
4]));
3941 ;; Split-patterns. Some of them have modes unspecified. This
3942 ;; should always be ok; if for no other reason sparc.md has it as
3945 ;; When register_operand is specified for an operand, we can get a
3946 ;; subreg as well (Axis-
990331), so don't just assume that REG_P is true
3947 ;; for a register_operand and that REGNO can be used as is. It is best to
3948 ;; guard with REG_P, unless it is worth it to adjust for the subreg case.
3950 ;; op [rx +
0],ry,rz
3951 ;; The index to rx is optimized into zero, and gone.
3953 ;; First, recognize bound [rx],ry,rz; where [rx] is zero-extended,
3954 ;; and add/sub [rx],ry,rz, with zero or sign-extend on [rx].
3958 ;; Lose if rz=ry or rx=rz.
3959 ;; Call this op-extend-split.
3960 ;; Do not match for V32; the addo and addi shouldn't be split
3964 [(set (match_operand
0 "register_operand" "")
3966 4 "cris_operand_extend_operator"
3967 [(match_operand
1 "register_operand" "")
3969 3 "cris_extend_operator"
3970 [(match_operand
2 "memory_operand" "")])]))]
3972 && REG_P (operands[
0])
3973 && REG_P (operands[
1])
3974 && REGNO (operands[
1]) != REGNO (operands[
0])
3975 && GET_MODE_SIZE (GET_MODE (operands[
0])) <= UNITS_PER_WORD
3976 && REG_P (XEXP (operands[
2],
0))
3977 && REGNO (XEXP (operands[
2],
0)) != REGNO (operands[
0])"
3983 (match_op_dup
3 [(match_dup
2)])]))]
3986 ;; As op-extend-split, but recognize and split op [rz],ry,rz into
3989 ;; Do this for plus or bound only, being commutative operations, since we
3990 ;; have swapped the operands.
3991 ;; Call this op-extend-split-rx=rz
3994 [(set (match_operand
0 "register_operand" "")
3996 4 "cris_plus_or_bound_operator"
3997 [(match_operand
1 "register_operand" "")
3999 3 "cris_extend_operator"
4000 [(match_operand
2 "memory_operand" "")])]))]
4002 && REG_P (operands[
0])
4003 && REG_P (operands[
1])
4004 && REGNO (operands[
1]) != REGNO (operands[
0])
4005 && GET_MODE_SIZE (GET_MODE (operands[
0])) <= UNITS_PER_WORD
4006 && REG_P (XEXP (operands[
2],
0))
4007 && REGNO (XEXP (operands[
2],
0)) == REGNO (operands[
0])"
4009 (match_op_dup
3 [(match_dup
2)]))
4016 ;; As the op-extend-split, but swapped operands, and only for
4017 ;; plus or bound, being the commutative extend-operators. FIXME: Why is
4018 ;; this needed? Is it?
4019 ;; Call this op-extend-split-swapped
4022 [(set (match_operand
0 "register_operand" "")
4024 4 "cris_plus_or_bound_operator"
4026 3 "cris_extend_operator"
4027 [(match_operand
2 "memory_operand" "")])
4028 (match_operand
1 "register_operand" "")]))]
4030 && REG_P (operands[
0])
4031 && REG_P (operands[
1])
4032 && REGNO (operands[
1]) != REGNO (operands[
0])
4033 && GET_MODE_SIZE (GET_MODE (operands[
0])) <= UNITS_PER_WORD
4034 && REG_P (XEXP (operands[
2],
0))
4035 && REGNO (XEXP (operands[
2],
0)) != REGNO (operands[
0])"
4041 (match_op_dup
3 [(match_dup
2)])]))]
4044 ;; As op-extend-split-rx=rz, but swapped operands, only for plus or
4045 ;; bound. Call this op-extend-split-swapped-rx=rz.
4048 [(set (match_operand
0 "register_operand" "")
4050 4 "cris_plus_or_bound_operator"
4052 3 "cris_extend_operator"
4053 [(match_operand
2 "memory_operand" "")])
4054 (match_operand
1 "register_operand" "")]))]
4056 && REG_P (operands[
0])
4057 && REG_P (operands[
1])
4058 && REGNO (operands[
1]) != REGNO (operands[
0])
4059 && GET_MODE_SIZE (GET_MODE (operands[
0])) <= UNITS_PER_WORD
4060 && REG_P (XEXP (operands[
2],
0))
4061 && REGNO (XEXP (operands[
2],
0)) == REGNO (operands[
0])"
4063 (match_op_dup
3 [(match_dup
2)]))
4070 ;; As op-extend-split, but the mem operand is not extended.
4072 ;; op [rx],ry,rz changed into
4075 ;; lose if ry=rz or rx=rz
4076 ;; Call this op-extend.
4079 [(set (match_operand
0 "register_operand" "")
4081 3 "cris_orthogonal_operator"
4082 [(match_operand
1 "register_operand" "")
4083 (match_operand
2 "memory_operand" "")]))]
4085 && REG_P (operands[
0])
4086 && REG_P (operands[
1])
4087 && REGNO (operands[
1]) != REGNO (operands[
0])
4088 && GET_MODE_SIZE (GET_MODE (operands[
0])) <= UNITS_PER_WORD
4089 && REG_P (XEXP (operands[
2],
0))
4090 && REGNO (XEXP (operands[
2],
0)) != REGNO (operands[
0])"
4099 ;; As op-extend-split-rx=rz, non-extended.
4100 ;; Call this op-split-rx=rz
4103 [(set (match_operand
0 "register_operand" "")
4105 3 "cris_commutative_orth_op"
4106 [(match_operand
2 "memory_operand" "")
4107 (match_operand
1 "register_operand" "")]))]
4109 && REG_P (operands[
0])
4110 && REG_P (operands[
1])
4111 && REGNO (operands[
1]) != REGNO (operands[
0])
4112 && GET_MODE_SIZE (GET_MODE (operands[
0])) <= UNITS_PER_WORD
4113 && REG_P (XEXP (operands[
2],
0))
4114 && REGNO (XEXP (operands[
2],
0)) != REGNO (operands[
0])"
4123 ;; As op-extend-split-swapped, nonextended.
4124 ;; Call this op-split-swapped.
4127 [(set (match_operand
0 "register_operand" "")
4129 3 "cris_commutative_orth_op"
4130 [(match_operand
1 "register_operand" "")
4131 (match_operand
2 "memory_operand" "")]))]
4133 && REG_P (operands[
0]) && REG_P (operands[
1])
4134 && REGNO (operands[
1]) != REGNO (operands[
0])
4135 && GET_MODE_SIZE (GET_MODE (operands[
0])) <= UNITS_PER_WORD
4136 && REG_P (XEXP (operands[
2],
0))
4137 && REGNO (XEXP (operands[
2],
0)) == REGNO (operands[
0])"
4146 ;; As op-extend-split-swapped-rx=rz, non-extended.
4147 ;; Call this op-split-swapped-rx=rz.
4150 [(set (match_operand
0 "register_operand" "")
4152 3 "cris_orthogonal_operator"
4153 [(match_operand
2 "memory_operand" "")
4154 (match_operand
1 "register_operand" "")]))]
4156 && REG_P (operands[
0]) && REG_P (operands[
1])
4157 && REGNO (operands[
1]) != REGNO (operands[
0])
4158 && GET_MODE_SIZE (GET_MODE (operands[
0])) <= UNITS_PER_WORD
4159 && REG_P (XEXP (operands[
2],
0))
4160 && REGNO (XEXP (operands[
2],
0)) == REGNO (operands[
0])"
4169 ;; Splits for all cases in side-effect insns where (possibly after reload
4170 ;; and register allocation) rx and ry in [rx=ry+i] are equal.
4172 ;; move.S1 [rx=rx+rz.S2],ry
4176 [(set (match_operand
0 "register_operand" "")
4180 (mult:SI (match_operand:SI
1 "register_operand" "")
4181 (match_operand:SI
2 "const_int_operand" ""))
4182 (match_operand:SI
3 "register_operand" ""))]))
4183 (set (match_operand:SI
4 "register_operand" "")
4184 (plus:SI (mult:SI (match_dup
1)
4187 "REG_P (operands[
3]) && REG_P (operands[
4])
4188 && REGNO (operands[
3]) == REGNO (operands[
4])"
4189 [(set (match_dup
4) (plus:SI (mult:SI (match_dup
1) (match_dup
2))
4191 (set (match_dup
0) (match_dup
5))]
4192 "operands[
5] = replace_equiv_address (operands[
6], operands[
3]);")
4194 ;; move.S1 [rx=rx+i],ry
4198 [(set (match_operand
0 "register_operand" "")
4201 [(plus:SI (match_operand:SI
1 "cris_bdap_operand" "")
4202 (match_operand:SI
2 "cris_bdap_operand" ""))]))
4203 (set (match_operand:SI
3 "register_operand" "")
4204 (plus:SI (match_dup
1)
4206 "(rtx_equal_p (operands[
3], operands[
1])
4207 || rtx_equal_p (operands[
3], operands[
2]))"
4208 [(set (match_dup
3) (plus:SI (match_dup
1) (match_dup
2)))
4209 (set (match_dup
0) (match_dup
4))]
4211 operands[
4] = replace_equiv_address (operands[
5], operands[
3]);
4212 cris_order_for_addsi3 (operands,
1);
4215 ;; move.S1 ry,[rx=rx+rz.S2]
4219 [(set (match_operator
4222 (mult:SI (match_operand:SI
0 "register_operand" "")
4223 (match_operand:SI
1 "const_int_operand" ""))
4224 (match_operand:SI
2 "register_operand" ""))])
4225 (match_operand
3 "register_operand" ""))
4226 (set (match_operand:SI
4 "register_operand" "")
4227 (plus:SI (mult:SI (match_dup
0)
4230 "REG_P (operands[
2]) && REG_P (operands[
4])
4231 && REGNO (operands[
4]) == REGNO (operands[
2])"
4232 [(set (match_dup
4) (plus:SI (mult:SI (match_dup
0) (match_dup
1))
4234 (set (match_dup
5) (match_dup
3))]
4235 "operands[
5] = replace_equiv_address (operands[
6], operands[
4]);")
4237 ;; move.S1 ry,[rx=rx+i]
4241 [(set (match_operator
4243 [(plus:SI (match_operand:SI
0 "cris_bdap_operand" "")
4244 (match_operand:SI
1 "cris_bdap_operand" ""))])
4245 (match_operand
2 "register_operand" ""))
4246 (set (match_operand:SI
3 "register_operand" "")
4247 (plus:SI (match_dup
0)
4249 "(rtx_equal_p (operands[
3], operands[
0])
4250 || rtx_equal_p (operands[
3], operands[
1]))"
4251 [(set (match_dup
3) (plus:SI (match_dup
0) (match_dup
1)))
4252 (set (match_dup
5) (match_dup
2))]
4254 operands[
5] = replace_equiv_address (operands[
6], operands[
3]);
4255 cris_order_for_addsi3 (operands,
0);
4258 ;; clear.[bwd] [rx=rx+rz.S2]
4262 [(set (mem:BWD (plus:SI
4263 (mult:SI (match_operand:SI
0 "register_operand" "")
4264 (match_operand:SI
1 "const_int_operand" ""))
4265 (match_operand:SI
2 "register_operand" "")))
4267 (set (match_operand:SI
3 "register_operand" "")
4268 (plus:SI (mult:SI (match_dup
0)
4271 "REG_P (operands[
2]) && REG_P (operands[
3])
4272 && REGNO (operands[
3]) == REGNO (operands[
2])"
4273 [(set (match_dup
3) (plus:SI (mult:SI (match_dup
0) (match_dup
1))
4275 (set (mem:BWD (match_dup
3)) (const_int
0))]
4278 ;; clear.[bwd] [rx=rx+i]
4283 (plus:SI (match_operand:SI
0 "cris_bdap_operand" "")
4284 (match_operand:SI
1 "cris_bdap_operand" "")))
4286 (set (match_operand:SI
2 "register_operand" "")
4287 (plus:SI (match_dup
0)
4289 "(rtx_equal_p (operands[
0], operands[
2])
4290 || rtx_equal_p (operands[
2], operands[
1]))"
4291 [(set (match_dup
2) (plus:SI (match_dup
0) (match_dup
1)))
4292 (set (mem:BWD (match_dup
2)) (const_int
0))]
4293 "cris_order_for_addsi3 (operands,
0);")
4295 ;; mov(s|u).S1 [rx=rx+rz.S2],ry
4299 [(set (match_operand
0 "register_operand" "")
4301 5 "cris_extend_operator"
4303 (mult:SI (match_operand:SI
1 "register_operand" "")
4304 (match_operand:SI
2 "const_int_operand" ""))
4305 (match_operand:SI
3 "register_operand" "")))]))
4306 (set (match_operand:SI
4 "register_operand" "")
4307 (plus:SI (mult:SI (match_dup
1)
4310 "REG_P (operands[
3])
4311 && REG_P (operands[
4])
4312 && REGNO (operands[
3]) == REGNO (operands[
4])"
4313 [(set (match_dup
4) (plus:SI (mult:SI (match_dup
1) (match_dup
2))
4315 (set (match_dup
0) (match_op_dup
5 [(match_dup
6)]))]
4316 "operands[
6] = replace_equiv_address (XEXP (operands[
5],
0), operands[
4]);")
4318 ;; mov(s|u).S1 [rx=rx+i],ry
4322 [(set (match_operand
0 "register_operand" "")
4324 4 "cris_extend_operator"
4326 (match_operand:SI
1 "cris_bdap_operand" "")
4327 (match_operand:SI
2 "cris_bdap_operand" "")))]))
4328 (set (match_operand:SI
3 "register_operand" "")
4329 (plus:SI (match_dup
1)
4331 "(rtx_equal_p (operands[
1], operands[
3])
4332 || rtx_equal_p (operands[
2], operands[
3]))"
4333 [(set (match_dup
3) (plus:SI (match_dup
1) (match_dup
2)))
4334 (set (match_dup
0) (match_op_dup
4 [(match_dup
5)]))]
4336 operands[
5] = replace_equiv_address (XEXP (operands[
4],
0), operands[
3]);
4337 cris_order_for_addsi3 (operands,
1);
4340 ;; op.S1 [rx=rx+i],ry
4344 [(set (match_operand
0 "register_operand" "")
4346 5 "cris_orthogonal_operator"
4347 [(match_operand
1 "register_operand" "")
4349 (match_operand:SI
2 "cris_bdap_operand" "")
4350 (match_operand:SI
3 "cris_bdap_operand" "")))]))
4351 (set (match_operand:SI
4 "register_operand" "")
4352 (plus:SI (match_dup
2)
4354 "(rtx_equal_p (operands[
4], operands[
2])
4355 || rtx_equal_p (operands[
4], operands[
3]))"
4356 [(set (match_dup
4) (plus:SI (match_dup
2) (match_dup
3)))
4357 (set (match_dup
0) (match_op_dup
5 [(match_dup
1) (match_dup
6)]))]
4359 operands[
6] = replace_equiv_address (XEXP (operands[
5],
1), operands[
4]);
4360 cris_order_for_addsi3 (operands,
2);
4363 ;; op.S1 [rx=rx+rz.S2],ry
4367 [(set (match_operand
0 "register_operand" "")
4369 6 "cris_orthogonal_operator"
4370 [(match_operand
1 "register_operand" "")
4372 (mult:SI (match_operand:SI
2 "register_operand" "")
4373 (match_operand:SI
3 "const_int_operand" ""))
4374 (match_operand:SI
4 "register_operand" "")))]))
4375 (set (match_operand:SI
5 "register_operand" "")
4376 (plus:SI (mult:SI (match_dup
2)
4379 "REG_P (operands[
4])
4380 && REG_P (operands[
5])
4381 && REGNO (operands[
5]) == REGNO (operands[
4])"
4382 [(set (match_dup
5) (plus:SI (mult:SI (match_dup
2) (match_dup
3))
4384 (set (match_dup
0) (match_op_dup
6 [(match_dup
1) (match_dup
7)]))]
4385 "operands[
7] = replace_equiv_address (XEXP (operands[
6],
1), operands[
5]);")
4387 ;; op.S1 [rx=rx+rz.S2],ry (swapped)
4391 [(set (match_operand
0 "register_operand" "")
4393 6 "cris_commutative_orth_op"
4395 (mult:SI (match_operand:SI
2 "register_operand" "")
4396 (match_operand:SI
3 "const_int_operand" ""))
4397 (match_operand:SI
4 "register_operand" "")))
4398 (match_operand
1 "register_operand" "")]))
4399 (set (match_operand:SI
5 "register_operand" "")
4400 (plus:SI (mult:SI (match_dup
2)
4403 "REG_P (operands[
4])
4404 && REG_P (operands[
5])
4405 && REGNO (operands[
5]) == REGNO (operands[
4])"
4406 [(set (match_dup
5) (plus:SI (mult:SI (match_dup
2) (match_dup
3))
4408 (set (match_dup
0) (match_op_dup
6 [(match_dup
7) (match_dup
1)]))]
4409 "operands[
7] = replace_equiv_address (XEXP (operands[
6],
0), operands[
5]);")
4411 ;; op.S1 [rx=rx+i],ry (swapped)
4415 [(set (match_operand
0 "register_operand" "")
4417 5 "cris_commutative_orth_op"
4419 (plus:SI (match_operand:SI
2 "cris_bdap_operand" "")
4420 (match_operand:SI
3 "cris_bdap_operand" "")))
4421 (match_operand
1 "register_operand" "")]))
4422 (set (match_operand:SI
4 "register_operand" "")
4423 (plus:SI (match_dup
2)
4425 "(rtx_equal_p (operands[
4], operands[
2])
4426 || rtx_equal_p (operands[
4], operands[
3]))"
4427 [(set (match_dup
4) (plus:SI (match_dup
2) (match_dup
3)))
4428 (set (match_dup
0) (match_op_dup
5 [(match_dup
6) (match_dup
1)]))]
4430 operands[
6] = replace_equiv_address (XEXP (operands[
5],
0), operands[
4]);
4431 cris_order_for_addsi3 (operands,
2);
4434 ;; op(s|u).S1 [rx=rx+rz.S2],ry
4438 [(set (match_operand
0 "register_operand" "")
4440 6 "cris_operand_extend_operator"
4441 [(match_operand
1 "register_operand" "")
4443 7 "cris_extend_operator"
4445 (mult:SI (match_operand:SI
2 "register_operand" "")
4446 (match_operand:SI
3 "const_int_operand" ""))
4447 (match_operand:SI
4 "register_operand" "")))])]))
4448 (set (match_operand:SI
5 "register_operand" "")
4449 (plus:SI (mult:SI (match_dup
2)
4452 "REG_P (operands[
4])
4453 && REG_P (operands[
5])
4454 && REGNO (operands[
5]) == REGNO (operands[
4])"
4455 [(set (match_dup
5) (plus:SI (mult:SI (match_dup
2) (match_dup
3))
4457 (set (match_dup
0) (match_op_dup
6 [(match_dup
1) (match_dup
8)]))]
4458 "operands[
8] = gen_rtx_fmt_e (GET_CODE (operands[
7]), GET_MODE (operands[
7]),
4459 replace_equiv_address (XEXP (operands[
7],
0),
4462 ;; op(s|u).S1 [rx=rx+i],ry
4466 [(set (match_operand
0 "register_operand" "")
4468 5 "cris_operand_extend_operator"
4469 [(match_operand
1 "register_operand" "")
4471 6 "cris_extend_operator"
4473 (plus:SI (match_operand:SI
2 "cris_bdap_operand" "")
4474 (match_operand:SI
3 "cris_bdap_operand" "")
4476 (set (match_operand:SI
4 "register_operand" "")
4477 (plus:SI (match_dup
2)
4479 "(rtx_equal_p (operands[
4], operands[
2])
4480 || rtx_equal_p (operands[
4], operands[
3]))"
4481 [(set (match_dup
4) (plus:SI (match_dup
2) (match_dup
3)))
4482 (set (match_dup
0) (match_op_dup
5 [(match_dup
1) (match_dup
7)]))]
4484 operands[
7] = gen_rtx_fmt_e (GET_CODE (operands[
6]), GET_MODE (operands[
6]),
4485 replace_equiv_address (XEXP (operands[
6],
0),
4487 cris_order_for_addsi3 (operands,
2);
4490 ;; op(s|u).S1 [rx=rx+rz.S2],ry (swapped, plus or bound)
4494 [(set (match_operand
0 "register_operand" "")
4496 7 "cris_plus_or_bound_operator"
4498 6 "cris_extend_operator"
4500 (mult:SI (match_operand:SI
2 "register_operand" "")
4501 (match_operand:SI
3 "const_int_operand" ""))
4502 (match_operand:SI
4 "register_operand" "")))])
4503 (match_operand
1 "register_operand" "")]))
4504 (set (match_operand:SI
5 "register_operand" "")
4505 (plus:SI (mult:SI (match_dup
2)
4508 "REG_P (operands[
4]) && REG_P (operands[
5])
4509 && REGNO (operands[
5]) == REGNO (operands[
4])"
4510 [(set (match_dup
5) (plus:SI (mult:SI (match_dup
2) (match_dup
3))
4512 (set (match_dup
0) (match_op_dup
6 [(match_dup
8) (match_dup
1)]))]
4513 "operands[
8] = gen_rtx_fmt_e (GET_CODE (operands[
6]), GET_MODE (operands[
6]),
4514 replace_equiv_address (XEXP (operands[
6],
0),
4517 ;; op(s|u).S1 [rx=rx+i],ry (swapped, plus or bound)
4521 [(set (match_operand
0 "register_operand" "")
4523 6 "cris_plus_or_bound_operator"
4525 5 "cris_extend_operator"
4527 (match_operand:SI
2 "cris_bdap_operand" "")
4528 (match_operand:SI
3 "cris_bdap_operand" "")))])
4529 (match_operand
1 "register_operand" "")]))
4530 (set (match_operand:SI
4 "register_operand" "")
4531 (plus:SI (match_dup
2)
4533 "(rtx_equal_p (operands[
4], operands[
2])
4534 || rtx_equal_p (operands[
4], operands[
3]))"
4535 [(set (match_dup
4) (plus:SI (match_dup
2) (match_dup
3)))
4536 (set (match_dup
0) (match_op_dup
6 [(match_dup
7) (match_dup
1)]))]
4538 operands[
7] = gen_rtx_fmt_e (GET_CODE (operands[
5]), GET_MODE (operands[
5]),
4539 replace_equiv_address (XEXP (operands[
5],
0),
4541 cris_order_for_addsi3 (operands,
2);
4544 ;; Splits for addressing prefixes that have no side-effects, so we can
4545 ;; fill a delay slot. Never split if we lose something, though.
4548 ;; move [indirect_ref],rx
4549 ;; where indirect ref = {const, [r+], [r]}, it costs as much as
4550 ;; move indirect_ref,rx
4552 ;; Take care not to allow indirect_ref = register.
4554 ;; We're not allowed to generate copies of registers with different mode
4555 ;; until after reload; copying pseudos upsets reload. CVS as of
4556 ;;
2001-
08-
24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in
4557 ;; cselib_invalidate_regno.
4559 (define_split ; indir_to_reg_split
4560 [(set (match_operand
0 "register_operand" "")
4561 (match_operand
1 "indirect_operand" ""))]
4563 && REG_P (operands[
0])
4564 && GET_MODE_SIZE (GET_MODE (operands[
0])) <= UNITS_PER_WORD
4565 && (MEM_P (XEXP (operands[
1],
0)) || CONSTANT_P (XEXP (operands[
1],
0)))
4566 && REGNO (operands[
0]) < CRIS_LAST_GENERAL_REGISTER"
4567 [(set (match_dup
2) (match_dup
4))
4568 (set (match_dup
0) (match_dup
3))]
4569 "operands[
2] = gen_rtx_REG (Pmode, REGNO (operands[
0]));
4570 operands[
3] = replace_equiv_address (operands[
1], operands[
2]);
4571 operands[
4] = XEXP (operands[
1],
0);")
4573 ;; As the above, but MOVS and MOVU.
4576 [(set (match_operand
0 "register_operand" "")
4578 4 "cris_extend_operator"
4579 [(match_operand
1 "indirect_operand" "")]))]
4581 && REG_P (operands[
0])
4582 && GET_MODE_SIZE (GET_MODE (operands[
0])) <= UNITS_PER_WORD
4583 && (MEM_P (XEXP (operands[
1],
0))
4584 || CONSTANT_P (XEXP (operands[
1],
0)))"
4585 [(set (match_dup
2) (match_dup
5))
4586 (set (match_dup
0) (match_op_dup
4 [(match_dup
3)]))]
4587 "operands[
2] = gen_rtx_REG (Pmode, REGNO (operands[
0]));
4588 operands[
3] = replace_equiv_address (XEXP (operands[
4],
0), operands[
2]);
4589 operands[
5] = XEXP (operands[
1],
0);")
4591 ;; Various peephole optimizations.
4593 ;; Watch out: when you exchange one set of instructions for another, the
4594 ;; condition codes setting must be the same, or you have to CC_INIT or
4595 ;; whatever is appropriate, in the pattern before you emit the
4596 ;; assembly text. This is best done here, not in cris_notice_update_cc,
4597 ;; to keep changes local to their cause.
4599 ;; Do not add patterns that you do not know will be matched.
4600 ;; Please also add a self-contained testcase.
4602 ;; We have trouble with and:s and shifts. Maybe something is broken in
4603 ;; gcc? Or it could just be that bit-field insn expansion is a bit
4604 ;; suboptimal when not having extzv insns.
4605 ;; Testcase for the following four peepholes: gcc.dg/cris-peep2-xsrand.c
4607 (define_peephole2 ; asrandb (peephole casesi+
31)
4608 [(set (match_operand:SI
0 "register_operand" "")
4609 (ashiftrt:SI (match_dup
0)
4610 (match_operand:SI
1 "const_int_operand" "")))
4612 (and:SI (match_dup
0)
4613 (match_operand
2 "const_int_operand" "")))]
4614 "INTVAL (operands[
2]) >
31
4615 && INTVAL (operands[
2]) <
255
4616 && INTVAL (operands[
1]) >
23
4617 /* Check that the and-operation enables us to use logical-shift. */
4618 && (INTVAL (operands[
2])
4619 & ((HOST_WIDE_INT) -
1 << (
32 - INTVAL (operands[
1])))) ==
0"
4620 [(set (match_dup
0) (lshiftrt:SI (match_dup
0) (match_dup
1)))
4621 (set (match_dup
3) (and:QI (match_dup
3) (match_dup
4)))]
4622 ;; FIXME: CC0 is valid except for the M bit.
4624 operands[
3] = gen_rtx_REG (QImode, REGNO (operands[
0]));
4625 operands[
4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[
2]), QImode));
4628 (define_peephole2 ; asrandw (peephole casesi+
32)
4629 [(set (match_operand:SI
0 "register_operand" "")
4630 (ashiftrt:SI (match_dup
0)
4631 (match_operand:SI
1 "const_int_operand" "")))
4633 (and:SI (match_dup
0) (match_operand
2 "const_int_operand" "")))]
4634 "INTVAL (operands[
2]) >
31
4635 && INTVAL (operands[
2]) <
65535
4636 && INTVAL (operands[
2]) !=
255
4637 && INTVAL (operands[
1]) >
15
4638 /* Check that the and-operation enables us to use logical-shift. */
4639 && (INTVAL (operands[
2])
4640 & ((HOST_WIDE_INT) -
1 << (
32 - INTVAL (operands[
1])))) ==
0"
4641 [(set (match_dup
0) (lshiftrt:SI (match_dup
0) (match_dup
1)))
4642 (set (match_dup
3) (and:HI (match_dup
3) (match_dup
4)))]
4643 ;; FIXME: CC0 is valid except for the M bit.
4645 operands[
3] = gen_rtx_REG (HImode, REGNO (operands[
0]));
4646 operands[
4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[
2]), HImode));
4649 (define_peephole2 ; lsrandb (peephole casesi+
33)
4650 [(set (match_operand:SI
0 "register_operand" "")
4651 (lshiftrt:SI (match_dup
0)
4652 (match_operand:SI
1 "const_int_operand" "")))
4654 (and:SI (match_dup
0) (match_operand
2 "const_int_operand" "")))]
4655 "INTVAL (operands[
2]) >
31
4656 && INTVAL (operands[
2]) <
255
4657 && INTVAL (operands[
1]) >
23"
4658 [(set (match_dup
0) (lshiftrt:SI (match_dup
0) (match_dup
1)))
4659 (set (match_dup
3) (and:QI (match_dup
3) (match_dup
4)))]
4660 ;; FIXME: CC0 is valid except for the M bit.
4662 operands[
3] = gen_rtx_REG (QImode, REGNO (operands[
0]));
4663 operands[
4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[
2]), QImode));
4666 (define_peephole2 ; lsrandw (peephole casesi+
34)
4667 [(set (match_operand:SI
0 "register_operand" "")
4668 (lshiftrt:SI (match_dup
0)
4669 (match_operand:SI
1 "const_int_operand" "")))
4671 (and:SI (match_dup
0) (match_operand
2 "const_int_operand" "")))]
4672 "INTVAL (operands[
2]) >
31 && INTVAL (operands[
2]) <
65535
4673 && INTVAL (operands[
2]) !=
255
4674 && INTVAL (operands[
1]) >
15"
4675 [(set (match_dup
0) (lshiftrt:SI (match_dup
0) (match_dup
1)))
4676 (set (match_dup
3) (and:HI (match_dup
3) (match_dup
4)))]
4677 ;; FIXME: CC0 is valid except for the M bit.
4679 operands[
3] = gen_rtx_REG (HImode, REGNO (operands[
0]));
4680 operands[
4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[
2]), HImode));
4688 ;; move [rx=rx+n],ry
4689 ;; when -
128 <= n <=
127.
4690 ;; This will reduce the size of the assembler code for n = [-
128.
.127],
4691 ;; and speed up accordingly. Don't match if the previous insn is
4692 ;; (set rx rz) because that combination is matched by another peephole.
4693 ;; No stable test-case.
4695 (define_peephole2 ; moversideqi (peephole casesi+
35)
4696 [(set (match_operand:SI
0 "register_operand" "")
4697 (plus:SI (match_operand:SI
1 "register_operand" "")
4698 (match_operand:SI
2 "const_int_operand" "")))
4699 (set (match_operand
3 "register_operand" "")
4700 (match_operator
4 "cris_mem_op" [(match_dup
0)]))]
4701 "GET_MODE_SIZE (GET_MODE (operands[
4])) <= UNITS_PER_WORD
4702 && REGNO (operands[
3]) != REGNO (operands[
0])
4703 && (cris_base_p (operands[
1], true) || cris_base_p (operands[
2], true))
4704 && !satisfies_constraint_J (operands[
2])
4705 && !satisfies_constraint_N (operands[
2])
4706 && (INTVAL (operands[
2]) >= -
128 && INTVAL (operands[
2]) <
128)
4707 && TARGET_SIDE_EFFECT_PREFIXES"
4709 [(set (match_dup
3) (match_dup
5))
4710 (set (match_dup
0) (plus:SI (match_dup
1) (match_dup
2)))])]
4711 ;; Checking the previous insn is a bit too awkward for the condition.
4713 rtx prev = prev_nonnote_insn (curr_insn);
4714 if (prev != NULL_RTX)
4716 rtx set = single_set (prev);
4718 && REG_S_P (SET_DEST (set))
4719 && REGNO (SET_DEST (set)) == REGNO (operands[
0])
4720 && REG_S_P (SET_SRC (set)))
4724 = replace_equiv_address (operands[
4],
4725 gen_rtx_PLUS (SImode,
4726 operands[
1], operands[
2]));
4729 ;; Vice versa: move ry,[rx=rx+n]
4731 (define_peephole2 ; movemsideqi (peephole casesi+
36)
4732 [(set (match_operand:SI
0 "register_operand" "")
4733 (plus:SI (match_operand:SI
1 "register_operand" "")
4734 (match_operand:SI
2 "const_int_operand" "")))
4735 (set (match_operator
3 "cris_mem_op" [(match_dup
0)])
4736 (match_operand
4 "register_operand" ""))]
4737 "GET_MODE_SIZE (GET_MODE (operands[
4])) <= UNITS_PER_WORD
4738 && REGNO (operands[
4]) != REGNO (operands[
0])
4739 && (cris_base_p (operands[
1], true) || cris_base_p (operands[
2], true))
4740 && !satisfies_constraint_J (operands[
2])
4741 && !satisfies_constraint_N (operands[
2])
4742 && (INTVAL (operands[
2]) >= -
128 && INTVAL (operands[
2]) <
128)
4743 && TARGET_SIDE_EFFECT_PREFIXES"
4745 [(set (match_dup
5) (match_dup
4))
4746 (set (match_dup
0) (plus:SI (match_dup
1) (match_dup
2)))])]
4748 = replace_equiv_address (operands[
3],
4749 gen_rtx_PLUS (SImode,
4750 operands[
1], operands[
2]));")
4752 ;; As above, change:
4756 ;; op.d [rx=rx+n],ry
4757 ;; Saves when n = [-
128.
.127].
4759 ;; Splitting and joining combinations for side-effect modes are slightly
4760 ;; out of hand. They probably will not save the time they take typing in,
4761 ;; not to mention the bugs that creep in. FIXME: Get rid of as many of
4762 ;; the splits and peepholes as possible.
4763 ;; No stable test-case.
4765 (define_peephole2 ; mover2side (peephole casesi+
37)
4766 [(set (match_operand:SI
0 "register_operand" "")
4767 (plus:SI (match_operand:SI
1 "register_operand" "")
4768 (match_operand:SI
2 "const_int_operand" "")))
4769 (set (match_operand
3 "register_operand" "")
4770 (match_operator
4 "cris_orthogonal_operator"
4773 5 "cris_mem_op" [(match_dup
0)])]))]
4774 ;; FIXME: What about DFmode?
4775 ;; Change to GET_MODE_SIZE (GET_MODE (operands[
3])) <= UNITS_PER_WORD?
4776 "GET_MODE (operands[
3]) != DImode
4777 && REGNO (operands[
0]) != REGNO (operands[
3])
4778 && !satisfies_constraint_J (operands[
2])
4779 && !satisfies_constraint_N (operands[
2])
4780 && INTVAL (operands[
2]) >= -
128
4781 && INTVAL (operands[
2]) <=
127
4782 && TARGET_SIDE_EFFECT_PREFIXES"
4784 [(set (match_dup
3) (match_op_dup
4 [(match_dup
3) (match_dup
6)]))
4785 (set (match_dup
0) (plus:SI (match_dup
1) (match_dup
2)))])]
4787 = replace_equiv_address (operands[
5],
4788 gen_rtx_PLUS (SImode,
4789 operands[
1], operands[
2]));")
4791 ;; Sometimes, for some reason the pattern
4795 ;; will occur. Solve this, and likewise for to-memory.
4796 ;; No stable test-case.
4798 (define_peephole2 ; moverside (peephole casesi+
38)
4799 [(set (match_operand:SI
0 "register_operand" "")
4800 (match_operand:SI
1 "cris_bdap_biap_operand" ""))
4802 (plus:SI (match_operand:SI
2 "cris_bdap_biap_operand" "")
4803 (match_operand:SI
3 "cris_bdap_biap_operand" "")))
4804 (set (match_operand
4 "register_operand" "")
4805 (match_operator
5 "cris_mem_op" [(match_dup
0)]))]
4806 "(rtx_equal_p (operands[
2], operands[
0])
4807 || rtx_equal_p (operands[
3], operands[
0]))
4808 && cris_side_effect_mode_ok (PLUS, operands,
0,
4809 (REG_S_P (operands[
1])
4811 : (rtx_equal_p (operands[
2], operands[
0])
4813 (! REG_S_P (operands[
1])
4815 : (rtx_equal_p (operands[
2], operands[
0])
4819 [(set (match_dup
4) (match_dup
6))
4820 (set (match_dup
0) (plus:SI (match_dup
7) (match_dup
8)))])]
4823 = rtx_equal_p (operands[
2], operands[
0]) ? operands[
3] : operands[
2];
4825 /* Make sure we have canonical RTX so we match the insn pattern -
4826 not a constant in the first operand. We also require the order
4827 (plus reg mem) to match the final pattern. */
4828 if (CONSTANT_P (otherop) || MEM_P (otherop))
4830 operands[
7] = operands[
1];
4831 operands[
8] = otherop;
4835 operands[
7] = otherop;
4836 operands[
8] = operands[
1];
4839 = replace_equiv_address (operands[
5],
4840 gen_rtx_PLUS (SImode,
4841 operands[
7], operands[
8]));
4844 ;; As above but to memory.
4845 ;; FIXME: Split movemside and moverside into variants and prune
4846 ;; the ones that don't trig.
4847 ;; No stable test-case.
4849 (define_peephole2 ; movemside (peephole casesi+
39)
4850 [(set (match_operand:SI
0 "register_operand" "")
4851 (match_operand:SI
1 "cris_bdap_biap_operand" ""))
4853 (plus:SI (match_operand:SI
2 "cris_bdap_biap_operand" "")
4854 (match_operand:SI
3 "cris_bdap_biap_operand" "")))
4855 (set (match_operator
4 "cris_mem_op" [(match_dup
0)])
4856 (match_operand
5 "register_operand" ""))]
4857 "(rtx_equal_p (operands[
2], operands[
0])
4858 || rtx_equal_p (operands[
3], operands[
0]))
4859 && cris_side_effect_mode_ok (PLUS, operands,
0,
4860 (REG_S_P (operands[
1])
4862 : (rtx_equal_p (operands[
2], operands[
0])
4864 (! REG_S_P (operands[
1])
4866 : (rtx_equal_p (operands[
2], operands[
0])
4870 [(set (match_dup
6) (match_dup
5))
4871 (set (match_dup
0) (plus:SI (match_dup
7) (match_dup
8)))])]
4874 = rtx_equal_p (operands[
2], operands[
0]) ? operands[
3] : operands[
2];
4876 /* Make sure we have canonical RTX so we match the insn pattern -
4877 not a constant in the first operand. We also require the order
4878 (plus reg mem) to match the final pattern. */
4879 if (CONSTANT_P (otherop) || MEM_P (otherop))
4881 operands[
7] = operands[
1];
4882 operands[
8] = otherop;
4886 operands[
7] = otherop;
4887 operands[
8] = operands[
1];
4890 = replace_equiv_address (operands[
4],
4891 gen_rtx_PLUS (SImode,
4892 operands[
7], operands[
8]));
4895 ;; Another spotted bad code:
4898 ;; No stable test-case.
4900 (define_peephole2 ; movei (peephole casesi+
42)
4901 [(set (match_operand:SI
0 "register_operand" "")
4902 (match_operand:SI
1 "register_operand" ""))
4903 (set (match_operand
2 "register_operand" "")
4904 (match_operator
3 "cris_mem_op" [(match_dup
0)]))]
4905 "REGNO (operands[
0]) == REGNO (operands[
2])
4906 && (REGNO_REG_CLASS (REGNO (operands[
0]))
4907 == REGNO_REG_CLASS (REGNO (operands[
1])))
4908 && GET_MODE_SIZE (GET_MODE (operands[
2])) <= UNITS_PER_WORD"
4909 [(set (match_dup
2) (match_dup
4))]
4910 "operands[
4] = replace_equiv_address (operands[
3], operands[
1]);")
4912 ;; move.d [r10+
16],r9
4915 ;; and.d [r10+
16],r12,r9
4916 ;; With generalization of the operation, the size and the addressing mode.
4917 ;; This seems to be the result of a quirk in register allocation
4918 ;; missing the three-operand cases when having different predicates.
4919 ;; Maybe that it matters that it is a commutative operation.
4920 ;; This pattern helps that situation, but there's still the increased
4921 ;; register pressure.
4922 ;; Note that adding the noncommutative variant did not show any matches
4923 ;; in ipps and cc1, so it's not here.
4924 ;; No stable test-case.
4926 (define_peephole2 ; op3 (peephole casesi+
44)
4927 [(set (match_operand
0 "register_operand" "")
4931 (match_operand:SI
1 "cris_bdap_biap_operand" "")
4932 (match_operand:SI
2 "cris_bdap_biap_operand" ""))]))
4935 5 "cris_commutative_orth_op"
4936 [(match_operand
3 "register_operand" "")
4937 (match_operand
4 "register_operand" "")]))]
4938 "(rtx_equal_p (operands[
3], operands[
0])
4939 || rtx_equal_p (operands[
4], operands[
0]))
4940 && ! rtx_equal_p (operands[
3], operands[
4])
4941 && (REG_S_P (operands[
1]) || REG_S_P (operands[
2]))
4942 && GET_MODE_SIZE (GET_MODE (operands[
0])) <= UNITS_PER_WORD"
4943 [(set (match_dup
0) (match_op_dup
5 [(match_dup
7) (match_dup
6)]))]
4945 = rtx_equal_p (operands[
3], operands[
0]) ? operands[
4] : operands[
3];")
4947 ;; There seems to be no other way to make GCC (including
4.8/trunk at
4948 ;; r186932) optimally reload an instruction that looks like
4949 ;; and.d reg_or_mem,const_32__65535,other_reg
4950 ;; where other_reg is the destination.
4952 ;; movu.[bw] reg_or_mem,reg_32
4953 ;; and.[bw] trunc_int_for_mode([bw], const_32__65535),reg_32 ;; or andq
4954 ;; but it turns into:
4955 ;; move.d reg_or_mem,reg_32
4956 ;; and.d const_32__65535,reg_32
4957 ;; Fix it with these two peephole2's.
4958 ;; Testcases: gcc.dg/cris-peep2-andu1.c gcc.dg/cris-peep2-andu2.c
4960 (define_peephole2 ; andu (casesi+
45)
4961 [(set (match_operand:SI
0 "register_operand" "")
4962 (match_operand:SI
1 "nonimmediate_operand" ""))
4963 (set (match_operand:SI
2 "register_operand" "")
4964 (and:SI (match_dup
0)
4965 (match_operand:SI
3 "const_int_operand" "")))]
4966 ;; Since the size of the memory access could be made different here,
4967 ;; don't do this for a mem-volatile access.
4968 "REGNO (operands[
2]) == REGNO (operands[
0])
4969 && INTVAL (operands[
3]) <=
65535 && INTVAL (operands[
3]) >=
0
4970 && !satisfies_constraint_I (operands[
3])
4971 && !side_effects_p (operands[
1])
4972 && (!REG_P (operands[
1])
4973 || REGNO (operands[
1]) <= CRIS_LAST_GENERAL_REGISTER)"
4974 ;; FIXME: CC0 valid except for M (i.e. CC_NOT_NEGATIVE).
4975 [(set (match_dup
0) (match_dup
4))
4976 (set (match_dup
5) (match_dup
6))]
4978 enum machine_mode zmode = INTVAL (operands[
3]) <=
255 ? QImode : HImode;
4979 enum machine_mode amode
4980 = satisfies_constraint_O (operands[
3]) ? SImode : zmode;
4982 = (REG_S_P (operands[
1])
4983 ? gen_rtx_REG (zmode, REGNO (operands[
1]))
4984 : adjust_address (operands[
1], zmode,
0));
4986 = gen_rtx_ZERO_EXTEND (SImode, op1);
4987 operands[
5] = gen_rtx_REG (amode, REGNO (operands[
0]));
4989 = gen_rtx_AND (amode, gen_rtx_REG (amode, REGNO (operands[
0])),
4990 GEN_INT (trunc_int_for_mode (INTVAL (operands[
3]),
4992 ? QImode : amode)));
4995 ;; Since r186861, gcc.dg/cris-peep2-andu2.c trigs this pattern, with which
5002 ;; Only do this for values fitting the quick immediate operand.
5003 (define_peephole2 ; andqu (casesi+
46)
5004 [(set (match_operand:SI
0 "register_operand")
5005 (match_operand:SI
1 "const_int_operand"))
5007 (and:SI (match_dup
0) (match_operand:SI
2 "nonimmediate_operand")))]
5008 ;; Since the size of the memory access will be made different here,
5009 ;; don't do this for a volatile access or a post-incremented address.
5010 "satisfies_constraint_O (operands[
1])
5011 && !side_effects_p (operands[
2])
5012 && !reg_overlap_mentioned_p (operands[
0], operands[
2])"
5013 [(set (match_dup
0) (match_dup
3))
5014 (set (match_dup
0) (and:SI (match_dup
0) (match_dup
4)))]
5016 enum machine_mode zmode = INTVAL (operands[
2]) <=
255 ? QImode : HImode;
5018 = (REG_S_P (operands[
2])
5019 ? gen_rtx_REG (zmode, REGNO (operands[
2]))
5020 : adjust_address (operands[
2], zmode,
0));
5021 operands[
3] = gen_rtx_ZERO_EXTEND (SImode, op1);
5022 operands[
4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[
1]), QImode));
5025 ;; Try and avoid GOTPLT reads escaping a call: transform them into
5026 ;; PLT. Curiously (but thankfully), peepholes for instructions
5027 ;; *without side-effects* that just feed a call (or call_value) are
5028 ;; not matched neither in a build or test-suite, so those patterns are
5031 ;; A "normal" move where we don't check the consumer.
5033 (define_peephole2 ; gotplt-to-plt
5035 (match_operand:SI
0 "register_operand" "")
5039 (reg:SI CRIS_GOT_REGNUM)
5041 (unspec:SI [(match_operand:SI
2 "cris_general_operand_or_symbol" "")]
5042 CRIS_UNSPEC_PLTGOTREAD)))]))]
5044 && cris_valid_pic_const (XEXP (XEXP (operands[
1],
0),
1), true)
5045 && REGNO_REG_CLASS (REGNO (operands[
0])) == REGNO_REG_CLASS (
0)"
5046 [(set (match_dup
0) (const:SI (unspec:SI [(match_dup
2)] CRIS_UNSPEC_PLT_GOTREL)))
5047 (set (match_dup
0) (plus:SI (match_dup
0) (reg:SI CRIS_GOT_REGNUM)))]
5050 ;; And one set with a side-effect getting the PLTGOT offset.
5051 ;; First call and call_value variants.
5053 (define_peephole2 ; gotplt-to-plt-side-call
5056 (match_operand:SI
0 "register_operand" "")
5060 (reg:SI CRIS_GOT_REGNUM)
5062 (unspec:SI [(match_operand:SI
5063 2 "cris_general_operand_or_symbol" "")]
5064 CRIS_UNSPEC_PLTGOTREAD)))]))
5065 (set (match_operand:SI
3 "register_operand" "")
5066 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5068 (unspec:SI [(match_dup
2)] CRIS_UNSPEC_PLTGOTREAD))))])
5069 (parallel [(call (mem:QI (match_dup
0))
5070 (match_operand
4 "" ""))
5071 (clobber (reg:SI CRIS_SRP_REGNUM))])]
5073 && cris_valid_pic_const (XEXP (XEXP (operands[
1],
0),
1), true)
5074 && peep2_reg_dead_p (
2, operands[
0])"
5075 [(parallel [(call (mem:QI (match_dup
1))
5077 (clobber (reg:SI CRIS_SRP_REGNUM))
5079 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5081 (unspec:SI [(match_dup
2)]
5082 CRIS_UNSPEC_PLTGOTREAD))))])]
5085 (define_peephole2 ; gotplt-to-plt-side-call-value
5088 (match_operand:SI
0 "register_operand" "")
5092 (reg:SI CRIS_GOT_REGNUM)
5094 (unspec:SI [(match_operand:SI
5095 2 "cris_general_operand_or_symbol" "")]
5096 CRIS_UNSPEC_PLTGOTREAD)))]))
5097 (set (match_operand:SI
3 "register_operand" "")
5098 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5100 (unspec:SI [(match_dup
2)] CRIS_UNSPEC_PLTGOTREAD))))])
5101 (parallel [(set (match_operand
5 "" "")
5102 (call (mem:QI (match_dup
0))
5103 (match_operand
4 "" "")))
5104 (clobber (reg:SI CRIS_SRP_REGNUM))])]
5106 && cris_valid_pic_const (XEXP (XEXP (operands[
1],
0),
1), true)
5107 && peep2_reg_dead_p (
2, operands[
0])"
5108 [(parallel [(set (match_dup
5)
5109 (call (mem:QI (match_dup
1))
5111 (clobber (reg:SI CRIS_SRP_REGNUM))
5113 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5115 (unspec:SI [(match_dup
2)]
5116 CRIS_UNSPEC_PLTGOTREAD))))])]
5119 (define_peephole2 ; gotplt-to-plt-side
5122 (match_operand:SI
0 "register_operand" "")
5126 (reg:SI CRIS_GOT_REGNUM)
5128 (unspec:SI [(match_operand:SI
5129 2 "cris_general_operand_or_symbol" "")]
5130 CRIS_UNSPEC_PLTGOTREAD)))]))
5131 (set (match_operand:SI
3 "register_operand" "")
5132 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5134 (unspec:SI [(match_dup
2)] CRIS_UNSPEC_PLTGOTREAD))))])]
5136 && cris_valid_pic_const (XEXP (XEXP (operands[
1],
0),
1), true)
5137 && REGNO_REG_CLASS (REGNO (operands[
0])) == REGNO_REG_CLASS (
0)"
5139 (const:SI (unspec:SI [(match_dup
2)] CRIS_UNSPEC_PLTGOTREAD)))
5140 (set (match_dup
3) (plus:SI (match_dup
3) (reg:SI CRIS_GOT_REGNUM)))
5142 (const:SI (unspec:SI [(match_dup
2)] CRIS_UNSPEC_PLT_GOTREL)))
5143 (set (match_dup
0) (plus:SI (match_dup
0) (reg:SI CRIS_GOT_REGNUM)))]
5148 ;; comment-start: ";; "
5149 ;; eval: (set-syntax-table (copy-sequence (syntax-table)))
5150 ;; eval: (modify-syntax-entry ?[ "(]")
5151 ;; eval: (modify-syntax-entry ?] ")[")
5152 ;; eval: (modify-syntax-entry ?{ "(}")
5153 ;; eval: (modify-syntax-entry ?} "){")
5154 ;; eval: (setq indent-tabs-mode t)