gcc/config/bfin/bfin.h

   1 /* Definitions for the Blackfin port.
   2    Copyright (C) 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
   3    Contributed by Analog Devices.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef _BFIN_CONFIG
  22 #define _BFIN_CONFIG
  23
  24 #define OBJECT_FORMAT_ELF
  25
  26 #define BRT 1
  27 #define BRF 0
  28
  29 /* CPU type.  */
  30 typedef enum bfin_cpu_type
  31 {
  32   BFIN_CPU_UNKNOWN,
  33   BFIN_CPU_BF512,
  34   BFIN_CPU_BF514,
  35   BFIN_CPU_BF516,
  36   BFIN_CPU_BF518,
  37   BFIN_CPU_BF522,
  38   BFIN_CPU_BF523,
  39   BFIN_CPU_BF524,
  40   BFIN_CPU_BF525,
  41   BFIN_CPU_BF526,
  42   BFIN_CPU_BF527,
  43   BFIN_CPU_BF531,
  44   BFIN_CPU_BF532,
  45   BFIN_CPU_BF533,
  46   BFIN_CPU_BF534,
  47   BFIN_CPU_BF536,
  48   BFIN_CPU_BF537,
  49   BFIN_CPU_BF538,
  50   BFIN_CPU_BF539,
  51   BFIN_CPU_BF542,
  52   BFIN_CPU_BF542M,
  53   BFIN_CPU_BF544,
  54   BFIN_CPU_BF544M,
  55   BFIN_CPU_BF547,
  56   BFIN_CPU_BF547M,
  57   BFIN_CPU_BF548,
  58   BFIN_CPU_BF548M,
  59   BFIN_CPU_BF549,
  60   BFIN_CPU_BF549M,
  61   BFIN_CPU_BF561
  62 } bfin_cpu_t;
  63
  64 /* Value of -mcpu= */
  65 extern bfin_cpu_t bfin_cpu_type;
  66
  67 /* Value of -msi-revision= */
  68 extern int bfin_si_revision;
  69
  70 extern unsigned int bfin_workarounds;
  71
  72 /* Print subsidiary information on the compiler version in use.  */
  73 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)")
  74
  75 /* Run-time compilation parameters selecting different hardware subsets.  */
  76
  77 extern int target_flags;
  78
  79 /* Predefinition in the preprocessor for this target machine */
  80 #ifndef TARGET_CPU_CPP_BUILTINS
  81 #define TARGET_CPU_CPP_BUILTINS()               \
  82   do                                            \
  83     {                                           \
  84       builtin_define_std ("bfin");              \
  85       builtin_define_std ("BFIN");              \
  86       builtin_define ("__ADSPBLACKFIN__");      \
  87       builtin_define ("__ADSPLPBLACKFIN__");    \
  88                                                 \
  89       switch (bfin_cpu_type)                    \
  90         {                                       \
  91         case BFIN_CPU_BF512:                    \
  92           builtin_define ("__ADSPBF512__");     \
  93           builtin_define ("__ADSPBF51x__");     \
  94           break;                                \
  95         case BFIN_CPU_BF514:                    \
  96           builtin_define ("__ADSPBF514__");     \
  97           builtin_define ("__ADSPBF51x__");     \
  98           break;                                \
  99         case BFIN_CPU_BF516:                    \
 100           builtin_define ("__ADSPBF516__");     \
 101           builtin_define ("__ADSPBF51x__");     \
 102           break;                                \
 103         case BFIN_CPU_BF518:                    \
 104           builtin_define ("__ADSPBF518__");     \
 105           builtin_define ("__ADSPBF51x__");     \
 106           break;                                \
 107         case BFIN_CPU_BF522:                    \
 108           builtin_define ("__ADSPBF522__");     \
 109           builtin_define ("__ADSPBF52x__");     \
 110           break;                                \
 111         case BFIN_CPU_BF523:                    \
 112           builtin_define ("__ADSPBF523__");     \
 113           builtin_define ("__ADSPBF52x__");     \
 114           break;                                \
 115         case BFIN_CPU_BF524:                    \
 116           builtin_define ("__ADSPBF524__");     \
 117           builtin_define ("__ADSPBF52x__");     \
 118           break;                                \
 119         case BFIN_CPU_BF525:                    \
 120           builtin_define ("__ADSPBF525__");     \
 121           builtin_define ("__ADSPBF52x__");     \
 122           break;                                \
 123         case BFIN_CPU_BF526:                    \
 124           builtin_define ("__ADSPBF526__");     \
 125           builtin_define ("__ADSPBF52x__");     \
 126           break;                                \
 127         case BFIN_CPU_BF527:                    \
 128           builtin_define ("__ADSPBF527__");     \
 129           builtin_define ("__ADSPBF52x__");     \
 130           break;                                \
 131         case BFIN_CPU_BF531:                    \
 132           builtin_define ("__ADSPBF531__");     \
 133           break;                                \
 134         case BFIN_CPU_BF532:                    \
 135           builtin_define ("__ADSPBF532__");     \
 136           break;                                \
 137         case BFIN_CPU_BF533:                    \
 138           builtin_define ("__ADSPBF533__");     \
 139           break;                                \
 140         case BFIN_CPU_BF534:                    \
 141           builtin_define ("__ADSPBF534__");     \
 142           break;                                \
 143         case BFIN_CPU_BF536:                    \
 144           builtin_define ("__ADSPBF536__");     \
 145           break;                                \
 146         case BFIN_CPU_BF537:                    \
 147           builtin_define ("__ADSPBF537__");     \
 148           break;                                \
 149         case BFIN_CPU_BF538:                    \
 150           builtin_define ("__ADSPBF538__");     \
 151           break;                                \
 152         case BFIN_CPU_BF539:                    \
 153           builtin_define ("__ADSPBF539__");     \
 154           break;                                \
 155         case BFIN_CPU_BF542M:                   \
 156           builtin_define ("__ADSPBF542M__");    \
 157         case BFIN_CPU_BF542:                    \
 158           builtin_define ("__ADSPBF542__");     \
 159           builtin_define ("__ADSPBF54x__");     \
 160           break;                                \
 161         case BFIN_CPU_BF544M:                   \
 162           builtin_define ("__ADSPBF544M__");    \
 163         case BFIN_CPU_BF544:                    \
 164           builtin_define ("__ADSPBF544__");     \
 165           builtin_define ("__ADSPBF54x__");     \
 166           break;                                \
 167         case BFIN_CPU_BF547M:                   \
 168           builtin_define ("__ADSPBF547M__");    \
 169         case BFIN_CPU_BF547:                    \
 170           builtin_define ("__ADSPBF547__");     \
 171           builtin_define ("__ADSPBF54x__");     \
 172           break;                                \
 173         case BFIN_CPU_BF548M:                   \
 174           builtin_define ("__ADSPBF548M__");    \
 175         case BFIN_CPU_BF548:                    \
 176           builtin_define ("__ADSPBF548__");     \
 177           builtin_define ("__ADSPBF54x__");     \
 178           break;                                \
 179         case BFIN_CPU_BF549M:                   \
 180           builtin_define ("__ADSPBF549M__");    \
 181         case BFIN_CPU_BF549:                    \
 182           builtin_define ("__ADSPBF549__");     \
 183           builtin_define ("__ADSPBF54x__");     \
 184           break;                                \
 185         case BFIN_CPU_BF561:                    \
 186           builtin_define ("__ADSPBF561__");     \
 187           break;                                \
 188         }                                       \
 189                                                 \
 190       if (bfin_si_revision != -1)               \
 191         {                                       \
 192           /* space of 0xnnnn and a NUL */       \
 193           char *buf = XALLOCAVEC (char, 7);     \
 194                                                 \
 195           sprintf (buf, "0x%04x", bfin_si_revision);                    \
 196           builtin_define_with_value ("__SILICON_REVISION__", buf, 0);   \
 197         }                                                               \
 198                                                                         \
 199       if (bfin_workarounds)                                             \
 200         builtin_define ("__WORKAROUNDS_ENABLED");                       \
 201       if (ENABLE_WA_SPECULATIVE_LOADS)                                  \
 202         builtin_define ("__WORKAROUND_SPECULATIVE_LOADS");              \
 203       if (ENABLE_WA_SPECULATIVE_SYNCS)                                  \
 204         builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS");              \
 205       if (ENABLE_WA_INDIRECT_CALLS)                                     \
 206         builtin_define ("__WORKAROUND_INDIRECT_CALLS");                 \
 207       if (ENABLE_WA_RETS)                                               \
 208         builtin_define ("__WORKAROUND_RETS");                           \
 209                                                 \
 210       if (TARGET_FDPIC)                         \
 211         {                                       \
 212           builtin_define ("__BFIN_FDPIC__");    \
 213           builtin_define ("__FDPIC__");         \
 214         }                                       \
 215       if (TARGET_ID_SHARED_LIBRARY              \
 216           && !TARGET_SEP_DATA)                  \
 217         builtin_define ("__ID_SHARED_LIB__");   \
 218       if (flag_no_builtin)                      \
 219         builtin_define ("__NO_BUILTIN");        \
 220       if (TARGET_MULTICORE)                     \
 221         builtin_define ("__BFIN_MULTICORE");    \
 222       if (TARGET_COREA)                         \
 223         builtin_define ("__BFIN_COREA");        \
 224       if (TARGET_COREB)                         \
 225         builtin_define ("__BFIN_COREB");        \
 226       if (TARGET_SDRAM)                         \
 227         builtin_define ("__BFIN_SDRAM");        \
 228     }                                           \
 229   while (0)
 230 #endif
 231
 232 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS   "\
 233  %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \
 234  %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
 235             %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \
 236 "
 237 #ifndef SUBTARGET_DRIVER_SELF_SPECS
 238 # define SUBTARGET_DRIVER_SELF_SPECS
 239 #endif
 240
 241 #define LINK_GCC_C_SEQUENCE_SPEC "\
 242   %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \
 243 "
 244
 245 /* A C string constant that tells the GCC driver program options to pass to
 246    the assembler.  It can also specify how to translate options you give to GNU
 247    CC into options for GCC to pass to the assembler.  See the file `sun3.h'
 248    for an example of this.
 249
 250    Do not define this macro if it does not need to do anything.
 251
 252    Defined in svr4.h.  */
 253 #undef  ASM_SPEC
 254 #define ASM_SPEC "\
 255 %{G*} %{v} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \
 256     %{mno-fdpic:-mnopic} %{mfdpic}"
 257
 258 #define LINK_SPEC "\
 259 %{h*} %{v:-V} \
 260 %{b} \
 261 %{mfdpic:-melf32bfinfd -z text} \
 262 %{static:-dn -Bstatic} \
 263 %{shared:-G -Bdynamic} \
 264 %{symbolic:-Bsymbolic} \
 265 %{G*} \
 266 %{YP,*} \
 267 %{Qy:} %{!Qn:-Qy} \
 268 -init __init -fini __fini "
 269
 270 /* Generate DSP instructions, like DSP halfword loads */
 271 #define TARGET_DSP                      (1)
 272
 273 #define TARGET_DEFAULT 0
 274
 275 /* Maximum number of library ids we permit */
 276 #define MAX_LIBRARY_ID 255
 277
 278 extern const char *bfin_library_id_string;
 279
 280 /* Sometimes certain combinations of command options do not make
 281    sense on a particular target machine.  You can define a macro
 282    `OVERRIDE_OPTIONS' to take account of this.  This macro, if
 283    defined, is executed once just after all the command options have
 284    been parsed.
 285
 286    Don't use this macro to turn on various extra optimizations for
 287    `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
 288
 289 #define OVERRIDE_OPTIONS override_options ()
 290
 291 #define FUNCTION_MODE    SImode
 292 #define Pmode            SImode
 293
 294 /* store-condition-codes instructions store 0 for false
 295    This is the value stored for true.  */
 296 #define STORE_FLAG_VALUE 1
 297
 298 /* Define this if pushing a word on the stack
 299    makes the stack pointer a smaller address.  */
 300 #define STACK_GROWS_DOWNWARD
 301
 302 #define STACK_PUSH_CODE PRE_DEC
 303
 304 /* Define this to nonzero if the nominal address of the stack frame
 305    is at the high-address end of the local variables;
 306    that is, each additional local variable allocated
 307    goes at a more negative offset in the frame.  */
 308 #define FRAME_GROWS_DOWNWARD 1
 309
 310 /* We define a dummy ARGP register; the parameters start at offset 0 from
 311    it. */
 312 #define FIRST_PARM_OFFSET(DECL) 0
 313
 314 /* Offset within stack frame to start allocating local variables at.
 315    If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
 316    first local allocated.  Otherwise, it is the offset to the BEGINNING
 317    of the first local allocated.  */
 318 #define STARTING_FRAME_OFFSET 0
 319
 320 /* Register to use for pushing function arguments.  */
 321 #define STACK_POINTER_REGNUM REG_P6
 322
 323 /* Base register for access to local variables of the function.  */
 324 #define FRAME_POINTER_REGNUM REG_P7
 325
 326 /* A dummy register that will be eliminated to either FP or SP.  */
 327 #define ARG_POINTER_REGNUM REG_ARGP
 328
 329 /* `PIC_OFFSET_TABLE_REGNUM'
 330      The register number of the register used to address a table of
 331      static data addresses in memory.  In some cases this register is
 332      defined by a processor's "application binary interface" (ABI).
 333      When this macro is defined, RTL is generated for this register
 334      once, as with the stack pointer and frame pointer registers.  If
 335      this macro is not defined, it is up to the machine-dependent files
 336      to allocate such a register (if necessary). */
 337 #define PIC_OFFSET_TABLE_REGNUM (REG_P5)
 338
 339 #define FDPIC_FPTR_REGNO REG_P1
 340 #define FDPIC_REGNO REG_P3
 341 #define OUR_FDPIC_REG   get_hard_reg_initial_val (SImode, FDPIC_REGNO)
 342
 343 /* A static chain register for nested functions.  We need to use a
 344    call-clobbered register for this.  */
 345 #define STATIC_CHAIN_REGNUM REG_P2
 346
 347 /* Define this if functions should assume that stack space has been
 348    allocated for arguments even when their values are passed in
 349    registers.
 350
 351    The value of this macro is the size, in bytes, of the area reserved for
 352    arguments passed in registers.
 353
 354    This space can either be allocated by the caller or be a part of the
 355    machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
 356    says which.  */
 357 #define FIXED_STACK_AREA 12
 358 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA
 359
 360 /* Define this if the above stack space is to be considered part of the
 361  * space allocated by the caller.  */
 362 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 363
 364 /* Define this if the maximum size of all the outgoing args is to be
 365    accumulated and pushed during the prologue.  The amount can be
 366    found in the variable crtl->outgoing_args_size. */
 367 #define ACCUMULATE_OUTGOING_ARGS 1
 368
 369 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */
 370
 371 /* If defined, a C expression to compute the alignment for a local
 372    variable.  TYPE is the data type, and ALIGN is the alignment that
 373    the object would ordinarily have.  The value of this macro is used
 374    instead of that alignment to align the object.
 375
 376    If this macro is not defined, then ALIGN is used.
 377
 378    One use of this macro is to increase alignment of medium-size
 379    data to make it all fit in fewer cache lines.  */
 380
 381 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
 382
 383 /* Make strings word-aligned so strcpy from constants will be faster.  */
 384 #define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
 385   (TREE_CODE (EXP) == STRING_CST        \
 386    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
 387
 388 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
 389 \f
 390 /* Definitions for register eliminations.
 391
 392    This is an array of structures.  Each structure initializes one pair
 393    of eliminable registers.  The "from" register number is given first,
 394    followed by "to".  Eliminations of the same "from" register are listed
 395    in order of preference.
 396
 397    There are two registers that can always be eliminated on the i386.
 398    The frame pointer and the arg pointer can be replaced by either the
 399    hard frame pointer or to the stack pointer, depending upon the
 400    circumstances.  The hard frame pointer is not used before reload and
 401    so it is not eligible for elimination.  */
 402
 403 #define ELIMINABLE_REGS                         \
 404 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},   \
 405  { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},   \
 406  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \
 407
 408 /* Define the offset between two registers, one to be eliminated, and the other
 409    its replacement, at the start of a routine.  */
 410
 411 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 412   ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO)))
 413 \f
 414 /* This processor has
 415    8 data register for doing arithmetic
 416    8  pointer register for doing addressing, including
 417       1  stack pointer P6
 418       1  frame pointer P7
 419    4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3)
 420    1  condition code flag register CC
 421    5  return address registers RETS/I/X/N/E
 422    1  arithmetic status register (ASTAT).  */
 423
 424 #define FIRST_PSEUDO_REGISTER 50
 425
 426 #define D_REGNO_P(X) ((X) <= REG_R7)
 427 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7)
 428 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3)
 429 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X))
 430 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3)
 431 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X)))
 432 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X)))
 433 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X)))
 434 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X)))
 435
 436 #define REGISTER_NAMES { \
 437   "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
 438   "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \
 439   "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \
 440   "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \
 441   "A0", "A1", \
 442   "CC", \
 443   "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \
 444   "ARGP", \
 445   "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \
 446 }
 447
 448 #define SHORT_REGISTER_NAMES { \
 449         "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \
 450         "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \
 451         "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \
 452         "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", }
 453
 454 #define HIGH_REGISTER_NAMES { \
 455         "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \
 456         "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \
 457         "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \
 458         "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", }
 459
 460 #define DREGS_PAIR_NAMES { \
 461   "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0,  }
 462
 463 #define BYTE_REGISTER_NAMES { \
 464   "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",  }
 465
 466
 467 /* 1 for registers that have pervasive standard uses
 468    and are not available for the register allocator.  */
 469
 470 #define FIXED_REGISTERS \
 471 /*r0 r1 r2 r3 r4 r5 r6 r7   p0 p1 p2 p3 p4 p5 p6 p7 */ \
 472 { 0, 0, 0, 0, 0, 0, 0, 0,   0, 0, 0, 0, 0, 0, 1, 0,    \
 473 /*i0 i1 i2 i3 b0 b1 b2 b3   l0 l1 l2 l3 m0 m1 m2 m3 */ \
 474   0, 0, 0, 0, 0, 0, 0, 0,   1, 1, 1, 1, 0, 0, 0, 0,    \
 475 /*a0 a1 cc rets/i/x/n/e     astat seqstat usp argp lt0/1 lc0/1 */ \
 476   0, 0, 0, 1, 1, 1, 1, 1,   1, 1, 1, 1, 1, 1, 1, 1,    \
 477 /*lb0/1 */ \
 478   1, 1  \
 479 }
 480
 481 /* 1 for registers not available across function calls.
 482    These must include the FIXED_REGISTERS and also any
 483    registers that can be used without being saved.
 484    The latter must include the registers where values are returned
 485    and the register where structure-value addresses are passed.
 486    Aside from that, you can include as many other registers as you like.  */
 487
 488 #define CALL_USED_REGISTERS \
 489 /*r0 r1 r2 r3 r4 r5 r6 r7   p0 p1 p2 p3 p4 p5 p6 p7 */ \
 490 { 1, 1, 1, 1, 0, 0, 0, 0,   1, 1, 1, 0, 0, 0, 1, 0, \
 491 /*i0 i1 i2 i3 b0 b1 b2 b3   l0 l1 l2 l3 m0 m1 m2 m3 */ \
 492   1, 1, 1, 1, 1, 1, 1, 1,   1, 1, 1, 1, 1, 1, 1, 1,   \
 493 /*a0 a1 cc rets/i/x/n/e     astat seqstat usp argp lt0/1 lc0/1 */ \
 494   1, 1, 1, 1, 1, 1, 1, 1,   1, 1, 1, 1, 1, 1, 1, 1, \
 495 /*lb0/1 */ \
 496   1, 1  \
 497 }
 498
 499 /* Order in which to allocate registers.  Each register must be
 500    listed once, even those in FIXED_REGISTERS.  List frame pointer
 501    late and fixed registers last.  Note that, in general, we prefer
 502    registers listed in CALL_USED_REGISTERS, keeping the others
 503    available for storage of persistent values. */
 504
 505 #define REG_ALLOC_ORDER \
 506 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \
 507   REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \
 508   REG_A0, REG_A1, \
 509   REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \
 510   REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \
 511   REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE,               \
 512   REG_ASTAT, REG_SEQSTAT, REG_USP,                                \
 513   REG_CC, REG_ARGP,                                               \
 514   REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1            \
 515 }
 516
 517 /* Macro to conditionally modify fixed_regs/call_used_regs.  */
 518 #define CONDITIONAL_REGISTER_USAGE                      \
 519   {                                                     \
 520     conditional_register_usage();                       \
 521     if (TARGET_FDPIC)                                   \
 522       call_used_regs[FDPIC_REGNO] = 1;                  \
 523     if (!TARGET_FDPIC && flag_pic)                      \
 524       {                                                 \
 525         fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;        \
 526         call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;    \
 527       }                                                 \
 528   }
 529
 530 /* Define the classes of registers for register constraints in the
 531    machine description.  Also define ranges of constants.
 532
 533    One of the classes must always be named ALL_REGS and include all hard regs.
 534    If there is more than one class, another class must be named NO_REGS
 535    and contain no registers.
 536
 537    The name GENERAL_REGS must be the name of a class (or an alias for
 538    another name such as ALL_REGS).  This is the class of registers
 539    that is allowed by "g" or "r" in a register constraint.
 540    Also, registers outside this class are allocated only when
 541    instructions express preferences for them.
 542
 543    The classes must be numbered in nondecreasing order; that is,
 544    a larger-numbered class must never be contained completely
 545    in a smaller-numbered class.
 546
 547    For any two classes, it is very desirable that there be another
 548    class that represents their union. */
 549
 550
 551 enum reg_class
 552 {
 553   NO_REGS,
 554   IREGS,
 555   BREGS,
 556   LREGS,
 557   MREGS,
 558   CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form.  See Automatic Circular Buffering.  */
 559   DAGREGS,
 560   EVEN_AREGS,
 561   ODD_AREGS,
 562   AREGS,
 563   CCREGS,
 564   EVEN_DREGS,
 565   ODD_DREGS,
 566   D0REGS,
 567   D1REGS,
 568   D2REGS,
 569   D3REGS,
 570   D4REGS,
 571   D5REGS,
 572   D6REGS,
 573   D7REGS,
 574   DREGS,
 575   P0REGS,
 576   FDPIC_REGS,
 577   FDPIC_FPTR_REGS,
 578   PREGS_CLOBBERED,
 579   PREGS,
 580   IPREGS,
 581   DPREGS,
 582   MOST_REGS,
 583   LT_REGS,
 584   LC_REGS,
 585   LB_REGS,
 586   PROLOGUE_REGS,
 587   NON_A_CC_REGS,
 588   ALL_REGS, LIM_REG_CLASSES
 589 };
 590
 591 #define N_REG_CLASSES ((int)LIM_REG_CLASSES)
 592
 593 #define GENERAL_REGS DPREGS
 594
 595 /* Give names of register classes as strings for dump file.   */
 596
 597 #define REG_CLASS_NAMES \
 598 {  "NO_REGS",           \
 599    "IREGS",             \
 600    "BREGS",             \
 601    "LREGS",             \
 602    "MREGS",             \
 603    "CIRCREGS",          \
 604    "DAGREGS",           \
 605    "EVEN_AREGS",        \
 606    "ODD_AREGS",         \
 607    "AREGS",             \
 608    "CCREGS",            \
 609    "EVEN_DREGS",        \
 610    "ODD_DREGS",         \
 611    "D0REGS",            \
 612    "D1REGS",            \
 613    "D2REGS",            \
 614    "D3REGS",            \
 615    "D4REGS",            \
 616    "D5REGS",            \
 617    "D6REGS",            \
 618    "D7REGS",            \
 619    "DREGS",             \
 620    "P0REGS",            \
 621    "FDPIC_REGS",        \
 622    "FDPIC_FPTR_REGS",   \
 623    "PREGS_CLOBBERED",   \
 624    "PREGS",             \
 625    "IPREGS",            \
 626    "DPREGS",            \
 627    "MOST_REGS",         \
 628    "LT_REGS",           \
 629    "LC_REGS",           \
 630    "LB_REGS",           \
 631    "PROLOGUE_REGS",     \
 632    "NON_A_CC_REGS",     \
 633    "ALL_REGS" }
 634
 635 /* An initializer containing the contents of the register classes, as integers
 636    which are bit masks.  The Nth integer specifies the contents of class N.
 637    The way the integer MASK is interpreted is that register R is in the class
 638    if `MASK & (1 << R)' is 1.
 639
 640    When the machine has more than 32 registers, an integer does not suffice.
 641    Then the integers are replaced by sub-initializers, braced groupings
 642    containing several integers.  Each sub-initializer must be suitable as an
 643    initializer for the type `HARD_REG_SET' which is defined in
 644    `hard-reg-set.h'.  */
 645
 646 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS.  We use
 647    MOST_REGS as the union of DPREGS and DAGREGS.  */
 648
 649 #define REG_CLASS_CONTENTS \
 650     /* 31 - 0       63-32   */ \
 651 {   { 0x00000000,    0 },               /* NO_REGS */   \
 652     { 0x000f0000,    0 },               /* IREGS */     \
 653     { 0x00f00000,    0 },               /* BREGS */             \
 654     { 0x0f000000,    0 },               /* LREGS */     \
 655     { 0xf0000000,    0 },               /* MREGS */   \
 656     { 0x0fff0000,    0 },               /* CIRCREGS */   \
 657     { 0xffff0000,    0 },               /* DAGREGS */   \
 658     { 0x00000000,    0x1 },             /* EVEN_AREGS */   \
 659     { 0x00000000,    0x2 },             /* ODD_AREGS */   \
 660     { 0x00000000,    0x3 },             /* AREGS */   \
 661     { 0x00000000,    0x4 },             /* CCREGS */  \
 662     { 0x00000055,    0 },               /* EVEN_DREGS */   \
 663     { 0x000000aa,    0 },               /* ODD_DREGS */   \
 664     { 0x00000001,    0 },               /* D0REGS */   \
 665     { 0x00000002,    0 },               /* D1REGS */   \
 666     { 0x00000004,    0 },               /* D2REGS */   \
 667     { 0x00000008,    0 },               /* D3REGS */   \
 668     { 0x00000010,    0 },               /* D4REGS */   \
 669     { 0x00000020,    0 },               /* D5REGS */   \
 670     { 0x00000040,    0 },               /* D6REGS */   \
 671     { 0x00000080,    0 },               /* D7REGS */   \
 672     { 0x000000ff,    0 },               /* DREGS */   \
 673     { 0x00000100,    0x000 },           /* P0REGS */   \
 674     { 0x00000800,    0x000 },           /* FDPIC_REGS */   \
 675     { 0x00000200,    0x000 },           /* FDPIC_FPTR_REGS */   \
 676     { 0x00004700,    0x800 },           /* PREGS_CLOBBERED */   \
 677     { 0x0000ff00,    0x800 },           /* PREGS */   \
 678     { 0x000fff00,    0x800 },           /* IPREGS */    \
 679     { 0x0000ffff,    0x800 },           /* DPREGS */   \
 680     { 0xffffffff,    0x800 },           /* MOST_REGS */\
 681     { 0x00000000,    0x3000 },          /* LT_REGS */\
 682     { 0x00000000,    0xc000 },          /* LC_REGS */\
 683     { 0x00000000,    0x30000 },         /* LB_REGS */\
 684     { 0x00000000,    0x3f7f8 },         /* PROLOGUE_REGS */\
 685     { 0xffffffff,    0x3fff8 },         /* NON_A_CC_REGS */\
 686     { 0xffffffff,    0x3ffff }}         /* ALL_REGS */
 687
 688 #define IREG_POSSIBLE_P(OUTER)                               \
 689   ((OUTER) == POST_INC || (OUTER) == PRE_INC                 \
 690    || (OUTER) == POST_DEC || (OUTER) == PRE_DEC              \
 691    || (OUTER) == MEM || (OUTER) == ADDRESS)
 692
 693 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX)                    \
 694   ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
 695
 696 #define INDEX_REG_CLASS         PREGS
 697
 698 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX)       \
 699   (P_REGNO_P (X) || (X) == REG_ARGP                             \
 700    || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode              \
 701        && I_REGNO_P (X)))
 702
 703 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX)    \
 704   ((X) >= FIRST_PSEUDO_REGISTER                                 \
 705    || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
 706
 707 #ifdef REG_OK_STRICT
 708 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
 709   REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
 710 #else
 711 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \
 712   REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
 713 #endif
 714
 715 #define REGNO_OK_FOR_INDEX_P(X)   0
 716
 717 /* The same information, inverted:
 718    Return the class number of the smallest class containing
 719    reg number REGNO.  This could be a conditional expression
 720    or could index an array.  */
 721
 722 #define REGNO_REG_CLASS(REGNO) \
 723 ((REGNO) == REG_R0 ? D0REGS                             \
 724  : (REGNO) == REG_R1 ? D1REGS                           \
 725  : (REGNO) == REG_R2 ? D2REGS                           \
 726  : (REGNO) == REG_R3 ? D3REGS                           \
 727  : (REGNO) == REG_R4 ? D4REGS                           \
 728  : (REGNO) == REG_R5 ? D5REGS                           \
 729  : (REGNO) == REG_R6 ? D6REGS                           \
 730  : (REGNO) == REG_R7 ? D7REGS                           \
 731  : (REGNO) == REG_P0 ? P0REGS                           \
 732  : (REGNO) < REG_I0 ? PREGS                             \
 733  : (REGNO) == REG_ARGP ? PREGS                          \
 734  : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS       \
 735  : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS       \
 736  : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS       \
 737  : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS       \
 738  : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS       \
 739  : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS   \
 740  : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS   \
 741  : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS   \
 742  : (REGNO) == REG_CC ? CCREGS                           \
 743  : (REGNO) >= REG_RETS ? PROLOGUE_REGS                  \
 744  : NO_REGS)
 745
 746 /* The following macro defines cover classes for Integrated Register
 747    Allocator.  Cover classes is a set of non-intersected register
 748    classes covering all hard registers used for register allocation
 749    purpose.  Any move between two registers of a cover class should be
 750    cheaper than load or store of the registers.  The macro value is
 751    array of register classes with LIM_REG_CLASSES used as the end
 752    marker.  */
 753
 754 #define IRA_COVER_CLASSES                               \
 755 {                                                       \
 756     MOST_REGS, AREGS, CCREGS, LIM_REG_CLASSES           \
 757 }
 758
 759 /* When defined, the compiler allows registers explicitly used in the
 760    rtl to be used as spill registers but prevents the compiler from
 761    extending the lifetime of these registers. */
 762 #define SMALL_REGISTER_CLASSES 1
 763
 764 #define CLASS_LIKELY_SPILLED_P(CLASS) \
 765     ((CLASS) == PREGS_CLOBBERED \
 766      || (CLASS) == PROLOGUE_REGS \
 767      || (CLASS) == P0REGS \
 768      || (CLASS) == D0REGS \
 769      || (CLASS) == D1REGS \
 770      || (CLASS) == D2REGS \
 771      || (CLASS) == CCREGS)
 772
 773 /* Do not allow to store a value in REG_CC for any mode */
 774 /* Do not allow to store value in pregs if mode is not SI*/
 775 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
 776
 777 /* Return the maximum number of consecutive registers
 778    needed to represent mode MODE in a register of class CLASS.  */
 779 #define CLASS_MAX_NREGS(CLASS, MODE)                                    \
 780   ((MODE) == V2PDImode && (CLASS) == AREGS ? 2                          \
 781    : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 782
 783 #define HARD_REGNO_NREGS(REGNO, MODE) \
 784   ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1    \
 785    : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
 786    : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
 787
 788 /* A C expression that is nonzero if hard register TO can be
 789    considered for use as a rename register for FROM register */
 790 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
 791
 792 /* A C expression that is nonzero if it is desirable to choose
 793    register allocation so as to avoid move instructions between a
 794    value of mode MODE1 and a value of mode MODE2.
 795
 796    If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
 797    MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
 798    MODE2)' must be zero. */
 799 #define MODES_TIEABLE_P(MODE1, MODE2)                   \
 800  ((MODE1) == (MODE2)                                    \
 801   || ((GET_MODE_CLASS (MODE1) == MODE_INT               \
 802        || GET_MODE_CLASS (MODE1) == MODE_FLOAT)         \
 803       && (GET_MODE_CLASS (MODE2) == MODE_INT            \
 804           || GET_MODE_CLASS (MODE2) == MODE_FLOAT)      \
 805       && (MODE1) != BImode && (MODE2) != BImode         \
 806       && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD        \
 807       && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD))
 808
 809 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
 810    A C expression that places additional restrictions on the register
 811    class to use when it is necessary to copy value X into a register
 812    in class CLASS.  The value is a register class; perhaps CLASS, or
 813    perhaps another, smaller class.  */
 814 #define PREFERRED_RELOAD_CLASS(X, CLASS)                \
 815   (GET_CODE (X) == POST_INC                             \
 816    || GET_CODE (X) == POST_DEC                          \
 817    || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS))
 818
 819 /* Function Calling Conventions. */
 820
 821 /* The type of the current function; normal functions are of type
 822    SUBROUTINE.  */
 823 typedef enum {
 824   SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER
 825 } e_funkind;
 826 #define FUNCTION_RETURN_REGISTERS { REG_RETS, REG_RETI, REG_RETX, REG_RETN }
 827
 828 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 }
 829
 830 /* Flags for the call/call_value rtl operations set up by function_arg */
 831 #define CALL_NORMAL             0x00000000      /* no special processing */
 832 #define CALL_LONG               0x00000001      /* always call indirect */
 833 #define CALL_SHORT              0x00000002      /* always call by symbol */
 834
 835 typedef struct {
 836   int words;                    /* # words passed so far */
 837   int nregs;                    /* # registers available for passing */
 838   int *arg_regs;                /* array of register -1 terminated */
 839   int call_cookie;              /* Do special things for this call */
 840 } CUMULATIVE_ARGS;
 841
 842 /* Define where to put the arguments to a function.
 843    Value is zero to push the argument on the stack,
 844    or a hard register in which to store the argument.
 845
 846    MODE is the argument's machine mode.
 847    TYPE is the data type of the argument (as a tree).
 848     This is null for libcalls where that information may
 849     not be available.
 850    CUM is a variable of type CUMULATIVE_ARGS which gives info about
 851     the preceding args and about the function being called.
 852    NAMED is nonzero if this argument is a named parameter
 853     (otherwise it is an extra parameter matching an ellipsis).  */
 854
 855 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
 856   (function_arg (&CUM, MODE, TYPE, NAMED))
 857
 858 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO)
 859
 860
 861 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 862    for a call to a function whose data type is FNTYPE.
 863    For a library call, FNTYPE is 0.  */
 864 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \
 865   (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
 866
 867 /* Update the data in CUM to advance over an argument
 868    of mode MODE and data type TYPE.
 869    (TYPE is null for libcalls where that information may not be available.)  */
 870 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)    \
 871   (function_arg_advance (&CUM, MODE, TYPE, NAMED))
 872
 873 #define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0
 874
 875 /* Define how to find the value returned by a function.
 876    VALTYPE is the data type of the value (as a tree).
 877    If the precise function being called is known, FUNC is its FUNCTION_DECL;
 878    otherwise, FUNC is 0.
 879 */
 880
 881 #define VALUE_REGNO(MODE) (REG_R0)
 882
 883 #define FUNCTION_VALUE(VALTYPE, FUNC)           \
 884   gen_rtx_REG (TYPE_MODE (VALTYPE),             \
 885                VALUE_REGNO(TYPE_MODE(VALTYPE)))
 886
 887 /* Define how to find the value returned by a library function
 888    assuming the value has mode MODE.  */
 889
 890 #define LIBCALL_VALUE(MODE)  gen_rtx_REG (MODE, VALUE_REGNO(MODE))
 891
 892 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0)
 893
 894 #define DEFAULT_PCC_STRUCT_RETURN 0
 895
 896 /* Before the prologue, the return address is in the RETS register.  */
 897 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS)
 898
 899 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT)
 900
 901 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS)
 902
 903 /* Call instructions don't modify the stack pointer on the Blackfin.  */
 904 #define INCOMING_FRAME_SP_OFFSET 0
 905
 906 /* Describe how we implement __builtin_eh_return.  */
 907 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
 908 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, REG_P2)
 909 #define EH_RETURN_HANDLER_RTX \
 910     gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD))
 911
 912 /* Addressing Modes */
 913
 914 /* Recognize any constant value that is a valid address.  */
 915 #define CONSTANT_ADDRESS_P(X)   (CONSTANT_P (X))
 916
 917 /* Nonzero if the constant value X is a legitimate general operand.
 918    symbol_ref are not legitimate and will be put into constant pool.
 919    See force_const_mem().
 920    If -mno-pool, all constants are legitimate.
 921  */
 922 #define LEGITIMATE_CONSTANT_P(X) bfin_legitimate_constant_p (X)
 923
 924 /*   A number, the maximum number of registers that can appear in a
 925      valid memory address.  Note that it is up to you to specify a
 926      value equal to the maximum number that `TARGET_LEGITIMATE_ADDRESS_P'
 927      would ever accept. */
 928 #define MAX_REGS_PER_ADDRESS 1
 929
 930 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \
 931       (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode)
 932
 933 #define HAVE_POST_INCREMENT 1
 934 #define HAVE_POST_DECREMENT 1
 935 #define HAVE_PRE_DECREMENT  1
 936
 937 /* `LEGITIMATE_PIC_OPERAND_P (X)'
 938      A C expression that is nonzero if X is a legitimate immediate
 939      operand on the target machine when generating position independent
 940      code.  You can assume that X satisfies `CONSTANT_P', so you need
 941      not check this.  You can also assume FLAG_PIC is true, so you need
 942      not check it either.  You need not define this macro if all
 943      constants (including `SYMBOL_REF') can be immediate operands when
 944      generating position independent code. */
 945 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
 946
 947 #define SYMBOLIC_CONST(X)       \
 948 (GET_CODE (X) == SYMBOL_REF                                             \
 949  || GET_CODE (X) == LABEL_REF                                           \
 950  || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
 951
 952 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
 953
 954 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
 955    is done just by pretending it is already truncated.  */
 956 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 957
 958 /* Max number of bytes we can move from memory to memory
 959    in one reasonably fast instruction.  */
 960 #define MOVE_MAX UNITS_PER_WORD
 961
 962 /* If a memory-to-memory move would take MOVE_RATIO or more simple
 963    move-instruction pairs, we will do a movmem or libcall instead.  */
 964
 965 #define MOVE_RATIO(speed) 5
 966
 967 /* STORAGE LAYOUT: target machine storage layout
 968    Define this macro as a C expression which is nonzero if accessing
 969    less than a word of memory (i.e. a `char' or a `short') is no
 970    faster than accessing a word of memory, i.e., if such access
 971    require more than one instruction or if there is no difference in
 972    cost between byte and (aligned) word loads.
 973
 974    When this macro is not defined, the compiler will access a field by
 975    finding the smallest containing object; when it is defined, a
 976    fullword load will be used if alignment permits.  Unless bytes
 977    accesses are faster than word accesses, using word accesses is
 978    preferable since it may eliminate subsequent memory access if
 979    subsequent accesses occur to other fields in the same word of the
 980    structure, but to different bytes.  */
 981 #define SLOW_BYTE_ACCESS  0
 982 #define SLOW_SHORT_ACCESS 0
 983
 984 /* Define this if most significant bit is lowest numbered
 985    in instructions that operate on numbered bit-fields. */
 986 #define BITS_BIG_ENDIAN  0
 987
 988 /* Define this if most significant byte of a word is the lowest numbered.
 989    We can't access bytes but if we could we would in the Big Endian order. */
 990 #define BYTES_BIG_ENDIAN 0
 991
 992 /* Define this if most significant word of a multiword number is numbered. */
 993 #define WORDS_BIG_ENDIAN 0
 994
 995 /* number of bits in an addressable storage unit */
 996 #define BITS_PER_UNIT 8
 997
 998 /* Width in bits of a "word", which is the contents of a machine register.
 999    Note that this is not necessarily the width of data type `int';
1000    if using 16-bit ints on a 68000, this would still be 32.
1001    But on a machine with 16-bit registers, this would be 16.  */
1002 #define BITS_PER_WORD 32
1003
1004 /* Width of a word, in units (bytes).  */
1005 #define UNITS_PER_WORD 4
1006
1007 /* Width in bits of a pointer.
1008    See also the macro `Pmode1' defined below.  */
1009 #define POINTER_SIZE 32
1010
1011 /* Allocation boundary (in *bits*) for storing pointers in memory.  */
1012 #define POINTER_BOUNDARY 32
1013
1014 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
1015 #define PARM_BOUNDARY 32
1016
1017 /* Boundary (in *bits*) on which stack pointer should be aligned.  */
1018 #define STACK_BOUNDARY 32
1019
1020 /* Allocation boundary (in *bits*) for the code of a function.  */
1021 #define FUNCTION_BOUNDARY 32
1022
1023 /* Alignment of field after `int : 0' in a structure.  */
1024 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
1025
1026 /* No data type wants to be aligned rounder than this.  */
1027 #define BIGGEST_ALIGNMENT 32
1028
1029 /* Define this if move instructions will actually fail to work
1030    when given unaligned data.  */
1031 #define STRICT_ALIGNMENT 1
1032
1033 /* (shell-command "rm c-decl.o stor-layout.o")
1034  *  never define PCC_BITFIELD_TYPE_MATTERS
1035  *  really cause some alignment problem
1036  */
1037
1038 #define UNITS_PER_FLOAT  ((FLOAT_TYPE_SIZE  + BITS_PER_UNIT - 1) / \
1039                            BITS_PER_UNIT)
1040
1041 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \
1042                            BITS_PER_UNIT)
1043
1044
1045 /* what is the 'type' of size_t */
1046 #define SIZE_TYPE "long unsigned int"
1047
1048 /* Define this as 1 if `char' should by default be signed; else as 0.  */
1049 #define DEFAULT_SIGNED_CHAR 1
1050 #define FLOAT_TYPE_SIZE BITS_PER_WORD
1051 #define SHORT_TYPE_SIZE 16
1052 #define CHAR_TYPE_SIZE  8
1053 #define INT_TYPE_SIZE   32
1054 #define LONG_TYPE_SIZE  32
1055 #define LONG_LONG_TYPE_SIZE 64
1056
1057 /* Note: Fix this to depend on target switch. -- lev */
1058
1059 /* Note: Try to implement double and force long double. -- tonyko
1060  * #define __DOUBLES_ARE_FLOATS__
1061  * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE
1062  * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
1063  * #define DOUBLES_ARE_FLOATS 1
1064  */
1065
1066 #define DOUBLE_TYPE_SIZE        64
1067 #define LONG_DOUBLE_TYPE_SIZE   64
1068
1069 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)'
1070      A macro to update M and UNSIGNEDP when an object whose type is
1071      TYPE and which has the specified mode and signedness is to be
1072      stored in a register.  This macro is only called when TYPE is a
1073      scalar type.
1074
1075      On most RISC machines, which only have operations that operate on
1076      a full register, define this macro to set M to `word_mode' if M is
1077      an integer mode narrower than `BITS_PER_WORD'.  In most cases,
1078      only integer modes should be widened because wider-precision
1079      floating-point operations are usually more expensive than their
1080      narrower counterparts.
1081
1082      For most machines, the macro definition does not change UNSIGNEDP.
1083      However, some machines, have instructions that preferentially
1084      handle either signed or unsigned quantities of certain modes.  For
1085      example, on the DEC Alpha, 32-bit loads from memory and 32-bit add
1086      instructions sign-extend the result to 64 bits.  On such machines,
1087      set UNSIGNEDP according to which kind of extension is more
1088      efficient.
1089
1090      Do not define this macro if it would never modify M.*/
1091
1092 #define BFIN_PROMOTE_MODE_P(MODE) \
1093     (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT   \
1094       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)
1095
1096 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
1097   if (BFIN_PROMOTE_MODE_P(MODE))                \
1098     {                                           \
1099       if (MODE == QImode)                       \
1100         UNSIGNEDP = 1;                          \
1101       else if (MODE == HImode)                  \
1102         UNSIGNEDP = 0;                          \
1103       (MODE) = SImode;                          \
1104     }
1105
1106 /* Describing Relative Costs of Operations */
1107
1108 /* Do not put function addr into constant pool */
1109 #define NO_FUNCTION_CSE 1
1110
1111 /* A C expression for the cost of moving data from a register in class FROM to
1112    one in class TO.  The classes are expressed using the enumeration values
1113    such as `GENERAL_REGS'.  A value of 2 is the default; other values are
1114    interpreted relative to that.
1115
1116    It is not required that the cost always equal 2 when FROM is the same as TO;
1117    on some machines it is expensive to move between registers if they are not
1118    general registers.  */
1119
1120 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1121    bfin_register_move_cost ((MODE), (CLASS1), (CLASS2))
1122
1123 /* A C expression for the cost of moving data of mode M between a
1124    register and memory.  A value of 2 is the default; this cost is
1125    relative to those in `REGISTER_MOVE_COST'.
1126
1127    If moving between registers and memory is more expensive than
1128    between two registers, you should define this macro to express the
1129    relative cost.  */
1130
1131 #define MEMORY_MOVE_COST(MODE, CLASS, IN)       \
1132   bfin_memory_move_cost ((MODE), (CLASS), (IN))
1133
1134 /* Specify the machine mode that this machine uses
1135    for the index in the tablejump instruction.  */
1136 #define CASE_VECTOR_MODE SImode
1137
1138 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
1139
1140 /* Define if operations between registers always perform the operation
1141    on the full register even if a narrower mode is specified.
1142 #define WORD_REGISTER_OPERATIONS
1143 */
1144
1145 /* Evaluates to true if A and B are mac flags that can be used
1146    together in a single multiply insn.  That is the case if they are
1147    both the same flag not involving M, or if one is a combination of
1148    the other with M.  */
1149 #define MACFLAGS_MATCH_P(A, B) \
1150  ((A) == (B) \
1151   || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \
1152   || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \
1153   || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \
1154   || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS))
1155
1156 /* Switch into a generic section.  */
1157 #define TARGET_ASM_NAMED_SECTION  default_elf_asm_named_section
1158
1159 #define PRINT_OPERAND(FILE, RTX, CODE)   print_operand (FILE, RTX, CODE)
1160 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX)
1161
1162 typedef enum sections {
1163     CODE_DIR,
1164     DATA_DIR,
1165     LAST_SECT_NM
1166 } SECT_ENUM_T;
1167
1168 typedef enum directives {
1169     LONG_CONST_DIR,
1170     SHORT_CONST_DIR,
1171     BYTE_CONST_DIR,
1172     SPACE_DIR,
1173     INIT_DIR,
1174     LAST_DIR_NM
1175 } DIR_ENUM_T;
1176
1177 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR)   \
1178   ((C) == ';'                                   \
1179    || ((C) == '|' && (STR)[1] == '|'))
1180
1181 #define TEXT_SECTION_ASM_OP ".text;"
1182 #define DATA_SECTION_ASM_OP ".data;"
1183
1184 #define ASM_APP_ON  ""
1185 #define ASM_APP_OFF ""
1186
1187 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \
1188   do {  fputs (".global ", FILE);               \
1189         assemble_name (FILE, NAME);             \
1190         fputc (';',FILE);                       \
1191         fputc ('\n',FILE);                      \
1192       } while (0)
1193
1194 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1195   do {                                  \
1196     fputs (".type ", FILE);             \
1197     assemble_name (FILE, NAME);         \
1198     fputs (", STT_FUNC", FILE);         \
1199     fputc (';',FILE);                   \
1200     fputc ('\n',FILE);                  \
1201     ASM_OUTPUT_LABEL(FILE, NAME);       \
1202   } while (0)
1203
1204 #define ASM_OUTPUT_LABEL(FILE, NAME)    \
1205   do {  assemble_name (FILE, NAME);             \
1206         fputs (":\n",FILE);                     \
1207       } while (0)
1208
1209 #define ASM_OUTPUT_LABELREF(FILE,NAME)  \
1210     do {  fprintf (FILE, "_%s", NAME); \
1211         } while (0)
1212
1213 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)            \
1214 do { char __buf[256];                                   \
1215      fprintf (FILE, "\t.dd\t");                         \
1216      ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE);   \
1217      assemble_name (FILE, __buf);                       \
1218      fputc (';', FILE);                                 \
1219      fputc ('\n', FILE);                                \
1220    } while (0)
1221
1222 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1223     MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)
1224
1225 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL)           \
1226     do {                                                        \
1227         char __buf[256];                                        \
1228         fprintf (FILE, "\t.dd\t");                              \
1229         ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE);        \
1230         assemble_name (FILE, __buf);                            \
1231         fputs (" - ", FILE);                                    \
1232         ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL);          \
1233         assemble_name (FILE, __buf);                            \
1234         fputc (';', FILE);                                      \
1235         fputc ('\n', FILE);                                     \
1236     } while (0)
1237
1238 #define ASM_OUTPUT_ALIGN(FILE,LOG)                              \
1239     do {                                                        \
1240       if ((LOG) != 0)                                           \
1241         fprintf (FILE, "\t.align %d\n", 1 << (LOG));            \
1242     } while (0)
1243
1244 #define ASM_OUTPUT_SKIP(FILE,SIZE)              \
1245     do {                                        \
1246         asm_output_skip (FILE, SIZE);           \
1247     } while (0)
1248
1249 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED)     \
1250 do {                                            \
1251     switch_to_section (data_section);                           \
1252     if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2);  \
1253     ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE);               \
1254     ASM_OUTPUT_LABEL (FILE, NAME);                              \
1255     fprintf (FILE, "%s %ld;\n", ASM_SPACE,                      \
1256              (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1);     \
1257 } while (0)
1258
1259 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)    \
1260      do {                                               \
1261         ASM_GLOBALIZE_LABEL1(FILE,NAME);                \
1262         ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1263
1264 #define ASM_COMMENT_START "//"
1265
1266 #define FUNCTION_PROFILER(FILE, LABELNO)        \
1267   do {                                          \
1268     fprintf (FILE, "\tCALL __mcount;\n");       \
1269   } while(0)
1270
1271 #undef NO_PROFILE_COUNTERS
1272 #define NO_PROFILE_COUNTERS 1
1273
1274 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO])
1275 #define ASM_OUTPUT_REG_POP(FILE, REGNO)  fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO])
1276
1277 extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx;
1278
1279 /* This works for GAS and some other assemblers.  */
1280 #define SET_ASM_OP              ".set "
1281
1282 /* DBX register number for a given compiler register number */
1283 #define DBX_REGISTER_NUMBER(REGNO)  (REGNO)
1284
1285 #define SIZE_ASM_OP     "\t.size\t"
1286
1287 extern int splitting_for_sched, splitting_loops;
1288
1289 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!')
1290
1291 #ifndef TARGET_SUPPORTS_SYNC_CALLS
1292 #define TARGET_SUPPORTS_SYNC_CALLS 0
1293 #endif
1294
1295 #endif /*  _BFIN_CONFIG */