gcc/config/arm/cortex-a9.md

   1 ;; ARM Cortex-A9 pipeline description
   2 ;; Copyright (C) 2008-2020 Free Software Foundation, Inc.
   3 ;; Originally written by CodeSourcery for VFP.
   4 ;;
   5 ;; Rewritten by Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
   6 ;; Integer Pipeline description contributed by ARM Ltd.
   7 ;; VFP Pipeline description rewritten and contributed by ARM Ltd.
   8
   9 ;; This file is part of GCC.
  10 ;;
  11 ;; GCC is free software; you can redistribute it and/or modify it
  12 ;; under the terms of the GNU General Public License as published by
  13 ;; the Free Software Foundation; either version 3, or (at your option)
  14 ;; any later version.
  15 ;;
  16 ;; GCC is distributed in the hope that it will be useful, but
  17 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19 ;; General Public License for more details.
  20 ;;
  21 ;; You should have received a copy of the GNU General Public License
  22 ;; along with GCC; see the file COPYING3.  If not see
  23 ;; <http://www.gnu.org/licenses/>.
  24
  25 (define_automaton "cortex_a9")
  26
  27 ;; The Cortex-A9 core is modelled as a dual issue pipeline that has
  28 ;; the following components.
  29 ;; 1. 1 Load Store Pipeline.
  30 ;; 2. P0 / main pipeline for data processing instructions.
  31 ;; 3. P1 / Dual pipeline for Data processing instructions.
  32 ;; 4. MAC pipeline for multiply as well as multiply
  33 ;;    and accumulate instructions.
  34 ;; 5. 1 VFP and an optional Neon unit.
  35 ;; The Load/Store, VFP and Neon issue pipeline are multiplexed.
  36 ;; The P0 / main pipeline and M1 stage of the MAC pipeline are
  37 ;;   multiplexed.
  38 ;; The P1 / dual pipeline and M2 stage of the MAC pipeline are
  39 ;;   multiplexed.
  40 ;; There are only 4 integer register read ports and hence at any point of
  41 ;; time we can't have issue down the E1 and the E2 ports unless
  42 ;; of course there are bypass paths that get exercised.
  43 ;; Both P0 and P1 have 2 stages E1 and E2.
  44 ;; Data processing instructions issue to E1 or E2 depending on
  45 ;; whether they have an early shift or not.
  46
  47 (define_cpu_unit "ca9_issue_vfp_neon, cortex_a9_ls" "cortex_a9")
  48 (define_cpu_unit "cortex_a9_p0_e1, cortex_a9_p0_e2" "cortex_a9")
  49 (define_cpu_unit "cortex_a9_p1_e1, cortex_a9_p1_e2" "cortex_a9")
  50 (define_cpu_unit "cortex_a9_p0_wb, cortex_a9_p1_wb" "cortex_a9")
  51 (define_cpu_unit "cortex_a9_mac_m1, cortex_a9_mac_m2" "cortex_a9")
  52 (define_cpu_unit "cortex_a9_branch, cortex_a9_issue_branch" "cortex_a9")
  53
  54 (define_reservation "cortex_a9_p0_default" "cortex_a9_p0_e2, cortex_a9_p0_wb")
  55 (define_reservation "cortex_a9_p1_default" "cortex_a9_p1_e2, cortex_a9_p1_wb")
  56 (define_reservation "cortex_a9_p0_shift" "cortex_a9_p0_e1, cortex_a9_p0_default")
  57 (define_reservation "cortex_a9_p1_shift" "cortex_a9_p1_e1, cortex_a9_p1_default")
  58
  59 (define_reservation "cortex_a9_multcycle1"
  60   "cortex_a9_p0_e2 + cortex_a9_mac_m1 + cortex_a9_mac_m2 + \
  61 cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
  62
  63 (define_reservation "cortex_a9_mult16"
  64   "cortex_a9_mac_m1, cortex_a9_mac_m2, cortex_a9_p0_wb")
  65 (define_reservation "cortex_a9_mac16"
  66   "cortex_a9_multcycle1, cortex_a9_mac_m2, cortex_a9_p0_wb")
  67 (define_reservation "cortex_a9_mult"
  68   "cortex_a9_mac_m1*2, cortex_a9_mac_m2, cortex_a9_p0_wb")
  69 (define_reservation "cortex_a9_mac"
  70   "cortex_a9_multcycle1*2 ,cortex_a9_mac_m2, cortex_a9_p0_wb")
  71 (define_reservation "cortex_a9_mult_long"
  72   "cortex_a9_mac_m1*3, cortex_a9_mac_m2, cortex_a9_p0_wb")
  73
  74 ;; Issue at the same time along the load store pipeline and
  75 ;; the VFP / Neon pipeline is not possible.
  76 (exclusion_set "cortex_a9_ls" "ca9_issue_vfp_neon")
  77
  78 ;; Default data processing instruction without any shift
  79 ;; The only exception to this is the mov instruction
  80 ;; which can go down E2 without any problem.
  81 (define_insn_reservation "cortex_a9_dp" 2
  82   (and (eq_attr "tune" "cortexa9")
  83        (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
  84                         alu_sreg,alus_sreg,logic_reg,logics_reg,\
  85                         adc_imm,adcs_imm,adc_reg,adcs_reg,\
  86                         adr,bfm,clz,rbit,rev,alu_dsp_reg,\
  87                         shift_imm,shift_reg,\
  88                         mov_imm,mov_reg,mvn_imm,mvn_reg,\
  89                         mov_shift_reg,mov_shift,\
  90                         mrs,multiple"))
  91   "cortex_a9_p0_default|cortex_a9_p1_default")
  92
  93 ;; An instruction using the shifter will go down E1.
  94 (define_insn_reservation "cortex_a9_dp_shift" 3
  95    (and (eq_attr "tune" "cortexa9")
  96         (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
  97                          logic_shift_imm,logics_shift_imm,\
  98                          alu_shift_reg,alus_shift_reg,\
  99                          logic_shift_reg,logics_shift_reg,\
 100                          extend,mvn_shift,mvn_shift_reg"))
 101    "cortex_a9_p0_shift | cortex_a9_p1_shift")
 102
 103 ;; Loads have a latency of 4 cycles.
 104 ;; We don't model autoincrement instructions. These
 105 ;; instructions use the load store pipeline and 1 of
 106 ;; the E2 units to write back the result of the increment.
 107
 108 (define_insn_reservation "cortex_a9_load1_2" 4
 109   (and (eq_attr "tune" "cortexa9")
 110        (eq_attr "type" "load_4, load_8, load_byte, f_loads, f_loadd"))
 111   "cortex_a9_ls")
 112
 113 ;; Loads multiples and store multiples can't be issued for 2 cycles in a
 114 ;; row. The description below assumes that addresses are 64 bit aligned.
 115 ;; If not, there is an extra cycle latency which is not modelled.
 116
 117 (define_insn_reservation "cortex_a9_load3_4" 5
 118   (and (eq_attr "tune" "cortexa9")
 119        (eq_attr "type" "load_12, load_16"))
 120   "cortex_a9_ls, cortex_a9_ls")
 121
 122 (define_insn_reservation "cortex_a9_store1_2" 0
 123   (and (eq_attr "tune" "cortexa9")
 124        (eq_attr "type" "store_4, store_8, f_stores, f_stored"))
 125   "cortex_a9_ls")
 126
 127 ;; Almost all our store multiples use an auto-increment
 128 ;; form. Don't issue back to back load and store multiples
 129 ;; because the load store unit will stall.
 130
 131 (define_insn_reservation "cortex_a9_store3_4" 0
 132   (and (eq_attr "tune" "cortexa9")
 133        (eq_attr "type" "store_12, store_16"))
 134   "cortex_a9_ls+(cortex_a9_p0_default | cortex_a9_p1_default), cortex_a9_ls")
 135
 136 ;; We get 16*16 multiply / mac results in 3 cycles.
 137 (define_insn_reservation "cortex_a9_mult16" 3
 138   (and (eq_attr "tune" "cortexa9")
 139        (eq_attr "type" "smulxy"))
 140        "cortex_a9_mult16")
 141
 142 ;; The 16*16 mac is slightly different that it
 143 ;; reserves M1 and M2 in the same cycle.
 144 (define_insn_reservation "cortex_a9_mac16" 3
 145   (and (eq_attr "tune" "cortexa9")
 146        (eq_attr "type" "smlaxy"))
 147   "cortex_a9_mac16")
 148
 149 (define_insn_reservation "cortex_a9_multiply" 4
 150   (and (eq_attr "tune" "cortexa9")
 151        (eq_attr "type" "mul,smmul,smmulr"))
 152        "cortex_a9_mult")
 153
 154 (define_insn_reservation "cortex_a9_mac" 4
 155   (and (eq_attr "tune" "cortexa9")
 156        (eq_attr "type" "mla,smmla"))
 157        "cortex_a9_mac")
 158
 159 (define_insn_reservation "cortex_a9_multiply_long" 5
 160   (and (eq_attr "tune" "cortexa9")
 161        (eq_attr "type" "smull,umull,smulls,umulls,smlal,smlals,umlal,umlals"))
 162        "cortex_a9_mult_long")
 163
 164 ;; An instruction with a result in E2 can be forwarded
 165 ;; to E2 or E1 or M1 or the load store unit in the next cycle.
 166
 167 (define_bypass 1 "cortex_a9_dp"
 168                  "cortex_a9_dp_shift, cortex_a9_multiply,
 169  cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2,
 170  cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4,
 171  cortex_a9_multiply_long")
 172
 173 (define_bypass 2 "cortex_a9_dp_shift"
 174                  "cortex_a9_dp_shift, cortex_a9_multiply,
 175  cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2,
 176  cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4,
 177  cortex_a9_multiply_long")
 178
 179 ;; An instruction in the load store pipeline can provide
 180 ;; read access to a DP instruction in the P0 default pipeline
 181 ;; before the writeback stage.
 182
 183 (define_bypass 3 "cortex_a9_load1_2" "cortex_a9_dp, cortex_a9_load1_2,
 184 cortex_a9_store3_4, cortex_a9_store1_2")
 185
 186 (define_bypass 4 "cortex_a9_load3_4" "cortex_a9_dp, cortex_a9_load1_2,
 187 cortex_a9_store3_4, cortex_a9_store1_2,  cortex_a9_load3_4")
 188
 189 ;; Calls and branches.
 190
 191 ;; Branch instructions
 192
 193 (define_insn_reservation "cortex_a9_branch" 0
 194   (and (eq_attr "tune" "cortexa9")
 195        (eq_attr "type" "branch"))
 196   "cortex_a9_branch")
 197
 198 ;; Call latencies are essentially 0 but make sure
 199 ;; dual issue doesn't happen i.e the next instruction
 200 ;; starts at the next cycle.
 201 (define_insn_reservation "cortex_a9_call"  0
 202   (and (eq_attr "tune" "cortexa9")
 203        (eq_attr "type" "call"))
 204   "cortex_a9_issue_branch + cortex_a9_multcycle1 + cortex_a9_ls + ca9_issue_vfp_neon")
 205
 206
 207 ;; Pipelining for VFP instructions.
 208 ;; Issue happens either along load store unit or the VFP / Neon unit.
 209 ;; Pipeline   Instruction Classification.
 210 ;; FPS - fmov, ffariths, ffarithd,f_mcr,f_mcrr,f_mrc,f_mrrc
 211 ;; FP_ADD   - fadds, faddd, fcmps (1)
 212 ;; FPMUL   - fmul{s,d}, fmac{s,d}, ffma{s,d}
 213 ;; FPDIV - fdiv{s,d}
 214 (define_cpu_unit "ca9fps" "cortex_a9")
 215 (define_cpu_unit "ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4" "cortex_a9")
 216 (define_cpu_unit "ca9fp_mul1, ca9fp_mul2 , ca9fp_mul3, ca9fp_mul4" "cortex_a9")
 217 (define_cpu_unit "ca9fp_ds1" "cortex_a9")
 218
 219
 220 ;; fmrs, fmrrd, fmstat and fmrx - The data is available after 1 cycle.
 221 (define_insn_reservation "cortex_a9_fps" 2
 222  (and (eq_attr "tune" "cortexa9")
 223       (eq_attr "type" "fmov, fconsts, fconstd, ffariths, ffarithd,\
 224                        f_mcr, f_mcrr, f_mrc, f_mrrc, f_flag"))
 225  "ca9_issue_vfp_neon + ca9fps")
 226
 227 (define_bypass 1
 228   "cortex_a9_fps"
 229   "cortex_a9_fadd, cortex_a9_fps, cortex_a9_fcmp, cortex_a9_dp, cortex_a9_dp_shift, cortex_a9_multiply, cortex_a9_multiply_long")
 230
 231 ;; Scheduling on the FP_ADD pipeline.
 232 (define_reservation "ca9fp_add" "ca9_issue_vfp_neon + ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4")
 233
 234 (define_insn_reservation "cortex_a9_fadd" 4
 235   (and (eq_attr "tune" "cortexa9")
 236        (eq_attr "type" "fadds, faddd, f_cvt, f_cvtf2i, f_cvti2f"))
 237   "ca9fp_add")
 238
 239 (define_insn_reservation "cortex_a9_fcmp" 1
 240   (and (eq_attr "tune" "cortexa9")
 241       (eq_attr "type" "fcmps, fcmpd"))
 242  "ca9_issue_vfp_neon + ca9fp_add1")
 243
 244 ;; Scheduling for the Multiply and MAC instructions.
 245 (define_reservation "ca9fmuls"
 246   "ca9fp_mul1 + ca9_issue_vfp_neon, ca9fp_mul2, ca9fp_mul3, ca9fp_mul4")
 247
 248 (define_reservation "ca9fmuld"
 249   "ca9fp_mul1 + ca9_issue_vfp_neon, (ca9fp_mul1 + ca9fp_mul2), ca9fp_mul2, ca9fp_mul3, ca9fp_mul4")
 250
 251 (define_insn_reservation "cortex_a9_fmuls" 4
 252   (and (eq_attr "tune" "cortexa9")
 253        (eq_attr "type" "fmuls"))
 254   "ca9fmuls")
 255
 256 (define_insn_reservation "cortex_a9_fmuld" 5
 257   (and (eq_attr "tune" "cortexa9")
 258        (eq_attr "type" "fmuld"))
 259   "ca9fmuld")
 260
 261 (define_insn_reservation "cortex_a9_fmacs" 8
 262   (and (eq_attr "tune" "cortexa9")
 263        (eq_attr "type" "fmacs,ffmas"))
 264   "ca9fmuls, ca9fp_add")
 265
 266 (define_insn_reservation "cortex_a9_fmacd" 9
 267   (and (eq_attr "tune" "cortexa9")
 268        (eq_attr "type" "fmacd,ffmad"))
 269   "ca9fmuld, ca9fp_add")
 270
 271 ;; Division pipeline description.
 272 (define_insn_reservation "cortex_a9_fdivs" 15
 273   (and (eq_attr "tune" "cortexa9")
 274        (eq_attr "type" "fdivs, fsqrts"))
 275   "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*14")
 276
 277 (define_insn_reservation "cortex_a9_fdivd" 25
 278   (and (eq_attr "tune" "cortexa9")
 279        (eq_attr "type" "fdivd, fsqrtd"))
 280   "ca9fp_ds1 + ca9_issue_vfp_neon, nothing*24")
 281
 282 ;; Include Neon pipeline description
 283 (include "cortex-a9-neon.md")