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[gcc.git] / gcc / config / arm / arm.h
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 93-98, 1999 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6 Minor hacks by Nick Clifton (nickc@cygnus.com)
7
8 This file is part of GNU CC.
9
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 #ifndef __ARM_H__
26 #define __ARM_H__
27
28 #define TARGET_CPU_arm2 0x0000
29 #define TARGET_CPU_arm250 0x0000
30 #define TARGET_CPU_arm3 0x0000
31 #define TARGET_CPU_arm6 0x0001
32 #define TARGET_CPU_arm600 0x0001
33 #define TARGET_CPU_arm610 0x0002
34 #define TARGET_CPU_arm7 0x0001
35 #define TARGET_CPU_arm7m 0x0004
36 #define TARGET_CPU_arm7dm 0x0004
37 #define TARGET_CPU_arm7dmi 0x0004
38 #define TARGET_CPU_arm700 0x0001
39 #define TARGET_CPU_arm710 0x0002
40 #define TARGET_CPU_arm7100 0x0002
41 #define TARGET_CPU_arm7500 0x0002
42 #define TARGET_CPU_arm7500fe 0x1001
43 #define TARGET_CPU_arm7tdmi 0x0008
44 #define TARGET_CPU_arm8 0x0010
45 #define TARGET_CPU_arm810 0x0020
46 #define TARGET_CPU_strongarm 0x0040
47 #define TARGET_CPU_strongarm110 0x0040
48 #define TARGET_CPU_strongarm1100 0x0040
49 #define TARGET_CPU_arm9 0x0080
50 #define TARGET_CPU_arm9tdmi 0x0080
51 /* Configure didn't specify */
52 #define TARGET_CPU_generic 0x8000
53
54 enum arm_cond_code
55 {
56 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
57 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
58 };
59
60 extern enum arm_cond_code arm_current_cc;
61 extern char * arm_condition_codes[];
62
63 #define ARM_INVERSE_CONDITION_CODE(X) ((enum arm_cond_code) (((int)X) ^ 1))
64
65 extern int arm_target_label;
66 extern int arm_ccfsm_state;
67 extern struct rtx_def * arm_target_insn;
68 extern int lr_save_eliminated;
69 /* This is needed by the tail-calling peepholes */
70 extern int frame_pointer_needed;
71 /* Run-time compilation parameters selecting different hardware subsets. */
72 extern int target_flags;
73 /* The floating point instruction architecture, can be 2 or 3 */
74 extern const char * target_fp_name;
75
76 \f
77 /* Just in case configure has failed to define anything. */
78 #ifndef TARGET_CPU_DEFAULT
79 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
80 #endif
81
82 /* If the configuration file doesn't specify the cpu, the subtarget may
83 override it. If it doesn't, then default to an ARM6. */
84 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
85 #undef TARGET_CPU_DEFAULT
86 #ifdef SUBTARGET_CPU_DEFAULT
87 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
88 #else
89 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
90 #endif
91 #endif
92
93 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
94 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
95 #else
96 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
97 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
98 #else
99 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
100 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
101 #else
102 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9
103 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
104 #else
105 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm
106 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
107 #else
108 Unrecognized value in TARGET_CPU_DEFAULT.
109 #endif
110 #endif
111 #endif
112 #endif
113 #endif
114
115 #ifndef CPP_PREDEFINES
116 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
117 #endif
118
119 #define CPP_SPEC "\
120 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
121 %(cpp_endian) %(subtarget_cpp_spec)"
122
123 /* Set the architecture define -- if -march= is set, then it overrides
124 the -mcpu= setting. */
125 #define CPP_CPU_ARCH_SPEC "\
126 %{march=arm2:-D__ARM_ARCH_2__} \
127 %{march=arm250:-D__ARM_ARCH_2__} \
128 %{march=arm3:-D__ARM_ARCH_2__} \
129 %{march=arm6:-D__ARM_ARCH_3__} \
130 %{march=arm600:-D__ARM_ARCH_3__} \
131 %{march=arm610:-D__ARM_ARCH_3__} \
132 %{march=arm7:-D__ARM_ARCH_3__} \
133 %{march=arm700:-D__ARM_ARCH_3__} \
134 %{march=arm710:-D__ARM_ARCH_3__} \
135 %{march=arm7100:-D__ARM_ARCH_3__} \
136 %{march=arm7500:-D__ARM_ARCH_3__} \
137 %{march=arm7500fe:-D__ARM_ARCH_3__} \
138 %{march=arm7m:-D__ARM_ARCH_3M__} \
139 %{march=arm7dm:-D__ARM_ARCH_3M__} \
140 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
141 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
142 %{march=arm8:-D__ARM_ARCH_4__} \
143 %{march=arm810:-D__ARM_ARCH_4__} \
144 %{march=arm9:-D__ARM_ARCH_4T__} \
145 %{march=arm920:-D__ARM_ARCH_4__} \
146 %{march=arm920t:-D__ARM_ARCH_4T__} \
147 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
148 %{march=strongarm:-D__ARM_ARCH_4__} \
149 %{march=strongarm110:-D__ARM_ARCH_4__} \
150 %{march=strongarm1100:-D__ARM_ARCH_4__} \
151 %{march=armv2:-D__ARM_ARCH_2__} \
152 %{march=armv2a:-D__ARM_ARCH_2__} \
153 %{march=armv3:-D__ARM_ARCH_3__} \
154 %{march=armv3m:-D__ARM_ARCH_3M__} \
155 %{march=armv4:-D__ARM_ARCH_4__} \
156 %{march=armv4t:-D__ARM_ARCH_4T__} \
157 %{march=armv5:-D__ARM_ARCH_5__} \
158 %{!march=*: \
159 %{mcpu=arm2:-D__ARM_ARCH_2__} \
160 %{mcpu=arm250:-D__ARM_ARCH_2__} \
161 %{mcpu=arm3:-D__ARM_ARCH_2__} \
162 %{mcpu=arm6:-D__ARM_ARCH_3__} \
163 %{mcpu=arm600:-D__ARM_ARCH_3__} \
164 %{mcpu=arm610:-D__ARM_ARCH_3__} \
165 %{mcpu=arm7:-D__ARM_ARCH_3__} \
166 %{mcpu=arm700:-D__ARM_ARCH_3__} \
167 %{mcpu=arm710:-D__ARM_ARCH_3__} \
168 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
169 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
170 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
171 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
172 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
173 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
174 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
175 %{mcpu=arm8:-D__ARM_ARCH_4__} \
176 %{mcpu=arm810:-D__ARM_ARCH_4__} \
177 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
178 %{mcpu=arm920:-D__ARM_ARCH_4__} \
179 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
180 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
181 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
182 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
183 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
184 %{!mcpu*:%(cpp_cpu_arch_default)}} \
185 "
186
187 /* Define __APCS_26__ if the PC also contains the PSR */
188 #define CPP_APCS_PC_SPEC "\
189 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
190 -D__APCS_32__} \
191 %{mapcs-26:-D__APCS_26__} \
192 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
193 "
194
195 #ifndef CPP_APCS_PC_DEFAULT_SPEC
196 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
197 #endif
198
199 #define CPP_FLOAT_SPEC "\
200 %{msoft-float:\
201 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
202 -D__SOFTFP__} \
203 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
204 "
205
206 /* Default is hard float, which doesn't define anything */
207 #define CPP_FLOAT_DEFAULT_SPEC ""
208
209 #define CPP_ENDIAN_SPEC "\
210 %{mbig-endian: \
211 %{mlittle-endian: \
212 %e-mbig-endian and -mlittle-endian may not be used together} \
213 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \
214 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
215 "
216
217 /* Default is little endian, which doesn't define anything. */
218 #define CPP_ENDIAN_DEFAULT_SPEC ""
219
220 #define CC1_SPEC ""
221
222 /* This macro defines names of additional specifications to put in the specs
223 that can be used in various specifications like CC1_SPEC. Its definition
224 is an initializer with a subgrouping for each command option.
225
226 Each subgrouping contains a string constant, that defines the
227 specification name, and a string constant that used by the GNU CC driver
228 program.
229
230 Do not define this macro if it does not need to do anything. */
231 #define EXTRA_SPECS \
232 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
233 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
234 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
235 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
236 { "cpp_float", CPP_FLOAT_SPEC }, \
237 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
238 { "cpp_endian", CPP_ENDIAN_SPEC }, \
239 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
240 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
241 SUBTARGET_EXTRA_SPECS
242
243 #define SUBTARGET_EXTRA_SPECS
244 #ifndef SUBTARGET_CPP_SPEC
245 #define SUBTARGET_CPP_SPEC ""
246 #endif
247
248 \f
249 /* Run-time Target Specification. */
250 #ifndef TARGET_VERSION
251 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
252 #endif
253
254 /* Nonzero if the function prologue (and epilogue) should obey
255 the ARM Procedure Call Standard. */
256 #define ARM_FLAG_APCS_FRAME (1 << 0)
257
258 /* Nonzero if the function prologue should output the function name to enable
259 the post mortem debugger to print a backtrace (very useful on RISCOS,
260 unused on RISCiX). Specifying this flag also enables
261 -fno-omit-frame-pointer.
262 XXX Must still be implemented in the prologue. */
263 #define ARM_FLAG_POKE (1 << 1)
264
265 /* Nonzero if floating point instructions are emulated by the FPE, in which
266 case instruction scheduling becomes very uninteresting. */
267 #define ARM_FLAG_FPE (1 << 2)
268
269 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
270 that assume restoration of the condition flags when returning from a
271 branch and link (ie a function). */
272 #define ARM_FLAG_APCS_32 (1 << 3)
273
274 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
275
276 /* Nonzero if stack checking should be performed on entry to each function
277 which allocates temporary variables on the stack. */
278 #define ARM_FLAG_APCS_STACK (1 << 4)
279
280 /* Nonzero if floating point parameters should be passed to functions in
281 floating point registers. */
282 #define ARM_FLAG_APCS_FLOAT (1 << 5)
283
284 /* Nonzero if re-entrant, position independent code should be generated.
285 This is equivalent to -fpic. */
286 #define ARM_FLAG_APCS_REENT (1 << 6)
287
288 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must be
289 loaded byte-at-a-time. */
290 #define ARM_FLAG_SHORT_BYTE (1 << 7)
291
292 /* Nonzero if all floating point instructions are missing (and there is no
293 emulator either). Generate function calls for all ops in this case. */
294 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
295
296 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
297 #define ARM_FLAG_BIG_END (1 << 9)
298
299 /* Nonzero if we should compile for Thumb interworking. */
300 #define ARM_FLAG_INTERWORK (1 << 10)
301
302 /* Nonzero if we should have little-endian words even when compiling for
303 big-endian (for backwards compatibility with older versions of GCC). */
304 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
305
306 /* Nonzero if we need to protect the prolog from scheduling */
307 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
308
309 /* Nonzero if a call to abort should be generated if a noreturn
310 function tries to return. */
311 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
312
313 /* Nonzero if function prologues should not load the PIC register. */
314 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
315
316 #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME)
317 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
318 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
319 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
320 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
321 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
322 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
323 /* Note: TARGET_SHORT_BY_BYTES is really a misnomer. What it means is
324 that short values should not be accessed using word load instructions
325 as there is a possibility that they may not be word aligned and this
326 would generate an MMU fault. On processors which do not have a 16 bit
327 load instruction therefore, short values must be loaded by individual
328 byte accesses rather than loading a word and then shifting the desired
329 value into place. */
330 #define TARGET_SHORT_BY_BYTES (target_flags & ARM_FLAG_SHORT_BYTE)
331 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
332 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
333 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
334 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
335 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
336 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
337 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
338 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
339
340 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
341 Bit 31 is reserved. See riscix.h. */
342 #ifndef SUBTARGET_SWITCHES
343 #define SUBTARGET_SWITCHES
344 #endif
345
346 #define TARGET_SWITCHES \
347 { \
348 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
349 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
350 "Generate APCS conformant stack frames" }, \
351 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
352 {"poke-function-name", ARM_FLAG_POKE, \
353 "Store function names in object code" }, \
354 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
355 {"fpe", ARM_FLAG_FPE, "" }, \
356 {"apcs-32", ARM_FLAG_APCS_32, \
357 "Use the 32bit version of the APCS" }, \
358 {"apcs-26", -ARM_FLAG_APCS_32, \
359 "Use the 26bit version of the APCS" }, \
360 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
361 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
362 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
363 "Pass FP arguments in FP registers" }, \
364 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
365 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
366 "Generate re-entrant, PIC code" }, \
367 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
368 {"short-load-bytes", ARM_FLAG_SHORT_BYTE, \
369 "Load shorts a byte at a time" }, \
370 {"no-short-load-bytes", -ARM_FLAG_SHORT_BYTE, "" }, \
371 {"short-load-words", -ARM_FLAG_SHORT_BYTE, \
372 "Load words a byte at a time" }, \
373 {"no-short-load-words", ARM_FLAG_SHORT_BYTE, "" }, \
374 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
375 "Use library calls to perform FP operations" }, \
376 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
377 "Use hardware floating point instructions" }, \
378 {"big-endian", ARM_FLAG_BIG_END, \
379 "Assume target CPU is configured as big endian" }, \
380 {"little-endian", -ARM_FLAG_BIG_END, \
381 "Assume target CPU is configured as little endian" }, \
382 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
383 "Assume big endian bytes, little endian words" }, \
384 {"thumb-interwork", ARM_FLAG_INTERWORK, \
385 "Support calls between THUMB and ARM instructions sets" }, \
386 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
387 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
388 "Generate a call to abort if a noreturn function returns"}, \
389 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, ""}, \
390 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \
391 "Do not move instructions into a function's prologue" }, \
392 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \
393 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
394 "Do not load the PIC register in function prologues" }, \
395 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
396 SUBTARGET_SWITCHES \
397 {"", TARGET_DEFAULT, "" } \
398 }
399
400 #define TARGET_OPTIONS \
401 { \
402 {"cpu=", & arm_select[0].string, \
403 "Specify the name of the target CPU" }, \
404 {"arch=", & arm_select[1].string, \
405 "Specify the name of the target architecture" }, \
406 {"tune=", & arm_select[2].string, "" }, \
407 {"fpe=", & target_fp_name, "" }, \
408 {"fp=", & target_fp_name, \
409 "Specify the version of the floating point emulator" }, \
410 { "structure-size-boundary=", & structure_size_string, \
411 "Specify the minumum bit alignment of structures" }, \
412 { "pic-register=", & arm_pic_register_string, \
413 "Specify the register to be used for PIC addressing" } \
414 }
415
416 struct arm_cpu_select
417 {
418 const char * string;
419 const char * name;
420 const struct processors * processors;
421 };
422
423 /* This is a magic array. If the user specifies a command line switch
424 which matches one of the entries in TARGET_OPTIONS then the corresponding
425 string pointer will be set to the value specified by the user. */
426 extern struct arm_cpu_select arm_select[];
427
428 enum prog_mode_type
429 {
430 prog_mode26,
431 prog_mode32
432 };
433
434 /* Recast the program mode class to be the prog_mode attribute */
435 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
436
437 extern enum prog_mode_type arm_prgmode;
438
439 /* What sort of floating point unit do we have? Hardware or software.
440 If software, is it issue 2 or issue 3? */
441 enum floating_point_type
442 {
443 FP_HARD,
444 FP_SOFT2,
445 FP_SOFT3
446 };
447
448 /* Recast the floating point class to be the floating point attribute. */
449 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
450
451 /* What type of floating point to tune for */
452 extern enum floating_point_type arm_fpu;
453
454 /* What type of floating point instructions are available */
455 extern enum floating_point_type arm_fpu_arch;
456
457 /* Default floating point architecture. Override in sub-target if
458 necessary. */
459 #define FP_DEFAULT FP_SOFT2
460
461 /* Nonzero if the processor has a fast multiply insn, and one that does
462 a 64-bit multiply of two 32-bit values. */
463 extern int arm_fast_multiply;
464
465 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
466 extern int arm_arch4;
467
468 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
469 extern int arm_arch5;
470
471 /* Nonzero if this chip can benefit from load scheduling. */
472 extern int arm_ld_sched;
473
474 /* Nonzero if this chip is a StrongARM. */
475 extern int arm_is_strong;
476
477 /* Nonzero if this chip is a an ARM6 or an ARM7. */
478 extern int arm_is_6_or_7;
479
480 #ifndef TARGET_DEFAULT
481 #define TARGET_DEFAULT 0
482 #endif
483
484 /* The frame pointer register used in gcc has nothing to do with debugging;
485 that is controlled by the APCS-FRAME option. */
486 /* Not fully implemented yet */
487 /* #define CAN_DEBUG_WITHOUT_FP 1 */
488
489 #define TARGET_MEM_FUNCTIONS 1
490
491 #define OVERRIDE_OPTIONS arm_override_options ()
492
493 /* Nonzero if PIC code requires explicit qualifiers to generate
494 PLT and GOT relocs rather than the assembler doing so implicitly.
495 Subtargets can override these if required. */
496 #ifndef NEED_GOT_RELOC
497 #define NEED_GOT_RELOC 0
498 #endif
499 #ifndef NEED_PLT_RELOC
500 #define NEED_PLT_RELOC 0
501 #endif
502
503 /* Nonzero if we need to refer to the GOT with a PC-relative
504 offset. In other words, generate
505
506 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
507
508 rather than
509
510 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
511
512 The default is true, which matches NetBSD. Subtargets can
513 override this if required. */
514 #ifndef GOT_PCREL
515 #define GOT_PCREL 1
516 #endif
517 \f
518 /* Target machine storage Layout. */
519
520
521 /* Define this macro if it is advisable to hold scalars in registers
522 in a wider mode than that declared by the program. In such cases,
523 the value is constrained to be within the bounds of the declared
524 type, but kept valid in the wider mode. The signedness of the
525 extension may differ from that of the type. */
526
527 /* It is far faster to zero extend chars than to sign extend them */
528
529 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
530 if (GET_MODE_CLASS (MODE) == MODE_INT \
531 && GET_MODE_SIZE (MODE) < 4) \
532 { \
533 if (MODE == QImode) \
534 UNSIGNEDP = 1; \
535 else if (MODE == HImode) \
536 UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \
537 (MODE) = SImode; \
538 }
539
540 /* Define this macro if the promotion described by `PROMOTE_MODE'
541 should also be done for outgoing function arguments. */
542 /* This is required to ensure that push insns always push a word. */
543 #define PROMOTE_FUNCTION_ARGS
544
545 /* Define for XFmode extended real floating point support.
546 This will automatically cause REAL_ARITHMETIC to be defined. */
547 /* For the ARM:
548 I think I have added all the code to make this work. Unfortunately,
549 early releases of the floating point emulation code on RISCiX used a
550 different format for extended precision numbers. On my RISCiX box there
551 is a bug somewhere which causes the machine to lock up when running enquire
552 with long doubles. There is the additional aspect that Norcroft C
553 treats long doubles as doubles and we ought to remain compatible.
554 Perhaps someone with an FPA coprocessor and not running RISCiX would like
555 to try this someday. */
556 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
557
558 /* Disable XFmode patterns in md file */
559 #define ENABLE_XF_PATTERNS 0
560
561 /* Define if you don't want extended real, but do want to use the
562 software floating point emulator for REAL_ARITHMETIC and
563 decimal <-> binary conversion. */
564 /* See comment above */
565 #define REAL_ARITHMETIC
566
567 /* Define this if most significant bit is lowest numbered
568 in instructions that operate on numbered bit-fields. */
569 #define BITS_BIG_ENDIAN 0
570
571 /* Define this if most significant byte of a word is the lowest numbered.
572 Most ARM processors are run in little endian mode, so that is the default.
573 If you want to have it run-time selectable, change the definition in a
574 cover file to be TARGET_BIG_ENDIAN. */
575 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
576
577 /* Define this if most significant word of a multiword number is the lowest
578 numbered.
579 This is always false, even when in big-endian mode. */
580 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
581
582 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
583 on processor pre-defineds when compiling libgcc2.c. */
584 #if defined(__ARMEB__) && !defined(__ARMWEL__)
585 #define LIBGCC2_WORDS_BIG_ENDIAN 1
586 #else
587 #define LIBGCC2_WORDS_BIG_ENDIAN 0
588 #endif
589
590 /* Define this if most significant word of doubles is the lowest numbered.
591 This is always true, even when in little-endian mode. */
592 #define FLOAT_WORDS_BIG_ENDIAN 1
593
594 /* Number of bits in an addressable storage unit */
595 #define BITS_PER_UNIT 8
596
597 #define BITS_PER_WORD 32
598
599 #define UNITS_PER_WORD 4
600
601 #define POINTER_SIZE 32
602
603 #define PARM_BOUNDARY 32
604
605 #define STACK_BOUNDARY 32
606
607 #define FUNCTION_BOUNDARY 32
608
609 #define EMPTY_FIELD_BOUNDARY 32
610
611 #define BIGGEST_ALIGNMENT 32
612
613 /* Make strings word-aligned so strcpy from constants will be faster. */
614 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
615 (TREE_CODE (EXP) == STRING_CST \
616 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
617
618 /* Every structures size must be a multiple of 32 bits. */
619 /* This is for compatibility with ARMCC. ARM SDT Reference Manual
620 (ARM DUI 0020D) page 2-20 says "Structures are aligned on word
621 boundaries". */
622 #ifndef STRUCTURE_SIZE_BOUNDARY
623 #define STRUCTURE_SIZE_BOUNDARY 32
624 #endif
625
626 /* Used when parsing command line option -mstructure_size_boundary. */
627 extern const char * structure_size_string;
628
629 /* Non-zero if move instructions will actually fail to work
630 when given unaligned data. */
631 #define STRICT_ALIGNMENT 1
632
633 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
634
635 \f
636 /* Standard register usage. */
637
638 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
639 (S - saved over call).
640
641 r0 * argument word/integer result
642 r1-r3 argument word
643
644 r4-r8 S register variable
645 r9 S (rfp) register variable (real frame pointer)
646
647 r10 F S (sl) stack limit (used by -mapcs-stack-check)
648 r11 F S (fp) argument pointer
649 r12 (ip) temp workspace
650 r13 F S (sp) lower end of current stack frame
651 r14 (lr) link address/workspace
652 r15 F (pc) program counter
653
654 f0 floating point result
655 f1-f3 floating point scratch
656
657 f4-f7 S floating point variable
658
659 cc This is NOT a real register, but is used internally
660 to represent things that use or set the condition
661 codes.
662 sfp This isn't either. It is used during rtl generation
663 since the offset between the frame pointer and the
664 auto's isn't known until after register allocation.
665 afp Nor this, we only need this because of non-local
666 goto. Without it fp appears to be used and the
667 elimination code won't get rid of sfp. It tracks
668 fp exactly at all times.
669
670 *: See CONDITIONAL_REGISTER_USAGE */
671
672 /* The stack backtrace structure is as follows:
673 fp points to here: | save code pointer | [fp]
674 | return link value | [fp, #-4]
675 | return sp value | [fp, #-8]
676 | return fp value | [fp, #-12]
677 [| saved r10 value |]
678 [| saved r9 value |]
679 [| saved r8 value |]
680 [| saved r7 value |]
681 [| saved r6 value |]
682 [| saved r5 value |]
683 [| saved r4 value |]
684 [| saved r3 value |]
685 [| saved r2 value |]
686 [| saved r1 value |]
687 [| saved r0 value |]
688 [| saved f7 value |] three words
689 [| saved f6 value |] three words
690 [| saved f5 value |] three words
691 [| saved f4 value |] three words
692 r0-r3 are not normally saved in a C function. */
693
694 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
695 #define FIRST_PSEUDO_REGISTER 27
696
697 /* 1 for registers that have pervasive standard uses
698 and are not available for the register allocator. */
699 #define FIXED_REGISTERS \
700 { \
701 0,0,0,0,0,0,0,0, \
702 0,0,0,1,0,1,0,1, \
703 0,0,0,0,0,0,0,0, \
704 1,1,1 \
705 }
706
707 /* 1 for registers not available across function calls.
708 These must include the FIXED_REGISTERS and also any
709 registers that can be used without being saved.
710 The latter must include the registers where values are returned
711 and the register where structure-value addresses are passed.
712 Aside from that, you can include as many other registers as you like.
713 The CC is not preserved over function calls on the ARM 6, so it is
714 easier to assume this for all. SFP is preserved, since FP is. */
715 #define CALL_USED_REGISTERS \
716 { \
717 1,1,1,1,0,0,0,0, \
718 0,0,0,1,1,1,1,1, \
719 1,1,1,1,0,0,0,0, \
720 1,1,1 \
721 }
722
723 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
724 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
725 #endif
726
727 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
728 trampled. This effectively reduces the number of available registers by 1.
729 XXX It is a hack, I know.
730 XXX Is this still needed? */
731 #define CONDITIONAL_REGISTER_USAGE \
732 { \
733 if (obey_regdecls) \
734 fixed_regs[0] = 1; \
735 if (TARGET_SOFT_FLOAT) \
736 { \
737 int regno; \
738 for (regno = 16; regno < 24; ++regno) \
739 fixed_regs[regno] = call_used_regs[regno] = 1; \
740 } \
741 if (flag_pic) \
742 { \
743 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
744 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
745 } \
746 else if (TARGET_APCS_STACK) \
747 { \
748 fixed_regs[10] = 1; \
749 call_used_regs[10] = 1; \
750 } \
751 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
752 }
753
754 /* These are a couple of extensions to the formats accecpted
755 by asm_fprintf:
756 %@ prints out ASM_COMMENT_START
757 %r prints out REGISTER_PREFIX reg_names[arg] */
758 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
759 case '@': \
760 fputs (ASM_COMMENT_START, FILE); \
761 break; \
762 \
763 case 'r': \
764 fputs (REGISTER_PREFIX, FILE); \
765 fputs (reg_names [va_arg (ARGS, int)], FILE); \
766 break;
767
768 /* Convert fron bytes to ints. */
769 #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
770
771 /* The number of (integer) registers required to hold a quantity of type MODE. */
772 #define NUM_REGS(MODE) \
773 NUM_INTS (GET_MODE_SIZE (MODE))
774
775 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
776 #define NUM_REGS2(MODE, TYPE) \
777 NUM_INTS ((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
778
779 /* The number of (integer) argument register available. */
780 #define NUM_ARG_REGS 4
781
782 /* Return the regiser number of the N'th (integer) argument. */
783 #define ARG_REGISTER(N) (N - 1)
784
785 /* The number of the last argument register. */
786 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
787
788 /* Return number of consecutive hard regs needed starting at reg REGNO
789 to hold something of mode MODE.
790 This is ordinarily the length in words of a value of mode MODE
791 but can be less for certain modes in special long registers.
792
793 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
794 mode. */
795 #define HARD_REGNO_NREGS(REGNO, MODE) \
796 (( REGNO >= 16 \
797 && REGNO != FRAME_POINTER_REGNUM \
798 && REGNO != ARG_POINTER_REGNUM) \
799 ? 1 : NUM_REGS (MODE))
800
801 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
802 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
803 regs holding FP. */
804 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
805 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
806 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
807 || REGNO == ARG_POINTER_REGNUM \
808 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
809
810 /* Value is 1 if it is a good idea to tie two pseudo registers
811 when one has mode MODE1 and one has mode MODE2.
812 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
813 for any hard reg, then this must be 0 for correct output. */
814 #define MODES_TIEABLE_P(MODE1, MODE2) \
815 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
816
817 /* Specify the registers used for certain standard purposes.
818 The values of these macros are register numbers. */
819
820 /* Define this if the program counter is overloaded on a register. */
821 #define PC_REGNUM 15
822
823 /* Register to use for pushing function arguments. */
824 #define STACK_POINTER_REGNUM 13
825 #define SP_REGNUM STACK_POINTER_REGNUM
826
827 /* Base register for access to local variables of the function. */
828 #define FRAME_POINTER_REGNUM 25
829
830 /* Define this to be where the real frame pointer is if it is not possible to
831 work out the offset between the frame pointer and the automatic variables
832 until after register allocation has taken place. FRAME_POINTER_REGNUM
833 should point to a special register that we will make sure is eliminated. */
834 #define HARD_FRAME_POINTER_REGNUM 11
835 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
836
837 /* Register which holds return address from a subroutine call. */
838 #define LR_REGNUM 14
839
840 /* Scratch register - used in all kinds of places, eg trampolines. */
841 #define IP_REGNUM 12
842
843 /* Value should be nonzero if functions must have frame pointers.
844 Zero means the frame pointer need not be set up (and parms may be accessed
845 via the stack pointer) in functions that seem suitable.
846 If we have to have a frame pointer we might as well make use of it.
847 APCS says that the frame pointer does not need to be pushed in leaf
848 functions, or simple tail call functions. */
849 #define FRAME_POINTER_REQUIRED \
850 (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ()))
851
852 /* Base register for access to arguments of the function. */
853 #define ARG_POINTER_REGNUM 26
854
855 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
856 as an invisible last argument (possible since varargs don't exist in
857 Pascal), so the following is not true. */
858 #define STATIC_CHAIN_REGNUM 8
859
860 /* Register in which address to store a structure value
861 is passed to a function. */
862 #define STRUCT_VALUE_REGNUM 0
863
864 /* Internal, so that we don't need to refer to a raw number */
865 #define CC_REGNUM 24
866
867 /* The order in which register should be allocated. It is good to use ip
868 since no saving is required (though calls clobber it) and it never contains
869 function parameters. It is quite good to use lr since other calls may
870 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
871 least likely to contain a function parameter; in addition results are
872 returned in r0.
873 */
874 #define REG_ALLOC_ORDER \
875 { \
876 3, 2, 1, 0, 12, 14, 4, 5, \
877 6, 7, 8, 10, 9, 11, 13, 15, \
878 16, 17, 18, 19, 20, 21, 22, 23, \
879 24, 25, 26 \
880 }
881 \f
882 /* Register and constant classes. */
883
884 /* Register classes: all ARM regs or all FPU regs---simple! */
885 enum reg_class
886 {
887 NO_REGS,
888 FPU_REGS,
889 GENERAL_REGS,
890 ALL_REGS,
891 LIM_REG_CLASSES
892 };
893
894 #define N_REG_CLASSES (int) LIM_REG_CLASSES
895
896 /* Give names of register classes as strings for dump file. */
897 #define REG_CLASS_NAMES \
898 { \
899 "NO_REGS", \
900 "FPU_REGS", \
901 "GENERAL_REGS", \
902 "ALL_REGS", \
903 }
904
905 /* Define which registers fit in which classes.
906 This is an initializer for a vector of HARD_REG_SET
907 of length N_REG_CLASSES. */
908 #define REG_CLASS_CONTENTS \
909 { \
910 { 0x0000000 }, /* NO_REGS */ \
911 { 0x0FF0000 }, /* FPU_REGS */ \
912 { 0x200FFFF }, /* GENERAL_REGS */ \
913 { 0x2FFFFFF } /* ALL_REGS */ \
914 }
915
916 /* The same information, inverted:
917 Return the class number of the smallest class containing
918 reg number REGNO. This could be a conditional expression
919 or could index an array. */
920 #define REGNO_REG_CLASS(REGNO) \
921 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
922 || REGNO == ARG_POINTER_REGNUM) \
923 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
924 ? NO_REGS : FPU_REGS)
925
926 /* The class value for index registers, and the one for base regs. */
927 #define INDEX_REG_CLASS GENERAL_REGS
928 #define BASE_REG_CLASS GENERAL_REGS
929
930 /* Get reg_class from a letter such as appears in the machine description.
931 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
932 #define REG_CLASS_FROM_LETTER(C) \
933 ((C)=='f' ? FPU_REGS : NO_REGS)
934
935 /* The letters I, J, K, L and M in a register constraint string
936 can be used to stand for particular ranges of immediate operands.
937 This macro defines what the ranges are.
938 C is the letter, and VALUE is a constant value.
939 Return 1 if VALUE is in the range specified by C.
940 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
941 J: valid indexing constants.
942 K: ~value ok in rhs argument of data operand.
943 L: -value ok in rhs argument of data operand.
944 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
945 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
946 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
947 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
948 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
949 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
950 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
951 || (((VALUE) & ((VALUE) - 1)) == 0)) \
952 : 0)
953
954 /* For the ARM, `Q' means that this is a memory operand that is just
955 an offset from a register.
956 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
957 address. This means that the symbol is in the text segment and can be
958 accessed without using a load. */
959
960 #define EXTRA_CONSTRAINT(OP, C) \
961 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
962 : (C) == 'R' ? (GET_CODE (OP) == MEM \
963 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
964 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
965 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
966 : 0)
967
968 /* Constant letter 'G' for the FPU immediate constants.
969 'H' means the same constant negated. */
970 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
971 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
972 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
973
974 /* Given an rtx X being reloaded into a reg required to be
975 in class CLASS, return the class of reg to actually use.
976 In general this is just CLASS; but on some machines
977 in some cases it is preferable to use a more restrictive class. */
978 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
979
980 /* Return the register class of a scratch register needed to copy IN into
981 or out of a register in CLASS in MODE. If it can be done directly,
982 NO_REGS is returned. */
983 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
984 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
985 ? GENERAL_REGS : NO_REGS)
986
987 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
988 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
989 (((MODE) == HImode && ! arm_arch4 && TARGET_SHORT_BY_BYTES \
990 && (GET_CODE (X) == MEM \
991 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
992 && true_regnum (X) == -1))) \
993 ? GENERAL_REGS : NO_REGS)
994
995 /* Try a machine-dependent way of reloading an illegitimate address
996 operand. If we find one, push the reload and jump to WIN. This
997 macro is used in only one place: `find_reloads_address' in reload.c.
998
999 For the ARM, we wish to handle large displacements off a base
1000 register by splitting the addend across a MOV and the mem insn.
1001 This can cut the number of reloads needed. */
1002 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1003 do \
1004 { \
1005 if (GET_CODE (X) == PLUS \
1006 && GET_CODE (XEXP (X, 0)) == REG \
1007 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1008 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1009 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1010 { \
1011 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1012 HOST_WIDE_INT low, high; \
1013 \
1014 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1015 low = ((val & 0xf) ^ 0x8) - 0x8; \
1016 else if (MODE == SImode || MODE == QImode \
1017 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1018 || (MODE == HImode && ! arm_arch4)) \
1019 /* Need to be careful, -4096 is not a valid offset */ \
1020 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1021 else if (MODE == HImode && arm_arch4) \
1022 /* Need to be careful, -256 is not a valid offset */ \
1023 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1024 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1025 && TARGET_HARD_FLOAT) \
1026 /* Need to be careful, -1024 is not a valid offset */ \
1027 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1028 else \
1029 break; \
1030 \
1031 high = ((((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000); \
1032 /* Check for overflow or zero */ \
1033 if (low == 0 || high == 0 || (high + low != val)) \
1034 break; \
1035 \
1036 /* Reload the high part into a base reg; leave the low part \
1037 in the mem. */ \
1038 X = gen_rtx_PLUS (GET_MODE (X), \
1039 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1040 GEN_INT (high)), \
1041 GEN_INT (low)); \
1042 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1043 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1044 OPNUM, TYPE); \
1045 goto WIN; \
1046 } \
1047 } \
1048 while (0)
1049
1050 /* Return the maximum number of consecutive registers
1051 needed to represent mode MODE in a register of class CLASS.
1052 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1053 #define CLASS_MAX_NREGS(CLASS, MODE) \
1054 ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE))
1055
1056 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1057 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1058 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
1059 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
1060 ? 20 : 2)
1061 \f
1062 /* Stack layout; function entry, exit and calling. */
1063
1064 /* Define this if pushing a word on the stack
1065 makes the stack pointer a smaller address. */
1066 #define STACK_GROWS_DOWNWARD 1
1067
1068 /* Define this if the nominal address of the stack frame
1069 is at the high-address end of the local variables;
1070 that is, each additional local variable allocated
1071 goes at a more negative offset in the frame. */
1072 #define FRAME_GROWS_DOWNWARD 1
1073
1074 /* Offset within stack frame to start allocating local variables at.
1075 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1076 first local allocated. Otherwise, it is the offset to the BEGINNING
1077 of the first local allocated. */
1078 #define STARTING_FRAME_OFFSET 0
1079
1080 /* If we generate an insn to push BYTES bytes,
1081 this says how many the stack pointer really advances by. */
1082 /* The push insns do not do this rounding implicitly. So don't define this. */
1083 /* #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) */
1084
1085 /* Define this if the maximum size of all the outgoing args is to be
1086 accumulated and pushed during the prologue. The amount can be
1087 found in the variable current_function_outgoing_args_size. */
1088 #define ACCUMULATE_OUTGOING_ARGS 1
1089
1090 /* Offset of first parameter from the argument pointer register value. */
1091 #define FIRST_PARM_OFFSET(FNDECL) 4
1092
1093 /* Value is the number of byte of arguments automatically
1094 popped when returning from a subroutine call.
1095 FUNDECL is the declaration node of the function (as a tree),
1096 FUNTYPE is the data type of the function (as a tree),
1097 or for a library call it is an identifier node for the subroutine name.
1098 SIZE is the number of bytes of arguments passed on the stack.
1099
1100 On the ARM, the caller does not pop any of its arguments that were passed
1101 on the stack. */
1102 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1103
1104 /* Define how to find the value returned by a library function
1105 assuming the value has mode MODE. */
1106 #define LIBCALL_VALUE(MODE) \
1107 (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \
1108 ? gen_rtx_REG (MODE, 16) \
1109 : gen_rtx_REG (MODE, 0))
1110
1111 /* Define how to find the value returned by a function.
1112 VALTYPE is the data type of the value (as a tree).
1113 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1114 otherwise, FUNC is 0. */
1115 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1116 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1117
1118 /* 1 if N is a possible register number for a function value.
1119 On the ARM, only r0 and f0 can return results. */
1120 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1121 ((REGNO) == 0 || (((REGNO) == 16) && TARGET_HARD_FLOAT))
1122
1123 /* How large values are returned */
1124 /* A C expression which can inhibit the returning of certain function values
1125 in registers, based on the type of value. */
1126 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1127
1128 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1129 values must be in memory. On the ARM, they need only do so if larger
1130 than a word, or if they contain elements offset from zero in the struct. */
1131 #define DEFAULT_PCC_STRUCT_RETURN 0
1132
1133 /* Define where to put the arguments to a function.
1134 Value is zero to push the argument on the stack,
1135 or a hard register in which to store the argument.
1136
1137 MODE is the argument's machine mode.
1138 TYPE is the data type of the argument (as a tree).
1139 This is null for libcalls where that information may
1140 not be available.
1141 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1142 the preceding args and about the function being called.
1143 NAMED is nonzero if this argument is a named parameter
1144 (otherwise it is an extra parameter matching an ellipsis).
1145
1146 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1147 other arguments are passed on the stack. If (NAMED == 0) (which happens
1148 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1149 passed in the stack (function_prologue will indeed make it pass in the
1150 stack if necessary). */
1151 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1152 ((NAMED) \
1153 ? ((CUM) >= NUM_ARG_REGS ? 0 : gen_rtx_REG (MODE, CUM))\
1154 : 0)
1155
1156 /* For an arg passed partly in registers and partly in memory,
1157 this is the number of registers used.
1158 For args passed entirely in registers or entirely in memory, zero. */
1159 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1160 ( NUM_ARG_REGS > (CUM) \
1161 && (NUM_ARG_REGS < ((CUM) + NUM_REGS2 (MODE, TYPE))) \
1162 ? NUM_ARG_REGS - (CUM) : 0)
1163
1164 /* A C type for declaring a variable that is used as the first argument of
1165 `FUNCTION_ARG' and other related values. For some target machines, the
1166 type `int' suffices and can hold the number of bytes of argument so far.
1167
1168 On the ARM, this is the number of bytes of arguments scanned so far. */
1169 #define CUMULATIVE_ARGS int
1170
1171 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1172 for a call to a function whose data type is FNTYPE.
1173 For a library call, FNTYPE is 0.
1174 On the ARM, the offset starts at 0. */
1175 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1176 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 1 : 0))
1177
1178 /* Update the data in CUM to advance over an argument
1179 of mode MODE and data type TYPE.
1180 (TYPE is null for libcalls where that information may not be available.) */
1181 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1182 (CUM) += NUM_REGS2 (MODE, TYPE)
1183
1184 /* 1 if N is a possible register number for function argument passing.
1185 On the ARM, r0-r3 are used to pass args. */
1186 #define FUNCTION_ARG_REGNO_P(REGNO) \
1187 ((REGNO) >= 0 && (REGNO) <= 3)
1188
1189 /* Perform any actions needed for a function that is receiving a variable
1190 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1191 of the current parameter. PRETEND_SIZE is a variable that should be set to
1192 the amount of stack that must be pushed by the prolog to pretend that our
1193 caller pushed it.
1194
1195 Normally, this macro will push all remaining incoming registers on the
1196 stack and set PRETEND_SIZE to the length of the registers pushed.
1197
1198 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1199 named arg and all anonymous args onto the stack.
1200 XXX I know the prologue shouldn't be pushing registers, but it is faster
1201 that way. */
1202 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1203 { \
1204 extern int current_function_anonymous_args; \
1205 current_function_anonymous_args = 1; \
1206 if ((CUM) < NUM_ARG_REGS) \
1207 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM)) * UNITS_PER_WORD; \
1208 }
1209
1210 /* Generate assembly output for the start of a function. */
1211 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
1212 output_func_prologue ((STREAM), (SIZE))
1213
1214 /* If your target environment doesn't prefix user functions with an
1215 underscore, you may wish to re-define this to prevent any conflicts.
1216 e.g. AOF may prefix mcount with an underscore. */
1217 #ifndef ARM_MCOUNT_NAME
1218 #define ARM_MCOUNT_NAME "*mcount"
1219 #endif
1220
1221 /* Call the function profiler with a given profile label. The Acorn
1222 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1223 On the ARM the full profile code will look like:
1224 .data
1225 LP1
1226 .word 0
1227 .text
1228 mov ip, lr
1229 bl mcount
1230 .word LP1
1231
1232 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1233 will output the .text section.
1234
1235 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1236 ``prof'' doesn't seem to mind about this! */
1237 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1238 { \
1239 char temp[20]; \
1240 rtx sym; \
1241 \
1242 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1243 IP_REGNUM, LR_REGNUM); \
1244 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1245 fputc ('\n', STREAM); \
1246 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1247 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1248 ASM_OUTPUT_INT (STREAM, sym); \
1249 }
1250
1251 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1252 the stack pointer does not matter. The value is tested only in
1253 functions that have frame pointers.
1254 No definition is equivalent to always zero.
1255
1256 On the ARM, the function epilogue recovers the stack pointer from the
1257 frame. */
1258 #define EXIT_IGNORE_STACK 1
1259
1260 /* Generate the assembly code for function exit. */
1261 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
1262 output_func_epilogue (STREAM, SIZE)
1263
1264 /* Determine if the epilogue should be output as RTL.
1265 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1266 #define USE_RETURN_INSN(ISCOND) use_return_insn (ISCOND)
1267
1268 /* Definitions for register eliminations.
1269
1270 This is an array of structures. Each structure initializes one pair
1271 of eliminable registers. The "from" register number is given first,
1272 followed by "to". Eliminations of the same "from" register are listed
1273 in order of preference.
1274
1275 We have two registers that can be eliminated on the ARM. First, the
1276 arg pointer register can often be eliminated in favor of the stack
1277 pointer register. Secondly, the pseudo frame pointer register can always
1278 be eliminated; it is replaced with either the stack or the real frame
1279 pointer. */
1280
1281 #define ELIMINABLE_REGS \
1282 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1283 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
1284 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1285 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }}
1286
1287 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1288 Frame pointer elimination is automatically handled.
1289
1290 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1291 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1292 pointer, we must eliminate FRAME_POINTER_REGNUM into
1293 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
1294 #define CAN_ELIMINATE(FROM, TO) \
1295 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
1296
1297 /* Define the offset between two registers, one to be eliminated, and the other
1298 its replacement, at the start of a routine. */
1299 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1300 { \
1301 int volatile_func = arm_volatile_func (); \
1302 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
1303 (OFFSET) = 0; \
1304 else if ((FROM) == FRAME_POINTER_REGNUM \
1305 && (TO) == STACK_POINTER_REGNUM) \
1306 (OFFSET) = current_function_outgoing_args_size \
1307 + ((get_frame_size () + 3) & ~3); \
1308 else \
1309 { \
1310 int regno; \
1311 int offset = 12; \
1312 int saved_hard_reg = 0; \
1313 \
1314 if (! volatile_func) \
1315 { \
1316 for (regno = 0; regno <= 10; regno++) \
1317 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1318 saved_hard_reg = 1, offset += 4; \
1319 /* PIC register is a fixed reg, so call_used_regs set. */ \
1320 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) \
1321 saved_hard_reg = 1, offset += 4; \
1322 for (regno = 16; regno <=23; regno++) \
1323 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1324 offset += 12; \
1325 } \
1326 if ((FROM) == FRAME_POINTER_REGNUM) \
1327 (OFFSET) = -offset; \
1328 else \
1329 { \
1330 if (! frame_pointer_needed) \
1331 offset -= 16; \
1332 if (! volatile_func \
1333 && (regs_ever_live[LR_REGNUM] || saved_hard_reg)) \
1334 offset += 4; \
1335 offset += current_function_outgoing_args_size; \
1336 (OFFSET) = ((get_frame_size () + 3) & ~3) + offset; \
1337 } \
1338 } \
1339 }
1340
1341 /* Output assembler code for a block containing the constant parts
1342 of a trampoline, leaving space for the variable parts.
1343
1344 On the ARM, (if r8 is the static chain regnum, and remembering that
1345 referencing pc adds an offset of 8) the trampoline looks like:
1346 ldr r8, [pc, #0]
1347 ldr pc, [pc]
1348 .word static chain value
1349 .word function's address
1350 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1351 #define TRAMPOLINE_TEMPLATE(FILE) \
1352 { \
1353 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \
1354 REGISTER_PREFIX, reg_names[STATIC_CHAIN_REGNUM], \
1355 REGISTER_PREFIX, reg_names[PC_REGNUM]); \
1356 fprintf ((FILE), "\tldr\t%s%s, [%s%s, #0]\n", \
1357 REGISTER_PREFIX, reg_names[PC_REGNUM], \
1358 REGISTER_PREFIX, reg_names[PC_REGNUM]); \
1359 ASM_OUTPUT_INT ((FILE), const0_rtx); \
1360 ASM_OUTPUT_INT ((FILE), const0_rtx); \
1361 }
1362
1363 /* Length in units of the trampoline for entering a nested function. */
1364 #define TRAMPOLINE_SIZE 16
1365
1366 /* Alignment required for a trampoline in units. */
1367 #define TRAMPOLINE_ALIGN 4
1368
1369 /* Emit RTL insns to initialize the variable parts of a trampoline.
1370 FNADDR is an RTX for the address of the function's pure code.
1371 CXT is an RTX for the static chain value for the function. */
1372 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1373 { \
1374 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
1375 (CXT)); \
1376 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
1377 (FNADDR)); \
1378 }
1379
1380 \f
1381 /* Addressing modes, and classification of registers for them. */
1382
1383 #define HAVE_POST_INCREMENT 1
1384 #define HAVE_PRE_INCREMENT 1
1385 #define HAVE_POST_DECREMENT 1
1386 #define HAVE_PRE_DECREMENT 1
1387
1388 /* Macros to check register numbers against specific register classes. */
1389
1390 /* These assume that REGNO is a hard or pseudo reg number.
1391 They give nonzero only if REGNO is a hard reg of the suitable class
1392 or a pseudo reg currently allocated to a suitable hard reg.
1393 Since they use reg_renumber, they are safe only once reg_renumber
1394 has been allocated, which happens in local-alloc.c.
1395
1396 On the ARM, don't allow the pc to be used. */
1397 #define REGNO_OK_FOR_BASE_P(REGNO) \
1398 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
1399 || (REGNO) == ARG_POINTER_REGNUM \
1400 || (unsigned) reg_renumber[(REGNO)] < 15 \
1401 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
1402 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
1403 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1404 REGNO_OK_FOR_BASE_P(REGNO)
1405
1406 /* Maximum number of registers that can appear in a valid memory address.
1407 Shifts in addresses can't be by a register. */
1408
1409 #define MAX_REGS_PER_ADDRESS 2
1410
1411 /* Recognize any constant value that is a valid address. */
1412 /* XXX We can address any constant, eventually... */
1413
1414 #ifdef AOF_ASSEMBLER
1415
1416 #define CONSTANT_ADDRESS_P(X) \
1417 (GET_CODE (X) == SYMBOL_REF \
1418 && CONSTANT_POOL_ADDRESS_P (X))
1419
1420 #else
1421
1422 #define CONSTANT_ADDRESS_P(X) \
1423 (GET_CODE (X) == SYMBOL_REF \
1424 && (CONSTANT_POOL_ADDRESS_P (X) \
1425 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
1426
1427 #endif /* AOF_ASSEMBLER */
1428
1429 /* Nonzero if the constant value X is a legitimate general operand.
1430 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1431
1432 On the ARM, allow any integer (invalid ones are removed later by insn
1433 patterns), nice doubles and symbol_refs which refer to the function's
1434 constant pool XXX. */
1435 #define LEGITIMATE_CONSTANT_P(X) (! label_mentioned_p (X))
1436
1437 /* Symbols in the text segment can be accessed without indirecting via the
1438 constant pool; it may take an extra binary operation, but this is still
1439 faster than indirecting via memory. Don't do this when not optimizing,
1440 since we won't be calculating al of the offsets necessary to do this
1441 simplification. */
1442 /* This doesn't work with AOF syntax, since the string table may be in
1443 a different AREA. */
1444 #ifndef AOF_ASSEMBLER
1445 #define ENCODE_SECTION_INFO(decl) \
1446 { \
1447 if (optimize > 0 && TREE_CONSTANT (decl) \
1448 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1449 { \
1450 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1451 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1452 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1453 } \
1454 }
1455 #endif
1456
1457 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1458 and check its validity for a certain class.
1459 We have two alternate definitions for each of them.
1460 The usual definition accepts all pseudo regs; the other rejects
1461 them unless they have been allocated suitable hard regs.
1462 The symbol REG_OK_STRICT causes the latter definition to be used. */
1463 #ifndef REG_OK_STRICT
1464
1465 /* Nonzero if X is a hard reg that can be used as a base reg
1466 or if it is a pseudo reg. */
1467 #define REG_OK_FOR_BASE_P(X) \
1468 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1469 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1470
1471 /* Nonzero if X is a hard reg that can be used as an index
1472 or if it is a pseudo reg. */
1473 #define REG_OK_FOR_INDEX_P(X) \
1474 REG_OK_FOR_BASE_P(X)
1475
1476 #define REG_OK_FOR_PRE_POST_P(X) \
1477 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1478 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
1479
1480 #else
1481
1482 /* Nonzero if X is a hard reg that can be used as a base reg. */
1483 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1484
1485 /* Nonzero if X is a hard reg that can be used as an index. */
1486 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1487
1488 #define REG_OK_FOR_PRE_POST_P(X) \
1489 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
1490 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
1491 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
1492 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
1493
1494 #endif
1495 \f
1496 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1497 that is a valid memory address for an instruction.
1498 The MODE argument is the machine mode for the MEM expression
1499 that wants to use this address.
1500
1501 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1502 #define BASE_REGISTER_RTX_P(X) \
1503 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
1504
1505 #define INDEX_REGISTER_RTX_P(X) \
1506 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
1507
1508 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
1509 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
1510 only be small constants. */
1511 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
1512 do \
1513 { \
1514 HOST_WIDE_INT range; \
1515 enum rtx_code code = GET_CODE (INDEX); \
1516 \
1517 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1518 { \
1519 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
1520 && INTVAL (INDEX) > -1024 \
1521 && (INTVAL (INDEX) & 3) == 0) \
1522 goto LABEL; \
1523 } \
1524 else \
1525 { \
1526 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
1527 goto LABEL; \
1528 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
1529 && (! arm_arch4 || (MODE) != HImode)) \
1530 { \
1531 rtx xiop0 = XEXP (INDEX, 0); \
1532 rtx xiop1 = XEXP (INDEX, 1); \
1533 if (INDEX_REGISTER_RTX_P (xiop0) \
1534 && power_of_two_operand (xiop1, SImode)) \
1535 goto LABEL; \
1536 if (INDEX_REGISTER_RTX_P (xiop1) \
1537 && power_of_two_operand (xiop0, SImode)) \
1538 goto LABEL; \
1539 } \
1540 if (GET_MODE_SIZE (MODE) <= 4 \
1541 && (code == LSHIFTRT || code == ASHIFTRT \
1542 || code == ASHIFT || code == ROTATERT) \
1543 && (! arm_arch4 || (MODE) != HImode)) \
1544 { \
1545 rtx op = XEXP (INDEX, 1); \
1546 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1547 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1548 && INTVAL (op) <= 31) \
1549 goto LABEL; \
1550 } \
1551 /* NASTY: Since this limits the addressing of unsigned byte loads */ \
1552 range = ((MODE) == HImode || (MODE) == QImode) \
1553 ? (arm_arch4 ? 256 : 4095) : 4096; \
1554 if (code == CONST_INT && INTVAL (INDEX) < range \
1555 && INTVAL (INDEX) > -range) \
1556 goto LABEL; \
1557 } \
1558 } \
1559 while (0)
1560
1561 /* Jump to LABEL if X is a valid address RTX. This must also take
1562 REG_OK_STRICT into account when deciding about valid registers, but it uses
1563 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1564 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1565 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1566 refs must be forced though a static cell to ensure addressability. */
1567 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1568 { \
1569 if (BASE_REGISTER_RTX_P (X)) \
1570 goto LABEL; \
1571 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1572 && GET_CODE (XEXP (X, 0)) == REG \
1573 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1574 goto LABEL; \
1575 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
1576 && (GET_CODE (X) == LABEL_REF \
1577 || (GET_CODE (X) == CONST \
1578 && GET_CODE (XEXP ((X), 0)) == PLUS \
1579 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
1580 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
1581 goto LABEL; \
1582 else if ((MODE) == TImode) \
1583 ; \
1584 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
1585 { \
1586 if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1587 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1588 { \
1589 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1590 if (val == 4 || val == -4 || val == -8) \
1591 goto LABEL; \
1592 } \
1593 } \
1594 else if (GET_CODE (X) == PLUS) \
1595 { \
1596 rtx xop0 = XEXP(X,0); \
1597 rtx xop1 = XEXP(X,1); \
1598 \
1599 if (BASE_REGISTER_RTX_P (xop0)) \
1600 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1601 else if (BASE_REGISTER_RTX_P (xop1)) \
1602 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1603 } \
1604 /* Reload currently can't handle MINUS, so disable this for now */ \
1605 /* else if (GET_CODE (X) == MINUS) \
1606 { \
1607 rtx xop0 = XEXP (X,0); \
1608 rtx xop1 = XEXP (X,1); \
1609 \
1610 if (BASE_REGISTER_RTX_P (xop0)) \
1611 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1612 } */ \
1613 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1614 && GET_CODE (X) == SYMBOL_REF \
1615 && CONSTANT_POOL_ADDRESS_P (X) \
1616 && ! (flag_pic \
1617 && symbol_mentioned_p (get_pool_constant (X)))) \
1618 goto LABEL; \
1619 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1620 && (GET_MODE_SIZE (MODE) <= 4) \
1621 && GET_CODE (XEXP (X, 0)) == REG \
1622 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1623 goto LABEL; \
1624 }
1625 \f
1626 /* Try machine-dependent ways of modifying an illegitimate address
1627 to be legitimate. If we find one, return the new, valid address.
1628 This macro is used in only one place: `memory_address' in explow.c.
1629
1630 OLDX is the address as it was before break_out_memory_refs was called.
1631 In some cases it is useful to look at this to decide what needs to be done.
1632
1633 MODE and WIN are passed so that this macro can use
1634 GO_IF_LEGITIMATE_ADDRESS.
1635
1636 It is always safe for this macro to do nothing. It exists to recognize
1637 opportunities to optimize the output.
1638
1639 On the ARM, try to convert [REG, #BIGCONST]
1640 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1641 where VALIDCONST == 0 in case of TImode. */
1642 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1643 { \
1644 if (GET_CODE (X) == PLUS) \
1645 { \
1646 rtx xop0 = XEXP (X, 0); \
1647 rtx xop1 = XEXP (X, 1); \
1648 \
1649 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
1650 xop0 = force_reg (SImode, xop0); \
1651 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1652 xop1 = force_reg (SImode, xop1); \
1653 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1654 { \
1655 HOST_WIDE_INT n, low_n; \
1656 rtx base_reg, val; \
1657 n = INTVAL (xop1); \
1658 \
1659 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1660 { \
1661 low_n = n & 0x0f; \
1662 n &= ~0x0f; \
1663 if (low_n > 4) \
1664 { \
1665 n += 16; \
1666 low_n -= 16; \
1667 } \
1668 } \
1669 else \
1670 { \
1671 low_n = ((MODE) == TImode ? 0 \
1672 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
1673 n -= low_n; \
1674 } \
1675 base_reg = gen_reg_rtx (SImode); \
1676 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
1677 GEN_INT (n)), NULL_RTX); \
1678 emit_move_insn (base_reg, val); \
1679 (X) = (low_n == 0 ? base_reg \
1680 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
1681 } \
1682 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
1683 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
1684 } \
1685 else if (GET_CODE (X) == MINUS) \
1686 { \
1687 rtx xop0 = XEXP (X, 0); \
1688 rtx xop1 = XEXP (X, 1); \
1689 \
1690 if (CONSTANT_P (xop0)) \
1691 xop0 = force_reg (SImode, xop0); \
1692 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
1693 xop1 = force_reg (SImode, xop1); \
1694 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
1695 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
1696 } \
1697 if (flag_pic) \
1698 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
1699 if (memory_address_p (MODE, X)) \
1700 goto WIN; \
1701 }
1702
1703 /* Go to LABEL if ADDR (a legitimate address expression)
1704 has an effect that depends on the machine mode it is used for. */
1705 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1706 { \
1707 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1708 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1709 goto LABEL; \
1710 }
1711 \f
1712 /* Specify the machine mode that this machine uses
1713 for the index in the tablejump instruction. */
1714 #define CASE_VECTOR_MODE SImode
1715
1716 /* Define as C expression which evaluates to nonzero if the tablejump
1717 instruction expects the table to contain offsets from the address of the
1718 table.
1719 Do not define this if the table should contain absolute addresses. */
1720 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1721
1722 /* Specify the tree operation to be used to convert reals to integers. */
1723 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1724
1725 /* This is the kind of divide that is easiest to do in the general case. */
1726 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1727
1728 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1729 unsigned is probably best, but may break some code. */
1730 #ifndef DEFAULT_SIGNED_CHAR
1731 #define DEFAULT_SIGNED_CHAR 0
1732 #endif
1733
1734 /* Don't cse the address of the function being compiled. */
1735 #define NO_RECURSIVE_FUNCTION_CSE 1
1736
1737 /* Max number of bytes we can move from memory to memory
1738 in one reasonably fast instruction. */
1739 #define MOVE_MAX 4
1740
1741 /* Define if operations between registers always perform the operation
1742 on the full register even if a narrower mode is specified. */
1743 #define WORD_REGISTER_OPERATIONS
1744
1745 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1746 will either zero-extend or sign-extend. The value of this macro should
1747 be the code that says which one of the two operations is implicitly
1748 done, NIL if none. */
1749 #define LOAD_EXTEND_OP(MODE) \
1750 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
1751 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))
1752
1753 /* Define this if zero-extension is slow (more than one real instruction).
1754 On the ARM, it is more than one instruction only if not fetching from
1755 memory. */
1756 /* #define SLOW_ZERO_EXTEND */
1757
1758 /* Nonzero if access to memory by bytes is slow and undesirable. */
1759 #define SLOW_BYTE_ACCESS 0
1760
1761 /* Immediate shift counts are truncated by the output routines (or was it
1762 the assembler?). Shift counts in a register are truncated by ARM. Note
1763 that the native compiler puts too large (> 32) immediate shift counts
1764 into a register and shifts by the register, letting the ARM decide what
1765 to do instead of doing that itself. */
1766 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1767 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1768 On the arm, Y in a register is used modulo 256 for the shift. Only for
1769 rotates is modulo 32 used. */
1770 /* #define SHIFT_COUNT_TRUNCATED 1 */
1771
1772 /* All integers have the same format so truncation is easy. */
1773 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1774
1775 /* Calling from registers is a massive pain. */
1776 #define NO_FUNCTION_CSE 1
1777
1778 /* Chars and shorts should be passed as ints. */
1779 #define PROMOTE_PROTOTYPES 1
1780
1781 /* The machine modes of pointers and functions */
1782 #define Pmode SImode
1783 #define FUNCTION_MODE Pmode
1784
1785 /* The structure type of the machine dependent info field of insns
1786 No uses for this yet. */
1787 /* #define INSN_MACHINE_INFO struct machine_info */
1788
1789 /* The relative costs of various types of constants. Note that cse.c defines
1790 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1791 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1792 case CONST_INT: \
1793 if (const_ok_for_arm (INTVAL (RTX))) \
1794 return (OUTER_CODE) == SET ? 2 : -1; \
1795 else if (OUTER_CODE == AND \
1796 && const_ok_for_arm (~INTVAL (RTX))) \
1797 return -1; \
1798 else if ((OUTER_CODE == COMPARE \
1799 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1800 && const_ok_for_arm (-INTVAL (RTX))) \
1801 return -1; \
1802 else \
1803 return 5; \
1804 case CONST: \
1805 case LABEL_REF: \
1806 case SYMBOL_REF: \
1807 return 6; \
1808 case CONST_DOUBLE: \
1809 if (const_double_rtx_ok_for_fpu (RTX)) \
1810 return (OUTER_CODE) == SET ? 2 : -1; \
1811 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1812 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1813 return -1; \
1814 return(7);
1815
1816 #define ARM_FRAME_RTX(X) \
1817 ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
1818 || (X) == arg_pointer_rtx)
1819
1820 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
1821 return arm_rtx_costs (X, CODE);
1822
1823 /* Moves to and from memory are quite expensive */
1824 #define MEMORY_MOVE_COST(MODE,CLASS,IN) 10
1825
1826 /* All address computations that can be done are free, but rtx cost returns
1827 the same for practically all of them. So we weight the different types
1828 of address here in the order (most pref first):
1829 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
1830 #define ADDRESS_COST(X) \
1831 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
1832 || GET_CODE (X) == SYMBOL_REF) \
1833 ? 0 \
1834 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
1835 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1836 ? 10 \
1837 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
1838 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
1839 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
1840 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
1841 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
1842 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
1843 ? 1 : 0)) \
1844 : 4)))))
1845
1846 /* Try to generate sequences that don't involve branches, we can then use
1847 conditional instructions */
1848 #define BRANCH_COST 4
1849
1850 /* A C statement to update the variable COST based on the relationship
1851 between INSN that is dependent on DEP through dependence LINK. */
1852 #define ADJUST_COST(INSN, LINK, DEP, COST) \
1853 (COST) = arm_adjust_cost (INSN, LINK, DEP, COST)
1854 \f
1855 /* Position Independent Code. */
1856 /* We decide which register to use based on the compilation options and
1857 the assembler in use; this is more general than the APCS restriction of
1858 using sb (r9) all the time. */
1859 extern int arm_pic_register;
1860
1861 /* Used when parsing command line option -mpic-register=. */
1862 extern const char * arm_pic_register_string;
1863
1864 /* The register number of the register used to address a table of static
1865 data addresses in memory. */
1866 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
1867
1868 #define FINALIZE_PIC arm_finalize_pic ()
1869
1870 /* We can't directly access anything that contains a symbol,
1871 nor can we indirect via the constant pool. */
1872 #define LEGITIMATE_PIC_OPERAND_P(X) \
1873 (! symbol_mentioned_p (X) \
1874 && (! CONSTANT_POOL_ADDRESS_P (X) \
1875 || ! symbol_mentioned_p (get_pool_constant (X))))
1876
1877 /* We need to know when we are making a constant pool; this determines
1878 whether data needs to be in the GOT or can be referenced via a GOT
1879 offset. */
1880 extern int making_const_table;
1881
1882 \f
1883 /* Condition code information. */
1884 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1885 return the mode to be used for the comparison.
1886 CCFPEmode should be used with floating inequalities,
1887 CCFPmode should be used with floating equalities.
1888 CC_NOOVmode should be used with SImode integer equalities.
1889 CC_Zmode should be used if only the Z flag is set correctly
1890 CCmode should be used otherwise. */
1891
1892 #define EXTRA_CC_MODES \
1893 CC(CC_NOOVmode, "CC_NOOV") \
1894 CC(CC_Zmode, "CC_Z") \
1895 CC(CC_SWPmode, "CC_SWP") \
1896 CC(CCFPmode, "CCFP") \
1897 CC(CCFPEmode, "CCFPE") \
1898 CC(CC_DNEmode, "CC_DNE") \
1899 CC(CC_DEQmode, "CC_DEQ") \
1900 CC(CC_DLEmode, "CC_DLE") \
1901 CC(CC_DLTmode, "CC_DLT") \
1902 CC(CC_DGEmode, "CC_DGE") \
1903 CC(CC_DGTmode, "CC_DGT") \
1904 CC(CC_DLEUmode, "CC_DLEU") \
1905 CC(CC_DLTUmode, "CC_DLTU") \
1906 CC(CC_DGEUmode, "CC_DGEU") \
1907 CC(CC_DGTUmode, "CC_DGTU") \
1908 CC(CC_Cmode, "CC_C")
1909
1910 #define SELECT_CC_MODE(OP,X,Y) arm_select_cc_mode ((OP), (X), (Y))
1911
1912 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1913
1914 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
1915 do \
1916 { \
1917 if (GET_CODE (OP1) == CONST_INT \
1918 && ! (const_ok_for_arm (INTVAL (OP1)) \
1919 || (const_ok_for_arm (- INTVAL (OP1))))) \
1920 { \
1921 rtx const_op = OP1; \
1922 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
1923 OP1 = const_op; \
1924 } \
1925 } \
1926 while (0)
1927
1928 #define STORE_FLAG_VALUE 1
1929
1930 /* Define the information needed to generate branch insns. This is
1931 stored from the compare operation. Note that we can't use "rtx" here
1932 since it hasn't been defined! */
1933
1934 extern struct rtx_def * arm_compare_op0;
1935 extern struct rtx_def * arm_compare_op1;
1936
1937 /* Define the codes that are matched by predicates in arm.c */
1938 #define PREDICATE_CODES \
1939 {"s_register_operand", {SUBREG, REG}}, \
1940 {"f_register_operand", {SUBREG, REG}}, \
1941 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1942 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1943 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1944 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1945 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1946 {"offsettable_memory_operand", {MEM}}, \
1947 {"bad_signed_byte_operand", {MEM}}, \
1948 {"alignable_memory_operand", {MEM}}, \
1949 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1950 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
1951 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
1952 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1953 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
1954 {"load_multiple_operation", {PARALLEL}}, \
1955 {"store_multiple_operation", {PARALLEL}}, \
1956 {"equality_operator", {EQ, NE}}, \
1957 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1958 {"const_shift_operand", {CONST_INT}}, \
1959 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1960 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
1961 {"multi_register_push", {PARALLEL}}, \
1962 {"cc_register", {REG}}, \
1963 {"dominant_cc_register", {REG}},
1964
1965 \f
1966
1967 /* Gcc puts the pool in the wrong place for ARM, since we can only
1968 load addresses a limited distance around the pc. We do some
1969 special munging to move the constant pool values to the correct
1970 point in the code. */
1971 #define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN))
1972
1973 /* Output an internal label definition. */
1974 #ifndef ASM_OUTPUT_INTERNAL_LABEL
1975 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1976 do \
1977 { \
1978 char * s = (char *) alloca (40 + strlen (PREFIX)); \
1979 \
1980 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1981 && !strcmp (PREFIX, "L")) \
1982 { \
1983 arm_ccfsm_state = 0; \
1984 arm_target_insn = NULL; \
1985 } \
1986 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
1987 ASM_OUTPUT_LABEL (STREAM, s); \
1988 } \
1989 while (0)
1990 #endif
1991
1992 /* Output a push or a pop instruction (only used when profiling). */
1993 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
1994 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", SP_REGNUM, REGNO)
1995
1996 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
1997 asm_fprintf (STREAM,"\tldmfd\t%r!,{%r}\n", SP_REGNUM, REGNO)
1998
1999 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2000 do \
2001 { \
2002 if (TARGET_POKE_FUNCTION_NAME) \
2003 arm_poke_function_name (STREAM, NAME); \
2004 } \
2005 while (0)
2006
2007 /* Target characters. */
2008 #define TARGET_BELL 007
2009 #define TARGET_BS 010
2010 #define TARGET_TAB 011
2011 #define TARGET_NEWLINE 012
2012 #define TARGET_VT 013
2013 #define TARGET_FF 014
2014 #define TARGET_CR 015
2015 \f
2016 /* Only perform branch elimination (by making instructions conditional) if
2017 we're optimising. Otherwise it's of no use anyway. */
2018 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2019 if (optimize) \
2020 arm_final_prescan_insn (INSN)
2021
2022 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2023 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
2024
2025 /* Output an operand of an instruction. */
2026 #define PRINT_OPERAND(STREAM, X, CODE) \
2027 arm_print_operand (STREAM, X, CODE)
2028
2029 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2030 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
2031 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
2032 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
2033 ? ((~ (HOST_WIDE_INT) 0) \
2034 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2035 : 0))))
2036
2037 /* Output the address of an operand. */
2038 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
2039 { \
2040 int is_minus = GET_CODE (X) == MINUS; \
2041 \
2042 if (GET_CODE (X) == REG) \
2043 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2044 else if (GET_CODE (X) == PLUS || is_minus) \
2045 { \
2046 rtx base = XEXP (X, 0); \
2047 rtx index = XEXP (X, 1); \
2048 int base_reg; \
2049 HOST_WIDE_INT offset = 0; \
2050 if (GET_CODE (base) != REG) \
2051 { \
2052 /* Ensure that BASE is a register (one of them must be). */ \
2053 rtx temp = base; \
2054 base = index; \
2055 index = temp; \
2056 } \
2057 base_reg = REGNO (base); \
2058 switch (GET_CODE (index)) \
2059 { \
2060 case CONST_INT: \
2061 offset = INTVAL (index); \
2062 if (is_minus) \
2063 offset = -offset; \
2064 asm_fprintf (STREAM, "[%r, #%d]", base_reg, offset); \
2065 break; \
2066 \
2067 case REG: \
2068 asm_fprintf (STREAM, "[%r, %s%r]", base_reg, \
2069 is_minus ? "-" : "", REGNO (index)); \
2070 break; \
2071 \
2072 case MULT: \
2073 case ASHIFTRT: \
2074 case LSHIFTRT: \
2075 case ASHIFT: \
2076 case ROTATERT: \
2077 { \
2078 asm_fprintf (STREAM, "[%r, %s%r", base_reg, \
2079 is_minus ? "-" : "", REGNO (XEXP (index, 0))); \
2080 arm_print_operand (STREAM, index, 'S'); \
2081 fputs ("]", STREAM); \
2082 break; \
2083 } \
2084 \
2085 default: \
2086 abort(); \
2087 } \
2088 } \
2089 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2090 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2091 { \
2092 extern int output_memory_reference_mode; \
2093 \
2094 if (GET_CODE (XEXP (X, 0)) != REG) \
2095 abort (); \
2096 \
2097 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2098 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2099 REGNO (XEXP (X, 0)), \
2100 GET_CODE (X) == PRE_DEC ? "-" : "", \
2101 GET_MODE_SIZE (output_memory_reference_mode)); \
2102 else \
2103 asm_fprintf (STREAM, "[%r], #%s%d", \
2104 REGNO (XEXP (X, 0)), \
2105 GET_CODE (X) == POST_DEC ? "-" : "", \
2106 GET_MODE_SIZE (output_memory_reference_mode)); \
2107 } \
2108 else output_addr_const (STREAM, X); \
2109 }
2110
2111 /* Handles PIC addr specially */
2112 #define OUTPUT_INT_ADDR_CONST(STREAM,X) \
2113 { \
2114 if (flag_pic && GET_CODE (X) == CONST && is_pic (X)) \
2115 { \
2116 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \
2117 fputs (" - (", STREAM); \
2118 output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \
2119 fputs (")", STREAM); \
2120 } \
2121 else output_addr_const (STREAM, X); \
2122 \
2123 /* Mark symbols as position independent. We only do this in the \
2124 .text segment, not in the .data segment. */ \
2125 if (NEED_GOT_RELOC && flag_pic && making_const_table && \
2126 (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) \
2127 { \
2128 if (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) \
2129 fprintf (STREAM, "(GOTOFF)"); \
2130 else if (GET_CODE (X) == LABEL_REF) \
2131 fprintf (STREAM, "(GOTOFF)"); \
2132 else \
2133 fprintf (STREAM, "(GOT)"); \
2134 } \
2135 }
2136
2137 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2138 Used for C++ multiple inheritance. */
2139 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2140 do \
2141 { \
2142 int mi_delta = (DELTA); \
2143 char * mi_op = mi_delta < 0 ? "sub" : "add"; \
2144 int shift = 0; \
2145 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2146 ? 1 : 0); \
2147 if (mi_delta < 0) mi_delta = -mi_delta; \
2148 while (mi_delta != 0) \
2149 { \
2150 if (mi_delta & (3 << shift) == 0) \
2151 shift += 2; \
2152 else \
2153 { \
2154 asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \
2155 mi_op, this_regno, this_regno, \
2156 mi_delta & (0xff << shift)); \
2157 mi_delta &= ~(0xff << shift); \
2158 shift += 8; \
2159 } \
2160 } \
2161 fputs ("\tb\t", FILE); \
2162 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2163 if (NEED_PLT_RELOC) \
2164 fputs ("(PLT)", FILE); \
2165 fputc ('\n', FILE); \
2166 } \
2167 while (0)
2168
2169 /* A C expression whose value is RTL representing the value of the return
2170 address for the frame COUNT steps up from the current frame. */
2171
2172 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2173 ((COUNT == 0) \
2174 ? gen_rtx_MEM (Pmode, plus_constant (FRAME, -4)) \
2175 : NULL_RTX)
2176
2177 /* Used to mask out junk bits from the return address, such as
2178 processor state, interrupt status, condition codes and the like. */
2179 #define MASK_RETURN_ADDR \
2180 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2181 in 26 bit mode, the condition codes must be masked out of the \
2182 return address. This does not apply to ARM6 and later processors \
2183 when running in 32 bit mode. */ \
2184 ((!TARGET_APCS_32) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff)))
2185
2186 /* The remainder of this file is only needed for building the compiler
2187 itself, not for the collateral. */
2188 #ifdef HAVE_CONFIG_H
2189
2190 /* Prototypes for functions in arm.c */
2191
2192 #ifdef BUFSIZ /* stdio.h has been included, ok to use FILE * */
2193 #define STDIO_PROTO(ARGS) PROTO (ARGS)
2194 #else
2195 #define STDIO_PROTO(ARGS) ()
2196 #endif
2197
2198 #ifndef TREE_CODE
2199 union tree_node;
2200 #define Tree union tree_node *
2201 #else
2202 #define Tree tree
2203 #endif
2204
2205 #ifndef RTX_CODE
2206 struct rtx_def;
2207 #define Rtx struct rtx_def *
2208 #else
2209 #define Rtx rtx
2210 #endif
2211
2212 #ifndef HOST_WIDE_INT
2213 #include "hwint.h"
2214 #endif
2215
2216
2217 #ifndef HAVE_MACHINE_MODES
2218 #include "machmode.h"
2219 #endif
2220
2221 #define Mmode enum machine_mode
2222
2223 #ifdef RTX_CODE
2224 #define RTX_CODE_PROTO(ARGS) PROTO (ARGS)
2225 #else
2226 #define RTX_CODE_PROTO(ARGS) ()
2227 #endif
2228
2229 #define Rcode enum rtx_code
2230
2231 void arm_override_options PROTO ((void));
2232 int use_return_insn PROTO ((int));
2233 int const_ok_for_arm PROTO ((HOST_WIDE_INT));
2234 int arm_split_constant RTX_CODE_PROTO ((Rcode, Mmode, HOST_WIDE_INT, Rtx,
2235 Rtx, int));
2236 Rcode arm_canonicalize_comparison RTX_CODE_PROTO ((Rcode, Rtx *));
2237 int arm_return_in_memory PROTO ((Tree));
2238 int legitimate_pic_operand_p PROTO ((Rtx));
2239 Rtx legitimize_pic_address PROTO ((Rtx, Mmode, Rtx));
2240 int is_pic PROTO ((Rtx));
2241 void arm_finalize_pic PROTO ((void));
2242 int arm_rtx_costs RTX_CODE_PROTO ((Rtx, Rcode));
2243 int arm_adjust_cost PROTO ((Rtx, Rtx, Rtx, int));
2244 int const_double_rtx_ok_for_fpu PROTO ((Rtx));
2245 int neg_const_double_rtx_ok_for_fpu PROTO ((Rtx));
2246 int s_register_operand PROTO ((Rtx, Mmode));
2247 int f_register_operand PROTO ((Rtx, Mmode));
2248 int reg_or_int_operand PROTO ((Rtx, Mmode));
2249 int reload_memory_operand PROTO ((Rtx, Mmode));
2250 int arm_rhs_operand PROTO ((Rtx, Mmode));
2251 int arm_rhsm_operand PROTO ((Rtx, Mmode));
2252 int arm_add_operand PROTO ((Rtx, Mmode));
2253 int arm_not_operand PROTO ((Rtx, Mmode));
2254 int offsettable_memory_operand PROTO ((Rtx, Mmode));
2255 int alignable_memory_operand PROTO ((Rtx, Mmode));
2256 int bad_signed_byte_operand PROTO ((Rtx, Mmode));
2257 int fpu_rhs_operand PROTO ((Rtx, Mmode));
2258 int fpu_add_operand PROTO ((Rtx, Mmode));
2259 int power_of_two_operand PROTO ((Rtx, Mmode));
2260 int di_operand PROTO ((Rtx, Mmode));
2261 int soft_df_operand PROTO ((Rtx, Mmode));
2262 int index_operand PROTO ((Rtx, Mmode));
2263 int const_shift_operand PROTO ((Rtx, Mmode));
2264 int shiftable_operator PROTO ((Rtx, Mmode));
2265 int shift_operator PROTO ((Rtx, Mmode));
2266 int equality_operator PROTO ((Rtx, Mmode));
2267 int minmax_operator PROTO ((Rtx, Mmode));
2268 int cc_register PROTO ((Rtx, Mmode));
2269 int dominant_cc_register PROTO ((Rtx, Mmode));
2270 int symbol_mentioned_p PROTO ((Rtx));
2271 int label_mentioned_p PROTO ((Rtx));
2272 Rcode minmax_code PROTO ((Rtx));
2273 int adjacent_mem_locations PROTO ((Rtx, Rtx));
2274 int load_multiple_operation PROTO ((Rtx, Mmode));
2275 int store_multiple_operation PROTO ((Rtx, Mmode));
2276 int load_multiple_sequence PROTO ((Rtx *, int, int *, int *,
2277 HOST_WIDE_INT *));
2278 char * emit_ldm_seq PROTO ((Rtx *, int));
2279 int store_multiple_sequence PROTO ((Rtx *, int, int *, int *,
2280 HOST_WIDE_INT *));
2281 char * emit_stm_seq PROTO ((Rtx *, int));
2282 int arm_valid_machine_decl_attribute PROTO ((Tree, Tree, Tree));
2283 Rtx arm_gen_load_multiple PROTO ((int, int, Rtx, int, int, int, int, int));
2284 Rtx arm_gen_store_multiple PROTO ((int, int, Rtx, int, int, int, int, int));
2285 int arm_gen_movstrqi PROTO ((Rtx *));
2286 Rtx gen_rotated_half_load PROTO ((Rtx));
2287 Mmode arm_select_cc_mode RTX_CODE_PROTO ((Rcode, Rtx, Rtx));
2288 Rtx gen_compare_reg RTX_CODE_PROTO ((Rcode, Rtx, Rtx, int));
2289 void arm_reload_in_hi PROTO ((Rtx *));
2290 void arm_reload_out_hi PROTO ((Rtx *));
2291 void arm_reorg PROTO ((Rtx));
2292 char * fp_immediate_constant PROTO ((Rtx));
2293 void print_multi_reg STDIO_PROTO ((FILE *, char *, int, int));
2294 char * output_call PROTO ((Rtx *));
2295 char * output_call_mem PROTO ((Rtx *));
2296 char * output_mov_long_double_fpu_from_arm PROTO ((Rtx *));
2297 char * output_mov_long_double_arm_from_fpu PROTO ((Rtx *));
2298 char * output_mov_long_double_arm_from_arm PROTO ((Rtx *));
2299 char * output_mov_double_fpu_from_arm PROTO ((Rtx *));
2300 char * output_mov_double_arm_from_fpu PROTO ((Rtx *));
2301 char * output_move_double PROTO ((Rtx *));
2302 char * output_mov_immediate PROTO ((Rtx *));
2303 char * output_add_immediate PROTO ((Rtx *));
2304 char * arithmetic_instr PROTO ((Rtx, int));
2305 void output_ascii_pseudo_op STDIO_PROTO ((FILE *, unsigned char *, int));
2306 char * output_return_instruction PROTO ((Rtx, int, int));
2307 int arm_volatile_func PROTO ((void));
2308 void arm_poke_function_name STDIO_PROTO ((FILE *, char *));
2309 void output_func_prologue STDIO_PROTO ((FILE *, int));
2310 void output_func_epilogue STDIO_PROTO ((FILE *, int));
2311 void arm_expand_prologue PROTO ((void));
2312 char * arm_output_epilogue PROTO ((void));
2313 void arm_print_operand STDIO_PROTO ((FILE *, Rtx, int));
2314 void arm_final_prescan_insn PROTO ((Rtx));
2315 int short_branch PROTO ((int, int));
2316 void assemble_align PROTO((int)); /* Used in arm.md, but defined in output.c */
2317 int multi_register_push PROTO ((Rtx, Mmode));
2318 #ifdef AOF_ASSEMBLER
2319 Rtx aof_pic_entry PROTO ((Rtx));
2320 void aof_dump_pic_table STDIO_PROTO ((FILE *));
2321 char * aof_text_section PROTO ((void));
2322 char * aof_data_section PROTO ((void));
2323 void aof_add_import PROTO ((char *));
2324 void aof_delete_import PROTO ((char *));
2325 void aof_dump_imports STDIO_PROTO ((FILE *));
2326 #endif
2327 #endif /* HAVE_CONFIG_H */
2328
2329 #endif /* __ARM_H__ */
GNU Compiler Collection
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