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1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991-2015 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6 Minor hacks by Nick Clifton (nickc@cygnus.com)
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 3, or (at your
13 option) any later version.
14
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
19
20 Under Section 7 of GPL version 3, you are granted additional
21 permissions described in the GCC Runtime Library Exception, version
22 3.1, as published by the Free Software Foundation.
23
24 You should have received a copy of the GNU General Public License and
25 a copy of the GCC Runtime Library Exception along with this program;
26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
27 <http://www.gnu.org/licenses/>. */
28
29 #ifndef GCC_ARM_H
30 #define GCC_ARM_H
31
32 /* We can't use machine_mode inside a generator file because it
33 hasn't been created yet; we shouldn't be using any code that
34 needs the real definition though, so this ought to be safe. */
35 #ifdef GENERATOR_FILE
36 #define MACHMODE int
37 #else
38 #include "insn-modes.h"
39 #define MACHMODE machine_mode
40 #endif
41
42 #include "config/vxworks-dummy.h"
43
44 /* The architecture define. */
45 extern char arm_arch_name[];
46
47 /* Target CPU builtins. */
48 #define TARGET_CPU_CPP_BUILTINS() \
49 do \
50 { \
51 if (TARGET_DSP_MULTIPLY) \
52 builtin_define ("__ARM_FEATURE_DSP"); \
53 if (TARGET_ARM_QBIT) \
54 builtin_define ("__ARM_FEATURE_QBIT"); \
55 if (TARGET_ARM_SAT) \
56 builtin_define ("__ARM_FEATURE_SAT"); \
57 if (TARGET_CRYPTO) \
58 builtin_define ("__ARM_FEATURE_CRYPTO"); \
59 if (unaligned_access) \
60 builtin_define ("__ARM_FEATURE_UNALIGNED"); \
61 if (TARGET_CRC32) \
62 builtin_define ("__ARM_FEATURE_CRC32"); \
63 if (TARGET_32BIT) \
64 builtin_define ("__ARM_32BIT_STATE"); \
65 if (TARGET_ARM_FEATURE_LDREX) \
66 builtin_define_with_int_value ( \
67 "__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); \
68 if ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB) \
69 || TARGET_ARM_ARCH_ISA_THUMB >=2) \
70 builtin_define ("__ARM_FEATURE_CLZ"); \
71 if (TARGET_INT_SIMD) \
72 builtin_define ("__ARM_FEATURE_SIMD32"); \
73 \
74 builtin_define_with_int_value ( \
75 "__ARM_SIZEOF_MINIMAL_ENUM", \
76 flag_short_enums ? 1 : 4); \
77 builtin_define_type_sizeof ("__ARM_SIZEOF_WCHAR_T", \
78 wchar_type_node); \
79 if (TARGET_ARM_ARCH_PROFILE) \
80 builtin_define_with_int_value ( \
81 "__ARM_ARCH_PROFILE", TARGET_ARM_ARCH_PROFILE); \
82 \
83 /* Define __arm__ even when in thumb mode, for \
84 consistency with armcc. */ \
85 builtin_define ("__arm__"); \
86 if (TARGET_ARM_ARCH) \
87 builtin_define_with_int_value ( \
88 "__ARM_ARCH", TARGET_ARM_ARCH); \
89 if (arm_arch_notm) \
90 builtin_define ("__ARM_ARCH_ISA_ARM"); \
91 builtin_define ("__APCS_32__"); \
92 if (TARGET_THUMB) \
93 builtin_define ("__thumb__"); \
94 if (TARGET_THUMB2) \
95 builtin_define ("__thumb2__"); \
96 if (TARGET_ARM_ARCH_ISA_THUMB) \
97 builtin_define_with_int_value ( \
98 "__ARM_ARCH_ISA_THUMB", \
99 TARGET_ARM_ARCH_ISA_THUMB); \
100 \
101 if (TARGET_BIG_END) \
102 { \
103 builtin_define ("__ARMEB__"); \
104 builtin_define ("__ARM_BIG_ENDIAN"); \
105 if (TARGET_THUMB) \
106 builtin_define ("__THUMBEB__"); \
107 } \
108 else \
109 { \
110 builtin_define ("__ARMEL__"); \
111 if (TARGET_THUMB) \
112 builtin_define ("__THUMBEL__"); \
113 } \
114 \
115 if (TARGET_SOFT_FLOAT) \
116 builtin_define ("__SOFTFP__"); \
117 \
118 if (TARGET_VFP) \
119 builtin_define ("__VFP_FP__"); \
120 \
121 if (TARGET_ARM_FP) \
122 builtin_define_with_int_value ( \
123 "__ARM_FP", TARGET_ARM_FP); \
124 if (arm_fp16_format == ARM_FP16_FORMAT_IEEE) \
125 builtin_define ("__ARM_FP16_FORMAT_IEEE"); \
126 if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) \
127 builtin_define ("__ARM_FP16_FORMAT_ALTERNATIVE"); \
128 if (TARGET_FMA) \
129 builtin_define ("__ARM_FEATURE_FMA"); \
130 \
131 if (TARGET_NEON) \
132 { \
133 builtin_define ("__ARM_NEON__"); \
134 builtin_define ("__ARM_NEON"); \
135 } \
136 if (TARGET_NEON_FP) \
137 builtin_define_with_int_value ( \
138 "__ARM_NEON_FP", TARGET_NEON_FP); \
139 \
140 /* Add a define for interworking. \
141 Needed when building libgcc.a. */ \
142 if (arm_cpp_interwork) \
143 builtin_define ("__THUMB_INTERWORK__"); \
144 \
145 builtin_assert ("cpu=arm"); \
146 builtin_assert ("machine=arm"); \
147 \
148 builtin_define (arm_arch_name); \
149 if (arm_arch_xscale) \
150 builtin_define ("__XSCALE__"); \
151 if (arm_arch_iwmmxt) \
152 { \
153 builtin_define ("__IWMMXT__"); \
154 builtin_define ("__ARM_WMMX"); \
155 } \
156 if (arm_arch_iwmmxt2) \
157 builtin_define ("__IWMMXT2__"); \
158 if (TARGET_AAPCS_BASED) \
159 { \
160 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \
161 builtin_define ("__ARM_PCS_VFP"); \
162 else if (arm_pcs_default == ARM_PCS_AAPCS) \
163 builtin_define ("__ARM_PCS"); \
164 builtin_define ("__ARM_EABI__"); \
165 } \
166 if (TARGET_IDIV) \
167 { \
168 builtin_define ("__ARM_ARCH_EXT_IDIV__"); \
169 builtin_define ("__ARM_FEATURE_IDIV"); \
170 } \
171 if (inline_asm_unified) \
172 builtin_define ("__ARM_ASM_SYNTAX_UNIFIED__");\
173 } while (0)
174
175 #include "config/arm/arm-opts.h"
176
177 enum target_cpus
178 {
179 #define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \
180 TARGET_CPU_##INTERNAL_IDENT,
181 #include "arm-cores.def"
182 #undef ARM_CORE
183 TARGET_CPU_generic
184 };
185
186 /* The processor for which instructions should be scheduled. */
187 extern enum processor_type arm_tune;
188
189 typedef enum arm_cond_code
190 {
191 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
192 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
193 }
194 arm_cc;
195
196 extern arm_cc arm_current_cc;
197
198 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
199
200 /* The maximum number of instructions that is beneficial to
201 conditionally execute. */
202 #undef MAX_CONDITIONAL_EXECUTE
203 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute ()
204
205 extern int arm_target_label;
206 extern int arm_ccfsm_state;
207 extern GTY(()) rtx arm_target_insn;
208 /* The label of the current constant pool. */
209 extern rtx pool_vector_label;
210 /* Set to 1 when a return insn is output, this means that the epilogue
211 is not needed. */
212 extern int return_used_this_function;
213 /* Callback to output language specific object attributes. */
214 extern void (*arm_lang_output_object_attributes_hook)(void);
215 \f
216 /* Just in case configure has failed to define anything. */
217 #ifndef TARGET_CPU_DEFAULT
218 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
219 #endif
220
221
222 #undef CPP_SPEC
223 #define CPP_SPEC "%(subtarget_cpp_spec) \
224 %{mfloat-abi=soft:%{mfloat-abi=hard: \
225 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \
226 %{mbig-endian:%{mlittle-endian: \
227 %e-mbig-endian and -mlittle-endian may not be used together}}"
228
229 #ifndef CC1_SPEC
230 #define CC1_SPEC ""
231 #endif
232
233 /* This macro defines names of additional specifications to put in the specs
234 that can be used in various specifications like CC1_SPEC. Its definition
235 is an initializer with a subgrouping for each command option.
236
237 Each subgrouping contains a string constant, that defines the
238 specification name, and a string constant that used by the GCC driver
239 program.
240
241 Do not define this macro if it does not need to do anything. */
242 #define EXTRA_SPECS \
243 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
244 { "asm_cpu_spec", ASM_CPU_SPEC }, \
245 SUBTARGET_EXTRA_SPECS
246
247 #ifndef SUBTARGET_EXTRA_SPECS
248 #define SUBTARGET_EXTRA_SPECS
249 #endif
250
251 #ifndef SUBTARGET_CPP_SPEC
252 #define SUBTARGET_CPP_SPEC ""
253 #endif
254 \f
255 /* Run-time Target Specification. */
256 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
257 /* Use hardware floating point instructions. */
258 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
259 /* Use hardware floating point calling convention. */
260 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
261 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
262 #define TARGET_IWMMXT (arm_arch_iwmmxt)
263 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2)
264 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
265 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT)
266 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
267 #define TARGET_ARM (! TARGET_THUMB)
268 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
269 #define TARGET_BACKTRACE (leaf_function_p () \
270 ? TARGET_TPCS_LEAF_FRAME \
271 : TARGET_TPCS_FRAME)
272 #define TARGET_AAPCS_BASED \
273 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
274
275 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
276 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
277 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2)
278
279 /* Only 16-bit thumb code. */
280 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
281 /* Arm or Thumb-2 32-bit code. */
282 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
283 /* 32-bit Thumb-2 code. */
284 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
285 /* Thumb-1 only. */
286 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
287
288 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \
289 && !TARGET_THUMB1)
290
291 #define TARGET_CRC32 (arm_arch_crc)
292
293 /* The following two macros concern the ability to execute coprocessor
294 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
295 only ever tested when we know we are generating for VFP hardware; we need
296 to be more careful with TARGET_NEON as noted below. */
297
298 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
299 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
300
301 /* FPU supports VFPv3 instructions. */
302 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
303
304 /* FPU supports FPv5 instructions. */
305 #define TARGET_VFP5 (TARGET_VFP && arm_fpu_desc->rev >= 5)
306
307 /* FPU only supports VFP single-precision instructions. */
308 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
309
310 /* FPU supports VFP double-precision instructions. */
311 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
312
313 /* FPU supports half-precision floating-point with NEON element load/store. */
314 #define TARGET_NEON_FP16 \
315 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
316
317 /* FPU supports VFP half-precision floating-point. */
318 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
319
320 /* FPU supports fused-multiply-add operations. */
321 #define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4)
322
323 /* FPU is ARMv8 compatible. */
324 #define TARGET_FPU_ARMV8 (TARGET_VFP && arm_fpu_desc->rev >= 8)
325
326 /* FPU supports Crypto extensions. */
327 #define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto)
328
329 /* FPU supports Neon instructions. The setting of this macro gets
330 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
331 and TARGET_HARD_FLOAT to ensure that NEON instructions are
332 available. */
333 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
334 && TARGET_VFP && arm_fpu_desc->neon)
335
336 /* Q-bit is present. */
337 #define TARGET_ARM_QBIT \
338 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7))
339 /* Saturation operation, e.g. SSAT. */
340 #define TARGET_ARM_SAT \
341 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7))
342 /* "DSP" multiply instructions, eg. SMULxy. */
343 #define TARGET_DSP_MULTIPLY \
344 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
345 /* Integer SIMD instructions, and extend-accumulate instructions. */
346 #define TARGET_INT_SIMD \
347 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
348
349 /* Should MOVW/MOVT be used in preference to a constant pool. */
350 #define TARGET_USE_MOVT \
351 (arm_arch_thumb2 \
352 && (arm_disable_literal_pool \
353 || (!optimize_size && !current_tune->prefer_constant_pool)))
354
355 /* We could use unified syntax for arm mode, but for now we just use it
356 for thumb mode. */
357 #define TARGET_UNIFIED_ASM (TARGET_THUMB)
358
359 /* Nonzero if this chip provides the DMB instruction. */
360 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7)
361
362 /* Nonzero if this chip implements a memory barrier via CP15. */
363 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \
364 && ! TARGET_THUMB1)
365
366 /* Nonzero if this chip implements a memory barrier instruction. */
367 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
368
369 /* Nonzero if this chip supports ldrex and strex */
370 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
371
372 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */
373 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7)
374
375 /* Nonzero if this chip supports ldrexd and strexd. */
376 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \
377 && arm_arch_notm)
378
379 /* Nonzero if this chip supports load-acquire and store-release. */
380 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8)
381
382 /* Nonzero if integer division instructions supported. */
383 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \
384 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv))
385
386 /* Should NEON be used for 64-bits bitops. */
387 #define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits)
388
389 /* True iff the full BPABI is being used. If TARGET_BPABI is true,
390 then TARGET_AAPCS_BASED must be true -- but the converse does not
391 hold. TARGET_BPABI implies the use of the BPABI runtime library,
392 etc., in addition to just the AAPCS calling conventions. */
393 #ifndef TARGET_BPABI
394 #define TARGET_BPABI false
395 #endif
396
397 /* Support for a compile-time default CPU, et cetera. The rules are:
398 --with-arch is ignored if -march or -mcpu are specified.
399 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
400 by --with-arch.
401 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
402 by -march).
403 --with-float is ignored if -mfloat-abi is specified.
404 --with-fpu is ignored if -mfpu is specified.
405 --with-abi is ignored if -mabi is specified.
406 --with-tls is ignored if -mtls-dialect is specified. */
407 #define OPTION_DEFAULT_SPECS \
408 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
409 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
410 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
411 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \
412 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
413 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
414 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \
415 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"},
416
417 /* Which floating point model to use. */
418 enum arm_fp_model
419 {
420 ARM_FP_MODEL_UNKNOWN,
421 /* VFP floating point model. */
422 ARM_FP_MODEL_VFP
423 };
424
425 enum vfp_reg_type
426 {
427 VFP_NONE = 0,
428 VFP_REG_D16,
429 VFP_REG_D32,
430 VFP_REG_SINGLE
431 };
432
433 extern const struct arm_fpu_desc
434 {
435 const char *name;
436 enum arm_fp_model model;
437 int rev;
438 enum vfp_reg_type regs;
439 int neon;
440 int fp16;
441 int crypto;
442 } *arm_fpu_desc;
443
444 /* Which floating point hardware to schedule for. */
445 extern int arm_fpu_attr;
446
447 #ifndef TARGET_DEFAULT_FLOAT_ABI
448 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
449 #endif
450
451 #ifndef ARM_DEFAULT_ABI
452 #define ARM_DEFAULT_ABI ARM_ABI_APCS
453 #endif
454
455 /* Map each of the micro-architecture variants to their corresponding
456 major architecture revision. */
457
458 enum base_architecture
459 {
460 BASE_ARCH_0 = 0,
461 BASE_ARCH_2 = 2,
462 BASE_ARCH_3 = 3,
463 BASE_ARCH_3M = 3,
464 BASE_ARCH_4 = 4,
465 BASE_ARCH_4T = 4,
466 BASE_ARCH_5 = 5,
467 BASE_ARCH_5E = 5,
468 BASE_ARCH_5T = 5,
469 BASE_ARCH_5TE = 5,
470 BASE_ARCH_5TEJ = 5,
471 BASE_ARCH_6 = 6,
472 BASE_ARCH_6J = 6,
473 BASE_ARCH_6ZK = 6,
474 BASE_ARCH_6K = 6,
475 BASE_ARCH_6T2 = 6,
476 BASE_ARCH_6M = 6,
477 BASE_ARCH_6Z = 6,
478 BASE_ARCH_7 = 7,
479 BASE_ARCH_7A = 7,
480 BASE_ARCH_7R = 7,
481 BASE_ARCH_7M = 7,
482 BASE_ARCH_7EM = 7,
483 BASE_ARCH_8A = 8
484 };
485
486 /* The major revision number of the ARM Architecture implemented by the target. */
487 extern enum base_architecture arm_base_arch;
488
489 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
490 extern int arm_arch3m;
491
492 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
493 extern int arm_arch4;
494
495 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */
496 extern int arm_arch4t;
497
498 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
499 extern int arm_arch5;
500
501 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
502 extern int arm_arch5e;
503
504 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
505 extern int arm_arch6;
506
507 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */
508 extern int arm_arch6k;
509
510 /* Nonzero if instructions present in ARMv6-M can be used. */
511 extern int arm_arch6m;
512
513 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */
514 extern int arm_arch7;
515
516 /* Nonzero if instructions not present in the 'M' profile can be used. */
517 extern int arm_arch_notm;
518
519 /* Nonzero if instructions present in ARMv7E-M can be used. */
520 extern int arm_arch7em;
521
522 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */
523 extern int arm_arch8;
524
525 /* Nonzero if this chip can benefit from load scheduling. */
526 extern int arm_ld_sched;
527
528 /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */
529 extern int thumb_code;
530
531 /* Nonzero if generating Thumb-1 code. */
532 extern int thumb1_code;
533
534 /* Nonzero if this chip is a StrongARM. */
535 extern int arm_tune_strongarm;
536
537 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
538 extern int arm_arch_iwmmxt;
539
540 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */
541 extern int arm_arch_iwmmxt2;
542
543 /* Nonzero if this chip is an XScale. */
544 extern int arm_arch_xscale;
545
546 /* Nonzero if tuning for XScale. */
547 extern int arm_tune_xscale;
548
549 /* Nonzero if tuning for stores via the write buffer. */
550 extern int arm_tune_wbuf;
551
552 /* Nonzero if tuning for Cortex-A9. */
553 extern int arm_tune_cortex_a9;
554
555 /* Nonzero if we should define __THUMB_INTERWORK__ in the
556 preprocessor.
557 XXX This is a bit of a hack, it's intended to help work around
558 problems in GLD which doesn't understand that armv5t code is
559 interworking clean. */
560 extern int arm_cpp_interwork;
561
562 /* Nonzero if chip supports Thumb 2. */
563 extern int arm_arch_thumb2;
564
565 /* Nonzero if chip supports integer division instruction in ARM mode. */
566 extern int arm_arch_arm_hwdiv;
567
568 /* Nonzero if chip supports integer division instruction in Thumb mode. */
569 extern int arm_arch_thumb_hwdiv;
570
571 /* Nonzero if we should use Neon to handle 64-bits operations rather
572 than core registers. */
573 extern int prefer_neon_for_64bits;
574
575 /* Nonzero if we shouldn't use literal pools. */
576 #ifndef USED_FOR_TARGET
577 extern bool arm_disable_literal_pool;
578 #endif
579
580 /* Nonzero if chip supports the ARMv8 CRC instructions. */
581 extern int arm_arch_crc;
582
583 #ifndef TARGET_DEFAULT
584 #define TARGET_DEFAULT (MASK_APCS_FRAME)
585 #endif
586
587 /* Nonzero if PIC code requires explicit qualifiers to generate
588 PLT and GOT relocs rather than the assembler doing so implicitly.
589 Subtargets can override these if required. */
590 #ifndef NEED_GOT_RELOC
591 #define NEED_GOT_RELOC 0
592 #endif
593 #ifndef NEED_PLT_RELOC
594 #define NEED_PLT_RELOC 0
595 #endif
596
597 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE
598 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1
599 #endif
600
601 /* Nonzero if we need to refer to the GOT with a PC-relative
602 offset. In other words, generate
603
604 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
605
606 rather than
607
608 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
609
610 The default is true, which matches NetBSD. Subtargets can
611 override this if required. */
612 #ifndef GOT_PCREL
613 #define GOT_PCREL 1
614 #endif
615 \f
616 /* Target machine storage Layout. */
617
618
619 /* Define this macro if it is advisable to hold scalars in registers
620 in a wider mode than that declared by the program. In such cases,
621 the value is constrained to be within the bounds of the declared
622 type, but kept valid in the wider mode. The signedness of the
623 extension may differ from that of the type. */
624
625 /* It is far faster to zero extend chars than to sign extend them */
626
627 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
628 if (GET_MODE_CLASS (MODE) == MODE_INT \
629 && GET_MODE_SIZE (MODE) < 4) \
630 { \
631 if (MODE == QImode) \
632 UNSIGNEDP = 1; \
633 else if (MODE == HImode) \
634 UNSIGNEDP = 1; \
635 (MODE) = SImode; \
636 }
637
638 /* Define this if most significant bit is lowest numbered
639 in instructions that operate on numbered bit-fields. */
640 #define BITS_BIG_ENDIAN 0
641
642 /* Define this if most significant byte of a word is the lowest numbered.
643 Most ARM processors are run in little endian mode, so that is the default.
644 If you want to have it run-time selectable, change the definition in a
645 cover file to be TARGET_BIG_ENDIAN. */
646 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
647
648 /* Define this if most significant word of a multiword number is the lowest
649 numbered. */
650 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
651
652 #define UNITS_PER_WORD 4
653
654 /* True if natural alignment is used for doubleword types. */
655 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
656
657 #define DOUBLEWORD_ALIGNMENT 64
658
659 #define PARM_BOUNDARY 32
660
661 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
662
663 #define PREFERRED_STACK_BOUNDARY \
664 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
665
666 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
667
668 /* The lowest bit is used to indicate Thumb-mode functions, so the
669 vbit must go into the delta field of pointers to member
670 functions. */
671 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
672
673 #define EMPTY_FIELD_BOUNDARY 32
674
675 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
676
677 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT
678
679 /* XXX Blah -- this macro is used directly by libobjc. Since it
680 supports no vector modes, cut out the complexity and fall back
681 on BIGGEST_FIELD_ALIGNMENT. */
682 #ifdef IN_TARGET_LIBS
683 #define BIGGEST_FIELD_ALIGNMENT 64
684 #endif
685
686 /* Make strings word-aligned so strcpy from constants will be faster. */
687 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
688
689 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
690 ((TREE_CODE (EXP) == STRING_CST \
691 && !optimize_size \
692 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
693 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
694
695 /* Align definitions of arrays, unions and structures so that
696 initializations and copies can be made more efficient. This is not
697 ABI-changing, so it only affects places where we can see the
698 definition. Increasing the alignment tends to introduce padding,
699 so don't do this when optimizing for size/conserving stack space. */
700 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \
701 (((COND) && ((ALIGN) < BITS_PER_WORD) \
702 && (TREE_CODE (EXP) == ARRAY_TYPE \
703 || TREE_CODE (EXP) == UNION_TYPE \
704 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
705
706 /* Align global data. */
707 #define DATA_ALIGNMENT(EXP, ALIGN) \
708 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN)
709
710 /* Similarly, make sure that objects on the stack are sensibly aligned. */
711 #define LOCAL_ALIGNMENT(EXP, ALIGN) \
712 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN)
713
714 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
715 value set in previous versions of this toolchain was 8, which produces more
716 compact structures. The command line option -mstructure_size_boundary=<n>
717 can be used to change this value. For compatibility with the ARM SDK
718 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
719 0020D) page 2-20 says "Structures are aligned on word boundaries".
720 The AAPCS specifies a value of 8. */
721 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
722
723 /* This is the value used to initialize arm_structure_size_boundary. If a
724 particular arm target wants to change the default value it should change
725 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
726 for an example of this. */
727 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
728 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
729 #endif
730
731 /* Nonzero if move instructions will actually fail to work
732 when given unaligned data. */
733 #define STRICT_ALIGNMENT 1
734
735 /* wchar_t is unsigned under the AAPCS. */
736 #ifndef WCHAR_TYPE
737 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
738
739 #define WCHAR_TYPE_SIZE BITS_PER_WORD
740 #endif
741
742 /* Sized for fixed-point types. */
743
744 #define SHORT_FRACT_TYPE_SIZE 8
745 #define FRACT_TYPE_SIZE 16
746 #define LONG_FRACT_TYPE_SIZE 32
747 #define LONG_LONG_FRACT_TYPE_SIZE 64
748
749 #define SHORT_ACCUM_TYPE_SIZE 16
750 #define ACCUM_TYPE_SIZE 32
751 #define LONG_ACCUM_TYPE_SIZE 64
752 #define LONG_LONG_ACCUM_TYPE_SIZE 64
753
754 #define MAX_FIXED_MODE_SIZE 64
755
756 #ifndef SIZE_TYPE
757 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
758 #endif
759
760 #ifndef PTRDIFF_TYPE
761 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
762 #endif
763
764 /* AAPCS requires that structure alignment is affected by bitfields. */
765 #ifndef PCC_BITFIELD_TYPE_MATTERS
766 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
767 #endif
768
769 \f
770 /* Standard register usage. */
771
772 /* Register allocation in ARM Procedure Call Standard
773 (S - saved over call).
774
775 r0 * argument word/integer result
776 r1-r3 argument word
777
778 r4-r8 S register variable
779 r9 S (rfp) register variable (real frame pointer)
780
781 r10 F S (sl) stack limit (used by -mapcs-stack-check)
782 r11 F S (fp) argument pointer
783 r12 (ip) temp workspace
784 r13 F S (sp) lower end of current stack frame
785 r14 (lr) link address/workspace
786 r15 F (pc) program counter
787
788 cc This is NOT a real register, but is used internally
789 to represent things that use or set the condition
790 codes.
791 sfp This isn't either. It is used during rtl generation
792 since the offset between the frame pointer and the
793 auto's isn't known until after register allocation.
794 afp Nor this, we only need this because of non-local
795 goto. Without it fp appears to be used and the
796 elimination code won't get rid of sfp. It tracks
797 fp exactly at all times.
798
799 *: See TARGET_CONDITIONAL_REGISTER_USAGE */
800
801 /* s0-s15 VFP scratch (aka d0-d7).
802 s16-s31 S VFP variable (aka d8-d15).
803 vfpcc Not a real register. Represents the VFP condition
804 code flags. */
805
806 /* The stack backtrace structure is as follows:
807 fp points to here: | save code pointer | [fp]
808 | return link value | [fp, #-4]
809 | return sp value | [fp, #-8]
810 | return fp value | [fp, #-12]
811 [| saved r10 value |]
812 [| saved r9 value |]
813 [| saved r8 value |]
814 [| saved r7 value |]
815 [| saved r6 value |]
816 [| saved r5 value |]
817 [| saved r4 value |]
818 [| saved r3 value |]
819 [| saved r2 value |]
820 [| saved r1 value |]
821 [| saved r0 value |]
822 r0-r3 are not normally saved in a C function. */
823
824 /* 1 for registers that have pervasive standard uses
825 and are not available for the register allocator. */
826 #define FIXED_REGISTERS \
827 { \
828 /* Core regs. */ \
829 0,0,0,0,0,0,0,0, \
830 0,0,0,0,0,1,0,1, \
831 /* VFP regs. */ \
832 1,1,1,1,1,1,1,1, \
833 1,1,1,1,1,1,1,1, \
834 1,1,1,1,1,1,1,1, \
835 1,1,1,1,1,1,1,1, \
836 1,1,1,1,1,1,1,1, \
837 1,1,1,1,1,1,1,1, \
838 1,1,1,1,1,1,1,1, \
839 1,1,1,1,1,1,1,1, \
840 /* IWMMXT regs. */ \
841 1,1,1,1,1,1,1,1, \
842 1,1,1,1,1,1,1,1, \
843 1,1,1,1, \
844 /* Specials. */ \
845 1,1,1,1 \
846 }
847
848 /* 1 for registers not available across function calls.
849 These must include the FIXED_REGISTERS and also any
850 registers that can be used without being saved.
851 The latter must include the registers where values are returned
852 and the register where structure-value addresses are passed.
853 Aside from that, you can include as many other registers as you like.
854 The CC is not preserved over function calls on the ARM 6, so it is
855 easier to assume this for all. SFP is preserved, since FP is. */
856 #define CALL_USED_REGISTERS \
857 { \
858 /* Core regs. */ \
859 1,1,1,1,0,0,0,0, \
860 0,0,0,0,1,1,1,1, \
861 /* VFP Regs. */ \
862 1,1,1,1,1,1,1,1, \
863 1,1,1,1,1,1,1,1, \
864 1,1,1,1,1,1,1,1, \
865 1,1,1,1,1,1,1,1, \
866 1,1,1,1,1,1,1,1, \
867 1,1,1,1,1,1,1,1, \
868 1,1,1,1,1,1,1,1, \
869 1,1,1,1,1,1,1,1, \
870 /* IWMMXT regs. */ \
871 1,1,1,1,1,1,1,1, \
872 1,1,1,1,1,1,1,1, \
873 1,1,1,1, \
874 /* Specials. */ \
875 1,1,1,1 \
876 }
877
878 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
879 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
880 #endif
881
882 /* These are a couple of extensions to the formats accepted
883 by asm_fprintf:
884 %@ prints out ASM_COMMENT_START
885 %r prints out REGISTER_PREFIX reg_names[arg] */
886 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
887 case '@': \
888 fputs (ASM_COMMENT_START, FILE); \
889 break; \
890 \
891 case 'r': \
892 fputs (REGISTER_PREFIX, FILE); \
893 fputs (reg_names [va_arg (ARGS, int)], FILE); \
894 break;
895
896 /* Round X up to the nearest word. */
897 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
898
899 /* Convert fron bytes to ints. */
900 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
901
902 /* The number of (integer) registers required to hold a quantity of type MODE.
903 Also used for VFP registers. */
904 #define ARM_NUM_REGS(MODE) \
905 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
906
907 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
908 #define ARM_NUM_REGS2(MODE, TYPE) \
909 ARM_NUM_INTS ((MODE) == BLKmode ? \
910 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
911
912 /* The number of (integer) argument register available. */
913 #define NUM_ARG_REGS 4
914
915 /* And similarly for the VFP. */
916 #define NUM_VFP_ARG_REGS 16
917
918 /* Return the register number of the N'th (integer) argument. */
919 #define ARG_REGISTER(N) (N - 1)
920
921 /* Specify the registers used for certain standard purposes.
922 The values of these macros are register numbers. */
923
924 /* The number of the last argument register. */
925 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
926
927 /* The numbers of the Thumb register ranges. */
928 #define FIRST_LO_REGNUM 0
929 #define LAST_LO_REGNUM 7
930 #define FIRST_HI_REGNUM 8
931 #define LAST_HI_REGNUM 11
932
933 /* Overridden by config/arm/bpabi.h. */
934 #ifndef ARM_UNWIND_INFO
935 #define ARM_UNWIND_INFO 0
936 #endif
937
938 /* Use r0 and r1 to pass exception handling information. */
939 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
940
941 /* The register that holds the return address in exception handlers. */
942 #define ARM_EH_STACKADJ_REGNUM 2
943 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
944
945 #ifndef ARM_TARGET2_DWARF_FORMAT
946 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel
947 #endif
948
949 /* ttype entries (the only interesting data references used)
950 use TARGET2 relocations. */
951 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \
952 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \
953 : DW_EH_PE_absptr)
954
955 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
956 as an invisible last argument (possible since varargs don't exist in
957 Pascal), so the following is not true. */
958 #define STATIC_CHAIN_REGNUM 12
959
960 /* Define this to be where the real frame pointer is if it is not possible to
961 work out the offset between the frame pointer and the automatic variables
962 until after register allocation has taken place. FRAME_POINTER_REGNUM
963 should point to a special register that we will make sure is eliminated.
964
965 For the Thumb we have another problem. The TPCS defines the frame pointer
966 as r11, and GCC believes that it is always possible to use the frame pointer
967 as base register for addressing purposes. (See comments in
968 find_reloads_address()). But - the Thumb does not allow high registers,
969 including r11, to be used as base address registers. Hence our problem.
970
971 The solution used here, and in the old thumb port is to use r7 instead of
972 r11 as the hard frame pointer and to have special code to generate
973 backtrace structures on the stack (if required to do so via a command line
974 option) using r11. This is the only 'user visible' use of r11 as a frame
975 pointer. */
976 #define ARM_HARD_FRAME_POINTER_REGNUM 11
977 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
978
979 #define HARD_FRAME_POINTER_REGNUM \
980 (TARGET_ARM \
981 ? ARM_HARD_FRAME_POINTER_REGNUM \
982 : THUMB_HARD_FRAME_POINTER_REGNUM)
983
984 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
985 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
986
987 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
988
989 /* Register to use for pushing function arguments. */
990 #define STACK_POINTER_REGNUM SP_REGNUM
991
992 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1)
993 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15)
994
995 /* Need to sync with WCGR in iwmmxt.md. */
996 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1)
997 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3)
998
999 #define IS_IWMMXT_REGNUM(REGNUM) \
1000 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1001 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
1002 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1003
1004 /* Base register for access to local variables of the function. */
1005 #define FRAME_POINTER_REGNUM 102
1006
1007 /* Base register for access to arguments of the function. */
1008 #define ARG_POINTER_REGNUM 103
1009
1010 #define FIRST_VFP_REGNUM 16
1011 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15)
1012 #define LAST_VFP_REGNUM \
1013 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
1014
1015 #define IS_VFP_REGNUM(REGNUM) \
1016 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1017
1018 /* VFP registers are split into two types: those defined by VFP versions < 3
1019 have D registers overlaid on consecutive pairs of S registers. VFP version 3
1020 defines 16 new D registers (d16-d31) which, for simplicity and correctness
1021 in various parts of the backend, we implement as "fake" single-precision
1022 registers (which would be S32-S63, but cannot be used in that way). The
1023 following macros define these ranges of registers. */
1024 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31)
1025 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1)
1026 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31)
1027
1028 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
1029 ((REGNUM) <= LAST_LO_VFP_REGNUM)
1030
1031 /* DFmode values are only valid in even register pairs. */
1032 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
1033 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
1034
1035 /* Neon Quad values must start at a multiple of four registers. */
1036 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
1037 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
1038
1039 /* Neon structures of vectors must be in even register pairs and there
1040 must be enough registers available. Because of various patterns
1041 requiring quad registers, we require them to start at a multiple of
1042 four. */
1043 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1044 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1045 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1046
1047 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */
1048 /* Intel Wireless MMX Technology registers add 16 + 4 more. */
1049 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
1050 #define FIRST_PSEUDO_REGISTER 104
1051
1052 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1053
1054 /* Value should be nonzero if functions must have frame pointers.
1055 Zero means the frame pointer need not be set up (and parms may be accessed
1056 via the stack pointer) in functions that seem suitable.
1057 If we have to have a frame pointer we might as well make use of it.
1058 APCS says that the frame pointer does not need to be pushed in leaf
1059 functions, or simple tail call functions. */
1060
1061 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1062 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1063 #endif
1064
1065 /* Return number of consecutive hard regs needed starting at reg REGNO
1066 to hold something of mode MODE.
1067 This is ordinarily the length in words of a value of mode MODE
1068 but can be less for certain modes in special long registers.
1069
1070 On the ARM core regs are UNITS_PER_WORD bits wide. */
1071 #define HARD_REGNO_NREGS(REGNO, MODE) \
1072 ((TARGET_32BIT \
1073 && REGNO > PC_REGNUM \
1074 && REGNO != FRAME_POINTER_REGNUM \
1075 && REGNO != ARG_POINTER_REGNUM) \
1076 && !IS_VFP_REGNUM (REGNO) \
1077 ? 1 : ARM_NUM_REGS (MODE))
1078
1079 /* Return true if REGNO is suitable for holding a quantity of type MODE. */
1080 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1081 arm_hard_regno_mode_ok ((REGNO), (MODE))
1082
1083 #define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2)
1084
1085 #define VALID_IWMMXT_REG_MODE(MODE) \
1086 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
1087
1088 /* Modes valid for Neon D registers. */
1089 #define VALID_NEON_DREG_MODE(MODE) \
1090 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1091 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode)
1092
1093 /* Modes valid for Neon Q registers. */
1094 #define VALID_NEON_QREG_MODE(MODE) \
1095 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1096 || (MODE) == V4SFmode || (MODE) == V2DImode)
1097
1098 /* Structure modes valid for Neon registers. */
1099 #define VALID_NEON_STRUCT_MODE(MODE) \
1100 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1101 || (MODE) == CImode || (MODE) == XImode)
1102
1103 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */
1104 extern int arm_regs_in_sequence[];
1105
1106 /* The order in which register should be allocated. It is good to use ip
1107 since no saving is required (though calls clobber it) and it never contains
1108 function parameters. It is quite good to use lr since other calls may
1109 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1110 least likely to contain a function parameter; in addition results are
1111 returned in r0.
1112 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1113 then D8-D15. The reason for doing this is to attempt to reduce register
1114 pressure when both single- and double-precision registers are used in a
1115 function. */
1116
1117 #define VREG(X) (FIRST_VFP_REGNUM + (X))
1118 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X))
1119 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X))
1120
1121 #define REG_ALLOC_ORDER \
1122 { \
1123 /* General registers. */ \
1124 3, 2, 1, 0, 12, 14, 4, 5, \
1125 6, 7, 8, 9, 10, 11, \
1126 /* High VFP registers. */ \
1127 VREG(32), VREG(33), VREG(34), VREG(35), \
1128 VREG(36), VREG(37), VREG(38), VREG(39), \
1129 VREG(40), VREG(41), VREG(42), VREG(43), \
1130 VREG(44), VREG(45), VREG(46), VREG(47), \
1131 VREG(48), VREG(49), VREG(50), VREG(51), \
1132 VREG(52), VREG(53), VREG(54), VREG(55), \
1133 VREG(56), VREG(57), VREG(58), VREG(59), \
1134 VREG(60), VREG(61), VREG(62), VREG(63), \
1135 /* VFP argument registers. */ \
1136 VREG(15), VREG(14), VREG(13), VREG(12), \
1137 VREG(11), VREG(10), VREG(9), VREG(8), \
1138 VREG(7), VREG(6), VREG(5), VREG(4), \
1139 VREG(3), VREG(2), VREG(1), VREG(0), \
1140 /* VFP call-saved registers. */ \
1141 VREG(16), VREG(17), VREG(18), VREG(19), \
1142 VREG(20), VREG(21), VREG(22), VREG(23), \
1143 VREG(24), VREG(25), VREG(26), VREG(27), \
1144 VREG(28), VREG(29), VREG(30), VREG(31), \
1145 /* IWMMX registers. */ \
1146 WREG(0), WREG(1), WREG(2), WREG(3), \
1147 WREG(4), WREG(5), WREG(6), WREG(7), \
1148 WREG(8), WREG(9), WREG(10), WREG(11), \
1149 WREG(12), WREG(13), WREG(14), WREG(15), \
1150 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \
1151 /* Registers not for general use. */ \
1152 CC_REGNUM, VFPCC_REGNUM, \
1153 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
1154 SP_REGNUM, PC_REGNUM \
1155 }
1156
1157 /* Use different register alloc ordering for Thumb. */
1158 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1159
1160 /* Tell IRA to use the order we define rather than messing it up with its
1161 own cost calculations. */
1162 #define HONOR_REG_ALLOC_ORDER 1
1163
1164 /* Interrupt functions can only use registers that have already been
1165 saved by the prologue, even if they would normally be
1166 call-clobbered. */
1167 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1168 (! IS_INTERRUPT (cfun->machine->func_type) || \
1169 df_regs_ever_live_p (DST))
1170 \f
1171 /* Register and constant classes. */
1172
1173 /* Register classes. */
1174 enum reg_class
1175 {
1176 NO_REGS,
1177 LO_REGS,
1178 STACK_REG,
1179 BASE_REGS,
1180 HI_REGS,
1181 CALLER_SAVE_REGS,
1182 GENERAL_REGS,
1183 CORE_REGS,
1184 VFP_D0_D7_REGS,
1185 VFP_LO_REGS,
1186 VFP_HI_REGS,
1187 VFP_REGS,
1188 IWMMXT_REGS,
1189 IWMMXT_GR_REGS,
1190 CC_REG,
1191 VFPCC_REG,
1192 SFP_REG,
1193 AFP_REG,
1194 ALL_REGS,
1195 LIM_REG_CLASSES
1196 };
1197
1198 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1199
1200 /* Give names of register classes as strings for dump file. */
1201 #define REG_CLASS_NAMES \
1202 { \
1203 "NO_REGS", \
1204 "LO_REGS", \
1205 "STACK_REG", \
1206 "BASE_REGS", \
1207 "HI_REGS", \
1208 "CALLER_SAVE_REGS", \
1209 "GENERAL_REGS", \
1210 "CORE_REGS", \
1211 "VFP_D0_D7_REGS", \
1212 "VFP_LO_REGS", \
1213 "VFP_HI_REGS", \
1214 "VFP_REGS", \
1215 "IWMMXT_REGS", \
1216 "IWMMXT_GR_REGS", \
1217 "CC_REG", \
1218 "VFPCC_REG", \
1219 "SFP_REG", \
1220 "AFP_REG", \
1221 "ALL_REGS" \
1222 }
1223
1224 /* Define which registers fit in which classes.
1225 This is an initializer for a vector of HARD_REG_SET
1226 of length N_REG_CLASSES. */
1227 #define REG_CLASS_CONTENTS \
1228 { \
1229 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1230 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1231 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1232 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1233 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1234 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \
1235 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1236 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1237 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1238 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \
1239 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \
1240 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \
1241 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \
1242 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \
1243 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \
1244 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \
1245 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
1246 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
1247 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS */ \
1248 }
1249
1250 /* Any of the VFP register classes. */
1251 #define IS_VFP_CLASS(X) \
1252 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1253 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1254
1255 /* The same information, inverted:
1256 Return the class number of the smallest class containing
1257 reg number REGNO. This could be a conditional expression
1258 or could index an array. */
1259 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1260
1261 /* In VFPv1, VFP registers could only be accessed in the mode they
1262 were set, so subregs would be invalid there. However, we don't
1263 support VFPv1 at the moment, and the restriction was lifted in
1264 VFPv2.
1265 In big-endian mode, modes greater than word size (i.e. DFmode) are stored in
1266 VFP registers in little-endian order. We can't describe that accurately to
1267 GCC, so avoid taking subregs of such values.
1268 The only exception is going from a 128-bit to a 64-bit type. In that case
1269 the data layout happens to be consistent for big-endian, so we explicitly allow
1270 that case. */
1271 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1272 (TARGET_VFP && TARGET_BIG_END \
1273 && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \
1274 && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \
1275 || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \
1276 && reg_classes_intersect_p (VFP_REGS, (CLASS)))
1277
1278 /* The class value for index registers, and the one for base regs. */
1279 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1280 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
1281
1282 /* For the Thumb the high registers cannot be used as base registers
1283 when addressing quantities in QI or HI mode; if we don't know the
1284 mode, then we must be conservative. */
1285 #define MODE_BASE_REG_CLASS(MODE) \
1286 (arm_lra_flag \
1287 ? (TARGET_32BIT ? CORE_REGS \
1288 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \
1289 : LO_REGS) \
1290 : ((TARGET_ARM || (TARGET_THUMB2 && !optimize_size)) ? CORE_REGS \
1291 : ((MODE) == SImode) ? BASE_REGS \
1292 : LO_REGS))
1293
1294 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1295 instead of BASE_REGS. */
1296 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
1297
1298 /* When this hook returns true for MODE, the compiler allows
1299 registers explicitly used in the rtl to be used as spill registers
1300 but prevents the compiler from extending the lifetime of these
1301 registers. */
1302 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1303 arm_small_register_classes_for_mode_p
1304
1305 /* Must leave BASE_REGS reloads alone */
1306 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1307 (lra_in_progress ? NO_REGS \
1308 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1309 ? ((true_regnum (X) == -1 ? LO_REGS \
1310 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1311 : NO_REGS)) \
1312 : NO_REGS))
1313
1314 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1315 (lra_in_progress ? NO_REGS \
1316 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1317 ? ((true_regnum (X) == -1 ? LO_REGS \
1318 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1319 : NO_REGS)) \
1320 : NO_REGS)
1321
1322 /* Return the register class of a scratch register needed to copy IN into
1323 or out of a register in CLASS in MODE. If it can be done directly,
1324 NO_REGS is returned. */
1325 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1326 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1327 ((TARGET_VFP && TARGET_HARD_FLOAT \
1328 && IS_VFP_CLASS (CLASS)) \
1329 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1330 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1331 ? coproc_secondary_reload_class (MODE, X, TRUE) \
1332 : TARGET_32BIT \
1333 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1334 ? GENERAL_REGS : NO_REGS) \
1335 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1336
1337 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1338 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1339 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
1340 ((TARGET_VFP && TARGET_HARD_FLOAT \
1341 && IS_VFP_CLASS (CLASS)) \
1342 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1343 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1344 coproc_secondary_reload_class (MODE, X, TRUE) : \
1345 (TARGET_32BIT ? \
1346 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1347 && CONSTANT_P (X)) \
1348 ? GENERAL_REGS : \
1349 (((MODE) == HImode && ! arm_arch4 \
1350 && (MEM_P (X) \
1351 || ((REG_P (X) || GET_CODE (X) == SUBREG) \
1352 && true_regnum (X) == -1))) \
1353 ? GENERAL_REGS : NO_REGS) \
1354 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
1355
1356 /* Try a machine-dependent way of reloading an illegitimate address
1357 operand. If we find one, push the reload and jump to WIN. This
1358 macro is used in only one place: `find_reloads_address' in reload.c.
1359
1360 For the ARM, we wish to handle large displacements off a base
1361 register by splitting the addend across a MOV and the mem insn.
1362 This can cut the number of reloads needed. */
1363 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1364 do \
1365 { \
1366 if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \
1367 goto WIN; \
1368 } \
1369 while (0)
1370
1371 /* XXX If an HImode FP+large_offset address is converted to an HImode
1372 SP+large_offset address, then reload won't know how to fix it. It sees
1373 only that SP isn't valid for HImode, and so reloads the SP into an index
1374 register, but the resulting address is still invalid because the offset
1375 is too big. We fix it here instead by reloading the entire address. */
1376 /* We could probably achieve better results by defining PROMOTE_MODE to help
1377 cope with the variances between the Thumb's signed and unsigned byte and
1378 halfword load instructions. */
1379 /* ??? This should be safe for thumb2, but we may be able to do better. */
1380 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1381 do { \
1382 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1383 if (new_x) \
1384 { \
1385 X = new_x; \
1386 goto WIN; \
1387 } \
1388 } while (0)
1389
1390 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1391 if (TARGET_ARM) \
1392 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1393 else \
1394 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1395
1396 /* Return the maximum number of consecutive registers
1397 needed to represent mode MODE in a register of class CLASS.
1398 ARM regs are UNITS_PER_WORD bits.
1399 FIXME: Is this true for iWMMX? */
1400 #define CLASS_MAX_NREGS(CLASS, MODE) \
1401 (ARM_NUM_REGS (MODE))
1402
1403 /* If defined, gives a class of registers that cannot be used as the
1404 operand of a SUBREG that changes the mode of the object illegally. */
1405 \f
1406 /* Stack layout; function entry, exit and calling. */
1407
1408 /* Define this if pushing a word on the stack
1409 makes the stack pointer a smaller address. */
1410 #define STACK_GROWS_DOWNWARD 1
1411
1412 /* Define this to nonzero if the nominal address of the stack frame
1413 is at the high-address end of the local variables;
1414 that is, each additional local variable allocated
1415 goes at a more negative offset in the frame. */
1416 #define FRAME_GROWS_DOWNWARD 1
1417
1418 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1419 When present, it is one word in size, and sits at the top of the frame,
1420 between the soft frame pointer and either r7 or r11.
1421
1422 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1423 and only then if some outgoing arguments are passed on the stack. It would
1424 be tempting to also check whether the stack arguments are passed by indirect
1425 calls, but there seems to be no reason in principle why a post-reload pass
1426 couldn't convert a direct call into an indirect one. */
1427 #define CALLER_INTERWORKING_SLOT_SIZE \
1428 (TARGET_CALLER_INTERWORKING \
1429 && crtl->outgoing_args_size != 0 \
1430 ? UNITS_PER_WORD : 0)
1431
1432 /* Offset within stack frame to start allocating local variables at.
1433 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1434 first local allocated. Otherwise, it is the offset to the BEGINNING
1435 of the first local allocated. */
1436 #define STARTING_FRAME_OFFSET 0
1437
1438 /* If we generate an insn to push BYTES bytes,
1439 this says how many the stack pointer really advances by. */
1440 /* The push insns do not do this rounding implicitly.
1441 So don't define this. */
1442 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
1443
1444 /* Define this if the maximum size of all the outgoing args is to be
1445 accumulated and pushed during the prologue. The amount can be
1446 found in the variable crtl->outgoing_args_size. */
1447 #define ACCUMULATE_OUTGOING_ARGS 1
1448
1449 /* Offset of first parameter from the argument pointer register value. */
1450 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1451
1452 /* Amount of memory needed for an untyped call to save all possible return
1453 registers. */
1454 #define APPLY_RESULT_SIZE arm_apply_result_size()
1455
1456 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1457 values must be in memory. On the ARM, they need only do so if larger
1458 than a word, or if they contain elements offset from zero in the struct. */
1459 #define DEFAULT_PCC_STRUCT_RETURN 0
1460
1461 /* These bits describe the different types of function supported
1462 by the ARM backend. They are exclusive. i.e. a function cannot be both a
1463 normal function and an interworked function, for example. Knowing the
1464 type of a function is important for determining its prologue and
1465 epilogue sequences.
1466 Note value 7 is currently unassigned. Also note that the interrupt
1467 function types all have bit 2 set, so that they can be tested for easily.
1468 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1469 machine_function structure is initialized (to zero) func_type will
1470 default to unknown. This will force the first use of arm_current_func_type
1471 to call arm_compute_func_type. */
1472 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1473 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1474 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1475 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1476 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1477 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1478
1479 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1480
1481 /* In addition functions can have several type modifiers,
1482 outlined by these bit masks: */
1483 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1484 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1485 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1486 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1487 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
1488
1489 /* Some macros to test these flags. */
1490 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1491 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1492 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1493 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1494 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1495 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
1496
1497
1498 /* Structure used to hold the function stack frame layout. Offsets are
1499 relative to the stack pointer on function entry. Positive offsets are
1500 in the direction of stack growth.
1501 Only soft_frame is used in thumb mode. */
1502
1503 typedef struct GTY(()) arm_stack_offsets
1504 {
1505 int saved_args; /* ARG_POINTER_REGNUM. */
1506 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1507 int saved_regs;
1508 int soft_frame; /* FRAME_POINTER_REGNUM. */
1509 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
1510 int outgoing_args; /* STACK_POINTER_REGNUM. */
1511 unsigned int saved_regs_mask;
1512 }
1513 arm_stack_offsets;
1514
1515 #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET)
1516 /* A C structure for machine-specific, per-function data.
1517 This is added to the cfun structure. */
1518 typedef struct GTY(()) machine_function
1519 {
1520 /* Additional stack adjustment in __builtin_eh_throw. */
1521 rtx eh_epilogue_sp_ofs;
1522 /* Records if LR has to be saved for far jumps. */
1523 int far_jump_used;
1524 /* Records if ARG_POINTER was ever live. */
1525 int arg_pointer_live;
1526 /* Records if the save of LR has been eliminated. */
1527 int lr_save_eliminated;
1528 /* The size of the stack frame. Only valid after reload. */
1529 arm_stack_offsets stack_offsets;
1530 /* Records the type of the current function. */
1531 unsigned long func_type;
1532 /* Record if the function has a variable argument list. */
1533 int uses_anonymous_args;
1534 /* Records if sibcalls are blocked because an argument
1535 register is needed to preserve stack alignment. */
1536 int sibcall_blocked;
1537 /* The PIC register for this function. This might be a pseudo. */
1538 rtx pic_reg;
1539 /* Labels for per-function Thumb call-via stubs. One per potential calling
1540 register. We can never call via LR or PC. We can call via SP if a
1541 trampoline happens to be on the top of the stack. */
1542 rtx call_via[14];
1543 /* Set to 1 when a return insn is output, this means that the epilogue
1544 is not needed. */
1545 int return_used_this_function;
1546 /* When outputting Thumb-1 code, record the last insn that provides
1547 information about condition codes, and the comparison operands. */
1548 rtx thumb1_cc_insn;
1549 rtx thumb1_cc_op0;
1550 rtx thumb1_cc_op1;
1551 /* Also record the CC mode that is supported. */
1552 machine_mode thumb1_cc_mode;
1553 /* Set to 1 after arm_reorg has started. */
1554 int after_arm_reorg;
1555 }
1556 machine_function;
1557 #endif
1558
1559 /* As in the machine_function, a global set of call-via labels, for code
1560 that is in text_section. */
1561 extern GTY(()) rtx thumb_call_via_label[14];
1562
1563 /* The number of potential ways of assigning to a co-processor. */
1564 #define ARM_NUM_COPROC_SLOTS 1
1565
1566 /* Enumeration of procedure calling standard variants. We don't really
1567 support all of these yet. */
1568 enum arm_pcs
1569 {
1570 ARM_PCS_AAPCS, /* Base standard AAPCS. */
1571 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */
1572 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */
1573 /* This must be the last AAPCS variant. */
1574 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */
1575 ARM_PCS_ATPCS, /* ATPCS. */
1576 ARM_PCS_APCS, /* APCS (legacy Linux etc). */
1577 ARM_PCS_UNKNOWN
1578 };
1579
1580 /* Default procedure calling standard of current compilation unit. */
1581 extern enum arm_pcs arm_pcs_default;
1582
1583 #if !defined (USED_FOR_TARGET)
1584 /* A C type for declaring a variable that is used as the first argument of
1585 `FUNCTION_ARG' and other related values. */
1586 typedef struct
1587 {
1588 /* This is the number of registers of arguments scanned so far. */
1589 int nregs;
1590 /* This is the number of iWMMXt register arguments scanned so far. */
1591 int iwmmxt_nregs;
1592 int named_count;
1593 int nargs;
1594 /* Which procedure call variant to use for this call. */
1595 enum arm_pcs pcs_variant;
1596
1597 /* AAPCS related state tracking. */
1598 int aapcs_arg_processed; /* No need to lay out this argument again. */
1599 int aapcs_cprc_slot; /* Index of co-processor rules to handle
1600 this argument, or -1 if using core
1601 registers. */
1602 int aapcs_ncrn;
1603 int aapcs_next_ncrn;
1604 rtx aapcs_reg; /* Register assigned to this argument. */
1605 int aapcs_partial; /* How many bytes are passed in regs (if
1606 split between core regs and stack.
1607 Zero otherwise. */
1608 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS];
1609 int can_split; /* Argument can be split between core regs
1610 and the stack. */
1611 /* Private data for tracking VFP register allocation */
1612 unsigned aapcs_vfp_regs_free;
1613 unsigned aapcs_vfp_reg_alloc;
1614 int aapcs_vfp_rcount;
1615 MACHMODE aapcs_vfp_rmode;
1616 } CUMULATIVE_ARGS;
1617 #endif
1618
1619 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1620 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1621
1622 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1623 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1624
1625 /* For AAPCS, padding should never be below the argument. For other ABIs,
1626 * mimic the default. */
1627 #define PAD_VARARGS_DOWN \
1628 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1629
1630 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1631 for a call to a function whose data type is FNTYPE.
1632 For a library call, FNTYPE is 0.
1633 On the ARM, the offset starts at 0. */
1634 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1635 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1636
1637 /* 1 if N is a possible register number for function argument passing.
1638 On the ARM, r0-r3 are used to pass args. */
1639 #define FUNCTION_ARG_REGNO_P(REGNO) \
1640 (IN_RANGE ((REGNO), 0, 3) \
1641 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1642 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1643 || (TARGET_IWMMXT_ABI \
1644 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
1645
1646 \f
1647 /* If your target environment doesn't prefix user functions with an
1648 underscore, you may wish to re-define this to prevent any conflicts. */
1649 #ifndef ARM_MCOUNT_NAME
1650 #define ARM_MCOUNT_NAME "*mcount"
1651 #endif
1652
1653 /* Call the function profiler with a given profile label. The Acorn
1654 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1655 On the ARM the full profile code will look like:
1656 .data
1657 LP1
1658 .word 0
1659 .text
1660 mov ip, lr
1661 bl mcount
1662 .word LP1
1663
1664 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1665 will output the .text section.
1666
1667 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1668 ``prof'' doesn't seem to mind about this!
1669
1670 Note - this version of the code is designed to work in both ARM and
1671 Thumb modes. */
1672 #ifndef ARM_FUNCTION_PROFILER
1673 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1674 { \
1675 char temp[20]; \
1676 rtx sym; \
1677 \
1678 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1679 IP_REGNUM, LR_REGNUM); \
1680 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1681 fputc ('\n', STREAM); \
1682 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1683 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
1684 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1685 }
1686 #endif
1687
1688 #ifdef THUMB_FUNCTION_PROFILER
1689 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1690 if (TARGET_ARM) \
1691 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1692 else \
1693 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1694 #else
1695 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1696 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1697 #endif
1698
1699 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1700 the stack pointer does not matter. The value is tested only in
1701 functions that have frame pointers.
1702 No definition is equivalent to always zero.
1703
1704 On the ARM, the function epilogue recovers the stack pointer from the
1705 frame. */
1706 #define EXIT_IGNORE_STACK 1
1707
1708 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM)
1709
1710 /* Determine if the epilogue should be output as RTL.
1711 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1712 #define USE_RETURN_INSN(ISCOND) \
1713 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
1714
1715 /* Definitions for register eliminations.
1716
1717 This is an array of structures. Each structure initializes one pair
1718 of eliminable registers. The "from" register number is given first,
1719 followed by "to". Eliminations of the same "from" register are listed
1720 in order of preference.
1721
1722 We have two registers that can be eliminated on the ARM. First, the
1723 arg pointer register can often be eliminated in favor of the stack
1724 pointer register. Secondly, the pseudo frame pointer register can always
1725 be eliminated; it is replaced with either the stack or the real frame
1726 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1727 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1728
1729 #define ELIMINABLE_REGS \
1730 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1731 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1732 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1733 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1734 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1735 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1736 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1737
1738 /* Define the offset between two registers, one to be eliminated, and the
1739 other its replacement, at the start of a routine. */
1740 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1741 if (TARGET_ARM) \
1742 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1743 else \
1744 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1745
1746 /* Special case handling of the location of arguments passed on the stack. */
1747 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1748
1749 /* Initialize data used by insn expanders. This is called from insn_emit,
1750 once for every function before code is generated. */
1751 #define INIT_EXPANDERS arm_init_expanders ()
1752
1753 /* Length in units of the trampoline for entering a nested function. */
1754 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
1755
1756 /* Alignment required for a trampoline in bits. */
1757 #define TRAMPOLINE_ALIGNMENT 32
1758 \f
1759 /* Addressing modes, and classification of registers for them. */
1760 #define HAVE_POST_INCREMENT 1
1761 #define HAVE_PRE_INCREMENT TARGET_32BIT
1762 #define HAVE_POST_DECREMENT TARGET_32BIT
1763 #define HAVE_PRE_DECREMENT TARGET_32BIT
1764 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1765 #define HAVE_POST_MODIFY_DISP TARGET_32BIT
1766 #define HAVE_PRE_MODIFY_REG TARGET_32BIT
1767 #define HAVE_POST_MODIFY_REG TARGET_32BIT
1768
1769 enum arm_auto_incmodes
1770 {
1771 ARM_POST_INC,
1772 ARM_PRE_INC,
1773 ARM_POST_DEC,
1774 ARM_PRE_DEC
1775 };
1776
1777 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \
1778 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code))
1779 #define USE_LOAD_POST_INCREMENT(mode) \
1780 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC)
1781 #define USE_LOAD_PRE_INCREMENT(mode) \
1782 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC)
1783 #define USE_LOAD_POST_DECREMENT(mode) \
1784 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC)
1785 #define USE_LOAD_PRE_DECREMENT(mode) \
1786 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC)
1787
1788 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode)
1789 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode)
1790 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode)
1791 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
1792
1793 /* Macros to check register numbers against specific register classes. */
1794
1795 /* These assume that REGNO is a hard or pseudo reg number.
1796 They give nonzero only if REGNO is a hard reg of the suitable class
1797 or a pseudo reg currently allocated to a suitable hard reg.
1798 Since they use reg_renumber, they are safe only once reg_renumber
1799 has been allocated, which happens in reginfo.c during register
1800 allocation. */
1801 #define TEST_REGNO(R, TEST, VALUE) \
1802 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1803
1804 /* Don't allow the pc to be used. */
1805 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1806 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1807 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1808 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1809
1810 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1811 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1812 || (GET_MODE_SIZE (MODE) >= 4 \
1813 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1814
1815 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1816 (TARGET_THUMB1 \
1817 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1818 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1819
1820 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1821 For Thumb, we can not use SP + reg, so reject SP. */
1822 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1823 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
1824
1825 /* For ARM code, we don't care about the mode, but for Thumb, the index
1826 must be suitable for use in a QImode load. */
1827 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1828 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1829 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
1830
1831 /* Maximum number of registers that can appear in a valid memory address.
1832 Shifts in addresses can't be by a register. */
1833 #define MAX_REGS_PER_ADDRESS 2
1834
1835 /* Recognize any constant value that is a valid address. */
1836 /* XXX We can address any constant, eventually... */
1837 /* ??? Should the TARGET_ARM here also apply to thumb2? */
1838 #define CONSTANT_ADDRESS_P(X) \
1839 (GET_CODE (X) == SYMBOL_REF \
1840 && (CONSTANT_POOL_ADDRESS_P (X) \
1841 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1842
1843 /* True if SYMBOL + OFFSET constants must refer to something within
1844 SYMBOL's section. */
1845 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1846
1847 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1848 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1849 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
1850 #endif
1851
1852 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1853 #define SUBTARGET_NAME_ENCODING_LENGTHS
1854 #endif
1855
1856 /* This is a C fragment for the inside of a switch statement.
1857 Each case label should return the number of characters to
1858 be stripped from the start of a function's name, if that
1859 name starts with the indicated character. */
1860 #define ARM_NAME_ENCODING_LENGTHS \
1861 case '*': return 1; \
1862 SUBTARGET_NAME_ENCODING_LENGTHS
1863
1864 /* This is how to output a reference to a user-level label named NAME.
1865 `assemble_name' uses this. */
1866 #undef ASM_OUTPUT_LABELREF
1867 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1868 arm_asm_output_labelref (FILE, NAME)
1869
1870 /* Output IT instructions for conditionally executed Thumb-2 instructions. */
1871 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1872 if (TARGET_THUMB2) \
1873 thumb2_asm_output_opcode (STREAM);
1874
1875 /* The EABI specifies that constructors should go in .init_array.
1876 Other targets use .ctors for compatibility. */
1877 #ifndef ARM_EABI_CTORS_SECTION_OP
1878 #define ARM_EABI_CTORS_SECTION_OP \
1879 "\t.section\t.init_array,\"aw\",%init_array"
1880 #endif
1881 #ifndef ARM_EABI_DTORS_SECTION_OP
1882 #define ARM_EABI_DTORS_SECTION_OP \
1883 "\t.section\t.fini_array,\"aw\",%fini_array"
1884 #endif
1885 #define ARM_CTORS_SECTION_OP \
1886 "\t.section\t.ctors,\"aw\",%progbits"
1887 #define ARM_DTORS_SECTION_OP \
1888 "\t.section\t.dtors,\"aw\",%progbits"
1889
1890 /* Define CTORS_SECTION_ASM_OP. */
1891 #undef CTORS_SECTION_ASM_OP
1892 #undef DTORS_SECTION_ASM_OP
1893 #ifndef IN_LIBGCC2
1894 # define CTORS_SECTION_ASM_OP \
1895 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1896 # define DTORS_SECTION_ASM_OP \
1897 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1898 #else /* !defined (IN_LIBGCC2) */
1899 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1900 so we cannot use the definition above. */
1901 # ifdef __ARM_EABI__
1902 /* The .ctors section is not part of the EABI, so we do not define
1903 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1904 from trying to use it. We do define it when doing normal
1905 compilation, as .init_array can be used instead of .ctors. */
1906 /* There is no need to emit begin or end markers when using
1907 init_array; the dynamic linker will compute the size of the
1908 array itself based on special symbols created by the static
1909 linker. However, we do need to arrange to set up
1910 exception-handling here. */
1911 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1912 # define CTOR_LIST_END /* empty */
1913 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1914 # define DTOR_LIST_END /* empty */
1915 # else /* !defined (__ARM_EABI__) */
1916 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1917 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1918 # endif /* !defined (__ARM_EABI__) */
1919 #endif /* !defined (IN_LIBCC2) */
1920
1921 /* True if the operating system can merge entities with vague linkage
1922 (e.g., symbols in COMDAT group) during dynamic linking. */
1923 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1924 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1925 #endif
1926
1927 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1928
1929 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1930 and check its validity for a certain class.
1931 We have two alternate definitions for each of them.
1932 The usual definition accepts all pseudo regs; the other rejects
1933 them unless they have been allocated suitable hard regs.
1934 The symbol REG_OK_STRICT causes the latter definition to be used.
1935 Thumb-2 has the same restrictions as arm. */
1936 #ifndef REG_OK_STRICT
1937
1938 #define ARM_REG_OK_FOR_BASE_P(X) \
1939 (REGNO (X) <= LAST_ARM_REGNUM \
1940 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1941 || REGNO (X) == FRAME_POINTER_REGNUM \
1942 || REGNO (X) == ARG_POINTER_REGNUM)
1943
1944 #define ARM_REG_OK_FOR_INDEX_P(X) \
1945 ((REGNO (X) <= LAST_ARM_REGNUM \
1946 && REGNO (X) != STACK_POINTER_REGNUM) \
1947 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1948 || REGNO (X) == FRAME_POINTER_REGNUM \
1949 || REGNO (X) == ARG_POINTER_REGNUM)
1950
1951 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1952 (REGNO (X) <= LAST_LO_REGNUM \
1953 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1954 || (GET_MODE_SIZE (MODE) >= 4 \
1955 && (REGNO (X) == STACK_POINTER_REGNUM \
1956 || (X) == hard_frame_pointer_rtx \
1957 || (X) == arg_pointer_rtx)))
1958
1959 #define REG_STRICT_P 0
1960
1961 #else /* REG_OK_STRICT */
1962
1963 #define ARM_REG_OK_FOR_BASE_P(X) \
1964 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1965
1966 #define ARM_REG_OK_FOR_INDEX_P(X) \
1967 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
1968
1969 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1970 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1971
1972 #define REG_STRICT_P 1
1973
1974 #endif /* REG_OK_STRICT */
1975
1976 /* Now define some helpers in terms of the above. */
1977
1978 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1979 (TARGET_THUMB1 \
1980 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1981 : ARM_REG_OK_FOR_BASE_P (X))
1982
1983 /* For 16-bit Thumb, a valid index register is anything that can be used in
1984 a byte load instruction. */
1985 #define THUMB1_REG_OK_FOR_INDEX_P(X) \
1986 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
1987
1988 /* Nonzero if X is a hard reg that can be used as an index
1989 or if it is a pseudo reg. On the Thumb, the stack pointer
1990 is not suitable. */
1991 #define REG_OK_FOR_INDEX_P(X) \
1992 (TARGET_THUMB1 \
1993 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
1994 : ARM_REG_OK_FOR_INDEX_P (X))
1995
1996 /* Nonzero if X can be the base register in a reg+reg addressing mode.
1997 For Thumb, we can not use SP + reg, so reject SP. */
1998 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1999 REG_OK_FOR_INDEX_P (X)
2000 \f
2001 #define ARM_BASE_REGISTER_RTX_P(X) \
2002 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X))
2003
2004 #define ARM_INDEX_REGISTER_RTX_P(X) \
2005 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X))
2006 \f
2007 /* Specify the machine mode that this machine uses
2008 for the index in the tablejump instruction. */
2009 #define CASE_VECTOR_MODE Pmode
2010
2011 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
2012 || (TARGET_THUMB1 \
2013 && (optimize_size || flag_pic)))
2014
2015 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2016 (TARGET_THUMB1 \
2017 ? (min >= 0 && max < 512 \
2018 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
2019 : min >= -256 && max < 256 \
2020 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
2021 : min >= 0 && max < 8192 \
2022 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
2023 : min >= -4096 && max < 4096 \
2024 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
2025 : SImode) \
2026 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \
2027 : (max >= 0x200) ? HImode \
2028 : QImode))
2029
2030 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2031 unsigned is probably best, but may break some code. */
2032 #ifndef DEFAULT_SIGNED_CHAR
2033 #define DEFAULT_SIGNED_CHAR 0
2034 #endif
2035
2036 /* Max number of bytes we can move from memory to memory
2037 in one reasonably fast instruction. */
2038 #define MOVE_MAX 4
2039
2040 #undef MOVE_RATIO
2041 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
2042
2043 /* Define if operations between registers always perform the operation
2044 on the full register even if a narrower mode is specified. */
2045 #define WORD_REGISTER_OPERATIONS
2046
2047 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2048 will either zero-extend or sign-extend. The value of this macro should
2049 be the code that says which one of the two operations is implicitly
2050 done, UNKNOWN if none. */
2051 #define LOAD_EXTEND_OP(MODE) \
2052 (TARGET_THUMB ? ZERO_EXTEND : \
2053 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2054 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
2055
2056 /* Nonzero if access to memory by bytes is slow and undesirable. */
2057 #define SLOW_BYTE_ACCESS 0
2058
2059 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2060
2061 /* Immediate shift counts are truncated by the output routines (or was it
2062 the assembler?). Shift counts in a register are truncated by ARM. Note
2063 that the native compiler puts too large (> 32) immediate shift counts
2064 into a register and shifts by the register, letting the ARM decide what
2065 to do instead of doing that itself. */
2066 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2067 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2068 On the arm, Y in a register is used modulo 256 for the shift. Only for
2069 rotates is modulo 32 used. */
2070 /* #define SHIFT_COUNT_TRUNCATED 1 */
2071
2072 /* All integers have the same format so truncation is easy. */
2073 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2074
2075 /* Calling from registers is a massive pain. */
2076 #define NO_FUNCTION_CSE 1
2077
2078 /* The machine modes of pointers and functions */
2079 #define Pmode SImode
2080 #define FUNCTION_MODE Pmode
2081
2082 #define ARM_FRAME_RTX(X) \
2083 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2084 || (X) == arg_pointer_rtx)
2085
2086 /* Try to generate sequences that don't involve branches, we can then use
2087 conditional instructions. */
2088 #define BRANCH_COST(speed_p, predictable_p) \
2089 (current_tune->branch_cost (speed_p, predictable_p))
2090
2091 /* False if short circuit operation is preferred. */
2092 #define LOGICAL_OP_NON_SHORT_CIRCUIT \
2093 ((optimize_size) \
2094 ? (TARGET_THUMB ? false : true) \
2095 : (current_tune->logical_op_non_short_circuit[TARGET_ARM]))
2096
2097 \f
2098 /* Position Independent Code. */
2099 /* We decide which register to use based on the compilation options and
2100 the assembler in use; this is more general than the APCS restriction of
2101 using sb (r9) all the time. */
2102 extern unsigned arm_pic_register;
2103
2104 /* The register number of the register used to address a table of static
2105 data addresses in memory. */
2106 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2107
2108 /* We can't directly access anything that contains a symbol,
2109 nor can we indirect via the constant pool. One exception is
2110 UNSPEC_TLS, which is always PIC. */
2111 #define LEGITIMATE_PIC_OPERAND_P(X) \
2112 (!(symbol_mentioned_p (X) \
2113 || label_mentioned_p (X) \
2114 || (GET_CODE (X) == SYMBOL_REF \
2115 && CONSTANT_POOL_ADDRESS_P (X) \
2116 && (symbol_mentioned_p (get_pool_constant (X)) \
2117 || label_mentioned_p (get_pool_constant (X))))) \
2118 || tls_mentioned_p (X))
2119
2120 /* We need to know when we are making a constant pool; this determines
2121 whether data needs to be in the GOT or can be referenced via a GOT
2122 offset. */
2123 extern int making_const_table;
2124 \f
2125 /* Handle pragmas for compatibility with Intel's compilers. */
2126 /* Also abuse this to register additional C specific EABI attributes. */
2127 #define REGISTER_TARGET_PRAGMAS() do { \
2128 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2129 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2130 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
2131 arm_lang_object_attributes_init(); \
2132 } while (0)
2133
2134 /* Condition code information. */
2135 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2136 return the mode to be used for the comparison. */
2137
2138 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2139
2140 #define REVERSIBLE_CC_MODE(MODE) 1
2141
2142 #define REVERSE_CONDITION(CODE,MODE) \
2143 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2144 ? reverse_condition_maybe_unordered (code) \
2145 : reverse_condition (code))
2146
2147 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2148 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE))
2149 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2150 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE))
2151 \f
2152 #define CC_STATUS_INIT \
2153 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
2154
2155 #undef ASM_APP_ON
2156 #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \
2157 "\t.syntax divided\n")
2158
2159 #undef ASM_APP_OFF
2160 #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax divided\n" : \
2161 "\t.thumb\n\t.syntax unified\n")
2162
2163 /* Output a push or a pop instruction (only used when profiling).
2164 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2165 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2166 that r7 isn't used by the function profiler, so we can use it as a
2167 scratch reg. WARNING: This isn't safe in the general case! It may be
2168 sensitive to future changes in final.c:profile_function. */
2169 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2170 do \
2171 { \
2172 if (TARGET_ARM) \
2173 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2174 STACK_POINTER_REGNUM, REGNO); \
2175 else if (TARGET_THUMB1 \
2176 && (REGNO) == STATIC_CHAIN_REGNUM) \
2177 { \
2178 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2179 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\
2180 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2181 } \
2182 else \
2183 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2184 } while (0)
2185
2186
2187 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
2188 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2189 do \
2190 { \
2191 if (TARGET_ARM) \
2192 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2193 STACK_POINTER_REGNUM, REGNO); \
2194 else if (TARGET_THUMB1 \
2195 && (REGNO) == STATIC_CHAIN_REGNUM) \
2196 { \
2197 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2198 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\
2199 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2200 } \
2201 else \
2202 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2203 } while (0)
2204
2205 #define ADDR_VEC_ALIGN(JUMPTABLE) \
2206 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0)
2207
2208 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the
2209 default alignment from elfos.h. */
2210 #undef ASM_OUTPUT_BEFORE_CASE_LABEL
2211 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */
2212
2213 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \
2214 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \
2215 ? 1 : 0)
2216
2217 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2218 do \
2219 { \
2220 if (TARGET_THUMB) \
2221 { \
2222 if (is_called_in_ARM_mode (DECL) \
2223 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
2224 && cfun->is_thunk)) \
2225 fprintf (STREAM, "\t.code 32\n") ; \
2226 else if (TARGET_THUMB1) \
2227 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
2228 else \
2229 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
2230 } \
2231 if (TARGET_POKE_FUNCTION_NAME) \
2232 arm_poke_function_name (STREAM, (const char *) NAME); \
2233 } \
2234 while (0)
2235
2236 /* For aliases of functions we use .thumb_set instead. */
2237 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2238 do \
2239 { \
2240 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2241 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2242 \
2243 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2244 { \
2245 fprintf (FILE, "\t.thumb_set "); \
2246 assemble_name (FILE, LABEL1); \
2247 fprintf (FILE, ","); \
2248 assemble_name (FILE, LABEL2); \
2249 fprintf (FILE, "\n"); \
2250 } \
2251 else \
2252 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2253 } \
2254 while (0)
2255
2256 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2257 /* To support -falign-* switches we need to use .p2align so
2258 that alignment directives in code sections will be padded
2259 with no-op instructions, rather than zeroes. */
2260 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
2261 if ((LOG) != 0) \
2262 { \
2263 if ((MAX_SKIP) == 0) \
2264 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
2265 else \
2266 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2267 (int) (LOG), (int) (MAX_SKIP)); \
2268 }
2269 #endif
2270 \f
2271 /* Add two bytes to the length of conditionally executed Thumb-2
2272 instructions for the IT instruction. */
2273 #define ADJUST_INSN_LENGTH(insn, length) \
2274 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2275 length += 2;
2276
2277 /* Only perform branch elimination (by making instructions conditional) if
2278 we're optimizing. For Thumb-2 check if any IT instructions need
2279 outputting. */
2280 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2281 if (TARGET_ARM && optimize) \
2282 arm_final_prescan_insn (INSN); \
2283 else if (TARGET_THUMB2) \
2284 thumb2_final_prescan_insn (INSN); \
2285 else if (TARGET_THUMB1) \
2286 thumb1_final_prescan_insn (INSN)
2287
2288 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2289 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2290 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2291 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2292 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2293 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2294 : 0))))
2295
2296 /* A C expression whose value is RTL representing the value of the return
2297 address for the frame COUNT steps up from the current frame. */
2298
2299 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2300 arm_return_addr (COUNT, FRAME)
2301
2302 /* Mask of the bits in the PC that contain the real return address
2303 when running in 26-bit mode. */
2304 #define RETURN_ADDR_MASK26 (0x03fffffc)
2305
2306 /* Pick up the return address upon entry to a procedure. Used for
2307 dwarf2 unwind information. This also enables the table driven
2308 mechanism. */
2309 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2310 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2311
2312 /* Used to mask out junk bits from the return address, such as
2313 processor state, interrupt status, condition codes and the like. */
2314 #define MASK_RETURN_ADDR \
2315 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2316 in 26 bit mode, the condition codes must be masked out of the \
2317 return address. This does not apply to ARM6 and later processors \
2318 when running in 32 bit mode. */ \
2319 ((arm_arch4 || TARGET_THUMB) \
2320 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
2321 : arm_gen_return_addr_mask ())
2322
2323 \f
2324 /* Do not emit .note.GNU-stack by default. */
2325 #ifndef NEED_INDICATE_EXEC_STACK
2326 #define NEED_INDICATE_EXEC_STACK 0
2327 #endif
2328
2329 #define TARGET_ARM_ARCH \
2330 (arm_base_arch) \
2331
2332 #define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2)
2333 #define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2)
2334
2335 /* The highest Thumb instruction set version supported by the chip. */
2336 #define TARGET_ARM_ARCH_ISA_THUMB \
2337 (arm_arch_thumb2 ? 2 \
2338 : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0))
2339
2340 /* Expands to an upper-case char of the target's architectural
2341 profile. */
2342 #define TARGET_ARM_ARCH_PROFILE \
2343 (!arm_arch_notm \
2344 ? 'M' \
2345 : (arm_arch7 \
2346 ? (strlen (arm_arch_name) >=3 \
2347 ? (arm_arch_name[strlen (arm_arch_name) - 3]) \
2348 : 0) \
2349 : 0))
2350
2351 /* Bit-field indicating what size LDREX/STREX loads/stores are available.
2352 Bit 0 for bytes, up to bit 3 for double-words. */
2353 #define TARGET_ARM_FEATURE_LDREX \
2354 ((TARGET_HAVE_LDREX ? 4 : 0) \
2355 | (TARGET_HAVE_LDREXBH ? 3 : 0) \
2356 | (TARGET_HAVE_LDREXD ? 8 : 0))
2357
2358 /* Set as a bit mask indicating the available widths of hardware floating
2359 point types. Where bit 1 indicates 16-bit support, bit 2 indicates
2360 32-bit support, bit 3 indicates 64-bit support. */
2361 #define TARGET_ARM_FP \
2362 (TARGET_VFP_SINGLE ? 4 \
2363 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0))
2364
2365
2366 /* Set as a bit mask indicating the available widths of floating point
2367 types for hardware NEON floating point. This is the same as
2368 TARGET_ARM_FP without the 64-bit bit set. */
2369 #ifdef TARGET_NEON
2370 #define TARGET_NEON_FP \
2371 (TARGET_ARM_FP & (0xff ^ 0x08))
2372 #endif
2373
2374 /* The maximum number of parallel loads or stores we support in an ldm/stm
2375 instruction. */
2376 #define MAX_LDM_STM_OPS 4
2377
2378 #define BIG_LITTLE_SPEC \
2379 " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}"
2380
2381 extern const char *arm_rewrite_mcpu (int argc, const char **argv);
2382 #define BIG_LITTLE_CPU_SPEC_FUNCTIONS \
2383 { "rewrite_mcpu", arm_rewrite_mcpu },
2384
2385 #define ASM_CPU_SPEC \
2386 " %{mcpu=generic-*:-march=%*;" \
2387 " :%{march=*:-march=%*}}" \
2388 BIG_LITTLE_SPEC
2389
2390 /* -mcpu=native handling only makes sense with compiler running on
2391 an ARM chip. */
2392 #if defined(__arm__)
2393 extern const char *host_detect_local_cpu (int argc, const char **argv);
2394 # define EXTRA_SPEC_FUNCTIONS \
2395 { "local_cpu_detect", host_detect_local_cpu }, \
2396 BIG_LITTLE_CPU_SPEC_FUNCTIONS
2397
2398 # define MCPU_MTUNE_NATIVE_SPECS \
2399 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \
2400 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \
2401 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
2402 #else
2403 # define MCPU_MTUNE_NATIVE_SPECS ""
2404 # define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS
2405 #endif
2406
2407 #define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS
2408 #define TARGET_SUPPORTS_WIDE_INT 1
2409 #endif /* ! GCC_ARM_H */
GNU Compiler Collection
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