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1 /* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
2 Copyright (C) 1991, 1993, 1994 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
6
7 This file is part of GNU CC.
8
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22
23 /* Sometimes the directive `riscos' is checked. This does not imply that this
24 tm file can be used unchanged to build a GCC for RISC OS.
25 (Since in fact, it can't.) */
26
27 extern void output_prologue ();
28 extern void output_epilogue ();
29 extern char *arm_output_asm_insn ();
30 extern char *arm_output_llc ();
31 extern char *arithmetic_instr ();
32 extern char *output_add_immediate ();
33 extern char *output_call ();
34 extern char *output_call_mem ();
35 extern char *output_move_double ();
36 extern char *output_mov_double_fpu_from_arm ();
37 extern char *output_mov_double_arm_from_fpu ();
38 extern char *output_mov_long_double_fpu_from_arm ();
39 extern char *output_mov_long_double_arm_from_fpu ();
40 extern char *output_mov_long_double_arm_from_arm ();
41 extern char *output_mov_immediate ();
42 extern char *output_multi_immediate ();
43 extern char *output_shifted_move ();
44 extern char *output_shift_compare ();
45 extern char *output_arithmetic_with_immediate_multiply ();
46 extern char *output_arithmetic_with_shift ();
47 extern char *output_return_instruction ();
48 extern char *output_load_symbol ();
49 extern char *fp_immediate_constant ();
50 extern char *shift_instr ();
51 extern struct rtx_def *gen_compare_reg ();
52 extern struct rtx_def *arm_gen_store_multiple ();
53 extern struct rtx_def *arm_gen_load_multiple ();
54
55 extern char *arm_condition_codes[];
56
57 /* This is needed by the tail-calling peepholes */
58 extern int frame_pointer_needed;
59
60 \f
61 #ifndef CPP_PREDEFINES
62 #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
63 #endif
64
65 #ifndef CPP_SPEC
66 #define CPP_SPEC "%{m6:-D__arm6__}"
67 #endif
68 \f
69 /* Run-time Target Specification. */
70 #ifndef TARGET_VERSION
71 #define TARGET_VERSION \
72 fputs (" (ARM/generic)", stderr);
73 #endif
74
75 /* Run-time compilation parameters selecting different hardware subsets.
76 On the ARM, misuse it in a different way. */
77 extern int target_flags;
78
79 /* Nonzero if the function prologue (and epilogue) should obey
80 the ARM Procedure Call Standard. */
81 #define TARGET_APCS (target_flags & 1)
82
83 /* Nonzero if the function prologue should output the function name to enable
84 the post mortem debugger to print a backtrace (very useful on RISCOS,
85 unused on RISCiX). Specifying this flag also enables -mapcs.
86 XXX Must still be implemented in the prologue. */
87 #define TARGET_POKE_FUNCTION_NAME (target_flags & 2)
88
89 /* Nonzero if floating point instructions are emulated by the FPE, in which
90 case instruction scheduling becomes very uninteresting. */
91 #define TARGET_FPE (target_flags & 4)
92
93 /* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration
94 of condition flags when returning from a branch & link (ie. a function) */
95 #define TARGET_6 (target_flags & 8)
96
97 /* ARM_EXTRA_TARGET_SWITCHES is used in riscix.h to define some options which
98 are passed to the preprocessor and the assembler post-processor. They
99 aren't needed in the main pass of the compiler, but if we don't define
100 them in target switches cc1 complains about them. For the sake of
101 argument lets allocate bit 31 of target flags for such options. */
102
103 #ifndef ARM_EXTRA_TARGET_SWITCHES
104 #define ARM_EXTRA_TARGET_SWITCHES
105 #endif
106
107 #define TARGET_SWITCHES \
108 { \
109 {"apcs", 1}, \
110 {"poke-function-name", 2}, \
111 {"fpe", 4}, \
112 {"6", 8}, \
113 {"2", -8}, \
114 {"3", -8}, \
115 ARM_EXTRA_TARGET_SWITCHES \
116 {"", TARGET_DEFAULT } \
117 }
118
119 /* Which processor we are running on. Currently this is only used to
120 get the condition code clobbering attribute right when we are running on
121 an arm 6 */
122
123 enum processor_type
124 {
125 PROCESSOR_ARM2,
126 PROCESSOR_ARM3,
127 PROCESSOR_ARM6
128 };
129
130 /* Recast the cpu class to be the cpu attribute. */
131
132 /* Recast the cpu class to be the cpu attribute. */
133 #define arm_cpu_attr ((enum attr_cpu)arm_cpu)
134
135 extern enum processor_type arm_cpu;
136
137 #define TARGET_DEFAULT 0
138
139 #define TARGET_MEM_FUNCTIONS 1
140
141 /* OVERRIDE_OPTIONS takes care of the following:
142 - if -mpoke-function-name, then -mapcs.
143 - if doing debugging, then -mapcs; if RISCOS, then -mpoke-function-name.
144 - if floating point is done by emulation, forget about instruction
145 scheduling. Note that this only saves compilation time; it doesn't
146 matter for the final code. */
147 #ifndef TARGET_WHEN_DEBUGGING
148 #define TARGET_WHEN_DEBUGGING 1
149 #endif
150
151 #define OVERRIDE_OPTIONS \
152 { \
153 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer) \
154 warning ("-g without a frame pointer may not give sensible debugging");\
155 if (TARGET_POKE_FUNCTION_NAME) \
156 target_flags |= 1; \
157 if (TARGET_FPE) \
158 flag_schedule_insns = flag_schedule_insns_after_reload = 0; \
159 arm_cpu = TARGET_6 ? PROCESSOR_ARM6: PROCESSOR_ARM2; \
160 }
161 \f
162 /* Target machine storage Layout. */
163
164
165 /* Define this macro if it is advisable to hold scalars in registers
166 in a wider mode than that declared by the program. In such cases,
167 the value is constrained to be within the bounds of the declared
168 type, but kept valid in the wider mode. The signedness of the
169 extension may differ from that of the type. */
170
171 /* It is far faster to zero extend chars than to sign extend them */
172
173 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
174 if (GET_MODE_CLASS (MODE) == MODE_INT \
175 && GET_MODE_SIZE (MODE) < 4) \
176 { \
177 if (MODE == QImode) \
178 UNSIGNEDP = 1; \
179 (MODE) = SImode; \
180 }
181
182 /* Define for XFmode extended real floating point support.
183 This will automatically cause REAL_ARITHMETIC to be defined. */
184 /* For the ARM:
185 I think I have added all the code to make this work. Unfortunately,
186 early releases of the floating point emulation code on RISCiX used a
187 different format for extended precision numbers. On my RISCiX box there
188 is a bug somewhere which causes the machine to lock up when running enquire
189 with long doubles. There is the additional aspect that Norcroft C
190 treats long doubles as doubles and we ought to remain compatible.
191 Perhaps someone with an FPA coprocessor and not running RISCiX would like
192 to try this someday. */
193 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
194
195 /* Disable XFmode patterns in md file */
196 #define ENABLE_XF_PATTERNS 0
197
198 /* Define if you don't want extended real, but do want to use the
199 software floating point emulator for REAL_ARITHMETIC and
200 decimal <-> binary conversion. */
201 /* See comment above */
202 #define REAL_ARITHMETIC
203
204 /* Define this if most significant bit is lowest numbered
205 in instructions that operate on numbered bit-fields. */
206 #define BITS_BIG_ENDIAN 0
207
208 /* Define this if most significant byte of a word is the lowest numbered. */
209 #define BYTES_BIG_ENDIAN 0
210
211 /* Define this if most significant word of a multiword number is the lowest
212 numbered. */
213 #define WORDS_BIG_ENDIAN 0
214
215 /* Define this if most significant word of doubles is the lowest numbered */
216 #define FLOAT_WORDS_BIG_ENDIAN 1
217
218 /* Number of bits in an addressable storage unit */
219 #define BITS_PER_UNIT 8
220
221 #define BITS_PER_WORD 32
222
223 #define UNITS_PER_WORD 4
224
225 #define POINTER_SIZE 32
226
227 #define PARM_BOUNDARY 32
228
229 #define STACK_BOUNDARY 32
230
231 #define FUNCTION_BOUNDARY 32
232
233 #define EMPTY_FIELD_BOUNDARY 32
234
235 #define BIGGEST_ALIGNMENT 32
236
237 /* Make strings word-aligned so strcpy from constants will be faster. */
238 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
239 (TREE_CODE (EXP) == STRING_CST \
240 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
241
242 /* Every structures size must be a multiple of 32 bits. */
243 #define STRUCTURE_SIZE_BOUNDARY 32
244
245 /* Non-zero if move instructions will actually fail to work
246 when given unaligned data. */
247 #define STRICT_ALIGNMENT 1
248
249 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
250
251 /* Define number of bits in most basic integer type.
252 (If undefined, default is BITS_PER_WORD). */
253 /* #define INT_TYPE_SIZE */
254 \f
255 /* Standard register usage. */
256
257 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
258 (S - saved over call).
259
260 r0 * argument word/integer result
261 r1-r3 argument word
262
263 r4-r8 S register variable
264 r9 S (rfp) register variable (real frame pointer)
265
266 r10 F S (sl) stack limit (not currently used)
267 r11 F S (fp) argument pointer
268 r12 (ip) temp workspace
269 r13 F S (sp) lower end of current stack frame
270 r14 (lr) link address/workspace
271 r15 F (pc) program counter
272
273 f0 floating point result
274 f1-f3 floating point scratch
275
276 f4-f7 S floating point variable
277
278 cc This is NOT a real register, but is used internally
279 to represent things that use or set the condition
280 codes.
281 sfp This isn't either. It is used during rtl generation
282 since the offset between the frame pointer and the
283 auto's isn't known until after register allocation.
284 afp Nor this, we only need this because of non-local
285 goto. Without it fp appears to be used and the
286 elimination code won't get rid of sfp. It tracks
287 fp exactly at all times.
288
289 *: See CONDITIONAL_REGISTER_USAGE */
290
291 /* The stack backtrace structure is as follows:
292 fp points to here: | save code pointer | [fp]
293 | return link value | [fp, #-4]
294 | return sp value | [fp, #-8]
295 | return fp value | [fp, #-12]
296 [| saved r10 value |]
297 [| saved r9 value |]
298 [| saved r8 value |]
299 [| saved r7 value |]
300 [| saved r6 value |]
301 [| saved r5 value |]
302 [| saved r4 value |]
303 [| saved r3 value |]
304 [| saved r2 value |]
305 [| saved r1 value |]
306 [| saved r0 value |]
307 [| saved f7 value |] three words
308 [| saved f6 value |] three words
309 [| saved f5 value |] three words
310 [| saved f4 value |] three words
311 r0-r3 are not normally saved in a C function. */
312
313 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
314 #define FIRST_PSEUDO_REGISTER 27
315
316 /* 1 for registers that have pervasive standard uses
317 and are not available for the register allocator. */
318 #define FIXED_REGISTERS \
319 { \
320 0,0,0,0,0,0,0,0, \
321 0,0,1,1,0,1,0,1, \
322 0,0,0,0,0,0,0,0, \
323 1,1,1 \
324 }
325
326 /* 1 for registers not available across function calls.
327 These must include the FIXED_REGISTERS and also any
328 registers that can be used without being saved.
329 The latter must include the registers where values are returned
330 and the register where structure-value addresses are passed.
331 Aside from that, you can include as many other registers as you like.
332 The CC is not preserved over function calls on the ARM 6, so it is
333 easier to assume this for all. SFP is preserved, since FP is. */
334 #define CALL_USED_REGISTERS \
335 { \
336 1,1,1,1,0,0,0,0, \
337 0,0,1,1,1,1,1,1, \
338 1,1,1,1,0,0,0,0, \
339 1,1,1 \
340 }
341
342 /* If doing stupid life analysis, avoid a bug causing a return value r0 to be
343 trampled. This effectively reduces the number of available registers by 1.
344 XXX It is a hack, I know.
345 XXX Is this still needed? */
346 #define CONDITIONAL_REGISTER_USAGE \
347 { \
348 if (obey_regdecls) \
349 fixed_regs[0] = 1; \
350 }
351
352 /* Return number of consecutive hard regs needed starting at reg REGNO
353 to hold something of mode MODE.
354 This is ordinarily the length in words of a value of mode MODE
355 but can be less for certain modes in special long registers.
356
357 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
358 mode. */
359 #define HARD_REGNO_NREGS(REGNO, MODE) \
360 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
361 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
362 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
363
364 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
365 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
366 regs holding FP. */
367 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
368 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
369 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
370 || REGNO == ARG_POINTER_REGNUM \
371 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
372
373 /* Value is 1 if it is a good idea to tie two pseudo registers
374 when one has mode MODE1 and one has mode MODE2.
375 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
376 for any hard reg, then this must be 0 for correct output. */
377 #define MODES_TIEABLE_P(MODE1, MODE2) \
378 (((MODE1) == SFmode || (MODE1) == DFmode) \
379 == ((MODE2) == SFmode || (MODE2) == DFmode))
380
381 /* Specify the registers used for certain standard purposes.
382 The values of these macros are register numbers. */
383
384 /* Define this if the program counter is overloaded on a register. */
385 #define PC_REGNUM 15
386
387 /* Register to use for pushing function arguments. */
388 #define STACK_POINTER_REGNUM 13
389
390 /* Base register for access to local variables of the function. */
391 #define FRAME_POINTER_REGNUM 25
392
393 /* Define this to be where the real frame pointer is if it is not possible to
394 work out the offset between the frame pointer and the automatic variables
395 until after register allocation has taken place. FRAME_POINTER_REGNUM
396 should point to a special register that we will make sure is eliminated. */
397 #define HARD_FRAME_POINTER_REGNUM 11
398
399 /* Value should be nonzero if functions must have frame pointers.
400 Zero means the frame pointer need not be set up (and parms may be accessed
401 via the stack pointer) in functions that seem suitable.
402 If we have to have a frame pointer we might as well make use of it.
403 APCS says that the frame pointer does not need to be pushed in leaf
404 functions. */
405 #define FRAME_POINTER_REQUIRED (TARGET_APCS && !leaf_function_p ())
406
407 /* Base register for access to arguments of the function. */
408 #define ARG_POINTER_REGNUM 26
409
410 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
411 as an invisible last argument (possible since varargs don't exist in
412 Pascal), so the following is not true. */
413 #define STATIC_CHAIN_REGNUM 8
414
415 /* Register in which address to store a structure value
416 is passed to a function. */
417 #define STRUCT_VALUE_REGNUM 0
418
419 /* Internal, so that we don't need to refer to a raw number */
420 #define CC_REGNUM 24
421
422 /* The order in which register should be allocated. It is good to use ip
423 since no saving is required (though calls clobber it) and it never contains
424 function parameters. It is quite good to use lr since other calls may
425 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
426 least likely to contain a function parameter; in addition results are
427 returned in r0.
428 */
429 #define REG_ALLOC_ORDER \
430 { \
431 3, 2, 1, 0, 12, 14, 4, 5, \
432 6, 7, 8, 10, 9, 11, 13, 15, \
433 16, 17, 18, 19, 20, 21, 22, 23, \
434 24, 25 \
435 }
436 \f
437 /* Register and constant classes. */
438
439 /* Register classes: all ARM regs or all FPU regs---simple! */
440 enum reg_class
441 {
442 NO_REGS,
443 FPU_REGS,
444 GENERAL_REGS,
445 ALL_REGS,
446 LIM_REG_CLASSES
447 };
448
449 #define N_REG_CLASSES (int) LIM_REG_CLASSES
450
451 /* Give names of register classes as strings for dump file. */
452 #define REG_CLASS_NAMES \
453 { \
454 "NO_REGS", \
455 "FPU_REGS", \
456 "GENERAL_REGS", \
457 "ALL_REGS", \
458 }
459
460 /* Define which registers fit in which classes.
461 This is an initializer for a vector of HARD_REG_SET
462 of length N_REG_CLASSES. */
463 #define REG_CLASS_CONTENTS \
464 { \
465 0x0000000, /* NO_REGS */ \
466 0x0FF0000, /* FPU_REGS */ \
467 0x200FFFF, /* GENERAL_REGS */ \
468 0x2FFFFFF /* ALL_REGS */ \
469 }
470
471 /* The same information, inverted:
472 Return the class number of the smallest class containing
473 reg number REGNO. This could be a conditional expression
474 or could index an array. */
475 #define REGNO_REG_CLASS(REGNO) \
476 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
477 || REGNO == ARG_POINTER_REGNUM) \
478 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
479 ? NO_REGS : FPU_REGS)
480
481 /* The class value for index registers, and the one for base regs. */
482 #define INDEX_REG_CLASS GENERAL_REGS
483 #define BASE_REG_CLASS GENERAL_REGS
484
485 /* Get reg_class from a letter such as appears in the machine description.
486 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
487 #define REG_CLASS_FROM_LETTER(C) \
488 ((C)=='f' ? FPU_REGS : NO_REGS)
489
490 /* The letters I, J, K, L and M in a register constraint string
491 can be used to stand for particular ranges of immediate operands.
492 This macro defines what the ranges are.
493 C is the letter, and VALUE is a constant value.
494 Return 1 if VALUE is in the range specified by C.
495 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
496 J: valid indexing constants.
497 K: as I but also (not (value)) ok.
498 L: as I but also (neg (value)) ok.*/
499 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
500 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
501 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
502 (C) == 'K' ? (const_ok_for_arm (VALUE) || const_ok_for_arm (~(VALUE))) : \
503 (C) == 'L' ? (const_ok_for_arm (VALUE) || const_ok_for_arm (-(VALUE))) : 0)
504
505 /* For the ARM, `Q' means that this is a memory operand that is just
506 an offset from a register.
507 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
508 address. This means that the symbol is in the text segment and can be
509 accessed without using a load. */
510
511 #define EXTRA_CONSTRAINT(OP, C) \
512 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
513 : (C) == 'S' ? CONSTANT_ADDRESS_P (OP) : 0)
514
515 /* Constant letter 'G' for the FPU immediate constants.
516 'H' means the same constant negated. */
517 #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
518 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
519 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
520
521 /* Given an rtx X being reloaded into a reg required to be
522 in class CLASS, return the class of reg to actually use.
523 In general this is just CLASS; but on some machines
524 in some cases it is preferable to use a more restrictive class. */
525 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
526
527 /* Return the register class of a scratch register needed to copy IN into
528 or out of a register in CLASS in MODE. If it can be done directly,
529 NO_REGS is returned. */
530 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
531 (((MODE) == DFmode && (CLASS) == GENERAL_REGS \
532 && true_regnum (X) == -1) ? GENERAL_REGS \
533 : ((MODE) == HImode && true_regnum (X) == -1) ? GENERAL_REGS : NO_REGS)
534
535 /* Return the maximum number of consecutive registers
536 needed to represent mode MODE in a register of class CLASS.
537 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
538 #define CLASS_MAX_NREGS(CLASS, MODE) \
539 ((CLASS) == FPU_REGS ? 1 \
540 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
541
542 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
543 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
544 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
545 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
546 ? 20 : 2)
547 \f
548 /* Stack layout; function entry, exit and calling. */
549
550 /* Define this if pushing a word on the stack
551 makes the stack pointer a smaller address. */
552 #define STACK_GROWS_DOWNWARD 1
553
554 /* Define this if the nominal address of the stack frame
555 is at the high-address end of the local variables;
556 that is, each additional local variable allocated
557 goes at a more negative offset in the frame. */
558 #define FRAME_GROWS_DOWNWARD 1
559
560 /* Offset within stack frame to start allocating local variables at.
561 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
562 first local allocated. Otherwise, it is the offset to the BEGINNING
563 of the first local allocated. */
564 #define STARTING_FRAME_OFFSET 0
565
566 /* If we generate an insn to push BYTES bytes,
567 this says how many the stack pointer really advances by. */
568 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
569
570 /* Offset of first parameter from the argument pointer register value. */
571 #define FIRST_PARM_OFFSET(FNDECL) 4
572
573 /* Value is the number of byte of arguments automatically
574 popped when returning from a subroutine call.
575 FUNTYPE is the data type of the function (as a tree),
576 or for a library call it is an identifier node for the subroutine name.
577 SIZE is the number of bytes of arguments passed on the stack.
578
579 On the ARM, the caller does not pop any of its arguments that were passed
580 on the stack. */
581 #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
582
583 /* Define how to find the value returned by a function.
584 VALTYPE is the data type of the value (as a tree).
585 If the precise function being called is known, FUNC is its FUNCTION_DECL;
586 otherwise, FUNC is 0. */
587 #define FUNCTION_VALUE(VALTYPE, FUNC) \
588 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
589 ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
590 : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
591
592 /* Define how to find the value returned by a library function
593 assuming the value has mode MODE. */
594 #define LIBCALL_VALUE(MODE) \
595 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
596 ? gen_rtx (REG, MODE, 16) \
597 : gen_rtx (REG, MODE, 0))
598
599 /* 1 if N is a possible register number for a function value.
600 On the ARM, only r0 and f0 can return results. */
601 #define FUNCTION_VALUE_REGNO_P(REGNO) \
602 ((REGNO) == 0 || (REGNO) == 16)
603
604 /* Define where to put the arguments to a function.
605 Value is zero to push the argument on the stack,
606 or a hard register in which to store the argument.
607
608 MODE is the argument's machine mode.
609 TYPE is the data type of the argument (as a tree).
610 This is null for libcalls where that information may
611 not be available.
612 CUM is a variable of type CUMULATIVE_ARGS which gives info about
613 the preceding args and about the function being called.
614 NAMED is nonzero if this argument is a named parameter
615 (otherwise it is an extra parameter matching an ellipsis).
616
617 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
618 other arguments are passed on the stack. If (NAMED == 0) (which happens
619 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
620 passed in the stack (function_prologue will indeed make it pass in the
621 stack if necessary). */
622 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
623 ((NAMED) \
624 ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \
625 : 0)
626
627 /* For an arg passed partly in registers and partly in memory,
628 this is the number of registers used.
629 For args passed entirely in registers or entirely in memory, zero. */
630 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
631 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
632 ? GET_MODE_SIZE (MODE) \
633 : int_size_in_bytes (TYPE)) \
634 ? 4 - (CUM) / 4 : 0)
635
636 /* A C type for declaring a variable that is used as the first argument of
637 `FUNCTION_ARG' and other related values. For some target machines, the
638 type `int' suffices and can hold the number of bytes of argument so far.
639
640 On the ARM, this is the number of bytes of arguments scanned so far. */
641 #define CUMULATIVE_ARGS int
642
643 /* Initialize a variable CUM of type CUMULATIVE_ARGS
644 for a call to a function whose data type is FNTYPE.
645 For a library call, FNTYPE is 0.
646 On the ARM, the offset starts at 0. */
647 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
648 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
649
650 /* Update the data in CUM to advance over an argument
651 of mode MODE and data type TYPE.
652 (TYPE is null for libcalls where that information may not be available.) */
653 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
654 (CUM) += ((MODE) != BLKmode \
655 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
656 : (int_size_in_bytes (TYPE) + 3) & ~3) \
657
658 /* 1 if N is a possible register number for function argument passing.
659 On the ARM, r0-r3 are used to pass args. */
660 #define FUNCTION_ARG_REGNO_P(REGNO) \
661 ((REGNO) >= 0 && (REGNO) <= 3)
662
663 /* Perform any actions needed for a function that is receiving a variable
664 number of arguments. CUM is as above. MODE and TYPE are the mode and type
665 of the current parameter. PRETEND_SIZE is a variable that should be set to
666 the amount of stack that must be pushed by the prolog to pretend that our
667 caller pushed it.
668
669 Normally, this macro will push all remaining incoming registers on the
670 stack and set PRETEND_SIZE to the length of the registers pushed.
671
672 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
673 named arg and all anonymous args onto the stack.
674 XXX I know the prologue shouldn't be pushing registers, but it is faster
675 that way. */
676 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
677 { \
678 extern int current_function_anonymous_args; \
679 current_function_anonymous_args = 1; \
680 if ((CUM) < 16) \
681 (PRETEND_SIZE) = 16 - (CUM); \
682 }
683
684 /* Generate assembly output for the start of a function. */
685 #define FUNCTION_PROLOGUE(STREAM, SIZE) \
686 output_prologue ((STREAM), (SIZE))
687
688 /* Call the function profiler with a given profile label. The Acorn compiler
689 puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
690 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
691 to mind about this! */
692 #define FUNCTION_PROFILER(STREAM,LABELNO) \
693 { \
694 fprintf(STREAM, "\tmov\tip, lr\n"); \
695 fprintf(STREAM, "\tbl\tmcount\n"); \
696 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
697 arm_increase_location (12); \
698 }
699
700 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
701 the stack pointer does not matter. The value is tested only in
702 functions that have frame pointers.
703 No definition is equivalent to always zero.
704
705 On the ARM, the function epilogue recovers the stack pointer from the
706 frame. */
707 #define EXIT_IGNORE_STACK 1
708
709 /* Generate the assembly code for function exit. */
710 #define FUNCTION_EPILOGUE(STREAM, SIZE) \
711 output_epilogue ((STREAM), (SIZE))
712
713 /* Determine if the epilogue should be output as RTL.
714 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
715 #define USE_RETURN_INSN use_return_insn ()
716
717 /* Definitions for register eliminations.
718
719 This is an array of structures. Each structure initializes one pair
720 of eliminable registers. The "from" register number is given first,
721 followed by "to". Eliminations of the same "from" register are listed
722 in order of preference.
723
724 We have two registers that can be eliminated on the ARM. First, the
725 arg pointer register can often be eliminated in favor of the stack
726 pointer register. Secondly, the pseudo frame pointer register can always
727 be eliminated; it is replaced with either the stack or the real frame
728 pointer. */
729
730 #define ELIMINABLE_REGS \
731 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
732 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
733 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
734 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
735
736 /* Given FROM and TO register numbers, say whether this elimination is allowed.
737 Frame pointer elimination is automatically handled.
738
739 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
740 HARD_FRAME_POINTER_REGNUM are infact the same thing. If we need a frame
741 pointer, we must eliminate FRAME_POINTER_REGNUM into
742 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
743 #define CAN_ELIMINATE(FROM, TO) \
744 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
745
746 /* Define the offset between two registers, one to be eliminated, and the other
747 its replacement, at the start of a routine. */
748 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
749 { \
750 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
751 (OFFSET) = 0; \
752 else if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)\
753 (OFFSET) = (get_frame_size () + 3 & ~3); \
754 else \
755 { \
756 int regno; \
757 int offset = 12; \
758 \
759 for (regno = 4; regno <= 10; regno++) \
760 if (regs_ever_live[regno]) \
761 offset += 4; \
762 for (regno = 20; regno <=23; regno++) \
763 if (regs_ever_live[regno]) \
764 offset += 12; \
765 if ((FROM) == FRAME_POINTER_REGNUM) \
766 (OFFSET) = -offset; \
767 else \
768 { \
769 if (! regs_ever_live[HARD_FRAME_POINTER_REGNUM]) \
770 offset -= 16; \
771 if (regs_ever_live[14]) \
772 offset += 4; \
773 (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \
774 } \
775 } \
776 }
777
778 #if 0
779 /* Store in the variable DEPTH the initial difference between the frame
780 pointer reg contents and the stack pointer reg contents, as of the start of
781 the function body. This depends on the layout of the fixed parts of the
782 stack frame and on how registers are saved. */
783 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
784 { \
785 int regno; \
786 int offset = 12; \
787 \
788 for (regno = 0; regno < FRAME_POINTER_REGNUM; regno++) \
789 if (regs_ever_live[regno]) \
790 offset += 4; \
791 for (regno = 20; regno < 24; regno++) \
792 if (regs_ever_live[regno]) \
793 offset += 12; \
794 (DEPTH) = offset + (get_frame_size () + 3 & ~3); \
795 }
796
797 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
798 (DEPTH) = (get_frame_size () + 3) & ~3;
799 #endif
800 /* Output assembler code for a block containing the constant parts
801 of a trampoline, leaving space for the variable parts.
802
803 On the ARM, (if r8 is the static chain regnum, and remembering that
804 referencing pc adds an offset of 8) the trampoline looks like:
805 ldr r8, [pc, #0]
806 ldr pc, [pc]
807 .word static chain value
808 .word function's address */
809 #define TRAMPOLINE_TEMPLATE(FILE) \
810 { \
811 fprintf ((FILE), "\tldr\tr8, [pc, #0]\n"); \
812 fprintf ((FILE), "\tldr\tpc, [pc, #0]\n"); \
813 fprintf ((FILE), "\t.word\t0\n"); \
814 fprintf ((FILE), "\t.word\t0\n"); \
815 }
816
817 /* Length in units of the trampoline for entering a nested function. */
818 #define TRAMPOLINE_SIZE 16
819
820 /* Alignment required for a trampoline in units. */
821 #define TRAMPOLINE_ALIGN 4
822
823 /* Emit RTL insns to initialize the variable parts of a trampoline.
824 FNADDR is an RTX for the address of the function's pure code.
825 CXT is an RTX for the static chain value for the function. */
826 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
827 { \
828 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
829 (CXT)); \
830 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
831 (FNADDR)); \
832 }
833
834 /* Call the function profiler with a given profile label. The Acorn compiler
835 puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
836 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
837 to mind about this! */
838 #define FUNCTION_PROFILER(STREAM,LABELNO) \
839 { \
840 fprintf(STREAM, "\tmov\tip, lr\n"); \
841 fprintf(STREAM, "\tbl\tmcount\n"); \
842 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
843 arm_increase_location (12); \
844 }
845 \f
846 /* Addressing modes, and classification of registers for them. */
847
848 #define HAVE_POST_INCREMENT 1
849 #define HAVE_PRE_INCREMENT 1
850 #define HAVE_POST_DECREMENT 1
851 #define HAVE_PRE_DECREMENT 1
852
853 /* Macros to check register numbers against specific register classes. */
854
855 /* These assume that REGNO is a hard or pseudo reg number.
856 They give nonzero only if REGNO is a hard reg of the suitable class
857 or a pseudo reg currently allocated to a suitable hard reg.
858 Since they use reg_renumber, they are safe only once reg_renumber
859 has been allocated, which happens in local-alloc.c.
860
861 On the ARM, don't allow the pc to be used. */
862 #define REGNO_OK_FOR_BASE_P(REGNO) \
863 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
864 || (REGNO) == ARG_POINTER_REGNUM \
865 || (unsigned) reg_renumber[(REGNO)] < 15 \
866 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
867 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
868 #define REGNO_OK_FOR_INDEX_P(REGNO) \
869 REGNO_OK_FOR_BASE_P(REGNO)
870
871 /* Maximum number of registers that can appear in a valid memory address.
872 Shifts in addresses can't be by a register. */
873
874 #define MAX_REGS_PER_ADDRESS 2
875
876 /* Recognize any constant value that is a valid address. */
877 /* XXX We can address any constant, eventually... */
878 #if 0
879 #define CONSTANT_ADDRESS_P(X) \
880 ( GET_CODE(X) == LABEL_REF \
881 || GET_CODE(X) == SYMBOL_REF \
882 || GET_CODE(X) == CONST_INT \
883 || GET_CODE(X) == CONST )
884 #endif
885
886 #define CONSTANT_ADDRESS_P(X) \
887 (GET_CODE (X) == SYMBOL_REF \
888 && (CONSTANT_POOL_ADDRESS_P (X) || SYMBOL_REF_FLAG (X)))
889
890 /* Nonzero if the constant value X is a legitimate general operand.
891 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
892
893 On the ARM, allow any integer (invalid ones are removed later by insn
894 patterns), nice doubles and symbol_refs which refer to the function's
895 constant pool XXX. */
896 #define LEGITIMATE_CONSTANT_P(X) \
897 (GET_CODE (X) == CONST_INT \
898 || (GET_CODE (X) == CONST_DOUBLE \
899 && (const_double_rtx_ok_for_fpu (X) \
900 || neg_const_double_rtx_ok_for_fpu (X))) \
901 || CONSTANT_ADDRESS_P (X))
902
903 /* Symbols in the text segment can be accessed without indirecting via the
904 constant pool; it may take an extra binary operation, but this is still
905 faster than indirecting via memory. */
906
907 #define ENCODE_SECTION_INFO(decl) \
908 { \
909 if (TREE_CONSTANT (decl) \
910 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
911 { \
912 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
913 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
914 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
915 } \
916 }
917
918 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
919 and check its validity for a certain class.
920 We have two alternate definitions for each of them.
921 The usual definition accepts all pseudo regs; the other rejects
922 them unless they have been allocated suitable hard regs.
923 The symbol REG_OK_STRICT causes the latter definition to be used. */
924 #ifndef REG_OK_STRICT
925
926 /* Nonzero if X is a hard reg that can be used as a base reg
927 or if it is a pseudo reg. */
928 #define REG_OK_FOR_BASE_P(X) \
929 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
930 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
931
932 /* Nonzero if X is a hard reg that can be used as an index
933 or if it is a pseudo reg. */
934 #define REG_OK_FOR_INDEX_P(X) \
935 REG_OK_FOR_BASE_P(X)
936
937 #define REG_OK_FOR_PRE_POST_P(X) \
938 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
939 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
940
941 #else
942
943 /* Nonzero if X is a hard reg that can be used as a base reg. */
944 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
945
946 /* Nonzero if X is a hard reg that can be used as an index. */
947 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
948
949 #define REG_OK_FOR_PRE_POST_P(X) \
950 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
951 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
952 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
953 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
954
955 #endif
956 \f
957 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
958 that is a valid memory address for an instruction.
959 The MODE argument is the machine mode for the MEM expression
960 that wants to use this address.
961
962 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
963 #define BASE_REGISTER_RTX_P(X) \
964 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
965
966 #define INDEX_REGISTER_RTX_P(X) \
967 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
968
969 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
970 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
971 only be small constants. */
972 #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
973 do \
974 { \
975 int range; \
976 int code = GET_CODE (INDEX); \
977 \
978 if (GET_MODE_CLASS (MODE) == MODE_FLOAT) \
979 { \
980 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
981 && INTVAL (INDEX) > -1024 \
982 && (INTVAL (INDEX) & 3) == 0) \
983 goto LABEL; \
984 } \
985 else \
986 { \
987 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
988 goto LABEL; \
989 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT) \
990 { \
991 rtx xiop0 = XEXP (INDEX, 0); \
992 rtx xiop1 = XEXP (INDEX, 1); \
993 if (INDEX_REGISTER_RTX_P (xiop0) \
994 && power_of_two_operand (xiop1, SImode)) \
995 goto LABEL; \
996 if (INDEX_REGISTER_RTX_P (xiop1) \
997 && power_of_two_operand (xiop0, SImode)) \
998 goto LABEL; \
999 } \
1000 if (GET_MODE_SIZE (MODE) <= 4 \
1001 && (code == LSHIFTRT || code == ASHIFTRT \
1002 || code == ASHIFT || code == ROTATERT)) \
1003 { \
1004 rtx op = XEXP (INDEX, 1); \
1005 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
1006 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
1007 && INTVAL (op) <= 31) \
1008 goto LABEL; \
1009 } \
1010 range = (MODE) == HImode ? 4095 : 4096; \
1011 if (code == CONST_INT && INTVAL (INDEX) < range \
1012 && INTVAL (INDEX) > -range) \
1013 goto LABEL; \
1014 } \
1015 } while (0)
1016
1017 /* Jump to LABEL if X is a valid address RTX. This must also take
1018 REG_OK_STRICT into account when deciding about valid registers, but it uses
1019 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
1020 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
1021 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
1022 refs must be forced though a static cell to ensure addressability. */
1023 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1024 { \
1025 if (BASE_REGISTER_RTX_P (X)) \
1026 goto LABEL; \
1027 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1028 && GET_CODE (XEXP (X, 0)) == REG \
1029 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1030 goto LABEL; \
1031 else if ((MODE) == TImode) \
1032 ; \
1033 else if (GET_CODE (X) == PLUS) \
1034 { \
1035 rtx xop0 = XEXP(X,0); \
1036 rtx xop1 = XEXP(X,1); \
1037 \
1038 if (BASE_REGISTER_RTX_P (xop0)) \
1039 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1040 else if (BASE_REGISTER_RTX_P (xop1)) \
1041 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1042 } \
1043 else if (GET_CODE (X) == MINUS) \
1044 { \
1045 rtx xop0 = XEXP (X,0); \
1046 rtx xop1 = XEXP (X,1); \
1047 \
1048 if (BASE_REGISTER_RTX_P (xop0)) \
1049 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1050 } \
1051 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1052 && GET_CODE (X) == SYMBOL_REF \
1053 && CONSTANT_POOL_ADDRESS_P (X)) \
1054 goto LABEL; \
1055 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1056 && GET_CODE (XEXP (X, 0)) == REG \
1057 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1058 goto LABEL; \
1059 }
1060 \f
1061 /* Try machine-dependent ways of modifying an illegitimate address
1062 to be legitimate. If we find one, return the new, valid address.
1063 This macro is used in only one place: `memory_address' in explow.c.
1064
1065 OLDX is the address as it was before break_out_memory_refs was called.
1066 In some cases it is useful to look at this to decide what needs to be done.
1067
1068 MODE and WIN are passed so that this macro can use
1069 GO_IF_LEGITIMATE_ADDRESS.
1070
1071 It is always safe for this macro to do nothing. It exists to recognize
1072 opportunities to optimize the output.
1073
1074 On the ARM, try to convert [REG, #BIGCONST]
1075 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1076 where VALIDCONST == 0 in case of TImode. */
1077 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1078 { \
1079 if (GET_CODE (X) == PLUS) \
1080 { \
1081 rtx xop0 = XEXP (X, 0); \
1082 rtx xop1 = XEXP (X, 1); \
1083 \
1084 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1085 { \
1086 int n = INTVAL (xop1); \
1087 int low_n = ((MODE) == TImode ? 0 \
1088 : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \
1089 rtx base_reg = gen_reg_rtx (SImode); \
1090 rtx val = force_operand (gen_rtx (PLUS, SImode, xop0, \
1091 gen_rtx (CONST_INT, \
1092 VOIDmode, n - low_n)), \
1093 0); \
1094 emit_move_insn (base_reg, val); \
1095 (X) = (low_n == 0 ? base_reg \
1096 : gen_rtx (PLUS, SImode, base_reg, \
1097 gen_rtx (CONST_INT, VOIDmode, low_n))); \
1098 } \
1099 else if (BASE_REGISTER_RTX_P (xop1) && GET_CODE (xop0) == CONST_INT) \
1100 { \
1101 int n = INTVAL (xop0); \
1102 int low_n = ((MODE) == TImode ? 0 \
1103 : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \
1104 rtx base_reg = gen_reg_rtx (SImode); \
1105 rtx val = force_operand (gen_rtx (PLUS, SImode, xop1, \
1106 gen_rtx (CONST_INT, \
1107 VOIDmode, n - low_n)), \
1108 0); \
1109 emit_move_insn (base_reg, val); \
1110 (X) = (low_n == 0 ? base_reg \
1111 : gen_rtx (PLUS, SImode, base_reg, \
1112 gen_rtx (CONST_INT, VOIDmode, low_n))); \
1113 } \
1114 } \
1115 if (memory_address_p (MODE, X)) \
1116 goto win; \
1117 }
1118
1119 /* Go to LABEL if ADDR (a legitimate address expression)
1120 has an effect that depends on the machine mode it is used for. */
1121 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1122 { \
1123 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1124 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1125 goto LABEL; \
1126 }
1127 \f
1128 /* Specify the machine mode that this machine uses
1129 for the index in the tablejump instruction. */
1130 #define CASE_VECTOR_MODE SImode
1131
1132 /* Define this if the tablejump instruction expects the table
1133 to contain offsets from the address of the table.
1134 Do not define this if the table should contain absolute addresses. */
1135 /* #define CASE_VECTOR_PC_RELATIVE */
1136
1137 /* Specify the tree operation to be used to convert reals to integers. */
1138 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1139
1140 /* This is the kind of divide that is easiest to do in the general case. */
1141 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1142
1143 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
1144 unsigned is probably best, but may break some code. */
1145 #ifndef DEFAULT_SIGNED_CHAR
1146 #define DEFAULT_SIGNED_CHAR 1
1147 #endif
1148
1149 /* Don't cse the address of the function being compiled. */
1150 #define NO_RECURSIVE_FUNCTION_CSE 1
1151
1152 /* Max number of bytes we can move from memory to memory
1153 in one reasonably fast instruction. */
1154 #define MOVE_MAX 4
1155
1156 /* Define if operations between registers always perform the operation
1157 on the full register even if a narrower mode is specified. */
1158 #define WORD_REGISTER_OPERATIONS
1159
1160 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1161 will either zero-extend or sign-extend. The value of this macro should
1162 be the code that says which one of the two operations is implicitly
1163 done, NIL if none. */
1164 #define LOAD_EXTEND_OP(MODE) \
1165 ((MODE) == QImode ? ZERO_EXTEND : NIL)
1166
1167 /* Define this if zero-extension is slow (more than one real instruction).
1168 On the ARM, it is more than one instruction only if not fetching from
1169 memory. */
1170 /* #define SLOW_ZERO_EXTEND */
1171
1172 /* Nonzero if access to memory by bytes is slow and undesirable. */
1173 #define SLOW_BYTE_ACCESS 0
1174
1175 /* Immediate shift counts are truncated by the output routines (or was it
1176 the assembler?). Shift counts in a register are truncated by ARM. Note
1177 that the native compiler puts too large (> 32) immediate shift counts
1178 into a register and shifts by the register, letting the ARM decide what
1179 to do instead of doing that itself. */
1180 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1181 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1182 On the arm, Y in a register is used modulo 256 for the shift. Only for
1183 rotates is modulo 32 used. */
1184 /* #define SHIFT_COUNT_TRUNCATED 1 */
1185
1186 /* XX This is not true, is it? */
1187 /* All integers have the same format so truncation is easy. */
1188 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1189
1190 /* Calling from registers is a massive pain. */
1191 #define NO_FUNCTION_CSE 1
1192
1193 /* Chars and shorts should be passed as ints. */
1194 #define PROMOTE_PROTOTYPES 1
1195
1196 /* The machine modes of pointers and functions */
1197 #define Pmode SImode
1198 #define FUNCTION_MODE Pmode
1199
1200 /* The structure type of the machine dependent info field of insns
1201 No uses for this yet. */
1202 /* #define INSN_MACHINE_INFO struct machine_info */
1203
1204 /* The relative costs of various types of constants. Note that cse.c defines
1205 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1206 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1207 case CONST_INT: \
1208 if (const_ok_for_arm (INTVAL (RTX))) \
1209 return (OUTER_CODE) == SET ? 2 : -1; \
1210 else if (OUTER_CODE == AND \
1211 && const_ok_for_arm (~INTVAL (RTX))) \
1212 return -1; \
1213 else if ((OUTER_CODE == COMPARE \
1214 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1215 && const_ok_for_arm (-INTVAL (RTX))) \
1216 return -1; \
1217 else \
1218 return 5; \
1219 case CONST: \
1220 case LABEL_REF: \
1221 case SYMBOL_REF: \
1222 return 6; \
1223 case CONST_DOUBLE: \
1224 if (const_double_rtx_ok_for_fpu (RTX)) \
1225 return (OUTER_CODE) == SET ? 2 : -1; \
1226 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1227 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1228 return -1; \
1229 return(7);
1230
1231 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1232 case MEM: \
1233 { \
1234 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1;\
1235 return (COSTS_N_INSNS (10*num_words)); \
1236 } \
1237 case MULT: \
1238 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1239 && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \
1240 return rtx_cost (XEXP (X, 0), GET_CODE (X))+1; \
1241 return COSTS_N_INSNS (9); \
1242 case ASHIFT: \
1243 case LSHIFTRT: \
1244 case ASHIFTRT: \
1245 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1246 return rtx_cost (XEXP (X, 0), GET_CODE (X))+1; \
1247 break; \
1248 case MINUS: \
1249 { \
1250 enum rtx_code code = GET_CODE (XEXP (X, 1)); \
1251 if (code == MULT) \
1252 { \
1253 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT \
1254 && exact_log2 (INTVAL (XEXP (XEXP (X, 0), 1))) >= 0) \
1255 return COSTS_N_INSNS (1); \
1256 break; \
1257 } \
1258 else if (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT) \
1259 return COSTS_N_INSNS (1); \
1260 } /* fall through */ \
1261 case PLUS: \
1262 case IOR: \
1263 case XOR: \
1264 case AND: \
1265 { \
1266 enum rtx_code code = GET_CODE (XEXP (X, 0)); \
1267 if (code == MULT) \
1268 { \
1269 if (GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1270 && exact_log2 (INTVAL (XEXP (XEXP (X, 0), 1))) >= 0) \
1271 return COSTS_N_INSNS (1); \
1272 if (GET_CODE (X) == PLUS) \
1273 return COSTS_N_INSNS (12); \
1274 break; \
1275 } \
1276 else if (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT) \
1277 return COSTS_N_INSNS (1); \
1278 break; \
1279 } \
1280 case NOT: \
1281 return rtx_cost (XEXP (X, 0), GET_CODE (XEXP (X, 0))); \
1282 case IF_THEN_ELSE: \
1283 { \
1284 if (GET_CODE (XEXP(X,1)) == PC || GET_CODE (XEXP(X,2)) == PC) \
1285 return COSTS_N_INSNS (4); \
1286 return COSTS_N_INSNS (1); \
1287 } \
1288 case SIGN_EXTEND: \
1289 return COSTS_N_INSNS (2); \
1290 case ZERO_EXTEND: \
1291 if (GET_MODE (XEXP (X, 0)) == QImode) \
1292 { \
1293 if (GET_CODE (XEXP (X, 0)) == MEM) \
1294 return COSTS_N_INSNS (10); \
1295 return COSTS_N_INSNS (1); \
1296 } \
1297 break; \
1298 case COMPARE: \
1299 if (GET_CODE (XEXP (X, 1)) == REG) \
1300 return 4; \
1301 case SMIN: \
1302 case SMAX: \
1303 case UMIN: \
1304 case UMAX: \
1305 return COSTS_N_INSNS (3); \
1306 case ABS: \
1307 if (GET_MODE (X) == SImode) \
1308 return COSTS_N_INSNS (2); \
1309 return COSTS_N_INSNS (1);
1310
1311 /* Moves to and from memory are quite expensive */
1312 #define MEMORY_MOVE_COST(MODE) 10
1313
1314 /* All address computations that can be done are free */
1315 #define ADDRESS_COST(x) 2
1316
1317 /* Try to generate sequences that don't involve branches, we can then use
1318 conditional instructions */
1319 #define BRANCH_COST 4
1320 \f
1321 /* Condition code information. */
1322 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1323 return the mode to be used for the comparison.
1324 CCFPEmode should be used with floating inequalites,
1325 CCFPmode should be used with floating equalities.
1326 CC_NOOVmode should be used with SImode integer equalites
1327 CCmode should be used otherwise. */
1328
1329 #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1330
1331 #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1332
1333 #define SELECT_CC_MODE(OP,X,Y) \
1334 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1335 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1336 : ((GET_MODE (X) == SImode) \
1337 && ((OP) == EQ || (OP) == NE) \
1338 && (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1339 || GET_CODE (X) == AND || GET_CODE (X) == IOR \
1340 || GET_CODE (X) == XOR || GET_CODE (X) == MULT \
1341 || GET_CODE (X) == NOT || GET_CODE (X) == NEG \
1342 || GET_CODE (X) == LSHIFTRT \
1343 || GET_CODE (X) == ASHIFT || GET_CODE (X) == ASHIFTRT \
1344 || GET_CODE (X) == ROTATERT || GET_CODE (X) == ZERO_EXTRACT) \
1345 ? CC_NOOVmode \
1346 : GET_MODE (X) == QImode ? CC_NOOVmode : CCmode))
1347
1348 #define STORE_FLAG_VALUE 1
1349
1350 /* Define the information needed to generate branch insns. This is
1351 stored from the compare operation. Note that we can't use "rtx" here
1352 since it hasn't been defined! */
1353
1354 extern struct rtx_def *arm_compare_op0, *arm_compare_op1;
1355 extern int arm_compare_fp;
1356
1357 /* Define the codes that are matched by predicates in arm.c */
1358 #define PREDICATE_CODES \
1359 {"s_register_operand", {SUBREG, REG}}, \
1360 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1361 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1362 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1363 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1364 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1365 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1366 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
1367 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, MULT}}, \
1368 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1369 {"load_multiple_operation", {PARALLEL}}, \
1370 {"store_multiple_operation", {PARALLEL}}, \
1371 {"equality_operator", {EQ, NE}}, \
1372 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1373 {"const_shift_operand", {CONST_INT}}, \
1374 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1375 {"cc_register", {REG}},
1376
1377 \f
1378 /* Assembler output control */
1379
1380 #ifndef ARM_OS_NAME
1381 #define ARM_OS_NAME "(generic)"
1382 #endif
1383
1384 /* The text to go at the start of the assembler file */
1385 #define ASM_FILE_START(STREAM) \
1386 { \
1387 extern char *version_string; \
1388 \
1389 fprintf (STREAM,"@ Generated by gcc %s for ARM/%s\n", version_string, \
1390 ARM_OS_NAME); \
1391 fprintf (STREAM,"rfp\t.req\tr9\n"); \
1392 fprintf (STREAM,"fp\t.req\tr11\n"); \
1393 fprintf (STREAM,"ip\t.req\tr12\n"); \
1394 fprintf (STREAM,"sp\t.req\tr13\n"); \
1395 fprintf (STREAM,"lr\t.req\tr14\n"); \
1396 fprintf (STREAM,"pc\t.req\tr15\n"); \
1397 }
1398
1399 #define ASM_APP_ON ""
1400 #define ASM_APP_OFF ""
1401
1402 /* Switch to the text or data segment. */
1403 #define TEXT_SECTION_ASM_OP ".text"
1404 #define DATA_SECTION_ASM_OP ".data"
1405
1406 /* The assembler's names for the registers. RFP need not always be used as
1407 the Real framepointer; it can also be used as a normal general register.
1408 Note that the name `fp' is horribly misleading since `fp' is in fact only
1409 the argument-and-return-context pointer. */
1410 #define REGISTER_NAMES \
1411 { \
1412 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1413 "r8","rfp", "sl", "fp", "ip", "sp", "lr", "pc", \
1414 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1415 "cc", "sfp", "afp" \
1416 }
1417
1418 /* Arm Assembler barfs on dollars */
1419 #define DOLLARS_IN_IDENTIFIERS 0
1420
1421 #define NO_DOLLAR_IN_LABEL
1422
1423 /* DBX register number for a given compiler register number */
1424 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1425
1426 /* Generate DBX debugging information. riscix.h will undefine this because
1427 the native assembler does not support stabs. */
1428 #define DBX_DEBUGGING_INFO 1
1429
1430 /* Acorn dbx moans about continuation chars, so don't use any. */
1431 #define DBX_CONTIN_LENGTH 0
1432
1433 /* Output a source filename for the debugger. RISCiX dbx insists that the
1434 ``desc'' field is set to compiler version number >= 315 (sic). */
1435 #define DBX_OUTPUT_MAIN_SOURCE_FILENAME(STREAM,NAME) \
1436 do { \
1437 fprintf (STREAM, ".stabs \"%s\",%d,0,315,%s\n", (NAME), N_SO, \
1438 &ltext_label_name[1]); \
1439 text_section (); \
1440 ASM_OUTPUT_INTERNAL_LABEL (STREAM, "Ltext", 0); \
1441 } while (0)
1442
1443 /* Output a label definition. */
1444 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
1445 arm_asm_output_label ((STREAM), (NAME))
1446
1447 /* Output a function label definition. */
1448 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1449 ASM_OUTPUT_LABEL(STREAM, NAME)
1450
1451 /* Output a globalising directive for a label. */
1452 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1453 (fprintf (STREAM, "\t.global\t"), \
1454 assemble_name (STREAM, NAME), \
1455 fputc ('\n',STREAM)) \
1456
1457 /* Output a reference to a label. */
1458 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1459 fprintf (STREAM, "_%s", NAME)
1460
1461 /* Make an internal label into a string. */
1462 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1463 sprintf (STRING, "*%s%d", PREFIX, NUM)
1464
1465 /* Output an internal label definition. */
1466 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1467 do \
1468 { \
1469 char *s = (char *) alloca (11 + strlen (PREFIX)); \
1470 extern int arm_target_label, arm_ccfsm_state; \
1471 extern rtx arm_target_insn; \
1472 \
1473 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1474 && !strcmp (PREFIX, "L")) \
1475 { \
1476 arm_ccfsm_state = 0; \
1477 arm_target_insn = NULL; \
1478 } \
1479 strcpy (s, "*"); \
1480 sprintf (&s[strlen (s)], "%s%d", (PREFIX), (NUM)); \
1481 arm_asm_output_label (STREAM, s); \
1482 } while (0)
1483
1484 /* Nothing special is done about jump tables */
1485 /* #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) */
1486 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1487
1488 /* Construct a private name. */
1489 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1490 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1491 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1492
1493 /* Output a push or a pop instruction (only used when profiling). */
1494 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1495 (arm_increase_location (4) \
1496 , fprintf(STREAM,"\tstmfd\tsp!,{%s}\n", reg_names[REGNO]))
1497
1498 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1499 (arm_increase_location (4) \
1500 , fprintf(STREAM,"\tldmfd\tsp!,{%s}\n", reg_names[REGNO]))
1501
1502 /* Output a relative address. Not needed since jump tables are absolute
1503 but we must define it anyway. */
1504 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1505 fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
1506
1507 /* Output an element of a dispatch table. */
1508 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1509 (arm_increase_location (4) \
1510 , fprintf (STREAM, "\t.word\tL%d\n", VALUE))
1511
1512 /* Output various types of constants. For real numbers we output hex, with
1513 a comment containing the "human" value, this allows us to pass NaN's which
1514 the riscix assembler doesn't understand (it also makes cross-assembling
1515 less likely to fail). */
1516
1517 #define ASM_OUTPUT_LONG_DOUBLE(STREAM,VALUE) \
1518 do { char dstr[30]; \
1519 long l[3]; \
1520 arm_increase_location (12); \
1521 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
1522 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1523 if (sizeof (int) == sizeof (long)) \
1524 fprintf (STREAM, "\t.long 0x%x,0x%x,0x%x\t@ long double %s\n", \
1525 l[2], l[1], l[0], dstr); \
1526 else \
1527 fprintf (STREAM, "\t.long 0x%lx,0x%lx,0x%lx\t@ long double %s\n",\
1528 l[0], l[1], l[2], dstr); \
1529 } while (0)
1530
1531
1532 #define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \
1533 do { char dstr[30]; \
1534 long l[2]; \
1535 arm_increase_location (8); \
1536 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
1537 REAL_VALUE_TO_DECIMAL (VALUE, "%.14g", dstr); \
1538 if (sizeof (int) == sizeof (long)) \
1539 fprintf (STREAM, "\t.long 0x%x, 0x%x\t@ double %s\n", l[0], l[1],\
1540 dstr); \
1541 else \
1542 fprintf (STREAM, "\t.long 0x%lx, 0x%lx\t@ double %s\n", l[0], \
1543 l[1], dstr); \
1544 } while (0)
1545
1546 #define ASM_OUTPUT_FLOAT(STREAM, VALUE) \
1547 do { char dstr[30]; \
1548 long l; \
1549 arm_increase_location (4); \
1550 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1551 REAL_VALUE_TO_DECIMAL (VALUE, "%.7g", dstr); \
1552 if (sizeof (int) == sizeof (long)) \
1553 fprintf (STREAM, "\t.word 0x%x\t@ float %s\n", l, dstr); \
1554 else \
1555 fprintf (STREAM, "\t.word 0x%lx\t@ float %s\n", l, dstr); \
1556 } while (0);
1557
1558 #define ASM_OUTPUT_INT(STREAM, EXP) \
1559 (fprintf (STREAM, "\t.word\t"), \
1560 output_addr_const (STREAM, (EXP)), \
1561 arm_increase_location (4), \
1562 fputc ('\n', STREAM))
1563
1564 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1565 (fprintf (STREAM, "\t.short\t"), \
1566 output_addr_const (STREAM, (EXP)), \
1567 arm_increase_location (2), \
1568 fputc ('\n', STREAM))
1569
1570 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1571 (fprintf (STREAM, "\t.byte\t"), \
1572 output_addr_const (STREAM, (EXP)), \
1573 arm_increase_location (1), \
1574 fputc ('\n', STREAM))
1575
1576 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1577 (fprintf (STREAM, "\t.byte\t%d\n", VALUE), \
1578 arm_increase_location (1))
1579
1580 #define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \
1581 output_ascii_pseudo_op ((STREAM), (unsigned char *)(PTR), (LEN))
1582
1583 /* Output a gap. In fact we fill it with nulls. */
1584 #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
1585 (arm_increase_location (NBYTES), \
1586 fprintf (STREAM, "\t.space\t%d\n", NBYTES))
1587
1588 /* Align output to a power of two. Horrible /bin/as. */
1589 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1590 do \
1591 { \
1592 register int amount = 1 << (POWER); \
1593 extern int arm_text_location; \
1594 \
1595 if (amount == 2) \
1596 fprintf (STREAM, "\t.even\n"); \
1597 else \
1598 fprintf (STREAM, "\t.align\t%d\n", amount - 4); \
1599 \
1600 if (in_text_section ()) \
1601 arm_text_location = ((arm_text_location + amount - 1) \
1602 & ~(amount - 1)); \
1603 } while (0)
1604
1605 /* Output a common block */
1606 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
1607 (fprintf (STREAM, "\t.comm\t"), \
1608 assemble_name ((STREAM), (NAME)), \
1609 fprintf(STREAM, ", %d\t@%d\n", ROUNDED, SIZE))
1610
1611 /* Output a local common block. /bin/as can't do this, so hack a `.space' into
1612 the bss segment. Note that this is *bad* practice. */
1613 #define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \
1614 output_lcomm_directive (STREAM, NAME, SIZE, ROUNDED)
1615
1616 /* Output a source filename for the debugger. RISCiX dbx insists that the
1617 ``desc'' field is set to compiler version number >= 315 (sic). */
1618 #if 0
1619 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM,NAME) \
1620 fprintf (STREAM, "\t.stabs\t\"%s\", %d, 0, 315, Ltext\n", (NAME), N_SOL)
1621 #endif
1622
1623 /* Output a source line for the debugger. */
1624 /* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */
1625
1626 /* Output a #ident directive. */
1627 #define ASM_OUTPUT_IDENT(STREAM,STRING) \
1628 fprintf (STREAM,"- - - ident %s\n",STRING)
1629
1630 /* The assembler's parentheses characters. */
1631 #define ASM_OPEN_PAREN "("
1632 #define ASM_CLOSE_PAREN ")"
1633
1634 /* Target characters. */
1635 #define TARGET_BELL 007
1636 #define TARGET_BS 010
1637 #define TARGET_TAB 011
1638 #define TARGET_NEWLINE 012
1639 #define TARGET_VT 013
1640 #define TARGET_FF 014
1641 #define TARGET_CR 015
1642 \f
1643 /* FINAL_PRESCAN_INSN is used to take a look at the insns, in order to delete
1644 small-distance conditional branches and have ASM_OUTPUT_OPCODE make the
1645 instructions conditional. Suffixes like s (affect flags) and b (bytewise
1646 load/store) need to stay suffixes, so the possible condition code comes
1647 before these suffixes. %d<n> or %D<n> may appear in the opcode if
1648 it can take a condition; a null rtx will cause no condition to be added,
1649 this is what we expect to happen if arm_ccfsm_state is non-zero. */
1650 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1651 { \
1652 extern int arm_ccfsm_state, arm_current_cc; \
1653 extern char *arm_condition_codes[]; \
1654 int i; \
1655 \
1656 fflush (STREAM); /* XXX for debugging only. */ \
1657 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) \
1658 { \
1659 for (i = 0; *(PTR) != ' ' && *(PTR) != '\t' && *(PTR) != '%' && i < 3;\
1660 i++, (PTR)++) \
1661 putc (*(PTR), STREAM); \
1662 fprintf (STREAM, "%s", arm_condition_codes[arm_current_cc]); \
1663 for (; *(PTR) != ' ' && *(PTR) != '\t' && *(PTR) != '%'; (PTR)++) \
1664 putc (*(PTR), STREAM); \
1665 } \
1666 }
1667
1668 /* Only perform branch elimination (by making instructions conditional) if
1669 we're optimising. Otherwise it's of no use anyway. */
1670 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1671 if (optimize) \
1672 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1673
1674 /* Output an operand of an instruction. If X is a REG and CODE is `M', output
1675 a ldm/stm style multi-reg. */
1676 #define PRINT_OPERAND(STREAM, X, CODE) \
1677 { \
1678 if ((CODE) == 'd') \
1679 { \
1680 if (X) \
1681 fputs (arm_condition_codes[get_arm_condition_code (X)], \
1682 (STREAM)); \
1683 } \
1684 else if ((CODE) == 'D') \
1685 { \
1686 if (X) \
1687 fputs (arm_condition_codes[get_arm_condition_code (X) ^ 1], \
1688 (STREAM)); \
1689 } \
1690 else if ((CODE) == 'R') \
1691 fputs (reg_names[REGNO (X) + 1], (STREAM)); \
1692 else if (GET_CODE (X) == REG) \
1693 { \
1694 if ((CODE) != 'M') \
1695 fputs (reg_names[REGNO (X)], (STREAM)); \
1696 else \
1697 fprintf ((STREAM), "{%s-%s}", \
1698 reg_names[REGNO (X)], \
1699 reg_names[REGNO (X) - 1 \
1700 + ((GET_MODE_SIZE (GET_MODE (X)) \
1701 + GET_MODE_SIZE (SImode) - 1) \
1702 / GET_MODE_SIZE (SImode))]); \
1703 } \
1704 else if (GET_CODE (X) == MEM) \
1705 { \
1706 extern int output_memory_reference_mode; \
1707 output_memory_reference_mode = GET_MODE (X); \
1708 output_address (XEXP (X, 0)); \
1709 } \
1710 else if (GET_CODE(X) == CONST_DOUBLE) \
1711 fprintf(STREAM,"#%s", fp_immediate_constant(X)); \
1712 else if (GET_CODE (X) == NEG) \
1713 { \
1714 fputc ('-', (STREAM)); \
1715 output_operand ((X), 0); \
1716 } \
1717 else \
1718 { \
1719 fputc('#', STREAM); \
1720 output_addr_const(STREAM, X); \
1721 } \
1722 }
1723
1724 /* Output the address of an operand. */
1725 #define PRINT_OPERAND_ADDRESS(STREAM,X) \
1726 { \
1727 int is_minus = GET_CODE (X) == MINUS; \
1728 \
1729 if (GET_CODE (X) == REG) \
1730 fprintf (STREAM, "[%s, #0]", reg_names[REGNO (X)]); \
1731 else if (GET_CODE (X) == PLUS || is_minus) \
1732 { \
1733 rtx base = XEXP (X, 0); \
1734 rtx index = XEXP (X, 1); \
1735 char *base_reg_name; \
1736 int offset = 0; \
1737 int shift; \
1738 if (GET_CODE (base) != REG) \
1739 { \
1740 /* Ensure that BASE is a register (one of them must be). */ \
1741 rtx temp = base; \
1742 base = index; \
1743 index = temp; \
1744 } \
1745 base_reg_name = reg_names[REGNO (base)]; \
1746 switch (GET_CODE (index)) \
1747 { \
1748 case CONST_INT: \
1749 offset = INTVAL (index); \
1750 if (is_minus) \
1751 offset = -offset; \
1752 fprintf (STREAM, "[%s, #%d]", base_reg_name, offset); \
1753 break; \
1754 \
1755 case REG: \
1756 fprintf (STREAM, "[%s, %s%s]", base_reg_name, \
1757 is_minus ? "-" : "", reg_names[REGNO (index)] ); \
1758 break; \
1759 \
1760 case MULT: \
1761 if (GET_CODE (XEXP (index,0)) == CONST_INT) \
1762 { \
1763 shift = int_log2 (INTVAL (XEXP (index, 0))); \
1764 index = XEXP (index, 1); \
1765 } \
1766 else if (GET_CODE(XEXP(index,1)) == CONST_INT) \
1767 { \
1768 shift = int_log2 (INTVAL (XEXP (index, 1))); \
1769 index = XEXP (index, 0); \
1770 } \
1771 else \
1772 abort(); \
1773 fprintf (STREAM, "[%s, %s%s, asl #%d]", base_reg_name, \
1774 is_minus ? "-" : "", reg_names[REGNO (index)], \
1775 shift); \
1776 break; \
1777 case ASHIFTRT: \
1778 case LSHIFTRT: \
1779 case ASHIFT: \
1780 case ROTATERT: \
1781 { \
1782 char *shift_type = shift_instr (GET_CODE (index), \
1783 &XEXP (index, 1)); \
1784 shift = INTVAL (XEXP (index, 1)); \
1785 index = XEXP (index, 0); \
1786 fprintf (STREAM, "[%s, %s%s, %s #%d]", base_reg_name, \
1787 is_minus ? "-" : "", reg_names[REGNO (index)], \
1788 shift_type, shift); \
1789 break; \
1790 } \
1791 \
1792 default: \
1793 abort(); \
1794 } \
1795 } \
1796 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1797 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1798 { \
1799 extern int output_memory_reference_mode; \
1800 \
1801 if (GET_CODE (XEXP (X, 0)) != REG) \
1802 abort (); \
1803 \
1804 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
1805 fprintf (STREAM, "[%s, #%s%d]!", reg_names[REGNO (XEXP (X, 0))],\
1806 GET_CODE (X) == PRE_DEC ? "-" : "", \
1807 GET_MODE_SIZE (output_memory_reference_mode)); \
1808 else \
1809 fprintf (STREAM, "[%s], #%s%d", reg_names[REGNO (XEXP (X, 0))], \
1810 GET_CODE (X) == POST_DEC ? "-" : "", \
1811 GET_MODE_SIZE (output_memory_reference_mode)); \
1812 } \
1813 else output_addr_const(STREAM, X); \
1814 }
1815
1816 /* EOF arm.h */
GNU Compiler Collection
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