1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 /* Forward definitions of types. */
55 typedef struct minipool_node Mnode
;
56 typedef struct minipool_fixup Mfix
;
58 const struct attribute_spec arm_attribute_table
[];
60 /* Forward function declarations. */
61 static void arm_add_gc_roots (void);
62 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, HOST_WIDE_INT
,
64 static unsigned bit_count (unsigned long);
65 static int arm_address_register_rtx_p (rtx
, int);
66 static int arm_legitimate_index_p (enum machine_mode
, rtx
, int);
67 static int thumb_base_register_rtx_p (rtx
, enum machine_mode
, int);
68 inline static int thumb_index_register_rtx_p (rtx
, int);
69 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
70 static rtx
emit_multi_reg_push (int);
71 static rtx
emit_sfm (int, int);
73 static bool arm_assemble_integer (rtx
, unsigned int, int);
75 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
76 static arm_cc
get_arm_condition_code (rtx
);
77 static void init_fpa_table (void);
78 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
79 static rtx
is_jump_table (rtx
);
80 static const char *output_multi_immediate (rtx
*, const char *, const char *,
82 static void print_multi_reg (FILE *, const char *, int, int);
83 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
84 static struct machine_function
*arm_init_machine_status (void);
85 static int number_of_first_bit_set (int);
86 static void replace_symbols_in_block (tree
, rtx
, rtx
);
87 static void thumb_exit (FILE *, int, rtx
);
88 static void thumb_pushpop (FILE *, int, int);
89 static const char *thumb_condition_code (rtx
, int);
90 static rtx
is_jump_table (rtx
);
91 static HOST_WIDE_INT
get_jump_table_size (rtx
);
92 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
93 static Mnode
*add_minipool_forward_ref (Mfix
*);
94 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
95 static Mnode
*add_minipool_backward_ref (Mfix
*);
96 static void assign_minipool_offsets (Mfix
*);
97 static void arm_print_value (FILE *, rtx
);
98 static void dump_minipool (rtx
);
99 static int arm_barrier_cost (rtx
);
100 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
101 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
102 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
104 static void arm_reorg (void);
105 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
106 static int current_file_function_operand (rtx
);
107 static unsigned long arm_compute_save_reg0_reg12_mask (void);
108 static unsigned long arm_compute_save_reg_mask (void);
109 static unsigned long arm_isr_value (tree
);
110 static unsigned long arm_compute_func_type (void);
111 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
112 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
113 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
114 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
115 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT
);
116 static int arm_comp_type_attributes (tree
, tree
);
117 static void arm_set_default_type_attributes (tree
);
118 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
119 static int arm_use_dfa_pipeline_interface (void);
120 static int count_insns_for_constant (HOST_WIDE_INT
, int);
121 static int arm_get_strip_length (int);
122 static bool arm_function_ok_for_sibcall (tree
, tree
);
123 static void arm_internal_label (FILE *, const char *, unsigned long);
124 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
126 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
127 static bool arm_rtx_costs (rtx
, int, int, int *);
128 static int arm_address_cost (rtx
);
129 static bool arm_memory_load_p (rtx
);
130 static bool arm_cirrus_insn_p (rtx
);
131 static void cirrus_reorg (rtx
);
132 static void arm_init_builtins (void);
133 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
134 static void arm_init_iwmmxt_builtins (void);
135 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
136 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
137 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
138 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
140 #ifdef OBJECT_FORMAT_ELF
141 static void arm_elf_asm_named_section (const char *, unsigned int);
144 static void arm_encode_section_info (tree
, rtx
, int);
147 static void aof_globalize_label (FILE *, const char *);
148 static void aof_dump_imports (FILE *);
149 static void aof_dump_pic_table (FILE *);
150 static void aof_file_start (void);
151 static void aof_file_end (void);
155 /* Initialize the GCC target structure. */
156 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
157 #undef TARGET_MERGE_DECL_ATTRIBUTES
158 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
161 #undef TARGET_ATTRIBUTE_TABLE
162 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
165 #undef TARGET_ASM_BYTE_OP
166 #define TARGET_ASM_BYTE_OP "\tDCB\t"
167 #undef TARGET_ASM_ALIGNED_HI_OP
168 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
169 #undef TARGET_ASM_ALIGNED_SI_OP
170 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
171 #undef TARGET_ASM_GLOBALIZE_LABEL
172 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
173 #undef TARGET_ASM_FILE_START
174 #define TARGET_ASM_FILE_START aof_file_start
175 #undef TARGET_ASM_FILE_END
176 #define TARGET_ASM_FILE_END aof_file_end
178 #undef TARGET_ASM_ALIGNED_SI_OP
179 #define TARGET_ASM_ALIGNED_SI_OP NULL
180 #undef TARGET_ASM_INTEGER
181 #define TARGET_ASM_INTEGER arm_assemble_integer
184 #undef TARGET_ASM_FUNCTION_PROLOGUE
185 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
187 #undef TARGET_ASM_FUNCTION_EPILOGUE
188 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
190 #undef TARGET_COMP_TYPE_ATTRIBUTES
191 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
193 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
194 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
196 #undef TARGET_SCHED_ADJUST_COST
197 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
199 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
200 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface
202 #undef TARGET_ENCODE_SECTION_INFO
204 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
206 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
209 #undef TARGET_STRIP_NAME_ENCODING
210 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
212 #undef TARGET_ASM_INTERNAL_LABEL
213 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
215 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
216 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
218 #undef TARGET_ASM_OUTPUT_MI_THUNK
219 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
220 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
221 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
223 #undef TARGET_RTX_COSTS
224 #define TARGET_RTX_COSTS arm_rtx_costs
225 #undef TARGET_ADDRESS_COST
226 #define TARGET_ADDRESS_COST arm_address_cost
228 #undef TARGET_MACHINE_DEPENDENT_REORG
229 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
231 #undef TARGET_INIT_BUILTINS
232 #define TARGET_INIT_BUILTINS arm_init_builtins
233 #undef TARGET_EXPAND_BUILTIN
234 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
236 struct gcc_target targetm
= TARGET_INITIALIZER
;
238 /* Obstack for minipool constant handling. */
239 static struct obstack minipool_obstack
;
240 static char * minipool_startobj
;
242 /* The maximum number of insns skipped which
243 will be conditionalised if possible. */
244 static int max_insns_skipped
= 5;
246 extern FILE * asm_out_file
;
248 /* True if we are currently building a constant table. */
249 int making_const_table
;
251 /* Define the information needed to generate branch insns. This is
252 stored from the compare operation. */
253 rtx arm_compare_op0
, arm_compare_op1
;
255 /* What type of floating point are we tuning for? */
256 enum fputype arm_fpu_tune
;
258 /* What type of floating point instructions are available? */
259 enum fputype arm_fpu_arch
;
261 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
262 enum prog_mode_type arm_prgmode
;
264 /* Set by the -mfp=... option. */
265 const char * target_fp_name
= NULL
;
267 /* Used to parse -mstructure_size_boundary command line option. */
268 const char * structure_size_string
= NULL
;
269 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
271 /* Bit values used to identify processor capabilities. */
272 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
273 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
274 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
275 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
276 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
277 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
278 #define FL_THUMB (1 << 6) /* Thumb aware */
279 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
280 #define FL_STRONG (1 << 8) /* StrongARM */
281 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
282 #define FL_XSCALE (1 << 10) /* XScale */
283 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
284 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
286 /* The bits in this mask specify which
287 instructions we are allowed to generate. */
288 static unsigned long insn_flags
= 0;
290 /* The bits in this mask specify which instruction scheduling options should
291 be used. Note - there is an overlap with the FL_FAST_MULT. For some
292 hardware we want to be able to generate the multiply instructions, but to
293 tune as if they were not present in the architecture. */
294 static unsigned long tune_flags
= 0;
296 /* The following are used in the arm.md file as equivalents to bits
297 in the above two flag variables. */
299 /* Nonzero if this is an "M" variant of the processor. */
300 int arm_fast_multiply
= 0;
302 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
305 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
308 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
311 /* Nonzero if this chip can benefit from load scheduling. */
312 int arm_ld_sched
= 0;
314 /* Nonzero if this chip is a StrongARM. */
315 int arm_is_strong
= 0;
317 /* Nonzero if this chip supports Intel Wireless MMX technology. */
318 int arm_arch_iwmmxt
= 0;
320 /* Nonzero if this chip is an XScale. */
321 int arm_arch_xscale
= 0;
323 /* Nonzero if tuning for XScale */
324 int arm_tune_xscale
= 0;
326 /* Nonzero if this chip is an ARM6 or an ARM7. */
327 int arm_is_6_or_7
= 0;
329 /* Nonzero if this chip is a Cirrus/DSP. */
330 int arm_is_cirrus
= 0;
332 /* Nonzero if generating Thumb instructions. */
335 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
336 must report the mode of the memory reference from PRINT_OPERAND to
337 PRINT_OPERAND_ADDRESS. */
338 enum machine_mode output_memory_reference_mode
;
340 /* The register number to be used for the PIC offset register. */
341 const char * arm_pic_register_string
= NULL
;
342 int arm_pic_register
= INVALID_REGNUM
;
344 /* Set to 1 when a return insn is output, this means that the epilogue
346 int return_used_this_function
;
348 /* Set to 1 after arm_reorg has started. Reset to start at the start of
349 the next function. */
350 static int after_arm_reorg
= 0;
352 /* The maximum number of insns to be used when loading a constant. */
353 static int arm_constant_limit
= 3;
355 /* For an explanation of these variables, see final_prescan_insn below. */
357 enum arm_cond_code arm_current_cc
;
359 int arm_target_label
;
361 /* The condition codes of the ARM, and the inverse function. */
362 static const char * const arm_condition_codes
[] =
364 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
365 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
368 #define streq(string1, string2) (strcmp (string1, string2) == 0)
370 /* Initialization code. */
374 const char *const name
;
375 const unsigned long flags
;
378 /* Not all of these give usefully different compilation alternatives,
379 but there is no simple way of generalizing them. */
380 static const struct processors all_cores
[] =
384 {"arm2", FL_CO_PROC
| FL_MODE26
},
385 {"arm250", FL_CO_PROC
| FL_MODE26
},
386 {"arm3", FL_CO_PROC
| FL_MODE26
},
387 {"arm6", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
388 {"arm60", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
389 {"arm600", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
390 {"arm610", FL_MODE26
| FL_MODE32
},
391 {"arm620", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
392 {"arm7", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
393 /* arm7m doesn't exist on its own, but only with D, (and I), but
394 those don't alter the code, so arm7m is sometimes used. */
395 {"arm7m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
396 {"arm7d", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
397 {"arm7dm", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
398 {"arm7di", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
399 {"arm7dmi", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
400 {"arm70", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
401 {"arm700", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
402 {"arm700i", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
403 {"arm710", FL_MODE26
| FL_MODE32
},
404 {"arm710t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
405 {"arm720", FL_MODE26
| FL_MODE32
},
406 {"arm720t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
407 {"arm740t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
408 {"arm710c", FL_MODE26
| FL_MODE32
},
409 {"arm7100", FL_MODE26
| FL_MODE32
},
410 {"arm7500", FL_MODE26
| FL_MODE32
},
411 /* Doesn't have an external co-proc, but does have embedded fpa. */
412 {"arm7500fe", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
413 {"arm7tdmi", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
414 {"arm8", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
415 {"arm810", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
416 {"arm9", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
417 {"arm920", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
418 {"arm920t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
419 {"arm940t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
420 {"arm9tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
421 {"arm9e", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
422 {"ep9312", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_CIRRUS
},
423 {"strongarm", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
424 {"strongarm110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
425 {"strongarm1100", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
426 {"strongarm1110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
427 {"arm10tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_ARCH5
},
428 {"arm1020t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_ARCH5
},
429 {"xscale", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_STRONG
| FL_ARCH5
| FL_ARCH5E
| FL_XSCALE
},
430 {"iwmmxt", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_STRONG
| FL_ARCH5
| FL_ARCH5E
| FL_XSCALE
| FL_IWMMXT
},
435 static const struct processors all_architectures
[] =
437 /* ARM Architectures */
439 { "armv2", FL_CO_PROC
| FL_MODE26
},
440 { "armv2a", FL_CO_PROC
| FL_MODE26
},
441 { "armv3", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
442 { "armv3m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
443 { "armv4", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
},
444 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
445 implementations that support it, so we will leave it out for now. */
446 { "armv4t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
447 { "armv5", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
448 { "armv5t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
449 { "armv5te", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
| FL_ARCH5E
},
450 { "ep9312", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_CIRRUS
},
451 {"iwmmxt", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_STRONG
| FL_ARCH5
| FL_ARCH5E
| FL_XSCALE
| FL_IWMMXT
},
455 /* This is a magic stucture. The 'string' field is magically filled in
456 with a pointer to the value specified by the user on the command line
457 assuming that the user has specified such a value. */
459 struct arm_cpu_select arm_select
[] =
461 /* string name processors */
462 { NULL
, "-mcpu=", all_cores
},
463 { NULL
, "-march=", all_architectures
},
464 { NULL
, "-mtune=", all_cores
}
467 /* Return the number of bits set in VALUE. */
469 bit_count (unsigned long value
)
471 unsigned long count
= 0;
476 value
&= value
- 1; /* Clear the least-significant set bit. */
482 /* Fix up any incompatible options that the user has specified.
483 This has now turned into a maze. */
485 arm_override_options (void)
489 /* Set up the flags based on the cpu/architecture selected by the user. */
490 for (i
= ARRAY_SIZE (arm_select
); i
--;)
492 struct arm_cpu_select
* ptr
= arm_select
+ i
;
494 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
496 const struct processors
* sel
;
498 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
499 if (streq (ptr
->string
, sel
->name
))
502 tune_flags
= sel
->flags
;
505 /* If we have been given an architecture and a processor
506 make sure that they are compatible. We only generate
507 a warning though, and we prefer the CPU over the
509 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
510 warning ("switch -mcpu=%s conflicts with -march= switch",
513 insn_flags
= sel
->flags
;
519 if (sel
->name
== NULL
)
520 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
524 /* If the user did not specify a processor, choose one for them. */
527 const struct processors
* sel
;
529 static const struct cpu_default
532 const char *const name
;
536 { TARGET_CPU_arm2
, "arm2" },
537 { TARGET_CPU_arm6
, "arm6" },
538 { TARGET_CPU_arm610
, "arm610" },
539 { TARGET_CPU_arm710
, "arm710" },
540 { TARGET_CPU_arm7m
, "arm7m" },
541 { TARGET_CPU_arm7500fe
, "arm7500fe" },
542 { TARGET_CPU_arm7tdmi
, "arm7tdmi" },
543 { TARGET_CPU_arm8
, "arm8" },
544 { TARGET_CPU_arm810
, "arm810" },
545 { TARGET_CPU_arm9
, "arm9" },
546 { TARGET_CPU_strongarm
, "strongarm" },
547 { TARGET_CPU_xscale
, "xscale" },
548 { TARGET_CPU_ep9312
, "ep9312" },
549 { TARGET_CPU_iwmmxt
, "iwmmxt" },
550 { TARGET_CPU_generic
, "arm" },
553 const struct cpu_default
* def
;
555 /* Find the default. */
556 for (def
= cpu_defaults
; def
->name
; def
++)
557 if (def
->cpu
== TARGET_CPU_DEFAULT
)
560 /* Make sure we found the default CPU. */
561 if (def
->name
== NULL
)
564 /* Find the default CPU's flags. */
565 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
566 if (streq (def
->name
, sel
->name
))
569 if (sel
->name
== NULL
)
572 insn_flags
= sel
->flags
;
574 /* Now check to see if the user has specified some command line
575 switch that require certain abilities from the cpu. */
578 if (TARGET_INTERWORK
|| TARGET_THUMB
)
580 sought
|= (FL_THUMB
| FL_MODE32
);
582 /* Force apcs-32 to be used for interworking. */
583 target_flags
|= ARM_FLAG_APCS_32
;
585 /* There are no ARM processors that support both APCS-26 and
586 interworking. Therefore we force FL_MODE26 to be removed
587 from insn_flags here (if it was set), so that the search
588 below will always be able to find a compatible processor. */
589 insn_flags
&= ~FL_MODE26
;
591 else if (!TARGET_APCS_32
)
594 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
596 /* Try to locate a CPU type that supports all of the abilities
597 of the default CPU, plus the extra abilities requested by
599 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
600 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
603 if (sel
->name
== NULL
)
605 unsigned current_bit_count
= 0;
606 const struct processors
* best_fit
= NULL
;
608 /* Ideally we would like to issue an error message here
609 saying that it was not possible to find a CPU compatible
610 with the default CPU, but which also supports the command
611 line options specified by the programmer, and so they
612 ought to use the -mcpu=<name> command line option to
613 override the default CPU type.
615 Unfortunately this does not work with multilibing. We
616 need to be able to support multilibs for -mapcs-26 and for
617 -mthumb-interwork and there is no CPU that can support both
618 options. Instead if we cannot find a cpu that has both the
619 characteristics of the default cpu and the given command line
620 options we scan the array again looking for a best match. */
621 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
622 if ((sel
->flags
& sought
) == sought
)
626 count
= bit_count (sel
->flags
& insn_flags
);
628 if (count
>= current_bit_count
)
631 current_bit_count
= count
;
635 if (best_fit
== NULL
)
641 insn_flags
= sel
->flags
;
645 /* If tuning has not been specified, tune for whichever processor or
646 architecture has been selected. */
648 tune_flags
= insn_flags
;
650 /* Make sure that the processor choice does not conflict with any of the
651 other command line choices. */
652 if (TARGET_APCS_32
&& !(insn_flags
& FL_MODE32
))
654 /* If APCS-32 was not the default then it must have been set by the
655 user, so issue a warning message. If the user has specified
656 "-mapcs-32 -mcpu=arm2" then we loose here. */
657 if ((TARGET_DEFAULT
& ARM_FLAG_APCS_32
) == 0)
658 warning ("target CPU does not support APCS-32" );
659 target_flags
&= ~ARM_FLAG_APCS_32
;
661 else if (!TARGET_APCS_32
&& !(insn_flags
& FL_MODE26
))
663 warning ("target CPU does not support APCS-26" );
664 target_flags
|= ARM_FLAG_APCS_32
;
667 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
669 warning ("target CPU does not support interworking" );
670 target_flags
&= ~ARM_FLAG_INTERWORK
;
673 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
675 warning ("target CPU does not support THUMB instructions");
676 target_flags
&= ~ARM_FLAG_THUMB
;
679 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
681 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
682 target_flags
&= ~ARM_FLAG_APCS_FRAME
;
685 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
686 from here where no function is being compiled currently. */
687 if ((target_flags
& (THUMB_FLAG_LEAF_BACKTRACE
| THUMB_FLAG_BACKTRACE
))
689 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
691 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
692 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
694 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
695 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
697 /* If interworking is enabled then APCS-32 must be selected as well. */
698 if (TARGET_INTERWORK
)
701 warning ("interworking forces APCS-32 to be used" );
702 target_flags
|= ARM_FLAG_APCS_32
;
705 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
707 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
708 target_flags
|= ARM_FLAG_APCS_FRAME
;
711 if (TARGET_POKE_FUNCTION_NAME
)
712 target_flags
|= ARM_FLAG_APCS_FRAME
;
714 if (TARGET_APCS_REENT
&& flag_pic
)
715 error ("-fpic and -mapcs-reent are incompatible");
717 if (TARGET_APCS_REENT
)
718 warning ("APCS reentrant code not supported. Ignored");
720 /* If this target is normally configured to use APCS frames, warn if they
721 are turned off and debugging is turned on. */
723 && write_symbols
!= NO_DEBUG
724 && !TARGET_APCS_FRAME
725 && (TARGET_DEFAULT
& ARM_FLAG_APCS_FRAME
))
726 warning ("-g with -mno-apcs-frame may not give sensible debugging");
728 /* If stack checking is disabled, we can use r10 as the PIC register,
729 which keeps r9 available. */
731 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
733 if (TARGET_APCS_FLOAT
)
734 warning ("passing floating point arguments in fp regs not yet supported");
736 /* Initialize boolean versions of the flags, for use in the arm.md file. */
737 arm_fast_multiply
= (insn_flags
& FL_FAST_MULT
) != 0;
738 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
739 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
740 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
741 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
743 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
744 arm_is_strong
= (tune_flags
& FL_STRONG
) != 0;
745 thumb_code
= (TARGET_ARM
== 0);
746 arm_is_6_or_7
= (((tune_flags
& (FL_MODE26
| FL_MODE32
))
747 && !(tune_flags
& FL_ARCH4
))) != 0;
748 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
749 arm_is_cirrus
= (tune_flags
& FL_CIRRUS
) != 0;
750 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
752 if (TARGET_IWMMXT
&& (! TARGET_ATPCS
))
753 target_flags
|= ARM_FLAG_ATPCS
;
757 arm_fpu_tune
= FPUTYPE_MAVERICK
;
759 /* Ignore -mhard-float if -mcpu=ep9312. */
760 if (TARGET_HARD_FLOAT
)
761 target_flags
^= ARM_FLAG_SOFT_FLOAT
;
764 /* Default value for floating point code... if no co-processor
765 bus, then schedule for emulated floating point. Otherwise,
766 assume the user has an FPA.
767 Note: this does not prevent use of floating point instructions,
768 -msoft-float does that. */
769 arm_fpu_tune
= (tune_flags
& FL_CO_PROC
) ? FPUTYPE_FPA
: FPUTYPE_FPA_EMU3
;
773 if (streq (target_fp_name
, "2"))
774 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
775 else if (streq (target_fp_name
, "3"))
776 arm_fpu_arch
= FPUTYPE_FPA_EMU3
;
778 error ("invalid floating point emulation option: -mfpe-%s",
782 arm_fpu_arch
= FPUTYPE_DEFAULT
;
786 if (arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
787 arm_fpu_tune
= FPUTYPE_FPA_EMU2
;
788 else if (arm_fpu_tune
== FPUTYPE_MAVERICK
)
789 warning ("-mfpe switch not supported by ep9312 target cpu - ignored.");
790 else if (arm_fpu_tune
!= FPUTYPE_FPA
)
791 arm_fpu_tune
= FPUTYPE_FPA_EMU2
;
794 /* For arm2/3 there is no need to do any scheduling if there is only
795 a floating point emulator, or we are doing software floating-point. */
796 if ((TARGET_SOFT_FLOAT
|| arm_fpu_tune
!= FPUTYPE_FPA
)
797 && (tune_flags
& FL_MODE32
) == 0)
798 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
800 arm_prgmode
= TARGET_APCS_32
? PROG_MODE_PROG32
: PROG_MODE_PROG26
;
802 if (structure_size_string
!= NULL
)
804 int size
= strtol (structure_size_string
, NULL
, 0);
806 if (size
== 8 || size
== 32)
807 arm_structure_size_boundary
= size
;
809 warning ("structure size boundary can only be set to 8 or 32");
812 if (arm_pic_register_string
!= NULL
)
814 int pic_register
= decode_reg_name (arm_pic_register_string
);
817 warning ("-mpic-register= is useless without -fpic");
819 /* Prevent the user from choosing an obviously stupid PIC register. */
820 else if (pic_register
< 0 || call_used_regs
[pic_register
]
821 || pic_register
== HARD_FRAME_POINTER_REGNUM
822 || pic_register
== STACK_POINTER_REGNUM
823 || pic_register
>= PC_REGNUM
)
824 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
826 arm_pic_register
= pic_register
;
829 if (TARGET_THUMB
&& flag_schedule_insns
)
831 /* Don't warn since it's on by default in -O2. */
832 flag_schedule_insns
= 0;
835 /* If optimizing for space, don't synthesize constants.
836 For processors with load scheduling, it never costs more than 2 cycles
837 to load a constant, and the load scheduler may well reduce that to 1. */
838 if (optimize_size
|| (tune_flags
& FL_LDSCHED
))
839 arm_constant_limit
= 1;
842 arm_constant_limit
= 2;
844 /* If optimizing for size, bump the number of instructions that we
845 are prepared to conditionally execute (even on a StrongARM).
846 Otherwise for the StrongARM, which has early execution of branches,
847 a sequence that is worth skipping is shorter. */
849 max_insns_skipped
= 6;
850 else if (arm_is_strong
)
851 max_insns_skipped
= 3;
853 /* Register global variables with the garbage collector. */
858 arm_add_gc_roots (void)
860 gcc_obstack_init(&minipool_obstack
);
861 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
864 /* A table of known ARM exception types.
865 For use with the interrupt function attribute. */
869 const char *const arg
;
870 const unsigned long return_value
;
874 static const isr_attribute_arg isr_attribute_args
[] =
876 { "IRQ", ARM_FT_ISR
},
877 { "irq", ARM_FT_ISR
},
878 { "FIQ", ARM_FT_FIQ
},
879 { "fiq", ARM_FT_FIQ
},
880 { "ABORT", ARM_FT_ISR
},
881 { "abort", ARM_FT_ISR
},
882 { "ABORT", ARM_FT_ISR
},
883 { "abort", ARM_FT_ISR
},
884 { "UNDEF", ARM_FT_EXCEPTION
},
885 { "undef", ARM_FT_EXCEPTION
},
886 { "SWI", ARM_FT_EXCEPTION
},
887 { "swi", ARM_FT_EXCEPTION
},
888 { NULL
, ARM_FT_NORMAL
}
891 /* Returns the (interrupt) function type of the current
892 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
895 arm_isr_value (tree argument
)
897 const isr_attribute_arg
* ptr
;
900 /* No argument - default to IRQ. */
901 if (argument
== NULL_TREE
)
904 /* Get the value of the argument. */
905 if (TREE_VALUE (argument
) == NULL_TREE
906 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
907 return ARM_FT_UNKNOWN
;
909 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
911 /* Check it against the list of known arguments. */
912 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
913 if (streq (arg
, ptr
->arg
))
914 return ptr
->return_value
;
916 /* An unrecognized interrupt type. */
917 return ARM_FT_UNKNOWN
;
920 /* Computes the type of the current function. */
923 arm_compute_func_type (void)
925 unsigned long type
= ARM_FT_UNKNOWN
;
929 if (TREE_CODE (current_function_decl
) != FUNCTION_DECL
)
932 /* Decide if the current function is volatile. Such functions
933 never return, and many memory cycles can be saved by not storing
934 register values that will never be needed again. This optimization
935 was added to speed up context switching in a kernel application. */
937 && current_function_nothrow
938 && TREE_THIS_VOLATILE (current_function_decl
))
939 type
|= ARM_FT_VOLATILE
;
941 if (current_function_needs_context
)
942 type
|= ARM_FT_NESTED
;
944 attr
= DECL_ATTRIBUTES (current_function_decl
);
946 a
= lookup_attribute ("naked", attr
);
948 type
|= ARM_FT_NAKED
;
950 if (cfun
->machine
->eh_epilogue_sp_ofs
!= NULL_RTX
)
951 type
|= ARM_FT_EXCEPTION_HANDLER
;
954 a
= lookup_attribute ("isr", attr
);
956 a
= lookup_attribute ("interrupt", attr
);
959 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
961 type
|= arm_isr_value (TREE_VALUE (a
));
967 /* Returns the type of the current function. */
970 arm_current_func_type (void)
972 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
973 cfun
->machine
->func_type
= arm_compute_func_type ();
975 return cfun
->machine
->func_type
;
978 /* Return 1 if it is possible to return using a single instruction. */
981 use_return_insn (int iscond
)
984 unsigned int func_type
;
985 unsigned long saved_int_regs
;
987 /* Never use a return instruction before reload has run. */
988 if (!reload_completed
)
991 func_type
= arm_current_func_type ();
993 /* Naked functions and volatile functions need special
995 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
998 /* So do interrupt functions that use the frame pointer. */
999 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1002 /* As do variadic functions. */
1003 if (current_function_pretend_args_size
1004 || cfun
->machine
->uses_anonymous_args
1005 /* Of if the function calls __builtin_eh_return () */
1006 || ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
1007 /* Or if there is no frame pointer and there is a stack adjustment. */
1008 || ((arm_get_frame_size () + current_function_outgoing_args_size
!= 0)
1009 && !frame_pointer_needed
))
1012 saved_int_regs
= arm_compute_save_reg_mask ();
1014 /* Can't be done if interworking with Thumb, and any registers have been
1016 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1019 /* On StrongARM, conditional returns are expensive if they aren't
1020 taken and multiple registers have been stacked. */
1021 if (iscond
&& arm_is_strong
)
1023 /* Conditional return when just the LR is stored is a simple
1024 conditional-load instruction, that's not expensive. */
1025 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1028 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1032 /* If there are saved registers but the LR isn't saved, then we need
1033 two instructions for the return. */
1034 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1037 /* Can't be done if any of the FPA regs are pushed,
1038 since this also requires an insn. */
1039 if (TARGET_HARD_FLOAT
)
1040 for (regno
= FIRST_ARM_FP_REGNUM
; regno
<= LAST_ARM_FP_REGNUM
; regno
++)
1041 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1044 if (TARGET_REALLY_IWMMXT
)
1045 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1046 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1052 /* Return TRUE if int I is a valid immediate ARM constant. */
1055 const_ok_for_arm (HOST_WIDE_INT i
)
1057 unsigned HOST_WIDE_INT mask
= ~(unsigned HOST_WIDE_INT
)0xFF;
1059 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1060 be all zero, or all one. */
1061 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1062 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1063 != ((~(unsigned HOST_WIDE_INT
) 0)
1064 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1067 /* Fast return for 0 and powers of 2 */
1068 if ((i
& (i
- 1)) == 0)
1073 if ((i
& mask
& (unsigned HOST_WIDE_INT
) 0xffffffff) == 0)
1076 (mask
<< 2) | ((mask
& (unsigned HOST_WIDE_INT
) 0xffffffff)
1077 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT
) 0xffffffff;
1079 while (mask
!= ~(unsigned HOST_WIDE_INT
) 0xFF);
1084 /* Return true if I is a valid constant for the operation CODE. */
1086 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1088 if (const_ok_for_arm (i
))
1094 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1096 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1102 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1109 /* Emit a sequence of insns to handle a large constant.
1110 CODE is the code of the operation required, it can be any of SET, PLUS,
1111 IOR, AND, XOR, MINUS;
1112 MODE is the mode in which the operation is being performed;
1113 VAL is the integer to operate on;
1114 SOURCE is the other operand (a register, or a null-pointer for SET);
1115 SUBTARGETS means it is safe to create scratch registers if that will
1116 either produce a simpler sequence, or we will want to cse the values.
1117 Return value is the number of insns emitted. */
1120 arm_split_constant (enum rtx_code code
, enum machine_mode mode
,
1121 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1123 if (subtargets
|| code
== SET
1124 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1125 && REGNO (target
) != REGNO (source
)))
1127 /* After arm_reorg has been called, we can't fix up expensive
1128 constants by pushing them into memory so we must synthesize
1129 them in-line, regardless of the cost. This is only likely to
1130 be more costly on chips that have load delay slots and we are
1131 compiling without running the scheduler (so no splitting
1132 occurred before the final instruction emission).
1134 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1136 if (!after_arm_reorg
1137 && (arm_gen_constant (code
, mode
, val
, target
, source
, 1, 0)
1138 > arm_constant_limit
+ (code
!= SET
)))
1142 /* Currently SET is the only monadic value for CODE, all
1143 the rest are diadic. */
1144 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1149 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1151 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1152 /* For MINUS, the value is subtracted from, since we never
1153 have subtraction of a constant. */
1155 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1156 gen_rtx_MINUS (mode
, temp
, source
)));
1158 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1159 gen_rtx (code
, mode
, source
, temp
)));
1165 return arm_gen_constant (code
, mode
, val
, target
, source
, subtargets
, 1);
1169 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1171 HOST_WIDE_INT temp1
;
1179 if (remainder
& (3 << (i
- 2)))
1184 temp1
= remainder
& ((0x0ff << end
)
1185 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1186 remainder
&= ~temp1
;
1191 } while (remainder
);
1195 /* As above, but extra parameter GENERATE which, if clear, suppresses
1199 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
,
1200 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1205 int can_negate_initial
= 0;
1208 int num_bits_set
= 0;
1209 int set_sign_bit_copies
= 0;
1210 int clear_sign_bit_copies
= 0;
1211 int clear_zero_bit_copies
= 0;
1212 int set_zero_bit_copies
= 0;
1214 unsigned HOST_WIDE_INT temp1
, temp2
;
1215 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1217 /* Find out which operations are safe for a given CODE. Also do a quick
1218 check for degenerate cases; these can occur when DImode operations
1230 can_negate_initial
= 1;
1234 if (remainder
== 0xffffffff)
1237 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1238 GEN_INT (ARM_SIGN_EXTEND (val
))));
1243 if (reload_completed
&& rtx_equal_p (target
, source
))
1246 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1255 emit_insn (gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1258 if (remainder
== 0xffffffff)
1260 if (reload_completed
&& rtx_equal_p (target
, source
))
1263 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1272 if (reload_completed
&& rtx_equal_p (target
, source
))
1275 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1278 if (remainder
== 0xffffffff)
1281 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1282 gen_rtx_NOT (mode
, source
)));
1286 /* We don't know how to handle this yet below. */
1290 /* We treat MINUS as (val - source), since (source - val) is always
1291 passed as (source + (-val)). */
1295 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1296 gen_rtx_NEG (mode
, source
)));
1299 if (const_ok_for_arm (val
))
1302 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1303 gen_rtx_MINUS (mode
, GEN_INT (val
),
1315 /* If we can do it in one insn get out quickly. */
1316 if (const_ok_for_arm (val
)
1317 || (can_negate_initial
&& const_ok_for_arm (-val
))
1318 || (can_invert
&& const_ok_for_arm (~val
)))
1321 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1322 (source
? gen_rtx (code
, mode
, source
,
1328 /* Calculate a few attributes that may be useful for specific
1330 for (i
= 31; i
>= 0; i
--)
1332 if ((remainder
& (1 << i
)) == 0)
1333 clear_sign_bit_copies
++;
1338 for (i
= 31; i
>= 0; i
--)
1340 if ((remainder
& (1 << i
)) != 0)
1341 set_sign_bit_copies
++;
1346 for (i
= 0; i
<= 31; i
++)
1348 if ((remainder
& (1 << i
)) == 0)
1349 clear_zero_bit_copies
++;
1354 for (i
= 0; i
<= 31; i
++)
1356 if ((remainder
& (1 << i
)) != 0)
1357 set_zero_bit_copies
++;
1365 /* See if we can do this by sign_extending a constant that is known
1366 to be negative. This is a good, way of doing it, since the shift
1367 may well merge into a subsequent insn. */
1368 if (set_sign_bit_copies
> 1)
1370 if (const_ok_for_arm
1371 (temp1
= ARM_SIGN_EXTEND (remainder
1372 << (set_sign_bit_copies
- 1))))
1376 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1377 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
1379 emit_insn (gen_ashrsi3 (target
, new_src
,
1380 GEN_INT (set_sign_bit_copies
- 1)));
1384 /* For an inverted constant, we will need to set the low bits,
1385 these will be shifted out of harm's way. */
1386 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1387 if (const_ok_for_arm (~temp1
))
1391 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1392 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
1394 emit_insn (gen_ashrsi3 (target
, new_src
,
1395 GEN_INT (set_sign_bit_copies
- 1)));
1401 /* See if we can generate this by setting the bottom (or the top)
1402 16 bits, and then shifting these into the other half of the
1403 word. We only look for the simplest cases, to do more would cost
1404 too much. Be careful, however, not to generate this when the
1405 alternative would take fewer insns. */
1406 if (val
& 0xffff0000)
1408 temp1
= remainder
& 0xffff0000;
1409 temp2
= remainder
& 0x0000ffff;
1411 /* Overlaps outside this range are best done using other methods. */
1412 for (i
= 9; i
< 24; i
++)
1414 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
1415 && !const_ok_for_arm (temp2
))
1417 rtx new_src
= (subtargets
1418 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1420 insns
= arm_gen_constant (code
, mode
, temp2
, new_src
,
1421 source
, subtargets
, generate
);
1424 emit_insn (gen_rtx_SET
1427 gen_rtx_ASHIFT (mode
, source
,
1434 /* Don't duplicate cases already considered. */
1435 for (i
= 17; i
< 24; i
++)
1437 if (((temp1
| (temp1
>> i
)) == remainder
)
1438 && !const_ok_for_arm (temp1
))
1440 rtx new_src
= (subtargets
1441 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1443 insns
= arm_gen_constant (code
, mode
, temp1
, new_src
,
1444 source
, subtargets
, generate
);
1448 (gen_rtx_SET (VOIDmode
, target
,
1451 gen_rtx_LSHIFTRT (mode
, source
,
1462 /* If we have IOR or XOR, and the constant can be loaded in a
1463 single instruction, and we can find a temporary to put it in,
1464 then this can be done in two instructions instead of 3-4. */
1466 /* TARGET can't be NULL if SUBTARGETS is 0 */
1467 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
1469 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
1473 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1475 emit_insn (gen_rtx_SET (VOIDmode
, sub
, GEN_INT (val
)));
1476 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1477 gen_rtx (code
, mode
, source
, sub
)));
1486 if (set_sign_bit_copies
> 8
1487 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
1491 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1492 rtx shift
= GEN_INT (set_sign_bit_copies
);
1494 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1496 gen_rtx_ASHIFT (mode
,
1499 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1501 gen_rtx_LSHIFTRT (mode
, sub
,
1507 if (set_zero_bit_copies
> 8
1508 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
1512 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1513 rtx shift
= GEN_INT (set_zero_bit_copies
);
1515 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1517 gen_rtx_LSHIFTRT (mode
,
1520 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1522 gen_rtx_ASHIFT (mode
, sub
,
1528 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
1532 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1533 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1534 gen_rtx_NOT (mode
, source
)));
1537 sub
= gen_reg_rtx (mode
);
1538 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1539 gen_rtx_AND (mode
, source
,
1541 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1542 gen_rtx_NOT (mode
, sub
)));
1549 /* See if two shifts will do 2 or more insn's worth of work. */
1550 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
1552 HOST_WIDE_INT shift_mask
= ((0xffffffff
1553 << (32 - clear_sign_bit_copies
))
1556 if ((remainder
| shift_mask
) != 0xffffffff)
1560 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1561 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1562 new_src
, source
, subtargets
, 1);
1567 rtx targ
= subtargets
? NULL_RTX
: target
;
1568 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1569 targ
, source
, subtargets
, 0);
1575 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1576 rtx shift
= GEN_INT (clear_sign_bit_copies
);
1578 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
1579 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
1585 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
1587 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
1589 if ((remainder
| shift_mask
) != 0xffffffff)
1593 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1595 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1596 new_src
, source
, subtargets
, 1);
1601 rtx targ
= subtargets
? NULL_RTX
: target
;
1603 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1604 targ
, source
, subtargets
, 0);
1610 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1611 rtx shift
= GEN_INT (clear_zero_bit_copies
);
1613 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
1614 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
1626 for (i
= 0; i
< 32; i
++)
1627 if (remainder
& (1 << i
))
1630 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
1631 remainder
= (~remainder
) & 0xffffffff;
1632 else if (code
== PLUS
&& num_bits_set
> 16)
1633 remainder
= (-remainder
) & 0xffffffff;
1640 /* Now try and find a way of doing the job in either two or three
1642 We start by looking for the largest block of zeros that are aligned on
1643 a 2-bit boundary, we then fill up the temps, wrapping around to the
1644 top of the word when we drop off the bottom.
1645 In the worst case this code should produce no more than four insns. */
1648 int best_consecutive_zeros
= 0;
1650 for (i
= 0; i
< 32; i
+= 2)
1652 int consecutive_zeros
= 0;
1654 if (!(remainder
& (3 << i
)))
1656 while ((i
< 32) && !(remainder
& (3 << i
)))
1658 consecutive_zeros
+= 2;
1661 if (consecutive_zeros
> best_consecutive_zeros
)
1663 best_consecutive_zeros
= consecutive_zeros
;
1664 best_start
= i
- consecutive_zeros
;
1670 /* So long as it won't require any more insns to do so, it's
1671 desirable to emit a small constant (in bits 0...9) in the last
1672 insn. This way there is more chance that it can be combined with
1673 a later addressing insn to form a pre-indexed load or store
1674 operation. Consider:
1676 *((volatile int *)0xe0000100) = 1;
1677 *((volatile int *)0xe0000110) = 2;
1679 We want this to wind up as:
1683 str rB, [rA, #0x100]
1685 str rB, [rA, #0x110]
1687 rather than having to synthesize both large constants from scratch.
1689 Therefore, we calculate how many insns would be required to emit
1690 the constant starting from `best_start', and also starting from
1691 zero (ie with bit 31 first to be output). If `best_start' doesn't
1692 yield a shorter sequence, we may as well use zero. */
1694 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
1695 && (count_insns_for_constant (remainder
, 0) <=
1696 count_insns_for_constant (remainder
, best_start
)))
1699 /* Now start emitting the insns. */
1707 if (remainder
& (3 << (i
- 2)))
1712 temp1
= remainder
& ((0x0ff << end
)
1713 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1714 remainder
&= ~temp1
;
1718 rtx new_src
, temp1_rtx
;
1720 if (code
== SET
|| code
== MINUS
)
1722 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
1723 if (can_invert
&& code
!= MINUS
)
1728 if (remainder
&& subtargets
)
1729 new_src
= gen_reg_rtx (mode
);
1734 else if (can_negate
)
1738 temp1
= trunc_int_for_mode (temp1
, mode
);
1739 temp1_rtx
= GEN_INT (temp1
);
1743 else if (code
== MINUS
)
1744 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
1746 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
1748 emit_insn (gen_rtx_SET (VOIDmode
, new_src
, temp1_rtx
));
1757 else if (code
== MINUS
)
1771 /* Canonicalize a comparison so that we are more likely to recognize it.
1772 This can be done for a few constant compares, where we can make the
1773 immediate value easier to load. */
1776 arm_canonicalize_comparison (enum rtx_code code
, rtx
* op1
)
1778 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
1788 if (i
!= ((((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1)) - 1)
1789 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
1791 *op1
= GEN_INT (i
+ 1);
1792 return code
== GT
? GE
: LT
;
1798 if (i
!= (((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1))
1799 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
1801 *op1
= GEN_INT (i
- 1);
1802 return code
== GE
? GT
: LE
;
1808 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
1809 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
1811 *op1
= GEN_INT (i
+ 1);
1812 return code
== GTU
? GEU
: LTU
;
1819 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
1821 *op1
= GEN_INT (i
- 1);
1822 return code
== GEU
? GTU
: LEU
;
1833 /* Decide whether a type should be returned in memory (true)
1834 or in a register (false). This is called by the macro
1835 RETURN_IN_MEMORY. */
1837 arm_return_in_memory (tree type
)
1841 if (!AGGREGATE_TYPE_P (type
))
1842 /* All simple types are returned in registers. */
1845 size
= int_size_in_bytes (type
);
1849 /* ATPCS returns aggregate types in memory only if they are
1850 larger than a word (or are variable size). */
1851 return (size
< 0 || size
> UNITS_PER_WORD
);
1854 /* For the arm-wince targets we choose to be compatible with Microsoft's
1855 ARM and Thumb compilers, which always return aggregates in memory. */
1857 /* All structures/unions bigger than one word are returned in memory.
1858 Also catch the case where int_size_in_bytes returns -1. In this case
1859 the aggregate is either huge or of variable size, and in either case
1860 we will want to return it via memory and not in a register. */
1861 if (size
< 0 || size
> UNITS_PER_WORD
)
1864 if (TREE_CODE (type
) == RECORD_TYPE
)
1868 /* For a struct the APCS says that we only return in a register
1869 if the type is 'integer like' and every addressable element
1870 has an offset of zero. For practical purposes this means
1871 that the structure can have at most one non bit-field element
1872 and that this element must be the first one in the structure. */
1874 /* Find the first field, ignoring non FIELD_DECL things which will
1875 have been created by C++. */
1876 for (field
= TYPE_FIELDS (type
);
1877 field
&& TREE_CODE (field
) != FIELD_DECL
;
1878 field
= TREE_CHAIN (field
))
1882 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1884 /* Check that the first field is valid for returning in a register. */
1886 /* ... Floats are not allowed */
1887 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1890 /* ... Aggregates that are not themselves valid for returning in
1891 a register are not allowed. */
1892 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1895 /* Now check the remaining fields, if any. Only bitfields are allowed,
1896 since they are not addressable. */
1897 for (field
= TREE_CHAIN (field
);
1899 field
= TREE_CHAIN (field
))
1901 if (TREE_CODE (field
) != FIELD_DECL
)
1904 if (!DECL_BIT_FIELD_TYPE (field
))
1911 if (TREE_CODE (type
) == UNION_TYPE
)
1915 /* Unions can be returned in registers if every element is
1916 integral, or can be returned in an integer register. */
1917 for (field
= TYPE_FIELDS (type
);
1919 field
= TREE_CHAIN (field
))
1921 if (TREE_CODE (field
) != FIELD_DECL
)
1924 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1927 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1933 #endif /* not ARM_WINCE */
1935 /* Return all other types in memory. */
1939 /* Indicate whether or not words of a double are in big-endian order. */
1942 arm_float_words_big_endian (void)
1947 /* For FPA, float words are always big-endian. For VFP, floats words
1948 follow the memory system mode. */
1950 if (TARGET_HARD_FLOAT
)
1952 /* FIXME: TARGET_HARD_FLOAT currently implies FPA. */
1957 return (TARGET_BIG_END
? 1 : 0);
1962 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1963 for a call to a function whose data type is FNTYPE.
1964 For a library call, FNTYPE is NULL. */
1966 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
1967 rtx libname ATTRIBUTE_UNUSED
,
1968 tree fndecl ATTRIBUTE_UNUSED
)
1970 /* On the ARM, the offset starts at 0. */
1971 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
))) ? 1 : 0);
1972 pcum
->iwmmxt_nregs
= 0;
1974 pcum
->call_cookie
= CALL_NORMAL
;
1976 if (TARGET_LONG_CALLS
)
1977 pcum
->call_cookie
= CALL_LONG
;
1979 /* Check for long call/short call attributes. The attributes
1980 override any command line option. */
1983 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
1984 pcum
->call_cookie
= CALL_SHORT
;
1985 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
1986 pcum
->call_cookie
= CALL_LONG
;
1989 /* Varargs vectors are treated the same as long long.
1990 named_count avoids having to change the way arm handles 'named' */
1991 pcum
->named_count
= 0;
1994 if (TARGET_REALLY_IWMMXT
&& fntype
)
1998 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2000 fn_arg
= TREE_CHAIN (fn_arg
))
2001 pcum
->named_count
+= 1;
2003 if (! pcum
->named_count
)
2004 pcum
->named_count
= INT_MAX
;
2008 /* Determine where to put an argument to a function.
2009 Value is zero to push the argument on the stack,
2010 or a hard register in which to store the argument.
2012 MODE is the argument's machine mode.
2013 TYPE is the data type of the argument (as a tree).
2014 This is null for libcalls where that information may
2016 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2017 the preceding args and about the function being called.
2018 NAMED is nonzero if this argument is a named parameter
2019 (otherwise it is an extra parameter matching an ellipsis). */
2022 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2023 tree type ATTRIBUTE_UNUSED
, int named
)
2025 if (TARGET_REALLY_IWMMXT
)
2027 if (VECTOR_MODE_SUPPORTED_P (mode
))
2029 /* varargs vectors are treated the same as long long.
2030 named_count avoids having to change the way arm handles 'named' */
2031 if (pcum
->named_count
<= pcum
->nargs
+ 1)
2033 if (pcum
->nregs
== 1)
2035 if (pcum
->nregs
<= 2)
2036 return gen_rtx_REG (mode
, pcum
->nregs
);
2040 else if (pcum
->iwmmxt_nregs
<= 9)
2041 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2045 else if ((mode
== DImode
|| mode
== DFmode
) && pcum
->nregs
& 1)
2049 if (mode
== VOIDmode
)
2050 /* Compute operand 2 of the call insn. */
2051 return GEN_INT (pcum
->call_cookie
);
2053 if (!named
|| pcum
->nregs
>= NUM_ARG_REGS
)
2056 return gen_rtx_REG (mode
, pcum
->nregs
);
2059 /* Variable sized types are passed by reference. This is a GCC
2060 extension to the ARM ABI. */
2063 arm_function_arg_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2064 enum machine_mode mode ATTRIBUTE_UNUSED
,
2065 tree type
, int named ATTRIBUTE_UNUSED
)
2067 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2070 /* Implement va_arg. */
2073 arm_va_arg (tree valist
, tree type
)
2075 /* Variable sized types are passed by reference. */
2076 if (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
2078 rtx addr
= std_expand_builtin_va_arg (valist
, build_pointer_type (type
));
2079 return gen_rtx_MEM (ptr_mode
, force_reg (Pmode
, addr
));
2082 if (FUNCTION_ARG_BOUNDARY (TYPE_MODE (type
), NULL
) == IWMMXT_ALIGNMENT
)
2087 /* Maintain 64-bit alignment of the valist pointer by
2088 contructing: valist = ((valist + (8 - 1)) & -8). */
2089 minus_eight
= build_int_2 (- (IWMMXT_ALIGNMENT
/ BITS_PER_UNIT
), -1);
2090 t
= build_int_2 ((IWMMXT_ALIGNMENT
/ BITS_PER_UNIT
) - 1, 0);
2091 t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
, t
);
2092 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
, minus_eight
);
2093 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
2094 TREE_SIDE_EFFECTS (t
) = 1;
2095 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2097 /* This is to stop the combine pass optimizing
2098 away the alignment adjustment. */
2099 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
2102 return std_expand_builtin_va_arg (valist
, type
);
2105 /* Encode the current state of the #pragma [no_]long_calls. */
2108 OFF
, /* No #pramgma [no_]long_calls is in effect. */
2109 LONG
, /* #pragma long_calls is in effect. */
2110 SHORT
/* #pragma no_long_calls is in effect. */
2113 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2116 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2118 arm_pragma_long_calls
= LONG
;
2122 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2124 arm_pragma_long_calls
= SHORT
;
2128 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2130 arm_pragma_long_calls
= OFF
;
2133 /* Table of machine attributes. */
2134 const struct attribute_spec arm_attribute_table
[] =
2136 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2137 /* Function calls made to this symbol must be done indirectly, because
2138 it may lie outside of the 26 bit addressing range of a normal function
2140 { "long_call", 0, 0, false, true, true, NULL
},
2141 /* Whereas these functions are always known to reside within the 26 bit
2142 addressing range. */
2143 { "short_call", 0, 0, false, true, true, NULL
},
2144 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2145 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2146 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2147 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2149 /* ARM/PE has three new attributes:
2151 dllexport - for exporting a function/variable that will live in a dll
2152 dllimport - for importing a function/variable from a dll
2154 Microsoft allows multiple declspecs in one __declspec, separating
2155 them with spaces. We do NOT support this. Instead, use __declspec
2158 { "dllimport", 0, 0, true, false, false, NULL
},
2159 { "dllexport", 0, 0, true, false, false, NULL
},
2160 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2162 { NULL
, 0, 0, false, false, false, NULL
}
2165 /* Handle an attribute requiring a FUNCTION_DECL;
2166 arguments as in struct attribute_spec.handler. */
2168 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2169 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2171 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2173 warning ("`%s' attribute only applies to functions",
2174 IDENTIFIER_POINTER (name
));
2175 *no_add_attrs
= true;
2181 /* Handle an "interrupt" or "isr" attribute;
2182 arguments as in struct attribute_spec.handler. */
2184 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
2189 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2191 warning ("`%s' attribute only applies to functions",
2192 IDENTIFIER_POINTER (name
));
2193 *no_add_attrs
= true;
2195 /* FIXME: the argument if any is checked for type attributes;
2196 should it be checked for decl ones? */
2200 if (TREE_CODE (*node
) == FUNCTION_TYPE
2201 || TREE_CODE (*node
) == METHOD_TYPE
)
2203 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2205 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2206 *no_add_attrs
= true;
2209 else if (TREE_CODE (*node
) == POINTER_TYPE
2210 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2211 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2212 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2214 *node
= build_type_copy (*node
);
2215 TREE_TYPE (*node
) = build_type_attribute_variant
2217 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2218 *no_add_attrs
= true;
2222 /* Possibly pass this attribute on from the type to a decl. */
2223 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2224 | (int) ATTR_FLAG_FUNCTION_NEXT
2225 | (int) ATTR_FLAG_ARRAY_NEXT
))
2227 *no_add_attrs
= true;
2228 return tree_cons (name
, args
, NULL_TREE
);
2232 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2240 /* Return 0 if the attributes for two types are incompatible, 1 if they
2241 are compatible, and 2 if they are nearly compatible (which causes a
2242 warning to be generated). */
2244 arm_comp_type_attributes (tree type1
, tree type2
)
2248 /* Check for mismatch of non-default calling convention. */
2249 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2252 /* Check for mismatched call attributes. */
2253 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2254 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2255 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2256 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2258 /* Only bother to check if an attribute is defined. */
2259 if (l1
| l2
| s1
| s2
)
2261 /* If one type has an attribute, the other must have the same attribute. */
2262 if ((l1
!= l2
) || (s1
!= s2
))
2265 /* Disallow mixed attributes. */
2266 if ((l1
& s2
) || (l2
& s1
))
2270 /* Check for mismatched ISR attribute. */
2271 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2273 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2274 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2276 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2283 /* Encode long_call or short_call attribute by prefixing
2284 symbol name in DECL with a special character FLAG. */
2286 arm_encode_call_attribute (tree decl
, int flag
)
2288 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2289 int len
= strlen (str
);
2292 /* Do not allow weak functions to be treated as short call. */
2293 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
2296 newstr
= alloca (len
+ 2);
2298 strcpy (newstr
+ 1, str
);
2300 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
2301 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2304 /* Assigns default attributes to newly defined type. This is used to
2305 set short_call/long_call attributes for function types of
2306 functions defined inside corresponding #pragma scopes. */
2308 arm_set_default_type_attributes (tree type
)
2310 /* Add __attribute__ ((long_call)) to all functions, when
2311 inside #pragma long_calls or __attribute__ ((short_call)),
2312 when inside #pragma no_long_calls. */
2313 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
2315 tree type_attr_list
, attr_name
;
2316 type_attr_list
= TYPE_ATTRIBUTES (type
);
2318 if (arm_pragma_long_calls
== LONG
)
2319 attr_name
= get_identifier ("long_call");
2320 else if (arm_pragma_long_calls
== SHORT
)
2321 attr_name
= get_identifier ("short_call");
2325 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
2326 TYPE_ATTRIBUTES (type
) = type_attr_list
;
2330 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2331 defined within the current compilation unit. If this cannot be
2332 determined, then 0 is returned. */
2334 current_file_function_operand (rtx sym_ref
)
2336 /* This is a bit of a fib. A function will have a short call flag
2337 applied to its name if it has the short call attribute, or it has
2338 already been defined within the current compilation unit. */
2339 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
2342 /* The current function is always defined within the current compilation
2343 unit. if it s a weak definition however, then this may not be the real
2344 definition of the function, and so we have to say no. */
2345 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
2346 && !DECL_WEAK (current_function_decl
))
2349 /* We cannot make the determination - default to returning 0. */
2353 /* Return nonzero if a 32 bit "long_call" should be generated for
2354 this call. We generate a long_call if the function:
2356 a. has an __attribute__((long call))
2357 or b. is within the scope of a #pragma long_calls
2358 or c. the -mlong-calls command line switch has been specified
2360 However we do not generate a long call if the function:
2362 d. has an __attribute__ ((short_call))
2363 or e. is inside the scope of a #pragma no_long_calls
2364 or f. has an __attribute__ ((section))
2365 or g. is defined within the current compilation unit.
2367 This function will be called by C fragments contained in the machine
2368 description file. CALL_REF and CALL_COOKIE correspond to the matched
2369 rtl operands. CALL_SYMBOL is used to distinguish between
2370 two different callers of the function. It is set to 1 in the
2371 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2372 and "call_value" patterns. This is because of the difference in the
2373 SYM_REFs passed by these patterns. */
2375 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
2379 if (GET_CODE (sym_ref
) != MEM
)
2382 sym_ref
= XEXP (sym_ref
, 0);
2385 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
2388 if (call_cookie
& CALL_SHORT
)
2391 if (TARGET_LONG_CALLS
&& flag_function_sections
)
2394 if (current_file_function_operand (sym_ref
))
2397 return (call_cookie
& CALL_LONG
)
2398 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
2399 || TARGET_LONG_CALLS
;
2402 /* Return nonzero if it is ok to make a tail-call to DECL. */
2404 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
2406 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
2408 if (cfun
->machine
->sibcall_blocked
)
2411 /* Never tailcall something for which we have no decl, or if we
2412 are in Thumb mode. */
2413 if (decl
== NULL
|| TARGET_THUMB
)
2416 /* Get the calling method. */
2417 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2418 call_type
= CALL_SHORT
;
2419 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2420 call_type
= CALL_LONG
;
2422 /* Cannot tail-call to long calls, since these are out of range of
2423 a branch instruction. However, if not compiling PIC, we know
2424 we can reach the symbol if it is in this compilation unit. */
2425 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
2428 /* If we are interworking and the function is not declared static
2429 then we can't tail-call it unless we know that it exists in this
2430 compilation unit (since it might be a Thumb routine). */
2431 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
2434 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2435 if (IS_INTERRUPT (arm_current_func_type ()))
2438 /* Everything else is ok. */
2443 /* Addressing mode support functions. */
2445 /* Return nonzero if X is a legitimate immediate operand when compiling
2448 legitimate_pic_operand_p (rtx x
)
2452 && (GET_CODE (x
) == SYMBOL_REF
2453 || (GET_CODE (x
) == CONST
2454 && GET_CODE (XEXP (x
, 0)) == PLUS
2455 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
2462 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
2464 if (GET_CODE (orig
) == SYMBOL_REF
2465 || GET_CODE (orig
) == LABEL_REF
)
2467 #ifndef AOF_ASSEMBLER
2468 rtx pic_ref
, address
;
2478 reg
= gen_reg_rtx (Pmode
);
2483 #ifdef AOF_ASSEMBLER
2484 /* The AOF assembler can generate relocations for these directly, and
2485 understands that the PIC register has to be added into the offset. */
2486 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
2489 address
= gen_reg_rtx (Pmode
);
2494 emit_insn (gen_pic_load_addr_arm (address
, orig
));
2496 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
2498 if ((GET_CODE (orig
) == LABEL_REF
2499 || (GET_CODE (orig
) == SYMBOL_REF
&&
2500 ENCODED_SHORT_CALL_ATTR_P (XSTR (orig
, 0))))
2502 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
2505 pic_ref
= gen_rtx_MEM (Pmode
,
2506 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
2508 RTX_UNCHANGING_P (pic_ref
) = 1;
2511 insn
= emit_move_insn (reg
, pic_ref
);
2513 current_function_uses_pic_offset_table
= 1;
2514 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2516 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
2520 else if (GET_CODE (orig
) == CONST
)
2524 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2525 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2533 reg
= gen_reg_rtx (Pmode
);
2536 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2538 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2539 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2540 base
== reg
? 0 : reg
);
2545 if (GET_CODE (offset
) == CONST_INT
)
2547 /* The base register doesn't really matter, we only want to
2548 test the index for the appropriate mode. */
2549 if (!arm_legitimate_index_p (mode
, offset
, 0))
2551 if (!no_new_pseudos
)
2552 offset
= force_reg (Pmode
, offset
);
2557 if (GET_CODE (offset
) == CONST_INT
)
2558 return plus_constant (base
, INTVAL (offset
));
2561 if (GET_MODE_SIZE (mode
) > 4
2562 && (GET_MODE_CLASS (mode
) == MODE_INT
2563 || TARGET_SOFT_FLOAT
))
2565 emit_insn (gen_addsi3 (reg
, base
, offset
));
2569 return gen_rtx_PLUS (Pmode
, base
, offset
);
2575 /* Generate code to load the PIC register. PROLOGUE is true if
2576 called from arm_expand_prologue (in which case we want the
2577 generated insns at the start of the function); false if called
2578 by an exception receiver that needs the PIC register reloaded
2579 (in which case the insns are just dumped at the current location). */
2581 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED
)
2583 #ifndef AOF_ASSEMBLER
2584 rtx l1
, pic_tmp
, pic_tmp2
, seq
, pic_rtx
;
2585 rtx global_offset_table
;
2587 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
2594 l1
= gen_label_rtx ();
2596 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
2597 /* On the ARM the PC register contains 'dot + 8' at the time of the
2598 addition, on the Thumb it is 'dot + 4'. */
2599 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), TARGET_ARM
? 8 : 4);
2601 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
2602 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
2604 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
2606 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
2610 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
2611 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
2615 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
2616 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
, l1
));
2622 emit_insn_after (seq
, get_insns ());
2626 /* Need to emit this whether or not we obey regdecls,
2627 since setjmp/longjmp can cause life info to screw up. */
2628 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
2629 #endif /* AOF_ASSEMBLER */
2632 /* Return nonzero if X is valid as an ARM state addressing register. */
2634 arm_address_register_rtx_p (rtx x
, int strict_p
)
2638 if (GET_CODE (x
) != REG
)
2644 return ARM_REGNO_OK_FOR_BASE_P (regno
);
2646 return (regno
<= LAST_ARM_REGNUM
2647 || regno
>= FIRST_PSEUDO_REGISTER
2648 || regno
== FRAME_POINTER_REGNUM
2649 || regno
== ARG_POINTER_REGNUM
);
2652 /* Return nonzero if X is a valid ARM state address operand. */
2654 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
2656 if (arm_address_register_rtx_p (x
, strict_p
))
2659 else if (GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_DEC
)
2660 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
2662 else if ((GET_CODE (x
) == POST_MODIFY
|| GET_CODE (x
) == PRE_MODIFY
)
2663 && GET_MODE_SIZE (mode
) <= 4
2664 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
2665 && GET_CODE (XEXP (x
, 1)) == PLUS
2666 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2667 return arm_legitimate_index_p (mode
, XEXP (XEXP (x
, 1), 1), strict_p
);
2669 /* After reload constants split into minipools will have addresses
2670 from a LABEL_REF. */
2671 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
2672 && (GET_CODE (x
) == LABEL_REF
2673 || (GET_CODE (x
) == CONST
2674 && GET_CODE (XEXP (x
, 0)) == PLUS
2675 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
2676 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
2679 else if (mode
== TImode
)
2682 else if (mode
== DImode
|| (TARGET_SOFT_FLOAT
&& mode
== DFmode
))
2684 if (GET_CODE (x
) == PLUS
2685 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
2686 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2688 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2690 if (val
== 4 || val
== -4 || val
== -8)
2695 else if (GET_CODE (x
) == PLUS
)
2697 rtx xop0
= XEXP (x
, 0);
2698 rtx xop1
= XEXP (x
, 1);
2700 return ((arm_address_register_rtx_p (xop0
, strict_p
)
2701 && arm_legitimate_index_p (mode
, xop1
, strict_p
))
2702 || (arm_address_register_rtx_p (xop1
, strict_p
)
2703 && arm_legitimate_index_p (mode
, xop0
, strict_p
)));
2707 /* Reload currently can't handle MINUS, so disable this for now */
2708 else if (GET_CODE (x
) == MINUS
)
2710 rtx xop0
= XEXP (x
, 0);
2711 rtx xop1
= XEXP (x
, 1);
2713 return (arm_address_register_rtx_p (xop0
, strict_p
)
2714 && arm_legitimate_index_p (mode
, xop1
, strict_p
));
2718 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
2719 && GET_CODE (x
) == SYMBOL_REF
2720 && CONSTANT_POOL_ADDRESS_P (x
)
2722 && symbol_mentioned_p (get_pool_constant (x
))))
2725 else if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == POST_DEC
)
2726 && (GET_MODE_SIZE (mode
) <= 4)
2727 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
))
2733 /* Return nonzero if INDEX is valid for an address index operand in
2736 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, int strict_p
)
2738 HOST_WIDE_INT range
;
2739 enum rtx_code code
= GET_CODE (index
);
2741 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2742 return (code
== CONST_INT
&& INTVAL (index
) < 1024
2743 && INTVAL (index
) > -1024
2744 && (INTVAL (index
) & 3) == 0);
2747 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
|| mode
== DImode
))
2748 return (code
== CONST_INT
2749 && INTVAL (index
) < 255
2750 && INTVAL (index
) > -255);
2752 if (arm_address_register_rtx_p (index
, strict_p
)
2753 && GET_MODE_SIZE (mode
) <= 4)
2756 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
2757 return (code
== CONST_INT
2758 && INTVAL (index
) < 256
2759 && INTVAL (index
) > -256);
2761 /* XXX What about ldrsb? */
2762 if (GET_MODE_SIZE (mode
) <= 4 && code
== MULT
2763 && (!arm_arch4
|| (mode
) != HImode
))
2765 rtx xiop0
= XEXP (index
, 0);
2766 rtx xiop1
= XEXP (index
, 1);
2768 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
2769 && power_of_two_operand (xiop1
, SImode
))
2770 || (arm_address_register_rtx_p (xiop1
, strict_p
)
2771 && power_of_two_operand (xiop0
, SImode
)));
2774 if (GET_MODE_SIZE (mode
) <= 4
2775 && (code
== LSHIFTRT
|| code
== ASHIFTRT
2776 || code
== ASHIFT
|| code
== ROTATERT
)
2777 && (!arm_arch4
|| (mode
) != HImode
))
2779 rtx op
= XEXP (index
, 1);
2781 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
2782 && GET_CODE (op
) == CONST_INT
2784 && INTVAL (op
) <= 31);
2787 /* XXX For ARM v4 we may be doing a sign-extend operation during the
2788 load, but that has a restricted addressing range and we are unable
2789 to tell here whether that is the case. To be safe we restrict all
2790 loads to that range. */
2791 range
= ((mode
) == HImode
|| (mode
) == QImode
)
2792 ? (arm_arch4
? 256 : 4095) : 4096;
2794 return (code
== CONST_INT
2795 && INTVAL (index
) < range
2796 && INTVAL (index
) > -range
);
2799 /* Return nonzero if X is valid as an ARM state addressing register. */
2801 thumb_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
2805 if (GET_CODE (x
) != REG
)
2811 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
2813 return (regno
<= LAST_LO_REGNUM
2814 || regno
>= FIRST_PSEUDO_REGISTER
2815 || regno
== FRAME_POINTER_REGNUM
2816 || (GET_MODE_SIZE (mode
) >= 4
2817 && (regno
== STACK_POINTER_REGNUM
2818 || x
== hard_frame_pointer_rtx
2819 || x
== arg_pointer_rtx
)));
2822 /* Return nonzero if x is a legitimate index register. This is the case
2823 for any base register that can access a QImode object. */
2825 thumb_index_register_rtx_p (rtx x
, int strict_p
)
2827 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
2830 /* Return nonzero if x is a legitimate Thumb-state address.
2832 The AP may be eliminated to either the SP or the FP, so we use the
2833 least common denominator, e.g. SImode, and offsets from 0 to 64.
2835 ??? Verify whether the above is the right approach.
2837 ??? Also, the FP may be eliminated to the SP, so perhaps that
2838 needs special handling also.
2840 ??? Look at how the mips16 port solves this problem. It probably uses
2841 better ways to solve some of these problems.
2843 Although it is not incorrect, we don't accept QImode and HImode
2844 addresses based on the frame pointer or arg pointer until the
2845 reload pass starts. This is so that eliminating such addresses
2846 into stack based ones won't produce impossible code. */
2848 thumb_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
2850 /* ??? Not clear if this is right. Experiment. */
2851 if (GET_MODE_SIZE (mode
) < 4
2852 && !(reload_in_progress
|| reload_completed
)
2853 && (reg_mentioned_p (frame_pointer_rtx
, x
)
2854 || reg_mentioned_p (arg_pointer_rtx
, x
)
2855 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
2856 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
2857 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
2858 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
2861 /* Accept any base register. SP only in SImode or larger. */
2862 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
2865 /* This is PC relative data before arm_reorg runs. */
2866 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
2867 && GET_CODE (x
) == SYMBOL_REF
2868 && CONSTANT_POOL_ADDRESS_P (x
) && ! flag_pic
)
2871 /* This is PC relative data after arm_reorg runs. */
2872 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
2873 && (GET_CODE (x
) == LABEL_REF
2874 || (GET_CODE (x
) == CONST
2875 && GET_CODE (XEXP (x
, 0)) == PLUS
2876 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
2877 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
2880 /* Post-inc indexing only supported for SImode and larger. */
2881 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
2882 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
2885 else if (GET_CODE (x
) == PLUS
)
2887 /* REG+REG address can be any two index registers. */
2888 /* We disallow FRAME+REG addressing since we know that FRAME
2889 will be replaced with STACK, and SP relative addressing only
2890 permits SP+OFFSET. */
2891 if (GET_MODE_SIZE (mode
) <= 4
2892 && XEXP (x
, 0) != frame_pointer_rtx
2893 && XEXP (x
, 1) != frame_pointer_rtx
2894 && XEXP (x
, 0) != virtual_stack_vars_rtx
2895 && XEXP (x
, 1) != virtual_stack_vars_rtx
2896 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
2897 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
2900 /* REG+const has 5-7 bit offset for non-SP registers. */
2901 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
2902 || XEXP (x
, 0) == arg_pointer_rtx
)
2903 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2904 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
2907 /* REG+const has 10 bit offset for SP, but only SImode and
2908 larger is supported. */
2909 /* ??? Should probably check for DI/DFmode overflow here
2910 just like GO_IF_LEGITIMATE_OFFSET does. */
2911 else if (GET_CODE (XEXP (x
, 0)) == REG
2912 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
2913 && GET_MODE_SIZE (mode
) >= 4
2914 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2915 && INTVAL (XEXP (x
, 1)) >= 0
2916 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
2917 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
2920 else if (GET_CODE (XEXP (x
, 0)) == REG
2921 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
2922 && GET_MODE_SIZE (mode
) >= 4
2923 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2924 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
2928 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
2929 && GET_CODE (x
) == SYMBOL_REF
2930 && CONSTANT_POOL_ADDRESS_P (x
)
2932 && symbol_mentioned_p (get_pool_constant (x
))))
2938 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
2939 instruction of mode MODE. */
2941 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
2943 switch (GET_MODE_SIZE (mode
))
2946 return val
>= 0 && val
< 32;
2949 return val
>= 0 && val
< 64 && (val
& 1) == 0;
2953 && (val
+ GET_MODE_SIZE (mode
)) <= 128
2958 /* Try machine-dependent ways of modifying an illegitimate address
2959 to be legitimate. If we find one, return the new, valid address. */
2961 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
2963 if (GET_CODE (x
) == PLUS
)
2965 rtx xop0
= XEXP (x
, 0);
2966 rtx xop1
= XEXP (x
, 1);
2968 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
2969 xop0
= force_reg (SImode
, xop0
);
2971 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
2972 xop1
= force_reg (SImode
, xop1
);
2974 if (ARM_BASE_REGISTER_RTX_P (xop0
)
2975 && GET_CODE (xop1
) == CONST_INT
)
2977 HOST_WIDE_INT n
, low_n
;
2981 if (mode
== DImode
|| (TARGET_SOFT_FLOAT
&& mode
== DFmode
))
2993 low_n
= ((mode
) == TImode
? 0
2994 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
2998 base_reg
= gen_reg_rtx (SImode
);
2999 val
= force_operand (gen_rtx_PLUS (SImode
, xop0
,
3000 GEN_INT (n
)), NULL_RTX
);
3001 emit_move_insn (base_reg
, val
);
3002 x
= (low_n
== 0 ? base_reg
3003 : gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (low_n
)));
3005 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3006 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3009 /* XXX We don't allow MINUS any more -- see comment in
3010 arm_legitimate_address_p (). */
3011 else if (GET_CODE (x
) == MINUS
)
3013 rtx xop0
= XEXP (x
, 0);
3014 rtx xop1
= XEXP (x
, 1);
3016 if (CONSTANT_P (xop0
))
3017 xop0
= force_reg (SImode
, xop0
);
3019 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
3020 xop1
= force_reg (SImode
, xop1
);
3022 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3023 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
3028 /* We need to find and carefully transform any SYMBOL and LABEL
3029 references; so go back to the original address expression. */
3030 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3032 if (new_x
!= orig_x
)
3041 #define REG_OR_SUBREG_REG(X) \
3042 (GET_CODE (X) == REG \
3043 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3045 #define REG_OR_SUBREG_RTX(X) \
3046 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3048 #ifndef COSTS_N_INSNS
3049 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3051 /* Worker routine for arm_rtx_costs. */
3053 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
3055 enum machine_mode mode
= GET_MODE (x
);
3056 enum rtx_code subcode
;
3072 return COSTS_N_INSNS (1);
3075 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3078 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
3085 return COSTS_N_INSNS (2) + cycles
;
3087 return COSTS_N_INSNS (1) + 16;
3090 return (COSTS_N_INSNS (1)
3091 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
3092 + GET_CODE (SET_DEST (x
)) == MEM
));
3097 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
3099 if (thumb_shiftable_const (INTVAL (x
)))
3100 return COSTS_N_INSNS (2);
3101 return COSTS_N_INSNS (3);
3103 else if (outer
== PLUS
3104 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
3106 else if (outer
== COMPARE
3107 && (unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
3109 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
3110 || outer
== LSHIFTRT
)
3112 return COSTS_N_INSNS (2);
3118 return COSTS_N_INSNS (3);
3137 /* XXX another guess. */
3138 /* Memory costs quite a lot for the first word, but subsequent words
3139 load at the equivalent of a single insn each. */
3140 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3141 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
3146 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3151 /* XXX still guessing. */
3152 switch (GET_MODE (XEXP (x
, 0)))
3155 return (1 + (mode
== DImode
? 4 : 0)
3156 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3159 return (4 + (mode
== DImode
? 4 : 0)
3160 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3163 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3177 fprintf (stderr
, "unexpected code for thumb in rtx_costs: %s\n",
3187 /* Memory costs quite a lot for the first word, but subsequent words
3188 load at the equivalent of a single insn each. */
3189 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3190 + (GET_CODE (x
) == SYMBOL_REF
3191 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
3198 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
3205 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
3207 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
3208 + ((GET_CODE (XEXP (x
, 0)) == REG
3209 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3210 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3212 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
3213 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3214 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3216 + ((GET_CODE (XEXP (x
, 1)) == REG
3217 || (GET_CODE (XEXP (x
, 1)) == SUBREG
3218 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
3219 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
3224 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
3225 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3226 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
3227 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
3230 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3231 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3232 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3233 && const_double_rtx_ok_for_fpa (XEXP (x
, 1))))
3235 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3236 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
3237 && const_double_rtx_ok_for_fpa (XEXP (x
, 0))))
3240 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
3241 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
3242 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
3243 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
3244 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
3245 || subcode
== ROTATE
|| subcode
== ROTATERT
3247 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
3248 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
3249 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
3250 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
3251 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
3252 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
3253 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
3258 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3259 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3260 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3261 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3262 && const_double_rtx_ok_for_fpa (XEXP (x
, 1))))
3266 case AND
: case XOR
: case IOR
:
3269 /* Normally the frame registers will be spilt into reg+const during
3270 reload, so it is a bad idea to combine them with other instructions,
3271 since then they might not be moved outside of loops. As a compromise
3272 we allow integration with ops that have a constant as their second
3274 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3275 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
3276 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3277 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
3278 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
3282 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3283 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3284 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3285 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3288 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
3289 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
3290 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3291 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3292 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3295 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
3296 return (1 + extra_cost
3297 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
3298 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
3299 || subcode
== ROTATE
|| subcode
== ROTATERT
3301 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3302 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
3303 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
3304 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
3305 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
3306 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
3312 /* There is no point basing this on the tuning, since it is always the
3313 fast variant if it exists at all. */
3314 if (arm_fast_multiply
&& mode
== DImode
3315 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
3316 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
3317 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
3320 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3324 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3326 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
3327 & (unsigned HOST_WIDE_INT
) 0xffffffff);
3328 int add_cost
= const_ok_for_arm (i
) ? 4 : 8;
3331 /* Tune as appropriate. */
3332 int booth_unit_size
= ((tune_flags
& FL_FAST_MULT
) ? 8 : 2);
3334 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
3336 i
>>= booth_unit_size
;
3343 return (((tune_flags
& FL_FAST_MULT
) ? 8 : 30)
3344 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
3345 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4));
3348 if (arm_fast_multiply
&& mode
== SImode
3349 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3350 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
3351 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
3352 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
3353 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
3354 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
3359 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3360 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
3364 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
3366 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
3369 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3377 return 4 + (mode
== DImode
? 4 : 0);
3380 if (GET_MODE (XEXP (x
, 0)) == QImode
)
3381 return (4 + (mode
== DImode
? 4 : 0)
3382 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3385 switch (GET_MODE (XEXP (x
, 0)))
3388 return (1 + (mode
== DImode
? 4 : 0)
3389 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3392 return (4 + (mode
== DImode
? 4 : 0)
3393 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3396 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3411 if (const_ok_for_arm (INTVAL (x
)))
3412 return outer
== SET
? 2 : -1;
3413 else if (outer
== AND
3414 && const_ok_for_arm (~INTVAL (x
)))
3416 else if ((outer
== COMPARE
3417 || outer
== PLUS
|| outer
== MINUS
)
3418 && const_ok_for_arm (-INTVAL (x
)))
3429 if (const_double_rtx_ok_for_fpa (x
))
3430 return outer
== SET
? 2 : -1;
3431 else if ((outer
== COMPARE
|| outer
== PLUS
)
3432 && neg_const_double_rtx_ok_for_fpa (x
))
3442 arm_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
3444 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
3448 /* All address computations that can be done are free, but rtx cost returns
3449 the same for practically all of them. So we weight the different types
3450 of address here in the order (most pref first):
3451 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
3453 arm_address_cost (rtx x
)
3455 #define ARM_ADDRESS_COST(X) \
3456 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
3457 || GET_CODE (X) == SYMBOL_REF) \
3459 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
3460 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
3462 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
3463 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
3464 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
3465 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
3466 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
3467 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
3471 #define THUMB_ADDRESS_COST(X) \
3472 ((GET_CODE (X) == REG \
3473 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
3474 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
3477 return (TARGET_ARM
? ARM_ADDRESS_COST (x
) : THUMB_ADDRESS_COST (x
));
3481 arm_use_dfa_pipeline_interface (void)
3487 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
3491 /* Some true dependencies can have a higher cost depending
3492 on precisely how certain input operands are used. */
3494 && REG_NOTE_KIND (link
) == 0
3495 && recog_memoized (insn
) >= 0
3496 && recog_memoized (dep
) >= 0)
3498 int shift_opnum
= get_attr_shift (insn
);
3499 enum attr_type attr_type
= get_attr_type (dep
);
3501 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
3502 operand for INSN. If we have a shifted input operand and the
3503 instruction we depend on is another ALU instruction, then we may
3504 have to account for an additional stall. */
3505 if (shift_opnum
!= 0 && attr_type
== TYPE_NORMAL
)
3507 rtx shifted_operand
;
3510 /* Get the shifted operand. */
3511 extract_insn (insn
);
3512 shifted_operand
= recog_data
.operand
[shift_opnum
];
3514 /* Iterate over all the operands in DEP. If we write an operand
3515 that overlaps with SHIFTED_OPERAND, then we have increase the
3516 cost of this dependency. */
3518 preprocess_constraints ();
3519 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
3521 /* We can ignore strict inputs. */
3522 if (recog_data
.operand_type
[opno
] == OP_IN
)
3525 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
3532 /* XXX This is not strictly true for the FPA. */
3533 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
3534 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
3537 /* Call insns don't incur a stall, even if they follow a load. */
3538 if (REG_NOTE_KIND (link
) == 0
3539 && GET_CODE (insn
) == CALL_INSN
)
3542 if ((i_pat
= single_set (insn
)) != NULL
3543 && GET_CODE (SET_SRC (i_pat
)) == MEM
3544 && (d_pat
= single_set (dep
)) != NULL
3545 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
3547 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
3548 /* This is a load after a store, there is no conflict if the load reads
3549 from a cached area. Assume that loads from the stack, and from the
3550 constant pool are cached, and that others will miss. This is a
3553 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
3554 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
3555 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
3556 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
3563 static int fpa_consts_inited
= 0;
3565 static const char * const strings_fpa
[8] =
3568 "4", "5", "0.5", "10"
3571 static REAL_VALUE_TYPE values_fpa
[8];
3574 init_fpa_table (void)
3579 for (i
= 0; i
< 8; i
++)
3581 r
= REAL_VALUE_ATOF (strings_fpa
[i
], DFmode
);
3585 fpa_consts_inited
= 1;
3588 /* Return TRUE if rtx X is a valid immediate FPA constant. */
3590 const_double_rtx_ok_for_fpa (rtx x
)
3595 if (!fpa_consts_inited
)
3598 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3599 if (REAL_VALUE_MINUS_ZERO (r
))
3602 for (i
= 0; i
< 8; i
++)
3603 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
3609 /* Return TRUE if rtx X is a valid immediate FPA constant. */
3611 neg_const_double_rtx_ok_for_fpa (rtx x
)
3616 if (!fpa_consts_inited
)
3619 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3620 r
= REAL_VALUE_NEGATE (r
);
3621 if (REAL_VALUE_MINUS_ZERO (r
))
3624 for (i
= 0; i
< 8; i
++)
3625 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
3631 /* Predicates for `match_operand' and `match_operator'. */
3633 /* s_register_operand is the same as register_operand, but it doesn't accept
3636 This function exists because at the time it was put in it led to better
3637 code. SUBREG(MEM) always needs a reload in the places where
3638 s_register_operand is used, and this seemed to lead to excessive
3641 s_register_operand (rtx op
, enum machine_mode mode
)
3643 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3646 if (GET_CODE (op
) == SUBREG
)
3647 op
= SUBREG_REG (op
);
3649 /* We don't consider registers whose class is NO_REGS
3650 to be a register operand. */
3651 /* XXX might have to check for lo regs only for thumb ??? */
3652 return (GET_CODE (op
) == REG
3653 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3654 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
3657 /* A hard register operand (even before reload. */
3659 arm_hard_register_operand (rtx op
, enum machine_mode mode
)
3661 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3664 return (GET_CODE (op
) == REG
3665 && REGNO (op
) < FIRST_PSEUDO_REGISTER
);
3668 /* Only accept reg, subreg(reg), const_int. */
3670 reg_or_int_operand (rtx op
, enum machine_mode mode
)
3672 if (GET_CODE (op
) == CONST_INT
)
3675 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3678 if (GET_CODE (op
) == SUBREG
)
3679 op
= SUBREG_REG (op
);
3681 /* We don't consider registers whose class is NO_REGS
3682 to be a register operand. */
3683 return (GET_CODE (op
) == REG
3684 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3685 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
3688 /* Return 1 if OP is an item in memory, given that we are in reload. */
3690 arm_reload_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3692 int regno
= true_regnum (op
);
3694 return (!CONSTANT_P (op
)
3696 || (GET_CODE (op
) == REG
3697 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)));
3700 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
3701 memory access (architecture V4).
3702 MODE is QImode if called when computing constraints, or VOIDmode when
3703 emitting patterns. In this latter case we cannot use memory_operand()
3704 because it will fail on badly formed MEMs, which is precisely what we are
3707 bad_signed_byte_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3710 if ((mode
== QImode
&& !memory_operand (op
, mode
)) || GET_CODE (op
) != MEM
)
3713 if (GET_CODE (op
) != MEM
)
3718 /* A sum of anything more complex than reg + reg or reg + const is bad. */
3719 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3720 && (!s_register_operand (XEXP (op
, 0), VOIDmode
)
3721 || (!s_register_operand (XEXP (op
, 1), VOIDmode
)
3722 && GET_CODE (XEXP (op
, 1)) != CONST_INT
)))
3725 /* Big constants are also bad. */
3726 if (GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
3727 && (INTVAL (XEXP (op
, 1)) > 0xff
3728 || -INTVAL (XEXP (op
, 1)) > 0xff))
3731 /* Everything else is good, or can will automatically be made so. */
3735 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
3737 arm_rhs_operand (rtx op
, enum machine_mode mode
)
3739 return (s_register_operand (op
, mode
)
3740 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
))));
3743 /* Return TRUE for valid operands for the
3744 rhs of an ARM instruction, or a load. */
3746 arm_rhsm_operand (rtx op
, enum machine_mode mode
)
3748 return (s_register_operand (op
, mode
)
3749 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
)))
3750 || memory_operand (op
, mode
));
3753 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
3754 constant that is valid when negated. */
3756 arm_add_operand (rtx op
, enum machine_mode mode
)
3759 return thumb_cmp_operand (op
, mode
);
3761 return (s_register_operand (op
, mode
)
3762 || (GET_CODE (op
) == CONST_INT
3763 && (const_ok_for_arm (INTVAL (op
))
3764 || const_ok_for_arm (-INTVAL (op
)))));
3768 arm_not_operand (rtx op
, enum machine_mode mode
)
3770 return (s_register_operand (op
, mode
)
3771 || (GET_CODE (op
) == CONST_INT
3772 && (const_ok_for_arm (INTVAL (op
))
3773 || const_ok_for_arm (~INTVAL (op
)))));
3776 /* Return TRUE if the operand is a memory reference which contains an
3777 offsettable address. */
3779 offsettable_memory_operand (rtx op
, enum machine_mode mode
)
3781 if (mode
== VOIDmode
)
3782 mode
= GET_MODE (op
);
3784 return (mode
== GET_MODE (op
)
3785 && GET_CODE (op
) == MEM
3786 && offsettable_address_p (reload_completed
| reload_in_progress
,
3787 mode
, XEXP (op
, 0)));
3790 /* Return TRUE if the operand is a memory reference which is, or can be
3791 made word aligned by adjusting the offset. */
3793 alignable_memory_operand (rtx op
, enum machine_mode mode
)
3797 if (mode
== VOIDmode
)
3798 mode
= GET_MODE (op
);
3800 if (mode
!= GET_MODE (op
) || GET_CODE (op
) != MEM
)
3805 return ((GET_CODE (reg
= op
) == REG
3806 || (GET_CODE (op
) == SUBREG
3807 && GET_CODE (reg
= SUBREG_REG (op
)) == REG
)
3808 || (GET_CODE (op
) == PLUS
3809 && GET_CODE (XEXP (op
, 1)) == CONST_INT
3810 && (GET_CODE (reg
= XEXP (op
, 0)) == REG
3811 || (GET_CODE (XEXP (op
, 0)) == SUBREG
3812 && GET_CODE (reg
= SUBREG_REG (XEXP (op
, 0))) == REG
))))
3813 && REGNO_POINTER_ALIGN (REGNO (reg
)) >= 32);
3816 /* Similar to s_register_operand, but does not allow hard integer
3819 f_register_operand (rtx op
, enum machine_mode mode
)
3821 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3824 if (GET_CODE (op
) == SUBREG
)
3825 op
= SUBREG_REG (op
);
3827 /* We don't consider registers whose class is NO_REGS
3828 to be a register operand. */
3829 return (GET_CODE (op
) == REG
3830 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3831 || REGNO_REG_CLASS (REGNO (op
)) == FPA_REGS
));
3834 /* Return TRUE for valid operands for the rhs of an FPA instruction. */
3836 fpa_rhs_operand (rtx op
, enum machine_mode mode
)
3838 if (s_register_operand (op
, mode
))
3841 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3844 if (GET_CODE (op
) == CONST_DOUBLE
)
3845 return const_double_rtx_ok_for_fpa (op
);
3851 fpa_add_operand (rtx op
, enum machine_mode mode
)
3853 if (s_register_operand (op
, mode
))
3856 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3859 if (GET_CODE (op
) == CONST_DOUBLE
)
3860 return (const_double_rtx_ok_for_fpa (op
)
3861 || neg_const_double_rtx_ok_for_fpa (op
));
3866 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
3868 cirrus_memory_offset (rtx op
)
3870 /* Reject eliminable registers. */
3871 if (! (reload_in_progress
|| reload_completed
)
3872 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
3873 || reg_mentioned_p (arg_pointer_rtx
, op
)
3874 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
3875 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
3876 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
3877 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
3880 if (GET_CODE (op
) == MEM
)
3886 /* Match: (mem (reg)). */
3887 if (GET_CODE (ind
) == REG
)
3893 if (GET_CODE (ind
) == PLUS
3894 && GET_CODE (XEXP (ind
, 0)) == REG
3895 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
3896 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
3903 /* Return nonzero if OP is a Cirrus or general register. */
3905 cirrus_register_operand (rtx op
, enum machine_mode mode
)
3907 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3910 if (GET_CODE (op
) == SUBREG
)
3911 op
= SUBREG_REG (op
);
3913 return (GET_CODE (op
) == REG
3914 && (REGNO_REG_CLASS (REGNO (op
)) == CIRRUS_REGS
3915 || REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
));
3918 /* Return nonzero if OP is a cirrus FP register. */
3920 cirrus_fp_register (rtx op
, enum machine_mode mode
)
3922 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3925 if (GET_CODE (op
) == SUBREG
)
3926 op
= SUBREG_REG (op
);
3928 return (GET_CODE (op
) == REG
3929 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3930 || REGNO_REG_CLASS (REGNO (op
)) == CIRRUS_REGS
));
3933 /* Return nonzero if OP is a 6bit constant (0..63). */
3935 cirrus_shift_const (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3937 return (GET_CODE (op
) == CONST_INT
3939 && INTVAL (op
) < 64);
3942 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
3943 Use by the Cirrus Maverick code which has to workaround
3944 a hardware bug triggered by such instructions. */
3946 arm_memory_load_p (rtx insn
)
3948 rtx body
, lhs
, rhs
;;
3950 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
3953 body
= PATTERN (insn
);
3955 if (GET_CODE (body
) != SET
)
3958 lhs
= XEXP (body
, 0);
3959 rhs
= XEXP (body
, 1);
3961 lhs
= REG_OR_SUBREG_RTX (lhs
);
3963 /* If the destination is not a general purpose
3964 register we do not have to worry. */
3965 if (GET_CODE (lhs
) != REG
3966 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
3969 /* As well as loads from memory we also have to react
3970 to loads of invalid constants which will be turned
3971 into loads from the minipool. */
3972 return (GET_CODE (rhs
) == MEM
3973 || GET_CODE (rhs
) == SYMBOL_REF
3974 || note_invalid_constants (insn
, -1, false));
3977 /* Return TRUE if INSN is a Cirrus instruction. */
3979 arm_cirrus_insn_p (rtx insn
)
3981 enum attr_cirrus attr
;
3983 /* get_attr aborts on USE and CLOBBER. */
3985 || GET_CODE (insn
) != INSN
3986 || GET_CODE (PATTERN (insn
)) == USE
3987 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
3990 attr
= get_attr_cirrus (insn
);
3992 return attr
!= CIRRUS_NOT
;
3995 /* Cirrus reorg for invalid instruction combinations. */
3997 cirrus_reorg (rtx first
)
3999 enum attr_cirrus attr
;
4000 rtx body
= PATTERN (first
);
4004 /* Any branch must be followed by 2 non Cirrus instructions. */
4005 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
4008 t
= next_nonnote_insn (first
);
4010 if (arm_cirrus_insn_p (t
))
4013 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
4017 emit_insn_after (gen_nop (), first
);
4022 /* (float (blah)) is in parallel with a clobber. */
4023 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
4024 body
= XVECEXP (body
, 0, 0);
4026 if (GET_CODE (body
) == SET
)
4028 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
4030 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4031 be followed by a non Cirrus insn. */
4032 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
4034 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
4035 emit_insn_after (gen_nop (), first
);
4039 else if (arm_memory_load_p (first
))
4041 unsigned int arm_regno
;
4043 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4044 ldr/cfmv64hr combination where the Rd field is the same
4045 in both instructions must be split with a non Cirrus
4052 /* Get Arm register number for ldr insn. */
4053 if (GET_CODE (lhs
) == REG
)
4054 arm_regno
= REGNO (lhs
);
4055 else if (GET_CODE (rhs
) == REG
)
4056 arm_regno
= REGNO (rhs
);
4061 first
= next_nonnote_insn (first
);
4063 if (! arm_cirrus_insn_p (first
))
4066 body
= PATTERN (first
);
4068 /* (float (blah)) is in parallel with a clobber. */
4069 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
4070 body
= XVECEXP (body
, 0, 0);
4072 if (GET_CODE (body
) == FLOAT
)
4073 body
= XEXP (body
, 0);
4075 if (get_attr_cirrus (first
) == CIRRUS_MOVE
4076 && GET_CODE (XEXP (body
, 1)) == REG
4077 && arm_regno
== REGNO (XEXP (body
, 1)))
4078 emit_insn_after (gen_nop (), first
);
4084 /* get_attr aborts on USE and CLOBBER. */
4086 || GET_CODE (first
) != INSN
4087 || GET_CODE (PATTERN (first
)) == USE
4088 || GET_CODE (PATTERN (first
)) == CLOBBER
)
4091 attr
= get_attr_cirrus (first
);
4093 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4094 must be followed by a non-coprocessor instruction. */
4095 if (attr
== CIRRUS_COMPARE
)
4099 t
= next_nonnote_insn (first
);
4101 if (arm_cirrus_insn_p (t
))
4104 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
4108 emit_insn_after (gen_nop (), first
);
4114 /* Return nonzero if OP is a constant power of two. */
4116 power_of_two_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4118 if (GET_CODE (op
) == CONST_INT
)
4120 HOST_WIDE_INT value
= INTVAL (op
);
4122 return value
!= 0 && (value
& (value
- 1)) == 0;
4128 /* Return TRUE for a valid operand of a DImode operation.
4129 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4130 Note that this disallows MEM(REG+REG), but allows
4131 MEM(PRE/POST_INC/DEC(REG)). */
4133 di_operand (rtx op
, enum machine_mode mode
)
4135 if (s_register_operand (op
, mode
))
4138 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
4141 if (GET_CODE (op
) == SUBREG
)
4142 op
= SUBREG_REG (op
);
4144 switch (GET_CODE (op
))
4151 return memory_address_p (DImode
, XEXP (op
, 0));
4158 /* Like di_operand, but don't accept constants. */
4160 nonimmediate_di_operand (rtx op
, enum machine_mode mode
)
4162 if (s_register_operand (op
, mode
))
4165 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
4168 if (GET_CODE (op
) == SUBREG
)
4169 op
= SUBREG_REG (op
);
4171 if (GET_CODE (op
) == MEM
)
4172 return memory_address_p (DImode
, XEXP (op
, 0));
4177 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
4178 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4179 Note that this disallows MEM(REG+REG), but allows
4180 MEM(PRE/POST_INC/DEC(REG)). */
4182 soft_df_operand (rtx op
, enum machine_mode mode
)
4184 if (s_register_operand (op
, mode
))
4187 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
4190 if (GET_CODE (op
) == SUBREG
&& CONSTANT_P (SUBREG_REG (op
)))
4193 if (GET_CODE (op
) == SUBREG
)
4194 op
= SUBREG_REG (op
);
4196 switch (GET_CODE (op
))
4202 return memory_address_p (DFmode
, XEXP (op
, 0));
4209 /* Like soft_df_operand, but don't accept constants. */
4211 nonimmediate_soft_df_operand (rtx op
, enum machine_mode mode
)
4213 if (s_register_operand (op
, mode
))
4216 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
4219 if (GET_CODE (op
) == SUBREG
)
4220 op
= SUBREG_REG (op
);
4222 if (GET_CODE (op
) == MEM
)
4223 return memory_address_p (DFmode
, XEXP (op
, 0));
4227 /* Return TRUE for valid index operands. */
4229 index_operand (rtx op
, enum machine_mode mode
)
4231 return (s_register_operand (op
, mode
)
4232 || (immediate_operand (op
, mode
)
4233 && (GET_CODE (op
) != CONST_INT
4234 || (INTVAL (op
) < 4096 && INTVAL (op
) > -4096))));
4237 /* Return TRUE for valid shifts by a constant. This also accepts any
4238 power of two on the (somewhat overly relaxed) assumption that the
4239 shift operator in this case was a mult. */
4241 const_shift_operand (rtx op
, enum machine_mode mode
)
4243 return (power_of_two_operand (op
, mode
)
4244 || (immediate_operand (op
, mode
)
4245 && (GET_CODE (op
) != CONST_INT
4246 || (INTVAL (op
) < 32 && INTVAL (op
) > 0))));
4249 /* Return TRUE for arithmetic operators which can be combined with a multiply
4252 shiftable_operator (rtx x
, enum machine_mode mode
)
4256 if (GET_MODE (x
) != mode
)
4259 code
= GET_CODE (x
);
4261 return (code
== PLUS
|| code
== MINUS
4262 || code
== IOR
|| code
== XOR
|| code
== AND
);
4265 /* Return TRUE for binary logical operators. */
4267 logical_binary_operator (rtx x
, enum machine_mode mode
)
4271 if (GET_MODE (x
) != mode
)
4274 code
= GET_CODE (x
);
4276 return (code
== IOR
|| code
== XOR
|| code
== AND
);
4279 /* Return TRUE for shift operators. */
4281 shift_operator (rtx x
,enum machine_mode mode
)
4285 if (GET_MODE (x
) != mode
)
4288 code
= GET_CODE (x
);
4291 return power_of_two_operand (XEXP (x
, 1), mode
);
4293 return (code
== ASHIFT
|| code
== ASHIFTRT
|| code
== LSHIFTRT
4294 || code
== ROTATERT
);
4297 /* Return TRUE if x is EQ or NE. */
4299 equality_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4301 return GET_CODE (x
) == EQ
|| GET_CODE (x
) == NE
;
4304 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
4306 arm_comparison_operator (rtx x
, enum machine_mode mode
)
4308 return (comparison_operator (x
, mode
)
4309 && GET_CODE (x
) != LTGT
4310 && GET_CODE (x
) != UNEQ
);
4313 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
4315 minmax_operator (rtx x
, enum machine_mode mode
)
4317 enum rtx_code code
= GET_CODE (x
);
4319 if (GET_MODE (x
) != mode
)
4322 return code
== SMIN
|| code
== SMAX
|| code
== UMIN
|| code
== UMAX
;
4325 /* Return TRUE if this is the condition code register, if we aren't given
4326 a mode, accept any class CCmode register. */
4328 cc_register (rtx x
, enum machine_mode mode
)
4330 if (mode
== VOIDmode
)
4332 mode
= GET_MODE (x
);
4334 if (GET_MODE_CLASS (mode
) != MODE_CC
)
4338 if ( GET_MODE (x
) == mode
4339 && GET_CODE (x
) == REG
4340 && REGNO (x
) == CC_REGNUM
)
4346 /* Return TRUE if this is the condition code register, if we aren't given
4347 a mode, accept any class CCmode register which indicates a dominance
4350 dominant_cc_register (rtx x
, enum machine_mode mode
)
4352 if (mode
== VOIDmode
)
4354 mode
= GET_MODE (x
);
4356 if (GET_MODE_CLASS (mode
) != MODE_CC
)
4360 if (mode
!= CC_DNEmode
&& mode
!= CC_DEQmode
4361 && mode
!= CC_DLEmode
&& mode
!= CC_DLTmode
4362 && mode
!= CC_DGEmode
&& mode
!= CC_DGTmode
4363 && mode
!= CC_DLEUmode
&& mode
!= CC_DLTUmode
4364 && mode
!= CC_DGEUmode
&& mode
!= CC_DGTUmode
)
4367 return cc_register (x
, mode
);
4370 /* Return TRUE if X references a SYMBOL_REF. */
4372 symbol_mentioned_p (rtx x
)
4377 if (GET_CODE (x
) == SYMBOL_REF
)
4380 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
4382 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
4388 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4389 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
4392 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
4399 /* Return TRUE if X references a LABEL_REF. */
4401 label_mentioned_p (rtx x
)
4406 if (GET_CODE (x
) == LABEL_REF
)
4409 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
4410 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
4416 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4417 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
4420 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
4430 enum rtx_code code
= GET_CODE (x
);
4434 else if (code
== SMIN
)
4436 else if (code
== UMIN
)
4438 else if (code
== UMAX
)
4444 /* Return 1 if memory locations are adjacent. */
4446 adjacent_mem_locations (rtx a
, rtx b
)
4448 if ((GET_CODE (XEXP (a
, 0)) == REG
4449 || (GET_CODE (XEXP (a
, 0)) == PLUS
4450 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
4451 && (GET_CODE (XEXP (b
, 0)) == REG
4452 || (GET_CODE (XEXP (b
, 0)) == PLUS
4453 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
4455 int val0
= 0, val1
= 0;
4458 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
4460 reg0
= REGNO (XEXP (XEXP (a
, 0), 0));
4461 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
4464 reg0
= REGNO (XEXP (a
, 0));
4466 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
4468 reg1
= REGNO (XEXP (XEXP (b
, 0), 0));
4469 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
4472 reg1
= REGNO (XEXP (b
, 0));
4474 /* Don't accept any offset that will require multiple
4475 instructions to handle, since this would cause the
4476 arith_adjacentmem pattern to output an overlong sequence. */
4477 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
4480 return (reg0
== reg1
) && ((val1
- val0
) == 4 || (val0
- val1
) == 4);
4485 /* Return 1 if OP is a load multiple operation. It is known to be
4486 parallel and the first section will be tested. */
4488 load_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4490 HOST_WIDE_INT count
= XVECLEN (op
, 0);
4493 HOST_WIDE_INT i
= 1, base
= 0;
4497 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
4500 /* Check to see if this might be a write-back. */
4501 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
4506 /* Now check it more carefully. */
4507 if (GET_CODE (SET_DEST (elt
)) != REG
4508 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
4509 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
4510 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
4511 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
4515 /* Perform a quick check so we don't blow up below. */
4517 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
4518 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != REG
4519 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != MEM
)
4522 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, i
- 1)));
4523 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, i
- 1)), 0);
4525 for (; i
< count
; i
++)
4527 elt
= XVECEXP (op
, 0, i
);
4529 if (GET_CODE (elt
) != SET
4530 || GET_CODE (SET_DEST (elt
)) != REG
4531 || GET_MODE (SET_DEST (elt
)) != SImode
4532 || REGNO (SET_DEST (elt
)) != (unsigned int)(dest_regno
+ i
- base
)
4533 || GET_CODE (SET_SRC (elt
)) != MEM
4534 || GET_MODE (SET_SRC (elt
)) != SImode
4535 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
4536 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
4537 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
4538 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != (i
- base
) * 4)
4545 /* Return 1 if OP is a store multiple operation. It is known to be
4546 parallel and the first section will be tested. */
4548 store_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4550 HOST_WIDE_INT count
= XVECLEN (op
, 0);
4553 HOST_WIDE_INT i
= 1, base
= 0;
4557 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
4560 /* Check to see if this might be a write-back. */
4561 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
4566 /* Now check it more carefully. */
4567 if (GET_CODE (SET_DEST (elt
)) != REG
4568 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
4569 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
4570 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
4571 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
4575 /* Perform a quick check so we don't blow up below. */
4577 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
4578 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != MEM
4579 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != REG
)
4582 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, i
- 1)));
4583 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, i
- 1)), 0);
4585 for (; i
< count
; i
++)
4587 elt
= XVECEXP (op
, 0, i
);
4589 if (GET_CODE (elt
) != SET
4590 || GET_CODE (SET_SRC (elt
)) != REG
4591 || GET_MODE (SET_SRC (elt
)) != SImode
4592 || REGNO (SET_SRC (elt
)) != (unsigned int)(src_regno
+ i
- base
)
4593 || GET_CODE (SET_DEST (elt
)) != MEM
4594 || GET_MODE (SET_DEST (elt
)) != SImode
4595 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
4596 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
4597 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
4598 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != (i
- base
) * 4)
4606 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
4607 HOST_WIDE_INT
*load_offset
)
4609 int unsorted_regs
[4];
4610 HOST_WIDE_INT unsorted_offsets
[4];
4615 /* Can only handle 2, 3, or 4 insns at present,
4616 though could be easily extended if required. */
4617 if (nops
< 2 || nops
> 4)
4620 /* Loop over the operands and check that the memory references are
4621 suitable (ie immediate offsets from the same base register). At
4622 the same time, extract the target register, and the memory
4624 for (i
= 0; i
< nops
; i
++)
4629 /* Convert a subreg of a mem into the mem itself. */
4630 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
4631 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
4633 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
4636 /* Don't reorder volatile memory references; it doesn't seem worth
4637 looking for the case where the order is ok anyway. */
4638 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
4641 offset
= const0_rtx
;
4643 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
4644 || (GET_CODE (reg
) == SUBREG
4645 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4646 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
4647 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
4649 || (GET_CODE (reg
) == SUBREG
4650 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4651 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
4656 base_reg
= REGNO (reg
);
4657 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
4658 ? REGNO (operands
[i
])
4659 : REGNO (SUBREG_REG (operands
[i
])));
4664 if (base_reg
!= (int) REGNO (reg
))
4665 /* Not addressed from the same base register. */
4668 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
4669 ? REGNO (operands
[i
])
4670 : REGNO (SUBREG_REG (operands
[i
])));
4671 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
4675 /* If it isn't an integer register, or if it overwrites the
4676 base register but isn't the last insn in the list, then
4677 we can't do this. */
4678 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
4679 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
4682 unsorted_offsets
[i
] = INTVAL (offset
);
4685 /* Not a suitable memory address. */
4689 /* All the useful information has now been extracted from the
4690 operands into unsorted_regs and unsorted_offsets; additionally,
4691 order[0] has been set to the lowest numbered register in the
4692 list. Sort the registers into order, and check that the memory
4693 offsets are ascending and adjacent. */
4695 for (i
= 1; i
< nops
; i
++)
4699 order
[i
] = order
[i
- 1];
4700 for (j
= 0; j
< nops
; j
++)
4701 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
4702 && (order
[i
] == order
[i
- 1]
4703 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
4706 /* Have we found a suitable register? if not, one must be used more
4708 if (order
[i
] == order
[i
- 1])
4711 /* Is the memory address adjacent and ascending? */
4712 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
4720 for (i
= 0; i
< nops
; i
++)
4721 regs
[i
] = unsorted_regs
[order
[i
]];
4723 *load_offset
= unsorted_offsets
[order
[0]];
4726 if (unsorted_offsets
[order
[0]] == 0)
4727 return 1; /* ldmia */
4729 if (unsorted_offsets
[order
[0]] == 4)
4730 return 2; /* ldmib */
4732 if (unsorted_offsets
[order
[nops
- 1]] == 0)
4733 return 3; /* ldmda */
4735 if (unsorted_offsets
[order
[nops
- 1]] == -4)
4736 return 4; /* ldmdb */
4738 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
4739 if the offset isn't small enough. The reason 2 ldrs are faster
4740 is because these ARMs are able to do more than one cache access
4741 in a single cycle. The ARM9 and StrongARM have Harvard caches,
4742 whilst the ARM8 has a double bandwidth cache. This means that
4743 these cores can do both an instruction fetch and a data fetch in
4744 a single cycle, so the trick of calculating the address into a
4745 scratch register (one of the result regs) and then doing a load
4746 multiple actually becomes slower (and no smaller in code size).
4747 That is the transformation
4749 ldr rd1, [rbase + offset]
4750 ldr rd2, [rbase + offset + 4]
4754 add rd1, rbase, offset
4755 ldmia rd1, {rd1, rd2}
4757 produces worse code -- '3 cycles + any stalls on rd2' instead of
4758 '2 cycles + any stalls on rd2'. On ARMs with only one cache
4759 access per cycle, the first sequence could never complete in less
4760 than 6 cycles, whereas the ldm sequence would only take 5 and
4761 would make better use of sequential accesses if not hitting the
4764 We cheat here and test 'arm_ld_sched' which we currently know to
4765 only be true for the ARM8, ARM9 and StrongARM. If this ever
4766 changes, then the test below needs to be reworked. */
4767 if (nops
== 2 && arm_ld_sched
)
4770 /* Can't do it without setting up the offset, only do this if it takes
4771 no more than one insn. */
4772 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
4773 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
4777 emit_ldm_seq (rtx
*operands
, int nops
)
4781 HOST_WIDE_INT offset
;
4785 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
4788 strcpy (buf
, "ldm%?ia\t");
4792 strcpy (buf
, "ldm%?ib\t");
4796 strcpy (buf
, "ldm%?da\t");
4800 strcpy (buf
, "ldm%?db\t");
4805 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
4806 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
4809 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
4810 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
4812 output_asm_insn (buf
, operands
);
4814 strcpy (buf
, "ldm%?ia\t");
4821 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
4822 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
4824 for (i
= 1; i
< nops
; i
++)
4825 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
4826 reg_names
[regs
[i
]]);
4828 strcat (buf
, "}\t%@ phole ldm");
4830 output_asm_insn (buf
, operands
);
4835 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
4836 HOST_WIDE_INT
* load_offset
)
4838 int unsorted_regs
[4];
4839 HOST_WIDE_INT unsorted_offsets
[4];
4844 /* Can only handle 2, 3, or 4 insns at present, though could be easily
4845 extended if required. */
4846 if (nops
< 2 || nops
> 4)
4849 /* Loop over the operands and check that the memory references are
4850 suitable (ie immediate offsets from the same base register). At
4851 the same time, extract the target register, and the memory
4853 for (i
= 0; i
< nops
; i
++)
4858 /* Convert a subreg of a mem into the mem itself. */
4859 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
4860 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
4862 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
4865 /* Don't reorder volatile memory references; it doesn't seem worth
4866 looking for the case where the order is ok anyway. */
4867 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
4870 offset
= const0_rtx
;
4872 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
4873 || (GET_CODE (reg
) == SUBREG
4874 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4875 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
4876 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
4878 || (GET_CODE (reg
) == SUBREG
4879 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4880 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
4885 base_reg
= REGNO (reg
);
4886 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
4887 ? REGNO (operands
[i
])
4888 : REGNO (SUBREG_REG (operands
[i
])));
4893 if (base_reg
!= (int) REGNO (reg
))
4894 /* Not addressed from the same base register. */
4897 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
4898 ? REGNO (operands
[i
])
4899 : REGNO (SUBREG_REG (operands
[i
])));
4900 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
4904 /* If it isn't an integer register, then we can't do this. */
4905 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
4908 unsorted_offsets
[i
] = INTVAL (offset
);
4911 /* Not a suitable memory address. */
4915 /* All the useful information has now been extracted from the
4916 operands into unsorted_regs and unsorted_offsets; additionally,
4917 order[0] has been set to the lowest numbered register in the
4918 list. Sort the registers into order, and check that the memory
4919 offsets are ascending and adjacent. */
4921 for (i
= 1; i
< nops
; i
++)
4925 order
[i
] = order
[i
- 1];
4926 for (j
= 0; j
< nops
; j
++)
4927 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
4928 && (order
[i
] == order
[i
- 1]
4929 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
4932 /* Have we found a suitable register? if not, one must be used more
4934 if (order
[i
] == order
[i
- 1])
4937 /* Is the memory address adjacent and ascending? */
4938 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
4946 for (i
= 0; i
< nops
; i
++)
4947 regs
[i
] = unsorted_regs
[order
[i
]];
4949 *load_offset
= unsorted_offsets
[order
[0]];
4952 if (unsorted_offsets
[order
[0]] == 0)
4953 return 1; /* stmia */
4955 if (unsorted_offsets
[order
[0]] == 4)
4956 return 2; /* stmib */
4958 if (unsorted_offsets
[order
[nops
- 1]] == 0)
4959 return 3; /* stmda */
4961 if (unsorted_offsets
[order
[nops
- 1]] == -4)
4962 return 4; /* stmdb */
4968 emit_stm_seq (rtx
*operands
, int nops
)
4972 HOST_WIDE_INT offset
;
4976 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
4979 strcpy (buf
, "stm%?ia\t");
4983 strcpy (buf
, "stm%?ib\t");
4987 strcpy (buf
, "stm%?da\t");
4991 strcpy (buf
, "stm%?db\t");
4998 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
4999 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5001 for (i
= 1; i
< nops
; i
++)
5002 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5003 reg_names
[regs
[i
]]);
5005 strcat (buf
, "}\t%@ phole stm");
5007 output_asm_insn (buf
, operands
);
5012 multi_register_push (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5014 if (GET_CODE (op
) != PARALLEL
5015 || (GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
5016 || (GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
)
5017 || (XINT (SET_SRC (XVECEXP (op
, 0, 0)), 1) != UNSPEC_PUSH_MULT
))
5023 /* Routines for use in generating RTL. */
5026 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
5027 int write_back
, int unchanging_p
, int in_struct_p
,
5032 int sign
= up
? 1 : -1;
5035 /* XScale has load-store double instructions, but they have stricter
5036 alignment requirements than load-store multiple, so we can not
5039 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5040 the pipeline until completion.
5048 An ldr instruction takes 1-3 cycles, but does not block the
5057 Best case ldr will always win. However, the more ldr instructions
5058 we issue, the less likely we are to be able to schedule them well.
5059 Using ldr instructions also increases code size.
5061 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5062 for counts of 3 or 4 regs. */
5063 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5069 for (i
= 0; i
< count
; i
++)
5071 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, i
* 4 * sign
));
5072 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5073 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5074 MEM_SCALAR_P (mem
) = scalar_p
;
5075 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
5079 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
5087 result
= gen_rtx_PARALLEL (VOIDmode
,
5088 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5091 XVECEXP (result
, 0, 0)
5092 = gen_rtx_SET (GET_MODE (from
), from
,
5093 plus_constant (from
, count
* 4 * sign
));
5098 for (j
= 0; i
< count
; i
++, j
++)
5100 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, j
* 4 * sign
));
5101 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5102 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5103 MEM_SCALAR_P (mem
) = scalar_p
;
5104 XVECEXP (result
, 0, i
)
5105 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
5112 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
5113 int write_back
, int unchanging_p
, int in_struct_p
,
5118 int sign
= up
? 1 : -1;
5121 /* See arm_gen_load_multiple for discussion of
5122 the pros/cons of ldm/stm usage for XScale. */
5123 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5129 for (i
= 0; i
< count
; i
++)
5131 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, i
* 4 * sign
));
5132 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5133 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5134 MEM_SCALAR_P (mem
) = scalar_p
;
5135 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
5139 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
5147 result
= gen_rtx_PARALLEL (VOIDmode
,
5148 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5151 XVECEXP (result
, 0, 0)
5152 = gen_rtx_SET (GET_MODE (to
), to
,
5153 plus_constant (to
, count
* 4 * sign
));
5158 for (j
= 0; i
< count
; i
++, j
++)
5160 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, j
* 4 * sign
));
5161 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5162 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5163 MEM_SCALAR_P (mem
) = scalar_p
;
5165 XVECEXP (result
, 0, i
)
5166 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
5173 arm_gen_movstrqi (rtx
*operands
)
5175 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
5178 rtx st_src
, st_dst
, fin_src
, fin_dst
;
5179 rtx part_bytes_reg
= NULL
;
5181 int dst_unchanging_p
, dst_in_struct_p
, src_unchanging_p
, src_in_struct_p
;
5182 int dst_scalar_p
, src_scalar_p
;
5184 if (GET_CODE (operands
[2]) != CONST_INT
5185 || GET_CODE (operands
[3]) != CONST_INT
5186 || INTVAL (operands
[2]) > 64
5187 || INTVAL (operands
[3]) & 3)
5190 st_dst
= XEXP (operands
[0], 0);
5191 st_src
= XEXP (operands
[1], 0);
5193 dst_unchanging_p
= RTX_UNCHANGING_P (operands
[0]);
5194 dst_in_struct_p
= MEM_IN_STRUCT_P (operands
[0]);
5195 dst_scalar_p
= MEM_SCALAR_P (operands
[0]);
5196 src_unchanging_p
= RTX_UNCHANGING_P (operands
[1]);
5197 src_in_struct_p
= MEM_IN_STRUCT_P (operands
[1]);
5198 src_scalar_p
= MEM_SCALAR_P (operands
[1]);
5200 fin_dst
= dst
= copy_to_mode_reg (SImode
, st_dst
);
5201 fin_src
= src
= copy_to_mode_reg (SImode
, st_src
);
5203 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
5204 out_words_to_go
= INTVAL (operands
[2]) / 4;
5205 last_bytes
= INTVAL (operands
[2]) & 3;
5207 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
5208 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
5210 for (i
= 0; in_words_to_go
>= 2; i
+=4)
5212 if (in_words_to_go
> 4)
5213 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
5218 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
5219 FALSE
, src_unchanging_p
,
5220 src_in_struct_p
, src_scalar_p
));
5222 if (out_words_to_go
)
5224 if (out_words_to_go
> 4)
5225 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
5229 else if (out_words_to_go
!= 1)
5230 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
5239 mem
= gen_rtx_MEM (SImode
, dst
);
5240 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5241 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5242 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5243 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
5244 if (last_bytes
!= 0)
5245 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
5249 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
5250 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
5253 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5254 if (out_words_to_go
)
5258 mem
= gen_rtx_MEM (SImode
, src
);
5259 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
5260 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
5261 MEM_SCALAR_P (mem
) = src_scalar_p
;
5262 emit_move_insn (sreg
= gen_reg_rtx (SImode
), mem
);
5263 emit_move_insn (fin_src
= gen_reg_rtx (SImode
), plus_constant (src
, 4));
5265 mem
= gen_rtx_MEM (SImode
, dst
);
5266 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5267 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5268 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5269 emit_move_insn (mem
, sreg
);
5270 emit_move_insn (fin_dst
= gen_reg_rtx (SImode
), plus_constant (dst
, 4));
5273 if (in_words_to_go
) /* Sanity check */
5279 if (in_words_to_go
< 0)
5282 mem
= gen_rtx_MEM (SImode
, src
);
5283 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
5284 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
5285 MEM_SCALAR_P (mem
) = src_scalar_p
;
5286 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
5289 if (last_bytes
&& part_bytes_reg
== NULL
)
5292 if (BYTES_BIG_ENDIAN
&& last_bytes
)
5294 rtx tmp
= gen_reg_rtx (SImode
);
5296 /* The bytes we want are in the top end of the word. */
5297 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
5298 GEN_INT (8 * (4 - last_bytes
))));
5299 part_bytes_reg
= tmp
;
5303 mem
= gen_rtx_MEM (QImode
, plus_constant (dst
, last_bytes
- 1));
5304 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5305 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5306 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5307 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
5311 tmp
= gen_reg_rtx (SImode
);
5312 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
5313 part_bytes_reg
= tmp
;
5322 mem
= gen_rtx_MEM (HImode
, dst
);
5323 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5324 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5325 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5326 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
5330 rtx tmp
= gen_reg_rtx (SImode
);
5332 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (2)));
5333 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
5334 part_bytes_reg
= tmp
;
5340 mem
= gen_rtx_MEM (QImode
, dst
);
5341 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5342 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5343 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5344 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
5351 /* Generate a memory reference for a half word, such that it will be loaded
5352 into the top 16 bits of the word. We can assume that the address is
5353 known to be alignable and of the form reg, or plus (reg, const). */
5356 arm_gen_rotated_half_load (rtx memref
)
5358 HOST_WIDE_INT offset
= 0;
5359 rtx base
= XEXP (memref
, 0);
5361 if (GET_CODE (base
) == PLUS
)
5363 offset
= INTVAL (XEXP (base
, 1));
5364 base
= XEXP (base
, 0);
5367 /* If we aren't allowed to generate unaligned addresses, then fail. */
5368 if (TARGET_MMU_TRAPS
5369 && ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 0)))
5372 base
= gen_rtx_MEM (SImode
, plus_constant (base
, offset
& ~2));
5374 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 2))
5377 return gen_rtx_ROTATE (SImode
, base
, GEN_INT (16));
5380 /* Select a dominance comparison mode if possible for a test of the general
5381 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
5382 COND_OR == DOM_CC_X_AND_Y => (X && Y)
5383 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
5384 COND_OR == DOM_CC_X_OR_Y => (X || Y)
5385 In all cases OP will be either EQ or NE, but we don't need to know which
5386 here. If we are unable to support a dominance comparison we return
5387 CC mode. This will then fail to match for the RTL expressions that
5388 generate this call. */
5390 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
5392 enum rtx_code cond1
, cond2
;
5395 /* Currently we will probably get the wrong result if the individual
5396 comparisons are not simple. This also ensures that it is safe to
5397 reverse a comparison if necessary. */
5398 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
5400 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
5404 /* The if_then_else variant of this tests the second condition if the
5405 first passes, but is true if the first fails. Reverse the first
5406 condition to get a true "inclusive-or" expression. */
5407 if (cond_or
== DOM_CC_NX_OR_Y
)
5408 cond1
= reverse_condition (cond1
);
5410 /* If the comparisons are not equal, and one doesn't dominate the other,
5411 then we can't do this. */
5413 && !comparison_dominates_p (cond1
, cond2
)
5414 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
5419 enum rtx_code temp
= cond1
;
5427 if (cond2
== EQ
|| cond_or
== DOM_CC_X_AND_Y
)
5432 case LE
: return CC_DLEmode
;
5433 case LEU
: return CC_DLEUmode
;
5434 case GE
: return CC_DGEmode
;
5435 case GEU
: return CC_DGEUmode
;
5442 if (cond2
== LT
|| cond_or
== DOM_CC_X_AND_Y
)
5451 if (cond2
== GT
|| cond_or
== DOM_CC_X_AND_Y
)
5460 if (cond2
== LTU
|| cond_or
== DOM_CC_X_AND_Y
)
5469 if (cond2
== GTU
|| cond_or
== DOM_CC_X_AND_Y
)
5477 /* The remaining cases only occur when both comparisons are the
5502 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
5504 /* All floating point compares return CCFP if it is an equality
5505 comparison, and CCFPE otherwise. */
5506 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5535 /* A compare with a shifted operand. Because of canonicalization, the
5536 comparison will have to be swapped when we emit the assembler. */
5537 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
5538 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
5539 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
5540 || GET_CODE (x
) == ROTATERT
))
5543 /* This is a special case that is used by combine to allow a
5544 comparison of a shifted byte load to be split into a zero-extend
5545 followed by a comparison of the shifted integer (only valid for
5546 equalities and unsigned inequalities). */
5547 if (GET_MODE (x
) == SImode
5548 && GET_CODE (x
) == ASHIFT
5549 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
5550 && GET_CODE (XEXP (x
, 0)) == SUBREG
5551 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
5552 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
5553 && (op
== EQ
|| op
== NE
5554 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
5555 && GET_CODE (y
) == CONST_INT
)
5558 /* A construct for a conditional compare, if the false arm contains
5559 0, then both conditions must be true, otherwise either condition
5560 must be true. Not all conditions are possible, so CCmode is
5561 returned if it can't be done. */
5562 if (GET_CODE (x
) == IF_THEN_ELSE
5563 && (XEXP (x
, 2) == const0_rtx
5564 || XEXP (x
, 2) == const1_rtx
)
5565 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
5566 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
5567 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
5568 INTVAL (XEXP (x
, 2)));
5570 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
5571 if (GET_CODE (x
) == AND
5572 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
5573 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
5574 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
5577 if (GET_CODE (x
) == IOR
5578 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
5579 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
5580 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
5583 /* An operation that sets the condition codes as a side-effect, the
5584 V flag is not set correctly, so we can only use comparisons where
5585 this doesn't matter. (For LT and GE we can use "mi" and "pl"
5587 if (GET_MODE (x
) == SImode
5589 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
5590 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
5591 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
5592 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
5593 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
5594 || GET_CODE (x
) == LSHIFTRT
5595 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
5596 || GET_CODE (x
) == ROTATERT
|| GET_CODE (x
) == ZERO_EXTRACT
))
5599 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
5602 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
5603 && GET_CODE (x
) == PLUS
5604 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
5610 /* X and Y are two things to compare using CODE. Emit the compare insn and
5611 return the rtx for register 0 in the proper mode. FP means this is a
5612 floating point compare: I don't think that it is needed on the arm. */
5614 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
5616 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
5617 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
5619 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
5620 gen_rtx_COMPARE (mode
, x
, y
)));
5625 /* Generate a sequence of insns that will generate the correct return
5626 address mask depending on the physical architecture that the program
5629 arm_gen_return_addr_mask (void)
5631 rtx reg
= gen_reg_rtx (Pmode
);
5633 emit_insn (gen_return_addr_mask (reg
));
5638 arm_reload_in_hi (rtx
*operands
)
5640 rtx ref
= operands
[1];
5642 HOST_WIDE_INT offset
= 0;
5644 if (GET_CODE (ref
) == SUBREG
)
5646 offset
= SUBREG_BYTE (ref
);
5647 ref
= SUBREG_REG (ref
);
5650 if (GET_CODE (ref
) == REG
)
5652 /* We have a pseudo which has been spilt onto the stack; there
5653 are two cases here: the first where there is a simple
5654 stack-slot replacement and a second where the stack-slot is
5655 out of range, or is used as a subreg. */
5656 if (reg_equiv_mem
[REGNO (ref
)])
5658 ref
= reg_equiv_mem
[REGNO (ref
)];
5659 base
= find_replacement (&XEXP (ref
, 0));
5662 /* The slot is out of range, or was dressed up in a SUBREG. */
5663 base
= reg_equiv_address
[REGNO (ref
)];
5666 base
= find_replacement (&XEXP (ref
, 0));
5668 /* Handle the case where the address is too complex to be offset by 1. */
5669 if (GET_CODE (base
) == MINUS
5670 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
5672 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5674 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
5677 else if (GET_CODE (base
) == PLUS
)
5679 /* The addend must be CONST_INT, or we would have dealt with it above. */
5680 HOST_WIDE_INT hi
, lo
;
5682 offset
+= INTVAL (XEXP (base
, 1));
5683 base
= XEXP (base
, 0);
5685 /* Rework the address into a legal sequence of insns. */
5686 /* Valid range for lo is -4095 -> 4095 */
5689 : -((-offset
) & 0xfff));
5691 /* Corner case, if lo is the max offset then we would be out of range
5692 once we have added the additional 1 below, so bump the msb into the
5693 pre-loading insn(s). */
5697 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
5698 ^ (HOST_WIDE_INT
) 0x80000000)
5699 - (HOST_WIDE_INT
) 0x80000000);
5701 if (hi
+ lo
!= offset
)
5706 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5708 /* Get the base address; addsi3 knows how to handle constants
5709 that require more than one insn. */
5710 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
5716 /* Operands[2] may overlap operands[0] (though it won't overlap
5717 operands[1]), that's why we asked for a DImode reg -- so we can
5718 use the bit that does not overlap. */
5719 if (REGNO (operands
[2]) == REGNO (operands
[0]))
5720 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5722 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
5724 emit_insn (gen_zero_extendqisi2 (scratch
,
5725 gen_rtx_MEM (QImode
,
5726 plus_constant (base
,
5728 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
5729 gen_rtx_MEM (QImode
,
5730 plus_constant (base
,
5732 if (!BYTES_BIG_ENDIAN
)
5733 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
5734 gen_rtx_IOR (SImode
,
5737 gen_rtx_SUBREG (SImode
, operands
[0], 0),
5741 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
5742 gen_rtx_IOR (SImode
,
5743 gen_rtx_ASHIFT (SImode
, scratch
,
5745 gen_rtx_SUBREG (SImode
, operands
[0],
5749 /* Handle storing a half-word to memory during reload by synthesizing as two
5750 byte stores. Take care not to clobber the input values until after we
5751 have moved them somewhere safe. This code assumes that if the DImode
5752 scratch in operands[2] overlaps either the input value or output address
5753 in some way, then that value must die in this insn (we absolutely need
5754 two scratch registers for some corner cases). */
5756 arm_reload_out_hi (rtx
*operands
)
5758 rtx ref
= operands
[0];
5759 rtx outval
= operands
[1];
5761 HOST_WIDE_INT offset
= 0;
5763 if (GET_CODE (ref
) == SUBREG
)
5765 offset
= SUBREG_BYTE (ref
);
5766 ref
= SUBREG_REG (ref
);
5769 if (GET_CODE (ref
) == REG
)
5771 /* We have a pseudo which has been spilt onto the stack; there
5772 are two cases here: the first where there is a simple
5773 stack-slot replacement and a second where the stack-slot is
5774 out of range, or is used as a subreg. */
5775 if (reg_equiv_mem
[REGNO (ref
)])
5777 ref
= reg_equiv_mem
[REGNO (ref
)];
5778 base
= find_replacement (&XEXP (ref
, 0));
5781 /* The slot is out of range, or was dressed up in a SUBREG. */
5782 base
= reg_equiv_address
[REGNO (ref
)];
5785 base
= find_replacement (&XEXP (ref
, 0));
5787 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
5789 /* Handle the case where the address is too complex to be offset by 1. */
5790 if (GET_CODE (base
) == MINUS
5791 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
5793 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5795 /* Be careful not to destroy OUTVAL. */
5796 if (reg_overlap_mentioned_p (base_plus
, outval
))
5798 /* Updating base_plus might destroy outval, see if we can
5799 swap the scratch and base_plus. */
5800 if (!reg_overlap_mentioned_p (scratch
, outval
))
5803 scratch
= base_plus
;
5808 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
5810 /* Be conservative and copy OUTVAL into the scratch now,
5811 this should only be necessary if outval is a subreg
5812 of something larger than a word. */
5813 /* XXX Might this clobber base? I can't see how it can,
5814 since scratch is known to overlap with OUTVAL, and
5815 must be wider than a word. */
5816 emit_insn (gen_movhi (scratch_hi
, outval
));
5817 outval
= scratch_hi
;
5821 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
5824 else if (GET_CODE (base
) == PLUS
)
5826 /* The addend must be CONST_INT, or we would have dealt with it above. */
5827 HOST_WIDE_INT hi
, lo
;
5829 offset
+= INTVAL (XEXP (base
, 1));
5830 base
= XEXP (base
, 0);
5832 /* Rework the address into a legal sequence of insns. */
5833 /* Valid range for lo is -4095 -> 4095 */
5836 : -((-offset
) & 0xfff));
5838 /* Corner case, if lo is the max offset then we would be out of range
5839 once we have added the additional 1 below, so bump the msb into the
5840 pre-loading insn(s). */
5844 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
5845 ^ (HOST_WIDE_INT
) 0x80000000)
5846 - (HOST_WIDE_INT
) 0x80000000);
5848 if (hi
+ lo
!= offset
)
5853 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5855 /* Be careful not to destroy OUTVAL. */
5856 if (reg_overlap_mentioned_p (base_plus
, outval
))
5858 /* Updating base_plus might destroy outval, see if we
5859 can swap the scratch and base_plus. */
5860 if (!reg_overlap_mentioned_p (scratch
, outval
))
5863 scratch
= base_plus
;
5868 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
5870 /* Be conservative and copy outval into scratch now,
5871 this should only be necessary if outval is a
5872 subreg of something larger than a word. */
5873 /* XXX Might this clobber base? I can't see how it
5874 can, since scratch is known to overlap with
5876 emit_insn (gen_movhi (scratch_hi
, outval
));
5877 outval
= scratch_hi
;
5881 /* Get the base address; addsi3 knows how to handle constants
5882 that require more than one insn. */
5883 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
5889 if (BYTES_BIG_ENDIAN
)
5891 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
5892 plus_constant (base
, offset
+ 1)),
5893 gen_lowpart (QImode
, outval
)));
5894 emit_insn (gen_lshrsi3 (scratch
,
5895 gen_rtx_SUBREG (SImode
, outval
, 0),
5897 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
5898 gen_lowpart (QImode
, scratch
)));
5902 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
5903 gen_lowpart (QImode
, outval
)));
5904 emit_insn (gen_lshrsi3 (scratch
,
5905 gen_rtx_SUBREG (SImode
, outval
, 0),
5907 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
5908 plus_constant (base
, offset
+ 1)),
5909 gen_lowpart (QImode
, scratch
)));
5913 /* Print a symbolic form of X to the debug file, F. */
5915 arm_print_value (FILE *f
, rtx x
)
5917 switch (GET_CODE (x
))
5920 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
5924 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
5932 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
5934 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
5935 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
5943 fprintf (f
, "\"%s\"", XSTR (x
, 0));
5947 fprintf (f
, "`%s'", XSTR (x
, 0));
5951 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
5955 arm_print_value (f
, XEXP (x
, 0));
5959 arm_print_value (f
, XEXP (x
, 0));
5961 arm_print_value (f
, XEXP (x
, 1));
5969 fprintf (f
, "????");
5974 /* Routines for manipulation of the constant pool. */
5976 /* Arm instructions cannot load a large constant directly into a
5977 register; they have to come from a pc relative load. The constant
5978 must therefore be placed in the addressable range of the pc
5979 relative load. Depending on the precise pc relative load
5980 instruction the range is somewhere between 256 bytes and 4k. This
5981 means that we often have to dump a constant inside a function, and
5982 generate code to branch around it.
5984 It is important to minimize this, since the branches will slow
5985 things down and make the code larger.
5987 Normally we can hide the table after an existing unconditional
5988 branch so that there is no interruption of the flow, but in the
5989 worst case the code looks like this:
6007 We fix this by performing a scan after scheduling, which notices
6008 which instructions need to have their operands fetched from the
6009 constant table and builds the table.
6011 The algorithm starts by building a table of all the constants that
6012 need fixing up and all the natural barriers in the function (places
6013 where a constant table can be dropped without breaking the flow).
6014 For each fixup we note how far the pc-relative replacement will be
6015 able to reach and the offset of the instruction into the function.
6017 Having built the table we then group the fixes together to form
6018 tables that are as large as possible (subject to addressing
6019 constraints) and emit each table of constants after the last
6020 barrier that is within range of all the instructions in the group.
6021 If a group does not contain a barrier, then we forcibly create one
6022 by inserting a jump instruction into the flow. Once the table has
6023 been inserted, the insns are then modified to reference the
6024 relevant entry in the pool.
6026 Possible enhancements to the algorithm (not implemented) are:
6028 1) For some processors and object formats, there may be benefit in
6029 aligning the pools to the start of cache lines; this alignment
6030 would need to be taken into account when calculating addressability
6033 /* These typedefs are located at the start of this file, so that
6034 they can be used in the prototypes there. This comment is to
6035 remind readers of that fact so that the following structures
6036 can be understood more easily.
6038 typedef struct minipool_node Mnode;
6039 typedef struct minipool_fixup Mfix; */
6041 struct minipool_node
6043 /* Doubly linked chain of entries. */
6046 /* The maximum offset into the code that this entry can be placed. While
6047 pushing fixes for forward references, all entries are sorted in order
6048 of increasing max_address. */
6049 HOST_WIDE_INT max_address
;
6050 /* Similarly for an entry inserted for a backwards ref. */
6051 HOST_WIDE_INT min_address
;
6052 /* The number of fixes referencing this entry. This can become zero
6053 if we "unpush" an entry. In this case we ignore the entry when we
6054 come to emit the code. */
6056 /* The offset from the start of the minipool. */
6057 HOST_WIDE_INT offset
;
6058 /* The value in table. */
6060 /* The mode of value. */
6061 enum machine_mode mode
;
6062 /* The size of the value. With iWMMXt enabled
6063 sizes > 4 also imply an alignment of 8-bytes. */
6067 struct minipool_fixup
6071 HOST_WIDE_INT address
;
6073 enum machine_mode mode
;
6077 HOST_WIDE_INT forwards
;
6078 HOST_WIDE_INT backwards
;
6081 /* Fixes less than a word need padding out to a word boundary. */
6082 #define MINIPOOL_FIX_SIZE(mode) \
6083 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6085 static Mnode
* minipool_vector_head
;
6086 static Mnode
* minipool_vector_tail
;
6087 static rtx minipool_vector_label
;
6089 /* The linked list of all minipool fixes required for this function. */
6090 Mfix
* minipool_fix_head
;
6091 Mfix
* minipool_fix_tail
;
6092 /* The fix entry for the current minipool, once it has been placed. */
6093 Mfix
* minipool_barrier
;
6095 /* Determines if INSN is the start of a jump table. Returns the end
6096 of the TABLE or NULL_RTX. */
6098 is_jump_table (rtx insn
)
6102 if (GET_CODE (insn
) == JUMP_INSN
6103 && JUMP_LABEL (insn
) != NULL
6104 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
6105 == next_real_insn (insn
))
6107 && GET_CODE (table
) == JUMP_INSN
6108 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
6109 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
6115 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6116 #define JUMP_TABLES_IN_TEXT_SECTION 0
6119 static HOST_WIDE_INT
6120 get_jump_table_size (rtx insn
)
6122 /* ADDR_VECs only take room if read-only data does into the text
6124 if (JUMP_TABLES_IN_TEXT_SECTION
6125 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6130 rtx body
= PATTERN (insn
);
6131 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
6133 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
6139 /* Move a minipool fix MP from its current location to before MAX_MP.
6140 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6141 contrains may need updating. */
6143 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
6144 HOST_WIDE_INT max_address
)
6146 /* This should never be true and the code below assumes these are
6153 if (max_address
< mp
->max_address
)
6154 mp
->max_address
= max_address
;
6158 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
6159 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
6161 mp
->max_address
= max_address
;
6163 /* Unlink MP from its current position. Since max_mp is non-null,
6164 mp->prev must be non-null. */
6165 mp
->prev
->next
= mp
->next
;
6166 if (mp
->next
!= NULL
)
6167 mp
->next
->prev
= mp
->prev
;
6169 minipool_vector_tail
= mp
->prev
;
6171 /* Re-insert it before MAX_MP. */
6173 mp
->prev
= max_mp
->prev
;
6176 if (mp
->prev
!= NULL
)
6177 mp
->prev
->next
= mp
;
6179 minipool_vector_head
= mp
;
6182 /* Save the new entry. */
6185 /* Scan over the preceding entries and adjust their addresses as
6187 while (mp
->prev
!= NULL
6188 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
6190 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
6197 /* Add a constant to the minipool for a forward reference. Returns the
6198 node added or NULL if the constant will not fit in this pool. */
6200 add_minipool_forward_ref (Mfix
*fix
)
6202 /* If set, max_mp is the first pool_entry that has a lower
6203 constraint than the one we are trying to add. */
6204 Mnode
* max_mp
= NULL
;
6205 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
6208 /* If this fix's address is greater than the address of the first
6209 entry, then we can't put the fix in this pool. We subtract the
6210 size of the current fix to ensure that if the table is fully
6211 packed we still have enough room to insert this value by suffling
6212 the other fixes forwards. */
6213 if (minipool_vector_head
&&
6214 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
6217 /* Scan the pool to see if a constant with the same value has
6218 already been added. While we are doing this, also note the
6219 location where we must insert the constant if it doesn't already
6221 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6223 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
6224 && fix
->mode
== mp
->mode
6225 && (GET_CODE (fix
->value
) != CODE_LABEL
6226 || (CODE_LABEL_NUMBER (fix
->value
)
6227 == CODE_LABEL_NUMBER (mp
->value
)))
6228 && rtx_equal_p (fix
->value
, mp
->value
))
6230 /* More than one fix references this entry. */
6232 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
6235 /* Note the insertion point if necessary. */
6237 && mp
->max_address
> max_address
)
6240 /* If we are inserting an 8-bytes aligned quantity and
6241 we have not already found an insertion point, then
6242 make sure that all such 8-byte aligned quantities are
6243 placed at the start of the pool. */
6244 if (TARGET_REALLY_IWMMXT
6246 && fix
->fix_size
== 8
6247 && mp
->fix_size
!= 8)
6250 max_address
= mp
->max_address
;
6254 /* The value is not currently in the minipool, so we need to create
6255 a new entry for it. If MAX_MP is NULL, the entry will be put on
6256 the end of the list since the placement is less constrained than
6257 any existing entry. Otherwise, we insert the new fix before
6258 MAX_MP and, if necessary, adjust the constraints on the other
6260 mp
= xmalloc (sizeof (* mp
));
6261 mp
->fix_size
= fix
->fix_size
;
6262 mp
->mode
= fix
->mode
;
6263 mp
->value
= fix
->value
;
6265 /* Not yet required for a backwards ref. */
6266 mp
->min_address
= -65536;
6270 mp
->max_address
= max_address
;
6272 mp
->prev
= minipool_vector_tail
;
6274 if (mp
->prev
== NULL
)
6276 minipool_vector_head
= mp
;
6277 minipool_vector_label
= gen_label_rtx ();
6280 mp
->prev
->next
= mp
;
6282 minipool_vector_tail
= mp
;
6286 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
6287 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
6289 mp
->max_address
= max_address
;
6292 mp
->prev
= max_mp
->prev
;
6294 if (mp
->prev
!= NULL
)
6295 mp
->prev
->next
= mp
;
6297 minipool_vector_head
= mp
;
6300 /* Save the new entry. */
6303 /* Scan over the preceding entries and adjust their addresses as
6305 while (mp
->prev
!= NULL
6306 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
6308 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
6316 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
6317 HOST_WIDE_INT min_address
)
6319 HOST_WIDE_INT offset
;
6321 /* This should never be true, and the code below assumes these are
6328 if (min_address
> mp
->min_address
)
6329 mp
->min_address
= min_address
;
6333 /* We will adjust this below if it is too loose. */
6334 mp
->min_address
= min_address
;
6336 /* Unlink MP from its current position. Since min_mp is non-null,
6337 mp->next must be non-null. */
6338 mp
->next
->prev
= mp
->prev
;
6339 if (mp
->prev
!= NULL
)
6340 mp
->prev
->next
= mp
->next
;
6342 minipool_vector_head
= mp
->next
;
6344 /* Reinsert it after MIN_MP. */
6346 mp
->next
= min_mp
->next
;
6348 if (mp
->next
!= NULL
)
6349 mp
->next
->prev
= mp
;
6351 minipool_vector_tail
= mp
;
6357 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6359 mp
->offset
= offset
;
6360 if (mp
->refcount
> 0)
6361 offset
+= mp
->fix_size
;
6363 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
6364 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
6370 /* Add a constant to the minipool for a backward reference. Returns the
6371 node added or NULL if the constant will not fit in this pool.
6373 Note that the code for insertion for a backwards reference can be
6374 somewhat confusing because the calculated offsets for each fix do
6375 not take into account the size of the pool (which is still under
6378 add_minipool_backward_ref (Mfix
*fix
)
6380 /* If set, min_mp is the last pool_entry that has a lower constraint
6381 than the one we are trying to add. */
6382 Mnode
*min_mp
= NULL
;
6383 /* This can be negative, since it is only a constraint. */
6384 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
6387 /* If we can't reach the current pool from this insn, or if we can't
6388 insert this entry at the end of the pool without pushing other
6389 fixes out of range, then we don't try. This ensures that we
6390 can't fail later on. */
6391 if (min_address
>= minipool_barrier
->address
6392 || (minipool_vector_tail
->min_address
+ fix
->fix_size
6393 >= minipool_barrier
->address
))
6396 /* Scan the pool to see if a constant with the same value has
6397 already been added. While we are doing this, also note the
6398 location where we must insert the constant if it doesn't already
6400 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
6402 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
6403 && fix
->mode
== mp
->mode
6404 && (GET_CODE (fix
->value
) != CODE_LABEL
6405 || (CODE_LABEL_NUMBER (fix
->value
)
6406 == CODE_LABEL_NUMBER (mp
->value
)))
6407 && rtx_equal_p (fix
->value
, mp
->value
)
6408 /* Check that there is enough slack to move this entry to the
6409 end of the table (this is conservative). */
6411 > (minipool_barrier
->address
6412 + minipool_vector_tail
->offset
6413 + minipool_vector_tail
->fix_size
)))
6416 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
6420 mp
->min_address
+= fix
->fix_size
;
6423 /* Note the insertion point if necessary. */
6424 if (mp
->min_address
< min_address
)
6426 /* For now, we do not allow the insertion of 8-byte alignment
6427 requiring nodes anywhere but at the start of the pool. */
6428 if (TARGET_REALLY_IWMMXT
&& fix
->fix_size
== 8 && mp
->fix_size
!= 8)
6433 else if (mp
->max_address
6434 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
6436 /* Inserting before this entry would push the fix beyond
6437 its maximum address (which can happen if we have
6438 re-located a forwards fix); force the new fix to come
6441 min_address
= mp
->min_address
+ fix
->fix_size
;
6443 /* If we are inserting an 8-bytes aligned quantity and
6444 we have not already found an insertion point, then
6445 make sure that all such 8-byte aligned quantities are
6446 placed at the start of the pool. */
6447 else if (TARGET_REALLY_IWMMXT
6449 && fix
->fix_size
== 8
6450 && mp
->fix_size
< 8)
6453 min_address
= mp
->min_address
+ fix
->fix_size
;
6458 /* We need to create a new entry. */
6459 mp
= xmalloc (sizeof (* mp
));
6460 mp
->fix_size
= fix
->fix_size
;
6461 mp
->mode
= fix
->mode
;
6462 mp
->value
= fix
->value
;
6464 mp
->max_address
= minipool_barrier
->address
+ 65536;
6466 mp
->min_address
= min_address
;
6471 mp
->next
= minipool_vector_head
;
6473 if (mp
->next
== NULL
)
6475 minipool_vector_tail
= mp
;
6476 minipool_vector_label
= gen_label_rtx ();
6479 mp
->next
->prev
= mp
;
6481 minipool_vector_head
= mp
;
6485 mp
->next
= min_mp
->next
;
6489 if (mp
->next
!= NULL
)
6490 mp
->next
->prev
= mp
;
6492 minipool_vector_tail
= mp
;
6495 /* Save the new entry. */
6503 /* Scan over the following entries and adjust their offsets. */
6504 while (mp
->next
!= NULL
)
6506 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
6507 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
6510 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
6512 mp
->next
->offset
= mp
->offset
;
6521 assign_minipool_offsets (Mfix
*barrier
)
6523 HOST_WIDE_INT offset
= 0;
6526 minipool_barrier
= barrier
;
6528 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6530 mp
->offset
= offset
;
6532 if (mp
->refcount
> 0)
6533 offset
+= mp
->fix_size
;
6537 /* Output the literal table */
6539 dump_minipool (rtx scan
)
6545 if (TARGET_REALLY_IWMMXT
)
6546 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6547 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
6554 fprintf (rtl_dump_file
,
6555 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
6556 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
6558 scan
= emit_label_after (gen_label_rtx (), scan
);
6559 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
6560 scan
= emit_label_after (minipool_vector_label
, scan
);
6562 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
6564 if (mp
->refcount
> 0)
6568 fprintf (rtl_dump_file
,
6569 ";; Offset %u, min %ld, max %ld ",
6570 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
6571 (unsigned long) mp
->max_address
);
6572 arm_print_value (rtl_dump_file
, mp
->value
);
6573 fputc ('\n', rtl_dump_file
);
6576 switch (mp
->fix_size
)
6578 #ifdef HAVE_consttable_1
6580 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
6584 #ifdef HAVE_consttable_2
6586 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
6590 #ifdef HAVE_consttable_4
6592 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
6596 #ifdef HAVE_consttable_8
6598 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
6612 minipool_vector_head
= minipool_vector_tail
= NULL
;
6613 scan
= emit_insn_after (gen_consttable_end (), scan
);
6614 scan
= emit_barrier_after (scan
);
6617 /* Return the cost of forcibly inserting a barrier after INSN. */
6619 arm_barrier_cost (rtx insn
)
6621 /* Basing the location of the pool on the loop depth is preferable,
6622 but at the moment, the basic block information seems to be
6623 corrupt by this stage of the compilation. */
6625 rtx next
= next_nonnote_insn (insn
);
6627 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
6630 switch (GET_CODE (insn
))
6633 /* It will always be better to place the table before the label, rather
6642 return base_cost
- 10;
6645 return base_cost
+ 10;
6649 /* Find the best place in the insn stream in the range
6650 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
6651 Create the barrier by inserting a jump and add a new fix entry for
6654 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
6656 HOST_WIDE_INT count
= 0;
6658 rtx from
= fix
->insn
;
6659 rtx selected
= from
;
6661 HOST_WIDE_INT selected_address
;
6663 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
6664 rtx label
= gen_label_rtx ();
6666 selected_cost
= arm_barrier_cost (from
);
6667 selected_address
= fix
->address
;
6669 while (from
&& count
< max_count
)
6674 /* This code shouldn't have been called if there was a natural barrier
6676 if (GET_CODE (from
) == BARRIER
)
6679 /* Count the length of this insn. */
6680 count
+= get_attr_length (from
);
6682 /* If there is a jump table, add its length. */
6683 tmp
= is_jump_table (from
);
6686 count
+= get_jump_table_size (tmp
);
6688 /* Jump tables aren't in a basic block, so base the cost on
6689 the dispatch insn. If we select this location, we will
6690 still put the pool after the table. */
6691 new_cost
= arm_barrier_cost (from
);
6693 if (count
< max_count
&& new_cost
<= selected_cost
)
6696 selected_cost
= new_cost
;
6697 selected_address
= fix
->address
+ count
;
6700 /* Continue after the dispatch table. */
6701 from
= NEXT_INSN (tmp
);
6705 new_cost
= arm_barrier_cost (from
);
6707 if (count
< max_count
&& new_cost
<= selected_cost
)
6710 selected_cost
= new_cost
;
6711 selected_address
= fix
->address
+ count
;
6714 from
= NEXT_INSN (from
);
6717 /* Create a new JUMP_INSN that branches around a barrier. */
6718 from
= emit_jump_insn_after (gen_jump (label
), selected
);
6719 JUMP_LABEL (from
) = label
;
6720 barrier
= emit_barrier_after (from
);
6721 emit_label_after (label
, barrier
);
6723 /* Create a minipool barrier entry for the new barrier. */
6724 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
6725 new_fix
->insn
= barrier
;
6726 new_fix
->address
= selected_address
;
6727 new_fix
->next
= fix
->next
;
6728 fix
->next
= new_fix
;
6733 /* Record that there is a natural barrier in the insn stream at
6736 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
6738 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
6741 fix
->address
= address
;
6744 if (minipool_fix_head
!= NULL
)
6745 minipool_fix_tail
->next
= fix
;
6747 minipool_fix_head
= fix
;
6749 minipool_fix_tail
= fix
;
6752 /* Record INSN, which will need fixing up to load a value from the
6753 minipool. ADDRESS is the offset of the insn since the start of the
6754 function; LOC is a pointer to the part of the insn which requires
6755 fixing; VALUE is the constant that must be loaded, which is of type
6758 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
6759 enum machine_mode mode
, rtx value
)
6761 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
6763 #ifdef AOF_ASSEMBLER
6764 /* PIC symbol refereneces need to be converted into offsets into the
6766 /* XXX This shouldn't be done here. */
6767 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
6768 value
= aof_pic_entry (value
);
6769 #endif /* AOF_ASSEMBLER */
6772 fix
->address
= address
;
6775 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
6777 fix
->forwards
= get_attr_pool_range (insn
);
6778 fix
->backwards
= get_attr_neg_pool_range (insn
);
6779 fix
->minipool
= NULL
;
6781 /* If an insn doesn't have a range defined for it, then it isn't
6782 expecting to be reworked by this code. Better to abort now than
6783 to generate duff assembly code. */
6784 if (fix
->forwards
== 0 && fix
->backwards
== 0)
6787 /* With iWMMXt enabled, the pool is aligned to an 8-byte boundary.
6788 So there might be an empty word before the start of the pool.
6789 Hence we reduce the forward range by 4 to allow for this
6791 if (TARGET_REALLY_IWMMXT
&& fix
->fix_size
== 8)
6796 fprintf (rtl_dump_file
,
6797 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
6798 GET_MODE_NAME (mode
),
6799 INSN_UID (insn
), (unsigned long) address
,
6800 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
6801 arm_print_value (rtl_dump_file
, fix
->value
);
6802 fprintf (rtl_dump_file
, "\n");
6805 /* Add it to the chain of fixes. */
6808 if (minipool_fix_head
!= NULL
)
6809 minipool_fix_tail
->next
= fix
;
6811 minipool_fix_head
= fix
;
6813 minipool_fix_tail
= fix
;
6816 /* Scan INSN and note any of its operands that need fixing.
6817 If DO_PUSHES is false we do not actually push any of the fixups
6818 needed. The function returns TRUE is any fixups were needed/pushed.
6819 This is used by arm_memory_load_p() which needs to know about loads
6820 of constants that will be converted into minipool loads. */
6822 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
6824 bool result
= false;
6827 extract_insn (insn
);
6829 if (!constrain_operands (1))
6830 fatal_insn_not_found (insn
);
6832 /* Fill in recog_op_alt with information about the constraints of this insn. */
6833 preprocess_constraints ();
6835 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
6837 /* Things we need to fix can only occur in inputs. */
6838 if (recog_data
.operand_type
[opno
] != OP_IN
)
6841 /* If this alternative is a memory reference, then any mention
6842 of constants in this alternative is really to fool reload
6843 into allowing us to accept one there. We need to fix them up
6844 now so that we output the right code. */
6845 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
6847 rtx op
= recog_data
.operand
[opno
];
6849 if (CONSTANT_P (op
))
6852 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
6853 recog_data
.operand_mode
[opno
], op
);
6856 else if (GET_CODE (op
) == MEM
6857 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
6858 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
6861 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
6862 recog_data
.operand_mode
[opno
],
6863 get_pool_constant (XEXP (op
, 0)));
6873 /* Gcc puts the pool in the wrong place for ARM, since we can only
6874 load addresses a limited distance around the pc. We do some
6875 special munging to move the constant pool values to the correct
6876 point in the code. */
6881 HOST_WIDE_INT address
= 0;
6884 minipool_fix_head
= minipool_fix_tail
= NULL
;
6886 /* The first insn must always be a note, or the code below won't
6887 scan it properly. */
6888 insn
= get_insns ();
6889 if (GET_CODE (insn
) != NOTE
)
6892 /* Scan all the insns and record the operands that will need fixing. */
6893 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
6895 if (TARGET_CIRRUS_FIX_INVALID_INSNS
6896 && (arm_cirrus_insn_p (insn
)
6897 || GET_CODE (insn
) == JUMP_INSN
6898 || arm_memory_load_p (insn
)))
6899 cirrus_reorg (insn
);
6901 if (GET_CODE (insn
) == BARRIER
)
6902 push_minipool_barrier (insn
, address
);
6903 else if (INSN_P (insn
))
6907 note_invalid_constants (insn
, address
, true);
6908 address
+= get_attr_length (insn
);
6910 /* If the insn is a vector jump, add the size of the table
6911 and skip the table. */
6912 if ((table
= is_jump_table (insn
)) != NULL
)
6914 address
+= get_jump_table_size (table
);
6920 fix
= minipool_fix_head
;
6922 /* Now scan the fixups and perform the required changes. */
6927 Mfix
* last_added_fix
;
6928 Mfix
* last_barrier
= NULL
;
6931 /* Skip any further barriers before the next fix. */
6932 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
6935 /* No more fixes. */
6939 last_added_fix
= NULL
;
6941 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
6943 if (GET_CODE (ftmp
->insn
) == BARRIER
)
6945 if (ftmp
->address
>= minipool_vector_head
->max_address
)
6948 last_barrier
= ftmp
;
6950 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
6953 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
6956 /* If we found a barrier, drop back to that; any fixes that we
6957 could have reached but come after the barrier will now go in
6958 the next mini-pool. */
6959 if (last_barrier
!= NULL
)
6961 /* Reduce the refcount for those fixes that won't go into this
6963 for (fdel
= last_barrier
->next
;
6964 fdel
&& fdel
!= ftmp
;
6967 fdel
->minipool
->refcount
--;
6968 fdel
->minipool
= NULL
;
6971 ftmp
= last_barrier
;
6975 /* ftmp is first fix that we can't fit into this pool and
6976 there no natural barriers that we could use. Insert a
6977 new barrier in the code somewhere between the previous
6978 fix and this one, and arrange to jump around it. */
6979 HOST_WIDE_INT max_address
;
6981 /* The last item on the list of fixes must be a barrier, so
6982 we can never run off the end of the list of fixes without
6983 last_barrier being set. */
6987 max_address
= minipool_vector_head
->max_address
;
6988 /* Check that there isn't another fix that is in range that
6989 we couldn't fit into this pool because the pool was
6990 already too large: we need to put the pool before such an
6992 if (ftmp
->address
< max_address
)
6993 max_address
= ftmp
->address
;
6995 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
6998 assign_minipool_offsets (last_barrier
);
7002 if (GET_CODE (ftmp
->insn
) != BARRIER
7003 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
7010 /* Scan over the fixes we have identified for this pool, fixing them
7011 up and adding the constants to the pool itself. */
7012 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
7013 this_fix
= this_fix
->next
)
7014 if (GET_CODE (this_fix
->insn
) != BARRIER
)
7017 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
7018 minipool_vector_label
),
7019 this_fix
->minipool
->offset
);
7020 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
7023 dump_minipool (last_barrier
->insn
);
7027 /* From now on we must synthesize any constants that we can't handle
7028 directly. This can happen if the RTL gets split during final
7029 instruction generation. */
7030 after_arm_reorg
= 1;
7032 /* Free the minipool memory. */
7033 obstack_free (&minipool_obstack
, minipool_startobj
);
7036 /* Routines to output assembly language. */
7038 /* If the rtx is the correct value then return the string of the number.
7039 In this way we can ensure that valid double constants are generated even
7040 when cross compiling. */
7042 fp_immediate_constant (rtx x
)
7047 if (!fpa_consts_inited
)
7050 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
7051 for (i
= 0; i
< 8; i
++)
7052 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
7053 return strings_fpa
[i
];
7058 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7060 fp_const_from_val (REAL_VALUE_TYPE
*r
)
7064 if (!fpa_consts_inited
)
7067 for (i
= 0; i
< 8; i
++)
7068 if (REAL_VALUES_EQUAL (*r
, values_fpa
[i
]))
7069 return strings_fpa
[i
];
7074 /* Output the operands of a LDM/STM instruction to STREAM.
7075 MASK is the ARM register set mask of which only bits 0-15 are important.
7076 REG is the base register, either the frame pointer or the stack pointer,
7077 INSTR is the possibly suffixed load or store instruction. */
7079 print_multi_reg (FILE *stream
, const char *instr
, int reg
, int mask
)
7082 int not_first
= FALSE
;
7084 fputc ('\t', stream
);
7085 asm_fprintf (stream
, instr
, reg
);
7086 fputs (", {", stream
);
7088 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7089 if (mask
& (1 << i
))
7092 fprintf (stream
, ", ");
7094 asm_fprintf (stream
, "%r", i
);
7098 fprintf (stream
, "}");
7100 /* Add a ^ character for the 26-bit ABI, but only if we were loading
7101 the PC. Otherwise we would generate an UNPREDICTABLE instruction.
7102 Strictly speaking the instruction would be unpredicatble only if
7103 we were writing back the base register as well, but since we never
7104 want to generate an LDM type 2 instruction (register bank switching)
7105 which is what you get if the PC is not being loaded, we do not need
7106 to check for writeback. */
7107 if (! TARGET_APCS_32
7108 && ((mask
& (1 << PC_REGNUM
)) != 0))
7109 fprintf (stream
, "^");
7111 fprintf (stream
, "\n");
7114 /* Output a 'call' insn. */
7116 output_call (rtx
*operands
)
7118 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
7120 if (REGNO (operands
[0]) == LR_REGNUM
)
7122 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
7123 output_asm_insn ("mov%?\t%0, %|lr", operands
);
7126 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7128 if (TARGET_INTERWORK
)
7129 output_asm_insn ("bx%?\t%0", operands
);
7131 output_asm_insn ("mov%?\t%|pc, %0", operands
);
7136 /* Output a 'call' insn that is a reference in memory. */
7138 output_call_mem (rtx
*operands
)
7140 if (TARGET_INTERWORK
)
7142 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
7143 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7144 output_asm_insn ("bx%?\t%|ip", operands
);
7146 else if (regno_use_in (LR_REGNUM
, operands
[0]))
7148 /* LR is used in the memory address. We load the address in the
7149 first instruction. It's safe to use IP as the target of the
7150 load since the call will kill it anyway. */
7151 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
7152 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7153 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
7157 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7158 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
7165 /* Output a move from arm registers to an fpa registers.
7166 OPERANDS[0] is an fpa register.
7167 OPERANDS[1] is the first registers of an arm register pair. */
7169 output_mov_long_double_fpa_from_arm (rtx
*operands
)
7171 int arm_reg0
= REGNO (operands
[1]);
7174 if (arm_reg0
== IP_REGNUM
)
7177 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7178 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7179 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
7181 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
7182 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
7187 /* Output a move from an fpa register to arm registers.
7188 OPERANDS[0] is the first registers of an arm register pair.
7189 OPERANDS[1] is an fpa register. */
7191 output_mov_long_double_arm_from_fpa (rtx
*operands
)
7193 int arm_reg0
= REGNO (operands
[0]);
7196 if (arm_reg0
== IP_REGNUM
)
7199 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7200 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7201 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
7203 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
7204 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
7208 /* Output a move from arm registers to arm registers of a long double
7209 OPERANDS[0] is the destination.
7210 OPERANDS[1] is the source. */
7212 output_mov_long_double_arm_from_arm (rtx
*operands
)
7214 /* We have to be careful here because the two might overlap. */
7215 int dest_start
= REGNO (operands
[0]);
7216 int src_start
= REGNO (operands
[1]);
7220 if (dest_start
< src_start
)
7222 for (i
= 0; i
< 3; i
++)
7224 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
7225 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
7226 output_asm_insn ("mov%?\t%0, %1", ops
);
7231 for (i
= 2; i
>= 0; i
--)
7233 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
7234 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
7235 output_asm_insn ("mov%?\t%0, %1", ops
);
7243 /* Output a move from arm registers to an fpa registers.
7244 OPERANDS[0] is an fpa register.
7245 OPERANDS[1] is the first registers of an arm register pair. */
7247 output_mov_double_fpa_from_arm (rtx
*operands
)
7249 int arm_reg0
= REGNO (operands
[1]);
7252 if (arm_reg0
== IP_REGNUM
)
7255 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7256 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7257 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
7258 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
7262 /* Output a move from an fpa register to arm registers.
7263 OPERANDS[0] is the first registers of an arm register pair.
7264 OPERANDS[1] is an fpa register. */
7266 output_mov_double_arm_from_fpa (rtx
*operands
)
7268 int arm_reg0
= REGNO (operands
[0]);
7271 if (arm_reg0
== IP_REGNUM
)
7274 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7275 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7276 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
7277 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
7281 /* Output a move between double words.
7282 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
7283 or MEM<-REG and all MEMs must be offsettable addresses. */
7285 output_move_double (rtx
*operands
)
7287 enum rtx_code code0
= GET_CODE (operands
[0]);
7288 enum rtx_code code1
= GET_CODE (operands
[1]);
7293 int reg0
= REGNO (operands
[0]);
7295 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
7299 int reg1
= REGNO (operands
[1]);
7300 if (reg1
== IP_REGNUM
)
7303 /* Ensure the second source is not overwritten. */
7304 if (reg1
== reg0
+ (WORDS_BIG_ENDIAN
? -1 : 1))
7305 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands
);
7307 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands
);
7309 else if (code1
== CONST_VECTOR
)
7311 HOST_WIDE_INT hint
= 0;
7313 switch (GET_MODE (operands
[1]))
7316 otherops
[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands
[1], 1)));
7317 operands
[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands
[1], 0)));
7321 if (BYTES_BIG_ENDIAN
)
7323 hint
= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
7325 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
7329 hint
= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
7331 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
7334 otherops
[1] = GEN_INT (hint
);
7337 if (BYTES_BIG_ENDIAN
)
7339 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
7341 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
7345 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
7347 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
7350 operands
[1] = GEN_INT (hint
);
7354 if (BYTES_BIG_ENDIAN
)
7356 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 4));
7358 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 5));
7360 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 6));
7362 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 7));
7366 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 7));
7368 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 6));
7370 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 5));
7372 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 4));
7375 otherops
[1] = GEN_INT (hint
);
7378 if (BYTES_BIG_ENDIAN
)
7380 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
7382 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
7384 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
7386 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
7390 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
7392 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
7394 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
7396 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
7399 operands
[1] = GEN_INT (hint
);
7405 output_mov_immediate (operands
);
7406 output_mov_immediate (otherops
);
7408 else if (code1
== CONST_DOUBLE
)
7410 if (GET_MODE (operands
[1]) == DFmode
)
7415 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
7416 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
7417 otherops
[1] = GEN_INT (l
[1]);
7418 operands
[1] = GEN_INT (l
[0]);
7420 else if (GET_MODE (operands
[1]) != VOIDmode
)
7422 else if (WORDS_BIG_ENDIAN
)
7424 otherops
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
7425 operands
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
7429 otherops
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
7430 operands
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
7433 output_mov_immediate (operands
);
7434 output_mov_immediate (otherops
);
7436 else if (code1
== CONST_INT
)
7438 #if HOST_BITS_PER_WIDE_INT > 32
7439 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
7440 what the upper word is. */
7441 if (WORDS_BIG_ENDIAN
)
7443 otherops
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
7444 operands
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
7448 otherops
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
7449 operands
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
7452 /* Sign extend the intval into the high-order word. */
7453 if (WORDS_BIG_ENDIAN
)
7455 otherops
[1] = operands
[1];
7456 operands
[1] = (INTVAL (operands
[1]) < 0
7457 ? constm1_rtx
: const0_rtx
);
7460 otherops
[1] = INTVAL (operands
[1]) < 0 ? constm1_rtx
: const0_rtx
;
7462 output_mov_immediate (otherops
);
7463 output_mov_immediate (operands
);
7465 else if (code1
== MEM
)
7467 switch (GET_CODE (XEXP (operands
[1], 0)))
7470 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
7474 abort (); /* Should never happen now. */
7478 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
7482 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
7486 abort (); /* Should never happen now. */
7491 output_asm_insn ("adr%?\t%0, %1", operands
);
7492 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
7496 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
7497 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
7499 otherops
[0] = operands
[0];
7500 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
7501 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
7503 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
7505 if (GET_CODE (otherops
[2]) == CONST_INT
)
7507 switch ((int) INTVAL (otherops
[2]))
7510 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
7513 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
7516 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
7520 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
7521 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
7523 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
7526 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
7529 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
7531 return "ldm%?ia\t%0, %M0";
7535 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
7536 /* Take care of overlapping base/data reg. */
7537 if (reg_mentioned_p (operands
[0], operands
[1]))
7539 output_asm_insn ("ldr%?\t%0, %1", otherops
);
7540 output_asm_insn ("ldr%?\t%0, %1", operands
);
7544 output_asm_insn ("ldr%?\t%0, %1", operands
);
7545 output_asm_insn ("ldr%?\t%0, %1", otherops
);
7551 abort (); /* Constraints should prevent this. */
7553 else if (code0
== MEM
&& code1
== REG
)
7555 if (REGNO (operands
[1]) == IP_REGNUM
)
7558 switch (GET_CODE (XEXP (operands
[0], 0)))
7561 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
7565 abort (); /* Should never happen now. */
7569 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
7573 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
7577 abort (); /* Should never happen now. */
7581 if (GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == CONST_INT
)
7583 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
7586 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
7590 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
7594 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
7601 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
7602 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
7603 output_asm_insn ("str%?\t%1, %0", operands
);
7604 output_asm_insn ("str%?\t%1, %0", otherops
);
7608 /* Constraints should prevent this. */
7615 /* Output an arbitrary MOV reg, #n.
7616 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
7618 output_mov_immediate (rtx
*operands
)
7620 HOST_WIDE_INT n
= INTVAL (operands
[1]);
7622 /* Try to use one MOV. */
7623 if (const_ok_for_arm (n
))
7624 output_asm_insn ("mov%?\t%0, %1", operands
);
7626 /* Try to use one MVN. */
7627 else if (const_ok_for_arm (~n
))
7629 operands
[1] = GEN_INT (~n
);
7630 output_asm_insn ("mvn%?\t%0, %1", operands
);
7637 /* If all else fails, make it out of ORRs or BICs as appropriate. */
7638 for (i
= 0; i
< 32; i
++)
7642 if (n_ones
> 16) /* Shorter to use MVN with BIC in this case. */
7643 output_multi_immediate (operands
, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n
);
7645 output_multi_immediate (operands
, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n
);
7651 /* Output an ADD r, s, #n where n may be too big for one instruction.
7652 If adding zero to one register, output nothing. */
7654 output_add_immediate (rtx
*operands
)
7656 HOST_WIDE_INT n
= INTVAL (operands
[2]);
7658 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
7661 output_multi_immediate (operands
,
7662 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
7665 output_multi_immediate (operands
,
7666 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
7673 /* Output a multiple immediate operation.
7674 OPERANDS is the vector of operands referred to in the output patterns.
7675 INSTR1 is the output pattern to use for the first constant.
7676 INSTR2 is the output pattern to use for subsequent constants.
7677 IMMED_OP is the index of the constant slot in OPERANDS.
7678 N is the constant value. */
7680 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
7681 int immed_op
, HOST_WIDE_INT n
)
7683 #if HOST_BITS_PER_WIDE_INT > 32
7689 /* Quick and easy output. */
7690 operands
[immed_op
] = const0_rtx
;
7691 output_asm_insn (instr1
, operands
);
7696 const char * instr
= instr1
;
7698 /* Note that n is never zero here (which would give no output). */
7699 for (i
= 0; i
< 32; i
+= 2)
7703 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
7704 output_asm_insn (instr
, operands
);
7714 /* Return the appropriate ARM instruction for the operation code.
7715 The returned result should not be overwritten. OP is the rtx of the
7716 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
7719 arithmetic_instr (rtx op
, int shift_first_arg
)
7721 switch (GET_CODE (op
))
7727 return shift_first_arg
? "rsb" : "sub";
7743 /* Ensure valid constant shifts and return the appropriate shift mnemonic
7744 for the operation code. The returned result should not be overwritten.
7745 OP is the rtx code of the shift.
7746 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
7749 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
7752 enum rtx_code code
= GET_CODE (op
);
7754 if (GET_CODE (XEXP (op
, 1)) == REG
|| GET_CODE (XEXP (op
, 1)) == SUBREG
)
7756 else if (GET_CODE (XEXP (op
, 1)) == CONST_INT
)
7757 *amountp
= INTVAL (XEXP (op
, 1));
7780 /* We never have to worry about the amount being other than a
7781 power of 2, since this case can never be reloaded from a reg. */
7783 *amountp
= int_log2 (*amountp
);
7794 /* This is not 100% correct, but follows from the desire to merge
7795 multiplication by a power of 2 with the recognizer for a
7796 shift. >=32 is not a valid shift for "asl", so we must try and
7797 output a shift that produces the correct arithmetical result.
7798 Using lsr #32 is identical except for the fact that the carry bit
7799 is not set correctly if we set the flags; but we never use the
7800 carry bit from such an operation, so we can ignore that. */
7801 if (code
== ROTATERT
)
7802 /* Rotate is just modulo 32. */
7804 else if (*amountp
!= (*amountp
& 31))
7811 /* Shifts of 0 are no-ops. */
7819 /* Obtain the shift from the POWER of two. */
7821 static HOST_WIDE_INT
7822 int_log2 (HOST_WIDE_INT power
)
7824 HOST_WIDE_INT shift
= 0;
7826 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
7836 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
7837 /bin/as is horribly restrictive. */
7838 #define MAX_ASCII_LEN 51
7841 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
7846 fputs ("\t.ascii\t\"", stream
);
7848 for (i
= 0; i
< len
; i
++)
7852 if (len_so_far
>= MAX_ASCII_LEN
)
7854 fputs ("\"\n\t.ascii\t\"", stream
);
7861 fputs ("\\t", stream
);
7866 fputs ("\\f", stream
);
7871 fputs ("\\b", stream
);
7876 fputs ("\\r", stream
);
7880 case TARGET_NEWLINE
:
7881 fputs ("\\n", stream
);
7883 if ((c
>= ' ' && c
<= '~')
7885 /* This is a good place for a line break. */
7886 len_so_far
= MAX_ASCII_LEN
;
7893 putc ('\\', stream
);
7898 if (c
>= ' ' && c
<= '~')
7905 fprintf (stream
, "\\%03o", c
);
7912 fputs ("\"\n", stream
);
7915 /* Compute the register sabe mask for registers 0 through 12
7916 inclusive. This code is used by both arm_compute_save_reg_mask
7917 and arm_compute_initial_elimination_offset. */
7918 static unsigned long
7919 arm_compute_save_reg0_reg12_mask (void)
7921 unsigned long func_type
= arm_current_func_type ();
7922 unsigned int save_reg_mask
= 0;
7925 if (IS_INTERRUPT (func_type
))
7927 unsigned int max_reg
;
7928 /* Interrupt functions must not corrupt any registers,
7929 even call clobbered ones. If this is a leaf function
7930 we can just examine the registers used by the RTL, but
7931 otherwise we have to assume that whatever function is
7932 called might clobber anything, and so we have to save
7933 all the call-clobbered registers as well. */
7934 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
7935 /* FIQ handlers have registers r8 - r12 banked, so
7936 we only need to check r0 - r7, Normal ISRs only
7937 bank r14 and r15, so we must check up to r12.
7938 r13 is the stack pointer which is always preserved,
7939 so we do not need to consider it here. */
7944 for (reg
= 0; reg
<= max_reg
; reg
++)
7945 if (regs_ever_live
[reg
]
7946 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
7947 save_reg_mask
|= (1 << reg
);
7951 /* In the normal case we only need to save those registers
7952 which are call saved and which are used by this function. */
7953 for (reg
= 0; reg
<= 10; reg
++)
7954 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
7955 save_reg_mask
|= (1 << reg
);
7957 /* Handle the frame pointer as a special case. */
7958 if (! TARGET_APCS_FRAME
7959 && ! frame_pointer_needed
7960 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
7961 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
7962 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
7964 /* If we aren't loading the PIC register,
7965 don't stack it even though it may be live. */
7967 && ! TARGET_SINGLE_PIC_BASE
7968 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
7969 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
7972 return save_reg_mask
;
7975 /* Compute a bit mask of which registers need to be
7976 saved on the stack for the current function. */
7978 static unsigned long
7979 arm_compute_save_reg_mask (void)
7981 unsigned int save_reg_mask
= 0;
7982 unsigned long func_type
= arm_current_func_type ();
7984 if (IS_NAKED (func_type
))
7985 /* This should never really happen. */
7988 /* If we are creating a stack frame, then we must save the frame pointer,
7989 IP (which will hold the old stack pointer), LR and the PC. */
7990 if (frame_pointer_needed
)
7992 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
7997 /* Volatile functions do not return, so there
7998 is no need to save any other registers. */
7999 if (IS_VOLATILE (func_type
))
8000 return save_reg_mask
;
8002 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
8004 /* Decide if we need to save the link register.
8005 Interrupt routines have their own banked link register,
8006 so they never need to save it.
8007 Otherwise if we do not use the link register we do not need to save
8008 it. If we are pushing other registers onto the stack however, we
8009 can save an instruction in the epilogue by pushing the link register
8010 now and then popping it back into the PC. This incurs extra memory
8011 accesses though, so we only do it when optimizing for size, and only
8012 if we know that we will not need a fancy return sequence. */
8013 if (regs_ever_live
[LR_REGNUM
]
8016 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
))
8017 save_reg_mask
|= 1 << LR_REGNUM
;
8019 if (cfun
->machine
->lr_save_eliminated
)
8020 save_reg_mask
&= ~ (1 << LR_REGNUM
);
8022 if (TARGET_REALLY_IWMMXT
8023 && ((bit_count (save_reg_mask
)
8024 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
8028 /* The total number of registers that are going to be pushed
8029 onto the stack is odd. We need to ensure that the stack
8030 is 64-bit aligned before we start to save iWMMXt registers,
8031 and also before we start to create locals. (A local variable
8032 might be a double or long long which we will load/store using
8033 an iWMMXt instruction). Therefore we need to push another
8034 ARM register, so that the stack will be 64-bit aligned. We
8035 try to avoid using the arg registers (r0 -r3) as they might be
8036 used to pass values in a tail call. */
8037 for (reg
= 4; reg
<= 12; reg
++)
8038 if ((save_reg_mask
& (1 << reg
)) == 0)
8042 save_reg_mask
|= (1 << reg
);
8045 cfun
->machine
->sibcall_blocked
= 1;
8046 save_reg_mask
|= (1 << 3);
8050 return save_reg_mask
;
8053 /* Generate a function exit sequence. If REALLY_RETURN is true, then do
8054 everything bar the final return instruction. */
8056 output_return_instruction (rtx operand
, int really_return
, int reverse
)
8058 char conditional
[10];
8061 unsigned long live_regs_mask
;
8062 unsigned long func_type
;
8064 func_type
= arm_current_func_type ();
8066 if (IS_NAKED (func_type
))
8069 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
8071 /* If this function was declared non-returning, and we have found a tail
8072 call, then we have to trust that the called function won't return. */
8077 /* Otherwise, trap an attempted return by aborting. */
8079 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
8081 assemble_external_libcall (ops
[1]);
8082 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
8088 if (current_function_calls_alloca
&& !really_return
)
8091 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
8093 return_used_this_function
= 1;
8095 live_regs_mask
= arm_compute_save_reg_mask ();
8099 const char * return_reg
;
8101 /* If we do not have any special requirements for function exit
8102 (eg interworking, or ISR) then we can load the return address
8103 directly into the PC. Otherwise we must load it into LR. */
8105 && ! TARGET_INTERWORK
)
8106 return_reg
= reg_names
[PC_REGNUM
];
8108 return_reg
= reg_names
[LR_REGNUM
];
8110 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
8111 /* There are two possible reasons for the IP register being saved.
8112 Either a stack frame was created, in which case IP contains the
8113 old stack pointer, or an ISR routine corrupted it. If this in an
8114 ISR routine then just restore IP, otherwise restore IP into SP. */
8115 if (! IS_INTERRUPT (func_type
))
8117 live_regs_mask
&= ~ (1 << IP_REGNUM
);
8118 live_regs_mask
|= (1 << SP_REGNUM
);
8121 /* On some ARM architectures it is faster to use LDR rather than
8122 LDM to load a single register. On other architectures, the
8123 cost is the same. In 26 bit mode, or for exception handlers,
8124 we have to use LDM to load the PC so that the CPSR is also
8126 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
8128 if (live_regs_mask
== (unsigned int)(1 << reg
))
8131 if (reg
<= LAST_ARM_REGNUM
8132 && (reg
!= LR_REGNUM
8134 || (TARGET_APCS_32
&& ! IS_INTERRUPT (func_type
))))
8136 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
8137 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
8144 /* Generate the load multiple instruction to restore the registers. */
8145 if (frame_pointer_needed
)
8146 sprintf (instr
, "ldm%sea\t%%|fp, {", conditional
);
8147 else if (live_regs_mask
& (1 << SP_REGNUM
))
8148 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
8150 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
8152 p
= instr
+ strlen (instr
);
8154 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
8155 if (live_regs_mask
& (1 << reg
))
8157 int l
= strlen (reg_names
[reg
]);
8163 memcpy (p
, ", ", 2);
8167 memcpy (p
, "%|", 2);
8168 memcpy (p
+ 2, reg_names
[reg
], l
);
8172 if (live_regs_mask
& (1 << LR_REGNUM
))
8174 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
8175 /* Decide if we need to add the ^ symbol to the end of the
8176 register list. This causes the saved condition codes
8177 register to be copied into the current condition codes
8178 register. We do the copy if we are conforming to the 32-bit
8179 ABI and this is an interrupt function, or if we are
8180 conforming to the 26-bit ABI. There is a special case for
8181 the 26-bit ABI however, which is if we are writing back the
8182 stack pointer but not loading the PC. In this case adding
8183 the ^ symbol would create a type 2 LDM instruction, where
8184 writeback is UNPREDICTABLE. We are safe in leaving the ^
8185 character off in this case however, since the actual return
8186 instruction will be a MOVS which will restore the CPSR. */
8187 if ((TARGET_APCS_32
&& IS_INTERRUPT (func_type
))
8188 || (! TARGET_APCS_32
&& really_return
))
8195 output_asm_insn (instr
, & operand
);
8197 /* See if we need to generate an extra instruction to
8198 perform the actual function return. */
8200 && func_type
!= ARM_FT_INTERWORKED
8201 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
8203 /* The return has already been handled
8204 by loading the LR into the PC. */
8211 switch ((int) ARM_FUNC_TYPE (func_type
))
8215 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
8218 case ARM_FT_INTERWORKED
:
8219 sprintf (instr
, "bx%s\t%%|lr", conditional
);
8222 case ARM_FT_EXCEPTION
:
8223 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
8227 /* ARMv5 implementations always provide BX, so interworking
8228 is the default unless APCS-26 is in use. */
8229 if ((insn_flags
& FL_ARCH5
) != 0 && TARGET_APCS_32
)
8230 sprintf (instr
, "bx%s\t%%|lr", conditional
);
8232 sprintf (instr
, "mov%s%s\t%%|pc, %%|lr",
8233 conditional
, TARGET_APCS_32
? "" : "s");
8237 output_asm_insn (instr
, & operand
);
8243 /* Write the function name into the code section, directly preceding
8244 the function prologue.
8246 Code will be output similar to this:
8248 .ascii "arm_poke_function_name", 0
8251 .word 0xff000000 + (t1 - t0)
8252 arm_poke_function_name
8254 stmfd sp!, {fp, ip, lr, pc}
8257 When performing a stack backtrace, code can inspect the value
8258 of 'pc' stored at 'fp' + 0. If the trace function then looks
8259 at location pc - 12 and the top 8 bits are set, then we know
8260 that there is a function name embedded immediately preceding this
8261 location and has length ((pc[-3]) & 0xff000000).
8263 We assume that pc is declared as a pointer to an unsigned long.
8265 It is of no benefit to output the function name if we are assembling
8266 a leaf function. These function types will not contain a stack
8267 backtrace structure, therefore it is not possible to determine the
8270 arm_poke_function_name (FILE *stream
, const char *name
)
8272 unsigned long alignlength
;
8273 unsigned long length
;
8276 length
= strlen (name
) + 1;
8277 alignlength
= ROUND_UP_WORD (length
);
8279 ASM_OUTPUT_ASCII (stream
, name
, length
);
8280 ASM_OUTPUT_ALIGN (stream
, 2);
8281 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
8282 assemble_aligned_integer (UNITS_PER_WORD
, x
);
8285 /* Place some comments into the assembler stream
8286 describing the current function. */
8288 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
8290 unsigned long func_type
;
8294 thumb_output_function_prologue (f
, frame_size
);
8299 if (arm_ccfsm_state
|| arm_target_insn
)
8302 func_type
= arm_current_func_type ();
8304 switch ((int) ARM_FUNC_TYPE (func_type
))
8309 case ARM_FT_INTERWORKED
:
8310 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
8312 case ARM_FT_EXCEPTION_HANDLER
:
8313 asm_fprintf (f
, "\t%@ C++ Exception Handler.\n");
8316 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
8319 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
8321 case ARM_FT_EXCEPTION
:
8322 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
8326 if (IS_NAKED (func_type
))
8327 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
8329 if (IS_VOLATILE (func_type
))
8330 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
8332 if (IS_NESTED (func_type
))
8333 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
8335 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
8336 current_function_args_size
,
8337 current_function_pretend_args_size
, frame_size
);
8339 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
8340 frame_pointer_needed
,
8341 cfun
->machine
->uses_anonymous_args
);
8343 if (cfun
->machine
->lr_save_eliminated
)
8344 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
8346 #ifdef AOF_ASSEMBLER
8348 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
8351 return_used_this_function
= 0;
8355 arm_output_epilogue (int really_return
)
8358 unsigned long saved_regs_mask
;
8359 unsigned long func_type
;
8360 /* Floats_offset is the offset from the "virtual" frame. In an APCS
8361 frame that is $fp + 4 for a non-variadic function. */
8362 int floats_offset
= 0;
8364 int frame_size
= arm_get_frame_size ();
8365 FILE * f
= asm_out_file
;
8366 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
8367 unsigned int lrm_count
= 0;
8369 /* If we have already generated the return instruction
8370 then it is futile to generate anything else. */
8371 if (use_return_insn (FALSE
) && return_used_this_function
)
8374 func_type
= arm_current_func_type ();
8376 if (IS_NAKED (func_type
))
8377 /* Naked functions don't have epilogues. */
8380 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
8384 /* A volatile function should never return. Call abort. */
8385 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
8386 assemble_external_libcall (op
);
8387 output_asm_insn ("bl\t%a0", &op
);
8392 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
8394 /* If we are throwing an exception, then we really must
8395 be doing a return, so we can't tail-call. */
8398 saved_regs_mask
= arm_compute_save_reg_mask ();
8401 lrm_count
= bit_count (saved_regs_mask
);
8403 /* XXX We should adjust floats_offset for any anonymous args, and then
8404 re-adjust vfp_offset below to compensate. */
8406 /* Compute how far away the floats will be. */
8407 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
8408 if (saved_regs_mask
& (1 << reg
))
8411 if (frame_pointer_needed
)
8415 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
8417 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
8418 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8420 floats_offset
+= 12;
8421 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
8422 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
8427 int start_reg
= LAST_ARM_FP_REGNUM
;
8429 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
8431 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8433 floats_offset
+= 12;
8435 /* We can't unstack more than four registers at once. */
8436 if (start_reg
- reg
== 3)
8438 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
8439 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
8440 start_reg
= reg
- 1;
8445 if (reg
!= start_reg
)
8446 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
8447 reg
+ 1, start_reg
- reg
,
8448 FP_REGNUM
, floats_offset
- vfp_offset
);
8449 start_reg
= reg
- 1;
8453 /* Just in case the last register checked also needs unstacking. */
8454 if (reg
!= start_reg
)
8455 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
8456 reg
+ 1, start_reg
- reg
,
8457 FP_REGNUM
, floats_offset
- vfp_offset
);
8462 /* The frame pointer is guaranteed to be non-double-word aligned.
8463 This is because it is set to (old_stack_pointer - 4) and the
8464 old_stack_pointer was double word aligned. Thus the offset to
8465 the iWMMXt registers to be loaded must also be non-double-word
8466 sized, so that the resultant address *is* double-word aligned.
8467 We can ignore floats_offset since that was already included in
8468 the live_regs_mask. */
8469 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
8471 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
8472 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8474 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
8475 reg
, FP_REGNUM
, lrm_count
* 4);
8480 /* saved_regs_mask should contain the IP, which at the time of stack
8481 frame generation actually contains the old stack pointer. So a
8482 quick way to unwind the stack is just pop the IP register directly
8483 into the stack pointer. */
8484 if ((saved_regs_mask
& (1 << IP_REGNUM
)) == 0)
8486 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
8487 saved_regs_mask
|= (1 << SP_REGNUM
);
8489 /* There are two registers left in saved_regs_mask - LR and PC. We
8490 only need to restore the LR register (the return address), but to
8491 save time we can load it directly into the PC, unless we need a
8492 special function exit sequence, or we are not really returning. */
8493 if (really_return
&& ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
)
8494 /* Delete the LR from the register mask, so that the LR on
8495 the stack is loaded into the PC in the register mask. */
8496 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
8498 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
8500 print_multi_reg (f
, "ldmea\t%r", FP_REGNUM
, saved_regs_mask
);
8502 if (IS_INTERRUPT (func_type
))
8503 /* Interrupt handlers will have pushed the
8504 IP onto the stack, so restore it now. */
8505 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
8509 /* Restore stack pointer if necessary. */
8510 if (frame_size
+ current_function_outgoing_args_size
!= 0)
8512 operands
[0] = operands
[1] = stack_pointer_rtx
;
8513 operands
[2] = GEN_INT (frame_size
8514 + current_function_outgoing_args_size
);
8515 output_add_immediate (operands
);
8518 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
8520 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
8521 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8522 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
8527 int start_reg
= FIRST_ARM_FP_REGNUM
;
8529 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
8531 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8533 if (reg
- start_reg
== 3)
8535 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
8536 start_reg
, SP_REGNUM
);
8537 start_reg
= reg
+ 1;
8542 if (reg
!= start_reg
)
8543 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
8544 start_reg
, reg
- start_reg
,
8547 start_reg
= reg
+ 1;
8551 /* Just in case the last register checked also needs unstacking. */
8552 if (reg
!= start_reg
)
8553 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
8554 start_reg
, reg
- start_reg
, SP_REGNUM
);
8558 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
8559 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8560 asm_fprintf (f
, "\twldrd\t%r, [%r, #+8]!\n", reg
, SP_REGNUM
);
8562 /* If we can, restore the LR into the PC. */
8563 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
8565 && current_function_pretend_args_size
== 0
8566 && saved_regs_mask
& (1 << LR_REGNUM
))
8568 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
8569 saved_regs_mask
|= (1 << PC_REGNUM
);
8572 /* Load the registers off the stack. If we only have one register
8573 to load use the LDR instruction - it is faster. */
8574 if (saved_regs_mask
== (1 << LR_REGNUM
))
8576 /* The exception handler ignores the LR, so we do
8577 not really need to load it off the stack. */
8579 asm_fprintf (f
, "\tadd\t%r, %r, #4\n", SP_REGNUM
, SP_REGNUM
);
8581 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
8583 else if (saved_regs_mask
)
8585 if (saved_regs_mask
& (1 << SP_REGNUM
))
8586 /* Note - write back to the stack register is not enabled
8587 (ie "ldmfd sp!..."). We know that the stack pointer is
8588 in the list of registers and if we add writeback the
8589 instruction becomes UNPREDICTABLE. */
8590 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
8592 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
8595 if (current_function_pretend_args_size
)
8597 /* Unwind the pre-pushed regs. */
8598 operands
[0] = operands
[1] = stack_pointer_rtx
;
8599 operands
[2] = GEN_INT (current_function_pretend_args_size
);
8600 output_add_immediate (operands
);
8605 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
)
8606 /* Adjust the stack to remove the exception handler stuff. */
8607 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
8612 || (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
8613 && current_function_pretend_args_size
== 0
8614 && saved_regs_mask
& (1 << PC_REGNUM
)))
8617 /* Generate the return instruction. */
8618 switch ((int) ARM_FUNC_TYPE (func_type
))
8620 case ARM_FT_EXCEPTION_HANDLER
:
8621 /* Even in 26-bit mode we do a mov (rather than a movs)
8622 because we don't have the PSR bits set in the address. */
8623 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, EXCEPTION_LR_REGNUM
);
8628 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
8631 case ARM_FT_EXCEPTION
:
8632 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
8635 case ARM_FT_INTERWORKED
:
8636 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
8640 if (frame_pointer_needed
)
8641 /* If we used the frame pointer then the return address
8642 will have been loaded off the stack directly into the
8643 PC, so there is no need to issue a MOV instruction
8646 else if (current_function_pretend_args_size
== 0
8647 && (saved_regs_mask
& (1 << LR_REGNUM
)))
8648 /* Similarly we may have been able to load LR into the PC
8649 even if we did not create a stack frame. */
8651 else if (TARGET_APCS_32
)
8652 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
8654 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
8662 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
8663 HOST_WIDE_INT frame_size
)
8667 /* ??? Probably not safe to set this here, since it assumes that a
8668 function will be emitted as assembly immediately after we generate
8669 RTL for it. This does not happen for inline functions. */
8670 return_used_this_function
= 0;
8674 /* We need to take into account any stack-frame rounding. */
8675 frame_size
= arm_get_frame_size ();
8677 if (use_return_insn (FALSE
)
8678 && return_used_this_function
8679 && (frame_size
+ current_function_outgoing_args_size
) != 0
8680 && !frame_pointer_needed
)
8683 /* Reset the ARM-specific per-function variables. */
8684 after_arm_reorg
= 0;
8688 /* Generate and emit an insn that we will recognize as a push_multi.
8689 Unfortunately, since this insn does not reflect very well the actual
8690 semantics of the operation, we need to annotate the insn for the benefit
8691 of DWARF2 frame unwind information. */
8693 emit_multi_reg_push (int mask
)
8700 int dwarf_par_index
;
8703 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8704 if (mask
& (1 << i
))
8707 if (num_regs
== 0 || num_regs
> 16)
8710 /* We don't record the PC in the dwarf frame information. */
8711 num_dwarf_regs
= num_regs
;
8712 if (mask
& (1 << PC_REGNUM
))
8715 /* For the body of the insn we are going to generate an UNSPEC in
8716 parallel with several USEs. This allows the insn to be recognized
8717 by the push_multi pattern in the arm.md file. The insn looks
8718 something like this:
8721 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
8722 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
8723 (use (reg:SI 11 fp))
8724 (use (reg:SI 12 ip))
8725 (use (reg:SI 14 lr))
8726 (use (reg:SI 15 pc))
8729 For the frame note however, we try to be more explicit and actually
8730 show each register being stored into the stack frame, plus a (single)
8731 decrement of the stack pointer. We do it this way in order to be
8732 friendly to the stack unwinding code, which only wants to see a single
8733 stack decrement per instruction. The RTL we generate for the note looks
8734 something like this:
8737 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
8738 (set (mem:SI (reg:SI sp)) (reg:SI r4))
8739 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
8740 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
8741 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
8744 This sequence is used both by the code to support stack unwinding for
8745 exceptions handlers and the code to generate dwarf2 frame debugging. */
8747 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
8748 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
8749 dwarf_par_index
= 1;
8751 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8753 if (mask
& (1 << i
))
8755 reg
= gen_rtx_REG (SImode
, i
);
8758 = gen_rtx_SET (VOIDmode
,
8759 gen_rtx_MEM (BLKmode
,
8760 gen_rtx_PRE_DEC (BLKmode
,
8761 stack_pointer_rtx
)),
8762 gen_rtx_UNSPEC (BLKmode
,
8768 tmp
= gen_rtx_SET (VOIDmode
,
8769 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
8771 RTX_FRAME_RELATED_P (tmp
) = 1;
8772 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
8780 for (j
= 1, i
++; j
< num_regs
; i
++)
8782 if (mask
& (1 << i
))
8784 reg
= gen_rtx_REG (SImode
, i
);
8786 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
8790 tmp
= gen_rtx_SET (VOIDmode
,
8791 gen_rtx_MEM (SImode
,
8792 plus_constant (stack_pointer_rtx
,
8795 RTX_FRAME_RELATED_P (tmp
) = 1;
8796 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
8803 par
= emit_insn (par
);
8805 tmp
= gen_rtx_SET (SImode
,
8807 gen_rtx_PLUS (SImode
,
8809 GEN_INT (-4 * num_regs
)));
8810 RTX_FRAME_RELATED_P (tmp
) = 1;
8811 XVECEXP (dwarf
, 0, 0) = tmp
;
8813 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8819 emit_sfm (int base_reg
, int count
)
8826 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8827 dwarf
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8829 reg
= gen_rtx_REG (XFmode
, base_reg
++);
8832 = gen_rtx_SET (VOIDmode
,
8833 gen_rtx_MEM (BLKmode
,
8834 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
8835 gen_rtx_UNSPEC (BLKmode
,
8839 = gen_rtx_SET (VOIDmode
,
8840 gen_rtx_MEM (XFmode
,
8841 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
8843 RTX_FRAME_RELATED_P (tmp
) = 1;
8844 XVECEXP (dwarf
, 0, count
- 1) = tmp
;
8846 for (i
= 1; i
< count
; i
++)
8848 reg
= gen_rtx_REG (XFmode
, base_reg
++);
8849 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8851 tmp
= gen_rtx_SET (VOIDmode
,
8852 gen_rtx_MEM (XFmode
,
8853 gen_rtx_PRE_DEC (BLKmode
,
8854 stack_pointer_rtx
)),
8856 RTX_FRAME_RELATED_P (tmp
) = 1;
8857 XVECEXP (dwarf
, 0, count
- i
- 1) = tmp
;
8860 par
= emit_insn (par
);
8861 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8866 /* Compute the distance from register FROM to register TO.
8867 These can be the arg pointer (26), the soft frame pointer (25),
8868 the stack pointer (13) or the hard frame pointer (11).
8869 Typical stack layout looks like this:
8871 old stack pointer -> | |
8874 | | saved arguments for
8875 | | vararg functions
8878 hard FP & arg pointer -> | | \
8886 soft frame pointer -> | | /
8896 current stack pointer -> | | /
8899 For a given function some or all of these stack components
8900 may not be needed, giving rise to the possibility of
8901 eliminating some of the registers.
8903 The values returned by this function must reflect the behavior
8904 of arm_expand_prologue() and arm_compute_save_reg_mask().
8906 The sign of the number returned reflects the direction of stack
8907 growth, so the values are positive for all eliminations except
8908 from the soft frame pointer to the hard frame pointer. */
8910 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
8912 unsigned int local_vars
= arm_get_frame_size ();
8913 unsigned int outgoing_args
= current_function_outgoing_args_size
;
8914 unsigned int stack_frame
;
8915 unsigned int call_saved_registers
;
8916 unsigned long func_type
;
8918 func_type
= arm_current_func_type ();
8920 /* Volatile functions never return, so there is
8921 no need to save call saved registers. */
8922 call_saved_registers
= 0;
8923 if (! IS_VOLATILE (func_type
))
8925 unsigned int reg_mask
;
8928 /* Make sure that we compute which registers will be saved
8929 on the stack using the same algorithm that is used by
8930 the prologue creation code. */
8931 reg_mask
= arm_compute_save_reg_mask ();
8933 /* Now count the number of bits set in save_reg_mask.
8934 If we have already counted the registers in the stack
8935 frame, do not count them again. Non call-saved registers
8936 might be saved in the call-save area of the stack, if
8937 doing so will preserve the stack's alignment. Hence we
8938 must count them here. For each set bit we need 4 bytes
8940 if (frame_pointer_needed
)
8942 call_saved_registers
+= 4 * bit_count (reg_mask
);
8944 /* If the hard floating point registers are going to be
8945 used then they must be saved on the stack as well.
8946 Each register occupies 12 bytes of stack space. */
8947 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
8948 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
8949 call_saved_registers
+= 12;
8951 if (TARGET_REALLY_IWMMXT
)
8952 /* Check for the call-saved iWMMXt registers. */
8953 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
8954 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
8955 call_saved_registers
+= 8;
8958 /* The stack frame contains 4 registers - the old frame pointer,
8959 the old stack pointer, the return address and PC of the start
8961 stack_frame
= frame_pointer_needed
? 16 : 0;
8963 /* OK, now we have enough information to compute the distances.
8964 There must be an entry in these switch tables for each pair
8965 of registers in ELIMINABLE_REGS, even if some of the entries
8966 seem to be redundant or useless. */
8969 case ARG_POINTER_REGNUM
:
8972 case THUMB_HARD_FRAME_POINTER_REGNUM
:
8975 case FRAME_POINTER_REGNUM
:
8976 /* This is the reverse of the soft frame pointer
8977 to hard frame pointer elimination below. */
8978 if (call_saved_registers
== 0 && stack_frame
== 0)
8980 return (call_saved_registers
+ stack_frame
- 4);
8982 case ARM_HARD_FRAME_POINTER_REGNUM
:
8983 /* If there is no stack frame then the hard
8984 frame pointer and the arg pointer coincide. */
8985 if (stack_frame
== 0 && call_saved_registers
!= 0)
8987 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
8988 return (frame_pointer_needed
8989 && current_function_needs_context
8990 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
8992 case STACK_POINTER_REGNUM
:
8993 /* If nothing has been pushed on the stack at all
8994 then this will return -4. This *is* correct! */
8995 return call_saved_registers
+ stack_frame
+ local_vars
+ outgoing_args
- 4;
9002 case FRAME_POINTER_REGNUM
:
9005 case THUMB_HARD_FRAME_POINTER_REGNUM
:
9008 case ARM_HARD_FRAME_POINTER_REGNUM
:
9009 /* The hard frame pointer points to the top entry in the
9010 stack frame. The soft frame pointer to the bottom entry
9011 in the stack frame. If there is no stack frame at all,
9012 then they are identical. */
9013 if (call_saved_registers
== 0 && stack_frame
== 0)
9015 return - (call_saved_registers
+ stack_frame
- 4);
9017 case STACK_POINTER_REGNUM
:
9018 return local_vars
+ outgoing_args
;
9026 /* You cannot eliminate from the stack pointer.
9027 In theory you could eliminate from the hard frame
9028 pointer to the stack pointer, but this will never
9029 happen, since if a stack frame is not needed the
9030 hard frame pointer will never be used. */
9035 /* Calculate the size of the stack frame, taking into account any
9036 padding that is required to ensure stack-alignment. */
9038 arm_get_frame_size (void)
9042 int base_size
= ROUND_UP_WORD (get_frame_size ());
9044 unsigned long func_type
= arm_current_func_type ();
9053 /* We need to know if we are a leaf function. Unfortunately, it
9054 is possible to be called after start_sequence has been called,
9055 which causes get_insns to return the insns for the sequence,
9056 not the function, which will cause leaf_function_p to return
9057 the incorrect result.
9059 To work around this, we cache the computed frame size. This
9060 works because we will only be calling RTL expanders that need
9061 to know about leaf functions once reload has completed, and the
9062 frame size cannot be changed after that time, so we can safely
9063 use the cached value. */
9065 if (reload_completed
)
9066 return cfun
->machine
->frame_size
;
9068 leaf
= leaf_function_p ();
9070 /* A leaf function does not need any stack alignment if it has nothing
9072 if (leaf
&& base_size
== 0)
9074 cfun
->machine
->frame_size
= 0;
9078 /* We know that SP will be word aligned on entry, and we must
9079 preserve that condition at any subroutine call. But those are
9080 the only constraints. */
9082 /* Space for variadic functions. */
9083 if (current_function_pretend_args_size
)
9084 entry_size
+= current_function_pretend_args_size
;
9086 /* Space for saved registers. */
9087 entry_size
+= bit_count (arm_compute_save_reg_mask ()) * 4;
9089 /* Space for saved FPA registers. */
9090 if (! IS_VOLATILE (func_type
))
9092 for (regno
= FIRST_ARM_FP_REGNUM
; regno
<= LAST_ARM_FP_REGNUM
; regno
++)
9093 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
9097 if (TARGET_REALLY_IWMMXT
)
9099 /* Check for the call-saved iWMMXt registers. */
9100 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
9101 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
9105 if ((entry_size
+ base_size
+ current_function_outgoing_args_size
) & 7)
9107 if ((entry_size
+ base_size
+ current_function_outgoing_args_size
) & 7)
9110 cfun
->machine
->frame_size
= base_size
;
9115 /* Generate the prologue instructions for entry into an ARM function. */
9117 arm_expand_prologue (void)
9123 unsigned long live_regs_mask
;
9124 unsigned long func_type
;
9126 int saved_pretend_args
= 0;
9127 unsigned int args_to_push
;
9129 func_type
= arm_current_func_type ();
9131 /* Naked functions don't have prologues. */
9132 if (IS_NAKED (func_type
))
9135 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
9136 args_to_push
= current_function_pretend_args_size
;
9138 /* Compute which register we will have to save onto the stack. */
9139 live_regs_mask
= arm_compute_save_reg_mask ();
9141 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
9143 if (frame_pointer_needed
)
9145 if (IS_INTERRUPT (func_type
))
9147 /* Interrupt functions must not corrupt any registers.
9148 Creating a frame pointer however, corrupts the IP
9149 register, so we must push it first. */
9150 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
9152 /* Do not set RTX_FRAME_RELATED_P on this insn.
9153 The dwarf stack unwinding code only wants to see one
9154 stack decrement per function, and this is not it. If
9155 this instruction is labeled as being part of the frame
9156 creation sequence then dwarf2out_frame_debug_expr will
9157 abort when it encounters the assignment of IP to FP
9158 later on, since the use of SP here establishes SP as
9159 the CFA register and not IP.
9161 Anyway this instruction is not really part of the stack
9162 frame creation although it is part of the prologue. */
9164 else if (IS_NESTED (func_type
))
9166 /* The Static chain register is the same as the IP register
9167 used as a scratch register during stack frame creation.
9168 To get around this need to find somewhere to store IP
9169 whilst the frame is being created. We try the following
9172 1. The last argument register.
9173 2. A slot on the stack above the frame. (This only
9174 works if the function is not a varargs function).
9175 3. Register r3, after pushing the argument registers
9178 Note - we only need to tell the dwarf2 backend about the SP
9179 adjustment in the second variant; the static chain register
9180 doesn't need to be unwound, as it doesn't contain a value
9181 inherited from the caller. */
9183 if (regs_ever_live
[3] == 0)
9185 insn
= gen_rtx_REG (SImode
, 3);
9186 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
9187 insn
= emit_insn (insn
);
9189 else if (args_to_push
== 0)
9192 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
9193 insn
= gen_rtx_MEM (SImode
, insn
);
9194 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
9195 insn
= emit_insn (insn
);
9199 /* Just tell the dwarf backend that we adjusted SP. */
9200 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
9201 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
9202 GEN_INT (-fp_offset
)));
9203 RTX_FRAME_RELATED_P (insn
) = 1;
9204 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
9205 dwarf
, REG_NOTES (insn
));
9209 /* Store the args on the stack. */
9210 if (cfun
->machine
->uses_anonymous_args
)
9211 insn
= emit_multi_reg_push
9212 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
9215 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9216 GEN_INT (- args_to_push
)));
9218 RTX_FRAME_RELATED_P (insn
) = 1;
9220 saved_pretend_args
= 1;
9221 fp_offset
= args_to_push
;
9224 /* Now reuse r3 to preserve IP. */
9225 insn
= gen_rtx_REG (SImode
, 3);
9226 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
9227 (void) emit_insn (insn
);
9233 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
9234 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
9237 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
9239 insn
= emit_insn (insn
);
9240 RTX_FRAME_RELATED_P (insn
) = 1;
9245 /* Push the argument registers, or reserve space for them. */
9246 if (cfun
->machine
->uses_anonymous_args
)
9247 insn
= emit_multi_reg_push
9248 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
9251 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9252 GEN_INT (- args_to_push
)));
9253 RTX_FRAME_RELATED_P (insn
) = 1;
9256 /* If this is an interrupt service routine, and the link register
9257 is going to be pushed, and we are not creating a stack frame,
9258 (which would involve an extra push of IP and a pop in the epilogue)
9259 subtracting four from LR now will mean that the function return
9260 can be done with a single instruction. */
9261 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
9262 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
9263 && ! frame_pointer_needed
)
9264 emit_insn (gen_rtx_SET (SImode
,
9265 gen_rtx_REG (SImode
, LR_REGNUM
),
9266 gen_rtx_PLUS (SImode
,
9267 gen_rtx_REG (SImode
, LR_REGNUM
),
9272 insn
= emit_multi_reg_push (live_regs_mask
);
9273 RTX_FRAME_RELATED_P (insn
) = 1;
9277 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
9278 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
9280 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
9281 insn
= gen_rtx_MEM (V2SImode
, insn
);
9282 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
9283 gen_rtx_REG (V2SImode
, reg
)));
9284 RTX_FRAME_RELATED_P (insn
) = 1;
9287 if (! IS_VOLATILE (func_type
))
9289 /* Save any floating point call-saved registers used by this
9291 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9293 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
9294 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9296 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
9297 insn
= gen_rtx_MEM (XFmode
, insn
);
9298 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
9299 gen_rtx_REG (XFmode
, reg
)));
9300 RTX_FRAME_RELATED_P (insn
) = 1;
9305 int start_reg
= LAST_ARM_FP_REGNUM
;
9307 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
9309 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9311 if (start_reg
- reg
== 3)
9313 insn
= emit_sfm (reg
, 4);
9314 RTX_FRAME_RELATED_P (insn
) = 1;
9315 start_reg
= reg
- 1;
9320 if (start_reg
!= reg
)
9322 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
9323 RTX_FRAME_RELATED_P (insn
) = 1;
9325 start_reg
= reg
- 1;
9329 if (start_reg
!= reg
)
9331 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
9332 RTX_FRAME_RELATED_P (insn
) = 1;
9337 if (frame_pointer_needed
)
9339 /* Create the new frame pointer. */
9340 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
9341 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
9342 RTX_FRAME_RELATED_P (insn
) = 1;
9344 if (IS_NESTED (func_type
))
9346 /* Recover the static chain register. */
9347 if (regs_ever_live
[3] == 0
9348 || saved_pretend_args
)
9349 insn
= gen_rtx_REG (SImode
, 3);
9350 else /* if (current_function_pretend_args_size == 0) */
9352 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
,
9354 insn
= gen_rtx_MEM (SImode
, insn
);
9357 emit_insn (gen_rtx_SET (SImode
, ip_rtx
, insn
));
9358 /* Add a USE to stop propagate_one_insn() from barfing. */
9359 emit_insn (gen_prologue_use (ip_rtx
));
9363 amount
= GEN_INT (-(arm_get_frame_size ()
9364 + current_function_outgoing_args_size
));
9366 if (amount
!= const0_rtx
)
9368 /* This add can produce multiple insns for a large constant, so we
9369 need to get tricky. */
9370 rtx last
= get_last_insn ();
9371 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9375 last
= last
? NEXT_INSN (last
) : get_insns ();
9376 RTX_FRAME_RELATED_P (last
) = 1;
9378 while (last
!= insn
);
9380 /* If the frame pointer is needed, emit a special barrier that
9381 will prevent the scheduler from moving stores to the frame
9382 before the stack adjustment. */
9383 if (frame_pointer_needed
)
9384 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
9385 hard_frame_pointer_rtx
));
9388 /* If we are profiling, make sure no instructions are scheduled before
9389 the call to mcount. Similarly if the user has requested no
9390 scheduling in the prolog. */
9391 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
9392 emit_insn (gen_blockage ());
9394 /* If the link register is being kept alive, with the return address in it,
9395 then make sure that it does not get reused by the ce2 pass. */
9396 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
9398 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
9399 cfun
->machine
->lr_save_eliminated
= 1;
9403 /* If CODE is 'd', then the X is a condition operand and the instruction
9404 should only be executed if the condition is true.
9405 if CODE is 'D', then the X is a condition operand and the instruction
9406 should only be executed if the condition is false: however, if the mode
9407 of the comparison is CCFPEmode, then always execute the instruction -- we
9408 do this because in these circumstances !GE does not necessarily imply LT;
9409 in these cases the instruction pattern will take care to make sure that
9410 an instruction containing %d will follow, thereby undoing the effects of
9411 doing this instruction unconditionally.
9412 If CODE is 'N' then X is a floating point operand that must be negated
9414 If CODE is 'B' then output a bitwise inverted value of X (a const int).
9415 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
9417 arm_print_operand (FILE *stream
, rtx x
, int code
)
9422 fputs (ASM_COMMENT_START
, stream
);
9426 fputs (user_label_prefix
, stream
);
9430 fputs (REGISTER_PREFIX
, stream
);
9434 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
9436 if (TARGET_THUMB
|| current_insn_predicate
!= NULL
)
9439 fputs (arm_condition_codes
[arm_current_cc
], stream
);
9441 else if (current_insn_predicate
)
9443 enum arm_cond_code code
;
9448 code
= get_arm_condition_code (current_insn_predicate
);
9449 fputs (arm_condition_codes
[code
], stream
);
9456 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
9457 r
= REAL_VALUE_NEGATE (r
);
9458 fprintf (stream
, "%s", fp_const_from_val (&r
));
9463 if (GET_CODE (x
) == CONST_INT
)
9466 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
9467 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
9472 output_addr_const (stream
, x
);
9477 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
9480 /* Truncate Cirrus shift counts. */
9482 if (GET_CODE (x
) == CONST_INT
)
9484 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
9487 arm_print_operand (stream
, x
, 0);
9491 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
9497 const char * shift
= shift_op (x
, &val
);
9501 fprintf (stream
, ", %s ", shift_op (x
, &val
));
9503 arm_print_operand (stream
, XEXP (x
, 1), 0);
9505 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
9510 /* An explanation of the 'Q', 'R' and 'H' register operands:
9512 In a pair of registers containing a DI or DF value the 'Q'
9513 operand returns the register number of the register containing
9514 the least signficant part of the value. The 'R' operand returns
9515 the register number of the register containing the most
9516 significant part of the value.
9518 The 'H' operand returns the higher of the two register numbers.
9519 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
9520 same as the 'Q' operand, since the most signficant part of the
9521 value is held in the lower number register. The reverse is true
9522 on systems where WORDS_BIG_ENDIAN is false.
9524 The purpose of these operands is to distinguish between cases
9525 where the endian-ness of the values is important (for example
9526 when they are added together), and cases where the endian-ness
9527 is irrelevant, but the order of register operations is important.
9528 For example when loading a value from memory into a register
9529 pair, the endian-ness does not matter. Provided that the value
9530 from the lower memory address is put into the lower numbered
9531 register, and the value from the higher address is put into the
9532 higher numbered register, the load will work regardless of whether
9533 the value being loaded is big-wordian or little-wordian. The
9534 order of the two register loads can matter however, if the address
9535 of the memory location is actually held in one of the registers
9536 being overwritten by the load. */
9538 if (REGNO (x
) > LAST_ARM_REGNUM
)
9540 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
9544 if (REGNO (x
) > LAST_ARM_REGNUM
)
9546 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
9550 if (REGNO (x
) > LAST_ARM_REGNUM
)
9552 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
9556 asm_fprintf (stream
, "%r",
9557 GET_CODE (XEXP (x
, 0)) == REG
9558 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
9562 asm_fprintf (stream
, "{%r-%r}",
9564 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
9568 /* CONST_TRUE_RTX means always -- that's the default. */
9569 if (x
== const_true_rtx
)
9573 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
9576 fputs (thumb_condition_code (x
, 0), stream
);
9580 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
9582 if (x
== const_true_rtx
)
9586 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
9587 (get_arm_condition_code (x
))],
9590 fputs (thumb_condition_code (x
, 1), stream
);
9593 /* Cirrus registers can be accessed in a variety of ways:
9594 single floating point (f)
9595 double floating point (d)
9597 64bit integer (dx). */
9598 case 'W': /* Cirrus register in F mode. */
9599 case 'X': /* Cirrus register in D mode. */
9600 case 'Y': /* Cirrus register in FX mode. */
9601 case 'Z': /* Cirrus register in DX mode. */
9602 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
9605 fprintf (stream
, "mv%s%s",
9608 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
9612 /* Print cirrus register in the mode specified by the register's mode. */
9615 int mode
= GET_MODE (x
);
9617 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
9620 fprintf (stream
, "mv%s%s",
9621 mode
== DFmode
? "d"
9622 : mode
== SImode
? "fx"
9623 : mode
== DImode
? "dx"
9624 : "f", reg_names
[REGNO (x
)] + 2);
9630 if (GET_CODE (x
) != REG
9631 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
9632 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
9633 /* Bad value for wCG register number. */
9636 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
9639 /* Print an iWMMXt control register name. */
9641 if (GET_CODE (x
) != CONST_INT
9643 || INTVAL (x
) >= 16)
9644 /* Bad value for wC register number. */
9648 static const char * wc_reg_names
[16] =
9650 "wCID", "wCon", "wCSSF", "wCASF",
9651 "wC4", "wC5", "wC6", "wC7",
9652 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
9653 "wC12", "wC13", "wC14", "wC15"
9656 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
9664 if (GET_CODE (x
) == REG
)
9665 asm_fprintf (stream
, "%r", REGNO (x
));
9666 else if (GET_CODE (x
) == MEM
)
9668 output_memory_reference_mode
= GET_MODE (x
);
9669 output_address (XEXP (x
, 0));
9671 else if (GET_CODE (x
) == CONST_DOUBLE
)
9672 fprintf (stream
, "#%s", fp_immediate_constant (x
));
9673 else if (GET_CODE (x
) == NEG
)
9674 abort (); /* This should never happen now. */
9677 fputc ('#', stream
);
9678 output_addr_const (stream
, x
);
9683 #ifndef AOF_ASSEMBLER
9684 /* Target hook for assembling integer objects. The ARM version needs to
9685 handle word-sized values specially. */
9687 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
9689 if (size
== UNITS_PER_WORD
&& aligned_p
)
9691 fputs ("\t.word\t", asm_out_file
);
9692 output_addr_const (asm_out_file
, x
);
9694 /* Mark symbols as position independent. We only do this in the
9695 .text segment, not in the .data segment. */
9696 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
9697 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
9699 if (GET_CODE (x
) == SYMBOL_REF
9700 && (CONSTANT_POOL_ADDRESS_P (x
)
9701 || ENCODED_SHORT_CALL_ATTR_P (XSTR (x
, 0))))
9702 fputs ("(GOTOFF)", asm_out_file
);
9703 else if (GET_CODE (x
) == LABEL_REF
)
9704 fputs ("(GOTOFF)", asm_out_file
);
9706 fputs ("(GOT)", asm_out_file
);
9708 fputc ('\n', asm_out_file
);
9712 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x
)))
9716 if (GET_CODE (x
) != CONST_VECTOR
)
9719 units
= CONST_VECTOR_NUNITS (x
);
9721 switch (GET_MODE (x
))
9723 case V2SImode
: size
= 4; break;
9724 case V4HImode
: size
= 2; break;
9725 case V8QImode
: size
= 1; break;
9730 for (i
= 0; i
< units
; i
++)
9734 elt
= CONST_VECTOR_ELT (x
, i
);
9736 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
9742 return default_assemble_integer (x
, size
, aligned_p
);
9746 /* A finite state machine takes care of noticing whether or not instructions
9747 can be conditionally executed, and thus decrease execution time and code
9748 size by deleting branch instructions. The fsm is controlled by
9749 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
9751 /* The state of the fsm controlling condition codes are:
9752 0: normal, do nothing special
9753 1: make ASM_OUTPUT_OPCODE not output this instruction
9754 2: make ASM_OUTPUT_OPCODE not output this instruction
9755 3: make instructions conditional
9756 4: make instructions conditional
9758 State transitions (state->state by whom under condition):
9759 0 -> 1 final_prescan_insn if the `target' is a label
9760 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
9761 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
9762 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
9763 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
9764 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
9765 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
9766 (the target insn is arm_target_insn).
9768 If the jump clobbers the conditions then we use states 2 and 4.
9770 A similar thing can be done with conditional return insns.
9772 XXX In case the `target' is an unconditional branch, this conditionalising
9773 of the instructions always reduces code size, but not always execution
9774 time. But then, I want to reduce the code size to somewhere near what
9775 /bin/cc produces. */
9777 /* Returns the index of the ARM condition code string in
9778 `arm_condition_codes'. COMPARISON should be an rtx like
9779 `(eq (...) (...))'. */
9780 static enum arm_cond_code
9781 get_arm_condition_code (rtx comparison
)
9783 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
9785 enum rtx_code comp_code
= GET_CODE (comparison
);
9787 if (GET_MODE_CLASS (mode
) != MODE_CC
)
9788 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
9789 XEXP (comparison
, 1));
9793 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
9794 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
9795 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
9796 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
9797 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
9798 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
9799 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
9800 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
9801 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
9802 case CC_DLTUmode
: code
= ARM_CC
;
9805 if (comp_code
!= EQ
&& comp_code
!= NE
)
9808 if (comp_code
== EQ
)
9809 return ARM_INVERSE_CONDITION_CODE (code
);
9815 case NE
: return ARM_NE
;
9816 case EQ
: return ARM_EQ
;
9817 case GE
: return ARM_PL
;
9818 case LT
: return ARM_MI
;
9825 case NE
: return ARM_NE
;
9826 case EQ
: return ARM_EQ
;
9832 /* These encodings assume that AC=1 in the FPA system control
9833 byte. This allows us to handle all cases except UNEQ and
9837 case GE
: return ARM_GE
;
9838 case GT
: return ARM_GT
;
9839 case LE
: return ARM_LS
;
9840 case LT
: return ARM_MI
;
9841 case NE
: return ARM_NE
;
9842 case EQ
: return ARM_EQ
;
9843 case ORDERED
: return ARM_VC
;
9844 case UNORDERED
: return ARM_VS
;
9845 case UNLT
: return ARM_LT
;
9846 case UNLE
: return ARM_LE
;
9847 case UNGT
: return ARM_HI
;
9848 case UNGE
: return ARM_PL
;
9849 /* UNEQ and LTGT do not have a representation. */
9850 case UNEQ
: /* Fall through. */
9851 case LTGT
: /* Fall through. */
9858 case NE
: return ARM_NE
;
9859 case EQ
: return ARM_EQ
;
9860 case GE
: return ARM_LE
;
9861 case GT
: return ARM_LT
;
9862 case LE
: return ARM_GE
;
9863 case LT
: return ARM_GT
;
9864 case GEU
: return ARM_LS
;
9865 case GTU
: return ARM_CC
;
9866 case LEU
: return ARM_CS
;
9867 case LTU
: return ARM_HI
;
9874 case LTU
: return ARM_CS
;
9875 case GEU
: return ARM_CC
;
9882 case NE
: return ARM_NE
;
9883 case EQ
: return ARM_EQ
;
9884 case GE
: return ARM_GE
;
9885 case GT
: return ARM_GT
;
9886 case LE
: return ARM_LE
;
9887 case LT
: return ARM_LT
;
9888 case GEU
: return ARM_CS
;
9889 case GTU
: return ARM_HI
;
9890 case LEU
: return ARM_LS
;
9891 case LTU
: return ARM_CC
;
9902 arm_final_prescan_insn (rtx insn
)
9904 /* BODY will hold the body of INSN. */
9905 rtx body
= PATTERN (insn
);
9907 /* This will be 1 if trying to repeat the trick, and things need to be
9908 reversed if it appears to fail. */
9911 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
9912 taken are clobbered, even if the rtl suggests otherwise. It also
9913 means that we have to grub around within the jump expression to find
9914 out what the conditions are when the jump isn't taken. */
9915 int jump_clobbers
= 0;
9917 /* If we start with a return insn, we only succeed if we find another one. */
9918 int seeking_return
= 0;
9920 /* START_INSN will hold the insn from where we start looking. This is the
9921 first insn after the following code_label if REVERSE is true. */
9922 rtx start_insn
= insn
;
9924 /* If in state 4, check if the target branch is reached, in order to
9925 change back to state 0. */
9926 if (arm_ccfsm_state
== 4)
9928 if (insn
== arm_target_insn
)
9930 arm_target_insn
= NULL
;
9931 arm_ccfsm_state
= 0;
9936 /* If in state 3, it is possible to repeat the trick, if this insn is an
9937 unconditional branch to a label, and immediately following this branch
9938 is the previous target label which is only used once, and the label this
9939 branch jumps to is not too far off. */
9940 if (arm_ccfsm_state
== 3)
9942 if (simplejump_p (insn
))
9944 start_insn
= next_nonnote_insn (start_insn
);
9945 if (GET_CODE (start_insn
) == BARRIER
)
9947 /* XXX Isn't this always a barrier? */
9948 start_insn
= next_nonnote_insn (start_insn
);
9950 if (GET_CODE (start_insn
) == CODE_LABEL
9951 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
9952 && LABEL_NUSES (start_insn
) == 1)
9957 else if (GET_CODE (body
) == RETURN
)
9959 start_insn
= next_nonnote_insn (start_insn
);
9960 if (GET_CODE (start_insn
) == BARRIER
)
9961 start_insn
= next_nonnote_insn (start_insn
);
9962 if (GET_CODE (start_insn
) == CODE_LABEL
9963 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
9964 && LABEL_NUSES (start_insn
) == 1)
9976 if (arm_ccfsm_state
!= 0 && !reverse
)
9978 if (GET_CODE (insn
) != JUMP_INSN
)
9981 /* This jump might be paralleled with a clobber of the condition codes
9982 the jump should always come first */
9983 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
9984 body
= XVECEXP (body
, 0, 0);
9987 /* If this is a conditional return then we don't want to know */
9988 if (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
9989 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
9990 && (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
9991 || GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
))
9996 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
9997 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
10000 int fail
= FALSE
, succeed
= FALSE
;
10001 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
10002 int then_not_else
= TRUE
;
10003 rtx this_insn
= start_insn
, label
= 0;
10005 /* If the jump cannot be done with one instruction, we cannot
10006 conditionally execute the instruction in the inverse case. */
10007 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
10013 /* Register the insn jumped to. */
10016 if (!seeking_return
)
10017 label
= XEXP (SET_SRC (body
), 0);
10019 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
10020 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
10021 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
10023 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
10024 then_not_else
= FALSE
;
10026 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
10027 seeking_return
= 1;
10028 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
10030 seeking_return
= 1;
10031 then_not_else
= FALSE
;
10036 /* See how many insns this branch skips, and what kind of insns. If all
10037 insns are okay, and the label or unconditional branch to the same
10038 label is not too far away, succeed. */
10039 for (insns_skipped
= 0;
10040 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
10044 this_insn
= next_nonnote_insn (this_insn
);
10048 switch (GET_CODE (this_insn
))
10051 /* Succeed if it is the target label, otherwise fail since
10052 control falls in from somewhere else. */
10053 if (this_insn
== label
)
10057 arm_ccfsm_state
= 2;
10058 this_insn
= next_nonnote_insn (this_insn
);
10061 arm_ccfsm_state
= 1;
10069 /* Succeed if the following insn is the target label.
10071 If return insns are used then the last insn in a function
10072 will be a barrier. */
10073 this_insn
= next_nonnote_insn (this_insn
);
10074 if (this_insn
&& this_insn
== label
)
10078 arm_ccfsm_state
= 2;
10079 this_insn
= next_nonnote_insn (this_insn
);
10082 arm_ccfsm_state
= 1;
10090 /* If using 32-bit addresses the cc is not preserved over
10092 if (TARGET_APCS_32
)
10094 /* Succeed if the following insn is the target label,
10095 or if the following two insns are a barrier and
10096 the target label. */
10097 this_insn
= next_nonnote_insn (this_insn
);
10098 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
10099 this_insn
= next_nonnote_insn (this_insn
);
10101 if (this_insn
&& this_insn
== label
10102 && insns_skipped
< max_insns_skipped
)
10106 arm_ccfsm_state
= 2;
10107 this_insn
= next_nonnote_insn (this_insn
);
10110 arm_ccfsm_state
= 1;
10119 /* If this is an unconditional branch to the same label, succeed.
10120 If it is to another label, do nothing. If it is conditional,
10122 /* XXX Probably, the tests for SET and the PC are
10125 scanbody
= PATTERN (this_insn
);
10126 if (GET_CODE (scanbody
) == SET
10127 && GET_CODE (SET_DEST (scanbody
)) == PC
)
10129 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
10130 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
10132 arm_ccfsm_state
= 2;
10135 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
10138 /* Fail if a conditional return is undesirable (eg on a
10139 StrongARM), but still allow this if optimizing for size. */
10140 else if (GET_CODE (scanbody
) == RETURN
10141 && !use_return_insn (TRUE
)
10144 else if (GET_CODE (scanbody
) == RETURN
10147 arm_ccfsm_state
= 2;
10150 else if (GET_CODE (scanbody
) == PARALLEL
)
10152 switch (get_attr_conds (this_insn
))
10162 fail
= TRUE
; /* Unrecognized jump (eg epilogue). */
10167 /* Instructions using or affecting the condition codes make it
10169 scanbody
= PATTERN (this_insn
);
10170 if (!(GET_CODE (scanbody
) == SET
10171 || GET_CODE (scanbody
) == PARALLEL
)
10172 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
10175 /* A conditional cirrus instruction must be followed by
10176 a non Cirrus instruction. However, since we
10177 conditionalize instructions in this function and by
10178 the time we get here we can't add instructions
10179 (nops), because shorten_branches() has already been
10180 called, we will disable conditionalizing Cirrus
10181 instructions to be safe. */
10182 if (GET_CODE (scanbody
) != USE
10183 && GET_CODE (scanbody
) != CLOBBER
10184 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
10194 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
10195 arm_target_label
= CODE_LABEL_NUMBER (label
);
10196 else if (seeking_return
|| arm_ccfsm_state
== 2)
10198 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
10200 this_insn
= next_nonnote_insn (this_insn
);
10201 if (this_insn
&& (GET_CODE (this_insn
) == BARRIER
10202 || GET_CODE (this_insn
) == CODE_LABEL
))
10207 /* Oh, dear! we ran off the end.. give up */
10208 recog (PATTERN (insn
), insn
, NULL
);
10209 arm_ccfsm_state
= 0;
10210 arm_target_insn
= NULL
;
10213 arm_target_insn
= this_insn
;
10222 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
10224 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
10225 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
10226 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
10227 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
10231 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
10234 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
10238 if (reverse
|| then_not_else
)
10239 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
10242 /* Restore recog_data (getting the attributes of other insns can
10243 destroy this array, but final.c assumes that it remains intact
10244 across this call; since the insn has been recognized already we
10245 call recog direct). */
10246 recog (PATTERN (insn
), insn
, NULL
);
10250 /* Returns true if REGNO is a valid register
10251 for holding a quantity of tyoe MODE. */
10253 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
10255 if (GET_MODE_CLASS (mode
) == MODE_CC
)
10256 return regno
== CC_REGNUM
;
10259 /* For the Thumb we only allow values bigger than SImode in
10260 registers 0 - 6, so that there is always a second low
10261 register available to hold the upper part of the value.
10262 We probably we ought to ensure that the register is the
10263 start of an even numbered register pair. */
10264 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
10266 if (IS_CIRRUS_REGNUM (regno
))
10267 /* We have outlawed SI values in Cirrus registers because they
10268 reside in the lower 32 bits, but SF values reside in the
10269 upper 32 bits. This causes gcc all sorts of grief. We can't
10270 even split the registers into pairs because Cirrus SI values
10271 get sign extended to 64bits-- aldyh. */
10272 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
10274 if (IS_IWMMXT_GR_REGNUM (regno
))
10275 return mode
== SImode
;
10277 if (IS_IWMMXT_REGNUM (regno
))
10278 return VALID_IWMMXT_REG_MODE (mode
);
10280 if (regno
<= LAST_ARM_REGNUM
)
10281 /* We allow any value to be stored in the general regisetrs. */
10284 if ( regno
== FRAME_POINTER_REGNUM
10285 || regno
== ARG_POINTER_REGNUM
)
10286 /* We only allow integers in the fake hard registers. */
10287 return GET_MODE_CLASS (mode
) == MODE_INT
;
10289 /* The only registers left are the FPA registers
10290 which we only allow to hold FP values. */
10291 return GET_MODE_CLASS (mode
) == MODE_FLOAT
10292 && regno
>= FIRST_ARM_FP_REGNUM
10293 && regno
<= LAST_ARM_FP_REGNUM
;
10297 arm_regno_class (int regno
)
10301 if (regno
== STACK_POINTER_REGNUM
)
10303 if (regno
== CC_REGNUM
)
10310 if ( regno
<= LAST_ARM_REGNUM
10311 || regno
== FRAME_POINTER_REGNUM
10312 || regno
== ARG_POINTER_REGNUM
)
10313 return GENERAL_REGS
;
10315 if (regno
== CC_REGNUM
)
10318 if (IS_CIRRUS_REGNUM (regno
))
10319 return CIRRUS_REGS
;
10321 if (IS_IWMMXT_REGNUM (regno
))
10322 return IWMMXT_REGS
;
10327 /* Handle a special case when computing the offset
10328 of an argument from the frame pointer. */
10330 arm_debugger_arg_offset (int value
, rtx addr
)
10334 /* We are only interested if dbxout_parms() failed to compute the offset. */
10338 /* We can only cope with the case where the address is held in a register. */
10339 if (GET_CODE (addr
) != REG
)
10342 /* If we are using the frame pointer to point at the argument, then
10343 an offset of 0 is correct. */
10344 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
10347 /* If we are using the stack pointer to point at the
10348 argument, then an offset of 0 is correct. */
10349 if ((TARGET_THUMB
|| !frame_pointer_needed
)
10350 && REGNO (addr
) == SP_REGNUM
)
10353 /* Oh dear. The argument is pointed to by a register rather
10354 than being held in a register, or being stored at a known
10355 offset from the frame pointer. Since GDB only understands
10356 those two kinds of argument we must translate the address
10357 held in the register into an offset from the frame pointer.
10358 We do this by searching through the insns for the function
10359 looking to see where this register gets its value. If the
10360 register is initialized from the frame pointer plus an offset
10361 then we are in luck and we can continue, otherwise we give up.
10363 This code is exercised by producing debugging information
10364 for a function with arguments like this:
10366 double func (double a, double b, int c, double d) {return d;}
10368 Without this code the stab for parameter 'd' will be set to
10369 an offset of 0 from the frame pointer, rather than 8. */
10371 /* The if() statement says:
10373 If the insn is a normal instruction
10374 and if the insn is setting the value in a register
10375 and if the register being set is the register holding the address of the argument
10376 and if the address is computing by an addition
10377 that involves adding to a register
10378 which is the frame pointer
10383 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10385 if ( GET_CODE (insn
) == INSN
10386 && GET_CODE (PATTERN (insn
)) == SET
10387 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
10388 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
10389 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
10390 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
10391 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
10394 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
10403 warning ("unable to compute real location of stacked parameter");
10404 value
= 8; /* XXX magic hack */
10410 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
10413 if ((MASK) & insn_flags) \
10414 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
10418 struct builtin_description
10420 const unsigned int mask
;
10421 const enum insn_code icode
;
10422 const char * const name
;
10423 const enum arm_builtins code
;
10424 const enum rtx_code comparison
;
10425 const unsigned int flag
;
10428 static const struct builtin_description bdesc_2arg
[] =
10430 #define IWMMXT_BUILTIN(code, string, builtin) \
10431 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
10432 ARM_BUILTIN_##builtin, 0, 0 },
10434 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
10435 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
10436 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
10437 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
10438 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
10439 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
10440 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
10441 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
10442 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
10443 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
10444 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
10445 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
10446 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
10447 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
10448 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
10449 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
10450 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
10451 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
10452 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
10453 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsh", WMULSH
)
10454 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmuluh", WMULUH
)
10455 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
10456 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
10457 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
10458 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
10459 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
10460 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
10461 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
10462 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
10463 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
10464 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
10465 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
10466 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
10467 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
10468 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
10469 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
10470 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
10471 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
10472 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
10473 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
10474 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
10475 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
10476 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
10477 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
10478 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
10479 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
10480 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
10481 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
10482 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
10483 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
10484 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
10485 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
10486 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
10487 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
10488 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
10489 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
10490 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
10491 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
10493 #define IWMMXT_BUILTIN2(code, builtin) \
10494 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
10496 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
10497 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
10498 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
10499 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
10500 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
10501 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
10502 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
10503 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
10504 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
10505 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
10506 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
10507 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
10508 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
10509 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
10510 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
10511 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
10512 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
10513 IWMMXT_BUILTIN2 (lshrdi3
, WSRLDI
)
10514 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
10515 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
10516 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
10517 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
10518 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
10519 IWMMXT_BUILTIN2 (ashrdi3
, WSRADI
)
10520 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
10521 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
10522 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
10523 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
10524 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
10525 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
10526 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
10527 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
10530 static const struct builtin_description bdesc_1arg
[] =
10532 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
10533 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
10534 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
10535 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
10536 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
10537 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
10538 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
10539 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
10540 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
10541 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
10542 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
10543 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
10544 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
10545 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
10546 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
10547 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
10548 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
10549 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
10552 /* Set up all the iWMMXt builtins. This is
10553 not called if TARGET_IWMMXT is zero. */
10556 arm_init_iwmmxt_builtins (void)
10558 const struct builtin_description
* d
;
10560 tree endlink
= void_list_node
;
10563 = build_function_type (integer_type_node
,
10564 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
10565 tree v8qi_ftype_v8qi_v8qi_int
10566 = build_function_type (V8QI_type_node
,
10567 tree_cons (NULL_TREE
, V8QI_type_node
,
10568 tree_cons (NULL_TREE
, V8QI_type_node
,
10569 tree_cons (NULL_TREE
,
10572 tree v4hi_ftype_v4hi_int
10573 = build_function_type (V4HI_type_node
,
10574 tree_cons (NULL_TREE
, V4HI_type_node
,
10575 tree_cons (NULL_TREE
, integer_type_node
,
10577 tree v2si_ftype_v2si_int
10578 = build_function_type (V2SI_type_node
,
10579 tree_cons (NULL_TREE
, V2SI_type_node
,
10580 tree_cons (NULL_TREE
, integer_type_node
,
10582 tree v2si_ftype_di_di
10583 = build_function_type (V2SI_type_node
,
10584 tree_cons (NULL_TREE
, long_long_integer_type_node
,
10585 tree_cons (NULL_TREE
, long_long_integer_type_node
,
10587 tree di_ftype_di_int
10588 = build_function_type (long_long_integer_type_node
,
10589 tree_cons (NULL_TREE
, long_long_integer_type_node
,
10590 tree_cons (NULL_TREE
, integer_type_node
,
10592 tree di_ftype_di_int_int
10593 = build_function_type (long_long_integer_type_node
,
10594 tree_cons (NULL_TREE
, long_long_integer_type_node
,
10595 tree_cons (NULL_TREE
, integer_type_node
,
10596 tree_cons (NULL_TREE
,
10599 tree int_ftype_v8qi
10600 = build_function_type (integer_type_node
,
10601 tree_cons (NULL_TREE
, V8QI_type_node
,
10603 tree int_ftype_v4hi
10604 = build_function_type (integer_type_node
,
10605 tree_cons (NULL_TREE
, V4HI_type_node
,
10607 tree int_ftype_v2si
10608 = build_function_type (integer_type_node
,
10609 tree_cons (NULL_TREE
, V2SI_type_node
,
10611 tree int_ftype_v8qi_int
10612 = build_function_type (integer_type_node
,
10613 tree_cons (NULL_TREE
, V8QI_type_node
,
10614 tree_cons (NULL_TREE
, integer_type_node
,
10616 tree int_ftype_v4hi_int
10617 = build_function_type (integer_type_node
,
10618 tree_cons (NULL_TREE
, V4HI_type_node
,
10619 tree_cons (NULL_TREE
, integer_type_node
,
10621 tree int_ftype_v2si_int
10622 = build_function_type (integer_type_node
,
10623 tree_cons (NULL_TREE
, V2SI_type_node
,
10624 tree_cons (NULL_TREE
, integer_type_node
,
10626 tree v8qi_ftype_v8qi_int_int
10627 = build_function_type (V8QI_type_node
,
10628 tree_cons (NULL_TREE
, V8QI_type_node
,
10629 tree_cons (NULL_TREE
, integer_type_node
,
10630 tree_cons (NULL_TREE
,
10633 tree v4hi_ftype_v4hi_int_int
10634 = build_function_type (V4HI_type_node
,
10635 tree_cons (NULL_TREE
, V4HI_type_node
,
10636 tree_cons (NULL_TREE
, integer_type_node
,
10637 tree_cons (NULL_TREE
,
10640 tree v2si_ftype_v2si_int_int
10641 = build_function_type (V2SI_type_node
,
10642 tree_cons (NULL_TREE
, V2SI_type_node
,
10643 tree_cons (NULL_TREE
, integer_type_node
,
10644 tree_cons (NULL_TREE
,
10647 /* Miscellaneous. */
10648 tree v8qi_ftype_v4hi_v4hi
10649 = build_function_type (V8QI_type_node
,
10650 tree_cons (NULL_TREE
, V4HI_type_node
,
10651 tree_cons (NULL_TREE
, V4HI_type_node
,
10653 tree v4hi_ftype_v2si_v2si
10654 = build_function_type (V4HI_type_node
,
10655 tree_cons (NULL_TREE
, V2SI_type_node
,
10656 tree_cons (NULL_TREE
, V2SI_type_node
,
10658 tree v2si_ftype_v4hi_v4hi
10659 = build_function_type (V2SI_type_node
,
10660 tree_cons (NULL_TREE
, V4HI_type_node
,
10661 tree_cons (NULL_TREE
, V4HI_type_node
,
10663 tree v2si_ftype_v8qi_v8qi
10664 = build_function_type (V2SI_type_node
,
10665 tree_cons (NULL_TREE
, V8QI_type_node
,
10666 tree_cons (NULL_TREE
, V8QI_type_node
,
10668 tree v4hi_ftype_v4hi_di
10669 = build_function_type (V4HI_type_node
,
10670 tree_cons (NULL_TREE
, V4HI_type_node
,
10671 tree_cons (NULL_TREE
,
10672 long_long_integer_type_node
,
10674 tree v2si_ftype_v2si_di
10675 = build_function_type (V2SI_type_node
,
10676 tree_cons (NULL_TREE
, V2SI_type_node
,
10677 tree_cons (NULL_TREE
,
10678 long_long_integer_type_node
,
10680 tree void_ftype_int_int
10681 = build_function_type (void_type_node
,
10682 tree_cons (NULL_TREE
, integer_type_node
,
10683 tree_cons (NULL_TREE
, integer_type_node
,
10686 = build_function_type (long_long_unsigned_type_node
, endlink
);
10688 = build_function_type (long_long_integer_type_node
,
10689 tree_cons (NULL_TREE
, V8QI_type_node
,
10692 = build_function_type (long_long_integer_type_node
,
10693 tree_cons (NULL_TREE
, V4HI_type_node
,
10696 = build_function_type (long_long_integer_type_node
,
10697 tree_cons (NULL_TREE
, V2SI_type_node
,
10699 tree v2si_ftype_v4hi
10700 = build_function_type (V2SI_type_node
,
10701 tree_cons (NULL_TREE
, V4HI_type_node
,
10703 tree v4hi_ftype_v8qi
10704 = build_function_type (V4HI_type_node
,
10705 tree_cons (NULL_TREE
, V8QI_type_node
,
10708 tree di_ftype_di_v4hi_v4hi
10709 = build_function_type (long_long_unsigned_type_node
,
10710 tree_cons (NULL_TREE
,
10711 long_long_unsigned_type_node
,
10712 tree_cons (NULL_TREE
, V4HI_type_node
,
10713 tree_cons (NULL_TREE
,
10717 tree di_ftype_v4hi_v4hi
10718 = build_function_type (long_long_unsigned_type_node
,
10719 tree_cons (NULL_TREE
, V4HI_type_node
,
10720 tree_cons (NULL_TREE
, V4HI_type_node
,
10723 /* Normal vector binops. */
10724 tree v8qi_ftype_v8qi_v8qi
10725 = build_function_type (V8QI_type_node
,
10726 tree_cons (NULL_TREE
, V8QI_type_node
,
10727 tree_cons (NULL_TREE
, V8QI_type_node
,
10729 tree v4hi_ftype_v4hi_v4hi
10730 = build_function_type (V4HI_type_node
,
10731 tree_cons (NULL_TREE
, V4HI_type_node
,
10732 tree_cons (NULL_TREE
, V4HI_type_node
,
10734 tree v2si_ftype_v2si_v2si
10735 = build_function_type (V2SI_type_node
,
10736 tree_cons (NULL_TREE
, V2SI_type_node
,
10737 tree_cons (NULL_TREE
, V2SI_type_node
,
10739 tree di_ftype_di_di
10740 = build_function_type (long_long_unsigned_type_node
,
10741 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
10742 tree_cons (NULL_TREE
,
10743 long_long_unsigned_type_node
,
10746 /* Add all builtins that are more or less simple operations on two
10748 for (i
= 0, d
= bdesc_2arg
; i
< sizeof (bdesc_2arg
) / sizeof *d
; i
++, d
++)
10750 /* Use one of the operands; the target can have a different mode for
10751 mask-generating compares. */
10752 enum machine_mode mode
;
10758 mode
= insn_data
[d
->icode
].operand
[1].mode
;
10763 type
= v8qi_ftype_v8qi_v8qi
;
10766 type
= v4hi_ftype_v4hi_v4hi
;
10769 type
= v2si_ftype_v2si_v2si
;
10772 type
= di_ftype_di_di
;
10779 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
10782 /* Add the remaining MMX insns with somewhat more complicated types. */
10783 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
10784 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
10785 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
10787 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
10788 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
10789 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
10790 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
10791 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
10792 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
10794 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
10795 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
10796 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
10797 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
10798 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
10799 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
10801 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
10802 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
10803 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
10804 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
10805 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
10806 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
10808 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
10809 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
10810 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
10811 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
10812 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
10813 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
10815 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
10817 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
10818 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
10819 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
10820 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
10822 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
10823 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
10824 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
10825 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
10826 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
10827 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
10828 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
10829 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
10830 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
10832 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
10833 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
10834 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
10836 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
10837 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
10838 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
10840 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
10841 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
10842 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
10843 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
10844 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
10845 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
10847 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
10848 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
10849 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
10850 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
10851 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
10852 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
10853 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
10854 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
10855 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
10856 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
10857 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
10858 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
10860 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
10861 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
10862 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
10863 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
10865 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
10866 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
10867 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
10868 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
10869 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
10870 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
10871 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
10875 arm_init_builtins (void)
10877 if (TARGET_REALLY_IWMMXT
)
10878 arm_init_iwmmxt_builtins ();
10881 /* Errors in the source file can cause expand_expr to return const0_rtx
10882 where we expect a vector. To avoid crashing, use one of the vector
10883 clear instructions. */
10886 safe_vector_operand (rtx x
, enum machine_mode mode
)
10888 if (x
!= const0_rtx
)
10890 x
= gen_reg_rtx (mode
);
10892 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
10893 : gen_rtx_SUBREG (DImode
, x
, 0)));
10897 /* Subroutine of arm_expand_builtin to take care of binop insns. */
10900 arm_expand_binop_builtin (enum insn_code icode
,
10901 tree arglist
, rtx target
)
10904 tree arg0
= TREE_VALUE (arglist
);
10905 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
10906 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
10907 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
10908 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10909 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10910 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
10912 if (VECTOR_MODE_P (mode0
))
10913 op0
= safe_vector_operand (op0
, mode0
);
10914 if (VECTOR_MODE_P (mode1
))
10915 op1
= safe_vector_operand (op1
, mode1
);
10918 || GET_MODE (target
) != tmode
10919 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10920 target
= gen_reg_rtx (tmode
);
10922 /* In case the insn wants input operands in modes different from
10923 the result, abort. */
10924 if (GET_MODE (op0
) != mode0
|| GET_MODE (op1
) != mode1
)
10927 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10928 op0
= copy_to_mode_reg (mode0
, op0
);
10929 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
10930 op1
= copy_to_mode_reg (mode1
, op1
);
10932 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
10939 /* Subroutine of arm_expand_builtin to take care of unop insns. */
10942 arm_expand_unop_builtin (enum insn_code icode
,
10943 tree arglist
, rtx target
, int do_load
)
10946 tree arg0
= TREE_VALUE (arglist
);
10947 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
10948 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10949 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
10952 || GET_MODE (target
) != tmode
10953 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10954 target
= gen_reg_rtx (tmode
);
10956 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
10959 if (VECTOR_MODE_P (mode0
))
10960 op0
= safe_vector_operand (op0
, mode0
);
10962 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
10963 op0
= copy_to_mode_reg (mode0
, op0
);
10966 pat
= GEN_FCN (icode
) (target
, op0
);
10973 /* Expand an expression EXP that calls a built-in function,
10974 with result going to TARGET if that's convenient
10975 (and in mode MODE if that's convenient).
10976 SUBTARGET may be used as the target for computing one of EXP's operands.
10977 IGNORE is nonzero if the value is to be ignored. */
10980 arm_expand_builtin (tree exp
,
10982 rtx subtarget ATTRIBUTE_UNUSED
,
10983 enum machine_mode mode ATTRIBUTE_UNUSED
,
10984 int ignore ATTRIBUTE_UNUSED
)
10986 const struct builtin_description
* d
;
10987 enum insn_code icode
;
10988 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
10989 tree arglist
= TREE_OPERAND (exp
, 1);
10997 int fcode
= DECL_FUNCTION_CODE (fndecl
);
10999 enum machine_mode tmode
;
11000 enum machine_mode mode0
;
11001 enum machine_mode mode1
;
11002 enum machine_mode mode2
;
11006 case ARM_BUILTIN_TEXTRMSB
:
11007 case ARM_BUILTIN_TEXTRMUB
:
11008 case ARM_BUILTIN_TEXTRMSH
:
11009 case ARM_BUILTIN_TEXTRMUH
:
11010 case ARM_BUILTIN_TEXTRMSW
:
11011 case ARM_BUILTIN_TEXTRMUW
:
11012 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
11013 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
11014 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
11015 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
11016 : CODE_FOR_iwmmxt_textrmw
);
11018 arg0
= TREE_VALUE (arglist
);
11019 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11020 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11021 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11022 tmode
= insn_data
[icode
].operand
[0].mode
;
11023 mode0
= insn_data
[icode
].operand
[1].mode
;
11024 mode1
= insn_data
[icode
].operand
[2].mode
;
11026 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11027 op0
= copy_to_mode_reg (mode0
, op0
);
11028 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11030 /* @@@ better error message */
11031 error ("selector must be an immediate");
11032 return gen_reg_rtx (tmode
);
11035 || GET_MODE (target
) != tmode
11036 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11037 target
= gen_reg_rtx (tmode
);
11038 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11044 case ARM_BUILTIN_TINSRB
:
11045 case ARM_BUILTIN_TINSRH
:
11046 case ARM_BUILTIN_TINSRW
:
11047 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
11048 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
11049 : CODE_FOR_iwmmxt_tinsrw
);
11050 arg0
= TREE_VALUE (arglist
);
11051 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11052 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
11053 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11054 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11055 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
11056 tmode
= insn_data
[icode
].operand
[0].mode
;
11057 mode0
= insn_data
[icode
].operand
[1].mode
;
11058 mode1
= insn_data
[icode
].operand
[2].mode
;
11059 mode2
= insn_data
[icode
].operand
[3].mode
;
11061 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11062 op0
= copy_to_mode_reg (mode0
, op0
);
11063 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11064 op1
= copy_to_mode_reg (mode1
, op1
);
11065 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
11067 /* @@@ better error message */
11068 error ("selector must be an immediate");
11072 || GET_MODE (target
) != tmode
11073 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11074 target
= gen_reg_rtx (tmode
);
11075 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
11081 case ARM_BUILTIN_SETWCX
:
11082 arg0
= TREE_VALUE (arglist
);
11083 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11084 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11085 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11086 emit_insn (gen_iwmmxt_tmcr (op0
, op1
));
11089 case ARM_BUILTIN_GETWCX
:
11090 arg0
= TREE_VALUE (arglist
);
11091 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11092 target
= gen_reg_rtx (SImode
);
11093 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
11096 case ARM_BUILTIN_WSHUFH
:
11097 icode
= CODE_FOR_iwmmxt_wshufh
;
11098 arg0
= TREE_VALUE (arglist
);
11099 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11100 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11101 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11102 tmode
= insn_data
[icode
].operand
[0].mode
;
11103 mode1
= insn_data
[icode
].operand
[1].mode
;
11104 mode2
= insn_data
[icode
].operand
[2].mode
;
11106 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
11107 op0
= copy_to_mode_reg (mode1
, op0
);
11108 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
11110 /* @@@ better error message */
11111 error ("mask must be an immediate");
11115 || GET_MODE (target
) != tmode
11116 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11117 target
= gen_reg_rtx (tmode
);
11118 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11124 case ARM_BUILTIN_WSADB
:
11125 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
11126 case ARM_BUILTIN_WSADH
:
11127 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
11128 case ARM_BUILTIN_WSADBZ
:
11129 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
11130 case ARM_BUILTIN_WSADHZ
:
11131 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
11133 /* Several three-argument builtins. */
11134 case ARM_BUILTIN_WMACS
:
11135 case ARM_BUILTIN_WMACU
:
11136 case ARM_BUILTIN_WALIGN
:
11137 case ARM_BUILTIN_TMIA
:
11138 case ARM_BUILTIN_TMIAPH
:
11139 case ARM_BUILTIN_TMIATT
:
11140 case ARM_BUILTIN_TMIATB
:
11141 case ARM_BUILTIN_TMIABT
:
11142 case ARM_BUILTIN_TMIABB
:
11143 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
11144 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
11145 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
11146 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
11147 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
11148 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
11149 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
11150 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
11151 : CODE_FOR_iwmmxt_walign
);
11152 arg0
= TREE_VALUE (arglist
);
11153 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11154 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
11155 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11156 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11157 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
11158 tmode
= insn_data
[icode
].operand
[0].mode
;
11159 mode0
= insn_data
[icode
].operand
[1].mode
;
11160 mode1
= insn_data
[icode
].operand
[2].mode
;
11161 mode2
= insn_data
[icode
].operand
[3].mode
;
11163 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11164 op0
= copy_to_mode_reg (mode0
, op0
);
11165 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11166 op1
= copy_to_mode_reg (mode1
, op1
);
11167 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
11168 op2
= copy_to_mode_reg (mode2
, op2
);
11170 || GET_MODE (target
) != tmode
11171 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11172 target
= gen_reg_rtx (tmode
);
11173 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
11179 case ARM_BUILTIN_WZERO
:
11180 target
= gen_reg_rtx (DImode
);
11181 emit_insn (gen_iwmmxt_clrdi (target
));
11188 for (i
= 0, d
= bdesc_2arg
; i
< sizeof (bdesc_2arg
) / sizeof *d
; i
++, d
++)
11189 if (d
->code
== (const enum arm_builtins
) fcode
)
11190 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
11192 for (i
= 0, d
= bdesc_1arg
; i
< sizeof (bdesc_1arg
) / sizeof *d
; i
++, d
++)
11193 if (d
->code
== (const enum arm_builtins
) fcode
)
11194 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
11196 /* @@@ Should really do something sensible here. */
11200 /* Recursively search through all of the blocks in a function
11201 checking to see if any of the variables created in that
11202 function match the RTX called 'orig'. If they do then
11203 replace them with the RTX called 'new'. */
11205 replace_symbols_in_block (tree block
, rtx orig
, rtx
new)
11207 for (; block
; block
= BLOCK_CHAIN (block
))
11211 if (!TREE_USED (block
))
11214 for (sym
= BLOCK_VARS (block
); sym
; sym
= TREE_CHAIN (sym
))
11216 if ( (DECL_NAME (sym
) == 0 && TREE_CODE (sym
) != TYPE_DECL
)
11217 || DECL_IGNORED_P (sym
)
11218 || TREE_CODE (sym
) != VAR_DECL
11219 || DECL_EXTERNAL (sym
)
11220 || !rtx_equal_p (DECL_RTL (sym
), orig
)
11224 SET_DECL_RTL (sym
, new);
11227 replace_symbols_in_block (BLOCK_SUBBLOCKS (block
), orig
, new);
11231 /* Return the number (counting from 0) of
11232 the least significant set bit in MASK. */
11235 number_of_first_bit_set (int mask
)
11240 (mask
& (1 << bit
)) == 0;
11247 /* Generate code to return from a thumb function.
11248 If 'reg_containing_return_addr' is -1, then the return address is
11249 actually on the stack, at the stack pointer. */
11251 thumb_exit (FILE *f
, int reg_containing_return_addr
, rtx eh_ofs
)
11253 unsigned regs_available_for_popping
;
11254 unsigned regs_to_pop
;
11256 unsigned available
;
11260 int restore_a4
= FALSE
;
11262 /* Compute the registers we need to pop. */
11266 /* There is an assumption here, that if eh_ofs is not NULL, the
11267 normal return address will have been pushed. */
11268 if (reg_containing_return_addr
== -1 || eh_ofs
)
11270 /* When we are generating a return for __builtin_eh_return,
11271 reg_containing_return_addr must specify the return regno. */
11272 if (eh_ofs
&& reg_containing_return_addr
== -1)
11275 regs_to_pop
|= 1 << LR_REGNUM
;
11279 if (TARGET_BACKTRACE
)
11281 /* Restore the (ARM) frame pointer and stack pointer. */
11282 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
11286 /* If there is nothing to pop then just emit the BX instruction and
11288 if (pops_needed
== 0)
11291 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
11293 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
11296 /* Otherwise if we are not supporting interworking and we have not created
11297 a backtrace structure and the function was not entered in ARM mode then
11298 just pop the return address straight into the PC. */
11299 else if (!TARGET_INTERWORK
11300 && !TARGET_BACKTRACE
11301 && !is_called_in_ARM_mode (current_function_decl
))
11305 asm_fprintf (f
, "\tadd\t%r, #4\n", SP_REGNUM
);
11306 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
11307 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
11310 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
11315 /* Find out how many of the (return) argument registers we can corrupt. */
11316 regs_available_for_popping
= 0;
11318 /* If returning via __builtin_eh_return, the bottom three registers
11319 all contain information needed for the return. */
11325 /* If we can deduce the registers used from the function's
11326 return value. This is more reliable that examining
11327 regs_ever_live[] because that will be set if the register is
11328 ever used in the function, not just if the register is used
11329 to hold a return value. */
11331 if (current_function_return_rtx
!= 0)
11332 mode
= GET_MODE (current_function_return_rtx
);
11335 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
11337 size
= GET_MODE_SIZE (mode
);
11341 /* In a void function we can use any argument register.
11342 In a function that returns a structure on the stack
11343 we can use the second and third argument registers. */
11344 if (mode
== VOIDmode
)
11345 regs_available_for_popping
=
11346 (1 << ARG_REGISTER (1))
11347 | (1 << ARG_REGISTER (2))
11348 | (1 << ARG_REGISTER (3));
11350 regs_available_for_popping
=
11351 (1 << ARG_REGISTER (2))
11352 | (1 << ARG_REGISTER (3));
11354 else if (size
<= 4)
11355 regs_available_for_popping
=
11356 (1 << ARG_REGISTER (2))
11357 | (1 << ARG_REGISTER (3));
11358 else if (size
<= 8)
11359 regs_available_for_popping
=
11360 (1 << ARG_REGISTER (3));
11363 /* Match registers to be popped with registers into which we pop them. */
11364 for (available
= regs_available_for_popping
,
11365 required
= regs_to_pop
;
11366 required
!= 0 && available
!= 0;
11367 available
&= ~(available
& - available
),
11368 required
&= ~(required
& - required
))
11371 /* If we have any popping registers left over, remove them. */
11373 regs_available_for_popping
&= ~available
;
11375 /* Otherwise if we need another popping register we can use
11376 the fourth argument register. */
11377 else if (pops_needed
)
11379 /* If we have not found any free argument registers and
11380 reg a4 contains the return address, we must move it. */
11381 if (regs_available_for_popping
== 0
11382 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
11384 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
11385 reg_containing_return_addr
= LR_REGNUM
;
11387 else if (size
> 12)
11389 /* Register a4 is being used to hold part of the return value,
11390 but we have dire need of a free, low register. */
11393 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
11396 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
11398 /* The fourth argument register is available. */
11399 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
11405 /* Pop as many registers as we can. */
11406 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
11408 /* Process the registers we popped. */
11409 if (reg_containing_return_addr
== -1)
11411 /* The return address was popped into the lowest numbered register. */
11412 regs_to_pop
&= ~(1 << LR_REGNUM
);
11414 reg_containing_return_addr
=
11415 number_of_first_bit_set (regs_available_for_popping
);
11417 /* Remove this register for the mask of available registers, so that
11418 the return address will not be corrupted by further pops. */
11419 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
11422 /* If we popped other registers then handle them here. */
11423 if (regs_available_for_popping
)
11427 /* Work out which register currently contains the frame pointer. */
11428 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
11430 /* Move it into the correct place. */
11431 asm_fprintf (f
, "\tmov\t%r, %r\n",
11432 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
11434 /* (Temporarily) remove it from the mask of popped registers. */
11435 regs_available_for_popping
&= ~(1 << frame_pointer
);
11436 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
11438 if (regs_available_for_popping
)
11442 /* We popped the stack pointer as well,
11443 find the register that contains it. */
11444 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
11446 /* Move it into the stack register. */
11447 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
11449 /* At this point we have popped all necessary registers, so
11450 do not worry about restoring regs_available_for_popping
11451 to its correct value:
11453 assert (pops_needed == 0)
11454 assert (regs_available_for_popping == (1 << frame_pointer))
11455 assert (regs_to_pop == (1 << STACK_POINTER)) */
11459 /* Since we have just move the popped value into the frame
11460 pointer, the popping register is available for reuse, and
11461 we know that we still have the stack pointer left to pop. */
11462 regs_available_for_popping
|= (1 << frame_pointer
);
11466 /* If we still have registers left on the stack, but we no longer have
11467 any registers into which we can pop them, then we must move the return
11468 address into the link register and make available the register that
11470 if (regs_available_for_popping
== 0 && pops_needed
> 0)
11472 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
11474 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
11475 reg_containing_return_addr
);
11477 reg_containing_return_addr
= LR_REGNUM
;
11480 /* If we have registers left on the stack then pop some more.
11481 We know that at most we will want to pop FP and SP. */
11482 if (pops_needed
> 0)
11487 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
11489 /* We have popped either FP or SP.
11490 Move whichever one it is into the correct register. */
11491 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
11492 move_to
= number_of_first_bit_set (regs_to_pop
);
11494 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
11496 regs_to_pop
&= ~(1 << move_to
);
11501 /* If we still have not popped everything then we must have only
11502 had one register available to us and we are now popping the SP. */
11503 if (pops_needed
> 0)
11507 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
11509 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
11511 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
11513 assert (regs_to_pop == (1 << STACK_POINTER))
11514 assert (pops_needed == 1)
11518 /* If necessary restore the a4 register. */
11521 if (reg_containing_return_addr
!= LR_REGNUM
)
11523 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
11524 reg_containing_return_addr
= LR_REGNUM
;
11527 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
11531 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
11533 /* Return to caller. */
11534 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
11537 /* Emit code to push or pop registers to or from the stack. */
11539 thumb_pushpop (FILE *f
, int mask
, int push
)
11542 int lo_mask
= mask
& 0xFF;
11544 if (lo_mask
== 0 && !push
&& (mask
& (1 << 15)))
11546 /* Special case. Do not generate a POP PC statement here, do it in
11548 thumb_exit (f
, -1, NULL_RTX
);
11552 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
11554 /* Look at the low registers first. */
11555 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
11559 asm_fprintf (f
, "%r", regno
);
11561 if ((lo_mask
& ~1) != 0)
11566 if (push
&& (mask
& (1 << LR_REGNUM
)))
11568 /* Catch pushing the LR. */
11572 asm_fprintf (f
, "%r", LR_REGNUM
);
11574 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
11576 /* Catch popping the PC. */
11577 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
)
11579 /* The PC is never poped directly, instead
11580 it is popped into r3 and then BX is used. */
11581 fprintf (f
, "}\n");
11583 thumb_exit (f
, -1, NULL_RTX
);
11592 asm_fprintf (f
, "%r", PC_REGNUM
);
11596 fprintf (f
, "}\n");
11600 thumb_final_prescan_insn (rtx insn
)
11602 if (flag_print_asm_name
)
11603 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
11604 INSN_ADDRESSES (INSN_UID (insn
)));
11608 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
11610 unsigned HOST_WIDE_INT mask
= 0xff;
11613 if (val
== 0) /* XXX */
11616 for (i
= 0; i
< 25; i
++)
11617 if ((val
& (mask
<< i
)) == val
)
11623 /* Returns nonzero if the current function contains,
11624 or might contain a far jump. */
11626 thumb_far_jump_used_p (int in_prologue
)
11630 /* This test is only important for leaf functions. */
11631 /* assert (!leaf_function_p ()); */
11633 /* If we have already decided that far jumps may be used,
11634 do not bother checking again, and always return true even if
11635 it turns out that they are not being used. Once we have made
11636 the decision that far jumps are present (and that hence the link
11637 register will be pushed onto the stack) we cannot go back on it. */
11638 if (cfun
->machine
->far_jump_used
)
11641 /* If this function is not being called from the prologue/epilogue
11642 generation code then it must be being called from the
11643 INITIAL_ELIMINATION_OFFSET macro. */
11646 /* In this case we know that we are being asked about the elimination
11647 of the arg pointer register. If that register is not being used,
11648 then there are no arguments on the stack, and we do not have to
11649 worry that a far jump might force the prologue to push the link
11650 register, changing the stack offsets. In this case we can just
11651 return false, since the presence of far jumps in the function will
11652 not affect stack offsets.
11654 If the arg pointer is live (or if it was live, but has now been
11655 eliminated and so set to dead) then we do have to test to see if
11656 the function might contain a far jump. This test can lead to some
11657 false negatives, since before reload is completed, then length of
11658 branch instructions is not known, so gcc defaults to returning their
11659 longest length, which in turn sets the far jump attribute to true.
11661 A false negative will not result in bad code being generated, but it
11662 will result in a needless push and pop of the link register. We
11663 hope that this does not occur too often. */
11664 if (regs_ever_live
[ARG_POINTER_REGNUM
])
11665 cfun
->machine
->arg_pointer_live
= 1;
11666 else if (!cfun
->machine
->arg_pointer_live
)
11670 /* Check to see if the function contains a branch
11671 insn with the far jump attribute set. */
11672 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11674 if (GET_CODE (insn
) == JUMP_INSN
11675 /* Ignore tablejump patterns. */
11676 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
11677 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
11678 && get_attr_far_jump (insn
) == FAR_JUMP_YES
11681 /* Record the fact that we have decied that
11682 the function does use far jumps. */
11683 cfun
->machine
->far_jump_used
= 1;
11691 /* Return nonzero if FUNC must be entered in ARM mode. */
11693 is_called_in_ARM_mode (tree func
)
11695 if (TREE_CODE (func
) != FUNCTION_DECL
)
11698 /* Ignore the problem about functions whoes address is taken. */
11699 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
11703 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
11709 /* The bits which aren't usefully expanded as rtl. */
11711 thumb_unexpanded_epilogue (void)
11714 int live_regs_mask
= 0;
11715 int high_regs_pushed
= 0;
11716 int leaf_function
= leaf_function_p ();
11717 int had_to_push_lr
;
11718 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
11720 if (return_used_this_function
)
11723 if (IS_NAKED (arm_current_func_type ()))
11726 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
11727 if (THUMB_REG_PUSHED_P (regno
))
11728 live_regs_mask
|= 1 << regno
;
11730 for (regno
= 8; regno
< 13; regno
++)
11731 if (THUMB_REG_PUSHED_P (regno
))
11732 high_regs_pushed
++;
11734 /* The prolog may have pushed some high registers to use as
11735 work registers. eg the testuite file:
11736 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
11737 compiles to produce:
11738 push {r4, r5, r6, r7, lr}
11742 as part of the prolog. We have to undo that pushing here. */
11744 if (high_regs_pushed
)
11746 int mask
= live_regs_mask
;
11752 /* If we can deduce the registers used from the function's return value.
11753 This is more reliable that examining regs_ever_live[] because that
11754 will be set if the register is ever used in the function, not just if
11755 the register is used to hold a return value. */
11757 if (current_function_return_rtx
!= 0)
11758 mode
= GET_MODE (current_function_return_rtx
);
11761 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
11763 size
= GET_MODE_SIZE (mode
);
11765 /* Unless we are returning a type of size > 12 register r3 is
11771 /* Oh dear! We have no low registers into which we can pop
11774 ("no low registers available for popping high registers");
11776 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
11777 if (THUMB_REG_PUSHED_P (next_hi_reg
))
11780 while (high_regs_pushed
)
11782 /* Find lo register(s) into which the high register(s) can
11784 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
11786 if (mask
& (1 << regno
))
11787 high_regs_pushed
--;
11788 if (high_regs_pushed
== 0)
11792 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
11794 /* Pop the values into the low register(s). */
11795 thumb_pushpop (asm_out_file
, mask
, 0);
11797 /* Move the value(s) into the high registers. */
11798 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
11800 if (mask
& (1 << regno
))
11802 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
11805 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
11806 if (THUMB_REG_PUSHED_P (next_hi_reg
))
11813 had_to_push_lr
= (live_regs_mask
|| !leaf_function
11814 || thumb_far_jump_used_p (1));
11816 if (TARGET_BACKTRACE
11817 && ((live_regs_mask
& 0xFF) == 0)
11818 && regs_ever_live
[LAST_ARG_REGNUM
] != 0)
11820 /* The stack backtrace structure creation code had to
11821 push R7 in order to get a work register, so we pop
11823 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
11826 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
11829 && !is_called_in_ARM_mode (current_function_decl
)
11831 live_regs_mask
|= 1 << PC_REGNUM
;
11833 /* Either no argument registers were pushed or a backtrace
11834 structure was created which includes an adjusted stack
11835 pointer, so just pop everything. */
11836 if (live_regs_mask
)
11837 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
);
11840 thumb_exit (asm_out_file
, 2, eh_ofs
);
11841 /* We have either just popped the return address into the
11842 PC or it is was kept in LR for the entire function or
11843 it is still on the stack because we do not want to
11844 return by doing a pop {pc}. */
11845 else if ((live_regs_mask
& (1 << PC_REGNUM
)) == 0)
11846 thumb_exit (asm_out_file
,
11848 && is_called_in_ARM_mode (current_function_decl
)) ?
11849 -1 : LR_REGNUM
, NULL_RTX
);
11853 /* Pop everything but the return address. */
11854 live_regs_mask
&= ~(1 << PC_REGNUM
);
11856 if (live_regs_mask
)
11857 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
);
11859 if (had_to_push_lr
)
11860 /* Get the return address into a temporary register. */
11861 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0);
11863 /* Remove the argument registers that were pushed onto the stack. */
11864 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
11865 SP_REGNUM
, SP_REGNUM
,
11866 current_function_pretend_args_size
);
11869 thumb_exit (asm_out_file
, 2, eh_ofs
);
11871 thumb_exit (asm_out_file
,
11872 had_to_push_lr
? LAST_ARG_REGNUM
: LR_REGNUM
, NULL_RTX
);
11878 /* Functions to save and restore machine-specific function data. */
11879 static struct machine_function
*
11880 arm_init_machine_status (void)
11882 struct machine_function
*machine
;
11883 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
11885 #if ARM_FT_UNKNOWN != 0
11886 machine
->func_type
= ARM_FT_UNKNOWN
;
11891 /* Return an RTX indicating where the return address to the
11892 calling function can be found. */
11894 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
11899 if (TARGET_APCS_32
)
11900 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
11903 rtx lr
= gen_rtx_AND (Pmode
, gen_rtx_REG (Pmode
, LR_REGNUM
),
11904 GEN_INT (RETURN_ADDR_MASK26
));
11905 return get_func_hard_reg_initial_val (cfun
, lr
);
11909 /* Do anything needed before RTL is emitted for each function. */
11911 arm_init_expanders (void)
11913 /* Arrange to initialize and mark the machine per-function status. */
11914 init_machine_status
= arm_init_machine_status
;
11918 thumb_get_frame_size (void)
11922 int base_size
= ROUND_UP_WORD (get_frame_size ());
11923 int count_regs
= 0;
11924 int entry_size
= 0;
11927 if (! TARGET_THUMB
)
11930 if (! TARGET_ATPCS
)
11933 /* We need to know if we are a leaf function. Unfortunately, it
11934 is possible to be called after start_sequence has been called,
11935 which causes get_insns to return the insns for the sequence,
11936 not the function, which will cause leaf_function_p to return
11937 the incorrect result.
11939 To work around this, we cache the computed frame size. This
11940 works because we will only be calling RTL expanders that need
11941 to know about leaf functions once reload has completed, and the
11942 frame size cannot be changed after that time, so we can safely
11943 use the cached value. */
11945 if (reload_completed
)
11946 return cfun
->machine
->frame_size
;
11948 leaf
= leaf_function_p ();
11950 /* A leaf function does not need any stack alignment if it has nothing
11952 if (leaf
&& base_size
== 0)
11954 cfun
->machine
->frame_size
= 0;
11958 /* We know that SP will be word aligned on entry, and we must
11959 preserve that condition at any subroutine call. But those are
11960 the only constraints. */
11962 /* Space for variadic functions. */
11963 if (current_function_pretend_args_size
)
11964 entry_size
+= current_function_pretend_args_size
;
11966 /* Space for pushed lo registers. */
11967 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
11968 if (THUMB_REG_PUSHED_P (regno
))
11971 /* Space for backtrace structure. */
11972 if (TARGET_BACKTRACE
)
11974 if (count_regs
== 0 && regs_ever_live
[LAST_ARG_REGNUM
] != 0)
11980 if (count_regs
|| !leaf
|| thumb_far_jump_used_p (1))
11981 count_regs
++; /* LR */
11983 entry_size
+= count_regs
* 4;
11986 /* Space for pushed hi regs. */
11987 for (regno
= 8; regno
< 13; regno
++)
11988 if (THUMB_REG_PUSHED_P (regno
))
11991 entry_size
+= count_regs
* 4;
11993 if ((entry_size
+ base_size
+ current_function_outgoing_args_size
) & 7)
11995 if ((entry_size
+ base_size
+ current_function_outgoing_args_size
) & 7)
11998 cfun
->machine
->frame_size
= base_size
;
12003 /* Generate the rest of a function's prologue. */
12005 thumb_expand_prologue (void)
12007 HOST_WIDE_INT amount
= (thumb_get_frame_size ()
12008 + current_function_outgoing_args_size
);
12009 unsigned long func_type
;
12011 func_type
= arm_current_func_type ();
12013 /* Naked functions don't have prologues. */
12014 if (IS_NAKED (func_type
))
12017 if (IS_INTERRUPT (func_type
))
12019 error ("interrupt Service Routines cannot be coded in Thumb mode");
12023 if (frame_pointer_needed
)
12024 emit_insn (gen_movsi (hard_frame_pointer_rtx
, stack_pointer_rtx
));
12028 amount
= ROUND_UP_WORD (amount
);
12031 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
12032 GEN_INT (- amount
)));
12038 /* The stack decrement is too big for an immediate value in a single
12039 insn. In theory we could issue multiple subtracts, but after
12040 three of them it becomes more space efficient to place the full
12041 value in the constant pool and load into a register. (Also the
12042 ARM debugger really likes to see only one stack decrement per
12043 function). So instead we look for a scratch register into which
12044 we can load the decrement, and then we subtract this from the
12045 stack pointer. Unfortunately on the thumb the only available
12046 scratch registers are the argument registers, and we cannot use
12047 these as they may hold arguments to the function. Instead we
12048 attempt to locate a call preserved register which is used by this
12049 function. If we can find one, then we know that it will have
12050 been pushed at the start of the prologue and so we can corrupt
12052 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
12053 if (THUMB_REG_PUSHED_P (regno
)
12054 && !(frame_pointer_needed
12055 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
12058 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
12060 rtx spare
= gen_rtx (REG
, SImode
, IP_REGNUM
);
12062 /* Choose an arbitrary, non-argument low register. */
12063 reg
= gen_rtx (REG
, SImode
, LAST_LO_REGNUM
);
12065 /* Save it by copying it into a high, scratch register. */
12066 emit_insn (gen_movsi (spare
, reg
));
12067 /* Add a USE to stop propagate_one_insn() from barfing. */
12068 emit_insn (gen_prologue_use (spare
));
12070 /* Decrement the stack. */
12071 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
12072 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
12075 /* Restore the low register's original value. */
12076 emit_insn (gen_movsi (reg
, spare
));
12078 /* Emit a USE of the restored scratch register, so that flow
12079 analysis will not consider the restore redundant. The
12080 register won't be used again in this function and isn't
12081 restored by the epilogue. */
12082 emit_insn (gen_prologue_use (reg
));
12086 reg
= gen_rtx (REG
, SImode
, regno
);
12088 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
12089 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
12095 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
12096 emit_insn (gen_blockage ());
12100 thumb_expand_epilogue (void)
12102 HOST_WIDE_INT amount
= (thumb_get_frame_size ()
12103 + current_function_outgoing_args_size
);
12105 /* Naked functions don't have prologues. */
12106 if (IS_NAKED (arm_current_func_type ()))
12109 if (frame_pointer_needed
)
12110 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
12113 amount
= ROUND_UP_WORD (amount
);
12116 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
12117 GEN_INT (amount
)));
12120 /* r3 is always free in the epilogue. */
12121 rtx reg
= gen_rtx (REG
, SImode
, LAST_ARG_REGNUM
);
12123 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
12124 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
12128 /* Emit a USE (stack_pointer_rtx), so that
12129 the stack adjustment will not be deleted. */
12130 emit_insn (gen_prologue_use (stack_pointer_rtx
));
12132 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
12133 emit_insn (gen_blockage ());
12137 thumb_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
12139 int live_regs_mask
= 0;
12140 int high_regs_pushed
= 0;
12143 if (IS_NAKED (arm_current_func_type ()))
12146 if (is_called_in_ARM_mode (current_function_decl
))
12150 if (GET_CODE (DECL_RTL (current_function_decl
)) != MEM
)
12152 if (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0)) != SYMBOL_REF
)
12154 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
12156 /* Generate code sequence to switch us into Thumb mode. */
12157 /* The .code 32 directive has already been emitted by
12158 ASM_DECLARE_FUNCTION_NAME. */
12159 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
12160 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
12162 /* Generate a label, so that the debugger will notice the
12163 change in instruction sets. This label is also used by
12164 the assembler to bypass the ARM code when this function
12165 is called from a Thumb encoded function elsewhere in the
12166 same file. Hence the definition of STUB_NAME here must
12167 agree with the definition in gas/config/tc-arm.c */
12169 #define STUB_NAME ".real_start_of"
12171 fprintf (f
, "\t.code\t16\n");
12173 if (arm_dllexport_name_p (name
))
12174 name
= arm_strip_name_encoding (name
);
12176 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
12177 fprintf (f
, "\t.thumb_func\n");
12178 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
12181 if (current_function_pretend_args_size
)
12183 if (cfun
->machine
->uses_anonymous_args
)
12187 fprintf (f
, "\tpush\t{");
12189 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
12191 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
12192 regno
<= LAST_ARG_REGNUM
;
12194 asm_fprintf (f
, "%r%s", regno
,
12195 regno
== LAST_ARG_REGNUM
? "" : ", ");
12197 fprintf (f
, "}\n");
12200 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
12201 SP_REGNUM
, SP_REGNUM
,
12202 current_function_pretend_args_size
);
12205 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
12206 if (THUMB_REG_PUSHED_P (regno
))
12207 live_regs_mask
|= 1 << regno
;
12209 if (live_regs_mask
|| !leaf_function_p () || thumb_far_jump_used_p (1))
12210 live_regs_mask
|= 1 << LR_REGNUM
;
12212 if (TARGET_BACKTRACE
)
12215 int work_register
= 0;
12218 /* We have been asked to create a stack backtrace structure.
12219 The code looks like this:
12223 0 sub SP, #16 Reserve space for 4 registers.
12224 2 push {R7} Get a work register.
12225 4 add R7, SP, #20 Get the stack pointer before the push.
12226 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
12227 8 mov R7, PC Get hold of the start of this code plus 12.
12228 10 str R7, [SP, #16] Store it.
12229 12 mov R7, FP Get hold of the current frame pointer.
12230 14 str R7, [SP, #4] Store it.
12231 16 mov R7, LR Get hold of the current return address.
12232 18 str R7, [SP, #12] Store it.
12233 20 add R7, SP, #16 Point at the start of the backtrace structure.
12234 22 mov FP, R7 Put this value into the frame pointer. */
12236 if ((live_regs_mask
& 0xFF) == 0)
12238 /* See if the a4 register is free. */
12240 if (regs_ever_live
[LAST_ARG_REGNUM
] == 0)
12241 work_register
= LAST_ARG_REGNUM
;
12242 else /* We must push a register of our own */
12243 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
12246 if (work_register
== 0)
12248 /* Select a register from the list that will be pushed to
12249 use as our work register. */
12250 for (work_register
= (LAST_LO_REGNUM
+ 1); work_register
--;)
12251 if ((1 << work_register
) & live_regs_mask
)
12256 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
12257 SP_REGNUM
, SP_REGNUM
);
12259 if (live_regs_mask
)
12260 thumb_pushpop (f
, live_regs_mask
, 1);
12262 for (offset
= 0, wr
= 1 << 15; wr
!= 0; wr
>>= 1)
12263 if (wr
& live_regs_mask
)
12266 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
12267 offset
+ 16 + current_function_pretend_args_size
);
12269 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12272 /* Make sure that the instruction fetching the PC is in the right place
12273 to calculate "start of backtrace creation code + 12". */
12274 if (live_regs_mask
)
12276 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
12277 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12279 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
12280 ARM_HARD_FRAME_POINTER_REGNUM
);
12281 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12286 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
12287 ARM_HARD_FRAME_POINTER_REGNUM
);
12288 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12290 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
12291 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12295 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
12296 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12298 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
12300 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
12301 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
12303 else if (live_regs_mask
)
12304 thumb_pushpop (f
, live_regs_mask
, 1);
12306 for (regno
= 8; regno
< 13; regno
++)
12307 if (THUMB_REG_PUSHED_P (regno
))
12308 high_regs_pushed
++;
12310 if (high_regs_pushed
)
12312 int pushable_regs
= 0;
12313 int mask
= live_regs_mask
& 0xff;
12316 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
12317 if (THUMB_REG_PUSHED_P (next_hi_reg
))
12320 pushable_regs
= mask
;
12322 if (pushable_regs
== 0)
12324 /* Desperation time -- this probably will never happen. */
12325 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
))
12326 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, LAST_ARG_REGNUM
);
12327 mask
= 1 << LAST_ARG_REGNUM
;
12330 while (high_regs_pushed
> 0)
12332 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
12334 if (mask
& (1 << regno
))
12336 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
12338 high_regs_pushed
--;
12340 if (high_regs_pushed
)
12342 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
12344 if (THUMB_REG_PUSHED_P (next_hi_reg
))
12349 mask
&= ~((1 << regno
) - 1);
12355 thumb_pushpop (f
, mask
, 1);
12358 if (pushable_regs
== 0
12359 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
)))
12360 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
12364 /* Handle the case of a double word load into a low register from
12365 a computed memory address. The computed address may involve a
12366 register which is overwritten by the load. */
12368 thumb_load_double_from_address (rtx
*operands
)
12376 if (GET_CODE (operands
[0]) != REG
)
12379 if (GET_CODE (operands
[1]) != MEM
)
12382 /* Get the memory address. */
12383 addr
= XEXP (operands
[1], 0);
12385 /* Work out how the memory address is computed. */
12386 switch (GET_CODE (addr
))
12389 operands
[2] = gen_rtx (MEM
, SImode
,
12390 plus_constant (XEXP (operands
[1], 0), 4));
12392 if (REGNO (operands
[0]) == REGNO (addr
))
12394 output_asm_insn ("ldr\t%H0, %2", operands
);
12395 output_asm_insn ("ldr\t%0, %1", operands
);
12399 output_asm_insn ("ldr\t%0, %1", operands
);
12400 output_asm_insn ("ldr\t%H0, %2", operands
);
12405 /* Compute <address> + 4 for the high order load. */
12406 operands
[2] = gen_rtx (MEM
, SImode
,
12407 plus_constant (XEXP (operands
[1], 0), 4));
12409 output_asm_insn ("ldr\t%0, %1", operands
);
12410 output_asm_insn ("ldr\t%H0, %2", operands
);
12414 arg1
= XEXP (addr
, 0);
12415 arg2
= XEXP (addr
, 1);
12417 if (CONSTANT_P (arg1
))
12418 base
= arg2
, offset
= arg1
;
12420 base
= arg1
, offset
= arg2
;
12422 if (GET_CODE (base
) != REG
)
12425 /* Catch the case of <address> = <reg> + <reg> */
12426 if (GET_CODE (offset
) == REG
)
12428 int reg_offset
= REGNO (offset
);
12429 int reg_base
= REGNO (base
);
12430 int reg_dest
= REGNO (operands
[0]);
12432 /* Add the base and offset registers together into the
12433 higher destination register. */
12434 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
12435 reg_dest
+ 1, reg_base
, reg_offset
);
12437 /* Load the lower destination register from the address in
12438 the higher destination register. */
12439 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
12440 reg_dest
, reg_dest
+ 1);
12442 /* Load the higher destination register from its own address
12444 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
12445 reg_dest
+ 1, reg_dest
+ 1);
12449 /* Compute <address> + 4 for the high order load. */
12450 operands
[2] = gen_rtx (MEM
, SImode
,
12451 plus_constant (XEXP (operands
[1], 0), 4));
12453 /* If the computed address is held in the low order register
12454 then load the high order register first, otherwise always
12455 load the low order register first. */
12456 if (REGNO (operands
[0]) == REGNO (base
))
12458 output_asm_insn ("ldr\t%H0, %2", operands
);
12459 output_asm_insn ("ldr\t%0, %1", operands
);
12463 output_asm_insn ("ldr\t%0, %1", operands
);
12464 output_asm_insn ("ldr\t%H0, %2", operands
);
12470 /* With no registers to worry about we can just load the value
12472 operands
[2] = gen_rtx (MEM
, SImode
,
12473 plus_constant (XEXP (operands
[1], 0), 4));
12475 output_asm_insn ("ldr\t%H0, %2", operands
);
12476 output_asm_insn ("ldr\t%0, %1", operands
);
12488 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
12495 if (REGNO (operands
[4]) > REGNO (operands
[5]))
12498 operands
[4] = operands
[5];
12501 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
12502 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
12506 if (REGNO (operands
[4]) > REGNO (operands
[5]))
12509 operands
[4] = operands
[5];
12512 if (REGNO (operands
[5]) > REGNO (operands
[6]))
12515 operands
[5] = operands
[6];
12518 if (REGNO (operands
[4]) > REGNO (operands
[5]))
12521 operands
[4] = operands
[5];
12525 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
12526 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
12536 /* Routines for generating rtl. */
12538 thumb_expand_movstrqi (rtx
*operands
)
12540 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
12541 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
12542 HOST_WIDE_INT len
= INTVAL (operands
[2]);
12543 HOST_WIDE_INT offset
= 0;
12547 emit_insn (gen_movmem12b (out
, in
, out
, in
));
12553 emit_insn (gen_movmem8b (out
, in
, out
, in
));
12559 rtx reg
= gen_reg_rtx (SImode
);
12560 emit_insn (gen_movsi (reg
, gen_rtx (MEM
, SImode
, in
)));
12561 emit_insn (gen_movsi (gen_rtx (MEM
, SImode
, out
), reg
));
12568 rtx reg
= gen_reg_rtx (HImode
);
12569 emit_insn (gen_movhi (reg
, gen_rtx (MEM
, HImode
,
12570 plus_constant (in
, offset
))));
12571 emit_insn (gen_movhi (gen_rtx (MEM
, HImode
, plus_constant (out
, offset
)),
12579 rtx reg
= gen_reg_rtx (QImode
);
12580 emit_insn (gen_movqi (reg
, gen_rtx (MEM
, QImode
,
12581 plus_constant (in
, offset
))));
12582 emit_insn (gen_movqi (gen_rtx (MEM
, QImode
, plus_constant (out
, offset
)),
12588 thumb_cmp_operand (rtx op
, enum machine_mode mode
)
12590 return ((GET_CODE (op
) == CONST_INT
12591 && (unsigned HOST_WIDE_INT
) (INTVAL (op
)) < 256)
12592 || register_operand (op
, mode
));
12595 static const char *
12596 thumb_condition_code (rtx x
, int invert
)
12598 static const char * const conds
[] =
12600 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
12601 "hi", "ls", "ge", "lt", "gt", "le"
12605 switch (GET_CODE (x
))
12607 case EQ
: val
= 0; break;
12608 case NE
: val
= 1; break;
12609 case GEU
: val
= 2; break;
12610 case LTU
: val
= 3; break;
12611 case GTU
: val
= 8; break;
12612 case LEU
: val
= 9; break;
12613 case GE
: val
= 10; break;
12614 case LT
: val
= 11; break;
12615 case GT
: val
= 12; break;
12616 case LE
: val
= 13; break;
12621 return conds
[val
^ invert
];
12624 /* Handle storing a half-word to memory during reload. */
12626 thumb_reload_out_hi (rtx
*operands
)
12628 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
12631 /* Handle reading a half-word from memory during reload. */
12633 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
12638 /* Return the length of a function name prefix
12639 that starts with the character 'c'. */
12641 arm_get_strip_length (int c
)
12645 ARM_NAME_ENCODING_LENGTHS
12650 /* Return a pointer to a function's name with any
12651 and all prefix encodings stripped from it. */
12653 arm_strip_name_encoding (const char *name
)
12657 while ((skip
= arm_get_strip_length (* name
)))
12663 /* If there is a '*' anywhere in the name's prefix, then
12664 emit the stripped name verbatim, otherwise prepend an
12665 underscore if leading underscores are being used. */
12667 arm_asm_output_labelref (FILE *stream
, const char *name
)
12672 while ((skip
= arm_get_strip_length (* name
)))
12674 verbatim
|= (*name
== '*');
12679 fputs (name
, stream
);
12681 asm_fprintf (stream
, "%U%s", name
);
12686 #ifdef AOF_ASSEMBLER
12687 /* Special functions only needed when producing AOF syntax assembler. */
12691 struct pic_chain
* next
;
12692 const char * symname
;
12695 static struct pic_chain
* aof_pic_chain
= NULL
;
12698 aof_pic_entry (rtx x
)
12700 struct pic_chain
** chainp
;
12703 if (aof_pic_label
== NULL_RTX
)
12705 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
12708 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
12709 offset
+= 4, chainp
= &(*chainp
)->next
)
12710 if ((*chainp
)->symname
== XSTR (x
, 0))
12711 return plus_constant (aof_pic_label
, offset
);
12713 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
12714 (*chainp
)->next
= NULL
;
12715 (*chainp
)->symname
= XSTR (x
, 0);
12716 return plus_constant (aof_pic_label
, offset
);
12720 aof_dump_pic_table (FILE *f
)
12722 struct pic_chain
* chain
;
12724 if (aof_pic_chain
== NULL
)
12727 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
12728 PIC_OFFSET_TABLE_REGNUM
,
12729 PIC_OFFSET_TABLE_REGNUM
);
12730 fputs ("|x$adcons|\n", f
);
12732 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
12734 fputs ("\tDCD\t", f
);
12735 assemble_name (f
, chain
->symname
);
12740 int arm_text_section_count
= 1;
12743 aof_text_section (void )
12745 static char buf
[100];
12746 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
12747 arm_text_section_count
++);
12749 strcat (buf
, ", PIC, REENTRANT");
12753 static int arm_data_section_count
= 1;
12756 aof_data_section (void)
12758 static char buf
[100];
12759 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
12763 /* The AOF assembler is religiously strict about declarations of
12764 imported and exported symbols, so that it is impossible to declare
12765 a function as imported near the beginning of the file, and then to
12766 export it later on. It is, however, possible to delay the decision
12767 until all the functions in the file have been compiled. To get
12768 around this, we maintain a list of the imports and exports, and
12769 delete from it any that are subsequently defined. At the end of
12770 compilation we spit the remainder of the list out before the END
12775 struct import
* next
;
12779 static struct import
* imports_list
= NULL
;
12782 aof_add_import (const char *name
)
12784 struct import
* new;
12786 for (new = imports_list
; new; new = new->next
)
12787 if (new->name
== name
)
12790 new = (struct import
*) xmalloc (sizeof (struct import
));
12791 new->next
= imports_list
;
12792 imports_list
= new;
12797 aof_delete_import (const char *name
)
12799 struct import
** old
;
12801 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
12803 if ((*old
)->name
== name
)
12805 *old
= (*old
)->next
;
12811 int arm_main_function
= 0;
12814 aof_dump_imports (FILE *f
)
12816 /* The AOF assembler needs this to cause the startup code to be extracted
12817 from the library. Brining in __main causes the whole thing to work
12819 if (arm_main_function
)
12822 fputs ("\tIMPORT __main\n", f
);
12823 fputs ("\tDCD __main\n", f
);
12826 /* Now dump the remaining imports. */
12827 while (imports_list
)
12829 fprintf (f
, "\tIMPORT\t");
12830 assemble_name (f
, imports_list
->name
);
12832 imports_list
= imports_list
->next
;
12837 aof_globalize_label (FILE *stream
, const char *name
)
12839 default_globalize_label (stream
, name
);
12840 if (! strcmp (name
, "main"))
12841 arm_main_function
= 1;
12847 fputs ("__r0\tRN\t0\n", asm_out_file
);
12848 fputs ("__a1\tRN\t0\n", asm_out_file
);
12849 fputs ("__a2\tRN\t1\n", asm_out_file
);
12850 fputs ("__a3\tRN\t2\n", asm_out_file
);
12851 fputs ("__a4\tRN\t3\n", asm_out_file
);
12852 fputs ("__v1\tRN\t4\n", asm_out_file
);
12853 fputs ("__v2\tRN\t5\n", asm_out_file
);
12854 fputs ("__v3\tRN\t6\n", asm_out_file
);
12855 fputs ("__v4\tRN\t7\n", asm_out_file
);
12856 fputs ("__v5\tRN\t8\n", asm_out_file
);
12857 fputs ("__v6\tRN\t9\n", asm_out_file
);
12858 fputs ("__sl\tRN\t10\n", asm_out_file
);
12859 fputs ("__fp\tRN\t11\n", asm_out_file
);
12860 fputs ("__ip\tRN\t12\n", asm_out_file
);
12861 fputs ("__sp\tRN\t13\n", asm_out_file
);
12862 fputs ("__lr\tRN\t14\n", asm_out_file
);
12863 fputs ("__pc\tRN\t15\n", asm_out_file
);
12864 fputs ("__f0\tFN\t0\n", asm_out_file
);
12865 fputs ("__f1\tFN\t1\n", asm_out_file
);
12866 fputs ("__f2\tFN\t2\n", asm_out_file
);
12867 fputs ("__f3\tFN\t3\n", asm_out_file
);
12868 fputs ("__f4\tFN\t4\n", asm_out_file
);
12869 fputs ("__f5\tFN\t5\n", asm_out_file
);
12870 fputs ("__f6\tFN\t6\n", asm_out_file
);
12871 fputs ("__f7\tFN\t7\n", asm_out_file
);
12876 aof_file_end (void)
12879 aof_dump_pic_table (asm_out_file
);
12880 aof_dump_imports (asm_out_file
);
12881 fputs ("\tEND\n", asm_out_file
);
12883 #endif /* AOF_ASSEMBLER */
12885 #ifdef OBJECT_FORMAT_ELF
12886 /* Switch to an arbitrary section NAME with attributes as specified
12887 by FLAGS. ALIGN specifies any known alignment requirements for
12888 the section; 0 if the default should be used.
12890 Differs from the default elf version only in the prefix character
12891 used before the section type. */
12894 arm_elf_asm_named_section (const char *name
, unsigned int flags
)
12896 char flagchars
[10], *f
= flagchars
;
12898 if (! named_section_first_declaration (name
))
12900 fprintf (asm_out_file
, "\t.section\t%s\n", name
);
12904 if (!(flags
& SECTION_DEBUG
))
12906 if (flags
& SECTION_WRITE
)
12908 if (flags
& SECTION_CODE
)
12910 if (flags
& SECTION_SMALL
)
12912 if (flags
& SECTION_MERGE
)
12914 if (flags
& SECTION_STRINGS
)
12916 if (flags
& SECTION_TLS
)
12920 fprintf (asm_out_file
, "\t.section\t%s,\"%s\"", name
, flagchars
);
12922 if (!(flags
& SECTION_NOTYPE
))
12926 if (flags
& SECTION_BSS
)
12931 fprintf (asm_out_file
, ",%%%s", type
);
12933 if (flags
& SECTION_ENTSIZE
)
12934 fprintf (asm_out_file
, ",%d", flags
& SECTION_ENTSIZE
);
12937 putc ('\n', asm_out_file
);
12942 /* Symbols in the text segment can be accessed without indirecting via the
12943 constant pool; it may take an extra binary operation, but this is still
12944 faster than indirecting via memory. Don't do this when not optimizing,
12945 since we won't be calculating al of the offsets necessary to do this
12949 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
12951 /* This doesn't work with AOF syntax, since the string table may be in
12952 a different AREA. */
12953 #ifndef AOF_ASSEMBLER
12954 if (optimize
> 0 && TREE_CONSTANT (decl
)
12955 && (!flag_writable_strings
|| TREE_CODE (decl
) != STRING_CST
))
12956 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
12959 /* If we are referencing a function that is weak then encode a long call
12960 flag in the function name, otherwise if the function is static or
12961 or known to be defined in this file then encode a short call flag. */
12962 if (first
&& TREE_CODE_CLASS (TREE_CODE (decl
)) == 'd')
12964 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
12965 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
12966 else if (! TREE_PUBLIC (decl
))
12967 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
12970 #endif /* !ARM_PE */
12973 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
12975 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
12976 && !strcmp (prefix
, "L"))
12978 arm_ccfsm_state
= 0;
12979 arm_target_insn
= NULL
;
12981 default_internal_label (stream
, prefix
, labelno
);
12984 /* Output code to add DELTA to the first argument, and then jump
12985 to FUNCTION. Used for C++ multiple inheritance. */
12987 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
12988 HOST_WIDE_INT delta
,
12989 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
12992 int mi_delta
= delta
;
12993 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
12995 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)))
12998 mi_delta
= - mi_delta
;
12999 while (mi_delta
!= 0)
13001 if ((mi_delta
& (3 << shift
)) == 0)
13005 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
13006 mi_op
, this_regno
, this_regno
,
13007 mi_delta
& (0xff << shift
));
13008 mi_delta
&= ~(0xff << shift
);
13012 fputs ("\tb\t", file
);
13013 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
13014 if (NEED_PLT_RELOC
)
13015 fputs ("(PLT)", file
);
13016 fputc ('\n', file
);
13020 arm_emit_vector_const (file
, x
)
13025 const char * pattern
;
13027 if (GET_CODE (x
) != CONST_VECTOR
)
13030 switch (GET_MODE (x
))
13032 case V2SImode
: pattern
= "%08x"; break;
13033 case V4HImode
: pattern
= "%04x"; break;
13034 case V8QImode
: pattern
= "%02x"; break;
13038 fprintf (file
, "0x");
13039 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
13043 element
= CONST_VECTOR_ELT (x
, i
);
13044 fprintf (file
, pattern
, INTVAL (element
));
13051 arm_output_load_gr (operands
)
13059 if (GET_CODE (operands
[1]) != MEM
13060 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
13061 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
13062 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
13063 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
13064 return "wldrw%?\t%0, %1";
13066 /* Fix up an out-of-range load of a GR register. */
13067 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
13068 wcgr
= operands
[0];
13070 output_asm_insn ("ldr%?\t%0, %1", operands
);
13072 operands
[0] = wcgr
;
13074 output_asm_insn ("tmcr%?\t%0, %1", operands
);
13075 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);