1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode
;
58 typedef struct minipool_fixup Mfix
;
60 const struct attribute_spec arm_attribute_table
[];
62 /* Forward function declarations. */
63 static arm_stack_offsets
*arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, rtx
,
66 HOST_WIDE_INT
, rtx
, rtx
, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx
, int);
69 static int arm_legitimate_index_p (enum machine_mode
, rtx
, RTX_CODE
, int);
70 static int thumb_base_register_rtx_p (rtx
, enum machine_mode
, int);
71 inline static int thumb_index_register_rtx_p (rtx
, int);
72 static int thumb_far_jump_used_p (void);
73 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
74 static rtx
emit_multi_reg_push (int);
75 static rtx
emit_sfm (int, int);
77 static bool arm_assemble_integer (rtx
, unsigned int, int);
79 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
80 static arm_cc
get_arm_condition_code (rtx
);
81 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
82 static rtx
is_jump_table (rtx
);
83 static const char *output_multi_immediate (rtx
*, const char *, const char *,
85 static void print_multi_reg (FILE *, const char *, int, int);
86 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
87 static struct machine_function
*arm_init_machine_status (void);
88 static int number_of_first_bit_set (int);
89 static void replace_symbols_in_block (tree
, rtx
, rtx
);
90 static void thumb_exit (FILE *, int);
91 static void thumb_pushpop (FILE *, int, int, int *, int);
92 static rtx
is_jump_table (rtx
);
93 static HOST_WIDE_INT
get_jump_table_size (rtx
);
94 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
95 static Mnode
*add_minipool_forward_ref (Mfix
*);
96 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
97 static Mnode
*add_minipool_backward_ref (Mfix
*);
98 static void assign_minipool_offsets (Mfix
*);
99 static void arm_print_value (FILE *, rtx
);
100 static void dump_minipool (rtx
);
101 static int arm_barrier_cost (rtx
);
102 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
103 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
104 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
106 static void arm_reorg (void);
107 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
108 static int current_file_function_operand (rtx
);
109 static unsigned long arm_compute_save_reg0_reg12_mask (void);
110 static unsigned long arm_compute_save_reg_mask (void);
111 static unsigned long arm_isr_value (tree
);
112 static unsigned long arm_compute_func_type (void);
113 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
114 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
115 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
116 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
117 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT
);
118 static int arm_comp_type_attributes (tree
, tree
);
119 static void arm_set_default_type_attributes (tree
);
120 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
121 static int count_insns_for_constant (HOST_WIDE_INT
, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree
, tree
);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
127 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
128 static bool arm_slowmul_rtx_costs (rtx
, int, int, int *);
129 static bool arm_fastmul_rtx_costs (rtx
, int, int, int *);
130 static bool arm_xscale_rtx_costs (rtx
, int, int, int *);
131 static bool arm_9e_rtx_costs (rtx
, int, int, int *);
132 static int arm_address_cost (rtx
);
133 static bool arm_memory_load_p (rtx
);
134 static bool arm_cirrus_insn_p (rtx
);
135 static void cirrus_reorg (rtx
);
136 static void arm_init_builtins (void);
137 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
138 static void arm_init_iwmmxt_builtins (void);
139 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
140 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
141 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
142 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
143 static void emit_constant_insn (rtx cond
, rtx pattern
);
145 #ifdef OBJECT_FORMAT_ELF
146 static void arm_elf_asm_named_section (const char *, unsigned int);
149 static void arm_encode_section_info (tree
, rtx
, int);
152 static void aof_globalize_label (FILE *, const char *);
153 static void aof_dump_imports (FILE *);
154 static void aof_dump_pic_table (FILE *);
155 static void aof_file_start (void);
156 static void aof_file_end (void);
158 static rtx
arm_struct_value_rtx (tree
, int);
159 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
161 static bool arm_pass_by_reference (CUMULATIVE_ARGS
*,
162 enum machine_mode
, tree
, bool);
163 static bool arm_promote_prototypes (tree
);
164 static bool arm_default_short_enums (void);
165 static bool arm_align_anon_bitfield (void);
167 static tree
arm_cxx_guard_type (void);
168 static bool arm_cxx_guard_mask_bit (void);
169 static tree
arm_get_cookie_size (tree
);
170 static bool arm_cookie_has_size (void);
171 static bool arm_cxx_cdtor_returns_this (void);
172 static void arm_init_libfuncs (void);
175 /* Initialize the GCC target structure. */
176 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
177 #undef TARGET_MERGE_DECL_ATTRIBUTES
178 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
181 #undef TARGET_ATTRIBUTE_TABLE
182 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
185 #undef TARGET_ASM_BYTE_OP
186 #define TARGET_ASM_BYTE_OP "\tDCB\t"
187 #undef TARGET_ASM_ALIGNED_HI_OP
188 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
189 #undef TARGET_ASM_ALIGNED_SI_OP
190 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
191 #undef TARGET_ASM_GLOBALIZE_LABEL
192 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
193 #undef TARGET_ASM_FILE_START
194 #define TARGET_ASM_FILE_START aof_file_start
195 #undef TARGET_ASM_FILE_END
196 #define TARGET_ASM_FILE_END aof_file_end
198 #undef TARGET_ASM_ALIGNED_SI_OP
199 #define TARGET_ASM_ALIGNED_SI_OP NULL
200 #undef TARGET_ASM_INTEGER
201 #define TARGET_ASM_INTEGER arm_assemble_integer
204 #undef TARGET_ASM_FUNCTION_PROLOGUE
205 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
207 #undef TARGET_ASM_FUNCTION_EPILOGUE
208 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
210 #undef TARGET_COMP_TYPE_ATTRIBUTES
211 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
213 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
214 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
216 #undef TARGET_SCHED_ADJUST_COST
217 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
219 #undef TARGET_ENCODE_SECTION_INFO
221 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
223 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
226 #undef TARGET_STRIP_NAME_ENCODING
227 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
229 #undef TARGET_ASM_INTERNAL_LABEL
230 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
232 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
233 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
235 #undef TARGET_ASM_OUTPUT_MI_THUNK
236 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
237 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
238 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
240 /* This will be overridden in arm_override_options. */
241 #undef TARGET_RTX_COSTS
242 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
243 #undef TARGET_ADDRESS_COST
244 #define TARGET_ADDRESS_COST arm_address_cost
246 #undef TARGET_MACHINE_DEPENDENT_REORG
247 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
249 #undef TARGET_INIT_BUILTINS
250 #define TARGET_INIT_BUILTINS arm_init_builtins
251 #undef TARGET_EXPAND_BUILTIN
252 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
254 #undef TARGET_INIT_LIBFUNCS
255 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
257 #undef TARGET_PROMOTE_FUNCTION_ARGS
258 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
259 #undef TARGET_PROMOTE_FUNCTION_RETURN
260 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
261 #undef TARGET_PROMOTE_PROTOTYPES
262 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
263 #undef TARGET_PASS_BY_REFERENCE
264 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
266 #undef TARGET_STRUCT_VALUE_RTX
267 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
269 #undef TARGET_SETUP_INCOMING_VARARGS
270 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
272 #undef TARGET_DEFAULT_SHORT_ENUMS
273 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
275 #undef TARGET_ALIGN_ANON_BITFIELD
276 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
278 #undef TARGET_CXX_GUARD_TYPE
279 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
281 #undef TARGET_CXX_GUARD_MASK_BIT
282 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
284 #undef TARGET_CXX_GET_COOKIE_SIZE
285 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
287 #undef TARGET_CXX_COOKIE_HAS_SIZE
288 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
290 #undef TARGET_CXX_CDTOR_RETURNS_THIS
291 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
293 struct gcc_target targetm
= TARGET_INITIALIZER
;
295 /* Obstack for minipool constant handling. */
296 static struct obstack minipool_obstack
;
297 static char * minipool_startobj
;
299 /* The maximum number of insns skipped which
300 will be conditionalised if possible. */
301 static int max_insns_skipped
= 5;
303 extern FILE * asm_out_file
;
305 /* True if we are currently building a constant table. */
306 int making_const_table
;
308 /* Define the information needed to generate branch insns. This is
309 stored from the compare operation. */
310 rtx arm_compare_op0
, arm_compare_op1
;
312 /* The processor for which instructions should be scheduled. */
313 enum processor_type arm_tune
= arm_none
;
315 /* Which floating point model to use. */
316 enum arm_fp_model arm_fp_model
;
318 /* Which floating point hardware is available. */
319 enum fputype arm_fpu_arch
;
321 /* Which floating point hardware to schedule for. */
322 enum fputype arm_fpu_tune
;
324 /* Whether to use floating point hardware. */
325 enum float_abi_type arm_float_abi
;
327 /* Which ABI to use. */
328 enum arm_abi_type arm_abi
;
330 /* Set by the -mfpu=... option. */
331 const char * target_fpu_name
= NULL
;
333 /* Set by the -mfpe=... option. */
334 const char * target_fpe_name
= NULL
;
336 /* Set by the -mfloat-abi=... option. */
337 const char * target_float_abi_name
= NULL
;
339 /* Set by the -mabi=... option. */
340 const char * target_abi_name
= NULL
;
342 /* Used to parse -mstructure_size_boundary command line option. */
343 const char * structure_size_string
= NULL
;
344 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
346 /* Bit values used to identify processor capabilities. */
347 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
348 #define FL_ARCH3M (1 << 1) /* Extended multiply */
349 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
350 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
351 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
352 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
353 #define FL_THUMB (1 << 6) /* Thumb aware */
354 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
355 #define FL_STRONG (1 << 8) /* StrongARM */
356 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
357 #define FL_XSCALE (1 << 10) /* XScale */
358 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
359 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
360 media instructions. */
361 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
363 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
365 #define FL_FOR_ARCH2 0
366 #define FL_FOR_ARCH3 FL_MODE32
367 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
368 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
369 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
370 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
371 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
372 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
373 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
374 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
375 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
376 #define FL_FOR_ARCH6J FL_FOR_ARCH6
378 /* The bits in this mask specify which
379 instructions we are allowed to generate. */
380 static unsigned long insn_flags
= 0;
382 /* The bits in this mask specify which instruction scheduling options should
384 static unsigned long tune_flags
= 0;
386 /* The following are used in the arm.md file as equivalents to bits
387 in the above two flag variables. */
389 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
392 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
395 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
398 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
401 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
404 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
407 /* Nonzero if this chip can benefit from load scheduling. */
408 int arm_ld_sched
= 0;
410 /* Nonzero if this chip is a StrongARM. */
411 int arm_is_strong
= 0;
413 /* Nonzero if this chip is a Cirrus variant. */
414 int arm_arch_cirrus
= 0;
416 /* Nonzero if this chip supports Intel Wireless MMX technology. */
417 int arm_arch_iwmmxt
= 0;
419 /* Nonzero if this chip is an XScale. */
420 int arm_arch_xscale
= 0;
422 /* Nonzero if tuning for XScale */
423 int arm_tune_xscale
= 0;
425 /* Nonzero if this chip is an ARM6 or an ARM7. */
426 int arm_is_6_or_7
= 0;
428 /* Nonzero if generating Thumb instructions. */
431 /* Nonzero if we should define __THUMB_INTERWORK__ in the
433 XXX This is a bit of a hack, it's intended to help work around
434 problems in GLD which doesn't understand that armv5t code is
435 interworking clean. */
436 int arm_cpp_interwork
= 0;
438 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
439 must report the mode of the memory reference from PRINT_OPERAND to
440 PRINT_OPERAND_ADDRESS. */
441 enum machine_mode output_memory_reference_mode
;
443 /* The register number to be used for the PIC offset register. */
444 const char * arm_pic_register_string
= NULL
;
445 int arm_pic_register
= INVALID_REGNUM
;
447 /* Set to 1 when a return insn is output, this means that the epilogue
449 int return_used_this_function
;
451 /* Set to 1 after arm_reorg has started. Reset to start at the start of
452 the next function. */
453 static int after_arm_reorg
= 0;
455 /* The maximum number of insns to be used when loading a constant. */
456 static int arm_constant_limit
= 3;
458 /* For an explanation of these variables, see final_prescan_insn below. */
460 enum arm_cond_code arm_current_cc
;
462 int arm_target_label
;
464 /* The condition codes of the ARM, and the inverse function. */
465 static const char * const arm_condition_codes
[] =
467 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
468 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
471 #define streq(string1, string2) (strcmp (string1, string2) == 0)
473 /* Initialization code. */
477 const char *const name
;
478 enum processor_type core
;
480 const unsigned long flags
;
481 bool (* rtx_costs
) (rtx
, int, int, int *);
484 /* Not all of these give usefully different compilation alternatives,
485 but there is no simple way of generalizing them. */
486 static const struct processors all_cores
[] =
489 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
490 {#NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
491 #include "arm-cores.def"
493 {NULL
, arm_none
, NULL
, 0, NULL
}
496 static const struct processors all_architectures
[] =
498 /* ARM Architectures */
499 /* We don't specify rtx_costs here as it will be figured out
502 {"armv2", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
503 {"armv2a", arm2
, "2", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH2
, NULL
},
504 {"armv3", arm6
, "3", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3
, NULL
},
505 {"armv3m", arm7m
, "3M", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH3M
, NULL
},
506 {"armv4", arm7tdmi
, "4", FL_CO_PROC
| FL_MODE26
| FL_FOR_ARCH4
, NULL
},
507 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
508 implementations that support it, so we will leave it out for now. */
509 {"armv4t", arm7tdmi
, "4T", FL_CO_PROC
| FL_FOR_ARCH4T
, NULL
},
510 {"armv5", arm10tdmi
, "5", FL_CO_PROC
| FL_FOR_ARCH5
, NULL
},
511 {"armv5t", arm10tdmi
, "5T", FL_CO_PROC
| FL_FOR_ARCH5T
, NULL
},
512 {"armv5e", arm1026ejs
, "5E", FL_CO_PROC
| FL_FOR_ARCH5E
, NULL
},
513 {"armv5te", arm1026ejs
, "5TE", FL_CO_PROC
| FL_FOR_ARCH5TE
, NULL
},
514 {"armv6", arm1136js
, "6", FL_CO_PROC
| FL_FOR_ARCH6
, NULL
},
515 {"armv6j", arm1136js
, "6J", FL_CO_PROC
| FL_FOR_ARCH6J
, NULL
},
516 {"ep9312", ep9312
, "4T", FL_LDSCHED
| FL_CIRRUS
| FL_FOR_ARCH4
, NULL
},
517 {"iwmmxt", iwmmxt
, "5TE", FL_LDSCHED
| FL_STRONG
| FL_FOR_ARCH5TE
| FL_XSCALE
| FL_IWMMXT
, NULL
},
518 {NULL
, arm_none
, NULL
, 0 , NULL
}
521 /* This is a magic structure. The 'string' field is magically filled in
522 with a pointer to the value specified by the user on the command line
523 assuming that the user has specified such a value. */
525 struct arm_cpu_select arm_select
[] =
527 /* string name processors */
528 { NULL
, "-mcpu=", all_cores
},
529 { NULL
, "-march=", all_architectures
},
530 { NULL
, "-mtune=", all_cores
}
534 /* The name of the proprocessor macro to define for this architecture. */
536 char arm_arch_name
[] = "__ARM_ARCH_0UNK__";
545 /* Available values for for -mfpu=. */
547 static const struct fpu_desc all_fpus
[] =
549 {"fpa", FPUTYPE_FPA
},
550 {"fpe2", FPUTYPE_FPA_EMU2
},
551 {"fpe3", FPUTYPE_FPA_EMU2
},
552 {"maverick", FPUTYPE_MAVERICK
},
557 /* Floating point models used by the different hardware.
558 See fputype in arm.h. */
560 static const enum fputype fp_model_for_fpu
[] =
562 /* No FP hardware. */
563 ARM_FP_MODEL_UNKNOWN
, /* FPUTYPE_NONE */
564 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA */
565 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU2 */
566 ARM_FP_MODEL_FPA
, /* FPUTYPE_FPA_EMU3 */
567 ARM_FP_MODEL_MAVERICK
, /* FPUTYPE_MAVERICK */
568 ARM_FP_MODEL_VFP
/* FPUTYPE_VFP */
575 enum float_abi_type abi_type
;
579 /* Available values for -mfloat-abi=. */
581 static const struct float_abi all_float_abis
[] =
583 {"soft", ARM_FLOAT_ABI_SOFT
},
584 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
585 {"hard", ARM_FLOAT_ABI_HARD
}
592 enum arm_abi_type abi_type
;
596 /* Available values for -mabi=. */
598 static const struct abi_name arm_all_abis
[] =
600 {"apcs-gnu", ARM_ABI_APCS
},
601 {"atpcs", ARM_ABI_ATPCS
},
602 {"aapcs", ARM_ABI_AAPCS
},
603 {"iwmmxt", ARM_ABI_IWMMXT
}
606 /* Return the number of bits set in VALUE. */
608 bit_count (unsigned long value
)
610 unsigned long count
= 0;
615 value
&= value
- 1; /* Clear the least-significant set bit. */
621 /* Set up library functions uqniue to ARM. */
624 arm_init_libfuncs (void)
626 /* There are no special library functions unless we are using the
631 /* The functions below are described in Section 4 of the "Run-Time
632 ABI for the ARM architecture", Version 1.0. */
634 /* Double-precision floating-point arithmetic. Table 2. */
635 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
636 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
637 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
638 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
639 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
641 /* Double-precision comparisions. Table 3. */
642 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
643 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
644 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
645 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
646 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
647 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
648 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
650 /* Single-precision floating-point arithmetic. Table 4. */
651 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
652 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
653 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
654 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
655 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
657 /* Single-precision comparisions. Table 5. */
658 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
659 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
660 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
661 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
662 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
663 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
664 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
666 /* Floating-point to integer conversions. Table 6. */
667 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
668 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
669 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
670 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
671 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
672 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
673 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
674 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
676 /* Conversions between floating types. Table 7. */
677 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
678 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
680 /* Integer to floating-point converisons. Table 8. */
681 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
682 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
683 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
684 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
685 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
686 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
687 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
688 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
690 /* Long long. Table 9. */
691 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
692 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
693 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
694 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
695 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
696 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
697 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
698 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
700 /* Integer (32/32->32) division. \S 4.3.1. */
701 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
702 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
704 /* The divmod functions are designed so that they can be used for
705 plain division, even though they return both the quotient and the
706 remainder. The quotient is returned in the usual location (i.e.,
707 r0 for SImode, {r0, r1} for DImode), just as would be expected
708 for an ordinary division routine. Because the AAPCS calling
709 conventions specify that all of { r0, r1, r2, r3 } are
710 callee-saved registers, there is no need to tell the compiler
711 explicitly that those registers are clobbered by these
713 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
714 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
715 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idivmod");
716 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidivmod");
719 /* Fix up any incompatible options that the user has specified.
720 This has now turned into a maze. */
722 arm_override_options (void)
726 /* Set up the flags based on the cpu/architecture selected by the user. */
727 for (i
= ARRAY_SIZE (arm_select
); i
--;)
729 struct arm_cpu_select
* ptr
= arm_select
+ i
;
731 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
733 const struct processors
* sel
;
735 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
736 if (streq (ptr
->string
, sel
->name
))
738 /* Set the architecture define. */
740 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
742 /* Determine the processor core for which we should
743 tune code-generation. */
744 if (/* -mcpu= is a sensible default. */
746 /* If -march= is used, and -mcpu= has not been used,
747 assume that we should tune for a representative
748 CPU from that architecture. */
750 /* -mtune= overrides -mcpu= and -march=. */
752 arm_tune
= (enum processor_type
) (sel
- ptr
->processors
);
756 /* If we have been given an architecture and a processor
757 make sure that they are compatible. We only generate
758 a warning though, and we prefer the CPU over the
760 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
761 warning ("switch -mcpu=%s conflicts with -march= switch",
764 insn_flags
= sel
->flags
;
770 if (sel
->name
== NULL
)
771 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
775 /* If the user did not specify a processor, choose one for them. */
778 const struct processors
* sel
;
780 enum processor_type cpu
;
782 cpu
= TARGET_CPU_DEFAULT
;
785 #ifdef SUBTARGET_CPU_DEFAULT
786 /* Use the subtarget default CPU if none was specified by
788 cpu
= SUBTARGET_CPU_DEFAULT
;
790 /* Default to ARM6. */
794 sel
= &all_cores
[cpu
];
796 insn_flags
= sel
->flags
;
798 /* Now check to see if the user has specified some command line
799 switch that require certain abilities from the cpu. */
802 if (TARGET_INTERWORK
|| TARGET_THUMB
)
804 sought
|= (FL_THUMB
| FL_MODE32
);
806 /* There are no ARM processors that support both APCS-26 and
807 interworking. Therefore we force FL_MODE26 to be removed
808 from insn_flags here (if it was set), so that the search
809 below will always be able to find a compatible processor. */
810 insn_flags
&= ~FL_MODE26
;
813 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
815 /* Try to locate a CPU type that supports all of the abilities
816 of the default CPU, plus the extra abilities requested by
818 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
819 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
822 if (sel
->name
== NULL
)
824 unsigned current_bit_count
= 0;
825 const struct processors
* best_fit
= NULL
;
827 /* Ideally we would like to issue an error message here
828 saying that it was not possible to find a CPU compatible
829 with the default CPU, but which also supports the command
830 line options specified by the programmer, and so they
831 ought to use the -mcpu=<name> command line option to
832 override the default CPU type.
834 If we cannot find a cpu that has both the
835 characteristics of the default cpu and the given
836 command line options we scan the array again looking
838 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
839 if ((sel
->flags
& sought
) == sought
)
843 count
= bit_count (sel
->flags
& insn_flags
);
845 if (count
>= current_bit_count
)
848 current_bit_count
= count
;
852 if (best_fit
== NULL
)
858 insn_flags
= sel
->flags
;
860 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", sel
->arch
);
861 if (arm_tune
== arm_none
)
862 arm_tune
= (enum processor_type
) (sel
- all_cores
);
865 /* The processor for which we should tune should now have been
867 if (arm_tune
== arm_none
)
870 tune_flags
= all_cores
[(int)arm_tune
].flags
;
871 targetm
.rtx_costs
= all_cores
[(int)arm_tune
].rtx_costs
;
873 /* Make sure that the processor choice does not conflict with any of the
874 other command line choices. */
875 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
877 warning ("target CPU does not support interworking" );
878 target_flags
&= ~ARM_FLAG_INTERWORK
;
881 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
883 warning ("target CPU does not support THUMB instructions");
884 target_flags
&= ~ARM_FLAG_THUMB
;
887 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
889 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
890 target_flags
&= ~ARM_FLAG_APCS_FRAME
;
893 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
894 from here where no function is being compiled currently. */
895 if ((target_flags
& (THUMB_FLAG_LEAF_BACKTRACE
| THUMB_FLAG_BACKTRACE
))
897 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
899 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
900 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
902 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
903 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
905 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
907 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
908 target_flags
|= ARM_FLAG_APCS_FRAME
;
911 if (TARGET_POKE_FUNCTION_NAME
)
912 target_flags
|= ARM_FLAG_APCS_FRAME
;
914 if (TARGET_APCS_REENT
&& flag_pic
)
915 error ("-fpic and -mapcs-reent are incompatible");
917 if (TARGET_APCS_REENT
)
918 warning ("APCS reentrant code not supported. Ignored");
920 /* If this target is normally configured to use APCS frames, warn if they
921 are turned off and debugging is turned on. */
923 && write_symbols
!= NO_DEBUG
924 && !TARGET_APCS_FRAME
925 && (TARGET_DEFAULT
& ARM_FLAG_APCS_FRAME
))
926 warning ("-g with -mno-apcs-frame may not give sensible debugging");
928 /* If stack checking is disabled, we can use r10 as the PIC register,
929 which keeps r9 available. */
931 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
933 if (TARGET_APCS_FLOAT
)
934 warning ("passing floating point arguments in fp regs not yet supported");
936 /* Initialize boolean versions of the flags, for use in the arm.md file. */
937 arm_arch3m
= (insn_flags
& FL_ARCH3M
) != 0;
938 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
939 arm_arch4t
= arm_arch4
& ((insn_flags
& FL_THUMB
) != 0);
940 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
941 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
942 arm_arch6
= (insn_flags
& FL_ARCH6
) != 0;
943 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
944 arm_arch_cirrus
= (insn_flags
& FL_CIRRUS
) != 0;
946 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
947 arm_is_strong
= (tune_flags
& FL_STRONG
) != 0;
948 thumb_code
= (TARGET_ARM
== 0);
949 arm_is_6_or_7
= (((tune_flags
& (FL_MODE26
| FL_MODE32
))
950 && !(tune_flags
& FL_ARCH4
))) != 0;
951 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
952 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
954 /* V5 code we generate is completely interworking capable, so we turn off
955 TARGET_INTERWORK here to avoid many tests later on. */
957 /* XXX However, we must pass the right pre-processor defines to CPP
958 or GLD can get confused. This is a hack. */
959 if (TARGET_INTERWORK
)
960 arm_cpp_interwork
= 1;
963 target_flags
&= ~ARM_FLAG_INTERWORK
;
967 for (i
= 0; i
< ARRAY_SIZE (arm_all_abis
); i
++)
969 if (streq (arm_all_abis
[i
].name
, target_abi_name
))
971 arm_abi
= arm_all_abis
[i
].abi_type
;
975 if (i
== ARRAY_SIZE (arm_all_abis
))
976 error ("invalid ABI option: -mabi=%s", target_abi_name
);
979 arm_abi
= ARM_DEFAULT_ABI
;
981 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
982 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
984 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
985 error ("iwmmxt abi requires an iwmmxt capable cpu");
987 arm_fp_model
= ARM_FP_MODEL_UNKNOWN
;
988 if (target_fpu_name
== NULL
&& target_fpe_name
!= NULL
)
990 if (streq (target_fpe_name
, "2"))
991 target_fpu_name
= "fpe2";
992 else if (streq (target_fpe_name
, "3"))
993 target_fpu_name
= "fpe3";
995 error ("invalid floating point emulation option: -mfpe=%s",
998 if (target_fpu_name
!= NULL
)
1000 /* The user specified a FPU. */
1001 for (i
= 0; i
< ARRAY_SIZE (all_fpus
); i
++)
1003 if (streq (all_fpus
[i
].name
, target_fpu_name
))
1005 arm_fpu_arch
= all_fpus
[i
].fpu
;
1006 arm_fpu_tune
= arm_fpu_arch
;
1007 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1011 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
1012 error ("invalid floating point option: -mfpu=%s", target_fpu_name
);
1016 #ifdef FPUTYPE_DEFAULT
1017 /* Use the default if it is specified for this platform. */
1018 arm_fpu_arch
= FPUTYPE_DEFAULT
;
1019 arm_fpu_tune
= FPUTYPE_DEFAULT
;
1021 /* Pick one based on CPU type. */
1022 /* ??? Some targets assume FPA is the default.
1023 if ((insn_flags & FL_VFP) != 0)
1024 arm_fpu_arch = FPUTYPE_VFP;
1027 if (arm_arch_cirrus
)
1028 arm_fpu_arch
= FPUTYPE_MAVERICK
;
1030 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
1032 if (tune_flags
& FL_CO_PROC
&& arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
1033 arm_fpu_tune
= FPUTYPE_FPA
;
1035 arm_fpu_tune
= arm_fpu_arch
;
1036 arm_fp_model
= fp_model_for_fpu
[arm_fpu_arch
];
1037 if (arm_fp_model
== ARM_FP_MODEL_UNKNOWN
)
1041 if (target_float_abi_name
!= NULL
)
1043 /* The user specified a FP ABI. */
1044 for (i
= 0; i
< ARRAY_SIZE (all_float_abis
); i
++)
1046 if (streq (all_float_abis
[i
].name
, target_float_abi_name
))
1048 arm_float_abi
= all_float_abis
[i
].abi_type
;
1052 if (i
== ARRAY_SIZE (all_float_abis
))
1053 error ("invalid floating point abi: -mfloat-abi=%s",
1054 target_float_abi_name
);
1058 /* Use soft-float target flag. */
1059 if (target_flags
& ARM_FLAG_SOFT_FLOAT
)
1060 arm_float_abi
= ARM_FLOAT_ABI_SOFT
;
1062 arm_float_abi
= ARM_FLOAT_ABI_HARD
;
1065 if (arm_float_abi
== ARM_FLOAT_ABI_SOFTFP
)
1066 sorry ("-mfloat-abi=softfp");
1067 /* If soft-float is specified then don't use FPU. */
1068 if (TARGET_SOFT_FLOAT
)
1069 arm_fpu_arch
= FPUTYPE_NONE
;
1071 /* For arm2/3 there is no need to do any scheduling if there is only
1072 a floating point emulator, or we are doing software floating-point. */
1073 if ((TARGET_SOFT_FLOAT
1074 || arm_fpu_tune
== FPUTYPE_FPA_EMU2
1075 || arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
1076 && (tune_flags
& FL_MODE32
) == 0)
1077 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
1079 /* Override the default structure alignment for AAPCS ABI. */
1080 if (arm_abi
== ARM_ABI_AAPCS
)
1081 arm_structure_size_boundary
= 8;
1083 if (structure_size_string
!= NULL
)
1085 int size
= strtol (structure_size_string
, NULL
, 0);
1087 if (size
== 8 || size
== 32
1088 || (ARM_DOUBLEWORD_ALIGN
&& size
== 64))
1089 arm_structure_size_boundary
= size
;
1091 warning ("structure size boundary can only be set to %s",
1092 ARM_DOUBLEWORD_ALIGN
? "8, 32 or 64": "8 or 32");
1095 if (arm_pic_register_string
!= NULL
)
1097 int pic_register
= decode_reg_name (arm_pic_register_string
);
1100 warning ("-mpic-register= is useless without -fpic");
1102 /* Prevent the user from choosing an obviously stupid PIC register. */
1103 else if (pic_register
< 0 || call_used_regs
[pic_register
]
1104 || pic_register
== HARD_FRAME_POINTER_REGNUM
1105 || pic_register
== STACK_POINTER_REGNUM
1106 || pic_register
>= PC_REGNUM
)
1107 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
1109 arm_pic_register
= pic_register
;
1112 if (TARGET_THUMB
&& flag_schedule_insns
)
1114 /* Don't warn since it's on by default in -O2. */
1115 flag_schedule_insns
= 0;
1120 /* There's some dispute as to whether this should be 1 or 2. However,
1121 experiments seem to show that in pathological cases a setting of
1122 1 degrades less severely than a setting of 2. This could change if
1123 other parts of the compiler change their behavior. */
1124 arm_constant_limit
= 1;
1126 /* If optimizing for size, bump the number of instructions that we
1127 are prepared to conditionally execute (even on a StrongARM). */
1128 max_insns_skipped
= 6;
1132 /* For processors with load scheduling, it never costs more than
1133 2 cycles to load a constant, and the load scheduler may well
1134 reduce that to 1. */
1135 if (tune_flags
& FL_LDSCHED
)
1136 arm_constant_limit
= 1;
1138 /* On XScale the longer latency of a load makes it more difficult
1139 to achieve a good schedule, so it's faster to synthesize
1140 constants that can be done in two insns. */
1141 if (arm_tune_xscale
)
1142 arm_constant_limit
= 2;
1144 /* StrongARM has early execution of branches, so a sequence
1145 that is worth skipping is shorter. */
1147 max_insns_skipped
= 3;
1150 /* Register global variables with the garbage collector. */
1151 arm_add_gc_roots ();
1155 arm_add_gc_roots (void)
1157 gcc_obstack_init(&minipool_obstack
);
1158 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
1161 /* A table of known ARM exception types.
1162 For use with the interrupt function attribute. */
1166 const char *const arg
;
1167 const unsigned long return_value
;
1171 static const isr_attribute_arg isr_attribute_args
[] =
1173 { "IRQ", ARM_FT_ISR
},
1174 { "irq", ARM_FT_ISR
},
1175 { "FIQ", ARM_FT_FIQ
},
1176 { "fiq", ARM_FT_FIQ
},
1177 { "ABORT", ARM_FT_ISR
},
1178 { "abort", ARM_FT_ISR
},
1179 { "ABORT", ARM_FT_ISR
},
1180 { "abort", ARM_FT_ISR
},
1181 { "UNDEF", ARM_FT_EXCEPTION
},
1182 { "undef", ARM_FT_EXCEPTION
},
1183 { "SWI", ARM_FT_EXCEPTION
},
1184 { "swi", ARM_FT_EXCEPTION
},
1185 { NULL
, ARM_FT_NORMAL
}
1188 /* Returns the (interrupt) function type of the current
1189 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1191 static unsigned long
1192 arm_isr_value (tree argument
)
1194 const isr_attribute_arg
* ptr
;
1197 /* No argument - default to IRQ. */
1198 if (argument
== NULL_TREE
)
1201 /* Get the value of the argument. */
1202 if (TREE_VALUE (argument
) == NULL_TREE
1203 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
1204 return ARM_FT_UNKNOWN
;
1206 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
1208 /* Check it against the list of known arguments. */
1209 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
1210 if (streq (arg
, ptr
->arg
))
1211 return ptr
->return_value
;
1213 /* An unrecognized interrupt type. */
1214 return ARM_FT_UNKNOWN
;
1217 /* Computes the type of the current function. */
1219 static unsigned long
1220 arm_compute_func_type (void)
1222 unsigned long type
= ARM_FT_UNKNOWN
;
1226 if (TREE_CODE (current_function_decl
) != FUNCTION_DECL
)
1229 /* Decide if the current function is volatile. Such functions
1230 never return, and many memory cycles can be saved by not storing
1231 register values that will never be needed again. This optimization
1232 was added to speed up context switching in a kernel application. */
1234 && TREE_NOTHROW (current_function_decl
)
1235 && TREE_THIS_VOLATILE (current_function_decl
))
1236 type
|= ARM_FT_VOLATILE
;
1238 if (cfun
->static_chain_decl
!= NULL
)
1239 type
|= ARM_FT_NESTED
;
1241 attr
= DECL_ATTRIBUTES (current_function_decl
);
1243 a
= lookup_attribute ("naked", attr
);
1245 type
|= ARM_FT_NAKED
;
1247 a
= lookup_attribute ("isr", attr
);
1249 a
= lookup_attribute ("interrupt", attr
);
1252 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
1254 type
|= arm_isr_value (TREE_VALUE (a
));
1259 /* Returns the type of the current function. */
1262 arm_current_func_type (void)
1264 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1265 cfun
->machine
->func_type
= arm_compute_func_type ();
1267 return cfun
->machine
->func_type
;
1270 /* Return 1 if it is possible to return using a single instruction.
1271 If SIBLING is non-null, this is a test for a return before a sibling
1272 call. SIBLING is the call insn, so we can examine its register usage. */
1275 use_return_insn (int iscond
, rtx sibling
)
1278 unsigned int func_type
;
1279 unsigned long saved_int_regs
;
1280 unsigned HOST_WIDE_INT stack_adjust
;
1281 arm_stack_offsets
*offsets
;
1283 /* Never use a return instruction before reload has run. */
1284 if (!reload_completed
)
1287 func_type
= arm_current_func_type ();
1289 /* Naked functions and volatile functions need special
1291 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
1294 /* So do interrupt functions that use the frame pointer. */
1295 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1298 offsets
= arm_get_frame_offsets ();
1299 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
1301 /* As do variadic functions. */
1302 if (current_function_pretend_args_size
1303 || cfun
->machine
->uses_anonymous_args
1304 /* Or if the function calls __builtin_eh_return () */
1305 || current_function_calls_eh_return
1306 /* Or if the function calls alloca */
1307 || current_function_calls_alloca
1308 /* Or if there is a stack adjustment. However, if the stack pointer
1309 is saved on the stack, we can use a pre-incrementing stack load. */
1310 || !(stack_adjust
== 0 || (frame_pointer_needed
&& stack_adjust
== 4)))
1313 saved_int_regs
= arm_compute_save_reg_mask ();
1315 /* Unfortunately, the insn
1317 ldmib sp, {..., sp, ...}
1319 triggers a bug on most SA-110 based devices, such that the stack
1320 pointer won't be correctly restored if the instruction takes a
1321 page fault. We work around this problem by popping r3 along with
1322 the other registers, since that is never slower than executing
1323 another instruction.
1325 We test for !arm_arch5 here, because code for any architecture
1326 less than this could potentially be run on one of the buggy
1328 if (stack_adjust
== 4 && !arm_arch5
)
1330 /* Validate that r3 is a call-clobbered register (always true in
1331 the default abi) ... */
1332 if (!call_used_regs
[3])
1335 /* ... that it isn't being used for a return value (always true
1336 until we implement return-in-regs), or for a tail-call
1340 if (GET_CODE (sibling
) != CALL_INSN
)
1343 if (find_regno_fusage (sibling
, USE
, 3))
1347 /* ... and that there are no call-saved registers in r0-r2
1348 (always true in the default ABI). */
1349 if (saved_int_regs
& 0x7)
1353 /* Can't be done if interworking with Thumb, and any registers have been
1355 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1358 /* On StrongARM, conditional returns are expensive if they aren't
1359 taken and multiple registers have been stacked. */
1360 if (iscond
&& arm_is_strong
)
1362 /* Conditional return when just the LR is stored is a simple
1363 conditional-load instruction, that's not expensive. */
1364 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1367 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1371 /* If there are saved registers but the LR isn't saved, then we need
1372 two instructions for the return. */
1373 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1376 /* Can't be done if any of the FPA regs are pushed,
1377 since this also requires an insn. */
1378 if (TARGET_HARD_FLOAT
&& TARGET_FPA
)
1379 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
1380 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1383 /* Likewise VFP regs. */
1384 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
1385 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
1386 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1389 if (TARGET_REALLY_IWMMXT
)
1390 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1391 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1397 /* Return TRUE if int I is a valid immediate ARM constant. */
1400 const_ok_for_arm (HOST_WIDE_INT i
)
1402 unsigned HOST_WIDE_INT mask
= ~(unsigned HOST_WIDE_INT
)0xFF;
1404 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1405 be all zero, or all one. */
1406 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1407 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1408 != ((~(unsigned HOST_WIDE_INT
) 0)
1409 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1412 /* Fast return for 0 and powers of 2 */
1413 if ((i
& (i
- 1)) == 0)
1418 if ((i
& mask
& (unsigned HOST_WIDE_INT
) 0xffffffff) == 0)
1421 (mask
<< 2) | ((mask
& (unsigned HOST_WIDE_INT
) 0xffffffff)
1422 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT
) 0xffffffff;
1424 while (mask
!= ~(unsigned HOST_WIDE_INT
) 0xFF);
1429 /* Return true if I is a valid constant for the operation CODE. */
1431 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1433 if (const_ok_for_arm (i
))
1439 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1441 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1447 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1454 /* Emit a sequence of insns to handle a large constant.
1455 CODE is the code of the operation required, it can be any of SET, PLUS,
1456 IOR, AND, XOR, MINUS;
1457 MODE is the mode in which the operation is being performed;
1458 VAL is the integer to operate on;
1459 SOURCE is the other operand (a register, or a null-pointer for SET);
1460 SUBTARGETS means it is safe to create scratch registers if that will
1461 either produce a simpler sequence, or we will want to cse the values.
1462 Return value is the number of insns emitted. */
1465 arm_split_constant (enum rtx_code code
, enum machine_mode mode
, rtx insn
,
1466 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1470 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
1471 cond
= COND_EXEC_TEST (PATTERN (insn
));
1475 if (subtargets
|| code
== SET
1476 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1477 && REGNO (target
) != REGNO (source
)))
1479 /* After arm_reorg has been called, we can't fix up expensive
1480 constants by pushing them into memory so we must synthesize
1481 them in-line, regardless of the cost. This is only likely to
1482 be more costly on chips that have load delay slots and we are
1483 compiling without running the scheduler (so no splitting
1484 occurred before the final instruction emission).
1486 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1488 if (!after_arm_reorg
1490 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
1492 > arm_constant_limit
+ (code
!= SET
)))
1496 /* Currently SET is the only monadic value for CODE, all
1497 the rest are diadic. */
1498 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1503 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1505 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1506 /* For MINUS, the value is subtracted from, since we never
1507 have subtraction of a constant. */
1509 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1510 gen_rtx_MINUS (mode
, temp
, source
)));
1512 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1513 gen_rtx_fmt_ee (code
, mode
, source
, temp
)));
1519 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
1524 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1526 HOST_WIDE_INT temp1
;
1534 if (remainder
& (3 << (i
- 2)))
1539 temp1
= remainder
& ((0x0ff << end
)
1540 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1541 remainder
&= ~temp1
;
1546 } while (remainder
);
1550 /* Emit an instruction with the indicated PATTERN. If COND is
1551 non-NULL, conditionalize the execution of the instruction on COND
1555 emit_constant_insn (rtx cond
, rtx pattern
)
1558 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
1559 emit_insn (pattern
);
1562 /* As above, but extra parameter GENERATE which, if clear, suppresses
1566 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
, rtx cond
,
1567 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1572 int can_negate_initial
= 0;
1575 int num_bits_set
= 0;
1576 int set_sign_bit_copies
= 0;
1577 int clear_sign_bit_copies
= 0;
1578 int clear_zero_bit_copies
= 0;
1579 int set_zero_bit_copies
= 0;
1581 unsigned HOST_WIDE_INT temp1
, temp2
;
1582 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1584 /* Find out which operations are safe for a given CODE. Also do a quick
1585 check for degenerate cases; these can occur when DImode operations
1597 can_negate_initial
= 1;
1601 if (remainder
== 0xffffffff)
1604 emit_constant_insn (cond
,
1605 gen_rtx_SET (VOIDmode
, target
,
1606 GEN_INT (ARM_SIGN_EXTEND (val
))));
1611 if (reload_completed
&& rtx_equal_p (target
, source
))
1614 emit_constant_insn (cond
,
1615 gen_rtx_SET (VOIDmode
, target
, source
));
1624 emit_constant_insn (cond
,
1625 gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1628 if (remainder
== 0xffffffff)
1630 if (reload_completed
&& rtx_equal_p (target
, source
))
1633 emit_constant_insn (cond
,
1634 gen_rtx_SET (VOIDmode
, target
, source
));
1643 if (reload_completed
&& rtx_equal_p (target
, source
))
1646 emit_constant_insn (cond
,
1647 gen_rtx_SET (VOIDmode
, target
, source
));
1650 if (remainder
== 0xffffffff)
1653 emit_constant_insn (cond
,
1654 gen_rtx_SET (VOIDmode
, target
,
1655 gen_rtx_NOT (mode
, source
)));
1659 /* We don't know how to handle this yet below. */
1663 /* We treat MINUS as (val - source), since (source - val) is always
1664 passed as (source + (-val)). */
1668 emit_constant_insn (cond
,
1669 gen_rtx_SET (VOIDmode
, target
,
1670 gen_rtx_NEG (mode
, source
)));
1673 if (const_ok_for_arm (val
))
1676 emit_constant_insn (cond
,
1677 gen_rtx_SET (VOIDmode
, target
,
1678 gen_rtx_MINUS (mode
, GEN_INT (val
),
1690 /* If we can do it in one insn get out quickly. */
1691 if (const_ok_for_arm (val
)
1692 || (can_negate_initial
&& const_ok_for_arm (-val
))
1693 || (can_invert
&& const_ok_for_arm (~val
)))
1696 emit_constant_insn (cond
,
1697 gen_rtx_SET (VOIDmode
, target
,
1699 ? gen_rtx_fmt_ee (code
, mode
, source
,
1705 /* Calculate a few attributes that may be useful for specific
1707 for (i
= 31; i
>= 0; i
--)
1709 if ((remainder
& (1 << i
)) == 0)
1710 clear_sign_bit_copies
++;
1715 for (i
= 31; i
>= 0; i
--)
1717 if ((remainder
& (1 << i
)) != 0)
1718 set_sign_bit_copies
++;
1723 for (i
= 0; i
<= 31; i
++)
1725 if ((remainder
& (1 << i
)) == 0)
1726 clear_zero_bit_copies
++;
1731 for (i
= 0; i
<= 31; i
++)
1733 if ((remainder
& (1 << i
)) != 0)
1734 set_zero_bit_copies
++;
1742 /* See if we can do this by sign_extending a constant that is known
1743 to be negative. This is a good, way of doing it, since the shift
1744 may well merge into a subsequent insn. */
1745 if (set_sign_bit_copies
> 1)
1747 if (const_ok_for_arm
1748 (temp1
= ARM_SIGN_EXTEND (remainder
1749 << (set_sign_bit_copies
- 1))))
1753 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1754 emit_constant_insn (cond
,
1755 gen_rtx_SET (VOIDmode
, new_src
,
1757 emit_constant_insn (cond
,
1758 gen_ashrsi3 (target
, new_src
,
1759 GEN_INT (set_sign_bit_copies
- 1)));
1763 /* For an inverted constant, we will need to set the low bits,
1764 these will be shifted out of harm's way. */
1765 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1766 if (const_ok_for_arm (~temp1
))
1770 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1771 emit_constant_insn (cond
,
1772 gen_rtx_SET (VOIDmode
, new_src
,
1774 emit_constant_insn (cond
,
1775 gen_ashrsi3 (target
, new_src
,
1776 GEN_INT (set_sign_bit_copies
- 1)));
1782 /* See if we can generate this by setting the bottom (or the top)
1783 16 bits, and then shifting these into the other half of the
1784 word. We only look for the simplest cases, to do more would cost
1785 too much. Be careful, however, not to generate this when the
1786 alternative would take fewer insns. */
1787 if (val
& 0xffff0000)
1789 temp1
= remainder
& 0xffff0000;
1790 temp2
= remainder
& 0x0000ffff;
1792 /* Overlaps outside this range are best done using other methods. */
1793 for (i
= 9; i
< 24; i
++)
1795 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
1796 && !const_ok_for_arm (temp2
))
1798 rtx new_src
= (subtargets
1799 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1801 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
1802 source
, subtargets
, generate
);
1810 gen_rtx_ASHIFT (mode
, source
,
1817 /* Don't duplicate cases already considered. */
1818 for (i
= 17; i
< 24; i
++)
1820 if (((temp1
| (temp1
>> i
)) == remainder
)
1821 && !const_ok_for_arm (temp1
))
1823 rtx new_src
= (subtargets
1824 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1826 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
1827 source
, subtargets
, generate
);
1832 gen_rtx_SET (VOIDmode
, target
,
1835 gen_rtx_LSHIFTRT (mode
, source
,
1846 /* If we have IOR or XOR, and the constant can be loaded in a
1847 single instruction, and we can find a temporary to put it in,
1848 then this can be done in two instructions instead of 3-4. */
1850 /* TARGET can't be NULL if SUBTARGETS is 0 */
1851 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
1853 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
1857 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1859 emit_constant_insn (cond
,
1860 gen_rtx_SET (VOIDmode
, sub
,
1862 emit_constant_insn (cond
,
1863 gen_rtx_SET (VOIDmode
, target
,
1864 gen_rtx_fmt_ee (code
, mode
,
1874 if (set_sign_bit_copies
> 8
1875 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
1879 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1880 rtx shift
= GEN_INT (set_sign_bit_copies
);
1884 gen_rtx_SET (VOIDmode
, sub
,
1886 gen_rtx_ASHIFT (mode
,
1891 gen_rtx_SET (VOIDmode
, target
,
1893 gen_rtx_LSHIFTRT (mode
, sub
,
1899 if (set_zero_bit_copies
> 8
1900 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
1904 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1905 rtx shift
= GEN_INT (set_zero_bit_copies
);
1909 gen_rtx_SET (VOIDmode
, sub
,
1911 gen_rtx_LSHIFTRT (mode
,
1916 gen_rtx_SET (VOIDmode
, target
,
1918 gen_rtx_ASHIFT (mode
, sub
,
1924 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
1928 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1929 emit_constant_insn (cond
,
1930 gen_rtx_SET (VOIDmode
, sub
,
1931 gen_rtx_NOT (mode
, source
)));
1934 sub
= gen_reg_rtx (mode
);
1935 emit_constant_insn (cond
,
1936 gen_rtx_SET (VOIDmode
, sub
,
1937 gen_rtx_AND (mode
, source
,
1939 emit_constant_insn (cond
,
1940 gen_rtx_SET (VOIDmode
, target
,
1941 gen_rtx_NOT (mode
, sub
)));
1948 /* See if two shifts will do 2 or more insn's worth of work. */
1949 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
1951 HOST_WIDE_INT shift_mask
= ((0xffffffff
1952 << (32 - clear_sign_bit_copies
))
1955 if ((remainder
| shift_mask
) != 0xffffffff)
1959 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1960 insns
= arm_gen_constant (AND
, mode
, cond
,
1961 remainder
| shift_mask
,
1962 new_src
, source
, subtargets
, 1);
1967 rtx targ
= subtargets
? NULL_RTX
: target
;
1968 insns
= arm_gen_constant (AND
, mode
, cond
,
1969 remainder
| shift_mask
,
1970 targ
, source
, subtargets
, 0);
1976 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1977 rtx shift
= GEN_INT (clear_sign_bit_copies
);
1979 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
1980 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
1986 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
1988 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
1990 if ((remainder
| shift_mask
) != 0xffffffff)
1994 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1996 insns
= arm_gen_constant (AND
, mode
, cond
,
1997 remainder
| shift_mask
,
1998 new_src
, source
, subtargets
, 1);
2003 rtx targ
= subtargets
? NULL_RTX
: target
;
2005 insns
= arm_gen_constant (AND
, mode
, cond
,
2006 remainder
| shift_mask
,
2007 targ
, source
, subtargets
, 0);
2013 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
2014 rtx shift
= GEN_INT (clear_zero_bit_copies
);
2016 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
2017 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
2029 for (i
= 0; i
< 32; i
++)
2030 if (remainder
& (1 << i
))
2033 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
2034 remainder
= (~remainder
) & 0xffffffff;
2035 else if (code
== PLUS
&& num_bits_set
> 16)
2036 remainder
= (-remainder
) & 0xffffffff;
2043 /* Now try and find a way of doing the job in either two or three
2045 We start by looking for the largest block of zeros that are aligned on
2046 a 2-bit boundary, we then fill up the temps, wrapping around to the
2047 top of the word when we drop off the bottom.
2048 In the worst case this code should produce no more than four insns. */
2051 int best_consecutive_zeros
= 0;
2053 for (i
= 0; i
< 32; i
+= 2)
2055 int consecutive_zeros
= 0;
2057 if (!(remainder
& (3 << i
)))
2059 while ((i
< 32) && !(remainder
& (3 << i
)))
2061 consecutive_zeros
+= 2;
2064 if (consecutive_zeros
> best_consecutive_zeros
)
2066 best_consecutive_zeros
= consecutive_zeros
;
2067 best_start
= i
- consecutive_zeros
;
2073 /* So long as it won't require any more insns to do so, it's
2074 desirable to emit a small constant (in bits 0...9) in the last
2075 insn. This way there is more chance that it can be combined with
2076 a later addressing insn to form a pre-indexed load or store
2077 operation. Consider:
2079 *((volatile int *)0xe0000100) = 1;
2080 *((volatile int *)0xe0000110) = 2;
2082 We want this to wind up as:
2086 str rB, [rA, #0x100]
2088 str rB, [rA, #0x110]
2090 rather than having to synthesize both large constants from scratch.
2092 Therefore, we calculate how many insns would be required to emit
2093 the constant starting from `best_start', and also starting from
2094 zero (ie with bit 31 first to be output). If `best_start' doesn't
2095 yield a shorter sequence, we may as well use zero. */
2097 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
2098 && (count_insns_for_constant (remainder
, 0) <=
2099 count_insns_for_constant (remainder
, best_start
)))
2102 /* Now start emitting the insns. */
2110 if (remainder
& (3 << (i
- 2)))
2115 temp1
= remainder
& ((0x0ff << end
)
2116 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
2117 remainder
&= ~temp1
;
2121 rtx new_src
, temp1_rtx
;
2123 if (code
== SET
|| code
== MINUS
)
2125 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
2126 if (can_invert
&& code
!= MINUS
)
2131 if (remainder
&& subtargets
)
2132 new_src
= gen_reg_rtx (mode
);
2137 else if (can_negate
)
2141 temp1
= trunc_int_for_mode (temp1
, mode
);
2142 temp1_rtx
= GEN_INT (temp1
);
2146 else if (code
== MINUS
)
2147 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
2149 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
2151 emit_constant_insn (cond
,
2152 gen_rtx_SET (VOIDmode
, new_src
,
2162 else if (code
== MINUS
)
2176 /* Canonicalize a comparison so that we are more likely to recognize it.
2177 This can be done for a few constant compares, where we can make the
2178 immediate value easier to load. */
2181 arm_canonicalize_comparison (enum rtx_code code
, rtx
* op1
)
2183 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
2193 if (i
!= ((((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1)) - 1)
2194 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2196 *op1
= GEN_INT (i
+ 1);
2197 return code
== GT
? GE
: LT
;
2203 if (i
!= (((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1))
2204 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2206 *op1
= GEN_INT (i
- 1);
2207 return code
== GE
? GT
: LE
;
2213 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
2214 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
2216 *op1
= GEN_INT (i
+ 1);
2217 return code
== GTU
? GEU
: LTU
;
2224 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
2226 *op1
= GEN_INT (i
- 1);
2227 return code
== GEU
? GTU
: LEU
;
2239 /* Define how to find the value returned by a function. */
2241 rtx
arm_function_value(tree type
, tree func ATTRIBUTE_UNUSED
)
2243 enum machine_mode mode
;
2244 int unsignedp ATTRIBUTE_UNUSED
;
2245 rtx r ATTRIBUTE_UNUSED
;
2248 mode
= TYPE_MODE (type
);
2249 /* Promote integer types. */
2250 if (INTEGRAL_TYPE_P (type
))
2251 PROMOTE_FUNCTION_MODE (mode
, unsignedp
, type
);
2252 return LIBCALL_VALUE(mode
);
2256 /* Decide whether a type should be returned in memory (true)
2257 or in a register (false). This is called by the macro
2258 RETURN_IN_MEMORY. */
2260 arm_return_in_memory (tree type
)
2264 if (!AGGREGATE_TYPE_P (type
))
2265 /* All simple types are returned in registers. */
2268 size
= int_size_in_bytes (type
);
2270 if (arm_abi
!= ARM_ABI_APCS
)
2272 /* ATPCS and later return aggregate types in memory only if they are
2273 larger than a word (or are variable size). */
2274 return (size
< 0 || size
> UNITS_PER_WORD
);
2277 /* For the arm-wince targets we choose to be compatible with Microsoft's
2278 ARM and Thumb compilers, which always return aggregates in memory. */
2280 /* All structures/unions bigger than one word are returned in memory.
2281 Also catch the case where int_size_in_bytes returns -1. In this case
2282 the aggregate is either huge or of variable size, and in either case
2283 we will want to return it via memory and not in a register. */
2284 if (size
< 0 || size
> UNITS_PER_WORD
)
2287 if (TREE_CODE (type
) == RECORD_TYPE
)
2291 /* For a struct the APCS says that we only return in a register
2292 if the type is 'integer like' and every addressable element
2293 has an offset of zero. For practical purposes this means
2294 that the structure can have at most one non bit-field element
2295 and that this element must be the first one in the structure. */
2297 /* Find the first field, ignoring non FIELD_DECL things which will
2298 have been created by C++. */
2299 for (field
= TYPE_FIELDS (type
);
2300 field
&& TREE_CODE (field
) != FIELD_DECL
;
2301 field
= TREE_CHAIN (field
))
2305 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2307 /* Check that the first field is valid for returning in a register. */
2309 /* ... Floats are not allowed */
2310 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2313 /* ... Aggregates that are not themselves valid for returning in
2314 a register are not allowed. */
2315 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2318 /* Now check the remaining fields, if any. Only bitfields are allowed,
2319 since they are not addressable. */
2320 for (field
= TREE_CHAIN (field
);
2322 field
= TREE_CHAIN (field
))
2324 if (TREE_CODE (field
) != FIELD_DECL
)
2327 if (!DECL_BIT_FIELD_TYPE (field
))
2334 if (TREE_CODE (type
) == UNION_TYPE
)
2338 /* Unions can be returned in registers if every element is
2339 integral, or can be returned in an integer register. */
2340 for (field
= TYPE_FIELDS (type
);
2342 field
= TREE_CHAIN (field
))
2344 if (TREE_CODE (field
) != FIELD_DECL
)
2347 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
2350 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2356 #endif /* not ARM_WINCE */
2358 /* Return all other types in memory. */
2362 /* Indicate whether or not words of a double are in big-endian order. */
2365 arm_float_words_big_endian (void)
2367 if (TARGET_MAVERICK
)
2370 /* For FPA, float words are always big-endian. For VFP, floats words
2371 follow the memory system mode. */
2379 return (TARGET_BIG_END
? 1 : 0);
2384 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2385 for a call to a function whose data type is FNTYPE.
2386 For a library call, FNTYPE is NULL. */
2388 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
2389 rtx libname ATTRIBUTE_UNUSED
,
2390 tree fndecl ATTRIBUTE_UNUSED
)
2392 /* On the ARM, the offset starts at 0. */
2393 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fntype
)) ? 1 : 0);
2394 pcum
->iwmmxt_nregs
= 0;
2395 pcum
->can_split
= true;
2397 pcum
->call_cookie
= CALL_NORMAL
;
2399 if (TARGET_LONG_CALLS
)
2400 pcum
->call_cookie
= CALL_LONG
;
2402 /* Check for long call/short call attributes. The attributes
2403 override any command line option. */
2406 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
2407 pcum
->call_cookie
= CALL_SHORT
;
2408 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
2409 pcum
->call_cookie
= CALL_LONG
;
2412 /* Varargs vectors are treated the same as long long.
2413 named_count avoids having to change the way arm handles 'named' */
2414 pcum
->named_count
= 0;
2417 if (TARGET_REALLY_IWMMXT
&& fntype
)
2421 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2423 fn_arg
= TREE_CHAIN (fn_arg
))
2424 pcum
->named_count
+= 1;
2426 if (! pcum
->named_count
)
2427 pcum
->named_count
= INT_MAX
;
2432 /* Return true if mode/type need doubleword alignment. */
2434 arm_needs_doubleword_align (enum machine_mode mode
, tree type
)
2436 return (GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
2437 || (type
&& TYPE_ALIGN (type
) > PARM_BOUNDARY
));
2441 /* Determine where to put an argument to a function.
2442 Value is zero to push the argument on the stack,
2443 or a hard register in which to store the argument.
2445 MODE is the argument's machine mode.
2446 TYPE is the data type of the argument (as a tree).
2447 This is null for libcalls where that information may
2449 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2450 the preceding args and about the function being called.
2451 NAMED is nonzero if this argument is a named parameter
2452 (otherwise it is an extra parameter matching an ellipsis). */
2455 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2456 tree type
, int named
)
2460 /* Varargs vectors are treated the same as long long.
2461 named_count avoids having to change the way arm handles 'named' */
2462 if (TARGET_IWMMXT_ABI
2463 && VECTOR_MODE_SUPPORTED_P (mode
)
2464 && pcum
->named_count
> pcum
->nargs
+ 1)
2466 if (pcum
->iwmmxt_nregs
<= 9)
2467 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2470 pcum
->can_split
= false;
2475 /* Put doubleword aligned quantities in even register pairs. */
2477 && ARM_DOUBLEWORD_ALIGN
2478 && arm_needs_doubleword_align (mode
, type
))
2481 if (mode
== VOIDmode
)
2482 /* Compute operand 2 of the call insn. */
2483 return GEN_INT (pcum
->call_cookie
);
2485 /* Only allow splitting an arg between regs and memory if all preceding
2486 args were allocated to regs. For args passed by reference we only count
2487 the reference pointer. */
2488 if (pcum
->can_split
)
2491 nregs
= ARM_NUM_REGS2 (mode
, type
);
2493 if (!named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
2496 return gen_rtx_REG (mode
, pcum
->nregs
);
2499 /* Variable sized types are passed by reference. This is a GCC
2500 extension to the ARM ABI. */
2503 arm_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2504 enum machine_mode mode ATTRIBUTE_UNUSED
,
2505 tree type
, bool named ATTRIBUTE_UNUSED
)
2507 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2510 /* Encode the current state of the #pragma [no_]long_calls. */
2513 OFF
, /* No #pramgma [no_]long_calls is in effect. */
2514 LONG
, /* #pragma long_calls is in effect. */
2515 SHORT
/* #pragma no_long_calls is in effect. */
2518 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2521 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2523 arm_pragma_long_calls
= LONG
;
2527 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2529 arm_pragma_long_calls
= SHORT
;
2533 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2535 arm_pragma_long_calls
= OFF
;
2538 /* Table of machine attributes. */
2539 const struct attribute_spec arm_attribute_table
[] =
2541 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2542 /* Function calls made to this symbol must be done indirectly, because
2543 it may lie outside of the 26 bit addressing range of a normal function
2545 { "long_call", 0, 0, false, true, true, NULL
},
2546 /* Whereas these functions are always known to reside within the 26 bit
2547 addressing range. */
2548 { "short_call", 0, 0, false, true, true, NULL
},
2549 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2550 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2551 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2552 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2554 /* ARM/PE has three new attributes:
2556 dllexport - for exporting a function/variable that will live in a dll
2557 dllimport - for importing a function/variable from a dll
2559 Microsoft allows multiple declspecs in one __declspec, separating
2560 them with spaces. We do NOT support this. Instead, use __declspec
2563 { "dllimport", 0, 0, true, false, false, NULL
},
2564 { "dllexport", 0, 0, true, false, false, NULL
},
2565 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2566 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2567 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
},
2568 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
},
2570 { NULL
, 0, 0, false, false, false, NULL
}
2573 /* Handle an attribute requiring a FUNCTION_DECL;
2574 arguments as in struct attribute_spec.handler. */
2576 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2577 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2579 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2581 warning ("`%s' attribute only applies to functions",
2582 IDENTIFIER_POINTER (name
));
2583 *no_add_attrs
= true;
2589 /* Handle an "interrupt" or "isr" attribute;
2590 arguments as in struct attribute_spec.handler. */
2592 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
2597 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2599 warning ("`%s' attribute only applies to functions",
2600 IDENTIFIER_POINTER (name
));
2601 *no_add_attrs
= true;
2603 /* FIXME: the argument if any is checked for type attributes;
2604 should it be checked for decl ones? */
2608 if (TREE_CODE (*node
) == FUNCTION_TYPE
2609 || TREE_CODE (*node
) == METHOD_TYPE
)
2611 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2613 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2614 *no_add_attrs
= true;
2617 else if (TREE_CODE (*node
) == POINTER_TYPE
2618 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2619 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2620 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2622 *node
= build_type_copy (*node
);
2623 TREE_TYPE (*node
) = build_type_attribute_variant
2625 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2626 *no_add_attrs
= true;
2630 /* Possibly pass this attribute on from the type to a decl. */
2631 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2632 | (int) ATTR_FLAG_FUNCTION_NEXT
2633 | (int) ATTR_FLAG_ARRAY_NEXT
))
2635 *no_add_attrs
= true;
2636 return tree_cons (name
, args
, NULL_TREE
);
2640 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2648 /* Return 0 if the attributes for two types are incompatible, 1 if they
2649 are compatible, and 2 if they are nearly compatible (which causes a
2650 warning to be generated). */
2652 arm_comp_type_attributes (tree type1
, tree type2
)
2656 /* Check for mismatch of non-default calling convention. */
2657 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2660 /* Check for mismatched call attributes. */
2661 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2662 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2663 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2664 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2666 /* Only bother to check if an attribute is defined. */
2667 if (l1
| l2
| s1
| s2
)
2669 /* If one type has an attribute, the other must have the same attribute. */
2670 if ((l1
!= l2
) || (s1
!= s2
))
2673 /* Disallow mixed attributes. */
2674 if ((l1
& s2
) || (l2
& s1
))
2678 /* Check for mismatched ISR attribute. */
2679 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2681 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2682 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2684 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2691 /* Encode long_call or short_call attribute by prefixing
2692 symbol name in DECL with a special character FLAG. */
2694 arm_encode_call_attribute (tree decl
, int flag
)
2696 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2697 int len
= strlen (str
);
2700 /* Do not allow weak functions to be treated as short call. */
2701 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
2704 newstr
= alloca (len
+ 2);
2706 strcpy (newstr
+ 1, str
);
2708 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
2709 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2712 /* Assigns default attributes to newly defined type. This is used to
2713 set short_call/long_call attributes for function types of
2714 functions defined inside corresponding #pragma scopes. */
2716 arm_set_default_type_attributes (tree type
)
2718 /* Add __attribute__ ((long_call)) to all functions, when
2719 inside #pragma long_calls or __attribute__ ((short_call)),
2720 when inside #pragma no_long_calls. */
2721 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
2723 tree type_attr_list
, attr_name
;
2724 type_attr_list
= TYPE_ATTRIBUTES (type
);
2726 if (arm_pragma_long_calls
== LONG
)
2727 attr_name
= get_identifier ("long_call");
2728 else if (arm_pragma_long_calls
== SHORT
)
2729 attr_name
= get_identifier ("short_call");
2733 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
2734 TYPE_ATTRIBUTES (type
) = type_attr_list
;
2738 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2739 defined within the current compilation unit. If this cannot be
2740 determined, then 0 is returned. */
2742 current_file_function_operand (rtx sym_ref
)
2744 /* This is a bit of a fib. A function will have a short call flag
2745 applied to its name if it has the short call attribute, or it has
2746 already been defined within the current compilation unit. */
2747 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
2750 /* The current function is always defined within the current compilation
2751 unit. if it s a weak definition however, then this may not be the real
2752 definition of the function, and so we have to say no. */
2753 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
2754 && !DECL_WEAK (current_function_decl
))
2757 /* We cannot make the determination - default to returning 0. */
2761 /* Return nonzero if a 32 bit "long_call" should be generated for
2762 this call. We generate a long_call if the function:
2764 a. has an __attribute__((long call))
2765 or b. is within the scope of a #pragma long_calls
2766 or c. the -mlong-calls command line switch has been specified
2768 However we do not generate a long call if the function:
2770 d. has an __attribute__ ((short_call))
2771 or e. is inside the scope of a #pragma no_long_calls
2772 or f. has an __attribute__ ((section))
2773 or g. is defined within the current compilation unit.
2775 This function will be called by C fragments contained in the machine
2776 description file. CALL_REF and CALL_COOKIE correspond to the matched
2777 rtl operands. CALL_SYMBOL is used to distinguish between
2778 two different callers of the function. It is set to 1 in the
2779 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2780 and "call_value" patterns. This is because of the difference in the
2781 SYM_REFs passed by these patterns. */
2783 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
2787 if (GET_CODE (sym_ref
) != MEM
)
2790 sym_ref
= XEXP (sym_ref
, 0);
2793 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
2796 if (call_cookie
& CALL_SHORT
)
2799 if (TARGET_LONG_CALLS
&& flag_function_sections
)
2802 if (current_file_function_operand (sym_ref
))
2805 return (call_cookie
& CALL_LONG
)
2806 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
2807 || TARGET_LONG_CALLS
;
2810 /* Return nonzero if it is ok to make a tail-call to DECL. */
2812 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
2814 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
2816 if (cfun
->machine
->sibcall_blocked
)
2819 /* Never tailcall something for which we have no decl, or if we
2820 are in Thumb mode. */
2821 if (decl
== NULL
|| TARGET_THUMB
)
2824 /* Get the calling method. */
2825 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2826 call_type
= CALL_SHORT
;
2827 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2828 call_type
= CALL_LONG
;
2830 /* Cannot tail-call to long calls, since these are out of range of
2831 a branch instruction. However, if not compiling PIC, we know
2832 we can reach the symbol if it is in this compilation unit. */
2833 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
2836 /* If we are interworking and the function is not declared static
2837 then we can't tail-call it unless we know that it exists in this
2838 compilation unit (since it might be a Thumb routine). */
2839 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
2842 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2843 if (IS_INTERRUPT (arm_current_func_type ()))
2846 /* Everything else is ok. */
2851 /* Addressing mode support functions. */
2853 /* Return nonzero if X is a legitimate immediate operand when compiling
2856 legitimate_pic_operand_p (rtx x
)
2860 && (GET_CODE (x
) == SYMBOL_REF
2861 || (GET_CODE (x
) == CONST
2862 && GET_CODE (XEXP (x
, 0)) == PLUS
2863 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
2870 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
2872 if (GET_CODE (orig
) == SYMBOL_REF
2873 || GET_CODE (orig
) == LABEL_REF
)
2875 #ifndef AOF_ASSEMBLER
2876 rtx pic_ref
, address
;
2886 reg
= gen_reg_rtx (Pmode
);
2891 #ifdef AOF_ASSEMBLER
2892 /* The AOF assembler can generate relocations for these directly, and
2893 understands that the PIC register has to be added into the offset. */
2894 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
2897 address
= gen_reg_rtx (Pmode
);
2902 emit_insn (gen_pic_load_addr_arm (address
, orig
));
2904 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
2906 if ((GET_CODE (orig
) == LABEL_REF
2907 || (GET_CODE (orig
) == SYMBOL_REF
&&
2908 SYMBOL_REF_LOCAL_P (orig
)))
2910 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
2913 pic_ref
= gen_rtx_MEM (Pmode
,
2914 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
2916 RTX_UNCHANGING_P (pic_ref
) = 1;
2919 insn
= emit_move_insn (reg
, pic_ref
);
2921 current_function_uses_pic_offset_table
= 1;
2922 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2924 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
2928 else if (GET_CODE (orig
) == CONST
)
2932 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2933 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2941 reg
= gen_reg_rtx (Pmode
);
2944 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2946 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2947 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2948 base
== reg
? 0 : reg
);
2953 if (GET_CODE (offset
) == CONST_INT
)
2955 /* The base register doesn't really matter, we only want to
2956 test the index for the appropriate mode. */
2957 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
2959 if (!no_new_pseudos
)
2960 offset
= force_reg (Pmode
, offset
);
2965 if (GET_CODE (offset
) == CONST_INT
)
2966 return plus_constant (base
, INTVAL (offset
));
2969 if (GET_MODE_SIZE (mode
) > 4
2970 && (GET_MODE_CLASS (mode
) == MODE_INT
2971 || TARGET_SOFT_FLOAT
))
2973 emit_insn (gen_addsi3 (reg
, base
, offset
));
2977 return gen_rtx_PLUS (Pmode
, base
, offset
);
2983 /* Generate code to load the PIC register. PROLOGUE is true if
2984 called from arm_expand_prologue (in which case we want the
2985 generated insns at the start of the function); false if called
2986 by an exception receiver that needs the PIC register reloaded
2987 (in which case the insns are just dumped at the current location). */
2989 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED
)
2991 #ifndef AOF_ASSEMBLER
2992 rtx l1
, pic_tmp
, pic_tmp2
, seq
, pic_rtx
;
2993 rtx global_offset_table
;
2995 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
3002 l1
= gen_label_rtx ();
3004 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3005 /* On the ARM the PC register contains 'dot + 8' at the time of the
3006 addition, on the Thumb it is 'dot + 4'. */
3007 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), TARGET_ARM
? 8 : 4);
3009 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
3010 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
3012 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
3014 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
3018 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
3019 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
3023 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
3024 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
, l1
));
3030 emit_insn_after (seq
, get_insns ());
3034 /* Need to emit this whether or not we obey regdecls,
3035 since setjmp/longjmp can cause life info to screw up. */
3036 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
3037 #endif /* AOF_ASSEMBLER */
3040 /* Return nonzero if X is valid as an ARM state addressing register. */
3042 arm_address_register_rtx_p (rtx x
, int strict_p
)
3046 if (GET_CODE (x
) != REG
)
3052 return ARM_REGNO_OK_FOR_BASE_P (regno
);
3054 return (regno
<= LAST_ARM_REGNUM
3055 || regno
>= FIRST_PSEUDO_REGISTER
3056 || regno
== FRAME_POINTER_REGNUM
3057 || regno
== ARG_POINTER_REGNUM
);
3060 /* Return nonzero if X is a valid ARM state address operand. */
3062 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, RTX_CODE outer
,
3066 enum rtx_code code
= GET_CODE (x
);
3068 if (arm_address_register_rtx_p (x
, strict_p
))
3071 use_ldrd
= (TARGET_LDRD
3073 || (mode
== DFmode
&& (TARGET_SOFT_FLOAT
|| TARGET_VFP
))));
3075 if (code
== POST_INC
|| code
== PRE_DEC
3076 || ((code
== PRE_INC
|| code
== POST_DEC
)
3077 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
3078 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
3080 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3081 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
3082 && GET_CODE (XEXP (x
, 1)) == PLUS
3083 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
3085 rtx addend
= XEXP (XEXP (x
, 1), 1);
3087 /* Don't allow ldrd post increment by register becuase it's hard
3088 to fixup invalid register choices. */
3090 && GET_CODE (x
) == POST_MODIFY
3091 && GET_CODE (addend
) == REG
)
3094 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
3095 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
3098 /* After reload constants split into minipools will have addresses
3099 from a LABEL_REF. */
3100 else if (reload_completed
3101 && (code
== LABEL_REF
3103 && GET_CODE (XEXP (x
, 0)) == PLUS
3104 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3105 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3108 else if (mode
== TImode
)
3111 else if (code
== PLUS
)
3113 rtx xop0
= XEXP (x
, 0);
3114 rtx xop1
= XEXP (x
, 1);
3116 return ((arm_address_register_rtx_p (xop0
, strict_p
)
3117 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
3118 || (arm_address_register_rtx_p (xop1
, strict_p
)
3119 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
3123 /* Reload currently can't handle MINUS, so disable this for now */
3124 else if (GET_CODE (x
) == MINUS
)
3126 rtx xop0
= XEXP (x
, 0);
3127 rtx xop1
= XEXP (x
, 1);
3129 return (arm_address_register_rtx_p (xop0
, strict_p
)
3130 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
3134 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3135 && code
== SYMBOL_REF
3136 && CONSTANT_POOL_ADDRESS_P (x
)
3138 && symbol_mentioned_p (get_pool_constant (x
))))
3144 /* Return nonzero if INDEX is valid for an address index operand in
3147 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, RTX_CODE outer
,
3150 HOST_WIDE_INT range
;
3151 enum rtx_code code
= GET_CODE (index
);
3153 /* Standard coprocessor addressing modes. */
3154 if (TARGET_HARD_FLOAT
3155 && (TARGET_FPA
|| TARGET_MAVERICK
)
3156 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
3157 || (TARGET_MAVERICK
&& mode
== DImode
)))
3158 return (code
== CONST_INT
&& INTVAL (index
) < 1024
3159 && INTVAL (index
) > -1024
3160 && (INTVAL (index
) & 3) == 0);
3162 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
3163 return (code
== CONST_INT
3164 && INTVAL (index
) < 1024
3165 && INTVAL (index
) > -1024
3166 && (INTVAL (index
) & 3) == 0);
3168 if (arm_address_register_rtx_p (index
, strict_p
)
3169 && (GET_MODE_SIZE (mode
) <= 4))
3172 if (mode
== DImode
|| mode
== DFmode
)
3174 if (code
== CONST_INT
)
3176 HOST_WIDE_INT val
= INTVAL (index
);
3179 return val
> -256 && val
< 256;
3181 return val
> -4096 && val
< 4092;
3184 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
3187 if (GET_MODE_SIZE (mode
) <= 4
3190 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
3194 rtx xiop0
= XEXP (index
, 0);
3195 rtx xiop1
= XEXP (index
, 1);
3197 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
3198 && power_of_two_operand (xiop1
, SImode
))
3199 || (arm_address_register_rtx_p (xiop1
, strict_p
)
3200 && power_of_two_operand (xiop0
, SImode
)));
3202 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
3203 || code
== ASHIFT
|| code
== ROTATERT
)
3205 rtx op
= XEXP (index
, 1);
3207 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
3208 && GET_CODE (op
) == CONST_INT
3210 && INTVAL (op
) <= 31);
3214 /* For ARM v4 we may be doing a sign-extend operation during the
3218 if (mode
== HImode
|| (outer
== SIGN_EXTEND
&& mode
== QImode
))
3224 range
= (mode
== HImode
) ? 4095 : 4096;
3226 return (code
== CONST_INT
3227 && INTVAL (index
) < range
3228 && INTVAL (index
) > -range
);
3231 /* Return nonzero if X is valid as a Thumb state base register. */
3233 thumb_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
3237 if (GET_CODE (x
) != REG
)
3243 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
3245 return (regno
<= LAST_LO_REGNUM
3246 || regno
> LAST_VIRTUAL_REGISTER
3247 || regno
== FRAME_POINTER_REGNUM
3248 || (GET_MODE_SIZE (mode
) >= 4
3249 && (regno
== STACK_POINTER_REGNUM
3250 || regno
>= FIRST_PSEUDO_REGISTER
3251 || x
== hard_frame_pointer_rtx
3252 || x
== arg_pointer_rtx
)));
3255 /* Return nonzero if x is a legitimate index register. This is the case
3256 for any base register that can access a QImode object. */
3258 thumb_index_register_rtx_p (rtx x
, int strict_p
)
3260 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
3263 /* Return nonzero if x is a legitimate Thumb-state address.
3265 The AP may be eliminated to either the SP or the FP, so we use the
3266 least common denominator, e.g. SImode, and offsets from 0 to 64.
3268 ??? Verify whether the above is the right approach.
3270 ??? Also, the FP may be eliminated to the SP, so perhaps that
3271 needs special handling also.
3273 ??? Look at how the mips16 port solves this problem. It probably uses
3274 better ways to solve some of these problems.
3276 Although it is not incorrect, we don't accept QImode and HImode
3277 addresses based on the frame pointer or arg pointer until the
3278 reload pass starts. This is so that eliminating such addresses
3279 into stack based ones won't produce impossible code. */
3281 thumb_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
3283 /* ??? Not clear if this is right. Experiment. */
3284 if (GET_MODE_SIZE (mode
) < 4
3285 && !(reload_in_progress
|| reload_completed
)
3286 && (reg_mentioned_p (frame_pointer_rtx
, x
)
3287 || reg_mentioned_p (arg_pointer_rtx
, x
)
3288 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
3289 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
3290 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
3291 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
3294 /* Accept any base register. SP only in SImode or larger. */
3295 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
3298 /* This is PC relative data before arm_reorg runs. */
3299 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
3300 && GET_CODE (x
) == SYMBOL_REF
3301 && CONSTANT_POOL_ADDRESS_P (x
) && ! flag_pic
)
3304 /* This is PC relative data after arm_reorg runs. */
3305 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
3306 && (GET_CODE (x
) == LABEL_REF
3307 || (GET_CODE (x
) == CONST
3308 && GET_CODE (XEXP (x
, 0)) == PLUS
3309 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
3310 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
3313 /* Post-inc indexing only supported for SImode and larger. */
3314 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
3315 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
3318 else if (GET_CODE (x
) == PLUS
)
3320 /* REG+REG address can be any two index registers. */
3321 /* We disallow FRAME+REG addressing since we know that FRAME
3322 will be replaced with STACK, and SP relative addressing only
3323 permits SP+OFFSET. */
3324 if (GET_MODE_SIZE (mode
) <= 4
3325 && XEXP (x
, 0) != frame_pointer_rtx
3326 && XEXP (x
, 1) != frame_pointer_rtx
3327 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3328 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
3331 /* REG+const has 5-7 bit offset for non-SP registers. */
3332 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
3333 || XEXP (x
, 0) == arg_pointer_rtx
)
3334 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3335 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
3338 /* REG+const has 10 bit offset for SP, but only SImode and
3339 larger is supported. */
3340 /* ??? Should probably check for DI/DFmode overflow here
3341 just like GO_IF_LEGITIMATE_OFFSET does. */
3342 else if (GET_CODE (XEXP (x
, 0)) == REG
3343 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
3344 && GET_MODE_SIZE (mode
) >= 4
3345 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3346 && INTVAL (XEXP (x
, 1)) >= 0
3347 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
3348 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3351 else if (GET_CODE (XEXP (x
, 0)) == REG
3352 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
3353 && GET_MODE_SIZE (mode
) >= 4
3354 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3355 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3359 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3360 && GET_MODE_SIZE (mode
) == 4
3361 && GET_CODE (x
) == SYMBOL_REF
3362 && CONSTANT_POOL_ADDRESS_P (x
)
3364 && symbol_mentioned_p (get_pool_constant (x
))))
3370 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3371 instruction of mode MODE. */
3373 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
3375 switch (GET_MODE_SIZE (mode
))
3378 return val
>= 0 && val
< 32;
3381 return val
>= 0 && val
< 64 && (val
& 1) == 0;
3385 && (val
+ GET_MODE_SIZE (mode
)) <= 128
3390 /* Try machine-dependent ways of modifying an illegitimate address
3391 to be legitimate. If we find one, return the new, valid address. */
3393 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3395 if (GET_CODE (x
) == PLUS
)
3397 rtx xop0
= XEXP (x
, 0);
3398 rtx xop1
= XEXP (x
, 1);
3400 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
3401 xop0
= force_reg (SImode
, xop0
);
3403 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
3404 xop1
= force_reg (SImode
, xop1
);
3406 if (ARM_BASE_REGISTER_RTX_P (xop0
)
3407 && GET_CODE (xop1
) == CONST_INT
)
3409 HOST_WIDE_INT n
, low_n
;
3413 /* VFP addressing modes actually allow greater offsets, but for
3414 now we just stick with the lowest common denominator. */
3416 || ((TARGET_SOFT_FLOAT
|| TARGET_VFP
) && mode
== DFmode
))
3428 low_n
= ((mode
) == TImode
? 0
3429 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
3433 base_reg
= gen_reg_rtx (SImode
);
3434 val
= force_operand (gen_rtx_PLUS (SImode
, xop0
,
3435 GEN_INT (n
)), NULL_RTX
);
3436 emit_move_insn (base_reg
, val
);
3437 x
= (low_n
== 0 ? base_reg
3438 : gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (low_n
)));
3440 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3441 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3444 /* XXX We don't allow MINUS any more -- see comment in
3445 arm_legitimate_address_p (). */
3446 else if (GET_CODE (x
) == MINUS
)
3448 rtx xop0
= XEXP (x
, 0);
3449 rtx xop1
= XEXP (x
, 1);
3451 if (CONSTANT_P (xop0
))
3452 xop0
= force_reg (SImode
, xop0
);
3454 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
3455 xop1
= force_reg (SImode
, xop1
);
3457 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3458 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
3463 /* We need to find and carefully transform any SYMBOL and LABEL
3464 references; so go back to the original address expression. */
3465 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3467 if (new_x
!= orig_x
)
3475 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3476 to be legitimate. If we find one, return the new, valid address. */
3478 thumb_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3480 if (GET_CODE (x
) == PLUS
3481 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3482 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
3483 || INTVAL (XEXP (x
, 1)) < 0))
3485 rtx xop0
= XEXP (x
, 0);
3486 rtx xop1
= XEXP (x
, 1);
3487 HOST_WIDE_INT offset
= INTVAL (xop1
);
3489 /* Try and fold the offset into a biasing of the base register and
3490 then offsetting that. Don't do this when optimizing for space
3491 since it can cause too many CSEs. */
3492 if (optimize_size
&& offset
>= 0
3493 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
3495 HOST_WIDE_INT delta
;
3498 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
3499 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
3500 delta
= 31 * GET_MODE_SIZE (mode
);
3502 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
3504 xop0
= force_operand (plus_constant (xop0
, offset
- delta
),
3506 x
= plus_constant (xop0
, delta
);
3508 else if (offset
< 0 && offset
> -256)
3509 /* Small negative offsets are best done with a subtract before the
3510 dereference, forcing these into a register normally takes two
3512 x
= force_operand (x
, NULL_RTX
);
3515 /* For the remaining cases, force the constant into a register. */
3516 xop1
= force_reg (SImode
, xop1
);
3517 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3520 else if (GET_CODE (x
) == PLUS
3521 && s_register_operand (XEXP (x
, 1), SImode
)
3522 && !s_register_operand (XEXP (x
, 0), SImode
))
3524 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
3526 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
3531 /* We need to find and carefully transform any SYMBOL and LABEL
3532 references; so go back to the original address expression. */
3533 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3535 if (new_x
!= orig_x
)
3544 #define REG_OR_SUBREG_REG(X) \
3545 (GET_CODE (X) == REG \
3546 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3548 #define REG_OR_SUBREG_RTX(X) \
3549 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3551 #ifndef COSTS_N_INSNS
3552 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3555 thumb_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
3557 enum machine_mode mode
= GET_MODE (x
);
3570 return COSTS_N_INSNS (1);
3573 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3576 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
3583 return COSTS_N_INSNS (2) + cycles
;
3585 return COSTS_N_INSNS (1) + 16;
3588 return (COSTS_N_INSNS (1)
3589 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
3590 + GET_CODE (SET_DEST (x
)) == MEM
));
3595 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
3597 if (thumb_shiftable_const (INTVAL (x
)))
3598 return COSTS_N_INSNS (2);
3599 return COSTS_N_INSNS (3);
3601 else if ((outer
== PLUS
|| outer
== COMPARE
)
3602 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
3604 else if (outer
== AND
3605 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
3606 return COSTS_N_INSNS (1);
3607 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
3608 || outer
== LSHIFTRT
)
3610 return COSTS_N_INSNS (2);
3616 return COSTS_N_INSNS (3);
3634 /* XXX another guess. */
3635 /* Memory costs quite a lot for the first word, but subsequent words
3636 load at the equivalent of a single insn each. */
3637 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3638 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
3643 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3648 /* XXX still guessing. */
3649 switch (GET_MODE (XEXP (x
, 0)))
3652 return (1 + (mode
== DImode
? 4 : 0)
3653 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3656 return (4 + (mode
== DImode
? 4 : 0)
3657 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3660 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3672 /* Worker routine for arm_rtx_costs. */
3674 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
3676 enum machine_mode mode
= GET_MODE (x
);
3677 enum rtx_code subcode
;
3683 /* Memory costs quite a lot for the first word, but subsequent words
3684 load at the equivalent of a single insn each. */
3685 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3686 + (GET_CODE (x
) == SYMBOL_REF
3687 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
3693 return optimize_size
? COSTS_N_INSNS (2) : 100;
3696 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
3703 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
3705 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
3706 + ((GET_CODE (XEXP (x
, 0)) == REG
3707 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3708 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3710 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
3711 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3712 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3714 + ((GET_CODE (XEXP (x
, 1)) == REG
3715 || (GET_CODE (XEXP (x
, 1)) == SUBREG
3716 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
3717 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
3722 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
3723 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3724 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
3725 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
3728 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3729 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3730 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3731 && arm_const_double_rtx (XEXP (x
, 1))))
3733 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3734 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
3735 && arm_const_double_rtx (XEXP (x
, 0))))
3738 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
3739 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
3740 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
3741 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
3742 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
3743 || subcode
== ROTATE
|| subcode
== ROTATERT
3745 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
3746 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
3747 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
3748 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
3749 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
3750 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
3751 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
3756 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3757 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3758 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3759 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3760 && arm_const_double_rtx (XEXP (x
, 1))))
3764 case AND
: case XOR
: case IOR
:
3767 /* Normally the frame registers will be spilt into reg+const during
3768 reload, so it is a bad idea to combine them with other instructions,
3769 since then they might not be moved outside of loops. As a compromise
3770 we allow integration with ops that have a constant as their second
3772 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3773 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
3774 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3775 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
3776 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
3780 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3781 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3782 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3783 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3786 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
3787 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
3788 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3789 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3790 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3793 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
3794 return (1 + extra_cost
3795 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
3796 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
3797 || subcode
== ROTATE
|| subcode
== ROTATERT
3799 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3800 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
3801 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
3802 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
3803 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
3804 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
3810 /* This should have been handled by the CPU specific routines. */
3814 if (arm_arch3m
&& mode
== SImode
3815 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3816 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
3817 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
3818 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
3819 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
3820 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
3825 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3826 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
3830 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
3832 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
3835 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3843 return 4 + (mode
== DImode
? 4 : 0);
3846 if (GET_MODE (XEXP (x
, 0)) == QImode
)
3847 return (4 + (mode
== DImode
? 4 : 0)
3848 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3851 switch (GET_MODE (XEXP (x
, 0)))
3854 return (1 + (mode
== DImode
? 4 : 0)
3855 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3858 return (4 + (mode
== DImode
? 4 : 0)
3859 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3862 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3877 if (const_ok_for_arm (INTVAL (x
)))
3878 return outer
== SET
? 2 : -1;
3879 else if (outer
== AND
3880 && const_ok_for_arm (~INTVAL (x
)))
3882 else if ((outer
== COMPARE
3883 || outer
== PLUS
|| outer
== MINUS
)
3884 && const_ok_for_arm (-INTVAL (x
)))
3895 if (arm_const_double_rtx (x
))
3896 return outer
== SET
? 2 : -1;
3897 else if ((outer
== COMPARE
|| outer
== PLUS
)
3898 && neg_const_double_rtx_ok_for_fpa (x
))
3907 /* RTX costs for cores with a slow MUL implementation. */
3910 arm_slowmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
3912 enum machine_mode mode
= GET_MODE (x
);
3916 *total
= thumb_rtx_costs (x
, code
, outer_code
);
3923 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3930 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3932 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
3933 & (unsigned HOST_WIDE_INT
) 0xffffffff);
3934 int cost
, const_ok
= const_ok_for_arm (i
);
3935 int j
, booth_unit_size
;
3937 /* Tune as appropriate. */
3938 cost
= const_ok
? 4 : 8;
3939 booth_unit_size
= 2;
3940 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
3942 i
>>= booth_unit_size
;
3950 *total
= 30 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
3951 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
3955 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
3961 /* RTX cost for cores with a fast multiply unit (M variants). */
3964 arm_fastmul_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
3966 enum machine_mode mode
= GET_MODE (x
);
3970 *total
= thumb_rtx_costs (x
, code
, outer_code
);
3977 /* There is no point basing this on the tuning, since it is always the
3978 fast variant if it exists at all. */
3980 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
3981 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
3982 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
3989 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3996 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3998 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
3999 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4000 int cost
, const_ok
= const_ok_for_arm (i
);
4001 int j
, booth_unit_size
;
4003 /* Tune as appropriate. */
4004 cost
= const_ok
? 4 : 8;
4005 booth_unit_size
= 8;
4006 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
4008 i
>>= booth_unit_size
;
4016 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4017 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4021 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4027 /* RTX cost for XScale CPUs. */
4030 arm_xscale_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4032 enum machine_mode mode
= GET_MODE (x
);
4036 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4043 /* There is no point basing this on the tuning, since it is always the
4044 fast variant if it exists at all. */
4046 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4047 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4048 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4055 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4062 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4064 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
4065 & (unsigned HOST_WIDE_INT
) 0xffffffff);
4066 int cost
, const_ok
= const_ok_for_arm (i
);
4067 unsigned HOST_WIDE_INT masked_const
;
4069 /* The cost will be related to two insns.
4070 First a load of the constant (MOV or LDR), then a multiply. */
4073 cost
+= 1; /* LDR is probably more expensive because
4074 of longer result latency. */
4075 masked_const
= i
& 0xffff8000;
4076 if (masked_const
!= 0 && masked_const
!= 0xffff8000)
4078 masked_const
= i
& 0xf8000000;
4079 if (masked_const
== 0 || masked_const
== 0xf8000000)
4088 *total
= 8 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
4089 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4);
4093 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4099 /* RTX costs for 9e (and later) cores. */
4102 arm_9e_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4104 enum machine_mode mode
= GET_MODE (x
);
4113 *total
= COSTS_N_INSNS (3);
4117 *total
= thumb_rtx_costs (x
, code
, outer_code
);
4125 /* There is no point basing this on the tuning, since it is always the
4126 fast variant if it exists at all. */
4128 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
4129 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
4130 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
4137 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4154 *total
= cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : nonreg_cost
)
4155 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : nonreg_cost
);
4159 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
4163 /* All address computations that can be done are free, but rtx cost returns
4164 the same for practically all of them. So we weight the different types
4165 of address here in the order (most pref first):
4166 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4168 arm_arm_address_cost (rtx x
)
4170 enum rtx_code c
= GET_CODE (x
);
4172 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
4174 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
4177 if (c
== PLUS
|| c
== MINUS
)
4179 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
4182 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
4192 arm_thumb_address_cost (rtx x
)
4194 enum rtx_code c
= GET_CODE (x
);
4199 && GET_CODE (XEXP (x
, 0)) == REG
4200 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4207 arm_address_cost (rtx x
)
4209 return TARGET_ARM
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
4213 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
4217 /* Some true dependencies can have a higher cost depending
4218 on precisely how certain input operands are used. */
4220 && REG_NOTE_KIND (link
) == 0
4221 && recog_memoized (insn
) >= 0
4222 && recog_memoized (dep
) >= 0)
4224 int shift_opnum
= get_attr_shift (insn
);
4225 enum attr_type attr_type
= get_attr_type (dep
);
4227 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4228 operand for INSN. If we have a shifted input operand and the
4229 instruction we depend on is another ALU instruction, then we may
4230 have to account for an additional stall. */
4231 if (shift_opnum
!= 0
4232 && (attr_type
== TYPE_ALU_SHIFT
|| attr_type
== TYPE_ALU_SHIFT_REG
))
4234 rtx shifted_operand
;
4237 /* Get the shifted operand. */
4238 extract_insn (insn
);
4239 shifted_operand
= recog_data
.operand
[shift_opnum
];
4241 /* Iterate over all the operands in DEP. If we write an operand
4242 that overlaps with SHIFTED_OPERAND, then we have increase the
4243 cost of this dependency. */
4245 preprocess_constraints ();
4246 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
4248 /* We can ignore strict inputs. */
4249 if (recog_data
.operand_type
[opno
] == OP_IN
)
4252 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
4259 /* XXX This is not strictly true for the FPA. */
4260 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
4261 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
4264 /* Call insns don't incur a stall, even if they follow a load. */
4265 if (REG_NOTE_KIND (link
) == 0
4266 && GET_CODE (insn
) == CALL_INSN
)
4269 if ((i_pat
= single_set (insn
)) != NULL
4270 && GET_CODE (SET_SRC (i_pat
)) == MEM
4271 && (d_pat
= single_set (dep
)) != NULL
4272 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
4274 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
4275 /* This is a load after a store, there is no conflict if the load reads
4276 from a cached area. Assume that loads from the stack, and from the
4277 constant pool are cached, and that others will miss. This is a
4280 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
4281 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
4282 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
4283 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
4290 static int fp_consts_inited
= 0;
4292 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4293 static const char * const strings_fp
[8] =
4296 "4", "5", "0.5", "10"
4299 static REAL_VALUE_TYPE values_fp
[8];
4302 init_fp_table (void)
4308 fp_consts_inited
= 1;
4310 fp_consts_inited
= 8;
4312 for (i
= 0; i
< fp_consts_inited
; i
++)
4314 r
= REAL_VALUE_ATOF (strings_fp
[i
], DFmode
);
4319 /* Return TRUE if rtx X is a valid immediate FP constant. */
4321 arm_const_double_rtx (rtx x
)
4326 if (!fp_consts_inited
)
4329 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4330 if (REAL_VALUE_MINUS_ZERO (r
))
4333 for (i
= 0; i
< fp_consts_inited
; i
++)
4334 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
4340 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4342 neg_const_double_rtx_ok_for_fpa (rtx x
)
4347 if (!fp_consts_inited
)
4350 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4351 r
= REAL_VALUE_NEGATE (r
);
4352 if (REAL_VALUE_MINUS_ZERO (r
))
4355 for (i
= 0; i
< 8; i
++)
4356 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
4362 /* Predicates for `match_operand' and `match_operator'. */
4364 /* s_register_operand is the same as register_operand, but it doesn't accept
4367 This function exists because at the time it was put in it led to better
4368 code. SUBREG(MEM) always needs a reload in the places where
4369 s_register_operand is used, and this seemed to lead to excessive
4372 s_register_operand (rtx op
, enum machine_mode mode
)
4374 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4377 if (GET_CODE (op
) == SUBREG
)
4378 op
= SUBREG_REG (op
);
4380 /* We don't consider registers whose class is NO_REGS
4381 to be a register operand. */
4382 /* XXX might have to check for lo regs only for thumb ??? */
4383 return (GET_CODE (op
) == REG
4384 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
4385 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
4388 /* A hard register operand (even before reload. */
4390 arm_hard_register_operand (rtx op
, enum machine_mode mode
)
4392 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4395 return (GET_CODE (op
) == REG
4396 && REGNO (op
) < FIRST_PSEUDO_REGISTER
);
4399 /* An arm register operand. */
4401 arm_general_register_operand (rtx op
, enum machine_mode mode
)
4403 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4406 if (GET_CODE (op
) == SUBREG
)
4407 op
= SUBREG_REG (op
);
4409 return (GET_CODE (op
) == REG
4410 && (REGNO (op
) <= LAST_ARM_REGNUM
4411 || REGNO (op
) >= FIRST_PSEUDO_REGISTER
));
4414 /* Only accept reg, subreg(reg), const_int. */
4416 reg_or_int_operand (rtx op
, enum machine_mode mode
)
4418 if (GET_CODE (op
) == CONST_INT
)
4421 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4424 if (GET_CODE (op
) == SUBREG
)
4425 op
= SUBREG_REG (op
);
4427 /* We don't consider registers whose class is NO_REGS
4428 to be a register operand. */
4429 return (GET_CODE (op
) == REG
4430 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
4431 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
4434 /* Return 1 if OP is an item in memory, given that we are in reload. */
4436 arm_reload_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4438 int regno
= true_regnum (op
);
4440 return (!CONSTANT_P (op
)
4442 || (GET_CODE (op
) == REG
4443 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)));
4446 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
4448 arm_rhs_operand (rtx op
, enum machine_mode mode
)
4450 return (s_register_operand (op
, mode
)
4451 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
))));
4454 /* Return TRUE for valid operands for the
4455 rhs of an ARM instruction, or a load. */
4457 arm_rhsm_operand (rtx op
, enum machine_mode mode
)
4459 return (s_register_operand (op
, mode
)
4460 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
)))
4461 || memory_operand (op
, mode
));
4464 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
4465 constant that is valid when negated. */
4467 arm_add_operand (rtx op
, enum machine_mode mode
)
4470 return thumb_cmp_operand (op
, mode
);
4472 return (s_register_operand (op
, mode
)
4473 || (GET_CODE (op
) == CONST_INT
4474 && (const_ok_for_arm (INTVAL (op
))
4475 || const_ok_for_arm (-INTVAL (op
)))));
4478 /* Return TRUE for valid ARM constants (or when valid if negated). */
4480 arm_addimm_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4482 return (GET_CODE (op
) == CONST_INT
4483 && (const_ok_for_arm (INTVAL (op
))
4484 || const_ok_for_arm (-INTVAL (op
))));
4488 arm_not_operand (rtx op
, enum machine_mode mode
)
4490 return (s_register_operand (op
, mode
)
4491 || (GET_CODE (op
) == CONST_INT
4492 && (const_ok_for_arm (INTVAL (op
))
4493 || const_ok_for_arm (~INTVAL (op
)))));
4496 /* Return TRUE if the operand is a memory reference which contains an
4497 offsettable address. */
4499 offsettable_memory_operand (rtx op
, enum machine_mode mode
)
4501 if (mode
== VOIDmode
)
4502 mode
= GET_MODE (op
);
4504 return (mode
== GET_MODE (op
)
4505 && GET_CODE (op
) == MEM
4506 && offsettable_address_p (reload_completed
| reload_in_progress
,
4507 mode
, XEXP (op
, 0)));
4510 /* Return TRUE if the operand is a memory reference which is, or can be
4511 made word aligned by adjusting the offset. */
4513 alignable_memory_operand (rtx op
, enum machine_mode mode
)
4517 if (mode
== VOIDmode
)
4518 mode
= GET_MODE (op
);
4520 if (mode
!= GET_MODE (op
) || GET_CODE (op
) != MEM
)
4525 return ((GET_CODE (reg
= op
) == REG
4526 || (GET_CODE (op
) == SUBREG
4527 && GET_CODE (reg
= SUBREG_REG (op
)) == REG
)
4528 || (GET_CODE (op
) == PLUS
4529 && GET_CODE (XEXP (op
, 1)) == CONST_INT
4530 && (GET_CODE (reg
= XEXP (op
, 0)) == REG
4531 || (GET_CODE (XEXP (op
, 0)) == SUBREG
4532 && GET_CODE (reg
= SUBREG_REG (XEXP (op
, 0))) == REG
))))
4533 && REGNO_POINTER_ALIGN (REGNO (reg
)) >= 32);
4536 /* Similar to s_register_operand, but does not allow hard integer
4539 f_register_operand (rtx op
, enum machine_mode mode
)
4541 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4544 if (GET_CODE (op
) == SUBREG
)
4545 op
= SUBREG_REG (op
);
4547 /* We don't consider registers whose class is NO_REGS
4548 to be a register operand. */
4549 return (GET_CODE (op
) == REG
4550 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
4551 || REGNO_REG_CLASS (REGNO (op
)) == FPA_REGS
));
4554 /* Return TRUE for valid operands for the rhs of an floating point insns.
4555 Allows regs or certain consts on FPA, just regs for everything else. */
4557 arm_float_rhs_operand (rtx op
, enum machine_mode mode
)
4559 if (s_register_operand (op
, mode
))
4562 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4565 if (TARGET_FPA
&& GET_CODE (op
) == CONST_DOUBLE
)
4566 return arm_const_double_rtx (op
);
4572 arm_float_add_operand (rtx op
, enum machine_mode mode
)
4574 if (s_register_operand (op
, mode
))
4577 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4580 if (TARGET_FPA
&& GET_CODE (op
) == CONST_DOUBLE
)
4581 return (arm_const_double_rtx (op
)
4582 || neg_const_double_rtx_ok_for_fpa (op
));
4588 /* Return TRUE if OP is suitable for the rhs of a floating point comparison.
4589 Depends which fpu we are targeting. */
4592 arm_float_compare_operand (rtx op
, enum machine_mode mode
)
4595 return vfp_compare_operand (op
, mode
);
4597 return arm_float_rhs_operand (op
, mode
);
4601 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4603 cirrus_memory_offset (rtx op
)
4605 /* Reject eliminable registers. */
4606 if (! (reload_in_progress
|| reload_completed
)
4607 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
4608 || reg_mentioned_p (arg_pointer_rtx
, op
)
4609 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
4610 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
4611 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
4612 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
4615 if (GET_CODE (op
) == MEM
)
4621 /* Match: (mem (reg)). */
4622 if (GET_CODE (ind
) == REG
)
4628 if (GET_CODE (ind
) == PLUS
4629 && GET_CODE (XEXP (ind
, 0)) == REG
4630 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
4631 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
4639 arm_extendqisi_mem_op (rtx op
, enum machine_mode mode
)
4641 if (!memory_operand (op
, mode
))
4644 return arm_legitimate_address_p (mode
, XEXP (op
, 0), SIGN_EXTEND
, 0);
4647 /* Return nonzero if OP is a Cirrus or general register. */
4649 cirrus_register_operand (rtx op
, enum machine_mode mode
)
4651 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4654 if (GET_CODE (op
) == SUBREG
)
4655 op
= SUBREG_REG (op
);
4657 return (GET_CODE (op
) == REG
4658 && (REGNO_REG_CLASS (REGNO (op
)) == CIRRUS_REGS
4659 || REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
));
4662 /* Return nonzero if OP is a cirrus FP register. */
4664 cirrus_fp_register (rtx op
, enum machine_mode mode
)
4666 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4669 if (GET_CODE (op
) == SUBREG
)
4670 op
= SUBREG_REG (op
);
4672 return (GET_CODE (op
) == REG
4673 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
4674 || REGNO_REG_CLASS (REGNO (op
)) == CIRRUS_REGS
));
4677 /* Return nonzero if OP is a 6bit constant (0..63). */
4679 cirrus_shift_const (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4681 return (GET_CODE (op
) == CONST_INT
4683 && INTVAL (op
) < 64);
4687 /* Return TRUE if OP is a valid VFP memory address pattern.
4688 WB if true if writeback address modes are allowed. */
4691 arm_coproc_mem_operand (rtx op
, bool wb
)
4695 /* Reject eliminable registers. */
4696 if (! (reload_in_progress
|| reload_completed
)
4697 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
4698 || reg_mentioned_p (arg_pointer_rtx
, op
)
4699 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
4700 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
4701 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
4702 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
4705 /* Constants are converted into offsets from labels. */
4706 if (GET_CODE (op
) != MEM
)
4711 if (reload_completed
4712 && (GET_CODE (ind
) == LABEL_REF
4713 || (GET_CODE (ind
) == CONST
4714 && GET_CODE (XEXP (ind
, 0)) == PLUS
4715 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
4716 && GET_CODE (XEXP (XEXP (ind
, 0), 1)) == CONST_INT
)))
4719 /* Match: (mem (reg)). */
4720 if (GET_CODE (ind
) == REG
)
4721 return arm_address_register_rtx_p (ind
, 0);
4723 /* Autoincremment addressing modes. */
4725 && (GET_CODE (ind
) == PRE_INC
4726 || GET_CODE (ind
) == POST_INC
4727 || GET_CODE (ind
) == PRE_DEC
4728 || GET_CODE (ind
) == POST_DEC
))
4729 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
4732 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
4733 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
4734 && GET_CODE (XEXP (ind
, 1)) == PLUS
4735 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
4736 ind
= XEXP (ind
, 1);
4741 if (GET_CODE (ind
) == PLUS
4742 && GET_CODE (XEXP (ind
, 0)) == REG
4743 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
4744 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
4745 && INTVAL (XEXP (ind
, 1)) > -1024
4746 && INTVAL (XEXP (ind
, 1)) < 1024
4747 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
4754 /* Return TRUE if OP is a REG or constant zero. */
4756 vfp_compare_operand (rtx op
, enum machine_mode mode
)
4758 if (s_register_operand (op
, mode
))
4761 return (GET_CODE (op
) == CONST_DOUBLE
4762 && arm_const_double_rtx (op
));
4766 /* Return GENERAL_REGS if a scratch register required to reload x to/from
4767 VFP registers. Otherwise return NO_REGS. */
4770 vfp_secondary_reload_class (enum machine_mode mode
, rtx x
)
4772 if (arm_coproc_mem_operand (x
, FALSE
) || s_register_operand (x
, mode
))
4775 return GENERAL_REGS
;
4779 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4780 Use by the Cirrus Maverick code which has to workaround
4781 a hardware bug triggered by such instructions. */
4783 arm_memory_load_p (rtx insn
)
4785 rtx body
, lhs
, rhs
;;
4787 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
4790 body
= PATTERN (insn
);
4792 if (GET_CODE (body
) != SET
)
4795 lhs
= XEXP (body
, 0);
4796 rhs
= XEXP (body
, 1);
4798 lhs
= REG_OR_SUBREG_RTX (lhs
);
4800 /* If the destination is not a general purpose
4801 register we do not have to worry. */
4802 if (GET_CODE (lhs
) != REG
4803 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
4806 /* As well as loads from memory we also have to react
4807 to loads of invalid constants which will be turned
4808 into loads from the minipool. */
4809 return (GET_CODE (rhs
) == MEM
4810 || GET_CODE (rhs
) == SYMBOL_REF
4811 || note_invalid_constants (insn
, -1, false));
4814 /* Return TRUE if INSN is a Cirrus instruction. */
4816 arm_cirrus_insn_p (rtx insn
)
4818 enum attr_cirrus attr
;
4820 /* get_attr aborts on USE and CLOBBER. */
4822 || GET_CODE (insn
) != INSN
4823 || GET_CODE (PATTERN (insn
)) == USE
4824 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4827 attr
= get_attr_cirrus (insn
);
4829 return attr
!= CIRRUS_NOT
;
4832 /* Cirrus reorg for invalid instruction combinations. */
4834 cirrus_reorg (rtx first
)
4836 enum attr_cirrus attr
;
4837 rtx body
= PATTERN (first
);
4841 /* Any branch must be followed by 2 non Cirrus instructions. */
4842 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
4845 t
= next_nonnote_insn (first
);
4847 if (arm_cirrus_insn_p (t
))
4850 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
4854 emit_insn_after (gen_nop (), first
);
4859 /* (float (blah)) is in parallel with a clobber. */
4860 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
4861 body
= XVECEXP (body
, 0, 0);
4863 if (GET_CODE (body
) == SET
)
4865 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
4867 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4868 be followed by a non Cirrus insn. */
4869 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
4871 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
4872 emit_insn_after (gen_nop (), first
);
4876 else if (arm_memory_load_p (first
))
4878 unsigned int arm_regno
;
4880 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4881 ldr/cfmv64hr combination where the Rd field is the same
4882 in both instructions must be split with a non Cirrus
4889 /* Get Arm register number for ldr insn. */
4890 if (GET_CODE (lhs
) == REG
)
4891 arm_regno
= REGNO (lhs
);
4892 else if (GET_CODE (rhs
) == REG
)
4893 arm_regno
= REGNO (rhs
);
4898 first
= next_nonnote_insn (first
);
4900 if (! arm_cirrus_insn_p (first
))
4903 body
= PATTERN (first
);
4905 /* (float (blah)) is in parallel with a clobber. */
4906 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
4907 body
= XVECEXP (body
, 0, 0);
4909 if (GET_CODE (body
) == FLOAT
)
4910 body
= XEXP (body
, 0);
4912 if (get_attr_cirrus (first
) == CIRRUS_MOVE
4913 && GET_CODE (XEXP (body
, 1)) == REG
4914 && arm_regno
== REGNO (XEXP (body
, 1)))
4915 emit_insn_after (gen_nop (), first
);
4921 /* get_attr aborts on USE and CLOBBER. */
4923 || GET_CODE (first
) != INSN
4924 || GET_CODE (PATTERN (first
)) == USE
4925 || GET_CODE (PATTERN (first
)) == CLOBBER
)
4928 attr
= get_attr_cirrus (first
);
4930 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4931 must be followed by a non-coprocessor instruction. */
4932 if (attr
== CIRRUS_COMPARE
)
4936 t
= next_nonnote_insn (first
);
4938 if (arm_cirrus_insn_p (t
))
4941 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
4945 emit_insn_after (gen_nop (), first
);
4951 /* Return nonzero if OP is a constant power of two. */
4953 power_of_two_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4955 if (GET_CODE (op
) == CONST_INT
)
4957 HOST_WIDE_INT value
= INTVAL (op
);
4959 return value
!= 0 && (value
& (value
- 1)) == 0;
4965 /* Return TRUE for a valid operand of a DImode operation.
4966 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4967 Note that this disallows MEM(REG+REG), but allows
4968 MEM(PRE/POST_INC/DEC(REG)). */
4970 di_operand (rtx op
, enum machine_mode mode
)
4972 if (s_register_operand (op
, mode
))
4975 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
4978 if (GET_CODE (op
) == SUBREG
)
4979 op
= SUBREG_REG (op
);
4981 switch (GET_CODE (op
))
4988 return memory_address_p (DImode
, XEXP (op
, 0));
4995 /* Like di_operand, but don't accept constants. */
4997 nonimmediate_di_operand (rtx op
, enum machine_mode mode
)
4999 if (s_register_operand (op
, mode
))
5002 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
5005 if (GET_CODE (op
) == SUBREG
)
5006 op
= SUBREG_REG (op
);
5008 if (GET_CODE (op
) == MEM
)
5009 return memory_address_p (DImode
, XEXP (op
, 0));
5014 /* Return TRUE for a valid operand of a DFmode operation when soft-float.
5015 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
5016 Note that this disallows MEM(REG+REG), but allows
5017 MEM(PRE/POST_INC/DEC(REG)). */
5019 soft_df_operand (rtx op
, enum machine_mode mode
)
5021 if (s_register_operand (op
, mode
))
5024 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
5027 if (GET_CODE (op
) == SUBREG
&& CONSTANT_P (SUBREG_REG (op
)))
5030 if (GET_CODE (op
) == SUBREG
)
5031 op
= SUBREG_REG (op
);
5033 switch (GET_CODE (op
))
5039 return memory_address_p (DFmode
, XEXP (op
, 0));
5046 /* Like soft_df_operand, but don't accept constants. */
5048 nonimmediate_soft_df_operand (rtx op
, enum machine_mode mode
)
5050 if (s_register_operand (op
, mode
))
5053 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
5056 if (GET_CODE (op
) == SUBREG
)
5057 op
= SUBREG_REG (op
);
5059 if (GET_CODE (op
) == MEM
)
5060 return memory_address_p (DFmode
, XEXP (op
, 0));
5064 /* Return TRUE for valid index operands. */
5066 index_operand (rtx op
, enum machine_mode mode
)
5068 return (s_register_operand (op
, mode
)
5069 || (immediate_operand (op
, mode
)
5070 && (GET_CODE (op
) != CONST_INT
5071 || (INTVAL (op
) < 4096 && INTVAL (op
) > -4096))));
5074 /* Return TRUE for valid shifts by a constant. This also accepts any
5075 power of two on the (somewhat overly relaxed) assumption that the
5076 shift operator in this case was a mult. */
5078 const_shift_operand (rtx op
, enum machine_mode mode
)
5080 return (power_of_two_operand (op
, mode
)
5081 || (immediate_operand (op
, mode
)
5082 && (GET_CODE (op
) != CONST_INT
5083 || (INTVAL (op
) < 32 && INTVAL (op
) > 0))));
5086 /* Return TRUE for arithmetic operators which can be combined with a multiply
5089 shiftable_operator (rtx x
, enum machine_mode mode
)
5093 if (GET_MODE (x
) != mode
)
5096 code
= GET_CODE (x
);
5098 return (code
== PLUS
|| code
== MINUS
5099 || code
== IOR
|| code
== XOR
|| code
== AND
);
5102 /* Return TRUE for binary logical operators. */
5104 logical_binary_operator (rtx x
, enum machine_mode mode
)
5108 if (GET_MODE (x
) != mode
)
5111 code
= GET_CODE (x
);
5113 return (code
== IOR
|| code
== XOR
|| code
== AND
);
5116 /* Return TRUE for shift operators. */
5118 shift_operator (rtx x
,enum machine_mode mode
)
5122 if (GET_MODE (x
) != mode
)
5125 code
= GET_CODE (x
);
5128 return power_of_two_operand (XEXP (x
, 1), mode
);
5130 return (code
== ASHIFT
|| code
== ASHIFTRT
|| code
== LSHIFTRT
5131 || code
== ROTATERT
);
5134 /* Return TRUE if x is EQ or NE. */
5136 equality_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5138 return GET_CODE (x
) == EQ
|| GET_CODE (x
) == NE
;
5141 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
5143 arm_comparison_operator (rtx x
, enum machine_mode mode
)
5145 return (comparison_operator (x
, mode
)
5146 && GET_CODE (x
) != LTGT
5147 && GET_CODE (x
) != UNEQ
);
5150 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
5152 minmax_operator (rtx x
, enum machine_mode mode
)
5154 enum rtx_code code
= GET_CODE (x
);
5156 if (GET_MODE (x
) != mode
)
5159 return code
== SMIN
|| code
== SMAX
|| code
== UMIN
|| code
== UMAX
;
5162 /* Return TRUE if this is the condition code register, if we aren't given
5163 a mode, accept any class CCmode register. */
5165 cc_register (rtx x
, enum machine_mode mode
)
5167 if (mode
== VOIDmode
)
5169 mode
= GET_MODE (x
);
5171 if (GET_MODE_CLASS (mode
) != MODE_CC
)
5175 if ( GET_MODE (x
) == mode
5176 && GET_CODE (x
) == REG
5177 && REGNO (x
) == CC_REGNUM
)
5183 /* Return TRUE if this is the condition code register, if we aren't given
5184 a mode, accept any class CCmode register which indicates a dominance
5187 dominant_cc_register (rtx x
, enum machine_mode mode
)
5189 if (mode
== VOIDmode
)
5191 mode
= GET_MODE (x
);
5193 if (GET_MODE_CLASS (mode
) != MODE_CC
)
5197 if (mode
!= CC_DNEmode
&& mode
!= CC_DEQmode
5198 && mode
!= CC_DLEmode
&& mode
!= CC_DLTmode
5199 && mode
!= CC_DGEmode
&& mode
!= CC_DGTmode
5200 && mode
!= CC_DLEUmode
&& mode
!= CC_DLTUmode
5201 && mode
!= CC_DGEUmode
&& mode
!= CC_DGTUmode
)
5204 return cc_register (x
, mode
);
5207 /* Return TRUE if X references a SYMBOL_REF. */
5209 symbol_mentioned_p (rtx x
)
5214 if (GET_CODE (x
) == SYMBOL_REF
)
5217 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5219 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5225 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5226 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5229 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
5236 /* Return TRUE if X references a LABEL_REF. */
5238 label_mentioned_p (rtx x
)
5243 if (GET_CODE (x
) == LABEL_REF
)
5246 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5247 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5253 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5254 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
5257 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
5267 enum rtx_code code
= GET_CODE (x
);
5271 else if (code
== SMIN
)
5273 else if (code
== UMIN
)
5275 else if (code
== UMAX
)
5281 /* Return 1 if memory locations are adjacent. */
5283 adjacent_mem_locations (rtx a
, rtx b
)
5285 if ((GET_CODE (XEXP (a
, 0)) == REG
5286 || (GET_CODE (XEXP (a
, 0)) == PLUS
5287 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
5288 && (GET_CODE (XEXP (b
, 0)) == REG
5289 || (GET_CODE (XEXP (b
, 0)) == PLUS
5290 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
5292 int val0
= 0, val1
= 0;
5295 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
5297 reg0
= REGNO (XEXP (XEXP (a
, 0), 0));
5298 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
5301 reg0
= REGNO (XEXP (a
, 0));
5303 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
5305 reg1
= REGNO (XEXP (XEXP (b
, 0), 0));
5306 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
5309 reg1
= REGNO (XEXP (b
, 0));
5311 /* Don't accept any offset that will require multiple
5312 instructions to handle, since this would cause the
5313 arith_adjacentmem pattern to output an overlong sequence. */
5314 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
5317 return (reg0
== reg1
) && ((val1
- val0
) == 4 || (val0
- val1
) == 4);
5322 /* Return 1 if OP is a load multiple operation. It is known to be
5323 parallel and the first section will be tested. */
5325 load_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5327 HOST_WIDE_INT count
= XVECLEN (op
, 0);
5330 HOST_WIDE_INT i
= 1, base
= 0;
5334 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
5337 /* Check to see if this might be a write-back. */
5338 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
5343 /* Now check it more carefully. */
5344 if (GET_CODE (SET_DEST (elt
)) != REG
5345 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
5346 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
5347 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
5351 /* Perform a quick check so we don't blow up below. */
5353 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
5354 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != REG
5355 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != MEM
)
5358 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, i
- 1)));
5359 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, i
- 1)), 0);
5361 for (; i
< count
; i
++)
5363 elt
= XVECEXP (op
, 0, i
);
5365 if (GET_CODE (elt
) != SET
5366 || GET_CODE (SET_DEST (elt
)) != REG
5367 || GET_MODE (SET_DEST (elt
)) != SImode
5368 || REGNO (SET_DEST (elt
)) != (unsigned int)(dest_regno
+ i
- base
)
5369 || GET_CODE (SET_SRC (elt
)) != MEM
5370 || GET_MODE (SET_SRC (elt
)) != SImode
5371 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
5372 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
5373 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
5374 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != (i
- base
) * 4)
5381 /* Return 1 if OP is a store multiple operation. It is known to be
5382 parallel and the first section will be tested. */
5384 store_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5386 HOST_WIDE_INT count
= XVECLEN (op
, 0);
5389 HOST_WIDE_INT i
= 1, base
= 0;
5393 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
5396 /* Check to see if this might be a write-back. */
5397 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
5402 /* Now check it more carefully. */
5403 if (GET_CODE (SET_DEST (elt
)) != REG
5404 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
5405 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
5406 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
5410 /* Perform a quick check so we don't blow up below. */
5412 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
5413 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != MEM
5414 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != REG
)
5417 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, i
- 1)));
5418 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, i
- 1)), 0);
5420 for (; i
< count
; i
++)
5422 elt
= XVECEXP (op
, 0, i
);
5424 if (GET_CODE (elt
) != SET
5425 || GET_CODE (SET_SRC (elt
)) != REG
5426 || GET_MODE (SET_SRC (elt
)) != SImode
5427 || REGNO (SET_SRC (elt
)) != (unsigned int)(src_regno
+ i
- base
)
5428 || GET_CODE (SET_DEST (elt
)) != MEM
5429 || GET_MODE (SET_DEST (elt
)) != SImode
5430 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
5431 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
5432 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
5433 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != (i
- base
) * 4)
5441 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5442 HOST_WIDE_INT
*load_offset
)
5444 int unsorted_regs
[4];
5445 HOST_WIDE_INT unsorted_offsets
[4];
5450 /* Can only handle 2, 3, or 4 insns at present,
5451 though could be easily extended if required. */
5452 if (nops
< 2 || nops
> 4)
5455 /* Loop over the operands and check that the memory references are
5456 suitable (ie immediate offsets from the same base register). At
5457 the same time, extract the target register, and the memory
5459 for (i
= 0; i
< nops
; i
++)
5464 /* Convert a subreg of a mem into the mem itself. */
5465 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5466 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5468 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
5471 /* Don't reorder volatile memory references; it doesn't seem worth
5472 looking for the case where the order is ok anyway. */
5473 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5476 offset
= const0_rtx
;
5478 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5479 || (GET_CODE (reg
) == SUBREG
5480 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5481 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5482 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5484 || (GET_CODE (reg
) == SUBREG
5485 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5486 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5491 base_reg
= REGNO (reg
);
5492 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5493 ? REGNO (operands
[i
])
5494 : REGNO (SUBREG_REG (operands
[i
])));
5499 if (base_reg
!= (int) REGNO (reg
))
5500 /* Not addressed from the same base register. */
5503 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5504 ? REGNO (operands
[i
])
5505 : REGNO (SUBREG_REG (operands
[i
])));
5506 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5510 /* If it isn't an integer register, or if it overwrites the
5511 base register but isn't the last insn in the list, then
5512 we can't do this. */
5513 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
5514 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
5517 unsorted_offsets
[i
] = INTVAL (offset
);
5520 /* Not a suitable memory address. */
5524 /* All the useful information has now been extracted from the
5525 operands into unsorted_regs and unsorted_offsets; additionally,
5526 order[0] has been set to the lowest numbered register in the
5527 list. Sort the registers into order, and check that the memory
5528 offsets are ascending and adjacent. */
5530 for (i
= 1; i
< nops
; i
++)
5534 order
[i
] = order
[i
- 1];
5535 for (j
= 0; j
< nops
; j
++)
5536 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5537 && (order
[i
] == order
[i
- 1]
5538 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5541 /* Have we found a suitable register? if not, one must be used more
5543 if (order
[i
] == order
[i
- 1])
5546 /* Is the memory address adjacent and ascending? */
5547 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5555 for (i
= 0; i
< nops
; i
++)
5556 regs
[i
] = unsorted_regs
[order
[i
]];
5558 *load_offset
= unsorted_offsets
[order
[0]];
5561 if (unsorted_offsets
[order
[0]] == 0)
5562 return 1; /* ldmia */
5564 if (unsorted_offsets
[order
[0]] == 4)
5565 return 2; /* ldmib */
5567 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5568 return 3; /* ldmda */
5570 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5571 return 4; /* ldmdb */
5573 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5574 if the offset isn't small enough. The reason 2 ldrs are faster
5575 is because these ARMs are able to do more than one cache access
5576 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5577 whilst the ARM8 has a double bandwidth cache. This means that
5578 these cores can do both an instruction fetch and a data fetch in
5579 a single cycle, so the trick of calculating the address into a
5580 scratch register (one of the result regs) and then doing a load
5581 multiple actually becomes slower (and no smaller in code size).
5582 That is the transformation
5584 ldr rd1, [rbase + offset]
5585 ldr rd2, [rbase + offset + 4]
5589 add rd1, rbase, offset
5590 ldmia rd1, {rd1, rd2}
5592 produces worse code -- '3 cycles + any stalls on rd2' instead of
5593 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5594 access per cycle, the first sequence could never complete in less
5595 than 6 cycles, whereas the ldm sequence would only take 5 and
5596 would make better use of sequential accesses if not hitting the
5599 We cheat here and test 'arm_ld_sched' which we currently know to
5600 only be true for the ARM8, ARM9 and StrongARM. If this ever
5601 changes, then the test below needs to be reworked. */
5602 if (nops
== 2 && arm_ld_sched
)
5605 /* Can't do it without setting up the offset, only do this if it takes
5606 no more than one insn. */
5607 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
5608 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
5612 emit_ldm_seq (rtx
*operands
, int nops
)
5616 HOST_WIDE_INT offset
;
5620 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5623 strcpy (buf
, "ldm%?ia\t");
5627 strcpy (buf
, "ldm%?ib\t");
5631 strcpy (buf
, "ldm%?da\t");
5635 strcpy (buf
, "ldm%?db\t");
5640 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5641 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5644 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
5645 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
5647 output_asm_insn (buf
, operands
);
5649 strcpy (buf
, "ldm%?ia\t");
5656 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5657 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5659 for (i
= 1; i
< nops
; i
++)
5660 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5661 reg_names
[regs
[i
]]);
5663 strcat (buf
, "}\t%@ phole ldm");
5665 output_asm_insn (buf
, operands
);
5670 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
5671 HOST_WIDE_INT
* load_offset
)
5673 int unsorted_regs
[4];
5674 HOST_WIDE_INT unsorted_offsets
[4];
5679 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5680 extended if required. */
5681 if (nops
< 2 || nops
> 4)
5684 /* Loop over the operands and check that the memory references are
5685 suitable (ie immediate offsets from the same base register). At
5686 the same time, extract the target register, and the memory
5688 for (i
= 0; i
< nops
; i
++)
5693 /* Convert a subreg of a mem into the mem itself. */
5694 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
5695 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
5697 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
5700 /* Don't reorder volatile memory references; it doesn't seem worth
5701 looking for the case where the order is ok anyway. */
5702 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
5705 offset
= const0_rtx
;
5707 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
5708 || (GET_CODE (reg
) == SUBREG
5709 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5710 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
5711 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
5713 || (GET_CODE (reg
) == SUBREG
5714 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
5715 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
5720 base_reg
= REGNO (reg
);
5721 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
5722 ? REGNO (operands
[i
])
5723 : REGNO (SUBREG_REG (operands
[i
])));
5728 if (base_reg
!= (int) REGNO (reg
))
5729 /* Not addressed from the same base register. */
5732 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5733 ? REGNO (operands
[i
])
5734 : REGNO (SUBREG_REG (operands
[i
])));
5735 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5739 /* If it isn't an integer register, then we can't do this. */
5740 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
5743 unsorted_offsets
[i
] = INTVAL (offset
);
5746 /* Not a suitable memory address. */
5750 /* All the useful information has now been extracted from the
5751 operands into unsorted_regs and unsorted_offsets; additionally,
5752 order[0] has been set to the lowest numbered register in the
5753 list. Sort the registers into order, and check that the memory
5754 offsets are ascending and adjacent. */
5756 for (i
= 1; i
< nops
; i
++)
5760 order
[i
] = order
[i
- 1];
5761 for (j
= 0; j
< nops
; j
++)
5762 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5763 && (order
[i
] == order
[i
- 1]
5764 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5767 /* Have we found a suitable register? if not, one must be used more
5769 if (order
[i
] == order
[i
- 1])
5772 /* Is the memory address adjacent and ascending? */
5773 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5781 for (i
= 0; i
< nops
; i
++)
5782 regs
[i
] = unsorted_regs
[order
[i
]];
5784 *load_offset
= unsorted_offsets
[order
[0]];
5787 if (unsorted_offsets
[order
[0]] == 0)
5788 return 1; /* stmia */
5790 if (unsorted_offsets
[order
[0]] == 4)
5791 return 2; /* stmib */
5793 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5794 return 3; /* stmda */
5796 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5797 return 4; /* stmdb */
5803 emit_stm_seq (rtx
*operands
, int nops
)
5807 HOST_WIDE_INT offset
;
5811 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5814 strcpy (buf
, "stm%?ia\t");
5818 strcpy (buf
, "stm%?ib\t");
5822 strcpy (buf
, "stm%?da\t");
5826 strcpy (buf
, "stm%?db\t");
5833 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5834 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5836 for (i
= 1; i
< nops
; i
++)
5837 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5838 reg_names
[regs
[i
]]);
5840 strcat (buf
, "}\t%@ phole stm");
5842 output_asm_insn (buf
, operands
);
5847 multi_register_push (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5849 if (GET_CODE (op
) != PARALLEL
5850 || (GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
5851 || (GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
)
5852 || (XINT (SET_SRC (XVECEXP (op
, 0, 0)), 1) != UNSPEC_PUSH_MULT
))
5858 /* Routines for use in generating RTL. */
5861 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
5862 int write_back
, int unchanging_p
, int in_struct_p
,
5867 int sign
= up
? 1 : -1;
5870 /* XScale has load-store double instructions, but they have stricter
5871 alignment requirements than load-store multiple, so we can not
5874 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5875 the pipeline until completion.
5883 An ldr instruction takes 1-3 cycles, but does not block the
5892 Best case ldr will always win. However, the more ldr instructions
5893 we issue, the less likely we are to be able to schedule them well.
5894 Using ldr instructions also increases code size.
5896 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5897 for counts of 3 or 4 regs. */
5898 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5904 for (i
= 0; i
< count
; i
++)
5906 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, i
* 4 * sign
));
5907 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5908 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5909 MEM_SCALAR_P (mem
) = scalar_p
;
5910 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
5914 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
5922 result
= gen_rtx_PARALLEL (VOIDmode
,
5923 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5926 XVECEXP (result
, 0, 0)
5927 = gen_rtx_SET (GET_MODE (from
), from
,
5928 plus_constant (from
, count
* 4 * sign
));
5933 for (j
= 0; i
< count
; i
++, j
++)
5935 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, j
* 4 * sign
));
5936 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5937 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5938 MEM_SCALAR_P (mem
) = scalar_p
;
5939 XVECEXP (result
, 0, i
)
5940 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
5947 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
5948 int write_back
, int unchanging_p
, int in_struct_p
,
5953 int sign
= up
? 1 : -1;
5956 /* See arm_gen_load_multiple for discussion of
5957 the pros/cons of ldm/stm usage for XScale. */
5958 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5964 for (i
= 0; i
< count
; i
++)
5966 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, i
* 4 * sign
));
5967 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5968 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5969 MEM_SCALAR_P (mem
) = scalar_p
;
5970 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
5974 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
5982 result
= gen_rtx_PARALLEL (VOIDmode
,
5983 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5986 XVECEXP (result
, 0, 0)
5987 = gen_rtx_SET (GET_MODE (to
), to
,
5988 plus_constant (to
, count
* 4 * sign
));
5993 for (j
= 0; i
< count
; i
++, j
++)
5995 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, j
* 4 * sign
));
5996 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5997 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5998 MEM_SCALAR_P (mem
) = scalar_p
;
6000 XVECEXP (result
, 0, i
)
6001 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
6008 arm_gen_movmemqi (rtx
*operands
)
6010 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
6013 rtx st_src
, st_dst
, fin_src
, fin_dst
;
6014 rtx part_bytes_reg
= NULL
;
6016 int dst_unchanging_p
, dst_in_struct_p
, src_unchanging_p
, src_in_struct_p
;
6017 int dst_scalar_p
, src_scalar_p
;
6019 if (GET_CODE (operands
[2]) != CONST_INT
6020 || GET_CODE (operands
[3]) != CONST_INT
6021 || INTVAL (operands
[2]) > 64
6022 || INTVAL (operands
[3]) & 3)
6025 st_dst
= XEXP (operands
[0], 0);
6026 st_src
= XEXP (operands
[1], 0);
6028 dst_unchanging_p
= RTX_UNCHANGING_P (operands
[0]);
6029 dst_in_struct_p
= MEM_IN_STRUCT_P (operands
[0]);
6030 dst_scalar_p
= MEM_SCALAR_P (operands
[0]);
6031 src_unchanging_p
= RTX_UNCHANGING_P (operands
[1]);
6032 src_in_struct_p
= MEM_IN_STRUCT_P (operands
[1]);
6033 src_scalar_p
= MEM_SCALAR_P (operands
[1]);
6035 fin_dst
= dst
= copy_to_mode_reg (SImode
, st_dst
);
6036 fin_src
= src
= copy_to_mode_reg (SImode
, st_src
);
6038 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
6039 out_words_to_go
= INTVAL (operands
[2]) / 4;
6040 last_bytes
= INTVAL (operands
[2]) & 3;
6042 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
6043 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
6045 for (i
= 0; in_words_to_go
>= 2; i
+=4)
6047 if (in_words_to_go
> 4)
6048 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
6053 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
6054 FALSE
, src_unchanging_p
,
6055 src_in_struct_p
, src_scalar_p
));
6057 if (out_words_to_go
)
6059 if (out_words_to_go
> 4)
6060 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
6064 else if (out_words_to_go
!= 1)
6065 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
6074 mem
= gen_rtx_MEM (SImode
, dst
);
6075 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
6076 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6077 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6078 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
6079 if (last_bytes
!= 0)
6080 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
6084 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
6085 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
6088 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6089 if (out_words_to_go
)
6093 mem
= gen_rtx_MEM (SImode
, src
);
6094 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
6095 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
6096 MEM_SCALAR_P (mem
) = src_scalar_p
;
6097 emit_move_insn (sreg
= gen_reg_rtx (SImode
), mem
);
6098 emit_move_insn (fin_src
= gen_reg_rtx (SImode
), plus_constant (src
, 4));
6100 mem
= gen_rtx_MEM (SImode
, dst
);
6101 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
6102 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6103 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6104 emit_move_insn (mem
, sreg
);
6105 emit_move_insn (fin_dst
= gen_reg_rtx (SImode
), plus_constant (dst
, 4));
6108 if (in_words_to_go
) /* Sanity check */
6114 if (in_words_to_go
< 0)
6117 mem
= gen_rtx_MEM (SImode
, src
);
6118 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
6119 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
6120 MEM_SCALAR_P (mem
) = src_scalar_p
;
6121 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
6124 if (last_bytes
&& part_bytes_reg
== NULL
)
6127 if (BYTES_BIG_ENDIAN
&& last_bytes
)
6129 rtx tmp
= gen_reg_rtx (SImode
);
6131 /* The bytes we want are in the top end of the word. */
6132 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
6133 GEN_INT (8 * (4 - last_bytes
))));
6134 part_bytes_reg
= tmp
;
6138 mem
= gen_rtx_MEM (QImode
, plus_constant (dst
, last_bytes
- 1));
6139 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
6140 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6141 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6142 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6146 tmp
= gen_reg_rtx (SImode
);
6147 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
6148 part_bytes_reg
= tmp
;
6157 mem
= gen_rtx_MEM (HImode
, dst
);
6158 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
6159 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6160 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6161 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
6165 rtx tmp
= gen_reg_rtx (SImode
);
6167 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
6168 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
6169 part_bytes_reg
= tmp
;
6175 mem
= gen_rtx_MEM (QImode
, dst
);
6176 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
6177 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
6178 MEM_SCALAR_P (mem
) = dst_scalar_p
;
6179 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
6186 /* Generate a memory reference for a half word, such that it will be loaded
6187 into the top 16 bits of the word. We can assume that the address is
6188 known to be alignable and of the form reg, or plus (reg, const). */
6191 arm_gen_rotated_half_load (rtx memref
)
6193 HOST_WIDE_INT offset
= 0;
6194 rtx base
= XEXP (memref
, 0);
6196 if (GET_CODE (base
) == PLUS
)
6198 offset
= INTVAL (XEXP (base
, 1));
6199 base
= XEXP (base
, 0);
6202 /* If we aren't allowed to generate unaligned addresses, then fail. */
6203 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 0))
6206 base
= gen_rtx_MEM (SImode
, plus_constant (base
, offset
& ~2));
6208 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 2))
6211 return gen_rtx_ROTATE (SImode
, base
, GEN_INT (16));
6214 /* Select a dominance comparison mode if possible for a test of the general
6215 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6216 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6217 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6218 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6219 In all cases OP will be either EQ or NE, but we don't need to know which
6220 here. If we are unable to support a dominance comparison we return
6221 CC mode. This will then fail to match for the RTL expressions that
6222 generate this call. */
6224 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
6226 enum rtx_code cond1
, cond2
;
6229 /* Currently we will probably get the wrong result if the individual
6230 comparisons are not simple. This also ensures that it is safe to
6231 reverse a comparison if necessary. */
6232 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
6234 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
6238 /* The if_then_else variant of this tests the second condition if the
6239 first passes, but is true if the first fails. Reverse the first
6240 condition to get a true "inclusive-or" expression. */
6241 if (cond_or
== DOM_CC_NX_OR_Y
)
6242 cond1
= reverse_condition (cond1
);
6244 /* If the comparisons are not equal, and one doesn't dominate the other,
6245 then we can't do this. */
6247 && !comparison_dominates_p (cond1
, cond2
)
6248 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
6253 enum rtx_code temp
= cond1
;
6261 if (cond2
== EQ
|| cond_or
== DOM_CC_X_AND_Y
)
6266 case LE
: return CC_DLEmode
;
6267 case LEU
: return CC_DLEUmode
;
6268 case GE
: return CC_DGEmode
;
6269 case GEU
: return CC_DGEUmode
;
6276 if (cond2
== LT
|| cond_or
== DOM_CC_X_AND_Y
)
6285 if (cond2
== GT
|| cond_or
== DOM_CC_X_AND_Y
)
6294 if (cond2
== LTU
|| cond_or
== DOM_CC_X_AND_Y
)
6303 if (cond2
== GTU
|| cond_or
== DOM_CC_X_AND_Y
)
6311 /* The remaining cases only occur when both comparisons are the
6336 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
6338 /* All floating point compares return CCFP if it is an equality
6339 comparison, and CCFPE otherwise. */
6340 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6360 if (TARGET_HARD_FLOAT
&& TARGET_MAVERICK
)
6369 /* A compare with a shifted operand. Because of canonicalization, the
6370 comparison will have to be swapped when we emit the assembler. */
6371 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
6372 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6373 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
6374 || GET_CODE (x
) == ROTATERT
))
6377 /* This is a special case that is used by combine to allow a
6378 comparison of a shifted byte load to be split into a zero-extend
6379 followed by a comparison of the shifted integer (only valid for
6380 equalities and unsigned inequalities). */
6381 if (GET_MODE (x
) == SImode
6382 && GET_CODE (x
) == ASHIFT
6383 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
6384 && GET_CODE (XEXP (x
, 0)) == SUBREG
6385 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
6386 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
6387 && (op
== EQ
|| op
== NE
6388 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
6389 && GET_CODE (y
) == CONST_INT
)
6392 /* A construct for a conditional compare, if the false arm contains
6393 0, then both conditions must be true, otherwise either condition
6394 must be true. Not all conditions are possible, so CCmode is
6395 returned if it can't be done. */
6396 if (GET_CODE (x
) == IF_THEN_ELSE
6397 && (XEXP (x
, 2) == const0_rtx
6398 || XEXP (x
, 2) == const1_rtx
)
6399 && COMPARISON_P (XEXP (x
, 0))
6400 && COMPARISON_P (XEXP (x
, 1)))
6401 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6402 INTVAL (XEXP (x
, 2)));
6404 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6405 if (GET_CODE (x
) == AND
6406 && COMPARISON_P (XEXP (x
, 0))
6407 && COMPARISON_P (XEXP (x
, 1)))
6408 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6411 if (GET_CODE (x
) == IOR
6412 && COMPARISON_P (XEXP (x
, 0))
6413 && COMPARISON_P (XEXP (x
, 1)))
6414 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
6417 /* An operation (on Thumb) where we want to test for a single bit.
6418 This is done by shifting that bit up into the top bit of a
6419 scratch register; we can then branch on the sign bit. */
6421 && GET_MODE (x
) == SImode
6422 && (op
== EQ
|| op
== NE
)
6423 && (GET_CODE (x
) == ZERO_EXTRACT
))
6426 /* An operation that sets the condition codes as a side-effect, the
6427 V flag is not set correctly, so we can only use comparisons where
6428 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6430 if (GET_MODE (x
) == SImode
6432 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
6433 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
6434 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
6435 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
6436 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
6437 || GET_CODE (x
) == LSHIFTRT
6438 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
6439 || GET_CODE (x
) == ROTATERT
6440 || (TARGET_ARM
&& GET_CODE (x
) == ZERO_EXTRACT
)))
6443 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
6446 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
6447 && GET_CODE (x
) == PLUS
6448 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
6454 /* X and Y are two things to compare using CODE. Emit the compare insn and
6455 return the rtx for register 0 in the proper mode. FP means this is a
6456 floating point compare: I don't think that it is needed on the arm. */
6458 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
6460 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
6461 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
6463 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
6464 gen_rtx_COMPARE (mode
, x
, y
)));
6469 /* Generate a sequence of insns that will generate the correct return
6470 address mask depending on the physical architecture that the program
6473 arm_gen_return_addr_mask (void)
6475 rtx reg
= gen_reg_rtx (Pmode
);
6477 emit_insn (gen_return_addr_mask (reg
));
6482 arm_reload_in_hi (rtx
*operands
)
6484 rtx ref
= operands
[1];
6486 HOST_WIDE_INT offset
= 0;
6488 if (GET_CODE (ref
) == SUBREG
)
6490 offset
= SUBREG_BYTE (ref
);
6491 ref
= SUBREG_REG (ref
);
6494 if (GET_CODE (ref
) == REG
)
6496 /* We have a pseudo which has been spilt onto the stack; there
6497 are two cases here: the first where there is a simple
6498 stack-slot replacement and a second where the stack-slot is
6499 out of range, or is used as a subreg. */
6500 if (reg_equiv_mem
[REGNO (ref
)])
6502 ref
= reg_equiv_mem
[REGNO (ref
)];
6503 base
= find_replacement (&XEXP (ref
, 0));
6506 /* The slot is out of range, or was dressed up in a SUBREG. */
6507 base
= reg_equiv_address
[REGNO (ref
)];
6510 base
= find_replacement (&XEXP (ref
, 0));
6512 /* Handle the case where the address is too complex to be offset by 1. */
6513 if (GET_CODE (base
) == MINUS
6514 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6516 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6518 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6521 else if (GET_CODE (base
) == PLUS
)
6523 /* The addend must be CONST_INT, or we would have dealt with it above. */
6524 HOST_WIDE_INT hi
, lo
;
6526 offset
+= INTVAL (XEXP (base
, 1));
6527 base
= XEXP (base
, 0);
6529 /* Rework the address into a legal sequence of insns. */
6530 /* Valid range for lo is -4095 -> 4095 */
6533 : -((-offset
) & 0xfff));
6535 /* Corner case, if lo is the max offset then we would be out of range
6536 once we have added the additional 1 below, so bump the msb into the
6537 pre-loading insn(s). */
6541 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6542 ^ (HOST_WIDE_INT
) 0x80000000)
6543 - (HOST_WIDE_INT
) 0x80000000);
6545 if (hi
+ lo
!= offset
)
6550 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6552 /* Get the base address; addsi3 knows how to handle constants
6553 that require more than one insn. */
6554 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6560 /* Operands[2] may overlap operands[0] (though it won't overlap
6561 operands[1]), that's why we asked for a DImode reg -- so we can
6562 use the bit that does not overlap. */
6563 if (REGNO (operands
[2]) == REGNO (operands
[0]))
6564 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6566 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6568 emit_insn (gen_zero_extendqisi2 (scratch
,
6569 gen_rtx_MEM (QImode
,
6570 plus_constant (base
,
6572 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
6573 gen_rtx_MEM (QImode
,
6574 plus_constant (base
,
6576 if (!BYTES_BIG_ENDIAN
)
6577 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6578 gen_rtx_IOR (SImode
,
6581 gen_rtx_SUBREG (SImode
, operands
[0], 0),
6585 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
6586 gen_rtx_IOR (SImode
,
6587 gen_rtx_ASHIFT (SImode
, scratch
,
6589 gen_rtx_SUBREG (SImode
, operands
[0],
6593 /* Handle storing a half-word to memory during reload by synthesizing as two
6594 byte stores. Take care not to clobber the input values until after we
6595 have moved them somewhere safe. This code assumes that if the DImode
6596 scratch in operands[2] overlaps either the input value or output address
6597 in some way, then that value must die in this insn (we absolutely need
6598 two scratch registers for some corner cases). */
6600 arm_reload_out_hi (rtx
*operands
)
6602 rtx ref
= operands
[0];
6603 rtx outval
= operands
[1];
6605 HOST_WIDE_INT offset
= 0;
6607 if (GET_CODE (ref
) == SUBREG
)
6609 offset
= SUBREG_BYTE (ref
);
6610 ref
= SUBREG_REG (ref
);
6613 if (GET_CODE (ref
) == REG
)
6615 /* We have a pseudo which has been spilt onto the stack; there
6616 are two cases here: the first where there is a simple
6617 stack-slot replacement and a second where the stack-slot is
6618 out of range, or is used as a subreg. */
6619 if (reg_equiv_mem
[REGNO (ref
)])
6621 ref
= reg_equiv_mem
[REGNO (ref
)];
6622 base
= find_replacement (&XEXP (ref
, 0));
6625 /* The slot is out of range, or was dressed up in a SUBREG. */
6626 base
= reg_equiv_address
[REGNO (ref
)];
6629 base
= find_replacement (&XEXP (ref
, 0));
6631 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
6633 /* Handle the case where the address is too complex to be offset by 1. */
6634 if (GET_CODE (base
) == MINUS
6635 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
6637 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6639 /* Be careful not to destroy OUTVAL. */
6640 if (reg_overlap_mentioned_p (base_plus
, outval
))
6642 /* Updating base_plus might destroy outval, see if we can
6643 swap the scratch and base_plus. */
6644 if (!reg_overlap_mentioned_p (scratch
, outval
))
6647 scratch
= base_plus
;
6652 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6654 /* Be conservative and copy OUTVAL into the scratch now,
6655 this should only be necessary if outval is a subreg
6656 of something larger than a word. */
6657 /* XXX Might this clobber base? I can't see how it can,
6658 since scratch is known to overlap with OUTVAL, and
6659 must be wider than a word. */
6660 emit_insn (gen_movhi (scratch_hi
, outval
));
6661 outval
= scratch_hi
;
6665 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
6668 else if (GET_CODE (base
) == PLUS
)
6670 /* The addend must be CONST_INT, or we would have dealt with it above. */
6671 HOST_WIDE_INT hi
, lo
;
6673 offset
+= INTVAL (XEXP (base
, 1));
6674 base
= XEXP (base
, 0);
6676 /* Rework the address into a legal sequence of insns. */
6677 /* Valid range for lo is -4095 -> 4095 */
6680 : -((-offset
) & 0xfff));
6682 /* Corner case, if lo is the max offset then we would be out of range
6683 once we have added the additional 1 below, so bump the msb into the
6684 pre-loading insn(s). */
6688 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
6689 ^ (HOST_WIDE_INT
) 0x80000000)
6690 - (HOST_WIDE_INT
) 0x80000000);
6692 if (hi
+ lo
!= offset
)
6697 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
6699 /* Be careful not to destroy OUTVAL. */
6700 if (reg_overlap_mentioned_p (base_plus
, outval
))
6702 /* Updating base_plus might destroy outval, see if we
6703 can swap the scratch and base_plus. */
6704 if (!reg_overlap_mentioned_p (scratch
, outval
))
6707 scratch
= base_plus
;
6712 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
6714 /* Be conservative and copy outval into scratch now,
6715 this should only be necessary if outval is a
6716 subreg of something larger than a word. */
6717 /* XXX Might this clobber base? I can't see how it
6718 can, since scratch is known to overlap with
6720 emit_insn (gen_movhi (scratch_hi
, outval
));
6721 outval
= scratch_hi
;
6725 /* Get the base address; addsi3 knows how to handle constants
6726 that require more than one insn. */
6727 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6733 if (BYTES_BIG_ENDIAN
)
6735 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6736 plus_constant (base
, offset
+ 1)),
6737 gen_lowpart (QImode
, outval
)));
6738 emit_insn (gen_lshrsi3 (scratch
,
6739 gen_rtx_SUBREG (SImode
, outval
, 0),
6741 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6742 gen_lowpart (QImode
, scratch
)));
6746 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6747 gen_lowpart (QImode
, outval
)));
6748 emit_insn (gen_lshrsi3 (scratch
,
6749 gen_rtx_SUBREG (SImode
, outval
, 0),
6751 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6752 plus_constant (base
, offset
+ 1)),
6753 gen_lowpart (QImode
, scratch
)));
6757 /* Print a symbolic form of X to the debug file, F. */
6759 arm_print_value (FILE *f
, rtx x
)
6761 switch (GET_CODE (x
))
6764 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
6768 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
6776 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
6778 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
6779 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
6787 fprintf (f
, "\"%s\"", XSTR (x
, 0));
6791 fprintf (f
, "`%s'", XSTR (x
, 0));
6795 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
6799 arm_print_value (f
, XEXP (x
, 0));
6803 arm_print_value (f
, XEXP (x
, 0));
6805 arm_print_value (f
, XEXP (x
, 1));
6813 fprintf (f
, "????");
6818 /* Routines for manipulation of the constant pool. */
6820 /* Arm instructions cannot load a large constant directly into a
6821 register; they have to come from a pc relative load. The constant
6822 must therefore be placed in the addressable range of the pc
6823 relative load. Depending on the precise pc relative load
6824 instruction the range is somewhere between 256 bytes and 4k. This
6825 means that we often have to dump a constant inside a function, and
6826 generate code to branch around it.
6828 It is important to minimize this, since the branches will slow
6829 things down and make the code larger.
6831 Normally we can hide the table after an existing unconditional
6832 branch so that there is no interruption of the flow, but in the
6833 worst case the code looks like this:
6851 We fix this by performing a scan after scheduling, which notices
6852 which instructions need to have their operands fetched from the
6853 constant table and builds the table.
6855 The algorithm starts by building a table of all the constants that
6856 need fixing up and all the natural barriers in the function (places
6857 where a constant table can be dropped without breaking the flow).
6858 For each fixup we note how far the pc-relative replacement will be
6859 able to reach and the offset of the instruction into the function.
6861 Having built the table we then group the fixes together to form
6862 tables that are as large as possible (subject to addressing
6863 constraints) and emit each table of constants after the last
6864 barrier that is within range of all the instructions in the group.
6865 If a group does not contain a barrier, then we forcibly create one
6866 by inserting a jump instruction into the flow. Once the table has
6867 been inserted, the insns are then modified to reference the
6868 relevant entry in the pool.
6870 Possible enhancements to the algorithm (not implemented) are:
6872 1) For some processors and object formats, there may be benefit in
6873 aligning the pools to the start of cache lines; this alignment
6874 would need to be taken into account when calculating addressability
6877 /* These typedefs are located at the start of this file, so that
6878 they can be used in the prototypes there. This comment is to
6879 remind readers of that fact so that the following structures
6880 can be understood more easily.
6882 typedef struct minipool_node Mnode;
6883 typedef struct minipool_fixup Mfix; */
6885 struct minipool_node
6887 /* Doubly linked chain of entries. */
6890 /* The maximum offset into the code that this entry can be placed. While
6891 pushing fixes for forward references, all entries are sorted in order
6892 of increasing max_address. */
6893 HOST_WIDE_INT max_address
;
6894 /* Similarly for an entry inserted for a backwards ref. */
6895 HOST_WIDE_INT min_address
;
6896 /* The number of fixes referencing this entry. This can become zero
6897 if we "unpush" an entry. In this case we ignore the entry when we
6898 come to emit the code. */
6900 /* The offset from the start of the minipool. */
6901 HOST_WIDE_INT offset
;
6902 /* The value in table. */
6904 /* The mode of value. */
6905 enum machine_mode mode
;
6906 /* The size of the value. With iWMMXt enabled
6907 sizes > 4 also imply an alignment of 8-bytes. */
6911 struct minipool_fixup
6915 HOST_WIDE_INT address
;
6917 enum machine_mode mode
;
6921 HOST_WIDE_INT forwards
;
6922 HOST_WIDE_INT backwards
;
6925 /* Fixes less than a word need padding out to a word boundary. */
6926 #define MINIPOOL_FIX_SIZE(mode) \
6927 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6929 static Mnode
* minipool_vector_head
;
6930 static Mnode
* minipool_vector_tail
;
6931 static rtx minipool_vector_label
;
6933 /* The linked list of all minipool fixes required for this function. */
6934 Mfix
* minipool_fix_head
;
6935 Mfix
* minipool_fix_tail
;
6936 /* The fix entry for the current minipool, once it has been placed. */
6937 Mfix
* minipool_barrier
;
6939 /* Determines if INSN is the start of a jump table. Returns the end
6940 of the TABLE or NULL_RTX. */
6942 is_jump_table (rtx insn
)
6946 if (GET_CODE (insn
) == JUMP_INSN
6947 && JUMP_LABEL (insn
) != NULL
6948 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
6949 == next_real_insn (insn
))
6951 && GET_CODE (table
) == JUMP_INSN
6952 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
6953 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
6959 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6960 #define JUMP_TABLES_IN_TEXT_SECTION 0
6963 static HOST_WIDE_INT
6964 get_jump_table_size (rtx insn
)
6966 /* ADDR_VECs only take room if read-only data does into the text
6968 if (JUMP_TABLES_IN_TEXT_SECTION
6969 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6974 rtx body
= PATTERN (insn
);
6975 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
6977 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
6983 /* Move a minipool fix MP from its current location to before MAX_MP.
6984 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6985 constraints may need updating. */
6987 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
6988 HOST_WIDE_INT max_address
)
6990 /* This should never be true and the code below assumes these are
6997 if (max_address
< mp
->max_address
)
6998 mp
->max_address
= max_address
;
7002 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7003 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7005 mp
->max_address
= max_address
;
7007 /* Unlink MP from its current position. Since max_mp is non-null,
7008 mp->prev must be non-null. */
7009 mp
->prev
->next
= mp
->next
;
7010 if (mp
->next
!= NULL
)
7011 mp
->next
->prev
= mp
->prev
;
7013 minipool_vector_tail
= mp
->prev
;
7015 /* Re-insert it before MAX_MP. */
7017 mp
->prev
= max_mp
->prev
;
7020 if (mp
->prev
!= NULL
)
7021 mp
->prev
->next
= mp
;
7023 minipool_vector_head
= mp
;
7026 /* Save the new entry. */
7029 /* Scan over the preceding entries and adjust their addresses as
7031 while (mp
->prev
!= NULL
7032 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7034 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7041 /* Add a constant to the minipool for a forward reference. Returns the
7042 node added or NULL if the constant will not fit in this pool. */
7044 add_minipool_forward_ref (Mfix
*fix
)
7046 /* If set, max_mp is the first pool_entry that has a lower
7047 constraint than the one we are trying to add. */
7048 Mnode
* max_mp
= NULL
;
7049 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
7052 /* If this fix's address is greater than the address of the first
7053 entry, then we can't put the fix in this pool. We subtract the
7054 size of the current fix to ensure that if the table is fully
7055 packed we still have enough room to insert this value by suffling
7056 the other fixes forwards. */
7057 if (minipool_vector_head
&&
7058 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
7061 /* Scan the pool to see if a constant with the same value has
7062 already been added. While we are doing this, also note the
7063 location where we must insert the constant if it doesn't already
7065 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7067 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7068 && fix
->mode
== mp
->mode
7069 && (GET_CODE (fix
->value
) != CODE_LABEL
7070 || (CODE_LABEL_NUMBER (fix
->value
)
7071 == CODE_LABEL_NUMBER (mp
->value
)))
7072 && rtx_equal_p (fix
->value
, mp
->value
))
7074 /* More than one fix references this entry. */
7076 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
7079 /* Note the insertion point if necessary. */
7081 && mp
->max_address
> max_address
)
7084 /* If we are inserting an 8-bytes aligned quantity and
7085 we have not already found an insertion point, then
7086 make sure that all such 8-byte aligned quantities are
7087 placed at the start of the pool. */
7088 if (ARM_DOUBLEWORD_ALIGN
7090 && fix
->fix_size
== 8
7091 && mp
->fix_size
!= 8)
7094 max_address
= mp
->max_address
;
7098 /* The value is not currently in the minipool, so we need to create
7099 a new entry for it. If MAX_MP is NULL, the entry will be put on
7100 the end of the list since the placement is less constrained than
7101 any existing entry. Otherwise, we insert the new fix before
7102 MAX_MP and, if necessary, adjust the constraints on the other
7104 mp
= xmalloc (sizeof (* mp
));
7105 mp
->fix_size
= fix
->fix_size
;
7106 mp
->mode
= fix
->mode
;
7107 mp
->value
= fix
->value
;
7109 /* Not yet required for a backwards ref. */
7110 mp
->min_address
= -65536;
7114 mp
->max_address
= max_address
;
7116 mp
->prev
= minipool_vector_tail
;
7118 if (mp
->prev
== NULL
)
7120 minipool_vector_head
= mp
;
7121 minipool_vector_label
= gen_label_rtx ();
7124 mp
->prev
->next
= mp
;
7126 minipool_vector_tail
= mp
;
7130 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
7131 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
7133 mp
->max_address
= max_address
;
7136 mp
->prev
= max_mp
->prev
;
7138 if (mp
->prev
!= NULL
)
7139 mp
->prev
->next
= mp
;
7141 minipool_vector_head
= mp
;
7144 /* Save the new entry. */
7147 /* Scan over the preceding entries and adjust their addresses as
7149 while (mp
->prev
!= NULL
7150 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
7152 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
7160 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
7161 HOST_WIDE_INT min_address
)
7163 HOST_WIDE_INT offset
;
7165 /* This should never be true, and the code below assumes these are
7172 if (min_address
> mp
->min_address
)
7173 mp
->min_address
= min_address
;
7177 /* We will adjust this below if it is too loose. */
7178 mp
->min_address
= min_address
;
7180 /* Unlink MP from its current position. Since min_mp is non-null,
7181 mp->next must be non-null. */
7182 mp
->next
->prev
= mp
->prev
;
7183 if (mp
->prev
!= NULL
)
7184 mp
->prev
->next
= mp
->next
;
7186 minipool_vector_head
= mp
->next
;
7188 /* Reinsert it after MIN_MP. */
7190 mp
->next
= min_mp
->next
;
7192 if (mp
->next
!= NULL
)
7193 mp
->next
->prev
= mp
;
7195 minipool_vector_tail
= mp
;
7201 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7203 mp
->offset
= offset
;
7204 if (mp
->refcount
> 0)
7205 offset
+= mp
->fix_size
;
7207 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7208 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7214 /* Add a constant to the minipool for a backward reference. Returns the
7215 node added or NULL if the constant will not fit in this pool.
7217 Note that the code for insertion for a backwards reference can be
7218 somewhat confusing because the calculated offsets for each fix do
7219 not take into account the size of the pool (which is still under
7222 add_minipool_backward_ref (Mfix
*fix
)
7224 /* If set, min_mp is the last pool_entry that has a lower constraint
7225 than the one we are trying to add. */
7226 Mnode
*min_mp
= NULL
;
7227 /* This can be negative, since it is only a constraint. */
7228 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
7231 /* If we can't reach the current pool from this insn, or if we can't
7232 insert this entry at the end of the pool without pushing other
7233 fixes out of range, then we don't try. This ensures that we
7234 can't fail later on. */
7235 if (min_address
>= minipool_barrier
->address
7236 || (minipool_vector_tail
->min_address
+ fix
->fix_size
7237 >= minipool_barrier
->address
))
7240 /* Scan the pool to see if a constant with the same value has
7241 already been added. While we are doing this, also note the
7242 location where we must insert the constant if it doesn't already
7244 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
7246 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
7247 && fix
->mode
== mp
->mode
7248 && (GET_CODE (fix
->value
) != CODE_LABEL
7249 || (CODE_LABEL_NUMBER (fix
->value
)
7250 == CODE_LABEL_NUMBER (mp
->value
)))
7251 && rtx_equal_p (fix
->value
, mp
->value
)
7252 /* Check that there is enough slack to move this entry to the
7253 end of the table (this is conservative). */
7255 > (minipool_barrier
->address
7256 + minipool_vector_tail
->offset
7257 + minipool_vector_tail
->fix_size
)))
7260 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
7264 mp
->min_address
+= fix
->fix_size
;
7267 /* Note the insertion point if necessary. */
7268 if (mp
->min_address
< min_address
)
7270 /* For now, we do not allow the insertion of 8-byte alignment
7271 requiring nodes anywhere but at the start of the pool. */
7272 if (ARM_DOUBLEWORD_ALIGN
7273 && fix
->fix_size
== 8 && mp
->fix_size
!= 8)
7278 else if (mp
->max_address
7279 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
7281 /* Inserting before this entry would push the fix beyond
7282 its maximum address (which can happen if we have
7283 re-located a forwards fix); force the new fix to come
7286 min_address
= mp
->min_address
+ fix
->fix_size
;
7288 /* If we are inserting an 8-bytes aligned quantity and
7289 we have not already found an insertion point, then
7290 make sure that all such 8-byte aligned quantities are
7291 placed at the start of the pool. */
7292 else if (ARM_DOUBLEWORD_ALIGN
7294 && fix
->fix_size
== 8
7295 && mp
->fix_size
< 8)
7298 min_address
= mp
->min_address
+ fix
->fix_size
;
7303 /* We need to create a new entry. */
7304 mp
= xmalloc (sizeof (* mp
));
7305 mp
->fix_size
= fix
->fix_size
;
7306 mp
->mode
= fix
->mode
;
7307 mp
->value
= fix
->value
;
7309 mp
->max_address
= minipool_barrier
->address
+ 65536;
7311 mp
->min_address
= min_address
;
7316 mp
->next
= minipool_vector_head
;
7318 if (mp
->next
== NULL
)
7320 minipool_vector_tail
= mp
;
7321 minipool_vector_label
= gen_label_rtx ();
7324 mp
->next
->prev
= mp
;
7326 minipool_vector_head
= mp
;
7330 mp
->next
= min_mp
->next
;
7334 if (mp
->next
!= NULL
)
7335 mp
->next
->prev
= mp
;
7337 minipool_vector_tail
= mp
;
7340 /* Save the new entry. */
7348 /* Scan over the following entries and adjust their offsets. */
7349 while (mp
->next
!= NULL
)
7351 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
7352 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
7355 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
7357 mp
->next
->offset
= mp
->offset
;
7366 assign_minipool_offsets (Mfix
*barrier
)
7368 HOST_WIDE_INT offset
= 0;
7371 minipool_barrier
= barrier
;
7373 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7375 mp
->offset
= offset
;
7377 if (mp
->refcount
> 0)
7378 offset
+= mp
->fix_size
;
7382 /* Output the literal table */
7384 dump_minipool (rtx scan
)
7390 if (ARM_DOUBLEWORD_ALIGN
)
7391 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
7392 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
7400 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7401 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
7403 scan
= emit_label_after (gen_label_rtx (), scan
);
7404 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
7405 scan
= emit_label_after (minipool_vector_label
, scan
);
7407 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
7409 if (mp
->refcount
> 0)
7414 ";; Offset %u, min %ld, max %ld ",
7415 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
7416 (unsigned long) mp
->max_address
);
7417 arm_print_value (dump_file
, mp
->value
);
7418 fputc ('\n', dump_file
);
7421 switch (mp
->fix_size
)
7423 #ifdef HAVE_consttable_1
7425 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
7429 #ifdef HAVE_consttable_2
7431 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
7435 #ifdef HAVE_consttable_4
7437 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
7441 #ifdef HAVE_consttable_8
7443 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
7457 minipool_vector_head
= minipool_vector_tail
= NULL
;
7458 scan
= emit_insn_after (gen_consttable_end (), scan
);
7459 scan
= emit_barrier_after (scan
);
7462 /* Return the cost of forcibly inserting a barrier after INSN. */
7464 arm_barrier_cost (rtx insn
)
7466 /* Basing the location of the pool on the loop depth is preferable,
7467 but at the moment, the basic block information seems to be
7468 corrupt by this stage of the compilation. */
7470 rtx next
= next_nonnote_insn (insn
);
7472 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
7475 switch (GET_CODE (insn
))
7478 /* It will always be better to place the table before the label, rather
7487 return base_cost
- 10;
7490 return base_cost
+ 10;
7494 /* Find the best place in the insn stream in the range
7495 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7496 Create the barrier by inserting a jump and add a new fix entry for
7499 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
7501 HOST_WIDE_INT count
= 0;
7503 rtx from
= fix
->insn
;
7504 rtx selected
= from
;
7506 HOST_WIDE_INT selected_address
;
7508 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
7509 rtx label
= gen_label_rtx ();
7511 selected_cost
= arm_barrier_cost (from
);
7512 selected_address
= fix
->address
;
7514 while (from
&& count
< max_count
)
7519 /* This code shouldn't have been called if there was a natural barrier
7521 if (GET_CODE (from
) == BARRIER
)
7524 /* Count the length of this insn. */
7525 count
+= get_attr_length (from
);
7527 /* If there is a jump table, add its length. */
7528 tmp
= is_jump_table (from
);
7531 count
+= get_jump_table_size (tmp
);
7533 /* Jump tables aren't in a basic block, so base the cost on
7534 the dispatch insn. If we select this location, we will
7535 still put the pool after the table. */
7536 new_cost
= arm_barrier_cost (from
);
7538 if (count
< max_count
&& new_cost
<= selected_cost
)
7541 selected_cost
= new_cost
;
7542 selected_address
= fix
->address
+ count
;
7545 /* Continue after the dispatch table. */
7546 from
= NEXT_INSN (tmp
);
7550 new_cost
= arm_barrier_cost (from
);
7552 if (count
< max_count
&& new_cost
<= selected_cost
)
7555 selected_cost
= new_cost
;
7556 selected_address
= fix
->address
+ count
;
7559 from
= NEXT_INSN (from
);
7562 /* Create a new JUMP_INSN that branches around a barrier. */
7563 from
= emit_jump_insn_after (gen_jump (label
), selected
);
7564 JUMP_LABEL (from
) = label
;
7565 barrier
= emit_barrier_after (from
);
7566 emit_label_after (label
, barrier
);
7568 /* Create a minipool barrier entry for the new barrier. */
7569 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
7570 new_fix
->insn
= barrier
;
7571 new_fix
->address
= selected_address
;
7572 new_fix
->next
= fix
->next
;
7573 fix
->next
= new_fix
;
7578 /* Record that there is a natural barrier in the insn stream at
7581 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
7583 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7586 fix
->address
= address
;
7589 if (minipool_fix_head
!= NULL
)
7590 minipool_fix_tail
->next
= fix
;
7592 minipool_fix_head
= fix
;
7594 minipool_fix_tail
= fix
;
7597 /* Record INSN, which will need fixing up to load a value from the
7598 minipool. ADDRESS is the offset of the insn since the start of the
7599 function; LOC is a pointer to the part of the insn which requires
7600 fixing; VALUE is the constant that must be loaded, which is of type
7603 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
7604 enum machine_mode mode
, rtx value
)
7606 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
7608 #ifdef AOF_ASSEMBLER
7609 /* PIC symbol references need to be converted into offsets into the
7611 /* XXX This shouldn't be done here. */
7612 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
7613 value
= aof_pic_entry (value
);
7614 #endif /* AOF_ASSEMBLER */
7617 fix
->address
= address
;
7620 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
7622 fix
->forwards
= get_attr_pool_range (insn
);
7623 fix
->backwards
= get_attr_neg_pool_range (insn
);
7624 fix
->minipool
= NULL
;
7626 /* If an insn doesn't have a range defined for it, then it isn't
7627 expecting to be reworked by this code. Better to abort now than
7628 to generate duff assembly code. */
7629 if (fix
->forwards
== 0 && fix
->backwards
== 0)
7632 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7633 So there might be an empty word before the start of the pool.
7634 Hence we reduce the forward range by 4 to allow for this
7636 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
== 8)
7642 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7643 GET_MODE_NAME (mode
),
7644 INSN_UID (insn
), (unsigned long) address
,
7645 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
7646 arm_print_value (dump_file
, fix
->value
);
7647 fprintf (dump_file
, "\n");
7650 /* Add it to the chain of fixes. */
7653 if (minipool_fix_head
!= NULL
)
7654 minipool_fix_tail
->next
= fix
;
7656 minipool_fix_head
= fix
;
7658 minipool_fix_tail
= fix
;
7661 /* Scan INSN and note any of its operands that need fixing.
7662 If DO_PUSHES is false we do not actually push any of the fixups
7663 needed. The function returns TRUE is any fixups were needed/pushed.
7664 This is used by arm_memory_load_p() which needs to know about loads
7665 of constants that will be converted into minipool loads. */
7667 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
7669 bool result
= false;
7672 extract_insn (insn
);
7674 if (!constrain_operands (1))
7675 fatal_insn_not_found (insn
);
7677 if (recog_data
.n_alternatives
== 0)
7680 /* Fill in recog_op_alt with information about the constraints of this insn. */
7681 preprocess_constraints ();
7683 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
7685 /* Things we need to fix can only occur in inputs. */
7686 if (recog_data
.operand_type
[opno
] != OP_IN
)
7689 /* If this alternative is a memory reference, then any mention
7690 of constants in this alternative is really to fool reload
7691 into allowing us to accept one there. We need to fix them up
7692 now so that we output the right code. */
7693 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
7695 rtx op
= recog_data
.operand
[opno
];
7697 if (CONSTANT_P (op
))
7700 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
7701 recog_data
.operand_mode
[opno
], op
);
7704 else if (GET_CODE (op
) == MEM
7705 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
7706 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
7710 rtx cop
= avoid_constant_pool_reference (op
);
7712 /* Casting the address of something to a mode narrower
7713 than a word can cause avoid_constant_pool_reference()
7714 to return the pool reference itself. That's no good to
7715 us here. Lets just hope that we can use the
7716 constant pool value directly. */
7718 cop
= get_pool_constant (XEXP (op
, 0));
7720 push_minipool_fix (insn
, address
,
7721 recog_data
.operand_loc
[opno
],
7722 recog_data
.operand_mode
[opno
], cop
);
7733 /* Gcc puts the pool in the wrong place for ARM, since we can only
7734 load addresses a limited distance around the pc. We do some
7735 special munging to move the constant pool values to the correct
7736 point in the code. */
7741 HOST_WIDE_INT address
= 0;
7744 minipool_fix_head
= minipool_fix_tail
= NULL
;
7746 /* The first insn must always be a note, or the code below won't
7747 scan it properly. */
7748 insn
= get_insns ();
7749 if (GET_CODE (insn
) != NOTE
)
7752 /* Scan all the insns and record the operands that will need fixing. */
7753 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
7755 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7756 && (arm_cirrus_insn_p (insn
)
7757 || GET_CODE (insn
) == JUMP_INSN
7758 || arm_memory_load_p (insn
)))
7759 cirrus_reorg (insn
);
7761 if (GET_CODE (insn
) == BARRIER
)
7762 push_minipool_barrier (insn
, address
);
7763 else if (INSN_P (insn
))
7767 note_invalid_constants (insn
, address
, true);
7768 address
+= get_attr_length (insn
);
7770 /* If the insn is a vector jump, add the size of the table
7771 and skip the table. */
7772 if ((table
= is_jump_table (insn
)) != NULL
)
7774 address
+= get_jump_table_size (table
);
7780 fix
= minipool_fix_head
;
7782 /* Now scan the fixups and perform the required changes. */
7787 Mfix
* last_added_fix
;
7788 Mfix
* last_barrier
= NULL
;
7791 /* Skip any further barriers before the next fix. */
7792 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
7795 /* No more fixes. */
7799 last_added_fix
= NULL
;
7801 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
7803 if (GET_CODE (ftmp
->insn
) == BARRIER
)
7805 if (ftmp
->address
>= minipool_vector_head
->max_address
)
7808 last_barrier
= ftmp
;
7810 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
7813 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
7816 /* If we found a barrier, drop back to that; any fixes that we
7817 could have reached but come after the barrier will now go in
7818 the next mini-pool. */
7819 if (last_barrier
!= NULL
)
7821 /* Reduce the refcount for those fixes that won't go into this
7823 for (fdel
= last_barrier
->next
;
7824 fdel
&& fdel
!= ftmp
;
7827 fdel
->minipool
->refcount
--;
7828 fdel
->minipool
= NULL
;
7831 ftmp
= last_barrier
;
7835 /* ftmp is first fix that we can't fit into this pool and
7836 there no natural barriers that we could use. Insert a
7837 new barrier in the code somewhere between the previous
7838 fix and this one, and arrange to jump around it. */
7839 HOST_WIDE_INT max_address
;
7841 /* The last item on the list of fixes must be a barrier, so
7842 we can never run off the end of the list of fixes without
7843 last_barrier being set. */
7847 max_address
= minipool_vector_head
->max_address
;
7848 /* Check that there isn't another fix that is in range that
7849 we couldn't fit into this pool because the pool was
7850 already too large: we need to put the pool before such an
7852 if (ftmp
->address
< max_address
)
7853 max_address
= ftmp
->address
;
7855 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
7858 assign_minipool_offsets (last_barrier
);
7862 if (GET_CODE (ftmp
->insn
) != BARRIER
7863 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
7870 /* Scan over the fixes we have identified for this pool, fixing them
7871 up and adding the constants to the pool itself. */
7872 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
7873 this_fix
= this_fix
->next
)
7874 if (GET_CODE (this_fix
->insn
) != BARRIER
)
7877 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
7878 minipool_vector_label
),
7879 this_fix
->minipool
->offset
);
7880 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
7883 dump_minipool (last_barrier
->insn
);
7887 /* From now on we must synthesize any constants that we can't handle
7888 directly. This can happen if the RTL gets split during final
7889 instruction generation. */
7890 after_arm_reorg
= 1;
7892 /* Free the minipool memory. */
7893 obstack_free (&minipool_obstack
, minipool_startobj
);
7896 /* Routines to output assembly language. */
7898 /* If the rtx is the correct value then return the string of the number.
7899 In this way we can ensure that valid double constants are generated even
7900 when cross compiling. */
7902 fp_immediate_constant (rtx x
)
7907 if (!fp_consts_inited
)
7910 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
7911 for (i
= 0; i
< 8; i
++)
7912 if (REAL_VALUES_EQUAL (r
, values_fp
[i
]))
7913 return strings_fp
[i
];
7918 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7920 fp_const_from_val (REAL_VALUE_TYPE
*r
)
7924 if (!fp_consts_inited
)
7927 for (i
= 0; i
< 8; i
++)
7928 if (REAL_VALUES_EQUAL (*r
, values_fp
[i
]))
7929 return strings_fp
[i
];
7934 /* Output the operands of a LDM/STM instruction to STREAM.
7935 MASK is the ARM register set mask of which only bits 0-15 are important.
7936 REG is the base register, either the frame pointer or the stack pointer,
7937 INSTR is the possibly suffixed load or store instruction. */
7939 print_multi_reg (FILE *stream
, const char *instr
, int reg
, int mask
)
7942 int not_first
= FALSE
;
7944 fputc ('\t', stream
);
7945 asm_fprintf (stream
, instr
, reg
);
7946 fputs (", {", stream
);
7948 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7949 if (mask
& (1 << i
))
7952 fprintf (stream
, ", ");
7954 asm_fprintf (stream
, "%r", i
);
7958 fprintf (stream
, "}\n");
7962 /* Output a FLDMX instruction to STREAM.
7963 BASE if the register containing the address.
7964 REG and COUNT specify the register range.
7965 Extra registers may be added to avoid hardware bugs. */
7968 arm_output_fldmx (FILE * stream
, unsigned int base
, int reg
, int count
)
7972 /* Workaround ARM10 VFPr1 bug. */
7973 if (count
== 2 && !arm_arch6
)
7980 fputc ('\t', stream
);
7981 asm_fprintf (stream
, "fldmfdx\t%r!, {", base
);
7983 for (i
= reg
; i
< reg
+ count
; i
++)
7986 fputs (", ", stream
);
7987 asm_fprintf (stream
, "d%d", i
);
7989 fputs ("}\n", stream
);
7994 /* Output the assembly for a store multiple. */
7997 vfp_output_fstmx (rtx
* operands
)
8004 strcpy (pattern
, "fstmfdx\t%m0!, {%P1");
8005 p
= strlen (pattern
);
8007 if (GET_CODE (operands
[1]) != REG
)
8010 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
8011 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
8013 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
8015 strcpy (&pattern
[p
], "}");
8017 output_asm_insn (pattern
, operands
);
8022 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8023 number of bytes pushed. */
8026 vfp_emit_fstmx (int base_reg
, int count
)
8033 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8034 register pairs are stored by a store multiple insn. We avoid this
8035 by pushing an extra pair. */
8036 if (count
== 2 && !arm_arch6
)
8038 if (base_reg
== LAST_VFP_REGNUM
- 3)
8043 /* ??? The frame layout is implementation defined. We describe
8044 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8045 We really need some way of representing the whole block so that the
8046 unwinder can figure it out at runtime. */
8047 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8048 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
8050 reg
= gen_rtx_REG (DFmode
, base_reg
);
8054 = gen_rtx_SET (VOIDmode
,
8055 gen_rtx_MEM (BLKmode
,
8056 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
8057 gen_rtx_UNSPEC (BLKmode
,
8061 tmp
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8062 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
8063 GEN_INT (-(count
* 8 + 4))));
8064 RTX_FRAME_RELATED_P (tmp
) = 1;
8065 XVECEXP (dwarf
, 0, 0) = tmp
;
8067 tmp
= gen_rtx_SET (VOIDmode
,
8068 gen_rtx_MEM (DFmode
, stack_pointer_rtx
),
8070 RTX_FRAME_RELATED_P (tmp
) = 1;
8071 XVECEXP (dwarf
, 0, 1) = tmp
;
8073 for (i
= 1; i
< count
; i
++)
8075 reg
= gen_rtx_REG (DFmode
, base_reg
);
8077 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8079 tmp
= gen_rtx_SET (VOIDmode
,
8080 gen_rtx_MEM (DFmode
,
8081 gen_rtx_PLUS (SImode
,
8085 RTX_FRAME_RELATED_P (tmp
) = 1;
8086 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
8089 par
= emit_insn (par
);
8090 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8092 RTX_FRAME_RELATED_P (par
) = 1;
8094 return count
* 8 + 4;
8098 /* Output a 'call' insn. */
8100 output_call (rtx
*operands
)
8103 abort (); /* Patterns should call blx <reg> directly. */
8105 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8106 if (REGNO (operands
[0]) == LR_REGNUM
)
8108 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
8109 output_asm_insn ("mov%?\t%0, %|lr", operands
);
8112 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8114 if (TARGET_INTERWORK
|| arm_arch4t
)
8115 output_asm_insn ("bx%?\t%0", operands
);
8117 output_asm_insn ("mov%?\t%|pc, %0", operands
);
8122 /* Output a 'call' insn that is a reference in memory. */
8124 output_call_mem (rtx
*operands
)
8126 if (TARGET_INTERWORK
&& !arm_arch5
)
8128 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8129 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8130 output_asm_insn ("bx%?\t%|ip", operands
);
8132 else if (regno_use_in (LR_REGNUM
, operands
[0]))
8134 /* LR is used in the memory address. We load the address in the
8135 first instruction. It's safe to use IP as the target of the
8136 load since the call will kill it anyway. */
8137 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
8139 output_asm_insn ("blx%?%|ip", operands
);
8142 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8144 output_asm_insn ("bx%?\t%|ip", operands
);
8146 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
8151 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
8152 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
8159 /* Output a move from arm registers to an fpa registers.
8160 OPERANDS[0] is an fpa register.
8161 OPERANDS[1] is the first registers of an arm register pair. */
8163 output_mov_long_double_fpa_from_arm (rtx
*operands
)
8165 int arm_reg0
= REGNO (operands
[1]);
8168 if (arm_reg0
== IP_REGNUM
)
8171 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8172 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8173 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8175 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8176 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
8181 /* Output a move from an fpa register to arm registers.
8182 OPERANDS[0] is the first registers of an arm register pair.
8183 OPERANDS[1] is an fpa register. */
8185 output_mov_long_double_arm_from_fpa (rtx
*operands
)
8187 int arm_reg0
= REGNO (operands
[0]);
8190 if (arm_reg0
== IP_REGNUM
)
8193 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8194 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8195 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
8197 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
8198 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
8202 /* Output a move from arm registers to arm registers of a long double
8203 OPERANDS[0] is the destination.
8204 OPERANDS[1] is the source. */
8206 output_mov_long_double_arm_from_arm (rtx
*operands
)
8208 /* We have to be careful here because the two might overlap. */
8209 int dest_start
= REGNO (operands
[0]);
8210 int src_start
= REGNO (operands
[1]);
8214 if (dest_start
< src_start
)
8216 for (i
= 0; i
< 3; i
++)
8218 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8219 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8220 output_asm_insn ("mov%?\t%0, %1", ops
);
8225 for (i
= 2; i
>= 0; i
--)
8227 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
8228 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
8229 output_asm_insn ("mov%?\t%0, %1", ops
);
8237 /* Output a move from arm registers to an fpa registers.
8238 OPERANDS[0] is an fpa register.
8239 OPERANDS[1] is the first registers of an arm register pair. */
8241 output_mov_double_fpa_from_arm (rtx
*operands
)
8243 int arm_reg0
= REGNO (operands
[1]);
8246 if (arm_reg0
== IP_REGNUM
)
8249 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8250 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8251 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
8252 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
8256 /* Output a move from an fpa register to arm registers.
8257 OPERANDS[0] is the first registers of an arm register pair.
8258 OPERANDS[1] is an fpa register. */
8260 output_mov_double_arm_from_fpa (rtx
*operands
)
8262 int arm_reg0
= REGNO (operands
[0]);
8265 if (arm_reg0
== IP_REGNUM
)
8268 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
8269 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
8270 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
8271 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
8275 /* Output a move between double words.
8276 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8277 or MEM<-REG and all MEMs must be offsettable addresses. */
8279 output_move_double (rtx
*operands
)
8281 enum rtx_code code0
= GET_CODE (operands
[0]);
8282 enum rtx_code code1
= GET_CODE (operands
[1]);
8287 int reg0
= REGNO (operands
[0]);
8289 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
8293 int reg1
= REGNO (operands
[1]);
8294 if (reg1
== IP_REGNUM
)
8297 /* Ensure the second source is not overwritten. */
8298 if (reg1
== reg0
+ (WORDS_BIG_ENDIAN
? -1 : 1))
8299 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands
);
8301 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands
);
8303 else if (code1
== CONST_VECTOR
)
8305 HOST_WIDE_INT hint
= 0;
8307 switch (GET_MODE (operands
[1]))
8310 otherops
[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands
[1], 1)));
8311 operands
[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands
[1], 0)));
8315 if (BYTES_BIG_ENDIAN
)
8317 hint
= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
8319 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
8323 hint
= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
8325 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
8328 otherops
[1] = GEN_INT (hint
);
8331 if (BYTES_BIG_ENDIAN
)
8333 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
8335 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
8339 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
8341 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
8344 operands
[1] = GEN_INT (hint
);
8348 if (BYTES_BIG_ENDIAN
)
8350 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 4));
8352 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 5));
8354 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 6));
8356 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 7));
8360 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 7));
8362 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 6));
8364 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 5));
8366 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 4));
8369 otherops
[1] = GEN_INT (hint
);
8372 if (BYTES_BIG_ENDIAN
)
8374 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
8376 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
8378 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
8380 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
8384 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
8386 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
8388 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
8390 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
8393 operands
[1] = GEN_INT (hint
);
8399 output_mov_immediate (operands
);
8400 output_mov_immediate (otherops
);
8402 else if (code1
== CONST_DOUBLE
)
8404 if (GET_MODE (operands
[1]) == DFmode
)
8409 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
8410 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
8411 otherops
[1] = GEN_INT (l
[1]);
8412 operands
[1] = GEN_INT (l
[0]);
8414 else if (GET_MODE (operands
[1]) != VOIDmode
)
8416 else if (WORDS_BIG_ENDIAN
)
8418 otherops
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
8419 operands
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
8423 otherops
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
8424 operands
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
8427 output_mov_immediate (operands
);
8428 output_mov_immediate (otherops
);
8430 else if (code1
== CONST_INT
)
8432 #if HOST_BITS_PER_WIDE_INT > 32
8433 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
8434 what the upper word is. */
8435 if (WORDS_BIG_ENDIAN
)
8437 otherops
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
8438 operands
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
8442 otherops
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
8443 operands
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
8446 /* Sign extend the intval into the high-order word. */
8447 if (WORDS_BIG_ENDIAN
)
8449 otherops
[1] = operands
[1];
8450 operands
[1] = (INTVAL (operands
[1]) < 0
8451 ? constm1_rtx
: const0_rtx
);
8454 otherops
[1] = INTVAL (operands
[1]) < 0 ? constm1_rtx
: const0_rtx
;
8456 output_mov_immediate (otherops
);
8457 output_mov_immediate (operands
);
8459 else if (code1
== MEM
)
8461 switch (GET_CODE (XEXP (operands
[1], 0)))
8464 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
8469 abort (); /* Should never happen now. */
8470 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands
);
8474 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
8478 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
8483 abort (); /* Should never happen now. */
8484 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands
);
8489 otherops
[0] = operands
[0];
8490 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
8491 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
8493 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
8495 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
8497 /* Registers overlap so split out the increment. */
8498 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8499 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops
);
8502 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops
);
8506 /* We only allow constant increments, so this is safe. */
8507 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops
);
8513 output_asm_insn ("adr%?\t%0, %1", operands
);
8514 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
8518 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
8519 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
8521 otherops
[0] = operands
[0];
8522 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
8523 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
8525 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
8527 if (GET_CODE (otherops
[2]) == CONST_INT
)
8529 switch ((int) INTVAL (otherops
[2]))
8532 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
8535 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
8538 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
8543 && (GET_CODE (otherops
[2]) == REG
8544 || (GET_CODE (otherops
[2]) == CONST_INT
8545 && INTVAL (otherops
[2]) > -256
8546 && INTVAL (otherops
[2]) < 256)))
8548 if (reg_overlap_mentioned_p (otherops
[0],
8551 /* Swap base and index registers over to
8552 avoid a conflict. */
8553 otherops
[1] = XEXP (XEXP (operands
[1], 0), 1);
8554 otherops
[2] = XEXP (XEXP (operands
[1], 0), 0);
8557 /* If both registers conflict, it will usually
8558 have been fixed by a splitter. */
8559 if (reg_overlap_mentioned_p (otherops
[0],
8562 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
8563 output_asm_insn ("ldr%?d\t%0, [%1]",
8569 output_asm_insn ("ldr%?d\t%0, [%1, %2]",
8574 if (GET_CODE (otherops
[2]) == CONST_INT
)
8576 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
8577 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
8579 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8582 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
8585 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
8587 return "ldm%?ia\t%0, %M0";
8591 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
8592 /* Take care of overlapping base/data reg. */
8593 if (reg_mentioned_p (operands
[0], operands
[1]))
8595 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8596 output_asm_insn ("ldr%?\t%0, %1", operands
);
8600 output_asm_insn ("ldr%?\t%0, %1", operands
);
8601 output_asm_insn ("ldr%?\t%0, %1", otherops
);
8607 abort (); /* Constraints should prevent this. */
8609 else if (code0
== MEM
&& code1
== REG
)
8611 if (REGNO (operands
[1]) == IP_REGNUM
)
8614 switch (GET_CODE (XEXP (operands
[0], 0)))
8617 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
8622 abort (); /* Should never happen now. */
8623 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands
);
8627 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
8631 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
8636 abort (); /* Should never happen now. */
8637 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands
);
8642 otherops
[0] = operands
[1];
8643 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
8644 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
8646 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
8647 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops
);
8649 output_asm_insn ("str%?d\t%0, [%1], %2", otherops
);
8653 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
8654 if (GET_CODE (otherops
[2]) == CONST_INT
)
8656 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
8659 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
8663 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
8667 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
8672 && (GET_CODE (otherops
[2]) == REG
8673 || (GET_CODE (otherops
[2]) == CONST_INT
8674 && INTVAL (otherops
[2]) > -256
8675 && INTVAL (otherops
[2]) < 256)))
8677 otherops
[0] = operands
[1];
8678 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
8679 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops
);
8685 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
8686 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
8687 output_asm_insn ("str%?\t%1, %0", operands
);
8688 output_asm_insn ("str%?\t%1, %0", otherops
);
8692 /* Constraints should prevent this. */
8699 /* Output an arbitrary MOV reg, #n.
8700 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
8702 output_mov_immediate (rtx
*operands
)
8704 HOST_WIDE_INT n
= INTVAL (operands
[1]);
8706 /* Try to use one MOV. */
8707 if (const_ok_for_arm (n
))
8708 output_asm_insn ("mov%?\t%0, %1", operands
);
8710 /* Try to use one MVN. */
8711 else if (const_ok_for_arm (~n
))
8713 operands
[1] = GEN_INT (~n
);
8714 output_asm_insn ("mvn%?\t%0, %1", operands
);
8721 /* If all else fails, make it out of ORRs or BICs as appropriate. */
8722 for (i
= 0; i
< 32; i
++)
8726 if (n_ones
> 16) /* Shorter to use MVN with BIC in this case. */
8727 output_multi_immediate (operands
, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n
);
8729 output_multi_immediate (operands
, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n
);
8735 /* Output an ADD r, s, #n where n may be too big for one instruction.
8736 If adding zero to one register, output nothing. */
8738 output_add_immediate (rtx
*operands
)
8740 HOST_WIDE_INT n
= INTVAL (operands
[2]);
8742 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
8745 output_multi_immediate (operands
,
8746 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8749 output_multi_immediate (operands
,
8750 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8757 /* Output a multiple immediate operation.
8758 OPERANDS is the vector of operands referred to in the output patterns.
8759 INSTR1 is the output pattern to use for the first constant.
8760 INSTR2 is the output pattern to use for subsequent constants.
8761 IMMED_OP is the index of the constant slot in OPERANDS.
8762 N is the constant value. */
8764 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
8765 int immed_op
, HOST_WIDE_INT n
)
8767 #if HOST_BITS_PER_WIDE_INT > 32
8773 /* Quick and easy output. */
8774 operands
[immed_op
] = const0_rtx
;
8775 output_asm_insn (instr1
, operands
);
8780 const char * instr
= instr1
;
8782 /* Note that n is never zero here (which would give no output). */
8783 for (i
= 0; i
< 32; i
+= 2)
8787 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
8788 output_asm_insn (instr
, operands
);
8798 /* Return the appropriate ARM instruction for the operation code.
8799 The returned result should not be overwritten. OP is the rtx of the
8800 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8803 arithmetic_instr (rtx op
, int shift_first_arg
)
8805 switch (GET_CODE (op
))
8811 return shift_first_arg
? "rsb" : "sub";
8827 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8828 for the operation code. The returned result should not be overwritten.
8829 OP is the rtx code of the shift.
8830 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8833 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
8836 enum rtx_code code
= GET_CODE (op
);
8838 if (GET_CODE (XEXP (op
, 1)) == REG
|| GET_CODE (XEXP (op
, 1)) == SUBREG
)
8840 else if (GET_CODE (XEXP (op
, 1)) == CONST_INT
)
8841 *amountp
= INTVAL (XEXP (op
, 1));
8864 /* We never have to worry about the amount being other than a
8865 power of 2, since this case can never be reloaded from a reg. */
8867 *amountp
= int_log2 (*amountp
);
8878 /* This is not 100% correct, but follows from the desire to merge
8879 multiplication by a power of 2 with the recognizer for a
8880 shift. >=32 is not a valid shift for "asl", so we must try and
8881 output a shift that produces the correct arithmetical result.
8882 Using lsr #32 is identical except for the fact that the carry bit
8883 is not set correctly if we set the flags; but we never use the
8884 carry bit from such an operation, so we can ignore that. */
8885 if (code
== ROTATERT
)
8886 /* Rotate is just modulo 32. */
8888 else if (*amountp
!= (*amountp
& 31))
8895 /* Shifts of 0 are no-ops. */
8903 /* Obtain the shift from the POWER of two. */
8905 static HOST_WIDE_INT
8906 int_log2 (HOST_WIDE_INT power
)
8908 HOST_WIDE_INT shift
= 0;
8910 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
8920 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
8921 /bin/as is horribly restrictive. */
8922 #define MAX_ASCII_LEN 51
8925 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
8930 fputs ("\t.ascii\t\"", stream
);
8932 for (i
= 0; i
< len
; i
++)
8936 if (len_so_far
>= MAX_ASCII_LEN
)
8938 fputs ("\"\n\t.ascii\t\"", stream
);
8945 fputs ("\\t", stream
);
8950 fputs ("\\f", stream
);
8955 fputs ("\\b", stream
);
8960 fputs ("\\r", stream
);
8964 case TARGET_NEWLINE
:
8965 fputs ("\\n", stream
);
8967 if ((c
>= ' ' && c
<= '~')
8969 /* This is a good place for a line break. */
8970 len_so_far
= MAX_ASCII_LEN
;
8977 putc ('\\', stream
);
8982 if (c
>= ' ' && c
<= '~')
8989 fprintf (stream
, "\\%03o", c
);
8996 fputs ("\"\n", stream
);
8999 /* Compute the register save mask for registers 0 through 12
9000 inclusive. This code is used by arm_compute_save_reg_mask. */
9001 static unsigned long
9002 arm_compute_save_reg0_reg12_mask (void)
9004 unsigned long func_type
= arm_current_func_type ();
9005 unsigned int save_reg_mask
= 0;
9008 if (IS_INTERRUPT (func_type
))
9010 unsigned int max_reg
;
9011 /* Interrupt functions must not corrupt any registers,
9012 even call clobbered ones. If this is a leaf function
9013 we can just examine the registers used by the RTL, but
9014 otherwise we have to assume that whatever function is
9015 called might clobber anything, and so we have to save
9016 all the call-clobbered registers as well. */
9017 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
9018 /* FIQ handlers have registers r8 - r12 banked, so
9019 we only need to check r0 - r7, Normal ISRs only
9020 bank r14 and r15, so we must check up to r12.
9021 r13 is the stack pointer which is always preserved,
9022 so we do not need to consider it here. */
9027 for (reg
= 0; reg
<= max_reg
; reg
++)
9028 if (regs_ever_live
[reg
]
9029 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
9030 save_reg_mask
|= (1 << reg
);
9034 /* In the normal case we only need to save those registers
9035 which are call saved and which are used by this function. */
9036 for (reg
= 0; reg
<= 10; reg
++)
9037 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
9038 save_reg_mask
|= (1 << reg
);
9040 /* Handle the frame pointer as a special case. */
9041 if (! TARGET_APCS_FRAME
9042 && ! frame_pointer_needed
9043 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
9044 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
9045 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
9047 /* If we aren't loading the PIC register,
9048 don't stack it even though it may be live. */
9050 && ! TARGET_SINGLE_PIC_BASE
9051 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
9052 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
9055 /* Save registers so the exception handler can modify them. */
9056 if (current_function_calls_eh_return
)
9062 reg
= EH_RETURN_DATA_REGNO (i
);
9063 if (reg
== INVALID_REGNUM
)
9065 save_reg_mask
|= 1 << reg
;
9069 return save_reg_mask
;
9072 /* Compute a bit mask of which registers need to be
9073 saved on the stack for the current function. */
9075 static unsigned long
9076 arm_compute_save_reg_mask (void)
9078 unsigned int save_reg_mask
= 0;
9079 unsigned long func_type
= arm_current_func_type ();
9081 if (IS_NAKED (func_type
))
9082 /* This should never really happen. */
9085 /* If we are creating a stack frame, then we must save the frame pointer,
9086 IP (which will hold the old stack pointer), LR and the PC. */
9087 if (frame_pointer_needed
)
9089 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
9094 /* Volatile functions do not return, so there
9095 is no need to save any other registers. */
9096 if (IS_VOLATILE (func_type
))
9097 return save_reg_mask
;
9099 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
9101 /* Decide if we need to save the link register.
9102 Interrupt routines have their own banked link register,
9103 so they never need to save it.
9104 Otherwise if we do not use the link register we do not need to save
9105 it. If we are pushing other registers onto the stack however, we
9106 can save an instruction in the epilogue by pushing the link register
9107 now and then popping it back into the PC. This incurs extra memory
9108 accesses though, so we only do it when optimizing for size, and only
9109 if we know that we will not need a fancy return sequence. */
9110 if (regs_ever_live
[LR_REGNUM
]
9113 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9114 && !current_function_calls_eh_return
))
9115 save_reg_mask
|= 1 << LR_REGNUM
;
9117 if (cfun
->machine
->lr_save_eliminated
)
9118 save_reg_mask
&= ~ (1 << LR_REGNUM
);
9120 if (TARGET_REALLY_IWMMXT
9121 && ((bit_count (save_reg_mask
)
9122 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
9126 /* The total number of registers that are going to be pushed
9127 onto the stack is odd. We need to ensure that the stack
9128 is 64-bit aligned before we start to save iWMMXt registers,
9129 and also before we start to create locals. (A local variable
9130 might be a double or long long which we will load/store using
9131 an iWMMXt instruction). Therefore we need to push another
9132 ARM register, so that the stack will be 64-bit aligned. We
9133 try to avoid using the arg registers (r0 -r3) as they might be
9134 used to pass values in a tail call. */
9135 for (reg
= 4; reg
<= 12; reg
++)
9136 if ((save_reg_mask
& (1 << reg
)) == 0)
9140 save_reg_mask
|= (1 << reg
);
9143 cfun
->machine
->sibcall_blocked
= 1;
9144 save_reg_mask
|= (1 << 3);
9148 return save_reg_mask
;
9152 /* Return the number of bytes required to save VFP registers. */
9154 arm_get_vfp_saved_size (void)
9161 /* Space for saved VFP registers. */
9162 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9165 for (regno
= FIRST_VFP_REGNUM
;
9166 regno
< LAST_VFP_REGNUM
;
9169 if ((!regs_ever_live
[regno
] || call_used_regs
[regno
])
9170 && (!regs_ever_live
[regno
+ 1] || call_used_regs
[regno
+ 1]))
9174 /* Workaround ARM10 VFPr1 bug. */
9175 if (count
== 2 && !arm_arch6
)
9177 saved
+= count
* 8 + 4;
9186 if (count
== 2 && !arm_arch6
)
9188 saved
+= count
* 8 + 4;
9195 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9196 everything bar the final return instruction. */
9198 output_return_instruction (rtx operand
, int really_return
, int reverse
)
9200 char conditional
[10];
9203 unsigned long live_regs_mask
;
9204 unsigned long func_type
;
9205 arm_stack_offsets
*offsets
;
9207 func_type
= arm_current_func_type ();
9209 if (IS_NAKED (func_type
))
9212 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9214 /* If this function was declared non-returning, and we have
9215 found a tail call, then we have to trust that the called
9216 function won't return. */
9221 /* Otherwise, trap an attempted return by aborting. */
9223 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
9225 assemble_external_libcall (ops
[1]);
9226 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
9232 if (current_function_calls_alloca
&& !really_return
)
9235 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
9237 return_used_this_function
= 1;
9239 live_regs_mask
= arm_compute_save_reg_mask ();
9243 const char * return_reg
;
9245 /* If we do not have any special requirements for function exit
9246 (eg interworking, or ISR) then we can load the return address
9247 directly into the PC. Otherwise we must load it into LR. */
9249 && ! TARGET_INTERWORK
)
9250 return_reg
= reg_names
[PC_REGNUM
];
9252 return_reg
= reg_names
[LR_REGNUM
];
9254 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
9256 /* There are three possible reasons for the IP register
9257 being saved. 1) a stack frame was created, in which case
9258 IP contains the old stack pointer, or 2) an ISR routine
9259 corrupted it, or 3) it was saved to align the stack on
9260 iWMMXt. In case 1, restore IP into SP, otherwise just
9262 if (frame_pointer_needed
)
9264 live_regs_mask
&= ~ (1 << IP_REGNUM
);
9265 live_regs_mask
|= (1 << SP_REGNUM
);
9269 if (! IS_INTERRUPT (func_type
)
9270 && ! TARGET_REALLY_IWMMXT
)
9275 /* On some ARM architectures it is faster to use LDR rather than
9276 LDM to load a single register. On other architectures, the
9277 cost is the same. In 26 bit mode, or for exception handlers,
9278 we have to use LDM to load the PC so that the CPSR is also
9280 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9282 if (live_regs_mask
== (unsigned int)(1 << reg
))
9285 if (reg
<= LAST_ARM_REGNUM
9286 && (reg
!= LR_REGNUM
9288 || ! IS_INTERRUPT (func_type
)))
9290 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
9291 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
9298 /* Generate the load multiple instruction to restore the
9299 registers. Note we can get here, even if
9300 frame_pointer_needed is true, but only if sp already
9301 points to the base of the saved core registers. */
9302 if (live_regs_mask
& (1 << SP_REGNUM
))
9304 unsigned HOST_WIDE_INT stack_adjust
;
9306 offsets
= arm_get_frame_offsets ();
9307 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
9308 if (stack_adjust
!= 0 && stack_adjust
!= 4)
9311 if (stack_adjust
&& arm_arch5
)
9312 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
9315 /* If we can't use ldmib (SA110 bug), then try to pop r3
9318 live_regs_mask
|= 1 << 3;
9319 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
9323 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
9325 p
= instr
+ strlen (instr
);
9327 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
9328 if (live_regs_mask
& (1 << reg
))
9330 int l
= strlen (reg_names
[reg
]);
9336 memcpy (p
, ", ", 2);
9340 memcpy (p
, "%|", 2);
9341 memcpy (p
+ 2, reg_names
[reg
], l
);
9345 if (live_regs_mask
& (1 << LR_REGNUM
))
9347 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
9348 /* If returning from an interrupt, restore the CPSR. */
9349 if (IS_INTERRUPT (func_type
))
9356 output_asm_insn (instr
, & operand
);
9358 /* See if we need to generate an extra instruction to
9359 perform the actual function return. */
9361 && func_type
!= ARM_FT_INTERWORKED
9362 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
9364 /* The return has already been handled
9365 by loading the LR into the PC. */
9372 switch ((int) ARM_FUNC_TYPE (func_type
))
9376 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
9379 case ARM_FT_INTERWORKED
:
9380 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9383 case ARM_FT_EXCEPTION
:
9384 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
9388 /* Use bx if it's available. */
9389 if (arm_arch5
|| arm_arch4t
)
9390 sprintf (instr
, "bx%s\t%%|lr", conditional
);
9392 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
9396 output_asm_insn (instr
, & operand
);
9402 /* Write the function name into the code section, directly preceding
9403 the function prologue.
9405 Code will be output similar to this:
9407 .ascii "arm_poke_function_name", 0
9410 .word 0xff000000 + (t1 - t0)
9411 arm_poke_function_name
9413 stmfd sp!, {fp, ip, lr, pc}
9416 When performing a stack backtrace, code can inspect the value
9417 of 'pc' stored at 'fp' + 0. If the trace function then looks
9418 at location pc - 12 and the top 8 bits are set, then we know
9419 that there is a function name embedded immediately preceding this
9420 location and has length ((pc[-3]) & 0xff000000).
9422 We assume that pc is declared as a pointer to an unsigned long.
9424 It is of no benefit to output the function name if we are assembling
9425 a leaf function. These function types will not contain a stack
9426 backtrace structure, therefore it is not possible to determine the
9429 arm_poke_function_name (FILE *stream
, const char *name
)
9431 unsigned long alignlength
;
9432 unsigned long length
;
9435 length
= strlen (name
) + 1;
9436 alignlength
= ROUND_UP_WORD (length
);
9438 ASM_OUTPUT_ASCII (stream
, name
, length
);
9439 ASM_OUTPUT_ALIGN (stream
, 2);
9440 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
9441 assemble_aligned_integer (UNITS_PER_WORD
, x
);
9444 /* Place some comments into the assembler stream
9445 describing the current function. */
9447 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
9449 unsigned long func_type
;
9453 thumb_output_function_prologue (f
, frame_size
);
9458 if (arm_ccfsm_state
|| arm_target_insn
)
9461 func_type
= arm_current_func_type ();
9463 switch ((int) ARM_FUNC_TYPE (func_type
))
9468 case ARM_FT_INTERWORKED
:
9469 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
9472 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
9475 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
9477 case ARM_FT_EXCEPTION
:
9478 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
9482 if (IS_NAKED (func_type
))
9483 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9485 if (IS_VOLATILE (func_type
))
9486 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
9488 if (IS_NESTED (func_type
))
9489 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
9491 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9492 current_function_args_size
,
9493 current_function_pretend_args_size
, frame_size
);
9495 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9496 frame_pointer_needed
,
9497 cfun
->machine
->uses_anonymous_args
);
9499 if (cfun
->machine
->lr_save_eliminated
)
9500 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
9502 if (current_function_calls_eh_return
)
9503 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
9505 #ifdef AOF_ASSEMBLER
9507 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
9510 return_used_this_function
= 0;
9514 arm_output_epilogue (rtx sibling
)
9517 unsigned long saved_regs_mask
;
9518 unsigned long func_type
;
9519 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9520 frame that is $fp + 4 for a non-variadic function. */
9521 int floats_offset
= 0;
9523 FILE * f
= asm_out_file
;
9524 unsigned int lrm_count
= 0;
9525 int really_return
= (sibling
== NULL
);
9527 arm_stack_offsets
*offsets
;
9529 /* If we have already generated the return instruction
9530 then it is futile to generate anything else. */
9531 if (use_return_insn (FALSE
, sibling
) && return_used_this_function
)
9534 func_type
= arm_current_func_type ();
9536 if (IS_NAKED (func_type
))
9537 /* Naked functions don't have epilogues. */
9540 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
9544 /* A volatile function should never return. Call abort. */
9545 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
9546 assemble_external_libcall (op
);
9547 output_asm_insn ("bl\t%a0", &op
);
9552 if (current_function_calls_eh_return
9554 /* If we are throwing an exception, then we really must
9555 be doing a return, so we can't tail-call. */
9558 offsets
= arm_get_frame_offsets ();
9559 saved_regs_mask
= arm_compute_save_reg_mask ();
9562 lrm_count
= bit_count (saved_regs_mask
);
9564 floats_offset
= offsets
->saved_args
;
9565 /* Compute how far away the floats will be. */
9566 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
9567 if (saved_regs_mask
& (1 << reg
))
9570 if (frame_pointer_needed
)
9572 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9573 int vfp_offset
= offsets
->frame
;
9575 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9577 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9578 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9580 floats_offset
+= 12;
9581 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
9582 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9587 start_reg
= LAST_FPA_REGNUM
;
9589 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
9591 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9593 floats_offset
+= 12;
9595 /* We can't unstack more than four registers at once. */
9596 if (start_reg
- reg
== 3)
9598 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
9599 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
9600 start_reg
= reg
- 1;
9605 if (reg
!= start_reg
)
9606 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9607 reg
+ 1, start_reg
- reg
,
9608 FP_REGNUM
, floats_offset
- vfp_offset
);
9609 start_reg
= reg
- 1;
9613 /* Just in case the last register checked also needs unstacking. */
9614 if (reg
!= start_reg
)
9615 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
9616 reg
+ 1, start_reg
- reg
,
9617 FP_REGNUM
, floats_offset
- vfp_offset
);
9620 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9624 /* The fldmx insn does not have base+offset addressing modes,
9625 so we use IP to hold the address. */
9626 saved_size
= arm_get_vfp_saved_size ();
9630 floats_offset
+= saved_size
;
9631 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", IP_REGNUM
,
9632 FP_REGNUM
, floats_offset
- vfp_offset
);
9634 start_reg
= FIRST_VFP_REGNUM
;
9635 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9637 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9638 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9640 if (start_reg
!= reg
)
9641 arm_output_fldmx (f
, IP_REGNUM
,
9642 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9643 (reg
- start_reg
) / 2);
9644 start_reg
= reg
+ 2;
9647 if (start_reg
!= reg
)
9648 arm_output_fldmx (f
, IP_REGNUM
,
9649 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9650 (reg
- start_reg
) / 2);
9655 /* The frame pointer is guaranteed to be non-double-word aligned.
9656 This is because it is set to (old_stack_pointer - 4) and the
9657 old_stack_pointer was double word aligned. Thus the offset to
9658 the iWMMXt registers to be loaded must also be non-double-word
9659 sized, so that the resultant address *is* double-word aligned.
9660 We can ignore floats_offset since that was already included in
9661 the live_regs_mask. */
9662 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
9664 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
9665 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9667 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
9668 reg
, FP_REGNUM
, lrm_count
* 4);
9673 /* saved_regs_mask should contain the IP, which at the time of stack
9674 frame generation actually contains the old stack pointer. So a
9675 quick way to unwind the stack is just pop the IP register directly
9676 into the stack pointer. */
9677 if ((saved_regs_mask
& (1 << IP_REGNUM
)) == 0)
9679 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
9680 saved_regs_mask
|= (1 << SP_REGNUM
);
9682 /* There are two registers left in saved_regs_mask - LR and PC. We
9683 only need to restore the LR register (the return address), but to
9684 save time we can load it directly into the PC, unless we need a
9685 special function exit sequence, or we are not really returning. */
9687 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9688 && !current_function_calls_eh_return
)
9689 /* Delete the LR from the register mask, so that the LR on
9690 the stack is loaded into the PC in the register mask. */
9691 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9693 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
9695 /* We must use SP as the base register, because SP is one of the
9696 registers being restored. If an interrupt or page fault
9697 happens in the ldm instruction, the SP might or might not
9698 have been restored. That would be bad, as then SP will no
9699 longer indicate the safe area of stack, and we can get stack
9700 corruption. Using SP as the base register means that it will
9701 be reset correctly to the original value, should an interrupt
9702 occur. If the stack pointer already points at the right
9703 place, then omit the subtraction. */
9704 if (offsets
->outgoing_args
!= (1 + (int) bit_count (saved_regs_mask
))
9705 || current_function_calls_alloca
)
9706 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
9707 4 * bit_count (saved_regs_mask
));
9708 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9710 if (IS_INTERRUPT (func_type
))
9711 /* Interrupt handlers will have pushed the
9712 IP onto the stack, so restore it now. */
9713 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
9717 /* Restore stack pointer if necessary. */
9718 if (offsets
->outgoing_args
!= offsets
->saved_regs
)
9720 operands
[0] = operands
[1] = stack_pointer_rtx
;
9721 operands
[2] = GEN_INT (offsets
->outgoing_args
- offsets
->saved_regs
);
9722 output_add_immediate (operands
);
9725 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9727 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9728 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9729 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
9734 start_reg
= FIRST_FPA_REGNUM
;
9736 for (reg
= FIRST_FPA_REGNUM
; reg
<= LAST_FPA_REGNUM
; reg
++)
9738 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9740 if (reg
- start_reg
== 3)
9742 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
9743 start_reg
, SP_REGNUM
);
9744 start_reg
= reg
+ 1;
9749 if (reg
!= start_reg
)
9750 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9751 start_reg
, reg
- start_reg
,
9754 start_reg
= reg
+ 1;
9758 /* Just in case the last register checked also needs unstacking. */
9759 if (reg
!= start_reg
)
9760 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
9761 start_reg
, reg
- start_reg
, SP_REGNUM
);
9764 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
9766 start_reg
= FIRST_VFP_REGNUM
;
9767 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
9769 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
9770 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
9772 if (start_reg
!= reg
)
9773 arm_output_fldmx (f
, SP_REGNUM
,
9774 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9775 (reg
- start_reg
) / 2);
9776 start_reg
= reg
+ 2;
9779 if (start_reg
!= reg
)
9780 arm_output_fldmx (f
, SP_REGNUM
,
9781 (start_reg
- FIRST_VFP_REGNUM
) / 2,
9782 (reg
- start_reg
) / 2);
9785 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
9786 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9787 asm_fprintf (f
, "\twldrd\t%r, [%r], #8\n", reg
, SP_REGNUM
);
9789 /* If we can, restore the LR into the PC. */
9790 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
9792 && current_function_pretend_args_size
== 0
9793 && saved_regs_mask
& (1 << LR_REGNUM
)
9794 && !current_function_calls_eh_return
)
9796 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
9797 saved_regs_mask
|= (1 << PC_REGNUM
);
9800 /* Load the registers off the stack. If we only have one register
9801 to load use the LDR instruction - it is faster. */
9802 if (saved_regs_mask
== (1 << LR_REGNUM
))
9804 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
9806 else if (saved_regs_mask
)
9808 if (saved_regs_mask
& (1 << SP_REGNUM
))
9809 /* Note - write back to the stack register is not enabled
9810 (ie "ldmfd sp!..."). We know that the stack pointer is
9811 in the list of registers and if we add writeback the
9812 instruction becomes UNPREDICTABLE. */
9813 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
9815 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
9818 if (current_function_pretend_args_size
)
9820 /* Unwind the pre-pushed regs. */
9821 operands
[0] = operands
[1] = stack_pointer_rtx
;
9822 operands
[2] = GEN_INT (current_function_pretend_args_size
);
9823 output_add_immediate (operands
);
9827 /* We may have already restored PC directly from the stack. */
9828 if (!really_return
|| saved_regs_mask
& (1 << PC_REGNUM
))
9831 /* Stack adjustment for exception handler. */
9832 if (current_function_calls_eh_return
)
9833 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
9834 ARM_EH_STACKADJ_REGNUM
);
9836 /* Generate the return instruction. */
9837 switch ((int) ARM_FUNC_TYPE (func_type
))
9841 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
9844 case ARM_FT_EXCEPTION
:
9845 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
9848 case ARM_FT_INTERWORKED
:
9849 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
9853 if (arm_arch5
|| arm_arch4t
)
9854 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
9856 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
9864 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
9865 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
9867 arm_stack_offsets
*offsets
;
9871 /* ??? Probably not safe to set this here, since it assumes that a
9872 function will be emitted as assembly immediately after we generate
9873 RTL for it. This does not happen for inline functions. */
9874 return_used_this_function
= 0;
9878 /* We need to take into account any stack-frame rounding. */
9879 offsets
= arm_get_frame_offsets ();
9881 if (use_return_insn (FALSE
, NULL
)
9882 && return_used_this_function
9883 && offsets
->saved_regs
!= offsets
->outgoing_args
9884 && !frame_pointer_needed
)
9887 /* Reset the ARM-specific per-function variables. */
9888 after_arm_reorg
= 0;
9892 /* Generate and emit an insn that we will recognize as a push_multi.
9893 Unfortunately, since this insn does not reflect very well the actual
9894 semantics of the operation, we need to annotate the insn for the benefit
9895 of DWARF2 frame unwind information. */
9897 emit_multi_reg_push (int mask
)
9904 int dwarf_par_index
;
9907 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
9908 if (mask
& (1 << i
))
9911 if (num_regs
== 0 || num_regs
> 16)
9914 /* We don't record the PC in the dwarf frame information. */
9915 num_dwarf_regs
= num_regs
;
9916 if (mask
& (1 << PC_REGNUM
))
9919 /* For the body of the insn we are going to generate an UNSPEC in
9920 parallel with several USEs. This allows the insn to be recognized
9921 by the push_multi pattern in the arm.md file. The insn looks
9922 something like this:
9925 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9926 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9927 (use (reg:SI 11 fp))
9928 (use (reg:SI 12 ip))
9929 (use (reg:SI 14 lr))
9930 (use (reg:SI 15 pc))
9933 For the frame note however, we try to be more explicit and actually
9934 show each register being stored into the stack frame, plus a (single)
9935 decrement of the stack pointer. We do it this way in order to be
9936 friendly to the stack unwinding code, which only wants to see a single
9937 stack decrement per instruction. The RTL we generate for the note looks
9938 something like this:
9941 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9942 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9943 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9944 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9945 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9948 This sequence is used both by the code to support stack unwinding for
9949 exceptions handlers and the code to generate dwarf2 frame debugging. */
9951 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
9952 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
9953 dwarf_par_index
= 1;
9955 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
9957 if (mask
& (1 << i
))
9959 reg
= gen_rtx_REG (SImode
, i
);
9962 = gen_rtx_SET (VOIDmode
,
9963 gen_rtx_MEM (BLKmode
,
9964 gen_rtx_PRE_DEC (BLKmode
,
9965 stack_pointer_rtx
)),
9966 gen_rtx_UNSPEC (BLKmode
,
9972 tmp
= gen_rtx_SET (VOIDmode
,
9973 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
9975 RTX_FRAME_RELATED_P (tmp
) = 1;
9976 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
9984 for (j
= 1, i
++; j
< num_regs
; i
++)
9986 if (mask
& (1 << i
))
9988 reg
= gen_rtx_REG (SImode
, i
);
9990 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
9994 tmp
= gen_rtx_SET (VOIDmode
,
9995 gen_rtx_MEM (SImode
,
9996 plus_constant (stack_pointer_rtx
,
9999 RTX_FRAME_RELATED_P (tmp
) = 1;
10000 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
10007 par
= emit_insn (par
);
10009 tmp
= gen_rtx_SET (SImode
,
10011 gen_rtx_PLUS (SImode
,
10013 GEN_INT (-4 * num_regs
)));
10014 RTX_FRAME_RELATED_P (tmp
) = 1;
10015 XVECEXP (dwarf
, 0, 0) = tmp
;
10017 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10023 emit_sfm (int base_reg
, int count
)
10030 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
10031 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
10033 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10035 XVECEXP (par
, 0, 0)
10036 = gen_rtx_SET (VOIDmode
,
10037 gen_rtx_MEM (BLKmode
,
10038 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
10039 gen_rtx_UNSPEC (BLKmode
,
10040 gen_rtvec (1, reg
),
10041 UNSPEC_PUSH_MULT
));
10042 tmp
= gen_rtx_SET (VOIDmode
,
10043 gen_rtx_MEM (XFmode
, stack_pointer_rtx
), reg
);
10044 RTX_FRAME_RELATED_P (tmp
) = 1;
10045 XVECEXP (dwarf
, 0, 1) = tmp
;
10047 for (i
= 1; i
< count
; i
++)
10049 reg
= gen_rtx_REG (XFmode
, base_reg
++);
10050 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
10052 tmp
= gen_rtx_SET (VOIDmode
,
10053 gen_rtx_MEM (XFmode
,
10054 plus_constant (stack_pointer_rtx
,
10057 RTX_FRAME_RELATED_P (tmp
) = 1;
10058 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
10061 tmp
= gen_rtx_SET (VOIDmode
,
10063 gen_rtx_PLUS (SImode
,
10065 GEN_INT (-12 * count
)));
10066 RTX_FRAME_RELATED_P (tmp
) = 1;
10067 XVECEXP (dwarf
, 0, 0) = tmp
;
10069 par
= emit_insn (par
);
10070 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
10076 /* Return true if the current function needs to save/restore LR. */
10079 thumb_force_lr_save (void)
10081 return !cfun
->machine
->lr_save_eliminated
10082 && (!leaf_function_p ()
10083 || thumb_far_jump_used_p ()
10084 || regs_ever_live
[LR_REGNUM
]);
10088 /* Compute the distance from register FROM to register TO.
10089 These can be the arg pointer (26), the soft frame pointer (25),
10090 the stack pointer (13) or the hard frame pointer (11).
10091 In thumb mode r7 is used as the soft frame pointer, if needed.
10092 Typical stack layout looks like this:
10094 old stack pointer -> | |
10097 | | saved arguments for
10098 | | vararg functions
10101 hard FP & arg pointer -> | | \
10109 soft frame pointer -> | | /
10119 current stack pointer -> | | /
10122 For a given function some or all of these stack components
10123 may not be needed, giving rise to the possibility of
10124 eliminating some of the registers.
10126 The values returned by this function must reflect the behavior
10127 of arm_expand_prologue() and arm_compute_save_reg_mask().
10129 The sign of the number returned reflects the direction of stack
10130 growth, so the values are positive for all eliminations except
10131 from the soft frame pointer to the hard frame pointer.
10133 SFP may point just inside the local variables block to ensure correct
10137 /* Calculate stack offsets. These are used to calculate register elimination
10138 offsets and in prologue/epilogue code. */
10140 static arm_stack_offsets
*
10141 arm_get_frame_offsets (void)
10143 struct arm_stack_offsets
*offsets
;
10144 unsigned long func_type
;
10147 HOST_WIDE_INT frame_size
;
10149 offsets
= &cfun
->machine
->stack_offsets
;
10151 /* We need to know if we are a leaf function. Unfortunately, it
10152 is possible to be called after start_sequence has been called,
10153 which causes get_insns to return the insns for the sequence,
10154 not the function, which will cause leaf_function_p to return
10155 the incorrect result.
10157 to know about leaf functions once reload has completed, and the
10158 frame size cannot be changed after that time, so we can safely
10159 use the cached value. */
10161 if (reload_completed
)
10164 /* Initially this is the size of the local variables. It will translated
10165 into an offset once we have determined the size of preceding data. */
10166 frame_size
= ROUND_UP_WORD (get_frame_size ());
10168 leaf
= leaf_function_p ();
10170 /* Space for variadic functions. */
10171 offsets
->saved_args
= current_function_pretend_args_size
;
10173 offsets
->frame
= offsets
->saved_args
+ (frame_pointer_needed
? 4 : 0);
10177 unsigned int regno
;
10179 saved
= bit_count (arm_compute_save_reg_mask ()) * 4;
10181 /* We know that SP will be doubleword aligned on entry, and we must
10182 preserve that condition at any subroutine call. We also require the
10183 soft frame pointer to be doubleword aligned. */
10185 if (TARGET_REALLY_IWMMXT
)
10187 /* Check for the call-saved iWMMXt registers. */
10188 for (regno
= FIRST_IWMMXT_REGNUM
;
10189 regno
<= LAST_IWMMXT_REGNUM
;
10191 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10195 func_type
= arm_current_func_type ();
10196 if (! IS_VOLATILE (func_type
))
10198 /* Space for saved FPA registers. */
10199 for (regno
= FIRST_FPA_REGNUM
; regno
<= LAST_FPA_REGNUM
; regno
++)
10200 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
10203 /* Space for saved VFP registers. */
10204 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10205 saved
+= arm_get_vfp_saved_size ();
10208 else /* TARGET_THUMB */
10215 for (reg
= 8; reg
< 13; reg
++)
10216 if (THUMB_REG_PUSHED_P (reg
))
10219 saved
+= 4 * count_regs
;
10221 for (reg
= 0; reg
<= LAST_LO_REGNUM
; reg
++)
10222 if (THUMB_REG_PUSHED_P (reg
))
10224 if (count_regs
|| thumb_force_lr_save ())
10225 saved
+= 4 * (count_regs
+ 1);
10226 if (TARGET_BACKTRACE
)
10228 if ((count_regs
& 0xFF) == 0 && (regs_ever_live
[3] != 0))
10235 /* Saved registers include the stack frame. */
10236 offsets
->saved_regs
= offsets
->saved_args
+ saved
;
10237 offsets
->soft_frame
= offsets
->saved_regs
;
10238 /* A leaf function does not need any stack alignment if it has nothing
10240 if (leaf
&& frame_size
== 0)
10242 offsets
->outgoing_args
= offsets
->soft_frame
;
10246 /* Ensure SFP has the correct alignment. */
10247 if (ARM_DOUBLEWORD_ALIGN
10248 && (offsets
->soft_frame
& 7))
10249 offsets
->soft_frame
+= 4;
10251 offsets
->outgoing_args
= offsets
->soft_frame
+ frame_size
10252 + current_function_outgoing_args_size
;
10254 if (ARM_DOUBLEWORD_ALIGN
)
10256 /* Ensure SP remains doubleword aligned. */
10257 if (offsets
->outgoing_args
& 7)
10258 offsets
->outgoing_args
+= 4;
10259 if (offsets
->outgoing_args
& 7)
10267 /* Calculate the relative offsets for the different stack pointers. Positive
10268 offsets are in the direction of stack growth. */
10271 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
10273 arm_stack_offsets
*offsets
;
10275 offsets
= arm_get_frame_offsets ();
10277 /* OK, now we have enough information to compute the distances.
10278 There must be an entry in these switch tables for each pair
10279 of registers in ELIMINABLE_REGS, even if some of the entries
10280 seem to be redundant or useless. */
10283 case ARG_POINTER_REGNUM
:
10286 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10289 case FRAME_POINTER_REGNUM
:
10290 /* This is the reverse of the soft frame pointer
10291 to hard frame pointer elimination below. */
10292 return offsets
->soft_frame
- offsets
->saved_args
;
10294 case ARM_HARD_FRAME_POINTER_REGNUM
:
10295 /* If there is no stack frame then the hard
10296 frame pointer and the arg pointer coincide. */
10297 if (offsets
->frame
== offsets
->saved_regs
)
10299 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10300 return (frame_pointer_needed
10301 && cfun
->static_chain_decl
!= NULL
10302 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
10304 case STACK_POINTER_REGNUM
:
10305 /* If nothing has been pushed on the stack at all
10306 then this will return -4. This *is* correct! */
10307 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
10314 case FRAME_POINTER_REGNUM
:
10317 case THUMB_HARD_FRAME_POINTER_REGNUM
:
10320 case ARM_HARD_FRAME_POINTER_REGNUM
:
10321 /* The hard frame pointer points to the top entry in the
10322 stack frame. The soft frame pointer to the bottom entry
10323 in the stack frame. If there is no stack frame at all,
10324 then they are identical. */
10326 return offsets
->frame
- offsets
->soft_frame
;
10328 case STACK_POINTER_REGNUM
:
10329 return offsets
->outgoing_args
- offsets
->soft_frame
;
10337 /* You cannot eliminate from the stack pointer.
10338 In theory you could eliminate from the hard frame
10339 pointer to the stack pointer, but this will never
10340 happen, since if a stack frame is not needed the
10341 hard frame pointer will never be used. */
10347 /* Generate the prologue instructions for entry into an ARM function. */
10349 arm_expand_prologue (void)
10355 unsigned long live_regs_mask
;
10356 unsigned long func_type
;
10358 int saved_pretend_args
= 0;
10359 int saved_regs
= 0;
10360 unsigned int args_to_push
;
10361 arm_stack_offsets
*offsets
;
10363 func_type
= arm_current_func_type ();
10365 /* Naked functions don't have prologues. */
10366 if (IS_NAKED (func_type
))
10369 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10370 args_to_push
= current_function_pretend_args_size
;
10372 /* Compute which register we will have to save onto the stack. */
10373 live_regs_mask
= arm_compute_save_reg_mask ();
10375 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
10377 if (frame_pointer_needed
)
10379 if (IS_INTERRUPT (func_type
))
10381 /* Interrupt functions must not corrupt any registers.
10382 Creating a frame pointer however, corrupts the IP
10383 register, so we must push it first. */
10384 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
10386 /* Do not set RTX_FRAME_RELATED_P on this insn.
10387 The dwarf stack unwinding code only wants to see one
10388 stack decrement per function, and this is not it. If
10389 this instruction is labeled as being part of the frame
10390 creation sequence then dwarf2out_frame_debug_expr will
10391 abort when it encounters the assignment of IP to FP
10392 later on, since the use of SP here establishes SP as
10393 the CFA register and not IP.
10395 Anyway this instruction is not really part of the stack
10396 frame creation although it is part of the prologue. */
10398 else if (IS_NESTED (func_type
))
10400 /* The Static chain register is the same as the IP register
10401 used as a scratch register during stack frame creation.
10402 To get around this need to find somewhere to store IP
10403 whilst the frame is being created. We try the following
10406 1. The last argument register.
10407 2. A slot on the stack above the frame. (This only
10408 works if the function is not a varargs function).
10409 3. Register r3, after pushing the argument registers
10412 Note - we only need to tell the dwarf2 backend about the SP
10413 adjustment in the second variant; the static chain register
10414 doesn't need to be unwound, as it doesn't contain a value
10415 inherited from the caller. */
10417 if (regs_ever_live
[3] == 0)
10419 insn
= gen_rtx_REG (SImode
, 3);
10420 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10421 insn
= emit_insn (insn
);
10423 else if (args_to_push
== 0)
10426 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
10427 insn
= gen_rtx_MEM (SImode
, insn
);
10428 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
10429 insn
= emit_insn (insn
);
10433 /* Just tell the dwarf backend that we adjusted SP. */
10434 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10435 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
10436 GEN_INT (-fp_offset
)));
10437 RTX_FRAME_RELATED_P (insn
) = 1;
10438 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
10439 dwarf
, REG_NOTES (insn
));
10443 /* Store the args on the stack. */
10444 if (cfun
->machine
->uses_anonymous_args
)
10445 insn
= emit_multi_reg_push
10446 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10449 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10450 GEN_INT (- args_to_push
)));
10452 RTX_FRAME_RELATED_P (insn
) = 1;
10454 saved_pretend_args
= 1;
10455 fp_offset
= args_to_push
;
10458 /* Now reuse r3 to preserve IP. */
10459 insn
= gen_rtx_REG (SImode
, 3);
10460 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
10461 (void) emit_insn (insn
);
10467 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
10468 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
10471 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
10473 insn
= emit_insn (insn
);
10474 RTX_FRAME_RELATED_P (insn
) = 1;
10479 /* Push the argument registers, or reserve space for them. */
10480 if (cfun
->machine
->uses_anonymous_args
)
10481 insn
= emit_multi_reg_push
10482 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
10485 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10486 GEN_INT (- args_to_push
)));
10487 RTX_FRAME_RELATED_P (insn
) = 1;
10490 /* If this is an interrupt service routine, and the link register
10491 is going to be pushed, and we are not creating a stack frame,
10492 (which would involve an extra push of IP and a pop in the epilogue)
10493 subtracting four from LR now will mean that the function return
10494 can be done with a single instruction. */
10495 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
10496 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
10497 && ! frame_pointer_needed
)
10498 emit_insn (gen_rtx_SET (SImode
,
10499 gen_rtx_REG (SImode
, LR_REGNUM
),
10500 gen_rtx_PLUS (SImode
,
10501 gen_rtx_REG (SImode
, LR_REGNUM
),
10504 if (live_regs_mask
)
10506 insn
= emit_multi_reg_push (live_regs_mask
);
10507 saved_regs
+= bit_count (live_regs_mask
) * 4;
10508 RTX_FRAME_RELATED_P (insn
) = 1;
10512 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
10513 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
10515 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
10516 insn
= gen_rtx_MEM (V2SImode
, insn
);
10517 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10518 gen_rtx_REG (V2SImode
, reg
)));
10519 RTX_FRAME_RELATED_P (insn
) = 1;
10523 if (! IS_VOLATILE (func_type
))
10527 /* Save any floating point call-saved registers used by this
10529 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
10531 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10532 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10534 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
10535 insn
= gen_rtx_MEM (XFmode
, insn
);
10536 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
10537 gen_rtx_REG (XFmode
, reg
)));
10538 RTX_FRAME_RELATED_P (insn
) = 1;
10544 start_reg
= LAST_FPA_REGNUM
;
10546 for (reg
= LAST_FPA_REGNUM
; reg
>= FIRST_FPA_REGNUM
; reg
--)
10548 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
10550 if (start_reg
- reg
== 3)
10552 insn
= emit_sfm (reg
, 4);
10553 RTX_FRAME_RELATED_P (insn
) = 1;
10555 start_reg
= reg
- 1;
10560 if (start_reg
!= reg
)
10562 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10563 RTX_FRAME_RELATED_P (insn
) = 1;
10564 saved_regs
+= (start_reg
- reg
) * 12;
10566 start_reg
= reg
- 1;
10570 if (start_reg
!= reg
)
10572 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
10573 saved_regs
+= (start_reg
- reg
) * 12;
10574 RTX_FRAME_RELATED_P (insn
) = 1;
10577 if (TARGET_HARD_FLOAT
&& TARGET_VFP
)
10579 start_reg
= FIRST_VFP_REGNUM
;
10581 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
10583 if ((!regs_ever_live
[reg
] || call_used_regs
[reg
])
10584 && (!regs_ever_live
[reg
+ 1] || call_used_regs
[reg
+ 1]))
10586 if (start_reg
!= reg
)
10587 saved_regs
+= vfp_emit_fstmx (start_reg
,
10588 (reg
- start_reg
) / 2);
10589 start_reg
= reg
+ 2;
10592 if (start_reg
!= reg
)
10593 saved_regs
+= vfp_emit_fstmx (start_reg
,
10594 (reg
- start_reg
) / 2);
10598 if (frame_pointer_needed
)
10600 /* Create the new frame pointer. */
10601 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
10602 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
10603 RTX_FRAME_RELATED_P (insn
) = 1;
10605 if (IS_NESTED (func_type
))
10607 /* Recover the static chain register. */
10608 if (regs_ever_live
[3] == 0
10609 || saved_pretend_args
)
10610 insn
= gen_rtx_REG (SImode
, 3);
10611 else /* if (current_function_pretend_args_size == 0) */
10613 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
,
10615 insn
= gen_rtx_MEM (SImode
, insn
);
10618 emit_insn (gen_rtx_SET (SImode
, ip_rtx
, insn
));
10619 /* Add a USE to stop propagate_one_insn() from barfing. */
10620 emit_insn (gen_prologue_use (ip_rtx
));
10624 offsets
= arm_get_frame_offsets ();
10625 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
10627 /* This add can produce multiple insns for a large constant, so we
10628 need to get tricky. */
10629 rtx last
= get_last_insn ();
10631 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
10632 - offsets
->outgoing_args
);
10634 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10638 last
= last
? NEXT_INSN (last
) : get_insns ();
10639 RTX_FRAME_RELATED_P (last
) = 1;
10641 while (last
!= insn
);
10643 /* If the frame pointer is needed, emit a special barrier that
10644 will prevent the scheduler from moving stores to the frame
10645 before the stack adjustment. */
10646 if (frame_pointer_needed
)
10647 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
10648 hard_frame_pointer_rtx
));
10651 /* If we are profiling, make sure no instructions are scheduled before
10652 the call to mcount. Similarly if the user has requested no
10653 scheduling in the prolog. */
10654 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
10655 emit_insn (gen_blockage ());
10657 /* If the link register is being kept alive, with the return address in it,
10658 then make sure that it does not get reused by the ce2 pass. */
10659 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
10661 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
10662 cfun
->machine
->lr_save_eliminated
= 1;
10666 /* If CODE is 'd', then the X is a condition operand and the instruction
10667 should only be executed if the condition is true.
10668 if CODE is 'D', then the X is a condition operand and the instruction
10669 should only be executed if the condition is false: however, if the mode
10670 of the comparison is CCFPEmode, then always execute the instruction -- we
10671 do this because in these circumstances !GE does not necessarily imply LT;
10672 in these cases the instruction pattern will take care to make sure that
10673 an instruction containing %d will follow, thereby undoing the effects of
10674 doing this instruction unconditionally.
10675 If CODE is 'N' then X is a floating point operand that must be negated
10677 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10678 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10680 arm_print_operand (FILE *stream
, rtx x
, int code
)
10685 fputs (ASM_COMMENT_START
, stream
);
10689 fputs (user_label_prefix
, stream
);
10693 fputs (REGISTER_PREFIX
, stream
);
10697 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
10699 if (TARGET_THUMB
|| current_insn_predicate
!= NULL
)
10702 fputs (arm_condition_codes
[arm_current_cc
], stream
);
10704 else if (current_insn_predicate
)
10706 enum arm_cond_code code
;
10711 code
= get_arm_condition_code (current_insn_predicate
);
10712 fputs (arm_condition_codes
[code
], stream
);
10719 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
10720 r
= REAL_VALUE_NEGATE (r
);
10721 fprintf (stream
, "%s", fp_const_from_val (&r
));
10726 if (GET_CODE (x
) == CONST_INT
)
10729 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
10730 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
10734 putc ('~', stream
);
10735 output_addr_const (stream
, x
);
10740 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
10743 /* Truncate Cirrus shift counts. */
10745 if (GET_CODE (x
) == CONST_INT
)
10747 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
10750 arm_print_operand (stream
, x
, 0);
10754 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
10760 const char * shift
= shift_op (x
, &val
);
10764 fprintf (stream
, ", %s ", shift_op (x
, &val
));
10766 arm_print_operand (stream
, XEXP (x
, 1), 0);
10768 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
10773 /* An explanation of the 'Q', 'R' and 'H' register operands:
10775 In a pair of registers containing a DI or DF value the 'Q'
10776 operand returns the register number of the register containing
10777 the least significant part of the value. The 'R' operand returns
10778 the register number of the register containing the most
10779 significant part of the value.
10781 The 'H' operand returns the higher of the two register numbers.
10782 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10783 same as the 'Q' operand, since the most significant part of the
10784 value is held in the lower number register. The reverse is true
10785 on systems where WORDS_BIG_ENDIAN is false.
10787 The purpose of these operands is to distinguish between cases
10788 where the endian-ness of the values is important (for example
10789 when they are added together), and cases where the endian-ness
10790 is irrelevant, but the order of register operations is important.
10791 For example when loading a value from memory into a register
10792 pair, the endian-ness does not matter. Provided that the value
10793 from the lower memory address is put into the lower numbered
10794 register, and the value from the higher address is put into the
10795 higher numbered register, the load will work regardless of whether
10796 the value being loaded is big-wordian or little-wordian. The
10797 order of the two register loads can matter however, if the address
10798 of the memory location is actually held in one of the registers
10799 being overwritten by the load. */
10801 if (REGNO (x
) > LAST_ARM_REGNUM
)
10803 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
10807 if (REGNO (x
) > LAST_ARM_REGNUM
)
10809 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
10813 if (REGNO (x
) > LAST_ARM_REGNUM
)
10815 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
10819 asm_fprintf (stream
, "%r",
10820 GET_CODE (XEXP (x
, 0)) == REG
10821 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
10825 asm_fprintf (stream
, "{%r-%r}",
10827 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
10831 /* CONST_TRUE_RTX means always -- that's the default. */
10832 if (x
== const_true_rtx
)
10835 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
10840 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
10841 want to do that. */
10842 if (x
== const_true_rtx
)
10845 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
10846 (get_arm_condition_code (x
))],
10850 /* Cirrus registers can be accessed in a variety of ways:
10851 single floating point (f)
10852 double floating point (d)
10854 64bit integer (dx). */
10855 case 'W': /* Cirrus register in F mode. */
10856 case 'X': /* Cirrus register in D mode. */
10857 case 'Y': /* Cirrus register in FX mode. */
10858 case 'Z': /* Cirrus register in DX mode. */
10859 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
10862 fprintf (stream
, "mv%s%s",
10864 : code
== 'X' ? "d"
10865 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
10869 /* Print cirrus register in the mode specified by the register's mode. */
10872 int mode
= GET_MODE (x
);
10874 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
10877 fprintf (stream
, "mv%s%s",
10878 mode
== DFmode
? "d"
10879 : mode
== SImode
? "fx"
10880 : mode
== DImode
? "dx"
10881 : "f", reg_names
[REGNO (x
)] + 2);
10887 if (GET_CODE (x
) != REG
10888 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
10889 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
10890 /* Bad value for wCG register number. */
10893 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
10896 /* Print an iWMMXt control register name. */
10898 if (GET_CODE (x
) != CONST_INT
10900 || INTVAL (x
) >= 16)
10901 /* Bad value for wC register number. */
10905 static const char * wc_reg_names
[16] =
10907 "wCID", "wCon", "wCSSF", "wCASF",
10908 "wC4", "wC5", "wC6", "wC7",
10909 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10910 "wC12", "wC13", "wC14", "wC15"
10913 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
10917 /* Print a VFP double precision register name. */
10920 int mode
= GET_MODE (x
);
10923 if (mode
!= DImode
&& mode
!= DFmode
)
10926 if (GET_CODE (x
) != REG
10927 || !IS_VFP_REGNUM (REGNO (x
)))
10930 num
= REGNO(x
) - FIRST_VFP_REGNUM
;
10934 fprintf (stream
, "d%d", num
>> 1);
10942 if (GET_CODE (x
) == REG
)
10943 asm_fprintf (stream
, "%r", REGNO (x
));
10944 else if (GET_CODE (x
) == MEM
)
10946 output_memory_reference_mode
= GET_MODE (x
);
10947 output_address (XEXP (x
, 0));
10949 else if (GET_CODE (x
) == CONST_DOUBLE
)
10950 fprintf (stream
, "#%s", fp_immediate_constant (x
));
10951 else if (GET_CODE (x
) == NEG
)
10952 abort (); /* This should never happen now. */
10955 fputc ('#', stream
);
10956 output_addr_const (stream
, x
);
10961 #ifndef AOF_ASSEMBLER
10962 /* Target hook for assembling integer objects. The ARM version needs to
10963 handle word-sized values specially. */
10965 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
10967 if (size
== UNITS_PER_WORD
&& aligned_p
)
10969 fputs ("\t.word\t", asm_out_file
);
10970 output_addr_const (asm_out_file
, x
);
10972 /* Mark symbols as position independent. We only do this in the
10973 .text segment, not in the .data segment. */
10974 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
10975 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
10977 if (GET_CODE (x
) == SYMBOL_REF
10978 && (CONSTANT_POOL_ADDRESS_P (x
)
10979 || SYMBOL_REF_LOCAL_P (x
)))
10980 fputs ("(GOTOFF)", asm_out_file
);
10981 else if (GET_CODE (x
) == LABEL_REF
)
10982 fputs ("(GOTOFF)", asm_out_file
);
10984 fputs ("(GOT)", asm_out_file
);
10986 fputc ('\n', asm_out_file
);
10990 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x
)))
10994 if (GET_CODE (x
) != CONST_VECTOR
)
10997 units
= CONST_VECTOR_NUNITS (x
);
10999 switch (GET_MODE (x
))
11001 case V2SImode
: size
= 4; break;
11002 case V4HImode
: size
= 2; break;
11003 case V8QImode
: size
= 1; break;
11008 for (i
= 0; i
< units
; i
++)
11012 elt
= CONST_VECTOR_ELT (x
, i
);
11014 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
11020 return default_assemble_integer (x
, size
, aligned_p
);
11024 /* A finite state machine takes care of noticing whether or not instructions
11025 can be conditionally executed, and thus decrease execution time and code
11026 size by deleting branch instructions. The fsm is controlled by
11027 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
11029 /* The state of the fsm controlling condition codes are:
11030 0: normal, do nothing special
11031 1: make ASM_OUTPUT_OPCODE not output this instruction
11032 2: make ASM_OUTPUT_OPCODE not output this instruction
11033 3: make instructions conditional
11034 4: make instructions conditional
11036 State transitions (state->state by whom under condition):
11037 0 -> 1 final_prescan_insn if the `target' is a label
11038 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
11039 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
11040 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
11041 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
11042 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
11043 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
11044 (the target insn is arm_target_insn).
11046 If the jump clobbers the conditions then we use states 2 and 4.
11048 A similar thing can be done with conditional return insns.
11050 XXX In case the `target' is an unconditional branch, this conditionalising
11051 of the instructions always reduces code size, but not always execution
11052 time. But then, I want to reduce the code size to somewhere near what
11053 /bin/cc produces. */
11055 /* Returns the index of the ARM condition code string in
11056 `arm_condition_codes'. COMPARISON should be an rtx like
11057 `(eq (...) (...))'. */
11058 static enum arm_cond_code
11059 get_arm_condition_code (rtx comparison
)
11061 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
11063 enum rtx_code comp_code
= GET_CODE (comparison
);
11065 if (GET_MODE_CLASS (mode
) != MODE_CC
)
11066 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
11067 XEXP (comparison
, 1));
11071 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
11072 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
11073 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
11074 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
11075 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
11076 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
11077 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
11078 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
11079 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
11080 case CC_DLTUmode
: code
= ARM_CC
;
11083 if (comp_code
!= EQ
&& comp_code
!= NE
)
11086 if (comp_code
== EQ
)
11087 return ARM_INVERSE_CONDITION_CODE (code
);
11093 case NE
: return ARM_NE
;
11094 case EQ
: return ARM_EQ
;
11095 case GE
: return ARM_PL
;
11096 case LT
: return ARM_MI
;
11103 case NE
: return ARM_NE
;
11104 case EQ
: return ARM_EQ
;
11111 case NE
: return ARM_MI
;
11112 case EQ
: return ARM_PL
;
11118 /* These encodings assume that AC=1 in the FPA system control
11119 byte. This allows us to handle all cases except UNEQ and
11123 case GE
: return ARM_GE
;
11124 case GT
: return ARM_GT
;
11125 case LE
: return ARM_LS
;
11126 case LT
: return ARM_MI
;
11127 case NE
: return ARM_NE
;
11128 case EQ
: return ARM_EQ
;
11129 case ORDERED
: return ARM_VC
;
11130 case UNORDERED
: return ARM_VS
;
11131 case UNLT
: return ARM_LT
;
11132 case UNLE
: return ARM_LE
;
11133 case UNGT
: return ARM_HI
;
11134 case UNGE
: return ARM_PL
;
11135 /* UNEQ and LTGT do not have a representation. */
11136 case UNEQ
: /* Fall through. */
11137 case LTGT
: /* Fall through. */
11144 case NE
: return ARM_NE
;
11145 case EQ
: return ARM_EQ
;
11146 case GE
: return ARM_LE
;
11147 case GT
: return ARM_LT
;
11148 case LE
: return ARM_GE
;
11149 case LT
: return ARM_GT
;
11150 case GEU
: return ARM_LS
;
11151 case GTU
: return ARM_CC
;
11152 case LEU
: return ARM_CS
;
11153 case LTU
: return ARM_HI
;
11160 case LTU
: return ARM_CS
;
11161 case GEU
: return ARM_CC
;
11168 case NE
: return ARM_NE
;
11169 case EQ
: return ARM_EQ
;
11170 case GE
: return ARM_GE
;
11171 case GT
: return ARM_GT
;
11172 case LE
: return ARM_LE
;
11173 case LT
: return ARM_LT
;
11174 case GEU
: return ARM_CS
;
11175 case GTU
: return ARM_HI
;
11176 case LEU
: return ARM_LS
;
11177 case LTU
: return ARM_CC
;
11188 arm_final_prescan_insn (rtx insn
)
11190 /* BODY will hold the body of INSN. */
11191 rtx body
= PATTERN (insn
);
11193 /* This will be 1 if trying to repeat the trick, and things need to be
11194 reversed if it appears to fail. */
11197 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11198 taken are clobbered, even if the rtl suggests otherwise. It also
11199 means that we have to grub around within the jump expression to find
11200 out what the conditions are when the jump isn't taken. */
11201 int jump_clobbers
= 0;
11203 /* If we start with a return insn, we only succeed if we find another one. */
11204 int seeking_return
= 0;
11206 /* START_INSN will hold the insn from where we start looking. This is the
11207 first insn after the following code_label if REVERSE is true. */
11208 rtx start_insn
= insn
;
11210 /* If in state 4, check if the target branch is reached, in order to
11211 change back to state 0. */
11212 if (arm_ccfsm_state
== 4)
11214 if (insn
== arm_target_insn
)
11216 arm_target_insn
= NULL
;
11217 arm_ccfsm_state
= 0;
11222 /* If in state 3, it is possible to repeat the trick, if this insn is an
11223 unconditional branch to a label, and immediately following this branch
11224 is the previous target label which is only used once, and the label this
11225 branch jumps to is not too far off. */
11226 if (arm_ccfsm_state
== 3)
11228 if (simplejump_p (insn
))
11230 start_insn
= next_nonnote_insn (start_insn
);
11231 if (GET_CODE (start_insn
) == BARRIER
)
11233 /* XXX Isn't this always a barrier? */
11234 start_insn
= next_nonnote_insn (start_insn
);
11236 if (GET_CODE (start_insn
) == CODE_LABEL
11237 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11238 && LABEL_NUSES (start_insn
) == 1)
11243 else if (GET_CODE (body
) == RETURN
)
11245 start_insn
= next_nonnote_insn (start_insn
);
11246 if (GET_CODE (start_insn
) == BARRIER
)
11247 start_insn
= next_nonnote_insn (start_insn
);
11248 if (GET_CODE (start_insn
) == CODE_LABEL
11249 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
11250 && LABEL_NUSES (start_insn
) == 1)
11253 seeking_return
= 1;
11262 if (arm_ccfsm_state
!= 0 && !reverse
)
11264 if (GET_CODE (insn
) != JUMP_INSN
)
11267 /* This jump might be paralleled with a clobber of the condition codes
11268 the jump should always come first */
11269 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
11270 body
= XVECEXP (body
, 0, 0);
11273 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
11274 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
11277 int fail
= FALSE
, succeed
= FALSE
;
11278 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11279 int then_not_else
= TRUE
;
11280 rtx this_insn
= start_insn
, label
= 0;
11282 /* If the jump cannot be done with one instruction, we cannot
11283 conditionally execute the instruction in the inverse case. */
11284 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
11290 /* Register the insn jumped to. */
11293 if (!seeking_return
)
11294 label
= XEXP (SET_SRC (body
), 0);
11296 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
11297 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
11298 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
11300 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
11301 then_not_else
= FALSE
;
11303 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
11304 seeking_return
= 1;
11305 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
11307 seeking_return
= 1;
11308 then_not_else
= FALSE
;
11313 /* See how many insns this branch skips, and what kind of insns. If all
11314 insns are okay, and the label or unconditional branch to the same
11315 label is not too far away, succeed. */
11316 for (insns_skipped
= 0;
11317 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
11321 this_insn
= next_nonnote_insn (this_insn
);
11325 switch (GET_CODE (this_insn
))
11328 /* Succeed if it is the target label, otherwise fail since
11329 control falls in from somewhere else. */
11330 if (this_insn
== label
)
11334 arm_ccfsm_state
= 2;
11335 this_insn
= next_nonnote_insn (this_insn
);
11338 arm_ccfsm_state
= 1;
11346 /* Succeed if the following insn is the target label.
11348 If return insns are used then the last insn in a function
11349 will be a barrier. */
11350 this_insn
= next_nonnote_insn (this_insn
);
11351 if (this_insn
&& this_insn
== label
)
11355 arm_ccfsm_state
= 2;
11356 this_insn
= next_nonnote_insn (this_insn
);
11359 arm_ccfsm_state
= 1;
11367 /* The AAPCS says that conditional calls should not be
11368 used since they make interworking inefficient (the
11369 linker can't transform BL<cond> into BLX). That's
11370 only a problem if the machine has BLX. */
11377 /* Succeed if the following insn is the target label, or
11378 if the following two insns are a barrier and the
11380 this_insn
= next_nonnote_insn (this_insn
);
11381 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
11382 this_insn
= next_nonnote_insn (this_insn
);
11384 if (this_insn
&& this_insn
== label
11385 && insns_skipped
< max_insns_skipped
)
11389 arm_ccfsm_state
= 2;
11390 this_insn
= next_nonnote_insn (this_insn
);
11393 arm_ccfsm_state
= 1;
11401 /* If this is an unconditional branch to the same label, succeed.
11402 If it is to another label, do nothing. If it is conditional,
11404 /* XXX Probably, the tests for SET and the PC are
11407 scanbody
= PATTERN (this_insn
);
11408 if (GET_CODE (scanbody
) == SET
11409 && GET_CODE (SET_DEST (scanbody
)) == PC
)
11411 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
11412 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
11414 arm_ccfsm_state
= 2;
11417 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
11420 /* Fail if a conditional return is undesirable (eg on a
11421 StrongARM), but still allow this if optimizing for size. */
11422 else if (GET_CODE (scanbody
) == RETURN
11423 && !use_return_insn (TRUE
, NULL
)
11426 else if (GET_CODE (scanbody
) == RETURN
11429 arm_ccfsm_state
= 2;
11432 else if (GET_CODE (scanbody
) == PARALLEL
)
11434 switch (get_attr_conds (this_insn
))
11444 fail
= TRUE
; /* Unrecognized jump (eg epilogue). */
11449 /* Instructions using or affecting the condition codes make it
11451 scanbody
= PATTERN (this_insn
);
11452 if (!(GET_CODE (scanbody
) == SET
11453 || GET_CODE (scanbody
) == PARALLEL
)
11454 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
11457 /* A conditional cirrus instruction must be followed by
11458 a non Cirrus instruction. However, since we
11459 conditionalize instructions in this function and by
11460 the time we get here we can't add instructions
11461 (nops), because shorten_branches() has already been
11462 called, we will disable conditionalizing Cirrus
11463 instructions to be safe. */
11464 if (GET_CODE (scanbody
) != USE
11465 && GET_CODE (scanbody
) != CLOBBER
11466 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
11476 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
11477 arm_target_label
= CODE_LABEL_NUMBER (label
);
11478 else if (seeking_return
|| arm_ccfsm_state
== 2)
11480 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
11482 this_insn
= next_nonnote_insn (this_insn
);
11483 if (this_insn
&& (GET_CODE (this_insn
) == BARRIER
11484 || GET_CODE (this_insn
) == CODE_LABEL
))
11489 /* Oh, dear! we ran off the end.. give up. */
11490 recog (PATTERN (insn
), insn
, NULL
);
11491 arm_ccfsm_state
= 0;
11492 arm_target_insn
= NULL
;
11495 arm_target_insn
= this_insn
;
11504 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
11506 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
11507 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11508 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
11509 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11513 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11516 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
11520 if (reverse
|| then_not_else
)
11521 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
11524 /* Restore recog_data (getting the attributes of other insns can
11525 destroy this array, but final.c assumes that it remains intact
11526 across this call; since the insn has been recognized already we
11527 call recog direct). */
11528 recog (PATTERN (insn
), insn
, NULL
);
11532 /* Returns true if REGNO is a valid register
11533 for holding a quantity of tyoe MODE. */
11535 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
11537 if (GET_MODE_CLASS (mode
) == MODE_CC
)
11538 return regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
;
11541 /* For the Thumb we only allow values bigger than SImode in
11542 registers 0 - 6, so that there is always a second low
11543 register available to hold the upper part of the value.
11544 We probably we ought to ensure that the register is the
11545 start of an even numbered register pair. */
11546 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
11548 if (IS_CIRRUS_REGNUM (regno
))
11549 /* We have outlawed SI values in Cirrus registers because they
11550 reside in the lower 32 bits, but SF values reside in the
11551 upper 32 bits. This causes gcc all sorts of grief. We can't
11552 even split the registers into pairs because Cirrus SI values
11553 get sign extended to 64bits-- aldyh. */
11554 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
11556 if (IS_VFP_REGNUM (regno
))
11558 if (mode
== SFmode
|| mode
== SImode
)
11561 /* DFmode values are only valid in even register pairs. */
11562 if (mode
== DFmode
)
11563 return ((regno
- FIRST_VFP_REGNUM
) & 1) == 0;
11567 if (IS_IWMMXT_GR_REGNUM (regno
))
11568 return mode
== SImode
;
11570 if (IS_IWMMXT_REGNUM (regno
))
11571 return VALID_IWMMXT_REG_MODE (mode
);
11573 /* We allow any value to be stored in the general registers.
11574 Restrict doubleword quantities to even register pairs so that we can
11576 if (regno
<= LAST_ARM_REGNUM
)
11577 return !(TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0);
11579 if ( regno
== FRAME_POINTER_REGNUM
11580 || regno
== ARG_POINTER_REGNUM
)
11581 /* We only allow integers in the fake hard registers. */
11582 return GET_MODE_CLASS (mode
) == MODE_INT
;
11584 /* The only registers left are the FPA registers
11585 which we only allow to hold FP values. */
11586 return GET_MODE_CLASS (mode
) == MODE_FLOAT
11587 && regno
>= FIRST_FPA_REGNUM
11588 && regno
<= LAST_FPA_REGNUM
;
11592 arm_regno_class (int regno
)
11596 if (regno
== STACK_POINTER_REGNUM
)
11598 if (regno
== CC_REGNUM
)
11605 if ( regno
<= LAST_ARM_REGNUM
11606 || regno
== FRAME_POINTER_REGNUM
11607 || regno
== ARG_POINTER_REGNUM
)
11608 return GENERAL_REGS
;
11610 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
11613 if (IS_CIRRUS_REGNUM (regno
))
11614 return CIRRUS_REGS
;
11616 if (IS_VFP_REGNUM (regno
))
11619 if (IS_IWMMXT_REGNUM (regno
))
11620 return IWMMXT_REGS
;
11622 if (IS_IWMMXT_GR_REGNUM (regno
))
11623 return IWMMXT_GR_REGS
;
11628 /* Handle a special case when computing the offset
11629 of an argument from the frame pointer. */
11631 arm_debugger_arg_offset (int value
, rtx addr
)
11635 /* We are only interested if dbxout_parms() failed to compute the offset. */
11639 /* We can only cope with the case where the address is held in a register. */
11640 if (GET_CODE (addr
) != REG
)
11643 /* If we are using the frame pointer to point at the argument, then
11644 an offset of 0 is correct. */
11645 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
11648 /* If we are using the stack pointer to point at the
11649 argument, then an offset of 0 is correct. */
11650 if ((TARGET_THUMB
|| !frame_pointer_needed
)
11651 && REGNO (addr
) == SP_REGNUM
)
11654 /* Oh dear. The argument is pointed to by a register rather
11655 than being held in a register, or being stored at a known
11656 offset from the frame pointer. Since GDB only understands
11657 those two kinds of argument we must translate the address
11658 held in the register into an offset from the frame pointer.
11659 We do this by searching through the insns for the function
11660 looking to see where this register gets its value. If the
11661 register is initialized from the frame pointer plus an offset
11662 then we are in luck and we can continue, otherwise we give up.
11664 This code is exercised by producing debugging information
11665 for a function with arguments like this:
11667 double func (double a, double b, int c, double d) {return d;}
11669 Without this code the stab for parameter 'd' will be set to
11670 an offset of 0 from the frame pointer, rather than 8. */
11672 /* The if() statement says:
11674 If the insn is a normal instruction
11675 and if the insn is setting the value in a register
11676 and if the register being set is the register holding the address of the argument
11677 and if the address is computing by an addition
11678 that involves adding to a register
11679 which is the frame pointer
11684 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11686 if ( GET_CODE (insn
) == INSN
11687 && GET_CODE (PATTERN (insn
)) == SET
11688 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
11689 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
11690 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
11691 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11692 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
11695 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
11704 warning ("unable to compute real location of stacked parameter");
11705 value
= 8; /* XXX magic hack */
11711 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11714 if ((MASK) & insn_flags) \
11715 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
11716 BUILT_IN_MD, NULL, NULL_TREE); \
11720 struct builtin_description
11722 const unsigned int mask
;
11723 const enum insn_code icode
;
11724 const char * const name
;
11725 const enum arm_builtins code
;
11726 const enum rtx_code comparison
;
11727 const unsigned int flag
;
11730 static const struct builtin_description bdesc_2arg
[] =
11732 #define IWMMXT_BUILTIN(code, string, builtin) \
11733 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11734 ARM_BUILTIN_##builtin, 0, 0 },
11736 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
11737 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
11738 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
11739 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
11740 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
11741 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
11742 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
11743 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
11744 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
11745 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
11746 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
11747 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
11748 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
11749 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
11750 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
11751 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
11752 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
11753 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
11754 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
11755 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsm", WMULSM
)
11756 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmulum", WMULUM
)
11757 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
11758 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
11759 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
11760 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
11761 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
11762 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
11763 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
11764 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
11765 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
11766 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
11767 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
11768 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
11769 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
11770 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
11771 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
11772 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
11773 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
11774 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
11775 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
11776 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
11777 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
11778 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
11779 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
11780 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
11781 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
11782 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
11783 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
11784 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
11785 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
11786 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
11787 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
11788 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
11789 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
11790 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
11791 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
11792 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
11793 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
11795 #define IWMMXT_BUILTIN2(code, builtin) \
11796 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11798 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
11799 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
11800 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
11801 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
11802 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
11803 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
11804 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
11805 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
11806 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
11807 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
11808 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
11809 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
11810 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
11811 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
11812 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
11813 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
11814 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
11815 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt
, WSRLDI
)
11816 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
11817 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
11818 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
11819 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
11820 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
11821 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt
, WSRADI
)
11822 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
11823 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
11824 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
11825 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
11826 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
11827 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
11828 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
11829 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
11832 static const struct builtin_description bdesc_1arg
[] =
11834 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
11835 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
11836 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
11837 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
11838 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
11839 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
11840 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
11841 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
11842 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
11843 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
11844 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
11845 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
11846 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
11847 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
11848 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
11849 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
11850 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
11851 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
11854 /* Set up all the iWMMXt builtins. This is
11855 not called if TARGET_IWMMXT is zero. */
11858 arm_init_iwmmxt_builtins (void)
11860 const struct builtin_description
* d
;
11862 tree endlink
= void_list_node
;
11864 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
11865 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
11866 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
11869 = build_function_type (integer_type_node
,
11870 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
11871 tree v8qi_ftype_v8qi_v8qi_int
11872 = build_function_type (V8QI_type_node
,
11873 tree_cons (NULL_TREE
, V8QI_type_node
,
11874 tree_cons (NULL_TREE
, V8QI_type_node
,
11875 tree_cons (NULL_TREE
,
11878 tree v4hi_ftype_v4hi_int
11879 = build_function_type (V4HI_type_node
,
11880 tree_cons (NULL_TREE
, V4HI_type_node
,
11881 tree_cons (NULL_TREE
, integer_type_node
,
11883 tree v2si_ftype_v2si_int
11884 = build_function_type (V2SI_type_node
,
11885 tree_cons (NULL_TREE
, V2SI_type_node
,
11886 tree_cons (NULL_TREE
, integer_type_node
,
11888 tree v2si_ftype_di_di
11889 = build_function_type (V2SI_type_node
,
11890 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11891 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11893 tree di_ftype_di_int
11894 = build_function_type (long_long_integer_type_node
,
11895 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11896 tree_cons (NULL_TREE
, integer_type_node
,
11898 tree di_ftype_di_int_int
11899 = build_function_type (long_long_integer_type_node
,
11900 tree_cons (NULL_TREE
, long_long_integer_type_node
,
11901 tree_cons (NULL_TREE
, integer_type_node
,
11902 tree_cons (NULL_TREE
,
11905 tree int_ftype_v8qi
11906 = build_function_type (integer_type_node
,
11907 tree_cons (NULL_TREE
, V8QI_type_node
,
11909 tree int_ftype_v4hi
11910 = build_function_type (integer_type_node
,
11911 tree_cons (NULL_TREE
, V4HI_type_node
,
11913 tree int_ftype_v2si
11914 = build_function_type (integer_type_node
,
11915 tree_cons (NULL_TREE
, V2SI_type_node
,
11917 tree int_ftype_v8qi_int
11918 = build_function_type (integer_type_node
,
11919 tree_cons (NULL_TREE
, V8QI_type_node
,
11920 tree_cons (NULL_TREE
, integer_type_node
,
11922 tree int_ftype_v4hi_int
11923 = build_function_type (integer_type_node
,
11924 tree_cons (NULL_TREE
, V4HI_type_node
,
11925 tree_cons (NULL_TREE
, integer_type_node
,
11927 tree int_ftype_v2si_int
11928 = build_function_type (integer_type_node
,
11929 tree_cons (NULL_TREE
, V2SI_type_node
,
11930 tree_cons (NULL_TREE
, integer_type_node
,
11932 tree v8qi_ftype_v8qi_int_int
11933 = build_function_type (V8QI_type_node
,
11934 tree_cons (NULL_TREE
, V8QI_type_node
,
11935 tree_cons (NULL_TREE
, integer_type_node
,
11936 tree_cons (NULL_TREE
,
11939 tree v4hi_ftype_v4hi_int_int
11940 = build_function_type (V4HI_type_node
,
11941 tree_cons (NULL_TREE
, V4HI_type_node
,
11942 tree_cons (NULL_TREE
, integer_type_node
,
11943 tree_cons (NULL_TREE
,
11946 tree v2si_ftype_v2si_int_int
11947 = build_function_type (V2SI_type_node
,
11948 tree_cons (NULL_TREE
, V2SI_type_node
,
11949 tree_cons (NULL_TREE
, integer_type_node
,
11950 tree_cons (NULL_TREE
,
11953 /* Miscellaneous. */
11954 tree v8qi_ftype_v4hi_v4hi
11955 = build_function_type (V8QI_type_node
,
11956 tree_cons (NULL_TREE
, V4HI_type_node
,
11957 tree_cons (NULL_TREE
, V4HI_type_node
,
11959 tree v4hi_ftype_v2si_v2si
11960 = build_function_type (V4HI_type_node
,
11961 tree_cons (NULL_TREE
, V2SI_type_node
,
11962 tree_cons (NULL_TREE
, V2SI_type_node
,
11964 tree v2si_ftype_v4hi_v4hi
11965 = build_function_type (V2SI_type_node
,
11966 tree_cons (NULL_TREE
, V4HI_type_node
,
11967 tree_cons (NULL_TREE
, V4HI_type_node
,
11969 tree v2si_ftype_v8qi_v8qi
11970 = build_function_type (V2SI_type_node
,
11971 tree_cons (NULL_TREE
, V8QI_type_node
,
11972 tree_cons (NULL_TREE
, V8QI_type_node
,
11974 tree v4hi_ftype_v4hi_di
11975 = build_function_type (V4HI_type_node
,
11976 tree_cons (NULL_TREE
, V4HI_type_node
,
11977 tree_cons (NULL_TREE
,
11978 long_long_integer_type_node
,
11980 tree v2si_ftype_v2si_di
11981 = build_function_type (V2SI_type_node
,
11982 tree_cons (NULL_TREE
, V2SI_type_node
,
11983 tree_cons (NULL_TREE
,
11984 long_long_integer_type_node
,
11986 tree void_ftype_int_int
11987 = build_function_type (void_type_node
,
11988 tree_cons (NULL_TREE
, integer_type_node
,
11989 tree_cons (NULL_TREE
, integer_type_node
,
11992 = build_function_type (long_long_unsigned_type_node
, endlink
);
11994 = build_function_type (long_long_integer_type_node
,
11995 tree_cons (NULL_TREE
, V8QI_type_node
,
11998 = build_function_type (long_long_integer_type_node
,
11999 tree_cons (NULL_TREE
, V4HI_type_node
,
12002 = build_function_type (long_long_integer_type_node
,
12003 tree_cons (NULL_TREE
, V2SI_type_node
,
12005 tree v2si_ftype_v4hi
12006 = build_function_type (V2SI_type_node
,
12007 tree_cons (NULL_TREE
, V4HI_type_node
,
12009 tree v4hi_ftype_v8qi
12010 = build_function_type (V4HI_type_node
,
12011 tree_cons (NULL_TREE
, V8QI_type_node
,
12014 tree di_ftype_di_v4hi_v4hi
12015 = build_function_type (long_long_unsigned_type_node
,
12016 tree_cons (NULL_TREE
,
12017 long_long_unsigned_type_node
,
12018 tree_cons (NULL_TREE
, V4HI_type_node
,
12019 tree_cons (NULL_TREE
,
12023 tree di_ftype_v4hi_v4hi
12024 = build_function_type (long_long_unsigned_type_node
,
12025 tree_cons (NULL_TREE
, V4HI_type_node
,
12026 tree_cons (NULL_TREE
, V4HI_type_node
,
12029 /* Normal vector binops. */
12030 tree v8qi_ftype_v8qi_v8qi
12031 = build_function_type (V8QI_type_node
,
12032 tree_cons (NULL_TREE
, V8QI_type_node
,
12033 tree_cons (NULL_TREE
, V8QI_type_node
,
12035 tree v4hi_ftype_v4hi_v4hi
12036 = build_function_type (V4HI_type_node
,
12037 tree_cons (NULL_TREE
, V4HI_type_node
,
12038 tree_cons (NULL_TREE
, V4HI_type_node
,
12040 tree v2si_ftype_v2si_v2si
12041 = build_function_type (V2SI_type_node
,
12042 tree_cons (NULL_TREE
, V2SI_type_node
,
12043 tree_cons (NULL_TREE
, V2SI_type_node
,
12045 tree di_ftype_di_di
12046 = build_function_type (long_long_unsigned_type_node
,
12047 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
12048 tree_cons (NULL_TREE
,
12049 long_long_unsigned_type_node
,
12052 /* Add all builtins that are more or less simple operations on two
12054 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12056 /* Use one of the operands; the target can have a different mode for
12057 mask-generating compares. */
12058 enum machine_mode mode
;
12064 mode
= insn_data
[d
->icode
].operand
[1].mode
;
12069 type
= v8qi_ftype_v8qi_v8qi
;
12072 type
= v4hi_ftype_v4hi_v4hi
;
12075 type
= v2si_ftype_v2si_v2si
;
12078 type
= di_ftype_di_di
;
12085 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
12088 /* Add the remaining MMX insns with somewhat more complicated types. */
12089 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
12090 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
12091 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
12093 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
12094 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
12095 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
12096 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
12097 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
12098 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
12100 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
12101 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
12102 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
12103 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
12104 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
12105 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
12107 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
12108 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
12109 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
12110 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
12111 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
12112 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
12114 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
12115 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
12116 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
12117 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
12118 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
12119 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
12121 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
12123 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
12124 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
12125 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
12126 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
12128 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
12129 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
12130 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
12131 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
12132 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
12133 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
12134 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
12135 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
12136 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
12138 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
12139 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
12140 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
12142 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
12143 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
12144 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
12146 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
12147 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
12148 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
12149 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
12150 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
12151 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
12153 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
12154 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
12155 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
12156 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
12157 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
12158 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
12159 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
12160 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
12161 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
12162 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
12163 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
12164 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
12166 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
12167 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
12168 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
12169 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
12171 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
12172 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
12173 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
12174 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
12175 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
12176 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
12177 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
12181 arm_init_builtins (void)
12183 if (TARGET_REALLY_IWMMXT
)
12184 arm_init_iwmmxt_builtins ();
12187 /* Errors in the source file can cause expand_expr to return const0_rtx
12188 where we expect a vector. To avoid crashing, use one of the vector
12189 clear instructions. */
12192 safe_vector_operand (rtx x
, enum machine_mode mode
)
12194 if (x
!= const0_rtx
)
12196 x
= gen_reg_rtx (mode
);
12198 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
12199 : gen_rtx_SUBREG (DImode
, x
, 0)));
12203 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12206 arm_expand_binop_builtin (enum insn_code icode
,
12207 tree arglist
, rtx target
)
12210 tree arg0
= TREE_VALUE (arglist
);
12211 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12212 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12213 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12214 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12215 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12216 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12218 if (VECTOR_MODE_P (mode0
))
12219 op0
= safe_vector_operand (op0
, mode0
);
12220 if (VECTOR_MODE_P (mode1
))
12221 op1
= safe_vector_operand (op1
, mode1
);
12224 || GET_MODE (target
) != tmode
12225 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12226 target
= gen_reg_rtx (tmode
);
12228 /* In case the insn wants input operands in modes different from
12229 the result, abort. */
12230 if (GET_MODE (op0
) != mode0
|| GET_MODE (op1
) != mode1
)
12233 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12234 op0
= copy_to_mode_reg (mode0
, op0
);
12235 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12236 op1
= copy_to_mode_reg (mode1
, op1
);
12238 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12245 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12248 arm_expand_unop_builtin (enum insn_code icode
,
12249 tree arglist
, rtx target
, int do_load
)
12252 tree arg0
= TREE_VALUE (arglist
);
12253 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12254 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12255 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12258 || GET_MODE (target
) != tmode
12259 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12260 target
= gen_reg_rtx (tmode
);
12262 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12265 if (VECTOR_MODE_P (mode0
))
12266 op0
= safe_vector_operand (op0
, mode0
);
12268 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12269 op0
= copy_to_mode_reg (mode0
, op0
);
12272 pat
= GEN_FCN (icode
) (target
, op0
);
12279 /* Expand an expression EXP that calls a built-in function,
12280 with result going to TARGET if that's convenient
12281 (and in mode MODE if that's convenient).
12282 SUBTARGET may be used as the target for computing one of EXP's operands.
12283 IGNORE is nonzero if the value is to be ignored. */
12286 arm_expand_builtin (tree exp
,
12288 rtx subtarget ATTRIBUTE_UNUSED
,
12289 enum machine_mode mode ATTRIBUTE_UNUSED
,
12290 int ignore ATTRIBUTE_UNUSED
)
12292 const struct builtin_description
* d
;
12293 enum insn_code icode
;
12294 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
12295 tree arglist
= TREE_OPERAND (exp
, 1);
12303 int fcode
= DECL_FUNCTION_CODE (fndecl
);
12305 enum machine_mode tmode
;
12306 enum machine_mode mode0
;
12307 enum machine_mode mode1
;
12308 enum machine_mode mode2
;
12312 case ARM_BUILTIN_TEXTRMSB
:
12313 case ARM_BUILTIN_TEXTRMUB
:
12314 case ARM_BUILTIN_TEXTRMSH
:
12315 case ARM_BUILTIN_TEXTRMUH
:
12316 case ARM_BUILTIN_TEXTRMSW
:
12317 case ARM_BUILTIN_TEXTRMUW
:
12318 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
12319 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
12320 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
12321 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
12322 : CODE_FOR_iwmmxt_textrmw
);
12324 arg0
= TREE_VALUE (arglist
);
12325 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12326 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12327 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12328 tmode
= insn_data
[icode
].operand
[0].mode
;
12329 mode0
= insn_data
[icode
].operand
[1].mode
;
12330 mode1
= insn_data
[icode
].operand
[2].mode
;
12332 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12333 op0
= copy_to_mode_reg (mode0
, op0
);
12334 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12336 /* @@@ better error message */
12337 error ("selector must be an immediate");
12338 return gen_reg_rtx (tmode
);
12341 || GET_MODE (target
) != tmode
12342 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12343 target
= gen_reg_rtx (tmode
);
12344 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12350 case ARM_BUILTIN_TINSRB
:
12351 case ARM_BUILTIN_TINSRH
:
12352 case ARM_BUILTIN_TINSRW
:
12353 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
12354 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
12355 : CODE_FOR_iwmmxt_tinsrw
);
12356 arg0
= TREE_VALUE (arglist
);
12357 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12358 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12359 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12360 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12361 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12362 tmode
= insn_data
[icode
].operand
[0].mode
;
12363 mode0
= insn_data
[icode
].operand
[1].mode
;
12364 mode1
= insn_data
[icode
].operand
[2].mode
;
12365 mode2
= insn_data
[icode
].operand
[3].mode
;
12367 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12368 op0
= copy_to_mode_reg (mode0
, op0
);
12369 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12370 op1
= copy_to_mode_reg (mode1
, op1
);
12371 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12373 /* @@@ better error message */
12374 error ("selector must be an immediate");
12378 || GET_MODE (target
) != tmode
12379 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12380 target
= gen_reg_rtx (tmode
);
12381 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12387 case ARM_BUILTIN_SETWCX
:
12388 arg0
= TREE_VALUE (arglist
);
12389 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12390 op0
= force_reg (SImode
, expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
12391 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12392 emit_insn (gen_iwmmxt_tmcr (op1
, op0
));
12395 case ARM_BUILTIN_GETWCX
:
12396 arg0
= TREE_VALUE (arglist
);
12397 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12398 target
= gen_reg_rtx (SImode
);
12399 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
12402 case ARM_BUILTIN_WSHUFH
:
12403 icode
= CODE_FOR_iwmmxt_wshufh
;
12404 arg0
= TREE_VALUE (arglist
);
12405 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12406 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12407 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12408 tmode
= insn_data
[icode
].operand
[0].mode
;
12409 mode1
= insn_data
[icode
].operand
[1].mode
;
12410 mode2
= insn_data
[icode
].operand
[2].mode
;
12412 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
12413 op0
= copy_to_mode_reg (mode1
, op0
);
12414 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
12416 /* @@@ better error message */
12417 error ("mask must be an immediate");
12421 || GET_MODE (target
) != tmode
12422 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12423 target
= gen_reg_rtx (tmode
);
12424 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12430 case ARM_BUILTIN_WSADB
:
12431 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
12432 case ARM_BUILTIN_WSADH
:
12433 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
12434 case ARM_BUILTIN_WSADBZ
:
12435 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
12436 case ARM_BUILTIN_WSADHZ
:
12437 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
12439 /* Several three-argument builtins. */
12440 case ARM_BUILTIN_WMACS
:
12441 case ARM_BUILTIN_WMACU
:
12442 case ARM_BUILTIN_WALIGN
:
12443 case ARM_BUILTIN_TMIA
:
12444 case ARM_BUILTIN_TMIAPH
:
12445 case ARM_BUILTIN_TMIATT
:
12446 case ARM_BUILTIN_TMIATB
:
12447 case ARM_BUILTIN_TMIABT
:
12448 case ARM_BUILTIN_TMIABB
:
12449 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
12450 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
12451 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
12452 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
12453 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
12454 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
12455 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
12456 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
12457 : CODE_FOR_iwmmxt_walign
);
12458 arg0
= TREE_VALUE (arglist
);
12459 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12460 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
12461 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12462 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12463 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
12464 tmode
= insn_data
[icode
].operand
[0].mode
;
12465 mode0
= insn_data
[icode
].operand
[1].mode
;
12466 mode1
= insn_data
[icode
].operand
[2].mode
;
12467 mode2
= insn_data
[icode
].operand
[3].mode
;
12469 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12470 op0
= copy_to_mode_reg (mode0
, op0
);
12471 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12472 op1
= copy_to_mode_reg (mode1
, op1
);
12473 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12474 op2
= copy_to_mode_reg (mode2
, op2
);
12476 || GET_MODE (target
) != tmode
12477 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12478 target
= gen_reg_rtx (tmode
);
12479 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12485 case ARM_BUILTIN_WZERO
:
12486 target
= gen_reg_rtx (DImode
);
12487 emit_insn (gen_iwmmxt_clrdi (target
));
12494 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12495 if (d
->code
== (const enum arm_builtins
) fcode
)
12496 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
12498 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12499 if (d
->code
== (const enum arm_builtins
) fcode
)
12500 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
12502 /* @@@ Should really do something sensible here. */
12506 /* Recursively search through all of the blocks in a function
12507 checking to see if any of the variables created in that
12508 function match the RTX called 'orig'. If they do then
12509 replace them with the RTX called 'new'. */
12511 replace_symbols_in_block (tree block
, rtx orig
, rtx
new)
12513 for (; block
; block
= BLOCK_CHAIN (block
))
12517 if (!TREE_USED (block
))
12520 for (sym
= BLOCK_VARS (block
); sym
; sym
= TREE_CHAIN (sym
))
12522 if ( (DECL_NAME (sym
) == 0 && TREE_CODE (sym
) != TYPE_DECL
)
12523 || DECL_IGNORED_P (sym
)
12524 || TREE_CODE (sym
) != VAR_DECL
12525 || DECL_EXTERNAL (sym
)
12526 || !rtx_equal_p (DECL_RTL (sym
), orig
)
12530 SET_DECL_RTL (sym
, new);
12533 replace_symbols_in_block (BLOCK_SUBBLOCKS (block
), orig
, new);
12537 /* Return the number (counting from 0) of
12538 the least significant set bit in MASK. */
12541 number_of_first_bit_set (int mask
)
12546 (mask
& (1 << bit
)) == 0;
12553 /* Generate code to return from a thumb function.
12554 If 'reg_containing_return_addr' is -1, then the return address is
12555 actually on the stack, at the stack pointer. */
12557 thumb_exit (FILE *f
, int reg_containing_return_addr
)
12559 unsigned regs_available_for_popping
;
12560 unsigned regs_to_pop
;
12562 unsigned available
;
12566 int restore_a4
= FALSE
;
12568 /* Compute the registers we need to pop. */
12572 if (reg_containing_return_addr
== -1)
12574 regs_to_pop
|= 1 << LR_REGNUM
;
12578 if (TARGET_BACKTRACE
)
12580 /* Restore the (ARM) frame pointer and stack pointer. */
12581 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
12585 /* If there is nothing to pop then just emit the BX instruction and
12587 if (pops_needed
== 0)
12589 if (current_function_calls_eh_return
)
12590 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
12592 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12595 /* Otherwise if we are not supporting interworking and we have not created
12596 a backtrace structure and the function was not entered in ARM mode then
12597 just pop the return address straight into the PC. */
12598 else if (!TARGET_INTERWORK
12599 && !TARGET_BACKTRACE
12600 && !is_called_in_ARM_mode (current_function_decl
)
12601 && !current_function_calls_eh_return
)
12603 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
12607 /* Find out how many of the (return) argument registers we can corrupt. */
12608 regs_available_for_popping
= 0;
12610 /* If returning via __builtin_eh_return, the bottom three registers
12611 all contain information needed for the return. */
12612 if (current_function_calls_eh_return
)
12616 /* If we can deduce the registers used from the function's
12617 return value. This is more reliable that examining
12618 regs_ever_live[] because that will be set if the register is
12619 ever used in the function, not just if the register is used
12620 to hold a return value. */
12622 if (current_function_return_rtx
!= 0)
12623 mode
= GET_MODE (current_function_return_rtx
);
12625 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
12627 size
= GET_MODE_SIZE (mode
);
12631 /* In a void function we can use any argument register.
12632 In a function that returns a structure on the stack
12633 we can use the second and third argument registers. */
12634 if (mode
== VOIDmode
)
12635 regs_available_for_popping
=
12636 (1 << ARG_REGISTER (1))
12637 | (1 << ARG_REGISTER (2))
12638 | (1 << ARG_REGISTER (3));
12640 regs_available_for_popping
=
12641 (1 << ARG_REGISTER (2))
12642 | (1 << ARG_REGISTER (3));
12644 else if (size
<= 4)
12645 regs_available_for_popping
=
12646 (1 << ARG_REGISTER (2))
12647 | (1 << ARG_REGISTER (3));
12648 else if (size
<= 8)
12649 regs_available_for_popping
=
12650 (1 << ARG_REGISTER (3));
12653 /* Match registers to be popped with registers into which we pop them. */
12654 for (available
= regs_available_for_popping
,
12655 required
= regs_to_pop
;
12656 required
!= 0 && available
!= 0;
12657 available
&= ~(available
& - available
),
12658 required
&= ~(required
& - required
))
12661 /* If we have any popping registers left over, remove them. */
12663 regs_available_for_popping
&= ~available
;
12665 /* Otherwise if we need another popping register we can use
12666 the fourth argument register. */
12667 else if (pops_needed
)
12669 /* If we have not found any free argument registers and
12670 reg a4 contains the return address, we must move it. */
12671 if (regs_available_for_popping
== 0
12672 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
12674 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
12675 reg_containing_return_addr
= LR_REGNUM
;
12677 else if (size
> 12)
12679 /* Register a4 is being used to hold part of the return value,
12680 but we have dire need of a free, low register. */
12683 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
12686 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
12688 /* The fourth argument register is available. */
12689 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
12695 /* Pop as many registers as we can. */
12696 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12697 regs_available_for_popping
);
12699 /* Process the registers we popped. */
12700 if (reg_containing_return_addr
== -1)
12702 /* The return address was popped into the lowest numbered register. */
12703 regs_to_pop
&= ~(1 << LR_REGNUM
);
12705 reg_containing_return_addr
=
12706 number_of_first_bit_set (regs_available_for_popping
);
12708 /* Remove this register for the mask of available registers, so that
12709 the return address will not be corrupted by further pops. */
12710 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
12713 /* If we popped other registers then handle them here. */
12714 if (regs_available_for_popping
)
12718 /* Work out which register currently contains the frame pointer. */
12719 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
12721 /* Move it into the correct place. */
12722 asm_fprintf (f
, "\tmov\t%r, %r\n",
12723 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
12725 /* (Temporarily) remove it from the mask of popped registers. */
12726 regs_available_for_popping
&= ~(1 << frame_pointer
);
12727 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
12729 if (regs_available_for_popping
)
12733 /* We popped the stack pointer as well,
12734 find the register that contains it. */
12735 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
12737 /* Move it into the stack register. */
12738 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
12740 /* At this point we have popped all necessary registers, so
12741 do not worry about restoring regs_available_for_popping
12742 to its correct value:
12744 assert (pops_needed == 0)
12745 assert (regs_available_for_popping == (1 << frame_pointer))
12746 assert (regs_to_pop == (1 << STACK_POINTER)) */
12750 /* Since we have just move the popped value into the frame
12751 pointer, the popping register is available for reuse, and
12752 we know that we still have the stack pointer left to pop. */
12753 regs_available_for_popping
|= (1 << frame_pointer
);
12757 /* If we still have registers left on the stack, but we no longer have
12758 any registers into which we can pop them, then we must move the return
12759 address into the link register and make available the register that
12761 if (regs_available_for_popping
== 0 && pops_needed
> 0)
12763 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
12765 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
12766 reg_containing_return_addr
);
12768 reg_containing_return_addr
= LR_REGNUM
;
12771 /* If we have registers left on the stack then pop some more.
12772 We know that at most we will want to pop FP and SP. */
12773 if (pops_needed
> 0)
12778 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12779 regs_available_for_popping
);
12781 /* We have popped either FP or SP.
12782 Move whichever one it is into the correct register. */
12783 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
12784 move_to
= number_of_first_bit_set (regs_to_pop
);
12786 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
12788 regs_to_pop
&= ~(1 << move_to
);
12793 /* If we still have not popped everything then we must have only
12794 had one register available to us and we are now popping the SP. */
12795 if (pops_needed
> 0)
12799 thumb_pushpop (f
, regs_available_for_popping
, FALSE
, NULL
,
12800 regs_available_for_popping
);
12802 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
12804 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
12806 assert (regs_to_pop == (1 << STACK_POINTER))
12807 assert (pops_needed == 1)
12811 /* If necessary restore the a4 register. */
12814 if (reg_containing_return_addr
!= LR_REGNUM
)
12816 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
12817 reg_containing_return_addr
= LR_REGNUM
;
12820 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
12823 if (current_function_calls_eh_return
)
12824 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
12826 /* Return to caller. */
12827 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
12830 /* Emit code to push or pop registers to or from the stack. F is the
12831 assembly file. MASK is the registers to push or pop. PUSH is
12832 nonzero if we should push, and zero if we should pop. For debugging
12833 output, if pushing, adjust CFA_OFFSET by the amount of space added
12834 to the stack. REAL_REGS should have the same number of bits set as
12835 MASK, and will be used instead (in the same order) to describe which
12836 registers were saved - this is used to mark the save slots when we
12837 push high registers after moving them to low registers. */
12839 thumb_pushpop (FILE *f
, int mask
, int push
, int *cfa_offset
, int real_regs
)
12842 int lo_mask
= mask
& 0xFF;
12843 int pushed_words
= 0;
12845 if (lo_mask
== 0 && !push
&& (mask
& (1 << PC_REGNUM
)))
12847 /* Special case. Do not generate a POP PC statement here, do it in
12849 thumb_exit (f
, -1);
12853 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
12855 /* Look at the low registers first. */
12856 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
12860 asm_fprintf (f
, "%r", regno
);
12862 if ((lo_mask
& ~1) != 0)
12869 if (push
&& (mask
& (1 << LR_REGNUM
)))
12871 /* Catch pushing the LR. */
12875 asm_fprintf (f
, "%r", LR_REGNUM
);
12879 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
12881 /* Catch popping the PC. */
12882 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
12883 || current_function_calls_eh_return
)
12885 /* The PC is never poped directly, instead
12886 it is popped into r3 and then BX is used. */
12887 fprintf (f
, "}\n");
12889 thumb_exit (f
, -1);
12898 asm_fprintf (f
, "%r", PC_REGNUM
);
12902 fprintf (f
, "}\n");
12904 if (push
&& pushed_words
&& dwarf2out_do_frame ())
12906 char *l
= dwarf2out_cfi_label ();
12907 int pushed_mask
= real_regs
;
12909 *cfa_offset
+= pushed_words
* 4;
12910 dwarf2out_def_cfa (l
, SP_REGNUM
, *cfa_offset
);
12913 pushed_mask
= real_regs
;
12914 for (regno
= 0; regno
<= 14; regno
++, pushed_mask
>>= 1)
12916 if (pushed_mask
& 1)
12917 dwarf2out_reg_save (l
, regno
, 4 * pushed_words
++ - *cfa_offset
);
12923 thumb_final_prescan_insn (rtx insn
)
12925 if (flag_print_asm_name
)
12926 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
12927 INSN_ADDRESSES (INSN_UID (insn
)));
12931 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
12933 unsigned HOST_WIDE_INT mask
= 0xff;
12936 if (val
== 0) /* XXX */
12939 for (i
= 0; i
< 25; i
++)
12940 if ((val
& (mask
<< i
)) == val
)
12946 /* Returns nonzero if the current function contains,
12947 or might contain a far jump. */
12949 thumb_far_jump_used_p (void)
12953 /* This test is only important for leaf functions. */
12954 /* assert (!leaf_function_p ()); */
12956 /* If we have already decided that far jumps may be used,
12957 do not bother checking again, and always return true even if
12958 it turns out that they are not being used. Once we have made
12959 the decision that far jumps are present (and that hence the link
12960 register will be pushed onto the stack) we cannot go back on it. */
12961 if (cfun
->machine
->far_jump_used
)
12964 /* If this function is not being called from the prologue/epilogue
12965 generation code then it must be being called from the
12966 INITIAL_ELIMINATION_OFFSET macro. */
12967 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
12969 /* In this case we know that we are being asked about the elimination
12970 of the arg pointer register. If that register is not being used,
12971 then there are no arguments on the stack, and we do not have to
12972 worry that a far jump might force the prologue to push the link
12973 register, changing the stack offsets. In this case we can just
12974 return false, since the presence of far jumps in the function will
12975 not affect stack offsets.
12977 If the arg pointer is live (or if it was live, but has now been
12978 eliminated and so set to dead) then we do have to test to see if
12979 the function might contain a far jump. This test can lead to some
12980 false negatives, since before reload is completed, then length of
12981 branch instructions is not known, so gcc defaults to returning their
12982 longest length, which in turn sets the far jump attribute to true.
12984 A false negative will not result in bad code being generated, but it
12985 will result in a needless push and pop of the link register. We
12986 hope that this does not occur too often.
12988 If we need doubleword stack alignment this could affect the other
12989 elimination offsets so we can't risk getting it wrong. */
12990 if (regs_ever_live
[ARG_POINTER_REGNUM
])
12991 cfun
->machine
->arg_pointer_live
= 1;
12992 else if (!cfun
->machine
->arg_pointer_live
)
12996 /* Check to see if the function contains a branch
12997 insn with the far jump attribute set. */
12998 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13000 if (GET_CODE (insn
) == JUMP_INSN
13001 /* Ignore tablejump patterns. */
13002 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
13003 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
13004 && get_attr_far_jump (insn
) == FAR_JUMP_YES
13007 /* Record the fact that we have decided that
13008 the function does use far jumps. */
13009 cfun
->machine
->far_jump_used
= 1;
13017 /* Return nonzero if FUNC must be entered in ARM mode. */
13019 is_called_in_ARM_mode (tree func
)
13021 if (TREE_CODE (func
) != FUNCTION_DECL
)
13024 /* Ignore the problem about functions whoes address is taken. */
13025 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
13029 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
13035 /* The bits which aren't usefully expanded as rtl. */
13037 thumb_unexpanded_epilogue (void)
13040 int live_regs_mask
= 0;
13041 int high_regs_pushed
= 0;
13042 int had_to_push_lr
;
13044 if (return_used_this_function
)
13047 if (IS_NAKED (arm_current_func_type ()))
13050 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13051 if (THUMB_REG_PUSHED_P (regno
))
13052 live_regs_mask
|= 1 << regno
;
13054 for (regno
= 8; regno
< 13; regno
++)
13055 if (THUMB_REG_PUSHED_P (regno
))
13056 high_regs_pushed
++;
13058 /* The prolog may have pushed some high registers to use as
13059 work registers. eg the testsuite file:
13060 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
13061 compiles to produce:
13062 push {r4, r5, r6, r7, lr}
13066 as part of the prolog. We have to undo that pushing here. */
13068 if (high_regs_pushed
)
13070 int mask
= live_regs_mask
;
13075 /* If we can deduce the registers used from the function's return value.
13076 This is more reliable that examining regs_ever_live[] because that
13077 will be set if the register is ever used in the function, not just if
13078 the register is used to hold a return value. */
13080 if (current_function_return_rtx
!= 0)
13081 mode
= GET_MODE (current_function_return_rtx
);
13083 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
13085 size
= GET_MODE_SIZE (mode
);
13087 /* Unless we are returning a type of size > 12 register r3 is
13093 /* Oh dear! We have no low registers into which we can pop
13096 ("no low registers available for popping high registers");
13098 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
13099 if (THUMB_REG_PUSHED_P (next_hi_reg
))
13102 while (high_regs_pushed
)
13104 /* Find lo register(s) into which the high register(s) can
13106 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13108 if (mask
& (1 << regno
))
13109 high_regs_pushed
--;
13110 if (high_regs_pushed
== 0)
13114 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
13116 /* Pop the values into the low register(s). */
13117 thumb_pushpop (asm_out_file
, mask
, 0, NULL
, mask
);
13119 /* Move the value(s) into the high registers. */
13120 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13122 if (mask
& (1 << regno
))
13124 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
13127 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
13128 if (THUMB_REG_PUSHED_P (next_hi_reg
))
13135 had_to_push_lr
= (live_regs_mask
|| thumb_force_lr_save ());
13137 if (TARGET_BACKTRACE
13138 && ((live_regs_mask
& 0xFF) == 0)
13139 && regs_ever_live
[LAST_ARG_REGNUM
] != 0)
13141 /* The stack backtrace structure creation code had to
13142 push R7 in order to get a work register, so we pop
13144 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
13147 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
13150 && !is_called_in_ARM_mode (current_function_decl
))
13151 live_regs_mask
|= 1 << PC_REGNUM
;
13153 /* Either no argument registers were pushed or a backtrace
13154 structure was created which includes an adjusted stack
13155 pointer, so just pop everything. */
13156 if (live_regs_mask
)
13157 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13160 /* We have either just popped the return address into the
13161 PC or it is was kept in LR for the entire function or
13162 it is still on the stack because we do not want to
13163 return by doing a pop {pc}. */
13164 if ((live_regs_mask
& (1 << PC_REGNUM
)) == 0)
13165 thumb_exit (asm_out_file
,
13167 && is_called_in_ARM_mode (current_function_decl
)) ?
13172 /* Pop everything but the return address. */
13173 live_regs_mask
&= ~(1 << PC_REGNUM
);
13175 if (live_regs_mask
)
13176 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
, NULL
,
13179 if (had_to_push_lr
)
13180 /* Get the return address into a temporary register. */
13181 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0, NULL
,
13182 1 << LAST_ARG_REGNUM
);
13184 /* Remove the argument registers that were pushed onto the stack. */
13185 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
13186 SP_REGNUM
, SP_REGNUM
,
13187 current_function_pretend_args_size
);
13189 thumb_exit (asm_out_file
,
13190 had_to_push_lr
? LAST_ARG_REGNUM
: LR_REGNUM
);
13196 /* Functions to save and restore machine-specific function data. */
13197 static struct machine_function
*
13198 arm_init_machine_status (void)
13200 struct machine_function
*machine
;
13201 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
13203 #if ARM_FT_UNKNOWN != 0
13204 machine
->func_type
= ARM_FT_UNKNOWN
;
13209 /* Return an RTX indicating where the return address to the
13210 calling function can be found. */
13212 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
13217 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
13220 /* Do anything needed before RTL is emitted for each function. */
13222 arm_init_expanders (void)
13224 /* Arrange to initialize and mark the machine per-function status. */
13225 init_machine_status
= arm_init_machine_status
;
13227 /* This is to stop the combine pass optimizing away the alignment
13228 adjustment of va_arg. */
13229 /* ??? It is claimed that this should not be necessary. */
13231 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
13235 /* Like arm_compute_initial_elimination offset. Simpler because
13236 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
13239 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
13241 arm_stack_offsets
*offsets
;
13243 offsets
= arm_get_frame_offsets ();
13247 case ARG_POINTER_REGNUM
:
13250 case STACK_POINTER_REGNUM
:
13251 return offsets
->outgoing_args
- offsets
->saved_args
;
13253 case FRAME_POINTER_REGNUM
:
13254 return offsets
->soft_frame
- offsets
->saved_args
;
13256 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13257 case ARM_HARD_FRAME_POINTER_REGNUM
:
13258 return offsets
->saved_regs
- offsets
->saved_args
;
13265 case FRAME_POINTER_REGNUM
:
13268 case STACK_POINTER_REGNUM
:
13269 return offsets
->outgoing_args
- offsets
->soft_frame
;
13271 case THUMB_HARD_FRAME_POINTER_REGNUM
:
13272 case ARM_HARD_FRAME_POINTER_REGNUM
:
13273 return offsets
->saved_regs
- offsets
->soft_frame
;
13286 /* Generate the rest of a function's prologue. */
13288 thumb_expand_prologue (void)
13292 HOST_WIDE_INT amount
;
13293 arm_stack_offsets
*offsets
;
13294 unsigned long func_type
;
13297 func_type
= arm_current_func_type ();
13299 /* Naked functions don't have prologues. */
13300 if (IS_NAKED (func_type
))
13303 if (IS_INTERRUPT (func_type
))
13305 error ("interrupt Service Routines cannot be coded in Thumb mode");
13309 offsets
= arm_get_frame_offsets ();
13311 if (frame_pointer_needed
)
13313 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
13314 stack_pointer_rtx
));
13315 RTX_FRAME_RELATED_P (insn
) = 1;
13318 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13323 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13324 GEN_INT (- amount
)));
13325 RTX_FRAME_RELATED_P (insn
) = 1;
13331 /* The stack decrement is too big for an immediate value in a single
13332 insn. In theory we could issue multiple subtracts, but after
13333 three of them it becomes more space efficient to place the full
13334 value in the constant pool and load into a register. (Also the
13335 ARM debugger really likes to see only one stack decrement per
13336 function). So instead we look for a scratch register into which
13337 we can load the decrement, and then we subtract this from the
13338 stack pointer. Unfortunately on the thumb the only available
13339 scratch registers are the argument registers, and we cannot use
13340 these as they may hold arguments to the function. Instead we
13341 attempt to locate a call preserved register which is used by this
13342 function. If we can find one, then we know that it will have
13343 been pushed at the start of the prologue and so we can corrupt
13345 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
13346 if (THUMB_REG_PUSHED_P (regno
)
13347 && !(frame_pointer_needed
13348 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
13351 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
13353 rtx spare
= gen_rtx_REG (SImode
, IP_REGNUM
);
13355 /* Choose an arbitrary, non-argument low register. */
13356 reg
= gen_rtx_REG (SImode
, LAST_LO_REGNUM
);
13358 /* Save it by copying it into a high, scratch register. */
13359 emit_insn (gen_movsi (spare
, reg
));
13360 /* Add a USE to stop propagate_one_insn() from barfing. */
13361 emit_insn (gen_prologue_use (spare
));
13363 /* Decrement the stack. */
13364 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13365 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13366 stack_pointer_rtx
, reg
));
13367 RTX_FRAME_RELATED_P (insn
) = 1;
13368 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13369 plus_constant (stack_pointer_rtx
,
13371 RTX_FRAME_RELATED_P (dwarf
) = 1;
13373 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13376 /* Restore the low register's original value. */
13377 emit_insn (gen_movsi (reg
, spare
));
13379 /* Emit a USE of the restored scratch register, so that flow
13380 analysis will not consider the restore redundant. The
13381 register won't be used again in this function and isn't
13382 restored by the epilogue. */
13383 emit_insn (gen_prologue_use (reg
));
13387 reg
= gen_rtx_REG (SImode
, regno
);
13389 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
13391 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
13392 stack_pointer_rtx
, reg
));
13393 RTX_FRAME_RELATED_P (insn
) = 1;
13394 dwarf
= gen_rtx_SET (SImode
, stack_pointer_rtx
,
13395 plus_constant (stack_pointer_rtx
,
13397 RTX_FRAME_RELATED_P (dwarf
) = 1;
13399 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
13403 /* If the frame pointer is needed, emit a special barrier that
13404 will prevent the scheduler from moving stores to the frame
13405 before the stack adjustment. */
13406 if (frame_pointer_needed
)
13407 emit_insn (gen_stack_tie (stack_pointer_rtx
,
13408 hard_frame_pointer_rtx
));
13411 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
13412 emit_insn (gen_blockage ());
13414 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
13415 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13417 if (THUMB_REG_PUSHED_P (regno
))
13419 cfun
->machine
->lr_save_eliminated
= 0;
13424 /* If the link register is being kept alive, with the return address in it,
13425 then make sure that it does not get reused by the ce2 pass. */
13426 if (cfun
->machine
->lr_save_eliminated
)
13427 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
13431 thumb_expand_epilogue (void)
13433 HOST_WIDE_INT amount
;
13434 arm_stack_offsets
*offsets
;
13437 /* Naked functions don't have prologues. */
13438 if (IS_NAKED (arm_current_func_type ()))
13441 offsets
= arm_get_frame_offsets ();
13442 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
13444 if (frame_pointer_needed
)
13445 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
13449 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
13450 GEN_INT (amount
)));
13453 /* r3 is always free in the epilogue. */
13454 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
13456 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
13457 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
13461 /* Emit a USE (stack_pointer_rtx), so that
13462 the stack adjustment will not be deleted. */
13463 emit_insn (gen_prologue_use (stack_pointer_rtx
));
13465 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
13466 emit_insn (gen_blockage ());
13468 /* Emit a clobber for each insn that will be restored in the epilogue,
13469 so that flow2 will get register lifetimes correct. */
13470 for (regno
= 0; regno
< 13; regno
++)
13471 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
13472 emit_insn (gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, regno
)));
13474 if (! regs_ever_live
[LR_REGNUM
])
13475 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
13479 thumb_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
13481 int live_regs_mask
= 0;
13482 int high_regs_pushed
= 0;
13483 int cfa_offset
= 0;
13486 if (IS_NAKED (arm_current_func_type ()))
13489 if (is_called_in_ARM_mode (current_function_decl
))
13493 if (GET_CODE (DECL_RTL (current_function_decl
)) != MEM
)
13495 if (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0)) != SYMBOL_REF
)
13497 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
13499 /* Generate code sequence to switch us into Thumb mode. */
13500 /* The .code 32 directive has already been emitted by
13501 ASM_DECLARE_FUNCTION_NAME. */
13502 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
13503 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
13505 /* Generate a label, so that the debugger will notice the
13506 change in instruction sets. This label is also used by
13507 the assembler to bypass the ARM code when this function
13508 is called from a Thumb encoded function elsewhere in the
13509 same file. Hence the definition of STUB_NAME here must
13510 agree with the definition in gas/config/tc-arm.c. */
13512 #define STUB_NAME ".real_start_of"
13514 fprintf (f
, "\t.code\t16\n");
13516 if (arm_dllexport_name_p (name
))
13517 name
= arm_strip_name_encoding (name
);
13519 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
13520 fprintf (f
, "\t.thumb_func\n");
13521 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
13524 if (current_function_pretend_args_size
)
13526 if (cfun
->machine
->uses_anonymous_args
)
13530 fprintf (f
, "\tpush\t{");
13532 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
13534 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
13535 regno
<= LAST_ARG_REGNUM
;
13537 asm_fprintf (f
, "%r%s", regno
,
13538 regno
== LAST_ARG_REGNUM
? "" : ", ");
13540 fprintf (f
, "}\n");
13543 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
13544 SP_REGNUM
, SP_REGNUM
,
13545 current_function_pretend_args_size
);
13547 /* We don't need to record the stores for unwinding (would it
13548 help the debugger any if we did?), but record the change in
13549 the stack pointer. */
13550 if (dwarf2out_do_frame ())
13552 char *l
= dwarf2out_cfi_label ();
13553 cfa_offset
= cfa_offset
+ current_function_pretend_args_size
;
13554 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13558 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
13559 if (THUMB_REG_PUSHED_P (regno
))
13560 live_regs_mask
|= 1 << regno
;
13562 if (live_regs_mask
|| thumb_force_lr_save ())
13563 live_regs_mask
|= 1 << LR_REGNUM
;
13565 if (TARGET_BACKTRACE
)
13568 int work_register
= 0;
13571 /* We have been asked to create a stack backtrace structure.
13572 The code looks like this:
13576 0 sub SP, #16 Reserve space for 4 registers.
13577 2 push {R7} Get a work register.
13578 4 add R7, SP, #20 Get the stack pointer before the push.
13579 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13580 8 mov R7, PC Get hold of the start of this code plus 12.
13581 10 str R7, [SP, #16] Store it.
13582 12 mov R7, FP Get hold of the current frame pointer.
13583 14 str R7, [SP, #4] Store it.
13584 16 mov R7, LR Get hold of the current return address.
13585 18 str R7, [SP, #12] Store it.
13586 20 add R7, SP, #16 Point at the start of the backtrace structure.
13587 22 mov FP, R7 Put this value into the frame pointer. */
13589 if ((live_regs_mask
& 0xFF) == 0)
13591 /* See if the a4 register is free. */
13593 if (regs_ever_live
[LAST_ARG_REGNUM
] == 0)
13594 work_register
= LAST_ARG_REGNUM
;
13595 else /* We must push a register of our own. */
13596 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
13599 if (work_register
== 0)
13601 /* Select a register from the list that will be pushed to
13602 use as our work register. */
13603 for (work_register
= (LAST_LO_REGNUM
+ 1); work_register
--;)
13604 if ((1 << work_register
) & live_regs_mask
)
13609 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13610 SP_REGNUM
, SP_REGNUM
);
13612 if (dwarf2out_do_frame ())
13614 char *l
= dwarf2out_cfi_label ();
13615 cfa_offset
= cfa_offset
+ 16;
13616 dwarf2out_def_cfa (l
, SP_REGNUM
, cfa_offset
);
13619 if (live_regs_mask
)
13620 thumb_pushpop (f
, live_regs_mask
, 1, &cfa_offset
, live_regs_mask
);
13622 for (offset
= 0, wr
= 1 << 15; wr
!= 0; wr
>>= 1)
13623 if (wr
& live_regs_mask
)
13626 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13627 offset
+ 16 + current_function_pretend_args_size
);
13629 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13632 /* Make sure that the instruction fetching the PC is in the right place
13633 to calculate "start of backtrace creation code + 12". */
13634 if (live_regs_mask
)
13636 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13637 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13639 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13640 ARM_HARD_FRAME_POINTER_REGNUM
);
13641 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13646 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
13647 ARM_HARD_FRAME_POINTER_REGNUM
);
13648 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13650 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
13651 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13655 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
13656 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
13658 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
13660 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13661 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
13663 else if (live_regs_mask
)
13664 thumb_pushpop (f
, live_regs_mask
, 1, &cfa_offset
, live_regs_mask
);
13666 for (regno
= 8; regno
< 13; regno
++)
13667 if (THUMB_REG_PUSHED_P (regno
))
13668 high_regs_pushed
++;
13670 if (high_regs_pushed
)
13672 int pushable_regs
= 0;
13673 int mask
= live_regs_mask
& 0xff;
13676 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
13677 if (THUMB_REG_PUSHED_P (next_hi_reg
))
13680 pushable_regs
= mask
;
13682 if (pushable_regs
== 0)
13684 /* Desperation time -- this probably will never happen. */
13685 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
))
13686 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, LAST_ARG_REGNUM
);
13687 mask
= 1 << LAST_ARG_REGNUM
;
13690 while (high_regs_pushed
> 0)
13692 int real_regs_mask
= 0;
13694 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
13696 if (mask
& (1 << regno
))
13698 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
13700 high_regs_pushed
--;
13701 real_regs_mask
|= (1 << next_hi_reg
);
13703 if (high_regs_pushed
)
13705 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
13707 if (THUMB_REG_PUSHED_P (next_hi_reg
))
13712 mask
&= ~((1 << regno
) - 1);
13718 thumb_pushpop (f
, mask
, 1, &cfa_offset
, real_regs_mask
);
13721 if (pushable_regs
== 0
13722 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
)))
13723 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
13727 /* Handle the case of a double word load into a low register from
13728 a computed memory address. The computed address may involve a
13729 register which is overwritten by the load. */
13731 thumb_load_double_from_address (rtx
*operands
)
13739 if (GET_CODE (operands
[0]) != REG
)
13742 if (GET_CODE (operands
[1]) != MEM
)
13745 /* Get the memory address. */
13746 addr
= XEXP (operands
[1], 0);
13748 /* Work out how the memory address is computed. */
13749 switch (GET_CODE (addr
))
13752 operands
[2] = gen_rtx_MEM (SImode
,
13753 plus_constant (XEXP (operands
[1], 0), 4));
13755 if (REGNO (operands
[0]) == REGNO (addr
))
13757 output_asm_insn ("ldr\t%H0, %2", operands
);
13758 output_asm_insn ("ldr\t%0, %1", operands
);
13762 output_asm_insn ("ldr\t%0, %1", operands
);
13763 output_asm_insn ("ldr\t%H0, %2", operands
);
13768 /* Compute <address> + 4 for the high order load. */
13769 operands
[2] = gen_rtx_MEM (SImode
,
13770 plus_constant (XEXP (operands
[1], 0), 4));
13772 output_asm_insn ("ldr\t%0, %1", operands
);
13773 output_asm_insn ("ldr\t%H0, %2", operands
);
13777 arg1
= XEXP (addr
, 0);
13778 arg2
= XEXP (addr
, 1);
13780 if (CONSTANT_P (arg1
))
13781 base
= arg2
, offset
= arg1
;
13783 base
= arg1
, offset
= arg2
;
13785 if (GET_CODE (base
) != REG
)
13788 /* Catch the case of <address> = <reg> + <reg> */
13789 if (GET_CODE (offset
) == REG
)
13791 int reg_offset
= REGNO (offset
);
13792 int reg_base
= REGNO (base
);
13793 int reg_dest
= REGNO (operands
[0]);
13795 /* Add the base and offset registers together into the
13796 higher destination register. */
13797 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
13798 reg_dest
+ 1, reg_base
, reg_offset
);
13800 /* Load the lower destination register from the address in
13801 the higher destination register. */
13802 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
13803 reg_dest
, reg_dest
+ 1);
13805 /* Load the higher destination register from its own address
13807 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
13808 reg_dest
+ 1, reg_dest
+ 1);
13812 /* Compute <address> + 4 for the high order load. */
13813 operands
[2] = gen_rtx_MEM (SImode
,
13814 plus_constant (XEXP (operands
[1], 0), 4));
13816 /* If the computed address is held in the low order register
13817 then load the high order register first, otherwise always
13818 load the low order register first. */
13819 if (REGNO (operands
[0]) == REGNO (base
))
13821 output_asm_insn ("ldr\t%H0, %2", operands
);
13822 output_asm_insn ("ldr\t%0, %1", operands
);
13826 output_asm_insn ("ldr\t%0, %1", operands
);
13827 output_asm_insn ("ldr\t%H0, %2", operands
);
13833 /* With no registers to worry about we can just load the value
13835 operands
[2] = gen_rtx_MEM (SImode
,
13836 plus_constant (XEXP (operands
[1], 0), 4));
13838 output_asm_insn ("ldr\t%H0, %2", operands
);
13839 output_asm_insn ("ldr\t%0, %1", operands
);
13851 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
13858 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13861 operands
[4] = operands
[5];
13864 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
13865 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
13869 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13872 operands
[4] = operands
[5];
13875 if (REGNO (operands
[5]) > REGNO (operands
[6]))
13878 operands
[5] = operands
[6];
13881 if (REGNO (operands
[4]) > REGNO (operands
[5]))
13884 operands
[4] = operands
[5];
13888 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
13889 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
13899 /* Routines for generating rtl. */
13901 thumb_expand_movmemqi (rtx
*operands
)
13903 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
13904 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
13905 HOST_WIDE_INT len
= INTVAL (operands
[2]);
13906 HOST_WIDE_INT offset
= 0;
13910 emit_insn (gen_movmem12b (out
, in
, out
, in
));
13916 emit_insn (gen_movmem8b (out
, in
, out
, in
));
13922 rtx reg
= gen_reg_rtx (SImode
);
13923 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
13924 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
13931 rtx reg
= gen_reg_rtx (HImode
);
13932 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
13933 plus_constant (in
, offset
))));
13934 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (out
, offset
)),
13942 rtx reg
= gen_reg_rtx (QImode
);
13943 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
13944 plus_constant (in
, offset
))));
13945 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (out
, offset
)),
13951 thumb_cmp_operand (rtx op
, enum machine_mode mode
)
13953 return ((GET_CODE (op
) == CONST_INT
13954 && INTVAL (op
) < 256
13955 && INTVAL (op
) >= 0)
13956 || s_register_operand (op
, mode
));
13960 thumb_cmpneg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
13962 return (GET_CODE (op
) == CONST_INT
13964 && INTVAL (op
) > -256);
13967 /* Return TRUE if a result can be stored in OP without clobbering the
13968 condition code register. Prior to reload we only accept a
13969 register. After reload we have to be able to handle memory as
13970 well, since a pseudo may not get a hard reg and reload cannot
13971 handle output-reloads on jump insns.
13973 We could possibly handle mem before reload as well, but that might
13974 complicate things with the need to handle increment
13978 thumb_cbrch_target_operand (rtx op
, enum machine_mode mode
)
13980 return (s_register_operand (op
, mode
)
13981 || ((reload_in_progress
|| reload_completed
)
13982 && memory_operand (op
, mode
)));
13985 /* Handle storing a half-word to memory during reload. */
13987 thumb_reload_out_hi (rtx
*operands
)
13989 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
13992 /* Handle reading a half-word from memory during reload. */
13994 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
13999 /* Return the length of a function name prefix
14000 that starts with the character 'c'. */
14002 arm_get_strip_length (int c
)
14006 ARM_NAME_ENCODING_LENGTHS
14011 /* Return a pointer to a function's name with any
14012 and all prefix encodings stripped from it. */
14014 arm_strip_name_encoding (const char *name
)
14018 while ((skip
= arm_get_strip_length (* name
)))
14024 /* If there is a '*' anywhere in the name's prefix, then
14025 emit the stripped name verbatim, otherwise prepend an
14026 underscore if leading underscores are being used. */
14028 arm_asm_output_labelref (FILE *stream
, const char *name
)
14033 while ((skip
= arm_get_strip_length (* name
)))
14035 verbatim
|= (*name
== '*');
14040 fputs (name
, stream
);
14042 asm_fprintf (stream
, "%U%s", name
);
14047 #ifdef AOF_ASSEMBLER
14048 /* Special functions only needed when producing AOF syntax assembler. */
14052 struct pic_chain
* next
;
14053 const char * symname
;
14056 static struct pic_chain
* aof_pic_chain
= NULL
;
14059 aof_pic_entry (rtx x
)
14061 struct pic_chain
** chainp
;
14064 if (aof_pic_label
== NULL_RTX
)
14066 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
14069 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
14070 offset
+= 4, chainp
= &(*chainp
)->next
)
14071 if ((*chainp
)->symname
== XSTR (x
, 0))
14072 return plus_constant (aof_pic_label
, offset
);
14074 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
14075 (*chainp
)->next
= NULL
;
14076 (*chainp
)->symname
= XSTR (x
, 0);
14077 return plus_constant (aof_pic_label
, offset
);
14081 aof_dump_pic_table (FILE *f
)
14083 struct pic_chain
* chain
;
14085 if (aof_pic_chain
== NULL
)
14088 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
14089 PIC_OFFSET_TABLE_REGNUM
,
14090 PIC_OFFSET_TABLE_REGNUM
);
14091 fputs ("|x$adcons|\n", f
);
14093 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
14095 fputs ("\tDCD\t", f
);
14096 assemble_name (f
, chain
->symname
);
14101 int arm_text_section_count
= 1;
14104 aof_text_section (void )
14106 static char buf
[100];
14107 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
14108 arm_text_section_count
++);
14110 strcat (buf
, ", PIC, REENTRANT");
14114 static int arm_data_section_count
= 1;
14117 aof_data_section (void)
14119 static char buf
[100];
14120 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
14124 /* The AOF assembler is religiously strict about declarations of
14125 imported and exported symbols, so that it is impossible to declare
14126 a function as imported near the beginning of the file, and then to
14127 export it later on. It is, however, possible to delay the decision
14128 until all the functions in the file have been compiled. To get
14129 around this, we maintain a list of the imports and exports, and
14130 delete from it any that are subsequently defined. At the end of
14131 compilation we spit the remainder of the list out before the END
14136 struct import
* next
;
14140 static struct import
* imports_list
= NULL
;
14143 aof_add_import (const char *name
)
14145 struct import
* new;
14147 for (new = imports_list
; new; new = new->next
)
14148 if (new->name
== name
)
14151 new = (struct import
*) xmalloc (sizeof (struct import
));
14152 new->next
= imports_list
;
14153 imports_list
= new;
14158 aof_delete_import (const char *name
)
14160 struct import
** old
;
14162 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
14164 if ((*old
)->name
== name
)
14166 *old
= (*old
)->next
;
14172 int arm_main_function
= 0;
14175 aof_dump_imports (FILE *f
)
14177 /* The AOF assembler needs this to cause the startup code to be extracted
14178 from the library. Brining in __main causes the whole thing to work
14180 if (arm_main_function
)
14183 fputs ("\tIMPORT __main\n", f
);
14184 fputs ("\tDCD __main\n", f
);
14187 /* Now dump the remaining imports. */
14188 while (imports_list
)
14190 fprintf (f
, "\tIMPORT\t");
14191 assemble_name (f
, imports_list
->name
);
14193 imports_list
= imports_list
->next
;
14198 aof_globalize_label (FILE *stream
, const char *name
)
14200 default_globalize_label (stream
, name
);
14201 if (! strcmp (name
, "main"))
14202 arm_main_function
= 1;
14206 aof_file_start (void)
14208 fputs ("__r0\tRN\t0\n", asm_out_file
);
14209 fputs ("__a1\tRN\t0\n", asm_out_file
);
14210 fputs ("__a2\tRN\t1\n", asm_out_file
);
14211 fputs ("__a3\tRN\t2\n", asm_out_file
);
14212 fputs ("__a4\tRN\t3\n", asm_out_file
);
14213 fputs ("__v1\tRN\t4\n", asm_out_file
);
14214 fputs ("__v2\tRN\t5\n", asm_out_file
);
14215 fputs ("__v3\tRN\t6\n", asm_out_file
);
14216 fputs ("__v4\tRN\t7\n", asm_out_file
);
14217 fputs ("__v5\tRN\t8\n", asm_out_file
);
14218 fputs ("__v6\tRN\t9\n", asm_out_file
);
14219 fputs ("__sl\tRN\t10\n", asm_out_file
);
14220 fputs ("__fp\tRN\t11\n", asm_out_file
);
14221 fputs ("__ip\tRN\t12\n", asm_out_file
);
14222 fputs ("__sp\tRN\t13\n", asm_out_file
);
14223 fputs ("__lr\tRN\t14\n", asm_out_file
);
14224 fputs ("__pc\tRN\t15\n", asm_out_file
);
14225 fputs ("__f0\tFN\t0\n", asm_out_file
);
14226 fputs ("__f1\tFN\t1\n", asm_out_file
);
14227 fputs ("__f2\tFN\t2\n", asm_out_file
);
14228 fputs ("__f3\tFN\t3\n", asm_out_file
);
14229 fputs ("__f4\tFN\t4\n", asm_out_file
);
14230 fputs ("__f5\tFN\t5\n", asm_out_file
);
14231 fputs ("__f6\tFN\t6\n", asm_out_file
);
14232 fputs ("__f7\tFN\t7\n", asm_out_file
);
14237 aof_file_end (void)
14240 aof_dump_pic_table (asm_out_file
);
14241 aof_dump_imports (asm_out_file
);
14242 fputs ("\tEND\n", asm_out_file
);
14244 #endif /* AOF_ASSEMBLER */
14246 #ifdef OBJECT_FORMAT_ELF
14247 /* Switch to an arbitrary section NAME with attributes as specified
14248 by FLAGS. ALIGN specifies any known alignment requirements for
14249 the section; 0 if the default should be used.
14251 Differs from the default elf version only in the prefix character
14252 used before the section type. */
14255 arm_elf_asm_named_section (const char *name
, unsigned int flags
)
14257 char flagchars
[10], *f
= flagchars
;
14259 if (! named_section_first_declaration (name
))
14261 fprintf (asm_out_file
, "\t.section\t%s\n", name
);
14265 if (!(flags
& SECTION_DEBUG
))
14267 if (flags
& SECTION_WRITE
)
14269 if (flags
& SECTION_CODE
)
14271 if (flags
& SECTION_SMALL
)
14273 if (flags
& SECTION_MERGE
)
14275 if (flags
& SECTION_STRINGS
)
14277 if (flags
& SECTION_TLS
)
14281 fprintf (asm_out_file
, "\t.section\t%s,\"%s\"", name
, flagchars
);
14283 if (!(flags
& SECTION_NOTYPE
))
14287 if (flags
& SECTION_BSS
)
14292 fprintf (asm_out_file
, ",%%%s", type
);
14294 if (flags
& SECTION_ENTSIZE
)
14295 fprintf (asm_out_file
, ",%d", flags
& SECTION_ENTSIZE
);
14298 putc ('\n', asm_out_file
);
14303 /* Symbols in the text segment can be accessed without indirecting via the
14304 constant pool; it may take an extra binary operation, but this is still
14305 faster than indirecting via memory. Don't do this when not optimizing,
14306 since we won't be calculating al of the offsets necessary to do this
14310 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
14312 /* This doesn't work with AOF syntax, since the string table may be in
14313 a different AREA. */
14314 #ifndef AOF_ASSEMBLER
14315 if (optimize
> 0 && TREE_CONSTANT (decl
))
14316 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
14319 /* If we are referencing a function that is weak then encode a long call
14320 flag in the function name, otherwise if the function is static or
14321 or known to be defined in this file then encode a short call flag. */
14322 if (first
&& TREE_CODE_CLASS (TREE_CODE (decl
)) == 'd')
14324 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
14325 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
14326 else if (! TREE_PUBLIC (decl
))
14327 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
14330 #endif /* !ARM_PE */
14333 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
14335 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
14336 && !strcmp (prefix
, "L"))
14338 arm_ccfsm_state
= 0;
14339 arm_target_insn
= NULL
;
14341 default_internal_label (stream
, prefix
, labelno
);
14344 /* Output code to add DELTA to the first argument, and then jump
14345 to FUNCTION. Used for C++ multiple inheritance. */
14347 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
14348 HOST_WIDE_INT delta
,
14349 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
14352 static int thunk_label
= 0;
14354 int mi_delta
= delta
;
14355 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
14357 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
14360 mi_delta
= - mi_delta
;
14363 int labelno
= thunk_label
++;
14364 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
14365 fputs ("\tldr\tr12, ", file
);
14366 assemble_name (file
, label
);
14367 fputc ('\n', file
);
14369 while (mi_delta
!= 0)
14371 if ((mi_delta
& (3 << shift
)) == 0)
14375 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
14376 mi_op
, this_regno
, this_regno
,
14377 mi_delta
& (0xff << shift
));
14378 mi_delta
&= ~(0xff << shift
);
14384 fprintf (file
, "\tbx\tr12\n");
14385 ASM_OUTPUT_ALIGN (file
, 2);
14386 assemble_name (file
, label
);
14387 fputs (":\n", file
);
14388 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
14392 fputs ("\tb\t", file
);
14393 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
14394 if (NEED_PLT_RELOC
)
14395 fputs ("(PLT)", file
);
14396 fputc ('\n', file
);
14401 arm_emit_vector_const (FILE *file
, rtx x
)
14404 const char * pattern
;
14406 if (GET_CODE (x
) != CONST_VECTOR
)
14409 switch (GET_MODE (x
))
14411 case V2SImode
: pattern
= "%08x"; break;
14412 case V4HImode
: pattern
= "%04x"; break;
14413 case V8QImode
: pattern
= "%02x"; break;
14417 fprintf (file
, "0x");
14418 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
14422 element
= CONST_VECTOR_ELT (x
, i
);
14423 fprintf (file
, pattern
, INTVAL (element
));
14430 arm_output_load_gr (rtx
*operands
)
14437 if (GET_CODE (operands
[1]) != MEM
14438 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
14439 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
14440 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
14441 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
14442 return "wldrw%?\t%0, %1";
14444 /* Fix up an out-of-range load of a GR register. */
14445 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
14446 wcgr
= operands
[0];
14448 output_asm_insn ("ldr%?\t%0, %1", operands
);
14450 operands
[0] = wcgr
;
14452 output_asm_insn ("tmcr%?\t%0, %1", operands
);
14453 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
14459 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
14460 int incoming ATTRIBUTE_UNUSED
)
14463 /* FIXME: The ARM backend has special code to handle structure
14464 returns, and will reserve its own hidden first argument. So
14465 if this macro is enabled a *second* hidden argument will be
14466 reserved, which will break binary compatibility with old
14467 toolchains and also thunk handling. One day this should be
14471 /* Register in which address to store a structure value
14472 is passed to a function. */
14473 return gen_rtx_REG (Pmode
, ARG_REGISTER (1));
14477 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14479 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14480 named arg and all anonymous args onto the stack.
14481 XXX I know the prologue shouldn't be pushing registers, but it is faster
14485 arm_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
,
14486 enum machine_mode mode ATTRIBUTE_UNUSED
,
14487 tree type ATTRIBUTE_UNUSED
,
14489 int second_time ATTRIBUTE_UNUSED
)
14491 cfun
->machine
->uses_anonymous_args
= 1;
14492 if (cum
->nregs
< NUM_ARG_REGS
)
14493 *pretend_size
= (NUM_ARG_REGS
- cum
->nregs
) * UNITS_PER_WORD
;
14496 /* Return nonzero if the CONSUMER instruction (a store) does not need
14497 PRODUCER's value to calculate the address. */
14500 arm_no_early_store_addr_dep (rtx producer
, rtx consumer
)
14502 rtx value
= PATTERN (producer
);
14503 rtx addr
= PATTERN (consumer
);
14505 if (GET_CODE (value
) == COND_EXEC
)
14506 value
= COND_EXEC_CODE (value
);
14507 if (GET_CODE (value
) == PARALLEL
)
14508 value
= XVECEXP (value
, 0, 0);
14509 value
= XEXP (value
, 0);
14510 if (GET_CODE (addr
) == COND_EXEC
)
14511 addr
= COND_EXEC_CODE (addr
);
14512 if (GET_CODE (addr
) == PARALLEL
)
14513 addr
= XVECEXP (addr
, 0, 0);
14514 addr
= XEXP (addr
, 0);
14516 return !reg_overlap_mentioned_p (value
, addr
);
14519 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14520 have an early register shift value or amount dependency on the
14521 result of PRODUCER. */
14524 arm_no_early_alu_shift_dep (rtx producer
, rtx consumer
)
14526 rtx value
= PATTERN (producer
);
14527 rtx op
= PATTERN (consumer
);
14530 if (GET_CODE (value
) == COND_EXEC
)
14531 value
= COND_EXEC_CODE (value
);
14532 if (GET_CODE (value
) == PARALLEL
)
14533 value
= XVECEXP (value
, 0, 0);
14534 value
= XEXP (value
, 0);
14535 if (GET_CODE (op
) == COND_EXEC
)
14536 op
= COND_EXEC_CODE (op
);
14537 if (GET_CODE (op
) == PARALLEL
)
14538 op
= XVECEXP (op
, 0, 0);
14541 early_op
= XEXP (op
, 0);
14542 /* This is either an actual independent shift, or a shift applied to
14543 the first operand of another operation. We want the whole shift
14545 if (GET_CODE (early_op
) == REG
)
14548 return !reg_overlap_mentioned_p (value
, early_op
);
14551 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14552 have an early register shift value dependency on the result of
14556 arm_no_early_alu_shift_value_dep (rtx producer
, rtx consumer
)
14558 rtx value
= PATTERN (producer
);
14559 rtx op
= PATTERN (consumer
);
14562 if (GET_CODE (value
) == COND_EXEC
)
14563 value
= COND_EXEC_CODE (value
);
14564 if (GET_CODE (value
) == PARALLEL
)
14565 value
= XVECEXP (value
, 0, 0);
14566 value
= XEXP (value
, 0);
14567 if (GET_CODE (op
) == COND_EXEC
)
14568 op
= COND_EXEC_CODE (op
);
14569 if (GET_CODE (op
) == PARALLEL
)
14570 op
= XVECEXP (op
, 0, 0);
14573 early_op
= XEXP (op
, 0);
14575 /* This is either an actual independent shift, or a shift applied to
14576 the first operand of another operation. We want the value being
14577 shifted, in either case. */
14578 if (GET_CODE (early_op
) != REG
)
14579 early_op
= XEXP (early_op
, 0);
14581 return !reg_overlap_mentioned_p (value
, early_op
);
14584 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14585 have an early register mult dependency on the result of
14589 arm_no_early_mul_dep (rtx producer
, rtx consumer
)
14591 rtx value
= PATTERN (producer
);
14592 rtx op
= PATTERN (consumer
);
14594 if (GET_CODE (value
) == COND_EXEC
)
14595 value
= COND_EXEC_CODE (value
);
14596 if (GET_CODE (value
) == PARALLEL
)
14597 value
= XVECEXP (value
, 0, 0);
14598 value
= XEXP (value
, 0);
14599 if (GET_CODE (op
) == COND_EXEC
)
14600 op
= COND_EXEC_CODE (op
);
14601 if (GET_CODE (op
) == PARALLEL
)
14602 op
= XVECEXP (op
, 0, 0);
14605 return (GET_CODE (op
) == PLUS
14606 && !reg_overlap_mentioned_p (value
, XEXP (op
, 0)));
14610 /* We can't rely on the caller doing the proper promotion when
14611 using APCS or ATPCS. */
14614 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED
)
14616 return !TARGET_AAPCS_BASED
;
14620 /* AAPCS based ABIs use short enums by default. */
14623 arm_default_short_enums (void)
14625 return TARGET_AAPCS_BASED
;
14629 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14632 arm_align_anon_bitfield (void)
14634 return TARGET_AAPCS_BASED
;
14638 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14641 arm_cxx_guard_type (void)
14643 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
14647 /* The EABI says test the least significan bit of a guard variable. */
14650 arm_cxx_guard_mask_bit (void)
14652 return TARGET_AAPCS_BASED
;
14656 /* The EABI specifies that all array cookies are 8 bytes long. */
14659 arm_get_cookie_size (tree type
)
14663 if (!TARGET_AAPCS_BASED
)
14664 return default_cxx_get_cookie_size (type
);
14666 size
= build_int_2 (8, 0);
14667 TREE_TYPE (size
) = sizetype
;
14672 /* The EABI says that array cookies should also contain the element size. */
14675 arm_cookie_has_size (void)
14677 return TARGET_AAPCS_BASED
;
14681 /* The EABI says constructors and destructors should return a pointer to
14682 the object constructed/destroyed. */
14685 arm_cxx_cdtor_returns_this (void)
14687 return TARGET_AAPCS_BASED
;
14692 arm_set_return_address (rtx source
, rtx scratch
)
14694 arm_stack_offsets
*offsets
;
14695 HOST_WIDE_INT delta
;
14697 unsigned long saved_regs
;
14699 saved_regs
= arm_compute_save_reg_mask ();
14701 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
14702 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
14705 if (frame_pointer_needed
)
14706 addr
= plus_constant(hard_frame_pointer_rtx
, -4);
14709 /* LR will be the first saved register. */
14710 offsets
= arm_get_frame_offsets ();
14711 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
14716 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
14717 GEN_INT (delta
& ~4095)));
14722 addr
= stack_pointer_rtx
;
14724 addr
= plus_constant (addr
, delta
);
14726 emit_move_insn (gen_rtx_MEM (Pmode
, addr
), source
);
14732 thumb_set_return_address (rtx source
, rtx scratch
)
14734 arm_stack_offsets
*offsets
;
14736 HOST_WIDE_INT delta
;
14740 emit_insn (gen_rtx_USE (VOIDmode
, source
));
14742 for (reg
= 0; reg
<= LAST_LO_REGNUM
; reg
++)
14744 if (THUMB_REG_PUSHED_P (reg
))
14750 lr_saved
|= thumb_force_lr_save ();
14754 offsets
= arm_get_frame_offsets ();
14756 /* Find the saved regs. */
14757 if (frame_pointer_needed
)
14759 delta
= offsets
->soft_frame
- offsets
->saved_args
;
14760 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
14764 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
14767 /* Allow for the stack frame. */
14768 if (TARGET_BACKTRACE
)
14770 /* The link register is always the first saved register. */
14773 /* Construct the address. */
14774 addr
= gen_rtx_REG (SImode
, reg
);
14775 if ((reg
!= SP_REGNUM
&& delta
>= 128)
14778 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
14779 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
14783 addr
= plus_constant (addr
, delta
);
14785 emit_move_insn (gen_rtx_MEM (Pmode
, addr
), source
);
14788 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);