1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 /* Forward definitions of types. */
55 typedef struct minipool_node Mnode
;
56 typedef struct minipool_fixup Mfix
;
58 const struct attribute_spec arm_attribute_table
[];
60 /* Forward function declarations. */
61 static void arm_add_gc_roots (void);
62 static int arm_gen_constant (enum rtx_code
, enum machine_mode
, HOST_WIDE_INT
,
64 static unsigned bit_count (unsigned long);
65 static int arm_address_register_rtx_p (rtx
, int);
66 static int arm_legitimate_index_p (enum machine_mode
, rtx
, int);
67 static int thumb_base_register_rtx_p (rtx
, enum machine_mode
, int);
68 inline static int thumb_index_register_rtx_p (rtx
, int);
69 static int const_ok_for_op (HOST_WIDE_INT
, enum rtx_code
);
70 static rtx
emit_multi_reg_push (int);
71 static rtx
emit_sfm (int, int);
73 static bool arm_assemble_integer (rtx
, unsigned int, int);
75 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
76 static arm_cc
get_arm_condition_code (rtx
);
77 static void init_fpa_table (void);
78 static HOST_WIDE_INT
int_log2 (HOST_WIDE_INT
);
79 static rtx
is_jump_table (rtx
);
80 static const char *output_multi_immediate (rtx
*, const char *, const char *,
82 static void print_multi_reg (FILE *, const char *, int, int);
83 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
84 static struct machine_function
*arm_init_machine_status (void);
85 static int number_of_first_bit_set (int);
86 static void replace_symbols_in_block (tree
, rtx
, rtx
);
87 static void thumb_exit (FILE *, int, rtx
);
88 static void thumb_pushpop (FILE *, int, int);
89 static rtx
is_jump_table (rtx
);
90 static HOST_WIDE_INT
get_jump_table_size (rtx
);
91 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
92 static Mnode
*add_minipool_forward_ref (Mfix
*);
93 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
94 static Mnode
*add_minipool_backward_ref (Mfix
*);
95 static void assign_minipool_offsets (Mfix
*);
96 static void arm_print_value (FILE *, rtx
);
97 static void dump_minipool (rtx
);
98 static int arm_barrier_cost (rtx
);
99 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
100 static void push_minipool_barrier (rtx
, HOST_WIDE_INT
);
101 static void push_minipool_fix (rtx
, HOST_WIDE_INT
, rtx
*, enum machine_mode
,
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx
, HOST_WIDE_INT
, int);
105 static int current_file_function_operand (rtx
);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree
);
109 static unsigned long arm_compute_func_type (void);
110 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
111 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
112 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT
);
113 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT
);
114 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT
);
115 static int arm_comp_type_attributes (tree
, tree
);
116 static void arm_set_default_type_attributes (tree
);
117 static int arm_adjust_cost (rtx
, rtx
, rtx
, int);
118 static int arm_use_dfa_pipeline_interface (void);
119 static int count_insns_for_constant (HOST_WIDE_INT
, int);
120 static int arm_get_strip_length (int);
121 static bool arm_function_ok_for_sibcall (tree
, tree
);
122 static void arm_internal_label (FILE *, const char *, unsigned long);
123 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
125 static int arm_rtx_costs_1 (rtx
, enum rtx_code
, enum rtx_code
);
126 static bool arm_rtx_costs (rtx
, int, int, int *);
127 static int arm_address_cost (rtx
);
128 static bool arm_memory_load_p (rtx
);
129 static bool arm_cirrus_insn_p (rtx
);
130 static void cirrus_reorg (rtx
);
131 static void arm_init_builtins (void);
132 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
133 static void arm_init_iwmmxt_builtins (void);
134 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
135 static rtx
arm_expand_binop_builtin (enum insn_code
, tree
, rtx
);
136 static rtx
arm_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
137 static rtx
arm_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
139 #ifdef OBJECT_FORMAT_ELF
140 static void arm_elf_asm_named_section (const char *, unsigned int);
143 static void arm_encode_section_info (tree
, rtx
, int);
146 static void aof_globalize_label (FILE *, const char *);
147 static void aof_dump_imports (FILE *);
148 static void aof_dump_pic_table (FILE *);
149 static void aof_file_start (void);
150 static void aof_file_end (void);
154 /* Initialize the GCC target structure. */
155 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
156 #undef TARGET_MERGE_DECL_ATTRIBUTES
157 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
160 #undef TARGET_ATTRIBUTE_TABLE
161 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
164 #undef TARGET_ASM_BYTE_OP
165 #define TARGET_ASM_BYTE_OP "\tDCB\t"
166 #undef TARGET_ASM_ALIGNED_HI_OP
167 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
168 #undef TARGET_ASM_ALIGNED_SI_OP
169 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
170 #undef TARGET_ASM_GLOBALIZE_LABEL
171 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
172 #undef TARGET_ASM_FILE_START
173 #define TARGET_ASM_FILE_START aof_file_start
174 #undef TARGET_ASM_FILE_END
175 #define TARGET_ASM_FILE_END aof_file_end
177 #undef TARGET_ASM_ALIGNED_SI_OP
178 #define TARGET_ASM_ALIGNED_SI_OP NULL
179 #undef TARGET_ASM_INTEGER
180 #define TARGET_ASM_INTEGER arm_assemble_integer
183 #undef TARGET_ASM_FUNCTION_PROLOGUE
184 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
186 #undef TARGET_ASM_FUNCTION_EPILOGUE
187 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
189 #undef TARGET_COMP_TYPE_ATTRIBUTES
190 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
192 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
193 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
195 #undef TARGET_SCHED_ADJUST_COST
196 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
198 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
199 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface
201 #undef TARGET_ENCODE_SECTION_INFO
203 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
205 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
208 #undef TARGET_STRIP_NAME_ENCODING
209 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
211 #undef TARGET_ASM_INTERNAL_LABEL
212 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
214 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
215 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
217 #undef TARGET_ASM_OUTPUT_MI_THUNK
218 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
219 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
220 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
222 #undef TARGET_RTX_COSTS
223 #define TARGET_RTX_COSTS arm_rtx_costs
224 #undef TARGET_ADDRESS_COST
225 #define TARGET_ADDRESS_COST arm_address_cost
227 #undef TARGET_MACHINE_DEPENDENT_REORG
228 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
230 #undef TARGET_INIT_BUILTINS
231 #define TARGET_INIT_BUILTINS arm_init_builtins
232 #undef TARGET_EXPAND_BUILTIN
233 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
235 struct gcc_target targetm
= TARGET_INITIALIZER
;
237 /* Obstack for minipool constant handling. */
238 static struct obstack minipool_obstack
;
239 static char * minipool_startobj
;
241 /* The maximum number of insns skipped which
242 will be conditionalised if possible. */
243 static int max_insns_skipped
= 5;
245 extern FILE * asm_out_file
;
247 /* True if we are currently building a constant table. */
248 int making_const_table
;
250 /* Define the information needed to generate branch insns. This is
251 stored from the compare operation. */
252 rtx arm_compare_op0
, arm_compare_op1
;
254 /* What type of floating point are we tuning for? */
255 enum fputype arm_fpu_tune
;
257 /* What type of floating point instructions are available? */
258 enum fputype arm_fpu_arch
;
260 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
261 enum prog_mode_type arm_prgmode
;
263 /* Set by the -mfp=... option. */
264 const char * target_fp_name
= NULL
;
266 /* Used to parse -mstructure_size_boundary command line option. */
267 const char * structure_size_string
= NULL
;
268 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
270 /* Bit values used to identify processor capabilities. */
271 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
272 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
273 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
274 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
275 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
276 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
277 #define FL_THUMB (1 << 6) /* Thumb aware */
278 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
279 #define FL_STRONG (1 << 8) /* StrongARM */
280 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
281 #define FL_XSCALE (1 << 10) /* XScale */
282 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
283 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
284 #define FL_ARCH6J (1 << 12) /* Architecture rel 6. Adds
285 media instructions. */
286 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
288 /* The bits in this mask specify which
289 instructions we are allowed to generate. */
290 static unsigned long insn_flags
= 0;
292 /* The bits in this mask specify which instruction scheduling options should
293 be used. Note - there is an overlap with the FL_FAST_MULT. For some
294 hardware we want to be able to generate the multiply instructions, but to
295 tune as if they were not present in the architecture. */
296 static unsigned long tune_flags
= 0;
298 /* The following are used in the arm.md file as equivalents to bits
299 in the above two flag variables. */
301 /* Nonzero if this is an "M" variant of the processor. */
302 int arm_fast_multiply
= 0;
304 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
307 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
310 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
313 /* Nonzero if this chip can benefit from load scheduling. */
314 int arm_ld_sched
= 0;
316 /* Nonzero if this chip is a StrongARM. */
317 int arm_is_strong
= 0;
319 /* Nonzero if this chip supports Intel Wireless MMX technology. */
320 int arm_arch_iwmmxt
= 0;
322 /* Nonzero if this chip is an XScale. */
323 int arm_arch_xscale
= 0;
325 /* Nonzero if tuning for XScale */
326 int arm_tune_xscale
= 0;
328 /* Nonzero if this chip is an ARM6 or an ARM7. */
329 int arm_is_6_or_7
= 0;
331 /* Nonzero if this chip is a Cirrus/DSP. */
332 int arm_is_cirrus
= 0;
334 /* Nonzero if generating Thumb instructions. */
337 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
338 must report the mode of the memory reference from PRINT_OPERAND to
339 PRINT_OPERAND_ADDRESS. */
340 enum machine_mode output_memory_reference_mode
;
342 /* The register number to be used for the PIC offset register. */
343 const char * arm_pic_register_string
= NULL
;
344 int arm_pic_register
= INVALID_REGNUM
;
346 /* Set to 1 when a return insn is output, this means that the epilogue
348 int return_used_this_function
;
350 /* Set to 1 after arm_reorg has started. Reset to start at the start of
351 the next function. */
352 static int after_arm_reorg
= 0;
354 /* The maximum number of insns to be used when loading a constant. */
355 static int arm_constant_limit
= 3;
357 /* For an explanation of these variables, see final_prescan_insn below. */
359 enum arm_cond_code arm_current_cc
;
361 int arm_target_label
;
363 /* The condition codes of the ARM, and the inverse function. */
364 static const char * const arm_condition_codes
[] =
366 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
367 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
370 #define streq(string1, string2) (strcmp (string1, string2) == 0)
372 /* Initialization code. */
376 const char *const name
;
377 const unsigned long flags
;
380 /* Not all of these give usefully different compilation alternatives,
381 but there is no simple way of generalizing them. */
382 static const struct processors all_cores
[] =
386 {"arm2", FL_CO_PROC
| FL_MODE26
},
387 {"arm250", FL_CO_PROC
| FL_MODE26
},
388 {"arm3", FL_CO_PROC
| FL_MODE26
},
389 {"arm6", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
390 {"arm60", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
391 {"arm600", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
392 {"arm610", FL_MODE26
| FL_MODE32
},
393 {"arm620", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
394 {"arm7", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
395 /* arm7m doesn't exist on its own, but only with D, (and I), but
396 those don't alter the code, so arm7m is sometimes used. */
397 {"arm7m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
398 {"arm7d", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
399 {"arm7dm", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
400 {"arm7di", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
401 {"arm7dmi", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
402 {"arm70", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
403 {"arm700", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
404 {"arm700i", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
405 {"arm710", FL_MODE26
| FL_MODE32
},
406 {"arm720", FL_MODE26
| FL_MODE32
},
407 {"arm710c", FL_MODE26
| FL_MODE32
},
408 {"arm7100", FL_MODE26
| FL_MODE32
},
409 {"arm7500", FL_MODE26
| FL_MODE32
},
410 /* Doesn't have an external co-proc, but does have embedded fpa. */
411 {"arm7500fe", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
412 /* V4 Architecture Processors */
413 {"arm7tdmi", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
414 {"arm710t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
415 {"arm720t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
416 {"arm740t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
417 {"arm8", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
418 {"arm810", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
419 {"arm9", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
420 {"arm920", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
421 {"arm920t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
422 {"arm940t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
423 {"arm9tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
424 {"arm9e", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
425 {"ep9312", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_CIRRUS
},
426 {"strongarm", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
427 {"strongarm110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
428 {"strongarm1100", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
429 {"strongarm1110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
430 /* V5 Architecture Processors */
431 {"arm10tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_ARCH5
},
432 {"arm1020t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_ARCH5
},
433 {"arm926ejs", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
| FL_ARCH5E
},
434 {"arm1026ejs", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
| FL_ARCH5E
},
435 {"xscale", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_STRONG
| FL_ARCH5
| FL_ARCH5E
| FL_XSCALE
},
436 {"iwmmxt", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_STRONG
| FL_ARCH5
| FL_ARCH5E
| FL_XSCALE
| FL_IWMMXT
},
437 /* V6 Architecture Processors */
438 {"arm1136js", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
| FL_ARCH5E
| FL_ARCH6J
},
439 {"arm1136jfs", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
| FL_ARCH5E
| FL_ARCH6J
| FL_VFPV2
},
443 static const struct processors all_architectures
[] =
445 /* ARM Architectures */
447 { "armv2", FL_CO_PROC
| FL_MODE26
},
448 { "armv2a", FL_CO_PROC
| FL_MODE26
},
449 { "armv3", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
450 { "armv3m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
451 { "armv4", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
},
452 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
453 implementations that support it, so we will leave it out for now. */
454 { "armv4t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
455 { "armv5", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
456 { "armv5t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
457 { "armv5te", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
| FL_ARCH5E
},
458 { "armv6j", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
| FL_ARCH5E
| FL_ARCH6J
},
459 { "ep9312", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_CIRRUS
},
460 {"iwmmxt", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_STRONG
| FL_ARCH5
| FL_ARCH5E
| FL_XSCALE
| FL_IWMMXT
},
464 /* This is a magic structure. The 'string' field is magically filled in
465 with a pointer to the value specified by the user on the command line
466 assuming that the user has specified such a value. */
468 struct arm_cpu_select arm_select
[] =
470 /* string name processors */
471 { NULL
, "-mcpu=", all_cores
},
472 { NULL
, "-march=", all_architectures
},
473 { NULL
, "-mtune=", all_cores
}
476 /* Return the number of bits set in VALUE. */
478 bit_count (unsigned long value
)
480 unsigned long count
= 0;
485 value
&= value
- 1; /* Clear the least-significant set bit. */
491 /* Fix up any incompatible options that the user has specified.
492 This has now turned into a maze. */
494 arm_override_options (void)
498 /* Set up the flags based on the cpu/architecture selected by the user. */
499 for (i
= ARRAY_SIZE (arm_select
); i
--;)
501 struct arm_cpu_select
* ptr
= arm_select
+ i
;
503 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
505 const struct processors
* sel
;
507 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
508 if (streq (ptr
->string
, sel
->name
))
511 tune_flags
= sel
->flags
;
514 /* If we have been given an architecture and a processor
515 make sure that they are compatible. We only generate
516 a warning though, and we prefer the CPU over the
518 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
519 warning ("switch -mcpu=%s conflicts with -march= switch",
522 insn_flags
= sel
->flags
;
528 if (sel
->name
== NULL
)
529 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
533 /* If the user did not specify a processor, choose one for them. */
536 const struct processors
* sel
;
538 static const struct cpu_default
541 const char *const name
;
545 { TARGET_CPU_arm2
, "arm2" },
546 { TARGET_CPU_arm6
, "arm6" },
547 { TARGET_CPU_arm610
, "arm610" },
548 { TARGET_CPU_arm710
, "arm710" },
549 { TARGET_CPU_arm7m
, "arm7m" },
550 { TARGET_CPU_arm7500fe
, "arm7500fe" },
551 { TARGET_CPU_arm7tdmi
, "arm7tdmi" },
552 { TARGET_CPU_arm8
, "arm8" },
553 { TARGET_CPU_arm810
, "arm810" },
554 { TARGET_CPU_arm9
, "arm9" },
555 { TARGET_CPU_strongarm
, "strongarm" },
556 { TARGET_CPU_xscale
, "xscale" },
557 { TARGET_CPU_ep9312
, "ep9312" },
558 { TARGET_CPU_iwmmxt
, "iwmmxt" },
559 { TARGET_CPU_arm926ej_s
, "arm926ej-s" },
560 { TARGET_CPU_arm1026ej_s
, "arm1026ej-s" },
561 { TARGET_CPU_arm1136j_s
, "arm1136j_s" },
562 { TARGET_CPU_arm1136jf_s
, "arm1136jf_s" },
563 { TARGET_CPU_generic
, "arm" },
566 const struct cpu_default
* def
;
568 /* Find the default. */
569 for (def
= cpu_defaults
; def
->name
; def
++)
570 if (def
->cpu
== TARGET_CPU_DEFAULT
)
573 /* Make sure we found the default CPU. */
574 if (def
->name
== NULL
)
577 /* Find the default CPU's flags. */
578 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
579 if (streq (def
->name
, sel
->name
))
582 if (sel
->name
== NULL
)
585 insn_flags
= sel
->flags
;
587 /* Now check to see if the user has specified some command line
588 switch that require certain abilities from the cpu. */
591 if (TARGET_INTERWORK
|| TARGET_THUMB
)
593 sought
|= (FL_THUMB
| FL_MODE32
);
595 /* Force apcs-32 to be used for interworking. */
596 target_flags
|= ARM_FLAG_APCS_32
;
598 /* There are no ARM processors that support both APCS-26 and
599 interworking. Therefore we force FL_MODE26 to be removed
600 from insn_flags here (if it was set), so that the search
601 below will always be able to find a compatible processor. */
602 insn_flags
&= ~FL_MODE26
;
604 else if (!TARGET_APCS_32
)
607 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
609 /* Try to locate a CPU type that supports all of the abilities
610 of the default CPU, plus the extra abilities requested by
612 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
613 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
616 if (sel
->name
== NULL
)
618 unsigned current_bit_count
= 0;
619 const struct processors
* best_fit
= NULL
;
621 /* Ideally we would like to issue an error message here
622 saying that it was not possible to find a CPU compatible
623 with the default CPU, but which also supports the command
624 line options specified by the programmer, and so they
625 ought to use the -mcpu=<name> command line option to
626 override the default CPU type.
628 Unfortunately this does not work with multilibing. We
629 need to be able to support multilibs for -mapcs-26 and for
630 -mthumb-interwork and there is no CPU that can support both
631 options. Instead if we cannot find a cpu that has both the
632 characteristics of the default cpu and the given command line
633 options we scan the array again looking for a best match. */
634 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
635 if ((sel
->flags
& sought
) == sought
)
639 count
= bit_count (sel
->flags
& insn_flags
);
641 if (count
>= current_bit_count
)
644 current_bit_count
= count
;
648 if (best_fit
== NULL
)
654 insn_flags
= sel
->flags
;
658 /* If tuning has not been specified, tune for whichever processor or
659 architecture has been selected. */
661 tune_flags
= insn_flags
;
663 /* Make sure that the processor choice does not conflict with any of the
664 other command line choices. */
665 if (TARGET_APCS_32
&& !(insn_flags
& FL_MODE32
))
667 /* If APCS-32 was not the default then it must have been set by the
668 user, so issue a warning message. If the user has specified
669 "-mapcs-32 -mcpu=arm2" then we loose here. */
670 if ((TARGET_DEFAULT
& ARM_FLAG_APCS_32
) == 0)
671 warning ("target CPU does not support APCS-32" );
672 target_flags
&= ~ARM_FLAG_APCS_32
;
674 else if (!TARGET_APCS_32
&& !(insn_flags
& FL_MODE26
))
676 warning ("target CPU does not support APCS-26" );
677 target_flags
|= ARM_FLAG_APCS_32
;
680 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
682 warning ("target CPU does not support interworking" );
683 target_flags
&= ~ARM_FLAG_INTERWORK
;
686 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
688 warning ("target CPU does not support THUMB instructions");
689 target_flags
&= ~ARM_FLAG_THUMB
;
692 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
694 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
695 target_flags
&= ~ARM_FLAG_APCS_FRAME
;
698 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
699 from here where no function is being compiled currently. */
700 if ((target_flags
& (THUMB_FLAG_LEAF_BACKTRACE
| THUMB_FLAG_BACKTRACE
))
702 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
704 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
705 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
707 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
708 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
710 /* If interworking is enabled then APCS-32 must be selected as well. */
711 if (TARGET_INTERWORK
)
714 warning ("interworking forces APCS-32 to be used" );
715 target_flags
|= ARM_FLAG_APCS_32
;
718 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
720 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
721 target_flags
|= ARM_FLAG_APCS_FRAME
;
724 if (TARGET_POKE_FUNCTION_NAME
)
725 target_flags
|= ARM_FLAG_APCS_FRAME
;
727 if (TARGET_APCS_REENT
&& flag_pic
)
728 error ("-fpic and -mapcs-reent are incompatible");
730 if (TARGET_APCS_REENT
)
731 warning ("APCS reentrant code not supported. Ignored");
733 /* If this target is normally configured to use APCS frames, warn if they
734 are turned off and debugging is turned on. */
736 && write_symbols
!= NO_DEBUG
737 && !TARGET_APCS_FRAME
738 && (TARGET_DEFAULT
& ARM_FLAG_APCS_FRAME
))
739 warning ("-g with -mno-apcs-frame may not give sensible debugging");
741 /* If stack checking is disabled, we can use r10 as the PIC register,
742 which keeps r9 available. */
744 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
746 if (TARGET_APCS_FLOAT
)
747 warning ("passing floating point arguments in fp regs not yet supported");
749 /* Initialize boolean versions of the flags, for use in the arm.md file. */
750 arm_fast_multiply
= (insn_flags
& FL_FAST_MULT
) != 0;
751 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
752 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
753 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
754 arm_arch_xscale
= (insn_flags
& FL_XSCALE
) != 0;
756 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
757 arm_is_strong
= (tune_flags
& FL_STRONG
) != 0;
758 thumb_code
= (TARGET_ARM
== 0);
759 arm_is_6_or_7
= (((tune_flags
& (FL_MODE26
| FL_MODE32
))
760 && !(tune_flags
& FL_ARCH4
))) != 0;
761 arm_tune_xscale
= (tune_flags
& FL_XSCALE
) != 0;
762 arm_is_cirrus
= (tune_flags
& FL_CIRRUS
) != 0;
763 arm_arch_iwmmxt
= (insn_flags
& FL_IWMMXT
) != 0;
765 if (TARGET_IWMMXT
&& (! TARGET_ATPCS
))
766 target_flags
|= ARM_FLAG_ATPCS
;
770 arm_fpu_tune
= FPUTYPE_MAVERICK
;
772 /* Ignore -mhard-float if -mcpu=ep9312. */
773 if (TARGET_HARD_FLOAT
)
774 target_flags
^= ARM_FLAG_SOFT_FLOAT
;
777 /* Default value for floating point code... if no co-processor
778 bus, then schedule for emulated floating point. Otherwise,
779 assume the user has an FPA.
780 Note: this does not prevent use of floating point instructions,
781 -msoft-float does that. */
782 arm_fpu_tune
= (tune_flags
& FL_CO_PROC
) ? FPUTYPE_FPA
: FPUTYPE_FPA_EMU3
;
786 if (streq (target_fp_name
, "2"))
787 arm_fpu_arch
= FPUTYPE_FPA_EMU2
;
788 else if (streq (target_fp_name
, "3"))
789 arm_fpu_arch
= FPUTYPE_FPA_EMU3
;
791 error ("invalid floating point emulation option: -mfpe-%s",
795 arm_fpu_arch
= FPUTYPE_DEFAULT
;
799 if (arm_fpu_tune
== FPUTYPE_FPA_EMU3
)
800 arm_fpu_tune
= FPUTYPE_FPA_EMU2
;
801 else if (arm_fpu_tune
== FPUTYPE_MAVERICK
)
802 warning ("-mfpe switch not supported by ep9312 target cpu - ignored.");
803 else if (arm_fpu_tune
!= FPUTYPE_FPA
)
804 arm_fpu_tune
= FPUTYPE_FPA_EMU2
;
807 /* For arm2/3 there is no need to do any scheduling if there is only
808 a floating point emulator, or we are doing software floating-point. */
809 if ((TARGET_SOFT_FLOAT
|| arm_fpu_tune
!= FPUTYPE_FPA
)
810 && (tune_flags
& FL_MODE32
) == 0)
811 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
813 arm_prgmode
= TARGET_APCS_32
? PROG_MODE_PROG32
: PROG_MODE_PROG26
;
815 if (structure_size_string
!= NULL
)
817 int size
= strtol (structure_size_string
, NULL
, 0);
819 if (size
== 8 || size
== 32)
820 arm_structure_size_boundary
= size
;
822 warning ("structure size boundary can only be set to 8 or 32");
825 if (arm_pic_register_string
!= NULL
)
827 int pic_register
= decode_reg_name (arm_pic_register_string
);
830 warning ("-mpic-register= is useless without -fpic");
832 /* Prevent the user from choosing an obviously stupid PIC register. */
833 else if (pic_register
< 0 || call_used_regs
[pic_register
]
834 || pic_register
== HARD_FRAME_POINTER_REGNUM
835 || pic_register
== STACK_POINTER_REGNUM
836 || pic_register
>= PC_REGNUM
)
837 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
839 arm_pic_register
= pic_register
;
842 if (TARGET_THUMB
&& flag_schedule_insns
)
844 /* Don't warn since it's on by default in -O2. */
845 flag_schedule_insns
= 0;
850 /* There's some dispute as to whether this should be 1 or 2. However,
851 experiments seem to show that in pathological cases a setting of
852 1 degrades less severly than a setting of 2. This could change if
853 other parts of the compiler change their behavior. */
854 arm_constant_limit
= 1;
856 /* If optimizing for size, bump the number of instructions that we
857 are prepared to conditionally execute (even on a StrongARM). */
858 max_insns_skipped
= 6;
862 /* For processors with load scheduling, it never costs more than
863 2 cycles to load a constant, and the load scheduler may well
865 if (tune_flags
& FL_LDSCHED
)
866 arm_constant_limit
= 1;
868 /* On XScale the longer latency of a load makes it more difficult
869 to achieve a good schedule, so it's faster to synthesize
870 constants that can be done in two insns. */
872 arm_constant_limit
= 2;
874 /* StrongARM has early execution of branches, so a sequence
875 that is worth skipping is shorter. */
877 max_insns_skipped
= 3;
880 /* Register global variables with the garbage collector. */
885 arm_add_gc_roots (void)
887 gcc_obstack_init(&minipool_obstack
);
888 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
891 /* A table of known ARM exception types.
892 For use with the interrupt function attribute. */
896 const char *const arg
;
897 const unsigned long return_value
;
901 static const isr_attribute_arg isr_attribute_args
[] =
903 { "IRQ", ARM_FT_ISR
},
904 { "irq", ARM_FT_ISR
},
905 { "FIQ", ARM_FT_FIQ
},
906 { "fiq", ARM_FT_FIQ
},
907 { "ABORT", ARM_FT_ISR
},
908 { "abort", ARM_FT_ISR
},
909 { "ABORT", ARM_FT_ISR
},
910 { "abort", ARM_FT_ISR
},
911 { "UNDEF", ARM_FT_EXCEPTION
},
912 { "undef", ARM_FT_EXCEPTION
},
913 { "SWI", ARM_FT_EXCEPTION
},
914 { "swi", ARM_FT_EXCEPTION
},
915 { NULL
, ARM_FT_NORMAL
}
918 /* Returns the (interrupt) function type of the current
919 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
922 arm_isr_value (tree argument
)
924 const isr_attribute_arg
* ptr
;
927 /* No argument - default to IRQ. */
928 if (argument
== NULL_TREE
)
931 /* Get the value of the argument. */
932 if (TREE_VALUE (argument
) == NULL_TREE
933 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
934 return ARM_FT_UNKNOWN
;
936 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
938 /* Check it against the list of known arguments. */
939 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
940 if (streq (arg
, ptr
->arg
))
941 return ptr
->return_value
;
943 /* An unrecognized interrupt type. */
944 return ARM_FT_UNKNOWN
;
947 /* Computes the type of the current function. */
950 arm_compute_func_type (void)
952 unsigned long type
= ARM_FT_UNKNOWN
;
956 if (TREE_CODE (current_function_decl
) != FUNCTION_DECL
)
959 /* Decide if the current function is volatile. Such functions
960 never return, and many memory cycles can be saved by not storing
961 register values that will never be needed again. This optimization
962 was added to speed up context switching in a kernel application. */
964 && current_function_nothrow
965 && TREE_THIS_VOLATILE (current_function_decl
))
966 type
|= ARM_FT_VOLATILE
;
968 if (current_function_needs_context
)
969 type
|= ARM_FT_NESTED
;
971 attr
= DECL_ATTRIBUTES (current_function_decl
);
973 a
= lookup_attribute ("naked", attr
);
975 type
|= ARM_FT_NAKED
;
977 if (cfun
->machine
->eh_epilogue_sp_ofs
!= NULL_RTX
)
978 type
|= ARM_FT_EXCEPTION_HANDLER
;
981 a
= lookup_attribute ("isr", attr
);
983 a
= lookup_attribute ("interrupt", attr
);
986 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
988 type
|= arm_isr_value (TREE_VALUE (a
));
994 /* Returns the type of the current function. */
997 arm_current_func_type (void)
999 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
1000 cfun
->machine
->func_type
= arm_compute_func_type ();
1002 return cfun
->machine
->func_type
;
1005 /* Return 1 if it is possible to return using a single instruction.
1006 If SIBLING is non-null, this is a test for a return before a sibling
1007 call. SIBLING is the call insn, so we can examine its register usage. */
1010 use_return_insn (int iscond
, rtx sibling
)
1013 unsigned int func_type
;
1014 unsigned long saved_int_regs
;
1015 unsigned HOST_WIDE_INT stack_adjust
;
1017 /* Never use a return instruction before reload has run. */
1018 if (!reload_completed
)
1021 func_type
= arm_current_func_type ();
1023 /* Naked functions and volatile functions need special
1025 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
1028 /* So do interrupt functions that use the frame pointer. */
1029 if (IS_INTERRUPT (func_type
) && frame_pointer_needed
)
1032 stack_adjust
= arm_get_frame_size () + current_function_outgoing_args_size
;
1034 /* As do variadic functions. */
1035 if (current_function_pretend_args_size
1036 || cfun
->machine
->uses_anonymous_args
1037 /* Or if the function calls __builtin_eh_return () */
1038 || ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
1039 /* Or if the function calls alloca */
1040 || current_function_calls_alloca
1041 /* Or if there is a stack adjustment. However, if the stack pointer
1042 is saved on the stack, we can use a pre-incrementing stack load. */
1043 || !(stack_adjust
== 0 || (frame_pointer_needed
&& stack_adjust
== 4)))
1046 saved_int_regs
= arm_compute_save_reg_mask ();
1048 /* Unfortunately, the insn
1050 ldmib sp, {..., sp, ...}
1052 triggers a bug on most SA-110 based devices, such that the stack
1053 pointer won't be correctly restored if the instruction takes a
1054 page fault. We work around this problem by poping r3 along with
1055 the other registers, since that is never slower than executing
1056 another instruction.
1058 We test for !arm_arch5 here, because code for any architecture
1059 less than this could potentially be run on one of the buggy
1061 if (stack_adjust
== 4 && !arm_arch5
)
1063 /* Validate that r3 is a call-clobbered register (always true in
1064 the default abi) ... */
1065 if (!call_used_regs
[3])
1068 /* ... that it isn't being used for a return value (always true
1069 until we implement return-in-regs), or for a tail-call
1073 if (GET_CODE (sibling
) != CALL_INSN
)
1076 if (find_regno_fusage (sibling
, USE
, 3))
1080 /* ... and that there are no call-saved registers in r0-r2
1081 (always true in the default ABI). */
1082 if (saved_int_regs
& 0x7)
1086 /* Can't be done if interworking with Thumb, and any registers have been
1088 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
1091 /* On StrongARM, conditional returns are expensive if they aren't
1092 taken and multiple registers have been stacked. */
1093 if (iscond
&& arm_is_strong
)
1095 /* Conditional return when just the LR is stored is a simple
1096 conditional-load instruction, that's not expensive. */
1097 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
1100 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
1104 /* If there are saved registers but the LR isn't saved, then we need
1105 two instructions for the return. */
1106 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
1109 /* Can't be done if any of the FPA regs are pushed,
1110 since this also requires an insn. */
1111 if (TARGET_HARD_FLOAT
)
1112 for (regno
= FIRST_ARM_FP_REGNUM
; regno
<= LAST_ARM_FP_REGNUM
; regno
++)
1113 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
1116 if (TARGET_REALLY_IWMMXT
)
1117 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
1118 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1124 /* Return TRUE if int I is a valid immediate ARM constant. */
1127 const_ok_for_arm (HOST_WIDE_INT i
)
1129 unsigned HOST_WIDE_INT mask
= ~(unsigned HOST_WIDE_INT
)0xFF;
1131 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1132 be all zero, or all one. */
1133 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
1134 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
1135 != ((~(unsigned HOST_WIDE_INT
) 0)
1136 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
1139 /* Fast return for 0 and powers of 2 */
1140 if ((i
& (i
- 1)) == 0)
1145 if ((i
& mask
& (unsigned HOST_WIDE_INT
) 0xffffffff) == 0)
1148 (mask
<< 2) | ((mask
& (unsigned HOST_WIDE_INT
) 0xffffffff)
1149 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT
) 0xffffffff;
1151 while (mask
!= ~(unsigned HOST_WIDE_INT
) 0xFF);
1156 /* Return true if I is a valid constant for the operation CODE. */
1158 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
1160 if (const_ok_for_arm (i
))
1166 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1168 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1174 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1181 /* Emit a sequence of insns to handle a large constant.
1182 CODE is the code of the operation required, it can be any of SET, PLUS,
1183 IOR, AND, XOR, MINUS;
1184 MODE is the mode in which the operation is being performed;
1185 VAL is the integer to operate on;
1186 SOURCE is the other operand (a register, or a null-pointer for SET);
1187 SUBTARGETS means it is safe to create scratch registers if that will
1188 either produce a simpler sequence, or we will want to cse the values.
1189 Return value is the number of insns emitted. */
1192 arm_split_constant (enum rtx_code code
, enum machine_mode mode
,
1193 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
1195 if (subtargets
|| code
== SET
1196 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1197 && REGNO (target
) != REGNO (source
)))
1199 /* After arm_reorg has been called, we can't fix up expensive
1200 constants by pushing them into memory so we must synthesize
1201 them in-line, regardless of the cost. This is only likely to
1202 be more costly on chips that have load delay slots and we are
1203 compiling without running the scheduler (so no splitting
1204 occurred before the final instruction emission).
1206 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1208 if (!after_arm_reorg
1209 && (arm_gen_constant (code
, mode
, val
, target
, source
, 1, 0)
1210 > arm_constant_limit
+ (code
!= SET
)))
1214 /* Currently SET is the only monadic value for CODE, all
1215 the rest are diadic. */
1216 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1221 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1223 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1224 /* For MINUS, the value is subtracted from, since we never
1225 have subtraction of a constant. */
1227 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1228 gen_rtx_MINUS (mode
, temp
, source
)));
1230 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1231 gen_rtx (code
, mode
, source
, temp
)));
1237 return arm_gen_constant (code
, mode
, val
, target
, source
, subtargets
, 1);
1241 count_insns_for_constant (HOST_WIDE_INT remainder
, int i
)
1243 HOST_WIDE_INT temp1
;
1251 if (remainder
& (3 << (i
- 2)))
1256 temp1
= remainder
& ((0x0ff << end
)
1257 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1258 remainder
&= ~temp1
;
1263 } while (remainder
);
1267 /* As above, but extra parameter GENERATE which, if clear, suppresses
1271 arm_gen_constant (enum rtx_code code
, enum machine_mode mode
,
1272 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
,
1277 int can_negate_initial
= 0;
1280 int num_bits_set
= 0;
1281 int set_sign_bit_copies
= 0;
1282 int clear_sign_bit_copies
= 0;
1283 int clear_zero_bit_copies
= 0;
1284 int set_zero_bit_copies
= 0;
1286 unsigned HOST_WIDE_INT temp1
, temp2
;
1287 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1289 /* Find out which operations are safe for a given CODE. Also do a quick
1290 check for degenerate cases; these can occur when DImode operations
1302 can_negate_initial
= 1;
1306 if (remainder
== 0xffffffff)
1309 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1310 GEN_INT (ARM_SIGN_EXTEND (val
))));
1315 if (reload_completed
&& rtx_equal_p (target
, source
))
1318 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1327 emit_insn (gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1330 if (remainder
== 0xffffffff)
1332 if (reload_completed
&& rtx_equal_p (target
, source
))
1335 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1344 if (reload_completed
&& rtx_equal_p (target
, source
))
1347 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1350 if (remainder
== 0xffffffff)
1353 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1354 gen_rtx_NOT (mode
, source
)));
1358 /* We don't know how to handle this yet below. */
1362 /* We treat MINUS as (val - source), since (source - val) is always
1363 passed as (source + (-val)). */
1367 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1368 gen_rtx_NEG (mode
, source
)));
1371 if (const_ok_for_arm (val
))
1374 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1375 gen_rtx_MINUS (mode
, GEN_INT (val
),
1387 /* If we can do it in one insn get out quickly. */
1388 if (const_ok_for_arm (val
)
1389 || (can_negate_initial
&& const_ok_for_arm (-val
))
1390 || (can_invert
&& const_ok_for_arm (~val
)))
1393 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1394 (source
? gen_rtx (code
, mode
, source
,
1400 /* Calculate a few attributes that may be useful for specific
1402 for (i
= 31; i
>= 0; i
--)
1404 if ((remainder
& (1 << i
)) == 0)
1405 clear_sign_bit_copies
++;
1410 for (i
= 31; i
>= 0; i
--)
1412 if ((remainder
& (1 << i
)) != 0)
1413 set_sign_bit_copies
++;
1418 for (i
= 0; i
<= 31; i
++)
1420 if ((remainder
& (1 << i
)) == 0)
1421 clear_zero_bit_copies
++;
1426 for (i
= 0; i
<= 31; i
++)
1428 if ((remainder
& (1 << i
)) != 0)
1429 set_zero_bit_copies
++;
1437 /* See if we can do this by sign_extending a constant that is known
1438 to be negative. This is a good, way of doing it, since the shift
1439 may well merge into a subsequent insn. */
1440 if (set_sign_bit_copies
> 1)
1442 if (const_ok_for_arm
1443 (temp1
= ARM_SIGN_EXTEND (remainder
1444 << (set_sign_bit_copies
- 1))))
1448 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1449 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
1451 emit_insn (gen_ashrsi3 (target
, new_src
,
1452 GEN_INT (set_sign_bit_copies
- 1)));
1456 /* For an inverted constant, we will need to set the low bits,
1457 these will be shifted out of harm's way. */
1458 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1459 if (const_ok_for_arm (~temp1
))
1463 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1464 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
1466 emit_insn (gen_ashrsi3 (target
, new_src
,
1467 GEN_INT (set_sign_bit_copies
- 1)));
1473 /* See if we can generate this by setting the bottom (or the top)
1474 16 bits, and then shifting these into the other half of the
1475 word. We only look for the simplest cases, to do more would cost
1476 too much. Be careful, however, not to generate this when the
1477 alternative would take fewer insns. */
1478 if (val
& 0xffff0000)
1480 temp1
= remainder
& 0xffff0000;
1481 temp2
= remainder
& 0x0000ffff;
1483 /* Overlaps outside this range are best done using other methods. */
1484 for (i
= 9; i
< 24; i
++)
1486 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
1487 && !const_ok_for_arm (temp2
))
1489 rtx new_src
= (subtargets
1490 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1492 insns
= arm_gen_constant (code
, mode
, temp2
, new_src
,
1493 source
, subtargets
, generate
);
1496 emit_insn (gen_rtx_SET
1499 gen_rtx_ASHIFT (mode
, source
,
1506 /* Don't duplicate cases already considered. */
1507 for (i
= 17; i
< 24; i
++)
1509 if (((temp1
| (temp1
>> i
)) == remainder
)
1510 && !const_ok_for_arm (temp1
))
1512 rtx new_src
= (subtargets
1513 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1515 insns
= arm_gen_constant (code
, mode
, temp1
, new_src
,
1516 source
, subtargets
, generate
);
1520 (gen_rtx_SET (VOIDmode
, target
,
1523 gen_rtx_LSHIFTRT (mode
, source
,
1534 /* If we have IOR or XOR, and the constant can be loaded in a
1535 single instruction, and we can find a temporary to put it in,
1536 then this can be done in two instructions instead of 3-4. */
1538 /* TARGET can't be NULL if SUBTARGETS is 0 */
1539 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
1541 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
1545 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1547 emit_insn (gen_rtx_SET (VOIDmode
, sub
, GEN_INT (val
)));
1548 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1549 gen_rtx (code
, mode
, source
, sub
)));
1558 if (set_sign_bit_copies
> 8
1559 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
1563 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1564 rtx shift
= GEN_INT (set_sign_bit_copies
);
1566 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1568 gen_rtx_ASHIFT (mode
,
1571 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1573 gen_rtx_LSHIFTRT (mode
, sub
,
1579 if (set_zero_bit_copies
> 8
1580 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
1584 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1585 rtx shift
= GEN_INT (set_zero_bit_copies
);
1587 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1589 gen_rtx_LSHIFTRT (mode
,
1592 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1594 gen_rtx_ASHIFT (mode
, sub
,
1600 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
1604 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1605 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1606 gen_rtx_NOT (mode
, source
)));
1609 sub
= gen_reg_rtx (mode
);
1610 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1611 gen_rtx_AND (mode
, source
,
1613 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1614 gen_rtx_NOT (mode
, sub
)));
1621 /* See if two shifts will do 2 or more insn's worth of work. */
1622 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
1624 HOST_WIDE_INT shift_mask
= ((0xffffffff
1625 << (32 - clear_sign_bit_copies
))
1628 if ((remainder
| shift_mask
) != 0xffffffff)
1632 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1633 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1634 new_src
, source
, subtargets
, 1);
1639 rtx targ
= subtargets
? NULL_RTX
: target
;
1640 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1641 targ
, source
, subtargets
, 0);
1647 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1648 rtx shift
= GEN_INT (clear_sign_bit_copies
);
1650 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
1651 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
1657 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
1659 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
1661 if ((remainder
| shift_mask
) != 0xffffffff)
1665 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1667 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1668 new_src
, source
, subtargets
, 1);
1673 rtx targ
= subtargets
? NULL_RTX
: target
;
1675 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1676 targ
, source
, subtargets
, 0);
1682 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1683 rtx shift
= GEN_INT (clear_zero_bit_copies
);
1685 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
1686 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
1698 for (i
= 0; i
< 32; i
++)
1699 if (remainder
& (1 << i
))
1702 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
1703 remainder
= (~remainder
) & 0xffffffff;
1704 else if (code
== PLUS
&& num_bits_set
> 16)
1705 remainder
= (-remainder
) & 0xffffffff;
1712 /* Now try and find a way of doing the job in either two or three
1714 We start by looking for the largest block of zeros that are aligned on
1715 a 2-bit boundary, we then fill up the temps, wrapping around to the
1716 top of the word when we drop off the bottom.
1717 In the worst case this code should produce no more than four insns. */
1720 int best_consecutive_zeros
= 0;
1722 for (i
= 0; i
< 32; i
+= 2)
1724 int consecutive_zeros
= 0;
1726 if (!(remainder
& (3 << i
)))
1728 while ((i
< 32) && !(remainder
& (3 << i
)))
1730 consecutive_zeros
+= 2;
1733 if (consecutive_zeros
> best_consecutive_zeros
)
1735 best_consecutive_zeros
= consecutive_zeros
;
1736 best_start
= i
- consecutive_zeros
;
1742 /* So long as it won't require any more insns to do so, it's
1743 desirable to emit a small constant (in bits 0...9) in the last
1744 insn. This way there is more chance that it can be combined with
1745 a later addressing insn to form a pre-indexed load or store
1746 operation. Consider:
1748 *((volatile int *)0xe0000100) = 1;
1749 *((volatile int *)0xe0000110) = 2;
1751 We want this to wind up as:
1755 str rB, [rA, #0x100]
1757 str rB, [rA, #0x110]
1759 rather than having to synthesize both large constants from scratch.
1761 Therefore, we calculate how many insns would be required to emit
1762 the constant starting from `best_start', and also starting from
1763 zero (ie with bit 31 first to be output). If `best_start' doesn't
1764 yield a shorter sequence, we may as well use zero. */
1766 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
1767 && (count_insns_for_constant (remainder
, 0) <=
1768 count_insns_for_constant (remainder
, best_start
)))
1771 /* Now start emitting the insns. */
1779 if (remainder
& (3 << (i
- 2)))
1784 temp1
= remainder
& ((0x0ff << end
)
1785 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1786 remainder
&= ~temp1
;
1790 rtx new_src
, temp1_rtx
;
1792 if (code
== SET
|| code
== MINUS
)
1794 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
1795 if (can_invert
&& code
!= MINUS
)
1800 if (remainder
&& subtargets
)
1801 new_src
= gen_reg_rtx (mode
);
1806 else if (can_negate
)
1810 temp1
= trunc_int_for_mode (temp1
, mode
);
1811 temp1_rtx
= GEN_INT (temp1
);
1815 else if (code
== MINUS
)
1816 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
1818 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
1820 emit_insn (gen_rtx_SET (VOIDmode
, new_src
, temp1_rtx
));
1829 else if (code
== MINUS
)
1843 /* Canonicalize a comparison so that we are more likely to recognize it.
1844 This can be done for a few constant compares, where we can make the
1845 immediate value easier to load. */
1848 arm_canonicalize_comparison (enum rtx_code code
, rtx
* op1
)
1850 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
1860 if (i
!= ((((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1)) - 1)
1861 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
1863 *op1
= GEN_INT (i
+ 1);
1864 return code
== GT
? GE
: LT
;
1870 if (i
!= (((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1))
1871 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
1873 *op1
= GEN_INT (i
- 1);
1874 return code
== GE
? GT
: LE
;
1880 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
1881 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
1883 *op1
= GEN_INT (i
+ 1);
1884 return code
== GTU
? GEU
: LTU
;
1891 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
1893 *op1
= GEN_INT (i
- 1);
1894 return code
== GEU
? GTU
: LEU
;
1905 /* Decide whether a type should be returned in memory (true)
1906 or in a register (false). This is called by the macro
1907 RETURN_IN_MEMORY. */
1909 arm_return_in_memory (tree type
)
1913 if (!AGGREGATE_TYPE_P (type
))
1914 /* All simple types are returned in registers. */
1917 size
= int_size_in_bytes (type
);
1921 /* ATPCS returns aggregate types in memory only if they are
1922 larger than a word (or are variable size). */
1923 return (size
< 0 || size
> UNITS_PER_WORD
);
1926 /* For the arm-wince targets we choose to be compatible with Microsoft's
1927 ARM and Thumb compilers, which always return aggregates in memory. */
1929 /* All structures/unions bigger than one word are returned in memory.
1930 Also catch the case where int_size_in_bytes returns -1. In this case
1931 the aggregate is either huge or of variable size, and in either case
1932 we will want to return it via memory and not in a register. */
1933 if (size
< 0 || size
> UNITS_PER_WORD
)
1936 if (TREE_CODE (type
) == RECORD_TYPE
)
1940 /* For a struct the APCS says that we only return in a register
1941 if the type is 'integer like' and every addressable element
1942 has an offset of zero. For practical purposes this means
1943 that the structure can have at most one non bit-field element
1944 and that this element must be the first one in the structure. */
1946 /* Find the first field, ignoring non FIELD_DECL things which will
1947 have been created by C++. */
1948 for (field
= TYPE_FIELDS (type
);
1949 field
&& TREE_CODE (field
) != FIELD_DECL
;
1950 field
= TREE_CHAIN (field
))
1954 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1956 /* Check that the first field is valid for returning in a register. */
1958 /* ... Floats are not allowed */
1959 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1962 /* ... Aggregates that are not themselves valid for returning in
1963 a register are not allowed. */
1964 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1967 /* Now check the remaining fields, if any. Only bitfields are allowed,
1968 since they are not addressable. */
1969 for (field
= TREE_CHAIN (field
);
1971 field
= TREE_CHAIN (field
))
1973 if (TREE_CODE (field
) != FIELD_DECL
)
1976 if (!DECL_BIT_FIELD_TYPE (field
))
1983 if (TREE_CODE (type
) == UNION_TYPE
)
1987 /* Unions can be returned in registers if every element is
1988 integral, or can be returned in an integer register. */
1989 for (field
= TYPE_FIELDS (type
);
1991 field
= TREE_CHAIN (field
))
1993 if (TREE_CODE (field
) != FIELD_DECL
)
1996 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1999 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
2005 #endif /* not ARM_WINCE */
2007 /* Return all other types in memory. */
2011 /* Indicate whether or not words of a double are in big-endian order. */
2014 arm_float_words_big_endian (void)
2019 /* For FPA, float words are always big-endian. For VFP, floats words
2020 follow the memory system mode. */
2022 if (TARGET_HARD_FLOAT
)
2024 /* FIXME: TARGET_HARD_FLOAT currently implies FPA. */
2029 return (TARGET_BIG_END
? 1 : 0);
2034 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2035 for a call to a function whose data type is FNTYPE.
2036 For a library call, FNTYPE is NULL. */
2038 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
2039 rtx libname ATTRIBUTE_UNUSED
,
2040 tree fndecl ATTRIBUTE_UNUSED
)
2042 /* On the ARM, the offset starts at 0. */
2043 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fntype
)) ? 1 : 0);
2044 pcum
->iwmmxt_nregs
= 0;
2046 pcum
->call_cookie
= CALL_NORMAL
;
2048 if (TARGET_LONG_CALLS
)
2049 pcum
->call_cookie
= CALL_LONG
;
2051 /* Check for long call/short call attributes. The attributes
2052 override any command line option. */
2055 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
2056 pcum
->call_cookie
= CALL_SHORT
;
2057 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
2058 pcum
->call_cookie
= CALL_LONG
;
2061 /* Varargs vectors are treated the same as long long.
2062 named_count avoids having to change the way arm handles 'named' */
2063 pcum
->named_count
= 0;
2066 if (TARGET_REALLY_IWMMXT
&& fntype
)
2070 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
2072 fn_arg
= TREE_CHAIN (fn_arg
))
2073 pcum
->named_count
+= 1;
2075 if (! pcum
->named_count
)
2076 pcum
->named_count
= INT_MAX
;
2080 /* Determine where to put an argument to a function.
2081 Value is zero to push the argument on the stack,
2082 or a hard register in which to store the argument.
2084 MODE is the argument's machine mode.
2085 TYPE is the data type of the argument (as a tree).
2086 This is null for libcalls where that information may
2088 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2089 the preceding args and about the function being called.
2090 NAMED is nonzero if this argument is a named parameter
2091 (otherwise it is an extra parameter matching an ellipsis). */
2094 arm_function_arg (CUMULATIVE_ARGS
*pcum
, enum machine_mode mode
,
2095 tree type ATTRIBUTE_UNUSED
, int named
)
2097 if (TARGET_REALLY_IWMMXT
)
2099 if (VECTOR_MODE_SUPPORTED_P (mode
))
2101 /* varargs vectors are treated the same as long long.
2102 named_count avoids having to change the way arm handles 'named' */
2103 if (pcum
->named_count
<= pcum
->nargs
+ 1)
2105 if (pcum
->nregs
== 1)
2107 if (pcum
->nregs
<= 2)
2108 return gen_rtx_REG (mode
, pcum
->nregs
);
2112 else if (pcum
->iwmmxt_nregs
<= 9)
2113 return gen_rtx_REG (mode
, pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
2117 else if ((mode
== DImode
|| mode
== DFmode
) && pcum
->nregs
& 1)
2121 if (mode
== VOIDmode
)
2122 /* Compute operand 2 of the call insn. */
2123 return GEN_INT (pcum
->call_cookie
);
2125 if (!named
|| pcum
->nregs
>= NUM_ARG_REGS
)
2128 return gen_rtx_REG (mode
, pcum
->nregs
);
2131 /* Variable sized types are passed by reference. This is a GCC
2132 extension to the ARM ABI. */
2135 arm_function_arg_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2136 enum machine_mode mode ATTRIBUTE_UNUSED
,
2137 tree type
, int named ATTRIBUTE_UNUSED
)
2139 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
2142 /* Implement va_arg. */
2145 arm_va_arg (tree valist
, tree type
)
2147 /* Variable sized types are passed by reference. */
2148 if (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
2150 rtx addr
= std_expand_builtin_va_arg (valist
, build_pointer_type (type
));
2151 return gen_rtx_MEM (ptr_mode
, force_reg (Pmode
, addr
));
2154 if (FUNCTION_ARG_BOUNDARY (TYPE_MODE (type
), NULL
) == IWMMXT_ALIGNMENT
)
2159 /* Maintain 64-bit alignment of the valist pointer by
2160 constructing: valist = ((valist + (8 - 1)) & -8). */
2161 minus_eight
= build_int_2 (- (IWMMXT_ALIGNMENT
/ BITS_PER_UNIT
), -1);
2162 t
= build_int_2 ((IWMMXT_ALIGNMENT
/ BITS_PER_UNIT
) - 1, 0);
2163 t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
, t
);
2164 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
, minus_eight
);
2165 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
2166 TREE_SIDE_EFFECTS (t
) = 1;
2167 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2169 /* This is to stop the combine pass optimizing
2170 away the alignment adjustment. */
2171 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
2174 return std_expand_builtin_va_arg (valist
, type
);
2177 /* Encode the current state of the #pragma [no_]long_calls. */
2180 OFF
, /* No #pramgma [no_]long_calls is in effect. */
2181 LONG
, /* #pragma long_calls is in effect. */
2182 SHORT
/* #pragma no_long_calls is in effect. */
2185 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
2188 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2190 arm_pragma_long_calls
= LONG
;
2194 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2196 arm_pragma_long_calls
= SHORT
;
2200 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
2202 arm_pragma_long_calls
= OFF
;
2205 /* Table of machine attributes. */
2206 const struct attribute_spec arm_attribute_table
[] =
2208 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2209 /* Function calls made to this symbol must be done indirectly, because
2210 it may lie outside of the 26 bit addressing range of a normal function
2212 { "long_call", 0, 0, false, true, true, NULL
},
2213 /* Whereas these functions are always known to reside within the 26 bit
2214 addressing range. */
2215 { "short_call", 0, 0, false, true, true, NULL
},
2216 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2217 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2218 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2219 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2221 /* ARM/PE has three new attributes:
2223 dllexport - for exporting a function/variable that will live in a dll
2224 dllimport - for importing a function/variable from a dll
2226 Microsoft allows multiple declspecs in one __declspec, separating
2227 them with spaces. We do NOT support this. Instead, use __declspec
2230 { "dllimport", 0, 0, true, false, false, NULL
},
2231 { "dllexport", 0, 0, true, false, false, NULL
},
2232 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2234 { NULL
, 0, 0, false, false, false, NULL
}
2237 /* Handle an attribute requiring a FUNCTION_DECL;
2238 arguments as in struct attribute_spec.handler. */
2240 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
2241 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
2243 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2245 warning ("`%s' attribute only applies to functions",
2246 IDENTIFIER_POINTER (name
));
2247 *no_add_attrs
= true;
2253 /* Handle an "interrupt" or "isr" attribute;
2254 arguments as in struct attribute_spec.handler. */
2256 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
2261 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2263 warning ("`%s' attribute only applies to functions",
2264 IDENTIFIER_POINTER (name
));
2265 *no_add_attrs
= true;
2267 /* FIXME: the argument if any is checked for type attributes;
2268 should it be checked for decl ones? */
2272 if (TREE_CODE (*node
) == FUNCTION_TYPE
2273 || TREE_CODE (*node
) == METHOD_TYPE
)
2275 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2277 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2278 *no_add_attrs
= true;
2281 else if (TREE_CODE (*node
) == POINTER_TYPE
2282 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2283 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2284 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2286 *node
= build_type_copy (*node
);
2287 TREE_TYPE (*node
) = build_type_attribute_variant
2289 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2290 *no_add_attrs
= true;
2294 /* Possibly pass this attribute on from the type to a decl. */
2295 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2296 | (int) ATTR_FLAG_FUNCTION_NEXT
2297 | (int) ATTR_FLAG_ARRAY_NEXT
))
2299 *no_add_attrs
= true;
2300 return tree_cons (name
, args
, NULL_TREE
);
2304 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2312 /* Return 0 if the attributes for two types are incompatible, 1 if they
2313 are compatible, and 2 if they are nearly compatible (which causes a
2314 warning to be generated). */
2316 arm_comp_type_attributes (tree type1
, tree type2
)
2320 /* Check for mismatch of non-default calling convention. */
2321 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2324 /* Check for mismatched call attributes. */
2325 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2326 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2327 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2328 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2330 /* Only bother to check if an attribute is defined. */
2331 if (l1
| l2
| s1
| s2
)
2333 /* If one type has an attribute, the other must have the same attribute. */
2334 if ((l1
!= l2
) || (s1
!= s2
))
2337 /* Disallow mixed attributes. */
2338 if ((l1
& s2
) || (l2
& s1
))
2342 /* Check for mismatched ISR attribute. */
2343 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2345 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2346 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2348 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2355 /* Encode long_call or short_call attribute by prefixing
2356 symbol name in DECL with a special character FLAG. */
2358 arm_encode_call_attribute (tree decl
, int flag
)
2360 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2361 int len
= strlen (str
);
2364 /* Do not allow weak functions to be treated as short call. */
2365 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
2368 newstr
= alloca (len
+ 2);
2370 strcpy (newstr
+ 1, str
);
2372 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
2373 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2376 /* Assigns default attributes to newly defined type. This is used to
2377 set short_call/long_call attributes for function types of
2378 functions defined inside corresponding #pragma scopes. */
2380 arm_set_default_type_attributes (tree type
)
2382 /* Add __attribute__ ((long_call)) to all functions, when
2383 inside #pragma long_calls or __attribute__ ((short_call)),
2384 when inside #pragma no_long_calls. */
2385 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
2387 tree type_attr_list
, attr_name
;
2388 type_attr_list
= TYPE_ATTRIBUTES (type
);
2390 if (arm_pragma_long_calls
== LONG
)
2391 attr_name
= get_identifier ("long_call");
2392 else if (arm_pragma_long_calls
== SHORT
)
2393 attr_name
= get_identifier ("short_call");
2397 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
2398 TYPE_ATTRIBUTES (type
) = type_attr_list
;
2402 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2403 defined within the current compilation unit. If this cannot be
2404 determined, then 0 is returned. */
2406 current_file_function_operand (rtx sym_ref
)
2408 /* This is a bit of a fib. A function will have a short call flag
2409 applied to its name if it has the short call attribute, or it has
2410 already been defined within the current compilation unit. */
2411 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
2414 /* The current function is always defined within the current compilation
2415 unit. if it s a weak definition however, then this may not be the real
2416 definition of the function, and so we have to say no. */
2417 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
2418 && !DECL_WEAK (current_function_decl
))
2421 /* We cannot make the determination - default to returning 0. */
2425 /* Return nonzero if a 32 bit "long_call" should be generated for
2426 this call. We generate a long_call if the function:
2428 a. has an __attribute__((long call))
2429 or b. is within the scope of a #pragma long_calls
2430 or c. the -mlong-calls command line switch has been specified
2432 However we do not generate a long call if the function:
2434 d. has an __attribute__ ((short_call))
2435 or e. is inside the scope of a #pragma no_long_calls
2436 or f. has an __attribute__ ((section))
2437 or g. is defined within the current compilation unit.
2439 This function will be called by C fragments contained in the machine
2440 description file. CALL_REF and CALL_COOKIE correspond to the matched
2441 rtl operands. CALL_SYMBOL is used to distinguish between
2442 two different callers of the function. It is set to 1 in the
2443 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2444 and "call_value" patterns. This is because of the difference in the
2445 SYM_REFs passed by these patterns. */
2447 arm_is_longcall_p (rtx sym_ref
, int call_cookie
, int call_symbol
)
2451 if (GET_CODE (sym_ref
) != MEM
)
2454 sym_ref
= XEXP (sym_ref
, 0);
2457 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
2460 if (call_cookie
& CALL_SHORT
)
2463 if (TARGET_LONG_CALLS
&& flag_function_sections
)
2466 if (current_file_function_operand (sym_ref
))
2469 return (call_cookie
& CALL_LONG
)
2470 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
2471 || TARGET_LONG_CALLS
;
2474 /* Return nonzero if it is ok to make a tail-call to DECL. */
2476 arm_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
2478 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
2480 if (cfun
->machine
->sibcall_blocked
)
2483 /* Never tailcall something for which we have no decl, or if we
2484 are in Thumb mode. */
2485 if (decl
== NULL
|| TARGET_THUMB
)
2488 /* Get the calling method. */
2489 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2490 call_type
= CALL_SHORT
;
2491 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2492 call_type
= CALL_LONG
;
2494 /* Cannot tail-call to long calls, since these are out of range of
2495 a branch instruction. However, if not compiling PIC, we know
2496 we can reach the symbol if it is in this compilation unit. */
2497 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
2500 /* If we are interworking and the function is not declared static
2501 then we can't tail-call it unless we know that it exists in this
2502 compilation unit (since it might be a Thumb routine). */
2503 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
2506 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2507 if (IS_INTERRUPT (arm_current_func_type ()))
2510 /* Everything else is ok. */
2515 /* Addressing mode support functions. */
2517 /* Return nonzero if X is a legitimate immediate operand when compiling
2520 legitimate_pic_operand_p (rtx x
)
2524 && (GET_CODE (x
) == SYMBOL_REF
2525 || (GET_CODE (x
) == CONST
2526 && GET_CODE (XEXP (x
, 0)) == PLUS
2527 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
2534 legitimize_pic_address (rtx orig
, enum machine_mode mode
, rtx reg
)
2536 if (GET_CODE (orig
) == SYMBOL_REF
2537 || GET_CODE (orig
) == LABEL_REF
)
2539 #ifndef AOF_ASSEMBLER
2540 rtx pic_ref
, address
;
2550 reg
= gen_reg_rtx (Pmode
);
2555 #ifdef AOF_ASSEMBLER
2556 /* The AOF assembler can generate relocations for these directly, and
2557 understands that the PIC register has to be added into the offset. */
2558 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
2561 address
= gen_reg_rtx (Pmode
);
2566 emit_insn (gen_pic_load_addr_arm (address
, orig
));
2568 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
2570 if ((GET_CODE (orig
) == LABEL_REF
2571 || (GET_CODE (orig
) == SYMBOL_REF
&&
2572 SYMBOL_REF_LOCAL_P (orig
)))
2574 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
2577 pic_ref
= gen_rtx_MEM (Pmode
,
2578 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
2580 RTX_UNCHANGING_P (pic_ref
) = 1;
2583 insn
= emit_move_insn (reg
, pic_ref
);
2585 current_function_uses_pic_offset_table
= 1;
2586 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2588 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
2592 else if (GET_CODE (orig
) == CONST
)
2596 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2597 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2605 reg
= gen_reg_rtx (Pmode
);
2608 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2610 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2611 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2612 base
== reg
? 0 : reg
);
2617 if (GET_CODE (offset
) == CONST_INT
)
2619 /* The base register doesn't really matter, we only want to
2620 test the index for the appropriate mode. */
2621 if (!arm_legitimate_index_p (mode
, offset
, 0))
2623 if (!no_new_pseudos
)
2624 offset
= force_reg (Pmode
, offset
);
2629 if (GET_CODE (offset
) == CONST_INT
)
2630 return plus_constant (base
, INTVAL (offset
));
2633 if (GET_MODE_SIZE (mode
) > 4
2634 && (GET_MODE_CLASS (mode
) == MODE_INT
2635 || TARGET_SOFT_FLOAT
))
2637 emit_insn (gen_addsi3 (reg
, base
, offset
));
2641 return gen_rtx_PLUS (Pmode
, base
, offset
);
2647 /* Generate code to load the PIC register. PROLOGUE is true if
2648 called from arm_expand_prologue (in which case we want the
2649 generated insns at the start of the function); false if called
2650 by an exception receiver that needs the PIC register reloaded
2651 (in which case the insns are just dumped at the current location). */
2653 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED
)
2655 #ifndef AOF_ASSEMBLER
2656 rtx l1
, pic_tmp
, pic_tmp2
, seq
, pic_rtx
;
2657 rtx global_offset_table
;
2659 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
2666 l1
= gen_label_rtx ();
2668 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
2669 /* On the ARM the PC register contains 'dot + 8' at the time of the
2670 addition, on the Thumb it is 'dot + 4'. */
2671 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), TARGET_ARM
? 8 : 4);
2673 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
2674 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
2676 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
2678 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
2682 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
2683 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
2687 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
2688 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
, l1
));
2694 emit_insn_after (seq
, get_insns ());
2698 /* Need to emit this whether or not we obey regdecls,
2699 since setjmp/longjmp can cause life info to screw up. */
2700 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
2701 #endif /* AOF_ASSEMBLER */
2704 /* Return nonzero if X is valid as an ARM state addressing register. */
2706 arm_address_register_rtx_p (rtx x
, int strict_p
)
2710 if (GET_CODE (x
) != REG
)
2716 return ARM_REGNO_OK_FOR_BASE_P (regno
);
2718 return (regno
<= LAST_ARM_REGNUM
2719 || regno
>= FIRST_PSEUDO_REGISTER
2720 || regno
== FRAME_POINTER_REGNUM
2721 || regno
== ARG_POINTER_REGNUM
);
2724 /* Return nonzero if X is a valid ARM state address operand. */
2726 arm_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
2728 if (arm_address_register_rtx_p (x
, strict_p
))
2731 else if (GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_DEC
)
2732 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
2734 else if ((GET_CODE (x
) == POST_MODIFY
|| GET_CODE (x
) == PRE_MODIFY
)
2735 && GET_MODE_SIZE (mode
) <= 4
2736 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
2737 && GET_CODE (XEXP (x
, 1)) == PLUS
2738 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2739 return arm_legitimate_index_p (mode
, XEXP (XEXP (x
, 1), 1), strict_p
);
2741 /* After reload constants split into minipools will have addresses
2742 from a LABEL_REF. */
2743 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
2744 && (GET_CODE (x
) == LABEL_REF
2745 || (GET_CODE (x
) == CONST
2746 && GET_CODE (XEXP (x
, 0)) == PLUS
2747 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
2748 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
2751 else if (mode
== TImode
)
2754 else if (mode
== DImode
|| (TARGET_SOFT_FLOAT
&& mode
== DFmode
))
2756 if (GET_CODE (x
) == PLUS
2757 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
2758 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2760 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2762 if (val
== 4 || val
== -4 || val
== -8)
2767 else if (GET_CODE (x
) == PLUS
)
2769 rtx xop0
= XEXP (x
, 0);
2770 rtx xop1
= XEXP (x
, 1);
2772 return ((arm_address_register_rtx_p (xop0
, strict_p
)
2773 && arm_legitimate_index_p (mode
, xop1
, strict_p
))
2774 || (arm_address_register_rtx_p (xop1
, strict_p
)
2775 && arm_legitimate_index_p (mode
, xop0
, strict_p
)));
2779 /* Reload currently can't handle MINUS, so disable this for now */
2780 else if (GET_CODE (x
) == MINUS
)
2782 rtx xop0
= XEXP (x
, 0);
2783 rtx xop1
= XEXP (x
, 1);
2785 return (arm_address_register_rtx_p (xop0
, strict_p
)
2786 && arm_legitimate_index_p (mode
, xop1
, strict_p
));
2790 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
2791 && GET_CODE (x
) == SYMBOL_REF
2792 && CONSTANT_POOL_ADDRESS_P (x
)
2794 && symbol_mentioned_p (get_pool_constant (x
))))
2797 else if ((GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == POST_DEC
)
2798 && (GET_MODE_SIZE (mode
) <= 4)
2799 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
))
2805 /* Return nonzero if INDEX is valid for an address index operand in
2808 arm_legitimate_index_p (enum machine_mode mode
, rtx index
, int strict_p
)
2810 HOST_WIDE_INT range
;
2811 enum rtx_code code
= GET_CODE (index
);
2813 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2814 return (code
== CONST_INT
&& INTVAL (index
) < 1024
2815 && INTVAL (index
) > -1024
2816 && (INTVAL (index
) & 3) == 0);
2819 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
|| mode
== DImode
))
2820 return (code
== CONST_INT
2821 && INTVAL (index
) < 255
2822 && INTVAL (index
) > -255);
2824 if (arm_address_register_rtx_p (index
, strict_p
)
2825 && GET_MODE_SIZE (mode
) <= 4)
2828 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
2829 return (code
== CONST_INT
2830 && INTVAL (index
) < 256
2831 && INTVAL (index
) > -256);
2833 /* XXX What about ldrsb? */
2834 if (GET_MODE_SIZE (mode
) <= 4 && code
== MULT
2835 && (!arm_arch4
|| (mode
) != HImode
))
2837 rtx xiop0
= XEXP (index
, 0);
2838 rtx xiop1
= XEXP (index
, 1);
2840 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
2841 && power_of_two_operand (xiop1
, SImode
))
2842 || (arm_address_register_rtx_p (xiop1
, strict_p
)
2843 && power_of_two_operand (xiop0
, SImode
)));
2846 if (GET_MODE_SIZE (mode
) <= 4
2847 && (code
== LSHIFTRT
|| code
== ASHIFTRT
2848 || code
== ASHIFT
|| code
== ROTATERT
)
2849 && (!arm_arch4
|| (mode
) != HImode
))
2851 rtx op
= XEXP (index
, 1);
2853 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
2854 && GET_CODE (op
) == CONST_INT
2856 && INTVAL (op
) <= 31);
2859 /* XXX For ARM v4 we may be doing a sign-extend operation during the
2860 load, but that has a restricted addressing range and we are unable
2861 to tell here whether that is the case. To be safe we restrict all
2862 loads to that range. */
2863 range
= ((mode
) == HImode
|| (mode
) == QImode
)
2864 ? (arm_arch4
? 256 : 4095) : 4096;
2866 return (code
== CONST_INT
2867 && INTVAL (index
) < range
2868 && INTVAL (index
) > -range
);
2871 /* Return nonzero if X is valid as an ARM state addressing register. */
2873 thumb_base_register_rtx_p (rtx x
, enum machine_mode mode
, int strict_p
)
2877 if (GET_CODE (x
) != REG
)
2883 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
2885 return (regno
<= LAST_LO_REGNUM
2886 || regno
>= FIRST_PSEUDO_REGISTER
2887 || regno
== FRAME_POINTER_REGNUM
2888 || (GET_MODE_SIZE (mode
) >= 4
2889 && (regno
== STACK_POINTER_REGNUM
2890 || x
== hard_frame_pointer_rtx
2891 || x
== arg_pointer_rtx
)));
2894 /* Return nonzero if x is a legitimate index register. This is the case
2895 for any base register that can access a QImode object. */
2897 thumb_index_register_rtx_p (rtx x
, int strict_p
)
2899 return thumb_base_register_rtx_p (x
, QImode
, strict_p
);
2902 /* Return nonzero if x is a legitimate Thumb-state address.
2904 The AP may be eliminated to either the SP or the FP, so we use the
2905 least common denominator, e.g. SImode, and offsets from 0 to 64.
2907 ??? Verify whether the above is the right approach.
2909 ??? Also, the FP may be eliminated to the SP, so perhaps that
2910 needs special handling also.
2912 ??? Look at how the mips16 port solves this problem. It probably uses
2913 better ways to solve some of these problems.
2915 Although it is not incorrect, we don't accept QImode and HImode
2916 addresses based on the frame pointer or arg pointer until the
2917 reload pass starts. This is so that eliminating such addresses
2918 into stack based ones won't produce impossible code. */
2920 thumb_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict_p
)
2922 /* ??? Not clear if this is right. Experiment. */
2923 if (GET_MODE_SIZE (mode
) < 4
2924 && !(reload_in_progress
|| reload_completed
)
2925 && (reg_mentioned_p (frame_pointer_rtx
, x
)
2926 || reg_mentioned_p (arg_pointer_rtx
, x
)
2927 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
2928 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
2929 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
2930 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
2933 /* Accept any base register. SP only in SImode or larger. */
2934 else if (thumb_base_register_rtx_p (x
, mode
, strict_p
))
2937 /* This is PC relative data before arm_reorg runs. */
2938 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
2939 && GET_CODE (x
) == SYMBOL_REF
2940 && CONSTANT_POOL_ADDRESS_P (x
) && ! flag_pic
)
2943 /* This is PC relative data after arm_reorg runs. */
2944 else if (GET_MODE_SIZE (mode
) >= 4 && reload_completed
2945 && (GET_CODE (x
) == LABEL_REF
2946 || (GET_CODE (x
) == CONST
2947 && GET_CODE (XEXP (x
, 0)) == PLUS
2948 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
2949 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
2952 /* Post-inc indexing only supported for SImode and larger. */
2953 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
2954 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
))
2957 else if (GET_CODE (x
) == PLUS
)
2959 /* REG+REG address can be any two index registers. */
2960 /* We disallow FRAME+REG addressing since we know that FRAME
2961 will be replaced with STACK, and SP relative addressing only
2962 permits SP+OFFSET. */
2963 if (GET_MODE_SIZE (mode
) <= 4
2964 && XEXP (x
, 0) != frame_pointer_rtx
2965 && XEXP (x
, 1) != frame_pointer_rtx
2966 && XEXP (x
, 0) != virtual_stack_vars_rtx
2967 && XEXP (x
, 1) != virtual_stack_vars_rtx
2968 && thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
2969 && thumb_index_register_rtx_p (XEXP (x
, 1), strict_p
))
2972 /* REG+const has 5-7 bit offset for non-SP registers. */
2973 else if ((thumb_index_register_rtx_p (XEXP (x
, 0), strict_p
)
2974 || XEXP (x
, 0) == arg_pointer_rtx
)
2975 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2976 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
2979 /* REG+const has 10 bit offset for SP, but only SImode and
2980 larger is supported. */
2981 /* ??? Should probably check for DI/DFmode overflow here
2982 just like GO_IF_LEGITIMATE_OFFSET does. */
2983 else if (GET_CODE (XEXP (x
, 0)) == REG
2984 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
2985 && GET_MODE_SIZE (mode
) >= 4
2986 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2987 && INTVAL (XEXP (x
, 1)) >= 0
2988 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
2989 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
2992 else if (GET_CODE (XEXP (x
, 0)) == REG
2993 && REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
2994 && GET_MODE_SIZE (mode
) >= 4
2995 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2996 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
3000 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
3001 && GET_CODE (x
) == SYMBOL_REF
3002 && CONSTANT_POOL_ADDRESS_P (x
)
3004 && symbol_mentioned_p (get_pool_constant (x
))))
3010 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3011 instruction of mode MODE. */
3013 thumb_legitimate_offset_p (enum machine_mode mode
, HOST_WIDE_INT val
)
3015 switch (GET_MODE_SIZE (mode
))
3018 return val
>= 0 && val
< 32;
3021 return val
>= 0 && val
< 64 && (val
& 1) == 0;
3025 && (val
+ GET_MODE_SIZE (mode
)) <= 128
3030 /* Try machine-dependent ways of modifying an illegitimate address
3031 to be legitimate. If we find one, return the new, valid address. */
3033 arm_legitimize_address (rtx x
, rtx orig_x
, enum machine_mode mode
)
3035 if (GET_CODE (x
) == PLUS
)
3037 rtx xop0
= XEXP (x
, 0);
3038 rtx xop1
= XEXP (x
, 1);
3040 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
3041 xop0
= force_reg (SImode
, xop0
);
3043 if (CONSTANT_P (xop1
) && !symbol_mentioned_p (xop1
))
3044 xop1
= force_reg (SImode
, xop1
);
3046 if (ARM_BASE_REGISTER_RTX_P (xop0
)
3047 && GET_CODE (xop1
) == CONST_INT
)
3049 HOST_WIDE_INT n
, low_n
;
3053 if (mode
== DImode
|| (TARGET_SOFT_FLOAT
&& mode
== DFmode
))
3065 low_n
= ((mode
) == TImode
? 0
3066 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
3070 base_reg
= gen_reg_rtx (SImode
);
3071 val
= force_operand (gen_rtx_PLUS (SImode
, xop0
,
3072 GEN_INT (n
)), NULL_RTX
);
3073 emit_move_insn (base_reg
, val
);
3074 x
= (low_n
== 0 ? base_reg
3075 : gen_rtx_PLUS (SImode
, base_reg
, GEN_INT (low_n
)));
3077 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3078 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
3081 /* XXX We don't allow MINUS any more -- see comment in
3082 arm_legitimate_address_p (). */
3083 else if (GET_CODE (x
) == MINUS
)
3085 rtx xop0
= XEXP (x
, 0);
3086 rtx xop1
= XEXP (x
, 1);
3088 if (CONSTANT_P (xop0
))
3089 xop0
= force_reg (SImode
, xop0
);
3091 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
3092 xop1
= force_reg (SImode
, xop1
);
3094 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
3095 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
3100 /* We need to find and carefully transform any SYMBOL and LABEL
3101 references; so go back to the original address expression. */
3102 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
);
3104 if (new_x
!= orig_x
)
3113 #define REG_OR_SUBREG_REG(X) \
3114 (GET_CODE (X) == REG \
3115 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3117 #define REG_OR_SUBREG_RTX(X) \
3118 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3120 #ifndef COSTS_N_INSNS
3121 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3123 /* Worker routine for arm_rtx_costs. */
3125 arm_rtx_costs_1 (rtx x
, enum rtx_code code
, enum rtx_code outer
)
3127 enum machine_mode mode
= GET_MODE (x
);
3128 enum rtx_code subcode
;
3144 return COSTS_N_INSNS (1);
3147 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3150 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
3157 return COSTS_N_INSNS (2) + cycles
;
3159 return COSTS_N_INSNS (1) + 16;
3162 return (COSTS_N_INSNS (1)
3163 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
3164 + GET_CODE (SET_DEST (x
)) == MEM
));
3169 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
3171 if (thumb_shiftable_const (INTVAL (x
)))
3172 return COSTS_N_INSNS (2);
3173 return COSTS_N_INSNS (3);
3175 else if ((outer
== PLUS
|| outer
== COMPARE
)
3176 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
3178 else if (outer
== AND
3179 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
3180 return COSTS_N_INSNS (1);
3181 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
3182 || outer
== LSHIFTRT
)
3184 return COSTS_N_INSNS (2);
3190 return COSTS_N_INSNS (3);
3209 /* XXX another guess. */
3210 /* Memory costs quite a lot for the first word, but subsequent words
3211 load at the equivalent of a single insn each. */
3212 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3213 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
3218 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3223 /* XXX still guessing. */
3224 switch (GET_MODE (XEXP (x
, 0)))
3227 return (1 + (mode
== DImode
? 4 : 0)
3228 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3231 return (4 + (mode
== DImode
? 4 : 0)
3232 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3235 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3249 /* Memory costs quite a lot for the first word, but subsequent words
3250 load at the equivalent of a single insn each. */
3251 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
3252 + (GET_CODE (x
) == SYMBOL_REF
3253 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
3259 return optimize_size
? COSTS_N_INSNS (2) : 100;
3262 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
3269 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
3271 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
3272 + ((GET_CODE (XEXP (x
, 0)) == REG
3273 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3274 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3276 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
3277 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3278 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
3280 + ((GET_CODE (XEXP (x
, 1)) == REG
3281 || (GET_CODE (XEXP (x
, 1)) == SUBREG
3282 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
3283 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
3288 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
3289 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3290 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
3291 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
3294 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3295 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3296 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3297 && const_double_rtx_ok_for_fpa (XEXP (x
, 1))))
3299 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3300 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
3301 && const_double_rtx_ok_for_fpa (XEXP (x
, 0))))
3304 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
3305 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
3306 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
3307 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
3308 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
3309 || subcode
== ROTATE
|| subcode
== ROTATERT
3311 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
3312 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
3313 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
3314 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
3315 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
3316 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
3317 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
3322 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3323 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3324 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3325 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
3326 && const_double_rtx_ok_for_fpa (XEXP (x
, 1))))
3330 case AND
: case XOR
: case IOR
:
3333 /* Normally the frame registers will be spilt into reg+const during
3334 reload, so it is a bad idea to combine them with other instructions,
3335 since then they might not be moved outside of loops. As a compromise
3336 we allow integration with ops that have a constant as their second
3338 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
3339 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
3340 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3341 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
3342 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
3346 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
3347 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3348 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3349 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3352 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
3353 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
3354 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
3355 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
3356 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
3359 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
3360 return (1 + extra_cost
3361 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
3362 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
3363 || subcode
== ROTATE
|| subcode
== ROTATERT
3365 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3366 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
3367 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
3368 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
3369 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
3370 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
3376 /* There is no point basing this on the tuning, since it is always the
3377 fast variant if it exists at all. */
3378 if (arm_fast_multiply
&& mode
== DImode
3379 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
3380 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
3381 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
3384 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
3388 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3390 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
3391 & (unsigned HOST_WIDE_INT
) 0xffffffff);
3392 int cost
, const_ok
= const_ok_for_arm (i
);
3393 int j
, booth_unit_size
;
3395 if (arm_tune_xscale
)
3397 unsigned HOST_WIDE_INT masked_const
;
3399 /* The cost will be related to two insns.
3400 First a load of the constant (MOV or LDR), then a multiply. */
3403 cost
+= 1; /* LDR is probably more expensive because
3404 of longer result latency. */
3405 masked_const
= i
& 0xffff8000;
3406 if (masked_const
!= 0 && masked_const
!= 0xffff8000)
3408 masked_const
= i
& 0xf8000000;
3409 if (masked_const
== 0 || masked_const
== 0xf8000000)
3417 /* Tune as appropriate. */
3418 cost
= const_ok
? 4 : 8;
3419 booth_unit_size
= ((tune_flags
& FL_FAST_MULT
) ? 8 : 2);
3420 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
3422 i
>>= booth_unit_size
;
3429 return (((tune_flags
& FL_FAST_MULT
) ? 8 : 30)
3430 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
3431 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4));
3434 if (arm_fast_multiply
&& mode
== SImode
3435 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3436 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
3437 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
3438 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
3439 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
3440 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
3445 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3446 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
3450 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
3452 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
3455 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
3463 return 4 + (mode
== DImode
? 4 : 0);
3466 if (GET_MODE (XEXP (x
, 0)) == QImode
)
3467 return (4 + (mode
== DImode
? 4 : 0)
3468 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3471 switch (GET_MODE (XEXP (x
, 0)))
3474 return (1 + (mode
== DImode
? 4 : 0)
3475 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3478 return (4 + (mode
== DImode
? 4 : 0)
3479 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3482 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
3497 if (const_ok_for_arm (INTVAL (x
)))
3498 return outer
== SET
? 2 : -1;
3499 else if (outer
== AND
3500 && const_ok_for_arm (~INTVAL (x
)))
3502 else if ((outer
== COMPARE
3503 || outer
== PLUS
|| outer
== MINUS
)
3504 && const_ok_for_arm (-INTVAL (x
)))
3515 if (const_double_rtx_ok_for_fpa (x
))
3516 return outer
== SET
? 2 : -1;
3517 else if ((outer
== COMPARE
|| outer
== PLUS
)
3518 && neg_const_double_rtx_ok_for_fpa (x
))
3528 arm_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
3530 *total
= arm_rtx_costs_1 (x
, code
, outer_code
);
3534 /* All address computations that can be done are free, but rtx cost returns
3535 the same for practically all of them. So we weight the different types
3536 of address here in the order (most pref first):
3537 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
3539 arm_arm_address_cost (rtx x
)
3541 enum rtx_code c
= GET_CODE (x
);
3543 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
3545 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
3548 if (c
== PLUS
|| c
== MINUS
)
3550 char cl0
= GET_RTX_CLASS (GET_CODE (XEXP (x
, 0)));
3551 char cl1
= GET_RTX_CLASS (GET_CODE (XEXP (x
, 1)));
3553 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
3556 if (cl0
== '2' || cl0
== 'c' || cl1
== '2' || cl1
== 'c')
3566 arm_thumb_address_cost (rtx x
)
3568 enum rtx_code c
= GET_CODE (x
);
3573 && GET_CODE (XEXP (x
, 0)) == REG
3574 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3581 arm_address_cost (rtx x
)
3583 return TARGET_ARM
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
3587 arm_use_dfa_pipeline_interface (void)
3593 arm_adjust_cost (rtx insn
, rtx link
, rtx dep
, int cost
)
3597 /* Some true dependencies can have a higher cost depending
3598 on precisely how certain input operands are used. */
3600 && REG_NOTE_KIND (link
) == 0
3601 && recog_memoized (insn
) >= 0
3602 && recog_memoized (dep
) >= 0)
3604 int shift_opnum
= get_attr_shift (insn
);
3605 enum attr_type attr_type
= get_attr_type (dep
);
3607 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
3608 operand for INSN. If we have a shifted input operand and the
3609 instruction we depend on is another ALU instruction, then we may
3610 have to account for an additional stall. */
3611 if (shift_opnum
!= 0 && attr_type
== TYPE_NORMAL
)
3613 rtx shifted_operand
;
3616 /* Get the shifted operand. */
3617 extract_insn (insn
);
3618 shifted_operand
= recog_data
.operand
[shift_opnum
];
3620 /* Iterate over all the operands in DEP. If we write an operand
3621 that overlaps with SHIFTED_OPERAND, then we have increase the
3622 cost of this dependency. */
3624 preprocess_constraints ();
3625 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
3627 /* We can ignore strict inputs. */
3628 if (recog_data
.operand_type
[opno
] == OP_IN
)
3631 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
3638 /* XXX This is not strictly true for the FPA. */
3639 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
3640 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
3643 /* Call insns don't incur a stall, even if they follow a load. */
3644 if (REG_NOTE_KIND (link
) == 0
3645 && GET_CODE (insn
) == CALL_INSN
)
3648 if ((i_pat
= single_set (insn
)) != NULL
3649 && GET_CODE (SET_SRC (i_pat
)) == MEM
3650 && (d_pat
= single_set (dep
)) != NULL
3651 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
3653 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
3654 /* This is a load after a store, there is no conflict if the load reads
3655 from a cached area. Assume that loads from the stack, and from the
3656 constant pool are cached, and that others will miss. This is a
3659 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
3660 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
3661 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
3662 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
3669 static int fpa_consts_inited
= 0;
3671 static const char * const strings_fpa
[8] =
3674 "4", "5", "0.5", "10"
3677 static REAL_VALUE_TYPE values_fpa
[8];
3680 init_fpa_table (void)
3685 for (i
= 0; i
< 8; i
++)
3687 r
= REAL_VALUE_ATOF (strings_fpa
[i
], DFmode
);
3691 fpa_consts_inited
= 1;
3694 /* Return TRUE if rtx X is a valid immediate FPA constant. */
3696 const_double_rtx_ok_for_fpa (rtx x
)
3701 if (!fpa_consts_inited
)
3704 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3705 if (REAL_VALUE_MINUS_ZERO (r
))
3708 for (i
= 0; i
< 8; i
++)
3709 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
3715 /* Return TRUE if rtx X is a valid immediate FPA constant. */
3717 neg_const_double_rtx_ok_for_fpa (rtx x
)
3722 if (!fpa_consts_inited
)
3725 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3726 r
= REAL_VALUE_NEGATE (r
);
3727 if (REAL_VALUE_MINUS_ZERO (r
))
3730 for (i
= 0; i
< 8; i
++)
3731 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
3737 /* Predicates for `match_operand' and `match_operator'. */
3739 /* s_register_operand is the same as register_operand, but it doesn't accept
3742 This function exists because at the time it was put in it led to better
3743 code. SUBREG(MEM) always needs a reload in the places where
3744 s_register_operand is used, and this seemed to lead to excessive
3747 s_register_operand (rtx op
, enum machine_mode mode
)
3749 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3752 if (GET_CODE (op
) == SUBREG
)
3753 op
= SUBREG_REG (op
);
3755 /* We don't consider registers whose class is NO_REGS
3756 to be a register operand. */
3757 /* XXX might have to check for lo regs only for thumb ??? */
3758 return (GET_CODE (op
) == REG
3759 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3760 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
3763 /* A hard register operand (even before reload. */
3765 arm_hard_register_operand (rtx op
, enum machine_mode mode
)
3767 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3770 return (GET_CODE (op
) == REG
3771 && REGNO (op
) < FIRST_PSEUDO_REGISTER
);
3774 /* Only accept reg, subreg(reg), const_int. */
3776 reg_or_int_operand (rtx op
, enum machine_mode mode
)
3778 if (GET_CODE (op
) == CONST_INT
)
3781 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3784 if (GET_CODE (op
) == SUBREG
)
3785 op
= SUBREG_REG (op
);
3787 /* We don't consider registers whose class is NO_REGS
3788 to be a register operand. */
3789 return (GET_CODE (op
) == REG
3790 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3791 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
3794 /* Return 1 if OP is an item in memory, given that we are in reload. */
3796 arm_reload_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3798 int regno
= true_regnum (op
);
3800 return (!CONSTANT_P (op
)
3802 || (GET_CODE (op
) == REG
3803 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)));
3806 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
3807 memory access (architecture V4).
3808 MODE is QImode if called when computing constraints, or VOIDmode when
3809 emitting patterns. In this latter case we cannot use memory_operand()
3810 because it will fail on badly formed MEMs, which is precisely what we are
3813 bad_signed_byte_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3815 if (GET_CODE (op
) != MEM
)
3820 /* A sum of anything more complex than reg + reg or reg + const is bad. */
3821 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3822 && (!s_register_operand (XEXP (op
, 0), VOIDmode
)
3823 || (!s_register_operand (XEXP (op
, 1), VOIDmode
)
3824 && GET_CODE (XEXP (op
, 1)) != CONST_INT
)))
3827 /* Big constants are also bad. */
3828 if (GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
3829 && (INTVAL (XEXP (op
, 1)) > 0xff
3830 || -INTVAL (XEXP (op
, 1)) > 0xff))
3833 /* Everything else is good, or can will automatically be made so. */
3837 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
3839 arm_rhs_operand (rtx op
, enum machine_mode mode
)
3841 return (s_register_operand (op
, mode
)
3842 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
))));
3845 /* Return TRUE for valid operands for the
3846 rhs of an ARM instruction, or a load. */
3848 arm_rhsm_operand (rtx op
, enum machine_mode mode
)
3850 return (s_register_operand (op
, mode
)
3851 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
)))
3852 || memory_operand (op
, mode
));
3855 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
3856 constant that is valid when negated. */
3858 arm_add_operand (rtx op
, enum machine_mode mode
)
3861 return thumb_cmp_operand (op
, mode
);
3863 return (s_register_operand (op
, mode
)
3864 || (GET_CODE (op
) == CONST_INT
3865 && (const_ok_for_arm (INTVAL (op
))
3866 || const_ok_for_arm (-INTVAL (op
)))));
3869 /* Return TRUE for valid ARM constants (or when valid if negated). */
3871 arm_addimm_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3873 return (GET_CODE (op
) == CONST_INT
3874 && (const_ok_for_arm (INTVAL (op
))
3875 || const_ok_for_arm (-INTVAL (op
))));
3879 arm_not_operand (rtx op
, enum machine_mode mode
)
3881 return (s_register_operand (op
, mode
)
3882 || (GET_CODE (op
) == CONST_INT
3883 && (const_ok_for_arm (INTVAL (op
))
3884 || const_ok_for_arm (~INTVAL (op
)))));
3887 /* Return TRUE if the operand is a memory reference which contains an
3888 offsettable address. */
3890 offsettable_memory_operand (rtx op
, enum machine_mode mode
)
3892 if (mode
== VOIDmode
)
3893 mode
= GET_MODE (op
);
3895 return (mode
== GET_MODE (op
)
3896 && GET_CODE (op
) == MEM
3897 && offsettable_address_p (reload_completed
| reload_in_progress
,
3898 mode
, XEXP (op
, 0)));
3901 /* Return TRUE if the operand is a memory reference which is, or can be
3902 made word aligned by adjusting the offset. */
3904 alignable_memory_operand (rtx op
, enum machine_mode mode
)
3908 if (mode
== VOIDmode
)
3909 mode
= GET_MODE (op
);
3911 if (mode
!= GET_MODE (op
) || GET_CODE (op
) != MEM
)
3916 return ((GET_CODE (reg
= op
) == REG
3917 || (GET_CODE (op
) == SUBREG
3918 && GET_CODE (reg
= SUBREG_REG (op
)) == REG
)
3919 || (GET_CODE (op
) == PLUS
3920 && GET_CODE (XEXP (op
, 1)) == CONST_INT
3921 && (GET_CODE (reg
= XEXP (op
, 0)) == REG
3922 || (GET_CODE (XEXP (op
, 0)) == SUBREG
3923 && GET_CODE (reg
= SUBREG_REG (XEXP (op
, 0))) == REG
))))
3924 && REGNO_POINTER_ALIGN (REGNO (reg
)) >= 32);
3927 /* Similar to s_register_operand, but does not allow hard integer
3930 f_register_operand (rtx op
, enum machine_mode mode
)
3932 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3935 if (GET_CODE (op
) == SUBREG
)
3936 op
= SUBREG_REG (op
);
3938 /* We don't consider registers whose class is NO_REGS
3939 to be a register operand. */
3940 return (GET_CODE (op
) == REG
3941 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3942 || REGNO_REG_CLASS (REGNO (op
)) == FPA_REGS
));
3945 /* Return TRUE for valid operands for the rhs of an FPA instruction. */
3947 fpa_rhs_operand (rtx op
, enum machine_mode mode
)
3949 if (s_register_operand (op
, mode
))
3952 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3955 if (GET_CODE (op
) == CONST_DOUBLE
)
3956 return const_double_rtx_ok_for_fpa (op
);
3962 fpa_add_operand (rtx op
, enum machine_mode mode
)
3964 if (s_register_operand (op
, mode
))
3967 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3970 if (GET_CODE (op
) == CONST_DOUBLE
)
3971 return (const_double_rtx_ok_for_fpa (op
)
3972 || neg_const_double_rtx_ok_for_fpa (op
));
3977 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
3979 cirrus_memory_offset (rtx op
)
3981 /* Reject eliminable registers. */
3982 if (! (reload_in_progress
|| reload_completed
)
3983 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
3984 || reg_mentioned_p (arg_pointer_rtx
, op
)
3985 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
3986 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
3987 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
3988 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
3991 if (GET_CODE (op
) == MEM
)
3997 /* Match: (mem (reg)). */
3998 if (GET_CODE (ind
) == REG
)
4004 if (GET_CODE (ind
) == PLUS
4005 && GET_CODE (XEXP (ind
, 0)) == REG
4006 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
4007 && GET_CODE (XEXP (ind
, 1)) == CONST_INT
)
4014 /* Return nonzero if OP is a Cirrus or general register. */
4016 cirrus_register_operand (rtx op
, enum machine_mode mode
)
4018 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4021 if (GET_CODE (op
) == SUBREG
)
4022 op
= SUBREG_REG (op
);
4024 return (GET_CODE (op
) == REG
4025 && (REGNO_REG_CLASS (REGNO (op
)) == CIRRUS_REGS
4026 || REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
));
4029 /* Return nonzero if OP is a cirrus FP register. */
4031 cirrus_fp_register (rtx op
, enum machine_mode mode
)
4033 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
4036 if (GET_CODE (op
) == SUBREG
)
4037 op
= SUBREG_REG (op
);
4039 return (GET_CODE (op
) == REG
4040 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
4041 || REGNO_REG_CLASS (REGNO (op
)) == CIRRUS_REGS
));
4044 /* Return nonzero if OP is a 6bit constant (0..63). */
4046 cirrus_shift_const (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4048 return (GET_CODE (op
) == CONST_INT
4050 && INTVAL (op
) < 64);
4053 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4054 Use by the Cirrus Maverick code which has to workaround
4055 a hardware bug triggered by such instructions. */
4057 arm_memory_load_p (rtx insn
)
4059 rtx body
, lhs
, rhs
;;
4061 if (insn
== NULL_RTX
|| GET_CODE (insn
) != INSN
)
4064 body
= PATTERN (insn
);
4066 if (GET_CODE (body
) != SET
)
4069 lhs
= XEXP (body
, 0);
4070 rhs
= XEXP (body
, 1);
4072 lhs
= REG_OR_SUBREG_RTX (lhs
);
4074 /* If the destination is not a general purpose
4075 register we do not have to worry. */
4076 if (GET_CODE (lhs
) != REG
4077 || REGNO_REG_CLASS (REGNO (lhs
)) != GENERAL_REGS
)
4080 /* As well as loads from memory we also have to react
4081 to loads of invalid constants which will be turned
4082 into loads from the minipool. */
4083 return (GET_CODE (rhs
) == MEM
4084 || GET_CODE (rhs
) == SYMBOL_REF
4085 || note_invalid_constants (insn
, -1, false));
4088 /* Return TRUE if INSN is a Cirrus instruction. */
4090 arm_cirrus_insn_p (rtx insn
)
4092 enum attr_cirrus attr
;
4094 /* get_attr aborts on USE and CLOBBER. */
4096 || GET_CODE (insn
) != INSN
4097 || GET_CODE (PATTERN (insn
)) == USE
4098 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4101 attr
= get_attr_cirrus (insn
);
4103 return attr
!= CIRRUS_NOT
;
4106 /* Cirrus reorg for invalid instruction combinations. */
4108 cirrus_reorg (rtx first
)
4110 enum attr_cirrus attr
;
4111 rtx body
= PATTERN (first
);
4115 /* Any branch must be followed by 2 non Cirrus instructions. */
4116 if (GET_CODE (first
) == JUMP_INSN
&& GET_CODE (body
) != RETURN
)
4119 t
= next_nonnote_insn (first
);
4121 if (arm_cirrus_insn_p (t
))
4124 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
4128 emit_insn_after (gen_nop (), first
);
4133 /* (float (blah)) is in parallel with a clobber. */
4134 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
4135 body
= XVECEXP (body
, 0, 0);
4137 if (GET_CODE (body
) == SET
)
4139 rtx lhs
= XEXP (body
, 0), rhs
= XEXP (body
, 1);
4141 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4142 be followed by a non Cirrus insn. */
4143 if (get_attr_cirrus (first
) == CIRRUS_DOUBLE
)
4145 if (arm_cirrus_insn_p (next_nonnote_insn (first
)))
4146 emit_insn_after (gen_nop (), first
);
4150 else if (arm_memory_load_p (first
))
4152 unsigned int arm_regno
;
4154 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4155 ldr/cfmv64hr combination where the Rd field is the same
4156 in both instructions must be split with a non Cirrus
4163 /* Get Arm register number for ldr insn. */
4164 if (GET_CODE (lhs
) == REG
)
4165 arm_regno
= REGNO (lhs
);
4166 else if (GET_CODE (rhs
) == REG
)
4167 arm_regno
= REGNO (rhs
);
4172 first
= next_nonnote_insn (first
);
4174 if (! arm_cirrus_insn_p (first
))
4177 body
= PATTERN (first
);
4179 /* (float (blah)) is in parallel with a clobber. */
4180 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0))
4181 body
= XVECEXP (body
, 0, 0);
4183 if (GET_CODE (body
) == FLOAT
)
4184 body
= XEXP (body
, 0);
4186 if (get_attr_cirrus (first
) == CIRRUS_MOVE
4187 && GET_CODE (XEXP (body
, 1)) == REG
4188 && arm_regno
== REGNO (XEXP (body
, 1)))
4189 emit_insn_after (gen_nop (), first
);
4195 /* get_attr aborts on USE and CLOBBER. */
4197 || GET_CODE (first
) != INSN
4198 || GET_CODE (PATTERN (first
)) == USE
4199 || GET_CODE (PATTERN (first
)) == CLOBBER
)
4202 attr
= get_attr_cirrus (first
);
4204 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4205 must be followed by a non-coprocessor instruction. */
4206 if (attr
== CIRRUS_COMPARE
)
4210 t
= next_nonnote_insn (first
);
4212 if (arm_cirrus_insn_p (t
))
4215 if (arm_cirrus_insn_p (next_nonnote_insn (t
)))
4219 emit_insn_after (gen_nop (), first
);
4225 /* Return nonzero if OP is a constant power of two. */
4227 power_of_two_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4229 if (GET_CODE (op
) == CONST_INT
)
4231 HOST_WIDE_INT value
= INTVAL (op
);
4233 return value
!= 0 && (value
& (value
- 1)) == 0;
4239 /* Return TRUE for a valid operand of a DImode operation.
4240 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4241 Note that this disallows MEM(REG+REG), but allows
4242 MEM(PRE/POST_INC/DEC(REG)). */
4244 di_operand (rtx op
, enum machine_mode mode
)
4246 if (s_register_operand (op
, mode
))
4249 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
4252 if (GET_CODE (op
) == SUBREG
)
4253 op
= SUBREG_REG (op
);
4255 switch (GET_CODE (op
))
4262 return memory_address_p (DImode
, XEXP (op
, 0));
4269 /* Like di_operand, but don't accept constants. */
4271 nonimmediate_di_operand (rtx op
, enum machine_mode mode
)
4273 if (s_register_operand (op
, mode
))
4276 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
4279 if (GET_CODE (op
) == SUBREG
)
4280 op
= SUBREG_REG (op
);
4282 if (GET_CODE (op
) == MEM
)
4283 return memory_address_p (DImode
, XEXP (op
, 0));
4288 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
4289 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4290 Note that this disallows MEM(REG+REG), but allows
4291 MEM(PRE/POST_INC/DEC(REG)). */
4293 soft_df_operand (rtx op
, enum machine_mode mode
)
4295 if (s_register_operand (op
, mode
))
4298 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
4301 if (GET_CODE (op
) == SUBREG
&& CONSTANT_P (SUBREG_REG (op
)))
4304 if (GET_CODE (op
) == SUBREG
)
4305 op
= SUBREG_REG (op
);
4307 switch (GET_CODE (op
))
4313 return memory_address_p (DFmode
, XEXP (op
, 0));
4320 /* Like soft_df_operand, but don't accept constants. */
4322 nonimmediate_soft_df_operand (rtx op
, enum machine_mode mode
)
4324 if (s_register_operand (op
, mode
))
4327 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
4330 if (GET_CODE (op
) == SUBREG
)
4331 op
= SUBREG_REG (op
);
4333 if (GET_CODE (op
) == MEM
)
4334 return memory_address_p (DFmode
, XEXP (op
, 0));
4338 /* Return TRUE for valid index operands. */
4340 index_operand (rtx op
, enum machine_mode mode
)
4342 return (s_register_operand (op
, mode
)
4343 || (immediate_operand (op
, mode
)
4344 && (GET_CODE (op
) != CONST_INT
4345 || (INTVAL (op
) < 4096 && INTVAL (op
) > -4096))));
4348 /* Return TRUE for valid shifts by a constant. This also accepts any
4349 power of two on the (somewhat overly relaxed) assumption that the
4350 shift operator in this case was a mult. */
4352 const_shift_operand (rtx op
, enum machine_mode mode
)
4354 return (power_of_two_operand (op
, mode
)
4355 || (immediate_operand (op
, mode
)
4356 && (GET_CODE (op
) != CONST_INT
4357 || (INTVAL (op
) < 32 && INTVAL (op
) > 0))));
4360 /* Return TRUE for arithmetic operators which can be combined with a multiply
4363 shiftable_operator (rtx x
, enum machine_mode mode
)
4367 if (GET_MODE (x
) != mode
)
4370 code
= GET_CODE (x
);
4372 return (code
== PLUS
|| code
== MINUS
4373 || code
== IOR
|| code
== XOR
|| code
== AND
);
4376 /* Return TRUE for binary logical operators. */
4378 logical_binary_operator (rtx x
, enum machine_mode mode
)
4382 if (GET_MODE (x
) != mode
)
4385 code
= GET_CODE (x
);
4387 return (code
== IOR
|| code
== XOR
|| code
== AND
);
4390 /* Return TRUE for shift operators. */
4392 shift_operator (rtx x
,enum machine_mode mode
)
4396 if (GET_MODE (x
) != mode
)
4399 code
= GET_CODE (x
);
4402 return power_of_two_operand (XEXP (x
, 1), mode
);
4404 return (code
== ASHIFT
|| code
== ASHIFTRT
|| code
== LSHIFTRT
4405 || code
== ROTATERT
);
4408 /* Return TRUE if x is EQ or NE. */
4410 equality_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4412 return GET_CODE (x
) == EQ
|| GET_CODE (x
) == NE
;
4415 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
4417 arm_comparison_operator (rtx x
, enum machine_mode mode
)
4419 return (comparison_operator (x
, mode
)
4420 && GET_CODE (x
) != LTGT
4421 && GET_CODE (x
) != UNEQ
);
4424 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
4426 minmax_operator (rtx x
, enum machine_mode mode
)
4428 enum rtx_code code
= GET_CODE (x
);
4430 if (GET_MODE (x
) != mode
)
4433 return code
== SMIN
|| code
== SMAX
|| code
== UMIN
|| code
== UMAX
;
4436 /* Return TRUE if this is the condition code register, if we aren't given
4437 a mode, accept any class CCmode register. */
4439 cc_register (rtx x
, enum machine_mode mode
)
4441 if (mode
== VOIDmode
)
4443 mode
= GET_MODE (x
);
4445 if (GET_MODE_CLASS (mode
) != MODE_CC
)
4449 if ( GET_MODE (x
) == mode
4450 && GET_CODE (x
) == REG
4451 && REGNO (x
) == CC_REGNUM
)
4457 /* Return TRUE if this is the condition code register, if we aren't given
4458 a mode, accept any class CCmode register which indicates a dominance
4461 dominant_cc_register (rtx x
, enum machine_mode mode
)
4463 if (mode
== VOIDmode
)
4465 mode
= GET_MODE (x
);
4467 if (GET_MODE_CLASS (mode
) != MODE_CC
)
4471 if (mode
!= CC_DNEmode
&& mode
!= CC_DEQmode
4472 && mode
!= CC_DLEmode
&& mode
!= CC_DLTmode
4473 && mode
!= CC_DGEmode
&& mode
!= CC_DGTmode
4474 && mode
!= CC_DLEUmode
&& mode
!= CC_DLTUmode
4475 && mode
!= CC_DGEUmode
&& mode
!= CC_DGTUmode
)
4478 return cc_register (x
, mode
);
4481 /* Return TRUE if X references a SYMBOL_REF. */
4483 symbol_mentioned_p (rtx x
)
4488 if (GET_CODE (x
) == SYMBOL_REF
)
4491 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
4493 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
4499 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4500 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
4503 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
4510 /* Return TRUE if X references a LABEL_REF. */
4512 label_mentioned_p (rtx x
)
4517 if (GET_CODE (x
) == LABEL_REF
)
4520 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
4521 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
4527 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4528 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
4531 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
4541 enum rtx_code code
= GET_CODE (x
);
4545 else if (code
== SMIN
)
4547 else if (code
== UMIN
)
4549 else if (code
== UMAX
)
4555 /* Return 1 if memory locations are adjacent. */
4557 adjacent_mem_locations (rtx a
, rtx b
)
4559 if ((GET_CODE (XEXP (a
, 0)) == REG
4560 || (GET_CODE (XEXP (a
, 0)) == PLUS
4561 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
4562 && (GET_CODE (XEXP (b
, 0)) == REG
4563 || (GET_CODE (XEXP (b
, 0)) == PLUS
4564 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
4566 int val0
= 0, val1
= 0;
4569 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
4571 reg0
= REGNO (XEXP (XEXP (a
, 0), 0));
4572 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
4575 reg0
= REGNO (XEXP (a
, 0));
4577 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
4579 reg1
= REGNO (XEXP (XEXP (b
, 0), 0));
4580 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
4583 reg1
= REGNO (XEXP (b
, 0));
4585 /* Don't accept any offset that will require multiple
4586 instructions to handle, since this would cause the
4587 arith_adjacentmem pattern to output an overlong sequence. */
4588 if (!const_ok_for_op (PLUS
, val0
) || !const_ok_for_op (PLUS
, val1
))
4591 return (reg0
== reg1
) && ((val1
- val0
) == 4 || (val0
- val1
) == 4);
4596 /* Return 1 if OP is a load multiple operation. It is known to be
4597 parallel and the first section will be tested. */
4599 load_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4601 HOST_WIDE_INT count
= XVECLEN (op
, 0);
4604 HOST_WIDE_INT i
= 1, base
= 0;
4608 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
4611 /* Check to see if this might be a write-back. */
4612 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
4617 /* Now check it more carefully. */
4618 if (GET_CODE (SET_DEST (elt
)) != REG
4619 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
4620 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
4621 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
4622 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
4626 /* Perform a quick check so we don't blow up below. */
4628 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
4629 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != REG
4630 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != MEM
)
4633 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, i
- 1)));
4634 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, i
- 1)), 0);
4636 for (; i
< count
; i
++)
4638 elt
= XVECEXP (op
, 0, i
);
4640 if (GET_CODE (elt
) != SET
4641 || GET_CODE (SET_DEST (elt
)) != REG
4642 || GET_MODE (SET_DEST (elt
)) != SImode
4643 || REGNO (SET_DEST (elt
)) != (unsigned int)(dest_regno
+ i
- base
)
4644 || GET_CODE (SET_SRC (elt
)) != MEM
4645 || GET_MODE (SET_SRC (elt
)) != SImode
4646 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
4647 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
4648 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
4649 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != (i
- base
) * 4)
4656 /* Return 1 if OP is a store multiple operation. It is known to be
4657 parallel and the first section will be tested. */
4659 store_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4661 HOST_WIDE_INT count
= XVECLEN (op
, 0);
4664 HOST_WIDE_INT i
= 1, base
= 0;
4668 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
4671 /* Check to see if this might be a write-back. */
4672 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
4677 /* Now check it more carefully. */
4678 if (GET_CODE (SET_DEST (elt
)) != REG
4679 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
4680 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
4681 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
4682 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
4686 /* Perform a quick check so we don't blow up below. */
4688 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
4689 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != MEM
4690 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != REG
)
4693 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, i
- 1)));
4694 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, i
- 1)), 0);
4696 for (; i
< count
; i
++)
4698 elt
= XVECEXP (op
, 0, i
);
4700 if (GET_CODE (elt
) != SET
4701 || GET_CODE (SET_SRC (elt
)) != REG
4702 || GET_MODE (SET_SRC (elt
)) != SImode
4703 || REGNO (SET_SRC (elt
)) != (unsigned int)(src_regno
+ i
- base
)
4704 || GET_CODE (SET_DEST (elt
)) != MEM
4705 || GET_MODE (SET_DEST (elt
)) != SImode
4706 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
4707 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
4708 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
4709 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != (i
- base
) * 4)
4717 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
4718 HOST_WIDE_INT
*load_offset
)
4720 int unsorted_regs
[4];
4721 HOST_WIDE_INT unsorted_offsets
[4];
4726 /* Can only handle 2, 3, or 4 insns at present,
4727 though could be easily extended if required. */
4728 if (nops
< 2 || nops
> 4)
4731 /* Loop over the operands and check that the memory references are
4732 suitable (ie immediate offsets from the same base register). At
4733 the same time, extract the target register, and the memory
4735 for (i
= 0; i
< nops
; i
++)
4740 /* Convert a subreg of a mem into the mem itself. */
4741 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
4742 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
4744 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
4747 /* Don't reorder volatile memory references; it doesn't seem worth
4748 looking for the case where the order is ok anyway. */
4749 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
4752 offset
= const0_rtx
;
4754 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
4755 || (GET_CODE (reg
) == SUBREG
4756 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4757 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
4758 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
4760 || (GET_CODE (reg
) == SUBREG
4761 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4762 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
4767 base_reg
= REGNO (reg
);
4768 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
4769 ? REGNO (operands
[i
])
4770 : REGNO (SUBREG_REG (operands
[i
])));
4775 if (base_reg
!= (int) REGNO (reg
))
4776 /* Not addressed from the same base register. */
4779 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
4780 ? REGNO (operands
[i
])
4781 : REGNO (SUBREG_REG (operands
[i
])));
4782 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
4786 /* If it isn't an integer register, or if it overwrites the
4787 base register but isn't the last insn in the list, then
4788 we can't do this. */
4789 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
4790 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
4793 unsorted_offsets
[i
] = INTVAL (offset
);
4796 /* Not a suitable memory address. */
4800 /* All the useful information has now been extracted from the
4801 operands into unsorted_regs and unsorted_offsets; additionally,
4802 order[0] has been set to the lowest numbered register in the
4803 list. Sort the registers into order, and check that the memory
4804 offsets are ascending and adjacent. */
4806 for (i
= 1; i
< nops
; i
++)
4810 order
[i
] = order
[i
- 1];
4811 for (j
= 0; j
< nops
; j
++)
4812 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
4813 && (order
[i
] == order
[i
- 1]
4814 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
4817 /* Have we found a suitable register? if not, one must be used more
4819 if (order
[i
] == order
[i
- 1])
4822 /* Is the memory address adjacent and ascending? */
4823 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
4831 for (i
= 0; i
< nops
; i
++)
4832 regs
[i
] = unsorted_regs
[order
[i
]];
4834 *load_offset
= unsorted_offsets
[order
[0]];
4837 if (unsorted_offsets
[order
[0]] == 0)
4838 return 1; /* ldmia */
4840 if (unsorted_offsets
[order
[0]] == 4)
4841 return 2; /* ldmib */
4843 if (unsorted_offsets
[order
[nops
- 1]] == 0)
4844 return 3; /* ldmda */
4846 if (unsorted_offsets
[order
[nops
- 1]] == -4)
4847 return 4; /* ldmdb */
4849 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
4850 if the offset isn't small enough. The reason 2 ldrs are faster
4851 is because these ARMs are able to do more than one cache access
4852 in a single cycle. The ARM9 and StrongARM have Harvard caches,
4853 whilst the ARM8 has a double bandwidth cache. This means that
4854 these cores can do both an instruction fetch and a data fetch in
4855 a single cycle, so the trick of calculating the address into a
4856 scratch register (one of the result regs) and then doing a load
4857 multiple actually becomes slower (and no smaller in code size).
4858 That is the transformation
4860 ldr rd1, [rbase + offset]
4861 ldr rd2, [rbase + offset + 4]
4865 add rd1, rbase, offset
4866 ldmia rd1, {rd1, rd2}
4868 produces worse code -- '3 cycles + any stalls on rd2' instead of
4869 '2 cycles + any stalls on rd2'. On ARMs with only one cache
4870 access per cycle, the first sequence could never complete in less
4871 than 6 cycles, whereas the ldm sequence would only take 5 and
4872 would make better use of sequential accesses if not hitting the
4875 We cheat here and test 'arm_ld_sched' which we currently know to
4876 only be true for the ARM8, ARM9 and StrongARM. If this ever
4877 changes, then the test below needs to be reworked. */
4878 if (nops
== 2 && arm_ld_sched
)
4881 /* Can't do it without setting up the offset, only do this if it takes
4882 no more than one insn. */
4883 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
4884 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
4888 emit_ldm_seq (rtx
*operands
, int nops
)
4892 HOST_WIDE_INT offset
;
4896 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
4899 strcpy (buf
, "ldm%?ia\t");
4903 strcpy (buf
, "ldm%?ib\t");
4907 strcpy (buf
, "ldm%?da\t");
4911 strcpy (buf
, "ldm%?db\t");
4916 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
4917 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
4920 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
4921 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
4923 output_asm_insn (buf
, operands
);
4925 strcpy (buf
, "ldm%?ia\t");
4932 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
4933 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
4935 for (i
= 1; i
< nops
; i
++)
4936 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
4937 reg_names
[regs
[i
]]);
4939 strcat (buf
, "}\t%@ phole ldm");
4941 output_asm_insn (buf
, operands
);
4946 store_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *base
,
4947 HOST_WIDE_INT
* load_offset
)
4949 int unsorted_regs
[4];
4950 HOST_WIDE_INT unsorted_offsets
[4];
4955 /* Can only handle 2, 3, or 4 insns at present, though could be easily
4956 extended if required. */
4957 if (nops
< 2 || nops
> 4)
4960 /* Loop over the operands and check that the memory references are
4961 suitable (ie immediate offsets from the same base register). At
4962 the same time, extract the target register, and the memory
4964 for (i
= 0; i
< nops
; i
++)
4969 /* Convert a subreg of a mem into the mem itself. */
4970 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
4971 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
4973 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
4976 /* Don't reorder volatile memory references; it doesn't seem worth
4977 looking for the case where the order is ok anyway. */
4978 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
4981 offset
= const0_rtx
;
4983 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
4984 || (GET_CODE (reg
) == SUBREG
4985 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4986 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
4987 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
4989 || (GET_CODE (reg
) == SUBREG
4990 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4991 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
4996 base_reg
= REGNO (reg
);
4997 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
4998 ? REGNO (operands
[i
])
4999 : REGNO (SUBREG_REG (operands
[i
])));
5004 if (base_reg
!= (int) REGNO (reg
))
5005 /* Not addressed from the same base register. */
5008 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
5009 ? REGNO (operands
[i
])
5010 : REGNO (SUBREG_REG (operands
[i
])));
5011 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
5015 /* If it isn't an integer register, then we can't do this. */
5016 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
5019 unsorted_offsets
[i
] = INTVAL (offset
);
5022 /* Not a suitable memory address. */
5026 /* All the useful information has now been extracted from the
5027 operands into unsorted_regs and unsorted_offsets; additionally,
5028 order[0] has been set to the lowest numbered register in the
5029 list. Sort the registers into order, and check that the memory
5030 offsets are ascending and adjacent. */
5032 for (i
= 1; i
< nops
; i
++)
5036 order
[i
] = order
[i
- 1];
5037 for (j
= 0; j
< nops
; j
++)
5038 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
5039 && (order
[i
] == order
[i
- 1]
5040 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
5043 /* Have we found a suitable register? if not, one must be used more
5045 if (order
[i
] == order
[i
- 1])
5048 /* Is the memory address adjacent and ascending? */
5049 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
5057 for (i
= 0; i
< nops
; i
++)
5058 regs
[i
] = unsorted_regs
[order
[i
]];
5060 *load_offset
= unsorted_offsets
[order
[0]];
5063 if (unsorted_offsets
[order
[0]] == 0)
5064 return 1; /* stmia */
5066 if (unsorted_offsets
[order
[0]] == 4)
5067 return 2; /* stmib */
5069 if (unsorted_offsets
[order
[nops
- 1]] == 0)
5070 return 3; /* stmda */
5072 if (unsorted_offsets
[order
[nops
- 1]] == -4)
5073 return 4; /* stmdb */
5079 emit_stm_seq (rtx
*operands
, int nops
)
5083 HOST_WIDE_INT offset
;
5087 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
5090 strcpy (buf
, "stm%?ia\t");
5094 strcpy (buf
, "stm%?ib\t");
5098 strcpy (buf
, "stm%?da\t");
5102 strcpy (buf
, "stm%?db\t");
5109 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
5110 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
5112 for (i
= 1; i
< nops
; i
++)
5113 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
5114 reg_names
[regs
[i
]]);
5116 strcat (buf
, "}\t%@ phole stm");
5118 output_asm_insn (buf
, operands
);
5123 multi_register_push (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
5125 if (GET_CODE (op
) != PARALLEL
5126 || (GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
5127 || (GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
)
5128 || (XINT (SET_SRC (XVECEXP (op
, 0, 0)), 1) != UNSPEC_PUSH_MULT
))
5134 /* Routines for use in generating RTL. */
5137 arm_gen_load_multiple (int base_regno
, int count
, rtx from
, int up
,
5138 int write_back
, int unchanging_p
, int in_struct_p
,
5143 int sign
= up
? 1 : -1;
5146 /* XScale has load-store double instructions, but they have stricter
5147 alignment requirements than load-store multiple, so we can not
5150 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5151 the pipeline until completion.
5159 An ldr instruction takes 1-3 cycles, but does not block the
5168 Best case ldr will always win. However, the more ldr instructions
5169 we issue, the less likely we are to be able to schedule them well.
5170 Using ldr instructions also increases code size.
5172 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5173 for counts of 3 or 4 regs. */
5174 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5180 for (i
= 0; i
< count
; i
++)
5182 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, i
* 4 * sign
));
5183 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5184 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5185 MEM_SCALAR_P (mem
) = scalar_p
;
5186 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
5190 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
5198 result
= gen_rtx_PARALLEL (VOIDmode
,
5199 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5202 XVECEXP (result
, 0, 0)
5203 = gen_rtx_SET (GET_MODE (from
), from
,
5204 plus_constant (from
, count
* 4 * sign
));
5209 for (j
= 0; i
< count
; i
++, j
++)
5211 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, j
* 4 * sign
));
5212 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5213 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5214 MEM_SCALAR_P (mem
) = scalar_p
;
5215 XVECEXP (result
, 0, i
)
5216 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
5223 arm_gen_store_multiple (int base_regno
, int count
, rtx to
, int up
,
5224 int write_back
, int unchanging_p
, int in_struct_p
,
5229 int sign
= up
? 1 : -1;
5232 /* See arm_gen_load_multiple for discussion of
5233 the pros/cons of ldm/stm usage for XScale. */
5234 if (arm_tune_xscale
&& count
<= 2 && ! optimize_size
)
5240 for (i
= 0; i
< count
; i
++)
5242 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, i
* 4 * sign
));
5243 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5244 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5245 MEM_SCALAR_P (mem
) = scalar_p
;
5246 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
5250 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
5258 result
= gen_rtx_PARALLEL (VOIDmode
,
5259 rtvec_alloc (count
+ (write_back
? 1 : 0)));
5262 XVECEXP (result
, 0, 0)
5263 = gen_rtx_SET (GET_MODE (to
), to
,
5264 plus_constant (to
, count
* 4 * sign
));
5269 for (j
= 0; i
< count
; i
++, j
++)
5271 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, j
* 4 * sign
));
5272 RTX_UNCHANGING_P (mem
) = unchanging_p
;
5273 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
5274 MEM_SCALAR_P (mem
) = scalar_p
;
5276 XVECEXP (result
, 0, i
)
5277 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
5284 arm_gen_movstrqi (rtx
*operands
)
5286 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
5289 rtx st_src
, st_dst
, fin_src
, fin_dst
;
5290 rtx part_bytes_reg
= NULL
;
5292 int dst_unchanging_p
, dst_in_struct_p
, src_unchanging_p
, src_in_struct_p
;
5293 int dst_scalar_p
, src_scalar_p
;
5295 if (GET_CODE (operands
[2]) != CONST_INT
5296 || GET_CODE (operands
[3]) != CONST_INT
5297 || INTVAL (operands
[2]) > 64
5298 || INTVAL (operands
[3]) & 3)
5301 st_dst
= XEXP (operands
[0], 0);
5302 st_src
= XEXP (operands
[1], 0);
5304 dst_unchanging_p
= RTX_UNCHANGING_P (operands
[0]);
5305 dst_in_struct_p
= MEM_IN_STRUCT_P (operands
[0]);
5306 dst_scalar_p
= MEM_SCALAR_P (operands
[0]);
5307 src_unchanging_p
= RTX_UNCHANGING_P (operands
[1]);
5308 src_in_struct_p
= MEM_IN_STRUCT_P (operands
[1]);
5309 src_scalar_p
= MEM_SCALAR_P (operands
[1]);
5311 fin_dst
= dst
= copy_to_mode_reg (SImode
, st_dst
);
5312 fin_src
= src
= copy_to_mode_reg (SImode
, st_src
);
5314 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
5315 out_words_to_go
= INTVAL (operands
[2]) / 4;
5316 last_bytes
= INTVAL (operands
[2]) & 3;
5318 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
5319 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
5321 for (i
= 0; in_words_to_go
>= 2; i
+=4)
5323 if (in_words_to_go
> 4)
5324 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
5329 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
5330 FALSE
, src_unchanging_p
,
5331 src_in_struct_p
, src_scalar_p
));
5333 if (out_words_to_go
)
5335 if (out_words_to_go
> 4)
5336 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
5340 else if (out_words_to_go
!= 1)
5341 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
5350 mem
= gen_rtx_MEM (SImode
, dst
);
5351 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5352 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5353 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5354 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
5355 if (last_bytes
!= 0)
5356 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
5360 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
5361 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
5364 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5365 if (out_words_to_go
)
5369 mem
= gen_rtx_MEM (SImode
, src
);
5370 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
5371 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
5372 MEM_SCALAR_P (mem
) = src_scalar_p
;
5373 emit_move_insn (sreg
= gen_reg_rtx (SImode
), mem
);
5374 emit_move_insn (fin_src
= gen_reg_rtx (SImode
), plus_constant (src
, 4));
5376 mem
= gen_rtx_MEM (SImode
, dst
);
5377 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5378 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5379 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5380 emit_move_insn (mem
, sreg
);
5381 emit_move_insn (fin_dst
= gen_reg_rtx (SImode
), plus_constant (dst
, 4));
5384 if (in_words_to_go
) /* Sanity check */
5390 if (in_words_to_go
< 0)
5393 mem
= gen_rtx_MEM (SImode
, src
);
5394 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
5395 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
5396 MEM_SCALAR_P (mem
) = src_scalar_p
;
5397 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
5400 if (last_bytes
&& part_bytes_reg
== NULL
)
5403 if (BYTES_BIG_ENDIAN
&& last_bytes
)
5405 rtx tmp
= gen_reg_rtx (SImode
);
5407 /* The bytes we want are in the top end of the word. */
5408 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
5409 GEN_INT (8 * (4 - last_bytes
))));
5410 part_bytes_reg
= tmp
;
5414 mem
= gen_rtx_MEM (QImode
, plus_constant (dst
, last_bytes
- 1));
5415 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5416 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5417 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5418 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
5422 tmp
= gen_reg_rtx (SImode
);
5423 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
5424 part_bytes_reg
= tmp
;
5433 mem
= gen_rtx_MEM (HImode
, dst
);
5434 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5435 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5436 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5437 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
5441 rtx tmp
= gen_reg_rtx (SImode
);
5443 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (2)));
5444 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
5445 part_bytes_reg
= tmp
;
5451 mem
= gen_rtx_MEM (QImode
, dst
);
5452 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
5453 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
5454 MEM_SCALAR_P (mem
) = dst_scalar_p
;
5455 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
5462 /* Generate a memory reference for a half word, such that it will be loaded
5463 into the top 16 bits of the word. We can assume that the address is
5464 known to be alignable and of the form reg, or plus (reg, const). */
5467 arm_gen_rotated_half_load (rtx memref
)
5469 HOST_WIDE_INT offset
= 0;
5470 rtx base
= XEXP (memref
, 0);
5472 if (GET_CODE (base
) == PLUS
)
5474 offset
= INTVAL (XEXP (base
, 1));
5475 base
= XEXP (base
, 0);
5478 /* If we aren't allowed to generate unaligned addresses, then fail. */
5479 if (TARGET_MMU_TRAPS
5480 && ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 0)))
5483 base
= gen_rtx_MEM (SImode
, plus_constant (base
, offset
& ~2));
5485 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 2))
5488 return gen_rtx_ROTATE (SImode
, base
, GEN_INT (16));
5491 /* Select a dominance comparison mode if possible for a test of the general
5492 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
5493 COND_OR == DOM_CC_X_AND_Y => (X && Y)
5494 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
5495 COND_OR == DOM_CC_X_OR_Y => (X || Y)
5496 In all cases OP will be either EQ or NE, but we don't need to know which
5497 here. If we are unable to support a dominance comparison we return
5498 CC mode. This will then fail to match for the RTL expressions that
5499 generate this call. */
5501 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
5503 enum rtx_code cond1
, cond2
;
5506 /* Currently we will probably get the wrong result if the individual
5507 comparisons are not simple. This also ensures that it is safe to
5508 reverse a comparison if necessary. */
5509 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
5511 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
5515 /* The if_then_else variant of this tests the second condition if the
5516 first passes, but is true if the first fails. Reverse the first
5517 condition to get a true "inclusive-or" expression. */
5518 if (cond_or
== DOM_CC_NX_OR_Y
)
5519 cond1
= reverse_condition (cond1
);
5521 /* If the comparisons are not equal, and one doesn't dominate the other,
5522 then we can't do this. */
5524 && !comparison_dominates_p (cond1
, cond2
)
5525 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
5530 enum rtx_code temp
= cond1
;
5538 if (cond2
== EQ
|| cond_or
== DOM_CC_X_AND_Y
)
5543 case LE
: return CC_DLEmode
;
5544 case LEU
: return CC_DLEUmode
;
5545 case GE
: return CC_DGEmode
;
5546 case GEU
: return CC_DGEUmode
;
5553 if (cond2
== LT
|| cond_or
== DOM_CC_X_AND_Y
)
5562 if (cond2
== GT
|| cond_or
== DOM_CC_X_AND_Y
)
5571 if (cond2
== LTU
|| cond_or
== DOM_CC_X_AND_Y
)
5580 if (cond2
== GTU
|| cond_or
== DOM_CC_X_AND_Y
)
5588 /* The remaining cases only occur when both comparisons are the
5613 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
5615 /* All floating point compares return CCFP if it is an equality
5616 comparison, and CCFPE otherwise. */
5617 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5646 /* A compare with a shifted operand. Because of canonicalization, the
5647 comparison will have to be swapped when we emit the assembler. */
5648 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
5649 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
5650 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
5651 || GET_CODE (x
) == ROTATERT
))
5654 /* This is a special case that is used by combine to allow a
5655 comparison of a shifted byte load to be split into a zero-extend
5656 followed by a comparison of the shifted integer (only valid for
5657 equalities and unsigned inequalities). */
5658 if (GET_MODE (x
) == SImode
5659 && GET_CODE (x
) == ASHIFT
5660 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
5661 && GET_CODE (XEXP (x
, 0)) == SUBREG
5662 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
5663 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
5664 && (op
== EQ
|| op
== NE
5665 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
5666 && GET_CODE (y
) == CONST_INT
)
5669 /* A construct for a conditional compare, if the false arm contains
5670 0, then both conditions must be true, otherwise either condition
5671 must be true. Not all conditions are possible, so CCmode is
5672 returned if it can't be done. */
5673 if (GET_CODE (x
) == IF_THEN_ELSE
5674 && (XEXP (x
, 2) == const0_rtx
5675 || XEXP (x
, 2) == const1_rtx
)
5676 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
5677 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
5678 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
5679 INTVAL (XEXP (x
, 2)));
5681 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
5682 if (GET_CODE (x
) == AND
5683 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
5684 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
5685 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
5688 if (GET_CODE (x
) == IOR
5689 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
5690 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
5691 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
5694 /* An operation (on Thumb) where we want to test for a single bit.
5695 This is done by shifting that bit up into the top bit of a
5696 scratch register; we can then branch on the sign bit. */
5698 && GET_MODE (x
) == SImode
5699 && (op
== EQ
|| op
== NE
)
5700 && (GET_CODE (x
) == ZERO_EXTRACT
))
5703 /* An operation that sets the condition codes as a side-effect, the
5704 V flag is not set correctly, so we can only use comparisons where
5705 this doesn't matter. (For LT and GE we can use "mi" and "pl"
5707 if (GET_MODE (x
) == SImode
5709 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
5710 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
5711 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
5712 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
5713 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
5714 || GET_CODE (x
) == LSHIFTRT
5715 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
5716 || GET_CODE (x
) == ROTATERT
5717 || (TARGET_ARM
&& GET_CODE (x
) == ZERO_EXTRACT
)))
5720 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
5723 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
5724 && GET_CODE (x
) == PLUS
5725 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
5731 /* X and Y are two things to compare using CODE. Emit the compare insn and
5732 return the rtx for register 0 in the proper mode. FP means this is a
5733 floating point compare: I don't think that it is needed on the arm. */
5735 arm_gen_compare_reg (enum rtx_code code
, rtx x
, rtx y
)
5737 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
5738 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
5740 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
5741 gen_rtx_COMPARE (mode
, x
, y
)));
5746 /* Generate a sequence of insns that will generate the correct return
5747 address mask depending on the physical architecture that the program
5750 arm_gen_return_addr_mask (void)
5752 rtx reg
= gen_reg_rtx (Pmode
);
5754 emit_insn (gen_return_addr_mask (reg
));
5759 arm_reload_in_hi (rtx
*operands
)
5761 rtx ref
= operands
[1];
5763 HOST_WIDE_INT offset
= 0;
5765 if (GET_CODE (ref
) == SUBREG
)
5767 offset
= SUBREG_BYTE (ref
);
5768 ref
= SUBREG_REG (ref
);
5771 if (GET_CODE (ref
) == REG
)
5773 /* We have a pseudo which has been spilt onto the stack; there
5774 are two cases here: the first where there is a simple
5775 stack-slot replacement and a second where the stack-slot is
5776 out of range, or is used as a subreg. */
5777 if (reg_equiv_mem
[REGNO (ref
)])
5779 ref
= reg_equiv_mem
[REGNO (ref
)];
5780 base
= find_replacement (&XEXP (ref
, 0));
5783 /* The slot is out of range, or was dressed up in a SUBREG. */
5784 base
= reg_equiv_address
[REGNO (ref
)];
5787 base
= find_replacement (&XEXP (ref
, 0));
5789 /* Handle the case where the address is too complex to be offset by 1. */
5790 if (GET_CODE (base
) == MINUS
5791 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
5793 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5795 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
5798 else if (GET_CODE (base
) == PLUS
)
5800 /* The addend must be CONST_INT, or we would have dealt with it above. */
5801 HOST_WIDE_INT hi
, lo
;
5803 offset
+= INTVAL (XEXP (base
, 1));
5804 base
= XEXP (base
, 0);
5806 /* Rework the address into a legal sequence of insns. */
5807 /* Valid range for lo is -4095 -> 4095 */
5810 : -((-offset
) & 0xfff));
5812 /* Corner case, if lo is the max offset then we would be out of range
5813 once we have added the additional 1 below, so bump the msb into the
5814 pre-loading insn(s). */
5818 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
5819 ^ (HOST_WIDE_INT
) 0x80000000)
5820 - (HOST_WIDE_INT
) 0x80000000);
5822 if (hi
+ lo
!= offset
)
5827 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5829 /* Get the base address; addsi3 knows how to handle constants
5830 that require more than one insn. */
5831 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
5837 /* Operands[2] may overlap operands[0] (though it won't overlap
5838 operands[1]), that's why we asked for a DImode reg -- so we can
5839 use the bit that does not overlap. */
5840 if (REGNO (operands
[2]) == REGNO (operands
[0]))
5841 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5843 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
5845 emit_insn (gen_zero_extendqisi2 (scratch
,
5846 gen_rtx_MEM (QImode
,
5847 plus_constant (base
,
5849 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
5850 gen_rtx_MEM (QImode
,
5851 plus_constant (base
,
5853 if (!BYTES_BIG_ENDIAN
)
5854 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
5855 gen_rtx_IOR (SImode
,
5858 gen_rtx_SUBREG (SImode
, operands
[0], 0),
5862 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
5863 gen_rtx_IOR (SImode
,
5864 gen_rtx_ASHIFT (SImode
, scratch
,
5866 gen_rtx_SUBREG (SImode
, operands
[0],
5870 /* Handle storing a half-word to memory during reload by synthesizing as two
5871 byte stores. Take care not to clobber the input values until after we
5872 have moved them somewhere safe. This code assumes that if the DImode
5873 scratch in operands[2] overlaps either the input value or output address
5874 in some way, then that value must die in this insn (we absolutely need
5875 two scratch registers for some corner cases). */
5877 arm_reload_out_hi (rtx
*operands
)
5879 rtx ref
= operands
[0];
5880 rtx outval
= operands
[1];
5882 HOST_WIDE_INT offset
= 0;
5884 if (GET_CODE (ref
) == SUBREG
)
5886 offset
= SUBREG_BYTE (ref
);
5887 ref
= SUBREG_REG (ref
);
5890 if (GET_CODE (ref
) == REG
)
5892 /* We have a pseudo which has been spilt onto the stack; there
5893 are two cases here: the first where there is a simple
5894 stack-slot replacement and a second where the stack-slot is
5895 out of range, or is used as a subreg. */
5896 if (reg_equiv_mem
[REGNO (ref
)])
5898 ref
= reg_equiv_mem
[REGNO (ref
)];
5899 base
= find_replacement (&XEXP (ref
, 0));
5902 /* The slot is out of range, or was dressed up in a SUBREG. */
5903 base
= reg_equiv_address
[REGNO (ref
)];
5906 base
= find_replacement (&XEXP (ref
, 0));
5908 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
5910 /* Handle the case where the address is too complex to be offset by 1. */
5911 if (GET_CODE (base
) == MINUS
5912 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
5914 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5916 /* Be careful not to destroy OUTVAL. */
5917 if (reg_overlap_mentioned_p (base_plus
, outval
))
5919 /* Updating base_plus might destroy outval, see if we can
5920 swap the scratch and base_plus. */
5921 if (!reg_overlap_mentioned_p (scratch
, outval
))
5924 scratch
= base_plus
;
5929 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
5931 /* Be conservative and copy OUTVAL into the scratch now,
5932 this should only be necessary if outval is a subreg
5933 of something larger than a word. */
5934 /* XXX Might this clobber base? I can't see how it can,
5935 since scratch is known to overlap with OUTVAL, and
5936 must be wider than a word. */
5937 emit_insn (gen_movhi (scratch_hi
, outval
));
5938 outval
= scratch_hi
;
5942 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
5945 else if (GET_CODE (base
) == PLUS
)
5947 /* The addend must be CONST_INT, or we would have dealt with it above. */
5948 HOST_WIDE_INT hi
, lo
;
5950 offset
+= INTVAL (XEXP (base
, 1));
5951 base
= XEXP (base
, 0);
5953 /* Rework the address into a legal sequence of insns. */
5954 /* Valid range for lo is -4095 -> 4095 */
5957 : -((-offset
) & 0xfff));
5959 /* Corner case, if lo is the max offset then we would be out of range
5960 once we have added the additional 1 below, so bump the msb into the
5961 pre-loading insn(s). */
5965 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
5966 ^ (HOST_WIDE_INT
) 0x80000000)
5967 - (HOST_WIDE_INT
) 0x80000000);
5969 if (hi
+ lo
!= offset
)
5974 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5976 /* Be careful not to destroy OUTVAL. */
5977 if (reg_overlap_mentioned_p (base_plus
, outval
))
5979 /* Updating base_plus might destroy outval, see if we
5980 can swap the scratch and base_plus. */
5981 if (!reg_overlap_mentioned_p (scratch
, outval
))
5984 scratch
= base_plus
;
5989 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
5991 /* Be conservative and copy outval into scratch now,
5992 this should only be necessary if outval is a
5993 subreg of something larger than a word. */
5994 /* XXX Might this clobber base? I can't see how it
5995 can, since scratch is known to overlap with
5997 emit_insn (gen_movhi (scratch_hi
, outval
));
5998 outval
= scratch_hi
;
6002 /* Get the base address; addsi3 knows how to handle constants
6003 that require more than one insn. */
6004 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
6010 if (BYTES_BIG_ENDIAN
)
6012 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6013 plus_constant (base
, offset
+ 1)),
6014 gen_lowpart (QImode
, outval
)));
6015 emit_insn (gen_lshrsi3 (scratch
,
6016 gen_rtx_SUBREG (SImode
, outval
, 0),
6018 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6019 gen_lowpart (QImode
, scratch
)));
6023 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
6024 gen_lowpart (QImode
, outval
)));
6025 emit_insn (gen_lshrsi3 (scratch
,
6026 gen_rtx_SUBREG (SImode
, outval
, 0),
6028 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
6029 plus_constant (base
, offset
+ 1)),
6030 gen_lowpart (QImode
, scratch
)));
6034 /* Print a symbolic form of X to the debug file, F. */
6036 arm_print_value (FILE *f
, rtx x
)
6038 switch (GET_CODE (x
))
6041 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
6045 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
6053 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
6055 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
6056 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
6064 fprintf (f
, "\"%s\"", XSTR (x
, 0));
6068 fprintf (f
, "`%s'", XSTR (x
, 0));
6072 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
6076 arm_print_value (f
, XEXP (x
, 0));
6080 arm_print_value (f
, XEXP (x
, 0));
6082 arm_print_value (f
, XEXP (x
, 1));
6090 fprintf (f
, "????");
6095 /* Routines for manipulation of the constant pool. */
6097 /* Arm instructions cannot load a large constant directly into a
6098 register; they have to come from a pc relative load. The constant
6099 must therefore be placed in the addressable range of the pc
6100 relative load. Depending on the precise pc relative load
6101 instruction the range is somewhere between 256 bytes and 4k. This
6102 means that we often have to dump a constant inside a function, and
6103 generate code to branch around it.
6105 It is important to minimize this, since the branches will slow
6106 things down and make the code larger.
6108 Normally we can hide the table after an existing unconditional
6109 branch so that there is no interruption of the flow, but in the
6110 worst case the code looks like this:
6128 We fix this by performing a scan after scheduling, which notices
6129 which instructions need to have their operands fetched from the
6130 constant table and builds the table.
6132 The algorithm starts by building a table of all the constants that
6133 need fixing up and all the natural barriers in the function (places
6134 where a constant table can be dropped without breaking the flow).
6135 For each fixup we note how far the pc-relative replacement will be
6136 able to reach and the offset of the instruction into the function.
6138 Having built the table we then group the fixes together to form
6139 tables that are as large as possible (subject to addressing
6140 constraints) and emit each table of constants after the last
6141 barrier that is within range of all the instructions in the group.
6142 If a group does not contain a barrier, then we forcibly create one
6143 by inserting a jump instruction into the flow. Once the table has
6144 been inserted, the insns are then modified to reference the
6145 relevant entry in the pool.
6147 Possible enhancements to the algorithm (not implemented) are:
6149 1) For some processors and object formats, there may be benefit in
6150 aligning the pools to the start of cache lines; this alignment
6151 would need to be taken into account when calculating addressability
6154 /* These typedefs are located at the start of this file, so that
6155 they can be used in the prototypes there. This comment is to
6156 remind readers of that fact so that the following structures
6157 can be understood more easily.
6159 typedef struct minipool_node Mnode;
6160 typedef struct minipool_fixup Mfix; */
6162 struct minipool_node
6164 /* Doubly linked chain of entries. */
6167 /* The maximum offset into the code that this entry can be placed. While
6168 pushing fixes for forward references, all entries are sorted in order
6169 of increasing max_address. */
6170 HOST_WIDE_INT max_address
;
6171 /* Similarly for an entry inserted for a backwards ref. */
6172 HOST_WIDE_INT min_address
;
6173 /* The number of fixes referencing this entry. This can become zero
6174 if we "unpush" an entry. In this case we ignore the entry when we
6175 come to emit the code. */
6177 /* The offset from the start of the minipool. */
6178 HOST_WIDE_INT offset
;
6179 /* The value in table. */
6181 /* The mode of value. */
6182 enum machine_mode mode
;
6183 /* The size of the value. With iWMMXt enabled
6184 sizes > 4 also imply an alignment of 8-bytes. */
6188 struct minipool_fixup
6192 HOST_WIDE_INT address
;
6194 enum machine_mode mode
;
6198 HOST_WIDE_INT forwards
;
6199 HOST_WIDE_INT backwards
;
6202 /* Fixes less than a word need padding out to a word boundary. */
6203 #define MINIPOOL_FIX_SIZE(mode) \
6204 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6206 static Mnode
* minipool_vector_head
;
6207 static Mnode
* minipool_vector_tail
;
6208 static rtx minipool_vector_label
;
6210 /* The linked list of all minipool fixes required for this function. */
6211 Mfix
* minipool_fix_head
;
6212 Mfix
* minipool_fix_tail
;
6213 /* The fix entry for the current minipool, once it has been placed. */
6214 Mfix
* minipool_barrier
;
6216 /* Determines if INSN is the start of a jump table. Returns the end
6217 of the TABLE or NULL_RTX. */
6219 is_jump_table (rtx insn
)
6223 if (GET_CODE (insn
) == JUMP_INSN
6224 && JUMP_LABEL (insn
) != NULL
6225 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
6226 == next_real_insn (insn
))
6228 && GET_CODE (table
) == JUMP_INSN
6229 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
6230 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
6236 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6237 #define JUMP_TABLES_IN_TEXT_SECTION 0
6240 static HOST_WIDE_INT
6241 get_jump_table_size (rtx insn
)
6243 /* ADDR_VECs only take room if read-only data does into the text
6245 if (JUMP_TABLES_IN_TEXT_SECTION
6246 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6251 rtx body
= PATTERN (insn
);
6252 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
6254 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
6260 /* Move a minipool fix MP from its current location to before MAX_MP.
6261 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6262 constraints may need updating. */
6264 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
6265 HOST_WIDE_INT max_address
)
6267 /* This should never be true and the code below assumes these are
6274 if (max_address
< mp
->max_address
)
6275 mp
->max_address
= max_address
;
6279 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
6280 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
6282 mp
->max_address
= max_address
;
6284 /* Unlink MP from its current position. Since max_mp is non-null,
6285 mp->prev must be non-null. */
6286 mp
->prev
->next
= mp
->next
;
6287 if (mp
->next
!= NULL
)
6288 mp
->next
->prev
= mp
->prev
;
6290 minipool_vector_tail
= mp
->prev
;
6292 /* Re-insert it before MAX_MP. */
6294 mp
->prev
= max_mp
->prev
;
6297 if (mp
->prev
!= NULL
)
6298 mp
->prev
->next
= mp
;
6300 minipool_vector_head
= mp
;
6303 /* Save the new entry. */
6306 /* Scan over the preceding entries and adjust their addresses as
6308 while (mp
->prev
!= NULL
6309 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
6311 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
6318 /* Add a constant to the minipool for a forward reference. Returns the
6319 node added or NULL if the constant will not fit in this pool. */
6321 add_minipool_forward_ref (Mfix
*fix
)
6323 /* If set, max_mp is the first pool_entry that has a lower
6324 constraint than the one we are trying to add. */
6325 Mnode
* max_mp
= NULL
;
6326 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
6329 /* If this fix's address is greater than the address of the first
6330 entry, then we can't put the fix in this pool. We subtract the
6331 size of the current fix to ensure that if the table is fully
6332 packed we still have enough room to insert this value by suffling
6333 the other fixes forwards. */
6334 if (minipool_vector_head
&&
6335 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
6338 /* Scan the pool to see if a constant with the same value has
6339 already been added. While we are doing this, also note the
6340 location where we must insert the constant if it doesn't already
6342 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6344 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
6345 && fix
->mode
== mp
->mode
6346 && (GET_CODE (fix
->value
) != CODE_LABEL
6347 || (CODE_LABEL_NUMBER (fix
->value
)
6348 == CODE_LABEL_NUMBER (mp
->value
)))
6349 && rtx_equal_p (fix
->value
, mp
->value
))
6351 /* More than one fix references this entry. */
6353 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
6356 /* Note the insertion point if necessary. */
6358 && mp
->max_address
> max_address
)
6361 /* If we are inserting an 8-bytes aligned quantity and
6362 we have not already found an insertion point, then
6363 make sure that all such 8-byte aligned quantities are
6364 placed at the start of the pool. */
6365 if (TARGET_REALLY_IWMMXT
6367 && fix
->fix_size
== 8
6368 && mp
->fix_size
!= 8)
6371 max_address
= mp
->max_address
;
6375 /* The value is not currently in the minipool, so we need to create
6376 a new entry for it. If MAX_MP is NULL, the entry will be put on
6377 the end of the list since the placement is less constrained than
6378 any existing entry. Otherwise, we insert the new fix before
6379 MAX_MP and, if necessary, adjust the constraints on the other
6381 mp
= xmalloc (sizeof (* mp
));
6382 mp
->fix_size
= fix
->fix_size
;
6383 mp
->mode
= fix
->mode
;
6384 mp
->value
= fix
->value
;
6386 /* Not yet required for a backwards ref. */
6387 mp
->min_address
= -65536;
6391 mp
->max_address
= max_address
;
6393 mp
->prev
= minipool_vector_tail
;
6395 if (mp
->prev
== NULL
)
6397 minipool_vector_head
= mp
;
6398 minipool_vector_label
= gen_label_rtx ();
6401 mp
->prev
->next
= mp
;
6403 minipool_vector_tail
= mp
;
6407 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
6408 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
6410 mp
->max_address
= max_address
;
6413 mp
->prev
= max_mp
->prev
;
6415 if (mp
->prev
!= NULL
)
6416 mp
->prev
->next
= mp
;
6418 minipool_vector_head
= mp
;
6421 /* Save the new entry. */
6424 /* Scan over the preceding entries and adjust their addresses as
6426 while (mp
->prev
!= NULL
6427 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
6429 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
6437 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
6438 HOST_WIDE_INT min_address
)
6440 HOST_WIDE_INT offset
;
6442 /* This should never be true, and the code below assumes these are
6449 if (min_address
> mp
->min_address
)
6450 mp
->min_address
= min_address
;
6454 /* We will adjust this below if it is too loose. */
6455 mp
->min_address
= min_address
;
6457 /* Unlink MP from its current position. Since min_mp is non-null,
6458 mp->next must be non-null. */
6459 mp
->next
->prev
= mp
->prev
;
6460 if (mp
->prev
!= NULL
)
6461 mp
->prev
->next
= mp
->next
;
6463 minipool_vector_head
= mp
->next
;
6465 /* Reinsert it after MIN_MP. */
6467 mp
->next
= min_mp
->next
;
6469 if (mp
->next
!= NULL
)
6470 mp
->next
->prev
= mp
;
6472 minipool_vector_tail
= mp
;
6478 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6480 mp
->offset
= offset
;
6481 if (mp
->refcount
> 0)
6482 offset
+= mp
->fix_size
;
6484 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
6485 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
6491 /* Add a constant to the minipool for a backward reference. Returns the
6492 node added or NULL if the constant will not fit in this pool.
6494 Note that the code for insertion for a backwards reference can be
6495 somewhat confusing because the calculated offsets for each fix do
6496 not take into account the size of the pool (which is still under
6499 add_minipool_backward_ref (Mfix
*fix
)
6501 /* If set, min_mp is the last pool_entry that has a lower constraint
6502 than the one we are trying to add. */
6503 Mnode
*min_mp
= NULL
;
6504 /* This can be negative, since it is only a constraint. */
6505 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
6508 /* If we can't reach the current pool from this insn, or if we can't
6509 insert this entry at the end of the pool without pushing other
6510 fixes out of range, then we don't try. This ensures that we
6511 can't fail later on. */
6512 if (min_address
>= minipool_barrier
->address
6513 || (minipool_vector_tail
->min_address
+ fix
->fix_size
6514 >= minipool_barrier
->address
))
6517 /* Scan the pool to see if a constant with the same value has
6518 already been added. While we are doing this, also note the
6519 location where we must insert the constant if it doesn't already
6521 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
6523 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
6524 && fix
->mode
== mp
->mode
6525 && (GET_CODE (fix
->value
) != CODE_LABEL
6526 || (CODE_LABEL_NUMBER (fix
->value
)
6527 == CODE_LABEL_NUMBER (mp
->value
)))
6528 && rtx_equal_p (fix
->value
, mp
->value
)
6529 /* Check that there is enough slack to move this entry to the
6530 end of the table (this is conservative). */
6532 > (minipool_barrier
->address
6533 + minipool_vector_tail
->offset
6534 + minipool_vector_tail
->fix_size
)))
6537 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
6541 mp
->min_address
+= fix
->fix_size
;
6544 /* Note the insertion point if necessary. */
6545 if (mp
->min_address
< min_address
)
6547 /* For now, we do not allow the insertion of 8-byte alignment
6548 requiring nodes anywhere but at the start of the pool. */
6549 if (TARGET_REALLY_IWMMXT
&& fix
->fix_size
== 8 && mp
->fix_size
!= 8)
6554 else if (mp
->max_address
6555 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
6557 /* Inserting before this entry would push the fix beyond
6558 its maximum address (which can happen if we have
6559 re-located a forwards fix); force the new fix to come
6562 min_address
= mp
->min_address
+ fix
->fix_size
;
6564 /* If we are inserting an 8-bytes aligned quantity and
6565 we have not already found an insertion point, then
6566 make sure that all such 8-byte aligned quantities are
6567 placed at the start of the pool. */
6568 else if (TARGET_REALLY_IWMMXT
6570 && fix
->fix_size
== 8
6571 && mp
->fix_size
< 8)
6574 min_address
= mp
->min_address
+ fix
->fix_size
;
6579 /* We need to create a new entry. */
6580 mp
= xmalloc (sizeof (* mp
));
6581 mp
->fix_size
= fix
->fix_size
;
6582 mp
->mode
= fix
->mode
;
6583 mp
->value
= fix
->value
;
6585 mp
->max_address
= minipool_barrier
->address
+ 65536;
6587 mp
->min_address
= min_address
;
6592 mp
->next
= minipool_vector_head
;
6594 if (mp
->next
== NULL
)
6596 minipool_vector_tail
= mp
;
6597 minipool_vector_label
= gen_label_rtx ();
6600 mp
->next
->prev
= mp
;
6602 minipool_vector_head
= mp
;
6606 mp
->next
= min_mp
->next
;
6610 if (mp
->next
!= NULL
)
6611 mp
->next
->prev
= mp
;
6613 minipool_vector_tail
= mp
;
6616 /* Save the new entry. */
6624 /* Scan over the following entries and adjust their offsets. */
6625 while (mp
->next
!= NULL
)
6627 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
6628 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
6631 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
6633 mp
->next
->offset
= mp
->offset
;
6642 assign_minipool_offsets (Mfix
*barrier
)
6644 HOST_WIDE_INT offset
= 0;
6647 minipool_barrier
= barrier
;
6649 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6651 mp
->offset
= offset
;
6653 if (mp
->refcount
> 0)
6654 offset
+= mp
->fix_size
;
6658 /* Output the literal table */
6660 dump_minipool (rtx scan
)
6666 if (TARGET_REALLY_IWMMXT
)
6667 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
6668 if (mp
->refcount
> 0 && mp
->fix_size
== 8)
6675 fprintf (rtl_dump_file
,
6676 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
6677 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
6679 scan
= emit_label_after (gen_label_rtx (), scan
);
6680 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
6681 scan
= emit_label_after (minipool_vector_label
, scan
);
6683 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
6685 if (mp
->refcount
> 0)
6689 fprintf (rtl_dump_file
,
6690 ";; Offset %u, min %ld, max %ld ",
6691 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
6692 (unsigned long) mp
->max_address
);
6693 arm_print_value (rtl_dump_file
, mp
->value
);
6694 fputc ('\n', rtl_dump_file
);
6697 switch (mp
->fix_size
)
6699 #ifdef HAVE_consttable_1
6701 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
6705 #ifdef HAVE_consttable_2
6707 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
6711 #ifdef HAVE_consttable_4
6713 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
6717 #ifdef HAVE_consttable_8
6719 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
6733 minipool_vector_head
= minipool_vector_tail
= NULL
;
6734 scan
= emit_insn_after (gen_consttable_end (), scan
);
6735 scan
= emit_barrier_after (scan
);
6738 /* Return the cost of forcibly inserting a barrier after INSN. */
6740 arm_barrier_cost (rtx insn
)
6742 /* Basing the location of the pool on the loop depth is preferable,
6743 but at the moment, the basic block information seems to be
6744 corrupt by this stage of the compilation. */
6746 rtx next
= next_nonnote_insn (insn
);
6748 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
6751 switch (GET_CODE (insn
))
6754 /* It will always be better to place the table before the label, rather
6763 return base_cost
- 10;
6766 return base_cost
+ 10;
6770 /* Find the best place in the insn stream in the range
6771 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
6772 Create the barrier by inserting a jump and add a new fix entry for
6775 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
6777 HOST_WIDE_INT count
= 0;
6779 rtx from
= fix
->insn
;
6780 rtx selected
= from
;
6782 HOST_WIDE_INT selected_address
;
6784 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
6785 rtx label
= gen_label_rtx ();
6787 selected_cost
= arm_barrier_cost (from
);
6788 selected_address
= fix
->address
;
6790 while (from
&& count
< max_count
)
6795 /* This code shouldn't have been called if there was a natural barrier
6797 if (GET_CODE (from
) == BARRIER
)
6800 /* Count the length of this insn. */
6801 count
+= get_attr_length (from
);
6803 /* If there is a jump table, add its length. */
6804 tmp
= is_jump_table (from
);
6807 count
+= get_jump_table_size (tmp
);
6809 /* Jump tables aren't in a basic block, so base the cost on
6810 the dispatch insn. If we select this location, we will
6811 still put the pool after the table. */
6812 new_cost
= arm_barrier_cost (from
);
6814 if (count
< max_count
&& new_cost
<= selected_cost
)
6817 selected_cost
= new_cost
;
6818 selected_address
= fix
->address
+ count
;
6821 /* Continue after the dispatch table. */
6822 from
= NEXT_INSN (tmp
);
6826 new_cost
= arm_barrier_cost (from
);
6828 if (count
< max_count
&& new_cost
<= selected_cost
)
6831 selected_cost
= new_cost
;
6832 selected_address
= fix
->address
+ count
;
6835 from
= NEXT_INSN (from
);
6838 /* Create a new JUMP_INSN that branches around a barrier. */
6839 from
= emit_jump_insn_after (gen_jump (label
), selected
);
6840 JUMP_LABEL (from
) = label
;
6841 barrier
= emit_barrier_after (from
);
6842 emit_label_after (label
, barrier
);
6844 /* Create a minipool barrier entry for the new barrier. */
6845 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
6846 new_fix
->insn
= barrier
;
6847 new_fix
->address
= selected_address
;
6848 new_fix
->next
= fix
->next
;
6849 fix
->next
= new_fix
;
6854 /* Record that there is a natural barrier in the insn stream at
6857 push_minipool_barrier (rtx insn
, HOST_WIDE_INT address
)
6859 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
6862 fix
->address
= address
;
6865 if (minipool_fix_head
!= NULL
)
6866 minipool_fix_tail
->next
= fix
;
6868 minipool_fix_head
= fix
;
6870 minipool_fix_tail
= fix
;
6873 /* Record INSN, which will need fixing up to load a value from the
6874 minipool. ADDRESS is the offset of the insn since the start of the
6875 function; LOC is a pointer to the part of the insn which requires
6876 fixing; VALUE is the constant that must be loaded, which is of type
6879 push_minipool_fix (rtx insn
, HOST_WIDE_INT address
, rtx
*loc
,
6880 enum machine_mode mode
, rtx value
)
6882 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
6884 #ifdef AOF_ASSEMBLER
6885 /* PIC symbol references need to be converted into offsets into the
6887 /* XXX This shouldn't be done here. */
6888 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
6889 value
= aof_pic_entry (value
);
6890 #endif /* AOF_ASSEMBLER */
6893 fix
->address
= address
;
6896 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
6898 fix
->forwards
= get_attr_pool_range (insn
);
6899 fix
->backwards
= get_attr_neg_pool_range (insn
);
6900 fix
->minipool
= NULL
;
6902 /* If an insn doesn't have a range defined for it, then it isn't
6903 expecting to be reworked by this code. Better to abort now than
6904 to generate duff assembly code. */
6905 if (fix
->forwards
== 0 && fix
->backwards
== 0)
6908 /* With iWMMXt enabled, the pool is aligned to an 8-byte boundary.
6909 So there might be an empty word before the start of the pool.
6910 Hence we reduce the forward range by 4 to allow for this
6912 if (TARGET_REALLY_IWMMXT
&& fix
->fix_size
== 8)
6917 fprintf (rtl_dump_file
,
6918 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
6919 GET_MODE_NAME (mode
),
6920 INSN_UID (insn
), (unsigned long) address
,
6921 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
6922 arm_print_value (rtl_dump_file
, fix
->value
);
6923 fprintf (rtl_dump_file
, "\n");
6926 /* Add it to the chain of fixes. */
6929 if (minipool_fix_head
!= NULL
)
6930 minipool_fix_tail
->next
= fix
;
6932 minipool_fix_head
= fix
;
6934 minipool_fix_tail
= fix
;
6937 /* Scan INSN and note any of its operands that need fixing.
6938 If DO_PUSHES is false we do not actually push any of the fixups
6939 needed. The function returns TRUE is any fixups were needed/pushed.
6940 This is used by arm_memory_load_p() which needs to know about loads
6941 of constants that will be converted into minipool loads. */
6943 note_invalid_constants (rtx insn
, HOST_WIDE_INT address
, int do_pushes
)
6945 bool result
= false;
6948 extract_insn (insn
);
6950 if (!constrain_operands (1))
6951 fatal_insn_not_found (insn
);
6953 if (recog_data
.n_alternatives
== 0)
6956 /* Fill in recog_op_alt with information about the constraints of this insn. */
6957 preprocess_constraints ();
6959 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
6961 /* Things we need to fix can only occur in inputs. */
6962 if (recog_data
.operand_type
[opno
] != OP_IN
)
6965 /* If this alternative is a memory reference, then any mention
6966 of constants in this alternative is really to fool reload
6967 into allowing us to accept one there. We need to fix them up
6968 now so that we output the right code. */
6969 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
6971 rtx op
= recog_data
.operand
[opno
];
6973 if (CONSTANT_P (op
))
6976 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
6977 recog_data
.operand_mode
[opno
], op
);
6980 else if (GET_CODE (op
) == MEM
6981 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
6982 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
6986 rtx cop
= avoid_constant_pool_reference (op
);
6988 /* Casting the address of something to a mode narrower
6989 than a word can cause avoid_constant_pool_reference()
6990 to return the pool reference itself. That's no good to
6991 us here. Lets just hope that we can use the
6992 constant pool value directly. */
6994 cop
= get_pool_constant (XEXP (op
, 0));
6996 push_minipool_fix (insn
, address
,
6997 recog_data
.operand_loc
[opno
],
6998 recog_data
.operand_mode
[opno
], cop
);
7009 /* Gcc puts the pool in the wrong place for ARM, since we can only
7010 load addresses a limited distance around the pc. We do some
7011 special munging to move the constant pool values to the correct
7012 point in the code. */
7017 HOST_WIDE_INT address
= 0;
7020 minipool_fix_head
= minipool_fix_tail
= NULL
;
7022 /* The first insn must always be a note, or the code below won't
7023 scan it properly. */
7024 insn
= get_insns ();
7025 if (GET_CODE (insn
) != NOTE
)
7028 /* Scan all the insns and record the operands that will need fixing. */
7029 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
7031 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7032 && (arm_cirrus_insn_p (insn
)
7033 || GET_CODE (insn
) == JUMP_INSN
7034 || arm_memory_load_p (insn
)))
7035 cirrus_reorg (insn
);
7037 if (GET_CODE (insn
) == BARRIER
)
7038 push_minipool_barrier (insn
, address
);
7039 else if (INSN_P (insn
))
7043 note_invalid_constants (insn
, address
, true);
7044 address
+= get_attr_length (insn
);
7046 /* If the insn is a vector jump, add the size of the table
7047 and skip the table. */
7048 if ((table
= is_jump_table (insn
)) != NULL
)
7050 address
+= get_jump_table_size (table
);
7056 fix
= minipool_fix_head
;
7058 /* Now scan the fixups and perform the required changes. */
7063 Mfix
* last_added_fix
;
7064 Mfix
* last_barrier
= NULL
;
7067 /* Skip any further barriers before the next fix. */
7068 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
7071 /* No more fixes. */
7075 last_added_fix
= NULL
;
7077 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
7079 if (GET_CODE (ftmp
->insn
) == BARRIER
)
7081 if (ftmp
->address
>= minipool_vector_head
->max_address
)
7084 last_barrier
= ftmp
;
7086 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
7089 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
7092 /* If we found a barrier, drop back to that; any fixes that we
7093 could have reached but come after the barrier will now go in
7094 the next mini-pool. */
7095 if (last_barrier
!= NULL
)
7097 /* Reduce the refcount for those fixes that won't go into this
7099 for (fdel
= last_barrier
->next
;
7100 fdel
&& fdel
!= ftmp
;
7103 fdel
->minipool
->refcount
--;
7104 fdel
->minipool
= NULL
;
7107 ftmp
= last_barrier
;
7111 /* ftmp is first fix that we can't fit into this pool and
7112 there no natural barriers that we could use. Insert a
7113 new barrier in the code somewhere between the previous
7114 fix and this one, and arrange to jump around it. */
7115 HOST_WIDE_INT max_address
;
7117 /* The last item on the list of fixes must be a barrier, so
7118 we can never run off the end of the list of fixes without
7119 last_barrier being set. */
7123 max_address
= minipool_vector_head
->max_address
;
7124 /* Check that there isn't another fix that is in range that
7125 we couldn't fit into this pool because the pool was
7126 already too large: we need to put the pool before such an
7128 if (ftmp
->address
< max_address
)
7129 max_address
= ftmp
->address
;
7131 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
7134 assign_minipool_offsets (last_barrier
);
7138 if (GET_CODE (ftmp
->insn
) != BARRIER
7139 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
7146 /* Scan over the fixes we have identified for this pool, fixing them
7147 up and adding the constants to the pool itself. */
7148 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
7149 this_fix
= this_fix
->next
)
7150 if (GET_CODE (this_fix
->insn
) != BARRIER
)
7153 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
7154 minipool_vector_label
),
7155 this_fix
->minipool
->offset
);
7156 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
7159 dump_minipool (last_barrier
->insn
);
7163 /* From now on we must synthesize any constants that we can't handle
7164 directly. This can happen if the RTL gets split during final
7165 instruction generation. */
7166 after_arm_reorg
= 1;
7168 /* Free the minipool memory. */
7169 obstack_free (&minipool_obstack
, minipool_startobj
);
7172 /* Routines to output assembly language. */
7174 /* If the rtx is the correct value then return the string of the number.
7175 In this way we can ensure that valid double constants are generated even
7176 when cross compiling. */
7178 fp_immediate_constant (rtx x
)
7183 if (!fpa_consts_inited
)
7186 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
7187 for (i
= 0; i
< 8; i
++)
7188 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
7189 return strings_fpa
[i
];
7194 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7196 fp_const_from_val (REAL_VALUE_TYPE
*r
)
7200 if (!fpa_consts_inited
)
7203 for (i
= 0; i
< 8; i
++)
7204 if (REAL_VALUES_EQUAL (*r
, values_fpa
[i
]))
7205 return strings_fpa
[i
];
7210 /* Output the operands of a LDM/STM instruction to STREAM.
7211 MASK is the ARM register set mask of which only bits 0-15 are important.
7212 REG is the base register, either the frame pointer or the stack pointer,
7213 INSTR is the possibly suffixed load or store instruction. */
7215 print_multi_reg (FILE *stream
, const char *instr
, int reg
, int mask
)
7218 int not_first
= FALSE
;
7220 fputc ('\t', stream
);
7221 asm_fprintf (stream
, instr
, reg
);
7222 fputs (", {", stream
);
7224 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7225 if (mask
& (1 << i
))
7228 fprintf (stream
, ", ");
7230 asm_fprintf (stream
, "%r", i
);
7234 fprintf (stream
, "}");
7236 /* Add a ^ character for the 26-bit ABI, but only if we were loading
7237 the PC. Otherwise we would generate an UNPREDICTABLE instruction.
7238 Strictly speaking the instruction would be unpredicatble only if
7239 we were writing back the base register as well, but since we never
7240 want to generate an LDM type 2 instruction (register bank switching)
7241 which is what you get if the PC is not being loaded, we do not need
7242 to check for writeback. */
7243 if (! TARGET_APCS_32
7244 && ((mask
& (1 << PC_REGNUM
)) != 0))
7245 fprintf (stream
, "^");
7247 fprintf (stream
, "\n");
7250 /* Output a 'call' insn. */
7252 output_call (rtx
*operands
)
7254 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
7256 if (REGNO (operands
[0]) == LR_REGNUM
)
7258 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
7259 output_asm_insn ("mov%?\t%0, %|lr", operands
);
7262 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7264 if (TARGET_INTERWORK
)
7265 output_asm_insn ("bx%?\t%0", operands
);
7267 output_asm_insn ("mov%?\t%|pc, %0", operands
);
7272 /* Output a 'call' insn that is a reference in memory. */
7274 output_call_mem (rtx
*operands
)
7276 if (TARGET_INTERWORK
)
7278 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
7279 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7280 output_asm_insn ("bx%?\t%|ip", operands
);
7282 else if (regno_use_in (LR_REGNUM
, operands
[0]))
7284 /* LR is used in the memory address. We load the address in the
7285 first instruction. It's safe to use IP as the target of the
7286 load since the call will kill it anyway. */
7287 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
7288 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7289 output_asm_insn ("mov%?\t%|pc, %|ip", operands
);
7293 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
7294 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
7301 /* Output a move from arm registers to an fpa registers.
7302 OPERANDS[0] is an fpa register.
7303 OPERANDS[1] is the first registers of an arm register pair. */
7305 output_mov_long_double_fpa_from_arm (rtx
*operands
)
7307 int arm_reg0
= REGNO (operands
[1]);
7310 if (arm_reg0
== IP_REGNUM
)
7313 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7314 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7315 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
7317 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
7318 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
7323 /* Output a move from an fpa register to arm registers.
7324 OPERANDS[0] is the first registers of an arm register pair.
7325 OPERANDS[1] is an fpa register. */
7327 output_mov_long_double_arm_from_fpa (rtx
*operands
)
7329 int arm_reg0
= REGNO (operands
[0]);
7332 if (arm_reg0
== IP_REGNUM
)
7335 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7336 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7337 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
7339 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
7340 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
7344 /* Output a move from arm registers to arm registers of a long double
7345 OPERANDS[0] is the destination.
7346 OPERANDS[1] is the source. */
7348 output_mov_long_double_arm_from_arm (rtx
*operands
)
7350 /* We have to be careful here because the two might overlap. */
7351 int dest_start
= REGNO (operands
[0]);
7352 int src_start
= REGNO (operands
[1]);
7356 if (dest_start
< src_start
)
7358 for (i
= 0; i
< 3; i
++)
7360 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
7361 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
7362 output_asm_insn ("mov%?\t%0, %1", ops
);
7367 for (i
= 2; i
>= 0; i
--)
7369 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
7370 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
7371 output_asm_insn ("mov%?\t%0, %1", ops
);
7379 /* Output a move from arm registers to an fpa registers.
7380 OPERANDS[0] is an fpa register.
7381 OPERANDS[1] is the first registers of an arm register pair. */
7383 output_mov_double_fpa_from_arm (rtx
*operands
)
7385 int arm_reg0
= REGNO (operands
[1]);
7388 if (arm_reg0
== IP_REGNUM
)
7391 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7392 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7393 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
7394 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
7398 /* Output a move from an fpa register to arm registers.
7399 OPERANDS[0] is the first registers of an arm register pair.
7400 OPERANDS[1] is an fpa register. */
7402 output_mov_double_arm_from_fpa (rtx
*operands
)
7404 int arm_reg0
= REGNO (operands
[0]);
7407 if (arm_reg0
== IP_REGNUM
)
7410 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
7411 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
7412 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
7413 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
7417 /* Output a move between double words.
7418 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
7419 or MEM<-REG and all MEMs must be offsettable addresses. */
7421 output_move_double (rtx
*operands
)
7423 enum rtx_code code0
= GET_CODE (operands
[0]);
7424 enum rtx_code code1
= GET_CODE (operands
[1]);
7429 int reg0
= REGNO (operands
[0]);
7431 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
7435 int reg1
= REGNO (operands
[1]);
7436 if (reg1
== IP_REGNUM
)
7439 /* Ensure the second source is not overwritten. */
7440 if (reg1
== reg0
+ (WORDS_BIG_ENDIAN
? -1 : 1))
7441 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands
);
7443 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands
);
7445 else if (code1
== CONST_VECTOR
)
7447 HOST_WIDE_INT hint
= 0;
7449 switch (GET_MODE (operands
[1]))
7452 otherops
[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands
[1], 1)));
7453 operands
[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands
[1], 0)));
7457 if (BYTES_BIG_ENDIAN
)
7459 hint
= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
7461 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
7465 hint
= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
7467 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
7470 otherops
[1] = GEN_INT (hint
);
7473 if (BYTES_BIG_ENDIAN
)
7475 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
7477 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
7481 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
7483 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
7486 operands
[1] = GEN_INT (hint
);
7490 if (BYTES_BIG_ENDIAN
)
7492 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 4));
7494 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 5));
7496 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 6));
7498 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 7));
7502 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 7));
7504 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 6));
7506 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 5));
7508 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 4));
7511 otherops
[1] = GEN_INT (hint
);
7514 if (BYTES_BIG_ENDIAN
)
7516 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
7518 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
7520 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
7522 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
7526 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 3));
7528 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 2));
7530 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 1));
7532 hint
|= INTVAL (CONST_VECTOR_ELT (operands
[1], 0));
7535 operands
[1] = GEN_INT (hint
);
7541 output_mov_immediate (operands
);
7542 output_mov_immediate (otherops
);
7544 else if (code1
== CONST_DOUBLE
)
7546 if (GET_MODE (operands
[1]) == DFmode
)
7551 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
7552 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
7553 otherops
[1] = GEN_INT (l
[1]);
7554 operands
[1] = GEN_INT (l
[0]);
7556 else if (GET_MODE (operands
[1]) != VOIDmode
)
7558 else if (WORDS_BIG_ENDIAN
)
7560 otherops
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
7561 operands
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
7565 otherops
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
7566 operands
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
7569 output_mov_immediate (operands
);
7570 output_mov_immediate (otherops
);
7572 else if (code1
== CONST_INT
)
7574 #if HOST_BITS_PER_WIDE_INT > 32
7575 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
7576 what the upper word is. */
7577 if (WORDS_BIG_ENDIAN
)
7579 otherops
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
7580 operands
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
7584 otherops
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
7585 operands
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
7588 /* Sign extend the intval into the high-order word. */
7589 if (WORDS_BIG_ENDIAN
)
7591 otherops
[1] = operands
[1];
7592 operands
[1] = (INTVAL (operands
[1]) < 0
7593 ? constm1_rtx
: const0_rtx
);
7596 otherops
[1] = INTVAL (operands
[1]) < 0 ? constm1_rtx
: const0_rtx
;
7598 output_mov_immediate (otherops
);
7599 output_mov_immediate (operands
);
7601 else if (code1
== MEM
)
7603 switch (GET_CODE (XEXP (operands
[1], 0)))
7606 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
7610 abort (); /* Should never happen now. */
7614 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
7618 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
7622 abort (); /* Should never happen now. */
7627 output_asm_insn ("adr%?\t%0, %1", operands
);
7628 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
7632 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
7633 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
7635 otherops
[0] = operands
[0];
7636 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
7637 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
7639 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
7641 if (GET_CODE (otherops
[2]) == CONST_INT
)
7643 switch ((int) INTVAL (otherops
[2]))
7646 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
7649 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
7652 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
7656 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
7657 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
7659 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
7662 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
7665 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
7667 return "ldm%?ia\t%0, %M0";
7671 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
7672 /* Take care of overlapping base/data reg. */
7673 if (reg_mentioned_p (operands
[0], operands
[1]))
7675 output_asm_insn ("ldr%?\t%0, %1", otherops
);
7676 output_asm_insn ("ldr%?\t%0, %1", operands
);
7680 output_asm_insn ("ldr%?\t%0, %1", operands
);
7681 output_asm_insn ("ldr%?\t%0, %1", otherops
);
7687 abort (); /* Constraints should prevent this. */
7689 else if (code0
== MEM
&& code1
== REG
)
7691 if (REGNO (operands
[1]) == IP_REGNUM
)
7694 switch (GET_CODE (XEXP (operands
[0], 0)))
7697 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
7701 abort (); /* Should never happen now. */
7705 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
7709 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
7713 abort (); /* Should never happen now. */
7717 if (GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == CONST_INT
)
7719 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
7722 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
7726 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
7730 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
7737 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
7738 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
7739 output_asm_insn ("str%?\t%1, %0", operands
);
7740 output_asm_insn ("str%?\t%1, %0", otherops
);
7744 /* Constraints should prevent this. */
7751 /* Output an arbitrary MOV reg, #n.
7752 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
7754 output_mov_immediate (rtx
*operands
)
7756 HOST_WIDE_INT n
= INTVAL (operands
[1]);
7758 /* Try to use one MOV. */
7759 if (const_ok_for_arm (n
))
7760 output_asm_insn ("mov%?\t%0, %1", operands
);
7762 /* Try to use one MVN. */
7763 else if (const_ok_for_arm (~n
))
7765 operands
[1] = GEN_INT (~n
);
7766 output_asm_insn ("mvn%?\t%0, %1", operands
);
7773 /* If all else fails, make it out of ORRs or BICs as appropriate. */
7774 for (i
= 0; i
< 32; i
++)
7778 if (n_ones
> 16) /* Shorter to use MVN with BIC in this case. */
7779 output_multi_immediate (operands
, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n
);
7781 output_multi_immediate (operands
, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n
);
7787 /* Output an ADD r, s, #n where n may be too big for one instruction.
7788 If adding zero to one register, output nothing. */
7790 output_add_immediate (rtx
*operands
)
7792 HOST_WIDE_INT n
= INTVAL (operands
[2]);
7794 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
7797 output_multi_immediate (operands
,
7798 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
7801 output_multi_immediate (operands
,
7802 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
7809 /* Output a multiple immediate operation.
7810 OPERANDS is the vector of operands referred to in the output patterns.
7811 INSTR1 is the output pattern to use for the first constant.
7812 INSTR2 is the output pattern to use for subsequent constants.
7813 IMMED_OP is the index of the constant slot in OPERANDS.
7814 N is the constant value. */
7816 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
7817 int immed_op
, HOST_WIDE_INT n
)
7819 #if HOST_BITS_PER_WIDE_INT > 32
7825 /* Quick and easy output. */
7826 operands
[immed_op
] = const0_rtx
;
7827 output_asm_insn (instr1
, operands
);
7832 const char * instr
= instr1
;
7834 /* Note that n is never zero here (which would give no output). */
7835 for (i
= 0; i
< 32; i
+= 2)
7839 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
7840 output_asm_insn (instr
, operands
);
7850 /* Return the appropriate ARM instruction for the operation code.
7851 The returned result should not be overwritten. OP is the rtx of the
7852 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
7855 arithmetic_instr (rtx op
, int shift_first_arg
)
7857 switch (GET_CODE (op
))
7863 return shift_first_arg
? "rsb" : "sub";
7879 /* Ensure valid constant shifts and return the appropriate shift mnemonic
7880 for the operation code. The returned result should not be overwritten.
7881 OP is the rtx code of the shift.
7882 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
7885 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
7888 enum rtx_code code
= GET_CODE (op
);
7890 if (GET_CODE (XEXP (op
, 1)) == REG
|| GET_CODE (XEXP (op
, 1)) == SUBREG
)
7892 else if (GET_CODE (XEXP (op
, 1)) == CONST_INT
)
7893 *amountp
= INTVAL (XEXP (op
, 1));
7916 /* We never have to worry about the amount being other than a
7917 power of 2, since this case can never be reloaded from a reg. */
7919 *amountp
= int_log2 (*amountp
);
7930 /* This is not 100% correct, but follows from the desire to merge
7931 multiplication by a power of 2 with the recognizer for a
7932 shift. >=32 is not a valid shift for "asl", so we must try and
7933 output a shift that produces the correct arithmetical result.
7934 Using lsr #32 is identical except for the fact that the carry bit
7935 is not set correctly if we set the flags; but we never use the
7936 carry bit from such an operation, so we can ignore that. */
7937 if (code
== ROTATERT
)
7938 /* Rotate is just modulo 32. */
7940 else if (*amountp
!= (*amountp
& 31))
7947 /* Shifts of 0 are no-ops. */
7955 /* Obtain the shift from the POWER of two. */
7957 static HOST_WIDE_INT
7958 int_log2 (HOST_WIDE_INT power
)
7960 HOST_WIDE_INT shift
= 0;
7962 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
7972 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
7973 /bin/as is horribly restrictive. */
7974 #define MAX_ASCII_LEN 51
7977 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
7982 fputs ("\t.ascii\t\"", stream
);
7984 for (i
= 0; i
< len
; i
++)
7988 if (len_so_far
>= MAX_ASCII_LEN
)
7990 fputs ("\"\n\t.ascii\t\"", stream
);
7997 fputs ("\\t", stream
);
8002 fputs ("\\f", stream
);
8007 fputs ("\\b", stream
);
8012 fputs ("\\r", stream
);
8016 case TARGET_NEWLINE
:
8017 fputs ("\\n", stream
);
8019 if ((c
>= ' ' && c
<= '~')
8021 /* This is a good place for a line break. */
8022 len_so_far
= MAX_ASCII_LEN
;
8029 putc ('\\', stream
);
8034 if (c
>= ' ' && c
<= '~')
8041 fprintf (stream
, "\\%03o", c
);
8048 fputs ("\"\n", stream
);
8051 /* Compute the register sabe mask for registers 0 through 12
8052 inclusive. This code is used by both arm_compute_save_reg_mask
8053 and arm_compute_initial_elimination_offset. */
8054 static unsigned long
8055 arm_compute_save_reg0_reg12_mask (void)
8057 unsigned long func_type
= arm_current_func_type ();
8058 unsigned int save_reg_mask
= 0;
8061 if (IS_INTERRUPT (func_type
))
8063 unsigned int max_reg
;
8064 /* Interrupt functions must not corrupt any registers,
8065 even call clobbered ones. If this is a leaf function
8066 we can just examine the registers used by the RTL, but
8067 otherwise we have to assume that whatever function is
8068 called might clobber anything, and so we have to save
8069 all the call-clobbered registers as well. */
8070 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
8071 /* FIQ handlers have registers r8 - r12 banked, so
8072 we only need to check r0 - r7, Normal ISRs only
8073 bank r14 and r15, so we must check up to r12.
8074 r13 is the stack pointer which is always preserved,
8075 so we do not need to consider it here. */
8080 for (reg
= 0; reg
<= max_reg
; reg
++)
8081 if (regs_ever_live
[reg
]
8082 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
8083 save_reg_mask
|= (1 << reg
);
8087 /* In the normal case we only need to save those registers
8088 which are call saved and which are used by this function. */
8089 for (reg
= 0; reg
<= 10; reg
++)
8090 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
8091 save_reg_mask
|= (1 << reg
);
8093 /* Handle the frame pointer as a special case. */
8094 if (! TARGET_APCS_FRAME
8095 && ! frame_pointer_needed
8096 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
8097 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
8098 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
8100 /* If we aren't loading the PIC register,
8101 don't stack it even though it may be live. */
8103 && ! TARGET_SINGLE_PIC_BASE
8104 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
8105 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
8108 return save_reg_mask
;
8111 /* Compute a bit mask of which registers need to be
8112 saved on the stack for the current function. */
8114 static unsigned long
8115 arm_compute_save_reg_mask (void)
8117 unsigned int save_reg_mask
= 0;
8118 unsigned long func_type
= arm_current_func_type ();
8120 if (IS_NAKED (func_type
))
8121 /* This should never really happen. */
8124 /* If we are creating a stack frame, then we must save the frame pointer,
8125 IP (which will hold the old stack pointer), LR and the PC. */
8126 if (frame_pointer_needed
)
8128 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
8133 /* Volatile functions do not return, so there
8134 is no need to save any other registers. */
8135 if (IS_VOLATILE (func_type
))
8136 return save_reg_mask
;
8138 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
8140 /* Decide if we need to save the link register.
8141 Interrupt routines have their own banked link register,
8142 so they never need to save it.
8143 Otherwise if we do not use the link register we do not need to save
8144 it. If we are pushing other registers onto the stack however, we
8145 can save an instruction in the epilogue by pushing the link register
8146 now and then popping it back into the PC. This incurs extra memory
8147 accesses though, so we only do it when optimizing for size, and only
8148 if we know that we will not need a fancy return sequence. */
8149 if (regs_ever_live
[LR_REGNUM
]
8152 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
))
8153 save_reg_mask
|= 1 << LR_REGNUM
;
8155 if (cfun
->machine
->lr_save_eliminated
)
8156 save_reg_mask
&= ~ (1 << LR_REGNUM
);
8158 if (TARGET_REALLY_IWMMXT
8159 && ((bit_count (save_reg_mask
)
8160 + ARM_NUM_INTS (current_function_pretend_args_size
)) % 2) != 0)
8164 /* The total number of registers that are going to be pushed
8165 onto the stack is odd. We need to ensure that the stack
8166 is 64-bit aligned before we start to save iWMMXt registers,
8167 and also before we start to create locals. (A local variable
8168 might be a double or long long which we will load/store using
8169 an iWMMXt instruction). Therefore we need to push another
8170 ARM register, so that the stack will be 64-bit aligned. We
8171 try to avoid using the arg registers (r0 -r3) as they might be
8172 used to pass values in a tail call. */
8173 for (reg
= 4; reg
<= 12; reg
++)
8174 if ((save_reg_mask
& (1 << reg
)) == 0)
8178 save_reg_mask
|= (1 << reg
);
8181 cfun
->machine
->sibcall_blocked
= 1;
8182 save_reg_mask
|= (1 << 3);
8186 return save_reg_mask
;
8189 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
8190 everything bar the final return instruction. */
8192 output_return_instruction (rtx operand
, int really_return
, int reverse
)
8194 char conditional
[10];
8197 unsigned long live_regs_mask
;
8198 unsigned long func_type
;
8200 func_type
= arm_current_func_type ();
8202 if (IS_NAKED (func_type
))
8205 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
8207 /* If this function was declared non-returning, and we have
8208 found a tail call, then we have to trust that the called
8209 function won't return. */
8214 /* Otherwise, trap an attempted return by aborting. */
8216 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
8218 assemble_external_libcall (ops
[1]);
8219 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
8225 if (current_function_calls_alloca
&& !really_return
)
8228 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
8230 return_used_this_function
= 1;
8232 live_regs_mask
= arm_compute_save_reg_mask ();
8236 const char * return_reg
;
8238 /* If we do not have any special requirements for function exit
8239 (eg interworking, or ISR) then we can load the return address
8240 directly into the PC. Otherwise we must load it into LR. */
8242 && ! TARGET_INTERWORK
)
8243 return_reg
= reg_names
[PC_REGNUM
];
8245 return_reg
= reg_names
[LR_REGNUM
];
8247 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
8248 /* There are two possible reasons for the IP register being saved.
8249 Either a stack frame was created, in which case IP contains the
8250 old stack pointer, or an ISR routine corrupted it. If this in an
8251 ISR routine then just restore IP, otherwise restore IP into SP. */
8252 if (! IS_INTERRUPT (func_type
))
8254 live_regs_mask
&= ~ (1 << IP_REGNUM
);
8255 live_regs_mask
|= (1 << SP_REGNUM
);
8258 /* On some ARM architectures it is faster to use LDR rather than
8259 LDM to load a single register. On other architectures, the
8260 cost is the same. In 26 bit mode, or for exception handlers,
8261 we have to use LDM to load the PC so that the CPSR is also
8263 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
8265 if (live_regs_mask
== (unsigned int)(1 << reg
))
8268 if (reg
<= LAST_ARM_REGNUM
8269 && (reg
!= LR_REGNUM
8271 || (TARGET_APCS_32
&& ! IS_INTERRUPT (func_type
))))
8273 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
8274 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
8281 /* Generate the load multiple instruction to restore the
8282 registers. Note we can get here, even if
8283 frame_pointer_needed is true, but only if sp already
8284 points to the base of the saved core registers. */
8285 if (live_regs_mask
& (1 << SP_REGNUM
))
8287 unsigned HOST_WIDE_INT stack_adjust
=
8288 arm_get_frame_size () + current_function_outgoing_args_size
;
8290 if (stack_adjust
!= 0 && stack_adjust
!= 4)
8293 if (stack_adjust
&& arm_arch5
)
8294 sprintf (instr
, "ldm%sib\t%%|sp, {", conditional
);
8297 /* If we can't use ldmib (SA110 bug), then try to pop r3
8300 live_regs_mask
|= 1 << 3;
8301 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
8305 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
8307 p
= instr
+ strlen (instr
);
8309 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
8310 if (live_regs_mask
& (1 << reg
))
8312 int l
= strlen (reg_names
[reg
]);
8318 memcpy (p
, ", ", 2);
8322 memcpy (p
, "%|", 2);
8323 memcpy (p
+ 2, reg_names
[reg
], l
);
8327 if (live_regs_mask
& (1 << LR_REGNUM
))
8329 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
8330 /* Decide if we need to add the ^ symbol to the end of the
8331 register list. This causes the saved condition codes
8332 register to be copied into the current condition codes
8333 register. We do the copy if we are conforming to the 32-bit
8334 ABI and this is an interrupt function, or if we are
8335 conforming to the 26-bit ABI. There is a special case for
8336 the 26-bit ABI however, which is if we are writing back the
8337 stack pointer but not loading the PC. In this case adding
8338 the ^ symbol would create a type 2 LDM instruction, where
8339 writeback is UNPREDICTABLE. We are safe in leaving the ^
8340 character off in this case however, since the actual return
8341 instruction will be a MOVS which will restore the CPSR. */
8342 if ((TARGET_APCS_32
&& IS_INTERRUPT (func_type
))
8343 || (! TARGET_APCS_32
&& really_return
))
8350 output_asm_insn (instr
, & operand
);
8352 /* See if we need to generate an extra instruction to
8353 perform the actual function return. */
8355 && func_type
!= ARM_FT_INTERWORKED
8356 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
8358 /* The return has already been handled
8359 by loading the LR into the PC. */
8366 switch ((int) ARM_FUNC_TYPE (func_type
))
8370 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
8373 case ARM_FT_INTERWORKED
:
8374 sprintf (instr
, "bx%s\t%%|lr", conditional
);
8377 case ARM_FT_EXCEPTION
:
8378 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
8382 /* ARMv5 implementations always provide BX, so interworking
8383 is the default unless APCS-26 is in use. */
8384 if ((insn_flags
& FL_ARCH5
) != 0 && TARGET_APCS_32
)
8385 sprintf (instr
, "bx%s\t%%|lr", conditional
);
8387 sprintf (instr
, "mov%s%s\t%%|pc, %%|lr",
8388 conditional
, TARGET_APCS_32
? "" : "s");
8392 output_asm_insn (instr
, & operand
);
8398 /* Write the function name into the code section, directly preceding
8399 the function prologue.
8401 Code will be output similar to this:
8403 .ascii "arm_poke_function_name", 0
8406 .word 0xff000000 + (t1 - t0)
8407 arm_poke_function_name
8409 stmfd sp!, {fp, ip, lr, pc}
8412 When performing a stack backtrace, code can inspect the value
8413 of 'pc' stored at 'fp' + 0. If the trace function then looks
8414 at location pc - 12 and the top 8 bits are set, then we know
8415 that there is a function name embedded immediately preceding this
8416 location and has length ((pc[-3]) & 0xff000000).
8418 We assume that pc is declared as a pointer to an unsigned long.
8420 It is of no benefit to output the function name if we are assembling
8421 a leaf function. These function types will not contain a stack
8422 backtrace structure, therefore it is not possible to determine the
8425 arm_poke_function_name (FILE *stream
, const char *name
)
8427 unsigned long alignlength
;
8428 unsigned long length
;
8431 length
= strlen (name
) + 1;
8432 alignlength
= ROUND_UP_WORD (length
);
8434 ASM_OUTPUT_ASCII (stream
, name
, length
);
8435 ASM_OUTPUT_ALIGN (stream
, 2);
8436 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
8437 assemble_aligned_integer (UNITS_PER_WORD
, x
);
8440 /* Place some comments into the assembler stream
8441 describing the current function. */
8443 arm_output_function_prologue (FILE *f
, HOST_WIDE_INT frame_size
)
8445 unsigned long func_type
;
8449 thumb_output_function_prologue (f
, frame_size
);
8454 if (arm_ccfsm_state
|| arm_target_insn
)
8457 func_type
= arm_current_func_type ();
8459 switch ((int) ARM_FUNC_TYPE (func_type
))
8464 case ARM_FT_INTERWORKED
:
8465 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
8467 case ARM_FT_EXCEPTION_HANDLER
:
8468 asm_fprintf (f
, "\t%@ C++ Exception Handler.\n");
8471 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
8474 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
8476 case ARM_FT_EXCEPTION
:
8477 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
8481 if (IS_NAKED (func_type
))
8482 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
8484 if (IS_VOLATILE (func_type
))
8485 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
8487 if (IS_NESTED (func_type
))
8488 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
8490 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %wd\n",
8491 current_function_args_size
,
8492 current_function_pretend_args_size
, frame_size
);
8494 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
8495 frame_pointer_needed
,
8496 cfun
->machine
->uses_anonymous_args
);
8498 if (cfun
->machine
->lr_save_eliminated
)
8499 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
8501 #ifdef AOF_ASSEMBLER
8503 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
8506 return_used_this_function
= 0;
8510 arm_output_epilogue (rtx sibling
)
8513 unsigned long saved_regs_mask
;
8514 unsigned long func_type
;
8515 /* Floats_offset is the offset from the "virtual" frame. In an APCS
8516 frame that is $fp + 4 for a non-variadic function. */
8517 int floats_offset
= 0;
8519 int frame_size
= arm_get_frame_size ();
8520 FILE * f
= asm_out_file
;
8521 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
8522 unsigned int lrm_count
= 0;
8523 int really_return
= (sibling
== NULL
);
8525 /* If we have already generated the return instruction
8526 then it is futile to generate anything else. */
8527 if (use_return_insn (FALSE
, sibling
) && return_used_this_function
)
8530 func_type
= arm_current_func_type ();
8532 if (IS_NAKED (func_type
))
8533 /* Naked functions don't have epilogues. */
8536 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
8540 /* A volatile function should never return. Call abort. */
8541 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
8542 assemble_external_libcall (op
);
8543 output_asm_insn ("bl\t%a0", &op
);
8548 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
8550 /* If we are throwing an exception, then we really must
8551 be doing a return, so we can't tail-call. */
8554 saved_regs_mask
= arm_compute_save_reg_mask ();
8557 lrm_count
= bit_count (saved_regs_mask
);
8559 /* XXX We should adjust floats_offset for any anonymous args, and then
8560 re-adjust vfp_offset below to compensate. */
8562 /* Compute how far away the floats will be. */
8563 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
8564 if (saved_regs_mask
& (1 << reg
))
8567 if (frame_pointer_needed
)
8571 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
8573 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
8574 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8576 floats_offset
+= 12;
8577 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
8578 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
8583 int start_reg
= LAST_ARM_FP_REGNUM
;
8585 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
8587 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8589 floats_offset
+= 12;
8591 /* We can't unstack more than four registers at once. */
8592 if (start_reg
- reg
== 3)
8594 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
8595 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
8596 start_reg
= reg
- 1;
8601 if (reg
!= start_reg
)
8602 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
8603 reg
+ 1, start_reg
- reg
,
8604 FP_REGNUM
, floats_offset
- vfp_offset
);
8605 start_reg
= reg
- 1;
8609 /* Just in case the last register checked also needs unstacking. */
8610 if (reg
!= start_reg
)
8611 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
8612 reg
+ 1, start_reg
- reg
,
8613 FP_REGNUM
, floats_offset
- vfp_offset
);
8618 /* The frame pointer is guaranteed to be non-double-word aligned.
8619 This is because it is set to (old_stack_pointer - 4) and the
8620 old_stack_pointer was double word aligned. Thus the offset to
8621 the iWMMXt registers to be loaded must also be non-double-word
8622 sized, so that the resultant address *is* double-word aligned.
8623 We can ignore floats_offset since that was already included in
8624 the live_regs_mask. */
8625 lrm_count
+= (lrm_count
% 2 ? 2 : 1);
8627 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
8628 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8630 asm_fprintf (f
, "\twldrd\t%r, [%r, #-%d]\n",
8631 reg
, FP_REGNUM
, lrm_count
* 4);
8636 /* saved_regs_mask should contain the IP, which at the time of stack
8637 frame generation actually contains the old stack pointer. So a
8638 quick way to unwind the stack is just pop the IP register directly
8639 into the stack pointer. */
8640 if ((saved_regs_mask
& (1 << IP_REGNUM
)) == 0)
8642 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
8643 saved_regs_mask
|= (1 << SP_REGNUM
);
8645 /* There are two registers left in saved_regs_mask - LR and PC. We
8646 only need to restore the LR register (the return address), but to
8647 save time we can load it directly into the PC, unless we need a
8648 special function exit sequence, or we are not really returning. */
8649 if (really_return
&& ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
)
8650 /* Delete the LR from the register mask, so that the LR on
8651 the stack is loaded into the PC in the register mask. */
8652 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
8654 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
8656 /* We must use SP as the base register, because SP is one of the
8657 registers being restored. If an interrupt or page fault
8658 happens in the ldm instruction, the SP might or might not
8659 have been restored. That would be bad, as then SP will no
8660 longer indicate the safe area of stack, and we can get stack
8661 corruption. Using SP as the base register means that it will
8662 be reset correctly to the original value, should an interrupt
8663 occur. If the stack pointer already points at the right
8664 place, then omit the subtraction. */
8665 if (((frame_size
+ current_function_outgoing_args_size
+ floats_offset
)
8666 != 4 * (1 + (int) bit_count (saved_regs_mask
)))
8667 || current_function_calls_alloca
)
8668 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n", SP_REGNUM
, FP_REGNUM
,
8669 4 * bit_count (saved_regs_mask
));
8670 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
8672 if (IS_INTERRUPT (func_type
))
8673 /* Interrupt handlers will have pushed the
8674 IP onto the stack, so restore it now. */
8675 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, 1 << IP_REGNUM
);
8679 /* Restore stack pointer if necessary. */
8680 if (frame_size
+ current_function_outgoing_args_size
!= 0)
8682 operands
[0] = operands
[1] = stack_pointer_rtx
;
8683 operands
[2] = GEN_INT (frame_size
8684 + current_function_outgoing_args_size
);
8685 output_add_immediate (operands
);
8688 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
8690 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
8691 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8692 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
8697 int start_reg
= FIRST_ARM_FP_REGNUM
;
8699 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
8701 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8703 if (reg
- start_reg
== 3)
8705 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
8706 start_reg
, SP_REGNUM
);
8707 start_reg
= reg
+ 1;
8712 if (reg
!= start_reg
)
8713 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
8714 start_reg
, reg
- start_reg
,
8717 start_reg
= reg
+ 1;
8721 /* Just in case the last register checked also needs unstacking. */
8722 if (reg
!= start_reg
)
8723 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
8724 start_reg
, reg
- start_reg
, SP_REGNUM
);
8728 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
8729 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8730 asm_fprintf (f
, "\twldrd\t%r, [%r, #+8]!\n", reg
, SP_REGNUM
);
8732 /* If we can, restore the LR into the PC. */
8733 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
8735 && current_function_pretend_args_size
== 0
8736 && saved_regs_mask
& (1 << LR_REGNUM
))
8738 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
8739 saved_regs_mask
|= (1 << PC_REGNUM
);
8742 /* Load the registers off the stack. If we only have one register
8743 to load use the LDR instruction - it is faster. */
8744 if (saved_regs_mask
== (1 << LR_REGNUM
))
8746 /* The exception handler ignores the LR, so we do
8747 not really need to load it off the stack. */
8749 asm_fprintf (f
, "\tadd\t%r, %r, #4\n", SP_REGNUM
, SP_REGNUM
);
8751 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
8753 else if (saved_regs_mask
)
8755 if (saved_regs_mask
& (1 << SP_REGNUM
))
8756 /* Note - write back to the stack register is not enabled
8757 (ie "ldmfd sp!..."). We know that the stack pointer is
8758 in the list of registers and if we add writeback the
8759 instruction becomes UNPREDICTABLE. */
8760 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
8762 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
8765 if (current_function_pretend_args_size
)
8767 /* Unwind the pre-pushed regs. */
8768 operands
[0] = operands
[1] = stack_pointer_rtx
;
8769 operands
[2] = GEN_INT (current_function_pretend_args_size
);
8770 output_add_immediate (operands
);
8775 || (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
8776 && current_function_pretend_args_size
== 0
8777 && saved_regs_mask
& (1 << PC_REGNUM
)))
8780 /* Generate the return instruction. */
8781 switch ((int) ARM_FUNC_TYPE (func_type
))
8783 case ARM_FT_EXCEPTION_HANDLER
:
8784 /* Even in 26-bit mode we do a mov (rather than a movs)
8785 because we don't have the PSR bits set in the address. */
8786 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, EXCEPTION_LR_REGNUM
);
8791 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
8794 case ARM_FT_EXCEPTION
:
8795 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
8798 case ARM_FT_INTERWORKED
:
8799 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
8803 if (frame_pointer_needed
)
8804 /* If we used the frame pointer then the return address
8805 will have been loaded off the stack directly into the
8806 PC, so there is no need to issue a MOV instruction
8809 else if (current_function_pretend_args_size
== 0
8810 && (saved_regs_mask
& (1 << LR_REGNUM
)))
8811 /* Similarly we may have been able to load LR into the PC
8812 even if we did not create a stack frame. */
8814 else if (TARGET_APCS_32
)
8815 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
8817 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
8825 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
8826 HOST_WIDE_INT frame_size
)
8830 /* ??? Probably not safe to set this here, since it assumes that a
8831 function will be emitted as assembly immediately after we generate
8832 RTL for it. This does not happen for inline functions. */
8833 return_used_this_function
= 0;
8837 /* We need to take into account any stack-frame rounding. */
8838 frame_size
= arm_get_frame_size ();
8840 if (use_return_insn (FALSE
, NULL
)
8841 && return_used_this_function
8842 && (frame_size
+ current_function_outgoing_args_size
) != 0
8843 && !frame_pointer_needed
)
8846 /* Reset the ARM-specific per-function variables. */
8847 after_arm_reorg
= 0;
8851 /* Generate and emit an insn that we will recognize as a push_multi.
8852 Unfortunately, since this insn does not reflect very well the actual
8853 semantics of the operation, we need to annotate the insn for the benefit
8854 of DWARF2 frame unwind information. */
8856 emit_multi_reg_push (int mask
)
8863 int dwarf_par_index
;
8866 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8867 if (mask
& (1 << i
))
8870 if (num_regs
== 0 || num_regs
> 16)
8873 /* We don't record the PC in the dwarf frame information. */
8874 num_dwarf_regs
= num_regs
;
8875 if (mask
& (1 << PC_REGNUM
))
8878 /* For the body of the insn we are going to generate an UNSPEC in
8879 parallel with several USEs. This allows the insn to be recognized
8880 by the push_multi pattern in the arm.md file. The insn looks
8881 something like this:
8884 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
8885 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
8886 (use (reg:SI 11 fp))
8887 (use (reg:SI 12 ip))
8888 (use (reg:SI 14 lr))
8889 (use (reg:SI 15 pc))
8892 For the frame note however, we try to be more explicit and actually
8893 show each register being stored into the stack frame, plus a (single)
8894 decrement of the stack pointer. We do it this way in order to be
8895 friendly to the stack unwinding code, which only wants to see a single
8896 stack decrement per instruction. The RTL we generate for the note looks
8897 something like this:
8900 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
8901 (set (mem:SI (reg:SI sp)) (reg:SI r4))
8902 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
8903 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
8904 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
8907 This sequence is used both by the code to support stack unwinding for
8908 exceptions handlers and the code to generate dwarf2 frame debugging. */
8910 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
8911 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
8912 dwarf_par_index
= 1;
8914 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
8916 if (mask
& (1 << i
))
8918 reg
= gen_rtx_REG (SImode
, i
);
8921 = gen_rtx_SET (VOIDmode
,
8922 gen_rtx_MEM (BLKmode
,
8923 gen_rtx_PRE_DEC (BLKmode
,
8924 stack_pointer_rtx
)),
8925 gen_rtx_UNSPEC (BLKmode
,
8931 tmp
= gen_rtx_SET (VOIDmode
,
8932 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
8934 RTX_FRAME_RELATED_P (tmp
) = 1;
8935 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
8943 for (j
= 1, i
++; j
< num_regs
; i
++)
8945 if (mask
& (1 << i
))
8947 reg
= gen_rtx_REG (SImode
, i
);
8949 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
8953 tmp
= gen_rtx_SET (VOIDmode
,
8954 gen_rtx_MEM (SImode
,
8955 plus_constant (stack_pointer_rtx
,
8958 RTX_FRAME_RELATED_P (tmp
) = 1;
8959 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
8966 par
= emit_insn (par
);
8968 tmp
= gen_rtx_SET (SImode
,
8970 gen_rtx_PLUS (SImode
,
8972 GEN_INT (-4 * num_regs
)));
8973 RTX_FRAME_RELATED_P (tmp
) = 1;
8974 XVECEXP (dwarf
, 0, 0) = tmp
;
8976 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8982 emit_sfm (int base_reg
, int count
)
8989 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8990 dwarf
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8992 reg
= gen_rtx_REG (XFmode
, base_reg
++);
8995 = gen_rtx_SET (VOIDmode
,
8996 gen_rtx_MEM (BLKmode
,
8997 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
8998 gen_rtx_UNSPEC (BLKmode
,
9002 = gen_rtx_SET (VOIDmode
,
9003 gen_rtx_MEM (XFmode
,
9004 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
9006 RTX_FRAME_RELATED_P (tmp
) = 1;
9007 XVECEXP (dwarf
, 0, count
- 1) = tmp
;
9009 for (i
= 1; i
< count
; i
++)
9011 reg
= gen_rtx_REG (XFmode
, base_reg
++);
9012 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
9014 tmp
= gen_rtx_SET (VOIDmode
,
9015 gen_rtx_MEM (XFmode
,
9016 gen_rtx_PRE_DEC (BLKmode
,
9017 stack_pointer_rtx
)),
9019 RTX_FRAME_RELATED_P (tmp
) = 1;
9020 XVECEXP (dwarf
, 0, count
- i
- 1) = tmp
;
9023 par
= emit_insn (par
);
9024 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
9029 /* Compute the distance from register FROM to register TO.
9030 These can be the arg pointer (26), the soft frame pointer (25),
9031 the stack pointer (13) or the hard frame pointer (11).
9032 Typical stack layout looks like this:
9034 old stack pointer -> | |
9037 | | saved arguments for
9038 | | vararg functions
9041 hard FP & arg pointer -> | | \
9049 soft frame pointer -> | | /
9059 current stack pointer -> | | /
9062 For a given function some or all of these stack components
9063 may not be needed, giving rise to the possibility of
9064 eliminating some of the registers.
9066 The values returned by this function must reflect the behavior
9067 of arm_expand_prologue() and arm_compute_save_reg_mask().
9069 The sign of the number returned reflects the direction of stack
9070 growth, so the values are positive for all eliminations except
9071 from the soft frame pointer to the hard frame pointer. */
9073 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
9075 unsigned int local_vars
= arm_get_frame_size ();
9076 unsigned int outgoing_args
= current_function_outgoing_args_size
;
9077 unsigned int stack_frame
;
9078 unsigned int call_saved_registers
;
9079 unsigned long func_type
;
9081 func_type
= arm_current_func_type ();
9083 /* Volatile functions never return, so there is
9084 no need to save call saved registers. */
9085 call_saved_registers
= 0;
9086 if (! IS_VOLATILE (func_type
))
9088 unsigned int reg_mask
;
9091 /* Make sure that we compute which registers will be saved
9092 on the stack using the same algorithm that is used by
9093 the prologue creation code. */
9094 reg_mask
= arm_compute_save_reg_mask ();
9096 /* Now count the number of bits set in save_reg_mask.
9097 If we have already counted the registers in the stack
9098 frame, do not count them again. Non call-saved registers
9099 might be saved in the call-save area of the stack, if
9100 doing so will preserve the stack's alignment. Hence we
9101 must count them here. For each set bit we need 4 bytes
9103 if (frame_pointer_needed
)
9105 call_saved_registers
+= 4 * bit_count (reg_mask
);
9107 /* If the hard floating point registers are going to be
9108 used then they must be saved on the stack as well.
9109 Each register occupies 12 bytes of stack space. */
9110 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
9111 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
9112 call_saved_registers
+= 12;
9114 if (TARGET_REALLY_IWMMXT
)
9115 /* Check for the call-saved iWMMXt registers. */
9116 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
9117 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
9118 call_saved_registers
+= 8;
9121 /* The stack frame contains 4 registers - the old frame pointer,
9122 the old stack pointer, the return address and PC of the start
9124 stack_frame
= frame_pointer_needed
? 16 : 0;
9126 /* OK, now we have enough information to compute the distances.
9127 There must be an entry in these switch tables for each pair
9128 of registers in ELIMINABLE_REGS, even if some of the entries
9129 seem to be redundant or useless. */
9132 case ARG_POINTER_REGNUM
:
9135 case THUMB_HARD_FRAME_POINTER_REGNUM
:
9138 case FRAME_POINTER_REGNUM
:
9139 /* This is the reverse of the soft frame pointer
9140 to hard frame pointer elimination below. */
9141 if (call_saved_registers
== 0 && stack_frame
== 0)
9143 return (call_saved_registers
+ stack_frame
- 4);
9145 case ARM_HARD_FRAME_POINTER_REGNUM
:
9146 /* If there is no stack frame then the hard
9147 frame pointer and the arg pointer coincide. */
9148 if (stack_frame
== 0 && call_saved_registers
!= 0)
9150 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
9151 return (frame_pointer_needed
9152 && current_function_needs_context
9153 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
9155 case STACK_POINTER_REGNUM
:
9156 /* If nothing has been pushed on the stack at all
9157 then this will return -4. This *is* correct! */
9158 return call_saved_registers
+ stack_frame
+ local_vars
+ outgoing_args
- 4;
9165 case FRAME_POINTER_REGNUM
:
9168 case THUMB_HARD_FRAME_POINTER_REGNUM
:
9171 case ARM_HARD_FRAME_POINTER_REGNUM
:
9172 /* The hard frame pointer points to the top entry in the
9173 stack frame. The soft frame pointer to the bottom entry
9174 in the stack frame. If there is no stack frame at all,
9175 then they are identical. */
9176 if (call_saved_registers
== 0 && stack_frame
== 0)
9178 return - (call_saved_registers
+ stack_frame
- 4);
9180 case STACK_POINTER_REGNUM
:
9181 return local_vars
+ outgoing_args
;
9189 /* You cannot eliminate from the stack pointer.
9190 In theory you could eliminate from the hard frame
9191 pointer to the stack pointer, but this will never
9192 happen, since if a stack frame is not needed the
9193 hard frame pointer will never be used. */
9198 /* Calculate the size of the stack frame, taking into account any
9199 padding that is required to ensure stack-alignment. */
9201 arm_get_frame_size (void)
9205 int base_size
= ROUND_UP_WORD (get_frame_size ());
9207 unsigned long func_type
= arm_current_func_type ();
9216 /* We need to know if we are a leaf function. Unfortunately, it
9217 is possible to be called after start_sequence has been called,
9218 which causes get_insns to return the insns for the sequence,
9219 not the function, which will cause leaf_function_p to return
9220 the incorrect result.
9222 To work around this, we cache the computed frame size. This
9223 works because we will only be calling RTL expanders that need
9224 to know about leaf functions once reload has completed, and the
9225 frame size cannot be changed after that time, so we can safely
9226 use the cached value. */
9228 if (reload_completed
)
9229 return cfun
->machine
->frame_size
;
9231 leaf
= leaf_function_p ();
9233 /* A leaf function does not need any stack alignment if it has nothing
9235 if (leaf
&& base_size
== 0)
9237 cfun
->machine
->frame_size
= 0;
9241 /* We know that SP will be word aligned on entry, and we must
9242 preserve that condition at any subroutine call. But those are
9243 the only constraints. */
9245 /* Space for variadic functions. */
9246 if (current_function_pretend_args_size
)
9247 entry_size
+= current_function_pretend_args_size
;
9249 /* Space for saved registers. */
9250 entry_size
+= bit_count (arm_compute_save_reg_mask ()) * 4;
9252 /* Space for saved FPA registers. */
9253 if (! IS_VOLATILE (func_type
))
9255 for (regno
= FIRST_ARM_FP_REGNUM
; regno
<= LAST_ARM_FP_REGNUM
; regno
++)
9256 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
9260 if (TARGET_REALLY_IWMMXT
)
9262 /* Check for the call-saved iWMMXt registers. */
9263 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
9264 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
9268 if ((entry_size
+ base_size
+ current_function_outgoing_args_size
) & 7)
9270 if ((entry_size
+ base_size
+ current_function_outgoing_args_size
) & 7)
9273 cfun
->machine
->frame_size
= base_size
;
9278 /* Generate the prologue instructions for entry into an ARM function. */
9280 arm_expand_prologue (void)
9286 unsigned long live_regs_mask
;
9287 unsigned long func_type
;
9289 int saved_pretend_args
= 0;
9290 unsigned int args_to_push
;
9292 func_type
= arm_current_func_type ();
9294 /* Naked functions don't have prologues. */
9295 if (IS_NAKED (func_type
))
9298 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
9299 args_to_push
= current_function_pretend_args_size
;
9301 /* Compute which register we will have to save onto the stack. */
9302 live_regs_mask
= arm_compute_save_reg_mask ();
9304 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
9306 if (frame_pointer_needed
)
9308 if (IS_INTERRUPT (func_type
))
9310 /* Interrupt functions must not corrupt any registers.
9311 Creating a frame pointer however, corrupts the IP
9312 register, so we must push it first. */
9313 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
9315 /* Do not set RTX_FRAME_RELATED_P on this insn.
9316 The dwarf stack unwinding code only wants to see one
9317 stack decrement per function, and this is not it. If
9318 this instruction is labeled as being part of the frame
9319 creation sequence then dwarf2out_frame_debug_expr will
9320 abort when it encounters the assignment of IP to FP
9321 later on, since the use of SP here establishes SP as
9322 the CFA register and not IP.
9324 Anyway this instruction is not really part of the stack
9325 frame creation although it is part of the prologue. */
9327 else if (IS_NESTED (func_type
))
9329 /* The Static chain register is the same as the IP register
9330 used as a scratch register during stack frame creation.
9331 To get around this need to find somewhere to store IP
9332 whilst the frame is being created. We try the following
9335 1. The last argument register.
9336 2. A slot on the stack above the frame. (This only
9337 works if the function is not a varargs function).
9338 3. Register r3, after pushing the argument registers
9341 Note - we only need to tell the dwarf2 backend about the SP
9342 adjustment in the second variant; the static chain register
9343 doesn't need to be unwound, as it doesn't contain a value
9344 inherited from the caller. */
9346 if (regs_ever_live
[3] == 0)
9348 insn
= gen_rtx_REG (SImode
, 3);
9349 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
9350 insn
= emit_insn (insn
);
9352 else if (args_to_push
== 0)
9355 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
9356 insn
= gen_rtx_MEM (SImode
, insn
);
9357 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
9358 insn
= emit_insn (insn
);
9362 /* Just tell the dwarf backend that we adjusted SP. */
9363 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
9364 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
9365 GEN_INT (-fp_offset
)));
9366 RTX_FRAME_RELATED_P (insn
) = 1;
9367 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
9368 dwarf
, REG_NOTES (insn
));
9372 /* Store the args on the stack. */
9373 if (cfun
->machine
->uses_anonymous_args
)
9374 insn
= emit_multi_reg_push
9375 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
9378 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9379 GEN_INT (- args_to_push
)));
9381 RTX_FRAME_RELATED_P (insn
) = 1;
9383 saved_pretend_args
= 1;
9384 fp_offset
= args_to_push
;
9387 /* Now reuse r3 to preserve IP. */
9388 insn
= gen_rtx_REG (SImode
, 3);
9389 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
9390 (void) emit_insn (insn
);
9396 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
9397 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
9400 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
9402 insn
= emit_insn (insn
);
9403 RTX_FRAME_RELATED_P (insn
) = 1;
9408 /* Push the argument registers, or reserve space for them. */
9409 if (cfun
->machine
->uses_anonymous_args
)
9410 insn
= emit_multi_reg_push
9411 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
9414 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9415 GEN_INT (- args_to_push
)));
9416 RTX_FRAME_RELATED_P (insn
) = 1;
9419 /* If this is an interrupt service routine, and the link register
9420 is going to be pushed, and we are not creating a stack frame,
9421 (which would involve an extra push of IP and a pop in the epilogue)
9422 subtracting four from LR now will mean that the function return
9423 can be done with a single instruction. */
9424 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
9425 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
9426 && ! frame_pointer_needed
)
9427 emit_insn (gen_rtx_SET (SImode
,
9428 gen_rtx_REG (SImode
, LR_REGNUM
),
9429 gen_rtx_PLUS (SImode
,
9430 gen_rtx_REG (SImode
, LR_REGNUM
),
9435 insn
= emit_multi_reg_push (live_regs_mask
);
9436 RTX_FRAME_RELATED_P (insn
) = 1;
9440 for (reg
= FIRST_IWMMXT_REGNUM
; reg
<= LAST_IWMMXT_REGNUM
; reg
++)
9441 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
9443 insn
= gen_rtx_PRE_DEC (V2SImode
, stack_pointer_rtx
);
9444 insn
= gen_rtx_MEM (V2SImode
, insn
);
9445 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
9446 gen_rtx_REG (V2SImode
, reg
)));
9447 RTX_FRAME_RELATED_P (insn
) = 1;
9450 if (! IS_VOLATILE (func_type
))
9452 /* Save any floating point call-saved registers used by this
9454 if (arm_fpu_arch
== FPUTYPE_FPA_EMU2
)
9456 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
9457 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9459 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
9460 insn
= gen_rtx_MEM (XFmode
, insn
);
9461 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
9462 gen_rtx_REG (XFmode
, reg
)));
9463 RTX_FRAME_RELATED_P (insn
) = 1;
9468 int start_reg
= LAST_ARM_FP_REGNUM
;
9470 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
9472 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
9474 if (start_reg
- reg
== 3)
9476 insn
= emit_sfm (reg
, 4);
9477 RTX_FRAME_RELATED_P (insn
) = 1;
9478 start_reg
= reg
- 1;
9483 if (start_reg
!= reg
)
9485 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
9486 RTX_FRAME_RELATED_P (insn
) = 1;
9488 start_reg
= reg
- 1;
9492 if (start_reg
!= reg
)
9494 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
9495 RTX_FRAME_RELATED_P (insn
) = 1;
9500 if (frame_pointer_needed
)
9502 /* Create the new frame pointer. */
9503 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
9504 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
9505 RTX_FRAME_RELATED_P (insn
) = 1;
9507 if (IS_NESTED (func_type
))
9509 /* Recover the static chain register. */
9510 if (regs_ever_live
[3] == 0
9511 || saved_pretend_args
)
9512 insn
= gen_rtx_REG (SImode
, 3);
9513 else /* if (current_function_pretend_args_size == 0) */
9515 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
,
9517 insn
= gen_rtx_MEM (SImode
, insn
);
9520 emit_insn (gen_rtx_SET (SImode
, ip_rtx
, insn
));
9521 /* Add a USE to stop propagate_one_insn() from barfing. */
9522 emit_insn (gen_prologue_use (ip_rtx
));
9526 amount
= GEN_INT (-(arm_get_frame_size ()
9527 + current_function_outgoing_args_size
));
9529 if (amount
!= const0_rtx
)
9531 /* This add can produce multiple insns for a large constant, so we
9532 need to get tricky. */
9533 rtx last
= get_last_insn ();
9534 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9538 last
= last
? NEXT_INSN (last
) : get_insns ();
9539 RTX_FRAME_RELATED_P (last
) = 1;
9541 while (last
!= insn
);
9543 /* If the frame pointer is needed, emit a special barrier that
9544 will prevent the scheduler from moving stores to the frame
9545 before the stack adjustment. */
9546 if (frame_pointer_needed
)
9547 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
9548 hard_frame_pointer_rtx
));
9551 /* If we are profiling, make sure no instructions are scheduled before
9552 the call to mcount. Similarly if the user has requested no
9553 scheduling in the prolog. */
9554 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
9555 emit_insn (gen_blockage ());
9557 /* If the link register is being kept alive, with the return address in it,
9558 then make sure that it does not get reused by the ce2 pass. */
9559 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
9561 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
9562 cfun
->machine
->lr_save_eliminated
= 1;
9566 /* If CODE is 'd', then the X is a condition operand and the instruction
9567 should only be executed if the condition is true.
9568 if CODE is 'D', then the X is a condition operand and the instruction
9569 should only be executed if the condition is false: however, if the mode
9570 of the comparison is CCFPEmode, then always execute the instruction -- we
9571 do this because in these circumstances !GE does not necessarily imply LT;
9572 in these cases the instruction pattern will take care to make sure that
9573 an instruction containing %d will follow, thereby undoing the effects of
9574 doing this instruction unconditionally.
9575 If CODE is 'N' then X is a floating point operand that must be negated
9577 If CODE is 'B' then output a bitwise inverted value of X (a const int).
9578 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
9580 arm_print_operand (FILE *stream
, rtx x
, int code
)
9585 fputs (ASM_COMMENT_START
, stream
);
9589 fputs (user_label_prefix
, stream
);
9593 fputs (REGISTER_PREFIX
, stream
);
9597 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
9599 if (TARGET_THUMB
|| current_insn_predicate
!= NULL
)
9602 fputs (arm_condition_codes
[arm_current_cc
], stream
);
9604 else if (current_insn_predicate
)
9606 enum arm_cond_code code
;
9611 code
= get_arm_condition_code (current_insn_predicate
);
9612 fputs (arm_condition_codes
[code
], stream
);
9619 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
9620 r
= REAL_VALUE_NEGATE (r
);
9621 fprintf (stream
, "%s", fp_const_from_val (&r
));
9626 if (GET_CODE (x
) == CONST_INT
)
9629 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
9630 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
9635 output_addr_const (stream
, x
);
9640 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
9643 /* Truncate Cirrus shift counts. */
9645 if (GET_CODE (x
) == CONST_INT
)
9647 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0x3f);
9650 arm_print_operand (stream
, x
, 0);
9654 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
9660 const char * shift
= shift_op (x
, &val
);
9664 fprintf (stream
, ", %s ", shift_op (x
, &val
));
9666 arm_print_operand (stream
, XEXP (x
, 1), 0);
9668 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
9673 /* An explanation of the 'Q', 'R' and 'H' register operands:
9675 In a pair of registers containing a DI or DF value the 'Q'
9676 operand returns the register number of the register containing
9677 the least significant part of the value. The 'R' operand returns
9678 the register number of the register containing the most
9679 significant part of the value.
9681 The 'H' operand returns the higher of the two register numbers.
9682 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
9683 same as the 'Q' operand, since the most significant part of the
9684 value is held in the lower number register. The reverse is true
9685 on systems where WORDS_BIG_ENDIAN is false.
9687 The purpose of these operands is to distinguish between cases
9688 where the endian-ness of the values is important (for example
9689 when they are added together), and cases where the endian-ness
9690 is irrelevant, but the order of register operations is important.
9691 For example when loading a value from memory into a register
9692 pair, the endian-ness does not matter. Provided that the value
9693 from the lower memory address is put into the lower numbered
9694 register, and the value from the higher address is put into the
9695 higher numbered register, the load will work regardless of whether
9696 the value being loaded is big-wordian or little-wordian. The
9697 order of the two register loads can matter however, if the address
9698 of the memory location is actually held in one of the registers
9699 being overwritten by the load. */
9701 if (REGNO (x
) > LAST_ARM_REGNUM
)
9703 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
9707 if (REGNO (x
) > LAST_ARM_REGNUM
)
9709 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
9713 if (REGNO (x
) > LAST_ARM_REGNUM
)
9715 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
9719 asm_fprintf (stream
, "%r",
9720 GET_CODE (XEXP (x
, 0)) == REG
9721 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
9725 asm_fprintf (stream
, "{%r-%r}",
9727 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
9731 /* CONST_TRUE_RTX means always -- that's the default. */
9732 if (x
== const_true_rtx
)
9735 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
9740 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
9742 if (x
== const_true_rtx
)
9745 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
9746 (get_arm_condition_code (x
))],
9750 /* Cirrus registers can be accessed in a variety of ways:
9751 single floating point (f)
9752 double floating point (d)
9754 64bit integer (dx). */
9755 case 'W': /* Cirrus register in F mode. */
9756 case 'X': /* Cirrus register in D mode. */
9757 case 'Y': /* Cirrus register in FX mode. */
9758 case 'Z': /* Cirrus register in DX mode. */
9759 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
9762 fprintf (stream
, "mv%s%s",
9765 : code
== 'Y' ? "fx" : "dx", reg_names
[REGNO (x
)] + 2);
9769 /* Print cirrus register in the mode specified by the register's mode. */
9772 int mode
= GET_MODE (x
);
9774 if (GET_CODE (x
) != REG
|| REGNO_REG_CLASS (REGNO (x
)) != CIRRUS_REGS
)
9777 fprintf (stream
, "mv%s%s",
9778 mode
== DFmode
? "d"
9779 : mode
== SImode
? "fx"
9780 : mode
== DImode
? "dx"
9781 : "f", reg_names
[REGNO (x
)] + 2);
9787 if (GET_CODE (x
) != REG
9788 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
9789 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
9790 /* Bad value for wCG register number. */
9793 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
9796 /* Print an iWMMXt control register name. */
9798 if (GET_CODE (x
) != CONST_INT
9800 || INTVAL (x
) >= 16)
9801 /* Bad value for wC register number. */
9805 static const char * wc_reg_names
[16] =
9807 "wCID", "wCon", "wCSSF", "wCASF",
9808 "wC4", "wC5", "wC6", "wC7",
9809 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
9810 "wC12", "wC13", "wC14", "wC15"
9813 fprintf (stream
, wc_reg_names
[INTVAL (x
)]);
9821 if (GET_CODE (x
) == REG
)
9822 asm_fprintf (stream
, "%r", REGNO (x
));
9823 else if (GET_CODE (x
) == MEM
)
9825 output_memory_reference_mode
= GET_MODE (x
);
9826 output_address (XEXP (x
, 0));
9828 else if (GET_CODE (x
) == CONST_DOUBLE
)
9829 fprintf (stream
, "#%s", fp_immediate_constant (x
));
9830 else if (GET_CODE (x
) == NEG
)
9831 abort (); /* This should never happen now. */
9834 fputc ('#', stream
);
9835 output_addr_const (stream
, x
);
9840 #ifndef AOF_ASSEMBLER
9841 /* Target hook for assembling integer objects. The ARM version needs to
9842 handle word-sized values specially. */
9844 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
9846 if (size
== UNITS_PER_WORD
&& aligned_p
)
9848 fputs ("\t.word\t", asm_out_file
);
9849 output_addr_const (asm_out_file
, x
);
9851 /* Mark symbols as position independent. We only do this in the
9852 .text segment, not in the .data segment. */
9853 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
9854 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
9856 if (GET_CODE (x
) == SYMBOL_REF
9857 && (CONSTANT_POOL_ADDRESS_P (x
)
9858 || SYMBOL_REF_LOCAL_P (x
)))
9859 fputs ("(GOTOFF)", asm_out_file
);
9860 else if (GET_CODE (x
) == LABEL_REF
)
9861 fputs ("(GOTOFF)", asm_out_file
);
9863 fputs ("(GOT)", asm_out_file
);
9865 fputc ('\n', asm_out_file
);
9869 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x
)))
9873 if (GET_CODE (x
) != CONST_VECTOR
)
9876 units
= CONST_VECTOR_NUNITS (x
);
9878 switch (GET_MODE (x
))
9880 case V2SImode
: size
= 4; break;
9881 case V4HImode
: size
= 2; break;
9882 case V8QImode
: size
= 1; break;
9887 for (i
= 0; i
< units
; i
++)
9891 elt
= CONST_VECTOR_ELT (x
, i
);
9893 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
9899 return default_assemble_integer (x
, size
, aligned_p
);
9903 /* A finite state machine takes care of noticing whether or not instructions
9904 can be conditionally executed, and thus decrease execution time and code
9905 size by deleting branch instructions. The fsm is controlled by
9906 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
9908 /* The state of the fsm controlling condition codes are:
9909 0: normal, do nothing special
9910 1: make ASM_OUTPUT_OPCODE not output this instruction
9911 2: make ASM_OUTPUT_OPCODE not output this instruction
9912 3: make instructions conditional
9913 4: make instructions conditional
9915 State transitions (state->state by whom under condition):
9916 0 -> 1 final_prescan_insn if the `target' is a label
9917 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
9918 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
9919 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
9920 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
9921 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
9922 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
9923 (the target insn is arm_target_insn).
9925 If the jump clobbers the conditions then we use states 2 and 4.
9927 A similar thing can be done with conditional return insns.
9929 XXX In case the `target' is an unconditional branch, this conditionalising
9930 of the instructions always reduces code size, but not always execution
9931 time. But then, I want to reduce the code size to somewhere near what
9932 /bin/cc produces. */
9934 /* Returns the index of the ARM condition code string in
9935 `arm_condition_codes'. COMPARISON should be an rtx like
9936 `(eq (...) (...))'. */
9937 static enum arm_cond_code
9938 get_arm_condition_code (rtx comparison
)
9940 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
9942 enum rtx_code comp_code
= GET_CODE (comparison
);
9944 if (GET_MODE_CLASS (mode
) != MODE_CC
)
9945 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
9946 XEXP (comparison
, 1));
9950 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
9951 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
9952 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
9953 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
9954 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
9955 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
9956 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
9957 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
9958 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
9959 case CC_DLTUmode
: code
= ARM_CC
;
9962 if (comp_code
!= EQ
&& comp_code
!= NE
)
9965 if (comp_code
== EQ
)
9966 return ARM_INVERSE_CONDITION_CODE (code
);
9972 case NE
: return ARM_NE
;
9973 case EQ
: return ARM_EQ
;
9974 case GE
: return ARM_PL
;
9975 case LT
: return ARM_MI
;
9982 case NE
: return ARM_NE
;
9983 case EQ
: return ARM_EQ
;
9990 case NE
: return ARM_MI
;
9991 case EQ
: return ARM_PL
;
9997 /* These encodings assume that AC=1 in the FPA system control
9998 byte. This allows us to handle all cases except UNEQ and
10002 case GE
: return ARM_GE
;
10003 case GT
: return ARM_GT
;
10004 case LE
: return ARM_LS
;
10005 case LT
: return ARM_MI
;
10006 case NE
: return ARM_NE
;
10007 case EQ
: return ARM_EQ
;
10008 case ORDERED
: return ARM_VC
;
10009 case UNORDERED
: return ARM_VS
;
10010 case UNLT
: return ARM_LT
;
10011 case UNLE
: return ARM_LE
;
10012 case UNGT
: return ARM_HI
;
10013 case UNGE
: return ARM_PL
;
10014 /* UNEQ and LTGT do not have a representation. */
10015 case UNEQ
: /* Fall through. */
10016 case LTGT
: /* Fall through. */
10023 case NE
: return ARM_NE
;
10024 case EQ
: return ARM_EQ
;
10025 case GE
: return ARM_LE
;
10026 case GT
: return ARM_LT
;
10027 case LE
: return ARM_GE
;
10028 case LT
: return ARM_GT
;
10029 case GEU
: return ARM_LS
;
10030 case GTU
: return ARM_CC
;
10031 case LEU
: return ARM_CS
;
10032 case LTU
: return ARM_HI
;
10039 case LTU
: return ARM_CS
;
10040 case GEU
: return ARM_CC
;
10047 case NE
: return ARM_NE
;
10048 case EQ
: return ARM_EQ
;
10049 case GE
: return ARM_GE
;
10050 case GT
: return ARM_GT
;
10051 case LE
: return ARM_LE
;
10052 case LT
: return ARM_LT
;
10053 case GEU
: return ARM_CS
;
10054 case GTU
: return ARM_HI
;
10055 case LEU
: return ARM_LS
;
10056 case LTU
: return ARM_CC
;
10067 arm_final_prescan_insn (rtx insn
)
10069 /* BODY will hold the body of INSN. */
10070 rtx body
= PATTERN (insn
);
10072 /* This will be 1 if trying to repeat the trick, and things need to be
10073 reversed if it appears to fail. */
10076 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
10077 taken are clobbered, even if the rtl suggests otherwise. It also
10078 means that we have to grub around within the jump expression to find
10079 out what the conditions are when the jump isn't taken. */
10080 int jump_clobbers
= 0;
10082 /* If we start with a return insn, we only succeed if we find another one. */
10083 int seeking_return
= 0;
10085 /* START_INSN will hold the insn from where we start looking. This is the
10086 first insn after the following code_label if REVERSE is true. */
10087 rtx start_insn
= insn
;
10089 /* If in state 4, check if the target branch is reached, in order to
10090 change back to state 0. */
10091 if (arm_ccfsm_state
== 4)
10093 if (insn
== arm_target_insn
)
10095 arm_target_insn
= NULL
;
10096 arm_ccfsm_state
= 0;
10101 /* If in state 3, it is possible to repeat the trick, if this insn is an
10102 unconditional branch to a label, and immediately following this branch
10103 is the previous target label which is only used once, and the label this
10104 branch jumps to is not too far off. */
10105 if (arm_ccfsm_state
== 3)
10107 if (simplejump_p (insn
))
10109 start_insn
= next_nonnote_insn (start_insn
);
10110 if (GET_CODE (start_insn
) == BARRIER
)
10112 /* XXX Isn't this always a barrier? */
10113 start_insn
= next_nonnote_insn (start_insn
);
10115 if (GET_CODE (start_insn
) == CODE_LABEL
10116 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
10117 && LABEL_NUSES (start_insn
) == 1)
10122 else if (GET_CODE (body
) == RETURN
)
10124 start_insn
= next_nonnote_insn (start_insn
);
10125 if (GET_CODE (start_insn
) == BARRIER
)
10126 start_insn
= next_nonnote_insn (start_insn
);
10127 if (GET_CODE (start_insn
) == CODE_LABEL
10128 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
10129 && LABEL_NUSES (start_insn
) == 1)
10132 seeking_return
= 1;
10141 if (arm_ccfsm_state
!= 0 && !reverse
)
10143 if (GET_CODE (insn
) != JUMP_INSN
)
10146 /* This jump might be paralleled with a clobber of the condition codes
10147 the jump should always come first */
10148 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
10149 body
= XVECEXP (body
, 0, 0);
10152 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
10153 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
10156 int fail
= FALSE
, succeed
= FALSE
;
10157 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
10158 int then_not_else
= TRUE
;
10159 rtx this_insn
= start_insn
, label
= 0;
10161 /* If the jump cannot be done with one instruction, we cannot
10162 conditionally execute the instruction in the inverse case. */
10163 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
10169 /* Register the insn jumped to. */
10172 if (!seeking_return
)
10173 label
= XEXP (SET_SRC (body
), 0);
10175 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
10176 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
10177 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
10179 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
10180 then_not_else
= FALSE
;
10182 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
10183 seeking_return
= 1;
10184 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
10186 seeking_return
= 1;
10187 then_not_else
= FALSE
;
10192 /* See how many insns this branch skips, and what kind of insns. If all
10193 insns are okay, and the label or unconditional branch to the same
10194 label is not too far away, succeed. */
10195 for (insns_skipped
= 0;
10196 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
10200 this_insn
= next_nonnote_insn (this_insn
);
10204 switch (GET_CODE (this_insn
))
10207 /* Succeed if it is the target label, otherwise fail since
10208 control falls in from somewhere else. */
10209 if (this_insn
== label
)
10213 arm_ccfsm_state
= 2;
10214 this_insn
= next_nonnote_insn (this_insn
);
10217 arm_ccfsm_state
= 1;
10225 /* Succeed if the following insn is the target label.
10227 If return insns are used then the last insn in a function
10228 will be a barrier. */
10229 this_insn
= next_nonnote_insn (this_insn
);
10230 if (this_insn
&& this_insn
== label
)
10234 arm_ccfsm_state
= 2;
10235 this_insn
= next_nonnote_insn (this_insn
);
10238 arm_ccfsm_state
= 1;
10246 /* If using 32-bit addresses the cc is not preserved over
10248 if (TARGET_APCS_32
)
10250 /* Succeed if the following insn is the target label,
10251 or if the following two insns are a barrier and
10252 the target label. */
10253 this_insn
= next_nonnote_insn (this_insn
);
10254 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
10255 this_insn
= next_nonnote_insn (this_insn
);
10257 if (this_insn
&& this_insn
== label
10258 && insns_skipped
< max_insns_skipped
)
10262 arm_ccfsm_state
= 2;
10263 this_insn
= next_nonnote_insn (this_insn
);
10266 arm_ccfsm_state
= 1;
10275 /* If this is an unconditional branch to the same label, succeed.
10276 If it is to another label, do nothing. If it is conditional,
10278 /* XXX Probably, the tests for SET and the PC are
10281 scanbody
= PATTERN (this_insn
);
10282 if (GET_CODE (scanbody
) == SET
10283 && GET_CODE (SET_DEST (scanbody
)) == PC
)
10285 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
10286 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
10288 arm_ccfsm_state
= 2;
10291 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
10294 /* Fail if a conditional return is undesirable (eg on a
10295 StrongARM), but still allow this if optimizing for size. */
10296 else if (GET_CODE (scanbody
) == RETURN
10297 && !use_return_insn (TRUE
, NULL
)
10300 else if (GET_CODE (scanbody
) == RETURN
10303 arm_ccfsm_state
= 2;
10306 else if (GET_CODE (scanbody
) == PARALLEL
)
10308 switch (get_attr_conds (this_insn
))
10318 fail
= TRUE
; /* Unrecognized jump (eg epilogue). */
10323 /* Instructions using or affecting the condition codes make it
10325 scanbody
= PATTERN (this_insn
);
10326 if (!(GET_CODE (scanbody
) == SET
10327 || GET_CODE (scanbody
) == PARALLEL
)
10328 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
10331 /* A conditional cirrus instruction must be followed by
10332 a non Cirrus instruction. However, since we
10333 conditionalize instructions in this function and by
10334 the time we get here we can't add instructions
10335 (nops), because shorten_branches() has already been
10336 called, we will disable conditionalizing Cirrus
10337 instructions to be safe. */
10338 if (GET_CODE (scanbody
) != USE
10339 && GET_CODE (scanbody
) != CLOBBER
10340 && get_attr_cirrus (this_insn
) != CIRRUS_NOT
)
10350 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
10351 arm_target_label
= CODE_LABEL_NUMBER (label
);
10352 else if (seeking_return
|| arm_ccfsm_state
== 2)
10354 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
10356 this_insn
= next_nonnote_insn (this_insn
);
10357 if (this_insn
&& (GET_CODE (this_insn
) == BARRIER
10358 || GET_CODE (this_insn
) == CODE_LABEL
))
10363 /* Oh, dear! we ran off the end.. give up */
10364 recog (PATTERN (insn
), insn
, NULL
);
10365 arm_ccfsm_state
= 0;
10366 arm_target_insn
= NULL
;
10369 arm_target_insn
= this_insn
;
10378 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
10380 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
10381 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
10382 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
10383 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
10387 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
10390 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
10394 if (reverse
|| then_not_else
)
10395 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
10398 /* Restore recog_data (getting the attributes of other insns can
10399 destroy this array, but final.c assumes that it remains intact
10400 across this call; since the insn has been recognized already we
10401 call recog direct). */
10402 recog (PATTERN (insn
), insn
, NULL
);
10406 /* Returns true if REGNO is a valid register
10407 for holding a quantity of tyoe MODE. */
10409 arm_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
10411 if (GET_MODE_CLASS (mode
) == MODE_CC
)
10412 return regno
== CC_REGNUM
;
10415 /* For the Thumb we only allow values bigger than SImode in
10416 registers 0 - 6, so that there is always a second low
10417 register available to hold the upper part of the value.
10418 We probably we ought to ensure that the register is the
10419 start of an even numbered register pair. */
10420 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
10422 if (IS_CIRRUS_REGNUM (regno
))
10423 /* We have outlawed SI values in Cirrus registers because they
10424 reside in the lower 32 bits, but SF values reside in the
10425 upper 32 bits. This causes gcc all sorts of grief. We can't
10426 even split the registers into pairs because Cirrus SI values
10427 get sign extended to 64bits-- aldyh. */
10428 return (GET_MODE_CLASS (mode
) == MODE_FLOAT
) || (mode
== DImode
);
10430 if (IS_IWMMXT_GR_REGNUM (regno
))
10431 return mode
== SImode
;
10433 if (IS_IWMMXT_REGNUM (regno
))
10434 return VALID_IWMMXT_REG_MODE (mode
);
10436 if (regno
<= LAST_ARM_REGNUM
)
10437 /* We allow any value to be stored in the general registers. */
10440 if ( regno
== FRAME_POINTER_REGNUM
10441 || regno
== ARG_POINTER_REGNUM
)
10442 /* We only allow integers in the fake hard registers. */
10443 return GET_MODE_CLASS (mode
) == MODE_INT
;
10445 /* The only registers left are the FPA registers
10446 which we only allow to hold FP values. */
10447 return GET_MODE_CLASS (mode
) == MODE_FLOAT
10448 && regno
>= FIRST_ARM_FP_REGNUM
10449 && regno
<= LAST_ARM_FP_REGNUM
;
10453 arm_regno_class (int regno
)
10457 if (regno
== STACK_POINTER_REGNUM
)
10459 if (regno
== CC_REGNUM
)
10466 if ( regno
<= LAST_ARM_REGNUM
10467 || regno
== FRAME_POINTER_REGNUM
10468 || regno
== ARG_POINTER_REGNUM
)
10469 return GENERAL_REGS
;
10471 if (regno
== CC_REGNUM
)
10474 if (IS_CIRRUS_REGNUM (regno
))
10475 return CIRRUS_REGS
;
10477 if (IS_IWMMXT_REGNUM (regno
))
10478 return IWMMXT_REGS
;
10480 if (IS_IWMMXT_GR_REGNUM (regno
))
10481 return IWMMXT_GR_REGS
;
10486 /* Handle a special case when computing the offset
10487 of an argument from the frame pointer. */
10489 arm_debugger_arg_offset (int value
, rtx addr
)
10493 /* We are only interested if dbxout_parms() failed to compute the offset. */
10497 /* We can only cope with the case where the address is held in a register. */
10498 if (GET_CODE (addr
) != REG
)
10501 /* If we are using the frame pointer to point at the argument, then
10502 an offset of 0 is correct. */
10503 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
10506 /* If we are using the stack pointer to point at the
10507 argument, then an offset of 0 is correct. */
10508 if ((TARGET_THUMB
|| !frame_pointer_needed
)
10509 && REGNO (addr
) == SP_REGNUM
)
10512 /* Oh dear. The argument is pointed to by a register rather
10513 than being held in a register, or being stored at a known
10514 offset from the frame pointer. Since GDB only understands
10515 those two kinds of argument we must translate the address
10516 held in the register into an offset from the frame pointer.
10517 We do this by searching through the insns for the function
10518 looking to see where this register gets its value. If the
10519 register is initialized from the frame pointer plus an offset
10520 then we are in luck and we can continue, otherwise we give up.
10522 This code is exercised by producing debugging information
10523 for a function with arguments like this:
10525 double func (double a, double b, int c, double d) {return d;}
10527 Without this code the stab for parameter 'd' will be set to
10528 an offset of 0 from the frame pointer, rather than 8. */
10530 /* The if() statement says:
10532 If the insn is a normal instruction
10533 and if the insn is setting the value in a register
10534 and if the register being set is the register holding the address of the argument
10535 and if the address is computing by an addition
10536 that involves adding to a register
10537 which is the frame pointer
10542 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10544 if ( GET_CODE (insn
) == INSN
10545 && GET_CODE (PATTERN (insn
)) == SET
10546 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
10547 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
10548 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
10549 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
10550 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
10553 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
10562 warning ("unable to compute real location of stacked parameter");
10563 value
= 8; /* XXX magic hack */
10569 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
10572 if ((MASK) & insn_flags) \
10573 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
10577 struct builtin_description
10579 const unsigned int mask
;
10580 const enum insn_code icode
;
10581 const char * const name
;
10582 const enum arm_builtins code
;
10583 const enum rtx_code comparison
;
10584 const unsigned int flag
;
10587 static const struct builtin_description bdesc_2arg
[] =
10589 #define IWMMXT_BUILTIN(code, string, builtin) \
10590 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
10591 ARM_BUILTIN_##builtin, 0, 0 },
10593 IWMMXT_BUILTIN (addv8qi3
, "waddb", WADDB
)
10594 IWMMXT_BUILTIN (addv4hi3
, "waddh", WADDH
)
10595 IWMMXT_BUILTIN (addv2si3
, "waddw", WADDW
)
10596 IWMMXT_BUILTIN (subv8qi3
, "wsubb", WSUBB
)
10597 IWMMXT_BUILTIN (subv4hi3
, "wsubh", WSUBH
)
10598 IWMMXT_BUILTIN (subv2si3
, "wsubw", WSUBW
)
10599 IWMMXT_BUILTIN (ssaddv8qi3
, "waddbss", WADDSSB
)
10600 IWMMXT_BUILTIN (ssaddv4hi3
, "waddhss", WADDSSH
)
10601 IWMMXT_BUILTIN (ssaddv2si3
, "waddwss", WADDSSW
)
10602 IWMMXT_BUILTIN (sssubv8qi3
, "wsubbss", WSUBSSB
)
10603 IWMMXT_BUILTIN (sssubv4hi3
, "wsubhss", WSUBSSH
)
10604 IWMMXT_BUILTIN (sssubv2si3
, "wsubwss", WSUBSSW
)
10605 IWMMXT_BUILTIN (usaddv8qi3
, "waddbus", WADDUSB
)
10606 IWMMXT_BUILTIN (usaddv4hi3
, "waddhus", WADDUSH
)
10607 IWMMXT_BUILTIN (usaddv2si3
, "waddwus", WADDUSW
)
10608 IWMMXT_BUILTIN (ussubv8qi3
, "wsubbus", WSUBUSB
)
10609 IWMMXT_BUILTIN (ussubv4hi3
, "wsubhus", WSUBUSH
)
10610 IWMMXT_BUILTIN (ussubv2si3
, "wsubwus", WSUBUSW
)
10611 IWMMXT_BUILTIN (mulv4hi3
, "wmulul", WMULUL
)
10612 IWMMXT_BUILTIN (smulv4hi3_highpart
, "wmulsh", WMULSH
)
10613 IWMMXT_BUILTIN (umulv4hi3_highpart
, "wmuluh", WMULUH
)
10614 IWMMXT_BUILTIN (eqv8qi3
, "wcmpeqb", WCMPEQB
)
10615 IWMMXT_BUILTIN (eqv4hi3
, "wcmpeqh", WCMPEQH
)
10616 IWMMXT_BUILTIN (eqv2si3
, "wcmpeqw", WCMPEQW
)
10617 IWMMXT_BUILTIN (gtuv8qi3
, "wcmpgtub", WCMPGTUB
)
10618 IWMMXT_BUILTIN (gtuv4hi3
, "wcmpgtuh", WCMPGTUH
)
10619 IWMMXT_BUILTIN (gtuv2si3
, "wcmpgtuw", WCMPGTUW
)
10620 IWMMXT_BUILTIN (gtv8qi3
, "wcmpgtsb", WCMPGTSB
)
10621 IWMMXT_BUILTIN (gtv4hi3
, "wcmpgtsh", WCMPGTSH
)
10622 IWMMXT_BUILTIN (gtv2si3
, "wcmpgtsw", WCMPGTSW
)
10623 IWMMXT_BUILTIN (umaxv8qi3
, "wmaxub", WMAXUB
)
10624 IWMMXT_BUILTIN (smaxv8qi3
, "wmaxsb", WMAXSB
)
10625 IWMMXT_BUILTIN (umaxv4hi3
, "wmaxuh", WMAXUH
)
10626 IWMMXT_BUILTIN (smaxv4hi3
, "wmaxsh", WMAXSH
)
10627 IWMMXT_BUILTIN (umaxv2si3
, "wmaxuw", WMAXUW
)
10628 IWMMXT_BUILTIN (smaxv2si3
, "wmaxsw", WMAXSW
)
10629 IWMMXT_BUILTIN (uminv8qi3
, "wminub", WMINUB
)
10630 IWMMXT_BUILTIN (sminv8qi3
, "wminsb", WMINSB
)
10631 IWMMXT_BUILTIN (uminv4hi3
, "wminuh", WMINUH
)
10632 IWMMXT_BUILTIN (sminv4hi3
, "wminsh", WMINSH
)
10633 IWMMXT_BUILTIN (uminv2si3
, "wminuw", WMINUW
)
10634 IWMMXT_BUILTIN (sminv2si3
, "wminsw", WMINSW
)
10635 IWMMXT_BUILTIN (iwmmxt_anddi3
, "wand", WAND
)
10636 IWMMXT_BUILTIN (iwmmxt_nanddi3
, "wandn", WANDN
)
10637 IWMMXT_BUILTIN (iwmmxt_iordi3
, "wor", WOR
)
10638 IWMMXT_BUILTIN (iwmmxt_xordi3
, "wxor", WXOR
)
10639 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3
, "wavg2b", WAVG2B
)
10640 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3
, "wavg2h", WAVG2H
)
10641 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3
, "wavg2br", WAVG2BR
)
10642 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3
, "wavg2hr", WAVG2HR
)
10643 IWMMXT_BUILTIN (iwmmxt_wunpckilb
, "wunpckilb", WUNPCKILB
)
10644 IWMMXT_BUILTIN (iwmmxt_wunpckilh
, "wunpckilh", WUNPCKILH
)
10645 IWMMXT_BUILTIN (iwmmxt_wunpckilw
, "wunpckilw", WUNPCKILW
)
10646 IWMMXT_BUILTIN (iwmmxt_wunpckihb
, "wunpckihb", WUNPCKIHB
)
10647 IWMMXT_BUILTIN (iwmmxt_wunpckihh
, "wunpckihh", WUNPCKIHH
)
10648 IWMMXT_BUILTIN (iwmmxt_wunpckihw
, "wunpckihw", WUNPCKIHW
)
10649 IWMMXT_BUILTIN (iwmmxt_wmadds
, "wmadds", WMADDS
)
10650 IWMMXT_BUILTIN (iwmmxt_wmaddu
, "wmaddu", WMADDU
)
10652 #define IWMMXT_BUILTIN2(code, builtin) \
10653 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
10655 IWMMXT_BUILTIN2 (iwmmxt_wpackhss
, WPACKHSS
)
10656 IWMMXT_BUILTIN2 (iwmmxt_wpackwss
, WPACKWSS
)
10657 IWMMXT_BUILTIN2 (iwmmxt_wpackdss
, WPACKDSS
)
10658 IWMMXT_BUILTIN2 (iwmmxt_wpackhus
, WPACKHUS
)
10659 IWMMXT_BUILTIN2 (iwmmxt_wpackwus
, WPACKWUS
)
10660 IWMMXT_BUILTIN2 (iwmmxt_wpackdus
, WPACKDUS
)
10661 IWMMXT_BUILTIN2 (ashlv4hi3_di
, WSLLH
)
10662 IWMMXT_BUILTIN2 (ashlv4hi3
, WSLLHI
)
10663 IWMMXT_BUILTIN2 (ashlv2si3_di
, WSLLW
)
10664 IWMMXT_BUILTIN2 (ashlv2si3
, WSLLWI
)
10665 IWMMXT_BUILTIN2 (ashldi3_di
, WSLLD
)
10666 IWMMXT_BUILTIN2 (ashldi3_iwmmxt
, WSLLDI
)
10667 IWMMXT_BUILTIN2 (lshrv4hi3_di
, WSRLH
)
10668 IWMMXT_BUILTIN2 (lshrv4hi3
, WSRLHI
)
10669 IWMMXT_BUILTIN2 (lshrv2si3_di
, WSRLW
)
10670 IWMMXT_BUILTIN2 (lshrv2si3
, WSRLWI
)
10671 IWMMXT_BUILTIN2 (lshrdi3_di
, WSRLD
)
10672 IWMMXT_BUILTIN2 (lshrdi3
, WSRLDI
)
10673 IWMMXT_BUILTIN2 (ashrv4hi3_di
, WSRAH
)
10674 IWMMXT_BUILTIN2 (ashrv4hi3
, WSRAHI
)
10675 IWMMXT_BUILTIN2 (ashrv2si3_di
, WSRAW
)
10676 IWMMXT_BUILTIN2 (ashrv2si3
, WSRAWI
)
10677 IWMMXT_BUILTIN2 (ashrdi3_di
, WSRAD
)
10678 IWMMXT_BUILTIN2 (ashrdi3
, WSRADI
)
10679 IWMMXT_BUILTIN2 (rorv4hi3_di
, WRORH
)
10680 IWMMXT_BUILTIN2 (rorv4hi3
, WRORHI
)
10681 IWMMXT_BUILTIN2 (rorv2si3_di
, WRORW
)
10682 IWMMXT_BUILTIN2 (rorv2si3
, WRORWI
)
10683 IWMMXT_BUILTIN2 (rordi3_di
, WRORD
)
10684 IWMMXT_BUILTIN2 (rordi3
, WRORDI
)
10685 IWMMXT_BUILTIN2 (iwmmxt_wmacuz
, WMACUZ
)
10686 IWMMXT_BUILTIN2 (iwmmxt_wmacsz
, WMACSZ
)
10689 static const struct builtin_description bdesc_1arg
[] =
10691 IWMMXT_BUILTIN (iwmmxt_tmovmskb
, "tmovmskb", TMOVMSKB
)
10692 IWMMXT_BUILTIN (iwmmxt_tmovmskh
, "tmovmskh", TMOVMSKH
)
10693 IWMMXT_BUILTIN (iwmmxt_tmovmskw
, "tmovmskw", TMOVMSKW
)
10694 IWMMXT_BUILTIN (iwmmxt_waccb
, "waccb", WACCB
)
10695 IWMMXT_BUILTIN (iwmmxt_wacch
, "wacch", WACCH
)
10696 IWMMXT_BUILTIN (iwmmxt_waccw
, "waccw", WACCW
)
10697 IWMMXT_BUILTIN (iwmmxt_wunpckehub
, "wunpckehub", WUNPCKEHUB
)
10698 IWMMXT_BUILTIN (iwmmxt_wunpckehuh
, "wunpckehuh", WUNPCKEHUH
)
10699 IWMMXT_BUILTIN (iwmmxt_wunpckehuw
, "wunpckehuw", WUNPCKEHUW
)
10700 IWMMXT_BUILTIN (iwmmxt_wunpckehsb
, "wunpckehsb", WUNPCKEHSB
)
10701 IWMMXT_BUILTIN (iwmmxt_wunpckehsh
, "wunpckehsh", WUNPCKEHSH
)
10702 IWMMXT_BUILTIN (iwmmxt_wunpckehsw
, "wunpckehsw", WUNPCKEHSW
)
10703 IWMMXT_BUILTIN (iwmmxt_wunpckelub
, "wunpckelub", WUNPCKELUB
)
10704 IWMMXT_BUILTIN (iwmmxt_wunpckeluh
, "wunpckeluh", WUNPCKELUH
)
10705 IWMMXT_BUILTIN (iwmmxt_wunpckeluw
, "wunpckeluw", WUNPCKELUW
)
10706 IWMMXT_BUILTIN (iwmmxt_wunpckelsb
, "wunpckelsb", WUNPCKELSB
)
10707 IWMMXT_BUILTIN (iwmmxt_wunpckelsh
, "wunpckelsh", WUNPCKELSH
)
10708 IWMMXT_BUILTIN (iwmmxt_wunpckelsw
, "wunpckelsw", WUNPCKELSW
)
10711 /* Set up all the iWMMXt builtins. This is
10712 not called if TARGET_IWMMXT is zero. */
10715 arm_init_iwmmxt_builtins (void)
10717 const struct builtin_description
* d
;
10719 tree endlink
= void_list_node
;
10722 = build_function_type (integer_type_node
,
10723 tree_cons (NULL_TREE
, integer_type_node
, endlink
));
10724 tree v8qi_ftype_v8qi_v8qi_int
10725 = build_function_type (V8QI_type_node
,
10726 tree_cons (NULL_TREE
, V8QI_type_node
,
10727 tree_cons (NULL_TREE
, V8QI_type_node
,
10728 tree_cons (NULL_TREE
,
10731 tree v4hi_ftype_v4hi_int
10732 = build_function_type (V4HI_type_node
,
10733 tree_cons (NULL_TREE
, V4HI_type_node
,
10734 tree_cons (NULL_TREE
, integer_type_node
,
10736 tree v2si_ftype_v2si_int
10737 = build_function_type (V2SI_type_node
,
10738 tree_cons (NULL_TREE
, V2SI_type_node
,
10739 tree_cons (NULL_TREE
, integer_type_node
,
10741 tree v2si_ftype_di_di
10742 = build_function_type (V2SI_type_node
,
10743 tree_cons (NULL_TREE
, long_long_integer_type_node
,
10744 tree_cons (NULL_TREE
, long_long_integer_type_node
,
10746 tree di_ftype_di_int
10747 = build_function_type (long_long_integer_type_node
,
10748 tree_cons (NULL_TREE
, long_long_integer_type_node
,
10749 tree_cons (NULL_TREE
, integer_type_node
,
10751 tree di_ftype_di_int_int
10752 = build_function_type (long_long_integer_type_node
,
10753 tree_cons (NULL_TREE
, long_long_integer_type_node
,
10754 tree_cons (NULL_TREE
, integer_type_node
,
10755 tree_cons (NULL_TREE
,
10758 tree int_ftype_v8qi
10759 = build_function_type (integer_type_node
,
10760 tree_cons (NULL_TREE
, V8QI_type_node
,
10762 tree int_ftype_v4hi
10763 = build_function_type (integer_type_node
,
10764 tree_cons (NULL_TREE
, V4HI_type_node
,
10766 tree int_ftype_v2si
10767 = build_function_type (integer_type_node
,
10768 tree_cons (NULL_TREE
, V2SI_type_node
,
10770 tree int_ftype_v8qi_int
10771 = build_function_type (integer_type_node
,
10772 tree_cons (NULL_TREE
, V8QI_type_node
,
10773 tree_cons (NULL_TREE
, integer_type_node
,
10775 tree int_ftype_v4hi_int
10776 = build_function_type (integer_type_node
,
10777 tree_cons (NULL_TREE
, V4HI_type_node
,
10778 tree_cons (NULL_TREE
, integer_type_node
,
10780 tree int_ftype_v2si_int
10781 = build_function_type (integer_type_node
,
10782 tree_cons (NULL_TREE
, V2SI_type_node
,
10783 tree_cons (NULL_TREE
, integer_type_node
,
10785 tree v8qi_ftype_v8qi_int_int
10786 = build_function_type (V8QI_type_node
,
10787 tree_cons (NULL_TREE
, V8QI_type_node
,
10788 tree_cons (NULL_TREE
, integer_type_node
,
10789 tree_cons (NULL_TREE
,
10792 tree v4hi_ftype_v4hi_int_int
10793 = build_function_type (V4HI_type_node
,
10794 tree_cons (NULL_TREE
, V4HI_type_node
,
10795 tree_cons (NULL_TREE
, integer_type_node
,
10796 tree_cons (NULL_TREE
,
10799 tree v2si_ftype_v2si_int_int
10800 = build_function_type (V2SI_type_node
,
10801 tree_cons (NULL_TREE
, V2SI_type_node
,
10802 tree_cons (NULL_TREE
, integer_type_node
,
10803 tree_cons (NULL_TREE
,
10806 /* Miscellaneous. */
10807 tree v8qi_ftype_v4hi_v4hi
10808 = build_function_type (V8QI_type_node
,
10809 tree_cons (NULL_TREE
, V4HI_type_node
,
10810 tree_cons (NULL_TREE
, V4HI_type_node
,
10812 tree v4hi_ftype_v2si_v2si
10813 = build_function_type (V4HI_type_node
,
10814 tree_cons (NULL_TREE
, V2SI_type_node
,
10815 tree_cons (NULL_TREE
, V2SI_type_node
,
10817 tree v2si_ftype_v4hi_v4hi
10818 = build_function_type (V2SI_type_node
,
10819 tree_cons (NULL_TREE
, V4HI_type_node
,
10820 tree_cons (NULL_TREE
, V4HI_type_node
,
10822 tree v2si_ftype_v8qi_v8qi
10823 = build_function_type (V2SI_type_node
,
10824 tree_cons (NULL_TREE
, V8QI_type_node
,
10825 tree_cons (NULL_TREE
, V8QI_type_node
,
10827 tree v4hi_ftype_v4hi_di
10828 = build_function_type (V4HI_type_node
,
10829 tree_cons (NULL_TREE
, V4HI_type_node
,
10830 tree_cons (NULL_TREE
,
10831 long_long_integer_type_node
,
10833 tree v2si_ftype_v2si_di
10834 = build_function_type (V2SI_type_node
,
10835 tree_cons (NULL_TREE
, V2SI_type_node
,
10836 tree_cons (NULL_TREE
,
10837 long_long_integer_type_node
,
10839 tree void_ftype_int_int
10840 = build_function_type (void_type_node
,
10841 tree_cons (NULL_TREE
, integer_type_node
,
10842 tree_cons (NULL_TREE
, integer_type_node
,
10845 = build_function_type (long_long_unsigned_type_node
, endlink
);
10847 = build_function_type (long_long_integer_type_node
,
10848 tree_cons (NULL_TREE
, V8QI_type_node
,
10851 = build_function_type (long_long_integer_type_node
,
10852 tree_cons (NULL_TREE
, V4HI_type_node
,
10855 = build_function_type (long_long_integer_type_node
,
10856 tree_cons (NULL_TREE
, V2SI_type_node
,
10858 tree v2si_ftype_v4hi
10859 = build_function_type (V2SI_type_node
,
10860 tree_cons (NULL_TREE
, V4HI_type_node
,
10862 tree v4hi_ftype_v8qi
10863 = build_function_type (V4HI_type_node
,
10864 tree_cons (NULL_TREE
, V8QI_type_node
,
10867 tree di_ftype_di_v4hi_v4hi
10868 = build_function_type (long_long_unsigned_type_node
,
10869 tree_cons (NULL_TREE
,
10870 long_long_unsigned_type_node
,
10871 tree_cons (NULL_TREE
, V4HI_type_node
,
10872 tree_cons (NULL_TREE
,
10876 tree di_ftype_v4hi_v4hi
10877 = build_function_type (long_long_unsigned_type_node
,
10878 tree_cons (NULL_TREE
, V4HI_type_node
,
10879 tree_cons (NULL_TREE
, V4HI_type_node
,
10882 /* Normal vector binops. */
10883 tree v8qi_ftype_v8qi_v8qi
10884 = build_function_type (V8QI_type_node
,
10885 tree_cons (NULL_TREE
, V8QI_type_node
,
10886 tree_cons (NULL_TREE
, V8QI_type_node
,
10888 tree v4hi_ftype_v4hi_v4hi
10889 = build_function_type (V4HI_type_node
,
10890 tree_cons (NULL_TREE
, V4HI_type_node
,
10891 tree_cons (NULL_TREE
, V4HI_type_node
,
10893 tree v2si_ftype_v2si_v2si
10894 = build_function_type (V2SI_type_node
,
10895 tree_cons (NULL_TREE
, V2SI_type_node
,
10896 tree_cons (NULL_TREE
, V2SI_type_node
,
10898 tree di_ftype_di_di
10899 = build_function_type (long_long_unsigned_type_node
,
10900 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
10901 tree_cons (NULL_TREE
,
10902 long_long_unsigned_type_node
,
10905 /* Add all builtins that are more or less simple operations on two
10907 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
10909 /* Use one of the operands; the target can have a different mode for
10910 mask-generating compares. */
10911 enum machine_mode mode
;
10917 mode
= insn_data
[d
->icode
].operand
[1].mode
;
10922 type
= v8qi_ftype_v8qi_v8qi
;
10925 type
= v4hi_ftype_v4hi_v4hi
;
10928 type
= v2si_ftype_v2si_v2si
;
10931 type
= di_ftype_di_di
;
10938 def_mbuiltin (d
->mask
, d
->name
, type
, d
->code
);
10941 /* Add the remaining MMX insns with somewhat more complicated types. */
10942 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wzero", di_ftype_void
, ARM_BUILTIN_WZERO
);
10943 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_setwcx", void_ftype_int_int
, ARM_BUILTIN_SETWCX
);
10944 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_getwcx", int_ftype_int
, ARM_BUILTIN_GETWCX
);
10946 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSLLH
);
10947 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSLLW
);
10948 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslld", di_ftype_di_di
, ARM_BUILTIN_WSLLD
);
10949 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSLLHI
);
10950 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsllwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSLLWI
);
10951 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wslldi", di_ftype_di_int
, ARM_BUILTIN_WSLLDI
);
10953 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRLH
);
10954 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRLW
);
10955 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrld", di_ftype_di_di
, ARM_BUILTIN_WSRLD
);
10956 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRLHI
);
10957 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRLWI
);
10958 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrldi", di_ftype_di_int
, ARM_BUILTIN_WSRLDI
);
10960 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WSRAH
);
10961 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsraw", v2si_ftype_v2si_di
, ARM_BUILTIN_WSRAW
);
10962 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrad", di_ftype_di_di
, ARM_BUILTIN_WSRAD
);
10963 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSRAHI
);
10964 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsrawi", v2si_ftype_v2si_int
, ARM_BUILTIN_WSRAWI
);
10965 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsradi", di_ftype_di_int
, ARM_BUILTIN_WSRADI
);
10967 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di
, ARM_BUILTIN_WRORH
);
10968 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorw", v2si_ftype_v2si_di
, ARM_BUILTIN_WRORW
);
10969 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrord", di_ftype_di_di
, ARM_BUILTIN_WRORD
);
10970 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WRORHI
);
10971 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrorwi", v2si_ftype_v2si_int
, ARM_BUILTIN_WRORWI
);
10972 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wrordi", di_ftype_di_int
, ARM_BUILTIN_WRORDI
);
10974 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int
, ARM_BUILTIN_WSHUFH
);
10976 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADB
);
10977 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADH
);
10978 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi
, ARM_BUILTIN_WSADBZ
);
10979 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi
, ARM_BUILTIN_WSADHZ
);
10981 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsb", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMSB
);
10982 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMSH
);
10983 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmsw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMSW
);
10984 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmub", int_ftype_v8qi_int
, ARM_BUILTIN_TEXTRMUB
);
10985 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuh", int_ftype_v4hi_int
, ARM_BUILTIN_TEXTRMUH
);
10986 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_textrmuw", int_ftype_v2si_int
, ARM_BUILTIN_TEXTRMUW
);
10987 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int
, ARM_BUILTIN_TINSRB
);
10988 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int
, ARM_BUILTIN_TINSRH
);
10989 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int
, ARM_BUILTIN_TINSRW
);
10991 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccb", di_ftype_v8qi
, ARM_BUILTIN_WACCB
);
10992 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wacch", di_ftype_v4hi
, ARM_BUILTIN_WACCH
);
10993 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_waccw", di_ftype_v2si
, ARM_BUILTIN_WACCW
);
10995 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskb", int_ftype_v8qi
, ARM_BUILTIN_TMOVMSKB
);
10996 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskh", int_ftype_v4hi
, ARM_BUILTIN_TMOVMSKH
);
10997 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmovmskw", int_ftype_v2si
, ARM_BUILTIN_TMOVMSKW
);
10999 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHSS
);
11000 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi
, ARM_BUILTIN_WPACKHUS
);
11001 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWUS
);
11002 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si
, ARM_BUILTIN_WPACKWSS
);
11003 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdus", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDUS
);
11004 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wpackdss", v2si_ftype_di_di
, ARM_BUILTIN_WPACKDSS
);
11006 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHUB
);
11007 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHUH
);
11008 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehuw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHUW
);
11009 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKEHSB
);
11010 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKEHSH
);
11011 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckehsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKEHSW
);
11012 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELUB
);
11013 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELUH
);
11014 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckeluw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELUW
);
11015 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi
, ARM_BUILTIN_WUNPCKELSB
);
11016 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi
, ARM_BUILTIN_WUNPCKELSH
);
11017 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wunpckelsw", di_ftype_v2si
, ARM_BUILTIN_WUNPCKELSW
);
11019 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACS
);
11020 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACSZ
);
11021 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi
, ARM_BUILTIN_WMACU
);
11022 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi
, ARM_BUILTIN_WMACUZ
);
11024 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int
, ARM_BUILTIN_WALIGN
);
11025 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmia", di_ftype_di_int_int
, ARM_BUILTIN_TMIA
);
11026 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiaph", di_ftype_di_int_int
, ARM_BUILTIN_TMIAPH
);
11027 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabb", di_ftype_di_int_int
, ARM_BUILTIN_TMIABB
);
11028 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiabt", di_ftype_di_int_int
, ARM_BUILTIN_TMIABT
);
11029 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatb", di_ftype_di_int_int
, ARM_BUILTIN_TMIATB
);
11030 def_mbuiltin (FL_IWMMXT
, "__builtin_arm_tmiatt", di_ftype_di_int_int
, ARM_BUILTIN_TMIATT
);
11034 arm_init_builtins (void)
11036 if (TARGET_REALLY_IWMMXT
)
11037 arm_init_iwmmxt_builtins ();
11040 /* Errors in the source file can cause expand_expr to return const0_rtx
11041 where we expect a vector. To avoid crashing, use one of the vector
11042 clear instructions. */
11045 safe_vector_operand (rtx x
, enum machine_mode mode
)
11047 if (x
!= const0_rtx
)
11049 x
= gen_reg_rtx (mode
);
11051 emit_insn (gen_iwmmxt_clrdi (mode
== DImode
? x
11052 : gen_rtx_SUBREG (DImode
, x
, 0)));
11056 /* Subroutine of arm_expand_builtin to take care of binop insns. */
11059 arm_expand_binop_builtin (enum insn_code icode
,
11060 tree arglist
, rtx target
)
11063 tree arg0
= TREE_VALUE (arglist
);
11064 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11065 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11066 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11067 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11068 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11069 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11071 if (VECTOR_MODE_P (mode0
))
11072 op0
= safe_vector_operand (op0
, mode0
);
11073 if (VECTOR_MODE_P (mode1
))
11074 op1
= safe_vector_operand (op1
, mode1
);
11077 || GET_MODE (target
) != tmode
11078 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11079 target
= gen_reg_rtx (tmode
);
11081 /* In case the insn wants input operands in modes different from
11082 the result, abort. */
11083 if (GET_MODE (op0
) != mode0
|| GET_MODE (op1
) != mode1
)
11086 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11087 op0
= copy_to_mode_reg (mode0
, op0
);
11088 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11089 op1
= copy_to_mode_reg (mode1
, op1
);
11091 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11098 /* Subroutine of arm_expand_builtin to take care of unop insns. */
11101 arm_expand_unop_builtin (enum insn_code icode
,
11102 tree arglist
, rtx target
, int do_load
)
11105 tree arg0
= TREE_VALUE (arglist
);
11106 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11107 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11108 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11111 || GET_MODE (target
) != tmode
11112 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11113 target
= gen_reg_rtx (tmode
);
11115 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
11118 if (VECTOR_MODE_P (mode0
))
11119 op0
= safe_vector_operand (op0
, mode0
);
11121 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11122 op0
= copy_to_mode_reg (mode0
, op0
);
11125 pat
= GEN_FCN (icode
) (target
, op0
);
11132 /* Expand an expression EXP that calls a built-in function,
11133 with result going to TARGET if that's convenient
11134 (and in mode MODE if that's convenient).
11135 SUBTARGET may be used as the target for computing one of EXP's operands.
11136 IGNORE is nonzero if the value is to be ignored. */
11139 arm_expand_builtin (tree exp
,
11141 rtx subtarget ATTRIBUTE_UNUSED
,
11142 enum machine_mode mode ATTRIBUTE_UNUSED
,
11143 int ignore ATTRIBUTE_UNUSED
)
11145 const struct builtin_description
* d
;
11146 enum insn_code icode
;
11147 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
11148 tree arglist
= TREE_OPERAND (exp
, 1);
11156 int fcode
= DECL_FUNCTION_CODE (fndecl
);
11158 enum machine_mode tmode
;
11159 enum machine_mode mode0
;
11160 enum machine_mode mode1
;
11161 enum machine_mode mode2
;
11165 case ARM_BUILTIN_TEXTRMSB
:
11166 case ARM_BUILTIN_TEXTRMUB
:
11167 case ARM_BUILTIN_TEXTRMSH
:
11168 case ARM_BUILTIN_TEXTRMUH
:
11169 case ARM_BUILTIN_TEXTRMSW
:
11170 case ARM_BUILTIN_TEXTRMUW
:
11171 icode
= (fcode
== ARM_BUILTIN_TEXTRMSB
? CODE_FOR_iwmmxt_textrmsb
11172 : fcode
== ARM_BUILTIN_TEXTRMUB
? CODE_FOR_iwmmxt_textrmub
11173 : fcode
== ARM_BUILTIN_TEXTRMSH
? CODE_FOR_iwmmxt_textrmsh
11174 : fcode
== ARM_BUILTIN_TEXTRMUH
? CODE_FOR_iwmmxt_textrmuh
11175 : CODE_FOR_iwmmxt_textrmw
);
11177 arg0
= TREE_VALUE (arglist
);
11178 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11179 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11180 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11181 tmode
= insn_data
[icode
].operand
[0].mode
;
11182 mode0
= insn_data
[icode
].operand
[1].mode
;
11183 mode1
= insn_data
[icode
].operand
[2].mode
;
11185 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11186 op0
= copy_to_mode_reg (mode0
, op0
);
11187 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11189 /* @@@ better error message */
11190 error ("selector must be an immediate");
11191 return gen_reg_rtx (tmode
);
11194 || GET_MODE (target
) != tmode
11195 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11196 target
= gen_reg_rtx (tmode
);
11197 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11203 case ARM_BUILTIN_TINSRB
:
11204 case ARM_BUILTIN_TINSRH
:
11205 case ARM_BUILTIN_TINSRW
:
11206 icode
= (fcode
== ARM_BUILTIN_TINSRB
? CODE_FOR_iwmmxt_tinsrb
11207 : fcode
== ARM_BUILTIN_TINSRH
? CODE_FOR_iwmmxt_tinsrh
11208 : CODE_FOR_iwmmxt_tinsrw
);
11209 arg0
= TREE_VALUE (arglist
);
11210 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11211 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
11212 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11213 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11214 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
11215 tmode
= insn_data
[icode
].operand
[0].mode
;
11216 mode0
= insn_data
[icode
].operand
[1].mode
;
11217 mode1
= insn_data
[icode
].operand
[2].mode
;
11218 mode2
= insn_data
[icode
].operand
[3].mode
;
11220 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11221 op0
= copy_to_mode_reg (mode0
, op0
);
11222 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11223 op1
= copy_to_mode_reg (mode1
, op1
);
11224 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
11226 /* @@@ better error message */
11227 error ("selector must be an immediate");
11231 || GET_MODE (target
) != tmode
11232 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11233 target
= gen_reg_rtx (tmode
);
11234 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
11240 case ARM_BUILTIN_SETWCX
:
11241 arg0
= TREE_VALUE (arglist
);
11242 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11243 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11244 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11245 emit_insn (gen_iwmmxt_tmcr (op0
, op1
));
11248 case ARM_BUILTIN_GETWCX
:
11249 arg0
= TREE_VALUE (arglist
);
11250 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11251 target
= gen_reg_rtx (SImode
);
11252 emit_insn (gen_iwmmxt_tmrc (target
, op0
));
11255 case ARM_BUILTIN_WSHUFH
:
11256 icode
= CODE_FOR_iwmmxt_wshufh
;
11257 arg0
= TREE_VALUE (arglist
);
11258 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11259 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11260 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11261 tmode
= insn_data
[icode
].operand
[0].mode
;
11262 mode1
= insn_data
[icode
].operand
[1].mode
;
11263 mode2
= insn_data
[icode
].operand
[2].mode
;
11265 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
11266 op0
= copy_to_mode_reg (mode1
, op0
);
11267 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
11269 /* @@@ better error message */
11270 error ("mask must be an immediate");
11274 || GET_MODE (target
) != tmode
11275 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11276 target
= gen_reg_rtx (tmode
);
11277 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11283 case ARM_BUILTIN_WSADB
:
11284 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb
, arglist
, target
);
11285 case ARM_BUILTIN_WSADH
:
11286 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh
, arglist
, target
);
11287 case ARM_BUILTIN_WSADBZ
:
11288 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz
, arglist
, target
);
11289 case ARM_BUILTIN_WSADHZ
:
11290 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz
, arglist
, target
);
11292 /* Several three-argument builtins. */
11293 case ARM_BUILTIN_WMACS
:
11294 case ARM_BUILTIN_WMACU
:
11295 case ARM_BUILTIN_WALIGN
:
11296 case ARM_BUILTIN_TMIA
:
11297 case ARM_BUILTIN_TMIAPH
:
11298 case ARM_BUILTIN_TMIATT
:
11299 case ARM_BUILTIN_TMIATB
:
11300 case ARM_BUILTIN_TMIABT
:
11301 case ARM_BUILTIN_TMIABB
:
11302 icode
= (fcode
== ARM_BUILTIN_WMACS
? CODE_FOR_iwmmxt_wmacs
11303 : fcode
== ARM_BUILTIN_WMACU
? CODE_FOR_iwmmxt_wmacu
11304 : fcode
== ARM_BUILTIN_TMIA
? CODE_FOR_iwmmxt_tmia
11305 : fcode
== ARM_BUILTIN_TMIAPH
? CODE_FOR_iwmmxt_tmiaph
11306 : fcode
== ARM_BUILTIN_TMIABB
? CODE_FOR_iwmmxt_tmiabb
11307 : fcode
== ARM_BUILTIN_TMIABT
? CODE_FOR_iwmmxt_tmiabt
11308 : fcode
== ARM_BUILTIN_TMIATB
? CODE_FOR_iwmmxt_tmiatb
11309 : fcode
== ARM_BUILTIN_TMIATT
? CODE_FOR_iwmmxt_tmiatt
11310 : CODE_FOR_iwmmxt_walign
);
11311 arg0
= TREE_VALUE (arglist
);
11312 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11313 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
11314 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11315 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11316 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
11317 tmode
= insn_data
[icode
].operand
[0].mode
;
11318 mode0
= insn_data
[icode
].operand
[1].mode
;
11319 mode1
= insn_data
[icode
].operand
[2].mode
;
11320 mode2
= insn_data
[icode
].operand
[3].mode
;
11322 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11323 op0
= copy_to_mode_reg (mode0
, op0
);
11324 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11325 op1
= copy_to_mode_reg (mode1
, op1
);
11326 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
11327 op2
= copy_to_mode_reg (mode2
, op2
);
11329 || GET_MODE (target
) != tmode
11330 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11331 target
= gen_reg_rtx (tmode
);
11332 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
11338 case ARM_BUILTIN_WZERO
:
11339 target
= gen_reg_rtx (DImode
);
11340 emit_insn (gen_iwmmxt_clrdi (target
));
11347 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
11348 if (d
->code
== (const enum arm_builtins
) fcode
)
11349 return arm_expand_binop_builtin (d
->icode
, arglist
, target
);
11351 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
11352 if (d
->code
== (const enum arm_builtins
) fcode
)
11353 return arm_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
11355 /* @@@ Should really do something sensible here. */
11359 /* Recursively search through all of the blocks in a function
11360 checking to see if any of the variables created in that
11361 function match the RTX called 'orig'. If they do then
11362 replace them with the RTX called 'new'. */
11364 replace_symbols_in_block (tree block
, rtx orig
, rtx
new)
11366 for (; block
; block
= BLOCK_CHAIN (block
))
11370 if (!TREE_USED (block
))
11373 for (sym
= BLOCK_VARS (block
); sym
; sym
= TREE_CHAIN (sym
))
11375 if ( (DECL_NAME (sym
) == 0 && TREE_CODE (sym
) != TYPE_DECL
)
11376 || DECL_IGNORED_P (sym
)
11377 || TREE_CODE (sym
) != VAR_DECL
11378 || DECL_EXTERNAL (sym
)
11379 || !rtx_equal_p (DECL_RTL (sym
), orig
)
11383 SET_DECL_RTL (sym
, new);
11386 replace_symbols_in_block (BLOCK_SUBBLOCKS (block
), orig
, new);
11390 /* Return the number (counting from 0) of
11391 the least significant set bit in MASK. */
11394 number_of_first_bit_set (int mask
)
11399 (mask
& (1 << bit
)) == 0;
11406 /* Generate code to return from a thumb function.
11407 If 'reg_containing_return_addr' is -1, then the return address is
11408 actually on the stack, at the stack pointer. */
11410 thumb_exit (FILE *f
, int reg_containing_return_addr
, rtx eh_ofs
)
11412 unsigned regs_available_for_popping
;
11413 unsigned regs_to_pop
;
11415 unsigned available
;
11419 int restore_a4
= FALSE
;
11421 /* Compute the registers we need to pop. */
11425 /* There is an assumption here, that if eh_ofs is not NULL, the
11426 normal return address will have been pushed. */
11427 if (reg_containing_return_addr
== -1 || eh_ofs
)
11429 /* When we are generating a return for __builtin_eh_return,
11430 reg_containing_return_addr must specify the return regno. */
11431 if (eh_ofs
&& reg_containing_return_addr
== -1)
11434 regs_to_pop
|= 1 << LR_REGNUM
;
11438 if (TARGET_BACKTRACE
)
11440 /* Restore the (ARM) frame pointer and stack pointer. */
11441 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
11445 /* If there is nothing to pop then just emit the BX instruction and
11447 if (pops_needed
== 0)
11450 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
11452 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
11455 /* Otherwise if we are not supporting interworking and we have not created
11456 a backtrace structure and the function was not entered in ARM mode then
11457 just pop the return address straight into the PC. */
11458 else if (!TARGET_INTERWORK
11459 && !TARGET_BACKTRACE
11460 && !is_called_in_ARM_mode (current_function_decl
))
11464 asm_fprintf (f
, "\tadd\t%r, #4\n", SP_REGNUM
);
11465 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
11466 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
11469 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
11474 /* Find out how many of the (return) argument registers we can corrupt. */
11475 regs_available_for_popping
= 0;
11477 /* If returning via __builtin_eh_return, the bottom three registers
11478 all contain information needed for the return. */
11484 /* If we can deduce the registers used from the function's
11485 return value. This is more reliable that examining
11486 regs_ever_live[] because that will be set if the register is
11487 ever used in the function, not just if the register is used
11488 to hold a return value. */
11490 if (current_function_return_rtx
!= 0)
11491 mode
= GET_MODE (current_function_return_rtx
);
11494 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
11496 size
= GET_MODE_SIZE (mode
);
11500 /* In a void function we can use any argument register.
11501 In a function that returns a structure on the stack
11502 we can use the second and third argument registers. */
11503 if (mode
== VOIDmode
)
11504 regs_available_for_popping
=
11505 (1 << ARG_REGISTER (1))
11506 | (1 << ARG_REGISTER (2))
11507 | (1 << ARG_REGISTER (3));
11509 regs_available_for_popping
=
11510 (1 << ARG_REGISTER (2))
11511 | (1 << ARG_REGISTER (3));
11513 else if (size
<= 4)
11514 regs_available_for_popping
=
11515 (1 << ARG_REGISTER (2))
11516 | (1 << ARG_REGISTER (3));
11517 else if (size
<= 8)
11518 regs_available_for_popping
=
11519 (1 << ARG_REGISTER (3));
11522 /* Match registers to be popped with registers into which we pop them. */
11523 for (available
= regs_available_for_popping
,
11524 required
= regs_to_pop
;
11525 required
!= 0 && available
!= 0;
11526 available
&= ~(available
& - available
),
11527 required
&= ~(required
& - required
))
11530 /* If we have any popping registers left over, remove them. */
11532 regs_available_for_popping
&= ~available
;
11534 /* Otherwise if we need another popping register we can use
11535 the fourth argument register. */
11536 else if (pops_needed
)
11538 /* If we have not found any free argument registers and
11539 reg a4 contains the return address, we must move it. */
11540 if (regs_available_for_popping
== 0
11541 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
11543 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
11544 reg_containing_return_addr
= LR_REGNUM
;
11546 else if (size
> 12)
11548 /* Register a4 is being used to hold part of the return value,
11549 but we have dire need of a free, low register. */
11552 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
11555 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
11557 /* The fourth argument register is available. */
11558 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
11564 /* Pop as many registers as we can. */
11565 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
11567 /* Process the registers we popped. */
11568 if (reg_containing_return_addr
== -1)
11570 /* The return address was popped into the lowest numbered register. */
11571 regs_to_pop
&= ~(1 << LR_REGNUM
);
11573 reg_containing_return_addr
=
11574 number_of_first_bit_set (regs_available_for_popping
);
11576 /* Remove this register for the mask of available registers, so that
11577 the return address will not be corrupted by further pops. */
11578 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
11581 /* If we popped other registers then handle them here. */
11582 if (regs_available_for_popping
)
11586 /* Work out which register currently contains the frame pointer. */
11587 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
11589 /* Move it into the correct place. */
11590 asm_fprintf (f
, "\tmov\t%r, %r\n",
11591 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
11593 /* (Temporarily) remove it from the mask of popped registers. */
11594 regs_available_for_popping
&= ~(1 << frame_pointer
);
11595 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
11597 if (regs_available_for_popping
)
11601 /* We popped the stack pointer as well,
11602 find the register that contains it. */
11603 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
11605 /* Move it into the stack register. */
11606 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
11608 /* At this point we have popped all necessary registers, so
11609 do not worry about restoring regs_available_for_popping
11610 to its correct value:
11612 assert (pops_needed == 0)
11613 assert (regs_available_for_popping == (1 << frame_pointer))
11614 assert (regs_to_pop == (1 << STACK_POINTER)) */
11618 /* Since we have just move the popped value into the frame
11619 pointer, the popping register is available for reuse, and
11620 we know that we still have the stack pointer left to pop. */
11621 regs_available_for_popping
|= (1 << frame_pointer
);
11625 /* If we still have registers left on the stack, but we no longer have
11626 any registers into which we can pop them, then we must move the return
11627 address into the link register and make available the register that
11629 if (regs_available_for_popping
== 0 && pops_needed
> 0)
11631 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
11633 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
11634 reg_containing_return_addr
);
11636 reg_containing_return_addr
= LR_REGNUM
;
11639 /* If we have registers left on the stack then pop some more.
11640 We know that at most we will want to pop FP and SP. */
11641 if (pops_needed
> 0)
11646 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
11648 /* We have popped either FP or SP.
11649 Move whichever one it is into the correct register. */
11650 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
11651 move_to
= number_of_first_bit_set (regs_to_pop
);
11653 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
11655 regs_to_pop
&= ~(1 << move_to
);
11660 /* If we still have not popped everything then we must have only
11661 had one register available to us and we are now popping the SP. */
11662 if (pops_needed
> 0)
11666 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
11668 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
11670 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
11672 assert (regs_to_pop == (1 << STACK_POINTER))
11673 assert (pops_needed == 1)
11677 /* If necessary restore the a4 register. */
11680 if (reg_containing_return_addr
!= LR_REGNUM
)
11682 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
11683 reg_containing_return_addr
= LR_REGNUM
;
11686 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
11690 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
11692 /* Return to caller. */
11693 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
11696 /* Emit code to push or pop registers to or from the stack. */
11698 thumb_pushpop (FILE *f
, int mask
, int push
)
11701 int lo_mask
= mask
& 0xFF;
11703 if (lo_mask
== 0 && !push
&& (mask
& (1 << 15)))
11705 /* Special case. Do not generate a POP PC statement here, do it in
11707 thumb_exit (f
, -1, NULL_RTX
);
11711 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
11713 /* Look at the low registers first. */
11714 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
11718 asm_fprintf (f
, "%r", regno
);
11720 if ((lo_mask
& ~1) != 0)
11725 if (push
&& (mask
& (1 << LR_REGNUM
)))
11727 /* Catch pushing the LR. */
11731 asm_fprintf (f
, "%r", LR_REGNUM
);
11733 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
11735 /* Catch popping the PC. */
11736 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
)
11738 /* The PC is never poped directly, instead
11739 it is popped into r3 and then BX is used. */
11740 fprintf (f
, "}\n");
11742 thumb_exit (f
, -1, NULL_RTX
);
11751 asm_fprintf (f
, "%r", PC_REGNUM
);
11755 fprintf (f
, "}\n");
11759 thumb_final_prescan_insn (rtx insn
)
11761 if (flag_print_asm_name
)
11762 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
11763 INSN_ADDRESSES (INSN_UID (insn
)));
11767 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
11769 unsigned HOST_WIDE_INT mask
= 0xff;
11772 if (val
== 0) /* XXX */
11775 for (i
= 0; i
< 25; i
++)
11776 if ((val
& (mask
<< i
)) == val
)
11782 /* Returns nonzero if the current function contains,
11783 or might contain a far jump. */
11785 thumb_far_jump_used_p (int in_prologue
)
11789 /* This test is only important for leaf functions. */
11790 /* assert (!leaf_function_p ()); */
11792 /* If we have already decided that far jumps may be used,
11793 do not bother checking again, and always return true even if
11794 it turns out that they are not being used. Once we have made
11795 the decision that far jumps are present (and that hence the link
11796 register will be pushed onto the stack) we cannot go back on it. */
11797 if (cfun
->machine
->far_jump_used
)
11800 /* If this function is not being called from the prologue/epilogue
11801 generation code then it must be being called from the
11802 INITIAL_ELIMINATION_OFFSET macro. */
11805 /* In this case we know that we are being asked about the elimination
11806 of the arg pointer register. If that register is not being used,
11807 then there are no arguments on the stack, and we do not have to
11808 worry that a far jump might force the prologue to push the link
11809 register, changing the stack offsets. In this case we can just
11810 return false, since the presence of far jumps in the function will
11811 not affect stack offsets.
11813 If the arg pointer is live (or if it was live, but has now been
11814 eliminated and so set to dead) then we do have to test to see if
11815 the function might contain a far jump. This test can lead to some
11816 false negatives, since before reload is completed, then length of
11817 branch instructions is not known, so gcc defaults to returning their
11818 longest length, which in turn sets the far jump attribute to true.
11820 A false negative will not result in bad code being generated, but it
11821 will result in a needless push and pop of the link register. We
11822 hope that this does not occur too often. */
11823 if (regs_ever_live
[ARG_POINTER_REGNUM
])
11824 cfun
->machine
->arg_pointer_live
= 1;
11825 else if (!cfun
->machine
->arg_pointer_live
)
11829 /* Check to see if the function contains a branch
11830 insn with the far jump attribute set. */
11831 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11833 if (GET_CODE (insn
) == JUMP_INSN
11834 /* Ignore tablejump patterns. */
11835 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
11836 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
11837 && get_attr_far_jump (insn
) == FAR_JUMP_YES
11840 /* Record the fact that we have decided that
11841 the function does use far jumps. */
11842 cfun
->machine
->far_jump_used
= 1;
11850 /* Return nonzero if FUNC must be entered in ARM mode. */
11852 is_called_in_ARM_mode (tree func
)
11854 if (TREE_CODE (func
) != FUNCTION_DECL
)
11857 /* Ignore the problem about functions whoes address is taken. */
11858 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
11862 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
11868 /* The bits which aren't usefully expanded as rtl. */
11870 thumb_unexpanded_epilogue (void)
11873 int live_regs_mask
= 0;
11874 int high_regs_pushed
= 0;
11875 int leaf_function
= leaf_function_p ();
11876 int had_to_push_lr
;
11877 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
11879 if (return_used_this_function
)
11882 if (IS_NAKED (arm_current_func_type ()))
11885 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
11886 if (THUMB_REG_PUSHED_P (regno
))
11887 live_regs_mask
|= 1 << regno
;
11889 for (regno
= 8; regno
< 13; regno
++)
11890 if (THUMB_REG_PUSHED_P (regno
))
11891 high_regs_pushed
++;
11893 /* The prolog may have pushed some high registers to use as
11894 work registers. eg the testsuite file:
11895 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
11896 compiles to produce:
11897 push {r4, r5, r6, r7, lr}
11901 as part of the prolog. We have to undo that pushing here. */
11903 if (high_regs_pushed
)
11905 int mask
= live_regs_mask
;
11911 /* If we can deduce the registers used from the function's return value.
11912 This is more reliable that examining regs_ever_live[] because that
11913 will be set if the register is ever used in the function, not just if
11914 the register is used to hold a return value. */
11916 if (current_function_return_rtx
!= 0)
11917 mode
= GET_MODE (current_function_return_rtx
);
11920 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
11922 size
= GET_MODE_SIZE (mode
);
11924 /* Unless we are returning a type of size > 12 register r3 is
11930 /* Oh dear! We have no low registers into which we can pop
11933 ("no low registers available for popping high registers");
11935 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
11936 if (THUMB_REG_PUSHED_P (next_hi_reg
))
11939 while (high_regs_pushed
)
11941 /* Find lo register(s) into which the high register(s) can
11943 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
11945 if (mask
& (1 << regno
))
11946 high_regs_pushed
--;
11947 if (high_regs_pushed
== 0)
11951 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
11953 /* Pop the values into the low register(s). */
11954 thumb_pushpop (asm_out_file
, mask
, 0);
11956 /* Move the value(s) into the high registers. */
11957 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
11959 if (mask
& (1 << regno
))
11961 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
11964 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
11965 if (THUMB_REG_PUSHED_P (next_hi_reg
))
11972 had_to_push_lr
= (live_regs_mask
|| !leaf_function
11973 || thumb_far_jump_used_p (1));
11975 if (TARGET_BACKTRACE
11976 && ((live_regs_mask
& 0xFF) == 0)
11977 && regs_ever_live
[LAST_ARG_REGNUM
] != 0)
11979 /* The stack backtrace structure creation code had to
11980 push R7 in order to get a work register, so we pop
11982 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
11985 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
11988 && !is_called_in_ARM_mode (current_function_decl
)
11990 live_regs_mask
|= 1 << PC_REGNUM
;
11992 /* Either no argument registers were pushed or a backtrace
11993 structure was created which includes an adjusted stack
11994 pointer, so just pop everything. */
11995 if (live_regs_mask
)
11996 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
);
11999 thumb_exit (asm_out_file
, 2, eh_ofs
);
12000 /* We have either just popped the return address into the
12001 PC or it is was kept in LR for the entire function or
12002 it is still on the stack because we do not want to
12003 return by doing a pop {pc}. */
12004 else if ((live_regs_mask
& (1 << PC_REGNUM
)) == 0)
12005 thumb_exit (asm_out_file
,
12007 && is_called_in_ARM_mode (current_function_decl
)) ?
12008 -1 : LR_REGNUM
, NULL_RTX
);
12012 /* Pop everything but the return address. */
12013 live_regs_mask
&= ~(1 << PC_REGNUM
);
12015 if (live_regs_mask
)
12016 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
);
12018 if (had_to_push_lr
)
12019 /* Get the return address into a temporary register. */
12020 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0);
12022 /* Remove the argument registers that were pushed onto the stack. */
12023 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
12024 SP_REGNUM
, SP_REGNUM
,
12025 current_function_pretend_args_size
);
12028 thumb_exit (asm_out_file
, 2, eh_ofs
);
12030 thumb_exit (asm_out_file
,
12031 had_to_push_lr
? LAST_ARG_REGNUM
: LR_REGNUM
, NULL_RTX
);
12037 /* Functions to save and restore machine-specific function data. */
12038 static struct machine_function
*
12039 arm_init_machine_status (void)
12041 struct machine_function
*machine
;
12042 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
12044 #if ARM_FT_UNKNOWN != 0
12045 machine
->func_type
= ARM_FT_UNKNOWN
;
12050 /* Return an RTX indicating where the return address to the
12051 calling function can be found. */
12053 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
12058 if (TARGET_APCS_32
)
12059 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
12062 rtx lr
= gen_rtx_AND (Pmode
, gen_rtx_REG (Pmode
, LR_REGNUM
),
12063 GEN_INT (RETURN_ADDR_MASK26
));
12064 return get_func_hard_reg_initial_val (cfun
, lr
);
12068 /* Do anything needed before RTL is emitted for each function. */
12070 arm_init_expanders (void)
12072 /* Arrange to initialize and mark the machine per-function status. */
12073 init_machine_status
= arm_init_machine_status
;
12077 thumb_get_frame_size (void)
12081 int base_size
= ROUND_UP_WORD (get_frame_size ());
12082 int count_regs
= 0;
12083 int entry_size
= 0;
12086 if (! TARGET_THUMB
)
12089 if (! TARGET_ATPCS
)
12092 /* We need to know if we are a leaf function. Unfortunately, it
12093 is possible to be called after start_sequence has been called,
12094 which causes get_insns to return the insns for the sequence,
12095 not the function, which will cause leaf_function_p to return
12096 the incorrect result.
12098 To work around this, we cache the computed frame size. This
12099 works because we will only be calling RTL expanders that need
12100 to know about leaf functions once reload has completed, and the
12101 frame size cannot be changed after that time, so we can safely
12102 use the cached value. */
12104 if (reload_completed
)
12105 return cfun
->machine
->frame_size
;
12107 leaf
= leaf_function_p ();
12109 /* A leaf function does not need any stack alignment if it has nothing
12111 if (leaf
&& base_size
== 0)
12113 cfun
->machine
->frame_size
= 0;
12117 /* We know that SP will be word aligned on entry, and we must
12118 preserve that condition at any subroutine call. But those are
12119 the only constraints. */
12121 /* Space for variadic functions. */
12122 if (current_function_pretend_args_size
)
12123 entry_size
+= current_function_pretend_args_size
;
12125 /* Space for pushed lo registers. */
12126 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
12127 if (THUMB_REG_PUSHED_P (regno
))
12130 /* Space for backtrace structure. */
12131 if (TARGET_BACKTRACE
)
12133 if (count_regs
== 0 && regs_ever_live
[LAST_ARG_REGNUM
] != 0)
12139 if (count_regs
|| !leaf
|| thumb_far_jump_used_p (1))
12140 count_regs
++; /* LR */
12142 entry_size
+= count_regs
* 4;
12145 /* Space for pushed hi regs. */
12146 for (regno
= 8; regno
< 13; regno
++)
12147 if (THUMB_REG_PUSHED_P (regno
))
12150 entry_size
+= count_regs
* 4;
12152 if ((entry_size
+ base_size
+ current_function_outgoing_args_size
) & 7)
12154 if ((entry_size
+ base_size
+ current_function_outgoing_args_size
) & 7)
12157 cfun
->machine
->frame_size
= base_size
;
12162 /* Generate the rest of a function's prologue. */
12164 thumb_expand_prologue (void)
12166 HOST_WIDE_INT amount
= (thumb_get_frame_size ()
12167 + current_function_outgoing_args_size
);
12168 unsigned long func_type
;
12170 func_type
= arm_current_func_type ();
12172 /* Naked functions don't have prologues. */
12173 if (IS_NAKED (func_type
))
12176 if (IS_INTERRUPT (func_type
))
12178 error ("interrupt Service Routines cannot be coded in Thumb mode");
12182 if (frame_pointer_needed
)
12183 emit_insn (gen_movsi (hard_frame_pointer_rtx
, stack_pointer_rtx
));
12187 amount
= ROUND_UP_WORD (amount
);
12190 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
12191 GEN_INT (- amount
)));
12197 /* The stack decrement is too big for an immediate value in a single
12198 insn. In theory we could issue multiple subtracts, but after
12199 three of them it becomes more space efficient to place the full
12200 value in the constant pool and load into a register. (Also the
12201 ARM debugger really likes to see only one stack decrement per
12202 function). So instead we look for a scratch register into which
12203 we can load the decrement, and then we subtract this from the
12204 stack pointer. Unfortunately on the thumb the only available
12205 scratch registers are the argument registers, and we cannot use
12206 these as they may hold arguments to the function. Instead we
12207 attempt to locate a call preserved register which is used by this
12208 function. If we can find one, then we know that it will have
12209 been pushed at the start of the prologue and so we can corrupt
12211 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
12212 if (THUMB_REG_PUSHED_P (regno
)
12213 && !(frame_pointer_needed
12214 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
12217 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
12219 rtx spare
= gen_rtx (REG
, SImode
, IP_REGNUM
);
12221 /* Choose an arbitrary, non-argument low register. */
12222 reg
= gen_rtx (REG
, SImode
, LAST_LO_REGNUM
);
12224 /* Save it by copying it into a high, scratch register. */
12225 emit_insn (gen_movsi (spare
, reg
));
12226 /* Add a USE to stop propagate_one_insn() from barfing. */
12227 emit_insn (gen_prologue_use (spare
));
12229 /* Decrement the stack. */
12230 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
12231 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
12234 /* Restore the low register's original value. */
12235 emit_insn (gen_movsi (reg
, spare
));
12237 /* Emit a USE of the restored scratch register, so that flow
12238 analysis will not consider the restore redundant. The
12239 register won't be used again in this function and isn't
12240 restored by the epilogue. */
12241 emit_insn (gen_prologue_use (reg
));
12245 reg
= gen_rtx (REG
, SImode
, regno
);
12247 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
12248 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
12254 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
12255 emit_insn (gen_blockage ());
12259 thumb_expand_epilogue (void)
12261 HOST_WIDE_INT amount
= (thumb_get_frame_size ()
12262 + current_function_outgoing_args_size
);
12265 /* Naked functions don't have prologues. */
12266 if (IS_NAKED (arm_current_func_type ()))
12269 if (frame_pointer_needed
)
12270 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
12273 amount
= ROUND_UP_WORD (amount
);
12276 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
12277 GEN_INT (amount
)));
12280 /* r3 is always free in the epilogue. */
12281 rtx reg
= gen_rtx (REG
, SImode
, LAST_ARG_REGNUM
);
12283 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
12284 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
12288 /* Emit a USE (stack_pointer_rtx), so that
12289 the stack adjustment will not be deleted. */
12290 emit_insn (gen_prologue_use (stack_pointer_rtx
));
12292 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
12293 emit_insn (gen_blockage ());
12295 /* Emit a clobber for each insn that will be restored in the epilogue,
12296 so that flow2 will get register lifetimes correct. */
12297 for (regno
= 0; regno
< 13; regno
++)
12298 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
12299 emit_insn (gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, regno
)));
12301 if (! regs_ever_live
[LR_REGNUM
])
12302 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, LR_REGNUM
)));
12306 thumb_output_function_prologue (FILE *f
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
12308 int live_regs_mask
= 0;
12309 int high_regs_pushed
= 0;
12312 if (IS_NAKED (arm_current_func_type ()))
12315 if (is_called_in_ARM_mode (current_function_decl
))
12319 if (GET_CODE (DECL_RTL (current_function_decl
)) != MEM
)
12321 if (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0)) != SYMBOL_REF
)
12323 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
12325 /* Generate code sequence to switch us into Thumb mode. */
12326 /* The .code 32 directive has already been emitted by
12327 ASM_DECLARE_FUNCTION_NAME. */
12328 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
12329 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
12331 /* Generate a label, so that the debugger will notice the
12332 change in instruction sets. This label is also used by
12333 the assembler to bypass the ARM code when this function
12334 is called from a Thumb encoded function elsewhere in the
12335 same file. Hence the definition of STUB_NAME here must
12336 agree with the definition in gas/config/tc-arm.c */
12338 #define STUB_NAME ".real_start_of"
12340 fprintf (f
, "\t.code\t16\n");
12342 if (arm_dllexport_name_p (name
))
12343 name
= arm_strip_name_encoding (name
);
12345 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
12346 fprintf (f
, "\t.thumb_func\n");
12347 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
12350 if (current_function_pretend_args_size
)
12352 if (cfun
->machine
->uses_anonymous_args
)
12356 fprintf (f
, "\tpush\t{");
12358 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
12360 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
12361 regno
<= LAST_ARG_REGNUM
;
12363 asm_fprintf (f
, "%r%s", regno
,
12364 regno
== LAST_ARG_REGNUM
? "" : ", ");
12366 fprintf (f
, "}\n");
12369 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
12370 SP_REGNUM
, SP_REGNUM
,
12371 current_function_pretend_args_size
);
12374 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
12375 if (THUMB_REG_PUSHED_P (regno
))
12376 live_regs_mask
|= 1 << regno
;
12378 if (live_regs_mask
|| !leaf_function_p () || thumb_far_jump_used_p (1))
12379 live_regs_mask
|= 1 << LR_REGNUM
;
12381 if (TARGET_BACKTRACE
)
12384 int work_register
= 0;
12387 /* We have been asked to create a stack backtrace structure.
12388 The code looks like this:
12392 0 sub SP, #16 Reserve space for 4 registers.
12393 2 push {R7} Get a work register.
12394 4 add R7, SP, #20 Get the stack pointer before the push.
12395 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
12396 8 mov R7, PC Get hold of the start of this code plus 12.
12397 10 str R7, [SP, #16] Store it.
12398 12 mov R7, FP Get hold of the current frame pointer.
12399 14 str R7, [SP, #4] Store it.
12400 16 mov R7, LR Get hold of the current return address.
12401 18 str R7, [SP, #12] Store it.
12402 20 add R7, SP, #16 Point at the start of the backtrace structure.
12403 22 mov FP, R7 Put this value into the frame pointer. */
12405 if ((live_regs_mask
& 0xFF) == 0)
12407 /* See if the a4 register is free. */
12409 if (regs_ever_live
[LAST_ARG_REGNUM
] == 0)
12410 work_register
= LAST_ARG_REGNUM
;
12411 else /* We must push a register of our own */
12412 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
12415 if (work_register
== 0)
12417 /* Select a register from the list that will be pushed to
12418 use as our work register. */
12419 for (work_register
= (LAST_LO_REGNUM
+ 1); work_register
--;)
12420 if ((1 << work_register
) & live_regs_mask
)
12425 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
12426 SP_REGNUM
, SP_REGNUM
);
12428 if (live_regs_mask
)
12429 thumb_pushpop (f
, live_regs_mask
, 1);
12431 for (offset
= 0, wr
= 1 << 15; wr
!= 0; wr
>>= 1)
12432 if (wr
& live_regs_mask
)
12435 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
12436 offset
+ 16 + current_function_pretend_args_size
);
12438 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12441 /* Make sure that the instruction fetching the PC is in the right place
12442 to calculate "start of backtrace creation code + 12". */
12443 if (live_regs_mask
)
12445 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
12446 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12448 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
12449 ARM_HARD_FRAME_POINTER_REGNUM
);
12450 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12455 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
12456 ARM_HARD_FRAME_POINTER_REGNUM
);
12457 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12459 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
12460 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12464 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
12465 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
12467 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
12469 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
12470 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
12472 else if (live_regs_mask
)
12473 thumb_pushpop (f
, live_regs_mask
, 1);
12475 for (regno
= 8; regno
< 13; regno
++)
12476 if (THUMB_REG_PUSHED_P (regno
))
12477 high_regs_pushed
++;
12479 if (high_regs_pushed
)
12481 int pushable_regs
= 0;
12482 int mask
= live_regs_mask
& 0xff;
12485 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
12486 if (THUMB_REG_PUSHED_P (next_hi_reg
))
12489 pushable_regs
= mask
;
12491 if (pushable_regs
== 0)
12493 /* Desperation time -- this probably will never happen. */
12494 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
))
12495 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, LAST_ARG_REGNUM
);
12496 mask
= 1 << LAST_ARG_REGNUM
;
12499 while (high_regs_pushed
> 0)
12501 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
12503 if (mask
& (1 << regno
))
12505 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
12507 high_regs_pushed
--;
12509 if (high_regs_pushed
)
12511 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
12513 if (THUMB_REG_PUSHED_P (next_hi_reg
))
12518 mask
&= ~((1 << regno
) - 1);
12524 thumb_pushpop (f
, mask
, 1);
12527 if (pushable_regs
== 0
12528 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
)))
12529 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
12533 /* Handle the case of a double word load into a low register from
12534 a computed memory address. The computed address may involve a
12535 register which is overwritten by the load. */
12537 thumb_load_double_from_address (rtx
*operands
)
12545 if (GET_CODE (operands
[0]) != REG
)
12548 if (GET_CODE (operands
[1]) != MEM
)
12551 /* Get the memory address. */
12552 addr
= XEXP (operands
[1], 0);
12554 /* Work out how the memory address is computed. */
12555 switch (GET_CODE (addr
))
12558 operands
[2] = gen_rtx (MEM
, SImode
,
12559 plus_constant (XEXP (operands
[1], 0), 4));
12561 if (REGNO (operands
[0]) == REGNO (addr
))
12563 output_asm_insn ("ldr\t%H0, %2", operands
);
12564 output_asm_insn ("ldr\t%0, %1", operands
);
12568 output_asm_insn ("ldr\t%0, %1", operands
);
12569 output_asm_insn ("ldr\t%H0, %2", operands
);
12574 /* Compute <address> + 4 for the high order load. */
12575 operands
[2] = gen_rtx (MEM
, SImode
,
12576 plus_constant (XEXP (operands
[1], 0), 4));
12578 output_asm_insn ("ldr\t%0, %1", operands
);
12579 output_asm_insn ("ldr\t%H0, %2", operands
);
12583 arg1
= XEXP (addr
, 0);
12584 arg2
= XEXP (addr
, 1);
12586 if (CONSTANT_P (arg1
))
12587 base
= arg2
, offset
= arg1
;
12589 base
= arg1
, offset
= arg2
;
12591 if (GET_CODE (base
) != REG
)
12594 /* Catch the case of <address> = <reg> + <reg> */
12595 if (GET_CODE (offset
) == REG
)
12597 int reg_offset
= REGNO (offset
);
12598 int reg_base
= REGNO (base
);
12599 int reg_dest
= REGNO (operands
[0]);
12601 /* Add the base and offset registers together into the
12602 higher destination register. */
12603 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
12604 reg_dest
+ 1, reg_base
, reg_offset
);
12606 /* Load the lower destination register from the address in
12607 the higher destination register. */
12608 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
12609 reg_dest
, reg_dest
+ 1);
12611 /* Load the higher destination register from its own address
12613 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
12614 reg_dest
+ 1, reg_dest
+ 1);
12618 /* Compute <address> + 4 for the high order load. */
12619 operands
[2] = gen_rtx (MEM
, SImode
,
12620 plus_constant (XEXP (operands
[1], 0), 4));
12622 /* If the computed address is held in the low order register
12623 then load the high order register first, otherwise always
12624 load the low order register first. */
12625 if (REGNO (operands
[0]) == REGNO (base
))
12627 output_asm_insn ("ldr\t%H0, %2", operands
);
12628 output_asm_insn ("ldr\t%0, %1", operands
);
12632 output_asm_insn ("ldr\t%0, %1", operands
);
12633 output_asm_insn ("ldr\t%H0, %2", operands
);
12639 /* With no registers to worry about we can just load the value
12641 operands
[2] = gen_rtx (MEM
, SImode
,
12642 plus_constant (XEXP (operands
[1], 0), 4));
12644 output_asm_insn ("ldr\t%H0, %2", operands
);
12645 output_asm_insn ("ldr\t%0, %1", operands
);
12657 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
12664 if (REGNO (operands
[4]) > REGNO (operands
[5]))
12667 operands
[4] = operands
[5];
12670 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
12671 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
12675 if (REGNO (operands
[4]) > REGNO (operands
[5]))
12678 operands
[4] = operands
[5];
12681 if (REGNO (operands
[5]) > REGNO (operands
[6]))
12684 operands
[5] = operands
[6];
12687 if (REGNO (operands
[4]) > REGNO (operands
[5]))
12690 operands
[4] = operands
[5];
12694 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
12695 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
12705 /* Routines for generating rtl. */
12707 thumb_expand_movstrqi (rtx
*operands
)
12709 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
12710 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
12711 HOST_WIDE_INT len
= INTVAL (operands
[2]);
12712 HOST_WIDE_INT offset
= 0;
12716 emit_insn (gen_movmem12b (out
, in
, out
, in
));
12722 emit_insn (gen_movmem8b (out
, in
, out
, in
));
12728 rtx reg
= gen_reg_rtx (SImode
);
12729 emit_insn (gen_movsi (reg
, gen_rtx (MEM
, SImode
, in
)));
12730 emit_insn (gen_movsi (gen_rtx (MEM
, SImode
, out
), reg
));
12737 rtx reg
= gen_reg_rtx (HImode
);
12738 emit_insn (gen_movhi (reg
, gen_rtx (MEM
, HImode
,
12739 plus_constant (in
, offset
))));
12740 emit_insn (gen_movhi (gen_rtx (MEM
, HImode
, plus_constant (out
, offset
)),
12748 rtx reg
= gen_reg_rtx (QImode
);
12749 emit_insn (gen_movqi (reg
, gen_rtx (MEM
, QImode
,
12750 plus_constant (in
, offset
))));
12751 emit_insn (gen_movqi (gen_rtx (MEM
, QImode
, plus_constant (out
, offset
)),
12757 thumb_cmp_operand (rtx op
, enum machine_mode mode
)
12759 return ((GET_CODE (op
) == CONST_INT
12760 && INTVAL (op
) < 256
12761 && INTVAL (op
) >= 0)
12762 || s_register_operand (op
, mode
));
12766 thumb_cmpneg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
12768 return (GET_CODE (op
) == CONST_INT
12770 && INTVAL (op
) > -256);
12773 /* Return TRUE if a result can be stored in OP without clobbering the
12774 condition code register. Prior to reload we only accept a
12775 register. After reload we have to be able to handle memory as
12776 well, since a pseudo may not get a hard reg and reload cannot
12777 handle output-reloads on jump insns.
12779 We could possibly handle mem before reload as well, but that might
12780 complicate things with the need to handle increment
12784 thumb_cbrch_target_operand (rtx op
, enum machine_mode mode
)
12786 return (s_register_operand (op
, mode
)
12787 || ((reload_in_progress
|| reload_completed
)
12788 && memory_operand (op
, mode
)));
12791 /* Handle storing a half-word to memory during reload. */
12793 thumb_reload_out_hi (rtx
*operands
)
12795 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
12798 /* Handle reading a half-word from memory during reload. */
12800 thumb_reload_in_hi (rtx
*operands ATTRIBUTE_UNUSED
)
12805 /* Return the length of a function name prefix
12806 that starts with the character 'c'. */
12808 arm_get_strip_length (int c
)
12812 ARM_NAME_ENCODING_LENGTHS
12817 /* Return a pointer to a function's name with any
12818 and all prefix encodings stripped from it. */
12820 arm_strip_name_encoding (const char *name
)
12824 while ((skip
= arm_get_strip_length (* name
)))
12830 /* If there is a '*' anywhere in the name's prefix, then
12831 emit the stripped name verbatim, otherwise prepend an
12832 underscore if leading underscores are being used. */
12834 arm_asm_output_labelref (FILE *stream
, const char *name
)
12839 while ((skip
= arm_get_strip_length (* name
)))
12841 verbatim
|= (*name
== '*');
12846 fputs (name
, stream
);
12848 asm_fprintf (stream
, "%U%s", name
);
12853 #ifdef AOF_ASSEMBLER
12854 /* Special functions only needed when producing AOF syntax assembler. */
12858 struct pic_chain
* next
;
12859 const char * symname
;
12862 static struct pic_chain
* aof_pic_chain
= NULL
;
12865 aof_pic_entry (rtx x
)
12867 struct pic_chain
** chainp
;
12870 if (aof_pic_label
== NULL_RTX
)
12872 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
12875 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
12876 offset
+= 4, chainp
= &(*chainp
)->next
)
12877 if ((*chainp
)->symname
== XSTR (x
, 0))
12878 return plus_constant (aof_pic_label
, offset
);
12880 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
12881 (*chainp
)->next
= NULL
;
12882 (*chainp
)->symname
= XSTR (x
, 0);
12883 return plus_constant (aof_pic_label
, offset
);
12887 aof_dump_pic_table (FILE *f
)
12889 struct pic_chain
* chain
;
12891 if (aof_pic_chain
== NULL
)
12894 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
12895 PIC_OFFSET_TABLE_REGNUM
,
12896 PIC_OFFSET_TABLE_REGNUM
);
12897 fputs ("|x$adcons|\n", f
);
12899 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
12901 fputs ("\tDCD\t", f
);
12902 assemble_name (f
, chain
->symname
);
12907 int arm_text_section_count
= 1;
12910 aof_text_section (void )
12912 static char buf
[100];
12913 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
12914 arm_text_section_count
++);
12916 strcat (buf
, ", PIC, REENTRANT");
12920 static int arm_data_section_count
= 1;
12923 aof_data_section (void)
12925 static char buf
[100];
12926 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
12930 /* The AOF assembler is religiously strict about declarations of
12931 imported and exported symbols, so that it is impossible to declare
12932 a function as imported near the beginning of the file, and then to
12933 export it later on. It is, however, possible to delay the decision
12934 until all the functions in the file have been compiled. To get
12935 around this, we maintain a list of the imports and exports, and
12936 delete from it any that are subsequently defined. At the end of
12937 compilation we spit the remainder of the list out before the END
12942 struct import
* next
;
12946 static struct import
* imports_list
= NULL
;
12949 aof_add_import (const char *name
)
12951 struct import
* new;
12953 for (new = imports_list
; new; new = new->next
)
12954 if (new->name
== name
)
12957 new = (struct import
*) xmalloc (sizeof (struct import
));
12958 new->next
= imports_list
;
12959 imports_list
= new;
12964 aof_delete_import (const char *name
)
12966 struct import
** old
;
12968 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
12970 if ((*old
)->name
== name
)
12972 *old
= (*old
)->next
;
12978 int arm_main_function
= 0;
12981 aof_dump_imports (FILE *f
)
12983 /* The AOF assembler needs this to cause the startup code to be extracted
12984 from the library. Brining in __main causes the whole thing to work
12986 if (arm_main_function
)
12989 fputs ("\tIMPORT __main\n", f
);
12990 fputs ("\tDCD __main\n", f
);
12993 /* Now dump the remaining imports. */
12994 while (imports_list
)
12996 fprintf (f
, "\tIMPORT\t");
12997 assemble_name (f
, imports_list
->name
);
12999 imports_list
= imports_list
->next
;
13004 aof_globalize_label (FILE *stream
, const char *name
)
13006 default_globalize_label (stream
, name
);
13007 if (! strcmp (name
, "main"))
13008 arm_main_function
= 1;
13014 fputs ("__r0\tRN\t0\n", asm_out_file
);
13015 fputs ("__a1\tRN\t0\n", asm_out_file
);
13016 fputs ("__a2\tRN\t1\n", asm_out_file
);
13017 fputs ("__a3\tRN\t2\n", asm_out_file
);
13018 fputs ("__a4\tRN\t3\n", asm_out_file
);
13019 fputs ("__v1\tRN\t4\n", asm_out_file
);
13020 fputs ("__v2\tRN\t5\n", asm_out_file
);
13021 fputs ("__v3\tRN\t6\n", asm_out_file
);
13022 fputs ("__v4\tRN\t7\n", asm_out_file
);
13023 fputs ("__v5\tRN\t8\n", asm_out_file
);
13024 fputs ("__v6\tRN\t9\n", asm_out_file
);
13025 fputs ("__sl\tRN\t10\n", asm_out_file
);
13026 fputs ("__fp\tRN\t11\n", asm_out_file
);
13027 fputs ("__ip\tRN\t12\n", asm_out_file
);
13028 fputs ("__sp\tRN\t13\n", asm_out_file
);
13029 fputs ("__lr\tRN\t14\n", asm_out_file
);
13030 fputs ("__pc\tRN\t15\n", asm_out_file
);
13031 fputs ("__f0\tFN\t0\n", asm_out_file
);
13032 fputs ("__f1\tFN\t1\n", asm_out_file
);
13033 fputs ("__f2\tFN\t2\n", asm_out_file
);
13034 fputs ("__f3\tFN\t3\n", asm_out_file
);
13035 fputs ("__f4\tFN\t4\n", asm_out_file
);
13036 fputs ("__f5\tFN\t5\n", asm_out_file
);
13037 fputs ("__f6\tFN\t6\n", asm_out_file
);
13038 fputs ("__f7\tFN\t7\n", asm_out_file
);
13043 aof_file_end (void)
13046 aof_dump_pic_table (asm_out_file
);
13047 aof_dump_imports (asm_out_file
);
13048 fputs ("\tEND\n", asm_out_file
);
13050 #endif /* AOF_ASSEMBLER */
13052 #ifdef OBJECT_FORMAT_ELF
13053 /* Switch to an arbitrary section NAME with attributes as specified
13054 by FLAGS. ALIGN specifies any known alignment requirements for
13055 the section; 0 if the default should be used.
13057 Differs from the default elf version only in the prefix character
13058 used before the section type. */
13061 arm_elf_asm_named_section (const char *name
, unsigned int flags
)
13063 char flagchars
[10], *f
= flagchars
;
13065 if (! named_section_first_declaration (name
))
13067 fprintf (asm_out_file
, "\t.section\t%s\n", name
);
13071 if (!(flags
& SECTION_DEBUG
))
13073 if (flags
& SECTION_WRITE
)
13075 if (flags
& SECTION_CODE
)
13077 if (flags
& SECTION_SMALL
)
13079 if (flags
& SECTION_MERGE
)
13081 if (flags
& SECTION_STRINGS
)
13083 if (flags
& SECTION_TLS
)
13087 fprintf (asm_out_file
, "\t.section\t%s,\"%s\"", name
, flagchars
);
13089 if (!(flags
& SECTION_NOTYPE
))
13093 if (flags
& SECTION_BSS
)
13098 fprintf (asm_out_file
, ",%%%s", type
);
13100 if (flags
& SECTION_ENTSIZE
)
13101 fprintf (asm_out_file
, ",%d", flags
& SECTION_ENTSIZE
);
13104 putc ('\n', asm_out_file
);
13109 /* Symbols in the text segment can be accessed without indirecting via the
13110 constant pool; it may take an extra binary operation, but this is still
13111 faster than indirecting via memory. Don't do this when not optimizing,
13112 since we won't be calculating al of the offsets necessary to do this
13116 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
13118 /* This doesn't work with AOF syntax, since the string table may be in
13119 a different AREA. */
13120 #ifndef AOF_ASSEMBLER
13121 if (optimize
> 0 && TREE_CONSTANT (decl
)
13122 && (!flag_writable_strings
|| TREE_CODE (decl
) != STRING_CST
))
13123 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
13126 /* If we are referencing a function that is weak then encode a long call
13127 flag in the function name, otherwise if the function is static or
13128 or known to be defined in this file then encode a short call flag. */
13129 if (first
&& TREE_CODE_CLASS (TREE_CODE (decl
)) == 'd')
13131 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
13132 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
13133 else if (! TREE_PUBLIC (decl
))
13134 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
13137 #endif /* !ARM_PE */
13140 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
13142 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
13143 && !strcmp (prefix
, "L"))
13145 arm_ccfsm_state
= 0;
13146 arm_target_insn
= NULL
;
13148 default_internal_label (stream
, prefix
, labelno
);
13151 /* Output code to add DELTA to the first argument, and then jump
13152 to FUNCTION. Used for C++ multiple inheritance. */
13154 arm_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
13155 HOST_WIDE_INT delta
,
13156 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
13159 int mi_delta
= delta
;
13160 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
13162 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
13165 mi_delta
= - mi_delta
;
13166 while (mi_delta
!= 0)
13168 if ((mi_delta
& (3 << shift
)) == 0)
13172 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
13173 mi_op
, this_regno
, this_regno
,
13174 mi_delta
& (0xff << shift
));
13175 mi_delta
&= ~(0xff << shift
);
13179 fputs ("\tb\t", file
);
13180 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
13181 if (NEED_PLT_RELOC
)
13182 fputs ("(PLT)", file
);
13183 fputc ('\n', file
);
13187 arm_emit_vector_const (FILE *file
, rtx x
)
13190 const char * pattern
;
13192 if (GET_CODE (x
) != CONST_VECTOR
)
13195 switch (GET_MODE (x
))
13197 case V2SImode
: pattern
= "%08x"; break;
13198 case V4HImode
: pattern
= "%04x"; break;
13199 case V8QImode
: pattern
= "%02x"; break;
13203 fprintf (file
, "0x");
13204 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
13208 element
= CONST_VECTOR_ELT (x
, i
);
13209 fprintf (file
, pattern
, INTVAL (element
));
13216 arm_output_load_gr (rtx
*operands
)
13223 if (GET_CODE (operands
[1]) != MEM
13224 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
13225 || GET_CODE (reg
= XEXP (sum
, 0)) != REG
13226 || GET_CODE (offset
= XEXP (sum
, 1)) != CONST_INT
13227 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
13228 return "wldrw%?\t%0, %1";
13230 /* Fix up an out-of-range load of a GR register. */
13231 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
13232 wcgr
= operands
[0];
13234 output_asm_insn ("ldr%?\t%0, %1", operands
);
13236 operands
[0] = wcgr
;
13238 output_asm_insn ("tmcr%?\t%0, %1", operands
);
13239 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);