1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991-2021 Free Software Foundation, Inc.
3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
5 More major hacks by Richard Earnshaw (rearnsha@arm.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
23 #define IN_TARGET_CODE 1
26 #define INCLUDE_STRING
28 #include "coretypes.h"
37 #include "stringpool.h"
44 #include "diagnostic-core.h"
46 #include "fold-const.h"
47 #include "stor-layout.h"
51 #include "insn-attr.h"
57 #include "sched-int.h"
58 #include "common/common-target.h"
59 #include "langhooks.h"
64 #include "target-globals.h"
66 #include "tm-constrs.h"
68 #include "optabs-libfuncs.h"
73 /* This file should be included last. */
74 #include "target-def.h"
76 /* Forward definitions of types. */
77 typedef struct minipool_node Mnode
;
78 typedef struct minipool_fixup Mfix
;
80 /* The last .arch and .fpu assembly strings that we printed. */
81 static std::string arm_last_printed_arch_string
;
82 static std::string arm_last_printed_fpu_string
;
84 void (*arm_lang_output_object_attributes_hook
)(void);
91 /* Forward function declarations. */
92 static bool arm_const_not_ok_for_debug_p (rtx
);
93 static int arm_needs_doubleword_align (machine_mode
, const_tree
);
94 static int arm_compute_static_chain_stack_bytes (void);
95 static arm_stack_offsets
*arm_get_frame_offsets (void);
96 static void arm_compute_frame_layout (void);
97 static void arm_add_gc_roots (void);
98 static int arm_gen_constant (enum rtx_code
, machine_mode
, rtx
,
99 unsigned HOST_WIDE_INT
, rtx
, rtx
, int, int);
100 static unsigned bit_count (unsigned long);
101 static unsigned bitmap_popcount (const sbitmap
);
102 static int arm_address_register_rtx_p (rtx
, int);
103 static int arm_legitimate_index_p (machine_mode
, rtx
, RTX_CODE
, int);
104 static bool is_called_in_ARM_mode (tree
);
105 static int thumb2_legitimate_index_p (machine_mode
, rtx
, int);
106 static int thumb1_base_register_rtx_p (rtx
, machine_mode
, int);
107 static rtx
arm_legitimize_address (rtx
, rtx
, machine_mode
);
108 static reg_class_t
arm_preferred_reload_class (rtx
, reg_class_t
);
109 static rtx
thumb_legitimize_address (rtx
, rtx
, machine_mode
);
110 inline static int thumb1_index_register_rtx_p (rtx
, int);
111 static int thumb_far_jump_used_p (void);
112 static bool thumb_force_lr_save (void);
113 static unsigned arm_size_return_regs (void);
114 static bool arm_assemble_integer (rtx
, unsigned int, int);
115 static void arm_print_operand (FILE *, rtx
, int);
116 static void arm_print_operand_address (FILE *, machine_mode
, rtx
);
117 static bool arm_print_operand_punct_valid_p (unsigned char code
);
118 static const char *fp_const_from_val (REAL_VALUE_TYPE
*);
119 static arm_cc
get_arm_condition_code (rtx
);
120 static bool arm_fixed_condition_code_regs (unsigned int *, unsigned int *);
121 static const char *output_multi_immediate (rtx
*, const char *, const char *,
123 static const char *shift_op (rtx
, HOST_WIDE_INT
*);
124 static struct machine_function
*arm_init_machine_status (void);
125 static void thumb_exit (FILE *, int);
126 static HOST_WIDE_INT
get_jump_table_size (rtx_jump_table_data
*);
127 static Mnode
*move_minipool_fix_forward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
128 static Mnode
*add_minipool_forward_ref (Mfix
*);
129 static Mnode
*move_minipool_fix_backward_ref (Mnode
*, Mnode
*, HOST_WIDE_INT
);
130 static Mnode
*add_minipool_backward_ref (Mfix
*);
131 static void assign_minipool_offsets (Mfix
*);
132 static void arm_print_value (FILE *, rtx
);
133 static void dump_minipool (rtx_insn
*);
134 static int arm_barrier_cost (rtx_insn
*);
135 static Mfix
*create_fix_barrier (Mfix
*, HOST_WIDE_INT
);
136 static void push_minipool_barrier (rtx_insn
*, HOST_WIDE_INT
);
137 static void push_minipool_fix (rtx_insn
*, HOST_WIDE_INT
, rtx
*,
139 static void arm_reorg (void);
140 static void note_invalid_constants (rtx_insn
*, HOST_WIDE_INT
, int);
141 static unsigned long arm_compute_save_reg0_reg12_mask (void);
142 static unsigned long arm_compute_save_core_reg_mask (void);
143 static unsigned long arm_isr_value (tree
);
144 static unsigned long arm_compute_func_type (void);
145 static tree
arm_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
146 static tree
arm_handle_pcs_attribute (tree
*, tree
, tree
, int, bool *);
147 static tree
arm_handle_isr_attribute (tree
*, tree
, tree
, int, bool *);
148 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
149 static tree
arm_handle_notshared_attribute (tree
*, tree
, tree
, int, bool *);
151 static tree
arm_handle_cmse_nonsecure_entry (tree
*, tree
, tree
, int, bool *);
152 static tree
arm_handle_cmse_nonsecure_call (tree
*, tree
, tree
, int, bool *);
153 static void arm_output_function_epilogue (FILE *);
154 static void arm_output_function_prologue (FILE *);
155 static int arm_comp_type_attributes (const_tree
, const_tree
);
156 static void arm_set_default_type_attributes (tree
);
157 static int arm_adjust_cost (rtx_insn
*, int, rtx_insn
*, int, unsigned int);
158 static int arm_sched_reorder (FILE *, int, rtx_insn
**, int *, int);
159 static int optimal_immediate_sequence (enum rtx_code code
,
160 unsigned HOST_WIDE_INT val
,
161 struct four_ints
*return_sequence
);
162 static int optimal_immediate_sequence_1 (enum rtx_code code
,
163 unsigned HOST_WIDE_INT val
,
164 struct four_ints
*return_sequence
,
166 static int arm_get_strip_length (int);
167 static bool arm_function_ok_for_sibcall (tree
, tree
);
168 static machine_mode
arm_promote_function_mode (const_tree
,
171 static bool arm_return_in_memory (const_tree
, const_tree
);
172 static rtx
arm_function_value (const_tree
, const_tree
, bool);
173 static rtx
arm_libcall_value_1 (machine_mode
);
174 static rtx
arm_libcall_value (machine_mode
, const_rtx
);
175 static bool arm_function_value_regno_p (const unsigned int);
176 static void arm_internal_label (FILE *, const char *, unsigned long);
177 static void arm_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
179 static bool arm_have_conditional_execution (void);
180 static bool arm_cannot_force_const_mem (machine_mode
, rtx
);
181 static bool arm_legitimate_constant_p (machine_mode
, rtx
);
182 static bool arm_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
183 static int arm_insn_cost (rtx_insn
*, bool);
184 static int arm_address_cost (rtx
, machine_mode
, addr_space_t
, bool);
185 static int arm_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
186 static int arm_memory_move_cost (machine_mode
, reg_class_t
, bool);
187 static void emit_constant_insn (rtx cond
, rtx pattern
);
188 static rtx_insn
*emit_set_insn (rtx
, rtx
);
189 static void arm_add_cfa_adjust_cfa_note (rtx
, int, rtx
, rtx
);
190 static rtx
emit_multi_reg_push (unsigned long, unsigned long);
191 static void arm_emit_multi_reg_pop (unsigned long);
192 static int vfp_emit_fstmd (int, int);
193 static void arm_emit_vfp_multi_reg_pop (int, int, rtx
);
194 static int arm_arg_partial_bytes (cumulative_args_t
,
195 const function_arg_info
&);
196 static rtx
arm_function_arg (cumulative_args_t
, const function_arg_info
&);
197 static void arm_function_arg_advance (cumulative_args_t
,
198 const function_arg_info
&);
199 static pad_direction
arm_function_arg_padding (machine_mode
, const_tree
);
200 static unsigned int arm_function_arg_boundary (machine_mode
, const_tree
);
201 static rtx
aapcs_allocate_return_reg (machine_mode
, const_tree
,
203 static rtx
aapcs_libcall_value (machine_mode
);
204 static int aapcs_select_return_coproc (const_tree
, const_tree
);
206 #ifdef OBJECT_FORMAT_ELF
207 static void arm_elf_asm_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
208 static void arm_elf_asm_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
211 static void arm_encode_section_info (tree
, rtx
, int);
214 static void arm_file_end (void);
215 static void arm_file_start (void);
216 static void arm_insert_attributes (tree
, tree
*);
218 static void arm_setup_incoming_varargs (cumulative_args_t
,
219 const function_arg_info
&, int *, int);
220 static bool arm_pass_by_reference (cumulative_args_t
,
221 const function_arg_info
&);
222 static bool arm_promote_prototypes (const_tree
);
223 static bool arm_default_short_enums (void);
224 static bool arm_align_anon_bitfield (void);
225 static bool arm_return_in_msb (const_tree
);
226 static bool arm_must_pass_in_stack (const function_arg_info
&);
227 static bool arm_return_in_memory (const_tree
, const_tree
);
229 static void arm_unwind_emit (FILE *, rtx_insn
*);
230 static bool arm_output_ttype (rtx
);
231 static void arm_asm_emit_except_personality (rtx
);
233 static void arm_asm_init_sections (void);
234 static rtx
arm_dwarf_register_span (rtx
);
236 static tree
arm_cxx_guard_type (void);
237 static bool arm_cxx_guard_mask_bit (void);
238 static tree
arm_get_cookie_size (tree
);
239 static bool arm_cookie_has_size (void);
240 static bool arm_cxx_cdtor_returns_this (void);
241 static bool arm_cxx_key_method_may_be_inline (void);
242 static void arm_cxx_determine_class_data_visibility (tree
);
243 static bool arm_cxx_class_data_always_comdat (void);
244 static bool arm_cxx_use_aeabi_atexit (void);
245 static void arm_init_libfuncs (void);
246 static tree
arm_build_builtin_va_list (void);
247 static void arm_expand_builtin_va_start (tree
, rtx
);
248 static tree
arm_gimplify_va_arg_expr (tree
, tree
, gimple_seq
*, gimple_seq
*);
249 static void arm_option_override (void);
250 static void arm_option_restore (struct gcc_options
*, struct gcc_options
*,
251 struct cl_target_option
*);
252 static void arm_override_options_after_change (void);
253 static void arm_option_print (FILE *, int, struct cl_target_option
*);
254 static void arm_set_current_function (tree
);
255 static bool arm_can_inline_p (tree
, tree
);
256 static void arm_relayout_function (tree
);
257 static bool arm_valid_target_attribute_p (tree
, tree
, tree
, int);
258 static unsigned HOST_WIDE_INT
arm_shift_truncation_mask (machine_mode
);
259 static bool arm_sched_can_speculate_insn (rtx_insn
*);
260 static bool arm_macro_fusion_p (void);
261 static bool arm_cannot_copy_insn_p (rtx_insn
*);
262 static int arm_issue_rate (void);
263 static int arm_sched_variable_issue (FILE *, int, rtx_insn
*, int);
264 static int arm_first_cycle_multipass_dfa_lookahead (void);
265 static int arm_first_cycle_multipass_dfa_lookahead_guard (rtx_insn
*, int);
266 static void arm_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
267 static bool arm_output_addr_const_extra (FILE *, rtx
);
268 static bool arm_allocate_stack_slots_for_args (void);
269 static bool arm_warn_func_return (tree
);
270 static tree
arm_promoted_type (const_tree t
);
271 static bool arm_scalar_mode_supported_p (scalar_mode
);
272 static bool arm_frame_pointer_required (void);
273 static bool arm_can_eliminate (const int, const int);
274 static void arm_asm_trampoline_template (FILE *);
275 static void arm_trampoline_init (rtx
, tree
, rtx
);
276 static rtx
arm_trampoline_adjust_address (rtx
);
277 static rtx_insn
*arm_pic_static_addr (rtx orig
, rtx reg
);
278 static bool cortex_a9_sched_adjust_cost (rtx_insn
*, int, rtx_insn
*, int *);
279 static bool xscale_sched_adjust_cost (rtx_insn
*, int, rtx_insn
*, int *);
280 static bool fa726te_sched_adjust_cost (rtx_insn
*, int, rtx_insn
*, int *);
281 static bool arm_array_mode_supported_p (machine_mode
,
282 unsigned HOST_WIDE_INT
);
283 static machine_mode
arm_preferred_simd_mode (scalar_mode
);
284 static bool arm_class_likely_spilled_p (reg_class_t
);
285 static HOST_WIDE_INT
arm_vector_alignment (const_tree type
);
286 static bool arm_vector_alignment_reachable (const_tree type
, bool is_packed
);
287 static bool arm_builtin_support_vector_misalignment (machine_mode mode
,
291 static void arm_conditional_register_usage (void);
292 static enum flt_eval_method
arm_excess_precision (enum excess_precision_type
);
293 static reg_class_t
arm_preferred_rename_class (reg_class_t rclass
);
294 static unsigned int arm_autovectorize_vector_modes (vector_modes
*, bool);
295 static int arm_default_branch_cost (bool, bool);
296 static int arm_cortex_a5_branch_cost (bool, bool);
297 static int arm_cortex_m_branch_cost (bool, bool);
298 static int arm_cortex_m7_branch_cost (bool, bool);
300 static bool arm_vectorize_vec_perm_const (machine_mode
, rtx
, rtx
, rtx
,
301 const vec_perm_indices
&);
303 static bool aarch_macro_fusion_pair_p (rtx_insn
*, rtx_insn
*);
305 static int arm_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
307 int misalign ATTRIBUTE_UNUSED
);
308 static unsigned arm_add_stmt_cost (vec_info
*vinfo
, void *data
, int count
,
309 enum vect_cost_for_stmt kind
,
310 struct _stmt_vec_info
*stmt_info
,
311 tree vectype
, int misalign
,
312 enum vect_cost_model_location where
);
314 static void arm_canonicalize_comparison (int *code
, rtx
*op0
, rtx
*op1
,
315 bool op0_preserve_value
);
316 static unsigned HOST_WIDE_INT
arm_asan_shadow_offset (void);
318 static void arm_sched_fusion_priority (rtx_insn
*, int, int *, int*);
319 static bool arm_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
, HOST_WIDE_INT
,
321 static section
*arm_function_section (tree
, enum node_frequency
, bool, bool);
322 static bool arm_asm_elf_flags_numeric (unsigned int flags
, unsigned int *num
);
323 static unsigned int arm_elf_section_type_flags (tree decl
, const char *name
,
325 static void arm_expand_divmod_libfunc (rtx
, machine_mode
, rtx
, rtx
, rtx
*, rtx
*);
326 static opt_scalar_float_mode
arm_floatn_mode (int, bool);
327 static unsigned int arm_hard_regno_nregs (unsigned int, machine_mode
);
328 static bool arm_hard_regno_mode_ok (unsigned int, machine_mode
);
329 static bool arm_modes_tieable_p (machine_mode
, machine_mode
);
330 static HOST_WIDE_INT
arm_constant_alignment (const_tree
, HOST_WIDE_INT
);
331 static rtx_insn
*thumb1_md_asm_adjust (vec
<rtx
> &, vec
<rtx
> &,
333 vec
<const char *> &, vec
<rtx
> &,
336 /* Table of machine attributes. */
337 static const struct attribute_spec arm_attribute_table
[] =
339 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
340 affects_type_identity, handler, exclude } */
341 /* Function calls made to this symbol must be done indirectly, because
342 it may lie outside of the 26 bit addressing range of a normal function
344 { "long_call", 0, 0, false, true, true, false, NULL
, NULL
},
345 /* Whereas these functions are always known to reside within the 26 bit
347 { "short_call", 0, 0, false, true, true, false, NULL
, NULL
},
348 /* Specify the procedure call conventions for a function. */
349 { "pcs", 1, 1, false, true, true, false, arm_handle_pcs_attribute
,
351 /* Interrupt Service Routines have special prologue and epilogue requirements. */
352 { "isr", 0, 1, false, false, false, false, arm_handle_isr_attribute
,
354 { "interrupt", 0, 1, false, false, false, false, arm_handle_isr_attribute
,
356 { "naked", 0, 0, true, false, false, false,
357 arm_handle_fndecl_attribute
, NULL
},
359 /* ARM/PE has three new attributes:
361 dllexport - for exporting a function/variable that will live in a dll
362 dllimport - for importing a function/variable from a dll
364 Microsoft allows multiple declspecs in one __declspec, separating
365 them with spaces. We do NOT support this. Instead, use __declspec
368 { "dllimport", 0, 0, true, false, false, false, NULL
, NULL
},
369 { "dllexport", 0, 0, true, false, false, false, NULL
, NULL
},
370 { "interfacearm", 0, 0, true, false, false, false,
371 arm_handle_fndecl_attribute
, NULL
},
372 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
373 { "dllimport", 0, 0, false, false, false, false, handle_dll_attribute
,
375 { "dllexport", 0, 0, false, false, false, false, handle_dll_attribute
,
377 { "notshared", 0, 0, false, true, false, false,
378 arm_handle_notshared_attribute
, NULL
},
380 /* ARMv8-M Security Extensions support. */
381 { "cmse_nonsecure_entry", 0, 0, true, false, false, false,
382 arm_handle_cmse_nonsecure_entry
, NULL
},
383 { "cmse_nonsecure_call", 0, 0, true, false, false, true,
384 arm_handle_cmse_nonsecure_call
, NULL
},
385 { "Advanced SIMD type", 1, 1, false, true, false, true, NULL
, NULL
},
386 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
389 /* Initialize the GCC target structure. */
390 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
391 #undef TARGET_MERGE_DECL_ATTRIBUTES
392 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
395 #undef TARGET_CHECK_BUILTIN_CALL
396 #define TARGET_CHECK_BUILTIN_CALL arm_check_builtin_call
398 #undef TARGET_LEGITIMIZE_ADDRESS
399 #define TARGET_LEGITIMIZE_ADDRESS arm_legitimize_address
401 #undef TARGET_ATTRIBUTE_TABLE
402 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
404 #undef TARGET_INSERT_ATTRIBUTES
405 #define TARGET_INSERT_ATTRIBUTES arm_insert_attributes
407 #undef TARGET_ASM_FILE_START
408 #define TARGET_ASM_FILE_START arm_file_start
409 #undef TARGET_ASM_FILE_END
410 #define TARGET_ASM_FILE_END arm_file_end
412 #undef TARGET_ASM_ALIGNED_SI_OP
413 #define TARGET_ASM_ALIGNED_SI_OP NULL
414 #undef TARGET_ASM_INTEGER
415 #define TARGET_ASM_INTEGER arm_assemble_integer
417 #undef TARGET_PRINT_OPERAND
418 #define TARGET_PRINT_OPERAND arm_print_operand
419 #undef TARGET_PRINT_OPERAND_ADDRESS
420 #define TARGET_PRINT_OPERAND_ADDRESS arm_print_operand_address
421 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
422 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P arm_print_operand_punct_valid_p
424 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
425 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA arm_output_addr_const_extra
427 #undef TARGET_ASM_FUNCTION_PROLOGUE
428 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
430 #undef TARGET_ASM_FUNCTION_EPILOGUE
431 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
433 #undef TARGET_CAN_INLINE_P
434 #define TARGET_CAN_INLINE_P arm_can_inline_p
436 #undef TARGET_RELAYOUT_FUNCTION
437 #define TARGET_RELAYOUT_FUNCTION arm_relayout_function
439 #undef TARGET_OPTION_OVERRIDE
440 #define TARGET_OPTION_OVERRIDE arm_option_override
442 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
443 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE arm_override_options_after_change
445 #undef TARGET_OPTION_RESTORE
446 #define TARGET_OPTION_RESTORE arm_option_restore
448 #undef TARGET_OPTION_PRINT
449 #define TARGET_OPTION_PRINT arm_option_print
451 #undef TARGET_COMP_TYPE_ATTRIBUTES
452 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
454 #undef TARGET_SCHED_CAN_SPECULATE_INSN
455 #define TARGET_SCHED_CAN_SPECULATE_INSN arm_sched_can_speculate_insn
457 #undef TARGET_SCHED_MACRO_FUSION_P
458 #define TARGET_SCHED_MACRO_FUSION_P arm_macro_fusion_p
460 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
461 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
463 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
464 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
466 #undef TARGET_SCHED_ADJUST_COST
467 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
469 #undef TARGET_SET_CURRENT_FUNCTION
470 #define TARGET_SET_CURRENT_FUNCTION arm_set_current_function
472 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
473 #define TARGET_OPTION_VALID_ATTRIBUTE_P arm_valid_target_attribute_p
475 #undef TARGET_SCHED_REORDER
476 #define TARGET_SCHED_REORDER arm_sched_reorder
478 #undef TARGET_REGISTER_MOVE_COST
479 #define TARGET_REGISTER_MOVE_COST arm_register_move_cost
481 #undef TARGET_MEMORY_MOVE_COST
482 #define TARGET_MEMORY_MOVE_COST arm_memory_move_cost
484 #undef TARGET_ENCODE_SECTION_INFO
486 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
488 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
491 #undef TARGET_STRIP_NAME_ENCODING
492 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
494 #undef TARGET_ASM_INTERNAL_LABEL
495 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
497 #undef TARGET_FLOATN_MODE
498 #define TARGET_FLOATN_MODE arm_floatn_mode
500 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
501 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
503 #undef TARGET_FUNCTION_VALUE
504 #define TARGET_FUNCTION_VALUE arm_function_value
506 #undef TARGET_LIBCALL_VALUE
507 #define TARGET_LIBCALL_VALUE arm_libcall_value
509 #undef TARGET_FUNCTION_VALUE_REGNO_P
510 #define TARGET_FUNCTION_VALUE_REGNO_P arm_function_value_regno_p
512 #undef TARGET_ASM_OUTPUT_MI_THUNK
513 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
514 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
515 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK arm_can_output_mi_thunk
517 #undef TARGET_RTX_COSTS
518 #define TARGET_RTX_COSTS arm_rtx_costs
519 #undef TARGET_ADDRESS_COST
520 #define TARGET_ADDRESS_COST arm_address_cost
521 #undef TARGET_INSN_COST
522 #define TARGET_INSN_COST arm_insn_cost
524 #undef TARGET_SHIFT_TRUNCATION_MASK
525 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
526 #undef TARGET_VECTOR_MODE_SUPPORTED_P
527 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
528 #undef TARGET_ARRAY_MODE_SUPPORTED_P
529 #define TARGET_ARRAY_MODE_SUPPORTED_P arm_array_mode_supported_p
530 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
531 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arm_preferred_simd_mode
532 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES
533 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES \
534 arm_autovectorize_vector_modes
536 #undef TARGET_MACHINE_DEPENDENT_REORG
537 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
539 #undef TARGET_INIT_BUILTINS
540 #define TARGET_INIT_BUILTINS arm_init_builtins
541 #undef TARGET_EXPAND_BUILTIN
542 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
543 #undef TARGET_BUILTIN_DECL
544 #define TARGET_BUILTIN_DECL arm_builtin_decl
546 #undef TARGET_INIT_LIBFUNCS
547 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
549 #undef TARGET_PROMOTE_FUNCTION_MODE
550 #define TARGET_PROMOTE_FUNCTION_MODE arm_promote_function_mode
551 #undef TARGET_PROMOTE_PROTOTYPES
552 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
553 #undef TARGET_PASS_BY_REFERENCE
554 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
555 #undef TARGET_ARG_PARTIAL_BYTES
556 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
557 #undef TARGET_FUNCTION_ARG
558 #define TARGET_FUNCTION_ARG arm_function_arg
559 #undef TARGET_FUNCTION_ARG_ADVANCE
560 #define TARGET_FUNCTION_ARG_ADVANCE arm_function_arg_advance
561 #undef TARGET_FUNCTION_ARG_PADDING
562 #define TARGET_FUNCTION_ARG_PADDING arm_function_arg_padding
563 #undef TARGET_FUNCTION_ARG_BOUNDARY
564 #define TARGET_FUNCTION_ARG_BOUNDARY arm_function_arg_boundary
566 #undef TARGET_SETUP_INCOMING_VARARGS
567 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
569 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
570 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arm_allocate_stack_slots_for_args
572 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
573 #define TARGET_ASM_TRAMPOLINE_TEMPLATE arm_asm_trampoline_template
574 #undef TARGET_TRAMPOLINE_INIT
575 #define TARGET_TRAMPOLINE_INIT arm_trampoline_init
576 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
577 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS arm_trampoline_adjust_address
579 #undef TARGET_WARN_FUNC_RETURN
580 #define TARGET_WARN_FUNC_RETURN arm_warn_func_return
582 #undef TARGET_DEFAULT_SHORT_ENUMS
583 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
585 #undef TARGET_ALIGN_ANON_BITFIELD
586 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
588 #undef TARGET_NARROW_VOLATILE_BITFIELD
589 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
591 #undef TARGET_CXX_GUARD_TYPE
592 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
594 #undef TARGET_CXX_GUARD_MASK_BIT
595 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
597 #undef TARGET_CXX_GET_COOKIE_SIZE
598 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
600 #undef TARGET_CXX_COOKIE_HAS_SIZE
601 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
603 #undef TARGET_CXX_CDTOR_RETURNS_THIS
604 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
606 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
607 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
609 #undef TARGET_CXX_USE_AEABI_ATEXIT
610 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
612 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
613 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
614 arm_cxx_determine_class_data_visibility
616 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
617 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
619 #undef TARGET_RETURN_IN_MSB
620 #define TARGET_RETURN_IN_MSB arm_return_in_msb
622 #undef TARGET_RETURN_IN_MEMORY
623 #define TARGET_RETURN_IN_MEMORY arm_return_in_memory
625 #undef TARGET_MUST_PASS_IN_STACK
626 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
629 #undef TARGET_ASM_UNWIND_EMIT
630 #define TARGET_ASM_UNWIND_EMIT arm_unwind_emit
632 /* EABI unwinding tables use a different format for the typeinfo tables. */
633 #undef TARGET_ASM_TTYPE
634 #define TARGET_ASM_TTYPE arm_output_ttype
636 #undef TARGET_ARM_EABI_UNWINDER
637 #define TARGET_ARM_EABI_UNWINDER true
639 #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
640 #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY arm_asm_emit_except_personality
642 #endif /* ARM_UNWIND_INFO */
644 #undef TARGET_ASM_INIT_SECTIONS
645 #define TARGET_ASM_INIT_SECTIONS arm_asm_init_sections
647 #undef TARGET_DWARF_REGISTER_SPAN
648 #define TARGET_DWARF_REGISTER_SPAN arm_dwarf_register_span
650 #undef TARGET_CANNOT_COPY_INSN_P
651 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
654 #undef TARGET_HAVE_TLS
655 #define TARGET_HAVE_TLS true
658 #undef TARGET_HAVE_CONDITIONAL_EXECUTION
659 #define TARGET_HAVE_CONDITIONAL_EXECUTION arm_have_conditional_execution
661 #undef TARGET_LEGITIMATE_CONSTANT_P
662 #define TARGET_LEGITIMATE_CONSTANT_P arm_legitimate_constant_p
664 #undef TARGET_CANNOT_FORCE_CONST_MEM
665 #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem
667 #undef TARGET_MAX_ANCHOR_OFFSET
668 #define TARGET_MAX_ANCHOR_OFFSET 4095
670 /* The minimum is set such that the total size of the block
671 for a particular anchor is -4088 + 1 + 4095 bytes, which is
672 divisible by eight, ensuring natural spacing of anchors. */
673 #undef TARGET_MIN_ANCHOR_OFFSET
674 #define TARGET_MIN_ANCHOR_OFFSET -4088
676 #undef TARGET_SCHED_ISSUE_RATE
677 #define TARGET_SCHED_ISSUE_RATE arm_issue_rate
679 #undef TARGET_SCHED_VARIABLE_ISSUE
680 #define TARGET_SCHED_VARIABLE_ISSUE arm_sched_variable_issue
682 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
683 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
684 arm_first_cycle_multipass_dfa_lookahead
686 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
687 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
688 arm_first_cycle_multipass_dfa_lookahead_guard
690 #undef TARGET_MANGLE_TYPE
691 #define TARGET_MANGLE_TYPE arm_mangle_type
693 #undef TARGET_INVALID_CONVERSION
694 #define TARGET_INVALID_CONVERSION arm_invalid_conversion
696 #undef TARGET_INVALID_UNARY_OP
697 #define TARGET_INVALID_UNARY_OP arm_invalid_unary_op
699 #undef TARGET_INVALID_BINARY_OP
700 #define TARGET_INVALID_BINARY_OP arm_invalid_binary_op
702 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
703 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV arm_atomic_assign_expand_fenv
705 #undef TARGET_BUILD_BUILTIN_VA_LIST
706 #define TARGET_BUILD_BUILTIN_VA_LIST arm_build_builtin_va_list
707 #undef TARGET_EXPAND_BUILTIN_VA_START
708 #define TARGET_EXPAND_BUILTIN_VA_START arm_expand_builtin_va_start
709 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
710 #define TARGET_GIMPLIFY_VA_ARG_EXPR arm_gimplify_va_arg_expr
713 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
714 #define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel
717 #undef TARGET_LEGITIMATE_ADDRESS_P
718 #define TARGET_LEGITIMATE_ADDRESS_P arm_legitimate_address_p
720 #undef TARGET_PREFERRED_RELOAD_CLASS
721 #define TARGET_PREFERRED_RELOAD_CLASS arm_preferred_reload_class
723 #undef TARGET_PROMOTED_TYPE
724 #define TARGET_PROMOTED_TYPE arm_promoted_type
726 #undef TARGET_SCALAR_MODE_SUPPORTED_P
727 #define TARGET_SCALAR_MODE_SUPPORTED_P arm_scalar_mode_supported_p
729 #undef TARGET_COMPUTE_FRAME_LAYOUT
730 #define TARGET_COMPUTE_FRAME_LAYOUT arm_compute_frame_layout
732 #undef TARGET_FRAME_POINTER_REQUIRED
733 #define TARGET_FRAME_POINTER_REQUIRED arm_frame_pointer_required
735 #undef TARGET_CAN_ELIMINATE
736 #define TARGET_CAN_ELIMINATE arm_can_eliminate
738 #undef TARGET_CONDITIONAL_REGISTER_USAGE
739 #define TARGET_CONDITIONAL_REGISTER_USAGE arm_conditional_register_usage
741 #undef TARGET_CLASS_LIKELY_SPILLED_P
742 #define TARGET_CLASS_LIKELY_SPILLED_P arm_class_likely_spilled_p
744 #undef TARGET_VECTORIZE_BUILTINS
745 #define TARGET_VECTORIZE_BUILTINS
747 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
748 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
749 arm_builtin_vectorized_function
751 #undef TARGET_VECTOR_ALIGNMENT
752 #define TARGET_VECTOR_ALIGNMENT arm_vector_alignment
754 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
755 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
756 arm_vector_alignment_reachable
758 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
759 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
760 arm_builtin_support_vector_misalignment
762 #undef TARGET_PREFERRED_RENAME_CLASS
763 #define TARGET_PREFERRED_RENAME_CLASS \
764 arm_preferred_rename_class
766 #undef TARGET_VECTORIZE_VEC_PERM_CONST
767 #define TARGET_VECTORIZE_VEC_PERM_CONST arm_vectorize_vec_perm_const
769 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
770 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
771 arm_builtin_vectorization_cost
772 #undef TARGET_VECTORIZE_ADD_STMT_COST
773 #define TARGET_VECTORIZE_ADD_STMT_COST arm_add_stmt_cost
775 #undef TARGET_CANONICALIZE_COMPARISON
776 #define TARGET_CANONICALIZE_COMPARISON \
777 arm_canonicalize_comparison
779 #undef TARGET_ASAN_SHADOW_OFFSET
780 #define TARGET_ASAN_SHADOW_OFFSET arm_asan_shadow_offset
782 #undef MAX_INSN_PER_IT_BLOCK
783 #define MAX_INSN_PER_IT_BLOCK (arm_restrict_it ? 1 : 4)
785 #undef TARGET_CAN_USE_DOLOOP_P
786 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
788 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
789 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P arm_const_not_ok_for_debug_p
791 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
792 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
794 #undef TARGET_SCHED_FUSION_PRIORITY
795 #define TARGET_SCHED_FUSION_PRIORITY arm_sched_fusion_priority
797 #undef TARGET_ASM_FUNCTION_SECTION
798 #define TARGET_ASM_FUNCTION_SECTION arm_function_section
800 #undef TARGET_ASM_ELF_FLAGS_NUMERIC
801 #define TARGET_ASM_ELF_FLAGS_NUMERIC arm_asm_elf_flags_numeric
803 #undef TARGET_SECTION_TYPE_FLAGS
804 #define TARGET_SECTION_TYPE_FLAGS arm_elf_section_type_flags
806 #undef TARGET_EXPAND_DIVMOD_LIBFUNC
807 #define TARGET_EXPAND_DIVMOD_LIBFUNC arm_expand_divmod_libfunc
809 #undef TARGET_C_EXCESS_PRECISION
810 #define TARGET_C_EXCESS_PRECISION arm_excess_precision
812 /* Although the architecture reserves bits 0 and 1, only the former is
813 used for ARM/Thumb ISA selection in v7 and earlier versions. */
814 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
815 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 2
817 #undef TARGET_FIXED_CONDITION_CODE_REGS
818 #define TARGET_FIXED_CONDITION_CODE_REGS arm_fixed_condition_code_regs
820 #undef TARGET_HARD_REGNO_NREGS
821 #define TARGET_HARD_REGNO_NREGS arm_hard_regno_nregs
822 #undef TARGET_HARD_REGNO_MODE_OK
823 #define TARGET_HARD_REGNO_MODE_OK arm_hard_regno_mode_ok
825 #undef TARGET_MODES_TIEABLE_P
826 #define TARGET_MODES_TIEABLE_P arm_modes_tieable_p
828 #undef TARGET_CAN_CHANGE_MODE_CLASS
829 #define TARGET_CAN_CHANGE_MODE_CLASS arm_can_change_mode_class
831 #undef TARGET_CONSTANT_ALIGNMENT
832 #define TARGET_CONSTANT_ALIGNMENT arm_constant_alignment
834 #undef TARGET_INVALID_WITHIN_DOLOOP
835 #define TARGET_INVALID_WITHIN_DOLOOP arm_invalid_within_doloop
837 #undef TARGET_MD_ASM_ADJUST
838 #define TARGET_MD_ASM_ADJUST arm_md_asm_adjust
840 /* Obstack for minipool constant handling. */
841 static struct obstack minipool_obstack
;
842 static char * minipool_startobj
;
844 /* The maximum number of insns skipped which
845 will be conditionalised if possible. */
846 static int max_insns_skipped
= 5;
848 extern FILE * asm_out_file
;
850 /* True if we are currently building a constant table. */
851 int making_const_table
;
853 /* The processor for which instructions should be scheduled. */
854 enum processor_type arm_tune
= TARGET_CPU_arm_none
;
856 /* The current tuning set. */
857 const struct tune_params
*current_tune
;
859 /* Which floating point hardware to schedule for. */
862 /* Used for Thumb call_via trampolines. */
863 rtx thumb_call_via_label
[14];
864 static int thumb_call_reg_needed
;
866 /* The bits in this mask specify which instruction scheduling options should
868 unsigned int tune_flags
= 0;
870 /* The highest ARM architecture version supported by the
872 enum base_architecture arm_base_arch
= BASE_ARCH_0
;
874 /* Active target architecture and tuning. */
876 struct arm_build_target arm_active_target
;
878 /* The following are used in the arm.md file as equivalents to bits
879 in the above two flag variables. */
881 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
884 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
887 /* Nonzero if this chip supports the ARM Architecture 5T extensions. */
890 /* Nonzero if this chip supports the ARM Architecture 5TE extensions. */
893 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
896 /* Nonzero if this chip supports the ARM 6K extensions. */
899 /* Nonzero if this chip supports the ARM 6KZ extensions. */
902 /* Nonzero if instructions present in ARMv6-M can be used. */
905 /* Nonzero if this chip supports the ARM 7 extensions. */
908 /* Nonzero if this chip supports the Large Physical Address Extension. */
909 int arm_arch_lpae
= 0;
911 /* Nonzero if instructions not present in the 'M' profile can be used. */
912 int arm_arch_notm
= 0;
914 /* Nonzero if instructions present in ARMv7E-M can be used. */
917 /* Nonzero if instructions present in ARMv8 can be used. */
920 /* Nonzero if this chip supports the ARMv8.1 extensions. */
923 /* Nonzero if this chip supports the ARM Architecture 8.2 extensions. */
926 /* Nonzero if this chip supports the ARM Architecture 8.3 extensions. */
929 /* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */
931 /* Nonzero if this chip supports the ARM Architecture 8.1-M Mainline
933 int arm_arch8_1m_main
= 0;
935 /* Nonzero if this chip supports the FP16 instructions extension of ARM
937 int arm_fp16_inst
= 0;
939 /* Nonzero if this chip can benefit from load scheduling. */
940 int arm_ld_sched
= 0;
942 /* Nonzero if this chip is a StrongARM. */
943 int arm_tune_strongarm
= 0;
945 /* Nonzero if this chip supports Intel Wireless MMX technology. */
946 int arm_arch_iwmmxt
= 0;
948 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */
949 int arm_arch_iwmmxt2
= 0;
951 /* Nonzero if this chip is an XScale. */
952 int arm_arch_xscale
= 0;
954 /* Nonzero if tuning for XScale */
955 int arm_tune_xscale
= 0;
957 /* Nonzero if we want to tune for stores that access the write-buffer.
958 This typically means an ARM6 or ARM7 with MMU or MPU. */
959 int arm_tune_wbuf
= 0;
961 /* Nonzero if tuning for Cortex-A9. */
962 int arm_tune_cortex_a9
= 0;
964 /* Nonzero if we should define __THUMB_INTERWORK__ in the
966 XXX This is a bit of a hack, it's intended to help work around
967 problems in GLD which doesn't understand that armv5t code is
968 interworking clean. */
969 int arm_cpp_interwork
= 0;
971 /* Nonzero if chip supports Thumb 1. */
974 /* Nonzero if chip supports Thumb 2. */
977 /* Nonzero if chip supports integer division instruction. */
978 int arm_arch_arm_hwdiv
;
979 int arm_arch_thumb_hwdiv
;
981 /* Nonzero if chip disallows volatile memory access in IT block. */
982 int arm_arch_no_volatile_ce
;
984 /* Nonzero if we shouldn't use literal pools. */
985 bool arm_disable_literal_pool
= false;
987 /* The register number to be used for the PIC offset register. */
988 unsigned arm_pic_register
= INVALID_REGNUM
;
990 enum arm_pcs arm_pcs_default
;
992 /* For an explanation of these variables, see final_prescan_insn below. */
994 /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */
995 enum arm_cond_code arm_current_cc
;
998 int arm_target_label
;
999 /* The number of conditionally executed insns, including the current insn. */
1000 int arm_condexec_count
= 0;
1001 /* A bitmask specifying the patterns for the IT block.
1002 Zero means do not output an IT block before this insn. */
1003 int arm_condexec_mask
= 0;
1004 /* The number of bits used in arm_condexec_mask. */
1005 int arm_condexec_masklen
= 0;
1007 /* Nonzero if chip supports the ARMv8 CRC instructions. */
1008 int arm_arch_crc
= 0;
1010 /* Nonzero if chip supports the AdvSIMD Dot Product instructions. */
1011 int arm_arch_dotprod
= 0;
1013 /* Nonzero if chip supports the ARMv8-M security extensions. */
1014 int arm_arch_cmse
= 0;
1016 /* Nonzero if the core has a very small, high-latency, multiply unit. */
1017 int arm_m_profile_small_mul
= 0;
1019 /* Nonzero if chip supports the AdvSIMD I8MM instructions. */
1020 int arm_arch_i8mm
= 0;
1022 /* Nonzero if chip supports the BFloat16 instructions. */
1023 int arm_arch_bf16
= 0;
1025 /* Nonzero if chip supports the Custom Datapath Extension. */
1026 int arm_arch_cde
= 0;
1027 int arm_arch_cde_coproc
= 0;
1028 const int arm_arch_cde_coproc_bits
[] = {
1029 0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80
1032 /* The condition codes of the ARM, and the inverse function. */
1033 static const char * const arm_condition_codes
[] =
1035 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
1036 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
1039 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */
1040 int arm_regs_in_sequence
[] =
1042 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
1045 #define DEF_FP_SYSREG(reg) #reg,
1046 const char *fp_sysreg_names
[NB_FP_SYSREGS
] = {
1049 #undef DEF_FP_SYSREG
1051 #define ARM_LSL_NAME "lsl"
1052 #define streq(string1, string2) (strcmp (string1, string2) == 0)
1054 #define THUMB2_WORK_REGS \
1055 (0xff & ~((1 << THUMB_HARD_FRAME_POINTER_REGNUM) \
1056 | (1 << SP_REGNUM) \
1057 | (1 << PC_REGNUM) \
1058 | (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
1059 ? (1 << PIC_OFFSET_TABLE_REGNUM) \
1062 /* Initialization code. */
1066 enum processor_type scheduler
;
1067 unsigned int tune_flags
;
1068 const struct tune_params
*tune
;
1071 #define ARM_PREFETCH_NOT_BENEFICIAL { 0, -1, -1 }
1072 #define ARM_PREFETCH_BENEFICIAL(num_slots,l1_size,l1_line_size) \
1079 /* arm generic vectorizer costs. */
1081 struct cpu_vec_costs arm_default_vec_cost
= {
1082 1, /* scalar_stmt_cost. */
1083 1, /* scalar load_cost. */
1084 1, /* scalar_store_cost. */
1085 1, /* vec_stmt_cost. */
1086 1, /* vec_to_scalar_cost. */
1087 1, /* scalar_to_vec_cost. */
1088 1, /* vec_align_load_cost. */
1089 1, /* vec_unalign_load_cost. */
1090 1, /* vec_unalign_store_cost. */
1091 1, /* vec_store_cost. */
1092 3, /* cond_taken_branch_cost. */
1093 1, /* cond_not_taken_branch_cost. */
1096 /* Cost tables for AArch32 + AArch64 cores should go in aarch-cost-tables.h */
1097 #include "aarch-cost-tables.h"
1101 const struct cpu_cost_table cortexa9_extra_costs
=
1108 COSTS_N_INSNS (1), /* shift_reg. */
1109 COSTS_N_INSNS (1), /* arith_shift. */
1110 COSTS_N_INSNS (2), /* arith_shift_reg. */
1112 COSTS_N_INSNS (1), /* log_shift_reg. */
1113 COSTS_N_INSNS (1), /* extend. */
1114 COSTS_N_INSNS (2), /* extend_arith. */
1115 COSTS_N_INSNS (1), /* bfi. */
1116 COSTS_N_INSNS (1), /* bfx. */
1120 true /* non_exec_costs_exec. */
1125 COSTS_N_INSNS (3), /* simple. */
1126 COSTS_N_INSNS (3), /* flag_setting. */
1127 COSTS_N_INSNS (2), /* extend. */
1128 COSTS_N_INSNS (3), /* add. */
1129 COSTS_N_INSNS (2), /* extend_add. */
1130 COSTS_N_INSNS (30) /* idiv. No HW div on Cortex A9. */
1134 0, /* simple (N/A). */
1135 0, /* flag_setting (N/A). */
1136 COSTS_N_INSNS (4), /* extend. */
1138 COSTS_N_INSNS (4), /* extend_add. */
1144 COSTS_N_INSNS (2), /* load. */
1145 COSTS_N_INSNS (2), /* load_sign_extend. */
1146 COSTS_N_INSNS (2), /* ldrd. */
1147 COSTS_N_INSNS (2), /* ldm_1st. */
1148 1, /* ldm_regs_per_insn_1st. */
1149 2, /* ldm_regs_per_insn_subsequent. */
1150 COSTS_N_INSNS (5), /* loadf. */
1151 COSTS_N_INSNS (5), /* loadd. */
1152 COSTS_N_INSNS (1), /* load_unaligned. */
1153 COSTS_N_INSNS (2), /* store. */
1154 COSTS_N_INSNS (2), /* strd. */
1155 COSTS_N_INSNS (2), /* stm_1st. */
1156 1, /* stm_regs_per_insn_1st. */
1157 2, /* stm_regs_per_insn_subsequent. */
1158 COSTS_N_INSNS (1), /* storef. */
1159 COSTS_N_INSNS (1), /* stored. */
1160 COSTS_N_INSNS (1), /* store_unaligned. */
1161 COSTS_N_INSNS (1), /* loadv. */
1162 COSTS_N_INSNS (1) /* storev. */
1167 COSTS_N_INSNS (14), /* div. */
1168 COSTS_N_INSNS (4), /* mult. */
1169 COSTS_N_INSNS (7), /* mult_addsub. */
1170 COSTS_N_INSNS (30), /* fma. */
1171 COSTS_N_INSNS (3), /* addsub. */
1172 COSTS_N_INSNS (1), /* fpconst. */
1173 COSTS_N_INSNS (1), /* neg. */
1174 COSTS_N_INSNS (3), /* compare. */
1175 COSTS_N_INSNS (3), /* widen. */
1176 COSTS_N_INSNS (3), /* narrow. */
1177 COSTS_N_INSNS (3), /* toint. */
1178 COSTS_N_INSNS (3), /* fromint. */
1179 COSTS_N_INSNS (3) /* roundint. */
1183 COSTS_N_INSNS (24), /* div. */
1184 COSTS_N_INSNS (5), /* mult. */
1185 COSTS_N_INSNS (8), /* mult_addsub. */
1186 COSTS_N_INSNS (30), /* fma. */
1187 COSTS_N_INSNS (3), /* addsub. */
1188 COSTS_N_INSNS (1), /* fpconst. */
1189 COSTS_N_INSNS (1), /* neg. */
1190 COSTS_N_INSNS (3), /* compare. */
1191 COSTS_N_INSNS (3), /* widen. */
1192 COSTS_N_INSNS (3), /* narrow. */
1193 COSTS_N_INSNS (3), /* toint. */
1194 COSTS_N_INSNS (3), /* fromint. */
1195 COSTS_N_INSNS (3) /* roundint. */
1200 COSTS_N_INSNS (1), /* alu. */
1201 COSTS_N_INSNS (4) /* mult. */
1205 const struct cpu_cost_table cortexa8_extra_costs
=
1211 COSTS_N_INSNS (1), /* shift. */
1213 COSTS_N_INSNS (1), /* arith_shift. */
1214 0, /* arith_shift_reg. */
1215 COSTS_N_INSNS (1), /* log_shift. */
1216 0, /* log_shift_reg. */
1218 0, /* extend_arith. */
1224 true /* non_exec_costs_exec. */
1229 COSTS_N_INSNS (1), /* simple. */
1230 COSTS_N_INSNS (1), /* flag_setting. */
1231 COSTS_N_INSNS (1), /* extend. */
1232 COSTS_N_INSNS (1), /* add. */
1233 COSTS_N_INSNS (1), /* extend_add. */
1234 COSTS_N_INSNS (30) /* idiv. No HW div on Cortex A8. */
1238 0, /* simple (N/A). */
1239 0, /* flag_setting (N/A). */
1240 COSTS_N_INSNS (2), /* extend. */
1242 COSTS_N_INSNS (2), /* extend_add. */
1248 COSTS_N_INSNS (1), /* load. */
1249 COSTS_N_INSNS (1), /* load_sign_extend. */
1250 COSTS_N_INSNS (1), /* ldrd. */
1251 COSTS_N_INSNS (1), /* ldm_1st. */
1252 1, /* ldm_regs_per_insn_1st. */
1253 2, /* ldm_regs_per_insn_subsequent. */
1254 COSTS_N_INSNS (1), /* loadf. */
1255 COSTS_N_INSNS (1), /* loadd. */
1256 COSTS_N_INSNS (1), /* load_unaligned. */
1257 COSTS_N_INSNS (1), /* store. */
1258 COSTS_N_INSNS (1), /* strd. */
1259 COSTS_N_INSNS (1), /* stm_1st. */
1260 1, /* stm_regs_per_insn_1st. */
1261 2, /* stm_regs_per_insn_subsequent. */
1262 COSTS_N_INSNS (1), /* storef. */
1263 COSTS_N_INSNS (1), /* stored. */
1264 COSTS_N_INSNS (1), /* store_unaligned. */
1265 COSTS_N_INSNS (1), /* loadv. */
1266 COSTS_N_INSNS (1) /* storev. */
1271 COSTS_N_INSNS (36), /* div. */
1272 COSTS_N_INSNS (11), /* mult. */
1273 COSTS_N_INSNS (20), /* mult_addsub. */
1274 COSTS_N_INSNS (30), /* fma. */
1275 COSTS_N_INSNS (9), /* addsub. */
1276 COSTS_N_INSNS (3), /* fpconst. */
1277 COSTS_N_INSNS (3), /* neg. */
1278 COSTS_N_INSNS (6), /* compare. */
1279 COSTS_N_INSNS (4), /* widen. */
1280 COSTS_N_INSNS (4), /* narrow. */
1281 COSTS_N_INSNS (8), /* toint. */
1282 COSTS_N_INSNS (8), /* fromint. */
1283 COSTS_N_INSNS (8) /* roundint. */
1287 COSTS_N_INSNS (64), /* div. */
1288 COSTS_N_INSNS (16), /* mult. */
1289 COSTS_N_INSNS (25), /* mult_addsub. */
1290 COSTS_N_INSNS (30), /* fma. */
1291 COSTS_N_INSNS (9), /* addsub. */
1292 COSTS_N_INSNS (3), /* fpconst. */
1293 COSTS_N_INSNS (3), /* neg. */
1294 COSTS_N_INSNS (6), /* compare. */
1295 COSTS_N_INSNS (6), /* widen. */
1296 COSTS_N_INSNS (6), /* narrow. */
1297 COSTS_N_INSNS (8), /* toint. */
1298 COSTS_N_INSNS (8), /* fromint. */
1299 COSTS_N_INSNS (8) /* roundint. */
1304 COSTS_N_INSNS (1), /* alu. */
1305 COSTS_N_INSNS (4) /* mult. */
1309 const struct cpu_cost_table cortexa5_extra_costs
=
1315 COSTS_N_INSNS (1), /* shift. */
1316 COSTS_N_INSNS (1), /* shift_reg. */
1317 COSTS_N_INSNS (1), /* arith_shift. */
1318 COSTS_N_INSNS (1), /* arith_shift_reg. */
1319 COSTS_N_INSNS (1), /* log_shift. */
1320 COSTS_N_INSNS (1), /* log_shift_reg. */
1321 COSTS_N_INSNS (1), /* extend. */
1322 COSTS_N_INSNS (1), /* extend_arith. */
1323 COSTS_N_INSNS (1), /* bfi. */
1324 COSTS_N_INSNS (1), /* bfx. */
1325 COSTS_N_INSNS (1), /* clz. */
1326 COSTS_N_INSNS (1), /* rev. */
1328 true /* non_exec_costs_exec. */
1335 COSTS_N_INSNS (1), /* flag_setting. */
1336 COSTS_N_INSNS (1), /* extend. */
1337 COSTS_N_INSNS (1), /* add. */
1338 COSTS_N_INSNS (1), /* extend_add. */
1339 COSTS_N_INSNS (7) /* idiv. */
1343 0, /* simple (N/A). */
1344 0, /* flag_setting (N/A). */
1345 COSTS_N_INSNS (1), /* extend. */
1347 COSTS_N_INSNS (2), /* extend_add. */
1353 COSTS_N_INSNS (1), /* load. */
1354 COSTS_N_INSNS (1), /* load_sign_extend. */
1355 COSTS_N_INSNS (6), /* ldrd. */
1356 COSTS_N_INSNS (1), /* ldm_1st. */
1357 1, /* ldm_regs_per_insn_1st. */
1358 2, /* ldm_regs_per_insn_subsequent. */
1359 COSTS_N_INSNS (2), /* loadf. */
1360 COSTS_N_INSNS (4), /* loadd. */
1361 COSTS_N_INSNS (1), /* load_unaligned. */
1362 COSTS_N_INSNS (1), /* store. */
1363 COSTS_N_INSNS (3), /* strd. */
1364 COSTS_N_INSNS (1), /* stm_1st. */
1365 1, /* stm_regs_per_insn_1st. */
1366 2, /* stm_regs_per_insn_subsequent. */
1367 COSTS_N_INSNS (2), /* storef. */
1368 COSTS_N_INSNS (2), /* stored. */
1369 COSTS_N_INSNS (1), /* store_unaligned. */
1370 COSTS_N_INSNS (1), /* loadv. */
1371 COSTS_N_INSNS (1) /* storev. */
1376 COSTS_N_INSNS (15), /* div. */
1377 COSTS_N_INSNS (3), /* mult. */
1378 COSTS_N_INSNS (7), /* mult_addsub. */
1379 COSTS_N_INSNS (7), /* fma. */
1380 COSTS_N_INSNS (3), /* addsub. */
1381 COSTS_N_INSNS (3), /* fpconst. */
1382 COSTS_N_INSNS (3), /* neg. */
1383 COSTS_N_INSNS (3), /* compare. */
1384 COSTS_N_INSNS (3), /* widen. */
1385 COSTS_N_INSNS (3), /* narrow. */
1386 COSTS_N_INSNS (3), /* toint. */
1387 COSTS_N_INSNS (3), /* fromint. */
1388 COSTS_N_INSNS (3) /* roundint. */
1392 COSTS_N_INSNS (30), /* div. */
1393 COSTS_N_INSNS (6), /* mult. */
1394 COSTS_N_INSNS (10), /* mult_addsub. */
1395 COSTS_N_INSNS (7), /* fma. */
1396 COSTS_N_INSNS (3), /* addsub. */
1397 COSTS_N_INSNS (3), /* fpconst. */
1398 COSTS_N_INSNS (3), /* neg. */
1399 COSTS_N_INSNS (3), /* compare. */
1400 COSTS_N_INSNS (3), /* widen. */
1401 COSTS_N_INSNS (3), /* narrow. */
1402 COSTS_N_INSNS (3), /* toint. */
1403 COSTS_N_INSNS (3), /* fromint. */
1404 COSTS_N_INSNS (3) /* roundint. */
1409 COSTS_N_INSNS (1), /* alu. */
1410 COSTS_N_INSNS (4) /* mult. */
1415 const struct cpu_cost_table cortexa7_extra_costs
=
1421 COSTS_N_INSNS (1), /* shift. */
1422 COSTS_N_INSNS (1), /* shift_reg. */
1423 COSTS_N_INSNS (1), /* arith_shift. */
1424 COSTS_N_INSNS (1), /* arith_shift_reg. */
1425 COSTS_N_INSNS (1), /* log_shift. */
1426 COSTS_N_INSNS (1), /* log_shift_reg. */
1427 COSTS_N_INSNS (1), /* extend. */
1428 COSTS_N_INSNS (1), /* extend_arith. */
1429 COSTS_N_INSNS (1), /* bfi. */
1430 COSTS_N_INSNS (1), /* bfx. */
1431 COSTS_N_INSNS (1), /* clz. */
1432 COSTS_N_INSNS (1), /* rev. */
1434 true /* non_exec_costs_exec. */
1441 COSTS_N_INSNS (1), /* flag_setting. */
1442 COSTS_N_INSNS (1), /* extend. */
1443 COSTS_N_INSNS (1), /* add. */
1444 COSTS_N_INSNS (1), /* extend_add. */
1445 COSTS_N_INSNS (7) /* idiv. */
1449 0, /* simple (N/A). */
1450 0, /* flag_setting (N/A). */
1451 COSTS_N_INSNS (1), /* extend. */
1453 COSTS_N_INSNS (2), /* extend_add. */
1459 COSTS_N_INSNS (1), /* load. */
1460 COSTS_N_INSNS (1), /* load_sign_extend. */
1461 COSTS_N_INSNS (3), /* ldrd. */
1462 COSTS_N_INSNS (1), /* ldm_1st. */
1463 1, /* ldm_regs_per_insn_1st. */
1464 2, /* ldm_regs_per_insn_subsequent. */
1465 COSTS_N_INSNS (2), /* loadf. */
1466 COSTS_N_INSNS (2), /* loadd. */
1467 COSTS_N_INSNS (1), /* load_unaligned. */
1468 COSTS_N_INSNS (1), /* store. */
1469 COSTS_N_INSNS (3), /* strd. */
1470 COSTS_N_INSNS (1), /* stm_1st. */
1471 1, /* stm_regs_per_insn_1st. */
1472 2, /* stm_regs_per_insn_subsequent. */
1473 COSTS_N_INSNS (2), /* storef. */
1474 COSTS_N_INSNS (2), /* stored. */
1475 COSTS_N_INSNS (1), /* store_unaligned. */
1476 COSTS_N_INSNS (1), /* loadv. */
1477 COSTS_N_INSNS (1) /* storev. */
1482 COSTS_N_INSNS (15), /* div. */
1483 COSTS_N_INSNS (3), /* mult. */
1484 COSTS_N_INSNS (7), /* mult_addsub. */
1485 COSTS_N_INSNS (7), /* fma. */
1486 COSTS_N_INSNS (3), /* addsub. */
1487 COSTS_N_INSNS (3), /* fpconst. */
1488 COSTS_N_INSNS (3), /* neg. */
1489 COSTS_N_INSNS (3), /* compare. */
1490 COSTS_N_INSNS (3), /* widen. */
1491 COSTS_N_INSNS (3), /* narrow. */
1492 COSTS_N_INSNS (3), /* toint. */
1493 COSTS_N_INSNS (3), /* fromint. */
1494 COSTS_N_INSNS (3) /* roundint. */
1498 COSTS_N_INSNS (30), /* div. */
1499 COSTS_N_INSNS (6), /* mult. */
1500 COSTS_N_INSNS (10), /* mult_addsub. */
1501 COSTS_N_INSNS (7), /* fma. */
1502 COSTS_N_INSNS (3), /* addsub. */
1503 COSTS_N_INSNS (3), /* fpconst. */
1504 COSTS_N_INSNS (3), /* neg. */
1505 COSTS_N_INSNS (3), /* compare. */
1506 COSTS_N_INSNS (3), /* widen. */
1507 COSTS_N_INSNS (3), /* narrow. */
1508 COSTS_N_INSNS (3), /* toint. */
1509 COSTS_N_INSNS (3), /* fromint. */
1510 COSTS_N_INSNS (3) /* roundint. */
1515 COSTS_N_INSNS (1), /* alu. */
1516 COSTS_N_INSNS (4) /* mult. */
1520 const struct cpu_cost_table cortexa12_extra_costs
=
1527 COSTS_N_INSNS (1), /* shift_reg. */
1528 COSTS_N_INSNS (1), /* arith_shift. */
1529 COSTS_N_INSNS (1), /* arith_shift_reg. */
1530 COSTS_N_INSNS (1), /* log_shift. */
1531 COSTS_N_INSNS (1), /* log_shift_reg. */
1533 COSTS_N_INSNS (1), /* extend_arith. */
1535 COSTS_N_INSNS (1), /* bfx. */
1536 COSTS_N_INSNS (1), /* clz. */
1537 COSTS_N_INSNS (1), /* rev. */
1539 true /* non_exec_costs_exec. */
1544 COSTS_N_INSNS (2), /* simple. */
1545 COSTS_N_INSNS (3), /* flag_setting. */
1546 COSTS_N_INSNS (2), /* extend. */
1547 COSTS_N_INSNS (3), /* add. */
1548 COSTS_N_INSNS (2), /* extend_add. */
1549 COSTS_N_INSNS (18) /* idiv. */
1553 0, /* simple (N/A). */
1554 0, /* flag_setting (N/A). */
1555 COSTS_N_INSNS (3), /* extend. */
1557 COSTS_N_INSNS (3), /* extend_add. */
1563 COSTS_N_INSNS (3), /* load. */
1564 COSTS_N_INSNS (3), /* load_sign_extend. */
1565 COSTS_N_INSNS (3), /* ldrd. */
1566 COSTS_N_INSNS (3), /* ldm_1st. */
1567 1, /* ldm_regs_per_insn_1st. */
1568 2, /* ldm_regs_per_insn_subsequent. */
1569 COSTS_N_INSNS (3), /* loadf. */
1570 COSTS_N_INSNS (3), /* loadd. */
1571 0, /* load_unaligned. */
1575 1, /* stm_regs_per_insn_1st. */
1576 2, /* stm_regs_per_insn_subsequent. */
1577 COSTS_N_INSNS (2), /* storef. */
1578 COSTS_N_INSNS (2), /* stored. */
1579 0, /* store_unaligned. */
1580 COSTS_N_INSNS (1), /* loadv. */
1581 COSTS_N_INSNS (1) /* storev. */
1586 COSTS_N_INSNS (17), /* div. */
1587 COSTS_N_INSNS (4), /* mult. */
1588 COSTS_N_INSNS (8), /* mult_addsub. */
1589 COSTS_N_INSNS (8), /* fma. */
1590 COSTS_N_INSNS (4), /* addsub. */
1591 COSTS_N_INSNS (2), /* fpconst. */
1592 COSTS_N_INSNS (2), /* neg. */
1593 COSTS_N_INSNS (2), /* compare. */
1594 COSTS_N_INSNS (4), /* widen. */
1595 COSTS_N_INSNS (4), /* narrow. */
1596 COSTS_N_INSNS (4), /* toint. */
1597 COSTS_N_INSNS (4), /* fromint. */
1598 COSTS_N_INSNS (4) /* roundint. */
1602 COSTS_N_INSNS (31), /* div. */
1603 COSTS_N_INSNS (4), /* mult. */
1604 COSTS_N_INSNS (8), /* mult_addsub. */
1605 COSTS_N_INSNS (8), /* fma. */
1606 COSTS_N_INSNS (4), /* addsub. */
1607 COSTS_N_INSNS (2), /* fpconst. */
1608 COSTS_N_INSNS (2), /* neg. */
1609 COSTS_N_INSNS (2), /* compare. */
1610 COSTS_N_INSNS (4), /* widen. */
1611 COSTS_N_INSNS (4), /* narrow. */
1612 COSTS_N_INSNS (4), /* toint. */
1613 COSTS_N_INSNS (4), /* fromint. */
1614 COSTS_N_INSNS (4) /* roundint. */
1619 COSTS_N_INSNS (1), /* alu. */
1620 COSTS_N_INSNS (4) /* mult. */
1624 const struct cpu_cost_table cortexa15_extra_costs
=
1632 COSTS_N_INSNS (1), /* arith_shift. */
1633 COSTS_N_INSNS (1), /* arith_shift_reg. */
1634 COSTS_N_INSNS (1), /* log_shift. */
1635 COSTS_N_INSNS (1), /* log_shift_reg. */
1637 COSTS_N_INSNS (1), /* extend_arith. */
1638 COSTS_N_INSNS (1), /* bfi. */
1643 true /* non_exec_costs_exec. */
1648 COSTS_N_INSNS (2), /* simple. */
1649 COSTS_N_INSNS (3), /* flag_setting. */
1650 COSTS_N_INSNS (2), /* extend. */
1651 COSTS_N_INSNS (2), /* add. */
1652 COSTS_N_INSNS (2), /* extend_add. */
1653 COSTS_N_INSNS (18) /* idiv. */
1657 0, /* simple (N/A). */
1658 0, /* flag_setting (N/A). */
1659 COSTS_N_INSNS (3), /* extend. */
1661 COSTS_N_INSNS (3), /* extend_add. */
1667 COSTS_N_INSNS (3), /* load. */
1668 COSTS_N_INSNS (3), /* load_sign_extend. */
1669 COSTS_N_INSNS (3), /* ldrd. */
1670 COSTS_N_INSNS (4), /* ldm_1st. */
1671 1, /* ldm_regs_per_insn_1st. */
1672 2, /* ldm_regs_per_insn_subsequent. */
1673 COSTS_N_INSNS (4), /* loadf. */
1674 COSTS_N_INSNS (4), /* loadd. */
1675 0, /* load_unaligned. */
1678 COSTS_N_INSNS (1), /* stm_1st. */
1679 1, /* stm_regs_per_insn_1st. */
1680 2, /* stm_regs_per_insn_subsequent. */
1683 0, /* store_unaligned. */
1684 COSTS_N_INSNS (1), /* loadv. */
1685 COSTS_N_INSNS (1) /* storev. */
1690 COSTS_N_INSNS (17), /* div. */
1691 COSTS_N_INSNS (4), /* mult. */
1692 COSTS_N_INSNS (8), /* mult_addsub. */
1693 COSTS_N_INSNS (8), /* fma. */
1694 COSTS_N_INSNS (4), /* addsub. */
1695 COSTS_N_INSNS (2), /* fpconst. */
1696 COSTS_N_INSNS (2), /* neg. */
1697 COSTS_N_INSNS (5), /* compare. */
1698 COSTS_N_INSNS (4), /* widen. */
1699 COSTS_N_INSNS (4), /* narrow. */
1700 COSTS_N_INSNS (4), /* toint. */
1701 COSTS_N_INSNS (4), /* fromint. */
1702 COSTS_N_INSNS (4) /* roundint. */
1706 COSTS_N_INSNS (31), /* div. */
1707 COSTS_N_INSNS (4), /* mult. */
1708 COSTS_N_INSNS (8), /* mult_addsub. */
1709 COSTS_N_INSNS (8), /* fma. */
1710 COSTS_N_INSNS (4), /* addsub. */
1711 COSTS_N_INSNS (2), /* fpconst. */
1712 COSTS_N_INSNS (2), /* neg. */
1713 COSTS_N_INSNS (2), /* compare. */
1714 COSTS_N_INSNS (4), /* widen. */
1715 COSTS_N_INSNS (4), /* narrow. */
1716 COSTS_N_INSNS (4), /* toint. */
1717 COSTS_N_INSNS (4), /* fromint. */
1718 COSTS_N_INSNS (4) /* roundint. */
1723 COSTS_N_INSNS (1), /* alu. */
1724 COSTS_N_INSNS (4) /* mult. */
1728 const struct cpu_cost_table v7m_extra_costs
=
1736 0, /* arith_shift. */
1737 COSTS_N_INSNS (1), /* arith_shift_reg. */
1739 COSTS_N_INSNS (1), /* log_shift_reg. */
1741 COSTS_N_INSNS (1), /* extend_arith. */
1746 COSTS_N_INSNS (1), /* non_exec. */
1747 false /* non_exec_costs_exec. */
1752 COSTS_N_INSNS (1), /* simple. */
1753 COSTS_N_INSNS (1), /* flag_setting. */
1754 COSTS_N_INSNS (2), /* extend. */
1755 COSTS_N_INSNS (1), /* add. */
1756 COSTS_N_INSNS (3), /* extend_add. */
1757 COSTS_N_INSNS (8) /* idiv. */
1761 0, /* simple (N/A). */
1762 0, /* flag_setting (N/A). */
1763 COSTS_N_INSNS (2), /* extend. */
1765 COSTS_N_INSNS (3), /* extend_add. */
1771 COSTS_N_INSNS (2), /* load. */
1772 0, /* load_sign_extend. */
1773 COSTS_N_INSNS (3), /* ldrd. */
1774 COSTS_N_INSNS (2), /* ldm_1st. */
1775 1, /* ldm_regs_per_insn_1st. */
1776 1, /* ldm_regs_per_insn_subsequent. */
1777 COSTS_N_INSNS (2), /* loadf. */
1778 COSTS_N_INSNS (3), /* loadd. */
1779 COSTS_N_INSNS (1), /* load_unaligned. */
1780 COSTS_N_INSNS (2), /* store. */
1781 COSTS_N_INSNS (3), /* strd. */
1782 COSTS_N_INSNS (2), /* stm_1st. */
1783 1, /* stm_regs_per_insn_1st. */
1784 1, /* stm_regs_per_insn_subsequent. */
1785 COSTS_N_INSNS (2), /* storef. */
1786 COSTS_N_INSNS (3), /* stored. */
1787 COSTS_N_INSNS (1), /* store_unaligned. */
1788 COSTS_N_INSNS (1), /* loadv. */
1789 COSTS_N_INSNS (1) /* storev. */
1794 COSTS_N_INSNS (7), /* div. */
1795 COSTS_N_INSNS (2), /* mult. */
1796 COSTS_N_INSNS (5), /* mult_addsub. */
1797 COSTS_N_INSNS (3), /* fma. */
1798 COSTS_N_INSNS (1), /* addsub. */
1810 COSTS_N_INSNS (15), /* div. */
1811 COSTS_N_INSNS (5), /* mult. */
1812 COSTS_N_INSNS (7), /* mult_addsub. */
1813 COSTS_N_INSNS (7), /* fma. */
1814 COSTS_N_INSNS (3), /* addsub. */
1827 COSTS_N_INSNS (1), /* alu. */
1828 COSTS_N_INSNS (4) /* mult. */
1832 const struct addr_mode_cost_table generic_addr_mode_costs
=
1836 COSTS_N_INSNS (0), /* AMO_DEFAULT. */
1837 COSTS_N_INSNS (0), /* AMO_NO_WB. */
1838 COSTS_N_INSNS (0) /* AMO_WB. */
1842 COSTS_N_INSNS (0), /* AMO_DEFAULT. */
1843 COSTS_N_INSNS (0), /* AMO_NO_WB. */
1844 COSTS_N_INSNS (0) /* AMO_WB. */
1848 COSTS_N_INSNS (0), /* AMO_DEFAULT. */
1849 COSTS_N_INSNS (0), /* AMO_NO_WB. */
1850 COSTS_N_INSNS (0) /* AMO_WB. */
1854 const struct tune_params arm_slowmul_tune
=
1856 &generic_extra_costs
, /* Insn extra costs. */
1857 &generic_addr_mode_costs
, /* Addressing mode costs. */
1858 NULL
, /* Sched adj cost. */
1859 arm_default_branch_cost
,
1860 &arm_default_vec_cost
,
1861 3, /* Constant limit. */
1862 5, /* Max cond insns. */
1863 8, /* Memset max inline. */
1864 1, /* Issue rate. */
1865 ARM_PREFETCH_NOT_BENEFICIAL
,
1866 tune_params::PREF_CONST_POOL_TRUE
,
1867 tune_params::PREF_LDRD_FALSE
,
1868 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
1869 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
1870 tune_params::DISPARAGE_FLAGS_NEITHER
,
1871 tune_params::PREF_NEON_STRINGOPS_FALSE
,
1872 tune_params::FUSE_NOTHING
,
1873 tune_params::SCHED_AUTOPREF_OFF
1876 const struct tune_params arm_fastmul_tune
=
1878 &generic_extra_costs
, /* Insn extra costs. */
1879 &generic_addr_mode_costs
, /* Addressing mode costs. */
1880 NULL
, /* Sched adj cost. */
1881 arm_default_branch_cost
,
1882 &arm_default_vec_cost
,
1883 1, /* Constant limit. */
1884 5, /* Max cond insns. */
1885 8, /* Memset max inline. */
1886 1, /* Issue rate. */
1887 ARM_PREFETCH_NOT_BENEFICIAL
,
1888 tune_params::PREF_CONST_POOL_TRUE
,
1889 tune_params::PREF_LDRD_FALSE
,
1890 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
1891 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
1892 tune_params::DISPARAGE_FLAGS_NEITHER
,
1893 tune_params::PREF_NEON_STRINGOPS_FALSE
,
1894 tune_params::FUSE_NOTHING
,
1895 tune_params::SCHED_AUTOPREF_OFF
1898 /* StrongARM has early execution of branches, so a sequence that is worth
1899 skipping is shorter. Set max_insns_skipped to a lower value. */
1901 const struct tune_params arm_strongarm_tune
=
1903 &generic_extra_costs
, /* Insn extra costs. */
1904 &generic_addr_mode_costs
, /* Addressing mode costs. */
1905 NULL
, /* Sched adj cost. */
1906 arm_default_branch_cost
,
1907 &arm_default_vec_cost
,
1908 1, /* Constant limit. */
1909 3, /* Max cond insns. */
1910 8, /* Memset max inline. */
1911 1, /* Issue rate. */
1912 ARM_PREFETCH_NOT_BENEFICIAL
,
1913 tune_params::PREF_CONST_POOL_TRUE
,
1914 tune_params::PREF_LDRD_FALSE
,
1915 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
1916 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
1917 tune_params::DISPARAGE_FLAGS_NEITHER
,
1918 tune_params::PREF_NEON_STRINGOPS_FALSE
,
1919 tune_params::FUSE_NOTHING
,
1920 tune_params::SCHED_AUTOPREF_OFF
1923 const struct tune_params arm_xscale_tune
=
1925 &generic_extra_costs
, /* Insn extra costs. */
1926 &generic_addr_mode_costs
, /* Addressing mode costs. */
1927 xscale_sched_adjust_cost
,
1928 arm_default_branch_cost
,
1929 &arm_default_vec_cost
,
1930 2, /* Constant limit. */
1931 3, /* Max cond insns. */
1932 8, /* Memset max inline. */
1933 1, /* Issue rate. */
1934 ARM_PREFETCH_NOT_BENEFICIAL
,
1935 tune_params::PREF_CONST_POOL_TRUE
,
1936 tune_params::PREF_LDRD_FALSE
,
1937 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
1938 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
1939 tune_params::DISPARAGE_FLAGS_NEITHER
,
1940 tune_params::PREF_NEON_STRINGOPS_FALSE
,
1941 tune_params::FUSE_NOTHING
,
1942 tune_params::SCHED_AUTOPREF_OFF
1945 const struct tune_params arm_9e_tune
=
1947 &generic_extra_costs
, /* Insn extra costs. */
1948 &generic_addr_mode_costs
, /* Addressing mode costs. */
1949 NULL
, /* Sched adj cost. */
1950 arm_default_branch_cost
,
1951 &arm_default_vec_cost
,
1952 1, /* Constant limit. */
1953 5, /* Max cond insns. */
1954 8, /* Memset max inline. */
1955 1, /* Issue rate. */
1956 ARM_PREFETCH_NOT_BENEFICIAL
,
1957 tune_params::PREF_CONST_POOL_TRUE
,
1958 tune_params::PREF_LDRD_FALSE
,
1959 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
1960 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
1961 tune_params::DISPARAGE_FLAGS_NEITHER
,
1962 tune_params::PREF_NEON_STRINGOPS_FALSE
,
1963 tune_params::FUSE_NOTHING
,
1964 tune_params::SCHED_AUTOPREF_OFF
1967 const struct tune_params arm_marvell_pj4_tune
=
1969 &generic_extra_costs
, /* Insn extra costs. */
1970 &generic_addr_mode_costs
, /* Addressing mode costs. */
1971 NULL
, /* Sched adj cost. */
1972 arm_default_branch_cost
,
1973 &arm_default_vec_cost
,
1974 1, /* Constant limit. */
1975 5, /* Max cond insns. */
1976 8, /* Memset max inline. */
1977 2, /* Issue rate. */
1978 ARM_PREFETCH_NOT_BENEFICIAL
,
1979 tune_params::PREF_CONST_POOL_TRUE
,
1980 tune_params::PREF_LDRD_FALSE
,
1981 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
1982 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
1983 tune_params::DISPARAGE_FLAGS_NEITHER
,
1984 tune_params::PREF_NEON_STRINGOPS_FALSE
,
1985 tune_params::FUSE_NOTHING
,
1986 tune_params::SCHED_AUTOPREF_OFF
1989 const struct tune_params arm_v6t2_tune
=
1991 &generic_extra_costs
, /* Insn extra costs. */
1992 &generic_addr_mode_costs
, /* Addressing mode costs. */
1993 NULL
, /* Sched adj cost. */
1994 arm_default_branch_cost
,
1995 &arm_default_vec_cost
,
1996 1, /* Constant limit. */
1997 5, /* Max cond insns. */
1998 8, /* Memset max inline. */
1999 1, /* Issue rate. */
2000 ARM_PREFETCH_NOT_BENEFICIAL
,
2001 tune_params::PREF_CONST_POOL_FALSE
,
2002 tune_params::PREF_LDRD_FALSE
,
2003 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
2004 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
2005 tune_params::DISPARAGE_FLAGS_NEITHER
,
2006 tune_params::PREF_NEON_STRINGOPS_FALSE
,
2007 tune_params::FUSE_NOTHING
,
2008 tune_params::SCHED_AUTOPREF_OFF
2012 /* Generic Cortex tuning. Use more specific tunings if appropriate. */
2013 const struct tune_params arm_cortex_tune
=
2015 &generic_extra_costs
,
2016 &generic_addr_mode_costs
, /* Addressing mode costs. */
2017 NULL
, /* Sched adj cost. */
2018 arm_default_branch_cost
,
2019 &arm_default_vec_cost
,
2020 1, /* Constant limit. */
2021 5, /* Max cond insns. */
2022 8, /* Memset max inline. */
2023 2, /* Issue rate. */
2024 ARM_PREFETCH_NOT_BENEFICIAL
,
2025 tune_params::PREF_CONST_POOL_FALSE
,
2026 tune_params::PREF_LDRD_FALSE
,
2027 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
2028 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
2029 tune_params::DISPARAGE_FLAGS_NEITHER
,
2030 tune_params::PREF_NEON_STRINGOPS_FALSE
,
2031 tune_params::FUSE_NOTHING
,
2032 tune_params::SCHED_AUTOPREF_OFF
2035 const struct tune_params arm_cortex_a8_tune
=
2037 &cortexa8_extra_costs
,
2038 &generic_addr_mode_costs
, /* Addressing mode costs. */
2039 NULL
, /* Sched adj cost. */
2040 arm_default_branch_cost
,
2041 &arm_default_vec_cost
,
2042 1, /* Constant limit. */
2043 5, /* Max cond insns. */
2044 8, /* Memset max inline. */
2045 2, /* Issue rate. */
2046 ARM_PREFETCH_NOT_BENEFICIAL
,
2047 tune_params::PREF_CONST_POOL_FALSE
,
2048 tune_params::PREF_LDRD_FALSE
,
2049 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
2050 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
2051 tune_params::DISPARAGE_FLAGS_NEITHER
,
2052 tune_params::PREF_NEON_STRINGOPS_TRUE
,
2053 tune_params::FUSE_NOTHING
,
2054 tune_params::SCHED_AUTOPREF_OFF
2057 const struct tune_params arm_cortex_a7_tune
=
2059 &cortexa7_extra_costs
,
2060 &generic_addr_mode_costs
, /* Addressing mode costs. */
2061 NULL
, /* Sched adj cost. */
2062 arm_default_branch_cost
,
2063 &arm_default_vec_cost
,
2064 1, /* Constant limit. */
2065 5, /* Max cond insns. */
2066 8, /* Memset max inline. */
2067 2, /* Issue rate. */
2068 ARM_PREFETCH_NOT_BENEFICIAL
,
2069 tune_params::PREF_CONST_POOL_FALSE
,
2070 tune_params::PREF_LDRD_FALSE
,
2071 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
2072 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
2073 tune_params::DISPARAGE_FLAGS_NEITHER
,
2074 tune_params::PREF_NEON_STRINGOPS_TRUE
,
2075 tune_params::FUSE_NOTHING
,
2076 tune_params::SCHED_AUTOPREF_OFF
2079 const struct tune_params arm_cortex_a15_tune
=
2081 &cortexa15_extra_costs
,
2082 &generic_addr_mode_costs
, /* Addressing mode costs. */
2083 NULL
, /* Sched adj cost. */
2084 arm_default_branch_cost
,
2085 &arm_default_vec_cost
,
2086 1, /* Constant limit. */
2087 2, /* Max cond insns. */
2088 8, /* Memset max inline. */
2089 3, /* Issue rate. */
2090 ARM_PREFETCH_NOT_BENEFICIAL
,
2091 tune_params::PREF_CONST_POOL_FALSE
,
2092 tune_params::PREF_LDRD_TRUE
,
2093 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
2094 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
2095 tune_params::DISPARAGE_FLAGS_ALL
,
2096 tune_params::PREF_NEON_STRINGOPS_TRUE
,
2097 tune_params::FUSE_NOTHING
,
2098 tune_params::SCHED_AUTOPREF_FULL
2101 const struct tune_params arm_cortex_a35_tune
=
2103 &cortexa53_extra_costs
,
2104 &generic_addr_mode_costs
, /* Addressing mode costs. */
2105 NULL
, /* Sched adj cost. */
2106 arm_default_branch_cost
,
2107 &arm_default_vec_cost
,
2108 1, /* Constant limit. */
2109 5, /* Max cond insns. */
2110 8, /* Memset max inline. */
2111 1, /* Issue rate. */
2112 ARM_PREFETCH_NOT_BENEFICIAL
,
2113 tune_params::PREF_CONST_POOL_FALSE
,
2114 tune_params::PREF_LDRD_FALSE
,
2115 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
2116 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
2117 tune_params::DISPARAGE_FLAGS_NEITHER
,
2118 tune_params::PREF_NEON_STRINGOPS_TRUE
,
2119 FUSE_OPS (tune_params::FUSE_MOVW_MOVT
),
2120 tune_params::SCHED_AUTOPREF_OFF
2123 const struct tune_params arm_cortex_a53_tune
=
2125 &cortexa53_extra_costs
,
2126 &generic_addr_mode_costs
, /* Addressing mode costs. */
2127 NULL
, /* Sched adj cost. */
2128 arm_default_branch_cost
,
2129 &arm_default_vec_cost
,
2130 1, /* Constant limit. */
2131 5, /* Max cond insns. */
2132 8, /* Memset max inline. */
2133 2, /* Issue rate. */
2134 ARM_PREFETCH_NOT_BENEFICIAL
,
2135 tune_params::PREF_CONST_POOL_FALSE
,
2136 tune_params::PREF_LDRD_FALSE
,
2137 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
2138 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
2139 tune_params::DISPARAGE_FLAGS_NEITHER
,
2140 tune_params::PREF_NEON_STRINGOPS_TRUE
,
2141 FUSE_OPS (tune_params::FUSE_MOVW_MOVT
| tune_params::FUSE_AES_AESMC
),
2142 tune_params::SCHED_AUTOPREF_OFF
2145 const struct tune_params arm_cortex_a57_tune
=
2147 &cortexa57_extra_costs
,
2148 &generic_addr_mode_costs
, /* addressing mode costs */
2149 NULL
, /* Sched adj cost. */
2150 arm_default_branch_cost
,
2151 &arm_default_vec_cost
,
2152 1, /* Constant limit. */
2153 2, /* Max cond insns. */
2154 8, /* Memset max inline. */
2155 3, /* Issue rate. */
2156 ARM_PREFETCH_NOT_BENEFICIAL
,
2157 tune_params::PREF_CONST_POOL_FALSE
,
2158 tune_params::PREF_LDRD_TRUE
,
2159 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
2160 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
2161 tune_params::DISPARAGE_FLAGS_ALL
,
2162 tune_params::PREF_NEON_STRINGOPS_TRUE
,
2163 FUSE_OPS (tune_params::FUSE_MOVW_MOVT
| tune_params::FUSE_AES_AESMC
),
2164 tune_params::SCHED_AUTOPREF_FULL
2167 const struct tune_params arm_exynosm1_tune
=
2169 &exynosm1_extra_costs
,
2170 &generic_addr_mode_costs
, /* Addressing mode costs. */
2171 NULL
, /* Sched adj cost. */
2172 arm_default_branch_cost
,
2173 &arm_default_vec_cost
,
2174 1, /* Constant limit. */
2175 2, /* Max cond insns. */
2176 8, /* Memset max inline. */
2177 3, /* Issue rate. */
2178 ARM_PREFETCH_NOT_BENEFICIAL
,
2179 tune_params::PREF_CONST_POOL_FALSE
,
2180 tune_params::PREF_LDRD_TRUE
,
2181 tune_params::LOG_OP_NON_SHORT_CIRCUIT_FALSE
, /* Thumb. */
2182 tune_params::LOG_OP_NON_SHORT_CIRCUIT_FALSE
, /* ARM. */
2183 tune_params::DISPARAGE_FLAGS_ALL
,
2184 tune_params::PREF_NEON_STRINGOPS_TRUE
,
2185 tune_params::FUSE_NOTHING
,
2186 tune_params::SCHED_AUTOPREF_OFF
2189 const struct tune_params arm_xgene1_tune
=
2191 &xgene1_extra_costs
,
2192 &generic_addr_mode_costs
, /* Addressing mode costs. */
2193 NULL
, /* Sched adj cost. */
2194 arm_default_branch_cost
,
2195 &arm_default_vec_cost
,
2196 1, /* Constant limit. */
2197 2, /* Max cond insns. */
2198 32, /* Memset max inline. */
2199 4, /* Issue rate. */
2200 ARM_PREFETCH_NOT_BENEFICIAL
,
2201 tune_params::PREF_CONST_POOL_FALSE
,
2202 tune_params::PREF_LDRD_TRUE
,
2203 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
2204 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
2205 tune_params::DISPARAGE_FLAGS_ALL
,
2206 tune_params::PREF_NEON_STRINGOPS_FALSE
,
2207 tune_params::FUSE_NOTHING
,
2208 tune_params::SCHED_AUTOPREF_OFF
2211 /* Branches can be dual-issued on Cortex-A5, so conditional execution is
2212 less appealing. Set max_insns_skipped to a low value. */
2214 const struct tune_params arm_cortex_a5_tune
=
2216 &cortexa5_extra_costs
,
2217 &generic_addr_mode_costs
, /* Addressing mode costs. */
2218 NULL
, /* Sched adj cost. */
2219 arm_cortex_a5_branch_cost
,
2220 &arm_default_vec_cost
,
2221 1, /* Constant limit. */
2222 1, /* Max cond insns. */
2223 8, /* Memset max inline. */
2224 2, /* Issue rate. */
2225 ARM_PREFETCH_NOT_BENEFICIAL
,
2226 tune_params::PREF_CONST_POOL_FALSE
,
2227 tune_params::PREF_LDRD_FALSE
,
2228 tune_params::LOG_OP_NON_SHORT_CIRCUIT_FALSE
, /* Thumb. */
2229 tune_params::LOG_OP_NON_SHORT_CIRCUIT_FALSE
, /* ARM. */
2230 tune_params::DISPARAGE_FLAGS_NEITHER
,
2231 tune_params::PREF_NEON_STRINGOPS_TRUE
,
2232 tune_params::FUSE_NOTHING
,
2233 tune_params::SCHED_AUTOPREF_OFF
2236 const struct tune_params arm_cortex_a9_tune
=
2238 &cortexa9_extra_costs
,
2239 &generic_addr_mode_costs
, /* Addressing mode costs. */
2240 cortex_a9_sched_adjust_cost
,
2241 arm_default_branch_cost
,
2242 &arm_default_vec_cost
,
2243 1, /* Constant limit. */
2244 5, /* Max cond insns. */
2245 8, /* Memset max inline. */
2246 2, /* Issue rate. */
2247 ARM_PREFETCH_BENEFICIAL(4,32,32),
2248 tune_params::PREF_CONST_POOL_FALSE
,
2249 tune_params::PREF_LDRD_FALSE
,
2250 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
2251 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
2252 tune_params::DISPARAGE_FLAGS_NEITHER
,
2253 tune_params::PREF_NEON_STRINGOPS_FALSE
,
2254 tune_params::FUSE_NOTHING
,
2255 tune_params::SCHED_AUTOPREF_OFF
2258 const struct tune_params arm_cortex_a12_tune
=
2260 &cortexa12_extra_costs
,
2261 &generic_addr_mode_costs
, /* Addressing mode costs. */
2262 NULL
, /* Sched adj cost. */
2263 arm_default_branch_cost
,
2264 &arm_default_vec_cost
, /* Vectorizer costs. */
2265 1, /* Constant limit. */
2266 2, /* Max cond insns. */
2267 8, /* Memset max inline. */
2268 2, /* Issue rate. */
2269 ARM_PREFETCH_NOT_BENEFICIAL
,
2270 tune_params::PREF_CONST_POOL_FALSE
,
2271 tune_params::PREF_LDRD_TRUE
,
2272 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
2273 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
2274 tune_params::DISPARAGE_FLAGS_ALL
,
2275 tune_params::PREF_NEON_STRINGOPS_TRUE
,
2276 FUSE_OPS (tune_params::FUSE_MOVW_MOVT
),
2277 tune_params::SCHED_AUTOPREF_OFF
2280 const struct tune_params arm_cortex_a73_tune
=
2282 &cortexa57_extra_costs
,
2283 &generic_addr_mode_costs
, /* Addressing mode costs. */
2284 NULL
, /* Sched adj cost. */
2285 arm_default_branch_cost
,
2286 &arm_default_vec_cost
, /* Vectorizer costs. */
2287 1, /* Constant limit. */
2288 2, /* Max cond insns. */
2289 8, /* Memset max inline. */
2290 2, /* Issue rate. */
2291 ARM_PREFETCH_NOT_BENEFICIAL
,
2292 tune_params::PREF_CONST_POOL_FALSE
,
2293 tune_params::PREF_LDRD_TRUE
,
2294 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
2295 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
2296 tune_params::DISPARAGE_FLAGS_ALL
,
2297 tune_params::PREF_NEON_STRINGOPS_TRUE
,
2298 FUSE_OPS (tune_params::FUSE_AES_AESMC
| tune_params::FUSE_MOVW_MOVT
),
2299 tune_params::SCHED_AUTOPREF_FULL
2302 /* armv7m tuning. On Cortex-M4 cores for example, MOVW/MOVT take a single
2303 cycle to execute each. An LDR from the constant pool also takes two cycles
2304 to execute, but mildly increases pipelining opportunity (consecutive
2305 loads/stores can be pipelined together, saving one cycle), and may also
2306 improve icache utilisation. Hence we prefer the constant pool for such
2309 const struct tune_params arm_v7m_tune
=
2312 &generic_addr_mode_costs
, /* Addressing mode costs. */
2313 NULL
, /* Sched adj cost. */
2314 arm_cortex_m_branch_cost
,
2315 &arm_default_vec_cost
,
2316 1, /* Constant limit. */
2317 2, /* Max cond insns. */
2318 8, /* Memset max inline. */
2319 1, /* Issue rate. */
2320 ARM_PREFETCH_NOT_BENEFICIAL
,
2321 tune_params::PREF_CONST_POOL_TRUE
,
2322 tune_params::PREF_LDRD_FALSE
,
2323 tune_params::LOG_OP_NON_SHORT_CIRCUIT_FALSE
, /* Thumb. */
2324 tune_params::LOG_OP_NON_SHORT_CIRCUIT_FALSE
, /* ARM. */
2325 tune_params::DISPARAGE_FLAGS_NEITHER
,
2326 tune_params::PREF_NEON_STRINGOPS_FALSE
,
2327 tune_params::FUSE_NOTHING
,
2328 tune_params::SCHED_AUTOPREF_OFF
2331 /* Cortex-M7 tuning. */
2333 const struct tune_params arm_cortex_m7_tune
=
2336 &generic_addr_mode_costs
, /* Addressing mode costs. */
2337 NULL
, /* Sched adj cost. */
2338 arm_cortex_m7_branch_cost
,
2339 &arm_default_vec_cost
,
2340 0, /* Constant limit. */
2341 1, /* Max cond insns. */
2342 8, /* Memset max inline. */
2343 2, /* Issue rate. */
2344 ARM_PREFETCH_NOT_BENEFICIAL
,
2345 tune_params::PREF_CONST_POOL_TRUE
,
2346 tune_params::PREF_LDRD_FALSE
,
2347 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
2348 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
2349 tune_params::DISPARAGE_FLAGS_NEITHER
,
2350 tune_params::PREF_NEON_STRINGOPS_FALSE
,
2351 tune_params::FUSE_NOTHING
,
2352 tune_params::SCHED_AUTOPREF_OFF
2355 /* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than
2356 arm_v6t2_tune. It is used for cortex-m0, cortex-m1, cortex-m0plus and
2358 const struct tune_params arm_v6m_tune
=
2360 &generic_extra_costs
, /* Insn extra costs. */
2361 &generic_addr_mode_costs
, /* Addressing mode costs. */
2362 NULL
, /* Sched adj cost. */
2363 arm_default_branch_cost
,
2364 &arm_default_vec_cost
, /* Vectorizer costs. */
2365 1, /* Constant limit. */
2366 5, /* Max cond insns. */
2367 8, /* Memset max inline. */
2368 1, /* Issue rate. */
2369 ARM_PREFETCH_NOT_BENEFICIAL
,
2370 tune_params::PREF_CONST_POOL_FALSE
,
2371 tune_params::PREF_LDRD_FALSE
,
2372 tune_params::LOG_OP_NON_SHORT_CIRCUIT_FALSE
, /* Thumb. */
2373 tune_params::LOG_OP_NON_SHORT_CIRCUIT_FALSE
, /* ARM. */
2374 tune_params::DISPARAGE_FLAGS_NEITHER
,
2375 tune_params::PREF_NEON_STRINGOPS_FALSE
,
2376 tune_params::FUSE_NOTHING
,
2377 tune_params::SCHED_AUTOPREF_OFF
2380 const struct tune_params arm_fa726te_tune
=
2382 &generic_extra_costs
, /* Insn extra costs. */
2383 &generic_addr_mode_costs
, /* Addressing mode costs. */
2384 fa726te_sched_adjust_cost
,
2385 arm_default_branch_cost
,
2386 &arm_default_vec_cost
,
2387 1, /* Constant limit. */
2388 5, /* Max cond insns. */
2389 8, /* Memset max inline. */
2390 2, /* Issue rate. */
2391 ARM_PREFETCH_NOT_BENEFICIAL
,
2392 tune_params::PREF_CONST_POOL_TRUE
,
2393 tune_params::PREF_LDRD_FALSE
,
2394 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* Thumb. */
2395 tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE
, /* ARM. */
2396 tune_params::DISPARAGE_FLAGS_NEITHER
,
2397 tune_params::PREF_NEON_STRINGOPS_FALSE
,
2398 tune_params::FUSE_NOTHING
,
2399 tune_params::SCHED_AUTOPREF_OFF
2402 /* Auto-generated CPU, FPU and architecture tables. */
2403 #include "arm-cpu-data.h"
2405 /* The name of the preprocessor macro to define for this architecture. PROFILE
2406 is replaced by the architecture name (eg. 8A) in arm_option_override () and
2407 is thus chosen to be big enough to hold the longest architecture name. */
2409 char arm_arch_name
[] = "__ARM_ARCH_PROFILE__";
2411 /* Supported TLS relocations. */
2422 TLS_DESCSEQ
/* GNU scheme */
2425 /* The maximum number of insns to be used when loading a constant. */
2427 arm_constant_limit (bool size_p
)
2429 return size_p
? 1 : current_tune
->constant_limit
;
2432 /* Emit an insn that's a simple single-set. Both the operands must be known
2434 inline static rtx_insn
*
2435 emit_set_insn (rtx x
, rtx y
)
2437 return emit_insn (gen_rtx_SET (x
, y
));
2440 /* Return the number of bits set in VALUE. */
2442 bit_count (unsigned long value
)
2444 unsigned long count
= 0;
2449 value
&= value
- 1; /* Clear the least-significant set bit. */
2455 /* Return the number of bits set in BMAP. */
2457 bitmap_popcount (const sbitmap bmap
)
2459 unsigned int count
= 0;
2461 sbitmap_iterator sbi
;
2463 EXECUTE_IF_SET_IN_BITMAP (bmap
, 0, n
, sbi
)
2472 } arm_fixed_mode_set
;
2474 /* A small helper for setting fixed-point library libfuncs. */
2477 arm_set_fixed_optab_libfunc (optab optable
, machine_mode mode
,
2478 const char *funcname
, const char *modename
,
2483 if (num_suffix
== 0)
2484 sprintf (buffer
, "__gnu_%s%s", funcname
, modename
);
2486 sprintf (buffer
, "__gnu_%s%s%d", funcname
, modename
, num_suffix
);
2488 set_optab_libfunc (optable
, mode
, buffer
);
2492 arm_set_fixed_conv_libfunc (convert_optab optable
, machine_mode to
,
2493 machine_mode from
, const char *funcname
,
2494 const char *toname
, const char *fromname
)
2497 const char *maybe_suffix_2
= "";
2499 /* Follow the logic for selecting a "2" suffix in fixed-bit.h. */
2500 if (ALL_FIXED_POINT_MODE_P (from
) && ALL_FIXED_POINT_MODE_P (to
)
2501 && UNSIGNED_FIXED_POINT_MODE_P (from
) == UNSIGNED_FIXED_POINT_MODE_P (to
)
2502 && ALL_FRACT_MODE_P (from
) == ALL_FRACT_MODE_P (to
))
2503 maybe_suffix_2
= "2";
2505 sprintf (buffer
, "__gnu_%s%s%s%s", funcname
, fromname
, toname
,
2508 set_conv_libfunc (optable
, to
, from
, buffer
);
2511 static GTY(()) rtx speculation_barrier_libfunc
;
2513 /* Record that we have no arithmetic or comparison libfuncs for
2514 machine mode MODE. */
2517 arm_block_arith_comp_libfuncs_for_mode (machine_mode mode
)
2520 set_optab_libfunc (add_optab
, mode
, NULL
);
2521 set_optab_libfunc (sdiv_optab
, mode
, NULL
);
2522 set_optab_libfunc (smul_optab
, mode
, NULL
);
2523 set_optab_libfunc (neg_optab
, mode
, NULL
);
2524 set_optab_libfunc (sub_optab
, mode
, NULL
);
2527 set_optab_libfunc (eq_optab
, mode
, NULL
);
2528 set_optab_libfunc (ne_optab
, mode
, NULL
);
2529 set_optab_libfunc (lt_optab
, mode
, NULL
);
2530 set_optab_libfunc (le_optab
, mode
, NULL
);
2531 set_optab_libfunc (ge_optab
, mode
, NULL
);
2532 set_optab_libfunc (gt_optab
, mode
, NULL
);
2533 set_optab_libfunc (unord_optab
, mode
, NULL
);
2536 /* Set up library functions unique to ARM. */
2538 arm_init_libfuncs (void)
2540 machine_mode mode_iter
;
2542 /* For Linux, we have access to kernel support for atomic operations. */
2543 if (arm_abi
== ARM_ABI_AAPCS_LINUX
)
2544 init_sync_libfuncs (MAX_SYNC_LIBFUNC_SIZE
);
2546 /* There are no special library functions unless we are using the
2551 /* The functions below are described in Section 4 of the "Run-Time
2552 ABI for the ARM architecture", Version 1.0. */
2554 /* Double-precision floating-point arithmetic. Table 2. */
2555 set_optab_libfunc (add_optab
, DFmode
, "__aeabi_dadd");
2556 set_optab_libfunc (sdiv_optab
, DFmode
, "__aeabi_ddiv");
2557 set_optab_libfunc (smul_optab
, DFmode
, "__aeabi_dmul");
2558 set_optab_libfunc (neg_optab
, DFmode
, "__aeabi_dneg");
2559 set_optab_libfunc (sub_optab
, DFmode
, "__aeabi_dsub");
2561 /* Double-precision comparisons. Table 3. */
2562 set_optab_libfunc (eq_optab
, DFmode
, "__aeabi_dcmpeq");
2563 set_optab_libfunc (ne_optab
, DFmode
, NULL
);
2564 set_optab_libfunc (lt_optab
, DFmode
, "__aeabi_dcmplt");
2565 set_optab_libfunc (le_optab
, DFmode
, "__aeabi_dcmple");
2566 set_optab_libfunc (ge_optab
, DFmode
, "__aeabi_dcmpge");
2567 set_optab_libfunc (gt_optab
, DFmode
, "__aeabi_dcmpgt");
2568 set_optab_libfunc (unord_optab
, DFmode
, "__aeabi_dcmpun");
2570 /* Single-precision floating-point arithmetic. Table 4. */
2571 set_optab_libfunc (add_optab
, SFmode
, "__aeabi_fadd");
2572 set_optab_libfunc (sdiv_optab
, SFmode
, "__aeabi_fdiv");
2573 set_optab_libfunc (smul_optab
, SFmode
, "__aeabi_fmul");
2574 set_optab_libfunc (neg_optab
, SFmode
, "__aeabi_fneg");
2575 set_optab_libfunc (sub_optab
, SFmode
, "__aeabi_fsub");
2577 /* Single-precision comparisons. Table 5. */
2578 set_optab_libfunc (eq_optab
, SFmode
, "__aeabi_fcmpeq");
2579 set_optab_libfunc (ne_optab
, SFmode
, NULL
);
2580 set_optab_libfunc (lt_optab
, SFmode
, "__aeabi_fcmplt");
2581 set_optab_libfunc (le_optab
, SFmode
, "__aeabi_fcmple");
2582 set_optab_libfunc (ge_optab
, SFmode
, "__aeabi_fcmpge");
2583 set_optab_libfunc (gt_optab
, SFmode
, "__aeabi_fcmpgt");
2584 set_optab_libfunc (unord_optab
, SFmode
, "__aeabi_fcmpun");
2586 /* Floating-point to integer conversions. Table 6. */
2587 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__aeabi_d2iz");
2588 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__aeabi_d2uiz");
2589 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__aeabi_d2lz");
2590 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__aeabi_d2ulz");
2591 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__aeabi_f2iz");
2592 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__aeabi_f2uiz");
2593 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__aeabi_f2lz");
2594 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__aeabi_f2ulz");
2596 /* Conversions between floating types. Table 7. */
2597 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__aeabi_d2f");
2598 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__aeabi_f2d");
2600 /* Integer to floating-point conversions. Table 8. */
2601 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__aeabi_i2d");
2602 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
, "__aeabi_ui2d");
2603 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__aeabi_l2d");
2604 set_conv_libfunc (ufloat_optab
, DFmode
, DImode
, "__aeabi_ul2d");
2605 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__aeabi_i2f");
2606 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__aeabi_ui2f");
2607 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__aeabi_l2f");
2608 set_conv_libfunc (ufloat_optab
, SFmode
, DImode
, "__aeabi_ul2f");
2610 /* Long long. Table 9. */
2611 set_optab_libfunc (smul_optab
, DImode
, "__aeabi_lmul");
2612 set_optab_libfunc (sdivmod_optab
, DImode
, "__aeabi_ldivmod");
2613 set_optab_libfunc (udivmod_optab
, DImode
, "__aeabi_uldivmod");
2614 set_optab_libfunc (ashl_optab
, DImode
, "__aeabi_llsl");
2615 set_optab_libfunc (lshr_optab
, DImode
, "__aeabi_llsr");
2616 set_optab_libfunc (ashr_optab
, DImode
, "__aeabi_lasr");
2617 set_optab_libfunc (cmp_optab
, DImode
, "__aeabi_lcmp");
2618 set_optab_libfunc (ucmp_optab
, DImode
, "__aeabi_ulcmp");
2620 /* Integer (32/32->32) division. \S 4.3.1. */
2621 set_optab_libfunc (sdivmod_optab
, SImode
, "__aeabi_idivmod");
2622 set_optab_libfunc (udivmod_optab
, SImode
, "__aeabi_uidivmod");
2624 /* The divmod functions are designed so that they can be used for
2625 plain division, even though they return both the quotient and the
2626 remainder. The quotient is returned in the usual location (i.e.,
2627 r0 for SImode, {r0, r1} for DImode), just as would be expected
2628 for an ordinary division routine. Because the AAPCS calling
2629 conventions specify that all of { r0, r1, r2, r3 } are
2630 callee-saved registers, there is no need to tell the compiler
2631 explicitly that those registers are clobbered by these
2633 set_optab_libfunc (sdiv_optab
, DImode
, "__aeabi_ldivmod");
2634 set_optab_libfunc (udiv_optab
, DImode
, "__aeabi_uldivmod");
2636 /* For SImode division the ABI provides div-without-mod routines,
2637 which are faster. */
2638 set_optab_libfunc (sdiv_optab
, SImode
, "__aeabi_idiv");
2639 set_optab_libfunc (udiv_optab
, SImode
, "__aeabi_uidiv");
2641 /* We don't have mod libcalls. Fortunately gcc knows how to use the
2642 divmod libcalls instead. */
2643 set_optab_libfunc (smod_optab
, DImode
, NULL
);
2644 set_optab_libfunc (umod_optab
, DImode
, NULL
);
2645 set_optab_libfunc (smod_optab
, SImode
, NULL
);
2646 set_optab_libfunc (umod_optab
, SImode
, NULL
);
2648 /* Half-precision float operations. The compiler handles all operations
2649 with NULL libfuncs by converting the SFmode. */
2650 switch (arm_fp16_format
)
2652 case ARM_FP16_FORMAT_IEEE
:
2653 case ARM_FP16_FORMAT_ALTERNATIVE
:
2656 set_conv_libfunc (trunc_optab
, HFmode
, SFmode
,
2657 (arm_fp16_format
== ARM_FP16_FORMAT_IEEE
2659 : "__gnu_f2h_alternative"));
2660 set_conv_libfunc (sext_optab
, SFmode
, HFmode
,
2661 (arm_fp16_format
== ARM_FP16_FORMAT_IEEE
2663 : "__gnu_h2f_alternative"));
2665 set_conv_libfunc (trunc_optab
, HFmode
, DFmode
,
2666 (arm_fp16_format
== ARM_FP16_FORMAT_IEEE
2668 : "__gnu_d2h_alternative"));
2670 arm_block_arith_comp_libfuncs_for_mode (HFmode
);
2677 /* For all possible libcalls in BFmode, record NULL. */
2678 FOR_EACH_MODE_IN_CLASS (mode_iter
, MODE_FLOAT
)
2680 set_conv_libfunc (trunc_optab
, BFmode
, mode_iter
, NULL
);
2681 set_conv_libfunc (trunc_optab
, mode_iter
, BFmode
, NULL
);
2682 set_conv_libfunc (sext_optab
, mode_iter
, BFmode
, NULL
);
2683 set_conv_libfunc (sext_optab
, BFmode
, mode_iter
, NULL
);
2685 arm_block_arith_comp_libfuncs_for_mode (BFmode
);
2687 /* Use names prefixed with __gnu_ for fixed-point helper functions. */
2689 const arm_fixed_mode_set fixed_arith_modes
[] =
2692 { E_UQQmode
, "uqq" },
2694 { E_UHQmode
, "uhq" },
2696 { E_USQmode
, "usq" },
2698 { E_UDQmode
, "udq" },
2700 { E_UTQmode
, "utq" },
2702 { E_UHAmode
, "uha" },
2704 { E_USAmode
, "usa" },
2706 { E_UDAmode
, "uda" },
2708 { E_UTAmode
, "uta" }
2710 const arm_fixed_mode_set fixed_conv_modes
[] =
2713 { E_UQQmode
, "uqq" },
2715 { E_UHQmode
, "uhq" },
2717 { E_USQmode
, "usq" },
2719 { E_UDQmode
, "udq" },
2721 { E_UTQmode
, "utq" },
2723 { E_UHAmode
, "uha" },
2725 { E_USAmode
, "usa" },
2727 { E_UDAmode
, "uda" },
2729 { E_UTAmode
, "uta" },
2740 for (i
= 0; i
< ARRAY_SIZE (fixed_arith_modes
); i
++)
2742 arm_set_fixed_optab_libfunc (add_optab
, fixed_arith_modes
[i
].mode
,
2743 "add", fixed_arith_modes
[i
].name
, 3);
2744 arm_set_fixed_optab_libfunc (ssadd_optab
, fixed_arith_modes
[i
].mode
,
2745 "ssadd", fixed_arith_modes
[i
].name
, 3);
2746 arm_set_fixed_optab_libfunc (usadd_optab
, fixed_arith_modes
[i
].mode
,
2747 "usadd", fixed_arith_modes
[i
].name
, 3);
2748 arm_set_fixed_optab_libfunc (sub_optab
, fixed_arith_modes
[i
].mode
,
2749 "sub", fixed_arith_modes
[i
].name
, 3);
2750 arm_set_fixed_optab_libfunc (sssub_optab
, fixed_arith_modes
[i
].mode
,
2751 "sssub", fixed_arith_modes
[i
].name
, 3);
2752 arm_set_fixed_optab_libfunc (ussub_optab
, fixed_arith_modes
[i
].mode
,
2753 "ussub", fixed_arith_modes
[i
].name
, 3);
2754 arm_set_fixed_optab_libfunc (smul_optab
, fixed_arith_modes
[i
].mode
,
2755 "mul", fixed_arith_modes
[i
].name
, 3);
2756 arm_set_fixed_optab_libfunc (ssmul_optab
, fixed_arith_modes
[i
].mode
,
2757 "ssmul", fixed_arith_modes
[i
].name
, 3);
2758 arm_set_fixed_optab_libfunc (usmul_optab
, fixed_arith_modes
[i
].mode
,
2759 "usmul", fixed_arith_modes
[i
].name
, 3);
2760 arm_set_fixed_optab_libfunc (sdiv_optab
, fixed_arith_modes
[i
].mode
,
2761 "div", fixed_arith_modes
[i
].name
, 3);
2762 arm_set_fixed_optab_libfunc (udiv_optab
, fixed_arith_modes
[i
].mode
,
2763 "udiv", fixed_arith_modes
[i
].name
, 3);
2764 arm_set_fixed_optab_libfunc (ssdiv_optab
, fixed_arith_modes
[i
].mode
,
2765 "ssdiv", fixed_arith_modes
[i
].name
, 3);
2766 arm_set_fixed_optab_libfunc (usdiv_optab
, fixed_arith_modes
[i
].mode
,
2767 "usdiv", fixed_arith_modes
[i
].name
, 3);
2768 arm_set_fixed_optab_libfunc (neg_optab
, fixed_arith_modes
[i
].mode
,
2769 "neg", fixed_arith_modes
[i
].name
, 2);
2770 arm_set_fixed_optab_libfunc (ssneg_optab
, fixed_arith_modes
[i
].mode
,
2771 "ssneg", fixed_arith_modes
[i
].name
, 2);
2772 arm_set_fixed_optab_libfunc (usneg_optab
, fixed_arith_modes
[i
].mode
,
2773 "usneg", fixed_arith_modes
[i
].name
, 2);
2774 arm_set_fixed_optab_libfunc (ashl_optab
, fixed_arith_modes
[i
].mode
,
2775 "ashl", fixed_arith_modes
[i
].name
, 3);
2776 arm_set_fixed_optab_libfunc (ashr_optab
, fixed_arith_modes
[i
].mode
,
2777 "ashr", fixed_arith_modes
[i
].name
, 3);
2778 arm_set_fixed_optab_libfunc (lshr_optab
, fixed_arith_modes
[i
].mode
,
2779 "lshr", fixed_arith_modes
[i
].name
, 3);
2780 arm_set_fixed_optab_libfunc (ssashl_optab
, fixed_arith_modes
[i
].mode
,
2781 "ssashl", fixed_arith_modes
[i
].name
, 3);
2782 arm_set_fixed_optab_libfunc (usashl_optab
, fixed_arith_modes
[i
].mode
,
2783 "usashl", fixed_arith_modes
[i
].name
, 3);
2784 arm_set_fixed_optab_libfunc (cmp_optab
, fixed_arith_modes
[i
].mode
,
2785 "cmp", fixed_arith_modes
[i
].name
, 2);
2788 for (i
= 0; i
< ARRAY_SIZE (fixed_conv_modes
); i
++)
2789 for (j
= 0; j
< ARRAY_SIZE (fixed_conv_modes
); j
++)
2792 || (!ALL_FIXED_POINT_MODE_P (fixed_conv_modes
[i
].mode
)
2793 && !ALL_FIXED_POINT_MODE_P (fixed_conv_modes
[j
].mode
)))
2796 arm_set_fixed_conv_libfunc (fract_optab
, fixed_conv_modes
[i
].mode
,
2797 fixed_conv_modes
[j
].mode
, "fract",
2798 fixed_conv_modes
[i
].name
,
2799 fixed_conv_modes
[j
].name
);
2800 arm_set_fixed_conv_libfunc (satfract_optab
,
2801 fixed_conv_modes
[i
].mode
,
2802 fixed_conv_modes
[j
].mode
, "satfract",
2803 fixed_conv_modes
[i
].name
,
2804 fixed_conv_modes
[j
].name
);
2805 arm_set_fixed_conv_libfunc (fractuns_optab
,
2806 fixed_conv_modes
[i
].mode
,
2807 fixed_conv_modes
[j
].mode
, "fractuns",
2808 fixed_conv_modes
[i
].name
,
2809 fixed_conv_modes
[j
].name
);
2810 arm_set_fixed_conv_libfunc (satfractuns_optab
,
2811 fixed_conv_modes
[i
].mode
,
2812 fixed_conv_modes
[j
].mode
, "satfractuns",
2813 fixed_conv_modes
[i
].name
,
2814 fixed_conv_modes
[j
].name
);
2818 if (TARGET_AAPCS_BASED
)
2819 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
2821 speculation_barrier_libfunc
= init_one_libfunc ("__speculation_barrier");
2824 /* On AAPCS systems, this is the "struct __va_list". */
2825 static GTY(()) tree va_list_type
;
2827 /* Return the type to use as __builtin_va_list. */
2829 arm_build_builtin_va_list (void)
2834 if (!TARGET_AAPCS_BASED
)
2835 return std_build_builtin_va_list ();
2837 /* AAPCS \S 7.1.4 requires that va_list be a typedef for a type
2845 The C Library ABI further reinforces this definition in \S
2848 We must follow this definition exactly. The structure tag
2849 name is visible in C++ mangled names, and thus forms a part
2850 of the ABI. The field name may be used by people who
2851 #include <stdarg.h>. */
2852 /* Create the type. */
2853 va_list_type
= lang_hooks
.types
.make_type (RECORD_TYPE
);
2854 /* Give it the required name. */
2855 va_list_name
= build_decl (BUILTINS_LOCATION
,
2857 get_identifier ("__va_list"),
2859 DECL_ARTIFICIAL (va_list_name
) = 1;
2860 TYPE_NAME (va_list_type
) = va_list_name
;
2861 TYPE_STUB_DECL (va_list_type
) = va_list_name
;
2862 /* Create the __ap field. */
2863 ap_field
= build_decl (BUILTINS_LOCATION
,
2865 get_identifier ("__ap"),
2867 DECL_ARTIFICIAL (ap_field
) = 1;
2868 DECL_FIELD_CONTEXT (ap_field
) = va_list_type
;
2869 TYPE_FIELDS (va_list_type
) = ap_field
;
2870 /* Compute its layout. */
2871 layout_type (va_list_type
);
2873 return va_list_type
;
2876 /* Return an expression of type "void *" pointing to the next
2877 available argument in a variable-argument list. VALIST is the
2878 user-level va_list object, of type __builtin_va_list. */
2880 arm_extract_valist_ptr (tree valist
)
2882 if (TREE_TYPE (valist
) == error_mark_node
)
2883 return error_mark_node
;
2885 /* On an AAPCS target, the pointer is stored within "struct
2887 if (TARGET_AAPCS_BASED
)
2889 tree ap_field
= TYPE_FIELDS (TREE_TYPE (valist
));
2890 valist
= build3 (COMPONENT_REF
, TREE_TYPE (ap_field
),
2891 valist
, ap_field
, NULL_TREE
);
2897 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
2899 arm_expand_builtin_va_start (tree valist
, rtx nextarg
)
2901 valist
= arm_extract_valist_ptr (valist
);
2902 std_expand_builtin_va_start (valist
, nextarg
);
2905 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
2907 arm_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
2910 valist
= arm_extract_valist_ptr (valist
);
2911 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
2914 /* Check any incompatible options that the user has specified. */
2916 arm_option_check_internal (struct gcc_options
*opts
)
2918 int flags
= opts
->x_target_flags
;
2920 /* iWMMXt and NEON are incompatible. */
2922 && bitmap_bit_p (arm_active_target
.isa
, isa_bit_neon
))
2923 error ("iWMMXt and NEON are incompatible");
2925 /* Make sure that the processor choice does not conflict with any of the
2926 other command line choices. */
2927 if (TARGET_ARM_P (flags
)
2928 && !bitmap_bit_p (arm_active_target
.isa
, isa_bit_notm
))
2929 error ("target CPU does not support ARM mode");
2931 /* TARGET_BACKTRACE cannot be used here as crtl->is_leaf is not set yet. */
2932 if ((TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
) && TARGET_ARM_P (flags
))
2933 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
2935 if (TARGET_ARM_P (flags
) && TARGET_CALLEE_INTERWORKING
)
2936 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
2938 /* If this target is normally configured to use APCS frames, warn if they
2939 are turned off and debugging is turned on. */
2940 if (TARGET_ARM_P (flags
)
2941 && write_symbols
!= NO_DEBUG
2942 && !TARGET_APCS_FRAME
2943 && (TARGET_DEFAULT
& MASK_APCS_FRAME
))
2944 warning (0, "%<-g%> with %<-mno-apcs-frame%> may not give sensible "
2947 /* iWMMXt unsupported under Thumb mode. */
2948 if (TARGET_THUMB_P (flags
) && TARGET_IWMMXT
)
2949 error ("iWMMXt unsupported under Thumb mode");
2951 if (TARGET_HARD_TP
&& TARGET_THUMB1_P (flags
))
2952 error ("cannot use %<-mtp=cp15%> with 16-bit Thumb");
2954 if (TARGET_THUMB_P (flags
) && TARGET_VXWORKS_RTP
&& flag_pic
)
2956 error ("RTP PIC is incompatible with Thumb");
2960 if (target_pure_code
|| target_slow_flash_data
)
2962 const char *flag
= (target_pure_code
? "-mpure-code" :
2963 "-mslow-flash-data");
2964 bool common_unsupported_modes
= arm_arch_notm
|| flag_pic
|| TARGET_NEON
;
2966 /* We only support -mslow-flash-data on M-profile targets with
2968 if (target_slow_flash_data
&& (!TARGET_HAVE_MOVT
|| common_unsupported_modes
))
2969 error ("%s only supports non-pic code on M-profile targets with the "
2970 "MOVT instruction", flag
);
2972 /* We only support -mpure-code on M-profile targets. */
2973 if (target_pure_code
&& common_unsupported_modes
)
2974 error ("%s only supports non-pic code on M-profile targets", flag
);
2976 /* Cannot load addresses: -mslow-flash-data forbids literal pool and
2977 -mword-relocations forbids relocation of MOVT/MOVW. */
2978 if (target_word_relocations
)
2979 error ("%s incompatible with %<-mword-relocations%>", flag
);
2983 /* Recompute the global settings depending on target attribute options. */
2986 arm_option_params_internal (void)
2988 /* If we are not using the default (ARM mode) section anchor offset
2989 ranges, then set the correct ranges now. */
2992 /* Thumb-1 LDR instructions cannot have negative offsets.
2993 Permissible positive offset ranges are 5-bit (for byte loads),
2994 6-bit (for halfword loads), or 7-bit (for word loads).
2995 Empirical results suggest a 7-bit anchor range gives the best
2996 overall code size. */
2997 targetm
.min_anchor_offset
= 0;
2998 targetm
.max_anchor_offset
= 127;
3000 else if (TARGET_THUMB2
)
3002 /* The minimum is set such that the total size of the block
3003 for a particular anchor is 248 + 1 + 4095 bytes, which is
3004 divisible by eight, ensuring natural spacing of anchors. */
3005 targetm
.min_anchor_offset
= -248;
3006 targetm
.max_anchor_offset
= 4095;
3010 targetm
.min_anchor_offset
= TARGET_MIN_ANCHOR_OFFSET
;
3011 targetm
.max_anchor_offset
= TARGET_MAX_ANCHOR_OFFSET
;
3014 /* Increase the number of conditional instructions with -Os. */
3015 max_insns_skipped
= optimize_size
? 4 : current_tune
->max_insns_skipped
;
3017 /* For THUMB2, we limit the conditional sequence to one IT block. */
3019 max_insns_skipped
= MIN (max_insns_skipped
, MAX_INSN_PER_IT_BLOCK
);
3022 targetm
.md_asm_adjust
= thumb1_md_asm_adjust
;
3024 targetm
.md_asm_adjust
= arm_md_asm_adjust
;
3027 /* True if -mflip-thumb should next add an attribute for the default
3028 mode, false if it should next add an attribute for the opposite mode. */
3029 static GTY(()) bool thumb_flipper
;
3031 /* Options after initial target override. */
3032 static GTY(()) tree init_optimize
;
3035 arm_override_options_after_change_1 (struct gcc_options
*opts
,
3036 struct gcc_options
*opts_set
)
3038 /* -falign-functions without argument: supply one. */
3039 if (opts
->x_flag_align_functions
&& !opts_set
->x_str_align_functions
)
3040 opts
->x_str_align_functions
= TARGET_THUMB_P (opts
->x_target_flags
)
3041 && opts
->x_optimize_size
? "2" : "4";
3044 /* Implement targetm.override_options_after_change. */
3047 arm_override_options_after_change (void)
3049 arm_override_options_after_change_1 (&global_options
, &global_options_set
);
3052 /* Implement TARGET_OPTION_RESTORE. */
3054 arm_option_restore (struct gcc_options */
* opts */
,
3055 struct gcc_options
*opts_set
, struct cl_target_option
*ptr
)
3057 arm_configure_build_target (&arm_active_target
, ptr
, opts_set
, false);
3060 /* Reset options between modes that the user has specified. */
3062 arm_option_override_internal (struct gcc_options
*opts
,
3063 struct gcc_options
*opts_set
)
3065 arm_override_options_after_change_1 (opts
, opts_set
);
3067 if (TARGET_INTERWORK
&& !bitmap_bit_p (arm_active_target
.isa
, isa_bit_thumb
))
3069 /* The default is to enable interworking, so this warning message would
3070 be confusing to users who have just compiled with
3071 eg, -march=armv4. */
3072 /* warning (0, "ignoring -minterwork because target CPU does not support THUMB"); */
3073 opts
->x_target_flags
&= ~MASK_INTERWORK
;
3076 if (TARGET_THUMB_P (opts
->x_target_flags
)
3077 && !bitmap_bit_p (arm_active_target
.isa
, isa_bit_thumb
))
3079 warning (0, "target CPU does not support THUMB instructions");
3080 opts
->x_target_flags
&= ~MASK_THUMB
;
3083 if (TARGET_APCS_FRAME
&& TARGET_THUMB_P (opts
->x_target_flags
))
3085 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
3086 opts
->x_target_flags
&= ~MASK_APCS_FRAME
;
3089 /* Callee super interworking implies thumb interworking. Adding
3090 this to the flags here simplifies the logic elsewhere. */
3091 if (TARGET_THUMB_P (opts
->x_target_flags
) && TARGET_CALLEE_INTERWORKING
)
3092 opts
->x_target_flags
|= MASK_INTERWORK
;
3094 /* need to remember initial values so combinaisons of options like
3095 -mflip-thumb -mthumb -fno-schedule-insns work for any attribute. */
3096 cl_optimization
*to
= TREE_OPTIMIZATION (init_optimize
);
3098 if (! opts_set
->x_arm_restrict_it
)
3099 opts
->x_arm_restrict_it
= arm_arch8
;
3101 /* ARM execution state and M profile don't have [restrict] IT. */
3102 if (!TARGET_THUMB2_P (opts
->x_target_flags
) || !arm_arch_notm
)
3103 opts
->x_arm_restrict_it
= 0;
3105 /* Use the IT size from CPU specific tuning unless -mrestrict-it is used. */
3106 if (!opts_set
->x_arm_restrict_it
3107 && (opts_set
->x_arm_cpu_string
|| opts_set
->x_arm_tune_string
))
3108 opts
->x_arm_restrict_it
= 0;
3110 /* Enable -munaligned-access by default for
3111 - all ARMv6 architecture-based processors when compiling for a 32-bit ISA
3112 i.e. Thumb2 and ARM state only.
3113 - ARMv7-A, ARMv7-R, and ARMv7-M architecture-based processors.
3114 - ARMv8 architecture-base processors.
3116 Disable -munaligned-access by default for
3117 - all pre-ARMv6 architecture-based processors
3118 - ARMv6-M architecture-based processors
3119 - ARMv8-M Baseline processors. */
3121 if (! opts_set
->x_unaligned_access
)
3123 opts
->x_unaligned_access
= (TARGET_32BIT_P (opts
->x_target_flags
)
3124 && arm_arch6
&& (arm_arch_notm
|| arm_arch7
));
3126 else if (opts
->x_unaligned_access
== 1
3127 && !(arm_arch6
&& (arm_arch_notm
|| arm_arch7
)))
3129 warning (0, "target CPU does not support unaligned accesses");
3130 opts
->x_unaligned_access
= 0;
3133 /* Don't warn since it's on by default in -O2. */
3134 if (TARGET_THUMB1_P (opts
->x_target_flags
))
3135 opts
->x_flag_schedule_insns
= 0;
3137 opts
->x_flag_schedule_insns
= to
->x_flag_schedule_insns
;
3139 /* Disable shrink-wrap when optimizing function for size, since it tends to
3140 generate additional returns. */
3141 if (optimize_function_for_size_p (cfun
)
3142 && TARGET_THUMB2_P (opts
->x_target_flags
))
3143 opts
->x_flag_shrink_wrap
= false;
3145 opts
->x_flag_shrink_wrap
= to
->x_flag_shrink_wrap
;
3147 /* In Thumb1 mode, we emit the epilogue in RTL, but the last insn
3148 - epilogue_insns - does not accurately model the corresponding insns
3149 emitted in the asm file. In particular, see the comment in thumb_exit
3150 'Find out how many of the (return) argument registers we can corrupt'.
3151 As a consequence, the epilogue may clobber registers without fipa-ra
3152 finding out about it. Therefore, disable fipa-ra in Thumb1 mode.
3153 TODO: Accurately model clobbers for epilogue_insns and reenable
3155 if (TARGET_THUMB1_P (opts
->x_target_flags
))
3156 opts
->x_flag_ipa_ra
= 0;
3158 opts
->x_flag_ipa_ra
= to
->x_flag_ipa_ra
;
3160 /* Thumb2 inline assembly code should always use unified syntax.
3161 This will apply to ARM and Thumb1 eventually. */
3162 if (TARGET_THUMB2_P (opts
->x_target_flags
))
3163 opts
->x_inline_asm_unified
= true;
3165 #ifdef SUBTARGET_OVERRIDE_INTERNAL_OPTIONS
3166 SUBTARGET_OVERRIDE_INTERNAL_OPTIONS
;
3170 static sbitmap isa_all_fpubits_internal
;
3171 static sbitmap isa_all_fpbits
;
3172 static sbitmap isa_quirkbits
;
3174 /* Configure a build target TARGET from the user-specified options OPTS and
3175 OPTS_SET. If WARN_COMPATIBLE, emit a diagnostic if both the CPU and
3176 architecture have been specified, but the two are not identical. */
3178 arm_configure_build_target (struct arm_build_target
*target
,
3179 struct cl_target_option
*opts
,
3180 struct gcc_options
*opts_set
,
3181 bool warn_compatible
)
3183 const cpu_option
*arm_selected_tune
= NULL
;
3184 const arch_option
*arm_selected_arch
= NULL
;
3185 const cpu_option
*arm_selected_cpu
= NULL
;
3186 const arm_fpu_desc
*arm_selected_fpu
= NULL
;
3187 const char *tune_opts
= NULL
;
3188 const char *arch_opts
= NULL
;
3189 const char *cpu_opts
= NULL
;
3191 bitmap_clear (target
->isa
);
3192 target
->core_name
= NULL
;
3193 target
->arch_name
= NULL
;
3195 if (opts_set
->x_arm_arch_string
)
3197 arm_selected_arch
= arm_parse_arch_option_name (all_architectures
,
3199 opts
->x_arm_arch_string
);
3200 arch_opts
= strchr (opts
->x_arm_arch_string
, '+');
3203 if (opts_set
->x_arm_cpu_string
)
3205 arm_selected_cpu
= arm_parse_cpu_option_name (all_cores
, "-mcpu",
3206 opts
->x_arm_cpu_string
);
3207 cpu_opts
= strchr (opts
->x_arm_cpu_string
, '+');
3208 arm_selected_tune
= arm_selected_cpu
;
3209 /* If taking the tuning from -mcpu, we don't need to rescan the
3210 options for tuning. */
3213 if (opts_set
->x_arm_tune_string
)
3215 arm_selected_tune
= arm_parse_cpu_option_name (all_cores
, "-mtune",
3216 opts
->x_arm_tune_string
);
3217 tune_opts
= strchr (opts
->x_arm_tune_string
, '+');
3220 if (arm_selected_arch
)
3222 arm_initialize_isa (target
->isa
, arm_selected_arch
->common
.isa_bits
);
3223 arm_parse_option_features (target
->isa
, &arm_selected_arch
->common
,
3226 if (arm_selected_cpu
)
3228 auto_sbitmap
cpu_isa (isa_num_bits
);
3229 auto_sbitmap
isa_delta (isa_num_bits
);
3231 arm_initialize_isa (cpu_isa
, arm_selected_cpu
->common
.isa_bits
);
3232 arm_parse_option_features (cpu_isa
, &arm_selected_cpu
->common
,
3234 bitmap_xor (isa_delta
, cpu_isa
, target
->isa
);
3235 /* Ignore any bits that are quirk bits. */
3236 bitmap_and_compl (isa_delta
, isa_delta
, isa_quirkbits
);
3237 /* If the user (or the default configuration) has specified a
3238 specific FPU, then ignore any bits that depend on the FPU
3239 configuration. Do similarly if using the soft-float
3241 if (opts
->x_arm_fpu_index
!= TARGET_FPU_auto
3242 || arm_float_abi
== ARM_FLOAT_ABI_SOFT
)
3243 bitmap_and_compl (isa_delta
, isa_delta
, isa_all_fpbits
);
3245 if (!bitmap_empty_p (isa_delta
))
3247 if (warn_compatible
)
3248 warning (0, "switch %<-mcpu=%s%> conflicts "
3249 "with switch %<-march=%s%>",
3250 opts
->x_arm_cpu_string
,
3251 opts
->x_arm_arch_string
);
3253 /* -march wins for code generation.
3254 -mcpu wins for default tuning. */
3255 if (!arm_selected_tune
)
3256 arm_selected_tune
= arm_selected_cpu
;
3258 arm_selected_cpu
= all_cores
+ arm_selected_arch
->tune_id
;
3259 target
->arch_name
= arm_selected_arch
->common
.name
;
3263 /* Architecture and CPU are essentially the same.
3264 Prefer the CPU setting. */
3265 arm_selected_arch
= all_architectures
+ arm_selected_cpu
->arch
;
3266 target
->core_name
= arm_selected_cpu
->common
.name
;
3267 /* Copy the CPU's capabilities, so that we inherit the
3268 appropriate extensions and quirks. */
3269 bitmap_copy (target
->isa
, cpu_isa
);
3274 /* Pick a CPU based on the architecture. */
3275 arm_selected_cpu
= all_cores
+ arm_selected_arch
->tune_id
;
3276 target
->arch_name
= arm_selected_arch
->common
.name
;
3277 /* Note: target->core_name is left unset in this path. */
3280 else if (arm_selected_cpu
)
3282 target
->core_name
= arm_selected_cpu
->common
.name
;
3283 arm_initialize_isa (target
->isa
, arm_selected_cpu
->common
.isa_bits
);
3284 arm_parse_option_features (target
->isa
, &arm_selected_cpu
->common
,
3286 arm_selected_arch
= all_architectures
+ arm_selected_cpu
->arch
;
3288 /* If the user did not specify a processor or architecture, choose
3292 const cpu_option
*sel
;
3293 auto_sbitmap
sought_isa (isa_num_bits
);
3294 bitmap_clear (sought_isa
);
3295 auto_sbitmap
default_isa (isa_num_bits
);
3297 arm_selected_cpu
= arm_parse_cpu_option_name (all_cores
, "default CPU",
3298 TARGET_CPU_DEFAULT
);
3299 cpu_opts
= strchr (TARGET_CPU_DEFAULT
, '+');
3300 gcc_assert (arm_selected_cpu
->common
.name
);
3302 /* RWE: All of the selection logic below (to the end of this
3303 'if' clause) looks somewhat suspect. It appears to be mostly
3304 there to support forcing thumb support when the default CPU
3305 does not have thumb (somewhat dubious in terms of what the
3306 user might be expecting). I think it should be removed once
3307 support for the pre-thumb era cores is removed. */
3308 sel
= arm_selected_cpu
;
3309 arm_initialize_isa (default_isa
, sel
->common
.isa_bits
);
3310 arm_parse_option_features (default_isa
, &arm_selected_cpu
->common
,
3313 /* Now check to see if the user has specified any command line
3314 switches that require certain abilities from the cpu. */
3316 if (TARGET_INTERWORK
|| TARGET_THUMB
)
3317 bitmap_set_bit (sought_isa
, isa_bit_thumb
);
3319 /* If there are such requirements and the default CPU does not
3320 satisfy them, we need to run over the complete list of
3321 cores looking for one that is satisfactory. */
3322 if (!bitmap_empty_p (sought_isa
)
3323 && !bitmap_subset_p (sought_isa
, default_isa
))
3325 auto_sbitmap
candidate_isa (isa_num_bits
);
3326 /* We're only interested in a CPU with at least the
3327 capabilities of the default CPU and the required
3328 additional features. */
3329 bitmap_ior (default_isa
, default_isa
, sought_isa
);
3331 /* Try to locate a CPU type that supports all of the abilities
3332 of the default CPU, plus the extra abilities requested by
3334 for (sel
= all_cores
; sel
->common
.name
!= NULL
; sel
++)
3336 arm_initialize_isa (candidate_isa
, sel
->common
.isa_bits
);
3337 /* An exact match? */
3338 if (bitmap_equal_p (default_isa
, candidate_isa
))
3342 if (sel
->common
.name
== NULL
)
3344 unsigned current_bit_count
= isa_num_bits
;
3345 const cpu_option
*best_fit
= NULL
;
3347 /* Ideally we would like to issue an error message here
3348 saying that it was not possible to find a CPU compatible
3349 with the default CPU, but which also supports the command
3350 line options specified by the programmer, and so they
3351 ought to use the -mcpu=<name> command line option to
3352 override the default CPU type.
3354 If we cannot find a CPU that has exactly the
3355 characteristics of the default CPU and the given
3356 command line options we scan the array again looking
3357 for a best match. The best match must have at least
3358 the capabilities of the perfect match. */
3359 for (sel
= all_cores
; sel
->common
.name
!= NULL
; sel
++)
3361 arm_initialize_isa (candidate_isa
, sel
->common
.isa_bits
);
3363 if (bitmap_subset_p (default_isa
, candidate_isa
))
3367 bitmap_and_compl (candidate_isa
, candidate_isa
,
3369 count
= bitmap_popcount (candidate_isa
);
3371 if (count
< current_bit_count
)
3374 current_bit_count
= count
;
3378 gcc_assert (best_fit
);
3382 arm_selected_cpu
= sel
;
3385 /* Now we know the CPU, we can finally initialize the target
3387 target
->core_name
= arm_selected_cpu
->common
.name
;
3388 arm_initialize_isa (target
->isa
, arm_selected_cpu
->common
.isa_bits
);
3389 arm_parse_option_features (target
->isa
, &arm_selected_cpu
->common
,
3391 arm_selected_arch
= all_architectures
+ arm_selected_cpu
->arch
;
3394 gcc_assert (arm_selected_cpu
);
3395 gcc_assert (arm_selected_arch
);
3397 if (opts
->x_arm_fpu_index
!= TARGET_FPU_auto
)
3399 arm_selected_fpu
= &all_fpus
[opts
->x_arm_fpu_index
];
3400 auto_sbitmap
fpu_bits (isa_num_bits
);
3402 arm_initialize_isa (fpu_bits
, arm_selected_fpu
->isa_bits
);
3403 /* This should clear out ALL bits relating to the FPU/simd
3404 extensions, to avoid potentially invalid combinations later on
3405 that we can't match. At present we only clear out those bits
3406 that can be set by -mfpu. This should be fixed in GCC-12. */
3407 bitmap_and_compl (target
->isa
, target
->isa
, isa_all_fpubits_internal
);
3408 bitmap_ior (target
->isa
, target
->isa
, fpu_bits
);
3411 /* There may be implied bits which we still need to enable. These are
3412 non-named features which are needed to complete other sets of features,
3413 but cannot be enabled from arm-cpus.in due to being shared between
3414 multiple fgroups. Each entry in all_implied_fbits is of the form
3415 ante -> cons, meaning that if the feature "ante" is enabled, we should
3416 implicitly enable "cons". */
3417 const struct fbit_implication
*impl
= all_implied_fbits
;
3420 if (bitmap_bit_p (target
->isa
, impl
->ante
))
3421 bitmap_set_bit (target
->isa
, impl
->cons
);
3425 if (!arm_selected_tune
)
3426 arm_selected_tune
= arm_selected_cpu
;
3427 else /* Validate the features passed to -mtune. */
3428 arm_parse_option_features (NULL
, &arm_selected_tune
->common
, tune_opts
);
3430 const cpu_tune
*tune_data
= &all_tunes
[arm_selected_tune
- all_cores
];
3432 /* Finish initializing the target structure. */
3433 target
->arch_pp_name
= arm_selected_arch
->arch
;
3434 target
->base_arch
= arm_selected_arch
->base_arch
;
3435 target
->profile
= arm_selected_arch
->profile
;
3437 target
->tune_flags
= tune_data
->tune_flags
;
3438 target
->tune
= tune_data
->tune
;
3439 target
->tune_core
= tune_data
->scheduler
;
3440 arm_option_reconfigure_globals ();
3443 /* Fix up any incompatible options that the user has specified. */
3445 arm_option_override (void)
3447 static const enum isa_feature fpu_bitlist_internal
[]
3448 = { ISA_ALL_FPU_INTERNAL
, isa_nobit
};
3449 /* isa_bit_mve_float is also part of FP bit list for arch v8.1-m.main. */
3450 static const enum isa_feature fp_bitlist
[]
3451 = { ISA_ALL_FP
, isa_bit_mve_float
, isa_nobit
};
3452 static const enum isa_feature quirk_bitlist
[] = { ISA_ALL_QUIRKS
, isa_nobit
};
3453 cl_target_option opts
;
3455 isa_quirkbits
= sbitmap_alloc (isa_num_bits
);
3456 arm_initialize_isa (isa_quirkbits
, quirk_bitlist
);
3458 isa_all_fpubits_internal
= sbitmap_alloc (isa_num_bits
);
3459 isa_all_fpbits
= sbitmap_alloc (isa_num_bits
);
3460 arm_initialize_isa (isa_all_fpubits_internal
, fpu_bitlist_internal
);
3461 arm_initialize_isa (isa_all_fpbits
, fp_bitlist
);
3463 arm_active_target
.isa
= sbitmap_alloc (isa_num_bits
);
3465 if (!global_options_set
.x_arm_fpu_index
)
3470 ok
= opt_enum_arg_to_value (OPT_mfpu_
, FPUTYPE_AUTO
, &fpu_index
,
3473 arm_fpu_index
= (enum fpu_type
) fpu_index
;
3476 cl_target_option_save (&opts
, &global_options
, &global_options_set
);
3477 arm_configure_build_target (&arm_active_target
, &opts
, &global_options_set
,
3480 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3481 SUBTARGET_OVERRIDE_OPTIONS
;
3484 /* Initialize boolean versions of the architectural flags, for use
3485 in the arm.md file and for enabling feature flags. */
3486 arm_option_reconfigure_globals ();
3488 arm_tune
= arm_active_target
.tune_core
;
3489 tune_flags
= arm_active_target
.tune_flags
;
3490 current_tune
= arm_active_target
.tune
;
3492 /* TBD: Dwarf info for apcs frame is not handled yet. */
3493 if (TARGET_APCS_FRAME
)
3494 flag_shrink_wrap
= false;
3496 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
3498 warning (0, "%<-mapcs-stack-check%> incompatible with "
3499 "%<-mno-apcs-frame%>");
3500 target_flags
|= MASK_APCS_FRAME
;
3503 if (TARGET_POKE_FUNCTION_NAME
)
3504 target_flags
|= MASK_APCS_FRAME
;
3506 if (TARGET_APCS_REENT
&& flag_pic
)
3507 error ("%<-fpic%> and %<-mapcs-reent%> are incompatible");
3509 if (TARGET_APCS_REENT
)
3510 warning (0, "APCS reentrant code not supported. Ignored");
3512 /* Set up some tuning parameters. */
3513 arm_ld_sched
= (tune_flags
& TF_LDSCHED
) != 0;
3514 arm_tune_strongarm
= (tune_flags
& TF_STRONG
) != 0;
3515 arm_tune_wbuf
= (tune_flags
& TF_WBUF
) != 0;
3516 arm_tune_xscale
= (tune_flags
& TF_XSCALE
) != 0;
3517 arm_tune_cortex_a9
= (arm_tune
== TARGET_CPU_cortexa9
) != 0;
3518 arm_m_profile_small_mul
= (tune_flags
& TF_SMALLMUL
) != 0;
3520 /* For arm2/3 there is no need to do any scheduling if we are doing
3521 software floating-point. */
3522 if (TARGET_SOFT_FLOAT
&& (tune_flags
& TF_NO_MODE32
))
3523 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
3525 /* Override the default structure alignment for AAPCS ABI. */
3526 if (!global_options_set
.x_arm_structure_size_boundary
)
3528 if (TARGET_AAPCS_BASED
)
3529 arm_structure_size_boundary
= 8;
3533 warning (0, "option %<-mstructure-size-boundary%> is deprecated");
3535 if (arm_structure_size_boundary
!= 8
3536 && arm_structure_size_boundary
!= 32
3537 && !(ARM_DOUBLEWORD_ALIGN
&& arm_structure_size_boundary
== 64))
3539 if (ARM_DOUBLEWORD_ALIGN
)
3541 "structure size boundary can only be set to 8, 32 or 64");
3543 warning (0, "structure size boundary can only be set to 8 or 32");
3544 arm_structure_size_boundary
3545 = (TARGET_AAPCS_BASED
? 8 : DEFAULT_STRUCTURE_SIZE_BOUNDARY
);
3549 if (TARGET_VXWORKS_RTP
)
3551 if (!global_options_set
.x_arm_pic_data_is_text_relative
)
3552 arm_pic_data_is_text_relative
= 0;
3555 && !arm_pic_data_is_text_relative
3556 && !(global_options_set
.x_target_flags
& MASK_SINGLE_PIC_BASE
))
3557 /* When text & data segments don't have a fixed displacement, the
3558 intended use is with a single, read only, pic base register.
3559 Unless the user explicitly requested not to do that, set
3561 target_flags
|= MASK_SINGLE_PIC_BASE
;
3563 /* If stack checking is disabled, we can use r10 as the PIC register,
3564 which keeps r9 available. The EABI specifies r9 as the PIC register. */
3565 if (flag_pic
&& TARGET_SINGLE_PIC_BASE
)
3567 if (TARGET_VXWORKS_RTP
)
3568 warning (0, "RTP PIC is incompatible with %<-msingle-pic-base%>");
3569 arm_pic_register
= (TARGET_APCS_STACK
|| TARGET_AAPCS_BASED
) ? 9 : 10;
3572 if (flag_pic
&& TARGET_VXWORKS_RTP
)
3573 arm_pic_register
= 9;
3575 /* If in FDPIC mode then force arm_pic_register to be r9. */
3578 arm_pic_register
= FDPIC_REGNUM
;
3580 sorry ("FDPIC mode is not supported in Thumb-1 mode");
3583 if (arm_pic_register_string
!= NULL
)
3585 int pic_register
= decode_reg_name (arm_pic_register_string
);
3588 warning (0, "%<-mpic-register=%> is useless without %<-fpic%>");
3590 /* Prevent the user from choosing an obviously stupid PIC register. */
3591 else if (pic_register
< 0 || call_used_or_fixed_reg_p (pic_register
)
3592 || pic_register
== HARD_FRAME_POINTER_REGNUM
3593 || pic_register
== STACK_POINTER_REGNUM
3594 || pic_register
>= PC_REGNUM
3595 || (TARGET_VXWORKS_RTP
3596 && (unsigned int) pic_register
!= arm_pic_register
))
3597 error ("unable to use %qs for PIC register", arm_pic_register_string
);
3599 arm_pic_register
= pic_register
;
3603 target_word_relocations
= 1;
3605 /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */
3606 if (fix_cm3_ldrd
== 2)
3608 if (bitmap_bit_p (arm_active_target
.isa
, isa_bit_quirk_cm3_ldrd
))
3614 /* Hot/Cold partitioning is not currently supported, since we can't
3615 handle literal pool placement in that case. */
3616 if (flag_reorder_blocks_and_partition
)
3618 inform (input_location
,
3619 "%<-freorder-blocks-and-partition%> not supported "
3620 "on this architecture");
3621 flag_reorder_blocks_and_partition
= 0;
3622 flag_reorder_blocks
= 1;
3626 /* Hoisting PIC address calculations more aggressively provides a small,
3627 but measurable, size reduction for PIC code. Therefore, we decrease
3628 the bar for unrestricted expression hoisting to the cost of PIC address
3629 calculation, which is 2 instructions. */
3630 SET_OPTION_IF_UNSET (&global_options
, &global_options_set
,
3631 param_gcse_unrestricted_cost
, 2);
3633 /* ARM EABI defaults to strict volatile bitfields. */
3634 if (TARGET_AAPCS_BASED
&& flag_strict_volatile_bitfields
< 0
3635 && abi_version_at_least(2))
3636 flag_strict_volatile_bitfields
= 1;
3638 /* Enable sw prefetching at -O3 for CPUS that have prefetch, and we
3639 have deemed it beneficial (signified by setting
3640 prefetch.num_slots to 1 or more). */
3641 if (flag_prefetch_loop_arrays
< 0
3644 && current_tune
->prefetch
.num_slots
> 0)
3645 flag_prefetch_loop_arrays
= 1;
3647 /* Set up parameters to be used in prefetching algorithm. Do not
3648 override the defaults unless we are tuning for a core we have
3649 researched values for. */
3650 if (current_tune
->prefetch
.num_slots
> 0)
3651 SET_OPTION_IF_UNSET (&global_options
, &global_options_set
,
3652 param_simultaneous_prefetches
,
3653 current_tune
->prefetch
.num_slots
);
3654 if (current_tune
->prefetch
.l1_cache_line_size
>= 0)
3655 SET_OPTION_IF_UNSET (&global_options
, &global_options_set
,
3656 param_l1_cache_line_size
,
3657 current_tune
->prefetch
.l1_cache_line_size
);
3658 if (current_tune
->prefetch
.l1_cache_size
>= 0)
3659 SET_OPTION_IF_UNSET (&global_options
, &global_options_set
,
3660 param_l1_cache_size
,
3661 current_tune
->prefetch
.l1_cache_size
);
3663 /* Look through ready list and all of queue for instructions
3664 relevant for L2 auto-prefetcher. */
3665 int sched_autopref_queue_depth
;
3667 switch (current_tune
->sched_autopref
)
3669 case tune_params::SCHED_AUTOPREF_OFF
:
3670 sched_autopref_queue_depth
= -1;
3673 case tune_params::SCHED_AUTOPREF_RANK
:
3674 sched_autopref_queue_depth
= 0;
3677 case tune_params::SCHED_AUTOPREF_FULL
:
3678 sched_autopref_queue_depth
= max_insn_queue_index
+ 1;
3685 SET_OPTION_IF_UNSET (&global_options
, &global_options_set
,
3686 param_sched_autopref_queue_depth
,
3687 sched_autopref_queue_depth
);
3689 /* Currently, for slow flash data, we just disable literal pools. We also
3690 disable it for pure-code. */
3691 if (target_slow_flash_data
|| target_pure_code
)
3692 arm_disable_literal_pool
= true;
3694 /* Disable scheduling fusion by default if it's not armv7 processor
3695 or doesn't prefer ldrd/strd. */
3696 if (flag_schedule_fusion
== 2
3697 && (!arm_arch7
|| !current_tune
->prefer_ldrd_strd
))
3698 flag_schedule_fusion
= 0;
3700 /* Need to remember initial options before they are overriden. */
3701 init_optimize
= build_optimization_node (&global_options
,
3702 &global_options_set
);
3704 arm_options_perform_arch_sanity_checks ();
3705 arm_option_override_internal (&global_options
, &global_options_set
);
3706 arm_option_check_internal (&global_options
);
3707 arm_option_params_internal ();
3709 /* Create the default target_options structure. */
3710 target_option_default_node
= target_option_current_node
3711 = build_target_option_node (&global_options
, &global_options_set
);
3713 /* Register global variables with the garbage collector. */
3714 arm_add_gc_roots ();
3716 /* Init initial mode for testing. */
3717 thumb_flipper
= TARGET_THUMB
;
3721 /* Reconfigure global status flags from the active_target.isa. */
3723 arm_option_reconfigure_globals (void)
3725 sprintf (arm_arch_name
, "__ARM_ARCH_%s__", arm_active_target
.arch_pp_name
);
3726 arm_base_arch
= arm_active_target
.base_arch
;
3728 /* Initialize boolean versions of the architectural flags, for use
3729 in the arm.md file. */
3730 arm_arch4
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_armv4
);
3731 arm_arch4t
= arm_arch4
&& bitmap_bit_p (arm_active_target
.isa
, isa_bit_thumb
);
3732 arm_arch5t
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_armv5t
);
3733 arm_arch5te
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_armv5te
);
3734 arm_arch6
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_armv6
);
3735 arm_arch6k
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_armv6k
);
3736 arm_arch_notm
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_notm
);
3737 arm_arch6m
= arm_arch6
&& !arm_arch_notm
;
3738 arm_arch7
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_armv7
);
3739 arm_arch7em
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_armv7em
);
3740 arm_arch8
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_armv8
);
3741 arm_arch8_1
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_armv8_1
);
3742 arm_arch8_2
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_armv8_2
);
3743 arm_arch8_3
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_armv8_3
);
3744 arm_arch8_4
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_armv8_4
);
3745 arm_arch8_1m_main
= bitmap_bit_p (arm_active_target
.isa
,
3746 isa_bit_armv8_1m_main
);
3747 arm_arch_thumb1
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_thumb
);
3748 arm_arch_thumb2
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_thumb2
);
3749 arm_arch_xscale
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_xscale
);
3750 arm_arch_iwmmxt
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_iwmmxt
);
3751 arm_arch_iwmmxt2
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_iwmmxt2
);
3752 arm_arch_thumb_hwdiv
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_tdiv
);
3753 arm_arch_arm_hwdiv
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_adiv
);
3754 arm_arch_crc
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_crc32
);
3755 arm_arch_cmse
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_cmse
);
3756 arm_arch_lpae
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_lpae
);
3757 arm_arch_i8mm
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_i8mm
);
3758 arm_arch_bf16
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_bf16
);
3760 arm_fp16_inst
= bitmap_bit_p (arm_active_target
.isa
, isa_bit_fp16
);
3763 if (arm_fp16_format
== ARM_FP16_FORMAT_ALTERNATIVE
)
3764 error ("selected fp16 options are incompatible");
3765 arm_fp16_format
= ARM_FP16_FORMAT_IEEE
;
3769 arm_arch_cde_coproc
= 0;
3770 int cde_bits
[] = {isa_bit_cdecp0
, isa_bit_cdecp1
, isa_bit_cdecp2
,
3771 isa_bit_cdecp3
, isa_bit_cdecp4
, isa_bit_cdecp5
,
3772 isa_bit_cdecp6
, isa_bit_cdecp7
};
3773 for (int i
= 0, e
= ARRAY_SIZE (cde_bits
); i
< e
; i
++)
3775 int cde_bit
= bitmap_bit_p (arm_active_target
.isa
, cde_bits
[i
]);
3778 arm_arch_cde
|= cde_bit
;
3779 arm_arch_cde_coproc
|= arm_arch_cde_coproc_bits
[i
];
3783 /* And finally, set up some quirks. */
3784 arm_arch_no_volatile_ce
3785 = bitmap_bit_p (arm_active_target
.isa
, isa_bit_quirk_no_volatile_ce
);
3786 arm_arch6kz
= arm_arch6k
&& bitmap_bit_p (arm_active_target
.isa
,
3787 isa_bit_quirk_armv6kz
);
3789 /* Use the cp15 method if it is available. */
3790 if (target_thread_pointer
== TP_AUTO
)
3792 if (arm_arch6k
&& !TARGET_THUMB1
)
3793 target_thread_pointer
= TP_CP15
;
3795 target_thread_pointer
= TP_SOFT
;
3799 /* Perform some validation between the desired architecture and the rest of the
3802 arm_options_perform_arch_sanity_checks (void)
3804 /* V5T code we generate is completely interworking capable, so we turn off
3805 TARGET_INTERWORK here to avoid many tests later on. */
3807 /* XXX However, we must pass the right pre-processor defines to CPP
3808 or GLD can get confused. This is a hack. */
3809 if (TARGET_INTERWORK
)
3810 arm_cpp_interwork
= 1;
3813 target_flags
&= ~MASK_INTERWORK
;
3815 if (TARGET_IWMMXT
&& !ARM_DOUBLEWORD_ALIGN
)
3816 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
3818 if (TARGET_IWMMXT_ABI
&& !TARGET_IWMMXT
)
3819 error ("iwmmxt abi requires an iwmmxt capable cpu");
3821 /* BPABI targets use linker tricks to allow interworking on cores
3822 without thumb support. */
3823 if (TARGET_INTERWORK
3825 && !bitmap_bit_p (arm_active_target
.isa
, isa_bit_thumb
))
3827 warning (0, "target CPU does not support interworking" );
3828 target_flags
&= ~MASK_INTERWORK
;
3831 /* If soft-float is specified then don't use FPU. */
3832 if (TARGET_SOFT_FLOAT
)
3833 arm_fpu_attr
= FPU_NONE
;
3835 arm_fpu_attr
= FPU_VFP
;
3837 if (TARGET_AAPCS_BASED
)
3839 if (TARGET_CALLER_INTERWORKING
)
3840 error ("AAPCS does not support %<-mcaller-super-interworking%>");
3842 if (TARGET_CALLEE_INTERWORKING
)
3843 error ("AAPCS does not support %<-mcallee-super-interworking%>");
3846 /* __fp16 support currently assumes the core has ldrh. */
3847 if (!arm_arch4
&& arm_fp16_format
!= ARM_FP16_FORMAT_NONE
)
3848 sorry ("__fp16 and no ldrh");
3850 if (use_cmse
&& !arm_arch_cmse
)
3851 error ("target CPU does not support ARMv8-M Security Extensions");
3853 /* We don't clear D16-D31 VFP registers for cmse_nonsecure_call functions
3854 and ARMv8-M Baseline and Mainline do not allow such configuration. */
3855 if (use_cmse
&& TARGET_HARD_FLOAT
&& LAST_VFP_REGNUM
> LAST_LO_VFP_REGNUM
)
3856 error ("ARMv8-M Security Extensions incompatible with selected FPU");
3859 if (TARGET_AAPCS_BASED
)
3861 if (arm_abi
== ARM_ABI_IWMMXT
)
3862 arm_pcs_default
= ARM_PCS_AAPCS_IWMMXT
;
3863 else if (TARGET_HARD_FLOAT_ABI
)
3865 arm_pcs_default
= ARM_PCS_AAPCS_VFP
;
3866 if (!bitmap_bit_p (arm_active_target
.isa
, isa_bit_vfpv2
)
3867 && !bitmap_bit_p (arm_active_target
.isa
, isa_bit_mve
))
3868 error ("%<-mfloat-abi=hard%>: selected architecture lacks an FPU");
3871 arm_pcs_default
= ARM_PCS_AAPCS
;
3875 if (arm_float_abi
== ARM_FLOAT_ABI_HARD
)
3876 sorry ("%<-mfloat-abi=hard%> and VFP");
3878 if (arm_abi
== ARM_ABI_APCS
)
3879 arm_pcs_default
= ARM_PCS_APCS
;
3881 arm_pcs_default
= ARM_PCS_ATPCS
;
3885 /* Test whether a local function descriptor is canonical, i.e.,
3886 whether we can use GOTOFFFUNCDESC to compute the address of the
3889 arm_fdpic_local_funcdesc_p (rtx fnx
)
3892 enum symbol_visibility vis
;
3898 if (! SYMBOL_REF_LOCAL_P (fnx
))
3901 fn
= SYMBOL_REF_DECL (fnx
);
3906 vis
= DECL_VISIBILITY (fn
);
3908 if (vis
== VISIBILITY_PROTECTED
)
3909 /* Private function descriptors for protected functions are not
3910 canonical. Temporarily change the visibility to global so that
3911 we can ensure uniqueness of funcdesc pointers. */
3912 DECL_VISIBILITY (fn
) = VISIBILITY_DEFAULT
;
3914 ret
= default_binds_local_p_1 (fn
, flag_pic
);
3916 DECL_VISIBILITY (fn
) = vis
;
3922 arm_add_gc_roots (void)
3924 gcc_obstack_init(&minipool_obstack
);
3925 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
3928 /* A table of known ARM exception types.
3929 For use with the interrupt function attribute. */
3933 const char *const arg
;
3934 const unsigned long return_value
;
3938 static const isr_attribute_arg isr_attribute_args
[] =
3940 { "IRQ", ARM_FT_ISR
},
3941 { "irq", ARM_FT_ISR
},
3942 { "FIQ", ARM_FT_FIQ
},
3943 { "fiq", ARM_FT_FIQ
},
3944 { "ABORT", ARM_FT_ISR
},
3945 { "abort", ARM_FT_ISR
},
3946 { "UNDEF", ARM_FT_EXCEPTION
},
3947 { "undef", ARM_FT_EXCEPTION
},
3948 { "SWI", ARM_FT_EXCEPTION
},
3949 { "swi", ARM_FT_EXCEPTION
},
3950 { NULL
, ARM_FT_NORMAL
}
3953 /* Returns the (interrupt) function type of the current
3954 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
3956 static unsigned long
3957 arm_isr_value (tree argument
)
3959 const isr_attribute_arg
* ptr
;
3963 return ARM_FT_NORMAL
| ARM_FT_STACKALIGN
;
3965 /* No argument - default to IRQ. */
3966 if (argument
== NULL_TREE
)
3969 /* Get the value of the argument. */
3970 if (TREE_VALUE (argument
) == NULL_TREE
3971 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
3972 return ARM_FT_UNKNOWN
;
3974 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
3976 /* Check it against the list of known arguments. */
3977 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
3978 if (streq (arg
, ptr
->arg
))
3979 return ptr
->return_value
;
3981 /* An unrecognized interrupt type. */
3982 return ARM_FT_UNKNOWN
;
3985 /* Computes the type of the current function. */
3987 static unsigned long
3988 arm_compute_func_type (void)
3990 unsigned long type
= ARM_FT_UNKNOWN
;
3994 gcc_assert (TREE_CODE (current_function_decl
) == FUNCTION_DECL
);
3996 /* Decide if the current function is volatile. Such functions
3997 never return, and many memory cycles can be saved by not storing
3998 register values that will never be needed again. This optimization
3999 was added to speed up context switching in a kernel application. */
4001 && (TREE_NOTHROW (current_function_decl
)
4002 || !(flag_unwind_tables
4004 && arm_except_unwind_info (&global_options
) != UI_SJLJ
)))
4005 && TREE_THIS_VOLATILE (current_function_decl
))
4006 type
|= ARM_FT_VOLATILE
;
4008 if (cfun
->static_chain_decl
!= NULL
)
4009 type
|= ARM_FT_NESTED
;
4011 attr
= DECL_ATTRIBUTES (current_function_decl
);
4013 a
= lookup_attribute ("naked", attr
);
4015 type
|= ARM_FT_NAKED
;
4017 a
= lookup_attribute ("isr", attr
);
4019 a
= lookup_attribute ("interrupt", attr
);
4022 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
4024 type
|= arm_isr_value (TREE_VALUE (a
));
4026 if (lookup_attribute ("cmse_nonsecure_entry", attr
))
4027 type
|= ARM_FT_CMSE_ENTRY
;
4032 /* Returns the type of the current function. */
4035 arm_current_func_type (void)
4037 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
4038 cfun
->machine
->func_type
= arm_compute_func_type ();
4040 return cfun
->machine
->func_type
;
4044 arm_allocate_stack_slots_for_args (void)
4046 /* Naked functions should not allocate stack slots for arguments. */
4047 return !IS_NAKED (arm_current_func_type ());
4051 arm_warn_func_return (tree decl
)
4053 /* Naked functions are implemented entirely in assembly, including the
4054 return sequence, so suppress warnings about this. */
4055 return lookup_attribute ("naked", DECL_ATTRIBUTES (decl
)) == NULL_TREE
;
4059 /* Output assembler code for a block containing the constant parts
4060 of a trampoline, leaving space for the variable parts.
4062 On the ARM, (if r8 is the static chain regnum, and remembering that
4063 referencing pc adds an offset of 8) the trampoline looks like:
4066 .word static chain value
4067 .word function's address
4068 XXX FIXME: When the trampoline returns, r8 will be clobbered.
4070 In FDPIC mode, the trampoline looks like:
4071 .word trampoline address
4072 .word trampoline GOT address
4073 ldr r12, [pc, #8] ; #4 for Arm mode
4074 ldr r9, [pc, #8] ; #4 for Arm mode
4075 ldr pc, [pc, #8] ; #4 for Arm mode
4076 .word static chain value
4078 .word function's address
4082 arm_asm_trampoline_template (FILE *f
)
4084 fprintf (f
, "\t.syntax unified\n");
4088 /* The first two words are a function descriptor pointing to the
4089 trampoline code just below. */
4091 fprintf (f
, "\t.arm\n");
4092 else if (TARGET_THUMB2
)
4093 fprintf (f
, "\t.thumb\n");
4095 /* Only ARM and Thumb-2 are supported. */
4098 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
4099 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
4100 /* Trampoline code which sets the static chain register but also
4101 PIC register before jumping into real code. */
4102 asm_fprintf (f
, "\tldr\t%r, [%r, #%d]\n",
4103 STATIC_CHAIN_REGNUM
, PC_REGNUM
,
4104 TARGET_THUMB2
? 8 : 4);
4105 asm_fprintf (f
, "\tldr\t%r, [%r, #%d]\n",
4106 PIC_OFFSET_TABLE_REGNUM
, PC_REGNUM
,
4107 TARGET_THUMB2
? 8 : 4);
4108 asm_fprintf (f
, "\tldr\t%r, [%r, #%d]\n",
4109 PC_REGNUM
, PC_REGNUM
,
4110 TARGET_THUMB2
? 8 : 4);
4111 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
4113 else if (TARGET_ARM
)
4115 fprintf (f
, "\t.arm\n");
4116 asm_fprintf (f
, "\tldr\t%r, [%r, #0]\n", STATIC_CHAIN_REGNUM
, PC_REGNUM
);
4117 asm_fprintf (f
, "\tldr\t%r, [%r, #0]\n", PC_REGNUM
, PC_REGNUM
);
4119 else if (TARGET_THUMB2
)
4121 fprintf (f
, "\t.thumb\n");
4122 /* The Thumb-2 trampoline is similar to the arm implementation.
4123 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
4124 asm_fprintf (f
, "\tldr.w\t%r, [%r, #4]\n",
4125 STATIC_CHAIN_REGNUM
, PC_REGNUM
);
4126 asm_fprintf (f
, "\tldr.w\t%r, [%r, #4]\n", PC_REGNUM
, PC_REGNUM
);
4130 ASM_OUTPUT_ALIGN (f
, 2);
4131 fprintf (f
, "\t.code\t16\n");
4132 fprintf (f
, ".Ltrampoline_start:\n");
4133 asm_fprintf (f
, "\tpush\t{r0, r1}\n");
4134 asm_fprintf (f
, "\tldr\tr0, [%r, #8]\n", PC_REGNUM
);
4135 asm_fprintf (f
, "\tmov\t%r, r0\n", STATIC_CHAIN_REGNUM
);
4136 asm_fprintf (f
, "\tldr\tr0, [%r, #8]\n", PC_REGNUM
);
4137 asm_fprintf (f
, "\tstr\tr0, [%r, #4]\n", SP_REGNUM
);
4138 asm_fprintf (f
, "\tpop\t{r0, %r}\n", PC_REGNUM
);
4140 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
4141 assemble_aligned_integer (UNITS_PER_WORD
, const0_rtx
);
4144 /* Emit RTL insns to initialize the variable parts of a trampoline. */
4147 arm_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
4149 rtx fnaddr
, mem
, a_tramp
;
4151 emit_block_move (m_tramp
, assemble_trampoline_template (),
4152 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
4156 rtx funcdesc
= XEXP (DECL_RTL (fndecl
), 0);
4157 rtx fnaddr
= gen_rtx_MEM (Pmode
, funcdesc
);
4158 rtx gotaddr
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
, funcdesc
, 4));
4159 /* The function start address is at offset 8, but in Thumb mode
4160 we want bit 0 set to 1 to indicate Thumb-ness, hence 9
4162 rtx trampoline_code_start
4163 = plus_constant (Pmode
, XEXP (m_tramp
, 0), TARGET_THUMB2
? 9 : 8);
4165 /* Write initial funcdesc which points to the trampoline. */
4166 mem
= adjust_address (m_tramp
, SImode
, 0);
4167 emit_move_insn (mem
, trampoline_code_start
);
4168 mem
= adjust_address (m_tramp
, SImode
, 4);
4169 emit_move_insn (mem
, gen_rtx_REG (Pmode
, PIC_OFFSET_TABLE_REGNUM
));
4170 /* Setup static chain. */
4171 mem
= adjust_address (m_tramp
, SImode
, 20);
4172 emit_move_insn (mem
, chain_value
);
4173 /* GOT + real function entry point. */
4174 mem
= adjust_address (m_tramp
, SImode
, 24);
4175 emit_move_insn (mem
, gotaddr
);
4176 mem
= adjust_address (m_tramp
, SImode
, 28);
4177 emit_move_insn (mem
, fnaddr
);
4181 mem
= adjust_address (m_tramp
, SImode
, TARGET_32BIT
? 8 : 12);
4182 emit_move_insn (mem
, chain_value
);
4184 mem
= adjust_address (m_tramp
, SImode
, TARGET_32BIT
? 12 : 16);
4185 fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
4186 emit_move_insn (mem
, fnaddr
);
4189 a_tramp
= XEXP (m_tramp
, 0);
4190 maybe_emit_call_builtin___clear_cache (a_tramp
,
4191 plus_constant (ptr_mode
,
4196 /* Thumb trampolines should be entered in thumb mode, so set
4197 the bottom bit of the address. */
4200 arm_trampoline_adjust_address (rtx addr
)
4202 /* For FDPIC don't fix trampoline address since it's a function
4203 descriptor and not a function address. */
4204 if (TARGET_THUMB
&& !TARGET_FDPIC
)
4205 addr
= expand_simple_binop (Pmode
, IOR
, addr
, const1_rtx
,
4206 NULL
, 0, OPTAB_LIB_WIDEN
);
4210 /* Return 1 if REG needs to be saved. For interrupt handlers, this
4211 includes call-clobbered registers too. If this is a leaf function
4212 we can just examine the registers used by the RTL, but otherwise we
4213 have to assume that whatever function is called might clobber
4214 anything, and so we have to save all the call-clobbered registers
4216 static inline bool reg_needs_saving_p (unsigned reg
)
4218 unsigned long func_type
= arm_current_func_type ();
4220 if (IS_INTERRUPT (func_type
))
4221 if (df_regs_ever_live_p (reg
)
4222 /* Save call-clobbered core registers. */
4223 || (! crtl
->is_leaf
&& call_used_or_fixed_reg_p (reg
) && reg
< FIRST_VFP_REGNUM
))
4228 if (!df_regs_ever_live_p (reg
)
4229 || call_used_or_fixed_reg_p (reg
))
4235 /* Return 1 if it is possible to return using a single instruction.
4236 If SIBLING is non-null, this is a test for a return before a sibling
4237 call. SIBLING is the call insn, so we can examine its register usage. */
4240 use_return_insn (int iscond
, rtx sibling
)
4243 unsigned int func_type
;
4244 unsigned long saved_int_regs
;
4245 unsigned HOST_WIDE_INT stack_adjust
;
4246 arm_stack_offsets
*offsets
;
4248 /* Never use a return instruction before reload has run. */
4249 if (!reload_completed
)
4252 func_type
= arm_current_func_type ();
4254 /* Naked, volatile and stack alignment functions need special
4256 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
| ARM_FT_STACKALIGN
))
4259 /* So do interrupt functions that use the frame pointer and Thumb
4260 interrupt functions. */
4261 if (IS_INTERRUPT (func_type
) && (frame_pointer_needed
|| TARGET_THUMB
))
4264 if (TARGET_LDRD
&& current_tune
->prefer_ldrd_strd
4265 && !optimize_function_for_size_p (cfun
))
4268 offsets
= arm_get_frame_offsets ();
4269 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
4271 /* As do variadic functions. */
4272 if (crtl
->args
.pretend_args_size
4273 || cfun
->machine
->uses_anonymous_args
4274 /* Or if the function calls __builtin_eh_return () */
4275 || crtl
->calls_eh_return
4276 /* Or if the function calls alloca */
4277 || cfun
->calls_alloca
4278 /* Or if there is a stack adjustment. However, if the stack pointer
4279 is saved on the stack, we can use a pre-incrementing stack load. */
4280 || !(stack_adjust
== 0 || (TARGET_APCS_FRAME
&& frame_pointer_needed
4281 && stack_adjust
== 4))
4282 /* Or if the static chain register was saved above the frame, under the
4283 assumption that the stack pointer isn't saved on the stack. */
4284 || (!(TARGET_APCS_FRAME
&& frame_pointer_needed
)
4285 && arm_compute_static_chain_stack_bytes() != 0))
4288 saved_int_regs
= offsets
->saved_regs_mask
;
4290 /* Unfortunately, the insn
4292 ldmib sp, {..., sp, ...}
4294 triggers a bug on most SA-110 based devices, such that the stack
4295 pointer won't be correctly restored if the instruction takes a
4296 page fault. We work around this problem by popping r3 along with
4297 the other registers, since that is never slower than executing
4298 another instruction.
4300 We test for !arm_arch5t here, because code for any architecture
4301 less than this could potentially be run on one of the buggy
4303 if (stack_adjust
== 4 && !arm_arch5t
&& TARGET_ARM
)
4305 /* Validate that r3 is a call-clobbered register (always true in
4306 the default abi) ... */
4307 if (!call_used_or_fixed_reg_p (3))
4310 /* ... that it isn't being used for a return value ... */
4311 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD
))
4314 /* ... or for a tail-call argument ... */
4317 gcc_assert (CALL_P (sibling
));
4319 if (find_regno_fusage (sibling
, USE
, 3))
4323 /* ... and that there are no call-saved registers in r0-r2
4324 (always true in the default ABI). */
4325 if (saved_int_regs
& 0x7)
4329 /* Can't be done if interworking with Thumb, and any registers have been
4331 if (TARGET_INTERWORK
&& saved_int_regs
!= 0 && !IS_INTERRUPT(func_type
))
4334 /* On StrongARM, conditional returns are expensive if they aren't
4335 taken and multiple registers have been stacked. */
4336 if (iscond
&& arm_tune_strongarm
)
4338 /* Conditional return when just the LR is stored is a simple
4339 conditional-load instruction, that's not expensive. */
4340 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
4344 && arm_pic_register
!= INVALID_REGNUM
4345 && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
4349 /* ARMv8-M nonsecure entry function need to use bxns to return and thus need
4350 several instructions if anything needs to be popped. Armv8.1-M Mainline
4351 also needs several instructions to save and restore FP context. */
4352 if (IS_CMSE_ENTRY (func_type
) && (saved_int_regs
|| TARGET_HAVE_FPCXT_CMSE
))
4355 /* If there are saved registers but the LR isn't saved, then we need
4356 two instructions for the return. */
4357 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
4360 /* Can't be done if any of the VFP regs are pushed,
4361 since this also requires an insn. */
4362 if (TARGET_VFP_BASE
)
4363 for (regno
= FIRST_VFP_REGNUM
; regno
<= LAST_VFP_REGNUM
; regno
++)
4364 if (reg_needs_saving_p (regno
))
4367 if (TARGET_REALLY_IWMMXT
)
4368 for (regno
= FIRST_IWMMXT_REGNUM
; regno
<= LAST_IWMMXT_REGNUM
; regno
++)
4369 if (reg_needs_saving_p (regno
))
4375 /* Return TRUE if we should try to use a simple_return insn, i.e. perform
4376 shrink-wrapping if possible. This is the case if we need to emit a
4377 prologue, which we can test by looking at the offsets. */
4379 use_simple_return_p (void)
4381 arm_stack_offsets
*offsets
;
4383 /* Note this function can be called before or after reload. */
4384 if (!reload_completed
)
4385 arm_compute_frame_layout ();
4387 offsets
= arm_get_frame_offsets ();
4388 return offsets
->outgoing_args
!= 0;
4391 /* Return TRUE if int I is a valid immediate ARM constant. */
4394 const_ok_for_arm (HOST_WIDE_INT i
)
4398 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
4399 be all zero, or all one. */
4400 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
4401 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
4402 != ((~(unsigned HOST_WIDE_INT
) 0)
4403 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
4406 i
&= (unsigned HOST_WIDE_INT
) 0xffffffff;
4408 /* Fast return for 0 and small values. We must do this for zero, since
4409 the code below can't handle that one case. */
4410 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xff) == 0)
4413 /* Get the number of trailing zeros. */
4414 lowbit
= ffs((int) i
) - 1;
4416 /* Only even shifts are allowed in ARM mode so round down to the
4417 nearest even number. */
4421 if ((i
& ~(((unsigned HOST_WIDE_INT
) 0xff) << lowbit
)) == 0)
4426 /* Allow rotated constants in ARM mode. */
4428 && ((i
& ~0xc000003f) == 0
4429 || (i
& ~0xf000000f) == 0
4430 || (i
& ~0xfc000003) == 0))
4433 else if (TARGET_THUMB2
)
4437 /* Allow repeated patterns 0x00XY00XY or 0xXYXYXYXY. */
4440 if (i
== v
|| i
== (v
| (v
<< 8)))
4443 /* Allow repeated pattern 0xXY00XY00. */
4449 else if (TARGET_HAVE_MOVT
)
4451 /* Thumb-1 Targets with MOVT. */
4461 /* Return true if I is a valid constant for the operation CODE. */
4463 const_ok_for_op (HOST_WIDE_INT i
, enum rtx_code code
)
4465 if (const_ok_for_arm (i
))
4471 /* See if we can use movw. */
4472 if (TARGET_HAVE_MOVT
&& (i
& 0xffff0000) == 0)
4475 /* Otherwise, try mvn. */
4476 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
4479 /* See if we can use addw or subw. */
4481 && ((i
& 0xfffff000) == 0
4482 || ((-i
) & 0xfffff000) == 0))
4503 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
4505 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
4511 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
4515 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
4522 /* Return true if I is a valid di mode constant for the operation CODE. */
4524 const_ok_for_dimode_op (HOST_WIDE_INT i
, enum rtx_code code
)
4526 HOST_WIDE_INT hi_val
= (i
>> 32) & 0xFFFFFFFF;
4527 HOST_WIDE_INT lo_val
= i
& 0xFFFFFFFF;
4528 rtx hi
= GEN_INT (hi_val
);
4529 rtx lo
= GEN_INT (lo_val
);
4539 return const_ok_for_op (hi_val
, code
) || hi_val
== 0xFFFFFFFF
4540 || const_ok_for_op (lo_val
, code
) || lo_val
== 0xFFFFFFFF;
4542 return arm_not_operand (hi
, SImode
) && arm_add_operand (lo
, SImode
);
4549 /* Emit a sequence of insns to handle a large constant.
4550 CODE is the code of the operation required, it can be any of SET, PLUS,
4551 IOR, AND, XOR, MINUS;
4552 MODE is the mode in which the operation is being performed;
4553 VAL is the integer to operate on;
4554 SOURCE is the other operand (a register, or a null-pointer for SET);
4555 SUBTARGETS means it is safe to create scratch registers if that will
4556 either produce a simpler sequence, or we will want to cse the values.
4557 Return value is the number of insns emitted. */
4559 /* ??? Tweak this for thumb2. */
4561 arm_split_constant (enum rtx_code code
, machine_mode mode
, rtx insn
,
4562 HOST_WIDE_INT val
, rtx target
, rtx source
, int subtargets
)
4566 if (insn
&& GET_CODE (PATTERN (insn
)) == COND_EXEC
)
4567 cond
= COND_EXEC_TEST (PATTERN (insn
));
4571 if (subtargets
|| code
== SET
4572 || (REG_P (target
) && REG_P (source
)
4573 && REGNO (target
) != REGNO (source
)))
4575 /* After arm_reorg has been called, we can't fix up expensive
4576 constants by pushing them into memory so we must synthesize
4577 them in-line, regardless of the cost. This is only likely to
4578 be more costly on chips that have load delay slots and we are
4579 compiling without running the scheduler (so no splitting
4580 occurred before the final instruction emission).
4582 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
4584 if (!cfun
->machine
->after_arm_reorg
4586 && (arm_gen_constant (code
, mode
, NULL_RTX
, val
, target
, source
,
4588 > (arm_constant_limit (optimize_function_for_size_p (cfun
))
4593 /* Currently SET is the only monadic value for CODE, all
4594 the rest are diadic. */
4595 if (TARGET_USE_MOVT
)
4596 arm_emit_movpair (target
, GEN_INT (val
));
4598 emit_set_insn (target
, GEN_INT (val
));
4604 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
4606 if (TARGET_USE_MOVT
)
4607 arm_emit_movpair (temp
, GEN_INT (val
));
4609 emit_set_insn (temp
, GEN_INT (val
));
4611 /* For MINUS, the value is subtracted from, since we never
4612 have subtraction of a constant. */
4614 emit_set_insn (target
, gen_rtx_MINUS (mode
, temp
, source
));
4616 emit_set_insn (target
,
4617 gen_rtx_fmt_ee (code
, mode
, source
, temp
));
4623 return arm_gen_constant (code
, mode
, cond
, val
, target
, source
, subtargets
,
4627 /* Return a sequence of integers, in RETURN_SEQUENCE that fit into
4628 ARM/THUMB2 immediates, and add up to VAL.
4629 Thr function return value gives the number of insns required. */
4631 optimal_immediate_sequence (enum rtx_code code
, unsigned HOST_WIDE_INT val
,
4632 struct four_ints
*return_sequence
)
4634 int best_consecutive_zeros
= 0;
4638 struct four_ints tmp_sequence
;
4640 /* If we aren't targeting ARM, the best place to start is always at
4641 the bottom, otherwise look more closely. */
4644 for (i
= 0; i
< 32; i
+= 2)
4646 int consecutive_zeros
= 0;
4648 if (!(val
& (3 << i
)))
4650 while ((i
< 32) && !(val
& (3 << i
)))
4652 consecutive_zeros
+= 2;
4655 if (consecutive_zeros
> best_consecutive_zeros
)
4657 best_consecutive_zeros
= consecutive_zeros
;
4658 best_start
= i
- consecutive_zeros
;
4665 /* So long as it won't require any more insns to do so, it's
4666 desirable to emit a small constant (in bits 0...9) in the last
4667 insn. This way there is more chance that it can be combined with
4668 a later addressing insn to form a pre-indexed load or store
4669 operation. Consider:
4671 *((volatile int *)0xe0000100) = 1;
4672 *((volatile int *)0xe0000110) = 2;
4674 We want this to wind up as:
4678 str rB, [rA, #0x100]
4680 str rB, [rA, #0x110]
4682 rather than having to synthesize both large constants from scratch.
4684 Therefore, we calculate how many insns would be required to emit
4685 the constant starting from `best_start', and also starting from
4686 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
4687 yield a shorter sequence, we may as well use zero. */
4688 insns1
= optimal_immediate_sequence_1 (code
, val
, return_sequence
, best_start
);
4690 && ((HOST_WIDE_INT_1U
<< best_start
) < val
))
4692 insns2
= optimal_immediate_sequence_1 (code
, val
, &tmp_sequence
, 0);
4693 if (insns2
<= insns1
)
4695 *return_sequence
= tmp_sequence
;
4703 /* As for optimal_immediate_sequence, but starting at bit-position I. */
4705 optimal_immediate_sequence_1 (enum rtx_code code
, unsigned HOST_WIDE_INT val
,
4706 struct four_ints
*return_sequence
, int i
)
4708 int remainder
= val
& 0xffffffff;
4711 /* Try and find a way of doing the job in either two or three
4714 In ARM mode we can use 8-bit constants, rotated to any 2-bit aligned
4715 location. We start at position I. This may be the MSB, or
4716 optimial_immediate_sequence may have positioned it at the largest block
4717 of zeros that are aligned on a 2-bit boundary. We then fill up the temps,
4718 wrapping around to the top of the word when we drop off the bottom.
4719 In the worst case this code should produce no more than four insns.
4721 In Thumb2 mode, we can use 32/16-bit replicated constants, and 8-bit
4722 constants, shifted to any arbitrary location. We should always start
4727 unsigned int b1
, b2
, b3
, b4
;
4728 unsigned HOST_WIDE_INT result
;
4731 gcc_assert (insns
< 4);
4736 /* First, find the next normal 12/8-bit shifted/rotated immediate. */
4737 if (remainder
& ((TARGET_ARM
? (3 << (i
- 2)) : (1 << (i
- 1)))))
4740 if (i
<= 12 && TARGET_THUMB2
&& code
== PLUS
)
4741 /* We can use addw/subw for the last 12 bits. */
4745 /* Use an 8-bit shifted/rotated immediate. */
4749 result
= remainder
& ((0x0ff << end
)
4750 | ((i
< end
) ? (0xff >> (32 - end
))
4757 /* Arm allows rotates by a multiple of two. Thumb-2 allows
4758 arbitrary shifts. */
4759 i
-= TARGET_ARM
? 2 : 1;
4763 /* Next, see if we can do a better job with a thumb2 replicated
4766 We do it this way around to catch the cases like 0x01F001E0 where
4767 two 8-bit immediates would work, but a replicated constant would
4770 TODO: 16-bit constants that don't clear all the bits, but still win.
4771 TODO: Arithmetic splitting for set/add/sub, rather than bitwise. */
4774 b1
= (remainder
& 0xff000000) >> 24;
4775 b2
= (remainder
& 0x00ff0000) >> 16;
4776 b3
= (remainder
& 0x0000ff00) >> 8;
4777 b4
= remainder
& 0xff;
4781 /* The 8-bit immediate already found clears b1 (and maybe b2),
4782 but must leave b3 and b4 alone. */
4784 /* First try to find a 32-bit replicated constant that clears
4785 almost everything. We can assume that we can't do it in one,
4786 or else we wouldn't be here. */
4787 unsigned int tmp
= b1
& b2
& b3
& b4
;
4788 unsigned int tmp2
= tmp
+ (tmp
<< 8) + (tmp
<< 16)
4790 unsigned int matching_bytes
= (tmp
== b1
) + (tmp
== b2
)
4791 + (tmp
== b3
) + (tmp
== b4
);
4793 && (matching_bytes
>= 3
4794 || (matching_bytes
== 2
4795 && const_ok_for_op (remainder
& ~tmp2
, code
))))
4797 /* At least 3 of the bytes match, and the fourth has at
4798 least as many bits set, or two of the bytes match
4799 and it will only require one more insn to finish. */
4807 /* Second, try to find a 16-bit replicated constant that can
4808 leave three of the bytes clear. If b2 or b4 is already
4809 zero, then we can. If the 8-bit from above would not
4810 clear b2 anyway, then we still win. */
4811 else if (b1
== b3
&& (!b2
|| !b4
4812 || (remainder
& 0x00ff0000 & ~result
)))
4814 result
= remainder
& 0xff00ff00;
4820 /* The 8-bit immediate already found clears b2 (and maybe b3)
4821 and we don't get here unless b1 is alredy clear, but it will
4822 leave b4 unchanged. */
4824 /* If we can clear b2 and b4 at once, then we win, since the
4825 8-bits couldn't possibly reach that far. */
4828 result
= remainder
& 0x00ff00ff;
4834 return_sequence
->i
[insns
++] = result
;
4835 remainder
&= ~result
;
4837 if (code
== SET
|| code
== MINUS
)
4845 /* Emit an instruction with the indicated PATTERN. If COND is
4846 non-NULL, conditionalize the execution of the instruction on COND
4850 emit_constant_insn (rtx cond
, rtx pattern
)
4853 pattern
= gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
), pattern
);
4854 emit_insn (pattern
);
4857 /* As above, but extra parameter GENERATE which, if clear, suppresses
4861 arm_gen_constant (enum rtx_code code
, machine_mode mode
, rtx cond
,
4862 unsigned HOST_WIDE_INT val
, rtx target
, rtx source
,
4863 int subtargets
, int generate
)
4867 int final_invert
= 0;
4869 int set_sign_bit_copies
= 0;
4870 int clear_sign_bit_copies
= 0;
4871 int clear_zero_bit_copies
= 0;
4872 int set_zero_bit_copies
= 0;
4873 int insns
= 0, neg_insns
, inv_insns
;
4874 unsigned HOST_WIDE_INT temp1
, temp2
;
4875 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
4876 struct four_ints
*immediates
;
4877 struct four_ints pos_immediates
, neg_immediates
, inv_immediates
;
4879 /* Find out which operations are safe for a given CODE. Also do a quick
4880 check for degenerate cases; these can occur when DImode operations
4893 if (remainder
== 0xffffffff)
4896 emit_constant_insn (cond
,
4897 gen_rtx_SET (target
,
4898 GEN_INT (ARM_SIGN_EXTEND (val
))));
4904 if (reload_completed
&& rtx_equal_p (target
, source
))
4908 emit_constant_insn (cond
, gen_rtx_SET (target
, source
));
4917 emit_constant_insn (cond
, gen_rtx_SET (target
, const0_rtx
));
4920 if (remainder
== 0xffffffff)
4922 if (reload_completed
&& rtx_equal_p (target
, source
))
4925 emit_constant_insn (cond
, gen_rtx_SET (target
, source
));
4934 if (reload_completed
&& rtx_equal_p (target
, source
))
4937 emit_constant_insn (cond
, gen_rtx_SET (target
, source
));
4941 if (remainder
== 0xffffffff)
4944 emit_constant_insn (cond
,
4945 gen_rtx_SET (target
,
4946 gen_rtx_NOT (mode
, source
)));
4953 /* We treat MINUS as (val - source), since (source - val) is always
4954 passed as (source + (-val)). */
4958 emit_constant_insn (cond
,
4959 gen_rtx_SET (target
,
4960 gen_rtx_NEG (mode
, source
)));
4963 if (const_ok_for_arm (val
))
4966 emit_constant_insn (cond
,
4967 gen_rtx_SET (target
,
4968 gen_rtx_MINUS (mode
, GEN_INT (val
),
4979 /* If we can do it in one insn get out quickly. */
4980 if (const_ok_for_op (val
, code
))
4983 emit_constant_insn (cond
,
4984 gen_rtx_SET (target
,
4986 ? gen_rtx_fmt_ee (code
, mode
, source
,
4992 /* On targets with UXTH/UBFX, we can deal with AND (2^N)-1 in a single
4994 if (code
== AND
&& (i
= exact_log2 (remainder
+ 1)) > 0
4995 && (arm_arch_thumb2
|| (i
== 16 && arm_arch6
&& mode
== SImode
)))
4999 if (mode
== SImode
&& i
== 16)
5000 /* Use UXTH in preference to UBFX, since on Thumb2 it's a
5002 emit_constant_insn (cond
,
5003 gen_zero_extendhisi2
5004 (target
, gen_lowpart (HImode
, source
)));
5006 /* Extz only supports SImode, but we can coerce the operands
5008 emit_constant_insn (cond
,
5009 gen_extzv_t2 (gen_lowpart (SImode
, target
),
5010 gen_lowpart (SImode
, source
),
5011 GEN_INT (i
), const0_rtx
));
5017 /* Calculate a few attributes that may be useful for specific
5019 /* Count number of leading zeros. */
5020 for (i
= 31; i
>= 0; i
--)
5022 if ((remainder
& (1 << i
)) == 0)
5023 clear_sign_bit_copies
++;
5028 /* Count number of leading 1's. */
5029 for (i
= 31; i
>= 0; i
--)
5031 if ((remainder
& (1 << i
)) != 0)
5032 set_sign_bit_copies
++;
5037 /* Count number of trailing zero's. */
5038 for (i
= 0; i
<= 31; i
++)
5040 if ((remainder
& (1 << i
)) == 0)
5041 clear_zero_bit_copies
++;
5046 /* Count number of trailing 1's. */
5047 for (i
= 0; i
<= 31; i
++)
5049 if ((remainder
& (1 << i
)) != 0)
5050 set_zero_bit_copies
++;
5058 /* See if we can do this by sign_extending a constant that is known
5059 to be negative. This is a good, way of doing it, since the shift
5060 may well merge into a subsequent insn. */
5061 if (set_sign_bit_copies
> 1)
5063 if (const_ok_for_arm
5064 (temp1
= ARM_SIGN_EXTEND (remainder
5065 << (set_sign_bit_copies
- 1))))
5069 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
5070 emit_constant_insn (cond
,
5071 gen_rtx_SET (new_src
, GEN_INT (temp1
)));
5072 emit_constant_insn (cond
,
5073 gen_ashrsi3 (target
, new_src
,
5074 GEN_INT (set_sign_bit_copies
- 1)));
5078 /* For an inverted constant, we will need to set the low bits,
5079 these will be shifted out of harm's way. */
5080 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
5081 if (const_ok_for_arm (~temp1
))
5085 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
5086 emit_constant_insn (cond
,
5087 gen_rtx_SET (new_src
, GEN_INT (temp1
)));
5088 emit_constant_insn (cond
,
5089 gen_ashrsi3 (target
, new_src
,
5090 GEN_INT (set_sign_bit_copies
- 1)));
5096 /* See if we can calculate the value as the difference between two
5097 valid immediates. */
5098 if (clear_sign_bit_copies
+ clear_zero_bit_copies
<= 16)
5100 int topshift
= clear_sign_bit_copies
& ~1;
5102 temp1
= ARM_SIGN_EXTEND ((remainder
+ (0x00800000 >> topshift
))
5103 & (0xff000000 >> topshift
));
5105 /* If temp1 is zero, then that means the 9 most significant
5106 bits of remainder were 1 and we've caused it to overflow.
5107 When topshift is 0 we don't need to do anything since we
5108 can borrow from 'bit 32'. */
5109 if (temp1
== 0 && topshift
!= 0)
5110 temp1
= 0x80000000 >> (topshift
- 1);
5112 temp2
= ARM_SIGN_EXTEND (temp1
- remainder
);
5114 if (const_ok_for_arm (temp2
))
5118 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
5119 emit_constant_insn (cond
,
5120 gen_rtx_SET (new_src
, GEN_INT (temp1
)));
5121 emit_constant_insn (cond
,
5122 gen_addsi3 (target
, new_src
,
5130 /* See if we can generate this by setting the bottom (or the top)
5131 16 bits, and then shifting these into the other half of the
5132 word. We only look for the simplest cases, to do more would cost
5133 too much. Be careful, however, not to generate this when the
5134 alternative would take fewer insns. */
5135 if (val
& 0xffff0000)
5137 temp1
= remainder
& 0xffff0000;
5138 temp2
= remainder
& 0x0000ffff;
5140 /* Overlaps outside this range are best done using other methods. */
5141 for (i
= 9; i
< 24; i
++)
5143 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
5144 && !const_ok_for_arm (temp2
))
5146 rtx new_src
= (subtargets
5147 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
5149 insns
= arm_gen_constant (code
, mode
, cond
, temp2
, new_src
,
5150 source
, subtargets
, generate
);
5158 gen_rtx_ASHIFT (mode
, source
,
5165 /* Don't duplicate cases already considered. */
5166 for (i
= 17; i
< 24; i
++)
5168 if (((temp1
| (temp1
>> i
)) == remainder
)
5169 && !const_ok_for_arm (temp1
))
5171 rtx new_src
= (subtargets
5172 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
5174 insns
= arm_gen_constant (code
, mode
, cond
, temp1
, new_src
,
5175 source
, subtargets
, generate
);
5180 gen_rtx_SET (target
,
5183 gen_rtx_LSHIFTRT (mode
, source
,
5194 /* If we have IOR or XOR, and the constant can be loaded in a
5195 single instruction, and we can find a temporary to put it in,
5196 then this can be done in two instructions instead of 3-4. */
5198 /* TARGET can't be NULL if SUBTARGETS is 0 */
5199 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
5201 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
5205 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
5207 emit_constant_insn (cond
,
5208 gen_rtx_SET (sub
, GEN_INT (val
)));
5209 emit_constant_insn (cond
,
5210 gen_rtx_SET (target
,
5211 gen_rtx_fmt_ee (code
, mode
,
5222 x = y | constant ( which is composed of set_sign_bit_copies of leading 1s
5223 and the remainder 0s for e.g. 0xfff00000)
5224 x = ~(~(y ashift set_sign_bit_copies) lshiftrt set_sign_bit_copies)
5226 This can be done in 2 instructions by using shifts with mov or mvn.
5231 mvn r0, r0, lsr #12 */
5232 if (set_sign_bit_copies
> 8
5233 && (val
& (HOST_WIDE_INT_M1U
<< (32 - set_sign_bit_copies
))) == val
)
5237 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
5238 rtx shift
= GEN_INT (set_sign_bit_copies
);
5244 gen_rtx_ASHIFT (mode
,
5249 gen_rtx_SET (target
,
5251 gen_rtx_LSHIFTRT (mode
, sub
,
5258 x = y | constant (which has set_zero_bit_copies number of trailing ones).
5260 x = ~((~y lshiftrt set_zero_bit_copies) ashift set_zero_bit_copies).
5262 For eg. r0 = r0 | 0xfff
5267 if (set_zero_bit_copies
> 8
5268 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
5272 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
5273 rtx shift
= GEN_INT (set_zero_bit_copies
);
5279 gen_rtx_LSHIFTRT (mode
,
5284 gen_rtx_SET (target
,
5286 gen_rtx_ASHIFT (mode
, sub
,
5292 /* This will never be reached for Thumb2 because orn is a valid
5293 instruction. This is for Thumb1 and the ARM 32 bit cases.
5295 x = y | constant (such that ~constant is a valid constant)
5297 x = ~(~y & ~constant).
5299 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
5303 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
5304 emit_constant_insn (cond
,
5306 gen_rtx_NOT (mode
, source
)));
5309 sub
= gen_reg_rtx (mode
);
5310 emit_constant_insn (cond
,
5312 gen_rtx_AND (mode
, source
,
5314 emit_constant_insn (cond
,
5315 gen_rtx_SET (target
,
5316 gen_rtx_NOT (mode
, sub
)));
5323 /* See if two shifts will do 2 or more insn's worth of work. */
5324 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
5326 HOST_WIDE_INT shift_mask
= ((0xffffffff
5327 << (32 - clear_sign_bit_copies
))
5330 if ((remainder
| shift_mask
) != 0xffffffff)
5332 HOST_WIDE_INT new_val
5333 = ARM_SIGN_EXTEND (remainder
| shift_mask
);
5337 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
5338 insns
= arm_gen_constant (AND
, SImode
, cond
, new_val
,
5339 new_src
, source
, subtargets
, 1);
5344 rtx targ
= subtargets
? NULL_RTX
: target
;
5345 insns
= arm_gen_constant (AND
, mode
, cond
, new_val
,
5346 targ
, source
, subtargets
, 0);
5352 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
5353 rtx shift
= GEN_INT (clear_sign_bit_copies
);
5355 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
5356 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
5362 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
5364 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
5366 if ((remainder
| shift_mask
) != 0xffffffff)
5368 HOST_WIDE_INT new_val
5369 = ARM_SIGN_EXTEND (remainder
| shift_mask
);
5372 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
5374 insns
= arm_gen_constant (AND
, mode
, cond
, new_val
,
5375 new_src
, source
, subtargets
, 1);
5380 rtx targ
= subtargets
? NULL_RTX
: target
;
5382 insns
= arm_gen_constant (AND
, mode
, cond
, new_val
,
5383 targ
, source
, subtargets
, 0);
5389 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
5390 rtx shift
= GEN_INT (clear_zero_bit_copies
);
5392 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
5393 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
5405 /* Calculate what the instruction sequences would be if we generated it
5406 normally, negated, or inverted. */
5408 /* AND cannot be split into multiple insns, so invert and use BIC. */
5411 insns
= optimal_immediate_sequence (code
, remainder
, &pos_immediates
);
5414 neg_insns
= optimal_immediate_sequence (code
, (-remainder
) & 0xffffffff,
5419 if (can_invert
|| final_invert
)
5420 inv_insns
= optimal_immediate_sequence (code
, remainder
^ 0xffffffff,
5425 immediates
= &pos_immediates
;
5427 /* Is the negated immediate sequence more efficient? */
5428 if (neg_insns
< insns
&& neg_insns
<= inv_insns
)
5431 immediates
= &neg_immediates
;
5436 /* Is the inverted immediate sequence more efficient?
5437 We must allow for an extra NOT instruction for XOR operations, although
5438 there is some chance that the final 'mvn' will get optimized later. */
5439 if ((inv_insns
+ 1) < insns
|| (!final_invert
&& inv_insns
< insns
))
5442 immediates
= &inv_immediates
;
5450 /* Now output the chosen sequence as instructions. */
5453 for (i
= 0; i
< insns
; i
++)
5455 rtx new_src
, temp1_rtx
;
5457 temp1
= immediates
->i
[i
];
5459 if (code
== SET
|| code
== MINUS
)
5460 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
5461 else if ((final_invert
|| i
< (insns
- 1)) && subtargets
)
5462 new_src
= gen_reg_rtx (mode
);
5468 else if (can_negate
)
5471 temp1
= trunc_int_for_mode (temp1
, mode
);
5472 temp1_rtx
= GEN_INT (temp1
);
5476 else if (code
== MINUS
)
5477 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
5479 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
5481 emit_constant_insn (cond
, gen_rtx_SET (new_src
, temp1_rtx
));
5486 can_negate
= can_invert
;
5490 else if (code
== MINUS
)
5498 emit_constant_insn (cond
, gen_rtx_SET (target
,
5499 gen_rtx_NOT (mode
, source
)));
5506 /* Return TRUE if op is a constant where both the low and top words are
5507 suitable for RSB/RSC instructions. This is never true for Thumb, since
5508 we do not have RSC in that case. */
5510 arm_const_double_prefer_rsbs_rsc (rtx op
)
5512 /* Thumb lacks RSC, so we never prefer that sequence. */
5513 if (TARGET_THUMB
|| !CONST_INT_P (op
))
5515 HOST_WIDE_INT hi
, lo
;
5516 lo
= UINTVAL (op
) & 0xffffffffULL
;
5517 hi
= UINTVAL (op
) >> 32;
5518 return const_ok_for_arm (lo
) && const_ok_for_arm (hi
);
5521 /* Canonicalize a comparison so that we are more likely to recognize it.
5522 This can be done for a few constant compares, where we can make the
5523 immediate value easier to load. */
5526 arm_canonicalize_comparison (int *code
, rtx
*op0
, rtx
*op1
,
5527 bool op0_preserve_value
)
5530 unsigned HOST_WIDE_INT i
, maxval
;
5532 mode
= GET_MODE (*op0
);
5533 if (mode
== VOIDmode
)
5534 mode
= GET_MODE (*op1
);
5536 maxval
= (HOST_WIDE_INT_1U
<< (GET_MODE_BITSIZE (mode
) - 1)) - 1;
5538 /* For DImode, we have GE/LT/GEU/LTU comparisons (with cmp/sbc). In
5539 ARM mode we can also use cmp/cmpeq for GTU/LEU. GT/LE must be
5540 either reversed or (for constant OP1) adjusted to GE/LT.
5541 Similarly for GTU/LEU in Thumb mode. */
5545 if (*code
== GT
|| *code
== LE
5546 || *code
== GTU
|| *code
== LEU
)
5548 /* Missing comparison. First try to use an available
5550 if (CONST_INT_P (*op1
))
5559 /* Try to convert to GE/LT, unless that would be more
5561 if (!arm_const_double_by_immediates (GEN_INT (i
+ 1))
5562 && arm_const_double_prefer_rsbs_rsc (*op1
))
5564 *op1
= GEN_INT (i
+ 1);
5565 *code
= *code
== GT
? GE
: LT
;
5572 if (i
!= ~((unsigned HOST_WIDE_INT
) 0))
5574 /* Try to convert to GEU/LTU, unless that would
5575 be more expensive. */
5576 if (!arm_const_double_by_immediates (GEN_INT (i
+ 1))
5577 && arm_const_double_prefer_rsbs_rsc (*op1
))
5579 *op1
= GEN_INT (i
+ 1);
5580 *code
= *code
== GTU
? GEU
: LTU
;
5590 if (!op0_preserve_value
)
5592 std::swap (*op0
, *op1
);
5593 *code
= (int)swap_condition ((enum rtx_code
)*code
);
5599 /* If *op0 is (zero_extend:SI (subreg:QI (reg:SI) 0)) and comparing
5600 with const0_rtx, change it to (and:SI (reg:SI) (const_int 255)),
5601 to facilitate possible combining with a cmp into 'ands'. */
5603 && GET_CODE (*op0
) == ZERO_EXTEND
5604 && GET_CODE (XEXP (*op0
, 0)) == SUBREG
5605 && GET_MODE (XEXP (*op0
, 0)) == QImode
5606 && GET_MODE (SUBREG_REG (XEXP (*op0
, 0))) == SImode
5607 && subreg_lowpart_p (XEXP (*op0
, 0))
5608 && *op1
== const0_rtx
)
5609 *op0
= gen_rtx_AND (SImode
, SUBREG_REG (XEXP (*op0
, 0)),
5612 /* Comparisons smaller than DImode. Only adjust comparisons against
5613 an out-of-range constant. */
5614 if (!CONST_INT_P (*op1
)
5615 || const_ok_for_arm (INTVAL (*op1
))
5616 || const_ok_for_arm (- INTVAL (*op1
)))
5630 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
5632 *op1
= GEN_INT (ARM_SIGN_EXTEND (i
+ 1));
5633 *code
= *code
== GT
? GE
: LT
;
5641 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
5643 *op1
= GEN_INT (i
- 1);
5644 *code
= *code
== GE
? GT
: LE
;
5651 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
5652 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
5654 *op1
= GEN_INT (ARM_SIGN_EXTEND (i
+ 1));
5655 *code
= *code
== GTU
? GEU
: LTU
;
5663 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
5665 *op1
= GEN_INT (i
- 1);
5666 *code
= *code
== GEU
? GTU
: LEU
;
5677 /* Define how to find the value returned by a function. */
5680 arm_function_value(const_tree type
, const_tree func
,
5681 bool outgoing ATTRIBUTE_UNUSED
)
5684 int unsignedp ATTRIBUTE_UNUSED
;
5685 rtx r ATTRIBUTE_UNUSED
;
5687 mode
= TYPE_MODE (type
);
5689 if (TARGET_AAPCS_BASED
)
5690 return aapcs_allocate_return_reg (mode
, type
, func
);
5692 /* Promote integer types. */
5693 if (INTEGRAL_TYPE_P (type
))
5694 mode
= arm_promote_function_mode (type
, mode
, &unsignedp
, func
, 1);
5696 /* Promotes small structs returned in a register to full-word size
5697 for big-endian AAPCS. */
5698 if (arm_return_in_msb (type
))
5700 HOST_WIDE_INT size
= int_size_in_bytes (type
);
5701 if (size
% UNITS_PER_WORD
!= 0)
5703 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5704 mode
= int_mode_for_size (size
* BITS_PER_UNIT
, 0).require ();
5708 return arm_libcall_value_1 (mode
);
5711 /* libcall hashtable helpers. */
5713 struct libcall_hasher
: nofree_ptr_hash
<const rtx_def
>
5715 static inline hashval_t
hash (const rtx_def
*);
5716 static inline bool equal (const rtx_def
*, const rtx_def
*);
5717 static inline void remove (rtx_def
*);
5721 libcall_hasher::equal (const rtx_def
*p1
, const rtx_def
*p2
)
5723 return rtx_equal_p (p1
, p2
);
5727 libcall_hasher::hash (const rtx_def
*p1
)
5729 return hash_rtx (p1
, VOIDmode
, NULL
, NULL
, FALSE
);
5732 typedef hash_table
<libcall_hasher
> libcall_table_type
;
5735 add_libcall (libcall_table_type
*htab
, rtx libcall
)
5737 *htab
->find_slot (libcall
, INSERT
) = libcall
;
5741 arm_libcall_uses_aapcs_base (const_rtx libcall
)
5743 static bool init_done
= false;
5744 static libcall_table_type
*libcall_htab
= NULL
;
5750 libcall_htab
= new libcall_table_type (31);
5751 add_libcall (libcall_htab
,
5752 convert_optab_libfunc (sfloat_optab
, SFmode
, SImode
));
5753 add_libcall (libcall_htab
,
5754 convert_optab_libfunc (sfloat_optab
, DFmode
, SImode
));
5755 add_libcall (libcall_htab
,
5756 convert_optab_libfunc (sfloat_optab
, SFmode
, DImode
));
5757 add_libcall (libcall_htab
,
5758 convert_optab_libfunc (sfloat_optab
, DFmode
, DImode
));
5760 add_libcall (libcall_htab
,
5761 convert_optab_libfunc (ufloat_optab
, SFmode
, SImode
));
5762 add_libcall (libcall_htab
,
5763 convert_optab_libfunc (ufloat_optab
, DFmode
, SImode
));
5764 add_libcall (libcall_htab
,
5765 convert_optab_libfunc (ufloat_optab
, SFmode
, DImode
));
5766 add_libcall (libcall_htab
,
5767 convert_optab_libfunc (ufloat_optab
, DFmode
, DImode
));
5769 add_libcall (libcall_htab
,
5770 convert_optab_libfunc (sext_optab
, SFmode
, HFmode
));
5771 add_libcall (libcall_htab
,
5772 convert_optab_libfunc (trunc_optab
, HFmode
, SFmode
));
5773 add_libcall (libcall_htab
,
5774 convert_optab_libfunc (sfix_optab
, SImode
, DFmode
));
5775 add_libcall (libcall_htab
,
5776 convert_optab_libfunc (ufix_optab
, SImode
, DFmode
));
5777 add_libcall (libcall_htab
,
5778 convert_optab_libfunc (sfix_optab
, DImode
, DFmode
));
5779 add_libcall (libcall_htab
,
5780 convert_optab_libfunc (ufix_optab
, DImode
, DFmode
));
5781 add_libcall (libcall_htab
,
5782 convert_optab_libfunc (sfix_optab
, DImode
, SFmode
));
5783 add_libcall (libcall_htab
,
5784 convert_optab_libfunc (ufix_optab
, DImode
, SFmode
));
5785 add_libcall (libcall_htab
,
5786 convert_optab_libfunc (sfix_optab
, SImode
, SFmode
));
5787 add_libcall (libcall_htab
,
5788 convert_optab_libfunc (ufix_optab
, SImode
, SFmode
));
5790 /* Values from double-precision helper functions are returned in core
5791 registers if the selected core only supports single-precision
5792 arithmetic, even if we are using the hard-float ABI. The same is
5793 true for single-precision helpers except in case of MVE, because in
5794 MVE we will be using the hard-float ABI on a CPU which doesn't support
5795 single-precision operations in hardware. In MVE the following check
5796 enables use of emulation for the single-precision arithmetic
5798 if (TARGET_HAVE_MVE
)
5800 add_libcall (libcall_htab
, optab_libfunc (add_optab
, SFmode
));
5801 add_libcall (libcall_htab
, optab_libfunc (sdiv_optab
, SFmode
));
5802 add_libcall (libcall_htab
, optab_libfunc (smul_optab
, SFmode
));
5803 add_libcall (libcall_htab
, optab_libfunc (neg_optab
, SFmode
));
5804 add_libcall (libcall_htab
, optab_libfunc (sub_optab
, SFmode
));
5805 add_libcall (libcall_htab
, optab_libfunc (eq_optab
, SFmode
));
5806 add_libcall (libcall_htab
, optab_libfunc (lt_optab
, SFmode
));
5807 add_libcall (libcall_htab
, optab_libfunc (le_optab
, SFmode
));
5808 add_libcall (libcall_htab
, optab_libfunc (ge_optab
, SFmode
));
5809 add_libcall (libcall_htab
, optab_libfunc (gt_optab
, SFmode
));
5810 add_libcall (libcall_htab
, optab_libfunc (unord_optab
, SFmode
));
5812 add_libcall (libcall_htab
, optab_libfunc (add_optab
, DFmode
));
5813 add_libcall (libcall_htab
, optab_libfunc (sdiv_optab
, DFmode
));
5814 add_libcall (libcall_htab
, optab_libfunc (smul_optab
, DFmode
));
5815 add_libcall (libcall_htab
, optab_libfunc (neg_optab
, DFmode
));
5816 add_libcall (libcall_htab
, optab_libfunc (sub_optab
, DFmode
));
5817 add_libcall (libcall_htab
, optab_libfunc (eq_optab
, DFmode
));
5818 add_libcall (libcall_htab
, optab_libfunc (lt_optab
, DFmode
));
5819 add_libcall (libcall_htab
, optab_libfunc (le_optab
, DFmode
));
5820 add_libcall (libcall_htab
, optab_libfunc (ge_optab
, DFmode
));
5821 add_libcall (libcall_htab
, optab_libfunc (gt_optab
, DFmode
));
5822 add_libcall (libcall_htab
, optab_libfunc (unord_optab
, DFmode
));
5823 add_libcall (libcall_htab
, convert_optab_libfunc (sext_optab
, DFmode
,
5825 add_libcall (libcall_htab
, convert_optab_libfunc (trunc_optab
, SFmode
,
5827 add_libcall (libcall_htab
,
5828 convert_optab_libfunc (trunc_optab
, HFmode
, DFmode
));
5831 return libcall
&& libcall_htab
->find (libcall
) != NULL
;
5835 arm_libcall_value_1 (machine_mode mode
)
5837 if (TARGET_AAPCS_BASED
)
5838 return aapcs_libcall_value (mode
);
5839 else if (TARGET_IWMMXT_ABI
5840 && arm_vector_mode_supported_p (mode
))
5841 return gen_rtx_REG (mode
, FIRST_IWMMXT_REGNUM
);
5843 return gen_rtx_REG (mode
, ARG_REGISTER (1));
5846 /* Define how to find the value returned by a library function
5847 assuming the value has mode MODE. */
5850 arm_libcall_value (machine_mode mode
, const_rtx libcall
)
5852 if (TARGET_AAPCS_BASED
&& arm_pcs_default
!= ARM_PCS_AAPCS
5853 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5855 /* The following libcalls return their result in integer registers,
5856 even though they return a floating point value. */
5857 if (arm_libcall_uses_aapcs_base (libcall
))
5858 return gen_rtx_REG (mode
, ARG_REGISTER(1));
5862 return arm_libcall_value_1 (mode
);
5865 /* Implement TARGET_FUNCTION_VALUE_REGNO_P. */
5868 arm_function_value_regno_p (const unsigned int regno
)
5870 if (regno
== ARG_REGISTER (1)
5872 && TARGET_AAPCS_BASED
5873 && TARGET_HARD_FLOAT
5874 && regno
== FIRST_VFP_REGNUM
)
5875 || (TARGET_IWMMXT_ABI
5876 && regno
== FIRST_IWMMXT_REGNUM
))
5882 /* Determine the amount of memory needed to store the possible return
5883 registers of an untyped call. */
5885 arm_apply_result_size (void)
5891 if (TARGET_HARD_FLOAT_ABI
)
5893 if (TARGET_IWMMXT_ABI
)
5900 /* Decide whether TYPE should be returned in memory (true)
5901 or in a register (false). FNTYPE is the type of the function making
5904 arm_return_in_memory (const_tree type
, const_tree fntype
)
5908 size
= int_size_in_bytes (type
); /* Negative if not fixed size. */
5910 if (TARGET_AAPCS_BASED
)
5912 /* Simple, non-aggregate types (ie not including vectors and
5913 complex) are always returned in a register (or registers).
5914 We don't care about which register here, so we can short-cut
5915 some of the detail. */
5916 if (!AGGREGATE_TYPE_P (type
)
5917 && TREE_CODE (type
) != VECTOR_TYPE
5918 && TREE_CODE (type
) != COMPLEX_TYPE
)
5921 /* Any return value that is no larger than one word can be
5923 if (((unsigned HOST_WIDE_INT
) size
) <= UNITS_PER_WORD
)
5926 /* Check any available co-processors to see if they accept the
5927 type as a register candidate (VFP, for example, can return
5928 some aggregates in consecutive registers). These aren't
5929 available if the call is variadic. */
5930 if (aapcs_select_return_coproc (type
, fntype
) >= 0)
5933 /* Vector values should be returned using ARM registers, not
5934 memory (unless they're over 16 bytes, which will break since
5935 we only have four call-clobbered registers to play with). */
5936 if (TREE_CODE (type
) == VECTOR_TYPE
)
5937 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
5939 /* The rest go in memory. */
5943 if (TREE_CODE (type
) == VECTOR_TYPE
)
5944 return (size
< 0 || size
> (4 * UNITS_PER_WORD
));
5946 if (!AGGREGATE_TYPE_P (type
) &&
5947 (TREE_CODE (type
) != VECTOR_TYPE
))
5948 /* All simple types are returned in registers. */
5951 if (arm_abi
!= ARM_ABI_APCS
)
5953 /* ATPCS and later return aggregate types in memory only if they are
5954 larger than a word (or are variable size). */
5955 return (size
< 0 || size
> UNITS_PER_WORD
);
5958 /* For the arm-wince targets we choose to be compatible with Microsoft's
5959 ARM and Thumb compilers, which always return aggregates in memory. */
5961 /* All structures/unions bigger than one word are returned in memory.
5962 Also catch the case where int_size_in_bytes returns -1. In this case
5963 the aggregate is either huge or of variable size, and in either case
5964 we will want to return it via memory and not in a register. */
5965 if (size
< 0 || size
> UNITS_PER_WORD
)
5968 if (TREE_CODE (type
) == RECORD_TYPE
)
5972 /* For a struct the APCS says that we only return in a register
5973 if the type is 'integer like' and every addressable element
5974 has an offset of zero. For practical purposes this means
5975 that the structure can have at most one non bit-field element
5976 and that this element must be the first one in the structure. */
5978 /* Find the first field, ignoring non FIELD_DECL things which will
5979 have been created by C++. */
5980 /* NOTE: This code is deprecated and has not been updated to handle
5981 DECL_FIELD_ABI_IGNORED. */
5982 for (field
= TYPE_FIELDS (type
);
5983 field
&& TREE_CODE (field
) != FIELD_DECL
;
5984 field
= DECL_CHAIN (field
))
5988 return false; /* An empty structure. Allowed by an extension to ANSI C. */
5990 /* Check that the first field is valid for returning in a register. */
5992 /* ... Floats are not allowed */
5993 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
5996 /* ... Aggregates that are not themselves valid for returning in
5997 a register are not allowed. */
5998 if (arm_return_in_memory (TREE_TYPE (field
), NULL_TREE
))
6001 /* Now check the remaining fields, if any. Only bitfields are allowed,
6002 since they are not addressable. */
6003 for (field
= DECL_CHAIN (field
);
6005 field
= DECL_CHAIN (field
))
6007 if (TREE_CODE (field
) != FIELD_DECL
)
6010 if (!DECL_BIT_FIELD_TYPE (field
))
6017 if (TREE_CODE (type
) == UNION_TYPE
)
6021 /* Unions can be returned in registers if every element is
6022 integral, or can be returned in an integer register. */
6023 for (field
= TYPE_FIELDS (type
);
6025 field
= DECL_CHAIN (field
))
6027 if (TREE_CODE (field
) != FIELD_DECL
)
6030 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
6033 if (arm_return_in_memory (TREE_TYPE (field
), NULL_TREE
))
6039 #endif /* not ARM_WINCE */
6041 /* Return all other types in memory. */
6045 const struct pcs_attribute_arg
6049 } pcs_attribute_args
[] =
6051 {"aapcs", ARM_PCS_AAPCS
},
6052 {"aapcs-vfp", ARM_PCS_AAPCS_VFP
},
6054 /* We could recognize these, but changes would be needed elsewhere
6055 * to implement them. */
6056 {"aapcs-iwmmxt", ARM_PCS_AAPCS_IWMMXT
},
6057 {"atpcs", ARM_PCS_ATPCS
},
6058 {"apcs", ARM_PCS_APCS
},
6060 {NULL
, ARM_PCS_UNKNOWN
}
6064 arm_pcs_from_attribute (tree attr
)
6066 const struct pcs_attribute_arg
*ptr
;
6069 /* Get the value of the argument. */
6070 if (TREE_VALUE (attr
) == NULL_TREE
6071 || TREE_CODE (TREE_VALUE (attr
)) != STRING_CST
)
6072 return ARM_PCS_UNKNOWN
;
6074 arg
= TREE_STRING_POINTER (TREE_VALUE (attr
));
6076 /* Check it against the list of known arguments. */
6077 for (ptr
= pcs_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
6078 if (streq (arg
, ptr
->arg
))
6081 /* An unrecognized interrupt type. */
6082 return ARM_PCS_UNKNOWN
;
6085 /* Get the PCS variant to use for this call. TYPE is the function's type
6086 specification, DECL is the specific declartion. DECL may be null if
6087 the call could be indirect or if this is a library call. */
6089 arm_get_pcs_model (const_tree type
, const_tree decl
)
6091 bool user_convention
= false;
6092 enum arm_pcs user_pcs
= arm_pcs_default
;
6097 attr
= lookup_attribute ("pcs", TYPE_ATTRIBUTES (type
));
6100 user_pcs
= arm_pcs_from_attribute (TREE_VALUE (attr
));
6101 user_convention
= true;
6104 if (TARGET_AAPCS_BASED
)
6106 /* Detect varargs functions. These always use the base rules
6107 (no argument is ever a candidate for a co-processor
6109 bool base_rules
= stdarg_p (type
);
6111 if (user_convention
)
6113 if (user_pcs
> ARM_PCS_AAPCS_LOCAL
)
6114 sorry ("non-AAPCS derived PCS variant");
6115 else if (base_rules
&& user_pcs
!= ARM_PCS_AAPCS
)
6116 error ("variadic functions must use the base AAPCS variant");
6120 return ARM_PCS_AAPCS
;
6121 else if (user_convention
)
6123 else if (decl
&& flag_unit_at_a_time
)
6125 /* Local functions never leak outside this compilation unit,
6126 so we are free to use whatever conventions are
6128 /* FIXME: remove CONST_CAST_TREE when cgraph is constified. */
6129 cgraph_node
*local_info_node
6130 = cgraph_node::local_info_node (CONST_CAST_TREE (decl
));
6131 if (local_info_node
&& local_info_node
->local
)
6132 return ARM_PCS_AAPCS_LOCAL
;
6135 else if (user_convention
&& user_pcs
!= arm_pcs_default
)
6136 sorry ("PCS variant");
6138 /* For everything else we use the target's default. */
6139 return arm_pcs_default
;
6144 aapcs_vfp_cum_init (CUMULATIVE_ARGS
*pcum ATTRIBUTE_UNUSED
,
6145 const_tree fntype ATTRIBUTE_UNUSED
,
6146 rtx libcall ATTRIBUTE_UNUSED
,
6147 const_tree fndecl ATTRIBUTE_UNUSED
)
6149 /* Record the unallocated VFP registers. */
6150 pcum
->aapcs_vfp_regs_free
= (1 << NUM_VFP_ARG_REGS
) - 1;
6151 pcum
->aapcs_vfp_reg_alloc
= 0;
6154 /* Bitmasks that indicate whether earlier versions of GCC would have
6155 taken a different path through the ABI logic. This should result in
6156 a -Wpsabi warning if the earlier path led to a different ABI decision.
6158 WARN_PSABI_EMPTY_CXX17_BASE
6159 Indicates that the type includes an artificial empty C++17 base field
6160 that, prior to GCC 10.1, would prevent the type from being treated as
6161 a HFA or HVA. See PR94711 for details.
6163 WARN_PSABI_NO_UNIQUE_ADDRESS
6164 Indicates that the type includes an empty [[no_unique_address]] field
6165 that, prior to GCC 10.1, would prevent the type from being treated as
6167 const unsigned int WARN_PSABI_EMPTY_CXX17_BASE
= 1U << 0;
6168 const unsigned int WARN_PSABI_NO_UNIQUE_ADDRESS
= 1U << 1;
6170 /* Walk down the type tree of TYPE counting consecutive base elements.
6171 If *MODEP is VOIDmode, then set it to the first valid floating point
6172 type. If a non-floating point type is found, or if a floating point
6173 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
6174 otherwise return the count in the sub-tree.
6176 The WARN_PSABI_FLAGS argument allows the caller to check whether this
6177 function has changed its behavior relative to earlier versions of GCC.
6178 Normally the argument should be nonnull and point to a zero-initialized
6179 variable. The function then records whether the ABI decision might
6180 be affected by a known fix to the ABI logic, setting the associated
6181 WARN_PSABI_* bits if so.
6183 When the argument is instead a null pointer, the function tries to
6184 simulate the behavior of GCC before all such ABI fixes were made.
6185 This is useful to check whether the function returns something
6186 different after the ABI fixes. */
6188 aapcs_vfp_sub_candidate (const_tree type
, machine_mode
*modep
,
6189 unsigned int *warn_psabi_flags
)
6194 switch (TREE_CODE (type
))
6197 mode
= TYPE_MODE (type
);
6198 if (mode
!= DFmode
&& mode
!= SFmode
&& mode
!= HFmode
&& mode
!= BFmode
)
6201 if (*modep
== VOIDmode
)
6210 mode
= TYPE_MODE (TREE_TYPE (type
));
6211 if (mode
!= DFmode
&& mode
!= SFmode
)
6214 if (*modep
== VOIDmode
)
6223 /* Use V2SImode and V4SImode as representatives of all 64-bit
6224 and 128-bit vector types, whether or not those modes are
6225 supported with the present options. */
6226 size
= int_size_in_bytes (type
);
6239 if (*modep
== VOIDmode
)
6242 /* Vector modes are considered to be opaque: two vectors are
6243 equivalent for the purposes of being homogeneous aggregates
6244 if they are the same size. */
6253 tree index
= TYPE_DOMAIN (type
);
6255 /* Can't handle incomplete types nor sizes that are not
6257 if (!COMPLETE_TYPE_P (type
)
6258 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
6261 count
= aapcs_vfp_sub_candidate (TREE_TYPE (type
), modep
,
6265 || !TYPE_MAX_VALUE (index
)
6266 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
6267 || !TYPE_MIN_VALUE (index
)
6268 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
6272 count
*= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
6273 - tree_to_uhwi (TYPE_MIN_VALUE (index
)));
6275 /* There must be no padding. */
6276 if (wi::to_wide (TYPE_SIZE (type
))
6277 != count
* GET_MODE_BITSIZE (*modep
))
6289 /* Can't handle incomplete types nor sizes that are not
6291 if (!COMPLETE_TYPE_P (type
)
6292 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
6295 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6297 if (TREE_CODE (field
) != FIELD_DECL
)
6300 if (DECL_FIELD_ABI_IGNORED (field
))
6302 /* See whether this is something that earlier versions of
6303 GCC failed to ignore. */
6305 if (lookup_attribute ("no_unique_address",
6306 DECL_ATTRIBUTES (field
)))
6307 flag
= WARN_PSABI_NO_UNIQUE_ADDRESS
;
6308 else if (cxx17_empty_base_field_p (field
))
6309 flag
= WARN_PSABI_EMPTY_CXX17_BASE
;
6311 /* No compatibility problem. */
6314 /* Simulate the old behavior when WARN_PSABI_FLAGS is null. */
6315 if (warn_psabi_flags
)
6317 *warn_psabi_flags
|= flag
;
6322 sub_count
= aapcs_vfp_sub_candidate (TREE_TYPE (field
), modep
,
6329 /* There must be no padding. */
6330 if (wi::to_wide (TYPE_SIZE (type
))
6331 != count
* GET_MODE_BITSIZE (*modep
))
6338 case QUAL_UNION_TYPE
:
6340 /* These aren't very interesting except in a degenerate case. */
6345 /* Can't handle incomplete types nor sizes that are not
6347 if (!COMPLETE_TYPE_P (type
)
6348 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
6351 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6353 if (TREE_CODE (field
) != FIELD_DECL
)
6356 sub_count
= aapcs_vfp_sub_candidate (TREE_TYPE (field
), modep
,
6360 count
= count
> sub_count
? count
: sub_count
;
6363 /* There must be no padding. */
6364 if (wi::to_wide (TYPE_SIZE (type
))
6365 != count
* GET_MODE_BITSIZE (*modep
))
6378 /* Return true if PCS_VARIANT should use VFP registers. */
6380 use_vfp_abi (enum arm_pcs pcs_variant
, bool is_double
)
6382 if (pcs_variant
== ARM_PCS_AAPCS_VFP
)
6384 static bool seen_thumb1_vfp
= false;
6386 if (TARGET_THUMB1
&& !seen_thumb1_vfp
)
6388 sorry ("Thumb-1 hard-float VFP ABI");
6389 /* sorry() is not immediately fatal, so only display this once. */
6390 seen_thumb1_vfp
= true;
6396 if (pcs_variant
!= ARM_PCS_AAPCS_LOCAL
)
6399 return (TARGET_32BIT
&& TARGET_HARD_FLOAT
&&
6400 (TARGET_VFP_DOUBLE
|| !is_double
));
6403 /* Return true if an argument whose type is TYPE, or mode is MODE, is
6404 suitable for passing or returning in VFP registers for the PCS
6405 variant selected. If it is, then *BASE_MODE is updated to contain
6406 a machine mode describing each element of the argument's type and
6407 *COUNT to hold the number of such elements. */
6409 aapcs_vfp_is_call_or_return_candidate (enum arm_pcs pcs_variant
,
6410 machine_mode mode
, const_tree type
,
6411 machine_mode
*base_mode
, int *count
)
6413 machine_mode new_mode
= VOIDmode
;
6415 /* If we have the type information, prefer that to working things
6416 out from the mode. */
6419 unsigned int warn_psabi_flags
= 0;
6420 int ag_count
= aapcs_vfp_sub_candidate (type
, &new_mode
,
6422 if (ag_count
> 0 && ag_count
<= 4)
6424 static unsigned last_reported_type_uid
;
6425 unsigned uid
= TYPE_UID (TYPE_MAIN_VARIANT (type
));
6429 && uid
!= last_reported_type_uid
6430 && ((alt
= aapcs_vfp_sub_candidate (type
, &new_mode
, NULL
))
6434 = CHANGES_ROOT_URL
"gcc-10/changes.html#empty_base";
6435 gcc_assert (alt
== -1);
6436 last_reported_type_uid
= uid
;
6437 /* Use TYPE_MAIN_VARIANT to strip any redundant const
6439 if (warn_psabi_flags
& WARN_PSABI_NO_UNIQUE_ADDRESS
)
6440 inform (input_location
, "parameter passing for argument of "
6441 "type %qT with %<[[no_unique_address]]%> members "
6442 "changed %{in GCC 10.1%}",
6443 TYPE_MAIN_VARIANT (type
), url
);
6444 else if (warn_psabi_flags
& WARN_PSABI_EMPTY_CXX17_BASE
)
6445 inform (input_location
, "parameter passing for argument of "
6446 "type %qT when C++17 is enabled changed to match "
6447 "C++14 %{in GCC 10.1%}",
6448 TYPE_MAIN_VARIANT (type
), url
);
6455 else if (GET_MODE_CLASS (mode
) == MODE_FLOAT
6456 || GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
6457 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
6462 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6465 new_mode
= (mode
== DCmode
? DFmode
: SFmode
);
6471 if (!use_vfp_abi (pcs_variant
, ARM_NUM_REGS (new_mode
) > 1))
6474 *base_mode
= new_mode
;
6476 if (TARGET_GENERAL_REGS_ONLY
)
6477 error ("argument of type %qT not permitted with -mgeneral-regs-only",
6484 aapcs_vfp_is_return_candidate (enum arm_pcs pcs_variant
,
6485 machine_mode mode
, const_tree type
)
6487 int count ATTRIBUTE_UNUSED
;
6488 machine_mode ag_mode ATTRIBUTE_UNUSED
;
6490 if (!use_vfp_abi (pcs_variant
, false))
6492 return aapcs_vfp_is_call_or_return_candidate (pcs_variant
, mode
, type
,
6497 aapcs_vfp_is_call_candidate (CUMULATIVE_ARGS
*pcum
, machine_mode mode
,
6500 if (!use_vfp_abi (pcum
->pcs_variant
, false))
6503 return aapcs_vfp_is_call_or_return_candidate (pcum
->pcs_variant
, mode
, type
,
6504 &pcum
->aapcs_vfp_rmode
,
6505 &pcum
->aapcs_vfp_rcount
);
6508 /* Implement the allocate field in aapcs_cp_arg_layout. See the comment there
6509 for the behaviour of this function. */
6512 aapcs_vfp_allocate (CUMULATIVE_ARGS
*pcum
, machine_mode mode
,
6513 const_tree type ATTRIBUTE_UNUSED
)
6516 = MAX (GET_MODE_SIZE (pcum
->aapcs_vfp_rmode
), GET_MODE_SIZE (SFmode
));
6517 int shift
= rmode_size
/ GET_MODE_SIZE (SFmode
);
6518 unsigned mask
= (1 << (shift
* pcum
->aapcs_vfp_rcount
)) - 1;
6521 for (regno
= 0; regno
< NUM_VFP_ARG_REGS
; regno
+= shift
)
6522 if (((pcum
->aapcs_vfp_regs_free
>> regno
) & mask
) == mask
)
6524 pcum
->aapcs_vfp_reg_alloc
= mask
<< regno
;
6526 || (mode
== TImode
&& ! (TARGET_NEON
|| TARGET_HAVE_MVE
))
6527 || ! arm_hard_regno_mode_ok (FIRST_VFP_REGNUM
+ regno
, mode
))
6530 int rcount
= pcum
->aapcs_vfp_rcount
;
6532 machine_mode rmode
= pcum
->aapcs_vfp_rmode
;
6534 if (!(TARGET_NEON
|| TARGET_HAVE_MVE
))
6536 /* Avoid using unsupported vector modes. */
6537 if (rmode
== V2SImode
)
6539 else if (rmode
== V4SImode
)
6546 par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (rcount
));
6547 for (i
= 0; i
< rcount
; i
++)
6549 rtx tmp
= gen_rtx_REG (rmode
,
6550 FIRST_VFP_REGNUM
+ regno
+ i
* rshift
);
6551 tmp
= gen_rtx_EXPR_LIST
6553 GEN_INT (i
* GET_MODE_SIZE (rmode
)));
6554 XVECEXP (par
, 0, i
) = tmp
;
6557 pcum
->aapcs_reg
= par
;
6560 pcum
->aapcs_reg
= gen_rtx_REG (mode
, FIRST_VFP_REGNUM
+ regno
);
6566 /* Implement the allocate_return_reg field in aapcs_cp_arg_layout. See the
6567 comment there for the behaviour of this function. */
6570 aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED
,
6572 const_tree type ATTRIBUTE_UNUSED
)
6574 if (!use_vfp_abi (pcs_variant
, false))
6578 || (GET_MODE_CLASS (mode
) == MODE_INT
6579 && GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (TImode
)
6580 && !(TARGET_NEON
|| TARGET_HAVE_MVE
)))
6583 machine_mode ag_mode
;
6588 aapcs_vfp_is_call_or_return_candidate (pcs_variant
, mode
, type
,
6591 if (!(TARGET_NEON
|| TARGET_HAVE_MVE
))
6593 if (ag_mode
== V2SImode
)
6595 else if (ag_mode
== V4SImode
)
6601 shift
= GET_MODE_SIZE(ag_mode
) / GET_MODE_SIZE(SFmode
);
6602 par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (count
));
6603 for (i
= 0; i
< count
; i
++)
6605 rtx tmp
= gen_rtx_REG (ag_mode
, FIRST_VFP_REGNUM
+ i
* shift
);
6606 tmp
= gen_rtx_EXPR_LIST (VOIDmode
, tmp
,
6607 GEN_INT (i
* GET_MODE_SIZE (ag_mode
)));
6608 XVECEXP (par
, 0, i
) = tmp
;
6614 return gen_rtx_REG (mode
, FIRST_VFP_REGNUM
);
6618 aapcs_vfp_advance (CUMULATIVE_ARGS
*pcum ATTRIBUTE_UNUSED
,
6619 machine_mode mode ATTRIBUTE_UNUSED
,
6620 const_tree type ATTRIBUTE_UNUSED
)
6622 pcum
->aapcs_vfp_regs_free
&= ~pcum
->aapcs_vfp_reg_alloc
;
6623 pcum
->aapcs_vfp_reg_alloc
= 0;
6627 #define AAPCS_CP(X) \
6629 aapcs_ ## X ## _cum_init, \
6630 aapcs_ ## X ## _is_call_candidate, \
6631 aapcs_ ## X ## _allocate, \
6632 aapcs_ ## X ## _is_return_candidate, \
6633 aapcs_ ## X ## _allocate_return_reg, \
6634 aapcs_ ## X ## _advance \
6637 /* Table of co-processors that can be used to pass arguments in
6638 registers. Idealy no arugment should be a candidate for more than
6639 one co-processor table entry, but the table is processed in order
6640 and stops after the first match. If that entry then fails to put
6641 the argument into a co-processor register, the argument will go on
6645 /* Initialize co-processor related state in CUMULATIVE_ARGS structure. */
6646 void (*cum_init
) (CUMULATIVE_ARGS
*, const_tree
, rtx
, const_tree
);
6648 /* Return true if an argument of mode MODE (or type TYPE if MODE is
6649 BLKmode) is a candidate for this co-processor's registers; this
6650 function should ignore any position-dependent state in
6651 CUMULATIVE_ARGS and only use call-type dependent information. */
6652 bool (*is_call_candidate
) (CUMULATIVE_ARGS
*, machine_mode
, const_tree
);
6654 /* Return true if the argument does get a co-processor register; it
6655 should set aapcs_reg to an RTX of the register allocated as is
6656 required for a return from FUNCTION_ARG. */
6657 bool (*allocate
) (CUMULATIVE_ARGS
*, machine_mode
, const_tree
);
6659 /* Return true if a result of mode MODE (or type TYPE if MODE is BLKmode) can
6660 be returned in this co-processor's registers. */
6661 bool (*is_return_candidate
) (enum arm_pcs
, machine_mode
, const_tree
);
6663 /* Allocate and return an RTX element to hold the return type of a call. This
6664 routine must not fail and will only be called if is_return_candidate
6665 returned true with the same parameters. */
6666 rtx (*allocate_return_reg
) (enum arm_pcs
, machine_mode
, const_tree
);
6668 /* Finish processing this argument and prepare to start processing
6670 void (*advance
) (CUMULATIVE_ARGS
*, machine_mode
, const_tree
);
6671 } aapcs_cp_arg_layout
[ARM_NUM_COPROC_SLOTS
] =
6679 aapcs_select_call_coproc (CUMULATIVE_ARGS
*pcum
, machine_mode mode
,
6684 for (i
= 0; i
< ARM_NUM_COPROC_SLOTS
; i
++)
6685 if (aapcs_cp_arg_layout
[i
].is_call_candidate (pcum
, mode
, type
))
6692 aapcs_select_return_coproc (const_tree type
, const_tree fntype
)
6694 /* We aren't passed a decl, so we can't check that a call is local.
6695 However, it isn't clear that that would be a win anyway, since it
6696 might limit some tail-calling opportunities. */
6697 enum arm_pcs pcs_variant
;
6701 const_tree fndecl
= NULL_TREE
;
6703 if (TREE_CODE (fntype
) == FUNCTION_DECL
)
6706 fntype
= TREE_TYPE (fntype
);
6709 pcs_variant
= arm_get_pcs_model (fntype
, fndecl
);
6712 pcs_variant
= arm_pcs_default
;
6714 if (pcs_variant
!= ARM_PCS_AAPCS
)
6718 for (i
= 0; i
< ARM_NUM_COPROC_SLOTS
; i
++)
6719 if (aapcs_cp_arg_layout
[i
].is_return_candidate (pcs_variant
,
6728 aapcs_allocate_return_reg (machine_mode mode
, const_tree type
,
6731 /* We aren't passed a decl, so we can't check that a call is local.
6732 However, it isn't clear that that would be a win anyway, since it
6733 might limit some tail-calling opportunities. */
6734 enum arm_pcs pcs_variant
;
6735 int unsignedp ATTRIBUTE_UNUSED
;
6739 const_tree fndecl
= NULL_TREE
;
6741 if (TREE_CODE (fntype
) == FUNCTION_DECL
)
6744 fntype
= TREE_TYPE (fntype
);
6747 pcs_variant
= arm_get_pcs_model (fntype
, fndecl
);
6750 pcs_variant
= arm_pcs_default
;
6752 /* Promote integer types. */
6753 if (type
&& INTEGRAL_TYPE_P (type
))
6754 mode
= arm_promote_function_mode (type
, mode
, &unsignedp
, fntype
, 1);
6756 if (pcs_variant
!= ARM_PCS_AAPCS
)
6760 for (i
= 0; i
< ARM_NUM_COPROC_SLOTS
; i
++)
6761 if (aapcs_cp_arg_layout
[i
].is_return_candidate (pcs_variant
, mode
,
6763 return aapcs_cp_arg_layout
[i
].allocate_return_reg (pcs_variant
,
6767 /* Promotes small structs returned in a register to full-word size
6768 for big-endian AAPCS. */
6769 if (type
&& arm_return_in_msb (type
))
6771 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6772 if (size
% UNITS_PER_WORD
!= 0)
6774 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
6775 mode
= int_mode_for_size (size
* BITS_PER_UNIT
, 0).require ();
6779 return gen_rtx_REG (mode
, R0_REGNUM
);
6783 aapcs_libcall_value (machine_mode mode
)
6785 if (BYTES_BIG_ENDIAN
&& ALL_FIXED_POINT_MODE_P (mode
)
6786 && GET_MODE_SIZE (mode
) <= 4)
6789 return aapcs_allocate_return_reg (mode
, NULL_TREE
, NULL_TREE
);
6792 /* Lay out a function argument using the AAPCS rules. The rule
6793 numbers referred to here are those in the AAPCS. */
6795 aapcs_layout_arg (CUMULATIVE_ARGS
*pcum
, machine_mode mode
,
6796 const_tree type
, bool named
)
6801 /* We only need to do this once per argument. */
6802 if (pcum
->aapcs_arg_processed
)
6805 pcum
->aapcs_arg_processed
= true;
6807 /* Special case: if named is false then we are handling an incoming
6808 anonymous argument which is on the stack. */
6812 /* Is this a potential co-processor register candidate? */
6813 if (pcum
->pcs_variant
!= ARM_PCS_AAPCS
)
6815 int slot
= aapcs_select_call_coproc (pcum
, mode
, type
);
6816 pcum
->aapcs_cprc_slot
= slot
;
6818 /* We don't have to apply any of the rules from part B of the
6819 preparation phase, these are handled elsewhere in the
6824 /* A Co-processor register candidate goes either in its own
6825 class of registers or on the stack. */
6826 if (!pcum
->aapcs_cprc_failed
[slot
])
6828 /* C1.cp - Try to allocate the argument to co-processor
6830 if (aapcs_cp_arg_layout
[slot
].allocate (pcum
, mode
, type
))
6833 /* C2.cp - Put the argument on the stack and note that we
6834 can't assign any more candidates in this slot. We also
6835 need to note that we have allocated stack space, so that
6836 we won't later try to split a non-cprc candidate between
6837 core registers and the stack. */
6838 pcum
->aapcs_cprc_failed
[slot
] = true;
6839 pcum
->can_split
= false;
6842 /* We didn't get a register, so this argument goes on the
6844 gcc_assert (pcum
->can_split
== false);
6849 /* C3 - For double-word aligned arguments, round the NCRN up to the
6850 next even number. */
6851 ncrn
= pcum
->aapcs_ncrn
;
6854 int res
= arm_needs_doubleword_align (mode
, type
);
6855 /* Only warn during RTL expansion of call stmts, otherwise we would
6856 warn e.g. during gimplification even on functions that will be
6857 always inlined, and we'd warn multiple times. Don't warn when
6858 called in expand_function_start either, as we warn instead in
6859 arm_function_arg_boundary in that case. */
6860 if (res
< 0 && warn_psabi
&& currently_expanding_gimple_stmt
)
6861 inform (input_location
, "parameter passing for argument of type "
6862 "%qT changed in GCC 7.1", type
);
6867 nregs
= ARM_NUM_REGS2(mode
, type
);
6869 /* Sigh, this test should really assert that nregs > 0, but a GCC
6870 extension allows empty structs and then gives them empty size; it
6871 then allows such a structure to be passed by value. For some of
6872 the code below we have to pretend that such an argument has
6873 non-zero size so that we 'locate' it correctly either in
6874 registers or on the stack. */
6875 gcc_assert (nregs
>= 0);
6877 nregs2
= nregs
? nregs
: 1;
6879 /* C4 - Argument fits entirely in core registers. */
6880 if (ncrn
+ nregs2
<= NUM_ARG_REGS
)
6882 pcum
->aapcs_reg
= gen_rtx_REG (mode
, ncrn
);
6883 pcum
->aapcs_next_ncrn
= ncrn
+ nregs
;
6887 /* C5 - Some core registers left and there are no arguments already
6888 on the stack: split this argument between the remaining core
6889 registers and the stack. */
6890 if (ncrn
< NUM_ARG_REGS
&& pcum
->can_split
)
6892 pcum
->aapcs_reg
= gen_rtx_REG (mode
, ncrn
);
6893 pcum
->aapcs_next_ncrn
= NUM_ARG_REGS
;
6894 pcum
->aapcs_partial
= (NUM_ARG_REGS
- ncrn
) * UNITS_PER_WORD
;
6898 /* C6 - NCRN is set to 4. */
6899 pcum
->aapcs_next_ncrn
= NUM_ARG_REGS
;
6901 /* C7,C8 - arugment goes on the stack. We have nothing to do here. */
6905 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6906 for a call to a function whose data type is FNTYPE.
6907 For a library call, FNTYPE is NULL. */
6909 arm_init_cumulative_args (CUMULATIVE_ARGS
*pcum
, tree fntype
,
6911 tree fndecl ATTRIBUTE_UNUSED
)
6913 /* Long call handling. */
6915 pcum
->pcs_variant
= arm_get_pcs_model (fntype
, fndecl
);
6917 pcum
->pcs_variant
= arm_pcs_default
;
6919 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
6921 if (arm_libcall_uses_aapcs_base (libname
))
6922 pcum
->pcs_variant
= ARM_PCS_AAPCS
;
6924 pcum
->aapcs_ncrn
= pcum
->aapcs_next_ncrn
= 0;
6925 pcum
->aapcs_reg
= NULL_RTX
;
6926 pcum
->aapcs_partial
= 0;
6927 pcum
->aapcs_arg_processed
= false;
6928 pcum
->aapcs_cprc_slot
= -1;
6929 pcum
->can_split
= true;
6931 if (pcum
->pcs_variant
!= ARM_PCS_AAPCS
)
6935 for (i
= 0; i
< ARM_NUM_COPROC_SLOTS
; i
++)
6937 pcum
->aapcs_cprc_failed
[i
] = false;
6938 aapcs_cp_arg_layout
[i
].cum_init (pcum
, fntype
, libname
, fndecl
);
6946 /* On the ARM, the offset starts at 0. */
6948 pcum
->iwmmxt_nregs
= 0;
6949 pcum
->can_split
= true;
6951 /* Varargs vectors are treated the same as long long.
6952 named_count avoids having to change the way arm handles 'named' */
6953 pcum
->named_count
= 0;
6956 if (TARGET_REALLY_IWMMXT
&& fntype
)
6960 for (fn_arg
= TYPE_ARG_TYPES (fntype
);
6962 fn_arg
= TREE_CHAIN (fn_arg
))
6963 pcum
->named_count
+= 1;
6965 if (! pcum
->named_count
)
6966 pcum
->named_count
= INT_MAX
;
6970 /* Return 2 if double word alignment is required for argument passing,
6971 but wasn't required before the fix for PR88469.
6972 Return 1 if double word alignment is required for argument passing.
6973 Return -1 if double word alignment used to be required for argument
6974 passing before PR77728 ABI fix, but is not required anymore.
6975 Return 0 if double word alignment is not required and wasn't requried
6978 arm_needs_doubleword_align (machine_mode mode
, const_tree type
)
6981 return GET_MODE_ALIGNMENT (mode
) > PARM_BOUNDARY
;
6983 /* Scalar and vector types: Use natural alignment, i.e. of base type. */
6984 if (!AGGREGATE_TYPE_P (type
))
6985 return TYPE_ALIGN (TYPE_MAIN_VARIANT (type
)) > PARM_BOUNDARY
;
6987 /* Array types: Use member alignment of element type. */
6988 if (TREE_CODE (type
) == ARRAY_TYPE
)
6989 return TYPE_ALIGN (TREE_TYPE (type
)) > PARM_BOUNDARY
;
6993 /* Record/aggregate types: Use greatest member alignment of any member.
6995 Note that we explicitly consider zero-sized fields here, even though
6996 they don't map to AAPCS machine types. For example, in:
6998 struct __attribute__((aligned(8))) empty {};
7001 [[no_unique_address]] empty e;
7005 "s" contains only one Fundamental Data Type (the int field)
7006 but gains 8-byte alignment and size thanks to "e". */
7007 for (tree field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
7008 if (DECL_ALIGN (field
) > PARM_BOUNDARY
)
7010 if (TREE_CODE (field
) == FIELD_DECL
)
7013 /* Before PR77728 fix, we were incorrectly considering also
7014 other aggregate fields, like VAR_DECLs, TYPE_DECLs etc.
7015 Make sure we can warn about that with -Wpsabi. */
7018 else if (TREE_CODE (field
) == FIELD_DECL
7019 && DECL_BIT_FIELD_TYPE (field
)
7020 && TYPE_ALIGN (DECL_BIT_FIELD_TYPE (field
)) > PARM_BOUNDARY
)
7030 /* Determine where to put an argument to a function.
7031 Value is zero to push the argument on the stack,
7032 or a hard register in which to store the argument.
7034 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7035 the preceding args and about the function being called.
7036 ARG is a description of the argument.
7038 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
7039 other arguments are passed on the stack. If (NAMED == 0) (which happens
7040 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
7041 defined), say it is passed in the stack (function_prologue will
7042 indeed make it pass in the stack if necessary). */
7045 arm_function_arg (cumulative_args_t pcum_v
, const function_arg_info
&arg
)
7047 CUMULATIVE_ARGS
*pcum
= get_cumulative_args (pcum_v
);
7050 /* Handle the special case quickly. Pick an arbitrary value for op2 of
7051 a call insn (op3 of a call_value insn). */
7052 if (arg
.end_marker_p ())
7055 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
7057 aapcs_layout_arg (pcum
, arg
.mode
, arg
.type
, arg
.named
);
7058 return pcum
->aapcs_reg
;
7061 /* Varargs vectors are treated the same as long long.
7062 named_count avoids having to change the way arm handles 'named' */
7063 if (TARGET_IWMMXT_ABI
7064 && arm_vector_mode_supported_p (arg
.mode
)
7065 && pcum
->named_count
> pcum
->nargs
+ 1)
7067 if (pcum
->iwmmxt_nregs
<= 9)
7068 return gen_rtx_REG (arg
.mode
,
7069 pcum
->iwmmxt_nregs
+ FIRST_IWMMXT_REGNUM
);
7072 pcum
->can_split
= false;
7077 /* Put doubleword aligned quantities in even register pairs. */
7078 if ((pcum
->nregs
& 1) && ARM_DOUBLEWORD_ALIGN
)
7080 int res
= arm_needs_doubleword_align (arg
.mode
, arg
.type
);
7081 if (res
< 0 && warn_psabi
)
7082 inform (input_location
, "parameter passing for argument of type "
7083 "%qT changed in GCC 7.1", arg
.type
);
7087 if (res
> 1 && warn_psabi
)
7088 inform (input_location
, "parameter passing for argument of type "
7089 "%qT changed in GCC 9.1", arg
.type
);
7093 /* Only allow splitting an arg between regs and memory if all preceding
7094 args were allocated to regs. For args passed by reference we only count
7095 the reference pointer. */
7096 if (pcum
->can_split
)
7099 nregs
= ARM_NUM_REGS2 (arg
.mode
, arg
.type
);
7101 if (!arg
.named
|| pcum
->nregs
+ nregs
> NUM_ARG_REGS
)
7104 return gen_rtx_REG (arg
.mode
, pcum
->nregs
);
7108 arm_function_arg_boundary (machine_mode mode
, const_tree type
)
7110 if (!ARM_DOUBLEWORD_ALIGN
)
7111 return PARM_BOUNDARY
;
7113 int res
= arm_needs_doubleword_align (mode
, type
);
7114 if (res
< 0 && warn_psabi
)
7115 inform (input_location
, "parameter passing for argument of type %qT "
7116 "changed in GCC 7.1", type
);
7117 if (res
> 1 && warn_psabi
)
7118 inform (input_location
, "parameter passing for argument of type "
7119 "%qT changed in GCC 9.1", type
);
7121 return res
> 0 ? DOUBLEWORD_ALIGNMENT
: PARM_BOUNDARY
;
7125 arm_arg_partial_bytes (cumulative_args_t pcum_v
, const function_arg_info
&arg
)
7127 CUMULATIVE_ARGS
*pcum
= get_cumulative_args (pcum_v
);
7128 int nregs
= pcum
->nregs
;
7130 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
7132 aapcs_layout_arg (pcum
, arg
.mode
, arg
.type
, arg
.named
);
7133 return pcum
->aapcs_partial
;
7136 if (TARGET_IWMMXT_ABI
&& arm_vector_mode_supported_p (arg
.mode
))
7139 if (NUM_ARG_REGS
> nregs
7140 && (NUM_ARG_REGS
< nregs
+ ARM_NUM_REGS2 (arg
.mode
, arg
.type
))
7142 return (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
7147 /* Update the data in PCUM to advance over argument ARG. */
7150 arm_function_arg_advance (cumulative_args_t pcum_v
,
7151 const function_arg_info
&arg
)
7153 CUMULATIVE_ARGS
*pcum
= get_cumulative_args (pcum_v
);
7155 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
7157 aapcs_layout_arg (pcum
, arg
.mode
, arg
.type
, arg
.named
);
7159 if (pcum
->aapcs_cprc_slot
>= 0)
7161 aapcs_cp_arg_layout
[pcum
->aapcs_cprc_slot
].advance (pcum
, arg
.mode
,
7163 pcum
->aapcs_cprc_slot
= -1;
7166 /* Generic stuff. */
7167 pcum
->aapcs_arg_processed
= false;
7168 pcum
->aapcs_ncrn
= pcum
->aapcs_next_ncrn
;
7169 pcum
->aapcs_reg
= NULL_RTX
;
7170 pcum
->aapcs_partial
= 0;
7175 if (arm_vector_mode_supported_p (arg
.mode
)
7176 && pcum
->named_count
> pcum
->nargs
7177 && TARGET_IWMMXT_ABI
)
7178 pcum
->iwmmxt_nregs
+= 1;
7180 pcum
->nregs
+= ARM_NUM_REGS2 (arg
.mode
, arg
.type
);
7184 /* Variable sized types are passed by reference. This is a GCC
7185 extension to the ARM ABI. */
7188 arm_pass_by_reference (cumulative_args_t
, const function_arg_info
&arg
)
7190 return arg
.type
&& TREE_CODE (TYPE_SIZE (arg
.type
)) != INTEGER_CST
;
7193 /* Encode the current state of the #pragma [no_]long_calls. */
7196 OFF
, /* No #pragma [no_]long_calls is in effect. */
7197 LONG
, /* #pragma long_calls is in effect. */
7198 SHORT
/* #pragma no_long_calls is in effect. */
7201 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
7204 arm_pr_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
7206 arm_pragma_long_calls
= LONG
;
7210 arm_pr_no_long_calls (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
7212 arm_pragma_long_calls
= SHORT
;
7216 arm_pr_long_calls_off (struct cpp_reader
* pfile ATTRIBUTE_UNUSED
)
7218 arm_pragma_long_calls
= OFF
;
7221 /* Handle an attribute requiring a FUNCTION_DECL;
7222 arguments as in struct attribute_spec.handler. */
7224 arm_handle_fndecl_attribute (tree
*node
, tree name
, tree args ATTRIBUTE_UNUSED
,
7225 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
7227 if (TREE_CODE (*node
) != FUNCTION_DECL
)
7229 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
7231 *no_add_attrs
= true;
7237 /* Handle an "interrupt" or "isr" attribute;
7238 arguments as in struct attribute_spec.handler. */
7240 arm_handle_isr_attribute (tree
*node
, tree name
, tree args
, int flags
,
7245 if (TREE_CODE (*node
) != FUNCTION_DECL
)
7247 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
7249 *no_add_attrs
= true;
7251 else if (TARGET_VFP_BASE
)
7253 warning (OPT_Wattributes
, "FP registers might be clobbered despite %qE attribute: compile with %<-mgeneral-regs-only%>",
7256 /* FIXME: the argument if any is checked for type attributes;
7257 should it be checked for decl ones? */
7261 if (TREE_CODE (*node
) == FUNCTION_TYPE
7262 || TREE_CODE (*node
) == METHOD_TYPE
)
7264 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
7266 warning (OPT_Wattributes
, "%qE attribute ignored",
7268 *no_add_attrs
= true;
7271 else if (TREE_CODE (*node
) == POINTER_TYPE
7272 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
7273 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
7274 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
7276 *node
= build_variant_type_copy (*node
);
7277 TREE_TYPE (*node
) = build_type_attribute_variant
7279 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
7280 *no_add_attrs
= true;
7284 /* Possibly pass this attribute on from the type to a decl. */
7285 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
7286 | (int) ATTR_FLAG_FUNCTION_NEXT
7287 | (int) ATTR_FLAG_ARRAY_NEXT
))
7289 *no_add_attrs
= true;
7290 return tree_cons (name
, args
, NULL_TREE
);
7294 warning (OPT_Wattributes
, "%qE attribute ignored",
7303 /* Handle a "pcs" attribute; arguments as in struct
7304 attribute_spec.handler. */
7306 arm_handle_pcs_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
, tree args
,
7307 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
7309 if (arm_pcs_from_attribute (args
) == ARM_PCS_UNKNOWN
)
7311 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
7312 *no_add_attrs
= true;
7317 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
7318 /* Handle the "notshared" attribute. This attribute is another way of
7319 requesting hidden visibility. ARM's compiler supports
7320 "__declspec(notshared)"; we support the same thing via an
7324 arm_handle_notshared_attribute (tree
*node
,
7325 tree name ATTRIBUTE_UNUSED
,
7326 tree args ATTRIBUTE_UNUSED
,
7327 int flags ATTRIBUTE_UNUSED
,
7330 tree decl
= TYPE_NAME (*node
);
7334 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
7335 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
7336 *no_add_attrs
= false;
7342 /* This function returns true if a function with declaration FNDECL and type
7343 FNTYPE uses the stack to pass arguments or return variables and false
7344 otherwise. This is used for functions with the attributes
7345 'cmse_nonsecure_call' or 'cmse_nonsecure_entry' and this function will issue
7346 diagnostic messages if the stack is used. NAME is the name of the attribute
7350 cmse_func_args_or_return_in_stack (tree fndecl
, tree name
, tree fntype
)
7352 function_args_iterator args_iter
;
7353 CUMULATIVE_ARGS args_so_far_v
;
7354 cumulative_args_t args_so_far
;
7355 bool first_param
= true;
7356 tree arg_type
, prev_arg_type
= NULL_TREE
, ret_type
;
7358 /* Error out if any argument is passed on the stack. */
7359 arm_init_cumulative_args (&args_so_far_v
, fntype
, NULL_RTX
, fndecl
);
7360 args_so_far
= pack_cumulative_args (&args_so_far_v
);
7361 FOREACH_FUNCTION_ARGS (fntype
, arg_type
, args_iter
)
7365 prev_arg_type
= arg_type
;
7366 if (VOID_TYPE_P (arg_type
))
7369 function_arg_info
arg (arg_type
, /*named=*/true);
7371 /* ??? We should advance after processing the argument and pass
7372 the argument we're advancing past. */
7373 arm_function_arg_advance (args_so_far
, arg
);
7374 arg_rtx
= arm_function_arg (args_so_far
, arg
);
7375 if (!arg_rtx
|| arm_arg_partial_bytes (args_so_far
, arg
))
7377 error ("%qE attribute not available to functions with arguments "
7378 "passed on the stack", name
);
7381 first_param
= false;
7384 /* Error out for variadic functions since we cannot control how many
7385 arguments will be passed and thus stack could be used. stdarg_p () is not
7386 used for the checking to avoid browsing arguments twice. */
7387 if (prev_arg_type
!= NULL_TREE
&& !VOID_TYPE_P (prev_arg_type
))
7389 error ("%qE attribute not available to functions with variable number "
7390 "of arguments", name
);
7394 /* Error out if return value is passed on the stack. */
7395 ret_type
= TREE_TYPE (fntype
);
7396 if (arm_return_in_memory (ret_type
, fntype
))
7398 error ("%qE attribute not available to functions that return value on "
7405 /* Called upon detection of the use of the cmse_nonsecure_entry attribute, this
7406 function will check whether the attribute is allowed here and will add the
7407 attribute to the function declaration tree or otherwise issue a warning. */
7410 arm_handle_cmse_nonsecure_entry (tree
*node
, tree name
,
7419 *no_add_attrs
= true;
7420 warning (OPT_Wattributes
, "%qE attribute ignored without %<-mcmse%> "
7425 /* Ignore attribute for function types. */
7426 if (TREE_CODE (*node
) != FUNCTION_DECL
)
7428 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
7430 *no_add_attrs
= true;
7436 /* Warn for static linkage functions. */
7437 if (!TREE_PUBLIC (fndecl
))
7439 warning (OPT_Wattributes
, "%qE attribute has no effect on functions "
7440 "with static linkage", name
);
7441 *no_add_attrs
= true;
7445 *no_add_attrs
|= cmse_func_args_or_return_in_stack (fndecl
, name
,
7446 TREE_TYPE (fndecl
));
7451 /* Called upon detection of the use of the cmse_nonsecure_call attribute, this
7452 function will check whether the attribute is allowed here and will add the
7453 attribute to the function type tree or otherwise issue a diagnostic. The
7454 reason we check this at declaration time is to only allow the use of the
7455 attribute with declarations of function pointers and not function
7456 declarations. This function checks NODE is of the expected type and issues
7457 diagnostics otherwise using NAME. If it is not of the expected type
7458 *NO_ADD_ATTRS will be set to true. */
7461 arm_handle_cmse_nonsecure_call (tree
*node
, tree name
,
7466 tree decl
= NULL_TREE
, fntype
= NULL_TREE
;
7471 *no_add_attrs
= true;
7472 warning (OPT_Wattributes
, "%qE attribute ignored without %<-mcmse%> "
7477 if (TREE_CODE (*node
) == VAR_DECL
|| TREE_CODE (*node
) == TYPE_DECL
)
7480 fntype
= TREE_TYPE (decl
);
7483 while (fntype
!= NULL_TREE
&& TREE_CODE (fntype
) == POINTER_TYPE
)
7484 fntype
= TREE_TYPE (fntype
);
7486 if (!decl
|| TREE_CODE (fntype
) != FUNCTION_TYPE
)
7488 warning (OPT_Wattributes
, "%qE attribute only applies to base type of a "
7489 "function pointer", name
);
7490 *no_add_attrs
= true;
7494 *no_add_attrs
|= cmse_func_args_or_return_in_stack (NULL
, name
, fntype
);
7499 /* Prevent trees being shared among function types with and without
7500 cmse_nonsecure_call attribute. */
7501 type
= TREE_TYPE (decl
);
7503 type
= build_distinct_type_copy (type
);
7504 TREE_TYPE (decl
) = type
;
7507 while (TREE_CODE (fntype
) != FUNCTION_TYPE
)
7510 fntype
= TREE_TYPE (fntype
);
7511 fntype
= build_distinct_type_copy (fntype
);
7512 TREE_TYPE (type
) = fntype
;
7515 /* Construct a type attribute and add it to the function type. */
7516 tree attrs
= tree_cons (get_identifier ("cmse_nonsecure_call"), NULL_TREE
,
7517 TYPE_ATTRIBUTES (fntype
));
7518 TYPE_ATTRIBUTES (fntype
) = attrs
;
7522 /* Return 0 if the attributes for two types are incompatible, 1 if they
7523 are compatible, and 2 if they are nearly compatible (which causes a
7524 warning to be generated). */
7526 arm_comp_type_attributes (const_tree type1
, const_tree type2
)
7530 tree attrs1
= lookup_attribute ("Advanced SIMD type",
7531 TYPE_ATTRIBUTES (type1
));
7532 tree attrs2
= lookup_attribute ("Advanced SIMD type",
7533 TYPE_ATTRIBUTES (type2
));
7534 if (bool (attrs1
) != bool (attrs2
))
7536 if (attrs1
&& !attribute_value_equal (attrs1
, attrs2
))
7539 /* Check for mismatch of non-default calling convention. */
7540 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
7543 /* Check for mismatched call attributes. */
7544 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
7545 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
7546 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
7547 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
7549 /* Only bother to check if an attribute is defined. */
7550 if (l1
| l2
| s1
| s2
)
7552 /* If one type has an attribute, the other must have the same attribute. */
7553 if ((l1
!= l2
) || (s1
!= s2
))
7556 /* Disallow mixed attributes. */
7557 if ((l1
& s2
) || (l2
& s1
))
7561 /* Check for mismatched ISR attribute. */
7562 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
7564 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
7565 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
7567 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
7571 l1
= lookup_attribute ("cmse_nonsecure_call",
7572 TYPE_ATTRIBUTES (type1
)) != NULL
;
7573 l2
= lookup_attribute ("cmse_nonsecure_call",
7574 TYPE_ATTRIBUTES (type2
)) != NULL
;
7582 /* Assigns default attributes to newly defined type. This is used to
7583 set short_call/long_call attributes for function types of
7584 functions defined inside corresponding #pragma scopes. */
7586 arm_set_default_type_attributes (tree type
)
7588 /* Add __attribute__ ((long_call)) to all functions, when
7589 inside #pragma long_calls or __attribute__ ((short_call)),
7590 when inside #pragma no_long_calls. */
7591 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
7593 tree type_attr_list
, attr_name
;
7594 type_attr_list
= TYPE_ATTRIBUTES (type
);
7596 if (arm_pragma_long_calls
== LONG
)
7597 attr_name
= get_identifier ("long_call");
7598 else if (arm_pragma_long_calls
== SHORT
)
7599 attr_name
= get_identifier ("short_call");
7603 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
7604 TYPE_ATTRIBUTES (type
) = type_attr_list
;
7608 /* Return true if DECL is known to be linked into section SECTION. */
7611 arm_function_in_section_p (tree decl
, section
*section
)
7613 /* We can only be certain about the prevailing symbol definition. */
7614 if (!decl_binds_to_current_def_p (decl
))
7617 /* If DECL_SECTION_NAME is set, assume it is trustworthy. */
7618 if (!DECL_SECTION_NAME (decl
))
7620 /* Make sure that we will not create a unique section for DECL. */
7621 if (flag_function_sections
|| DECL_COMDAT_GROUP (decl
))
7625 return function_section (decl
) == section
;
7628 /* Return nonzero if a 32-bit "long_call" should be generated for
7629 a call from the current function to DECL. We generate a long_call
7632 a. has an __attribute__((long call))
7633 or b. is within the scope of a #pragma long_calls
7634 or c. the -mlong-calls command line switch has been specified
7636 However we do not generate a long call if the function:
7638 d. has an __attribute__ ((short_call))
7639 or e. is inside the scope of a #pragma no_long_calls
7640 or f. is defined in the same section as the current function. */
7643 arm_is_long_call_p (tree decl
)
7648 return TARGET_LONG_CALLS
;
7650 attrs
= TYPE_ATTRIBUTES (TREE_TYPE (decl
));
7651 if (lookup_attribute ("short_call", attrs
))
7654 /* For "f", be conservative, and only cater for cases in which the
7655 whole of the current function is placed in the same section. */
7656 if (!flag_reorder_blocks_and_partition
7657 && TREE_CODE (decl
) == FUNCTION_DECL
7658 && arm_function_in_section_p (decl
, current_function_section ()))
7661 if (lookup_attribute ("long_call", attrs
))
7664 return TARGET_LONG_CALLS
;
7667 /* Return nonzero if it is ok to make a tail-call to DECL. */
7669 arm_function_ok_for_sibcall (tree decl
, tree exp
)
7671 unsigned long func_type
;
7673 if (cfun
->machine
->sibcall_blocked
)
7678 /* In FDPIC, never tailcall something for which we have no decl:
7679 the target function could be in a different module, requiring
7680 a different FDPIC register value. */
7685 /* Never tailcall something if we are generating code for Thumb-1. */
7689 /* The PIC register is live on entry to VxWorks PLT entries, so we
7690 must make the call before restoring the PIC register. */
7691 if (TARGET_VXWORKS_RTP
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
7694 /* ??? Cannot tail-call to long calls with APCS frame and VFP, because IP
7695 may be used both as target of the call and base register for restoring
7696 the VFP registers */
7697 if (TARGET_APCS_FRAME
&& TARGET_ARM
7698 && TARGET_HARD_FLOAT
7699 && decl
&& arm_is_long_call_p (decl
))
7702 /* If we are interworking and the function is not declared static
7703 then we can't tail-call it unless we know that it exists in this
7704 compilation unit (since it might be a Thumb routine). */
7705 if (TARGET_INTERWORK
&& decl
&& TREE_PUBLIC (decl
)
7706 && !TREE_ASM_WRITTEN (decl
))
7709 func_type
= arm_current_func_type ();
7710 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
7711 if (IS_INTERRUPT (func_type
))
7714 /* ARMv8-M non-secure entry functions need to return with bxns which is only
7715 generated for entry functions themselves. */
7716 if (IS_CMSE_ENTRY (arm_current_func_type ()))
7719 /* We do not allow ARMv8-M non-secure calls to be turned into sibling calls,
7720 this would complicate matters for later code generation. */
7721 if (TREE_CODE (exp
) == CALL_EXPR
)
7723 tree fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
7724 if (lookup_attribute ("cmse_nonsecure_call", TYPE_ATTRIBUTES (fntype
)))
7728 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
7730 /* Check that the return value locations are the same. For
7731 example that we aren't returning a value from the sibling in
7732 a VFP register but then need to transfer it to a core
7735 tree decl_or_type
= decl
;
7737 /* If it is an indirect function pointer, get the function type. */
7739 decl_or_type
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
7741 a
= arm_function_value (TREE_TYPE (exp
), decl_or_type
, false);
7742 b
= arm_function_value (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
7744 if (!rtx_equal_p (a
, b
))
7748 /* Never tailcall if function may be called with a misaligned SP. */
7749 if (IS_STACKALIGN (func_type
))
7752 /* The AAPCS says that, on bare-metal, calls to unresolved weak
7753 references should become a NOP. Don't convert such calls into
7755 if (TARGET_AAPCS_BASED
7756 && arm_abi
== ARM_ABI_AAPCS
7758 && DECL_WEAK (decl
))
7761 /* We cannot do a tailcall for an indirect call by descriptor if all the
7762 argument registers are used because the only register left to load the
7763 address is IP and it will already contain the static chain. */
7764 if (!decl
&& CALL_EXPR_BY_DESCRIPTOR (exp
) && !flag_trampolines
)
7766 tree fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
7767 CUMULATIVE_ARGS cum
;
7768 cumulative_args_t cum_v
;
7770 arm_init_cumulative_args (&cum
, fntype
, NULL_RTX
, NULL_TREE
);
7771 cum_v
= pack_cumulative_args (&cum
);
7773 for (tree t
= TYPE_ARG_TYPES (fntype
); t
; t
= TREE_CHAIN (t
))
7775 tree type
= TREE_VALUE (t
);
7776 if (!VOID_TYPE_P (type
))
7778 function_arg_info
arg (type
, /*named=*/true);
7779 arm_function_arg_advance (cum_v
, arg
);
7783 function_arg_info
arg (integer_type_node
, /*named=*/true);
7784 if (!arm_function_arg (cum_v
, arg
))
7788 /* Everything else is ok. */
7793 /* Addressing mode support functions. */
7795 /* Return nonzero if X is a legitimate immediate operand when compiling
7796 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
7798 legitimate_pic_operand_p (rtx x
)
7800 if (SYMBOL_REF_P (x
)
7801 || (GET_CODE (x
) == CONST
7802 && GET_CODE (XEXP (x
, 0)) == PLUS
7803 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
))
7809 /* Record that the current function needs a PIC register. If PIC_REG is null,
7810 a new pseudo is allocated as PIC register, otherwise PIC_REG is used. In
7811 both case cfun->machine->pic_reg is initialized if we have not already done
7812 so. COMPUTE_NOW decide whether and where to set the PIC register. If true,
7813 PIC register is reloaded in the current position of the instruction stream
7814 irregardless of whether it was loaded before. Otherwise, it is only loaded
7815 if not already done so (crtl->uses_pic_offset_table is null). Note that
7816 nonnull PIC_REG is only supported iff COMPUTE_NOW is true and null PIC_REG
7817 is only supported iff COMPUTE_NOW is false. */
7820 require_pic_register (rtx pic_reg
, bool compute_now
)
7822 gcc_assert (compute_now
== (pic_reg
!= NULL_RTX
));
7824 /* A lot of the logic here is made obscure by the fact that this
7825 routine gets called as part of the rtx cost estimation process.
7826 We don't want those calls to affect any assumptions about the real
7827 function; and further, we can't call entry_of_function() until we
7828 start the real expansion process. */
7829 if (!crtl
->uses_pic_offset_table
|| compute_now
)
7831 gcc_assert (can_create_pseudo_p ()
7832 || (pic_reg
!= NULL_RTX
7834 && GET_MODE (pic_reg
) == Pmode
));
7835 if (arm_pic_register
!= INVALID_REGNUM
7837 && !(TARGET_THUMB1
&& arm_pic_register
> LAST_LO_REGNUM
))
7839 if (!cfun
->machine
->pic_reg
)
7840 cfun
->machine
->pic_reg
= gen_rtx_REG (Pmode
, arm_pic_register
);
7842 /* Play games to avoid marking the function as needing pic
7843 if we are being called as part of the cost-estimation
7845 if (current_ir_type () != IR_GIMPLE
|| currently_expanding_to_rtl
)
7846 crtl
->uses_pic_offset_table
= 1;
7850 rtx_insn
*seq
, *insn
;
7852 if (pic_reg
== NULL_RTX
)
7853 pic_reg
= gen_reg_rtx (Pmode
);
7854 if (!cfun
->machine
->pic_reg
)
7855 cfun
->machine
->pic_reg
= pic_reg
;
7857 /* Play games to avoid marking the function as needing pic
7858 if we are being called as part of the cost-estimation
7860 if (current_ir_type () != IR_GIMPLE
|| currently_expanding_to_rtl
)
7862 crtl
->uses_pic_offset_table
= 1;
7865 if (TARGET_THUMB1
&& arm_pic_register
!= INVALID_REGNUM
7866 && arm_pic_register
> LAST_LO_REGNUM
7868 emit_move_insn (cfun
->machine
->pic_reg
,
7869 gen_rtx_REG (Pmode
, arm_pic_register
));
7871 arm_load_pic_register (0UL, pic_reg
);
7876 for (insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
7878 INSN_LOCATION (insn
) = prologue_location
;
7880 /* We can be called during expansion of PHI nodes, where
7881 we can't yet emit instructions directly in the final
7882 insn stream. Queue the insns on the entry edge, they will
7883 be committed after everything else is expanded. */
7884 if (currently_expanding_to_rtl
)
7885 insert_insn_on_edge (seq
,
7887 (ENTRY_BLOCK_PTR_FOR_FN (cfun
)));
7895 /* Generate insns to calculate the address of ORIG in pic mode. */
7897 calculate_pic_address_constant (rtx reg
, rtx pic_reg
, rtx orig
)
7902 pat
= gen_calculate_pic_address (reg
, pic_reg
, orig
);
7904 /* Make the MEM as close to a constant as possible. */
7905 mem
= SET_SRC (pat
);
7906 gcc_assert (MEM_P (mem
) && !MEM_VOLATILE_P (mem
));
7907 MEM_READONLY_P (mem
) = 1;
7908 MEM_NOTRAP_P (mem
) = 1;
7910 return emit_insn (pat
);
7913 /* Legitimize PIC load to ORIG into REG. If REG is NULL, a new pseudo is
7914 created to hold the result of the load. If not NULL, PIC_REG indicates
7915 which register to use as PIC register, otherwise it is decided by register
7916 allocator. COMPUTE_NOW forces the PIC register to be loaded at the current
7917 location in the instruction stream, irregardless of whether it was loaded
7918 previously. Note that nonnull PIC_REG is only supported iff COMPUTE_NOW is
7919 true and null PIC_REG is only supported iff COMPUTE_NOW is false.
7921 Returns the register REG into which the PIC load is performed. */
7924 legitimize_pic_address (rtx orig
, machine_mode mode
, rtx reg
, rtx pic_reg
,
7927 gcc_assert (compute_now
== (pic_reg
!= NULL_RTX
));
7929 if (SYMBOL_REF_P (orig
)
7930 || LABEL_REF_P (orig
))
7934 gcc_assert (can_create_pseudo_p ());
7935 reg
= gen_reg_rtx (Pmode
);
7938 /* VxWorks does not impose a fixed gap between segments; the run-time
7939 gap can be different from the object-file gap. We therefore can't
7940 use GOTOFF unless we are absolutely sure that the symbol is in the
7941 same segment as the GOT. Unfortunately, the flexibility of linker
7942 scripts means that we can't be sure of that in general, so assume
7943 that GOTOFF is never valid on VxWorks. */
7944 /* References to weak symbols cannot be resolved locally: they
7945 may be overridden by a non-weak definition at link time. */
7947 if ((LABEL_REF_P (orig
)
7948 || (SYMBOL_REF_P (orig
)
7949 && SYMBOL_REF_LOCAL_P (orig
)
7950 && (SYMBOL_REF_DECL (orig
)
7951 ? !DECL_WEAK (SYMBOL_REF_DECL (orig
)) : 1)
7952 && (!SYMBOL_REF_FUNCTION_P (orig
)
7953 || arm_fdpic_local_funcdesc_p (orig
))))
7955 && arm_pic_data_is_text_relative
)
7956 insn
= arm_pic_static_addr (orig
, reg
);
7959 /* If this function doesn't have a pic register, create one now. */
7960 require_pic_register (pic_reg
, compute_now
);
7962 if (pic_reg
== NULL_RTX
)
7963 pic_reg
= cfun
->machine
->pic_reg
;
7965 insn
= calculate_pic_address_constant (reg
, pic_reg
, orig
);
7968 /* Put a REG_EQUAL note on this insn, so that it can be optimized
7970 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
7974 else if (GET_CODE (orig
) == CONST
)
7978 if (GET_CODE (XEXP (orig
, 0)) == PLUS
7979 && XEXP (XEXP (orig
, 0), 0) == cfun
->machine
->pic_reg
)
7982 /* Handle the case where we have: const (UNSPEC_TLS). */
7983 if (GET_CODE (XEXP (orig
, 0)) == UNSPEC
7984 && XINT (XEXP (orig
, 0), 1) == UNSPEC_TLS
)
7987 /* Handle the case where we have:
7988 const (plus (UNSPEC_TLS) (ADDEND)). The ADDEND must be a
7990 if (GET_CODE (XEXP (orig
, 0)) == PLUS
7991 && GET_CODE (XEXP (XEXP (orig
, 0), 0)) == UNSPEC
7992 && XINT (XEXP (XEXP (orig
, 0), 0), 1) == UNSPEC_TLS
)
7994 gcc_assert (CONST_INT_P (XEXP (XEXP (orig
, 0), 1)));
8000 gcc_assert (can_create_pseudo_p ());
8001 reg
= gen_reg_rtx (Pmode
);
8004 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
8006 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
,
8007 pic_reg
, compute_now
);
8008 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
8009 base
== reg
? 0 : reg
, pic_reg
,
8012 if (CONST_INT_P (offset
))
8014 /* The base register doesn't really matter, we only want to
8015 test the index for the appropriate mode. */
8016 if (!arm_legitimate_index_p (mode
, offset
, SET
, 0))
8018 gcc_assert (can_create_pseudo_p ());
8019 offset
= force_reg (Pmode
, offset
);
8022 if (CONST_INT_P (offset
))
8023 return plus_constant (Pmode
, base
, INTVAL (offset
));
8026 if (GET_MODE_SIZE (mode
) > 4
8027 && (GET_MODE_CLASS (mode
) == MODE_INT
8028 || TARGET_SOFT_FLOAT
))
8030 emit_insn (gen_addsi3 (reg
, base
, offset
));
8034 return gen_rtx_PLUS (Pmode
, base
, offset
);
8041 /* Whether a register is callee saved or not. This is necessary because high
8042 registers are marked as caller saved when optimizing for size on Thumb-1
8043 targets despite being callee saved in order to avoid using them. */
8044 #define callee_saved_reg_p(reg) \
8045 (!call_used_or_fixed_reg_p (reg) \
8046 || (TARGET_THUMB1 && optimize_size \
8047 && reg >= FIRST_HI_REGNUM && reg <= LAST_HI_REGNUM))
8049 /* Return a mask for the call-clobbered low registers that are unused
8050 at the end of the prologue. */
8051 static unsigned long
8052 thumb1_prologue_unused_call_clobbered_lo_regs (void)
8054 unsigned long mask
= 0;
8055 bitmap prologue_live_out
= df_get_live_out (ENTRY_BLOCK_PTR_FOR_FN (cfun
));
8057 for (int reg
= FIRST_LO_REGNUM
; reg
<= LAST_LO_REGNUM
; reg
++)
8058 if (!callee_saved_reg_p (reg
) && !REGNO_REG_SET_P (prologue_live_out
, reg
))
8059 mask
|= 1 << (reg
- FIRST_LO_REGNUM
);
8063 /* Similarly for the start of the epilogue. */
8064 static unsigned long
8065 thumb1_epilogue_unused_call_clobbered_lo_regs (void)
8067 unsigned long mask
= 0;
8068 bitmap epilogue_live_in
= df_get_live_in (EXIT_BLOCK_PTR_FOR_FN (cfun
));
8070 for (int reg
= FIRST_LO_REGNUM
; reg
<= LAST_LO_REGNUM
; reg
++)
8071 if (!callee_saved_reg_p (reg
) && !REGNO_REG_SET_P (epilogue_live_in
, reg
))
8072 mask
|= 1 << (reg
- FIRST_LO_REGNUM
);
8076 /* Find a spare register to use during the prolog of a function. */
8079 thumb_find_work_register (unsigned long pushed_regs_mask
)
8083 unsigned long unused_regs
8084 = thumb1_prologue_unused_call_clobbered_lo_regs ();
8086 /* Check the argument registers first as these are call-used. The
8087 register allocation order means that sometimes r3 might be used
8088 but earlier argument registers might not, so check them all. */
8089 for (reg
= LAST_LO_REGNUM
; reg
>= FIRST_LO_REGNUM
; reg
--)
8090 if (unused_regs
& (1 << (reg
- FIRST_LO_REGNUM
)))
8093 /* Otherwise look for a call-saved register that is going to be pushed. */
8094 for (reg
= LAST_LO_REGNUM
; reg
> LAST_ARG_REGNUM
; reg
--)
8095 if (pushed_regs_mask
& (1 << reg
))
8100 /* Thumb-2 can use high regs. */
8101 for (reg
= FIRST_HI_REGNUM
; reg
< 15; reg
++)
8102 if (pushed_regs_mask
& (1 << reg
))
8105 /* Something went wrong - thumb_compute_save_reg_mask()
8106 should have arranged for a suitable register to be pushed. */
8110 static GTY(()) int pic_labelno
;
8112 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
8116 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED
, rtx pic_reg
)
8118 rtx l1
, labelno
, pic_tmp
, pic_rtx
;
8120 if (crtl
->uses_pic_offset_table
== 0
8121 || TARGET_SINGLE_PIC_BASE
8125 gcc_assert (flag_pic
);
8127 if (pic_reg
== NULL_RTX
)
8128 pic_reg
= cfun
->machine
->pic_reg
;
8129 if (TARGET_VXWORKS_RTP
)
8131 pic_rtx
= gen_rtx_SYMBOL_REF (Pmode
, VXWORKS_GOTT_BASE
);
8132 pic_rtx
= gen_rtx_CONST (Pmode
, pic_rtx
);
8133 emit_insn (gen_pic_load_addr_32bit (pic_reg
, pic_rtx
));
8135 emit_insn (gen_rtx_SET (pic_reg
, gen_rtx_MEM (Pmode
, pic_reg
)));
8137 pic_tmp
= gen_rtx_SYMBOL_REF (Pmode
, VXWORKS_GOTT_INDEX
);
8138 emit_insn (gen_pic_offset_arm (pic_reg
, pic_reg
, pic_tmp
));
8142 /* We use an UNSPEC rather than a LABEL_REF because this label
8143 never appears in the code stream. */
8145 labelno
= GEN_INT (pic_labelno
++);
8146 l1
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
8147 l1
= gen_rtx_CONST (VOIDmode
, l1
);
8149 /* On the ARM the PC register contains 'dot + 8' at the time of the
8150 addition, on the Thumb it is 'dot + 4'. */
8151 pic_rtx
= plus_constant (Pmode
, l1
, TARGET_ARM
? 8 : 4);
8152 pic_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, pic_rtx
),
8154 pic_rtx
= gen_rtx_CONST (Pmode
, pic_rtx
);
8158 emit_insn (gen_pic_load_addr_unified (pic_reg
, pic_rtx
, labelno
));
8160 else /* TARGET_THUMB1 */
8162 if (arm_pic_register
!= INVALID_REGNUM
8163 && REGNO (pic_reg
) > LAST_LO_REGNUM
)
8165 /* We will have pushed the pic register, so we should always be
8166 able to find a work register. */
8167 pic_tmp
= gen_rtx_REG (SImode
,
8168 thumb_find_work_register (saved_regs
));
8169 emit_insn (gen_pic_load_addr_thumb1 (pic_tmp
, pic_rtx
));
8170 emit_insn (gen_movsi (pic_offset_table_rtx
, pic_tmp
));
8171 emit_insn (gen_pic_add_dot_plus_four (pic_reg
, pic_reg
, labelno
));
8173 else if (arm_pic_register
!= INVALID_REGNUM
8174 && arm_pic_register
> LAST_LO_REGNUM
8175 && REGNO (pic_reg
) <= LAST_LO_REGNUM
)
8177 emit_insn (gen_pic_load_addr_unified (pic_reg
, pic_rtx
, labelno
));
8178 emit_move_insn (gen_rtx_REG (Pmode
, arm_pic_register
), pic_reg
);
8179 emit_use (gen_rtx_REG (Pmode
, arm_pic_register
));
8182 emit_insn (gen_pic_load_addr_unified (pic_reg
, pic_rtx
, labelno
));
8186 /* Need to emit this whether or not we obey regdecls,
8187 since setjmp/longjmp can cause life info to screw up. */
8191 /* Try to determine whether an object, referenced via ORIG, will be
8192 placed in the text or data segment. This is used in FDPIC mode, to
8193 decide which relocations to use when accessing ORIG. *IS_READONLY
8194 is set to true if ORIG is a read-only location, false otherwise.
8195 Return true if we could determine the location of ORIG, false
8196 otherwise. *IS_READONLY is valid only when we return true. */
8198 arm_is_segment_info_known (rtx orig
, bool *is_readonly
)
8200 *is_readonly
= false;
8202 if (LABEL_REF_P (orig
))
8204 *is_readonly
= true;
8208 if (SYMBOL_REF_P (orig
))
8210 if (CONSTANT_POOL_ADDRESS_P (orig
))
8212 *is_readonly
= true;
8215 if (SYMBOL_REF_LOCAL_P (orig
)
8216 && !SYMBOL_REF_EXTERNAL_P (orig
)
8217 && SYMBOL_REF_DECL (orig
)
8218 && (!DECL_P (SYMBOL_REF_DECL (orig
))
8219 || !DECL_COMMON (SYMBOL_REF_DECL (orig
))))
8221 tree decl
= SYMBOL_REF_DECL (orig
);
8222 tree init
= (TREE_CODE (decl
) == VAR_DECL
)
8223 ? DECL_INITIAL (decl
) : (TREE_CODE (decl
) == CONSTRUCTOR
)
8226 bool named_section
, readonly
;
8228 if (init
&& init
!= error_mark_node
)
8229 reloc
= compute_reloc_for_constant (init
);
8231 named_section
= TREE_CODE (decl
) == VAR_DECL
8232 && lookup_attribute ("section", DECL_ATTRIBUTES (decl
));
8233 readonly
= decl_readonly_section (decl
, reloc
);
8235 /* We don't know where the link script will put a named
8236 section, so return false in such a case. */
8240 *is_readonly
= readonly
;
8244 /* We don't know. */
8251 /* Generate code to load the address of a static var when flag_pic is set. */
8253 arm_pic_static_addr (rtx orig
, rtx reg
)
8255 rtx l1
, labelno
, offset_rtx
;
8258 gcc_assert (flag_pic
);
8260 bool is_readonly
= false;
8261 bool info_known
= false;
8264 && SYMBOL_REF_P (orig
)
8265 && !SYMBOL_REF_FUNCTION_P (orig
))
8266 info_known
= arm_is_segment_info_known (orig
, &is_readonly
);
8269 && SYMBOL_REF_P (orig
)
8270 && !SYMBOL_REF_FUNCTION_P (orig
)
8273 /* We don't know where orig is stored, so we have be
8274 pessimistic and use a GOT relocation. */
8275 rtx pic_reg
= gen_rtx_REG (Pmode
, FDPIC_REGNUM
);
8277 insn
= calculate_pic_address_constant (reg
, pic_reg
, orig
);
8279 else if (TARGET_FDPIC
8280 && SYMBOL_REF_P (orig
)
8281 && (SYMBOL_REF_FUNCTION_P (orig
)
8284 /* We use the GOTOFF relocation. */
8285 rtx pic_reg
= gen_rtx_REG (Pmode
, FDPIC_REGNUM
);
8287 rtx l1
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, orig
), UNSPEC_PIC_SYM
);
8288 emit_insn (gen_movsi (reg
, l1
));
8289 insn
= emit_insn (gen_addsi3 (reg
, reg
, pic_reg
));
8293 /* Not FDPIC, not SYMBOL_REF_P or readonly: we can use
8294 PC-relative access. */
8295 /* We use an UNSPEC rather than a LABEL_REF because this label
8296 never appears in the code stream. */
8297 labelno
= GEN_INT (pic_labelno
++);
8298 l1
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
8299 l1
= gen_rtx_CONST (VOIDmode
, l1
);
8301 /* On the ARM the PC register contains 'dot + 8' at the time of the
8302 addition, on the Thumb it is 'dot + 4'. */
8303 offset_rtx
= plus_constant (Pmode
, l1
, TARGET_ARM
? 8 : 4);
8304 offset_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, orig
, offset_rtx
),
8305 UNSPEC_SYMBOL_OFFSET
);
8306 offset_rtx
= gen_rtx_CONST (Pmode
, offset_rtx
);
8308 insn
= emit_insn (gen_pic_load_addr_unified (reg
, offset_rtx
,
8315 /* Return nonzero if X is valid as an ARM state addressing register. */
8317 arm_address_register_rtx_p (rtx x
, int strict_p
)
8327 return ARM_REGNO_OK_FOR_BASE_P (regno
);
8329 return (regno
<= LAST_ARM_REGNUM
8330 || regno
>= FIRST_PSEUDO_REGISTER
8331 || regno
== FRAME_POINTER_REGNUM
8332 || regno
== ARG_POINTER_REGNUM
);
8335 /* Return TRUE if this rtx is the difference of a symbol and a label,
8336 and will reduce to a PC-relative relocation in the object file.
8337 Expressions like this can be left alone when generating PIC, rather
8338 than forced through the GOT. */
8340 pcrel_constant_p (rtx x
)
8342 if (GET_CODE (x
) == MINUS
)
8343 return symbol_mentioned_p (XEXP (x
, 0)) && label_mentioned_p (XEXP (x
, 1));
8348 /* Return true if X will surely end up in an index register after next
8351 will_be_in_index_register (const_rtx x
)
8353 /* arm.md: calculate_pic_address will split this into a register. */
8354 return GET_CODE (x
) == UNSPEC
&& (XINT (x
, 1) == UNSPEC_PIC_SYM
);
8357 /* Return nonzero if X is a valid ARM state address operand. */
8359 arm_legitimate_address_outer_p (machine_mode mode
, rtx x
, RTX_CODE outer
,
8363 enum rtx_code code
= GET_CODE (x
);
8365 if (arm_address_register_rtx_p (x
, strict_p
))
8368 use_ldrd
= (TARGET_LDRD
8369 && (mode
== DImode
|| mode
== DFmode
));
8371 if (code
== POST_INC
|| code
== PRE_DEC
8372 || ((code
== PRE_INC
|| code
== POST_DEC
)
8373 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
8374 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
8376 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
8377 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
8378 && GET_CODE (XEXP (x
, 1)) == PLUS
8379 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
8381 rtx addend
= XEXP (XEXP (x
, 1), 1);
8383 /* Don't allow ldrd post increment by register because it's hard
8384 to fixup invalid register choices. */
8386 && GET_CODE (x
) == POST_MODIFY
8390 return ((use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)
8391 && arm_legitimate_index_p (mode
, addend
, outer
, strict_p
));
8394 /* After reload constants split into minipools will have addresses
8395 from a LABEL_REF. */
8396 else if (reload_completed
8397 && (code
== LABEL_REF
8399 && GET_CODE (XEXP (x
, 0)) == PLUS
8400 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
8401 && CONST_INT_P (XEXP (XEXP (x
, 0), 1)))))
8404 else if (mode
== TImode
|| (TARGET_NEON
&& VALID_NEON_STRUCT_MODE (mode
)))
8407 else if (code
== PLUS
)
8409 rtx xop0
= XEXP (x
, 0);
8410 rtx xop1
= XEXP (x
, 1);
8412 return ((arm_address_register_rtx_p (xop0
, strict_p
)
8413 && ((CONST_INT_P (xop1
)
8414 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
))
8415 || (!strict_p
&& will_be_in_index_register (xop1
))))
8416 || (arm_address_register_rtx_p (xop1
, strict_p
)
8417 && arm_legitimate_index_p (mode
, xop0
, outer
, strict_p
)));
8421 /* Reload currently can't handle MINUS, so disable this for now */
8422 else if (GET_CODE (x
) == MINUS
)
8424 rtx xop0
= XEXP (x
, 0);
8425 rtx xop1
= XEXP (x
, 1);
8427 return (arm_address_register_rtx_p (xop0
, strict_p
)
8428 && arm_legitimate_index_p (mode
, xop1
, outer
, strict_p
));
8432 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
8433 && code
== SYMBOL_REF
8434 && CONSTANT_POOL_ADDRESS_P (x
)
8436 && symbol_mentioned_p (get_pool_constant (x
))
8437 && ! pcrel_constant_p (get_pool_constant (x
))))
8443 /* Return true if we can avoid creating a constant pool entry for x. */
8445 can_avoid_literal_pool_for_label_p (rtx x
)
8447 /* Normally we can assign constant values to target registers without
8448 the help of constant pool. But there are cases we have to use constant
8450 1) assign a label to register.
8451 2) sign-extend a 8bit value to 32bit and then assign to register.
8453 Constant pool access in format:
8454 (set (reg r0) (mem (symbol_ref (".LC0"))))
8455 will cause the use of literal pool (later in function arm_reorg).
8456 So here we mark such format as an invalid format, then the compiler
8457 will adjust it into:
8458 (set (reg r0) (symbol_ref (".LC0")))
8459 (set (reg r0) (mem (reg r0))).
8460 No extra register is required, and (mem (reg r0)) won't cause the use
8461 of literal pools. */
8462 if (arm_disable_literal_pool
&& SYMBOL_REF_P (x
)
8463 && CONSTANT_POOL_ADDRESS_P (x
))
8469 /* Return nonzero if X is a valid Thumb-2 address operand. */
8471 thumb2_legitimate_address_p (machine_mode mode
, rtx x
, int strict_p
)
8474 enum rtx_code code
= GET_CODE (x
);
8477 && (mode
== V8QImode
|| mode
== E_V4QImode
|| mode
== V4HImode
))
8478 return mve_vector_mem_operand (mode
, x
, strict_p
);
8480 if (arm_address_register_rtx_p (x
, strict_p
))
8483 use_ldrd
= (TARGET_LDRD
8484 && (mode
== DImode
|| mode
== DFmode
));
8486 if (code
== POST_INC
|| code
== PRE_DEC
8487 || ((code
== PRE_INC
|| code
== POST_DEC
)
8488 && (use_ldrd
|| GET_MODE_SIZE (mode
) <= 4)))
8489 return arm_address_register_rtx_p (XEXP (x
, 0), strict_p
);
8491 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
8492 && arm_address_register_rtx_p (XEXP (x
, 0), strict_p
)
8493 && GET_CODE (XEXP (x
, 1)) == PLUS
8494 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
8496 /* Thumb-2 only has autoincrement by constant. */
8497 rtx addend
= XEXP (XEXP (x
, 1), 1);
8498 HOST_WIDE_INT offset
;
8500 if (!CONST_INT_P (addend
))
8503 offset
= INTVAL(addend
);
8504 if (GET_MODE_SIZE (mode
) <= 4)
8505 return (offset
> -256 && offset
< 256);
8507 return (use_ldrd
&& offset
> -1024 && offset
< 1024
8508 && (offset
& 3) == 0);
8511 /* After reload constants split into minipools will have addresses
8512 from a LABEL_REF. */
8513 else if (reload_completed
8514 && (code
== LABEL_REF
8516 && GET_CODE (XEXP (x
, 0)) == PLUS
8517 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
8518 && CONST_INT_P (XEXP (XEXP (x
, 0), 1)))))
8521 else if (mode
== TImode
8522 || (TARGET_NEON
&& VALID_NEON_STRUCT_MODE (mode
))
8523 || (TARGET_HAVE_MVE
&& VALID_MVE_STRUCT_MODE (mode
)))
8526 else if (code
== PLUS
)
8528 rtx xop0
= XEXP (x
, 0);
8529 rtx xop1
= XEXP (x
, 1);
8531 return ((arm_address_register_rtx_p (xop0
, strict_p
)
8532 && (thumb2_legitimate_index_p (mode
, xop1
, strict_p
)
8533 || (!strict_p
&& will_be_in_index_register (xop1
))))
8534 || (arm_address_register_rtx_p (xop1
, strict_p
)
8535 && thumb2_legitimate_index_p (mode
, xop0
, strict_p
)));
8538 else if (can_avoid_literal_pool_for_label_p (x
))
8541 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
8542 && code
== SYMBOL_REF
8543 && CONSTANT_POOL_ADDRESS_P (x
)
8545 && symbol_mentioned_p (get_pool_constant (x
))
8546 && ! pcrel_constant_p (get_pool_constant (x
))))
8552 /* Return nonzero if INDEX is valid for an address index operand in
8555 arm_legitimate_index_p (machine_mode mode
, rtx index
, RTX_CODE outer
,
8558 HOST_WIDE_INT range
;
8559 enum rtx_code code
= GET_CODE (index
);
8561 /* Standard coprocessor addressing modes. */
8562 if (TARGET_HARD_FLOAT
8563 && (mode
== SFmode
|| mode
== DFmode
))
8564 return (code
== CONST_INT
&& INTVAL (index
) < 1024
8565 && INTVAL (index
) > -1024
8566 && (INTVAL (index
) & 3) == 0);
8568 /* For quad modes, we restrict the constant offset to be slightly less
8569 than what the instruction format permits. We do this because for
8570 quad mode moves, we will actually decompose them into two separate
8571 double-mode reads or writes. INDEX must therefore be a valid
8572 (double-mode) offset and so should INDEX+8. */
8573 if (TARGET_NEON
&& VALID_NEON_QREG_MODE (mode
))
8574 return (code
== CONST_INT
8575 && INTVAL (index
) < 1016
8576 && INTVAL (index
) > -1024
8577 && (INTVAL (index
) & 3) == 0);
8579 /* We have no such constraint on double mode offsets, so we permit the
8580 full range of the instruction format. */
8581 if (TARGET_NEON
&& VALID_NEON_DREG_MODE (mode
))
8582 return (code
== CONST_INT
8583 && INTVAL (index
) < 1024
8584 && INTVAL (index
) > -1024
8585 && (INTVAL (index
) & 3) == 0);
8587 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
8588 return (code
== CONST_INT
8589 && INTVAL (index
) < 1024
8590 && INTVAL (index
) > -1024
8591 && (INTVAL (index
) & 3) == 0);
8593 if (arm_address_register_rtx_p (index
, strict_p
)
8594 && (GET_MODE_SIZE (mode
) <= 4))
8597 if (mode
== DImode
|| mode
== DFmode
)
8599 if (code
== CONST_INT
)
8601 HOST_WIDE_INT val
= INTVAL (index
);
8603 /* Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
8604 If vldr is selected it uses arm_coproc_mem_operand. */
8606 return val
> -256 && val
< 256;
8608 return val
> -4096 && val
< 4092;
8611 return TARGET_LDRD
&& arm_address_register_rtx_p (index
, strict_p
);
8614 if (GET_MODE_SIZE (mode
) <= 4
8618 || (mode
== QImode
&& outer
== SIGN_EXTEND
))))
8622 rtx xiop0
= XEXP (index
, 0);
8623 rtx xiop1
= XEXP (index
, 1);
8625 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
8626 && power_of_two_operand (xiop1
, SImode
))
8627 || (arm_address_register_rtx_p (xiop1
, strict_p
)
8628 && power_of_two_operand (xiop0
, SImode
)));
8630 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
8631 || code
== ASHIFT
|| code
== ROTATERT
)
8633 rtx op
= XEXP (index
, 1);
8635 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
8638 && INTVAL (op
) <= 31);
8642 /* For ARM v4 we may be doing a sign-extend operation during the
8648 || (outer
== SIGN_EXTEND
&& mode
== QImode
))
8654 range
= (mode
== HImode
|| mode
== HFmode
) ? 4095 : 4096;
8656 return (code
== CONST_INT
8657 && INTVAL (index
) < range
8658 && INTVAL (index
) > -range
);
8661 /* Return true if OP is a valid index scaling factor for Thumb-2 address
8662 index operand. i.e. 1, 2, 4 or 8. */
8664 thumb2_index_mul_operand (rtx op
)
8668 if (!CONST_INT_P (op
))
8672 return (val
== 1 || val
== 2 || val
== 4 || val
== 8);
8675 /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */
8677 thumb2_legitimate_index_p (machine_mode mode
, rtx index
, int strict_p
)
8679 enum rtx_code code
= GET_CODE (index
);
8681 /* ??? Combine arm and thumb2 coprocessor addressing modes. */
8682 /* Standard coprocessor addressing modes. */
8684 && (mode
== SFmode
|| mode
== DFmode
))
8685 return (code
== CONST_INT
&& INTVAL (index
) < 1024
8686 /* Thumb-2 allows only > -256 index range for it's core register
8687 load/stores. Since we allow SF/DF in core registers, we have
8688 to use the intersection between -256~4096 (core) and -1024~1024
8690 && INTVAL (index
) > -256
8691 && (INTVAL (index
) & 3) == 0);
8693 if (TARGET_REALLY_IWMMXT
&& VALID_IWMMXT_REG_MODE (mode
))
8695 /* For DImode assume values will usually live in core regs
8696 and only allow LDRD addressing modes. */
8697 if (!TARGET_LDRD
|| mode
!= DImode
)
8698 return (code
== CONST_INT
8699 && INTVAL (index
) < 1024
8700 && INTVAL (index
) > -1024
8701 && (INTVAL (index
) & 3) == 0);
8704 /* For quad modes, we restrict the constant offset to be slightly less
8705 than what the instruction format permits. We do this because for
8706 quad mode moves, we will actually decompose them into two separate
8707 double-mode reads or writes. INDEX must therefore be a valid
8708 (double-mode) offset and so should INDEX+8. */
8709 if (TARGET_NEON
&& VALID_NEON_QREG_MODE (mode
))
8710 return (code
== CONST_INT
8711 && INTVAL (index
) < 1016
8712 && INTVAL (index
) > -1024
8713 && (INTVAL (index
) & 3) == 0);
8715 /* We have no such constraint on double mode offsets, so we permit the
8716 full range of the instruction format. */
8717 if (TARGET_NEON
&& VALID_NEON_DREG_MODE (mode
))
8718 return (code
== CONST_INT
8719 && INTVAL (index
) < 1024
8720 && INTVAL (index
) > -1024
8721 && (INTVAL (index
) & 3) == 0);
8723 if (arm_address_register_rtx_p (index
, strict_p
)
8724 && (GET_MODE_SIZE (mode
) <= 4))
8727 if (mode
== DImode
|| mode
== DFmode
)
8729 if (code
== CONST_INT
)
8731 HOST_WIDE_INT val
= INTVAL (index
);
8732 /* Thumb-2 ldrd only has reg+const addressing modes.
8733 Assume we emit ldrd or 2x ldr if !TARGET_LDRD.
8734 If vldr is selected it uses arm_coproc_mem_operand. */
8736 return IN_RANGE (val
, -1020, 1020) && (val
& 3) == 0;
8738 return IN_RANGE (val
, -255, 4095 - 4);
8746 rtx xiop0
= XEXP (index
, 0);
8747 rtx xiop1
= XEXP (index
, 1);
8749 return ((arm_address_register_rtx_p (xiop0
, strict_p
)
8750 && thumb2_index_mul_operand (xiop1
))
8751 || (arm_address_register_rtx_p (xiop1
, strict_p
)
8752 && thumb2_index_mul_operand (xiop0
)));
8754 else if (code
== ASHIFT
)
8756 rtx op
= XEXP (index
, 1);
8758 return (arm_address_register_rtx_p (XEXP (index
, 0), strict_p
)
8761 && INTVAL (op
) <= 3);
8764 return (code
== CONST_INT
8765 && INTVAL (index
) < 4096
8766 && INTVAL (index
) > -256);
8769 /* Return nonzero if X is valid as a 16-bit Thumb state base register. */
8771 thumb1_base_register_rtx_p (rtx x
, machine_mode mode
, int strict_p
)
8781 return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno
, mode
);
8783 return (regno
<= LAST_LO_REGNUM
8784 || regno
> LAST_VIRTUAL_REGISTER
8785 || regno
== FRAME_POINTER_REGNUM
8786 || (GET_MODE_SIZE (mode
) >= 4
8787 && (regno
== STACK_POINTER_REGNUM
8788 || regno
>= FIRST_PSEUDO_REGISTER
8789 || x
== hard_frame_pointer_rtx
8790 || x
== arg_pointer_rtx
)));
8793 /* Return nonzero if x is a legitimate index register. This is the case
8794 for any base register that can access a QImode object. */
8796 thumb1_index_register_rtx_p (rtx x
, int strict_p
)
8798 return thumb1_base_register_rtx_p (x
, QImode
, strict_p
);
8801 /* Return nonzero if x is a legitimate 16-bit Thumb-state address.
8803 The AP may be eliminated to either the SP or the FP, so we use the
8804 least common denominator, e.g. SImode, and offsets from 0 to 64.
8806 ??? Verify whether the above is the right approach.
8808 ??? Also, the FP may be eliminated to the SP, so perhaps that
8809 needs special handling also.
8811 ??? Look at how the mips16 port solves this problem. It probably uses
8812 better ways to solve some of these problems.
8814 Although it is not incorrect, we don't accept QImode and HImode
8815 addresses based on the frame pointer or arg pointer until the
8816 reload pass starts. This is so that eliminating such addresses
8817 into stack based ones won't produce impossible code. */
8819 thumb1_legitimate_address_p (machine_mode mode
, rtx x
, int strict_p
)
8821 if (TARGET_HAVE_MOVT
&& can_avoid_literal_pool_for_label_p (x
))
8824 /* ??? Not clear if this is right. Experiment. */
8825 if (GET_MODE_SIZE (mode
) < 4
8826 && !(reload_in_progress
|| reload_completed
)
8827 && (reg_mentioned_p (frame_pointer_rtx
, x
)
8828 || reg_mentioned_p (arg_pointer_rtx
, x
)
8829 || reg_mentioned_p (virtual_incoming_args_rtx
, x
)
8830 || reg_mentioned_p (virtual_outgoing_args_rtx
, x
)
8831 || reg_mentioned_p (virtual_stack_dynamic_rtx
, x
)
8832 || reg_mentioned_p (virtual_stack_vars_rtx
, x
)))
8835 /* Accept any base register. SP only in SImode or larger. */
8836 else if (thumb1_base_register_rtx_p (x
, mode
, strict_p
))
8839 /* This is PC relative data before arm_reorg runs. */
8840 else if (GET_MODE_SIZE (mode
) >= 4 && CONSTANT_P (x
)
8842 && CONSTANT_POOL_ADDRESS_P (x
) && !flag_pic
8843 && !arm_disable_literal_pool
)
8846 /* This is PC relative data after arm_reorg runs. */
8847 else if ((GET_MODE_SIZE (mode
) >= 4 || mode
== HFmode
)
8850 || (GET_CODE (x
) == CONST
8851 && GET_CODE (XEXP (x
, 0)) == PLUS
8852 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
8853 && CONST_INT_P (XEXP (XEXP (x
, 0), 1)))))
8856 /* Post-inc indexing only supported for SImode and larger. */
8857 else if (GET_CODE (x
) == POST_INC
&& GET_MODE_SIZE (mode
) >= 4
8858 && thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
))
8861 else if (GET_CODE (x
) == PLUS
)
8863 /* REG+REG address can be any two index registers. */
8864 /* We disallow FRAME+REG addressing since we know that FRAME
8865 will be replaced with STACK, and SP relative addressing only
8866 permits SP+OFFSET. */
8867 if (GET_MODE_SIZE (mode
) <= 4
8868 && XEXP (x
, 0) != frame_pointer_rtx
8869 && XEXP (x
, 1) != frame_pointer_rtx
8870 && thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
)
8871 && (thumb1_index_register_rtx_p (XEXP (x
, 1), strict_p
)
8872 || (!strict_p
&& will_be_in_index_register (XEXP (x
, 1)))))
8875 /* REG+const has 5-7 bit offset for non-SP registers. */
8876 else if ((thumb1_index_register_rtx_p (XEXP (x
, 0), strict_p
)
8877 || XEXP (x
, 0) == arg_pointer_rtx
)
8878 && CONST_INT_P (XEXP (x
, 1))
8879 && thumb_legitimate_offset_p (mode
, INTVAL (XEXP (x
, 1))))
8882 /* REG+const has 10-bit offset for SP, but only SImode and
8883 larger is supported. */
8884 /* ??? Should probably check for DI/DFmode overflow here
8885 just like GO_IF_LEGITIMATE_OFFSET does. */
8886 else if (REG_P (XEXP (x
, 0))
8887 && REGNO (XEXP (x
, 0)) == STACK_POINTER_REGNUM
8888 && GET_MODE_SIZE (mode
) >= 4
8889 && CONST_INT_P (XEXP (x
, 1))
8890 && INTVAL (XEXP (x
, 1)) >= 0
8891 && INTVAL (XEXP (x
, 1)) + GET_MODE_SIZE (mode
) <= 1024
8892 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
8895 else if (REG_P (XEXP (x
, 0))
8896 && (REGNO (XEXP (x
, 0)) == FRAME_POINTER_REGNUM
8897 || REGNO (XEXP (x
, 0)) == ARG_POINTER_REGNUM
8898 || (REGNO (XEXP (x
, 0)) >= FIRST_VIRTUAL_REGISTER
8899 && REGNO (XEXP (x
, 0))
8900 <= LAST_VIRTUAL_POINTER_REGISTER
))
8901 && GET_MODE_SIZE (mode
) >= 4
8902 && CONST_INT_P (XEXP (x
, 1))
8903 && (INTVAL (XEXP (x
, 1)) & 3) == 0)
8907 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
8908 && GET_MODE_SIZE (mode
) == 4
8910 && CONSTANT_POOL_ADDRESS_P (x
)
8911 && !arm_disable_literal_pool
8913 && symbol_mentioned_p (get_pool_constant (x
))
8914 && ! pcrel_constant_p (get_pool_constant (x
))))
8920 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
8921 instruction of mode MODE. */
8923 thumb_legitimate_offset_p (machine_mode mode
, HOST_WIDE_INT val
)
8925 switch (GET_MODE_SIZE (mode
))
8928 return val
>= 0 && val
< 32;
8931 return val
>= 0 && val
< 64 && (val
& 1) == 0;
8935 && (val
+ GET_MODE_SIZE (mode
)) <= 128
8941 arm_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
8944 return arm_legitimate_address_outer_p (mode
, x
, SET
, strict_p
);
8945 else if (TARGET_THUMB2
)
8946 return thumb2_legitimate_address_p (mode
, x
, strict_p
);
8947 else /* if (TARGET_THUMB1) */
8948 return thumb1_legitimate_address_p (mode
, x
, strict_p
);
8951 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS.
8953 Given an rtx X being reloaded into a reg required to be
8954 in class CLASS, return the class of reg to actually use.
8955 In general this is just CLASS, but for the Thumb core registers and
8956 immediate constants we prefer a LO_REGS class or a subset. */
8959 arm_preferred_reload_class (rtx x ATTRIBUTE_UNUSED
, reg_class_t rclass
)
8965 if (rclass
== GENERAL_REGS
)
8972 /* Build the SYMBOL_REF for __tls_get_addr. */
8974 static GTY(()) rtx tls_get_addr_libfunc
;
8977 get_tls_get_addr (void)
8979 if (!tls_get_addr_libfunc
)
8980 tls_get_addr_libfunc
= init_one_libfunc ("__tls_get_addr");
8981 return tls_get_addr_libfunc
;
8985 arm_load_tp (rtx target
)
8988 target
= gen_reg_rtx (SImode
);
8992 /* Can return in any reg. */
8993 emit_insn (gen_load_tp_hard (target
));
8997 /* Always returned in r0. Immediately copy the result into a pseudo,
8998 otherwise other uses of r0 (e.g. setting up function arguments) may
8999 clobber the value. */
9005 rtx fdpic_reg
= gen_rtx_REG (Pmode
, FDPIC_REGNUM
);
9006 rtx initial_fdpic_reg
= get_hard_reg_initial_val (Pmode
, FDPIC_REGNUM
);
9008 emit_insn (gen_load_tp_soft_fdpic ());
9011 emit_insn (gen_restore_pic_register_after_call(fdpic_reg
, initial_fdpic_reg
));
9014 emit_insn (gen_load_tp_soft ());
9016 tmp
= gen_rtx_REG (SImode
, R0_REGNUM
);
9017 emit_move_insn (target
, tmp
);
9023 load_tls_operand (rtx x
, rtx reg
)
9027 if (reg
== NULL_RTX
)
9028 reg
= gen_reg_rtx (SImode
);
9030 tmp
= gen_rtx_CONST (SImode
, x
);
9032 emit_move_insn (reg
, tmp
);
9038 arm_call_tls_get_addr (rtx x
, rtx reg
, rtx
*valuep
, int reloc
)
9040 rtx label
, labelno
= NULL_RTX
, sum
;
9042 gcc_assert (reloc
!= TLS_DESCSEQ
);
9047 sum
= gen_rtx_UNSPEC (Pmode
,
9048 gen_rtvec (2, x
, GEN_INT (reloc
)),
9053 labelno
= GEN_INT (pic_labelno
++);
9054 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
9055 label
= gen_rtx_CONST (VOIDmode
, label
);
9057 sum
= gen_rtx_UNSPEC (Pmode
,
9058 gen_rtvec (4, x
, GEN_INT (reloc
), label
,
9059 GEN_INT (TARGET_ARM
? 8 : 4)),
9062 reg
= load_tls_operand (sum
, reg
);
9065 emit_insn (gen_addsi3 (reg
, reg
, gen_rtx_REG (Pmode
, FDPIC_REGNUM
)));
9066 else if (TARGET_ARM
)
9067 emit_insn (gen_pic_add_dot_plus_eight (reg
, reg
, labelno
));
9069 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
9071 *valuep
= emit_library_call_value (get_tls_get_addr (), NULL_RTX
,
9072 LCT_PURE
, /* LCT_CONST? */
9075 rtx_insn
*insns
= get_insns ();
9082 arm_tls_descseq_addr (rtx x
, rtx reg
)
9084 rtx labelno
= GEN_INT (pic_labelno
++);
9085 rtx label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
9086 rtx sum
= gen_rtx_UNSPEC (Pmode
,
9087 gen_rtvec (4, x
, GEN_INT (TLS_DESCSEQ
),
9088 gen_rtx_CONST (VOIDmode
, label
),
9089 GEN_INT (!TARGET_ARM
)),
9091 rtx reg0
= load_tls_operand (sum
, gen_rtx_REG (SImode
, R0_REGNUM
));
9093 emit_insn (gen_tlscall (x
, labelno
));
9095 reg
= gen_reg_rtx (SImode
);
9097 gcc_assert (REGNO (reg
) != R0_REGNUM
);
9099 emit_move_insn (reg
, reg0
);
9106 legitimize_tls_address (rtx x
, rtx reg
)
9108 rtx dest
, tp
, label
, labelno
, sum
, ret
, eqv
, addend
;
9110 unsigned int model
= SYMBOL_REF_TLS_MODEL (x
);
9114 case TLS_MODEL_GLOBAL_DYNAMIC
:
9115 if (TARGET_GNU2_TLS
)
9117 gcc_assert (!TARGET_FDPIC
);
9119 reg
= arm_tls_descseq_addr (x
, reg
);
9121 tp
= arm_load_tp (NULL_RTX
);
9123 dest
= gen_rtx_PLUS (Pmode
, tp
, reg
);
9127 /* Original scheme */
9129 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_GD32_FDPIC
);
9131 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_GD32
);
9132 dest
= gen_reg_rtx (Pmode
);
9133 emit_libcall_block (insns
, dest
, ret
, x
);
9137 case TLS_MODEL_LOCAL_DYNAMIC
:
9138 if (TARGET_GNU2_TLS
)
9140 gcc_assert (!TARGET_FDPIC
);
9142 reg
= arm_tls_descseq_addr (x
, reg
);
9144 tp
= arm_load_tp (NULL_RTX
);
9146 dest
= gen_rtx_PLUS (Pmode
, tp
, reg
);
9151 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_LDM32_FDPIC
);
9153 insns
= arm_call_tls_get_addr (x
, reg
, &ret
, TLS_LDM32
);
9155 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
9156 share the LDM result with other LD model accesses. */
9157 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
),
9159 dest
= gen_reg_rtx (Pmode
);
9160 emit_libcall_block (insns
, dest
, ret
, eqv
);
9162 /* Load the addend. */
9163 addend
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
,
9164 GEN_INT (TLS_LDO32
)),
9166 addend
= force_reg (SImode
, gen_rtx_CONST (SImode
, addend
));
9167 dest
= gen_rtx_PLUS (Pmode
, dest
, addend
);
9171 case TLS_MODEL_INITIAL_EXEC
:
9174 sum
= gen_rtx_UNSPEC (Pmode
,
9175 gen_rtvec (2, x
, GEN_INT (TLS_IE32_FDPIC
)),
9177 reg
= load_tls_operand (sum
, reg
);
9178 emit_insn (gen_addsi3 (reg
, reg
, gen_rtx_REG (Pmode
, FDPIC_REGNUM
)));
9179 emit_move_insn (reg
, gen_rtx_MEM (Pmode
, reg
));
9183 labelno
= GEN_INT (pic_labelno
++);
9184 label
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, labelno
), UNSPEC_PIC_LABEL
);
9185 label
= gen_rtx_CONST (VOIDmode
, label
);
9186 sum
= gen_rtx_UNSPEC (Pmode
,
9187 gen_rtvec (4, x
, GEN_INT (TLS_IE32
), label
,
9188 GEN_INT (TARGET_ARM
? 8 : 4)),
9190 reg
= load_tls_operand (sum
, reg
);
9193 emit_insn (gen_tls_load_dot_plus_eight (reg
, reg
, labelno
));
9194 else if (TARGET_THUMB2
)
9195 emit_insn (gen_tls_load_dot_plus_four (reg
, NULL
, reg
, labelno
));
9198 emit_insn (gen_pic_add_dot_plus_four (reg
, reg
, labelno
));
9199 emit_move_insn (reg
, gen_const_mem (SImode
, reg
));
9203 tp
= arm_load_tp (NULL_RTX
);
9205 return gen_rtx_PLUS (Pmode
, tp
, reg
);
9207 case TLS_MODEL_LOCAL_EXEC
:
9208 tp
= arm_load_tp (NULL_RTX
);
9210 reg
= gen_rtx_UNSPEC (Pmode
,
9211 gen_rtvec (2, x
, GEN_INT (TLS_LE32
)),
9213 reg
= force_reg (SImode
, gen_rtx_CONST (SImode
, reg
));
9215 return gen_rtx_PLUS (Pmode
, tp
, reg
);
9222 /* Try machine-dependent ways of modifying an illegitimate address
9223 to be legitimate. If we find one, return the new, valid address. */
9225 arm_legitimize_address (rtx x
, rtx orig_x
, machine_mode mode
)
9227 if (arm_tls_referenced_p (x
))
9231 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
9233 addend
= XEXP (XEXP (x
, 0), 1);
9234 x
= XEXP (XEXP (x
, 0), 0);
9237 if (!SYMBOL_REF_P (x
))
9240 gcc_assert (SYMBOL_REF_TLS_MODEL (x
) != 0);
9242 x
= legitimize_tls_address (x
, NULL_RTX
);
9246 x
= gen_rtx_PLUS (SImode
, x
, addend
);
9254 return thumb_legitimize_address (x
, orig_x
, mode
);
9256 if (GET_CODE (x
) == PLUS
)
9258 rtx xop0
= XEXP (x
, 0);
9259 rtx xop1
= XEXP (x
, 1);
9261 if (CONSTANT_P (xop0
) && !symbol_mentioned_p (xop0
))
9262 xop0
= force_reg (SImode
, xop0
);
9264 if (CONSTANT_P (xop1
) && !CONST_INT_P (xop1
)
9265 && !symbol_mentioned_p (xop1
))
9266 xop1
= force_reg (SImode
, xop1
);
9268 if (ARM_BASE_REGISTER_RTX_P (xop0
)
9269 && CONST_INT_P (xop1
))
9271 HOST_WIDE_INT n
, low_n
;
9275 /* VFP addressing modes actually allow greater offsets, but for
9276 now we just stick with the lowest common denominator. */
9277 if (mode
== DImode
|| mode
== DFmode
)
9289 low_n
= ((mode
) == TImode
? 0
9290 : n
>= 0 ? (n
& 0xfff) : -((-n
) & 0xfff));
9294 base_reg
= gen_reg_rtx (SImode
);
9295 val
= force_operand (plus_constant (Pmode
, xop0
, n
), NULL_RTX
);
9296 emit_move_insn (base_reg
, val
);
9297 x
= plus_constant (Pmode
, base_reg
, low_n
);
9299 else if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
9300 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
9303 /* XXX We don't allow MINUS any more -- see comment in
9304 arm_legitimate_address_outer_p (). */
9305 else if (GET_CODE (x
) == MINUS
)
9307 rtx xop0
= XEXP (x
, 0);
9308 rtx xop1
= XEXP (x
, 1);
9310 if (CONSTANT_P (xop0
))
9311 xop0
= force_reg (SImode
, xop0
);
9313 if (CONSTANT_P (xop1
) && ! symbol_mentioned_p (xop1
))
9314 xop1
= force_reg (SImode
, xop1
);
9316 if (xop0
!= XEXP (x
, 0) || xop1
!= XEXP (x
, 1))
9317 x
= gen_rtx_MINUS (SImode
, xop0
, xop1
);
9320 /* Make sure to take full advantage of the pre-indexed addressing mode
9321 with absolute addresses which often allows for the base register to
9322 be factorized for multiple adjacent memory references, and it might
9323 even allows for the mini pool to be avoided entirely. */
9324 else if (CONST_INT_P (x
) && optimize
> 0)
9327 HOST_WIDE_INT mask
, base
, index
;
9330 /* LDR and LDRB can use a 12-bit index, ldrsb and the rest can
9331 only use a 8-bit index. So let's use a 12-bit index for
9332 SImode only and hope that arm_gen_constant will enable LDRB
9333 to use more bits. */
9334 bits
= (mode
== SImode
) ? 12 : 8;
9335 mask
= (1 << bits
) - 1;
9336 base
= INTVAL (x
) & ~mask
;
9337 index
= INTVAL (x
) & mask
;
9338 if (TARGET_ARM
&& bit_count (base
& 0xffffffff) > (32 - bits
)/2)
9340 /* It'll most probably be more efficient to generate the
9341 base with more bits set and use a negative index instead.
9342 Don't do this for Thumb as negative offsets are much more
9347 base_reg
= force_reg (SImode
, GEN_INT (base
));
9348 x
= plus_constant (Pmode
, base_reg
, index
);
9353 /* We need to find and carefully transform any SYMBOL and LABEL
9354 references; so go back to the original address expression. */
9355 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
, NULL_RTX
,
9356 false /*compute_now*/);
9358 if (new_x
!= orig_x
)
9366 /* Try machine-dependent ways of modifying an illegitimate Thumb address
9367 to be legitimate. If we find one, return the new, valid address. */
9369 thumb_legitimize_address (rtx x
, rtx orig_x
, machine_mode mode
)
9371 if (GET_CODE (x
) == PLUS
9372 && CONST_INT_P (XEXP (x
, 1))
9373 && (INTVAL (XEXP (x
, 1)) >= 32 * GET_MODE_SIZE (mode
)
9374 || INTVAL (XEXP (x
, 1)) < 0))
9376 rtx xop0
= XEXP (x
, 0);
9377 rtx xop1
= XEXP (x
, 1);
9378 HOST_WIDE_INT offset
= INTVAL (xop1
);
9380 /* Try and fold the offset into a biasing of the base register and
9381 then offsetting that. Don't do this when optimizing for space
9382 since it can cause too many CSEs. */
9383 if (optimize_size
&& offset
>= 0
9384 && offset
< 256 + 31 * GET_MODE_SIZE (mode
))
9386 HOST_WIDE_INT delta
;
9389 delta
= offset
- (256 - GET_MODE_SIZE (mode
));
9390 else if (offset
< 32 * GET_MODE_SIZE (mode
) + 8)
9391 delta
= 31 * GET_MODE_SIZE (mode
);
9393 delta
= offset
& (~31 * GET_MODE_SIZE (mode
));
9395 xop0
= force_operand (plus_constant (Pmode
, xop0
, offset
- delta
),
9397 x
= plus_constant (Pmode
, xop0
, delta
);
9399 else if (offset
< 0 && offset
> -256)
9400 /* Small negative offsets are best done with a subtract before the
9401 dereference, forcing these into a register normally takes two
9403 x
= force_operand (x
, NULL_RTX
);
9406 /* For the remaining cases, force the constant into a register. */
9407 xop1
= force_reg (SImode
, xop1
);
9408 x
= gen_rtx_PLUS (SImode
, xop0
, xop1
);
9411 else if (GET_CODE (x
) == PLUS
9412 && s_register_operand (XEXP (x
, 1), SImode
)
9413 && !s_register_operand (XEXP (x
, 0), SImode
))
9415 rtx xop0
= force_operand (XEXP (x
, 0), NULL_RTX
);
9417 x
= gen_rtx_PLUS (SImode
, xop0
, XEXP (x
, 1));
9422 /* We need to find and carefully transform any SYMBOL and LABEL
9423 references; so go back to the original address expression. */
9424 rtx new_x
= legitimize_pic_address (orig_x
, mode
, NULL_RTX
, NULL_RTX
,
9425 false /*compute_now*/);
9427 if (new_x
!= orig_x
)
9434 /* Return TRUE if X contains any TLS symbol references. */
9437 arm_tls_referenced_p (rtx x
)
9439 if (! TARGET_HAVE_TLS
)
9442 subrtx_iterator::array_type array
;
9443 FOR_EACH_SUBRTX (iter
, array
, x
, ALL
)
9445 const_rtx x
= *iter
;
9446 if (SYMBOL_REF_P (x
) && SYMBOL_REF_TLS_MODEL (x
) != 0)
9448 /* ARM currently does not provide relocations to encode TLS variables
9449 into AArch32 instructions, only data, so there is no way to
9450 currently implement these if a literal pool is disabled. */
9451 if (arm_disable_literal_pool
)
9452 sorry ("accessing thread-local storage is not currently supported "
9453 "with %<-mpure-code%> or %<-mslow-flash-data%>");
9458 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
9459 TLS offsets, not real symbol references. */
9460 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
9461 iter
.skip_subrtxes ();
9466 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
9468 On the ARM, allow any integer (invalid ones are removed later by insn
9469 patterns), nice doubles and symbol_refs which refer to the function's
9472 When generating pic allow anything. */
9475 arm_legitimate_constant_p_1 (machine_mode
, rtx x
)
9477 if (GET_CODE (x
) == CONST_VECTOR
&& !neon_make_constant (x
, false))
9480 return flag_pic
|| !label_mentioned_p (x
);
9484 thumb_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
9486 /* Splitters for TARGET_USE_MOVT call arm_emit_movpair which creates high
9487 RTX. These RTX must therefore be allowed for Thumb-1 so that when run
9488 for ARMv8-M Baseline or later the result is valid. */
9489 if (TARGET_HAVE_MOVT
&& GET_CODE (x
) == HIGH
)
9492 return (CONST_INT_P (x
)
9493 || CONST_DOUBLE_P (x
)
9494 || CONSTANT_ADDRESS_P (x
)
9495 || (TARGET_HAVE_MOVT
&& SYMBOL_REF_P (x
))
9496 /* On Thumb-1 without MOVT/MOVW and literal pool disabled,
9497 we build the symbol address with upper/lower
9500 && !label_mentioned_p (x
)
9501 && arm_valid_symbolic_address_p (x
)
9502 && arm_disable_literal_pool
)
9507 arm_legitimate_constant_p (machine_mode mode
, rtx x
)
9509 return (!arm_cannot_force_const_mem (mode
, x
)
9511 ? arm_legitimate_constant_p_1 (mode
, x
)
9512 : thumb_legitimate_constant_p (mode
, x
)));
9515 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
9518 arm_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
9521 split_const (x
, &base
, &offset
);
9523 if (SYMBOL_REF_P (base
))
9525 /* Function symbols cannot have an offset due to the Thumb bit. */
9526 if ((SYMBOL_REF_FLAGS (base
) & SYMBOL_FLAG_FUNCTION
)
9527 && INTVAL (offset
) != 0)
9530 if (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
9531 && !offset_within_block_p (base
, INTVAL (offset
)))
9534 return arm_tls_referenced_p (x
);
9537 #define REG_OR_SUBREG_REG(X) \
9539 || (SUBREG_P (X) && REG_P (SUBREG_REG (X))))
9541 #define REG_OR_SUBREG_RTX(X) \
9542 (REG_P (X) ? (X) : SUBREG_REG (X))
9545 thumb1_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
9547 machine_mode mode
= GET_MODE (x
);
9556 return (mode
== SImode
) ? COSTS_N_INSNS (1) : COSTS_N_INSNS (2);
9563 return COSTS_N_INSNS (1);
9566 if (arm_arch6m
&& arm_m_profile_small_mul
)
9567 return COSTS_N_INSNS (32);
9569 if (CONST_INT_P (XEXP (x
, 1)))
9572 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
9579 return COSTS_N_INSNS (2) + cycles
;
9581 return COSTS_N_INSNS (1) + 16;
9584 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
9586 words
= ARM_NUM_INTS (GET_MODE_SIZE (GET_MODE (SET_DEST (x
))));
9587 return (COSTS_N_INSNS (words
)
9588 + 4 * ((MEM_P (SET_SRC (x
)))
9589 + MEM_P (SET_DEST (x
))));
9594 if (UINTVAL (x
) < 256
9595 /* 16-bit constant. */
9596 || (TARGET_HAVE_MOVT
&& !(INTVAL (x
) & 0xffff0000)))
9598 if (thumb_shiftable_const (INTVAL (x
)))
9599 return COSTS_N_INSNS (2);
9600 return arm_disable_literal_pool
9602 : COSTS_N_INSNS (3);
9604 else if ((outer
== PLUS
|| outer
== COMPARE
)
9605 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
9607 else if ((outer
== IOR
|| outer
== XOR
|| outer
== AND
)
9608 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
9609 return COSTS_N_INSNS (1);
9610 else if (outer
== AND
)
9613 /* This duplicates the tests in the andsi3 expander. */
9614 for (i
= 9; i
<= 31; i
++)
9615 if ((HOST_WIDE_INT_1
<< i
) - 1 == INTVAL (x
)
9616 || (HOST_WIDE_INT_1
<< i
) - 1 == ~INTVAL (x
))
9617 return COSTS_N_INSNS (2);
9619 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
9620 || outer
== LSHIFTRT
)
9622 return COSTS_N_INSNS (2);
9628 return COSTS_N_INSNS (3);
9646 /* XXX another guess. */
9647 /* Memory costs quite a lot for the first word, but subsequent words
9648 load at the equivalent of a single insn each. */
9649 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
9650 + ((SYMBOL_REF_P (x
) && CONSTANT_POOL_ADDRESS_P (x
))
9655 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
9661 total
= mode
== DImode
? COSTS_N_INSNS (1) : 0;
9662 total
+= thumb1_rtx_costs (XEXP (x
, 0), GET_CODE (XEXP (x
, 0)), code
);
9668 return total
+ COSTS_N_INSNS (1);
9670 /* Assume a two-shift sequence. Increase the cost slightly so
9671 we prefer actual shifts over an extend operation. */
9672 return total
+ 1 + COSTS_N_INSNS (2);
9679 /* Estimates the size cost of thumb1 instructions.
9680 For now most of the code is copied from thumb1_rtx_costs. We need more
9681 fine grain tuning when we have more related test cases. */
9683 thumb1_size_rtx_costs (rtx x
, enum rtx_code code
, enum rtx_code outer
)
9685 machine_mode mode
= GET_MODE (x
);
9694 return (mode
== SImode
) ? COSTS_N_INSNS (1) : COSTS_N_INSNS (2);
9698 /* Thumb-1 needs two instructions to fulfill shiftadd/shiftsub0/shiftsub1
9699 defined by RTL expansion, especially for the expansion of
9701 if ((GET_CODE (XEXP (x
, 0)) == MULT
9702 && power_of_two_operand (XEXP (XEXP (x
,0),1), SImode
))
9703 || (GET_CODE (XEXP (x
, 1)) == MULT
9704 && power_of_two_operand (XEXP (XEXP (x
, 1), 1), SImode
)))
9705 return COSTS_N_INSNS (2);
9710 return COSTS_N_INSNS (1);
9713 if (CONST_INT_P (XEXP (x
, 1)))
9715 /* Thumb1 mul instruction can't operate on const. We must Load it
9716 into a register first. */
9717 int const_size
= thumb1_size_rtx_costs (XEXP (x
, 1), CONST_INT
, SET
);
9718 /* For the targets which have a very small and high-latency multiply
9719 unit, we prefer to synthesize the mult with up to 5 instructions,
9720 giving a good balance between size and performance. */
9721 if (arm_arch6m
&& arm_m_profile_small_mul
)
9722 return COSTS_N_INSNS (5);
9724 return COSTS_N_INSNS (1) + const_size
;
9726 return COSTS_N_INSNS (1);
9729 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
9731 words
= ARM_NUM_INTS (GET_MODE_SIZE (GET_MODE (SET_DEST (x
))));
9732 cost
= COSTS_N_INSNS (words
);
9733 if (satisfies_constraint_J (SET_SRC (x
))
9734 || satisfies_constraint_K (SET_SRC (x
))
9735 /* Too big an immediate for a 2-byte mov, using MOVT. */
9736 || (CONST_INT_P (SET_SRC (x
))
9737 && UINTVAL (SET_SRC (x
)) >= 256
9739 && satisfies_constraint_j (SET_SRC (x
)))
9740 /* thumb1_movdi_insn. */
9741 || ((words
> 1) && MEM_P (SET_SRC (x
))))
9742 cost
+= COSTS_N_INSNS (1);
9748 if (UINTVAL (x
) < 256)
9749 return COSTS_N_INSNS (1);
9750 /* movw is 4byte long. */
9751 if (TARGET_HAVE_MOVT
&& !(INTVAL (x
) & 0xffff0000))
9752 return COSTS_N_INSNS (2);
9753 /* See split "TARGET_THUMB1 && satisfies_constraint_J". */
9754 if (INTVAL (x
) >= -255 && INTVAL (x
) <= -1)
9755 return COSTS_N_INSNS (2);
9756 /* See split "TARGET_THUMB1 && satisfies_constraint_K". */
9757 if (thumb_shiftable_const (INTVAL (x
)))
9758 return COSTS_N_INSNS (2);
9759 return arm_disable_literal_pool
9761 : COSTS_N_INSNS (3);
9763 else if ((outer
== PLUS
|| outer
== COMPARE
)
9764 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
9766 else if ((outer
== IOR
|| outer
== XOR
|| outer
== AND
)
9767 && INTVAL (x
) < 256 && INTVAL (x
) >= -256)
9768 return COSTS_N_INSNS (1);
9769 else if (outer
== AND
)
9772 /* This duplicates the tests in the andsi3 expander. */
9773 for (i
= 9; i
<= 31; i
++)
9774 if ((HOST_WIDE_INT_1
<< i
) - 1 == INTVAL (x
)
9775 || (HOST_WIDE_INT_1
<< i
) - 1 == ~INTVAL (x
))
9776 return COSTS_N_INSNS (2);
9778 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
9779 || outer
== LSHIFTRT
)
9781 return COSTS_N_INSNS (2);
9787 return COSTS_N_INSNS (3);
9801 return COSTS_N_INSNS (1);
9804 return (COSTS_N_INSNS (1)
9806 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
9807 + ((SYMBOL_REF_P (x
) && CONSTANT_POOL_ADDRESS_P (x
))
9808 ? COSTS_N_INSNS (1) : 0));
9812 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
9817 /* XXX still guessing. */
9818 switch (GET_MODE (XEXP (x
, 0)))
9821 return (1 + (mode
== DImode
? 4 : 0)
9822 + (MEM_P (XEXP (x
, 0)) ? 10 : 0));
9825 return (4 + (mode
== DImode
? 4 : 0)
9826 + (MEM_P (XEXP (x
, 0)) ? 10 : 0));
9829 return (1 + (MEM_P (XEXP (x
, 0)) ? 10 : 0));
9840 /* Helper function for arm_rtx_costs. If one operand of the OP, a
9841 PLUS, adds the carry flag, then return the other operand. If
9842 neither is a carry, return OP unchanged. */
9844 strip_carry_operation (rtx op
)
9846 gcc_assert (GET_CODE (op
) == PLUS
);
9847 if (arm_carry_operation (XEXP (op
, 0), GET_MODE (op
)))
9848 return XEXP (op
, 1);
9849 else if (arm_carry_operation (XEXP (op
, 1), GET_MODE (op
)))
9850 return XEXP (op
, 0);
9854 /* Helper function for arm_rtx_costs. If the operand is a valid shift
9855 operand, then return the operand that is being shifted. If the shift
9856 is not by a constant, then set SHIFT_REG to point to the operand.
9857 Return NULL if OP is not a shifter operand. */
9859 shifter_op_p (rtx op
, rtx
*shift_reg
)
9861 enum rtx_code code
= GET_CODE (op
);
9863 if (code
== MULT
&& CONST_INT_P (XEXP (op
, 1))
9864 && exact_log2 (INTVAL (XEXP (op
, 1))) > 0)
9865 return XEXP (op
, 0);
9866 else if (code
== ROTATE
&& CONST_INT_P (XEXP (op
, 1)))
9867 return XEXP (op
, 0);
9868 else if (code
== ROTATERT
|| code
== ASHIFT
|| code
== LSHIFTRT
9869 || code
== ASHIFTRT
)
9871 if (!CONST_INT_P (XEXP (op
, 1)))
9872 *shift_reg
= XEXP (op
, 1);
9873 return XEXP (op
, 0);
9880 arm_unspec_cost (rtx x
, enum rtx_code
/* outer_code */, bool speed_p
, int *cost
)
9882 const struct cpu_cost_table
*extra_cost
= current_tune
->insn_extra_cost
;
9883 rtx_code code
= GET_CODE (x
);
9884 gcc_assert (code
== UNSPEC
|| code
== UNSPEC_VOLATILE
);
9886 switch (XINT (x
, 1))
9888 case UNSPEC_UNALIGNED_LOAD
:
9889 /* We can only do unaligned loads into the integer unit, and we can't
9891 *cost
= COSTS_N_INSNS (ARM_NUM_REGS (GET_MODE (x
)));
9893 *cost
+= (ARM_NUM_REGS (GET_MODE (x
)) * extra_cost
->ldst
.load
9894 + extra_cost
->ldst
.load_unaligned
);
9897 *cost
+= arm_address_cost (XEXP (XVECEXP (x
, 0, 0), 0), GET_MODE (x
),
9898 ADDR_SPACE_GENERIC
, speed_p
);
9902 case UNSPEC_UNALIGNED_STORE
:
9903 *cost
= COSTS_N_INSNS (ARM_NUM_REGS (GET_MODE (x
)));
9905 *cost
+= (ARM_NUM_REGS (GET_MODE (x
)) * extra_cost
->ldst
.store
9906 + extra_cost
->ldst
.store_unaligned
);
9908 *cost
+= rtx_cost (XVECEXP (x
, 0, 0), VOIDmode
, UNSPEC
, 0, speed_p
);
9910 *cost
+= arm_address_cost (XEXP (XVECEXP (x
, 0, 0), 0), GET_MODE (x
),
9911 ADDR_SPACE_GENERIC
, speed_p
);
9922 *cost
+= extra_cost
->fp
[GET_MODE (x
) == DFmode
].roundint
;
9926 *cost
= COSTS_N_INSNS (2);
9932 /* Cost of a libcall. We assume one insn per argument, an amount for the
9933 call (one insn for -Os) and then one for processing the result. */
9934 #define LIBCALL_COST(N) COSTS_N_INSNS (N + (speed_p ? 18 : 2))
9936 #define HANDLE_NARROW_SHIFT_ARITH(OP, IDX) \
9939 shift_op = shifter_op_p (XEXP (x, IDX), &shift_reg); \
9940 if (shift_op != NULL \
9941 && arm_rtx_shift_left_p (XEXP (x, IDX))) \
9946 *cost += extra_cost->alu.arith_shift_reg; \
9947 *cost += rtx_cost (shift_reg, GET_MODE (shift_reg), \
9948 ASHIFT, 1, speed_p); \
9951 *cost += extra_cost->alu.arith_shift; \
9953 *cost += (rtx_cost (shift_op, GET_MODE (shift_op), \
9954 ASHIFT, 0, speed_p) \
9955 + rtx_cost (XEXP (x, 1 - IDX), \
9956 GET_MODE (shift_op), \
9963 /* Helper function for arm_rtx_costs_internal. Calculates the cost of a MEM,
9964 considering the costs of the addressing mode and memory access
9967 arm_mem_costs (rtx x
, const struct cpu_cost_table
*extra_cost
,
9968 int *cost
, bool speed_p
)
9970 machine_mode mode
= GET_MODE (x
);
9972 *cost
= COSTS_N_INSNS (1);
9975 && GET_CODE (XEXP (x
, 0)) == PLUS
9976 && will_be_in_index_register (XEXP (XEXP (x
, 0), 1)))
9977 /* This will be split into two instructions. Add the cost of the
9978 additional instruction here. The cost of the memory access is computed
9979 below. See arm.md:calculate_pic_address. */
9980 *cost
+= COSTS_N_INSNS (1);
9982 /* Calculate cost of the addressing mode. */
9985 arm_addr_mode_op op_type
;
9986 switch (GET_CODE (XEXP (x
, 0)))
9990 op_type
= AMO_DEFAULT
;
9993 /* MINUS does not appear in RTL, but the architecture supports it,
9994 so handle this case defensively. */
9997 op_type
= AMO_NO_WB
;
10009 if (VECTOR_MODE_P (mode
))
10010 *cost
+= current_tune
->addr_mode_costs
->vector
[op_type
];
10011 else if (FLOAT_MODE_P (mode
))
10012 *cost
+= current_tune
->addr_mode_costs
->fp
[op_type
];
10014 *cost
+= current_tune
->addr_mode_costs
->integer
[op_type
];
10017 /* Calculate cost of memory access. */
10020 if (FLOAT_MODE_P (mode
))
10022 if (GET_MODE_SIZE (mode
) == 8)
10023 *cost
+= extra_cost
->ldst
.loadd
;
10025 *cost
+= extra_cost
->ldst
.loadf
;
10027 else if (VECTOR_MODE_P (mode
))
10028 *cost
+= extra_cost
->ldst
.loadv
;
10031 /* Integer modes */
10032 if (GET_MODE_SIZE (mode
) == 8)
10033 *cost
+= extra_cost
->ldst
.ldrd
;
10035 *cost
+= extra_cost
->ldst
.load
;
10042 /* RTX costs. Make an estimate of the cost of executing the operation
10043 X, which is contained within an operation with code OUTER_CODE.
10044 SPEED_P indicates whether the cost desired is the performance cost,
10045 or the size cost. The estimate is stored in COST and the return
10046 value is TRUE if the cost calculation is final, or FALSE if the
10047 caller should recurse through the operands of X to add additional
10050 We currently make no attempt to model the size savings of Thumb-2
10051 16-bit instructions. At the normal points in compilation where
10052 this code is called we have no measure of whether the condition
10053 flags are live or not, and thus no realistic way to determine what
10054 the size will eventually be. */
10056 arm_rtx_costs_internal (rtx x
, enum rtx_code code
, enum rtx_code outer_code
,
10057 const struct cpu_cost_table
*extra_cost
,
10058 int *cost
, bool speed_p
)
10060 machine_mode mode
= GET_MODE (x
);
10062 *cost
= COSTS_N_INSNS (1);
10067 *cost
= thumb1_rtx_costs (x
, code
, outer_code
);
10069 *cost
= thumb1_size_rtx_costs (x
, code
, outer_code
);
10077 /* SET RTXs don't have a mode so we get it from the destination. */
10078 mode
= GET_MODE (SET_DEST (x
));
10080 if (REG_P (SET_SRC (x
))
10081 && REG_P (SET_DEST (x
)))
10083 /* Assume that most copies can be done with a single insn,
10084 unless we don't have HW FP, in which case everything
10085 larger than word mode will require two insns. */
10086 *cost
= COSTS_N_INSNS (((!TARGET_VFP_BASE
10087 && GET_MODE_SIZE (mode
) > 4)
10090 /* Conditional register moves can be encoded
10091 in 16 bits in Thumb mode. */
10092 if (!speed_p
&& TARGET_THUMB
&& outer_code
== COND_EXEC
)
10098 if (CONST_INT_P (SET_SRC (x
)))
10100 /* Handle CONST_INT here, since the value doesn't have a mode
10101 and we would otherwise be unable to work out the true cost. */
10102 *cost
= rtx_cost (SET_DEST (x
), GET_MODE (SET_DEST (x
)), SET
,
10105 /* Slightly lower the cost of setting a core reg to a constant.
10106 This helps break up chains and allows for better scheduling. */
10107 if (REG_P (SET_DEST (x
))
10108 && REGNO (SET_DEST (x
)) <= LR_REGNUM
)
10111 /* Immediate moves with an immediate in the range [0, 255] can be
10112 encoded in 16 bits in Thumb mode. */
10113 if (!speed_p
&& TARGET_THUMB
&& GET_MODE (x
) == SImode
10114 && INTVAL (x
) >= 0 && INTVAL (x
) <=255)
10116 goto const_int_cost
;
10122 return arm_mem_costs (x
, extra_cost
, cost
, speed_p
);
10126 /* Calculations of LDM costs are complex. We assume an initial cost
10127 (ldm_1st) which will load the number of registers mentioned in
10128 ldm_regs_per_insn_1st registers; then each additional
10129 ldm_regs_per_insn_subsequent registers cost one more insn. The
10130 formula for N regs is thus:
10132 ldm_1st + COSTS_N_INSNS ((max (N - ldm_regs_per_insn_1st, 0)
10133 + ldm_regs_per_insn_subsequent - 1)
10134 / ldm_regs_per_insn_subsequent).
10136 Additional costs may also be added for addressing. A similar
10137 formula is used for STM. */
10139 bool is_ldm
= load_multiple_operation (x
, SImode
);
10140 bool is_stm
= store_multiple_operation (x
, SImode
);
10142 if (is_ldm
|| is_stm
)
10146 HOST_WIDE_INT nregs
= XVECLEN (x
, 0);
10147 HOST_WIDE_INT regs_per_insn_1st
= is_ldm
10148 ? extra_cost
->ldst
.ldm_regs_per_insn_1st
10149 : extra_cost
->ldst
.stm_regs_per_insn_1st
;
10150 HOST_WIDE_INT regs_per_insn_sub
= is_ldm
10151 ? extra_cost
->ldst
.ldm_regs_per_insn_subsequent
10152 : extra_cost
->ldst
.stm_regs_per_insn_subsequent
;
10154 *cost
+= regs_per_insn_1st
10155 + COSTS_N_INSNS (((MAX (nregs
- regs_per_insn_1st
, 0))
10156 + regs_per_insn_sub
- 1)
10157 / regs_per_insn_sub
);
10166 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
10167 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
10168 *cost
+= COSTS_N_INSNS (speed_p
10169 ? extra_cost
->fp
[mode
!= SFmode
].div
: 0);
10170 else if (mode
== SImode
&& TARGET_IDIV
)
10171 *cost
+= COSTS_N_INSNS (speed_p
? extra_cost
->mult
[0].idiv
: 0);
10173 *cost
= LIBCALL_COST (2);
10175 /* Make the cost of sdiv more expensive so when both sdiv and udiv are
10176 possible udiv is prefered. */
10177 *cost
+= (code
== DIV
? COSTS_N_INSNS (1) : 0);
10178 return false; /* All arguments must be in registers. */
10181 /* MOD by a power of 2 can be expanded as:
10183 and r0, r0, #(n - 1)
10184 and r1, r1, #(n - 1)
10185 rsbpl r0, r1, #0. */
10186 if (CONST_INT_P (XEXP (x
, 1))
10187 && exact_log2 (INTVAL (XEXP (x
, 1))) > 0
10190 *cost
+= COSTS_N_INSNS (3);
10193 *cost
+= 2 * extra_cost
->alu
.logical
10194 + extra_cost
->alu
.arith
;
10198 /* Fall-through. */
10200 /* Make the cost of sdiv more expensive so when both sdiv and udiv are
10201 possible udiv is prefered. */
10202 *cost
= LIBCALL_COST (2) + (code
== MOD
? COSTS_N_INSNS (1) : 0);
10203 return false; /* All arguments must be in registers. */
10206 if (mode
== SImode
&& REG_P (XEXP (x
, 1)))
10208 *cost
+= (COSTS_N_INSNS (1)
10209 + rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed_p
));
10211 *cost
+= extra_cost
->alu
.shift_reg
;
10219 if (mode
== DImode
&& CONST_INT_P (XEXP (x
, 1)))
10221 *cost
+= (COSTS_N_INSNS (2)
10222 + rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed_p
));
10224 *cost
+= 2 * extra_cost
->alu
.shift
;
10225 /* Slightly disparage left shift by 1 at so we prefer adddi3. */
10226 if (code
== ASHIFT
&& XEXP (x
, 1) == CONST1_RTX (SImode
))
10230 else if (mode
== SImode
)
10232 *cost
+= rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed_p
);
10233 /* Slightly disparage register shifts at -Os, but not by much. */
10234 if (!CONST_INT_P (XEXP (x
, 1)))
10235 *cost
+= (speed_p
? extra_cost
->alu
.shift_reg
: 1
10236 + rtx_cost (XEXP (x
, 1), mode
, code
, 1, speed_p
));
10239 else if (GET_MODE_CLASS (mode
) == MODE_INT
10240 && GET_MODE_SIZE (mode
) < 4)
10242 if (code
== ASHIFT
)
10244 *cost
+= rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed_p
);
10245 /* Slightly disparage register shifts at -Os, but not by
10247 if (!CONST_INT_P (XEXP (x
, 1)))
10248 *cost
+= (speed_p
? extra_cost
->alu
.shift_reg
: 1
10249 + rtx_cost (XEXP (x
, 1), mode
, code
, 1, speed_p
));
10251 else if (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10253 if (arm_arch_thumb2
&& CONST_INT_P (XEXP (x
, 1)))
10255 /* Can use SBFX/UBFX. */
10257 *cost
+= extra_cost
->alu
.bfx
;
10258 *cost
+= rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed_p
);
10262 *cost
+= COSTS_N_INSNS (1);
10263 *cost
+= rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed_p
);
10266 if (CONST_INT_P (XEXP (x
, 1)))
10267 *cost
+= 2 * extra_cost
->alu
.shift
;
10269 *cost
+= (extra_cost
->alu
.shift
10270 + extra_cost
->alu
.shift_reg
);
10273 /* Slightly disparage register shifts. */
10274 *cost
+= !CONST_INT_P (XEXP (x
, 1));
10277 else /* Rotates. */
10279 *cost
= COSTS_N_INSNS (2 + !CONST_INT_P (XEXP (x
, 1)));
10280 *cost
+= rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed_p
);
10283 if (CONST_INT_P (XEXP (x
, 1)))
10284 *cost
+= (2 * extra_cost
->alu
.shift
10285 + extra_cost
->alu
.log_shift
);
10287 *cost
+= (extra_cost
->alu
.shift
10288 + extra_cost
->alu
.shift_reg
10289 + extra_cost
->alu
.log_shift_reg
);
10295 *cost
= LIBCALL_COST (2);
10301 if (mode
== SImode
)
10304 *cost
+= extra_cost
->alu
.rev
;
10311 /* No rev instruction available. Look at arm_legacy_rev
10312 and thumb_legacy_rev for the form of RTL used then. */
10315 *cost
+= COSTS_N_INSNS (9);
10319 *cost
+= 6 * extra_cost
->alu
.shift
;
10320 *cost
+= 3 * extra_cost
->alu
.logical
;
10325 *cost
+= COSTS_N_INSNS (4);
10329 *cost
+= 2 * extra_cost
->alu
.shift
;
10330 *cost
+= extra_cost
->alu
.arith_shift
;
10331 *cost
+= 2 * extra_cost
->alu
.logical
;
10339 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
10340 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
10342 if (GET_CODE (XEXP (x
, 0)) == MULT
10343 || GET_CODE (XEXP (x
, 1)) == MULT
)
10345 rtx mul_op0
, mul_op1
, sub_op
;
10348 *cost
+= extra_cost
->fp
[mode
!= SFmode
].mult_addsub
;
10350 if (GET_CODE (XEXP (x
, 0)) == MULT
)
10352 mul_op0
= XEXP (XEXP (x
, 0), 0);
10353 mul_op1
= XEXP (XEXP (x
, 0), 1);
10354 sub_op
= XEXP (x
, 1);
10358 mul_op0
= XEXP (XEXP (x
, 1), 0);
10359 mul_op1
= XEXP (XEXP (x
, 1), 1);
10360 sub_op
= XEXP (x
, 0);
10363 /* The first operand of the multiply may be optionally
10365 if (GET_CODE (mul_op0
) == NEG
)
10366 mul_op0
= XEXP (mul_op0
, 0);
10368 *cost
+= (rtx_cost (mul_op0
, mode
, code
, 0, speed_p
)
10369 + rtx_cost (mul_op1
, mode
, code
, 0, speed_p
)
10370 + rtx_cost (sub_op
, mode
, code
, 0, speed_p
));
10376 *cost
+= extra_cost
->fp
[mode
!= SFmode
].addsub
;
10380 if (mode
== SImode
)
10382 rtx shift_by_reg
= NULL
;
10385 rtx op0
= XEXP (x
, 0);
10386 rtx op1
= XEXP (x
, 1);
10388 /* Factor out any borrow operation. There's more than one way
10389 of expressing this; try to recognize them all. */
10390 if (GET_CODE (op0
) == MINUS
)
10392 if (arm_borrow_operation (op1
, SImode
))
10394 op1
= XEXP (op0
, 1);
10395 op0
= XEXP (op0
, 0);
10397 else if (arm_borrow_operation (XEXP (op0
, 1), SImode
))
10398 op0
= XEXP (op0
, 0);
10400 else if (GET_CODE (op1
) == PLUS
10401 && arm_borrow_operation (XEXP (op1
, 0), SImode
))
10402 op1
= XEXP (op1
, 0);
10403 else if (GET_CODE (op0
) == NEG
10404 && arm_borrow_operation (op1
, SImode
))
10406 /* Negate with carry-in. For Thumb2 this is done with
10407 SBC R, X, X lsl #1 (ie X - 2X - C) as Thumb lacks the
10408 RSC instruction that exists in Arm mode. */
10410 *cost
+= (TARGET_THUMB2
10411 ? extra_cost
->alu
.arith_shift
10412 : extra_cost
->alu
.arith
);
10413 *cost
+= rtx_cost (XEXP (op0
, 0), mode
, MINUS
, 0, speed_p
);
10416 /* (Carry_op - reg) can be done as RSC Rd, Rn, #1 on Arm.
10417 Note we do mean ~borrow here. */
10418 else if (TARGET_ARM
&& arm_carry_operation (op0
, SImode
))
10420 *cost
+= rtx_cost (op1
, mode
, code
, 1, speed_p
);
10424 shift_op
= shifter_op_p (op0
, &shift_by_reg
);
10425 if (shift_op
== NULL
)
10427 shift_op
= shifter_op_p (op1
, &shift_by_reg
);
10428 non_shift_op
= op0
;
10431 non_shift_op
= op1
;
10433 if (shift_op
!= NULL
)
10435 if (shift_by_reg
!= NULL
)
10438 *cost
+= extra_cost
->alu
.arith_shift_reg
;
10439 *cost
+= rtx_cost (shift_by_reg
, mode
, code
, 0, speed_p
);
10442 *cost
+= extra_cost
->alu
.arith_shift
;
10444 *cost
+= rtx_cost (shift_op
, mode
, code
, 0, speed_p
);
10445 *cost
+= rtx_cost (non_shift_op
, mode
, code
, 0, speed_p
);
10449 if (arm_arch_thumb2
10450 && GET_CODE (XEXP (x
, 1)) == MULT
)
10454 *cost
+= extra_cost
->mult
[0].add
;
10455 *cost
+= rtx_cost (XEXP (x
, 0), mode
, MINUS
, 0, speed_p
);
10456 *cost
+= rtx_cost (XEXP (XEXP (x
, 1), 0), mode
, MULT
, 0, speed_p
);
10457 *cost
+= rtx_cost (XEXP (XEXP (x
, 1), 1), mode
, MULT
, 1, speed_p
);
10461 if (CONST_INT_P (op0
))
10463 int insns
= arm_gen_constant (MINUS
, SImode
, NULL_RTX
,
10464 INTVAL (op0
), NULL_RTX
,
10466 *cost
= COSTS_N_INSNS (insns
);
10468 *cost
+= insns
* extra_cost
->alu
.arith
;
10469 *cost
+= rtx_cost (XEXP (x
, 1), mode
, code
, 1, speed_p
);
10473 *cost
+= extra_cost
->alu
.arith
;
10475 /* Don't recurse as we don't want to cost any borrow that
10477 *cost
+= rtx_cost (op0
, mode
, MINUS
, 0, speed_p
);
10478 *cost
+= rtx_cost (op1
, mode
, MINUS
, 1, speed_p
);
10482 if (GET_MODE_CLASS (mode
) == MODE_INT
10483 && GET_MODE_SIZE (mode
) < 4)
10485 rtx shift_op
, shift_reg
;
10488 /* We check both sides of the MINUS for shifter operands since,
10489 unlike PLUS, it's not commutative. */
10491 HANDLE_NARROW_SHIFT_ARITH (MINUS
, 0);
10492 HANDLE_NARROW_SHIFT_ARITH (MINUS
, 1);
10494 /* Slightly disparage, as we might need to widen the result. */
10497 *cost
+= extra_cost
->alu
.arith
;
10499 if (CONST_INT_P (XEXP (x
, 0)))
10501 *cost
+= rtx_cost (XEXP (x
, 1), mode
, code
, 1, speed_p
);
10508 if (mode
== DImode
)
10510 *cost
+= COSTS_N_INSNS (1);
10512 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
10514 rtx op1
= XEXP (x
, 1);
10517 *cost
+= 2 * extra_cost
->alu
.arith
;
10519 if (GET_CODE (op1
) == ZERO_EXTEND
)
10520 *cost
+= rtx_cost (XEXP (op1
, 0), VOIDmode
, ZERO_EXTEND
,
10523 *cost
+= rtx_cost (op1
, mode
, MINUS
, 1, speed_p
);
10524 *cost
+= rtx_cost (XEXP (XEXP (x
, 0), 0), VOIDmode
, ZERO_EXTEND
,
10528 else if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
10531 *cost
+= extra_cost
->alu
.arith
+ extra_cost
->alu
.arith_shift
;
10532 *cost
+= (rtx_cost (XEXP (XEXP (x
, 0), 0), VOIDmode
, SIGN_EXTEND
,
10534 + rtx_cost (XEXP (x
, 1), mode
, MINUS
, 1, speed_p
));
10537 else if (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
10538 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
10541 *cost
+= (extra_cost
->alu
.arith
10542 + (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
10543 ? extra_cost
->alu
.arith
10544 : extra_cost
->alu
.arith_shift
));
10545 *cost
+= (rtx_cost (XEXP (x
, 0), mode
, MINUS
, 0, speed_p
)
10546 + rtx_cost (XEXP (XEXP (x
, 1), 0), VOIDmode
,
10547 GET_CODE (XEXP (x
, 1)), 0, speed_p
));
10552 *cost
+= 2 * extra_cost
->alu
.arith
;
10558 *cost
= LIBCALL_COST (2);
10562 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
10563 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
10565 if (GET_CODE (XEXP (x
, 0)) == MULT
)
10567 rtx mul_op0
, mul_op1
, add_op
;
10570 *cost
+= extra_cost
->fp
[mode
!= SFmode
].mult_addsub
;
10572 mul_op0
= XEXP (XEXP (x
, 0), 0);
10573 mul_op1
= XEXP (XEXP (x
, 0), 1);
10574 add_op
= XEXP (x
, 1);
10576 *cost
+= (rtx_cost (mul_op0
, mode
, code
, 0, speed_p
)
10577 + rtx_cost (mul_op1
, mode
, code
, 0, speed_p
)
10578 + rtx_cost (add_op
, mode
, code
, 0, speed_p
));
10584 *cost
+= extra_cost
->fp
[mode
!= SFmode
].addsub
;
10587 else if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
10589 *cost
= LIBCALL_COST (2);
10593 /* Narrow modes can be synthesized in SImode, but the range
10594 of useful sub-operations is limited. Check for shift operations
10595 on one of the operands. Only left shifts can be used in the
10597 if (GET_MODE_CLASS (mode
) == MODE_INT
10598 && GET_MODE_SIZE (mode
) < 4)
10600 rtx shift_op
, shift_reg
;
10603 HANDLE_NARROW_SHIFT_ARITH (PLUS
, 0);
10605 if (CONST_INT_P (XEXP (x
, 1)))
10607 int insns
= arm_gen_constant (PLUS
, SImode
, NULL_RTX
,
10608 INTVAL (XEXP (x
, 1)), NULL_RTX
,
10610 *cost
= COSTS_N_INSNS (insns
);
10612 *cost
+= insns
* extra_cost
->alu
.arith
;
10613 /* Slightly penalize a narrow operation as the result may
10615 *cost
+= 1 + rtx_cost (XEXP (x
, 0), mode
, PLUS
, 0, speed_p
);
10619 /* Slightly penalize a narrow operation as the result may
10623 *cost
+= extra_cost
->alu
.arith
;
10628 if (mode
== SImode
)
10630 rtx shift_op
, shift_reg
;
10632 if (TARGET_INT_SIMD
10633 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
10634 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
10636 /* UXTA[BH] or SXTA[BH]. */
10638 *cost
+= extra_cost
->alu
.extend_arith
;
10639 *cost
+= (rtx_cost (XEXP (XEXP (x
, 0), 0), VOIDmode
, ZERO_EXTEND
,
10641 + rtx_cost (XEXP (x
, 1), mode
, PLUS
, 0, speed_p
));
10645 rtx op0
= XEXP (x
, 0);
10646 rtx op1
= XEXP (x
, 1);
10648 /* Handle a side effect of adding in the carry to an addition. */
10649 if (GET_CODE (op0
) == PLUS
10650 && arm_carry_operation (op1
, mode
))
10652 op1
= XEXP (op0
, 1);
10653 op0
= XEXP (op0
, 0);
10655 else if (GET_CODE (op1
) == PLUS
10656 && arm_carry_operation (op0
, mode
))
10658 op0
= XEXP (op1
, 0);
10659 op1
= XEXP (op1
, 1);
10661 else if (GET_CODE (op0
) == PLUS
)
10663 op0
= strip_carry_operation (op0
);
10664 if (swap_commutative_operands_p (op0
, op1
))
10665 std::swap (op0
, op1
);
10668 if (arm_carry_operation (op0
, mode
))
10670 /* Adding the carry to a register is a canonicalization of
10671 adding 0 to the register plus the carry. */
10673 *cost
+= extra_cost
->alu
.arith
;
10674 *cost
+= rtx_cost (op1
, mode
, PLUS
, 1, speed_p
);
10679 shift_op
= shifter_op_p (op0
, &shift_reg
);
10680 if (shift_op
!= NULL
)
10685 *cost
+= extra_cost
->alu
.arith_shift_reg
;
10686 *cost
+= rtx_cost (shift_reg
, mode
, ASHIFT
, 1, speed_p
);
10689 *cost
+= extra_cost
->alu
.arith_shift
;
10691 *cost
+= (rtx_cost (shift_op
, mode
, ASHIFT
, 0, speed_p
)
10692 + rtx_cost (op1
, mode
, PLUS
, 1, speed_p
));
10696 if (GET_CODE (op0
) == MULT
)
10700 if (TARGET_DSP_MULTIPLY
10701 && ((GET_CODE (XEXP (mul_op
, 0)) == SIGN_EXTEND
10702 && (GET_CODE (XEXP (mul_op
, 1)) == SIGN_EXTEND
10703 || (GET_CODE (XEXP (mul_op
, 1)) == ASHIFTRT
10704 && CONST_INT_P (XEXP (XEXP (mul_op
, 1), 1))
10705 && INTVAL (XEXP (XEXP (mul_op
, 1), 1)) == 16)))
10706 || (GET_CODE (XEXP (mul_op
, 0)) == ASHIFTRT
10707 && CONST_INT_P (XEXP (XEXP (mul_op
, 0), 1))
10708 && INTVAL (XEXP (XEXP (mul_op
, 0), 1)) == 16
10709 && (GET_CODE (XEXP (mul_op
, 1)) == SIGN_EXTEND
10710 || (GET_CODE (XEXP (mul_op
, 1)) == ASHIFTRT
10711 && CONST_INT_P (XEXP (XEXP (mul_op
, 1), 1))
10712 && (INTVAL (XEXP (XEXP (mul_op
, 1), 1))
10715 /* SMLA[BT][BT]. */
10717 *cost
+= extra_cost
->mult
[0].extend_add
;
10718 *cost
+= (rtx_cost (XEXP (XEXP (mul_op
, 0), 0), mode
,
10719 SIGN_EXTEND
, 0, speed_p
)
10720 + rtx_cost (XEXP (XEXP (mul_op
, 1), 0), mode
,
10721 SIGN_EXTEND
, 0, speed_p
)
10722 + rtx_cost (op1
, mode
, PLUS
, 1, speed_p
));
10727 *cost
+= extra_cost
->mult
[0].add
;
10728 *cost
+= (rtx_cost (XEXP (mul_op
, 0), mode
, MULT
, 0, speed_p
)
10729 + rtx_cost (XEXP (mul_op
, 1), mode
, MULT
, 1, speed_p
)
10730 + rtx_cost (op1
, mode
, PLUS
, 1, speed_p
));
10734 if (CONST_INT_P (op1
))
10736 int insns
= arm_gen_constant (PLUS
, SImode
, NULL_RTX
,
10737 INTVAL (op1
), NULL_RTX
,
10739 *cost
= COSTS_N_INSNS (insns
);
10741 *cost
+= insns
* extra_cost
->alu
.arith
;
10742 *cost
+= rtx_cost (op0
, mode
, PLUS
, 0, speed_p
);
10747 *cost
+= extra_cost
->alu
.arith
;
10749 /* Don't recurse here because we want to test the operands
10750 without any carry operation. */
10751 *cost
+= rtx_cost (op0
, mode
, PLUS
, 0, speed_p
);
10752 *cost
+= rtx_cost (op1
, mode
, PLUS
, 1, speed_p
);
10756 if (mode
== DImode
)
10758 if (GET_CODE (XEXP (x
, 0)) == MULT
10759 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
10760 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == ZERO_EXTEND
)
10761 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
10762 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == SIGN_EXTEND
)))
10765 *cost
+= extra_cost
->mult
[1].extend_add
;
10766 *cost
+= (rtx_cost (XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
,
10767 ZERO_EXTEND
, 0, speed_p
)
10768 + rtx_cost (XEXP (XEXP (XEXP (x
, 0), 1), 0), mode
,
10769 ZERO_EXTEND
, 0, speed_p
)
10770 + rtx_cost (XEXP (x
, 1), mode
, PLUS
, 1, speed_p
));
10774 *cost
+= COSTS_N_INSNS (1);
10776 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
10777 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
10780 *cost
+= (extra_cost
->alu
.arith
10781 + (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
10782 ? extra_cost
->alu
.arith
10783 : extra_cost
->alu
.arith_shift
));
10785 *cost
+= (rtx_cost (XEXP (XEXP (x
, 0), 0), VOIDmode
, ZERO_EXTEND
,
10787 + rtx_cost (XEXP (x
, 1), mode
, PLUS
, 1, speed_p
));
10792 *cost
+= 2 * extra_cost
->alu
.arith
;
10797 *cost
= LIBCALL_COST (2);
10800 if (mode
== SImode
&& arm_arch6
&& aarch_rev16_p (x
))
10803 *cost
+= extra_cost
->alu
.rev
;
10807 /* Fall through. */
10808 case AND
: case XOR
:
10809 if (mode
== SImode
)
10811 enum rtx_code subcode
= GET_CODE (XEXP (x
, 0));
10812 rtx op0
= XEXP (x
, 0);
10813 rtx shift_op
, shift_reg
;
10817 || (code
== IOR
&& TARGET_THUMB2
)))
10818 op0
= XEXP (op0
, 0);
10821 shift_op
= shifter_op_p (op0
, &shift_reg
);
10822 if (shift_op
!= NULL
)
10827 *cost
+= extra_cost
->alu
.log_shift_reg
;
10828 *cost
+= rtx_cost (shift_reg
, mode
, ASHIFT
, 1, speed_p
);
10831 *cost
+= extra_cost
->alu
.log_shift
;
10833 *cost
+= (rtx_cost (shift_op
, mode
, ASHIFT
, 0, speed_p
)
10834 + rtx_cost (XEXP (x
, 1), mode
, code
, 1, speed_p
));
10838 if (CONST_INT_P (XEXP (x
, 1)))
10840 int insns
= arm_gen_constant (code
, SImode
, NULL_RTX
,
10841 INTVAL (XEXP (x
, 1)), NULL_RTX
,
10844 *cost
= COSTS_N_INSNS (insns
);
10846 *cost
+= insns
* extra_cost
->alu
.logical
;
10847 *cost
+= rtx_cost (op0
, mode
, code
, 0, speed_p
);
10852 *cost
+= extra_cost
->alu
.logical
;
10853 *cost
+= (rtx_cost (op0
, mode
, code
, 0, speed_p
)
10854 + rtx_cost (XEXP (x
, 1), mode
, code
, 1, speed_p
));
10858 if (mode
== DImode
)
10860 rtx op0
= XEXP (x
, 0);
10861 enum rtx_code subcode
= GET_CODE (op0
);
10863 *cost
+= COSTS_N_INSNS (1);
10867 || (code
== IOR
&& TARGET_THUMB2
)))
10868 op0
= XEXP (op0
, 0);
10870 if (GET_CODE (op0
) == ZERO_EXTEND
)
10873 *cost
+= 2 * extra_cost
->alu
.logical
;
10875 *cost
+= (rtx_cost (XEXP (op0
, 0), VOIDmode
, ZERO_EXTEND
,
10877 + rtx_cost (XEXP (x
, 1), mode
, code
, 0, speed_p
));
10880 else if (GET_CODE (op0
) == SIGN_EXTEND
)
10883 *cost
+= extra_cost
->alu
.logical
+ extra_cost
->alu
.log_shift
;
10885 *cost
+= (rtx_cost (XEXP (op0
, 0), VOIDmode
, SIGN_EXTEND
,
10887 + rtx_cost (XEXP (x
, 1), mode
, code
, 0, speed_p
));
10892 *cost
+= 2 * extra_cost
->alu
.logical
;
10898 *cost
= LIBCALL_COST (2);
10902 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
10903 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
10905 rtx op0
= XEXP (x
, 0);
10907 if (GET_CODE (op0
) == NEG
&& !flag_rounding_math
)
10908 op0
= XEXP (op0
, 0);
10911 *cost
+= extra_cost
->fp
[mode
!= SFmode
].mult
;
10913 *cost
+= (rtx_cost (op0
, mode
, MULT
, 0, speed_p
)
10914 + rtx_cost (XEXP (x
, 1), mode
, MULT
, 1, speed_p
));
10917 else if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
10919 *cost
= LIBCALL_COST (2);
10923 if (mode
== SImode
)
10925 if (TARGET_DSP_MULTIPLY
10926 && ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
10927 && (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
10928 || (GET_CODE (XEXP (x
, 1)) == ASHIFTRT
10929 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
10930 && INTVAL (XEXP (XEXP (x
, 1), 1)) == 16)))
10931 || (GET_CODE (XEXP (x
, 0)) == ASHIFTRT
10932 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
10933 && INTVAL (XEXP (XEXP (x
, 0), 1)) == 16
10934 && (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
10935 || (GET_CODE (XEXP (x
, 1)) == ASHIFTRT
10936 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
10937 && (INTVAL (XEXP (XEXP (x
, 1), 1))
10940 /* SMUL[TB][TB]. */
10942 *cost
+= extra_cost
->mult
[0].extend
;
10943 *cost
+= rtx_cost (XEXP (XEXP (x
, 0), 0), mode
,
10944 SIGN_EXTEND
, 0, speed_p
);
10945 *cost
+= rtx_cost (XEXP (XEXP (x
, 1), 0), mode
,
10946 SIGN_EXTEND
, 1, speed_p
);
10950 *cost
+= extra_cost
->mult
[0].simple
;
10954 if (mode
== DImode
)
10956 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
10957 && GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
)
10958 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
10959 && GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
))
10962 *cost
+= extra_cost
->mult
[1].extend
;
10963 *cost
+= (rtx_cost (XEXP (XEXP (x
, 0), 0), VOIDmode
,
10964 ZERO_EXTEND
, 0, speed_p
)
10965 + rtx_cost (XEXP (XEXP (x
, 1), 0), VOIDmode
,
10966 ZERO_EXTEND
, 0, speed_p
));
10970 *cost
= LIBCALL_COST (2);
10975 *cost
= LIBCALL_COST (2);
10979 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
10980 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
10982 if (GET_CODE (XEXP (x
, 0)) == MULT
)
10985 *cost
= rtx_cost (XEXP (x
, 0), mode
, NEG
, 0, speed_p
);
10990 *cost
+= extra_cost
->fp
[mode
!= SFmode
].neg
;
10994 else if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
10996 *cost
= LIBCALL_COST (1);
11000 if (mode
== SImode
)
11002 if (GET_CODE (XEXP (x
, 0)) == ABS
)
11004 *cost
+= COSTS_N_INSNS (1);
11005 /* Assume the non-flag-changing variant. */
11007 *cost
+= (extra_cost
->alu
.log_shift
11008 + extra_cost
->alu
.arith_shift
);
11009 *cost
+= rtx_cost (XEXP (XEXP (x
, 0), 0), mode
, ABS
, 0, speed_p
);
11013 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == RTX_COMPARE
11014 || GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == RTX_COMM_COMPARE
)
11016 *cost
+= COSTS_N_INSNS (1);
11017 /* No extra cost for MOV imm and MVN imm. */
11018 /* If the comparison op is using the flags, there's no further
11019 cost, otherwise we need to add the cost of the comparison. */
11020 if (!(REG_P (XEXP (XEXP (x
, 0), 0))
11021 && REGNO (XEXP (XEXP (x
, 0), 0)) == CC_REGNUM
11022 && XEXP (XEXP (x
, 0), 1) == const0_rtx
))
11024 mode
= GET_MODE (XEXP (XEXP (x
, 0), 0));
11025 *cost
+= (COSTS_N_INSNS (1)
11026 + rtx_cost (XEXP (XEXP (x
, 0), 0), mode
, COMPARE
,
11028 + rtx_cost (XEXP (XEXP (x
, 0), 1), mode
, COMPARE
,
11031 *cost
+= extra_cost
->alu
.arith
;
11037 *cost
+= extra_cost
->alu
.arith
;
11041 if (GET_MODE_CLASS (mode
) == MODE_INT
11042 && GET_MODE_SIZE (mode
) < 4)
11044 /* Slightly disparage, as we might need an extend operation. */
11047 *cost
+= extra_cost
->alu
.arith
;
11051 if (mode
== DImode
)
11053 *cost
+= COSTS_N_INSNS (1);
11055 *cost
+= 2 * extra_cost
->alu
.arith
;
11060 *cost
= LIBCALL_COST (1);
11064 if (mode
== SImode
)
11067 rtx shift_reg
= NULL
;
11069 shift_op
= shifter_op_p (XEXP (x
, 0), &shift_reg
);
11073 if (shift_reg
!= NULL
)
11076 *cost
+= extra_cost
->alu
.log_shift_reg
;
11077 *cost
+= rtx_cost (shift_reg
, mode
, ASHIFT
, 1, speed_p
);
11080 *cost
+= extra_cost
->alu
.log_shift
;
11081 *cost
+= rtx_cost (shift_op
, mode
, ASHIFT
, 0, speed_p
);
11086 *cost
+= extra_cost
->alu
.logical
;
11089 if (mode
== DImode
)
11091 *cost
+= COSTS_N_INSNS (1);
11097 *cost
+= LIBCALL_COST (1);
11102 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
11104 *cost
+= COSTS_N_INSNS (3);
11107 int op1cost
= rtx_cost (XEXP (x
, 1), mode
, SET
, 1, speed_p
);
11108 int op2cost
= rtx_cost (XEXP (x
, 2), mode
, SET
, 1, speed_p
);
11110 *cost
= rtx_cost (XEXP (x
, 0), mode
, IF_THEN_ELSE
, 0, speed_p
);
11111 /* Assume that if one arm of the if_then_else is a register,
11112 that it will be tied with the result and eliminate the
11113 conditional insn. */
11114 if (REG_P (XEXP (x
, 1)))
11116 else if (REG_P (XEXP (x
, 2)))
11122 if (extra_cost
->alu
.non_exec_costs_exec
)
11123 *cost
+= op1cost
+ op2cost
+ extra_cost
->alu
.non_exec
;
11125 *cost
+= MAX (op1cost
, op2cost
) + extra_cost
->alu
.non_exec
;
11128 *cost
+= op1cost
+ op2cost
;
11134 if (cc_register (XEXP (x
, 0), VOIDmode
) && XEXP (x
, 1) == const0_rtx
)
11138 machine_mode op0mode
;
11139 /* We'll mostly assume that the cost of a compare is the cost of the
11140 LHS. However, there are some notable exceptions. */
11142 /* Floating point compares are never done as side-effects. */
11143 op0mode
= GET_MODE (XEXP (x
, 0));
11144 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (op0mode
) == MODE_FLOAT
11145 && (op0mode
== SFmode
|| !TARGET_VFP_SINGLE
))
11148 *cost
+= extra_cost
->fp
[op0mode
!= SFmode
].compare
;
11150 if (XEXP (x
, 1) == CONST0_RTX (op0mode
))
11152 *cost
+= rtx_cost (XEXP (x
, 0), op0mode
, code
, 0, speed_p
);
11158 else if (GET_MODE_CLASS (op0mode
) == MODE_FLOAT
)
11160 *cost
= LIBCALL_COST (2);
11164 /* DImode compares normally take two insns. */
11165 if (op0mode
== DImode
)
11167 *cost
+= COSTS_N_INSNS (1);
11169 *cost
+= 2 * extra_cost
->alu
.arith
;
11173 if (op0mode
== SImode
)
11178 if (XEXP (x
, 1) == const0_rtx
11179 && !(REG_P (XEXP (x
, 0))
11180 || (GET_CODE (XEXP (x
, 0)) == SUBREG
11181 && REG_P (SUBREG_REG (XEXP (x
, 0))))))
11183 *cost
= rtx_cost (XEXP (x
, 0), op0mode
, COMPARE
, 0, speed_p
);
11185 /* Multiply operations that set the flags are often
11186 significantly more expensive. */
11188 && GET_CODE (XEXP (x
, 0)) == MULT
11189 && !power_of_two_operand (XEXP (XEXP (x
, 0), 1), mode
))
11190 *cost
+= extra_cost
->mult
[0].flag_setting
;
11193 && GET_CODE (XEXP (x
, 0)) == PLUS
11194 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
11195 && !power_of_two_operand (XEXP (XEXP (XEXP (x
, 0),
11197 *cost
+= extra_cost
->mult
[0].flag_setting
;
11202 shift_op
= shifter_op_p (XEXP (x
, 0), &shift_reg
);
11203 if (shift_op
!= NULL
)
11205 if (shift_reg
!= NULL
)
11207 *cost
+= rtx_cost (shift_reg
, op0mode
, ASHIFT
,
11210 *cost
+= extra_cost
->alu
.arith_shift_reg
;
11213 *cost
+= extra_cost
->alu
.arith_shift
;
11214 *cost
+= rtx_cost (shift_op
, op0mode
, ASHIFT
, 0, speed_p
);
11215 *cost
+= rtx_cost (XEXP (x
, 1), op0mode
, COMPARE
, 1, speed_p
);
11220 *cost
+= extra_cost
->alu
.arith
;
11221 if (CONST_INT_P (XEXP (x
, 1))
11222 && const_ok_for_op (INTVAL (XEXP (x
, 1)), COMPARE
))
11224 *cost
+= rtx_cost (XEXP (x
, 0), op0mode
, COMPARE
, 0, speed_p
);
11232 *cost
= LIBCALL_COST (2);
11242 /* Neon has special instructions when comparing with 0 (vceq, vcge, vcgt,
11245 && TARGET_HARD_FLOAT
11246 && (VALID_NEON_DREG_MODE (mode
) || VALID_NEON_QREG_MODE (mode
))
11247 && (XEXP (x
, 1) == CONST0_RTX (mode
)))
11253 /* Fall through. */
11267 if (outer_code
== SET
)
11269 /* Is it a store-flag operation? */
11270 if (REG_P (XEXP (x
, 0)) && REGNO (XEXP (x
, 0)) == CC_REGNUM
11271 && XEXP (x
, 1) == const0_rtx
)
11273 /* Thumb also needs an IT insn. */
11274 *cost
+= COSTS_N_INSNS (TARGET_THUMB
? 2 : 1);
11277 if (XEXP (x
, 1) == const0_rtx
)
11282 /* LSR Rd, Rn, #31. */
11284 *cost
+= extra_cost
->alu
.shift
;
11294 *cost
+= COSTS_N_INSNS (1);
11298 /* RSBS T1, Rn, Rn, LSR #31
11300 *cost
+= COSTS_N_INSNS (1);
11302 *cost
+= extra_cost
->alu
.arith_shift
;
11306 /* RSB Rd, Rn, Rn, ASR #1
11307 LSR Rd, Rd, #31. */
11308 *cost
+= COSTS_N_INSNS (1);
11310 *cost
+= (extra_cost
->alu
.arith_shift
11311 + extra_cost
->alu
.shift
);
11317 *cost
+= COSTS_N_INSNS (1);
11319 *cost
+= extra_cost
->alu
.shift
;
11323 /* Remaining cases are either meaningless or would take
11324 three insns anyway. */
11325 *cost
= COSTS_N_INSNS (3);
11328 *cost
+= rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed_p
);
11333 *cost
+= COSTS_N_INSNS (TARGET_THUMB
? 3 : 2);
11334 if (CONST_INT_P (XEXP (x
, 1))
11335 && const_ok_for_op (INTVAL (XEXP (x
, 1)), COMPARE
))
11337 *cost
+= rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed_p
);
11344 /* Not directly inside a set. If it involves the condition code
11345 register it must be the condition for a branch, cond_exec or
11346 I_T_E operation. Since the comparison is performed elsewhere
11347 this is just the control part which has no additional
11349 else if (REG_P (XEXP (x
, 0)) && REGNO (XEXP (x
, 0)) == CC_REGNUM
11350 && XEXP (x
, 1) == const0_rtx
)
11358 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
11359 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
11362 *cost
+= extra_cost
->fp
[mode
!= SFmode
].neg
;
11366 else if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
11368 *cost
= LIBCALL_COST (1);
11372 if (mode
== SImode
)
11375 *cost
+= extra_cost
->alu
.log_shift
+ extra_cost
->alu
.arith_shift
;
11379 *cost
= LIBCALL_COST (1);
11383 if ((arm_arch4
|| GET_MODE (XEXP (x
, 0)) == SImode
)
11384 && MEM_P (XEXP (x
, 0)))
11386 if (mode
== DImode
)
11387 *cost
+= COSTS_N_INSNS (1);
11392 if (GET_MODE (XEXP (x
, 0)) == SImode
)
11393 *cost
+= extra_cost
->ldst
.load
;
11395 *cost
+= extra_cost
->ldst
.load_sign_extend
;
11397 if (mode
== DImode
)
11398 *cost
+= extra_cost
->alu
.shift
;
11403 /* Widening from less than 32-bits requires an extend operation. */
11404 if (GET_MODE (XEXP (x
, 0)) != SImode
&& arm_arch6
)
11406 /* We have SXTB/SXTH. */
11407 *cost
+= rtx_cost (XEXP (x
, 0), VOIDmode
, code
, 0, speed_p
);
11409 *cost
+= extra_cost
->alu
.extend
;
11411 else if (GET_MODE (XEXP (x
, 0)) != SImode
)
11413 /* Needs two shifts. */
11414 *cost
+= COSTS_N_INSNS (1);
11415 *cost
+= rtx_cost (XEXP (x
, 0), VOIDmode
, code
, 0, speed_p
);
11417 *cost
+= 2 * extra_cost
->alu
.shift
;
11420 /* Widening beyond 32-bits requires one more insn. */
11421 if (mode
== DImode
)
11423 *cost
+= COSTS_N_INSNS (1);
11425 *cost
+= extra_cost
->alu
.shift
;
11432 || GET_MODE (XEXP (x
, 0)) == SImode
11433 || GET_MODE (XEXP (x
, 0)) == QImode
)
11434 && MEM_P (XEXP (x
, 0)))
11436 *cost
= rtx_cost (XEXP (x
, 0), VOIDmode
, code
, 0, speed_p
);
11438 if (mode
== DImode
)
11439 *cost
+= COSTS_N_INSNS (1); /* No speed penalty. */
11444 /* Widening from less than 32-bits requires an extend operation. */
11445 if (GET_MODE (XEXP (x
, 0)) == QImode
)
11447 /* UXTB can be a shorter instruction in Thumb2, but it might
11448 be slower than the AND Rd, Rn, #255 alternative. When
11449 optimizing for speed it should never be slower to use
11450 AND, and we don't really model 16-bit vs 32-bit insns
11453 *cost
+= extra_cost
->alu
.logical
;
11455 else if (GET_MODE (XEXP (x
, 0)) != SImode
&& arm_arch6
)
11457 /* We have UXTB/UXTH. */
11458 *cost
+= rtx_cost (XEXP (x
, 0), VOIDmode
, code
, 0, speed_p
);
11460 *cost
+= extra_cost
->alu
.extend
;
11462 else if (GET_MODE (XEXP (x
, 0)) != SImode
)
11464 /* Needs two shifts. It's marginally preferable to use
11465 shifts rather than two BIC instructions as the second
11466 shift may merge with a subsequent insn as a shifter
11468 *cost
= COSTS_N_INSNS (2);
11469 *cost
+= rtx_cost (XEXP (x
, 0), VOIDmode
, code
, 0, speed_p
);
11471 *cost
+= 2 * extra_cost
->alu
.shift
;
11474 /* Widening beyond 32-bits requires one more insn. */
11475 if (mode
== DImode
)
11477 *cost
+= COSTS_N_INSNS (1); /* No speed penalty. */
11484 /* CONST_INT has no mode, so we cannot tell for sure how many
11485 insns are really going to be needed. The best we can do is
11486 look at the value passed. If it fits in SImode, then assume
11487 that's the mode it will be used for. Otherwise assume it
11488 will be used in DImode. */
11489 if (INTVAL (x
) == trunc_int_for_mode (INTVAL (x
), SImode
))
11494 /* Avoid blowing up in arm_gen_constant (). */
11495 if (!(outer_code
== PLUS
11496 || outer_code
== AND
11497 || outer_code
== IOR
11498 || outer_code
== XOR
11499 || outer_code
== MINUS
))
11503 if (mode
== SImode
)
11505 *cost
+= COSTS_N_INSNS (arm_gen_constant (outer_code
, SImode
, NULL
,
11506 INTVAL (x
), NULL
, NULL
,
11512 *cost
+= COSTS_N_INSNS (arm_gen_constant
11513 (outer_code
, SImode
, NULL
,
11514 trunc_int_for_mode (INTVAL (x
), SImode
),
11516 + arm_gen_constant (outer_code
, SImode
, NULL
,
11517 INTVAL (x
) >> 32, NULL
,
11529 if (arm_arch_thumb2
&& !flag_pic
)
11530 *cost
+= COSTS_N_INSNS (1);
11532 *cost
+= extra_cost
->ldst
.load
;
11535 *cost
+= COSTS_N_INSNS (1);
11539 *cost
+= COSTS_N_INSNS (1);
11541 *cost
+= extra_cost
->alu
.arith
;
11547 *cost
= COSTS_N_INSNS (4);
11552 if (TARGET_HARD_FLOAT
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
11553 && (mode
== SFmode
|| !TARGET_VFP_SINGLE
))
11555 if (vfp3_const_double_rtx (x
))
11558 *cost
+= extra_cost
->fp
[mode
== DFmode
].fpconst
;
11564 if (mode
== DFmode
)
11565 *cost
+= extra_cost
->ldst
.loadd
;
11567 *cost
+= extra_cost
->ldst
.loadf
;
11570 *cost
+= COSTS_N_INSNS (1 + (mode
== DFmode
));
11574 *cost
= COSTS_N_INSNS (4);
11579 if (((TARGET_NEON
&& TARGET_HARD_FLOAT
11580 && (VALID_NEON_DREG_MODE (mode
) || VALID_NEON_QREG_MODE (mode
)))
11581 || TARGET_HAVE_MVE
)
11582 && simd_immediate_valid_for_move (x
, mode
, NULL
, NULL
))
11583 *cost
= COSTS_N_INSNS (1);
11585 *cost
= COSTS_N_INSNS (4);
11590 /* When optimizing for size, we prefer constant pool entries to
11591 MOVW/MOVT pairs, so bump the cost of these slightly. */
11598 *cost
+= extra_cost
->alu
.clz
;
11602 if (XEXP (x
, 1) == const0_rtx
)
11605 *cost
+= extra_cost
->alu
.log_shift
;
11606 *cost
+= rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed_p
);
11609 /* Fall through. */
11613 *cost
+= COSTS_N_INSNS (1);
11617 if (GET_CODE (XEXP (x
, 0)) == ASHIFTRT
11618 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
11619 && INTVAL (XEXP (XEXP (x
, 0), 1)) == 32
11620 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
11621 && ((GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
11622 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == SIGN_EXTEND
)
11623 || (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
11624 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1))
11628 *cost
+= extra_cost
->mult
[1].extend
;
11629 *cost
+= (rtx_cost (XEXP (XEXP (XEXP (x
, 0), 0), 0), VOIDmode
,
11630 ZERO_EXTEND
, 0, speed_p
)
11631 + rtx_cost (XEXP (XEXP (XEXP (x
, 0), 0), 1), VOIDmode
,
11632 ZERO_EXTEND
, 0, speed_p
));
11635 *cost
= LIBCALL_COST (1);
11638 case UNSPEC_VOLATILE
:
11640 return arm_unspec_cost (x
, outer_code
, speed_p
, cost
);
11643 /* Reading the PC is like reading any other register. Writing it
11644 is more expensive, but we take that into account elsewhere. */
11649 /* TODO: Simple zero_extract of bottom bits using AND. */
11650 /* Fall through. */
11654 && CONST_INT_P (XEXP (x
, 1))
11655 && CONST_INT_P (XEXP (x
, 2)))
11658 *cost
+= extra_cost
->alu
.bfx
;
11659 *cost
+= rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed_p
);
11662 /* Without UBFX/SBFX, need to resort to shift operations. */
11663 *cost
+= COSTS_N_INSNS (1);
11665 *cost
+= 2 * extra_cost
->alu
.shift
;
11666 *cost
+= rtx_cost (XEXP (x
, 0), mode
, ASHIFT
, 0, speed_p
);
11670 if (TARGET_HARD_FLOAT
)
11673 *cost
+= extra_cost
->fp
[mode
== DFmode
].widen
;
11675 && GET_MODE (XEXP (x
, 0)) == HFmode
)
11677 /* Pre v8, widening HF->DF is a two-step process, first
11678 widening to SFmode. */
11679 *cost
+= COSTS_N_INSNS (1);
11681 *cost
+= extra_cost
->fp
[0].widen
;
11683 *cost
+= rtx_cost (XEXP (x
, 0), VOIDmode
, code
, 0, speed_p
);
11687 *cost
= LIBCALL_COST (1);
11690 case FLOAT_TRUNCATE
:
11691 if (TARGET_HARD_FLOAT
)
11694 *cost
+= extra_cost
->fp
[mode
== DFmode
].narrow
;
11695 *cost
+= rtx_cost (XEXP (x
, 0), VOIDmode
, code
, 0, speed_p
);
11697 /* Vector modes? */
11699 *cost
= LIBCALL_COST (1);
11703 if (TARGET_32BIT
&& TARGET_HARD_FLOAT
&& TARGET_FMA
)
11705 rtx op0
= XEXP (x
, 0);
11706 rtx op1
= XEXP (x
, 1);
11707 rtx op2
= XEXP (x
, 2);
11710 /* vfms or vfnma. */
11711 if (GET_CODE (op0
) == NEG
)
11712 op0
= XEXP (op0
, 0);
11714 /* vfnms or vfnma. */
11715 if (GET_CODE (op2
) == NEG
)
11716 op2
= XEXP (op2
, 0);
11718 *cost
+= rtx_cost (op0
, mode
, FMA
, 0, speed_p
);
11719 *cost
+= rtx_cost (op1
, mode
, FMA
, 1, speed_p
);
11720 *cost
+= rtx_cost (op2
, mode
, FMA
, 2, speed_p
);
11723 *cost
+= extra_cost
->fp
[mode
==DFmode
].fma
;
11728 *cost
= LIBCALL_COST (3);
11733 if (TARGET_HARD_FLOAT
)
11735 /* The *combine_vcvtf2i reduces a vmul+vcvt into
11736 a vcvt fixed-point conversion. */
11737 if (code
== FIX
&& mode
== SImode
11738 && GET_CODE (XEXP (x
, 0)) == FIX
11739 && GET_MODE (XEXP (x
, 0)) == SFmode
11740 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
11741 && vfp3_const_double_for_bits (XEXP (XEXP (XEXP (x
, 0), 0), 1))
11745 *cost
+= extra_cost
->fp
[0].toint
;
11747 *cost
+= rtx_cost (XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
,
11752 if (GET_MODE_CLASS (mode
) == MODE_INT
)
11754 mode
= GET_MODE (XEXP (x
, 0));
11756 *cost
+= extra_cost
->fp
[mode
== DFmode
].toint
;
11757 /* Strip of the 'cost' of rounding towards zero. */
11758 if (GET_CODE (XEXP (x
, 0)) == FIX
)
11759 *cost
+= rtx_cost (XEXP (XEXP (x
, 0), 0), mode
, code
,
11762 *cost
+= rtx_cost (XEXP (x
, 0), mode
, code
, 0, speed_p
);
11763 /* ??? Increase the cost to deal with transferring from
11764 FP -> CORE registers? */
11767 else if (GET_MODE_CLASS (mode
) == MODE_FLOAT
11771 *cost
+= extra_cost
->fp
[mode
== DFmode
].roundint
;
11774 /* Vector costs? */
11776 *cost
= LIBCALL_COST (1);
11780 case UNSIGNED_FLOAT
:
11781 if (TARGET_HARD_FLOAT
)
11783 /* ??? Increase the cost to deal with transferring from CORE
11784 -> FP registers? */
11786 *cost
+= extra_cost
->fp
[mode
== DFmode
].fromint
;
11789 *cost
= LIBCALL_COST (1);
11797 /* Just a guess. Guess number of instructions in the asm
11798 plus one insn per input. Always a minimum of COSTS_N_INSNS (1)
11799 though (see PR60663). */
11800 int asm_length
= MAX (1, asm_str_count (ASM_OPERANDS_TEMPLATE (x
)));
11801 int num_operands
= ASM_OPERANDS_INPUT_LENGTH (x
);
11803 *cost
= COSTS_N_INSNS (asm_length
+ num_operands
);
11807 if (mode
!= VOIDmode
)
11808 *cost
= COSTS_N_INSNS (ARM_NUM_REGS (mode
));
11810 *cost
= COSTS_N_INSNS (4); /* Who knows? */
11815 #undef HANDLE_NARROW_SHIFT_ARITH
11817 /* RTX costs entry point. */
11820 arm_rtx_costs (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
, int outer_code
,
11821 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
11824 int code
= GET_CODE (x
);
11825 gcc_assert (current_tune
->insn_extra_cost
);
11827 result
= arm_rtx_costs_internal (x
, (enum rtx_code
) code
,
11828 (enum rtx_code
) outer_code
,
11829 current_tune
->insn_extra_cost
,
11832 if (dump_file
&& arm_verbose_cost
)
11834 print_rtl_single (dump_file
, x
);
11835 fprintf (dump_file
, "\n%s cost: %d (%s)\n", speed
? "Hot" : "Cold",
11836 *total
, result
? "final" : "partial");
11842 arm_insn_cost (rtx_insn
*insn
, bool speed
)
11846 /* Don't cost a simple reg-reg move at a full insn cost: such moves
11847 will likely disappear during register allocation. */
11848 if (!reload_completed
11849 && GET_CODE (PATTERN (insn
)) == SET
11850 && REG_P (SET_DEST (PATTERN (insn
)))
11851 && REG_P (SET_SRC (PATTERN (insn
))))
11853 cost
= pattern_cost (PATTERN (insn
), speed
);
11854 /* If the cost is zero, then it's likely a complex insn. We don't want the
11855 cost of these to be less than something we know about. */
11856 return cost
? cost
: COSTS_N_INSNS (2);
11859 /* All address computations that can be done are free, but rtx cost returns
11860 the same for practically all of them. So we weight the different types
11861 of address here in the order (most pref first):
11862 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
11864 arm_arm_address_cost (rtx x
)
11866 enum rtx_code c
= GET_CODE (x
);
11868 if (c
== PRE_INC
|| c
== PRE_DEC
|| c
== POST_INC
|| c
== POST_DEC
)
11870 if (c
== MEM
|| c
== LABEL_REF
|| c
== SYMBOL_REF
)
11875 if (CONST_INT_P (XEXP (x
, 1)))
11878 if (ARITHMETIC_P (XEXP (x
, 0)) || ARITHMETIC_P (XEXP (x
, 1)))
11888 arm_thumb_address_cost (rtx x
)
11890 enum rtx_code c
= GET_CODE (x
);
11895 && REG_P (XEXP (x
, 0))
11896 && CONST_INT_P (XEXP (x
, 1)))
11903 arm_address_cost (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
,
11904 addr_space_t as ATTRIBUTE_UNUSED
, bool speed ATTRIBUTE_UNUSED
)
11906 return TARGET_32BIT
? arm_arm_address_cost (x
) : arm_thumb_address_cost (x
);
11909 /* Adjust cost hook for XScale. */
11911 xscale_sched_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep
,
11914 /* Some true dependencies can have a higher cost depending
11915 on precisely how certain input operands are used. */
11917 && recog_memoized (insn
) >= 0
11918 && recog_memoized (dep
) >= 0)
11920 int shift_opnum
= get_attr_shift (insn
);
11921 enum attr_type attr_type
= get_attr_type (dep
);
11923 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
11924 operand for INSN. If we have a shifted input operand and the
11925 instruction we depend on is another ALU instruction, then we may
11926 have to account for an additional stall. */
11927 if (shift_opnum
!= 0
11928 && (attr_type
== TYPE_ALU_SHIFT_IMM_LSL_1TO4
11929 || attr_type
== TYPE_ALU_SHIFT_IMM_OTHER
11930 || attr_type
== TYPE_ALUS_SHIFT_IMM
11931 || attr_type
== TYPE_LOGIC_SHIFT_IMM
11932 || attr_type
== TYPE_LOGICS_SHIFT_IMM
11933 || attr_type
== TYPE_ALU_SHIFT_REG
11934 || attr_type
== TYPE_ALUS_SHIFT_REG
11935 || attr_type
== TYPE_LOGIC_SHIFT_REG
11936 || attr_type
== TYPE_LOGICS_SHIFT_REG
11937 || attr_type
== TYPE_MOV_SHIFT
11938 || attr_type
== TYPE_MVN_SHIFT
11939 || attr_type
== TYPE_MOV_SHIFT_REG
11940 || attr_type
== TYPE_MVN_SHIFT_REG
))
11942 rtx shifted_operand
;
11945 /* Get the shifted operand. */
11946 extract_insn (insn
);
11947 shifted_operand
= recog_data
.operand
[shift_opnum
];
11949 /* Iterate over all the operands in DEP. If we write an operand
11950 that overlaps with SHIFTED_OPERAND, then we have increase the
11951 cost of this dependency. */
11952 extract_insn (dep
);
11953 preprocess_constraints (dep
);
11954 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
11956 /* We can ignore strict inputs. */
11957 if (recog_data
.operand_type
[opno
] == OP_IN
)
11960 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
11972 /* Adjust cost hook for Cortex A9. */
11974 cortex_a9_sched_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep
,
11984 case REG_DEP_OUTPUT
:
11985 if (recog_memoized (insn
) >= 0
11986 && recog_memoized (dep
) >= 0)
11988 if (GET_CODE (PATTERN (insn
)) == SET
)
11991 (GET_MODE (SET_DEST (PATTERN (insn
)))) == MODE_FLOAT
11993 (GET_MODE (SET_SRC (PATTERN (insn
)))) == MODE_FLOAT
)
11995 enum attr_type attr_type_insn
= get_attr_type (insn
);
11996 enum attr_type attr_type_dep
= get_attr_type (dep
);
11998 /* By default all dependencies of the form
12001 have an extra latency of 1 cycle because
12002 of the input and output dependency in this
12003 case. However this gets modeled as an true
12004 dependency and hence all these checks. */
12005 if (REG_P (SET_DEST (PATTERN (insn
)))
12006 && reg_set_p (SET_DEST (PATTERN (insn
)), dep
))
12008 /* FMACS is a special case where the dependent
12009 instruction can be issued 3 cycles before
12010 the normal latency in case of an output
12012 if ((attr_type_insn
== TYPE_FMACS
12013 || attr_type_insn
== TYPE_FMACD
)
12014 && (attr_type_dep
== TYPE_FMACS
12015 || attr_type_dep
== TYPE_FMACD
))
12017 if (dep_type
== REG_DEP_OUTPUT
)
12018 *cost
= insn_default_latency (dep
) - 3;
12020 *cost
= insn_default_latency (dep
);
12025 if (dep_type
== REG_DEP_OUTPUT
)
12026 *cost
= insn_default_latency (dep
) + 1;
12028 *cost
= insn_default_latency (dep
);
12038 gcc_unreachable ();
12044 /* Adjust cost hook for FA726TE. */
12046 fa726te_sched_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep
,
12049 /* For FA726TE, true dependency on CPSR (i.e. set cond followed by predicated)
12050 have penalty of 3. */
12051 if (dep_type
== REG_DEP_TRUE
12052 && recog_memoized (insn
) >= 0
12053 && recog_memoized (dep
) >= 0
12054 && get_attr_conds (dep
) == CONDS_SET
)
12056 /* Use of carry (e.g. 64-bit arithmetic) in ALU: 3-cycle latency. */
12057 if (get_attr_conds (insn
) == CONDS_USE
12058 && get_attr_type (insn
) != TYPE_BRANCH
)
12064 if (GET_CODE (PATTERN (insn
)) == COND_EXEC
12065 || get_attr_conds (insn
) == CONDS_USE
)
12075 /* Implement TARGET_REGISTER_MOVE_COST.
12077 Moves between VFP_REGS and GENERAL_REGS are a single insn, but
12078 it is typically more expensive than a single memory access. We set
12079 the cost to less than two memory accesses so that floating
12080 point to integer conversion does not go through memory. */
12083 arm_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
12084 reg_class_t from
, reg_class_t to
)
12088 if ((IS_VFP_CLASS (from
) && !IS_VFP_CLASS (to
))
12089 || (!IS_VFP_CLASS (from
) && IS_VFP_CLASS (to
)))
12091 else if ((from
== IWMMXT_REGS
&& to
!= IWMMXT_REGS
)
12092 || (from
!= IWMMXT_REGS
&& to
== IWMMXT_REGS
))
12094 else if (from
== IWMMXT_GR_REGS
|| to
== IWMMXT_GR_REGS
)
12101 if (from
== HI_REGS
|| to
== HI_REGS
)
12108 /* Implement TARGET_MEMORY_MOVE_COST. */
12111 arm_memory_move_cost (machine_mode mode
, reg_class_t rclass
,
12112 bool in ATTRIBUTE_UNUSED
)
12118 if (GET_MODE_SIZE (mode
) < 4)
12121 return ((2 * GET_MODE_SIZE (mode
)) * (rclass
== LO_REGS
? 1 : 2));
12125 /* Vectorizer cost model implementation. */
12127 /* Implement targetm.vectorize.builtin_vectorization_cost. */
12129 arm_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
12131 int misalign ATTRIBUTE_UNUSED
)
12135 switch (type_of_cost
)
12138 return current_tune
->vec_costs
->scalar_stmt_cost
;
12141 return current_tune
->vec_costs
->scalar_load_cost
;
12144 return current_tune
->vec_costs
->scalar_store_cost
;
12147 return current_tune
->vec_costs
->vec_stmt_cost
;
12150 return current_tune
->vec_costs
->vec_align_load_cost
;
12153 return current_tune
->vec_costs
->vec_store_cost
;
12155 case vec_to_scalar
:
12156 return current_tune
->vec_costs
->vec_to_scalar_cost
;
12158 case scalar_to_vec
:
12159 return current_tune
->vec_costs
->scalar_to_vec_cost
;
12161 case unaligned_load
:
12162 case vector_gather_load
:
12163 return current_tune
->vec_costs
->vec_unalign_load_cost
;
12165 case unaligned_store
:
12166 case vector_scatter_store
:
12167 return current_tune
->vec_costs
->vec_unalign_store_cost
;
12169 case cond_branch_taken
:
12170 return current_tune
->vec_costs
->cond_taken_branch_cost
;
12172 case cond_branch_not_taken
:
12173 return current_tune
->vec_costs
->cond_not_taken_branch_cost
;
12176 case vec_promote_demote
:
12177 return current_tune
->vec_costs
->vec_stmt_cost
;
12179 case vec_construct
:
12180 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
12181 return elements
/ 2 + 1;
12184 gcc_unreachable ();
12188 /* Implement targetm.vectorize.add_stmt_cost. */
12191 arm_add_stmt_cost (vec_info
*vinfo
, void *data
, int count
,
12192 enum vect_cost_for_stmt kind
,
12193 struct _stmt_vec_info
*stmt_info
, tree vectype
,
12194 int misalign
, enum vect_cost_model_location where
)
12196 unsigned *cost
= (unsigned *) data
;
12197 unsigned retval
= 0;
12199 if (flag_vect_cost_model
)
12201 int stmt_cost
= arm_builtin_vectorization_cost (kind
, vectype
, misalign
);
12203 /* Statements in an inner loop relative to the loop being
12204 vectorized are weighted more heavily. The value here is
12205 arbitrary and could potentially be improved with analysis. */
12206 if (where
== vect_body
&& stmt_info
12207 && stmt_in_inner_loop_p (vinfo
, stmt_info
))
12208 count
*= 50; /* FIXME. */
12210 retval
= (unsigned) (count
* stmt_cost
);
12211 cost
[where
] += retval
;
12217 /* Return true if and only if this insn can dual-issue only as older. */
12219 cortexa7_older_only (rtx_insn
*insn
)
12221 if (recog_memoized (insn
) < 0)
12224 switch (get_attr_type (insn
))
12226 case TYPE_ALU_DSP_REG
:
12227 case TYPE_ALU_SREG
:
12228 case TYPE_ALUS_SREG
:
12229 case TYPE_LOGIC_REG
:
12230 case TYPE_LOGICS_REG
:
12232 case TYPE_ADCS_REG
:
12237 case TYPE_SHIFT_IMM
:
12238 case TYPE_SHIFT_REG
:
12239 case TYPE_LOAD_BYTE
:
12242 case TYPE_FFARITHS
:
12244 case TYPE_FFARITHD
:
12262 case TYPE_F_STORES
:
12269 /* Return true if and only if this insn can dual-issue as younger. */
12271 cortexa7_younger (FILE *file
, int verbose
, rtx_insn
*insn
)
12273 if (recog_memoized (insn
) < 0)
12276 fprintf (file
, ";; not cortexa7_younger %d\n", INSN_UID (insn
));
12280 switch (get_attr_type (insn
))
12283 case TYPE_ALUS_IMM
:
12284 case TYPE_LOGIC_IMM
:
12285 case TYPE_LOGICS_IMM
:
12290 case TYPE_MOV_SHIFT
:
12291 case TYPE_MOV_SHIFT_REG
:
12301 /* Look for an instruction that can dual issue only as an older
12302 instruction, and move it in front of any instructions that can
12303 dual-issue as younger, while preserving the relative order of all
12304 other instructions in the ready list. This is a hueuristic to help
12305 dual-issue in later cycles, by postponing issue of more flexible
12306 instructions. This heuristic may affect dual issue opportunities
12307 in the current cycle. */
12309 cortexa7_sched_reorder (FILE *file
, int verbose
, rtx_insn
**ready
,
12310 int *n_readyp
, int clock
)
12313 int first_older_only
= -1, first_younger
= -1;
12317 ";; sched_reorder for cycle %d with %d insns in ready list\n",
12321 /* Traverse the ready list from the head (the instruction to issue
12322 first), and looking for the first instruction that can issue as
12323 younger and the first instruction that can dual-issue only as
12325 for (i
= *n_readyp
- 1; i
>= 0; i
--)
12327 rtx_insn
*insn
= ready
[i
];
12328 if (cortexa7_older_only (insn
))
12330 first_older_only
= i
;
12332 fprintf (file
, ";; reorder older found %d\n", INSN_UID (insn
));
12335 else if (cortexa7_younger (file
, verbose
, insn
) && first_younger
== -1)
12339 /* Nothing to reorder because either no younger insn found or insn
12340 that can dual-issue only as older appears before any insn that
12341 can dual-issue as younger. */
12342 if (first_younger
== -1)
12345 fprintf (file
, ";; sched_reorder nothing to reorder as no younger\n");
12349 /* Nothing to reorder because no older-only insn in the ready list. */
12350 if (first_older_only
== -1)
12353 fprintf (file
, ";; sched_reorder nothing to reorder as no older_only\n");
12357 /* Move first_older_only insn before first_younger. */
12359 fprintf (file
, ";; cortexa7_sched_reorder insn %d before %d\n",
12360 INSN_UID(ready
[first_older_only
]),
12361 INSN_UID(ready
[first_younger
]));
12362 rtx_insn
*first_older_only_insn
= ready
[first_older_only
];
12363 for (i
= first_older_only
; i
< first_younger
; i
++)
12365 ready
[i
] = ready
[i
+1];
12368 ready
[i
] = first_older_only_insn
;
12372 /* Implement TARGET_SCHED_REORDER. */
12374 arm_sched_reorder (FILE *file
, int verbose
, rtx_insn
**ready
, int *n_readyp
,
12379 case TARGET_CPU_cortexa7
:
12380 cortexa7_sched_reorder (file
, verbose
, ready
, n_readyp
, clock
);
12383 /* Do nothing for other cores. */
12387 return arm_issue_rate ();
12390 /* This function implements the target macro TARGET_SCHED_ADJUST_COST.
12391 It corrects the value of COST based on the relationship between
12392 INSN and DEP through the dependence LINK. It returns the new
12393 value. There is a per-core adjust_cost hook to adjust scheduler costs
12394 and the per-core hook can choose to completely override the generic
12395 adjust_cost function. Only put bits of code into arm_adjust_cost that
12396 are common across all cores. */
12398 arm_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep
, int cost
,
12403 /* When generating Thumb-1 code, we want to place flag-setting operations
12404 close to a conditional branch which depends on them, so that we can
12405 omit the comparison. */
12408 && recog_memoized (insn
) == CODE_FOR_cbranchsi4_insn
12409 && recog_memoized (dep
) >= 0
12410 && get_attr_conds (dep
) == CONDS_SET
)
12413 if (current_tune
->sched_adjust_cost
!= NULL
)
12415 if (!current_tune
->sched_adjust_cost (insn
, dep_type
, dep
, &cost
))
12419 /* XXX Is this strictly true? */
12420 if (dep_type
== REG_DEP_ANTI
12421 || dep_type
== REG_DEP_OUTPUT
)
12424 /* Call insns don't incur a stall, even if they follow a load. */
12429 if ((i_pat
= single_set (insn
)) != NULL
12430 && MEM_P (SET_SRC (i_pat
))
12431 && (d_pat
= single_set (dep
)) != NULL
12432 && MEM_P (SET_DEST (d_pat
)))
12434 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
12435 /* This is a load after a store, there is no conflict if the load reads
12436 from a cached area. Assume that loads from the stack, and from the
12437 constant pool are cached, and that others will miss. This is a
12440 if ((SYMBOL_REF_P (src_mem
)
12441 && CONSTANT_POOL_ADDRESS_P (src_mem
))
12442 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
12443 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
12444 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
12452 arm_max_conditional_execute (void)
12454 return max_insns_skipped
;
12458 arm_default_branch_cost (bool speed_p
, bool predictable_p ATTRIBUTE_UNUSED
)
12461 return (TARGET_THUMB2
&& !speed_p
) ? 1 : 4;
12463 return (optimize
> 0) ? 2 : 0;
12467 arm_cortex_a5_branch_cost (bool speed_p
, bool predictable_p
)
12469 return speed_p
? 0 : arm_default_branch_cost (speed_p
, predictable_p
);
12472 /* Thumb-2 branches are relatively cheap on Cortex-M processors ("1 + P cycles"
12473 on Cortex-M4, where P varies from 1 to 3 according to some criteria), since
12474 sequences of non-executed instructions in IT blocks probably take the same
12475 amount of time as executed instructions (and the IT instruction itself takes
12476 space in icache). This function was experimentally determined to give good
12477 results on a popular embedded benchmark. */
12480 arm_cortex_m_branch_cost (bool speed_p
, bool predictable_p
)
12482 return (TARGET_32BIT
&& speed_p
) ? 1
12483 : arm_default_branch_cost (speed_p
, predictable_p
);
12487 arm_cortex_m7_branch_cost (bool speed_p
, bool predictable_p
)
12489 return speed_p
? 0 : arm_default_branch_cost (speed_p
, predictable_p
);
12492 static bool fp_consts_inited
= false;
12494 static REAL_VALUE_TYPE value_fp0
;
12497 init_fp_table (void)
12501 r
= REAL_VALUE_ATOF ("0", DFmode
);
12503 fp_consts_inited
= true;
12506 /* Return TRUE if rtx X is a valid immediate FP constant. */
12508 arm_const_double_rtx (rtx x
)
12510 const REAL_VALUE_TYPE
*r
;
12512 if (!fp_consts_inited
)
12515 r
= CONST_DOUBLE_REAL_VALUE (x
);
12516 if (REAL_VALUE_MINUS_ZERO (*r
))
12519 if (real_equal (r
, &value_fp0
))
12525 /* VFPv3 has a fairly wide range of representable immediates, formed from
12526 "quarter-precision" floating-point values. These can be evaluated using this
12527 formula (with ^ for exponentiation):
12531 Where 's' is a sign bit (0/1), 'n' and 'r' are integers such that
12532 16 <= n <= 31 and 0 <= r <= 7.
12534 These values are mapped onto an 8-bit integer ABCDEFGH s.t.
12536 - A (most-significant) is the sign bit.
12537 - BCD are the exponent (encoded as r XOR 3).
12538 - EFGH are the mantissa (encoded as n - 16).
12541 /* Return an integer index for a VFPv3 immediate operand X suitable for the
12542 fconst[sd] instruction, or -1 if X isn't suitable. */
12544 vfp3_const_double_index (rtx x
)
12546 REAL_VALUE_TYPE r
, m
;
12547 int sign
, exponent
;
12548 unsigned HOST_WIDE_INT mantissa
, mant_hi
;
12549 unsigned HOST_WIDE_INT mask
;
12550 int point_pos
= 2 * HOST_BITS_PER_WIDE_INT
- 1;
12553 if (!TARGET_VFP3
|| !CONST_DOUBLE_P (x
))
12556 r
= *CONST_DOUBLE_REAL_VALUE (x
);
12558 /* We can't represent these things, so detect them first. */
12559 if (REAL_VALUE_ISINF (r
) || REAL_VALUE_ISNAN (r
) || REAL_VALUE_MINUS_ZERO (r
))
12562 /* Extract sign, exponent and mantissa. */
12563 sign
= REAL_VALUE_NEGATIVE (r
) ? 1 : 0;
12564 r
= real_value_abs (&r
);
12565 exponent
= REAL_EXP (&r
);
12566 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
12567 highest (sign) bit, with a fixed binary point at bit point_pos.
12568 WARNING: If there's ever a VFP version which uses more than 2 * H_W_I - 1
12569 bits for the mantissa, this may fail (low bits would be lost). */
12570 real_ldexp (&m
, &r
, point_pos
- exponent
);
12571 wide_int w
= real_to_integer (&m
, &fail
, HOST_BITS_PER_WIDE_INT
* 2);
12572 mantissa
= w
.elt (0);
12573 mant_hi
= w
.elt (1);
12575 /* If there are bits set in the low part of the mantissa, we can't
12576 represent this value. */
12580 /* Now make it so that mantissa contains the most-significant bits, and move
12581 the point_pos to indicate that the least-significant bits have been
12583 point_pos
-= HOST_BITS_PER_WIDE_INT
;
12584 mantissa
= mant_hi
;
12586 /* We can permit four significant bits of mantissa only, plus a high bit
12587 which is always 1. */
12588 mask
= (HOST_WIDE_INT_1U
<< (point_pos
- 5)) - 1;
12589 if ((mantissa
& mask
) != 0)
12592 /* Now we know the mantissa is in range, chop off the unneeded bits. */
12593 mantissa
>>= point_pos
- 5;
12595 /* The mantissa may be zero. Disallow that case. (It's possible to load the
12596 floating-point immediate zero with Neon using an integer-zero load, but
12597 that case is handled elsewhere.) */
12601 gcc_assert (mantissa
>= 16 && mantissa
<= 31);
12603 /* The value of 5 here would be 4 if GCC used IEEE754-like encoding (where
12604 normalized significands are in the range [1, 2). (Our mantissa is shifted
12605 left 4 places at this point relative to normalized IEEE754 values). GCC
12606 internally uses [0.5, 1) (see real.c), so the exponent returned from
12607 REAL_EXP must be altered. */
12608 exponent
= 5 - exponent
;
12610 if (exponent
< 0 || exponent
> 7)
12613 /* Sign, mantissa and exponent are now in the correct form to plug into the
12614 formula described in the comment above. */
12615 return (sign
<< 7) | ((exponent
^ 3) << 4) | (mantissa
- 16);
12618 /* Return TRUE if rtx X is a valid immediate VFPv3 constant. */
12620 vfp3_const_double_rtx (rtx x
)
12625 return vfp3_const_double_index (x
) != -1;
12628 /* Recognize immediates which can be used in various Neon and MVE instructions.
12629 Legal immediates are described by the following table (for VMVN variants, the
12630 bitwise inverse of the constant shown is recognized. In either case, VMOV
12631 is output and the correct instruction to use for a given constant is chosen
12632 by the assembler). The constant shown is replicated across all elements of
12633 the destination vector.
12635 insn elems variant constant (binary)
12636 ---- ----- ------- -----------------
12637 vmov i32 0 00000000 00000000 00000000 abcdefgh
12638 vmov i32 1 00000000 00000000 abcdefgh 00000000
12639 vmov i32 2 00000000 abcdefgh 00000000 00000000
12640 vmov i32 3 abcdefgh 00000000 00000000 00000000
12641 vmov i16 4 00000000 abcdefgh
12642 vmov i16 5 abcdefgh 00000000
12643 vmvn i32 6 00000000 00000000 00000000 abcdefgh
12644 vmvn i32 7 00000000 00000000 abcdefgh 00000000
12645 vmvn i32 8 00000000 abcdefgh 00000000 00000000
12646 vmvn i32 9 abcdefgh 00000000 00000000 00000000
12647 vmvn i16 10 00000000 abcdefgh
12648 vmvn i16 11 abcdefgh 00000000
12649 vmov i32 12 00000000 00000000 abcdefgh 11111111
12650 vmvn i32 13 00000000 00000000 abcdefgh 11111111
12651 vmov i32 14 00000000 abcdefgh 11111111 11111111
12652 vmvn i32 15 00000000 abcdefgh 11111111 11111111
12653 vmov i8 16 abcdefgh
12654 vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd
12655 eeeeeeee ffffffff gggggggg hhhhhhhh
12656 vmov f32 18 aBbbbbbc defgh000 00000000 00000000
12657 vmov f32 19 00000000 00000000 00000000 00000000
12659 For case 18, B = !b. Representable values are exactly those accepted by
12660 vfp3_const_double_index, but are output as floating-point numbers rather
12663 For case 19, we will change it to vmov.i32 when assembling.
12665 Variants 0-5 (inclusive) may also be used as immediates for the second
12666 operand of VORR/VBIC instructions.
12668 The INVERSE argument causes the bitwise inverse of the given operand to be
12669 recognized instead (used for recognizing legal immediates for the VAND/VORN
12670 pseudo-instructions). If INVERSE is true, the value placed in *MODCONST is
12671 *not* inverted (i.e. the pseudo-instruction forms vand/vorn should still be
12672 output, rather than the real insns vbic/vorr).
12674 INVERSE makes no difference to the recognition of float vectors.
12676 The return value is the variant of immediate as shown in the above table, or
12677 -1 if the given value doesn't match any of the listed patterns.
12680 simd_valid_immediate (rtx op
, machine_mode mode
, int inverse
,
12681 rtx
*modconst
, int *elementwidth
)
12683 #define CHECK(STRIDE, ELSIZE, CLASS, TEST) \
12685 for (i = 0; i < idx; i += (STRIDE)) \
12690 immtype = (CLASS); \
12691 elsize = (ELSIZE); \
12695 unsigned int i
, elsize
= 0, idx
= 0, n_elts
;
12696 unsigned int innersize
;
12697 unsigned char bytes
[16] = {};
12698 int immtype
= -1, matches
;
12699 unsigned int invmask
= inverse
? 0xff : 0;
12700 bool vector
= GET_CODE (op
) == CONST_VECTOR
;
12703 n_elts
= CONST_VECTOR_NUNITS (op
);
12707 gcc_assert (mode
!= VOIDmode
);
12710 innersize
= GET_MODE_UNIT_SIZE (mode
);
12712 /* Only support 128-bit vectors for MVE. */
12713 if (TARGET_HAVE_MVE
&& (!vector
|| n_elts
* innersize
!= 16))
12716 /* Vectors of float constants. */
12717 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
12719 rtx el0
= CONST_VECTOR_ELT (op
, 0);
12721 if (!vfp3_const_double_rtx (el0
) && el0
!= CONST0_RTX (GET_MODE (el0
)))
12724 /* FP16 vectors cannot be represented. */
12725 if (GET_MODE_INNER (mode
) == HFmode
)
12728 /* All elements in the vector must be the same. Note that 0.0 and -0.0
12729 are distinct in this context. */
12730 if (!const_vec_duplicate_p (op
))
12734 *modconst
= CONST_VECTOR_ELT (op
, 0);
12739 if (el0
== CONST0_RTX (GET_MODE (el0
)))
12745 /* The tricks done in the code below apply for little-endian vector layout.
12746 For big-endian vectors only allow vectors of the form { a, a, a..., a }.
12747 FIXME: Implement logic for big-endian vectors. */
12748 if (BYTES_BIG_ENDIAN
&& vector
&& !const_vec_duplicate_p (op
))
12751 /* Splat vector constant out into a byte vector. */
12752 for (i
= 0; i
< n_elts
; i
++)
12754 rtx el
= vector
? CONST_VECTOR_ELT (op
, i
) : op
;
12755 unsigned HOST_WIDE_INT elpart
;
12757 gcc_assert (CONST_INT_P (el
));
12758 elpart
= INTVAL (el
);
12760 for (unsigned int byte
= 0; byte
< innersize
; byte
++)
12762 bytes
[idx
++] = (elpart
& 0xff) ^ invmask
;
12763 elpart
>>= BITS_PER_UNIT
;
12767 /* Sanity check. */
12768 gcc_assert (idx
== GET_MODE_SIZE (mode
));
12772 CHECK (4, 32, 0, bytes
[i
] == bytes
[0] && bytes
[i
+ 1] == 0
12773 && bytes
[i
+ 2] == 0 && bytes
[i
+ 3] == 0);
12775 CHECK (4, 32, 1, bytes
[i
] == 0 && bytes
[i
+ 1] == bytes
[1]
12776 && bytes
[i
+ 2] == 0 && bytes
[i
+ 3] == 0);
12778 CHECK (4, 32, 2, bytes
[i
] == 0 && bytes
[i
+ 1] == 0
12779 && bytes
[i
+ 2] == bytes
[2] && bytes
[i
+ 3] == 0);
12781 CHECK (4, 32, 3, bytes
[i
] == 0 && bytes
[i
+ 1] == 0
12782 && bytes
[i
+ 2] == 0 && bytes
[i
+ 3] == bytes
[3]);
12784 CHECK (2, 16, 4, bytes
[i
] == bytes
[0] && bytes
[i
+ 1] == 0);
12786 CHECK (2, 16, 5, bytes
[i
] == 0 && bytes
[i
+ 1] == bytes
[1]);
12788 CHECK (4, 32, 6, bytes
[i
] == bytes
[0] && bytes
[i
+ 1] == 0xff
12789 && bytes
[i
+ 2] == 0xff && bytes
[i
+ 3] == 0xff);
12791 CHECK (4, 32, 7, bytes
[i
] == 0xff && bytes
[i
+ 1] == bytes
[1]
12792 && bytes
[i
+ 2] == 0xff && bytes
[i
+ 3] == 0xff);
12794 CHECK (4, 32, 8, bytes
[i
] == 0xff && bytes
[i
+ 1] == 0xff
12795 && bytes
[i
+ 2] == bytes
[2] && bytes
[i
+ 3] == 0xff);
12797 CHECK (4, 32, 9, bytes
[i
] == 0xff && bytes
[i
+ 1] == 0xff
12798 && bytes
[i
+ 2] == 0xff && bytes
[i
+ 3] == bytes
[3]);
12800 CHECK (2, 16, 10, bytes
[i
] == bytes
[0] && bytes
[i
+ 1] == 0xff);
12802 CHECK (2, 16, 11, bytes
[i
] == 0xff && bytes
[i
+ 1] == bytes
[1]);
12804 CHECK (4, 32, 12, bytes
[i
] == 0xff && bytes
[i
+ 1] == bytes
[1]
12805 && bytes
[i
+ 2] == 0 && bytes
[i
+ 3] == 0);
12807 CHECK (4, 32, 13, bytes
[i
] == 0 && bytes
[i
+ 1] == bytes
[1]
12808 && bytes
[i
+ 2] == 0xff && bytes
[i
+ 3] == 0xff);
12810 CHECK (4, 32, 14, bytes
[i
] == 0xff && bytes
[i
+ 1] == 0xff
12811 && bytes
[i
+ 2] == bytes
[2] && bytes
[i
+ 3] == 0);
12813 CHECK (4, 32, 15, bytes
[i
] == 0 && bytes
[i
+ 1] == 0
12814 && bytes
[i
+ 2] == bytes
[2] && bytes
[i
+ 3] == 0xff);
12816 CHECK (1, 8, 16, bytes
[i
] == bytes
[0]);
12818 CHECK (1, 64, 17, (bytes
[i
] == 0 || bytes
[i
] == 0xff)
12819 && bytes
[i
] == bytes
[(i
+ 8) % idx
]);
12827 *elementwidth
= elsize
;
12831 unsigned HOST_WIDE_INT imm
= 0;
12833 /* Un-invert bytes of recognized vector, if necessary. */
12835 for (i
= 0; i
< idx
; i
++)
12836 bytes
[i
] ^= invmask
;
12840 /* FIXME: Broken on 32-bit H_W_I hosts. */
12841 gcc_assert (sizeof (HOST_WIDE_INT
) == 8);
12843 for (i
= 0; i
< 8; i
++)
12844 imm
|= (unsigned HOST_WIDE_INT
) (bytes
[i
] ? 0xff : 0)
12845 << (i
* BITS_PER_UNIT
);
12847 *modconst
= GEN_INT (imm
);
12851 unsigned HOST_WIDE_INT imm
= 0;
12853 for (i
= 0; i
< elsize
/ BITS_PER_UNIT
; i
++)
12854 imm
|= (unsigned HOST_WIDE_INT
) bytes
[i
] << (i
* BITS_PER_UNIT
);
12856 *modconst
= GEN_INT (imm
);
12864 /* Return TRUE if rtx X is legal for use as either a Neon or MVE VMOV (or,
12865 implicitly, VMVN) immediate. Write back width per element to *ELEMENTWIDTH
12866 (or zero for float elements), and a modified constant (whatever should be
12867 output for a VMOV) in *MODCONST. "neon_immediate_valid_for_move" function is
12868 modified to "simd_immediate_valid_for_move" as this function will be used
12869 both by neon and mve. */
12871 simd_immediate_valid_for_move (rtx op
, machine_mode mode
,
12872 rtx
*modconst
, int *elementwidth
)
12876 int retval
= simd_valid_immediate (op
, mode
, 0, &tmpconst
, &tmpwidth
);
12882 *modconst
= tmpconst
;
12885 *elementwidth
= tmpwidth
;
12890 /* Return TRUE if rtx X is legal for use in a VORR or VBIC instruction. If
12891 the immediate is valid, write a constant suitable for using as an operand
12892 to VORR/VBIC/VAND/VORN to *MODCONST and the corresponding element width to
12893 *ELEMENTWIDTH. See simd_valid_immediate for description of INVERSE. */
12896 neon_immediate_valid_for_logic (rtx op
, machine_mode mode
, int inverse
,
12897 rtx
*modconst
, int *elementwidth
)
12901 int retval
= simd_valid_immediate (op
, mode
, inverse
, &tmpconst
, &tmpwidth
);
12903 if (retval
< 0 || retval
> 5)
12907 *modconst
= tmpconst
;
12910 *elementwidth
= tmpwidth
;
12915 /* Return TRUE if rtx OP is legal for use in a VSHR or VSHL instruction. If
12916 the immediate is valid, write a constant suitable for using as an operand
12917 to VSHR/VSHL to *MODCONST and the corresponding element width to
12918 *ELEMENTWIDTH. ISLEFTSHIFT is for determine left or right shift,
12919 because they have different limitations. */
12922 neon_immediate_valid_for_shift (rtx op
, machine_mode mode
,
12923 rtx
*modconst
, int *elementwidth
,
12926 unsigned int innersize
= GET_MODE_UNIT_SIZE (mode
);
12927 unsigned int n_elts
= CONST_VECTOR_NUNITS (op
), i
;
12928 unsigned HOST_WIDE_INT last_elt
= 0;
12929 unsigned HOST_WIDE_INT maxshift
;
12931 /* Split vector constant out into a byte vector. */
12932 for (i
= 0; i
< n_elts
; i
++)
12934 rtx el
= CONST_VECTOR_ELT (op
, i
);
12935 unsigned HOST_WIDE_INT elpart
;
12937 if (CONST_INT_P (el
))
12938 elpart
= INTVAL (el
);
12939 else if (CONST_DOUBLE_P (el
))
12942 gcc_unreachable ();
12944 if (i
!= 0 && elpart
!= last_elt
)
12950 /* Shift less than element size. */
12951 maxshift
= innersize
* 8;
12955 /* Left shift immediate value can be from 0 to <size>-1. */
12956 if (last_elt
>= maxshift
)
12961 /* Right shift immediate value can be from 1 to <size>. */
12962 if (last_elt
== 0 || last_elt
> maxshift
)
12967 *elementwidth
= innersize
* 8;
12970 *modconst
= CONST_VECTOR_ELT (op
, 0);
12975 /* Return a string suitable for output of Neon immediate logic operation
12979 neon_output_logic_immediate (const char *mnem
, rtx
*op2
, machine_mode mode
,
12980 int inverse
, int quad
)
12982 int width
, is_valid
;
12983 static char templ
[40];
12985 is_valid
= neon_immediate_valid_for_logic (*op2
, mode
, inverse
, op2
, &width
);
12987 gcc_assert (is_valid
!= 0);
12990 sprintf (templ
, "%s.i%d\t%%q0, %%2", mnem
, width
);
12992 sprintf (templ
, "%s.i%d\t%%P0, %%2", mnem
, width
);
12997 /* Return a string suitable for output of Neon immediate shift operation
12998 (VSHR or VSHL) MNEM. */
13001 neon_output_shift_immediate (const char *mnem
, char sign
, rtx
*op2
,
13002 machine_mode mode
, int quad
,
13005 int width
, is_valid
;
13006 static char templ
[40];
13008 is_valid
= neon_immediate_valid_for_shift (*op2
, mode
, op2
, &width
, isleftshift
);
13009 gcc_assert (is_valid
!= 0);
13012 sprintf (templ
, "%s.%c%d\t%%q0, %%q1, %%2", mnem
, sign
, width
);
13014 sprintf (templ
, "%s.%c%d\t%%P0, %%P1, %%2", mnem
, sign
, width
);
13019 /* Output a sequence of pairwise operations to implement a reduction.
13020 NOTE: We do "too much work" here, because pairwise operations work on two
13021 registers-worth of operands in one go. Unfortunately we can't exploit those
13022 extra calculations to do the full operation in fewer steps, I don't think.
13023 Although all vector elements of the result but the first are ignored, we
13024 actually calculate the same result in each of the elements. An alternative
13025 such as initially loading a vector with zero to use as each of the second
13026 operands would use up an additional register and take an extra instruction,
13027 for no particular gain. */
13030 neon_pairwise_reduce (rtx op0
, rtx op1
, machine_mode mode
,
13031 rtx (*reduc
) (rtx
, rtx
, rtx
))
13033 unsigned int i
, parts
= GET_MODE_SIZE (mode
) / GET_MODE_UNIT_SIZE (mode
);
13036 for (i
= parts
/ 2; i
>= 1; i
/= 2)
13038 rtx dest
= (i
== 1) ? op0
: gen_reg_rtx (mode
);
13039 emit_insn (reduc (dest
, tmpsum
, tmpsum
));
13044 /* Return a non-NULL RTX iff VALS is a vector constant that can be
13045 loaded into a register using VDUP.
13047 If this is the case, and GENERATE is set, we also generate
13048 instructions to do this and return an RTX to assign to the register. */
13051 neon_vdup_constant (rtx vals
, bool generate
)
13053 machine_mode mode
= GET_MODE (vals
);
13054 machine_mode inner_mode
= GET_MODE_INNER (mode
);
13057 if (GET_CODE (vals
) != CONST_VECTOR
|| GET_MODE_SIZE (inner_mode
) > 4)
13060 if (!const_vec_duplicate_p (vals
, &x
))
13061 /* The elements are not all the same. We could handle repeating
13062 patterns of a mode larger than INNER_MODE here (e.g. int8x8_t
13063 {0, C, 0, C, 0, C, 0, C} which can be loaded using
13070 /* We can load this constant by using VDUP and a constant in a
13071 single ARM register. This will be cheaper than a vector
13074 x
= copy_to_mode_reg (inner_mode
, x
);
13075 return gen_vec_duplicate (mode
, x
);
13078 /* Return a non-NULL RTX iff VALS, which is a PARALLEL containing only
13079 constants (for vec_init) or CONST_VECTOR, can be effeciently loaded
13082 If this is the case, and GENERATE is set, we also generate code to do
13083 this and return an RTX to copy into the register. */
13086 neon_make_constant (rtx vals
, bool generate
)
13088 machine_mode mode
= GET_MODE (vals
);
13090 rtx const_vec
= NULL_RTX
;
13091 int n_elts
= GET_MODE_NUNITS (mode
);
13095 if (GET_CODE (vals
) == CONST_VECTOR
)
13097 else if (GET_CODE (vals
) == PARALLEL
)
13099 /* A CONST_VECTOR must contain only CONST_INTs and
13100 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
13101 Only store valid constants in a CONST_VECTOR. */
13102 for (i
= 0; i
< n_elts
; ++i
)
13104 rtx x
= XVECEXP (vals
, 0, i
);
13105 if (CONST_INT_P (x
) || CONST_DOUBLE_P (x
))
13108 if (n_const
== n_elts
)
13109 const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
13112 gcc_unreachable ();
13114 if (const_vec
!= NULL
13115 && simd_immediate_valid_for_move (const_vec
, mode
, NULL
, NULL
))
13116 /* Load using VMOV. On Cortex-A8 this takes one cycle. */
13118 else if ((target
= neon_vdup_constant (vals
, generate
)) != NULL_RTX
)
13119 /* Loaded using VDUP. On Cortex-A8 the VDUP takes one NEON
13120 pipeline cycle; creating the constant takes one or two ARM
13121 pipeline cycles. */
13123 else if (const_vec
!= NULL_RTX
)
13124 /* Load from constant pool. On Cortex-A8 this takes two cycles
13125 (for either double or quad vectors). We cannot take advantage
13126 of single-cycle VLD1 because we need a PC-relative addressing
13128 return arm_disable_literal_pool
? NULL_RTX
: const_vec
;
13130 /* A PARALLEL containing something not valid inside CONST_VECTOR.
13131 We cannot construct an initializer. */
13135 /* Initialize vector TARGET to VALS. */
13138 neon_expand_vector_init (rtx target
, rtx vals
)
13140 machine_mode mode
= GET_MODE (target
);
13141 machine_mode inner_mode
= GET_MODE_INNER (mode
);
13142 int n_elts
= GET_MODE_NUNITS (mode
);
13143 int n_var
= 0, one_var
= -1;
13144 bool all_same
= true;
13148 for (i
= 0; i
< n_elts
; ++i
)
13150 x
= XVECEXP (vals
, 0, i
);
13151 if (!CONSTANT_P (x
))
13152 ++n_var
, one_var
= i
;
13154 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
13160 rtx constant
= neon_make_constant (vals
);
13161 if (constant
!= NULL_RTX
)
13163 emit_move_insn (target
, constant
);
13168 /* Splat a single non-constant element if we can. */
13169 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
13171 x
= copy_to_mode_reg (inner_mode
, XVECEXP (vals
, 0, 0));
13172 emit_insn (gen_rtx_SET (target
, gen_vec_duplicate (mode
, x
)));
13176 /* One field is non-constant. Load constant then overwrite varying
13177 field. This is more efficient than using the stack. */
13180 rtx copy
= copy_rtx (vals
);
13181 rtx merge_mask
= GEN_INT (1 << one_var
);
13183 /* Load constant part of vector, substitute neighboring value for
13184 varying element. */
13185 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
13186 neon_expand_vector_init (target
, copy
);
13188 /* Insert variable. */
13189 x
= copy_to_mode_reg (inner_mode
, XVECEXP (vals
, 0, one_var
));
13190 emit_insn (gen_vec_set_internal (mode
, target
, x
, merge_mask
, target
));
13194 /* Construct the vector in memory one field at a time
13195 and load the whole vector. */
13196 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
13197 for (i
= 0; i
< n_elts
; i
++)
13198 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
13199 i
* GET_MODE_SIZE (inner_mode
)),
13200 XVECEXP (vals
, 0, i
));
13201 emit_move_insn (target
, mem
);
13204 /* Ensure OPERAND lies between LOW (inclusive) and HIGH (exclusive). Raise
13205 ERR if it doesn't. EXP indicates the source location, which includes the
13206 inlining history for intrinsics. */
13209 bounds_check (rtx operand
, HOST_WIDE_INT low
, HOST_WIDE_INT high
,
13210 const_tree exp
, const char *desc
)
13212 HOST_WIDE_INT lane
;
13214 gcc_assert (CONST_INT_P (operand
));
13216 lane
= INTVAL (operand
);
13218 if (lane
< low
|| lane
>= high
)
13221 error ("%K%s %wd out of range %wd - %wd",
13222 exp
, desc
, lane
, low
, high
- 1);
13224 error ("%s %wd out of range %wd - %wd", desc
, lane
, low
, high
- 1);
13228 /* Bounds-check lanes. */
13231 neon_lane_bounds (rtx operand
, HOST_WIDE_INT low
, HOST_WIDE_INT high
,
13234 bounds_check (operand
, low
, high
, exp
, "lane");
13237 /* Bounds-check constants. */
13240 arm_const_bounds (rtx operand
, HOST_WIDE_INT low
, HOST_WIDE_INT high
)
13242 bounds_check (operand
, low
, high
, NULL_TREE
, "constant");
13246 neon_element_bits (machine_mode mode
)
13248 return GET_MODE_UNIT_BITSIZE (mode
);
13252 /* Predicates for `match_operand' and `match_operator'. */
13254 /* Return TRUE if OP is a valid coprocessor memory address pattern.
13255 WB level is 2 if full writeback address modes are allowed, 1
13256 if limited writeback address modes (POST_INC and PRE_DEC) are
13257 allowed and 0 if no writeback at all is supported. */
13260 arm_coproc_mem_operand_wb (rtx op
, int wb_level
)
13262 gcc_assert (wb_level
== 0 || wb_level
== 1 || wb_level
== 2);
13265 /* Reject eliminable registers. */
13266 if (! (reload_in_progress
|| reload_completed
|| lra_in_progress
)
13267 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
13268 || reg_mentioned_p (arg_pointer_rtx
, op
)
13269 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
13270 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
13271 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
13272 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
13275 /* Constants are converted into offsets from labels. */
13279 ind
= XEXP (op
, 0);
13281 if (reload_completed
13282 && (LABEL_REF_P (ind
)
13283 || (GET_CODE (ind
) == CONST
13284 && GET_CODE (XEXP (ind
, 0)) == PLUS
13285 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
13286 && CONST_INT_P (XEXP (XEXP (ind
, 0), 1)))))
13289 /* Match: (mem (reg)). */
13291 return arm_address_register_rtx_p (ind
, 0);
13293 /* Autoincremment addressing modes. POST_INC and PRE_DEC are
13294 acceptable in any case (subject to verification by
13295 arm_address_register_rtx_p). We need full writeback to accept
13296 PRE_INC and POST_DEC, and at least restricted writeback for
13297 PRE_INC and POST_DEC. */
13299 && (GET_CODE (ind
) == POST_INC
13300 || GET_CODE (ind
) == PRE_DEC
13302 && (GET_CODE (ind
) == PRE_INC
13303 || GET_CODE (ind
) == POST_DEC
))))
13304 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
13307 && (GET_CODE (ind
) == POST_MODIFY
|| GET_CODE (ind
) == PRE_MODIFY
)
13308 && arm_address_register_rtx_p (XEXP (ind
, 0), 0)
13309 && GET_CODE (XEXP (ind
, 1)) == PLUS
13310 && rtx_equal_p (XEXP (XEXP (ind
, 1), 0), XEXP (ind
, 0)))
13311 ind
= XEXP (ind
, 1);
13317 The encoded immediate for 16-bit modes is multiplied by 2,
13318 while the encoded immediate for 32-bit and 64-bit modes is
13319 multiplied by 4. */
13320 int factor
= MIN (GET_MODE_SIZE (GET_MODE (op
)), 4);
13321 if (GET_CODE (ind
) == PLUS
13322 && REG_P (XEXP (ind
, 0))
13323 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
13324 && CONST_INT_P (XEXP (ind
, 1))
13325 && IN_RANGE (INTVAL (XEXP (ind
, 1)), -255 * factor
, 255 * factor
)
13326 && (INTVAL (XEXP (ind
, 1)) & (factor
- 1)) == 0)
13332 /* Return TRUE if OP is a valid coprocessor memory address pattern.
13333 WB is true if full writeback address modes are allowed and is false
13334 if limited writeback address modes (POST_INC and PRE_DEC) are
13337 int arm_coproc_mem_operand (rtx op
, bool wb
)
13339 return arm_coproc_mem_operand_wb (op
, wb
? 2 : 1);
13342 /* Return TRUE if OP is a valid coprocessor memory address pattern in a
13343 context in which no writeback address modes are allowed. */
13346 arm_coproc_mem_operand_no_writeback (rtx op
)
13348 return arm_coproc_mem_operand_wb (op
, 0);
13351 /* This function returns TRUE on matching mode and op.
13352 1. For given modes, check for [Rn], return TRUE for Rn <= LO_REGS.
13353 2. For other modes, check for [Rn], return TRUE for Rn < R15 (expect R13). */
13355 mve_vector_mem_operand (machine_mode mode
, rtx op
, bool strict
)
13357 enum rtx_code code
;
13360 /* Match: (mem (reg)). */
13363 int reg_no
= REGNO (op
);
13364 return (((mode
== E_V8QImode
|| mode
== E_V4QImode
|| mode
== E_V4HImode
)
13365 ? reg_no
<= LAST_LO_REGNUM
13366 :(reg_no
< LAST_ARM_REGNUM
&& reg_no
!= SP_REGNUM
))
13367 || (!strict
&& reg_no
>= FIRST_PSEUDO_REGISTER
));
13369 code
= GET_CODE (op
);
13371 if (code
== POST_INC
|| code
== PRE_DEC
13372 || code
== PRE_INC
|| code
== POST_DEC
)
13374 reg_no
= REGNO (XEXP (op
, 0));
13375 return (((mode
== E_V8QImode
|| mode
== E_V4QImode
|| mode
== E_V4HImode
)
13376 ? reg_no
<= LAST_LO_REGNUM
13377 :(reg_no
< LAST_ARM_REGNUM
&& reg_no
!= SP_REGNUM
))
13378 || (!strict
&& reg_no
>= FIRST_PSEUDO_REGISTER
));
13380 else if ((code
== POST_MODIFY
|| code
== PRE_MODIFY
)
13381 && GET_CODE (XEXP (op
, 1)) == PLUS
&& REG_P (XEXP (XEXP (op
, 1), 1)))
13383 reg_no
= REGNO (XEXP (op
, 0));
13384 val
= INTVAL (XEXP ( XEXP (op
, 1), 1));
13388 if (abs (val
) <= 127)
13389 return ((reg_no
< LAST_ARM_REGNUM
&& reg_no
!= SP_REGNUM
)
13390 || (!strict
&& reg_no
>= FIRST_PSEUDO_REGISTER
));
13394 if (abs (val
) <= 255)
13395 return ((reg_no
< LAST_ARM_REGNUM
&& reg_no
!= SP_REGNUM
)
13396 || (!strict
&& reg_no
>= FIRST_PSEUDO_REGISTER
));
13400 if (abs (val
) <= 127)
13401 return (reg_no
<= LAST_LO_REGNUM
13402 || (!strict
&& reg_no
>= FIRST_PSEUDO_REGISTER
));
13406 if (val
% 2 == 0 && abs (val
) <= 254)
13407 return (reg_no
<= LAST_LO_REGNUM
13408 || (!strict
&& reg_no
>= FIRST_PSEUDO_REGISTER
));
13412 if (val
% 4 == 0 && abs (val
) <= 508)
13413 return ((reg_no
< LAST_ARM_REGNUM
&& reg_no
!= SP_REGNUM
)
13414 || (!strict
&& reg_no
>= FIRST_PSEUDO_REGISTER
));
13419 if (val
% 4 == 0 && val
>= 0 && val
<= 1020)
13420 return ((reg_no
< LAST_ARM_REGNUM
&& reg_no
!= SP_REGNUM
)
13421 || (!strict
&& reg_no
>= FIRST_PSEUDO_REGISTER
));
13430 /* Return TRUE if OP is a memory operand which we can load or store a vector
13431 to/from. TYPE is one of the following values:
13432 0 - Vector load/stor (vldr)
13433 1 - Core registers (ldm)
13434 2 - Element/structure loads (vld1)
13437 neon_vector_mem_operand (rtx op
, int type
, bool strict
)
13441 /* Reject eliminable registers. */
13442 if (strict
&& ! (reload_in_progress
|| reload_completed
)
13443 && (reg_mentioned_p (frame_pointer_rtx
, op
)
13444 || reg_mentioned_p (arg_pointer_rtx
, op
)
13445 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
13446 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
13447 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
13448 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
13451 /* Constants are converted into offsets from labels. */
13455 ind
= XEXP (op
, 0);
13457 if (reload_completed
13458 && (LABEL_REF_P (ind
)
13459 || (GET_CODE (ind
) == CONST
13460 && GET_CODE (XEXP (ind
, 0)) == PLUS
13461 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
13462 && CONST_INT_P (XEXP (XEXP (ind
, 0), 1)))))
13465 /* Match: (mem (reg)). */
13467 return arm_address_register_rtx_p (ind
, 0);
13469 /* Allow post-increment with Neon registers. */
13470 if ((type
!= 1 && GET_CODE (ind
) == POST_INC
)
13471 || (type
== 0 && GET_CODE (ind
) == PRE_DEC
))
13472 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
13474 /* Allow post-increment by register for VLDn */
13475 if (type
== 2 && GET_CODE (ind
) == POST_MODIFY
13476 && GET_CODE (XEXP (ind
, 1)) == PLUS
13477 && REG_P (XEXP (XEXP (ind
, 1), 1))
13478 && REG_P (XEXP (ind
, 0))
13479 && rtx_equal_p (XEXP (ind
, 0), XEXP (XEXP (ind
, 1), 0)))
13486 && GET_CODE (ind
) == PLUS
13487 && REG_P (XEXP (ind
, 0))
13488 && REG_MODE_OK_FOR_BASE_P (XEXP (ind
, 0), VOIDmode
)
13489 && CONST_INT_P (XEXP (ind
, 1))
13490 && INTVAL (XEXP (ind
, 1)) > -1024
13491 /* For quad modes, we restrict the constant offset to be slightly less
13492 than what the instruction format permits. We have no such constraint
13493 on double mode offsets. (This must match arm_legitimate_index_p.) */
13494 && (INTVAL (XEXP (ind
, 1))
13495 < (VALID_NEON_QREG_MODE (GET_MODE (op
))? 1016 : 1024))
13496 && (INTVAL (XEXP (ind
, 1)) & 3) == 0)
13502 /* Return TRUE if OP is a mem suitable for loading/storing a Neon struct
13505 neon_struct_mem_operand (rtx op
)
13509 /* Reject eliminable registers. */
13510 if (! (reload_in_progress
|| reload_completed
)
13511 && ( reg_mentioned_p (frame_pointer_rtx
, op
)
13512 || reg_mentioned_p (arg_pointer_rtx
, op
)
13513 || reg_mentioned_p (virtual_incoming_args_rtx
, op
)
13514 || reg_mentioned_p (virtual_outgoing_args_rtx
, op
)
13515 || reg_mentioned_p (virtual_stack_dynamic_rtx
, op
)
13516 || reg_mentioned_p (virtual_stack_vars_rtx
, op
)))
13519 /* Constants are converted into offsets from labels. */
13523 ind
= XEXP (op
, 0);
13525 if (reload_completed
13526 && (LABEL_REF_P (ind
)
13527 || (GET_CODE (ind
) == CONST
13528 && GET_CODE (XEXP (ind
, 0)) == PLUS
13529 && GET_CODE (XEXP (XEXP (ind
, 0), 0)) == LABEL_REF
13530 && CONST_INT_P (XEXP (XEXP (ind
, 0), 1)))))
13533 /* Match: (mem (reg)). */
13535 return arm_address_register_rtx_p (ind
, 0);
13537 /* vldm/vstm allows POST_INC (ia) and PRE_DEC (db). */
13538 if (GET_CODE (ind
) == POST_INC
13539 || GET_CODE (ind
) == PRE_DEC
)
13540 return arm_address_register_rtx_p (XEXP (ind
, 0), 0);
13545 /* Prepares the operands for the VCMLA by lane instruction such that the right
13546 register number is selected. This instruction is special in that it always
13547 requires a D register, however there is a choice to be made between Dn[0],
13548 Dn[1], D(n+1)[0], and D(n+1)[1] depending on the mode of the registers.
13550 The VCMLA by lane function always selects two values. For instance given D0
13551 and a V2SF, the only valid index is 0 as the values in S0 and S1 will be
13552 used by the instruction. However given V4SF then index 0 and 1 are valid as
13553 D0[0] or D1[0] are both valid.
13555 This function centralizes that information based on OPERANDS, OPERANDS[3]
13556 will be changed from a REG into a CONST_INT RTX and OPERANDS[4] will be
13557 updated to contain the right index. */
13560 neon_vcmla_lane_prepare_operands (rtx
*operands
)
13562 int lane
= INTVAL (operands
[4]);
13563 machine_mode constmode
= SImode
;
13564 machine_mode mode
= GET_MODE (operands
[3]);
13565 int regno
= REGNO (operands
[3]);
13566 regno
= ((regno
- FIRST_VFP_REGNUM
) >> 1);
13567 if (lane
> 0 && lane
>= GET_MODE_NUNITS (mode
) / 4)
13569 operands
[3] = gen_int_mode (regno
+ 1, constmode
);
13571 = gen_int_mode (lane
- GET_MODE_NUNITS (mode
) / 4, constmode
);
13575 operands
[3] = gen_int_mode (regno
, constmode
);
13576 operands
[4] = gen_int_mode (lane
, constmode
);
13582 /* Return true if X is a register that will be eliminated later on. */
13584 arm_eliminable_register (rtx x
)
13586 return REG_P (x
) && (REGNO (x
) == FRAME_POINTER_REGNUM
13587 || REGNO (x
) == ARG_POINTER_REGNUM
13588 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
13589 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
));
13592 /* Return GENERAL_REGS if a scratch register required to reload x to/from
13593 coprocessor registers. Otherwise return NO_REGS. */
13596 coproc_secondary_reload_class (machine_mode mode
, rtx x
, bool wb
)
13598 if (mode
== HFmode
)
13600 if (!TARGET_NEON_FP16
&& !TARGET_VFP_FP16INST
)
13601 return GENERAL_REGS
;
13602 if (s_register_operand (x
, mode
) || neon_vector_mem_operand (x
, 2, true))
13604 return GENERAL_REGS
;
13607 /* The neon move patterns handle all legitimate vector and struct
13610 && (MEM_P (x
) || GET_CODE (x
) == CONST_VECTOR
)
13611 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
13612 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
13613 || VALID_NEON_STRUCT_MODE (mode
)))
13616 if (arm_coproc_mem_operand (x
, wb
) || s_register_operand (x
, mode
))
13619 return GENERAL_REGS
;
13622 /* Values which must be returned in the most-significant end of the return
13626 arm_return_in_msb (const_tree valtype
)
13628 return (TARGET_AAPCS_BASED
13629 && BYTES_BIG_ENDIAN
13630 && (AGGREGATE_TYPE_P (valtype
)
13631 || TREE_CODE (valtype
) == COMPLEX_TYPE
13632 || FIXED_POINT_TYPE_P (valtype
)));
13635 /* Return TRUE if X references a SYMBOL_REF. */
13637 symbol_mentioned_p (rtx x
)
13642 if (SYMBOL_REF_P (x
))
13645 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
13646 are constant offsets, not symbols. */
13647 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
13650 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13652 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
13658 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13659 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
13662 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
13669 /* Return TRUE if X references a LABEL_REF. */
13671 label_mentioned_p (rtx x
)
13676 if (LABEL_REF_P (x
))
13679 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
13680 instruction, but they are constant offsets, not symbols. */
13681 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
13684 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13685 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
13691 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13692 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
13695 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
13703 tls_mentioned_p (rtx x
)
13705 switch (GET_CODE (x
))
13708 return tls_mentioned_p (XEXP (x
, 0));
13711 if (XINT (x
, 1) == UNSPEC_TLS
)
13714 /* Fall through. */
13720 /* Must not copy any rtx that uses a pc-relative address.
13721 Also, disallow copying of load-exclusive instructions that
13722 may appear after splitting of compare-and-swap-style operations
13723 so as to prevent those loops from being transformed away from their
13724 canonical forms (see PR 69904). */
13727 arm_cannot_copy_insn_p (rtx_insn
*insn
)
13729 /* The tls call insn cannot be copied, as it is paired with a data
13731 if (recog_memoized (insn
) == CODE_FOR_tlscall
)
13734 subrtx_iterator::array_type array
;
13735 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), ALL
)
13737 const_rtx x
= *iter
;
13738 if (GET_CODE (x
) == UNSPEC
13739 && (XINT (x
, 1) == UNSPEC_PIC_BASE
13740 || XINT (x
, 1) == UNSPEC_PIC_UNIFIED
))
13744 rtx set
= single_set (insn
);
13747 rtx src
= SET_SRC (set
);
13748 if (GET_CODE (src
) == ZERO_EXTEND
)
13749 src
= XEXP (src
, 0);
13751 /* Catch the load-exclusive and load-acquire operations. */
13752 if (GET_CODE (src
) == UNSPEC_VOLATILE
13753 && (XINT (src
, 1) == VUNSPEC_LL
13754 || XINT (src
, 1) == VUNSPEC_LAX
))
13761 minmax_code (rtx x
)
13763 enum rtx_code code
= GET_CODE (x
);
13776 gcc_unreachable ();
13780 /* Match pair of min/max operators that can be implemented via usat/ssat. */
13783 arm_sat_operator_match (rtx lo_bound
, rtx hi_bound
,
13784 int *mask
, bool *signed_sat
)
13786 /* The high bound must be a power of two minus one. */
13787 int log
= exact_log2 (INTVAL (hi_bound
) + 1);
13791 /* The low bound is either zero (for usat) or one less than the
13792 negation of the high bound (for ssat). */
13793 if (INTVAL (lo_bound
) == 0)
13798 *signed_sat
= false;
13803 if (INTVAL (lo_bound
) == -INTVAL (hi_bound
) - 1)
13808 *signed_sat
= true;
13816 /* Return 1 if memory locations are adjacent. */
13818 adjacent_mem_locations (rtx a
, rtx b
)
13820 /* We don't guarantee to preserve the order of these memory refs. */
13821 if (volatile_refs_p (a
) || volatile_refs_p (b
))
13824 if ((REG_P (XEXP (a
, 0))
13825 || (GET_CODE (XEXP (a
, 0)) == PLUS
13826 && CONST_INT_P (XEXP (XEXP (a
, 0), 1))))
13827 && (REG_P (XEXP (b
, 0))
13828 || (GET_CODE (XEXP (b
, 0)) == PLUS
13829 && CONST_INT_P (XEXP (XEXP (b
, 0), 1)))))
13831 HOST_WIDE_INT val0
= 0, val1
= 0;
13835 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
13837 reg0
= XEXP (XEXP (a
, 0), 0);
13838 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
13841 reg0
= XEXP (a
, 0);
13843 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
13845 reg1
= XEXP (XEXP (b
, 0), 0);
13846 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
13849 reg1
= XEXP (b
, 0);
13851 /* Don't accept any offset that will require multiple
13852 instructions to handle, since this would cause the
13853 arith_adjacentmem pattern to output an overlong sequence. */
13854 if (!const_ok_for_op (val0
, PLUS
) || !const_ok_for_op (val1
, PLUS
))
13857 /* Don't allow an eliminable register: register elimination can make
13858 the offset too large. */
13859 if (arm_eliminable_register (reg0
))
13862 val_diff
= val1
- val0
;
13866 /* If the target has load delay slots, then there's no benefit
13867 to using an ldm instruction unless the offset is zero and
13868 we are optimizing for size. */
13869 return (optimize_size
&& (REGNO (reg0
) == REGNO (reg1
))
13870 && (val0
== 0 || val1
== 0 || val0
== 4 || val1
== 4)
13871 && (val_diff
== 4 || val_diff
== -4));
13874 return ((REGNO (reg0
) == REGNO (reg1
))
13875 && (val_diff
== 4 || val_diff
== -4));
13881 /* Return true if OP is a valid load or store multiple operation. LOAD is true
13882 for load operations, false for store operations. CONSECUTIVE is true
13883 if the register numbers in the operation must be consecutive in the register
13884 bank. RETURN_PC is true if value is to be loaded in PC.
13885 The pattern we are trying to match for load is:
13886 [(SET (R_d0) (MEM (PLUS (addr) (offset))))
13887 (SET (R_d1) (MEM (PLUS (addr) (offset + <reg_increment>))))
13890 (SET (R_dn) (MEM (PLUS (addr) (offset + n * <reg_increment>))))
13893 1. If offset is 0, first insn should be (SET (R_d0) (MEM (src_addr))).
13894 2. REGNO (R_d0) < REGNO (R_d1) < ... < REGNO (R_dn).
13895 3. If consecutive is TRUE, then for kth register being loaded,
13896 REGNO (R_dk) = REGNO (R_d0) + k.
13897 The pattern for store is similar. */
13899 ldm_stm_operation_p (rtx op
, bool load
, machine_mode mode
,
13900 bool consecutive
, bool return_pc
)
13902 HOST_WIDE_INT count
= XVECLEN (op
, 0);
13903 rtx reg
, mem
, addr
;
13905 unsigned first_regno
;
13906 HOST_WIDE_INT i
= 1, base
= 0, offset
= 0;
13908 bool addr_reg_in_reglist
= false;
13909 bool update
= false;
13914 /* If not in SImode, then registers must be consecutive
13915 (e.g., VLDM instructions for DFmode). */
13916 gcc_assert ((mode
== SImode
) || consecutive
);
13917 /* Setting return_pc for stores is illegal. */
13918 gcc_assert (!return_pc
|| load
);
13920 /* Set up the increments and the regs per val based on the mode. */
13921 reg_increment
= GET_MODE_SIZE (mode
);
13922 regs_per_val
= reg_increment
/ 4;
13923 offset_adj
= return_pc
? 1 : 0;
13926 || GET_CODE (XVECEXP (op
, 0, offset_adj
)) != SET
13927 || (load
&& !REG_P (SET_DEST (XVECEXP (op
, 0, offset_adj
)))))
13930 /* Check if this is a write-back. */
13931 elt
= XVECEXP (op
, 0, offset_adj
);
13932 if (GET_CODE (SET_SRC (elt
)) == PLUS
)
13938 /* The offset adjustment must be the number of registers being
13939 popped times the size of a single register. */
13940 if (!REG_P (SET_DEST (elt
))
13941 || !REG_P (XEXP (SET_SRC (elt
), 0))
13942 || (REGNO (SET_DEST (elt
)) != REGNO (XEXP (SET_SRC (elt
), 0)))
13943 || !CONST_INT_P (XEXP (SET_SRC (elt
), 1))
13944 || INTVAL (XEXP (SET_SRC (elt
), 1)) !=
13945 ((count
- 1 - offset_adj
) * reg_increment
))
13949 i
= i
+ offset_adj
;
13950 base
= base
+ offset_adj
;
13951 /* Perform a quick check so we don't blow up below. If only one reg is loaded,
13952 success depends on the type: VLDM can do just one reg,
13953 LDM must do at least two. */
13954 if ((count
<= i
) && (mode
== SImode
))
13957 elt
= XVECEXP (op
, 0, i
- 1);
13958 if (GET_CODE (elt
) != SET
)
13963 reg
= SET_DEST (elt
);
13964 mem
= SET_SRC (elt
);
13968 reg
= SET_SRC (elt
);
13969 mem
= SET_DEST (elt
);
13972 if (!REG_P (reg
) || !MEM_P (mem
))
13975 regno
= REGNO (reg
);
13976 first_regno
= regno
;
13977 addr
= XEXP (mem
, 0);
13978 if (GET_CODE (addr
) == PLUS
)
13980 if (!CONST_INT_P (XEXP (addr
, 1)))
13983 offset
= INTVAL (XEXP (addr
, 1));
13984 addr
= XEXP (addr
, 0);
13990 /* Don't allow SP to be loaded unless it is also the base register. It
13991 guarantees that SP is reset correctly when an LDM instruction
13992 is interrupted. Otherwise, we might end up with a corrupt stack. */
13993 if (load
&& (REGNO (reg
) == SP_REGNUM
) && (REGNO (addr
) != SP_REGNUM
))
13996 if (regno
== REGNO (addr
))
13997 addr_reg_in_reglist
= true;
13999 for (; i
< count
; i
++)
14001 elt
= XVECEXP (op
, 0, i
);
14002 if (GET_CODE (elt
) != SET
)
14007 reg
= SET_DEST (elt
);
14008 mem
= SET_SRC (elt
);
14012 reg
= SET_SRC (elt
);
14013 mem
= SET_DEST (elt
);
14017 || GET_MODE (reg
) != mode
14018 || REGNO (reg
) <= regno
14021 (unsigned int) (first_regno
+ regs_per_val
* (i
- base
))))
14022 /* Don't allow SP to be loaded unless it is also the base register. It
14023 guarantees that SP is reset correctly when an LDM instruction
14024 is interrupted. Otherwise, we might end up with a corrupt stack. */
14025 || (load
&& (REGNO (reg
) == SP_REGNUM
) && (REGNO (addr
) != SP_REGNUM
))
14027 || GET_MODE (mem
) != mode
14028 || ((GET_CODE (XEXP (mem
, 0)) != PLUS
14029 || !rtx_equal_p (XEXP (XEXP (mem
, 0), 0), addr
)
14030 || !CONST_INT_P (XEXP (XEXP (mem
, 0), 1))
14031 || (INTVAL (XEXP (XEXP (mem
, 0), 1)) !=
14032 offset
+ (i
- base
) * reg_increment
))
14033 && (!REG_P (XEXP (mem
, 0))
14034 || offset
+ (i
- base
) * reg_increment
!= 0)))
14037 regno
= REGNO (reg
);
14038 if (regno
== REGNO (addr
))
14039 addr_reg_in_reglist
= true;
14044 if (update
&& addr_reg_in_reglist
)
14047 /* For Thumb-1, address register is always modified - either by write-back
14048 or by explicit load. If the pattern does not describe an update,
14049 then the address register must be in the list of loaded registers. */
14051 return update
|| addr_reg_in_reglist
;
14057 /* Checks whether OP is a valid parallel pattern for a CLRM (if VFP is false)
14058 or VSCCLRM (otherwise) insn. To be a valid CLRM pattern, OP must have the
14061 [(set (reg:SI <N>) (const_int 0))
14062 (set (reg:SI <M>) (const_int 0))
14064 (unspec_volatile [(const_int 0)]
14066 (clobber (reg:CC CC_REGNUM))
14069 Any number (including 0) of set expressions is valid, the volatile unspec is
14070 optional. All registers but SP and PC are allowed and registers must be in
14071 strict increasing order.
14073 To be a valid VSCCLRM pattern, OP must have the following form:
14075 [(unspec_volatile [(const_int 0)]
14076 VUNSPEC_VSCCLRM_VPR)
14077 (set (reg:SF <N>) (const_int 0))
14078 (set (reg:SF <M>) (const_int 0))
14082 As with CLRM, any number (including 0) of set expressions is valid, however
14083 the volatile unspec is mandatory here. Any VFP single-precision register is
14084 accepted but all registers must be consecutive and in increasing order. */
14087 clear_operation_p (rtx op
, bool vfp
)
14090 unsigned last_regno
= INVALID_REGNUM
;
14091 rtx elt
, reg
, zero
;
14092 int count
= XVECLEN (op
, 0);
14093 int first_set
= vfp
? 1 : 0;
14094 machine_mode expected_mode
= vfp
? E_SFmode
: E_SImode
;
14096 for (int i
= first_set
; i
< count
; i
++)
14098 elt
= XVECEXP (op
, 0, i
);
14100 if (!vfp
&& GET_CODE (elt
) == UNSPEC_VOLATILE
)
14102 if (XINT (elt
, 1) != VUNSPEC_CLRM_APSR
14103 || XVECLEN (elt
, 0) != 1
14104 || XVECEXP (elt
, 0, 0) != CONST0_RTX (SImode
)
14111 if (GET_CODE (elt
) == CLOBBER
)
14114 if (GET_CODE (elt
) != SET
)
14117 reg
= SET_DEST (elt
);
14118 zero
= SET_SRC (elt
);
14121 || GET_MODE (reg
) != expected_mode
14122 || zero
!= CONST0_RTX (SImode
))
14125 regno
= REGNO (reg
);
14129 if (i
!= first_set
&& regno
!= last_regno
+ 1)
14134 if (regno
== SP_REGNUM
|| regno
== PC_REGNUM
)
14136 if (i
!= first_set
&& regno
<= last_regno
)
14140 last_regno
= regno
;
14146 /* Return true iff it would be profitable to turn a sequence of NOPS loads
14147 or stores (depending on IS_STORE) into a load-multiple or store-multiple
14148 instruction. ADD_OFFSET is nonzero if the base address register needs
14149 to be modified with an add instruction before we can use it. */
14152 multiple_operation_profitable_p (bool is_store ATTRIBUTE_UNUSED
,
14153 int nops
, HOST_WIDE_INT add_offset
)
14155 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
14156 if the offset isn't small enough. The reason 2 ldrs are faster
14157 is because these ARMs are able to do more than one cache access
14158 in a single cycle. The ARM9 and StrongARM have Harvard caches,
14159 whilst the ARM8 has a double bandwidth cache. This means that
14160 these cores can do both an instruction fetch and a data fetch in
14161 a single cycle, so the trick of calculating the address into a
14162 scratch register (one of the result regs) and then doing a load
14163 multiple actually becomes slower (and no smaller in code size).
14164 That is the transformation
14166 ldr rd1, [rbase + offset]
14167 ldr rd2, [rbase + offset + 4]
14171 add rd1, rbase, offset
14172 ldmia rd1, {rd1, rd2}
14174 produces worse code -- '3 cycles + any stalls on rd2' instead of
14175 '2 cycles + any stalls on rd2'. On ARMs with only one cache
14176 access per cycle, the first sequence could never complete in less
14177 than 6 cycles, whereas the ldm sequence would only take 5 and
14178 would make better use of sequential accesses if not hitting the
14181 We cheat here and test 'arm_ld_sched' which we currently know to
14182 only be true for the ARM8, ARM9 and StrongARM. If this ever
14183 changes, then the test below needs to be reworked. */
14184 if (nops
== 2 && arm_ld_sched
&& add_offset
!= 0)
14187 /* XScale has load-store double instructions, but they have stricter
14188 alignment requirements than load-store multiple, so we cannot
14191 For XScale ldm requires 2 + NREGS cycles to complete and blocks
14192 the pipeline until completion.
14200 An ldr instruction takes 1-3 cycles, but does not block the
14209 Best case ldr will always win. However, the more ldr instructions
14210 we issue, the less likely we are to be able to schedule them well.
14211 Using ldr instructions also increases code size.
14213 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
14214 for counts of 3 or 4 regs. */
14215 if (nops
<= 2 && arm_tune_xscale
&& !optimize_size
)
14220 /* Subroutine of load_multiple_sequence and store_multiple_sequence.
14221 Given an array of UNSORTED_OFFSETS, of which there are NOPS, compute
14222 an array ORDER which describes the sequence to use when accessing the
14223 offsets that produces an ascending order. In this sequence, each
14224 offset must be larger by exactly 4 than the previous one. ORDER[0]
14225 must have been filled in with the lowest offset by the caller.
14226 If UNSORTED_REGS is nonnull, it is an array of register numbers that
14227 we use to verify that ORDER produces an ascending order of registers.
14228 Return true if it was possible to construct such an order, false if
14232 compute_offset_order (int nops
, HOST_WIDE_INT
*unsorted_offsets
, int *order
,
14233 int *unsorted_regs
)
14236 for (i
= 1; i
< nops
; i
++)
14240 order
[i
] = order
[i
- 1];
14241 for (j
= 0; j
< nops
; j
++)
14242 if (unsorted_offsets
[j
] == unsorted_offsets
[order
[i
- 1]] + 4)
14244 /* We must find exactly one offset that is higher than the
14245 previous one by 4. */
14246 if (order
[i
] != order
[i
- 1])
14250 if (order
[i
] == order
[i
- 1])
14252 /* The register numbers must be ascending. */
14253 if (unsorted_regs
!= NULL
14254 && unsorted_regs
[order
[i
]] <= unsorted_regs
[order
[i
- 1]])
14260 /* Used to determine in a peephole whether a sequence of load
14261 instructions can be changed into a load-multiple instruction.
14262 NOPS is the number of separate load instructions we are examining. The
14263 first NOPS entries in OPERANDS are the destination registers, the
14264 next NOPS entries are memory operands. If this function is
14265 successful, *BASE is set to the common base register of the memory
14266 accesses; *LOAD_OFFSET is set to the first memory location's offset
14267 from that base register.
14268 REGS is an array filled in with the destination register numbers.
14269 SAVED_ORDER (if nonnull), is an array filled in with an order that maps
14270 insn numbers to an ascending order of stores. If CHECK_REGS is true,
14271 the sequence of registers in REGS matches the loads from ascending memory
14272 locations, and the function verifies that the register numbers are
14273 themselves ascending. If CHECK_REGS is false, the register numbers
14274 are stored in the order they are found in the operands. */
14276 load_multiple_sequence (rtx
*operands
, int nops
, int *regs
, int *saved_order
,
14277 int *base
, HOST_WIDE_INT
*load_offset
, bool check_regs
)
14279 int unsorted_regs
[MAX_LDM_STM_OPS
];
14280 HOST_WIDE_INT unsorted_offsets
[MAX_LDM_STM_OPS
];
14281 int order
[MAX_LDM_STM_OPS
];
14285 /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be
14286 easily extended if required. */
14287 gcc_assert (nops
>= 2 && nops
<= MAX_LDM_STM_OPS
);
14289 memset (order
, 0, MAX_LDM_STM_OPS
* sizeof (int));
14291 /* Loop over the operands and check that the memory references are
14292 suitable (i.e. immediate offsets from the same base register). At
14293 the same time, extract the target register, and the memory
14295 for (i
= 0; i
< nops
; i
++)
14300 /* Convert a subreg of a mem into the mem itself. */
14301 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
14302 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
), true);
14304 gcc_assert (MEM_P (operands
[nops
+ i
]));
14306 /* Don't reorder volatile memory references; it doesn't seem worth
14307 looking for the case where the order is ok anyway. */
14308 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
14311 offset
= const0_rtx
;
14313 if ((REG_P (reg
= XEXP (operands
[nops
+ i
], 0))
14315 && REG_P (reg
= SUBREG_REG (reg
))))
14316 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
14317 && ((REG_P (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0)))
14319 && REG_P (reg
= SUBREG_REG (reg
))))
14320 && (CONST_INT_P (offset
14321 = XEXP (XEXP (operands
[nops
+ i
], 0), 1)))))
14325 base_reg
= REGNO (reg
);
14326 if (TARGET_THUMB1
&& base_reg
> LAST_LO_REGNUM
)
14329 else if (base_reg
!= (int) REGNO (reg
))
14330 /* Not addressed from the same base register. */
14333 unsorted_regs
[i
] = (REG_P (operands
[i
])
14334 ? REGNO (operands
[i
])
14335 : REGNO (SUBREG_REG (operands
[i
])));
14337 /* If it isn't an integer register, or if it overwrites the
14338 base register but isn't the last insn in the list, then
14339 we can't do this. */
14340 if (unsorted_regs
[i
] < 0
14341 || (TARGET_THUMB1
&& unsorted_regs
[i
] > LAST_LO_REGNUM
)
14342 || unsorted_regs
[i
] > 14
14343 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
14346 /* Don't allow SP to be loaded unless it is also the base
14347 register. It guarantees that SP is reset correctly when
14348 an LDM instruction is interrupted. Otherwise, we might
14349 end up with a corrupt stack. */
14350 if (unsorted_regs
[i
] == SP_REGNUM
&& base_reg
!= SP_REGNUM
)
14353 unsorted_offsets
[i
] = INTVAL (offset
);
14354 if (i
== 0 || unsorted_offsets
[i
] < unsorted_offsets
[order
[0]])
14358 /* Not a suitable memory address. */
14362 /* All the useful information has now been extracted from the
14363 operands into unsorted_regs and unsorted_offsets; additionally,
14364 order[0] has been set to the lowest offset in the list. Sort
14365 the offsets into order, verifying that they are adjacent, and
14366 check that the register numbers are ascending. */
14367 if (!compute_offset_order (nops
, unsorted_offsets
, order
,
14368 check_regs
? unsorted_regs
: NULL
))
14372 memcpy (saved_order
, order
, sizeof order
);
14378 for (i
= 0; i
< nops
; i
++)
14379 regs
[i
] = unsorted_regs
[check_regs
? order
[i
] : i
];
14381 *load_offset
= unsorted_offsets
[order
[0]];
14384 if (unsorted_offsets
[order
[0]] == 0)
14385 ldm_case
= 1; /* ldmia */
14386 else if (TARGET_ARM
&& unsorted_offsets
[order
[0]] == 4)
14387 ldm_case
= 2; /* ldmib */
14388 else if (TARGET_ARM
&& unsorted_offsets
[order
[nops
- 1]] == 0)
14389 ldm_case
= 3; /* ldmda */
14390 else if (TARGET_32BIT
&& unsorted_offsets
[order
[nops
- 1]] == -4)
14391 ldm_case
= 4; /* ldmdb */
14392 else if (const_ok_for_arm (unsorted_offsets
[order
[0]])
14393 || const_ok_for_arm (-unsorted_offsets
[order
[0]]))
14398 if (!multiple_operation_profitable_p (false, nops
,
14400 ? unsorted_offsets
[order
[0]] : 0))
14406 /* Used to determine in a peephole whether a sequence of store instructions can
14407 be changed into a store-multiple instruction.
14408 NOPS is the number of separate store instructions we are examining.
14409 NOPS_TOTAL is the total number of instructions recognized by the peephole
14411 The first NOPS entries in OPERANDS are the source registers, the next
14412 NOPS entries are memory operands. If this function is successful, *BASE is
14413 set to the common base register of the memory accesses; *LOAD_OFFSET is set
14414 to the first memory location's offset from that base register. REGS is an
14415 array filled in with the source register numbers, REG_RTXS (if nonnull) is
14416 likewise filled with the corresponding rtx's.
14417 SAVED_ORDER (if nonnull), is an array filled in with an order that maps insn
14418 numbers to an ascending order of stores.
14419 If CHECK_REGS is true, the sequence of registers in *REGS matches the stores
14420 from ascending memory locations, and the function verifies that the register
14421 numbers are themselves ascending. If CHECK_REGS is false, the register
14422 numbers are stored in the order they are found in the operands. */
14424 store_multiple_sequence (rtx
*operands
, int nops
, int nops_total
,
14425 int *regs
, rtx
*reg_rtxs
, int *saved_order
, int *base
,
14426 HOST_WIDE_INT
*load_offset
, bool check_regs
)
14428 int unsorted_regs
[MAX_LDM_STM_OPS
];
14429 rtx unsorted_reg_rtxs
[MAX_LDM_STM_OPS
];
14430 HOST_WIDE_INT unsorted_offsets
[MAX_LDM_STM_OPS
];
14431 int order
[MAX_LDM_STM_OPS
];
14433 rtx base_reg_rtx
= NULL
;
14436 /* Write back of base register is currently only supported for Thumb 1. */
14437 int base_writeback
= TARGET_THUMB1
;
14439 /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be
14440 easily extended if required. */
14441 gcc_assert (nops
>= 2 && nops
<= MAX_LDM_STM_OPS
);
14443 memset (order
, 0, MAX_LDM_STM_OPS
* sizeof (int));
14445 /* Loop over the operands and check that the memory references are
14446 suitable (i.e. immediate offsets from the same base register). At
14447 the same time, extract the target register, and the memory
14449 for (i
= 0; i
< nops
; i
++)
14454 /* Convert a subreg of a mem into the mem itself. */
14455 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
14456 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
), true);
14458 gcc_assert (MEM_P (operands
[nops
+ i
]));
14460 /* Don't reorder volatile memory references; it doesn't seem worth
14461 looking for the case where the order is ok anyway. */
14462 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
14465 offset
= const0_rtx
;
14467 if ((REG_P (reg
= XEXP (operands
[nops
+ i
], 0))
14469 && REG_P (reg
= SUBREG_REG (reg
))))
14470 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
14471 && ((REG_P (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0)))
14473 && REG_P (reg
= SUBREG_REG (reg
))))
14474 && (CONST_INT_P (offset
14475 = XEXP (XEXP (operands
[nops
+ i
], 0), 1)))))
14477 unsorted_reg_rtxs
[i
] = (REG_P (operands
[i
])
14478 ? operands
[i
] : SUBREG_REG (operands
[i
]));
14479 unsorted_regs
[i
] = REGNO (unsorted_reg_rtxs
[i
]);
14483 base_reg
= REGNO (reg
);
14484 base_reg_rtx
= reg
;
14485 if (TARGET_THUMB1
&& base_reg
> LAST_LO_REGNUM
)
14488 else if (base_reg
!= (int) REGNO (reg
))
14489 /* Not addressed from the same base register. */
14492 /* If it isn't an integer register, then we can't do this. */
14493 if (unsorted_regs
[i
] < 0
14494 || (TARGET_THUMB1
&& unsorted_regs
[i
] > LAST_LO_REGNUM
)
14495 /* The effects are unpredictable if the base register is
14496 both updated and stored. */
14497 || (base_writeback
&& unsorted_regs
[i
] == base_reg
)
14498 || (TARGET_THUMB2
&& unsorted_regs
[i
] == SP_REGNUM
)
14499 || unsorted_regs
[i
] > 14)
14502 unsorted_offsets
[i
] = INTVAL (offset
);
14503 if (i
== 0 || unsorted_offsets
[i
] < unsorted_offsets
[order
[0]])
14507 /* Not a suitable memory address. */
14511 /* All the useful information has now been extracted from the
14512 operands into unsorted_regs and unsorted_offsets; additionally,
14513 order[0] has been set to the lowest offset in the list. Sort
14514 the offsets into order, verifying that they are adjacent, and
14515 check that the register numbers are ascending. */
14516 if (!compute_offset_order (nops
, unsorted_offsets
, order
,
14517 check_regs
? unsorted_regs
: NULL
))
14521 memcpy (saved_order
, order
, sizeof order
);
14527 for (i
= 0; i
< nops
; i
++)
14529 regs
[i
] = unsorted_regs
[check_regs
? order
[i
] : i
];
14531 reg_rtxs
[i
] = unsorted_reg_rtxs
[check_regs
? order
[i
] : i
];
14534 *load_offset
= unsorted_offsets
[order
[0]];
14538 && !peep2_reg_dead_p (nops_total
, base_reg_rtx
))
14541 if (unsorted_offsets
[order
[0]] == 0)
14542 stm_case
= 1; /* stmia */
14543 else if (TARGET_ARM
&& unsorted_offsets
[order
[0]] == 4)
14544 stm_case
= 2; /* stmib */
14545 else if (TARGET_ARM
&& unsorted_offsets
[order
[nops
- 1]] == 0)
14546 stm_case
= 3; /* stmda */
14547 else if (TARGET_32BIT
&& unsorted_offsets
[order
[nops
- 1]] == -4)
14548 stm_case
= 4; /* stmdb */
14552 if (!multiple_operation_profitable_p (false, nops
, 0))
14558 /* Routines for use in generating RTL. */
14560 /* Generate a load-multiple instruction. COUNT is the number of loads in
14561 the instruction; REGS and MEMS are arrays containing the operands.
14562 BASEREG is the base register to be used in addressing the memory operands.
14563 WBACK_OFFSET is nonzero if the instruction should update the base
14567 arm_gen_load_multiple_1 (int count
, int *regs
, rtx
*mems
, rtx basereg
,
14568 HOST_WIDE_INT wback_offset
)
14573 if (!multiple_operation_profitable_p (false, count
, 0))
14579 for (i
= 0; i
< count
; i
++)
14580 emit_move_insn (gen_rtx_REG (SImode
, regs
[i
]), mems
[i
]);
14582 if (wback_offset
!= 0)
14583 emit_move_insn (basereg
, plus_constant (Pmode
, basereg
, wback_offset
));
14585 seq
= get_insns ();
14591 result
= gen_rtx_PARALLEL (VOIDmode
,
14592 rtvec_alloc (count
+ (wback_offset
!= 0 ? 1 : 0)));
14593 if (wback_offset
!= 0)
14595 XVECEXP (result
, 0, 0)
14596 = gen_rtx_SET (basereg
, plus_constant (Pmode
, basereg
, wback_offset
));
14601 for (j
= 0; i
< count
; i
++, j
++)
14602 XVECEXP (result
, 0, i
)
14603 = gen_rtx_SET (gen_rtx_REG (SImode
, regs
[j
]), mems
[j
]);
14608 /* Generate a store-multiple instruction. COUNT is the number of stores in
14609 the instruction; REGS and MEMS are arrays containing the operands.
14610 BASEREG is the base register to be used in addressing the memory operands.
14611 WBACK_OFFSET is nonzero if the instruction should update the base
14615 arm_gen_store_multiple_1 (int count
, int *regs
, rtx
*mems
, rtx basereg
,
14616 HOST_WIDE_INT wback_offset
)
14621 if (GET_CODE (basereg
) == PLUS
)
14622 basereg
= XEXP (basereg
, 0);
14624 if (!multiple_operation_profitable_p (false, count
, 0))
14630 for (i
= 0; i
< count
; i
++)
14631 emit_move_insn (mems
[i
], gen_rtx_REG (SImode
, regs
[i
]));
14633 if (wback_offset
!= 0)
14634 emit_move_insn (basereg
, plus_constant (Pmode
, basereg
, wback_offset
));
14636 seq
= get_insns ();
14642 result
= gen_rtx_PARALLEL (VOIDmode
,
14643 rtvec_alloc (count
+ (wback_offset
!= 0 ? 1 : 0)));
14644 if (wback_offset
!= 0)
14646 XVECEXP (result
, 0, 0)
14647 = gen_rtx_SET (basereg
, plus_constant (Pmode
, basereg
, wback_offset
));
14652 for (j
= 0; i
< count
; i
++, j
++)
14653 XVECEXP (result
, 0, i
)
14654 = gen_rtx_SET (mems
[j
], gen_rtx_REG (SImode
, regs
[j
]));
14659 /* Generate either a load-multiple or a store-multiple instruction. This
14660 function can be used in situations where we can start with a single MEM
14661 rtx and adjust its address upwards.
14662 COUNT is the number of operations in the instruction, not counting a
14663 possible update of the base register. REGS is an array containing the
14665 BASEREG is the base register to be used in addressing the memory operands,
14666 which are constructed from BASEMEM.
14667 WRITE_BACK specifies whether the generated instruction should include an
14668 update of the base register.
14669 OFFSETP is used to pass an offset to and from this function; this offset
14670 is not used when constructing the address (instead BASEMEM should have an
14671 appropriate offset in its address), it is used only for setting
14672 MEM_OFFSET. It is updated only if WRITE_BACK is true.*/
14675 arm_gen_multiple_op (bool is_load
, int *regs
, int count
, rtx basereg
,
14676 bool write_back
, rtx basemem
, HOST_WIDE_INT
*offsetp
)
14678 rtx mems
[MAX_LDM_STM_OPS
];
14679 HOST_WIDE_INT offset
= *offsetp
;
14682 gcc_assert (count
<= MAX_LDM_STM_OPS
);
14684 if (GET_CODE (basereg
) == PLUS
)
14685 basereg
= XEXP (basereg
, 0);
14687 for (i
= 0; i
< count
; i
++)
14689 rtx addr
= plus_constant (Pmode
, basereg
, i
* 4);
14690 mems
[i
] = adjust_automodify_address_nv (basemem
, SImode
, addr
, offset
);
14698 return arm_gen_load_multiple_1 (count
, regs
, mems
, basereg
,
14699 write_back
? 4 * count
: 0);
14701 return arm_gen_store_multiple_1 (count
, regs
, mems
, basereg
,
14702 write_back
? 4 * count
: 0);
14706 arm_gen_load_multiple (int *regs
, int count
, rtx basereg
, int write_back
,
14707 rtx basemem
, HOST_WIDE_INT
*offsetp
)
14709 return arm_gen_multiple_op (TRUE
, regs
, count
, basereg
, write_back
, basemem
,
14714 arm_gen_store_multiple (int *regs
, int count
, rtx basereg
, int write_back
,
14715 rtx basemem
, HOST_WIDE_INT
*offsetp
)
14717 return arm_gen_multiple_op (FALSE
, regs
, count
, basereg
, write_back
, basemem
,
14721 /* Called from a peephole2 expander to turn a sequence of loads into an
14722 LDM instruction. OPERANDS are the operands found by the peephole matcher;
14723 NOPS indicates how many separate loads we are trying to combine. SORT_REGS
14724 is true if we can reorder the registers because they are used commutatively
14726 Returns true iff we could generate a new instruction. */
14729 gen_ldm_seq (rtx
*operands
, int nops
, bool sort_regs
)
14731 int regs
[MAX_LDM_STM_OPS
], mem_order
[MAX_LDM_STM_OPS
];
14732 rtx mems
[MAX_LDM_STM_OPS
];
14733 int i
, j
, base_reg
;
14735 HOST_WIDE_INT offset
;
14736 int write_back
= FALSE
;
14740 ldm_case
= load_multiple_sequence (operands
, nops
, regs
, mem_order
,
14741 &base_reg
, &offset
, !sort_regs
);
14747 for (i
= 0; i
< nops
- 1; i
++)
14748 for (j
= i
+ 1; j
< nops
; j
++)
14749 if (regs
[i
] > regs
[j
])
14755 base_reg_rtx
= gen_rtx_REG (Pmode
, base_reg
);
14759 gcc_assert (ldm_case
== 1 || ldm_case
== 5);
14761 /* Thumb-1 ldm uses writeback except if the base is loaded. */
14763 for (i
= 0; i
< nops
; i
++)
14764 if (base_reg
== regs
[i
])
14765 write_back
= false;
14767 /* Ensure the base is dead if it is updated. */
14768 if (write_back
&& !peep2_reg_dead_p (nops
, base_reg_rtx
))
14774 rtx newbase
= TARGET_THUMB1
? base_reg_rtx
: gen_rtx_REG (SImode
, regs
[0]);
14775 emit_insn (gen_addsi3 (newbase
, base_reg_rtx
, GEN_INT (offset
)));
14777 base_reg_rtx
= newbase
;
14780 for (i
= 0; i
< nops
; i
++)
14782 addr
= plus_constant (Pmode
, base_reg_rtx
, offset
+ i
* 4);
14783 mems
[i
] = adjust_automodify_address_nv (operands
[nops
+ mem_order
[i
]],
14786 emit_insn (arm_gen_load_multiple_1 (nops
, regs
, mems
, base_reg_rtx
,
14787 write_back
? offset
+ i
* 4 : 0));
14791 /* Called from a peephole2 expander to turn a sequence of stores into an
14792 STM instruction. OPERANDS are the operands found by the peephole matcher;
14793 NOPS indicates how many separate stores we are trying to combine.
14794 Returns true iff we could generate a new instruction. */
14797 gen_stm_seq (rtx
*operands
, int nops
)
14800 int regs
[MAX_LDM_STM_OPS
], mem_order
[MAX_LDM_STM_OPS
];
14801 rtx mems
[MAX_LDM_STM_OPS
];
14804 HOST_WIDE_INT offset
;
14805 int write_back
= FALSE
;
14808 bool base_reg_dies
;
14810 stm_case
= store_multiple_sequence (operands
, nops
, nops
, regs
, NULL
,
14811 mem_order
, &base_reg
, &offset
, true);
14816 base_reg_rtx
= gen_rtx_REG (Pmode
, base_reg
);
14818 base_reg_dies
= peep2_reg_dead_p (nops
, base_reg_rtx
);
14821 gcc_assert (base_reg_dies
);
14827 gcc_assert (base_reg_dies
);
14828 emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, GEN_INT (offset
)));
14832 addr
= plus_constant (Pmode
, base_reg_rtx
, offset
);
14834 for (i
= 0; i
< nops
; i
++)
14836 addr
= plus_constant (Pmode
, base_reg_rtx
, offset
+ i
* 4);
14837 mems
[i
] = adjust_automodify_address_nv (operands
[nops
+ mem_order
[i
]],
14840 emit_insn (arm_gen_store_multiple_1 (nops
, regs
, mems
, base_reg_rtx
,
14841 write_back
? offset
+ i
* 4 : 0));
14845 /* Called from a peephole2 expander to turn a sequence of stores that are
14846 preceded by constant loads into an STM instruction. OPERANDS are the
14847 operands found by the peephole matcher; NOPS indicates how many
14848 separate stores we are trying to combine; there are 2 * NOPS
14849 instructions in the peephole.
14850 Returns true iff we could generate a new instruction. */
14853 gen_const_stm_seq (rtx
*operands
, int nops
)
14855 int regs
[MAX_LDM_STM_OPS
], sorted_regs
[MAX_LDM_STM_OPS
];
14856 int reg_order
[MAX_LDM_STM_OPS
], mem_order
[MAX_LDM_STM_OPS
];
14857 rtx reg_rtxs
[MAX_LDM_STM_OPS
], orig_reg_rtxs
[MAX_LDM_STM_OPS
];
14858 rtx mems
[MAX_LDM_STM_OPS
];
14861 HOST_WIDE_INT offset
;
14862 int write_back
= FALSE
;
14865 bool base_reg_dies
;
14867 HARD_REG_SET allocated
;
14869 stm_case
= store_multiple_sequence (operands
, nops
, 2 * nops
, regs
, reg_rtxs
,
14870 mem_order
, &base_reg
, &offset
, false);
14875 memcpy (orig_reg_rtxs
, reg_rtxs
, sizeof orig_reg_rtxs
);
14877 /* If the same register is used more than once, try to find a free
14879 CLEAR_HARD_REG_SET (allocated
);
14880 for (i
= 0; i
< nops
; i
++)
14882 for (j
= i
+ 1; j
< nops
; j
++)
14883 if (regs
[i
] == regs
[j
])
14885 rtx t
= peep2_find_free_register (0, nops
* 2,
14886 TARGET_THUMB1
? "l" : "r",
14887 SImode
, &allocated
);
14891 regs
[i
] = REGNO (t
);
14895 /* Compute an ordering that maps the register numbers to an ascending
14898 for (i
= 0; i
< nops
; i
++)
14899 if (regs
[i
] < regs
[reg_order
[0]])
14902 for (i
= 1; i
< nops
; i
++)
14904 int this_order
= reg_order
[i
- 1];
14905 for (j
= 0; j
< nops
; j
++)
14906 if (regs
[j
] > regs
[reg_order
[i
- 1]]
14907 && (this_order
== reg_order
[i
- 1]
14908 || regs
[j
] < regs
[this_order
]))
14910 reg_order
[i
] = this_order
;
14913 /* Ensure that registers that must be live after the instruction end
14914 up with the correct value. */
14915 for (i
= 0; i
< nops
; i
++)
14917 int this_order
= reg_order
[i
];
14918 if ((this_order
!= mem_order
[i
]
14919 || orig_reg_rtxs
[this_order
] != reg_rtxs
[this_order
])
14920 && !peep2_reg_dead_p (nops
* 2, orig_reg_rtxs
[this_order
]))
14924 /* Load the constants. */
14925 for (i
= 0; i
< nops
; i
++)
14927 rtx op
= operands
[2 * nops
+ mem_order
[i
]];
14928 sorted_regs
[i
] = regs
[reg_order
[i
]];
14929 emit_move_insn (reg_rtxs
[reg_order
[i
]], op
);
14932 base_reg_rtx
= gen_rtx_REG (Pmode
, base_reg
);
14934 base_reg_dies
= peep2_reg_dead_p (nops
* 2, base_reg_rtx
);
14937 gcc_assert (base_reg_dies
);
14943 gcc_assert (base_reg_dies
);
14944 emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, GEN_INT (offset
)));
14948 addr
= plus_constant (Pmode
, base_reg_rtx
, offset
);
14950 for (i
= 0; i
< nops
; i
++)
14952 addr
= plus_constant (Pmode
, base_reg_rtx
, offset
+ i
* 4);
14953 mems
[i
] = adjust_automodify_address_nv (operands
[nops
+ mem_order
[i
]],
14956 emit_insn (arm_gen_store_multiple_1 (nops
, sorted_regs
, mems
, base_reg_rtx
,
14957 write_back
? offset
+ i
* 4 : 0));
14961 /* Copy a block of memory using plain ldr/str/ldrh/strh instructions, to permit
14962 unaligned copies on processors which support unaligned semantics for those
14963 instructions. INTERLEAVE_FACTOR can be used to attempt to hide load latency
14964 (using more registers) by doing e.g. load/load/store/store for a factor of 2.
14965 An interleave factor of 1 (the minimum) will perform no interleaving.
14966 Load/store multiple are used for aligned addresses where possible. */
14969 arm_block_move_unaligned_straight (rtx dstbase
, rtx srcbase
,
14970 HOST_WIDE_INT length
,
14971 unsigned int interleave_factor
)
14973 rtx
*regs
= XALLOCAVEC (rtx
, interleave_factor
);
14974 int *regnos
= XALLOCAVEC (int, interleave_factor
);
14975 HOST_WIDE_INT block_size_bytes
= interleave_factor
* UNITS_PER_WORD
;
14976 HOST_WIDE_INT i
, j
;
14977 HOST_WIDE_INT remaining
= length
, words
;
14978 rtx halfword_tmp
= NULL
, byte_tmp
= NULL
;
14980 bool src_aligned
= MEM_ALIGN (srcbase
) >= BITS_PER_WORD
;
14981 bool dst_aligned
= MEM_ALIGN (dstbase
) >= BITS_PER_WORD
;
14982 HOST_WIDE_INT srcoffset
, dstoffset
;
14983 HOST_WIDE_INT src_autoinc
, dst_autoinc
;
14986 gcc_assert (interleave_factor
>= 1 && interleave_factor
<= 4);
14988 /* Use hard registers if we have aligned source or destination so we can use
14989 load/store multiple with contiguous registers. */
14990 if (dst_aligned
|| src_aligned
)
14991 for (i
= 0; i
< interleave_factor
; i
++)
14992 regs
[i
] = gen_rtx_REG (SImode
, i
);
14994 for (i
= 0; i
< interleave_factor
; i
++)
14995 regs
[i
] = gen_reg_rtx (SImode
);
14997 dst
= copy_addr_to_reg (XEXP (dstbase
, 0));
14998 src
= copy_addr_to_reg (XEXP (srcbase
, 0));
15000 srcoffset
= dstoffset
= 0;
15002 /* Calls to arm_gen_load_multiple and arm_gen_store_multiple update SRC/DST.
15003 For copying the last bytes we want to subtract this offset again. */
15004 src_autoinc
= dst_autoinc
= 0;
15006 for (i
= 0; i
< interleave_factor
; i
++)
15009 /* Copy BLOCK_SIZE_BYTES chunks. */
15011 for (i
= 0; i
+ block_size_bytes
<= length
; i
+= block_size_bytes
)
15014 if (src_aligned
&& interleave_factor
> 1)
15016 emit_insn (arm_gen_load_multiple (regnos
, interleave_factor
, src
,
15017 TRUE
, srcbase
, &srcoffset
));
15018 src_autoinc
+= UNITS_PER_WORD
* interleave_factor
;
15022 for (j
= 0; j
< interleave_factor
; j
++)
15024 addr
= plus_constant (Pmode
, src
, (srcoffset
+ j
* UNITS_PER_WORD
15026 mem
= adjust_automodify_address (srcbase
, SImode
, addr
,
15027 srcoffset
+ j
* UNITS_PER_WORD
);
15028 emit_insn (gen_unaligned_loadsi (regs
[j
], mem
));
15030 srcoffset
+= block_size_bytes
;
15034 if (dst_aligned
&& interleave_factor
> 1)
15036 emit_insn (arm_gen_store_multiple (regnos
, interleave_factor
, dst
,
15037 TRUE
, dstbase
, &dstoffset
));
15038 dst_autoinc
+= UNITS_PER_WORD
* interleave_factor
;
15042 for (j
= 0; j
< interleave_factor
; j
++)
15044 addr
= plus_constant (Pmode
, dst
, (dstoffset
+ j
* UNITS_PER_WORD
15046 mem
= adjust_automodify_address (dstbase
, SImode
, addr
,
15047 dstoffset
+ j
* UNITS_PER_WORD
);
15048 emit_insn (gen_unaligned_storesi (mem
, regs
[j
]));
15050 dstoffset
+= block_size_bytes
;
15053 remaining
-= block_size_bytes
;
15056 /* Copy any whole words left (note these aren't interleaved with any
15057 subsequent halfword/byte load/stores in the interests of simplicity). */
15059 words
= remaining
/ UNITS_PER_WORD
;
15061 gcc_assert (words
< interleave_factor
);
15063 if (src_aligned
&& words
> 1)
15065 emit_insn (arm_gen_load_multiple (regnos
, words
, src
, TRUE
, srcbase
,
15067 src_autoinc
+= UNITS_PER_WORD
* words
;
15071 for (j
= 0; j
< words
; j
++)
15073 addr
= plus_constant (Pmode
, src
,
15074 srcoffset
+ j
* UNITS_PER_WORD
- src_autoinc
);
15075 mem
= adjust_automodify_address (srcbase
, SImode
, addr
,
15076 srcoffset
+ j
* UNITS_PER_WORD
);
15078 emit_move_insn (regs
[j
], mem
);
15080 emit_insn (gen_unaligned_loadsi (regs
[j
], mem
));
15082 srcoffset
+= words
* UNITS_PER_WORD
;
15085 if (dst_aligned
&& words
> 1)
15087 emit_insn (arm_gen_store_multiple (regnos
, words
, dst
, TRUE
, dstbase
,
15089 dst_autoinc
+= words
* UNITS_PER_WORD
;
15093 for (j
= 0; j
< words
; j
++)
15095 addr
= plus_constant (Pmode
, dst
,
15096 dstoffset
+ j
* UNITS_PER_WORD
- dst_autoinc
);
15097 mem
= adjust_automodify_address (dstbase
, SImode
, addr
,
15098 dstoffset
+ j
* UNITS_PER_WORD
);
15100 emit_move_insn (mem
, regs
[j
]);
15102 emit_insn (gen_unaligned_storesi (mem
, regs
[j
]));
15104 dstoffset
+= words
* UNITS_PER_WORD
;
15107 remaining
-= words
* UNITS_PER_WORD
;
15109 gcc_assert (remaining
< 4);
15111 /* Copy a halfword if necessary. */
15113 if (remaining
>= 2)
15115 halfword_tmp
= gen_reg_rtx (SImode
);
15117 addr
= plus_constant (Pmode
, src
, srcoffset
- src_autoinc
);
15118 mem
= adjust_automodify_address (srcbase
, HImode
, addr
, srcoffset
);
15119 emit_insn (gen_unaligned_loadhiu (halfword_tmp
, mem
));
15121 /* Either write out immediately, or delay until we've loaded the last
15122 byte, depending on interleave factor. */
15123 if (interleave_factor
== 1)
15125 addr
= plus_constant (Pmode
, dst
, dstoffset
- dst_autoinc
);
15126 mem
= adjust_automodify_address (dstbase
, HImode
, addr
, dstoffset
);
15127 emit_insn (gen_unaligned_storehi (mem
,
15128 gen_lowpart (HImode
, halfword_tmp
)));
15129 halfword_tmp
= NULL
;
15137 gcc_assert (remaining
< 2);
15139 /* Copy last byte. */
15141 if ((remaining
& 1) != 0)
15143 byte_tmp
= gen_reg_rtx (SImode
);
15145 addr
= plus_constant (Pmode
, src
, srcoffset
- src_autoinc
);
15146 mem
= adjust_automodify_address (srcbase
, QImode
, addr
, srcoffset
);
15147 emit_move_insn (gen_lowpart (QImode
, byte_tmp
), mem
);
15149 if (interleave_factor
== 1)
15151 addr
= plus_constant (Pmode
, dst
, dstoffset
- dst_autoinc
);
15152 mem
= adjust_automodify_address (dstbase
, QImode
, addr
, dstoffset
);
15153 emit_move_insn (mem
, gen_lowpart (QImode
, byte_tmp
));
15162 /* Store last halfword if we haven't done so already. */
15166 addr
= plus_constant (Pmode
, dst
, dstoffset
- dst_autoinc
);
15167 mem
= adjust_automodify_address (dstbase
, HImode
, addr
, dstoffset
);
15168 emit_insn (gen_unaligned_storehi (mem
,
15169 gen_lowpart (HImode
, halfword_tmp
)));
15173 /* Likewise for last byte. */
15177 addr
= plus_constant (Pmode
, dst
, dstoffset
- dst_autoinc
);
15178 mem
= adjust_automodify_address (dstbase
, QImode
, addr
, dstoffset
);
15179 emit_move_insn (mem
, gen_lowpart (QImode
, byte_tmp
));
15183 gcc_assert (remaining
== 0 && srcoffset
== dstoffset
);
15186 /* From mips_adjust_block_mem:
15188 Helper function for doing a loop-based block operation on memory
15189 reference MEM. Each iteration of the loop will operate on LENGTH
15192 Create a new base register for use within the loop and point it to
15193 the start of MEM. Create a new memory reference that uses this
15194 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
15197 arm_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
, rtx
*loop_reg
,
15200 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
15202 /* Although the new mem does not refer to a known location,
15203 it does keep up to LENGTH bytes of alignment. */
15204 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
15205 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
15208 /* From mips_block_move_loop:
15210 Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
15211 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
15212 the memory regions do not overlap. */
15215 arm_block_move_unaligned_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
15216 unsigned int interleave_factor
,
15217 HOST_WIDE_INT bytes_per_iter
)
15219 rtx src_reg
, dest_reg
, final_src
, test
;
15220 HOST_WIDE_INT leftover
;
15222 leftover
= length
% bytes_per_iter
;
15223 length
-= leftover
;
15225 /* Create registers and memory references for use within the loop. */
15226 arm_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
15227 arm_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
15229 /* Calculate the value that SRC_REG should have after the last iteration of
15231 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
15232 0, 0, OPTAB_WIDEN
);
15234 /* Emit the start of the loop. */
15235 rtx_code_label
*label
= gen_label_rtx ();
15236 emit_label (label
);
15238 /* Emit the loop body. */
15239 arm_block_move_unaligned_straight (dest
, src
, bytes_per_iter
,
15240 interleave_factor
);
15242 /* Move on to the next block. */
15243 emit_move_insn (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
15244 emit_move_insn (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
15246 /* Emit the loop condition. */
15247 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
15248 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
15250 /* Mop up any left-over bytes. */
15252 arm_block_move_unaligned_straight (dest
, src
, leftover
, interleave_factor
);
15255 /* Emit a block move when either the source or destination is unaligned (not
15256 aligned to a four-byte boundary). This may need further tuning depending on
15257 core type, optimize_size setting, etc. */
15260 arm_cpymemqi_unaligned (rtx
*operands
)
15262 HOST_WIDE_INT length
= INTVAL (operands
[2]);
15266 bool src_aligned
= MEM_ALIGN (operands
[1]) >= BITS_PER_WORD
;
15267 bool dst_aligned
= MEM_ALIGN (operands
[0]) >= BITS_PER_WORD
;
15268 /* Inlined memcpy using ldr/str/ldrh/strh can be quite big: try to limit
15269 size of code if optimizing for size. We'll use ldm/stm if src_aligned
15270 or dst_aligned though: allow more interleaving in those cases since the
15271 resulting code can be smaller. */
15272 unsigned int interleave_factor
= (src_aligned
|| dst_aligned
) ? 2 : 1;
15273 HOST_WIDE_INT bytes_per_iter
= (src_aligned
|| dst_aligned
) ? 8 : 4;
15276 arm_block_move_unaligned_loop (operands
[0], operands
[1], length
,
15277 interleave_factor
, bytes_per_iter
);
15279 arm_block_move_unaligned_straight (operands
[0], operands
[1], length
,
15280 interleave_factor
);
15284 /* Note that the loop created by arm_block_move_unaligned_loop may be
15285 subject to loop unrolling, which makes tuning this condition a little
15288 arm_block_move_unaligned_loop (operands
[0], operands
[1], length
, 4, 16);
15290 arm_block_move_unaligned_straight (operands
[0], operands
[1], length
, 4);
15297 arm_gen_cpymemqi (rtx
*operands
)
15299 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
15300 HOST_WIDE_INT srcoffset
, dstoffset
;
15301 rtx src
, dst
, srcbase
, dstbase
;
15302 rtx part_bytes_reg
= NULL
;
15305 if (!CONST_INT_P (operands
[2])
15306 || !CONST_INT_P (operands
[3])
15307 || INTVAL (operands
[2]) > 64)
15310 if (unaligned_access
&& (INTVAL (operands
[3]) & 3) != 0)
15311 return arm_cpymemqi_unaligned (operands
);
15313 if (INTVAL (operands
[3]) & 3)
15316 dstbase
= operands
[0];
15317 srcbase
= operands
[1];
15319 dst
= copy_to_mode_reg (SImode
, XEXP (dstbase
, 0));
15320 src
= copy_to_mode_reg (SImode
, XEXP (srcbase
, 0));
15322 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
15323 out_words_to_go
= INTVAL (operands
[2]) / 4;
15324 last_bytes
= INTVAL (operands
[2]) & 3;
15325 dstoffset
= srcoffset
= 0;
15327 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
15328 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
15330 while (in_words_to_go
>= 2)
15332 if (in_words_to_go
> 4)
15333 emit_insn (arm_gen_load_multiple (arm_regs_in_sequence
, 4, src
,
15334 TRUE
, srcbase
, &srcoffset
));
15336 emit_insn (arm_gen_load_multiple (arm_regs_in_sequence
, in_words_to_go
,
15337 src
, FALSE
, srcbase
,
15340 if (out_words_to_go
)
15342 if (out_words_to_go
> 4)
15343 emit_insn (arm_gen_store_multiple (arm_regs_in_sequence
, 4, dst
,
15344 TRUE
, dstbase
, &dstoffset
));
15345 else if (out_words_to_go
!= 1)
15346 emit_insn (arm_gen_store_multiple (arm_regs_in_sequence
,
15347 out_words_to_go
, dst
,
15350 dstbase
, &dstoffset
));
15353 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
15354 emit_move_insn (mem
, gen_rtx_REG (SImode
, R0_REGNUM
));
15355 if (last_bytes
!= 0)
15357 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
15363 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
15364 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
15367 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
15368 if (out_words_to_go
)
15372 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
15373 sreg
= copy_to_reg (mem
);
15375 mem
= adjust_automodify_address (dstbase
, SImode
, dst
, dstoffset
);
15376 emit_move_insn (mem
, sreg
);
15379 gcc_assert (!in_words_to_go
); /* Sanity check */
15382 if (in_words_to_go
)
15384 gcc_assert (in_words_to_go
> 0);
15386 mem
= adjust_automodify_address (srcbase
, SImode
, src
, srcoffset
);
15387 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
15390 gcc_assert (!last_bytes
|| part_bytes_reg
);
15392 if (BYTES_BIG_ENDIAN
&& last_bytes
)
15394 rtx tmp
= gen_reg_rtx (SImode
);
15396 /* The bytes we want are in the top end of the word. */
15397 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
15398 GEN_INT (8 * (4 - last_bytes
))));
15399 part_bytes_reg
= tmp
;
15403 mem
= adjust_automodify_address (dstbase
, QImode
,
15404 plus_constant (Pmode
, dst
,
15406 dstoffset
+ last_bytes
- 1);
15407 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
15411 tmp
= gen_reg_rtx (SImode
);
15412 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
15413 part_bytes_reg
= tmp
;
15420 if (last_bytes
> 1)
15422 mem
= adjust_automodify_address (dstbase
, HImode
, dst
, dstoffset
);
15423 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
15427 rtx tmp
= gen_reg_rtx (SImode
);
15428 emit_insn (gen_addsi3 (dst
, dst
, const2_rtx
));
15429 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
15430 part_bytes_reg
= tmp
;
15437 mem
= adjust_automodify_address (dstbase
, QImode
, dst
, dstoffset
);
15438 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
15445 /* Helper for gen_cpymem_ldrd_strd. Increase the address of memory rtx
15448 next_consecutive_mem (rtx mem
)
15450 machine_mode mode
= GET_MODE (mem
);
15451 HOST_WIDE_INT offset
= GET_MODE_SIZE (mode
);
15452 rtx addr
= plus_constant (Pmode
, XEXP (mem
, 0), offset
);
15454 return adjust_automodify_address (mem
, mode
, addr
, offset
);
15457 /* Copy using LDRD/STRD instructions whenever possible.
15458 Returns true upon success. */
15460 gen_cpymem_ldrd_strd (rtx
*operands
)
15462 unsigned HOST_WIDE_INT len
;
15463 HOST_WIDE_INT align
;
15464 rtx src
, dst
, base
;
15466 bool src_aligned
, dst_aligned
;
15467 bool src_volatile
, dst_volatile
;
15469 gcc_assert (CONST_INT_P (operands
[2]));
15470 gcc_assert (CONST_INT_P (operands
[3]));
15472 len
= UINTVAL (operands
[2]);
15476 /* Maximum alignment we can assume for both src and dst buffers. */
15477 align
= INTVAL (operands
[3]);
15479 if ((!unaligned_access
) && (len
>= 4) && ((align
& 3) != 0))
15482 /* Place src and dst addresses in registers
15483 and update the corresponding mem rtx. */
15485 dst_volatile
= MEM_VOLATILE_P (dst
);
15486 dst_aligned
= MEM_ALIGN (dst
) >= BITS_PER_WORD
;
15487 base
= copy_to_mode_reg (SImode
, XEXP (dst
, 0));
15488 dst
= adjust_automodify_address (dst
, VOIDmode
, base
, 0);
15491 src_volatile
= MEM_VOLATILE_P (src
);
15492 src_aligned
= MEM_ALIGN (src
) >= BITS_PER_WORD
;
15493 base
= copy_to_mode_reg (SImode
, XEXP (src
, 0));
15494 src
= adjust_automodify_address (src
, VOIDmode
, base
, 0);
15496 if (!unaligned_access
&& !(src_aligned
&& dst_aligned
))
15499 if (src_volatile
|| dst_volatile
)
15502 /* If we cannot generate any LDRD/STRD, try to generate LDM/STM. */
15503 if (!(dst_aligned
|| src_aligned
))
15504 return arm_gen_cpymemqi (operands
);
15506 /* If the either src or dst is unaligned we'll be accessing it as pairs
15507 of unaligned SImode accesses. Otherwise we can generate DImode
15508 ldrd/strd instructions. */
15509 src
= adjust_address (src
, src_aligned
? DImode
: SImode
, 0);
15510 dst
= adjust_address (dst
, dst_aligned
? DImode
: SImode
, 0);
15515 reg0
= gen_reg_rtx (DImode
);
15516 rtx low_reg
= NULL_RTX
;
15517 rtx hi_reg
= NULL_RTX
;
15519 if (!src_aligned
|| !dst_aligned
)
15521 low_reg
= gen_lowpart (SImode
, reg0
);
15522 hi_reg
= gen_highpart_mode (SImode
, DImode
, reg0
);
15524 if (MEM_ALIGN (src
) >= 2 * BITS_PER_WORD
)
15525 emit_move_insn (reg0
, src
);
15526 else if (src_aligned
)
15527 emit_insn (gen_unaligned_loaddi (reg0
, src
));
15530 emit_insn (gen_unaligned_loadsi (low_reg
, src
));
15531 src
= next_consecutive_mem (src
);
15532 emit_insn (gen_unaligned_loadsi (hi_reg
, src
));
15535 if (MEM_ALIGN (dst
) >= 2 * BITS_PER_WORD
)
15536 emit_move_insn (dst
, reg0
);
15537 else if (dst_aligned
)
15538 emit_insn (gen_unaligned_storedi (dst
, reg0
));
15541 emit_insn (gen_unaligned_storesi (dst
, low_reg
));
15542 dst
= next_consecutive_mem (dst
);
15543 emit_insn (gen_unaligned_storesi (dst
, hi_reg
));
15546 src
= next_consecutive_mem (src
);
15547 dst
= next_consecutive_mem (dst
);
15550 gcc_assert (len
< 8);
15553 /* More than a word but less than a double-word to copy. Copy a word. */
15554 reg0
= gen_reg_rtx (SImode
);
15555 src
= adjust_address (src
, SImode
, 0);
15556 dst
= adjust_address (dst
, SImode
, 0);
15558 emit_move_insn (reg0
, src
);
15560 emit_insn (gen_unaligned_loadsi (reg0
, src
));
15563 emit_move_insn (dst
, reg0
);
15565 emit_insn (gen_unaligned_storesi (dst
, reg0
));
15567 src
= next_consecutive_mem (src
);
15568 dst
= next_consecutive_mem (dst
);
15575 /* Copy the remaining bytes. */
15578 dst
= adjust_address (dst
, HImode
, 0);
15579 src
= adjust_address (src
, HImode
, 0);
15580 reg0
= gen_reg_rtx (SImode
);
15582 emit_insn (gen_zero_extendhisi2 (reg0
, src
));
15584 emit_insn (gen_unaligned_loadhiu (reg0
, src
));
15587 emit_insn (gen_movhi (dst
, gen_lowpart(HImode
, reg0
)));
15589 emit_insn (gen_unaligned_storehi (dst
, gen_lowpart (HImode
, reg0
)));
15591 src
= next_consecutive_mem (src
);
15592 dst
= next_consecutive_mem (dst
);
15597 dst
= adjust_address (dst
, QImode
, 0);
15598 src
= adjust_address (src
, QImode
, 0);
15599 reg0
= gen_reg_rtx (QImode
);
15600 emit_move_insn (reg0
, src
);
15601 emit_move_insn (dst
, reg0
);
15605 /* Decompose operands for a 64-bit binary operation in OP1 and OP2
15606 into its component 32-bit subregs. OP2 may be an immediate
15607 constant and we want to simplify it in that case. */
15609 arm_decompose_di_binop (rtx op1
, rtx op2
, rtx
*lo_op1
, rtx
*hi_op1
,
15610 rtx
*lo_op2
, rtx
*hi_op2
)
15612 *lo_op1
= gen_lowpart (SImode
, op1
);
15613 *hi_op1
= gen_highpart (SImode
, op1
);
15614 *lo_op2
= simplify_gen_subreg (SImode
, op2
, DImode
,
15615 subreg_lowpart_offset (SImode
, DImode
));
15616 *hi_op2
= simplify_gen_subreg (SImode
, op2
, DImode
,
15617 subreg_highpart_offset (SImode
, DImode
));
15620 /* Select a dominance comparison mode if possible for a test of the general
15621 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
15622 COND_OR == DOM_CC_X_AND_Y => (X && Y)
15623 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
15624 COND_OR == DOM_CC_X_OR_Y => (X || Y)
15625 In all cases OP will be either EQ or NE, but we don't need to know which
15626 here. If we are unable to support a dominance comparison we return
15627 CC mode. This will then fail to match for the RTL expressions that
15628 generate this call. */
15630 arm_select_dominance_cc_mode (rtx x
, rtx y
, HOST_WIDE_INT cond_or
)
15632 enum rtx_code cond1
, cond2
;
15635 /* Currently we will probably get the wrong result if the individual
15636 comparisons are not simple. This also ensures that it is safe to
15637 reverse a comparison if necessary. */
15638 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
15640 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
15644 /* The if_then_else variant of this tests the second condition if the
15645 first passes, but is true if the first fails. Reverse the first
15646 condition to get a true "inclusive-or" expression. */
15647 if (cond_or
== DOM_CC_NX_OR_Y
)
15648 cond1
= reverse_condition (cond1
);
15650 /* If the comparisons are not equal, and one doesn't dominate the other,
15651 then we can't do this. */
15653 && !comparison_dominates_p (cond1
, cond2
)
15654 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
15658 std::swap (cond1
, cond2
);
15663 if (cond_or
== DOM_CC_X_AND_Y
)
15668 case EQ
: return CC_DEQmode
;
15669 case LE
: return CC_DLEmode
;
15670 case LEU
: return CC_DLEUmode
;
15671 case GE
: return CC_DGEmode
;
15672 case GEU
: return CC_DGEUmode
;
15673 default: gcc_unreachable ();
15677 if (cond_or
== DOM_CC_X_AND_Y
)
15689 gcc_unreachable ();
15693 if (cond_or
== DOM_CC_X_AND_Y
)
15705 gcc_unreachable ();
15709 if (cond_or
== DOM_CC_X_AND_Y
)
15710 return CC_DLTUmode
;
15715 return CC_DLTUmode
;
15717 return CC_DLEUmode
;
15721 gcc_unreachable ();
15725 if (cond_or
== DOM_CC_X_AND_Y
)
15726 return CC_DGTUmode
;
15731 return CC_DGTUmode
;
15733 return CC_DGEUmode
;
15737 gcc_unreachable ();
15740 /* The remaining cases only occur when both comparisons are the
15743 gcc_assert (cond1
== cond2
);
15747 gcc_assert (cond1
== cond2
);
15751 gcc_assert (cond1
== cond2
);
15755 gcc_assert (cond1
== cond2
);
15756 return CC_DLEUmode
;
15759 gcc_assert (cond1
== cond2
);
15760 return CC_DGEUmode
;
15763 gcc_unreachable ();
15768 arm_select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
15770 /* All floating point compares return CCFP if it is an equality
15771 comparison, and CCFPE otherwise. */
15772 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
15795 gcc_unreachable ();
15799 /* A compare with a shifted operand. Because of canonicalization, the
15800 comparison will have to be swapped when we emit the assembler. */
15801 if (GET_MODE (y
) == SImode
15802 && (REG_P (y
) || (SUBREG_P (y
)))
15803 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
15804 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
15805 || GET_CODE (x
) == ROTATERT
))
15808 /* A widened compare of the sum of a value plus a carry against a
15809 constant. This is a representation of RSC. We want to swap the
15810 result of the comparison at output. Not valid if the Z bit is
15812 if (GET_MODE (x
) == DImode
15813 && GET_CODE (x
) == PLUS
15814 && arm_borrow_operation (XEXP (x
, 1), DImode
)
15816 && ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
15817 && (op
== LE
|| op
== GT
))
15818 || (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
15819 && (op
== LEU
|| op
== GTU
))))
15822 /* If X is a constant we want to use CC_RSBmode. This is
15823 non-canonical, but arm_gen_compare_reg uses this to generate the
15824 correct canonical form. */
15825 if (GET_MODE (y
) == SImode
15826 && (REG_P (y
) || SUBREG_P (y
))
15827 && CONST_INT_P (x
))
15830 /* This operation is performed swapped, but since we only rely on the Z
15831 flag we don't need an additional mode. */
15832 if (GET_MODE (y
) == SImode
15833 && (REG_P (y
) || (SUBREG_P (y
)))
15834 && GET_CODE (x
) == NEG
15835 && (op
== EQ
|| op
== NE
))
15838 /* This is a special case that is used by combine to allow a
15839 comparison of a shifted byte load to be split into a zero-extend
15840 followed by a comparison of the shifted integer (only valid for
15841 equalities and unsigned inequalities). */
15842 if (GET_MODE (x
) == SImode
15843 && GET_CODE (x
) == ASHIFT
15844 && CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) == 24
15845 && GET_CODE (XEXP (x
, 0)) == SUBREG
15846 && MEM_P (SUBREG_REG (XEXP (x
, 0)))
15847 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
15848 && (op
== EQ
|| op
== NE
15849 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
15850 && CONST_INT_P (y
))
15853 /* A construct for a conditional compare, if the false arm contains
15854 0, then both conditions must be true, otherwise either condition
15855 must be true. Not all conditions are possible, so CCmode is
15856 returned if it can't be done. */
15857 if (GET_CODE (x
) == IF_THEN_ELSE
15858 && (XEXP (x
, 2) == const0_rtx
15859 || XEXP (x
, 2) == const1_rtx
)
15860 && COMPARISON_P (XEXP (x
, 0))
15861 && COMPARISON_P (XEXP (x
, 1)))
15862 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
15863 INTVAL (XEXP (x
, 2)));
15865 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
15866 if (GET_CODE (x
) == AND
15867 && (op
== EQ
|| op
== NE
)
15868 && COMPARISON_P (XEXP (x
, 0))
15869 && COMPARISON_P (XEXP (x
, 1)))
15870 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
15873 if (GET_CODE (x
) == IOR
15874 && (op
== EQ
|| op
== NE
)
15875 && COMPARISON_P (XEXP (x
, 0))
15876 && COMPARISON_P (XEXP (x
, 1)))
15877 return arm_select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
15880 /* An operation (on Thumb) where we want to test for a single bit.
15881 This is done by shifting that bit up into the top bit of a
15882 scratch register; we can then branch on the sign bit. */
15884 && GET_MODE (x
) == SImode
15885 && (op
== EQ
|| op
== NE
)
15886 && GET_CODE (x
) == ZERO_EXTRACT
15887 && XEXP (x
, 1) == const1_rtx
)
15890 /* An operation that sets the condition codes as a side-effect, the
15891 V flag is not set correctly, so we can only use comparisons where
15892 this doesn't matter. (For LT and GE we can use "mi" and "pl"
15894 /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */
15895 if (GET_MODE (x
) == SImode
15897 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
15898 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
15899 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
15900 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
15901 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
15902 || GET_CODE (x
) == LSHIFTRT
15903 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
15904 || GET_CODE (x
) == ROTATERT
15905 || (TARGET_32BIT
&& GET_CODE (x
) == ZERO_EXTRACT
)))
15908 /* A comparison of ~reg with a const is really a special
15909 canoncialization of compare (~const, reg), which is a reverse
15910 subtract operation. We may not get here if CONST is 0, but that
15911 doesn't matter because ~0 isn't a valid immediate for RSB. */
15912 if (GET_MODE (x
) == SImode
15913 && GET_CODE (x
) == NOT
15914 && CONST_INT_P (y
))
15917 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
15920 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
15921 && GET_CODE (x
) == PLUS
15922 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
15925 if (GET_MODE (x
) == DImode
15926 && GET_CODE (x
) == PLUS
15927 && GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
15929 && UINTVAL (y
) == 0x800000000
15930 && (op
== GEU
|| op
== LTU
))
15933 if (GET_MODE (x
) == DImode
15934 && (op
== GE
|| op
== LT
)
15935 && GET_CODE (x
) == SIGN_EXTEND
15936 && ((GET_CODE (y
) == PLUS
15937 && arm_borrow_operation (XEXP (y
, 0), DImode
))
15938 || arm_borrow_operation (y
, DImode
)))
15941 if (GET_MODE (x
) == DImode
15942 && (op
== GEU
|| op
== LTU
)
15943 && GET_CODE (x
) == ZERO_EXTEND
15944 && ((GET_CODE (y
) == PLUS
15945 && arm_borrow_operation (XEXP (y
, 0), DImode
))
15946 || arm_borrow_operation (y
, DImode
)))
15949 if (GET_MODE (x
) == DImode
15950 && (op
== EQ
|| op
== NE
)
15951 && (GET_CODE (x
) == PLUS
15952 || GET_CODE (x
) == MINUS
)
15953 && (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
15954 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
15955 && GET_CODE (y
) == SIGN_EXTEND
15956 && GET_CODE (XEXP (y
, 0)) == GET_CODE (x
))
15959 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
15960 return GET_MODE (x
);
15965 /* X and Y are two (DImode) things to compare for the condition CODE. Emit
15966 the sequence of instructions needed to generate a suitable condition
15967 code register. Return the CC register result. */
15969 arm_gen_dicompare_reg (rtx_code code
, rtx x
, rtx y
, rtx scratch
)
15974 /* We don't currently handle DImode in thumb1, but rely on libgcc. */
15975 gcc_assert (TARGET_32BIT
);
15976 gcc_assert (!CONST_INT_P (x
));
15978 rtx x_lo
= simplify_gen_subreg (SImode
, x
, DImode
,
15979 subreg_lowpart_offset (SImode
, DImode
));
15980 rtx x_hi
= simplify_gen_subreg (SImode
, x
, DImode
,
15981 subreg_highpart_offset (SImode
, DImode
));
15982 rtx y_lo
= simplify_gen_subreg (SImode
, y
, DImode
,
15983 subreg_lowpart_offset (SImode
, DImode
));
15984 rtx y_hi
= simplify_gen_subreg (SImode
, y
, DImode
,
15985 subreg_highpart_offset (SImode
, DImode
));
15991 if (y_lo
== const0_rtx
|| y_hi
== const0_rtx
)
15993 if (y_lo
!= const0_rtx
)
15995 rtx scratch2
= scratch
? scratch
: gen_reg_rtx (SImode
);
15997 gcc_assert (y_hi
== const0_rtx
);
15998 y_lo
= gen_int_mode (-INTVAL (y_lo
), SImode
);
15999 if (!arm_add_operand (y_lo
, SImode
))
16000 y_lo
= force_reg (SImode
, y_lo
);
16001 emit_insn (gen_addsi3 (scratch2
, x_lo
, y_lo
));
16004 else if (y_hi
!= const0_rtx
)
16006 rtx scratch2
= scratch
? scratch
: gen_reg_rtx (SImode
);
16008 y_hi
= gen_int_mode (-INTVAL (y_hi
), SImode
);
16009 if (!arm_add_operand (y_hi
, SImode
))
16010 y_hi
= force_reg (SImode
, y_hi
);
16011 emit_insn (gen_addsi3 (scratch2
, x_hi
, y_hi
));
16017 gcc_assert (!reload_completed
);
16018 scratch
= gen_rtx_SCRATCH (SImode
);
16021 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
16022 cc_reg
= gen_rtx_REG (CC_NZmode
, CC_REGNUM
);
16025 = gen_rtx_SET (cc_reg
,
16026 gen_rtx_COMPARE (CC_NZmode
,
16027 gen_rtx_IOR (SImode
, x_lo
, x_hi
),
16029 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
,
16034 if (!arm_add_operand (y_lo
, SImode
))
16035 y_lo
= force_reg (SImode
, y_lo
);
16037 if (!arm_add_operand (y_hi
, SImode
))
16038 y_hi
= force_reg (SImode
, y_hi
);
16040 rtx cmp1
= gen_rtx_NE (SImode
, x_lo
, y_lo
);
16041 rtx cmp2
= gen_rtx_NE (SImode
, x_hi
, y_hi
);
16042 rtx conjunction
= gen_rtx_IOR (SImode
, cmp1
, cmp2
);
16043 mode
= SELECT_CC_MODE (code
, conjunction
, const0_rtx
);
16044 cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
16046 emit_insn (gen_rtx_SET (cc_reg
,
16047 gen_rtx_COMPARE (mode
, conjunction
,
16055 if (y_lo
== const0_rtx
)
16057 /* If the low word of y is 0, then this is simply a normal
16058 compare of the upper words. */
16059 if (!arm_add_operand (y_hi
, SImode
))
16060 y_hi
= force_reg (SImode
, y_hi
);
16062 return arm_gen_compare_reg (code
, x_hi
, y_hi
, NULL_RTX
);
16065 if (!arm_add_operand (y_lo
, SImode
))
16066 y_lo
= force_reg (SImode
, y_lo
);
16069 = gen_rtx_LTU (DImode
,
16070 arm_gen_compare_reg (LTU
, x_lo
, y_lo
, NULL_RTX
),
16074 scratch
= gen_rtx_SCRATCH (SImode
);
16076 if (!arm_not_operand (y_hi
, SImode
))
16077 y_hi
= force_reg (SImode
, y_hi
);
16080 if (y_hi
== const0_rtx
)
16081 insn
= emit_insn (gen_cmpsi3_0_carryin_CC_NVout (scratch
, x_hi
,
16083 else if (CONST_INT_P (y_hi
))
16084 insn
= emit_insn (gen_cmpsi3_imm_carryin_CC_NVout (scratch
, x_hi
,
16087 insn
= emit_insn (gen_cmpsi3_carryin_CC_NVout (scratch
, x_hi
, y_hi
,
16089 return SET_DEST (single_set (insn
));
16095 /* During expansion, we only expect to get here if y is a
16096 constant that we want to handle, otherwise we should have
16097 swapped the operands already. */
16098 gcc_assert (arm_const_double_prefer_rsbs_rsc (y
));
16100 if (!const_ok_for_arm (INTVAL (y_lo
)))
16101 y_lo
= force_reg (SImode
, y_lo
);
16103 /* Perform a reverse subtract and compare. */
16105 = gen_rtx_LTU (DImode
,
16106 arm_gen_compare_reg (LTU
, y_lo
, x_lo
, scratch
),
16108 rtx_insn
*insn
= emit_insn (gen_rscsi3_CC_NVout_scratch (scratch
, y_hi
,
16110 return SET_DEST (single_set (insn
));
16116 if (y_lo
== const0_rtx
)
16118 /* If the low word of y is 0, then this is simply a normal
16119 compare of the upper words. */
16120 if (!arm_add_operand (y_hi
, SImode
))
16121 y_hi
= force_reg (SImode
, y_hi
);
16123 return arm_gen_compare_reg (code
, x_hi
, y_hi
, NULL_RTX
);
16126 if (!arm_add_operand (y_lo
, SImode
))
16127 y_lo
= force_reg (SImode
, y_lo
);
16130 = gen_rtx_LTU (DImode
,
16131 arm_gen_compare_reg (LTU
, x_lo
, y_lo
, NULL_RTX
),
16135 scratch
= gen_rtx_SCRATCH (SImode
);
16136 if (!arm_not_operand (y_hi
, SImode
))
16137 y_hi
= force_reg (SImode
, y_hi
);
16140 if (y_hi
== const0_rtx
)
16141 insn
= emit_insn (gen_cmpsi3_0_carryin_CC_Bout (scratch
, x_hi
,
16143 else if (CONST_INT_P (y_hi
))
16145 /* Constant is viewed as unsigned when zero-extended. */
16146 y_hi
= GEN_INT (UINTVAL (y_hi
) & 0xffffffffULL
);
16147 insn
= emit_insn (gen_cmpsi3_imm_carryin_CC_Bout (scratch
, x_hi
,
16151 insn
= emit_insn (gen_cmpsi3_carryin_CC_Bout (scratch
, x_hi
, y_hi
,
16153 return SET_DEST (single_set (insn
));
16159 /* During expansion, we only expect to get here if y is a
16160 constant that we want to handle, otherwise we should have
16161 swapped the operands already. */
16162 gcc_assert (arm_const_double_prefer_rsbs_rsc (y
));
16164 if (!const_ok_for_arm (INTVAL (y_lo
)))
16165 y_lo
= force_reg (SImode
, y_lo
);
16167 /* Perform a reverse subtract and compare. */
16169 = gen_rtx_LTU (DImode
,
16170 arm_gen_compare_reg (LTU
, y_lo
, x_lo
, scratch
),
16172 y_hi
= GEN_INT (0xffffffff & UINTVAL (y_hi
));
16173 rtx_insn
*insn
= emit_insn (gen_rscsi3_CC_Bout_scratch (scratch
, y_hi
,
16175 return SET_DEST (single_set (insn
));
16179 gcc_unreachable ();
16183 /* X and Y are two things to compare using CODE. Emit the compare insn and
16184 return the rtx for register 0 in the proper mode. */
16186 arm_gen_compare_reg (rtx_code code
, rtx x
, rtx y
, rtx scratch
)
16188 if (GET_MODE (x
) == DImode
|| GET_MODE (y
) == DImode
)
16189 return arm_gen_dicompare_reg (code
, x
, y
, scratch
);
16191 machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
16192 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
16193 if (mode
== CC_RSBmode
)
16196 scratch
= gen_rtx_SCRATCH (SImode
);
16197 emit_insn (gen_rsb_imm_compare_scratch (scratch
,
16198 GEN_INT (~UINTVAL (x
)), y
));
16201 emit_set_insn (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
));
16206 /* Generate a sequence of insns that will generate the correct return
16207 address mask depending on the physical architecture that the program
16210 arm_gen_return_addr_mask (void)
16212 rtx reg
= gen_reg_rtx (Pmode
);
16214 emit_insn (gen_return_addr_mask (reg
));
16219 arm_reload_in_hi (rtx
*operands
)
16221 rtx ref
= operands
[1];
16223 HOST_WIDE_INT offset
= 0;
16225 if (SUBREG_P (ref
))
16227 offset
= SUBREG_BYTE (ref
);
16228 ref
= SUBREG_REG (ref
);
16233 /* We have a pseudo which has been spilt onto the stack; there
16234 are two cases here: the first where there is a simple
16235 stack-slot replacement and a second where the stack-slot is
16236 out of range, or is used as a subreg. */
16237 if (reg_equiv_mem (REGNO (ref
)))
16239 ref
= reg_equiv_mem (REGNO (ref
));
16240 base
= find_replacement (&XEXP (ref
, 0));
16243 /* The slot is out of range, or was dressed up in a SUBREG. */
16244 base
= reg_equiv_address (REGNO (ref
));
16246 /* PR 62554: If there is no equivalent memory location then just move
16247 the value as an SImode register move. This happens when the target
16248 architecture variant does not have an HImode register move. */
16251 gcc_assert (REG_P (operands
[0]));
16252 emit_insn (gen_movsi (gen_rtx_SUBREG (SImode
, operands
[0], 0),
16253 gen_rtx_SUBREG (SImode
, ref
, 0)));
16258 base
= find_replacement (&XEXP (ref
, 0));
16260 /* Handle the case where the address is too complex to be offset by 1. */
16261 if (GET_CODE (base
) == MINUS
16262 || (GET_CODE (base
) == PLUS
&& !CONST_INT_P (XEXP (base
, 1))))
16264 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
16266 emit_set_insn (base_plus
, base
);
16269 else if (GET_CODE (base
) == PLUS
)
16271 /* The addend must be CONST_INT, or we would have dealt with it above. */
16272 HOST_WIDE_INT hi
, lo
;
16274 offset
+= INTVAL (XEXP (base
, 1));
16275 base
= XEXP (base
, 0);
16277 /* Rework the address into a legal sequence of insns. */
16278 /* Valid range for lo is -4095 -> 4095 */
16281 : -((-offset
) & 0xfff));
16283 /* Corner case, if lo is the max offset then we would be out of range
16284 once we have added the additional 1 below, so bump the msb into the
16285 pre-loading insn(s). */
16289 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
16290 ^ (HOST_WIDE_INT
) 0x80000000)
16291 - (HOST_WIDE_INT
) 0x80000000);
16293 gcc_assert (hi
+ lo
== offset
);
16297 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
16299 /* Get the base address; addsi3 knows how to handle constants
16300 that require more than one insn. */
16301 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
16307 /* Operands[2] may overlap operands[0] (though it won't overlap
16308 operands[1]), that's why we asked for a DImode reg -- so we can
16309 use the bit that does not overlap. */
16310 if (REGNO (operands
[2]) == REGNO (operands
[0]))
16311 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
16313 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
16315 emit_insn (gen_zero_extendqisi2 (scratch
,
16316 gen_rtx_MEM (QImode
,
16317 plus_constant (Pmode
, base
,
16319 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
16320 gen_rtx_MEM (QImode
,
16321 plus_constant (Pmode
, base
,
16323 if (!BYTES_BIG_ENDIAN
)
16324 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
16325 gen_rtx_IOR (SImode
,
16328 gen_rtx_SUBREG (SImode
, operands
[0], 0),
16332 emit_set_insn (gen_rtx_SUBREG (SImode
, operands
[0], 0),
16333 gen_rtx_IOR (SImode
,
16334 gen_rtx_ASHIFT (SImode
, scratch
,
16336 gen_rtx_SUBREG (SImode
, operands
[0], 0)));
16339 /* Handle storing a half-word to memory during reload by synthesizing as two
16340 byte stores. Take care not to clobber the input values until after we
16341 have moved them somewhere safe. This code assumes that if the DImode
16342 scratch in operands[2] overlaps either the input value or output address
16343 in some way, then that value must die in this insn (we absolutely need
16344 two scratch registers for some corner cases). */
16346 arm_reload_out_hi (rtx
*operands
)
16348 rtx ref
= operands
[0];
16349 rtx outval
= operands
[1];
16351 HOST_WIDE_INT offset
= 0;
16353 if (SUBREG_P (ref
))
16355 offset
= SUBREG_BYTE (ref
);
16356 ref
= SUBREG_REG (ref
);
16361 /* We have a pseudo which has been spilt onto the stack; there
16362 are two cases here: the first where there is a simple
16363 stack-slot replacement and a second where the stack-slot is
16364 out of range, or is used as a subreg. */
16365 if (reg_equiv_mem (REGNO (ref
)))
16367 ref
= reg_equiv_mem (REGNO (ref
));
16368 base
= find_replacement (&XEXP (ref
, 0));
16371 /* The slot is out of range, or was dressed up in a SUBREG. */
16372 base
= reg_equiv_address (REGNO (ref
));
16374 /* PR 62254: If there is no equivalent memory location then just move
16375 the value as an SImode register move. This happens when the target
16376 architecture variant does not have an HImode register move. */
16379 gcc_assert (REG_P (outval
) || SUBREG_P (outval
));
16381 if (REG_P (outval
))
16383 emit_insn (gen_movsi (gen_rtx_SUBREG (SImode
, ref
, 0),
16384 gen_rtx_SUBREG (SImode
, outval
, 0)));
16386 else /* SUBREG_P (outval) */
16388 if (GET_MODE (SUBREG_REG (outval
)) == SImode
)
16389 emit_insn (gen_movsi (gen_rtx_SUBREG (SImode
, ref
, 0),
16390 SUBREG_REG (outval
)));
16392 /* FIXME: Handle other cases ? */
16393 gcc_unreachable ();
16399 base
= find_replacement (&XEXP (ref
, 0));
16401 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
16403 /* Handle the case where the address is too complex to be offset by 1. */
16404 if (GET_CODE (base
) == MINUS
16405 || (GET_CODE (base
) == PLUS
&& !CONST_INT_P (XEXP (base
, 1))))
16407 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
16409 /* Be careful not to destroy OUTVAL. */
16410 if (reg_overlap_mentioned_p (base_plus
, outval
))
16412 /* Updating base_plus might destroy outval, see if we can
16413 swap the scratch and base_plus. */
16414 if (!reg_overlap_mentioned_p (scratch
, outval
))
16415 std::swap (scratch
, base_plus
);
16418 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
16420 /* Be conservative and copy OUTVAL into the scratch now,
16421 this should only be necessary if outval is a subreg
16422 of something larger than a word. */
16423 /* XXX Might this clobber base? I can't see how it can,
16424 since scratch is known to overlap with OUTVAL, and
16425 must be wider than a word. */
16426 emit_insn (gen_movhi (scratch_hi
, outval
));
16427 outval
= scratch_hi
;
16431 emit_set_insn (base_plus
, base
);
16434 else if (GET_CODE (base
) == PLUS
)
16436 /* The addend must be CONST_INT, or we would have dealt with it above. */
16437 HOST_WIDE_INT hi
, lo
;
16439 offset
+= INTVAL (XEXP (base
, 1));
16440 base
= XEXP (base
, 0);
16442 /* Rework the address into a legal sequence of insns. */
16443 /* Valid range for lo is -4095 -> 4095 */
16446 : -((-offset
) & 0xfff));
16448 /* Corner case, if lo is the max offset then we would be out of range
16449 once we have added the additional 1 below, so bump the msb into the
16450 pre-loading insn(s). */
16454 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
16455 ^ (HOST_WIDE_INT
) 0x80000000)
16456 - (HOST_WIDE_INT
) 0x80000000);
16458 gcc_assert (hi
+ lo
== offset
);
16462 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
16464 /* Be careful not to destroy OUTVAL. */
16465 if (reg_overlap_mentioned_p (base_plus
, outval
))
16467 /* Updating base_plus might destroy outval, see if we
16468 can swap the scratch and base_plus. */
16469 if (!reg_overlap_mentioned_p (scratch
, outval
))
16470 std::swap (scratch
, base_plus
);
16473 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
16475 /* Be conservative and copy outval into scratch now,
16476 this should only be necessary if outval is a
16477 subreg of something larger than a word. */
16478 /* XXX Might this clobber base? I can't see how it
16479 can, since scratch is known to overlap with
16481 emit_insn (gen_movhi (scratch_hi
, outval
));
16482 outval
= scratch_hi
;
16486 /* Get the base address; addsi3 knows how to handle constants
16487 that require more than one insn. */
16488 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
16494 if (BYTES_BIG_ENDIAN
)
16496 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
16497 plus_constant (Pmode
, base
,
16499 gen_lowpart (QImode
, outval
)));
16500 emit_insn (gen_lshrsi3 (scratch
,
16501 gen_rtx_SUBREG (SImode
, outval
, 0),
16503 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (Pmode
, base
,
16505 gen_lowpart (QImode
, scratch
)));
16509 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (Pmode
, base
,
16511 gen_lowpart (QImode
, outval
)));
16512 emit_insn (gen_lshrsi3 (scratch
,
16513 gen_rtx_SUBREG (SImode
, outval
, 0),
16515 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
16516 plus_constant (Pmode
, base
,
16518 gen_lowpart (QImode
, scratch
)));
16522 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
16523 (padded to the size of a word) should be passed in a register. */
16526 arm_must_pass_in_stack (const function_arg_info
&arg
)
16528 if (TARGET_AAPCS_BASED
)
16529 return must_pass_in_stack_var_size (arg
);
16531 return must_pass_in_stack_var_size_or_pad (arg
);
16535 /* Implement TARGET_FUNCTION_ARG_PADDING; return PAD_UPWARD if the lowest
16536 byte of a stack argument has useful data. For legacy APCS ABIs we use
16537 the default. For AAPCS based ABIs small aggregate types are placed
16538 in the lowest memory address. */
16540 static pad_direction
16541 arm_function_arg_padding (machine_mode mode
, const_tree type
)
16543 if (!TARGET_AAPCS_BASED
)
16544 return default_function_arg_padding (mode
, type
);
16546 if (type
&& BYTES_BIG_ENDIAN
&& INTEGRAL_TYPE_P (type
))
16547 return PAD_DOWNWARD
;
16553 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
16554 Return !BYTES_BIG_ENDIAN if the least significant byte of the
16555 register has useful data, and return the opposite if the most
16556 significant byte does. */
16559 arm_pad_reg_upward (machine_mode mode
,
16560 tree type
, int first ATTRIBUTE_UNUSED
)
16562 if (TARGET_AAPCS_BASED
&& BYTES_BIG_ENDIAN
)
16564 /* For AAPCS, small aggregates, small fixed-point types,
16565 and small complex types are always padded upwards. */
16568 if ((AGGREGATE_TYPE_P (type
)
16569 || TREE_CODE (type
) == COMPLEX_TYPE
16570 || FIXED_POINT_TYPE_P (type
))
16571 && int_size_in_bytes (type
) <= 4)
16576 if ((COMPLEX_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
))
16577 && GET_MODE_SIZE (mode
) <= 4)
16582 /* Otherwise, use default padding. */
16583 return !BYTES_BIG_ENDIAN
;
16586 /* Returns true iff OFFSET is valid for use in an LDRD/STRD instruction,
16587 assuming that the address in the base register is word aligned. */
16589 offset_ok_for_ldrd_strd (HOST_WIDE_INT offset
)
16591 HOST_WIDE_INT max_offset
;
16593 /* Offset must be a multiple of 4 in Thumb mode. */
16594 if (TARGET_THUMB2
&& ((offset
& 3) != 0))
16599 else if (TARGET_ARM
)
16604 return ((offset
<= max_offset
) && (offset
>= -max_offset
));
16607 /* Checks whether the operands are valid for use in an LDRD/STRD instruction.
16608 Assumes that RT, RT2, and RN are REG. This is guaranteed by the patterns.
16609 Assumes that the address in the base register RN is word aligned. Pattern
16610 guarantees that both memory accesses use the same base register,
16611 the offsets are constants within the range, and the gap between the offsets is 4.
16612 If preload complete then check that registers are legal. WBACK indicates whether
16613 address is updated. LOAD indicates whether memory access is load or store. */
16615 operands_ok_ldrd_strd (rtx rt
, rtx rt2
, rtx rn
, HOST_WIDE_INT offset
,
16616 bool wback
, bool load
)
16618 unsigned int t
, t2
, n
;
16620 if (!reload_completed
)
16623 if (!offset_ok_for_ldrd_strd (offset
))
16630 if ((TARGET_THUMB2
)
16631 && ((wback
&& (n
== t
|| n
== t2
))
16632 || (t
== SP_REGNUM
)
16633 || (t
== PC_REGNUM
)
16634 || (t2
== SP_REGNUM
)
16635 || (t2
== PC_REGNUM
)
16636 || (!load
&& (n
== PC_REGNUM
))
16637 || (load
&& (t
== t2
))
16638 /* Triggers Cortex-M3 LDRD errata. */
16639 || (!wback
&& load
&& fix_cm3_ldrd
&& (n
== t
))))
16643 && ((wback
&& (n
== t
|| n
== t2
))
16644 || (t2
== PC_REGNUM
)
16645 || (t
% 2 != 0) /* First destination register is not even. */
16647 /* PC can be used as base register (for offset addressing only),
16648 but it is depricated. */
16649 || (n
== PC_REGNUM
)))
16655 /* Return true if a 64-bit access with alignment ALIGN and with a
16656 constant offset OFFSET from the base pointer is permitted on this
16659 align_ok_ldrd_strd (HOST_WIDE_INT align
, HOST_WIDE_INT offset
)
16661 return (unaligned_access
16662 ? (align
>= BITS_PER_WORD
&& (offset
& 3) == 0)
16663 : (align
>= 2 * BITS_PER_WORD
&& (offset
& 7) == 0));
16666 /* Helper for gen_operands_ldrd_strd. Returns true iff the memory
16667 operand MEM's address contains an immediate offset from the base
16668 register and has no side effects, in which case it sets BASE,
16669 OFFSET and ALIGN accordingly. */
16671 mem_ok_for_ldrd_strd (rtx mem
, rtx
*base
, rtx
*offset
, HOST_WIDE_INT
*align
)
16675 gcc_assert (base
!= NULL
&& offset
!= NULL
);
16677 /* TODO: Handle more general memory operand patterns, such as
16678 PRE_DEC and PRE_INC. */
16680 if (side_effects_p (mem
))
16683 /* Can't deal with subregs. */
16684 if (SUBREG_P (mem
))
16687 gcc_assert (MEM_P (mem
));
16689 *offset
= const0_rtx
;
16690 *align
= MEM_ALIGN (mem
);
16692 addr
= XEXP (mem
, 0);
16694 /* If addr isn't valid for DImode, then we can't handle it. */
16695 if (!arm_legitimate_address_p (DImode
, addr
,
16696 reload_in_progress
|| reload_completed
))
16704 else if (GET_CODE (addr
) == PLUS
)
16706 *base
= XEXP (addr
, 0);
16707 *offset
= XEXP (addr
, 1);
16708 return (REG_P (*base
) && CONST_INT_P (*offset
));
16714 /* Called from a peephole2 to replace two word-size accesses with a
16715 single LDRD/STRD instruction. Returns true iff we can generate a
16716 new instruction sequence. That is, both accesses use the same base
16717 register and the gap between constant offsets is 4. This function
16718 may reorder its operands to match ldrd/strd RTL templates.
16719 OPERANDS are the operands found by the peephole matcher;
16720 OPERANDS[0,1] are register operands, and OPERANDS[2,3] are the
16721 corresponding memory operands. LOAD indicaates whether the access
16722 is load or store. CONST_STORE indicates a store of constant
16723 integer values held in OPERANDS[4,5] and assumes that the pattern
16724 is of length 4 insn, for the purpose of checking dead registers.
16725 COMMUTE indicates that register operands may be reordered. */
16727 gen_operands_ldrd_strd (rtx
*operands
, bool load
,
16728 bool const_store
, bool commute
)
16731 HOST_WIDE_INT offsets
[2], offset
, align
[2];
16732 rtx base
= NULL_RTX
;
16733 rtx cur_base
, cur_offset
, tmp
;
16735 HARD_REG_SET regset
;
16737 gcc_assert (!const_store
|| !load
);
16738 /* Check that the memory references are immediate offsets from the
16739 same base register. Extract the base register, the destination
16740 registers, and the corresponding memory offsets. */
16741 for (i
= 0; i
< nops
; i
++)
16743 if (!mem_ok_for_ldrd_strd (operands
[nops
+i
], &cur_base
, &cur_offset
,
16749 else if (REGNO (base
) != REGNO (cur_base
))
16752 offsets
[i
] = INTVAL (cur_offset
);
16753 if (GET_CODE (operands
[i
]) == SUBREG
)
16755 tmp
= SUBREG_REG (operands
[i
]);
16756 gcc_assert (GET_MODE (operands
[i
]) == GET_MODE (tmp
));
16761 /* Make sure there is no dependency between the individual loads. */
16762 if (load
&& REGNO (operands
[0]) == REGNO (base
))
16763 return false; /* RAW */
16765 if (load
&& REGNO (operands
[0]) == REGNO (operands
[1]))
16766 return false; /* WAW */
16768 /* If the same input register is used in both stores
16769 when storing different constants, try to find a free register.
16770 For example, the code
16775 can be transformed into
16779 in Thumb mode assuming that r1 is free.
16780 For ARM mode do the same but only if the starting register
16781 can be made to be even. */
16783 && REGNO (operands
[0]) == REGNO (operands
[1])
16784 && INTVAL (operands
[4]) != INTVAL (operands
[5]))
16788 CLEAR_HARD_REG_SET (regset
);
16789 tmp
= peep2_find_free_register (0, 4, "r", SImode
, ®set
);
16790 if (tmp
== NULL_RTX
)
16793 /* Use the new register in the first load to ensure that
16794 if the original input register is not dead after peephole,
16795 then it will have the correct constant value. */
16798 else if (TARGET_ARM
)
16800 int regno
= REGNO (operands
[0]);
16801 if (!peep2_reg_dead_p (4, operands
[0]))
16803 /* When the input register is even and is not dead after the
16804 pattern, it has to hold the second constant but we cannot
16805 form a legal STRD in ARM mode with this register as the second
16807 if (regno
% 2 == 0)
16810 /* Is regno-1 free? */
16811 SET_HARD_REG_SET (regset
);
16812 CLEAR_HARD_REG_BIT(regset
, regno
- 1);
16813 tmp
= peep2_find_free_register (0, 4, "r", SImode
, ®set
);
16814 if (tmp
== NULL_RTX
)
16821 /* Find a DImode register. */
16822 CLEAR_HARD_REG_SET (regset
);
16823 tmp
= peep2_find_free_register (0, 4, "r", DImode
, ®set
);
16824 if (tmp
!= NULL_RTX
)
16826 operands
[0] = simplify_gen_subreg (SImode
, tmp
, DImode
, 0);
16827 operands
[1] = simplify_gen_subreg (SImode
, tmp
, DImode
, 4);
16831 /* Can we use the input register to form a DI register? */
16832 SET_HARD_REG_SET (regset
);
16833 CLEAR_HARD_REG_BIT(regset
,
16834 regno
% 2 == 0 ? regno
+ 1 : regno
- 1);
16835 tmp
= peep2_find_free_register (0, 4, "r", SImode
, ®set
);
16836 if (tmp
== NULL_RTX
)
16838 operands
[regno
% 2 == 1 ? 0 : 1] = tmp
;
16842 gcc_assert (operands
[0] != NULL_RTX
);
16843 gcc_assert (operands
[1] != NULL_RTX
);
16844 gcc_assert (REGNO (operands
[0]) % 2 == 0);
16845 gcc_assert (REGNO (operands
[1]) == REGNO (operands
[0]) + 1);
16849 /* Make sure the instructions are ordered with lower memory access first. */
16850 if (offsets
[0] > offsets
[1])
16852 gap
= offsets
[0] - offsets
[1];
16853 offset
= offsets
[1];
16855 /* Swap the instructions such that lower memory is accessed first. */
16856 std::swap (operands
[0], operands
[1]);
16857 std::swap (operands
[2], operands
[3]);
16858 std::swap (align
[0], align
[1]);
16860 std::swap (operands
[4], operands
[5]);
16864 gap
= offsets
[1] - offsets
[0];
16865 offset
= offsets
[0];
16868 /* Make sure accesses are to consecutive memory locations. */
16869 if (gap
!= GET_MODE_SIZE (SImode
))
16872 if (!align_ok_ldrd_strd (align
[0], offset
))
16875 /* Make sure we generate legal instructions. */
16876 if (operands_ok_ldrd_strd (operands
[0], operands
[1], base
, offset
,
16880 /* In Thumb state, where registers are almost unconstrained, there
16881 is little hope to fix it. */
16885 if (load
&& commute
)
16887 /* Try reordering registers. */
16888 std::swap (operands
[0], operands
[1]);
16889 if (operands_ok_ldrd_strd (operands
[0], operands
[1], base
, offset
,
16896 /* If input registers are dead after this pattern, they can be
16897 reordered or replaced by other registers that are free in the
16898 current pattern. */
16899 if (!peep2_reg_dead_p (4, operands
[0])
16900 || !peep2_reg_dead_p (4, operands
[1]))
16903 /* Try to reorder the input registers. */
16904 /* For example, the code
16909 can be transformed into
16914 if (operands_ok_ldrd_strd (operands
[1], operands
[0], base
, offset
,
16917 std::swap (operands
[0], operands
[1]);
16921 /* Try to find a free DI register. */
16922 CLEAR_HARD_REG_SET (regset
);
16923 add_to_hard_reg_set (®set
, SImode
, REGNO (operands
[0]));
16924 add_to_hard_reg_set (®set
, SImode
, REGNO (operands
[1]));
16927 tmp
= peep2_find_free_register (0, 4, "r", DImode
, ®set
);
16928 if (tmp
== NULL_RTX
)
16931 /* DREG must be an even-numbered register in DImode.
16932 Split it into SI registers. */
16933 operands
[0] = simplify_gen_subreg (SImode
, tmp
, DImode
, 0);
16934 operands
[1] = simplify_gen_subreg (SImode
, tmp
, DImode
, 4);
16935 gcc_assert (operands
[0] != NULL_RTX
);
16936 gcc_assert (operands
[1] != NULL_RTX
);
16937 gcc_assert (REGNO (operands
[0]) % 2 == 0);
16938 gcc_assert (REGNO (operands
[0]) + 1 == REGNO (operands
[1]));
16940 return (operands_ok_ldrd_strd (operands
[0], operands
[1],
16950 /* Return true if parallel execution of the two word-size accesses provided
16951 could be satisfied with a single LDRD/STRD instruction. Two word-size
16952 accesses are represented by the OPERANDS array, where OPERANDS[0,1] are
16953 register operands and OPERANDS[2,3] are the corresponding memory operands.
16956 valid_operands_ldrd_strd (rtx
*operands
, bool load
)
16959 HOST_WIDE_INT offsets
[2], offset
, align
[2];
16960 rtx base
= NULL_RTX
;
16961 rtx cur_base
, cur_offset
;
16964 /* Check that the memory references are immediate offsets from the
16965 same base register. Extract the base register, the destination
16966 registers, and the corresponding memory offsets. */
16967 for (i
= 0; i
< nops
; i
++)
16969 if (!mem_ok_for_ldrd_strd (operands
[nops
+i
], &cur_base
, &cur_offset
,
16975 else if (REGNO (base
) != REGNO (cur_base
))
16978 offsets
[i
] = INTVAL (cur_offset
);
16979 if (GET_CODE (operands
[i
]) == SUBREG
)
16983 if (offsets
[0] > offsets
[1])
16986 gap
= offsets
[1] - offsets
[0];
16987 offset
= offsets
[0];
16989 /* Make sure accesses are to consecutive memory locations. */
16990 if (gap
!= GET_MODE_SIZE (SImode
))
16993 if (!align_ok_ldrd_strd (align
[0], offset
))
16996 return operands_ok_ldrd_strd (operands
[0], operands
[1], base
, offset
,
17001 /* Print a symbolic form of X to the debug file, F. */
17003 arm_print_value (FILE *f
, rtx x
)
17005 switch (GET_CODE (x
))
17008 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
17014 real_to_decimal (fpstr
, CONST_DOUBLE_REAL_VALUE (x
),
17015 sizeof (fpstr
), 0, 1);
17025 for (i
= 0; i
< CONST_VECTOR_NUNITS (x
); i
++)
17027 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (CONST_VECTOR_ELT (x
, i
)));
17028 if (i
< (CONST_VECTOR_NUNITS (x
) - 1))
17036 fprintf (f
, "\"%s\"", XSTR (x
, 0));
17040 fprintf (f
, "`%s'", XSTR (x
, 0));
17044 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
17048 arm_print_value (f
, XEXP (x
, 0));
17052 arm_print_value (f
, XEXP (x
, 0));
17054 arm_print_value (f
, XEXP (x
, 1));
17062 fprintf (f
, "????");
17067 /* Routines for manipulation of the constant pool. */
17069 /* Arm instructions cannot load a large constant directly into a
17070 register; they have to come from a pc relative load. The constant
17071 must therefore be placed in the addressable range of the pc
17072 relative load. Depending on the precise pc relative load
17073 instruction the range is somewhere between 256 bytes and 4k. This
17074 means that we often have to dump a constant inside a function, and
17075 generate code to branch around it.
17077 It is important to minimize this, since the branches will slow
17078 things down and make the code larger.
17080 Normally we can hide the table after an existing unconditional
17081 branch so that there is no interruption of the flow, but in the
17082 worst case the code looks like this:
17100 We fix this by performing a scan after scheduling, which notices
17101 which instructions need to have their operands fetched from the
17102 constant table and builds the table.
17104 The algorithm starts by building a table of all the constants that
17105 need fixing up and all the natural barriers in the function (places
17106 where a constant table can be dropped without breaking the flow).
17107 For each fixup we note how far the pc-relative replacement will be
17108 able to reach and the offset of the instruction into the function.
17110 Having built the table we then group the fixes together to form
17111 tables that are as large as possible (subject to addressing
17112 constraints) and emit each table of constants after the last
17113 barrier that is within range of all the instructions in the group.
17114 If a group does not contain a barrier, then we forcibly create one
17115 by inserting a jump instruction into the flow. Once the table has
17116 been inserted, the insns are then modified to reference the
17117 relevant entry in the pool.
17119 Possible enhancements to the algorithm (not implemented) are:
17121 1) For some processors and object formats, there may be benefit in
17122 aligning the pools to the start of cache lines; this alignment
17123 would need to be taken into account when calculating addressability
17126 /* These typedefs are located at the start of this file, so that
17127 they can be used in the prototypes there. This comment is to
17128 remind readers of that fact so that the following structures
17129 can be understood more easily.
17131 typedef struct minipool_node Mnode;
17132 typedef struct minipool_fixup Mfix; */
17134 struct minipool_node
17136 /* Doubly linked chain of entries. */
17139 /* The maximum offset into the code that this entry can be placed. While
17140 pushing fixes for forward references, all entries are sorted in order
17141 of increasing max_address. */
17142 HOST_WIDE_INT max_address
;
17143 /* Similarly for an entry inserted for a backwards ref. */
17144 HOST_WIDE_INT min_address
;
17145 /* The number of fixes referencing this entry. This can become zero
17146 if we "unpush" an entry. In this case we ignore the entry when we
17147 come to emit the code. */
17149 /* The offset from the start of the minipool. */
17150 HOST_WIDE_INT offset
;
17151 /* The value in table. */
17153 /* The mode of value. */
17155 /* The size of the value. With iWMMXt enabled
17156 sizes > 4 also imply an alignment of 8-bytes. */
17160 struct minipool_fixup
17164 HOST_WIDE_INT address
;
17170 HOST_WIDE_INT forwards
;
17171 HOST_WIDE_INT backwards
;
17174 /* Fixes less than a word need padding out to a word boundary. */
17175 #define MINIPOOL_FIX_SIZE(mode) \
17176 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
17178 static Mnode
* minipool_vector_head
;
17179 static Mnode
* minipool_vector_tail
;
17180 static rtx_code_label
*minipool_vector_label
;
17181 static int minipool_pad
;
17183 /* The linked list of all minipool fixes required for this function. */
17184 Mfix
* minipool_fix_head
;
17185 Mfix
* minipool_fix_tail
;
17186 /* The fix entry for the current minipool, once it has been placed. */
17187 Mfix
* minipool_barrier
;
17189 #ifndef JUMP_TABLES_IN_TEXT_SECTION
17190 #define JUMP_TABLES_IN_TEXT_SECTION 0
17193 static HOST_WIDE_INT
17194 get_jump_table_size (rtx_jump_table_data
*insn
)
17196 /* ADDR_VECs only take room if read-only data does into the text
17198 if (JUMP_TABLES_IN_TEXT_SECTION
|| readonly_data_section
== text_section
)
17200 rtx body
= PATTERN (insn
);
17201 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
17202 HOST_WIDE_INT size
;
17203 HOST_WIDE_INT modesize
;
17205 modesize
= GET_MODE_SIZE (GET_MODE (body
));
17206 size
= modesize
* XVECLEN (body
, elt
);
17210 /* Round up size of TBB table to a halfword boundary. */
17211 size
= (size
+ 1) & ~HOST_WIDE_INT_1
;
17214 /* No padding necessary for TBH. */
17217 /* Add two bytes for alignment on Thumb. */
17222 gcc_unreachable ();
17230 /* Emit insns to load the function address from FUNCDESC (an FDPIC
17231 function descriptor) into a register and the GOT address into the
17232 FDPIC register, returning an rtx for the register holding the
17233 function address. */
17236 arm_load_function_descriptor (rtx funcdesc
)
17238 rtx fnaddr_reg
= gen_reg_rtx (Pmode
);
17239 rtx pic_reg
= gen_rtx_REG (Pmode
, FDPIC_REGNUM
);
17240 rtx fnaddr
= gen_rtx_MEM (Pmode
, funcdesc
);
17241 rtx gotaddr
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
, funcdesc
, 4));
17243 emit_move_insn (fnaddr_reg
, fnaddr
);
17245 /* The ABI requires the entry point address to be loaded first, but
17246 since we cannot support lazy binding for lack of atomic load of
17247 two 32-bits values, we do not need to bother to prevent the
17248 previous load from being moved after that of the GOT address. */
17249 emit_insn (gen_restore_pic_register_after_call (pic_reg
, gotaddr
));
17254 /* Return the maximum amount of padding that will be inserted before
17256 static HOST_WIDE_INT
17257 get_label_padding (rtx label
)
17259 HOST_WIDE_INT align
, min_insn_size
;
17261 align
= 1 << label_to_alignment (label
).levels
[0].log
;
17262 min_insn_size
= TARGET_THUMB
? 2 : 4;
17263 return align
> min_insn_size
? align
- min_insn_size
: 0;
17266 /* Move a minipool fix MP from its current location to before MAX_MP.
17267 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
17268 constraints may need updating. */
17270 move_minipool_fix_forward_ref (Mnode
*mp
, Mnode
*max_mp
,
17271 HOST_WIDE_INT max_address
)
17273 /* The code below assumes these are different. */
17274 gcc_assert (mp
!= max_mp
);
17276 if (max_mp
== NULL
)
17278 if (max_address
< mp
->max_address
)
17279 mp
->max_address
= max_address
;
17283 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
17284 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
17286 mp
->max_address
= max_address
;
17288 /* Unlink MP from its current position. Since max_mp is non-null,
17289 mp->prev must be non-null. */
17290 mp
->prev
->next
= mp
->next
;
17291 if (mp
->next
!= NULL
)
17292 mp
->next
->prev
= mp
->prev
;
17294 minipool_vector_tail
= mp
->prev
;
17296 /* Re-insert it before MAX_MP. */
17298 mp
->prev
= max_mp
->prev
;
17301 if (mp
->prev
!= NULL
)
17302 mp
->prev
->next
= mp
;
17304 minipool_vector_head
= mp
;
17307 /* Save the new entry. */
17310 /* Scan over the preceding entries and adjust their addresses as
17312 while (mp
->prev
!= NULL
17313 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
17315 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
17322 /* Add a constant to the minipool for a forward reference. Returns the
17323 node added or NULL if the constant will not fit in this pool. */
17325 add_minipool_forward_ref (Mfix
*fix
)
17327 /* If set, max_mp is the first pool_entry that has a lower
17328 constraint than the one we are trying to add. */
17329 Mnode
* max_mp
= NULL
;
17330 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
- minipool_pad
;
17333 /* If the minipool starts before the end of FIX->INSN then this FIX
17334 cannot be placed into the current pool. Furthermore, adding the
17335 new constant pool entry may cause the pool to start FIX_SIZE bytes
17337 if (minipool_vector_head
&&
17338 (fix
->address
+ get_attr_length (fix
->insn
)
17339 >= minipool_vector_head
->max_address
- fix
->fix_size
))
17342 /* Scan the pool to see if a constant with the same value has
17343 already been added. While we are doing this, also note the
17344 location where we must insert the constant if it doesn't already
17346 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
17348 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
17349 && fix
->mode
== mp
->mode
17350 && (!LABEL_P (fix
->value
)
17351 || (CODE_LABEL_NUMBER (fix
->value
)
17352 == CODE_LABEL_NUMBER (mp
->value
)))
17353 && rtx_equal_p (fix
->value
, mp
->value
))
17355 /* More than one fix references this entry. */
17357 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
17360 /* Note the insertion point if necessary. */
17362 && mp
->max_address
> max_address
)
17365 /* If we are inserting an 8-bytes aligned quantity and
17366 we have not already found an insertion point, then
17367 make sure that all such 8-byte aligned quantities are
17368 placed at the start of the pool. */
17369 if (ARM_DOUBLEWORD_ALIGN
17371 && fix
->fix_size
>= 8
17372 && mp
->fix_size
< 8)
17375 max_address
= mp
->max_address
;
17379 /* The value is not currently in the minipool, so we need to create
17380 a new entry for it. If MAX_MP is NULL, the entry will be put on
17381 the end of the list since the placement is less constrained than
17382 any existing entry. Otherwise, we insert the new fix before
17383 MAX_MP and, if necessary, adjust the constraints on the other
17386 mp
->fix_size
= fix
->fix_size
;
17387 mp
->mode
= fix
->mode
;
17388 mp
->value
= fix
->value
;
17390 /* Not yet required for a backwards ref. */
17391 mp
->min_address
= -65536;
17393 if (max_mp
== NULL
)
17395 mp
->max_address
= max_address
;
17397 mp
->prev
= minipool_vector_tail
;
17399 if (mp
->prev
== NULL
)
17401 minipool_vector_head
= mp
;
17402 minipool_vector_label
= gen_label_rtx ();
17405 mp
->prev
->next
= mp
;
17407 minipool_vector_tail
= mp
;
17411 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
17412 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
17414 mp
->max_address
= max_address
;
17417 mp
->prev
= max_mp
->prev
;
17419 if (mp
->prev
!= NULL
)
17420 mp
->prev
->next
= mp
;
17422 minipool_vector_head
= mp
;
17425 /* Save the new entry. */
17428 /* Scan over the preceding entries and adjust their addresses as
17430 while (mp
->prev
!= NULL
17431 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
17433 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
17441 move_minipool_fix_backward_ref (Mnode
*mp
, Mnode
*min_mp
,
17442 HOST_WIDE_INT min_address
)
17444 HOST_WIDE_INT offset
;
17446 /* The code below assumes these are different. */
17447 gcc_assert (mp
!= min_mp
);
17449 if (min_mp
== NULL
)
17451 if (min_address
> mp
->min_address
)
17452 mp
->min_address
= min_address
;
17456 /* We will adjust this below if it is too loose. */
17457 mp
->min_address
= min_address
;
17459 /* Unlink MP from its current position. Since min_mp is non-null,
17460 mp->next must be non-null. */
17461 mp
->next
->prev
= mp
->prev
;
17462 if (mp
->prev
!= NULL
)
17463 mp
->prev
->next
= mp
->next
;
17465 minipool_vector_head
= mp
->next
;
17467 /* Reinsert it after MIN_MP. */
17469 mp
->next
= min_mp
->next
;
17471 if (mp
->next
!= NULL
)
17472 mp
->next
->prev
= mp
;
17474 minipool_vector_tail
= mp
;
17480 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
17482 mp
->offset
= offset
;
17483 if (mp
->refcount
> 0)
17484 offset
+= mp
->fix_size
;
17486 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
17487 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
17493 /* Add a constant to the minipool for a backward reference. Returns the
17494 node added or NULL if the constant will not fit in this pool.
17496 Note that the code for insertion for a backwards reference can be
17497 somewhat confusing because the calculated offsets for each fix do
17498 not take into account the size of the pool (which is still under
17501 add_minipool_backward_ref (Mfix
*fix
)
17503 /* If set, min_mp is the last pool_entry that has a lower constraint
17504 than the one we are trying to add. */
17505 Mnode
*min_mp
= NULL
;
17506 /* This can be negative, since it is only a constraint. */
17507 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
17510 /* If we can't reach the current pool from this insn, or if we can't
17511 insert this entry at the end of the pool without pushing other
17512 fixes out of range, then we don't try. This ensures that we
17513 can't fail later on. */
17514 if (min_address
>= minipool_barrier
->address
17515 || (minipool_vector_tail
->min_address
+ fix
->fix_size
17516 >= minipool_barrier
->address
))
17519 /* Scan the pool to see if a constant with the same value has
17520 already been added. While we are doing this, also note the
17521 location where we must insert the constant if it doesn't already
17523 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
17525 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
17526 && fix
->mode
== mp
->mode
17527 && (!LABEL_P (fix
->value
)
17528 || (CODE_LABEL_NUMBER (fix
->value
)
17529 == CODE_LABEL_NUMBER (mp
->value
)))
17530 && rtx_equal_p (fix
->value
, mp
->value
)
17531 /* Check that there is enough slack to move this entry to the
17532 end of the table (this is conservative). */
17533 && (mp
->max_address
17534 > (minipool_barrier
->address
17535 + minipool_vector_tail
->offset
17536 + minipool_vector_tail
->fix_size
)))
17539 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
17542 if (min_mp
!= NULL
)
17543 mp
->min_address
+= fix
->fix_size
;
17546 /* Note the insertion point if necessary. */
17547 if (mp
->min_address
< min_address
)
17549 /* For now, we do not allow the insertion of 8-byte alignment
17550 requiring nodes anywhere but at the start of the pool. */
17551 if (ARM_DOUBLEWORD_ALIGN
17552 && fix
->fix_size
>= 8 && mp
->fix_size
< 8)
17557 else if (mp
->max_address
17558 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
17560 /* Inserting before this entry would push the fix beyond
17561 its maximum address (which can happen if we have
17562 re-located a forwards fix); force the new fix to come
17564 if (ARM_DOUBLEWORD_ALIGN
17565 && fix
->fix_size
>= 8 && mp
->fix_size
< 8)
17570 min_address
= mp
->min_address
+ fix
->fix_size
;
17573 /* Do not insert a non-8-byte aligned quantity before 8-byte
17574 aligned quantities. */
17575 else if (ARM_DOUBLEWORD_ALIGN
17576 && fix
->fix_size
< 8
17577 && mp
->fix_size
>= 8)
17580 min_address
= mp
->min_address
+ fix
->fix_size
;
17585 /* We need to create a new entry. */
17587 mp
->fix_size
= fix
->fix_size
;
17588 mp
->mode
= fix
->mode
;
17589 mp
->value
= fix
->value
;
17591 mp
->max_address
= minipool_barrier
->address
+ 65536;
17593 mp
->min_address
= min_address
;
17595 if (min_mp
== NULL
)
17598 mp
->next
= minipool_vector_head
;
17600 if (mp
->next
== NULL
)
17602 minipool_vector_tail
= mp
;
17603 minipool_vector_label
= gen_label_rtx ();
17606 mp
->next
->prev
= mp
;
17608 minipool_vector_head
= mp
;
17612 mp
->next
= min_mp
->next
;
17616 if (mp
->next
!= NULL
)
17617 mp
->next
->prev
= mp
;
17619 minipool_vector_tail
= mp
;
17622 /* Save the new entry. */
17630 /* Scan over the following entries and adjust their offsets. */
17631 while (mp
->next
!= NULL
)
17633 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
17634 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
17637 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
17639 mp
->next
->offset
= mp
->offset
;
17648 assign_minipool_offsets (Mfix
*barrier
)
17650 HOST_WIDE_INT offset
= 0;
17653 minipool_barrier
= barrier
;
17655 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
17657 mp
->offset
= offset
;
17659 if (mp
->refcount
> 0)
17660 offset
+= mp
->fix_size
;
17664 /* Output the literal table */
17666 dump_minipool (rtx_insn
*scan
)
17672 if (ARM_DOUBLEWORD_ALIGN
)
17673 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
17674 if (mp
->refcount
> 0 && mp
->fix_size
>= 8)
17681 fprintf (dump_file
,
17682 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
17683 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
, align64
? 8 : 4);
17685 scan
= emit_label_after (gen_label_rtx (), scan
);
17686 scan
= emit_insn_after (align64
? gen_align_8 () : gen_align_4 (), scan
);
17687 scan
= emit_label_after (minipool_vector_label
, scan
);
17689 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
17691 if (mp
->refcount
> 0)
17695 fprintf (dump_file
,
17696 ";; Offset %u, min %ld, max %ld ",
17697 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
17698 (unsigned long) mp
->max_address
);
17699 arm_print_value (dump_file
, mp
->value
);
17700 fputc ('\n', dump_file
);
17703 rtx val
= copy_rtx (mp
->value
);
17705 switch (GET_MODE_SIZE (mp
->mode
))
17707 #ifdef HAVE_consttable_1
17709 scan
= emit_insn_after (gen_consttable_1 (val
), scan
);
17713 #ifdef HAVE_consttable_2
17715 scan
= emit_insn_after (gen_consttable_2 (val
), scan
);
17719 #ifdef HAVE_consttable_4
17721 scan
= emit_insn_after (gen_consttable_4 (val
), scan
);
17725 #ifdef HAVE_consttable_8
17727 scan
= emit_insn_after (gen_consttable_8 (val
), scan
);
17731 #ifdef HAVE_consttable_16
17733 scan
= emit_insn_after (gen_consttable_16 (val
), scan
);
17738 gcc_unreachable ();
17746 minipool_vector_head
= minipool_vector_tail
= NULL
;
17747 scan
= emit_insn_after (gen_consttable_end (), scan
);
17748 scan
= emit_barrier_after (scan
);
17751 /* Return the cost of forcibly inserting a barrier after INSN. */
17753 arm_barrier_cost (rtx_insn
*insn
)
17755 /* Basing the location of the pool on the loop depth is preferable,
17756 but at the moment, the basic block information seems to be
17757 corrupt by this stage of the compilation. */
17758 int base_cost
= 50;
17759 rtx_insn
*next
= next_nonnote_insn (insn
);
17761 if (next
!= NULL
&& LABEL_P (next
))
17764 switch (GET_CODE (insn
))
17767 /* It will always be better to place the table before the label, rather
17776 return base_cost
- 10;
17779 return base_cost
+ 10;
17783 /* Find the best place in the insn stream in the range
17784 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
17785 Create the barrier by inserting a jump and add a new fix entry for
17788 create_fix_barrier (Mfix
*fix
, HOST_WIDE_INT max_address
)
17790 HOST_WIDE_INT count
= 0;
17791 rtx_barrier
*barrier
;
17792 rtx_insn
*from
= fix
->insn
;
17793 /* The instruction after which we will insert the jump. */
17794 rtx_insn
*selected
= NULL
;
17796 /* The address at which the jump instruction will be placed. */
17797 HOST_WIDE_INT selected_address
;
17799 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
17800 rtx_code_label
*label
= gen_label_rtx ();
17802 selected_cost
= arm_barrier_cost (from
);
17803 selected_address
= fix
->address
;
17805 while (from
&& count
< max_count
)
17807 rtx_jump_table_data
*tmp
;
17810 /* This code shouldn't have been called if there was a natural barrier
17812 gcc_assert (!BARRIER_P (from
));
17814 /* Count the length of this insn. This must stay in sync with the
17815 code that pushes minipool fixes. */
17816 if (LABEL_P (from
))
17817 count
+= get_label_padding (from
);
17819 count
+= get_attr_length (from
);
17821 /* If there is a jump table, add its length. */
17822 if (tablejump_p (from
, NULL
, &tmp
))
17824 count
+= get_jump_table_size (tmp
);
17826 /* Jump tables aren't in a basic block, so base the cost on
17827 the dispatch insn. If we select this location, we will
17828 still put the pool after the table. */
17829 new_cost
= arm_barrier_cost (from
);
17831 if (count
< max_count
17832 && (!selected
|| new_cost
<= selected_cost
))
17835 selected_cost
= new_cost
;
17836 selected_address
= fix
->address
+ count
;
17839 /* Continue after the dispatch table. */
17840 from
= NEXT_INSN (tmp
);
17844 new_cost
= arm_barrier_cost (from
);
17846 if (count
< max_count
17847 && (!selected
|| new_cost
<= selected_cost
))
17850 selected_cost
= new_cost
;
17851 selected_address
= fix
->address
+ count
;
17854 from
= NEXT_INSN (from
);
17857 /* Make sure that we found a place to insert the jump. */
17858 gcc_assert (selected
);
17860 /* Create a new JUMP_INSN that branches around a barrier. */
17861 from
= emit_jump_insn_after (gen_jump (label
), selected
);
17862 JUMP_LABEL (from
) = label
;
17863 barrier
= emit_barrier_after (from
);
17864 emit_label_after (label
, barrier
);
17866 /* Create a minipool barrier entry for the new barrier. */
17867 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
17868 new_fix
->insn
= barrier
;
17869 new_fix
->address
= selected_address
;
17870 new_fix
->next
= fix
->next
;
17871 fix
->next
= new_fix
;
17876 /* Record that there is a natural barrier in the insn stream at
17879 push_minipool_barrier (rtx_insn
*insn
, HOST_WIDE_INT address
)
17881 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
17884 fix
->address
= address
;
17887 if (minipool_fix_head
!= NULL
)
17888 minipool_fix_tail
->next
= fix
;
17890 minipool_fix_head
= fix
;
17892 minipool_fix_tail
= fix
;
17895 /* Record INSN, which will need fixing up to load a value from the
17896 minipool. ADDRESS is the offset of the insn since the start of the
17897 function; LOC is a pointer to the part of the insn which requires
17898 fixing; VALUE is the constant that must be loaded, which is of type
17901 push_minipool_fix (rtx_insn
*insn
, HOST_WIDE_INT address
, rtx
*loc
,
17902 machine_mode mode
, rtx value
)
17904 gcc_assert (!arm_disable_literal_pool
);
17905 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
17908 fix
->address
= address
;
17911 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
17912 fix
->value
= value
;
17913 fix
->forwards
= get_attr_pool_range (insn
);
17914 fix
->backwards
= get_attr_neg_pool_range (insn
);
17915 fix
->minipool
= NULL
;
17917 /* If an insn doesn't have a range defined for it, then it isn't
17918 expecting to be reworked by this code. Better to stop now than
17919 to generate duff assembly code. */
17920 gcc_assert (fix
->forwards
|| fix
->backwards
);
17922 /* If an entry requires 8-byte alignment then assume all constant pools
17923 require 4 bytes of padding. Trying to do this later on a per-pool
17924 basis is awkward because existing pool entries have to be modified. */
17925 if (ARM_DOUBLEWORD_ALIGN
&& fix
->fix_size
>= 8)
17930 fprintf (dump_file
,
17931 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
17932 GET_MODE_NAME (mode
),
17933 INSN_UID (insn
), (unsigned long) address
,
17934 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
17935 arm_print_value (dump_file
, fix
->value
);
17936 fprintf (dump_file
, "\n");
17939 /* Add it to the chain of fixes. */
17942 if (minipool_fix_head
!= NULL
)
17943 minipool_fix_tail
->next
= fix
;
17945 minipool_fix_head
= fix
;
17947 minipool_fix_tail
= fix
;
17950 /* Return maximum allowed cost of synthesizing a 64-bit constant VAL inline.
17951 Returns the number of insns needed, or 99 if we always want to synthesize
17954 arm_max_const_double_inline_cost ()
17956 return ((optimize_size
|| arm_ld_sched
) ? 3 : 4);
17959 /* Return the cost of synthesizing a 64-bit constant VAL inline.
17960 Returns the number of insns needed, or 99 if we don't know how to
17963 arm_const_double_inline_cost (rtx val
)
17965 rtx lowpart
, highpart
;
17968 mode
= GET_MODE (val
);
17970 if (mode
== VOIDmode
)
17973 gcc_assert (GET_MODE_SIZE (mode
) == 8);
17975 lowpart
= gen_lowpart (SImode
, val
);
17976 highpart
= gen_highpart_mode (SImode
, mode
, val
);
17978 gcc_assert (CONST_INT_P (lowpart
));
17979 gcc_assert (CONST_INT_P (highpart
));
17981 return (arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (lowpart
),
17982 NULL_RTX
, NULL_RTX
, 0, 0)
17983 + arm_gen_constant (SET
, SImode
, NULL_RTX
, INTVAL (highpart
),
17984 NULL_RTX
, NULL_RTX
, 0, 0));
17987 /* Cost of loading a SImode constant. */
17989 arm_const_inline_cost (enum rtx_code code
, rtx val
)
17991 return arm_gen_constant (code
, SImode
, NULL_RTX
, INTVAL (val
),
17992 NULL_RTX
, NULL_RTX
, 1, 0);
17995 /* Return true if it is worthwhile to split a 64-bit constant into two
17996 32-bit operations. This is the case if optimizing for size, or
17997 if we have load delay slots, or if one 32-bit part can be done with
17998 a single data operation. */
18000 arm_const_double_by_parts (rtx val
)
18002 machine_mode mode
= GET_MODE (val
);
18005 if (optimize_size
|| arm_ld_sched
)
18008 if (mode
== VOIDmode
)
18011 part
= gen_highpart_mode (SImode
, mode
, val
);
18013 gcc_assert (CONST_INT_P (part
));
18015 if (const_ok_for_arm (INTVAL (part
))
18016 || const_ok_for_arm (~INTVAL (part
)))
18019 part
= gen_lowpart (SImode
, val
);
18021 gcc_assert (CONST_INT_P (part
));
18023 if (const_ok_for_arm (INTVAL (part
))
18024 || const_ok_for_arm (~INTVAL (part
)))
18030 /* Return true if it is possible to inline both the high and low parts
18031 of a 64-bit constant into 32-bit data processing instructions. */
18033 arm_const_double_by_immediates (rtx val
)
18035 machine_mode mode
= GET_MODE (val
);
18038 if (mode
== VOIDmode
)
18041 part
= gen_highpart_mode (SImode
, mode
, val
);
18043 gcc_assert (CONST_INT_P (part
));
18045 if (!const_ok_for_arm (INTVAL (part
)))
18048 part
= gen_lowpart (SImode
, val
);
18050 gcc_assert (CONST_INT_P (part
));
18052 if (!const_ok_for_arm (INTVAL (part
)))
18058 /* Scan INSN and note any of its operands that need fixing.
18059 If DO_PUSHES is false we do not actually push any of the fixups
18062 note_invalid_constants (rtx_insn
*insn
, HOST_WIDE_INT address
, int do_pushes
)
18066 extract_constrain_insn (insn
);
18068 if (recog_data
.n_alternatives
== 0)
18071 /* Fill in recog_op_alt with information about the constraints of
18073 preprocess_constraints (insn
);
18075 const operand_alternative
*op_alt
= which_op_alt ();
18076 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
18078 /* Things we need to fix can only occur in inputs. */
18079 if (recog_data
.operand_type
[opno
] != OP_IN
)
18082 /* If this alternative is a memory reference, then any mention
18083 of constants in this alternative is really to fool reload
18084 into allowing us to accept one there. We need to fix them up
18085 now so that we output the right code. */
18086 if (op_alt
[opno
].memory_ok
)
18088 rtx op
= recog_data
.operand
[opno
];
18090 if (CONSTANT_P (op
))
18093 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
18094 recog_data
.operand_mode
[opno
], op
);
18096 else if (MEM_P (op
)
18097 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
18098 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
18102 rtx cop
= avoid_constant_pool_reference (op
);
18104 /* Casting the address of something to a mode narrower
18105 than a word can cause avoid_constant_pool_reference()
18106 to return the pool reference itself. That's no good to
18107 us here. Lets just hope that we can use the
18108 constant pool value directly. */
18110 cop
= get_pool_constant (XEXP (op
, 0));
18112 push_minipool_fix (insn
, address
,
18113 recog_data
.operand_loc
[opno
],
18114 recog_data
.operand_mode
[opno
], cop
);
18124 /* This function computes the clear mask and PADDING_BITS_TO_CLEAR for structs
18125 and unions in the context of ARMv8-M Security Extensions. It is used as a
18126 helper function for both 'cmse_nonsecure_call' and 'cmse_nonsecure_entry'
18127 functions. The PADDING_BITS_TO_CLEAR pointer can be the base to either one
18128 or four masks, depending on whether it is being computed for a
18129 'cmse_nonsecure_entry' return value or a 'cmse_nonsecure_call' argument
18130 respectively. The tree for the type of the argument or a field within an
18131 argument is passed in ARG_TYPE, the current register this argument or field
18132 starts in is kept in the pointer REGNO and updated accordingly, the bit this
18133 argument or field starts at is passed in STARTING_BIT and the last used bit
18134 is kept in LAST_USED_BIT which is also updated accordingly. */
18136 static unsigned HOST_WIDE_INT
18137 comp_not_to_clear_mask_str_un (tree arg_type
, int * regno
,
18138 uint32_t * padding_bits_to_clear
,
18139 unsigned starting_bit
, int * last_used_bit
)
18142 unsigned HOST_WIDE_INT not_to_clear_reg_mask
= 0;
18144 if (TREE_CODE (arg_type
) == RECORD_TYPE
)
18146 unsigned current_bit
= starting_bit
;
18148 long int offset
, size
;
18151 field
= TYPE_FIELDS (arg_type
);
18154 /* The offset within a structure is always an offset from
18155 the start of that structure. Make sure we take that into the
18156 calculation of the register based offset that we use here. */
18157 offset
= starting_bit
;
18158 offset
+= TREE_INT_CST_ELT (DECL_FIELD_BIT_OFFSET (field
), 0);
18161 /* This is the actual size of the field, for bitfields this is the
18162 bitfield width and not the container size. */
18163 size
= TREE_INT_CST_ELT (DECL_SIZE (field
), 0);
18165 if (*last_used_bit
!= offset
)
18167 if (offset
< *last_used_bit
)
18169 /* This field's offset is before the 'last_used_bit', that
18170 means this field goes on the next register. So we need to
18171 pad the rest of the current register and increase the
18172 register number. */
18174 mask
= ((uint32_t)-1) - ((uint32_t) 1 << *last_used_bit
);
18177 padding_bits_to_clear
[*regno
] |= mask
;
18178 not_to_clear_reg_mask
|= HOST_WIDE_INT_1U
<< *regno
;
18183 /* Otherwise we pad the bits between the last field's end and
18184 the start of the new field. */
18187 mask
= ((uint32_t)-1) >> (32 - offset
);
18188 mask
-= ((uint32_t) 1 << *last_used_bit
) - 1;
18189 padding_bits_to_clear
[*regno
] |= mask
;
18191 current_bit
= offset
;
18194 /* Calculate further padding bits for inner structs/unions too. */
18195 if (RECORD_OR_UNION_TYPE_P (TREE_TYPE (field
)))
18197 *last_used_bit
= current_bit
;
18198 not_to_clear_reg_mask
18199 |= comp_not_to_clear_mask_str_un (TREE_TYPE (field
), regno
,
18200 padding_bits_to_clear
, offset
,
18205 /* Update 'current_bit' with this field's size. If the
18206 'current_bit' lies in a subsequent register, update 'regno' and
18207 reset 'current_bit' to point to the current bit in that new
18209 current_bit
+= size
;
18210 while (current_bit
>= 32)
18213 not_to_clear_reg_mask
|= HOST_WIDE_INT_1U
<< *regno
;
18216 *last_used_bit
= current_bit
;
18219 field
= TREE_CHAIN (field
);
18221 not_to_clear_reg_mask
|= HOST_WIDE_INT_1U
<< *regno
;
18223 else if (TREE_CODE (arg_type
) == UNION_TYPE
)
18225 tree field
, field_t
;
18226 int i
, regno_t
, field_size
;
18230 uint32_t padding_bits_to_clear_res
[NUM_ARG_REGS
]
18231 = {-1, -1, -1, -1};
18233 /* To compute the padding bits in a union we only consider bits as
18234 padding bits if they are always either a padding bit or fall outside a
18235 fields size for all fields in the union. */
18236 field
= TYPE_FIELDS (arg_type
);
18239 uint32_t padding_bits_to_clear_t
[NUM_ARG_REGS
]
18240 = {0U, 0U, 0U, 0U};
18241 int last_used_bit_t
= *last_used_bit
;
18243 field_t
= TREE_TYPE (field
);
18245 /* If the field's type is either a record or a union make sure to
18246 compute their padding bits too. */
18247 if (RECORD_OR_UNION_TYPE_P (field_t
))
18248 not_to_clear_reg_mask
18249 |= comp_not_to_clear_mask_str_un (field_t
, ®no_t
,
18250 &padding_bits_to_clear_t
[0],
18251 starting_bit
, &last_used_bit_t
);
18254 field_size
= TREE_INT_CST_ELT (DECL_SIZE (field
), 0);
18255 regno_t
= (field_size
/ 32) + *regno
;
18256 last_used_bit_t
= (starting_bit
+ field_size
) % 32;
18259 for (i
= *regno
; i
< regno_t
; i
++)
18261 /* For all but the last register used by this field only keep the
18262 padding bits that were padding bits in this field. */
18263 padding_bits_to_clear_res
[i
] &= padding_bits_to_clear_t
[i
];
18266 /* For the last register, keep all padding bits that were padding
18267 bits in this field and any padding bits that are still valid
18268 as padding bits but fall outside of this field's size. */
18269 mask
= (((uint32_t) -1) - ((uint32_t) 1 << last_used_bit_t
)) + 1;
18270 padding_bits_to_clear_res
[regno_t
]
18271 &= padding_bits_to_clear_t
[regno_t
] | mask
;
18273 /* Update the maximum size of the fields in terms of registers used
18274 ('max_reg') and the 'last_used_bit' in said register. */
18275 if (max_reg
< regno_t
)
18278 max_bit
= last_used_bit_t
;
18280 else if (max_reg
== regno_t
&& max_bit
< last_used_bit_t
)
18281 max_bit
= last_used_bit_t
;
18283 field
= TREE_CHAIN (field
);
18286 /* Update the current padding_bits_to_clear using the intersection of the
18287 padding bits of all the fields. */
18288 for (i
=*regno
; i
< max_reg
; i
++)
18289 padding_bits_to_clear
[i
] |= padding_bits_to_clear_res
[i
];
18291 /* Do not keep trailing padding bits, we do not know yet whether this
18292 is the end of the argument. */
18293 mask
= ((uint32_t) 1 << max_bit
) - 1;
18294 padding_bits_to_clear
[max_reg
]
18295 |= padding_bits_to_clear_res
[max_reg
] & mask
;
18298 *last_used_bit
= max_bit
;
18301 /* This function should only be used for structs and unions. */
18302 gcc_unreachable ();
18304 return not_to_clear_reg_mask
;
18307 /* In the context of ARMv8-M Security Extensions, this function is used for both
18308 'cmse_nonsecure_call' and 'cmse_nonsecure_entry' functions to compute what
18309 registers are used when returning or passing arguments, which is then
18310 returned as a mask. It will also compute a mask to indicate padding/unused
18311 bits for each of these registers, and passes this through the
18312 PADDING_BITS_TO_CLEAR pointer. The tree of the argument type is passed in
18313 ARG_TYPE, the rtl representation of the argument is passed in ARG_RTX and
18314 the starting register used to pass this argument or return value is passed
18315 in REGNO. It makes use of 'comp_not_to_clear_mask_str_un' to compute these
18316 for struct and union types. */
18318 static unsigned HOST_WIDE_INT
18319 compute_not_to_clear_mask (tree arg_type
, rtx arg_rtx
, int regno
,
18320 uint32_t * padding_bits_to_clear
)
18323 int last_used_bit
= 0;
18324 unsigned HOST_WIDE_INT not_to_clear_mask
;
18326 if (RECORD_OR_UNION_TYPE_P (arg_type
))
18329 = comp_not_to_clear_mask_str_un (arg_type
, ®no
,
18330 padding_bits_to_clear
, 0,
18334 /* If the 'last_used_bit' is not zero, that means we are still using a
18335 part of the last 'regno'. In such cases we must clear the trailing
18336 bits. Otherwise we are not using regno and we should mark it as to
18338 if (last_used_bit
!= 0)
18339 padding_bits_to_clear
[regno
]
18340 |= ((uint32_t)-1) - ((uint32_t) 1 << last_used_bit
) + 1;
18342 not_to_clear_mask
&= ~(HOST_WIDE_INT_1U
<< regno
);
18346 not_to_clear_mask
= 0;
18347 /* We are not dealing with structs nor unions. So these arguments may be
18348 passed in floating point registers too. In some cases a BLKmode is
18349 used when returning or passing arguments in multiple VFP registers. */
18350 if (GET_MODE (arg_rtx
) == BLKmode
)
18355 /* This should really only occur when dealing with the hard-float
18357 gcc_assert (TARGET_HARD_FLOAT_ABI
);
18359 for (i
= 0; i
< XVECLEN (arg_rtx
, 0); i
++)
18361 reg
= XEXP (XVECEXP (arg_rtx
, 0, i
), 0);
18362 gcc_assert (REG_P (reg
));
18364 not_to_clear_mask
|= HOST_WIDE_INT_1U
<< REGNO (reg
);
18366 /* If we are dealing with DF mode, make sure we don't
18367 clear either of the registers it addresses. */
18368 arg_regs
= ARM_NUM_REGS (GET_MODE (reg
));
18371 unsigned HOST_WIDE_INT mask
;
18372 mask
= HOST_WIDE_INT_1U
<< (REGNO (reg
) + arg_regs
);
18373 mask
-= HOST_WIDE_INT_1U
<< REGNO (reg
);
18374 not_to_clear_mask
|= mask
;
18380 /* Otherwise we can rely on the MODE to determine how many registers
18381 are being used by this argument. */
18382 int arg_regs
= ARM_NUM_REGS (GET_MODE (arg_rtx
));
18383 not_to_clear_mask
|= HOST_WIDE_INT_1U
<< REGNO (arg_rtx
);
18386 unsigned HOST_WIDE_INT
18387 mask
= HOST_WIDE_INT_1U
<< (REGNO (arg_rtx
) + arg_regs
);
18388 mask
-= HOST_WIDE_INT_1U
<< REGNO (arg_rtx
);
18389 not_to_clear_mask
|= mask
;
18394 return not_to_clear_mask
;
18397 /* Clear registers secret before doing a cmse_nonsecure_call or returning from
18398 a cmse_nonsecure_entry function. TO_CLEAR_BITMAP indicates which registers
18399 are to be fully cleared, using the value in register CLEARING_REG if more
18400 efficient. The PADDING_BITS_LEN entries array PADDING_BITS_TO_CLEAR gives
18401 the bits that needs to be cleared in caller-saved core registers, with
18402 SCRATCH_REG used as a scratch register for that clearing.
18404 NOTE: one of three following assertions must hold:
18405 - SCRATCH_REG is a low register
18406 - CLEARING_REG is in the set of registers fully cleared (ie. its bit is set
18407 in TO_CLEAR_BITMAP)
18408 - CLEARING_REG is a low register. */
18411 cmse_clear_registers (sbitmap to_clear_bitmap
, uint32_t *padding_bits_to_clear
,
18412 int padding_bits_len
, rtx scratch_reg
, rtx clearing_reg
)
18414 bool saved_clearing
= false;
18415 rtx saved_clearing_reg
= NULL_RTX
;
18416 int i
, regno
, clearing_regno
, minregno
= R0_REGNUM
, maxregno
= minregno
- 1;
18418 gcc_assert (arm_arch_cmse
);
18420 if (!bitmap_empty_p (to_clear_bitmap
))
18422 minregno
= bitmap_first_set_bit (to_clear_bitmap
);
18423 maxregno
= bitmap_last_set_bit (to_clear_bitmap
);
18425 clearing_regno
= REGNO (clearing_reg
);
18427 /* Clear padding bits. */
18428 gcc_assert (padding_bits_len
<= NUM_ARG_REGS
);
18429 for (i
= 0, regno
= R0_REGNUM
; i
< padding_bits_len
; i
++, regno
++)
18432 rtx rtx16
, dest
, cleared_reg
= gen_rtx_REG (SImode
, regno
);
18434 if (padding_bits_to_clear
[i
] == 0)
18437 /* If this is a Thumb-1 target and SCRATCH_REG is not a low register, use
18438 CLEARING_REG as scratch. */
18440 && REGNO (scratch_reg
) > LAST_LO_REGNUM
)
18442 /* clearing_reg is not to be cleared, copy its value into scratch_reg
18443 such that we can use clearing_reg to clear the unused bits in the
18445 if ((clearing_regno
> maxregno
18446 || !bitmap_bit_p (to_clear_bitmap
, clearing_regno
))
18447 && !saved_clearing
)
18449 gcc_assert (clearing_regno
<= LAST_LO_REGNUM
);
18450 emit_move_insn (scratch_reg
, clearing_reg
);
18451 saved_clearing
= true;
18452 saved_clearing_reg
= scratch_reg
;
18454 scratch_reg
= clearing_reg
;
18457 /* Fill the lower half of the negated padding_bits_to_clear[i]. */
18458 mask
= (~padding_bits_to_clear
[i
]) & 0xFFFF;
18459 emit_move_insn (scratch_reg
, gen_int_mode (mask
, SImode
));
18461 /* Fill the top half of the negated padding_bits_to_clear[i]. */
18462 mask
= (~padding_bits_to_clear
[i
]) >> 16;
18463 rtx16
= gen_int_mode (16, SImode
);
18464 dest
= gen_rtx_ZERO_EXTRACT (SImode
, scratch_reg
, rtx16
, rtx16
);
18466 emit_insn (gen_rtx_SET (dest
, gen_int_mode (mask
, SImode
)));
18468 emit_insn (gen_andsi3 (cleared_reg
, cleared_reg
, scratch_reg
));
18470 if (saved_clearing
)
18471 emit_move_insn (clearing_reg
, saved_clearing_reg
);
18474 /* Clear full registers. */
18476 if (TARGET_HAVE_FPCXT_CMSE
)
18479 int i
, j
, k
, nb_regs
;
18480 rtx use_seq
, par
, reg
, set
, vunspec
;
18481 int to_clear_bitmap_size
= SBITMAP_SIZE (to_clear_bitmap
);
18482 auto_sbitmap
core_regs_bitmap (to_clear_bitmap_size
);
18483 auto_sbitmap
to_clear_core_bitmap (to_clear_bitmap_size
);
18485 for (i
= FIRST_VFP_REGNUM
; i
<= maxregno
; i
+= nb_regs
)
18487 /* Find next register to clear and exit if none. */
18488 for (; i
<= maxregno
&& !bitmap_bit_p (to_clear_bitmap
, i
); i
++);
18492 /* Compute number of consecutive registers to clear. */
18493 for (j
= i
; j
<= maxregno
&& bitmap_bit_p (to_clear_bitmap
, j
);
18497 /* Create VSCCLRM RTX pattern. */
18498 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nb_regs
+ 1));
18499 vunspec_vec
= gen_rtvec (1, gen_int_mode (0, SImode
));
18500 vunspec
= gen_rtx_UNSPEC_VOLATILE (SImode
, vunspec_vec
,
18501 VUNSPEC_VSCCLRM_VPR
);
18502 XVECEXP (par
, 0, 0) = vunspec
;
18504 /* Insert VFP register clearing RTX in the pattern. */
18506 for (k
= 1, j
= i
; j
<= maxregno
&& k
< nb_regs
+ 1; j
++)
18508 if (!bitmap_bit_p (to_clear_bitmap
, j
))
18511 reg
= gen_rtx_REG (SFmode
, j
);
18512 set
= gen_rtx_SET (reg
, const0_rtx
);
18513 XVECEXP (par
, 0, k
++) = set
;
18516 use_seq
= get_insns ();
18519 emit_insn_after (use_seq
, emit_insn (par
));
18522 /* Get set of core registers to clear. */
18523 bitmap_clear (core_regs_bitmap
);
18524 bitmap_set_range (core_regs_bitmap
, R0_REGNUM
,
18525 IP_REGNUM
- R0_REGNUM
+ 1);
18526 bitmap_and (to_clear_core_bitmap
, to_clear_bitmap
,
18528 gcc_assert (!bitmap_empty_p (to_clear_core_bitmap
));
18530 if (bitmap_empty_p (to_clear_core_bitmap
))
18533 /* Create clrm RTX pattern. */
18534 nb_regs
= bitmap_count_bits (to_clear_core_bitmap
);
18535 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nb_regs
+ 2));
18537 /* Insert core register clearing RTX in the pattern. */
18539 for (j
= 0, i
= minregno
; j
< nb_regs
; i
++)
18541 if (!bitmap_bit_p (to_clear_core_bitmap
, i
))
18544 reg
= gen_rtx_REG (SImode
, i
);
18545 set
= gen_rtx_SET (reg
, const0_rtx
);
18546 XVECEXP (par
, 0, j
++) = set
;
18550 /* Insert APSR register clearing RTX in the pattern
18551 * along with clobbering CC. */
18552 vunspec_vec
= gen_rtvec (1, gen_int_mode (0, SImode
));
18553 vunspec
= gen_rtx_UNSPEC_VOLATILE (SImode
, vunspec_vec
,
18554 VUNSPEC_CLRM_APSR
);
18556 XVECEXP (par
, 0, j
++) = vunspec
;
18558 rtx ccreg
= gen_rtx_REG (CCmode
, CC_REGNUM
);
18559 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, ccreg
);
18560 XVECEXP (par
, 0, j
) = clobber
;
18562 use_seq
= get_insns ();
18565 emit_insn_after (use_seq
, emit_insn (par
));
18569 /* If not marked for clearing, clearing_reg already does not contain
18571 if (clearing_regno
<= maxregno
18572 && bitmap_bit_p (to_clear_bitmap
, clearing_regno
))
18574 emit_move_insn (clearing_reg
, const0_rtx
);
18575 emit_use (clearing_reg
);
18576 bitmap_clear_bit (to_clear_bitmap
, clearing_regno
);
18579 for (regno
= minregno
; regno
<= maxregno
; regno
++)
18581 if (!bitmap_bit_p (to_clear_bitmap
, regno
))
18584 if (IS_VFP_REGNUM (regno
))
18586 /* If regno is an even vfp register and its successor is also to
18587 be cleared, use vmov. */
18588 if (TARGET_VFP_DOUBLE
18589 && VFP_REGNO_OK_FOR_DOUBLE (regno
)
18590 && bitmap_bit_p (to_clear_bitmap
, regno
+ 1))
18592 emit_move_insn (gen_rtx_REG (DFmode
, regno
),
18593 CONST1_RTX (DFmode
));
18594 emit_use (gen_rtx_REG (DFmode
, regno
));
18599 emit_move_insn (gen_rtx_REG (SFmode
, regno
),
18600 CONST1_RTX (SFmode
));
18601 emit_use (gen_rtx_REG (SFmode
, regno
));
18606 emit_move_insn (gen_rtx_REG (SImode
, regno
), clearing_reg
);
18607 emit_use (gen_rtx_REG (SImode
, regno
));
18613 /* Clear core and caller-saved VFP registers not used to pass arguments before
18614 a cmse_nonsecure_call. Saving, clearing and restoring of VFP callee-saved
18615 registers is done in the __gnu_cmse_nonsecure_call libcall. See
18616 libgcc/config/arm/cmse_nonsecure_call.S. */
18619 cmse_nonsecure_call_inline_register_clear (void)
18623 FOR_EACH_BB_FN (bb
, cfun
)
18627 FOR_BB_INSNS (bb
, insn
)
18629 bool clear_callee_saved
= TARGET_HAVE_FPCXT_CMSE
;
18630 /* frame = VFP regs + FPSCR + VPR. */
18631 unsigned lazy_store_stack_frame_size
18632 = (LAST_VFP_REGNUM
- FIRST_VFP_REGNUM
+ 1 + 2) * UNITS_PER_WORD
;
18633 unsigned long callee_saved_mask
18634 = ((1 << (LAST_HI_REGNUM
+ 1)) - 1)
18635 & ~((1 << (LAST_ARG_REGNUM
+ 1)) - 1);
18636 unsigned address_regnum
, regno
;
18637 unsigned max_int_regno
18638 = clear_callee_saved
? IP_REGNUM
: LAST_ARG_REGNUM
;
18639 unsigned max_fp_regno
18640 = TARGET_HAVE_FPCXT_CMSE
? LAST_VFP_REGNUM
: D7_VFP_REGNUM
;
18642 = TARGET_HARD_FLOAT_ABI
? max_fp_regno
: max_int_regno
;
18643 auto_sbitmap
to_clear_bitmap (maxregno
+ 1);
18645 rtx pat
, call
, unspec
, clearing_reg
, ip_reg
, shift
;
18647 CUMULATIVE_ARGS args_so_far_v
;
18648 cumulative_args_t args_so_far
;
18649 tree arg_type
, fntype
;
18650 bool first_param
= true, lazy_fpclear
= !TARGET_HARD_FLOAT_ABI
;
18651 function_args_iterator args_iter
;
18652 uint32_t padding_bits_to_clear
[4] = {0U, 0U, 0U, 0U};
18654 if (!NONDEBUG_INSN_P (insn
))
18657 if (!CALL_P (insn
))
18660 pat
= PATTERN (insn
);
18661 gcc_assert (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 0);
18662 call
= XVECEXP (pat
, 0, 0);
18664 /* Get the real call RTX if the insn sets a value, ie. returns. */
18665 if (GET_CODE (call
) == SET
)
18666 call
= SET_SRC (call
);
18668 /* Check if it is a cmse_nonsecure_call. */
18669 unspec
= XEXP (call
, 0);
18670 if (GET_CODE (unspec
) != UNSPEC
18671 || XINT (unspec
, 1) != UNSPEC_NONSECURE_MEM
)
18674 /* Mark registers that needs to be cleared. Those that holds a
18675 parameter are removed from the set further below. */
18676 bitmap_clear (to_clear_bitmap
);
18677 bitmap_set_range (to_clear_bitmap
, R0_REGNUM
,
18678 max_int_regno
- R0_REGNUM
+ 1);
18680 /* Only look at the caller-saved floating point registers in case of
18681 -mfloat-abi=hard. For -mfloat-abi=softfp we will be using the
18682 lazy store and loads which clear both caller- and callee-saved
18686 auto_sbitmap
float_bitmap (maxregno
+ 1);
18688 bitmap_clear (float_bitmap
);
18689 bitmap_set_range (float_bitmap
, FIRST_VFP_REGNUM
,
18690 max_fp_regno
- FIRST_VFP_REGNUM
+ 1);
18691 bitmap_ior (to_clear_bitmap
, to_clear_bitmap
, float_bitmap
);
18694 /* Make sure the register used to hold the function address is not
18696 address
= RTVEC_ELT (XVEC (unspec
, 0), 0);
18697 gcc_assert (MEM_P (address
));
18698 gcc_assert (REG_P (XEXP (address
, 0)));
18699 address_regnum
= REGNO (XEXP (address
, 0));
18700 if (address_regnum
<= max_int_regno
)
18701 bitmap_clear_bit (to_clear_bitmap
, address_regnum
);
18703 /* Set basic block of call insn so that df rescan is performed on
18704 insns inserted here. */
18705 set_block_for_insn (insn
, bb
);
18706 df_set_flags (DF_DEFER_INSN_RESCAN
);
18709 /* Make sure the scheduler doesn't schedule other insns beyond
18711 emit_insn (gen_blockage ());
18713 /* Walk through all arguments and clear registers appropriately.
18715 fntype
= TREE_TYPE (MEM_EXPR (address
));
18716 arm_init_cumulative_args (&args_so_far_v
, fntype
, NULL_RTX
,
18718 args_so_far
= pack_cumulative_args (&args_so_far_v
);
18719 FOREACH_FUNCTION_ARGS (fntype
, arg_type
, args_iter
)
18722 uint64_t to_clear_args_mask
;
18724 if (VOID_TYPE_P (arg_type
))
18727 function_arg_info
arg (arg_type
, /*named=*/true);
18729 /* ??? We should advance after processing the argument and pass
18730 the argument we're advancing past. */
18731 arm_function_arg_advance (args_so_far
, arg
);
18733 arg_rtx
= arm_function_arg (args_so_far
, arg
);
18734 gcc_assert (REG_P (arg_rtx
));
18736 = compute_not_to_clear_mask (arg_type
, arg_rtx
,
18738 &padding_bits_to_clear
[0]);
18739 if (to_clear_args_mask
)
18741 for (regno
= R0_REGNUM
; regno
<= maxregno
; regno
++)
18743 if (to_clear_args_mask
& (1ULL << regno
))
18744 bitmap_clear_bit (to_clear_bitmap
, regno
);
18748 first_param
= false;
18751 /* We use right shift and left shift to clear the LSB of the address
18752 we jump to instead of using bic, to avoid having to use an extra
18753 register on Thumb-1. */
18754 clearing_reg
= XEXP (address
, 0);
18755 shift
= gen_rtx_LSHIFTRT (SImode
, clearing_reg
, const1_rtx
);
18756 emit_insn (gen_rtx_SET (clearing_reg
, shift
));
18757 shift
= gen_rtx_ASHIFT (SImode
, clearing_reg
, const1_rtx
);
18758 emit_insn (gen_rtx_SET (clearing_reg
, shift
));
18760 if (clear_callee_saved
)
18763 emit_multi_reg_push (callee_saved_mask
, callee_saved_mask
);
18764 /* Disable frame debug info in push because it needs to be
18765 disabled for pop (see below). */
18766 RTX_FRAME_RELATED_P (push_insn
) = 0;
18768 /* Lazy store multiple. */
18772 rtx_insn
*add_insn
;
18774 imm
= gen_int_mode (- lazy_store_stack_frame_size
, SImode
);
18775 add_insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
18776 stack_pointer_rtx
, imm
));
18777 arm_add_cfa_adjust_cfa_note (add_insn
,
18778 - lazy_store_stack_frame_size
,
18780 stack_pointer_rtx
);
18781 emit_insn (gen_lazy_store_multiple_insn (stack_pointer_rtx
));
18783 /* Save VFP callee-saved registers. */
18786 vfp_emit_fstmd (D7_VFP_REGNUM
+ 1,
18787 (max_fp_regno
- D7_VFP_REGNUM
) / 2);
18788 /* Disable frame debug info in push because it needs to be
18789 disabled for vpop (see below). */
18790 RTX_FRAME_RELATED_P (get_last_insn ()) = 0;
18794 /* Clear caller-saved registers that leak before doing a non-secure
18796 ip_reg
= gen_rtx_REG (SImode
, IP_REGNUM
);
18797 cmse_clear_registers (to_clear_bitmap
, padding_bits_to_clear
,
18798 NUM_ARG_REGS
, ip_reg
, clearing_reg
);
18800 seq
= get_insns ();
18802 emit_insn_before (seq
, insn
);
18804 if (TARGET_HAVE_FPCXT_CMSE
)
18806 rtx_insn
*last
, *pop_insn
, *after
= insn
;
18810 /* Lazy load multiple done as part of libcall in Armv8-M. */
18813 rtx imm
= gen_int_mode (lazy_store_stack_frame_size
, SImode
);
18814 emit_insn (gen_lazy_load_multiple_insn (stack_pointer_rtx
));
18815 rtx_insn
*add_insn
=
18816 emit_insn (gen_addsi3 (stack_pointer_rtx
,
18817 stack_pointer_rtx
, imm
));
18818 arm_add_cfa_adjust_cfa_note (add_insn
,
18819 lazy_store_stack_frame_size
,
18821 stack_pointer_rtx
);
18823 /* Restore VFP callee-saved registers. */
18826 int nb_callee_saved_vfp_regs
=
18827 (max_fp_regno
- D7_VFP_REGNUM
) / 2;
18828 arm_emit_vfp_multi_reg_pop (D7_VFP_REGNUM
+ 1,
18829 nb_callee_saved_vfp_regs
,
18830 stack_pointer_rtx
);
18831 /* Disable frame debug info in vpop because the SP adjustment
18832 is made using a CFA adjustment note while CFA used is
18833 sometimes R7. This then causes an assert failure in the
18834 CFI note creation code. */
18835 RTX_FRAME_RELATED_P (get_last_insn ()) = 0;
18838 arm_emit_multi_reg_pop (callee_saved_mask
);
18839 pop_insn
= get_last_insn ();
18841 /* Disable frame debug info in pop because they reset the state
18842 of popped registers to what it was at the beginning of the
18843 function, before the prologue. This leads to incorrect state
18844 when doing the pop after the nonsecure call for registers that
18845 are pushed both in prologue and before the nonsecure call.
18847 It also occasionally triggers an assert failure in CFI note
18848 creation code when there are two codepaths to the epilogue,
18849 one of which does not go through the nonsecure call.
18850 Obviously this mean that debugging between the push and pop is
18852 RTX_FRAME_RELATED_P (pop_insn
) = 0;
18854 seq
= get_insns ();
18855 last
= get_last_insn ();
18858 emit_insn_after (seq
, after
);
18860 /* Skip pop we have just inserted after nonsecure call, we know
18861 it does not contain a nonsecure call. */
18868 /* Rewrite move insn into subtract of 0 if the condition codes will
18869 be useful in next conditional jump insn. */
18872 thumb1_reorg (void)
18876 FOR_EACH_BB_FN (bb
, cfun
)
18879 rtx cmp
, op0
, op1
, set
= NULL
;
18880 rtx_insn
*prev
, *insn
= BB_END (bb
);
18881 bool insn_clobbered
= false;
18883 while (insn
!= BB_HEAD (bb
) && !NONDEBUG_INSN_P (insn
))
18884 insn
= PREV_INSN (insn
);
18886 /* Find the last cbranchsi4_insn in basic block BB. */
18887 if (insn
== BB_HEAD (bb
)
18888 || INSN_CODE (insn
) != CODE_FOR_cbranchsi4_insn
)
18891 /* Get the register with which we are comparing. */
18892 cmp
= XEXP (SET_SRC (PATTERN (insn
)), 0);
18893 op0
= XEXP (cmp
, 0);
18894 op1
= XEXP (cmp
, 1);
18896 /* Check that comparison is against ZERO. */
18897 if (!CONST_INT_P (op1
) || INTVAL (op1
) != 0)
18900 /* Find the first flag setting insn before INSN in basic block BB. */
18901 gcc_assert (insn
!= BB_HEAD (bb
));
18902 for (prev
= PREV_INSN (insn
);
18904 && prev
!= BB_HEAD (bb
)
18906 || DEBUG_INSN_P (prev
)
18907 || ((set
= single_set (prev
)) != NULL
18908 && get_attr_conds (prev
) == CONDS_NOCOND
)));
18909 prev
= PREV_INSN (prev
))
18911 if (reg_set_p (op0
, prev
))
18912 insn_clobbered
= true;
18915 /* Skip if op0 is clobbered by insn other than prev. */
18916 if (insn_clobbered
)
18922 dest
= SET_DEST (set
);
18923 src
= SET_SRC (set
);
18924 if (!low_register_operand (dest
, SImode
)
18925 || !low_register_operand (src
, SImode
))
18928 /* Rewrite move into subtract of 0 if its operand is compared with ZERO
18929 in INSN. Both src and dest of the move insn are checked. */
18930 if (REGNO (op0
) == REGNO (src
) || REGNO (op0
) == REGNO (dest
))
18932 dest
= copy_rtx (dest
);
18933 src
= copy_rtx (src
);
18934 src
= gen_rtx_MINUS (SImode
, src
, const0_rtx
);
18935 PATTERN (prev
) = gen_rtx_SET (dest
, src
);
18936 INSN_CODE (prev
) = -1;
18937 /* Set test register in INSN to dest. */
18938 XEXP (cmp
, 0) = copy_rtx (dest
);
18939 INSN_CODE (insn
) = -1;
18944 /* Convert instructions to their cc-clobbering variant if possible, since
18945 that allows us to use smaller encodings. */
18948 thumb2_reorg (void)
18953 INIT_REG_SET (&live
);
18955 /* We are freeing block_for_insn in the toplev to keep compatibility
18956 with old MDEP_REORGS that are not CFG based. Recompute it now. */
18957 compute_bb_for_insn ();
18960 enum Convert_Action
{SKIP
, CONV
, SWAP_CONV
};
18962 FOR_EACH_BB_FN (bb
, cfun
)
18964 if ((current_tune
->disparage_flag_setting_t16_encodings
18965 == tune_params::DISPARAGE_FLAGS_ALL
)
18966 && optimize_bb_for_speed_p (bb
))
18970 Convert_Action action
= SKIP
;
18971 Convert_Action action_for_partial_flag_setting
18972 = ((current_tune
->disparage_flag_setting_t16_encodings
18973 != tune_params::DISPARAGE_FLAGS_NEITHER
)
18974 && optimize_bb_for_speed_p (bb
))
18977 COPY_REG_SET (&live
, DF_LR_OUT (bb
));
18978 df_simulate_initialize_backwards (bb
, &live
);
18979 FOR_BB_INSNS_REVERSE (bb
, insn
)
18981 if (NONJUMP_INSN_P (insn
)
18982 && !REGNO_REG_SET_P (&live
, CC_REGNUM
)
18983 && GET_CODE (PATTERN (insn
)) == SET
)
18986 rtx pat
= PATTERN (insn
);
18987 rtx dst
= XEXP (pat
, 0);
18988 rtx src
= XEXP (pat
, 1);
18989 rtx op0
= NULL_RTX
, op1
= NULL_RTX
;
18991 if (UNARY_P (src
) || BINARY_P (src
))
18992 op0
= XEXP (src
, 0);
18994 if (BINARY_P (src
))
18995 op1
= XEXP (src
, 1);
18997 if (low_register_operand (dst
, SImode
))
18999 switch (GET_CODE (src
))
19002 /* Adding two registers and storing the result
19003 in the first source is already a 16-bit
19005 if (rtx_equal_p (dst
, op0
)
19006 && register_operand (op1
, SImode
))
19009 if (low_register_operand (op0
, SImode
))
19011 /* ADDS <Rd>,<Rn>,<Rm> */
19012 if (low_register_operand (op1
, SImode
))
19014 /* ADDS <Rdn>,#<imm8> */
19015 /* SUBS <Rdn>,#<imm8> */
19016 else if (rtx_equal_p (dst
, op0
)
19017 && CONST_INT_P (op1
)
19018 && IN_RANGE (INTVAL (op1
), -255, 255))
19020 /* ADDS <Rd>,<Rn>,#<imm3> */
19021 /* SUBS <Rd>,<Rn>,#<imm3> */
19022 else if (CONST_INT_P (op1
)
19023 && IN_RANGE (INTVAL (op1
), -7, 7))
19026 /* ADCS <Rd>, <Rn> */
19027 else if (GET_CODE (XEXP (src
, 0)) == PLUS
19028 && rtx_equal_p (XEXP (XEXP (src
, 0), 0), dst
)
19029 && low_register_operand (XEXP (XEXP (src
, 0), 1),
19031 && COMPARISON_P (op1
)
19032 && cc_register (XEXP (op1
, 0), VOIDmode
)
19033 && maybe_get_arm_condition_code (op1
) == ARM_CS
19034 && XEXP (op1
, 1) == const0_rtx
)
19039 /* RSBS <Rd>,<Rn>,#0
19040 Not handled here: see NEG below. */
19041 /* SUBS <Rd>,<Rn>,#<imm3>
19043 Not handled here: see PLUS above. */
19044 /* SUBS <Rd>,<Rn>,<Rm> */
19045 if (low_register_operand (op0
, SImode
)
19046 && low_register_operand (op1
, SImode
))
19051 /* MULS <Rdm>,<Rn>,<Rdm>
19052 As an exception to the rule, this is only used
19053 when optimizing for size since MULS is slow on all
19054 known implementations. We do not even want to use
19055 MULS in cold code, if optimizing for speed, so we
19056 test the global flag here. */
19057 if (!optimize_size
)
19059 /* Fall through. */
19063 /* ANDS <Rdn>,<Rm> */
19064 if (rtx_equal_p (dst
, op0
)
19065 && low_register_operand (op1
, SImode
))
19066 action
= action_for_partial_flag_setting
;
19067 else if (rtx_equal_p (dst
, op1
)
19068 && low_register_operand (op0
, SImode
))
19069 action
= action_for_partial_flag_setting
== SKIP
19070 ? SKIP
: SWAP_CONV
;
19076 /* ASRS <Rdn>,<Rm> */
19077 /* LSRS <Rdn>,<Rm> */
19078 /* LSLS <Rdn>,<Rm> */
19079 if (rtx_equal_p (dst
, op0
)
19080 && low_register_operand (op1
, SImode
))
19081 action
= action_for_partial_flag_setting
;
19082 /* ASRS <Rd>,<Rm>,#<imm5> */
19083 /* LSRS <Rd>,<Rm>,#<imm5> */
19084 /* LSLS <Rd>,<Rm>,#<imm5> */
19085 else if (low_register_operand (op0
, SImode
)
19086 && CONST_INT_P (op1
)
19087 && IN_RANGE (INTVAL (op1
), 0, 31))
19088 action
= action_for_partial_flag_setting
;
19092 /* RORS <Rdn>,<Rm> */
19093 if (rtx_equal_p (dst
, op0
)
19094 && low_register_operand (op1
, SImode
))
19095 action
= action_for_partial_flag_setting
;
19099 /* MVNS <Rd>,<Rm> */
19100 if (low_register_operand (op0
, SImode
))
19101 action
= action_for_partial_flag_setting
;
19105 /* NEGS <Rd>,<Rm> (a.k.a RSBS) */
19106 if (low_register_operand (op0
, SImode
))
19111 /* MOVS <Rd>,#<imm8> */
19112 if (CONST_INT_P (src
)
19113 && IN_RANGE (INTVAL (src
), 0, 255))
19114 action
= action_for_partial_flag_setting
;
19118 /* MOVS and MOV<c> with registers have different
19119 encodings, so are not relevant here. */
19127 if (action
!= SKIP
)
19129 rtx ccreg
= gen_rtx_REG (CCmode
, CC_REGNUM
);
19130 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, ccreg
);
19133 if (action
== SWAP_CONV
)
19135 src
= copy_rtx (src
);
19136 XEXP (src
, 0) = op1
;
19137 XEXP (src
, 1) = op0
;
19138 pat
= gen_rtx_SET (dst
, src
);
19139 vec
= gen_rtvec (2, pat
, clobber
);
19141 else /* action == CONV */
19142 vec
= gen_rtvec (2, pat
, clobber
);
19144 PATTERN (insn
) = gen_rtx_PARALLEL (VOIDmode
, vec
);
19145 INSN_CODE (insn
) = -1;
19149 if (NONDEBUG_INSN_P (insn
))
19150 df_simulate_one_insn_backwards (bb
, insn
, &live
);
19154 CLEAR_REG_SET (&live
);
19157 /* Gcc puts the pool in the wrong place for ARM, since we can only
19158 load addresses a limited distance around the pc. We do some
19159 special munging to move the constant pool values to the correct
19160 point in the code. */
19165 HOST_WIDE_INT address
= 0;
19169 cmse_nonsecure_call_inline_register_clear ();
19171 /* We cannot run the Thumb passes for thunks because there is no CFG. */
19172 if (cfun
->is_thunk
)
19174 else if (TARGET_THUMB1
)
19176 else if (TARGET_THUMB2
)
19179 /* Ensure all insns that must be split have been split at this point.
19180 Otherwise, the pool placement code below may compute incorrect
19181 insn lengths. Note that when optimizing, all insns have already
19182 been split at this point. */
19184 split_all_insns_noflow ();
19186 /* Make sure we do not attempt to create a literal pool even though it should
19187 no longer be necessary to create any. */
19188 if (arm_disable_literal_pool
)
19191 minipool_fix_head
= minipool_fix_tail
= NULL
;
19193 /* The first insn must always be a note, or the code below won't
19194 scan it properly. */
19195 insn
= get_insns ();
19196 gcc_assert (NOTE_P (insn
));
19199 /* Scan all the insns and record the operands that will need fixing. */
19200 for (insn
= next_nonnote_insn (insn
); insn
; insn
= next_nonnote_insn (insn
))
19202 if (BARRIER_P (insn
))
19203 push_minipool_barrier (insn
, address
);
19204 else if (INSN_P (insn
))
19206 rtx_jump_table_data
*table
;
19208 note_invalid_constants (insn
, address
, true);
19209 address
+= get_attr_length (insn
);
19211 /* If the insn is a vector jump, add the size of the table
19212 and skip the table. */
19213 if (tablejump_p (insn
, NULL
, &table
))
19215 address
+= get_jump_table_size (table
);
19219 else if (LABEL_P (insn
))
19220 /* Add the worst-case padding due to alignment. We don't add
19221 the _current_ padding because the minipool insertions
19222 themselves might change it. */
19223 address
+= get_label_padding (insn
);
19226 fix
= minipool_fix_head
;
19228 /* Now scan the fixups and perform the required changes. */
19233 Mfix
* last_added_fix
;
19234 Mfix
* last_barrier
= NULL
;
19237 /* Skip any further barriers before the next fix. */
19238 while (fix
&& BARRIER_P (fix
->insn
))
19241 /* No more fixes. */
19245 last_added_fix
= NULL
;
19247 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
19249 if (BARRIER_P (ftmp
->insn
))
19251 if (ftmp
->address
>= minipool_vector_head
->max_address
)
19254 last_barrier
= ftmp
;
19256 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
19259 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
19262 /* If we found a barrier, drop back to that; any fixes that we
19263 could have reached but come after the barrier will now go in
19264 the next mini-pool. */
19265 if (last_barrier
!= NULL
)
19267 /* Reduce the refcount for those fixes that won't go into this
19269 for (fdel
= last_barrier
->next
;
19270 fdel
&& fdel
!= ftmp
;
19273 fdel
->minipool
->refcount
--;
19274 fdel
->minipool
= NULL
;
19277 ftmp
= last_barrier
;
19281 /* ftmp is first fix that we can't fit into this pool and
19282 there no natural barriers that we could use. Insert a
19283 new barrier in the code somewhere between the previous
19284 fix and this one, and arrange to jump around it. */
19285 HOST_WIDE_INT max_address
;
19287 /* The last item on the list of fixes must be a barrier, so
19288 we can never run off the end of the list of fixes without
19289 last_barrier being set. */
19292 max_address
= minipool_vector_head
->max_address
;
19293 /* Check that there isn't another fix that is in range that
19294 we couldn't fit into this pool because the pool was
19295 already too large: we need to put the pool before such an
19296 instruction. The pool itself may come just after the
19297 fix because create_fix_barrier also allows space for a
19298 jump instruction. */
19299 if (ftmp
->address
< max_address
)
19300 max_address
= ftmp
->address
+ 1;
19302 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
19305 assign_minipool_offsets (last_barrier
);
19309 if (!BARRIER_P (ftmp
->insn
)
19310 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
19317 /* Scan over the fixes we have identified for this pool, fixing them
19318 up and adding the constants to the pool itself. */
19319 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
19320 this_fix
= this_fix
->next
)
19321 if (!BARRIER_P (this_fix
->insn
))
19324 = plus_constant (Pmode
,
19325 gen_rtx_LABEL_REF (VOIDmode
,
19326 minipool_vector_label
),
19327 this_fix
->minipool
->offset
);
19328 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
19331 dump_minipool (last_barrier
->insn
);
19335 /* From now on we must synthesize any constants that we can't handle
19336 directly. This can happen if the RTL gets split during final
19337 instruction generation. */
19338 cfun
->machine
->after_arm_reorg
= 1;
19340 /* Free the minipool memory. */
19341 obstack_free (&minipool_obstack
, minipool_startobj
);
19344 /* Routines to output assembly language. */
19346 /* Return string representation of passed in real value. */
19347 static const char *
19348 fp_const_from_val (REAL_VALUE_TYPE
*r
)
19350 if (!fp_consts_inited
)
19353 gcc_assert (real_equal (r
, &value_fp0
));
19357 /* OPERANDS[0] is the entire list of insns that constitute pop,
19358 OPERANDS[1] is the base register, RETURN_PC is true iff return insn
19359 is in the list, UPDATE is true iff the list contains explicit
19360 update of base register. */
19362 arm_output_multireg_pop (rtx
*operands
, bool return_pc
, rtx cond
, bool reverse
,
19368 const char *conditional
;
19369 int num_saves
= XVECLEN (operands
[0], 0);
19370 unsigned int regno
;
19371 unsigned int regno_base
= REGNO (operands
[1]);
19372 bool interrupt_p
= IS_INTERRUPT (arm_current_func_type ());
19375 offset
+= update
? 1 : 0;
19376 offset
+= return_pc
? 1 : 0;
19378 /* Is the base register in the list? */
19379 for (i
= offset
; i
< num_saves
; i
++)
19381 regno
= REGNO (XEXP (XVECEXP (operands
[0], 0, i
), 0));
19382 /* If SP is in the list, then the base register must be SP. */
19383 gcc_assert ((regno
!= SP_REGNUM
) || (regno_base
== SP_REGNUM
));
19384 /* If base register is in the list, there must be no explicit update. */
19385 if (regno
== regno_base
)
19386 gcc_assert (!update
);
19389 conditional
= reverse
? "%?%D0" : "%?%d0";
19390 /* Can't use POP if returning from an interrupt. */
19391 if ((regno_base
== SP_REGNUM
) && update
&& !(interrupt_p
&& return_pc
))
19392 sprintf (pattern
, "pop%s\t{", conditional
);
19395 /* Output ldmfd when the base register is SP, otherwise output ldmia.
19396 It's just a convention, their semantics are identical. */
19397 if (regno_base
== SP_REGNUM
)
19398 sprintf (pattern
, "ldmfd%s\t", conditional
);
19400 sprintf (pattern
, "ldmia%s\t", conditional
);
19402 sprintf (pattern
, "ldm%s\t", conditional
);
19404 strcat (pattern
, reg_names
[regno_base
]);
19406 strcat (pattern
, "!, {");
19408 strcat (pattern
, ", {");
19411 /* Output the first destination register. */
19413 reg_names
[REGNO (XEXP (XVECEXP (operands
[0], 0, offset
), 0))]);
19415 /* Output the rest of the destination registers. */
19416 for (i
= offset
+ 1; i
< num_saves
; i
++)
19418 strcat (pattern
, ", ");
19420 reg_names
[REGNO (XEXP (XVECEXP (operands
[0], 0, i
), 0))]);
19423 strcat (pattern
, "}");
19425 if (interrupt_p
&& return_pc
)
19426 strcat (pattern
, "^");
19428 output_asm_insn (pattern
, &cond
);
19432 /* Output the assembly for a store multiple. */
19435 vfp_output_vstmd (rtx
* operands
)
19441 rtx addr_reg
= REG_P (XEXP (operands
[0], 0))
19442 ? XEXP (operands
[0], 0)
19443 : XEXP (XEXP (operands
[0], 0), 0);
19444 bool push_p
= REGNO (addr_reg
) == SP_REGNUM
;
19447 strcpy (pattern
, "vpush%?.64\t{%P1");
19449 strcpy (pattern
, "vstmdb%?.64\t%m0!, {%P1");
19451 p
= strlen (pattern
);
19453 gcc_assert (REG_P (operands
[1]));
19455 base
= (REGNO (operands
[1]) - FIRST_VFP_REGNUM
) / 2;
19456 for (i
= 1; i
< XVECLEN (operands
[2], 0); i
++)
19458 p
+= sprintf (&pattern
[p
], ", d%d", base
+ i
);
19460 strcpy (&pattern
[p
], "}");
19462 output_asm_insn (pattern
, operands
);
19467 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
19468 number of bytes pushed. */
19471 vfp_emit_fstmd (int base_reg
, int count
)
19478 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
19479 register pairs are stored by a store multiple insn. We avoid this
19480 by pushing an extra pair. */
19481 if (count
== 2 && !arm_arch6
)
19483 if (base_reg
== LAST_VFP_REGNUM
- 3)
19488 /* FSTMD may not store more than 16 doubleword registers at once. Split
19489 larger stores into multiple parts (up to a maximum of two, in
19494 /* NOTE: base_reg is an internal register number, so each D register
19496 saved
= vfp_emit_fstmd (base_reg
+ 32, count
- 16);
19497 saved
+= vfp_emit_fstmd (base_reg
, 16);
19501 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
19502 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (count
+ 1));
19504 reg
= gen_rtx_REG (DFmode
, base_reg
);
19507 XVECEXP (par
, 0, 0)
19508 = gen_rtx_SET (gen_frame_mem
19510 gen_rtx_PRE_MODIFY (Pmode
,
19513 (Pmode
, stack_pointer_rtx
,
19516 gen_rtx_UNSPEC (BLKmode
,
19517 gen_rtvec (1, reg
),
19518 UNSPEC_PUSH_MULT
));
19520 tmp
= gen_rtx_SET (stack_pointer_rtx
,
19521 plus_constant (Pmode
, stack_pointer_rtx
, -(count
* 8)));
19522 RTX_FRAME_RELATED_P (tmp
) = 1;
19523 XVECEXP (dwarf
, 0, 0) = tmp
;
19525 tmp
= gen_rtx_SET (gen_frame_mem (DFmode
, stack_pointer_rtx
), reg
);
19526 RTX_FRAME_RELATED_P (tmp
) = 1;
19527 XVECEXP (dwarf
, 0, 1) = tmp
;
19529 for (i
= 1; i
< count
; i
++)
19531 reg
= gen_rtx_REG (DFmode
, base_reg
);
19533 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
19535 tmp
= gen_rtx_SET (gen_frame_mem (DFmode
,
19536 plus_constant (Pmode
,
19540 RTX_FRAME_RELATED_P (tmp
) = 1;
19541 XVECEXP (dwarf
, 0, i
+ 1) = tmp
;
19544 par
= emit_insn (par
);
19545 add_reg_note (par
, REG_FRAME_RELATED_EXPR
, dwarf
);
19546 RTX_FRAME_RELATED_P (par
) = 1;
19551 /* Returns true if -mcmse has been passed and the function pointed to by 'addr'
19552 has the cmse_nonsecure_call attribute and returns false otherwise. */
19555 detect_cmse_nonsecure_call (tree addr
)
19560 tree fntype
= TREE_TYPE (addr
);
19561 if (use_cmse
&& lookup_attribute ("cmse_nonsecure_call",
19562 TYPE_ATTRIBUTES (fntype
)))
19568 /* Emit a call instruction with pattern PAT. ADDR is the address of
19569 the call target. */
19572 arm_emit_call_insn (rtx pat
, rtx addr
, bool sibcall
)
19576 insn
= emit_call_insn (pat
);
19578 /* The PIC register is live on entry to VxWorks PIC PLT entries.
19579 If the call might use such an entry, add a use of the PIC register
19580 to the instruction's CALL_INSN_FUNCTION_USAGE. */
19581 if (TARGET_VXWORKS_RTP
19584 && SYMBOL_REF_P (addr
)
19585 && (SYMBOL_REF_DECL (addr
)
19586 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
19587 : !SYMBOL_REF_LOCAL_P (addr
)))
19589 require_pic_register (NULL_RTX
, false /*compute_now*/);
19590 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), cfun
->machine
->pic_reg
);
19595 rtx fdpic_reg
= gen_rtx_REG (Pmode
, FDPIC_REGNUM
);
19596 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), fdpic_reg
);
19599 if (TARGET_AAPCS_BASED
)
19601 /* For AAPCS, IP and CC can be clobbered by veneers inserted by the
19602 linker. We need to add an IP clobber to allow setting
19603 TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS to true. A CC clobber
19604 is not needed since it's a fixed register. */
19605 rtx
*fusage
= &CALL_INSN_FUNCTION_USAGE (insn
);
19606 clobber_reg (fusage
, gen_rtx_REG (word_mode
, IP_REGNUM
));
19610 /* Output a 'call' insn. */
19612 output_call (rtx
*operands
)
19614 gcc_assert (!arm_arch5t
); /* Patterns should call blx <reg> directly. */
19616 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
19617 if (REGNO (operands
[0]) == LR_REGNUM
)
19619 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
19620 output_asm_insn ("mov%?\t%0, %|lr", operands
);
19623 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
19625 if (TARGET_INTERWORK
|| arm_arch4t
)
19626 output_asm_insn ("bx%?\t%0", operands
);
19628 output_asm_insn ("mov%?\t%|pc, %0", operands
);
19633 /* Output a move from arm registers to arm registers of a long double
19634 OPERANDS[0] is the destination.
19635 OPERANDS[1] is the source. */
19637 output_mov_long_double_arm_from_arm (rtx
*operands
)
19639 /* We have to be careful here because the two might overlap. */
19640 int dest_start
= REGNO (operands
[0]);
19641 int src_start
= REGNO (operands
[1]);
19645 if (dest_start
< src_start
)
19647 for (i
= 0; i
< 3; i
++)
19649 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
19650 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
19651 output_asm_insn ("mov%?\t%0, %1", ops
);
19656 for (i
= 2; i
>= 0; i
--)
19658 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
19659 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
19660 output_asm_insn ("mov%?\t%0, %1", ops
);
19668 arm_emit_movpair (rtx dest
, rtx src
)
19670 /* If the src is an immediate, simplify it. */
19671 if (CONST_INT_P (src
))
19673 HOST_WIDE_INT val
= INTVAL (src
);
19674 emit_set_insn (dest
, GEN_INT (val
& 0x0000ffff));
19675 if ((val
>> 16) & 0x0000ffff)
19677 emit_set_insn (gen_rtx_ZERO_EXTRACT (SImode
, dest
, GEN_INT (16),
19679 GEN_INT ((val
>> 16) & 0x0000ffff));
19680 rtx_insn
*insn
= get_last_insn ();
19681 set_unique_reg_note (insn
, REG_EQUAL
, copy_rtx (src
));
19685 emit_set_insn (dest
, gen_rtx_HIGH (SImode
, src
));
19686 emit_set_insn (dest
, gen_rtx_LO_SUM (SImode
, dest
, src
));
19687 rtx_insn
*insn
= get_last_insn ();
19688 set_unique_reg_note (insn
, REG_EQUAL
, copy_rtx (src
));
19691 /* Output a move between double words. It must be REG<-MEM
19694 output_move_double (rtx
*operands
, bool emit
, int *count
)
19696 enum rtx_code code0
= GET_CODE (operands
[0]);
19697 enum rtx_code code1
= GET_CODE (operands
[1]);
19702 /* The only case when this might happen is when
19703 you are looking at the length of a DImode instruction
19704 that has an invalid constant in it. */
19705 if (code0
== REG
&& code1
!= MEM
)
19707 gcc_assert (!emit
);
19714 unsigned int reg0
= REGNO (operands
[0]);
19715 const bool can_ldrd
= TARGET_LDRD
&& (TARGET_THUMB2
|| (reg0
% 2 == 0));
19717 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
19719 gcc_assert (code1
== MEM
); /* Constraints should ensure this. */
19721 switch (GET_CODE (XEXP (operands
[1], 0)))
19728 && !(fix_cm3_ldrd
&& reg0
== REGNO(XEXP (operands
[1], 0))))
19729 output_asm_insn ("ldrd%?\t%0, [%m1]", operands
);
19731 output_asm_insn ("ldmia%?\t%m1, %M0", operands
);
19736 gcc_assert (can_ldrd
);
19738 output_asm_insn ("ldrd%?\t%0, [%m1, #8]!", operands
);
19745 output_asm_insn ("ldrd%?\t%0, [%m1, #-8]!", operands
);
19747 output_asm_insn ("ldmdb%?\t%m1!, %M0", operands
);
19755 output_asm_insn ("ldrd%?\t%0, [%m1], #8", operands
);
19757 output_asm_insn ("ldmia%?\t%m1!, %M0", operands
);
19762 gcc_assert (can_ldrd
);
19764 output_asm_insn ("ldrd%?\t%0, [%m1], #-8", operands
);
19769 /* Autoicrement addressing modes should never have overlapping
19770 base and destination registers, and overlapping index registers
19771 are already prohibited, so this doesn't need to worry about
19773 otherops
[0] = operands
[0];
19774 otherops
[1] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 0);
19775 otherops
[2] = XEXP (XEXP (XEXP (operands
[1], 0), 1), 1);
19777 if (GET_CODE (XEXP (operands
[1], 0)) == PRE_MODIFY
)
19779 if (reg_overlap_mentioned_p (otherops
[0], otherops
[2]))
19781 /* Registers overlap so split out the increment. */
19784 gcc_assert (can_ldrd
);
19785 output_asm_insn ("add%?\t%1, %1, %2", otherops
);
19786 output_asm_insn ("ldrd%?\t%0, [%1] @split", otherops
);
19793 /* Use a single insn if we can.
19794 FIXME: IWMMXT allows offsets larger than ldrd can
19795 handle, fix these up with a pair of ldr. */
19798 || !CONST_INT_P (otherops
[2])
19799 || (INTVAL (otherops
[2]) > -256
19800 && INTVAL (otherops
[2]) < 256)))
19803 output_asm_insn ("ldrd%?\t%0, [%1, %2]!", otherops
);
19809 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops
);
19810 output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops
);
19820 /* Use a single insn if we can.
19821 FIXME: IWMMXT allows offsets larger than ldrd can handle,
19822 fix these up with a pair of ldr. */
19825 || !CONST_INT_P (otherops
[2])
19826 || (INTVAL (otherops
[2]) > -256
19827 && INTVAL (otherops
[2]) < 256)))
19830 output_asm_insn ("ldrd%?\t%0, [%1], %2", otherops
);
19836 output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops
);
19837 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops
);
19847 /* We might be able to use ldrd %0, %1 here. However the range is
19848 different to ldr/adr, and it is broken on some ARMv7-M
19849 implementations. */
19850 /* Use the second register of the pair to avoid problematic
19852 otherops
[1] = operands
[1];
19854 output_asm_insn ("adr%?\t%0, %1", otherops
);
19855 operands
[1] = otherops
[0];
19859 output_asm_insn ("ldrd%?\t%0, [%1]", operands
);
19861 output_asm_insn ("ldmia%?\t%1, %M0", operands
);
19868 /* ??? This needs checking for thumb2. */
19870 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
19871 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
19873 otherops
[0] = operands
[0];
19874 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
19875 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
19877 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
19879 if (CONST_INT_P (otherops
[2]) && !TARGET_LDRD
)
19881 switch ((int) INTVAL (otherops
[2]))
19885 output_asm_insn ("ldmdb%?\t%1, %M0", otherops
);
19891 output_asm_insn ("ldmda%?\t%1, %M0", otherops
);
19897 output_asm_insn ("ldmib%?\t%1, %M0", otherops
);
19901 otherops
[0] = gen_rtx_REG(SImode
, REGNO(operands
[0]) + 1);
19902 operands
[1] = otherops
[0];
19904 && (REG_P (otherops
[2])
19906 || (CONST_INT_P (otherops
[2])
19907 && INTVAL (otherops
[2]) > -256
19908 && INTVAL (otherops
[2]) < 256)))
19910 if (reg_overlap_mentioned_p (operands
[0],
19913 /* Swap base and index registers over to
19914 avoid a conflict. */
19915 std::swap (otherops
[1], otherops
[2]);
19917 /* If both registers conflict, it will usually
19918 have been fixed by a splitter. */
19919 if (reg_overlap_mentioned_p (operands
[0], otherops
[2])
19920 || (fix_cm3_ldrd
&& reg0
== REGNO (otherops
[1])))
19924 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
19925 output_asm_insn ("ldrd%?\t%0, [%1]", operands
);
19932 otherops
[0] = operands
[0];
19934 output_asm_insn ("ldrd%?\t%0, [%1, %2]", otherops
);
19939 if (CONST_INT_P (otherops
[2]))
19943 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
19944 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
19946 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
19952 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
19958 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
19965 return "ldrd%?\t%0, [%1]";
19967 return "ldmia%?\t%1, %M0";
19971 otherops
[1] = adjust_address (operands
[1], SImode
, 4);
19972 /* Take care of overlapping base/data reg. */
19973 if (reg_mentioned_p (operands
[0], operands
[1]))
19977 output_asm_insn ("ldr%?\t%0, %1", otherops
);
19978 output_asm_insn ("ldr%?\t%0, %1", operands
);
19988 output_asm_insn ("ldr%?\t%0, %1", operands
);
19989 output_asm_insn ("ldr%?\t%0, %1", otherops
);
19999 /* Constraints should ensure this. */
20000 gcc_assert (code0
== MEM
&& code1
== REG
);
20001 gcc_assert ((REGNO (operands
[1]) != IP_REGNUM
)
20002 || (TARGET_ARM
&& TARGET_LDRD
));
20004 /* For TARGET_ARM the first source register of an STRD
20005 must be even. This is usually the case for double-word
20006 values but user assembly constraints can force an odd
20007 starting register. */
20008 bool allow_strd
= TARGET_LDRD
20009 && !(TARGET_ARM
&& (REGNO (operands
[1]) & 1) == 1);
20010 switch (GET_CODE (XEXP (operands
[0], 0)))
20016 output_asm_insn ("strd%?\t%1, [%m0]", operands
);
20018 output_asm_insn ("stm%?\t%m0, %M1", operands
);
20023 gcc_assert (allow_strd
);
20025 output_asm_insn ("strd%?\t%1, [%m0, #8]!", operands
);
20032 output_asm_insn ("strd%?\t%1, [%m0, #-8]!", operands
);
20034 output_asm_insn ("stmdb%?\t%m0!, %M1", operands
);
20042 output_asm_insn ("strd%?\t%1, [%m0], #8", operands
);
20044 output_asm_insn ("stm%?\t%m0!, %M1", operands
);
20049 gcc_assert (allow_strd
);
20051 output_asm_insn ("strd%?\t%1, [%m0], #-8", operands
);
20056 otherops
[0] = operands
[1];
20057 otherops
[1] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 0);
20058 otherops
[2] = XEXP (XEXP (XEXP (operands
[0], 0), 1), 1);
20060 /* IWMMXT allows offsets larger than strd can handle,
20061 fix these up with a pair of str. */
20063 && CONST_INT_P (otherops
[2])
20064 && (INTVAL(otherops
[2]) <= -256
20065 || INTVAL(otherops
[2]) >= 256))
20067 if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
20071 output_asm_insn ("str%?\t%0, [%1, %2]!", otherops
);
20072 output_asm_insn ("str%?\t%H0, [%1, #4]", otherops
);
20081 output_asm_insn ("str%?\t%H0, [%1, #4]", otherops
);
20082 output_asm_insn ("str%?\t%0, [%1], %2", otherops
);
20088 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
)
20091 output_asm_insn ("strd%?\t%0, [%1, %2]!", otherops
);
20096 output_asm_insn ("strd%?\t%0, [%1], %2", otherops
);
20101 otherops
[2] = XEXP (XEXP (operands
[0], 0), 1);
20102 if (CONST_INT_P (otherops
[2]) && !TARGET_LDRD
)
20104 switch ((int) INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
20108 output_asm_insn ("stmdb%?\t%m0, %M1", operands
);
20115 output_asm_insn ("stmda%?\t%m0, %M1", operands
);
20122 output_asm_insn ("stmib%?\t%m0, %M1", operands
);
20127 && (REG_P (otherops
[2])
20129 || (CONST_INT_P (otherops
[2])
20130 && INTVAL (otherops
[2]) > -256
20131 && INTVAL (otherops
[2]) < 256)))
20133 otherops
[0] = operands
[1];
20134 otherops
[1] = XEXP (XEXP (operands
[0], 0), 0);
20136 output_asm_insn ("strd%?\t%0, [%1, %2]", otherops
);
20142 otherops
[0] = adjust_address (operands
[0], SImode
, 4);
20143 otherops
[1] = operands
[1];
20146 output_asm_insn ("str%?\t%1, %0", operands
);
20147 output_asm_insn ("str%?\t%H1, %0", otherops
);
20157 /* Output a move, load or store for quad-word vectors in ARM registers. Only
20158 handles MEMs accepted by neon_vector_mem_operand with TYPE=1. */
20161 output_move_quad (rtx
*operands
)
20163 if (REG_P (operands
[0]))
20165 /* Load, or reg->reg move. */
20167 if (MEM_P (operands
[1]))
20169 switch (GET_CODE (XEXP (operands
[1], 0)))
20172 output_asm_insn ("ldmia%?\t%m1, %M0", operands
);
20177 output_asm_insn ("adr%?\t%0, %1", operands
);
20178 output_asm_insn ("ldmia%?\t%0, %M0", operands
);
20182 gcc_unreachable ();
20190 gcc_assert (REG_P (operands
[1]));
20192 dest
= REGNO (operands
[0]);
20193 src
= REGNO (operands
[1]);
20195 /* This seems pretty dumb, but hopefully GCC won't try to do it
20198 for (i
= 0; i
< 4; i
++)
20200 ops
[0] = gen_rtx_REG (SImode
, dest
+ i
);
20201 ops
[1] = gen_rtx_REG (SImode
, src
+ i
);
20202 output_asm_insn ("mov%?\t%0, %1", ops
);
20205 for (i
= 3; i
>= 0; i
--)
20207 ops
[0] = gen_rtx_REG (SImode
, dest
+ i
);
20208 ops
[1] = gen_rtx_REG (SImode
, src
+ i
);
20209 output_asm_insn ("mov%?\t%0, %1", ops
);
20215 gcc_assert (MEM_P (operands
[0]));
20216 gcc_assert (REG_P (operands
[1]));
20217 gcc_assert (!reg_overlap_mentioned_p (operands
[1], operands
[0]));
20219 switch (GET_CODE (XEXP (operands
[0], 0)))
20222 output_asm_insn ("stm%?\t%m0, %M1", operands
);
20226 gcc_unreachable ();
20233 /* Output a VFP load or store instruction. */
20236 output_move_vfp (rtx
*operands
)
20238 rtx reg
, mem
, addr
, ops
[2];
20239 int load
= REG_P (operands
[0]);
20240 int dp
= GET_MODE_SIZE (GET_MODE (operands
[0])) == 8;
20241 int sp
= (!TARGET_VFP_FP16INST
20242 || GET_MODE_SIZE (GET_MODE (operands
[0])) == 4);
20243 int integer_p
= GET_MODE_CLASS (GET_MODE (operands
[0])) == MODE_INT
;
20248 reg
= operands
[!load
];
20249 mem
= operands
[load
];
20251 mode
= GET_MODE (reg
);
20253 gcc_assert (REG_P (reg
));
20254 gcc_assert (IS_VFP_REGNUM (REGNO (reg
)));
20255 gcc_assert ((mode
== HFmode
&& TARGET_HARD_FLOAT
)
20261 || (TARGET_NEON
&& VALID_NEON_DREG_MODE (mode
)));
20262 gcc_assert (MEM_P (mem
));
20264 addr
= XEXP (mem
, 0);
20266 switch (GET_CODE (addr
))
20269 templ
= "v%smdb%%?.%s\t%%0!, {%%%s1}%s";
20270 ops
[0] = XEXP (addr
, 0);
20275 templ
= "v%smia%%?.%s\t%%0!, {%%%s1}%s";
20276 ops
[0] = XEXP (addr
, 0);
20281 templ
= "v%sr%%?.%s\t%%%s0, %%1%s";
20287 sprintf (buff
, templ
,
20288 load
? "ld" : "st",
20289 dp
? "64" : sp
? "32" : "16",
20291 integer_p
? "\t%@ int" : "");
20292 output_asm_insn (buff
, ops
);
20297 /* Output a Neon double-word or quad-word load or store, or a load
20298 or store for larger structure modes.
20300 WARNING: The ordering of elements is weird in big-endian mode,
20301 because the EABI requires that vectors stored in memory appear
20302 as though they were stored by a VSTM, as required by the EABI.
20303 GCC RTL defines element ordering based on in-memory order.
20304 This can be different from the architectural ordering of elements
20305 within a NEON register. The intrinsics defined in arm_neon.h use the
20306 NEON register element ordering, not the GCC RTL element ordering.
20308 For example, the in-memory ordering of a big-endian a quadword
20309 vector with 16-bit elements when stored from register pair {d0,d1}
20310 will be (lowest address first, d0[N] is NEON register element N):
20312 [d0[3], d0[2], d0[1], d0[0], d1[7], d1[6], d1[5], d1[4]]
20314 When necessary, quadword registers (dN, dN+1) are moved to ARM
20315 registers from rN in the order:
20317 dN -> (rN+1, rN), dN+1 -> (rN+3, rN+2)
20319 So that STM/LDM can be used on vectors in ARM registers, and the
20320 same memory layout will result as if VSTM/VLDM were used.
20322 Instead of VSTM/VLDM we prefer to use VST1.64/VLD1.64 where
20323 possible, which allows use of appropriate alignment tags.
20324 Note that the choice of "64" is independent of the actual vector
20325 element size; this size simply ensures that the behavior is
20326 equivalent to VSTM/VLDM in both little-endian and big-endian mode.
20328 Due to limitations of those instructions, use of VST1.64/VLD1.64
20329 is not possible if:
20330 - the address contains PRE_DEC, or
20331 - the mode refers to more than 4 double-word registers
20333 In those cases, it would be possible to replace VSTM/VLDM by a
20334 sequence of instructions; this is not currently implemented since
20335 this is not certain to actually improve performance. */
20338 output_move_neon (rtx
*operands
)
20340 rtx reg
, mem
, addr
, ops
[2];
20341 int regno
, nregs
, load
= REG_P (operands
[0]);
20346 reg
= operands
[!load
];
20347 mem
= operands
[load
];
20349 mode
= GET_MODE (reg
);
20351 gcc_assert (REG_P (reg
));
20352 regno
= REGNO (reg
);
20353 nregs
= REG_NREGS (reg
) / 2;
20354 gcc_assert (VFP_REGNO_OK_FOR_DOUBLE (regno
)
20355 || NEON_REGNO_OK_FOR_QUAD (regno
));
20356 gcc_assert (VALID_NEON_DREG_MODE (mode
)
20357 || VALID_NEON_QREG_MODE (mode
)
20358 || VALID_NEON_STRUCT_MODE (mode
));
20359 gcc_assert (MEM_P (mem
));
20361 addr
= XEXP (mem
, 0);
20363 /* Strip off const from addresses like (const (plus (...))). */
20364 if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
)
20365 addr
= XEXP (addr
, 0);
20367 switch (GET_CODE (addr
))
20370 /* We have to use vldm / vstm for too-large modes. */
20371 if (nregs
> 4 || (TARGET_HAVE_MVE
&& nregs
>= 2))
20373 templ
= "v%smia%%?\t%%0!, %%h1";
20374 ops
[0] = XEXP (addr
, 0);
20378 templ
= "v%s1.64\t%%h1, %%A0";
20385 /* We have to use vldm / vstm in this case, since there is no
20386 pre-decrement form of the vld1 / vst1 instructions. */
20387 templ
= "v%smdb%%?\t%%0!, %%h1";
20388 ops
[0] = XEXP (addr
, 0);
20393 /* FIXME: Not currently enabled in neon_vector_mem_operand. */
20394 gcc_unreachable ();
20397 /* We have to use vldm / vstm for too-large modes. */
20400 if (nregs
> 4 || (TARGET_HAVE_MVE
&& nregs
>= 2))
20401 templ
= "v%smia%%?\t%%m0, %%h1";
20403 templ
= "v%s1.64\t%%h1, %%A0";
20409 /* Fall through. */
20411 if (GET_CODE (addr
) == PLUS
)
20412 addr
= XEXP (addr
, 0);
20413 /* Fall through. */
20418 for (i
= 0; i
< nregs
; i
++)
20420 /* We're only using DImode here because it's a convenient
20422 ops
[0] = gen_rtx_REG (DImode
, REGNO (reg
) + 2 * i
);
20423 ops
[1] = adjust_address (mem
, DImode
, 8 * i
);
20424 if (reg_overlap_mentioned_p (ops
[0], mem
))
20426 gcc_assert (overlap
== -1);
20431 if (TARGET_HAVE_MVE
&& LABEL_REF_P (addr
))
20432 sprintf (buff
, "v%sr.64\t%%P0, %%1", load
? "ld" : "st");
20434 sprintf (buff
, "v%sr%%?\t%%P0, %%1", load
? "ld" : "st");
20435 output_asm_insn (buff
, ops
);
20440 ops
[0] = gen_rtx_REG (DImode
, REGNO (reg
) + 2 * overlap
);
20441 ops
[1] = adjust_address (mem
, SImode
, 8 * overlap
);
20442 if (TARGET_HAVE_MVE
&& LABEL_REF_P (addr
))
20443 sprintf (buff
, "v%sr.32\t%%P0, %%1", load
? "ld" : "st");
20445 sprintf (buff
, "v%sr%%?\t%%P0, %%1", load
? "ld" : "st");
20446 output_asm_insn (buff
, ops
);
20453 gcc_unreachable ();
20456 sprintf (buff
, templ
, load
? "ld" : "st");
20457 output_asm_insn (buff
, ops
);
20462 /* Compute and return the length of neon_mov<mode>, where <mode> is
20463 one of VSTRUCT modes: EI, OI, CI or XI. */
20465 arm_attr_length_move_neon (rtx_insn
*insn
)
20467 rtx reg
, mem
, addr
;
20471 extract_insn_cached (insn
);
20473 if (REG_P (recog_data
.operand
[0]) && REG_P (recog_data
.operand
[1]))
20475 mode
= GET_MODE (recog_data
.operand
[0]);
20486 gcc_unreachable ();
20490 load
= REG_P (recog_data
.operand
[0]);
20491 reg
= recog_data
.operand
[!load
];
20492 mem
= recog_data
.operand
[load
];
20494 gcc_assert (MEM_P (mem
));
20496 addr
= XEXP (mem
, 0);
20498 /* Strip off const from addresses like (const (plus (...))). */
20499 if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
)
20500 addr
= XEXP (addr
, 0);
20502 if (LABEL_REF_P (addr
) || GET_CODE (addr
) == PLUS
)
20504 int insns
= REG_NREGS (reg
) / 2;
20511 /* Return nonzero if the offset in the address is an immediate. Otherwise,
20515 arm_address_offset_is_imm (rtx_insn
*insn
)
20519 extract_insn_cached (insn
);
20521 if (REG_P (recog_data
.operand
[0]))
20524 mem
= recog_data
.operand
[0];
20526 gcc_assert (MEM_P (mem
));
20528 addr
= XEXP (mem
, 0);
20531 || (GET_CODE (addr
) == PLUS
20532 && REG_P (XEXP (addr
, 0))
20533 && CONST_INT_P (XEXP (addr
, 1))))
20539 /* Output an ADD r, s, #n where n may be too big for one instruction.
20540 If adding zero to one register, output nothing. */
20542 output_add_immediate (rtx
*operands
)
20544 HOST_WIDE_INT n
= INTVAL (operands
[2]);
20546 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
20549 output_multi_immediate (operands
,
20550 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
20553 output_multi_immediate (operands
,
20554 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
20561 /* Output a multiple immediate operation.
20562 OPERANDS is the vector of operands referred to in the output patterns.
20563 INSTR1 is the output pattern to use for the first constant.
20564 INSTR2 is the output pattern to use for subsequent constants.
20565 IMMED_OP is the index of the constant slot in OPERANDS.
20566 N is the constant value. */
20567 static const char *
20568 output_multi_immediate (rtx
*operands
, const char *instr1
, const char *instr2
,
20569 int immed_op
, HOST_WIDE_INT n
)
20571 #if HOST_BITS_PER_WIDE_INT > 32
20577 /* Quick and easy output. */
20578 operands
[immed_op
] = const0_rtx
;
20579 output_asm_insn (instr1
, operands
);
20584 const char * instr
= instr1
;
20586 /* Note that n is never zero here (which would give no output). */
20587 for (i
= 0; i
< 32; i
+= 2)
20591 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
20592 output_asm_insn (instr
, operands
);
20602 /* Return the name of a shifter operation. */
20603 static const char *
20604 arm_shift_nmem(enum rtx_code code
)
20609 return ARM_LSL_NAME
;
20625 /* Return the appropriate ARM instruction for the operation code.
20626 The returned result should not be overwritten. OP is the rtx of the
20627 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
20630 arithmetic_instr (rtx op
, int shift_first_arg
)
20632 switch (GET_CODE (op
))
20638 return shift_first_arg
? "rsb" : "sub";
20653 return arm_shift_nmem(GET_CODE(op
));
20656 gcc_unreachable ();
20660 /* Ensure valid constant shifts and return the appropriate shift mnemonic
20661 for the operation code. The returned result should not be overwritten.
20662 OP is the rtx code of the shift.
20663 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
20665 static const char *
20666 shift_op (rtx op
, HOST_WIDE_INT
*amountp
)
20669 enum rtx_code code
= GET_CODE (op
);
20674 if (!CONST_INT_P (XEXP (op
, 1)))
20676 output_operand_lossage ("invalid shift operand");
20681 *amountp
= 32 - INTVAL (XEXP (op
, 1));
20689 mnem
= arm_shift_nmem(code
);
20690 if (CONST_INT_P (XEXP (op
, 1)))
20692 *amountp
= INTVAL (XEXP (op
, 1));
20694 else if (REG_P (XEXP (op
, 1)))
20701 output_operand_lossage ("invalid shift operand");
20707 /* We never have to worry about the amount being other than a
20708 power of 2, since this case can never be reloaded from a reg. */
20709 if (!CONST_INT_P (XEXP (op
, 1)))
20711 output_operand_lossage ("invalid shift operand");
20715 *amountp
= INTVAL (XEXP (op
, 1)) & 0xFFFFFFFF;
20717 /* Amount must be a power of two. */
20718 if (*amountp
& (*amountp
- 1))
20720 output_operand_lossage ("invalid shift operand");
20724 *amountp
= exact_log2 (*amountp
);
20725 gcc_assert (IN_RANGE (*amountp
, 0, 31));
20726 return ARM_LSL_NAME
;
20729 output_operand_lossage ("invalid shift operand");
20733 /* This is not 100% correct, but follows from the desire to merge
20734 multiplication by a power of 2 with the recognizer for a
20735 shift. >=32 is not a valid shift for "lsl", so we must try and
20736 output a shift that produces the correct arithmetical result.
20737 Using lsr #32 is identical except for the fact that the carry bit
20738 is not set correctly if we set the flags; but we never use the
20739 carry bit from such an operation, so we can ignore that. */
20740 if (code
== ROTATERT
)
20741 /* Rotate is just modulo 32. */
20743 else if (*amountp
!= (*amountp
& 31))
20745 if (code
== ASHIFT
)
20750 /* Shifts of 0 are no-ops. */
20757 /* Output a .ascii pseudo-op, keeping track of lengths. This is
20758 because /bin/as is horribly restrictive. The judgement about
20759 whether or not each character is 'printable' (and can be output as
20760 is) or not (and must be printed with an octal escape) must be made
20761 with reference to the *host* character set -- the situation is
20762 similar to that discussed in the comments above pp_c_char in
20763 c-pretty-print.c. */
20765 #define MAX_ASCII_LEN 51
20768 output_ascii_pseudo_op (FILE *stream
, const unsigned char *p
, int len
)
20771 int len_so_far
= 0;
20773 fputs ("\t.ascii\t\"", stream
);
20775 for (i
= 0; i
< len
; i
++)
20779 if (len_so_far
>= MAX_ASCII_LEN
)
20781 fputs ("\"\n\t.ascii\t\"", stream
);
20787 if (c
== '\\' || c
== '\"')
20789 putc ('\\', stream
);
20797 fprintf (stream
, "\\%03o", c
);
20802 fputs ("\"\n", stream
);
20806 /* Compute the register save mask for registers 0 through 12
20807 inclusive. This code is used by arm_compute_save_core_reg_mask (). */
20809 static unsigned long
20810 arm_compute_save_reg0_reg12_mask (void)
20812 unsigned long func_type
= arm_current_func_type ();
20813 unsigned long save_reg_mask
= 0;
20816 if (IS_INTERRUPT (func_type
))
20818 unsigned int max_reg
;
20819 /* Interrupt functions must not corrupt any registers,
20820 even call clobbered ones. If this is a leaf function
20821 we can just examine the registers used by the RTL, but
20822 otherwise we have to assume that whatever function is
20823 called might clobber anything, and so we have to save
20824 all the call-clobbered registers as well. */
20825 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
20826 /* FIQ handlers have registers r8 - r12 banked, so
20827 we only need to check r0 - r7, Normal ISRs only
20828 bank r14 and r15, so we must check up to r12.
20829 r13 is the stack pointer which is always preserved,
20830 so we do not need to consider it here. */
20835 for (reg
= 0; reg
<= max_reg
; reg
++)
20836 if (reg_needs_saving_p (reg
))
20837 save_reg_mask
|= (1 << reg
);
20839 /* Also save the pic base register if necessary. */
20840 if (PIC_REGISTER_MAY_NEED_SAVING
20841 && crtl
->uses_pic_offset_table
)
20842 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
20844 else if (IS_VOLATILE(func_type
))
20846 /* For noreturn functions we historically omitted register saves
20847 altogether. However this really messes up debugging. As a
20848 compromise save just the frame pointers. Combined with the link
20849 register saved elsewhere this should be sufficient to get
20851 if (frame_pointer_needed
)
20852 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
20853 if (df_regs_ever_live_p (ARM_HARD_FRAME_POINTER_REGNUM
))
20854 save_reg_mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
20855 if (df_regs_ever_live_p (THUMB_HARD_FRAME_POINTER_REGNUM
))
20856 save_reg_mask
|= 1 << THUMB_HARD_FRAME_POINTER_REGNUM
;
20860 /* In the normal case we only need to save those registers
20861 which are call saved and which are used by this function. */
20862 for (reg
= 0; reg
<= 11; reg
++)
20863 if (df_regs_ever_live_p (reg
) && callee_saved_reg_p (reg
))
20864 save_reg_mask
|= (1 << reg
);
20866 /* Handle the frame pointer as a special case. */
20867 if (frame_pointer_needed
)
20868 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
20870 /* If we aren't loading the PIC register,
20871 don't stack it even though it may be live. */
20872 if (PIC_REGISTER_MAY_NEED_SAVING
20873 && (df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
)
20874 || crtl
->uses_pic_offset_table
))
20875 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
20877 /* The prologue will copy SP into R0, so save it. */
20878 if (IS_STACKALIGN (func_type
))
20879 save_reg_mask
|= 1;
20882 /* Save registers so the exception handler can modify them. */
20883 if (crtl
->calls_eh_return
)
20889 reg
= EH_RETURN_DATA_REGNO (i
);
20890 if (reg
== INVALID_REGNUM
)
20892 save_reg_mask
|= 1 << reg
;
20896 return save_reg_mask
;
20899 /* Return true if r3 is live at the start of the function. */
20902 arm_r3_live_at_start_p (void)
20904 /* Just look at cfg info, which is still close enough to correct at this
20905 point. This gives false positives for broken functions that might use
20906 uninitialized data that happens to be allocated in r3, but who cares? */
20907 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR_FOR_FN (cfun
)), 3);
20910 /* Compute the number of bytes used to store the static chain register on the
20911 stack, above the stack frame. We need to know this accurately to get the
20912 alignment of the rest of the stack frame correct. */
20915 arm_compute_static_chain_stack_bytes (void)
20917 /* Once the value is updated from the init value of -1, do not
20919 if (cfun
->machine
->static_chain_stack_bytes
!= -1)
20920 return cfun
->machine
->static_chain_stack_bytes
;
20922 /* See the defining assertion in arm_expand_prologue. */
20923 if (IS_NESTED (arm_current_func_type ())
20924 && ((TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
)
20925 || ((flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
20926 || flag_stack_clash_protection
)
20927 && !df_regs_ever_live_p (LR_REGNUM
)))
20928 && arm_r3_live_at_start_p ()
20929 && crtl
->args
.pretend_args_size
== 0)
20935 /* Compute a bit mask of which core registers need to be
20936 saved on the stack for the current function.
20937 This is used by arm_compute_frame_layout, which may add extra registers. */
20939 static unsigned long
20940 arm_compute_save_core_reg_mask (void)
20942 unsigned int save_reg_mask
= 0;
20943 unsigned long func_type
= arm_current_func_type ();
20946 if (IS_NAKED (func_type
))
20947 /* This should never really happen. */
20950 /* If we are creating a stack frame, then we must save the frame pointer,
20951 IP (which will hold the old stack pointer), LR and the PC. */
20952 if (TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
)
20954 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
20957 | (1 << PC_REGNUM
);
20959 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
20961 /* Decide if we need to save the link register.
20962 Interrupt routines have their own banked link register,
20963 so they never need to save it.
20964 Otherwise if we do not use the link register we do not need to save
20965 it. If we are pushing other registers onto the stack however, we
20966 can save an instruction in the epilogue by pushing the link register
20967 now and then popping it back into the PC. This incurs extra memory
20968 accesses though, so we only do it when optimizing for size, and only
20969 if we know that we will not need a fancy return sequence. */
20970 if (df_regs_ever_live_p (LR_REGNUM
)
20973 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
20974 && !crtl
->tail_call_emit
20975 && !crtl
->calls_eh_return
))
20976 save_reg_mask
|= 1 << LR_REGNUM
;
20978 if (cfun
->machine
->lr_save_eliminated
)
20979 save_reg_mask
&= ~ (1 << LR_REGNUM
);
20981 if (TARGET_REALLY_IWMMXT
20982 && ((bit_count (save_reg_mask
)
20983 + ARM_NUM_INTS (crtl
->args
.pretend_args_size
+
20984 arm_compute_static_chain_stack_bytes())
20987 /* The total number of registers that are going to be pushed
20988 onto the stack is odd. We need to ensure that the stack
20989 is 64-bit aligned before we start to save iWMMXt registers,
20990 and also before we start to create locals. (A local variable
20991 might be a double or long long which we will load/store using
20992 an iWMMXt instruction). Therefore we need to push another
20993 ARM register, so that the stack will be 64-bit aligned. We
20994 try to avoid using the arg registers (r0 -r3) as they might be
20995 used to pass values in a tail call. */
20996 for (reg
= 4; reg
<= 12; reg
++)
20997 if ((save_reg_mask
& (1 << reg
)) == 0)
21001 save_reg_mask
|= (1 << reg
);
21004 cfun
->machine
->sibcall_blocked
= 1;
21005 save_reg_mask
|= (1 << 3);
21009 /* We may need to push an additional register for use initializing the
21010 PIC base register. */
21011 if (TARGET_THUMB2
&& IS_NESTED (func_type
) && flag_pic
21012 && (save_reg_mask
& THUMB2_WORK_REGS
) == 0)
21014 reg
= thumb_find_work_register (1 << 4);
21015 if (!call_used_or_fixed_reg_p (reg
))
21016 save_reg_mask
|= (1 << reg
);
21019 return save_reg_mask
;
21022 /* Compute a bit mask of which core registers need to be
21023 saved on the stack for the current function. */
21024 static unsigned long
21025 thumb1_compute_save_core_reg_mask (void)
21027 unsigned long mask
;
21031 for (reg
= 0; reg
< 12; reg
++)
21032 if (df_regs_ever_live_p (reg
) && callee_saved_reg_p (reg
))
21035 /* Handle the frame pointer as a special case. */
21036 if (frame_pointer_needed
)
21037 mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
21040 && !TARGET_SINGLE_PIC_BASE
21041 && arm_pic_register
!= INVALID_REGNUM
21042 && crtl
->uses_pic_offset_table
)
21043 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
21045 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
21046 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
21047 mask
|= 1 << ARM_HARD_FRAME_POINTER_REGNUM
;
21049 /* LR will also be pushed if any lo regs are pushed. */
21050 if (mask
& 0xff || thumb_force_lr_save ())
21051 mask
|= (1 << LR_REGNUM
);
21053 bool call_clobbered_scratch
21054 = (thumb1_prologue_unused_call_clobbered_lo_regs ()
21055 && thumb1_epilogue_unused_call_clobbered_lo_regs ());
21057 /* Make sure we have a low work register if we need one. We will
21058 need one if we are going to push a high register, but we are not
21059 currently intending to push a low register. However if both the
21060 prologue and epilogue have a spare call-clobbered low register,
21061 then we won't need to find an additional work register. It does
21062 not need to be the same register in the prologue and
21064 if ((mask
& 0xff) == 0
21065 && !call_clobbered_scratch
21066 && ((mask
& 0x0f00) || TARGET_BACKTRACE
))
21068 /* Use thumb_find_work_register to choose which register
21069 we will use. If the register is live then we will
21070 have to push it. Use LAST_LO_REGNUM as our fallback
21071 choice for the register to select. */
21072 reg
= thumb_find_work_register (1 << LAST_LO_REGNUM
);
21073 /* Make sure the register returned by thumb_find_work_register is
21074 not part of the return value. */
21075 if (reg
* UNITS_PER_WORD
<= (unsigned) arm_size_return_regs ())
21076 reg
= LAST_LO_REGNUM
;
21078 if (callee_saved_reg_p (reg
))
21082 /* The 504 below is 8 bytes less than 512 because there are two possible
21083 alignment words. We can't tell here if they will be present or not so we
21084 have to play it safe and assume that they are. */
21085 if ((CALLER_INTERWORKING_SLOT_SIZE
+
21086 ROUND_UP_WORD (get_frame_size ()) +
21087 crtl
->outgoing_args_size
) >= 504)
21089 /* This is the same as the code in thumb1_expand_prologue() which
21090 determines which register to use for stack decrement. */
21091 for (reg
= LAST_ARG_REGNUM
+ 1; reg
<= LAST_LO_REGNUM
; reg
++)
21092 if (mask
& (1 << reg
))
21095 if (reg
> LAST_LO_REGNUM
)
21097 /* Make sure we have a register available for stack decrement. */
21098 mask
|= 1 << LAST_LO_REGNUM
;
21105 /* Return the number of bytes required to save VFP registers. */
21107 arm_get_vfp_saved_size (void)
21109 unsigned int regno
;
21114 /* Space for saved VFP registers. */
21115 if (TARGET_VFP_BASE
)
21118 for (regno
= FIRST_VFP_REGNUM
;
21119 regno
< LAST_VFP_REGNUM
;
21122 if (!reg_needs_saving_p (regno
) && !reg_needs_saving_p (regno
+ 1))
21126 /* Workaround ARM10 VFPr1 bug. */
21127 if (count
== 2 && !arm_arch6
)
21129 saved
+= count
* 8;
21138 if (count
== 2 && !arm_arch6
)
21140 saved
+= count
* 8;
21147 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
21148 everything bar the final return instruction. If simple_return is true,
21149 then do not output epilogue, because it has already been emitted in RTL.
21151 Note: do not forget to update length attribute of corresponding insn pattern
21152 when changing assembly output (eg. length attribute of
21153 thumb2_cmse_entry_return when updating Armv8-M Mainline Security Extensions
21154 register clearing sequences). */
21156 output_return_instruction (rtx operand
, bool really_return
, bool reverse
,
21157 bool simple_return
)
21159 char conditional
[10];
21162 unsigned long live_regs_mask
;
21163 unsigned long func_type
;
21164 arm_stack_offsets
*offsets
;
21166 func_type
= arm_current_func_type ();
21168 if (IS_NAKED (func_type
))
21171 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
21173 /* If this function was declared non-returning, and we have
21174 found a tail call, then we have to trust that the called
21175 function won't return. */
21180 /* Otherwise, trap an attempted return by aborting. */
21182 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
21184 assemble_external_libcall (ops
[1]);
21185 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
21191 gcc_assert (!cfun
->calls_alloca
|| really_return
);
21193 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
21195 cfun
->machine
->return_used_this_function
= 1;
21197 offsets
= arm_get_frame_offsets ();
21198 live_regs_mask
= offsets
->saved_regs_mask
;
21200 if (!simple_return
&& live_regs_mask
)
21202 const char * return_reg
;
21204 /* If we do not have any special requirements for function exit
21205 (e.g. interworking) then we can load the return address
21206 directly into the PC. Otherwise we must load it into LR. */
21208 && !IS_CMSE_ENTRY (func_type
)
21209 && (IS_INTERRUPT (func_type
) || !TARGET_INTERWORK
))
21210 return_reg
= reg_names
[PC_REGNUM
];
21212 return_reg
= reg_names
[LR_REGNUM
];
21214 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
21216 /* There are three possible reasons for the IP register
21217 being saved. 1) a stack frame was created, in which case
21218 IP contains the old stack pointer, or 2) an ISR routine
21219 corrupted it, or 3) it was saved to align the stack on
21220 iWMMXt. In case 1, restore IP into SP, otherwise just
21222 if (frame_pointer_needed
)
21224 live_regs_mask
&= ~ (1 << IP_REGNUM
);
21225 live_regs_mask
|= (1 << SP_REGNUM
);
21228 gcc_assert (IS_INTERRUPT (func_type
) || TARGET_REALLY_IWMMXT
);
21231 /* On some ARM architectures it is faster to use LDR rather than
21232 LDM to load a single register. On other architectures, the
21233 cost is the same. In 26 bit mode, or for exception handlers,
21234 we have to use LDM to load the PC so that the CPSR is also
21236 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
21237 if (live_regs_mask
== (1U << reg
))
21240 if (reg
<= LAST_ARM_REGNUM
21241 && (reg
!= LR_REGNUM
21243 || ! IS_INTERRUPT (func_type
)))
21245 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
21246 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
21253 /* Generate the load multiple instruction to restore the
21254 registers. Note we can get here, even if
21255 frame_pointer_needed is true, but only if sp already
21256 points to the base of the saved core registers. */
21257 if (live_regs_mask
& (1 << SP_REGNUM
))
21259 unsigned HOST_WIDE_INT stack_adjust
;
21261 stack_adjust
= offsets
->outgoing_args
- offsets
->saved_regs
;
21262 gcc_assert (stack_adjust
== 0 || stack_adjust
== 4);
21264 if (stack_adjust
&& arm_arch5t
&& TARGET_ARM
)
21265 sprintf (instr
, "ldmib%s\t%%|sp, {", conditional
);
21268 /* If we can't use ldmib (SA110 bug),
21269 then try to pop r3 instead. */
21271 live_regs_mask
|= 1 << 3;
21273 sprintf (instr
, "ldmfd%s\t%%|sp, {", conditional
);
21276 /* For interrupt returns we have to use an LDM rather than
21277 a POP so that we can use the exception return variant. */
21278 else if (IS_INTERRUPT (func_type
))
21279 sprintf (instr
, "ldmfd%s\t%%|sp!, {", conditional
);
21281 sprintf (instr
, "pop%s\t{", conditional
);
21283 p
= instr
+ strlen (instr
);
21285 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
21286 if (live_regs_mask
& (1 << reg
))
21288 int l
= strlen (reg_names
[reg
]);
21294 memcpy (p
, ", ", 2);
21298 memcpy (p
, "%|", 2);
21299 memcpy (p
+ 2, reg_names
[reg
], l
);
21303 if (live_regs_mask
& (1 << LR_REGNUM
))
21305 sprintf (p
, "%s%%|%s}", first
? "" : ", ", return_reg
);
21306 /* If returning from an interrupt, restore the CPSR. */
21307 if (IS_INTERRUPT (func_type
))
21314 output_asm_insn (instr
, & operand
);
21316 /* See if we need to generate an extra instruction to
21317 perform the actual function return. */
21319 && func_type
!= ARM_FT_INTERWORKED
21320 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
21322 /* The return has already been handled
21323 by loading the LR into the PC. */
21330 switch ((int) ARM_FUNC_TYPE (func_type
))
21334 /* ??? This is wrong for unified assembly syntax. */
21335 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
21338 case ARM_FT_INTERWORKED
:
21339 gcc_assert (arm_arch5t
|| arm_arch4t
);
21340 sprintf (instr
, "bx%s\t%%|lr", conditional
);
21343 case ARM_FT_EXCEPTION
:
21344 /* ??? This is wrong for unified assembly syntax. */
21345 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
21349 if (IS_CMSE_ENTRY (func_type
))
21351 /* For Armv8.1-M, this is cleared as part of the CLRM instruction
21352 emitted by cmse_nonsecure_entry_clear_before_return () and the
21353 VSTR/VLDR instructions in the prologue and epilogue. */
21354 if (!TARGET_HAVE_FPCXT_CMSE
)
21356 /* Check if we have to clear the 'GE bits' which is only used if
21357 parallel add and subtraction instructions are available. */
21358 if (TARGET_INT_SIMD
)
21359 snprintf (instr
, sizeof (instr
),
21360 "msr%s\tAPSR_nzcvqg, %%|lr", conditional
);
21362 snprintf (instr
, sizeof (instr
),
21363 "msr%s\tAPSR_nzcvq, %%|lr", conditional
);
21365 output_asm_insn (instr
, & operand
);
21366 /* Do not clear FPSCR if targeting Armv8.1-M Mainline, VLDR takes
21368 if (TARGET_HARD_FLOAT
)
21370 /* Clear the cumulative exception-status bits (0-4,7) and
21371 the condition code bits (28-31) of the FPSCR. We need
21372 to remember to clear the first scratch register used
21373 (IP) and save and restore the second (r4).
21375 Important note: the length of the
21376 thumb2_cmse_entry_return insn pattern must account for
21377 the size of the below instructions. */
21378 output_asm_insn ("push\t{%|r4}", & operand
);
21379 output_asm_insn ("vmrs\t%|ip, fpscr", & operand
);
21380 output_asm_insn ("movw\t%|r4, #65376", & operand
);
21381 output_asm_insn ("movt\t%|r4, #4095", & operand
);
21382 output_asm_insn ("and\t%|ip, %|r4", & operand
);
21383 output_asm_insn ("vmsr\tfpscr, %|ip", & operand
);
21384 output_asm_insn ("pop\t{%|r4}", & operand
);
21385 output_asm_insn ("mov\t%|ip, %|lr", & operand
);
21388 snprintf (instr
, sizeof (instr
), "bxns\t%%|lr");
21390 /* Use bx if it's available. */
21391 else if (arm_arch5t
|| arm_arch4t
)
21392 sprintf (instr
, "bx%s\t%%|lr", conditional
);
21394 sprintf (instr
, "mov%s\t%%|pc, %%|lr", conditional
);
21398 output_asm_insn (instr
, & operand
);
21404 /* Output in FILE asm statements needed to declare the NAME of the function
21405 defined by its DECL node. */
21408 arm_asm_declare_function_name (FILE *file
, const char *name
, tree decl
)
21410 size_t cmse_name_len
;
21411 char *cmse_name
= 0;
21412 char cmse_prefix
[] = "__acle_se_";
21414 /* When compiling with ARMv8-M Security Extensions enabled, we should print an
21415 extra function label for each function with the 'cmse_nonsecure_entry'
21416 attribute. This extra function label should be prepended with
21417 '__acle_se_', telling the linker that it needs to create secure gateway
21418 veneers for this function. */
21419 if (use_cmse
&& lookup_attribute ("cmse_nonsecure_entry",
21420 DECL_ATTRIBUTES (decl
)))
21422 cmse_name_len
= sizeof (cmse_prefix
) + strlen (name
);
21423 cmse_name
= XALLOCAVEC (char, cmse_name_len
);
21424 snprintf (cmse_name
, cmse_name_len
, "%s%s", cmse_prefix
, name
);
21425 targetm
.asm_out
.globalize_label (file
, cmse_name
);
21427 ARM_DECLARE_FUNCTION_NAME (file
, cmse_name
, decl
);
21428 ASM_OUTPUT_TYPE_DIRECTIVE (file
, cmse_name
, "function");
21431 ARM_DECLARE_FUNCTION_NAME (file
, name
, decl
);
21432 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
21433 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
21434 ASM_OUTPUT_LABEL (file
, name
);
21437 ASM_OUTPUT_LABEL (file
, cmse_name
);
21439 ARM_OUTPUT_FN_UNWIND (file
, TRUE
);
21442 /* Write the function name into the code section, directly preceding
21443 the function prologue.
21445 Code will be output similar to this:
21447 .ascii "arm_poke_function_name", 0
21450 .word 0xff000000 + (t1 - t0)
21451 arm_poke_function_name
21453 stmfd sp!, {fp, ip, lr, pc}
21456 When performing a stack backtrace, code can inspect the value
21457 of 'pc' stored at 'fp' + 0. If the trace function then looks
21458 at location pc - 12 and the top 8 bits are set, then we know
21459 that there is a function name embedded immediately preceding this
21460 location and has length ((pc[-3]) & 0xff000000).
21462 We assume that pc is declared as a pointer to an unsigned long.
21464 It is of no benefit to output the function name if we are assembling
21465 a leaf function. These function types will not contain a stack
21466 backtrace structure, therefore it is not possible to determine the
21469 arm_poke_function_name (FILE *stream
, const char *name
)
21471 unsigned long alignlength
;
21472 unsigned long length
;
21475 length
= strlen (name
) + 1;
21476 alignlength
= ROUND_UP_WORD (length
);
21478 ASM_OUTPUT_ASCII (stream
, name
, length
);
21479 ASM_OUTPUT_ALIGN (stream
, 2);
21480 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
21481 assemble_aligned_integer (UNITS_PER_WORD
, x
);
21484 /* Place some comments into the assembler stream
21485 describing the current function. */
21487 arm_output_function_prologue (FILE *f
)
21489 unsigned long func_type
;
21491 /* Sanity check. */
21492 gcc_assert (!arm_ccfsm_state
&& !arm_target_insn
);
21494 func_type
= arm_current_func_type ();
21496 switch ((int) ARM_FUNC_TYPE (func_type
))
21499 case ARM_FT_NORMAL
:
21501 case ARM_FT_INTERWORKED
:
21502 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
21505 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
21508 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
21510 case ARM_FT_EXCEPTION
:
21511 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
21515 if (IS_NAKED (func_type
))
21516 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
21518 if (IS_VOLATILE (func_type
))
21519 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
21521 if (IS_NESTED (func_type
))
21522 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
21523 if (IS_STACKALIGN (func_type
))
21524 asm_fprintf (f
, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
21525 if (IS_CMSE_ENTRY (func_type
))
21526 asm_fprintf (f
, "\t%@ Non-secure entry function: called from non-secure code.\n");
21528 asm_fprintf (f
, "\t%@ args = %wd, pretend = %d, frame = %wd\n",
21529 (HOST_WIDE_INT
) crtl
->args
.size
,
21530 crtl
->args
.pretend_args_size
,
21531 (HOST_WIDE_INT
) get_frame_size ());
21533 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
21534 frame_pointer_needed
,
21535 cfun
->machine
->uses_anonymous_args
);
21537 if (cfun
->machine
->lr_save_eliminated
)
21538 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
21540 if (crtl
->calls_eh_return
)
21541 asm_fprintf (f
, "\t@ Calls __builtin_eh_return.\n");
21546 arm_output_function_epilogue (FILE *)
21548 arm_stack_offsets
*offsets
;
21554 /* Emit any call-via-reg trampolines that are needed for v4t support
21555 of call_reg and call_value_reg type insns. */
21556 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
21558 rtx label
= cfun
->machine
->call_via
[regno
];
21562 switch_to_section (function_section (current_function_decl
));
21563 targetm
.asm_out
.internal_label (asm_out_file
, "L",
21564 CODE_LABEL_NUMBER (label
));
21565 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
21569 /* ??? Probably not safe to set this here, since it assumes that a
21570 function will be emitted as assembly immediately after we generate
21571 RTL for it. This does not happen for inline functions. */
21572 cfun
->machine
->return_used_this_function
= 0;
21574 else /* TARGET_32BIT */
21576 /* We need to take into account any stack-frame rounding. */
21577 offsets
= arm_get_frame_offsets ();
21579 gcc_assert (!use_return_insn (FALSE
, NULL
)
21580 || (cfun
->machine
->return_used_this_function
!= 0)
21581 || offsets
->saved_regs
== offsets
->outgoing_args
21582 || frame_pointer_needed
);
21586 /* Generate and emit a sequence of insns equivalent to PUSH, but using
21587 STR and STRD. If an even number of registers are being pushed, one
21588 or more STRD patterns are created for each register pair. If an
21589 odd number of registers are pushed, emit an initial STR followed by
21590 as many STRD instructions as are needed. This works best when the
21591 stack is initially 64-bit aligned (the normal case), since it
21592 ensures that each STRD is also 64-bit aligned. */
21594 thumb2_emit_strd_push (unsigned long saved_regs_mask
)
21599 rtx par
= NULL_RTX
;
21600 rtx dwarf
= NULL_RTX
;
21604 num_regs
= bit_count (saved_regs_mask
);
21606 /* Must be at least one register to save, and can't save SP or PC. */
21607 gcc_assert (num_regs
> 0 && num_regs
<= 14);
21608 gcc_assert (!(saved_regs_mask
& (1 << SP_REGNUM
)));
21609 gcc_assert (!(saved_regs_mask
& (1 << PC_REGNUM
)));
21611 /* Create sequence for DWARF info. All the frame-related data for
21612 debugging is held in this wrapper. */
21613 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_regs
+ 1));
21615 /* Describe the stack adjustment. */
21616 tmp
= gen_rtx_SET (stack_pointer_rtx
,
21617 plus_constant (Pmode
, stack_pointer_rtx
, -4 * num_regs
));
21618 RTX_FRAME_RELATED_P (tmp
) = 1;
21619 XVECEXP (dwarf
, 0, 0) = tmp
;
21621 /* Find the first register. */
21622 for (regno
= 0; (saved_regs_mask
& (1 << regno
)) == 0; regno
++)
21627 /* If there's an odd number of registers to push. Start off by
21628 pushing a single register. This ensures that subsequent strd
21629 operations are dword aligned (assuming that SP was originally
21630 64-bit aligned). */
21631 if ((num_regs
& 1) != 0)
21633 rtx reg
, mem
, insn
;
21635 reg
= gen_rtx_REG (SImode
, regno
);
21637 mem
= gen_frame_mem (Pmode
, gen_rtx_PRE_DEC (Pmode
,
21638 stack_pointer_rtx
));
21640 mem
= gen_frame_mem (Pmode
,
21642 (Pmode
, stack_pointer_rtx
,
21643 plus_constant (Pmode
, stack_pointer_rtx
,
21646 tmp
= gen_rtx_SET (mem
, reg
);
21647 RTX_FRAME_RELATED_P (tmp
) = 1;
21648 insn
= emit_insn (tmp
);
21649 RTX_FRAME_RELATED_P (insn
) = 1;
21650 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
21651 tmp
= gen_rtx_SET (gen_frame_mem (Pmode
, stack_pointer_rtx
), reg
);
21652 RTX_FRAME_RELATED_P (tmp
) = 1;
21655 XVECEXP (dwarf
, 0, i
) = tmp
;
21659 while (i
< num_regs
)
21660 if (saved_regs_mask
& (1 << regno
))
21662 rtx reg1
, reg2
, mem1
, mem2
;
21663 rtx tmp0
, tmp1
, tmp2
;
21666 /* Find the register to pair with this one. */
21667 for (regno2
= regno
+ 1; (saved_regs_mask
& (1 << regno2
)) == 0;
21671 reg1
= gen_rtx_REG (SImode
, regno
);
21672 reg2
= gen_rtx_REG (SImode
, regno2
);
21679 mem1
= gen_frame_mem (Pmode
, plus_constant (Pmode
,
21682 mem2
= gen_frame_mem (Pmode
, plus_constant (Pmode
,
21684 -4 * (num_regs
- 1)));
21685 tmp0
= gen_rtx_SET (stack_pointer_rtx
,
21686 plus_constant (Pmode
, stack_pointer_rtx
,
21688 tmp1
= gen_rtx_SET (mem1
, reg1
);
21689 tmp2
= gen_rtx_SET (mem2
, reg2
);
21690 RTX_FRAME_RELATED_P (tmp0
) = 1;
21691 RTX_FRAME_RELATED_P (tmp1
) = 1;
21692 RTX_FRAME_RELATED_P (tmp2
) = 1;
21693 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (3));
21694 XVECEXP (par
, 0, 0) = tmp0
;
21695 XVECEXP (par
, 0, 1) = tmp1
;
21696 XVECEXP (par
, 0, 2) = tmp2
;
21697 insn
= emit_insn (par
);
21698 RTX_FRAME_RELATED_P (insn
) = 1;
21699 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
21703 mem1
= gen_frame_mem (Pmode
, plus_constant (Pmode
,
21706 mem2
= gen_frame_mem (Pmode
, plus_constant (Pmode
,
21709 tmp1
= gen_rtx_SET (mem1
, reg1
);
21710 tmp2
= gen_rtx_SET (mem2
, reg2
);
21711 RTX_FRAME_RELATED_P (tmp1
) = 1;
21712 RTX_FRAME_RELATED_P (tmp2
) = 1;
21713 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
21714 XVECEXP (par
, 0, 0) = tmp1
;
21715 XVECEXP (par
, 0, 1) = tmp2
;
21719 /* Create unwind information. This is an approximation. */
21720 tmp1
= gen_rtx_SET (gen_frame_mem (Pmode
,
21721 plus_constant (Pmode
,
21725 tmp2
= gen_rtx_SET (gen_frame_mem (Pmode
,
21726 plus_constant (Pmode
,
21731 RTX_FRAME_RELATED_P (tmp1
) = 1;
21732 RTX_FRAME_RELATED_P (tmp2
) = 1;
21733 XVECEXP (dwarf
, 0, i
+ 1) = tmp1
;
21734 XVECEXP (dwarf
, 0, i
+ 2) = tmp2
;
21736 regno
= regno2
+ 1;
21744 /* STRD in ARM mode requires consecutive registers. This function emits STRD
21745 whenever possible, otherwise it emits single-word stores. The first store
21746 also allocates stack space for all saved registers, using writeback with
21747 post-addressing mode. All other stores use offset addressing. If no STRD
21748 can be emitted, this function emits a sequence of single-word stores,
21749 and not an STM as before, because single-word stores provide more freedom
21750 scheduling and can be turned into an STM by peephole optimizations. */
21752 arm_emit_strd_push (unsigned long saved_regs_mask
)
21755 int i
, j
, dwarf_index
= 0;
21757 rtx dwarf
= NULL_RTX
;
21758 rtx insn
= NULL_RTX
;
21761 /* TODO: A more efficient code can be emitted by changing the
21762 layout, e.g., first push all pairs that can use STRD to keep the
21763 stack aligned, and then push all other registers. */
21764 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
21765 if (saved_regs_mask
& (1 << i
))
21768 gcc_assert (!(saved_regs_mask
& (1 << SP_REGNUM
)));
21769 gcc_assert (!(saved_regs_mask
& (1 << PC_REGNUM
)));
21770 gcc_assert (num_regs
> 0);
21772 /* Create sequence for DWARF info. */
21773 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_regs
+ 1));
21775 /* For dwarf info, we generate explicit stack update. */
21776 tmp
= gen_rtx_SET (stack_pointer_rtx
,
21777 plus_constant (Pmode
, stack_pointer_rtx
, -4 * num_regs
));
21778 RTX_FRAME_RELATED_P (tmp
) = 1;
21779 XVECEXP (dwarf
, 0, dwarf_index
++) = tmp
;
21781 /* Save registers. */
21782 offset
= - 4 * num_regs
;
21784 while (j
<= LAST_ARM_REGNUM
)
21785 if (saved_regs_mask
& (1 << j
))
21788 && (saved_regs_mask
& (1 << (j
+ 1))))
21790 /* Current register and previous register form register pair for
21791 which STRD can be generated. */
21794 /* Allocate stack space for all saved registers. */
21795 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, offset
);
21796 tmp
= gen_rtx_PRE_MODIFY (Pmode
, stack_pointer_rtx
, tmp
);
21797 mem
= gen_frame_mem (DImode
, tmp
);
21800 else if (offset
> 0)
21801 mem
= gen_frame_mem (DImode
,
21802 plus_constant (Pmode
,
21806 mem
= gen_frame_mem (DImode
, stack_pointer_rtx
);
21808 tmp
= gen_rtx_SET (mem
, gen_rtx_REG (DImode
, j
));
21809 RTX_FRAME_RELATED_P (tmp
) = 1;
21810 tmp
= emit_insn (tmp
);
21812 /* Record the first store insn. */
21813 if (dwarf_index
== 1)
21816 /* Generate dwarf info. */
21817 mem
= gen_frame_mem (SImode
,
21818 plus_constant (Pmode
,
21821 tmp
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, j
));
21822 RTX_FRAME_RELATED_P (tmp
) = 1;
21823 XVECEXP (dwarf
, 0, dwarf_index
++) = tmp
;
21825 mem
= gen_frame_mem (SImode
,
21826 plus_constant (Pmode
,
21829 tmp
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, j
+ 1));
21830 RTX_FRAME_RELATED_P (tmp
) = 1;
21831 XVECEXP (dwarf
, 0, dwarf_index
++) = tmp
;
21838 /* Emit a single word store. */
21841 /* Allocate stack space for all saved registers. */
21842 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, offset
);
21843 tmp
= gen_rtx_PRE_MODIFY (Pmode
, stack_pointer_rtx
, tmp
);
21844 mem
= gen_frame_mem (SImode
, tmp
);
21847 else if (offset
> 0)
21848 mem
= gen_frame_mem (SImode
,
21849 plus_constant (Pmode
,
21853 mem
= gen_frame_mem (SImode
, stack_pointer_rtx
);
21855 tmp
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, j
));
21856 RTX_FRAME_RELATED_P (tmp
) = 1;
21857 tmp
= emit_insn (tmp
);
21859 /* Record the first store insn. */
21860 if (dwarf_index
== 1)
21863 /* Generate dwarf info. */
21864 mem
= gen_frame_mem (SImode
,
21865 plus_constant(Pmode
,
21868 tmp
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, j
));
21869 RTX_FRAME_RELATED_P (tmp
) = 1;
21870 XVECEXP (dwarf
, 0, dwarf_index
++) = tmp
;
21879 /* Attach dwarf info to the first insn we generate. */
21880 gcc_assert (insn
!= NULL_RTX
);
21881 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
21882 RTX_FRAME_RELATED_P (insn
) = 1;
21885 /* Generate and emit an insn that we will recognize as a push_multi.
21886 Unfortunately, since this insn does not reflect very well the actual
21887 semantics of the operation, we need to annotate the insn for the benefit
21888 of DWARF2 frame unwind information. DWARF_REGS_MASK is a subset of
21889 MASK for registers that should be annotated for DWARF2 frame unwind
21892 emit_multi_reg_push (unsigned long mask
, unsigned long dwarf_regs_mask
)
21895 int num_dwarf_regs
= 0;
21899 int dwarf_par_index
;
21902 /* We don't record the PC in the dwarf frame information. */
21903 dwarf_regs_mask
&= ~(1 << PC_REGNUM
);
21905 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
21907 if (mask
& (1 << i
))
21909 if (dwarf_regs_mask
& (1 << i
))
21913 gcc_assert (num_regs
&& num_regs
<= 16);
21914 gcc_assert ((dwarf_regs_mask
& ~mask
) == 0);
21916 /* For the body of the insn we are going to generate an UNSPEC in
21917 parallel with several USEs. This allows the insn to be recognized
21918 by the push_multi pattern in the arm.md file.
21920 The body of the insn looks something like this:
21923 (set (mem:BLK (pre_modify:SI (reg:SI sp)
21924 (const_int:SI <num>)))
21925 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
21931 For the frame note however, we try to be more explicit and actually
21932 show each register being stored into the stack frame, plus a (single)
21933 decrement of the stack pointer. We do it this way in order to be
21934 friendly to the stack unwinding code, which only wants to see a single
21935 stack decrement per instruction. The RTL we generate for the note looks
21936 something like this:
21939 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
21940 (set (mem:SI (reg:SI sp)) (reg:SI r4))
21941 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI XX))
21942 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI YY))
21946 FIXME:: In an ideal world the PRE_MODIFY would not exist and
21947 instead we'd have a parallel expression detailing all
21948 the stores to the various memory addresses so that debug
21949 information is more up-to-date. Remember however while writing
21950 this to take care of the constraints with the push instruction.
21952 Note also that this has to be taken care of for the VFP registers.
21954 For more see PR43399. */
21956 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
21957 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
21958 dwarf_par_index
= 1;
21960 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
21962 if (mask
& (1 << i
))
21964 reg
= gen_rtx_REG (SImode
, i
);
21966 XVECEXP (par
, 0, 0)
21967 = gen_rtx_SET (gen_frame_mem
21969 gen_rtx_PRE_MODIFY (Pmode
,
21972 (Pmode
, stack_pointer_rtx
,
21975 gen_rtx_UNSPEC (BLKmode
,
21976 gen_rtvec (1, reg
),
21977 UNSPEC_PUSH_MULT
));
21979 if (dwarf_regs_mask
& (1 << i
))
21981 tmp
= gen_rtx_SET (gen_frame_mem (SImode
, stack_pointer_rtx
),
21983 RTX_FRAME_RELATED_P (tmp
) = 1;
21984 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
21991 for (j
= 1, i
++; j
< num_regs
; i
++)
21993 if (mask
& (1 << i
))
21995 reg
= gen_rtx_REG (SImode
, i
);
21997 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
21999 if (dwarf_regs_mask
& (1 << i
))
22002 = gen_rtx_SET (gen_frame_mem
22004 plus_constant (Pmode
, stack_pointer_rtx
,
22007 RTX_FRAME_RELATED_P (tmp
) = 1;
22008 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
22015 par
= emit_insn (par
);
22017 tmp
= gen_rtx_SET (stack_pointer_rtx
,
22018 plus_constant (Pmode
, stack_pointer_rtx
, -4 * num_regs
));
22019 RTX_FRAME_RELATED_P (tmp
) = 1;
22020 XVECEXP (dwarf
, 0, 0) = tmp
;
22022 add_reg_note (par
, REG_FRAME_RELATED_EXPR
, dwarf
);
22027 /* Add a REG_CFA_ADJUST_CFA REG note to INSN.
22028 SIZE is the offset to be adjusted.
22029 DEST and SRC might be stack_pointer_rtx or hard_frame_pointer_rtx. */
22031 arm_add_cfa_adjust_cfa_note (rtx insn
, int size
, rtx dest
, rtx src
)
22035 RTX_FRAME_RELATED_P (insn
) = 1;
22036 dwarf
= gen_rtx_SET (dest
, plus_constant (Pmode
, src
, size
));
22037 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, dwarf
);
22040 /* Generate and emit an insn pattern that we will recognize as a pop_multi.
22041 SAVED_REGS_MASK shows which registers need to be restored.
22043 Unfortunately, since this insn does not reflect very well the actual
22044 semantics of the operation, we need to annotate the insn for the benefit
22045 of DWARF2 frame unwind information. */
22047 arm_emit_multi_reg_pop (unsigned long saved_regs_mask
)
22052 rtx dwarf
= NULL_RTX
;
22054 bool return_in_pc
= saved_regs_mask
& (1 << PC_REGNUM
);
22058 offset_adj
= return_in_pc
? 1 : 0;
22059 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
22060 if (saved_regs_mask
& (1 << i
))
22063 gcc_assert (num_regs
&& num_regs
<= 16);
22065 /* If SP is in reglist, then we don't emit SP update insn. */
22066 emit_update
= (saved_regs_mask
& (1 << SP_REGNUM
)) ? 0 : 1;
22068 /* The parallel needs to hold num_regs SETs
22069 and one SET for the stack update. */
22070 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
+ emit_update
+ offset_adj
));
22073 XVECEXP (par
, 0, 0) = ret_rtx
;
22077 /* Increment the stack pointer, based on there being
22078 num_regs 4-byte registers to restore. */
22079 tmp
= gen_rtx_SET (stack_pointer_rtx
,
22080 plus_constant (Pmode
,
22083 RTX_FRAME_RELATED_P (tmp
) = 1;
22084 XVECEXP (par
, 0, offset_adj
) = tmp
;
22087 /* Now restore every reg, which may include PC. */
22088 for (j
= 0, i
= 0; j
< num_regs
; i
++)
22089 if (saved_regs_mask
& (1 << i
))
22091 reg
= gen_rtx_REG (SImode
, i
);
22092 if ((num_regs
== 1) && emit_update
&& !return_in_pc
)
22094 /* Emit single load with writeback. */
22095 tmp
= gen_frame_mem (SImode
,
22096 gen_rtx_POST_INC (Pmode
,
22097 stack_pointer_rtx
));
22098 tmp
= emit_insn (gen_rtx_SET (reg
, tmp
));
22099 REG_NOTES (tmp
) = alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
22103 tmp
= gen_rtx_SET (reg
,
22106 plus_constant (Pmode
, stack_pointer_rtx
, 4 * j
)));
22107 RTX_FRAME_RELATED_P (tmp
) = 1;
22108 XVECEXP (par
, 0, j
+ emit_update
+ offset_adj
) = tmp
;
22110 /* We need to maintain a sequence for DWARF info too. As dwarf info
22111 should not have PC, skip PC. */
22112 if (i
!= PC_REGNUM
)
22113 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
22119 par
= emit_jump_insn (par
);
22121 par
= emit_insn (par
);
22123 REG_NOTES (par
) = dwarf
;
22125 arm_add_cfa_adjust_cfa_note (par
, UNITS_PER_WORD
* num_regs
,
22126 stack_pointer_rtx
, stack_pointer_rtx
);
22129 /* Generate and emit an insn pattern that we will recognize as a pop_multi
22130 of NUM_REGS consecutive VFP regs, starting at FIRST_REG.
22132 Unfortunately, since this insn does not reflect very well the actual
22133 semantics of the operation, we need to annotate the insn for the benefit
22134 of DWARF2 frame unwind information. */
22136 arm_emit_vfp_multi_reg_pop (int first_reg
, int num_regs
, rtx base_reg
)
22140 rtx dwarf
= NULL_RTX
;
22143 gcc_assert (num_regs
&& num_regs
<= 32);
22145 /* Workaround ARM10 VFPr1 bug. */
22146 if (num_regs
== 2 && !arm_arch6
)
22148 if (first_reg
== 15)
22154 /* We can emit at most 16 D-registers in a single pop_multi instruction, and
22155 there could be up to 32 D-registers to restore.
22156 If there are more than 16 D-registers, make two recursive calls,
22157 each of which emits one pop_multi instruction. */
22160 arm_emit_vfp_multi_reg_pop (first_reg
, 16, base_reg
);
22161 arm_emit_vfp_multi_reg_pop (first_reg
+ 16, num_regs
- 16, base_reg
);
22165 /* The parallel needs to hold num_regs SETs
22166 and one SET for the stack update. */
22167 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
+ 1));
22169 /* Increment the stack pointer, based on there being
22170 num_regs 8-byte registers to restore. */
22171 tmp
= gen_rtx_SET (base_reg
, plus_constant (Pmode
, base_reg
, 8 * num_regs
));
22172 RTX_FRAME_RELATED_P (tmp
) = 1;
22173 XVECEXP (par
, 0, 0) = tmp
;
22175 /* Now show every reg that will be restored, using a SET for each. */
22176 for (j
= 0, i
=first_reg
; j
< num_regs
; i
+= 2)
22178 reg
= gen_rtx_REG (DFmode
, i
);
22180 tmp
= gen_rtx_SET (reg
,
22183 plus_constant (Pmode
, base_reg
, 8 * j
)));
22184 RTX_FRAME_RELATED_P (tmp
) = 1;
22185 XVECEXP (par
, 0, j
+ 1) = tmp
;
22187 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
22192 par
= emit_insn (par
);
22193 REG_NOTES (par
) = dwarf
;
22195 /* Make sure cfa doesn't leave with IP_REGNUM to allow unwinding fron FP. */
22196 if (REGNO (base_reg
) == IP_REGNUM
)
22198 RTX_FRAME_RELATED_P (par
) = 1;
22199 add_reg_note (par
, REG_CFA_DEF_CFA
, hard_frame_pointer_rtx
);
22202 arm_add_cfa_adjust_cfa_note (par
, 2 * UNITS_PER_WORD
* num_regs
,
22203 base_reg
, base_reg
);
22206 /* Generate and emit a pattern that will be recognized as LDRD pattern. If even
22207 number of registers are being popped, multiple LDRD patterns are created for
22208 all register pairs. If odd number of registers are popped, last register is
22209 loaded by using LDR pattern. */
22211 thumb2_emit_ldrd_pop (unsigned long saved_regs_mask
)
22215 rtx par
= NULL_RTX
;
22216 rtx dwarf
= NULL_RTX
;
22217 rtx tmp
, reg
, tmp1
;
22218 bool return_in_pc
= saved_regs_mask
& (1 << PC_REGNUM
);
22220 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
22221 if (saved_regs_mask
& (1 << i
))
22224 gcc_assert (num_regs
&& num_regs
<= 16);
22226 /* We cannot generate ldrd for PC. Hence, reduce the count if PC is
22227 to be popped. So, if num_regs is even, now it will become odd,
22228 and we can generate pop with PC. If num_regs is odd, it will be
22229 even now, and ldr with return can be generated for PC. */
22233 gcc_assert (!(saved_regs_mask
& (1 << SP_REGNUM
)));
22235 /* Var j iterates over all the registers to gather all the registers in
22236 saved_regs_mask. Var i gives index of saved registers in stack frame.
22237 A PARALLEL RTX of register-pair is created here, so that pattern for
22238 LDRD can be matched. As PC is always last register to be popped, and
22239 we have already decremented num_regs if PC, we don't have to worry
22240 about PC in this loop. */
22241 for (i
= 0, j
= 0; i
< (num_regs
- (num_regs
% 2)); j
++)
22242 if (saved_regs_mask
& (1 << j
))
22244 /* Create RTX for memory load. */
22245 reg
= gen_rtx_REG (SImode
, j
);
22246 tmp
= gen_rtx_SET (reg
,
22247 gen_frame_mem (SImode
,
22248 plus_constant (Pmode
,
22249 stack_pointer_rtx
, 4 * i
)));
22250 RTX_FRAME_RELATED_P (tmp
) = 1;
22254 /* When saved-register index (i) is even, the RTX to be emitted is
22255 yet to be created. Hence create it first. The LDRD pattern we
22256 are generating is :
22257 [ (SET (reg_t0) (MEM (PLUS (SP) (NUM))))
22258 (SET (reg_t1) (MEM (PLUS (SP) (NUM + 4)))) ]
22259 where target registers need not be consecutive. */
22260 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
22264 /* ith register is added in PARALLEL RTX. If i is even, the reg_i is
22265 added as 0th element and if i is odd, reg_i is added as 1st element
22266 of LDRD pattern shown above. */
22267 XVECEXP (par
, 0, (i
% 2)) = tmp
;
22268 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
22272 /* When saved-register index (i) is odd, RTXs for both the registers
22273 to be loaded are generated in above given LDRD pattern, and the
22274 pattern can be emitted now. */
22275 par
= emit_insn (par
);
22276 REG_NOTES (par
) = dwarf
;
22277 RTX_FRAME_RELATED_P (par
) = 1;
22283 /* If the number of registers pushed is odd AND return_in_pc is false OR
22284 number of registers are even AND return_in_pc is true, last register is
22285 popped using LDR. It can be PC as well. Hence, adjust the stack first and
22286 then LDR with post increment. */
22288 /* Increment the stack pointer, based on there being
22289 num_regs 4-byte registers to restore. */
22290 tmp
= gen_rtx_SET (stack_pointer_rtx
,
22291 plus_constant (Pmode
, stack_pointer_rtx
, 4 * i
));
22292 RTX_FRAME_RELATED_P (tmp
) = 1;
22293 tmp
= emit_insn (tmp
);
22296 arm_add_cfa_adjust_cfa_note (tmp
, UNITS_PER_WORD
* i
,
22297 stack_pointer_rtx
, stack_pointer_rtx
);
22302 if (((num_regs
% 2) == 1 && !return_in_pc
)
22303 || ((num_regs
% 2) == 0 && return_in_pc
))
22305 /* Scan for the single register to be popped. Skip until the saved
22306 register is found. */
22307 for (; (saved_regs_mask
& (1 << j
)) == 0; j
++);
22309 /* Gen LDR with post increment here. */
22310 tmp1
= gen_rtx_MEM (SImode
,
22311 gen_rtx_POST_INC (SImode
,
22312 stack_pointer_rtx
));
22313 set_mem_alias_set (tmp1
, get_frame_alias_set ());
22315 reg
= gen_rtx_REG (SImode
, j
);
22316 tmp
= gen_rtx_SET (reg
, tmp1
);
22317 RTX_FRAME_RELATED_P (tmp
) = 1;
22318 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
22322 /* If return_in_pc, j must be PC_REGNUM. */
22323 gcc_assert (j
== PC_REGNUM
);
22324 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
22325 XVECEXP (par
, 0, 0) = ret_rtx
;
22326 XVECEXP (par
, 0, 1) = tmp
;
22327 par
= emit_jump_insn (par
);
22331 par
= emit_insn (tmp
);
22332 REG_NOTES (par
) = dwarf
;
22333 arm_add_cfa_adjust_cfa_note (par
, UNITS_PER_WORD
,
22334 stack_pointer_rtx
, stack_pointer_rtx
);
22338 else if ((num_regs
% 2) == 1 && return_in_pc
)
22340 /* There are 2 registers to be popped. So, generate the pattern
22341 pop_multiple_with_stack_update_and_return to pop in PC. */
22342 arm_emit_multi_reg_pop (saved_regs_mask
& (~((1 << j
) - 1)));
22348 /* LDRD in ARM mode needs consecutive registers as operands. This function
22349 emits LDRD whenever possible, otherwise it emits single-word loads. It uses
22350 offset addressing and then generates one separate stack udpate. This provides
22351 more scheduling freedom, compared to writeback on every load. However,
22352 if the function returns using load into PC directly
22353 (i.e., if PC is in SAVED_REGS_MASK), the stack needs to be updated
22354 before the last load. TODO: Add a peephole optimization to recognize
22355 the new epilogue sequence as an LDM instruction whenever possible. TODO: Add
22356 peephole optimization to merge the load at stack-offset zero
22357 with the stack update instruction using load with writeback
22358 in post-index addressing mode. */
22360 arm_emit_ldrd_pop (unsigned long saved_regs_mask
)
22364 rtx par
= NULL_RTX
;
22365 rtx dwarf
= NULL_RTX
;
22368 /* Restore saved registers. */
22369 gcc_assert (!((saved_regs_mask
& (1 << SP_REGNUM
))));
22371 while (j
<= LAST_ARM_REGNUM
)
22372 if (saved_regs_mask
& (1 << j
))
22375 && (saved_regs_mask
& (1 << (j
+ 1)))
22376 && (j
+ 1) != PC_REGNUM
)
22378 /* Current register and next register form register pair for which
22379 LDRD can be generated. PC is always the last register popped, and
22380 we handle it separately. */
22382 mem
= gen_frame_mem (DImode
,
22383 plus_constant (Pmode
,
22387 mem
= gen_frame_mem (DImode
, stack_pointer_rtx
);
22389 tmp
= gen_rtx_SET (gen_rtx_REG (DImode
, j
), mem
);
22390 tmp
= emit_insn (tmp
);
22391 RTX_FRAME_RELATED_P (tmp
) = 1;
22393 /* Generate dwarf info. */
22395 dwarf
= alloc_reg_note (REG_CFA_RESTORE
,
22396 gen_rtx_REG (SImode
, j
),
22398 dwarf
= alloc_reg_note (REG_CFA_RESTORE
,
22399 gen_rtx_REG (SImode
, j
+ 1),
22402 REG_NOTES (tmp
) = dwarf
;
22407 else if (j
!= PC_REGNUM
)
22409 /* Emit a single word load. */
22411 mem
= gen_frame_mem (SImode
,
22412 plus_constant (Pmode
,
22416 mem
= gen_frame_mem (SImode
, stack_pointer_rtx
);
22418 tmp
= gen_rtx_SET (gen_rtx_REG (SImode
, j
), mem
);
22419 tmp
= emit_insn (tmp
);
22420 RTX_FRAME_RELATED_P (tmp
) = 1;
22422 /* Generate dwarf info. */
22423 REG_NOTES (tmp
) = alloc_reg_note (REG_CFA_RESTORE
,
22424 gen_rtx_REG (SImode
, j
),
22430 else /* j == PC_REGNUM */
22436 /* Update the stack. */
22439 tmp
= gen_rtx_SET (stack_pointer_rtx
,
22440 plus_constant (Pmode
,
22443 tmp
= emit_insn (tmp
);
22444 arm_add_cfa_adjust_cfa_note (tmp
, offset
,
22445 stack_pointer_rtx
, stack_pointer_rtx
);
22449 if (saved_regs_mask
& (1 << PC_REGNUM
))
22451 /* Only PC is to be popped. */
22452 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
22453 XVECEXP (par
, 0, 0) = ret_rtx
;
22454 tmp
= gen_rtx_SET (gen_rtx_REG (SImode
, PC_REGNUM
),
22455 gen_frame_mem (SImode
,
22456 gen_rtx_POST_INC (SImode
,
22457 stack_pointer_rtx
)));
22458 RTX_FRAME_RELATED_P (tmp
) = 1;
22459 XVECEXP (par
, 0, 1) = tmp
;
22460 par
= emit_jump_insn (par
);
22462 /* Generate dwarf info. */
22463 dwarf
= alloc_reg_note (REG_CFA_RESTORE
,
22464 gen_rtx_REG (SImode
, PC_REGNUM
),
22466 REG_NOTES (par
) = dwarf
;
22467 arm_add_cfa_adjust_cfa_note (par
, UNITS_PER_WORD
,
22468 stack_pointer_rtx
, stack_pointer_rtx
);
22472 /* Calculate the size of the return value that is passed in registers. */
22474 arm_size_return_regs (void)
22478 if (crtl
->return_rtx
!= 0)
22479 mode
= GET_MODE (crtl
->return_rtx
);
22481 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
22483 return GET_MODE_SIZE (mode
);
22486 /* Return true if the current function needs to save/restore LR. */
22488 thumb_force_lr_save (void)
22490 return !cfun
->machine
->lr_save_eliminated
22492 || thumb_far_jump_used_p ()
22493 || df_regs_ever_live_p (LR_REGNUM
));
22496 /* We do not know if r3 will be available because
22497 we do have an indirect tailcall happening in this
22498 particular case. */
22500 is_indirect_tailcall_p (rtx call
)
22502 rtx pat
= PATTERN (call
);
22504 /* Indirect tail call. */
22505 pat
= XVECEXP (pat
, 0, 0);
22506 if (GET_CODE (pat
) == SET
)
22507 pat
= SET_SRC (pat
);
22509 pat
= XEXP (XEXP (pat
, 0), 0);
22510 return REG_P (pat
);
22513 /* Return true if r3 is used by any of the tail call insns in the
22514 current function. */
22516 any_sibcall_could_use_r3 (void)
22521 if (!crtl
->tail_call_emit
)
22523 FOR_EACH_EDGE (e
, ei
, EXIT_BLOCK_PTR_FOR_FN (cfun
)->preds
)
22524 if (e
->flags
& EDGE_SIBCALL
)
22526 rtx_insn
*call
= BB_END (e
->src
);
22527 if (!CALL_P (call
))
22528 call
= prev_nonnote_nondebug_insn (call
);
22529 gcc_assert (CALL_P (call
) && SIBLING_CALL_P (call
));
22530 if (find_regno_fusage (call
, USE
, 3)
22531 || is_indirect_tailcall_p (call
))
22538 /* Compute the distance from register FROM to register TO.
22539 These can be the arg pointer (26), the soft frame pointer (25),
22540 the stack pointer (13) or the hard frame pointer (11).
22541 In thumb mode r7 is used as the soft frame pointer, if needed.
22542 Typical stack layout looks like this:
22544 old stack pointer -> | |
22547 | | saved arguments for
22548 | | vararg functions
22551 hard FP & arg pointer -> | | \
22559 soft frame pointer -> | | /
22564 locals base pointer -> | | /
22569 current stack pointer -> | | /
22572 For a given function some or all of these stack components
22573 may not be needed, giving rise to the possibility of
22574 eliminating some of the registers.
22576 The values returned by this function must reflect the behavior
22577 of arm_expand_prologue () and arm_compute_save_core_reg_mask ().
22579 The sign of the number returned reflects the direction of stack
22580 growth, so the values are positive for all eliminations except
22581 from the soft frame pointer to the hard frame pointer.
22583 SFP may point just inside the local variables block to ensure correct
22587 /* Return cached stack offsets. */
22589 static arm_stack_offsets
*
22590 arm_get_frame_offsets (void)
22592 struct arm_stack_offsets
*offsets
;
22594 offsets
= &cfun
->machine
->stack_offsets
;
22600 /* Calculate stack offsets. These are used to calculate register elimination
22601 offsets and in prologue/epilogue code. Also calculates which registers
22602 should be saved. */
22605 arm_compute_frame_layout (void)
22607 struct arm_stack_offsets
*offsets
;
22608 unsigned long func_type
;
22611 HOST_WIDE_INT frame_size
;
22614 offsets
= &cfun
->machine
->stack_offsets
;
22616 /* Initially this is the size of the local variables. It will translated
22617 into an offset once we have determined the size of preceding data. */
22618 frame_size
= ROUND_UP_WORD (get_frame_size ());
22620 /* Space for variadic functions. */
22621 offsets
->saved_args
= crtl
->args
.pretend_args_size
;
22623 /* In Thumb mode this is incorrect, but never used. */
22625 = (offsets
->saved_args
22626 + arm_compute_static_chain_stack_bytes ()
22627 + (frame_pointer_needed
? 4 : 0));
22631 unsigned int regno
;
22633 offsets
->saved_regs_mask
= arm_compute_save_core_reg_mask ();
22634 core_saved
= bit_count (offsets
->saved_regs_mask
) * 4;
22635 saved
= core_saved
;
22637 /* We know that SP will be doubleword aligned on entry, and we must
22638 preserve that condition at any subroutine call. We also require the
22639 soft frame pointer to be doubleword aligned. */
22641 if (TARGET_REALLY_IWMMXT
)
22643 /* Check for the call-saved iWMMXt registers. */
22644 for (regno
= FIRST_IWMMXT_REGNUM
;
22645 regno
<= LAST_IWMMXT_REGNUM
;
22647 if (reg_needs_saving_p (regno
))
22651 func_type
= arm_current_func_type ();
22652 /* Space for saved VFP registers. */
22653 if (! IS_VOLATILE (func_type
)
22654 && TARGET_VFP_BASE
)
22655 saved
+= arm_get_vfp_saved_size ();
22657 /* Allocate space for saving/restoring FPCXTNS in Armv8.1-M Mainline
22658 nonecure entry functions with VSTR/VLDR. */
22659 if (TARGET_HAVE_FPCXT_CMSE
&& IS_CMSE_ENTRY (func_type
))
22662 else /* TARGET_THUMB1 */
22664 offsets
->saved_regs_mask
= thumb1_compute_save_core_reg_mask ();
22665 core_saved
= bit_count (offsets
->saved_regs_mask
) * 4;
22666 saved
= core_saved
;
22667 if (TARGET_BACKTRACE
)
22671 /* Saved registers include the stack frame. */
22672 offsets
->saved_regs
22673 = offsets
->saved_args
+ arm_compute_static_chain_stack_bytes () + saved
;
22674 offsets
->soft_frame
= offsets
->saved_regs
+ CALLER_INTERWORKING_SLOT_SIZE
;
22676 /* A leaf function does not need any stack alignment if it has nothing
22678 if (crtl
->is_leaf
&& frame_size
== 0
22679 /* However if it calls alloca(), we have a dynamically allocated
22680 block of BIGGEST_ALIGNMENT on stack, so still do stack alignment. */
22681 && ! cfun
->calls_alloca
)
22683 offsets
->outgoing_args
= offsets
->soft_frame
;
22684 offsets
->locals_base
= offsets
->soft_frame
;
22688 /* Ensure SFP has the correct alignment. */
22689 if (ARM_DOUBLEWORD_ALIGN
22690 && (offsets
->soft_frame
& 7))
22692 offsets
->soft_frame
+= 4;
22693 /* Try to align stack by pushing an extra reg. Don't bother doing this
22694 when there is a stack frame as the alignment will be rolled into
22695 the normal stack adjustment. */
22696 if (frame_size
+ crtl
->outgoing_args_size
== 0)
22700 /* Register r3 is caller-saved. Normally it does not need to be
22701 saved on entry by the prologue. However if we choose to save
22702 it for padding then we may confuse the compiler into thinking
22703 a prologue sequence is required when in fact it is not. This
22704 will occur when shrink-wrapping if r3 is used as a scratch
22705 register and there are no other callee-saved writes.
22707 This situation can be avoided when other callee-saved registers
22708 are available and r3 is not mandatory if we choose a callee-saved
22709 register for padding. */
22710 bool prefer_callee_reg_p
= false;
22712 /* If it is safe to use r3, then do so. This sometimes
22713 generates better code on Thumb-2 by avoiding the need to
22714 use 32-bit push/pop instructions. */
22715 if (! any_sibcall_could_use_r3 ()
22716 && arm_size_return_regs () <= 12
22717 && (offsets
->saved_regs_mask
& (1 << 3)) == 0
22719 || !(TARGET_LDRD
&& current_tune
->prefer_ldrd_strd
)))
22722 if (!TARGET_THUMB2
)
22723 prefer_callee_reg_p
= true;
22726 || prefer_callee_reg_p
)
22728 for (i
= 4; i
<= (TARGET_THUMB1
? LAST_LO_REGNUM
: 11); i
++)
22730 /* Avoid fixed registers; they may be changed at
22731 arbitrary times so it's unsafe to restore them
22732 during the epilogue. */
22734 && (offsets
->saved_regs_mask
& (1 << i
)) == 0)
22744 offsets
->saved_regs
+= 4;
22745 offsets
->saved_regs_mask
|= (1 << reg
);
22750 offsets
->locals_base
= offsets
->soft_frame
+ frame_size
;
22751 offsets
->outgoing_args
= (offsets
->locals_base
22752 + crtl
->outgoing_args_size
);
22754 if (ARM_DOUBLEWORD_ALIGN
)
22756 /* Ensure SP remains doubleword aligned. */
22757 if (offsets
->outgoing_args
& 7)
22758 offsets
->outgoing_args
+= 4;
22759 gcc_assert (!(offsets
->outgoing_args
& 7));
22764 /* Calculate the relative offsets for the different stack pointers. Positive
22765 offsets are in the direction of stack growth. */
22768 arm_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
22770 arm_stack_offsets
*offsets
;
22772 offsets
= arm_get_frame_offsets ();
22774 /* OK, now we have enough information to compute the distances.
22775 There must be an entry in these switch tables for each pair
22776 of registers in ELIMINABLE_REGS, even if some of the entries
22777 seem to be redundant or useless. */
22780 case ARG_POINTER_REGNUM
:
22783 case THUMB_HARD_FRAME_POINTER_REGNUM
:
22786 case FRAME_POINTER_REGNUM
:
22787 /* This is the reverse of the soft frame pointer
22788 to hard frame pointer elimination below. */
22789 return offsets
->soft_frame
- offsets
->saved_args
;
22791 case ARM_HARD_FRAME_POINTER_REGNUM
:
22792 /* This is only non-zero in the case where the static chain register
22793 is stored above the frame. */
22794 return offsets
->frame
- offsets
->saved_args
- 4;
22796 case STACK_POINTER_REGNUM
:
22797 /* If nothing has been pushed on the stack at all
22798 then this will return -4. This *is* correct! */
22799 return offsets
->outgoing_args
- (offsets
->saved_args
+ 4);
22802 gcc_unreachable ();
22804 gcc_unreachable ();
22806 case FRAME_POINTER_REGNUM
:
22809 case THUMB_HARD_FRAME_POINTER_REGNUM
:
22812 case ARM_HARD_FRAME_POINTER_REGNUM
:
22813 /* The hard frame pointer points to the top entry in the
22814 stack frame. The soft frame pointer to the bottom entry
22815 in the stack frame. If there is no stack frame at all,
22816 then they are identical. */
22818 return offsets
->frame
- offsets
->soft_frame
;
22820 case STACK_POINTER_REGNUM
:
22821 return offsets
->outgoing_args
- offsets
->soft_frame
;
22824 gcc_unreachable ();
22826 gcc_unreachable ();
22829 /* You cannot eliminate from the stack pointer.
22830 In theory you could eliminate from the hard frame
22831 pointer to the stack pointer, but this will never
22832 happen, since if a stack frame is not needed the
22833 hard frame pointer will never be used. */
22834 gcc_unreachable ();
22838 /* Given FROM and TO register numbers, say whether this elimination is
22839 allowed. Frame pointer elimination is automatically handled.
22841 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
22842 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
22843 pointer, we must eliminate FRAME_POINTER_REGNUM into
22844 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
22845 ARG_POINTER_REGNUM. */
22848 arm_can_eliminate (const int from
, const int to
)
22850 return ((to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
) ? false :
22851 (to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
) ? false :
22852 (to
== ARM_HARD_FRAME_POINTER_REGNUM
&& TARGET_THUMB
) ? false :
22853 (to
== THUMB_HARD_FRAME_POINTER_REGNUM
&& TARGET_ARM
) ? false :
22857 /* Emit RTL to save coprocessor registers on function entry. Returns the
22858 number of bytes pushed. */
22861 arm_save_coproc_regs(void)
22863 int saved_size
= 0;
22865 unsigned start_reg
;
22868 if (TARGET_REALLY_IWMMXT
)
22869 for (reg
= LAST_IWMMXT_REGNUM
; reg
>= FIRST_IWMMXT_REGNUM
; reg
--)
22870 if (reg_needs_saving_p (reg
))
22872 insn
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
22873 insn
= gen_rtx_MEM (V2SImode
, insn
);
22874 insn
= emit_set_insn (insn
, gen_rtx_REG (V2SImode
, reg
));
22875 RTX_FRAME_RELATED_P (insn
) = 1;
22879 if (TARGET_VFP_BASE
)
22881 start_reg
= FIRST_VFP_REGNUM
;
22883 for (reg
= FIRST_VFP_REGNUM
; reg
< LAST_VFP_REGNUM
; reg
+= 2)
22885 if (!reg_needs_saving_p (reg
) && !reg_needs_saving_p (reg
+ 1))
22887 if (start_reg
!= reg
)
22888 saved_size
+= vfp_emit_fstmd (start_reg
,
22889 (reg
- start_reg
) / 2);
22890 start_reg
= reg
+ 2;
22893 if (start_reg
!= reg
)
22894 saved_size
+= vfp_emit_fstmd (start_reg
,
22895 (reg
- start_reg
) / 2);
22901 /* Set the Thumb frame pointer from the stack pointer. */
22904 thumb_set_frame_pointer (arm_stack_offsets
*offsets
)
22906 HOST_WIDE_INT amount
;
22909 amount
= offsets
->outgoing_args
- offsets
->locals_base
;
22911 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
22912 stack_pointer_rtx
, GEN_INT (amount
)));
22915 emit_insn (gen_movsi (hard_frame_pointer_rtx
, GEN_INT (amount
)));
22916 /* Thumb-2 RTL patterns expect sp as the first input. Thumb-1
22917 expects the first two operands to be the same. */
22920 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
22922 hard_frame_pointer_rtx
));
22926 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
22927 hard_frame_pointer_rtx
,
22928 stack_pointer_rtx
));
22930 dwarf
= gen_rtx_SET (hard_frame_pointer_rtx
,
22931 plus_constant (Pmode
, stack_pointer_rtx
, amount
));
22932 RTX_FRAME_RELATED_P (dwarf
) = 1;
22933 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
22936 RTX_FRAME_RELATED_P (insn
) = 1;
22939 struct scratch_reg
{
22944 /* Return a short-lived scratch register for use as a 2nd scratch register on
22945 function entry after the registers are saved in the prologue. This register
22946 must be released by means of release_scratch_register_on_entry. IP is not
22947 considered since it is always used as the 1st scratch register if available.
22949 REGNO1 is the index number of the 1st scratch register and LIVE_REGS is the
22950 mask of live registers. */
22953 get_scratch_register_on_entry (struct scratch_reg
*sr
, unsigned int regno1
,
22954 unsigned long live_regs
)
22960 if (regno1
!= LR_REGNUM
&& (live_regs
& (1 << LR_REGNUM
)) != 0)
22966 for (i
= 4; i
< 11; i
++)
22967 if (regno1
!= i
&& (live_regs
& (1 << i
)) != 0)
22975 /* If IP is used as the 1st scratch register for a nested function,
22976 then either r3 wasn't available or is used to preserve IP. */
22977 if (regno1
== IP_REGNUM
&& IS_NESTED (arm_current_func_type ()))
22979 regno
= (regno1
== 3 ? 2 : 3);
22981 = REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR_FOR_FN (cfun
)),
22986 sr
->reg
= gen_rtx_REG (SImode
, regno
);
22989 rtx addr
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
22990 rtx insn
= emit_set_insn (gen_frame_mem (SImode
, addr
), sr
->reg
);
22991 rtx x
= gen_rtx_SET (stack_pointer_rtx
,
22992 plus_constant (Pmode
, stack_pointer_rtx
, -4));
22993 RTX_FRAME_RELATED_P (insn
) = 1;
22994 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, x
);
22998 /* Release a scratch register obtained from the preceding function. */
23001 release_scratch_register_on_entry (struct scratch_reg
*sr
)
23005 rtx addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
23006 rtx insn
= emit_set_insn (sr
->reg
, gen_frame_mem (SImode
, addr
));
23007 rtx x
= gen_rtx_SET (stack_pointer_rtx
,
23008 plus_constant (Pmode
, stack_pointer_rtx
, 4));
23009 RTX_FRAME_RELATED_P (insn
) = 1;
23010 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, x
);
23014 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
23016 #if PROBE_INTERVAL > 4096
23017 #error Cannot use indexed addressing mode for stack probing
23020 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
23021 inclusive. These are offsets from the current stack pointer. REGNO1
23022 is the index number of the 1st scratch register and LIVE_REGS is the
23023 mask of live registers. */
23026 arm_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
,
23027 unsigned int regno1
, unsigned long live_regs
)
23029 rtx reg1
= gen_rtx_REG (Pmode
, regno1
);
23031 /* See if we have a constant small number of probes to generate. If so,
23032 that's the easy case. */
23033 if (size
<= PROBE_INTERVAL
)
23035 emit_move_insn (reg1
, GEN_INT (first
+ PROBE_INTERVAL
));
23036 emit_set_insn (reg1
, gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, reg1
));
23037 emit_stack_probe (plus_constant (Pmode
, reg1
, PROBE_INTERVAL
- size
));
23040 /* The run-time loop is made up of 10 insns in the generic case while the
23041 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
23042 else if (size
<= 5 * PROBE_INTERVAL
)
23044 HOST_WIDE_INT i
, rem
;
23046 emit_move_insn (reg1
, GEN_INT (first
+ PROBE_INTERVAL
));
23047 emit_set_insn (reg1
, gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, reg1
));
23048 emit_stack_probe (reg1
);
23050 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
23051 it exceeds SIZE. If only two probes are needed, this will not
23052 generate any code. Then probe at FIRST + SIZE. */
23053 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
23055 emit_set_insn (reg1
, plus_constant (Pmode
, reg1
, -PROBE_INTERVAL
));
23056 emit_stack_probe (reg1
);
23059 rem
= size
- (i
- PROBE_INTERVAL
);
23060 if (rem
> 4095 || (TARGET_THUMB2
&& rem
> 255))
23062 emit_set_insn (reg1
, plus_constant (Pmode
, reg1
, -PROBE_INTERVAL
));
23063 emit_stack_probe (plus_constant (Pmode
, reg1
, PROBE_INTERVAL
- rem
));
23066 emit_stack_probe (plus_constant (Pmode
, reg1
, -rem
));
23069 /* Otherwise, do the same as above, but in a loop. Note that we must be
23070 extra careful with variables wrapping around because we might be at
23071 the very top (or the very bottom) of the address space and we have
23072 to be able to handle this case properly; in particular, we use an
23073 equality test for the loop condition. */
23076 HOST_WIDE_INT rounded_size
;
23077 struct scratch_reg sr
;
23079 get_scratch_register_on_entry (&sr
, regno1
, live_regs
);
23081 emit_move_insn (reg1
, GEN_INT (first
));
23084 /* Step 1: round SIZE to the previous multiple of the interval. */
23086 rounded_size
= size
& -PROBE_INTERVAL
;
23087 emit_move_insn (sr
.reg
, GEN_INT (rounded_size
));
23090 /* Step 2: compute initial and final value of the loop counter. */
23092 /* TEST_ADDR = SP + FIRST. */
23093 emit_set_insn (reg1
, gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, reg1
));
23095 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
23096 emit_set_insn (sr
.reg
, gen_rtx_MINUS (Pmode
, reg1
, sr
.reg
));
23099 /* Step 3: the loop
23103 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
23106 while (TEST_ADDR != LAST_ADDR)
23108 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
23109 until it is equal to ROUNDED_SIZE. */
23111 emit_insn (gen_probe_stack_range (reg1
, reg1
, sr
.reg
));
23114 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
23115 that SIZE is equal to ROUNDED_SIZE. */
23117 if (size
!= rounded_size
)
23119 HOST_WIDE_INT rem
= size
- rounded_size
;
23121 if (rem
> 4095 || (TARGET_THUMB2
&& rem
> 255))
23123 emit_set_insn (sr
.reg
,
23124 plus_constant (Pmode
, sr
.reg
, -PROBE_INTERVAL
));
23125 emit_stack_probe (plus_constant (Pmode
, sr
.reg
,
23126 PROBE_INTERVAL
- rem
));
23129 emit_stack_probe (plus_constant (Pmode
, sr
.reg
, -rem
));
23132 release_scratch_register_on_entry (&sr
);
23135 /* Make sure nothing is scheduled before we are done. */
23136 emit_insn (gen_blockage ());
23139 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
23140 absolute addresses. */
23143 output_probe_stack_range (rtx reg1
, rtx reg2
)
23145 static int labelno
= 0;
23149 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
23152 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
23154 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
23156 xops
[1] = GEN_INT (PROBE_INTERVAL
);
23157 output_asm_insn ("sub\t%0, %0, %1", xops
);
23159 /* Probe at TEST_ADDR. */
23160 output_asm_insn ("str\tr0, [%0, #0]", xops
);
23162 /* Test if TEST_ADDR == LAST_ADDR. */
23164 output_asm_insn ("cmp\t%0, %1", xops
);
23167 fputs ("\tbne\t", asm_out_file
);
23168 assemble_name_raw (asm_out_file
, loop_lab
);
23169 fputc ('\n', asm_out_file
);
23174 /* Generate the prologue instructions for entry into an ARM or Thumb-2
23177 arm_expand_prologue (void)
23182 unsigned long live_regs_mask
;
23183 unsigned long func_type
;
23185 int saved_pretend_args
= 0;
23186 int saved_regs
= 0;
23187 unsigned HOST_WIDE_INT args_to_push
;
23188 HOST_WIDE_INT size
;
23189 arm_stack_offsets
*offsets
;
23192 func_type
= arm_current_func_type ();
23194 /* Naked functions don't have prologues. */
23195 if (IS_NAKED (func_type
))
23197 if (flag_stack_usage_info
)
23198 current_function_static_stack_size
= 0;
23202 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
23203 args_to_push
= crtl
->args
.pretend_args_size
;
23205 /* Compute which register we will have to save onto the stack. */
23206 offsets
= arm_get_frame_offsets ();
23207 live_regs_mask
= offsets
->saved_regs_mask
;
23209 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
23211 if (IS_STACKALIGN (func_type
))
23215 /* Handle a word-aligned stack pointer. We generate the following:
23220 <save and restore r0 in normal prologue/epilogue>
23224 The unwinder doesn't need to know about the stack realignment.
23225 Just tell it we saved SP in r0. */
23226 gcc_assert (TARGET_THUMB2
&& !arm_arch_notm
&& args_to_push
== 0);
23228 r0
= gen_rtx_REG (SImode
, R0_REGNUM
);
23229 r1
= gen_rtx_REG (SImode
, R1_REGNUM
);
23231 insn
= emit_insn (gen_movsi (r0
, stack_pointer_rtx
));
23232 RTX_FRAME_RELATED_P (insn
) = 1;
23233 add_reg_note (insn
, REG_CFA_REGISTER
, NULL
);
23235 emit_insn (gen_andsi3 (r1
, r0
, GEN_INT (~(HOST_WIDE_INT
)7)));
23237 /* ??? The CFA changes here, which may cause GDB to conclude that it
23238 has entered a different function. That said, the unwind info is
23239 correct, individually, before and after this instruction because
23240 we've described the save of SP, which will override the default
23241 handling of SP as restoring from the CFA. */
23242 emit_insn (gen_movsi (stack_pointer_rtx
, r1
));
23245 /* Let's compute the static_chain_stack_bytes required and store it. Right
23246 now the value must be -1 as stored by arm_init_machine_status (). */
23247 cfun
->machine
->static_chain_stack_bytes
23248 = arm_compute_static_chain_stack_bytes ();
23250 /* The static chain register is the same as the IP register. If it is
23251 clobbered when creating the frame, we need to save and restore it. */
23252 clobber_ip
= IS_NESTED (func_type
)
23253 && ((TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
)
23254 || ((flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
23255 || flag_stack_clash_protection
)
23256 && !df_regs_ever_live_p (LR_REGNUM
)
23257 && arm_r3_live_at_start_p ()));
23259 /* Find somewhere to store IP whilst the frame is being created.
23260 We try the following places in order:
23262 1. The last argument register r3 if it is available.
23263 2. A slot on the stack above the frame if there are no
23264 arguments to push onto the stack.
23265 3. Register r3 again, after pushing the argument registers
23266 onto the stack, if this is a varargs function.
23267 4. The last slot on the stack created for the arguments to
23268 push, if this isn't a varargs function.
23270 Note - we only need to tell the dwarf2 backend about the SP
23271 adjustment in the second variant; the static chain register
23272 doesn't need to be unwound, as it doesn't contain a value
23273 inherited from the caller. */
23276 if (!arm_r3_live_at_start_p ())
23277 insn
= emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
23278 else if (args_to_push
== 0)
23282 gcc_assert(arm_compute_static_chain_stack_bytes() == 4);
23285 addr
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
23286 insn
= emit_set_insn (gen_frame_mem (SImode
, addr
), ip_rtx
);
23289 /* Just tell the dwarf backend that we adjusted SP. */
23290 dwarf
= gen_rtx_SET (stack_pointer_rtx
,
23291 plus_constant (Pmode
, stack_pointer_rtx
,
23293 RTX_FRAME_RELATED_P (insn
) = 1;
23294 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
23298 /* Store the args on the stack. */
23299 if (cfun
->machine
->uses_anonymous_args
)
23301 insn
= emit_multi_reg_push ((0xf0 >> (args_to_push
/ 4)) & 0xf,
23302 (0xf0 >> (args_to_push
/ 4)) & 0xf);
23303 emit_set_insn (gen_rtx_REG (SImode
, 3), ip_rtx
);
23304 saved_pretend_args
= 1;
23310 if (args_to_push
== 4)
23311 addr
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
23313 addr
= gen_rtx_PRE_MODIFY (Pmode
, stack_pointer_rtx
,
23314 plus_constant (Pmode
,
23318 insn
= emit_set_insn (gen_frame_mem (SImode
, addr
), ip_rtx
);
23320 /* Just tell the dwarf backend that we adjusted SP. */
23321 dwarf
= gen_rtx_SET (stack_pointer_rtx
,
23322 plus_constant (Pmode
, stack_pointer_rtx
,
23324 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
23327 RTX_FRAME_RELATED_P (insn
) = 1;
23328 fp_offset
= args_to_push
;
23333 if (TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
)
23335 if (IS_INTERRUPT (func_type
))
23337 /* Interrupt functions must not corrupt any registers.
23338 Creating a frame pointer however, corrupts the IP
23339 register, so we must push it first. */
23340 emit_multi_reg_push (1 << IP_REGNUM
, 1 << IP_REGNUM
);
23342 /* Do not set RTX_FRAME_RELATED_P on this insn.
23343 The dwarf stack unwinding code only wants to see one
23344 stack decrement per function, and this is not it. If
23345 this instruction is labeled as being part of the frame
23346 creation sequence then dwarf2out_frame_debug_expr will
23347 die when it encounters the assignment of IP to FP
23348 later on, since the use of SP here establishes SP as
23349 the CFA register and not IP.
23351 Anyway this instruction is not really part of the stack
23352 frame creation although it is part of the prologue. */
23355 insn
= emit_set_insn (ip_rtx
,
23356 plus_constant (Pmode
, stack_pointer_rtx
,
23358 RTX_FRAME_RELATED_P (insn
) = 1;
23361 /* Armv8.1-M Mainline nonsecure entry: save FPCXTNS on stack using VSTR. */
23362 if (TARGET_HAVE_FPCXT_CMSE
&& IS_CMSE_ENTRY (func_type
))
23365 insn
= emit_insn (gen_push_fpsysreg_insn (stack_pointer_rtx
,
23366 GEN_INT (FPCXTNS_ENUM
)));
23367 rtx dwarf
= gen_rtx_SET (stack_pointer_rtx
,
23368 plus_constant (Pmode
, stack_pointer_rtx
, -4));
23369 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
23370 RTX_FRAME_RELATED_P (insn
) = 1;
23375 /* Push the argument registers, or reserve space for them. */
23376 if (cfun
->machine
->uses_anonymous_args
)
23377 insn
= emit_multi_reg_push
23378 ((0xf0 >> (args_to_push
/ 4)) & 0xf,
23379 (0xf0 >> (args_to_push
/ 4)) & 0xf);
23382 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
23383 GEN_INT (- args_to_push
)));
23384 RTX_FRAME_RELATED_P (insn
) = 1;
23387 /* If this is an interrupt service routine, and the link register
23388 is going to be pushed, and we're not generating extra
23389 push of IP (needed when frame is needed and frame layout if apcs),
23390 subtracting four from LR now will mean that the function return
23391 can be done with a single instruction. */
23392 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
23393 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0
23394 && !(frame_pointer_needed
&& TARGET_APCS_FRAME
)
23397 rtx lr
= gen_rtx_REG (SImode
, LR_REGNUM
);
23399 emit_set_insn (lr
, plus_constant (SImode
, lr
, -4));
23402 if (live_regs_mask
)
23404 unsigned long dwarf_regs_mask
= live_regs_mask
;
23406 saved_regs
+= bit_count (live_regs_mask
) * 4;
23407 if (optimize_size
&& !frame_pointer_needed
23408 && saved_regs
== offsets
->saved_regs
- offsets
->saved_args
)
23410 /* If no coprocessor registers are being pushed and we don't have
23411 to worry about a frame pointer then push extra registers to
23412 create the stack frame. This is done in a way that does not
23413 alter the frame layout, so is independent of the epilogue. */
23417 while (n
< 8 && (live_regs_mask
& (1 << n
)) == 0)
23419 frame
= offsets
->outgoing_args
- (offsets
->saved_args
+ saved_regs
);
23420 if (frame
&& n
* 4 >= frame
)
23423 live_regs_mask
|= (1 << n
) - 1;
23424 saved_regs
+= frame
;
23429 && current_tune
->prefer_ldrd_strd
23430 && !optimize_function_for_size_p (cfun
))
23432 gcc_checking_assert (live_regs_mask
== dwarf_regs_mask
);
23434 thumb2_emit_strd_push (live_regs_mask
);
23435 else if (TARGET_ARM
23436 && !TARGET_APCS_FRAME
23437 && !IS_INTERRUPT (func_type
))
23438 arm_emit_strd_push (live_regs_mask
);
23441 insn
= emit_multi_reg_push (live_regs_mask
, live_regs_mask
);
23442 RTX_FRAME_RELATED_P (insn
) = 1;
23447 insn
= emit_multi_reg_push (live_regs_mask
, dwarf_regs_mask
);
23448 RTX_FRAME_RELATED_P (insn
) = 1;
23452 if (! IS_VOLATILE (func_type
))
23453 saved_regs
+= arm_save_coproc_regs ();
23455 if (frame_pointer_needed
&& TARGET_ARM
)
23457 /* Create the new frame pointer. */
23458 if (TARGET_APCS_FRAME
)
23460 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
23461 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
23462 RTX_FRAME_RELATED_P (insn
) = 1;
23466 insn
= GEN_INT (saved_regs
- (4 + fp_offset
));
23467 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
23468 stack_pointer_rtx
, insn
));
23469 RTX_FRAME_RELATED_P (insn
) = 1;
23473 size
= offsets
->outgoing_args
- offsets
->saved_args
;
23474 if (flag_stack_usage_info
)
23475 current_function_static_stack_size
= size
;
23477 /* If this isn't an interrupt service routine and we have a frame, then do
23478 stack checking. We use IP as the first scratch register, except for the
23479 non-APCS nested functions if LR or r3 are available (see clobber_ip). */
23480 if (!IS_INTERRUPT (func_type
)
23481 && (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
23482 || flag_stack_clash_protection
))
23484 unsigned int regno
;
23486 if (!IS_NESTED (func_type
) || clobber_ip
)
23488 else if (df_regs_ever_live_p (LR_REGNUM
))
23493 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
23495 if (size
> PROBE_INTERVAL
&& size
> get_stack_check_protect ())
23496 arm_emit_probe_stack_range (get_stack_check_protect (),
23497 size
- get_stack_check_protect (),
23498 regno
, live_regs_mask
);
23501 arm_emit_probe_stack_range (get_stack_check_protect (), size
,
23502 regno
, live_regs_mask
);
23505 /* Recover the static chain register. */
23508 if (!arm_r3_live_at_start_p () || saved_pretend_args
)
23509 insn
= gen_rtx_REG (SImode
, 3);
23512 insn
= plus_constant (Pmode
, hard_frame_pointer_rtx
, 4);
23513 insn
= gen_frame_mem (SImode
, insn
);
23515 emit_set_insn (ip_rtx
, insn
);
23516 emit_insn (gen_force_register_use (ip_rtx
));
23519 if (offsets
->outgoing_args
!= offsets
->saved_args
+ saved_regs
)
23521 /* This add can produce multiple insns for a large constant, so we
23522 need to get tricky. */
23523 rtx_insn
*last
= get_last_insn ();
23525 amount
= GEN_INT (offsets
->saved_args
+ saved_regs
23526 - offsets
->outgoing_args
);
23528 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
23532 last
= last
? NEXT_INSN (last
) : get_insns ();
23533 RTX_FRAME_RELATED_P (last
) = 1;
23535 while (last
!= insn
);
23537 /* If the frame pointer is needed, emit a special barrier that
23538 will prevent the scheduler from moving stores to the frame
23539 before the stack adjustment. */
23540 if (frame_pointer_needed
)
23541 emit_insn (gen_stack_tie (stack_pointer_rtx
,
23542 hard_frame_pointer_rtx
));
23546 if (frame_pointer_needed
&& TARGET_THUMB2
)
23547 thumb_set_frame_pointer (offsets
);
23549 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
23551 unsigned long mask
;
23553 mask
= live_regs_mask
;
23554 mask
&= THUMB2_WORK_REGS
;
23555 if (!IS_NESTED (func_type
))
23556 mask
|= (1 << IP_REGNUM
);
23557 arm_load_pic_register (mask
, NULL_RTX
);
23560 /* If we are profiling, make sure no instructions are scheduled before
23561 the call to mcount. Similarly if the user has requested no
23562 scheduling in the prolog. Similarly if we want non-call exceptions
23563 using the EABI unwinder, to prevent faulting instructions from being
23564 swapped with a stack adjustment. */
23565 if (crtl
->profile
|| !TARGET_SCHED_PROLOG
23566 || (arm_except_unwind_info (&global_options
) == UI_TARGET
23567 && cfun
->can_throw_non_call_exceptions
))
23568 emit_insn (gen_blockage ());
23570 /* If the link register is being kept alive, with the return address in it,
23571 then make sure that it does not get reused by the ce2 pass. */
23572 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
23573 cfun
->machine
->lr_save_eliminated
= 1;
23576 /* Print condition code to STREAM. Helper function for arm_print_operand. */
23578 arm_print_condition (FILE *stream
)
23580 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
23582 /* Branch conversion is not implemented for Thumb-2. */
23585 output_operand_lossage ("predicated Thumb instruction");
23588 if (current_insn_predicate
!= NULL
)
23590 output_operand_lossage
23591 ("predicated instruction in conditional sequence");
23595 fputs (arm_condition_codes
[arm_current_cc
], stream
);
23597 else if (current_insn_predicate
)
23599 enum arm_cond_code code
;
23603 output_operand_lossage ("predicated Thumb instruction");
23607 code
= get_arm_condition_code (current_insn_predicate
);
23608 fputs (arm_condition_codes
[code
], stream
);
23613 /* Globally reserved letters: acln
23614 Puncutation letters currently used: @_|?().!#
23615 Lower case letters currently used: bcdefhimpqtvwxyz
23616 Upper case letters currently used: ABCDEFGHIJKLMNOPQRSTU
23617 Letters previously used, but now deprecated/obsolete: sVWXYZ.
23619 Note that the global reservation for 'c' is only for CONSTANT_ADDRESS_P.
23621 If CODE is 'd', then the X is a condition operand and the instruction
23622 should only be executed if the condition is true.
23623 if CODE is 'D', then the X is a condition operand and the instruction
23624 should only be executed if the condition is false: however, if the mode
23625 of the comparison is CCFPEmode, then always execute the instruction -- we
23626 do this because in these circumstances !GE does not necessarily imply LT;
23627 in these cases the instruction pattern will take care to make sure that
23628 an instruction containing %d will follow, thereby undoing the effects of
23629 doing this instruction unconditionally.
23630 If CODE is 'N' then X is a floating point operand that must be negated
23632 If CODE is 'B' then output a bitwise inverted value of X (a const int).
23633 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
23635 arm_print_operand (FILE *stream
, rtx x
, int code
)
23640 fputs (ASM_COMMENT_START
, stream
);
23644 fputs (user_label_prefix
, stream
);
23648 fputs (REGISTER_PREFIX
, stream
);
23652 arm_print_condition (stream
);
23656 /* The current condition code for a condition code setting instruction.
23657 Preceded by 's' in unified syntax, otherwise followed by 's'. */
23658 fputc('s', stream
);
23659 arm_print_condition (stream
);
23663 /* If the instruction is conditionally executed then print
23664 the current condition code, otherwise print 's'. */
23665 gcc_assert (TARGET_THUMB2
);
23666 if (current_insn_predicate
)
23667 arm_print_condition (stream
);
23669 fputc('s', stream
);
23672 /* %# is a "break" sequence. It doesn't output anything, but is used to
23673 separate e.g. operand numbers from following text, if that text consists
23674 of further digits which we don't want to be part of the operand
23682 r
= real_value_negate (CONST_DOUBLE_REAL_VALUE (x
));
23683 fprintf (stream
, "%s", fp_const_from_val (&r
));
23687 /* An integer or symbol address without a preceding # sign. */
23689 switch (GET_CODE (x
))
23692 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
23696 output_addr_const (stream
, x
);
23700 if (GET_CODE (XEXP (x
, 0)) == PLUS
23701 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)
23703 output_addr_const (stream
, x
);
23706 /* Fall through. */
23709 output_operand_lossage ("Unsupported operand for code '%c'", code
);
23713 /* An integer that we want to print in HEX. */
23715 switch (GET_CODE (x
))
23718 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
23722 output_operand_lossage ("Unsupported operand for code '%c'", code
);
23727 if (CONST_INT_P (x
))
23730 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
23731 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
23735 putc ('~', stream
);
23736 output_addr_const (stream
, x
);
23741 /* Print the log2 of a CONST_INT. */
23745 if (!CONST_INT_P (x
)
23746 || (val
= exact_log2 (INTVAL (x
) & 0xffffffff)) < 0)
23747 output_operand_lossage ("Unsupported operand for code '%c'", code
);
23749 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
23754 /* The low 16 bits of an immediate constant. */
23755 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, INTVAL(x
) & 0xffff);
23759 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
23763 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
23771 shift
= shift_op (x
, &val
);
23775 fprintf (stream
, ", %s ", shift
);
23777 arm_print_operand (stream
, XEXP (x
, 1), 0);
23779 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, val
);
23784 /* An explanation of the 'Q', 'R' and 'H' register operands:
23786 In a pair of registers containing a DI or DF value the 'Q'
23787 operand returns the register number of the register containing
23788 the least significant part of the value. The 'R' operand returns
23789 the register number of the register containing the most
23790 significant part of the value.
23792 The 'H' operand returns the higher of the two register numbers.
23793 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
23794 same as the 'Q' operand, since the most significant part of the
23795 value is held in the lower number register. The reverse is true
23796 on systems where WORDS_BIG_ENDIAN is false.
23798 The purpose of these operands is to distinguish between cases
23799 where the endian-ness of the values is important (for example
23800 when they are added together), and cases where the endian-ness
23801 is irrelevant, but the order of register operations is important.
23802 For example when loading a value from memory into a register
23803 pair, the endian-ness does not matter. Provided that the value
23804 from the lower memory address is put into the lower numbered
23805 register, and the value from the higher address is put into the
23806 higher numbered register, the load will work regardless of whether
23807 the value being loaded is big-wordian or little-wordian. The
23808 order of the two register loads can matter however, if the address
23809 of the memory location is actually held in one of the registers
23810 being overwritten by the load.
23812 The 'Q' and 'R' constraints are also available for 64-bit
23815 if (CONST_INT_P (x
) || CONST_DOUBLE_P (x
))
23817 rtx part
= gen_lowpart (SImode
, x
);
23818 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, INTVAL (part
));
23822 if (!REG_P (x
) || REGNO (x
) > LAST_ARM_REGNUM
)
23824 output_operand_lossage ("invalid operand for code '%c'", code
);
23828 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
23832 if (CONST_INT_P (x
) || CONST_DOUBLE_P (x
))
23834 machine_mode mode
= GET_MODE (x
);
23837 if (mode
== VOIDmode
)
23839 part
= gen_highpart_mode (SImode
, mode
, x
);
23840 fprintf (stream
, "#" HOST_WIDE_INT_PRINT_DEC
, INTVAL (part
));
23844 if (!REG_P (x
) || REGNO (x
) > LAST_ARM_REGNUM
)
23846 output_operand_lossage ("invalid operand for code '%c'", code
);
23850 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
23854 if (!REG_P (x
) || REGNO (x
) > LAST_ARM_REGNUM
)
23856 output_operand_lossage ("invalid operand for code '%c'", code
);
23860 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
23864 if (!REG_P (x
) || REGNO (x
) > LAST_ARM_REGNUM
)
23866 output_operand_lossage ("invalid operand for code '%c'", code
);
23870 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 3 : 2));
23874 if (!REG_P (x
) || REGNO (x
) > LAST_ARM_REGNUM
)
23876 output_operand_lossage ("invalid operand for code '%c'", code
);
23880 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 2 : 3));
23884 asm_fprintf (stream
, "%r",
23885 REG_P (XEXP (x
, 0))
23886 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
23890 asm_fprintf (stream
, "{%r-%r}",
23892 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
23895 /* Like 'M', but writing doubleword vector registers, for use by Neon
23899 int regno
= (REGNO (x
) - FIRST_VFP_REGNUM
) / 2;
23900 int numregs
= ARM_NUM_REGS (GET_MODE (x
)) / 2;
23902 asm_fprintf (stream
, "{d%d}", regno
);
23904 asm_fprintf (stream
, "{d%d-d%d}", regno
, regno
+ numregs
- 1);
23909 /* CONST_TRUE_RTX means always -- that's the default. */
23910 if (x
== const_true_rtx
)
23913 if (!COMPARISON_P (x
))
23915 output_operand_lossage ("invalid operand for code '%c'", code
);
23919 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
23924 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
23925 want to do that. */
23926 if (x
== const_true_rtx
)
23928 output_operand_lossage ("instruction never executed");
23931 if (!COMPARISON_P (x
))
23933 output_operand_lossage ("invalid operand for code '%c'", code
);
23937 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
23938 (get_arm_condition_code (x
))],
23948 /* Former Maverick support, removed after GCC-4.7. */
23949 output_operand_lossage ("obsolete Maverick format code '%c'", code
);
23954 || REGNO (x
) < FIRST_IWMMXT_GR_REGNUM
23955 || REGNO (x
) > LAST_IWMMXT_GR_REGNUM
)
23956 /* Bad value for wCG register number. */
23958 output_operand_lossage ("invalid operand for code '%c'", code
);
23963 fprintf (stream
, "%d", REGNO (x
) - FIRST_IWMMXT_GR_REGNUM
);
23966 /* Print an iWMMXt control register name. */
23968 if (!CONST_INT_P (x
)
23970 || INTVAL (x
) >= 16)
23971 /* Bad value for wC register number. */
23973 output_operand_lossage ("invalid operand for code '%c'", code
);
23979 static const char * wc_reg_names
[16] =
23981 "wCID", "wCon", "wCSSF", "wCASF",
23982 "wC4", "wC5", "wC6", "wC7",
23983 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
23984 "wC12", "wC13", "wC14", "wC15"
23987 fputs (wc_reg_names
[INTVAL (x
)], stream
);
23991 /* Print the high single-precision register of a VFP double-precision
23995 machine_mode mode
= GET_MODE (x
);
23998 if (GET_MODE_SIZE (mode
) != 8 || !REG_P (x
))
24000 output_operand_lossage ("invalid operand for code '%c'", code
);
24005 if (!VFP_REGNO_OK_FOR_DOUBLE (regno
))
24007 output_operand_lossage ("invalid operand for code '%c'", code
);
24011 fprintf (stream
, "s%d", regno
- FIRST_VFP_REGNUM
+ 1);
24015 /* Print a VFP/Neon double precision or quad precision register name. */
24019 machine_mode mode
= GET_MODE (x
);
24020 int is_quad
= (code
== 'q');
24023 if (GET_MODE_SIZE (mode
) != (is_quad
? 16 : 8))
24025 output_operand_lossage ("invalid operand for code '%c'", code
);
24030 || !IS_VFP_REGNUM (REGNO (x
)))
24032 output_operand_lossage ("invalid operand for code '%c'", code
);
24037 if ((is_quad
&& !NEON_REGNO_OK_FOR_QUAD (regno
))
24038 || (!is_quad
&& !VFP_REGNO_OK_FOR_DOUBLE (regno
)))
24040 output_operand_lossage ("invalid operand for code '%c'", code
);
24044 fprintf (stream
, "%c%d", is_quad
? 'q' : 'd',
24045 (regno
- FIRST_VFP_REGNUM
) >> (is_quad
? 2 : 1));
24049 /* These two codes print the low/high doubleword register of a Neon quad
24050 register, respectively. For pair-structure types, can also print
24051 low/high quadword registers. */
24055 machine_mode mode
= GET_MODE (x
);
24058 if ((GET_MODE_SIZE (mode
) != 16
24059 && GET_MODE_SIZE (mode
) != 32) || !REG_P (x
))
24061 output_operand_lossage ("invalid operand for code '%c'", code
);
24066 if (!NEON_REGNO_OK_FOR_QUAD (regno
))
24068 output_operand_lossage ("invalid operand for code '%c'", code
);
24072 if (GET_MODE_SIZE (mode
) == 16)
24073 fprintf (stream
, "d%d", ((regno
- FIRST_VFP_REGNUM
) >> 1)
24074 + (code
== 'f' ? 1 : 0));
24076 fprintf (stream
, "q%d", ((regno
- FIRST_VFP_REGNUM
) >> 2)
24077 + (code
== 'f' ? 1 : 0));
24081 /* Print a VFPv3 floating-point constant, represented as an integer
24085 int index
= vfp3_const_double_index (x
);
24086 gcc_assert (index
!= -1);
24087 fprintf (stream
, "%d", index
);
24091 /* Print bits representing opcode features for Neon.
24093 Bit 0 is 1 for signed, 0 for unsigned. Floats count as signed
24094 and polynomials as unsigned.
24096 Bit 1 is 1 for floats and polynomials, 0 for ordinary integers.
24098 Bit 2 is 1 for rounding functions, 0 otherwise. */
24100 /* Identify the type as 's', 'u', 'p' or 'f'. */
24103 HOST_WIDE_INT bits
= INTVAL (x
);
24104 fputc ("uspf"[bits
& 3], stream
);
24108 /* Likewise, but signed and unsigned integers are both 'i'. */
24111 HOST_WIDE_INT bits
= INTVAL (x
);
24112 fputc ("iipf"[bits
& 3], stream
);
24116 /* As for 'T', but emit 'u' instead of 'p'. */
24119 HOST_WIDE_INT bits
= INTVAL (x
);
24120 fputc ("usuf"[bits
& 3], stream
);
24124 /* Bit 2: rounding (vs none). */
24127 HOST_WIDE_INT bits
= INTVAL (x
);
24128 fputs ((bits
& 4) != 0 ? "r" : "", stream
);
24132 /* Memory operand for vld1/vst1 instruction. */
24136 bool postinc
= FALSE
;
24137 rtx postinc_reg
= NULL
;
24138 unsigned align
, memsize
, align_bits
;
24140 gcc_assert (MEM_P (x
));
24141 addr
= XEXP (x
, 0);
24142 if (GET_CODE (addr
) == POST_INC
)
24145 addr
= XEXP (addr
, 0);
24147 if (GET_CODE (addr
) == POST_MODIFY
)
24149 postinc_reg
= XEXP( XEXP (addr
, 1), 1);
24150 addr
= XEXP (addr
, 0);
24152 asm_fprintf (stream
, "[%r", REGNO (addr
));
24154 /* We know the alignment of this access, so we can emit a hint in the
24155 instruction (for some alignments) as an aid to the memory subsystem
24157 align
= MEM_ALIGN (x
) >> 3;
24158 memsize
= MEM_SIZE (x
);
24160 /* Only certain alignment specifiers are supported by the hardware. */
24161 if (memsize
== 32 && (align
% 32) == 0)
24163 else if ((memsize
== 16 || memsize
== 32) && (align
% 16) == 0)
24165 else if (memsize
>= 8 && (align
% 8) == 0)
24170 if (align_bits
!= 0)
24171 asm_fprintf (stream
, ":%d", align_bits
);
24173 asm_fprintf (stream
, "]");
24176 fputs("!", stream
);
24178 asm_fprintf (stream
, ", %r", REGNO (postinc_reg
));
24182 /* To print the memory operand with "Ux" or "Uj" constraint. Based on the
24183 rtx_code the memory operands output looks like following.
24185 2. [Rn, #+/-<imm>]!
24191 rtx postinc_reg
= NULL
;
24192 unsigned inc_val
= 0;
24193 enum rtx_code code
;
24195 gcc_assert (MEM_P (x
));
24196 addr
= XEXP (x
, 0);
24197 code
= GET_CODE (addr
);
24198 if (code
== POST_INC
|| code
== POST_DEC
|| code
== PRE_INC
24199 || code
== PRE_DEC
)
24201 asm_fprintf (stream
, "[%r", REGNO (XEXP (addr
, 0)));
24202 inc_val
= GET_MODE_SIZE (GET_MODE (x
));
24203 if (code
== POST_INC
|| code
== POST_DEC
)
24204 asm_fprintf (stream
, "], #%s%d",(code
== POST_INC
)
24205 ? "": "-", inc_val
);
24207 asm_fprintf (stream
, ", #%s%d]!",(code
== PRE_INC
)
24208 ? "": "-", inc_val
);
24210 else if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
24212 asm_fprintf (stream
, "[%r", REGNO (XEXP (addr
, 0)));
24213 postinc_reg
= XEXP ( XEXP (x
, 1), 1);
24214 if (postinc_reg
&& CONST_INT_P (postinc_reg
))
24216 if (code
== POST_MODIFY
)
24217 asm_fprintf (stream
, "], #%wd",INTVAL (postinc_reg
));
24219 asm_fprintf (stream
, ", #%wd]!",INTVAL (postinc_reg
));
24222 else if (code
== PLUS
)
24224 rtx base
= XEXP (addr
, 0);
24225 rtx index
= XEXP (addr
, 1);
24227 gcc_assert (REG_P (base
) && CONST_INT_P (index
));
24229 HOST_WIDE_INT offset
= INTVAL (index
);
24230 asm_fprintf (stream
, "[%r, #%wd]", REGNO (base
), offset
);
24234 gcc_assert (REG_P (addr
));
24235 asm_fprintf (stream
, "[%r]",REGNO (addr
));
24244 gcc_assert (MEM_P (x
));
24245 addr
= XEXP (x
, 0);
24246 gcc_assert (REG_P (addr
));
24247 asm_fprintf (stream
, "[%r]", REGNO (addr
));
24251 /* Translate an S register number into a D register number and element index. */
24254 machine_mode mode
= GET_MODE (x
);
24257 if (GET_MODE_SIZE (mode
) != 4 || !REG_P (x
))
24259 output_operand_lossage ("invalid operand for code '%c'", code
);
24264 if (!VFP_REGNO_OK_FOR_SINGLE (regno
))
24266 output_operand_lossage ("invalid operand for code '%c'", code
);
24270 regno
= regno
- FIRST_VFP_REGNUM
;
24271 fprintf (stream
, "d%d[%d]", regno
/ 2, regno
% 2);
24276 gcc_assert (CONST_DOUBLE_P (x
));
24278 result
= vfp3_const_double_for_fract_bits (x
);
24280 result
= vfp3_const_double_for_bits (x
);
24281 fprintf (stream
, "#%d", result
);
24284 /* Register specifier for vld1.16/vst1.16. Translate the S register
24285 number into a D register number and element index. */
24288 machine_mode mode
= GET_MODE (x
);
24291 if (GET_MODE_SIZE (mode
) != 2 || !REG_P (x
))
24293 output_operand_lossage ("invalid operand for code '%c'", code
);
24298 if (!VFP_REGNO_OK_FOR_SINGLE (regno
))
24300 output_operand_lossage ("invalid operand for code '%c'", code
);
24304 regno
= regno
- FIRST_VFP_REGNUM
;
24305 fprintf (stream
, "d%d[%d]", regno
/2, ((regno
% 2) ? 2 : 0));
24312 output_operand_lossage ("missing operand");
24316 switch (GET_CODE (x
))
24319 asm_fprintf (stream
, "%r", REGNO (x
));
24323 output_address (GET_MODE (x
), XEXP (x
, 0));
24329 real_to_decimal (fpstr
, CONST_DOUBLE_REAL_VALUE (x
),
24330 sizeof (fpstr
), 0, 1);
24331 fprintf (stream
, "#%s", fpstr
);
24336 gcc_assert (GET_CODE (x
) != NEG
);
24337 fputc ('#', stream
);
24338 if (GET_CODE (x
) == HIGH
)
24340 fputs (":lower16:", stream
);
24344 output_addr_const (stream
, x
);
24350 /* Target hook for printing a memory address. */
24352 arm_print_operand_address (FILE *stream
, machine_mode mode
, rtx x
)
24356 int is_minus
= GET_CODE (x
) == MINUS
;
24359 asm_fprintf (stream
, "[%r]", REGNO (x
));
24360 else if (GET_CODE (x
) == PLUS
|| is_minus
)
24362 rtx base
= XEXP (x
, 0);
24363 rtx index
= XEXP (x
, 1);
24364 HOST_WIDE_INT offset
= 0;
24366 || (REG_P (index
) && REGNO (index
) == SP_REGNUM
))
24368 /* Ensure that BASE is a register. */
24369 /* (one of them must be). */
24370 /* Also ensure the SP is not used as in index register. */
24371 std::swap (base
, index
);
24373 switch (GET_CODE (index
))
24376 offset
= INTVAL (index
);
24379 asm_fprintf (stream
, "[%r, #%wd]",
24380 REGNO (base
), offset
);
24384 asm_fprintf (stream
, "[%r, %s%r]",
24385 REGNO (base
), is_minus
? "-" : "",
24395 asm_fprintf (stream
, "[%r, %s%r",
24396 REGNO (base
), is_minus
? "-" : "",
24397 REGNO (XEXP (index
, 0)));
24398 arm_print_operand (stream
, index
, 'S');
24399 fputs ("]", stream
);
24404 gcc_unreachable ();
24407 else if (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == POST_INC
24408 || GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_DEC
)
24410 gcc_assert (REG_P (XEXP (x
, 0)));
24412 if (GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == PRE_INC
)
24413 asm_fprintf (stream
, "[%r, #%s%d]!",
24414 REGNO (XEXP (x
, 0)),
24415 GET_CODE (x
) == PRE_DEC
? "-" : "",
24416 GET_MODE_SIZE (mode
));
24417 else if (TARGET_HAVE_MVE
&& (mode
== OImode
|| mode
== XImode
))
24418 asm_fprintf (stream
, "[%r]!", REGNO (XEXP (x
,0)));
24420 asm_fprintf (stream
, "[%r], #%s%d", REGNO (XEXP (x
, 0)),
24421 GET_CODE (x
) == POST_DEC
? "-" : "",
24422 GET_MODE_SIZE (mode
));
24424 else if (GET_CODE (x
) == PRE_MODIFY
)
24426 asm_fprintf (stream
, "[%r, ", REGNO (XEXP (x
, 0)));
24427 if (CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
24428 asm_fprintf (stream
, "#%wd]!",
24429 INTVAL (XEXP (XEXP (x
, 1), 1)));
24431 asm_fprintf (stream
, "%r]!",
24432 REGNO (XEXP (XEXP (x
, 1), 1)));
24434 else if (GET_CODE (x
) == POST_MODIFY
)
24436 asm_fprintf (stream
, "[%r], ", REGNO (XEXP (x
, 0)));
24437 if (CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
24438 asm_fprintf (stream
, "#%wd",
24439 INTVAL (XEXP (XEXP (x
, 1), 1)));
24441 asm_fprintf (stream
, "%r",
24442 REGNO (XEXP (XEXP (x
, 1), 1)));
24444 else output_addr_const (stream
, x
);
24449 asm_fprintf (stream
, "[%r]", REGNO (x
));
24450 else if (GET_CODE (x
) == POST_INC
)
24451 asm_fprintf (stream
, "%r!", REGNO (XEXP (x
, 0)));
24452 else if (GET_CODE (x
) == PLUS
)
24454 gcc_assert (REG_P (XEXP (x
, 0)));
24455 if (CONST_INT_P (XEXP (x
, 1)))
24456 asm_fprintf (stream
, "[%r, #%wd]",
24457 REGNO (XEXP (x
, 0)),
24458 INTVAL (XEXP (x
, 1)));
24460 asm_fprintf (stream
, "[%r, %r]",
24461 REGNO (XEXP (x
, 0)),
24462 REGNO (XEXP (x
, 1)));
24465 output_addr_const (stream
, x
);
24469 /* Target hook for indicating whether a punctuation character for
24470 TARGET_PRINT_OPERAND is valid. */
24472 arm_print_operand_punct_valid_p (unsigned char code
)
24474 return (code
== '@' || code
== '|' || code
== '.'
24475 || code
== '(' || code
== ')' || code
== '#'
24476 || (TARGET_32BIT
&& (code
== '?'))
24477 || (TARGET_THUMB2
&& (code
== '!'))
24478 || (TARGET_THUMB
&& (code
== '_')));
24481 /* Target hook for assembling integer objects. The ARM version needs to
24482 handle word-sized values specially. */
24484 arm_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
24488 if (size
== UNITS_PER_WORD
&& aligned_p
)
24490 fputs ("\t.word\t", asm_out_file
);
24491 output_addr_const (asm_out_file
, x
);
24493 /* Mark symbols as position independent. We only do this in the
24494 .text segment, not in the .data segment. */
24495 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
24496 (SYMBOL_REF_P (x
) || LABEL_REF_P (x
)))
24498 /* See legitimize_pic_address for an explanation of the
24499 TARGET_VXWORKS_RTP check. */
24500 /* References to weak symbols cannot be resolved locally:
24501 they may be overridden by a non-weak definition at link
24503 if (!arm_pic_data_is_text_relative
24504 || (SYMBOL_REF_P (x
)
24505 && (!SYMBOL_REF_LOCAL_P (x
)
24506 || (SYMBOL_REF_DECL (x
)
24507 ? DECL_WEAK (SYMBOL_REF_DECL (x
)) : 0)
24508 || (SYMBOL_REF_FUNCTION_P (x
)
24509 && !arm_fdpic_local_funcdesc_p (x
)))))
24511 if (TARGET_FDPIC
&& SYMBOL_REF_FUNCTION_P (x
))
24512 fputs ("(GOTFUNCDESC)", asm_out_file
);
24514 fputs ("(GOT)", asm_out_file
);
24518 if (TARGET_FDPIC
&& SYMBOL_REF_FUNCTION_P (x
))
24519 fputs ("(GOTOFFFUNCDESC)", asm_out_file
);
24525 || arm_is_segment_info_known (x
, &is_readonly
))
24526 fputs ("(GOTOFF)", asm_out_file
);
24528 fputs ("(GOT)", asm_out_file
);
24533 /* For FDPIC we also have to mark symbol for .data section. */
24535 && !making_const_table
24536 && SYMBOL_REF_P (x
)
24537 && SYMBOL_REF_FUNCTION_P (x
))
24538 fputs ("(FUNCDESC)", asm_out_file
);
24540 fputc ('\n', asm_out_file
);
24544 mode
= GET_MODE (x
);
24546 if (arm_vector_mode_supported_p (mode
))
24550 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
24552 units
= CONST_VECTOR_NUNITS (x
);
24553 size
= GET_MODE_UNIT_SIZE (mode
);
24555 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
24556 for (i
= 0; i
< units
; i
++)
24558 rtx elt
= CONST_VECTOR_ELT (x
, i
);
24560 (elt
, size
, i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
, 1);
24563 for (i
= 0; i
< units
; i
++)
24565 rtx elt
= CONST_VECTOR_ELT (x
, i
);
24567 (*CONST_DOUBLE_REAL_VALUE (elt
),
24568 as_a
<scalar_float_mode
> (GET_MODE_INNER (mode
)),
24569 i
== 0 ? BIGGEST_ALIGNMENT
: size
* BITS_PER_UNIT
);
24575 return default_assemble_integer (x
, size
, aligned_p
);
24579 arm_elf_asm_cdtor (rtx symbol
, int priority
, bool is_ctor
)
24583 if (!TARGET_AAPCS_BASED
)
24586 default_named_section_asm_out_constructor
24587 : default_named_section_asm_out_destructor
) (symbol
, priority
);
24591 /* Put these in the .init_array section, using a special relocation. */
24592 if (priority
!= DEFAULT_INIT_PRIORITY
)
24595 sprintf (buf
, "%s.%.5u",
24596 is_ctor
? ".init_array" : ".fini_array",
24598 s
= get_section (buf
, SECTION_WRITE
| SECTION_NOTYPE
, NULL_TREE
);
24605 switch_to_section (s
);
24606 assemble_align (POINTER_SIZE
);
24607 fputs ("\t.word\t", asm_out_file
);
24608 output_addr_const (asm_out_file
, symbol
);
24609 fputs ("(target1)\n", asm_out_file
);
24612 /* Add a function to the list of static constructors. */
24615 arm_elf_asm_constructor (rtx symbol
, int priority
)
24617 arm_elf_asm_cdtor (symbol
, priority
, /*is_ctor=*/true);
24620 /* Add a function to the list of static destructors. */
24623 arm_elf_asm_destructor (rtx symbol
, int priority
)
24625 arm_elf_asm_cdtor (symbol
, priority
, /*is_ctor=*/false);
24628 /* A finite state machine takes care of noticing whether or not instructions
24629 can be conditionally executed, and thus decrease execution time and code
24630 size by deleting branch instructions. The fsm is controlled by
24631 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
24633 /* The state of the fsm controlling condition codes are:
24634 0: normal, do nothing special
24635 1: make ASM_OUTPUT_OPCODE not output this instruction
24636 2: make ASM_OUTPUT_OPCODE not output this instruction
24637 3: make instructions conditional
24638 4: make instructions conditional
24640 State transitions (state->state by whom under condition):
24641 0 -> 1 final_prescan_insn if the `target' is a label
24642 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
24643 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
24644 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
24645 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
24646 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
24647 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
24648 (the target insn is arm_target_insn).
24650 If the jump clobbers the conditions then we use states 2 and 4.
24652 A similar thing can be done with conditional return insns.
24654 XXX In case the `target' is an unconditional branch, this conditionalising
24655 of the instructions always reduces code size, but not always execution
24656 time. But then, I want to reduce the code size to somewhere near what
24657 /bin/cc produces. */
24659 /* In addition to this, state is maintained for Thumb-2 COND_EXEC
24660 instructions. When a COND_EXEC instruction is seen the subsequent
24661 instructions are scanned so that multiple conditional instructions can be
24662 combined into a single IT block. arm_condexec_count and arm_condexec_mask
24663 specify the length and true/false mask for the IT block. These will be
24664 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
24666 /* Returns the index of the ARM condition code string in
24667 `arm_condition_codes', or ARM_NV if the comparison is invalid.
24668 COMPARISON should be an rtx like `(eq (...) (...))'. */
24671 maybe_get_arm_condition_code (rtx comparison
)
24673 machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
24674 enum arm_cond_code code
;
24675 enum rtx_code comp_code
= GET_CODE (comparison
);
24677 if (GET_MODE_CLASS (mode
) != MODE_CC
)
24678 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
24679 XEXP (comparison
, 1));
24683 case E_CC_DNEmode
: code
= ARM_NE
; goto dominance
;
24684 case E_CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
24685 case E_CC_DGEmode
: code
= ARM_GE
; goto dominance
;
24686 case E_CC_DGTmode
: code
= ARM_GT
; goto dominance
;
24687 case E_CC_DLEmode
: code
= ARM_LE
; goto dominance
;
24688 case E_CC_DLTmode
: code
= ARM_LT
; goto dominance
;
24689 case E_CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
24690 case E_CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
24691 case E_CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
24692 case E_CC_DLTUmode
: code
= ARM_CC
;
24695 if (comp_code
== EQ
)
24696 return ARM_INVERSE_CONDITION_CODE (code
);
24697 if (comp_code
== NE
)
24704 case NE
: return ARM_NE
;
24705 case EQ
: return ARM_EQ
;
24706 case GE
: return ARM_PL
;
24707 case LT
: return ARM_MI
;
24708 default: return ARM_NV
;
24714 case NE
: return ARM_NE
;
24715 case EQ
: return ARM_EQ
;
24716 default: return ARM_NV
;
24722 case NE
: return ARM_MI
;
24723 case EQ
: return ARM_PL
;
24724 default: return ARM_NV
;
24729 /* We can handle all cases except UNEQ and LTGT. */
24732 case GE
: return ARM_GE
;
24733 case GT
: return ARM_GT
;
24734 case LE
: return ARM_LS
;
24735 case LT
: return ARM_MI
;
24736 case NE
: return ARM_NE
;
24737 case EQ
: return ARM_EQ
;
24738 case ORDERED
: return ARM_VC
;
24739 case UNORDERED
: return ARM_VS
;
24740 case UNLT
: return ARM_LT
;
24741 case UNLE
: return ARM_LE
;
24742 case UNGT
: return ARM_HI
;
24743 case UNGE
: return ARM_PL
;
24744 /* UNEQ and LTGT do not have a representation. */
24745 case UNEQ
: /* Fall through. */
24746 case LTGT
: /* Fall through. */
24747 default: return ARM_NV
;
24753 case NE
: return ARM_NE
;
24754 case EQ
: return ARM_EQ
;
24755 case GE
: return ARM_LE
;
24756 case GT
: return ARM_LT
;
24757 case LE
: return ARM_GE
;
24758 case LT
: return ARM_GT
;
24759 case GEU
: return ARM_LS
;
24760 case GTU
: return ARM_CC
;
24761 case LEU
: return ARM_CS
;
24762 case LTU
: return ARM_HI
;
24763 default: return ARM_NV
;
24769 case LTU
: return ARM_CS
;
24770 case GEU
: return ARM_CC
;
24771 default: return ARM_NV
;
24777 case GE
: return ARM_GE
;
24778 case LT
: return ARM_LT
;
24779 default: return ARM_NV
;
24785 case GEU
: return ARM_CS
;
24786 case LTU
: return ARM_CC
;
24787 default: return ARM_NV
;
24793 case NE
: return ARM_VS
;
24794 case EQ
: return ARM_VC
;
24795 default: return ARM_NV
;
24801 case GEU
: return ARM_CS
;
24802 case LTU
: return ARM_CC
;
24803 default: return ARM_NV
;
24810 case NE
: return ARM_NE
;
24811 case EQ
: return ARM_EQ
;
24812 case GE
: return ARM_GE
;
24813 case GT
: return ARM_GT
;
24814 case LE
: return ARM_LE
;
24815 case LT
: return ARM_LT
;
24816 case GEU
: return ARM_CS
;
24817 case GTU
: return ARM_HI
;
24818 case LEU
: return ARM_LS
;
24819 case LTU
: return ARM_CC
;
24820 default: return ARM_NV
;
24823 default: gcc_unreachable ();
24827 /* Like maybe_get_arm_condition_code, but never return ARM_NV. */
24828 static enum arm_cond_code
24829 get_arm_condition_code (rtx comparison
)
24831 enum arm_cond_code code
= maybe_get_arm_condition_code (comparison
);
24832 gcc_assert (code
!= ARM_NV
);
24836 /* Implement TARGET_FIXED_CONDITION_CODE_REGS. We only have condition
24837 code registers when not targetting Thumb1. The VFP condition register
24838 only exists when generating hard-float code. */
24840 arm_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
24846 *p2
= TARGET_VFP_BASE
? VFPCC_REGNUM
: INVALID_REGNUM
;
24850 /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
24853 thumb2_final_prescan_insn (rtx_insn
*insn
)
24855 rtx_insn
*first_insn
= insn
;
24856 rtx body
= PATTERN (insn
);
24858 enum arm_cond_code code
;
24863 /* max_insns_skipped in the tune was already taken into account in the
24864 cost model of ifcvt pass when generating COND_EXEC insns. At this stage
24865 just emit the IT blocks as we can. It does not make sense to split
24867 max
= MAX_INSN_PER_IT_BLOCK
;
24869 /* Remove the previous insn from the count of insns to be output. */
24870 if (arm_condexec_count
)
24871 arm_condexec_count
--;
24873 /* Nothing to do if we are already inside a conditional block. */
24874 if (arm_condexec_count
)
24877 if (GET_CODE (body
) != COND_EXEC
)
24880 /* Conditional jumps are implemented directly. */
24884 predicate
= COND_EXEC_TEST (body
);
24885 arm_current_cc
= get_arm_condition_code (predicate
);
24887 n
= get_attr_ce_count (insn
);
24888 arm_condexec_count
= 1;
24889 arm_condexec_mask
= (1 << n
) - 1;
24890 arm_condexec_masklen
= n
;
24891 /* See if subsequent instructions can be combined into the same block. */
24894 insn
= next_nonnote_insn (insn
);
24896 /* Jumping into the middle of an IT block is illegal, so a label or
24897 barrier terminates the block. */
24898 if (!NONJUMP_INSN_P (insn
) && !JUMP_P (insn
))
24901 body
= PATTERN (insn
);
24902 /* USE and CLOBBER aren't really insns, so just skip them. */
24903 if (GET_CODE (body
) == USE
24904 || GET_CODE (body
) == CLOBBER
)
24907 /* ??? Recognize conditional jumps, and combine them with IT blocks. */
24908 if (GET_CODE (body
) != COND_EXEC
)
24910 /* Maximum number of conditionally executed instructions in a block. */
24911 n
= get_attr_ce_count (insn
);
24912 if (arm_condexec_masklen
+ n
> max
)
24915 predicate
= COND_EXEC_TEST (body
);
24916 code
= get_arm_condition_code (predicate
);
24917 mask
= (1 << n
) - 1;
24918 if (arm_current_cc
== code
)
24919 arm_condexec_mask
|= (mask
<< arm_condexec_masklen
);
24920 else if (arm_current_cc
!= ARM_INVERSE_CONDITION_CODE(code
))
24923 arm_condexec_count
++;
24924 arm_condexec_masklen
+= n
;
24926 /* A jump must be the last instruction in a conditional block. */
24930 /* Restore recog_data (getting the attributes of other insns can
24931 destroy this array, but final.c assumes that it remains intact
24932 across this call). */
24933 extract_constrain_insn_cached (first_insn
);
24937 arm_final_prescan_insn (rtx_insn
*insn
)
24939 /* BODY will hold the body of INSN. */
24940 rtx body
= PATTERN (insn
);
24942 /* This will be 1 if trying to repeat the trick, and things need to be
24943 reversed if it appears to fail. */
24946 /* If we start with a return insn, we only succeed if we find another one. */
24947 int seeking_return
= 0;
24948 enum rtx_code return_code
= UNKNOWN
;
24950 /* START_INSN will hold the insn from where we start looking. This is the
24951 first insn after the following code_label if REVERSE is true. */
24952 rtx_insn
*start_insn
= insn
;
24954 /* If in state 4, check if the target branch is reached, in order to
24955 change back to state 0. */
24956 if (arm_ccfsm_state
== 4)
24958 if (insn
== arm_target_insn
)
24960 arm_target_insn
= NULL
;
24961 arm_ccfsm_state
= 0;
24966 /* If in state 3, it is possible to repeat the trick, if this insn is an
24967 unconditional branch to a label, and immediately following this branch
24968 is the previous target label which is only used once, and the label this
24969 branch jumps to is not too far off. */
24970 if (arm_ccfsm_state
== 3)
24972 if (simplejump_p (insn
))
24974 start_insn
= next_nonnote_insn (start_insn
);
24975 if (BARRIER_P (start_insn
))
24977 /* XXX Isn't this always a barrier? */
24978 start_insn
= next_nonnote_insn (start_insn
);
24980 if (LABEL_P (start_insn
)
24981 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
24982 && LABEL_NUSES (start_insn
) == 1)
24987 else if (ANY_RETURN_P (body
))
24989 start_insn
= next_nonnote_insn (start_insn
);
24990 if (BARRIER_P (start_insn
))
24991 start_insn
= next_nonnote_insn (start_insn
);
24992 if (LABEL_P (start_insn
)
24993 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
24994 && LABEL_NUSES (start_insn
) == 1)
24997 seeking_return
= 1;
24998 return_code
= GET_CODE (body
);
25007 gcc_assert (!arm_ccfsm_state
|| reverse
);
25008 if (!JUMP_P (insn
))
25011 /* This jump might be paralleled with a clobber of the condition codes
25012 the jump should always come first */
25013 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
25014 body
= XVECEXP (body
, 0, 0);
25017 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
25018 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
25021 int fail
= FALSE
, succeed
= FALSE
;
25022 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
25023 int then_not_else
= TRUE
;
25024 rtx_insn
*this_insn
= start_insn
;
25027 /* Register the insn jumped to. */
25030 if (!seeking_return
)
25031 label
= XEXP (SET_SRC (body
), 0);
25033 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
25034 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
25035 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
25037 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
25038 then_not_else
= FALSE
;
25040 else if (ANY_RETURN_P (XEXP (SET_SRC (body
), 1)))
25042 seeking_return
= 1;
25043 return_code
= GET_CODE (XEXP (SET_SRC (body
), 1));
25045 else if (ANY_RETURN_P (XEXP (SET_SRC (body
), 2)))
25047 seeking_return
= 1;
25048 return_code
= GET_CODE (XEXP (SET_SRC (body
), 2));
25049 then_not_else
= FALSE
;
25052 gcc_unreachable ();
25054 /* See how many insns this branch skips, and what kind of insns. If all
25055 insns are okay, and the label or unconditional branch to the same
25056 label is not too far away, succeed. */
25057 for (insns_skipped
= 0;
25058 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
25062 this_insn
= next_nonnote_insn (this_insn
);
25066 switch (GET_CODE (this_insn
))
25069 /* Succeed if it is the target label, otherwise fail since
25070 control falls in from somewhere else. */
25071 if (this_insn
== label
)
25073 arm_ccfsm_state
= 1;
25081 /* Succeed if the following insn is the target label.
25083 If return insns are used then the last insn in a function
25084 will be a barrier. */
25085 this_insn
= next_nonnote_insn (this_insn
);
25086 if (this_insn
&& this_insn
== label
)
25088 arm_ccfsm_state
= 1;
25096 /* The AAPCS says that conditional calls should not be
25097 used since they make interworking inefficient (the
25098 linker can't transform BL<cond> into BLX). That's
25099 only a problem if the machine has BLX. */
25106 /* Succeed if the following insn is the target label, or
25107 if the following two insns are a barrier and the
25109 this_insn
= next_nonnote_insn (this_insn
);
25110 if (this_insn
&& BARRIER_P (this_insn
))
25111 this_insn
= next_nonnote_insn (this_insn
);
25113 if (this_insn
&& this_insn
== label
25114 && insns_skipped
< max_insns_skipped
)
25116 arm_ccfsm_state
= 1;
25124 /* If this is an unconditional branch to the same label, succeed.
25125 If it is to another label, do nothing. If it is conditional,
25127 /* XXX Probably, the tests for SET and the PC are
25130 scanbody
= PATTERN (this_insn
);
25131 if (GET_CODE (scanbody
) == SET
25132 && GET_CODE (SET_DEST (scanbody
)) == PC
)
25134 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
25135 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
25137 arm_ccfsm_state
= 2;
25140 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
25143 /* Fail if a conditional return is undesirable (e.g. on a
25144 StrongARM), but still allow this if optimizing for size. */
25145 else if (GET_CODE (scanbody
) == return_code
25146 && !use_return_insn (TRUE
, NULL
)
25149 else if (GET_CODE (scanbody
) == return_code
)
25151 arm_ccfsm_state
= 2;
25154 else if (GET_CODE (scanbody
) == PARALLEL
)
25156 switch (get_attr_conds (this_insn
))
25166 fail
= TRUE
; /* Unrecognized jump (e.g. epilogue). */
25171 /* Instructions using or affecting the condition codes make it
25173 scanbody
= PATTERN (this_insn
);
25174 if (!(GET_CODE (scanbody
) == SET
25175 || GET_CODE (scanbody
) == PARALLEL
)
25176 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
25186 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
25187 arm_target_label
= CODE_LABEL_NUMBER (label
);
25190 gcc_assert (seeking_return
|| arm_ccfsm_state
== 2);
25192 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
25194 this_insn
= next_nonnote_insn (this_insn
);
25195 gcc_assert (!this_insn
25196 || (!BARRIER_P (this_insn
)
25197 && !LABEL_P (this_insn
)));
25201 /* Oh, dear! we ran off the end.. give up. */
25202 extract_constrain_insn_cached (insn
);
25203 arm_ccfsm_state
= 0;
25204 arm_target_insn
= NULL
;
25207 arm_target_insn
= this_insn
;
25210 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
25213 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
), 0));
25215 if (reverse
|| then_not_else
)
25216 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
25219 /* Restore recog_data (getting the attributes of other insns can
25220 destroy this array, but final.c assumes that it remains intact
25221 across this call. */
25222 extract_constrain_insn_cached (insn
);
25226 /* Output IT instructions. */
25228 thumb2_asm_output_opcode (FILE * stream
)
25233 if (arm_condexec_mask
)
25235 for (n
= 0; n
< arm_condexec_masklen
; n
++)
25236 buff
[n
] = (arm_condexec_mask
& (1 << n
)) ? 't' : 'e';
25238 asm_fprintf(stream
, "i%s\t%s\n\t", buff
,
25239 arm_condition_codes
[arm_current_cc
]);
25240 arm_condexec_mask
= 0;
25244 /* Implement TARGET_HARD_REGNO_NREGS. On the ARM core regs are
25245 UNITS_PER_WORD bytes wide. */
25246 static unsigned int
25247 arm_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
25250 && regno
> PC_REGNUM
25251 && regno
!= FRAME_POINTER_REGNUM
25252 && regno
!= ARG_POINTER_REGNUM
25253 && !IS_VFP_REGNUM (regno
))
25256 return ARM_NUM_REGS (mode
);
25259 /* Implement TARGET_HARD_REGNO_MODE_OK. */
25261 arm_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
25263 if (GET_MODE_CLASS (mode
) == MODE_CC
)
25264 return (regno
== CC_REGNUM
25265 || (TARGET_VFP_BASE
25266 && regno
== VFPCC_REGNUM
));
25268 if (regno
== CC_REGNUM
&& GET_MODE_CLASS (mode
) != MODE_CC
)
25271 if (IS_VPR_REGNUM (regno
))
25272 return mode
== HImode
;
25275 /* For the Thumb we only allow values bigger than SImode in
25276 registers 0 - 6, so that there is always a second low
25277 register available to hold the upper part of the value.
25278 We probably we ought to ensure that the register is the
25279 start of an even numbered register pair. */
25280 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
25282 if (TARGET_VFP_BASE
&& IS_VFP_REGNUM (regno
))
25284 if (mode
== DFmode
|| mode
== DImode
)
25285 return VFP_REGNO_OK_FOR_DOUBLE (regno
);
25287 if (mode
== HFmode
|| mode
== BFmode
|| mode
== HImode
25288 || mode
== SFmode
|| mode
== SImode
)
25289 return VFP_REGNO_OK_FOR_SINGLE (regno
);
25292 return (VALID_NEON_DREG_MODE (mode
) && VFP_REGNO_OK_FOR_DOUBLE (regno
))
25293 || (VALID_NEON_QREG_MODE (mode
)
25294 && NEON_REGNO_OK_FOR_QUAD (regno
))
25295 || (mode
== TImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 2))
25296 || (mode
== EImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 3))
25297 || (mode
== OImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 4))
25298 || (mode
== CImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 6))
25299 || (mode
== XImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 8));
25300 if (TARGET_HAVE_MVE
)
25301 return ((VALID_MVE_MODE (mode
) && NEON_REGNO_OK_FOR_QUAD (regno
))
25302 || (mode
== OImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 4))
25303 || (mode
== XImode
&& NEON_REGNO_OK_FOR_NREGS (regno
, 8)));
25308 if (TARGET_REALLY_IWMMXT
)
25310 if (IS_IWMMXT_GR_REGNUM (regno
))
25311 return mode
== SImode
;
25313 if (IS_IWMMXT_REGNUM (regno
))
25314 return VALID_IWMMXT_REG_MODE (mode
);
25317 /* We allow almost any value to be stored in the general registers.
25318 Restrict doubleword quantities to even register pairs in ARM state
25319 so that we can use ldrd. The same restriction applies for MVE
25320 in order to support Armv8.1-M Mainline instructions.
25321 Do not allow very large Neon structure opaque modes in general
25322 registers; they would use too many. */
25323 if (regno
<= LAST_ARM_REGNUM
)
25325 if (ARM_NUM_REGS (mode
) > 4)
25328 if (TARGET_THUMB2
&& !(TARGET_HAVE_MVE
|| TARGET_CDE
))
25331 return !((TARGET_LDRD
|| TARGET_CDE
)
25332 && GET_MODE_SIZE (mode
) > 4 && (regno
& 1) != 0);
25335 if (regno
== FRAME_POINTER_REGNUM
25336 || regno
== ARG_POINTER_REGNUM
)
25337 /* We only allow integers in the fake hard registers. */
25338 return GET_MODE_CLASS (mode
) == MODE_INT
;
25343 /* Implement TARGET_MODES_TIEABLE_P. */
25346 arm_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
25348 if (GET_MODE_CLASS (mode1
) == GET_MODE_CLASS (mode2
))
25351 /* We specifically want to allow elements of "structure" modes to
25352 be tieable to the structure. This more general condition allows
25353 other rarer situations too. */
25355 && (VALID_NEON_DREG_MODE (mode1
)
25356 || VALID_NEON_QREG_MODE (mode1
)
25357 || VALID_NEON_STRUCT_MODE (mode1
))
25358 && (VALID_NEON_DREG_MODE (mode2
)
25359 || VALID_NEON_QREG_MODE (mode2
)
25360 || VALID_NEON_STRUCT_MODE (mode2
)))
25361 || (TARGET_HAVE_MVE
25362 && (VALID_MVE_MODE (mode1
)
25363 || VALID_MVE_STRUCT_MODE (mode1
))
25364 && (VALID_MVE_MODE (mode2
)
25365 || VALID_MVE_STRUCT_MODE (mode2
))))
25371 /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are
25372 not used in arm mode. */
25375 arm_regno_class (int regno
)
25377 if (regno
== PC_REGNUM
)
25380 if (IS_VPR_REGNUM (regno
))
25385 if (regno
== STACK_POINTER_REGNUM
)
25387 if (regno
== CC_REGNUM
)
25394 if (TARGET_THUMB2
&& regno
< 8)
25397 if ( regno
<= LAST_ARM_REGNUM
25398 || regno
== FRAME_POINTER_REGNUM
25399 || regno
== ARG_POINTER_REGNUM
)
25400 return TARGET_THUMB2
? HI_REGS
: GENERAL_REGS
;
25402 if (regno
== CC_REGNUM
|| regno
== VFPCC_REGNUM
)
25403 return TARGET_THUMB2
? CC_REG
: NO_REGS
;
25405 if (IS_VFP_REGNUM (regno
))
25407 if (regno
<= D7_VFP_REGNUM
)
25408 return VFP_D0_D7_REGS
;
25409 else if (regno
<= LAST_LO_VFP_REGNUM
)
25410 return VFP_LO_REGS
;
25412 return VFP_HI_REGS
;
25415 if (IS_IWMMXT_REGNUM (regno
))
25416 return IWMMXT_REGS
;
25418 if (IS_IWMMXT_GR_REGNUM (regno
))
25419 return IWMMXT_GR_REGS
;
25424 /* Handle a special case when computing the offset
25425 of an argument from the frame pointer. */
25427 arm_debugger_arg_offset (int value
, rtx addr
)
25431 /* We are only interested if dbxout_parms() failed to compute the offset. */
25435 /* We can only cope with the case where the address is held in a register. */
25439 /* If we are using the frame pointer to point at the argument, then
25440 an offset of 0 is correct. */
25441 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
25444 /* If we are using the stack pointer to point at the
25445 argument, then an offset of 0 is correct. */
25446 /* ??? Check this is consistent with thumb2 frame layout. */
25447 if ((TARGET_THUMB
|| !frame_pointer_needed
)
25448 && REGNO (addr
) == SP_REGNUM
)
25451 /* Oh dear. The argument is pointed to by a register rather
25452 than being held in a register, or being stored at a known
25453 offset from the frame pointer. Since GDB only understands
25454 those two kinds of argument we must translate the address
25455 held in the register into an offset from the frame pointer.
25456 We do this by searching through the insns for the function
25457 looking to see where this register gets its value. If the
25458 register is initialized from the frame pointer plus an offset
25459 then we are in luck and we can continue, otherwise we give up.
25461 This code is exercised by producing debugging information
25462 for a function with arguments like this:
25464 double func (double a, double b, int c, double d) {return d;}
25466 Without this code the stab for parameter 'd' will be set to
25467 an offset of 0 from the frame pointer, rather than 8. */
25469 /* The if() statement says:
25471 If the insn is a normal instruction
25472 and if the insn is setting the value in a register
25473 and if the register being set is the register holding the address of the argument
25474 and if the address is computing by an addition
25475 that involves adding to a register
25476 which is the frame pointer
25481 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
25483 if ( NONJUMP_INSN_P (insn
)
25484 && GET_CODE (PATTERN (insn
)) == SET
25485 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
25486 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
25487 && REG_P (XEXP (XEXP (PATTERN (insn
), 1), 0))
25488 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
25489 && CONST_INT_P (XEXP (XEXP (PATTERN (insn
), 1), 1))
25492 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
25501 warning (0, "unable to compute real location of stacked parameter");
25502 value
= 8; /* XXX magic hack */
25508 /* Implement TARGET_PROMOTED_TYPE. */
25511 arm_promoted_type (const_tree t
)
25513 if (SCALAR_FLOAT_TYPE_P (t
)
25514 && TYPE_PRECISION (t
) == 16
25515 && TYPE_MAIN_VARIANT (t
) == arm_fp16_type_node
)
25516 return float_type_node
;
25520 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P.
25521 This simply adds HFmode as a supported mode; even though we don't
25522 implement arithmetic on this type directly, it's supported by
25523 optabs conversions, much the way the double-word arithmetic is
25524 special-cased in the default hook. */
25527 arm_scalar_mode_supported_p (scalar_mode mode
)
25529 if (mode
== HFmode
)
25530 return (arm_fp16_format
!= ARM_FP16_FORMAT_NONE
);
25531 else if (ALL_FIXED_POINT_MODE_P (mode
))
25534 return default_scalar_mode_supported_p (mode
);
25537 /* Set the value of FLT_EVAL_METHOD.
25538 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
25540 0: evaluate all operations and constants, whose semantic type has at
25541 most the range and precision of type float, to the range and
25542 precision of float; evaluate all other operations and constants to
25543 the range and precision of the semantic type;
25545 N, where _FloatN is a supported interchange floating type
25546 evaluate all operations and constants, whose semantic type has at
25547 most the range and precision of _FloatN type, to the range and
25548 precision of the _FloatN type; evaluate all other operations and
25549 constants to the range and precision of the semantic type;
25551 If we have the ARMv8.2-A extensions then we support _Float16 in native
25552 precision, so we should set this to 16. Otherwise, we support the type,
25553 but want to evaluate expressions in float precision, so set this to
25556 static enum flt_eval_method
25557 arm_excess_precision (enum excess_precision_type type
)
25561 case EXCESS_PRECISION_TYPE_FAST
:
25562 case EXCESS_PRECISION_TYPE_STANDARD
:
25563 /* We can calculate either in 16-bit range and precision or
25564 32-bit range and precision. Make that decision based on whether
25565 we have native support for the ARMv8.2-A 16-bit floating-point
25566 instructions or not. */
25567 return (TARGET_VFP_FP16INST
25568 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
25569 : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT
);
25570 case EXCESS_PRECISION_TYPE_IMPLICIT
:
25571 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
;
25573 gcc_unreachable ();
25575 return FLT_EVAL_METHOD_UNPREDICTABLE
;
25579 /* Implement TARGET_FLOATN_MODE. Make very sure that we don't provide
25580 _Float16 if we are using anything other than ieee format for 16-bit
25581 floating point. Otherwise, punt to the default implementation. */
25582 static opt_scalar_float_mode
25583 arm_floatn_mode (int n
, bool extended
)
25585 if (!extended
&& n
== 16)
25587 if (arm_fp16_format
== ARM_FP16_FORMAT_IEEE
)
25589 return opt_scalar_float_mode ();
25592 return default_floatn_mode (n
, extended
);
25596 /* Set up OPERANDS for a register copy from SRC to DEST, taking care
25597 not to early-clobber SRC registers in the process.
25599 We assume that the operands described by SRC and DEST represent a
25600 decomposed copy of OPERANDS[1] into OPERANDS[0]. COUNT is the
25601 number of components into which the copy has been decomposed. */
25603 neon_disambiguate_copy (rtx
*operands
, rtx
*dest
, rtx
*src
, unsigned int count
)
25607 if (!reg_overlap_mentioned_p (operands
[0], operands
[1])
25608 || REGNO (operands
[0]) < REGNO (operands
[1]))
25610 for (i
= 0; i
< count
; i
++)
25612 operands
[2 * i
] = dest
[i
];
25613 operands
[2 * i
+ 1] = src
[i
];
25618 for (i
= 0; i
< count
; i
++)
25620 operands
[2 * i
] = dest
[count
- i
- 1];
25621 operands
[2 * i
+ 1] = src
[count
- i
- 1];
25626 /* Split operands into moves from op[1] + op[2] into op[0]. */
25629 neon_split_vcombine (rtx operands
[3])
25631 unsigned int dest
= REGNO (operands
[0]);
25632 unsigned int src1
= REGNO (operands
[1]);
25633 unsigned int src2
= REGNO (operands
[2]);
25634 machine_mode halfmode
= GET_MODE (operands
[1]);
25635 unsigned int halfregs
= REG_NREGS (operands
[1]);
25636 rtx destlo
, desthi
;
25638 if (src1
== dest
&& src2
== dest
+ halfregs
)
25640 /* No-op move. Can't split to nothing; emit something. */
25641 emit_note (NOTE_INSN_DELETED
);
25645 /* Preserve register attributes for variable tracking. */
25646 destlo
= gen_rtx_REG_offset (operands
[0], halfmode
, dest
, 0);
25647 desthi
= gen_rtx_REG_offset (operands
[0], halfmode
, dest
+ halfregs
,
25648 GET_MODE_SIZE (halfmode
));
25650 /* Special case of reversed high/low parts. Use VSWP. */
25651 if (src2
== dest
&& src1
== dest
+ halfregs
)
25653 rtx x
= gen_rtx_SET (destlo
, operands
[1]);
25654 rtx y
= gen_rtx_SET (desthi
, operands
[2]);
25655 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x
, y
)));
25659 if (!reg_overlap_mentioned_p (operands
[2], destlo
))
25661 /* Try to avoid unnecessary moves if part of the result
25662 is in the right place already. */
25664 emit_move_insn (destlo
, operands
[1]);
25665 if (src2
!= dest
+ halfregs
)
25666 emit_move_insn (desthi
, operands
[2]);
25670 if (src2
!= dest
+ halfregs
)
25671 emit_move_insn (desthi
, operands
[2]);
25673 emit_move_insn (destlo
, operands
[1]);
25677 /* Return the number (counting from 0) of
25678 the least significant set bit in MASK. */
25681 number_of_first_bit_set (unsigned mask
)
25683 return ctz_hwi (mask
);
25686 /* Like emit_multi_reg_push, but allowing for a different set of
25687 registers to be described as saved. MASK is the set of registers
25688 to be saved; REAL_REGS is the set of registers to be described as
25689 saved. If REAL_REGS is 0, only describe the stack adjustment. */
25692 thumb1_emit_multi_reg_push (unsigned long mask
, unsigned long real_regs
)
25694 unsigned long regno
;
25695 rtx par
[10], tmp
, reg
;
25699 /* Build the parallel of the registers actually being stored. */
25700 for (i
= 0; mask
; ++i
, mask
&= mask
- 1)
25702 regno
= ctz_hwi (mask
);
25703 reg
= gen_rtx_REG (SImode
, regno
);
25706 tmp
= gen_rtx_UNSPEC (BLKmode
, gen_rtvec (1, reg
), UNSPEC_PUSH_MULT
);
25708 tmp
= gen_rtx_USE (VOIDmode
, reg
);
25713 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, -4 * i
);
25714 tmp
= gen_rtx_PRE_MODIFY (Pmode
, stack_pointer_rtx
, tmp
);
25715 tmp
= gen_frame_mem (BLKmode
, tmp
);
25716 tmp
= gen_rtx_SET (tmp
, par
[0]);
25719 tmp
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (i
, par
));
25720 insn
= emit_insn (tmp
);
25722 /* Always build the stack adjustment note for unwind info. */
25723 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, -4 * i
);
25724 tmp
= gen_rtx_SET (stack_pointer_rtx
, tmp
);
25727 /* Build the parallel of the registers recorded as saved for unwind. */
25728 for (j
= 0; real_regs
; ++j
, real_regs
&= real_regs
- 1)
25730 regno
= ctz_hwi (real_regs
);
25731 reg
= gen_rtx_REG (SImode
, regno
);
25733 tmp
= plus_constant (Pmode
, stack_pointer_rtx
, j
* 4);
25734 tmp
= gen_frame_mem (SImode
, tmp
);
25735 tmp
= gen_rtx_SET (tmp
, reg
);
25736 RTX_FRAME_RELATED_P (tmp
) = 1;
25744 RTX_FRAME_RELATED_P (par
[0]) = 1;
25745 tmp
= gen_rtx_SEQUENCE (VOIDmode
, gen_rtvec_v (j
+ 1, par
));
25748 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, tmp
);
25753 /* Emit code to push or pop registers to or from the stack. F is the
25754 assembly file. MASK is the registers to pop. */
25756 thumb_pop (FILE *f
, unsigned long mask
)
25759 int lo_mask
= mask
& 0xFF;
25763 if (lo_mask
== 0 && (mask
& (1 << PC_REGNUM
)))
25765 /* Special case. Do not generate a POP PC statement here, do it in
25767 thumb_exit (f
, -1);
25771 fprintf (f
, "\tpop\t{");
25773 /* Look at the low registers first. */
25774 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
25778 asm_fprintf (f
, "%r", regno
);
25780 if ((lo_mask
& ~1) != 0)
25785 if (mask
& (1 << PC_REGNUM
))
25787 /* Catch popping the PC. */
25788 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
|| crtl
->calls_eh_return
25789 || IS_CMSE_ENTRY (arm_current_func_type ()))
25791 /* The PC is never poped directly, instead
25792 it is popped into r3 and then BX is used. */
25793 fprintf (f
, "}\n");
25795 thumb_exit (f
, -1);
25804 asm_fprintf (f
, "%r", PC_REGNUM
);
25808 fprintf (f
, "}\n");
25811 /* Generate code to return from a thumb function.
25812 If 'reg_containing_return_addr' is -1, then the return address is
25813 actually on the stack, at the stack pointer.
25815 Note: do not forget to update length attribute of corresponding insn pattern
25816 when changing assembly output (eg. length attribute of epilogue_insns when
25817 updating Armv8-M Baseline Security Extensions register clearing
25820 thumb_exit (FILE *f
, int reg_containing_return_addr
)
25822 unsigned regs_available_for_popping
;
25823 unsigned regs_to_pop
;
25825 unsigned available
;
25829 int restore_a4
= FALSE
;
25831 /* Compute the registers we need to pop. */
25835 if (reg_containing_return_addr
== -1)
25837 regs_to_pop
|= 1 << LR_REGNUM
;
25841 if (TARGET_BACKTRACE
)
25843 /* Restore the (ARM) frame pointer and stack pointer. */
25844 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
25848 /* If there is nothing to pop then just emit the BX instruction and
25850 if (pops_needed
== 0)
25852 if (crtl
->calls_eh_return
)
25853 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
25855 if (IS_CMSE_ENTRY (arm_current_func_type ()))
25857 /* For Armv8.1-M, this is cleared as part of the CLRM instruction
25858 emitted by cmse_nonsecure_entry_clear_before_return (). */
25859 if (!TARGET_HAVE_FPCXT_CMSE
)
25860 asm_fprintf (f
, "\tmsr\tAPSR_nzcvq, %r\n",
25861 reg_containing_return_addr
);
25862 asm_fprintf (f
, "\tbxns\t%r\n", reg_containing_return_addr
);
25865 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
25868 /* Otherwise if we are not supporting interworking and we have not created
25869 a backtrace structure and the function was not entered in ARM mode then
25870 just pop the return address straight into the PC. */
25871 else if (!TARGET_INTERWORK
25872 && !TARGET_BACKTRACE
25873 && !is_called_in_ARM_mode (current_function_decl
)
25874 && !crtl
->calls_eh_return
25875 && !IS_CMSE_ENTRY (arm_current_func_type ()))
25877 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
25881 /* Find out how many of the (return) argument registers we can corrupt. */
25882 regs_available_for_popping
= 0;
25884 /* If returning via __builtin_eh_return, the bottom three registers
25885 all contain information needed for the return. */
25886 if (crtl
->calls_eh_return
)
25890 /* If we can deduce the registers used from the function's
25891 return value. This is more reliable that examining
25892 df_regs_ever_live_p () because that will be set if the register is
25893 ever used in the function, not just if the register is used
25894 to hold a return value. */
25896 if (crtl
->return_rtx
!= 0)
25897 mode
= GET_MODE (crtl
->return_rtx
);
25899 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
25901 size
= GET_MODE_SIZE (mode
);
25905 /* In a void function we can use any argument register.
25906 In a function that returns a structure on the stack
25907 we can use the second and third argument registers. */
25908 if (mode
== VOIDmode
)
25909 regs_available_for_popping
=
25910 (1 << ARG_REGISTER (1))
25911 | (1 << ARG_REGISTER (2))
25912 | (1 << ARG_REGISTER (3));
25914 regs_available_for_popping
=
25915 (1 << ARG_REGISTER (2))
25916 | (1 << ARG_REGISTER (3));
25918 else if (size
<= 4)
25919 regs_available_for_popping
=
25920 (1 << ARG_REGISTER (2))
25921 | (1 << ARG_REGISTER (3));
25922 else if (size
<= 8)
25923 regs_available_for_popping
=
25924 (1 << ARG_REGISTER (3));
25927 /* Match registers to be popped with registers into which we pop them. */
25928 for (available
= regs_available_for_popping
,
25929 required
= regs_to_pop
;
25930 required
!= 0 && available
!= 0;
25931 available
&= ~(available
& - available
),
25932 required
&= ~(required
& - required
))
25935 /* If we have any popping registers left over, remove them. */
25937 regs_available_for_popping
&= ~available
;
25939 /* Otherwise if we need another popping register we can use
25940 the fourth argument register. */
25941 else if (pops_needed
)
25943 /* If we have not found any free argument registers and
25944 reg a4 contains the return address, we must move it. */
25945 if (regs_available_for_popping
== 0
25946 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
25948 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
25949 reg_containing_return_addr
= LR_REGNUM
;
25951 else if (size
> 12)
25953 /* Register a4 is being used to hold part of the return value,
25954 but we have dire need of a free, low register. */
25957 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
25960 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
25962 /* The fourth argument register is available. */
25963 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
25969 /* Pop as many registers as we can. */
25970 thumb_pop (f
, regs_available_for_popping
);
25972 /* Process the registers we popped. */
25973 if (reg_containing_return_addr
== -1)
25975 /* The return address was popped into the lowest numbered register. */
25976 regs_to_pop
&= ~(1 << LR_REGNUM
);
25978 reg_containing_return_addr
=
25979 number_of_first_bit_set (regs_available_for_popping
);
25981 /* Remove this register for the mask of available registers, so that
25982 the return address will not be corrupted by further pops. */
25983 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
25986 /* If we popped other registers then handle them here. */
25987 if (regs_available_for_popping
)
25991 /* Work out which register currently contains the frame pointer. */
25992 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
25994 /* Move it into the correct place. */
25995 asm_fprintf (f
, "\tmov\t%r, %r\n",
25996 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
25998 /* (Temporarily) remove it from the mask of popped registers. */
25999 regs_available_for_popping
&= ~(1 << frame_pointer
);
26000 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
26002 if (regs_available_for_popping
)
26006 /* We popped the stack pointer as well,
26007 find the register that contains it. */
26008 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
26010 /* Move it into the stack register. */
26011 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
26013 /* At this point we have popped all necessary registers, so
26014 do not worry about restoring regs_available_for_popping
26015 to its correct value:
26017 assert (pops_needed == 0)
26018 assert (regs_available_for_popping == (1 << frame_pointer))
26019 assert (regs_to_pop == (1 << STACK_POINTER)) */
26023 /* Since we have just move the popped value into the frame
26024 pointer, the popping register is available for reuse, and
26025 we know that we still have the stack pointer left to pop. */
26026 regs_available_for_popping
|= (1 << frame_pointer
);
26030 /* If we still have registers left on the stack, but we no longer have
26031 any registers into which we can pop them, then we must move the return
26032 address into the link register and make available the register that
26034 if (regs_available_for_popping
== 0 && pops_needed
> 0)
26036 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
26038 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
26039 reg_containing_return_addr
);
26041 reg_containing_return_addr
= LR_REGNUM
;
26044 /* If we have registers left on the stack then pop some more.
26045 We know that at most we will want to pop FP and SP. */
26046 if (pops_needed
> 0)
26051 thumb_pop (f
, regs_available_for_popping
);
26053 /* We have popped either FP or SP.
26054 Move whichever one it is into the correct register. */
26055 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
26056 move_to
= number_of_first_bit_set (regs_to_pop
);
26058 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
26062 /* If we still have not popped everything then we must have only
26063 had one register available to us and we are now popping the SP. */
26064 if (pops_needed
> 0)
26068 thumb_pop (f
, regs_available_for_popping
);
26070 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
26072 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
26074 assert (regs_to_pop == (1 << STACK_POINTER))
26075 assert (pops_needed == 1)
26079 /* If necessary restore the a4 register. */
26082 if (reg_containing_return_addr
!= LR_REGNUM
)
26084 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
26085 reg_containing_return_addr
= LR_REGNUM
;
26088 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
26091 if (crtl
->calls_eh_return
)
26092 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, ARM_EH_STACKADJ_REGNUM
);
26094 /* Return to caller. */
26095 if (IS_CMSE_ENTRY (arm_current_func_type ()))
26097 /* This is for the cases where LR is not being used to contain the return
26098 address. It may therefore contain information that we might not want
26099 to leak, hence it must be cleared. The value in R0 will never be a
26100 secret at this point, so it is safe to use it, see the clearing code
26101 in cmse_nonsecure_entry_clear_before_return (). */
26102 if (reg_containing_return_addr
!= LR_REGNUM
)
26103 asm_fprintf (f
, "\tmov\tlr, r0\n");
26105 /* For Armv8.1-M, this is cleared as part of the CLRM instruction emitted
26106 by cmse_nonsecure_entry_clear_before_return (). */
26107 if (!TARGET_HAVE_FPCXT_CMSE
)
26108 asm_fprintf (f
, "\tmsr\tAPSR_nzcvq, %r\n", reg_containing_return_addr
);
26109 asm_fprintf (f
, "\tbxns\t%r\n", reg_containing_return_addr
);
26112 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
26115 /* Scan INSN just before assembler is output for it.
26116 For Thumb-1, we track the status of the condition codes; this
26117 information is used in the cbranchsi4_insn pattern. */
26119 thumb1_final_prescan_insn (rtx_insn
*insn
)
26121 if (flag_print_asm_name
)
26122 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
26123 INSN_ADDRESSES (INSN_UID (insn
)));
26124 /* Don't overwrite the previous setter when we get to a cbranch. */
26125 if (INSN_CODE (insn
) != CODE_FOR_cbranchsi4_insn
)
26127 enum attr_conds conds
;
26129 if (cfun
->machine
->thumb1_cc_insn
)
26131 if (modified_in_p (cfun
->machine
->thumb1_cc_op0
, insn
)
26132 || modified_in_p (cfun
->machine
->thumb1_cc_op1
, insn
))
26135 conds
= get_attr_conds (insn
);
26136 if (conds
== CONDS_SET
)
26138 rtx set
= single_set (insn
);
26139 cfun
->machine
->thumb1_cc_insn
= insn
;
26140 cfun
->machine
->thumb1_cc_op0
= SET_DEST (set
);
26141 cfun
->machine
->thumb1_cc_op1
= const0_rtx
;
26142 cfun
->machine
->thumb1_cc_mode
= CC_NZmode
;
26143 if (INSN_CODE (insn
) == CODE_FOR_thumb1_subsi3_insn
)
26145 rtx src1
= XEXP (SET_SRC (set
), 1);
26146 if (src1
== const0_rtx
)
26147 cfun
->machine
->thumb1_cc_mode
= CCmode
;
26149 else if (REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
26151 /* Record the src register operand instead of dest because
26152 cprop_hardreg pass propagates src. */
26153 cfun
->machine
->thumb1_cc_op0
= SET_SRC (set
);
26156 else if (conds
!= CONDS_NOCOND
)
26157 cfun
->machine
->thumb1_cc_insn
= NULL_RTX
;
26160 /* Check if unexpected far jump is used. */
26161 if (cfun
->machine
->lr_save_eliminated
26162 && get_attr_far_jump (insn
) == FAR_JUMP_YES
)
26163 internal_error("Unexpected thumb1 far jump");
26167 thumb_shiftable_const (unsigned HOST_WIDE_INT val
)
26169 unsigned HOST_WIDE_INT mask
= 0xff;
26172 val
= val
& (unsigned HOST_WIDE_INT
)0xffffffffu
;
26173 if (val
== 0) /* XXX */
26176 for (i
= 0; i
< 25; i
++)
26177 if ((val
& (mask
<< i
)) == val
)
26183 /* Returns nonzero if the current function contains,
26184 or might contain a far jump. */
26186 thumb_far_jump_used_p (void)
26189 bool far_jump
= false;
26190 unsigned int func_size
= 0;
26192 /* If we have already decided that far jumps may be used,
26193 do not bother checking again, and always return true even if
26194 it turns out that they are not being used. Once we have made
26195 the decision that far jumps are present (and that hence the link
26196 register will be pushed onto the stack) we cannot go back on it. */
26197 if (cfun
->machine
->far_jump_used
)
26200 /* If this function is not being called from the prologue/epilogue
26201 generation code then it must be being called from the
26202 INITIAL_ELIMINATION_OFFSET macro. */
26203 if (!(ARM_DOUBLEWORD_ALIGN
|| reload_completed
))
26205 /* In this case we know that we are being asked about the elimination
26206 of the arg pointer register. If that register is not being used,
26207 then there are no arguments on the stack, and we do not have to
26208 worry that a far jump might force the prologue to push the link
26209 register, changing the stack offsets. In this case we can just
26210 return false, since the presence of far jumps in the function will
26211 not affect stack offsets.
26213 If the arg pointer is live (or if it was live, but has now been
26214 eliminated and so set to dead) then we do have to test to see if
26215 the function might contain a far jump. This test can lead to some
26216 false negatives, since before reload is completed, then length of
26217 branch instructions is not known, so gcc defaults to returning their
26218 longest length, which in turn sets the far jump attribute to true.
26220 A false negative will not result in bad code being generated, but it
26221 will result in a needless push and pop of the link register. We
26222 hope that this does not occur too often.
26224 If we need doubleword stack alignment this could affect the other
26225 elimination offsets so we can't risk getting it wrong. */
26226 if (df_regs_ever_live_p (ARG_POINTER_REGNUM
))
26227 cfun
->machine
->arg_pointer_live
= 1;
26228 else if (!cfun
->machine
->arg_pointer_live
)
26232 /* We should not change far_jump_used during or after reload, as there is
26233 no chance to change stack frame layout. */
26234 if (reload_in_progress
|| reload_completed
)
26237 /* Check to see if the function contains a branch
26238 insn with the far jump attribute set. */
26239 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
26241 if (JUMP_P (insn
) && get_attr_far_jump (insn
) == FAR_JUMP_YES
)
26245 func_size
+= get_attr_length (insn
);
26248 /* Attribute far_jump will always be true for thumb1 before
26249 shorten_branch pass. So checking far_jump attribute before
26250 shorten_branch isn't much useful.
26252 Following heuristic tries to estimate more accurately if a far jump
26253 may finally be used. The heuristic is very conservative as there is
26254 no chance to roll-back the decision of not to use far jump.
26256 Thumb1 long branch offset is -2048 to 2046. The worst case is each
26257 2-byte insn is associated with a 4 byte constant pool. Using
26258 function size 2048/3 as the threshold is conservative enough. */
26261 if ((func_size
* 3) >= 2048)
26263 /* Record the fact that we have decided that
26264 the function does use far jumps. */
26265 cfun
->machine
->far_jump_used
= 1;
26273 /* Return nonzero if FUNC must be entered in ARM mode. */
26275 is_called_in_ARM_mode (tree func
)
26277 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
26279 /* Ignore the problem about functions whose address is taken. */
26280 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
26284 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
26290 /* Given the stack offsets and register mask in OFFSETS, decide how
26291 many additional registers to push instead of subtracting a constant
26292 from SP. For epilogues the principle is the same except we use pop.
26293 FOR_PROLOGUE indicates which we're generating. */
26295 thumb1_extra_regs_pushed (arm_stack_offsets
*offsets
, bool for_prologue
)
26297 HOST_WIDE_INT amount
;
26298 unsigned long live_regs_mask
= offsets
->saved_regs_mask
;
26299 /* Extract a mask of the ones we can give to the Thumb's push/pop
26301 unsigned long l_mask
= live_regs_mask
& (for_prologue
? 0x40ff : 0xff);
26302 /* Then count how many other high registers will need to be pushed. */
26303 unsigned long high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
26304 int n_free
, reg_base
, size
;
26306 if (!for_prologue
&& frame_pointer_needed
)
26307 amount
= offsets
->locals_base
- offsets
->saved_regs
;
26309 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
26311 /* If the stack frame size is 512 exactly, we can save one load
26312 instruction, which should make this a win even when optimizing
26314 if (!optimize_size
&& amount
!= 512)
26317 /* Can't do this if there are high registers to push. */
26318 if (high_regs_pushed
!= 0)
26321 /* Shouldn't do it in the prologue if no registers would normally
26322 be pushed at all. In the epilogue, also allow it if we'll have
26323 a pop insn for the PC. */
26326 || TARGET_BACKTRACE
26327 || (live_regs_mask
& 1 << LR_REGNUM
) == 0
26328 || TARGET_INTERWORK
26329 || crtl
->args
.pretend_args_size
!= 0))
26332 /* Don't do this if thumb_expand_prologue wants to emit instructions
26333 between the push and the stack frame allocation. */
26335 && ((flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
26336 || (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)))
26343 size
= arm_size_return_regs ();
26344 reg_base
= ARM_NUM_INTS (size
);
26345 live_regs_mask
>>= reg_base
;
26348 while (reg_base
+ n_free
< 8 && !(live_regs_mask
& 1)
26349 && (for_prologue
|| call_used_or_fixed_reg_p (reg_base
+ n_free
)))
26351 live_regs_mask
>>= 1;
26357 gcc_assert (amount
/ 4 * 4 == amount
);
26359 if (amount
>= 512 && (amount
- n_free
* 4) < 512)
26360 return (amount
- 508) / 4;
26361 if (amount
<= n_free
* 4)
26366 /* The bits which aren't usefully expanded as rtl. */
26368 thumb1_unexpanded_epilogue (void)
26370 arm_stack_offsets
*offsets
;
26372 unsigned long live_regs_mask
= 0;
26373 int high_regs_pushed
= 0;
26375 int had_to_push_lr
;
26378 if (cfun
->machine
->return_used_this_function
!= 0)
26381 if (IS_NAKED (arm_current_func_type ()))
26384 offsets
= arm_get_frame_offsets ();
26385 live_regs_mask
= offsets
->saved_regs_mask
;
26386 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
26388 /* If we can deduce the registers used from the function's return value.
26389 This is more reliable that examining df_regs_ever_live_p () because that
26390 will be set if the register is ever used in the function, not just if
26391 the register is used to hold a return value. */
26392 size
= arm_size_return_regs ();
26394 extra_pop
= thumb1_extra_regs_pushed (offsets
, false);
26397 unsigned long extra_mask
= (1 << extra_pop
) - 1;
26398 live_regs_mask
|= extra_mask
<< ARM_NUM_INTS (size
);
26401 /* The prolog may have pushed some high registers to use as
26402 work registers. e.g. the testsuite file:
26403 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
26404 compiles to produce:
26405 push {r4, r5, r6, r7, lr}
26409 as part of the prolog. We have to undo that pushing here. */
26411 if (high_regs_pushed
)
26413 unsigned long mask
= live_regs_mask
& 0xff;
26416 mask
|= thumb1_epilogue_unused_call_clobbered_lo_regs ();
26419 /* Oh dear! We have no low registers into which we can pop
26422 ("no low registers available for popping high registers");
26424 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
26425 if (live_regs_mask
& (1 << next_hi_reg
))
26428 while (high_regs_pushed
)
26430 /* Find lo register(s) into which the high register(s) can
26432 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
26434 if (mask
& (1 << regno
))
26435 high_regs_pushed
--;
26436 if (high_regs_pushed
== 0)
26440 if (high_regs_pushed
== 0 && regno
>= 0)
26441 mask
&= ~((1 << regno
) - 1);
26443 /* Pop the values into the low register(s). */
26444 thumb_pop (asm_out_file
, mask
);
26446 /* Move the value(s) into the high registers. */
26447 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
26449 if (mask
& (1 << regno
))
26451 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
26454 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
26456 if (live_regs_mask
& (1 << next_hi_reg
))
26461 live_regs_mask
&= ~0x0f00;
26464 had_to_push_lr
= (live_regs_mask
& (1 << LR_REGNUM
)) != 0;
26465 live_regs_mask
&= 0xff;
26467 if (crtl
->args
.pretend_args_size
== 0 || TARGET_BACKTRACE
)
26469 /* Pop the return address into the PC. */
26470 if (had_to_push_lr
)
26471 live_regs_mask
|= 1 << PC_REGNUM
;
26473 /* Either no argument registers were pushed or a backtrace
26474 structure was created which includes an adjusted stack
26475 pointer, so just pop everything. */
26476 if (live_regs_mask
)
26477 thumb_pop (asm_out_file
, live_regs_mask
);
26479 /* We have either just popped the return address into the
26480 PC or it is was kept in LR for the entire function.
26481 Note that thumb_pop has already called thumb_exit if the
26482 PC was in the list. */
26483 if (!had_to_push_lr
)
26484 thumb_exit (asm_out_file
, LR_REGNUM
);
26488 /* Pop everything but the return address. */
26489 if (live_regs_mask
)
26490 thumb_pop (asm_out_file
, live_regs_mask
);
26492 if (had_to_push_lr
)
26496 /* We have no free low regs, so save one. */
26497 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", IP_REGNUM
,
26501 /* Get the return address into a temporary register. */
26502 thumb_pop (asm_out_file
, 1 << LAST_ARG_REGNUM
);
26506 /* Move the return address to lr. */
26507 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LR_REGNUM
,
26509 /* Restore the low register. */
26510 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
,
26515 regno
= LAST_ARG_REGNUM
;
26520 /* Remove the argument registers that were pushed onto the stack. */
26521 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
26522 SP_REGNUM
, SP_REGNUM
,
26523 crtl
->args
.pretend_args_size
);
26525 thumb_exit (asm_out_file
, regno
);
26531 /* Functions to save and restore machine-specific function data. */
26532 static struct machine_function
*
26533 arm_init_machine_status (void)
26535 struct machine_function
*machine
;
26536 machine
= ggc_cleared_alloc
<machine_function
> ();
26538 #if ARM_FT_UNKNOWN != 0
26539 machine
->func_type
= ARM_FT_UNKNOWN
;
26541 machine
->static_chain_stack_bytes
= -1;
26545 /* Return an RTX indicating where the return address to the
26546 calling function can be found. */
26548 arm_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
26553 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
26556 /* Do anything needed before RTL is emitted for each function. */
26558 arm_init_expanders (void)
26560 /* Arrange to initialize and mark the machine per-function status. */
26561 init_machine_status
= arm_init_machine_status
;
26563 /* This is to stop the combine pass optimizing away the alignment
26564 adjustment of va_arg. */
26565 /* ??? It is claimed that this should not be necessary. */
26567 mark_reg_pointer (arg_pointer_rtx
, PARM_BOUNDARY
);
26570 /* Check that FUNC is called with a different mode. */
26573 arm_change_mode_p (tree func
)
26575 if (TREE_CODE (func
) != FUNCTION_DECL
)
26578 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (func
);
26581 callee_tree
= target_option_default_node
;
26583 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
26584 int flags
= callee_opts
->x_target_flags
;
26586 return (TARGET_THUMB_P (flags
) != TARGET_THUMB
);
26589 /* Like arm_compute_initial_elimination offset. Simpler because there
26590 isn't an ABI specified frame pointer for Thumb. Instead, we set it
26591 to point at the base of the local variables after static stack
26592 space for a function has been allocated. */
26595 thumb_compute_initial_elimination_offset (unsigned int from
, unsigned int to
)
26597 arm_stack_offsets
*offsets
;
26599 offsets
= arm_get_frame_offsets ();
26603 case ARG_POINTER_REGNUM
:
26606 case STACK_POINTER_REGNUM
:
26607 return offsets
->outgoing_args
- offsets
->saved_args
;
26609 case FRAME_POINTER_REGNUM
:
26610 return offsets
->soft_frame
- offsets
->saved_args
;
26612 case ARM_HARD_FRAME_POINTER_REGNUM
:
26613 return offsets
->saved_regs
- offsets
->saved_args
;
26615 case THUMB_HARD_FRAME_POINTER_REGNUM
:
26616 return offsets
->locals_base
- offsets
->saved_args
;
26619 gcc_unreachable ();
26623 case FRAME_POINTER_REGNUM
:
26626 case STACK_POINTER_REGNUM
:
26627 return offsets
->outgoing_args
- offsets
->soft_frame
;
26629 case ARM_HARD_FRAME_POINTER_REGNUM
:
26630 return offsets
->saved_regs
- offsets
->soft_frame
;
26632 case THUMB_HARD_FRAME_POINTER_REGNUM
:
26633 return offsets
->locals_base
- offsets
->soft_frame
;
26636 gcc_unreachable ();
26641 gcc_unreachable ();
26645 /* Generate the function's prologue. */
26648 thumb1_expand_prologue (void)
26652 HOST_WIDE_INT amount
;
26653 HOST_WIDE_INT size
;
26654 arm_stack_offsets
*offsets
;
26655 unsigned long func_type
;
26657 unsigned long live_regs_mask
;
26658 unsigned long l_mask
;
26659 unsigned high_regs_pushed
= 0;
26660 bool lr_needs_saving
;
26662 func_type
= arm_current_func_type ();
26664 /* Naked functions don't have prologues. */
26665 if (IS_NAKED (func_type
))
26667 if (flag_stack_usage_info
)
26668 current_function_static_stack_size
= 0;
26672 if (IS_INTERRUPT (func_type
))
26674 error ("Interrupt Service Routines cannot be coded in Thumb-1 mode");
26678 if (is_called_in_ARM_mode (current_function_decl
))
26679 emit_insn (gen_prologue_thumb1_interwork ());
26681 offsets
= arm_get_frame_offsets ();
26682 live_regs_mask
= offsets
->saved_regs_mask
;
26683 lr_needs_saving
= live_regs_mask
& (1 << LR_REGNUM
);
26685 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
26686 l_mask
= live_regs_mask
& 0x40ff;
26687 /* Then count how many other high registers will need to be pushed. */
26688 high_regs_pushed
= bit_count (live_regs_mask
& 0x0f00);
26690 if (crtl
->args
.pretend_args_size
)
26692 rtx x
= GEN_INT (-crtl
->args
.pretend_args_size
);
26694 if (cfun
->machine
->uses_anonymous_args
)
26696 int num_pushes
= ARM_NUM_INTS (crtl
->args
.pretend_args_size
);
26697 unsigned long mask
;
26699 mask
= 1ul << (LAST_ARG_REGNUM
+ 1);
26700 mask
-= 1ul << (LAST_ARG_REGNUM
+ 1 - num_pushes
);
26702 insn
= thumb1_emit_multi_reg_push (mask
, 0);
26706 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
26707 stack_pointer_rtx
, x
));
26709 RTX_FRAME_RELATED_P (insn
) = 1;
26712 if (TARGET_BACKTRACE
)
26714 HOST_WIDE_INT offset
= 0;
26715 unsigned work_register
;
26716 rtx work_reg
, x
, arm_hfp_rtx
;
26718 /* We have been asked to create a stack backtrace structure.
26719 The code looks like this:
26723 0 sub SP, #16 Reserve space for 4 registers.
26724 2 push {R7} Push low registers.
26725 4 add R7, SP, #20 Get the stack pointer before the push.
26726 6 str R7, [SP, #8] Store the stack pointer
26727 (before reserving the space).
26728 8 mov R7, PC Get hold of the start of this code + 12.
26729 10 str R7, [SP, #16] Store it.
26730 12 mov R7, FP Get hold of the current frame pointer.
26731 14 str R7, [SP, #4] Store it.
26732 16 mov R7, LR Get hold of the current return address.
26733 18 str R7, [SP, #12] Store it.
26734 20 add R7, SP, #16 Point at the start of the
26735 backtrace structure.
26736 22 mov FP, R7 Put this value into the frame pointer. */
26738 work_register
= thumb_find_work_register (live_regs_mask
);
26739 work_reg
= gen_rtx_REG (SImode
, work_register
);
26740 arm_hfp_rtx
= gen_rtx_REG (SImode
, ARM_HARD_FRAME_POINTER_REGNUM
);
26742 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
26743 stack_pointer_rtx
, GEN_INT (-16)));
26744 RTX_FRAME_RELATED_P (insn
) = 1;
26748 insn
= thumb1_emit_multi_reg_push (l_mask
, l_mask
);
26749 RTX_FRAME_RELATED_P (insn
) = 1;
26750 lr_needs_saving
= false;
26752 offset
= bit_count (l_mask
) * UNITS_PER_WORD
;
26755 x
= GEN_INT (offset
+ 16 + crtl
->args
.pretend_args_size
);
26756 emit_insn (gen_addsi3 (work_reg
, stack_pointer_rtx
, x
));
26758 x
= plus_constant (Pmode
, stack_pointer_rtx
, offset
+ 4);
26759 x
= gen_frame_mem (SImode
, x
);
26760 emit_move_insn (x
, work_reg
);
26762 /* Make sure that the instruction fetching the PC is in the right place
26763 to calculate "start of backtrace creation code + 12". */
26764 /* ??? The stores using the common WORK_REG ought to be enough to
26765 prevent the scheduler from doing anything weird. Failing that
26766 we could always move all of the following into an UNSPEC_VOLATILE. */
26769 x
= gen_rtx_REG (SImode
, PC_REGNUM
);
26770 emit_move_insn (work_reg
, x
);
26772 x
= plus_constant (Pmode
, stack_pointer_rtx
, offset
+ 12);
26773 x
= gen_frame_mem (SImode
, x
);
26774 emit_move_insn (x
, work_reg
);
26776 emit_move_insn (work_reg
, arm_hfp_rtx
);
26778 x
= plus_constant (Pmode
, stack_pointer_rtx
, offset
);
26779 x
= gen_frame_mem (SImode
, x
);
26780 emit_move_insn (x
, work_reg
);
26784 emit_move_insn (work_reg
, arm_hfp_rtx
);
26786 x
= plus_constant (Pmode
, stack_pointer_rtx
, offset
);
26787 x
= gen_frame_mem (SImode
, x
);
26788 emit_move_insn (x
, work_reg
);
26790 x
= gen_rtx_REG (SImode
, PC_REGNUM
);
26791 emit_move_insn (work_reg
, x
);
26793 x
= plus_constant (Pmode
, stack_pointer_rtx
, offset
+ 12);
26794 x
= gen_frame_mem (SImode
, x
);
26795 emit_move_insn (x
, work_reg
);
26798 x
= gen_rtx_REG (SImode
, LR_REGNUM
);
26799 emit_move_insn (work_reg
, x
);
26801 x
= plus_constant (Pmode
, stack_pointer_rtx
, offset
+ 8);
26802 x
= gen_frame_mem (SImode
, x
);
26803 emit_move_insn (x
, work_reg
);
26805 x
= GEN_INT (offset
+ 12);
26806 emit_insn (gen_addsi3 (work_reg
, stack_pointer_rtx
, x
));
26808 emit_move_insn (arm_hfp_rtx
, work_reg
);
26810 /* Optimization: If we are not pushing any low registers but we are going
26811 to push some high registers then delay our first push. This will just
26812 be a push of LR and we can combine it with the push of the first high
26814 else if ((l_mask
& 0xff) != 0
26815 || (high_regs_pushed
== 0 && lr_needs_saving
))
26817 unsigned long mask
= l_mask
;
26818 mask
|= (1 << thumb1_extra_regs_pushed (offsets
, true)) - 1;
26819 insn
= thumb1_emit_multi_reg_push (mask
, mask
);
26820 RTX_FRAME_RELATED_P (insn
) = 1;
26821 lr_needs_saving
= false;
26824 if (high_regs_pushed
)
26826 unsigned pushable_regs
;
26827 unsigned next_hi_reg
;
26828 unsigned arg_regs_num
= TARGET_AAPCS_BASED
? crtl
->args
.info
.aapcs_ncrn
26829 : crtl
->args
.info
.nregs
;
26830 unsigned arg_regs_mask
= (1 << arg_regs_num
) - 1;
26832 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
26833 if (live_regs_mask
& (1 << next_hi_reg
))
26836 /* Here we need to mask out registers used for passing arguments
26837 even if they can be pushed. This is to avoid using them to
26838 stash the high registers. Such kind of stash may clobber the
26839 use of arguments. */
26840 pushable_regs
= l_mask
& (~arg_regs_mask
);
26841 pushable_regs
|= thumb1_prologue_unused_call_clobbered_lo_regs ();
26843 /* Normally, LR can be used as a scratch register once it has been
26844 saved; but if the function examines its own return address then
26845 the value is still live and we need to avoid using it. */
26846 bool return_addr_live
26847 = REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR_FOR_FN (cfun
)),
26850 if (lr_needs_saving
|| return_addr_live
)
26851 pushable_regs
&= ~(1 << LR_REGNUM
);
26853 if (pushable_regs
== 0)
26854 pushable_regs
= 1 << thumb_find_work_register (live_regs_mask
);
26856 while (high_regs_pushed
> 0)
26858 unsigned long real_regs_mask
= 0;
26859 unsigned long push_mask
= 0;
26861 for (regno
= LR_REGNUM
; regno
>= 0; regno
--)
26863 if (pushable_regs
& (1 << regno
))
26865 emit_move_insn (gen_rtx_REG (SImode
, regno
),
26866 gen_rtx_REG (SImode
, next_hi_reg
));
26868 high_regs_pushed
--;
26869 real_regs_mask
|= (1 << next_hi_reg
);
26870 push_mask
|= (1 << regno
);
26872 if (high_regs_pushed
)
26874 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
26876 if (live_regs_mask
& (1 << next_hi_reg
))
26884 /* If we had to find a work register and we have not yet
26885 saved the LR then add it to the list of regs to push. */
26886 if (lr_needs_saving
)
26888 push_mask
|= 1 << LR_REGNUM
;
26889 real_regs_mask
|= 1 << LR_REGNUM
;
26890 lr_needs_saving
= false;
26891 /* If the return address is not live at this point, we
26892 can add LR to the list of registers that we can use
26894 if (!return_addr_live
)
26895 pushable_regs
|= 1 << LR_REGNUM
;
26898 insn
= thumb1_emit_multi_reg_push (push_mask
, real_regs_mask
);
26899 RTX_FRAME_RELATED_P (insn
) = 1;
26903 /* Load the pic register before setting the frame pointer,
26904 so we can use r7 as a temporary work register. */
26905 if (flag_pic
&& arm_pic_register
!= INVALID_REGNUM
)
26906 arm_load_pic_register (live_regs_mask
, NULL_RTX
);
26908 if (!frame_pointer_needed
&& CALLER_INTERWORKING_SLOT_SIZE
> 0)
26909 emit_move_insn (gen_rtx_REG (Pmode
, ARM_HARD_FRAME_POINTER_REGNUM
),
26910 stack_pointer_rtx
);
26912 size
= offsets
->outgoing_args
- offsets
->saved_args
;
26913 if (flag_stack_usage_info
)
26914 current_function_static_stack_size
= size
;
26916 /* If we have a frame, then do stack checking. FIXME: not implemented. */
26917 if ((flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
26918 || flag_stack_clash_protection
)
26920 sorry ("%<-fstack-check=specific%> for Thumb-1");
26922 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
26923 amount
-= 4 * thumb1_extra_regs_pushed (offsets
, true);
26928 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
26929 GEN_INT (- amount
)));
26930 RTX_FRAME_RELATED_P (insn
) = 1;
26936 /* The stack decrement is too big for an immediate value in a single
26937 insn. In theory we could issue multiple subtracts, but after
26938 three of them it becomes more space efficient to place the full
26939 value in the constant pool and load into a register. (Also the
26940 ARM debugger really likes to see only one stack decrement per
26941 function). So instead we look for a scratch register into which
26942 we can load the decrement, and then we subtract this from the
26943 stack pointer. Unfortunately on the thumb the only available
26944 scratch registers are the argument registers, and we cannot use
26945 these as they may hold arguments to the function. Instead we
26946 attempt to locate a call preserved register which is used by this
26947 function. If we can find one, then we know that it will have
26948 been pushed at the start of the prologue and so we can corrupt
26950 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
26951 if (live_regs_mask
& (1 << regno
))
26954 gcc_assert(regno
<= LAST_LO_REGNUM
);
26956 reg
= gen_rtx_REG (SImode
, regno
);
26958 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
26960 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
26961 stack_pointer_rtx
, reg
));
26963 dwarf
= gen_rtx_SET (stack_pointer_rtx
,
26964 plus_constant (Pmode
, stack_pointer_rtx
,
26966 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
26967 RTX_FRAME_RELATED_P (insn
) = 1;
26971 if (frame_pointer_needed
)
26972 thumb_set_frame_pointer (offsets
);
26974 /* If we are profiling, make sure no instructions are scheduled before
26975 the call to mcount. Similarly if the user has requested no
26976 scheduling in the prolog. Similarly if we want non-call exceptions
26977 using the EABI unwinder, to prevent faulting instructions from being
26978 swapped with a stack adjustment. */
26979 if (crtl
->profile
|| !TARGET_SCHED_PROLOG
26980 || (arm_except_unwind_info (&global_options
) == UI_TARGET
26981 && cfun
->can_throw_non_call_exceptions
))
26982 emit_insn (gen_blockage ());
26984 cfun
->machine
->lr_save_eliminated
= !thumb_force_lr_save ();
26985 if (live_regs_mask
& 0xff)
26986 cfun
->machine
->lr_save_eliminated
= 0;
26989 /* Clear caller saved registers not used to pass return values and leaked
26990 condition flags before exiting a cmse_nonsecure_entry function. */
26993 cmse_nonsecure_entry_clear_before_return (void)
26995 bool clear_vfpregs
= TARGET_HARD_FLOAT
|| TARGET_HAVE_FPCXT_CMSE
;
26996 int regno
, maxregno
= clear_vfpregs
? LAST_VFP_REGNUM
: IP_REGNUM
;
26997 uint32_t padding_bits_to_clear
= 0;
26998 auto_sbitmap
to_clear_bitmap (maxregno
+ 1);
26999 rtx r1_reg
, result_rtl
, clearing_reg
= NULL_RTX
;
27002 bitmap_clear (to_clear_bitmap
);
27003 bitmap_set_range (to_clear_bitmap
, R0_REGNUM
, NUM_ARG_REGS
);
27004 bitmap_set_bit (to_clear_bitmap
, IP_REGNUM
);
27006 /* If we are not dealing with -mfloat-abi=soft we will need to clear VFP
27010 int float_bits
= D7_VFP_REGNUM
- FIRST_VFP_REGNUM
+ 1;
27012 bitmap_set_range (to_clear_bitmap
, FIRST_VFP_REGNUM
, float_bits
);
27014 if (!TARGET_HAVE_FPCXT_CMSE
)
27016 /* Make sure we don't clear the two scratch registers used to clear
27017 the relevant FPSCR bits in output_return_instruction. */
27018 emit_use (gen_rtx_REG (SImode
, IP_REGNUM
));
27019 bitmap_clear_bit (to_clear_bitmap
, IP_REGNUM
);
27020 emit_use (gen_rtx_REG (SImode
, 4));
27021 bitmap_clear_bit (to_clear_bitmap
, 4);
27025 /* If the user has defined registers to be caller saved, these are no longer
27026 restored by the function before returning and must thus be cleared for
27027 security purposes. */
27028 for (regno
= NUM_ARG_REGS
; regno
<= maxregno
; regno
++)
27030 /* We do not touch registers that can be used to pass arguments as per
27031 the AAPCS, since these should never be made callee-saved by user
27033 if (IN_RANGE (regno
, FIRST_VFP_REGNUM
, D7_VFP_REGNUM
))
27035 if (IN_RANGE (regno
, IP_REGNUM
, PC_REGNUM
))
27037 if (!callee_saved_reg_p (regno
)
27038 && (!IN_RANGE (regno
, FIRST_VFP_REGNUM
, LAST_VFP_REGNUM
)
27039 || TARGET_HARD_FLOAT
))
27040 bitmap_set_bit (to_clear_bitmap
, regno
);
27043 /* Make sure we do not clear the registers used to return the result in. */
27044 result_type
= TREE_TYPE (DECL_RESULT (current_function_decl
));
27045 if (!VOID_TYPE_P (result_type
))
27047 uint64_t to_clear_return_mask
;
27048 result_rtl
= arm_function_value (result_type
, current_function_decl
, 0);
27050 /* No need to check that we return in registers, because we don't
27051 support returning on stack yet. */
27052 gcc_assert (REG_P (result_rtl
));
27053 to_clear_return_mask
27054 = compute_not_to_clear_mask (result_type
, result_rtl
, 0,
27055 &padding_bits_to_clear
);
27056 if (to_clear_return_mask
)
27058 gcc_assert ((unsigned) maxregno
< sizeof (long long) * __CHAR_BIT__
);
27059 for (regno
= R0_REGNUM
; regno
<= maxregno
; regno
++)
27061 if (to_clear_return_mask
& (1ULL << regno
))
27062 bitmap_clear_bit (to_clear_bitmap
, regno
);
27067 if (padding_bits_to_clear
!= 0)
27069 int to_clear_bitmap_size
= SBITMAP_SIZE ((sbitmap
) to_clear_bitmap
);
27070 auto_sbitmap
to_clear_arg_regs_bitmap (to_clear_bitmap_size
);
27072 /* Padding_bits_to_clear is not 0 so we know we are dealing with
27073 returning a composite type, which only uses r0. Let's make sure that
27074 r1-r3 is cleared too. */
27075 bitmap_clear (to_clear_arg_regs_bitmap
);
27076 bitmap_set_range (to_clear_arg_regs_bitmap
, R1_REGNUM
, NUM_ARG_REGS
- 1);
27077 gcc_assert (bitmap_subset_p (to_clear_arg_regs_bitmap
, to_clear_bitmap
));
27080 /* Clear full registers that leak before returning. */
27081 clearing_reg
= gen_rtx_REG (SImode
, TARGET_THUMB1
? R0_REGNUM
: LR_REGNUM
);
27082 r1_reg
= gen_rtx_REG (SImode
, R0_REGNUM
+ 1);
27083 cmse_clear_registers (to_clear_bitmap
, &padding_bits_to_clear
, 1, r1_reg
,
27087 /* Generate pattern *pop_multiple_with_stack_update_and_return if single
27088 POP instruction can be generated. LR should be replaced by PC. All
27089 the checks required are already done by USE_RETURN_INSN (). Hence,
27090 all we really need to check here is if single register is to be
27091 returned, or multiple register return. */
27093 thumb2_expand_return (bool simple_return
)
27096 unsigned long saved_regs_mask
;
27097 arm_stack_offsets
*offsets
;
27099 offsets
= arm_get_frame_offsets ();
27100 saved_regs_mask
= offsets
->saved_regs_mask
;
27102 for (i
= 0, num_regs
= 0; i
<= LAST_ARM_REGNUM
; i
++)
27103 if (saved_regs_mask
& (1 << i
))
27106 if (!simple_return
&& saved_regs_mask
)
27108 /* TODO: Verify that this path is never taken for cmse_nonsecure_entry
27109 functions or adapt code to handle according to ACLE. This path should
27110 not be reachable for cmse_nonsecure_entry functions though we prefer
27111 to assert it for now to ensure that future code changes do not silently
27112 change this behavior. */
27113 gcc_assert (!IS_CMSE_ENTRY (arm_current_func_type ()));
27116 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
27117 rtx reg
= gen_rtx_REG (SImode
, PC_REGNUM
);
27118 rtx addr
= gen_rtx_MEM (SImode
,
27119 gen_rtx_POST_INC (SImode
,
27120 stack_pointer_rtx
));
27121 set_mem_alias_set (addr
, get_frame_alias_set ());
27122 XVECEXP (par
, 0, 0) = ret_rtx
;
27123 XVECEXP (par
, 0, 1) = gen_rtx_SET (reg
, addr
);
27124 RTX_FRAME_RELATED_P (XVECEXP (par
, 0, 1)) = 1;
27125 emit_jump_insn (par
);
27129 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
27130 saved_regs_mask
|= (1 << PC_REGNUM
);
27131 arm_emit_multi_reg_pop (saved_regs_mask
);
27136 if (IS_CMSE_ENTRY (arm_current_func_type ()))
27137 cmse_nonsecure_entry_clear_before_return ();
27138 emit_jump_insn (simple_return_rtx
);
27143 thumb1_expand_epilogue (void)
27145 HOST_WIDE_INT amount
;
27146 arm_stack_offsets
*offsets
;
27149 /* Naked functions don't have prologues. */
27150 if (IS_NAKED (arm_current_func_type ()))
27153 offsets
= arm_get_frame_offsets ();
27154 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
27156 if (frame_pointer_needed
)
27158 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
27159 amount
= offsets
->locals_base
- offsets
->saved_regs
;
27161 amount
-= 4 * thumb1_extra_regs_pushed (offsets
, false);
27163 gcc_assert (amount
>= 0);
27166 emit_insn (gen_blockage ());
27169 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
27170 GEN_INT (amount
)));
27173 /* r3 is always free in the epilogue. */
27174 rtx reg
= gen_rtx_REG (SImode
, LAST_ARG_REGNUM
);
27176 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
27177 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
27181 /* Emit a USE (stack_pointer_rtx), so that
27182 the stack adjustment will not be deleted. */
27183 emit_insn (gen_force_register_use (stack_pointer_rtx
));
27185 if (crtl
->profile
|| !TARGET_SCHED_PROLOG
)
27186 emit_insn (gen_blockage ());
27188 /* Emit a clobber for each insn that will be restored in the epilogue,
27189 so that flow2 will get register lifetimes correct. */
27190 for (regno
= 0; regno
< 13; regno
++)
27191 if (reg_needs_saving_p (regno
))
27192 emit_clobber (gen_rtx_REG (SImode
, regno
));
27194 if (! df_regs_ever_live_p (LR_REGNUM
))
27195 emit_use (gen_rtx_REG (SImode
, LR_REGNUM
));
27197 /* Clear all caller-saved regs that are not used to return. */
27198 if (IS_CMSE_ENTRY (arm_current_func_type ()))
27199 cmse_nonsecure_entry_clear_before_return ();
27202 /* Epilogue code for APCS frame. */
27204 arm_expand_epilogue_apcs_frame (bool really_return
)
27206 unsigned long func_type
;
27207 unsigned long saved_regs_mask
;
27210 int floats_from_frame
= 0;
27211 arm_stack_offsets
*offsets
;
27213 gcc_assert (TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
);
27214 func_type
= arm_current_func_type ();
27216 /* Get frame offsets for ARM. */
27217 offsets
= arm_get_frame_offsets ();
27218 saved_regs_mask
= offsets
->saved_regs_mask
;
27220 /* Find the offset of the floating-point save area in the frame. */
27222 = (offsets
->saved_args
27223 + arm_compute_static_chain_stack_bytes ()
27226 /* Compute how many core registers saved and how far away the floats are. */
27227 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
27228 if (saved_regs_mask
& (1 << i
))
27231 floats_from_frame
+= 4;
27234 if (TARGET_VFP_BASE
)
27237 rtx ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
27239 /* The offset is from IP_REGNUM. */
27240 int saved_size
= arm_get_vfp_saved_size ();
27241 if (saved_size
> 0)
27244 floats_from_frame
+= saved_size
;
27245 insn
= emit_insn (gen_addsi3 (ip_rtx
,
27246 hard_frame_pointer_rtx
,
27247 GEN_INT (-floats_from_frame
)));
27248 arm_add_cfa_adjust_cfa_note (insn
, -floats_from_frame
,
27249 ip_rtx
, hard_frame_pointer_rtx
);
27252 /* Generate VFP register multi-pop. */
27253 start_reg
= FIRST_VFP_REGNUM
;
27255 for (i
= FIRST_VFP_REGNUM
; i
< LAST_VFP_REGNUM
; i
+= 2)
27256 /* Look for a case where a reg does not need restoring. */
27257 if (!reg_needs_saving_p (i
) && !reg_needs_saving_p (i
+ 1))
27259 if (start_reg
!= i
)
27260 arm_emit_vfp_multi_reg_pop (start_reg
,
27261 (i
- start_reg
) / 2,
27262 gen_rtx_REG (SImode
,
27267 /* Restore the remaining regs that we have discovered (or possibly
27268 even all of them, if the conditional in the for loop never
27270 if (start_reg
!= i
)
27271 arm_emit_vfp_multi_reg_pop (start_reg
,
27272 (i
- start_reg
) / 2,
27273 gen_rtx_REG (SImode
, IP_REGNUM
));
27278 /* The frame pointer is guaranteed to be non-double-word aligned, as
27279 it is set to double-word-aligned old_stack_pointer - 4. */
27281 int lrm_count
= (num_regs
% 2) ? (num_regs
+ 2) : (num_regs
+ 1);
27283 for (i
= LAST_IWMMXT_REGNUM
; i
>= FIRST_IWMMXT_REGNUM
; i
--)
27284 if (reg_needs_saving_p (i
))
27286 rtx addr
= gen_frame_mem (V2SImode
,
27287 plus_constant (Pmode
, hard_frame_pointer_rtx
,
27289 insn
= emit_insn (gen_movsi (gen_rtx_REG (V2SImode
, i
), addr
));
27290 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_RESTORE
,
27291 gen_rtx_REG (V2SImode
, i
),
27297 /* saved_regs_mask should contain IP which contains old stack pointer
27298 at the time of activation creation. Since SP and IP are adjacent registers,
27299 we can restore the value directly into SP. */
27300 gcc_assert (saved_regs_mask
& (1 << IP_REGNUM
));
27301 saved_regs_mask
&= ~(1 << IP_REGNUM
);
27302 saved_regs_mask
|= (1 << SP_REGNUM
);
27304 /* There are two registers left in saved_regs_mask - LR and PC. We
27305 only need to restore LR (the return address), but to
27306 save time we can load it directly into PC, unless we need a
27307 special function exit sequence, or we are not really returning. */
27309 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
27310 && !crtl
->calls_eh_return
)
27311 /* Delete LR from the register mask, so that LR on
27312 the stack is loaded into the PC in the register mask. */
27313 saved_regs_mask
&= ~(1 << LR_REGNUM
);
27315 saved_regs_mask
&= ~(1 << PC_REGNUM
);
27317 num_regs
= bit_count (saved_regs_mask
);
27318 if ((offsets
->outgoing_args
!= (1 + num_regs
)) || cfun
->calls_alloca
)
27321 emit_insn (gen_blockage ());
27322 /* Unwind the stack to just below the saved registers. */
27323 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
27324 hard_frame_pointer_rtx
,
27325 GEN_INT (- 4 * num_regs
)));
27327 arm_add_cfa_adjust_cfa_note (insn
, - 4 * num_regs
,
27328 stack_pointer_rtx
, hard_frame_pointer_rtx
);
27331 arm_emit_multi_reg_pop (saved_regs_mask
);
27333 if (IS_INTERRUPT (func_type
))
27335 /* Interrupt handlers will have pushed the
27336 IP onto the stack, so restore it now. */
27338 rtx addr
= gen_rtx_MEM (SImode
,
27339 gen_rtx_POST_INC (SImode
,
27340 stack_pointer_rtx
));
27341 set_mem_alias_set (addr
, get_frame_alias_set ());
27342 insn
= emit_insn (gen_movsi (gen_rtx_REG (SImode
, IP_REGNUM
), addr
));
27343 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_RESTORE
,
27344 gen_rtx_REG (SImode
, IP_REGNUM
),
27348 if (!really_return
|| (saved_regs_mask
& (1 << PC_REGNUM
)))
27351 if (crtl
->calls_eh_return
)
27352 emit_insn (gen_addsi3 (stack_pointer_rtx
,
27354 gen_rtx_REG (SImode
, ARM_EH_STACKADJ_REGNUM
)));
27356 if (IS_STACKALIGN (func_type
))
27357 /* Restore the original stack pointer. Before prologue, the stack was
27358 realigned and the original stack pointer saved in r0. For details,
27359 see comment in arm_expand_prologue. */
27360 emit_insn (gen_movsi (stack_pointer_rtx
, gen_rtx_REG (SImode
, R0_REGNUM
)));
27362 emit_jump_insn (simple_return_rtx
);
27365 /* Generate RTL to represent ARM epilogue. Really_return is true if the
27366 function is not a sibcall. */
27368 arm_expand_epilogue (bool really_return
)
27370 unsigned long func_type
;
27371 unsigned long saved_regs_mask
;
27375 arm_stack_offsets
*offsets
;
27377 func_type
= arm_current_func_type ();
27379 /* Naked functions don't have epilogue. Hence, generate return pattern, and
27380 let output_return_instruction take care of instruction emission if any. */
27381 if (IS_NAKED (func_type
)
27382 || (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
))
27385 emit_jump_insn (simple_return_rtx
);
27389 /* If we are throwing an exception, then we really must be doing a
27390 return, so we can't tail-call. */
27391 gcc_assert (!crtl
->calls_eh_return
|| really_return
);
27393 if (TARGET_APCS_FRAME
&& frame_pointer_needed
&& TARGET_ARM
)
27395 arm_expand_epilogue_apcs_frame (really_return
);
27399 /* Get frame offsets for ARM. */
27400 offsets
= arm_get_frame_offsets ();
27401 saved_regs_mask
= offsets
->saved_regs_mask
;
27402 num_regs
= bit_count (saved_regs_mask
);
27404 if (frame_pointer_needed
)
27407 /* Restore stack pointer if necessary. */
27410 /* In ARM mode, frame pointer points to first saved register.
27411 Restore stack pointer to last saved register. */
27412 amount
= offsets
->frame
- offsets
->saved_regs
;
27414 /* Force out any pending memory operations that reference stacked data
27415 before stack de-allocation occurs. */
27416 emit_insn (gen_blockage ());
27417 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
27418 hard_frame_pointer_rtx
,
27419 GEN_INT (amount
)));
27420 arm_add_cfa_adjust_cfa_note (insn
, amount
,
27422 hard_frame_pointer_rtx
);
27424 /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not
27426 emit_insn (gen_force_register_use (stack_pointer_rtx
));
27430 /* In Thumb-2 mode, the frame pointer points to the last saved
27432 amount
= offsets
->locals_base
- offsets
->saved_regs
;
27435 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
27436 hard_frame_pointer_rtx
,
27437 GEN_INT (amount
)));
27438 arm_add_cfa_adjust_cfa_note (insn
, amount
,
27439 hard_frame_pointer_rtx
,
27440 hard_frame_pointer_rtx
);
27443 /* Force out any pending memory operations that reference stacked data
27444 before stack de-allocation occurs. */
27445 emit_insn (gen_blockage ());
27446 insn
= emit_insn (gen_movsi (stack_pointer_rtx
,
27447 hard_frame_pointer_rtx
));
27448 arm_add_cfa_adjust_cfa_note (insn
, 0,
27450 hard_frame_pointer_rtx
);
27451 /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is not
27453 emit_insn (gen_force_register_use (stack_pointer_rtx
));
27458 /* Pop off outgoing args and local frame to adjust stack pointer to
27459 last saved register. */
27460 amount
= offsets
->outgoing_args
- offsets
->saved_regs
;
27464 /* Force out any pending memory operations that reference stacked data
27465 before stack de-allocation occurs. */
27466 emit_insn (gen_blockage ());
27467 tmp
= emit_insn (gen_addsi3 (stack_pointer_rtx
,
27469 GEN_INT (amount
)));
27470 arm_add_cfa_adjust_cfa_note (tmp
, amount
,
27471 stack_pointer_rtx
, stack_pointer_rtx
);
27472 /* Emit USE(stack_pointer_rtx) to ensure that stack adjustment is
27474 emit_insn (gen_force_register_use (stack_pointer_rtx
));
27478 if (TARGET_VFP_BASE
)
27480 /* Generate VFP register multi-pop. */
27481 int end_reg
= LAST_VFP_REGNUM
+ 1;
27483 /* Scan the registers in reverse order. We need to match
27484 any groupings made in the prologue and generate matching
27485 vldm operations. The need to match groups is because,
27486 unlike pop, vldm can only do consecutive regs. */
27487 for (i
= LAST_VFP_REGNUM
- 1; i
>= FIRST_VFP_REGNUM
; i
-= 2)
27488 /* Look for a case where a reg does not need restoring. */
27489 if (!reg_needs_saving_p (i
) && !reg_needs_saving_p (i
+ 1))
27491 /* Restore the regs discovered so far (from reg+2 to
27493 if (end_reg
> i
+ 2)
27494 arm_emit_vfp_multi_reg_pop (i
+ 2,
27495 (end_reg
- (i
+ 2)) / 2,
27496 stack_pointer_rtx
);
27500 /* Restore the remaining regs that we have discovered (or possibly
27501 even all of them, if the conditional in the for loop never
27503 if (end_reg
> i
+ 2)
27504 arm_emit_vfp_multi_reg_pop (i
+ 2,
27505 (end_reg
- (i
+ 2)) / 2,
27506 stack_pointer_rtx
);
27510 for (i
= FIRST_IWMMXT_REGNUM
; i
<= LAST_IWMMXT_REGNUM
; i
++)
27511 if (reg_needs_saving_p (i
))
27514 rtx addr
= gen_rtx_MEM (V2SImode
,
27515 gen_rtx_POST_INC (SImode
,
27516 stack_pointer_rtx
));
27517 set_mem_alias_set (addr
, get_frame_alias_set ());
27518 insn
= emit_insn (gen_movsi (gen_rtx_REG (V2SImode
, i
), addr
));
27519 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_RESTORE
,
27520 gen_rtx_REG (V2SImode
, i
),
27522 arm_add_cfa_adjust_cfa_note (insn
, UNITS_PER_WORD
,
27523 stack_pointer_rtx
, stack_pointer_rtx
);
27526 if (saved_regs_mask
)
27529 bool return_in_pc
= false;
27531 if (ARM_FUNC_TYPE (func_type
) != ARM_FT_INTERWORKED
27532 && (TARGET_ARM
|| ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
)
27533 && !IS_CMSE_ENTRY (func_type
)
27534 && !IS_STACKALIGN (func_type
)
27536 && crtl
->args
.pretend_args_size
== 0
27537 && saved_regs_mask
& (1 << LR_REGNUM
)
27538 && !crtl
->calls_eh_return
)
27540 saved_regs_mask
&= ~(1 << LR_REGNUM
);
27541 saved_regs_mask
|= (1 << PC_REGNUM
);
27542 return_in_pc
= true;
27545 if (num_regs
== 1 && (!IS_INTERRUPT (func_type
) || !return_in_pc
))
27547 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
27548 if (saved_regs_mask
& (1 << i
))
27550 rtx addr
= gen_rtx_MEM (SImode
,
27551 gen_rtx_POST_INC (SImode
,
27552 stack_pointer_rtx
));
27553 set_mem_alias_set (addr
, get_frame_alias_set ());
27555 if (i
== PC_REGNUM
)
27557 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
27558 XVECEXP (insn
, 0, 0) = ret_rtx
;
27559 XVECEXP (insn
, 0, 1) = gen_rtx_SET (gen_rtx_REG (SImode
, i
),
27561 RTX_FRAME_RELATED_P (XVECEXP (insn
, 0, 1)) = 1;
27562 insn
= emit_jump_insn (insn
);
27566 insn
= emit_insn (gen_movsi (gen_rtx_REG (SImode
, i
),
27568 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_RESTORE
,
27569 gen_rtx_REG (SImode
, i
),
27571 arm_add_cfa_adjust_cfa_note (insn
, UNITS_PER_WORD
,
27573 stack_pointer_rtx
);
27580 && current_tune
->prefer_ldrd_strd
27581 && !optimize_function_for_size_p (cfun
))
27584 thumb2_emit_ldrd_pop (saved_regs_mask
);
27585 else if (TARGET_ARM
&& !IS_INTERRUPT (func_type
))
27586 arm_emit_ldrd_pop (saved_regs_mask
);
27588 arm_emit_multi_reg_pop (saved_regs_mask
);
27591 arm_emit_multi_reg_pop (saved_regs_mask
);
27599 = crtl
->args
.pretend_args_size
+ arm_compute_static_chain_stack_bytes();
27603 rtx dwarf
= NULL_RTX
;
27605 emit_insn (gen_addsi3 (stack_pointer_rtx
,
27607 GEN_INT (amount
)));
27609 RTX_FRAME_RELATED_P (tmp
) = 1;
27611 if (cfun
->machine
->uses_anonymous_args
)
27613 /* Restore pretend args. Refer arm_expand_prologue on how to save
27614 pretend_args in stack. */
27615 int num_regs
= crtl
->args
.pretend_args_size
/ 4;
27616 saved_regs_mask
= (0xf0 >> num_regs
) & 0xf;
27617 for (j
= 0, i
= 0; j
< num_regs
; i
++)
27618 if (saved_regs_mask
& (1 << i
))
27620 rtx reg
= gen_rtx_REG (SImode
, i
);
27621 dwarf
= alloc_reg_note (REG_CFA_RESTORE
, reg
, dwarf
);
27624 REG_NOTES (tmp
) = dwarf
;
27626 arm_add_cfa_adjust_cfa_note (tmp
, amount
,
27627 stack_pointer_rtx
, stack_pointer_rtx
);
27630 if (IS_CMSE_ENTRY (func_type
))
27632 /* CMSE_ENTRY always returns. */
27633 gcc_assert (really_return
);
27634 /* Clear all caller-saved regs that are not used to return. */
27635 cmse_nonsecure_entry_clear_before_return ();
27637 /* Armv8.1-M Mainline nonsecure entry: restore FPCXTNS from stack using
27639 if (TARGET_HAVE_FPCXT_CMSE
)
27643 insn
= emit_insn (gen_pop_fpsysreg_insn (stack_pointer_rtx
,
27644 GEN_INT (FPCXTNS_ENUM
)));
27645 rtx dwarf
= gen_rtx_SET (stack_pointer_rtx
,
27646 plus_constant (Pmode
, stack_pointer_rtx
, 4));
27647 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, dwarf
);
27648 RTX_FRAME_RELATED_P (insn
) = 1;
27652 if (!really_return
)
27655 if (crtl
->calls_eh_return
)
27656 emit_insn (gen_addsi3 (stack_pointer_rtx
,
27658 gen_rtx_REG (SImode
, ARM_EH_STACKADJ_REGNUM
)));
27660 if (IS_STACKALIGN (func_type
))
27661 /* Restore the original stack pointer. Before prologue, the stack was
27662 realigned and the original stack pointer saved in r0. For details,
27663 see comment in arm_expand_prologue. */
27664 emit_insn (gen_movsi (stack_pointer_rtx
, gen_rtx_REG (SImode
, R0_REGNUM
)));
27666 emit_jump_insn (simple_return_rtx
);
27669 /* Implementation of insn prologue_thumb1_interwork. This is the first
27670 "instruction" of a function called in ARM mode. Swap to thumb mode. */
27673 thumb1_output_interwork (void)
27676 FILE *f
= asm_out_file
;
27678 gcc_assert (MEM_P (DECL_RTL (current_function_decl
)));
27679 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0))
27681 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
27683 /* Generate code sequence to switch us into Thumb mode. */
27684 /* The .code 32 directive has already been emitted by
27685 ASM_DECLARE_FUNCTION_NAME. */
27686 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
27687 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
27689 /* Generate a label, so that the debugger will notice the
27690 change in instruction sets. This label is also used by
27691 the assembler to bypass the ARM code when this function
27692 is called from a Thumb encoded function elsewhere in the
27693 same file. Hence the definition of STUB_NAME here must
27694 agree with the definition in gas/config/tc-arm.c. */
27696 #define STUB_NAME ".real_start_of"
27698 fprintf (f
, "\t.code\t16\n");
27700 if (arm_dllexport_name_p (name
))
27701 name
= arm_strip_name_encoding (name
);
27703 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
27704 fprintf (f
, "\t.thumb_func\n");
27705 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
27710 /* Handle the case of a double word load into a low register from
27711 a computed memory address. The computed address may involve a
27712 register which is overwritten by the load. */
27714 thumb_load_double_from_address (rtx
*operands
)
27722 gcc_assert (REG_P (operands
[0]));
27723 gcc_assert (MEM_P (operands
[1]));
27725 /* Get the memory address. */
27726 addr
= XEXP (operands
[1], 0);
27728 /* Work out how the memory address is computed. */
27729 switch (GET_CODE (addr
))
27732 operands
[2] = adjust_address (operands
[1], SImode
, 4);
27734 if (REGNO (operands
[0]) == REGNO (addr
))
27736 output_asm_insn ("ldr\t%H0, %2", operands
);
27737 output_asm_insn ("ldr\t%0, %1", operands
);
27741 output_asm_insn ("ldr\t%0, %1", operands
);
27742 output_asm_insn ("ldr\t%H0, %2", operands
);
27747 /* Compute <address> + 4 for the high order load. */
27748 operands
[2] = adjust_address (operands
[1], SImode
, 4);
27750 output_asm_insn ("ldr\t%0, %1", operands
);
27751 output_asm_insn ("ldr\t%H0, %2", operands
);
27755 arg1
= XEXP (addr
, 0);
27756 arg2
= XEXP (addr
, 1);
27758 if (CONSTANT_P (arg1
))
27759 base
= arg2
, offset
= arg1
;
27761 base
= arg1
, offset
= arg2
;
27763 gcc_assert (REG_P (base
));
27765 /* Catch the case of <address> = <reg> + <reg> */
27766 if (REG_P (offset
))
27768 int reg_offset
= REGNO (offset
);
27769 int reg_base
= REGNO (base
);
27770 int reg_dest
= REGNO (operands
[0]);
27772 /* Add the base and offset registers together into the
27773 higher destination register. */
27774 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
27775 reg_dest
+ 1, reg_base
, reg_offset
);
27777 /* Load the lower destination register from the address in
27778 the higher destination register. */
27779 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
27780 reg_dest
, reg_dest
+ 1);
27782 /* Load the higher destination register from its own address
27784 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
27785 reg_dest
+ 1, reg_dest
+ 1);
27789 /* Compute <address> + 4 for the high order load. */
27790 operands
[2] = adjust_address (operands
[1], SImode
, 4);
27792 /* If the computed address is held in the low order register
27793 then load the high order register first, otherwise always
27794 load the low order register first. */
27795 if (REGNO (operands
[0]) == REGNO (base
))
27797 output_asm_insn ("ldr\t%H0, %2", operands
);
27798 output_asm_insn ("ldr\t%0, %1", operands
);
27802 output_asm_insn ("ldr\t%0, %1", operands
);
27803 output_asm_insn ("ldr\t%H0, %2", operands
);
27809 /* With no registers to worry about we can just load the value
27811 operands
[2] = adjust_address (operands
[1], SImode
, 4);
27813 output_asm_insn ("ldr\t%H0, %2", operands
);
27814 output_asm_insn ("ldr\t%0, %1", operands
);
27818 gcc_unreachable ();
27825 thumb_output_move_mem_multiple (int n
, rtx
*operands
)
27830 if (REGNO (operands
[4]) > REGNO (operands
[5]))
27831 std::swap (operands
[4], operands
[5]);
27833 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
27834 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
27838 if (REGNO (operands
[4]) > REGNO (operands
[5]))
27839 std::swap (operands
[4], operands
[5]);
27840 if (REGNO (operands
[5]) > REGNO (operands
[6]))
27841 std::swap (operands
[5], operands
[6]);
27842 if (REGNO (operands
[4]) > REGNO (operands
[5]))
27843 std::swap (operands
[4], operands
[5]);
27845 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
27846 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
27850 gcc_unreachable ();
27856 /* Output a call-via instruction for thumb state. */
27858 thumb_call_via_reg (rtx reg
)
27860 int regno
= REGNO (reg
);
27863 gcc_assert (regno
< LR_REGNUM
);
27865 /* If we are in the normal text section we can use a single instance
27866 per compilation unit. If we are doing function sections, then we need
27867 an entry per section, since we can't rely on reachability. */
27868 if (in_section
== text_section
)
27870 thumb_call_reg_needed
= 1;
27872 if (thumb_call_via_label
[regno
] == NULL
)
27873 thumb_call_via_label
[regno
] = gen_label_rtx ();
27874 labelp
= thumb_call_via_label
+ regno
;
27878 if (cfun
->machine
->call_via
[regno
] == NULL
)
27879 cfun
->machine
->call_via
[regno
] = gen_label_rtx ();
27880 labelp
= cfun
->machine
->call_via
+ regno
;
27883 output_asm_insn ("bl\t%a0", labelp
);
27887 /* Routines for generating rtl. */
27889 thumb_expand_cpymemqi (rtx
*operands
)
27891 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
27892 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
27893 HOST_WIDE_INT len
= INTVAL (operands
[2]);
27894 HOST_WIDE_INT offset
= 0;
27898 emit_insn (gen_cpymem12b (out
, in
, out
, in
));
27904 emit_insn (gen_cpymem8b (out
, in
, out
, in
));
27910 rtx reg
= gen_reg_rtx (SImode
);
27911 emit_insn (gen_movsi (reg
, gen_rtx_MEM (SImode
, in
)));
27912 emit_insn (gen_movsi (gen_rtx_MEM (SImode
, out
), reg
));
27919 rtx reg
= gen_reg_rtx (HImode
);
27920 emit_insn (gen_movhi (reg
, gen_rtx_MEM (HImode
,
27921 plus_constant (Pmode
, in
,
27923 emit_insn (gen_movhi (gen_rtx_MEM (HImode
, plus_constant (Pmode
, out
,
27932 rtx reg
= gen_reg_rtx (QImode
);
27933 emit_insn (gen_movqi (reg
, gen_rtx_MEM (QImode
,
27934 plus_constant (Pmode
, in
,
27936 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (Pmode
, out
,
27943 thumb_reload_out_hi (rtx
*operands
)
27945 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
27948 /* Return the length of a function name prefix
27949 that starts with the character 'c'. */
27951 arm_get_strip_length (int c
)
27955 ARM_NAME_ENCODING_LENGTHS
27960 /* Return a pointer to a function's name with any
27961 and all prefix encodings stripped from it. */
27963 arm_strip_name_encoding (const char *name
)
27967 while ((skip
= arm_get_strip_length (* name
)))
27973 /* If there is a '*' anywhere in the name's prefix, then
27974 emit the stripped name verbatim, otherwise prepend an
27975 underscore if leading underscores are being used. */
27977 arm_asm_output_labelref (FILE *stream
, const char *name
)
27982 while ((skip
= arm_get_strip_length (* name
)))
27984 verbatim
|= (*name
== '*');
27989 fputs (name
, stream
);
27991 asm_fprintf (stream
, "%U%s", name
);
27994 /* This function is used to emit an EABI tag and its associated value.
27995 We emit the numerical value of the tag in case the assembler does not
27996 support textual tags. (Eg gas prior to 2.20). If requested we include
27997 the tag name in a comment so that anyone reading the assembler output
27998 will know which tag is being set.
28000 This function is not static because arm-c.c needs it too. */
28003 arm_emit_eabi_attribute (const char *name
, int num
, int val
)
28005 asm_fprintf (asm_out_file
, "\t.eabi_attribute %d, %d", num
, val
);
28006 if (flag_verbose_asm
|| flag_debug_asm
)
28007 asm_fprintf (asm_out_file
, "\t%s %s", ASM_COMMENT_START
, name
);
28008 asm_fprintf (asm_out_file
, "\n");
28011 /* This function is used to print CPU tuning information as comment
28012 in assembler file. Pointers are not printed for now. */
28015 arm_print_tune_info (void)
28017 asm_fprintf (asm_out_file
, "\t" ASM_COMMENT_START
".tune parameters\n");
28018 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
"constant_limit:\t%d\n",
28019 current_tune
->constant_limit
);
28020 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
28021 "max_insns_skipped:\t%d\n", current_tune
->max_insns_skipped
);
28022 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
28023 "prefetch.num_slots:\t%d\n", current_tune
->prefetch
.num_slots
);
28024 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
28025 "prefetch.l1_cache_size:\t%d\n",
28026 current_tune
->prefetch
.l1_cache_size
);
28027 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
28028 "prefetch.l1_cache_line_size:\t%d\n",
28029 current_tune
->prefetch
.l1_cache_line_size
);
28030 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
28031 "prefer_constant_pool:\t%d\n",
28032 (int) current_tune
->prefer_constant_pool
);
28033 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
28034 "branch_cost:\t(s:speed, p:predictable)\n");
28035 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
"\t\ts&p\tcost\n");
28036 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
"\t\t00\t%d\n",
28037 current_tune
->branch_cost (false, false));
28038 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
"\t\t01\t%d\n",
28039 current_tune
->branch_cost (false, true));
28040 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
"\t\t10\t%d\n",
28041 current_tune
->branch_cost (true, false));
28042 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
"\t\t11\t%d\n",
28043 current_tune
->branch_cost (true, true));
28044 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
28045 "prefer_ldrd_strd:\t%d\n",
28046 (int) current_tune
->prefer_ldrd_strd
);
28047 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
28048 "logical_op_non_short_circuit:\t[%d,%d]\n",
28049 (int) current_tune
->logical_op_non_short_circuit_thumb
,
28050 (int) current_tune
->logical_op_non_short_circuit_arm
);
28051 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
28052 "disparage_flag_setting_t16_encodings:\t%d\n",
28053 (int) current_tune
->disparage_flag_setting_t16_encodings
);
28054 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
28055 "string_ops_prefer_neon:\t%d\n",
28056 (int) current_tune
->string_ops_prefer_neon
);
28057 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
28058 "max_insns_inline_memset:\t%d\n",
28059 current_tune
->max_insns_inline_memset
);
28060 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
"fusible_ops:\t%u\n",
28061 current_tune
->fusible_ops
);
28062 asm_fprintf (asm_out_file
, "\t\t" ASM_COMMENT_START
"sched_autopref:\t%d\n",
28063 (int) current_tune
->sched_autopref
);
28066 /* Print .arch and .arch_extension directives corresponding to the
28067 current architecture configuration. */
28069 arm_print_asm_arch_directives ()
28071 const arch_option
*arch
28072 = arm_parse_arch_option_name (all_architectures
, "-march",
28073 arm_active_target
.arch_name
);
28074 auto_sbitmap
opt_bits (isa_num_bits
);
28078 asm_fprintf (asm_out_file
, "\t.arch %s\n", arm_active_target
.arch_name
);
28079 arm_last_printed_arch_string
= arm_active_target
.arch_name
;
28080 if (!arch
->common
.extensions
)
28083 for (const struct cpu_arch_extension
*opt
= arch
->common
.extensions
;
28089 arm_initialize_isa (opt_bits
, opt
->isa_bits
);
28091 /* For the cases "-march=armv8.1-m.main+mve -mfloat-abi=soft" and
28092 "-march=armv8.1-m.main+mve.fp -mfloat-abi=soft" MVE and MVE with
28093 floating point instructions is disabled. So the following check
28094 restricts the printing of ".arch_extension mve" and
28095 ".arch_extension fp" (for mve.fp) in the assembly file. MVE needs
28096 this special behaviour because the feature bit "mve" and
28097 "mve_float" are not part of "fpu bits", so they are not cleared
28098 when -mfloat-abi=soft (i.e nofp) but the marco TARGET_HAVE_MVE and
28099 TARGET_HAVE_MVE_FLOAT are disabled. */
28100 if ((bitmap_bit_p (opt_bits
, isa_bit_mve
) && !TARGET_HAVE_MVE
)
28101 || (bitmap_bit_p (opt_bits
, isa_bit_mve_float
)
28102 && !TARGET_HAVE_MVE_FLOAT
))
28105 /* If every feature bit of this option is set in the target
28106 ISA specification, print out the option name. However,
28107 don't print anything if all the bits are part of the
28108 FPU specification. */
28109 if (bitmap_subset_p (opt_bits
, arm_active_target
.isa
)
28110 && !bitmap_subset_p (opt_bits
, isa_all_fpubits_internal
))
28111 asm_fprintf (asm_out_file
, "\t.arch_extension %s\n", opt
->name
);
28117 arm_file_start (void)
28123 /* We don't have a specified CPU. Use the architecture to
28126 Note: it might be better to do this unconditionally, then the
28127 assembler would not need to know about all new CPU names as
28129 if (!arm_active_target
.core_name
)
28131 /* armv7ve doesn't support any extensions. */
28132 if (strcmp (arm_active_target
.arch_name
, "armv7ve") == 0)
28134 /* Keep backward compatability for assemblers
28135 which don't support armv7ve. */
28136 asm_fprintf (asm_out_file
, "\t.arch armv7-a\n");
28137 asm_fprintf (asm_out_file
, "\t.arch_extension virt\n");
28138 asm_fprintf (asm_out_file
, "\t.arch_extension idiv\n");
28139 asm_fprintf (asm_out_file
, "\t.arch_extension sec\n");
28140 asm_fprintf (asm_out_file
, "\t.arch_extension mp\n");
28141 arm_last_printed_arch_string
= "armv7ve";
28144 arm_print_asm_arch_directives ();
28146 else if (strncmp (arm_active_target
.core_name
, "generic", 7) == 0)
28148 asm_fprintf (asm_out_file
, "\t.arch %s\n",
28149 arm_active_target
.core_name
+ 8);
28150 arm_last_printed_arch_string
= arm_active_target
.core_name
+ 8;
28154 const char* truncated_name
28155 = arm_rewrite_selected_cpu (arm_active_target
.core_name
);
28156 if (bitmap_bit_p (arm_active_target
.isa
, isa_bit_quirk_no_asmcpu
))
28157 asm_fprintf (asm_out_file
, "\t.eabi_attribute 5, \"%s\"\n",
28160 asm_fprintf (asm_out_file
, "\t.cpu %s\n", truncated_name
);
28163 if (print_tune_info
)
28164 arm_print_tune_info ();
28166 if (TARGET_HARD_FLOAT
&& TARGET_VFP_SINGLE
)
28167 arm_emit_eabi_attribute ("Tag_ABI_HardFP_use", 27, 1);
28169 if (TARGET_HARD_FLOAT_ABI
)
28170 arm_emit_eabi_attribute ("Tag_ABI_VFP_args", 28, 1);
28172 /* Some of these attributes only apply when the corresponding features
28173 are used. However we don't have any easy way of figuring this out.
28174 Conservatively record the setting that would have been used. */
28176 if (flag_rounding_math
)
28177 arm_emit_eabi_attribute ("Tag_ABI_FP_rounding", 19, 1);
28179 if (!flag_unsafe_math_optimizations
)
28181 arm_emit_eabi_attribute ("Tag_ABI_FP_denormal", 20, 1);
28182 arm_emit_eabi_attribute ("Tag_ABI_FP_exceptions", 21, 1);
28184 if (flag_signaling_nans
)
28185 arm_emit_eabi_attribute ("Tag_ABI_FP_user_exceptions", 22, 1);
28187 arm_emit_eabi_attribute ("Tag_ABI_FP_number_model", 23,
28188 flag_finite_math_only
? 1 : 3);
28190 arm_emit_eabi_attribute ("Tag_ABI_align8_needed", 24, 1);
28191 arm_emit_eabi_attribute ("Tag_ABI_align8_preserved", 25, 1);
28192 arm_emit_eabi_attribute ("Tag_ABI_enum_size", 26,
28193 flag_short_enums
? 1 : 2);
28195 /* Tag_ABI_optimization_goals. */
28198 else if (optimize
>= 2)
28204 arm_emit_eabi_attribute ("Tag_ABI_optimization_goals", 30, val
);
28206 arm_emit_eabi_attribute ("Tag_CPU_unaligned_access", 34,
28209 if (arm_fp16_format
)
28210 arm_emit_eabi_attribute ("Tag_ABI_FP_16bit_format", 38,
28211 (int) arm_fp16_format
);
28213 if (arm_lang_output_object_attributes_hook
)
28214 arm_lang_output_object_attributes_hook();
28217 default_file_start ();
28221 arm_file_end (void)
28225 if (NEED_INDICATE_EXEC_STACK
)
28226 /* Add .note.GNU-stack. */
28227 file_end_indicate_exec_stack ();
28229 if (! thumb_call_reg_needed
)
28232 switch_to_section (text_section
);
28233 asm_fprintf (asm_out_file
, "\t.code 16\n");
28234 ASM_OUTPUT_ALIGN (asm_out_file
, 1);
28236 for (regno
= 0; regno
< LR_REGNUM
; regno
++)
28238 rtx label
= thumb_call_via_label
[regno
];
28242 targetm
.asm_out
.internal_label (asm_out_file
, "L",
28243 CODE_LABEL_NUMBER (label
));
28244 asm_fprintf (asm_out_file
, "\tbx\t%r\n", regno
);
28250 /* Symbols in the text segment can be accessed without indirecting via the
28251 constant pool; it may take an extra binary operation, but this is still
28252 faster than indirecting via memory. Don't do this when not optimizing,
28253 since we won't be calculating al of the offsets necessary to do this
28257 arm_encode_section_info (tree decl
, rtx rtl
, int first
)
28259 if (optimize
> 0 && TREE_CONSTANT (decl
))
28260 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
28262 default_encode_section_info (decl
, rtl
, first
);
28264 #endif /* !ARM_PE */
28267 arm_internal_label (FILE *stream
, const char *prefix
, unsigned long labelno
)
28269 if (arm_ccfsm_state
== 3 && (unsigned) arm_target_label
== labelno
28270 && !strcmp (prefix
, "L"))
28272 arm_ccfsm_state
= 0;
28273 arm_target_insn
= NULL
;
28275 default_internal_label (stream
, prefix
, labelno
);
28278 /* Define classes to generate code as RTL or output asm to a file.
28279 Using templates then allows to use the same code to output code
28280 sequences in the two formats. */
28281 class thumb1_const_rtl
28284 thumb1_const_rtl (rtx dst
) : dst (dst
) {}
28286 void mov (HOST_WIDE_INT val
)
28288 emit_set_insn (dst
, GEN_INT (val
));
28291 void add (HOST_WIDE_INT val
)
28293 emit_set_insn (dst
, gen_rtx_PLUS (SImode
, dst
, GEN_INT (val
)));
28296 void ashift (HOST_WIDE_INT shift
)
28298 emit_set_insn (dst
, gen_rtx_ASHIFT (SImode
, dst
, GEN_INT (shift
)));
28303 emit_set_insn (dst
, gen_rtx_NEG (SImode
, dst
));
28310 class thumb1_const_print
28313 thumb1_const_print (FILE *f
, int regno
)
28316 dst_regname
= reg_names
[regno
];
28319 void mov (HOST_WIDE_INT val
)
28321 asm_fprintf (t_file
, "\tmovs\t%s, #" HOST_WIDE_INT_PRINT_DEC
"\n",
28325 void add (HOST_WIDE_INT val
)
28327 asm_fprintf (t_file
, "\tadds\t%s, #" HOST_WIDE_INT_PRINT_DEC
"\n",
28331 void ashift (HOST_WIDE_INT shift
)
28333 asm_fprintf (t_file
, "\tlsls\t%s, #" HOST_WIDE_INT_PRINT_DEC
"\n",
28334 dst_regname
, shift
);
28339 asm_fprintf (t_file
, "\trsbs\t%s, #0\n", dst_regname
);
28344 const char *dst_regname
;
28347 /* Emit a sequence of movs/adds/shift to produce a 32-bit constant.
28348 Avoid generating useless code when one of the bytes is zero. */
28351 thumb1_gen_const_int_1 (T dst
, HOST_WIDE_INT op1
)
28353 bool mov_done_p
= false;
28354 unsigned HOST_WIDE_INT val
= op1
;
28358 gcc_assert (op1
== trunc_int_for_mode (op1
, SImode
));
28366 /* For negative numbers with the first nine bits set, build the
28367 opposite of OP1, then negate it, it's generally shorter and not
28369 if ((val
& 0xFF800000) == 0xFF800000)
28371 thumb1_gen_const_int_1 (dst
, -op1
);
28376 /* In the general case, we need 7 instructions to build
28377 a 32 bits constant (1 movs, 3 lsls, 3 adds). We can
28378 do better if VAL is small enough, or
28379 right-shiftable by a suitable amount. If the
28380 right-shift enables to encode at least one less byte,
28381 it's worth it: we save a adds and a lsls at the
28382 expense of a final lsls. */
28383 int final_shift
= number_of_first_bit_set (val
);
28385 int leading_zeroes
= clz_hwi (val
);
28386 int number_of_bytes_needed
28387 = ((HOST_BITS_PER_WIDE_INT
- 1 - leading_zeroes
)
28388 / BITS_PER_UNIT
) + 1;
28389 int number_of_bytes_needed2
28390 = ((HOST_BITS_PER_WIDE_INT
- 1 - leading_zeroes
- final_shift
)
28391 / BITS_PER_UNIT
) + 1;
28393 if (number_of_bytes_needed2
< number_of_bytes_needed
)
28394 val
>>= final_shift
;
28398 /* If we are in a very small range, we can use either a single movs
28404 unsigned HOST_WIDE_INT high
= val
- 255;
28412 if (final_shift
> 0)
28413 dst
.ashift (final_shift
);
28417 /* General case, emit upper 3 bytes as needed. */
28418 for (i
= 0; i
< 3; i
++)
28420 unsigned HOST_WIDE_INT byte
= (val
>> (8 * (3 - i
))) & 0xff;
28424 /* We are about to emit new bits, stop accumulating a
28425 shift amount, and left-shift only if we have already
28426 emitted some upper bits. */
28429 dst
.ashift (shift
);
28435 /* Stop accumulating shift amount since we've just
28436 emitted some bits. */
28446 /* Emit lower byte. */
28448 dst
.mov (val
& 0xff);
28451 dst
.ashift (shift
);
28453 dst
.add (val
& 0xff);
28456 if (final_shift
> 0)
28457 dst
.ashift (final_shift
);
28461 /* Proxies for thumb1.md, since the thumb1_const_print and
28462 thumb1_const_rtl classes are not exported. */
28464 thumb1_gen_const_int_rtl (rtx dst
, HOST_WIDE_INT op1
)
28466 thumb1_const_rtl
t (dst
);
28467 thumb1_gen_const_int_1 (t
, op1
);
28471 thumb1_gen_const_int_print (rtx dst
, HOST_WIDE_INT op1
)
28473 thumb1_const_print
t (asm_out_file
, REGNO (dst
));
28474 thumb1_gen_const_int_1 (t
, op1
);
28477 /* Output code to add DELTA to the first argument, and then jump
28478 to FUNCTION. Used for C++ multiple inheritance. */
28481 arm_thumb1_mi_thunk (FILE *file
, tree
, HOST_WIDE_INT delta
,
28482 HOST_WIDE_INT
, tree function
)
28484 static int thunk_label
= 0;
28487 int mi_delta
= delta
;
28488 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
28490 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
)
28493 mi_delta
= - mi_delta
;
28495 final_start_function (emit_barrier (), file
, 1);
28499 int labelno
= thunk_label
++;
28500 ASM_GENERATE_INTERNAL_LABEL (label
, "LTHUMBFUNC", labelno
);
28501 /* Thunks are entered in arm mode when available. */
28502 if (TARGET_THUMB1_ONLY
)
28504 /* push r3 so we can use it as a temporary. */
28505 /* TODO: Omit this save if r3 is not used. */
28506 fputs ("\tpush {r3}\n", file
);
28508 /* With -mpure-code, we cannot load the address from the
28509 constant pool: we build it explicitly. */
28510 if (target_pure_code
)
28512 fputs ("\tmovs\tr3, #:upper8_15:#", file
);
28513 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
28514 fputc ('\n', file
);
28515 fputs ("\tlsls r3, #8\n", file
);
28516 fputs ("\tadds\tr3, #:upper0_7:#", file
);
28517 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
28518 fputc ('\n', file
);
28519 fputs ("\tlsls r3, #8\n", file
);
28520 fputs ("\tadds\tr3, #:lower8_15:#", file
);
28521 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
28522 fputc ('\n', file
);
28523 fputs ("\tlsls r3, #8\n", file
);
28524 fputs ("\tadds\tr3, #:lower0_7:#", file
);
28525 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
28526 fputc ('\n', file
);
28529 fputs ("\tldr\tr3, ", file
);
28533 fputs ("\tldr\tr12, ", file
);
28536 if (!target_pure_code
)
28538 assemble_name (file
, label
);
28539 fputc ('\n', file
);
28544 /* If we are generating PIC, the ldr instruction below loads
28545 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
28546 the address of the add + 8, so we have:
28548 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
28551 Note that we have "+ 1" because some versions of GNU ld
28552 don't set the low bit of the result for R_ARM_REL32
28553 relocations against thumb function symbols.
28554 On ARMv6M this is +4, not +8. */
28555 ASM_GENERATE_INTERNAL_LABEL (labelpc
, "LTHUNKPC", labelno
);
28556 assemble_name (file
, labelpc
);
28557 fputs (":\n", file
);
28558 if (TARGET_THUMB1_ONLY
)
28560 /* This is 2 insns after the start of the thunk, so we know it
28561 is 4-byte aligned. */
28562 fputs ("\tadd\tr3, pc, r3\n", file
);
28563 fputs ("\tmov r12, r3\n", file
);
28566 fputs ("\tadd\tr12, pc, r12\n", file
);
28568 else if (TARGET_THUMB1_ONLY
)
28569 fputs ("\tmov r12, r3\n", file
);
28571 if (TARGET_THUMB1_ONLY
)
28573 if (mi_delta
> 255)
28575 /* With -mpure-code, we cannot load MI_DELTA from the
28576 constant pool: we build it explicitly. */
28577 if (target_pure_code
)
28579 thumb1_const_print
r3 (file
, 3);
28580 thumb1_gen_const_int_1 (r3
, mi_delta
);
28584 fputs ("\tldr\tr3, ", file
);
28585 assemble_name (file
, label
);
28586 fputs ("+4\n", file
);
28588 asm_fprintf (file
, "\t%ss\t%r, %r, r3\n",
28589 mi_op
, this_regno
, this_regno
);
28591 else if (mi_delta
!= 0)
28593 /* Thumb1 unified syntax requires s suffix in instruction name when
28594 one of the operands is immediate. */
28595 asm_fprintf (file
, "\t%ss\t%r, %r, #%d\n",
28596 mi_op
, this_regno
, this_regno
,
28602 /* TODO: Use movw/movt for large constants when available. */
28603 while (mi_delta
!= 0)
28605 if ((mi_delta
& (3 << shift
)) == 0)
28609 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
28610 mi_op
, this_regno
, this_regno
,
28611 mi_delta
& (0xff << shift
));
28612 mi_delta
&= ~(0xff << shift
);
28619 if (TARGET_THUMB1_ONLY
)
28620 fputs ("\tpop\t{r3}\n", file
);
28622 fprintf (file
, "\tbx\tr12\n");
28624 /* With -mpure-code, we don't need to emit literals for the
28625 function address and delta since we emitted code to build
28627 if (!target_pure_code
)
28629 ASM_OUTPUT_ALIGN (file
, 2);
28630 assemble_name (file
, label
);
28631 fputs (":\n", file
);
28634 /* Output ".word .LTHUNKn-[3,7]-.LTHUNKPCn". */
28635 rtx tem
= XEXP (DECL_RTL (function
), 0);
28636 /* For TARGET_THUMB1_ONLY the thunk is in Thumb mode, so the PC
28637 pipeline offset is four rather than eight. Adjust the offset
28639 tem
= plus_constant (GET_MODE (tem
), tem
,
28640 TARGET_THUMB1_ONLY
? -3 : -7);
28641 tem
= gen_rtx_MINUS (GET_MODE (tem
),
28643 gen_rtx_SYMBOL_REF (Pmode
,
28644 ggc_strdup (labelpc
)));
28645 assemble_integer (tem
, 4, BITS_PER_WORD
, 1);
28648 /* Output ".word .LTHUNKn". */
28649 assemble_integer (XEXP (DECL_RTL (function
), 0), 4, BITS_PER_WORD
, 1);
28651 if (TARGET_THUMB1_ONLY
&& mi_delta
> 255)
28652 assemble_integer (GEN_INT (mi_delta
), 4, BITS_PER_WORD
, 1);
28657 fputs ("\tb\t", file
);
28658 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
28659 if (NEED_PLT_RELOC
)
28660 fputs ("(PLT)", file
);
28661 fputc ('\n', file
);
28664 final_end_function ();
28667 /* MI thunk handling for TARGET_32BIT. */
28670 arm32_output_mi_thunk (FILE *file
, tree
, HOST_WIDE_INT delta
,
28671 HOST_WIDE_INT vcall_offset
, tree function
)
28673 const bool long_call_p
= arm_is_long_call_p (function
);
28675 /* On ARM, this_regno is R0 or R1 depending on
28676 whether the function returns an aggregate or not.
28678 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)),
28680 ? R1_REGNUM
: R0_REGNUM
);
28682 rtx temp
= gen_rtx_REG (Pmode
, IP_REGNUM
);
28683 rtx this_rtx
= gen_rtx_REG (Pmode
, this_regno
);
28684 reload_completed
= 1;
28685 emit_note (NOTE_INSN_PROLOGUE_END
);
28687 /* Add DELTA to THIS_RTX. */
28689 arm_split_constant (PLUS
, Pmode
, NULL_RTX
,
28690 delta
, this_rtx
, this_rtx
, false);
28692 /* Add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
28693 if (vcall_offset
!= 0)
28695 /* Load *THIS_RTX. */
28696 emit_move_insn (temp
, gen_rtx_MEM (Pmode
, this_rtx
));
28697 /* Compute *THIS_RTX + VCALL_OFFSET. */
28698 arm_split_constant (PLUS
, Pmode
, NULL_RTX
, vcall_offset
, temp
, temp
,
28700 /* Compute *(*THIS_RTX + VCALL_OFFSET). */
28701 emit_move_insn (temp
, gen_rtx_MEM (Pmode
, temp
));
28702 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp
));
28705 /* Generate a tail call to the target function. */
28706 if (!TREE_USED (function
))
28708 assemble_external (function
);
28709 TREE_USED (function
) = 1;
28711 rtx funexp
= XEXP (DECL_RTL (function
), 0);
28714 emit_move_insn (temp
, funexp
);
28717 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
28718 rtx_insn
*insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
, NULL_RTX
));
28719 SIBLING_CALL_P (insn
) = 1;
28722 /* Indirect calls require a bit of fixup in PIC mode. */
28725 split_all_insns_noflow ();
28729 insn
= get_insns ();
28730 shorten_branches (insn
);
28731 final_start_function (insn
, file
, 1);
28732 final (insn
, file
, 1);
28733 final_end_function ();
28735 /* Stop pretending this is a post-reload pass. */
28736 reload_completed
= 0;
28739 /* Output code to add DELTA to the first argument, and then jump
28740 to FUNCTION. Used for C++ multiple inheritance. */
28743 arm_output_mi_thunk (FILE *file
, tree thunk
, HOST_WIDE_INT delta
,
28744 HOST_WIDE_INT vcall_offset
, tree function
)
28746 const char *fnname
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk
));
28748 assemble_start_function (thunk
, fnname
);
28750 arm32_output_mi_thunk (file
, thunk
, delta
, vcall_offset
, function
);
28752 arm_thumb1_mi_thunk (file
, thunk
, delta
, vcall_offset
, function
);
28753 assemble_end_function (thunk
, fnname
);
28757 arm_emit_vector_const (FILE *file
, rtx x
)
28760 const char * pattern
;
28762 gcc_assert (GET_CODE (x
) == CONST_VECTOR
);
28764 switch (GET_MODE (x
))
28766 case E_V2SImode
: pattern
= "%08x"; break;
28767 case E_V4HImode
: pattern
= "%04x"; break;
28768 case E_V8QImode
: pattern
= "%02x"; break;
28769 default: gcc_unreachable ();
28772 fprintf (file
, "0x");
28773 for (i
= CONST_VECTOR_NUNITS (x
); i
--;)
28777 element
= CONST_VECTOR_ELT (x
, i
);
28778 fprintf (file
, pattern
, INTVAL (element
));
28784 /* Emit a fp16 constant appropriately padded to occupy a 4-byte word.
28785 HFmode constant pool entries are actually loaded with ldr. */
28787 arm_emit_fp16_const (rtx c
)
28791 bits
= real_to_target (NULL
, CONST_DOUBLE_REAL_VALUE (c
), HFmode
);
28792 if (WORDS_BIG_ENDIAN
)
28793 assemble_zeros (2);
28794 assemble_integer (GEN_INT (bits
), 2, BITS_PER_WORD
, 1);
28795 if (!WORDS_BIG_ENDIAN
)
28796 assemble_zeros (2);
28800 arm_output_load_gr (rtx
*operands
)
28807 if (!MEM_P (operands
[1])
28808 || GET_CODE (sum
= XEXP (operands
[1], 0)) != PLUS
28809 || !REG_P (reg
= XEXP (sum
, 0))
28810 || !CONST_INT_P (offset
= XEXP (sum
, 1))
28811 || ((INTVAL (offset
) < 1024) && (INTVAL (offset
) > -1024)))
28812 return "wldrw%?\t%0, %1";
28814 /* Fix up an out-of-range load of a GR register. */
28815 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg
);
28816 wcgr
= operands
[0];
28818 output_asm_insn ("ldr%?\t%0, %1", operands
);
28820 operands
[0] = wcgr
;
28822 output_asm_insn ("tmcr%?\t%0, %1", operands
);
28823 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg
);
28828 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
28830 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
28831 named arg and all anonymous args onto the stack.
28832 XXX I know the prologue shouldn't be pushing registers, but it is faster
28836 arm_setup_incoming_varargs (cumulative_args_t pcum_v
,
28837 const function_arg_info
&arg
,
28839 int second_time ATTRIBUTE_UNUSED
)
28841 CUMULATIVE_ARGS
*pcum
= get_cumulative_args (pcum_v
);
28844 cfun
->machine
->uses_anonymous_args
= 1;
28845 if (pcum
->pcs_variant
<= ARM_PCS_AAPCS_LOCAL
)
28847 nregs
= pcum
->aapcs_ncrn
;
28850 int res
= arm_needs_doubleword_align (arg
.mode
, arg
.type
);
28851 if (res
< 0 && warn_psabi
)
28852 inform (input_location
, "parameter passing for argument of "
28853 "type %qT changed in GCC 7.1", arg
.type
);
28857 if (res
> 1 && warn_psabi
)
28858 inform (input_location
,
28859 "parameter passing for argument of type "
28860 "%qT changed in GCC 9.1", arg
.type
);
28865 nregs
= pcum
->nregs
;
28867 if (nregs
< NUM_ARG_REGS
)
28868 *pretend_size
= (NUM_ARG_REGS
- nregs
) * UNITS_PER_WORD
;
28871 /* We can't rely on the caller doing the proper promotion when
28872 using APCS or ATPCS. */
28875 arm_promote_prototypes (const_tree t ATTRIBUTE_UNUSED
)
28877 return !TARGET_AAPCS_BASED
;
28880 static machine_mode
28881 arm_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
28883 int *punsignedp ATTRIBUTE_UNUSED
,
28884 const_tree fntype ATTRIBUTE_UNUSED
,
28885 int for_return ATTRIBUTE_UNUSED
)
28887 if (GET_MODE_CLASS (mode
) == MODE_INT
28888 && GET_MODE_SIZE (mode
) < 4)
28896 arm_default_short_enums (void)
28898 return ARM_DEFAULT_SHORT_ENUMS
;
28902 /* AAPCS requires that anonymous bitfields affect structure alignment. */
28905 arm_align_anon_bitfield (void)
28907 return TARGET_AAPCS_BASED
;
28911 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
28914 arm_cxx_guard_type (void)
28916 return TARGET_AAPCS_BASED
? integer_type_node
: long_long_integer_type_node
;
28920 /* The EABI says test the least significant bit of a guard variable. */
28923 arm_cxx_guard_mask_bit (void)
28925 return TARGET_AAPCS_BASED
;
28929 /* The EABI specifies that all array cookies are 8 bytes long. */
28932 arm_get_cookie_size (tree type
)
28936 if (!TARGET_AAPCS_BASED
)
28937 return default_cxx_get_cookie_size (type
);
28939 size
= build_int_cst (sizetype
, 8);
28944 /* The EABI says that array cookies should also contain the element size. */
28947 arm_cookie_has_size (void)
28949 return TARGET_AAPCS_BASED
;
28953 /* The EABI says constructors and destructors should return a pointer to
28954 the object constructed/destroyed. */
28957 arm_cxx_cdtor_returns_this (void)
28959 return TARGET_AAPCS_BASED
;
28962 /* The EABI says that an inline function may never be the key
28966 arm_cxx_key_method_may_be_inline (void)
28968 return !TARGET_AAPCS_BASED
;
28972 arm_cxx_determine_class_data_visibility (tree decl
)
28974 if (!TARGET_AAPCS_BASED
28975 || !TARGET_DLLIMPORT_DECL_ATTRIBUTES
)
28978 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
28979 is exported. However, on systems without dynamic vague linkage,
28980 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
28981 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
&& DECL_COMDAT (decl
))
28982 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
28984 DECL_VISIBILITY (decl
) = VISIBILITY_DEFAULT
;
28985 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
28989 arm_cxx_class_data_always_comdat (void)
28991 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
28992 vague linkage if the class has no key function. */
28993 return !TARGET_AAPCS_BASED
;
28997 /* The EABI says __aeabi_atexit should be used to register static
29001 arm_cxx_use_aeabi_atexit (void)
29003 return TARGET_AAPCS_BASED
;
29008 arm_set_return_address (rtx source
, rtx scratch
)
29010 arm_stack_offsets
*offsets
;
29011 HOST_WIDE_INT delta
;
29013 unsigned long saved_regs
;
29015 offsets
= arm_get_frame_offsets ();
29016 saved_regs
= offsets
->saved_regs_mask
;
29018 if ((saved_regs
& (1 << LR_REGNUM
)) == 0)
29019 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
29022 if (frame_pointer_needed
)
29023 addr
= plus_constant (Pmode
, hard_frame_pointer_rtx
, -4);
29026 /* LR will be the first saved register. */
29027 delta
= offsets
->outgoing_args
- (offsets
->frame
+ 4);
29032 emit_insn (gen_addsi3 (scratch
, stack_pointer_rtx
,
29033 GEN_INT (delta
& ~4095)));
29038 addr
= stack_pointer_rtx
;
29040 addr
= plus_constant (Pmode
, addr
, delta
);
29043 /* The store needs to be marked to prevent DSE from deleting
29044 it as dead if it is based on fp. */
29045 mem
= gen_frame_mem (Pmode
, addr
);
29046 MEM_VOLATILE_P (mem
) = true;
29047 emit_move_insn (mem
, source
);
29053 thumb_set_return_address (rtx source
, rtx scratch
)
29055 arm_stack_offsets
*offsets
;
29056 HOST_WIDE_INT delta
;
29057 HOST_WIDE_INT limit
;
29060 unsigned long mask
;
29064 offsets
= arm_get_frame_offsets ();
29065 mask
= offsets
->saved_regs_mask
;
29066 if (mask
& (1 << LR_REGNUM
))
29069 /* Find the saved regs. */
29070 if (frame_pointer_needed
)
29072 delta
= offsets
->soft_frame
- offsets
->saved_args
;
29073 reg
= THUMB_HARD_FRAME_POINTER_REGNUM
;
29079 delta
= offsets
->outgoing_args
- offsets
->saved_args
;
29082 /* Allow for the stack frame. */
29083 if (TARGET_THUMB1
&& TARGET_BACKTRACE
)
29085 /* The link register is always the first saved register. */
29088 /* Construct the address. */
29089 addr
= gen_rtx_REG (SImode
, reg
);
29092 emit_insn (gen_movsi (scratch
, GEN_INT (delta
)));
29093 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
29097 addr
= plus_constant (Pmode
, addr
, delta
);
29099 /* The store needs to be marked to prevent DSE from deleting
29100 it as dead if it is based on fp. */
29101 mem
= gen_frame_mem (Pmode
, addr
);
29102 MEM_VOLATILE_P (mem
) = true;
29103 emit_move_insn (mem
, source
);
29106 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNUM
), source
);
29109 /* Implements target hook vector_mode_supported_p. */
29111 arm_vector_mode_supported_p (machine_mode mode
)
29113 /* Neon also supports V2SImode, etc. listed in the clause below. */
29114 if (TARGET_NEON
&& (mode
== V2SFmode
|| mode
== V4SImode
|| mode
== V8HImode
29115 || mode
== V4HFmode
|| mode
== V16QImode
|| mode
== V4SFmode
29116 || mode
== V2DImode
|| mode
== V8HFmode
|| mode
== V4BFmode
29117 || mode
== V8BFmode
))
29120 if ((TARGET_NEON
|| TARGET_IWMMXT
)
29121 && ((mode
== V2SImode
)
29122 || (mode
== V4HImode
)
29123 || (mode
== V8QImode
)))
29126 if (TARGET_INT_SIMD
&& (mode
== V4UQQmode
|| mode
== V4QQmode
29127 || mode
== V2UHQmode
|| mode
== V2HQmode
|| mode
== V2UHAmode
29128 || mode
== V2HAmode
))
29131 if (TARGET_HAVE_MVE
29132 && (mode
== V2DImode
|| mode
== V4SImode
|| mode
== V8HImode
29133 || mode
== V16QImode
))
29136 if (TARGET_HAVE_MVE_FLOAT
29137 && (mode
== V2DFmode
|| mode
== V4SFmode
|| mode
== V8HFmode
))
29143 /* Implements target hook array_mode_supported_p. */
29146 arm_array_mode_supported_p (machine_mode mode
,
29147 unsigned HOST_WIDE_INT nelems
)
29149 /* We don't want to enable interleaved loads and stores for BYTES_BIG_ENDIAN
29150 for now, as the lane-swapping logic needs to be extended in the expanders.
29151 See PR target/82518. */
29152 if (TARGET_NEON
&& !BYTES_BIG_ENDIAN
29153 && (VALID_NEON_DREG_MODE (mode
) || VALID_NEON_QREG_MODE (mode
))
29154 && (nelems
>= 2 && nelems
<= 4))
29157 if (TARGET_HAVE_MVE
&& !BYTES_BIG_ENDIAN
29158 && VALID_MVE_MODE (mode
) && (nelems
== 2 || nelems
== 4))
29164 /* Use the option -mvectorize-with-neon-double to override the use of quardword
29165 registers when autovectorizing for Neon, at least until multiple vector
29166 widths are supported properly by the middle-end. */
29168 static machine_mode
29169 arm_preferred_simd_mode (scalar_mode mode
)
29175 return TARGET_NEON_VECTORIZE_DOUBLE
? V4HFmode
: V8HFmode
;
29177 return TARGET_NEON_VECTORIZE_DOUBLE
? V2SFmode
: V4SFmode
;
29179 return TARGET_NEON_VECTORIZE_DOUBLE
? V2SImode
: V4SImode
;
29181 return TARGET_NEON_VECTORIZE_DOUBLE
? V4HImode
: V8HImode
;
29183 return TARGET_NEON_VECTORIZE_DOUBLE
? V8QImode
: V16QImode
;
29185 if (!TARGET_NEON_VECTORIZE_DOUBLE
)
29192 if (TARGET_REALLY_IWMMXT
)
29205 if (TARGET_HAVE_MVE
)
29218 if (TARGET_HAVE_MVE_FLOAT
)
29232 /* Implement TARGET_CLASS_LIKELY_SPILLED_P.
29234 We need to define this for LO_REGS on Thumb-1. Otherwise we can end up
29235 using r0-r4 for function arguments, r7 for the stack frame and don't have
29236 enough left over to do doubleword arithmetic. For Thumb-2 all the
29237 potentially problematic instructions accept high registers so this is not
29238 necessary. Care needs to be taken to avoid adding new Thumb-2 patterns
29239 that require many low registers. */
29241 arm_class_likely_spilled_p (reg_class_t rclass
)
29243 if ((TARGET_THUMB1
&& rclass
== LO_REGS
)
29244 || rclass
== CC_REG
)
29250 /* Implements target hook small_register_classes_for_mode_p. */
29252 arm_small_register_classes_for_mode_p (machine_mode mode ATTRIBUTE_UNUSED
)
29254 return TARGET_THUMB1
;
29257 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
29258 ARM insns and therefore guarantee that the shift count is modulo 256.
29259 DImode shifts (those implemented by lib1funcs.S or by optabs.c)
29260 guarantee no particular behavior for out-of-range counts. */
29262 static unsigned HOST_WIDE_INT
29263 arm_shift_truncation_mask (machine_mode mode
)
29265 return mode
== SImode
? 255 : 0;
29269 /* Map internal gcc register numbers to DWARF2 register numbers. */
29272 arm_dbx_register_number (unsigned int regno
)
29277 if (IS_VFP_REGNUM (regno
))
29279 /* See comment in arm_dwarf_register_span. */
29280 if (VFP_REGNO_OK_FOR_SINGLE (regno
))
29281 return 64 + regno
- FIRST_VFP_REGNUM
;
29283 return 256 + (regno
- FIRST_VFP_REGNUM
) / 2;
29286 if (IS_IWMMXT_GR_REGNUM (regno
))
29287 return 104 + regno
- FIRST_IWMMXT_GR_REGNUM
;
29289 if (IS_IWMMXT_REGNUM (regno
))
29290 return 112 + regno
- FIRST_IWMMXT_REGNUM
;
29292 return DWARF_FRAME_REGISTERS
;
29295 /* Dwarf models VFPv3 registers as 32 64-bit registers.
29296 GCC models tham as 64 32-bit registers, so we need to describe this to
29297 the DWARF generation code. Other registers can use the default. */
29299 arm_dwarf_register_span (rtx rtl
)
29307 regno
= REGNO (rtl
);
29308 if (!IS_VFP_REGNUM (regno
))
29311 /* XXX FIXME: The EABI defines two VFP register ranges:
29312 64-95: Legacy VFPv2 numbering for S0-S31 (obsolescent)
29314 The recommended encoding for S0-S31 is a DW_OP_bit_piece of the
29315 corresponding D register. Until GDB supports this, we shall use the
29316 legacy encodings. We also use these encodings for D0-D15 for
29317 compatibility with older debuggers. */
29318 mode
= GET_MODE (rtl
);
29319 if (GET_MODE_SIZE (mode
) < 8)
29322 if (VFP_REGNO_OK_FOR_SINGLE (regno
))
29324 nregs
= GET_MODE_SIZE (mode
) / 4;
29325 for (i
= 0; i
< nregs
; i
+= 2)
29326 if (TARGET_BIG_END
)
29328 parts
[i
] = gen_rtx_REG (SImode
, regno
+ i
+ 1);
29329 parts
[i
+ 1] = gen_rtx_REG (SImode
, regno
+ i
);
29333 parts
[i
] = gen_rtx_REG (SImode
, regno
+ i
);
29334 parts
[i
+ 1] = gen_rtx_REG (SImode
, regno
+ i
+ 1);
29339 nregs
= GET_MODE_SIZE (mode
) / 8;
29340 for (i
= 0; i
< nregs
; i
++)
29341 parts
[i
] = gen_rtx_REG (DImode
, regno
+ i
);
29344 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nregs
, parts
));
29347 #if ARM_UNWIND_INFO
29348 /* Emit unwind directives for a store-multiple instruction or stack pointer
29349 push during alignment.
29350 These should only ever be generated by the function prologue code, so
29351 expect them to have a particular form.
29352 The store-multiple instruction sometimes pushes pc as the last register,
29353 although it should not be tracked into unwind information, or for -Os
29354 sometimes pushes some dummy registers before first register that needs
29355 to be tracked in unwind information; such dummy registers are there just
29356 to avoid separate stack adjustment, and will not be restored in the
29360 arm_unwind_emit_sequence (FILE * asm_out_file
, rtx p
)
29363 HOST_WIDE_INT offset
;
29364 HOST_WIDE_INT nregs
;
29368 unsigned padfirst
= 0, padlast
= 0;
29371 e
= XVECEXP (p
, 0, 0);
29372 gcc_assert (GET_CODE (e
) == SET
);
29374 /* First insn will adjust the stack pointer. */
29375 gcc_assert (GET_CODE (e
) == SET
29376 && REG_P (SET_DEST (e
))
29377 && REGNO (SET_DEST (e
)) == SP_REGNUM
29378 && GET_CODE (SET_SRC (e
)) == PLUS
);
29380 offset
= -INTVAL (XEXP (SET_SRC (e
), 1));
29381 nregs
= XVECLEN (p
, 0) - 1;
29382 gcc_assert (nregs
);
29384 reg
= REGNO (SET_SRC (XVECEXP (p
, 0, 1)));
29387 /* For -Os dummy registers can be pushed at the beginning to
29388 avoid separate stack pointer adjustment. */
29389 e
= XVECEXP (p
, 0, 1);
29390 e
= XEXP (SET_DEST (e
), 0);
29391 if (GET_CODE (e
) == PLUS
)
29392 padfirst
= INTVAL (XEXP (e
, 1));
29393 gcc_assert (padfirst
== 0 || optimize_size
);
29394 /* The function prologue may also push pc, but not annotate it as it is
29395 never restored. We turn this into a stack pointer adjustment. */
29396 e
= XVECEXP (p
, 0, nregs
);
29397 e
= XEXP (SET_DEST (e
), 0);
29398 if (GET_CODE (e
) == PLUS
)
29399 padlast
= offset
- INTVAL (XEXP (e
, 1)) - 4;
29401 padlast
= offset
- 4;
29402 gcc_assert (padlast
== 0 || padlast
== 4);
29404 fprintf (asm_out_file
, "\t.pad #4\n");
29406 fprintf (asm_out_file
, "\t.save {");
29408 else if (IS_VFP_REGNUM (reg
))
29411 fprintf (asm_out_file
, "\t.vsave {");
29414 /* Unknown register type. */
29415 gcc_unreachable ();
29417 /* If the stack increment doesn't match the size of the saved registers,
29418 something has gone horribly wrong. */
29419 gcc_assert (offset
== padfirst
+ nregs
* reg_size
+ padlast
);
29423 /* The remaining insns will describe the stores. */
29424 for (i
= 1; i
<= nregs
; i
++)
29426 /* Expect (set (mem <addr>) (reg)).
29427 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
29428 e
= XVECEXP (p
, 0, i
);
29429 gcc_assert (GET_CODE (e
) == SET
29430 && MEM_P (SET_DEST (e
))
29431 && REG_P (SET_SRC (e
)));
29433 reg
= REGNO (SET_SRC (e
));
29434 gcc_assert (reg
>= lastreg
);
29437 fprintf (asm_out_file
, ", ");
29438 /* We can't use %r for vfp because we need to use the
29439 double precision register names. */
29440 if (IS_VFP_REGNUM (reg
))
29441 asm_fprintf (asm_out_file
, "d%d", (reg
- FIRST_VFP_REGNUM
) / 2);
29443 asm_fprintf (asm_out_file
, "%r", reg
);
29447 /* Check that the addresses are consecutive. */
29448 e
= XEXP (SET_DEST (e
), 0);
29449 if (GET_CODE (e
) == PLUS
)
29450 gcc_assert (REG_P (XEXP (e
, 0))
29451 && REGNO (XEXP (e
, 0)) == SP_REGNUM
29452 && CONST_INT_P (XEXP (e
, 1))
29453 && offset
== INTVAL (XEXP (e
, 1)));
29457 && REGNO (e
) == SP_REGNUM
);
29458 offset
+= reg_size
;
29461 fprintf (asm_out_file
, "}\n");
29463 fprintf (asm_out_file
, "\t.pad #%d\n", padfirst
);
29466 /* Emit unwind directives for a SET. */
29469 arm_unwind_emit_set (FILE * asm_out_file
, rtx p
)
29477 switch (GET_CODE (e0
))
29480 /* Pushing a single register. */
29481 if (GET_CODE (XEXP (e0
, 0)) != PRE_DEC
29482 || !REG_P (XEXP (XEXP (e0
, 0), 0))
29483 || REGNO (XEXP (XEXP (e0
, 0), 0)) != SP_REGNUM
)
29486 asm_fprintf (asm_out_file
, "\t.save ");
29487 if (IS_VFP_REGNUM (REGNO (e1
)))
29488 asm_fprintf(asm_out_file
, "{d%d}\n",
29489 (REGNO (e1
) - FIRST_VFP_REGNUM
) / 2);
29491 asm_fprintf(asm_out_file
, "{%r}\n", REGNO (e1
));
29495 if (REGNO (e0
) == SP_REGNUM
)
29497 /* A stack increment. */
29498 if (GET_CODE (e1
) != PLUS
29499 || !REG_P (XEXP (e1
, 0))
29500 || REGNO (XEXP (e1
, 0)) != SP_REGNUM
29501 || !CONST_INT_P (XEXP (e1
, 1)))
29504 asm_fprintf (asm_out_file
, "\t.pad #%wd\n",
29505 -INTVAL (XEXP (e1
, 1)));
29507 else if (REGNO (e0
) == HARD_FRAME_POINTER_REGNUM
)
29509 HOST_WIDE_INT offset
;
29511 if (GET_CODE (e1
) == PLUS
)
29513 if (!REG_P (XEXP (e1
, 0))
29514 || !CONST_INT_P (XEXP (e1
, 1)))
29516 reg
= REGNO (XEXP (e1
, 0));
29517 offset
= INTVAL (XEXP (e1
, 1));
29518 asm_fprintf (asm_out_file
, "\t.setfp %r, %r, #%wd\n",
29519 HARD_FRAME_POINTER_REGNUM
, reg
,
29522 else if (REG_P (e1
))
29525 asm_fprintf (asm_out_file
, "\t.setfp %r, %r\n",
29526 HARD_FRAME_POINTER_REGNUM
, reg
);
29531 else if (REG_P (e1
) && REGNO (e1
) == SP_REGNUM
)
29533 /* Move from sp to reg. */
29534 asm_fprintf (asm_out_file
, "\t.movsp %r\n", REGNO (e0
));
29536 else if (GET_CODE (e1
) == PLUS
29537 && REG_P (XEXP (e1
, 0))
29538 && REGNO (XEXP (e1
, 0)) == SP_REGNUM
29539 && CONST_INT_P (XEXP (e1
, 1)))
29541 /* Set reg to offset from sp. */
29542 asm_fprintf (asm_out_file
, "\t.movsp %r, #%d\n",
29543 REGNO (e0
), (int)INTVAL(XEXP (e1
, 1)));
29555 /* Emit unwind directives for the given insn. */
29558 arm_unwind_emit (FILE * asm_out_file
, rtx_insn
*insn
)
29561 bool handled_one
= false;
29563 if (arm_except_unwind_info (&global_options
) != UI_TARGET
)
29566 if (!(flag_unwind_tables
|| crtl
->uses_eh_lsda
)
29567 && (TREE_NOTHROW (current_function_decl
)
29568 || crtl
->all_throwers_are_sibcalls
))
29571 if (NOTE_P (insn
) || !RTX_FRAME_RELATED_P (insn
))
29574 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
29576 switch (REG_NOTE_KIND (note
))
29578 case REG_FRAME_RELATED_EXPR
:
29579 pat
= XEXP (note
, 0);
29582 case REG_CFA_REGISTER
:
29583 pat
= XEXP (note
, 0);
29586 pat
= PATTERN (insn
);
29587 if (GET_CODE (pat
) == PARALLEL
)
29588 pat
= XVECEXP (pat
, 0, 0);
29591 /* Only emitted for IS_STACKALIGN re-alignment. */
29596 src
= SET_SRC (pat
);
29597 dest
= SET_DEST (pat
);
29599 gcc_assert (src
== stack_pointer_rtx
);
29600 reg
= REGNO (dest
);
29601 asm_fprintf (asm_out_file
, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n",
29604 handled_one
= true;
29607 /* The INSN is generated in epilogue. It is set as RTX_FRAME_RELATED_P
29608 to get correct dwarf information for shrink-wrap. We should not
29609 emit unwind information for it because these are used either for
29610 pretend arguments or notes to adjust sp and restore registers from
29612 case REG_CFA_DEF_CFA
:
29613 case REG_CFA_ADJUST_CFA
:
29614 case REG_CFA_RESTORE
:
29617 case REG_CFA_EXPRESSION
:
29618 case REG_CFA_OFFSET
:
29619 /* ??? Only handling here what we actually emit. */
29620 gcc_unreachable ();
29628 pat
= PATTERN (insn
);
29631 switch (GET_CODE (pat
))
29634 arm_unwind_emit_set (asm_out_file
, pat
);
29638 /* Store multiple. */
29639 arm_unwind_emit_sequence (asm_out_file
, pat
);
29648 /* Output a reference from a function exception table to the type_info
29649 object X. The EABI specifies that the symbol should be relocated by
29650 an R_ARM_TARGET2 relocation. */
29653 arm_output_ttype (rtx x
)
29655 fputs ("\t.word\t", asm_out_file
);
29656 output_addr_const (asm_out_file
, x
);
29657 /* Use special relocations for symbol references. */
29658 if (!CONST_INT_P (x
))
29659 fputs ("(TARGET2)", asm_out_file
);
29660 fputc ('\n', asm_out_file
);
29665 /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */
29668 arm_asm_emit_except_personality (rtx personality
)
29670 fputs ("\t.personality\t", asm_out_file
);
29671 output_addr_const (asm_out_file
, personality
);
29672 fputc ('\n', asm_out_file
);
29674 #endif /* ARM_UNWIND_INFO */
29676 /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */
29679 arm_asm_init_sections (void)
29681 #if ARM_UNWIND_INFO
29682 exception_section
= get_unnamed_section (0, output_section_asm_op
,
29684 #endif /* ARM_UNWIND_INFO */
29686 #ifdef OBJECT_FORMAT_ELF
29687 if (target_pure_code
)
29688 text_section
->unnamed
.data
= "\t.section .text,\"0x20000006\",%progbits";
29692 /* Output unwind directives for the start/end of a function. */
29695 arm_output_fn_unwind (FILE * f
, bool prologue
)
29697 if (arm_except_unwind_info (&global_options
) != UI_TARGET
)
29701 fputs ("\t.fnstart\n", f
);
29704 /* If this function will never be unwound, then mark it as such.
29705 The came condition is used in arm_unwind_emit to suppress
29706 the frame annotations. */
29707 if (!(flag_unwind_tables
|| crtl
->uses_eh_lsda
)
29708 && (TREE_NOTHROW (current_function_decl
)
29709 || crtl
->all_throwers_are_sibcalls
))
29710 fputs("\t.cantunwind\n", f
);
29712 fputs ("\t.fnend\n", f
);
29717 arm_emit_tls_decoration (FILE *fp
, rtx x
)
29719 enum tls_reloc reloc
;
29722 val
= XVECEXP (x
, 0, 0);
29723 reloc
= (enum tls_reloc
) INTVAL (XVECEXP (x
, 0, 1));
29725 output_addr_const (fp
, val
);
29730 fputs ("(tlsgd)", fp
);
29732 case TLS_GD32_FDPIC
:
29733 fputs ("(tlsgd_fdpic)", fp
);
29736 fputs ("(tlsldm)", fp
);
29738 case TLS_LDM32_FDPIC
:
29739 fputs ("(tlsldm_fdpic)", fp
);
29742 fputs ("(tlsldo)", fp
);
29745 fputs ("(gottpoff)", fp
);
29747 case TLS_IE32_FDPIC
:
29748 fputs ("(gottpoff_fdpic)", fp
);
29751 fputs ("(tpoff)", fp
);
29754 fputs ("(tlsdesc)", fp
);
29757 gcc_unreachable ();
29766 fputs (" + (. - ", fp
);
29767 output_addr_const (fp
, XVECEXP (x
, 0, 2));
29768 /* For DESCSEQ the 3rd operand encodes thumbness, and is added */
29769 fputs (reloc
== TLS_DESCSEQ
? " + " : " - ", fp
);
29770 output_addr_const (fp
, XVECEXP (x
, 0, 3));
29780 /* ARM implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
29783 arm_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
29785 gcc_assert (size
== 4);
29786 fputs ("\t.word\t", file
);
29787 output_addr_const (file
, x
);
29788 fputs ("(tlsldo)", file
);
29791 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
29794 arm_output_addr_const_extra (FILE *fp
, rtx x
)
29796 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLS
)
29797 return arm_emit_tls_decoration (fp
, x
);
29798 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_PIC_LABEL
)
29801 int labelno
= INTVAL (XVECEXP (x
, 0, 0));
29803 ASM_GENERATE_INTERNAL_LABEL (label
, "LPIC", labelno
);
29804 assemble_name_raw (fp
, label
);
29808 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_GOTSYM_OFF
)
29810 assemble_name (fp
, "_GLOBAL_OFFSET_TABLE_");
29814 output_addr_const (fp
, XVECEXP (x
, 0, 0));
29818 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_SYMBOL_OFFSET
)
29820 output_addr_const (fp
, XVECEXP (x
, 0, 0));
29824 output_addr_const (fp
, XVECEXP (x
, 0, 1));
29828 else if (GET_CODE (x
) == CONST_VECTOR
)
29829 return arm_emit_vector_const (fp
, x
);
29834 /* Output assembly for a shift instruction.
29835 SET_FLAGS determines how the instruction modifies the condition codes.
29836 0 - Do not set condition codes.
29837 1 - Set condition codes.
29838 2 - Use smallest instruction. */
29840 arm_output_shift(rtx
* operands
, int set_flags
)
29843 static const char flag_chars
[3] = {'?', '.', '!'};
29848 c
= flag_chars
[set_flags
];
29849 shift
= shift_op(operands
[3], &val
);
29853 operands
[2] = GEN_INT(val
);
29854 sprintf (pattern
, "%s%%%c\t%%0, %%1, %%2", shift
, c
);
29857 sprintf (pattern
, "mov%%%c\t%%0, %%1", c
);
29859 output_asm_insn (pattern
, operands
);
29863 /* Output assembly for a WMMX immediate shift instruction. */
29865 arm_output_iwmmxt_shift_immediate (const char *insn_name
, rtx
*operands
, bool wror_or_wsra
)
29867 int shift
= INTVAL (operands
[2]);
29869 machine_mode opmode
= GET_MODE (operands
[0]);
29871 gcc_assert (shift
>= 0);
29873 /* If the shift value in the register versions is > 63 (for D qualifier),
29874 31 (for W qualifier) or 15 (for H qualifier). */
29875 if (((opmode
== V4HImode
) && (shift
> 15))
29876 || ((opmode
== V2SImode
) && (shift
> 31))
29877 || ((opmode
== DImode
) && (shift
> 63)))
29881 sprintf (templ
, "%s\t%%0, %%1, #%d", insn_name
, 32);
29882 output_asm_insn (templ
, operands
);
29883 if (opmode
== DImode
)
29885 sprintf (templ
, "%s\t%%0, %%0, #%d", insn_name
, 32);
29886 output_asm_insn (templ
, operands
);
29891 /* The destination register will contain all zeros. */
29892 sprintf (templ
, "wzero\t%%0");
29893 output_asm_insn (templ
, operands
);
29898 if ((opmode
== DImode
) && (shift
> 32))
29900 sprintf (templ
, "%s\t%%0, %%1, #%d", insn_name
, 32);
29901 output_asm_insn (templ
, operands
);
29902 sprintf (templ
, "%s\t%%0, %%0, #%d", insn_name
, shift
- 32);
29903 output_asm_insn (templ
, operands
);
29907 sprintf (templ
, "%s\t%%0, %%1, #%d", insn_name
, shift
);
29908 output_asm_insn (templ
, operands
);
29913 /* Output assembly for a WMMX tinsr instruction. */
29915 arm_output_iwmmxt_tinsr (rtx
*operands
)
29917 int mask
= INTVAL (operands
[3]);
29920 int units
= mode_nunits
[GET_MODE (operands
[0])];
29921 gcc_assert ((mask
& (mask
- 1)) == 0);
29922 for (i
= 0; i
< units
; ++i
)
29924 if ((mask
& 0x01) == 1)
29930 gcc_assert (i
< units
);
29932 switch (GET_MODE (operands
[0]))
29935 sprintf (templ
, "tinsrb%%?\t%%0, %%2, #%d", i
);
29938 sprintf (templ
, "tinsrh%%?\t%%0, %%2, #%d", i
);
29941 sprintf (templ
, "tinsrw%%?\t%%0, %%2, #%d", i
);
29944 gcc_unreachable ();
29947 output_asm_insn (templ
, operands
);
29952 /* Output a Thumb-1 casesi dispatch sequence. */
29954 thumb1_output_casesi (rtx
*operands
)
29956 rtx diff_vec
= PATTERN (NEXT_INSN (as_a
<rtx_insn
*> (operands
[0])));
29958 gcc_assert (GET_CODE (diff_vec
) == ADDR_DIFF_VEC
);
29960 switch (GET_MODE(diff_vec
))
29963 return (ADDR_DIFF_VEC_FLAGS (diff_vec
).offset_unsigned
?
29964 "bl\t%___gnu_thumb1_case_uqi" : "bl\t%___gnu_thumb1_case_sqi");
29966 return (ADDR_DIFF_VEC_FLAGS (diff_vec
).offset_unsigned
?
29967 "bl\t%___gnu_thumb1_case_uhi" : "bl\t%___gnu_thumb1_case_shi");
29969 return "bl\t%___gnu_thumb1_case_si";
29971 gcc_unreachable ();
29975 /* Output a Thumb-2 casesi instruction. */
29977 thumb2_output_casesi (rtx
*operands
)
29979 rtx diff_vec
= PATTERN (NEXT_INSN (as_a
<rtx_insn
*> (operands
[2])));
29981 gcc_assert (GET_CODE (diff_vec
) == ADDR_DIFF_VEC
);
29983 output_asm_insn ("cmp\t%0, %1", operands
);
29984 output_asm_insn ("bhi\t%l3", operands
);
29985 switch (GET_MODE(diff_vec
))
29988 return "tbb\t[%|pc, %0]";
29990 return "tbh\t[%|pc, %0, lsl #1]";
29994 output_asm_insn ("adr\t%4, %l2", operands
);
29995 output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands
);
29996 output_asm_insn ("add\t%4, %4, %5", operands
);
30001 output_asm_insn ("adr\t%4, %l2", operands
);
30002 return "ldr\t%|pc, [%4, %0, lsl #2]";
30005 gcc_unreachable ();
30009 /* Implement TARGET_SCHED_ISSUE_RATE. Lookup the issue rate in the
30010 per-core tuning structs. */
30012 arm_issue_rate (void)
30014 return current_tune
->issue_rate
;
30017 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
30019 arm_sched_variable_issue (FILE *, int, rtx_insn
*insn
, int more
)
30021 if (DEBUG_INSN_P (insn
))
30024 rtx_code code
= GET_CODE (PATTERN (insn
));
30025 if (code
== USE
|| code
== CLOBBER
)
30028 if (get_attr_type (insn
) == TYPE_NO_INSN
)
30034 /* Return how many instructions should scheduler lookahead to choose the
30037 arm_first_cycle_multipass_dfa_lookahead (void)
30039 int issue_rate
= arm_issue_rate ();
30041 return issue_rate
> 1 && !sched_fusion
? issue_rate
: 0;
30044 /* Enable modeling of L2 auto-prefetcher. */
30046 arm_first_cycle_multipass_dfa_lookahead_guard (rtx_insn
*insn
, int ready_index
)
30048 return autopref_multipass_dfa_lookahead_guard (insn
, ready_index
);
30052 arm_mangle_type (const_tree type
)
30054 /* The ARM ABI documents (10th October 2008) say that "__va_list"
30055 has to be managled as if it is in the "std" namespace. */
30056 if (TARGET_AAPCS_BASED
30057 && lang_hooks
.types_compatible_p (CONST_CAST_TREE (type
), va_list_type
))
30058 return "St9__va_list";
30060 /* Half-precision floating point types. */
30061 if (TREE_CODE (type
) == REAL_TYPE
&& TYPE_PRECISION (type
) == 16)
30063 if (TYPE_MODE (type
) == BFmode
)
30069 /* Try mangling as a Neon type, TYPE_NAME is non-NULL if this is a
30071 if (TYPE_NAME (type
) != NULL
)
30072 return arm_mangle_builtin_type (type
);
30074 /* Use the default mangling. */
30078 /* Order of allocation of core registers for Thumb: this allocation is
30079 written over the corresponding initial entries of the array
30080 initialized with REG_ALLOC_ORDER. We allocate all low registers
30081 first. Saving and restoring a low register is usually cheaper than
30082 using a call-clobbered high register. */
30084 static const int thumb_core_reg_alloc_order
[] =
30086 3, 2, 1, 0, 4, 5, 6, 7,
30087 12, 14, 8, 9, 10, 11
30090 /* Adjust register allocation order when compiling for Thumb. */
30093 arm_order_regs_for_local_alloc (void)
30095 const int arm_reg_alloc_order
[] = REG_ALLOC_ORDER
;
30096 memcpy(reg_alloc_order
, arm_reg_alloc_order
, sizeof (reg_alloc_order
));
30098 memcpy (reg_alloc_order
, thumb_core_reg_alloc_order
,
30099 sizeof (thumb_core_reg_alloc_order
));
30102 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
30105 arm_frame_pointer_required (void)
30107 if (SUBTARGET_FRAME_POINTER_REQUIRED
)
30110 /* If the function receives nonlocal gotos, it needs to save the frame
30111 pointer in the nonlocal_goto_save_area object. */
30112 if (cfun
->has_nonlocal_label
)
30115 /* The frame pointer is required for non-leaf APCS frames. */
30116 if (TARGET_ARM
&& TARGET_APCS_FRAME
&& !crtl
->is_leaf
)
30119 /* If we are probing the stack in the prologue, we will have a faulting
30120 instruction prior to the stack adjustment and this requires a frame
30121 pointer if we want to catch the exception using the EABI unwinder. */
30122 if (!IS_INTERRUPT (arm_current_func_type ())
30123 && (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
30124 || flag_stack_clash_protection
)
30125 && arm_except_unwind_info (&global_options
) == UI_TARGET
30126 && cfun
->can_throw_non_call_exceptions
)
30128 HOST_WIDE_INT size
= get_frame_size ();
30130 /* That's irrelevant if there is no stack adjustment. */
30134 /* That's relevant only if there is a stack probe. */
30135 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
30137 /* We don't have the final size of the frame so adjust. */
30138 size
+= 32 * UNITS_PER_WORD
;
30139 if (size
> PROBE_INTERVAL
&& size
> get_stack_check_protect ())
30149 /* Implement the TARGET_HAVE_CONDITIONAL_EXECUTION hook.
30150 All modes except THUMB1 have conditional execution.
30151 If we have conditional arithmetic, return false before reload to
30152 enable some ifcvt transformations. */
30154 arm_have_conditional_execution (void)
30156 bool has_cond_exec
, enable_ifcvt_trans
;
30158 /* Only THUMB1 cannot support conditional execution. */
30159 has_cond_exec
= !TARGET_THUMB1
;
30161 /* Enable ifcvt transformations if we have conditional arithmetic, but only
30163 enable_ifcvt_trans
= TARGET_COND_ARITH
&& !reload_completed
;
30165 return has_cond_exec
&& !enable_ifcvt_trans
;
30168 /* The AAPCS sets the maximum alignment of a vector to 64 bits. */
30169 static HOST_WIDE_INT
30170 arm_vector_alignment (const_tree type
)
30172 HOST_WIDE_INT align
= tree_to_shwi (TYPE_SIZE (type
));
30174 if (TARGET_AAPCS_BASED
)
30175 align
= MIN (align
, 64);
30180 static unsigned int
30181 arm_autovectorize_vector_modes (vector_modes
*modes
, bool)
30183 if (!TARGET_NEON_VECTORIZE_DOUBLE
)
30185 modes
->safe_push (V16QImode
);
30186 modes
->safe_push (V8QImode
);
30192 arm_vector_alignment_reachable (const_tree type
, bool is_packed
)
30194 /* Vectors which aren't in packed structures will not be less aligned than
30195 the natural alignment of their element type, so this is safe. */
30196 if (TARGET_NEON
&& !BYTES_BIG_ENDIAN
&& unaligned_access
)
30199 return default_builtin_vector_alignment_reachable (type
, is_packed
);
30203 arm_builtin_support_vector_misalignment (machine_mode mode
,
30204 const_tree type
, int misalignment
,
30207 if (TARGET_NEON
&& !BYTES_BIG_ENDIAN
&& unaligned_access
)
30209 HOST_WIDE_INT align
= TYPE_ALIGN_UNIT (type
);
30214 /* If the misalignment is unknown, we should be able to handle the access
30215 so long as it is not to a member of a packed data structure. */
30216 if (misalignment
== -1)
30219 /* Return true if the misalignment is a multiple of the natural alignment
30220 of the vector's element type. This is probably always going to be
30221 true in practice, since we've already established that this isn't a
30223 return ((misalignment
% align
) == 0);
30226 return default_builtin_support_vector_misalignment (mode
, type
, misalignment
,
30231 arm_conditional_register_usage (void)
30235 if (TARGET_THUMB1
&& optimize_size
)
30237 /* When optimizing for size on Thumb-1, it's better not
30238 to use the HI regs, because of the overhead of
30240 for (regno
= FIRST_HI_REGNUM
; regno
<= LAST_HI_REGNUM
; ++regno
)
30241 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
30244 /* The link register can be clobbered by any branch insn,
30245 but we have no way to track that at present, so mark
30246 it as unavailable. */
30248 fixed_regs
[LR_REGNUM
] = call_used_regs
[LR_REGNUM
] = 1;
30250 if (TARGET_32BIT
&& TARGET_VFP_BASE
)
30252 /* VFPv3 registers are disabled when earlier VFP
30253 versions are selected due to the definition of
30254 LAST_VFP_REGNUM. */
30255 for (regno
= FIRST_VFP_REGNUM
;
30256 regno
<= LAST_VFP_REGNUM
; ++ regno
)
30258 fixed_regs
[regno
] = 0;
30259 call_used_regs
[regno
] = regno
< FIRST_VFP_REGNUM
+ 16
30260 || regno
>= FIRST_VFP_REGNUM
+ 32;
30262 if (TARGET_HAVE_MVE
)
30263 fixed_regs
[VPR_REGNUM
] = 0;
30266 if (TARGET_REALLY_IWMMXT
&& !TARGET_GENERAL_REGS_ONLY
)
30268 regno
= FIRST_IWMMXT_GR_REGNUM
;
30269 /* The 2002/10/09 revision of the XScale ABI has wCG0
30270 and wCG1 as call-preserved registers. The 2002/11/21
30271 revision changed this so that all wCG registers are
30272 scratch registers. */
30273 for (regno
= FIRST_IWMMXT_GR_REGNUM
;
30274 regno
<= LAST_IWMMXT_GR_REGNUM
; ++ regno
)
30275 fixed_regs
[regno
] = 0;
30276 /* The XScale ABI has wR0 - wR9 as scratch registers,
30277 the rest as call-preserved registers. */
30278 for (regno
= FIRST_IWMMXT_REGNUM
;
30279 regno
<= LAST_IWMMXT_REGNUM
; ++ regno
)
30281 fixed_regs
[regno
] = 0;
30282 call_used_regs
[regno
] = regno
< FIRST_IWMMXT_REGNUM
+ 10;
30286 if ((unsigned) PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
30288 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
30289 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
30291 else if (TARGET_APCS_STACK
)
30293 fixed_regs
[10] = 1;
30294 call_used_regs
[10] = 1;
30296 /* -mcaller-super-interworking reserves r11 for calls to
30297 _interwork_r11_call_via_rN(). Making the register global
30298 is an easy way of ensuring that it remains valid for all
30300 if (TARGET_APCS_FRAME
|| TARGET_CALLER_INTERWORKING
30301 || TARGET_TPCS_FRAME
|| TARGET_TPCS_LEAF_FRAME
)
30303 fixed_regs
[ARM_HARD_FRAME_POINTER_REGNUM
] = 1;
30304 call_used_regs
[ARM_HARD_FRAME_POINTER_REGNUM
] = 1;
30305 if (TARGET_CALLER_INTERWORKING
)
30306 global_regs
[ARM_HARD_FRAME_POINTER_REGNUM
] = 1;
30309 /* The Q and GE bits are only accessed via special ACLE patterns. */
30310 CLEAR_HARD_REG_BIT (operand_reg_set
, APSRQ_REGNUM
);
30311 CLEAR_HARD_REG_BIT (operand_reg_set
, APSRGE_REGNUM
);
30313 SUBTARGET_CONDITIONAL_REGISTER_USAGE
30317 arm_preferred_rename_class (reg_class_t rclass
)
30319 /* Thumb-2 instructions using LO_REGS may be smaller than instructions
30320 using GENERIC_REGS. During register rename pass, we prefer LO_REGS,
30321 and code size can be reduced. */
30322 if (TARGET_THUMB2
&& rclass
== GENERAL_REGS
)
30328 /* Compute the attribute "length" of insn "*push_multi".
30329 So this function MUST be kept in sync with that insn pattern. */
30331 arm_attr_length_push_multi(rtx parallel_op
, rtx first_op
)
30333 int i
, regno
, hi_reg
;
30334 int num_saves
= XVECLEN (parallel_op
, 0);
30344 regno
= REGNO (first_op
);
30345 /* For PUSH/STM under Thumb2 mode, we can use 16-bit encodings if the register
30346 list is 8-bit. Normally this means all registers in the list must be
30347 LO_REGS, that is (R0 -R7). If any HI_REGS used, then we must use 32-bit
30348 encodings. There is one exception for PUSH that LR in HI_REGS can be used
30349 with 16-bit encoding. */
30350 hi_reg
= (REGNO_REG_CLASS (regno
) == HI_REGS
) && (regno
!= LR_REGNUM
);
30351 for (i
= 1; i
< num_saves
&& !hi_reg
; i
++)
30353 regno
= REGNO (XEXP (XVECEXP (parallel_op
, 0, i
), 0));
30354 hi_reg
|= (REGNO_REG_CLASS (regno
) == HI_REGS
) && (regno
!= LR_REGNUM
);
30362 /* Compute the attribute "length" of insn. Currently, this function is used
30363 for "*load_multiple_with_writeback", "*pop_multiple_with_return" and
30364 "*pop_multiple_with_writeback_and_return". OPERANDS is the toplevel PARALLEL
30365 rtx, RETURN_PC is true if OPERANDS contains return insn. WRITE_BACK_P is
30366 true if OPERANDS contains insn which explicit updates base register. */
30369 arm_attr_length_pop_multi (rtx
*operands
, bool return_pc
, bool write_back_p
)
30378 rtx parallel_op
= operands
[0];
30379 /* Initialize to elements number of PARALLEL. */
30380 unsigned indx
= XVECLEN (parallel_op
, 0) - 1;
30381 /* Initialize the value to base register. */
30382 unsigned regno
= REGNO (operands
[1]);
30383 /* Skip return and write back pattern.
30384 We only need register pop pattern for later analysis. */
30385 unsigned first_indx
= 0;
30386 first_indx
+= return_pc
? 1 : 0;
30387 first_indx
+= write_back_p
? 1 : 0;
30389 /* A pop operation can be done through LDM or POP. If the base register is SP
30390 and if it's with write back, then a LDM will be alias of POP. */
30391 bool pop_p
= (regno
== SP_REGNUM
&& write_back_p
);
30392 bool ldm_p
= !pop_p
;
30394 /* Check base register for LDM. */
30395 if (ldm_p
&& REGNO_REG_CLASS (regno
) == HI_REGS
)
30398 /* Check each register in the list. */
30399 for (; indx
>= first_indx
; indx
--)
30401 regno
= REGNO (XEXP (XVECEXP (parallel_op
, 0, indx
), 0));
30402 /* For POP, PC in HI_REGS can be used with 16-bit encoding. See similar
30403 comment in arm_attr_length_push_multi. */
30404 if (REGNO_REG_CLASS (regno
) == HI_REGS
30405 && (regno
!= PC_REGNUM
|| ldm_p
))
30412 /* Compute the number of instructions emitted by output_move_double. */
30414 arm_count_output_move_double_insns (rtx
*operands
)
30418 /* output_move_double may modify the operands array, so call it
30419 here on a copy of the array. */
30420 ops
[0] = operands
[0];
30421 ops
[1] = operands
[1];
30422 output_move_double (ops
, false, &count
);
30426 /* Same as above, but operands are a register/memory pair in SImode.
30427 Assumes operands has the base register in position 0 and memory in position
30428 2 (which is the order provided by the arm_{ldrd,strd} patterns). */
30430 arm_count_ldrdstrd_insns (rtx
*operands
, bool load
)
30434 int regnum
, memnum
;
30436 regnum
= 0, memnum
= 1;
30438 regnum
= 1, memnum
= 0;
30439 ops
[regnum
] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
30440 ops
[memnum
] = adjust_address (operands
[2], DImode
, 0);
30441 output_move_double (ops
, false, &count
);
30447 vfp3_const_double_for_fract_bits (rtx operand
)
30449 REAL_VALUE_TYPE r0
;
30451 if (!CONST_DOUBLE_P (operand
))
30454 r0
= *CONST_DOUBLE_REAL_VALUE (operand
);
30455 if (exact_real_inverse (DFmode
, &r0
)
30456 && !REAL_VALUE_NEGATIVE (r0
))
30458 if (exact_real_truncate (DFmode
, &r0
))
30460 HOST_WIDE_INT value
= real_to_integer (&r0
);
30461 value
= value
& 0xffffffff;
30462 if ((value
!= 0) && ( (value
& (value
- 1)) == 0))
30464 int ret
= exact_log2 (value
);
30465 gcc_assert (IN_RANGE (ret
, 0, 31));
30473 /* If X is a CONST_DOUBLE with a value that is a power of 2 whose
30474 log2 is in [1, 32], return that log2. Otherwise return -1.
30475 This is used in the patterns for vcvt.s32.f32 floating-point to
30476 fixed-point conversions. */
30479 vfp3_const_double_for_bits (rtx x
)
30481 const REAL_VALUE_TYPE
*r
;
30483 if (!CONST_DOUBLE_P (x
))
30486 r
= CONST_DOUBLE_REAL_VALUE (x
);
30488 if (REAL_VALUE_NEGATIVE (*r
)
30489 || REAL_VALUE_ISNAN (*r
)
30490 || REAL_VALUE_ISINF (*r
)
30491 || !real_isinteger (r
, SFmode
))
30494 HOST_WIDE_INT hwint
= exact_log2 (real_to_integer (r
));
30496 /* The exact_log2 above will have returned -1 if this is
30497 not an exact log2. */
30498 if (!IN_RANGE (hwint
, 1, 32))
30505 /* Emit a memory barrier around an atomic sequence according to MODEL. */
30508 arm_pre_atomic_barrier (enum memmodel model
)
30510 if (need_atomic_barrier_p (model
, true))
30511 emit_insn (gen_memory_barrier ());
30515 arm_post_atomic_barrier (enum memmodel model
)
30517 if (need_atomic_barrier_p (model
, false))
30518 emit_insn (gen_memory_barrier ());
30521 /* Emit the load-exclusive and store-exclusive instructions.
30522 Use acquire and release versions if necessary. */
30525 arm_emit_load_exclusive (machine_mode mode
, rtx rval
, rtx mem
, bool acq
)
30527 rtx (*gen
) (rtx
, rtx
);
30533 case E_QImode
: gen
= gen_arm_load_acquire_exclusiveqi
; break;
30534 case E_HImode
: gen
= gen_arm_load_acquire_exclusivehi
; break;
30535 case E_SImode
: gen
= gen_arm_load_acquire_exclusivesi
; break;
30536 case E_DImode
: gen
= gen_arm_load_acquire_exclusivedi
; break;
30538 gcc_unreachable ();
30545 case E_QImode
: gen
= gen_arm_load_exclusiveqi
; break;
30546 case E_HImode
: gen
= gen_arm_load_exclusivehi
; break;
30547 case E_SImode
: gen
= gen_arm_load_exclusivesi
; break;
30548 case E_DImode
: gen
= gen_arm_load_exclusivedi
; break;
30550 gcc_unreachable ();
30554 emit_insn (gen (rval
, mem
));
30558 arm_emit_store_exclusive (machine_mode mode
, rtx bval
, rtx rval
,
30561 rtx (*gen
) (rtx
, rtx
, rtx
);
30567 case E_QImode
: gen
= gen_arm_store_release_exclusiveqi
; break;
30568 case E_HImode
: gen
= gen_arm_store_release_exclusivehi
; break;
30569 case E_SImode
: gen
= gen_arm_store_release_exclusivesi
; break;
30570 case E_DImode
: gen
= gen_arm_store_release_exclusivedi
; break;
30572 gcc_unreachable ();
30579 case E_QImode
: gen
= gen_arm_store_exclusiveqi
; break;
30580 case E_HImode
: gen
= gen_arm_store_exclusivehi
; break;
30581 case E_SImode
: gen
= gen_arm_store_exclusivesi
; break;
30582 case E_DImode
: gen
= gen_arm_store_exclusivedi
; break;
30584 gcc_unreachable ();
30588 emit_insn (gen (bval
, rval
, mem
));
30591 /* Mark the previous jump instruction as unlikely. */
30594 emit_unlikely_jump (rtx insn
)
30596 rtx_insn
*jump
= emit_jump_insn (insn
);
30597 add_reg_br_prob_note (jump
, profile_probability::very_unlikely ());
30600 /* Expand a compare and swap pattern. */
30603 arm_expand_compare_and_swap (rtx operands
[])
30605 rtx bval
, bdst
, rval
, mem
, oldval
, newval
, is_weak
, mod_s
, mod_f
, x
;
30606 machine_mode mode
, cmp_mode
;
30608 bval
= operands
[0];
30609 rval
= operands
[1];
30611 oldval
= operands
[3];
30612 newval
= operands
[4];
30613 is_weak
= operands
[5];
30614 mod_s
= operands
[6];
30615 mod_f
= operands
[7];
30616 mode
= GET_MODE (mem
);
30618 /* Normally the succ memory model must be stronger than fail, but in the
30619 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
30620 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
30622 if (TARGET_HAVE_LDACQ
30623 && is_mm_acquire (memmodel_from_int (INTVAL (mod_f
)))
30624 && is_mm_release (memmodel_from_int (INTVAL (mod_s
))))
30625 mod_s
= GEN_INT (MEMMODEL_ACQ_REL
);
30631 /* For narrow modes, we're going to perform the comparison in SImode,
30632 so do the zero-extension now. */
30633 rval
= gen_reg_rtx (SImode
);
30634 oldval
= convert_modes (SImode
, mode
, oldval
, true);
30638 /* Force the value into a register if needed. We waited until after
30639 the zero-extension above to do this properly. */
30640 if (!arm_add_operand (oldval
, SImode
))
30641 oldval
= force_reg (SImode
, oldval
);
30645 if (!cmpdi_operand (oldval
, mode
))
30646 oldval
= force_reg (mode
, oldval
);
30650 gcc_unreachable ();
30654 cmp_mode
= E_SImode
;
30656 cmp_mode
= CC_Zmode
;
30658 bdst
= TARGET_THUMB1
? bval
: gen_rtx_REG (CC_Zmode
, CC_REGNUM
);
30659 emit_insn (gen_atomic_compare_and_swap_1 (cmp_mode
, mode
, bdst
, rval
, mem
,
30660 oldval
, newval
, is_weak
, mod_s
, mod_f
));
30662 if (mode
== QImode
|| mode
== HImode
)
30663 emit_move_insn (operands
[1], gen_lowpart (mode
, rval
));
30665 /* In all cases, we arrange for success to be signaled by Z set.
30666 This arrangement allows for the boolean result to be used directly
30667 in a subsequent branch, post optimization. For Thumb-1 targets, the
30668 boolean negation of the result is also stored in bval because Thumb-1
30669 backend lacks dependency tracking for CC flag due to flag-setting not
30670 being represented at RTL level. */
30672 emit_insn (gen_cstoresi_eq0_thumb1 (bval
, bdst
));
30675 x
= gen_rtx_EQ (SImode
, bdst
, const0_rtx
);
30676 emit_insn (gen_rtx_SET (bval
, x
));
30680 /* Split a compare and swap pattern. It is IMPLEMENTATION DEFINED whether
30681 another memory store between the load-exclusive and store-exclusive can
30682 reset the monitor from Exclusive to Open state. This means we must wait
30683 until after reload to split the pattern, lest we get a register spill in
30684 the middle of the atomic sequence. Success of the compare and swap is
30685 indicated by the Z flag set for 32bit targets and by neg_bval being zero
30686 for Thumb-1 targets (ie. negation of the boolean value returned by
30687 atomic_compare_and_swapmode standard pattern in operand 0). */
30690 arm_split_compare_and_swap (rtx operands
[])
30692 rtx rval
, mem
, oldval
, newval
, neg_bval
, mod_s_rtx
;
30694 enum memmodel mod_s
, mod_f
;
30696 rtx_code_label
*label1
, *label2
;
30699 rval
= operands
[1];
30701 oldval
= operands
[3];
30702 newval
= operands
[4];
30703 is_weak
= (operands
[5] != const0_rtx
);
30704 mod_s_rtx
= operands
[6];
30705 mod_s
= memmodel_from_int (INTVAL (mod_s_rtx
));
30706 mod_f
= memmodel_from_int (INTVAL (operands
[7]));
30707 neg_bval
= TARGET_THUMB1
? operands
[0] : operands
[8];
30708 mode
= GET_MODE (mem
);
30710 bool is_armv8_sync
= arm_arch8
&& is_mm_sync (mod_s
);
30712 bool use_acquire
= TARGET_HAVE_LDACQ
&& aarch_mm_needs_acquire (mod_s_rtx
);
30713 bool use_release
= TARGET_HAVE_LDACQ
&& aarch_mm_needs_release (mod_s_rtx
);
30715 /* For ARMv8, the load-acquire is too weak for __sync memory orders. Instead,
30716 a full barrier is emitted after the store-release. */
30718 use_acquire
= false;
30720 /* Checks whether a barrier is needed and emits one accordingly. */
30721 if (!(use_acquire
|| use_release
))
30722 arm_pre_atomic_barrier (mod_s
);
30727 label1
= gen_label_rtx ();
30728 emit_label (label1
);
30730 label2
= gen_label_rtx ();
30732 arm_emit_load_exclusive (mode
, rval
, mem
, use_acquire
);
30734 /* Z is set to 0 for 32bit targets (resp. rval set to 1) if oldval != rval,
30735 as required to communicate with arm_expand_compare_and_swap. */
30738 cond
= arm_gen_compare_reg (NE
, rval
, oldval
, neg_bval
);
30739 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
30740 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
30741 gen_rtx_LABEL_REF (Pmode
, label2
), pc_rtx
);
30742 emit_unlikely_jump (gen_rtx_SET (pc_rtx
, x
));
30746 cond
= gen_rtx_NE (VOIDmode
, rval
, oldval
);
30747 if (thumb1_cmpneg_operand (oldval
, SImode
))
30750 if (!satisfies_constraint_L (oldval
))
30752 gcc_assert (satisfies_constraint_J (oldval
));
30754 /* For such immediates, ADDS needs the source and destination regs
30757 Normally this would be handled by RA, but this is all happening
30759 emit_move_insn (neg_bval
, rval
);
30763 emit_unlikely_jump (gen_cbranchsi4_neg_late (neg_bval
, src
, oldval
,
30768 emit_move_insn (neg_bval
, const1_rtx
);
30769 emit_unlikely_jump (gen_cbranchsi4_insn (cond
, rval
, oldval
, label2
));
30773 arm_emit_store_exclusive (mode
, neg_bval
, mem
, newval
, use_release
);
30775 /* Weak or strong, we want EQ to be true for success, so that we
30776 match the flags that we got from the compare above. */
30779 cond
= gen_rtx_REG (CCmode
, CC_REGNUM
);
30780 x
= gen_rtx_COMPARE (CCmode
, neg_bval
, const0_rtx
);
30781 emit_insn (gen_rtx_SET (cond
, x
));
30786 /* Z is set to boolean value of !neg_bval, as required to communicate
30787 with arm_expand_compare_and_swap. */
30788 x
= gen_rtx_NE (VOIDmode
, neg_bval
, const0_rtx
);
30789 emit_unlikely_jump (gen_cbranchsi4 (x
, neg_bval
, const0_rtx
, label1
));
30792 if (!is_mm_relaxed (mod_f
))
30793 emit_label (label2
);
30795 /* Checks whether a barrier is needed and emits one accordingly. */
30797 || !(use_acquire
|| use_release
))
30798 arm_post_atomic_barrier (mod_s
);
30800 if (is_mm_relaxed (mod_f
))
30801 emit_label (label2
);
30804 /* Split an atomic operation pattern. Operation is given by CODE and is one
30805 of PLUS, MINUS, IOR, XOR, SET (for an exchange operation) or NOT (for a nand
30806 operation). Operation is performed on the content at MEM and on VALUE
30807 following the memory model MODEL_RTX. The content at MEM before and after
30808 the operation is returned in OLD_OUT and NEW_OUT respectively while the
30809 success of the operation is returned in COND. Using a scratch register or
30810 an operand register for these determines what result is returned for that
30814 arm_split_atomic_op (enum rtx_code code
, rtx old_out
, rtx new_out
, rtx mem
,
30815 rtx value
, rtx model_rtx
, rtx cond
)
30817 enum memmodel model
= memmodel_from_int (INTVAL (model_rtx
));
30818 machine_mode mode
= GET_MODE (mem
);
30819 machine_mode wmode
= (mode
== DImode
? DImode
: SImode
);
30820 rtx_code_label
*label
;
30821 bool all_low_regs
, bind_old_new
;
30824 bool is_armv8_sync
= arm_arch8
&& is_mm_sync (model
);
30826 bool use_acquire
= TARGET_HAVE_LDACQ
&& aarch_mm_needs_acquire (model_rtx
);
30827 bool use_release
= TARGET_HAVE_LDACQ
&& aarch_mm_needs_release (model_rtx
);
30829 /* For ARMv8, a load-acquire is too weak for __sync memory orders. Instead,
30830 a full barrier is emitted after the store-release. */
30832 use_acquire
= false;
30834 /* Checks whether a barrier is needed and emits one accordingly. */
30835 if (!(use_acquire
|| use_release
))
30836 arm_pre_atomic_barrier (model
);
30838 label
= gen_label_rtx ();
30839 emit_label (label
);
30842 new_out
= gen_lowpart (wmode
, new_out
);
30844 old_out
= gen_lowpart (wmode
, old_out
);
30847 value
= simplify_gen_subreg (wmode
, value
, mode
, 0);
30849 arm_emit_load_exclusive (mode
, old_out
, mem
, use_acquire
);
30851 /* Does the operation require destination and first operand to use the same
30852 register? This is decided by register constraints of relevant insn
30853 patterns in thumb1.md. */
30854 gcc_assert (!new_out
|| REG_P (new_out
));
30855 all_low_regs
= REG_P (value
) && REGNO_REG_CLASS (REGNO (value
)) == LO_REGS
30856 && new_out
&& REGNO_REG_CLASS (REGNO (new_out
)) == LO_REGS
30857 && REGNO_REG_CLASS (REGNO (old_out
)) == LO_REGS
;
30862 && (code
!= PLUS
|| (!all_low_regs
&& !satisfies_constraint_L (value
))));
30864 /* We want to return the old value while putting the result of the operation
30865 in the same register as the old value so copy the old value over to the
30866 destination register and use that register for the operation. */
30867 if (old_out
&& bind_old_new
)
30869 emit_move_insn (new_out
, old_out
);
30880 x
= gen_rtx_AND (wmode
, old_out
, value
);
30881 emit_insn (gen_rtx_SET (new_out
, x
));
30882 x
= gen_rtx_NOT (wmode
, new_out
);
30883 emit_insn (gen_rtx_SET (new_out
, x
));
30887 if (CONST_INT_P (value
))
30889 value
= gen_int_mode (-INTVAL (value
), wmode
);
30895 if (mode
== DImode
)
30897 /* DImode plus/minus need to clobber flags. */
30898 /* The adddi3 and subdi3 patterns are incorrectly written so that
30899 they require matching operands, even when we could easily support
30900 three operands. Thankfully, this can be fixed up post-splitting,
30901 as the individual add+adc patterns do accept three operands and
30902 post-reload cprop can make these moves go away. */
30903 emit_move_insn (new_out
, old_out
);
30905 x
= gen_adddi3 (new_out
, new_out
, value
);
30907 x
= gen_subdi3 (new_out
, new_out
, value
);
30914 x
= gen_rtx_fmt_ee (code
, wmode
, old_out
, value
);
30915 emit_insn (gen_rtx_SET (new_out
, x
));
30919 arm_emit_store_exclusive (mode
, cond
, mem
, gen_lowpart (mode
, new_out
),
30922 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
30923 emit_unlikely_jump (gen_cbranchsi4 (x
, cond
, const0_rtx
, label
));
30925 /* Checks whether a barrier is needed and emits one accordingly. */
30927 || !(use_acquire
|| use_release
))
30928 arm_post_atomic_barrier (model
);
30931 /* Expand code to compare vectors OP0 and OP1 using condition CODE.
30932 If CAN_INVERT, store either the result or its inverse in TARGET
30933 and return true if TARGET contains the inverse. If !CAN_INVERT,
30934 always store the result in TARGET, never its inverse.
30936 Note that the handling of floating-point comparisons is not
30940 arm_expand_vector_compare (rtx target
, rtx_code code
, rtx op0
, rtx op1
,
30943 machine_mode cmp_result_mode
= GET_MODE (target
);
30944 machine_mode cmp_mode
= GET_MODE (op0
);
30949 /* For these we need to compute the inverse of the requested
30958 code
= reverse_condition_maybe_unordered (code
);
30961 /* Recursively emit the inverted comparison into a temporary
30962 and then store its inverse in TARGET. This avoids reusing
30963 TARGET (which for integer NE could be one of the inputs). */
30964 rtx tmp
= gen_reg_rtx (cmp_result_mode
);
30965 if (arm_expand_vector_compare (tmp
, code
, op0
, op1
, true))
30966 gcc_unreachable ();
30967 emit_insn (gen_rtx_SET (target
, gen_rtx_NOT (cmp_result_mode
, tmp
)));
30980 /* These are natively supported for zero comparisons, but otherwise
30981 require the operands to be swapped. */
30984 if (op1
!= CONST0_RTX (cmp_mode
))
30986 code
= swap_condition (code
);
30987 std::swap (op0
, op1
);
30989 /* Fall through. */
30991 /* These are natively supported for both register and zero operands. */
30995 emit_insn (gen_neon_vc (code
, cmp_mode
, target
, op0
, op1
));
30998 /* These are natively supported for register operands only.
30999 Comparisons with zero aren't useful and should be folded
31000 or canonicalized by target-independent code. */
31003 emit_insn (gen_neon_vc (code
, cmp_mode
, target
,
31004 op0
, force_reg (cmp_mode
, op1
)));
31007 /* These require the operands to be swapped and likewise do not
31008 support comparisons with zero. */
31011 emit_insn (gen_neon_vc (swap_condition (code
), cmp_mode
,
31012 target
, force_reg (cmp_mode
, op1
), op0
));
31015 /* These need a combination of two comparisons. */
31019 /* Operands are LTGT iff (a > b || a > b).
31020 Operands are ORDERED iff (a > b || a <= b). */
31021 rtx gt_res
= gen_reg_rtx (cmp_result_mode
);
31022 rtx alt_res
= gen_reg_rtx (cmp_result_mode
);
31023 rtx_code alt_code
= (code
== LTGT
? LT
: LE
);
31024 if (arm_expand_vector_compare (gt_res
, GT
, op0
, op1
, true)
31025 || arm_expand_vector_compare (alt_res
, alt_code
, op0
, op1
, true))
31026 gcc_unreachable ();
31027 emit_insn (gen_rtx_SET (target
, gen_rtx_IOR (cmp_result_mode
,
31028 gt_res
, alt_res
)));
31033 gcc_unreachable ();
31037 /* Expand a vcond or vcondu pattern with operands OPERANDS.
31038 CMP_RESULT_MODE is the mode of the comparison result. */
31041 arm_expand_vcond (rtx
*operands
, machine_mode cmp_result_mode
)
31043 rtx mask
= gen_reg_rtx (cmp_result_mode
);
31044 bool inverted
= arm_expand_vector_compare (mask
, GET_CODE (operands
[3]),
31045 operands
[4], operands
[5], true);
31047 std::swap (operands
[1], operands
[2]);
31048 emit_insn (gen_neon_vbsl (GET_MODE (operands
[0]), operands
[0],
31049 mask
, operands
[1], operands
[2]));
31052 #define MAX_VECT_LEN 16
31054 struct expand_vec_perm_d
31056 rtx target
, op0
, op1
;
31057 vec_perm_indices perm
;
31058 machine_mode vmode
;
31063 /* Generate a variable permutation. */
31066 arm_expand_vec_perm_1 (rtx target
, rtx op0
, rtx op1
, rtx sel
)
31068 machine_mode vmode
= GET_MODE (target
);
31069 bool one_vector_p
= rtx_equal_p (op0
, op1
);
31071 gcc_checking_assert (vmode
== V8QImode
|| vmode
== V16QImode
);
31072 gcc_checking_assert (GET_MODE (op0
) == vmode
);
31073 gcc_checking_assert (GET_MODE (op1
) == vmode
);
31074 gcc_checking_assert (GET_MODE (sel
) == vmode
);
31075 gcc_checking_assert (TARGET_NEON
);
31079 if (vmode
== V8QImode
)
31080 emit_insn (gen_neon_vtbl1v8qi (target
, op0
, sel
));
31082 emit_insn (gen_neon_vtbl1v16qi (target
, op0
, sel
));
31088 if (vmode
== V8QImode
)
31090 pair
= gen_reg_rtx (V16QImode
);
31091 emit_insn (gen_neon_vcombinev8qi (pair
, op0
, op1
));
31092 pair
= gen_lowpart (TImode
, pair
);
31093 emit_insn (gen_neon_vtbl2v8qi (target
, pair
, sel
));
31097 pair
= gen_reg_rtx (OImode
);
31098 emit_insn (gen_neon_vcombinev16qi (pair
, op0
, op1
));
31099 emit_insn (gen_neon_vtbl2v16qi (target
, pair
, sel
));
31105 arm_expand_vec_perm (rtx target
, rtx op0
, rtx op1
, rtx sel
)
31107 machine_mode vmode
= GET_MODE (target
);
31108 unsigned int nelt
= GET_MODE_NUNITS (vmode
);
31109 bool one_vector_p
= rtx_equal_p (op0
, op1
);
31112 /* TODO: ARM's VTBL indexing is little-endian. In order to handle GCC's
31113 numbering of elements for big-endian, we must reverse the order. */
31114 gcc_checking_assert (!BYTES_BIG_ENDIAN
);
31116 /* The VTBL instruction does not use a modulo index, so we must take care
31117 of that ourselves. */
31118 mask
= GEN_INT (one_vector_p
? nelt
- 1 : 2 * nelt
- 1);
31119 mask
= gen_const_vec_duplicate (vmode
, mask
);
31120 sel
= expand_simple_binop (vmode
, AND
, sel
, mask
, NULL
, 0, OPTAB_LIB_WIDEN
);
31122 arm_expand_vec_perm_1 (target
, op0
, op1
, sel
);
31125 /* Map lane ordering between architectural lane order, and GCC lane order,
31126 taking into account ABI. See comment above output_move_neon for details. */
31129 neon_endian_lane_map (machine_mode mode
, int lane
)
31131 if (BYTES_BIG_ENDIAN
)
31133 int nelems
= GET_MODE_NUNITS (mode
);
31134 /* Reverse lane order. */
31135 lane
= (nelems
- 1 - lane
);
31136 /* Reverse D register order, to match ABI. */
31137 if (GET_MODE_SIZE (mode
) == 16)
31138 lane
= lane
^ (nelems
/ 2);
31143 /* Some permutations index into pairs of vectors, this is a helper function
31144 to map indexes into those pairs of vectors. */
31147 neon_pair_endian_lane_map (machine_mode mode
, int lane
)
31149 int nelem
= GET_MODE_NUNITS (mode
);
31150 if (BYTES_BIG_ENDIAN
)
31152 neon_endian_lane_map (mode
, lane
& (nelem
- 1)) + (lane
& nelem
);
31156 /* Generate or test for an insn that supports a constant permutation. */
31158 /* Recognize patterns for the VUZP insns. */
31161 arm_evpc_neon_vuzp (struct expand_vec_perm_d
*d
)
31163 unsigned int i
, odd
, mask
, nelt
= d
->perm
.length ();
31164 rtx out0
, out1
, in0
, in1
;
31168 if (GET_MODE_UNIT_SIZE (d
->vmode
) >= 8)
31171 /* arm_expand_vec_perm_const_1 () helpfully swaps the operands for the
31172 big endian pattern on 64 bit vectors, so we correct for that. */
31173 swap_nelt
= BYTES_BIG_ENDIAN
&& !d
->one_vector_p
31174 && GET_MODE_SIZE (d
->vmode
) == 8 ? nelt
: 0;
31176 first_elem
= d
->perm
[neon_endian_lane_map (d
->vmode
, 0)] ^ swap_nelt
;
31178 if (first_elem
== neon_endian_lane_map (d
->vmode
, 0))
31180 else if (first_elem
== neon_endian_lane_map (d
->vmode
, 1))
31184 mask
= (d
->one_vector_p
? nelt
- 1 : 2 * nelt
- 1);
31186 for (i
= 0; i
< nelt
; i
++)
31189 (neon_pair_endian_lane_map (d
->vmode
, i
) * 2 + odd
) & mask
;
31190 if ((d
->perm
[i
] ^ swap_nelt
) != neon_pair_endian_lane_map (d
->vmode
, elt
))
31200 if (swap_nelt
!= 0)
31201 std::swap (in0
, in1
);
31204 out1
= gen_reg_rtx (d
->vmode
);
31206 std::swap (out0
, out1
);
31208 emit_insn (gen_neon_vuzp_internal (d
->vmode
, out0
, in0
, in1
, out1
));
31212 /* Recognize patterns for the VZIP insns. */
31215 arm_evpc_neon_vzip (struct expand_vec_perm_d
*d
)
31217 unsigned int i
, high
, mask
, nelt
= d
->perm
.length ();
31218 rtx out0
, out1
, in0
, in1
;
31222 if (GET_MODE_UNIT_SIZE (d
->vmode
) >= 8)
31225 is_swapped
= BYTES_BIG_ENDIAN
;
31227 first_elem
= d
->perm
[neon_endian_lane_map (d
->vmode
, 0) ^ is_swapped
];
31230 if (first_elem
== neon_endian_lane_map (d
->vmode
, high
))
31232 else if (first_elem
== neon_endian_lane_map (d
->vmode
, 0))
31236 mask
= (d
->one_vector_p
? nelt
- 1 : 2 * nelt
- 1);
31238 for (i
= 0; i
< nelt
/ 2; i
++)
31241 neon_pair_endian_lane_map (d
->vmode
, i
+ high
) & mask
;
31242 if (d
->perm
[neon_pair_endian_lane_map (d
->vmode
, 2 * i
+ is_swapped
)]
31246 neon_pair_endian_lane_map (d
->vmode
, i
+ nelt
+ high
) & mask
;
31247 if (d
->perm
[neon_pair_endian_lane_map (d
->vmode
, 2 * i
+ !is_swapped
)]
31259 std::swap (in0
, in1
);
31262 out1
= gen_reg_rtx (d
->vmode
);
31264 std::swap (out0
, out1
);
31266 emit_insn (gen_neon_vzip_internal (d
->vmode
, out0
, in0
, in1
, out1
));
31270 /* Recognize patterns for the VREV insns. */
31272 arm_evpc_neon_vrev (struct expand_vec_perm_d
*d
)
31274 unsigned int i
, j
, diff
, nelt
= d
->perm
.length ();
31275 rtx (*gen
) (machine_mode
, rtx
, rtx
);
31277 if (!d
->one_vector_p
)
31288 gen
= gen_neon_vrev64
;
31299 gen
= gen_neon_vrev32
;
31305 gen
= gen_neon_vrev64
;
31316 gen
= gen_neon_vrev16
;
31320 gen
= gen_neon_vrev32
;
31326 gen
= gen_neon_vrev64
;
31336 for (i
= 0; i
< nelt
; i
+= diff
+ 1)
31337 for (j
= 0; j
<= diff
; j
+= 1)
31339 /* This is guaranteed to be true as the value of diff
31340 is 7, 3, 1 and we should have enough elements in the
31341 queue to generate this. Getting a vector mask with a
31342 value of diff other than these values implies that
31343 something is wrong by the time we get here. */
31344 gcc_assert (i
+ j
< nelt
);
31345 if (d
->perm
[i
+ j
] != i
+ diff
- j
)
31353 emit_insn (gen (d
->vmode
, d
->target
, d
->op0
));
31357 /* Recognize patterns for the VTRN insns. */
31360 arm_evpc_neon_vtrn (struct expand_vec_perm_d
*d
)
31362 unsigned int i
, odd
, mask
, nelt
= d
->perm
.length ();
31363 rtx out0
, out1
, in0
, in1
;
31365 if (GET_MODE_UNIT_SIZE (d
->vmode
) >= 8)
31368 /* Note that these are little-endian tests. Adjust for big-endian later. */
31369 if (d
->perm
[0] == 0)
31371 else if (d
->perm
[0] == 1)
31375 mask
= (d
->one_vector_p
? nelt
- 1 : 2 * nelt
- 1);
31377 for (i
= 0; i
< nelt
; i
+= 2)
31379 if (d
->perm
[i
] != i
+ odd
)
31381 if (d
->perm
[i
+ 1] != ((i
+ nelt
+ odd
) & mask
))
31391 if (BYTES_BIG_ENDIAN
)
31393 std::swap (in0
, in1
);
31398 out1
= gen_reg_rtx (d
->vmode
);
31400 std::swap (out0
, out1
);
31402 emit_insn (gen_neon_vtrn_internal (d
->vmode
, out0
, in0
, in1
, out1
));
31406 /* Recognize patterns for the VEXT insns. */
31409 arm_evpc_neon_vext (struct expand_vec_perm_d
*d
)
31411 unsigned int i
, nelt
= d
->perm
.length ();
31414 unsigned int location
;
31416 unsigned int next
= d
->perm
[0] + 1;
31418 /* TODO: Handle GCC's numbering of elements for big-endian. */
31419 if (BYTES_BIG_ENDIAN
)
31422 /* Check if the extracted indexes are increasing by one. */
31423 for (i
= 1; i
< nelt
; next
++, i
++)
31425 /* If we hit the most significant element of the 2nd vector in
31426 the previous iteration, no need to test further. */
31427 if (next
== 2 * nelt
)
31430 /* If we are operating on only one vector: it could be a
31431 rotation. If there are only two elements of size < 64, let
31432 arm_evpc_neon_vrev catch it. */
31433 if (d
->one_vector_p
&& (next
== nelt
))
31435 if ((nelt
== 2) && (d
->vmode
!= V2DImode
))
31441 if (d
->perm
[i
] != next
)
31445 location
= d
->perm
[0];
31451 offset
= GEN_INT (location
);
31453 if(d
->vmode
== E_DImode
)
31456 emit_insn (gen_neon_vext (d
->vmode
, d
->target
, d
->op0
, d
->op1
, offset
));
31460 /* The NEON VTBL instruction is a fully variable permuation that's even
31461 stronger than what we expose via VEC_PERM_EXPR. What it doesn't do
31462 is mask the index operand as VEC_PERM_EXPR requires. Therefore we
31463 can do slightly better by expanding this as a constant where we don't
31464 have to apply a mask. */
31467 arm_evpc_neon_vtbl (struct expand_vec_perm_d
*d
)
31469 rtx rperm
[MAX_VECT_LEN
], sel
;
31470 machine_mode vmode
= d
->vmode
;
31471 unsigned int i
, nelt
= d
->perm
.length ();
31473 /* TODO: ARM's VTBL indexing is little-endian. In order to handle GCC's
31474 numbering of elements for big-endian, we must reverse the order. */
31475 if (BYTES_BIG_ENDIAN
)
31481 /* Generic code will try constant permutation twice. Once with the
31482 original mode and again with the elements lowered to QImode.
31483 So wait and don't do the selector expansion ourselves. */
31484 if (vmode
!= V8QImode
&& vmode
!= V16QImode
)
31487 for (i
= 0; i
< nelt
; ++i
)
31488 rperm
[i
] = GEN_INT (d
->perm
[i
]);
31489 sel
= gen_rtx_CONST_VECTOR (vmode
, gen_rtvec_v (nelt
, rperm
));
31490 sel
= force_reg (vmode
, sel
);
31492 arm_expand_vec_perm_1 (d
->target
, d
->op0
, d
->op1
, sel
);
31497 arm_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
31499 /* Check if the input mask matches vext before reordering the
31502 if (arm_evpc_neon_vext (d
))
31505 /* The pattern matching functions above are written to look for a small
31506 number to begin the sequence (0, 1, N/2). If we begin with an index
31507 from the second operand, we can swap the operands. */
31508 unsigned int nelt
= d
->perm
.length ();
31509 if (d
->perm
[0] >= nelt
)
31511 d
->perm
.rotate_inputs (1);
31512 std::swap (d
->op0
, d
->op1
);
31517 if (arm_evpc_neon_vuzp (d
))
31519 if (arm_evpc_neon_vzip (d
))
31521 if (arm_evpc_neon_vrev (d
))
31523 if (arm_evpc_neon_vtrn (d
))
31525 return arm_evpc_neon_vtbl (d
);
31530 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
31533 arm_vectorize_vec_perm_const (machine_mode vmode
, rtx target
, rtx op0
, rtx op1
,
31534 const vec_perm_indices
&sel
)
31536 struct expand_vec_perm_d d
;
31537 int i
, nelt
, which
;
31539 if (!VALID_NEON_DREG_MODE (vmode
) && !VALID_NEON_QREG_MODE (vmode
))
31545 rtx nop0
= force_reg (vmode
, op0
);
31551 op1
= force_reg (vmode
, op1
);
31556 gcc_assert (VECTOR_MODE_P (d
.vmode
));
31557 d
.testing_p
= !target
;
31559 nelt
= GET_MODE_NUNITS (d
.vmode
);
31560 for (i
= which
= 0; i
< nelt
; ++i
)
31562 int ei
= sel
[i
] & (2 * nelt
- 1);
31563 which
|= (ei
< nelt
? 1 : 2);
31572 d
.one_vector_p
= false;
31573 if (d
.testing_p
|| !rtx_equal_p (op0
, op1
))
31576 /* The elements of PERM do not suggest that only the first operand
31577 is used, but both operands are identical. Allow easier matching
31578 of the permutation by folding the permutation into the single
31583 d
.one_vector_p
= true;
31588 d
.one_vector_p
= true;
31592 d
.perm
.new_vector (sel
.encoding (), d
.one_vector_p
? 1 : 2, nelt
);
31595 return arm_expand_vec_perm_const_1 (&d
);
31597 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
31598 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
31599 if (!d
.one_vector_p
)
31600 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
31603 bool ret
= arm_expand_vec_perm_const_1 (&d
);
31610 arm_autoinc_modes_ok_p (machine_mode mode
, enum arm_auto_incmodes code
)
31612 /* If we are soft float and we do not have ldrd
31613 then all auto increment forms are ok. */
31614 if (TARGET_SOFT_FLOAT
&& (TARGET_LDRD
|| GET_MODE_SIZE (mode
) <= 4))
31619 /* Post increment and Pre Decrement are supported for all
31620 instruction forms except for vector forms. */
31623 if (VECTOR_MODE_P (mode
))
31625 if (code
!= ARM_PRE_DEC
)
31635 /* Without LDRD and mode size greater than
31636 word size, there is no point in auto-incrementing
31637 because ldm and stm will not have these forms. */
31638 if (!TARGET_LDRD
&& GET_MODE_SIZE (mode
) > 4)
31641 /* Vector and floating point modes do not support
31642 these auto increment forms. */
31643 if (FLOAT_MODE_P (mode
) || VECTOR_MODE_P (mode
))
31656 /* The default expansion of general 64-bit shifts in core-regs is suboptimal,
31657 on ARM, since we know that shifts by negative amounts are no-ops.
31658 Additionally, the default expansion code is not available or suitable
31659 for post-reload insn splits (this can occur when the register allocator
31660 chooses not to do a shift in NEON).
31662 This function is used in both initial expand and post-reload splits, and
31663 handles all kinds of 64-bit shifts.
31665 Input requirements:
31666 - It is safe for the input and output to be the same register, but
31667 early-clobber rules apply for the shift amount and scratch registers.
31668 - Shift by register requires both scratch registers. In all other cases
31669 the scratch registers may be NULL.
31670 - Ashiftrt by a register also clobbers the CC register. */
31672 arm_emit_coreregs_64bit_shift (enum rtx_code code
, rtx out
, rtx in
,
31673 rtx amount
, rtx scratch1
, rtx scratch2
)
31675 rtx out_high
= gen_highpart (SImode
, out
);
31676 rtx out_low
= gen_lowpart (SImode
, out
);
31677 rtx in_high
= gen_highpart (SImode
, in
);
31678 rtx in_low
= gen_lowpart (SImode
, in
);
31681 in = the register pair containing the input value.
31682 out = the destination register pair.
31683 up = the high- or low-part of each pair.
31684 down = the opposite part to "up".
31685 In a shift, we can consider bits to shift from "up"-stream to
31686 "down"-stream, so in a left-shift "up" is the low-part and "down"
31687 is the high-part of each register pair. */
31689 rtx out_up
= code
== ASHIFT
? out_low
: out_high
;
31690 rtx out_down
= code
== ASHIFT
? out_high
: out_low
;
31691 rtx in_up
= code
== ASHIFT
? in_low
: in_high
;
31692 rtx in_down
= code
== ASHIFT
? in_high
: in_low
;
31694 gcc_assert (code
== ASHIFT
|| code
== ASHIFTRT
|| code
== LSHIFTRT
);
31696 && (REG_P (out
) || SUBREG_P (out
))
31697 && GET_MODE (out
) == DImode
);
31699 && (REG_P (in
) || SUBREG_P (in
))
31700 && GET_MODE (in
) == DImode
);
31702 && (((REG_P (amount
) || SUBREG_P (amount
))
31703 && GET_MODE (amount
) == SImode
)
31704 || CONST_INT_P (amount
)));
31705 gcc_assert (scratch1
== NULL
31706 || (GET_CODE (scratch1
) == SCRATCH
)
31707 || (GET_MODE (scratch1
) == SImode
31708 && REG_P (scratch1
)));
31709 gcc_assert (scratch2
== NULL
31710 || (GET_CODE (scratch2
) == SCRATCH
)
31711 || (GET_MODE (scratch2
) == SImode
31712 && REG_P (scratch2
)));
31713 gcc_assert (!REG_P (out
) || !REG_P (amount
)
31714 || !HARD_REGISTER_P (out
)
31715 || (REGNO (out
) != REGNO (amount
)
31716 && REGNO (out
) + 1 != REGNO (amount
)));
31718 /* Macros to make following code more readable. */
31719 #define SUB_32(DEST,SRC) \
31720 gen_addsi3 ((DEST), (SRC), GEN_INT (-32))
31721 #define RSB_32(DEST,SRC) \
31722 gen_subsi3 ((DEST), GEN_INT (32), (SRC))
31723 #define SUB_S_32(DEST,SRC) \
31724 gen_addsi3_compare0 ((DEST), (SRC), \
31726 #define SET(DEST,SRC) \
31727 gen_rtx_SET ((DEST), (SRC))
31728 #define SHIFT(CODE,SRC,AMOUNT) \
31729 gen_rtx_fmt_ee ((CODE), SImode, (SRC), (AMOUNT))
31730 #define LSHIFT(CODE,SRC,AMOUNT) \
31731 gen_rtx_fmt_ee ((CODE) == ASHIFT ? ASHIFT : LSHIFTRT, \
31732 SImode, (SRC), (AMOUNT))
31733 #define REV_LSHIFT(CODE,SRC,AMOUNT) \
31734 gen_rtx_fmt_ee ((CODE) == ASHIFT ? LSHIFTRT : ASHIFT, \
31735 SImode, (SRC), (AMOUNT))
31737 gen_rtx_IOR (SImode, (A), (B))
31738 #define BRANCH(COND,LABEL) \
31739 gen_arm_cond_branch ((LABEL), \
31740 gen_rtx_ ## COND (CCmode, cc_reg, \
31744 /* Shifts by register and shifts by constant are handled separately. */
31745 if (CONST_INT_P (amount
))
31747 /* We have a shift-by-constant. */
31749 /* First, handle out-of-range shift amounts.
31750 In both cases we try to match the result an ARM instruction in a
31751 shift-by-register would give. This helps reduce execution
31752 differences between optimization levels, but it won't stop other
31753 parts of the compiler doing different things. This is "undefined
31754 behavior, in any case. */
31755 if (INTVAL (amount
) <= 0)
31756 emit_insn (gen_movdi (out
, in
));
31757 else if (INTVAL (amount
) >= 64)
31759 if (code
== ASHIFTRT
)
31761 rtx const31_rtx
= GEN_INT (31);
31762 emit_insn (SET (out_down
, SHIFT (code
, in_up
, const31_rtx
)));
31763 emit_insn (SET (out_up
, SHIFT (code
, in_up
, const31_rtx
)));
31766 emit_insn (gen_movdi (out
, const0_rtx
));
31769 /* Now handle valid shifts. */
31770 else if (INTVAL (amount
) < 32)
31772 /* Shifts by a constant less than 32. */
31773 rtx reverse_amount
= GEN_INT (32 - INTVAL (amount
));
31775 /* Clearing the out register in DImode first avoids lots
31776 of spilling and results in less stack usage.
31777 Later this redundant insn is completely removed.
31778 Do that only if "in" and "out" are different registers. */
31779 if (REG_P (out
) && REG_P (in
) && REGNO (out
) != REGNO (in
))
31780 emit_insn (SET (out
, const0_rtx
));
31781 emit_insn (SET (out_down
, LSHIFT (code
, in_down
, amount
)));
31782 emit_insn (SET (out_down
,
31783 ORR (REV_LSHIFT (code
, in_up
, reverse_amount
),
31785 emit_insn (SET (out_up
, SHIFT (code
, in_up
, amount
)));
31789 /* Shifts by a constant greater than 31. */
31790 rtx adj_amount
= GEN_INT (INTVAL (amount
) - 32);
31792 if (REG_P (out
) && REG_P (in
) && REGNO (out
) != REGNO (in
))
31793 emit_insn (SET (out
, const0_rtx
));
31794 emit_insn (SET (out_down
, SHIFT (code
, in_up
, adj_amount
)));
31795 if (code
== ASHIFTRT
)
31796 emit_insn (gen_ashrsi3 (out_up
, in_up
,
31799 emit_insn (SET (out_up
, const0_rtx
));
31804 /* We have a shift-by-register. */
31805 rtx cc_reg
= gen_rtx_REG (CC_NZmode
, CC_REGNUM
);
31807 /* This alternative requires the scratch registers. */
31808 gcc_assert (scratch1
&& REG_P (scratch1
));
31809 gcc_assert (scratch2
&& REG_P (scratch2
));
31811 /* We will need the values "amount-32" and "32-amount" later.
31812 Swapping them around now allows the later code to be more general. */
31816 emit_insn (SUB_32 (scratch1
, amount
));
31817 emit_insn (RSB_32 (scratch2
, amount
));
31820 emit_insn (RSB_32 (scratch1
, amount
));
31821 /* Also set CC = amount > 32. */
31822 emit_insn (SUB_S_32 (scratch2
, amount
));
31825 emit_insn (RSB_32 (scratch1
, amount
));
31826 emit_insn (SUB_32 (scratch2
, amount
));
31829 gcc_unreachable ();
31832 /* Emit code like this:
31835 out_down = in_down << amount;
31836 out_down = (in_up << (amount - 32)) | out_down;
31837 out_down = ((unsigned)in_up >> (32 - amount)) | out_down;
31838 out_up = in_up << amount;
31841 out_down = in_down >> amount;
31842 out_down = (in_up << (32 - amount)) | out_down;
31844 out_down = ((signed)in_up >> (amount - 32)) | out_down;
31845 out_up = in_up << amount;
31848 out_down = in_down >> amount;
31849 out_down = (in_up << (32 - amount)) | out_down;
31851 out_down = ((unsigned)in_up >> (amount - 32)) | out_down;
31852 out_up = in_up << amount;
31854 The ARM and Thumb2 variants are the same but implemented slightly
31855 differently. If this were only called during expand we could just
31856 use the Thumb2 case and let combine do the right thing, but this
31857 can also be called from post-reload splitters. */
31859 emit_insn (SET (out_down
, LSHIFT (code
, in_down
, amount
)));
31861 if (!TARGET_THUMB2
)
31863 /* Emit code for ARM mode. */
31864 emit_insn (SET (out_down
,
31865 ORR (SHIFT (ASHIFT
, in_up
, scratch1
), out_down
)));
31866 if (code
== ASHIFTRT
)
31868 rtx_code_label
*done_label
= gen_label_rtx ();
31869 emit_jump_insn (BRANCH (LT
, done_label
));
31870 emit_insn (SET (out_down
, ORR (SHIFT (ASHIFTRT
, in_up
, scratch2
),
31872 emit_label (done_label
);
31875 emit_insn (SET (out_down
, ORR (SHIFT (LSHIFTRT
, in_up
, scratch2
),
31880 /* Emit code for Thumb2 mode.
31881 Thumb2 can't do shift and or in one insn. */
31882 emit_insn (SET (scratch1
, SHIFT (ASHIFT
, in_up
, scratch1
)));
31883 emit_insn (gen_iorsi3 (out_down
, out_down
, scratch1
));
31885 if (code
== ASHIFTRT
)
31887 rtx_code_label
*done_label
= gen_label_rtx ();
31888 emit_jump_insn (BRANCH (LT
, done_label
));
31889 emit_insn (SET (scratch2
, SHIFT (ASHIFTRT
, in_up
, scratch2
)));
31890 emit_insn (SET (out_down
, ORR (out_down
, scratch2
)));
31891 emit_label (done_label
);
31895 emit_insn (SET (scratch2
, SHIFT (LSHIFTRT
, in_up
, scratch2
)));
31896 emit_insn (gen_iorsi3 (out_down
, out_down
, scratch2
));
31900 emit_insn (SET (out_up
, SHIFT (code
, in_up
, amount
)));
31914 /* Returns true if the pattern is a valid symbolic address, which is either a
31915 symbol_ref or (symbol_ref + addend).
31917 According to the ARM ELF ABI, the initial addend of REL-type relocations
31918 processing MOVW and MOVT instructions is formed by interpreting the 16-bit
31919 literal field of the instruction as a 16-bit signed value in the range
31920 -32768 <= A < 32768.
31922 In Thumb-1 mode, we use upper/lower relocations which have an 8-bit
31923 unsigned range of 0 <= A < 256 as described in the AAELF32
31924 relocation handling documentation: REL-type relocations are encoded
31925 as unsigned in this case. */
31928 arm_valid_symbolic_address_p (rtx addr
)
31930 rtx xop0
, xop1
= NULL_RTX
;
31933 if (target_word_relocations
)
31936 if (SYMBOL_REF_P (tmp
) || LABEL_REF_P (tmp
))
31939 /* (const (plus: symbol_ref const_int)) */
31940 if (GET_CODE (addr
) == CONST
)
31941 tmp
= XEXP (addr
, 0);
31943 if (GET_CODE (tmp
) == PLUS
)
31945 xop0
= XEXP (tmp
, 0);
31946 xop1
= XEXP (tmp
, 1);
31948 if (GET_CODE (xop0
) == SYMBOL_REF
&& CONST_INT_P (xop1
))
31950 if (TARGET_THUMB1
&& !TARGET_HAVE_MOVT
)
31951 return IN_RANGE (INTVAL (xop1
), 0, 0xff);
31953 return IN_RANGE (INTVAL (xop1
), -0x8000, 0x7fff);
31960 /* Returns true if a valid comparison operation and makes
31961 the operands in a form that is valid. */
31963 arm_validize_comparison (rtx
*comparison
, rtx
* op1
, rtx
* op2
)
31965 enum rtx_code code
= GET_CODE (*comparison
);
31967 machine_mode mode
= (GET_MODE (*op1
) == VOIDmode
)
31968 ? GET_MODE (*op2
) : GET_MODE (*op1
);
31970 gcc_assert (GET_MODE (*op1
) != VOIDmode
|| GET_MODE (*op2
) != VOIDmode
);
31972 if (code
== UNEQ
|| code
== LTGT
)
31975 code_int
= (int)code
;
31976 arm_canonicalize_comparison (&code_int
, op1
, op2
, 0);
31977 PUT_CODE (*comparison
, (enum rtx_code
)code_int
);
31982 if (!arm_add_operand (*op1
, mode
))
31983 *op1
= force_reg (mode
, *op1
);
31984 if (!arm_add_operand (*op2
, mode
))
31985 *op2
= force_reg (mode
, *op2
);
31989 /* gen_compare_reg() will sort out any invalid operands. */
31993 if (!TARGET_VFP_FP16INST
)
31995 /* FP16 comparisons are done in SF mode. */
31997 *op1
= convert_to_mode (mode
, *op1
, 1);
31998 *op2
= convert_to_mode (mode
, *op2
, 1);
31999 /* Fall through. */
32002 if (!vfp_compare_operand (*op1
, mode
))
32003 *op1
= force_reg (mode
, *op1
);
32004 if (!vfp_compare_operand (*op2
, mode
))
32005 *op2
= force_reg (mode
, *op2
);
32015 /* Maximum number of instructions to set block of memory. */
32017 arm_block_set_max_insns (void)
32019 if (optimize_function_for_size_p (cfun
))
32022 return current_tune
->max_insns_inline_memset
;
32025 /* Return TRUE if it's profitable to set block of memory for
32026 non-vectorized case. VAL is the value to set the memory
32027 with. LENGTH is the number of bytes to set. ALIGN is the
32028 alignment of the destination memory in bytes. UNALIGNED_P
32029 is TRUE if we can only set the memory with instructions
32030 meeting alignment requirements. USE_STRD_P is TRUE if we
32031 can use strd to set the memory. */
32033 arm_block_set_non_vect_profit_p (rtx val
,
32034 unsigned HOST_WIDE_INT length
,
32035 unsigned HOST_WIDE_INT align
,
32036 bool unaligned_p
, bool use_strd_p
)
32039 /* For leftovers in bytes of 0-7, we can set the memory block using
32040 strb/strh/str with minimum instruction number. */
32041 const int leftover
[8] = {0, 1, 1, 2, 1, 2, 2, 3};
32045 num
= arm_const_inline_cost (SET
, val
);
32046 num
+= length
/ align
+ length
% align
;
32048 else if (use_strd_p
)
32050 num
= arm_const_double_inline_cost (val
);
32051 num
+= (length
>> 3) + leftover
[length
& 7];
32055 num
= arm_const_inline_cost (SET
, val
);
32056 num
+= (length
>> 2) + leftover
[length
& 3];
32059 /* We may be able to combine last pair STRH/STRB into a single STR
32060 by shifting one byte back. */
32061 if (unaligned_access
&& length
> 3 && (length
& 3) == 3)
32064 return (num
<= arm_block_set_max_insns ());
32067 /* Return TRUE if it's profitable to set block of memory for
32068 vectorized case. LENGTH is the number of bytes to set.
32069 ALIGN is the alignment of destination memory in bytes.
32070 MODE is the vector mode used to set the memory. */
32072 arm_block_set_vect_profit_p (unsigned HOST_WIDE_INT length
,
32073 unsigned HOST_WIDE_INT align
,
32077 bool unaligned_p
= ((align
& 3) != 0);
32078 unsigned int nelt
= GET_MODE_NUNITS (mode
);
32080 /* Instruction loading constant value. */
32082 /* Instructions storing the memory. */
32083 num
+= (length
+ nelt
- 1) / nelt
;
32084 /* Instructions adjusting the address expression. Only need to
32085 adjust address expression if it's 4 bytes aligned and bytes
32086 leftover can only be stored by mis-aligned store instruction. */
32087 if (!unaligned_p
&& (length
& 3) != 0)
32090 /* Store the first 16 bytes using vst1:v16qi for the aligned case. */
32091 if (!unaligned_p
&& mode
== V16QImode
)
32094 return (num
<= arm_block_set_max_insns ());
32097 /* Set a block of memory using vectorization instructions for the
32098 unaligned case. We fill the first LENGTH bytes of the memory
32099 area starting from DSTBASE with byte constant VALUE. ALIGN is
32100 the alignment requirement of memory. Return TRUE if succeeded. */
32102 arm_block_set_unaligned_vect (rtx dstbase
,
32103 unsigned HOST_WIDE_INT length
,
32104 unsigned HOST_WIDE_INT value
,
32105 unsigned HOST_WIDE_INT align
)
32107 unsigned int i
, nelt_v16
, nelt_v8
, nelt_mode
;
32110 rtx (*gen_func
) (rtx
, rtx
);
32112 unsigned HOST_WIDE_INT v
= value
;
32113 unsigned int offset
= 0;
32114 gcc_assert ((align
& 0x3) != 0);
32115 nelt_v8
= GET_MODE_NUNITS (V8QImode
);
32116 nelt_v16
= GET_MODE_NUNITS (V16QImode
);
32117 if (length
>= nelt_v16
)
32120 gen_func
= gen_movmisalignv16qi
;
32125 gen_func
= gen_movmisalignv8qi
;
32127 nelt_mode
= GET_MODE_NUNITS (mode
);
32128 gcc_assert (length
>= nelt_mode
);
32129 /* Skip if it isn't profitable. */
32130 if (!arm_block_set_vect_profit_p (length
, align
, mode
))
32133 dst
= copy_addr_to_reg (XEXP (dstbase
, 0));
32134 mem
= adjust_automodify_address (dstbase
, mode
, dst
, offset
);
32136 v
= sext_hwi (v
, BITS_PER_WORD
);
32138 reg
= gen_reg_rtx (mode
);
32139 val_vec
= gen_const_vec_duplicate (mode
, GEN_INT (v
));
32140 /* Emit instruction loading the constant value. */
32141 emit_move_insn (reg
, val_vec
);
32143 /* Handle nelt_mode bytes in a vector. */
32144 for (i
= 0; (i
+ nelt_mode
<= length
); i
+= nelt_mode
)
32146 emit_insn ((*gen_func
) (mem
, reg
));
32147 if (i
+ 2 * nelt_mode
<= length
)
32149 emit_insn (gen_add2_insn (dst
, GEN_INT (nelt_mode
)));
32150 offset
+= nelt_mode
;
32151 mem
= adjust_automodify_address (dstbase
, mode
, dst
, offset
);
32155 /* If there are not less than nelt_v8 bytes leftover, we must be in
32157 gcc_assert ((i
+ nelt_v8
) > length
|| mode
== V16QImode
);
32159 /* Handle (8, 16) bytes leftover. */
32160 if (i
+ nelt_v8
< length
)
32162 emit_insn (gen_add2_insn (dst
, GEN_INT (length
- i
)));
32163 offset
+= length
- i
;
32164 mem
= adjust_automodify_address (dstbase
, mode
, dst
, offset
);
32166 /* We are shifting bytes back, set the alignment accordingly. */
32167 if ((length
& 1) != 0 && align
>= 2)
32168 set_mem_align (mem
, BITS_PER_UNIT
);
32170 emit_insn (gen_movmisalignv16qi (mem
, reg
));
32172 /* Handle (0, 8] bytes leftover. */
32173 else if (i
< length
&& i
+ nelt_v8
>= length
)
32175 if (mode
== V16QImode
)
32176 reg
= gen_lowpart (V8QImode
, reg
);
32178 emit_insn (gen_add2_insn (dst
, GEN_INT ((length
- i
)
32179 + (nelt_mode
- nelt_v8
))));
32180 offset
+= (length
- i
) + (nelt_mode
- nelt_v8
);
32181 mem
= adjust_automodify_address (dstbase
, V8QImode
, dst
, offset
);
32183 /* We are shifting bytes back, set the alignment accordingly. */
32184 if ((length
& 1) != 0 && align
>= 2)
32185 set_mem_align (mem
, BITS_PER_UNIT
);
32187 emit_insn (gen_movmisalignv8qi (mem
, reg
));
32193 /* Set a block of memory using vectorization instructions for the
32194 aligned case. We fill the first LENGTH bytes of the memory area
32195 starting from DSTBASE with byte constant VALUE. ALIGN is the
32196 alignment requirement of memory. Return TRUE if succeeded. */
32198 arm_block_set_aligned_vect (rtx dstbase
,
32199 unsigned HOST_WIDE_INT length
,
32200 unsigned HOST_WIDE_INT value
,
32201 unsigned HOST_WIDE_INT align
)
32203 unsigned int i
, nelt_v8
, nelt_v16
, nelt_mode
;
32204 rtx dst
, addr
, mem
;
32207 unsigned int offset
= 0;
32209 gcc_assert ((align
& 0x3) == 0);
32210 nelt_v8
= GET_MODE_NUNITS (V8QImode
);
32211 nelt_v16
= GET_MODE_NUNITS (V16QImode
);
32212 if (length
>= nelt_v16
&& unaligned_access
&& !BYTES_BIG_ENDIAN
)
32217 nelt_mode
= GET_MODE_NUNITS (mode
);
32218 gcc_assert (length
>= nelt_mode
);
32219 /* Skip if it isn't profitable. */
32220 if (!arm_block_set_vect_profit_p (length
, align
, mode
))
32223 dst
= copy_addr_to_reg (XEXP (dstbase
, 0));
32225 reg
= gen_reg_rtx (mode
);
32226 val_vec
= gen_const_vec_duplicate (mode
, gen_int_mode (value
, QImode
));
32227 /* Emit instruction loading the constant value. */
32228 emit_move_insn (reg
, val_vec
);
32231 /* Handle first 16 bytes specially using vst1:v16qi instruction. */
32232 if (mode
== V16QImode
)
32234 mem
= adjust_automodify_address (dstbase
, mode
, dst
, offset
);
32235 emit_insn (gen_movmisalignv16qi (mem
, reg
));
32237 /* Handle (8, 16) bytes leftover using vst1:v16qi again. */
32238 if (i
+ nelt_v8
< length
&& i
+ nelt_v16
> length
)
32240 emit_insn (gen_add2_insn (dst
, GEN_INT (length
- nelt_mode
)));
32241 offset
+= length
- nelt_mode
;
32242 mem
= adjust_automodify_address (dstbase
, mode
, dst
, offset
);
32243 /* We are shifting bytes back, set the alignment accordingly. */
32244 if ((length
& 0x3) == 0)
32245 set_mem_align (mem
, BITS_PER_UNIT
* 4);
32246 else if ((length
& 0x1) == 0)
32247 set_mem_align (mem
, BITS_PER_UNIT
* 2);
32249 set_mem_align (mem
, BITS_PER_UNIT
);
32251 emit_insn (gen_movmisalignv16qi (mem
, reg
));
32254 /* Fall through for bytes leftover. */
32256 nelt_mode
= GET_MODE_NUNITS (mode
);
32257 reg
= gen_lowpart (V8QImode
, reg
);
32260 /* Handle 8 bytes in a vector. */
32261 for (; (i
+ nelt_mode
<= length
); i
+= nelt_mode
)
32263 addr
= plus_constant (Pmode
, dst
, i
);
32264 mem
= adjust_automodify_address (dstbase
, mode
, addr
, offset
+ i
);
32265 if (MEM_ALIGN (mem
) >= 2 * BITS_PER_WORD
)
32266 emit_move_insn (mem
, reg
);
32268 emit_insn (gen_unaligned_storev8qi (mem
, reg
));
32271 /* Handle single word leftover by shifting 4 bytes back. We can
32272 use aligned access for this case. */
32273 if (i
+ UNITS_PER_WORD
== length
)
32275 addr
= plus_constant (Pmode
, dst
, i
- UNITS_PER_WORD
);
32276 offset
+= i
- UNITS_PER_WORD
;
32277 mem
= adjust_automodify_address (dstbase
, mode
, addr
, offset
);
32278 /* We are shifting 4 bytes back, set the alignment accordingly. */
32279 if (align
> UNITS_PER_WORD
)
32280 set_mem_align (mem
, BITS_PER_UNIT
* UNITS_PER_WORD
);
32282 emit_insn (gen_unaligned_storev8qi (mem
, reg
));
32284 /* Handle (0, 4), (4, 8) bytes leftover by shifting bytes back.
32285 We have to use unaligned access for this case. */
32286 else if (i
< length
)
32288 emit_insn (gen_add2_insn (dst
, GEN_INT (length
- nelt_mode
)));
32289 offset
+= length
- nelt_mode
;
32290 mem
= adjust_automodify_address (dstbase
, mode
, dst
, offset
);
32291 /* We are shifting bytes back, set the alignment accordingly. */
32292 if ((length
& 1) == 0)
32293 set_mem_align (mem
, BITS_PER_UNIT
* 2);
32295 set_mem_align (mem
, BITS_PER_UNIT
);
32297 emit_insn (gen_movmisalignv8qi (mem
, reg
));
32303 /* Set a block of memory using plain strh/strb instructions, only
32304 using instructions allowed by ALIGN on processor. We fill the
32305 first LENGTH bytes of the memory area starting from DSTBASE
32306 with byte constant VALUE. ALIGN is the alignment requirement
32309 arm_block_set_unaligned_non_vect (rtx dstbase
,
32310 unsigned HOST_WIDE_INT length
,
32311 unsigned HOST_WIDE_INT value
,
32312 unsigned HOST_WIDE_INT align
)
32315 rtx dst
, addr
, mem
;
32316 rtx val_exp
, val_reg
, reg
;
32318 HOST_WIDE_INT v
= value
;
32320 gcc_assert (align
== 1 || align
== 2);
32323 v
|= (value
<< BITS_PER_UNIT
);
32325 v
= sext_hwi (v
, BITS_PER_WORD
);
32326 val_exp
= GEN_INT (v
);
32327 /* Skip if it isn't profitable. */
32328 if (!arm_block_set_non_vect_profit_p (val_exp
, length
,
32329 align
, true, false))
32332 dst
= copy_addr_to_reg (XEXP (dstbase
, 0));
32333 mode
= (align
== 2 ? HImode
: QImode
);
32334 val_reg
= force_reg (SImode
, val_exp
);
32335 reg
= gen_lowpart (mode
, val_reg
);
32337 for (i
= 0; (i
+ GET_MODE_SIZE (mode
) <= length
); i
+= GET_MODE_SIZE (mode
))
32339 addr
= plus_constant (Pmode
, dst
, i
);
32340 mem
= adjust_automodify_address (dstbase
, mode
, addr
, i
);
32341 emit_move_insn (mem
, reg
);
32344 /* Handle single byte leftover. */
32345 if (i
+ 1 == length
)
32347 reg
= gen_lowpart (QImode
, val_reg
);
32348 addr
= plus_constant (Pmode
, dst
, i
);
32349 mem
= adjust_automodify_address (dstbase
, QImode
, addr
, i
);
32350 emit_move_insn (mem
, reg
);
32354 gcc_assert (i
== length
);
32358 /* Set a block of memory using plain strd/str/strh/strb instructions,
32359 to permit unaligned copies on processors which support unaligned
32360 semantics for those instructions. We fill the first LENGTH bytes
32361 of the memory area starting from DSTBASE with byte constant VALUE.
32362 ALIGN is the alignment requirement of memory. */
32364 arm_block_set_aligned_non_vect (rtx dstbase
,
32365 unsigned HOST_WIDE_INT length
,
32366 unsigned HOST_WIDE_INT value
,
32367 unsigned HOST_WIDE_INT align
)
32370 rtx dst
, addr
, mem
;
32371 rtx val_exp
, val_reg
, reg
;
32372 unsigned HOST_WIDE_INT v
;
32375 use_strd_p
= (length
>= 2 * UNITS_PER_WORD
&& (align
& 3) == 0
32376 && TARGET_LDRD
&& current_tune
->prefer_ldrd_strd
);
32378 v
= (value
| (value
<< 8) | (value
<< 16) | (value
<< 24));
32379 if (length
< UNITS_PER_WORD
)
32380 v
&= (0xFFFFFFFF >> (UNITS_PER_WORD
- length
) * BITS_PER_UNIT
);
32383 v
|= (v
<< BITS_PER_WORD
);
32385 v
= sext_hwi (v
, BITS_PER_WORD
);
32387 val_exp
= GEN_INT (v
);
32388 /* Skip if it isn't profitable. */
32389 if (!arm_block_set_non_vect_profit_p (val_exp
, length
,
32390 align
, false, use_strd_p
))
32395 /* Try without strd. */
32396 v
= (v
>> BITS_PER_WORD
);
32397 v
= sext_hwi (v
, BITS_PER_WORD
);
32398 val_exp
= GEN_INT (v
);
32399 use_strd_p
= false;
32400 if (!arm_block_set_non_vect_profit_p (val_exp
, length
,
32401 align
, false, use_strd_p
))
32406 dst
= copy_addr_to_reg (XEXP (dstbase
, 0));
32407 /* Handle double words using strd if possible. */
32410 val_reg
= force_reg (DImode
, val_exp
);
32412 for (; (i
+ 8 <= length
); i
+= 8)
32414 addr
= plus_constant (Pmode
, dst
, i
);
32415 mem
= adjust_automodify_address (dstbase
, DImode
, addr
, i
);
32416 if (MEM_ALIGN (mem
) >= 2 * BITS_PER_WORD
)
32417 emit_move_insn (mem
, reg
);
32419 emit_insn (gen_unaligned_storedi (mem
, reg
));
32423 val_reg
= force_reg (SImode
, val_exp
);
32425 /* Handle words. */
32426 reg
= (use_strd_p
? gen_lowpart (SImode
, val_reg
) : val_reg
);
32427 for (; (i
+ 4 <= length
); i
+= 4)
32429 addr
= plus_constant (Pmode
, dst
, i
);
32430 mem
= adjust_automodify_address (dstbase
, SImode
, addr
, i
);
32431 if ((align
& 3) == 0)
32432 emit_move_insn (mem
, reg
);
32434 emit_insn (gen_unaligned_storesi (mem
, reg
));
32437 /* Merge last pair of STRH and STRB into a STR if possible. */
32438 if (unaligned_access
&& i
> 0 && (i
+ 3) == length
)
32440 addr
= plus_constant (Pmode
, dst
, i
- 1);
32441 mem
= adjust_automodify_address (dstbase
, SImode
, addr
, i
- 1);
32442 /* We are shifting one byte back, set the alignment accordingly. */
32443 if ((align
& 1) == 0)
32444 set_mem_align (mem
, BITS_PER_UNIT
);
32446 /* Most likely this is an unaligned access, and we can't tell at
32447 compilation time. */
32448 emit_insn (gen_unaligned_storesi (mem
, reg
));
32452 /* Handle half word leftover. */
32453 if (i
+ 2 <= length
)
32455 reg
= gen_lowpart (HImode
, val_reg
);
32456 addr
= plus_constant (Pmode
, dst
, i
);
32457 mem
= adjust_automodify_address (dstbase
, HImode
, addr
, i
);
32458 if ((align
& 1) == 0)
32459 emit_move_insn (mem
, reg
);
32461 emit_insn (gen_unaligned_storehi (mem
, reg
));
32466 /* Handle single byte leftover. */
32467 if (i
+ 1 == length
)
32469 reg
= gen_lowpart (QImode
, val_reg
);
32470 addr
= plus_constant (Pmode
, dst
, i
);
32471 mem
= adjust_automodify_address (dstbase
, QImode
, addr
, i
);
32472 emit_move_insn (mem
, reg
);
32478 /* Set a block of memory using vectorization instructions for both
32479 aligned and unaligned cases. We fill the first LENGTH bytes of
32480 the memory area starting from DSTBASE with byte constant VALUE.
32481 ALIGN is the alignment requirement of memory. */
32483 arm_block_set_vect (rtx dstbase
,
32484 unsigned HOST_WIDE_INT length
,
32485 unsigned HOST_WIDE_INT value
,
32486 unsigned HOST_WIDE_INT align
)
32488 /* Check whether we need to use unaligned store instruction. */
32489 if (((align
& 3) != 0 || (length
& 3) != 0)
32490 /* Check whether unaligned store instruction is available. */
32491 && (!unaligned_access
|| BYTES_BIG_ENDIAN
))
32494 if ((align
& 3) == 0)
32495 return arm_block_set_aligned_vect (dstbase
, length
, value
, align
);
32497 return arm_block_set_unaligned_vect (dstbase
, length
, value
, align
);
32500 /* Expand string store operation. Firstly we try to do that by using
32501 vectorization instructions, then try with ARM unaligned access and
32502 double-word store if profitable. OPERANDS[0] is the destination,
32503 OPERANDS[1] is the number of bytes, operands[2] is the value to
32504 initialize the memory, OPERANDS[3] is the known alignment of the
32507 arm_gen_setmem (rtx
*operands
)
32509 rtx dstbase
= operands
[0];
32510 unsigned HOST_WIDE_INT length
;
32511 unsigned HOST_WIDE_INT value
;
32512 unsigned HOST_WIDE_INT align
;
32514 if (!CONST_INT_P (operands
[2]) || !CONST_INT_P (operands
[1]))
32517 length
= UINTVAL (operands
[1]);
32521 value
= (UINTVAL (operands
[2]) & 0xFF);
32522 align
= UINTVAL (operands
[3]);
32523 if (TARGET_NEON
&& length
>= 8
32524 && current_tune
->string_ops_prefer_neon
32525 && arm_block_set_vect (dstbase
, length
, value
, align
))
32528 if (!unaligned_access
&& (align
& 3) != 0)
32529 return arm_block_set_unaligned_non_vect (dstbase
, length
, value
, align
);
32531 return arm_block_set_aligned_non_vect (dstbase
, length
, value
, align
);
32536 arm_macro_fusion_p (void)
32538 return current_tune
->fusible_ops
!= tune_params::FUSE_NOTHING
;
32541 /* Return true if the two back-to-back sets PREV_SET, CURR_SET are suitable
32542 for MOVW / MOVT macro fusion. */
32545 arm_sets_movw_movt_fusible_p (rtx prev_set
, rtx curr_set
)
32547 /* We are trying to fuse
32548 movw imm / movt imm
32549 instructions as a group that gets scheduled together. */
32551 rtx set_dest
= SET_DEST (curr_set
);
32553 if (GET_MODE (set_dest
) != SImode
)
32556 /* We are trying to match:
32557 prev (movw) == (set (reg r0) (const_int imm16))
32558 curr (movt) == (set (zero_extract (reg r0)
32561 (const_int imm16_1))
32563 prev (movw) == (set (reg r1)
32564 (high (symbol_ref ("SYM"))))
32565 curr (movt) == (set (reg r0)
32567 (symbol_ref ("SYM")))) */
32569 if (GET_CODE (set_dest
) == ZERO_EXTRACT
)
32571 if (CONST_INT_P (SET_SRC (curr_set
))
32572 && CONST_INT_P (SET_SRC (prev_set
))
32573 && REG_P (XEXP (set_dest
, 0))
32574 && REG_P (SET_DEST (prev_set
))
32575 && REGNO (XEXP (set_dest
, 0)) == REGNO (SET_DEST (prev_set
)))
32579 else if (GET_CODE (SET_SRC (curr_set
)) == LO_SUM
32580 && REG_P (SET_DEST (curr_set
))
32581 && REG_P (SET_DEST (prev_set
))
32582 && GET_CODE (SET_SRC (prev_set
)) == HIGH
32583 && REGNO (SET_DEST (curr_set
)) == REGNO (SET_DEST (prev_set
)))
32590 aarch_macro_fusion_pair_p (rtx_insn
* prev
, rtx_insn
* curr
)
32592 rtx prev_set
= single_set (prev
);
32593 rtx curr_set
= single_set (curr
);
32599 if (any_condjump_p (curr
))
32602 if (!arm_macro_fusion_p ())
32605 if (current_tune
->fusible_ops
& tune_params::FUSE_MOVW_MOVT
32606 && arm_sets_movw_movt_fusible_p (prev_set
, curr_set
))
32612 /* Return true iff the instruction fusion described by OP is enabled. */
32614 arm_fusion_enabled_p (tune_params::fuse_ops op
)
32616 return current_tune
->fusible_ops
& op
;
32619 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
32620 scheduled for speculative execution. Reject the long-running division
32621 and square-root instructions. */
32624 arm_sched_can_speculate_insn (rtx_insn
*insn
)
32626 switch (get_attr_type (insn
))
32634 case TYPE_NEON_FP_SQRT_S
:
32635 case TYPE_NEON_FP_SQRT_D
:
32636 case TYPE_NEON_FP_SQRT_S_Q
:
32637 case TYPE_NEON_FP_SQRT_D_Q
:
32638 case TYPE_NEON_FP_DIV_S
:
32639 case TYPE_NEON_FP_DIV_D
:
32640 case TYPE_NEON_FP_DIV_S_Q
:
32641 case TYPE_NEON_FP_DIV_D_Q
:
32648 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
32650 static unsigned HOST_WIDE_INT
32651 arm_asan_shadow_offset (void)
32653 return HOST_WIDE_INT_1U
<< 29;
32657 /* This is a temporary fix for PR60655. Ideally we need
32658 to handle most of these cases in the generic part but
32659 currently we reject minus (..) (sym_ref). We try to
32660 ameliorate the case with minus (sym_ref1) (sym_ref2)
32661 where they are in the same section. */
32664 arm_const_not_ok_for_debug_p (rtx p
)
32666 tree decl_op0
= NULL
;
32667 tree decl_op1
= NULL
;
32669 if (GET_CODE (p
) == UNSPEC
)
32671 if (GET_CODE (p
) == MINUS
)
32673 if (GET_CODE (XEXP (p
, 1)) == SYMBOL_REF
)
32675 decl_op1
= SYMBOL_REF_DECL (XEXP (p
, 1));
32677 && GET_CODE (XEXP (p
, 0)) == SYMBOL_REF
32678 && (decl_op0
= SYMBOL_REF_DECL (XEXP (p
, 0))))
32680 if ((VAR_P (decl_op1
)
32681 || TREE_CODE (decl_op1
) == CONST_DECL
)
32682 && (VAR_P (decl_op0
)
32683 || TREE_CODE (decl_op0
) == CONST_DECL
))
32684 return (get_variable_section (decl_op1
, false)
32685 != get_variable_section (decl_op0
, false));
32687 if (TREE_CODE (decl_op1
) == LABEL_DECL
32688 && TREE_CODE (decl_op0
) == LABEL_DECL
)
32689 return (DECL_CONTEXT (decl_op1
)
32690 != DECL_CONTEXT (decl_op0
));
32700 /* return TRUE if x is a reference to a value in a constant pool */
32702 arm_is_constant_pool_ref (rtx x
)
32705 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
32706 && CONSTANT_POOL_ADDRESS_P (XEXP (x
, 0)));
32709 /* Remember the last target of arm_set_current_function. */
32710 static GTY(()) tree arm_previous_fndecl
;
32712 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE. */
32715 save_restore_target_globals (tree new_tree
)
32717 /* If we have a previous state, use it. */
32718 if (TREE_TARGET_GLOBALS (new_tree
))
32719 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
32720 else if (new_tree
== target_option_default_node
)
32721 restore_target_globals (&default_target_globals
);
32724 /* Call target_reinit and save the state for TARGET_GLOBALS. */
32725 TREE_TARGET_GLOBALS (new_tree
) = save_target_globals_default_opts ();
32728 arm_option_params_internal ();
32731 /* Invalidate arm_previous_fndecl. */
32734 arm_reset_previous_fndecl (void)
32736 arm_previous_fndecl
= NULL_TREE
;
32739 /* Establish appropriate back-end context for processing the function
32740 FNDECL. The argument might be NULL to indicate processing at top
32741 level, outside of any function scope. */
32744 arm_set_current_function (tree fndecl
)
32746 if (!fndecl
|| fndecl
== arm_previous_fndecl
)
32749 tree old_tree
= (arm_previous_fndecl
32750 ? DECL_FUNCTION_SPECIFIC_TARGET (arm_previous_fndecl
)
32753 tree new_tree
= DECL_FUNCTION_SPECIFIC_TARGET (fndecl
);
32755 /* If current function has no attributes but previous one did,
32756 use the default node. */
32757 if (! new_tree
&& old_tree
)
32758 new_tree
= target_option_default_node
;
32760 /* If nothing to do return. #pragma GCC reset or #pragma GCC pop to
32761 the default have been handled by save_restore_target_globals from
32762 arm_pragma_target_parse. */
32763 if (old_tree
== new_tree
)
32766 arm_previous_fndecl
= fndecl
;
32768 /* First set the target options. */
32769 cl_target_option_restore (&global_options
, &global_options_set
,
32770 TREE_TARGET_OPTION (new_tree
));
32772 save_restore_target_globals (new_tree
);
32774 arm_override_options_after_change_1 (&global_options
, &global_options_set
);
32777 /* Implement TARGET_OPTION_PRINT. */
32780 arm_option_print (FILE *file
, int indent
, struct cl_target_option
*ptr
)
32782 int flags
= ptr
->x_target_flags
;
32783 const char *fpu_name
;
32785 fpu_name
= (ptr
->x_arm_fpu_index
== TARGET_FPU_auto
32786 ? "auto" : all_fpus
[ptr
->x_arm_fpu_index
].name
);
32788 fprintf (file
, "%*sselected isa %s\n", indent
, "",
32789 TARGET_THUMB2_P (flags
) ? "thumb2" :
32790 TARGET_THUMB_P (flags
) ? "thumb1" :
32793 if (ptr
->x_arm_arch_string
)
32794 fprintf (file
, "%*sselected architecture %s\n", indent
, "",
32795 ptr
->x_arm_arch_string
);
32797 if (ptr
->x_arm_cpu_string
)
32798 fprintf (file
, "%*sselected CPU %s\n", indent
, "",
32799 ptr
->x_arm_cpu_string
);
32801 if (ptr
->x_arm_tune_string
)
32802 fprintf (file
, "%*sselected tune %s\n", indent
, "",
32803 ptr
->x_arm_tune_string
);
32805 fprintf (file
, "%*sselected fpu %s\n", indent
, "", fpu_name
);
32808 /* Hook to determine if one function can safely inline another. */
32811 arm_can_inline_p (tree caller
, tree callee
)
32813 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
32814 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
32815 bool can_inline
= true;
32817 struct cl_target_option
*caller_opts
32818 = TREE_TARGET_OPTION (caller_tree
? caller_tree
32819 : target_option_default_node
);
32821 struct cl_target_option
*callee_opts
32822 = TREE_TARGET_OPTION (callee_tree
? callee_tree
32823 : target_option_default_node
);
32825 if (callee_opts
== caller_opts
)
32828 /* Callee's ISA features should be a subset of the caller's. */
32829 struct arm_build_target caller_target
;
32830 struct arm_build_target callee_target
;
32831 caller_target
.isa
= sbitmap_alloc (isa_num_bits
);
32832 callee_target
.isa
= sbitmap_alloc (isa_num_bits
);
32834 arm_configure_build_target (&caller_target
, caller_opts
, &global_options_set
,
32836 arm_configure_build_target (&callee_target
, callee_opts
, &global_options_set
,
32838 if (!bitmap_subset_p (callee_target
.isa
, caller_target
.isa
))
32839 can_inline
= false;
32841 sbitmap_free (caller_target
.isa
);
32842 sbitmap_free (callee_target
.isa
);
32844 /* OK to inline between different modes.
32845 Function with mode specific instructions, e.g using asm,
32846 must be explicitly protected with noinline. */
32850 /* Hook to fix function's alignment affected by target attribute. */
32853 arm_relayout_function (tree fndecl
)
32855 if (DECL_USER_ALIGN (fndecl
))
32858 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (fndecl
);
32861 callee_tree
= target_option_default_node
;
32863 struct cl_target_option
*opts
= TREE_TARGET_OPTION (callee_tree
);
32866 FUNCTION_ALIGNMENT (FUNCTION_BOUNDARY_P (opts
->x_target_flags
)));
32869 /* Inner function to process the attribute((target(...))), take an argument and
32870 set the current options from the argument. If we have a list, recursively
32871 go over the list. */
32874 arm_valid_target_attribute_rec (tree args
, struct gcc_options
*opts
)
32876 if (TREE_CODE (args
) == TREE_LIST
)
32880 for (; args
; args
= TREE_CHAIN (args
))
32881 if (TREE_VALUE (args
)
32882 && !arm_valid_target_attribute_rec (TREE_VALUE (args
), opts
))
32887 else if (TREE_CODE (args
) != STRING_CST
)
32889 error ("attribute %<target%> argument not a string");
32893 char *argstr
= ASTRDUP (TREE_STRING_POINTER (args
));
32896 while ((q
= strtok (argstr
, ",")) != NULL
)
32899 if (!strcmp (q
, "thumb"))
32901 opts
->x_target_flags
|= MASK_THUMB
;
32902 if (TARGET_FDPIC
&& !arm_arch_thumb2
)
32903 sorry ("FDPIC mode is not supported in Thumb-1 mode");
32906 else if (!strcmp (q
, "arm"))
32907 opts
->x_target_flags
&= ~MASK_THUMB
;
32909 else if (!strcmp (q
, "general-regs-only"))
32910 opts
->x_target_flags
|= MASK_GENERAL_REGS_ONLY
;
32912 else if (!strncmp (q
, "fpu=", 4))
32915 if (! opt_enum_arg_to_value (OPT_mfpu_
, q
+ 4,
32916 &fpu_index
, CL_TARGET
))
32918 error ("invalid fpu for target attribute or pragma %qs", q
);
32921 if (fpu_index
== TARGET_FPU_auto
)
32923 /* This doesn't really make sense until we support
32924 general dynamic selection of the architecture and all
32926 sorry ("auto fpu selection not currently permitted here");
32929 opts
->x_arm_fpu_index
= (enum fpu_type
) fpu_index
;
32931 else if (!strncmp (q
, "arch=", 5))
32933 char *arch
= q
+ 5;
32934 const arch_option
*arm_selected_arch
32935 = arm_parse_arch_option_name (all_architectures
, "arch", arch
);
32937 if (!arm_selected_arch
)
32939 error ("invalid architecture for target attribute or pragma %qs",
32944 opts
->x_arm_arch_string
= xstrndup (arch
, strlen (arch
));
32946 else if (q
[0] == '+')
32948 opts
->x_arm_arch_string
32949 = xasprintf ("%s%s", opts
->x_arm_arch_string
, q
);
32953 error ("unknown target attribute or pragma %qs", q
);
32961 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
32964 arm_valid_target_attribute_tree (tree args
, struct gcc_options
*opts
,
32965 struct gcc_options
*opts_set
)
32967 struct cl_target_option cl_opts
;
32969 if (!arm_valid_target_attribute_rec (args
, opts
))
32972 cl_target_option_save (&cl_opts
, opts
, opts_set
);
32973 arm_configure_build_target (&arm_active_target
, &cl_opts
, opts_set
, false);
32974 arm_option_check_internal (opts
);
32975 /* Do any overrides, such as global options arch=xxx.
32976 We do this since arm_active_target was overridden. */
32977 arm_option_reconfigure_globals ();
32978 arm_options_perform_arch_sanity_checks ();
32979 arm_option_override_internal (opts
, opts_set
);
32981 return build_target_option_node (opts
, opts_set
);
32985 add_attribute (const char * mode
, tree
*attributes
)
32987 size_t len
= strlen (mode
);
32988 tree value
= build_string (len
, mode
);
32990 TREE_TYPE (value
) = build_array_type (char_type_node
,
32991 build_index_type (size_int (len
)));
32993 *attributes
= tree_cons (get_identifier ("target"),
32994 build_tree_list (NULL_TREE
, value
),
32998 /* For testing. Insert thumb or arm modes alternatively on functions. */
33001 arm_insert_attributes (tree fndecl
, tree
* attributes
)
33005 if (! TARGET_FLIP_THUMB
)
33008 if (TREE_CODE (fndecl
) != FUNCTION_DECL
|| DECL_EXTERNAL(fndecl
)
33009 || fndecl_built_in_p (fndecl
) || DECL_ARTIFICIAL (fndecl
))
33012 /* Nested definitions must inherit mode. */
33013 if (current_function_decl
)
33015 mode
= TARGET_THUMB
? "thumb" : "arm";
33016 add_attribute (mode
, attributes
);
33020 /* If there is already a setting don't change it. */
33021 if (lookup_attribute ("target", *attributes
) != NULL
)
33024 mode
= thumb_flipper
? "thumb" : "arm";
33025 add_attribute (mode
, attributes
);
33027 thumb_flipper
= !thumb_flipper
;
33030 /* Hook to validate attribute((target("string"))). */
33033 arm_valid_target_attribute_p (tree fndecl
, tree
ARG_UNUSED (name
),
33034 tree args
, int ARG_UNUSED (flags
))
33037 struct gcc_options func_options
, func_options_set
;
33038 tree cur_tree
, new_optimize
;
33039 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
33041 /* Get the optimization options of the current function. */
33042 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
33044 /* If the function changed the optimization levels as well as setting target
33045 options, start with the optimizations specified. */
33046 if (!func_optimize
)
33047 func_optimize
= optimization_default_node
;
33049 /* Init func_options. */
33050 memset (&func_options
, 0, sizeof (func_options
));
33051 init_options_struct (&func_options
, NULL
);
33052 lang_hooks
.init_options_struct (&func_options
);
33053 memset (&func_options_set
, 0, sizeof (func_options_set
));
33055 /* Initialize func_options to the defaults. */
33056 cl_optimization_restore (&func_options
, &func_options_set
,
33057 TREE_OPTIMIZATION (func_optimize
));
33059 cl_target_option_restore (&func_options
, &func_options_set
,
33060 TREE_TARGET_OPTION (target_option_default_node
));
33062 /* Set func_options flags with new target mode. */
33063 cur_tree
= arm_valid_target_attribute_tree (args
, &func_options
,
33064 &func_options_set
);
33066 if (cur_tree
== NULL_TREE
)
33069 new_optimize
= build_optimization_node (&func_options
, &func_options_set
);
33071 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = cur_tree
;
33073 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
33078 /* Match an ISA feature bitmap to a named FPU. We always use the
33079 first entry that exactly matches the feature set, so that we
33080 effectively canonicalize the FPU name for the assembler. */
33082 arm_identify_fpu_from_isa (sbitmap isa
)
33084 auto_sbitmap
fpubits (isa_num_bits
);
33085 auto_sbitmap
cand_fpubits (isa_num_bits
);
33087 bitmap_and (fpubits
, isa
, isa_all_fpubits_internal
);
33089 /* If there are no ISA feature bits relating to the FPU, we must be
33090 doing soft-float. */
33091 if (bitmap_empty_p (fpubits
))
33094 for (unsigned int i
= 0; i
< TARGET_FPU_auto
; i
++)
33096 arm_initialize_isa (cand_fpubits
, all_fpus
[i
].isa_bits
);
33097 if (bitmap_equal_p (fpubits
, cand_fpubits
))
33098 return all_fpus
[i
].name
;
33100 /* We must find an entry, or things have gone wrong. */
33101 gcc_unreachable ();
33104 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
33105 by the function fndecl. */
33107 arm_declare_function_name (FILE *stream
, const char *name
, tree decl
)
33109 tree target_parts
= DECL_FUNCTION_SPECIFIC_TARGET (decl
);
33111 struct cl_target_option
*targ_options
;
33113 targ_options
= TREE_TARGET_OPTION (target_parts
);
33115 targ_options
= TREE_TARGET_OPTION (target_option_current_node
);
33116 gcc_assert (targ_options
);
33118 /* Only update the assembler .arch string if it is distinct from the last
33119 such string we printed. arch_to_print is set conditionally in case
33120 targ_options->x_arm_arch_string is NULL which can be the case
33121 when cc1 is invoked directly without passing -march option. */
33122 std::string arch_to_print
;
33123 if (targ_options
->x_arm_arch_string
)
33124 arch_to_print
= targ_options
->x_arm_arch_string
;
33126 if (arch_to_print
!= arm_last_printed_arch_string
)
33128 std::string arch_name
33129 = arch_to_print
.substr (0, arch_to_print
.find ("+"));
33130 asm_fprintf (asm_out_file
, "\t.arch %s\n", arch_name
.c_str ());
33131 const arch_option
*arch
33132 = arm_parse_arch_option_name (all_architectures
, "-march",
33133 targ_options
->x_arm_arch_string
);
33134 auto_sbitmap
opt_bits (isa_num_bits
);
33137 if (arch
->common
.extensions
)
33139 for (const struct cpu_arch_extension
*opt
= arch
->common
.extensions
;
33145 arm_initialize_isa (opt_bits
, opt
->isa_bits
);
33146 /* For the cases "-march=armv8.1-m.main+mve -mfloat-abi=soft"
33147 and "-march=armv8.1-m.main+mve.fp -mfloat-abi=soft" MVE and
33148 MVE with floating point instructions is disabled. So the
33149 following check restricts the printing of ".arch_extension
33150 mve" and ".arch_extension fp" (for mve.fp) in the assembly
33151 file. MVE needs this special behaviour because the
33152 feature bit "mve" and "mve_float" are not part of
33153 "fpu bits", so they are not cleared when -mfloat-abi=soft
33154 (i.e nofp) but the marco TARGET_HAVE_MVE and
33155 TARGET_HAVE_MVE_FLOAT are disabled. */
33156 if ((bitmap_bit_p (opt_bits
, isa_bit_mve
) && !TARGET_HAVE_MVE
)
33157 || (bitmap_bit_p (opt_bits
, isa_bit_mve_float
)
33158 && !TARGET_HAVE_MVE_FLOAT
))
33160 if (bitmap_subset_p (opt_bits
, arm_active_target
.isa
)
33161 && !bitmap_subset_p (opt_bits
, isa_all_fpubits_internal
))
33162 asm_fprintf (asm_out_file
, "\t.arch_extension %s\n",
33168 arm_last_printed_arch_string
= arch_to_print
;
33171 fprintf (stream
, "\t.syntax unified\n");
33175 if (is_called_in_ARM_mode (decl
)
33176 || (TARGET_THUMB1
&& !TARGET_THUMB1_ONLY
33177 && cfun
->is_thunk
))
33178 fprintf (stream
, "\t.code 32\n");
33179 else if (TARGET_THUMB1
)
33180 fprintf (stream
, "\t.code\t16\n\t.thumb_func\n");
33182 fprintf (stream
, "\t.thumb\n\t.thumb_func\n");
33185 fprintf (stream
, "\t.arm\n");
33187 std::string fpu_to_print
33188 = TARGET_SOFT_FLOAT
33189 ? "softvfp" : arm_identify_fpu_from_isa (arm_active_target
.isa
);
33191 if (!(!strcmp (fpu_to_print
.c_str (), "softvfp") && TARGET_VFP_BASE
)
33192 && (fpu_to_print
!= arm_last_printed_arch_string
))
33194 asm_fprintf (asm_out_file
, "\t.fpu %s\n", fpu_to_print
.c_str ());
33195 arm_last_printed_fpu_string
= fpu_to_print
;
33198 if (TARGET_POKE_FUNCTION_NAME
)
33199 arm_poke_function_name (stream
, (const char *) name
);
33202 /* If MEM is in the form of [base+offset], extract the two parts
33203 of address and set to BASE and OFFSET, otherwise return false
33204 after clearing BASE and OFFSET. */
33207 extract_base_offset_in_addr (rtx mem
, rtx
*base
, rtx
*offset
)
33211 gcc_assert (MEM_P (mem
));
33213 addr
= XEXP (mem
, 0);
33215 /* Strip off const from addresses like (const (addr)). */
33216 if (GET_CODE (addr
) == CONST
)
33217 addr
= XEXP (addr
, 0);
33222 *offset
= const0_rtx
;
33226 if (GET_CODE (addr
) == PLUS
33227 && GET_CODE (XEXP (addr
, 0)) == REG
33228 && CONST_INT_P (XEXP (addr
, 1)))
33230 *base
= XEXP (addr
, 0);
33231 *offset
= XEXP (addr
, 1);
33236 *offset
= NULL_RTX
;
33241 /* If INSN is a load or store of address in the form of [base+offset],
33242 extract the two parts and set to BASE and OFFSET. IS_LOAD is set
33243 to TRUE if it's a load. Return TRUE if INSN is such an instruction,
33244 otherwise return FALSE. */
33247 fusion_load_store (rtx_insn
*insn
, rtx
*base
, rtx
*offset
, bool *is_load
)
33251 gcc_assert (INSN_P (insn
));
33252 x
= PATTERN (insn
);
33253 if (GET_CODE (x
) != SET
)
33257 dest
= SET_DEST (x
);
33258 if (REG_P (src
) && MEM_P (dest
))
33261 extract_base_offset_in_addr (dest
, base
, offset
);
33263 else if (MEM_P (src
) && REG_P (dest
))
33266 extract_base_offset_in_addr (src
, base
, offset
);
33271 return (*base
!= NULL_RTX
&& *offset
!= NULL_RTX
);
33274 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
33276 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
33277 and PRI are only calculated for these instructions. For other instruction,
33278 FUSION_PRI and PRI are simply set to MAX_PRI. In the future, other kind
33279 instruction fusion can be supported by returning different priorities.
33281 It's important that irrelevant instructions get the largest FUSION_PRI. */
33284 arm_sched_fusion_priority (rtx_insn
*insn
, int max_pri
,
33285 int *fusion_pri
, int *pri
)
33291 gcc_assert (INSN_P (insn
));
33294 if (!fusion_load_store (insn
, &base
, &offset
, &is_load
))
33301 /* Load goes first. */
33303 *fusion_pri
= tmp
- 1;
33305 *fusion_pri
= tmp
- 2;
33309 /* INSN with smaller base register goes first. */
33310 tmp
-= ((REGNO (base
) & 0xff) << 20);
33312 /* INSN with smaller offset goes first. */
33313 off_val
= (int)(INTVAL (offset
));
33315 tmp
-= (off_val
& 0xfffff);
33317 tmp
+= ((- off_val
) & 0xfffff);
33324 /* Construct and return a PARALLEL RTX vector with elements numbering the
33325 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
33326 the vector - from the perspective of the architecture. This does not
33327 line up with GCC's perspective on lane numbers, so we end up with
33328 different masks depending on our target endian-ness. The diagram
33329 below may help. We must draw the distinction when building masks
33330 which select one half of the vector. An instruction selecting
33331 architectural low-lanes for a big-endian target, must be described using
33332 a mask selecting GCC high-lanes.
33334 Big-Endian Little-Endian
33336 GCC 0 1 2 3 3 2 1 0
33337 | x | x | x | x | | x | x | x | x |
33338 Architecture 3 2 1 0 3 2 1 0
33340 Low Mask: { 2, 3 } { 0, 1 }
33341 High Mask: { 0, 1 } { 2, 3 }
33345 arm_simd_vect_par_cnst_half (machine_mode mode
, bool high
)
33347 int nunits
= GET_MODE_NUNITS (mode
);
33348 rtvec v
= rtvec_alloc (nunits
/ 2);
33349 int high_base
= nunits
/ 2;
33355 if (BYTES_BIG_ENDIAN
)
33356 base
= high
? low_base
: high_base
;
33358 base
= high
? high_base
: low_base
;
33360 for (i
= 0; i
< nunits
/ 2; i
++)
33361 RTVEC_ELT (v
, i
) = GEN_INT (base
+ i
);
33363 t1
= gen_rtx_PARALLEL (mode
, v
);
33367 /* Check OP for validity as a PARALLEL RTX vector with elements
33368 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
33369 from the perspective of the architecture. See the diagram above
33370 arm_simd_vect_par_cnst_half_p for more details. */
33373 arm_simd_check_vect_par_cnst_half_p (rtx op
, machine_mode mode
,
33376 rtx ideal
= arm_simd_vect_par_cnst_half (mode
, high
);
33377 HOST_WIDE_INT count_op
= XVECLEN (op
, 0);
33378 HOST_WIDE_INT count_ideal
= XVECLEN (ideal
, 0);
33381 if (!VECTOR_MODE_P (mode
))
33384 if (count_op
!= count_ideal
)
33387 for (i
= 0; i
< count_ideal
; i
++)
33389 rtx elt_op
= XVECEXP (op
, 0, i
);
33390 rtx elt_ideal
= XVECEXP (ideal
, 0, i
);
33392 if (!CONST_INT_P (elt_op
)
33393 || INTVAL (elt_ideal
) != INTVAL (elt_op
))
33399 /* Can output mi_thunk for all cases except for non-zero vcall_offset
33402 arm_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
, HOST_WIDE_INT vcall_offset
,
33405 /* For now, we punt and not handle this for TARGET_THUMB1. */
33406 if (vcall_offset
&& TARGET_THUMB1
)
33409 /* Otherwise ok. */
33413 /* Generate RTL for a conditional branch with rtx comparison CODE in
33414 mode CC_MODE. The destination of the unlikely conditional branch
33418 arm_gen_unlikely_cbranch (enum rtx_code code
, machine_mode cc_mode
,
33422 x
= gen_rtx_fmt_ee (code
, VOIDmode
,
33423 gen_rtx_REG (cc_mode
, CC_REGNUM
),
33426 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
,
33427 gen_rtx_LABEL_REF (VOIDmode
, label_ref
),
33429 emit_unlikely_jump (gen_rtx_SET (pc_rtx
, x
));
33432 /* Implement the TARGET_ASM_ELF_FLAGS_NUMERIC hook.
33434 For pure-code sections there is no letter code for this attribute, so
33435 output all the section flags numerically when this is needed. */
33438 arm_asm_elf_flags_numeric (unsigned int flags
, unsigned int *num
)
33441 if (flags
& SECTION_ARM_PURECODE
)
33445 if (!(flags
& SECTION_DEBUG
))
33447 if (flags
& SECTION_EXCLUDE
)
33448 *num
|= 0x80000000;
33449 if (flags
& SECTION_WRITE
)
33451 if (flags
& SECTION_CODE
)
33453 if (flags
& SECTION_MERGE
)
33455 if (flags
& SECTION_STRINGS
)
33457 if (flags
& SECTION_TLS
)
33459 if (HAVE_COMDAT_GROUP
&& (flags
& SECTION_LINKONCE
))
33468 /* Implement the TARGET_ASM_FUNCTION_SECTION hook.
33470 If pure-code is passed as an option, make sure all functions are in
33471 sections that have the SHF_ARM_PURECODE attribute. */
33474 arm_function_section (tree decl
, enum node_frequency freq
,
33475 bool startup
, bool exit
)
33477 const char * section_name
;
33480 if (!decl
|| TREE_CODE (decl
) != FUNCTION_DECL
)
33481 return default_function_section (decl
, freq
, startup
, exit
);
33483 if (!target_pure_code
)
33484 return default_function_section (decl
, freq
, startup
, exit
);
33487 section_name
= DECL_SECTION_NAME (decl
);
33489 /* If a function is not in a named section then it falls under the 'default'
33490 text section, also known as '.text'. We can preserve previous behavior as
33491 the default text section already has the SHF_ARM_PURECODE section
33495 section
*default_sec
= default_function_section (decl
, freq
, startup
,
33498 /* If default_sec is not null, then it must be a special section like for
33499 example .text.startup. We set the pure-code attribute and return the
33500 same section to preserve existing behavior. */
33502 default_sec
->common
.flags
|= SECTION_ARM_PURECODE
;
33503 return default_sec
;
33506 /* Otherwise look whether a section has already been created with
33508 sec
= get_named_section (decl
, section_name
, 0);
33510 /* If that is not the case passing NULL as the section's name to
33511 'get_named_section' will create a section with the declaration's
33513 sec
= get_named_section (decl
, NULL
, 0);
33515 /* Set the SHF_ARM_PURECODE attribute. */
33516 sec
->common
.flags
|= SECTION_ARM_PURECODE
;
33521 /* Implements the TARGET_SECTION_FLAGS hook.
33523 If DECL is a function declaration and pure-code is passed as an option
33524 then add the SFH_ARM_PURECODE attribute to the section flags. NAME is the
33525 section's name and RELOC indicates whether the declarations initializer may
33526 contain runtime relocations. */
33528 static unsigned int
33529 arm_elf_section_type_flags (tree decl
, const char *name
, int reloc
)
33531 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
33533 if (decl
&& TREE_CODE (decl
) == FUNCTION_DECL
&& target_pure_code
)
33534 flags
|= SECTION_ARM_PURECODE
;
33539 /* Generate call to __aeabi_[mode]divmod (op0, op1). */
33542 arm_expand_divmod_libfunc (rtx libfunc
, machine_mode mode
,
33544 rtx
*quot_p
, rtx
*rem_p
)
33546 if (mode
== SImode
)
33547 gcc_assert (!TARGET_IDIV
);
33549 scalar_int_mode libval_mode
33550 = smallest_int_mode_for_size (2 * GET_MODE_BITSIZE (mode
));
33552 rtx libval
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
33553 libval_mode
, op0
, mode
, op1
, mode
);
33555 rtx quotient
= simplify_gen_subreg (mode
, libval
, libval_mode
, 0);
33556 rtx remainder
= simplify_gen_subreg (mode
, libval
, libval_mode
,
33557 GET_MODE_SIZE (mode
));
33559 gcc_assert (quotient
);
33560 gcc_assert (remainder
);
33562 *quot_p
= quotient
;
33563 *rem_p
= remainder
;
33566 /* This function checks for the availability of the coprocessor builtin passed
33567 in BUILTIN for the current target. Returns true if it is available and
33568 false otherwise. If a BUILTIN is passed for which this function has not
33569 been implemented it will cause an exception. */
33572 arm_coproc_builtin_available (enum unspecv builtin
)
33574 /* None of these builtins are available in Thumb mode if the target only
33575 supports Thumb-1. */
33593 case VUNSPEC_LDC2L
:
33595 case VUNSPEC_STC2L
:
33598 /* Only present in ARMv5*, ARMv6 (but not ARMv6-M), ARMv7* and
33605 /* Only present in ARMv5TE, ARMv6 (but not ARMv6-M), ARMv7* and
33607 if (arm_arch6
|| arm_arch5te
)
33610 case VUNSPEC_MCRR2
:
33611 case VUNSPEC_MRRC2
:
33616 gcc_unreachable ();
33621 /* This function returns true if OP is a valid memory operand for the ldc and
33622 stc coprocessor instructions and false otherwise. */
33625 arm_coproc_ldc_stc_legitimate_address (rtx op
)
33627 HOST_WIDE_INT range
;
33628 /* Has to be a memory operand. */
33634 /* We accept registers. */
33638 switch GET_CODE (op
)
33642 /* Or registers with an offset. */
33643 if (!REG_P (XEXP (op
, 0)))
33648 /* The offset must be an immediate though. */
33649 if (!CONST_INT_P (op
))
33652 range
= INTVAL (op
);
33654 /* Within the range of [-1020,1020]. */
33655 if (!IN_RANGE (range
, -1020, 1020))
33658 /* And a multiple of 4. */
33659 return (range
% 4) == 0;
33665 return REG_P (XEXP (op
, 0));
33667 gcc_unreachable ();
33672 /* Return the diagnostic message string if conversion from FROMTYPE to
33673 TOTYPE is not allowed, NULL otherwise. */
33675 static const char *
33676 arm_invalid_conversion (const_tree fromtype
, const_tree totype
)
33678 if (element_mode (fromtype
) != element_mode (totype
))
33680 /* Do no allow conversions to/from BFmode scalar types. */
33681 if (TYPE_MODE (fromtype
) == BFmode
)
33682 return N_("invalid conversion from type %<bfloat16_t%>");
33683 if (TYPE_MODE (totype
) == BFmode
)
33684 return N_("invalid conversion to type %<bfloat16_t%>");
33687 /* Conversion allowed. */
33691 /* Return the diagnostic message string if the unary operation OP is
33692 not permitted on TYPE, NULL otherwise. */
33694 static const char *
33695 arm_invalid_unary_op (int op
, const_tree type
)
33697 /* Reject all single-operand operations on BFmode except for &. */
33698 if (element_mode (type
) == BFmode
&& op
!= ADDR_EXPR
)
33699 return N_("operation not permitted on type %<bfloat16_t%>");
33701 /* Operation allowed. */
33705 /* Return the diagnostic message string if the binary operation OP is
33706 not permitted on TYPE1 and TYPE2, NULL otherwise. */
33708 static const char *
33709 arm_invalid_binary_op (int op ATTRIBUTE_UNUSED
, const_tree type1
,
33712 /* Reject all 2-operand operations on BFmode. */
33713 if (element_mode (type1
) == BFmode
33714 || element_mode (type2
) == BFmode
)
33715 return N_("operation not permitted on type %<bfloat16_t%>");
33717 /* Operation allowed. */
33721 /* Implement TARGET_CAN_CHANGE_MODE_CLASS.
33723 In VFPv1, VFP registers could only be accessed in the mode they were
33724 set, so subregs would be invalid there. However, we don't support
33725 VFPv1 at the moment, and the restriction was lifted in VFPv2.
33727 In big-endian mode, modes greater than word size (i.e. DFmode) are stored in
33728 VFP registers in little-endian order. We can't describe that accurately to
33729 GCC, so avoid taking subregs of such values.
33731 The only exception is going from a 128-bit to a 64-bit type. In that
33732 case the data layout happens to be consistent for big-endian, so we
33733 explicitly allow that case. */
33736 arm_can_change_mode_class (machine_mode from
, machine_mode to
,
33737 reg_class_t rclass
)
33740 && !(GET_MODE_SIZE (from
) == 16 && GET_MODE_SIZE (to
) == 8)
33741 && (GET_MODE_SIZE (from
) > UNITS_PER_WORD
33742 || GET_MODE_SIZE (to
) > UNITS_PER_WORD
)
33743 && reg_classes_intersect_p (VFP_REGS
, rclass
))
33748 /* Implement TARGET_CONSTANT_ALIGNMENT. Make strings word-aligned so
33749 strcpy from constants will be faster. */
33751 static HOST_WIDE_INT
33752 arm_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
33754 unsigned int factor
= (TARGET_THUMB
|| ! arm_tune_xscale
? 1 : 2);
33755 if (TREE_CODE (exp
) == STRING_CST
&& !optimize_size
)
33756 return MAX (align
, BITS_PER_WORD
* factor
);
33760 /* Emit a speculation barrier on target architectures that do not have
33761 DSB/ISB directly. Such systems probably don't need a barrier
33762 themselves, but if the code is ever run on a later architecture, it
33763 might become a problem. */
33765 arm_emit_speculation_barrier_function ()
33767 emit_library_call (speculation_barrier_libfunc
, LCT_NORMAL
, VOIDmode
);
33770 /* Have we recorded an explicit access to the Q bit of APSR?. */
33772 arm_q_bit_access (void)
33774 if (cfun
&& cfun
->decl
)
33775 return lookup_attribute ("acle qbit",
33776 DECL_ATTRIBUTES (cfun
->decl
));
33780 /* Have we recorded an explicit access to the GE bits of PSTATE?. */
33782 arm_ge_bits_access (void)
33784 if (cfun
&& cfun
->decl
)
33785 return lookup_attribute ("acle gebits",
33786 DECL_ATTRIBUTES (cfun
->decl
));
33790 /* NULL if insn INSN is valid within a low-overhead loop.
33791 Otherwise return why doloop cannot be applied. */
33793 static const char *
33794 arm_invalid_within_doloop (const rtx_insn
*insn
)
33796 if (!TARGET_HAVE_LOB
)
33797 return default_invalid_within_doloop (insn
);
33800 return "Function call in the loop.";
33802 if (reg_mentioned_p (gen_rtx_REG (SImode
, LR_REGNUM
), insn
))
33803 return "LR is used inside loop.";
33809 arm_target_insn_ok_for_lob (rtx insn
)
33811 basic_block bb
= BLOCK_FOR_INSN (insn
);
33812 /* Make sure the basic block of the target insn is a simple latch
33813 having as single predecessor and successor the body of the loop
33814 itself. Only simple loops with a single basic block as body are
33815 supported for 'low over head loop' making sure that LE target is
33816 above LE itself in the generated code. */
33818 return single_succ_p (bb
)
33819 && single_pred_p (bb
)
33820 && single_succ_edge (bb
)->dest
== single_pred_edge (bb
)->src
33821 && contains_no_active_insn_p (bb
);
33825 namespace selftest
{
33827 /* Scan the static data tables generated by parsecpu.awk looking for
33828 potential issues with the data. We primarily check for
33829 inconsistencies in the option extensions at present (extensions
33830 that duplicate others but aren't marked as aliases). Furthermore,
33831 for correct canonicalization later options must never be a subset
33832 of an earlier option. Any extension should also only specify other
33833 feature bits and never an architecture bit. The architecture is inferred
33834 from the declaration of the extension. */
33836 arm_test_cpu_arch_data (void)
33838 const arch_option
*arch
;
33839 const cpu_option
*cpu
;
33840 auto_sbitmap
target_isa (isa_num_bits
);
33841 auto_sbitmap
isa1 (isa_num_bits
);
33842 auto_sbitmap
isa2 (isa_num_bits
);
33844 for (arch
= all_architectures
; arch
->common
.name
!= NULL
; ++arch
)
33846 const cpu_arch_extension
*ext1
, *ext2
;
33848 if (arch
->common
.extensions
== NULL
)
33851 arm_initialize_isa (target_isa
, arch
->common
.isa_bits
);
33853 for (ext1
= arch
->common
.extensions
; ext1
->name
!= NULL
; ++ext1
)
33858 arm_initialize_isa (isa1
, ext1
->isa_bits
);
33859 for (ext2
= ext1
+ 1; ext2
->name
!= NULL
; ++ext2
)
33861 if (ext2
->alias
|| ext1
->remove
!= ext2
->remove
)
33864 arm_initialize_isa (isa2
, ext2
->isa_bits
);
33865 /* If the option is a subset of the parent option, it doesn't
33866 add anything and so isn't useful. */
33867 ASSERT_TRUE (!bitmap_subset_p (isa2
, isa1
));
33869 /* If the extension specifies any architectural bits then
33870 disallow it. Extensions should only specify feature bits. */
33871 ASSERT_TRUE (!bitmap_intersect_p (isa2
, target_isa
));
33876 for (cpu
= all_cores
; cpu
->common
.name
!= NULL
; ++cpu
)
33878 const cpu_arch_extension
*ext1
, *ext2
;
33880 if (cpu
->common
.extensions
== NULL
)
33883 arm_initialize_isa (target_isa
, arch
->common
.isa_bits
);
33885 for (ext1
= cpu
->common
.extensions
; ext1
->name
!= NULL
; ++ext1
)
33890 arm_initialize_isa (isa1
, ext1
->isa_bits
);
33891 for (ext2
= ext1
+ 1; ext2
->name
!= NULL
; ++ext2
)
33893 if (ext2
->alias
|| ext1
->remove
!= ext2
->remove
)
33896 arm_initialize_isa (isa2
, ext2
->isa_bits
);
33897 /* If the option is a subset of the parent option, it doesn't
33898 add anything and so isn't useful. */
33899 ASSERT_TRUE (!bitmap_subset_p (isa2
, isa1
));
33901 /* If the extension specifies any architectural bits then
33902 disallow it. Extensions should only specify feature bits. */
33903 ASSERT_TRUE (!bitmap_intersect_p (isa2
, target_isa
));
33909 /* Scan the static data tables generated by parsecpu.awk looking for
33910 potential issues with the data. Here we check for consistency between the
33911 fpu bits, in particular we check that ISA_ALL_FPU_INTERNAL does not contain
33912 a feature bit that is not defined by any FPU flag. */
33914 arm_test_fpu_data (void)
33916 auto_sbitmap
isa_all_fpubits_internal (isa_num_bits
);
33917 auto_sbitmap
fpubits (isa_num_bits
);
33918 auto_sbitmap
tmpset (isa_num_bits
);
33920 static const enum isa_feature fpu_bitlist_internal
[]
33921 = { ISA_ALL_FPU_INTERNAL
, isa_nobit
};
33922 arm_initialize_isa (isa_all_fpubits_internal
, fpu_bitlist_internal
);
33924 for (unsigned int i
= 0; i
< TARGET_FPU_auto
; i
++)
33926 arm_initialize_isa (fpubits
, all_fpus
[i
].isa_bits
);
33927 bitmap_and_compl (tmpset
, isa_all_fpubits_internal
, fpubits
);
33928 bitmap_clear (isa_all_fpubits_internal
);
33929 bitmap_copy (isa_all_fpubits_internal
, tmpset
);
33932 if (!bitmap_empty_p (isa_all_fpubits_internal
))
33934 fprintf (stderr
, "Error: found feature bits in the ALL_FPU_INTERAL"
33935 " group that are not defined by any FPU.\n"
33936 " Check your arm-cpus.in.\n");
33937 ASSERT_TRUE (bitmap_empty_p (isa_all_fpubits_internal
));
33942 arm_run_selftests (void)
33944 arm_test_cpu_arch_data ();
33945 arm_test_fpu_data ();
33947 } /* Namespace selftest. */
33949 #undef TARGET_RUN_TARGET_SELFTESTS
33950 #define TARGET_RUN_TARGET_SELFTESTS selftest::arm_run_selftests
33951 #endif /* CHECKING_P */
33953 /* Worker function for TARGET_MD_ASM_ADJUST, while in thumb1 mode.
33954 Unlike the arm version, we do NOT implement asm flag outputs. */
33957 thumb1_md_asm_adjust (vec
<rtx
> &outputs
, vec
<rtx
> & /*inputs*/,
33958 vec
<machine_mode
> & /*input_modes*/,
33959 vec
<const char *> &constraints
, vec
<rtx
> & /*clobbers*/,
33960 HARD_REG_SET
& /*clobbered_regs*/)
33962 for (unsigned i
= 0, n
= outputs
.length (); i
< n
; ++i
)
33963 if (strncmp (constraints
[i
], "=@cc", 4) == 0)
33965 sorry ("asm flags not supported in thumb1 mode");
33971 /* Generate code to enable conditional branches in functions over 1 MiB.
33973 operands: is the operands list of the asm insn (see arm_cond_branch or
33974 arm_cond_branch_reversed).
33975 pos_label: is an index into the operands array where operands[pos_label] is
33976 the asm label of the final jump destination.
33977 dest: is a string which is used to generate the asm label of the intermediate
33979 branch_format: is a string denoting the intermediate branch format, e.g.
33980 "beq", "bne", etc. */
33983 arm_gen_far_branch (rtx
* operands
, int pos_label
, const char * dest
,
33984 const char * branch_format
)
33986 rtx_code_label
* tmp_label
= gen_label_rtx ();
33987 char label_buf
[256];
33989 ASM_GENERATE_INTERNAL_LABEL (label_buf
, dest
, \
33990 CODE_LABEL_NUMBER (tmp_label
));
33991 const char *label_ptr
= arm_strip_name_encoding (label_buf
);
33992 rtx dest_label
= operands
[pos_label
];
33993 operands
[pos_label
] = tmp_label
;
33995 snprintf (buffer
, sizeof (buffer
), "%s%s", branch_format
, label_ptr
);
33996 output_asm_insn (buffer
, operands
);
33998 snprintf (buffer
, sizeof (buffer
), "b\t%%l0%d\n%s:", pos_label
, label_ptr
);
33999 operands
[pos_label
] = dest_label
;
34000 output_asm_insn (buffer
, operands
);
34004 /* If given mode matches, load from memory to LO_REGS.
34005 (i.e [Rn], Rn <= LO_REGS). */
34007 arm_mode_base_reg_class (machine_mode mode
)
34009 if (TARGET_HAVE_MVE
34010 && (mode
== E_V8QImode
|| mode
== E_V4QImode
|| mode
== E_V4HImode
))
34013 return MODE_BASE_REG_REG_CLASS (mode
);
34016 struct gcc_target targetm
= TARGET_INITIALIZER
;
34018 #include "gt-arm.h"