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1 ;;- Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@nyu.edu)
4
5 ;; This file is part of GNU CC.
6
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
10 ;; any later version.
11
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
22 \f
23 ;; Define an insn type attribute. This is used in function unit delay
24 ;; computations, among other purposes. For the most part, we use the names
25 ;; defined in the EV4 documentation, but add a few that we have to know about
26 ;; separately.
27
28 (define_attr "type"
29 "ld,st,ibr,fbr,jsr,iaddlog,shiftcm,icmp,imull,imulq,fpop,fdivs,fdivt,ldsym"
30 (const_string "shiftcm"))
31
32 ;; We include four function units: ABOX, which computes the address,
33 ;; BBOX, used for branches, EBOX, used for integer operations, and FBOX,
34 ;; used for FP operations.
35 ;;
36 ;; We assume that we have been successful in getting double issues and
37 ;; hence multiply all costs by two insns per cycle. The minimum time in
38 ;; a function unit is 2 cycle, which will tend to produce the double
39 ;; issues.
40
41 ;; Memory delivers its result in three cycles.
42 (define_function_unit "abox" 1 0 (eq_attr "type" "ld,ldsym,st") 6 2)
43
44 ;; Branches have no delay cost, but do tie up the unit for two cycles.
45 (define_function_unit "bbox" 1 1 (eq_attr "type" "ibr,fbr,jsr") 4 4)
46
47 ;; Arithmetic insns are normally have their results available after two
48 ;; cycles. There are a number of exceptions. They are encoded in
49 ;; ADJUST_COST. Some of the other insns have similar exceptions.
50
51 (define_function_unit "ebox" 1 0 (eq_attr "type" "iaddlog,shiftcm,icmp") 4 2)
52
53 ;; These really don't take up the integer pipeline, but they do occupy
54 ;; IBOX1; we approximate here.
55
56 (define_function_unit "ebox" 1 0 (eq_attr "type" "imull") 42 2)
57 (define_function_unit "ebox" 1 0 (eq_attr "type" "imulq") 46 2)
58
59 (define_function_unit "imult" 1 0 (eq_attr "type" "imull") 42 38)
60 (define_function_unit "imult" 1 0 (eq_attr "type" "imulq") 46 42)
61
62 (define_function_unit "fbox" 1 0 (eq_attr "type" "fpop") 12 2)
63
64 (define_function_unit "fbox" 1 0 (eq_attr "type" "fdivs") 68 0)
65 (define_function_unit "fbox" 1 0 (eq_attr "type" "fdivt") 126 0)
66
67 (define_function_unit "divider" 1 0 (eq_attr "type" "fdivs") 68 60)
68 (define_function_unit "divider" 1 0 (eq_attr "type" "fdivt") 126 118)
69 \f
70 ;; First define the arithmetic insns. Note that the 32-bit forms also
71 ;; sign-extend.
72
73 ;; Note that we can do sign extensions in both FP and integer registers.
74 ;; However, the result must be in the same type of register as the input.
75 ;; The register preferencing code can't handle this case very well, so, for
76 ;; now, don't let the FP case show up here for preferencing.
77 (define_insn "extendsidi2"
78 [(set (match_operand:DI 0 "register_operand" "=r,r,f")
79 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,f")))]
80 ""
81 "@
82 addl %1,$31,%0
83 ldl %0,%1
84 cvtlq %1,%0"
85 [(set_attr "type" "iaddlog,ld,fpop")])
86
87 (define_insn "addsi3"
88 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
89 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,%rJ,%rJ")
90 (match_operand:SI 2 "add_operand" "rI,K,L")))]
91 ""
92 "@
93 addl %r1,%2,%0
94 lda %0,%2(%r1)
95 ldah %0,%h2(%r1)"
96 [(set_attr "type" "iaddlog")])
97
98 (define_split
99 [(set (match_operand:SI 0 "register_operand" "")
100 (plus:SI (match_operand:SI 1 "register_operand" "")
101 (match_operand:SI 2 "const_int_operand" "")))]
102 "! add_operand (operands[2], SImode)"
103 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
104 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
105 "
106 {
107 HOST_WIDE_INT val = INTVAL (operands[2]);
108 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
109 HOST_WIDE_INT rest = val - low;
110
111 operands[3] = GEN_INT (rest);
112 operands[4] = GEN_INT (low);
113 }")
114
115 (define_insn ""
116 [(set (match_operand:DI 0 "register_operand" "=r,r")
117 (sign_extend:DI
118 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
119 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
120 ""
121 "@
122 addl %r1,%2,%0
123 subl %r1,%n2,%0"
124 [(set_attr "type" "iaddlog")])
125
126 (define_insn "adddi3"
127 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
128 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,%rJ,%rJ")
129 (match_operand:DI 2 "add_operand" "rI,K,L")))]
130 ""
131 "@
132 addq %r1,%2,%0
133 lda %0,%2(%r1)
134 ldah %0,%h2(%r1)"
135 [(set_attr "type" "iaddlog")])
136
137 (define_split
138 [(set (match_operand:DI 0 "register_operand" "")
139 (plus:DI (match_operand:DI 1 "register_operand" "")
140 (match_operand:DI 2 "const_int_operand" "")))]
141 "! add_operand (operands[2], DImode)"
142 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
143 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
144 "
145 {
146 HOST_WIDE_INT val = INTVAL (operands[2]);
147 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
148 HOST_WIDE_INT rest = val - low;
149
150 operands[3] = GEN_INT (rest);
151 operands[4] = GEN_INT (low);
152 }")
153
154 (define_insn ""
155 [(set (match_operand:SI 0 "register_operand" "=r")
156 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
157 (match_operand:SI 2 "const48_operand" "I"))
158 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
159 ""
160 "s%2addl %r1,%3,%0"
161 [(set_attr "type" "iaddlog")])
162
163 (define_insn ""
164 [(set (match_operand:DI 0 "register_operand" "=r")
165 (sign_extend:DI
166 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
167 (match_operand:SI 2 "const48_operand" "I"))
168 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
169 ""
170 "s%2addl %r1,%3,%0"
171 [(set_attr "type" "iaddlog")])
172
173 (define_insn ""
174 [(set (match_operand:DI 0 "register_operand" "=r")
175 (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
176 (match_operand:DI 2 "const48_operand" "I"))
177 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
178 ""
179 "s%2addq %r1,%3,%0"
180 [(set_attr "type" "iaddlog")])
181
182 ;; These variants of the above insns can occur if the third operand
183 ;; is the frame pointer. This is a kludge, but there doesn't
184 ;; seem to be a way around it. Only recognize them while reloading.
185
186 (define_insn ""
187 [(set (match_operand:SI 0 "register_operand" "=&r")
188 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
189 (match_operand:SI 2 "const48_operand" "I"))
190 (match_operand:SI 3 "register_operand" "r"))
191 (match_operand:SI 4 "const_int_operand" "rI")))]
192 "reload_in_progress"
193 "s%2addl %r1,%3,%0\;addl %0,%4,%0"
194 [(set_attr "type" "iaddlog")])
195
196 (define_insn ""
197 [(set (match_operand:DI 0 "register_operand" "=&r")
198 (sign_extend:DI
199 (plus:SI (plus:SI
200 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
201 (match_operand:SI 2 "const48_operand" "I"))
202 (match_operand:SI 3 "register_operand" "r"))
203 (match_operand:SI 4 "const_int_operand" "rI"))))]
204 "reload_in_progress"
205 "s%2addl %r1,%3,%0\;addl %0,%4,%0"
206 [(set_attr "type" "iaddlog")])
207
208 (define_insn ""
209 [(set (match_operand:DI 0 "register_operand" "=&r")
210 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
211 (match_operand:DI 2 "const48_operand" "I"))
212 (match_operand:DI 3 "register_operand" "r"))
213 (match_operand:DI 4 "const_int_operand" "rI")))]
214 "reload_in_progress"
215 "s%2addq %r1,%3,%0\;addq %0,%4,%0"
216 [(set_attr "type" "iaddlog")])
217
218 (define_insn "negsi2"
219 [(set (match_operand:SI 0 "register_operand" "=r")
220 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
221 ""
222 "subl $31,%1,%0"
223 [(set_attr "type" "iaddlog")])
224
225 (define_insn ""
226 [(set (match_operand:DI 0 "register_operand" "=r")
227 (sign_extend:DI (neg:SI
228 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
229 ""
230 "subl $31,%1,%0"
231 [(set_attr "type" "iaddlog")])
232
233 (define_insn "negdi2"
234 [(set (match_operand:DI 0 "register_operand" "=r")
235 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
236 ""
237 "subq $31,%1,%0"
238 [(set_attr "type" "iaddlog")])
239
240 (define_insn "subsi3"
241 [(set (match_operand:SI 0 "register_operand" "=r")
242 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
243 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
244 ""
245 "subl %r1,%2,%0"
246 [(set_attr "type" "iaddlog")])
247
248 (define_insn ""
249 [(set (match_operand:DI 0 "register_operand" "=r")
250 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
251 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
252 ""
253 "subl %r1,%2,%0"
254 [(set_attr "type" "iaddlog")])
255
256 (define_insn "subdi3"
257 [(set (match_operand:DI 0 "register_operand" "=r")
258 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
259 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
260 ""
261 "subq %r1,%2,%0"
262 [(set_attr "type" "iaddlog")])
263
264 (define_insn ""
265 [(set (match_operand:SI 0 "register_operand" "=r")
266 (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
267 (match_operand:SI 2 "const48_operand" "I"))
268 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
269 ""
270 "s%2subl %r1,%3,%0"
271 [(set_attr "type" "iaddlog")])
272
273 (define_insn ""
274 [(set (match_operand:DI 0 "register_operand" "=r")
275 (sign_extend:DI
276 (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
277 (match_operand:SI 2 "const48_operand" "I"))
278 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
279 ""
280 "s%2subl %r1,%3,%0"
281 [(set_attr "type" "iaddlog")])
282
283 (define_insn ""
284 [(set (match_operand:DI 0 "register_operand" "=r")
285 (minus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
286 (match_operand:DI 2 "const48_operand" "I"))
287 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
288 ""
289 "s%2subq %r1,%3,%0"
290 [(set_attr "type" "iaddlog")])
291
292 (define_insn "mulsi3"
293 [(set (match_operand:SI 0 "register_operand" "=r")
294 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
295 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
296 ""
297 "mull %r1,%2,%0"
298 [(set_attr "type" "imull")])
299
300 (define_insn ""
301 [(set (match_operand:DI 0 "register_operand" "=r")
302 (sign_extend:DI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
303 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
304 ""
305 "mull %r1,%2,%0"
306 [(set_attr "type" "imull")])
307
308 (define_insn "muldi3"
309 [(set (match_operand:DI 0 "register_operand" "=r")
310 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
311 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
312 ""
313 "mulq %r1,%2,%0"
314 [(set_attr "type" "imulq")])
315 \f
316 ;; The divide and remainder operations always take their inputs from
317 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
318
319 (define_expand "divsi3"
320 [(parallel [(set (reg:SI 27)
321 (div:SI (match_operand:SI 1 "general_operand" "")
322 (match_operand:SI 2 "general_operand" "")))
323 (clobber (reg:DI 23))
324 (clobber (reg:DI 28))])
325 (set (match_operand:SI 0 "general_operand" "")
326 (reg:SI 27))]
327 ""
328 "
329 { rtx in0 = gen_rtx (REG, SImode, 24);
330 rtx in1 = gen_rtx (REG, SImode, 25);
331
332 emit_move_insn (in0, operands[1]);
333 emit_move_insn (in1, operands[2]);
334 operands[1] = in0, operands[2] = in1;
335 }")
336
337 (define_expand "udivsi3"
338 [(parallel [(set (reg:SI 27)
339 (udiv:SI (match_operand:SI 1 "general_operand" "")
340 (match_operand:SI 2 "general_operand" "")))
341 (clobber (reg:DI 23))
342 (clobber (reg:DI 28))])
343 (set (match_operand:SI 0 "general_operand" "")
344 (reg:SI 27))]
345 ""
346 "
347 { rtx in0 = gen_rtx (REG, SImode, 24);
348 rtx in1 = gen_rtx (REG, SImode, 25);
349
350 emit_move_insn (in0, operands[1]);
351 emit_move_insn (in1, operands[2]);
352 operands[1] = in0, operands[2] = in1;
353 }")
354
355 (define_expand "modsi3"
356 [(parallel [(set (reg:SI 27)
357 (mod:SI (match_operand:SI 1 "general_operand" "")
358 (match_operand:SI 2 "general_operand" "")))
359 (clobber (reg:DI 23))
360 (clobber (reg:DI 28))])
361 (set (match_operand:SI 0 "general_operand" "")
362 (reg:SI 27))]
363 ""
364 "
365 { rtx in0 = gen_rtx (REG, SImode, 24);
366 rtx in1 = gen_rtx (REG, SImode, 25);
367
368 emit_move_insn (in0, operands[1]);
369 emit_move_insn (in1, operands[2]);
370 operands[1] = in0, operands[2] = in1;
371 }")
372
373 (define_expand "umodsi3"
374 [(parallel [(set (reg:SI 27)
375 (umod:SI (match_operand:SI 1 "general_operand" "")
376 (match_operand:SI 2 "general_operand" "")))
377 (clobber (reg:DI 23))
378 (clobber (reg:DI 28))])
379 (set (match_operand:SI 0 "general_operand" "")
380 (reg:SI 27))]
381 ""
382 "
383 { rtx in0 = gen_rtx (REG, SImode, 24);
384 rtx in1 = gen_rtx (REG, SImode, 25);
385
386 emit_move_insn (in0, operands[1]);
387 emit_move_insn (in1, operands[2]);
388 operands[1] = in0, operands[2] = in1;
389 }")
390
391 (define_expand "divdi3"
392 [(parallel [(set (reg:DI 27)
393 (div:DI (match_operand:DI 1 "general_operand" "")
394 (match_operand:DI 2 "general_operand" "")))
395 (clobber (reg:DI 23))
396 (clobber (reg:DI 28))])
397 (set (match_operand:DI 0 "general_operand" "")
398 (reg:DI 27))]
399 ""
400 "
401 { rtx in0 = gen_rtx (REG, DImode, 24);
402 rtx in1 = gen_rtx (REG, DImode, 25);
403
404 emit_move_insn (in0, operands[1]);
405 emit_move_insn (in1, operands[2]);
406 operands[1] = in0, operands[2] = in1;
407 }")
408
409 (define_expand "udivdi3"
410 [(parallel [(set (reg:DI 27)
411 (udiv:DI (match_operand:DI 1 "general_operand" "")
412 (match_operand:DI 2 "general_operand" "")))
413 (clobber (reg:DI 23))
414 (clobber (reg:DI 28))])
415 (set (match_operand:DI 0 "general_operand" "")
416 (reg:DI 27))]
417 ""
418 "
419 { rtx in0 = gen_rtx (REG, DImode, 24);
420 rtx in1 = gen_rtx (REG, DImode, 25);
421
422 emit_move_insn (in0, operands[1]);
423 emit_move_insn (in1, operands[2]);
424 operands[1] = in0, operands[2] = in1;
425 }")
426
427 (define_expand "moddi3"
428 [(parallel [(set (reg:DI 27)
429 (mod:DI (match_operand:DI 1 "general_operand" "")
430 (match_operand:DI 2 "general_operand" "")))
431 (clobber (reg:DI 23))
432 (clobber (reg:DI 28))])
433 (set (match_operand:DI 0 "general_operand" "")
434 (reg:DI 27))]
435 ""
436 "
437 { rtx in0 = gen_rtx (REG, DImode, 24);
438 rtx in1 = gen_rtx (REG, DImode, 25);
439
440 emit_move_insn (in0, operands[1]);
441 emit_move_insn (in1, operands[2]);
442 operands[1] = in0, operands[2] = in1;
443 }")
444
445 (define_expand "umoddi3"
446 [(parallel [(set (reg:DI 27)
447 (umod:DI (match_operand:DI 1 "general_operand" "")
448 (match_operand:DI 2 "general_operand" "")))
449 (clobber (reg:DI 23))
450 (clobber (reg:DI 28))])
451 (set (match_operand:DI 0 "general_operand" "")
452 (reg:DI 27))]
453 ""
454 "
455 { rtx in0 = gen_rtx (REG, DImode, 24);
456 rtx in1 = gen_rtx (REG, DImode, 25);
457
458 emit_move_insn (in0, operands[1]);
459 emit_move_insn (in1, operands[2]);
460 operands[1] = in0, operands[2] = in1;
461 }")
462
463 (define_insn ""
464 [(set (reg:SI 27)
465 (match_operator:SI 1 "divmod_operator"
466 [(reg:SI 24) (reg:SI 25)]))
467 (clobber (reg:DI 23))
468 (clobber (reg:DI 28))]
469 ""
470 "%E1 $24,$25,$27")
471
472 (define_insn ""
473 [(set (reg:DI 27)
474 (match_operator:DI 1 "divmod_operator"
475 [(reg:DI 24) (reg:DI 25)]))
476 (clobber (reg:DI 23))
477 (clobber (reg:DI 28))]
478 ""
479 "%E1 $24,$25,$27")
480 \f
481 ;; Next are the basic logical operations. These only exist in DImode.
482
483 (define_insn "anddi3"
484 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
485 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
486 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
487 ""
488 "@
489 and %r1,%2,%0
490 bic %r1,%N2,%0
491 zapnot %r1,%m2,%0"
492 [(set_attr "type" "iaddlog,iaddlog,shiftcm")])
493
494 ;; There are times when we can split and AND into two AND insns. This occurs
495 ;; when we can first clear any bytes and then clear anything else. For
496 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
497 ;; Only to this when running on 64-bit host since the computations are
498 ;; too messy otherwise.
499
500 (define_split
501 [(set (match_operand:DI 0 "register_operand" "")
502 (and:DI (match_operand:DI 1 "register_operand" "")
503 (match_operand:DI 2 "const_int_operand" "")))]
504 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
505 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
506 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
507 "
508 {
509 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
510 unsigned HOST_WIDE_INT mask2 = mask1;
511 int i;
512
513 /* For each byte that isn't all zeros, make it all ones. */
514 for (i = 0; i < 64; i += 8)
515 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
516 mask1 |= (HOST_WIDE_INT) 0xff << i;
517
518 /* Now turn on any bits we've just turned off. */
519 mask2 |= ~ mask1;
520
521 operands[3] = GEN_INT (mask1);
522 operands[4] = GEN_INT (mask2);
523 }")
524
525 (define_insn "zero_extendqihi2"
526 [(set (match_operand:HI 0 "register_operand" "=r")
527 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
528 ""
529 "zapnot %1,1,%0"
530 [(set_attr "type" "iaddlog")])
531
532 (define_insn "zero_extendqisi2"
533 [(set (match_operand:SI 0 "register_operand" "=r")
534 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
535 ""
536 "zapnot %1,1,%0"
537 [(set_attr "type" "iaddlog")])
538
539 (define_insn "zero_extendqidi2"
540 [(set (match_operand:DI 0 "register_operand" "=r")
541 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
542 ""
543 "zapnot %1,1,%0"
544 [(set_attr "type" "iaddlog")])
545
546 (define_insn "zero_extendhisi2"
547 [(set (match_operand:SI 0 "register_operand" "=r")
548 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
549 ""
550 "zapnot %1,3,%0"
551 [(set_attr "type" "iaddlog")])
552
553 (define_insn "zero_extendhidi2"
554 [(set (match_operand:DI 0 "register_operand" "=r")
555 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
556 ""
557 "zapnot %1,3,%0"
558 [(set_attr "type" "iaddlog")])
559
560 (define_insn "zero_extendsidi2"
561 [(set (match_operand:DI 0 "register_operand" "=r")
562 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
563 ""
564 "zapnot %1,15,%0"
565 [(set_attr "type" "iaddlog")])
566
567 (define_insn ""
568 [(set (match_operand:DI 0 "register_operand" "=r")
569 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
570 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
571 ""
572 "bic %r2,%1,%0"
573 [(set_attr "type" "iaddlog")])
574
575 (define_insn "iordi3"
576 [(set (match_operand:DI 0 "register_operand" "=r")
577 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
578 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
579 ""
580 "bis %r1,%2,%0"
581 [(set_attr "type" "iaddlog")])
582
583 (define_insn "one_cmpldi2"
584 [(set (match_operand:DI 0 "register_operand" "=r")
585 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
586 ""
587 "ornot $31,%1,%0"
588 [(set_attr "type" "iaddlog")])
589
590 (define_insn ""
591 [(set (match_operand:DI 0 "register_operand" "=r")
592 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
593 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
594 ""
595 "ornot %r2,%1,%0"
596 [(set_attr "type" "iaddlog")])
597
598 (define_insn "xordi3"
599 [(set (match_operand:DI 0 "register_operand" "=r")
600 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
601 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
602 ""
603 "xor %r1,%2,%0"
604 [(set_attr "type" "iaddlog")])
605
606 (define_insn ""
607 [(set (match_operand:DI 0 "register_operand" "=r")
608 (not:DI (xor:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
609 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))))]
610 ""
611 "eqv %r1,%2,%0"
612 [(set_attr "type" "iaddlog")])
613 \f
614 ;; Next come the shifts and the various extract and insert operations.
615
616 (define_insn "ashldi3"
617 [(set (match_operand:DI 0 "register_operand" "=r,r")
618 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
619 (match_operand:DI 2 "reg_or_8bit_operand" "P,rI")))]
620 ""
621 "*
622 {
623 switch (which_alternative)
624 {
625 case 0:
626 if (operands[2] == const1_rtx)
627 return \"addq %r1,%r1,%0\";
628 else
629 return \"s%P2addq %r1,0,%0\";
630 case 1:
631 return \"sll %r1,%2,%0\";
632 }
633 }"
634 [(set_attr "type" "iaddlog,shiftcm")])
635
636 ;; This is the same as (sign_extend (shift X [123])).
637 (define_insn ""
638 [(set (match_operand:DI 0 "register_operand" "=r")
639 (ashiftrt:DI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
640 (match_operand:DI 2 "const_int_operand" "i"))
641 (const_int 32)))]
642 "INTVAL (operands[2]) >= 33 && INTVAL (operands[2]) <= 35"
643 "*
644 {
645 switch (INTVAL (operands[2]))
646 {
647 case 33:
648 return \"addl %r1,%r1,%0\";
649 case 34:
650 return \"s4addl %r1,0,%0\";
651 case 35:
652 return \"s8addl %r1,0,%0\";
653 default:
654 abort ();
655 }
656 }"
657 [(set_attr "type" "iaddlog")])
658
659 (define_insn "lshrdi3"
660 [(set (match_operand:DI 0 "register_operand" "=r")
661 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
662 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
663 ""
664 "srl %r1,%2,%0")
665
666 (define_insn "ashrdi3"
667 [(set (match_operand:DI 0 "register_operand" "=r")
668 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
669 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
670 ""
671 "sra %r1,%2,%0")
672
673 (define_expand "extendqihi2"
674 [(set (match_dup 2)
675 (ashift:DI (match_operand:QI 1 "register_operand" "")
676 (const_int 56)))
677 (set (match_operand:HI 0 "register_operand" "")
678 (ashiftrt:DI (match_dup 2)
679 (const_int 56)))]
680 ""
681 "
682 { operands[0] = gen_lowpart (DImode, operands[0]);
683 operands[1] = gen_lowpart (DImode, operands[1]);
684 operands[2] = gen_reg_rtx (DImode);
685 }")
686
687 (define_expand "extendqisi2"
688 [(set (match_dup 2)
689 (ashift:DI (match_operand:QI 1 "register_operand" "")
690 (const_int 56)))
691 (set (match_operand:SI 0 "register_operand" "")
692 (ashiftrt:DI (match_dup 2)
693 (const_int 56)))]
694 ""
695 "
696 { operands[0] = gen_lowpart (DImode, operands[0]);
697 operands[1] = gen_lowpart (DImode, operands[1]);
698 operands[2] = gen_reg_rtx (DImode);
699 }")
700
701 (define_expand "extendqidi2"
702 [(set (match_dup 2)
703 (ashift:DI (match_operand:QI 1 "register_operand" "")
704 (const_int 56)))
705 (set (match_operand:DI 0 "register_operand" "")
706 (ashiftrt:DI (match_dup 2)
707 (const_int 56)))]
708 ""
709 "
710 { operands[1] = gen_lowpart (DImode, operands[1]);
711 operands[2] = gen_reg_rtx (DImode);
712 }")
713
714 (define_expand "extendhisi2"
715 [(set (match_dup 2)
716 (ashift:DI (match_operand:HI 1 "register_operand" "")
717 (const_int 48)))
718 (set (match_operand:SI 0 "register_operand" "")
719 (ashiftrt:DI (match_dup 2)
720 (const_int 48)))]
721 ""
722 "
723 { operands[0] = gen_lowpart (DImode, operands[0]);
724 operands[1] = gen_lowpart (DImode, operands[1]);
725 operands[2] = gen_reg_rtx (DImode);
726 }")
727
728 (define_expand "extendhidi2"
729 [(set (match_dup 2)
730 (ashift:DI (match_operand:HI 1 "register_operand" "")
731 (const_int 48)))
732 (set (match_operand:DI 0 "register_operand" "")
733 (ashiftrt:DI (match_dup 2)
734 (const_int 48)))]
735 ""
736 "
737 { operands[1] = gen_lowpart (DImode, operands[1]);
738 operands[2] = gen_reg_rtx (DImode);
739 }")
740
741 (define_insn ""
742 [(set (match_operand:DI 0 "register_operand" "=r")
743 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
744 (match_operand:DI 2 "mode_width_operand" "n")
745 (match_operand:DI 3 "mul8_operand" "I")))]
746 ""
747 "ext%M2l %r1,%s3,%0")
748
749 (define_insn ""
750 [(set (match_operand:DI 0 "register_operand" "=r")
751 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
752 (match_operand:DI 2 "mode_width_operand" "n")
753 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
754 (const_int 3))))]
755 ""
756 "ext%M2l %r1,%3,%0")
757
758 (define_insn ""
759 [(set (match_operand:DI 0 "register_operand" "=r")
760 (ashift:DI
761 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
762 (const_int 8)
763 (ashift:DI
764 (plus:DI
765 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
766 (const_int -1))
767 (const_int 3)))
768 (const_int 56)))]
769 ""
770 "extqh %r1,%2,%0")
771
772 (define_insn ""
773 [(set (match_operand:DI 0 "register_operand" "=r")
774 (ashift:DI
775 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
776 (const_int 16)
777 (ashift:DI
778 (plus:DI
779 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
780 (const_int -2))
781 (const_int 3)))
782 (const_int 48)))]
783 ""
784 "extwh %r1,%2,%0")
785
786 (define_insn ""
787 [(set (match_operand:DI 0 "register_operand" "=r")
788 (ashift:DI
789 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
790 (const_int 32)
791 (ashift:DI
792 (plus:DI
793 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
794 (const_int -4))
795 (const_int 3)))
796 (const_int 32)))]
797 ""
798 "extlh %r1,%2,%0")
799
800 ;; This converts an extXl into an extXh with an appropriate adjustment
801 ;; to the address calculation.
802
803 (define_split
804 [(set (match_operand:DI 0 "register_operand" "")
805 (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
806 (match_operand:DI 2 "mode_width_operand" "")
807 (ashift:DI (match_operand:DI 3 "" "")
808 (const_int 3)))
809 (match_operand:DI 4 "const_int_operand" "")))
810 (clobber (match_operand:DI 5 "register_operand" ""))]
811 "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
812 [(set (match_dup 5) (match_dup 6))
813 (set (match_dup 0)
814 (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
815 (ashift:DI (plus:DI (match_dup 5)
816 (match_dup 7))
817 (const_int 3)))
818 (match_dup 4)))]
819 "
820 {
821 operands[6] = plus_constant (operands[3],
822 INTVAL (operands[2]) / BITS_PER_UNIT);
823 operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
824 }")
825
826 (define_insn ""
827 [(set (match_operand:DI 0 "register_operand" "=r")
828 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
829 (match_operand:DI 2 "mul8_operand" "I")))]
830 ""
831 "insbl %1,%s2,%0")
832
833 (define_insn ""
834 [(set (match_operand:DI 0 "register_operand" "=r")
835 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
836 (match_operand:DI 2 "mul8_operand" "I")))]
837 ""
838 "inswl %1,%s2,%0")
839
840 (define_insn ""
841 [(set (match_operand:DI 0 "register_operand" "=r")
842 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
843 (match_operand:DI 2 "mul8_operand" "I")))]
844 ""
845 "insll %1,%s2,%0")
846
847 (define_insn ""
848 [(set (match_operand:DI 0 "register_operand" "=r")
849 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
850 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
851 (const_int 3))))]
852 ""
853 "insbl %1,%2,%0")
854
855 (define_insn ""
856 [(set (match_operand:DI 0 "register_operand" "=r")
857 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
858 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
859 (const_int 3))))]
860 ""
861 "inswl %1,%2,%0")
862
863 (define_insn ""
864 [(set (match_operand:DI 0 "register_operand" "=r")
865 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
866 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
867 (const_int 3))))]
868 ""
869 "insll %1,%2,%0")
870
871 ;; We do not include the insXh insns because they are complex to express
872 ;; and it does not appear that we would ever want to generate them.
873
874 (define_insn ""
875 [(set (match_operand:DI 0 "register_operand" "=r")
876 (and:DI (ashift:DI
877 (match_operand:DI 2 "mode_mask_operand" "n")
878 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
879 (const_int 3)))
880 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
881 ""
882 "msk%U2l %r1,%3,%0")
883
884 ;; We do not include the mskXh insns because it does not appear we would ever
885 ;; generate one.
886 \f
887 ;; Floating-point operations. All the double-precision insns can extend
888 ;; from single, so indicate that. The exception are the ones that simply
889 ;; play with the sign bits; it's not clear what to do there.
890
891 (define_insn "abssf2"
892 [(set (match_operand:SF 0 "register_operand" "=f")
893 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
894 "TARGET_FP"
895 "cpys $f31,%R1,%0"
896 [(set_attr "type" "fpop")])
897
898 (define_insn "absdf2"
899 [(set (match_operand:DF 0 "register_operand" "=f")
900 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
901 "TARGET_FP"
902 "cpys $f31,%R1,%0"
903 [(set_attr "type" "fpop")])
904
905 (define_insn "negsf2"
906 [(set (match_operand:SF 0 "register_operand" "=f")
907 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
908 "TARGET_FP"
909 "cpysn %1,%R1,%0"
910 [(set_attr "type" "fpop")])
911
912 (define_insn "negdf2"
913 [(set (match_operand:DF 0 "register_operand" "=f")
914 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
915 "TARGET_FP"
916 "cpysn %1,%R1,%0"
917 [(set_attr "type" "fpop")])
918
919 (define_insn "addsf3"
920 [(set (match_operand:SF 0 "register_operand" "=f")
921 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
922 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
923 "TARGET_FP"
924 "adds %R1,%R2,%0"
925 [(set_attr "type" "fpop")])
926
927 (define_insn "adddf3"
928 [(set (match_operand:DF 0 "register_operand" "=f")
929 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
930 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
931 "TARGET_FP"
932 "addt %R1,%R2,%0"
933 [(set_attr "type" "fpop")])
934
935 (define_insn ""
936 [(set (match_operand:DF 0 "register_operand" "=f")
937 (plus:DF (float_extend:DF
938 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
939 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
940 "TARGET_FP"
941 "addt %R1,%R2,%0"
942 [(set_attr "type" "fpop")])
943
944 (define_insn ""
945 [(set (match_operand:DF 0 "register_operand" "=f")
946 (plus:DF (float_extend:DF
947 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
948 (float_extend:DF
949 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
950 "TARGET_FP"
951 "addt %R1,%R2,%0"
952 [(set_attr "type" "fpop")])
953
954 (define_insn "fix_truncdfdi2"
955 [(set (match_operand:DI 0 "register_operand" "=f")
956 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
957 "TARGET_FP"
958 "cvttq %R1,%0"
959 [(set_attr "type" "fpop")])
960
961 (define_insn "fix_truncsfdi2"
962 [(set (match_operand:DI 0 "register_operand" "=f")
963 (fix:DI (float_extend:DF
964 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
965 "TARGET_FP"
966 "cvttq %R1,%0"
967 [(set_attr "type" "fpop")])
968
969 (define_insn "floatdisf2"
970 [(set (match_operand:SF 0 "register_operand" "=f")
971 (float:SF (match_operand:DI 1 "register_operand" "f")))]
972 "TARGET_FP"
973 "cvtqs %1,%0"
974 [(set_attr "type" "fpop")])
975
976 (define_insn "floatdidf2"
977 [(set (match_operand:DF 0 "register_operand" "=f")
978 (float:DF (match_operand:DI 1 "register_operand" "f")))]
979 "TARGET_FP"
980 "cvtqt %1,%0"
981 [(set_attr "type" "fpop")])
982
983 (define_insn "extendsfdf2"
984 [(set (match_operand:DF 0 "register_operand" "=f,f")
985 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
986 "TARGET_FP"
987 "@
988 addt $f31,%1,%0
989 lds %0,%1"
990 [(set_attr "type" "fpop,ld")])
991
992 (define_insn "truncdfsf2"
993 [(set (match_operand:SF 0 "register_operand" "=f")
994 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
995 "TARGET_FP"
996 "cvtts %R1,%0"
997 [(set_attr "type" "fpop")])
998
999 (define_insn "divsf3"
1000 [(set (match_operand:SF 0 "register_operand" "=f")
1001 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
1002 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1003 "TARGET_FP"
1004 "divs %R1,%R2,%0"
1005 [(set_attr "type" "fdivs")])
1006
1007 (define_insn "divdf3"
1008 [(set (match_operand:DF 0 "register_operand" "=f")
1009 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1010 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1011 "TARGET_FP"
1012 "divt %R1,%R2,%0"
1013 [(set_attr "type" "fdivt")])
1014
1015 (define_insn ""
1016 [(set (match_operand:DF 0 "register_operand" "=f")
1017 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1018 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1019 "TARGET_FP"
1020 "divt %R1,%R2,%0"
1021 [(set_attr "type" "fdivt")])
1022
1023 (define_insn ""
1024 [(set (match_operand:DF 0 "register_operand" "=f")
1025 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1026 (float_extend:DF
1027 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1028 "TARGET_FP"
1029 "divt %R1,%R2,%0"
1030 [(set_attr "type" "fdivt")])
1031
1032 (define_insn ""
1033 [(set (match_operand:DF 0 "register_operand" "=f")
1034 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1035 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1036 "TARGET_FP"
1037 "divt %R1,%R2,%0"
1038 [(set_attr "type" "fdivt")])
1039
1040 (define_insn "mulsf3"
1041 [(set (match_operand:SF 0 "register_operand" "=f")
1042 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
1043 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1044 "TARGET_FP"
1045 "muls %R1,%R2,%0"
1046 [(set_attr "type" "fpop")])
1047
1048 (define_insn "muldf3"
1049 [(set (match_operand:DF 0 "register_operand" "=f")
1050 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1051 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1052 "TARGET_FP"
1053 "mult %R1,%R2,%0"
1054 [(set_attr "type" "fpop")])
1055
1056 (define_insn ""
1057 [(set (match_operand:DF 0 "register_operand" "=f")
1058 (mult:DF (float_extend:DF
1059 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1060 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1061 "TARGET_FP"
1062 "mult %R1,%R2,%0"
1063 [(set_attr "type" "fpop")])
1064
1065 (define_insn ""
1066 [(set (match_operand:DF 0 "register_operand" "=f")
1067 (mult:DF (float_extend:DF
1068 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1069 (float_extend:DF
1070 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1071 "TARGET_FP"
1072 "mult %R1,%R2,%0"
1073 [(set_attr "type" "fpop")])
1074
1075 (define_insn "subsf3"
1076 [(set (match_operand:SF 0 "register_operand" "=f")
1077 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1078 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1079 "TARGET_FP"
1080 "subs %R1,%R2,%0"
1081 [(set_attr "type" "fpop")])
1082
1083 (define_insn "subdf3"
1084 [(set (match_operand:DF 0 "register_operand" "=f")
1085 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1086 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1087 "TARGET_FP"
1088 "subt %R1,%R2,%0"
1089 [(set_attr "type" "fpop")])
1090
1091 (define_insn ""
1092 [(set (match_operand:DF 0 "register_operand" "=f")
1093 (minus:DF (float_extend:DF
1094 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1095 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1096 "TARGET_FP"
1097 "subt %R1,%R2,%0"
1098 [(set_attr "type" "fpop")])
1099
1100 (define_insn ""
1101 [(set (match_operand:DF 0 "register_operand" "=f")
1102 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1103 (float_extend:DF
1104 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1105 "TARGET_FP"
1106 "subt %R1,%R2,%0"
1107 [(set_attr "type" "fpop")])
1108
1109 (define_insn ""
1110 [(set (match_operand:DF 0 "register_operand" "=f")
1111 (minus:DF (float_extend:DF
1112 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1113 (float_extend:DF
1114 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1115 "TARGET_FP"
1116 "subt %R1,%R2,%0"
1117 [(set_attr "type" "fpop")])
1118 \f
1119 ;; Next are all the integer comparisons, and conditional moves and branches
1120 ;; and some of the related define_expand's and define_split's.
1121
1122 (define_insn ""
1123 [(set (match_operand:DI 0 "register_operand" "=r")
1124 (match_operator:DI 1 "alpha_comparison_operator"
1125 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
1126 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
1127 ""
1128 "cmp%C1 %r2,%3,%0"
1129 [(set_attr "type" "icmp")])
1130
1131 (define_insn ""
1132 [(set (match_operand:DI 0 "register_operand" "=r,r")
1133 (if_then_else:DI
1134 (match_operator 2 "signed_comparison_operator"
1135 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ")
1136 (const_int 0)])
1137 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
1138 (match_operand:DI 4 "reg_or_8bit_operand" "0,rI")))]
1139 ""
1140 "@
1141 cmov%C2 %r3,%1,%0
1142 cmov%D2 %r3,%4,%0")
1143
1144 (define_insn ""
1145 [(set (match_operand:DI 0 "register_operand" "=r,r")
1146 (if_then_else:DI
1147 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
1148 (const_int 1)
1149 (const_int 0))
1150 (const_int 0))
1151 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
1152 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
1153 ""
1154 "@
1155 cmovlbc %r2,%1,%0
1156 cmovlbs %r2,%3,%0")
1157
1158 (define_insn ""
1159 [(set (match_operand:DI 0 "register_operand" "=r,r")
1160 (if_then_else:DI
1161 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
1162 (const_int 1)
1163 (const_int 0))
1164 (const_int 0))
1165 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
1166 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
1167 ""
1168 "@
1169 cmovlbs %r2,%1,%0
1170 cmovlbc %r2,%3,%0")
1171
1172 ;; This form is added since combine thinks that an IF_THEN_ELSE with both
1173 ;; arms constant is a single insn, so it won't try to form it if combine
1174 ;; knows they are really two insns. This occurs in divides by powers
1175 ;; of two.
1176
1177 (define_insn ""
1178 [(set (match_operand:DI 0 "register_operand" "=r")
1179 (if_then_else:DI
1180 (match_operator 2 "signed_comparison_operator"
1181 [(match_operand:DI 3 "reg_or_0_operand" "rJ")
1182 (const_int 0)])
1183 (plus:DI (match_dup 0)
1184 (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1185 (match_dup 0)))
1186 (clobber (match_scratch:DI 4 "=&r"))]
1187 ""
1188 "addq %0,%1,%4\;cmov%C2 %r3,%4,%0")
1189
1190 (define_split
1191 [(set (match_operand:DI 0 "register_operand" "")
1192 (if_then_else:DI
1193 (match_operator 2 "signed_comparison_operator"
1194 [(match_operand:DI 3 "reg_or_0_operand" "")
1195 (const_int 0)])
1196 (plus:DI (match_dup 0)
1197 (match_operand:DI 1 "reg_or_8bit_operand" ""))
1198 (match_dup 0)))
1199 (clobber (match_operand:DI 4 "register_operand" ""))]
1200 ""
1201 [(set (match_dup 4) (plus:DI (match_dup 0) (match_dup 1)))
1202 (set (match_dup 0) (if_then_else:DI (match_op_dup 2
1203 [(match_dup 3)
1204 (const_int 0)])
1205 (match_dup 4) (match_dup 0)))]
1206 "")
1207
1208 (define_split
1209 [(parallel
1210 [(set (match_operand:DI 0 "register_operand" "")
1211 (if_then_else:DI
1212 (match_operator 1 "comparison_operator"
1213 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
1214 (const_int 1)
1215 (match_operand:DI 3 "const_int_operand" ""))
1216 (const_int 0)])
1217 (match_operand:DI 4 "reg_or_8bit_operand" "")
1218 (match_operand:DI 5 "reg_or_8bit_operand" "")))
1219 (clobber (match_operand:DI 6 "register_operand" ""))])]
1220 "INTVAL (operands[3]) != 0"
1221 [(set (match_dup 6)
1222 (lshiftrt:DI (match_dup 2) (match_dup 3)))
1223 (set (match_dup 0)
1224 (if_then_else:DI (match_op_dup 1
1225 [(zero_extract:DI (match_dup 6)
1226 (const_int 1)
1227 (const_int 0))
1228 (const_int 0)])
1229 (match_dup 4)
1230 (match_dup 5)))]
1231 "")
1232
1233 ;; For ABS, we have two choices, depending on whether the input and output
1234 ;; registers are the same or not.
1235 (define_expand "absdi2"
1236 [(set (match_operand:DI 0 "register_operand" "")
1237 (abs:DI (match_operand:DI 1 "register_operand" "")))]
1238 ""
1239 "
1240 { if (rtx_equal_p (operands[0], operands[1]))
1241 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
1242 else
1243 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
1244
1245 DONE;
1246 }")
1247
1248 (define_expand "absdi2_same"
1249 [(set (match_operand:DI 1 "register_operand" "")
1250 (neg:DI (match_operand:DI 0 "register_operand" "")))
1251 (set (match_dup 0)
1252 (if_then_else:DI (ge (match_dup 0) (const_int 0))
1253 (match_dup 0)
1254 (match_dup 1)))]
1255 ""
1256 "")
1257
1258 (define_expand "absdi2_diff"
1259 [(set (match_operand:DI 0 "register_operand" "")
1260 (neg:DI (match_operand:DI 1 "register_operand" "")))
1261 (set (match_dup 0)
1262 (if_then_else:DI (lt (match_dup 1) (const_int 0))
1263 (match_dup 0)
1264 (match_dup 1)))]
1265 ""
1266 "")
1267
1268 (define_split
1269 [(set (match_operand:DI 0 "register_operand" "")
1270 (abs:DI (match_dup 0)))
1271 (clobber (match_operand:DI 2 "register_operand" ""))]
1272 ""
1273 [(set (match_dup 1) (neg:DI (match_dup 0)))
1274 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
1275 (match_dup 0) (match_dup 1)))]
1276 "")
1277
1278 (define_split
1279 [(set (match_operand:DI 0 "register_operand" "")
1280 (abs:DI (match_operand:DI 1 "register_operand" "")))]
1281 "! rtx_equal_p (operands[0], operands[1])"
1282 [(set (match_dup 0) (neg:DI (match_dup 1)))
1283 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
1284 (match_dup 0) (match_dup 1)))]
1285 "")
1286
1287 (define_split
1288 [(set (match_operand:DI 0 "register_operand" "")
1289 (neg:DI (abs:DI (match_dup 0))))
1290 (clobber (match_operand:DI 2 "register_operand" ""))]
1291 ""
1292 [(set (match_dup 1) (neg:DI (match_dup 0)))
1293 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
1294 (match_dup 0) (match_dup 1)))]
1295 "")
1296
1297 (define_split
1298 [(set (match_operand:DI 0 "register_operand" "")
1299 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
1300 "! rtx_equal_p (operands[0], operands[1])"
1301 [(set (match_dup 0) (neg:DI (match_dup 1)))
1302 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
1303 (match_dup 0) (match_dup 1)))]
1304 "")
1305
1306 (define_expand "smaxdi3"
1307 [(set (match_dup 3)
1308 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
1309 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1310 (set (match_operand:DI 0 "register_operand" "")
1311 (if_then_else:DI (eq (match_dup 3) (const_int 0))
1312 (match_dup 1) (match_dup 2)))]
1313 ""
1314 "
1315 { operands[3] = gen_reg_rtx (DImode);
1316 }")
1317
1318 (define_split
1319 [(set (match_operand:DI 0 "register_operand" "")
1320 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
1321 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1322 (clobber (match_operand:DI 3 "register_operand" ""))]
1323 "operands[2] != const0_rtx"
1324 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
1325 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
1326 (match_dup 1) (match_dup 2)))]
1327 "")
1328
1329 (define_insn ""
1330 [(set (match_operand:DI 0 "register_operand" "=r")
1331 (smax:DI (match_operand:DI 1 "register_operand" "0")
1332 (const_int 0)))]
1333 ""
1334 "cmovlt %0,0,%0")
1335
1336 (define_expand "smindi3"
1337 [(set (match_dup 3)
1338 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
1339 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1340 (set (match_operand:DI 0 "register_operand" "")
1341 (if_then_else:DI (ne (match_dup 3) (const_int 0))
1342 (match_dup 1) (match_dup 2)))]
1343 ""
1344 "
1345 { operands[3] = gen_reg_rtx (DImode);
1346 }")
1347
1348 (define_split
1349 [(set (match_operand:DI 0 "register_operand" "")
1350 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
1351 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1352 (clobber (match_operand:DI 3 "register_operand" ""))]
1353 "operands[2] != const0_rtx"
1354 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
1355 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
1356 (match_dup 1) (match_dup 2)))]
1357 "")
1358
1359 (define_insn ""
1360 [(set (match_operand:DI 0 "register_operand" "=r")
1361 (smin:DI (match_operand:DI 1 "register_operand" "0")
1362 (const_int 0)))]
1363 ""
1364 "cmovgt %0,0,%0")
1365
1366 (define_expand "umaxdi3"
1367 [(set (match_dup 3)
1368 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
1369 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1370 (set (match_operand:DI 0 "register_operand" "")
1371 (if_then_else:DI (eq (match_dup 3) (const_int 0))
1372 (match_dup 1) (match_dup 2)))]
1373 ""
1374 "
1375 { operands[3] = gen_reg_rtx (DImode);
1376 }")
1377
1378 (define_split
1379 [(set (match_operand:DI 0 "register_operand" "")
1380 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
1381 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1382 (clobber (match_operand:DI 3 "register_operand" ""))]
1383 "operands[2] != const0_rtx"
1384 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
1385 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
1386 (match_dup 1) (match_dup 2)))]
1387 "")
1388
1389 (define_expand "umindi3"
1390 [(set (match_dup 3)
1391 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
1392 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1393 (set (match_operand:DI 0 "register_operand" "")
1394 (if_then_else:DI (ne (match_dup 3) (const_int 0))
1395 (match_dup 1) (match_dup 2)))]
1396 ""
1397 "
1398 { operands[3] = gen_reg_rtx (DImode);
1399 }")
1400
1401 (define_split
1402 [(set (match_operand:DI 0 "register_operand" "")
1403 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
1404 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1405 (clobber (match_operand:DI 3 "register_operand" ""))]
1406 "operands[2] != const0_rtx"
1407 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
1408 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
1409 (match_dup 1) (match_dup 2)))]
1410 "")
1411
1412 (define_insn ""
1413 [(set (pc)
1414 (if_then_else
1415 (match_operator 1 "signed_comparison_operator"
1416 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
1417 (const_int 0)])
1418 (label_ref (match_operand 0 "" ""))
1419 (pc)))]
1420 ""
1421 "b%C1 %r2,%0"
1422 [(set_attr "type" "ibr")])
1423
1424 (define_insn ""
1425 [(set (pc)
1426 (if_then_else
1427 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1428 (const_int 1)
1429 (const_int 0))
1430 (const_int 0))
1431 (label_ref (match_operand 0 "" ""))
1432 (pc)))]
1433 ""
1434 "blbs %r1,%0"
1435 [(set_attr "type" "ibr")])
1436
1437 (define_insn ""
1438 [(set (pc)
1439 (if_then_else
1440 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1441 (const_int 1)
1442 (const_int 0))
1443 (const_int 0))
1444 (label_ref (match_operand 0 "" ""))
1445 (pc)))]
1446 ""
1447 "blbc %r1,%0"
1448 [(set_attr "type" "ibr")])
1449
1450 (define_split
1451 [(parallel
1452 [(set (pc)
1453 (if_then_else
1454 (match_operator 1 "comparison_operator"
1455 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
1456 (const_int 1)
1457 (match_operand:DI 3 "const_int_operand" ""))
1458 (const_int 0)])
1459 (label_ref (match_operand 0 "" ""))
1460 (pc)))
1461 (clobber (match_operand:DI 4 "register_operand" ""))])]
1462 "INTVAL (operands[3]) != 0"
1463 [(set (match_dup 4)
1464 (lshiftrt:DI (match_dup 2) (match_dup 3)))
1465 (set (pc)
1466 (if_then_else (match_op_dup 1
1467 [(zero_extract:DI (match_dup 4)
1468 (const_int 1)
1469 (const_int 0))
1470 (const_int 0)])
1471 (label_ref (match_dup 0))
1472 (pc)))]
1473 "")
1474 \f
1475 ;; The following are the corresponding floating-point insns. Recall
1476 ;; we need to have variants that expand the arguments from SF mode
1477 ;; to DFmode.
1478
1479 (define_insn ""
1480 [(set (match_operand:DF 0 "register_operand" "=f")
1481 (match_operator:DF 1 "alpha_comparison_operator"
1482 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
1483 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
1484 "TARGET_FP"
1485 "cmpt%C1 %R2,%R3,%0"
1486 [(set_attr "type" "fpop")])
1487
1488 (define_insn ""
1489 [(set (match_operand:DF 0 "register_operand" "=f")
1490 (match_operator:DF 1 "alpha_comparison_operator"
1491 [(float_extend:DF
1492 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
1493 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
1494 "TARGET_FP"
1495 "cmpt%C1 %R2,%R3,%0"
1496 [(set_attr "type" "fpop")])
1497
1498 (define_insn ""
1499 [(set (match_operand:DF 0 "register_operand" "=f")
1500 (match_operator:DF 1 "alpha_comparison_operator"
1501 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
1502 (float_extend:DF
1503 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
1504 "TARGET_FP"
1505 "cmpt%C1 %R2,%R3,%0"
1506 [(set_attr "type" "fpop")])
1507
1508 (define_insn ""
1509 [(set (match_operand:DF 0 "register_operand" "=f")
1510 (match_operator:DF 1 "alpha_comparison_operator"
1511 [(float_extend:DF
1512 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
1513 (float_extend:DF
1514 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
1515 "TARGET_FP"
1516 "cmpt%C1 %R2,%R3,%0"
1517 [(set_attr "type" "fpop")])
1518
1519 (define_insn ""
1520 [(set (match_operand:DF 0 "register_operand" "=f,f")
1521 (if_then_else:DF
1522 (match_operator 3 "signed_comparison_operator"
1523 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
1524 (match_operand:DF 2 "fp0_operand" "G,G")])
1525 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
1526 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
1527 "TARGET_FP"
1528 "@
1529 fcmov%C3 %R4,%R1,%0
1530 fcmov%D3 %R4,%R5,%0"
1531 [(set_attr "type" "fpop")])
1532
1533 (define_insn ""
1534 [(set (match_operand:SF 0 "register_operand" "=f,f")
1535 (if_then_else:SF
1536 (match_operator 3 "signed_comparison_operator"
1537 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
1538 (match_operand:DF 2 "fp0_operand" "G,G")])
1539 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
1540 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
1541 "TARGET_FP"
1542 "@
1543 fcmov%C3 %R4,%R1,%0
1544 fcmov%D3 %R4,%R5,%0"
1545 [(set_attr "type" "fpop")])
1546
1547 (define_insn ""
1548 [(set (match_operand:DF 0 "register_operand" "=f,f")
1549 (if_then_else:DF
1550 (match_operator 3 "signed_comparison_operator"
1551 [(match_operand:DF 1 "reg_or_fp0_operand" "fG,fG")
1552 (match_operand:DF 2 "fp0_operand" "G,G")])
1553 (float_extend:DF (match_operand:SF 4 "reg_or_fp0_operand" "fG,0"))
1554 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
1555 "TARGET_FP"
1556 "@
1557 fcmov%C3 %R4,%R1,%0
1558 fcmov%D3 %R4,%R5,%0"
1559 [(set_attr "type" "fpop")])
1560
1561 (define_insn ""
1562 [(set (match_operand:DF 0 "register_operand" "=f,f")
1563 (if_then_else:DF
1564 (match_operator 3 "signed_comparison_operator"
1565 [(float_extend:DF
1566 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
1567 (match_operand:DF 2 "fp0_operand" "G,G")])
1568 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
1569 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
1570 "TARGET_FP"
1571 "@
1572 fcmov%C3 %R4,%R1,%0
1573 fcmov%D3 %R4,%R5,%0"
1574 [(set_attr "type" "fpop")])
1575
1576 (define_insn ""
1577 [(set (match_operand:SF 0 "register_operand" "=f,f")
1578 (if_then_else:SF
1579 (match_operator 3 "signed_comparison_operator"
1580 [(float_extend:DF
1581 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
1582 (match_operand:DF 2 "fp0_operand" "G,G")])
1583 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
1584 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
1585 "TARGET_FP"
1586 "@
1587 fcmov%C3 %R4,%R1,%0
1588 fcmov%D3 %R4,%R5,%0"
1589 [(set_attr "type" "fpop")])
1590
1591 (define_insn ""
1592 [(set (match_operand:DF 0 "register_operand" "=f,f")
1593 (if_then_else:DF
1594 (match_operator 3 "signed_comparison_operator"
1595 [(float_extend:DF
1596 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
1597 (match_operand:DF 2 "fp0_operand" "G,G")])
1598 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
1599 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
1600 "TARGET_FP"
1601 "@
1602 fcmov%C3 %R4,%R1,%0
1603 fcmov%D3 %R4,%R5,%0"
1604 [(set_attr "type" "fpop")])
1605
1606 (define_expand "smaxdf3"
1607 [(set (match_dup 3)
1608 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
1609 (match_operand:DF 2 "reg_or_fp0_operand" "")))
1610 (set (match_operand:DF 0 "register_operand" "")
1611 (if_then_else:DF (eq (match_dup 3) (const_int 0))
1612 (match_dup 1) (match_dup 2)))]
1613 "TARGET_FP"
1614 "
1615 { operands[3] = gen_reg_rtx (DFmode);
1616 }")
1617
1618 (define_expand "smindf3"
1619 [(set (match_dup 3)
1620 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
1621 (match_operand:DF 2 "reg_or_fp0_operand" "")))
1622 (set (match_operand:DF 0 "register_operand" "")
1623 (if_then_else:DF (ne (match_dup 3) (const_int 0))
1624 (match_dup 1) (match_dup 2)))]
1625 "TARGET_FP"
1626 "
1627 { operands[3] = gen_reg_rtx (DFmode);
1628 }")
1629
1630 (define_expand "smaxsf3"
1631 [(set (match_dup 3)
1632 (le:DF (match_operand:SF 1 "reg_or_fp0_operand" "")
1633 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
1634 (set (match_operand:SF 0 "register_operand" "")
1635 (if_then_else:SF (eq (match_dup 3) (const_int 0))
1636 (match_dup 1) (match_dup 2)))]
1637 "TARGET_FP"
1638 "
1639 { operands[3] = gen_reg_rtx (SFmode);
1640 }")
1641
1642 (define_expand "sminsf3"
1643 [(set (match_dup 3)
1644 (lt:DF (match_operand:SF 1 "reg_or_fp0_operand" "")
1645 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
1646 (set (match_operand:SF 0 "register_operand" "")
1647 (if_then_else:SF (ne (match_dup 3) (const_int 0))
1648 (match_dup 1) (match_dup 2)))]
1649 "TARGET_FP"
1650 "
1651 { operands[3] = gen_reg_rtx (SFmode);
1652 }")
1653
1654 (define_insn ""
1655 [(set (pc)
1656 (if_then_else
1657 (match_operator 1 "signed_comparison_operator"
1658 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
1659 (match_operand:DF 3 "fp0_operand" "G")])
1660 (label_ref (match_operand 0 "" ""))
1661 (pc)))]
1662 "TARGET_FP"
1663 "fb%C1 %R2,%0"
1664 [(set_attr "type" "fbr")])
1665
1666 (define_insn ""
1667 [(set (pc)
1668 (if_then_else
1669 (match_operator 1 "signed_comparison_operator"
1670 [(float_extend:DF
1671 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
1672 (match_operand:DF 3 "fp0_operand" "G")])
1673 (label_ref (match_operand 0 "" ""))
1674 (pc)))]
1675 "TARGET_FP"
1676 "fb%C1 %R2,%0"
1677 [(set_attr "type" "fbr")])
1678 \f
1679 ;; These are the main define_expand's used to make conditional branches
1680 ;; and compares.
1681
1682 (define_expand "cmpdf"
1683 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
1684 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
1685 ""
1686 "
1687 {
1688 alpha_compare_op0 = operands[0];
1689 alpha_compare_op1 = operands[1];
1690 alpha_compare_fp_p = 1;
1691 DONE;
1692 }")
1693
1694 (define_expand "cmpdi"
1695 [(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "")
1696 (match_operand:DI 1 "reg_or_8bit_operand" "")))]
1697 ""
1698 "
1699 {
1700 alpha_compare_op0 = operands[0];
1701 alpha_compare_op1 = operands[1];
1702 alpha_compare_fp_p = 0;
1703 DONE;
1704 }")
1705
1706 (define_expand "beq"
1707 [(set (match_dup 1) (match_dup 2))
1708 (set (pc)
1709 (if_then_else (match_dup 3)
1710 (label_ref (match_operand 0 "" ""))
1711 (pc)))]
1712 ""
1713 "
1714 {
1715 enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode;
1716 operands[1] = gen_reg_rtx (mode);
1717 operands[2] = gen_rtx (EQ, mode, alpha_compare_op0, alpha_compare_op1);
1718 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode));
1719 }")
1720
1721 (define_expand "bne"
1722 [(set (match_dup 1) (match_dup 2))
1723 (set (pc)
1724 (if_then_else (match_dup 3)
1725 (label_ref (match_operand 0 "" ""))
1726 (pc)))]
1727 ""
1728 "
1729 {
1730 enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode;
1731 operands[1] = gen_reg_rtx (mode);
1732 operands[2] = gen_rtx (EQ, mode, alpha_compare_op0, alpha_compare_op1);
1733 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], CONST0_RTX (mode));
1734 }")
1735
1736 (define_expand "blt"
1737 [(set (match_dup 1) (match_dup 2))
1738 (set (pc)
1739 (if_then_else (match_dup 3)
1740 (label_ref (match_operand 0 "" ""))
1741 (pc)))]
1742 ""
1743 "
1744 {
1745 enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode;
1746 operands[1] = gen_reg_rtx (mode);
1747 operands[2] = gen_rtx (LT, mode, alpha_compare_op0, alpha_compare_op1);
1748 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode));
1749 }")
1750
1751 (define_expand "ble"
1752 [(set (match_dup 1) (match_dup 2))
1753 (set (pc)
1754 (if_then_else (match_dup 3)
1755 (label_ref (match_operand 0 "" ""))
1756 (pc)))]
1757 ""
1758 "
1759 {
1760 enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode;
1761 operands[1] = gen_reg_rtx (mode);
1762 operands[2] = gen_rtx (LE, mode, alpha_compare_op0, alpha_compare_op1);
1763 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode));
1764 }")
1765
1766 (define_expand "bgt"
1767 [(set (match_dup 1) (match_dup 2))
1768 (set (pc)
1769 (if_then_else (match_dup 3)
1770 (label_ref (match_operand 0 "" ""))
1771 (pc)))]
1772 ""
1773 "
1774 {
1775 if (alpha_compare_fp_p)
1776 {
1777 operands[1] = gen_reg_rtx (DFmode);
1778 operands[2] = gen_rtx (LT, DFmode, alpha_compare_op1, alpha_compare_op0);
1779 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode));
1780 }
1781 else
1782 {
1783 operands[1] = gen_reg_rtx (DImode);
1784 operands[2] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1);
1785 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
1786 }
1787 }")
1788
1789 (define_expand "bge"
1790 [(set (match_dup 1) (match_dup 2))
1791 (set (pc)
1792 (if_then_else (match_dup 3)
1793 (label_ref (match_operand 0 "" ""))
1794 (pc)))]
1795 ""
1796 "
1797 {
1798 if (alpha_compare_fp_p)
1799 {
1800 operands[1] = gen_reg_rtx (DFmode);
1801 operands[2] = gen_rtx (LE, DFmode, alpha_compare_op1, alpha_compare_op0);
1802 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode));
1803 }
1804 else
1805 {
1806 operands[1] = gen_reg_rtx (DImode);
1807 operands[2] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1);
1808 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
1809 }
1810 }")
1811
1812 (define_expand "bltu"
1813 [(set (match_dup 1) (match_dup 2))
1814 (set (pc)
1815 (if_then_else (match_dup 3)
1816 (label_ref (match_operand 0 "" ""))
1817 (pc)))]
1818 ""
1819 "
1820 {
1821 operands[1] = gen_reg_rtx (DImode);
1822 operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
1823 operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx);
1824 }")
1825
1826 (define_expand "bleu"
1827 [(set (match_dup 1) (match_dup 2))
1828 (set (pc)
1829 (if_then_else (match_dup 3)
1830 (label_ref (match_operand 0 "" ""))
1831 (pc)))]
1832 ""
1833 "
1834 {
1835 operands[1] = gen_reg_rtx (DImode);
1836 operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
1837 operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx);
1838 }")
1839
1840 (define_expand "bgtu"
1841 [(set (match_dup 1) (match_dup 2))
1842 (set (pc)
1843 (if_then_else (match_dup 3)
1844 (label_ref (match_operand 0 "" ""))
1845 (pc)))]
1846 ""
1847 "
1848 {
1849 operands[1] = gen_reg_rtx (DImode);
1850 operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
1851 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
1852 }")
1853
1854 (define_expand "bgeu"
1855 [(set (match_dup 1) (match_dup 2))
1856 (set (pc)
1857 (if_then_else (match_dup 3)
1858 (label_ref (match_operand 0 "" ""))
1859 (pc)))]
1860 ""
1861 "
1862 {
1863 operands[1] = gen_reg_rtx (DImode);
1864 operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
1865 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
1866 }")
1867
1868 (define_expand "seq"
1869 [(set (match_operand:DI 0 "register_operand" "")
1870 (match_dup 1))]
1871 ""
1872 "
1873 {
1874 if (alpha_compare_fp_p)
1875 FAIL;
1876
1877 operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1);
1878 }")
1879
1880 (define_expand "sne"
1881 [(set (match_operand:DI 0 "register_operand" "")
1882 (match_dup 1))
1883 (set (match_dup 0) (xor:DI (match_dup 0) (const_int 1)))]
1884 ""
1885 "
1886 {
1887 if (alpha_compare_fp_p)
1888 FAIL;
1889
1890 operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1);
1891 }")
1892
1893 (define_expand "slt"
1894 [(set (match_operand:DI 0 "register_operand" "")
1895 (match_dup 1))]
1896 ""
1897 "
1898 {
1899 if (alpha_compare_fp_p)
1900 FAIL;
1901
1902 operands[1] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1);
1903 }")
1904
1905 (define_expand "sle"
1906 [(set (match_operand:DI 0 "register_operand" "")
1907 (match_dup 1))]
1908 ""
1909 "
1910 {
1911 if (alpha_compare_fp_p)
1912 FAIL;
1913
1914 operands[1] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1);
1915 }")
1916
1917 (define_expand "sgt"
1918 [(set (match_operand:DI 0 "register_operand" "")
1919 (match_dup 1))]
1920 ""
1921 "
1922 {
1923 if (alpha_compare_fp_p)
1924 FAIL;
1925
1926 operands[1] = gen_rtx (LT, DImode, force_reg (DImode, alpha_compare_op1),
1927 alpha_compare_op0);
1928 }")
1929
1930 (define_expand "sge"
1931 [(set (match_operand:DI 0 "register_operand" "")
1932 (match_dup 1))]
1933 ""
1934 "
1935 {
1936 if (alpha_compare_fp_p)
1937 FAIL;
1938
1939 operands[1] = gen_rtx (LE, DImode, force_reg (DImode, alpha_compare_op1),
1940 alpha_compare_op0);
1941 }")
1942
1943 (define_expand "sltu"
1944 [(set (match_operand:DI 0 "register_operand" "")
1945 (match_dup 1))]
1946 ""
1947 "
1948 {
1949 if (alpha_compare_fp_p)
1950 FAIL;
1951
1952 operands[1] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
1953 }")
1954
1955 (define_expand "sleu"
1956 [(set (match_operand:DI 0 "register_operand" "")
1957 (match_dup 1))]
1958 ""
1959 "
1960 {
1961 if (alpha_compare_fp_p)
1962 FAIL;
1963
1964 operands[1] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
1965 }")
1966
1967 (define_expand "sgtu"
1968 [(set (match_operand:DI 0 "register_operand" "")
1969 (match_dup 1))]
1970 ""
1971 "
1972 {
1973 if (alpha_compare_fp_p)
1974 FAIL;
1975
1976 operands[1] = gen_rtx (LTU, DImode, force_reg (DImode, alpha_compare_op1),
1977 alpha_compare_op0);
1978 }")
1979
1980 (define_expand "sgeu"
1981 [(set (match_operand:DI 0 "register_operand" "")
1982 (match_dup 1))]
1983 ""
1984 "
1985 {
1986 if (alpha_compare_fp_p)
1987 FAIL;
1988
1989 operands[1] = gen_rtx (LEU, DImode, force_reg (DImode, alpha_compare_op1),
1990 alpha_compare_op0);
1991 }")
1992 \f
1993 ;; These define_split definitions are used in cases when comparisons have
1994 ;; not be stated in the correct way and we need to reverse the second
1995 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
1996 ;; comparison that tests the result being reversed. We have one define_split
1997 ;; for each use of a comparison. They do not match valid insns and need
1998 ;; not generate valid insns.
1999 ;;
2000 ;; We can also handle equality comparisons (and inequality comparisons in
2001 ;; cases where the resulting add cannot overflow) with out-of-range numbers by
2002 ;; doing an add followed by a comparison with zero. For this case, we
2003 ;; also have an SImode pattern since we can merge the add and sign
2004 ;; extend and the order doesn't matter.
2005 ;;
2006 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
2007 ;; operation could have been generated.
2008
2009 (define_split
2010 [(set (match_operand:DI 0 "register_operand" "")
2011 (if_then_else:DI
2012 (match_operator 1 "comparison_operator"
2013 [(match_operand:DI 2 "reg_or_0_operand" "")
2014 (match_operand:DI 3 "reg_or_cint_operand" "")])
2015 (match_operand:DI 4 "reg_or_cint_operand" "")
2016 (match_operand:DI 5 "reg_or_cint_operand" "")))
2017 (clobber (match_operand:DI 6 "register_operand" ""))]
2018 "operands[3] != const0_rtx"
2019 [(set (match_dup 6) (match_dup 7))
2020 (set (match_dup 0)
2021 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
2022 "
2023 { enum rtx_code code = GET_CODE (operands[1]);
2024 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
2025
2026 /* If we are comparing for equality with a constant and that constant
2027 appears in the arm when the register equals the constant, use the
2028 register since that is more likely to match (and to produce better code
2029 if both would). */
2030
2031 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
2032 && rtx_equal_p (operands[4], operands[3]))
2033 operands[4] = operands[2];
2034
2035 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
2036 && rtx_equal_p (operands[5], operands[3]))
2037 operands[5] = operands[2];
2038
2039 if ((code == NE || code == EQ
2040 || (extended_count (operands[2], DImode, unsignedp) >= 1
2041 && extended_count (operands[3], DImode, unsignedp) >= 1))
2042 && GET_CODE (operands[3]) == CONST_INT
2043 && (unsigned) INTVAL (operands[3]) > 255)
2044 {
2045 operands[7] = gen_rtx (PLUS, DImode, operands[2],
2046 GEN_INT (- INTVAL (operands[3])));
2047 operands[8] = gen_rtx (code, VOIDmode, operands[6], const0_rtx);
2048 }
2049
2050 else if (code == EQ || code == LE || code == LT
2051 || code == LEU || code == LTU)
2052 {
2053 operands[7] = gen_rtx (code, DImode, operands[2], operands[3]);
2054 operands[8] = gen_rtx (NE, VOIDmode, operands[6], const0_rtx);
2055 }
2056 else
2057 {
2058 operands[7] = gen_rtx (reverse_condition (code), DImode, operands[2],
2059 operands[3]);
2060 operands[8] = gen_rtx (EQ, VOIDmode, operands[6], const0_rtx);
2061 }
2062 }")
2063
2064 (define_split
2065 [(set (match_operand:DI 0 "register_operand" "")
2066 (if_then_else:DI
2067 (match_operator 1 "comparison_operator"
2068 [(match_operand:SI 2 "reg_or_0_operand" "")
2069 (match_operand:SI 3 "const_int_operand" "")])
2070 (match_operand:DI 4 "reg_or_8bit_operand" "")
2071 (match_operand:DI 5 "reg_or_8bit_operand" "")))
2072 (clobber (match_operand:DI 6 "register_operand" ""))]
2073 "(unsigned) INTVAL (operands[3]) > 255"
2074 [(set (match_dup 6) (match_dup 7))
2075 (set (match_dup 0)
2076 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
2077 "
2078 { enum rtx_code code = GET_CODE (operands[1]);
2079 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
2080
2081 if ((code != NE && code != EQ
2082 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
2083 && extended_count (operands[3], DImode, unsignedp) >= 1)))
2084 FAIL;
2085
2086 operands[7] = gen_rtx (SIGN_EXTEND, DImode,
2087 gen_rtx (PLUS, SImode, operands[2],
2088 GEN_INT (- INTVAL (operands[3]))));
2089 operands[8] = gen_rtx (GET_CODE (operands[1]), VOIDmode, operands[6],
2090 const0_rtx);
2091 }")
2092
2093 (define_split
2094 [(set (pc)
2095 (if_then_else
2096 (match_operator 1 "comparison_operator"
2097 [(match_operand:DI 2 "reg_or_0_operand" "")
2098 (match_operand:DI 3 "reg_or_cint_operand" "")])
2099 (label_ref (match_operand 0 "" ""))
2100 (pc)))
2101 (clobber (match_operand:DI 4 "register_operand" ""))]
2102 "operands[3] != const0_rtx"
2103 [(set (match_dup 4) (match_dup 5))
2104 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
2105 "
2106 { enum rtx_code code = GET_CODE (operands[1]);
2107 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
2108
2109 if ((code == NE || code == EQ
2110 || (extended_count (operands[2], DImode, unsignedp) >= 1
2111 && extended_count (operands[3], DImode, unsignedp) >= 1))
2112 && GET_CODE (operands[3]) == CONST_INT
2113 && (unsigned) INTVAL (operands[3]) > 255)
2114 {
2115 operands[5] = gen_rtx (PLUS, DImode, operands[2],
2116 GEN_INT (- INTVAL (operands[3])));
2117 operands[6] = gen_rtx (code, VOIDmode, operands[4], const0_rtx);
2118 }
2119
2120 else if (code == EQ || code == LE || code == LT
2121 || code == LEU || code == LTU)
2122 {
2123 operands[5] = gen_rtx (code, DImode, operands[2], operands[3]);
2124 operands[6] = gen_rtx (NE, VOIDmode, operands[4], const0_rtx);
2125 }
2126 else
2127 {
2128 operands[5] = gen_rtx (reverse_condition (code), DImode, operands[2],
2129 operands[3]);
2130 operands[6] = gen_rtx (EQ, VOIDmode, operands[4], const0_rtx);
2131 }
2132 }")
2133
2134 (define_split
2135 [(set (pc)
2136 (if_then_else
2137 (match_operator 1 "comparison_operator"
2138 [(match_operand:SI 2 "reg_or_0_operand" "")
2139 (match_operand:SI 3 "const_int_operand" "")])
2140 (label_ref (match_operand 0 "" ""))
2141 (pc)))
2142 (clobber (match_operand:DI 4 "register_operand" ""))]
2143 "INTVAL (operands[3]) < 0
2144 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
2145 [(set (match_dup 4) (match_dup 5))
2146 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
2147 "
2148 { operands[5] = gen_rtx (SIGN_EXTEND, DImode,
2149 gen_rtx (PLUS, SImode, operands[2],
2150 GEN_INT (- INTVAL (operands[3]))));
2151 operands[6] = gen_rtx (GET_CODE (operands[1]), VOIDmode,
2152 operands[4], const0_rtx);
2153 }")
2154 \f
2155 ;; Here are the CALL and unconditional branch insns.
2156
2157 (define_expand "call"
2158 [(parallel [(call (mem:DI (match_dup 2))
2159 (match_operand 1 "" ""))
2160 (use (match_operand:DI 0 "" ""))
2161 (clobber (reg:DI 26))])]
2162 ""
2163 "
2164 { if (GET_CODE (operands[0]) != MEM)
2165 abort ();
2166 operands[0] = XEXP (operands[0], 0);
2167
2168 operands[2] = gen_rtx (REG, DImode, 27);
2169 emit_move_insn (operands[2], operands[0]);
2170
2171 if (GET_CODE (operands[0]) != SYMBOL_REF)
2172 operands[0] = const0_rtx;
2173 }")
2174
2175 (define_expand "call_value"
2176 [(parallel [(set (match_operand 0 "" "")
2177 (call (mem:DI (match_dup 3))
2178 (match_operand 2 "" "")))
2179 (use (match_operand:DI 1 "" ""))
2180 (clobber (reg:DI 26))])]
2181 ""
2182 "
2183 { if (GET_CODE (operands[1]) != MEM)
2184 abort ();
2185
2186 operands[1] = XEXP (operands[1], 0);
2187
2188 operands[3] = gen_rtx (REG, DImode, 27);
2189 emit_move_insn (operands[3], operands[1]);
2190
2191 if (GET_CODE (operands[1]) != SYMBOL_REF)
2192 operands[1] = const0_rtx;
2193 }")
2194
2195 (define_insn ""
2196 [(call (mem:DI (reg:DI 27))
2197 (match_operand 0 "" ""))
2198 (use (match_operand:DI 1 "" ""))
2199 (clobber (reg:DI 26))]
2200 ""
2201 "*
2202 { if (alpha_gp_dead_after (insn))
2203 return \"jsr $26,($27),%1\";
2204 else
2205 return \"jsr $26,($27),%1\;ldgp $29,0($26)\";
2206 }"
2207 [(set_attr "type" "jsr")])
2208
2209 (define_insn ""
2210 [(set (match_operand 0 "register_operand" "=rf")
2211 (call (mem:DI (reg:DI 27))
2212 (match_operand 1 "" "")))
2213 (use (match_operand:DI 2 "" ""))
2214 (clobber (reg:DI 26))]
2215 ""
2216 "*
2217 { if (alpha_gp_dead_after (insn))
2218 return \"jsr $26,($27),%2\";
2219 else
2220 return \"jsr $26,($27),%2\;ldgp $29,0($26)\";
2221 }"
2222 [(set_attr "type" "jsr")])
2223
2224 (define_insn ""
2225 [(call (mem:DI (match_operand 1 "current_function_operand" "i"))
2226 (match_operand 0 "" ""))
2227 (use (match_dup 1))
2228 (clobber (reg:DI 26))]
2229 ""
2230 "bsr $26,%F1"
2231 [(set_attr "type" "ibr")])
2232
2233 (define_insn ""
2234 [(set (match_operand 0 "register_operand" "=rf")
2235 (call (mem:DI (match_operand 1 "current_function_operand" "i"))
2236 (match_operand 2 "" "")))
2237 (use (match_dup 1))
2238 (clobber (reg:DI 26))]
2239 ""
2240 "bsr $26,%F1"
2241 [(set_attr "type" "ibr")])
2242
2243 (define_insn "jump"
2244 [(set (pc)
2245 (label_ref (match_operand 0 "" "")))]
2246 ""
2247 "br $31,%l0"
2248 [(set_attr "type" "ibr")])
2249
2250 (define_insn "return"
2251 [(return)]
2252 "direct_return ()"
2253 "ret $31,($26),1"
2254 [(set_attr "type" "ibr")])
2255
2256 (define_insn "indirect_jump"
2257 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
2258 ""
2259 "jmp $31,(%0),0"
2260 [(set_attr "type" "ibr")])
2261
2262 (define_insn "nop"
2263 [(const_int 0)]
2264 ""
2265 "bis $31,$31,$31"
2266 [(set_attr "type" "iaddlog")])
2267
2268 (define_expand "tablejump"
2269 [(set (match_dup 3)
2270 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
2271 (parallel [(set (pc) (plus:DI (match_dup 3) (reg:DI 29)))
2272 (use (label_ref (match_operand 1 "" "")))
2273 (clobber (match_scratch:DI 2 "=r"))])]
2274 ""
2275 "
2276 { operands[3] = gen_reg_rtx (DImode); }")
2277
2278 (define_insn ""
2279 [(set (pc)
2280 (plus:DI (match_operand:DI 0 "register_operand" "r")
2281 (reg:DI 29)))
2282 (use (label_ref (match_operand 1 "" "")))
2283 (clobber (match_scratch:DI 2 "=r"))]
2284 ""
2285 "*
2286 { rtx best_label = 0;
2287 rtx jump_table_insn = next_active_insn (operands[1]);
2288
2289 if (GET_CODE (jump_table_insn) == JUMP_INSN
2290 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_VEC)
2291 {
2292 rtx jump_table = PATTERN (jump_table_insn);
2293 int n_labels = XVECLEN (jump_table, 0);
2294 int best_count = -1;
2295 int i, j;
2296
2297 for (i = 0; i < n_labels; i++)
2298 {
2299 int count = 1;
2300
2301 for (j = i + 1; j < n_labels; j++)
2302 if (XEXP (XVECEXP (jump_table, 0, i), 0)
2303 == XEXP (XVECEXP (jump_table, 0, j), 0))
2304 count++;
2305
2306 if (count > best_count)
2307 best_count = count, best_label = XVECEXP (jump_table, 0, i);
2308 }
2309 }
2310
2311 if (best_label)
2312 {
2313 operands[3] = best_label;
2314 return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
2315 }
2316 else
2317 return \"addq %0,$29,%2\;jmp $31,(%2),0\";
2318 }"
2319 [(set_attr "type" "ibr")])
2320
2321 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
2322 ;; want to have to include pal.h in our .s file.
2323 (define_insn ""
2324 [(unspec_volatile [(const_int 0)] 0)]
2325 ""
2326 "call_pal 0x86")
2327 \f
2328 ;; Finally, we have the basic data motion insns. The byte and word insns
2329 ;; are done via define_expand. Start with the floating-point insns, since
2330 ;; they are simpler.
2331
2332 (define_insn ""
2333 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
2334 (match_operand:SF 1 "input_operand" "r,m,rG,f,G,m,fG"))]
2335 "register_operand (operands[0], SFmode)
2336 || reg_or_fp0_operand (operands[1], SFmode)"
2337 "@
2338 bis %1,%1,%0
2339 ldl %0,%1
2340 stl %r1,%0
2341 cpys %1,%1,%0
2342 cpys $f31,$f31,%0
2343 lds %0,%1
2344 sts %R1,%0"
2345 [(set_attr "type" "iaddlog,ld,st,fpop,fpop,ld,st")])
2346
2347 (define_insn ""
2348 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
2349 (match_operand:DF 1 "input_operand" "r,m,rG,f,G,m,fG"))]
2350 "register_operand (operands[0], DFmode)
2351 || reg_or_fp0_operand (operands[1], DFmode)"
2352 "@
2353 bis %1,%1,%0
2354 ldq %0,%1
2355 stq %r1,%0
2356 cpys %1,%1,%0
2357 cpys $f31,$f31,%0
2358 ldt %0,%1
2359 stt %R1,%0"
2360 [(set_attr "type" "iaddlog,ld,st,fpop,fpop,ld,st")])
2361
2362 (define_expand "movsf"
2363 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2364 (match_operand:SF 1 "general_operand" ""))]
2365 ""
2366 "
2367 {
2368 if (GET_CODE (operands[0]) == MEM
2369 && ! reg_or_fp0_operand (operands[1], SFmode))
2370 operands[1] = force_reg (SFmode, operands[1]);
2371 }")
2372
2373 (define_expand "movdf"
2374 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2375 (match_operand:DF 1 "general_operand" ""))]
2376 ""
2377 "
2378 {
2379 if (GET_CODE (operands[0]) == MEM
2380 && ! reg_or_fp0_operand (operands[1], DFmode))
2381 operands[1] = force_reg (DFmode, operands[1]);
2382 }")
2383
2384 ;; There is a problem with 32-bit values in FP registers. We keep such
2385 ;; values in the register as a quadword. This is done on loads by using
2386 ;; the cvtlq instruction. On stores, we can't do anything directly from
2387 ;; floating-point registers. Disallow such an operation and let reload
2388 ;; use an integer register instead. Don't encourage 32-bit values to
2389 ;; be placed in FP registers at all.
2390
2391 (define_insn ""
2392 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,*f")
2393 (match_operand:SI 1 "input_operand" "r,J,I,K,L,m,rJ,*f,J,m"))]
2394 "register_operand (operands[0], SImode)
2395 || reg_or_0_operand (operands[1], SImode)"
2396 "@
2397 bis %1,%1,%0
2398 bis $31,$31,%0
2399 bis $31,%1,%0
2400 lda %0,%1
2401 ldah %0,%h1
2402 ldl %0,%1
2403 stl %r1,%0
2404 cpys %1,%1,%0
2405 cpys $f31,$f31,%0
2406 lds %0,%1\;cvtlq %0,%0"
2407 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ld,st,fpop,fpop,ld")])
2408
2409 (define_insn ""
2410 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,f,f")
2411 (match_operand:HI 1 "input_operand" "r,J,I,n,f,J"))]
2412 "register_operand (operands[0], HImode)
2413 || register_operand (operands[1], HImode)"
2414 "@
2415 bis %1,%1,%0
2416 bis $31,$31,%0
2417 bis $31,%1,%0
2418 lda %0,%L1
2419 cpys %1,%1,%0
2420 cpys $f31,$f31,%0"
2421 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,fpop,fpop")])
2422
2423 (define_insn ""
2424 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,f,f")
2425 (match_operand:QI 1 "input_operand" "r,J,I,n,f,J"))]
2426 "register_operand (operands[0], QImode)
2427 || register_operand (operands[1], QImode)"
2428 "@
2429 bis %1,%1,%0
2430 bis $31,$31,%0
2431 bis $31,%1,%0
2432 lda %0,%L1
2433 cpys %1,%1,%0
2434 cpys $f31,$f31,%0"
2435 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,fpop,fpop")])
2436
2437 ;; We do two major things here: handle mem->mem and construct long
2438 ;; constants.
2439
2440 (define_expand "movsi"
2441 [(set (match_operand:SI 0 "general_operand" "")
2442 (match_operand:SI 1 "general_operand" ""))]
2443 ""
2444 "
2445 {
2446 if (GET_CODE (operands[0]) == MEM
2447 && ! reg_or_0_operand (operands[1], SImode))
2448 operands[1] = force_reg (SImode, operands[1]);
2449
2450 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
2451 ;
2452 else if (GET_CODE (operands[1]) == CONST_INT)
2453 {
2454 if (alpha_emit_set_const (operands[0], INTVAL (operands[1]), 3))
2455 DONE;
2456 else
2457 abort ();
2458 }
2459 }")
2460
2461 ;; Split a load of a large constant into the appropriate two-insn
2462 ;; sequence.
2463
2464 (define_split
2465 [(set (match_operand:SI 0 "register_operand" "")
2466 (match_operand:SI 1 "const_int_operand" ""))]
2467 "! add_operand (operands[1], SImode)"
2468 [(set (match_dup 0) (match_dup 2))
2469 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
2470 "
2471 { if (alpha_emit_set_const (operands[0], INTVAL (operands[1]), 2))
2472 DONE;
2473 else
2474 FAIL;
2475 }")
2476
2477 (define_insn ""
2478 [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,r,r,m,f,f,f,m")
2479 (match_operand:DI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,m,fG"))]
2480 "register_operand (operands[0], DImode)
2481 || reg_or_0_operand (operands[1], DImode)"
2482 "@
2483 bis %1,%1,%0
2484 bis $31,$31,%0
2485 bis $31,%1,%0
2486 lda %0,%1
2487 ldah %0,%h1
2488 lda %0,%1
2489 ldq%A1 %0,%1
2490 stq%A0 %r1,%0
2491 cpys %1,%1,%0
2492 cpys $f31,$f31,%0
2493 ldt %0,%1
2494 stt %R1,%0"
2495 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ldsym,ld,st,fpop,fpop,ld,st")])
2496
2497 ;; We do three major things here: handle mem->mem, put 64-bit constants in
2498 ;; memory, and construct long 32-bit constants.
2499
2500 (define_expand "movdi"
2501 [(set (match_operand:DI 0 "general_operand" "")
2502 (match_operand:DI 1 "general_operand" ""))]
2503 ""
2504 "
2505 {
2506 if (GET_CODE (operands[0]) == MEM
2507 && ! reg_or_0_operand (operands[1], DImode))
2508 operands[1] = force_reg (DImode, operands[1]);
2509
2510 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
2511 ;
2512 else if (GET_CODE (operands[1]) == CONST_INT
2513 && alpha_emit_set_const (operands[0], INTVAL (operands[1]), 3))
2514 DONE;
2515 else if (CONSTANT_P (operands[1]))
2516 {
2517 operands[1] = force_const_mem (DImode, operands[1]);
2518 if (reload_in_progress)
2519 {
2520 emit_move_insn (operands[0], XEXP (operands[1], 0));
2521 XEXP (operands[1], 0) = operands[0];
2522 }
2523 else
2524 operands[1] = validize_mem (operands[1]);
2525 }
2526 else
2527 abort ();
2528 }")
2529
2530 ;; Split a load of a large constant into the appropriate two-insn
2531 ;; sequence.
2532
2533 (define_split
2534 [(set (match_operand:DI 0 "register_operand" "")
2535 (match_operand:DI 1 "const_int_operand" ""))]
2536 "! add_operand (operands[1], DImode)"
2537 [(set (match_dup 0) (match_dup 2))
2538 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
2539 "
2540 { if (alpha_emit_set_const (operands[0], INTVAL (operands[1]), 2))
2541 DONE;
2542 else
2543 FAIL;
2544 }")
2545
2546 ;; These are the partial-word cases.
2547 ;;
2548 ;; First we have the code to load an aligned word. Operand 0 is the register
2549 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
2550 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
2551 ;; number of bits within the word that the value is. Operand 3 is an SImode
2552 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
2553 ;; same register. It is allowed to conflict with operand 1 as well.
2554
2555 (define_expand "aligned_loadqi"
2556 [(set (match_operand:SI 3 "register_operand" "")
2557 (match_operand:SI 1 "memory_operand" ""))
2558 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
2559 (zero_extract:DI (subreg:DI (match_dup 3) 0)
2560 (const_int 8)
2561 (match_operand:DI 2 "const_int_operand" "")))]
2562
2563 ""
2564 "")
2565
2566 (define_expand "aligned_loadhi"
2567 [(set (match_operand:SI 3 "register_operand" "")
2568 (match_operand:SI 1 "memory_operand" ""))
2569 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
2570 (zero_extract:DI (subreg:DI (match_dup 3) 0)
2571 (const_int 16)
2572 (match_operand:DI 2 "const_int_operand" "")))]
2573
2574 ""
2575 "")
2576
2577 ;; Similar for unaligned loads. For QImode, we use the sequence from the
2578 ;; Alpha Architecture manual. However, for HImode, we do not. HImode pointers
2579 ;; are normally aligned to the byte boundary, so an HImode object cannot
2580 ;; cross a longword boundary. We could use a sequence similar to that for
2581 ;; QImode, but that would fail if the pointer, was, in fact, not aligned.
2582 ;; Instead, we clear bit 1 in the address and do an ldl. If the low-order
2583 ;; bit was not aligned, this will trap and the trap handler will do what is
2584 ;; needed.
2585 ;;
2586 ;; Here operand 1 is the address. Operands 2 and 3 are temporaries, where
2587 ;; operand 3 can overlap the input and output registers.
2588
2589 (define_expand "unaligned_loadqi"
2590 [(set (match_operand:DI 2 "register_operand" "")
2591 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
2592 (const_int -8))))
2593 (set (match_operand:DI 3 "register_operand" "")
2594 (match_dup 1))
2595 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
2596 (zero_extract:DI (match_dup 2)
2597 (const_int 8)
2598 (ashift:DI (match_dup 3) (const_int 3))))]
2599 ""
2600 "")
2601
2602 ;; For this, the address must already be in a register. We also need two
2603 ;; DImode temporaries, neither of which may overlap the input (and hence the
2604 ;; output, since they might be the same register), but both of which may
2605 ;; be the same.
2606
2607 (define_expand "unaligned_loadhi"
2608 [(set (match_operand:DI 2 "register_operand" "")
2609 (and:DI (match_operand:DI 1 "register_operand" "")
2610 (const_int -7)))
2611 (set (match_operand:DI 3 "register_operand" "")
2612 (mem:DI (match_dup 2)))
2613 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
2614 (zero_extract:DI (match_dup 3)
2615 (const_int 16)
2616 (ashift:DI (match_dup 1) (const_int 3))))]
2617 ""
2618 "")
2619
2620 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
2621 ;; aligned SImode MEM. Operand 1 is the register containing the
2622 ;; byte or word to store. Operand 2 is the number of bits within the word that
2623 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
2624
2625 (define_expand "aligned_store"
2626 [(set (match_operand:SI 3 "register_operand" "")
2627 (match_operand:SI 0 "memory_operand" ""))
2628 (set (subreg:DI (match_dup 3) 0)
2629 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
2630 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
2631 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
2632 (match_operand:DI 2 "const_int_operand" "")))
2633 (set (subreg:DI (match_dup 4) 0)
2634 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
2635 (set (match_dup 0) (match_dup 4))]
2636 ""
2637 "
2638 { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
2639 << INTVAL (operands[2])));
2640 }")
2641
2642 ;; For the unaligned byte case, we use code similar to that in the
2643 ;; Architecture book, but reordered to lower the number of registers
2644 ;; required. Operand 0 is the address. Operand 1 is the data to store.
2645 ;; Operands 2, 3, and 4 are DImode temporaries, where the last two may
2646 ;; be the same temporary, if desired. If the address is in a register,
2647 ;; operand 2 can be that register.
2648
2649 (define_expand "unaligned_storeqi"
2650 [(set (match_operand:DI 3 "register_operand" "")
2651 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
2652 (const_int -8))))
2653 (set (match_operand:DI 2 "register_operand" "")
2654 (match_dup 0))
2655 (set (match_dup 3)
2656 (and:DI (ashift:DI (const_int 255)
2657 (ashift:DI (match_dup 2) (const_int 3)))
2658 (match_dup 3)))
2659 (set (match_operand:DI 4 "register_operand" "")
2660 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
2661 (ashift:DI (match_dup 2) (const_int 3))))
2662 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
2663 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
2664 (match_dup 4))]
2665 ""
2666 "")
2667
2668 ;; This is the code for storing into an unaligned short. It uses the same
2669 ;; trick as loading from an unaligned short. It needs lots of temporaries.
2670 ;; However, during reload, we only have two registers available. So we
2671 ;; repeat code so that only two temporaries are available. During RTL
2672 ;; generation, we can use different pseudos for each temporary and CSE
2673 ;; will remove the redundancies. During reload, we have to settle with
2674 ;; what we get. Luckily, unaligned accesses of this kind produced during
2675 ;; reload are quite rare.
2676 ;;
2677 ;; Operand 0 is the address of the memory location. Operand 1 contains the
2678 ;; data to store. The rest of the operands are all temporaries, with
2679 ;; various overlap possibilities during reload. See reload_outhi for
2680 ;; details of this use.
2681
2682 (define_expand "unaligned_storehi"
2683 [(set (match_operand:DI 2 "register_operand" "")
2684 (match_operand:DI 0 "address_operand" ""))
2685 (set (match_operand:DI 3 "register_operand" "")
2686 (and:DI (match_dup 2) (const_int -7)))
2687 (set (match_operand:DI 4 "register_operand" "")
2688 (mem:DI (match_dup 3)))
2689 (set (match_operand:DI 5 "register_operand" "")
2690 (and:DI (ashift:DI (const_int 65535)
2691 (ashift:DI (match_dup 2) (const_int 3)))
2692 (match_dup 4)))
2693 (set (match_operand:DI 6 "register_operand" "")
2694 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
2695 (ashift:DI (match_dup 2) (const_int 3))))
2696 (set (match_operand:DI 7 "register_operand" "")
2697 (ior:DI (match_dup 5) (match_dup 6)))
2698 (set (match_operand:DI 8 "register_operand" "") (match_dup 0))
2699 (set (match_operand:DI 9 "register_operand" "")
2700 (and:DI (match_dup 8) (const_int -7)))
2701 (set (mem:DI (match_dup 9)) (match_dup 7))]
2702 ""
2703 "")
2704 \f
2705 ;; Here are the define_expand's for QI and HI moves that use the above
2706 ;; patterns. We have the normal sets, plus the ones that need scratch
2707 ;; registers for reload.
2708
2709 (define_expand "movqi"
2710 [(set (match_operand:QI 0 "general_operand" "")
2711 (match_operand:QI 1 "general_operand" ""))]
2712 ""
2713 "
2714 { extern rtx get_unaligned_address ();
2715
2716 /* If the output is not a register, the input must be. */
2717 if (GET_CODE (operands[0]) == MEM)
2718 operands[1] = force_reg (QImode, operands[1]);
2719
2720 /* Handle four memory cases, unaligned and aligned for either the input
2721 or the output. The only case where we can be called during reload is
2722 for aligned loads; all other cases require temporaries. */
2723
2724 if (GET_CODE (operands[1]) == MEM
2725 || (GET_CODE (operands[1]) == SUBREG
2726 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
2727 || (reload_in_progress && GET_CODE (operands[1]) == REG
2728 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
2729 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
2730 && GET_CODE (SUBREG_REG (operands[1])) == REG
2731 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
2732 {
2733 if (aligned_memory_operand (operands[1], QImode))
2734 {
2735 rtx aligned_mem, bitnum;
2736 rtx scratch = (reload_in_progress
2737 ? gen_rtx (REG, SImode, REGNO (operands[0]))
2738 : gen_reg_rtx (SImode));
2739
2740 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
2741
2742 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
2743 scratch));
2744 }
2745 else
2746 {
2747 /* Don't pass these as parameters since that makes the generated
2748 code depend on parameter evaluation order which will cause
2749 bootstrap failures. */
2750
2751 rtx temp1 = gen_reg_rtx (DImode);
2752 rtx temp2 = gen_reg_rtx (DImode);
2753 rtx seq = gen_unaligned_loadqi (operands[0],
2754 get_unaligned_address (operands[1]),
2755 temp1, temp2);
2756
2757 alpha_set_memflags (seq, operands[1]);
2758 emit_insn (seq);
2759 }
2760
2761 DONE;
2762 }
2763
2764 else if (GET_CODE (operands[0]) == MEM
2765 || (GET_CODE (operands[0]) == SUBREG
2766 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
2767 || (reload_in_progress && GET_CODE (operands[0]) == REG
2768 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
2769 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
2770 && GET_CODE (SUBREG_REG (operands[0])) == REG
2771 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
2772 {
2773 if (aligned_memory_operand (operands[0], QImode))
2774 {
2775 rtx aligned_mem, bitnum;
2776 rtx temp1 = gen_reg_rtx (SImode);
2777 rtx temp2 = gen_reg_rtx (SImode);
2778
2779 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
2780
2781 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
2782 temp1, temp2));
2783 }
2784 else
2785 {
2786 rtx temp1 = gen_reg_rtx (DImode);
2787 rtx temp2 = gen_reg_rtx (DImode);
2788 rtx temp3 = gen_reg_rtx (DImode);
2789 rtx seq = gen_unaligned_storeqi (get_unaligned_address (operands[0]),
2790 operands[1], temp1, temp2, temp3);
2791
2792 alpha_set_memflags (seq, operands[0]);
2793 emit_insn (seq);
2794 }
2795 DONE;
2796 }
2797 }")
2798
2799 (define_expand "movhi"
2800 [(set (match_operand:HI 0 "general_operand" "")
2801 (match_operand:HI 1 "general_operand" ""))]
2802 ""
2803 "
2804 { extern rtx get_unaligned_address ();
2805
2806 /* If the output is not a register, the input must be. */
2807 if (GET_CODE (operands[0]) == MEM)
2808 operands[1] = force_reg (HImode, operands[1]);
2809
2810 /* Handle four memory cases, unaligned and aligned for either the input
2811 or the output. The only case where we can be called during reload is
2812 for aligned loads; all other cases require temporaries. */
2813
2814 if (GET_CODE (operands[1]) == MEM
2815 || (GET_CODE (operands[1]) == SUBREG
2816 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
2817 || (reload_in_progress && GET_CODE (operands[1]) == REG
2818 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
2819 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
2820 && GET_CODE (SUBREG_REG (operands[1])) == REG
2821 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
2822 {
2823 if (aligned_memory_operand (operands[1], HImode))
2824 {
2825 rtx aligned_mem, bitnum;
2826 rtx scratch = (reload_in_progress
2827 ? gen_rtx (REG, SImode, REGNO (operands[0]))
2828 : gen_reg_rtx (SImode));
2829
2830 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
2831
2832 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
2833 scratch));
2834 }
2835 else
2836 {
2837 rtx addr
2838 = force_reg (DImode,
2839 force_operand (get_unaligned_address (operands[1]),
2840 NULL_RTX));
2841 rtx scratch1 = gen_reg_rtx (DImode);
2842 rtx scratch2 = gen_reg_rtx (DImode);
2843 rtx seq = gen_unaligned_loadhi (operands[0], addr, scratch1,
2844 scratch2);
2845
2846 alpha_set_memflags (seq, operands[1]);
2847 emit_insn (seq);
2848 }
2849
2850 DONE;
2851 }
2852
2853 else if (GET_CODE (operands[0]) == MEM
2854 || (GET_CODE (operands[0]) == SUBREG
2855 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
2856 || (reload_in_progress && GET_CODE (operands[0]) == REG
2857 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
2858 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
2859 && GET_CODE (SUBREG_REG (operands[0])) == REG
2860 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
2861 {
2862 if (aligned_memory_operand (operands[0], HImode))
2863 {
2864 rtx aligned_mem, bitnum;
2865 rtx temp1 = gen_reg_rtx (SImode);
2866 rtx temp2 = gen_reg_rtx (SImode);
2867
2868 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
2869
2870 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
2871 temp1, temp2));
2872 }
2873 else
2874 {
2875 rtx temp1 = gen_reg_rtx (DImode);
2876 rtx temp2 = gen_reg_rtx (DImode);
2877 rtx temp3 = gen_reg_rtx (DImode);
2878 rtx temp4 = gen_reg_rtx (DImode);
2879 rtx temp5 = gen_reg_rtx (DImode);
2880 rtx temp6 = gen_reg_rtx (DImode);
2881 rtx temp7 = gen_reg_rtx (DImode);
2882 rtx temp8 = gen_reg_rtx (DImode);
2883 rtx seq = gen_unaligned_storehi (get_unaligned_address (operands[0]),
2884 operands[1], temp1, temp2,temp3,
2885 temp4, temp5, temp6,temp7, temp8);
2886
2887 alpha_set_memflags (seq, operands[0]);
2888 emit_insn (seq);
2889 }
2890
2891 DONE;
2892 }
2893 }")
2894
2895 ;; Here are the versions for reload. Note that in the unaligned cases
2896 ;; we know that the operand must not be a pseudo-register because stack
2897 ;; slots are always aligned references.
2898
2899 (define_expand "reload_inqi"
2900 [(parallel [(match_operand:QI 0 "register_operand" "=r")
2901 (match_operand:QI 1 "unaligned_memory_operand" "m")
2902 (match_operand:DI 2 "register_operand" "=&r")])]
2903 ""
2904 "
2905 { extern rtx get_unaligned_address ();
2906 rtx addr = get_unaligned_address (operands[1]);
2907 rtx seq = gen_unaligned_loadqi (operands[0], addr, operands[2],
2908 gen_rtx (REG, DImode, REGNO (operands[0])));
2909
2910 alpha_set_memflags (seq, operands[1]);
2911 emit_insn (seq);
2912 DONE;
2913 }")
2914
2915 (define_expand "reload_inhi"
2916 [(parallel [(match_operand:HI 0 "register_operand" "=r")
2917 (match_operand:HI 1 "unaligned_memory_operand" "m")
2918 (match_operand:TI 2 "register_operand" "=&r")])]
2919 ""
2920 "
2921 { extern rtx get_unaligned_address ();
2922 rtx addr = get_unaligned_address (operands[1]);
2923 rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2]));
2924 rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1);
2925 rtx seq;
2926
2927 if (GET_CODE (addr) != REG)
2928 {
2929 emit_insn (gen_rtx (SET, VOIDmode, scratch2, addr));
2930 addr = scratch2;
2931 }
2932
2933 seq = gen_unaligned_loadhi (operands[0], addr, scratch1, scratch1);
2934 alpha_set_memflags (seq, operands[1]);
2935 emit_insn (seq);
2936 DONE;
2937 }")
2938
2939 (define_expand "reload_outqi"
2940 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
2941 (match_operand:QI 1 "register_operand" "r")
2942 (match_operand:TI 2 "register_operand" "=&r")])]
2943 ""
2944 "
2945 { extern rtx get_unaligned_address ();
2946
2947 if (aligned_memory_operand (operands[0], QImode))
2948 {
2949 rtx aligned_mem, bitnum;
2950
2951 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
2952
2953 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
2954 gen_rtx (REG, SImode, REGNO (operands[2])),
2955 gen_rtx (REG, SImode,
2956 REGNO (operands[2]) + 1)));
2957 }
2958 else
2959 {
2960 rtx addr = get_unaligned_address (operands[0]);
2961 rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2]));
2962 rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1);
2963 rtx seq;
2964
2965 if (GET_CODE (addr) == REG)
2966 scratch1 = addr;
2967
2968 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
2969 scratch2, scratch2);
2970 alpha_set_memflags (seq, operands[0]);
2971 emit_insn (seq);
2972 }
2973
2974 DONE;
2975 }")
2976
2977 (define_expand "reload_outhi"
2978 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
2979 (match_operand:HI 1 "register_operand" "r")
2980 (match_operand:TI 2 "register_operand" "=&r")])]
2981 ""
2982 "
2983 { extern rtx get_unaligned_address ();
2984
2985 if (aligned_memory_operand (operands[0], HImode))
2986 {
2987 rtx aligned_mem, bitnum;
2988
2989 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
2990
2991 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
2992 gen_rtx (REG, SImode, REGNO (operands[2])),
2993 gen_rtx (REG, SImode,
2994 REGNO (operands[2]) + 1)));
2995 }
2996 else
2997 {
2998 rtx addr = get_unaligned_address (operands[0]);
2999 rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2]));
3000 rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1);
3001 rtx scratch_a = GET_CODE (addr) == REG ? addr : scratch1;
3002 rtx seq;
3003
3004 seq = gen_unaligned_storehi (addr, operands[1], scratch_a,
3005 scratch2, scratch2, scratch2,
3006 scratch1, scratch2, scratch_a,
3007 scratch1);
3008 alpha_set_memflags (seq, operands[0]);
3009 emit_insn (seq);
3010 }
3011
3012 DONE;
3013 }")
3014
3015 ;;- Local variables:
3016 ;;- mode:emacs-lisp
3017 ;;- comment-start: ";;- "
3018 ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
3019 ;;- eval: (modify-syntax-entry ?[ "(]")
3020 ;;- eval: (modify-syntax-entry ?] ")[")
3021 ;;- eval: (modify-syntax-entry ?{ "(}")
3022 ;;- eval: (modify-syntax-entry ?} "){")
3023 ;;- End:
GNU Compiler Collection
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