1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C)
1992,
93,
94,
95,
96,
97,
1998 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version
2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation,
59 Temple Place - Suite
330,
20 ;; Boston, MA
02111-
1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24 ;; Uses of UNSPEC in this file:
37 ;;
2 builtin_setjmp_receiver
40 ;;
5 prologue_stack_probe_loop
42 ;; Processor type -- this attribute must exactly match the processor_type
43 ;; enumeration in alpha.h.
45 (define_attr "cpu" "ev4,ev5,ev6"
46 (const (symbol_ref "alpha_cpu")))
48 ;; Define an insn type attribute. This is used in function unit delay
49 ;; computations, among other purposes. For the most part, we use the names
50 ;; defined in the EV4 documentation, but add a few that we have to know about
54 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof"
55 (const_string "iadd"))
57 ;; Define the operand size an insn operates on. Used primarily by mul
58 ;; and div operations that have size dependant timings.
60 (define_attr "opsize" "si,di,udi" (const_string "di"))
62 ;; The TRAP_TYPE attribute marks instructions that may generate traps
63 ;; (which are imprecise and may need a trapb if software completion
66 (define_attr "trap" "no,yes" (const_string "no"))
68 ;; The length of an instruction sequence in bytes.
70 (define_attr "length" "" (const_int
4))
72 ;; On EV4 there are two classes of resources to consider: resources needed
73 ;; to issue, and resources needed to execute. IBUS[
01] are in the first
74 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
75 ;; (There are a few other register-like resources, but ...)
77 ; First, describe all of the issue constraints with single cycle delays.
78 ; All insns need a bus, but all except loads require one or the other.
79 (define_function_unit "ev4_ibus0"
1 0
80 (and (eq_attr "cpu" "ev4")
81 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
84 (define_function_unit "ev4_ibus1"
1 0
85 (and (eq_attr "cpu" "ev4")
86 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
89 ; Memory delivers its result in three cycles. Actually return one and
90 ; take care of this in adjust_cost, since we want to handle user-defined
92 (define_function_unit "ev4_abox"
1 0
93 (and (eq_attr "cpu" "ev4")
94 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
97 ; Branches have no delay cost, but do tie up the unit for two cycles.
98 (define_function_unit "ev4_bbox"
1 1
99 (and (eq_attr "cpu" "ev4")
100 (eq_attr "type" "ibr,fbr,jsr"))
103 ; Arithmetic insns are normally have their results available after
104 ; two cycles. There are a number of exceptions. They are encoded in
105 ; ADJUST_COST. Some of the other insns have similar exceptions.
106 (define_function_unit "ev4_ebox"
1 0
107 (and (eq_attr "cpu" "ev4")
108 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
111 (define_function_unit "imul"
1 0
112 (and (eq_attr "cpu" "ev4")
113 (and (eq_attr "type" "imul")
114 (eq_attr "opsize" "si")))
117 (define_function_unit "imul"
1 0
118 (and (eq_attr "cpu" "ev4")
119 (and (eq_attr "type" "imul")
120 (eq_attr "opsize" "!si")))
123 (define_function_unit "ev4_fbox"
1 0
124 (and (eq_attr "cpu" "ev4")
125 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
128 (define_function_unit "fdiv"
1 0
129 (and (eq_attr "cpu" "ev4")
130 (and (eq_attr "type" "fdiv")
131 (eq_attr "opsize" "si")))
134 (define_function_unit "fdiv"
1 0
135 (and (eq_attr "cpu" "ev4")
136 (and (eq_attr "type" "fdiv")
137 (eq_attr "opsize" "di")))
140 ;; EV5 scheduling. EV5 can issue
4 insns per clock.
142 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
143 ;; with the combined resource EBOX.
145 (define_function_unit "ev5_ebox"
2 0
146 (and (eq_attr "cpu" "ev5")
147 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
150 ; Memory takes at least
2 clocks. Return one from here and fix up with
151 ; user-defined latencies in adjust_cost.
152 ; ??? How to: "An instruction of class LD cannot be issued in the _second_
153 ; cycle after an instruction of class ST is issued."
154 (define_function_unit "ev5_ebox"
2 0
155 (and (eq_attr "cpu" "ev5")
156 (eq_attr "type" "ild,fld,ldsym"))
159 ; Stores, shifts, multiplies can only issue to E0
160 (define_function_unit "ev5_e0"
1 0
161 (and (eq_attr "cpu" "ev5")
162 (eq_attr "type" "ist,fst,shift,imul"))
165 ; Motion video insns also issue only to E0, and take two ticks.
166 (define_function_unit "ev5_e0"
1 0
167 (and (eq_attr "cpu" "ev5")
168 (eq_attr "type" "mvi"))
171 ; Conditional moves always take
2 ticks.
172 (define_function_unit "ev5_ebox"
2 0
173 (and (eq_attr "cpu" "ev5")
174 (eq_attr "type" "icmov"))
177 ; Branches can only issue to E1
178 (define_function_unit "ev5_e1"
1 0
179 (and (eq_attr "cpu" "ev5")
180 (eq_attr "type" "ibr,jsr"))
183 ; Multiplies also use the integer multiplier.
184 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
185 ; cycles before an integer multiplication completes."
186 (define_function_unit "imul"
1 0
187 (and (eq_attr "cpu" "ev5")
188 (and (eq_attr "type" "imul")
189 (eq_attr "opsize" "si")))
192 (define_function_unit "imul"
1 0
193 (and (eq_attr "cpu" "ev5")
194 (and (eq_attr "type" "imul")
195 (eq_attr "opsize" "di")))
198 (define_function_unit "imul"
1 0
199 (and (eq_attr "cpu" "ev5")
200 (and (eq_attr "type" "imul")
201 (eq_attr "opsize" "udi")))
204 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
205 ;; on either so we have to play the game again.
207 (define_function_unit "ev5_fbox"
2 0
208 (and (eq_attr "cpu" "ev5")
209 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
212 (define_function_unit "ev5_fm"
1 0
213 (and (eq_attr "cpu" "ev5")
214 (eq_attr "type" "fmul"))
217 ; Add and cmov as you would expect; fbr never produces a result;
218 ; fdiv issues through fa to the divider,
219 (define_function_unit "ev5_fa"
1 0
220 (and (eq_attr "cpu" "ev5")
221 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
224 ; ??? How to: "No instruction can be issued to pipe FA exactly five
225 ; cycles before a floating point divide completes."
226 (define_function_unit "fdiv"
1 0
227 (and (eq_attr "cpu" "ev5")
228 (and (eq_attr "type" "fdiv")
229 (eq_attr "opsize" "si")))
230 15 15) ;
15 to
31 data dependant
232 (define_function_unit "fdiv"
1 0
233 (and (eq_attr "cpu" "ev5")
234 (and (eq_attr "type" "fdiv")
235 (eq_attr "opsize" "di")))
236 22 22) ;
22 to
60 data dependant
238 ;; EV6 scheduling. EV6 can issue
4 insns per clock.
240 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
241 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
243 ;; Conditional moves decompose into two independant primitives, each
244 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
246 (define_function_unit "ev6_ebox"
4 0
247 (and (eq_attr "cpu" "ev6")
248 (eq_attr "type" "icmov"))
251 (define_function_unit "ev6_ebox"
4 0
252 (and (eq_attr "cpu" "ev6")
253 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
256 ;; Integer loads take at least
3 clocks, and only issue to lower units.
257 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
258 (define_function_unit "ev6_l"
2 0
259 (and (eq_attr "cpu" "ev6")
260 (eq_attr "type" "ild,ldsym,ist,fst"))
263 ;; FP loads take at least
4 clocks. Return two from here...
264 (define_function_unit "ev6_l"
2 0
265 (and (eq_attr "cpu" "ev6")
266 (eq_attr "type" "fld"))
269 ;; Motion video insns also issue only to U0, and take three ticks.
270 (define_function_unit "ev6_u0"
1 0
271 (and (eq_attr "cpu" "ev6")
272 (eq_attr "type" "mvi"))
275 (define_function_unit "ev6_u"
2 0
276 (and (eq_attr "cpu" "ev6")
277 (eq_attr "type" "mvi"))
280 ;; Shifts issue to either upper pipe.
281 (define_function_unit "ev6_u"
2 0
282 (and (eq_attr "cpu" "ev6")
283 (eq_attr "type" "shift"))
286 ;; Multiplies issue only to U1, and all take
7 ticks.
287 ;; Rather than create a new function unit just for U1, reuse IMUL
288 (define_function_unit "imul"
1 0
289 (and (eq_attr "cpu" "ev6")
290 (eq_attr "type" "imul"))
293 (define_function_unit "ev6_u"
2 0
294 (and (eq_attr "cpu" "ev6")
295 (eq_attr "type" "imul"))
298 ;; Branches issue to either upper pipe
299 (define_function_unit "ev6_u"
2 0
300 (and (eq_attr "cpu" "ev6")
301 (eq_attr "type" "ibr"))
304 ;; Calls only issue to L0.
305 (define_function_unit "ev6_l0"
1 0
306 (and (eq_attr "cpu" "ev6")
307 (eq_attr "type" "jsr"))
310 (define_function_unit "ev6_l"
2 0
311 (and (eq_attr "cpu" "ev6")
312 (eq_attr "type" "jsr"))
315 ;; Ftoi/itof only issue to lower pipes
316 (define_function_unit "ev6_l"
2 0
317 (and (eq_attr "cpu" "ev6")
318 (eq_attr "type" "ftoi"))
321 (define_function_unit "ev6_l"
2 0
322 (and (eq_attr "cpu" "ev6")
323 (eq_attr "type" "itof"))
326 ;; For the FPU we are very similar to EV5, except there's no insn that
327 ;; can issue to fm & fa, so we get to leave that out.
329 (define_function_unit "ev6_fm"
1 0
330 (and (eq_attr "cpu" "ev6")
331 (eq_attr "type" "fmul"))
334 (define_function_unit "ev6_fa"
1 0
335 (and (eq_attr "cpu" "ev6")
336 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
339 (define_function_unit "ev6_fa"
1 0
340 (and (eq_attr "cpu" "ev6")
341 (eq_attr "type" "fcmov"))
344 (define_function_unit "fdiv"
1 0
345 (and (eq_attr "cpu" "ev6")
346 (and (eq_attr "type" "fdiv")
347 (eq_attr "opsize" "si")))
350 (define_function_unit "fdiv"
1 0
351 (and (eq_attr "cpu" "ev6")
352 (and (eq_attr "type" "fdiv")
353 (eq_attr "opsize" "di")))
356 (define_function_unit "fsqrt"
1 0
357 (and (eq_attr "cpu" "ev6")
358 (and (eq_attr "type" "fsqrt")
359 (eq_attr "opsize" "si")))
362 (define_function_unit "fsqrt"
1 0
363 (and (eq_attr "cpu" "ev6")
364 (and (eq_attr "type" "fsqrt")
365 (eq_attr "opsize" "di")))
368 ; ??? The FPU communicates with memory and the integer register file
369 ; via two fp store units. We need a slot in the fst immediately, and
370 ; a slot in LOW after the operand data is ready. At which point the
371 ; data may be moved either to the store queue or the integer register
372 ; file and the insn retired.
375 ;; First define the arithmetic insns. Note that the
32-bit forms also
378 ;; Handle
32-
64 bit extension from memory to a floating point register
379 ;; specially, since this ocurrs frequently in int->double conversions.
380 ;; This is done with a define_split after reload converting the plain
381 ;; sign-extension into a load+unspec, which of course results in lds+cvtlq.
383 ;; Note that while we must retain the =f case in the insn for reload's
384 ;; benefit, it should be eliminated after reload, so we should never emit
385 ;; code for that case. But we don't reject the possibility.
387 (define_insn "extendsidi2"
388 [(set (match_operand:DI
0 "register_operand" "=r,r,?f")
389 (sign_extend:DI (match_operand:SI
1 "nonimmediate_operand" "r,m,m")))]
394 lds %
0,%
1\;cvtlq %
0,%
0"
395 [(set_attr "type" "iadd,ild,fld")
396 (set_attr "length" "*,*,
8")])
398 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
400 [(set (match_operand:DI
0 "hard_fp_register_operand" "")
401 (sign_extend:DI (match_operand:SI
1 "memory_operand" "")))]
403 [(set (match_dup
2) (match_dup
1))
404 (set (match_dup
0) (unspec:DI [(match_dup
2)]
4))]
405 "operands[
2] = gen_rtx_REG (SImode, REGNO (operands[
0]));")
408 [(set (match_operand:DI
0 "register_operand" "=f")
409 (unspec:DI [(match_operand:SI
1 "register_operand" "f")]
4))]
412 [(set_attr "type" "fadd")])
414 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
415 ;; generates better code. We have the anonymous addsi3 pattern below in
416 ;; case combine wants to make it.
417 (define_expand "addsi3"
418 [(set (match_operand:SI
0 "register_operand" "")
419 (plus:SI (match_operand:SI
1 "reg_or_0_operand" "")
420 (match_operand:SI
2 "add_operand" "")))]
423 { emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (DImode, operands[
0]),
424 gen_rtx_PLUS (DImode,
425 gen_lowpart (DImode, operands[
1]),
426 gen_lowpart (DImode, operands[
2]))));
431 [(set (match_operand:SI
0 "register_operand" "=r,r,r,r")
432 (plus:SI (match_operand:SI
1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
433 (match_operand:SI
2 "add_operand" "rI,O,K,L")))]
442 [(set (match_operand:SI
0 "register_operand" "")
443 (plus:SI (match_operand:SI
1 "register_operand" "")
444 (match_operand:SI
2 "const_int_operand" "")))]
445 "! add_operand (operands[
2], SImode)"
446 [(set (match_dup
0) (plus:SI (match_dup
1) (match_dup
3)))
447 (set (match_dup
0) (plus:SI (match_dup
0) (match_dup
4)))]
450 HOST_WIDE_INT val = INTVAL (operands[
2]);
451 HOST_WIDE_INT low = (val &
0xffff) -
2 * (val &
0x8000);
452 HOST_WIDE_INT rest = val - low;
454 operands[
3] = GEN_INT (rest);
455 operands[
4] = GEN_INT (low);
459 [(set (match_operand:DI
0 "register_operand" "=r,r")
461 (plus:SI (match_operand:SI
1 "reg_or_0_operand" "%rJ,rJ")
462 (match_operand:SI
2 "sext_add_operand" "rI,O"))))]
469 [(set (match_operand:DI
0 "register_operand" "")
471 (plus:SI (match_operand:SI
1 "register_operand" "")
472 (match_operand:SI
2 "const_int_operand" ""))))
473 (clobber (match_operand:SI
3 "register_operand" ""))]
474 "! sext_add_operand (operands[
2], SImode) && INTVAL (operands[
2]) >
0
475 && INTVAL (operands[
2]) %
4 ==
0"
476 [(set (match_dup
3) (match_dup
4))
477 (set (match_dup
0) (sign_extend:DI (plus:SI (mult:SI (match_dup
3)
482 HOST_WIDE_INT val = INTVAL (operands[
2]) /
4;
488 operands[
4] = GEN_INT (val);
489 operands[
5] = GEN_INT (mult);
493 [(set (match_operand:DI
0 "register_operand" "")
495 (plus:SI (match_operator:SI
1 "comparison_operator"
496 [(match_operand
2 "" "")
497 (match_operand
3 "" "")])
498 (match_operand:SI
4 "add_operand" ""))))
499 (clobber (match_operand:DI
5 "register_operand" ""))]
501 [(set (match_dup
5) (match_dup
6))
502 (set (match_dup
0) (sign_extend:DI (plus:SI (match_dup
7) (match_dup
4))))]
505 operands[
6] = gen_rtx_fmt_ee (GET_CODE (operands[
1]), DImode,
506 operands[
2], operands[
3]);
507 operands[
7] = gen_lowpart (SImode, operands[
5]);
510 (define_insn "adddi3"
511 [(set (match_operand:DI
0 "register_operand" "=r,r,r,r")
512 (plus:DI (match_operand:DI
1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
513 (match_operand:DI
2 "add_operand" "rI,O,K,L")))]
521 ;; Don't do this if we are adjusting SP since we don't want to do
524 [(set (match_operand:DI
0 "register_operand" "")
525 (plus:DI (match_operand:DI
1 "register_operand" "")
526 (match_operand:DI
2 "const_int_operand" "")))]
527 "! add_operand (operands[
2], DImode)
528 && REGNO (operands[
0]) != STACK_POINTER_REGNUM"
529 [(set (match_dup
0) (plus:DI (match_dup
1) (match_dup
3)))
530 (set (match_dup
0) (plus:DI (match_dup
0) (match_dup
4)))]
533 HOST_WIDE_INT val = INTVAL (operands[
2]);
534 HOST_WIDE_INT low = (val &
0xffff) -
2 * (val &
0x8000);
535 HOST_WIDE_INT rest = val - low;
537 operands[
3] = GEN_INT (rest);
538 operands[
4] = GEN_INT (low);
542 [(set (match_operand:SI
0 "register_operand" "=r,r")
543 (plus:SI (mult:SI (match_operand:SI
1 "reg_or_0_operand" "rJ,rJ")
544 (match_operand:SI
2 "const48_operand" "I,I"))
545 (match_operand:SI
3 "sext_add_operand" "rI,O")))]
552 [(set (match_operand:DI
0 "register_operand" "=r,r")
554 (plus:SI (mult:SI (match_operand:SI
1 "reg_or_0_operand" "rJ,rJ")
555 (match_operand:SI
2 "const48_operand" "I,I"))
556 (match_operand:SI
3 "sext_add_operand" "rI,O"))))]
563 [(set (match_operand:DI
0 "register_operand" "")
565 (plus:SI (mult:SI (match_operator:SI
1 "comparison_operator"
566 [(match_operand
2 "" "")
567 (match_operand
3 "" "")])
568 (match_operand:SI
4 "const48_operand" ""))
569 (match_operand:SI
5 "add_operand" ""))))
570 (clobber (match_operand:DI
6 "register_operand" ""))]
572 [(set (match_dup
6) (match_dup
7))
574 (sign_extend:DI (plus:SI (mult:SI (match_dup
8) (match_dup
4))
578 operands[
7] = gen_rtx_fmt_ee (GET_CODE (operands[
1]), DImode,
579 operands[
2], operands[
3]);
580 operands[
8] = gen_lowpart (SImode, operands[
6]);
584 [(set (match_operand:DI
0 "register_operand" "=r,r")
585 (plus:DI (mult:DI (match_operand:DI
1 "reg_or_0_operand" "rJ,rJ")
586 (match_operand:DI
2 "const48_operand" "I,I"))
587 (match_operand:DI
3 "reg_or_8bit_operand" "rI,O")))]
593 ;; These variants of the above insns can occur if the third operand
594 ;; is the frame pointer. This is a kludge, but there doesn't
595 ;; seem to be a way around it. Only recognize them while reloading.
598 [(set (match_operand:DI
0 "some_operand" "=&r")
599 (plus:DI (plus:DI (match_operand:DI
1 "some_operand" "r")
600 (match_operand:DI
2 "some_operand" "r"))
601 (match_operand:DI
3 "some_operand" "rIOKL")))]
606 [(set (match_operand:DI
0 "register_operand" "")
607 (plus:DI (plus:DI (match_operand:DI
1 "register_operand" "")
608 (match_operand:DI
2 "register_operand" ""))
609 (match_operand:DI
3 "add_operand" "")))]
611 [(set (match_dup
0) (plus:DI (match_dup
1) (match_dup
2)))
612 (set (match_dup
0) (plus:DI (match_dup
0) (match_dup
3)))]
616 [(set (match_operand:SI
0 "some_operand" "=&r")
617 (plus:SI (plus:SI (mult:SI (match_operand:SI
1 "some_operand" "rJ")
618 (match_operand:SI
2 "const48_operand" "I"))
619 (match_operand:SI
3 "some_operand" "r"))
620 (match_operand:SI
4 "some_operand" "rIOKL")))]
625 [(set (match_operand:SI
0 "register_operand" "r")
626 (plus:SI (plus:SI (mult:SI (match_operand:SI
1 "reg_or_0_operand" "")
627 (match_operand:SI
2 "const48_operand" ""))
628 (match_operand:SI
3 "register_operand" ""))
629 (match_operand:SI
4 "add_operand" "rIOKL")))]
632 (plus:SI (mult:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
633 (set (match_dup
0) (plus:SI (match_dup
0) (match_dup
4)))]
637 [(set (match_operand:DI
0 "some_operand" "=&r")
640 (mult:SI (match_operand:SI
1 "some_operand" "rJ")
641 (match_operand:SI
2 "const48_operand" "I"))
642 (match_operand:SI
3 "some_operand" "r"))
643 (match_operand:SI
4 "some_operand" "rIOKL"))))]
648 [(set (match_operand:DI
0 "register_operand" "")
651 (mult:SI (match_operand:SI
1 "reg_or_0_operand" "")
652 (match_operand:SI
2 "const48_operand" ""))
653 (match_operand:SI
3 "register_operand" ""))
654 (match_operand:SI
4 "add_operand" ""))))]
657 (plus:SI (mult:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
658 (set (match_dup
0) (sign_extend:DI (plus:SI (match_dup
5) (match_dup
4))))]
660 { operands[
5] = gen_lowpart (SImode, operands[
0]);
664 [(set (match_operand:DI
0 "some_operand" "=&r")
665 (plus:DI (plus:DI (mult:DI (match_operand:DI
1 "some_operand" "rJ")
666 (match_operand:DI
2 "const48_operand" "I"))
667 (match_operand:DI
3 "some_operand" "r"))
668 (match_operand:DI
4 "some_operand" "rIOKL")))]
673 [(set (match_operand:DI
0 "register_operand" "=")
674 (plus:DI (plus:DI (mult:DI (match_operand:DI
1 "reg_or_0_operand" "")
675 (match_operand:DI
2 "const48_operand" ""))
676 (match_operand:DI
3 "register_operand" ""))
677 (match_operand:DI
4 "add_operand" "")))]
680 (plus:DI (mult:DI (match_dup
1) (match_dup
2)) (match_dup
3)))
681 (set (match_dup
0) (plus:DI (match_dup
0) (match_dup
4)))]
684 (define_insn "negsi2"
685 [(set (match_operand:SI
0 "register_operand" "=r")
686 (neg:SI (match_operand:SI
1 "reg_or_8bit_operand" "rI")))]
691 [(set (match_operand:DI
0 "register_operand" "=r")
692 (sign_extend:DI (neg:SI
693 (match_operand:SI
1 "reg_or_8bit_operand" "rI"))))]
697 (define_insn "negdi2"
698 [(set (match_operand:DI
0 "register_operand" "=r")
699 (neg:DI (match_operand:DI
1 "reg_or_8bit_operand" "rI")))]
703 (define_expand "subsi3"
704 [(set (match_operand:SI
0 "register_operand" "")
705 (minus:SI (match_operand:SI
1 "reg_or_0_operand" "")
706 (match_operand:SI
2 "reg_or_8bit_operand" "")))]
709 { emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (DImode, operands[
0]),
710 gen_rtx_MINUS (DImode,
711 gen_lowpart (DImode, operands[
1]),
712 gen_lowpart (DImode, operands[
2]))));
717 [(set (match_operand:SI
0 "register_operand" "=r")
718 (minus:SI (match_operand:SI
1 "reg_or_0_operand" "rJ")
719 (match_operand:SI
2 "reg_or_8bit_operand" "rI")))]
724 [(set (match_operand:DI
0 "register_operand" "=r")
725 (sign_extend:DI (minus:SI (match_operand:SI
1 "reg_or_0_operand" "rJ")
726 (match_operand:SI
2 "reg_or_8bit_operand" "rI"))))]
730 (define_insn "subdi3"
731 [(set (match_operand:DI
0 "register_operand" "=r")
732 (minus:DI (match_operand:DI
1 "reg_or_0_operand" "rJ")
733 (match_operand:DI
2 "reg_or_8bit_operand" "rI")))]
738 [(set (match_operand:SI
0 "register_operand" "=r")
739 (minus:SI (mult:SI (match_operand:SI
1 "reg_or_0_operand" "rJ")
740 (match_operand:SI
2 "const48_operand" "I"))
741 (match_operand:SI
3 "reg_or_8bit_operand" "rI")))]
746 [(set (match_operand:DI
0 "register_operand" "=r")
748 (minus:SI (mult:SI (match_operand:SI
1 "reg_or_0_operand" "rJ")
749 (match_operand:SI
2 "const48_operand" "I"))
750 (match_operand:SI
3 "reg_or_8bit_operand" "rI"))))]
755 [(set (match_operand:DI
0 "register_operand" "=r")
756 (minus:DI (mult:DI (match_operand:DI
1 "reg_or_0_operand" "rJ")
757 (match_operand:DI
2 "const48_operand" "I"))
758 (match_operand:DI
3 "reg_or_8bit_operand" "rI")))]
762 (define_insn "mulsi3"
763 [(set (match_operand:SI
0 "register_operand" "=r")
764 (mult:SI (match_operand:SI
1 "reg_or_0_operand" "%rJ")
765 (match_operand:SI
2 "reg_or_0_operand" "rJ")))]
768 [(set_attr "type" "imul")
769 (set_attr "opsize" "si")])
772 [(set (match_operand:DI
0 "register_operand" "=r")
773 (sign_extend:DI (mult:SI (match_operand:SI
1 "reg_or_0_operand" "%rJ")
774 (match_operand:SI
2 "reg_or_0_operand" "rJ"))))]
777 [(set_attr "type" "imul")
778 (set_attr "opsize" "si")])
780 (define_insn "muldi3"
781 [(set (match_operand:DI
0 "register_operand" "=r")
782 (mult:DI (match_operand:DI
1 "reg_or_0_operand" "%rJ")
783 (match_operand:DI
2 "reg_or_0_operand" "rJ")))]
786 [(set_attr "type" "imul")])
788 (define_insn "umuldi3_highpart"
789 [(set (match_operand:DI
0 "register_operand" "=r")
792 (mult:TI (zero_extend:TI (match_operand:DI
1 "register_operand" "r"))
793 (zero_extend:TI (match_operand:DI
2 "register_operand" "r")))
797 [(set_attr "type" "imul")
798 (set_attr "opsize" "udi")])
801 [(set (match_operand:DI
0 "register_operand" "=r")
804 (mult:TI (zero_extend:TI (match_operand:DI
1 "register_operand" "r"))
805 (match_operand:TI
2 "cint8_operand" "I"))
809 [(set_attr "type" "imul")
810 (set_attr "opsize" "udi")])
812 ;; The divide and remainder operations always take their inputs from
813 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
815 ;; ??? Force sign-extension here because some versions of OSF/
1 don't
816 ;; do the right thing if the inputs are not properly sign-extended.
817 ;; But Linux, for instance, does not have this problem. Is it worth
818 ;; the complication here to eliminate the sign extension?
820 (define_expand "divsi3"
822 (sign_extend:DI (match_operand:SI
1 "nonimmediate_operand" "")))
824 (sign_extend:DI (match_operand:SI
2 "nonimmediate_operand" "")))
825 (parallel [(set (reg:DI
27)
826 (sign_extend:DI (div:SI (reg:DI
24) (reg:DI
25))))
827 (clobber (reg:DI
23))
828 (clobber (reg:DI
28))])
829 (set (match_operand:SI
0 "general_operand" "")
830 (subreg:SI (reg:DI
27)
0))]
834 (define_expand "udivsi3"
836 (sign_extend:DI (match_operand:SI
1 "nonimmediate_operand" "")))
838 (sign_extend:DI (match_operand:SI
2 "nonimmediate_operand" "")))
839 (parallel [(set (reg:DI
27)
840 (sign_extend:DI (udiv:SI (reg:DI
24) (reg:DI
25))))
841 (clobber (reg:DI
23))
842 (clobber (reg:DI
28))])
843 (set (match_operand:SI
0 "general_operand" "")
844 (subreg:SI (reg:DI
27)
0))]
848 (define_expand "modsi3"
850 (sign_extend:DI (match_operand:SI
1 "nonimmediate_operand" "")))
852 (sign_extend:DI (match_operand:SI
2 "nonimmediate_operand" "")))
853 (parallel [(set (reg:DI
27)
854 (sign_extend:DI (mod:SI (reg:DI
24) (reg:DI
25))))
855 (clobber (reg:DI
23))
856 (clobber (reg:DI
28))])
857 (set (match_operand:SI
0 "general_operand" "")
858 (subreg:SI (reg:DI
27)
0))]
862 (define_expand "umodsi3"
864 (sign_extend:DI (match_operand:SI
1 "nonimmediate_operand" "")))
866 (sign_extend:DI (match_operand:SI
2 "nonimmediate_operand" "")))
867 (parallel [(set (reg:DI
27)
868 (sign_extend:DI (umod:SI (reg:DI
24) (reg:DI
25))))
869 (clobber (reg:DI
23))
870 (clobber (reg:DI
28))])
871 (set (match_operand:SI
0 "general_operand" "")
872 (subreg:SI (reg:DI
27)
0))]
876 (define_expand "divdi3"
877 [(set (reg:DI
24) (match_operand:DI
1 "input_operand" ""))
878 (set (reg:DI
25) (match_operand:DI
2 "input_operand" ""))
879 (parallel [(set (reg:DI
27)
882 (clobber (reg:DI
23))
883 (clobber (reg:DI
28))])
884 (set (match_operand:DI
0 "general_operand" "")
889 (define_expand "udivdi3"
890 [(set (reg:DI
24) (match_operand:DI
1 "input_operand" ""))
891 (set (reg:DI
25) (match_operand:DI
2 "input_operand" ""))
892 (parallel [(set (reg:DI
27)
895 (clobber (reg:DI
23))
896 (clobber (reg:DI
28))])
897 (set (match_operand:DI
0 "general_operand" "")
902 (define_expand "moddi3"
903 [(set (reg:DI
24) (match_operand:DI
1 "input_operand" ""))
904 (set (reg:DI
25) (match_operand:DI
2 "input_operand" ""))
905 (parallel [(set (reg:DI
27)
908 (clobber (reg:DI
23))
909 (clobber (reg:DI
28))])
910 (set (match_operand:DI
0 "general_operand" "")
915 (define_expand "umoddi3"
916 [(set (reg:DI
24) (match_operand:DI
1 "input_operand" ""))
917 (set (reg:DI
25) (match_operand:DI
2 "input_operand" ""))
918 (parallel [(set (reg:DI
27)
921 (clobber (reg:DI
23))
922 (clobber (reg:DI
28))])
923 (set (match_operand:DI
0 "general_operand" "")
928 ;; Lengths of
8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
929 ;; expanded by the assembler.
932 (sign_extend:DI (match_operator:SI
1 "divmod_operator"
933 [(reg:DI
24) (reg:DI
25)])))
934 (clobber (reg:DI
23))
935 (clobber (reg:DI
28))]
938 [(set_attr "type" "jsr")
939 (set_attr "length" "
8")])
943 (match_operator:DI
1 "divmod_operator"
944 [(reg:DI
24) (reg:DI
25)]))
945 (clobber (reg:DI
23))
946 (clobber (reg:DI
28))]
949 [(set_attr "type" "jsr")
950 (set_attr "length" "
8")])
952 ;; Next are the basic logical operations. These only exist in DImode.
954 (define_insn "anddi3"
955 [(set (match_operand:DI
0 "register_operand" "=r,r,r")
956 (and:DI (match_operand:DI
1 "reg_or_0_operand" "%rJ,rJ,rJ")
957 (match_operand:DI
2 "and_operand" "rI,N,MH")))]
963 [(set_attr "type" "ilog,ilog,shift")])
965 ;; There are times when we can split an AND into two AND insns. This occurs
966 ;; when we can first clear any bytes and then clear anything else. For
967 ;; example "I &
0xffff07" is "(I &
0xffffff) &
0xffffffffffffff07".
968 ;; Only do this when running on
64-bit host since the computations are
969 ;; too messy otherwise.
972 [(set (match_operand:DI
0 "register_operand" "")
973 (and:DI (match_operand:DI
1 "register_operand" "")
974 (match_operand:DI
2 "const_int_operand" "")))]
975 "HOST_BITS_PER_WIDE_INT ==
64 && ! and_operand (operands[
2], DImode)"
976 [(set (match_dup
0) (and:DI (match_dup
1) (match_dup
3)))
977 (set (match_dup
0) (and:DI (match_dup
0) (match_dup
4)))]
980 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[
2]);
981 unsigned HOST_WIDE_INT mask2 = mask1;
984 /* For each byte that isn't all zeros, make it all ones. */
985 for (i =
0; i <
64; i +=
8)
986 if ((mask1 & ((HOST_WIDE_INT)
0xff << i)) !=
0)
987 mask1 |= (HOST_WIDE_INT)
0xff << i;
989 /* Now turn on any bits we've just turned off. */
992 operands[
3] = GEN_INT (mask1);
993 operands[
4] = GEN_INT (mask2);
996 (define_insn "zero_extendqihi2"
997 [(set (match_operand:HI
0 "register_operand" "=r")
998 (zero_extend:HI (match_operand:QI
1 "register_operand" "r")))]
1001 [(set_attr "type" "ilog")])
1004 [(set (match_operand:SI
0 "register_operand" "=r,r")
1005 (zero_extend:SI (match_operand:QI
1 "nonimmediate_operand" "r,m")))]
1010 [(set_attr "type" "ilog,ild")])
1013 [(set (match_operand:SI
0 "register_operand" "=r")
1014 (zero_extend:SI (match_operand:QI
1 "register_operand" "r")))]
1017 [(set_attr "type" "ilog")])
1019 (define_expand "zero_extendqisi2"
1020 [(set (match_operand:SI
0 "register_operand" "")
1021 (zero_extend:SI (match_operand:QI
1 "register_operand" "")))]
1026 [(set (match_operand:DI
0 "register_operand" "=r,r")
1027 (zero_extend:DI (match_operand:QI
1 "nonimmediate_operand" "r,m")))]
1032 [(set_attr "type" "ilog,ild")])
1035 [(set (match_operand:DI
0 "register_operand" "=r")
1036 (zero_extend:DI (match_operand:QI
1 "register_operand" "r")))]
1039 [(set_attr "type" "ilog")])
1041 (define_expand "zero_extendqidi2"
1042 [(set (match_operand:DI
0 "register_operand" "")
1043 (zero_extend:DI (match_operand:QI
1 "register_operand" "")))]
1048 [(set (match_operand:SI
0 "register_operand" "=r,r")
1049 (zero_extend:SI (match_operand:HI
1 "nonimmediate_operand" "r,m")))]
1054 [(set_attr "type" "shift,ild")])
1057 [(set (match_operand:SI
0 "register_operand" "=r")
1058 (zero_extend:SI (match_operand:HI
1 "register_operand" "r")))]
1061 [(set_attr "type" "shift")])
1063 (define_expand "zero_extendhisi2"
1064 [(set (match_operand:SI
0 "register_operand" "")
1065 (zero_extend:SI (match_operand:HI
1 "register_operand" "")))]
1070 [(set (match_operand:DI
0 "register_operand" "=r,r")
1071 (zero_extend:DI (match_operand:HI
1 "nonimmediate_operand" "r,m")))]
1076 [(set_attr "type" "shift,ild")])
1079 [(set (match_operand:DI
0 "register_operand" "=r")
1080 (zero_extend:DI (match_operand:HI
1 "register_operand" "r")))]
1083 [(set_attr "type" "shift")])
1085 (define_expand "zero_extendhidi2"
1086 [(set (match_operand:DI
0 "register_operand" "")
1087 (zero_extend:DI (match_operand:HI
1 "register_operand" "")))]
1091 (define_insn "zero_extendsidi2"
1092 [(set (match_operand:DI
0 "register_operand" "=r")
1093 (zero_extend:DI (match_operand:SI
1 "register_operand" "r")))]
1096 [(set_attr "type" "shift")])
1099 [(set (match_operand:DI
0 "register_operand" "=r")
1100 (and:DI (not:DI (match_operand:DI
1 "reg_or_8bit_operand" "rI"))
1101 (match_operand:DI
2 "reg_or_0_operand" "rJ")))]
1104 [(set_attr "type" "ilog")])
1106 (define_insn "iordi3"
1107 [(set (match_operand:DI
0 "register_operand" "=r,r")
1108 (ior:DI (match_operand:DI
1 "reg_or_0_operand" "%rJ,rJ")
1109 (match_operand:DI
2 "or_operand" "rI,N")))]
1114 [(set_attr "type" "ilog")])
1116 (define_insn "one_cmpldi2"
1117 [(set (match_operand:DI
0 "register_operand" "=r")
1118 (not:DI (match_operand:DI
1 "reg_or_8bit_operand" "rI")))]
1121 [(set_attr "type" "ilog")])
1124 [(set (match_operand:DI
0 "register_operand" "=r")
1125 (ior:DI (not:DI (match_operand:DI
1 "reg_or_8bit_operand" "rI"))
1126 (match_operand:DI
2 "reg_or_0_operand" "rJ")))]
1129 [(set_attr "type" "ilog")])
1131 (define_insn "xordi3"
1132 [(set (match_operand:DI
0 "register_operand" "=r,r")
1133 (xor:DI (match_operand:DI
1 "reg_or_0_operand" "%rJ,rJ")
1134 (match_operand:DI
2 "or_operand" "rI,N")))]
1139 [(set_attr "type" "ilog")])
1142 [(set (match_operand:DI
0 "register_operand" "=r")
1143 (not:DI (xor:DI (match_operand:DI
1 "register_operand" "%rJ")
1144 (match_operand:DI
2 "register_operand" "rI"))))]
1147 [(set_attr "type" "ilog")])
1149 ;; Handle the FFS insn if we support CIX.
1151 (define_expand "ffsdi2"
1153 (unspec [(match_operand:DI
1 "register_operand" "")]
1))
1155 (plus:DI (match_dup
2) (const_int
1)))
1156 (set (match_operand:DI
0 "register_operand" "")
1157 (if_then_else:DI (eq (match_dup
1) (const_int
0))
1158 (const_int
0) (match_dup
3)))]
1162 operands[
2] = gen_reg_rtx (DImode);
1163 operands[
3] = gen_reg_rtx (DImode);
1167 [(set (match_operand:DI
0 "register_operand" "=r")
1168 (unspec [(match_operand:DI
1 "register_operand" "r")]
1))]
1171 ; ev6 calls all mvi and cttz/ctlz/popc class imisc, so just
1172 ; reuse the existing type name.
1173 [(set_attr "type" "mvi")])
1175 ;; Next come the shifts and the various extract and insert operations.
1177 (define_insn "ashldi3"
1178 [(set (match_operand:DI
0 "register_operand" "=r,r")
1179 (ashift:DI (match_operand:DI
1 "reg_or_0_operand" "rJ,rJ")
1180 (match_operand:DI
2 "reg_or_6bit_operand" "P,rS")))]
1184 switch (which_alternative)
1187 if (operands[
2] == const1_rtx)
1188 return
\"addq %r1,%r1,%
0\";
1190 return
\"s%P2addq %r1,
0,%
0\";
1192 return
\"sll %r1,%
2,%
0\";
1197 [(set_attr "type" "iadd,shift")])
1199 ;; ??? The following pattern is made by combine, but earlier phases
1200 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1201 ;; with this in a better way at some point.
1203 ;; [(set (match_operand:DI
0 "register_operand" "=r")
1205 ;; (subreg:SI (ashift:DI (match_operand:DI
1 "reg_or_0_operand" "rJ")
1206 ;; (match_operand:DI
2 "const_int_operand" "P"))
1208 ;; "INTVAL (operands[
2]) >=
1 && INTVAL (operands[
2]) <=
3"
1211 ;; if (operands[
2] == const1_rtx)
1212 ;; return
\"addl %r1,%r1,%
0\";
1214 ;; return
\"s%P2addl %r1,
0,%
0\";
1216 ;; [(set_attr "type" "iadd")])
1218 (define_insn "lshrdi3"
1219 [(set (match_operand:DI
0 "register_operand" "=r")
1220 (lshiftrt:DI (match_operand:DI
1 "reg_or_0_operand" "rJ")
1221 (match_operand:DI
2 "reg_or_6bit_operand" "rS")))]
1224 [(set_attr "type" "shift")])
1226 (define_insn "ashrdi3"
1227 [(set (match_operand:DI
0 "register_operand" "=r")
1228 (ashiftrt:DI (match_operand:DI
1 "reg_or_0_operand" "rJ")
1229 (match_operand:DI
2 "reg_or_6bit_operand" "rS")))]
1232 [(set_attr "type" "shift")])
1234 (define_expand "extendqihi2"
1236 (ashift:DI (match_operand:QI
1 "some_operand" "")
1238 (set (match_operand:HI
0 "register_operand" "")
1239 (ashiftrt:DI (match_dup
2)
1246 emit_insn (gen_extendqihi2x (operands[
0],
1247 force_reg (QImode, operands[
1])));
1251 /* If we have an unaligned MEM, extend to DImode (which we do
1252 specially) and then copy to the result. */
1253 if (unaligned_memory_operand (operands[
1], HImode))
1255 rtx temp = gen_reg_rtx (DImode);
1257 emit_insn (gen_extendqidi2 (temp, operands[
1]));
1258 emit_move_insn (operands[
0], gen_lowpart (HImode, temp));
1262 operands[
0] = gen_lowpart (DImode, operands[
0]);
1263 operands[
1] = gen_lowpart (DImode, force_reg (QImode, operands[
1]));
1264 operands[
2] = gen_reg_rtx (DImode);
1267 (define_insn "extendqidi2x"
1268 [(set (match_operand:DI
0 "register_operand" "=r")
1269 (sign_extend:DI (match_operand:QI
1 "register_operand" "r")))]
1272 [(set_attr "type" "shift")])
1274 (define_insn "extendhidi2x"
1275 [(set (match_operand:DI
0 "register_operand" "=r")
1276 (sign_extend:DI (match_operand:HI
1 "register_operand" "r")))]
1279 [(set_attr "type" "shift")])
1281 (define_insn "extendqisi2x"
1282 [(set (match_operand:SI
0 "register_operand" "=r")
1283 (sign_extend:SI (match_operand:QI
1 "register_operand" "r")))]
1286 [(set_attr "type" "shift")])
1288 (define_insn "extendhisi2x"
1289 [(set (match_operand:SI
0 "register_operand" "=r")
1290 (sign_extend:SI (match_operand:HI
1 "register_operand" "r")))]
1293 [(set_attr "type" "shift")])
1295 (define_insn "extendqihi2x"
1296 [(set (match_operand:HI
0 "register_operand" "=r")
1297 (sign_extend:HI (match_operand:QI
1 "register_operand" "r")))]
1300 [(set_attr "type" "shift")])
1302 (define_expand "extendqisi2"
1304 (ashift:DI (match_operand:QI
1 "some_operand" "")
1306 (set (match_operand:SI
0 "register_operand" "")
1307 (ashiftrt:DI (match_dup
2)
1314 emit_insn (gen_extendqisi2x (operands[
0],
1315 force_reg (QImode, operands[
1])));
1319 /* If we have an unaligned MEM, extend to a DImode form of
1320 the result (which we do specially). */
1321 if (unaligned_memory_operand (operands[
1], QImode))
1323 rtx temp = gen_reg_rtx (DImode);
1325 emit_insn (gen_extendqidi2 (temp, operands[
1]));
1326 emit_move_insn (operands[
0], gen_lowpart (SImode, temp));
1330 operands[
0] = gen_lowpart (DImode, operands[
0]);
1331 operands[
1] = gen_lowpart (DImode, force_reg (QImode, operands[
1]));
1332 operands[
2] = gen_reg_rtx (DImode);
1335 (define_expand "extendqidi2"
1337 (ashift:DI (match_operand:QI
1 "some_operand" "")
1339 (set (match_operand:DI
0 "register_operand" "")
1340 (ashiftrt:DI (match_dup
2)
1347 emit_insn (gen_extendqidi2x (operands[
0],
1348 force_reg (QImode, operands[
1])));
1352 if (unaligned_memory_operand (operands[
1], QImode))
1355 = gen_unaligned_extendqidi (operands[
0],
1356 get_unaligned_address (operands[
1],
1));
1358 alpha_set_memflags (seq, operands[
1]);
1363 operands[
1] = gen_lowpart (DImode, force_reg (QImode, operands[
1]));
1364 operands[
2] = gen_reg_rtx (DImode);
1367 (define_expand "extendhisi2"
1369 (ashift:DI (match_operand:HI
1 "some_operand" "")
1371 (set (match_operand:SI
0 "register_operand" "")
1372 (ashiftrt:DI (match_dup
2)
1379 emit_insn (gen_extendhisi2x (operands[
0],
1380 force_reg (HImode, operands[
1])));
1384 /* If we have an unaligned MEM, extend to a DImode form of
1385 the result (which we do specially). */
1386 if (unaligned_memory_operand (operands[
1], HImode))
1388 rtx temp = gen_reg_rtx (DImode);
1390 emit_insn (gen_extendhidi2 (temp, operands[
1]));
1391 emit_move_insn (operands[
0], gen_lowpart (SImode, temp));
1395 operands[
0] = gen_lowpart (DImode, operands[
0]);
1396 operands[
1] = gen_lowpart (DImode, force_reg (HImode, operands[
1]));
1397 operands[
2] = gen_reg_rtx (DImode);
1400 (define_expand "extendhidi2"
1402 (ashift:DI (match_operand:HI
1 "some_operand" "")
1404 (set (match_operand:DI
0 "register_operand" "")
1405 (ashiftrt:DI (match_dup
2)
1412 emit_insn (gen_extendhidi2x (operands[
0],
1413 force_reg (HImode, operands[
1])));
1417 if (unaligned_memory_operand (operands[
1], HImode))
1420 = gen_unaligned_extendhidi (operands[
0],
1421 get_unaligned_address (operands[
1],
2));
1423 alpha_set_memflags (seq, operands[
1]);
1428 operands[
1] = gen_lowpart (DImode, force_reg (HImode, operands[
1]));
1429 operands[
2] = gen_reg_rtx (DImode);
1432 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1433 ;; as a pattern saves one instruction. The code is similar to that for
1434 ;; the unaligned loads (see below).
1436 ;; Operand
1 is the address +
1 (+
2 for HI), operand
0 is the result.
1437 (define_expand "unaligned_extendqidi"
1438 [(set (match_dup
2) (match_operand:DI
1 "address_operand" ""))
1440 (mem:DI (and:DI (plus:DI (match_dup
2) (const_int -
1))
1443 (ashift:DI (match_dup
3)
1444 (minus:DI (const_int
56)
1446 (and:DI (plus:DI (match_dup
2) (const_int -
1))
1449 (set (subreg:DI (match_operand:QI
0 "register_operand" "")
0)
1450 (ashiftrt:DI (match_dup
4) (const_int
56)))]
1453 { operands[
2] = gen_reg_rtx (DImode);
1454 operands[
3] = gen_reg_rtx (DImode);
1455 operands[
4] = gen_reg_rtx (DImode);
1458 (define_expand "unaligned_extendhidi"
1459 [(set (match_dup
2) (match_operand:DI
1 "address_operand" ""))
1461 (mem:DI (and:DI (plus:DI (match_dup
2) (const_int -
2))
1464 (ashift:DI (match_dup
3)
1465 (minus:DI (const_int
56)
1467 (and:DI (plus:DI (match_dup
2) (const_int -
1))
1470 (set (subreg:DI (match_operand:QI
0 "register_operand" "")
0)
1471 (ashiftrt:DI (match_dup
4) (const_int
48)))]
1474 { operands[
2] = gen_reg_rtx (DImode);
1475 operands[
3] = gen_reg_rtx (DImode);
1476 operands[
4] = gen_reg_rtx (DImode);
1480 [(set (match_operand:DI
0 "register_operand" "=r")
1481 (zero_extract:DI (match_operand:DI
1 "reg_or_0_operand" "rJ")
1482 (match_operand:DI
2 "mode_width_operand" "n")
1483 (match_operand:DI
3 "mul8_operand" "I")))]
1485 "ext%M2l %r1,%s3,%
0"
1486 [(set_attr "type" "shift")])
1488 (define_insn "extxl"
1489 [(set (match_operand:DI
0 "register_operand" "=r")
1490 (zero_extract:DI (match_operand:DI
1 "reg_or_0_operand" "rJ")
1491 (match_operand:DI
2 "mode_width_operand" "n")
1492 (ashift:DI (match_operand:DI
3 "reg_or_8bit_operand" "rI")
1496 [(set_attr "type" "shift")])
1498 ;; Combine has some strange notion of preserving existing undefined behaviour
1499 ;; in shifts larger than a word size. So capture these patterns that it
1500 ;; should have turned into zero_extracts.
1503 [(set (match_operand:DI
0 "register_operand" "=r")
1504 (and (lshiftrt:DI (match_operand:DI
1 "reg_or_0_operand" "rJ")
1505 (ashift:DI (match_operand:DI
2 "reg_or_8bit_operand" "rI")
1507 (match_operand:DI
3 "mode_mask_operand" "n")))]
1510 [(set_attr "type" "shift")])
1513 [(set (match_operand:DI
0 "register_operand" "=r")
1514 (lshiftrt:DI (match_operand:DI
1 "reg_or_0_operand" "rJ")
1515 (ashift:DI (match_operand:DI
2 "reg_or_8bit_operand" "rI")
1519 [(set_attr "type" "shift")])
1521 (define_insn "extqh"
1522 [(set (match_operand:DI
0 "register_operand" "=r")
1524 (match_operand:DI
1 "reg_or_0_operand" "rJ")
1525 (minus:DI (const_int
56)
1528 (plus:DI (match_operand:DI
2 "reg_or_8bit_operand" "rI")
1534 [(set_attr "type" "shift")])
1536 (define_insn "extlh"
1537 [(set (match_operand:DI
0 "register_operand" "=r")
1539 (and:DI (match_operand:DI
1 "reg_or_0_operand" "rJ")
1540 (const_int
2147483647))
1541 (minus:DI (const_int
56)
1544 (plus:DI (match_operand:DI
2 "reg_or_8bit_operand" "rI")
1550 [(set_attr "type" "shift")])
1552 (define_insn "extwh"
1553 [(set (match_operand:DI
0 "register_operand" "=r")
1555 (and:DI (match_operand:DI
1 "reg_or_0_operand" "rJ")
1557 (minus:DI (const_int
56)
1560 (plus:DI (match_operand:DI
2 "reg_or_8bit_operand" "rI")
1566 [(set_attr "type" "shift")])
1568 ;; This converts an extXl into an extXh with an appropriate adjustment
1569 ;; to the address calculation.
1572 ;; [(set (match_operand:DI
0 "register_operand" "")
1573 ;; (ashift:DI (zero_extract:DI (match_operand:DI
1 "register_operand" "")
1574 ;; (match_operand:DI
2 "mode_width_operand" "")
1575 ;; (ashift:DI (match_operand:DI
3 "" "")
1577 ;; (match_operand:DI
4 "const_int_operand" "")))
1578 ;; (clobber (match_operand:DI
5 "register_operand" ""))]
1579 ;; "INTVAL (operands[
4]) ==
64 - INTVAL (operands[
2])"
1580 ;; [(set (match_dup
5) (match_dup
6))
1581 ;; (set (match_dup
0)
1582 ;; (ashift:DI (zero_extract:DI (match_dup
1) (match_dup
2)
1583 ;; (ashift:DI (plus:DI (match_dup
5)
1589 ;; operands[
6] = plus_constant (operands[
3],
1590 ;; INTVAL (operands[
2]) / BITS_PER_UNIT);
1591 ;; operands[
7] = GEN_INT (- INTVAL (operands[
2]) / BITS_PER_UNIT);
1595 [(set (match_operand:DI
0 "register_operand" "=r")
1596 (ashift:DI (zero_extend:DI (match_operand:QI
1 "register_operand" "r"))
1597 (match_operand:DI
2 "mul8_operand" "I")))]
1600 [(set_attr "type" "shift")])
1603 [(set (match_operand:DI
0 "register_operand" "=r")
1604 (ashift:DI (zero_extend:DI (match_operand:HI
1 "register_operand" "r"))
1605 (match_operand:DI
2 "mul8_operand" "I")))]
1608 [(set_attr "type" "shift")])
1611 [(set (match_operand:DI
0 "register_operand" "=r")
1612 (ashift:DI (zero_extend:DI (match_operand:SI
1 "register_operand" "r"))
1613 (match_operand:DI
2 "mul8_operand" "I")))]
1616 [(set_attr "type" "shift")])
1618 (define_insn "insbl"
1619 [(set (match_operand:DI
0 "register_operand" "=r")
1620 (ashift:DI (zero_extend:DI (match_operand:QI
1 "register_operand" "r"))
1621 (ashift:DI (match_operand:DI
2 "reg_or_8bit_operand" "rI")
1625 [(set_attr "type" "shift")])
1627 (define_insn "inswl"
1628 [(set (match_operand:DI
0 "register_operand" "=r")
1629 (ashift:DI (zero_extend:DI (match_operand:HI
1 "register_operand" "r"))
1630 (ashift:DI (match_operand:DI
2 "reg_or_8bit_operand" "rI")
1634 [(set_attr "type" "shift")])
1636 (define_insn "insll"
1637 [(set (match_operand:DI
0 "register_operand" "=r")
1638 (ashift:DI (zero_extend:DI (match_operand:SI
1 "register_operand" "r"))
1639 (ashift:DI (match_operand:DI
2 "reg_or_8bit_operand" "rI")
1643 [(set_attr "type" "shift")])
1645 (define_insn "insql"
1646 [(set (match_operand:DI
0 "register_operand" "=r")
1647 (ashift:DI (match_operand:DI
1 "register_operand" "r")
1648 (ashift:DI (match_operand:DI
2 "reg_or_8bit_operand" "rI")
1652 [(set_attr "type" "shift")])
1654 ;; Combine has this sometimes habit of moving the and outside of the
1655 ;; shift, making life more interesting.
1658 [(set (match_operand:DI
0 "register_operand" "=r")
1659 (and:DI (ashift:DI (match_operand:DI
1 "register_operand" "r")
1660 (match_operand:DI
2 "mul8_operand" "I"))
1661 (match_operand:DI
3 "immediate_operand" "i")))]
1662 "HOST_BITS_PER_WIDE_INT ==
64
1663 && GET_CODE (operands[
3]) == CONST_INT
1664 && (((unsigned HOST_WIDE_INT)
0xff << INTVAL (operands[
2])
1665 == INTVAL (operands[
3]))
1666 || ((unsigned HOST_WIDE_INT)
0xffff << INTVAL (operands[
2])
1667 == INTVAL (operands[
3]))
1668 || ((unsigned HOST_WIDE_INT)
0xffffffff << INTVAL (operands[
2])
1669 == INTVAL (operands[
3])))"
1672 #if HOST_BITS_PER_WIDE_INT == 64
1673 if ((unsigned HOST_WIDE_INT)
0xff << INTVAL (operands[
2])
1674 == INTVAL (operands[
3]))
1675 return
\"insbl %
1,%s2,%
0\";
1676 if ((unsigned HOST_WIDE_INT)
0xffff << INTVAL (operands[
2])
1677 == INTVAL (operands[
3]))
1678 return
\"inswl %
1,%s2,%
0\";
1679 if ((unsigned HOST_WIDE_INT)
0xffffffff << INTVAL (operands[
2])
1680 == INTVAL (operands[
3]))
1681 return
\"insll %
1,%s2,%
0\";
1685 [(set_attr "type" "shift")])
1687 ;; We do not include the insXh insns because they are complex to express
1688 ;; and it does not appear that we would ever want to generate them.
1690 ;; Since we need them for block moves, though, cop out and use unspec.
1692 (define_insn "insxh"
1693 [(set (match_operand:DI
0 "register_operand" "=r")
1694 (unspec [(match_operand:DI
1 "register_operand" "r")
1695 (match_operand:DI
2 "mode_width_operand" "n")
1696 (match_operand:DI
3 "reg_or_8bit_operand" "rI")]
2))]
1699 [(set_attr "type" "shift")])
1701 (define_insn "mskxl"
1702 [(set (match_operand:DI
0 "register_operand" "=r")
1703 (and:DI (not:DI (ashift:DI
1704 (match_operand:DI
2 "mode_mask_operand" "n")
1706 (match_operand:DI
3 "reg_or_8bit_operand" "rI")
1708 (match_operand:DI
1 "reg_or_0_operand" "rJ")))]
1711 [(set_attr "type" "shift")])
1713 ;; We do not include the mskXh insns because it does not appear we would
1714 ;; ever generate one.
1716 ;; Again, we do for block moves and we use unspec again.
1718 (define_insn "mskxh"
1719 [(set (match_operand:DI
0 "register_operand" "=r")
1720 (unspec [(match_operand:DI
1 "register_operand" "r")
1721 (match_operand:DI
2 "mode_width_operand" "n")
1722 (match_operand:DI
3 "reg_or_8bit_operand" "rI")]
3))]
1725 [(set_attr "type" "shift")])
1727 ;; Floating-point operations. All the double-precision insns can extend
1728 ;; from single, so indicate that. The exception are the ones that simply
1729 ;; play with the sign bits; it's not clear what to do there.
1731 (define_insn "abssf2"
1732 [(set (match_operand:SF
0 "register_operand" "=f")
1733 (abs:SF (match_operand:SF
1 "reg_or_fp0_operand" "fG")))]
1736 [(set_attr "type" "fcpys")])
1738 (define_insn "absdf2"
1739 [(set (match_operand:DF
0 "register_operand" "=f")
1740 (abs:DF (match_operand:DF
1 "reg_or_fp0_operand" "fG")))]
1743 [(set_attr "type" "fcpys")])
1745 (define_insn "negsf2"
1746 [(set (match_operand:SF
0 "register_operand" "=f")
1747 (neg:SF (match_operand:SF
1 "reg_or_fp0_operand" "fG")))]
1750 [(set_attr "type" "fadd")])
1752 (define_insn "negdf2"
1753 [(set (match_operand:DF
0 "register_operand" "=f")
1754 (neg:DF (match_operand:DF
1 "reg_or_fp0_operand" "fG")))]
1757 [(set_attr "type" "fadd")])
1760 [(set (match_operand:SF
0 "register_operand" "=&f")
1761 (plus:SF (match_operand:SF
1 "reg_or_fp0_operand" "%fG")
1762 (match_operand:SF
2 "reg_or_fp0_operand" "fG")))]
1763 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1764 "add%,%)%& %R1,%R2,%
0"
1765 [(set_attr "type" "fadd")
1766 (set_attr "trap" "yes")])
1768 (define_insn "addsf3"
1769 [(set (match_operand:SF
0 "register_operand" "=f")
1770 (plus:SF (match_operand:SF
1 "reg_or_fp0_operand" "%fG")
1771 (match_operand:SF
2 "reg_or_fp0_operand" "fG")))]
1773 "add%,%)%& %R1,%R2,%
0"
1774 [(set_attr "type" "fadd")
1775 (set_attr "trap" "yes")])
1778 [(set (match_operand:DF
0 "register_operand" "=&f")
1779 (plus:DF (match_operand:DF
1 "reg_or_fp0_operand" "%fG")
1780 (match_operand:DF
2 "reg_or_fp0_operand" "fG")))]
1781 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1782 "add%-%)%& %R1,%R2,%
0"
1783 [(set_attr "type" "fadd")
1784 (set_attr "trap" "yes")])
1786 (define_insn "adddf3"
1787 [(set (match_operand:DF
0 "register_operand" "=f")
1788 (plus:DF (match_operand:DF
1 "reg_or_fp0_operand" "%fG")
1789 (match_operand:DF
2 "reg_or_fp0_operand" "fG")))]
1791 "add%-%)%& %R1,%R2,%
0"
1792 [(set_attr "type" "fadd")
1793 (set_attr "trap" "yes")])
1796 [(set (match_operand:DF
0 "register_operand" "=f")
1797 (plus:DF (float_extend:DF
1798 (match_operand:SF
1 "reg_or_fp0_operand" "fG"))
1799 (match_operand:DF
2 "reg_or_fp0_operand" "fG")))]
1800 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1801 "add%-%)%& %R1,%R2,%
0"
1802 [(set_attr "type" "fadd")
1803 (set_attr "trap" "yes")])
1806 [(set (match_operand:DF
0 "register_operand" "=f")
1807 (plus:DF (float_extend:DF
1808 (match_operand:SF
1 "reg_or_fp0_operand" "%fG"))
1810 (match_operand:SF
2 "reg_or_fp0_operand" "fG"))))]
1811 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1812 "add%-%)%& %R1,%R2,%
0"
1813 [(set_attr "type" "fadd")
1814 (set_attr "trap" "yes")])
1816 ;; Define conversion operators between DFmode and SImode, using the cvtql
1817 ;; instruction. To allow combine et al to do useful things, we keep the
1818 ;; operation as a unit until after reload, at which point we split the
1821 ;; Note that we (attempt to) only consider this optimization when the
1822 ;; ultimate destination is memory. If we will be doing further integer
1823 ;; processing, it is cheaper to do the truncation in the int regs.
1825 (define_insn "*cvtql"
1826 [(set (match_operand:SI
0 "register_operand" "=f")
1827 (unspec:SI [(match_operand:DI
1 "reg_or_fp0_operand" "fG")]
5))]
1830 [(set_attr "type" "fadd")
1831 (set_attr "trap" "yes")])
1834 [(set (match_operand:SI 0 "memory_operand" "")
1835 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1836 (clobber (match_scratch:DI 2 ""))
1837 (clobber (match_scratch:SI 3 ""))]
1838 "TARGET_FP && reload_completed"
1839 [(set (match_dup 2) (fix:DI (match_dup 1)))
1840 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1841 (set (match_dup 0) (match_dup 3))]
1845 [(set (match_operand:SI 0 "memory_operand" "")
1846 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1847 (clobber (match_scratch:DI 2 ""))]
1848 "TARGET_FP && reload_completed"
1849 [(set (match_dup 2) (fix:DI (match_dup 1)))
1850 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1851 (set (match_dup 0) (match_dup 3))]
1852 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
1853 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
1856 [(set (match_operand:SI 0 "memory_operand" "=m")
1857 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
1858 (clobber (match_scratch:DI 2 "=&f"))
1859 (clobber (match_scratch:SI 3 "=&f"))]
1860 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1862 [(set_attr "type" "fadd")
1863 (set_attr "trap" "yes")])
1866 [(set (match_operand:SI 0 "memory_operand" "=m")
1867 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
1868 (clobber (match_scratch:DI 2 "=f"))]
1869 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1871 [(set_attr "type" "fadd")
1872 (set_attr "trap" "yes")])
1875 [(set (match_operand:DI 0 "register_operand" "=&f")
1876 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1877 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1879 [(set_attr "type" "fadd")
1880 (set_attr "trap" "yes")])
1882 (define_insn "fix_truncdfdi2"
1883 [(set (match_operand:DI 0 "register_operand" "=f")
1884 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1887 [(set_attr "type" "fadd")
1888 (set_attr "trap" "yes")])
1890 ;; Likewise between SFmode and SImode.
1893 [(set (match_operand:SI 0 "memory_operand" "")
1894 (subreg:SI (fix:DI (float_extend:DF
1895 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
1896 (clobber (match_scratch:DI 2 ""))
1897 (clobber (match_scratch:SI 3 ""))]
1898 "TARGET_FP && reload_completed"
1899 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
1900 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1901 (set (match_dup 0) (match_dup 3))]
1905 [(set (match_operand:SI 0 "memory_operand" "")
1906 (subreg:SI (fix:DI (float_extend:DF
1907 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
1908 (clobber (match_scratch:DI 2 ""))]
1909 "TARGET_FP && reload_completed"
1910 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
1911 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1912 (set (match_dup 0) (match_dup 3))]
1913 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
1914 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
1917 [(set (match_operand:SI 0 "memory_operand" "=m")
1918 (subreg:SI (fix:DI (float_extend:DF
1919 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
1920 (clobber (match_scratch:DI 2 "=&f"))
1921 (clobber (match_scratch:SI 3 "=&f"))]
1922 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1924 [(set_attr "type" "fadd")
1925 (set_attr "trap" "yes")])
1928 [(set (match_operand:SI 0 "memory_operand" "=m")
1929 (subreg:SI (fix:DI (float_extend:DF
1930 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
1931 (clobber (match_scratch:DI 2 "=f"))]
1932 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1934 [(set_attr "type" "fadd")
1935 (set_attr "trap" "yes")])
1938 [(set (match_operand:DI 0 "register_operand" "=&f")
1939 (fix:DI (float_extend:DF
1940 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
1941 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1943 [(set_attr "type" "fadd")
1944 (set_attr "trap" "yes")])
1946 (define_insn "fix_truncsfdi2"
1947 [(set (match_operand:DI 0 "register_operand" "=f")
1948 (fix:DI (float_extend:DF
1949 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
1952 [(set_attr "type" "fadd")
1953 (set_attr "trap" "yes")])
1956 [(set (match_operand:SF 0 "register_operand" "=&f")
1957 (float:SF (match_operand:DI 1 "register_operand" "f")))]
1958 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1960 [(set_attr "type" "fadd")
1961 (set_attr "trap" "yes")])
1963 (define_insn "floatdisf2"
1964 [(set (match_operand:SF 0 "register_operand" "=f")
1965 (float:SF (match_operand:DI 1 "register_operand" "f")))]
1968 [(set_attr "type" "fadd")
1969 (set_attr "trap" "yes")])
1972 [(set (match_operand:DF 0 "register_operand" "=&f")
1973 (float:DF (match_operand:DI 1 "register_operand" "f")))]
1974 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1976 [(set_attr "type" "fadd")
1977 (set_attr "trap" "yes")])
1979 (define_insn "floatdidf2"
1980 [(set (match_operand:DF 0 "register_operand" "=f")
1981 (float:DF (match_operand:DI 1 "register_operand" "f")))]
1984 [(set_attr "type" "fadd")
1985 (set_attr "trap" "yes")])
1987 (define_expand "extendsfdf2"
1988 [(use (match_operand:DF 0 "register_operand" ""))
1989 (use (match_operand:SF 1 "nonimmediate_operand" ""))]
1993 if (alpha_tp == ALPHA_TP_INSN)
1994 emit_insn (gen_extendsfdf2_tp (operands[0],
1995 force_reg (SFmode, operands[1])));
1997 emit_insn (gen_extendsfdf2_no_tp (operands[0], operands[1]));
2002 (define_insn "extendsfdf2_tp"
2003 [(set (match_operand:DF 0 "register_operand" "=&f")
2004 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2005 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2007 [(set_attr "type" "fadd")
2008 (set_attr "trap" "yes")])
2010 (define_insn "extendsfdf2_no_tp"
2011 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2012 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2013 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2018 [(set_attr "type" "fcpys,fld,fst")
2019 (set_attr "trap" "yes")])
2022 [(set (match_operand:SF 0 "register_operand" "=&f")
2023 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2024 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2025 "cvt%-%,%)%& %R1,%0"
2026 [(set_attr "type" "fadd")
2027 (set_attr "trap" "yes")])
2029 (define_insn "truncdfsf2"
2030 [(set (match_operand:SF 0 "register_operand" "=f")
2031 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2033 "cvt%-%,%)%& %R1,%0"
2034 [(set_attr "type" "fadd")
2035 (set_attr "trap" "yes")])
2038 [(set (match_operand:SF 0 "register_operand" "=&f")
2039 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2040 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2041 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2042 "div%,%)%& %R1,%R2,%0"
2043 [(set_attr "type" "fdiv")
2044 (set_attr "opsize" "si")
2045 (set_attr "trap" "yes")])
2047 (define_insn "divsf3"
2048 [(set (match_operand:SF 0 "register_operand" "=f")
2049 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2050 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2052 "div%,%)%& %R1,%R2,%0"
2053 [(set_attr "type" "fdiv")
2054 (set_attr "opsize" "si")
2055 (set_attr "trap" "yes")])
2058 [(set (match_operand:DF 0 "register_operand" "=&f")
2059 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2060 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2061 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2062 "div%-%)%& %R1,%R2,%0"
2063 [(set_attr "type" "fdiv")
2064 (set_attr "trap" "yes")])
2066 (define_insn "divdf3"
2067 [(set (match_operand:DF 0 "register_operand" "=f")
2068 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2069 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2071 "div%-%)%& %R1,%R2,%0"
2072 [(set_attr "type" "fdiv")
2073 (set_attr "trap" "yes")])
2076 [(set (match_operand:DF 0 "register_operand" "=f")
2077 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2078 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2079 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2080 "div%-%)%& %R1,%R2,%0"
2081 [(set_attr "type" "fdiv")
2082 (set_attr "trap" "yes")])
2085 [(set (match_operand:DF 0 "register_operand" "=f")
2086 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2088 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2089 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2090 "div%-%)%& %R1,%R2,%0"
2091 [(set_attr "type" "fdiv")
2092 (set_attr "trap" "yes")])
2095 [(set (match_operand:DF 0 "register_operand" "=f")
2096 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2097 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2098 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2099 "div%-%)%& %R1,%R2,%0"
2100 [(set_attr "type" "fdiv")
2101 (set_attr "trap" "yes")])
2104 [(set (match_operand:SF 0 "register_operand" "=&f")
2105 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2106 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2107 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2108 "mul%,%)%& %R1,%R2,%0"
2109 [(set_attr "type" "fmul")
2110 (set_attr "trap" "yes")])
2112 (define_insn "mulsf3"
2113 [(set (match_operand:SF 0 "register_operand" "=f")
2114 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2115 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2117 "mul%,%)%& %R1,%R2,%0"
2118 [(set_attr "type" "fmul")
2119 (set_attr "trap" "yes")])
2122 [(set (match_operand:DF 0 "register_operand" "=&f")
2123 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2124 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2125 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2126 "mul%-%)%& %R1,%R2,%0"
2127 [(set_attr "type" "fmul")
2128 (set_attr "trap" "yes")])
2130 (define_insn "muldf3"
2131 [(set (match_operand:DF 0 "register_operand" "=f")
2132 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2133 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2135 "mul%-%)%& %R1,%R2,%0"
2136 [(set_attr "type" "fmul")
2137 (set_attr "trap" "yes")])
2140 [(set (match_operand:DF 0 "register_operand" "=f")
2141 (mult:DF (float_extend:DF
2142 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2143 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2144 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2145 "mul%-%)%& %R1,%R2,%0"
2146 [(set_attr "type" "fmul")
2147 (set_attr "trap" "yes")])
2150 [(set (match_operand:DF 0 "register_operand" "=f")
2151 (mult:DF (float_extend:DF
2152 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2154 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2155 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2156 "mul%-%)%& %R1,%R2,%0"
2157 [(set_attr "type" "fmul")
2158 (set_attr "trap" "yes")])
2161 [(set (match_operand:SF 0 "register_operand" "=&f")
2162 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2163 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2164 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2165 "sub%,%)%& %R1,%R2,%0"
2166 [(set_attr "type" "fadd")
2167 (set_attr "trap" "yes")])
2169 (define_insn "subsf3"
2170 [(set (match_operand:SF 0 "register_operand" "=f")
2171 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2172 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2174 "sub%,%)%& %R1,%R2,%0"
2175 [(set_attr "type" "fadd")
2176 (set_attr "trap" "yes")])
2179 [(set (match_operand:DF 0 "register_operand" "=&f")
2180 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2181 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2182 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2183 "sub%-%)%& %R1,%R2,%0"
2184 [(set_attr "type" "fadd")
2185 (set_attr "trap" "yes")])
2187 (define_insn "subdf3"
2188 [(set (match_operand:DF 0 "register_operand" "=f")
2189 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2190 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2192 "sub%-%)%& %R1,%R2,%0"
2193 [(set_attr "type" "fadd")
2194 (set_attr "trap" "yes")])
2197 [(set (match_operand:DF 0 "register_operand" "=f")
2198 (minus:DF (float_extend:DF
2199 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2200 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2201 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2202 "sub%-%)%& %R1,%R2,%0"
2203 [(set_attr "type" "fadd")
2204 (set_attr "trap" "yes")])
2207 [(set (match_operand:DF 0 "register_operand" "=f")
2208 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2210 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2211 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2212 "sub%-%)%& %R1,%R2,%0"
2213 [(set_attr "type" "fadd")
2214 (set_attr "trap" "yes")])
2217 [(set (match_operand:DF 0 "register_operand" "=f")
2218 (minus:DF (float_extend:DF
2219 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2221 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2222 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2223 "sub%-%)%& %R1,%R2,%0"
2224 [(set_attr "type" "fadd")
2225 (set_attr "trap" "yes")])
2228 [(set (match_operand:SF 0 "register_operand" "=&f")
2229 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2230 "TARGET_FP && TARGET_CIX && alpha_tp == ALPHA_TP_INSN"
2232 [(set_attr "type" "fsqrt")
2233 (set_attr "opsize" "si")
2234 (set_attr "trap" "yes")])
2236 (define_insn "sqrtsf2"
2237 [(set (match_operand:SF 0 "register_operand" "=f")
2238 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2239 "TARGET_FP && TARGET_CIX"
2241 [(set_attr "type" "fsqrt")
2242 (set_attr "opsize" "si")
2243 (set_attr "trap" "yes")])
2246 [(set (match_operand:DF 0 "register_operand" "=&f")
2247 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2248 "TARGET_FP && TARGET_CIX && alpha_tp == ALPHA_TP_INSN"
2250 [(set_attr "type" "fsqrt")
2251 (set_attr "trap" "yes")])
2253 (define_insn "sqrtdf2"
2254 [(set (match_operand:DF 0 "register_operand" "=f")
2255 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2256 "TARGET_FP && TARGET_CIX"
2258 [(set_attr "type" "fsqrt")
2259 (set_attr "trap" "yes")])
2261 ;; Next are all the integer comparisons, and conditional moves and branches
2262 ;; and some of the related define_expand's and define_split's.
2265 [(set (match_operand:DI 0 "register_operand" "=r")
2266 (match_operator:DI 1 "alpha_comparison_operator"
2267 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2268 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2271 [(set_attr "type" "icmp")])
2274 [(set (match_operand:DI 0 "register_operand" "=r")
2275 (match_operator:DI 1 "alpha_swapped_comparison_operator"
2276 [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
2277 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2280 [(set_attr "type" "icmp")])
2282 ;; This pattern exists so conditional moves of SImode values are handled.
2283 ;; Comparisons are still done in DImode though.
2286 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2288 (match_operator 2 "signed_comparison_operator"
2289 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2290 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2291 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2292 (match_operand:SI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2293 "operands[3] == const0_rtx || operands[4] == const0_rtx"
2299 [(set_attr "type" "icmov")])
2302 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2304 (match_operator 2 "signed_comparison_operator"
2305 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2306 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2307 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2308 (match_operand:DI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2309 "operands[3] == const0_rtx || operands[4] == const0_rtx"
2315 [(set_attr "type" "icmov")])
2318 [(set (match_operand:DI 0 "register_operand" "=r,r")
2320 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2324 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2325 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2330 [(set_attr "type" "icmov")])
2333 [(set (match_operand:DI 0 "register_operand" "=r,r")
2335 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2339 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2340 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2345 [(set_attr "type" "icmov")])
2347 ;; This form is added since combine thinks that an IF_THEN_ELSE with both
2348 ;; arms constant is a single insn, so it won't try to form it if combine
2349 ;; knows they are really two insns. This occurs in divides by powers
2353 [(set (match_operand:DI 0 "register_operand" "=r")
2355 (match_operator 2 "signed_comparison_operator"
2356 [(match_operand:DI 3 "reg_or_0_operand" "rJ")
2358 (plus:DI (match_dup 0)
2359 (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
2361 (clobber (match_scratch:DI 4 "=&r"))]
2363 "addq %0,%1,%4\;cmov%C2 %r3,%4,%0"
2364 [(set_attr "type" "icmov")
2365 (set_attr "length" "8")])
2368 [(set (match_operand:DI 0 "register_operand" "")
2370 (match_operator 2 "signed_comparison_operator"
2371 [(match_operand:DI 3 "reg_or_0_operand" "")
2373 (plus:DI (match_dup 0)
2374 (match_operand:DI 1 "reg_or_8bit_operand" ""))
2376 (clobber (match_operand:DI 4 "register_operand" ""))]
2378 [(set (match_dup 4) (plus:DI (match_dup 0) (match_dup 1)))
2379 (set (match_dup 0) (if_then_else:DI (match_op_dup 2
2382 (match_dup 4) (match_dup 0)))]
2387 [(set (match_operand:DI 0 "register_operand" "")
2389 (match_operator 1 "comparison_operator"
2390 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
2392 (match_operand:DI 3 "const_int_operand" ""))
2394 (match_operand:DI 4 "reg_or_8bit_operand" "")
2395 (match_operand:DI 5 "reg_or_8bit_operand" "")))
2396 (clobber (match_operand:DI 6 "register_operand" ""))])]
2397 "INTVAL (operands[3]) != 0"
2399 (lshiftrt:DI (match_dup 2) (match_dup 3)))
2401 (if_then_else:DI (match_op_dup 1
2402 [(zero_extract:DI (match_dup 6)
2410 ;; For ABS, we have two choices, depending on whether the input and output
2411 ;; registers are the same or not.
2412 (define_expand "absdi2"
2413 [(set (match_operand:DI 0 "register_operand" "")
2414 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2417 { if (rtx_equal_p (operands[0], operands[1]))
2418 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
2420 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
2425 (define_expand "absdi2_same"
2426 [(set (match_operand:DI 1 "register_operand" "")
2427 (neg:DI (match_operand:DI 0 "register_operand" "")))
2429 (if_then_else:DI (ge (match_dup 0) (const_int 0))
2435 (define_expand "absdi2_diff"
2436 [(set (match_operand:DI 0 "register_operand" "")
2437 (neg:DI (match_operand:DI 1 "register_operand" "")))
2439 (if_then_else:DI (lt (match_dup 1) (const_int 0))
2446 [(set (match_operand:DI 0 "register_operand" "")
2447 (abs:DI (match_dup 0)))
2448 (clobber (match_operand:DI 2 "register_operand" ""))]
2450 [(set (match_dup 1) (neg:DI (match_dup 0)))
2451 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
2452 (match_dup 0) (match_dup 1)))]
2456 [(set (match_operand:DI 0 "register_operand" "")
2457 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2458 "! rtx_equal_p (operands[0], operands[1])"
2459 [(set (match_dup 0) (neg:DI (match_dup 1)))
2460 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
2461 (match_dup 0) (match_dup 1)))]
2465 [(set (match_operand:DI 0 "register_operand" "")
2466 (neg:DI (abs:DI (match_dup 0))))
2467 (clobber (match_operand:DI 2 "register_operand" ""))]
2469 [(set (match_dup 1) (neg:DI (match_dup 0)))
2470 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
2471 (match_dup 0) (match_dup 1)))]
2475 [(set (match_operand:DI 0 "register_operand" "")
2476 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
2477 "! rtx_equal_p (operands[0], operands[1])"
2478 [(set (match_dup 0) (neg:DI (match_dup 1)))
2479 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
2480 (match_dup 0) (match_dup 1)))]
2483 (define_insn "sminqi3"
2484 [(set (match_operand:QI 0 "register_operand" "=r")
2485 (smin:SI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2486 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2489 [(set_attr "type" "mvi")])
2491 (define_insn "uminqi3"
2492 [(set (match_operand:QI 0 "register_operand" "=r")
2493 (umin:SI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2494 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2497 [(set_attr "type" "mvi")])
2499 (define_insn "smaxqi3"
2500 [(set (match_operand:QI 0 "register_operand" "=r")
2501 (smax:SI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2502 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2505 [(set_attr "type" "mvi")])
2507 (define_insn "umaxqi3"
2508 [(set (match_operand:QI 0 "register_operand" "=r")
2509 (umax:SI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2510 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2513 [(set_attr "type" "mvi")])
2515 (define_insn "sminhi3"
2516 [(set (match_operand:HI 0 "register_operand" "=r")
2517 (smin:SI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2518 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2521 [(set_attr "type" "mvi")])
2523 (define_insn "uminhi3"
2524 [(set (match_operand:HI 0 "register_operand" "=r")
2525 (umin:SI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2526 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2529 [(set_attr "type" "mvi")])
2531 (define_insn "smaxhi3"
2532 [(set (match_operand:HI 0 "register_operand" "=r")
2533 (smax:SI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2534 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2537 [(set_attr "type" "mvi")])
2539 (define_insn "umaxhi3"
2540 [(set (match_operand:HI 0 "register_operand" "=r")
2541 (umax:SI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2542 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2545 [(set_attr "type" "shift")])
2547 (define_expand "smaxdi3"
2549 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
2550 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2551 (set (match_operand:DI 0 "register_operand" "")
2552 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2553 (match_dup 1) (match_dup 2)))]
2556 { operands[3] = gen_reg_rtx (DImode);
2560 [(set (match_operand:DI 0 "register_operand" "")
2561 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2562 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2563 (clobber (match_operand:DI 3 "register_operand" ""))]
2564 "operands[2] != const0_rtx"
2565 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
2566 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2567 (match_dup 1) (match_dup 2)))]
2571 [(set (match_operand:DI 0 "register_operand" "=r")
2572 (smax:DI (match_operand:DI 1 "register_operand" "0")
2576 [(set_attr "type" "icmov")])
2578 (define_expand "smindi3"
2580 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
2581 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2582 (set (match_operand:DI 0 "register_operand" "")
2583 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2584 (match_dup 1) (match_dup 2)))]
2587 { operands[3] = gen_reg_rtx (DImode);
2591 [(set (match_operand:DI 0 "register_operand" "")
2592 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2593 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2594 (clobber (match_operand:DI 3 "register_operand" ""))]
2595 "operands[2] != const0_rtx"
2596 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
2597 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2598 (match_dup 1) (match_dup 2)))]
2602 [(set (match_operand:DI 0 "register_operand" "=r")
2603 (smin:DI (match_operand:DI 1 "register_operand" "0")
2607 [(set_attr "type" "icmov")])
2609 (define_expand "umaxdi3"
2611 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2612 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2613 (set (match_operand:DI 0 "register_operand" "")
2614 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2615 (match_dup 1) (match_dup 2)))]
2618 { operands[3] = gen_reg_rtx (DImode);
2622 [(set (match_operand:DI 0 "register_operand" "")
2623 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2624 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2625 (clobber (match_operand:DI 3 "register_operand" ""))]
2626 "operands[2] != const0_rtx"
2627 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
2628 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2629 (match_dup 1) (match_dup 2)))]
2632 (define_expand "umindi3"
2634 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2635 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2636 (set (match_operand:DI 0 "register_operand" "")
2637 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2638 (match_dup 1) (match_dup 2)))]
2641 { operands[3] = gen_reg_rtx (DImode);
2645 [(set (match_operand:DI 0 "register_operand" "")
2646 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2647 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2648 (clobber (match_operand:DI 3 "register_operand" ""))]
2649 "operands[2] != const0_rtx"
2650 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
2651 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2652 (match_dup 1) (match_dup 2)))]
2658 (match_operator 1 "signed_comparison_operator"
2659 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2661 (label_ref (match_operand 0 "" ""))
2665 [(set_attr "type" "ibr")])
2670 (match_operator 1 "signed_comparison_operator"
2672 (match_operand:DI 2 "register_operand" "r")])
2673 (label_ref (match_operand 0 "" ""))
2677 [(set_attr "type" "ibr")])
2682 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2686 (label_ref (match_operand 0 "" ""))
2690 [(set_attr "type" "ibr")])
2695 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2699 (label_ref (match_operand 0 "" ""))
2703 [(set_attr "type" "ibr")])
2709 (match_operator 1 "comparison_operator"
2710 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
2712 (match_operand:DI 3 "const_int_operand" ""))
2714 (label_ref (match_operand 0 "" ""))
2716 (clobber (match_operand:DI 4 "register_operand" ""))])]
2717 "INTVAL (operands[3]) != 0"
2719 (lshiftrt:DI (match_dup 2) (match_dup 3)))
2721 (if_then_else (match_op_dup 1
2722 [(zero_extract:DI (match_dup 4)
2726 (label_ref (match_dup 0))
2730 ;; The following are the corresponding floating-point insns. Recall
2731 ;; we need to have variants that expand the arguments from SF mode
2735 [(set (match_operand:DF 0 "register_operand" "=&f")
2736 (match_operator:DF 1 "alpha_comparison_operator"
2737 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2738 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2739 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2740 "cmp%-%C1%' %R2,%R3,%0"
2741 [(set_attr "type" "fadd")
2742 (set_attr "trap" "yes")])
2745 [(set (match_operand:DF 0 "register_operand" "=f")
2746 (match_operator:DF 1 "alpha_comparison_operator"
2747 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2748 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2749 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2750 "cmp%-%C1%' %R2,%R3,%0"
2751 [(set_attr "type" "fadd")
2752 (set_attr "trap" "yes")])
2755 [(set (match_operand:DF 0 "register_operand" "=&f")
2756 (match_operator:DF 1 "alpha_comparison_operator"
2758 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2759 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2760 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2761 "cmp%-%C1%' %R2,%R3,%0"
2762 [(set_attr "type" "fadd")
2763 (set_attr "trap" "yes")])
2766 [(set (match_operand:DF 0 "register_operand" "=f")
2767 (match_operator:DF 1 "alpha_comparison_operator"
2769 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2770 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2771 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2772 "cmp%-%C1%' %R2,%R3,%0"
2773 [(set_attr "type" "fadd")
2774 (set_attr "trap" "yes")])
2777 [(set (match_operand:DF 0 "register_operand" "=&f")
2778 (match_operator:DF 1 "alpha_comparison_operator"
2779 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2781 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2782 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2783 "cmp%-%C1%' %R2,%R3,%0"
2784 [(set_attr "type" "fadd")
2785 (set_attr "trap" "yes")])
2788 [(set (match_operand:DF 0 "register_operand" "=f")
2789 (match_operator:DF 1 "alpha_comparison_operator"
2790 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2792 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2793 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2794 "cmp%-%C1%' %R2,%R3,%0"
2795 [(set_attr "type" "fadd")
2796 (set_attr "trap" "yes")])
2799 [(set (match_operand:DF 0 "register_operand" "=&f")
2800 (match_operator:DF 1 "alpha_comparison_operator"
2802 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2804 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2805 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2806 "cmp%-%C1%' %R2,%R3,%0"
2807 [(set_attr "type" "fadd")
2808 (set_attr "trap" "yes")])
2811 [(set (match_operand:DF 0 "register_operand" "=f")
2812 (match_operator:DF 1 "alpha_comparison_operator"
2814 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2816 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2817 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2818 "cmp%-%C1%' %R2,%R3,%0"
2819 [(set_attr "type" "fadd")
2820 (set_attr "trap" "yes")])
2823 [(set (match_operand:DF 0 "register_operand" "=f,f")
2825 (match_operator 3 "signed_comparison_operator"
2826 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2827 (match_operand:DF 2 "fp0_operand" "G,G")])
2828 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
2829 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2833 fcmov%D3 %R4,%R5,%0"
2834 [(set_attr "type" "fcmov")])
2837 [(set (match_operand:SF 0 "register_operand" "=f,f")
2839 (match_operator 3 "signed_comparison_operator"
2840 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2841 (match_operand:DF 2 "fp0_operand" "G,G")])
2842 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
2843 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
2847 fcmov%D3 %R4,%R5,%0"
2848 [(set_attr "type" "fcmov")])
2851 [(set (match_operand:DF 0 "register_operand" "=f,f")
2853 (match_operator 3 "signed_comparison_operator"
2854 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2855 (match_operand:DF 2 "fp0_operand" "G,G")])
2856 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
2857 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2861 fcmov%D3 %R4,%R5,%0"
2862 [(set_attr "type" "fcmov")])
2865 [(set (match_operand:DF 0 "register_operand" "=f,f")
2867 (match_operator 3 "signed_comparison_operator"
2869 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2870 (match_operand:DF 2 "fp0_operand" "G,G")])
2871 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
2872 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2876 fcmov%D3 %R4,%R5,%0"
2877 [(set_attr "type" "fcmov")])
2880 [(set (match_operand:SF 0 "register_operand" "=f,f")
2882 (match_operator 3 "signed_comparison_operator"
2884 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2885 (match_operand:DF 2 "fp0_operand" "G,G")])
2886 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
2887 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
2891 fcmov%D3 %R4,%R5,%0"
2892 [(set_attr "type" "fcmov")])
2895 [(set (match_operand:DF 0 "register_operand" "=f,f")
2897 (match_operator 3 "signed_comparison_operator"
2899 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2900 (match_operand:DF 2 "fp0_operand" "G,G")])
2901 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
2902 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2906 fcmov%D3 %R4,%R5,%0"
2907 [(set_attr "type" "fcmov")])
2909 (define_expand "maxdf3"
2911 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
2912 (match_operand:DF 2 "reg_or_fp0_operand" "")))
2913 (set (match_operand:DF 0 "register_operand" "")
2914 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
2915 (match_dup 1) (match_dup 2)))]
2918 { operands[3] = gen_reg_rtx (DFmode);
2919 operands[4] = CONST0_RTX (DFmode);
2922 (define_expand "mindf3"
2924 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
2925 (match_operand:DF 2 "reg_or_fp0_operand" "")))
2926 (set (match_operand:DF 0 "register_operand" "")
2927 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
2928 (match_dup 1) (match_dup 2)))]
2931 { operands[3] = gen_reg_rtx (DFmode);
2932 operands[4] = CONST0_RTX (DFmode);
2935 (define_expand "maxsf3"
2937 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
2938 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
2939 (set (match_operand:SF 0 "register_operand" "")
2940 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
2941 (match_dup 1) (match_dup 2)))]
2944 { operands[3] = gen_reg_rtx (DFmode);
2945 operands[4] = CONST0_RTX (DFmode);
2948 (define_expand "minsf3"
2950 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
2951 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
2952 (set (match_operand:SF 0 "register_operand" "")
2953 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
2954 (match_dup 1) (match_dup 2)))]
2957 { operands[3] = gen_reg_rtx (DFmode);
2958 operands[4] = CONST0_RTX (DFmode);
2964 (match_operator 1 "signed_comparison_operator"
2965 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2966 (match_operand:DF 3 "fp0_operand" "G")])
2967 (label_ref (match_operand 0 "" ""))
2971 [(set_attr "type" "fbr")])
2976 (match_operator 1 "signed_comparison_operator"
2978 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2979 (match_operand:DF 3 "fp0_operand" "G")])
2980 (label_ref (match_operand 0 "" ""))
2984 [(set_attr "type" "fbr")])
2986 ;; These are the main define_expand's used to make conditional branches
2989 (define_expand "cmpdf"
2990 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
2991 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
2995 alpha_compare_op0 = operands[0];
2996 alpha_compare_op1 = operands[1];
2997 alpha_compare_fp_p = 1;
3001 (define_expand "cmpdi"
3002 [(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "")
3003 (match_operand:DI 1 "reg_or_8bit_operand" "")))]
3007 alpha_compare_op0 = operands[0];
3008 alpha_compare_op1 = operands[1];
3009 alpha_compare_fp_p = 0;
3013 (define_expand "beq"
3015 (if_then_else (match_dup 1)
3016 (label_ref (match_operand 0 "" ""))
3019 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3021 (define_expand "bne"
3023 (if_then_else (match_dup 1)
3024 (label_ref (match_operand 0 "" ""))
3027 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3029 (define_expand "blt"
3031 (if_then_else (match_dup 1)
3032 (label_ref (match_operand 0 "" ""))
3035 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3037 (define_expand "ble"
3039 (if_then_else (match_dup 1)
3040 (label_ref (match_operand 0 "" ""))
3043 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3045 (define_expand "bgt"
3047 (if_then_else (match_dup 1)
3048 (label_ref (match_operand 0 "" ""))
3051 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3053 (define_expand "bge"
3055 (if_then_else (match_dup 1)
3056 (label_ref (match_operand 0 "" ""))
3059 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3061 (define_expand "bltu"
3063 (if_then_else (match_dup 1)
3064 (label_ref (match_operand 0 "" ""))
3067 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3069 (define_expand "bleu"
3071 (if_then_else (match_dup 1)
3072 (label_ref (match_operand 0 "" ""))
3075 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3077 (define_expand "bgtu"
3079 (if_then_else (match_dup 1)
3080 (label_ref (match_operand 0 "" ""))
3083 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3085 (define_expand "bgeu"
3087 (if_then_else (match_dup 1)
3088 (label_ref (match_operand 0 "" ""))
3091 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3093 (define_expand "seq"
3094 [(set (match_operand:DI 0 "register_operand" "")
3099 if (alpha_compare_fp_p)
3102 operands[1] = gen_rtx_EQ (DImode, alpha_compare_op0, alpha_compare_op1);
3105 (define_expand "sne"
3106 [(set (match_operand:DI 0 "register_operand" "")
3108 (set (match_dup 0) (xor:DI (match_dup 0) (const_int 1)))]
3112 if (alpha_compare_fp_p)
3115 operands[1] = gen_rtx_EQ (DImode, alpha_compare_op0, alpha_compare_op1);
3118 (define_expand "slt"
3119 [(set (match_operand:DI 0 "register_operand" "")
3124 if (alpha_compare_fp_p)
3127 operands[1] = gen_rtx_LT (DImode, alpha_compare_op0, alpha_compare_op1);
3130 (define_expand "sle"
3131 [(set (match_operand:DI 0 "register_operand" "")
3136 if (alpha_compare_fp_p)
3139 operands[1] = gen_rtx_LE (DImode, alpha_compare_op0, alpha_compare_op1);
3142 (define_expand "sgt"
3143 [(set (match_operand:DI 0 "register_operand" "")
3148 if (alpha_compare_fp_p)
3151 operands[1] = gen_rtx_LT (DImode, force_reg (DImode, alpha_compare_op1),
3155 (define_expand "sge"
3156 [(set (match_operand:DI 0 "register_operand" "")
3161 if (alpha_compare_fp_p)
3164 operands[1] = gen_rtx_LE (DImode, force_reg (DImode, alpha_compare_op1),
3168 (define_expand "sltu"
3169 [(set (match_operand:DI 0 "register_operand" "")
3174 if (alpha_compare_fp_p)
3177 operands[1] = gen_rtx_LTU (DImode, alpha_compare_op0, alpha_compare_op1);
3180 (define_expand "sleu"
3181 [(set (match_operand:DI 0 "register_operand" "")
3186 if (alpha_compare_fp_p)
3189 operands[1] = gen_rtx_LEU (DImode, alpha_compare_op0, alpha_compare_op1);
3192 (define_expand "sgtu"
3193 [(set (match_operand:DI 0 "register_operand" "")
3198 if (alpha_compare_fp_p)
3201 operands[1] = gen_rtx_LTU (DImode, force_reg (DImode, alpha_compare_op1),
3205 (define_expand "sgeu"
3206 [(set (match_operand:DI 0 "register_operand" "")
3211 if (alpha_compare_fp_p)
3214 operands[1] = gen_rtx_LEU (DImode, force_reg (DImode, alpha_compare_op1),
3218 ;; These are the main define_expand's used to make conditional moves.
3220 (define_expand "movsicc"
3221 [(set (match_operand:SI 0 "register_operand" "")
3222 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3223 (match_operand:SI 2 "reg_or_8bit_operand" "")
3224 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3228 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3232 (define_expand "movdicc"
3233 [(set (match_operand:DI 0 "register_operand" "")
3234 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3235 (match_operand:DI 2 "reg_or_8bit_operand" "")
3236 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3240 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3244 (define_expand "movsfcc"
3245 [(set (match_operand:SF 0 "register_operand" "")
3246 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3247 (match_operand:SF 2 "reg_or_8bit_operand" "")
3248 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3252 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3256 (define_expand "movdfcc"
3257 [(set (match_operand:DF 0 "register_operand" "")
3258 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3259 (match_operand:DF 2 "reg_or_8bit_operand" "")
3260 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3264 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3268 ;; These define_split definitions are used in cases when comparisons have
3269 ;; not be stated in the correct way and we need to reverse the second
3270 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3271 ;; comparison that tests the result being reversed. We have one define_split
3272 ;; for each use of a comparison. They do not match valid insns and need
3273 ;; not generate valid insns.
3275 ;; We can also handle equality comparisons (and inequality comparisons in
3276 ;; cases where the resulting add cannot overflow) by doing an add followed by
3277 ;; a comparison with zero. This is faster since the addition takes one
3278 ;; less cycle than a compare when feeding into a conditional move.
3279 ;; For this case, we also have an SImode pattern since we can merge the add
3280 ;; and sign extend and the order doesn't matter.
3282 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3283 ;; operation could have been generated.
3286 [(set (match_operand:DI 0 "register_operand" "")
3288 (match_operator 1 "comparison_operator"
3289 [(match_operand:DI 2 "reg_or_0_operand" "")
3290 (match_operand:DI 3 "reg_or_cint_operand" "")])
3291 (match_operand:DI 4 "reg_or_cint_operand" "")
3292 (match_operand:DI 5 "reg_or_cint_operand" "")))
3293 (clobber (match_operand:DI 6 "register_operand" ""))]
3294 "operands[3] != const0_rtx"
3295 [(set (match_dup 6) (match_dup 7))
3297 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3299 { enum rtx_code code = GET_CODE (operands[1]);
3300 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3302 /* If we are comparing for equality with a constant and that constant
3303 appears in the arm when the register equals the constant, use the
3304 register since that is more likely to match (and to produce better code
3307 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3308 && rtx_equal_p (operands[4], operands[3]))
3309 operands[4] = operands[2];
3311 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3312 && rtx_equal_p (operands[5], operands[3]))
3313 operands[5] = operands[2];
3315 if (code == NE || code == EQ
3316 || (extended_count (operands[2], DImode, unsignedp) >= 1
3317 && extended_count (operands[3], DImode, unsignedp) >= 1))
3319 if (GET_CODE (operands[3]) == CONST_INT)
3320 operands[7] = gen_rtx_PLUS (DImode, operands[2],
3321 GEN_INT (- INTVAL (operands[3])));
3323 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3325 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
3328 else if (code == EQ || code == LE || code == LT
3329 || code == LEU || code == LTU)
3331 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3332 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
3336 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3337 operands[2], operands[3]);
3338 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3343 [(set (match_operand:DI 0 "register_operand" "")
3345 (match_operator 1 "comparison_operator"
3346 [(match_operand:SI 2 "reg_or_0_operand" "")
3347 (match_operand:SI 3 "reg_or_cint_operand" "")])
3348 (match_operand:DI 4 "reg_or_8bit_operand" "")
3349 (match_operand:DI 5 "reg_or_8bit_operand" "")))
3350 (clobber (match_operand:DI 6 "register_operand" ""))]
3351 "operands[3] != const0_rtx
3352 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3353 [(set (match_dup 6) (match_dup 7))
3355 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3357 { enum rtx_code code = GET_CODE (operands[1]);
3358 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3361 if ((code != NE && code != EQ
3362 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
3363 && extended_count (operands[3], DImode, unsignedp) >= 1)))
3366 if (GET_CODE (operands[3]) == CONST_INT)
3367 tem = gen_rtx_PLUS (SImode, operands[2],
3368 GEN_INT (- INTVAL (operands[3])));
3370 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3372 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
3373 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3374 operands[6], const0_rtx);
3380 (match_operator 1 "comparison_operator"
3381 [(match_operand:DI 2 "reg_or_0_operand" "")
3382 (match_operand:DI 3 "reg_or_cint_operand" "")])
3383 (label_ref (match_operand 0 "" ""))
3385 (clobber (match_operand:DI 4 "register_operand" ""))]
3386 "operands[3] != const0_rtx"
3387 [(set (match_dup 4) (match_dup 5))
3388 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3390 { enum rtx_code code = GET_CODE (operands[1]);
3391 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3393 if (code == NE || code == EQ
3394 || (extended_count (operands[2], DImode, unsignedp) >= 1
3395 && extended_count (operands[3], DImode, unsignedp) >= 1))
3397 if (GET_CODE (operands[3]) == CONST_INT)
3398 operands[5] = gen_rtx_PLUS (DImode, operands[2],
3399 GEN_INT (- INTVAL (operands[3])));
3401 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3403 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
3406 else if (code == EQ || code == LE || code == LT
3407 || code == LEU || code == LTU)
3409 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3410 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
3414 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3415 operands[2], operands[3]);
3416 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
3423 (match_operator 1 "comparison_operator"
3424 [(match_operand:SI 2 "reg_or_0_operand" "")
3425 (match_operand:SI 3 "const_int_operand" "")])
3426 (label_ref (match_operand 0 "" ""))
3428 (clobber (match_operand:DI 4 "register_operand" ""))]
3429 "operands[3] != const0_rtx
3430 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3431 [(set (match_dup 4) (match_dup 5))
3432 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3436 if (GET_CODE (operands[3]) == CONST_INT)
3437 tem = gen_rtx_PLUS (SImode, operands[2],
3438 GEN_INT (- INTVAL (operands[3])));
3440 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3442 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
3443 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3444 operands[4], const0_rtx);
3447 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
3448 ;; This eliminates one, and sometimes two, insns when the AND can be done
3451 [(set (match_operand:DI 0 "register_operand" "")
3452 (match_operator 1 "comparison_operator"
3453 [(match_operand:DI 2 "register_operand" "")
3454 (match_operand:DI 3 "const_int_operand" "")]))
3455 (clobber (match_operand:DI 4 "register_operand" ""))]
3456 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
3457 && (GET_CODE (operands[1]) == GTU
3458 || GET_CODE (operands[1]) == LEU
3459 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
3460 && extended_count (operands[2], DImode, 1) > 0))"
3461 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
3462 (set (match_dup 0) (match_dup 6))]
3465 operands[5] = GEN_INT (~ INTVAL (operands[3]));
3466 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
3467 || GET_CODE (operands[1]) == GT)
3469 DImode, operands[4], const0_rtx);
3472 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
3473 ;; work differently, so we have different patterns for each.
3475 (define_expand "call"
3476 [(use (match_operand:DI 0 "" ""))
3477 (use (match_operand 1 "" ""))
3478 (use (match_operand 2 "" ""))
3479 (use (match_operand 3 "" ""))]
3482 { if (TARGET_WINDOWS_NT)
3483 emit_call_insn (gen_call_nt (operands[0], operands[1]));
3484 else if (TARGET_OPEN_VMS)
3485 emit_call_insn (gen_call_vms (operands[0], operands[2]));
3487 emit_call_insn (gen_call_osf (operands[0], operands[1]));
3492 (define_expand "call_osf"
3493 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3494 (match_operand 1 "" ""))
3495 (clobber (reg:DI 27))
3496 (clobber (reg:DI 26))])]
3499 { if (GET_CODE (operands[0]) != MEM)
3502 operands[0] = XEXP (operands[0], 0);
3504 if (GET_CODE (operands[0]) != SYMBOL_REF
3505 && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
3507 rtx tem = gen_rtx_REG (DImode, 27);
3508 emit_move_insn (tem, operands[0]);
3513 (define_expand "call_nt"
3514 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3515 (match_operand 1 "" ""))
3516 (clobber (reg:DI 26))])]
3519 { if (GET_CODE (operands[0]) != MEM)
3522 operands[0] = XEXP (operands[0], 0);
3523 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
3524 operands[0] = force_reg (DImode, operands[0]);
3528 ;; call openvms/alpha
3529 ;; op 0: symbol ref for called function
3530 ;; op 1: next_arg_reg (argument information value for R25)
3532 (define_expand "call_vms"
3533 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3534 (match_operand 1 "" ""))
3538 (clobber (reg:DI 27))])]
3541 { if (GET_CODE (operands[0]) != MEM)
3544 operands[0] = XEXP (operands[0], 0);
3546 /* Always load AI with argument information, then handle symbolic and
3547 indirect call differently. Load RA and set operands[2] to PV in
3550 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
3551 if (GET_CODE (operands[0]) == SYMBOL_REF)
3553 extern char *savealloc ();
3554 char *linksym, *symbol = XSTR (operands[0], 0);
3559 linksym = savealloc (strlen (symbol) + 6);
3561 alpha_need_linkage (symbol, 0);
3564 strcpy (linksym+1, symbol);
3565 strcat (linksym, \"..lk\");
3566 linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
3568 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
3571 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
3575 emit_move_insn (gen_rtx_REG (Pmode, 26),
3576 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
3578 operands[2] = operands[0];
3583 (define_expand "call_value"
3584 [(use (match_operand 0 "" ""))
3585 (use (match_operand:DI 1 "" ""))
3586 (use (match_operand 2 "" ""))
3587 (use (match_operand 3 "" ""))
3588 (use (match_operand 4 "" ""))]
3591 { if (TARGET_WINDOWS_NT)
3592 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
3593 else if (TARGET_OPEN_VMS)
3594 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
3597 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
3602 (define_expand "call_value_osf"
3603 [(parallel [(set (match_operand 0 "" "")
3604 (call (mem:DI (match_operand 1 "" ""))
3605 (match_operand 2 "" "")))
3606 (clobber (reg:DI 27))
3607 (clobber (reg:DI 26))])]
3610 { if (GET_CODE (operands[1]) != MEM)
3613 operands[1] = XEXP (operands[1], 0);
3615 if (GET_CODE (operands[1]) != SYMBOL_REF
3616 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
3618 rtx tem = gen_rtx_REG (DImode, 27);
3619 emit_move_insn (tem, operands[1]);
3624 (define_expand "call_value_nt"
3625 [(parallel [(set (match_operand 0 "" "")
3626 (call (mem:DI (match_operand 1 "" ""))
3627 (match_operand 2 "" "")))
3628 (clobber (reg:DI 26))])]
3631 { if (GET_CODE (operands[1]) != MEM)
3634 operands[1] = XEXP (operands[1], 0);
3635 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
3636 operands[1] = force_reg (DImode, operands[1]);
3639 (define_expand "call_value_vms"
3640 [(parallel [(set (match_operand 0 "" "")
3641 (call (mem:DI (match_operand:DI 1 "" ""))
3642 (match_operand 2 "" "")))
3646 (clobber (reg:DI 27))])]
3649 { if (GET_CODE (operands[1]) != MEM)
3652 operands[1] = XEXP (operands[1], 0);
3654 /* Always load AI with argument information, then handle symbolic and
3655 indirect call differently. Load RA and set operands[3] to PV in
3658 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
3659 if (GET_CODE (operands[1]) == SYMBOL_REF)
3661 extern char *savealloc ();
3662 char *linksym, *symbol = XSTR (operands[1], 0);
3667 linksym = savealloc (strlen (symbol) + 6);
3669 alpha_need_linkage (symbol, 0);
3671 strcpy (linksym+1, symbol);
3672 strcat (linksym, \"..lk\");
3673 linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
3675 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
3678 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
3682 emit_move_insn (gen_rtx_REG (Pmode, 26),
3683 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
3685 operands[3] = operands[1];
3690 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
3691 (match_operand 1 "" ""))
3692 (clobber (reg:DI 27))
3693 (clobber (reg:DI 26))]
3694 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
3696 jsr $26,($27),0\;ldgp $29,0($26)
3698 jsr $26,%0\;ldgp $29,0($26)"
3699 [(set_attr "type" "jsr")
3700 (set_attr "length" "12,*,12")])
3703 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
3704 (match_operand 1 "" ""))
3705 (clobber (reg:DI 26))]
3711 [(set_attr "type" "jsr")
3712 (set_attr "length" "*,*,12")])
3715 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
3716 (match_operand 1 "" ""))
3717 (use (match_operand:DI 2 "general_operand" "r,m"))
3720 (clobber (reg:DI 27))]
3723 bis %2,%2,$27\;jsr $26,0\;ldq $27,0($29)
3724 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
3725 [(set_attr "type" "jsr")
3726 (set_attr "length" "12,16")])
3729 [(set (match_operand 0 "register_operand" "=rf,rf,rf")
3730 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
3731 (match_operand 2 "" "")))
3732 (clobber (reg:DI 27))
3733 (clobber (reg:DI 26))]
3734 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
3736 jsr $26,($27),0\;ldgp $29,0($26)
3738 jsr $26,%1\;ldgp $29,0($26)"
3739 [(set_attr "type" "jsr")
3740 (set_attr "length" "12,*,12")])
3743 [(set (match_operand 0 "register_operand" "=rf,rf,rf")
3744 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
3745 (match_operand 2 "" "")))
3746 (clobber (reg:DI 26))]
3752 [(set_attr "type" "jsr")
3753 (set_attr "length" "*,*,12")])
3756 [(set (match_operand 0 "register_operand" "")
3757 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
3758 (match_operand 2 "" "")))
3759 (use (match_operand:DI 3 "general_operand" "r,m"))
3762 (clobber (reg:DI 27))]
3765 bis %3,%3,$27\;jsr $26,0\;ldq $27,0($29)
3766 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
3767 [(set_attr "type" "jsr")
3768 (set_attr "length" "12,16")])
3770 ;; Call subroutine returning any type.
3772 (define_expand "untyped_call"
3773 [(parallel [(call (match_operand 0 "" "")
3775 (match_operand 1 "" "")
3776 (match_operand 2 "" "")])]
3782 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
3784 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3786 rtx set = XVECEXP (operands[2], 0, i);
3787 emit_move_insn (SET_DEST (set), SET_SRC (set));
3790 /* The optimizer does not know that the call sets the function value
3791 registers we stored in the result block. We avoid problems by
3792 claiming that all hard registers are used and clobbered at this
3794 emit_insn (gen_blockage ());
3799 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
3800 ;; all of memory. This blocks insns from being moved across this point.
3802 (define_insn "blockage"
3803 [(unspec_volatile [(const_int 0)] 1)]
3806 [(set_attr "length" "0")])
3810 (label_ref (match_operand 0 "" "")))]
3813 [(set_attr "type" "ibr")])
3815 (define_insn "return"
3819 [(set_attr "type" "ibr")])
3821 ;; Use a different pattern for functions which have non-trivial
3822 ;; epilogues so as not to confuse jump and reorg.
3823 (define_insn "return_internal"
3828 [(set_attr "type" "ibr")])
3830 (define_insn "indirect_jump"
3831 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
3834 [(set_attr "type" "ibr")])
3840 [(set_attr "type" "ilog")])
3842 (define_expand "tablejump"
3843 [(use (match_operand:SI 0 "register_operand" ""))
3844 (use (match_operand:SI 1 "" ""))]
3848 if (TARGET_WINDOWS_NT)
3849 emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
3850 else if (TARGET_OPEN_VMS)
3851 emit_jump_insn (gen_tablejump_vms (operands[0], operands[1]));
3853 emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
3858 (define_expand "tablejump_osf"
3860 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
3861 (parallel [(set (pc)
3862 (plus:DI (match_dup 3)
3863 (label_ref:DI (match_operand 1 "" ""))))
3864 (clobber (match_scratch:DI 2 "=r"))])]
3867 { operands[3] = gen_reg_rtx (DImode); }")
3869 (define_expand "tablejump_nt"
3871 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
3872 (parallel [(set (pc)
3874 (use (label_ref (match_operand 1 "" "")))])]
3877 { operands[3] = gen_reg_rtx (DImode); }")
3880 ;; tablejump, openVMS way
3882 ;; op 1: label preceding jump-table
3884 (define_expand "tablejump_vms"
3886 (match_operand:DI 0 "register_operand" ""))
3888 (plus:DI (match_dup 2)
3889 (label_ref:DI (match_operand 1 "" ""))))]
3892 { operands[2] = gen_reg_rtx (DImode); }")
3896 (plus:DI (match_operand:DI 0 "register_operand" "r")
3897 (label_ref:DI (match_operand 1 "" ""))))
3898 (clobber (match_scratch:DI 2 "=r"))]
3899 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && next_active_insn (insn) != 0
3900 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
3901 && PREV_INSN (next_active_insn (insn)) == operands[1]"
3903 { rtx best_label = 0;
3904 rtx jump_table_insn = next_active_insn (operands[1]);
3906 if (GET_CODE (jump_table_insn) == JUMP_INSN
3907 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
3909 rtx jump_table = PATTERN (jump_table_insn);
3910 int n_labels = XVECLEN (jump_table, 1);
3911 int best_count = -1;
3914 for (i = 0; i < n_labels; i++)
3918 for (j = i + 1; j < n_labels; j++)
3919 if (XEXP (XVECEXP (jump_table, 1, i), 0)
3920 == XEXP (XVECEXP (jump_table, 1, j), 0))
3923 if (count > best_count)
3924 best_count = count, best_label = XVECEXP (jump_table, 1, i);
3930 operands[3] = best_label;
3931 return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
3934 return \"addq %0,$29,%2\;jmp $31,(%2),0\";
3936 [(set_attr "type" "ibr")
3937 (set_attr "length" "8")])
3941 (match_operand:DI 0 "register_operand" "r"))
3942 (use (label_ref (match_operand 1 "" "")))]
3943 "TARGET_WINDOWS_NT && next_active_insn (insn) != 0
3944 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
3945 && PREV_INSN (next_active_insn (insn)) == operands[1]"
3947 { rtx best_label = 0;
3948 rtx jump_table_insn = next_active_insn (operands[1]);
3950 if (GET_CODE (jump_table_insn) == JUMP_INSN
3951 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
3953 rtx jump_table = PATTERN (jump_table_insn);
3954 int n_labels = XVECLEN (jump_table, 1);
3955 int best_count = -1;
3958 for (i = 0; i < n_labels; i++)
3962 for (j = i + 1; j < n_labels; j++)
3963 if (XEXP (XVECEXP (jump_table, 1, i), 0)
3964 == XEXP (XVECEXP (jump_table, 1, j), 0))
3967 if (count > best_count)
3968 best_count = count, best_label = XVECEXP (jump_table, 1, i);
3974 operands[2] = best_label;
3975 return \"jmp $31,(%0),%2\";
3978 return \"jmp $31,(%0),0\";
3980 [(set_attr "type" "ibr")])
3983 ;; op 0 is table offset
3984 ;; op 1 is table label
3989 (plus:DI (match_operand 0 "register_operand" "r")
3990 (label_ref (match_operand 1 "" ""))))]
3993 [(set_attr "type" "ibr")])
3995 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
3996 ;; want to have to include pal.h in our .s file.
3998 ;; Technically the type for call_pal is jsr, but we use that for determining
3999 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4002 [(unspec_volatile [(const_int 0)] 0)]
4005 [(set_attr "type" "ibr")])
4007 ;; Finally, we have the basic data motion insns. The byte and word insns
4008 ;; are done via define_expand. Start with the floating-point insns, since
4009 ;; they are simpler.
4012 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
4013 (match_operand:SF 1 "input_operand" "rG,m,rG,f,G,m,fG"))]
4015 && (register_operand (operands[0], SFmode)
4016 || reg_or_fp0_operand (operands[1], SFmode))"
4025 [(set_attr "type" "ilog,ild,ist,fcpys,fcpys,fld,fst")])
4028 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m,f,*r")
4029 (match_operand:SF 1 "input_operand" "rG,m,rG,f,G,m,fG,r,*f"))]
4031 && (register_operand (operands[0], SFmode)
4032 || reg_or_fp0_operand (operands[1], SFmode))"
4043 [(set_attr "type" "ilog,ild,ist,fcpys,fcpys,fld,fst,itof,ftoi")])
4046 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
4047 (match_operand:DF 1 "input_operand" "rG,m,rG,f,G,m,fG"))]
4049 && (register_operand (operands[0], DFmode)
4050 || reg_or_fp0_operand (operands[1], DFmode))"
4059 [(set_attr "type" "ilog,ild,ist,fcpys,fcpys,fld,fst")])
4062 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m,f,*r")
4063 (match_operand:DF 1 "input_operand" "rG,m,rG,f,G,m,fG,r,*f"))]
4065 && (register_operand (operands[0], DFmode)
4066 || reg_or_fp0_operand (operands[1], DFmode))"
4077 [(set_attr "type" "ilog,ild,ist,fcpys,fcpys,fld,fst,itof,ftoi")])
4079 (define_expand "movsf"
4080 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4081 (match_operand:SF 1 "general_operand" ""))]
4085 if (GET_CODE (operands[0]) == MEM
4086 && ! reg_or_fp0_operand (operands[1], SFmode))
4087 operands[1] = force_reg (SFmode, operands[1]);
4090 (define_expand "movdf"
4091 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4092 (match_operand:DF 1 "general_operand" ""))]
4096 if (GET_CODE (operands[0]) == MEM
4097 && ! reg_or_fp0_operand (operands[1], DFmode))
4098 operands[1] = force_reg (DFmode, operands[1]);
4102 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,f,f,f,m")
4103 (match_operand:SI 1 "input_operand" "r,J,I,K,L,m,rJ,f,J,m,fG"))]
4104 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_CIX
4105 && (register_operand (operands[0], SImode)
4106 || reg_or_0_operand (operands[1], SImode))"
4119 [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ild,ist,fcpys,fcpys,fld,fst")])
4122 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,f,f,f,m,r,*f")
4123 (match_operand:SI 1 "input_operand" "r,J,I,K,L,m,rJ,f,J,m,fG,f,*r"))]
4124 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_CIX
4125 && (register_operand (operands[0], SImode)
4126 || reg_or_0_operand (operands[1], SImode))"
4141 [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ild,ist,fcpys,fcpys,fld,fst,ftoi,itof")])
4144 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,f,f,f,m")
4145 (match_operand:SI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,m,fG"))]
4146 "(TARGET_WINDOWS_NT || TARGET_OPEN_VMS)
4147 && (register_operand (operands[0], SImode)
4148 || reg_or_0_operand (operands[1], SImode))"
4162 [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ldsym,ild,ist,fcpys,fcpys,fld,fst")])
4165 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,f,f")
4166 (match_operand:HI 1 "input_operand" "r,J,I,n,f,J"))]
4168 && (register_operand (operands[0], HImode)
4169 || register_operand (operands[1], HImode))"
4177 [(set_attr "type" "ilog,ilog,ilog,iadd,fcpys,fcpys")])
4180 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f")
4181 (match_operand:HI 1 "input_operand" "r,J,I,n,m,rJ,f,J"))]
4183 && (register_operand (operands[0], HImode)
4184 || reg_or_0_operand (operands[1], HImode))"
4194 [(set_attr "type" "ilog,ilog,ilog,iadd,ild,ist,fcpys,fcpys")])
4197 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,f,f")
4198 (match_operand:QI 1 "input_operand" "r,J,I,n,f,J"))]
4200 && (register_operand (operands[0], QImode)
4201 || register_operand (operands[1], QImode))"
4209 [(set_attr "type" "ilog,ilog,ilog,iadd,fcpys,fcpys")])
4212 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f")
4213 (match_operand:QI 1 "input_operand" "r,J,I,n,m,rJ,f,J"))]
4215 && (register_operand (operands[0], QImode)
4216 || reg_or_0_operand (operands[1], QImode))"
4226 [(set_attr "type" "ilog,ilog,ilog,iadd,ild,ist,fcpys,fcpys")])
4228 ;; We do two major things here: handle mem->mem and construct long
4231 (define_expand "movsi"
4232 [(set (match_operand:SI 0 "general_operand" "")
4233 (match_operand:SI 1 "general_operand" ""))]
4237 if (GET_CODE (operands[0]) == MEM
4238 && ! reg_or_0_operand (operands[1], SImode))
4239 operands[1] = force_reg (SImode, operands[1]);
4241 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
4243 else if (GET_CODE (operands[1]) == CONST_INT)
4246 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
4247 if (rtx_equal_p (operands[0], operands[1]))
4252 ;; Split a load of a large constant into the appropriate two-insn
4256 [(set (match_operand:SI 0 "register_operand" "")
4257 (match_operand:SI 1 "const_int_operand" ""))]
4258 "! add_operand (operands[1], SImode)"
4259 [(set (match_dup 0) (match_dup 2))
4260 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
4263 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
4265 if (tem == operands[0])
4272 [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,r,r,m,f,f,f,Q")
4273 (match_operand:DI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,Q,fG"))]
4275 && (register_operand (operands[0], DImode)
4276 || reg_or_0_operand (operands[1], DImode))"
4290 [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ldsym,ild,ist,fcpys,fcpys,fld,fst")])
4293 [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,r,r,m,f,f,f,Q,r,*f")
4294 (match_operand:DI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,Q,fG,f,*r"))]
4296 && (register_operand (operands[0], DImode)
4297 || reg_or_0_operand (operands[1], DImode))"
4313 [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ldsym,ild,ist,fcpys,fcpys,fld,fst,ftoi,itof")])
4315 ;; We do three major things here: handle mem->mem, put 64-bit constants in
4316 ;; memory, and construct long 32-bit constants.
4318 (define_expand "movdi"
4319 [(set (match_operand:DI 0 "general_operand" "")
4320 (match_operand:DI 1 "general_operand" ""))]
4326 if (GET_CODE (operands[0]) == MEM
4327 && ! reg_or_0_operand (operands[1], DImode))
4328 operands[1] = force_reg (DImode, operands[1]);
4330 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
4332 else if (GET_CODE (operands[1]) == CONST_INT
4333 && (tem = alpha_emit_set_const (operands[0], DImode,
4334 INTVAL (operands[1]), 3)) != 0)
4336 if (rtx_equal_p (tem, operands[0]))
4341 else if (CONSTANT_P (operands[1]))
4343 if (TARGET_BUILD_CONSTANTS)
4345 #if HOST_BITS_PER_WIDE_INT == 64
4348 if (GET_CODE (operands[1]) == CONST_INT)
4349 i = INTVAL (operands[1]);
4350 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
4351 i = CONST_DOUBLE_LOW (operands[1]);
4355 tem = alpha_emit_set_long_const (operands[0], i);
4356 if (rtx_equal_p (tem, operands[0]))
4366 operands[1] = force_const_mem (DImode, operands[1]);
4367 if (reload_in_progress)
4369 emit_move_insn (operands[0], XEXP (operands[1], 0));
4370 operands[1] = copy_rtx (operands[1]);
4371 XEXP (operands[1], 0) = operands[0];
4374 operands[1] = validize_mem (operands[1]);
4381 ;; Split a load of a large constant into the appropriate two-insn
4385 [(set (match_operand:DI 0 "register_operand" "")
4386 (match_operand:DI 1 "const_int_operand" ""))]
4387 "! add_operand (operands[1], DImode)"
4388 [(set (match_dup 0) (match_dup 2))
4389 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
4392 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
4394 if (tem == operands[0])
4400 ;; These are the partial-word cases.
4402 ;; First we have the code to load an aligned word. Operand 0 is the register
4403 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
4404 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
4405 ;; number of bits within the word that the value is. Operand 3 is an SImode
4406 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
4407 ;; same register. It is allowed to conflict with operand 1 as well.
4409 (define_expand "aligned_loadqi"
4410 [(set (match_operand:SI 3 "register_operand" "")
4411 (match_operand:SI 1 "memory_operand" ""))
4412 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4413 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4415 (match_operand:DI 2 "const_int_operand" "")))]
4420 (define_expand "aligned_loadhi"
4421 [(set (match_operand:SI 3 "register_operand" "")
4422 (match_operand:SI 1 "memory_operand" ""))
4423 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
4424 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4426 (match_operand:DI 2 "const_int_operand" "")))]
4431 ;; Similar for unaligned loads, where we use the sequence from the
4432 ;; Alpha Architecture manual.
4434 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
4435 ;; operand 3 can overlap the input and output registers.
4437 (define_expand "unaligned_loadqi"
4438 [(set (match_operand:DI 2 "register_operand" "")
4439 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4441 (set (match_operand:DI 3 "register_operand" "")
4443 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4444 (zero_extract:DI (match_dup 2)
4446 (ashift:DI (match_dup 3) (const_int 3))))]
4450 (define_expand "unaligned_loadhi"
4451 [(set (match_operand:DI 2 "register_operand" "")
4452 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4454 (set (match_operand:DI 3 "register_operand" "")
4456 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4457 (zero_extract:DI (match_dup 2)
4459 (ashift:DI (match_dup 3) (const_int 3))))]
4463 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
4464 ;; aligned SImode MEM. Operand 1 is the register containing the
4465 ;; byte or word to store. Operand 2 is the number of bits within the word that
4466 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
4468 (define_expand "aligned_store"
4469 [(set (match_operand:SI 3 "register_operand" "")
4470 (match_operand:SI 0 "memory_operand" ""))
4471 (set (subreg:DI (match_dup 3) 0)
4472 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
4473 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
4474 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
4475 (match_operand:DI 2 "const_int_operand" "")))
4476 (set (subreg:DI (match_dup 4) 0)
4477 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
4478 (set (match_dup 0) (match_dup 4))]
4481 { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
4482 << INTVAL (operands[2])));
4485 ;; For the unaligned byte and halfword cases, we use code similar to that
4486 ;; in the ;; Architecture book, but reordered to lower the number of registers
4487 ;; required. Operand 0 is the address. Operand 1 is the data to store.
4488 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
4489 ;; be the same temporary, if desired. If the address is in a register,
4490 ;; operand 2 can be that register.
4492 (define_expand "unaligned_storeqi"
4493 [(set (match_operand:DI 3 "register_operand" "")
4494 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
4496 (set (match_operand:DI 2 "register_operand" "")
4499 (and:DI (not:DI (ashift:DI (const_int 255)
4500 (ashift:DI (match_dup 2) (const_int 3))))
4502 (set (match_operand:DI 4 "register_operand" "")
4503 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
4504 (ashift:DI (match_dup 2) (const_int 3))))
4505 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
4506 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
4511 (define_expand "unaligned_storehi"
4512 [(set (match_operand:DI 3 "register_operand" "")
4513 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
4515 (set (match_operand:DI 2 "register_operand" "")
4518 (and:DI (not:DI (ashift:DI (const_int 65535)
4519 (ashift:DI (match_dup 2) (const_int 3))))
4521 (set (match_operand:DI 4 "register_operand" "")
4522 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
4523 (ashift:DI (match_dup 2) (const_int 3))))
4524 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
4525 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
4530 ;; Here are the define_expand's for QI and HI moves that use the above
4531 ;; patterns. We have the normal sets, plus the ones that need scratch
4532 ;; registers for reload.
4534 (define_expand "movqi"
4535 [(set (match_operand:QI 0 "general_operand" "")
4536 (match_operand:QI 1 "general_operand" ""))]
4542 if (GET_CODE (operands[0]) == MEM
4543 && ! reg_or_0_operand (operands[1], QImode))
4544 operands[1] = force_reg (QImode, operands[1]);
4546 if (GET_CODE (operands[1]) == CONST_INT
4547 && ! input_operand (operands[1], QImode))
4549 operands[1] = alpha_emit_set_const (operands[0], QImode,
4550 INTVAL (operands[1]), 3);
4552 if (rtx_equal_p (operands[0], operands[1]))
4559 /* If the output is not a register, the input must be. */
4560 if (GET_CODE (operands[0]) == MEM)
4561 operands[1] = force_reg (QImode, operands[1]);
4563 /* Handle four memory cases, unaligned and aligned for either the input
4564 or the output. The only case where we can be called during reload is
4565 for aligned loads; all other cases require temporaries. */
4567 if (GET_CODE (operands[1]) == MEM
4568 || (GET_CODE (operands[1]) == SUBREG
4569 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
4570 || (reload_in_progress && GET_CODE (operands[1]) == REG
4571 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
4572 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
4573 && GET_CODE (SUBREG_REG (operands[1])) == REG
4574 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
4576 if (aligned_memory_operand (operands[1], QImode))
4578 rtx aligned_mem, bitnum;
4579 rtx scratch = (reload_in_progress
4580 ? gen_rtx_REG (SImode, REGNO (operands[0]))
4581 : gen_reg_rtx (SImode));
4583 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4585 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
4590 /* Don't pass these as parameters since that makes the generated
4591 code depend on parameter evaluation order which will cause
4592 bootstrap failures. */
4594 rtx temp1 = gen_reg_rtx (DImode);
4595 rtx temp2 = gen_reg_rtx (DImode);
4597 = gen_unaligned_loadqi (operands[0],
4598 get_unaligned_address (operands[1], 0),
4601 alpha_set_memflags (seq, operands[1]);
4608 else if (GET_CODE (operands[0]) == MEM
4609 || (GET_CODE (operands[0]) == SUBREG
4610 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
4611 || (reload_in_progress && GET_CODE (operands[0]) == REG
4612 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
4613 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
4614 && GET_CODE (SUBREG_REG (operands[0])) == REG
4615 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
4617 if (aligned_memory_operand (operands[0], QImode))
4619 rtx aligned_mem, bitnum;
4620 rtx temp1 = gen_reg_rtx (SImode);
4621 rtx temp2 = gen_reg_rtx (SImode);
4623 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4625 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4630 rtx temp1 = gen_reg_rtx (DImode);
4631 rtx temp2 = gen_reg_rtx (DImode);
4632 rtx temp3 = gen_reg_rtx (DImode);
4634 = gen_unaligned_storeqi (get_unaligned_address (operands[0], 0),
4635 operands[1], temp1, temp2, temp3);
4637 alpha_set_memflags (seq, operands[0]);
4645 (define_expand "movhi"
4646 [(set (match_operand:HI 0 "general_operand" "")
4647 (match_operand:HI 1 "general_operand" ""))]
4653 if (GET_CODE (operands[0]) == MEM
4654 && ! reg_or_0_operand (operands[1], HImode))
4655 operands[1] = force_reg (HImode, operands[1]);
4657 if (GET_CODE (operands[1]) == CONST_INT
4658 && ! input_operand (operands[1], HImode))
4660 operands[1] = alpha_emit_set_const (operands[0], HImode,
4661 INTVAL (operands[1]), 3);
4663 if (rtx_equal_p (operands[0], operands[1]))
4670 /* If the output is not a register, the input must be. */
4671 if (GET_CODE (operands[0]) == MEM)
4672 operands[1] = force_reg (HImode, operands[1]);
4674 /* Handle four memory cases, unaligned and aligned for either the input
4675 or the output. The only case where we can be called during reload is
4676 for aligned loads; all other cases require temporaries. */
4678 if (GET_CODE (operands[1]) == MEM
4679 || (GET_CODE (operands[1]) == SUBREG
4680 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
4681 || (reload_in_progress && GET_CODE (operands[1]) == REG
4682 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
4683 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
4684 && GET_CODE (SUBREG_REG (operands[1])) == REG
4685 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
4687 if (aligned_memory_operand (operands[1], HImode))
4689 rtx aligned_mem, bitnum;
4690 rtx scratch = (reload_in_progress
4691 ? gen_rtx_REG (SImode, REGNO (operands[0]))
4692 : gen_reg_rtx (SImode));
4694 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4696 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
4701 /* Don't pass these as parameters since that makes the generated
4702 code depend on parameter evaluation order which will cause
4703 bootstrap failures. */
4705 rtx temp1 = gen_reg_rtx (DImode);
4706 rtx temp2 = gen_reg_rtx (DImode);
4708 = gen_unaligned_loadhi (operands[0],
4709 get_unaligned_address (operands[1], 0),
4712 alpha_set_memflags (seq, operands[1]);
4719 else if (GET_CODE (operands[0]) == MEM
4720 || (GET_CODE (operands[0]) == SUBREG
4721 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
4722 || (reload_in_progress && GET_CODE (operands[0]) == REG
4723 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
4724 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
4725 && GET_CODE (SUBREG_REG (operands[0])) == REG
4726 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
4728 if (aligned_memory_operand (operands[0], HImode))
4730 rtx aligned_mem, bitnum;
4731 rtx temp1 = gen_reg_rtx (SImode);
4732 rtx temp2 = gen_reg_rtx (SImode);
4734 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4736 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4741 rtx temp1 = gen_reg_rtx (DImode);
4742 rtx temp2 = gen_reg_rtx (DImode);
4743 rtx temp3 = gen_reg_rtx (DImode);
4745 = gen_unaligned_storehi (get_unaligned_address (operands[0], 0),
4746 operands[1], temp1, temp2, temp3);
4748 alpha_set_memflags (seq, operands[0]);
4757 ;; Here are the versions for reload. Note that in the unaligned cases
4758 ;; we know that the operand must not be a pseudo-register because stack
4759 ;; slots are always aligned references.
4761 (define_expand "reload_inqi"
4762 [(parallel [(match_operand:QI 0 "register_operand" "=r")
4763 (match_operand:QI 1 "unaligned_memory_operand" "m")
4764 (match_operand:TI 2 "register_operand" "=&r")])]
4768 rtx addr = get_unaligned_address (operands[1], 0);
4770 /* It is possible that one of the registers we got for operands[2]
4771 might coincide with that of operands[0] (which is why we made
4772 it TImode). Pick the other one to use as our scratch. */
4773 rtx scratch = gen_rtx_REG (DImode,
4774 REGNO (operands[0]) == REGNO (operands[2])
4775 ? REGNO (operands[2]) + 1 : REGNO (operands[2]));
4777 rtx seq = gen_unaligned_loadqi (operands[0], addr, scratch,
4778 gen_rtx_REG (DImode, REGNO (operands[0])));
4780 alpha_set_memflags (seq, operands[1]);
4785 (define_expand "reload_inhi"
4786 [(parallel [(match_operand:HI 0 "register_operand" "=r")
4787 (match_operand:HI 1 "unaligned_memory_operand" "m")
4788 (match_operand:TI 2 "register_operand" "=&r")])]
4792 rtx addr = get_unaligned_address (operands[1], 0);
4794 /* It is possible that one of the registers we got for operands[2]
4795 might coincide with that of operands[0] (which is why we made
4796 it TImode). Pick the other one to use as our scratch. */
4797 rtx scratch = gen_rtx_REG (DImode,
4798 REGNO (operands[0]) == REGNO (operands[2])
4799 ? REGNO (operands[2]) + 1 : REGNO (operands[2]));
4801 rtx seq = gen_unaligned_loadhi (operands[0], addr, scratch,
4802 gen_rtx_REG (DImode, REGNO (operands[0])));
4804 alpha_set_memflags (seq, operands[1]);
4809 (define_expand "reload_outqi"
4810 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
4811 (match_operand:QI 1 "register_operand" "r")
4812 (match_operand:TI 2 "register_operand" "=&r")])]
4816 if (aligned_memory_operand (operands[0], QImode))
4818 rtx aligned_mem, bitnum;
4820 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4822 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4823 gen_rtx_REG (SImode, REGNO (operands[2])),
4824 gen_rtx_REG (SImode,
4825 REGNO (operands[2]) + 1)));
4829 rtx addr = get_unaligned_address (operands[0], 0);
4830 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
4831 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
4832 rtx scratch3 = scratch1;
4835 if (GET_CODE (addr) == REG)
4838 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
4839 scratch2, scratch3);
4840 alpha_set_memflags (seq, operands[0]);
4847 (define_expand "reload_outhi"
4848 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
4849 (match_operand:HI 1 "register_operand" "r")
4850 (match_operand:TI 2 "register_operand" "=&r")])]
4854 if (aligned_memory_operand (operands[0], HImode))
4856 rtx aligned_mem, bitnum;
4858 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4860 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4861 gen_rtx_REG (SImode, REGNO (operands[2])),
4862 gen_rtx_REG (SImode,
4863 REGNO (operands[2]) + 1)));
4867 rtx addr = get_unaligned_address (operands[0], 0);
4868 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
4869 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
4870 rtx scratch3 = scratch1;
4873 if (GET_CODE (addr) == REG)
4876 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
4877 scratch2, scratch3);
4878 alpha_set_memflags (seq, operands[0]);
4885 ;; Bit field extract patterns which use ext[wlq][lh]
4887 (define_expand "extv"
4888 [(set (match_operand:DI 0 "register_operand" "")
4889 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
4890 (match_operand:DI 2 "immediate_operand" "")
4891 (match_operand:DI 3 "immediate_operand" "")))]
4895 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
4896 if (INTVAL (operands[3]) % 8 != 0
4897 || (INTVAL (operands[2]) != 16
4898 && INTVAL (operands[2]) != 32
4899 && INTVAL (operands[2]) != 64))
4902 /* From mips.md: extract_bit_field doesn't verify that our source
4903 matches the predicate, so we force it to be a MEM here. */
4904 if (GET_CODE (operands[1]) != MEM)
4907 alpha_expand_unaligned_load (operands[0], operands[1],
4908 INTVAL (operands[2]) / 8,
4909 INTVAL (operands[3]) / 8, 1);
4913 (define_expand "extzv"
4914 [(set (match_operand:DI 0 "register_operand" "")
4915 (zero_extract:DI (match_operand:DI 1 "general_operand" "")
4916 (match_operand:DI 2 "immediate_operand" "")
4917 (match_operand:DI 3 "immediate_operand" "")))]
4921 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
4922 if (INTVAL (operands[3]) % 8 != 0
4923 || (INTVAL (operands[2]) != 8
4924 && INTVAL (operands[2]) != 16
4925 && INTVAL (operands[2]) != 32
4926 && INTVAL (operands[2]) != 64))
4929 if (GET_CODE (operands[1]) == MEM)
4931 /* Fail 8 bit fields, falling back on a simple byte load. */
4932 if (INTVAL (operands[2]) == 8)
4935 alpha_expand_unaligned_load (operands[0], operands[1],
4936 INTVAL (operands[2]) / 8,
4937 INTVAL (operands[3]) / 8, 0);
4942 (define_expand "insv"
4943 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
4944 (match_operand:DI 1 "immediate_operand" "")
4945 (match_operand:DI 2 "immediate_operand" ""))
4946 (match_operand:DI 3 "register_operand" ""))]
4950 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
4951 if (INTVAL (operands[2]) % 8 != 0
4952 || (INTVAL (operands[1]) != 16
4953 && INTVAL (operands[1]) != 32
4954 && INTVAL (operands[1]) != 64))
4957 /* From mips.md: store_bit_field doesn't verify that our source
4958 matches the predicate, so we force it to be a MEM here. */
4959 if (GET_CODE (operands[0]) != MEM)
4962 alpha_expand_unaligned_store (operands[0], operands[3],
4963 INTVAL (operands[1]) / 8,
4964 INTVAL (operands[2]) / 8);
4970 ;; Block move/clear, see alpha.c for more details.
4971 ;; Argument 0 is the destination
4972 ;; Argument 1 is the source
4973 ;; Argument 2 is the length
4974 ;; Argument 3 is the alignment
4976 (define_expand "movstrqi"
4977 [(parallel [(set (match_operand:BLK 0 "general_operand" "")
4978 (match_operand:BLK 1 "general_operand" ""))
4979 (use (match_operand:DI 2 "immediate_operand" ""))
4980 (use (match_operand:DI 3 "immediate_operand" ""))])]
4984 if (alpha_expand_block_move (operands))
4990 (define_expand "clrstrqi"
4991 [(parallel [(set (match_operand:BLK 0 "general_operand" "")
4993 (use (match_operand:DI 1 "immediate_operand" ""))
4994 (use (match_operand:DI 2 "immediate_operand" ""))])]
4998 if (alpha_expand_block_clear (operands))
5004 ;; Subroutine of stack space allocation. Perform a stack probe.
5005 (define_expand "probe_stack"
5006 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
5010 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
5011 INTVAL (operands[0])));
5012 MEM_VOLATILE_P (operands[1]) = 1;
5014 operands[0] = const0_rtx;
5017 ;; This is how we allocate stack space. If we are allocating a
5018 ;; constant amount of space and we know it is less than 4096
5019 ;; bytes, we need do nothing.
5021 ;; If it is more than 4096 bytes, we need to probe the stack
5023 (define_expand "allocate_stack"
5025 (plus:DI (reg:DI 30)
5026 (match_operand:DI 1 "reg_or_cint_operand" "")))
5027 (set (match_operand:DI 0 "register_operand" "=r")
5032 if (GET_CODE (operands[1]) == CONST_INT
5033 && INTVAL (operands[1]) < 32768)
5035 if (INTVAL (operands[1]) >= 4096)
5037 /* We do this the same way as in the prologue and generate explicit
5038 probes. Then we update the stack by the constant. */
5042 emit_insn (gen_probe_stack (GEN_INT (- probed)));
5043 while (probed + 8192 < INTVAL (operands[1]))
5044 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
5046 if (probed + 4096 < INTVAL (operands[1]))
5047 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
5050 operands[1] = GEN_INT (- INTVAL (operands[1]));
5051 operands[2] = virtual_stack_dynamic_rtx;
5056 rtx loop_label = gen_label_rtx ();
5057 rtx want = gen_reg_rtx (Pmode);
5058 rtx tmp = gen_reg_rtx (Pmode);
5061 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
5062 force_reg (Pmode, operands[1])));
5063 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
5065 if (GET_CODE (operands[1]) != CONST_INT)
5067 out_label = gen_label_rtx ();
5068 emit_insn (gen_cmpdi (want, tmp));
5069 emit_jump_insn (gen_bgeu (out_label));
5072 emit_label (loop_label);
5073 memref = gen_rtx_MEM (DImode, tmp);
5074 MEM_VOLATILE_P (memref) = 1;
5075 emit_move_insn (memref, const0_rtx);
5076 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
5077 emit_insn (gen_cmpdi (tmp, want));
5078 emit_jump_insn (gen_bgtu (loop_label));
5080 gen_rtx_USE (VOIDmode, tmp);
5082 memref = gen_rtx_MEM (DImode, want);
5083 MEM_VOLATILE_P (memref) = 1;
5084 emit_move_insn (memref, const0_rtx);
5087 emit_label (out_label);
5089 emit_move_insn (stack_pointer_rtx, want);
5090 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
5095 ;; This is used by alpha_expand_prolog to do the same thing as above,
5096 ;; except we cannot at that time generate new basic blocks, so we hide
5097 ;; the loop in this one insn.
5099 (define_insn "prologue_stack_probe_loop"
5100 [(unspec_volatile [(match_operand 0 "register_operand" "r")
5101 (match_operand 1 "register_operand" "r")] 5)]
5105 static int label_no;
5106 int count_regno = REGNO (operands[0]);
5107 int ptr_regno = REGNO (operands[1]);
5110 /* Ho hum, output the hard way to get the label at the beginning of
5111 the line. Wish there were a magic char you could get
5112 asm_output_printf to do that. Then we could use %= as well and
5113 get rid of the label_no bits here too. */
5115 ASM_GENERATE_INTERNAL_LABEL (label, \"LSC\", label_no);
5116 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LSC\", label_no++);
5118 fprintf (asm_out_file, \"\\tstq $31,-8192($%d)\\n\", ptr_regno);
5119 fprintf (asm_out_file, \"\\tsubq $%d,1,$%d\\n\", count_regno, count_regno);
5120 fprintf (asm_out_file, \"\\tlda $%d,-8192($%d)\\n\", ptr_regno, ptr_regno);
5121 fprintf (asm_out_file, \"\\tbne $%d,\", count_regno);
5122 assemble_name (asm_out_file, label);
5123 putc ('\\n', asm_out_file);
5127 [(set_attr "length" "16")])
5129 (define_expand "prologue"
5130 [(clobber (const_int 0))]
5132 "alpha_expand_prologue (); DONE;")
5134 (define_insn "init_fp"
5135 [(set (match_operand:DI 0 "register_operand" "r")
5136 (match_operand:DI 1 "register_operand" "r"))
5137 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "r")))]
5141 (define_expand "epilogue"
5142 [(clobber (const_int 0))]
5144 "alpha_expand_epilogue (); DONE;")
5146 (define_expand "builtin_longjmp"
5147 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
5148 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5151 /* The elements of the buffer are, in order: */
5152 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5153 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
5154 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
5155 rtx pv = gen_rtx_REG (Pmode, 27);
5157 /* This bit is the same as expand_builtin_longjmp. */
5158 emit_move_insn (hard_frame_pointer_rtx, fp);
5159 emit_move_insn (pv, lab);
5160 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5161 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5162 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5164 /* Load the label we are jumping through into $27 so that we know
5165 where to look for it when we get back to setjmp's function for
5166 restoring the gp. */
5167 emit_indirect_jump (pv);
5170 (define_insn "builtin_setjmp_receiver"
5171 [(unspec_volatile [(match_operand 0 "" "")] 2)]
5172 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT && TARGET_AS_CAN_SUBTRACT_LABELS"
5173 "\\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
5174 [(set_attr "length" "8")])
5177 [(unspec_volatile [(match_operand 0 "" "")] 2)]
5178 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5179 "br $27,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($27)"
5180 [(set_attr "length" "12")])
5182 (define_expand "nonlocal_goto_receiver"
5183 [(unspec_volatile [(const_int 0)] 1)
5184 (set (reg:DI 27) (mem:DI (reg:DI 29)))
5185 (unspec_volatile [(const_int 0)] 1)
5190 (define_insn "arg_home"
5191 [(unspec [(const_int 0)] 0)
5206 (clobber (mem:BLK (const_int 0)))
5207 (clobber (reg:DI 24))
5208 (clobber (reg:DI 25))
5209 (clobber (reg:DI 0))]
5211 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
5212 [(set_attr "length" "16")])
5214 ;; Close the trap shadow of preceeding instructions. This is generated
5217 (define_insn "trapb"
5218 [(unspec_volatile [(const_int 0)] 4)]
5221 [(set_attr "type" "misc")])
5223 ;; Peepholes go at the end.
5225 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
5226 ;; reload when converting fp->int.
5228 ;; ??? What to do now that we actually care about the packing and
5229 ;; alignment of instructions? Perhaps reload can be enlightened, or
5230 ;; the peephole pass moved up after reload but before sched2?
5233 ; [(set (match_operand:SI 0 "register_operand" "=r")
5234 ; (match_operand:SI 1 "memory_operand" "m"))
5235 ; (set (match_operand:DI 2 "register_operand" "=r")
5236 ; (sign_extend:DI (match_dup 0)))]
5237 ; "dead_or_set_p (insn, operands[0])"
5241 ; [(set (match_operand:SI 0 "register_operand" "=r")
5242 ; (match_operand:SI 1 "hard_fp_register_operand" "f"))
5243 ; (set (match_operand:DI 2 "register_operand" "=r")
5244 ; (sign_extend:DI (match_dup 0)))]
5245 ; "TARGET_CIX && dead_or_set_p (insn, operands[0])"