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1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
4
5 ;; This file is part of GNU CC.
6
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
10 ;; any later version.
11
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
22 \f
23 ;; Define an insn type attribute. This is used in function unit delay
24 ;; computations, among other purposes. For the most part, we use the names
25 ;; defined in the EV4 documentation, but add a few that we have to know about
26 ;; separately.
27
28 (define_attr "type"
29 "ld,st,ibr,fbr,jsr,iaddlog,shiftcm,icmp,imull,imulq,fpop,fdivs,fdivt,ldsym,isubr"
30 (const_string "shiftcm"))
31
32 ;; We include four function units: ABOX, which computes the address,
33 ;; BBOX, used for branches, EBOX, used for integer operations, and FBOX,
34 ;; used for FP operations.
35 ;;
36 ;; We assume that we have been successful in getting double issues and
37 ;; hence multiply all costs by two insns per cycle. The minimum time in
38 ;; a function unit is 2 cycle, which will tend to produce the double
39 ;; issues.
40
41 ;; Memory delivers its result in three cycles.
42 (define_function_unit "abox" 1 0 (eq_attr "type" "ld,ldsym,st") 6 2)
43
44 ;; Branches have no delay cost, but do tie up the unit for two cycles.
45 (define_function_unit "bbox" 1 1 (eq_attr "type" "ibr,fbr,jsr") 4 4)
46
47 ;; Arithmetic insns are normally have their results available after two
48 ;; cycles. There are a number of exceptions. They are encoded in
49 ;; ADJUST_COST. Some of the other insns have similar exceptions.
50
51 (define_function_unit "ebox" 1 0 (eq_attr "type" "iaddlog,shiftcm,icmp") 4 2)
52
53 ;; These really don't take up the integer pipeline, but they do occupy
54 ;; IBOX1; we approximate here.
55
56 (define_function_unit "ebox" 1 0 (eq_attr "type" "imull") 42 2)
57 (define_function_unit "ebox" 1 0 (eq_attr "type" "imulq") 46 2)
58
59 (define_function_unit "imult" 1 0 (eq_attr "type" "imull") 42 38)
60 (define_function_unit "imult" 1 0 (eq_attr "type" "imulq") 46 42)
61
62 (define_function_unit "fbox" 1 0 (eq_attr "type" "fpop") 12 2)
63
64 (define_function_unit "fbox" 1 0 (eq_attr "type" "fdivs") 68 0)
65 (define_function_unit "fbox" 1 0 (eq_attr "type" "fdivt") 126 0)
66
67 (define_function_unit "divider" 1 0 (eq_attr "type" "fdivs") 68 60)
68 (define_function_unit "divider" 1 0 (eq_attr "type" "fdivt") 126 118)
69 \f
70 ;; First define the arithmetic insns. Note that the 32-bit forms also
71 ;; sign-extend.
72
73 ;; Note that we can do sign extensions in both FP and integer registers.
74 ;; However, the result must be in the same type of register as the input.
75 ;; The register preferencing code can't handle this case very well, so, for
76 ;; now, don't let the FP case show up here for preferencing. Also,
77 ;; sign-extends in FP registers take two instructions.
78 (define_insn "extendsidi2"
79 [(set (match_operand:DI 0 "register_operand" "=r,r,*f")
80 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,*f")))]
81 ""
82 "@
83 addl %1,$31,%0
84 ldl %0,%1
85 cvtql %1,%0\;cvtlq %0,%0"
86 [(set_attr "type" "iaddlog,ld,fpop")])
87
88 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
89 ;; generates better code. We have the anonymous addsi3 pattern below in
90 ;; case combine wants to make it.
91 (define_expand "addsi3"
92 [(set (match_operand:SI 0 "register_operand" "")
93 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
94 (match_operand:SI 2 "add_operand" "")))]
95 ""
96 "
97 { emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (DImode, operands[0]),
98 gen_rtx (PLUS, DImode,
99 gen_lowpart (DImode, operands[1]),
100 gen_lowpart (DImode, operands[2]))));
101 DONE;
102 } ")
103
104 (define_insn ""
105 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
106 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
107 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
108 ""
109 "@
110 addl %r1,%2,%0
111 subl %r1,%n2,%0
112 lda %0,%2(%r1)
113 ldah %0,%h2(%r1)"
114 [(set_attr "type" "iaddlog")])
115
116 (define_split
117 [(set (match_operand:SI 0 "register_operand" "")
118 (plus:SI (match_operand:SI 1 "register_operand" "")
119 (match_operand:SI 2 "const_int_operand" "")))]
120 "! add_operand (operands[2], SImode)"
121 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
122 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
123 "
124 {
125 HOST_WIDE_INT val = INTVAL (operands[2]);
126 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
127 HOST_WIDE_INT rest = val - low;
128
129 operands[3] = GEN_INT (rest);
130 operands[4] = GEN_INT (low);
131 }")
132
133 (define_insn ""
134 [(set (match_operand:DI 0 "register_operand" "=r,r")
135 (sign_extend:DI
136 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
137 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
138 ""
139 "@
140 addl %r1,%2,%0
141 subl %r1,%n2,%0"
142 [(set_attr "type" "iaddlog")])
143
144 (define_split
145 [(set (match_operand:DI 0 "register_operand" "")
146 (sign_extend:DI
147 (plus:SI (match_operand:SI 1 "register_operand" "")
148 (match_operand:SI 2 "const_int_operand" ""))))
149 (clobber (match_operand:SI 3 "register_operand" ""))]
150 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
151 && INTVAL (operands[2]) % 4 == 0"
152 [(set (match_dup 3) (match_dup 4))
153 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
154 (match_dup 5))
155 (match_dup 1))))]
156 "
157 {
158 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
159 int mult = 4;
160
161 if (val % 2 == 0)
162 val /= 2, mult = 8;
163
164 operands[4] = GEN_INT (val);
165 operands[5] = GEN_INT (mult);
166 }")
167
168 (define_split
169 [(set (match_operand:DI 0 "register_operand" "")
170 (sign_extend:DI
171 (plus:SI (match_operator:SI 1 "comparison_operator"
172 [(match_operand 2 "" "")
173 (match_operand 3 "" "")])
174 (match_operand:SI 4 "add_operand" ""))))
175 (clobber (match_operand:DI 5 "register_operand" ""))]
176 ""
177 [(set (match_dup 5) (match_dup 6))
178 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
179 "
180 {
181 operands[6] = gen_rtx (GET_CODE (operands[1]), DImode,
182 operands[2], operands[3]);
183 operands[7] = gen_lowpart (SImode, operands[5]);
184 }")
185
186 (define_insn "adddi3"
187 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
188 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
189 (match_operand:DI 2 "add_operand" "rI,O,K,L")))]
190 ""
191 "@
192 addq %r1,%2,%0
193 subq %r1,%n2,%0
194 lda %0,%2(%r1)
195 ldah %0,%h2(%r1)"
196 [(set_attr "type" "iaddlog")])
197
198 ;; Don't do this if we are adjusting SP since we don't want to do
199 ;; it in two steps.
200 (define_split
201 [(set (match_operand:DI 0 "register_operand" "")
202 (plus:DI (match_operand:DI 1 "register_operand" "")
203 (match_operand:DI 2 "const_int_operand" "")))]
204 "! add_operand (operands[2], DImode)
205 && REGNO (operands[0]) != STACK_POINTER_REGNUM"
206 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
207 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
208 "
209 {
210 HOST_WIDE_INT val = INTVAL (operands[2]);
211 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
212 HOST_WIDE_INT rest = val - low;
213
214 operands[3] = GEN_INT (rest);
215 operands[4] = GEN_INT (low);
216 }")
217
218 (define_insn ""
219 [(set (match_operand:SI 0 "register_operand" "=r,r")
220 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ")
221 (match_operand:SI 2 "const48_operand" "I,I"))
222 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
223 ""
224 "@
225 s%2addl %r1,%3,%0
226 s%2subl %r1,%n3,%0"
227 [(set_attr "type" "iaddlog")])
228
229 (define_insn ""
230 [(set (match_operand:DI 0 "register_operand" "=r,r")
231 (sign_extend:DI
232 (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ,rJ")
233 (match_operand:SI 2 "const48_operand" "I,I"))
234 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
235 ""
236 "@
237 s%2addl %r1,%3,%0
238 s%2subl %r1,%n3,%0"
239 [(set_attr "type" "iaddlog")])
240
241 (define_split
242 [(set (match_operand:DI 0 "register_operand" "")
243 (sign_extend:DI
244 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
245 [(match_operand 2 "" "")
246 (match_operand 3 "" "")])
247 (match_operand:SI 4 "const48_operand" ""))
248 (match_operand:SI 5 "add_operand" ""))))
249 (clobber (match_operand:DI 6 "register_operand" ""))]
250 ""
251 [(set (match_dup 6) (match_dup 7))
252 (set (match_dup 0)
253 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
254 (match_dup 5))))]
255 "
256 {
257 operands[7] = gen_rtx (GET_CODE (operands[1]), DImode,
258 operands[2], operands[3]);
259 operands[8] = gen_lowpart (SImode, operands[6]);
260 }")
261
262 (define_insn ""
263 [(set (match_operand:DI 0 "register_operand" "=r,r")
264 (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
265 (match_operand:DI 2 "const48_operand" "I,I"))
266 (match_operand:DI 3 "reg_or_8bit_operand" "rI,O")))]
267 ""
268 "@
269 s%2addq %r1,%3,%0
270 s%2subq %1,%n3,%0"
271 [(set_attr "type" "iaddlog")])
272
273 ;; These variants of the above insns can occur if the third operand
274 ;; is the frame pointer. This is a kludge, but there doesn't
275 ;; seem to be a way around it. Only recognize them while reloading.
276
277 (define_insn ""
278 [(set (match_operand:DI 0 "register_operand" "=&r")
279 (plus:DI (plus:DI (match_operand:DI 1 "register_operand" "r")
280 (match_operand:DI 2 "register_operand" "r"))
281 (match_operand:DI 3 "add_operand" "rIOKL")))]
282 "reload_in_progress"
283 "#"
284 [(set_attr "type" "iaddlog")])
285
286 (define_split
287 [(set (match_operand:DI 0 "register_operand" "")
288 (plus:DI (plus:DI (match_operand:DI 1 "register_operand" "")
289 (match_operand:DI 2 "register_operand" ""))
290 (match_operand:DI 3 "add_operand" "")))]
291 "reload_completed"
292 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
293 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
294 "")
295
296 (define_insn ""
297 [(set (match_operand:SI 0 "register_operand" "=&r")
298 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "some_operand" "rJ")
299 (match_operand:SI 2 "const48_operand" "I"))
300 (match_operand:SI 3 "register_operand" "r"))
301 (match_operand:SI 4 "add_operand" "rIOKL")))]
302 "reload_in_progress"
303 "#"
304 [(set_attr "type" "iaddlog")])
305
306 (define_split
307 [(set (match_operand:SI 0 "register_operand" "r")
308 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
309 (match_operand:SI 2 "const48_operand" ""))
310 (match_operand:SI 3 "register_operand" ""))
311 (match_operand:SI 4 "add_operand" "rIOKL")))]
312 "reload_completed"
313 [(set (match_dup 0)
314 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
315 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
316 "")
317
318 (define_insn ""
319 [(set (match_operand:DI 0 "register_operand" "=&r")
320 (sign_extend:DI
321 (plus:SI (plus:SI
322 (mult:SI (match_operand:SI 1 "some_operand" "rJ")
323 (match_operand:SI 2 "const48_operand" "I"))
324 (match_operand:SI 3 "register_operand" "r"))
325 (match_operand:SI 4 "add_operand" "rIOKL"))))]
326 "reload_in_progress"
327 "#"
328 [(set_attr "type" "iaddlog")])
329
330 (define_split
331 [(set (match_operand:DI 0 "register_operand" "")
332 (sign_extend:DI
333 (plus:SI (plus:SI
334 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
335 (match_operand:SI 2 "const48_operand" ""))
336 (match_operand:SI 3 "register_operand" ""))
337 (match_operand:SI 4 "add_operand" ""))))]
338 "reload_completed"
339 [(set (match_dup 5)
340 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
341 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 5) (match_dup 4))))]
342 "
343 { operands[5] = gen_lowpart (SImode, operands[0]);
344 }")
345
346 (define_insn ""
347 [(set (match_operand:DI 0 "register_operand" "=&r")
348 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "some_operand" "rJ")
349 (match_operand:DI 2 "const48_operand" "I"))
350 (match_operand:DI 3 "register_operand" "r"))
351 (match_operand:DI 4 "add_operand" "rIOKL")))]
352 "reload_in_progress"
353 "s%2addq %r1,%3,%0\;addq %0,%4,%0"
354 [(set_attr "type" "iaddlog")])
355
356 (define_split
357 [(set (match_operand:DI 0 "register_operand" "=")
358 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "")
359 (match_operand:DI 2 "const48_operand" ""))
360 (match_operand:DI 3 "register_operand" ""))
361 (match_operand:DI 4 "add_operand" "")))]
362 "reload_completed"
363 [(set (match_dup 0)
364 (plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
365 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
366 "")
367
368 (define_insn "negsi2"
369 [(set (match_operand:SI 0 "register_operand" "=r")
370 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
371 ""
372 "subl $31,%1,%0"
373 [(set_attr "type" "iaddlog")])
374
375 (define_insn ""
376 [(set (match_operand:DI 0 "register_operand" "=r")
377 (sign_extend:DI (neg:SI
378 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
379 ""
380 "subl $31,%1,%0"
381 [(set_attr "type" "iaddlog")])
382
383 (define_insn "negdi2"
384 [(set (match_operand:DI 0 "register_operand" "=r")
385 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
386 ""
387 "subq $31,%1,%0"
388 [(set_attr "type" "iaddlog")])
389
390 (define_expand "subsi3"
391 [(set (match_operand:SI 0 "register_operand" "")
392 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
393 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
394 ""
395 "
396 { emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (DImode, operands[0]),
397 gen_rtx (MINUS, DImode,
398 gen_lowpart (DImode, operands[1]),
399 gen_lowpart (DImode, operands[2]))));
400 DONE;
401
402 } ")
403
404 (define_insn ""
405 [(set (match_operand:SI 0 "register_operand" "=r")
406 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
407 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
408 ""
409 "subl %r1,%2,%0"
410 [(set_attr "type" "iaddlog")])
411
412 (define_insn ""
413 [(set (match_operand:DI 0 "register_operand" "=r")
414 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
415 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
416 ""
417 "subl %r1,%2,%0"
418 [(set_attr "type" "iaddlog")])
419
420 (define_insn "subdi3"
421 [(set (match_operand:DI 0 "register_operand" "=r")
422 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
423 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
424 ""
425 "subq %r1,%2,%0"
426 [(set_attr "type" "iaddlog")])
427
428 (define_insn ""
429 [(set (match_operand:SI 0 "register_operand" "=r")
430 (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
431 (match_operand:SI 2 "const48_operand" "I"))
432 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
433 ""
434 "s%2subl %r1,%3,%0"
435 [(set_attr "type" "iaddlog")])
436
437 (define_insn ""
438 [(set (match_operand:DI 0 "register_operand" "=r")
439 (sign_extend:DI
440 (minus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
441 (match_operand:SI 2 "const48_operand" "I"))
442 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
443 ""
444 "s%2subl %r1,%3,%0"
445 [(set_attr "type" "iaddlog")])
446
447 (define_insn ""
448 [(set (match_operand:DI 0 "register_operand" "=r")
449 (minus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
450 (match_operand:DI 2 "const48_operand" "I"))
451 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
452 ""
453 "s%2subq %r1,%3,%0"
454 [(set_attr "type" "iaddlog")])
455
456 (define_insn "mulsi3"
457 [(set (match_operand:SI 0 "register_operand" "=r")
458 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
459 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
460 ""
461 "mull %r1,%r2,%0"
462 [(set_attr "type" "imull")])
463
464 (define_insn ""
465 [(set (match_operand:DI 0 "register_operand" "=r")
466 (sign_extend:DI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
467 (match_operand:SI 2 "reg_or_0_operand" "rJ"))))]
468 ""
469 "mull %r1,%r2,%0"
470 [(set_attr "type" "imull")])
471
472 (define_insn "muldi3"
473 [(set (match_operand:DI 0 "register_operand" "=r")
474 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
475 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
476 ""
477 "mulq %r1,%r2,%0"
478 [(set_attr "type" "imulq")])
479
480 (define_insn "umuldi3_highpart"
481 [(set (match_operand:DI 0 "register_operand" "=r")
482 (truncate:DI
483 (lshiftrt:TI
484 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
485 (zero_extend:TI (match_operand:DI 2 "register_operand" "r")))
486 (const_int 64))))]
487 ""
488 "umulh %1,%2,%0"
489 [(set_attr "type" "imulq")])
490
491 (define_insn ""
492 [(set (match_operand:DI 0 "register_operand" "=r")
493 (truncate:DI
494 (lshiftrt:TI
495 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
496 (match_operand:TI 2 "cint8_operand" "I"))
497 (const_int 64))))]
498 ""
499 "umulh %1,%2,%0"
500 [(set_attr "type" "imulq")])
501 \f
502 ;; The divide and remainder operations always take their inputs from
503 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
504
505 (define_expand "divsi3"
506 [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
507 (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
508 (parallel [(set (reg:SI 27)
509 (div:SI (reg:SI 24)
510 (reg:SI 25)))
511 (clobber (reg:DI 23))
512 (clobber (reg:DI 28))])
513 (set (match_operand:SI 0 "general_operand" "")
514 (reg:SI 27))]
515 ""
516 "")
517
518 (define_expand "udivsi3"
519 [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
520 (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
521 (parallel [(set (reg:SI 27)
522 (udiv:SI (reg:SI 24)
523 (reg:SI 25)))
524 (clobber (reg:DI 23))
525 (clobber (reg:DI 28))])
526 (set (match_operand:SI 0 "general_operand" "")
527 (reg:SI 27))]
528 ""
529 "")
530
531 (define_expand "modsi3"
532 [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
533 (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
534 (parallel [(set (reg:SI 27)
535 (mod:SI (reg:SI 24)
536 (reg:SI 25)))
537 (clobber (reg:DI 23))
538 (clobber (reg:DI 28))])
539 (set (match_operand:SI 0 "general_operand" "")
540 (reg:SI 27))]
541 ""
542 "")
543
544 (define_expand "umodsi3"
545 [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
546 (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
547 (parallel [(set (reg:SI 27)
548 (umod:SI (reg:SI 24)
549 (reg:SI 25)))
550 (clobber (reg:DI 23))
551 (clobber (reg:DI 28))])
552 (set (match_operand:SI 0 "general_operand" "")
553 (reg:SI 27))]
554 ""
555 "")
556
557 (define_expand "divdi3"
558 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
559 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
560 (parallel [(set (reg:DI 27)
561 (div:DI (reg:DI 24)
562 (reg:DI 25)))
563 (clobber (reg:DI 23))
564 (clobber (reg:DI 28))])
565 (set (match_operand:DI 0 "general_operand" "")
566 (reg:DI 27))]
567 ""
568 "")
569
570 (define_expand "udivdi3"
571 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
572 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
573 (parallel [(set (reg:DI 27)
574 (udiv:DI (reg:DI 24)
575 (reg:DI 25)))
576 (clobber (reg:DI 23))
577 (clobber (reg:DI 28))])
578 (set (match_operand:DI 0 "general_operand" "")
579 (reg:DI 27))]
580 ""
581 "")
582
583 (define_expand "moddi3"
584 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
585 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
586 (parallel [(set (reg:DI 27)
587 (mod:DI (reg:DI 24)
588 (reg:DI 25)))
589 (clobber (reg:DI 23))
590 (clobber (reg:DI 28))])
591 (set (match_operand:DI 0 "general_operand" "")
592 (reg:DI 27))]
593 ""
594 "")
595
596 (define_expand "umoddi3"
597 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
598 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
599 (parallel [(set (reg:DI 27)
600 (umod:DI (reg:DI 24)
601 (reg:DI 25)))
602 (clobber (reg:DI 23))
603 (clobber (reg:DI 28))])
604 (set (match_operand:DI 0 "general_operand" "")
605 (reg:DI 27))]
606 ""
607 "")
608
609 (define_insn ""
610 [(set (reg:SI 27)
611 (match_operator:SI 1 "divmod_operator"
612 [(reg:SI 24) (reg:SI 25)]))
613 (clobber (reg:DI 23))
614 (clobber (reg:DI 28))]
615 ""
616 "%E1 $24,$25,$27"
617 [(set_attr "type" "isubr")])
618
619 (define_insn ""
620 [(set (reg:DI 27)
621 (match_operator:DI 1 "divmod_operator"
622 [(reg:DI 24) (reg:DI 25)]))
623 (clobber (reg:DI 23))
624 (clobber (reg:DI 28))]
625 ""
626 "%E1 $24,$25,$27"
627 [(set_attr "type" "isubr")])
628 \f
629 ;; Next are the basic logical operations. These only exist in DImode.
630
631 (define_insn "anddi3"
632 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
633 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
634 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
635 ""
636 "@
637 and %r1,%2,%0
638 bic %r1,%N2,%0
639 zapnot %r1,%m2,%0"
640 [(set_attr "type" "iaddlog,iaddlog,shiftcm")])
641
642 ;; There are times when we can split and AND into two AND insns. This occurs
643 ;; when we can first clear any bytes and then clear anything else. For
644 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
645 ;; Only to this when running on 64-bit host since the computations are
646 ;; too messy otherwise.
647
648 (define_split
649 [(set (match_operand:DI 0 "register_operand" "")
650 (and:DI (match_operand:DI 1 "register_operand" "")
651 (match_operand:DI 2 "const_int_operand" "")))]
652 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
653 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
654 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
655 "
656 {
657 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
658 unsigned HOST_WIDE_INT mask2 = mask1;
659 int i;
660
661 /* For each byte that isn't all zeros, make it all ones. */
662 for (i = 0; i < 64; i += 8)
663 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
664 mask1 |= (HOST_WIDE_INT) 0xff << i;
665
666 /* Now turn on any bits we've just turned off. */
667 mask2 |= ~ mask1;
668
669 operands[3] = GEN_INT (mask1);
670 operands[4] = GEN_INT (mask2);
671 }")
672
673 (define_insn "zero_extendqihi2"
674 [(set (match_operand:HI 0 "register_operand" "=r")
675 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
676 ""
677 "zapnot %1,1,%0"
678 [(set_attr "type" "iaddlog")])
679
680 (define_insn "zero_extendqisi2"
681 [(set (match_operand:SI 0 "register_operand" "=r")
682 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
683 ""
684 "zapnot %1,1,%0"
685 [(set_attr "type" "iaddlog")])
686
687 (define_insn "zero_extendqidi2"
688 [(set (match_operand:DI 0 "register_operand" "=r")
689 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
690 ""
691 "zapnot %1,1,%0"
692 [(set_attr "type" "iaddlog")])
693
694 (define_insn "zero_extendhisi2"
695 [(set (match_operand:SI 0 "register_operand" "=r")
696 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
697 ""
698 "zapnot %1,3,%0"
699 [(set_attr "type" "iaddlog")])
700
701 (define_insn "zero_extendhidi2"
702 [(set (match_operand:DI 0 "register_operand" "=r")
703 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
704 ""
705 "zapnot %1,3,%0"
706 [(set_attr "type" "iaddlog")])
707
708 (define_insn "zero_extendsidi2"
709 [(set (match_operand:DI 0 "register_operand" "=r")
710 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
711 ""
712 "zapnot %1,15,%0"
713 [(set_attr "type" "iaddlog")])
714
715 (define_insn ""
716 [(set (match_operand:DI 0 "register_operand" "=r")
717 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
718 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
719 ""
720 "bic %r2,%1,%0"
721 [(set_attr "type" "iaddlog")])
722
723 (define_insn "iordi3"
724 [(set (match_operand:DI 0 "register_operand" "=r,r")
725 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
726 (match_operand:DI 2 "or_operand" "rI,N")))]
727 ""
728 "@
729 bis %r1,%2,%0
730 ornot %r1,%N2,%0"
731 [(set_attr "type" "iaddlog")])
732
733 (define_insn "one_cmpldi2"
734 [(set (match_operand:DI 0 "register_operand" "=r")
735 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
736 ""
737 "ornot $31,%1,%0"
738 [(set_attr "type" "iaddlog")])
739
740 (define_insn ""
741 [(set (match_operand:DI 0 "register_operand" "=r")
742 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
743 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
744 ""
745 "ornot %r2,%1,%0"
746 [(set_attr "type" "iaddlog")])
747
748 (define_insn "xordi3"
749 [(set (match_operand:DI 0 "register_operand" "=r,r")
750 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
751 (match_operand:DI 2 "or_operand" "rI,N")))]
752 ""
753 "@
754 xor %r1,%2,%0
755 eqv %r1,%N2,%0"
756 [(set_attr "type" "iaddlog")])
757
758 (define_insn ""
759 [(set (match_operand:DI 0 "register_operand" "=r")
760 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
761 (match_operand:DI 2 "register_operand" "rI"))))]
762 ""
763 "eqv %r1,%2,%0"
764 [(set_attr "type" "iaddlog")])
765 \f
766 ;; Next come the shifts and the various extract and insert operations.
767
768 (define_insn "ashldi3"
769 [(set (match_operand:DI 0 "register_operand" "=r,r")
770 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
771 (match_operand:DI 2 "reg_or_6bit_operand" "P,rI")))]
772 ""
773 "*
774 {
775 switch (which_alternative)
776 {
777 case 0:
778 if (operands[2] == const1_rtx)
779 return \"addq %r1,%r1,%0\";
780 else
781 return \"s%P2addq %r1,0,%0\";
782 case 1:
783 return \"sll %r1,%2,%0\";
784 }
785 }"
786 [(set_attr "type" "iaddlog,shiftcm")])
787
788 ;; ??? The following pattern is made by combine, but earlier phases
789 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
790 ;; with this in a better way at some point.
791 ;;(define_insn ""
792 ;; [(set (match_operand:DI 0 "register_operand" "=r")
793 ;; (sign_extend:DI
794 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
795 ;; (match_operand:DI 2 "const_int_operand" "P"))
796 ;; 0)))]
797 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
798 ;; "*
799 ;;{
800 ;; if (operands[2] == const1_rtx)
801 ;; return \"addl %r1,%r1,%0\";
802 ;; else
803 ;; return \"s%P2addl %r1,0,%0\";
804 ;; }"
805 ;; [(set_attr "type" "iaddlog")])
806
807 (define_insn "lshrdi3"
808 [(set (match_operand:DI 0 "register_operand" "=r")
809 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
810 (match_operand:DI 2 "reg_or_6bit_operand" "rI")))]
811 ""
812 "srl %r1,%2,%0")
813
814 (define_insn "ashrdi3"
815 [(set (match_operand:DI 0 "register_operand" "=r")
816 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
817 (match_operand:DI 2 "reg_or_6bit_operand" "rI")))]
818 ""
819 "sra %r1,%2,%0")
820
821 (define_expand "extendqihi2"
822 [(set (match_dup 2)
823 (ashift:DI (match_operand:QI 1 "register_operand" "")
824 (const_int 56)))
825 (set (match_operand:HI 0 "register_operand" "")
826 (ashiftrt:DI (match_dup 2)
827 (const_int 56)))]
828 ""
829 "
830 { operands[0] = gen_lowpart (DImode, operands[0]);
831 operands[1] = gen_lowpart (DImode, operands[1]);
832 operands[2] = gen_reg_rtx (DImode);
833 }")
834
835 (define_expand "extendqisi2"
836 [(set (match_dup 2)
837 (ashift:DI (match_operand:QI 1 "register_operand" "")
838 (const_int 56)))
839 (set (match_operand:SI 0 "register_operand" "")
840 (ashiftrt:DI (match_dup 2)
841 (const_int 56)))]
842 ""
843 "
844 { operands[0] = gen_lowpart (DImode, operands[0]);
845 operands[1] = gen_lowpart (DImode, operands[1]);
846 operands[2] = gen_reg_rtx (DImode);
847 }")
848
849 (define_expand "extendqidi2"
850 [(set (match_dup 2)
851 (ashift:DI (match_operand:QI 1 "register_operand" "")
852 (const_int 56)))
853 (set (match_operand:DI 0 "register_operand" "")
854 (ashiftrt:DI (match_dup 2)
855 (const_int 56)))]
856 ""
857 "
858 { operands[1] = gen_lowpart (DImode, operands[1]);
859 operands[2] = gen_reg_rtx (DImode);
860 }")
861
862 (define_expand "extendhisi2"
863 [(set (match_dup 2)
864 (ashift:DI (match_operand:HI 1 "register_operand" "")
865 (const_int 48)))
866 (set (match_operand:SI 0 "register_operand" "")
867 (ashiftrt:DI (match_dup 2)
868 (const_int 48)))]
869 ""
870 "
871 { operands[0] = gen_lowpart (DImode, operands[0]);
872 operands[1] = gen_lowpart (DImode, operands[1]);
873 operands[2] = gen_reg_rtx (DImode);
874 }")
875
876 (define_expand "extendhidi2"
877 [(set (match_dup 2)
878 (ashift:DI (match_operand:HI 1 "register_operand" "")
879 (const_int 48)))
880 (set (match_operand:DI 0 "register_operand" "")
881 (ashiftrt:DI (match_dup 2)
882 (const_int 48)))]
883 ""
884 "
885 { operands[1] = gen_lowpart (DImode, operands[1]);
886 operands[2] = gen_reg_rtx (DImode);
887 }")
888
889 (define_insn ""
890 [(set (match_operand:DI 0 "register_operand" "=r")
891 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
892 (match_operand:DI 2 "mode_width_operand" "n")
893 (match_operand:DI 3 "mul8_operand" "I")))]
894 ""
895 "ext%M2l %r1,%s3,%0")
896
897 (define_insn ""
898 [(set (match_operand:DI 0 "register_operand" "=r")
899 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
900 (match_operand:DI 2 "mode_width_operand" "n")
901 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
902 (const_int 3))))]
903 ""
904 "ext%M2l %r1,%3,%0")
905
906 (define_insn ""
907 [(set (match_operand:DI 0 "register_operand" "=r")
908 (ashift:DI
909 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
910 (const_int 8)
911 (ashift:DI
912 (plus:DI
913 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
914 (const_int -1))
915 (const_int 3)))
916 (const_int 56)))]
917 ""
918 "extqh %r1,%2,%0")
919
920 (define_insn ""
921 [(set (match_operand:DI 0 "register_operand" "=r")
922 (ashift:DI
923 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
924 (const_int 16)
925 (ashift:DI
926 (plus:DI
927 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
928 (const_int -2))
929 (const_int 3)))
930 (const_int 48)))]
931 ""
932 "extwh %r1,%2,%0")
933
934 (define_insn ""
935 [(set (match_operand:DI 0 "register_operand" "=r")
936 (ashift:DI
937 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
938 (const_int 32)
939 (ashift:DI
940 (plus:DI
941 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
942 (const_int -4))
943 (const_int 3)))
944 (const_int 32)))]
945 ""
946 "extlh %r1,%2,%0")
947
948 ;; This converts an extXl into an extXh with an appropriate adjustment
949 ;; to the address calculation.
950
951 (define_split
952 [(set (match_operand:DI 0 "register_operand" "")
953 (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
954 (match_operand:DI 2 "mode_width_operand" "")
955 (ashift:DI (match_operand:DI 3 "" "")
956 (const_int 3)))
957 (match_operand:DI 4 "const_int_operand" "")))
958 (clobber (match_operand:DI 5 "register_operand" ""))]
959 "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
960 [(set (match_dup 5) (match_dup 6))
961 (set (match_dup 0)
962 (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
963 (ashift:DI (plus:DI (match_dup 5)
964 (match_dup 7))
965 (const_int 3)))
966 (match_dup 4)))]
967 "
968 {
969 operands[6] = plus_constant (operands[3],
970 INTVAL (operands[2]) / BITS_PER_UNIT);
971 operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
972 }")
973
974 (define_insn ""
975 [(set (match_operand:DI 0 "register_operand" "=r")
976 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
977 (match_operand:DI 2 "mul8_operand" "I")))]
978 ""
979 "insbl %1,%s2,%0")
980
981 (define_insn ""
982 [(set (match_operand:DI 0 "register_operand" "=r")
983 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
984 (match_operand:DI 2 "mul8_operand" "I")))]
985 ""
986 "inswl %1,%s2,%0")
987
988 (define_insn ""
989 [(set (match_operand:DI 0 "register_operand" "=r")
990 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
991 (match_operand:DI 2 "mul8_operand" "I")))]
992 ""
993 "insll %1,%s2,%0")
994
995 (define_insn ""
996 [(set (match_operand:DI 0 "register_operand" "=r")
997 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
998 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
999 (const_int 3))))]
1000 ""
1001 "insbl %1,%2,%0")
1002
1003 (define_insn ""
1004 [(set (match_operand:DI 0 "register_operand" "=r")
1005 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1006 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1007 (const_int 3))))]
1008 ""
1009 "inswl %1,%2,%0")
1010
1011 (define_insn ""
1012 [(set (match_operand:DI 0 "register_operand" "=r")
1013 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1014 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1015 (const_int 3))))]
1016 ""
1017 "insll %1,%2,%0")
1018
1019 ;; We do not include the insXh insns because they are complex to express
1020 ;; and it does not appear that we would ever want to generate them.
1021
1022 (define_insn ""
1023 [(set (match_operand:DI 0 "register_operand" "=r")
1024 (and:DI (not:DI (ashift:DI
1025 (match_operand:DI 2 "mode_mask_operand" "n")
1026 (ashift:DI
1027 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1028 (const_int 3))))
1029 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
1030 ""
1031 "msk%U2l %r1,%3,%0")
1032
1033 ;; We do not include the mskXh insns because it does not appear we would ever
1034 ;; generate one.
1035 \f
1036 ;; Floating-point operations. All the double-precision insns can extend
1037 ;; from single, so indicate that. The exception are the ones that simply
1038 ;; play with the sign bits; it's not clear what to do there.
1039
1040 (define_insn "abssf2"
1041 [(set (match_operand:SF 0 "register_operand" "=f")
1042 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1043 "TARGET_FP"
1044 "cpys $f31,%R1,%0"
1045 [(set_attr "type" "fpop")])
1046
1047 (define_insn "absdf2"
1048 [(set (match_operand:DF 0 "register_operand" "=f")
1049 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1050 "TARGET_FP"
1051 "cpys $f31,%R1,%0"
1052 [(set_attr "type" "fpop")])
1053
1054 (define_insn "negsf2"
1055 [(set (match_operand:SF 0 "register_operand" "=f")
1056 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1057 "TARGET_FP"
1058 "cpysn %R1,%R1,%0"
1059 [(set_attr "type" "fpop")])
1060
1061 (define_insn "negdf2"
1062 [(set (match_operand:DF 0 "register_operand" "=f")
1063 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1064 "TARGET_FP"
1065 "cpysn %R1,%R1,%0"
1066 [(set_attr "type" "fpop")])
1067
1068 (define_insn "addsf3"
1069 [(set (match_operand:SF 0 "register_operand" "=f")
1070 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1071 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1072 "TARGET_FP"
1073 "adds %R1,%R2,%0"
1074 [(set_attr "type" "fpop")])
1075
1076 (define_insn "adddf3"
1077 [(set (match_operand:DF 0 "register_operand" "=f")
1078 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1079 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1080 "TARGET_FP"
1081 "addt %R1,%R2,%0"
1082 [(set_attr "type" "fpop")])
1083
1084 (define_insn ""
1085 [(set (match_operand:DF 0 "register_operand" "=f")
1086 (plus:DF (float_extend:DF
1087 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1088 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1089 "TARGET_FP"
1090 "addt %R1,%R2,%0"
1091 [(set_attr "type" "fpop")])
1092
1093 (define_insn ""
1094 [(set (match_operand:DF 0 "register_operand" "=f")
1095 (plus:DF (float_extend:DF
1096 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1097 (float_extend:DF
1098 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1099 "TARGET_FP"
1100 "addt %R1,%R2,%0"
1101 [(set_attr "type" "fpop")])
1102
1103 (define_insn "fix_truncdfdi2"
1104 [(set (match_operand:DI 0 "register_operand" "=f")
1105 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1106 "TARGET_FP"
1107 "cvttqc %R1,%0"
1108 [(set_attr "type" "fpop")])
1109
1110 (define_insn "fix_truncsfdi2"
1111 [(set (match_operand:DI 0 "register_operand" "=f")
1112 (fix:DI (float_extend:DF
1113 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
1114 "TARGET_FP"
1115 "cvttqc %R1,%0"
1116 [(set_attr "type" "fpop")])
1117
1118 (define_insn "floatdisf2"
1119 [(set (match_operand:SF 0 "register_operand" "=f")
1120 (float:SF (match_operand:DI 1 "register_operand" "f")))]
1121 "TARGET_FP"
1122 "cvtqs %1,%0"
1123 [(set_attr "type" "fpop")])
1124
1125 (define_insn "floatdidf2"
1126 [(set (match_operand:DF 0 "register_operand" "=f")
1127 (float:DF (match_operand:DI 1 "register_operand" "f")))]
1128 "TARGET_FP"
1129 "cvtqt %1,%0"
1130 [(set_attr "type" "fpop")])
1131
1132 (define_insn "extendsfdf2"
1133 [(set (match_operand:DF 0 "register_operand" "=f,f")
1134 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
1135 "TARGET_FP"
1136 "@
1137 addt $f31,%1,%0
1138 lds %0,%1"
1139 [(set_attr "type" "fpop,ld")])
1140
1141 (define_insn "truncdfsf2"
1142 [(set (match_operand:SF 0 "register_operand" "=f")
1143 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1144 "TARGET_FP"
1145 "cvtts %R1,%0"
1146 [(set_attr "type" "fpop")])
1147
1148 (define_insn "divsf3"
1149 [(set (match_operand:SF 0 "register_operand" "=f")
1150 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
1151 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1152 "TARGET_FP"
1153 "divs %R1,%R2,%0"
1154 [(set_attr "type" "fdivs")])
1155
1156 (define_insn "divdf3"
1157 [(set (match_operand:DF 0 "register_operand" "=f")
1158 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1159 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1160 "TARGET_FP"
1161 "divt %R1,%R2,%0"
1162 [(set_attr "type" "fdivt")])
1163
1164 (define_insn ""
1165 [(set (match_operand:DF 0 "register_operand" "=f")
1166 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1167 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1168 "TARGET_FP"
1169 "divt %R1,%R2,%0"
1170 [(set_attr "type" "fdivt")])
1171
1172 (define_insn ""
1173 [(set (match_operand:DF 0 "register_operand" "=f")
1174 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1175 (float_extend:DF
1176 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1177 "TARGET_FP"
1178 "divt %R1,%R2,%0"
1179 [(set_attr "type" "fdivt")])
1180
1181 (define_insn ""
1182 [(set (match_operand:DF 0 "register_operand" "=f")
1183 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1184 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1185 "TARGET_FP"
1186 "divt %R1,%R2,%0"
1187 [(set_attr "type" "fdivt")])
1188
1189 (define_insn "mulsf3"
1190 [(set (match_operand:SF 0 "register_operand" "=f")
1191 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1192 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1193 "TARGET_FP"
1194 "muls %R1,%R2,%0"
1195 [(set_attr "type" "fpop")])
1196
1197 (define_insn "muldf3"
1198 [(set (match_operand:DF 0 "register_operand" "=f")
1199 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1200 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1201 "TARGET_FP"
1202 "mult %R1,%R2,%0"
1203 [(set_attr "type" "fpop")])
1204
1205 (define_insn ""
1206 [(set (match_operand:DF 0 "register_operand" "=f")
1207 (mult:DF (float_extend:DF
1208 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1209 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1210 "TARGET_FP"
1211 "mult %R1,%R2,%0"
1212 [(set_attr "type" "fpop")])
1213
1214 (define_insn ""
1215 [(set (match_operand:DF 0 "register_operand" "=f")
1216 (mult:DF (float_extend:DF
1217 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1218 (float_extend:DF
1219 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1220 "TARGET_FP"
1221 "mult %R1,%R2,%0"
1222 [(set_attr "type" "fpop")])
1223
1224 (define_insn "subsf3"
1225 [(set (match_operand:SF 0 "register_operand" "=f")
1226 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
1227 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1228 "TARGET_FP"
1229 "subs %R1,%R2,%0"
1230 [(set_attr "type" "fpop")])
1231
1232 (define_insn "subdf3"
1233 [(set (match_operand:DF 0 "register_operand" "=f")
1234 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1235 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1236 "TARGET_FP"
1237 "subt %R1,%R2,%0"
1238 [(set_attr "type" "fpop")])
1239
1240 (define_insn ""
1241 [(set (match_operand:DF 0 "register_operand" "=f")
1242 (minus:DF (float_extend:DF
1243 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1244 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1245 "TARGET_FP"
1246 "subt %R1,%R2,%0"
1247 [(set_attr "type" "fpop")])
1248
1249 (define_insn ""
1250 [(set (match_operand:DF 0 "register_operand" "=f")
1251 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
1252 (float_extend:DF
1253 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1254 "TARGET_FP"
1255 "subt %R1,%R2,%0"
1256 [(set_attr "type" "fpop")])
1257
1258 (define_insn ""
1259 [(set (match_operand:DF 0 "register_operand" "=f")
1260 (minus:DF (float_extend:DF
1261 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1262 (float_extend:DF
1263 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1264 "TARGET_FP"
1265 "subt %R1,%R2,%0"
1266 [(set_attr "type" "fpop")])
1267 \f
1268 ;; Next are all the integer comparisons, and conditional moves and branches
1269 ;; and some of the related define_expand's and define_split's.
1270
1271 (define_insn ""
1272 [(set (match_operand:DI 0 "register_operand" "=r")
1273 (match_operator:DI 1 "alpha_comparison_operator"
1274 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
1275 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
1276 ""
1277 "cmp%C1 %r2,%3,%0"
1278 [(set_attr "type" "icmp")])
1279
1280 ;; There are three important special-case that don't fit the above pattern
1281 ;; but which we want to handle here.
1282
1283 (define_insn ""
1284 [(set (match_operand:DI 0 "register_operand" "=r")
1285 (ne:DI (match_operand:DI 1 "register_operand" "r")
1286 (const_int 0)))]
1287 ""
1288 "cmpult $31,%1,%0"
1289 [(set_attr "type" "icmp")])
1290
1291 (define_insn ""
1292 [(set (match_operand:DI 0 "register_operand" "=r")
1293 (gt:DI (match_operand:DI 1 "register_operand" "r")
1294 (const_int 0)))]
1295 ""
1296 "cmplt $31,%1,%0"
1297 [(set_attr "type" "icmp")])
1298
1299 (define_insn ""
1300 [(set (match_operand:DI 0 "register_operand" "=r")
1301 (ge:DI (match_operand:DI 1 "register_operand" "r")
1302 (const_int 0)))]
1303 ""
1304 "cmple $31,%1,%0"
1305 [(set_attr "type" "icmp")])
1306
1307 ;; This pattern exists so conditional moves of SImode values are handled.
1308 ;; Comparisons are still done in DImode though.
1309
1310 (define_insn ""
1311 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1312 (if_then_else:DI
1313 (match_operator 2 "signed_comparison_operator"
1314 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
1315 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
1316 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0,rI,0")
1317 (match_operand:SI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
1318 "operands[3] == const0_rtx || operands[4] == const0_rtx"
1319 "@
1320 cmov%C2 %r3,%1,%0
1321 cmov%D2 %r3,%5,%0
1322 cmov%c2 %r4,%1,%0
1323 cmov%d2 %r4,%5,%0")
1324
1325 (define_insn ""
1326 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
1327 (if_then_else:DI
1328 (match_operator 2 "signed_comparison_operator"
1329 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
1330 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
1331 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0,rI,0")
1332 (match_operand:DI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
1333 "operands[3] == const0_rtx || operands[4] == const0_rtx"
1334 "@
1335 cmov%C2 %r3,%1,%0
1336 cmov%D2 %r3,%5,%0
1337 cmov%c2 %r4,%1,%0
1338 cmov%d2 %r4,%5,%0")
1339
1340 (define_insn ""
1341 [(set (match_operand:DI 0 "register_operand" "=r,r")
1342 (if_then_else:DI
1343 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
1344 (const_int 1)
1345 (const_int 0))
1346 (const_int 0))
1347 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
1348 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
1349 ""
1350 "@
1351 cmovlbc %r2,%1,%0
1352 cmovlbs %r2,%3,%0")
1353
1354 (define_insn ""
1355 [(set (match_operand:DI 0 "register_operand" "=r,r")
1356 (if_then_else:DI
1357 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
1358 (const_int 1)
1359 (const_int 0))
1360 (const_int 0))
1361 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
1362 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
1363 ""
1364 "@
1365 cmovlbs %r2,%1,%0
1366 cmovlbc %r2,%3,%0")
1367
1368 ;; This form is added since combine thinks that an IF_THEN_ELSE with both
1369 ;; arms constant is a single insn, so it won't try to form it if combine
1370 ;; knows they are really two insns. This occurs in divides by powers
1371 ;; of two.
1372
1373 (define_insn ""
1374 [(set (match_operand:DI 0 "register_operand" "=r")
1375 (if_then_else:DI
1376 (match_operator 2 "signed_comparison_operator"
1377 [(match_operand:DI 3 "reg_or_0_operand" "rJ")
1378 (const_int 0)])
1379 (plus:DI (match_dup 0)
1380 (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1381 (match_dup 0)))
1382 (clobber (match_scratch:DI 4 "=&r"))]
1383 ""
1384 "addq %0,%1,%4\;cmov%C2 %r3,%4,%0")
1385
1386 (define_split
1387 [(set (match_operand:DI 0 "register_operand" "")
1388 (if_then_else:DI
1389 (match_operator 2 "signed_comparison_operator"
1390 [(match_operand:DI 3 "reg_or_0_operand" "")
1391 (const_int 0)])
1392 (plus:DI (match_dup 0)
1393 (match_operand:DI 1 "reg_or_8bit_operand" ""))
1394 (match_dup 0)))
1395 (clobber (match_operand:DI 4 "register_operand" ""))]
1396 ""
1397 [(set (match_dup 4) (plus:DI (match_dup 0) (match_dup 1)))
1398 (set (match_dup 0) (if_then_else:DI (match_op_dup 2
1399 [(match_dup 3)
1400 (const_int 0)])
1401 (match_dup 4) (match_dup 0)))]
1402 "")
1403
1404 (define_split
1405 [(parallel
1406 [(set (match_operand:DI 0 "register_operand" "")
1407 (if_then_else:DI
1408 (match_operator 1 "comparison_operator"
1409 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
1410 (const_int 1)
1411 (match_operand:DI 3 "const_int_operand" ""))
1412 (const_int 0)])
1413 (match_operand:DI 4 "reg_or_8bit_operand" "")
1414 (match_operand:DI 5 "reg_or_8bit_operand" "")))
1415 (clobber (match_operand:DI 6 "register_operand" ""))])]
1416 "INTVAL (operands[3]) != 0"
1417 [(set (match_dup 6)
1418 (lshiftrt:DI (match_dup 2) (match_dup 3)))
1419 (set (match_dup 0)
1420 (if_then_else:DI (match_op_dup 1
1421 [(zero_extract:DI (match_dup 6)
1422 (const_int 1)
1423 (const_int 0))
1424 (const_int 0)])
1425 (match_dup 4)
1426 (match_dup 5)))]
1427 "")
1428
1429 ;; For ABS, we have two choices, depending on whether the input and output
1430 ;; registers are the same or not.
1431 (define_expand "absdi2"
1432 [(set (match_operand:DI 0 "register_operand" "")
1433 (abs:DI (match_operand:DI 1 "register_operand" "")))]
1434 ""
1435 "
1436 { if (rtx_equal_p (operands[0], operands[1]))
1437 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
1438 else
1439 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
1440
1441 DONE;
1442 }")
1443
1444 (define_expand "absdi2_same"
1445 [(set (match_operand:DI 1 "register_operand" "")
1446 (neg:DI (match_operand:DI 0 "register_operand" "")))
1447 (set (match_dup 0)
1448 (if_then_else:DI (ge (match_dup 0) (const_int 0))
1449 (match_dup 0)
1450 (match_dup 1)))]
1451 ""
1452 "")
1453
1454 (define_expand "absdi2_diff"
1455 [(set (match_operand:DI 0 "register_operand" "")
1456 (neg:DI (match_operand:DI 1 "register_operand" "")))
1457 (set (match_dup 0)
1458 (if_then_else:DI (lt (match_dup 1) (const_int 0))
1459 (match_dup 0)
1460 (match_dup 1)))]
1461 ""
1462 "")
1463
1464 (define_split
1465 [(set (match_operand:DI 0 "register_operand" "")
1466 (abs:DI (match_dup 0)))
1467 (clobber (match_operand:DI 2 "register_operand" ""))]
1468 ""
1469 [(set (match_dup 1) (neg:DI (match_dup 0)))
1470 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
1471 (match_dup 0) (match_dup 1)))]
1472 "")
1473
1474 (define_split
1475 [(set (match_operand:DI 0 "register_operand" "")
1476 (abs:DI (match_operand:DI 1 "register_operand" "")))]
1477 "! rtx_equal_p (operands[0], operands[1])"
1478 [(set (match_dup 0) (neg:DI (match_dup 1)))
1479 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
1480 (match_dup 0) (match_dup 1)))]
1481 "")
1482
1483 (define_split
1484 [(set (match_operand:DI 0 "register_operand" "")
1485 (neg:DI (abs:DI (match_dup 0))))
1486 (clobber (match_operand:DI 2 "register_operand" ""))]
1487 ""
1488 [(set (match_dup 1) (neg:DI (match_dup 0)))
1489 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
1490 (match_dup 0) (match_dup 1)))]
1491 "")
1492
1493 (define_split
1494 [(set (match_operand:DI 0 "register_operand" "")
1495 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
1496 "! rtx_equal_p (operands[0], operands[1])"
1497 [(set (match_dup 0) (neg:DI (match_dup 1)))
1498 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
1499 (match_dup 0) (match_dup 1)))]
1500 "")
1501
1502 (define_expand "smaxdi3"
1503 [(set (match_dup 3)
1504 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
1505 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1506 (set (match_operand:DI 0 "register_operand" "")
1507 (if_then_else:DI (eq (match_dup 3) (const_int 0))
1508 (match_dup 1) (match_dup 2)))]
1509 ""
1510 "
1511 { operands[3] = gen_reg_rtx (DImode);
1512 }")
1513
1514 (define_split
1515 [(set (match_operand:DI 0 "register_operand" "")
1516 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
1517 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1518 (clobber (match_operand:DI 3 "register_operand" ""))]
1519 "operands[2] != const0_rtx"
1520 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
1521 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
1522 (match_dup 1) (match_dup 2)))]
1523 "")
1524
1525 (define_insn ""
1526 [(set (match_operand:DI 0 "register_operand" "=r")
1527 (smax:DI (match_operand:DI 1 "register_operand" "0")
1528 (const_int 0)))]
1529 ""
1530 "cmovlt %0,0,%0")
1531
1532 (define_expand "smindi3"
1533 [(set (match_dup 3)
1534 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
1535 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1536 (set (match_operand:DI 0 "register_operand" "")
1537 (if_then_else:DI (ne (match_dup 3) (const_int 0))
1538 (match_dup 1) (match_dup 2)))]
1539 ""
1540 "
1541 { operands[3] = gen_reg_rtx (DImode);
1542 }")
1543
1544 (define_split
1545 [(set (match_operand:DI 0 "register_operand" "")
1546 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
1547 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1548 (clobber (match_operand:DI 3 "register_operand" ""))]
1549 "operands[2] != const0_rtx"
1550 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
1551 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
1552 (match_dup 1) (match_dup 2)))]
1553 "")
1554
1555 (define_insn ""
1556 [(set (match_operand:DI 0 "register_operand" "=r")
1557 (smin:DI (match_operand:DI 1 "register_operand" "0")
1558 (const_int 0)))]
1559 ""
1560 "cmovgt %0,0,%0")
1561
1562 (define_expand "umaxdi3"
1563 [(set (match_dup 3)
1564 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
1565 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1566 (set (match_operand:DI 0 "register_operand" "")
1567 (if_then_else:DI (eq (match_dup 3) (const_int 0))
1568 (match_dup 1) (match_dup 2)))]
1569 ""
1570 "
1571 { operands[3] = gen_reg_rtx (DImode);
1572 }")
1573
1574 (define_split
1575 [(set (match_operand:DI 0 "register_operand" "")
1576 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
1577 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1578 (clobber (match_operand:DI 3 "register_operand" ""))]
1579 "operands[2] != const0_rtx"
1580 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
1581 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
1582 (match_dup 1) (match_dup 2)))]
1583 "")
1584
1585 (define_expand "umindi3"
1586 [(set (match_dup 3)
1587 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
1588 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1589 (set (match_operand:DI 0 "register_operand" "")
1590 (if_then_else:DI (ne (match_dup 3) (const_int 0))
1591 (match_dup 1) (match_dup 2)))]
1592 ""
1593 "
1594 { operands[3] = gen_reg_rtx (DImode);
1595 }")
1596
1597 (define_split
1598 [(set (match_operand:DI 0 "register_operand" "")
1599 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
1600 (match_operand:DI 2 "reg_or_8bit_operand" "")))
1601 (clobber (match_operand:DI 3 "register_operand" ""))]
1602 "operands[2] != const0_rtx"
1603 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
1604 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
1605 (match_dup 1) (match_dup 2)))]
1606 "")
1607
1608 (define_insn ""
1609 [(set (pc)
1610 (if_then_else
1611 (match_operator 1 "signed_comparison_operator"
1612 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
1613 (const_int 0)])
1614 (label_ref (match_operand 0 "" ""))
1615 (pc)))]
1616 ""
1617 "b%C1 %r2,%0"
1618 [(set_attr "type" "ibr")])
1619
1620 (define_insn ""
1621 [(set (pc)
1622 (if_then_else
1623 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1624 (const_int 1)
1625 (const_int 0))
1626 (const_int 0))
1627 (label_ref (match_operand 0 "" ""))
1628 (pc)))]
1629 ""
1630 "blbs %r1,%0"
1631 [(set_attr "type" "ibr")])
1632
1633 (define_insn ""
1634 [(set (pc)
1635 (if_then_else
1636 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1637 (const_int 1)
1638 (const_int 0))
1639 (const_int 0))
1640 (label_ref (match_operand 0 "" ""))
1641 (pc)))]
1642 ""
1643 "blbc %r1,%0"
1644 [(set_attr "type" "ibr")])
1645
1646 (define_split
1647 [(parallel
1648 [(set (pc)
1649 (if_then_else
1650 (match_operator 1 "comparison_operator"
1651 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
1652 (const_int 1)
1653 (match_operand:DI 3 "const_int_operand" ""))
1654 (const_int 0)])
1655 (label_ref (match_operand 0 "" ""))
1656 (pc)))
1657 (clobber (match_operand:DI 4 "register_operand" ""))])]
1658 "INTVAL (operands[3]) != 0"
1659 [(set (match_dup 4)
1660 (lshiftrt:DI (match_dup 2) (match_dup 3)))
1661 (set (pc)
1662 (if_then_else (match_op_dup 1
1663 [(zero_extract:DI (match_dup 4)
1664 (const_int 1)
1665 (const_int 0))
1666 (const_int 0)])
1667 (label_ref (match_dup 0))
1668 (pc)))]
1669 "")
1670 \f
1671 ;; The following are the corresponding floating-point insns. Recall
1672 ;; we need to have variants that expand the arguments from SF mode
1673 ;; to DFmode.
1674
1675 (define_insn ""
1676 [(set (match_operand:DF 0 "register_operand" "=f")
1677 (match_operator:DF 1 "alpha_comparison_operator"
1678 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
1679 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
1680 "TARGET_FP"
1681 "cmpt%C1 %R2,%R3,%0"
1682 [(set_attr "type" "fpop")])
1683
1684 (define_insn ""
1685 [(set (match_operand:DF 0 "register_operand" "=f")
1686 (match_operator:DF 1 "alpha_comparison_operator"
1687 [(float_extend:DF
1688 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
1689 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
1690 "TARGET_FP"
1691 "cmpt%C1 %R2,%R3,%0"
1692 [(set_attr "type" "fpop")])
1693
1694 (define_insn ""
1695 [(set (match_operand:DF 0 "register_operand" "=f")
1696 (match_operator:DF 1 "alpha_comparison_operator"
1697 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
1698 (float_extend:DF
1699 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
1700 "TARGET_FP"
1701 "cmpt%C1 %R2,%R3,%0"
1702 [(set_attr "type" "fpop")])
1703
1704 (define_insn ""
1705 [(set (match_operand:DF 0 "register_operand" "=f")
1706 (match_operator:DF 1 "alpha_comparison_operator"
1707 [(float_extend:DF
1708 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
1709 (float_extend:DF
1710 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
1711 "TARGET_FP"
1712 "cmpt%C1 %R2,%R3,%0"
1713 [(set_attr "type" "fpop")])
1714
1715 (define_insn ""
1716 [(set (match_operand:DF 0 "register_operand" "=f,f")
1717 (if_then_else:DF
1718 (match_operator 3 "signed_comparison_operator"
1719 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
1720 (match_operand:DF 2 "fp0_operand" "G,G")])
1721 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
1722 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
1723 "TARGET_FP"
1724 "@
1725 fcmov%C3 %R4,%R1,%0
1726 fcmov%D3 %R4,%R5,%0"
1727 [(set_attr "type" "fpop")])
1728
1729 (define_insn ""
1730 [(set (match_operand:SF 0 "register_operand" "=f,f")
1731 (if_then_else:SF
1732 (match_operator 3 "signed_comparison_operator"
1733 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
1734 (match_operand:DF 2 "fp0_operand" "G,G")])
1735 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
1736 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
1737 "TARGET_FP"
1738 "@
1739 fcmov%C3 %R4,%R1,%0
1740 fcmov%D3 %R4,%R5,%0"
1741 [(set_attr "type" "fpop")])
1742
1743 (define_insn ""
1744 [(set (match_operand:DF 0 "register_operand" "=f,f")
1745 (if_then_else:DF
1746 (match_operator 3 "signed_comparison_operator"
1747 [(match_operand:DF 1 "reg_or_fp0_operand" "fG,fG")
1748 (match_operand:DF 2 "fp0_operand" "G,G")])
1749 (float_extend:DF (match_operand:SF 4 "reg_or_fp0_operand" "fG,0"))
1750 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
1751 "TARGET_FP"
1752 "@
1753 fcmov%C3 %R4,%R1,%0
1754 fcmov%D3 %R4,%R5,%0"
1755 [(set_attr "type" "fpop")])
1756
1757 (define_insn ""
1758 [(set (match_operand:DF 0 "register_operand" "=f,f")
1759 (if_then_else:DF
1760 (match_operator 3 "signed_comparison_operator"
1761 [(float_extend:DF
1762 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
1763 (match_operand:DF 2 "fp0_operand" "G,G")])
1764 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
1765 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
1766 "TARGET_FP"
1767 "@
1768 fcmov%C3 %R4,%R1,%0
1769 fcmov%D3 %R4,%R5,%0"
1770 [(set_attr "type" "fpop")])
1771
1772 (define_insn ""
1773 [(set (match_operand:SF 0 "register_operand" "=f,f")
1774 (if_then_else:SF
1775 (match_operator 3 "signed_comparison_operator"
1776 [(float_extend:DF
1777 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
1778 (match_operand:DF 2 "fp0_operand" "G,G")])
1779 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
1780 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
1781 "TARGET_FP"
1782 "@
1783 fcmov%C3 %R4,%R1,%0
1784 fcmov%D3 %R4,%R5,%0"
1785 [(set_attr "type" "fpop")])
1786
1787 (define_insn ""
1788 [(set (match_operand:DF 0 "register_operand" "=f,f")
1789 (if_then_else:DF
1790 (match_operator 3 "signed_comparison_operator"
1791 [(float_extend:DF
1792 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
1793 (match_operand:DF 2 "fp0_operand" "G,G")])
1794 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
1795 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
1796 "TARGET_FP"
1797 "@
1798 fcmov%C3 %R4,%R1,%0
1799 fcmov%D3 %R4,%R5,%0"
1800 [(set_attr "type" "fpop")])
1801
1802 (define_expand "maxdf3"
1803 [(set (match_dup 3)
1804 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
1805 (match_operand:DF 2 "reg_or_fp0_operand" "")))
1806 (set (match_operand:DF 0 "register_operand" "")
1807 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
1808 (match_dup 1) (match_dup 2)))]
1809 "TARGET_FP"
1810 "
1811 { operands[3] = gen_reg_rtx (DFmode);
1812 operands[4] = CONST0_RTX (DFmode);
1813 }")
1814
1815 (define_expand "mindf3"
1816 [(set (match_dup 3)
1817 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
1818 (match_operand:DF 2 "reg_or_fp0_operand" "")))
1819 (set (match_operand:DF 0 "register_operand" "")
1820 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
1821 (match_dup 1) (match_dup 2)))]
1822 "TARGET_FP"
1823 "
1824 { operands[3] = gen_reg_rtx (DFmode);
1825 operands[4] = CONST0_RTX (DFmode);
1826 }")
1827
1828 (define_expand "maxsf3"
1829 [(set (match_dup 3)
1830 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
1831 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
1832 (set (match_operand:SF 0 "register_operand" "")
1833 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
1834 (match_dup 1) (match_dup 2)))]
1835 "TARGET_FP"
1836 "
1837 { operands[3] = gen_reg_rtx (DFmode);
1838 operands[4] = CONST0_RTX (DFmode);
1839 }")
1840
1841 (define_expand "minsf3"
1842 [(set (match_dup 3)
1843 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
1844 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
1845 (set (match_operand:SF 0 "register_operand" "")
1846 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
1847 (match_dup 1) (match_dup 2)))]
1848 "TARGET_FP"
1849 "
1850 { operands[3] = gen_reg_rtx (DFmode);
1851 operands[4] = CONST0_RTX (DFmode);
1852 }")
1853
1854 (define_insn ""
1855 [(set (pc)
1856 (if_then_else
1857 (match_operator 1 "signed_comparison_operator"
1858 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
1859 (match_operand:DF 3 "fp0_operand" "G")])
1860 (label_ref (match_operand 0 "" ""))
1861 (pc)))]
1862 "TARGET_FP"
1863 "fb%C1 %R2,%0"
1864 [(set_attr "type" "fbr")])
1865
1866 (define_insn ""
1867 [(set (pc)
1868 (if_then_else
1869 (match_operator 1 "signed_comparison_operator"
1870 [(float_extend:DF
1871 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
1872 (match_operand:DF 3 "fp0_operand" "G")])
1873 (label_ref (match_operand 0 "" ""))
1874 (pc)))]
1875 "TARGET_FP"
1876 "fb%C1 %R2,%0"
1877 [(set_attr "type" "fbr")])
1878 \f
1879 ;; These are the main define_expand's used to make conditional branches
1880 ;; and compares.
1881
1882 (define_expand "cmpdf"
1883 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
1884 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
1885 ""
1886 "
1887 {
1888 alpha_compare_op0 = operands[0];
1889 alpha_compare_op1 = operands[1];
1890 alpha_compare_fp_p = 1;
1891 DONE;
1892 }")
1893
1894 (define_expand "cmpdi"
1895 [(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "")
1896 (match_operand:DI 1 "reg_or_8bit_operand" "")))]
1897 ""
1898 "
1899 {
1900 alpha_compare_op0 = operands[0];
1901 alpha_compare_op1 = operands[1];
1902 alpha_compare_fp_p = 0;
1903 DONE;
1904 }")
1905
1906 (define_expand "beq"
1907 [(set (match_dup 1) (match_dup 2))
1908 (set (pc)
1909 (if_then_else (match_dup 3)
1910 (label_ref (match_operand 0 "" ""))
1911 (pc)))]
1912 ""
1913 "
1914 {
1915 enum machine_mode mode;
1916 enum rtx_code compare_code, branch_code;
1917
1918 if (alpha_compare_fp_p)
1919 mode = DFmode, compare_code = EQ, branch_code = NE;
1920 else
1921 {
1922 mode = DImode, compare_code = MINUS, branch_code = EQ;
1923 if (GET_CODE (alpha_compare_op1) == CONST_INT)
1924 {
1925 compare_code = PLUS;
1926 alpha_compare_op1 = GEN_INT (- INTVAL (alpha_compare_op1));
1927 }
1928 }
1929
1930 operands[1] = gen_reg_rtx (mode);
1931 operands[2] = gen_rtx (compare_code, mode,
1932 alpha_compare_op0, alpha_compare_op1);
1933 operands[3] = gen_rtx (branch_code, VOIDmode,
1934 operands[1], CONST0_RTX (mode));
1935 }")
1936
1937 (define_expand "bne"
1938 [(set (match_dup 1) (match_dup 2))
1939 (set (pc)
1940 (if_then_else (match_dup 3)
1941 (label_ref (match_operand 0 "" ""))
1942 (pc)))]
1943 ""
1944 "
1945 {
1946 enum machine_mode mode;
1947 enum rtx_code compare_code, branch_code;
1948
1949 if (alpha_compare_fp_p)
1950 mode = DFmode, compare_code = EQ, branch_code = EQ;
1951 else
1952 {
1953 mode = DImode, compare_code = MINUS, branch_code = NE;
1954 if (GET_CODE (alpha_compare_op1) == CONST_INT)
1955 {
1956 compare_code = PLUS;
1957 alpha_compare_op1 = GEN_INT (- INTVAL (alpha_compare_op1));
1958 }
1959 }
1960
1961 operands[1] = gen_reg_rtx (mode);
1962 operands[2] = gen_rtx (compare_code, mode,
1963 alpha_compare_op0, alpha_compare_op1);
1964 operands[3] = gen_rtx (branch_code, VOIDmode,
1965 operands[1], CONST0_RTX (mode));
1966 }")
1967
1968 (define_expand "blt"
1969 [(set (match_dup 1) (match_dup 2))
1970 (set (pc)
1971 (if_then_else (match_dup 3)
1972 (label_ref (match_operand 0 "" ""))
1973 (pc)))]
1974 ""
1975 "
1976 {
1977 enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode;
1978 operands[1] = gen_reg_rtx (mode);
1979 operands[2] = gen_rtx (LT, mode, alpha_compare_op0, alpha_compare_op1);
1980 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode));
1981 }")
1982
1983 (define_expand "ble"
1984 [(set (match_dup 1) (match_dup 2))
1985 (set (pc)
1986 (if_then_else (match_dup 3)
1987 (label_ref (match_operand 0 "" ""))
1988 (pc)))]
1989 ""
1990 "
1991 {
1992 enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode;
1993 operands[1] = gen_reg_rtx (mode);
1994 operands[2] = gen_rtx (LE, mode, alpha_compare_op0, alpha_compare_op1);
1995 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode));
1996 }")
1997
1998 (define_expand "bgt"
1999 [(set (match_dup 1) (match_dup 2))
2000 (set (pc)
2001 (if_then_else (match_dup 3)
2002 (label_ref (match_operand 0 "" ""))
2003 (pc)))]
2004 ""
2005 "
2006 {
2007 if (alpha_compare_fp_p)
2008 {
2009 operands[1] = gen_reg_rtx (DFmode);
2010 operands[2] = gen_rtx (LT, DFmode, alpha_compare_op1, alpha_compare_op0);
2011 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode));
2012 }
2013 else
2014 {
2015 operands[1] = gen_reg_rtx (DImode);
2016 operands[2] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1);
2017 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
2018 }
2019 }")
2020
2021 (define_expand "bge"
2022 [(set (match_dup 1) (match_dup 2))
2023 (set (pc)
2024 (if_then_else (match_dup 3)
2025 (label_ref (match_operand 0 "" ""))
2026 (pc)))]
2027 ""
2028 "
2029 {
2030 if (alpha_compare_fp_p)
2031 {
2032 operands[1] = gen_reg_rtx (DFmode);
2033 operands[2] = gen_rtx (LE, DFmode, alpha_compare_op1, alpha_compare_op0);
2034 operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode));
2035 }
2036 else
2037 {
2038 operands[1] = gen_reg_rtx (DImode);
2039 operands[2] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1);
2040 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
2041 }
2042 }")
2043
2044 (define_expand "bltu"
2045 [(set (match_dup 1) (match_dup 2))
2046 (set (pc)
2047 (if_then_else (match_dup 3)
2048 (label_ref (match_operand 0 "" ""))
2049 (pc)))]
2050 ""
2051 "
2052 {
2053 operands[1] = gen_reg_rtx (DImode);
2054 operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
2055 operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx);
2056 }")
2057
2058 (define_expand "bleu"
2059 [(set (match_dup 1) (match_dup 2))
2060 (set (pc)
2061 (if_then_else (match_dup 3)
2062 (label_ref (match_operand 0 "" ""))
2063 (pc)))]
2064 ""
2065 "
2066 {
2067 operands[1] = gen_reg_rtx (DImode);
2068 operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
2069 operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx);
2070 }")
2071
2072 (define_expand "bgtu"
2073 [(set (match_dup 1) (match_dup 2))
2074 (set (pc)
2075 (if_then_else (match_dup 3)
2076 (label_ref (match_operand 0 "" ""))
2077 (pc)))]
2078 ""
2079 "
2080 {
2081 operands[1] = gen_reg_rtx (DImode);
2082 operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
2083 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
2084 }")
2085
2086 (define_expand "bgeu"
2087 [(set (match_dup 1) (match_dup 2))
2088 (set (pc)
2089 (if_then_else (match_dup 3)
2090 (label_ref (match_operand 0 "" ""))
2091 (pc)))]
2092 ""
2093 "
2094 {
2095 operands[1] = gen_reg_rtx (DImode);
2096 operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
2097 operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
2098 }")
2099
2100 (define_expand "seq"
2101 [(set (match_operand:DI 0 "register_operand" "")
2102 (match_dup 1))]
2103 ""
2104 "
2105 {
2106 if (alpha_compare_fp_p)
2107 FAIL;
2108
2109 operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1);
2110 }")
2111
2112 (define_expand "sne"
2113 [(set (match_operand:DI 0 "register_operand" "")
2114 (match_dup 1))
2115 (set (match_dup 0) (xor:DI (match_dup 0) (const_int 1)))]
2116 ""
2117 "
2118 {
2119 if (alpha_compare_fp_p)
2120 FAIL;
2121
2122 operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1);
2123 }")
2124
2125 (define_expand "slt"
2126 [(set (match_operand:DI 0 "register_operand" "")
2127 (match_dup 1))]
2128 ""
2129 "
2130 {
2131 if (alpha_compare_fp_p)
2132 FAIL;
2133
2134 operands[1] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1);
2135 }")
2136
2137 (define_expand "sle"
2138 [(set (match_operand:DI 0 "register_operand" "")
2139 (match_dup 1))]
2140 ""
2141 "
2142 {
2143 if (alpha_compare_fp_p)
2144 FAIL;
2145
2146 operands[1] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1);
2147 }")
2148
2149 (define_expand "sgt"
2150 [(set (match_operand:DI 0 "register_operand" "")
2151 (match_dup 1))]
2152 ""
2153 "
2154 {
2155 if (alpha_compare_fp_p)
2156 FAIL;
2157
2158 operands[1] = gen_rtx (LT, DImode, force_reg (DImode, alpha_compare_op1),
2159 alpha_compare_op0);
2160 }")
2161
2162 (define_expand "sge"
2163 [(set (match_operand:DI 0 "register_operand" "")
2164 (match_dup 1))]
2165 ""
2166 "
2167 {
2168 if (alpha_compare_fp_p)
2169 FAIL;
2170
2171 operands[1] = gen_rtx (LE, DImode, force_reg (DImode, alpha_compare_op1),
2172 alpha_compare_op0);
2173 }")
2174
2175 (define_expand "sltu"
2176 [(set (match_operand:DI 0 "register_operand" "")
2177 (match_dup 1))]
2178 ""
2179 "
2180 {
2181 if (alpha_compare_fp_p)
2182 FAIL;
2183
2184 operands[1] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
2185 }")
2186
2187 (define_expand "sleu"
2188 [(set (match_operand:DI 0 "register_operand" "")
2189 (match_dup 1))]
2190 ""
2191 "
2192 {
2193 if (alpha_compare_fp_p)
2194 FAIL;
2195
2196 operands[1] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
2197 }")
2198
2199 (define_expand "sgtu"
2200 [(set (match_operand:DI 0 "register_operand" "")
2201 (match_dup 1))]
2202 ""
2203 "
2204 {
2205 if (alpha_compare_fp_p)
2206 FAIL;
2207
2208 operands[1] = gen_rtx (LTU, DImode, force_reg (DImode, alpha_compare_op1),
2209 alpha_compare_op0);
2210 }")
2211
2212 (define_expand "sgeu"
2213 [(set (match_operand:DI 0 "register_operand" "")
2214 (match_dup 1))]
2215 ""
2216 "
2217 {
2218 if (alpha_compare_fp_p)
2219 FAIL;
2220
2221 operands[1] = gen_rtx (LEU, DImode, force_reg (DImode, alpha_compare_op1),
2222 alpha_compare_op0);
2223 }")
2224 \f
2225 ;; These are the main define_expand's used to make conditional moves.
2226
2227 (define_expand "movsicc"
2228 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
2229 (set (match_operand:SI 0 "register_operand" "")
2230 (if_then_else:DI (match_dup 5)
2231 (match_operand:SI 2 "reg_or_8bit_operand" "")
2232 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
2233 ""
2234 "
2235 {
2236 rtx op0,op1;
2237 enum rtx_code code = GET_CODE (operands[1]), code2 = NE;
2238
2239 if (alpha_compare_fp_p)
2240 FAIL;
2241 switch (code)
2242 {
2243 case EQ: case LE: case LT:
2244 op0 = alpha_compare_op0;
2245 op1 = alpha_compare_op1;
2246 break;
2247 case NE:
2248 code = code2 = EQ;
2249 op0 = alpha_compare_op0;
2250 op1 = alpha_compare_op1;
2251 break;
2252 case GE:
2253 code = LE;
2254 op0 = force_reg (DImode, alpha_compare_op1);
2255 op1 = alpha_compare_op0;
2256 break;
2257 case GT:
2258 code = LT;
2259 op0 = force_reg (DImode, alpha_compare_op1);
2260 op1 = alpha_compare_op0;
2261 break;
2262 default:
2263 FAIL;
2264 }
2265 operands[1] = gen_rtx (code, DImode, op0, op1);
2266 operands[4] = gen_reg_rtx (DImode);
2267 operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DImode));
2268 }")
2269
2270 (define_expand "movdicc"
2271 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
2272 (set (match_operand:DI 0 "register_operand" "")
2273 (if_then_else:DI (match_dup 5)
2274 (match_operand:DI 2 "reg_or_8bit_operand" "")
2275 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
2276 ""
2277 "
2278 {
2279 rtx op0,op1;
2280 enum rtx_code code = GET_CODE (operands[1]), code2 = NE;
2281
2282 if (alpha_compare_fp_p)
2283 FAIL;
2284 switch (code)
2285 {
2286 case EQ: case LE: case LT:
2287 op0 = alpha_compare_op0;
2288 op1 = alpha_compare_op1;
2289 break;
2290 case NE:
2291 code = code2 = EQ;
2292 op0 = alpha_compare_op0;
2293 op1 = alpha_compare_op1;
2294 break;
2295 case GE:
2296 code = LE;
2297 op0 = force_reg (DImode, alpha_compare_op1);
2298 op1 = alpha_compare_op0;
2299 break;
2300 case GT:
2301 code = LT;
2302 op0 = force_reg (DImode, alpha_compare_op1);
2303 op1 = alpha_compare_op0;
2304 break;
2305 default:
2306 FAIL;
2307 }
2308 operands[1] = gen_rtx (code, DImode, op0, op1);
2309 operands[4] = gen_reg_rtx (DImode);
2310 operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DImode));
2311 }")
2312
2313 (define_expand "movsfcc"
2314 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
2315 (set (match_operand:SF 0 "register_operand" "")
2316 (if_then_else:SF (match_dup 5)
2317 (match_operand:SF 2 "reg_or_fp0_operand" "")
2318 (match_operand:SF 3 "reg_or_fp0_operand" "")))]
2319 ""
2320 "
2321 {
2322 rtx op0,op1;
2323 enum rtx_code code = GET_CODE (operands[1]), code2 = NE;
2324
2325 if (!alpha_compare_fp_p)
2326 FAIL;
2327 switch (code)
2328 {
2329 case EQ: case LE: case LT:
2330 op0 = alpha_compare_op0;
2331 op1 = alpha_compare_op1;
2332 break;
2333 case NE:
2334 /* There isn't a cmptne insn. */
2335 code = code2 = EQ;
2336 op0 = alpha_compare_op0;
2337 op1 = alpha_compare_op1;
2338 break;
2339 case GE:
2340 code = LE;
2341 op0 = force_reg (DFmode, alpha_compare_op1);
2342 op1 = alpha_compare_op0;
2343 break;
2344 case GT:
2345 code = LT;
2346 op0 = force_reg (DFmode, alpha_compare_op1);
2347 op1 = alpha_compare_op0;
2348 break;
2349 default:
2350 FAIL;
2351 }
2352 operands[1] = gen_rtx (code, DFmode, op0, op1);
2353 operands[4] = gen_reg_rtx (DFmode);
2354 operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DFmode));
2355 }")
2356
2357 (define_expand "movdfcc"
2358 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
2359 (set (match_operand:DF 0 "register_operand" "")
2360 (if_then_else:DF (match_dup 5)
2361 (match_operand:DF 2 "reg_or_fp0_operand" "")
2362 (match_operand:DF 3 "reg_or_fp0_operand" "")))]
2363 ""
2364 "
2365 {
2366 rtx op0,op1;
2367 enum rtx_code code = GET_CODE (operands[1]), code2 = NE;
2368
2369 if (!alpha_compare_fp_p)
2370 FAIL;
2371 switch (code)
2372 {
2373 case EQ: case LE: case LT:
2374 op0 = alpha_compare_op0;
2375 op1 = alpha_compare_op1;
2376 break;
2377 case NE:
2378 /* There isn't a cmptne insn. */
2379 code = code2 = EQ;
2380 op0 = alpha_compare_op0;
2381 op1 = alpha_compare_op1;
2382 break;
2383 case GE:
2384 code = LE;
2385 op0 = force_reg (DFmode, alpha_compare_op1);
2386 op1 = alpha_compare_op0;
2387 break;
2388 case GT:
2389 code = LT;
2390 op0 = force_reg (DFmode, alpha_compare_op1);
2391 op1 = alpha_compare_op0;
2392 break;
2393 default:
2394 FAIL;
2395 }
2396 operands[1] = gen_rtx (code, DFmode, op0, op1);
2397 operands[4] = gen_reg_rtx (DFmode);
2398 operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DFmode));
2399 }")
2400 \f
2401 ;; These define_split definitions are used in cases when comparisons have
2402 ;; not be stated in the correct way and we need to reverse the second
2403 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
2404 ;; comparison that tests the result being reversed. We have one define_split
2405 ;; for each use of a comparison. They do not match valid insns and need
2406 ;; not generate valid insns.
2407 ;;
2408 ;; We can also handle equality comparisons (and inequality comparisons in
2409 ;; cases where the resulting add cannot overflow) by doing an add followed by
2410 ;; a comparison with zero. This is faster since the addition takes one
2411 ;; less cycle than a compare when feeding into a conditional move.
2412 ;; For this case, we also have an SImode pattern since we can merge the add
2413 ;; and sign extend and the order doesn't matter.
2414 ;;
2415 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
2416 ;; operation could have been generated.
2417
2418 (define_split
2419 [(set (match_operand:DI 0 "register_operand" "")
2420 (if_then_else:DI
2421 (match_operator 1 "comparison_operator"
2422 [(match_operand:DI 2 "reg_or_0_operand" "")
2423 (match_operand:DI 3 "reg_or_cint_operand" "")])
2424 (match_operand:DI 4 "reg_or_cint_operand" "")
2425 (match_operand:DI 5 "reg_or_cint_operand" "")))
2426 (clobber (match_operand:DI 6 "register_operand" ""))]
2427 "operands[3] != const0_rtx"
2428 [(set (match_dup 6) (match_dup 7))
2429 (set (match_dup 0)
2430 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
2431 "
2432 { enum rtx_code code = GET_CODE (operands[1]);
2433 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
2434
2435 /* If we are comparing for equality with a constant and that constant
2436 appears in the arm when the register equals the constant, use the
2437 register since that is more likely to match (and to produce better code
2438 if both would). */
2439
2440 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
2441 && rtx_equal_p (operands[4], operands[3]))
2442 operands[4] = operands[2];
2443
2444 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
2445 && rtx_equal_p (operands[5], operands[3]))
2446 operands[5] = operands[2];
2447
2448 if (code == NE || code == EQ
2449 || (extended_count (operands[2], DImode, unsignedp) >= 1
2450 && extended_count (operands[3], DImode, unsignedp) >= 1))
2451 {
2452 if (GET_CODE (operands[3]) == CONST_INT)
2453 operands[7] = gen_rtx (PLUS, DImode, operands[2],
2454 GEN_INT (- INTVAL (operands[3])));
2455 else
2456 operands[7] = gen_rtx (MINUS, DImode, operands[2], operands[3]);
2457
2458 operands[8] = gen_rtx (code, VOIDmode, operands[6], const0_rtx);
2459 }
2460
2461 else if (code == EQ || code == LE || code == LT
2462 || code == LEU || code == LTU)
2463 {
2464 operands[7] = gen_rtx (code, DImode, operands[2], operands[3]);
2465 operands[8] = gen_rtx (NE, VOIDmode, operands[6], const0_rtx);
2466 }
2467 else
2468 {
2469 operands[7] = gen_rtx (reverse_condition (code), DImode, operands[2],
2470 operands[3]);
2471 operands[8] = gen_rtx (EQ, VOIDmode, operands[6], const0_rtx);
2472 }
2473 }")
2474
2475 (define_split
2476 [(set (match_operand:DI 0 "register_operand" "")
2477 (if_then_else:DI
2478 (match_operator 1 "comparison_operator"
2479 [(match_operand:SI 2 "reg_or_0_operand" "")
2480 (match_operand:SI 3 "reg_or_cint_operand" "")])
2481 (match_operand:DI 4 "reg_or_8bit_operand" "")
2482 (match_operand:DI 5 "reg_or_8bit_operand" "")))
2483 (clobber (match_operand:DI 6 "register_operand" ""))]
2484 "operands[3] != const0_rtx
2485 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
2486 [(set (match_dup 6) (match_dup 7))
2487 (set (match_dup 0)
2488 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
2489 "
2490 { enum rtx_code code = GET_CODE (operands[1]);
2491 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
2492 rtx tem;
2493
2494 if ((code != NE && code != EQ
2495 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
2496 && extended_count (operands[3], DImode, unsignedp) >= 1)))
2497 FAIL;
2498
2499 if (GET_CODE (operands[3]) == CONST_INT)
2500 tem = gen_rtx (PLUS, SImode, operands[2],
2501 GEN_INT (- INTVAL (operands[3])));
2502 else
2503 tem = gen_rtx (MINUS, SImode, operands[2], operands[3]);
2504
2505 operands[7] = gen_rtx (SIGN_EXTEND, DImode, tem);
2506 operands[8] = gen_rtx (GET_CODE (operands[1]), VOIDmode, operands[6],
2507 const0_rtx);
2508 }")
2509
2510 (define_split
2511 [(set (pc)
2512 (if_then_else
2513 (match_operator 1 "comparison_operator"
2514 [(match_operand:DI 2 "reg_or_0_operand" "")
2515 (match_operand:DI 3 "reg_or_cint_operand" "")])
2516 (label_ref (match_operand 0 "" ""))
2517 (pc)))
2518 (clobber (match_operand:DI 4 "register_operand" ""))]
2519 "operands[3] != const0_rtx"
2520 [(set (match_dup 4) (match_dup 5))
2521 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
2522 "
2523 { enum rtx_code code = GET_CODE (operands[1]);
2524 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
2525
2526 if (code == NE || code == EQ
2527 || (extended_count (operands[2], DImode, unsignedp) >= 1
2528 && extended_count (operands[3], DImode, unsignedp) >= 1))
2529 {
2530 if (GET_CODE (operands[3]) == CONST_INT)
2531 operands[5] = gen_rtx (PLUS, DImode, operands[2],
2532 GEN_INT (- INTVAL (operands[3])));
2533 else
2534 operands[5] = gen_rtx (MINUS, DImode, operands[2], operands[3]);
2535
2536 operands[6] = gen_rtx (code, VOIDmode, operands[4], const0_rtx);
2537 }
2538
2539 else if (code == EQ || code == LE || code == LT
2540 || code == LEU || code == LTU)
2541 {
2542 operands[5] = gen_rtx (code, DImode, operands[2], operands[3]);
2543 operands[6] = gen_rtx (NE, VOIDmode, operands[4], const0_rtx);
2544 }
2545 else
2546 {
2547 operands[5] = gen_rtx (reverse_condition (code), DImode, operands[2],
2548 operands[3]);
2549 operands[6] = gen_rtx (EQ, VOIDmode, operands[4], const0_rtx);
2550 }
2551 }")
2552
2553 (define_split
2554 [(set (pc)
2555 (if_then_else
2556 (match_operator 1 "comparison_operator"
2557 [(match_operand:SI 2 "reg_or_0_operand" "")
2558 (match_operand:SI 3 "const_int_operand" "")])
2559 (label_ref (match_operand 0 "" ""))
2560 (pc)))
2561 (clobber (match_operand:DI 4 "register_operand" ""))]
2562 "operands[3] != const0_rtx
2563 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
2564 [(set (match_dup 4) (match_dup 5))
2565 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
2566 "
2567 { rtx tem;
2568
2569 if (GET_CODE (operands[3]) == CONST_INT)
2570 tem = gen_rtx (PLUS, SImode, operands[2],
2571 GEN_INT (- INTVAL (operands[3])));
2572 else
2573 tem = gen_rtx (MINUS, SImode, operands[2], operands[3]);
2574
2575 operands[5] = gen_rtx (SIGN_EXTEND, DImode, tem);
2576 operands[6] = gen_rtx (GET_CODE (operands[1]), VOIDmode,
2577 operands[4], const0_rtx);
2578 }")
2579
2580 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
2581 ;; This eliminates one, and sometimes two, insns when the AND can be done
2582 ;; with a ZAP.
2583 (define_split
2584 [(set (match_operand:DI 0 "register_operand" "")
2585 (match_operator 1 "comparison_operator"
2586 [(match_operand:DI 2 "register_operand" "")
2587 (match_operand:DI 3 "const_int_operand" "")]))
2588 (clobber (match_operand:DI 4 "register_operand" ""))]
2589 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
2590 && (GET_CODE (operands[1]) == GTU
2591 || GET_CODE (operands[1]) == LEU
2592 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
2593 && extended_count (operands[2], DImode, 1) > 0))"
2594 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
2595 (set (match_dup 0) (match_dup 6))]
2596 "
2597 {
2598 operands[5] = GEN_INT (~ INTVAL (operands[3]));
2599 operands[6] = gen_rtx (((GET_CODE (operands[1]) == GTU
2600 || GET_CODE (operands[1]) == GT)
2601 ? NE : EQ),
2602 DImode, operands[4], const0_rtx);
2603 }")
2604 \f
2605 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
2606 ;; work differently, so we have different patterns for each.
2607
2608 (define_expand "call"
2609 [(use (match_operand:DI 0 "" ""))
2610 (use (match_operand 1 "" ""))]
2611 ""
2612 "
2613 { if (WINDOWS_NT)
2614 emit_call_insn (gen_call_nt (operands[0], operands[1]));
2615 else
2616 emit_call_insn (gen_call_osf (operands[0], operands[1]));
2617
2618 DONE;
2619 }")
2620
2621 (define_expand "call_osf"
2622 [(parallel [(call (mem:DI (match_operand 0 "" ""))
2623 (match_operand 1 "" ""))
2624 (clobber (reg:DI 27))
2625 (clobber (reg:DI 26))])]
2626 ""
2627 "
2628 { if (GET_CODE (operands[0]) != MEM)
2629 abort ();
2630
2631 operands[0] = XEXP (operands[0], 0);
2632
2633 if (GET_CODE (operands[0]) != SYMBOL_REF
2634 && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
2635 {
2636 rtx tem = gen_rtx (REG, DImode, 27);
2637 emit_move_insn (tem, operands[0]);
2638 operands[0] = tem;
2639 }
2640 }")
2641
2642 (define_expand "call_nt"
2643 [(parallel [(call (mem:DI (match_operand:DI 0 "" ""))
2644 (match_operand 1 "" ""))
2645 (clobber (reg:DI 26))])]
2646 ""
2647 "
2648 { if (GET_CODE (operands[0]) != MEM)
2649 abort ();
2650 operands[0] = XEXP (operands[0], 0);
2651
2652 if (GET_CODE (operands[0]) != SYMBOL_REF)
2653 operands[0] = force_reg (Pmode, operands[0]);
2654 }")
2655
2656 (define_expand "call_value"
2657 [(use (match_operand 0 "" ""))
2658 (use (match_operand:DI 1 "" ""))
2659 (use (match_operand 2 "" ""))]
2660 ""
2661 "
2662 { if (WINDOWS_NT)
2663 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
2664 else
2665 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
2666 operands[2]));
2667 DONE;
2668 }")
2669
2670 (define_expand "call_value_osf"
2671 [(parallel [(set (match_operand 0 "" "")
2672 (call (mem:DI (match_operand 1 "" ""))
2673 (match_operand 2 "" "")))
2674 (clobber (reg:DI 27))
2675 (clobber (reg:DI 26))])]
2676 ""
2677 "
2678 { if (GET_CODE (operands[1]) != MEM)
2679 abort ();
2680
2681 operands[1] = XEXP (operands[1], 0);
2682
2683 if (GET_CODE (operands[1]) != SYMBOL_REF
2684 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
2685 {
2686 rtx tem = gen_rtx (REG, DImode, 27);
2687 emit_move_insn (tem, operands[1]);
2688 operands[1] = tem;
2689 }
2690 }")
2691
2692 (define_expand "call_value_nt"
2693 [(parallel [(set (match_operand 0 "" "")
2694 (call (mem:DI (match_operand:DI 1 "" ""))
2695 (match_operand 2 "" "")))
2696 (clobber (reg:DI 26))])]
2697 ""
2698 "
2699 { if (GET_CODE (operands[1]) != MEM)
2700 abort ();
2701
2702 operands[1] = XEXP (operands[1], 0);
2703 if (GET_CODE (operands[1]) != SYMBOL_REF)
2704 operands[1] = force_reg (Pmode, operands[1]);
2705 }")
2706
2707 (define_insn ""
2708 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
2709 (match_operand 1 "" ""))
2710 (clobber (reg:DI 27))
2711 (clobber (reg:DI 26))]
2712 "! WINDOWS_NT"
2713 "@
2714 jsr $26,($27),0\;ldgp $29,0($26)
2715 bsr $26,%0..ng
2716 jsr $26,%0\;ldgp $29,0($26)"
2717 [(set_attr "type" "jsr,jsr,ibr")])
2718
2719 (define_insn ""
2720 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
2721 (match_operand 1 "" ""))
2722 (clobber (reg:DI 26))]
2723 "WINDOWS_NT"
2724 "@
2725 jsr $26,(%0)
2726 bsr $26,%0"
2727 [(set_attr "type" "jsr")])
2728
2729 (define_insn ""
2730 [(set (match_operand 0 "register_operand" "=rf,rf,rf")
2731 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
2732 (match_operand 2 "" "")))
2733 (clobber (reg:DI 27))
2734 (clobber (reg:DI 26))]
2735 "! WINDOWS_NT"
2736 "@
2737 jsr $26,($27),0\;ldgp $29,0($26)
2738 bsr $26,%1..ng
2739 jsr $26,%1\;ldgp $29,0($26)"
2740 [(set_attr "type" "jsr,jsr,ibr")])
2741
2742 (define_insn ""
2743 [(set (match_operand 0 "register_operand" "=rf,rf")
2744 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
2745 (match_operand 2 "" "")))
2746 (clobber (reg:DI 26))]
2747 "WINDOWS_NT"
2748 "@
2749 jsr $26,(%1)
2750 bsr $26,%1"
2751 [(set_attr "type" "jsr")])
2752
2753 ;; Call subroutine returning any type.
2754
2755 (define_expand "untyped_call"
2756 [(parallel [(call (match_operand 0 "" "")
2757 (const_int 0))
2758 (match_operand 1 "" "")
2759 (match_operand 2 "" "")])]
2760 ""
2761 "
2762 {
2763 int i;
2764
2765 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
2766
2767 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2768 {
2769 rtx set = XVECEXP (operands[2], 0, i);
2770 emit_move_insn (SET_DEST (set), SET_SRC (set));
2771 }
2772
2773 /* The optimizer does not know that the call sets the function value
2774 registers we stored in the result block. We avoid problems by
2775 claiming that all hard registers are used and clobbered at this
2776 point. */
2777 emit_insn (gen_blockage ());
2778
2779 DONE;
2780 }")
2781
2782 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2783 ;; all of memory. This blocks insns from being moved across this point.
2784
2785 (define_insn "blockage"
2786 [(unspec_volatile [(const_int 0)] 1)]
2787 ""
2788 "")
2789
2790 (define_insn "jump"
2791 [(set (pc)
2792 (label_ref (match_operand 0 "" "")))]
2793 ""
2794 "br $31,%l0"
2795 [(set_attr "type" "ibr")])
2796
2797 (define_insn "return"
2798 [(return)]
2799 "direct_return ()"
2800 "ret $31,($26),1"
2801 [(set_attr "type" "ibr")])
2802
2803 (define_insn "indirect_jump"
2804 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
2805 ""
2806 "jmp $31,(%0),0"
2807 [(set_attr "type" "ibr")])
2808
2809 (define_insn "nop"
2810 [(const_int 0)]
2811 ""
2812 "bis $31,$31,$31"
2813 [(set_attr "type" "iaddlog")])
2814
2815 (define_expand "tablejump"
2816 [(use (match_operand:SI 0 "register_operand" ""))
2817 (use (match_operand:SI 1 "" ""))]
2818 ""
2819 "
2820 {
2821 if (WINDOWS_NT)
2822 emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
2823 else
2824 emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
2825
2826 DONE;
2827 }")
2828
2829 (define_expand "tablejump_osf"
2830 [(set (match_dup 3)
2831 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
2832 (parallel [(set (pc)
2833 (plus:DI (match_dup 3)
2834 (label_ref:DI (match_operand 1 "" ""))))
2835 (clobber (match_scratch:DI 2 "=r"))])]
2836 ""
2837 "
2838 { operands[3] = gen_reg_rtx (DImode); }")
2839
2840 (define_expand "tablejump_nt"
2841 [(set (match_dup 3)
2842 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
2843 (parallel [(set (pc)
2844 (match_dup 3))
2845 (use (label_ref (match_operand 1 "" "")))])]
2846 ""
2847 "
2848 { operands[3] = gen_reg_rtx (DImode); }")
2849
2850 (define_insn ""
2851 [(set (pc)
2852 (plus:DI (match_operand:DI 0 "register_operand" "r")
2853 (label_ref:DI (match_operand 1 "" ""))))
2854 (clobber (match_scratch:DI 2 "=r"))]
2855 "! WINDOWS_NT && next_active_insn (insn) != 0
2856 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
2857 && PREV_INSN (next_active_insn (insn)) == operands[1]"
2858 "*
2859 { rtx best_label = 0;
2860 rtx jump_table_insn = next_active_insn (operands[1]);
2861
2862 if (GET_CODE (jump_table_insn) == JUMP_INSN
2863 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
2864 {
2865 rtx jump_table = PATTERN (jump_table_insn);
2866 int n_labels = XVECLEN (jump_table, 1);
2867 int best_count = -1;
2868 int i, j;
2869
2870 for (i = 0; i < n_labels; i++)
2871 {
2872 int count = 1;
2873
2874 for (j = i + 1; j < n_labels; j++)
2875 if (XEXP (XVECEXP (jump_table, 1, i), 0)
2876 == XEXP (XVECEXP (jump_table, 1, j), 0))
2877 count++;
2878
2879 if (count > best_count)
2880 best_count = count, best_label = XVECEXP (jump_table, 1, i);
2881 }
2882 }
2883
2884 if (best_label)
2885 {
2886 operands[3] = best_label;
2887 return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
2888 }
2889 else
2890 return \"addq %0,$29,%2\;jmp $31,(%2),0\";
2891 }"
2892 [(set_attr "type" "ibr")])
2893
2894 (define_insn ""
2895 [(set (pc)
2896 (match_operand:DI 0 "register_operand" "r"))
2897 (use (label_ref (match_operand 1 "" "")))]
2898 "WINDOWS_NT && next_active_insn (insn) != 0
2899 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
2900 && PREV_INSN (next_active_insn (insn)) == operands[1]"
2901 "*
2902 { rtx best_label = 0;
2903 rtx jump_table_insn = next_active_insn (operands[1]);
2904
2905 if (GET_CODE (jump_table_insn) == JUMP_INSN
2906 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
2907 {
2908 rtx jump_table = PATTERN (jump_table_insn);
2909 int n_labels = XVECLEN (jump_table, 1);
2910 int best_count = -1;
2911 int i, j;
2912
2913 for (i = 0; i < n_labels; i++)
2914 {
2915 int count = 1;
2916
2917 for (j = i + 1; j < n_labels; j++)
2918 if (XEXP (XVECEXP (jump_table, 1, i), 0)
2919 == XEXP (XVECEXP (jump_table, 1, j), 0))
2920 count++;
2921
2922 if (count > best_count)
2923 best_count = count, best_label = XVECEXP (jump_table, 1, i);
2924 }
2925 }
2926
2927 if (best_label)
2928 {
2929 operands[2] = best_label;
2930 return \"jmp $31,(%0),%2\";
2931 }
2932 else
2933 return \"jmp $31,(%0),0\";
2934 }"
2935 [(set_attr "type" "ibr")])
2936
2937 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
2938 ;; want to have to include pal.h in our .s file.
2939 (define_insn ""
2940 [(unspec_volatile [(const_int 0)] 0)]
2941 ""
2942 "call_pal 0x86")
2943 \f
2944 ;; Finally, we have the basic data motion insns. The byte and word insns
2945 ;; are done via define_expand. Start with the floating-point insns, since
2946 ;; they are simpler.
2947
2948 (define_insn ""
2949 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
2950 (match_operand:SF 1 "input_operand" "rG,m,rG,f,G,m,fG"))]
2951 "register_operand (operands[0], SFmode)
2952 || reg_or_fp0_operand (operands[1], SFmode)"
2953 "@
2954 bis %r1,%r1,%0
2955 ldl %0,%1
2956 stl %r1,%0
2957 cpys %1,%1,%0
2958 cpys $f31,$f31,%0
2959 lds %0,%1
2960 sts %R1,%0"
2961 [(set_attr "type" "iaddlog,ld,st,fpop,fpop,ld,st")])
2962
2963 (define_insn ""
2964 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
2965 (match_operand:DF 1 "input_operand" "rG,m,rG,f,G,m,fG"))]
2966 "register_operand (operands[0], DFmode)
2967 || reg_or_fp0_operand (operands[1], DFmode)"
2968 "@
2969 bis %r1,%r1,%0
2970 ldq %0,%1
2971 stq %r1,%0
2972 cpys %1,%1,%0
2973 cpys $f31,$f31,%0
2974 ldt %0,%1
2975 stt %R1,%0"
2976 [(set_attr "type" "iaddlog,ld,st,fpop,fpop,ld,st")])
2977
2978 (define_expand "movsf"
2979 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2980 (match_operand:SF 1 "general_operand" ""))]
2981 ""
2982 "
2983 {
2984 if (GET_CODE (operands[0]) == MEM
2985 && ! reg_or_fp0_operand (operands[1], SFmode))
2986 operands[1] = force_reg (SFmode, operands[1]);
2987 }")
2988
2989 (define_expand "movdf"
2990 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2991 (match_operand:DF 1 "general_operand" ""))]
2992 ""
2993 "
2994 {
2995 if (GET_CODE (operands[0]) == MEM
2996 && ! reg_or_fp0_operand (operands[1], DFmode))
2997 operands[1] = force_reg (DFmode, operands[1]);
2998 }")
2999
3000 (define_insn ""
3001 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,f,f,f,m")
3002 (match_operand:SI 1 "input_operand" "r,J,I,K,L,m,rJ,f,J,m,fG"))]
3003 "! WINDOWS_NT && (register_operand (operands[0], SImode)
3004 || reg_or_0_operand (operands[1], SImode))"
3005 "@
3006 bis %1,%1,%0
3007 bis $31,$31,%0
3008 bis $31,%1,%0
3009 lda %0,%1
3010 ldah %0,%h1
3011 ldl %0,%1
3012 stl %r1,%0
3013 cpys %1,%1,%0
3014 cpys $f31,$f31,%0
3015 lds %0,%1
3016 sts %R1,%0"
3017 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ld,st,fpop,fpop,ld,st")])
3018
3019 (define_insn ""
3020 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,f,f,f,m")
3021 (match_operand:SI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,m,fG"))]
3022 "WINDOWS_NT && (register_operand (operands[0], SImode)
3023 || reg_or_0_operand (operands[1], SImode))"
3024 "@
3025 bis %1,%1,%0
3026 bis $31,$31,%0
3027 bis $31,%1,%0
3028 lda %0,%1
3029 ldah %0,%h1
3030 lda %0,%1
3031 ldl %0,%1
3032 stl %r1,%0
3033 cpys %1,%1,%0
3034 cpys $f31,$f31,%0
3035 lds %0,%1
3036 sts %R1,%0"
3037 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ldsym,ld,st,fpop,fpop,ld,st")])
3038
3039 (define_insn ""
3040 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,f,f")
3041 (match_operand:HI 1 "input_operand" "r,J,I,n,f,J"))]
3042 "register_operand (operands[0], HImode)
3043 || register_operand (operands[1], HImode)"
3044 "@
3045 bis %1,%1,%0
3046 bis $31,$31,%0
3047 bis $31,%1,%0
3048 lda %0,%L1
3049 cpys %1,%1,%0
3050 cpys $f31,$f31,%0"
3051 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,fpop,fpop")])
3052
3053 (define_insn ""
3054 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,f,f")
3055 (match_operand:QI 1 "input_operand" "r,J,I,n,f,J"))]
3056 "register_operand (operands[0], QImode)
3057 || register_operand (operands[1], QImode)"
3058 "@
3059 bis %1,%1,%0
3060 bis $31,$31,%0
3061 bis $31,%1,%0
3062 lda %0,%L1
3063 cpys %1,%1,%0
3064 cpys $f31,$f31,%0"
3065 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,fpop,fpop")])
3066
3067 ;; We do two major things here: handle mem->mem and construct long
3068 ;; constants.
3069
3070 (define_expand "movsi"
3071 [(set (match_operand:SI 0 "general_operand" "")
3072 (match_operand:SI 1 "general_operand" ""))]
3073 ""
3074 "
3075 {
3076 if (GET_CODE (operands[0]) == MEM
3077 && ! reg_or_0_operand (operands[1], SImode))
3078 operands[1] = force_reg (SImode, operands[1]);
3079
3080 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
3081 ;
3082 else if (GET_CODE (operands[1]) == CONST_INT)
3083 {
3084 operands[1]
3085 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
3086 if (rtx_equal_p (operands[0], operands[1]))
3087 DONE;
3088 }
3089 }")
3090
3091 ;; Split a load of a large constant into the appropriate two-insn
3092 ;; sequence.
3093
3094 (define_split
3095 [(set (match_operand:SI 0 "register_operand" "")
3096 (match_operand:SI 1 "const_int_operand" ""))]
3097 "! add_operand (operands[1], SImode)"
3098 [(set (match_dup 0) (match_dup 2))
3099 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
3100 "
3101 { rtx tem
3102 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
3103
3104 if (tem == operands[0])
3105 DONE;
3106 else
3107 FAIL;
3108 }")
3109
3110 (define_insn ""
3111 [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,r,r,m,f,f,f,Q")
3112 (match_operand:DI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,Q,fG"))]
3113 "register_operand (operands[0], DImode)
3114 || reg_or_0_operand (operands[1], DImode)"
3115 "@
3116 bis %1,%1,%0
3117 bis $31,$31,%0
3118 bis $31,%1,%0
3119 lda %0,%1
3120 ldah %0,%h1
3121 lda %0,%1
3122 ldq%A1 %0,%1
3123 stq%A0 %r1,%0
3124 cpys %1,%1,%0
3125 cpys $f31,$f31,%0
3126 ldt %0,%1
3127 stt %R1,%0"
3128 [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ldsym,ld,st,fpop,fpop,ld,st")])
3129
3130 ;; We do three major things here: handle mem->mem, put 64-bit constants in
3131 ;; memory, and construct long 32-bit constants.
3132
3133 (define_expand "movdi"
3134 [(set (match_operand:DI 0 "general_operand" "")
3135 (match_operand:DI 1 "general_operand" ""))]
3136 ""
3137 "
3138 {
3139 rtx tem;
3140
3141 if (GET_CODE (operands[0]) == MEM
3142 && ! reg_or_0_operand (operands[1], DImode))
3143 operands[1] = force_reg (DImode, operands[1]);
3144
3145 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
3146 ;
3147 else if (GET_CODE (operands[1]) == CONST_INT
3148 && (tem = alpha_emit_set_const (operands[0], DImode,
3149 INTVAL (operands[1]), 3)) != 0)
3150 {
3151 if (rtx_equal_p (tem, operands[0]))
3152 DONE;
3153 else
3154 operands[1] = tem;
3155 }
3156 else if (CONSTANT_P (operands[1]))
3157 {
3158 operands[1] = force_const_mem (DImode, operands[1]);
3159 if (reload_in_progress)
3160 {
3161 emit_move_insn (operands[0], XEXP (operands[1], 0));
3162 XEXP (operands[1], 0) = operands[0];
3163 }
3164 else
3165 operands[1] = validize_mem (operands[1]);
3166 }
3167 else
3168 abort ();
3169 }")
3170
3171 ;; Split a load of a large constant into the appropriate two-insn
3172 ;; sequence.
3173
3174 (define_split
3175 [(set (match_operand:DI 0 "register_operand" "")
3176 (match_operand:DI 1 "const_int_operand" ""))]
3177 "! add_operand (operands[1], DImode)"
3178 [(set (match_dup 0) (match_dup 2))
3179 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
3180 "
3181 { rtx tem
3182 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
3183
3184 if (tem == operands[0])
3185 DONE;
3186 else
3187 FAIL;
3188 }")
3189
3190 ;; These are the partial-word cases.
3191 ;;
3192 ;; First we have the code to load an aligned word. Operand 0 is the register
3193 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
3194 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
3195 ;; number of bits within the word that the value is. Operand 3 is an SImode
3196 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
3197 ;; same register. It is allowed to conflict with operand 1 as well.
3198
3199 (define_expand "aligned_loadqi"
3200 [(set (match_operand:SI 3 "register_operand" "")
3201 (match_operand:SI 1 "memory_operand" ""))
3202 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
3203 (zero_extract:DI (subreg:DI (match_dup 3) 0)
3204 (const_int 8)
3205 (match_operand:DI 2 "const_int_operand" "")))]
3206
3207 ""
3208 "")
3209
3210 (define_expand "aligned_loadhi"
3211 [(set (match_operand:SI 3 "register_operand" "")
3212 (match_operand:SI 1 "memory_operand" ""))
3213 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
3214 (zero_extract:DI (subreg:DI (match_dup 3) 0)
3215 (const_int 16)
3216 (match_operand:DI 2 "const_int_operand" "")))]
3217
3218 ""
3219 "")
3220
3221 ;; Similar for unaligned loads. For QImode, we use the sequence from the
3222 ;; Alpha Architecture manual. However, for HImode, we do not. HImode pointers
3223 ;; are normally aligned to the byte boundary, so an HImode object cannot
3224 ;; cross a longword boundary. We could use a sequence similar to that for
3225 ;; QImode, but that would fail if the pointer, was, in fact, not aligned.
3226 ;; Instead, we clear bit 1 in the address and do an ldl. If the low-order
3227 ;; bit was not aligned, this will trap and the trap handler will do what is
3228 ;; needed.
3229 ;;
3230 ;; Here operand 1 is the address. Operands 2 and 3 are temporaries, where
3231 ;; operand 3 can overlap the input and output registers.
3232
3233 (define_expand "unaligned_loadqi"
3234 [(set (match_operand:DI 2 "register_operand" "")
3235 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
3236 (const_int -8))))
3237 (set (match_operand:DI 3 "register_operand" "")
3238 (match_dup 1))
3239 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
3240 (zero_extract:DI (match_dup 2)
3241 (const_int 8)
3242 (ashift:DI (match_dup 3) (const_int 3))))]
3243 ""
3244 "")
3245
3246 ;; For this, the address must already be in a register. We also need two
3247 ;; DImode temporaries, neither of which may overlap the input (and hence the
3248 ;; output, since they might be the same register), but both of which may
3249 ;; be the same.
3250
3251 (define_expand "unaligned_loadhi"
3252 [(set (match_operand:DI 2 "register_operand" "")
3253 (and:DI (match_operand:DI 1 "register_operand" "")
3254 (const_int -7)))
3255 (set (match_operand:DI 3 "register_operand" "")
3256 (mem:DI (match_dup 2)))
3257 (set (match_operand:DI 4 "register_operand" "")
3258 (and:DI (match_dup 1) (const_int -2)))
3259 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
3260 (zero_extract:DI (match_dup 3)
3261 (const_int 16)
3262 (ashift:DI (match_dup 4) (const_int 3))))]
3263 ""
3264 "")
3265
3266 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
3267 ;; aligned SImode MEM. Operand 1 is the register containing the
3268 ;; byte or word to store. Operand 2 is the number of bits within the word that
3269 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
3270
3271 (define_expand "aligned_store"
3272 [(set (match_operand:SI 3 "register_operand" "")
3273 (match_operand:SI 0 "memory_operand" ""))
3274 (set (subreg:DI (match_dup 3) 0)
3275 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
3276 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
3277 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
3278 (match_operand:DI 2 "const_int_operand" "")))
3279 (set (subreg:DI (match_dup 4) 0)
3280 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
3281 (set (match_dup 0) (match_dup 4))]
3282 ""
3283 "
3284 { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
3285 << INTVAL (operands[2])));
3286 }")
3287
3288 ;; For the unaligned byte case, we use code similar to that in the
3289 ;; Architecture book, but reordered to lower the number of registers
3290 ;; required. Operand 0 is the address. Operand 1 is the data to store.
3291 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
3292 ;; be the same temporary, if desired. If the address is in a register,
3293 ;; operand 2 can be that register.
3294
3295 (define_expand "unaligned_storeqi"
3296 [(set (match_operand:DI 3 "register_operand" "")
3297 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
3298 (const_int -8))))
3299 (set (match_operand:DI 2 "register_operand" "")
3300 (match_dup 0))
3301 (set (match_dup 3)
3302 (and:DI (not:DI (ashift:DI (const_int 255)
3303 (ashift:DI (match_dup 2) (const_int 3))))
3304 (match_dup 3)))
3305 (set (match_operand:DI 4 "register_operand" "")
3306 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
3307 (ashift:DI (match_dup 2) (const_int 3))))
3308 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
3309 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
3310 (match_dup 4))]
3311 ""
3312 "")
3313
3314 ;; This is the code for storing into an unaligned short. It uses the same
3315 ;; trick as loading from an unaligned short. It needs lots of temporaries.
3316 ;; However, during reload, we only have two registers available. So we
3317 ;; repeat code so that only two temporaries are available. During RTL
3318 ;; generation, we can use different pseudos for each temporary and CSE
3319 ;; will remove the redundancies. During reload, we have to settle with
3320 ;; what we get. Luckily, unaligned accesses of this kind produced during
3321 ;; reload are quite rare.
3322 ;;
3323 ;; Operand 0 is the address of the memory location. Operand 1 contains the
3324 ;; data to store. The rest of the operands are all temporaries, with
3325 ;; various overlap possibilities during reload. See reload_outhi for
3326 ;; details of this use.
3327
3328 (define_expand "unaligned_storehi"
3329 [(set (match_operand:DI 2 "register_operand" "")
3330 (match_operand:DI 0 "address_operand" ""))
3331 (set (match_operand:DI 3 "register_operand" "")
3332 (and:DI (match_dup 2) (const_int -7)))
3333 (set (match_operand:DI 4 "register_operand" "")
3334 (mem:DI (match_dup 3)))
3335 (set (match_operand:DI 10 "register_operand" "")
3336 (and:DI (match_dup 2) (const_int -2)))
3337 (set (match_operand:DI 5 "register_operand" "")
3338 (and:DI (not:DI (ashift:DI (const_int 65535)
3339 (ashift:DI (match_dup 10) (const_int 3))))
3340 (match_dup 4)))
3341 (set (match_operand:DI 6 "register_operand" "")
3342 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
3343 (ashift:DI (match_dup 10) (const_int 3))))
3344 (set (match_operand:DI 7 "register_operand" "")
3345 (ior:DI (match_dup 5) (match_dup 6)))
3346 (set (match_operand:DI 8 "register_operand" "") (match_dup 0))
3347 (set (match_operand:DI 9 "register_operand" "")
3348 (and:DI (match_dup 8) (const_int -7)))
3349 (set (mem:DI (match_dup 9)) (match_dup 7))]
3350 ""
3351 "")
3352 \f
3353 ;; Here are the define_expand's for QI and HI moves that use the above
3354 ;; patterns. We have the normal sets, plus the ones that need scratch
3355 ;; registers for reload.
3356
3357 (define_expand "movqi"
3358 [(set (match_operand:QI 0 "general_operand" "")
3359 (match_operand:QI 1 "general_operand" ""))]
3360 ""
3361 "
3362 { extern rtx get_unaligned_address ();
3363
3364 /* If the output is not a register, the input must be. */
3365 if (GET_CODE (operands[0]) == MEM)
3366 operands[1] = force_reg (QImode, operands[1]);
3367
3368 /* Handle four memory cases, unaligned and aligned for either the input
3369 or the output. The only case where we can be called during reload is
3370 for aligned loads; all other cases require temporaries. */
3371
3372 if (GET_CODE (operands[1]) == MEM
3373 || (GET_CODE (operands[1]) == SUBREG
3374 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
3375 || (reload_in_progress && GET_CODE (operands[1]) == REG
3376 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
3377 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
3378 && GET_CODE (SUBREG_REG (operands[1])) == REG
3379 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
3380 {
3381 if (aligned_memory_operand (operands[1], QImode))
3382 {
3383 rtx aligned_mem, bitnum;
3384 rtx scratch = (reload_in_progress
3385 ? gen_rtx (REG, SImode, REGNO (operands[0]))
3386 : gen_reg_rtx (SImode));
3387
3388 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
3389
3390 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
3391 scratch));
3392 }
3393 else
3394 {
3395 /* Don't pass these as parameters since that makes the generated
3396 code depend on parameter evaluation order which will cause
3397 bootstrap failures. */
3398
3399 rtx temp1 = gen_reg_rtx (DImode);
3400 rtx temp2 = gen_reg_rtx (DImode);
3401 rtx seq = gen_unaligned_loadqi (operands[0],
3402 get_unaligned_address (operands[1]),
3403 temp1, temp2);
3404
3405 alpha_set_memflags (seq, operands[1]);
3406 emit_insn (seq);
3407 }
3408
3409 DONE;
3410 }
3411
3412 else if (GET_CODE (operands[0]) == MEM
3413 || (GET_CODE (operands[0]) == SUBREG
3414 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
3415 || (reload_in_progress && GET_CODE (operands[0]) == REG
3416 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
3417 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
3418 && GET_CODE (SUBREG_REG (operands[0])) == REG
3419 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
3420 {
3421 if (aligned_memory_operand (operands[0], QImode))
3422 {
3423 rtx aligned_mem, bitnum;
3424 rtx temp1 = gen_reg_rtx (SImode);
3425 rtx temp2 = gen_reg_rtx (SImode);
3426
3427 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
3428
3429 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
3430 temp1, temp2));
3431 }
3432 else
3433 {
3434 rtx temp1 = gen_reg_rtx (DImode);
3435 rtx temp2 = gen_reg_rtx (DImode);
3436 rtx temp3 = gen_reg_rtx (DImode);
3437 rtx seq = gen_unaligned_storeqi (get_unaligned_address (operands[0]),
3438 operands[1], temp1, temp2, temp3);
3439
3440 alpha_set_memflags (seq, operands[0]);
3441 emit_insn (seq);
3442 }
3443 DONE;
3444 }
3445 }")
3446
3447 (define_expand "movhi"
3448 [(set (match_operand:HI 0 "general_operand" "")
3449 (match_operand:HI 1 "general_operand" ""))]
3450 ""
3451 "
3452 { extern rtx get_unaligned_address ();
3453
3454 /* If the output is not a register, the input must be. */
3455 if (GET_CODE (operands[0]) == MEM)
3456 operands[1] = force_reg (HImode, operands[1]);
3457
3458 /* Handle four memory cases, unaligned and aligned for either the input
3459 or the output. The only case where we can be called during reload is
3460 for aligned loads; all other cases require temporaries. */
3461
3462 if (GET_CODE (operands[1]) == MEM
3463 || (GET_CODE (operands[1]) == SUBREG
3464 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
3465 || (reload_in_progress && GET_CODE (operands[1]) == REG
3466 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
3467 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
3468 && GET_CODE (SUBREG_REG (operands[1])) == REG
3469 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
3470 {
3471 if (aligned_memory_operand (operands[1], HImode))
3472 {
3473 rtx aligned_mem, bitnum;
3474 rtx scratch = (reload_in_progress
3475 ? gen_rtx (REG, SImode, REGNO (operands[0]))
3476 : gen_reg_rtx (SImode));
3477
3478 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
3479
3480 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
3481 scratch));
3482 }
3483 else
3484 {
3485 rtx addr
3486 = force_reg (DImode,
3487 force_operand (get_unaligned_address (operands[1]),
3488 NULL_RTX));
3489 rtx scratch1 = gen_reg_rtx (DImode);
3490 rtx scratch2 = gen_reg_rtx (DImode);
3491 rtx scratch3 = gen_reg_rtx (DImode);
3492
3493 rtx seq = gen_unaligned_loadhi (operands[0], addr, scratch1,
3494 scratch2, scratch3);
3495
3496 alpha_set_memflags (seq, operands[1]);
3497 emit_insn (seq);
3498 }
3499
3500 DONE;
3501 }
3502
3503 else if (GET_CODE (operands[0]) == MEM
3504 || (GET_CODE (operands[0]) == SUBREG
3505 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
3506 || (reload_in_progress && GET_CODE (operands[0]) == REG
3507 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
3508 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
3509 && GET_CODE (SUBREG_REG (operands[0])) == REG
3510 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
3511 {
3512 if (aligned_memory_operand (operands[0], HImode))
3513 {
3514 rtx aligned_mem, bitnum;
3515 rtx temp1 = gen_reg_rtx (SImode);
3516 rtx temp2 = gen_reg_rtx (SImode);
3517
3518 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
3519
3520 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
3521 temp1, temp2));
3522 }
3523 else
3524 {
3525 rtx temp1 = gen_reg_rtx (DImode);
3526 rtx temp2 = gen_reg_rtx (DImode);
3527 rtx temp3 = gen_reg_rtx (DImode);
3528 rtx temp4 = gen_reg_rtx (DImode);
3529 rtx temp5 = gen_reg_rtx (DImode);
3530 rtx temp6 = gen_reg_rtx (DImode);
3531 rtx temp7 = gen_reg_rtx (DImode);
3532 rtx temp8 = gen_reg_rtx (DImode);
3533 rtx temp9 = gen_reg_rtx (DImode);
3534
3535 rtx seq = gen_unaligned_storehi (get_unaligned_address (operands[0]),
3536 operands[1], temp1, temp2,temp3,
3537 temp4, temp5, temp6,temp7,
3538 temp8, temp9);
3539
3540 alpha_set_memflags (seq, operands[0]);
3541 emit_insn (seq);
3542 }
3543
3544 DONE;
3545 }
3546 }")
3547
3548 ;; Here are the versions for reload. Note that in the unaligned cases
3549 ;; we know that the operand must not be a pseudo-register because stack
3550 ;; slots are always aligned references.
3551
3552 (define_expand "reload_inqi"
3553 [(parallel [(match_operand:QI 0 "register_operand" "=r")
3554 (match_operand:QI 1 "unaligned_memory_operand" "m")
3555 (match_operand:TI 2 "register_operand" "=&r")])]
3556 ""
3557 "
3558 { extern rtx get_unaligned_address ();
3559 rtx addr = get_unaligned_address (operands[1]);
3560 /* It is possible that one of the registers we got for operands[2]
3561 might coincide with that of operands[0] (which is why we made
3562 it TImode). Pick the other one to use as our scratch. */
3563 rtx scratch = gen_rtx (REG, DImode,
3564 REGNO (operands[0]) == REGNO (operands[2])
3565 ? REGNO (operands[2]) + 1 : REGNO (operands[2]));
3566 rtx seq = gen_unaligned_loadqi (operands[0], addr, scratch,
3567 gen_rtx (REG, DImode, REGNO (operands[0])));
3568
3569 alpha_set_memflags (seq, operands[1]);
3570 emit_insn (seq);
3571 DONE;
3572 }")
3573
3574 (define_expand "reload_inhi"
3575 [(parallel [(match_operand:HI 0 "register_operand" "=r")
3576 (match_operand:HI 1 "unaligned_memory_operand" "m")
3577 (match_operand:TI 2 "register_operand" "=&r")])]
3578 ""
3579 "
3580 { extern rtx get_unaligned_address ();
3581 rtx addr = get_unaligned_address (operands[1]);
3582 rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2]));
3583 rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1);
3584 rtx seq;
3585
3586 if (GET_CODE (addr) != REG)
3587 {
3588 emit_insn (gen_rtx (SET, VOIDmode, scratch2, addr));
3589 addr = scratch2;
3590 }
3591
3592 seq = gen_unaligned_loadhi (operands[0], addr, scratch1, scratch1, scratch2);
3593 alpha_set_memflags (seq, operands[1]);
3594 emit_insn (seq);
3595 DONE;
3596 }")
3597
3598 (define_expand "reload_outqi"
3599 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
3600 (match_operand:QI 1 "register_operand" "r")
3601 (match_operand:TI 2 "register_operand" "=&r")])]
3602 ""
3603 "
3604 { extern rtx get_unaligned_address ();
3605
3606 if (aligned_memory_operand (operands[0], QImode))
3607 {
3608 rtx aligned_mem, bitnum;
3609
3610 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
3611
3612 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
3613 gen_rtx (REG, SImode, REGNO (operands[2])),
3614 gen_rtx (REG, SImode,
3615 REGNO (operands[2]) + 1)));
3616 }
3617 else
3618 {
3619 rtx addr = get_unaligned_address (operands[0]);
3620 rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2]));
3621 rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1);
3622 rtx scratch3 = scratch1;
3623 rtx seq;
3624
3625 if (GET_CODE (addr) == REG)
3626 scratch1 = addr;
3627
3628 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
3629 scratch2, scratch3);
3630 alpha_set_memflags (seq, operands[0]);
3631 emit_insn (seq);
3632 }
3633
3634 DONE;
3635 }")
3636
3637 (define_expand "reload_outhi"
3638 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
3639 (match_operand:HI 1 "register_operand" "r")
3640 (match_operand:TI 2 "register_operand" "=&r")])]
3641 ""
3642 "
3643 { extern rtx get_unaligned_address ();
3644
3645 if (aligned_memory_operand (operands[0], HImode))
3646 {
3647 rtx aligned_mem, bitnum;
3648
3649 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
3650
3651 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
3652 gen_rtx (REG, SImode, REGNO (operands[2])),
3653 gen_rtx (REG, SImode,
3654 REGNO (operands[2]) + 1)));
3655 }
3656 else
3657 {
3658 rtx addr = get_unaligned_address (operands[0]);
3659 rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2]));
3660 rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1);
3661 rtx scratch_a = GET_CODE (addr) == REG ? addr : scratch1;
3662 rtx seq;
3663
3664 seq = gen_unaligned_storehi (addr, operands[1], scratch_a,
3665 scratch2, scratch2, scratch2,
3666 scratch1, scratch2, scratch_a,
3667 scratch1, scratch_a);
3668 alpha_set_memflags (seq, operands[0]);
3669 emit_insn (seq);
3670 }
3671
3672 DONE;
3673 }")
3674 \f
3675 ;; Subroutine of stack space allocation. Perform a stack probe.
3676 (define_expand "probe_stack"
3677 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
3678 ""
3679 "
3680 {
3681 operands[1] = gen_rtx (MEM, DImode, plus_constant (stack_pointer_rtx,
3682 INTVAL (operands[0])));
3683 MEM_VOLATILE_P (operands[1]) = 1;
3684
3685 operands[0] = const0_rtx;
3686 }")
3687
3688 ;; This is how we allocate stack space. If we are allocating a
3689 ;; constant amount of space and we know it is less than 4096
3690 ;; bytes, we need do nothing.
3691 ;;
3692 ;; If it is more than 4096 bytes, we need to probe the stack
3693 ;; periodically.
3694 (define_expand "allocate_stack"
3695 [(set (reg:DI 30)
3696 (plus:DI (reg:DI 30)
3697 (match_operand:DI 0 "reg_or_cint_operand" "")))]
3698 ""
3699 "
3700 {
3701 if (GET_CODE (operands[0]) == CONST_INT
3702 && INTVAL (operands[0]) < 32768)
3703 {
3704 if (INTVAL (operands[0]) >= 4096)
3705 {
3706 /* We do this the same way as in the prologue and generate explicit
3707 probes. Then we update the stack by the constant. */
3708
3709 int probed = 4096;
3710
3711 emit_insn (gen_probe_stack (GEN_INT (- probed)));
3712 while (probed + 8192 < INTVAL (operands[0]))
3713 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
3714
3715 if (probed + 4096 < INTVAL (operands[0]))
3716 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[0]))));
3717 }
3718
3719 operands[0] = GEN_INT (- INTVAL (operands[0]));
3720 }
3721 else
3722 {
3723 rtx out_label = 0;
3724 rtx loop_label = gen_label_rtx ();
3725 rtx want = gen_reg_rtx (Pmode);
3726 rtx tmp = gen_reg_rtx (Pmode);
3727 rtx memref;
3728
3729 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
3730 force_reg (Pmode, operands[0])));
3731 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
3732
3733 if (GET_CODE (operands[0]) != CONST_INT)
3734 {
3735 out_label = gen_label_rtx ();
3736 emit_insn (gen_cmpdi (want, tmp));
3737 emit_jump_insn (gen_bgeu (out_label));
3738 }
3739
3740 emit_label (loop_label);
3741 memref = gen_rtx (MEM, DImode, tmp);
3742 MEM_VOLATILE_P (memref) = 1;
3743 emit_move_insn (memref, const0_rtx);
3744 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
3745 emit_insn (gen_cmpdi (tmp, want));
3746 emit_jump_insn (gen_bgtu (loop_label));
3747 memref = gen_rtx (MEM, DImode, want);
3748 MEM_VOLATILE_P (memref) = 1;
3749 emit_move_insn (memref, const0_rtx);
3750
3751 if (out_label)
3752 emit_label (out_label);
3753
3754 emit_move_insn (stack_pointer_rtx, want);
3755
3756 DONE;
3757 }
3758 }")
GNU Compiler Collection
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