1 /* Definitions of target machine for GNU compiler, for DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* For C++ we need to ensure that __LANGUAGE_C_PLUS_PLUS is defined independent
25 of the source file extension. */
26 #define CPLUSPLUS_CPP_SPEC "\
27 -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus \
31 /* Write out the correct language type definition for the header files.
32 Unless we have assembler language, write out the symbols for C. */
35 %{.S:-D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY }}\
36 %{.m:-D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C }\
37 %{!.S:%{!.cc:%{!.cxx:%{!.cpp:%{!.cp:%{!.c++:%{!.C:%{!.m:-D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C }}}}}}}}}\
39 %{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT }}\
40 %(cpp_cpu) %(cpp_subtarget)"
42 #ifndef CPP_SUBTARGET_SPEC
43 #define CPP_SUBTARGET_SPEC ""
46 #define WORD_SWITCH_TAKES_ARG(STR) \
47 (!strcmp (STR, "rpath") || DEFAULT_WORD_SWITCH_TAKES_ARG(STR))
49 /* Print subsidiary information on the compiler version in use. */
50 #define TARGET_VERSION
52 /* Run-time compilation parameters selecting different hardware subsets. */
54 /* Which processor to schedule for. The cpu attribute defines a list that
55 mirrors this list, so changes to alpha.md must be made at the same time. */
58 {PROCESSOR_EV4
, /* 2106[46]{a,} */
59 PROCESSOR_EV5
, /* 21164{a,pc,} */
60 PROCESSOR_EV6
}; /* 21264 */
62 extern enum processor_type alpha_cpu
;
64 enum alpha_trap_precision
66 ALPHA_TP_PROG
, /* No precision (default). */
67 ALPHA_TP_FUNC
, /* Trap contained within originating function. */
68 ALPHA_TP_INSN
/* Instruction accuracy and code is resumption safe. */
71 enum alpha_fp_rounding_mode
73 ALPHA_FPRM_NORM
, /* Normal rounding mode. */
74 ALPHA_FPRM_MINF
, /* Round towards minus-infinity. */
75 ALPHA_FPRM_CHOP
, /* Chopped rounding mode (towards 0). */
76 ALPHA_FPRM_DYN
/* Dynamic rounding mode. */
79 enum alpha_fp_trap_mode
81 ALPHA_FPTM_N
, /* Normal trap mode. */
82 ALPHA_FPTM_U
, /* Underflow traps enabled. */
83 ALPHA_FPTM_SU
, /* Software completion, w/underflow traps */
84 ALPHA_FPTM_SUI
/* Software completion, w/underflow & inexact traps */
87 extern int target_flags
;
89 extern enum alpha_trap_precision alpha_tp
;
90 extern enum alpha_fp_rounding_mode alpha_fprm
;
91 extern enum alpha_fp_trap_mode alpha_fptm
;
93 /* This means that floating-point support exists in the target implementation
94 of the Alpha architecture. This is usually the default. */
95 #define MASK_FP (1 << 0)
96 #define TARGET_FP (target_flags & MASK_FP)
98 /* This means that floating-point registers are allowed to be used. Note
99 that Alpha implementations without FP operations are required to
100 provide the FP registers. */
102 #define MASK_FPREGS (1 << 1)
103 #define TARGET_FPREGS (target_flags & MASK_FPREGS)
105 /* This means that gas is used to process the assembler file. */
107 #define MASK_GAS (1 << 2)
108 #define TARGET_GAS (target_flags & MASK_GAS)
110 /* This means that we should mark procedures as IEEE conformant. */
112 #define MASK_IEEE_CONFORMANT (1 << 3)
113 #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
115 /* This means we should be IEEE-compliant except for inexact. */
117 #define MASK_IEEE (1 << 4)
118 #define TARGET_IEEE (target_flags & MASK_IEEE)
120 /* This means we should be fully IEEE-compliant. */
122 #define MASK_IEEE_WITH_INEXACT (1 << 5)
123 #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
125 /* This means we must construct all constants rather than emitting
126 them as literal data. */
128 #define MASK_BUILD_CONSTANTS (1 << 6)
129 #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
131 /* This means we handle floating points in VAX F- (float)
132 or G- (double) Format. */
134 #define MASK_FLOAT_VAX (1 << 7)
135 #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
137 /* This means that the processor has byte and half word loads and stores
138 (the BWX extension). */
140 #define MASK_BWX (1 << 8)
141 #define TARGET_BWX (target_flags & MASK_BWX)
143 /* This means that the processor has the MAX extension. */
144 #define MASK_MAX (1 << 9)
145 #define TARGET_MAX (target_flags & MASK_MAX)
147 /* This means that the processor has the FIX extension. */
148 #define MASK_FIX (1 << 10)
149 #define TARGET_FIX (target_flags & MASK_FIX)
151 /* This means that the processor has the CIX extension. */
152 #define MASK_CIX (1 << 11)
153 #define TARGET_CIX (target_flags & MASK_CIX)
155 /* This means use !literal style explicit relocations. */
156 #define MASK_EXPLICIT_RELOCS (1 << 12)
157 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
159 /* This means use 16-bit relocations to .sdata/.sbss. */
160 #define MASK_SMALL_DATA (1 << 13)
161 #define TARGET_SMALL_DATA (target_flags & MASK_SMALL_DATA)
163 /* This means that the processor is an EV5, EV56, or PCA56.
164 Unlike alpha_cpu this is not affected by -mtune= setting. */
165 #define MASK_CPU_EV5 (1 << 28)
166 #define TARGET_CPU_EV5 (target_flags & MASK_CPU_EV5)
168 /* Likewise for EV6. */
169 #define MASK_CPU_EV6 (1 << 29)
170 #define TARGET_CPU_EV6 (target_flags & MASK_CPU_EV6)
172 /* This means we support the .arch directive in the assembler. Only
173 defined in TARGET_CPU_DEFAULT. */
174 #define MASK_SUPPORT_ARCH (1 << 30)
175 #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
177 /* These are for target os support and cannot be changed at runtime. */
178 #define TARGET_ABI_WINDOWS_NT 0
179 #define TARGET_ABI_OPEN_VMS 0
180 #define TARGET_ABI_UNICOSMK 0
181 #define TARGET_ABI_OSF (!TARGET_ABI_WINDOWS_NT \
182 && !TARGET_ABI_OPEN_VMS \
183 && !TARGET_ABI_UNICOSMK)
185 #ifndef TARGET_AS_CAN_SUBTRACT_LABELS
186 #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS
188 #ifndef TARGET_AS_SLASH_BEFORE_SUFFIX
189 #define TARGET_AS_SLASH_BEFORE_SUFFIX TARGET_GAS
191 #ifndef TARGET_CAN_FAULT_IN_PROLOGUE
192 #define TARGET_CAN_FAULT_IN_PROLOGUE 0
194 #ifndef TARGET_HAS_XFLOATING_LIBS
195 #define TARGET_HAS_XFLOATING_LIBS 0
197 #ifndef TARGET_PROFILING_NEEDS_GP
198 #define TARGET_PROFILING_NEEDS_GP 0
200 #ifndef TARGET_LD_BUGGY_LDGP
201 #define TARGET_LD_BUGGY_LDGP 0
203 #ifndef TARGET_FIXUP_EV5_PREFETCH
204 #define TARGET_FIXUP_EV5_PREFETCH 0
207 /* Macro to define tables used to set the flags.
208 This is a list in braces of pairs in braces,
209 each pair being { "NAME", VALUE }
210 where VALUE is the bits to set or minus the bits to clear.
211 An empty string NAME is used to identify the default VALUE. */
213 #define TARGET_SWITCHES \
214 { {"no-soft-float", MASK_FP, N_("Use hardware fp")}, \
215 {"soft-float", - MASK_FP, N_("Do not use hardware fp")}, \
216 {"fp-regs", MASK_FPREGS, N_("Use fp registers")}, \
217 {"no-fp-regs", - (MASK_FP|MASK_FPREGS), \
218 N_("Do not use fp registers")}, \
219 {"alpha-as", -MASK_GAS, N_("Do not assume GAS")}, \
220 {"gas", MASK_GAS, N_("Assume GAS")}, \
221 {"ieee-conformant", MASK_IEEE_CONFORMANT, \
222 N_("Request IEEE-conformant math library routines (OSF/1)")}, \
223 {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \
224 N_("Emit IEEE-conformant code, without inexact exceptions")}, \
225 {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \
226 N_("Emit IEEE-conformant code, with inexact exceptions")}, \
227 {"build-constants", MASK_BUILD_CONSTANTS, \
228 N_("Do not emit complex integer constants to read-only memory")}, \
229 {"float-vax", MASK_FLOAT_VAX, N_("Use VAX fp")}, \
230 {"float-ieee", -MASK_FLOAT_VAX, N_("Do not use VAX fp")}, \
231 {"bwx", MASK_BWX, N_("Emit code for the byte/word ISA extension")}, \
232 {"no-bwx", -MASK_BWX, ""}, \
234 N_("Emit code for the motion video ISA extension")}, \
235 {"no-max", -MASK_MAX, ""}, \
237 N_("Emit code for the fp move and sqrt ISA extension")}, \
238 {"no-fix", -MASK_FIX, ""}, \
239 {"cix", MASK_CIX, N_("Emit code for the counting ISA extension")}, \
240 {"no-cix", -MASK_CIX, ""}, \
241 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
242 N_("Emit code using explicit relocation directives")}, \
243 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, ""}, \
244 {"small-data", MASK_SMALL_DATA, \
245 N_("Emit 16-bit relocations to the small data areas")}, \
246 {"large-data", -MASK_SMALL_DATA, \
247 N_("Emit 32-bit relocations to the small data areas")}, \
248 {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT \
249 | TARGET_DEFAULT_EXPLICIT_RELOCS, ""} }
251 #define TARGET_DEFAULT MASK_FP|MASK_FPREGS
253 #ifndef TARGET_CPU_DEFAULT
254 #define TARGET_CPU_DEFAULT 0
257 #ifndef TARGET_DEFAULT_EXPLICIT_RELOCS
258 #ifdef HAVE_AS_EXPLICIT_RELOCS
259 #define TARGET_DEFAULT_EXPLICIT_RELOCS MASK_EXPLICIT_RELOCS
261 #define TARGET_DEFAULT_EXPLICIT_RELOCS 0
265 extern const char *alpha_cpu_string
; /* For -mcpu= */
266 extern const char *alpha_tune_string
; /* For -mtune= */
267 extern const char *alpha_fprm_string
; /* For -mfp-rounding-mode=[n|m|c|d] */
268 extern const char *alpha_fptm_string
; /* For -mfp-trap-mode=[n|u|su|sui] */
269 extern const char *alpha_tp_string
; /* For -mtrap-precision=[p|f|i] */
270 extern const char *alpha_mlat_string
; /* For -mmemory-latency= */
272 #define TARGET_OPTIONS \
274 {"cpu=", &alpha_cpu_string, \
275 N_("Use features of and schedule given CPU")}, \
276 {"tune=", &alpha_tune_string, \
277 N_("Schedule given CPU")}, \
278 {"fp-rounding-mode=", &alpha_fprm_string, \
279 N_("Control the generated fp rounding mode")}, \
280 {"fp-trap-mode=", &alpha_fptm_string, \
281 N_("Control the IEEE trap mode")}, \
282 {"trap-precision=", &alpha_tp_string, \
283 N_("Control the precision given to fp exceptions")}, \
284 {"memory-latency=", &alpha_mlat_string, \
285 N_("Tune expected memory latency")}, \
288 /* Attempt to describe CPU characteristics to the preprocessor. */
290 /* Corresponding to amask... */
291 #define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu=bwx"
292 #define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu=max"
293 #define CPP_AM_FIX_SPEC "-D__alpha_fix__ -Acpu=fix"
294 #define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu=cix"
296 /* Corresponding to implver... */
297 #define CPP_IM_EV4_SPEC "-D__alpha_ev4__ -Acpu=ev4"
298 #define CPP_IM_EV5_SPEC "-D__alpha_ev5__ -Acpu=ev5"
299 #define CPP_IM_EV6_SPEC "-D__alpha_ev6__ -Acpu=ev6"
301 /* Common combinations. */
302 #define CPP_CPU_EV4_SPEC "%(cpp_im_ev4)"
303 #define CPP_CPU_EV5_SPEC "%(cpp_im_ev5)"
304 #define CPP_CPU_EV56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx)"
305 #define CPP_CPU_PCA56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)"
306 #define CPP_CPU_EV6_SPEC \
307 "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix)"
308 #define CPP_CPU_EV67_SPEC \
309 "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix) %(cpp_am_cix)"
311 #ifndef CPP_CPU_DEFAULT_SPEC
312 # if TARGET_CPU_DEFAULT & MASK_CPU_EV6
313 # if TARGET_CPU_DEFAULT & MASK_CIX
314 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV67_SPEC
316 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV6_SPEC
319 # if TARGET_CPU_DEFAULT & MASK_CPU_EV5
320 # if TARGET_CPU_DEFAULT & MASK_MAX
321 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_PCA56_SPEC
323 # if TARGET_CPU_DEFAULT & MASK_BWX
324 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV56_SPEC
326 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV5_SPEC
330 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV4_SPEC
333 #endif /* CPP_CPU_DEFAULT_SPEC */
336 #define CPP_CPU_SPEC "\
337 %{!undef:-Acpu=alpha -Amachine=alpha -D__alpha -D__alpha__ \
338 %{mcpu=ev4|mcpu=21064:%(cpp_cpu_ev4) }\
339 %{mcpu=ev5|mcpu=21164:%(cpp_cpu_ev5) }\
340 %{mcpu=ev56|mcpu=21164a:%(cpp_cpu_ev56) }\
341 %{mcpu=pca56|mcpu=21164pc|mcpu=21164PC:%(cpp_cpu_pca56) }\
342 %{mcpu=ev6|mcpu=21264:%(cpp_cpu_ev6) }\
343 %{mcpu=ev67|mcpu=21264a:%(cpp_cpu_ev67) }\
344 %{!mcpu*:%(cpp_cpu_default) }}"
347 /* This macro defines names of additional specifications to put in the
348 specs that can be used in various specifications like CC1_SPEC. Its
349 definition is an initializer with a subgrouping for each command option.
351 Each subgrouping contains a string constant, that defines the
352 specification name, and a string constant that used by the GNU CC driver
355 Do not define this macro if it does not need to do anything. */
357 #ifndef SUBTARGET_EXTRA_SPECS
358 #define SUBTARGET_EXTRA_SPECS
361 #define EXTRA_SPECS \
362 { "cpp_am_bwx", CPP_AM_BWX_SPEC }, \
363 { "cpp_am_max", CPP_AM_MAX_SPEC }, \
364 { "cpp_am_fix", CPP_AM_FIX_SPEC }, \
365 { "cpp_am_cix", CPP_AM_CIX_SPEC }, \
366 { "cpp_im_ev4", CPP_IM_EV4_SPEC }, \
367 { "cpp_im_ev5", CPP_IM_EV5_SPEC }, \
368 { "cpp_im_ev6", CPP_IM_EV6_SPEC }, \
369 { "cpp_cpu_ev4", CPP_CPU_EV4_SPEC }, \
370 { "cpp_cpu_ev5", CPP_CPU_EV5_SPEC }, \
371 { "cpp_cpu_ev56", CPP_CPU_EV56_SPEC }, \
372 { "cpp_cpu_pca56", CPP_CPU_PCA56_SPEC }, \
373 { "cpp_cpu_ev6", CPP_CPU_EV6_SPEC }, \
374 { "cpp_cpu_ev67", CPP_CPU_EV67_SPEC }, \
375 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
376 { "cpp_cpu", CPP_CPU_SPEC }, \
377 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
378 SUBTARGET_EXTRA_SPECS
381 /* Sometimes certain combinations of command options do not make sense
382 on a particular target machine. You can define a macro
383 `OVERRIDE_OPTIONS' to take account of this. This macro, if
384 defined, is executed once just after all the command options have
387 On the Alpha, it is used to translate target-option strings into
390 #define OVERRIDE_OPTIONS override_options ()
393 /* Define this macro to change register usage conditional on target flags.
395 On the Alpha, we use this to disable the floating-point registers when
398 #define CONDITIONAL_REGISTER_USAGE \
401 if (! TARGET_FPREGS) \
402 for (i = 32; i < 63; i++) \
403 fixed_regs[i] = call_used_regs[i] = 1; \
407 /* Show we can debug even without a frame pointer. */
408 #define CAN_DEBUG_WITHOUT_FP
410 /* target machine storage layout */
412 /* Define to enable software floating point emulation. */
413 #define REAL_ARITHMETIC
415 /* Define the size of `int'. The default is the same as the word size. */
416 #define INT_TYPE_SIZE 32
418 /* Define the size of `long long'. The default is the twice the word size. */
419 #define LONG_LONG_TYPE_SIZE 64
421 /* The two floating-point formats we support are S-floating, which is
422 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double'
423 and `long double' are T. */
425 #define FLOAT_TYPE_SIZE 32
426 #define DOUBLE_TYPE_SIZE 64
427 #define LONG_DOUBLE_TYPE_SIZE 64
429 #define WCHAR_TYPE "unsigned int"
430 #define WCHAR_TYPE_SIZE 32
432 /* Define this macro if it is advisable to hold scalars in registers
433 in a wider mode than that declared by the program. In such cases,
434 the value is constrained to be within the bounds of the declared
435 type, but kept valid in the wider mode. The signedness of the
436 extension may differ from that of the type.
438 For Alpha, we always store objects in a full register. 32-bit objects
439 are always sign-extended, but smaller objects retain their signedness. */
441 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
442 if (GET_MODE_CLASS (MODE) == MODE_INT \
443 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
445 if ((MODE) == SImode) \
450 /* Define this if function arguments should also be promoted using the above
453 #define PROMOTE_FUNCTION_ARGS
455 /* Likewise, if the function return value is promoted. */
457 #define PROMOTE_FUNCTION_RETURN
459 /* Define this if most significant bit is lowest numbered
460 in instructions that operate on numbered bit-fields.
462 There are no such instructions on the Alpha, but the documentation
464 #define BITS_BIG_ENDIAN 0
466 /* Define this if most significant byte of a word is the lowest numbered.
467 This is false on the Alpha. */
468 #define BYTES_BIG_ENDIAN 0
470 /* Define this if most significant word of a multiword number is lowest
473 For Alpha we can decide arbitrarily since there are no machine instructions
474 for them. Might as well be consistent with bytes. */
475 #define WORDS_BIG_ENDIAN 0
477 /* number of bits in an addressable storage unit */
478 #define BITS_PER_UNIT 8
480 /* Width in bits of a "word", which is the contents of a machine register.
481 Note that this is not necessarily the width of data type `int';
482 if using 16-bit ints on a 68000, this would still be 32.
483 But on a machine with 16-bit registers, this would be 16. */
484 #define BITS_PER_WORD 64
486 /* Width of a word, in units (bytes). */
487 #define UNITS_PER_WORD 8
489 /* Width in bits of a pointer.
490 See also the macro `Pmode' defined below. */
491 #define POINTER_SIZE 64
493 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
494 #define PARM_BOUNDARY 64
496 /* Boundary (in *bits*) on which stack pointer should be aligned. */
497 #define STACK_BOUNDARY 64
499 /* Allocation boundary (in *bits*) for the code of a function. */
500 #define FUNCTION_BOUNDARY 32
502 /* Alignment of field after `int : 0' in a structure. */
503 #define EMPTY_FIELD_BOUNDARY 64
505 /* Every structure's size must be a multiple of this. */
506 #define STRUCTURE_SIZE_BOUNDARY 8
508 /* A bitfield declared as `int' forces `int' alignment for the struct. */
509 #define PCC_BITFIELD_TYPE_MATTERS 1
511 /* No data type wants to be aligned rounder than this. */
512 #define BIGGEST_ALIGNMENT 128
514 /* For atomic access to objects, must have at least 32-bit alignment
515 unless the machine has byte operations. */
516 #define MINIMUM_ATOMIC_ALIGNMENT ((unsigned int) (TARGET_BWX ? 8 : 32))
518 /* Align all constants and variables to at least a word boundary so
519 we can pick up pieces of them faster. */
520 /* ??? Only if block-move stuff knows about different source/destination
523 #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
524 #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
527 /* Set this non-zero if move instructions will actually fail to work
528 when given unaligned data.
530 Since we get an error message when we do one, call them invalid. */
532 #define STRICT_ALIGNMENT 1
534 /* Set this non-zero if unaligned move instructions are extremely slow.
536 On the Alpha, they trap. */
538 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
540 /* Standard register usage. */
542 /* Number of actual hardware registers.
543 The hardware registers are assigned numbers for the compiler
544 from 0 to just below FIRST_PSEUDO_REGISTER.
545 All registers that the compiler knows about must be given numbers,
546 even those that are not normally considered general registers.
548 We define all 32 integer registers, even though $31 is always zero,
549 and all 32 floating-point registers, even though $f31 is also
550 always zero. We do not bother defining the FP status register and
551 there are no other registers.
553 Since $31 is always zero, we will use register number 31 as the
554 argument pointer. It will never appear in the generated code
555 because we will always be eliminating it in favor of the stack
556 pointer or hardware frame pointer.
558 Likewise, we use $f31 for the frame pointer, which will always
559 be eliminated in favor of the hardware frame pointer or the
562 #define FIRST_PSEUDO_REGISTER 64
564 /* 1 for registers that have pervasive standard uses
565 and are not available for the register allocator. */
567 #define FIXED_REGISTERS \
568 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
569 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
570 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
571 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
573 /* 1 for registers not available across function calls.
574 These must include the FIXED_REGISTERS and also any
575 registers that can be used without being saved.
576 The latter must include the registers where values are returned
577 and the register where structure-value addresses are passed.
578 Aside from that, you can include as many other registers as you like. */
579 #define CALL_USED_REGISTERS \
580 {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
581 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \
582 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
583 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
585 /* List the order in which to allocate registers. Each register must be
586 listed once, even those in FIXED_REGISTERS.
588 We allocate in the following order:
589 $f10-$f15 (nonsaved floating-point register)
591 $f21-$f16 (likewise, but input args)
592 $f0 (nonsaved, but return value)
593 $f1 (nonsaved, but immediate before saved)
594 $f2-$f9 (saved floating-point registers)
595 $1-$8 (nonsaved integer registers)
598 $0 (likewise, but return value)
599 $21-$16 (likewise, but input args)
600 $27 (procedure value in OSF, nonsaved in NT)
601 $9-$14 (saved integer registers)
605 $30, $31, $f31 (stack pointer and always zero/ap & fp) */
607 #define REG_ALLOC_ORDER \
608 {42, 43, 44, 45, 46, 47, \
609 54, 55, 56, 57, 58, 59, 60, 61, 62, \
610 53, 52, 51, 50, 49, 48, \
612 34, 35, 36, 37, 38, 39, 40, 41, \
613 1, 2, 3, 4, 5, 6, 7, 8, \
617 21, 20, 19, 18, 17, 16, \
619 9, 10, 11, 12, 13, 14, \
625 /* Return number of consecutive hard regs needed starting at reg REGNO
626 to hold something of mode MODE.
627 This is ordinarily the length in words of a value of mode MODE
628 but can be less for certain modes in special long registers. */
630 #define HARD_REGNO_NREGS(REGNO, MODE) \
631 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
633 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
634 On Alpha, the integer registers can hold any mode. The floating-point
635 registers can hold 32-bit and 64-bit integers as well, but not 16-bit
638 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
639 ((REGNO) >= 32 && (REGNO) <= 62 \
640 ? GET_MODE_UNIT_SIZE (MODE) == 8 || GET_MODE_UNIT_SIZE (MODE) == 4 \
643 /* A C expression that is nonzero if a value of mode
644 MODE1 is accessible in mode MODE2 without copying.
646 This asymmetric test is true when MODE1 could be put
647 in an FP register but MODE2 could not. */
649 #define MODES_TIEABLE_P(MODE1, MODE2) \
650 (HARD_REGNO_MODE_OK (32, (MODE1)) \
651 ? HARD_REGNO_MODE_OK (32, (MODE2)) \
654 /* Specify the registers used for certain standard purposes.
655 The values of these macros are register numbers. */
657 /* Alpha pc isn't overloaded on a register that the compiler knows about. */
658 /* #define PC_REGNUM */
660 /* Register to use for pushing function arguments. */
661 #define STACK_POINTER_REGNUM 30
663 /* Base register for access to local variables of the function. */
664 #define HARD_FRAME_POINTER_REGNUM 15
666 /* Value should be nonzero if functions must have frame pointers.
667 Zero means the frame pointer need not be set up (and parms
668 may be accessed via the stack pointer) in functions that seem suitable.
669 This is computed in `reload', in reload1.c. */
670 #define FRAME_POINTER_REQUIRED 0
672 /* Base register for access to arguments of the function. */
673 #define ARG_POINTER_REGNUM 31
675 /* Base register for access to local variables of function. */
676 #define FRAME_POINTER_REGNUM 63
678 /* Register in which static-chain is passed to a function.
680 For the Alpha, this is based on an example; the calling sequence
681 doesn't seem to specify this. */
682 #define STATIC_CHAIN_REGNUM 1
684 /* The register number of the register used to address a table of
685 static data addresses in memory. */
686 #define PIC_OFFSET_TABLE_REGNUM 29
688 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM'
689 is clobbered by calls. */
690 /* ??? It is and it isn't. It's required to be valid for a given
691 function when the function returns. It isn't clobbered by
692 current_file functions. Moreover, we do not expose the ldgp
693 until after reload, so we're probably safe. */
694 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
696 /* Register in which address to store a structure value
697 arrives in the function. On the Alpha, the address is passed
698 as a hidden argument. */
699 #define STRUCT_VALUE 0
701 /* Define the classes of registers for register constraints in the
702 machine description. Also define ranges of constants.
704 One of the classes must always be named ALL_REGS and include all hard regs.
705 If there is more than one class, another class must be named NO_REGS
706 and contain no registers.
708 The name GENERAL_REGS must be the name of a class (or an alias for
709 another name such as ALL_REGS). This is the class of registers
710 that is allowed by "g" or "r" in a register constraint.
711 Also, registers outside this class are allocated only when
712 instructions express preferences for them.
714 The classes must be numbered in nondecreasing order; that is,
715 a larger-numbered class must never be contained completely
716 in a smaller-numbered class.
718 For any two classes, it is very desirable that there be another
719 class that represents their union. */
722 NO_REGS
, R24_REG
, R25_REG
, R27_REG
,
723 GENERAL_REGS
, FLOAT_REGS
, ALL_REGS
,
727 #define N_REG_CLASSES (int) LIM_REG_CLASSES
729 /* Give names of register classes as strings for dump file. */
731 #define REG_CLASS_NAMES \
732 {"NO_REGS", "R24_REG", "R25_REG", "R27_REG", \
733 "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
735 /* Define which registers fit in which classes.
736 This is an initializer for a vector of HARD_REG_SET
737 of length N_REG_CLASSES. */
739 #define REG_CLASS_CONTENTS \
740 { {0x00000000, 0x00000000}, /* NO_REGS */ \
741 {0x01000000, 0x00000000}, /* R24_REG */ \
742 {0x02000000, 0x00000000}, /* R25_REG */ \
743 {0x08000000, 0x00000000}, /* R27_REG */ \
744 {0xffffffff, 0x80000000}, /* GENERAL_REGS */ \
745 {0x00000000, 0x7fffffff}, /* FLOAT_REGS */ \
746 {0xffffffff, 0xffffffff} }
748 /* The same information, inverted:
749 Return the class number of the smallest class containing
750 reg number REGNO. This could be a conditional expression
751 or could index an array. */
753 #define REGNO_REG_CLASS(REGNO) \
754 ((REGNO) == 24 ? R24_REG \
755 : (REGNO) == 25 ? R25_REG \
756 : (REGNO) == 27 ? R27_REG \
757 : (REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS \
760 /* The class value for index registers, and the one for base regs. */
761 #define INDEX_REG_CLASS NO_REGS
762 #define BASE_REG_CLASS GENERAL_REGS
764 /* Get reg_class from a letter such as appears in the machine description. */
766 #define REG_CLASS_FROM_LETTER(C) \
767 ((C) == 'a' ? R24_REG \
768 : (C) == 'b' ? R25_REG \
769 : (C) == 'c' ? R27_REG \
770 : (C) == 'f' ? FLOAT_REGS \
773 /* Define this macro to change register usage conditional on target flags. */
774 /* #define CONDITIONAL_REGISTER_USAGE */
776 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
777 can be used to stand for particular ranges of immediate operands.
778 This macro defines what the ranges are.
779 C is the letter, and VALUE is a constant value.
780 Return 1 if VALUE is in the range specified by C.
783 `I' is used for the range of constants most insns can contain.
784 `J' is the constant zero.
785 `K' is used for the constant in an LDA insn.
786 `L' is used for the constant in a LDAH insn.
787 `M' is used for the constants that can be AND'ed with using a ZAP insn.
788 `N' is used for complemented 8-bit constants.
789 `O' is used for negated 8-bit constants.
790 `P' is used for the constants 1, 2 and 3. */
792 #define CONST_OK_FOR_LETTER_P alpha_const_ok_for_letter_p
794 /* Similar, but for floating or large integer constants, and defining letters
795 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
797 For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE
798 that is the operand of a ZAP insn. */
800 #define CONST_DOUBLE_OK_FOR_LETTER_P alpha_const_double_ok_for_letter_p
802 /* Optional extra constraints for this machine.
804 For the Alpha, `Q' means that this is a memory operand but not a
805 reference to an unaligned location.
807 `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
810 'S' is a 6-bit constant (valid for a shift insn).
814 'U' is a symbolic operand. */
816 #define EXTRA_CONSTRAINT alpha_extra_constraint
818 /* Given an rtx X being reloaded into a reg required to be
819 in class CLASS, return the class of reg to actually use.
820 In general this is just CLASS; but on some machines
821 in some cases it is preferable to use a more restrictive class. */
823 #define PREFERRED_RELOAD_CLASS alpha_preferred_reload_class
825 /* Loading and storing HImode or QImode values to and from memory
826 usually requires a scratch register. The exceptions are loading
827 QImode and HImode from an aligned address to a general register
828 unless byte instructions are permitted.
829 We also cannot load an unaligned address or a paradoxical SUBREG into an
832 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
833 secondary_reload_class((CLASS), (MODE), (IN), 1)
835 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
836 secondary_reload_class((CLASS), (MODE), (OUT), 0)
838 /* If we are copying between general and FP registers, we need a memory
839 location unless the FIX extension is available. */
841 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
842 (! TARGET_FIX && (((CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS) \
843 || ((CLASS2) == FLOAT_REGS && (CLASS1) != FLOAT_REGS)))
845 /* Specify the mode to be used for memory when a secondary memory
846 location is needed. If MODE is floating-point, use it. Otherwise,
847 widen to a word like the default. This is needed because we always
848 store integers in FP registers in quadword format. This whole
849 area is very tricky! */
850 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
851 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \
852 : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \
853 : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))
855 /* Return the maximum number of consecutive registers
856 needed to represent mode MODE in a register of class CLASS. */
858 #define CLASS_MAX_NREGS(CLASS, MODE) \
859 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
861 /* If defined, gives a class of registers that cannot be used as the
862 operand of a SUBREG that changes the mode of the object illegally. */
864 #define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS
866 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
868 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
869 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
871 /* Define the cost of moving between registers of various classes. Moving
872 between FLOAT_REGS and anything else except float regs is expensive.
873 In fact, we make it quite expensive because we really don't want to
874 do these moves unless it is clearly worth it. Optimizations may
875 reduce the impact of not being able to allocate a pseudo to a
878 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
879 (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
881 : TARGET_FIX ? 3 : 4+2*alpha_memory_latency)
883 /* A C expressions returning the cost of moving data of MODE from a register to
886 On the Alpha, bump this up a bit. */
888 extern int alpha_memory_latency
;
889 #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency)
891 /* Provide the cost of a branch. Exact meaning under development. */
892 #define BRANCH_COST 5
894 /* Stack layout; function entry, exit and calling. */
896 /* Define this if pushing a word on the stack
897 makes the stack pointer a smaller address. */
898 #define STACK_GROWS_DOWNWARD
900 /* Define this if the nominal address of the stack frame
901 is at the high-address end of the local variables;
902 that is, each additional local variable allocated
903 goes at a more negative offset in the frame. */
904 /* #define FRAME_GROWS_DOWNWARD */
906 /* Offset within stack frame to start allocating local variables at.
907 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
908 first local allocated. Otherwise, it is the offset to the BEGINNING
909 of the first local allocated. */
911 #define STARTING_FRAME_OFFSET 0
913 /* If we generate an insn to push BYTES bytes,
914 this says how many the stack pointer really advances by.
915 On Alpha, don't define this because there are no push insns. */
916 /* #define PUSH_ROUNDING(BYTES) */
918 /* Define this to be nonzero if stack checking is built into the ABI. */
919 #define STACK_CHECK_BUILTIN 1
921 /* Define this if the maximum size of all the outgoing args is to be
922 accumulated and pushed during the prologue. The amount can be
923 found in the variable current_function_outgoing_args_size. */
924 #define ACCUMULATE_OUTGOING_ARGS 1
926 /* Offset of first parameter from the argument pointer register value. */
928 #define FIRST_PARM_OFFSET(FNDECL) 0
930 /* Definitions for register eliminations.
932 We have two registers that can be eliminated on the Alpha. First, the
933 frame pointer register can often be eliminated in favor of the stack
934 pointer register. Secondly, the argument pointer register can always be
935 eliminated; it is replaced with either the stack or frame pointer. */
937 /* This is an array of structures. Each structure initializes one pair
938 of eliminable registers. The "from" register number is given first,
939 followed by "to". Eliminations of the same "from" register are listed
940 in order of preference. */
942 #define ELIMINABLE_REGS \
943 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
944 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
945 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
946 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
948 /* Given FROM and TO register numbers, say whether this elimination is allowed.
949 Frame pointer elimination is automatically handled.
951 All eliminations are valid since the cases where FP can't be
952 eliminated are already handled. */
954 #define CAN_ELIMINATE(FROM, TO) 1
956 /* Round up to a multiple of 16 bytes. */
957 #define ALPHA_ROUND(X) (((X) + 15) & ~ 15)
959 /* Define the offset between two registers, one to be eliminated, and the other
960 its replacement, at the start of a routine. */
961 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
962 { if ((FROM) == FRAME_POINTER_REGNUM) \
963 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
964 + alpha_sa_size ()); \
965 else if ((FROM) == ARG_POINTER_REGNUM) \
966 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
968 + (ALPHA_ROUND (get_frame_size () \
969 + current_function_pretend_args_size) \
970 - current_function_pretend_args_size)); \
975 /* Define this if stack space is still allocated for a parameter passed
977 /* #define REG_PARM_STACK_SPACE */
979 /* Value is the number of bytes of arguments automatically
980 popped when returning from a subroutine call.
981 FUNDECL is the declaration node of the function (as a tree),
982 FUNTYPE is the data type of the function (as a tree),
983 or for a library call it is an identifier node for the subroutine name.
984 SIZE is the number of bytes of arguments passed on the stack. */
986 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
988 /* Define how to find the value returned by a function.
989 VALTYPE is the data type of the value (as a tree).
990 If the precise function being called is known, FUNC is its FUNCTION_DECL;
991 otherwise, FUNC is 0.
993 On Alpha the value is found in $0 for integer functions and
994 $f0 for floating-point functions. */
996 #define FUNCTION_VALUE(VALTYPE, FUNC) \
997 gen_rtx_REG (((INTEGRAL_TYPE_P (VALTYPE) \
998 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
999 || POINTER_TYPE_P (VALTYPE)) \
1000 ? word_mode : TYPE_MODE (VALTYPE), \
1002 && (TREE_CODE (VALTYPE) == REAL_TYPE \
1003 || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \
1006 /* Define how to find the value returned by a library function
1007 assuming the value has mode MODE. */
1009 #define LIBCALL_VALUE(MODE) \
1010 gen_rtx_REG (MODE, \
1012 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1013 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1016 /* The definition of this macro implies that there are cases where
1017 a scalar value cannot be returned in registers.
1019 For the Alpha, any structure or union type is returned in memory, as
1020 are integers whose size is larger than 64 bits. */
1022 #define RETURN_IN_MEMORY(TYPE) \
1023 (TYPE_MODE (TYPE) == BLKmode \
1024 || TYPE_MODE (TYPE) == TFmode \
1025 || TYPE_MODE (TYPE) == TCmode \
1026 || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64))
1028 /* 1 if N is a possible register number for a function value
1029 as seen by the caller. */
1031 #define FUNCTION_VALUE_REGNO_P(N) \
1032 ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33)
1034 /* 1 if N is a possible register number for function argument passing.
1035 On Alpha, these are $16-$21 and $f16-$f21. */
1037 #define FUNCTION_ARG_REGNO_P(N) \
1038 (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
1040 /* Define a data type for recording info about an argument list
1041 during the scan of that argument list. This data type should
1042 hold all necessary information about the function itself
1043 and about the args processed so far, enough to enable macros
1044 such as FUNCTION_ARG to determine where the next arg should go.
1046 On Alpha, this is a single integer, which is a number of words
1047 of arguments scanned so far.
1048 Thus 6 or more means all following args should go on the stack. */
1050 #define CUMULATIVE_ARGS int
1052 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1053 for a call to a function whose data type is FNTYPE.
1054 For a library call, FNTYPE is 0. */
1056 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0
1058 /* Define intermediate macro to compute the size (in registers) of an argument
1061 #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \
1062 ((MODE) == TFmode || (MODE) == TCmode ? 1 \
1063 : (((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
1064 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1066 /* Update the data in CUM to advance over an argument
1067 of mode MODE and data type TYPE.
1068 (TYPE is null for libcalls where that information may not be available.) */
1070 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1071 if (MUST_PASS_IN_STACK (MODE, TYPE)) \
1074 (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED)
1076 /* Determine where to put an argument to a function.
1077 Value is zero to push the argument on the stack,
1078 or a hard register in which to store the argument.
1080 MODE is the argument's machine mode.
1081 TYPE is the data type of the argument (as a tree).
1082 This is null for libcalls where that information may
1084 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1085 the preceding args and about the function being called.
1086 NAMED is nonzero if this argument is a named parameter
1087 (otherwise it is an extra parameter matching an ellipsis).
1089 On Alpha the first 6 words of args are normally in registers
1090 and the rest are pushed. */
1092 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1093 function_arg((CUM), (MODE), (TYPE), (NAMED))
1095 /* A C expression that indicates when an argument must be passed by
1096 reference. If nonzero for an argument, a copy of that argument is
1097 made in memory and a pointer to the argument is passed instead of
1098 the argument itself. The pointer is passed in whatever way is
1099 appropriate for passing a pointer to that type. */
1101 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1102 ((MODE) == TFmode || (MODE) == TCmode)
1104 /* Specify the padding direction of arguments.
1106 On the Alpha, we must pad upwards in order to be able to pass args in
1109 #define FUNCTION_ARG_PADDING(MODE, TYPE) upward
1111 /* For an arg passed partly in registers and partly in memory,
1112 this is the number of registers used.
1113 For args passed entirely in registers or entirely in memory, zero. */
1115 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1116 ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \
1119 /* Perform any needed actions needed for a function that is receiving a
1120 variable number of arguments.
1124 MODE and TYPE are the mode and type of the current parameter.
1126 PRETEND_SIZE is a variable that should be set to the amount of stack
1127 that must be pushed by the prolog to pretend that our caller pushed
1130 Normally, this macro will push all remaining incoming registers on the
1131 stack and set PRETEND_SIZE to the length of the registers pushed.
1133 On the Alpha, we allocate space for all 12 arg registers, but only
1134 push those that are remaining.
1136 However, if NO registers need to be saved, don't allocate any space.
1137 This is not only because we won't need the space, but because AP includes
1138 the current_pretend_args_size and we don't want to mess up any
1139 ap-relative addresses already made.
1141 If we are not to use the floating-point registers, save the integer
1142 registers where we would put the floating-point registers. This is
1143 not the most efficient way to implement varargs with just one register
1144 class, but it isn't worth doing anything more efficient in this rare
1147 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1152 rtx tmp; int set = get_varargs_alias_set (); \
1153 tmp = gen_rtx_MEM (BLKmode, \
1154 plus_constant (virtual_incoming_args_rtx, \
1155 ((CUM) + 6)* UNITS_PER_WORD)); \
1156 set_mem_alias_set (tmp, set); \
1157 move_block_from_reg \
1159 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1161 tmp = gen_rtx_MEM (BLKmode, \
1162 plus_constant (virtual_incoming_args_rtx, \
1163 (CUM) * UNITS_PER_WORD)); \
1164 set_mem_alias_set (tmp, set); \
1165 move_block_from_reg \
1166 (16 + (TARGET_FPREGS ? 32 : 0) + CUM, tmp, \
1167 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1169 PRETEND_SIZE = 12 * UNITS_PER_WORD; \
1173 /* We do not allow indirect calls to be optimized into sibling calls, nor
1174 can we allow a call to a function in a different compilation unit to
1175 be optimized into a sibcall. Except if the function is known not to
1176 return, in which case our caller doesn't care what the gp is. */
1177 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1179 && ((TREE_ASM_WRITTEN (DECL) && !flag_pic) \
1180 || ! TREE_PUBLIC (DECL)))
1182 /* Try to output insns to set TARGET equal to the constant C if it can be
1183 done in less than N insns. Do all computations in MODE. Returns the place
1184 where the output has been placed if it can be done and the insns have been
1185 emitted. If it would take more than N insns, zero is returned and no
1186 insns and emitted. */
1188 /* Define the information needed to generate branch and scc insns. This is
1189 stored from the compare operation. Note that we can't use "rtx" here
1190 since it hasn't been defined! */
1192 struct alpha_compare
1194 struct rtx_def
*op0
, *op1
;
1198 extern struct alpha_compare alpha_compare
;
1200 /* Make (or fake) .linkage entry for function call.
1201 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
1203 /* This macro defines the start of an assembly comment. */
1205 #define ASM_COMMENT_START " #"
1207 /* This macro produces the initial definition of a function. */
1209 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1210 alpha_start_function(FILE,NAME,DECL);
1212 /* This macro closes up a function definition for the assembler. */
1214 #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \
1215 alpha_end_function(FILE,NAME,DECL)
1217 /* Output any profiling code before the prologue. */
1219 #define PROFILE_BEFORE_PROLOGUE 1
1221 /* Output assembler code to FILE to increment profiler label # LABELNO
1222 for profiling a function entry. Under OSF/1, profiling is enabled
1223 by simply passing -pg to the assembler and linker. */
1225 #define FUNCTION_PROFILER(FILE, LABELNO)
1227 /* Output assembler code to FILE to initialize this source file's
1228 basic block profiling info, if that has not already been done.
1229 This assumes that __bb_init_func doesn't garble a1-a5. */
1231 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1233 ASM_OUTPUT_REG_PUSH (FILE, 16); \
1234 fputs ("\tlda $16,$PBX32\n", (FILE)); \
1235 fputs ("\tldq $26,0($16)\n", (FILE)); \
1236 fputs ("\tbne $26,1f\n", (FILE)); \
1237 fputs ("\tlda $27,__bb_init_func\n", (FILE)); \
1238 fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE)); \
1239 fputs ("\tldgp $29,0($26)\n", (FILE)); \
1240 fputs ("1:\n", (FILE)); \
1241 ASM_OUTPUT_REG_POP (FILE, 16); \
1244 /* Output assembler code to FILE to increment the entry-count for
1245 the BLOCKNO'th basic block in this source file. */
1247 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1249 int blockn = (BLOCKNO); \
1250 fputs ("\tsubq $30,16,$30\n", (FILE)); \
1251 fputs ("\tstq $26,0($30)\n", (FILE)); \
1252 fputs ("\tstq $27,8($30)\n", (FILE)); \
1253 fputs ("\tlda $26,$PBX34\n", (FILE)); \
1254 fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn); \
1255 fputs ("\taddq $27,1,$27\n", (FILE)); \
1256 fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn); \
1257 fputs ("\tldq $26,0($30)\n", (FILE)); \
1258 fputs ("\tldq $27,8($30)\n", (FILE)); \
1259 fputs ("\taddq $30,16,$30\n", (FILE)); \
1263 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1264 the stack pointer does not matter. The value is tested only in
1265 functions that have frame pointers.
1266 No definition is equivalent to always zero. */
1268 #define EXIT_IGNORE_STACK 1
1270 /* Define registers used by the epilogue and return instruction. */
1272 #define EPILOGUE_USES(REGNO) ((REGNO) == 26)
1274 /* Output assembler code for a block containing the constant parts
1275 of a trampoline, leaving space for the variable parts.
1277 The trampoline should set the static chain pointer to value placed
1278 into the trampoline and should branch to the specified routine.
1279 Note that $27 has been set to the address of the trampoline, so we can
1280 use it for addressability of the two data items. */
1282 #define TRAMPOLINE_TEMPLATE(FILE) \
1284 fprintf (FILE, "\tldq $1,24($27)\n"); \
1285 fprintf (FILE, "\tldq $27,16($27)\n"); \
1286 fprintf (FILE, "\tjmp $31,($27),0\n"); \
1287 fprintf (FILE, "\tnop\n"); \
1288 fprintf (FILE, "\t.quad 0,0\n"); \
1291 /* Section in which to place the trampoline. On Alpha, instructions
1292 may only be placed in a text segment. */
1294 #define TRAMPOLINE_SECTION text_section
1296 /* Length in units of the trampoline for entering a nested function. */
1298 #define TRAMPOLINE_SIZE 32
1300 /* The alignment of a trampoline, in bits. */
1302 #define TRAMPOLINE_ALIGNMENT 64
1304 /* Emit RTL insns to initialize the variable parts of a trampoline.
1305 FNADDR is an RTX for the address of the function's pure code.
1306 CXT is an RTX for the static chain value for the function. */
1308 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1309 alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8)
1311 /* A C expression whose value is RTL representing the value of the return
1312 address for the frame COUNT steps up from the current frame.
1313 FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of
1314 the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */
1316 #define RETURN_ADDR_RTX alpha_return_addr
1318 /* Before the prologue, RA lives in $26. */
1319 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26)
1320 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (26)
1322 /* Describe how we implement __builtin_eh_return. */
1323 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 16 : INVALID_REGNUM)
1324 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 28)
1325 #define EH_RETURN_HANDLER_RTX \
1326 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \
1327 current_function_outgoing_args_size))
1329 /* Addressing modes, and classification of registers for them. */
1331 /* #define HAVE_POST_INCREMENT 0 */
1332 /* #define HAVE_POST_DECREMENT 0 */
1334 /* #define HAVE_PRE_DECREMENT 0 */
1335 /* #define HAVE_PRE_INCREMENT 0 */
1337 /* Macros to check register numbers against specific register classes. */
1339 /* These assume that REGNO is a hard or pseudo reg number.
1340 They give nonzero only if REGNO is a hard reg of the suitable class
1341 or a pseudo reg currently allocated to a suitable hard reg.
1342 Since they use reg_renumber, they are safe only once reg_renumber
1343 has been allocated, which happens in local-alloc.c. */
1345 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
1346 #define REGNO_OK_FOR_BASE_P(REGNO) \
1347 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \
1348 || (REGNO) == 63 || reg_renumber[REGNO] == 63)
1350 /* Maximum number of registers that can appear in a valid memory address. */
1351 #define MAX_REGS_PER_ADDRESS 1
1353 /* Recognize any constant value that is a valid address. For the Alpha,
1354 there are only constants none since we want to use LDA to load any
1355 symbolic addresses into registers. */
1357 #define CONSTANT_ADDRESS_P(X) \
1358 (GET_CODE (X) == CONST_INT \
1359 && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1361 /* Include all constant integers and constant doubles, but not
1362 floating-point, except for floating-point zero. */
1364 #define LEGITIMATE_CONSTANT_P(X) \
1365 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1366 || (X) == CONST0_RTX (GET_MODE (X)))
1368 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1369 and check its validity for a certain class.
1370 We have two alternate definitions for each of them.
1371 The usual definition accepts all pseudo regs; the other rejects
1372 them unless they have been allocated suitable hard regs.
1373 The symbol REG_OK_STRICT causes the latter definition to be used.
1375 Most source files want to accept pseudo regs in the hope that
1376 they will get allocated to the class that the insn wants them to be in.
1377 Source files for reload pass need to be strict.
1378 After reload, it makes no difference, since pseudo regs have
1379 been eliminated by then. */
1381 /* Nonzero if X is a hard reg that can be used as an index
1382 or if it is a pseudo reg. */
1383 #define REG_OK_FOR_INDEX_P(X) 0
1385 /* Nonzero if X is a hard reg that can be used as a base reg
1386 or if it is a pseudo reg. */
1387 #define NONSTRICT_REG_OK_FOR_BASE_P(X) \
1388 (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1390 /* ??? Nonzero if X is the frame pointer, or some virtual register
1391 that may eliminate to the frame pointer. These will be allowed to
1392 have offsets greater than 32K. This is done because register
1393 elimination offsets will change the hi/lo split, and if we split
1394 before reload, we will require additional instructions. */
1395 #define NONSTRICT_REG_OK_FP_BASE_P(X) \
1396 (REGNO (X) == 31 || REGNO (X) == 63 \
1397 || (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1398 && REGNO (X) < LAST_VIRTUAL_REGISTER))
1400 /* Nonzero if X is a hard reg that can be used as a base reg. */
1401 #define STRICT_REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1403 #ifdef REG_OK_STRICT
1404 #define REG_OK_FOR_BASE_P(X) STRICT_REG_OK_FOR_BASE_P (X)
1406 #define REG_OK_FOR_BASE_P(X) NONSTRICT_REG_OK_FOR_BASE_P (X)
1409 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
1410 valid memory address for an instruction. */
1412 #ifdef REG_OK_STRICT
1413 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
1415 if (alpha_legitimate_address_p (MODE, X, 1)) \
1419 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
1421 if (alpha_legitimate_address_p (MODE, X, 0)) \
1426 /* Try machine-dependent ways of modifying an illegitimate address
1427 to be legitimate. If we find one, return the new, valid address.
1428 This macro is used in only one place: `memory_address' in explow.c. */
1430 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1432 rtx new_x = alpha_legitimize_address (X, NULL_RTX, MODE); \
1440 /* Try a machine-dependent way of reloading an illegitimate address
1441 operand. If we find one, push the reload and jump to WIN. This
1442 macro is used in only one place: `find_reloads_address' in reload.c. */
1444 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \
1446 rtx new_x = alpha_legitimize_reload_address (X, MODE, OPNUM, TYPE, IND_L); \
1454 /* Go to LABEL if ADDR (a legitimate address expression)
1455 has an effect that depends on the machine mode it is used for.
1456 On the Alpha this is true only for the unaligned modes. We can
1457 simplify this test since we know that the address must be valid. */
1459 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1460 { if (GET_CODE (ADDR) == AND) goto LABEL; }
1462 /* Compute the cost of an address. For the Alpha, all valid addresses are
1465 #define ADDRESS_COST(X) 0
1467 /* Machine-dependent reorg pass. */
1468 #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X)
1470 /* Specify the machine mode that this machine uses
1471 for the index in the tablejump instruction. */
1472 #define CASE_VECTOR_MODE SImode
1474 /* Define as C expression which evaluates to nonzero if the tablejump
1475 instruction expects the table to contain offsets from the address of the
1478 Do not define this if the table should contain absolute addresses.
1479 On the Alpha, the table is really GP-relative, not relative to the PC
1480 of the table, but we pretend that it is PC-relative; this should be OK,
1481 but we should try to find some better way sometime. */
1482 #define CASE_VECTOR_PC_RELATIVE 1
1484 /* Define this as 1 if `char' should by default be signed; else as 0. */
1485 #define DEFAULT_SIGNED_CHAR 1
1487 /* This flag, if defined, says the same insns that convert to a signed fixnum
1488 also convert validly to an unsigned one.
1490 We actually lie a bit here as overflow conditions are different. But
1491 they aren't being checked anyway. */
1493 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1495 /* Max number of bytes we can move to or from memory
1496 in one reasonably fast instruction. */
1500 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1501 move-instruction pairs, we will do a movstr or libcall instead.
1503 Without byte/word accesses, we want no more than four instructions;
1504 with, several single byte accesses are better. */
1506 #define MOVE_RATIO (TARGET_BWX ? 7 : 2)
1508 /* Largest number of bytes of an object that can be placed in a register.
1509 On the Alpha we have plenty of registers, so use TImode. */
1510 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1512 /* Nonzero if access to memory by bytes is no faster than for words.
1513 Also non-zero if doing byte operations (specifically shifts) in registers
1516 On the Alpha, we want to not use the byte operation and instead use
1517 masking operations to access fields; these will save instructions. */
1519 #define SLOW_BYTE_ACCESS 1
1521 /* Define if operations between registers always perform the operation
1522 on the full register even if a narrower mode is specified. */
1523 #define WORD_REGISTER_OPERATIONS
1525 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1526 will either zero-extend or sign-extend. The value of this macro should
1527 be the code that says which one of the two operations is implicitly
1528 done, NIL if none. */
1529 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
1531 /* Define if loading short immediate values into registers sign extends. */
1532 #define SHORT_IMMEDIATES_SIGN_EXTEND
1534 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1535 is done just by pretending it is already truncated. */
1536 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1538 /* We assume that the store-condition-codes instructions store 0 for false
1539 and some other value for true. This is the value stored for true. */
1541 #define STORE_FLAG_VALUE 1
1543 /* Define the value returned by a floating-point comparison instruction. */
1545 #define FLOAT_STORE_FLAG_VALUE(MODE) \
1546 REAL_VALUE_ATOF ((TARGET_FLOAT_VAX ? "0.5" : "2.0"), (MODE))
1548 /* Canonicalize a comparison from one we don't have to one we do have. */
1550 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1552 if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \
1553 && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \
1558 (CODE) = swap_condition (CODE); \
1560 if (((CODE) == LT || (CODE) == LTU) \
1561 && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \
1563 (CODE) = (CODE) == LT ? LE : LEU; \
1564 (OP1) = GEN_INT (255); \
1568 /* Specify the machine mode that pointers have.
1569 After generation of rtl, the compiler makes no further distinction
1570 between pointers and any other objects of this machine mode. */
1571 #define Pmode DImode
1573 /* Mode of a function address in a call instruction (for indexing purposes). */
1575 #define FUNCTION_MODE Pmode
1577 /* Define this if addresses of constant functions
1578 shouldn't be put through pseudo regs where they can be cse'd.
1579 Desirable on machines where ordinary constants are expensive
1580 but a CALL with constant address is cheap.
1582 We define this on the Alpha so that gen_call and gen_call_value
1583 get to see the SYMBOL_REF (for the hint field of the jsr). It will
1584 then copy it into a register, thus actually letting the address be
1587 #define NO_FUNCTION_CSE
1589 /* Define this to be nonzero if shift instructions ignore all but the low-order
1591 #define SHIFT_COUNT_TRUNCATED 1
1593 /* Compute the cost of computing a constant rtl expression RTX
1594 whose rtx-code is CODE. The body of this macro is a portion
1595 of a switch statement. If the code is computed here,
1596 return it with a return statement. Otherwise, break from the switch.
1598 If this is an 8-bit constant, return zero since it can be used
1599 nearly anywhere with no cost. If it is a valid operand for an
1600 ADD or AND, likewise return 0 if we know it will be used in that
1601 context. Otherwise, return 2 since it might be used there later.
1602 All other constants take at least two insns. */
1604 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1606 if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \
1608 case CONST_DOUBLE: \
1609 if ((RTX) == CONST0_RTX (GET_MODE (RTX))) \
1611 else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \
1612 || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \
1614 else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \
1617 return COSTS_N_INSNS (2); \
1621 switch (alpha_cpu) \
1623 case PROCESSOR_EV4: \
1624 return COSTS_N_INSNS (3); \
1625 case PROCESSOR_EV5: \
1626 case PROCESSOR_EV6: \
1627 return COSTS_N_INSNS (2); \
1631 /* Provide the costs of a rtl expression. This is in the body of a
1634 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1635 case PLUS: case MINUS: \
1636 if (FLOAT_MODE_P (GET_MODE (X))) \
1637 switch (alpha_cpu) \
1639 case PROCESSOR_EV4: \
1640 return COSTS_N_INSNS (6); \
1641 case PROCESSOR_EV5: \
1642 case PROCESSOR_EV6: \
1643 return COSTS_N_INSNS (4); \
1646 else if (GET_CODE (XEXP (X, 0)) == MULT \
1647 && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
1648 return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
1649 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
1652 switch (alpha_cpu) \
1654 case PROCESSOR_EV4: \
1655 if (FLOAT_MODE_P (GET_MODE (X))) \
1656 return COSTS_N_INSNS (6); \
1657 return COSTS_N_INSNS (23); \
1658 case PROCESSOR_EV5: \
1659 if (FLOAT_MODE_P (GET_MODE (X))) \
1660 return COSTS_N_INSNS (4); \
1661 else if (GET_MODE (X) == DImode) \
1662 return COSTS_N_INSNS (12); \
1664 return COSTS_N_INSNS (8); \
1665 case PROCESSOR_EV6: \
1666 if (FLOAT_MODE_P (GET_MODE (X))) \
1667 return COSTS_N_INSNS (4); \
1669 return COSTS_N_INSNS (7); \
1673 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1674 && INTVAL (XEXP (X, 1)) <= 3) \
1676 /* ... fall through ... */ \
1677 case ASHIFTRT: case LSHIFTRT: \
1678 switch (alpha_cpu) \
1680 case PROCESSOR_EV4: \
1681 return COSTS_N_INSNS (2); \
1682 case PROCESSOR_EV5: \
1683 case PROCESSOR_EV6: \
1684 return COSTS_N_INSNS (1); \
1687 case IF_THEN_ELSE: \
1688 switch (alpha_cpu) \
1690 case PROCESSOR_EV4: \
1691 case PROCESSOR_EV6: \
1692 return COSTS_N_INSNS (2); \
1693 case PROCESSOR_EV5: \
1694 return COSTS_N_INSNS (1); \
1697 case DIV: case UDIV: case MOD: case UMOD: \
1698 switch (alpha_cpu) \
1700 case PROCESSOR_EV4: \
1701 if (GET_MODE (X) == SFmode) \
1702 return COSTS_N_INSNS (34); \
1703 else if (GET_MODE (X) == DFmode) \
1704 return COSTS_N_INSNS (63); \
1706 return COSTS_N_INSNS (70); \
1707 case PROCESSOR_EV5: \
1708 if (GET_MODE (X) == SFmode) \
1709 return COSTS_N_INSNS (15); \
1710 else if (GET_MODE (X) == DFmode) \
1711 return COSTS_N_INSNS (22); \
1713 return COSTS_N_INSNS (70); /* ??? */ \
1714 case PROCESSOR_EV6: \
1715 if (GET_MODE (X) == SFmode) \
1716 return COSTS_N_INSNS (12); \
1717 else if (GET_MODE (X) == DFmode) \
1718 return COSTS_N_INSNS (15); \
1720 return COSTS_N_INSNS (70); /* ??? */ \
1724 switch (alpha_cpu) \
1726 case PROCESSOR_EV4: \
1727 case PROCESSOR_EV6: \
1728 return COSTS_N_INSNS (3); \
1729 case PROCESSOR_EV5: \
1730 return COSTS_N_INSNS (2); \
1733 case NEG: case ABS: \
1734 if (! FLOAT_MODE_P (GET_MODE (X))) \
1736 /* ... fall through ... */ \
1737 case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \
1738 case FLOAT_EXTEND: case FLOAT_TRUNCATE: \
1739 switch (alpha_cpu) \
1741 case PROCESSOR_EV4: \
1742 return COSTS_N_INSNS (6); \
1743 case PROCESSOR_EV5: \
1744 case PROCESSOR_EV6: \
1745 return COSTS_N_INSNS (4); \
1749 /* Control the assembler format that we output. */
1751 /* Output to assembler file text saying following lines
1752 may contain character constants, extra white space, comments, etc. */
1753 #define ASM_APP_ON (TARGET_EXPLICIT_RELOCS ? "\t.set\tmacro\n" : "")
1755 /* Output to assembler file text saying following lines
1756 no longer contain unusual constructs. */
1757 #define ASM_APP_OFF (TARGET_EXPLICIT_RELOCS ? "\t.set\tnomacro\n" : "")
1759 #define TEXT_SECTION_ASM_OP "\t.text"
1761 /* Output before read-only data. */
1763 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata"
1765 /* Output before writable data. */
1767 #define DATA_SECTION_ASM_OP "\t.data"
1769 /* Define an extra section for read-only data, a routine to enter it, and
1770 indicate that it is for read-only data.
1772 The first time we enter the readonly data section for a file, we write
1773 eight bytes of zero. This works around a bug in DEC's assembler in
1774 some versions of OSF/1 V3.x. */
1776 #define EXTRA_SECTIONS readonly_data
1778 #define EXTRA_SECTION_FUNCTIONS \
1780 literal_section () \
1782 if (in_section != readonly_data) \
1784 static int firsttime = 1; \
1786 fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
1790 assemble_aligned_integer (8, const0_rtx); \
1793 in_section = readonly_data; \
1797 #define READONLY_DATA_SECTION literal_section
1799 /* Define this macro if references to a symbol must be treated differently
1800 depending on something about the variable or function named by the symbol
1801 (such as what section it is in). */
1803 #define ENCODE_SECTION_INFO(DECL) alpha_encode_section_info (DECL)
1805 /* If a variable is weakened, made one only or moved into a different
1806 section, it may be necessary to redo the section info to move the
1807 variable out of sdata. */
1809 #define REDO_SECTION_INFO_P(DECL) \
1810 ((TREE_CODE (DECL) == VAR_DECL) \
1811 && (DECL_ONE_ONLY (DECL) || DECL_WEAK (DECL) || DECL_COMMON (DECL) \
1812 || DECL_SECTION_NAME (DECL) != 0))
1814 #define STRIP_NAME_ENCODING(VAR,SYMBOL_NAME) \
1816 (VAR) = (SYMBOL_NAME); \
1817 if ((VAR)[0] == '@') \
1819 if ((VAR)[0] == '*') \
1823 /* How to refer to registers in assembler output.
1824 This sequence is indexed by compiler's hard-register-number (see above). */
1826 #define REGISTER_NAMES \
1827 {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \
1828 "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
1829 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
1830 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \
1831 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \
1832 "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
1833 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\
1834 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"}
1836 /* Strip name encoding when emitting labels. */
1838 #define ASM_OUTPUT_LABELREF(STREAM, NAME) \
1840 const char *name_ = NAME; \
1841 if (*name_ == '@') \
1843 if (*name_ == '*') \
1846 fputs (user_label_prefix, STREAM); \
1847 fputs (name_, STREAM); \
1850 /* This is how to output the definition of a user-level label named NAME,
1851 such as the label on a static function or variable NAME. */
1853 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1854 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1856 /* This is how to output a command to make the user-level label named NAME
1857 defined for reference from other files. */
1859 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1860 do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1862 /* The prefix to add to user-visible assembler symbols. */
1864 #define USER_LABEL_PREFIX ""
1866 /* This is how to output an internal numbered label where
1867 PREFIX is the class of label and NUM is the number within the class. */
1869 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1870 fprintf (FILE, "$%s%d:\n", PREFIX, NUM)
1872 /* This is how to output a label for a jump table. Arguments are the same as
1873 for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
1876 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
1877 { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
1879 /* This is how to store into the string LABEL
1880 the symbol_ref name of an internal numbered label where
1881 PREFIX is the class of label and NUM is the number within the class.
1882 This is suitable for output with `assemble_name'. */
1884 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1885 sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM))
1887 /* Check a floating-point value for validity for a particular machine mode. */
1889 #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
1890 ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW))
1892 /* We use the default ASCII-output routine, except that we don't write more
1893 than 50 characters since the assembler doesn't support very long lines. */
1895 #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \
1897 FILE *_hide_asm_out_file = (MYFILE); \
1898 const unsigned char *_hide_p = (const unsigned char *) (MYSTRING); \
1899 int _hide_thissize = (MYLENGTH); \
1900 int _size_so_far = 0; \
1902 FILE *asm_out_file = _hide_asm_out_file; \
1903 const unsigned char *p = _hide_p; \
1904 int thissize = _hide_thissize; \
1906 fprintf (asm_out_file, "\t.ascii \""); \
1908 for (i = 0; i < thissize; i++) \
1910 register int c = p[i]; \
1912 if (_size_so_far ++ > 50 && i < thissize - 4) \
1913 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
1915 if (c == '\"' || c == '\\') \
1916 putc ('\\', asm_out_file); \
1917 if (c >= ' ' && c < 0177) \
1918 putc (c, asm_out_file); \
1921 fprintf (asm_out_file, "\\%o", c); \
1922 /* After an octal-escape, if a digit follows, \
1923 terminate one string constant and start another. \
1924 The VAX assembler fails to stop reading the escape \
1925 after three digits, so this is the only way we \
1926 can get it to parse the data properly. */ \
1927 if (i < thissize - 1 && ISDIGIT (p[i + 1])) \
1928 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
1931 fprintf (asm_out_file, "\"\n"); \
1936 /* This is how to output an insn to push a register on the stack.
1937 It need not be very fast code. */
1939 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1940 fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \
1941 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
1944 /* This is how to output an insn to pop a register from the stack.
1945 It need not be very fast code. */
1947 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1948 fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \
1949 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
1952 /* This is how to output an element of a case-vector that is absolute.
1953 (Alpha does not use such vectors, but we must define this macro anyway.) */
1955 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort ()
1957 /* This is how to output an element of a case-vector that is relative. */
1959 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1960 fprintf (FILE, "\t.%s $L%d\n", TARGET_ABI_WINDOWS_NT ? "long" : "gprel32", \
1963 /* This is how to output an assembler line
1964 that says to advance the location counter
1965 to a multiple of 2**LOG bytes. */
1967 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1969 fprintf (FILE, "\t.align %d\n", LOG);
1971 /* This is how to advance the location counter by SIZE bytes. */
1973 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1974 fprintf (FILE, "\t.space %d\n", (SIZE))
1976 /* This says how to output an assembler line
1977 to define a global common symbol. */
1979 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1980 ( fputs ("\t.comm ", (FILE)), \
1981 assemble_name ((FILE), (NAME)), \
1982 fprintf ((FILE), ",%d\n", (SIZE)))
1984 /* This says how to output an assembler line
1985 to define a local common symbol. */
1987 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
1988 ( fputs ("\t.lcomm ", (FILE)), \
1989 assemble_name ((FILE), (NAME)), \
1990 fprintf ((FILE), ",%d\n", (SIZE)))
1992 /* Store in OUTPUT a string (made with alloca) containing
1993 an assembler-name for a local static variable named NAME.
1994 LABELNO is an integer which is different for each call. */
1996 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1997 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1998 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2001 /* Print operand X (an rtx) in assembler syntax to file FILE.
2002 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2003 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2005 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2007 /* Determine which codes are valid without a following integer. These must
2010 ~ Generates the name of the current function.
2012 / Generates the instruction suffix. The TRAP_SUFFIX and ROUND_SUFFIX
2013 attributes are examined to determine what is appropriate.
2015 , Generates single precision suffix for floating point
2016 instructions (s for IEEE, f for VAX)
2018 - Generates double precision suffix for floating point
2019 instructions (t for IEEE, g for VAX)
2022 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2023 ((CODE) == '/' || (CODE) == ',' || (CODE) == '-' || (CODE) == '~' \
2024 || (CODE) == '#' || (CODE) == '*')
2026 /* Print a memory address as an operand to reference that memory location. */
2028 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2029 print_operand_address((FILE), (ADDR))
2031 /* Define the codes that are matched by predicates in alpha.c. */
2033 #define PREDICATE_CODES \
2034 {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2035 {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
2036 {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
2037 {"cint8_operand", {CONST_INT}}, \
2038 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2039 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2040 {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \
2041 {"const48_operand", {CONST_INT}}, \
2042 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2043 {"or_operand", {SUBREG, REG, CONST_INT}}, \
2044 {"mode_mask_operand", {CONST_INT}}, \
2045 {"mul8_operand", {CONST_INT}}, \
2046 {"mode_width_operand", {CONST_INT}}, \
2047 {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2048 {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
2049 {"alpha_zero_comparison_operator", {EQ, NE, LE, LT, LEU, LTU}}, \
2050 {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \
2051 {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
2052 {"alpha_fp_comparison_operator", {EQ, LE, LT, UNORDERED}}, \
2053 {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
2054 {"fp0_operand", {CONST_DOUBLE}}, \
2055 {"current_file_function_operand", {SYMBOL_REF}}, \
2056 {"direct_call_operand", {SYMBOL_REF}}, \
2057 {"local_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2058 {"small_symbolic_operand", {SYMBOL_REF, CONST}}, \
2059 {"global_symbolic_operand", {SYMBOL_REF, CONST}}, \
2060 {"call_operand", {REG, SYMBOL_REF}}, \
2061 {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2062 SYMBOL_REF, CONST, LABEL_REF, HIGH}}, \
2063 {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2064 SYMBOL_REF, CONST, LABEL_REF, HIGH}}, \
2065 {"some_ni_operand", {SUBREG, REG, MEM}}, \
2066 {"aligned_memory_operand", {MEM}}, \
2067 {"unaligned_memory_operand", {MEM}}, \
2068 {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
2069 {"any_memory_operand", {MEM}}, \
2070 {"hard_fp_register_operand", {SUBREG, REG}}, \
2071 {"hard_int_register_operand", {SUBREG, REG}}, \
2072 {"reg_not_elim_operand", {SUBREG, REG}}, \
2073 {"reg_no_subreg_operand", {REG}}, \
2074 {"addition_operation", {PLUS}}, \
2075 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2076 {"some_small_symbolic_mem_operand", {SET, PARALLEL}},
2078 /* Define the `__builtin_va_list' type for the ABI. */
2079 #define BUILD_VA_LIST_TYPE(VALIST) \
2080 (VALIST) = alpha_build_va_list ()
2082 /* Implement `va_start' for varargs and stdarg. */
2083 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2084 alpha_va_start (stdarg, valist, nextarg)
2086 /* Implement `va_arg'. */
2087 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2088 alpha_va_arg (valist, type)
2090 /* Tell collect that the object format is ECOFF. */
2091 #define OBJECT_FORMAT_COFF
2092 #define EXTENDED_COFF
2094 /* If we use NM, pass -g to it so it only lists globals. */
2095 #define NM_FLAGS "-pg"
2097 /* Definitions for debugging. */
2099 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
2100 #define DBX_DEBUGGING_INFO /* generate embedded stabs */
2101 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
2103 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
2104 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
2108 /* Correct the offset of automatic variables and arguments. Note that
2109 the Alpha debug format wants all automatic variables and arguments
2110 to be in terms of two different offsets from the virtual frame pointer,
2111 which is the stack pointer before any adjustment in the function.
2112 The offset for the argument pointer is fixed for the native compiler,
2113 it is either zero (for the no arguments case) or large enough to hold
2114 all argument registers.
2115 The offset for the auto pointer is the fourth argument to the .frame
2116 directive (local_offset).
2117 To stay compatible with the native tools we use the same offsets
2118 from the virtual frame pointer and adjust the debugger arg/auto offsets
2119 accordingly. These debugger offsets are set up in output_prolog. */
2121 extern long alpha_arg_offset
;
2122 extern long alpha_auto_offset
;
2123 #define DEBUGGER_AUTO_OFFSET(X) \
2124 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset)
2125 #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset)
2128 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2129 alpha_output_lineno (STREAM, LINE)
2131 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2132 alpha_output_filename (STREAM, NAME)
2134 /* mips-tfile.c limits us to strings of one page. We must underestimate this
2135 number, because the real length runs past this up to the next
2136 continuation point. This is really a dbxout.c bug. */
2137 #define DBX_CONTIN_LENGTH 3000
2139 /* By default, turn on GDB extensions. */
2140 #define DEFAULT_GDB_EXTENSIONS 1
2142 /* Stabs-in-ECOFF can't handle dbxout_function_end(). */
2143 #define NO_DBX_FUNCTION_END 1
2145 /* If we are smuggling stabs through the ALPHA ECOFF object
2146 format, put a comment in front of the .stab<x> operation so
2147 that the ALPHA assembler does not choke. The mips-tfile program
2148 will correctly put the stab into the object file. */
2150 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
2151 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
2152 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
2154 /* Forward references to tags are allowed. */
2155 #define SDB_ALLOW_FORWARD_REFERENCES
2157 /* Unknown tags are also allowed. */
2158 #define SDB_ALLOW_UNKNOWN_REFERENCES
2160 #define PUT_SDB_DEF(a) \
2162 fprintf (asm_out_file, "\t%s.def\t", \
2163 (TARGET_GAS) ? "" : "#"); \
2164 ASM_OUTPUT_LABELREF (asm_out_file, a); \
2165 fputc (';', asm_out_file); \
2168 #define PUT_SDB_PLAIN_DEF(a) \
2170 fprintf (asm_out_file, "\t%s.def\t.%s;", \
2171 (TARGET_GAS) ? "" : "#", (a)); \
2174 #define PUT_SDB_TYPE(a) \
2176 fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \
2179 /* For block start and end, we create labels, so that
2180 later we can figure out where the correct offset is.
2181 The normal .ent/.end serve well enough for functions,
2182 so those are just commented out. */
2184 extern int sdb_label_count
; /* block start/end next label # */
2186 #define PUT_SDB_BLOCK_START(LINE) \
2188 fprintf (asm_out_file, \
2189 "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \
2191 (TARGET_GAS) ? "" : "#", \
2194 sdb_label_count++; \
2197 #define PUT_SDB_BLOCK_END(LINE) \
2199 fprintf (asm_out_file, \
2200 "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \
2202 (TARGET_GAS) ? "" : "#", \
2205 sdb_label_count++; \
2208 #define PUT_SDB_FUNCTION_START(LINE)
2210 #define PUT_SDB_FUNCTION_END(LINE)
2212 #define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME))
2214 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
2215 mips-tdump.c to print them out.
2217 These must match the corresponding definitions in gdb/mipsread.c.
2218 Unfortunately, gcc and gdb do not currently share any directories. */
2220 #define CODE_MASK 0x8F300
2221 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
2222 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
2223 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
2225 /* Override some mips-tfile definitions. */
2227 #define SHASH_SIZE 511
2228 #define THASH_SIZE 55
2230 /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */
2232 #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7)
2234 /* The system headers under Alpha systems are generally C++-aware. */
2235 #define NO_IMPLICIT_EXTERN_C
2237 /* Generate calls to memcpy, etc., not bcopy, etc. */
2238 #define TARGET_MEM_FUNCTIONS 1
2240 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2241 Used for C++ multiple inheritance. */
2242 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2243 alpha_output_mi_thunk_osf (FILE, THUNK_FNDECL, DELTA, FUNCTION)