1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
55 /* Specify which cpu to schedule for. */
57 enum processor_type alpha_cpu
;
58 static const char * const alpha_cpu_name
[] =
63 /* Specify how accurate floating-point traps need to be. */
65 enum alpha_trap_precision alpha_tp
;
67 /* Specify the floating-point rounding mode. */
69 enum alpha_fp_rounding_mode alpha_fprm
;
71 /* Specify which things cause traps. */
73 enum alpha_fp_trap_mode alpha_fptm
;
75 /* Specify bit size of immediate TLS offsets. */
77 int alpha_tls_size
= 32;
79 /* Strings decoded into the above options. */
81 const char *alpha_cpu_string
; /* -mcpu= */
82 const char *alpha_tune_string
; /* -mtune= */
83 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
84 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
85 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
86 const char *alpha_mlat_string
; /* -mmemory-latency= */
87 const char *alpha_tls_size_string
; /* -mtls-size=[16|32|64] */
89 /* Save information from a "cmpxx" operation until the branch or scc is
92 struct alpha_compare alpha_compare
;
94 /* Nonzero if inside of a function, because the Alpha asm can't
95 handle .files inside of functions. */
97 static int inside_function
= FALSE
;
99 /* The number of cycles of latency we should assume on memory reads. */
101 int alpha_memory_latency
= 3;
103 /* Whether the function needs the GP. */
105 static int alpha_function_needs_gp
;
107 /* The alias set for prologue/epilogue register save/restore. */
109 static GTY(()) int alpha_sr_alias_set
;
111 /* The assembler name of the current function. */
113 static const char *alpha_fnname
;
115 /* The next explicit relocation sequence number. */
116 extern GTY(()) int alpha_next_sequence_number
;
117 int alpha_next_sequence_number
= 1;
119 /* The literal and gpdisp sequence numbers for this insn, as printed
120 by %# and %* respectively. */
121 extern GTY(()) int alpha_this_literal_sequence_number
;
122 extern GTY(()) int alpha_this_gpdisp_sequence_number
;
123 int alpha_this_literal_sequence_number
;
124 int alpha_this_gpdisp_sequence_number
;
126 /* Costs of various operations on the different architectures. */
128 struct alpha_rtx_cost_data
130 unsigned char fp_add
;
131 unsigned char fp_mult
;
132 unsigned char fp_div_sf
;
133 unsigned char fp_div_df
;
134 unsigned char int_mult_si
;
135 unsigned char int_mult_di
;
136 unsigned char int_shift
;
137 unsigned char int_cmov
;
140 static struct alpha_rtx_cost_data
const alpha_rtx_cost_data
[PROCESSOR_MAX
] =
143 COSTS_N_INSNS (6), /* fp_add */
144 COSTS_N_INSNS (6), /* fp_mult */
145 COSTS_N_INSNS (34), /* fp_div_sf */
146 COSTS_N_INSNS (63), /* fp_div_df */
147 COSTS_N_INSNS (23), /* int_mult_si */
148 COSTS_N_INSNS (23), /* int_mult_di */
149 COSTS_N_INSNS (2), /* int_shift */
150 COSTS_N_INSNS (2), /* int_cmov */
153 COSTS_N_INSNS (4), /* fp_add */
154 COSTS_N_INSNS (4), /* fp_mult */
155 COSTS_N_INSNS (15), /* fp_div_sf */
156 COSTS_N_INSNS (22), /* fp_div_df */
157 COSTS_N_INSNS (8), /* int_mult_si */
158 COSTS_N_INSNS (12), /* int_mult_di */
159 COSTS_N_INSNS (1) + 1, /* int_shift */
160 COSTS_N_INSNS (1), /* int_cmov */
163 COSTS_N_INSNS (4), /* fp_add */
164 COSTS_N_INSNS (4), /* fp_mult */
165 COSTS_N_INSNS (12), /* fp_div_sf */
166 COSTS_N_INSNS (15), /* fp_div_df */
167 COSTS_N_INSNS (7), /* int_mult_si */
168 COSTS_N_INSNS (7), /* int_mult_di */
169 COSTS_N_INSNS (1), /* int_shift */
170 COSTS_N_INSNS (2), /* int_cmov */
174 /* Declarations of static functions. */
175 static bool alpha_function_ok_for_sibcall
176 PARAMS ((tree
, tree
));
177 static int tls_symbolic_operand_1
178 PARAMS ((rtx
, enum machine_mode
, int, int));
179 static enum tls_model tls_symbolic_operand_type
181 static bool decl_in_text_section
183 static bool decl_has_samegp
185 static bool alpha_in_small_data_p
187 static void alpha_encode_section_info
188 PARAMS ((tree
, int));
189 static const char *alpha_strip_name_encoding
190 PARAMS ((const char *));
191 static int some_small_symbolic_operand_1
192 PARAMS ((rtx
*, void *));
193 static int split_small_symbolic_operand_1
194 PARAMS ((rtx
*, void *));
195 static bool alpha_rtx_costs
196 PARAMS ((rtx
, int, int, int *));
197 static void alpha_set_memflags_1
198 PARAMS ((rtx
, int, int, int));
199 static rtx alpha_emit_set_const_1
200 PARAMS ((rtx
, enum machine_mode
, HOST_WIDE_INT
, int));
201 static void alpha_expand_unaligned_load_words
202 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
203 static void alpha_expand_unaligned_store_words
204 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
205 static void alpha_init_builtins
207 static rtx alpha_expand_builtin
208 PARAMS ((tree
, rtx
, rtx
, enum machine_mode
, int));
209 static void alpha_sa_mask
210 PARAMS ((unsigned long *imaskP
, unsigned long *fmaskP
));
211 static int find_lo_sum_using_gp
212 PARAMS ((rtx
*, void *));
213 static int alpha_does_function_need_gp
215 static int alpha_ra_ever_killed
217 static const char *get_trap_mode_suffix
219 static const char *get_round_mode_suffix
221 static const char *get_some_local_dynamic_name
223 static int get_some_local_dynamic_name_1
224 PARAMS ((rtx
*, void *));
225 static rtx set_frame_related_p
227 static const char *alpha_lookup_xfloating_lib_func
228 PARAMS ((enum rtx_code
));
229 static int alpha_compute_xfloating_mode_arg
230 PARAMS ((enum rtx_code
, enum alpha_fp_rounding_mode
));
231 static void alpha_emit_xfloating_libcall
232 PARAMS ((const char *, rtx
, rtx
[], int, rtx
));
233 static rtx alpha_emit_xfloating_compare
234 PARAMS ((enum rtx_code
, rtx
, rtx
));
235 static void alpha_output_function_end_prologue
237 static int alpha_adjust_cost
238 PARAMS ((rtx
, rtx
, rtx
, int));
239 static int alpha_issue_rate
241 static int alpha_use_dfa_pipeline_interface
243 static int alpha_multipass_dfa_lookahead
246 #ifdef OBJECT_FORMAT_ELF
247 static void alpha_elf_select_rtx_section
248 PARAMS ((enum machine_mode
, rtx
, unsigned HOST_WIDE_INT
));
251 #if TARGET_ABI_OPEN_VMS
252 static bool alpha_linkage_symbol_p
253 PARAMS ((const char *symname
));
254 static int alpha_write_one_linkage
255 PARAMS ((splay_tree_node
, void *));
256 static void alpha_write_linkage
257 PARAMS ((FILE *, const char *, tree
));
261 static void alpha_output_mi_thunk_osf
262 PARAMS ((FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
));
265 static struct machine_function
* alpha_init_machine_status
268 static void unicosmk_output_deferred_case_vectors
PARAMS ((FILE *));
269 static void unicosmk_gen_dsib
PARAMS ((unsigned long *imaskP
));
270 static void unicosmk_output_ssib
PARAMS ((FILE *, const char *));
271 static int unicosmk_need_dex
PARAMS ((rtx
));
273 /* Get the number of args of a function in one of two ways. */
274 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
275 #define NUM_ARGS current_function_args_info.num_args
277 #define NUM_ARGS current_function_args_info
283 /* Initialize the GCC target structure. */
284 #if TARGET_ABI_OPEN_VMS
285 const struct attribute_spec vms_attribute_table
[];
286 static unsigned int vms_section_type_flags
PARAMS ((tree
, const char *, int));
287 static void vms_asm_named_section
PARAMS ((const char *, unsigned int));
288 static void vms_asm_out_constructor
PARAMS ((rtx
, int));
289 static void vms_asm_out_destructor
PARAMS ((rtx
, int));
290 # undef TARGET_ATTRIBUTE_TABLE
291 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
292 # undef TARGET_SECTION_TYPE_FLAGS
293 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
296 #undef TARGET_IN_SMALL_DATA_P
297 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
298 #undef TARGET_ENCODE_SECTION_INFO
299 #define TARGET_ENCODE_SECTION_INFO alpha_encode_section_info
300 #undef TARGET_STRIP_NAME_ENCODING
301 #define TARGET_STRIP_NAME_ENCODING alpha_strip_name_encoding
303 #if TARGET_ABI_UNICOSMK
304 static void unicosmk_asm_named_section
PARAMS ((const char *, unsigned int));
305 static void unicosmk_insert_attributes
PARAMS ((tree
, tree
*));
306 static unsigned int unicosmk_section_type_flags
PARAMS ((tree
, const char *,
308 static void unicosmk_unique_section
PARAMS ((tree
, int));
309 # undef TARGET_INSERT_ATTRIBUTES
310 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
311 # undef TARGET_SECTION_TYPE_FLAGS
312 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
313 # undef TARGET_ASM_UNIQUE_SECTION
314 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
315 # undef TARGET_ASM_GLOBALIZE_LABEL
316 # define TARGET_ASM_GLOBALIZE_LABEL hook_FILEptr_constcharptr_void
319 #undef TARGET_ASM_ALIGNED_HI_OP
320 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
321 #undef TARGET_ASM_ALIGNED_DI_OP
322 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
324 /* Default unaligned ops are provided for ELF systems. To get unaligned
325 data for non-ELF systems, we have to turn off auto alignment. */
326 #ifndef OBJECT_FORMAT_ELF
327 #undef TARGET_ASM_UNALIGNED_HI_OP
328 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
329 #undef TARGET_ASM_UNALIGNED_SI_OP
330 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
331 #undef TARGET_ASM_UNALIGNED_DI_OP
332 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
335 #ifdef OBJECT_FORMAT_ELF
336 #undef TARGET_ASM_SELECT_RTX_SECTION
337 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
340 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
341 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
343 #undef TARGET_SCHED_ADJUST_COST
344 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
345 #undef TARGET_SCHED_ISSUE_RATE
346 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
347 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
348 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
349 alpha_use_dfa_pipeline_interface
350 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
351 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
352 alpha_multipass_dfa_lookahead
354 #undef TARGET_HAVE_TLS
355 #define TARGET_HAVE_TLS HAVE_AS_TLS
357 #undef TARGET_INIT_BUILTINS
358 #define TARGET_INIT_BUILTINS alpha_init_builtins
359 #undef TARGET_EXPAND_BUILTIN
360 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
362 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
363 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
366 #undef TARGET_ASM_OUTPUT_MI_THUNK
367 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
368 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
369 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
372 #undef TARGET_RTX_COSTS
373 #define TARGET_RTX_COSTS alpha_rtx_costs
374 #undef TARGET_ADDRESS_COST
375 #define TARGET_ADDRESS_COST hook_int_rtx_0
377 struct gcc_target targetm
= TARGET_INITIALIZER
;
379 /* Parse target option strings. */
385 static const struct cpu_table
{
386 const char *const name
;
387 const enum processor_type processor
;
390 #define EV5_MASK (MASK_CPU_EV5)
391 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
392 { "ev4", PROCESSOR_EV4
, 0 },
393 { "ev45", PROCESSOR_EV4
, 0 },
394 { "21064", PROCESSOR_EV4
, 0 },
395 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
396 { "21164", PROCESSOR_EV5
, EV5_MASK
},
397 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
398 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
399 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
400 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
401 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
402 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
403 { "21264", PROCESSOR_EV6
, EV6_MASK
},
404 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
405 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
409 /* Unicos/Mk doesn't have shared libraries. */
410 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
412 warning ("-f%s ignored for Unicos/Mk (not supported)",
413 (flag_pic
> 1) ? "PIC" : "pic");
417 /* On Unicos/Mk, the native compiler consistenly generates /d suffices for
418 floating-point instructions. Make that the default for this target. */
419 if (TARGET_ABI_UNICOSMK
)
420 alpha_fprm
= ALPHA_FPRM_DYN
;
422 alpha_fprm
= ALPHA_FPRM_NORM
;
424 alpha_tp
= ALPHA_TP_PROG
;
425 alpha_fptm
= ALPHA_FPTM_N
;
427 /* We cannot use su and sui qualifiers for conversion instructions on
428 Unicos/Mk. I'm not sure if this is due to assembler or hardware
429 limitations. Right now, we issue a warning if -mieee is specified
430 and then ignore it; eventually, we should either get it right or
431 disable the option altogether. */
435 if (TARGET_ABI_UNICOSMK
)
436 warning ("-mieee not supported on Unicos/Mk");
439 alpha_tp
= ALPHA_TP_INSN
;
440 alpha_fptm
= ALPHA_FPTM_SU
;
444 if (TARGET_IEEE_WITH_INEXACT
)
446 if (TARGET_ABI_UNICOSMK
)
447 warning ("-mieee-with-inexact not supported on Unicos/Mk");
450 alpha_tp
= ALPHA_TP_INSN
;
451 alpha_fptm
= ALPHA_FPTM_SUI
;
457 if (! strcmp (alpha_tp_string
, "p"))
458 alpha_tp
= ALPHA_TP_PROG
;
459 else if (! strcmp (alpha_tp_string
, "f"))
460 alpha_tp
= ALPHA_TP_FUNC
;
461 else if (! strcmp (alpha_tp_string
, "i"))
462 alpha_tp
= ALPHA_TP_INSN
;
464 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string
);
467 if (alpha_fprm_string
)
469 if (! strcmp (alpha_fprm_string
, "n"))
470 alpha_fprm
= ALPHA_FPRM_NORM
;
471 else if (! strcmp (alpha_fprm_string
, "m"))
472 alpha_fprm
= ALPHA_FPRM_MINF
;
473 else if (! strcmp (alpha_fprm_string
, "c"))
474 alpha_fprm
= ALPHA_FPRM_CHOP
;
475 else if (! strcmp (alpha_fprm_string
,"d"))
476 alpha_fprm
= ALPHA_FPRM_DYN
;
478 error ("bad value `%s' for -mfp-rounding-mode switch",
482 if (alpha_fptm_string
)
484 if (strcmp (alpha_fptm_string
, "n") == 0)
485 alpha_fptm
= ALPHA_FPTM_N
;
486 else if (strcmp (alpha_fptm_string
, "u") == 0)
487 alpha_fptm
= ALPHA_FPTM_U
;
488 else if (strcmp (alpha_fptm_string
, "su") == 0)
489 alpha_fptm
= ALPHA_FPTM_SU
;
490 else if (strcmp (alpha_fptm_string
, "sui") == 0)
491 alpha_fptm
= ALPHA_FPTM_SUI
;
493 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string
);
496 if (alpha_tls_size_string
)
498 if (strcmp (alpha_tls_size_string
, "16") == 0)
500 else if (strcmp (alpha_tls_size_string
, "32") == 0)
502 else if (strcmp (alpha_tls_size_string
, "64") == 0)
505 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string
);
509 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
510 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
512 if (alpha_cpu_string
)
514 for (i
= 0; cpu_table
[i
].name
; i
++)
515 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
517 alpha_cpu
= cpu_table
[i
].processor
;
518 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
519 | MASK_CPU_EV5
| MASK_CPU_EV6
);
520 target_flags
|= cpu_table
[i
].flags
;
523 if (! cpu_table
[i
].name
)
524 error ("bad value `%s' for -mcpu switch", alpha_cpu_string
);
527 if (alpha_tune_string
)
529 for (i
= 0; cpu_table
[i
].name
; i
++)
530 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
532 alpha_cpu
= cpu_table
[i
].processor
;
535 if (! cpu_table
[i
].name
)
536 error ("bad value `%s' for -mcpu switch", alpha_tune_string
);
539 /* Do some sanity checks on the above options. */
541 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
543 warning ("trap mode not supported on Unicos/Mk");
544 alpha_fptm
= ALPHA_FPTM_N
;
547 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
548 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
550 warning ("fp software completion requires -mtrap-precision=i");
551 alpha_tp
= ALPHA_TP_INSN
;
556 /* Except for EV6 pass 1 (not released), we always have precise
557 arithmetic traps. Which means we can do software completion
558 without minding trap shadows. */
559 alpha_tp
= ALPHA_TP_PROG
;
562 if (TARGET_FLOAT_VAX
)
564 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
566 warning ("rounding mode not supported for VAX floats");
567 alpha_fprm
= ALPHA_FPRM_NORM
;
569 if (alpha_fptm
== ALPHA_FPTM_SUI
)
571 warning ("trap mode not supported for VAX floats");
572 alpha_fptm
= ALPHA_FPTM_SU
;
580 if (!alpha_mlat_string
)
581 alpha_mlat_string
= "L1";
583 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
584 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
586 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
587 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
588 && alpha_mlat_string
[2] == '\0')
590 static int const cache_latency
[][4] =
592 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
593 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
594 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
597 lat
= alpha_mlat_string
[1] - '0';
598 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
600 warning ("L%d cache latency unknown for %s",
601 lat
, alpha_cpu_name
[alpha_cpu
]);
605 lat
= cache_latency
[alpha_cpu
][lat
-1];
607 else if (! strcmp (alpha_mlat_string
, "main"))
609 /* Most current memories have about 370ns latency. This is
610 a reasonable guess for a fast cpu. */
615 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string
);
619 alpha_memory_latency
= lat
;
622 /* Default the definition of "small data" to 8 bytes. */
626 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
628 target_flags
|= MASK_SMALL_DATA
;
629 else if (flag_pic
== 2)
630 target_flags
&= ~MASK_SMALL_DATA
;
632 /* Align labels and loops for optimal branching. */
633 /* ??? Kludge these by not doing anything if we don't optimize and also if
634 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
635 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
637 if (align_loops
<= 0)
639 if (align_jumps
<= 0)
642 if (align_functions
<= 0)
643 align_functions
= 16;
645 /* Acquire a unique set number for our register saves and restores. */
646 alpha_sr_alias_set
= new_alias_set ();
648 /* Register variables and functions with the garbage collector. */
650 /* Set up function hooks. */
651 init_machine_status
= alpha_init_machine_status
;
653 /* Tell the compiler when we're using VAX floating point. */
654 if (TARGET_FLOAT_VAX
)
656 real_format_for_mode
[SFmode
- QFmode
] = &vax_f_format
;
657 real_format_for_mode
[DFmode
- QFmode
] = &vax_g_format
;
658 real_format_for_mode
[TFmode
- QFmode
] = NULL
;
662 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
670 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
672 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
678 /* Returns 1 if OP is either the constant zero or a register. If a
679 register, it must be in the proper mode unless MODE is VOIDmode. */
682 reg_or_0_operand (op
, mode
)
684 enum machine_mode mode
;
686 return op
== CONST0_RTX (mode
) || register_operand (op
, mode
);
689 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
693 reg_or_6bit_operand (op
, mode
)
695 enum machine_mode mode
;
697 return ((GET_CODE (op
) == CONST_INT
698 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64)
699 || register_operand (op
, mode
));
703 /* Return 1 if OP is an 8-bit constant or any register. */
706 reg_or_8bit_operand (op
, mode
)
708 enum machine_mode mode
;
710 return ((GET_CODE (op
) == CONST_INT
711 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
712 || register_operand (op
, mode
));
715 /* Return 1 if OP is a constant or any register. */
718 reg_or_const_int_operand (op
, mode
)
720 enum machine_mode mode
;
722 return GET_CODE (op
) == CONST_INT
|| register_operand (op
, mode
);
725 /* Return 1 if OP is an 8-bit constant. */
728 cint8_operand (op
, mode
)
730 enum machine_mode mode ATTRIBUTE_UNUSED
;
732 return ((GET_CODE (op
) == CONST_INT
733 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100));
736 /* Return 1 if the operand is a valid second operand to an add insn. */
739 add_operand (op
, mode
)
741 enum machine_mode mode
;
743 if (GET_CODE (op
) == CONST_INT
)
744 /* Constraints I, J, O and P are covered by K. */
745 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K')
746 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
748 return register_operand (op
, mode
);
751 /* Return 1 if the operand is a valid second operand to a sign-extending
755 sext_add_operand (op
, mode
)
757 enum machine_mode mode
;
759 if (GET_CODE (op
) == CONST_INT
)
760 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
761 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'));
763 return reg_not_elim_operand (op
, mode
);
766 /* Return 1 if OP is the constant 4 or 8. */
769 const48_operand (op
, mode
)
771 enum machine_mode mode ATTRIBUTE_UNUSED
;
773 return (GET_CODE (op
) == CONST_INT
774 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
777 /* Return 1 if OP is a valid first operand to an AND insn. */
780 and_operand (op
, mode
)
782 enum machine_mode mode
;
784 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
785 return (zap_mask (CONST_DOUBLE_LOW (op
))
786 && zap_mask (CONST_DOUBLE_HIGH (op
)));
788 if (GET_CODE (op
) == CONST_INT
)
789 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
790 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
791 || zap_mask (INTVAL (op
)));
793 return register_operand (op
, mode
);
796 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
799 or_operand (op
, mode
)
801 enum machine_mode mode
;
803 if (GET_CODE (op
) == CONST_INT
)
804 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
805 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100);
807 return register_operand (op
, mode
);
810 /* Return 1 if OP is a constant that is the width, in bits, of an integral
811 mode smaller than DImode. */
814 mode_width_operand (op
, mode
)
816 enum machine_mode mode ATTRIBUTE_UNUSED
;
818 return (GET_CODE (op
) == CONST_INT
819 && (INTVAL (op
) == 8 || INTVAL (op
) == 16
820 || INTVAL (op
) == 32 || INTVAL (op
) == 64));
823 /* Return 1 if OP is a constant that is the width of an integral machine mode
824 smaller than an integer. */
827 mode_mask_operand (op
, mode
)
829 enum machine_mode mode ATTRIBUTE_UNUSED
;
831 if (GET_CODE (op
) == CONST_INT
)
833 HOST_WIDE_INT value
= INTVAL (op
);
839 if (value
== 0xffffffff)
844 else if (HOST_BITS_PER_WIDE_INT
== 32 && GET_CODE (op
) == CONST_DOUBLE
)
846 if (CONST_DOUBLE_LOW (op
) == 0xffffffff && CONST_DOUBLE_HIGH (op
) == 0)
853 /* Return 1 if OP is a multiple of 8 less than 64. */
856 mul8_operand (op
, mode
)
858 enum machine_mode mode ATTRIBUTE_UNUSED
;
860 return (GET_CODE (op
) == CONST_INT
861 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
862 && (INTVAL (op
) & 7) == 0);
865 /* Return 1 if OP is the zero constant for MODE. */
868 const0_operand (op
, mode
)
870 enum machine_mode mode
;
872 return op
== CONST0_RTX (mode
);
875 /* Return 1 if OP is a hard floating-point register. */
878 hard_fp_register_operand (op
, mode
)
880 enum machine_mode mode
;
882 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
885 if (GET_CODE (op
) == SUBREG
)
886 op
= SUBREG_REG (op
);
887 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == FLOAT_REGS
;
890 /* Return 1 if OP is a hard general register. */
893 hard_int_register_operand (op
, mode
)
895 enum machine_mode mode
;
897 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
900 if (GET_CODE (op
) == SUBREG
)
901 op
= SUBREG_REG (op
);
902 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
;
905 /* Return 1 if OP is a register or a constant integer. */
909 reg_or_cint_operand (op
, mode
)
911 enum machine_mode mode
;
913 return (GET_CODE (op
) == CONST_INT
914 || register_operand (op
, mode
));
917 /* Return 1 if OP is something that can be reloaded into a register;
918 if it is a MEM, it need not be valid. */
921 some_operand (op
, mode
)
923 enum machine_mode mode
;
925 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
928 switch (GET_CODE (op
))
942 return some_operand (SUBREG_REG (op
), VOIDmode
);
951 /* Likewise, but don't accept constants. */
954 some_ni_operand (op
, mode
)
956 enum machine_mode mode
;
958 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
961 if (GET_CODE (op
) == SUBREG
)
962 op
= SUBREG_REG (op
);
964 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == MEM
);
967 /* Return 1 if OP is a valid operand for the source of a move insn. */
970 input_operand (op
, mode
)
972 enum machine_mode mode
;
974 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
977 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
980 switch (GET_CODE (op
))
985 if (TARGET_EXPLICIT_RELOCS
)
987 /* We don't split symbolic operands into something unintelligable
988 until after reload, but we do not wish non-small, non-global
989 symbolic operands to be reconstructed from their high/lo_sum
991 return (small_symbolic_operand (op
, mode
)
992 || global_symbolic_operand (op
, mode
)
993 || gotdtp_symbolic_operand (op
, mode
)
994 || gottp_symbolic_operand (op
, mode
));
997 /* This handles both the Windows/NT and OSF cases. */
998 return mode
== ptr_mode
|| mode
== DImode
;
1001 return (TARGET_EXPLICIT_RELOCS
1002 && local_symbolic_operand (XEXP (op
, 0), mode
));
1009 if (register_operand (op
, mode
))
1011 /* ... fall through ... */
1013 return ((TARGET_BWX
|| (mode
!= HImode
&& mode
!= QImode
))
1014 && general_operand (op
, mode
));
1018 return op
== CONST0_RTX (mode
);
1021 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
1023 case CONSTANT_P_RTX
:
1033 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
1034 file, and in the same section as the current function. */
1037 samegp_function_operand (op
, mode
)
1039 enum machine_mode mode ATTRIBUTE_UNUSED
;
1041 if (GET_CODE (op
) != SYMBOL_REF
)
1044 /* Easy test for recursion. */
1045 if (op
== XEXP (DECL_RTL (current_function_decl
), 0))
1048 /* Otherwise, encode_section_info recorded whether we are to treat
1049 this symbol as having the same GP. */
1050 return SYMBOL_REF_FLAG (op
);
1053 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
1056 direct_call_operand (op
, mode
)
1058 enum machine_mode mode
;
1060 /* Must share the same GP. */
1061 if (!samegp_function_operand (op
, mode
))
1064 /* If profiling is implemented via linker tricks, we can't jump
1065 to the nogp alternate entry point. Note that current_function_profile
1066 would not be correct, since that doesn't indicate if the target
1067 function uses profiling. */
1068 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
1069 but is approximately correct for the OSF ABIs. Don't know
1070 what to do for VMS, NT, or UMK. */
1071 if (!TARGET_PROFILING_NEEDS_GP
&& profile_flag
)
1074 /* Must be "near" so that the branch is assumed to reach. With
1075 -msmall-text, this is true of all local symbols. */
1076 if (TARGET_SMALL_TEXT
)
1079 /* Otherwise, a decl is "near" if it is defined in the same section.
1080 See alpha_encode_section_info for commentary. */
1081 return op
->jump
&& decl_in_text_section (cfun
->decl
);
1084 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
1085 a (non-tls) variable known to be defined in this file. */
1088 local_symbolic_operand (op
, mode
)
1090 enum machine_mode mode
;
1094 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1097 if (GET_CODE (op
) == LABEL_REF
)
1100 if (GET_CODE (op
) == CONST
1101 && GET_CODE (XEXP (op
, 0)) == PLUS
1102 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1103 op
= XEXP (XEXP (op
, 0), 0);
1105 if (GET_CODE (op
) != SYMBOL_REF
)
1108 /* Easy pickings. */
1109 if (CONSTANT_POOL_ADDRESS_P (op
) || STRING_POOL_ADDRESS_P (op
))
1112 /* ??? SYMBOL_REF_FLAG is set for local function symbols, but we
1113 run into problems with the rtl inliner in that the symbol was
1114 once external, but is local after inlining, which results in
1115 unrecognizable insns. */
1119 /* If @[LS], then alpha_encode_section_info sez it's local. */
1120 if (str
[0] == '@' && (str
[1] == 'L' || str
[1] == 'S'))
1123 /* If *$, then ASM_GENERATE_INTERNAL_LABEL sez it's local. */
1124 if (str
[0] == '*' && str
[1] == '$')
1130 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1131 known to be defined in this file in the small data area. */
1134 small_symbolic_operand (op
, mode
)
1136 enum machine_mode mode ATTRIBUTE_UNUSED
;
1140 if (! TARGET_SMALL_DATA
)
1143 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1146 if (GET_CODE (op
) == CONST
1147 && GET_CODE (XEXP (op
, 0)) == PLUS
1148 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1149 op
= XEXP (XEXP (op
, 0), 0);
1151 if (GET_CODE (op
) != SYMBOL_REF
)
1154 if (CONSTANT_POOL_ADDRESS_P (op
))
1155 return GET_MODE_SIZE (get_pool_mode (op
)) <= (unsigned) g_switch_value
;
1159 return str
[0] == '@' && str
[1] == 'S';
1163 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1164 not known (or known not) to be defined in this file. */
1167 global_symbolic_operand (op
, mode
)
1169 enum machine_mode mode
;
1173 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1176 if (GET_CODE (op
) == CONST
1177 && GET_CODE (XEXP (op
, 0)) == PLUS
1178 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1179 op
= XEXP (XEXP (op
, 0), 0);
1181 if (GET_CODE (op
) != SYMBOL_REF
)
1184 if (local_symbolic_operand (op
, mode
))
1187 /* Also verify that it's not a TLS symbol. */
1189 return str
[0] != '%' && str
[0] != '@';
1192 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
1195 call_operand (op
, mode
)
1197 enum machine_mode mode
;
1202 if (GET_CODE (op
) == REG
)
1206 /* Disallow virtual registers to cope with pathalogical test cases
1207 such as compile/930117-1.c in which the virtual reg decomposes
1208 to the frame pointer. Which is a hard reg that is not $27. */
1209 return (REGNO (op
) == 27 || REGNO (op
) > LAST_VIRTUAL_REGISTER
);
1214 if (TARGET_ABI_UNICOSMK
)
1216 if (GET_CODE (op
) == SYMBOL_REF
)
1222 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1223 possibly with an offset. */
1226 symbolic_operand (op
, mode
)
1228 enum machine_mode mode
;
1230 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1232 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1234 if (GET_CODE (op
) == CONST
1235 && GET_CODE (XEXP (op
,0)) == PLUS
1236 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1237 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1242 /* Return true if OP is valid for a particular TLS relocation. */
1245 tls_symbolic_operand_1 (op
, mode
, size
, unspec
)
1247 enum machine_mode mode
;
1252 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1255 if (GET_CODE (op
) != CONST
)
1259 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
1261 op
= XVECEXP (op
, 0, 0);
1263 if (GET_CODE (op
) != SYMBOL_REF
)
1272 else if (str
[0] == '@')
1274 if (alpha_tls_size
> size
)
1283 return unspec
== UNSPEC_DTPREL
;
1285 return unspec
== UNSPEC_TPREL
&& size
== 64;
1287 return unspec
== UNSPEC_TPREL
&& size
< 64;
1293 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1296 dtp16_symbolic_operand (op
, mode
)
1298 enum machine_mode mode
;
1300 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_DTPREL
);
1303 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1306 dtp32_symbolic_operand (op
, mode
)
1308 enum machine_mode mode
;
1310 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_DTPREL
);
1313 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1316 gotdtp_symbolic_operand (op
, mode
)
1318 enum machine_mode mode
;
1320 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_DTPREL
);
1323 /* Return true if OP is valid for 16-bit TP relative relocations. */
1326 tp16_symbolic_operand (op
, mode
)
1328 enum machine_mode mode
;
1330 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_TPREL
);
1333 /* Return true if OP is valid for 32-bit TP relative relocations. */
1336 tp32_symbolic_operand (op
, mode
)
1338 enum machine_mode mode
;
1340 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_TPREL
);
1343 /* Return true if OP is valid for 64-bit TP relative relocations. */
1346 gottp_symbolic_operand (op
, mode
)
1348 enum machine_mode mode
;
1350 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_TPREL
);
1353 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1354 comparisons are valid in which insn. */
1357 alpha_comparison_operator (op
, mode
)
1359 enum machine_mode mode
;
1361 enum rtx_code code
= GET_CODE (op
);
1363 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1366 return (code
== EQ
|| code
== LE
|| code
== LT
1367 || code
== LEU
|| code
== LTU
);
1370 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1371 Here we know which comparisons are valid in which insn. */
1374 alpha_zero_comparison_operator (op
, mode
)
1376 enum machine_mode mode
;
1378 enum rtx_code code
= GET_CODE (op
);
1380 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1383 return (code
== EQ
|| code
== NE
|| code
== LE
|| code
== LT
1384 || code
== LEU
|| code
== LTU
);
1387 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1390 alpha_swapped_comparison_operator (op
, mode
)
1392 enum machine_mode mode
;
1394 enum rtx_code code
= GET_CODE (op
);
1396 if ((mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1397 || GET_RTX_CLASS (code
) != '<')
1400 code
= swap_condition (code
);
1401 return (code
== EQ
|| code
== LE
|| code
== LT
1402 || code
== LEU
|| code
== LTU
);
1405 /* Return 1 if OP is a signed comparison operation. */
1408 signed_comparison_operator (op
, mode
)
1410 enum machine_mode mode ATTRIBUTE_UNUSED
;
1412 enum rtx_code code
= GET_CODE (op
);
1414 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1417 return (code
== EQ
|| code
== NE
1418 || code
== LE
|| code
== LT
1419 || code
== GE
|| code
== GT
);
1422 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1423 Here we know which comparisons are valid in which insn. */
1426 alpha_fp_comparison_operator (op
, mode
)
1428 enum machine_mode mode
;
1430 enum rtx_code code
= GET_CODE (op
);
1432 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1435 return (code
== EQ
|| code
== LE
|| code
== LT
|| code
== UNORDERED
);
1438 /* Return 1 if this is a divide or modulus operator. */
1441 divmod_operator (op
, mode
)
1443 enum machine_mode mode ATTRIBUTE_UNUSED
;
1445 switch (GET_CODE (op
))
1447 case DIV
: case MOD
: case UDIV
: case UMOD
:
1457 /* Return 1 if this memory address is a known aligned register plus
1458 a constant. It must be a valid address. This means that we can do
1459 this as an aligned reference plus some offset.
1461 Take into account what reload will do. */
1464 aligned_memory_operand (op
, mode
)
1466 enum machine_mode mode
;
1470 if (reload_in_progress
)
1473 if (GET_CODE (tmp
) == SUBREG
)
1474 tmp
= SUBREG_REG (tmp
);
1475 if (GET_CODE (tmp
) == REG
1476 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1478 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1484 if (GET_CODE (op
) != MEM
1485 || GET_MODE (op
) != mode
)
1489 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1490 sorts of constructs. Dig for the real base register. */
1491 if (reload_in_progress
1492 && GET_CODE (op
) == PLUS
1493 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1494 base
= XEXP (XEXP (op
, 0), 0);
1497 if (! memory_address_p (mode
, op
))
1499 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1502 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) >= 32);
1505 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1508 unaligned_memory_operand (op
, mode
)
1510 enum machine_mode mode
;
1514 if (reload_in_progress
)
1517 if (GET_CODE (tmp
) == SUBREG
)
1518 tmp
= SUBREG_REG (tmp
);
1519 if (GET_CODE (tmp
) == REG
1520 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1522 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1528 if (GET_CODE (op
) != MEM
1529 || GET_MODE (op
) != mode
)
1533 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1534 sorts of constructs. Dig for the real base register. */
1535 if (reload_in_progress
1536 && GET_CODE (op
) == PLUS
1537 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1538 base
= XEXP (XEXP (op
, 0), 0);
1541 if (! memory_address_p (mode
, op
))
1543 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1546 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) < 32);
1549 /* Return 1 if OP is either a register or an unaligned memory location. */
1552 reg_or_unaligned_mem_operand (op
, mode
)
1554 enum machine_mode mode
;
1556 return register_operand (op
, mode
) || unaligned_memory_operand (op
, mode
);
1559 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1562 any_memory_operand (op
, mode
)
1564 enum machine_mode mode ATTRIBUTE_UNUSED
;
1566 return (GET_CODE (op
) == MEM
1567 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
1568 || (reload_in_progress
&& GET_CODE (op
) == REG
1569 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1570 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
1571 && GET_CODE (SUBREG_REG (op
)) == REG
1572 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
1575 /* Returns 1 if OP is not an eliminable register.
1577 This exists to cure a pathological abort in the s8addq (et al) patterns,
1579 long foo () { long t; bar(); return (long) &t * 26107; }
1581 which run afoul of a hack in reload to cure a (presumably) similar
1582 problem with lea-type instructions on other targets. But there is
1583 one of us and many of them, so work around the problem by selectively
1584 preventing combine from making the optimization. */
1587 reg_not_elim_operand (op
, mode
)
1589 enum machine_mode mode
;
1592 if (GET_CODE (op
) == SUBREG
)
1593 inner
= SUBREG_REG (op
);
1594 if (inner
== frame_pointer_rtx
|| inner
== arg_pointer_rtx
)
1597 return register_operand (op
, mode
);
1600 /* Return 1 is OP is a memory location that is not a reference (using
1601 an AND) to an unaligned location. Take into account what reload
1605 normal_memory_operand (op
, mode
)
1607 enum machine_mode mode ATTRIBUTE_UNUSED
;
1609 if (reload_in_progress
)
1612 if (GET_CODE (tmp
) == SUBREG
)
1613 tmp
= SUBREG_REG (tmp
);
1614 if (GET_CODE (tmp
) == REG
1615 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1617 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1619 /* This may not have been assigned an equivalent address if it will
1620 be eliminated. In that case, it doesn't matter what we do. */
1626 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) != AND
;
1629 /* Accept a register, but not a subreg of any kind. This allows us to
1630 avoid pathological cases in reload wrt data movement common in
1631 int->fp conversion. */
1634 reg_no_subreg_operand (op
, mode
)
1636 enum machine_mode mode
;
1638 if (GET_CODE (op
) != REG
)
1640 return register_operand (op
, mode
);
1643 /* Recognize an addition operation that includes a constant. Used to
1644 convince reload to canonize (plus (plus reg c1) c2) during register
1648 addition_operation (op
, mode
)
1650 enum machine_mode mode
;
1652 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1654 if (GET_CODE (op
) == PLUS
1655 && register_operand (XEXP (op
, 0), mode
)
1656 && GET_CODE (XEXP (op
, 1)) == CONST_INT
1657 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op
, 1)), 'K'))
1662 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1663 the range defined for C in [I-P]. */
1666 alpha_const_ok_for_letter_p (value
, c
)
1667 HOST_WIDE_INT value
;
1673 /* An unsigned 8 bit constant. */
1674 return (unsigned HOST_WIDE_INT
) value
< 0x100;
1676 /* The constant zero. */
1679 /* A signed 16 bit constant. */
1680 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
1682 /* A shifted signed 16 bit constant appropriate for LDAH. */
1683 return ((value
& 0xffff) == 0
1684 && ((value
) >> 31 == -1 || value
>> 31 == 0));
1686 /* A constant that can be AND'ed with using a ZAP insn. */
1687 return zap_mask (value
);
1689 /* A complemented unsigned 8 bit constant. */
1690 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
1692 /* A negated unsigned 8 bit constant. */
1693 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
1695 /* The constant 1, 2 or 3. */
1696 return value
== 1 || value
== 2 || value
== 3;
1703 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1704 matches for C in [GH]. */
1707 alpha_const_double_ok_for_letter_p (value
, c
)
1714 /* The floating point zero constant. */
1715 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
1716 && value
== CONST0_RTX (GET_MODE (value
)));
1719 /* A valid operand of a ZAP insn. */
1720 return (GET_MODE (value
) == VOIDmode
1721 && zap_mask (CONST_DOUBLE_LOW (value
))
1722 && zap_mask (CONST_DOUBLE_HIGH (value
)));
1729 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1733 alpha_extra_constraint (value
, c
)
1740 return normal_memory_operand (value
, VOIDmode
);
1742 return direct_call_operand (value
, Pmode
);
1744 return (GET_CODE (value
) == CONST_INT
1745 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
1747 return GET_CODE (value
) == HIGH
;
1749 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
1751 return (GET_CODE (value
) == CONST_VECTOR
1752 && value
== CONST0_RTX (GET_MODE (value
)));
1758 /* Return 1 if this function can directly return via $26. */
1763 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
1765 && alpha_sa_size () == 0
1766 && get_frame_size () == 0
1767 && current_function_outgoing_args_size
== 0
1768 && current_function_pretend_args_size
== 0);
1771 /* Return the ADDR_VEC associated with a tablejump insn. */
1774 alpha_tablejump_addr_vec (insn
)
1779 tmp
= JUMP_LABEL (insn
);
1782 tmp
= NEXT_INSN (tmp
);
1785 if (GET_CODE (tmp
) == JUMP_INSN
1786 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
1787 return PATTERN (tmp
);
1791 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1794 alpha_tablejump_best_label (insn
)
1797 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
1798 rtx best_label
= NULL_RTX
;
1800 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1801 there for edge frequency counts from profile data. */
1805 int n_labels
= XVECLEN (jump_table
, 1);
1806 int best_count
= -1;
1809 for (i
= 0; i
< n_labels
; i
++)
1813 for (j
= i
+ 1; j
< n_labels
; j
++)
1814 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
1815 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
1818 if (count
> best_count
)
1819 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
1823 return best_label
? best_label
: const0_rtx
;
1826 /* Return the TLS model to use for SYMBOL. */
1828 static enum tls_model
1829 tls_symbolic_operand_type (symbol
)
1834 if (GET_CODE (symbol
) != SYMBOL_REF
)
1836 str
= XSTR (symbol
, 0);
1840 /* ??? Be prepared for -ftls-model=local-dynamic. Perhaps we shouldn't
1841 have separately encoded local-ness. On well, maybe the user will use
1842 attribute visibility next time. At least we don't crash... */
1843 if (str
[1] == 'G' || str
[1] == 'D')
1844 return TLS_MODEL_GLOBAL_DYNAMIC
;
1846 return TLS_MODEL_INITIAL_EXEC
;
1848 else if (str
[0] == '@')
1852 /* Local dynamic is a waste if we're not going to combine
1853 the __tls_get_addr calls. So avoid it if not optimizing. */
1855 return TLS_MODEL_LOCAL_DYNAMIC
;
1857 return TLS_MODEL_GLOBAL_DYNAMIC
;
1860 return TLS_MODEL_INITIAL_EXEC
;
1862 return TLS_MODEL_LOCAL_EXEC
;
1869 /* Return true if the function DECL will be placed in the default text
1871 /* ??? Ideally we'd be able to always move from a SYMBOL_REF back to the
1872 decl, as that would allow us to determine if two functions are in the
1873 same section, which is what we really want to know. */
1876 decl_in_text_section (decl
)
1879 return (DECL_SECTION_NAME (decl
) == NULL_TREE
1880 && ! (flag_function_sections
1881 || (targetm
.have_named_sections
1882 && DECL_ONE_ONLY (decl
))));
1885 /* Return true if the function DECL will share the same GP as any
1886 function in the current unit of translation. */
1889 decl_has_samegp (decl
)
1892 /* Functions that are not local can be overridden, and thus may
1893 not share the same gp. */
1894 if (!(*targetm
.binds_local_p
) (decl
))
1897 /* If -msmall-data is in effect, assume that there is only one GP
1898 for the module, and so any local symbol has this property. We
1899 need explicit relocations to be able to enforce this for symbols
1900 not defined in this unit of translation, however. */
1901 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
1904 /* Functions that are not external are defined in this UoT. */
1905 /* ??? Irritatingly, static functions not yet emitted are still
1906 marked "external". Apply this to non-static functions only. */
1907 return !TREE_PUBLIC (decl
) || !DECL_EXTERNAL (decl
);
1910 /* Return true if EXP should be placed in the small data section. */
1913 alpha_in_small_data_p (exp
)
1916 /* We want to merge strings, so we never consider them small data. */
1917 if (TREE_CODE (exp
) == STRING_CST
)
1920 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
1922 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
1923 if (strcmp (section
, ".sdata") == 0
1924 || strcmp (section
, ".sbss") == 0)
1929 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
1931 /* If this is an incomplete type with size 0, then we can't put it
1932 in sdata because it might be too big when completed. */
1933 if (size
> 0 && size
<= g_switch_value
)
1940 /* If we are referencing a function that is static, make the SYMBOL_REF
1941 special. We use this to see indicate we can branch to this function
1942 without setting PV or restoring GP.
1944 If this is a variable that is known to be defined locally, add "@v"
1945 to the name. If in addition the variable is to go in .sdata/.sbss,
1946 then add "@s" instead. */
1949 alpha_encode_section_info (decl
, first
)
1951 int first ATTRIBUTE_UNUSED
;
1953 const char *symbol_str
;
1958 rtl
= DECL_P (decl
) ? DECL_RTL (decl
) : TREE_CST_RTL (decl
);
1960 /* Careful not to prod global register variables. */
1961 if (GET_CODE (rtl
) != MEM
)
1963 symbol
= XEXP (rtl
, 0);
1964 if (GET_CODE (symbol
) != SYMBOL_REF
)
1967 /* A variable is considered "local" if it is defined in this module. */
1968 is_local
= (*targetm
.binds_local_p
) (decl
);
1970 if (TREE_CODE (decl
) == FUNCTION_DECL
)
1972 /* Mark whether the decl is "near" in distance. If -msmall-text is
1973 in effect, this is trivially true of all local symbols. */
1974 if (TARGET_SMALL_TEXT
)
1981 /* Otherwise, a decl is "near" if it is defined in this same
1982 section. What we really need is to be able to access the
1983 target decl of a call from the call_insn pattern, so that
1984 we can determine if the call is from the same section. We
1985 can't do that at present, so handle the common case and
1986 match up .text with .text.
1988 Delay marking public functions until they are emitted; otherwise
1989 we don't know that they exist in this unit of translation. */
1990 if (!TREE_PUBLIC (decl
) && decl_in_text_section (decl
))
1994 /* Indicate whether the target function shares the same GP as any
1995 function emitted in this unit of translation. */
1996 if (decl_has_samegp (decl
))
1997 SYMBOL_REF_FLAG (symbol
) = 1;
2001 /* Early out if we're not going to do anything with this data. */
2002 if (! TARGET_EXPLICIT_RELOCS
)
2005 symbol_str
= XSTR (symbol
, 0);
2007 /* Care for TLS variables. */
2008 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL (decl
))
2010 switch (decl_tls_model (decl
))
2012 case TLS_MODEL_GLOBAL_DYNAMIC
:
2015 case TLS_MODEL_LOCAL_DYNAMIC
:
2018 case TLS_MODEL_INITIAL_EXEC
:
2021 case TLS_MODEL_LOCAL_EXEC
:
2022 encoding
= (alpha_tls_size
== 64 ? 'T' : 't');
2028 /* Determine if DECL will wind up in .sdata/.sbss. */
2029 if (alpha_in_small_data_p (decl
))
2035 /* Finally, encode this into the symbol string. */
2040 char want_prefix
= (is_local
? '@' : '%');
2041 char other_prefix
= (is_local
? '%' : '@');
2043 if (symbol_str
[0] == want_prefix
)
2045 if (symbol_str
[1] == encoding
)
2049 else if (symbol_str
[0] == other_prefix
)
2052 len
= strlen (symbol_str
) + 1;
2053 newstr
= alloca (len
+ 2);
2055 newstr
[0] = want_prefix
;
2056 newstr
[1] = encoding
;
2057 memcpy (newstr
+ 2, symbol_str
, len
);
2059 XSTR (symbol
, 0) = ggc_alloc_string (newstr
, len
+ 2 - 1);
2063 /* Undo the effects of the above. */
2066 alpha_strip_name_encoding (str
)
2069 if (str
[0] == '@' || str
[0] == '%')
2076 #if TARGET_ABI_OPEN_VMS
2078 alpha_linkage_symbol_p (symname
)
2079 const char *symname
;
2081 int symlen
= strlen (symname
);
2084 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
2089 #define LINKAGE_SYMBOL_REF_P(X) \
2090 ((GET_CODE (X) == SYMBOL_REF \
2091 && alpha_linkage_symbol_p (XSTR (X, 0))) \
2092 || (GET_CODE (X) == CONST \
2093 && GET_CODE (XEXP (X, 0)) == PLUS \
2094 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
2095 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
2098 /* legitimate_address_p recognizes an RTL expression that is a valid
2099 memory address for an instruction. The MODE argument is the
2100 machine mode for the MEM expression that wants to use this address.
2102 For Alpha, we have either a constant address or the sum of a
2103 register and a constant address, or just a register. For DImode,
2104 any of those forms can be surrounded with an AND that clear the
2105 low-order three bits; this is an "unaligned" access. */
2108 alpha_legitimate_address_p (mode
, x
, strict
)
2109 enum machine_mode mode
;
2113 /* If this is an ldq_u type address, discard the outer AND. */
2115 && GET_CODE (x
) == AND
2116 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2117 && INTVAL (XEXP (x
, 1)) == -8)
2120 /* Discard non-paradoxical subregs. */
2121 if (GET_CODE (x
) == SUBREG
2122 && (GET_MODE_SIZE (GET_MODE (x
))
2123 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2126 /* Unadorned general registers are valid. */
2129 ? STRICT_REG_OK_FOR_BASE_P (x
)
2130 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
2133 /* Constant addresses (i.e. +/- 32k) are valid. */
2134 if (CONSTANT_ADDRESS_P (x
))
2137 #if TARGET_ABI_OPEN_VMS
2138 if (LINKAGE_SYMBOL_REF_P (x
))
2142 /* Register plus a small constant offset is valid. */
2143 if (GET_CODE (x
) == PLUS
)
2145 rtx ofs
= XEXP (x
, 1);
2148 /* Discard non-paradoxical subregs. */
2149 if (GET_CODE (x
) == SUBREG
2150 && (GET_MODE_SIZE (GET_MODE (x
))
2151 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2157 && NONSTRICT_REG_OK_FP_BASE_P (x
)
2158 && GET_CODE (ofs
) == CONST_INT
)
2161 ? STRICT_REG_OK_FOR_BASE_P (x
)
2162 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
2163 && CONSTANT_ADDRESS_P (ofs
))
2166 else if (GET_CODE (x
) == ADDRESSOF
2167 && GET_CODE (ofs
) == CONST_INT
)
2171 /* If we're managing explicit relocations, LO_SUM is valid, as
2172 are small data symbols. */
2173 else if (TARGET_EXPLICIT_RELOCS
)
2175 if (small_symbolic_operand (x
, Pmode
))
2178 if (GET_CODE (x
) == LO_SUM
)
2180 rtx ofs
= XEXP (x
, 1);
2183 /* Discard non-paradoxical subregs. */
2184 if (GET_CODE (x
) == SUBREG
2185 && (GET_MODE_SIZE (GET_MODE (x
))
2186 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2189 /* Must have a valid base register. */
2192 ? STRICT_REG_OK_FOR_BASE_P (x
)
2193 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
2196 /* The symbol must be local. */
2197 if (local_symbolic_operand (ofs
, Pmode
)
2198 || dtp32_symbolic_operand (ofs
, Pmode
)
2199 || tp32_symbolic_operand (ofs
, Pmode
))
2207 /* Try machine-dependent ways of modifying an illegitimate address
2208 to be legitimate. If we find one, return the new, valid address. */
2211 alpha_legitimize_address (x
, scratch
, mode
)
2214 enum machine_mode mode ATTRIBUTE_UNUSED
;
2216 HOST_WIDE_INT addend
;
2218 /* If the address is (plus reg const_int) and the CONST_INT is not a
2219 valid offset, compute the high part of the constant and add it to
2220 the register. Then our address is (plus temp low-part-const). */
2221 if (GET_CODE (x
) == PLUS
2222 && GET_CODE (XEXP (x
, 0)) == REG
2223 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2224 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
2226 addend
= INTVAL (XEXP (x
, 1));
2231 /* If the address is (const (plus FOO const_int)), find the low-order
2232 part of the CONST_INT. Then load FOO plus any high-order part of the
2233 CONST_INT into a register. Our address is (plus reg low-part-const).
2234 This is done to reduce the number of GOT entries. */
2236 && GET_CODE (x
) == CONST
2237 && GET_CODE (XEXP (x
, 0)) == PLUS
2238 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2240 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
2241 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
2245 /* If we have a (plus reg const), emit the load as in (2), then add
2246 the two registers, and finally generate (plus reg low-part-const) as
2249 && GET_CODE (x
) == PLUS
2250 && GET_CODE (XEXP (x
, 0)) == REG
2251 && GET_CODE (XEXP (x
, 1)) == CONST
2252 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
2253 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
2255 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
2256 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
2257 XEXP (XEXP (XEXP (x
, 1), 0), 0),
2258 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
2262 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
2263 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
2265 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
2267 switch (tls_symbolic_operand_type (x
))
2269 case TLS_MODEL_GLOBAL_DYNAMIC
:
2272 r0
= gen_rtx_REG (Pmode
, 0);
2273 r16
= gen_rtx_REG (Pmode
, 16);
2274 tga
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
2275 dest
= gen_reg_rtx (Pmode
);
2276 seq
= GEN_INT (alpha_next_sequence_number
++);
2278 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
2279 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
2280 insn
= emit_call_insn (insn
);
2281 CONST_OR_PURE_CALL_P (insn
) = 1;
2282 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2284 insn
= get_insns ();
2287 emit_libcall_block (insn
, dest
, r0
, x
);
2290 case TLS_MODEL_LOCAL_DYNAMIC
:
2293 r0
= gen_rtx_REG (Pmode
, 0);
2294 r16
= gen_rtx_REG (Pmode
, 16);
2295 tga
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
2296 scratch
= gen_reg_rtx (Pmode
);
2297 seq
= GEN_INT (alpha_next_sequence_number
++);
2299 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
2300 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
2301 insn
= emit_call_insn (insn
);
2302 CONST_OR_PURE_CALL_P (insn
) = 1;
2303 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2305 insn
= get_insns ();
2308 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2309 UNSPEC_TLSLDM_CALL
);
2310 emit_libcall_block (insn
, scratch
, r0
, eqv
);
2312 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
2313 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2315 if (alpha_tls_size
== 64)
2317 dest
= gen_reg_rtx (Pmode
);
2318 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
2319 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
2322 if (alpha_tls_size
== 32)
2324 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2325 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
2326 scratch
= gen_reg_rtx (Pmode
);
2327 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
2329 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
2331 case TLS_MODEL_INITIAL_EXEC
:
2332 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2333 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2334 tp
= gen_reg_rtx (Pmode
);
2335 scratch
= gen_reg_rtx (Pmode
);
2336 dest
= gen_reg_rtx (Pmode
);
2338 emit_insn (gen_load_tp (tp
));
2339 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
2340 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
2343 case TLS_MODEL_LOCAL_EXEC
:
2344 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2345 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2346 tp
= gen_reg_rtx (Pmode
);
2348 emit_insn (gen_load_tp (tp
));
2349 if (alpha_tls_size
== 32)
2351 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2352 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
2353 tp
= gen_reg_rtx (Pmode
);
2354 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
2356 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
2359 if (local_symbolic_operand (x
, Pmode
))
2361 if (small_symbolic_operand (x
, Pmode
))
2365 if (!no_new_pseudos
)
2366 scratch
= gen_reg_rtx (Pmode
);
2367 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
2368 gen_rtx_HIGH (Pmode
, x
)));
2369 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
2378 HOST_WIDE_INT low
, high
;
2380 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
2382 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2386 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
2387 (no_new_pseudos
? scratch
: NULL_RTX
),
2388 1, OPTAB_LIB_WIDEN
);
2390 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
2391 (no_new_pseudos
? scratch
: NULL_RTX
),
2392 1, OPTAB_LIB_WIDEN
);
2394 return plus_constant (x
, low
);
2398 /* We do not allow indirect calls to be optimized into sibling calls, nor
2399 can we allow a call to a function with a different GP to be optimized
2403 alpha_function_ok_for_sibcall (decl
, exp
)
2405 tree exp ATTRIBUTE_UNUSED
;
2407 /* Can't do indirect tail calls, since we don't know if the target
2408 uses the same GP. */
2412 /* Otherwise, we can make a tail call if the target function shares
2414 return decl_has_samegp (decl
);
2417 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
2418 small symbolic operand until after reload. At which point we need
2419 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
2420 so that sched2 has the proper dependency information. */
2423 some_small_symbolic_operand (x
, mode
)
2425 enum machine_mode mode ATTRIBUTE_UNUSED
;
2427 return for_each_rtx (&x
, some_small_symbolic_operand_1
, NULL
);
2431 some_small_symbolic_operand_1 (px
, data
)
2433 void *data ATTRIBUTE_UNUSED
;
2437 /* Don't re-split. */
2438 if (GET_CODE (x
) == LO_SUM
)
2441 return small_symbolic_operand (x
, Pmode
) != 0;
2445 split_small_symbolic_operand (x
)
2449 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
2454 split_small_symbolic_operand_1 (px
, data
)
2456 void *data ATTRIBUTE_UNUSED
;
2460 /* Don't re-split. */
2461 if (GET_CODE (x
) == LO_SUM
)
2464 if (small_symbolic_operand (x
, Pmode
))
2466 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
2474 /* Try a machine-dependent way of reloading an illegitimate address
2475 operand. If we find one, push the reload and return the new rtx. */
2478 alpha_legitimize_reload_address (x
, mode
, opnum
, type
, ind_levels
)
2480 enum machine_mode mode ATTRIBUTE_UNUSED
;
2483 int ind_levels ATTRIBUTE_UNUSED
;
2485 /* We must recognize output that we have already generated ourselves. */
2486 if (GET_CODE (x
) == PLUS
2487 && GET_CODE (XEXP (x
, 0)) == PLUS
2488 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2489 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2490 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2492 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2493 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2498 /* We wish to handle large displacements off a base register by
2499 splitting the addend across an ldah and the mem insn. This
2500 cuts number of extra insns needed from 3 to 1. */
2501 if (GET_CODE (x
) == PLUS
2502 && GET_CODE (XEXP (x
, 0)) == REG
2503 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2504 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
2505 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2507 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2508 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
2510 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2512 /* Check for 32-bit overflow. */
2513 if (high
+ low
!= val
)
2516 /* Reload the high part into a base reg; leave the low part
2517 in the mem directly. */
2518 x
= gen_rtx_PLUS (GET_MODE (x
),
2519 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
2523 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2524 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2532 /* Compute a (partial) cost for rtx X. Return true if the complete
2533 cost has been computed, and false if subexpressions should be
2534 scanned. In either case, *TOTAL contains the cost result. */
2537 alpha_rtx_costs (x
, code
, outer_code
, total
)
2539 int code
, outer_code
;
2542 enum machine_mode mode
= GET_MODE (x
);
2543 bool float_mode_p
= FLOAT_MODE_P (mode
);
2547 /* If this is an 8-bit constant, return zero since it can be used
2548 nearly anywhere with no cost. If it is a valid operand for an
2549 ADD or AND, likewise return 0 if we know it will be used in that
2550 context. Otherwise, return 2 since it might be used there later.
2551 All other constants take at least two insns. */
2553 if (INTVAL (x
) >= 0 && INTVAL (x
) < 256)
2561 if (x
== CONST0_RTX (mode
))
2563 else if ((outer_code
== PLUS
&& add_operand (x
, VOIDmode
))
2564 || (outer_code
== AND
&& and_operand (x
, VOIDmode
)))
2566 else if (add_operand (x
, VOIDmode
) || and_operand (x
, VOIDmode
))
2569 *total
= COSTS_N_INSNS (2);
2575 if (TARGET_EXPLICIT_RELOCS
&& small_symbolic_operand (x
, VOIDmode
))
2576 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
2577 else if (TARGET_EXPLICIT_RELOCS
&& local_symbolic_operand (x
, VOIDmode
))
2578 *total
= COSTS_N_INSNS (1 + (outer_code
!= MEM
));
2579 else if (tls_symbolic_operand_type (x
))
2580 /* Estimate of cost for call_pal rduniq. */
2581 *total
= COSTS_N_INSNS (15);
2583 /* Otherwise we do a load from the GOT. */
2584 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2590 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2591 else if (GET_CODE (XEXP (x
, 0)) == MULT
2592 && const48_operand (XEXP (XEXP (x
, 0), 1), VOIDmode
))
2594 *total
= (rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
)
2595 + rtx_cost (XEXP (x
, 1), outer_code
) + 2);
2602 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_mult
;
2603 else if (mode
== DImode
)
2604 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_di
;
2606 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_mult_si
;
2610 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2611 && INTVAL (XEXP (x
, 1)) <= 3)
2613 *total
= COSTS_N_INSNS (1);
2620 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_shift
;
2625 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2627 *total
= alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2635 *total
= COSTS_N_INSNS (70); /* ??? */
2636 else if (mode
== SFmode
)
2637 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_sf
;
2639 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_div_df
;
2643 *total
= COSTS_N_INSNS (alpha_memory_latency
);
2649 *total
= COSTS_N_INSNS (1);
2657 *total
= COSTS_N_INSNS (1) + alpha_rtx_cost_data
[alpha_cpu
].int_cmov
;
2663 case UNSIGNED_FLOAT
:
2667 case FLOAT_TRUNCATE
:
2668 *total
= alpha_rtx_cost_data
[alpha_cpu
].fp_add
;
2676 /* REF is an alignable memory location. Place an aligned SImode
2677 reference into *PALIGNED_MEM and the number of bits to shift into
2678 *PBITNUM. SCRATCH is a free register for use in reloading out
2679 of range stack slots. */
2682 get_aligned_mem (ref
, paligned_mem
, pbitnum
)
2684 rtx
*paligned_mem
, *pbitnum
;
2687 HOST_WIDE_INT offset
= 0;
2689 if (GET_CODE (ref
) != MEM
)
2692 if (reload_in_progress
2693 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2695 base
= find_replacement (&XEXP (ref
, 0));
2697 if (! memory_address_p (GET_MODE (ref
), base
))
2702 base
= XEXP (ref
, 0);
2705 if (GET_CODE (base
) == PLUS
)
2706 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2709 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
2711 if (WORDS_BIG_ENDIAN
)
2712 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
2713 + (offset
& 3) * 8));
2715 *pbitnum
= GEN_INT ((offset
& 3) * 8);
2718 /* Similar, but just get the address. Handle the two reload cases.
2719 Add EXTRA_OFFSET to the address we return. */
2722 get_unaligned_address (ref
, extra_offset
)
2727 HOST_WIDE_INT offset
= 0;
2729 if (GET_CODE (ref
) != MEM
)
2732 if (reload_in_progress
2733 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2735 base
= find_replacement (&XEXP (ref
, 0));
2737 if (! memory_address_p (GET_MODE (ref
), base
))
2742 base
= XEXP (ref
, 0);
2745 if (GET_CODE (base
) == PLUS
)
2746 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2748 return plus_constant (base
, offset
+ extra_offset
);
2751 /* On the Alpha, all (non-symbolic) constants except zero go into
2752 a floating-point register via memory. Note that we cannot
2753 return anything that is not a subset of CLASS, and that some
2754 symbolic constants cannot be dropped to memory. */
2757 alpha_preferred_reload_class(x
, class)
2759 enum reg_class
class;
2761 /* Zero is present in any register class. */
2762 if (x
== CONST0_RTX (GET_MODE (x
)))
2765 /* These sorts of constants we can easily drop to memory. */
2766 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2768 if (class == FLOAT_REGS
)
2770 if (class == ALL_REGS
)
2771 return GENERAL_REGS
;
2775 /* All other kinds of constants should not (and in the case of HIGH
2776 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2777 secondary reload. */
2779 return (class == ALL_REGS
? GENERAL_REGS
: class);
2784 /* Loading and storing HImode or QImode values to and from memory
2785 usually requires a scratch register. The exceptions are loading
2786 QImode and HImode from an aligned address to a general register
2787 unless byte instructions are permitted.
2789 We also cannot load an unaligned address or a paradoxical SUBREG
2790 into an FP register.
2792 We also cannot do integral arithmetic into FP regs, as might result
2793 from register elimination into a DImode fp register. */
2796 secondary_reload_class (class, mode
, x
, in
)
2797 enum reg_class
class;
2798 enum machine_mode mode
;
2802 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
2804 if (GET_CODE (x
) == MEM
2805 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
2806 || (GET_CODE (x
) == SUBREG
2807 && (GET_CODE (SUBREG_REG (x
)) == MEM
2808 || (GET_CODE (SUBREG_REG (x
)) == REG
2809 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
2811 if (!in
|| !aligned_memory_operand(x
, mode
))
2812 return GENERAL_REGS
;
2816 if (class == FLOAT_REGS
)
2818 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
2819 return GENERAL_REGS
;
2821 if (GET_CODE (x
) == SUBREG
2822 && (GET_MODE_SIZE (GET_MODE (x
))
2823 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2824 return GENERAL_REGS
;
2826 if (in
&& INTEGRAL_MODE_P (mode
)
2827 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
2828 return GENERAL_REGS
;
2834 /* Subfunction of the following function. Update the flags of any MEM
2835 found in part of X. */
2838 alpha_set_memflags_1 (x
, in_struct_p
, volatile_p
, unchanging_p
)
2840 int in_struct_p
, volatile_p
, unchanging_p
;
2844 switch (GET_CODE (x
))
2850 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2851 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
2856 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
2861 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
2863 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
2868 MEM_IN_STRUCT_P (x
) = in_struct_p
;
2869 MEM_VOLATILE_P (x
) = volatile_p
;
2870 RTX_UNCHANGING_P (x
) = unchanging_p
;
2871 /* Sadly, we cannot use alias sets because the extra aliasing
2872 produced by the AND interferes. Given that two-byte quantities
2873 are the only thing we would be able to differentiate anyway,
2874 there does not seem to be any point in convoluting the early
2875 out of the alias check. */
2883 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2884 generated to perform a memory operation, look for any MEMs in either
2885 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2886 volatile flags from REF into each of the MEMs found. If REF is not
2887 a MEM, don't do anything. */
2890 alpha_set_memflags (insn
, ref
)
2894 int in_struct_p
, volatile_p
, unchanging_p
;
2896 if (GET_CODE (ref
) != MEM
)
2899 in_struct_p
= MEM_IN_STRUCT_P (ref
);
2900 volatile_p
= MEM_VOLATILE_P (ref
);
2901 unchanging_p
= RTX_UNCHANGING_P (ref
);
2903 /* This is only called from alpha.md, after having had something
2904 generated from one of the insn patterns. So if everything is
2905 zero, the pattern is already up-to-date. */
2906 if (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
)
2909 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
2912 /* Try to output insns to set TARGET equal to the constant C if it can be
2913 done in less than N insns. Do all computations in MODE. Returns the place
2914 where the output has been placed if it can be done and the insns have been
2915 emitted. If it would take more than N insns, zero is returned and no
2916 insns and emitted. */
2919 alpha_emit_set_const (target
, mode
, c
, n
)
2921 enum machine_mode mode
;
2926 rtx orig_target
= target
;
2929 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2930 can't load this constant in one insn, do this in DImode. */
2931 if (no_new_pseudos
&& mode
== SImode
2932 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
2933 && (result
= alpha_emit_set_const_1 (target
, mode
, c
, 1)) == 0)
2935 target
= gen_lowpart (DImode
, target
);
2939 /* Try 1 insn, then 2, then up to N. */
2940 for (i
= 1; i
<= n
; i
++)
2942 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
);
2945 rtx insn
= get_last_insn ();
2946 rtx set
= single_set (insn
);
2947 if (! CONSTANT_P (SET_SRC (set
)))
2948 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
2953 /* Allow for the case where we changed the mode of TARGET. */
2954 if (result
== target
)
2955 result
= orig_target
;
2960 /* Internal routine for the above to check for N or below insns. */
2963 alpha_emit_set_const_1 (target
, mode
, c
, n
)
2965 enum machine_mode mode
;
2971 /* Use a pseudo if highly optimizing and still generating RTL. */
2973 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
2976 /* If this is a sign-extended 32-bit constant, we can do this in at most
2977 three insns, so do it if we have enough insns left. We always have
2978 a sign-extended 32-bit constant when compiling on a narrow machine. */
2980 if (HOST_BITS_PER_WIDE_INT
!= 64
2981 || c
>> 31 == -1 || c
>> 31 == 0)
2983 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
2984 HOST_WIDE_INT tmp1
= c
- low
;
2985 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
2986 HOST_WIDE_INT extra
= 0;
2988 /* If HIGH will be interpreted as negative but the constant is
2989 positive, we must adjust it to do two ldha insns. */
2991 if ((high
& 0x8000) != 0 && c
>= 0)
2995 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
2998 if (c
== low
|| (low
== 0 && extra
== 0))
3000 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
3001 but that meant that we can't handle INT_MIN on 32-bit machines
3002 (like NT/Alpha), because we recurse indefinitely through
3003 emit_move_insn to gen_movdi. So instead, since we know exactly
3004 what we want, create it explicitly. */
3007 target
= gen_reg_rtx (mode
);
3008 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
3011 else if (n
>= 2 + (extra
!= 0))
3013 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16), subtarget
, mode
);
3015 /* As of 2002-02-23, addsi3 is only available when not optimizing.
3016 This means that if we go through expand_binop, we'll try to
3017 generate extensions, etc, which will require new pseudos, which
3018 will fail during some split phases. The SImode add patterns
3019 still exist, but are not named. So build the insns by hand. */
3024 subtarget
= gen_reg_rtx (mode
);
3025 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
3026 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
3032 target
= gen_reg_rtx (mode
);
3033 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
3034 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
3040 /* If we couldn't do it that way, try some other methods. But if we have
3041 no instructions left, don't bother. Likewise, if this is SImode and
3042 we can't make pseudos, we can't do anything since the expand_binop
3043 and expand_unop calls will widen and try to make pseudos. */
3045 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
3048 /* Next, see if we can load a related constant and then shift and possibly
3049 negate it to get the constant we want. Try this once each increasing
3050 numbers of insns. */
3052 for (i
= 1; i
< n
; i
++)
3054 /* First, see if minus some low bits, we've an easy load of
3057 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
3059 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
3060 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
3061 target
, 0, OPTAB_WIDEN
);
3063 /* Next try complementing. */
3064 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
3065 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
3067 /* Next try to form a constant and do a left shift. We can do this
3068 if some low-order bits are zero; the exact_log2 call below tells
3069 us that information. The bits we are shifting out could be any
3070 value, but here we'll just try the 0- and sign-extended forms of
3071 the constant. To try to increase the chance of having the same
3072 constant in more than one insn, start at the highest number of
3073 bits to shift, but try all possibilities in case a ZAPNOT will
3076 if ((bits
= exact_log2 (c
& - c
)) > 0)
3077 for (; bits
> 0; bits
--)
3078 if ((temp
= (alpha_emit_set_const
3079 (subtarget
, mode
, c
>> bits
, i
))) != 0
3080 || ((temp
= (alpha_emit_set_const
3082 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
3084 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
3085 target
, 0, OPTAB_WIDEN
);
3087 /* Now try high-order zero bits. Here we try the shifted-in bits as
3088 all zero and all ones. Be careful to avoid shifting outside the
3089 mode and to avoid shifting outside the host wide int size. */
3090 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
3091 confuse the recursive call and set all of the high 32 bits. */
3093 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
3094 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
3095 for (; bits
> 0; bits
--)
3096 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
3098 || ((temp
= (alpha_emit_set_const
3100 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
3103 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
3104 target
, 1, OPTAB_WIDEN
);
3106 /* Now try high-order 1 bits. We get that with a sign-extension.
3107 But one bit isn't enough here. Be careful to avoid shifting outside
3108 the mode and to avoid shifting outside the host wide int size. */
3110 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
3111 - floor_log2 (~ c
) - 2)) > 0)
3112 for (; bits
> 0; bits
--)
3113 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
3115 || ((temp
= (alpha_emit_set_const
3117 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
3120 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
3121 target
, 0, OPTAB_WIDEN
);
3124 #if HOST_BITS_PER_WIDE_INT == 64
3125 /* Finally, see if can load a value into the target that is the same as the
3126 constant except that all bytes that are 0 are changed to be 0xff. If we
3127 can, then we can do a ZAPNOT to obtain the desired constant. */
3130 for (i
= 0; i
< 64; i
+= 8)
3131 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
3132 new |= (HOST_WIDE_INT
) 0xff << i
;
3134 /* We are only called for SImode and DImode. If this is SImode, ensure that
3135 we are sign extended to a full word. */
3138 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
3140 if (new != c
&& new != -1
3141 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
3142 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
3143 target
, 0, OPTAB_WIDEN
);
3149 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
3150 fall back to a straight forward decomposition. We do this to avoid
3151 exponential run times encountered when looking for longer sequences
3152 with alpha_emit_set_const. */
3155 alpha_emit_set_long_const (target
, c1
, c2
)
3157 HOST_WIDE_INT c1
, c2
;
3159 HOST_WIDE_INT d1
, d2
, d3
, d4
;
3161 /* Decompose the entire word */
3162 #if HOST_BITS_PER_WIDE_INT >= 64
3163 if (c2
!= -(c1
< 0))
3165 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
3167 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
3168 c1
= (c1
- d2
) >> 32;
3169 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
3171 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
3175 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
3177 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
3181 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
3183 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
3188 /* Construct the high word */
3191 emit_move_insn (target
, GEN_INT (d4
));
3193 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
3196 emit_move_insn (target
, GEN_INT (d3
));
3198 /* Shift it into place */
3199 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
3201 /* Add in the low bits. */
3203 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
3205 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
3210 /* Expand a move instruction; return true if all work is done.
3211 We don't handle non-bwx subword loads here. */
3214 alpha_expand_mov (mode
, operands
)
3215 enum machine_mode mode
;
3218 /* If the output is not a register, the input must be. */
3219 if (GET_CODE (operands
[0]) == MEM
3220 && ! reg_or_0_operand (operands
[1], mode
))
3221 operands
[1] = force_reg (mode
, operands
[1]);
3223 /* Allow legitimize_address to perform some simplifications. */
3224 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
3228 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
3229 compiled at the end of compilation. In the meantime, someone can
3230 re-encode-section-info on some symbol changing it e.g. from global
3231 to local-not-small. If this happens, we'd have emitted a plain
3232 load rather than a high+losum load and not recognize the insn.
3234 So if rtl inlining is in effect, we delay the global/not-global
3235 decision until rest_of_compilation by wrapping it in an
3237 if (TARGET_EXPLICIT_RELOCS
&& flag_inline_functions
3238 && rtx_equal_function_value_matters
3239 && global_symbolic_operand (operands
[1], mode
))
3241 emit_insn (gen_movdi_er_maybe_g (operands
[0], operands
[1]));
3245 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
3248 if (tmp
== operands
[0])
3255 /* Early out for non-constants and valid constants. */
3256 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
3259 /* Split large integers. */
3260 if (GET_CODE (operands
[1]) == CONST_INT
3261 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
3263 HOST_WIDE_INT i0
, i1
;
3264 rtx temp
= NULL_RTX
;
3266 if (GET_CODE (operands
[1]) == CONST_INT
)
3268 i0
= INTVAL (operands
[1]);
3271 else if (HOST_BITS_PER_WIDE_INT
>= 64)
3273 i0
= CONST_DOUBLE_LOW (operands
[1]);
3278 i0
= CONST_DOUBLE_LOW (operands
[1]);
3279 i1
= CONST_DOUBLE_HIGH (operands
[1]);
3282 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
3283 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
3285 if (!temp
&& TARGET_BUILD_CONSTANTS
)
3286 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
3290 if (rtx_equal_p (operands
[0], temp
))
3297 /* Otherwise we've nothing left but to drop the thing to memory. */
3298 operands
[1] = force_const_mem (mode
, operands
[1]);
3299 if (reload_in_progress
)
3301 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
3302 operands
[1] = copy_rtx (operands
[1]);
3303 XEXP (operands
[1], 0) = operands
[0];
3306 operands
[1] = validize_mem (operands
[1]);
3310 /* Expand a non-bwx QImode or HImode move instruction;
3311 return true if all work is done. */
3314 alpha_expand_mov_nobwx (mode
, operands
)
3315 enum machine_mode mode
;
3318 /* If the output is not a register, the input must be. */
3319 if (GET_CODE (operands
[0]) == MEM
)
3320 operands
[1] = force_reg (mode
, operands
[1]);
3322 /* Handle four memory cases, unaligned and aligned for either the input
3323 or the output. The only case where we can be called during reload is
3324 for aligned loads; all other cases require temporaries. */
3326 if (GET_CODE (operands
[1]) == MEM
3327 || (GET_CODE (operands
[1]) == SUBREG
3328 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
3329 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
3330 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
3331 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
3332 && GET_CODE (SUBREG_REG (operands
[1])) == REG
3333 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
3335 if (aligned_memory_operand (operands
[1], mode
))
3337 if (reload_in_progress
)
3339 emit_insn ((mode
== QImode
3340 ? gen_reload_inqi_help
3341 : gen_reload_inhi_help
)
3342 (operands
[0], operands
[1],
3343 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
3347 rtx aligned_mem
, bitnum
;
3348 rtx scratch
= gen_reg_rtx (SImode
);
3350 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
3352 emit_insn ((mode
== QImode
3353 ? gen_aligned_loadqi
3354 : gen_aligned_loadhi
)
3355 (operands
[0], aligned_mem
, bitnum
, scratch
));
3360 /* Don't pass these as parameters since that makes the generated
3361 code depend on parameter evaluation order which will cause
3362 bootstrap failures. */
3364 rtx temp1
= gen_reg_rtx (DImode
);
3365 rtx temp2
= gen_reg_rtx (DImode
);
3366 rtx seq
= ((mode
== QImode
3367 ? gen_unaligned_loadqi
3368 : gen_unaligned_loadhi
)
3369 (operands
[0], get_unaligned_address (operands
[1], 0),
3372 alpha_set_memflags (seq
, operands
[1]);
3378 if (GET_CODE (operands
[0]) == MEM
3379 || (GET_CODE (operands
[0]) == SUBREG
3380 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
3381 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
3382 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
3383 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
3384 && GET_CODE (SUBREG_REG (operands
[0])) == REG
3385 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
3387 if (aligned_memory_operand (operands
[0], mode
))
3389 rtx aligned_mem
, bitnum
;
3390 rtx temp1
= gen_reg_rtx (SImode
);
3391 rtx temp2
= gen_reg_rtx (SImode
);
3393 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
3395 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
3400 rtx temp1
= gen_reg_rtx (DImode
);
3401 rtx temp2
= gen_reg_rtx (DImode
);
3402 rtx temp3
= gen_reg_rtx (DImode
);
3403 rtx seq
= ((mode
== QImode
3404 ? gen_unaligned_storeqi
3405 : gen_unaligned_storehi
)
3406 (get_unaligned_address (operands
[0], 0),
3407 operands
[1], temp1
, temp2
, temp3
));
3409 alpha_set_memflags (seq
, operands
[0]);
3418 /* Generate an unsigned DImode to FP conversion. This is the same code
3419 optabs would emit if we didn't have TFmode patterns.
3421 For SFmode, this is the only construction I've found that can pass
3422 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
3423 intermediates will work, because you'll get intermediate rounding
3424 that ruins the end result. Some of this could be fixed by turning
3425 on round-to-positive-infinity, but that requires diddling the fpsr,
3426 which kills performance. I tried turning this around and converting
3427 to a negative number, so that I could turn on /m, but either I did
3428 it wrong or there's something else cause I wound up with the exact
3429 same single-bit error. There is a branch-less form of this same code:
3440 fcmoveq $f10,$f11,$f0
3442 I'm not using it because it's the same number of instructions as
3443 this branch-full form, and it has more serialized long latency
3444 instructions on the critical path.
3446 For DFmode, we can avoid rounding errors by breaking up the word
3447 into two pieces, converting them separately, and adding them back:
3449 LC0: .long 0,0x5f800000
3454 cpyse $f11,$f31,$f10
3455 cpyse $f31,$f11,$f11
3463 This doesn't seem to be a clear-cut win over the optabs form.
3464 It probably all depends on the distribution of numbers being
3465 converted -- in the optabs form, all but high-bit-set has a
3466 much lower minimum execution time. */
3469 alpha_emit_floatuns (operands
)
3472 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
3473 enum machine_mode mode
;
3476 in
= force_reg (DImode
, operands
[1]);
3477 mode
= GET_MODE (out
);
3478 neglab
= gen_label_rtx ();
3479 donelab
= gen_label_rtx ();
3480 i0
= gen_reg_rtx (DImode
);
3481 i1
= gen_reg_rtx (DImode
);
3482 f0
= gen_reg_rtx (mode
);
3484 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
3486 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
3487 emit_jump_insn (gen_jump (donelab
));
3490 emit_label (neglab
);
3492 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
3493 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
3494 emit_insn (gen_iordi3 (i0
, i0
, i1
));
3495 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
3496 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
3498 emit_label (donelab
);
3501 /* Generate the comparison for a conditional branch. */
3504 alpha_emit_conditional_branch (code
)
3507 enum rtx_code cmp_code
, branch_code
;
3508 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
3509 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3512 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
3514 if (! TARGET_HAS_XFLOATING_LIBS
)
3517 /* X_floating library comparison functions return
3521 Convert the compare against the raw return value. */
3543 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3545 alpha_compare
.fp_p
= 0;
3548 /* The general case: fold the comparison code to the types of compares
3549 that we have, choosing the branch as necessary. */
3552 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3554 /* We have these compares: */
3555 cmp_code
= code
, branch_code
= NE
;
3560 /* These must be reversed. */
3561 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
3564 case GE
: case GT
: case GEU
: case GTU
:
3565 /* For FP, we swap them, for INT, we reverse them. */
3566 if (alpha_compare
.fp_p
)
3568 cmp_code
= swap_condition (code
);
3570 tem
= op0
, op0
= op1
, op1
= tem
;
3574 cmp_code
= reverse_condition (code
);
3583 if (alpha_compare
.fp_p
)
3586 if (flag_unsafe_math_optimizations
)
3588 /* When we are not as concerned about non-finite values, and we
3589 are comparing against zero, we can branch directly. */
3590 if (op1
== CONST0_RTX (DFmode
))
3591 cmp_code
= NIL
, branch_code
= code
;
3592 else if (op0
== CONST0_RTX (DFmode
))
3594 /* Undo the swap we probably did just above. */
3595 tem
= op0
, op0
= op1
, op1
= tem
;
3596 branch_code
= swap_condition (cmp_code
);
3602 /* ??? We mark the branch mode to be CCmode to prevent the
3603 compare and branch from being combined, since the compare
3604 insn follows IEEE rules that the branch does not. */
3605 branch_mode
= CCmode
;
3612 /* The following optimizations are only for signed compares. */
3613 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
3615 /* Whee. Compare and branch against 0 directly. */
3616 if (op1
== const0_rtx
)
3617 cmp_code
= NIL
, branch_code
= code
;
3619 /* We want to use cmpcc/bcc when we can, since there is a zero delay
3620 bypass between logicals and br/cmov on EV5. But we don't want to
3621 force valid immediate constants into registers needlessly. */
3622 else if (GET_CODE (op1
) == CONST_INT
)
3624 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
3626 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
3627 && (CONST_OK_FOR_LETTER_P (n
, 'K')
3628 || CONST_OK_FOR_LETTER_P (n
, 'L')))
3630 cmp_code
= PLUS
, branch_code
= code
;
3636 if (!reg_or_0_operand (op0
, DImode
))
3637 op0
= force_reg (DImode
, op0
);
3638 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
3639 op1
= force_reg (DImode
, op1
);
3642 /* Emit an initial compare instruction, if necessary. */
3644 if (cmp_code
!= NIL
)
3646 tem
= gen_reg_rtx (cmp_mode
);
3647 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
3650 /* Zero the operands. */
3651 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3653 /* Return the branch comparison. */
3654 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
3657 /* Certain simplifications can be done to make invalid setcc operations
3658 valid. Return the final comparison, or NULL if we can't work. */
3661 alpha_emit_setcc (code
)
3664 enum rtx_code cmp_code
;
3665 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3666 int fp_p
= alpha_compare
.fp_p
;
3669 /* Zero the operands. */
3670 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3672 if (fp_p
&& GET_MODE (op0
) == TFmode
)
3674 if (! TARGET_HAS_XFLOATING_LIBS
)
3677 /* X_floating library comparison functions return
3681 Convert the compare against the raw return value. */
3683 if (code
== UNORDERED
|| code
== ORDERED
)
3688 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3692 if (code
== UNORDERED
)
3694 else if (code
== ORDERED
)
3700 if (fp_p
&& !TARGET_FIX
)
3703 /* The general case: fold the comparison code to the types of compares
3704 that we have, choosing the branch as necessary. */
3709 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3711 /* We have these compares. */
3713 cmp_code
= code
, code
= NE
;
3717 if (!fp_p
&& op1
== const0_rtx
)
3722 cmp_code
= reverse_condition (code
);
3726 case GE
: case GT
: case GEU
: case GTU
:
3727 /* These normally need swapping, but for integer zero we have
3728 special patterns that recognize swapped operands. */
3729 if (!fp_p
&& op1
== const0_rtx
)
3731 code
= swap_condition (code
);
3733 cmp_code
= code
, code
= NE
;
3734 tmp
= op0
, op0
= op1
, op1
= tmp
;
3743 if (!register_operand (op0
, DImode
))
3744 op0
= force_reg (DImode
, op0
);
3745 if (!reg_or_8bit_operand (op1
, DImode
))
3746 op1
= force_reg (DImode
, op1
);
3749 /* Emit an initial compare instruction, if necessary. */
3750 if (cmp_code
!= NIL
)
3752 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
3754 tmp
= gen_reg_rtx (mode
);
3755 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
3756 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
3758 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
3762 /* Return the setcc comparison. */
3763 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
3767 /* Rewrite a comparison against zero CMP of the form
3768 (CODE (cc0) (const_int 0)) so it can be written validly in
3769 a conditional move (if_then_else CMP ...).
3770 If both of the operands that set cc0 are nonzero we must emit
3771 an insn to perform the compare (it can't be done within
3772 the conditional move). */
3774 alpha_emit_conditional_move (cmp
, mode
)
3776 enum machine_mode mode
;
3778 enum rtx_code code
= GET_CODE (cmp
);
3779 enum rtx_code cmov_code
= NE
;
3780 rtx op0
= alpha_compare
.op0
;
3781 rtx op1
= alpha_compare
.op1
;
3782 int fp_p
= alpha_compare
.fp_p
;
3783 enum machine_mode cmp_mode
3784 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
3785 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
3786 enum machine_mode cmov_mode
= VOIDmode
;
3787 int local_fast_math
= flag_unsafe_math_optimizations
;
3790 /* Zero the operands. */
3791 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3793 if (fp_p
!= FLOAT_MODE_P (mode
))
3795 enum rtx_code cmp_code
;
3800 /* If we have fp<->int register move instructions, do a cmov by
3801 performing the comparison in fp registers, and move the
3802 zero/nonzero value to integer registers, where we can then
3803 use a normal cmov, or vice-versa. */
3807 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3808 /* We have these compares. */
3809 cmp_code
= code
, code
= NE
;
3813 /* This must be reversed. */
3814 cmp_code
= EQ
, code
= EQ
;
3817 case GE
: case GT
: case GEU
: case GTU
:
3818 /* These normally need swapping, but for integer zero we have
3819 special patterns that recognize swapped operands. */
3820 if (!fp_p
&& op1
== const0_rtx
)
3821 cmp_code
= code
, code
= NE
;
3824 cmp_code
= swap_condition (code
);
3826 tem
= op0
, op0
= op1
, op1
= tem
;
3834 tem
= gen_reg_rtx (cmp_op_mode
);
3835 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
3836 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
3839 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
3840 op0
= gen_lowpart (cmp_op_mode
, tem
);
3841 op1
= CONST0_RTX (cmp_op_mode
);
3843 local_fast_math
= 1;
3846 /* We may be able to use a conditional move directly.
3847 This avoids emitting spurious compares. */
3848 if (signed_comparison_operator (cmp
, VOIDmode
)
3849 && (!fp_p
|| local_fast_math
)
3850 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
3851 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3853 /* We can't put the comparison inside the conditional move;
3854 emit a compare instruction and put that inside the
3855 conditional move. Make sure we emit only comparisons we have;
3856 swap or reverse as necessary. */
3863 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3864 /* We have these compares: */
3868 /* This must be reversed. */
3869 code
= reverse_condition (code
);
3873 case GE
: case GT
: case GEU
: case GTU
:
3874 /* These must be swapped. */
3875 if (op1
!= CONST0_RTX (cmp_mode
))
3877 code
= swap_condition (code
);
3878 tem
= op0
, op0
= op1
, op1
= tem
;
3888 if (!reg_or_0_operand (op0
, DImode
))
3889 op0
= force_reg (DImode
, op0
);
3890 if (!reg_or_8bit_operand (op1
, DImode
))
3891 op1
= force_reg (DImode
, op1
);
3894 /* ??? We mark the branch mode to be CCmode to prevent the compare
3895 and cmov from being combined, since the compare insn follows IEEE
3896 rules that the cmov does not. */
3897 if (fp_p
&& !local_fast_math
)
3900 tem
= gen_reg_rtx (cmp_op_mode
);
3901 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
3902 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
3905 /* Simplify a conditional move of two constants into a setcc with
3906 arithmetic. This is done with a splitter since combine would
3907 just undo the work if done during code generation. It also catches
3908 cases we wouldn't have before cse. */
3911 alpha_split_conditional_move (code
, dest
, cond
, t_rtx
, f_rtx
)
3913 rtx dest
, cond
, t_rtx
, f_rtx
;
3915 HOST_WIDE_INT t
, f
, diff
;
3916 enum machine_mode mode
;
3917 rtx target
, subtarget
, tmp
;
3919 mode
= GET_MODE (dest
);
3924 if (((code
== NE
|| code
== EQ
) && diff
< 0)
3925 || (code
== GE
|| code
== GT
))
3927 code
= reverse_condition (code
);
3928 diff
= t
, t
= f
, f
= diff
;
3932 subtarget
= target
= dest
;
3935 target
= gen_lowpart (DImode
, dest
);
3936 if (! no_new_pseudos
)
3937 subtarget
= gen_reg_rtx (DImode
);
3941 /* Below, we must be careful to use copy_rtx on target and subtarget
3942 in intermediate insns, as they may be a subreg rtx, which may not
3945 if (f
== 0 && exact_log2 (diff
) > 0
3946 /* On EV6, we've got enough shifters to make non-arithmatic shifts
3947 viable over a longer latency cmove. On EV5, the E0 slot is a
3948 scarce resource, and on EV4 shift has the same latency as a cmove. */
3949 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
3951 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3952 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3954 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
3955 GEN_INT (exact_log2 (t
)));
3956 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3958 else if (f
== 0 && t
== -1)
3960 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3961 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3963 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
3965 else if (diff
== 1 || diff
== 4 || diff
== 8)
3969 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3970 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3973 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
3976 add_op
= GEN_INT (f
);
3977 if (sext_add_operand (add_op
, mode
))
3979 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
3981 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
3982 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3994 /* Look up the function X_floating library function name for the
3998 alpha_lookup_xfloating_lib_func (code
)
4003 const enum rtx_code code
;
4004 const char *const func
;
4007 static const struct xfloating_op vms_xfloating_ops
[] =
4009 { PLUS
, "OTS$ADD_X" },
4010 { MINUS
, "OTS$SUB_X" },
4011 { MULT
, "OTS$MUL_X" },
4012 { DIV
, "OTS$DIV_X" },
4013 { EQ
, "OTS$EQL_X" },
4014 { NE
, "OTS$NEQ_X" },
4015 { LT
, "OTS$LSS_X" },
4016 { LE
, "OTS$LEQ_X" },
4017 { GT
, "OTS$GTR_X" },
4018 { GE
, "OTS$GEQ_X" },
4019 { FIX
, "OTS$CVTXQ" },
4020 { FLOAT
, "OTS$CVTQX" },
4021 { UNSIGNED_FLOAT
, "OTS$CVTQUX" },
4022 { FLOAT_EXTEND
, "OTS$CVT_FLOAT_T_X" },
4023 { FLOAT_TRUNCATE
, "OTS$CVT_FLOAT_X_T" },
4026 static const struct xfloating_op osf_xfloating_ops
[] =
4028 { PLUS
, "_OtsAddX" },
4029 { MINUS
, "_OtsSubX" },
4030 { MULT
, "_OtsMulX" },
4031 { DIV
, "_OtsDivX" },
4038 { FIX
, "_OtsCvtXQ" },
4039 { FLOAT
, "_OtsCvtQX" },
4040 { UNSIGNED_FLOAT
, "_OtsCvtQUX" },
4041 { FLOAT_EXTEND
, "_OtsConvertFloatTX" },
4042 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT" },
4045 const struct xfloating_op
*ops
;
4046 const long n
= ARRAY_SIZE (osf_xfloating_ops
);
4049 /* How irritating. Nothing to key off for the table. Hardcode
4050 knowledge of the G_floating routines. */
4051 if (TARGET_FLOAT_VAX
)
4053 if (TARGET_ABI_OPEN_VMS
)
4055 if (code
== FLOAT_EXTEND
)
4056 return "OTS$CVT_FLOAT_G_X";
4057 if (code
== FLOAT_TRUNCATE
)
4058 return "OTS$CVT_FLOAT_X_G";
4062 if (code
== FLOAT_EXTEND
)
4063 return "_OtsConvertFloatGX";
4064 if (code
== FLOAT_TRUNCATE
)
4065 return "_OtsConvertFloatXG";
4069 if (TARGET_ABI_OPEN_VMS
)
4070 ops
= vms_xfloating_ops
;
4072 ops
= osf_xfloating_ops
;
4074 for (i
= 0; i
< n
; ++i
)
4075 if (ops
[i
].code
== code
)
4081 /* Most X_floating operations take the rounding mode as an argument.
4082 Compute that here. */
4085 alpha_compute_xfloating_mode_arg (code
, round
)
4087 enum alpha_fp_rounding_mode round
;
4093 case ALPHA_FPRM_NORM
:
4096 case ALPHA_FPRM_MINF
:
4099 case ALPHA_FPRM_CHOP
:
4102 case ALPHA_FPRM_DYN
:
4108 /* XXX For reference, round to +inf is mode = 3. */
4111 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
4117 /* Emit an X_floating library function call.
4119 Note that these functions do not follow normal calling conventions:
4120 TFmode arguments are passed in two integer registers (as opposed to
4121 indirect); TFmode return values appear in R16+R17.
4123 FUNC is the function name to call.
4124 TARGET is where the output belongs.
4125 OPERANDS are the inputs.
4126 NOPERANDS is the count of inputs.
4127 EQUIV is the expression equivalent for the function.
4131 alpha_emit_xfloating_libcall (func
, target
, operands
, noperands
, equiv
)
4138 rtx usage
= NULL_RTX
, tmp
, reg
;
4143 for (i
= 0; i
< noperands
; ++i
)
4145 switch (GET_MODE (operands
[i
]))
4148 reg
= gen_rtx_REG (TFmode
, regno
);
4153 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
4158 if (GET_CODE (operands
[i
]) != CONST_INT
)
4162 reg
= gen_rtx_REG (DImode
, regno
);
4170 emit_move_insn (reg
, operands
[i
]);
4171 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
4174 switch (GET_MODE (target
))
4177 reg
= gen_rtx_REG (TFmode
, 16);
4180 reg
= gen_rtx_REG (DFmode
, 32);
4183 reg
= gen_rtx_REG (DImode
, 0);
4189 tmp
= gen_rtx_MEM (QImode
, gen_rtx_SYMBOL_REF (Pmode
, (char *) func
));
4190 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
4191 const0_rtx
, const0_rtx
));
4192 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
4197 emit_libcall_block (tmp
, target
, reg
, equiv
);
4200 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
4203 alpha_emit_xfloating_arith (code
, operands
)
4209 rtx out_operands
[3];
4211 func
= alpha_lookup_xfloating_lib_func (code
);
4212 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
4214 out_operands
[0] = operands
[1];
4215 out_operands
[1] = operands
[2];
4216 out_operands
[2] = GEN_INT (mode
);
4217 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
4218 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
4222 /* Emit an X_floating library function call for a comparison. */
4225 alpha_emit_xfloating_compare (code
, op0
, op1
)
4230 rtx out
, operands
[2];
4232 func
= alpha_lookup_xfloating_lib_func (code
);
4236 out
= gen_reg_rtx (DImode
);
4238 /* ??? Strange mode for equiv because what's actually returned
4239 is -1,0,1, not a proper boolean value. */
4240 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
4241 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
4246 /* Emit an X_floating library function call for a conversion. */
4249 alpha_emit_xfloating_cvt (code
, operands
)
4253 int noperands
= 1, mode
;
4254 rtx out_operands
[2];
4257 func
= alpha_lookup_xfloating_lib_func (code
);
4259 out_operands
[0] = operands
[1];
4264 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
4265 out_operands
[1] = GEN_INT (mode
);
4268 case FLOAT_TRUNCATE
:
4269 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
4270 out_operands
[1] = GEN_INT (mode
);
4277 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
4278 gen_rtx_fmt_e (code
, GET_MODE (operands
[0]),
4282 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
4283 OP[0] into OP[0,1]. Naturally, output operand ordering is
4287 alpha_split_tfmode_pair (operands
)
4290 if (GET_CODE (operands
[1]) == REG
)
4292 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
4293 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
4295 else if (GET_CODE (operands
[1]) == MEM
)
4297 operands
[3] = adjust_address (operands
[1], DImode
, 8);
4298 operands
[2] = adjust_address (operands
[1], DImode
, 0);
4300 else if (operands
[1] == CONST0_RTX (TFmode
))
4301 operands
[2] = operands
[3] = const0_rtx
;
4305 if (GET_CODE (operands
[0]) == REG
)
4307 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
4308 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
4310 else if (GET_CODE (operands
[0]) == MEM
)
4312 operands
[1] = adjust_address (operands
[0], DImode
, 8);
4313 operands
[0] = adjust_address (operands
[0], DImode
, 0);
4319 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
4320 op2 is a register containing the sign bit, operation is the
4321 logical operation to be performed. */
4324 alpha_split_tfmode_frobsign (operands
, operation
)
4326 rtx (*operation
) PARAMS ((rtx
, rtx
, rtx
));
4328 rtx high_bit
= operands
[2];
4332 alpha_split_tfmode_pair (operands
);
4334 /* Detect three flavors of operand overlap. */
4336 if (rtx_equal_p (operands
[0], operands
[2]))
4338 else if (rtx_equal_p (operands
[1], operands
[2]))
4340 if (rtx_equal_p (operands
[0], high_bit
))
4347 emit_move_insn (operands
[0], operands
[2]);
4349 /* ??? If the destination overlaps both source tf and high_bit, then
4350 assume source tf is dead in its entirety and use the other half
4351 for a scratch register. Otherwise "scratch" is just the proper
4352 destination register. */
4353 scratch
= operands
[move
< 2 ? 1 : 3];
4355 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
4359 emit_move_insn (operands
[0], operands
[2]);
4361 emit_move_insn (operands
[1], scratch
);
4365 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
4369 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
4370 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
4371 lda r3,X(r11) lda r3,X+2(r11)
4372 extwl r1,r3,r1 extql r1,r3,r1
4373 extwh r2,r3,r2 extqh r2,r3,r2
4374 or r1.r2.r1 or r1,r2,r1
4377 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
4378 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
4379 lda r3,X(r11) lda r3,X(r11)
4380 extll r1,r3,r1 extll r1,r3,r1
4381 extlh r2,r3,r2 extlh r2,r3,r2
4382 or r1.r2.r1 addl r1,r2,r1
4384 quad: ldq_u r1,X(r11)
4393 alpha_expand_unaligned_load (tgt
, mem
, size
, ofs
, sign
)
4395 HOST_WIDE_INT size
, ofs
;
4398 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
4399 enum machine_mode mode
;
4401 meml
= gen_reg_rtx (DImode
);
4402 memh
= gen_reg_rtx (DImode
);
4403 addr
= gen_reg_rtx (DImode
);
4404 extl
= gen_reg_rtx (DImode
);
4405 exth
= gen_reg_rtx (DImode
);
4407 mema
= XEXP (mem
, 0);
4408 if (GET_CODE (mema
) == LO_SUM
)
4409 mema
= force_reg (Pmode
, mema
);
4411 /* AND addresses cannot be in any alias set, since they may implicitly
4412 alias surrounding code. Ideally we'd have some alias set that
4413 covered all types except those with alignment 8 or higher. */
4415 tmp
= change_address (mem
, DImode
,
4416 gen_rtx_AND (DImode
,
4417 plus_constant (mema
, ofs
),
4419 set_mem_alias_set (tmp
, 0);
4420 emit_move_insn (meml
, tmp
);
4422 tmp
= change_address (mem
, DImode
,
4423 gen_rtx_AND (DImode
,
4424 plus_constant (mema
, ofs
+ size
- 1),
4426 set_mem_alias_set (tmp
, 0);
4427 emit_move_insn (memh
, tmp
);
4429 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
4431 emit_move_insn (addr
, plus_constant (mema
, -1));
4433 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4434 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
4436 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4437 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
4438 addr
, 1, OPTAB_WIDEN
);
4440 else if (sign
&& size
== 2)
4442 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
4444 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
4445 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4447 /* We must use tgt here for the target. Alpha-vms port fails if we use
4448 addr for the target, because addr is marked as a pointer and combine
4449 knows that pointers are always sign-extended 32 bit values. */
4450 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4451 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
4452 addr
, 1, OPTAB_WIDEN
);
4456 if (WORDS_BIG_ENDIAN
)
4458 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
4462 emit_insn (gen_extwh_be (extl
, meml
, addr
));
4467 emit_insn (gen_extlh_be (extl
, meml
, addr
));
4472 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4479 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
4483 emit_move_insn (addr
, plus_constant (mema
, ofs
));
4484 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
4488 emit_insn (gen_extwh_le (exth
, memh
, addr
));
4493 emit_insn (gen_extlh_le (exth
, memh
, addr
));
4498 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4507 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
4508 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
4513 emit_move_insn (tgt
, gen_lowpart(GET_MODE (tgt
), addr
));
4516 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4519 alpha_expand_unaligned_store (dst
, src
, size
, ofs
)
4521 HOST_WIDE_INT size
, ofs
;
4523 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
4525 dstl
= gen_reg_rtx (DImode
);
4526 dsth
= gen_reg_rtx (DImode
);
4527 insl
= gen_reg_rtx (DImode
);
4528 insh
= gen_reg_rtx (DImode
);
4530 dsta
= XEXP (dst
, 0);
4531 if (GET_CODE (dsta
) == LO_SUM
)
4532 dsta
= force_reg (Pmode
, dsta
);
4534 /* AND addresses cannot be in any alias set, since they may implicitly
4535 alias surrounding code. Ideally we'd have some alias set that
4536 covered all types except those with alignment 8 or higher. */
4538 meml
= change_address (dst
, DImode
,
4539 gen_rtx_AND (DImode
,
4540 plus_constant (dsta
, ofs
),
4542 set_mem_alias_set (meml
, 0);
4544 memh
= change_address (dst
, DImode
,
4545 gen_rtx_AND (DImode
,
4546 plus_constant (dsta
, ofs
+ size
- 1),
4548 set_mem_alias_set (memh
, 0);
4550 emit_move_insn (dsth
, memh
);
4551 emit_move_insn (dstl
, meml
);
4552 if (WORDS_BIG_ENDIAN
)
4554 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
4556 if (src
!= const0_rtx
)
4561 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
4564 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
4567 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
4570 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
4571 GEN_INT (size
*8), addr
));
4577 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
4581 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4582 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
4586 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
4590 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
4594 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
4596 if (src
!= const0_rtx
)
4598 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
4599 GEN_INT (size
*8), addr
));
4604 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
4607 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
4610 emit_insn (gen_insql_le (insl
, src
, addr
));
4615 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
4620 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
4624 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4625 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
4629 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
4634 if (src
!= const0_rtx
)
4636 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
4637 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
4640 if (WORDS_BIG_ENDIAN
)
4642 emit_move_insn (meml
, dstl
);
4643 emit_move_insn (memh
, dsth
);
4647 /* Must store high before low for degenerate case of aligned. */
4648 emit_move_insn (memh
, dsth
);
4649 emit_move_insn (meml
, dstl
);
4653 /* The block move code tries to maximize speed by separating loads and
4654 stores at the expense of register pressure: we load all of the data
4655 before we store it back out. There are two secondary effects worth
4656 mentioning, that this speeds copying to/from aligned and unaligned
4657 buffers, and that it makes the code significantly easier to write. */
4659 #define MAX_MOVE_WORDS 8
4661 /* Load an integral number of consecutive unaligned quadwords. */
4664 alpha_expand_unaligned_load_words (out_regs
, smem
, words
, ofs
)
4667 HOST_WIDE_INT words
, ofs
;
4669 rtx
const im8
= GEN_INT (-8);
4670 rtx
const i64
= GEN_INT (64);
4671 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
4672 rtx sreg
, areg
, tmp
, smema
;
4675 smema
= XEXP (smem
, 0);
4676 if (GET_CODE (smema
) == LO_SUM
)
4677 smema
= force_reg (Pmode
, smema
);
4679 /* Generate all the tmp registers we need. */
4680 for (i
= 0; i
< words
; ++i
)
4682 data_regs
[i
] = out_regs
[i
];
4683 ext_tmps
[i
] = gen_reg_rtx (DImode
);
4685 data_regs
[words
] = gen_reg_rtx (DImode
);
4688 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
4690 /* Load up all of the source data. */
4691 for (i
= 0; i
< words
; ++i
)
4693 tmp
= change_address (smem
, DImode
,
4694 gen_rtx_AND (DImode
,
4695 plus_constant (smema
, 8*i
),
4697 set_mem_alias_set (tmp
, 0);
4698 emit_move_insn (data_regs
[i
], tmp
);
4701 tmp
= change_address (smem
, DImode
,
4702 gen_rtx_AND (DImode
,
4703 plus_constant (smema
, 8*words
- 1),
4705 set_mem_alias_set (tmp
, 0);
4706 emit_move_insn (data_regs
[words
], tmp
);
4708 /* Extract the half-word fragments. Unfortunately DEC decided to make
4709 extxh with offset zero a noop instead of zeroing the register, so
4710 we must take care of that edge condition ourselves with cmov. */
4712 sreg
= copy_addr_to_reg (smema
);
4713 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
4715 if (WORDS_BIG_ENDIAN
)
4716 emit_move_insn (sreg
, plus_constant (sreg
, 7));
4717 for (i
= 0; i
< words
; ++i
)
4719 if (WORDS_BIG_ENDIAN
)
4721 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
4722 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
4726 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
4727 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
4729 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
4730 gen_rtx_IF_THEN_ELSE (DImode
,
4731 gen_rtx_EQ (DImode
, areg
,
4733 const0_rtx
, ext_tmps
[i
])));
4736 /* Merge the half-words into whole words. */
4737 for (i
= 0; i
< words
; ++i
)
4739 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4740 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
4744 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4745 may be NULL to store zeros. */
4748 alpha_expand_unaligned_store_words (data_regs
, dmem
, words
, ofs
)
4751 HOST_WIDE_INT words
, ofs
;
4753 rtx
const im8
= GEN_INT (-8);
4754 rtx
const i64
= GEN_INT (64);
4755 rtx ins_tmps
[MAX_MOVE_WORDS
];
4756 rtx st_tmp_1
, st_tmp_2
, dreg
;
4757 rtx st_addr_1
, st_addr_2
, dmema
;
4760 dmema
= XEXP (dmem
, 0);
4761 if (GET_CODE (dmema
) == LO_SUM
)
4762 dmema
= force_reg (Pmode
, dmema
);
4764 /* Generate all the tmp registers we need. */
4765 if (data_regs
!= NULL
)
4766 for (i
= 0; i
< words
; ++i
)
4767 ins_tmps
[i
] = gen_reg_rtx(DImode
);
4768 st_tmp_1
= gen_reg_rtx(DImode
);
4769 st_tmp_2
= gen_reg_rtx(DImode
);
4772 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
4774 st_addr_2
= change_address (dmem
, DImode
,
4775 gen_rtx_AND (DImode
,
4776 plus_constant (dmema
, words
*8 - 1),
4778 set_mem_alias_set (st_addr_2
, 0);
4780 st_addr_1
= change_address (dmem
, DImode
,
4781 gen_rtx_AND (DImode
, dmema
, im8
));
4782 set_mem_alias_set (st_addr_1
, 0);
4784 /* Load up the destination end bits. */
4785 emit_move_insn (st_tmp_2
, st_addr_2
);
4786 emit_move_insn (st_tmp_1
, st_addr_1
);
4788 /* Shift the input data into place. */
4789 dreg
= copy_addr_to_reg (dmema
);
4790 if (WORDS_BIG_ENDIAN
)
4791 emit_move_insn (dreg
, plus_constant (dreg
, 7));
4792 if (data_regs
!= NULL
)
4794 for (i
= words
-1; i
>= 0; --i
)
4796 if (WORDS_BIG_ENDIAN
)
4798 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
4799 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
4803 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
4804 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
4807 for (i
= words
-1; i
> 0; --i
)
4809 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4810 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
4815 /* Split and merge the ends with the destination data. */
4816 if (WORDS_BIG_ENDIAN
)
4818 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
4819 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
4823 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
4824 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
4827 if (data_regs
!= NULL
)
4829 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
4830 st_tmp_2
, 1, OPTAB_WIDEN
);
4831 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
4832 st_tmp_1
, 1, OPTAB_WIDEN
);
4836 if (WORDS_BIG_ENDIAN
)
4837 emit_move_insn (st_addr_1
, st_tmp_1
);
4839 emit_move_insn (st_addr_2
, st_tmp_2
);
4840 for (i
= words
-1; i
> 0; --i
)
4842 rtx tmp
= change_address (dmem
, DImode
,
4843 gen_rtx_AND (DImode
,
4844 plus_constant(dmema
,
4845 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
4847 set_mem_alias_set (tmp
, 0);
4848 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
4850 if (WORDS_BIG_ENDIAN
)
4851 emit_move_insn (st_addr_2
, st_tmp_2
);
4853 emit_move_insn (st_addr_1
, st_tmp_1
);
4857 /* Expand string/block move operations.
4859 operands[0] is the pointer to the destination.
4860 operands[1] is the pointer to the source.
4861 operands[2] is the number of bytes to move.
4862 operands[3] is the alignment. */
4865 alpha_expand_block_move (operands
)
4868 rtx bytes_rtx
= operands
[2];
4869 rtx align_rtx
= operands
[3];
4870 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4871 HOST_WIDE_INT bytes
= orig_bytes
;
4872 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4873 HOST_WIDE_INT dst_align
= src_align
;
4874 rtx orig_src
= operands
[1];
4875 rtx orig_dst
= operands
[0];
4876 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
4878 unsigned int i
, words
, ofs
, nregs
= 0;
4880 if (orig_bytes
<= 0)
4882 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4885 /* Look for additional alignment information from recorded register info. */
4887 tmp
= XEXP (orig_src
, 0);
4888 if (GET_CODE (tmp
) == REG
)
4889 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4890 else if (GET_CODE (tmp
) == PLUS
4891 && GET_CODE (XEXP (tmp
, 0)) == REG
4892 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4894 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4895 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4899 if (a
>= 64 && c
% 8 == 0)
4901 else if (a
>= 32 && c
% 4 == 0)
4903 else if (a
>= 16 && c
% 2 == 0)
4908 tmp
= XEXP (orig_dst
, 0);
4909 if (GET_CODE (tmp
) == REG
)
4910 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4911 else if (GET_CODE (tmp
) == PLUS
4912 && GET_CODE (XEXP (tmp
, 0)) == REG
4913 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4915 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4916 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4920 if (a
>= 64 && c
% 8 == 0)
4922 else if (a
>= 32 && c
% 4 == 0)
4924 else if (a
>= 16 && c
% 2 == 0)
4929 /* Load the entire block into registers. */
4930 if (GET_CODE (XEXP (orig_src
, 0)) == ADDRESSOF
)
4932 enum machine_mode mode
;
4934 tmp
= XEXP (XEXP (orig_src
, 0), 0);
4936 /* Don't use the existing register if we're reading more than
4937 is held in the register. Nor if there is not a mode that
4938 handles the exact size. */
4939 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4941 && GET_MODE_SIZE (GET_MODE (tmp
)) >= bytes
)
4945 data_regs
[nregs
] = gen_lowpart (DImode
, tmp
);
4946 data_regs
[nregs
+ 1] = gen_highpart (DImode
, tmp
);
4950 data_regs
[nregs
++] = gen_lowpart (mode
, tmp
);
4955 /* No appropriate mode; fall back on memory. */
4956 orig_src
= replace_equiv_address (orig_src
,
4957 copy_addr_to_reg (XEXP (orig_src
, 0)));
4958 src_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4962 if (src_align
>= 64 && bytes
>= 8)
4966 for (i
= 0; i
< words
; ++i
)
4967 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4969 for (i
= 0; i
< words
; ++i
)
4970 emit_move_insn (data_regs
[nregs
+ i
],
4971 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
4978 if (src_align
>= 32 && bytes
>= 4)
4982 for (i
= 0; i
< words
; ++i
)
4983 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
4985 for (i
= 0; i
< words
; ++i
)
4986 emit_move_insn (data_regs
[nregs
+ i
],
4987 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
4998 for (i
= 0; i
< words
+1; ++i
)
4999 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
5001 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
5009 if (! TARGET_BWX
&& bytes
>= 4)
5011 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
5012 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
5019 if (src_align
>= 16)
5022 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
5023 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
5026 } while (bytes
>= 2);
5028 else if (! TARGET_BWX
)
5030 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
5031 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
5039 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
5040 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
5047 if (nregs
> ARRAY_SIZE (data_regs
))
5050 /* Now save it back out again. */
5054 if (GET_CODE (XEXP (orig_dst
, 0)) == ADDRESSOF
)
5056 enum machine_mode mode
;
5057 tmp
= XEXP (XEXP (orig_dst
, 0), 0);
5059 mode
= mode_for_size (orig_bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
5060 if (GET_MODE (tmp
) == mode
)
5064 emit_move_insn (tmp
, data_regs
[0]);
5069 else if (nregs
== 2 && mode
== TImode
)
5071 /* Undo the subregging done above when copying between
5072 two TImode registers. */
5073 if (GET_CODE (data_regs
[0]) == SUBREG
5074 && GET_MODE (SUBREG_REG (data_regs
[0])) == TImode
)
5075 emit_move_insn (tmp
, SUBREG_REG (data_regs
[0]));
5081 emit_move_insn (gen_lowpart (DImode
, tmp
), data_regs
[0]);
5082 emit_move_insn (gen_highpart (DImode
, tmp
), data_regs
[1]);
5086 emit_no_conflict_block (seq
, tmp
, data_regs
[0],
5087 data_regs
[1], NULL_RTX
);
5095 /* ??? If nregs > 1, consider reconstructing the word in regs. */
5096 /* ??? Optimize mode < dst_mode with strict_low_part. */
5098 /* No appropriate mode; fall back on memory. We can speed things
5099 up by recognizing extra alignment information. */
5100 orig_dst
= replace_equiv_address (orig_dst
,
5101 copy_addr_to_reg (XEXP (orig_dst
, 0)));
5102 dst_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
5105 /* Write out the data in whatever chunks reading the source allowed. */
5106 if (dst_align
>= 64)
5108 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
5110 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
5117 if (dst_align
>= 32)
5119 /* If the source has remaining DImode regs, write them out in
5121 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
5123 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
5124 NULL_RTX
, 1, OPTAB_WIDEN
);
5126 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
5127 gen_lowpart (SImode
, data_regs
[i
]));
5128 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
5129 gen_lowpart (SImode
, tmp
));
5134 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
5136 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
5143 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
5145 /* Write out a remaining block of words using unaligned methods. */
5147 for (words
= 1; i
+ words
< nregs
; words
++)
5148 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
5152 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
5154 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
5161 /* Due to the above, this won't be aligned. */
5162 /* ??? If we have more than one of these, consider constructing full
5163 words in registers and using alpha_expand_unaligned_store_words. */
5164 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
5166 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
5171 if (dst_align
>= 16)
5172 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
5174 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
5179 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
5181 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
5186 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
5188 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
5202 alpha_expand_block_clear (operands
)
5205 rtx bytes_rtx
= operands
[1];
5206 rtx align_rtx
= operands
[2];
5207 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
5208 HOST_WIDE_INT bytes
= orig_bytes
;
5209 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
5210 HOST_WIDE_INT alignofs
= 0;
5211 rtx orig_dst
= operands
[0];
5213 int i
, words
, ofs
= 0;
5215 if (orig_bytes
<= 0)
5217 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
5220 /* Look for stricter alignment. */
5221 tmp
= XEXP (orig_dst
, 0);
5222 if (GET_CODE (tmp
) == REG
)
5223 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
5224 else if (GET_CODE (tmp
) == PLUS
5225 && GET_CODE (XEXP (tmp
, 0)) == REG
5226 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
5228 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
5229 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
5234 align
= a
, alignofs
= 8 - c
% 8;
5236 align
= a
, alignofs
= 4 - c
% 4;
5238 align
= a
, alignofs
= 2 - c
% 2;
5241 else if (GET_CODE (tmp
) == ADDRESSOF
)
5243 enum machine_mode mode
;
5245 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
5246 if (GET_MODE (XEXP (tmp
, 0)) == mode
)
5248 emit_move_insn (XEXP (tmp
, 0), const0_rtx
);
5252 /* No appropriate mode; fall back on memory. */
5253 orig_dst
= replace_equiv_address (orig_dst
, copy_addr_to_reg (tmp
));
5254 align
= GET_MODE_BITSIZE (GET_MODE (XEXP (tmp
, 0)));
5257 /* Handle an unaligned prefix first. */
5261 #if HOST_BITS_PER_WIDE_INT >= 64
5262 /* Given that alignofs is bounded by align, the only time BWX could
5263 generate three stores is for a 7 byte fill. Prefer two individual
5264 stores over a load/mask/store sequence. */
5265 if ((!TARGET_BWX
|| alignofs
== 7)
5267 && !(alignofs
== 4 && bytes
>= 4))
5269 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
5270 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
5274 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
5275 set_mem_alias_set (mem
, 0);
5277 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
5278 if (bytes
< alignofs
)
5280 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
5291 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
5292 NULL_RTX
, 1, OPTAB_WIDEN
);
5294 emit_move_insn (mem
, tmp
);
5298 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
5300 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5305 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
5307 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
5312 if (alignofs
== 4 && bytes
>= 4)
5314 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
5320 /* If we've not used the extra lead alignment information by now,
5321 we won't be able to. Downgrade align to match what's left over. */
5324 alignofs
= alignofs
& -alignofs
;
5325 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
5329 /* Handle a block of contiguous long-words. */
5331 if (align
>= 64 && bytes
>= 8)
5335 for (i
= 0; i
< words
; ++i
)
5336 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
5343 /* If the block is large and appropriately aligned, emit a single
5344 store followed by a sequence of stq_u insns. */
5346 if (align
>= 32 && bytes
> 16)
5350 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
5354 orig_dsta
= XEXP (orig_dst
, 0);
5355 if (GET_CODE (orig_dsta
) == LO_SUM
)
5356 orig_dsta
= force_reg (Pmode
, orig_dsta
);
5359 for (i
= 0; i
< words
; ++i
)
5362 = change_address (orig_dst
, DImode
,
5363 gen_rtx_AND (DImode
,
5364 plus_constant (orig_dsta
, ofs
+ i
*8),
5366 set_mem_alias_set (mem
, 0);
5367 emit_move_insn (mem
, const0_rtx
);
5370 /* Depending on the alignment, the first stq_u may have overlapped
5371 with the initial stl, which means that the last stq_u didn't
5372 write as much as it would appear. Leave those questionable bytes
5374 bytes
-= words
* 8 - 4;
5375 ofs
+= words
* 8 - 4;
5378 /* Handle a smaller block of aligned words. */
5380 if ((align
>= 64 && bytes
== 4)
5381 || (align
== 32 && bytes
>= 4))
5385 for (i
= 0; i
< words
; ++i
)
5386 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
5393 /* An unaligned block uses stq_u stores for as many as possible. */
5399 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
5405 /* Next clean up any trailing pieces. */
5407 #if HOST_BITS_PER_WIDE_INT >= 64
5408 /* Count the number of bits in BYTES for which aligned stores could
5411 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
5415 /* If we have appropriate alignment (and it wouldn't take too many
5416 instructions otherwise), mask out the bytes we need. */
5417 if (TARGET_BWX
? words
> 2 : bytes
> 0)
5424 mem
= adjust_address (orig_dst
, DImode
, ofs
);
5425 set_mem_alias_set (mem
, 0);
5427 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5429 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
5430 NULL_RTX
, 1, OPTAB_WIDEN
);
5432 emit_move_insn (mem
, tmp
);
5435 else if (align
>= 32 && bytes
< 4)
5440 mem
= adjust_address (orig_dst
, SImode
, ofs
);
5441 set_mem_alias_set (mem
, 0);
5443 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5445 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
5446 NULL_RTX
, 1, OPTAB_WIDEN
);
5448 emit_move_insn (mem
, tmp
);
5454 if (!TARGET_BWX
&& bytes
>= 4)
5456 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
5466 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
5470 } while (bytes
>= 2);
5472 else if (! TARGET_BWX
)
5474 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
5482 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5490 /* Returns a mask so that zap(x, value) == x & mask. */
5493 alpha_expand_zap_mask (value
)
5494 HOST_WIDE_INT value
;
5499 if (HOST_BITS_PER_WIDE_INT
>= 64)
5501 HOST_WIDE_INT mask
= 0;
5503 for (i
= 7; i
>= 0; --i
)
5506 if (!((value
>> i
) & 1))
5510 result
= gen_int_mode (mask
, DImode
);
5512 else if (HOST_BITS_PER_WIDE_INT
== 32)
5514 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
5516 for (i
= 7; i
>= 4; --i
)
5519 if (!((value
>> i
) & 1))
5523 for (i
= 3; i
>= 0; --i
)
5526 if (!((value
>> i
) & 1))
5530 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
5539 alpha_expand_builtin_vector_binop (gen
, mode
, op0
, op1
, op2
)
5540 rtx (*gen
) PARAMS ((rtx
, rtx
, rtx
));
5541 enum machine_mode mode
;
5544 op0
= gen_lowpart (mode
, op0
);
5546 if (op1
== const0_rtx
)
5547 op1
= CONST0_RTX (mode
);
5549 op1
= gen_lowpart (mode
, op1
);
5551 if (op2
== const0_rtx
)
5552 op2
= CONST0_RTX (mode
);
5554 op2
= gen_lowpart (mode
, op2
);
5556 emit_insn ((*gen
) (op0
, op1
, op2
));
5559 /* Adjust the cost of a scheduling dependency. Return the new cost of
5560 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5563 alpha_adjust_cost (insn
, link
, dep_insn
, cost
)
5569 enum attr_type insn_type
, dep_insn_type
;
5571 /* If the dependence is an anti-dependence, there is no cost. For an
5572 output dependence, there is sometimes a cost, but it doesn't seem
5573 worth handling those few cases. */
5574 if (REG_NOTE_KIND (link
) != 0)
5577 /* If we can't recognize the insns, we can't really do anything. */
5578 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
5581 insn_type
= get_attr_type (insn
);
5582 dep_insn_type
= get_attr_type (dep_insn
);
5584 /* Bring in the user-defined memory latency. */
5585 if (dep_insn_type
== TYPE_ILD
5586 || dep_insn_type
== TYPE_FLD
5587 || dep_insn_type
== TYPE_LDSYM
)
5588 cost
+= alpha_memory_latency
-1;
5590 /* Everything else handled in DFA bypasses now. */
5595 /* The number of instructions that can be issued per cycle. */
5600 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
5604 alpha_use_dfa_pipeline_interface ()
5609 /* How many alternative schedules to try. This should be as wide as the
5610 scheduling freedom in the DFA, but no wider. Making this value too
5611 large results extra work for the scheduler.
5613 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5614 alternative schedules. For EV5, we can choose between E0/E1 and
5615 FA/FM. For EV6, an arithmatic insn can be issued to U0/U1/L0/L1. */
5618 alpha_multipass_dfa_lookahead ()
5620 return (alpha_cpu
== PROCESSOR_EV6
? 4 : 2);
5623 /* Machine-specific function data. */
5625 struct machine_function
GTY(())
5628 /* List of call information words for calls from this function. */
5629 struct rtx_def
*first_ciw
;
5630 struct rtx_def
*last_ciw
;
5633 /* List of deferred case vectors. */
5634 struct rtx_def
*addr_list
;
5637 const char *some_ld_name
;
5640 /* How to allocate a 'struct machine_function'. */
5642 static struct machine_function
*
5643 alpha_init_machine_status ()
5645 return ((struct machine_function
*)
5646 ggc_alloc_cleared (sizeof (struct machine_function
)));
5649 /* Functions to save and restore alpha_return_addr_rtx. */
5651 /* Start the ball rolling with RETURN_ADDR_RTX. */
5654 alpha_return_addr (count
, frame
)
5656 rtx frame ATTRIBUTE_UNUSED
;
5661 return get_hard_reg_initial_val (Pmode
, REG_RA
);
5664 /* Return or create a pseudo containing the gp value for the current
5665 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5668 alpha_gp_save_rtx ()
5670 rtx r
= get_hard_reg_initial_val (DImode
, 29);
5671 if (GET_CODE (r
) != MEM
)
5672 r
= gen_mem_addressof (r
, NULL_TREE
);
5677 alpha_ra_ever_killed ()
5681 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
5682 return regs_ever_live
[REG_RA
];
5684 push_topmost_sequence ();
5686 pop_topmost_sequence ();
5688 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
5692 /* Return the trap mode suffix applicable to the current
5693 instruction, or NULL. */
5696 get_trap_mode_suffix ()
5698 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
5702 case TRAP_SUFFIX_NONE
:
5705 case TRAP_SUFFIX_SU
:
5706 if (alpha_fptm
>= ALPHA_FPTM_SU
)
5710 case TRAP_SUFFIX_SUI
:
5711 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
5715 case TRAP_SUFFIX_V_SV
:
5723 case ALPHA_FPTM_SUI
:
5728 case TRAP_SUFFIX_V_SV_SVI
:
5737 case ALPHA_FPTM_SUI
:
5742 case TRAP_SUFFIX_U_SU_SUI
:
5751 case ALPHA_FPTM_SUI
:
5759 /* Return the rounding mode suffix applicable to the current
5760 instruction, or NULL. */
5763 get_round_mode_suffix ()
5765 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5769 case ROUND_SUFFIX_NONE
:
5771 case ROUND_SUFFIX_NORMAL
:
5774 case ALPHA_FPRM_NORM
:
5776 case ALPHA_FPRM_MINF
:
5778 case ALPHA_FPRM_CHOP
:
5780 case ALPHA_FPRM_DYN
:
5785 case ROUND_SUFFIX_C
:
5791 /* Locate some local-dynamic symbol still in use by this function
5792 so that we can print its name in some movdi_er_tlsldm pattern. */
5795 get_some_local_dynamic_name ()
5799 if (cfun
->machine
->some_ld_name
)
5800 return cfun
->machine
->some_ld_name
;
5802 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5804 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5805 return cfun
->machine
->some_ld_name
;
5811 get_some_local_dynamic_name_1 (px
, data
)
5813 void *data ATTRIBUTE_UNUSED
;
5817 if (GET_CODE (x
) == SYMBOL_REF
)
5819 const char *str
= XSTR (x
, 0);
5820 if (str
[0] == '@' && str
[1] == 'D')
5822 cfun
->machine
->some_ld_name
= str
;
5830 /* Print an operand. Recognize special options, documented below. */
5833 print_operand (file
, x
, code
)
5843 /* Print the assembler name of the current function. */
5844 assemble_name (file
, alpha_fnname
);
5848 assemble_name (file
, get_some_local_dynamic_name ());
5853 const char *trap
= get_trap_mode_suffix ();
5854 const char *round
= get_round_mode_suffix ();
5857 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5858 (trap
? trap
: ""), (round
? round
: ""));
5863 /* Generates single precision instruction suffix. */
5864 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5868 /* Generates double precision instruction suffix. */
5869 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5873 if (alpha_this_literal_sequence_number
== 0)
5874 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5875 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5879 if (alpha_this_gpdisp_sequence_number
== 0)
5880 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5881 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5885 if (GET_CODE (x
) == HIGH
)
5886 output_addr_const (file
, XEXP (x
, 0));
5888 output_operand_lossage ("invalid %%H value");
5895 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5897 x
= XVECEXP (x
, 0, 0);
5898 lituse
= "lituse_tlsgd";
5900 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5902 x
= XVECEXP (x
, 0, 0);
5903 lituse
= "lituse_tlsldm";
5905 else if (GET_CODE (x
) == CONST_INT
)
5906 lituse
= "lituse_jsr";
5909 output_operand_lossage ("invalid %%J value");
5913 if (x
!= const0_rtx
)
5914 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5919 /* If this operand is the constant zero, write it as "$31". */
5920 if (GET_CODE (x
) == REG
)
5921 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5922 else if (x
== CONST0_RTX (GET_MODE (x
)))
5923 fprintf (file
, "$31");
5925 output_operand_lossage ("invalid %%r value");
5929 /* Similar, but for floating-point. */
5930 if (GET_CODE (x
) == REG
)
5931 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5932 else if (x
== CONST0_RTX (GET_MODE (x
)))
5933 fprintf (file
, "$f31");
5935 output_operand_lossage ("invalid %%R value");
5939 /* Write the 1's complement of a constant. */
5940 if (GET_CODE (x
) != CONST_INT
)
5941 output_operand_lossage ("invalid %%N value");
5943 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5947 /* Write 1 << C, for a constant C. */
5948 if (GET_CODE (x
) != CONST_INT
)
5949 output_operand_lossage ("invalid %%P value");
5951 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5955 /* Write the high-order 16 bits of a constant, sign-extended. */
5956 if (GET_CODE (x
) != CONST_INT
)
5957 output_operand_lossage ("invalid %%h value");
5959 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5963 /* Write the low-order 16 bits of a constant, sign-extended. */
5964 if (GET_CODE (x
) != CONST_INT
)
5965 output_operand_lossage ("invalid %%L value");
5967 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5968 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5972 /* Write mask for ZAP insn. */
5973 if (GET_CODE (x
) == CONST_DOUBLE
)
5975 HOST_WIDE_INT mask
= 0;
5976 HOST_WIDE_INT value
;
5978 value
= CONST_DOUBLE_LOW (x
);
5979 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5984 value
= CONST_DOUBLE_HIGH (x
);
5985 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5988 mask
|= (1 << (i
+ sizeof (int)));
5990 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5993 else if (GET_CODE (x
) == CONST_INT
)
5995 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5997 for (i
= 0; i
< 8; i
++, value
>>= 8)
6001 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
6004 output_operand_lossage ("invalid %%m value");
6008 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
6009 if (GET_CODE (x
) != CONST_INT
6010 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
6011 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
6012 output_operand_lossage ("invalid %%M value");
6014 fprintf (file
, "%s",
6015 (INTVAL (x
) == 8 ? "b"
6016 : INTVAL (x
) == 16 ? "w"
6017 : INTVAL (x
) == 32 ? "l"
6022 /* Similar, except do it from the mask. */
6023 if (GET_CODE (x
) == CONST_INT
)
6025 HOST_WIDE_INT value
= INTVAL (x
);
6032 if (value
== 0xffff)
6037 if (value
== 0xffffffff)
6048 else if (HOST_BITS_PER_WIDE_INT
== 32
6049 && GET_CODE (x
) == CONST_DOUBLE
6050 && CONST_DOUBLE_LOW (x
) == 0xffffffff
6051 && CONST_DOUBLE_HIGH (x
) == 0)
6056 output_operand_lossage ("invalid %%U value");
6060 /* Write the constant value divided by 8 for little-endian mode or
6061 (56 - value) / 8 for big-endian mode. */
6063 if (GET_CODE (x
) != CONST_INT
6064 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
6067 || (INTVAL (x
) & 7) != 0)
6068 output_operand_lossage ("invalid %%s value");
6070 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6072 ? (56 - INTVAL (x
)) / 8
6077 /* Same, except compute (64 - c) / 8 */
6079 if (GET_CODE (x
) != CONST_INT
6080 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
6081 && (INTVAL (x
) & 7) != 8)
6082 output_operand_lossage ("invalid %%s value");
6084 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
6089 /* On Unicos/Mk systems: use a DEX expression if the symbol
6090 clashes with a register name. */
6091 int dex
= unicosmk_need_dex (x
);
6093 fprintf (file
, "DEX(%d)", dex
);
6095 output_addr_const (file
, x
);
6099 case 'C': case 'D': case 'c': case 'd':
6100 /* Write out comparison name. */
6102 enum rtx_code c
= GET_CODE (x
);
6104 if (GET_RTX_CLASS (c
) != '<')
6105 output_operand_lossage ("invalid %%C value");
6107 else if (code
== 'D')
6108 c
= reverse_condition (c
);
6109 else if (code
== 'c')
6110 c
= swap_condition (c
);
6111 else if (code
== 'd')
6112 c
= swap_condition (reverse_condition (c
));
6115 fprintf (file
, "ule");
6117 fprintf (file
, "ult");
6118 else if (c
== UNORDERED
)
6119 fprintf (file
, "un");
6121 fprintf (file
, "%s", GET_RTX_NAME (c
));
6126 /* Write the divide or modulus operator. */
6127 switch (GET_CODE (x
))
6130 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
6133 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
6136 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
6139 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
6142 output_operand_lossage ("invalid %%E value");
6148 /* Write "_u" for unaligned access. */
6149 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
6150 fprintf (file
, "_u");
6154 if (GET_CODE (x
) == REG
)
6155 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
6156 else if (GET_CODE (x
) == MEM
)
6157 output_address (XEXP (x
, 0));
6158 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
6160 switch (XINT (XEXP (x
, 0), 1))
6164 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
6167 output_operand_lossage ("unknown relocation unspec");
6172 output_addr_const (file
, x
);
6176 output_operand_lossage ("invalid %%xn code");
6181 print_operand_address (file
, addr
)
6186 HOST_WIDE_INT offset
= 0;
6188 if (GET_CODE (addr
) == AND
)
6189 addr
= XEXP (addr
, 0);
6191 if (GET_CODE (addr
) == PLUS
6192 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
6194 offset
= INTVAL (XEXP (addr
, 1));
6195 addr
= XEXP (addr
, 0);
6198 if (GET_CODE (addr
) == LO_SUM
)
6200 const char *reloc16
, *reloclo
;
6201 rtx op1
= XEXP (addr
, 1);
6203 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
6205 op1
= XEXP (op1
, 0);
6206 switch (XINT (op1
, 1))
6210 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
6214 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
6217 output_operand_lossage ("unknown relocation unspec");
6221 output_addr_const (file
, XVECEXP (op1
, 0, 0));
6226 reloclo
= "gprellow";
6227 output_addr_const (file
, op1
);
6233 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
6236 addr
= XEXP (addr
, 0);
6237 if (GET_CODE (addr
) == REG
)
6238 basereg
= REGNO (addr
);
6239 else if (GET_CODE (addr
) == SUBREG
6240 && GET_CODE (SUBREG_REG (addr
)) == REG
)
6241 basereg
= subreg_regno (addr
);
6245 fprintf (file
, "($%d)\t\t!%s", basereg
,
6246 (basereg
== 29 ? reloc16
: reloclo
));
6250 if (GET_CODE (addr
) == REG
)
6251 basereg
= REGNO (addr
);
6252 else if (GET_CODE (addr
) == SUBREG
6253 && GET_CODE (SUBREG_REG (addr
)) == REG
)
6254 basereg
= subreg_regno (addr
);
6255 else if (GET_CODE (addr
) == CONST_INT
)
6256 offset
= INTVAL (addr
);
6258 #if TARGET_ABI_OPEN_VMS
6259 else if (GET_CODE (addr
) == SYMBOL_REF
)
6261 fprintf (file
, "%s", XSTR (addr
, 0));
6264 else if (GET_CODE (addr
) == CONST
6265 && GET_CODE (XEXP (addr
, 0)) == PLUS
6266 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
6268 fprintf (file
, "%s+%d",
6269 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
6270 INTVAL (XEXP (XEXP (addr
, 0), 1)));
6278 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
6279 fprintf (file
, "($%d)", basereg
);
6282 /* Emit RTL insns to initialize the variable parts of a trampoline at
6283 TRAMP. FNADDR is an RTX for the address of the function's pure
6284 code. CXT is an RTX for the static chain value for the function.
6286 The three offset parameters are for the individual template's
6287 layout. A JMPOFS < 0 indicates that the trampoline does not
6288 contain instructions at all.
6290 We assume here that a function will be called many more times than
6291 its address is taken (e.g., it might be passed to qsort), so we
6292 take the trouble to initialize the "hint" field in the JMP insn.
6293 Note that the hint field is PC (new) + 4 * bits 13:0. */
6296 alpha_initialize_trampoline (tramp
, fnaddr
, cxt
, fnofs
, cxtofs
, jmpofs
)
6297 rtx tramp
, fnaddr
, cxt
;
6298 int fnofs
, cxtofs
, jmpofs
;
6300 rtx temp
, temp1
, addr
;
6301 /* VMS really uses DImode pointers in memory at this point. */
6302 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
6304 #ifdef POINTERS_EXTEND_UNSIGNED
6305 fnaddr
= convert_memory_address (mode
, fnaddr
);
6306 cxt
= convert_memory_address (mode
, cxt
);
6309 /* Store function address and CXT. */
6310 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
6311 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
6312 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
6313 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
6315 /* This has been disabled since the hint only has a 32k range, and in
6316 no existing OS is the stack within 32k of the text segment. */
6317 if (0 && jmpofs
>= 0)
6319 /* Compute hint value. */
6320 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
6321 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
6323 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
6324 build_int_2 (2, 0), NULL_RTX
, 1);
6325 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
6326 GEN_INT (0x3fff), 0);
6328 /* Merge in the hint. */
6329 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
6330 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
6331 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
6332 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
6334 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
6337 #ifdef TRANSFER_FROM_TRAMPOLINE
6338 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
6339 0, VOIDmode
, 1, tramp
, Pmode
);
6343 emit_insn (gen_imb ());
6346 /* Determine where to put an argument to a function.
6347 Value is zero to push the argument on the stack,
6348 or a hard register in which to store the argument.
6350 MODE is the argument's machine mode.
6351 TYPE is the data type of the argument (as a tree).
6352 This is null for libcalls where that information may
6354 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6355 the preceding args and about the function being called.
6356 NAMED is nonzero if this argument is a named parameter
6357 (otherwise it is an extra parameter matching an ellipsis).
6359 On Alpha the first 6 words of args are normally in registers
6360 and the rest are pushed. */
6363 function_arg (cum
, mode
, type
, named
)
6364 CUMULATIVE_ARGS cum
;
6365 enum machine_mode mode
;
6367 int named ATTRIBUTE_UNUSED
;
6372 /* Set up defaults for FP operands passed in FP registers, and
6373 integral operands passed in integer registers. */
6375 && (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
6376 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
6381 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
6382 the three platforms, so we can't avoid conditional compilation. */
6383 #if TARGET_ABI_OPEN_VMS
6385 if (mode
== VOIDmode
)
6386 return alpha_arg_info_reg_val (cum
);
6388 num_args
= cum
.num_args
;
6389 if (num_args
>= 6 || MUST_PASS_IN_STACK (mode
, type
))
6393 #if TARGET_ABI_UNICOSMK
6397 /* If this is the last argument, generate the call info word (CIW). */
6398 /* ??? We don't include the caller's line number in the CIW because
6399 I don't know how to determine it if debug infos are turned off. */
6400 if (mode
== VOIDmode
)
6409 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
6410 if (cum
.reg_args_type
[i
])
6411 lo
|= (1 << (7 - i
));
6413 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
6416 lo
|= cum
.num_reg_words
;
6418 #if HOST_BITS_PER_WIDE_INT == 32
6419 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
6421 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
6422 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
6425 ciw
= immed_double_const (lo
, hi
, DImode
);
6427 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
6428 UNSPEC_UMK_LOAD_CIW
);
6431 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
6432 num_args
= cum
.num_reg_words
;
6433 if (MUST_PASS_IN_STACK (mode
, type
)
6434 || cum
.num_reg_words
+ size
> 6 || cum
.force_stack
)
6436 else if (type
&& TYPE_MODE (type
) == BLKmode
)
6440 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
6441 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
6443 /* The argument fits in two registers. Note that we still need to
6444 reserve a register for empty structures. */
6448 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
6451 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
6452 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
6453 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
6463 /* VOID is passed as a special flag for "last argument". */
6464 if (type
== void_type_node
)
6466 else if (MUST_PASS_IN_STACK (mode
, type
))
6468 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum
, mode
, type
, named
))
6471 #endif /* TARGET_ABI_UNICOSMK */
6472 #endif /* TARGET_ABI_OPEN_VMS */
6474 return gen_rtx_REG (mode
, num_args
+ basereg
);
6478 alpha_build_va_list ()
6480 tree base
, ofs
, record
, type_decl
;
6482 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6483 return ptr_type_node
;
6485 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6486 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6487 TREE_CHAIN (record
) = type_decl
;
6488 TYPE_NAME (record
) = type_decl
;
6490 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6492 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
6494 DECL_FIELD_CONTEXT (ofs
) = record
;
6496 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
6498 DECL_FIELD_CONTEXT (base
) = record
;
6499 TREE_CHAIN (base
) = ofs
;
6501 TYPE_FIELDS (record
) = base
;
6502 layout_type (record
);
6508 alpha_va_start (valist
, nextarg
)
6510 rtx nextarg ATTRIBUTE_UNUSED
;
6512 HOST_WIDE_INT offset
;
6513 tree t
, offset_field
, base_field
;
6515 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6518 if (TARGET_ABI_UNICOSMK
)
6519 std_expand_builtin_va_start (valist
, nextarg
);
6521 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6522 up by 48, storing fp arg registers in the first 48 bytes, and the
6523 integer arg registers in the next 48 bytes. This is only done,
6524 however, if any integer registers need to be stored.
6526 If no integer registers need be stored, then we must subtract 48
6527 in order to account for the integer arg registers which are counted
6528 in argsize above, but which are not actually stored on the stack. */
6531 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6533 offset
= -6 * UNITS_PER_WORD
;
6535 if (TARGET_ABI_OPEN_VMS
)
6537 nextarg
= plus_constant (nextarg
, offset
);
6538 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
6539 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
6540 make_tree (ptr_type_node
, nextarg
));
6541 TREE_SIDE_EFFECTS (t
) = 1;
6543 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6547 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6548 offset_field
= TREE_CHAIN (base_field
);
6550 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6551 valist
, base_field
);
6552 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6553 valist
, offset_field
);
6555 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6556 t
= build (PLUS_EXPR
, ptr_type_node
, t
, build_int_2 (offset
, 0));
6557 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6558 TREE_SIDE_EFFECTS (t
) = 1;
6559 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6561 t
= build_int_2 (NUM_ARGS
* UNITS_PER_WORD
, 0);
6562 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6563 TREE_SIDE_EFFECTS (t
) = 1;
6564 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6569 alpha_va_arg (valist
, type
)
6573 tree t
, type_size
, rounded_size
;
6574 tree offset_field
, base_field
, addr_tree
, addend
;
6575 tree wide_type
, wide_ofs
;
6578 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6579 return std_expand_builtin_va_arg (valist
, type
);
6581 if (type
== error_mark_node
6582 || (type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
))) == NULL
6583 || TREE_OVERFLOW (type_size
))
6584 rounded_size
= size_zero_node
;
6586 rounded_size
= fold (build (MULT_EXPR
, sizetype
,
6587 fold (build (TRUNC_DIV_EXPR
, sizetype
,
6588 fold (build (PLUS_EXPR
, sizetype
,
6594 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6595 offset_field
= TREE_CHAIN (base_field
);
6597 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6598 valist
, base_field
);
6599 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6600 valist
, offset_field
);
6602 /* If the type could not be passed in registers, skip the block
6603 reserved for the registers. */
6604 if (MUST_PASS_IN_STACK (TYPE_MODE (type
), type
))
6606 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6607 build (MAX_EXPR
, TREE_TYPE (offset_field
),
6608 offset_field
, build_int_2 (6*8, 0)));
6609 TREE_SIDE_EFFECTS (t
) = 1;
6610 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6613 wide_type
= make_signed_type (64);
6614 wide_ofs
= save_expr (build1 (CONVERT_EXPR
, wide_type
, offset_field
));
6618 if (TYPE_MODE (type
) == TFmode
|| TYPE_MODE (type
) == TCmode
)
6621 rounded_size
= size_int (UNITS_PER_WORD
);
6623 else if (FLOAT_TYPE_P (type
))
6625 tree fpaddend
, cond
;
6627 fpaddend
= fold (build (PLUS_EXPR
, TREE_TYPE (addend
),
6628 addend
, build_int_2 (-6*8, 0)));
6630 cond
= fold (build (LT_EXPR
, integer_type_node
,
6631 wide_ofs
, build_int_2 (6*8, 0)));
6633 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
6637 addr_tree
= build (PLUS_EXPR
, TREE_TYPE (base_field
),
6638 base_field
, addend
);
6640 addr
= expand_expr (addr_tree
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
6641 addr
= copy_to_reg (addr
);
6643 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6644 build (PLUS_EXPR
, TREE_TYPE (offset_field
),
6645 offset_field
, rounded_size
));
6646 TREE_SIDE_EFFECTS (t
) = 1;
6647 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6651 addr
= force_reg (Pmode
, addr
);
6652 addr
= gen_rtx_MEM (Pmode
, addr
);
6662 ALPHA_BUILTIN_CMPBGE
,
6663 ALPHA_BUILTIN_EXTBL
,
6664 ALPHA_BUILTIN_EXTWL
,
6665 ALPHA_BUILTIN_EXTLL
,
6666 ALPHA_BUILTIN_EXTQL
,
6667 ALPHA_BUILTIN_EXTWH
,
6668 ALPHA_BUILTIN_EXTLH
,
6669 ALPHA_BUILTIN_EXTQH
,
6670 ALPHA_BUILTIN_INSBL
,
6671 ALPHA_BUILTIN_INSWL
,
6672 ALPHA_BUILTIN_INSLL
,
6673 ALPHA_BUILTIN_INSQL
,
6674 ALPHA_BUILTIN_INSWH
,
6675 ALPHA_BUILTIN_INSLH
,
6676 ALPHA_BUILTIN_INSQH
,
6677 ALPHA_BUILTIN_MSKBL
,
6678 ALPHA_BUILTIN_MSKWL
,
6679 ALPHA_BUILTIN_MSKLL
,
6680 ALPHA_BUILTIN_MSKQL
,
6681 ALPHA_BUILTIN_MSKWH
,
6682 ALPHA_BUILTIN_MSKLH
,
6683 ALPHA_BUILTIN_MSKQH
,
6684 ALPHA_BUILTIN_UMULH
,
6686 ALPHA_BUILTIN_ZAPNOT
,
6687 ALPHA_BUILTIN_AMASK
,
6688 ALPHA_BUILTIN_IMPLVER
,
6690 ALPHA_BUILTIN_THREAD_POINTER
,
6691 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6694 ALPHA_BUILTIN_MINUB8
,
6695 ALPHA_BUILTIN_MINSB8
,
6696 ALPHA_BUILTIN_MINUW4
,
6697 ALPHA_BUILTIN_MINSW4
,
6698 ALPHA_BUILTIN_MAXUB8
,
6699 ALPHA_BUILTIN_MAXSB8
,
6700 ALPHA_BUILTIN_MAXUW4
,
6701 ALPHA_BUILTIN_MAXSW4
,
6705 ALPHA_BUILTIN_UNPKBL
,
6706 ALPHA_BUILTIN_UNPKBW
,
6711 ALPHA_BUILTIN_CTPOP
,
6716 static unsigned int const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6717 CODE_FOR_builtin_cmpbge
,
6718 CODE_FOR_builtin_extbl
,
6719 CODE_FOR_builtin_extwl
,
6720 CODE_FOR_builtin_extll
,
6721 CODE_FOR_builtin_extql
,
6722 CODE_FOR_builtin_extwh
,
6723 CODE_FOR_builtin_extlh
,
6724 CODE_FOR_builtin_extqh
,
6725 CODE_FOR_builtin_insbl
,
6726 CODE_FOR_builtin_inswl
,
6727 CODE_FOR_builtin_insll
,
6728 CODE_FOR_builtin_insql
,
6729 CODE_FOR_builtin_inswh
,
6730 CODE_FOR_builtin_inslh
,
6731 CODE_FOR_builtin_insqh
,
6732 CODE_FOR_builtin_mskbl
,
6733 CODE_FOR_builtin_mskwl
,
6734 CODE_FOR_builtin_mskll
,
6735 CODE_FOR_builtin_mskql
,
6736 CODE_FOR_builtin_mskwh
,
6737 CODE_FOR_builtin_msklh
,
6738 CODE_FOR_builtin_mskqh
,
6739 CODE_FOR_umuldi3_highpart
,
6740 CODE_FOR_builtin_zap
,
6741 CODE_FOR_builtin_zapnot
,
6742 CODE_FOR_builtin_amask
,
6743 CODE_FOR_builtin_implver
,
6744 CODE_FOR_builtin_rpcc
,
6749 CODE_FOR_builtin_minub8
,
6750 CODE_FOR_builtin_minsb8
,
6751 CODE_FOR_builtin_minuw4
,
6752 CODE_FOR_builtin_minsw4
,
6753 CODE_FOR_builtin_maxub8
,
6754 CODE_FOR_builtin_maxsb8
,
6755 CODE_FOR_builtin_maxuw4
,
6756 CODE_FOR_builtin_maxsw4
,
6757 CODE_FOR_builtin_perr
,
6758 CODE_FOR_builtin_pklb
,
6759 CODE_FOR_builtin_pkwb
,
6760 CODE_FOR_builtin_unpkbl
,
6761 CODE_FOR_builtin_unpkbw
,
6764 CODE_FOR_builtin_cttz
,
6765 CODE_FOR_builtin_ctlz
,
6766 CODE_FOR_builtin_ctpop
6769 struct alpha_builtin_def
6772 enum alpha_builtin code
;
6773 unsigned int target_mask
;
6776 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6777 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0 },
6778 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0 }
6781 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6782 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0 },
6783 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
},
6784 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
},
6785 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
},
6786 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
},
6787 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
},
6788 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
},
6789 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
}
6792 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6793 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0 },
6794 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0 },
6795 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0 },
6796 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0 },
6797 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0 },
6798 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0 },
6799 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0 },
6800 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0 },
6801 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0 },
6802 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0 },
6803 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0 },
6804 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0 },
6805 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0 },
6806 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0 },
6807 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0 },
6808 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0 },
6809 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0 },
6810 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0 },
6811 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0 },
6812 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0 },
6813 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0 },
6814 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0 },
6815 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0 },
6816 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0 },
6817 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0 },
6818 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
},
6819 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
},
6820 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
},
6821 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
},
6822 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
},
6823 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
},
6824 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
},
6825 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
},
6826 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
}
6830 alpha_init_builtins ()
6832 const struct alpha_builtin_def
*p
;
6836 ftype
= build_function_type (long_integer_type_node
, void_list_node
);
6838 p
= zero_arg_builtins
;
6839 for (i
= 0; i
< ARRAY_SIZE (zero_arg_builtins
); ++i
, ++p
)
6840 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6841 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6844 ftype
= build_function_type_list (long_integer_type_node
,
6845 long_integer_type_node
, NULL_TREE
);
6847 p
= one_arg_builtins
;
6848 for (i
= 0; i
< ARRAY_SIZE (one_arg_builtins
); ++i
, ++p
)
6849 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6850 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6853 ftype
= build_function_type_list (long_integer_type_node
,
6854 long_integer_type_node
,
6855 long_integer_type_node
, NULL_TREE
);
6857 p
= two_arg_builtins
;
6858 for (i
= 0; i
< ARRAY_SIZE (two_arg_builtins
); ++i
, ++p
)
6859 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6860 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6863 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6864 builtin_function ("__builtin_thread_pointer", ftype
,
6865 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
6868 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6869 builtin_function ("__builtin_set_thread_pointer", ftype
,
6870 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
6874 /* Expand an expression EXP that calls a built-in function,
6875 with result going to TARGET if that's convenient
6876 (and in mode MODE if that's convenient).
6877 SUBTARGET may be used as the target for computing one of EXP's operands.
6878 IGNORE is nonzero if the value is to be ignored. */
6881 alpha_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
6884 rtx subtarget ATTRIBUTE_UNUSED
;
6885 enum machine_mode mode ATTRIBUTE_UNUSED
;
6886 int ignore ATTRIBUTE_UNUSED
;
6890 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6891 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6892 tree arglist
= TREE_OPERAND (exp
, 1);
6893 enum insn_code icode
;
6894 rtx op
[MAX_ARGS
], pat
;
6898 if (fcode
>= ALPHA_BUILTIN_max
)
6899 internal_error ("bad builtin fcode");
6900 icode
= code_for_builtin
[fcode
];
6902 internal_error ("bad builtin fcode");
6904 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6906 for (arglist
= TREE_OPERAND (exp
, 1), arity
= 0;
6908 arglist
= TREE_CHAIN (arglist
), arity
++)
6910 const struct insn_operand_data
*insn_op
;
6912 tree arg
= TREE_VALUE (arglist
);
6913 if (arg
== error_mark_node
)
6915 if (arity
> MAX_ARGS
)
6918 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6920 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
6922 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6923 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6928 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6930 || GET_MODE (target
) != tmode
6931 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6932 target
= gen_reg_rtx (tmode
);
6938 pat
= GEN_FCN (icode
) (target
);
6942 pat
= GEN_FCN (icode
) (target
, op
[0]);
6944 pat
= GEN_FCN (icode
) (op
[0]);
6947 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6962 /* This page contains routines that are used to determine what the function
6963 prologue and epilogue code will do and write them out. */
6965 /* Compute the size of the save area in the stack. */
6967 /* These variables are used for communication between the following functions.
6968 They indicate various things about the current function being compiled
6969 that are used to tell what kind of prologue, epilogue and procedure
6970 descriptior to generate. */
6972 /* Nonzero if we need a stack procedure. */
6973 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
6974 static enum alpha_procedure_types alpha_procedure_type
;
6976 /* Register number (either FP or SP) that is used to unwind the frame. */
6977 static int vms_unwind_regno
;
6979 /* Register number used to save FP. We need not have one for RA since
6980 we don't modify it for register procedures. This is only defined
6981 for register frame procedures. */
6982 static int vms_save_fp_regno
;
6984 /* Register number used to reference objects off our PV. */
6985 static int vms_base_regno
;
6987 /* Compute register masks for saved registers. */
6990 alpha_sa_mask (imaskP
, fmaskP
)
6991 unsigned long *imaskP
;
6992 unsigned long *fmaskP
;
6994 unsigned long imask
= 0;
6995 unsigned long fmask
= 0;
6998 /* Irritatingly, there are two kinds of thunks -- those created with
6999 TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go
7000 through the regular part of the compiler. In the
7001 TARGET_ASM_OUTPUT_MI_THUNK case we don't have valid register life
7002 info, but assemble_start_function wants to output .frame and
7003 .mask directives. */
7004 if (current_function_is_thunk
&& !no_new_pseudos
)
7011 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7012 imask
|= (1L << HARD_FRAME_POINTER_REGNUM
);
7014 /* One for every register we have to save. */
7015 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
7016 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
7017 && regs_ever_live
[i
] && i
!= REG_RA
7018 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
7023 fmask
|= (1L << (i
- 32));
7026 /* We need to restore these for the handler. */
7027 if (current_function_calls_eh_return
)
7030 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
7031 if (regno
== INVALID_REGNUM
)
7033 imask
|= 1L << regno
;
7036 /* If any register spilled, then spill the return address also. */
7037 /* ??? This is required by the Digital stack unwind specification
7038 and isn't needed if we're doing Dwarf2 unwinding. */
7039 if (imask
|| fmask
|| alpha_ra_ever_killed ())
7040 imask
|= (1L << REG_RA
);
7049 unsigned long mask
[2];
7053 alpha_sa_mask (&mask
[0], &mask
[1]);
7055 if (TARGET_ABI_UNICOSMK
)
7057 if (mask
[0] || mask
[1])
7062 for (j
= 0; j
< 2; ++j
)
7063 for (i
= 0; i
< 32; ++i
)
7064 if ((mask
[j
] >> i
) & 1)
7068 if (TARGET_ABI_UNICOSMK
)
7070 /* We might not need to generate a frame if we don't make any calls
7071 (including calls to __T3E_MISMATCH if this is a vararg function),
7072 don't have any local variables which require stack slots, don't
7073 use alloca and have not determined that we need a frame for other
7076 alpha_procedure_type
7077 = (sa_size
|| get_frame_size() != 0
7078 || current_function_outgoing_args_size
7079 || current_function_stdarg
|| current_function_calls_alloca
7080 || frame_pointer_needed
)
7081 ? PT_STACK
: PT_REGISTER
;
7083 /* Always reserve space for saving callee-saved registers if we
7084 need a frame as required by the calling convention. */
7085 if (alpha_procedure_type
== PT_STACK
)
7088 else if (TARGET_ABI_OPEN_VMS
)
7090 /* Start by assuming we can use a register procedure if we don't
7091 make any calls (REG_RA not used) or need to save any
7092 registers and a stack procedure if we do. */
7093 if ((mask
[0] >> REG_RA
) & 1)
7094 alpha_procedure_type
= PT_STACK
;
7095 else if (get_frame_size() != 0)
7096 alpha_procedure_type
= PT_REGISTER
;
7098 alpha_procedure_type
= PT_NULL
;
7100 /* Don't reserve space for saving FP & RA yet. Do that later after we've
7101 made the final decision on stack procedure vs register procedure. */
7102 if (alpha_procedure_type
== PT_STACK
)
7105 /* Decide whether to refer to objects off our PV via FP or PV.
7106 If we need FP for something else or if we receive a nonlocal
7107 goto (which expects PV to contain the value), we must use PV.
7108 Otherwise, start by assuming we can use FP. */
7111 = (frame_pointer_needed
7112 || current_function_has_nonlocal_label
7113 || alpha_procedure_type
== PT_STACK
7114 || current_function_outgoing_args_size
)
7115 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
7117 /* If we want to copy PV into FP, we need to find some register
7118 in which to save FP. */
7120 vms_save_fp_regno
= -1;
7121 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
7122 for (i
= 0; i
< 32; i
++)
7123 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
7124 vms_save_fp_regno
= i
;
7126 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
7127 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
7128 else if (alpha_procedure_type
== PT_NULL
)
7129 vms_base_regno
= REG_PV
;
7131 /* Stack unwinding should be done via FP unless we use it for PV. */
7132 vms_unwind_regno
= (vms_base_regno
== REG_PV
7133 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
7135 /* If this is a stack procedure, allow space for saving FP and RA. */
7136 if (alpha_procedure_type
== PT_STACK
)
7141 /* Our size must be even (multiple of 16 bytes). */
7150 alpha_pv_save_size ()
7153 return alpha_procedure_type
== PT_STACK
? 8 : 0;
7160 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
7163 #if TARGET_ABI_OPEN_VMS
7165 const struct attribute_spec vms_attribute_table
[] =
7167 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
7168 { "overlaid", 0, 0, true, false, false, NULL
},
7169 { "global", 0, 0, true, false, false, NULL
},
7170 { "initialize", 0, 0, true, false, false, NULL
},
7171 { NULL
, 0, 0, false, false, false, NULL
}
7177 find_lo_sum_using_gp (px
, data
)
7179 void *data ATTRIBUTE_UNUSED
;
7181 return GET_CODE (*px
) == LO_SUM
&& XEXP (*px
, 0) == pic_offset_table_rtx
;
7185 alpha_find_lo_sum_using_gp (insn
)
7188 return for_each_rtx (&PATTERN (insn
), find_lo_sum_using_gp
, NULL
) > 0;
7192 alpha_does_function_need_gp ()
7196 /* The GP being variable is an OSF abi thing. */
7197 if (! TARGET_ABI_OSF
)
7200 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7203 if (current_function_is_thunk
)
7206 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
7207 Even if we are a static function, we still need to do this in case
7208 our address is taken and passed to something like qsort. */
7210 push_topmost_sequence ();
7211 insn
= get_insns ();
7212 pop_topmost_sequence ();
7214 for (; insn
; insn
= NEXT_INSN (insn
))
7216 && GET_CODE (PATTERN (insn
)) != USE
7217 && GET_CODE (PATTERN (insn
)) != CLOBBER
7218 && get_attr_usegp (insn
))
7224 /* Write a version stamp. Don't write anything if we are running as a
7225 cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
7232 alpha_write_verstamp (file
)
7233 FILE *file ATTRIBUTE_UNUSED
;
7236 fprintf (file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
7240 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7244 set_frame_related_p ()
7246 rtx seq
= get_insns ();
7257 while (insn
!= NULL_RTX
)
7259 RTX_FRAME_RELATED_P (insn
) = 1;
7260 insn
= NEXT_INSN (insn
);
7262 seq
= emit_insn (seq
);
7266 seq
= emit_insn (seq
);
7267 RTX_FRAME_RELATED_P (seq
) = 1;
7272 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7274 /* Write function prologue. */
7276 /* On vms we have two kinds of functions:
7278 - stack frame (PROC_STACK)
7279 these are 'normal' functions with local vars and which are
7280 calling other functions
7281 - register frame (PROC_REGISTER)
7282 keeps all data in registers, needs no stack
7284 We must pass this to the assembler so it can generate the
7285 proper pdsc (procedure descriptor)
7286 This is done with the '.pdesc' command.
7288 On not-vms, we don't really differentiate between the two, as we can
7289 simply allocate stack without saving registers. */
7292 alpha_expand_prologue ()
7294 /* Registers to save. */
7295 unsigned long imask
= 0;
7296 unsigned long fmask
= 0;
7297 /* Stack space needed for pushing registers clobbered by us. */
7298 HOST_WIDE_INT sa_size
;
7299 /* Complete stack size needed. */
7300 HOST_WIDE_INT frame_size
;
7301 /* Offset from base reg to register save area. */
7302 HOST_WIDE_INT reg_offset
;
7306 sa_size
= alpha_sa_size ();
7308 frame_size
= get_frame_size ();
7309 if (TARGET_ABI_OPEN_VMS
)
7310 frame_size
= ALPHA_ROUND (sa_size
7311 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7313 + current_function_pretend_args_size
);
7314 else if (TARGET_ABI_UNICOSMK
)
7315 /* We have to allocate space for the DSIB if we generate a frame. */
7316 frame_size
= ALPHA_ROUND (sa_size
7317 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7318 + ALPHA_ROUND (frame_size
7319 + current_function_outgoing_args_size
);
7321 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7323 + ALPHA_ROUND (frame_size
7324 + current_function_pretend_args_size
));
7326 if (TARGET_ABI_OPEN_VMS
)
7329 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7331 alpha_sa_mask (&imask
, &fmask
);
7333 /* Emit an insn to reload GP, if needed. */
7336 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7337 if (alpha_function_needs_gp
)
7338 emit_insn (gen_prologue_ldgp ());
7341 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7342 the call to mcount ourselves, rather than having the linker do it
7343 magically in response to -pg. Since _mcount has special linkage,
7344 don't represent the call as a call. */
7345 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7346 emit_insn (gen_prologue_mcount ());
7348 if (TARGET_ABI_UNICOSMK
)
7349 unicosmk_gen_dsib (&imask
);
7351 /* Adjust the stack by the frame size. If the frame size is > 4096
7352 bytes, we need to be sure we probe somewhere in the first and last
7353 4096 bytes (we can probably get away without the latter test) and
7354 every 8192 bytes in between. If the frame size is > 32768, we
7355 do this in a loop. Otherwise, we generate the explicit probe
7358 Note that we are only allowed to adjust sp once in the prologue. */
7360 if (frame_size
<= 32768)
7362 if (frame_size
> 4096)
7367 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7370 while ((probed
+= 8192) < frame_size
);
7372 /* We only have to do this probe if we aren't saving registers. */
7373 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
7374 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
7377 if (frame_size
!= 0)
7378 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7379 GEN_INT (TARGET_ABI_UNICOSMK
7385 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7386 number of 8192 byte blocks to probe. We then probe each block
7387 in the loop and then set SP to the proper location. If the
7388 amount remaining is > 4096, we have to do one more probe if we
7389 are not saving any registers. */
7391 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
7392 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
7393 rtx ptr
= gen_rtx_REG (DImode
, 22);
7394 rtx count
= gen_rtx_REG (DImode
, 23);
7397 emit_move_insn (count
, GEN_INT (blocks
));
7398 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7399 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7401 /* Because of the difficulty in emitting a new basic block this
7402 late in the compilation, generate the loop as a single insn. */
7403 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7405 if (leftover
> 4096 && sa_size
== 0)
7407 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7408 MEM_VOLATILE_P (last
) = 1;
7409 emit_move_insn (last
, const0_rtx
);
7412 if (TARGET_ABI_WINDOWS_NT
)
7414 /* For NT stack unwind (done by 'reverse execution'), it's
7415 not OK to take the result of a loop, even though the value
7416 is already in ptr, so we reload it via a single operation
7417 and subtract it to sp.
7419 Yes, that's correct -- we have to reload the whole constant
7420 into a temporary via ldah+lda then subtract from sp. To
7421 ensure we get ldah+lda, we use a special pattern. */
7423 HOST_WIDE_INT lo
, hi
;
7424 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7425 hi
= frame_size
- lo
;
7427 emit_move_insn (ptr
, GEN_INT (hi
));
7428 emit_insn (gen_nt_lda (ptr
, GEN_INT (lo
)));
7429 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7434 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7435 GEN_INT (-leftover
)));
7438 /* This alternative is special, because the DWARF code cannot
7439 possibly intuit through the loop above. So we invent this
7440 note it looks at instead. */
7441 RTX_FRAME_RELATED_P (seq
) = 1;
7443 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7444 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7445 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7446 GEN_INT (TARGET_ABI_UNICOSMK
7452 if (!TARGET_ABI_UNICOSMK
)
7454 /* Cope with very large offsets to the register save area. */
7455 sa_reg
= stack_pointer_rtx
;
7456 if (reg_offset
+ sa_size
> 0x8000)
7458 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7461 if (low
+ sa_size
<= 0x8000)
7462 bias
= reg_offset
- low
, reg_offset
= low
;
7464 bias
= reg_offset
, reg_offset
= 0;
7466 sa_reg
= gen_rtx_REG (DImode
, 24);
7467 FRP (emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
,
7471 /* Save regs in stack order. Beginning with VMS PV. */
7472 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7474 mem
= gen_rtx_MEM (DImode
, stack_pointer_rtx
);
7475 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7476 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_PV
)));
7479 /* Save register RA next. */
7480 if (imask
& (1L << REG_RA
))
7482 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7483 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7484 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
7485 imask
&= ~(1L << REG_RA
);
7489 /* Now save any other registers required to be saved. */
7490 for (i
= 0; i
< 32; i
++)
7491 if (imask
& (1L << i
))
7493 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7494 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7495 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7499 for (i
= 0; i
< 32; i
++)
7500 if (fmask
& (1L << i
))
7502 mem
= gen_rtx_MEM (DFmode
, plus_constant (sa_reg
, reg_offset
));
7503 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7504 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7508 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7510 /* The standard frame on the T3E includes space for saving registers.
7511 We just have to use it. We don't have to save the return address and
7512 the old frame pointer here - they are saved in the DSIB. */
7515 for (i
= 9; i
< 15; i
++)
7516 if (imask
& (1L << i
))
7518 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7520 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7521 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7524 for (i
= 2; i
< 10; i
++)
7525 if (fmask
& (1L << i
))
7527 mem
= gen_rtx_MEM (DFmode
, plus_constant (hard_frame_pointer_rtx
,
7529 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7530 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7535 if (TARGET_ABI_OPEN_VMS
)
7537 if (alpha_procedure_type
== PT_REGISTER
)
7538 /* Register frame procedures save the fp.
7539 ?? Ought to have a dwarf2 save for this. */
7540 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7541 hard_frame_pointer_rtx
);
7543 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7544 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7545 gen_rtx_REG (DImode
, REG_PV
)));
7547 if (alpha_procedure_type
!= PT_NULL
7548 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7549 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7551 /* If we have to allocate space for outgoing args, do it now. */
7552 if (current_function_outgoing_args_size
!= 0)
7555 plus_constant (hard_frame_pointer_rtx
,
7557 (current_function_outgoing_args_size
)))));
7559 else if (!TARGET_ABI_UNICOSMK
)
7561 /* If we need a frame pointer, set it from the stack pointer. */
7562 if (frame_pointer_needed
)
7564 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7565 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7567 /* This must always be the last instruction in the
7568 prologue, thus we emit a special move + clobber. */
7569 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7570 stack_pointer_rtx
, sa_reg
)));
7574 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7575 the prologue, for exception handling reasons, we cannot do this for
7576 any insn that might fault. We could prevent this for mems with a
7577 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7578 have to prevent all such scheduling with a blockage.
7580 Linux, on the other hand, never bothered to implement OSF/1's
7581 exception handling, and so doesn't care about such things. Anyone
7582 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7584 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7585 emit_insn (gen_blockage ());
7588 /* Output the textual info surrounding the prologue. */
7591 alpha_start_function (file
, fnname
, decl
)
7594 tree decl ATTRIBUTE_UNUSED
;
7596 unsigned long imask
= 0;
7597 unsigned long fmask
= 0;
7598 /* Stack space needed for pushing registers clobbered by us. */
7599 HOST_WIDE_INT sa_size
;
7600 /* Complete stack size needed. */
7601 HOST_WIDE_INT frame_size
;
7602 /* Offset from base reg to register save area. */
7603 HOST_WIDE_INT reg_offset
;
7604 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7607 /* Don't emit an extern directive for functions defined in the same file. */
7608 if (TARGET_ABI_UNICOSMK
)
7611 name_tree
= get_identifier (fnname
);
7612 TREE_ASM_WRITTEN (name_tree
) = 1;
7615 alpha_fnname
= fnname
;
7616 sa_size
= alpha_sa_size ();
7618 frame_size
= get_frame_size ();
7619 if (TARGET_ABI_OPEN_VMS
)
7620 frame_size
= ALPHA_ROUND (sa_size
7621 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7623 + current_function_pretend_args_size
);
7624 else if (TARGET_ABI_UNICOSMK
)
7625 frame_size
= ALPHA_ROUND (sa_size
7626 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7627 + ALPHA_ROUND (frame_size
7628 + current_function_outgoing_args_size
);
7630 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7632 + ALPHA_ROUND (frame_size
7633 + current_function_pretend_args_size
));
7635 if (TARGET_ABI_OPEN_VMS
)
7638 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7640 alpha_sa_mask (&imask
, &fmask
);
7642 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7643 We have to do that before the .ent directive as we cannot switch
7644 files within procedures with native ecoff because line numbers are
7645 linked to procedure descriptors.
7646 Outputting the lineno helps debugging of one line functions as they
7647 would otherwise get no line number at all. Please note that we would
7648 like to put out last_linenum from final.c, but it is not accessible. */
7650 if (write_symbols
== SDB_DEBUG
)
7652 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7653 ASM_OUTPUT_SOURCE_FILENAME (file
,
7654 DECL_SOURCE_FILE (current_function_decl
));
7656 #ifdef ASM_OUTPUT_SOURCE_LINE
7657 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7658 ASM_OUTPUT_SOURCE_LINE (file
,
7659 DECL_SOURCE_LINE (current_function_decl
));
7663 /* Issue function start and label. */
7664 if (TARGET_ABI_OPEN_VMS
7665 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
7667 fputs ("\t.ent ", file
);
7668 assemble_name (file
, fnname
);
7671 /* If the function needs GP, we'll write the "..ng" label there.
7672 Otherwise, do it here. */
7674 && ! alpha_function_needs_gp
7675 && ! current_function_is_thunk
)
7678 assemble_name (file
, fnname
);
7679 fputs ("..ng:\n", file
);
7683 strcpy (entry_label
, fnname
);
7684 if (TARGET_ABI_OPEN_VMS
)
7685 strcat (entry_label
, "..en");
7687 /* For public functions, the label must be globalized by appending an
7688 additional colon. */
7689 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
7690 strcat (entry_label
, ":");
7692 ASM_OUTPUT_LABEL (file
, entry_label
);
7693 inside_function
= TRUE
;
7695 if (TARGET_ABI_OPEN_VMS
)
7696 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7698 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7699 && !flag_inhibit_size_directive
)
7701 /* Set flags in procedure descriptor to request IEEE-conformant
7702 math-library routines. The value we set it to is PDSC_EXC_IEEE
7703 (/usr/include/pdsc.h). */
7704 fputs ("\t.eflag 48\n", file
);
7707 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7708 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
7709 alpha_arg_offset
= -frame_size
+ 48;
7711 /* Describe our frame. If the frame size is larger than an integer,
7712 print it as zero to avoid an assembler error. We won't be
7713 properly describing such a frame, but that's the best we can do. */
7714 if (TARGET_ABI_UNICOSMK
)
7716 else if (TARGET_ABI_OPEN_VMS
)
7718 fprintf (file
, "\t.frame $%d,", vms_unwind_regno
);
7719 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7720 frame_size
>= ((HOST_WIDE_INT
) 1 << 31) ? 0 : frame_size
);
7721 fputs (",$26,", file
);
7722 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, reg_offset
);
7725 else if (!flag_inhibit_size_directive
)
7727 fprintf (file
, "\t.frame $%d,",
7728 (frame_pointer_needed
7729 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
));
7730 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7731 frame_size
>= (1l << 31) ? 0 : frame_size
);
7732 fprintf (file
, ",$26,%d\n", current_function_pretend_args_size
);
7735 /* Describe which registers were spilled. */
7736 if (TARGET_ABI_UNICOSMK
)
7738 else if (TARGET_ABI_OPEN_VMS
)
7741 /* ??? Does VMS care if mask contains ra? The old code didn't
7742 set it, so I don't here. */
7743 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1L << REG_RA
));
7745 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7746 if (alpha_procedure_type
== PT_REGISTER
)
7747 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7749 else if (!flag_inhibit_size_directive
)
7753 fprintf (file
, "\t.mask 0x%lx,", imask
);
7754 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7755 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
7758 for (i
= 0; i
< 32; ++i
)
7759 if (imask
& (1L << i
))
7765 fprintf (file
, "\t.fmask 0x%lx,", fmask
);
7766 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7767 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
7772 #if TARGET_ABI_OPEN_VMS
7773 /* Ifdef'ed cause link_section are only available then. */
7774 readonly_data_section ();
7775 fprintf (file
, "\t.align 3\n");
7776 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
7777 fputs ("\t.ascii \"", file
);
7778 assemble_name (file
, fnname
);
7779 fputs ("\\0\"\n", file
);
7780 alpha_need_linkage (fnname
, 1);
7785 /* Emit the .prologue note at the scheduled end of the prologue. */
7788 alpha_output_function_end_prologue (file
)
7791 if (TARGET_ABI_UNICOSMK
)
7793 else if (TARGET_ABI_OPEN_VMS
)
7794 fputs ("\t.prologue\n", file
);
7795 else if (TARGET_ABI_WINDOWS_NT
)
7796 fputs ("\t.prologue 0\n", file
);
7797 else if (!flag_inhibit_size_directive
)
7798 fprintf (file
, "\t.prologue %d\n",
7799 alpha_function_needs_gp
|| current_function_is_thunk
);
7802 /* Write function epilogue. */
7804 /* ??? At some point we will want to support full unwind, and so will
7805 need to mark the epilogue as well. At the moment, we just confuse
7808 #define FRP(exp) exp
7811 alpha_expand_epilogue ()
7813 /* Registers to save. */
7814 unsigned long imask
= 0;
7815 unsigned long fmask
= 0;
7816 /* Stack space needed for pushing registers clobbered by us. */
7817 HOST_WIDE_INT sa_size
;
7818 /* Complete stack size needed. */
7819 HOST_WIDE_INT frame_size
;
7820 /* Offset from base reg to register save area. */
7821 HOST_WIDE_INT reg_offset
;
7822 int fp_is_frame_pointer
, fp_offset
;
7823 rtx sa_reg
, sa_reg_exp
= NULL
;
7824 rtx sp_adj1
, sp_adj2
, mem
;
7828 sa_size
= alpha_sa_size ();
7830 frame_size
= get_frame_size ();
7831 if (TARGET_ABI_OPEN_VMS
)
7832 frame_size
= ALPHA_ROUND (sa_size
7833 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7835 + current_function_pretend_args_size
);
7836 else if (TARGET_ABI_UNICOSMK
)
7837 frame_size
= ALPHA_ROUND (sa_size
7838 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7839 + ALPHA_ROUND (frame_size
7840 + current_function_outgoing_args_size
);
7842 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7844 + ALPHA_ROUND (frame_size
7845 + current_function_pretend_args_size
));
7847 if (TARGET_ABI_OPEN_VMS
)
7849 if (alpha_procedure_type
== PT_STACK
)
7855 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7857 alpha_sa_mask (&imask
, &fmask
);
7860 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7861 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
7863 sa_reg
= stack_pointer_rtx
;
7865 if (current_function_calls_eh_return
)
7866 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7870 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
7872 /* If we have a frame pointer, restore SP from it. */
7873 if ((TARGET_ABI_OPEN_VMS
7874 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7875 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
7876 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7878 /* Cope with very large offsets to the register save area. */
7879 if (reg_offset
+ sa_size
> 0x8000)
7881 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7884 if (low
+ sa_size
<= 0x8000)
7885 bias
= reg_offset
- low
, reg_offset
= low
;
7887 bias
= reg_offset
, reg_offset
= 0;
7889 sa_reg
= gen_rtx_REG (DImode
, 22);
7890 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
7892 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
7895 /* Restore registers in order, excepting a true frame pointer. */
7897 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7899 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7900 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7903 imask
&= ~(1L << REG_RA
);
7905 for (i
= 0; i
< 32; ++i
)
7906 if (imask
& (1L << i
))
7908 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
7909 fp_offset
= reg_offset
;
7912 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
7913 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7914 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7919 for (i
= 0; i
< 32; ++i
)
7920 if (fmask
& (1L << i
))
7922 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
7923 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7924 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7928 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7930 /* Restore callee-saved general-purpose registers. */
7934 for (i
= 9; i
< 15; i
++)
7935 if (imask
& (1L << i
))
7937 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7939 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7940 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7944 for (i
= 2; i
< 10; i
++)
7945 if (fmask
& (1L << i
))
7947 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
7949 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7950 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7954 /* Restore the return address from the DSIB. */
7956 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
7957 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7958 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7961 if (frame_size
|| eh_ofs
)
7963 sp_adj1
= stack_pointer_rtx
;
7967 sp_adj1
= gen_rtx_REG (DImode
, 23);
7968 emit_move_insn (sp_adj1
,
7969 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
7972 /* If the stack size is large, begin computation into a temporary
7973 register so as not to interfere with a potential fp restore,
7974 which must be consecutive with an SP restore. */
7975 if (frame_size
< 32768
7976 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
7977 sp_adj2
= GEN_INT (frame_size
);
7978 else if (TARGET_ABI_UNICOSMK
)
7980 sp_adj1
= gen_rtx_REG (DImode
, 23);
7981 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
7982 sp_adj2
= const0_rtx
;
7984 else if (frame_size
< 0x40007fffL
)
7986 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7988 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
7989 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
7993 sp_adj1
= gen_rtx_REG (DImode
, 23);
7994 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
7996 sp_adj2
= GEN_INT (low
);
8000 rtx tmp
= gen_rtx_REG (DImode
, 23);
8001 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
8004 /* We can't drop new things to memory this late, afaik,
8005 so build it up by pieces. */
8006 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
8007 -(frame_size
< 0)));
8013 /* From now on, things must be in order. So emit blockages. */
8015 /* Restore the frame pointer. */
8016 if (TARGET_ABI_UNICOSMK
)
8018 emit_insn (gen_blockage ());
8019 mem
= gen_rtx_MEM (DImode
,
8020 plus_constant (hard_frame_pointer_rtx
, -16));
8021 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8022 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
8024 else if (fp_is_frame_pointer
)
8026 emit_insn (gen_blockage ());
8027 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
8028 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8029 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
8031 else if (TARGET_ABI_OPEN_VMS
)
8033 emit_insn (gen_blockage ());
8034 FRP (emit_move_insn (hard_frame_pointer_rtx
,
8035 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
8038 /* Restore the stack pointer. */
8039 emit_insn (gen_blockage ());
8040 if (sp_adj2
== const0_rtx
)
8041 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
8043 FRP (emit_move_insn (stack_pointer_rtx
,
8044 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
8048 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
8050 emit_insn (gen_blockage ());
8051 FRP (emit_move_insn (hard_frame_pointer_rtx
,
8052 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
8054 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
8056 /* Decrement the frame pointer if the function does not have a
8059 emit_insn (gen_blockage ());
8060 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8061 hard_frame_pointer_rtx
, GEN_INT (-1))));
8066 /* Output the rest of the textual info surrounding the epilogue. */
8069 alpha_end_function (file
, fnname
, decl
)
8074 /* End the function. */
8075 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
8077 fputs ("\t.end ", file
);
8078 assemble_name (file
, fnname
);
8081 inside_function
= FALSE
;
8083 #if TARGET_ABI_OPEN_VMS
8084 alpha_write_linkage (file
, fnname
, decl
);
8087 /* Show that we know this function if it is called again.
8088 This is only meaningful for symbols that bind locally. */
8089 if ((*targetm
.binds_local_p
) (decl
))
8091 rtx symbol
= XEXP (DECL_RTL (decl
), 0);
8093 /* Mark whether the decl is "near". See the commentary in
8094 alpha_encode_section_info wrt the .text section. */
8095 if (decl_in_text_section (decl
))
8098 /* Mark whether the decl shares a GP with other functions
8099 in this unit of translation. This is trivially true of
8101 SYMBOL_REF_FLAG (symbol
) = 1;
8104 /* Output jump tables and the static subroutine information block. */
8105 if (TARGET_ABI_UNICOSMK
)
8107 unicosmk_output_ssib (file
, fnname
);
8108 unicosmk_output_deferred_case_vectors (file
);
8113 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
8115 In order to avoid the hordes of differences between generated code
8116 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
8117 lots of code loading up large constants, generate rtl and emit it
8118 instead of going straight to text.
8120 Not sure why this idea hasn't been explored before... */
8123 alpha_output_mi_thunk_osf (file
, thunk_fndecl
, delta
, vcall_offset
, function
)
8125 tree thunk_fndecl ATTRIBUTE_UNUSED
;
8126 HOST_WIDE_INT delta
;
8127 HOST_WIDE_INT vcall_offset
;
8130 HOST_WIDE_INT hi
, lo
;
8131 rtx
this, insn
, funexp
;
8133 /* We always require a valid GP. */
8134 emit_insn (gen_prologue_ldgp ());
8135 emit_note (NULL
, NOTE_INSN_PROLOGUE_END
);
8137 /* Find the "this" pointer. If the function returns a structure,
8138 the structure return pointer is in $16. */
8139 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
))))
8140 this = gen_rtx_REG (Pmode
, 17);
8142 this = gen_rtx_REG (Pmode
, 16);
8144 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
8145 entire constant for the add. */
8146 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
8147 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8148 if (hi
+ lo
== delta
)
8151 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
8153 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
8157 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
8158 delta
, -(delta
< 0));
8159 emit_insn (gen_adddi3 (this, this, tmp
));
8162 /* Add a delta stored in the vtable at VCALL_OFFSET. */
8167 tmp
= gen_rtx_REG (Pmode
, 0);
8168 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
8170 lo
= ((vcall_offset
& 0xffff) ^ 0x8000) - 0x8000;
8171 hi
= (((vcall_offset
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8172 if (hi
+ lo
== vcall_offset
)
8175 emit_insn (gen_adddi3 (tmp
, tmp
, GEN_INT (hi
)));
8179 tmp2
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 1),
8180 vcall_offset
, -(vcall_offset
< 0));
8181 emit_insn (gen_adddi3 (tmp
, tmp
, tmp2
));
8185 tmp2
= gen_rtx_PLUS (Pmode
, tmp
, GEN_INT (lo
));
8188 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp2
));
8190 emit_insn (gen_adddi3 (this, this, tmp
));
8193 /* Generate a tail call to the target function. */
8194 if (! TREE_USED (function
))
8196 assemble_external (function
);
8197 TREE_USED (function
) = 1;
8199 funexp
= XEXP (DECL_RTL (function
), 0);
8200 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8201 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
8202 SIBLING_CALL_P (insn
) = 1;
8204 /* Run just enough of rest_of_compilation to get the insns emitted.
8205 There's not really enough bulk here to make other passes such as
8206 instruction scheduling worth while. Note that use_thunk calls
8207 assemble_start_function and assemble_end_function. */
8208 insn
= get_insns ();
8209 shorten_branches (insn
);
8210 final_start_function (insn
, file
, 1);
8211 final (insn
, file
, 1, 0);
8212 final_end_function ();
8214 #endif /* TARGET_ABI_OSF */
8216 /* Debugging support. */
8220 /* Count the number of sdb related labels are generated (to find block
8221 start and end boundaries). */
8223 int sdb_label_count
= 0;
8225 /* Next label # for each statement. */
8227 static int sym_lineno
= 0;
8229 /* Count the number of .file directives, so that .loc is up to date. */
8231 static int num_source_filenames
= 0;
8233 /* Name of the file containing the current function. */
8235 static const char *current_function_file
= "";
8237 /* Offsets to alpha virtual arg/local debugging pointers. */
8239 long alpha_arg_offset
;
8240 long alpha_auto_offset
;
8242 /* Emit a new filename to a stream. */
8245 alpha_output_filename (stream
, name
)
8249 static int first_time
= TRUE
;
8250 char ltext_label_name
[100];
8255 ++num_source_filenames
;
8256 current_function_file
= name
;
8257 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8258 output_quoted_string (stream
, name
);
8259 fprintf (stream
, "\n");
8260 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
8261 fprintf (stream
, "\t#@stabs\n");
8264 else if (write_symbols
== DBX_DEBUG
)
8266 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
8267 fprintf (stream
, "%s", ASM_STABS_OP
);
8268 output_quoted_string (stream
, name
);
8269 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
8272 else if (name
!= current_function_file
8273 && strcmp (name
, current_function_file
) != 0)
8275 if (inside_function
&& ! TARGET_GAS
)
8276 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
8279 ++num_source_filenames
;
8280 current_function_file
= name
;
8281 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8284 output_quoted_string (stream
, name
);
8285 fprintf (stream
, "\n");
8289 /* Emit a linenumber to a stream. */
8292 alpha_output_lineno (stream
, line
)
8296 if (write_symbols
== DBX_DEBUG
)
8298 /* mips-tfile doesn't understand .stabd directives. */
8300 fprintf (stream
, "$LM%d:\n%s%d,0,%d,$LM%d\n",
8301 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
8304 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
8307 /* Structure to show the current status of registers and memory. */
8309 struct shadow_summary
8312 unsigned int i
: 31; /* Mask of int regs */
8313 unsigned int fp
: 31; /* Mask of fp regs */
8314 unsigned int mem
: 1; /* mem == imem | fpmem */
8318 static void summarize_insn
PARAMS ((rtx
, struct shadow_summary
*, int));
8319 static void alpha_handle_trap_shadows
PARAMS ((rtx
));
8321 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8322 to the summary structure. SET is nonzero if the insn is setting the
8323 object, otherwise zero. */
8326 summarize_insn (x
, sum
, set
)
8328 struct shadow_summary
*sum
;
8331 const char *format_ptr
;
8337 switch (GET_CODE (x
))
8339 /* ??? Note that this case would be incorrect if the Alpha had a
8340 ZERO_EXTRACT in SET_DEST. */
8342 summarize_insn (SET_SRC (x
), sum
, 0);
8343 summarize_insn (SET_DEST (x
), sum
, 1);
8347 summarize_insn (XEXP (x
, 0), sum
, 1);
8351 summarize_insn (XEXP (x
, 0), sum
, 0);
8355 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8356 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8360 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8361 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8365 summarize_insn (SUBREG_REG (x
), sum
, 0);
8370 int regno
= REGNO (x
);
8371 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8373 if (regno
== 31 || regno
== 63)
8379 sum
->defd
.i
|= mask
;
8381 sum
->defd
.fp
|= mask
;
8386 sum
->used
.i
|= mask
;
8388 sum
->used
.fp
|= mask
;
8399 /* Find the regs used in memory address computation: */
8400 summarize_insn (XEXP (x
, 0), sum
, 0);
8403 case CONST_INT
: case CONST_DOUBLE
:
8404 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8405 case SCRATCH
: case ASM_INPUT
:
8408 /* Handle common unary and binary ops for efficiency. */
8409 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8410 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8411 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8412 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8413 case NE
: case EQ
: case GE
: case GT
: case LE
:
8414 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8415 summarize_insn (XEXP (x
, 0), sum
, 0);
8416 summarize_insn (XEXP (x
, 1), sum
, 0);
8419 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8420 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8421 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8422 case SQRT
: case FFS
:
8423 summarize_insn (XEXP (x
, 0), sum
, 0);
8427 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8428 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8429 switch (format_ptr
[i
])
8432 summarize_insn (XEXP (x
, i
), sum
, 0);
8436 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8437 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8449 /* Ensure a sufficient number of `trapb' insns are in the code when
8450 the user requests code with a trap precision of functions or
8453 In naive mode, when the user requests a trap-precision of
8454 "instruction", a trapb is needed after every instruction that may
8455 generate a trap. This ensures that the code is resumption safe but
8458 When optimizations are turned on, we delay issuing a trapb as long
8459 as possible. In this context, a trap shadow is the sequence of
8460 instructions that starts with a (potentially) trap generating
8461 instruction and extends to the next trapb or call_pal instruction
8462 (but GCC never generates call_pal by itself). We can delay (and
8463 therefore sometimes omit) a trapb subject to the following
8466 (a) On entry to the trap shadow, if any Alpha register or memory
8467 location contains a value that is used as an operand value by some
8468 instruction in the trap shadow (live on entry), then no instruction
8469 in the trap shadow may modify the register or memory location.
8471 (b) Within the trap shadow, the computation of the base register
8472 for a memory load or store instruction may not involve using the
8473 result of an instruction that might generate an UNPREDICTABLE
8476 (c) Within the trap shadow, no register may be used more than once
8477 as a destination register. (This is to make life easier for the
8480 (d) The trap shadow may not include any branch instructions. */
8483 alpha_handle_trap_shadows (insns
)
8486 struct shadow_summary shadow
;
8487 int trap_pending
, exception_nesting
;
8491 exception_nesting
= 0;
8494 shadow
.used
.mem
= 0;
8495 shadow
.defd
= shadow
.used
;
8497 for (i
= insns
; i
; i
= NEXT_INSN (i
))
8499 if (GET_CODE (i
) == NOTE
)
8501 switch (NOTE_LINE_NUMBER (i
))
8503 case NOTE_INSN_EH_REGION_BEG
:
8504 exception_nesting
++;
8509 case NOTE_INSN_EH_REGION_END
:
8510 exception_nesting
--;
8515 case NOTE_INSN_EPILOGUE_BEG
:
8516 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8521 else if (trap_pending
)
8523 if (alpha_tp
== ALPHA_TP_FUNC
)
8525 if (GET_CODE (i
) == JUMP_INSN
8526 && GET_CODE (PATTERN (i
)) == RETURN
)
8529 else if (alpha_tp
== ALPHA_TP_INSN
)
8533 struct shadow_summary sum
;
8538 sum
.defd
= sum
.used
;
8540 switch (GET_CODE (i
))
8543 /* Annoyingly, get_attr_trap will abort on these. */
8544 if (GET_CODE (PATTERN (i
)) == USE
8545 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8548 summarize_insn (PATTERN (i
), &sum
, 0);
8550 if ((sum
.defd
.i
& shadow
.defd
.i
)
8551 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8553 /* (c) would be violated */
8557 /* Combine shadow with summary of current insn: */
8558 shadow
.used
.i
|= sum
.used
.i
;
8559 shadow
.used
.fp
|= sum
.used
.fp
;
8560 shadow
.used
.mem
|= sum
.used
.mem
;
8561 shadow
.defd
.i
|= sum
.defd
.i
;
8562 shadow
.defd
.fp
|= sum
.defd
.fp
;
8563 shadow
.defd
.mem
|= sum
.defd
.mem
;
8565 if ((sum
.defd
.i
& shadow
.used
.i
)
8566 || (sum
.defd
.fp
& shadow
.used
.fp
)
8567 || (sum
.defd
.mem
& shadow
.used
.mem
))
8569 /* (a) would be violated (also takes care of (b)) */
8570 if (get_attr_trap (i
) == TRAP_YES
8571 && ((sum
.defd
.i
& sum
.used
.i
)
8572 || (sum
.defd
.fp
& sum
.used
.fp
)))
8591 n
= emit_insn_before (gen_trapb (), i
);
8592 PUT_MODE (n
, TImode
);
8593 PUT_MODE (i
, TImode
);
8597 shadow
.used
.mem
= 0;
8598 shadow
.defd
= shadow
.used
;
8603 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8604 && GET_CODE (i
) == INSN
8605 && GET_CODE (PATTERN (i
)) != USE
8606 && GET_CODE (PATTERN (i
)) != CLOBBER
8607 && get_attr_trap (i
) == TRAP_YES
)
8609 if (optimize
&& !trap_pending
)
8610 summarize_insn (PATTERN (i
), &shadow
, 0);
8616 /* Alpha can only issue instruction groups simultaneously if they are
8617 suitibly aligned. This is very processor-specific. */
8619 enum alphaev4_pipe
{
8626 enum alphaev5_pipe
{
8637 static enum alphaev4_pipe alphaev4_insn_pipe
PARAMS ((rtx
));
8638 static enum alphaev5_pipe alphaev5_insn_pipe
PARAMS ((rtx
));
8639 static rtx alphaev4_next_group
PARAMS ((rtx
, int *, int *));
8640 static rtx alphaev5_next_group
PARAMS ((rtx
, int *, int *));
8641 static rtx alphaev4_next_nop
PARAMS ((int *));
8642 static rtx alphaev5_next_nop
PARAMS ((int *));
8644 static void alpha_align_insns
8645 PARAMS ((rtx
, unsigned int, rtx (*)(rtx
, int *, int *), rtx (*)(int *)));
8647 static enum alphaev4_pipe
8648 alphaev4_insn_pipe (insn
)
8651 if (recog_memoized (insn
) < 0)
8653 if (get_attr_length (insn
) != 4)
8656 switch (get_attr_type (insn
))
8690 static enum alphaev5_pipe
8691 alphaev5_insn_pipe (insn
)
8694 if (recog_memoized (insn
) < 0)
8696 if (get_attr_length (insn
) != 4)
8699 switch (get_attr_type (insn
))
8740 /* IN_USE is a mask of the slots currently filled within the insn group.
8741 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8742 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8744 LEN is, of course, the length of the group in bytes. */
8747 alphaev4_next_group (insn
, pin_use
, plen
)
8749 int *pin_use
, *plen
;
8756 || GET_CODE (PATTERN (insn
)) == CLOBBER
8757 || GET_CODE (PATTERN (insn
)) == USE
)
8762 enum alphaev4_pipe pipe
;
8764 pipe
= alphaev4_insn_pipe (insn
);
8768 /* Force complex instructions to start new groups. */
8772 /* If this is a completely unrecognized insn, its an asm.
8773 We don't know how long it is, so record length as -1 to
8774 signal a needed realignment. */
8775 if (recog_memoized (insn
) < 0)
8778 len
= get_attr_length (insn
);
8782 if (in_use
& EV4_IB0
)
8784 if (in_use
& EV4_IB1
)
8789 in_use
|= EV4_IB0
| EV4_IBX
;
8793 if (in_use
& EV4_IB0
)
8795 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8803 if (in_use
& EV4_IB1
)
8813 /* Haifa doesn't do well scheduling branches. */
8814 if (GET_CODE (insn
) == JUMP_INSN
)
8818 insn
= next_nonnote_insn (insn
);
8820 if (!insn
|| ! INSN_P (insn
))
8823 /* Let Haifa tell us where it thinks insn group boundaries are. */
8824 if (GET_MODE (insn
) == TImode
)
8827 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8832 insn
= next_nonnote_insn (insn
);
8840 /* IN_USE is a mask of the slots currently filled within the insn group.
8841 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8842 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8844 LEN is, of course, the length of the group in bytes. */
8847 alphaev5_next_group (insn
, pin_use
, plen
)
8849 int *pin_use
, *plen
;
8856 || GET_CODE (PATTERN (insn
)) == CLOBBER
8857 || GET_CODE (PATTERN (insn
)) == USE
)
8862 enum alphaev5_pipe pipe
;
8864 pipe
= alphaev5_insn_pipe (insn
);
8868 /* Force complex instructions to start new groups. */
8872 /* If this is a completely unrecognized insn, its an asm.
8873 We don't know how long it is, so record length as -1 to
8874 signal a needed realignment. */
8875 if (recog_memoized (insn
) < 0)
8878 len
= get_attr_length (insn
);
8881 /* ??? Most of the places below, we would like to abort, as
8882 it would indicate an error either in Haifa, or in the
8883 scheduling description. Unfortunately, Haifa never
8884 schedules the last instruction of the BB, so we don't
8885 have an accurate TI bit to go off. */
8887 if (in_use
& EV5_E0
)
8889 if (in_use
& EV5_E1
)
8894 in_use
|= EV5_E0
| EV5_E01
;
8898 if (in_use
& EV5_E0
)
8900 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
8908 if (in_use
& EV5_E1
)
8914 if (in_use
& EV5_FA
)
8916 if (in_use
& EV5_FM
)
8921 in_use
|= EV5_FA
| EV5_FAM
;
8925 if (in_use
& EV5_FA
)
8931 if (in_use
& EV5_FM
)
8944 /* Haifa doesn't do well scheduling branches. */
8945 /* ??? If this is predicted not-taken, slotting continues, except
8946 that no more IBR, FBR, or JSR insns may be slotted. */
8947 if (GET_CODE (insn
) == JUMP_INSN
)
8951 insn
= next_nonnote_insn (insn
);
8953 if (!insn
|| ! INSN_P (insn
))
8956 /* Let Haifa tell us where it thinks insn group boundaries are. */
8957 if (GET_MODE (insn
) == TImode
)
8960 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8965 insn
= next_nonnote_insn (insn
);
8974 alphaev4_next_nop (pin_use
)
8977 int in_use
= *pin_use
;
8980 if (!(in_use
& EV4_IB0
))
8985 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
8990 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
9003 alphaev5_next_nop (pin_use
)
9006 int in_use
= *pin_use
;
9009 if (!(in_use
& EV5_E1
))
9014 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
9019 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
9031 /* The instruction group alignment main loop. */
9034 alpha_align_insns (insns
, max_align
, next_group
, next_nop
)
9036 unsigned int max_align
;
9037 rtx (*next_group
) PARAMS ((rtx
, int *, int *));
9038 rtx (*next_nop
) PARAMS ((int *));
9040 /* ALIGN is the known alignment for the insn group. */
9042 /* OFS is the offset of the current insn in the insn group. */
9044 int prev_in_use
, in_use
, len
;
9047 /* Let shorten branches care for assigning alignments to code labels. */
9048 shorten_branches (insns
);
9050 if (align_functions
< 4)
9052 else if ((unsigned int) align_functions
< max_align
)
9053 align
= align_functions
;
9057 ofs
= prev_in_use
= 0;
9059 if (GET_CODE (i
) == NOTE
)
9060 i
= next_nonnote_insn (i
);
9064 next
= (*next_group
) (i
, &in_use
, &len
);
9066 /* When we see a label, resync alignment etc. */
9067 if (GET_CODE (i
) == CODE_LABEL
)
9069 unsigned int new_align
= 1 << label_to_alignment (i
);
9071 if (new_align
>= align
)
9073 align
= new_align
< max_align
? new_align
: max_align
;
9077 else if (ofs
& (new_align
-1))
9078 ofs
= (ofs
| (new_align
-1)) + 1;
9083 /* Handle complex instructions special. */
9084 else if (in_use
== 0)
9086 /* Asms will have length < 0. This is a signal that we have
9087 lost alignment knowledge. Assume, however, that the asm
9088 will not mis-align instructions. */
9097 /* If the known alignment is smaller than the recognized insn group,
9098 realign the output. */
9099 else if ((int) align
< len
)
9101 unsigned int new_log_align
= len
> 8 ? 4 : 3;
9104 where
= prev
= prev_nonnote_insn (i
);
9105 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
9108 /* Can't realign between a call and its gp reload. */
9109 if (! (TARGET_EXPLICIT_RELOCS
9110 && prev
&& GET_CODE (prev
) == CALL_INSN
))
9112 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
9113 align
= 1 << new_log_align
;
9118 /* If the group won't fit in the same INT16 as the previous,
9119 we need to add padding to keep the group together. Rather
9120 than simply leaving the insn filling to the assembler, we
9121 can make use of the knowledge of what sorts of instructions
9122 were issued in the previous group to make sure that all of
9123 the added nops are really free. */
9124 else if (ofs
+ len
> (int) align
)
9126 int nop_count
= (align
- ofs
) / 4;
9129 /* Insert nops before labels, branches, and calls to truely merge
9130 the execution of the nops with the previous instruction group. */
9131 where
= prev_nonnote_insn (i
);
9134 if (GET_CODE (where
) == CODE_LABEL
)
9136 rtx where2
= prev_nonnote_insn (where
);
9137 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
9140 else if (GET_CODE (where
) == INSN
)
9147 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
9148 while (--nop_count
);
9152 ofs
= (ofs
+ len
) & (align
- 1);
9153 prev_in_use
= in_use
;
9158 /* Machine dependent reorg pass. */
9164 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
9165 alpha_handle_trap_shadows (insns
);
9167 /* Due to the number of extra trapb insns, don't bother fixing up
9168 alignment when trap precision is instruction. Moreover, we can
9169 only do our job when sched2 is run. */
9170 if (optimize
&& !optimize_size
9171 && alpha_tp
!= ALPHA_TP_INSN
9172 && flag_schedule_insns_after_reload
)
9174 if (alpha_cpu
== PROCESSOR_EV4
)
9175 alpha_align_insns (insns
, 8, alphaev4_next_group
, alphaev4_next_nop
);
9176 else if (alpha_cpu
== PROCESSOR_EV5
)
9177 alpha_align_insns (insns
, 16, alphaev5_next_group
, alphaev5_next_nop
);
9181 #ifdef OBJECT_FORMAT_ELF
9183 /* Switch to the section to which we should output X. The only thing
9184 special we do here is to honor small data. */
9187 alpha_elf_select_rtx_section (mode
, x
, align
)
9188 enum machine_mode mode
;
9190 unsigned HOST_WIDE_INT align
;
9192 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
9193 /* ??? Consider using mergable sdata sections. */
9196 default_elf_select_rtx_section (mode
, x
, align
);
9199 #endif /* OBJECT_FORMAT_ELF */
9201 /* Structure to collect function names for final output in link section. */
9202 /* Note that items marked with GTY can't be ifdef'ed out. */
9204 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
9205 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
9207 struct alpha_links
GTY(())
9211 enum links_kind lkind
;
9212 enum reloc_kind rkind
;
9215 struct alpha_funcs
GTY(())
9218 splay_tree
GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9222 static GTY ((param1_is (char *), param2_is (struct alpha_links
*)))
9223 splay_tree alpha_links_tree
;
9224 static GTY ((param1_is (tree
), param2_is (struct alpha_funcs
*)))
9225 splay_tree alpha_funcs_tree
;
9227 static GTY(()) int alpha_funcs_num
;
9229 #if TARGET_ABI_OPEN_VMS
9231 /* Return the VMS argument type corresponding to MODE. */
9234 alpha_arg_type (mode
)
9235 enum machine_mode mode
;
9240 return TARGET_FLOAT_VAX
? FF
: FS
;
9242 return TARGET_FLOAT_VAX
? FD
: FT
;
9248 /* Return an rtx for an integer representing the VMS Argument Information
9252 alpha_arg_info_reg_val (cum
)
9253 CUMULATIVE_ARGS cum
;
9255 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
9258 for (i
= 0; i
< 6; i
++)
9259 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
9261 return GEN_INT (regval
);
9264 /* Make (or fake) .linkage entry for function call.
9266 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9268 Return an SYMBOL_REF rtx for the linkage. */
9271 alpha_need_linkage (name
, is_local
)
9275 splay_tree_node node
;
9276 struct alpha_links
*al
;
9283 struct alpha_funcs
*cfaf
;
9285 if (!alpha_funcs_tree
)
9286 alpha_funcs_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
)
9287 splay_tree_compare_pointers
);
9289 cfaf
= (struct alpha_funcs
*) ggc_alloc (sizeof (struct alpha_funcs
));
9292 cfaf
->num
= ++alpha_funcs_num
;
9294 splay_tree_insert (alpha_funcs_tree
,
9295 (splay_tree_key
) current_function_decl
,
9296 (splay_tree_value
) cfaf
);
9299 if (alpha_links_tree
)
9301 /* Is this name already defined? */
9303 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9306 al
= (struct alpha_links
*) node
->value
;
9309 /* Defined here but external assumed. */
9310 if (al
->lkind
== KIND_EXTERN
)
9311 al
->lkind
= KIND_LOCAL
;
9315 /* Used here but unused assumed. */
9316 if (al
->lkind
== KIND_UNUSED
)
9317 al
->lkind
= KIND_LOCAL
;
9323 alpha_links_tree
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9325 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9326 name
= ggc_strdup (name
);
9328 /* Assume external if no definition. */
9329 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9331 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9332 get_identifier (name
);
9334 /* Construct a SYMBOL_REF for us to call. */
9336 size_t name_len
= strlen (name
);
9337 char *linksym
= alloca (name_len
+ 6);
9339 memcpy (linksym
+ 1, name
, name_len
);
9340 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
9341 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
9342 ggc_alloc_string (linksym
, name_len
+ 5));
9345 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
9346 (splay_tree_value
) al
);
9352 alpha_use_linkage (linkage
, cfundecl
, lflag
, rflag
)
9358 splay_tree_node cfunnode
;
9359 struct alpha_funcs
*cfaf
;
9360 struct alpha_links
*al
;
9361 const char *name
= XSTR (linkage
, 0);
9363 cfaf
= (struct alpha_funcs
*) 0;
9364 al
= (struct alpha_links
*) 0;
9366 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
9367 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
9371 splay_tree_node lnode
;
9373 /* Is this name already defined? */
9375 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
9377 al
= (struct alpha_links
*) lnode
->value
;
9380 cfaf
->links
= splay_tree_new_ggc ((splay_tree_compare_fn
) strcmp
);
9388 splay_tree_node node
= 0;
9389 struct alpha_links
*anl
;
9394 name_len
= strlen (name
);
9396 al
= (struct alpha_links
*) ggc_alloc (sizeof (struct alpha_links
));
9397 al
->num
= cfaf
->num
;
9399 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9402 anl
= (struct alpha_links
*) node
->value
;
9403 al
->lkind
= anl
->lkind
;
9406 sprintf (buf
, "$%d..%s..lk", cfaf
->num
, name
);
9407 buflen
= strlen (buf
);
9408 linksym
= alloca (buflen
+ 1);
9409 memcpy (linksym
, buf
, buflen
+ 1);
9411 al
->linkage
= gen_rtx_SYMBOL_REF
9412 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
9414 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
9415 (splay_tree_value
) al
);
9419 al
->rkind
= KIND_CODEADDR
;
9421 al
->rkind
= KIND_LINKAGE
;
9424 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
9430 alpha_write_one_linkage (node
, data
)
9431 splay_tree_node node
;
9434 const char *const name
= (const char *) node
->key
;
9435 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
9436 FILE *stream
= (FILE *) data
;
9438 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
9439 if (link
->rkind
== KIND_CODEADDR
)
9441 if (link
->lkind
== KIND_LOCAL
)
9443 /* Local and used */
9444 fprintf (stream
, "\t.quad %s..en\n", name
);
9448 /* External and used, request code address. */
9449 fprintf (stream
, "\t.code_address %s\n", name
);
9454 if (link
->lkind
== KIND_LOCAL
)
9456 /* Local and used, build linkage pair. */
9457 fprintf (stream
, "\t.quad %s..en\n", name
);
9458 fprintf (stream
, "\t.quad %s\n", name
);
9462 /* External and used, request linkage pair. */
9463 fprintf (stream
, "\t.linkage %s\n", name
);
9471 alpha_write_linkage (stream
, funname
, fundecl
)
9473 const char *funname
;
9476 splay_tree_node node
;
9477 struct alpha_funcs
*func
;
9480 fprintf (stream
, "\t.align 3\n");
9481 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
9482 func
= (struct alpha_funcs
*) node
->value
;
9484 fputs ("\t.name ", stream
);
9485 assemble_name (stream
, funname
);
9486 fputs ("..na\n", stream
);
9487 ASM_OUTPUT_LABEL (stream
, funname
);
9488 fprintf (stream
, "\t.pdesc ");
9489 assemble_name (stream
, funname
);
9490 fprintf (stream
, "..en,%s\n",
9491 alpha_procedure_type
== PT_STACK
? "stack"
9492 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
9496 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
9497 /* splay_tree_delete (func->links); */
9501 /* Given a decl, a section name, and whether the decl initializer
9502 has relocs, choose attributes for the section. */
9504 #define SECTION_VMS_OVERLAY SECTION_FORGET
9505 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9506 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9509 vms_section_type_flags (decl
, name
, reloc
)
9514 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9516 if (decl
&& DECL_ATTRIBUTES (decl
)
9517 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
9518 flags
|= SECTION_VMS_OVERLAY
;
9519 if (decl
&& DECL_ATTRIBUTES (decl
)
9520 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
9521 flags
|= SECTION_VMS_GLOBAL
;
9522 if (decl
&& DECL_ATTRIBUTES (decl
)
9523 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
9524 flags
|= SECTION_VMS_INITIALIZE
;
9529 /* Switch to an arbitrary section NAME with attributes as specified
9530 by FLAGS. ALIGN specifies any known alignment requirements for
9531 the section; 0 if the default should be used. */
9534 vms_asm_named_section (name
, flags
)
9538 fputc ('\n', asm_out_file
);
9539 fprintf (asm_out_file
, ".section\t%s", name
);
9541 if (flags
& SECTION_VMS_OVERLAY
)
9542 fprintf (asm_out_file
, ",OVR");
9543 if (flags
& SECTION_VMS_GLOBAL
)
9544 fprintf (asm_out_file
, ",GBL");
9545 if (flags
& SECTION_VMS_INITIALIZE
)
9546 fprintf (asm_out_file
, ",NOMOD");
9547 if (flags
& SECTION_DEBUG
)
9548 fprintf (asm_out_file
, ",NOWRT");
9550 fputc ('\n', asm_out_file
);
9553 /* Record an element in the table of global constructors. SYMBOL is
9554 a SYMBOL_REF of the function to be called; PRIORITY is a number
9555 between 0 and MAX_INIT_PRIORITY.
9557 Differs from default_ctors_section_asm_out_constructor in that the
9558 width of the .ctors entry is always 64 bits, rather than the 32 bits
9559 used by a normal pointer. */
9562 vms_asm_out_constructor (symbol
, priority
)
9564 int priority ATTRIBUTE_UNUSED
;
9567 assemble_align (BITS_PER_WORD
);
9568 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9572 vms_asm_out_destructor (symbol
, priority
)
9574 int priority ATTRIBUTE_UNUSED
;
9577 assemble_align (BITS_PER_WORD
);
9578 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9583 alpha_need_linkage (name
, is_local
)
9584 const char *name ATTRIBUTE_UNUSED
;
9585 int is_local ATTRIBUTE_UNUSED
;
9591 alpha_use_linkage (linkage
, cfundecl
, lflag
, rflag
)
9592 rtx linkage ATTRIBUTE_UNUSED
;
9593 tree cfundecl ATTRIBUTE_UNUSED
;
9594 int lflag ATTRIBUTE_UNUSED
;
9595 int rflag ATTRIBUTE_UNUSED
;
9600 #endif /* TARGET_ABI_OPEN_VMS */
9602 #if TARGET_ABI_UNICOSMK
9604 static void unicosmk_output_module_name
PARAMS ((FILE *));
9605 static void unicosmk_output_default_externs
PARAMS ((FILE *));
9606 static void unicosmk_output_dex
PARAMS ((FILE *));
9607 static void unicosmk_output_externs
PARAMS ((FILE *));
9608 static void unicosmk_output_addr_vec
PARAMS ((FILE *, rtx
));
9609 static const char *unicosmk_ssib_name
PARAMS ((void));
9610 static int unicosmk_special_name
PARAMS ((const char *));
9612 /* Define the offset between two registers, one to be eliminated, and the
9613 other its replacement, at the start of a routine. */
9616 unicosmk_initial_elimination_offset (from
, to
)
9622 fixed_size
= alpha_sa_size();
9623 if (fixed_size
!= 0)
9626 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9628 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9630 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9631 return (ALPHA_ROUND (current_function_outgoing_args_size
)
9632 + ALPHA_ROUND (get_frame_size()));
9633 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9634 return (ALPHA_ROUND (fixed_size
)
9635 + ALPHA_ROUND (get_frame_size()
9636 + current_function_outgoing_args_size
));
9641 /* Output the module name for .ident and .end directives. We have to strip
9642 directories and add make sure that the module name starts with a letter
9646 unicosmk_output_module_name (file
)
9651 /* Strip directories. */
9653 name
= strrchr (main_input_filename
, '/');
9657 name
= main_input_filename
;
9659 /* CAM only accepts module names that start with a letter or '$'. We
9660 prefix the module name with a '$' if necessary. */
9662 if (!ISALPHA (*name
))
9664 output_clean_symbol_name (file
, name
);
9667 /* Output text that to appear at the beginning of an assembler file. */
9670 unicosmk_asm_file_start (file
)
9675 fputs ("\t.ident\t", file
);
9676 unicosmk_output_module_name (file
);
9677 fputs ("\n\n", file
);
9679 /* The Unicos/Mk assembler uses different register names. Instead of trying
9680 to support them, we simply use micro definitions. */
9682 /* CAM has different register names: rN for the integer register N and fN
9683 for the floating-point register N. Instead of trying to use these in
9684 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9687 for (i
= 0; i
< 32; ++i
)
9688 fprintf (file
, "$%d <- r%d\n", i
, i
);
9690 for (i
= 0; i
< 32; ++i
)
9691 fprintf (file
, "$f%d <- f%d\n", i
, i
);
9695 /* The .align directive fill unused space with zeroes which does not work
9696 in code sections. We define the macro 'gcc@code@align' which uses nops
9697 instead. Note that it assumes that code sections always have the
9698 biggest possible alignment since . refers to the current offset from
9699 the beginning of the section. */
9701 fputs ("\t.macro gcc@code@align n\n", file
);
9702 fputs ("gcc@n@bytes = 1 << n\n", file
);
9703 fputs ("gcc@here = . % gcc@n@bytes\n", file
);
9704 fputs ("\t.if ne, gcc@here, 0\n", file
);
9705 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", file
);
9706 fputs ("\tbis r31,r31,r31\n", file
);
9707 fputs ("\t.endr\n", file
);
9708 fputs ("\t.endif\n", file
);
9709 fputs ("\t.endm gcc@code@align\n\n", file
);
9711 /* Output extern declarations which should always be visible. */
9712 unicosmk_output_default_externs (file
);
9714 /* Open a dummy section. We always need to be inside a section for the
9715 section-switching code to work correctly.
9716 ??? This should be a module id or something like that. I still have to
9717 figure out what the rules for those are. */
9718 fputs ("\n\t.psect\t$SG00000,data\n", file
);
9721 /* Output text to appear at the end of an assembler file. This includes all
9722 pending extern declarations and DEX expressions. */
9725 unicosmk_asm_file_end (file
)
9728 fputs ("\t.endp\n\n", file
);
9730 /* Output all pending externs. */
9732 unicosmk_output_externs (file
);
9734 /* Output dex definitions used for functions whose names conflict with
9737 unicosmk_output_dex (file
);
9739 fputs ("\t.end\t", file
);
9740 unicosmk_output_module_name (file
);
9744 /* Output the definition of a common variable. */
9747 unicosmk_output_common (file
, name
, size
, align
)
9754 printf ("T3E__: common %s\n", name
);
9757 fputs("\t.endp\n\n\t.psect ", file
);
9758 assemble_name(file
, name
);
9759 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
9760 fprintf(file
, "\t.byte\t0:%d\n", size
);
9762 /* Mark the symbol as defined in this module. */
9763 name_tree
= get_identifier (name
);
9764 TREE_ASM_WRITTEN (name_tree
) = 1;
9767 #define SECTION_PUBLIC SECTION_MACH_DEP
9768 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9769 static int current_section_align
;
9772 unicosmk_section_type_flags (decl
, name
, reloc
)
9775 int reloc ATTRIBUTE_UNUSED
;
9777 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9782 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9784 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9785 if (align_functions_log
> current_section_align
)
9786 current_section_align
= align_functions_log
;
9788 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
9789 flags
|= SECTION_MAIN
;
9792 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
9794 if (TREE_PUBLIC (decl
))
9795 flags
|= SECTION_PUBLIC
;
9800 /* Generate a section name for decl and associate it with the
9804 unicosmk_unique_section (decl
, reloc
)
9806 int reloc ATTRIBUTE_UNUSED
;
9814 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9815 name
= alpha_strip_name_encoding (name
);
9816 len
= strlen (name
);
9818 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9822 /* It is essential that we prefix the section name here because
9823 otherwise the section names generated for constructors and
9824 destructors confuse collect2. */
9826 string
= alloca (len
+ 6);
9827 sprintf (string
, "code@%s", name
);
9828 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9830 else if (TREE_PUBLIC (decl
))
9831 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
9836 string
= alloca (len
+ 6);
9837 sprintf (string
, "data@%s", name
);
9838 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9842 /* Switch to an arbitrary section NAME with attributes as specified
9843 by FLAGS. ALIGN specifies any known alignment requirements for
9844 the section; 0 if the default should be used. */
9847 unicosmk_asm_named_section (name
, flags
)
9853 /* Close the previous section. */
9855 fputs ("\t.endp\n\n", asm_out_file
);
9857 /* Find out what kind of section we are opening. */
9859 if (flags
& SECTION_MAIN
)
9860 fputs ("\t.start\tmain\n", asm_out_file
);
9862 if (flags
& SECTION_CODE
)
9864 else if (flags
& SECTION_PUBLIC
)
9869 if (current_section_align
!= 0)
9870 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
9871 current_section_align
, kind
);
9873 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
9877 unicosmk_insert_attributes (decl
, attr_ptr
)
9879 tree
*attr_ptr ATTRIBUTE_UNUSED
;
9882 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
9883 unicosmk_unique_section (decl
, 0);
9886 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9887 in code sections because .align fill unused space with zeroes. */
9890 unicosmk_output_align (file
, align
)
9894 if (inside_function
)
9895 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
9897 fprintf (file
, "\t.align\t%d\n", align
);
9900 /* Add a case vector to the current function's list of deferred case
9901 vectors. Case vectors have to be put into a separate section because CAM
9902 does not allow data definitions in code sections. */
9905 unicosmk_defer_case_vector (lab
, vec
)
9909 struct machine_function
*machine
= cfun
->machine
;
9911 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9912 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
9913 machine
->addr_list
);
9916 /* Output a case vector. */
9919 unicosmk_output_addr_vec (file
, vec
)
9923 rtx lab
= XEXP (vec
, 0);
9924 rtx body
= XEXP (vec
, 1);
9925 int vlen
= XVECLEN (body
, 0);
9928 (*targetm
.asm_out
.internal_label
) (file
, "L", CODE_LABEL_NUMBER (lab
));
9930 for (idx
= 0; idx
< vlen
; idx
++)
9932 ASM_OUTPUT_ADDR_VEC_ELT
9933 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9937 /* Output current function's deferred case vectors. */
9940 unicosmk_output_deferred_case_vectors (file
)
9943 struct machine_function
*machine
= cfun
->machine
;
9946 if (machine
->addr_list
== NULL_RTX
)
9950 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
9951 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
9954 /* Set up the dynamic subprogram information block (DSIB) and update the
9955 frame pointer register ($15) for subroutines which have a frame. If the
9956 subroutine doesn't have a frame, simply increment $15. */
9959 unicosmk_gen_dsib (imaskP
)
9960 unsigned long * imaskP
;
9962 if (alpha_procedure_type
== PT_STACK
)
9964 const char *ssib_name
;
9967 /* Allocate 64 bytes for the DSIB. */
9969 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9971 emit_insn (gen_blockage ());
9973 /* Save the return address. */
9975 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
9976 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9977 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
9978 (*imaskP
) &= ~(1L << REG_RA
);
9980 /* Save the old frame pointer. */
9982 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
9983 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9984 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
9985 (*imaskP
) &= ~(1L << HARD_FRAME_POINTER_REGNUM
);
9987 emit_insn (gen_blockage ());
9989 /* Store the SSIB pointer. */
9991 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
9992 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
9993 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9995 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
9996 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
9997 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
9999 /* Save the CIW index. */
10001 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
10002 set_mem_alias_set (mem
, alpha_sr_alias_set
);
10003 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
10005 emit_insn (gen_blockage ());
10007 /* Set the new frame pointer. */
10009 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
10010 stack_pointer_rtx
, GEN_INT (64))));
10015 /* Increment the frame pointer register to indicate that we do not
10018 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
10019 hard_frame_pointer_rtx
, GEN_INT (1))));
10023 #define SSIB_PREFIX "__SSIB_"
10024 #define SSIB_PREFIX_LEN 7
10026 /* Generate the name of the SSIB section for the current function. */
10028 static const char *
10029 unicosmk_ssib_name ()
10031 /* This is ok since CAM won't be able to deal with names longer than that
10034 static char name
[256];
10037 const char *fnname
;
10040 x
= DECL_RTL (cfun
->decl
);
10041 if (GET_CODE (x
) != MEM
)
10044 if (GET_CODE (x
) != SYMBOL_REF
)
10046 fnname
= alpha_strip_name_encoding (XSTR (x
, 0));
10048 len
= strlen (fnname
);
10049 if (len
+ SSIB_PREFIX_LEN
> 255)
10050 len
= 255 - SSIB_PREFIX_LEN
;
10052 strcpy (name
, SSIB_PREFIX
);
10053 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
10054 name
[len
+ SSIB_PREFIX_LEN
] = 0;
10059 /* Output the static subroutine information block for the current
10063 unicosmk_output_ssib (file
, fnname
)
10065 const char *fnname
;
10071 struct machine_function
*machine
= cfun
->machine
;
10074 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
10075 unicosmk_ssib_name ());
10077 /* Some required stuff and the function name length. */
10079 len
= strlen (fnname
);
10080 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
10083 ??? We don't do that yet. */
10085 fputs ("\t.quad\t0\n", file
);
10087 /* Function address. */
10089 fputs ("\t.quad\t", file
);
10090 assemble_name (file
, fnname
);
10093 fputs ("\t.quad\t0\n", file
);
10094 fputs ("\t.quad\t0\n", file
);
10097 ??? We do it the same way Cray CC does it but this could be
10100 for( i
= 0; i
< len
; i
++ )
10101 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
10102 if( (len
% 8) == 0 )
10103 fputs ("\t.quad\t0\n", file
);
10105 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
10107 /* All call information words used in the function. */
10109 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
10112 fprintf (file
, "\t.quad\t");
10113 #if HOST_BITS_PER_WIDE_INT == 32
10114 fprintf (file
, HOST_WIDE_INT_PRINT_DOUBLE_HEX
,
10115 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
10117 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (ciw
));
10119 fprintf (file
, "\n");
10123 /* Add a call information word (CIW) to the list of the current function's
10124 CIWs and return its index.
10126 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
10129 unicosmk_add_call_info_word (x
)
10133 struct machine_function
*machine
= cfun
->machine
;
10135 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
10136 if (machine
->first_ciw
== NULL_RTX
)
10137 machine
->first_ciw
= node
;
10139 XEXP (machine
->last_ciw
, 1) = node
;
10141 machine
->last_ciw
= node
;
10142 ++machine
->ciw_count
;
10144 return GEN_INT (machine
->ciw_count
10145 + strlen (current_function_name
)/8 + 5);
10148 static char unicosmk_section_buf
[100];
10151 unicosmk_text_section ()
10153 static int count
= 0;
10154 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
10156 return unicosmk_section_buf
;
10160 unicosmk_data_section ()
10162 static int count
= 1;
10163 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
10165 return unicosmk_section_buf
;
10168 /* The Cray assembler doesn't accept extern declarations for symbols which
10169 are defined in the same file. We have to keep track of all global
10170 symbols which are referenced and/or defined in a source file and output
10171 extern declarations for those which are referenced but not defined at
10172 the end of file. */
10174 /* List of identifiers for which an extern declaration might have to be
10176 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10178 struct unicosmk_extern_list
10180 struct unicosmk_extern_list
*next
;
10184 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
10186 /* Output extern declarations which are required for every asm file. */
10189 unicosmk_output_default_externs (file
)
10192 static const char *const externs
[] =
10193 { "__T3E_MISMATCH" };
10198 n
= ARRAY_SIZE (externs
);
10200 for (i
= 0; i
< n
; i
++)
10201 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
10204 /* Output extern declarations for global symbols which are have been
10205 referenced but not defined. */
10208 unicosmk_output_externs (file
)
10211 struct unicosmk_extern_list
*p
;
10212 const char *real_name
;
10216 len
= strlen (user_label_prefix
);
10217 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
10219 /* We have to strip the encoding and possibly remove user_label_prefix
10220 from the identifier in order to handle -fleading-underscore and
10221 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
10222 real_name
= alpha_strip_name_encoding (p
->name
);
10223 if (len
&& p
->name
[0] == '*'
10224 && !memcmp (real_name
, user_label_prefix
, len
))
10227 name_tree
= get_identifier (real_name
);
10228 if (! TREE_ASM_WRITTEN (name_tree
))
10230 TREE_ASM_WRITTEN (name_tree
) = 1;
10231 fputs ("\t.extern\t", file
);
10232 assemble_name (file
, p
->name
);
10238 /* Record an extern. */
10241 unicosmk_add_extern (name
)
10244 struct unicosmk_extern_list
*p
;
10246 p
= (struct unicosmk_extern_list
*)
10247 xmalloc (sizeof (struct unicosmk_extern_list
));
10248 p
->next
= unicosmk_extern_head
;
10250 unicosmk_extern_head
= p
;
10253 /* The Cray assembler generates incorrect code if identifiers which
10254 conflict with register names are used as instruction operands. We have
10255 to replace such identifiers with DEX expressions. */
10257 /* Structure to collect identifiers which have been replaced by DEX
10259 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10261 struct unicosmk_dex
{
10262 struct unicosmk_dex
*next
;
10266 /* List of identifiers which have been replaced by DEX expressions. The DEX
10267 number is determined by the position in the list. */
10269 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
10271 /* The number of elements in the DEX list. */
10273 static int unicosmk_dex_count
= 0;
10275 /* Check if NAME must be replaced by a DEX expression. */
10278 unicosmk_special_name (name
)
10281 if (name
[0] == '*')
10284 if (name
[0] == '$')
10287 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
10292 case '1': case '2':
10293 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
10296 return (name
[2] == '\0'
10297 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
10300 return (ISDIGIT (name
[1]) && name
[2] == '\0');
10304 /* Return the DEX number if X must be replaced by a DEX expression and 0
10308 unicosmk_need_dex (x
)
10311 struct unicosmk_dex
*dex
;
10315 if (GET_CODE (x
) != SYMBOL_REF
)
10319 if (! unicosmk_special_name (name
))
10322 i
= unicosmk_dex_count
;
10323 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10325 if (! strcmp (name
, dex
->name
))
10330 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
10332 dex
->next
= unicosmk_dex_list
;
10333 unicosmk_dex_list
= dex
;
10335 ++unicosmk_dex_count
;
10336 return unicosmk_dex_count
;
10339 /* Output the DEX definitions for this file. */
10342 unicosmk_output_dex (file
)
10345 struct unicosmk_dex
*dex
;
10348 if (unicosmk_dex_list
== NULL
)
10351 fprintf (file
, "\t.dexstart\n");
10353 i
= unicosmk_dex_count
;
10354 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10356 fprintf (file
, "\tDEX (%d) = ", i
);
10357 assemble_name (file
, dex
->name
);
10362 fprintf (file
, "\t.dexend\n");
10368 unicosmk_output_deferred_case_vectors (file
)
10369 FILE *file ATTRIBUTE_UNUSED
;
10373 unicosmk_gen_dsib (imaskP
)
10374 unsigned long * imaskP ATTRIBUTE_UNUSED
;
10378 unicosmk_output_ssib (file
, fnname
)
10379 FILE * file ATTRIBUTE_UNUSED
;
10380 const char * fnname ATTRIBUTE_UNUSED
;
10384 unicosmk_add_call_info_word (x
)
10385 rtx x ATTRIBUTE_UNUSED
;
10391 unicosmk_need_dex (x
)
10392 rtx x ATTRIBUTE_UNUSED
;
10397 #endif /* TARGET_ABI_UNICOSMK */
10399 #include "gt-alpha.h"