1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
45 #include "integrate.h"
48 #include "target-def.h"
50 #include "langhooks.h"
52 /* Specify which cpu to schedule for. */
54 enum processor_type alpha_cpu
;
55 static const char * const alpha_cpu_name
[] =
60 /* Specify how accurate floating-point traps need to be. */
62 enum alpha_trap_precision alpha_tp
;
64 /* Specify the floating-point rounding mode. */
66 enum alpha_fp_rounding_mode alpha_fprm
;
68 /* Specify which things cause traps. */
70 enum alpha_fp_trap_mode alpha_fptm
;
72 /* Specify bit size of immediate TLS offsets. */
74 int alpha_tls_size
= 32;
76 /* Strings decoded into the above options. */
78 const char *alpha_cpu_string
; /* -mcpu= */
79 const char *alpha_tune_string
; /* -mtune= */
80 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
81 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
82 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
83 const char *alpha_mlat_string
; /* -mmemory-latency= */
84 const char *alpha_tls_size_string
; /* -mtls-size=[16|32|64] */
86 /* Save information from a "cmpxx" operation until the branch or scc is
89 struct alpha_compare alpha_compare
;
91 /* Non-zero if inside of a function, because the Alpha asm can't
92 handle .files inside of functions. */
94 static int inside_function
= FALSE
;
96 /* The number of cycles of latency we should assume on memory reads. */
98 int alpha_memory_latency
= 3;
100 /* Whether the function needs the GP. */
102 static int alpha_function_needs_gp
;
104 /* The alias set for prologue/epilogue register save/restore. */
106 static int alpha_sr_alias_set
;
108 /* The assembler name of the current function. */
110 static const char *alpha_fnname
;
112 /* The next explicit relocation sequence number. */
113 int alpha_next_sequence_number
= 1;
115 /* The literal and gpdisp sequence numbers for this insn, as printed
116 by %# and %* respectively. */
117 int alpha_this_literal_sequence_number
;
118 int alpha_this_gpdisp_sequence_number
;
120 /* Declarations of static functions. */
121 static int tls_symbolic_operand_1
122 PARAMS ((rtx
, enum machine_mode
, int, int));
123 static enum tls_model tls_symbolic_operand_type
125 static bool decl_in_text_section
127 static bool alpha_in_small_data_p
129 static void alpha_encode_section_info
130 PARAMS ((tree
, int));
131 static const char *alpha_strip_name_encoding
132 PARAMS ((const char *));
133 static int some_small_symbolic_operand_1
134 PARAMS ((rtx
*, void *));
135 static int split_small_symbolic_operand_1
136 PARAMS ((rtx
*, void *));
137 static void alpha_set_memflags_1
138 PARAMS ((rtx
, int, int, int));
139 static rtx alpha_emit_set_const_1
140 PARAMS ((rtx
, enum machine_mode
, HOST_WIDE_INT
, int));
141 static void alpha_expand_unaligned_load_words
142 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
143 static void alpha_expand_unaligned_store_words
144 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
145 static void alpha_init_builtins
147 static rtx alpha_expand_builtin
148 PARAMS ((tree
, rtx
, rtx
, enum machine_mode
, int));
149 static void alpha_sa_mask
150 PARAMS ((unsigned long *imaskP
, unsigned long *fmaskP
));
151 static int find_lo_sum
152 PARAMS ((rtx
*, void *));
153 static int alpha_does_function_need_gp
155 static int alpha_ra_ever_killed
157 static const char *get_trap_mode_suffix
159 static const char *get_round_mode_suffix
161 static const char *get_some_local_dynamic_name
163 static int get_some_local_dynamic_name_1
164 PARAMS ((rtx
*, void *));
165 static rtx set_frame_related_p
167 static const char *alpha_lookup_xfloating_lib_func
168 PARAMS ((enum rtx_code
));
169 static int alpha_compute_xfloating_mode_arg
170 PARAMS ((enum rtx_code
, enum alpha_fp_rounding_mode
));
171 static void alpha_emit_xfloating_libcall
172 PARAMS ((const char *, rtx
, rtx
[], int, rtx
));
173 static rtx alpha_emit_xfloating_compare
174 PARAMS ((enum rtx_code
, rtx
, rtx
));
175 static void alpha_output_function_end_prologue
177 static int alpha_adjust_cost
178 PARAMS ((rtx
, rtx
, rtx
, int));
179 static int alpha_issue_rate
181 static int alpha_use_dfa_pipeline_interface
183 static int alpha_multipass_dfa_lookahead
186 #ifdef OBJECT_FORMAT_ELF
187 static void alpha_elf_select_rtx_section
188 PARAMS ((enum machine_mode
, rtx
, unsigned HOST_WIDE_INT
));
191 #if TARGET_ABI_OPEN_VMS
192 static bool alpha_linkage_symbol_p
193 PARAMS ((const char *symname
));
194 static void alpha_write_linkage
195 PARAMS ((FILE *, const char *, tree
));
198 static struct machine_function
* alpha_init_machine_status
201 static void unicosmk_output_deferred_case_vectors
PARAMS ((FILE *));
202 static void unicosmk_gen_dsib
PARAMS ((unsigned long *imaskP
));
203 static void unicosmk_output_ssib
PARAMS ((FILE *, const char *));
204 static int unicosmk_need_dex
PARAMS ((rtx
));
206 /* Get the number of args of a function in one of two ways. */
207 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
208 #define NUM_ARGS current_function_args_info.num_args
210 #define NUM_ARGS current_function_args_info
216 /* Initialize the GCC target structure. */
217 #if TARGET_ABI_OPEN_VMS
218 const struct attribute_spec vms_attribute_table
[];
219 static unsigned int vms_section_type_flags
PARAMS ((tree
, const char *, int));
220 static void vms_asm_named_section
PARAMS ((const char *, unsigned int));
221 static void vms_asm_out_constructor
PARAMS ((rtx
, int));
222 static void vms_asm_out_destructor
PARAMS ((rtx
, int));
223 # undef TARGET_ATTRIBUTE_TABLE
224 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
225 # undef TARGET_SECTION_TYPE_FLAGS
226 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
229 #undef TARGET_IN_SMALL_DATA_P
230 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
231 #undef TARGET_ENCODE_SECTION_INFO
232 #define TARGET_ENCODE_SECTION_INFO alpha_encode_section_info
233 #undef TARGET_STRIP_NAME_ENCODING
234 #define TARGET_STRIP_NAME_ENCODING alpha_strip_name_encoding
236 #if TARGET_ABI_UNICOSMK
237 static void unicosmk_asm_named_section
PARAMS ((const char *, unsigned int));
238 static void unicosmk_insert_attributes
PARAMS ((tree
, tree
*));
239 static unsigned int unicosmk_section_type_flags
PARAMS ((tree
, const char *,
241 static void unicosmk_unique_section
PARAMS ((tree
, int));
242 # undef TARGET_INSERT_ATTRIBUTES
243 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
244 # undef TARGET_SECTION_TYPE_FLAGS
245 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
246 # undef TARGET_ASM_UNIQUE_SECTION
247 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
248 # undef TARGET_ASM_GLOBALIZE_LABEL
249 # define TARGET_ASM_GLOBALIZE_LABEL hook_FILEptr_constcharptr_void
252 #undef TARGET_ASM_ALIGNED_HI_OP
253 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
254 #undef TARGET_ASM_ALIGNED_DI_OP
255 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
257 /* Default unaligned ops are provided for ELF systems. To get unaligned
258 data for non-ELF systems, we have to turn off auto alignment. */
259 #ifndef OBJECT_FORMAT_ELF
260 #undef TARGET_ASM_UNALIGNED_HI_OP
261 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
262 #undef TARGET_ASM_UNALIGNED_SI_OP
263 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
264 #undef TARGET_ASM_UNALIGNED_DI_OP
265 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
268 #ifdef OBJECT_FORMAT_ELF
269 #undef TARGET_ASM_SELECT_RTX_SECTION
270 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
273 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
274 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
276 #undef TARGET_SCHED_ADJUST_COST
277 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
278 #undef TARGET_SCHED_ISSUE_RATE
279 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
280 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
281 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
282 alpha_use_dfa_pipeline_interface
283 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
284 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
285 alpha_multipass_dfa_lookahead
287 #undef TARGET_HAVE_TLS
288 #define TARGET_HAVE_TLS HAVE_AS_TLS
290 #undef TARGET_INIT_BUILTINS
291 #define TARGET_INIT_BUILTINS alpha_init_builtins
292 #undef TARGET_EXPAND_BUILTIN
293 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
295 struct gcc_target targetm
= TARGET_INITIALIZER
;
297 /* Parse target option strings. */
303 static const struct cpu_table
{
304 const char *const name
;
305 const enum processor_type processor
;
308 #define EV5_MASK (MASK_CPU_EV5)
309 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
310 { "ev4", PROCESSOR_EV4
, 0 },
311 { "ev45", PROCESSOR_EV4
, 0 },
312 { "21064", PROCESSOR_EV4
, 0 },
313 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
314 { "21164", PROCESSOR_EV5
, EV5_MASK
},
315 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
316 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
317 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
318 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
319 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
320 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
321 { "21264", PROCESSOR_EV6
, EV6_MASK
},
322 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
323 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
327 /* Unicos/Mk doesn't have shared libraries. */
328 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
330 warning ("-f%s ignored for Unicos/Mk (not supported)",
331 (flag_pic
> 1) ? "PIC" : "pic");
335 /* On Unicos/Mk, the native compiler consistenly generates /d suffices for
336 floating-point instructions. Make that the default for this target. */
337 if (TARGET_ABI_UNICOSMK
)
338 alpha_fprm
= ALPHA_FPRM_DYN
;
340 alpha_fprm
= ALPHA_FPRM_NORM
;
342 alpha_tp
= ALPHA_TP_PROG
;
343 alpha_fptm
= ALPHA_FPTM_N
;
345 /* We cannot use su and sui qualifiers for conversion instructions on
346 Unicos/Mk. I'm not sure if this is due to assembler or hardware
347 limitations. Right now, we issue a warning if -mieee is specified
348 and then ignore it; eventually, we should either get it right or
349 disable the option altogether. */
353 if (TARGET_ABI_UNICOSMK
)
354 warning ("-mieee not supported on Unicos/Mk");
357 alpha_tp
= ALPHA_TP_INSN
;
358 alpha_fptm
= ALPHA_FPTM_SU
;
362 if (TARGET_IEEE_WITH_INEXACT
)
364 if (TARGET_ABI_UNICOSMK
)
365 warning ("-mieee-with-inexact not supported on Unicos/Mk");
368 alpha_tp
= ALPHA_TP_INSN
;
369 alpha_fptm
= ALPHA_FPTM_SUI
;
375 if (! strcmp (alpha_tp_string
, "p"))
376 alpha_tp
= ALPHA_TP_PROG
;
377 else if (! strcmp (alpha_tp_string
, "f"))
378 alpha_tp
= ALPHA_TP_FUNC
;
379 else if (! strcmp (alpha_tp_string
, "i"))
380 alpha_tp
= ALPHA_TP_INSN
;
382 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string
);
385 if (alpha_fprm_string
)
387 if (! strcmp (alpha_fprm_string
, "n"))
388 alpha_fprm
= ALPHA_FPRM_NORM
;
389 else if (! strcmp (alpha_fprm_string
, "m"))
390 alpha_fprm
= ALPHA_FPRM_MINF
;
391 else if (! strcmp (alpha_fprm_string
, "c"))
392 alpha_fprm
= ALPHA_FPRM_CHOP
;
393 else if (! strcmp (alpha_fprm_string
,"d"))
394 alpha_fprm
= ALPHA_FPRM_DYN
;
396 error ("bad value `%s' for -mfp-rounding-mode switch",
400 if (alpha_fptm_string
)
402 if (strcmp (alpha_fptm_string
, "n") == 0)
403 alpha_fptm
= ALPHA_FPTM_N
;
404 else if (strcmp (alpha_fptm_string
, "u") == 0)
405 alpha_fptm
= ALPHA_FPTM_U
;
406 else if (strcmp (alpha_fptm_string
, "su") == 0)
407 alpha_fptm
= ALPHA_FPTM_SU
;
408 else if (strcmp (alpha_fptm_string
, "sui") == 0)
409 alpha_fptm
= ALPHA_FPTM_SUI
;
411 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string
);
414 if (alpha_tls_size_string
)
416 if (strcmp (alpha_tls_size_string
, "16") == 0)
418 else if (strcmp (alpha_tls_size_string
, "32") == 0)
420 else if (strcmp (alpha_tls_size_string
, "64") == 0)
423 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string
);
427 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
428 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
430 if (alpha_cpu_string
)
432 for (i
= 0; cpu_table
[i
].name
; i
++)
433 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
435 alpha_cpu
= cpu_table
[i
].processor
;
436 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
437 | MASK_CPU_EV5
| MASK_CPU_EV6
);
438 target_flags
|= cpu_table
[i
].flags
;
441 if (! cpu_table
[i
].name
)
442 error ("bad value `%s' for -mcpu switch", alpha_cpu_string
);
445 if (alpha_tune_string
)
447 for (i
= 0; cpu_table
[i
].name
; i
++)
448 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
450 alpha_cpu
= cpu_table
[i
].processor
;
453 if (! cpu_table
[i
].name
)
454 error ("bad value `%s' for -mcpu switch", alpha_tune_string
);
457 /* Do some sanity checks on the above options. */
459 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
461 warning ("trap mode not supported on Unicos/Mk");
462 alpha_fptm
= ALPHA_FPTM_N
;
465 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
466 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
468 warning ("fp software completion requires -mtrap-precision=i");
469 alpha_tp
= ALPHA_TP_INSN
;
474 /* Except for EV6 pass 1 (not released), we always have precise
475 arithmetic traps. Which means we can do software completion
476 without minding trap shadows. */
477 alpha_tp
= ALPHA_TP_PROG
;
480 if (TARGET_FLOAT_VAX
)
482 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
484 warning ("rounding mode not supported for VAX floats");
485 alpha_fprm
= ALPHA_FPRM_NORM
;
487 if (alpha_fptm
== ALPHA_FPTM_SUI
)
489 warning ("trap mode not supported for VAX floats");
490 alpha_fptm
= ALPHA_FPTM_SU
;
498 if (!alpha_mlat_string
)
499 alpha_mlat_string
= "L1";
501 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
502 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
504 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
505 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
506 && alpha_mlat_string
[2] == '\0')
508 static int const cache_latency
[][4] =
510 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
511 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
512 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
515 lat
= alpha_mlat_string
[1] - '0';
516 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
518 warning ("L%d cache latency unknown for %s",
519 lat
, alpha_cpu_name
[alpha_cpu
]);
523 lat
= cache_latency
[alpha_cpu
][lat
-1];
525 else if (! strcmp (alpha_mlat_string
, "main"))
527 /* Most current memories have about 370ns latency. This is
528 a reasonable guess for a fast cpu. */
533 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string
);
537 alpha_memory_latency
= lat
;
540 /* Default the definition of "small data" to 8 bytes. */
544 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
546 target_flags
|= MASK_SMALL_DATA
;
547 else if (flag_pic
== 2)
548 target_flags
&= ~MASK_SMALL_DATA
;
550 /* Align labels and loops for optimal branching. */
551 /* ??? Kludge these by not doing anything if we don't optimize and also if
552 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
553 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
555 if (align_loops
<= 0)
557 if (align_jumps
<= 0)
560 if (align_functions
<= 0)
561 align_functions
= 16;
563 /* Acquire a unique set number for our register saves and restores. */
564 alpha_sr_alias_set
= new_alias_set ();
566 /* Register variables and functions with the garbage collector. */
568 /* Set up function hooks. */
569 init_machine_status
= alpha_init_machine_status
;
572 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
580 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
582 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
588 /* Returns 1 if OP is either the constant zero or a register. If a
589 register, it must be in the proper mode unless MODE is VOIDmode. */
592 reg_or_0_operand (op
, mode
)
594 enum machine_mode mode
;
596 return op
== CONST0_RTX (mode
) || register_operand (op
, mode
);
599 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
603 reg_or_6bit_operand (op
, mode
)
605 enum machine_mode mode
;
607 return ((GET_CODE (op
) == CONST_INT
608 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64)
609 || register_operand (op
, mode
));
613 /* Return 1 if OP is an 8-bit constant or any register. */
616 reg_or_8bit_operand (op
, mode
)
618 enum machine_mode mode
;
620 return ((GET_CODE (op
) == CONST_INT
621 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
622 || register_operand (op
, mode
));
625 /* Return 1 if OP is a constant or any register. */
628 reg_or_const_int_operand (op
, mode
)
630 enum machine_mode mode
;
632 return GET_CODE (op
) == CONST_INT
|| register_operand (op
, mode
);
635 /* Return 1 if OP is an 8-bit constant. */
638 cint8_operand (op
, mode
)
640 enum machine_mode mode ATTRIBUTE_UNUSED
;
642 return ((GET_CODE (op
) == CONST_INT
643 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100));
646 /* Return 1 if the operand is a valid second operand to an add insn. */
649 add_operand (op
, mode
)
651 enum machine_mode mode
;
653 if (GET_CODE (op
) == CONST_INT
)
654 /* Constraints I, J, O and P are covered by K. */
655 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K')
656 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
658 return register_operand (op
, mode
);
661 /* Return 1 if the operand is a valid second operand to a sign-extending
665 sext_add_operand (op
, mode
)
667 enum machine_mode mode
;
669 if (GET_CODE (op
) == CONST_INT
)
670 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
671 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'));
673 return reg_not_elim_operand (op
, mode
);
676 /* Return 1 if OP is the constant 4 or 8. */
679 const48_operand (op
, mode
)
681 enum machine_mode mode ATTRIBUTE_UNUSED
;
683 return (GET_CODE (op
) == CONST_INT
684 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
687 /* Return 1 if OP is a valid first operand to an AND insn. */
690 and_operand (op
, mode
)
692 enum machine_mode mode
;
694 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
695 return (zap_mask (CONST_DOUBLE_LOW (op
))
696 && zap_mask (CONST_DOUBLE_HIGH (op
)));
698 if (GET_CODE (op
) == CONST_INT
)
699 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
700 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
701 || zap_mask (INTVAL (op
)));
703 return register_operand (op
, mode
);
706 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
709 or_operand (op
, mode
)
711 enum machine_mode mode
;
713 if (GET_CODE (op
) == CONST_INT
)
714 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
715 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100);
717 return register_operand (op
, mode
);
720 /* Return 1 if OP is a constant that is the width, in bits, of an integral
721 mode smaller than DImode. */
724 mode_width_operand (op
, mode
)
726 enum machine_mode mode ATTRIBUTE_UNUSED
;
728 return (GET_CODE (op
) == CONST_INT
729 && (INTVAL (op
) == 8 || INTVAL (op
) == 16
730 || INTVAL (op
) == 32 || INTVAL (op
) == 64));
733 /* Return 1 if OP is a constant that is the width of an integral machine mode
734 smaller than an integer. */
737 mode_mask_operand (op
, mode
)
739 enum machine_mode mode ATTRIBUTE_UNUSED
;
741 if (GET_CODE (op
) == CONST_INT
)
743 HOST_WIDE_INT value
= INTVAL (op
);
749 if (value
== 0xffffffff)
754 else if (HOST_BITS_PER_WIDE_INT
== 32 && GET_CODE (op
) == CONST_DOUBLE
)
756 if (CONST_DOUBLE_LOW (op
) == 0xffffffff && CONST_DOUBLE_HIGH (op
) == 0)
763 /* Return 1 if OP is a multiple of 8 less than 64. */
766 mul8_operand (op
, mode
)
768 enum machine_mode mode ATTRIBUTE_UNUSED
;
770 return (GET_CODE (op
) == CONST_INT
771 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
772 && (INTVAL (op
) & 7) == 0);
775 /* Return 1 if OP is the zero constant for MODE. */
778 const0_operand (op
, mode
)
780 enum machine_mode mode
;
782 return op
== CONST0_RTX (mode
);
785 /* Return 1 if OP is a hard floating-point register. */
788 hard_fp_register_operand (op
, mode
)
790 enum machine_mode mode
;
792 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
795 if (GET_CODE (op
) == SUBREG
)
796 op
= SUBREG_REG (op
);
797 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == FLOAT_REGS
;
800 /* Return 1 if OP is a hard general register. */
803 hard_int_register_operand (op
, mode
)
805 enum machine_mode mode
;
807 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
810 if (GET_CODE (op
) == SUBREG
)
811 op
= SUBREG_REG (op
);
812 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
;
815 /* Return 1 if OP is a register or a constant integer. */
819 reg_or_cint_operand (op
, mode
)
821 enum machine_mode mode
;
823 return (GET_CODE (op
) == CONST_INT
824 || register_operand (op
, mode
));
827 /* Return 1 if OP is something that can be reloaded into a register;
828 if it is a MEM, it need not be valid. */
831 some_operand (op
, mode
)
833 enum machine_mode mode
;
835 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
838 switch (GET_CODE (op
))
852 return some_operand (SUBREG_REG (op
), VOIDmode
);
861 /* Likewise, but don't accept constants. */
864 some_ni_operand (op
, mode
)
866 enum machine_mode mode
;
868 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
871 if (GET_CODE (op
) == SUBREG
)
872 op
= SUBREG_REG (op
);
874 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == MEM
);
877 /* Return 1 if OP is a valid operand for the source of a move insn. */
880 input_operand (op
, mode
)
882 enum machine_mode mode
;
884 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
887 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
890 switch (GET_CODE (op
))
895 if (TARGET_EXPLICIT_RELOCS
)
897 /* We don't split symbolic operands into something unintelligable
898 until after reload, but we do not wish non-small, non-global
899 symbolic operands to be reconstructed from their high/lo_sum
901 return (small_symbolic_operand (op
, mode
)
902 || global_symbolic_operand (op
, mode
)
903 || gotdtp_symbolic_operand (op
, mode
)
904 || gottp_symbolic_operand (op
, mode
));
907 /* This handles both the Windows/NT and OSF cases. */
908 return mode
== ptr_mode
|| mode
== DImode
;
911 return (TARGET_EXPLICIT_RELOCS
912 && local_symbolic_operand (XEXP (op
, 0), mode
));
919 if (register_operand (op
, mode
))
921 /* ... fall through ... */
923 return ((TARGET_BWX
|| (mode
!= HImode
&& mode
!= QImode
))
924 && general_operand (op
, mode
));
928 return op
== CONST0_RTX (mode
);
931 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
943 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
944 file, and in the same section as the current function. */
947 current_file_function_operand (op
, mode
)
949 enum machine_mode mode ATTRIBUTE_UNUSED
;
951 if (GET_CODE (op
) != SYMBOL_REF
)
954 /* Easy test for recursion. */
955 if (op
== XEXP (DECL_RTL (current_function_decl
), 0))
958 /* Otherwise, we need the DECL for the SYMBOL_REF, which we can't get.
959 So SYMBOL_REF_FLAG has been declared to imply that the function is
960 in the default text section. So we must also check that the current
961 function is also in the text section. */
962 if (SYMBOL_REF_FLAG (op
) && decl_in_text_section (current_function_decl
))
968 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
971 direct_call_operand (op
, mode
)
973 enum machine_mode mode
;
975 /* Must be defined in this file. */
976 if (! current_file_function_operand (op
, mode
))
979 /* If profiling is implemented via linker tricks, we can't jump
980 to the nogp alternate entry point. */
981 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
982 but is approximately correct for the OSF ABIs. Don't know
983 what to do for VMS, NT, or UMK. */
984 if (! TARGET_PROFILING_NEEDS_GP
985 && ! current_function_profile
)
991 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
992 a (non-tls) variable known to be defined in this file. */
995 local_symbolic_operand (op
, mode
)
997 enum machine_mode mode
;
1001 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1004 if (GET_CODE (op
) == LABEL_REF
)
1007 if (GET_CODE (op
) == CONST
1008 && GET_CODE (XEXP (op
, 0)) == PLUS
1009 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1010 op
= XEXP (XEXP (op
, 0), 0);
1012 if (GET_CODE (op
) != SYMBOL_REF
)
1015 /* Easy pickings. */
1016 if (CONSTANT_POOL_ADDRESS_P (op
) || STRING_POOL_ADDRESS_P (op
))
1019 /* ??? SYMBOL_REF_FLAG is set for local function symbols, but we
1020 run into problems with the rtl inliner in that the symbol was
1021 once external, but is local after inlining, which results in
1022 unrecognizable insns. */
1026 /* If @[LS], then alpha_encode_section_info sez it's local. */
1027 if (str
[0] == '@' && (str
[1] == 'L' || str
[1] == 'S'))
1030 /* If *$, then ASM_GENERATE_INTERNAL_LABEL sez it's local. */
1031 if (str
[0] == '*' && str
[1] == '$')
1037 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1038 known to be defined in this file in the small data area. */
1041 small_symbolic_operand (op
, mode
)
1043 enum machine_mode mode ATTRIBUTE_UNUSED
;
1047 if (! TARGET_SMALL_DATA
)
1050 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1053 if (GET_CODE (op
) == CONST
1054 && GET_CODE (XEXP (op
, 0)) == PLUS
1055 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1056 op
= XEXP (XEXP (op
, 0), 0);
1058 if (GET_CODE (op
) != SYMBOL_REF
)
1061 if (CONSTANT_POOL_ADDRESS_P (op
))
1062 return GET_MODE_SIZE (get_pool_mode (op
)) <= (unsigned) g_switch_value
;
1066 return str
[0] == '@' && str
[1] == 'S';
1070 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1071 not known (or known not) to be defined in this file. */
1074 global_symbolic_operand (op
, mode
)
1076 enum machine_mode mode
;
1080 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1083 if (GET_CODE (op
) == CONST
1084 && GET_CODE (XEXP (op
, 0)) == PLUS
1085 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1086 op
= XEXP (XEXP (op
, 0), 0);
1088 if (GET_CODE (op
) != SYMBOL_REF
)
1091 if (local_symbolic_operand (op
, mode
))
1094 /* Also verify that it's not a TLS symbol. */
1096 return str
[0] != '%' && str
[0] != '@';
1099 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
1102 call_operand (op
, mode
)
1104 enum machine_mode mode
;
1109 if (GET_CODE (op
) == REG
)
1113 /* Disallow virtual registers to cope with pathalogical test cases
1114 such as compile/930117-1.c in which the virtual reg decomposes
1115 to the frame pointer. Which is a hard reg that is not $27. */
1116 return (REGNO (op
) == 27 || REGNO (op
) > LAST_VIRTUAL_REGISTER
);
1121 if (TARGET_ABI_UNICOSMK
)
1123 if (GET_CODE (op
) == SYMBOL_REF
)
1129 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1130 possibly with an offset. */
1133 symbolic_operand (op
, mode
)
1135 enum machine_mode mode
;
1137 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1139 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1141 if (GET_CODE (op
) == CONST
1142 && GET_CODE (XEXP (op
,0)) == PLUS
1143 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1144 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1149 /* Return true if OP is valid for a particular TLS relocation. */
1152 tls_symbolic_operand_1 (op
, mode
, size
, unspec
)
1154 enum machine_mode mode
;
1160 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1163 if (GET_CODE (op
) != CONST
)
1167 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
1169 op
= XVECEXP (op
, 0, 0);
1171 if (GET_CODE (op
) != SYMBOL_REF
)
1180 else if (str
[0] == '@')
1182 if (alpha_tls_size
> size
)
1188 letter
= (unspec
== UNSPEC_DTPREL
? 'D' : 'T');
1190 return str
[1] == letter
;
1193 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1196 dtp16_symbolic_operand (op
, mode
)
1198 enum machine_mode mode
;
1200 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_DTPREL
);
1203 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1206 dtp32_symbolic_operand (op
, mode
)
1208 enum machine_mode mode
;
1210 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_DTPREL
);
1213 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1216 gotdtp_symbolic_operand (op
, mode
)
1218 enum machine_mode mode
;
1220 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_DTPREL
);
1223 /* Return true if OP is valid for 16-bit TP relative relocations. */
1226 tp16_symbolic_operand (op
, mode
)
1228 enum machine_mode mode
;
1230 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_TPREL
);
1233 /* Return true if OP is valid for 32-bit TP relative relocations. */
1236 tp32_symbolic_operand (op
, mode
)
1238 enum machine_mode mode
;
1240 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_TPREL
);
1243 /* Return true if OP is valid for 64-bit TP relative relocations. */
1246 gottp_symbolic_operand (op
, mode
)
1248 enum machine_mode mode
;
1250 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_TPREL
);
1253 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1254 comparisons are valid in which insn. */
1257 alpha_comparison_operator (op
, mode
)
1259 enum machine_mode mode
;
1261 enum rtx_code code
= GET_CODE (op
);
1263 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1266 return (code
== EQ
|| code
== LE
|| code
== LT
1267 || code
== LEU
|| code
== LTU
);
1270 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1271 Here we know which comparisons are valid in which insn. */
1274 alpha_zero_comparison_operator (op
, mode
)
1276 enum machine_mode mode
;
1278 enum rtx_code code
= GET_CODE (op
);
1280 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1283 return (code
== EQ
|| code
== NE
|| code
== LE
|| code
== LT
1284 || code
== LEU
|| code
== LTU
);
1287 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1290 alpha_swapped_comparison_operator (op
, mode
)
1292 enum machine_mode mode
;
1294 enum rtx_code code
= GET_CODE (op
);
1296 if ((mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1297 || GET_RTX_CLASS (code
) != '<')
1300 code
= swap_condition (code
);
1301 return (code
== EQ
|| code
== LE
|| code
== LT
1302 || code
== LEU
|| code
== LTU
);
1305 /* Return 1 if OP is a signed comparison operation. */
1308 signed_comparison_operator (op
, mode
)
1310 enum machine_mode mode ATTRIBUTE_UNUSED
;
1312 enum rtx_code code
= GET_CODE (op
);
1314 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1317 return (code
== EQ
|| code
== NE
1318 || code
== LE
|| code
== LT
1319 || code
== GE
|| code
== GT
);
1322 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1323 Here we know which comparisons are valid in which insn. */
1326 alpha_fp_comparison_operator (op
, mode
)
1328 enum machine_mode mode
;
1330 enum rtx_code code
= GET_CODE (op
);
1332 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1335 return (code
== EQ
|| code
== LE
|| code
== LT
|| code
== UNORDERED
);
1338 /* Return 1 if this is a divide or modulus operator. */
1341 divmod_operator (op
, mode
)
1343 enum machine_mode mode ATTRIBUTE_UNUSED
;
1345 switch (GET_CODE (op
))
1347 case DIV
: case MOD
: case UDIV
: case UMOD
:
1357 /* Return 1 if this memory address is a known aligned register plus
1358 a constant. It must be a valid address. This means that we can do
1359 this as an aligned reference plus some offset.
1361 Take into account what reload will do. */
1364 aligned_memory_operand (op
, mode
)
1366 enum machine_mode mode
;
1370 if (reload_in_progress
)
1373 if (GET_CODE (tmp
) == SUBREG
)
1374 tmp
= SUBREG_REG (tmp
);
1375 if (GET_CODE (tmp
) == REG
1376 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1378 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1384 if (GET_CODE (op
) != MEM
1385 || GET_MODE (op
) != mode
)
1389 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1390 sorts of constructs. Dig for the real base register. */
1391 if (reload_in_progress
1392 && GET_CODE (op
) == PLUS
1393 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1394 base
= XEXP (XEXP (op
, 0), 0);
1397 if (! memory_address_p (mode
, op
))
1399 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1402 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) >= 32);
1405 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1408 unaligned_memory_operand (op
, mode
)
1410 enum machine_mode mode
;
1414 if (reload_in_progress
)
1417 if (GET_CODE (tmp
) == SUBREG
)
1418 tmp
= SUBREG_REG (tmp
);
1419 if (GET_CODE (tmp
) == REG
1420 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1422 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1428 if (GET_CODE (op
) != MEM
1429 || GET_MODE (op
) != mode
)
1433 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1434 sorts of constructs. Dig for the real base register. */
1435 if (reload_in_progress
1436 && GET_CODE (op
) == PLUS
1437 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1438 base
= XEXP (XEXP (op
, 0), 0);
1441 if (! memory_address_p (mode
, op
))
1443 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1446 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) < 32);
1449 /* Return 1 if OP is either a register or an unaligned memory location. */
1452 reg_or_unaligned_mem_operand (op
, mode
)
1454 enum machine_mode mode
;
1456 return register_operand (op
, mode
) || unaligned_memory_operand (op
, mode
);
1459 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1462 any_memory_operand (op
, mode
)
1464 enum machine_mode mode ATTRIBUTE_UNUSED
;
1466 return (GET_CODE (op
) == MEM
1467 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
1468 || (reload_in_progress
&& GET_CODE (op
) == REG
1469 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1470 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
1471 && GET_CODE (SUBREG_REG (op
)) == REG
1472 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
1475 /* Returns 1 if OP is not an eliminable register.
1477 This exists to cure a pathological abort in the s8addq (et al) patterns,
1479 long foo () { long t; bar(); return (long) &t * 26107; }
1481 which run afoul of a hack in reload to cure a (presumably) similar
1482 problem with lea-type instructions on other targets. But there is
1483 one of us and many of them, so work around the problem by selectively
1484 preventing combine from making the optimization. */
1487 reg_not_elim_operand (op
, mode
)
1489 enum machine_mode mode
;
1492 if (GET_CODE (op
) == SUBREG
)
1493 inner
= SUBREG_REG (op
);
1494 if (inner
== frame_pointer_rtx
|| inner
== arg_pointer_rtx
)
1497 return register_operand (op
, mode
);
1500 /* Return 1 is OP is a memory location that is not a reference (using
1501 an AND) to an unaligned location. Take into account what reload
1505 normal_memory_operand (op
, mode
)
1507 enum machine_mode mode ATTRIBUTE_UNUSED
;
1509 if (reload_in_progress
)
1512 if (GET_CODE (tmp
) == SUBREG
)
1513 tmp
= SUBREG_REG (tmp
);
1514 if (GET_CODE (tmp
) == REG
1515 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1517 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1519 /* This may not have been assigned an equivalent address if it will
1520 be eliminated. In that case, it doesn't matter what we do. */
1526 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) != AND
;
1529 /* Accept a register, but not a subreg of any kind. This allows us to
1530 avoid pathological cases in reload wrt data movement common in
1531 int->fp conversion. */
1534 reg_no_subreg_operand (op
, mode
)
1536 enum machine_mode mode
;
1538 if (GET_CODE (op
) != REG
)
1540 return register_operand (op
, mode
);
1543 /* Recognize an addition operation that includes a constant. Used to
1544 convince reload to canonize (plus (plus reg c1) c2) during register
1548 addition_operation (op
, mode
)
1550 enum machine_mode mode
;
1552 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1554 if (GET_CODE (op
) == PLUS
1555 && register_operand (XEXP (op
, 0), mode
)
1556 && GET_CODE (XEXP (op
, 1)) == CONST_INT
1557 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op
, 1)), 'K'))
1562 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1563 the range defined for C in [I-P]. */
1566 alpha_const_ok_for_letter_p (value
, c
)
1567 HOST_WIDE_INT value
;
1573 /* An unsigned 8 bit constant. */
1574 return (unsigned HOST_WIDE_INT
) value
< 0x100;
1576 /* The constant zero. */
1579 /* A signed 16 bit constant. */
1580 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
1582 /* A shifted signed 16 bit constant appropriate for LDAH. */
1583 return ((value
& 0xffff) == 0
1584 && ((value
) >> 31 == -1 || value
>> 31 == 0));
1586 /* A constant that can be AND'ed with using a ZAP insn. */
1587 return zap_mask (value
);
1589 /* A complemented unsigned 8 bit constant. */
1590 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
1592 /* A negated unsigned 8 bit constant. */
1593 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
1595 /* The constant 1, 2 or 3. */
1596 return value
== 1 || value
== 2 || value
== 3;
1603 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1604 matches for C in [GH]. */
1607 alpha_const_double_ok_for_letter_p (value
, c
)
1614 /* The floating point zero constant. */
1615 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
1616 && value
== CONST0_RTX (GET_MODE (value
)));
1619 /* A valid operand of a ZAP insn. */
1620 return (GET_MODE (value
) == VOIDmode
1621 && zap_mask (CONST_DOUBLE_LOW (value
))
1622 && zap_mask (CONST_DOUBLE_HIGH (value
)));
1629 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1633 alpha_extra_constraint (value
, c
)
1640 return normal_memory_operand (value
, VOIDmode
);
1642 return direct_call_operand (value
, Pmode
);
1644 return (GET_CODE (value
) == CONST_INT
1645 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
1647 return GET_CODE (value
) == HIGH
;
1649 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
1651 return (GET_CODE (value
) == CONST_VECTOR
1652 && value
== CONST0_RTX (GET_MODE (value
)));
1658 /* Return 1 if this function can directly return via $26. */
1663 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
1665 && alpha_sa_size () == 0
1666 && get_frame_size () == 0
1667 && current_function_outgoing_args_size
== 0
1668 && current_function_pretend_args_size
== 0);
1671 /* Return the ADDR_VEC associated with a tablejump insn. */
1674 alpha_tablejump_addr_vec (insn
)
1679 tmp
= JUMP_LABEL (insn
);
1682 tmp
= NEXT_INSN (tmp
);
1685 if (GET_CODE (tmp
) == JUMP_INSN
1686 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
1687 return PATTERN (tmp
);
1691 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1694 alpha_tablejump_best_label (insn
)
1697 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
1698 rtx best_label
= NULL_RTX
;
1700 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1701 there for edge frequency counts from profile data. */
1705 int n_labels
= XVECLEN (jump_table
, 1);
1706 int best_count
= -1;
1709 for (i
= 0; i
< n_labels
; i
++)
1713 for (j
= i
+ 1; j
< n_labels
; j
++)
1714 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
1715 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
1718 if (count
> best_count
)
1719 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
1723 return best_label
? best_label
: const0_rtx
;
1726 /* Return the TLS model to use for SYMBOL. */
1728 static enum tls_model
1729 tls_symbolic_operand_type (symbol
)
1734 if (GET_CODE (symbol
) != SYMBOL_REF
)
1736 str
= XSTR (symbol
, 0);
1740 /* ??? Be prepared for -ftls-model=local-dynamic. Perhaps we shouldn't
1741 have separately encoded local-ness. On well, maybe the user will use
1742 attribute visibility next time. At least we don't crash... */
1743 if (str
[1] == 'G' || str
[1] == 'D')
1744 return TLS_MODEL_GLOBAL_DYNAMIC
;
1746 return TLS_MODEL_INITIAL_EXEC
;
1748 else if (str
[0] == '@')
1752 /* Local dynamic is a waste if we're not going to combine
1753 the __tls_get_addr calls. So avoid it if not optimizing. */
1755 return TLS_MODEL_LOCAL_DYNAMIC
;
1757 return TLS_MODEL_GLOBAL_DYNAMIC
;
1761 /* 64-bit local exec is the same as initial exec except without
1762 the dynamic relocation. In either case we use a got entry. */
1763 if (alpha_tls_size
== 64)
1764 return TLS_MODEL_INITIAL_EXEC
;
1766 return TLS_MODEL_LOCAL_EXEC
;
1774 /* Return true if the function DECL will be placed in the default text
1776 /* ??? Ideally we'd be able to always move from a SYMBOL_REF back to the
1777 decl, as that would allow us to determine if two functions are in the
1778 same section, which is what we really want to know. */
1781 decl_in_text_section (decl
)
1784 return (DECL_SECTION_NAME (decl
) == NULL_TREE
1785 && ! (flag_function_sections
1786 || (targetm
.have_named_sections
1787 && DECL_ONE_ONLY (decl
))));
1790 /* Return true if EXP should be placed in the small data section. */
1793 alpha_in_small_data_p (exp
)
1796 /* We want to merge strings, so we never consider them small data. */
1797 if (TREE_CODE (exp
) == STRING_CST
)
1800 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
1802 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
1803 if (strcmp (section
, ".sdata") == 0
1804 || strcmp (section
, ".sbss") == 0)
1809 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
1811 /* If this is an incomplete type with size 0, then we can't put it
1812 in sdata because it might be too big when completed. */
1813 if (size
> 0 && size
<= g_switch_value
)
1820 /* If we are referencing a function that is static, make the SYMBOL_REF
1821 special. We use this to see indicate we can branch to this function
1822 without setting PV or restoring GP.
1824 If this is a variable that is known to be defined locally, add "@v"
1825 to the name. If in addition the variable is to go in .sdata/.sbss,
1826 then add "@s" instead. */
1829 alpha_encode_section_info (decl
, first
)
1831 int first ATTRIBUTE_UNUSED
;
1833 const char *symbol_str
;
1838 rtl
= DECL_P (decl
) ? DECL_RTL (decl
) : TREE_CST_RTL (decl
);
1840 /* Careful not to prod global register variables. */
1841 if (GET_CODE (rtl
) != MEM
)
1843 symbol
= XEXP (rtl
, 0);
1844 if (GET_CODE (symbol
) != SYMBOL_REF
)
1847 if (TREE_CODE (decl
) == FUNCTION_DECL
)
1849 /* We mark public functions once they are emitted; otherwise we
1850 don't know that they exist in this unit of translation. */
1851 if (TREE_PUBLIC (decl
))
1854 /* Do not mark functions that are not in .text; otherwise we
1855 don't know that they are near enough for a direct branch. */
1856 if (! decl_in_text_section (decl
))
1859 SYMBOL_REF_FLAG (symbol
) = 1;
1863 /* Early out if we're not going to do anything with this data. */
1864 if (! TARGET_EXPLICIT_RELOCS
)
1867 symbol_str
= XSTR (symbol
, 0);
1869 /* A variable is considered "local" if it is defined in this module. */
1870 is_local
= (*targetm
.binds_local_p
) (decl
);
1872 /* Care for TLS variables. */
1873 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL (decl
))
1875 enum tls_model kind
;
1879 kind
= TLS_MODEL_LOCAL_EXEC
;
1881 kind
= TLS_MODEL_INITIAL_EXEC
;
1884 kind
= TLS_MODEL_LOCAL_DYNAMIC
;
1886 kind
= TLS_MODEL_GLOBAL_DYNAMIC
;
1887 if (kind
< flag_tls_default
)
1888 kind
= flag_tls_default
;
1892 case TLS_MODEL_GLOBAL_DYNAMIC
:
1895 case TLS_MODEL_LOCAL_DYNAMIC
:
1898 case TLS_MODEL_INITIAL_EXEC
:
1899 case TLS_MODEL_LOCAL_EXEC
:
1906 /* Determine if DECL will wind up in .sdata/.sbss. */
1907 if (alpha_in_small_data_p (decl
))
1913 /* Finally, encode this into the symbol string. */
1919 if (symbol_str
[0] == (is_local
? '@' : '%'))
1921 if (symbol_str
[1] == encoding
)
1926 len
= strlen (symbol_str
) + 1;
1927 newstr
= alloca (len
+ 2);
1929 newstr
[0] = (is_local
? '@' : '%');
1930 newstr
[1] = encoding
;
1931 memcpy (newstr
+ 2, symbol_str
, len
);
1933 XSTR (symbol
, 0) = ggc_alloc_string (newstr
, len
+ 2 - 1);
1937 /* Undo the effects of the above. */
1940 alpha_strip_name_encoding (str
)
1943 if (str
[0] == '@' || str
[0] == '%')
1950 #if TARGET_ABI_OPEN_VMS
1952 alpha_linkage_symbol_p (symname
)
1953 const char *symname
;
1955 int symlen
= strlen (symname
);
1958 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
1963 #define LINKAGE_SYMBOL_REF_P(X) \
1964 ((GET_CODE (X) == SYMBOL_REF \
1965 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1966 || (GET_CODE (X) == CONST \
1967 && GET_CODE (XEXP (X, 0)) == PLUS \
1968 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1969 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1972 /* legitimate_address_p recognizes an RTL expression that is a valid
1973 memory address for an instruction. The MODE argument is the
1974 machine mode for the MEM expression that wants to use this address.
1976 For Alpha, we have either a constant address or the sum of a
1977 register and a constant address, or just a register. For DImode,
1978 any of those forms can be surrounded with an AND that clear the
1979 low-order three bits; this is an "unaligned" access. */
1982 alpha_legitimate_address_p (mode
, x
, strict
)
1983 enum machine_mode mode
;
1987 /* If this is an ldq_u type address, discard the outer AND. */
1989 && GET_CODE (x
) == AND
1990 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1991 && INTVAL (XEXP (x
, 1)) == -8)
1994 /* Discard non-paradoxical subregs. */
1995 if (GET_CODE (x
) == SUBREG
1996 && (GET_MODE_SIZE (GET_MODE (x
))
1997 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2000 /* Unadorned general registers are valid. */
2003 ? STRICT_REG_OK_FOR_BASE_P (x
)
2004 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
2007 /* Constant addresses (i.e. +/- 32k) are valid. */
2008 if (CONSTANT_ADDRESS_P (x
))
2011 #if TARGET_ABI_OPEN_VMS
2012 if (LINKAGE_SYMBOL_REF_P (x
))
2016 /* Register plus a small constant offset is valid. */
2017 if (GET_CODE (x
) == PLUS
)
2019 rtx ofs
= XEXP (x
, 1);
2022 /* Discard non-paradoxical subregs. */
2023 if (GET_CODE (x
) == SUBREG
2024 && (GET_MODE_SIZE (GET_MODE (x
))
2025 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2031 && NONSTRICT_REG_OK_FP_BASE_P (x
)
2032 && GET_CODE (ofs
) == CONST_INT
)
2035 ? STRICT_REG_OK_FOR_BASE_P (x
)
2036 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
2037 && CONSTANT_ADDRESS_P (ofs
))
2040 else if (GET_CODE (x
) == ADDRESSOF
2041 && GET_CODE (ofs
) == CONST_INT
)
2045 /* If we're managing explicit relocations, LO_SUM is valid, as
2046 are small data symbols. */
2047 else if (TARGET_EXPLICIT_RELOCS
)
2049 if (small_symbolic_operand (x
, Pmode
))
2052 if (GET_CODE (x
) == LO_SUM
)
2054 rtx ofs
= XEXP (x
, 1);
2057 /* Discard non-paradoxical subregs. */
2058 if (GET_CODE (x
) == SUBREG
2059 && (GET_MODE_SIZE (GET_MODE (x
))
2060 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2063 /* Must have a valid base register. */
2066 ? STRICT_REG_OK_FOR_BASE_P (x
)
2067 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
2070 /* The symbol must be local. */
2071 if (local_symbolic_operand (ofs
, Pmode
)
2072 || dtp32_symbolic_operand (ofs
, Pmode
)
2073 || tp32_symbolic_operand (ofs
, Pmode
))
2081 /* Try machine-dependent ways of modifying an illegitimate address
2082 to be legitimate. If we find one, return the new, valid address. */
2085 alpha_legitimize_address (x
, scratch
, mode
)
2088 enum machine_mode mode ATTRIBUTE_UNUSED
;
2090 HOST_WIDE_INT addend
;
2092 /* If the address is (plus reg const_int) and the CONST_INT is not a
2093 valid offset, compute the high part of the constant and add it to
2094 the register. Then our address is (plus temp low-part-const). */
2095 if (GET_CODE (x
) == PLUS
2096 && GET_CODE (XEXP (x
, 0)) == REG
2097 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2098 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
2100 addend
= INTVAL (XEXP (x
, 1));
2105 /* If the address is (const (plus FOO const_int)), find the low-order
2106 part of the CONST_INT. Then load FOO plus any high-order part of the
2107 CONST_INT into a register. Our address is (plus reg low-part-const).
2108 This is done to reduce the number of GOT entries. */
2110 && GET_CODE (x
) == CONST
2111 && GET_CODE (XEXP (x
, 0)) == PLUS
2112 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2114 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
2115 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
2119 /* If we have a (plus reg const), emit the load as in (2), then add
2120 the two registers, and finally generate (plus reg low-part-const) as
2123 && GET_CODE (x
) == PLUS
2124 && GET_CODE (XEXP (x
, 0)) == REG
2125 && GET_CODE (XEXP (x
, 1)) == CONST
2126 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
2127 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
2129 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
2130 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
2131 XEXP (XEXP (XEXP (x
, 1), 0), 0),
2132 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
2136 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
2137 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
2139 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
2141 switch (tls_symbolic_operand_type (x
))
2143 case TLS_MODEL_GLOBAL_DYNAMIC
:
2146 r0
= gen_rtx_REG (Pmode
, 0);
2147 r16
= gen_rtx_REG (Pmode
, 16);
2148 tga
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
2149 dest
= gen_reg_rtx (Pmode
);
2150 seq
= GEN_INT (alpha_next_sequence_number
++);
2152 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
2153 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
2154 insn
= emit_call_insn (insn
);
2155 CONST_OR_PURE_CALL_P (insn
) = 1;
2156 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2158 insn
= get_insns ();
2161 emit_libcall_block (insn
, dest
, r0
, x
);
2164 case TLS_MODEL_LOCAL_DYNAMIC
:
2167 r0
= gen_rtx_REG (Pmode
, 0);
2168 r16
= gen_rtx_REG (Pmode
, 16);
2169 tga
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
2170 scratch
= gen_reg_rtx (Pmode
);
2171 seq
= GEN_INT (alpha_next_sequence_number
++);
2173 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
2174 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
2175 insn
= emit_call_insn (insn
);
2176 CONST_OR_PURE_CALL_P (insn
) = 1;
2177 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2179 insn
= get_insns ();
2182 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2183 UNSPEC_TLSLDM_CALL
);
2184 emit_libcall_block (insn
, scratch
, r0
, eqv
);
2186 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
2187 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2189 if (alpha_tls_size
== 64)
2191 dest
= gen_reg_rtx (Pmode
);
2192 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
2193 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
2196 if (alpha_tls_size
== 32)
2198 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2199 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
2200 scratch
= gen_reg_rtx (Pmode
);
2201 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
2203 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
2205 case TLS_MODEL_INITIAL_EXEC
:
2206 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2207 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2208 tp
= gen_reg_rtx (Pmode
);
2209 scratch
= gen_reg_rtx (Pmode
);
2210 dest
= gen_reg_rtx (Pmode
);
2212 emit_insn (gen_load_tp (tp
));
2213 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
2214 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
2217 case TLS_MODEL_LOCAL_EXEC
:
2218 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2219 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2220 tp
= gen_reg_rtx (Pmode
);
2222 emit_insn (gen_load_tp (tp
));
2223 if (alpha_tls_size
== 32)
2225 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2226 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
2227 tp
= gen_reg_rtx (Pmode
);
2228 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
2230 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
2233 if (local_symbolic_operand (x
, Pmode
))
2235 if (small_symbolic_operand (x
, Pmode
))
2239 if (!no_new_pseudos
)
2240 scratch
= gen_reg_rtx (Pmode
);
2241 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
2242 gen_rtx_HIGH (Pmode
, x
)));
2243 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
2252 HOST_WIDE_INT low
, high
;
2254 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
2256 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2260 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
2261 (no_new_pseudos
? scratch
: NULL_RTX
),
2262 1, OPTAB_LIB_WIDEN
);
2264 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
2265 (no_new_pseudos
? scratch
: NULL_RTX
),
2266 1, OPTAB_LIB_WIDEN
);
2268 return plus_constant (x
, low
);
2272 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
2273 small symbolic operand until after reload. At which point we need
2274 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
2275 so that sched2 has the proper dependency information. */
2278 some_small_symbolic_operand (x
, mode
)
2280 enum machine_mode mode ATTRIBUTE_UNUSED
;
2282 return for_each_rtx (&x
, some_small_symbolic_operand_1
, NULL
);
2286 some_small_symbolic_operand_1 (px
, data
)
2288 void *data ATTRIBUTE_UNUSED
;
2292 /* Don't re-split. */
2293 if (GET_CODE (x
) == LO_SUM
)
2296 return small_symbolic_operand (x
, Pmode
) != 0;
2300 split_small_symbolic_operand (x
)
2304 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
2309 split_small_symbolic_operand_1 (px
, data
)
2311 void *data ATTRIBUTE_UNUSED
;
2315 /* Don't re-split. */
2316 if (GET_CODE (x
) == LO_SUM
)
2319 if (small_symbolic_operand (x
, Pmode
))
2321 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
2329 /* Try a machine-dependent way of reloading an illegitimate address
2330 operand. If we find one, push the reload and return the new rtx. */
2333 alpha_legitimize_reload_address (x
, mode
, opnum
, type
, ind_levels
)
2335 enum machine_mode mode ATTRIBUTE_UNUSED
;
2338 int ind_levels ATTRIBUTE_UNUSED
;
2340 /* We must recognize output that we have already generated ourselves. */
2341 if (GET_CODE (x
) == PLUS
2342 && GET_CODE (XEXP (x
, 0)) == PLUS
2343 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2344 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2345 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2347 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2348 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2353 /* We wish to handle large displacements off a base register by
2354 splitting the addend across an ldah and the mem insn. This
2355 cuts number of extra insns needed from 3 to 1. */
2356 if (GET_CODE (x
) == PLUS
2357 && GET_CODE (XEXP (x
, 0)) == REG
2358 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2359 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
2360 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2362 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2363 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
2365 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2367 /* Check for 32-bit overflow. */
2368 if (high
+ low
!= val
)
2371 /* Reload the high part into a base reg; leave the low part
2372 in the mem directly. */
2373 x
= gen_rtx_PLUS (GET_MODE (x
),
2374 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
2378 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2379 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2387 /* REF is an alignable memory location. Place an aligned SImode
2388 reference into *PALIGNED_MEM and the number of bits to shift into
2389 *PBITNUM. SCRATCH is a free register for use in reloading out
2390 of range stack slots. */
2393 get_aligned_mem (ref
, paligned_mem
, pbitnum
)
2395 rtx
*paligned_mem
, *pbitnum
;
2398 HOST_WIDE_INT offset
= 0;
2400 if (GET_CODE (ref
) != MEM
)
2403 if (reload_in_progress
2404 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2406 base
= find_replacement (&XEXP (ref
, 0));
2408 if (! memory_address_p (GET_MODE (ref
), base
))
2413 base
= XEXP (ref
, 0);
2416 if (GET_CODE (base
) == PLUS
)
2417 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2420 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
2422 if (WORDS_BIG_ENDIAN
)
2423 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
2424 + (offset
& 3) * 8));
2426 *pbitnum
= GEN_INT ((offset
& 3) * 8);
2429 /* Similar, but just get the address. Handle the two reload cases.
2430 Add EXTRA_OFFSET to the address we return. */
2433 get_unaligned_address (ref
, extra_offset
)
2438 HOST_WIDE_INT offset
= 0;
2440 if (GET_CODE (ref
) != MEM
)
2443 if (reload_in_progress
2444 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2446 base
= find_replacement (&XEXP (ref
, 0));
2448 if (! memory_address_p (GET_MODE (ref
), base
))
2453 base
= XEXP (ref
, 0);
2456 if (GET_CODE (base
) == PLUS
)
2457 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2459 return plus_constant (base
, offset
+ extra_offset
);
2462 /* On the Alpha, all (non-symbolic) constants except zero go into
2463 a floating-point register via memory. Note that we cannot
2464 return anything that is not a subset of CLASS, and that some
2465 symbolic constants cannot be dropped to memory. */
2468 alpha_preferred_reload_class(x
, class)
2470 enum reg_class
class;
2472 /* Zero is present in any register class. */
2473 if (x
== CONST0_RTX (GET_MODE (x
)))
2476 /* These sorts of constants we can easily drop to memory. */
2477 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2479 if (class == FLOAT_REGS
)
2481 if (class == ALL_REGS
)
2482 return GENERAL_REGS
;
2486 /* All other kinds of constants should not (and in the case of HIGH
2487 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2488 secondary reload. */
2490 return (class == ALL_REGS
? GENERAL_REGS
: class);
2495 /* Loading and storing HImode or QImode values to and from memory
2496 usually requires a scratch register. The exceptions are loading
2497 QImode and HImode from an aligned address to a general register
2498 unless byte instructions are permitted.
2500 We also cannot load an unaligned address or a paradoxical SUBREG
2501 into an FP register.
2503 We also cannot do integral arithmetic into FP regs, as might result
2504 from register elimination into a DImode fp register. */
2507 secondary_reload_class (class, mode
, x
, in
)
2508 enum reg_class
class;
2509 enum machine_mode mode
;
2513 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
2515 if (GET_CODE (x
) == MEM
2516 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
2517 || (GET_CODE (x
) == SUBREG
2518 && (GET_CODE (SUBREG_REG (x
)) == MEM
2519 || (GET_CODE (SUBREG_REG (x
)) == REG
2520 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
2522 if (!in
|| !aligned_memory_operand(x
, mode
))
2523 return GENERAL_REGS
;
2527 if (class == FLOAT_REGS
)
2529 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
2530 return GENERAL_REGS
;
2532 if (GET_CODE (x
) == SUBREG
2533 && (GET_MODE_SIZE (GET_MODE (x
))
2534 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2535 return GENERAL_REGS
;
2537 if (in
&& INTEGRAL_MODE_P (mode
)
2538 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
2539 return GENERAL_REGS
;
2545 /* Subfunction of the following function. Update the flags of any MEM
2546 found in part of X. */
2549 alpha_set_memflags_1 (x
, in_struct_p
, volatile_p
, unchanging_p
)
2551 int in_struct_p
, volatile_p
, unchanging_p
;
2555 switch (GET_CODE (x
))
2561 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2562 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
2567 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
2572 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
2574 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
2579 MEM_IN_STRUCT_P (x
) = in_struct_p
;
2580 MEM_VOLATILE_P (x
) = volatile_p
;
2581 RTX_UNCHANGING_P (x
) = unchanging_p
;
2582 /* Sadly, we cannot use alias sets because the extra aliasing
2583 produced by the AND interferes. Given that two-byte quantities
2584 are the only thing we would be able to differentiate anyway,
2585 there does not seem to be any point in convoluting the early
2586 out of the alias check. */
2594 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2595 generated to perform a memory operation, look for any MEMs in either
2596 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2597 volatile flags from REF into each of the MEMs found. If REF is not
2598 a MEM, don't do anything. */
2601 alpha_set_memflags (insn
, ref
)
2605 int in_struct_p
, volatile_p
, unchanging_p
;
2607 if (GET_CODE (ref
) != MEM
)
2610 in_struct_p
= MEM_IN_STRUCT_P (ref
);
2611 volatile_p
= MEM_VOLATILE_P (ref
);
2612 unchanging_p
= RTX_UNCHANGING_P (ref
);
2614 /* This is only called from alpha.md, after having had something
2615 generated from one of the insn patterns. So if everything is
2616 zero, the pattern is already up-to-date. */
2617 if (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
)
2620 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
2623 /* Try to output insns to set TARGET equal to the constant C if it can be
2624 done in less than N insns. Do all computations in MODE. Returns the place
2625 where the output has been placed if it can be done and the insns have been
2626 emitted. If it would take more than N insns, zero is returned and no
2627 insns and emitted. */
2630 alpha_emit_set_const (target
, mode
, c
, n
)
2632 enum machine_mode mode
;
2637 rtx orig_target
= target
;
2640 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2641 can't load this constant in one insn, do this in DImode. */
2642 if (no_new_pseudos
&& mode
== SImode
2643 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
2644 && (result
= alpha_emit_set_const_1 (target
, mode
, c
, 1)) == 0)
2646 target
= gen_lowpart (DImode
, target
);
2650 /* Try 1 insn, then 2, then up to N. */
2651 for (i
= 1; i
<= n
; i
++)
2653 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
);
2656 rtx insn
= get_last_insn ();
2657 rtx set
= single_set (insn
);
2658 if (! CONSTANT_P (SET_SRC (set
)))
2659 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
2664 /* Allow for the case where we changed the mode of TARGET. */
2665 if (result
== target
)
2666 result
= orig_target
;
2671 /* Internal routine for the above to check for N or below insns. */
2674 alpha_emit_set_const_1 (target
, mode
, c
, n
)
2676 enum machine_mode mode
;
2682 /* Use a pseudo if highly optimizing and still generating RTL. */
2684 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
2687 /* If this is a sign-extended 32-bit constant, we can do this in at most
2688 three insns, so do it if we have enough insns left. We always have
2689 a sign-extended 32-bit constant when compiling on a narrow machine. */
2691 if (HOST_BITS_PER_WIDE_INT
!= 64
2692 || c
>> 31 == -1 || c
>> 31 == 0)
2694 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
2695 HOST_WIDE_INT tmp1
= c
- low
;
2696 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
2697 HOST_WIDE_INT extra
= 0;
2699 /* If HIGH will be interpreted as negative but the constant is
2700 positive, we must adjust it to do two ldha insns. */
2702 if ((high
& 0x8000) != 0 && c
>= 0)
2706 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
2709 if (c
== low
|| (low
== 0 && extra
== 0))
2711 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2712 but that meant that we can't handle INT_MIN on 32-bit machines
2713 (like NT/Alpha), because we recurse indefinitely through
2714 emit_move_insn to gen_movdi. So instead, since we know exactly
2715 what we want, create it explicitly. */
2718 target
= gen_reg_rtx (mode
);
2719 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
2722 else if (n
>= 2 + (extra
!= 0))
2724 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16), subtarget
, mode
);
2726 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2727 This means that if we go through expand_binop, we'll try to
2728 generate extensions, etc, which will require new pseudos, which
2729 will fail during some split phases. The SImode add patterns
2730 still exist, but are not named. So build the insns by hand. */
2735 subtarget
= gen_reg_rtx (mode
);
2736 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
2737 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
2743 target
= gen_reg_rtx (mode
);
2744 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
2745 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
2751 /* If we couldn't do it that way, try some other methods. But if we have
2752 no instructions left, don't bother. Likewise, if this is SImode and
2753 we can't make pseudos, we can't do anything since the expand_binop
2754 and expand_unop calls will widen and try to make pseudos. */
2756 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
2759 /* Next, see if we can load a related constant and then shift and possibly
2760 negate it to get the constant we want. Try this once each increasing
2761 numbers of insns. */
2763 for (i
= 1; i
< n
; i
++)
2765 /* First, see if minus some low bits, we've an easy load of
2768 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
2770 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
2771 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
2772 target
, 0, OPTAB_WIDEN
);
2774 /* Next try complementing. */
2775 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
2776 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
2778 /* Next try to form a constant and do a left shift. We can do this
2779 if some low-order bits are zero; the exact_log2 call below tells
2780 us that information. The bits we are shifting out could be any
2781 value, but here we'll just try the 0- and sign-extended forms of
2782 the constant. To try to increase the chance of having the same
2783 constant in more than one insn, start at the highest number of
2784 bits to shift, but try all possibilities in case a ZAPNOT will
2787 if ((bits
= exact_log2 (c
& - c
)) > 0)
2788 for (; bits
> 0; bits
--)
2789 if ((temp
= (alpha_emit_set_const
2790 (subtarget
, mode
, c
>> bits
, i
))) != 0
2791 || ((temp
= (alpha_emit_set_const
2793 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
2795 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
2796 target
, 0, OPTAB_WIDEN
);
2798 /* Now try high-order zero bits. Here we try the shifted-in bits as
2799 all zero and all ones. Be careful to avoid shifting outside the
2800 mode and to avoid shifting outside the host wide int size. */
2801 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2802 confuse the recursive call and set all of the high 32 bits. */
2804 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2805 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
2806 for (; bits
> 0; bits
--)
2807 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2809 || ((temp
= (alpha_emit_set_const
2811 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2814 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
2815 target
, 1, OPTAB_WIDEN
);
2817 /* Now try high-order 1 bits. We get that with a sign-extension.
2818 But one bit isn't enough here. Be careful to avoid shifting outside
2819 the mode and to avoid shifting outside the host wide int size. */
2821 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2822 - floor_log2 (~ c
) - 2)) > 0)
2823 for (; bits
> 0; bits
--)
2824 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2826 || ((temp
= (alpha_emit_set_const
2828 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2831 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
2832 target
, 0, OPTAB_WIDEN
);
2835 #if HOST_BITS_PER_WIDE_INT == 64
2836 /* Finally, see if can load a value into the target that is the same as the
2837 constant except that all bytes that are 0 are changed to be 0xff. If we
2838 can, then we can do a ZAPNOT to obtain the desired constant. */
2841 for (i
= 0; i
< 64; i
+= 8)
2842 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
2843 new |= (HOST_WIDE_INT
) 0xff << i
;
2845 /* We are only called for SImode and DImode. If this is SImode, ensure that
2846 we are sign extended to a full word. */
2849 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2851 if (new != c
&& new != -1
2852 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
2853 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
2854 target
, 0, OPTAB_WIDEN
);
2860 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2861 fall back to a straight forward decomposition. We do this to avoid
2862 exponential run times encountered when looking for longer sequences
2863 with alpha_emit_set_const. */
2866 alpha_emit_set_long_const (target
, c1
, c2
)
2868 HOST_WIDE_INT c1
, c2
;
2870 HOST_WIDE_INT d1
, d2
, d3
, d4
;
2872 /* Decompose the entire word */
2873 #if HOST_BITS_PER_WIDE_INT >= 64
2874 if (c2
!= -(c1
< 0))
2876 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2878 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2879 c1
= (c1
- d2
) >> 32;
2880 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2882 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2886 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2888 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2892 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
2894 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2899 /* Construct the high word */
2902 emit_move_insn (target
, GEN_INT (d4
));
2904 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2907 emit_move_insn (target
, GEN_INT (d3
));
2909 /* Shift it into place */
2910 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2912 /* Add in the low bits. */
2914 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2916 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
2921 /* Expand a move instruction; return true if all work is done.
2922 We don't handle non-bwx subword loads here. */
2925 alpha_expand_mov (mode
, operands
)
2926 enum machine_mode mode
;
2929 /* If the output is not a register, the input must be. */
2930 if (GET_CODE (operands
[0]) == MEM
2931 && ! reg_or_0_operand (operands
[1], mode
))
2932 operands
[1] = force_reg (mode
, operands
[1]);
2934 /* Allow legitimize_address to perform some simplifications. */
2935 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2939 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2940 compiled at the end of compilation. In the meantime, someone can
2941 re-encode-section-info on some symbol changing it e.g. from global
2942 to local-not-small. If this happens, we'd have emitted a plain
2943 load rather than a high+losum load and not recognize the insn.
2945 So if rtl inlining is in effect, we delay the global/not-global
2946 decision until rest_of_compilation by wrapping it in an
2948 if (TARGET_EXPLICIT_RELOCS
&& flag_inline_functions
2949 && rtx_equal_function_value_matters
2950 && global_symbolic_operand (operands
[1], mode
))
2952 emit_insn (gen_movdi_er_maybe_g (operands
[0], operands
[1]));
2956 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
2959 if (tmp
== operands
[0])
2966 /* Early out for non-constants and valid constants. */
2967 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2970 /* Split large integers. */
2971 if (GET_CODE (operands
[1]) == CONST_INT
2972 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
2974 HOST_WIDE_INT i0
, i1
;
2975 rtx temp
= NULL_RTX
;
2977 if (GET_CODE (operands
[1]) == CONST_INT
)
2979 i0
= INTVAL (operands
[1]);
2982 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2984 i0
= CONST_DOUBLE_LOW (operands
[1]);
2989 i0
= CONST_DOUBLE_LOW (operands
[1]);
2990 i1
= CONST_DOUBLE_HIGH (operands
[1]);
2993 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2994 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
2996 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2997 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
3001 if (rtx_equal_p (operands
[0], temp
))
3008 /* Otherwise we've nothing left but to drop the thing to memory. */
3009 operands
[1] = force_const_mem (DImode
, operands
[1]);
3010 if (reload_in_progress
)
3012 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
3013 operands
[1] = copy_rtx (operands
[1]);
3014 XEXP (operands
[1], 0) = operands
[0];
3017 operands
[1] = validize_mem (operands
[1]);
3021 /* Expand a non-bwx QImode or HImode move instruction;
3022 return true if all work is done. */
3025 alpha_expand_mov_nobwx (mode
, operands
)
3026 enum machine_mode mode
;
3029 /* If the output is not a register, the input must be. */
3030 if (GET_CODE (operands
[0]) == MEM
)
3031 operands
[1] = force_reg (mode
, operands
[1]);
3033 /* Handle four memory cases, unaligned and aligned for either the input
3034 or the output. The only case where we can be called during reload is
3035 for aligned loads; all other cases require temporaries. */
3037 if (GET_CODE (operands
[1]) == MEM
3038 || (GET_CODE (operands
[1]) == SUBREG
3039 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
3040 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
3041 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
3042 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
3043 && GET_CODE (SUBREG_REG (operands
[1])) == REG
3044 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
3046 if (aligned_memory_operand (operands
[1], mode
))
3048 if (reload_in_progress
)
3050 emit_insn ((mode
== QImode
3051 ? gen_reload_inqi_help
3052 : gen_reload_inhi_help
)
3053 (operands
[0], operands
[1],
3054 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
3058 rtx aligned_mem
, bitnum
;
3059 rtx scratch
= gen_reg_rtx (SImode
);
3061 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
3063 emit_insn ((mode
== QImode
3064 ? gen_aligned_loadqi
3065 : gen_aligned_loadhi
)
3066 (operands
[0], aligned_mem
, bitnum
, scratch
));
3071 /* Don't pass these as parameters since that makes the generated
3072 code depend on parameter evaluation order which will cause
3073 bootstrap failures. */
3075 rtx temp1
= gen_reg_rtx (DImode
);
3076 rtx temp2
= gen_reg_rtx (DImode
);
3077 rtx seq
= ((mode
== QImode
3078 ? gen_unaligned_loadqi
3079 : gen_unaligned_loadhi
)
3080 (operands
[0], get_unaligned_address (operands
[1], 0),
3083 alpha_set_memflags (seq
, operands
[1]);
3089 if (GET_CODE (operands
[0]) == MEM
3090 || (GET_CODE (operands
[0]) == SUBREG
3091 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
3092 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
3093 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
3094 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
3095 && GET_CODE (SUBREG_REG (operands
[0])) == REG
3096 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
3098 if (aligned_memory_operand (operands
[0], mode
))
3100 rtx aligned_mem
, bitnum
;
3101 rtx temp1
= gen_reg_rtx (SImode
);
3102 rtx temp2
= gen_reg_rtx (SImode
);
3104 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
3106 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
3111 rtx temp1
= gen_reg_rtx (DImode
);
3112 rtx temp2
= gen_reg_rtx (DImode
);
3113 rtx temp3
= gen_reg_rtx (DImode
);
3114 rtx seq
= ((mode
== QImode
3115 ? gen_unaligned_storeqi
3116 : gen_unaligned_storehi
)
3117 (get_unaligned_address (operands
[0], 0),
3118 operands
[1], temp1
, temp2
, temp3
));
3120 alpha_set_memflags (seq
, operands
[0]);
3129 /* Generate an unsigned DImode to FP conversion. This is the same code
3130 optabs would emit if we didn't have TFmode patterns.
3132 For SFmode, this is the only construction I've found that can pass
3133 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
3134 intermediates will work, because you'll get intermediate rounding
3135 that ruins the end result. Some of this could be fixed by turning
3136 on round-to-positive-infinity, but that requires diddling the fpsr,
3137 which kills performance. I tried turning this around and converting
3138 to a negative number, so that I could turn on /m, but either I did
3139 it wrong or there's something else cause I wound up with the exact
3140 same single-bit error. There is a branch-less form of this same code:
3151 fcmoveq $f10,$f11,$f0
3153 I'm not using it because it's the same number of instructions as
3154 this branch-full form, and it has more serialized long latency
3155 instructions on the critical path.
3157 For DFmode, we can avoid rounding errors by breaking up the word
3158 into two pieces, converting them separately, and adding them back:
3160 LC0: .long 0,0x5f800000
3165 cpyse $f11,$f31,$f10
3166 cpyse $f31,$f11,$f11
3174 This doesn't seem to be a clear-cut win over the optabs form.
3175 It probably all depends on the distribution of numbers being
3176 converted -- in the optabs form, all but high-bit-set has a
3177 much lower minimum execution time. */
3180 alpha_emit_floatuns (operands
)
3183 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
3184 enum machine_mode mode
;
3187 in
= force_reg (DImode
, operands
[1]);
3188 mode
= GET_MODE (out
);
3189 neglab
= gen_label_rtx ();
3190 donelab
= gen_label_rtx ();
3191 i0
= gen_reg_rtx (DImode
);
3192 i1
= gen_reg_rtx (DImode
);
3193 f0
= gen_reg_rtx (mode
);
3195 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
3197 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
3198 emit_jump_insn (gen_jump (donelab
));
3201 emit_label (neglab
);
3203 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
3204 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
3205 emit_insn (gen_iordi3 (i0
, i0
, i1
));
3206 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
3207 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
3209 emit_label (donelab
);
3212 /* Generate the comparison for a conditional branch. */
3215 alpha_emit_conditional_branch (code
)
3218 enum rtx_code cmp_code
, branch_code
;
3219 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
3220 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3223 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
3225 if (! TARGET_HAS_XFLOATING_LIBS
)
3228 /* X_floating library comparison functions return
3232 Convert the compare against the raw return value. */
3254 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3256 alpha_compare
.fp_p
= 0;
3259 /* The general case: fold the comparison code to the types of compares
3260 that we have, choosing the branch as necessary. */
3263 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3265 /* We have these compares: */
3266 cmp_code
= code
, branch_code
= NE
;
3271 /* These must be reversed. */
3272 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
3275 case GE
: case GT
: case GEU
: case GTU
:
3276 /* For FP, we swap them, for INT, we reverse them. */
3277 if (alpha_compare
.fp_p
)
3279 cmp_code
= swap_condition (code
);
3281 tem
= op0
, op0
= op1
, op1
= tem
;
3285 cmp_code
= reverse_condition (code
);
3294 if (alpha_compare
.fp_p
)
3297 if (flag_unsafe_math_optimizations
)
3299 /* When we are not as concerned about non-finite values, and we
3300 are comparing against zero, we can branch directly. */
3301 if (op1
== CONST0_RTX (DFmode
))
3302 cmp_code
= NIL
, branch_code
= code
;
3303 else if (op0
== CONST0_RTX (DFmode
))
3305 /* Undo the swap we probably did just above. */
3306 tem
= op0
, op0
= op1
, op1
= tem
;
3307 branch_code
= swap_condition (cmp_code
);
3313 /* ??? We mark the branch mode to be CCmode to prevent the
3314 compare and branch from being combined, since the compare
3315 insn follows IEEE rules that the branch does not. */
3316 branch_mode
= CCmode
;
3323 /* The following optimizations are only for signed compares. */
3324 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
3326 /* Whee. Compare and branch against 0 directly. */
3327 if (op1
== const0_rtx
)
3328 cmp_code
= NIL
, branch_code
= code
;
3330 /* We want to use cmpcc/bcc when we can, since there is a zero delay
3331 bypass between logicals and br/cmov on EV5. But we don't want to
3332 force valid immediate constants into registers needlessly. */
3333 else if (GET_CODE (op1
) == CONST_INT
)
3335 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
3337 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
3338 && (CONST_OK_FOR_LETTER_P (n
, 'K')
3339 || CONST_OK_FOR_LETTER_P (n
, 'L')))
3341 cmp_code
= PLUS
, branch_code
= code
;
3347 if (!reg_or_0_operand (op0
, DImode
))
3348 op0
= force_reg (DImode
, op0
);
3349 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
3350 op1
= force_reg (DImode
, op1
);
3353 /* Emit an initial compare instruction, if necessary. */
3355 if (cmp_code
!= NIL
)
3357 tem
= gen_reg_rtx (cmp_mode
);
3358 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
3361 /* Zero the operands. */
3362 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3364 /* Return the branch comparison. */
3365 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
3368 /* Certain simplifications can be done to make invalid setcc operations
3369 valid. Return the final comparison, or NULL if we can't work. */
3372 alpha_emit_setcc (code
)
3375 enum rtx_code cmp_code
;
3376 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3377 int fp_p
= alpha_compare
.fp_p
;
3380 /* Zero the operands. */
3381 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3383 if (fp_p
&& GET_MODE (op0
) == TFmode
)
3385 if (! TARGET_HAS_XFLOATING_LIBS
)
3388 /* X_floating library comparison functions return
3392 Convert the compare against the raw return value. */
3394 if (code
== UNORDERED
|| code
== ORDERED
)
3399 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3403 if (code
== UNORDERED
)
3405 else if (code
== ORDERED
)
3411 if (fp_p
&& !TARGET_FIX
)
3414 /* The general case: fold the comparison code to the types of compares
3415 that we have, choosing the branch as necessary. */
3420 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3422 /* We have these compares. */
3424 cmp_code
= code
, code
= NE
;
3428 if (!fp_p
&& op1
== const0_rtx
)
3433 cmp_code
= reverse_condition (code
);
3437 case GE
: case GT
: case GEU
: case GTU
:
3438 /* These normally need swapping, but for integer zero we have
3439 special patterns that recognize swapped operands. */
3440 if (!fp_p
&& op1
== const0_rtx
)
3442 code
= swap_condition (code
);
3444 cmp_code
= code
, code
= NE
;
3445 tmp
= op0
, op0
= op1
, op1
= tmp
;
3454 if (!register_operand (op0
, DImode
))
3455 op0
= force_reg (DImode
, op0
);
3456 if (!reg_or_8bit_operand (op1
, DImode
))
3457 op1
= force_reg (DImode
, op1
);
3460 /* Emit an initial compare instruction, if necessary. */
3461 if (cmp_code
!= NIL
)
3463 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
3465 tmp
= gen_reg_rtx (mode
);
3466 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
3467 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
3469 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
3473 /* Return the setcc comparison. */
3474 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
3478 /* Rewrite a comparison against zero CMP of the form
3479 (CODE (cc0) (const_int 0)) so it can be written validly in
3480 a conditional move (if_then_else CMP ...).
3481 If both of the operands that set cc0 are non-zero we must emit
3482 an insn to perform the compare (it can't be done within
3483 the conditional move). */
3485 alpha_emit_conditional_move (cmp
, mode
)
3487 enum machine_mode mode
;
3489 enum rtx_code code
= GET_CODE (cmp
);
3490 enum rtx_code cmov_code
= NE
;
3491 rtx op0
= alpha_compare
.op0
;
3492 rtx op1
= alpha_compare
.op1
;
3493 int fp_p
= alpha_compare
.fp_p
;
3494 enum machine_mode cmp_mode
3495 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
3496 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
3497 enum machine_mode cmov_mode
= VOIDmode
;
3498 int local_fast_math
= flag_unsafe_math_optimizations
;
3501 /* Zero the operands. */
3502 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3504 if (fp_p
!= FLOAT_MODE_P (mode
))
3506 enum rtx_code cmp_code
;
3511 /* If we have fp<->int register move instructions, do a cmov by
3512 performing the comparison in fp registers, and move the
3513 zero/non-zero value to integer registers, where we can then
3514 use a normal cmov, or vice-versa. */
3518 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3519 /* We have these compares. */
3520 cmp_code
= code
, code
= NE
;
3524 /* This must be reversed. */
3525 cmp_code
= EQ
, code
= EQ
;
3528 case GE
: case GT
: case GEU
: case GTU
:
3529 /* These normally need swapping, but for integer zero we have
3530 special patterns that recognize swapped operands. */
3531 if (!fp_p
&& op1
== const0_rtx
)
3532 cmp_code
= code
, code
= NE
;
3535 cmp_code
= swap_condition (code
);
3537 tem
= op0
, op0
= op1
, op1
= tem
;
3545 tem
= gen_reg_rtx (cmp_op_mode
);
3546 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
3547 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
3550 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
3551 op0
= gen_lowpart (cmp_op_mode
, tem
);
3552 op1
= CONST0_RTX (cmp_op_mode
);
3554 local_fast_math
= 1;
3557 /* We may be able to use a conditional move directly.
3558 This avoids emitting spurious compares. */
3559 if (signed_comparison_operator (cmp
, VOIDmode
)
3560 && (!fp_p
|| local_fast_math
)
3561 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
3562 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3564 /* We can't put the comparison inside the conditional move;
3565 emit a compare instruction and put that inside the
3566 conditional move. Make sure we emit only comparisons we have;
3567 swap or reverse as necessary. */
3574 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3575 /* We have these compares: */
3579 /* This must be reversed. */
3580 code
= reverse_condition (code
);
3584 case GE
: case GT
: case GEU
: case GTU
:
3585 /* These must be swapped. */
3586 if (op1
!= CONST0_RTX (cmp_mode
))
3588 code
= swap_condition (code
);
3589 tem
= op0
, op0
= op1
, op1
= tem
;
3599 if (!reg_or_0_operand (op0
, DImode
))
3600 op0
= force_reg (DImode
, op0
);
3601 if (!reg_or_8bit_operand (op1
, DImode
))
3602 op1
= force_reg (DImode
, op1
);
3605 /* ??? We mark the branch mode to be CCmode to prevent the compare
3606 and cmov from being combined, since the compare insn follows IEEE
3607 rules that the cmov does not. */
3608 if (fp_p
&& !local_fast_math
)
3611 tem
= gen_reg_rtx (cmp_op_mode
);
3612 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
3613 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
3616 /* Simplify a conditional move of two constants into a setcc with
3617 arithmetic. This is done with a splitter since combine would
3618 just undo the work if done during code generation. It also catches
3619 cases we wouldn't have before cse. */
3622 alpha_split_conditional_move (code
, dest
, cond
, t_rtx
, f_rtx
)
3624 rtx dest
, cond
, t_rtx
, f_rtx
;
3626 HOST_WIDE_INT t
, f
, diff
;
3627 enum machine_mode mode
;
3628 rtx target
, subtarget
, tmp
;
3630 mode
= GET_MODE (dest
);
3635 if (((code
== NE
|| code
== EQ
) && diff
< 0)
3636 || (code
== GE
|| code
== GT
))
3638 code
= reverse_condition (code
);
3639 diff
= t
, t
= f
, f
= diff
;
3643 subtarget
= target
= dest
;
3646 target
= gen_lowpart (DImode
, dest
);
3647 if (! no_new_pseudos
)
3648 subtarget
= gen_reg_rtx (DImode
);
3652 /* Below, we must be careful to use copy_rtx on target and subtarget
3653 in intermediate insns, as they may be a subreg rtx, which may not
3656 if (f
== 0 && exact_log2 (diff
) > 0
3657 /* On EV6, we've got enough shifters to make non-arithmatic shifts
3658 viable over a longer latency cmove. On EV5, the E0 slot is a
3659 scarce resource, and on EV4 shift has the same latency as a cmove. */
3660 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
3662 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3663 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3665 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
3666 GEN_INT (exact_log2 (t
)));
3667 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3669 else if (f
== 0 && t
== -1)
3671 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3672 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3674 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
3676 else if (diff
== 1 || diff
== 4 || diff
== 8)
3680 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3681 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3684 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
3687 add_op
= GEN_INT (f
);
3688 if (sext_add_operand (add_op
, mode
))
3690 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
3692 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
3693 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3705 /* Look up the function X_floating library function name for the
3709 alpha_lookup_xfloating_lib_func (code
)
3714 const enum rtx_code code
;
3715 const char *const func
;
3718 static const struct xfloating_op vms_xfloating_ops
[] =
3720 { PLUS
, "OTS$ADD_X" },
3721 { MINUS
, "OTS$SUB_X" },
3722 { MULT
, "OTS$MUL_X" },
3723 { DIV
, "OTS$DIV_X" },
3724 { EQ
, "OTS$EQL_X" },
3725 { NE
, "OTS$NEQ_X" },
3726 { LT
, "OTS$LSS_X" },
3727 { LE
, "OTS$LEQ_X" },
3728 { GT
, "OTS$GTR_X" },
3729 { GE
, "OTS$GEQ_X" },
3730 { FIX
, "OTS$CVTXQ" },
3731 { FLOAT
, "OTS$CVTQX" },
3732 { UNSIGNED_FLOAT
, "OTS$CVTQUX" },
3733 { FLOAT_EXTEND
, "OTS$CVT_FLOAT_T_X" },
3734 { FLOAT_TRUNCATE
, "OTS$CVT_FLOAT_X_T" },
3737 static const struct xfloating_op osf_xfloating_ops
[] =
3739 { PLUS
, "_OtsAddX" },
3740 { MINUS
, "_OtsSubX" },
3741 { MULT
, "_OtsMulX" },
3742 { DIV
, "_OtsDivX" },
3749 { FIX
, "_OtsCvtXQ" },
3750 { FLOAT
, "_OtsCvtQX" },
3751 { UNSIGNED_FLOAT
, "_OtsCvtQUX" },
3752 { FLOAT_EXTEND
, "_OtsConvertFloatTX" },
3753 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT" },
3756 const struct xfloating_op
*ops
;
3757 const long n
= ARRAY_SIZE (osf_xfloating_ops
);
3760 /* How irritating. Nothing to key off for the table. Hardcode
3761 knowledge of the G_floating routines. */
3762 if (TARGET_FLOAT_VAX
)
3764 if (TARGET_ABI_OPEN_VMS
)
3766 if (code
== FLOAT_EXTEND
)
3767 return "OTS$CVT_FLOAT_G_X";
3768 if (code
== FLOAT_TRUNCATE
)
3769 return "OTS$CVT_FLOAT_X_G";
3773 if (code
== FLOAT_EXTEND
)
3774 return "_OtsConvertFloatGX";
3775 if (code
== FLOAT_TRUNCATE
)
3776 return "_OtsConvertFloatXG";
3780 if (TARGET_ABI_OPEN_VMS
)
3781 ops
= vms_xfloating_ops
;
3783 ops
= osf_xfloating_ops
;
3785 for (i
= 0; i
< n
; ++i
)
3786 if (ops
[i
].code
== code
)
3792 /* Most X_floating operations take the rounding mode as an argument.
3793 Compute that here. */
3796 alpha_compute_xfloating_mode_arg (code
, round
)
3798 enum alpha_fp_rounding_mode round
;
3804 case ALPHA_FPRM_NORM
:
3807 case ALPHA_FPRM_MINF
:
3810 case ALPHA_FPRM_CHOP
:
3813 case ALPHA_FPRM_DYN
:
3819 /* XXX For reference, round to +inf is mode = 3. */
3822 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3828 /* Emit an X_floating library function call.
3830 Note that these functions do not follow normal calling conventions:
3831 TFmode arguments are passed in two integer registers (as opposed to
3832 indirect); TFmode return values appear in R16+R17.
3834 FUNC is the function name to call.
3835 TARGET is where the output belongs.
3836 OPERANDS are the inputs.
3837 NOPERANDS is the count of inputs.
3838 EQUIV is the expression equivalent for the function.
3842 alpha_emit_xfloating_libcall (func
, target
, operands
, noperands
, equiv
)
3849 rtx usage
= NULL_RTX
, tmp
, reg
;
3854 for (i
= 0; i
< noperands
; ++i
)
3856 switch (GET_MODE (operands
[i
]))
3859 reg
= gen_rtx_REG (TFmode
, regno
);
3864 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3869 if (GET_CODE (operands
[i
]) != CONST_INT
)
3873 reg
= gen_rtx_REG (DImode
, regno
);
3881 emit_move_insn (reg
, operands
[i
]);
3882 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3885 switch (GET_MODE (target
))
3888 reg
= gen_rtx_REG (TFmode
, 16);
3891 reg
= gen_rtx_REG (DFmode
, 32);
3894 reg
= gen_rtx_REG (DImode
, 0);
3900 tmp
= gen_rtx_MEM (QImode
, gen_rtx_SYMBOL_REF (Pmode
, (char *) func
));
3901 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3902 const0_rtx
, const0_rtx
));
3903 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3908 emit_libcall_block (tmp
, target
, reg
, equiv
);
3911 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3914 alpha_emit_xfloating_arith (code
, operands
)
3920 rtx out_operands
[3];
3922 func
= alpha_lookup_xfloating_lib_func (code
);
3923 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3925 out_operands
[0] = operands
[1];
3926 out_operands
[1] = operands
[2];
3927 out_operands
[2] = GEN_INT (mode
);
3928 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
3929 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
3933 /* Emit an X_floating library function call for a comparison. */
3936 alpha_emit_xfloating_compare (code
, op0
, op1
)
3941 rtx out
, operands
[2];
3943 func
= alpha_lookup_xfloating_lib_func (code
);
3947 out
= gen_reg_rtx (DImode
);
3949 /* ??? Strange mode for equiv because what's actually returned
3950 is -1,0,1, not a proper boolean value. */
3951 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
3952 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
3957 /* Emit an X_floating library function call for a conversion. */
3960 alpha_emit_xfloating_cvt (code
, operands
)
3964 int noperands
= 1, mode
;
3965 rtx out_operands
[2];
3968 func
= alpha_lookup_xfloating_lib_func (code
);
3970 out_operands
[0] = operands
[1];
3975 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3976 out_operands
[1] = GEN_INT (mode
);
3979 case FLOAT_TRUNCATE
:
3980 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3981 out_operands
[1] = GEN_INT (mode
);
3988 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3989 gen_rtx_fmt_e (code
, GET_MODE (operands
[0]),
3993 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3994 OP[0] into OP[0,1]. Naturally, output operand ordering is
3998 alpha_split_tfmode_pair (operands
)
4001 if (GET_CODE (operands
[1]) == REG
)
4003 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
4004 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
4006 else if (GET_CODE (operands
[1]) == MEM
)
4008 operands
[3] = adjust_address (operands
[1], DImode
, 8);
4009 operands
[2] = adjust_address (operands
[1], DImode
, 0);
4011 else if (operands
[1] == CONST0_RTX (TFmode
))
4012 operands
[2] = operands
[3] = const0_rtx
;
4016 if (GET_CODE (operands
[0]) == REG
)
4018 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
4019 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
4021 else if (GET_CODE (operands
[0]) == MEM
)
4023 operands
[1] = adjust_address (operands
[0], DImode
, 8);
4024 operands
[0] = adjust_address (operands
[0], DImode
, 0);
4030 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
4031 op2 is a register containing the sign bit, operation is the
4032 logical operation to be performed. */
4035 alpha_split_tfmode_frobsign (operands
, operation
)
4037 rtx (*operation
) PARAMS ((rtx
, rtx
, rtx
));
4039 rtx high_bit
= operands
[2];
4043 alpha_split_tfmode_pair (operands
);
4045 /* Detect three flavours of operand overlap. */
4047 if (rtx_equal_p (operands
[0], operands
[2]))
4049 else if (rtx_equal_p (operands
[1], operands
[2]))
4051 if (rtx_equal_p (operands
[0], high_bit
))
4058 emit_move_insn (operands
[0], operands
[2]);
4060 /* ??? If the destination overlaps both source tf and high_bit, then
4061 assume source tf is dead in its entirety and use the other half
4062 for a scratch register. Otherwise "scratch" is just the proper
4063 destination register. */
4064 scratch
= operands
[move
< 2 ? 1 : 3];
4066 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
4070 emit_move_insn (operands
[0], operands
[2]);
4072 emit_move_insn (operands
[1], scratch
);
4076 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
4080 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
4081 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
4082 lda r3,X(r11) lda r3,X+2(r11)
4083 extwl r1,r3,r1 extql r1,r3,r1
4084 extwh r2,r3,r2 extqh r2,r3,r2
4085 or r1.r2.r1 or r1,r2,r1
4088 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
4089 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
4090 lda r3,X(r11) lda r3,X(r11)
4091 extll r1,r3,r1 extll r1,r3,r1
4092 extlh r2,r3,r2 extlh r2,r3,r2
4093 or r1.r2.r1 addl r1,r2,r1
4095 quad: ldq_u r1,X(r11)
4104 alpha_expand_unaligned_load (tgt
, mem
, size
, ofs
, sign
)
4106 HOST_WIDE_INT size
, ofs
;
4109 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
4110 enum machine_mode mode
;
4112 meml
= gen_reg_rtx (DImode
);
4113 memh
= gen_reg_rtx (DImode
);
4114 addr
= gen_reg_rtx (DImode
);
4115 extl
= gen_reg_rtx (DImode
);
4116 exth
= gen_reg_rtx (DImode
);
4118 mema
= XEXP (mem
, 0);
4119 if (GET_CODE (mema
) == LO_SUM
)
4120 mema
= force_reg (Pmode
, mema
);
4122 /* AND addresses cannot be in any alias set, since they may implicitly
4123 alias surrounding code. Ideally we'd have some alias set that
4124 covered all types except those with alignment 8 or higher. */
4126 tmp
= change_address (mem
, DImode
,
4127 gen_rtx_AND (DImode
,
4128 plus_constant (mema
, ofs
),
4130 set_mem_alias_set (tmp
, 0);
4131 emit_move_insn (meml
, tmp
);
4133 tmp
= change_address (mem
, DImode
,
4134 gen_rtx_AND (DImode
,
4135 plus_constant (mema
, ofs
+ size
- 1),
4137 set_mem_alias_set (tmp
, 0);
4138 emit_move_insn (memh
, tmp
);
4140 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
4142 emit_move_insn (addr
, plus_constant (mema
, -1));
4144 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4145 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
4147 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4148 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
4149 addr
, 1, OPTAB_WIDEN
);
4151 else if (sign
&& size
== 2)
4153 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
4155 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
4156 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4158 /* We must use tgt here for the target. Alpha-vms port fails if we use
4159 addr for the target, because addr is marked as a pointer and combine
4160 knows that pointers are always sign-extended 32 bit values. */
4161 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4162 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
4163 addr
, 1, OPTAB_WIDEN
);
4167 if (WORDS_BIG_ENDIAN
)
4169 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
4173 emit_insn (gen_extwh_be (extl
, meml
, addr
));
4178 emit_insn (gen_extlh_be (extl
, meml
, addr
));
4183 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4190 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
4194 emit_move_insn (addr
, plus_constant (mema
, ofs
));
4195 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
4199 emit_insn (gen_extwh_le (exth
, memh
, addr
));
4204 emit_insn (gen_extlh_le (exth
, memh
, addr
));
4209 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4218 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
4219 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
4224 emit_move_insn (tgt
, gen_lowpart(GET_MODE (tgt
), addr
));
4227 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4230 alpha_expand_unaligned_store (dst
, src
, size
, ofs
)
4232 HOST_WIDE_INT size
, ofs
;
4234 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
4236 dstl
= gen_reg_rtx (DImode
);
4237 dsth
= gen_reg_rtx (DImode
);
4238 insl
= gen_reg_rtx (DImode
);
4239 insh
= gen_reg_rtx (DImode
);
4241 dsta
= XEXP (dst
, 0);
4242 if (GET_CODE (dsta
) == LO_SUM
)
4243 dsta
= force_reg (Pmode
, dsta
);
4245 /* AND addresses cannot be in any alias set, since they may implicitly
4246 alias surrounding code. Ideally we'd have some alias set that
4247 covered all types except those with alignment 8 or higher. */
4249 meml
= change_address (dst
, DImode
,
4250 gen_rtx_AND (DImode
,
4251 plus_constant (dsta
, ofs
),
4253 set_mem_alias_set (meml
, 0);
4255 memh
= change_address (dst
, DImode
,
4256 gen_rtx_AND (DImode
,
4257 plus_constant (dsta
, ofs
+ size
- 1),
4259 set_mem_alias_set (memh
, 0);
4261 emit_move_insn (dsth
, memh
);
4262 emit_move_insn (dstl
, meml
);
4263 if (WORDS_BIG_ENDIAN
)
4265 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
4267 if (src
!= const0_rtx
)
4272 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
4275 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
4278 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
4281 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
4282 GEN_INT (size
*8), addr
));
4288 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
4292 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4293 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
4297 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
4301 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
4305 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
4307 if (src
!= const0_rtx
)
4309 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
4310 GEN_INT (size
*8), addr
));
4315 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
4318 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
4321 emit_insn (gen_insql_le (insl
, src
, addr
));
4326 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
4331 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
4335 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4336 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
4340 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
4345 if (src
!= const0_rtx
)
4347 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
4348 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
4351 if (WORDS_BIG_ENDIAN
)
4353 emit_move_insn (meml
, dstl
);
4354 emit_move_insn (memh
, dsth
);
4358 /* Must store high before low for degenerate case of aligned. */
4359 emit_move_insn (memh
, dsth
);
4360 emit_move_insn (meml
, dstl
);
4364 /* The block move code tries to maximize speed by separating loads and
4365 stores at the expense of register pressure: we load all of the data
4366 before we store it back out. There are two secondary effects worth
4367 mentioning, that this speeds copying to/from aligned and unaligned
4368 buffers, and that it makes the code significantly easier to write. */
4370 #define MAX_MOVE_WORDS 8
4372 /* Load an integral number of consecutive unaligned quadwords. */
4375 alpha_expand_unaligned_load_words (out_regs
, smem
, words
, ofs
)
4378 HOST_WIDE_INT words
, ofs
;
4380 rtx
const im8
= GEN_INT (-8);
4381 rtx
const i64
= GEN_INT (64);
4382 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
4383 rtx sreg
, areg
, tmp
, smema
;
4386 smema
= XEXP (smem
, 0);
4387 if (GET_CODE (smema
) == LO_SUM
)
4388 smema
= force_reg (Pmode
, smema
);
4390 /* Generate all the tmp registers we need. */
4391 for (i
= 0; i
< words
; ++i
)
4393 data_regs
[i
] = out_regs
[i
];
4394 ext_tmps
[i
] = gen_reg_rtx (DImode
);
4396 data_regs
[words
] = gen_reg_rtx (DImode
);
4399 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
4401 /* Load up all of the source data. */
4402 for (i
= 0; i
< words
; ++i
)
4404 tmp
= change_address (smem
, DImode
,
4405 gen_rtx_AND (DImode
,
4406 plus_constant (smema
, 8*i
),
4408 set_mem_alias_set (tmp
, 0);
4409 emit_move_insn (data_regs
[i
], tmp
);
4412 tmp
= change_address (smem
, DImode
,
4413 gen_rtx_AND (DImode
,
4414 plus_constant (smema
, 8*words
- 1),
4416 set_mem_alias_set (tmp
, 0);
4417 emit_move_insn (data_regs
[words
], tmp
);
4419 /* Extract the half-word fragments. Unfortunately DEC decided to make
4420 extxh with offset zero a noop instead of zeroing the register, so
4421 we must take care of that edge condition ourselves with cmov. */
4423 sreg
= copy_addr_to_reg (smema
);
4424 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
4426 if (WORDS_BIG_ENDIAN
)
4427 emit_move_insn (sreg
, plus_constant (sreg
, 7));
4428 for (i
= 0; i
< words
; ++i
)
4430 if (WORDS_BIG_ENDIAN
)
4432 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
4433 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
4437 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
4438 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
4440 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
4441 gen_rtx_IF_THEN_ELSE (DImode
,
4442 gen_rtx_EQ (DImode
, areg
,
4444 const0_rtx
, ext_tmps
[i
])));
4447 /* Merge the half-words into whole words. */
4448 for (i
= 0; i
< words
; ++i
)
4450 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4451 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
4455 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4456 may be NULL to store zeros. */
4459 alpha_expand_unaligned_store_words (data_regs
, dmem
, words
, ofs
)
4462 HOST_WIDE_INT words
, ofs
;
4464 rtx
const im8
= GEN_INT (-8);
4465 rtx
const i64
= GEN_INT (64);
4466 rtx ins_tmps
[MAX_MOVE_WORDS
];
4467 rtx st_tmp_1
, st_tmp_2
, dreg
;
4468 rtx st_addr_1
, st_addr_2
, dmema
;
4471 dmema
= XEXP (dmem
, 0);
4472 if (GET_CODE (dmema
) == LO_SUM
)
4473 dmema
= force_reg (Pmode
, dmema
);
4475 /* Generate all the tmp registers we need. */
4476 if (data_regs
!= NULL
)
4477 for (i
= 0; i
< words
; ++i
)
4478 ins_tmps
[i
] = gen_reg_rtx(DImode
);
4479 st_tmp_1
= gen_reg_rtx(DImode
);
4480 st_tmp_2
= gen_reg_rtx(DImode
);
4483 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
4485 st_addr_2
= change_address (dmem
, DImode
,
4486 gen_rtx_AND (DImode
,
4487 plus_constant (dmema
, words
*8 - 1),
4489 set_mem_alias_set (st_addr_2
, 0);
4491 st_addr_1
= change_address (dmem
, DImode
,
4492 gen_rtx_AND (DImode
, dmema
, im8
));
4493 set_mem_alias_set (st_addr_1
, 0);
4495 /* Load up the destination end bits. */
4496 emit_move_insn (st_tmp_2
, st_addr_2
);
4497 emit_move_insn (st_tmp_1
, st_addr_1
);
4499 /* Shift the input data into place. */
4500 dreg
= copy_addr_to_reg (dmema
);
4501 if (WORDS_BIG_ENDIAN
)
4502 emit_move_insn (dreg
, plus_constant (dreg
, 7));
4503 if (data_regs
!= NULL
)
4505 for (i
= words
-1; i
>= 0; --i
)
4507 if (WORDS_BIG_ENDIAN
)
4509 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
4510 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
4514 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
4515 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
4518 for (i
= words
-1; i
> 0; --i
)
4520 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4521 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
4526 /* Split and merge the ends with the destination data. */
4527 if (WORDS_BIG_ENDIAN
)
4529 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
4530 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
4534 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
4535 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
4538 if (data_regs
!= NULL
)
4540 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
4541 st_tmp_2
, 1, OPTAB_WIDEN
);
4542 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
4543 st_tmp_1
, 1, OPTAB_WIDEN
);
4547 if (WORDS_BIG_ENDIAN
)
4548 emit_move_insn (st_addr_1
, st_tmp_1
);
4550 emit_move_insn (st_addr_2
, st_tmp_2
);
4551 for (i
= words
-1; i
> 0; --i
)
4553 rtx tmp
= change_address (dmem
, DImode
,
4554 gen_rtx_AND (DImode
,
4555 plus_constant(dmema
,
4556 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
4558 set_mem_alias_set (tmp
, 0);
4559 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
4561 if (WORDS_BIG_ENDIAN
)
4562 emit_move_insn (st_addr_2
, st_tmp_2
);
4564 emit_move_insn (st_addr_1
, st_tmp_1
);
4568 /* Expand string/block move operations.
4570 operands[0] is the pointer to the destination.
4571 operands[1] is the pointer to the source.
4572 operands[2] is the number of bytes to move.
4573 operands[3] is the alignment. */
4576 alpha_expand_block_move (operands
)
4579 rtx bytes_rtx
= operands
[2];
4580 rtx align_rtx
= operands
[3];
4581 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4582 HOST_WIDE_INT bytes
= orig_bytes
;
4583 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4584 HOST_WIDE_INT dst_align
= src_align
;
4585 rtx orig_src
= operands
[1];
4586 rtx orig_dst
= operands
[0];
4587 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
4589 unsigned int i
, words
, ofs
, nregs
= 0;
4591 if (orig_bytes
<= 0)
4593 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4596 /* Look for additional alignment information from recorded register info. */
4598 tmp
= XEXP (orig_src
, 0);
4599 if (GET_CODE (tmp
) == REG
)
4600 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4601 else if (GET_CODE (tmp
) == PLUS
4602 && GET_CODE (XEXP (tmp
, 0)) == REG
4603 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4605 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4606 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4610 if (a
>= 64 && c
% 8 == 0)
4612 else if (a
>= 32 && c
% 4 == 0)
4614 else if (a
>= 16 && c
% 2 == 0)
4619 tmp
= XEXP (orig_dst
, 0);
4620 if (GET_CODE (tmp
) == REG
)
4621 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4622 else if (GET_CODE (tmp
) == PLUS
4623 && GET_CODE (XEXP (tmp
, 0)) == REG
4624 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4626 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4627 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4631 if (a
>= 64 && c
% 8 == 0)
4633 else if (a
>= 32 && c
% 4 == 0)
4635 else if (a
>= 16 && c
% 2 == 0)
4640 /* Load the entire block into registers. */
4641 if (GET_CODE (XEXP (orig_src
, 0)) == ADDRESSOF
)
4643 enum machine_mode mode
;
4645 tmp
= XEXP (XEXP (orig_src
, 0), 0);
4647 /* Don't use the existing register if we're reading more than
4648 is held in the register. Nor if there is not a mode that
4649 handles the exact size. */
4650 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4652 && GET_MODE_SIZE (GET_MODE (tmp
)) >= bytes
)
4656 data_regs
[nregs
] = gen_lowpart (DImode
, tmp
);
4657 data_regs
[nregs
+ 1] = gen_highpart (DImode
, tmp
);
4661 data_regs
[nregs
++] = gen_lowpart (mode
, tmp
);
4666 /* No appropriate mode; fall back on memory. */
4667 orig_src
= replace_equiv_address (orig_src
,
4668 copy_addr_to_reg (XEXP (orig_src
, 0)));
4669 src_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4673 if (src_align
>= 64 && bytes
>= 8)
4677 for (i
= 0; i
< words
; ++i
)
4678 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4680 for (i
= 0; i
< words
; ++i
)
4681 emit_move_insn (data_regs
[nregs
+ i
],
4682 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
4689 if (src_align
>= 32 && bytes
>= 4)
4693 for (i
= 0; i
< words
; ++i
)
4694 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
4696 for (i
= 0; i
< words
; ++i
)
4697 emit_move_insn (data_regs
[nregs
+ i
],
4698 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
4709 for (i
= 0; i
< words
+1; ++i
)
4710 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4712 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
4720 if (! TARGET_BWX
&& bytes
>= 4)
4722 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
4723 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
4730 if (src_align
>= 16)
4733 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4734 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
4737 } while (bytes
>= 2);
4739 else if (! TARGET_BWX
)
4741 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4742 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
4750 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
4751 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
4758 if (nregs
> ARRAY_SIZE (data_regs
))
4761 /* Now save it back out again. */
4765 if (GET_CODE (XEXP (orig_dst
, 0)) == ADDRESSOF
)
4767 enum machine_mode mode
;
4768 tmp
= XEXP (XEXP (orig_dst
, 0), 0);
4770 mode
= mode_for_size (orig_bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4771 if (GET_MODE (tmp
) == mode
)
4775 emit_move_insn (tmp
, data_regs
[0]);
4780 else if (nregs
== 2 && mode
== TImode
)
4782 /* Undo the subregging done above when copying between
4783 two TImode registers. */
4784 if (GET_CODE (data_regs
[0]) == SUBREG
4785 && GET_MODE (SUBREG_REG (data_regs
[0])) == TImode
)
4786 emit_move_insn (tmp
, SUBREG_REG (data_regs
[0]));
4792 emit_move_insn (gen_lowpart (DImode
, tmp
), data_regs
[0]);
4793 emit_move_insn (gen_highpart (DImode
, tmp
), data_regs
[1]);
4797 emit_no_conflict_block (seq
, tmp
, data_regs
[0],
4798 data_regs
[1], NULL_RTX
);
4806 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4807 /* ??? Optimize mode < dst_mode with strict_low_part. */
4809 /* No appropriate mode; fall back on memory. We can speed things
4810 up by recognizing extra alignment information. */
4811 orig_dst
= replace_equiv_address (orig_dst
,
4812 copy_addr_to_reg (XEXP (orig_dst
, 0)));
4813 dst_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4816 /* Write out the data in whatever chunks reading the source allowed. */
4817 if (dst_align
>= 64)
4819 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4821 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
4828 if (dst_align
>= 32)
4830 /* If the source has remaining DImode regs, write them out in
4832 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4834 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
4835 NULL_RTX
, 1, OPTAB_WIDEN
);
4837 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4838 gen_lowpart (SImode
, data_regs
[i
]));
4839 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
4840 gen_lowpart (SImode
, tmp
));
4845 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4847 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4854 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4856 /* Write out a remaining block of words using unaligned methods. */
4858 for (words
= 1; i
+ words
< nregs
; words
++)
4859 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4863 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4865 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4872 /* Due to the above, this won't be aligned. */
4873 /* ??? If we have more than one of these, consider constructing full
4874 words in registers and using alpha_expand_unaligned_store_words. */
4875 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4877 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4882 if (dst_align
>= 16)
4883 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4885 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4890 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4892 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4897 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
4899 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4913 alpha_expand_block_clear (operands
)
4916 rtx bytes_rtx
= operands
[1];
4917 rtx align_rtx
= operands
[2];
4918 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4919 HOST_WIDE_INT bytes
= orig_bytes
;
4920 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4921 HOST_WIDE_INT alignofs
= 0;
4922 rtx orig_dst
= operands
[0];
4924 int i
, words
, ofs
= 0;
4926 if (orig_bytes
<= 0)
4928 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4931 /* Look for stricter alignment. */
4932 tmp
= XEXP (orig_dst
, 0);
4933 if (GET_CODE (tmp
) == REG
)
4934 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4935 else if (GET_CODE (tmp
) == PLUS
4936 && GET_CODE (XEXP (tmp
, 0)) == REG
4937 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4939 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4940 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4945 align
= a
, alignofs
= 8 - c
% 8;
4947 align
= a
, alignofs
= 4 - c
% 4;
4949 align
= a
, alignofs
= 2 - c
% 2;
4952 else if (GET_CODE (tmp
) == ADDRESSOF
)
4954 enum machine_mode mode
;
4956 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4957 if (GET_MODE (XEXP (tmp
, 0)) == mode
)
4959 emit_move_insn (XEXP (tmp
, 0), const0_rtx
);
4963 /* No appropriate mode; fall back on memory. */
4964 orig_dst
= replace_equiv_address (orig_dst
, copy_addr_to_reg (tmp
));
4965 align
= GET_MODE_BITSIZE (GET_MODE (XEXP (tmp
, 0)));
4968 /* Handle an unaligned prefix first. */
4972 #if HOST_BITS_PER_WIDE_INT >= 64
4973 /* Given that alignofs is bounded by align, the only time BWX could
4974 generate three stores is for a 7 byte fill. Prefer two individual
4975 stores over a load/mask/store sequence. */
4976 if ((!TARGET_BWX
|| alignofs
== 7)
4978 && !(alignofs
== 4 && bytes
>= 4))
4980 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
4981 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
4985 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
4986 set_mem_alias_set (mem
, 0);
4988 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
4989 if (bytes
< alignofs
)
4991 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
5002 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
5003 NULL_RTX
, 1, OPTAB_WIDEN
);
5005 emit_move_insn (mem
, tmp
);
5009 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
5011 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5016 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
5018 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
5023 if (alignofs
== 4 && bytes
>= 4)
5025 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
5031 /* If we've not used the extra lead alignment information by now,
5032 we won't be able to. Downgrade align to match what's left over. */
5035 alignofs
= alignofs
& -alignofs
;
5036 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
5040 /* Handle a block of contiguous long-words. */
5042 if (align
>= 64 && bytes
>= 8)
5046 for (i
= 0; i
< words
; ++i
)
5047 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
5054 /* If the block is large and appropriately aligned, emit a single
5055 store followed by a sequence of stq_u insns. */
5057 if (align
>= 32 && bytes
> 16)
5061 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
5065 orig_dsta
= XEXP (orig_dst
, 0);
5066 if (GET_CODE (orig_dsta
) == LO_SUM
)
5067 orig_dsta
= force_reg (Pmode
, orig_dsta
);
5070 for (i
= 0; i
< words
; ++i
)
5073 = change_address (orig_dst
, DImode
,
5074 gen_rtx_AND (DImode
,
5075 plus_constant (orig_dsta
, ofs
+ i
*8),
5077 set_mem_alias_set (mem
, 0);
5078 emit_move_insn (mem
, const0_rtx
);
5081 /* Depending on the alignment, the first stq_u may have overlapped
5082 with the initial stl, which means that the last stq_u didn't
5083 write as much as it would appear. Leave those questionable bytes
5085 bytes
-= words
* 8 - 4;
5086 ofs
+= words
* 8 - 4;
5089 /* Handle a smaller block of aligned words. */
5091 if ((align
>= 64 && bytes
== 4)
5092 || (align
== 32 && bytes
>= 4))
5096 for (i
= 0; i
< words
; ++i
)
5097 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
5104 /* An unaligned block uses stq_u stores for as many as possible. */
5110 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
5116 /* Next clean up any trailing pieces. */
5118 #if HOST_BITS_PER_WIDE_INT >= 64
5119 /* Count the number of bits in BYTES for which aligned stores could
5122 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
5126 /* If we have appropriate alignment (and it wouldn't take too many
5127 instructions otherwise), mask out the bytes we need. */
5128 if (TARGET_BWX
? words
> 2 : bytes
> 0)
5135 mem
= adjust_address (orig_dst
, DImode
, ofs
);
5136 set_mem_alias_set (mem
, 0);
5138 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5140 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
5141 NULL_RTX
, 1, OPTAB_WIDEN
);
5143 emit_move_insn (mem
, tmp
);
5146 else if (align
>= 32 && bytes
< 4)
5151 mem
= adjust_address (orig_dst
, SImode
, ofs
);
5152 set_mem_alias_set (mem
, 0);
5154 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5156 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
5157 NULL_RTX
, 1, OPTAB_WIDEN
);
5159 emit_move_insn (mem
, tmp
);
5165 if (!TARGET_BWX
&& bytes
>= 4)
5167 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
5177 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
5181 } while (bytes
>= 2);
5183 else if (! TARGET_BWX
)
5185 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
5193 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5201 /* Returns a mask so that zap(x, value) == x & mask. */
5204 alpha_expand_zap_mask (value
)
5205 HOST_WIDE_INT value
;
5210 if (HOST_BITS_PER_WIDE_INT
>= 64)
5212 HOST_WIDE_INT mask
= 0;
5214 for (i
= 7; i
>= 0; --i
)
5217 if (!((value
>> i
) & 1))
5221 result
= gen_int_mode (mask
, DImode
);
5223 else if (HOST_BITS_PER_WIDE_INT
== 32)
5225 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
5227 for (i
= 7; i
>= 4; --i
)
5230 if (!((value
>> i
) & 1))
5234 for (i
= 3; i
>= 0; --i
)
5237 if (!((value
>> i
) & 1))
5241 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
5250 alpha_expand_builtin_vector_binop (gen
, mode
, op0
, op1
, op2
)
5251 rtx (*gen
) PARAMS ((rtx
, rtx
, rtx
));
5252 enum machine_mode mode
;
5255 op0
= gen_lowpart (mode
, op0
);
5257 if (op1
== const0_rtx
)
5258 op1
= CONST0_RTX (mode
);
5260 op1
= gen_lowpart (mode
, op1
);
5262 if (op2
== const0_rtx
)
5263 op2
= CONST0_RTX (mode
);
5265 op2
= gen_lowpart (mode
, op2
);
5267 emit_insn ((*gen
) (op0
, op1
, op2
));
5270 /* Adjust the cost of a scheduling dependency. Return the new cost of
5271 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5274 alpha_adjust_cost (insn
, link
, dep_insn
, cost
)
5280 enum attr_type insn_type
, dep_insn_type
;
5282 /* If the dependence is an anti-dependence, there is no cost. For an
5283 output dependence, there is sometimes a cost, but it doesn't seem
5284 worth handling those few cases. */
5285 if (REG_NOTE_KIND (link
) != 0)
5288 /* If we can't recognize the insns, we can't really do anything. */
5289 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
5292 insn_type
= get_attr_type (insn
);
5293 dep_insn_type
= get_attr_type (dep_insn
);
5295 /* Bring in the user-defined memory latency. */
5296 if (dep_insn_type
== TYPE_ILD
5297 || dep_insn_type
== TYPE_FLD
5298 || dep_insn_type
== TYPE_LDSYM
)
5299 cost
+= alpha_memory_latency
-1;
5301 /* Everything else handled in DFA bypasses now. */
5306 /* The number of instructions that can be issued per cycle. */
5311 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
5315 alpha_use_dfa_pipeline_interface ()
5320 /* How many alternative schedules to try. This should be as wide as the
5321 scheduling freedom in the DFA, but no wider. Making this value too
5322 large results extra work for the scheduler.
5324 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5325 alternative schedules. For EV5, we can choose between E0/E1 and
5326 FA/FM. For EV6, an arithmatic insn can be issued to U0/U1/L0/L1. */
5329 alpha_multipass_dfa_lookahead ()
5331 return (alpha_cpu
== PROCESSOR_EV6
? 4 : 2);
5334 /* Machine-specific function data. */
5336 struct machine_function
GTY(())
5339 /* List of call information words for calls from this function. */
5340 struct rtx_def
*first_ciw
;
5341 struct rtx_def
*last_ciw
;
5344 /* List of deferred case vectors. */
5345 struct rtx_def
*addr_list
;
5348 const char *some_ld_name
;
5351 /* How to allocate a 'struct machine_function'. */
5353 static struct machine_function
*
5354 alpha_init_machine_status ()
5356 return ((struct machine_function
*)
5357 ggc_alloc_cleared (sizeof (struct machine_function
)));
5360 /* Functions to save and restore alpha_return_addr_rtx. */
5362 /* Start the ball rolling with RETURN_ADDR_RTX. */
5365 alpha_return_addr (count
, frame
)
5367 rtx frame ATTRIBUTE_UNUSED
;
5372 return get_hard_reg_initial_val (Pmode
, REG_RA
);
5375 /* Return or create a pseudo containing the gp value for the current
5376 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5379 alpha_gp_save_rtx ()
5381 rtx r
= get_hard_reg_initial_val (DImode
, 29);
5382 if (GET_CODE (r
) != MEM
)
5383 r
= gen_mem_addressof (r
, NULL_TREE
);
5388 alpha_ra_ever_killed ()
5392 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
5393 return regs_ever_live
[REG_RA
];
5395 push_topmost_sequence ();
5397 pop_topmost_sequence ();
5399 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
5403 /* Return the trap mode suffix applicable to the current
5404 instruction, or NULL. */
5407 get_trap_mode_suffix ()
5409 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
5413 case TRAP_SUFFIX_NONE
:
5416 case TRAP_SUFFIX_SU
:
5417 if (alpha_fptm
>= ALPHA_FPTM_SU
)
5421 case TRAP_SUFFIX_SUI
:
5422 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
5426 case TRAP_SUFFIX_V_SV
:
5434 case ALPHA_FPTM_SUI
:
5439 case TRAP_SUFFIX_V_SV_SVI
:
5448 case ALPHA_FPTM_SUI
:
5453 case TRAP_SUFFIX_U_SU_SUI
:
5462 case ALPHA_FPTM_SUI
:
5470 /* Return the rounding mode suffix applicable to the current
5471 instruction, or NULL. */
5474 get_round_mode_suffix ()
5476 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5480 case ROUND_SUFFIX_NONE
:
5482 case ROUND_SUFFIX_NORMAL
:
5485 case ALPHA_FPRM_NORM
:
5487 case ALPHA_FPRM_MINF
:
5489 case ALPHA_FPRM_CHOP
:
5491 case ALPHA_FPRM_DYN
:
5496 case ROUND_SUFFIX_C
:
5502 /* Locate some local-dynamic symbol still in use by this function
5503 so that we can print its name in some movdi_er_tlsldm pattern. */
5506 get_some_local_dynamic_name ()
5510 if (cfun
->machine
->some_ld_name
)
5511 return cfun
->machine
->some_ld_name
;
5513 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5515 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5516 return cfun
->machine
->some_ld_name
;
5522 get_some_local_dynamic_name_1 (px
, data
)
5524 void *data ATTRIBUTE_UNUSED
;
5528 if (GET_CODE (x
) == SYMBOL_REF
)
5530 const char *str
= XSTR (x
, 0);
5531 if (str
[0] == '@' && str
[1] == 'D')
5533 cfun
->machine
->some_ld_name
= str
;
5541 /* Print an operand. Recognize special options, documented below. */
5544 print_operand (file
, x
, code
)
5554 /* Print the assembler name of the current function. */
5555 assemble_name (file
, alpha_fnname
);
5559 assemble_name (file
, get_some_local_dynamic_name ());
5564 const char *trap
= get_trap_mode_suffix ();
5565 const char *round
= get_round_mode_suffix ();
5568 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5569 (trap
? trap
: ""), (round
? round
: ""));
5574 /* Generates single precision instruction suffix. */
5575 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5579 /* Generates double precision instruction suffix. */
5580 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5584 if (alpha_this_literal_sequence_number
== 0)
5585 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5586 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5590 if (alpha_this_gpdisp_sequence_number
== 0)
5591 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5592 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5596 if (GET_CODE (x
) == HIGH
)
5597 output_addr_const (file
, XEXP (x
, 0));
5599 output_operand_lossage ("invalid %%H value");
5606 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5608 x
= XVECEXP (x
, 0, 0);
5609 lituse
= "lituse_tlsgd";
5611 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5613 x
= XVECEXP (x
, 0, 0);
5614 lituse
= "lituse_tlsldm";
5616 else if (GET_CODE (x
) == CONST_INT
)
5617 lituse
= "lituse_jsr";
5620 output_operand_lossage ("invalid %%J value");
5624 if (x
!= const0_rtx
)
5625 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5630 /* If this operand is the constant zero, write it as "$31". */
5631 if (GET_CODE (x
) == REG
)
5632 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5633 else if (x
== CONST0_RTX (GET_MODE (x
)))
5634 fprintf (file
, "$31");
5636 output_operand_lossage ("invalid %%r value");
5640 /* Similar, but for floating-point. */
5641 if (GET_CODE (x
) == REG
)
5642 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5643 else if (x
== CONST0_RTX (GET_MODE (x
)))
5644 fprintf (file
, "$f31");
5646 output_operand_lossage ("invalid %%R value");
5650 /* Write the 1's complement of a constant. */
5651 if (GET_CODE (x
) != CONST_INT
)
5652 output_operand_lossage ("invalid %%N value");
5654 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5658 /* Write 1 << C, for a constant C. */
5659 if (GET_CODE (x
) != CONST_INT
)
5660 output_operand_lossage ("invalid %%P value");
5662 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5666 /* Write the high-order 16 bits of a constant, sign-extended. */
5667 if (GET_CODE (x
) != CONST_INT
)
5668 output_operand_lossage ("invalid %%h value");
5670 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5674 /* Write the low-order 16 bits of a constant, sign-extended. */
5675 if (GET_CODE (x
) != CONST_INT
)
5676 output_operand_lossage ("invalid %%L value");
5678 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5679 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5683 /* Write mask for ZAP insn. */
5684 if (GET_CODE (x
) == CONST_DOUBLE
)
5686 HOST_WIDE_INT mask
= 0;
5687 HOST_WIDE_INT value
;
5689 value
= CONST_DOUBLE_LOW (x
);
5690 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5695 value
= CONST_DOUBLE_HIGH (x
);
5696 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5699 mask
|= (1 << (i
+ sizeof (int)));
5701 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5704 else if (GET_CODE (x
) == CONST_INT
)
5706 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5708 for (i
= 0; i
< 8; i
++, value
>>= 8)
5712 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5715 output_operand_lossage ("invalid %%m value");
5719 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5720 if (GET_CODE (x
) != CONST_INT
5721 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5722 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5723 output_operand_lossage ("invalid %%M value");
5725 fprintf (file
, "%s",
5726 (INTVAL (x
) == 8 ? "b"
5727 : INTVAL (x
) == 16 ? "w"
5728 : INTVAL (x
) == 32 ? "l"
5733 /* Similar, except do it from the mask. */
5734 if (GET_CODE (x
) == CONST_INT
)
5736 HOST_WIDE_INT value
= INTVAL (x
);
5743 if (value
== 0xffff)
5748 if (value
== 0xffffffff)
5759 else if (HOST_BITS_PER_WIDE_INT
== 32
5760 && GET_CODE (x
) == CONST_DOUBLE
5761 && CONST_DOUBLE_LOW (x
) == 0xffffffff
5762 && CONST_DOUBLE_HIGH (x
) == 0)
5767 output_operand_lossage ("invalid %%U value");
5771 /* Write the constant value divided by 8 for little-endian mode or
5772 (56 - value) / 8 for big-endian mode. */
5774 if (GET_CODE (x
) != CONST_INT
5775 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5778 || (INTVAL (x
) & 7) != 0)
5779 output_operand_lossage ("invalid %%s value");
5781 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5783 ? (56 - INTVAL (x
)) / 8
5788 /* Same, except compute (64 - c) / 8 */
5790 if (GET_CODE (x
) != CONST_INT
5791 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5792 && (INTVAL (x
) & 7) != 8)
5793 output_operand_lossage ("invalid %%s value");
5795 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5800 /* On Unicos/Mk systems: use a DEX expression if the symbol
5801 clashes with a register name. */
5802 int dex
= unicosmk_need_dex (x
);
5804 fprintf (file
, "DEX(%d)", dex
);
5806 output_addr_const (file
, x
);
5810 case 'C': case 'D': case 'c': case 'd':
5811 /* Write out comparison name. */
5813 enum rtx_code c
= GET_CODE (x
);
5815 if (GET_RTX_CLASS (c
) != '<')
5816 output_operand_lossage ("invalid %%C value");
5818 else if (code
== 'D')
5819 c
= reverse_condition (c
);
5820 else if (code
== 'c')
5821 c
= swap_condition (c
);
5822 else if (code
== 'd')
5823 c
= swap_condition (reverse_condition (c
));
5826 fprintf (file
, "ule");
5828 fprintf (file
, "ult");
5829 else if (c
== UNORDERED
)
5830 fprintf (file
, "un");
5832 fprintf (file
, "%s", GET_RTX_NAME (c
));
5837 /* Write the divide or modulus operator. */
5838 switch (GET_CODE (x
))
5841 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5844 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5847 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5850 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5853 output_operand_lossage ("invalid %%E value");
5859 /* Write "_u" for unaligned access. */
5860 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
5861 fprintf (file
, "_u");
5865 if (GET_CODE (x
) == REG
)
5866 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5867 else if (GET_CODE (x
) == MEM
)
5868 output_address (XEXP (x
, 0));
5869 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
5871 switch (XINT (XEXP (x
, 0), 1))
5875 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
5878 output_operand_lossage ("unknown relocation unspec");
5883 output_addr_const (file
, x
);
5887 output_operand_lossage ("invalid %%xn code");
5892 print_operand_address (file
, addr
)
5897 HOST_WIDE_INT offset
= 0;
5899 if (GET_CODE (addr
) == AND
)
5900 addr
= XEXP (addr
, 0);
5902 if (GET_CODE (addr
) == PLUS
5903 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5905 offset
= INTVAL (XEXP (addr
, 1));
5906 addr
= XEXP (addr
, 0);
5909 if (GET_CODE (addr
) == LO_SUM
)
5911 const char *reloc16
, *reloclo
;
5912 rtx op1
= XEXP (addr
, 1);
5914 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
5916 op1
= XEXP (op1
, 0);
5917 switch (XINT (op1
, 1))
5921 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
5925 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
5928 output_operand_lossage ("unknown relocation unspec");
5932 output_addr_const (file
, XVECEXP (op1
, 0, 0));
5937 reloclo
= "gprellow";
5938 output_addr_const (file
, op1
);
5944 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
5947 addr
= XEXP (addr
, 0);
5948 if (GET_CODE (addr
) == REG
)
5949 basereg
= REGNO (addr
);
5950 else if (GET_CODE (addr
) == SUBREG
5951 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5952 basereg
= subreg_regno (addr
);
5956 fprintf (file
, "($%d)\t\t!%s", basereg
,
5957 (basereg
== 29 ? reloc16
: reloclo
));
5961 if (GET_CODE (addr
) == REG
)
5962 basereg
= REGNO (addr
);
5963 else if (GET_CODE (addr
) == SUBREG
5964 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5965 basereg
= subreg_regno (addr
);
5966 else if (GET_CODE (addr
) == CONST_INT
)
5967 offset
= INTVAL (addr
);
5969 #if TARGET_ABI_OPEN_VMS
5970 else if (GET_CODE (addr
) == SYMBOL_REF
)
5972 fprintf (file
, "%s", XSTR (addr
, 0));
5975 else if (GET_CODE (addr
) == CONST
5976 && GET_CODE (XEXP (addr
, 0)) == PLUS
5977 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
5979 fprintf (file
, "%s+%d",
5980 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
5981 INTVAL (XEXP (XEXP (addr
, 0), 1)));
5989 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
5990 fprintf (file
, "($%d)", basereg
);
5993 /* Emit RTL insns to initialize the variable parts of a trampoline at
5994 TRAMP. FNADDR is an RTX for the address of the function's pure
5995 code. CXT is an RTX for the static chain value for the function.
5997 The three offset parameters are for the individual template's
5998 layout. A JMPOFS < 0 indicates that the trampoline does not
5999 contain instructions at all.
6001 We assume here that a function will be called many more times than
6002 its address is taken (e.g., it might be passed to qsort), so we
6003 take the trouble to initialize the "hint" field in the JMP insn.
6004 Note that the hint field is PC (new) + 4 * bits 13:0. */
6007 alpha_initialize_trampoline (tramp
, fnaddr
, cxt
, fnofs
, cxtofs
, jmpofs
)
6008 rtx tramp
, fnaddr
, cxt
;
6009 int fnofs
, cxtofs
, jmpofs
;
6011 rtx temp
, temp1
, addr
;
6012 /* VMS really uses DImode pointers in memory at this point. */
6013 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
6015 #ifdef POINTERS_EXTEND_UNSIGNED
6016 fnaddr
= convert_memory_address (mode
, fnaddr
);
6017 cxt
= convert_memory_address (mode
, cxt
);
6020 /* Store function address and CXT. */
6021 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
6022 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
6023 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
6024 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
6026 /* This has been disabled since the hint only has a 32k range, and in
6027 no existing OS is the stack within 32k of the text segment. */
6028 if (0 && jmpofs
>= 0)
6030 /* Compute hint value. */
6031 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
6032 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
6034 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
6035 build_int_2 (2, 0), NULL_RTX
, 1);
6036 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
6037 GEN_INT (0x3fff), 0);
6039 /* Merge in the hint. */
6040 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
6041 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
6042 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
6043 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
6045 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
6048 #ifdef TRANSFER_FROM_TRAMPOLINE
6049 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
6050 0, VOIDmode
, 1, addr
, Pmode
);
6054 emit_insn (gen_imb ());
6057 /* Determine where to put an argument to a function.
6058 Value is zero to push the argument on the stack,
6059 or a hard register in which to store the argument.
6061 MODE is the argument's machine mode.
6062 TYPE is the data type of the argument (as a tree).
6063 This is null for libcalls where that information may
6065 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6066 the preceding args and about the function being called.
6067 NAMED is nonzero if this argument is a named parameter
6068 (otherwise it is an extra parameter matching an ellipsis).
6070 On Alpha the first 6 words of args are normally in registers
6071 and the rest are pushed. */
6074 function_arg (cum
, mode
, type
, named
)
6075 CUMULATIVE_ARGS cum
;
6076 enum machine_mode mode
;
6078 int named ATTRIBUTE_UNUSED
;
6083 /* Set up defaults for FP operands passed in FP registers, and
6084 integral operands passed in integer registers. */
6086 && (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
6087 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
6092 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
6093 the three platforms, so we can't avoid conditional compilation. */
6094 #if TARGET_ABI_OPEN_VMS
6096 if (mode
== VOIDmode
)
6097 return alpha_arg_info_reg_val (cum
);
6099 num_args
= cum
.num_args
;
6100 if (num_args
>= 6 || MUST_PASS_IN_STACK (mode
, type
))
6104 #if TARGET_ABI_UNICOSMK
6108 /* If this is the last argument, generate the call info word (CIW). */
6109 /* ??? We don't include the caller's line number in the CIW because
6110 I don't know how to determine it if debug infos are turned off. */
6111 if (mode
== VOIDmode
)
6120 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
6121 if (cum
.reg_args_type
[i
])
6122 lo
|= (1 << (7 - i
));
6124 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
6127 lo
|= cum
.num_reg_words
;
6129 #if HOST_BITS_PER_WIDE_INT == 32
6130 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
6132 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
6133 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
6136 ciw
= immed_double_const (lo
, hi
, DImode
);
6138 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
6139 UNSPEC_UMK_LOAD_CIW
);
6142 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
6143 num_args
= cum
.num_reg_words
;
6144 if (MUST_PASS_IN_STACK (mode
, type
)
6145 || cum
.num_reg_words
+ size
> 6 || cum
.force_stack
)
6147 else if (type
&& TYPE_MODE (type
) == BLKmode
)
6151 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
6152 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
6154 /* The argument fits in two registers. Note that we still need to
6155 reserve a register for empty structures. */
6159 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
6162 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
6163 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
6164 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
6174 /* VOID is passed as a special flag for "last argument". */
6175 if (type
== void_type_node
)
6177 else if (MUST_PASS_IN_STACK (mode
, type
))
6179 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum
, mode
, type
, named
))
6182 #endif /* TARGET_ABI_UNICOSMK */
6183 #endif /* TARGET_ABI_OPEN_VMS */
6185 return gen_rtx_REG (mode
, num_args
+ basereg
);
6189 alpha_build_va_list ()
6191 tree base
, ofs
, record
, type_decl
;
6193 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6194 return ptr_type_node
;
6196 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6197 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6198 TREE_CHAIN (record
) = type_decl
;
6199 TYPE_NAME (record
) = type_decl
;
6201 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6203 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
6205 DECL_FIELD_CONTEXT (ofs
) = record
;
6207 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
6209 DECL_FIELD_CONTEXT (base
) = record
;
6210 TREE_CHAIN (base
) = ofs
;
6212 TYPE_FIELDS (record
) = base
;
6213 layout_type (record
);
6219 alpha_va_start (valist
, nextarg
)
6221 rtx nextarg ATTRIBUTE_UNUSED
;
6223 HOST_WIDE_INT offset
;
6224 tree t
, offset_field
, base_field
;
6226 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6229 if (TARGET_ABI_UNICOSMK
)
6230 std_expand_builtin_va_start (valist
, nextarg
);
6232 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6233 up by 48, storing fp arg registers in the first 48 bytes, and the
6234 integer arg registers in the next 48 bytes. This is only done,
6235 however, if any integer registers need to be stored.
6237 If no integer registers need be stored, then we must subtract 48
6238 in order to account for the integer arg registers which are counted
6239 in argsize above, but which are not actually stored on the stack. */
6242 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6244 offset
= -6 * UNITS_PER_WORD
;
6246 if (TARGET_ABI_OPEN_VMS
)
6248 nextarg
= plus_constant (nextarg
, offset
);
6249 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
6250 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
6251 make_tree (ptr_type_node
, nextarg
));
6252 TREE_SIDE_EFFECTS (t
) = 1;
6254 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6258 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6259 offset_field
= TREE_CHAIN (base_field
);
6261 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6262 valist
, base_field
);
6263 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6264 valist
, offset_field
);
6266 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6267 t
= build (PLUS_EXPR
, ptr_type_node
, t
, build_int_2 (offset
, 0));
6268 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6269 TREE_SIDE_EFFECTS (t
) = 1;
6270 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6272 t
= build_int_2 (NUM_ARGS
* UNITS_PER_WORD
, 0);
6273 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6274 TREE_SIDE_EFFECTS (t
) = 1;
6275 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6280 alpha_va_arg (valist
, type
)
6284 tree t
, type_size
, rounded_size
;
6285 tree offset_field
, base_field
, addr_tree
, addend
;
6286 tree wide_type
, wide_ofs
;
6289 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6290 return std_expand_builtin_va_arg (valist
, type
);
6292 if (type
== error_mark_node
6293 || (type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
))) == NULL
6294 || TREE_OVERFLOW (type_size
))
6295 rounded_size
= size_zero_node
;
6297 rounded_size
= fold (build (MULT_EXPR
, sizetype
,
6298 fold (build (TRUNC_DIV_EXPR
, sizetype
,
6299 fold (build (PLUS_EXPR
, sizetype
,
6305 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6306 offset_field
= TREE_CHAIN (base_field
);
6308 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6309 valist
, base_field
);
6310 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6311 valist
, offset_field
);
6313 /* If the type could not be passed in registers, skip the block
6314 reserved for the registers. */
6315 if (MUST_PASS_IN_STACK (TYPE_MODE (type
), type
))
6317 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6318 build (MAX_EXPR
, TREE_TYPE (offset_field
),
6319 offset_field
, build_int_2 (6*8, 0)));
6320 TREE_SIDE_EFFECTS (t
) = 1;
6321 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6324 wide_type
= make_signed_type (64);
6325 wide_ofs
= save_expr (build1 (CONVERT_EXPR
, wide_type
, offset_field
));
6329 if (TYPE_MODE (type
) == TFmode
|| TYPE_MODE (type
) == TCmode
)
6332 rounded_size
= size_int (UNITS_PER_WORD
);
6334 else if (FLOAT_TYPE_P (type
))
6336 tree fpaddend
, cond
;
6338 fpaddend
= fold (build (PLUS_EXPR
, TREE_TYPE (addend
),
6339 addend
, build_int_2 (-6*8, 0)));
6341 cond
= fold (build (LT_EXPR
, integer_type_node
,
6342 wide_ofs
, build_int_2 (6*8, 0)));
6344 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
6348 addr_tree
= build (PLUS_EXPR
, TREE_TYPE (base_field
),
6349 base_field
, addend
);
6351 addr
= expand_expr (addr_tree
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
6352 addr
= copy_to_reg (addr
);
6354 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6355 build (PLUS_EXPR
, TREE_TYPE (offset_field
),
6356 offset_field
, rounded_size
));
6357 TREE_SIDE_EFFECTS (t
) = 1;
6358 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6362 addr
= force_reg (Pmode
, addr
);
6363 addr
= gen_rtx_MEM (Pmode
, addr
);
6373 ALPHA_BUILTIN_CMPBGE
,
6374 ALPHA_BUILTIN_EXTBL
,
6375 ALPHA_BUILTIN_EXTWL
,
6376 ALPHA_BUILTIN_EXTLL
,
6377 ALPHA_BUILTIN_EXTQL
,
6378 ALPHA_BUILTIN_EXTWH
,
6379 ALPHA_BUILTIN_EXTLH
,
6380 ALPHA_BUILTIN_EXTQH
,
6381 ALPHA_BUILTIN_INSBL
,
6382 ALPHA_BUILTIN_INSWL
,
6383 ALPHA_BUILTIN_INSLL
,
6384 ALPHA_BUILTIN_INSQL
,
6385 ALPHA_BUILTIN_INSWH
,
6386 ALPHA_BUILTIN_INSLH
,
6387 ALPHA_BUILTIN_INSQH
,
6388 ALPHA_BUILTIN_MSKBL
,
6389 ALPHA_BUILTIN_MSKWL
,
6390 ALPHA_BUILTIN_MSKLL
,
6391 ALPHA_BUILTIN_MSKQL
,
6392 ALPHA_BUILTIN_MSKWH
,
6393 ALPHA_BUILTIN_MSKLH
,
6394 ALPHA_BUILTIN_MSKQH
,
6395 ALPHA_BUILTIN_UMULH
,
6397 ALPHA_BUILTIN_ZAPNOT
,
6398 ALPHA_BUILTIN_AMASK
,
6399 ALPHA_BUILTIN_IMPLVER
,
6401 ALPHA_BUILTIN_THREAD_POINTER
,
6402 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6405 ALPHA_BUILTIN_MINUB8
,
6406 ALPHA_BUILTIN_MINSB8
,
6407 ALPHA_BUILTIN_MINUW4
,
6408 ALPHA_BUILTIN_MINSW4
,
6409 ALPHA_BUILTIN_MAXUB8
,
6410 ALPHA_BUILTIN_MAXSB8
,
6411 ALPHA_BUILTIN_MAXUW4
,
6412 ALPHA_BUILTIN_MAXSW4
,
6416 ALPHA_BUILTIN_UNPKBL
,
6417 ALPHA_BUILTIN_UNPKBW
,
6422 ALPHA_BUILTIN_CTPOP
,
6427 static unsigned int const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6428 CODE_FOR_builtin_cmpbge
,
6429 CODE_FOR_builtin_extbl
,
6430 CODE_FOR_builtin_extwl
,
6431 CODE_FOR_builtin_extll
,
6432 CODE_FOR_builtin_extql
,
6433 CODE_FOR_builtin_extwh
,
6434 CODE_FOR_builtin_extlh
,
6435 CODE_FOR_builtin_extqh
,
6436 CODE_FOR_builtin_insbl
,
6437 CODE_FOR_builtin_inswl
,
6438 CODE_FOR_builtin_insll
,
6439 CODE_FOR_builtin_insql
,
6440 CODE_FOR_builtin_inswh
,
6441 CODE_FOR_builtin_inslh
,
6442 CODE_FOR_builtin_insqh
,
6443 CODE_FOR_builtin_mskbl
,
6444 CODE_FOR_builtin_mskwl
,
6445 CODE_FOR_builtin_mskll
,
6446 CODE_FOR_builtin_mskql
,
6447 CODE_FOR_builtin_mskwh
,
6448 CODE_FOR_builtin_msklh
,
6449 CODE_FOR_builtin_mskqh
,
6450 CODE_FOR_umuldi3_highpart
,
6451 CODE_FOR_builtin_zap
,
6452 CODE_FOR_builtin_zapnot
,
6453 CODE_FOR_builtin_amask
,
6454 CODE_FOR_builtin_implver
,
6455 CODE_FOR_builtin_rpcc
,
6460 CODE_FOR_builtin_minub8
,
6461 CODE_FOR_builtin_minsb8
,
6462 CODE_FOR_builtin_minuw4
,
6463 CODE_FOR_builtin_minsw4
,
6464 CODE_FOR_builtin_maxub8
,
6465 CODE_FOR_builtin_maxsb8
,
6466 CODE_FOR_builtin_maxuw4
,
6467 CODE_FOR_builtin_maxsw4
,
6468 CODE_FOR_builtin_perr
,
6469 CODE_FOR_builtin_pklb
,
6470 CODE_FOR_builtin_pkwb
,
6471 CODE_FOR_builtin_unpkbl
,
6472 CODE_FOR_builtin_unpkbw
,
6475 CODE_FOR_builtin_cttz
,
6476 CODE_FOR_builtin_ctlz
,
6477 CODE_FOR_builtin_ctpop
6480 struct alpha_builtin_def
6483 enum alpha_builtin code
;
6484 unsigned int target_mask
;
6487 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6488 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0 },
6489 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0 }
6492 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6493 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0 },
6494 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
},
6495 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
},
6496 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
},
6497 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
},
6498 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
},
6499 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
},
6500 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
}
6503 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6504 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0 },
6505 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0 },
6506 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0 },
6507 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0 },
6508 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0 },
6509 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0 },
6510 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0 },
6511 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0 },
6512 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0 },
6513 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0 },
6514 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0 },
6515 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0 },
6516 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0 },
6517 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0 },
6518 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0 },
6519 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0 },
6520 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0 },
6521 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0 },
6522 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0 },
6523 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0 },
6524 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0 },
6525 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0 },
6526 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0 },
6527 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0 },
6528 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0 },
6529 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
},
6530 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
},
6531 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
},
6532 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
},
6533 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
},
6534 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
},
6535 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
},
6536 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
},
6537 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
}
6541 alpha_init_builtins ()
6543 const struct alpha_builtin_def
*p
;
6547 ftype
= build_function_type (long_integer_type_node
, void_list_node
);
6549 p
= zero_arg_builtins
;
6550 for (i
= 0; i
< ARRAY_SIZE (zero_arg_builtins
); ++i
, ++p
)
6551 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6552 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6555 ftype
= build_function_type_list (long_integer_type_node
,
6556 long_integer_type_node
, NULL_TREE
);
6558 p
= one_arg_builtins
;
6559 for (i
= 0; i
< ARRAY_SIZE (one_arg_builtins
); ++i
, ++p
)
6560 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6561 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6564 ftype
= build_function_type_list (long_integer_type_node
,
6565 long_integer_type_node
,
6566 long_integer_type_node
, NULL_TREE
);
6568 p
= two_arg_builtins
;
6569 for (i
= 0; i
< ARRAY_SIZE (two_arg_builtins
); ++i
, ++p
)
6570 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6571 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6574 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6575 builtin_function ("__builtin_thread_pointer", ftype
,
6576 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
6579 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6580 builtin_function ("__builtin_set_thread_pointer", ftype
,
6581 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
6585 /* Expand an expression EXP that calls a built-in function,
6586 with result going to TARGET if that's convenient
6587 (and in mode MODE if that's convenient).
6588 SUBTARGET may be used as the target for computing one of EXP's operands.
6589 IGNORE is nonzero if the value is to be ignored. */
6592 alpha_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
6595 rtx subtarget ATTRIBUTE_UNUSED
;
6596 enum machine_mode mode ATTRIBUTE_UNUSED
;
6597 int ignore ATTRIBUTE_UNUSED
;
6601 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6602 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6603 tree arglist
= TREE_OPERAND (exp
, 1);
6604 enum insn_code icode
;
6605 rtx op
[MAX_ARGS
], pat
;
6609 if (fcode
>= ALPHA_BUILTIN_max
)
6610 internal_error ("bad builtin fcode");
6611 icode
= code_for_builtin
[fcode
];
6613 internal_error ("bad builtin fcode");
6615 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6617 for (arglist
= TREE_OPERAND (exp
, 1), arity
= 0;
6619 arglist
= TREE_CHAIN (arglist
), arity
++)
6621 const struct insn_operand_data
*insn_op
;
6623 tree arg
= TREE_VALUE (arglist
);
6624 if (arg
== error_mark_node
)
6626 if (arity
> MAX_ARGS
)
6629 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6631 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
6633 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6634 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6639 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6641 || GET_MODE (target
) != tmode
6642 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6643 target
= gen_reg_rtx (tmode
);
6649 pat
= GEN_FCN (icode
) (target
);
6653 pat
= GEN_FCN (icode
) (target
, op
[0]);
6655 pat
= GEN_FCN (icode
) (op
[0]);
6658 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6673 /* This page contains routines that are used to determine what the function
6674 prologue and epilogue code will do and write them out. */
6676 /* Compute the size of the save area in the stack. */
6678 /* These variables are used for communication between the following functions.
6679 They indicate various things about the current function being compiled
6680 that are used to tell what kind of prologue, epilogue and procedure
6681 descriptior to generate. */
6683 /* Nonzero if we need a stack procedure. */
6684 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
6685 static enum alpha_procedure_types alpha_procedure_type
;
6687 /* Register number (either FP or SP) that is used to unwind the frame. */
6688 static int vms_unwind_regno
;
6690 /* Register number used to save FP. We need not have one for RA since
6691 we don't modify it for register procedures. This is only defined
6692 for register frame procedures. */
6693 static int vms_save_fp_regno
;
6695 /* Register number used to reference objects off our PV. */
6696 static int vms_base_regno
;
6698 /* Compute register masks for saved registers. */
6701 alpha_sa_mask (imaskP
, fmaskP
)
6702 unsigned long *imaskP
;
6703 unsigned long *fmaskP
;
6705 unsigned long imask
= 0;
6706 unsigned long fmask
= 0;
6709 /* Irritatingly, there are two kinds of thunks -- those created with
6710 ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go through
6711 the regular part of the compiler. In the ASM_OUTPUT_MI_THUNK case
6712 we don't have valid register life info, but assemble_start_function
6713 wants to output .frame and .mask directives. */
6714 if (current_function_is_thunk
&& !no_new_pseudos
)
6721 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6722 imask
|= (1L << HARD_FRAME_POINTER_REGNUM
);
6724 /* One for every register we have to save. */
6725 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6726 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
6727 && regs_ever_live
[i
] && i
!= REG_RA
6728 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
6733 fmask
|= (1L << (i
- 32));
6736 /* We need to restore these for the handler. */
6737 if (current_function_calls_eh_return
)
6740 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
6741 if (regno
== INVALID_REGNUM
)
6743 imask
|= 1L << regno
;
6746 /* If any register spilled, then spill the return address also. */
6747 /* ??? This is required by the Digital stack unwind specification
6748 and isn't needed if we're doing Dwarf2 unwinding. */
6749 if (imask
|| fmask
|| alpha_ra_ever_killed ())
6750 imask
|= (1L << REG_RA
);
6759 unsigned long mask
[2];
6763 alpha_sa_mask (&mask
[0], &mask
[1]);
6765 if (TARGET_ABI_UNICOSMK
)
6767 if (mask
[0] || mask
[1])
6772 for (j
= 0; j
< 2; ++j
)
6773 for (i
= 0; i
< 32; ++i
)
6774 if ((mask
[j
] >> i
) & 1)
6778 if (TARGET_ABI_UNICOSMK
)
6780 /* We might not need to generate a frame if we don't make any calls
6781 (including calls to __T3E_MISMATCH if this is a vararg function),
6782 don't have any local variables which require stack slots, don't
6783 use alloca and have not determined that we need a frame for other
6786 alpha_procedure_type
6787 = (sa_size
|| get_frame_size() != 0
6788 || current_function_outgoing_args_size
6789 || current_function_stdarg
|| current_function_calls_alloca
6790 || frame_pointer_needed
)
6791 ? PT_STACK
: PT_REGISTER
;
6793 /* Always reserve space for saving callee-saved registers if we
6794 need a frame as required by the calling convention. */
6795 if (alpha_procedure_type
== PT_STACK
)
6798 else if (TARGET_ABI_OPEN_VMS
)
6800 /* Start by assuming we can use a register procedure if we don't
6801 make any calls (REG_RA not used) or need to save any
6802 registers and a stack procedure if we do. */
6803 if ((mask
[0] >> REG_RA
) & 1)
6804 alpha_procedure_type
= PT_STACK
;
6805 else if (get_frame_size() != 0)
6806 alpha_procedure_type
= PT_REGISTER
;
6808 alpha_procedure_type
= PT_NULL
;
6810 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6811 made the final decision on stack procedure vs register procedure. */
6812 if (alpha_procedure_type
== PT_STACK
)
6815 /* Decide whether to refer to objects off our PV via FP or PV.
6816 If we need FP for something else or if we receive a nonlocal
6817 goto (which expects PV to contain the value), we must use PV.
6818 Otherwise, start by assuming we can use FP. */
6821 = (frame_pointer_needed
6822 || current_function_has_nonlocal_label
6823 || alpha_procedure_type
== PT_STACK
6824 || current_function_outgoing_args_size
)
6825 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
6827 /* If we want to copy PV into FP, we need to find some register
6828 in which to save FP. */
6830 vms_save_fp_regno
= -1;
6831 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
6832 for (i
= 0; i
< 32; i
++)
6833 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
6834 vms_save_fp_regno
= i
;
6836 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
6837 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
6838 else if (alpha_procedure_type
== PT_NULL
)
6839 vms_base_regno
= REG_PV
;
6841 /* Stack unwinding should be done via FP unless we use it for PV. */
6842 vms_unwind_regno
= (vms_base_regno
== REG_PV
6843 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
6845 /* If this is a stack procedure, allow space for saving FP and RA. */
6846 if (alpha_procedure_type
== PT_STACK
)
6851 /* Our size must be even (multiple of 16 bytes). */
6860 alpha_pv_save_size ()
6863 return alpha_procedure_type
== PT_STACK
? 8 : 0;
6870 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
6873 #if TARGET_ABI_OPEN_VMS
6875 const struct attribute_spec vms_attribute_table
[] =
6877 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6878 { "overlaid", 0, 0, true, false, false, NULL
},
6879 { "global", 0, 0, true, false, false, NULL
},
6880 { "initialize", 0, 0, true, false, false, NULL
},
6881 { NULL
, 0, 0, false, false, false, NULL
}
6887 find_lo_sum (px
, data
)
6889 void *data ATTRIBUTE_UNUSED
;
6891 return GET_CODE (*px
) == LO_SUM
;
6895 alpha_does_function_need_gp ()
6899 /* The GP being variable is an OSF abi thing. */
6900 if (! TARGET_ABI_OSF
)
6903 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6906 if (current_function_is_thunk
)
6909 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6910 Even if we are a static function, we still need to do this in case
6911 our address is taken and passed to something like qsort. */
6913 push_topmost_sequence ();
6914 insn
= get_insns ();
6915 pop_topmost_sequence ();
6917 for (; insn
; insn
= NEXT_INSN (insn
))
6919 && GET_CODE (PATTERN (insn
)) != USE
6920 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6922 enum attr_type type
= get_attr_type (insn
);
6923 if (type
== TYPE_LDSYM
|| type
== TYPE_JSR
)
6925 if (TARGET_EXPLICIT_RELOCS
6926 && for_each_rtx (&PATTERN (insn
), find_lo_sum
, NULL
) > 0)
6933 /* Write a version stamp. Don't write anything if we are running as a
6934 cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
6941 alpha_write_verstamp (file
)
6942 FILE *file ATTRIBUTE_UNUSED
;
6945 fprintf (file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
6949 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6953 set_frame_related_p ()
6955 rtx seq
= get_insns ();
6966 while (insn
!= NULL_RTX
)
6968 RTX_FRAME_RELATED_P (insn
) = 1;
6969 insn
= NEXT_INSN (insn
);
6971 seq
= emit_insn (seq
);
6975 seq
= emit_insn (seq
);
6976 RTX_FRAME_RELATED_P (seq
) = 1;
6981 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
6983 /* Write function prologue. */
6985 /* On vms we have two kinds of functions:
6987 - stack frame (PROC_STACK)
6988 these are 'normal' functions with local vars and which are
6989 calling other functions
6990 - register frame (PROC_REGISTER)
6991 keeps all data in registers, needs no stack
6993 We must pass this to the assembler so it can generate the
6994 proper pdsc (procedure descriptor)
6995 This is done with the '.pdesc' command.
6997 On not-vms, we don't really differentiate between the two, as we can
6998 simply allocate stack without saving registers. */
7001 alpha_expand_prologue ()
7003 /* Registers to save. */
7004 unsigned long imask
= 0;
7005 unsigned long fmask
= 0;
7006 /* Stack space needed for pushing registers clobbered by us. */
7007 HOST_WIDE_INT sa_size
;
7008 /* Complete stack size needed. */
7009 HOST_WIDE_INT frame_size
;
7010 /* Offset from base reg to register save area. */
7011 HOST_WIDE_INT reg_offset
;
7015 sa_size
= alpha_sa_size ();
7017 frame_size
= get_frame_size ();
7018 if (TARGET_ABI_OPEN_VMS
)
7019 frame_size
= ALPHA_ROUND (sa_size
7020 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7022 + current_function_pretend_args_size
);
7023 else if (TARGET_ABI_UNICOSMK
)
7024 /* We have to allocate space for the DSIB if we generate a frame. */
7025 frame_size
= ALPHA_ROUND (sa_size
7026 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7027 + ALPHA_ROUND (frame_size
7028 + current_function_outgoing_args_size
);
7030 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7032 + ALPHA_ROUND (frame_size
7033 + current_function_pretend_args_size
));
7035 if (TARGET_ABI_OPEN_VMS
)
7038 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7040 alpha_sa_mask (&imask
, &fmask
);
7042 /* Emit an insn to reload GP, if needed. */
7045 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7046 if (alpha_function_needs_gp
)
7047 emit_insn (gen_prologue_ldgp ());
7050 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7051 the call to mcount ourselves, rather than having the linker do it
7052 magically in response to -pg. Since _mcount has special linkage,
7053 don't represent the call as a call. */
7054 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7055 emit_insn (gen_prologue_mcount ());
7057 if (TARGET_ABI_UNICOSMK
)
7058 unicosmk_gen_dsib (&imask
);
7060 /* Adjust the stack by the frame size. If the frame size is > 4096
7061 bytes, we need to be sure we probe somewhere in the first and last
7062 4096 bytes (we can probably get away without the latter test) and
7063 every 8192 bytes in between. If the frame size is > 32768, we
7064 do this in a loop. Otherwise, we generate the explicit probe
7067 Note that we are only allowed to adjust sp once in the prologue. */
7069 if (frame_size
<= 32768)
7071 if (frame_size
> 4096)
7076 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7079 while ((probed
+= 8192) < frame_size
);
7081 /* We only have to do this probe if we aren't saving registers. */
7082 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
7083 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
7086 if (frame_size
!= 0)
7087 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7088 GEN_INT (TARGET_ABI_UNICOSMK
7094 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7095 number of 8192 byte blocks to probe. We then probe each block
7096 in the loop and then set SP to the proper location. If the
7097 amount remaining is > 4096, we have to do one more probe if we
7098 are not saving any registers. */
7100 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
7101 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
7102 rtx ptr
= gen_rtx_REG (DImode
, 22);
7103 rtx count
= gen_rtx_REG (DImode
, 23);
7106 emit_move_insn (count
, GEN_INT (blocks
));
7107 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7108 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7110 /* Because of the difficulty in emitting a new basic block this
7111 late in the compilation, generate the loop as a single insn. */
7112 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7114 if (leftover
> 4096 && sa_size
== 0)
7116 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7117 MEM_VOLATILE_P (last
) = 1;
7118 emit_move_insn (last
, const0_rtx
);
7121 if (TARGET_ABI_WINDOWS_NT
)
7123 /* For NT stack unwind (done by 'reverse execution'), it's
7124 not OK to take the result of a loop, even though the value
7125 is already in ptr, so we reload it via a single operation
7126 and subtract it to sp.
7128 Yes, that's correct -- we have to reload the whole constant
7129 into a temporary via ldah+lda then subtract from sp. To
7130 ensure we get ldah+lda, we use a special pattern. */
7132 HOST_WIDE_INT lo
, hi
;
7133 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7134 hi
= frame_size
- lo
;
7136 emit_move_insn (ptr
, GEN_INT (hi
));
7137 emit_insn (gen_nt_lda (ptr
, GEN_INT (lo
)));
7138 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7143 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7144 GEN_INT (-leftover
)));
7147 /* This alternative is special, because the DWARF code cannot
7148 possibly intuit through the loop above. So we invent this
7149 note it looks at instead. */
7150 RTX_FRAME_RELATED_P (seq
) = 1;
7152 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7153 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7154 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7155 GEN_INT (TARGET_ABI_UNICOSMK
7161 if (!TARGET_ABI_UNICOSMK
)
7163 /* Cope with very large offsets to the register save area. */
7164 sa_reg
= stack_pointer_rtx
;
7165 if (reg_offset
+ sa_size
> 0x8000)
7167 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7170 if (low
+ sa_size
<= 0x8000)
7171 bias
= reg_offset
- low
, reg_offset
= low
;
7173 bias
= reg_offset
, reg_offset
= 0;
7175 sa_reg
= gen_rtx_REG (DImode
, 24);
7176 FRP (emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
,
7180 /* Save regs in stack order. Beginning with VMS PV. */
7181 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7183 mem
= gen_rtx_MEM (DImode
, stack_pointer_rtx
);
7184 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7185 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_PV
)));
7188 /* Save register RA next. */
7189 if (imask
& (1L << REG_RA
))
7191 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7192 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7193 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
7194 imask
&= ~(1L << REG_RA
);
7198 /* Now save any other registers required to be saved. */
7199 for (i
= 0; i
< 32; i
++)
7200 if (imask
& (1L << i
))
7202 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7203 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7204 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7208 for (i
= 0; i
< 32; i
++)
7209 if (fmask
& (1L << i
))
7211 mem
= gen_rtx_MEM (DFmode
, plus_constant (sa_reg
, reg_offset
));
7212 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7213 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7217 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7219 /* The standard frame on the T3E includes space for saving registers.
7220 We just have to use it. We don't have to save the return address and
7221 the old frame pointer here - they are saved in the DSIB. */
7224 for (i
= 9; i
< 15; i
++)
7225 if (imask
& (1L << i
))
7227 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7229 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7230 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7233 for (i
= 2; i
< 10; i
++)
7234 if (fmask
& (1L << i
))
7236 mem
= gen_rtx_MEM (DFmode
, plus_constant (hard_frame_pointer_rtx
,
7238 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7239 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7244 if (TARGET_ABI_OPEN_VMS
)
7246 if (alpha_procedure_type
== PT_REGISTER
)
7247 /* Register frame procedures save the fp.
7248 ?? Ought to have a dwarf2 save for this. */
7249 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7250 hard_frame_pointer_rtx
);
7252 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7253 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7254 gen_rtx_REG (DImode
, REG_PV
)));
7256 if (alpha_procedure_type
!= PT_NULL
7257 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7258 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7260 /* If we have to allocate space for outgoing args, do it now. */
7261 if (current_function_outgoing_args_size
!= 0)
7264 plus_constant (hard_frame_pointer_rtx
,
7266 (current_function_outgoing_args_size
)))));
7268 else if (!TARGET_ABI_UNICOSMK
)
7270 /* If we need a frame pointer, set it from the stack pointer. */
7271 if (frame_pointer_needed
)
7273 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7274 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7276 /* This must always be the last instruction in the
7277 prologue, thus we emit a special move + clobber. */
7278 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7279 stack_pointer_rtx
, sa_reg
)));
7283 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7284 the prologue, for exception handling reasons, we cannot do this for
7285 any insn that might fault. We could prevent this for mems with a
7286 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7287 have to prevent all such scheduling with a blockage.
7289 Linux, on the other hand, never bothered to implement OSF/1's
7290 exception handling, and so doesn't care about such things. Anyone
7291 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7293 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7294 emit_insn (gen_blockage ());
7297 /* Output the textual info surrounding the prologue. */
7300 alpha_start_function (file
, fnname
, decl
)
7303 tree decl ATTRIBUTE_UNUSED
;
7305 unsigned long imask
= 0;
7306 unsigned long fmask
= 0;
7307 /* Stack space needed for pushing registers clobbered by us. */
7308 HOST_WIDE_INT sa_size
;
7309 /* Complete stack size needed. */
7310 HOST_WIDE_INT frame_size
;
7311 /* Offset from base reg to register save area. */
7312 HOST_WIDE_INT reg_offset
;
7313 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7316 /* Don't emit an extern directive for functions defined in the same file. */
7317 if (TARGET_ABI_UNICOSMK
)
7320 name_tree
= get_identifier (fnname
);
7321 TREE_ASM_WRITTEN (name_tree
) = 1;
7324 alpha_fnname
= fnname
;
7325 sa_size
= alpha_sa_size ();
7327 frame_size
= get_frame_size ();
7328 if (TARGET_ABI_OPEN_VMS
)
7329 frame_size
= ALPHA_ROUND (sa_size
7330 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7332 + current_function_pretend_args_size
);
7333 else if (TARGET_ABI_UNICOSMK
)
7334 frame_size
= ALPHA_ROUND (sa_size
7335 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7336 + ALPHA_ROUND (frame_size
7337 + current_function_outgoing_args_size
);
7339 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7341 + ALPHA_ROUND (frame_size
7342 + current_function_pretend_args_size
));
7344 if (TARGET_ABI_OPEN_VMS
)
7347 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7349 alpha_sa_mask (&imask
, &fmask
);
7351 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7352 We have to do that before the .ent directive as we cannot switch
7353 files within procedures with native ecoff because line numbers are
7354 linked to procedure descriptors.
7355 Outputting the lineno helps debugging of one line functions as they
7356 would otherwise get no line number at all. Please note that we would
7357 like to put out last_linenum from final.c, but it is not accessible. */
7359 if (write_symbols
== SDB_DEBUG
)
7361 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7362 ASM_OUTPUT_SOURCE_FILENAME (file
,
7363 DECL_SOURCE_FILE (current_function_decl
));
7365 #ifdef ASM_OUTPUT_SOURCE_LINE
7366 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7367 ASM_OUTPUT_SOURCE_LINE (file
,
7368 DECL_SOURCE_LINE (current_function_decl
));
7372 /* Issue function start and label. */
7373 if (TARGET_ABI_OPEN_VMS
7374 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
7376 fputs ("\t.ent ", file
);
7377 assemble_name (file
, fnname
);
7380 /* If the function needs GP, we'll write the "..ng" label there.
7381 Otherwise, do it here. */
7383 && ! alpha_function_needs_gp
7384 && ! current_function_is_thunk
)
7387 assemble_name (file
, fnname
);
7388 fputs ("..ng:\n", file
);
7392 strcpy (entry_label
, fnname
);
7393 if (TARGET_ABI_OPEN_VMS
)
7394 strcat (entry_label
, "..en");
7396 /* For public functions, the label must be globalized by appending an
7397 additional colon. */
7398 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
7399 strcat (entry_label
, ":");
7401 ASM_OUTPUT_LABEL (file
, entry_label
);
7402 inside_function
= TRUE
;
7404 if (TARGET_ABI_OPEN_VMS
)
7405 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7407 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7408 && !flag_inhibit_size_directive
)
7410 /* Set flags in procedure descriptor to request IEEE-conformant
7411 math-library routines. The value we set it to is PDSC_EXC_IEEE
7412 (/usr/include/pdsc.h). */
7413 fputs ("\t.eflag 48\n", file
);
7416 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7417 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
7418 alpha_arg_offset
= -frame_size
+ 48;
7420 /* Describe our frame. If the frame size is larger than an integer,
7421 print it as zero to avoid an assembler error. We won't be
7422 properly describing such a frame, but that's the best we can do. */
7423 if (TARGET_ABI_UNICOSMK
)
7425 else if (TARGET_ABI_OPEN_VMS
)
7427 fprintf (file
, "\t.frame $%d,", vms_unwind_regno
);
7428 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7429 frame_size
>= ((HOST_WIDE_INT
) 1 << 31) ? 0 : frame_size
);
7430 fputs (",$26,", file
);
7431 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, reg_offset
);
7434 else if (!flag_inhibit_size_directive
)
7436 fprintf (file
, "\t.frame $%d,",
7437 (frame_pointer_needed
7438 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
));
7439 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7440 frame_size
>= (1l << 31) ? 0 : frame_size
);
7441 fprintf (file
, ",$26,%d\n", current_function_pretend_args_size
);
7444 /* Describe which registers were spilled. */
7445 if (TARGET_ABI_UNICOSMK
)
7447 else if (TARGET_ABI_OPEN_VMS
)
7450 /* ??? Does VMS care if mask contains ra? The old code didn't
7451 set it, so I don't here. */
7452 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1L << REG_RA
));
7454 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7455 if (alpha_procedure_type
== PT_REGISTER
)
7456 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7458 else if (!flag_inhibit_size_directive
)
7462 fprintf (file
, "\t.mask 0x%lx,", imask
);
7463 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7464 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
7467 for (i
= 0; i
< 32; ++i
)
7468 if (imask
& (1L << i
))
7474 fprintf (file
, "\t.fmask 0x%lx,", fmask
);
7475 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7476 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
7481 #if TARGET_ABI_OPEN_VMS
7482 /* Ifdef'ed cause link_section are only available then. */
7483 readonly_data_section ();
7484 fprintf (file
, "\t.align 3\n");
7485 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
7486 fputs ("\t.ascii \"", file
);
7487 assemble_name (file
, fnname
);
7488 fputs ("\\0\"\n", file
);
7489 alpha_need_linkage (fnname
, 1);
7494 /* Emit the .prologue note at the scheduled end of the prologue. */
7497 alpha_output_function_end_prologue (file
)
7500 if (TARGET_ABI_UNICOSMK
)
7502 else if (TARGET_ABI_OPEN_VMS
)
7503 fputs ("\t.prologue\n", file
);
7504 else if (TARGET_ABI_WINDOWS_NT
)
7505 fputs ("\t.prologue 0\n", file
);
7506 else if (!flag_inhibit_size_directive
)
7507 fprintf (file
, "\t.prologue %d\n",
7508 alpha_function_needs_gp
|| current_function_is_thunk
);
7511 /* Write function epilogue. */
7513 /* ??? At some point we will want to support full unwind, and so will
7514 need to mark the epilogue as well. At the moment, we just confuse
7517 #define FRP(exp) exp
7520 alpha_expand_epilogue ()
7522 /* Registers to save. */
7523 unsigned long imask
= 0;
7524 unsigned long fmask
= 0;
7525 /* Stack space needed for pushing registers clobbered by us. */
7526 HOST_WIDE_INT sa_size
;
7527 /* Complete stack size needed. */
7528 HOST_WIDE_INT frame_size
;
7529 /* Offset from base reg to register save area. */
7530 HOST_WIDE_INT reg_offset
;
7531 int fp_is_frame_pointer
, fp_offset
;
7532 rtx sa_reg
, sa_reg_exp
= NULL
;
7533 rtx sp_adj1
, sp_adj2
, mem
;
7537 sa_size
= alpha_sa_size ();
7539 frame_size
= get_frame_size ();
7540 if (TARGET_ABI_OPEN_VMS
)
7541 frame_size
= ALPHA_ROUND (sa_size
7542 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7544 + current_function_pretend_args_size
);
7545 else if (TARGET_ABI_UNICOSMK
)
7546 frame_size
= ALPHA_ROUND (sa_size
7547 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7548 + ALPHA_ROUND (frame_size
7549 + current_function_outgoing_args_size
);
7551 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7553 + ALPHA_ROUND (frame_size
7554 + current_function_pretend_args_size
));
7556 if (TARGET_ABI_OPEN_VMS
)
7558 if (alpha_procedure_type
== PT_STACK
)
7564 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7566 alpha_sa_mask (&imask
, &fmask
);
7569 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7570 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
7572 sa_reg
= stack_pointer_rtx
;
7574 if (current_function_calls_eh_return
)
7575 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7579 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
7581 /* If we have a frame pointer, restore SP from it. */
7582 if ((TARGET_ABI_OPEN_VMS
7583 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7584 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
7585 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7587 /* Cope with very large offsets to the register save area. */
7588 if (reg_offset
+ sa_size
> 0x8000)
7590 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7593 if (low
+ sa_size
<= 0x8000)
7594 bias
= reg_offset
- low
, reg_offset
= low
;
7596 bias
= reg_offset
, reg_offset
= 0;
7598 sa_reg
= gen_rtx_REG (DImode
, 22);
7599 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
7601 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
7604 /* Restore registers in order, excepting a true frame pointer. */
7606 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7608 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7609 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7612 imask
&= ~(1L << REG_RA
);
7614 for (i
= 0; i
< 32; ++i
)
7615 if (imask
& (1L << i
))
7617 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
7618 fp_offset
= reg_offset
;
7621 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
7622 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7623 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7628 for (i
= 0; i
< 32; ++i
)
7629 if (fmask
& (1L << i
))
7631 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
7632 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7633 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7637 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7639 /* Restore callee-saved general-purpose registers. */
7643 for (i
= 9; i
< 15; i
++)
7644 if (imask
& (1L << i
))
7646 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7648 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7649 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7653 for (i
= 2; i
< 10; i
++)
7654 if (fmask
& (1L << i
))
7656 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
7658 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7659 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7663 /* Restore the return address from the DSIB. */
7665 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
7666 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7667 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7670 if (frame_size
|| eh_ofs
)
7672 sp_adj1
= stack_pointer_rtx
;
7676 sp_adj1
= gen_rtx_REG (DImode
, 23);
7677 emit_move_insn (sp_adj1
,
7678 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
7681 /* If the stack size is large, begin computation into a temporary
7682 register so as not to interfere with a potential fp restore,
7683 which must be consecutive with an SP restore. */
7684 if (frame_size
< 32768
7685 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
7686 sp_adj2
= GEN_INT (frame_size
);
7687 else if (TARGET_ABI_UNICOSMK
)
7689 sp_adj1
= gen_rtx_REG (DImode
, 23);
7690 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
7691 sp_adj2
= const0_rtx
;
7693 else if (frame_size
< 0x40007fffL
)
7695 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7697 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
7698 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
7702 sp_adj1
= gen_rtx_REG (DImode
, 23);
7703 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
7705 sp_adj2
= GEN_INT (low
);
7709 rtx tmp
= gen_rtx_REG (DImode
, 23);
7710 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
7713 /* We can't drop new things to memory this late, afaik,
7714 so build it up by pieces. */
7715 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
7716 -(frame_size
< 0)));
7722 /* From now on, things must be in order. So emit blockages. */
7724 /* Restore the frame pointer. */
7725 if (TARGET_ABI_UNICOSMK
)
7727 emit_insn (gen_blockage ());
7728 mem
= gen_rtx_MEM (DImode
,
7729 plus_constant (hard_frame_pointer_rtx
, -16));
7730 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7731 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7733 else if (fp_is_frame_pointer
)
7735 emit_insn (gen_blockage ());
7736 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
7737 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7738 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7740 else if (TARGET_ABI_OPEN_VMS
)
7742 emit_insn (gen_blockage ());
7743 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7744 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7747 /* Restore the stack pointer. */
7748 emit_insn (gen_blockage ());
7749 if (sp_adj2
== const0_rtx
)
7750 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
7752 FRP (emit_move_insn (stack_pointer_rtx
,
7753 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
7757 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
7759 emit_insn (gen_blockage ());
7760 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7761 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7763 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
7765 /* Decrement the frame pointer if the function does not have a
7768 emit_insn (gen_blockage ());
7769 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7770 hard_frame_pointer_rtx
, GEN_INT (-1))));
7775 #if TARGET_ABI_OPEN_VMS
7776 #include <splay-tree.h>
7778 /* Structure to collect function names for final output
7781 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
7782 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
7794 enum links_kind lkind
;
7795 enum reloc_kind rkind
;
7798 static splay_tree alpha_funcs_tree
;
7799 static splay_tree alpha_links_tree
;
7801 static int mark_alpha_links_node
PARAMS ((splay_tree_node
, void *));
7802 static void mark_alpha_links
PARAMS ((void *));
7803 static int alpha_write_one_linkage
PARAMS ((splay_tree_node
, void *));
7805 static int alpha_funcs_num
;
7808 /* Output the rest of the textual info surrounding the epilogue. */
7811 alpha_end_function (file
, fnname
, decl
)
7816 /* End the function. */
7817 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
7819 fputs ("\t.end ", file
);
7820 assemble_name (file
, fnname
);
7823 inside_function
= FALSE
;
7825 #if TARGET_ABI_OPEN_VMS
7826 alpha_write_linkage (file
, fnname
, decl
);
7829 /* Show that we know this function if it is called again.
7831 Do this only for functions whose symbols bind locally.
7833 Don't do this for functions not defined in the .text section, as
7834 otherwise it's not unlikely that the destination is out of range
7835 for a direct branch. */
7837 if ((*targetm
.binds_local_p
) (decl
) && decl_in_text_section (decl
))
7838 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl
), 0)) = 1;
7840 /* Output jump tables and the static subroutine information block. */
7841 if (TARGET_ABI_UNICOSMK
)
7843 unicosmk_output_ssib (file
, fnname
);
7844 unicosmk_output_deferred_case_vectors (file
);
7848 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7850 In order to avoid the hordes of differences between generated code
7851 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7852 lots of code loading up large constants, generate rtl and emit it
7853 instead of going straight to text.
7855 Not sure why this idea hasn't been explored before... */
7858 alpha_output_mi_thunk_osf (file
, thunk_fndecl
, delta
, function
)
7860 tree thunk_fndecl ATTRIBUTE_UNUSED
;
7861 HOST_WIDE_INT delta
;
7864 HOST_WIDE_INT hi
, lo
;
7865 rtx
this, insn
, funexp
;
7867 /* We always require a valid GP. */
7868 emit_insn (gen_prologue_ldgp ());
7869 emit_note (NULL
, NOTE_INSN_PROLOGUE_END
);
7871 /* Find the "this" pointer. If the function returns a structure,
7872 the structure return pointer is in $16. */
7873 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
))))
7874 this = gen_rtx_REG (Pmode
, 17);
7876 this = gen_rtx_REG (Pmode
, 16);
7878 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7879 entire constant for the add. */
7880 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
7881 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7882 if (hi
+ lo
== delta
)
7885 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
7887 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
7891 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
7892 delta
, -(delta
< 0));
7893 emit_insn (gen_adddi3 (this, this, tmp
));
7896 /* Generate a tail call to the target function. */
7897 if (! TREE_USED (function
))
7899 assemble_external (function
);
7900 TREE_USED (function
) = 1;
7902 funexp
= XEXP (DECL_RTL (function
), 0);
7903 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
7904 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
7905 SIBLING_CALL_P (insn
) = 1;
7907 /* Run just enough of rest_of_compilation to get the insns emitted.
7908 There's not really enough bulk here to make other passes such as
7909 instruction scheduling worth while. Note that use_thunk calls
7910 assemble_start_function and assemble_end_function. */
7911 insn
= get_insns ();
7912 shorten_branches (insn
);
7913 final_start_function (insn
, file
, 1);
7914 final (insn
, file
, 1, 0);
7915 final_end_function ();
7918 /* Debugging support. */
7922 /* Count the number of sdb related labels are generated (to find block
7923 start and end boundaries). */
7925 int sdb_label_count
= 0;
7927 /* Next label # for each statement. */
7929 static int sym_lineno
= 0;
7931 /* Count the number of .file directives, so that .loc is up to date. */
7933 static int num_source_filenames
= 0;
7935 /* Name of the file containing the current function. */
7937 static const char *current_function_file
= "";
7939 /* Offsets to alpha virtual arg/local debugging pointers. */
7941 long alpha_arg_offset
;
7942 long alpha_auto_offset
;
7944 /* Emit a new filename to a stream. */
7947 alpha_output_filename (stream
, name
)
7951 static int first_time
= TRUE
;
7952 char ltext_label_name
[100];
7957 ++num_source_filenames
;
7958 current_function_file
= name
;
7959 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7960 output_quoted_string (stream
, name
);
7961 fprintf (stream
, "\n");
7962 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
7963 fprintf (stream
, "\t#@stabs\n");
7966 else if (write_symbols
== DBX_DEBUG
)
7968 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
7969 fprintf (stream
, "%s", ASM_STABS_OP
);
7970 output_quoted_string (stream
, name
);
7971 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
7974 else if (name
!= current_function_file
7975 && strcmp (name
, current_function_file
) != 0)
7977 if (inside_function
&& ! TARGET_GAS
)
7978 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
7981 ++num_source_filenames
;
7982 current_function_file
= name
;
7983 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7986 output_quoted_string (stream
, name
);
7987 fprintf (stream
, "\n");
7991 /* Emit a linenumber to a stream. */
7994 alpha_output_lineno (stream
, line
)
7998 if (write_symbols
== DBX_DEBUG
)
8000 /* mips-tfile doesn't understand .stabd directives. */
8002 fprintf (stream
, "$LM%d:\n%s%d,0,%d,$LM%d\n",
8003 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
8006 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
8009 /* Structure to show the current status of registers and memory. */
8011 struct shadow_summary
8014 unsigned int i
: 31; /* Mask of int regs */
8015 unsigned int fp
: 31; /* Mask of fp regs */
8016 unsigned int mem
: 1; /* mem == imem | fpmem */
8020 static void summarize_insn
PARAMS ((rtx
, struct shadow_summary
*, int));
8021 static void alpha_handle_trap_shadows
PARAMS ((rtx
));
8023 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8024 to the summary structure. SET is nonzero if the insn is setting the
8025 object, otherwise zero. */
8028 summarize_insn (x
, sum
, set
)
8030 struct shadow_summary
*sum
;
8033 const char *format_ptr
;
8039 switch (GET_CODE (x
))
8041 /* ??? Note that this case would be incorrect if the Alpha had a
8042 ZERO_EXTRACT in SET_DEST. */
8044 summarize_insn (SET_SRC (x
), sum
, 0);
8045 summarize_insn (SET_DEST (x
), sum
, 1);
8049 summarize_insn (XEXP (x
, 0), sum
, 1);
8053 summarize_insn (XEXP (x
, 0), sum
, 0);
8057 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8058 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8062 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8063 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8067 summarize_insn (SUBREG_REG (x
), sum
, 0);
8072 int regno
= REGNO (x
);
8073 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8075 if (regno
== 31 || regno
== 63)
8081 sum
->defd
.i
|= mask
;
8083 sum
->defd
.fp
|= mask
;
8088 sum
->used
.i
|= mask
;
8090 sum
->used
.fp
|= mask
;
8101 /* Find the regs used in memory address computation: */
8102 summarize_insn (XEXP (x
, 0), sum
, 0);
8105 case CONST_INT
: case CONST_DOUBLE
:
8106 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8107 case SCRATCH
: case ASM_INPUT
:
8110 /* Handle common unary and binary ops for efficiency. */
8111 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8112 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8113 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8114 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8115 case NE
: case EQ
: case GE
: case GT
: case LE
:
8116 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8117 summarize_insn (XEXP (x
, 0), sum
, 0);
8118 summarize_insn (XEXP (x
, 1), sum
, 0);
8121 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8122 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8123 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8124 case SQRT
: case FFS
:
8125 summarize_insn (XEXP (x
, 0), sum
, 0);
8129 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8130 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8131 switch (format_ptr
[i
])
8134 summarize_insn (XEXP (x
, i
), sum
, 0);
8138 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8139 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8151 /* Ensure a sufficient number of `trapb' insns are in the code when
8152 the user requests code with a trap precision of functions or
8155 In naive mode, when the user requests a trap-precision of
8156 "instruction", a trapb is needed after every instruction that may
8157 generate a trap. This ensures that the code is resumption safe but
8160 When optimizations are turned on, we delay issuing a trapb as long
8161 as possible. In this context, a trap shadow is the sequence of
8162 instructions that starts with a (potentially) trap generating
8163 instruction and extends to the next trapb or call_pal instruction
8164 (but GCC never generates call_pal by itself). We can delay (and
8165 therefore sometimes omit) a trapb subject to the following
8168 (a) On entry to the trap shadow, if any Alpha register or memory
8169 location contains a value that is used as an operand value by some
8170 instruction in the trap shadow (live on entry), then no instruction
8171 in the trap shadow may modify the register or memory location.
8173 (b) Within the trap shadow, the computation of the base register
8174 for a memory load or store instruction may not involve using the
8175 result of an instruction that might generate an UNPREDICTABLE
8178 (c) Within the trap shadow, no register may be used more than once
8179 as a destination register. (This is to make life easier for the
8182 (d) The trap shadow may not include any branch instructions. */
8185 alpha_handle_trap_shadows (insns
)
8188 struct shadow_summary shadow
;
8189 int trap_pending
, exception_nesting
;
8193 exception_nesting
= 0;
8196 shadow
.used
.mem
= 0;
8197 shadow
.defd
= shadow
.used
;
8199 for (i
= insns
; i
; i
= NEXT_INSN (i
))
8201 if (GET_CODE (i
) == NOTE
)
8203 switch (NOTE_LINE_NUMBER (i
))
8205 case NOTE_INSN_EH_REGION_BEG
:
8206 exception_nesting
++;
8211 case NOTE_INSN_EH_REGION_END
:
8212 exception_nesting
--;
8217 case NOTE_INSN_EPILOGUE_BEG
:
8218 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8223 else if (trap_pending
)
8225 if (alpha_tp
== ALPHA_TP_FUNC
)
8227 if (GET_CODE (i
) == JUMP_INSN
8228 && GET_CODE (PATTERN (i
)) == RETURN
)
8231 else if (alpha_tp
== ALPHA_TP_INSN
)
8235 struct shadow_summary sum
;
8240 sum
.defd
= sum
.used
;
8242 switch (GET_CODE (i
))
8245 /* Annoyingly, get_attr_trap will abort on these. */
8246 if (GET_CODE (PATTERN (i
)) == USE
8247 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8250 summarize_insn (PATTERN (i
), &sum
, 0);
8252 if ((sum
.defd
.i
& shadow
.defd
.i
)
8253 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8255 /* (c) would be violated */
8259 /* Combine shadow with summary of current insn: */
8260 shadow
.used
.i
|= sum
.used
.i
;
8261 shadow
.used
.fp
|= sum
.used
.fp
;
8262 shadow
.used
.mem
|= sum
.used
.mem
;
8263 shadow
.defd
.i
|= sum
.defd
.i
;
8264 shadow
.defd
.fp
|= sum
.defd
.fp
;
8265 shadow
.defd
.mem
|= sum
.defd
.mem
;
8267 if ((sum
.defd
.i
& shadow
.used
.i
)
8268 || (sum
.defd
.fp
& shadow
.used
.fp
)
8269 || (sum
.defd
.mem
& shadow
.used
.mem
))
8271 /* (a) would be violated (also takes care of (b)) */
8272 if (get_attr_trap (i
) == TRAP_YES
8273 && ((sum
.defd
.i
& sum
.used
.i
)
8274 || (sum
.defd
.fp
& sum
.used
.fp
)))
8293 n
= emit_insn_before (gen_trapb (), i
);
8294 PUT_MODE (n
, TImode
);
8295 PUT_MODE (i
, TImode
);
8299 shadow
.used
.mem
= 0;
8300 shadow
.defd
= shadow
.used
;
8305 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8306 && GET_CODE (i
) == INSN
8307 && GET_CODE (PATTERN (i
)) != USE
8308 && GET_CODE (PATTERN (i
)) != CLOBBER
8309 && get_attr_trap (i
) == TRAP_YES
)
8311 if (optimize
&& !trap_pending
)
8312 summarize_insn (PATTERN (i
), &shadow
, 0);
8318 /* Alpha can only issue instruction groups simultaneously if they are
8319 suitibly aligned. This is very processor-specific. */
8321 enum alphaev4_pipe
{
8328 enum alphaev5_pipe
{
8339 static enum alphaev4_pipe alphaev4_insn_pipe
PARAMS ((rtx
));
8340 static enum alphaev5_pipe alphaev5_insn_pipe
PARAMS ((rtx
));
8341 static rtx alphaev4_next_group
PARAMS ((rtx
, int *, int *));
8342 static rtx alphaev5_next_group
PARAMS ((rtx
, int *, int *));
8343 static rtx alphaev4_next_nop
PARAMS ((int *));
8344 static rtx alphaev5_next_nop
PARAMS ((int *));
8346 static void alpha_align_insns
8347 PARAMS ((rtx
, unsigned int, rtx (*)(rtx
, int *, int *), rtx (*)(int *)));
8349 static enum alphaev4_pipe
8350 alphaev4_insn_pipe (insn
)
8353 if (recog_memoized (insn
) < 0)
8355 if (get_attr_length (insn
) != 4)
8358 switch (get_attr_type (insn
))
8392 static enum alphaev5_pipe
8393 alphaev5_insn_pipe (insn
)
8396 if (recog_memoized (insn
) < 0)
8398 if (get_attr_length (insn
) != 4)
8401 switch (get_attr_type (insn
))
8442 /* IN_USE is a mask of the slots currently filled within the insn group.
8443 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8444 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8446 LEN is, of course, the length of the group in bytes. */
8449 alphaev4_next_group (insn
, pin_use
, plen
)
8451 int *pin_use
, *plen
;
8458 || GET_CODE (PATTERN (insn
)) == CLOBBER
8459 || GET_CODE (PATTERN (insn
)) == USE
)
8464 enum alphaev4_pipe pipe
;
8466 pipe
= alphaev4_insn_pipe (insn
);
8470 /* Force complex instructions to start new groups. */
8474 /* If this is a completely unrecognized insn, its an asm.
8475 We don't know how long it is, so record length as -1 to
8476 signal a needed realignment. */
8477 if (recog_memoized (insn
) < 0)
8480 len
= get_attr_length (insn
);
8484 if (in_use
& EV4_IB0
)
8486 if (in_use
& EV4_IB1
)
8491 in_use
|= EV4_IB0
| EV4_IBX
;
8495 if (in_use
& EV4_IB0
)
8497 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8505 if (in_use
& EV4_IB1
)
8515 /* Haifa doesn't do well scheduling branches. */
8516 if (GET_CODE (insn
) == JUMP_INSN
)
8520 insn
= next_nonnote_insn (insn
);
8522 if (!insn
|| ! INSN_P (insn
))
8525 /* Let Haifa tell us where it thinks insn group boundaries are. */
8526 if (GET_MODE (insn
) == TImode
)
8529 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8534 insn
= next_nonnote_insn (insn
);
8542 /* IN_USE is a mask of the slots currently filled within the insn group.
8543 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8544 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8546 LEN is, of course, the length of the group in bytes. */
8549 alphaev5_next_group (insn
, pin_use
, plen
)
8551 int *pin_use
, *plen
;
8558 || GET_CODE (PATTERN (insn
)) == CLOBBER
8559 || GET_CODE (PATTERN (insn
)) == USE
)
8564 enum alphaev5_pipe pipe
;
8566 pipe
= alphaev5_insn_pipe (insn
);
8570 /* Force complex instructions to start new groups. */
8574 /* If this is a completely unrecognized insn, its an asm.
8575 We don't know how long it is, so record length as -1 to
8576 signal a needed realignment. */
8577 if (recog_memoized (insn
) < 0)
8580 len
= get_attr_length (insn
);
8583 /* ??? Most of the places below, we would like to abort, as
8584 it would indicate an error either in Haifa, or in the
8585 scheduling description. Unfortunately, Haifa never
8586 schedules the last instruction of the BB, so we don't
8587 have an accurate TI bit to go off. */
8589 if (in_use
& EV5_E0
)
8591 if (in_use
& EV5_E1
)
8596 in_use
|= EV5_E0
| EV5_E01
;
8600 if (in_use
& EV5_E0
)
8602 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
8610 if (in_use
& EV5_E1
)
8616 if (in_use
& EV5_FA
)
8618 if (in_use
& EV5_FM
)
8623 in_use
|= EV5_FA
| EV5_FAM
;
8627 if (in_use
& EV5_FA
)
8633 if (in_use
& EV5_FM
)
8646 /* Haifa doesn't do well scheduling branches. */
8647 /* ??? If this is predicted not-taken, slotting continues, except
8648 that no more IBR, FBR, or JSR insns may be slotted. */
8649 if (GET_CODE (insn
) == JUMP_INSN
)
8653 insn
= next_nonnote_insn (insn
);
8655 if (!insn
|| ! INSN_P (insn
))
8658 /* Let Haifa tell us where it thinks insn group boundaries are. */
8659 if (GET_MODE (insn
) == TImode
)
8662 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8667 insn
= next_nonnote_insn (insn
);
8676 alphaev4_next_nop (pin_use
)
8679 int in_use
= *pin_use
;
8682 if (!(in_use
& EV4_IB0
))
8687 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
8692 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
8705 alphaev5_next_nop (pin_use
)
8708 int in_use
= *pin_use
;
8711 if (!(in_use
& EV5_E1
))
8716 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
8721 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
8733 /* The instruction group alignment main loop. */
8736 alpha_align_insns (insns
, max_align
, next_group
, next_nop
)
8738 unsigned int max_align
;
8739 rtx (*next_group
) PARAMS ((rtx
, int *, int *));
8740 rtx (*next_nop
) PARAMS ((int *));
8742 /* ALIGN is the known alignment for the insn group. */
8744 /* OFS is the offset of the current insn in the insn group. */
8746 int prev_in_use
, in_use
, len
;
8749 /* Let shorten branches care for assigning alignments to code labels. */
8750 shorten_branches (insns
);
8752 if (align_functions
< 4)
8754 else if ((unsigned int) align_functions
< max_align
)
8755 align
= align_functions
;
8759 ofs
= prev_in_use
= 0;
8761 if (GET_CODE (i
) == NOTE
)
8762 i
= next_nonnote_insn (i
);
8766 next
= (*next_group
) (i
, &in_use
, &len
);
8768 /* When we see a label, resync alignment etc. */
8769 if (GET_CODE (i
) == CODE_LABEL
)
8771 unsigned int new_align
= 1 << label_to_alignment (i
);
8773 if (new_align
>= align
)
8775 align
= new_align
< max_align
? new_align
: max_align
;
8779 else if (ofs
& (new_align
-1))
8780 ofs
= (ofs
| (new_align
-1)) + 1;
8785 /* Handle complex instructions special. */
8786 else if (in_use
== 0)
8788 /* Asms will have length < 0. This is a signal that we have
8789 lost alignment knowledge. Assume, however, that the asm
8790 will not mis-align instructions. */
8799 /* If the known alignment is smaller than the recognized insn group,
8800 realign the output. */
8801 else if ((int) align
< len
)
8803 unsigned int new_log_align
= len
> 8 ? 4 : 3;
8806 where
= prev
= prev_nonnote_insn (i
);
8807 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
8810 /* Can't realign between a call and its gp reload. */
8811 if (! (TARGET_EXPLICIT_RELOCS
8812 && prev
&& GET_CODE (prev
) == CALL_INSN
))
8814 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
8815 align
= 1 << new_log_align
;
8820 /* If the group won't fit in the same INT16 as the previous,
8821 we need to add padding to keep the group together. Rather
8822 than simply leaving the insn filling to the assembler, we
8823 can make use of the knowledge of what sorts of instructions
8824 were issued in the previous group to make sure that all of
8825 the added nops are really free. */
8826 else if (ofs
+ len
> (int) align
)
8828 int nop_count
= (align
- ofs
) / 4;
8831 /* Insert nops before labels, branches, and calls to truely merge
8832 the execution of the nops with the previous instruction group. */
8833 where
= prev_nonnote_insn (i
);
8836 if (GET_CODE (where
) == CODE_LABEL
)
8838 rtx where2
= prev_nonnote_insn (where
);
8839 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
8842 else if (GET_CODE (where
) == INSN
)
8849 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
8850 while (--nop_count
);
8854 ofs
= (ofs
+ len
) & (align
- 1);
8855 prev_in_use
= in_use
;
8860 /* Machine dependent reorg pass. */
8866 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
8867 alpha_handle_trap_shadows (insns
);
8869 /* Due to the number of extra trapb insns, don't bother fixing up
8870 alignment when trap precision is instruction. Moreover, we can
8871 only do our job when sched2 is run. */
8872 if (optimize
&& !optimize_size
8873 && alpha_tp
!= ALPHA_TP_INSN
8874 && flag_schedule_insns_after_reload
)
8876 if (alpha_cpu
== PROCESSOR_EV4
)
8877 alpha_align_insns (insns
, 8, alphaev4_next_group
, alphaev4_next_nop
);
8878 else if (alpha_cpu
== PROCESSOR_EV5
)
8879 alpha_align_insns (insns
, 16, alphaev5_next_group
, alphaev5_next_nop
);
8883 /* Check a floating-point value for validity for a particular machine mode. */
8885 static const char * const float_strings
[] =
8887 /* These are for FLOAT_VAX. */
8888 "1.70141173319264430e+38", /* 2^127 (2^24 - 1) / 2^24 */
8889 "-1.70141173319264430e+38",
8890 "2.93873587705571877e-39", /* 2^-128 */
8891 "-2.93873587705571877e-39",
8892 /* These are for the default broken IEEE mode, which traps
8893 on infinity or denormal numbers. */
8894 "3.402823466385288598117e+38", /* 2^128 (1 - 2^-24) */
8895 "-3.402823466385288598117e+38",
8896 "1.1754943508222875079687e-38", /* 2^-126 */
8897 "-1.1754943508222875079687e-38",
8900 static REAL_VALUE_TYPE float_values
[8];
8901 static int inited_float_values
= 0;
8904 check_float_value (mode
, d
, overflow
)
8905 enum machine_mode mode
;
8907 int overflow ATTRIBUTE_UNUSED
;
8910 if (TARGET_IEEE
|| TARGET_IEEE_CONFORMANT
|| TARGET_IEEE_WITH_INEXACT
)
8913 if (inited_float_values
== 0)
8916 for (i
= 0; i
< 8; i
++)
8917 float_values
[i
] = REAL_VALUE_ATOF (float_strings
[i
], DFmode
);
8919 inited_float_values
= 1;
8925 REAL_VALUE_TYPE
*fvptr
;
8927 if (TARGET_FLOAT_VAX
)
8928 fvptr
= &float_values
[0];
8930 fvptr
= &float_values
[4];
8932 memcpy (&r
, d
, sizeof (REAL_VALUE_TYPE
));
8933 if (REAL_VALUES_LESS (fvptr
[0], r
))
8935 memcpy (d
, &fvptr
[0], sizeof (REAL_VALUE_TYPE
));
8938 else if (REAL_VALUES_LESS (r
, fvptr
[1]))
8940 memcpy (d
, &fvptr
[1], sizeof (REAL_VALUE_TYPE
));
8943 else if (REAL_VALUES_LESS (dconst0
, r
)
8944 && REAL_VALUES_LESS (r
, fvptr
[2]))
8946 memcpy (d
, &dconst0
, sizeof (REAL_VALUE_TYPE
));
8949 else if (REAL_VALUES_LESS (r
, dconst0
)
8950 && REAL_VALUES_LESS (fvptr
[3], r
))
8952 memcpy (d
, &dconst0
, sizeof (REAL_VALUE_TYPE
));
8960 #ifdef OBJECT_FORMAT_ELF
8962 /* Switch to the section to which we should output X. The only thing
8963 special we do here is to honor small data. */
8966 alpha_elf_select_rtx_section (mode
, x
, align
)
8967 enum machine_mode mode
;
8969 unsigned HOST_WIDE_INT align
;
8971 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
8972 /* ??? Consider using mergable sdata sections. */
8975 default_elf_select_rtx_section (mode
, x
, align
);
8978 #endif /* OBJECT_FORMAT_ELF */
8980 #if TARGET_ABI_OPEN_VMS
8982 /* Return the VMS argument type corresponding to MODE. */
8985 alpha_arg_type (mode
)
8986 enum machine_mode mode
;
8991 return TARGET_FLOAT_VAX
? FF
: FS
;
8993 return TARGET_FLOAT_VAX
? FD
: FT
;
8999 /* Return an rtx for an integer representing the VMS Argument Information
9003 alpha_arg_info_reg_val (cum
)
9004 CUMULATIVE_ARGS cum
;
9006 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
9009 for (i
= 0; i
< 6; i
++)
9010 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
9012 return GEN_INT (regval
);
9015 /* Protect alpha_links from garbage collection. */
9018 mark_alpha_links_node (node
, data
)
9019 splay_tree_node node
;
9020 void *data ATTRIBUTE_UNUSED
;
9022 struct alpha_links
*links
= (struct alpha_links
*) node
->value
;
9023 ggc_mark_rtx (links
->linkage
);
9028 mark_alpha_links (ptr
)
9031 splay_tree tree
= *(splay_tree
*) ptr
;
9032 splay_tree_foreach (tree
, mark_alpha_links_node
, NULL
);
9035 /* Make (or fake) .linkage entry for function call.
9037 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9039 Return an SYMBOL_REF rtx for the linkage. */
9042 alpha_need_linkage (name
, is_local
)
9046 splay_tree_node node
;
9047 struct alpha_links
*al
;
9048 struct alpha_funcs
*cfaf
;
9055 alpha_funcs_tree
= splay_tree_new
9056 ((splay_tree_compare_fn
) splay_tree_compare_pointers
,
9057 (splay_tree_delete_key_fn
) free
,
9058 (splay_tree_delete_key_fn
) free
);
9060 cfaf
= (struct alpha_funcs
*) xmalloc (sizeof (struct alpha_funcs
));
9063 cfaf
->num
= ++alpha_funcs_num
;
9065 splay_tree_insert (alpha_funcs_tree
,
9066 (splay_tree_key
) current_function_decl
,
9067 (splay_tree_value
) cfaf
);
9071 if (alpha_links_tree
)
9073 /* Is this name already defined? */
9075 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9078 al
= (struct alpha_links
*) node
->value
;
9081 /* Defined here but external assumed. */
9082 if (al
->lkind
== KIND_EXTERN
)
9083 al
->lkind
= KIND_LOCAL
;
9087 /* Used here but unused assumed. */
9088 if (al
->lkind
== KIND_UNUSED
)
9089 al
->lkind
= KIND_LOCAL
;
9096 alpha_links_tree
= splay_tree_new
9097 ((splay_tree_compare_fn
) strcmp
,
9098 (splay_tree_delete_key_fn
) free
,
9099 (splay_tree_delete_key_fn
) free
);
9101 ggc_add_root (&alpha_links_tree
, 1, 1, mark_alpha_links
);
9104 al
= (struct alpha_links
*) xmalloc (sizeof (struct alpha_links
));
9105 name
= xstrdup (name
);
9107 /* Assume external if no definition. */
9108 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9110 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9111 get_identifier (name
);
9113 /* Construct a SYMBOL_REF for us to call. */
9115 size_t name_len
= strlen (name
);
9116 char *linksym
= alloca (name_len
+ 6);
9118 memcpy (linksym
+ 1, name
, name_len
);
9119 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
9120 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
9121 ggc_alloc_string (linksym
, name_len
+ 5));
9124 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
9125 (splay_tree_value
) al
);
9131 alpha_use_linkage (linkage
, cfundecl
, lflag
, rflag
)
9137 splay_tree_node cfunnode
;
9138 struct alpha_funcs
*cfaf
;
9139 struct alpha_links
*al
;
9140 const char *name
= XSTR (linkage
, 0);
9142 cfaf
= (struct alpha_funcs
*) 0;
9143 al
= (struct alpha_links
*) 0;
9145 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
9146 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
9150 splay_tree_node lnode
;
9152 /* Is this name already defined? */
9154 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
9156 al
= (struct alpha_links
*) lnode
->value
;
9160 cfaf
->links
= splay_tree_new
9161 ((splay_tree_compare_fn
) strcmp
,
9162 (splay_tree_delete_key_fn
) free
,
9163 (splay_tree_delete_key_fn
) free
);
9164 ggc_add_root (&cfaf
->links
, 1, 1, mark_alpha_links
);
9173 splay_tree_node node
= 0;
9174 struct alpha_links
*anl
;
9179 name_len
= strlen (name
);
9181 al
= (struct alpha_links
*) xmalloc (sizeof (struct alpha_links
));
9182 al
->num
= cfaf
->num
;
9184 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9187 anl
= (struct alpha_links
*) node
->value
;
9188 al
->lkind
= anl
->lkind
;
9191 sprintf (buf
, "$%d..%s..lk", cfaf
->num
, name
);
9192 buflen
= strlen (buf
);
9193 linksym
= alloca (buflen
+ 1);
9194 memcpy (linksym
, buf
, buflen
+ 1);
9196 al
->linkage
= gen_rtx_SYMBOL_REF
9197 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
9199 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
9200 (splay_tree_value
) al
);
9204 al
->rkind
= KIND_CODEADDR
;
9206 al
->rkind
= KIND_LINKAGE
;
9209 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
9215 alpha_write_one_linkage (node
, data
)
9216 splay_tree_node node
;
9219 const char *const name
= (const char *) node
->key
;
9220 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
9221 FILE *stream
= (FILE *) data
;
9223 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
9224 if (link
->rkind
== KIND_CODEADDR
)
9226 if (link
->lkind
== KIND_LOCAL
)
9228 /* Local and used */
9229 fprintf (stream
, "\t.quad %s..en\n", name
);
9233 /* External and used, request code address. */
9234 fprintf (stream
, "\t.code_address %s\n", name
);
9239 if (link
->lkind
== KIND_LOCAL
)
9241 /* Local and used, build linkage pair. */
9242 fprintf (stream
, "\t.quad %s..en\n", name
);
9243 fprintf (stream
, "\t.quad %s\n", name
);
9247 /* External and used, request linkage pair. */
9248 fprintf (stream
, "\t.linkage %s\n", name
);
9256 alpha_write_linkage (stream
, funname
, fundecl
)
9258 const char *funname
;
9261 splay_tree_node node
;
9262 struct alpha_funcs
*func
;
9265 fprintf (stream
, "\t.align 3\n");
9266 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
9267 func
= (struct alpha_funcs
*) node
->value
;
9269 fputs ("\t.name ", stream
);
9270 assemble_name (stream
, funname
);
9271 fputs ("..na\n", stream
);
9272 ASM_OUTPUT_LABEL (stream
, funname
);
9273 fprintf (stream
, "\t.pdesc ");
9274 assemble_name (stream
, funname
);
9275 fprintf (stream
, "..en,%s\n",
9276 alpha_procedure_type
== PT_STACK
? "stack"
9277 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
9281 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
9282 /* splay_tree_delete (func->links); */
9286 /* Given a decl, a section name, and whether the decl initializer
9287 has relocs, choose attributes for the section. */
9289 #define SECTION_VMS_OVERLAY SECTION_FORGET
9290 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9291 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9294 vms_section_type_flags (decl
, name
, reloc
)
9299 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9301 if (decl
&& DECL_ATTRIBUTES (decl
)
9302 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
9303 flags
|= SECTION_VMS_OVERLAY
;
9304 if (decl
&& DECL_ATTRIBUTES (decl
)
9305 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
9306 flags
|= SECTION_VMS_GLOBAL
;
9307 if (decl
&& DECL_ATTRIBUTES (decl
)
9308 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
9309 flags
|= SECTION_VMS_INITIALIZE
;
9314 /* Switch to an arbitrary section NAME with attributes as specified
9315 by FLAGS. ALIGN specifies any known alignment requirements for
9316 the section; 0 if the default should be used. */
9319 vms_asm_named_section (name
, flags
)
9323 fputc ('\n', asm_out_file
);
9324 fprintf (asm_out_file
, ".section\t%s", name
);
9326 if (flags
& SECTION_VMS_OVERLAY
)
9327 fprintf (asm_out_file
, ",OVR");
9328 if (flags
& SECTION_VMS_GLOBAL
)
9329 fprintf (asm_out_file
, ",GBL");
9330 if (flags
& SECTION_VMS_INITIALIZE
)
9331 fprintf (asm_out_file
, ",NOMOD");
9332 if (flags
& SECTION_DEBUG
)
9333 fprintf (asm_out_file
, ",NOWRT");
9335 fputc ('\n', asm_out_file
);
9338 /* Record an element in the table of global constructors. SYMBOL is
9339 a SYMBOL_REF of the function to be called; PRIORITY is a number
9340 between 0 and MAX_INIT_PRIORITY.
9342 Differs from default_ctors_section_asm_out_constructor in that the
9343 width of the .ctors entry is always 64 bits, rather than the 32 bits
9344 used by a normal pointer. */
9347 vms_asm_out_constructor (symbol
, priority
)
9349 int priority ATTRIBUTE_UNUSED
;
9352 assemble_align (BITS_PER_WORD
);
9353 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9357 vms_asm_out_destructor (symbol
, priority
)
9359 int priority ATTRIBUTE_UNUSED
;
9362 assemble_align (BITS_PER_WORD
);
9363 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9368 alpha_need_linkage (name
, is_local
)
9369 const char *name ATTRIBUTE_UNUSED
;
9370 int is_local ATTRIBUTE_UNUSED
;
9376 alpha_use_linkage (linkage
, cfundecl
, lflag
, rflag
)
9377 rtx linkage ATTRIBUTE_UNUSED
;
9378 tree cfundecl ATTRIBUTE_UNUSED
;
9379 int lflag ATTRIBUTE_UNUSED
;
9380 int rflag ATTRIBUTE_UNUSED
;
9385 #endif /* TARGET_ABI_OPEN_VMS */
9387 #if TARGET_ABI_UNICOSMK
9389 static void unicosmk_output_module_name
PARAMS ((FILE *));
9390 static void unicosmk_output_default_externs
PARAMS ((FILE *));
9391 static void unicosmk_output_dex
PARAMS ((FILE *));
9392 static void unicosmk_output_externs
PARAMS ((FILE *));
9393 static void unicosmk_output_addr_vec
PARAMS ((FILE *, rtx
));
9394 static const char *unicosmk_ssib_name
PARAMS ((void));
9395 static int unicosmk_special_name
PARAMS ((const char *));
9397 /* Define the offset between two registers, one to be eliminated, and the
9398 other its replacement, at the start of a routine. */
9401 unicosmk_initial_elimination_offset (from
, to
)
9407 fixed_size
= alpha_sa_size();
9408 if (fixed_size
!= 0)
9411 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9413 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9415 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9416 return (ALPHA_ROUND (current_function_outgoing_args_size
)
9417 + ALPHA_ROUND (get_frame_size()));
9418 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9419 return (ALPHA_ROUND (fixed_size
)
9420 + ALPHA_ROUND (get_frame_size()
9421 + current_function_outgoing_args_size
));
9426 /* Output the module name for .ident and .end directives. We have to strip
9427 directories and add make sure that the module name starts with a letter
9431 unicosmk_output_module_name (file
)
9436 /* Strip directories. */
9438 name
= strrchr (main_input_filename
, '/');
9442 name
= main_input_filename
;
9444 /* CAM only accepts module names that start with a letter or '$'. We
9445 prefix the module name with a '$' if necessary. */
9447 if (!ISALPHA (*name
))
9449 output_clean_symbol_name (file
, name
);
9452 /* Output text that to appear at the beginning of an assembler file. */
9455 unicosmk_asm_file_start (file
)
9460 fputs ("\t.ident\t", file
);
9461 unicosmk_output_module_name (file
);
9462 fputs ("\n\n", file
);
9464 /* The Unicos/Mk assembler uses different register names. Instead of trying
9465 to support them, we simply use micro definitions. */
9467 /* CAM has different register names: rN for the integer register N and fN
9468 for the floating-point register N. Instead of trying to use these in
9469 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9472 for (i
= 0; i
< 32; ++i
)
9473 fprintf (file
, "$%d <- r%d\n", i
, i
);
9475 for (i
= 0; i
< 32; ++i
)
9476 fprintf (file
, "$f%d <- f%d\n", i
, i
);
9480 /* The .align directive fill unused space with zeroes which does not work
9481 in code sections. We define the macro 'gcc@code@align' which uses nops
9482 instead. Note that it assumes that code sections always have the
9483 biggest possible alignment since . refers to the current offset from
9484 the beginning of the section. */
9486 fputs ("\t.macro gcc@code@align n\n", file
);
9487 fputs ("gcc@n@bytes = 1 << n\n", file
);
9488 fputs ("gcc@here = . % gcc@n@bytes\n", file
);
9489 fputs ("\t.if ne, gcc@here, 0\n", file
);
9490 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", file
);
9491 fputs ("\tbis r31,r31,r31\n", file
);
9492 fputs ("\t.endr\n", file
);
9493 fputs ("\t.endif\n", file
);
9494 fputs ("\t.endm gcc@code@align\n\n", file
);
9496 /* Output extern declarations which should always be visible. */
9497 unicosmk_output_default_externs (file
);
9499 /* Open a dummy section. We always need to be inside a section for the
9500 section-switching code to work correctly.
9501 ??? This should be a module id or something like that. I still have to
9502 figure out what the rules for those are. */
9503 fputs ("\n\t.psect\t$SG00000,data\n", file
);
9506 /* Output text to appear at the end of an assembler file. This includes all
9507 pending extern declarations and DEX expressions. */
9510 unicosmk_asm_file_end (file
)
9513 fputs ("\t.endp\n\n", file
);
9515 /* Output all pending externs. */
9517 unicosmk_output_externs (file
);
9519 /* Output dex definitions used for functions whose names conflict with
9522 unicosmk_output_dex (file
);
9524 fputs ("\t.end\t", file
);
9525 unicosmk_output_module_name (file
);
9529 /* Output the definition of a common variable. */
9532 unicosmk_output_common (file
, name
, size
, align
)
9539 printf ("T3E__: common %s\n", name
);
9542 fputs("\t.endp\n\n\t.psect ", file
);
9543 assemble_name(file
, name
);
9544 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
9545 fprintf(file
, "\t.byte\t0:%d\n", size
);
9547 /* Mark the symbol as defined in this module. */
9548 name_tree
= get_identifier (name
);
9549 TREE_ASM_WRITTEN (name_tree
) = 1;
9552 #define SECTION_PUBLIC SECTION_MACH_DEP
9553 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9554 static int current_section_align
;
9557 unicosmk_section_type_flags (decl
, name
, reloc
)
9560 int reloc ATTRIBUTE_UNUSED
;
9562 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9567 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9569 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9570 if (align_functions_log
> current_section_align
)
9571 current_section_align
= align_functions_log
;
9573 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
9574 flags
|= SECTION_MAIN
;
9577 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
9579 if (TREE_PUBLIC (decl
))
9580 flags
|= SECTION_PUBLIC
;
9585 /* Generate a section name for decl and associate it with the
9589 unicosmk_unique_section (decl
, reloc
)
9591 int reloc ATTRIBUTE_UNUSED
;
9599 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9600 name
= alpha_strip_name_encoding (name
);
9601 len
= strlen (name
);
9603 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9607 /* It is essential that we prefix the section name here because
9608 otherwise the section names generated for constructors and
9609 destructors confuse collect2. */
9611 string
= alloca (len
+ 6);
9612 sprintf (string
, "code@%s", name
);
9613 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9615 else if (TREE_PUBLIC (decl
))
9616 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
9621 string
= alloca (len
+ 6);
9622 sprintf (string
, "data@%s", name
);
9623 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9627 /* Switch to an arbitrary section NAME with attributes as specified
9628 by FLAGS. ALIGN specifies any known alignment requirements for
9629 the section; 0 if the default should be used. */
9632 unicosmk_asm_named_section (name
, flags
)
9638 /* Close the previous section. */
9640 fputs ("\t.endp\n\n", asm_out_file
);
9642 /* Find out what kind of section we are opening. */
9644 if (flags
& SECTION_MAIN
)
9645 fputs ("\t.start\tmain\n", asm_out_file
);
9647 if (flags
& SECTION_CODE
)
9649 else if (flags
& SECTION_PUBLIC
)
9654 if (current_section_align
!= 0)
9655 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
9656 current_section_align
, kind
);
9658 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
9662 unicosmk_insert_attributes (decl
, attr_ptr
)
9664 tree
*attr_ptr ATTRIBUTE_UNUSED
;
9667 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
9668 unicosmk_unique_section (decl
, 0);
9671 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9672 in code sections because .align fill unused space with zeroes. */
9675 unicosmk_output_align (file
, align
)
9679 if (inside_function
)
9680 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
9682 fprintf (file
, "\t.align\t%d\n", align
);
9685 /* Add a case vector to the current function's list of deferred case
9686 vectors. Case vectors have to be put into a separate section because CAM
9687 does not allow data definitions in code sections. */
9690 unicosmk_defer_case_vector (lab
, vec
)
9694 struct machine_function
*machine
= cfun
->machine
;
9696 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9697 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
9698 machine
->addr_list
);
9701 /* Output a case vector. */
9704 unicosmk_output_addr_vec (file
, vec
)
9708 rtx lab
= XEXP (vec
, 0);
9709 rtx body
= XEXP (vec
, 1);
9710 int vlen
= XVECLEN (body
, 0);
9713 ASM_OUTPUT_INTERNAL_LABEL (file
, "L", CODE_LABEL_NUMBER (lab
));
9715 for (idx
= 0; idx
< vlen
; idx
++)
9717 ASM_OUTPUT_ADDR_VEC_ELT
9718 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9722 /* Output current function's deferred case vectors. */
9725 unicosmk_output_deferred_case_vectors (file
)
9728 struct machine_function
*machine
= cfun
->machine
;
9731 if (machine
->addr_list
== NULL_RTX
)
9735 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
9736 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
9739 /* Set up the dynamic subprogram information block (DSIB) and update the
9740 frame pointer register ($15) for subroutines which have a frame. If the
9741 subroutine doesn't have a frame, simply increment $15. */
9744 unicosmk_gen_dsib (imaskP
)
9745 unsigned long * imaskP
;
9747 if (alpha_procedure_type
== PT_STACK
)
9749 const char *ssib_name
;
9752 /* Allocate 64 bytes for the DSIB. */
9754 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9756 emit_insn (gen_blockage ());
9758 /* Save the return address. */
9760 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
9761 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9762 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
9763 (*imaskP
) &= ~(1L << REG_RA
);
9765 /* Save the old frame pointer. */
9767 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
9768 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9769 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
9770 (*imaskP
) &= ~(1L << HARD_FRAME_POINTER_REGNUM
);
9772 emit_insn (gen_blockage ());
9774 /* Store the SSIB pointer. */
9776 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
9777 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
9778 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9780 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
9781 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
9782 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
9784 /* Save the CIW index. */
9786 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
9787 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9788 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
9790 emit_insn (gen_blockage ());
9792 /* Set the new frame pointer. */
9794 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9795 stack_pointer_rtx
, GEN_INT (64))));
9800 /* Increment the frame pointer register to indicate that we do not
9803 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9804 hard_frame_pointer_rtx
, GEN_INT (1))));
9808 #define SSIB_PREFIX "__SSIB_"
9809 #define SSIB_PREFIX_LEN 7
9811 /* Generate the name of the SSIB section for the current function. */
9814 unicosmk_ssib_name ()
9816 /* This is ok since CAM won't be able to deal with names longer than that
9819 static char name
[256];
9825 x
= DECL_RTL (cfun
->decl
);
9826 if (GET_CODE (x
) != MEM
)
9829 if (GET_CODE (x
) != SYMBOL_REF
)
9831 fnname
= alpha_strip_name_encoding (XSTR (x
, 0));
9833 len
= strlen (fnname
);
9834 if (len
+ SSIB_PREFIX_LEN
> 255)
9835 len
= 255 - SSIB_PREFIX_LEN
;
9837 strcpy (name
, SSIB_PREFIX
);
9838 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
9839 name
[len
+ SSIB_PREFIX_LEN
] = 0;
9844 /* Output the static subroutine information block for the current
9848 unicosmk_output_ssib (file
, fnname
)
9856 struct machine_function
*machine
= cfun
->machine
;
9859 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
9860 unicosmk_ssib_name ());
9862 /* Some required stuff and the function name length. */
9864 len
= strlen (fnname
);
9865 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
9868 ??? We don't do that yet. */
9870 fputs ("\t.quad\t0\n", file
);
9872 /* Function address. */
9874 fputs ("\t.quad\t", file
);
9875 assemble_name (file
, fnname
);
9878 fputs ("\t.quad\t0\n", file
);
9879 fputs ("\t.quad\t0\n", file
);
9882 ??? We do it the same way Cray CC does it but this could be
9885 for( i
= 0; i
< len
; i
++ )
9886 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
9887 if( (len
% 8) == 0 )
9888 fputs ("\t.quad\t0\n", file
);
9890 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
9892 /* All call information words used in the function. */
9894 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
9897 fprintf (file
, "\t.quad\t");
9898 #if HOST_BITS_PER_WIDE_INT == 32
9899 fprintf (file
, HOST_WIDE_INT_PRINT_DOUBLE_HEX
,
9900 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
9902 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (ciw
));
9904 fprintf (file
, "\n");
9908 /* Add a call information word (CIW) to the list of the current function's
9909 CIWs and return its index.
9911 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9914 unicosmk_add_call_info_word (x
)
9918 struct machine_function
*machine
= cfun
->machine
;
9920 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
9921 if (machine
->first_ciw
== NULL_RTX
)
9922 machine
->first_ciw
= node
;
9924 XEXP (machine
->last_ciw
, 1) = node
;
9926 machine
->last_ciw
= node
;
9927 ++machine
->ciw_count
;
9929 return GEN_INT (machine
->ciw_count
9930 + strlen (current_function_name
)/8 + 5);
9933 static char unicosmk_section_buf
[100];
9936 unicosmk_text_section ()
9938 static int count
= 0;
9939 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9941 return unicosmk_section_buf
;
9945 unicosmk_data_section ()
9947 static int count
= 1;
9948 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9950 return unicosmk_section_buf
;
9953 /* The Cray assembler doesn't accept extern declarations for symbols which
9954 are defined in the same file. We have to keep track of all global
9955 symbols which are referenced and/or defined in a source file and output
9956 extern declarations for those which are referenced but not defined at
9959 /* List of identifiers for which an extern declaration might have to be
9962 struct unicosmk_extern_list
9964 struct unicosmk_extern_list
*next
;
9968 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
9970 /* Output extern declarations which are required for every asm file. */
9973 unicosmk_output_default_externs (file
)
9976 static const char *const externs
[] =
9977 { "__T3E_MISMATCH" };
9982 n
= ARRAY_SIZE (externs
);
9984 for (i
= 0; i
< n
; i
++)
9985 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
9988 /* Output extern declarations for global symbols which are have been
9989 referenced but not defined. */
9992 unicosmk_output_externs (file
)
9995 struct unicosmk_extern_list
*p
;
9996 const char *real_name
;
10000 len
= strlen (user_label_prefix
);
10001 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
10003 /* We have to strip the encoding and possibly remove user_label_prefix
10004 from the identifier in order to handle -fleading-underscore and
10005 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
10006 real_name
= alpha_strip_name_encoding (p
->name
);
10007 if (len
&& p
->name
[0] == '*'
10008 && !memcmp (real_name
, user_label_prefix
, len
))
10011 name_tree
= get_identifier (real_name
);
10012 if (! TREE_ASM_WRITTEN (name_tree
))
10014 TREE_ASM_WRITTEN (name_tree
) = 1;
10015 fputs ("\t.extern\t", file
);
10016 assemble_name (file
, p
->name
);
10022 /* Record an extern. */
10025 unicosmk_add_extern (name
)
10028 struct unicosmk_extern_list
*p
;
10030 p
= (struct unicosmk_extern_list
*)
10031 xmalloc (sizeof (struct unicosmk_extern_list
));
10032 p
->next
= unicosmk_extern_head
;
10034 unicosmk_extern_head
= p
;
10037 /* The Cray assembler generates incorrect code if identifiers which
10038 conflict with register names are used as instruction operands. We have
10039 to replace such identifiers with DEX expressions. */
10041 /* Structure to collect identifiers which have been replaced by DEX
10044 struct unicosmk_dex
{
10045 struct unicosmk_dex
*next
;
10049 /* List of identifiers which have been replaced by DEX expressions. The DEX
10050 number is determined by the position in the list. */
10052 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
10054 /* The number of elements in the DEX list. */
10056 static int unicosmk_dex_count
= 0;
10058 /* Check if NAME must be replaced by a DEX expression. */
10061 unicosmk_special_name (name
)
10064 if (name
[0] == '*')
10067 if (name
[0] == '$')
10070 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
10075 case '1': case '2':
10076 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
10079 return (name
[2] == '\0'
10080 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
10083 return (ISDIGIT (name
[1]) && name
[2] == '\0');
10087 /* Return the DEX number if X must be replaced by a DEX expression and 0
10091 unicosmk_need_dex (x
)
10094 struct unicosmk_dex
*dex
;
10098 if (GET_CODE (x
) != SYMBOL_REF
)
10102 if (! unicosmk_special_name (name
))
10105 i
= unicosmk_dex_count
;
10106 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10108 if (! strcmp (name
, dex
->name
))
10113 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
10115 dex
->next
= unicosmk_dex_list
;
10116 unicosmk_dex_list
= dex
;
10118 ++unicosmk_dex_count
;
10119 return unicosmk_dex_count
;
10122 /* Output the DEX definitions for this file. */
10125 unicosmk_output_dex (file
)
10128 struct unicosmk_dex
*dex
;
10131 if (unicosmk_dex_list
== NULL
)
10134 fprintf (file
, "\t.dexstart\n");
10136 i
= unicosmk_dex_count
;
10137 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10139 fprintf (file
, "\tDEX (%d) = ", i
);
10140 assemble_name (file
, dex
->name
);
10145 fprintf (file
, "\t.dexend\n");
10151 unicosmk_output_deferred_case_vectors (file
)
10152 FILE *file ATTRIBUTE_UNUSED
;
10156 unicosmk_gen_dsib (imaskP
)
10157 unsigned long * imaskP ATTRIBUTE_UNUSED
;
10161 unicosmk_output_ssib (file
, fnname
)
10162 FILE * file ATTRIBUTE_UNUSED
;
10163 const char * fnname ATTRIBUTE_UNUSED
;
10167 unicosmk_add_call_info_word (x
)
10168 rtx x ATTRIBUTE_UNUSED
;
10174 unicosmk_need_dex (x
)
10175 rtx x ATTRIBUTE_UNUSED
;
10180 #endif /* TARGET_ABI_UNICOSMK */
10182 #include "gt-alpha.h"