1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
45 #include "integrate.h"
48 #include "target-def.h"
51 /* Specify which cpu to schedule for. */
53 enum processor_type alpha_cpu
;
54 static const char * const alpha_cpu_name
[] =
59 /* Specify how accurate floating-point traps need to be. */
61 enum alpha_trap_precision alpha_tp
;
63 /* Specify the floating-point rounding mode. */
65 enum alpha_fp_rounding_mode alpha_fprm
;
67 /* Specify which things cause traps. */
69 enum alpha_fp_trap_mode alpha_fptm
;
71 /* Strings decoded into the above options. */
73 const char *alpha_cpu_string
; /* -mcpu= */
74 const char *alpha_tune_string
; /* -mtune= */
75 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
76 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
77 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
78 const char *alpha_mlat_string
; /* -mmemory-latency= */
80 /* Save information from a "cmpxx" operation until the branch or scc is
83 struct alpha_compare alpha_compare
;
85 /* Non-zero if inside of a function, because the Alpha asm can't
86 handle .files inside of functions. */
88 static int inside_function
= FALSE
;
90 /* The number of cycles of latency we should assume on memory reads. */
92 int alpha_memory_latency
= 3;
94 /* Whether the function needs the GP. */
96 static int alpha_function_needs_gp
;
98 /* The alias set for prologue/epilogue register save/restore. */
100 static int alpha_sr_alias_set
;
102 /* The assembler name of the current function. */
104 static const char *alpha_fnname
;
106 /* The next explicit relocation sequence number. */
107 int alpha_next_sequence_number
= 1;
109 /* The literal and gpdisp sequence numbers for this insn, as printed
110 by %# and %* respectively. */
111 int alpha_this_literal_sequence_number
;
112 int alpha_this_gpdisp_sequence_number
;
114 /* Declarations of static functions. */
115 static bool decl_in_text_section
117 static int some_small_symbolic_operand_1
118 PARAMS ((rtx
*, void *));
119 static int split_small_symbolic_operand_1
120 PARAMS ((rtx
*, void *));
121 static bool local_symbol_p
123 static void alpha_set_memflags_1
124 PARAMS ((rtx
, int, int, int));
125 static rtx alpha_emit_set_const_1
126 PARAMS ((rtx
, enum machine_mode
, HOST_WIDE_INT
, int));
127 static void alpha_expand_unaligned_load_words
128 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
129 static void alpha_expand_unaligned_store_words
130 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
131 static void alpha_sa_mask
132 PARAMS ((unsigned long *imaskP
, unsigned long *fmaskP
));
133 static int find_lo_sum
134 PARAMS ((rtx
*, void *));
135 static int alpha_does_function_need_gp
137 static int alpha_ra_ever_killed
139 static const char *get_trap_mode_suffix
141 static const char *get_round_mode_suffix
143 static rtx set_frame_related_p
145 static const char *alpha_lookup_xfloating_lib_func
146 PARAMS ((enum rtx_code
));
147 static int alpha_compute_xfloating_mode_arg
148 PARAMS ((enum rtx_code
, enum alpha_fp_rounding_mode
));
149 static void alpha_emit_xfloating_libcall
150 PARAMS ((const char *, rtx
, rtx
[], int, rtx
));
151 static rtx alpha_emit_xfloating_compare
152 PARAMS ((enum rtx_code
, rtx
, rtx
));
153 static void alpha_output_function_end_prologue
155 static int alpha_adjust_cost
156 PARAMS ((rtx
, rtx
, rtx
, int));
157 static int alpha_issue_rate
159 static int alpha_variable_issue
160 PARAMS ((FILE *, int, rtx
, int));
162 #if TARGET_ABI_UNICOSMK
163 static void alpha_init_machine_status
164 PARAMS ((struct function
*p
));
165 static void alpha_mark_machine_status
166 PARAMS ((struct function
*p
));
167 static void alpha_free_machine_status
168 PARAMS ((struct function
*p
));
171 static void unicosmk_output_deferred_case_vectors
PARAMS ((FILE *));
172 static void unicosmk_gen_dsib
PARAMS ((unsigned long *imaskP
));
173 static void unicosmk_output_ssib
PARAMS ((FILE *, const char *));
174 static int unicosmk_need_dex
PARAMS ((rtx
));
176 /* Get the number of args of a function in one of two ways. */
177 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
178 #define NUM_ARGS current_function_args_info.num_args
180 #define NUM_ARGS current_function_args_info
186 /* Initialize the GCC target structure. */
187 #if TARGET_ABI_OPEN_VMS
188 const struct attribute_spec vms_attribute_table
[];
189 static unsigned int vms_section_type_flags
PARAMS ((tree
, const char *, int));
190 static void vms_asm_named_section
PARAMS ((const char *, unsigned int));
191 static void vms_asm_out_constructor
PARAMS ((rtx
, int));
192 static void vms_asm_out_destructor
PARAMS ((rtx
, int));
193 # undef TARGET_ATTRIBUTE_TABLE
194 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
195 # undef TARGET_SECTION_TYPE_FLAGS
196 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
199 #if TARGET_ABI_UNICOSMK
200 static void unicosmk_asm_named_section
PARAMS ((const char *, unsigned int));
201 static void unicosmk_insert_attributes
PARAMS ((tree
, tree
*));
202 static unsigned int unicosmk_section_type_flags
PARAMS ((tree
, const char *,
204 # undef TARGET_INSERT_ATTRIBUTES
205 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
206 # undef TARGET_SECTION_TYPE_FLAGS
207 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
210 #undef TARGET_ASM_ALIGNED_HI_OP
211 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
212 #undef TARGET_ASM_ALIGNED_DI_OP
213 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
215 /* Default unaligned ops are provided for ELF systems. To get unaligned
216 data for non-ELF systems, we have to turn off auto alignment. */
217 #ifndef OBJECT_FORMAT_ELF
218 #undef TARGET_ASM_UNALIGNED_HI_OP
219 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
220 #undef TARGET_ASM_UNALIGNED_SI_OP
221 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
222 #undef TARGET_ASM_UNALIGNED_DI_OP
223 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
226 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
227 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
229 #undef TARGET_SCHED_ADJUST_COST
230 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
231 #undef TARGET_SCHED_ISSUE_RATE
232 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
233 #undef TARGET_SCHED_VARIABLE_ISSUE
234 #define TARGET_SCHED_VARIABLE_ISSUE alpha_variable_issue
236 struct gcc_target targetm
= TARGET_INITIALIZER
;
238 /* Parse target option strings. */
244 static const struct cpu_table
{
245 const char *const name
;
246 const enum processor_type processor
;
249 #define EV5_MASK (MASK_CPU_EV5)
250 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
251 { "ev4", PROCESSOR_EV4
, 0 },
252 { "ev45", PROCESSOR_EV4
, 0 },
253 { "21064", PROCESSOR_EV4
, 0 },
254 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
255 { "21164", PROCESSOR_EV5
, EV5_MASK
},
256 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
257 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
258 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
259 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
260 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
261 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
262 { "21264", PROCESSOR_EV6
, EV6_MASK
},
263 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
264 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
268 /* Unicos/Mk doesn't have shared libraries. */
269 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
271 warning ("-f%s ignored for Unicos/Mk (not supported)",
272 (flag_pic
> 1) ? "PIC" : "pic");
276 /* On Unicos/Mk, the native compiler consistenly generates /d suffices for
277 floating-point instructions. Make that the default for this target. */
278 if (TARGET_ABI_UNICOSMK
)
279 alpha_fprm
= ALPHA_FPRM_DYN
;
281 alpha_fprm
= ALPHA_FPRM_NORM
;
283 alpha_tp
= ALPHA_TP_PROG
;
284 alpha_fptm
= ALPHA_FPTM_N
;
286 /* We cannot use su and sui qualifiers for conversion instructions on
287 Unicos/Mk. I'm not sure if this is due to assembler or hardware
288 limitations. Right now, we issue a warning if -mieee is specified
289 and then ignore it; eventually, we should either get it right or
290 disable the option altogether. */
294 if (TARGET_ABI_UNICOSMK
)
295 warning ("-mieee not supported on Unicos/Mk");
298 alpha_tp
= ALPHA_TP_INSN
;
299 alpha_fptm
= ALPHA_FPTM_SU
;
303 if (TARGET_IEEE_WITH_INEXACT
)
305 if (TARGET_ABI_UNICOSMK
)
306 warning ("-mieee-with-inexact not supported on Unicos/Mk");
309 alpha_tp
= ALPHA_TP_INSN
;
310 alpha_fptm
= ALPHA_FPTM_SUI
;
316 if (! strcmp (alpha_tp_string
, "p"))
317 alpha_tp
= ALPHA_TP_PROG
;
318 else if (! strcmp (alpha_tp_string
, "f"))
319 alpha_tp
= ALPHA_TP_FUNC
;
320 else if (! strcmp (alpha_tp_string
, "i"))
321 alpha_tp
= ALPHA_TP_INSN
;
323 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string
);
326 if (alpha_fprm_string
)
328 if (! strcmp (alpha_fprm_string
, "n"))
329 alpha_fprm
= ALPHA_FPRM_NORM
;
330 else if (! strcmp (alpha_fprm_string
, "m"))
331 alpha_fprm
= ALPHA_FPRM_MINF
;
332 else if (! strcmp (alpha_fprm_string
, "c"))
333 alpha_fprm
= ALPHA_FPRM_CHOP
;
334 else if (! strcmp (alpha_fprm_string
,"d"))
335 alpha_fprm
= ALPHA_FPRM_DYN
;
337 error ("bad value `%s' for -mfp-rounding-mode switch",
341 if (alpha_fptm_string
)
343 if (strcmp (alpha_fptm_string
, "n") == 0)
344 alpha_fptm
= ALPHA_FPTM_N
;
345 else if (strcmp (alpha_fptm_string
, "u") == 0)
346 alpha_fptm
= ALPHA_FPTM_U
;
347 else if (strcmp (alpha_fptm_string
, "su") == 0)
348 alpha_fptm
= ALPHA_FPTM_SU
;
349 else if (strcmp (alpha_fptm_string
, "sui") == 0)
350 alpha_fptm
= ALPHA_FPTM_SUI
;
352 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string
);
356 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
357 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
359 if (alpha_cpu_string
)
361 for (i
= 0; cpu_table
[i
].name
; i
++)
362 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
364 alpha_cpu
= cpu_table
[i
].processor
;
365 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
366 | MASK_CPU_EV5
| MASK_CPU_EV6
);
367 target_flags
|= cpu_table
[i
].flags
;
370 if (! cpu_table
[i
].name
)
371 error ("bad value `%s' for -mcpu switch", alpha_cpu_string
);
374 if (alpha_tune_string
)
376 for (i
= 0; cpu_table
[i
].name
; i
++)
377 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
379 alpha_cpu
= cpu_table
[i
].processor
;
382 if (! cpu_table
[i
].name
)
383 error ("bad value `%s' for -mcpu switch", alpha_tune_string
);
386 /* Do some sanity checks on the above options. */
388 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
390 warning ("trap mode not supported on Unicos/Mk");
391 alpha_fptm
= ALPHA_FPTM_N
;
394 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
395 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
397 warning ("fp software completion requires -mtrap-precision=i");
398 alpha_tp
= ALPHA_TP_INSN
;
403 /* Except for EV6 pass 1 (not released), we always have precise
404 arithmetic traps. Which means we can do software completion
405 without minding trap shadows. */
406 alpha_tp
= ALPHA_TP_PROG
;
409 if (TARGET_FLOAT_VAX
)
411 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
413 warning ("rounding mode not supported for VAX floats");
414 alpha_fprm
= ALPHA_FPRM_NORM
;
416 if (alpha_fptm
== ALPHA_FPTM_SUI
)
418 warning ("trap mode not supported for VAX floats");
419 alpha_fptm
= ALPHA_FPTM_SU
;
427 if (!alpha_mlat_string
)
428 alpha_mlat_string
= "L1";
430 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
431 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
433 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
434 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
435 && alpha_mlat_string
[2] == '\0')
437 static int const cache_latency
[][4] =
439 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
440 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
441 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
444 lat
= alpha_mlat_string
[1] - '0';
445 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
447 warning ("L%d cache latency unknown for %s",
448 lat
, alpha_cpu_name
[alpha_cpu
]);
452 lat
= cache_latency
[alpha_cpu
][lat
-1];
454 else if (! strcmp (alpha_mlat_string
, "main"))
456 /* Most current memories have about 370ns latency. This is
457 a reasonable guess for a fast cpu. */
462 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string
);
466 alpha_memory_latency
= lat
;
469 /* Default the definition of "small data" to 8 bytes. */
473 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
475 target_flags
|= MASK_SMALL_DATA
;
476 else if (flag_pic
== 2)
477 target_flags
&= ~MASK_SMALL_DATA
;
479 /* Align labels and loops for optimal branching. */
480 /* ??? Kludge these by not doing anything if we don't optimize and also if
481 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
482 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
484 if (align_loops
<= 0)
486 if (align_jumps
<= 0)
489 if (align_functions
<= 0)
490 align_functions
= 16;
492 /* Acquire a unique set number for our register saves and restores. */
493 alpha_sr_alias_set
= new_alias_set ();
495 /* Register variables and functions with the garbage collector. */
497 #if TARGET_ABI_UNICOSMK
498 /* Set up function hooks. */
499 init_machine_status
= alpha_init_machine_status
;
500 mark_machine_status
= alpha_mark_machine_status
;
501 free_machine_status
= alpha_free_machine_status
;
505 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
513 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
515 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
521 /* Returns 1 if OP is either the constant zero or a register. If a
522 register, it must be in the proper mode unless MODE is VOIDmode. */
525 reg_or_0_operand (op
, mode
)
527 enum machine_mode mode
;
529 return op
== const0_rtx
|| register_operand (op
, mode
);
532 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
536 reg_or_6bit_operand (op
, mode
)
538 enum machine_mode mode
;
540 return ((GET_CODE (op
) == CONST_INT
541 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64)
542 || register_operand (op
, mode
));
546 /* Return 1 if OP is an 8-bit constant or any register. */
549 reg_or_8bit_operand (op
, mode
)
551 enum machine_mode mode
;
553 return ((GET_CODE (op
) == CONST_INT
554 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
555 || register_operand (op
, mode
));
558 /* Return 1 if OP is an 8-bit constant. */
561 cint8_operand (op
, mode
)
563 enum machine_mode mode ATTRIBUTE_UNUSED
;
565 return ((GET_CODE (op
) == CONST_INT
566 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100));
569 /* Return 1 if the operand is a valid second operand to an add insn. */
572 add_operand (op
, mode
)
574 enum machine_mode mode
;
576 if (GET_CODE (op
) == CONST_INT
)
577 /* Constraints I, J, O and P are covered by K. */
578 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K')
579 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
581 return register_operand (op
, mode
);
584 /* Return 1 if the operand is a valid second operand to a sign-extending
588 sext_add_operand (op
, mode
)
590 enum machine_mode mode
;
592 if (GET_CODE (op
) == CONST_INT
)
593 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
594 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'));
596 return reg_not_elim_operand (op
, mode
);
599 /* Return 1 if OP is the constant 4 or 8. */
602 const48_operand (op
, mode
)
604 enum machine_mode mode ATTRIBUTE_UNUSED
;
606 return (GET_CODE (op
) == CONST_INT
607 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
610 /* Return 1 if OP is a valid first operand to an AND insn. */
613 and_operand (op
, mode
)
615 enum machine_mode mode
;
617 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
618 return (zap_mask (CONST_DOUBLE_LOW (op
))
619 && zap_mask (CONST_DOUBLE_HIGH (op
)));
621 if (GET_CODE (op
) == CONST_INT
)
622 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
623 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
624 || zap_mask (INTVAL (op
)));
626 return register_operand (op
, mode
);
629 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
632 or_operand (op
, mode
)
634 enum machine_mode mode
;
636 if (GET_CODE (op
) == CONST_INT
)
637 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
638 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100);
640 return register_operand (op
, mode
);
643 /* Return 1 if OP is a constant that is the width, in bits, of an integral
644 mode smaller than DImode. */
647 mode_width_operand (op
, mode
)
649 enum machine_mode mode ATTRIBUTE_UNUSED
;
651 return (GET_CODE (op
) == CONST_INT
652 && (INTVAL (op
) == 8 || INTVAL (op
) == 16
653 || INTVAL (op
) == 32 || INTVAL (op
) == 64));
656 /* Return 1 if OP is a constant that is the width of an integral machine mode
657 smaller than an integer. */
660 mode_mask_operand (op
, mode
)
662 enum machine_mode mode ATTRIBUTE_UNUSED
;
664 #if HOST_BITS_PER_WIDE_INT == 32
665 if (GET_CODE (op
) == CONST_DOUBLE
)
666 return (CONST_DOUBLE_LOW (op
) == -1
667 && (CONST_DOUBLE_HIGH (op
) == -1
668 || CONST_DOUBLE_HIGH (op
) == 0));
670 if (GET_CODE (op
) == CONST_DOUBLE
)
671 return (CONST_DOUBLE_LOW (op
) == -1 && CONST_DOUBLE_HIGH (op
) == 0);
674 return (GET_CODE (op
) == CONST_INT
675 && (INTVAL (op
) == 0xff
676 || INTVAL (op
) == 0xffff
677 || INTVAL (op
) == (HOST_WIDE_INT
)0xffffffff
678 #if HOST_BITS_PER_WIDE_INT == 64
684 /* Return 1 if OP is a multiple of 8 less than 64. */
687 mul8_operand (op
, mode
)
689 enum machine_mode mode ATTRIBUTE_UNUSED
;
691 return (GET_CODE (op
) == CONST_INT
692 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
693 && (INTVAL (op
) & 7) == 0);
696 /* Return 1 if OP is the constant zero in floating-point. */
699 fp0_operand (op
, mode
)
701 enum machine_mode mode
;
703 return (GET_MODE (op
) == mode
704 && GET_MODE_CLASS (mode
) == MODE_FLOAT
&& op
== CONST0_RTX (mode
));
707 /* Return 1 if OP is the floating-point constant zero or a register. */
710 reg_or_fp0_operand (op
, mode
)
712 enum machine_mode mode
;
714 return fp0_operand (op
, mode
) || register_operand (op
, mode
);
717 /* Return 1 if OP is a hard floating-point register. */
720 hard_fp_register_operand (op
, mode
)
722 enum machine_mode mode
;
724 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
727 if (GET_CODE (op
) == SUBREG
)
728 op
= SUBREG_REG (op
);
729 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == FLOAT_REGS
;
732 /* Return 1 if OP is a hard general register. */
735 hard_int_register_operand (op
, mode
)
737 enum machine_mode mode
;
739 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
742 if (GET_CODE (op
) == SUBREG
)
743 op
= SUBREG_REG (op
);
744 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
;
747 /* Return 1 if OP is a register or a constant integer. */
751 reg_or_cint_operand (op
, mode
)
753 enum machine_mode mode
;
755 return (GET_CODE (op
) == CONST_INT
756 || register_operand (op
, mode
));
759 /* Return 1 if OP is something that can be reloaded into a register;
760 if it is a MEM, it need not be valid. */
763 some_operand (op
, mode
)
765 enum machine_mode mode
;
767 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
770 switch (GET_CODE (op
))
772 case REG
: case MEM
: case CONST_DOUBLE
: case CONST_INT
: case LABEL_REF
:
773 case SYMBOL_REF
: case CONST
: case HIGH
:
777 return some_operand (SUBREG_REG (op
), VOIDmode
);
786 /* Likewise, but don't accept constants. */
789 some_ni_operand (op
, mode
)
791 enum machine_mode mode
;
793 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
796 if (GET_CODE (op
) == SUBREG
)
797 op
= SUBREG_REG (op
);
799 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == MEM
);
802 /* Return 1 if OP is a valid operand for the source of a move insn. */
805 input_operand (op
, mode
)
807 enum machine_mode mode
;
809 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
812 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
815 switch (GET_CODE (op
))
820 if (TARGET_EXPLICIT_RELOCS
)
822 /* We don't split symbolic operands into something unintelligable
823 until after reload, but we do not wish non-small, non-global
824 symbolic operands to be reconstructed from their high/lo_sum
826 return (small_symbolic_operand (op
, mode
)
827 || global_symbolic_operand (op
, mode
));
830 /* This handles both the Windows/NT and OSF cases. */
831 return mode
== ptr_mode
|| mode
== DImode
;
834 return (TARGET_EXPLICIT_RELOCS
835 && local_symbolic_operand (XEXP (op
, 0), mode
));
842 if (register_operand (op
, mode
))
844 /* ... fall through ... */
846 return ((TARGET_BWX
|| (mode
!= HImode
&& mode
!= QImode
))
847 && general_operand (op
, mode
));
850 return GET_MODE_CLASS (mode
) == MODE_FLOAT
&& op
== CONST0_RTX (mode
);
853 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
865 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
866 file, and in the same section as the current function. */
869 current_file_function_operand (op
, mode
)
871 enum machine_mode mode ATTRIBUTE_UNUSED
;
873 if (GET_CODE (op
) != SYMBOL_REF
)
876 /* Easy test for recursion. */
877 if (op
== XEXP (DECL_RTL (current_function_decl
), 0))
880 /* Otherwise, we need the DECL for the SYMBOL_REF, which we can't get.
881 So SYMBOL_REF_FLAG has been declared to imply that the function is
882 in the default text section. So we must also check that the current
883 function is also in the text section. */
884 if (SYMBOL_REF_FLAG (op
) && decl_in_text_section (current_function_decl
))
890 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
893 direct_call_operand (op
, mode
)
895 enum machine_mode mode
;
897 /* Must be defined in this file. */
898 if (! current_file_function_operand (op
, mode
))
901 /* If profiling is implemented via linker tricks, we can't jump
902 to the nogp alternate entry point. */
903 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
904 but is approximately correct for the OSF ABIs. Don't know
905 what to do for VMS, NT, or UMK. */
906 if (! TARGET_PROFILING_NEEDS_GP
907 && ! current_function_profile
)
913 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
914 a variable known to be defined in this file. */
920 const char *str
= XSTR (op
, 0);
922 /* ??? SYMBOL_REF_FLAG is set for local function symbols, but we
923 run into problems with the rtl inliner in that the symbol was
924 once external, but is local after inlining, which results in
925 unrecognizable insns. */
927 return (CONSTANT_POOL_ADDRESS_P (op
)
928 /* If @, then ENCODE_SECTION_INFO sez it's local. */
930 /* If *$, then ASM_GENERATE_INTERNAL_LABEL sez it's local. */
931 || (str
[0] == '*' && str
[1] == '$'));
935 local_symbolic_operand (op
, mode
)
937 enum machine_mode mode
;
939 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
942 if (GET_CODE (op
) == LABEL_REF
)
945 if (GET_CODE (op
) == CONST
946 && GET_CODE (XEXP (op
, 0)) == PLUS
947 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
948 op
= XEXP (XEXP (op
, 0), 0);
950 if (GET_CODE (op
) != SYMBOL_REF
)
953 return local_symbol_p (op
);
956 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
957 known to be defined in this file in the small data area. */
960 small_symbolic_operand (op
, mode
)
962 enum machine_mode mode ATTRIBUTE_UNUSED
;
966 if (! TARGET_SMALL_DATA
)
969 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
972 if (GET_CODE (op
) == CONST
973 && GET_CODE (XEXP (op
, 0)) == PLUS
974 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
975 op
= XEXP (XEXP (op
, 0), 0);
977 if (GET_CODE (op
) != SYMBOL_REF
)
980 if (CONSTANT_POOL_ADDRESS_P (op
))
981 return GET_MODE_SIZE (get_pool_mode (op
)) <= (unsigned) g_switch_value
;
985 return str
[0] == '@' && str
[1] == 's';
989 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
990 not known (or known not) to be defined in this file. */
993 global_symbolic_operand (op
, mode
)
995 enum machine_mode mode
;
997 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1000 if (GET_CODE (op
) == CONST
1001 && GET_CODE (XEXP (op
, 0)) == PLUS
1002 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1003 op
= XEXP (XEXP (op
, 0), 0);
1005 if (GET_CODE (op
) != SYMBOL_REF
)
1008 return ! local_symbol_p (op
);
1011 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
1014 call_operand (op
, mode
)
1016 enum machine_mode mode
;
1021 if (GET_CODE (op
) == REG
)
1025 /* Disallow virtual registers to cope with pathalogical test cases
1026 such as compile/930117-1.c in which the virtual reg decomposes
1027 to the frame pointer. Which is a hard reg that is not $27. */
1028 return (REGNO (op
) == 27 || REGNO (op
) > LAST_VIRTUAL_REGISTER
);
1033 if (TARGET_ABI_UNICOSMK
)
1035 if (GET_CODE (op
) == SYMBOL_REF
)
1041 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1042 possibly with an offset. */
1045 symbolic_operand (op
, mode
)
1047 enum machine_mode mode
;
1049 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1051 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1053 if (GET_CODE (op
) == CONST
1054 && GET_CODE (XEXP (op
,0)) == PLUS
1055 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1056 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1061 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1062 comparisons are valid in which insn. */
1065 alpha_comparison_operator (op
, mode
)
1067 enum machine_mode mode
;
1069 enum rtx_code code
= GET_CODE (op
);
1071 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1074 return (code
== EQ
|| code
== LE
|| code
== LT
1075 || code
== LEU
|| code
== LTU
);
1078 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1079 Here we know which comparisons are valid in which insn. */
1082 alpha_zero_comparison_operator (op
, mode
)
1084 enum machine_mode mode
;
1086 enum rtx_code code
= GET_CODE (op
);
1088 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1091 return (code
== EQ
|| code
== NE
|| code
== LE
|| code
== LT
1092 || code
== LEU
|| code
== LTU
);
1095 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1098 alpha_swapped_comparison_operator (op
, mode
)
1100 enum machine_mode mode
;
1102 enum rtx_code code
= GET_CODE (op
);
1104 if ((mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1105 || GET_RTX_CLASS (code
) != '<')
1108 code
= swap_condition (code
);
1109 return (code
== EQ
|| code
== LE
|| code
== LT
1110 || code
== LEU
|| code
== LTU
);
1113 /* Return 1 if OP is a signed comparison operation. */
1116 signed_comparison_operator (op
, mode
)
1118 enum machine_mode mode ATTRIBUTE_UNUSED
;
1120 enum rtx_code code
= GET_CODE (op
);
1122 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1125 return (code
== EQ
|| code
== NE
1126 || code
== LE
|| code
== LT
1127 || code
== GE
|| code
== GT
);
1130 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1131 Here we know which comparisons are valid in which insn. */
1134 alpha_fp_comparison_operator (op
, mode
)
1136 enum machine_mode mode
;
1138 enum rtx_code code
= GET_CODE (op
);
1140 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1143 return (code
== EQ
|| code
== LE
|| code
== LT
|| code
== UNORDERED
);
1146 /* Return 1 if this is a divide or modulus operator. */
1149 divmod_operator (op
, mode
)
1151 enum machine_mode mode ATTRIBUTE_UNUSED
;
1153 switch (GET_CODE (op
))
1155 case DIV
: case MOD
: case UDIV
: case UMOD
:
1165 /* Return 1 if this memory address is a known aligned register plus
1166 a constant. It must be a valid address. This means that we can do
1167 this as an aligned reference plus some offset.
1169 Take into account what reload will do. */
1172 aligned_memory_operand (op
, mode
)
1174 enum machine_mode mode
;
1178 if (reload_in_progress
)
1181 if (GET_CODE (tmp
) == SUBREG
)
1182 tmp
= SUBREG_REG (tmp
);
1183 if (GET_CODE (tmp
) == REG
1184 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1186 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1192 if (GET_CODE (op
) != MEM
1193 || GET_MODE (op
) != mode
)
1197 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1198 sorts of constructs. Dig for the real base register. */
1199 if (reload_in_progress
1200 && GET_CODE (op
) == PLUS
1201 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1202 base
= XEXP (XEXP (op
, 0), 0);
1205 if (! memory_address_p (mode
, op
))
1207 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1210 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) >= 32);
1213 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1216 unaligned_memory_operand (op
, mode
)
1218 enum machine_mode mode
;
1222 if (reload_in_progress
)
1225 if (GET_CODE (tmp
) == SUBREG
)
1226 tmp
= SUBREG_REG (tmp
);
1227 if (GET_CODE (tmp
) == REG
1228 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1230 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1236 if (GET_CODE (op
) != MEM
1237 || GET_MODE (op
) != mode
)
1241 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1242 sorts of constructs. Dig for the real base register. */
1243 if (reload_in_progress
1244 && GET_CODE (op
) == PLUS
1245 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1246 base
= XEXP (XEXP (op
, 0), 0);
1249 if (! memory_address_p (mode
, op
))
1251 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1254 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) < 32);
1257 /* Return 1 if OP is either a register or an unaligned memory location. */
1260 reg_or_unaligned_mem_operand (op
, mode
)
1262 enum machine_mode mode
;
1264 return register_operand (op
, mode
) || unaligned_memory_operand (op
, mode
);
1267 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1270 any_memory_operand (op
, mode
)
1272 enum machine_mode mode ATTRIBUTE_UNUSED
;
1274 return (GET_CODE (op
) == MEM
1275 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
1276 || (reload_in_progress
&& GET_CODE (op
) == REG
1277 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1278 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
1279 && GET_CODE (SUBREG_REG (op
)) == REG
1280 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
1283 /* Returns 1 if OP is not an eliminable register.
1285 This exists to cure a pathological abort in the s8addq (et al) patterns,
1287 long foo () { long t; bar(); return (long) &t * 26107; }
1289 which run afoul of a hack in reload to cure a (presumably) similar
1290 problem with lea-type instructions on other targets. But there is
1291 one of us and many of them, so work around the problem by selectively
1292 preventing combine from making the optimization. */
1295 reg_not_elim_operand (op
, mode
)
1297 enum machine_mode mode
;
1300 if (GET_CODE (op
) == SUBREG
)
1301 inner
= SUBREG_REG (op
);
1302 if (inner
== frame_pointer_rtx
|| inner
== arg_pointer_rtx
)
1305 return register_operand (op
, mode
);
1308 /* Return 1 is OP is a memory location that is not a reference (using
1309 an AND) to an unaligned location. Take into account what reload
1313 normal_memory_operand (op
, mode
)
1315 enum machine_mode mode ATTRIBUTE_UNUSED
;
1317 if (reload_in_progress
)
1320 if (GET_CODE (tmp
) == SUBREG
)
1321 tmp
= SUBREG_REG (tmp
);
1322 if (GET_CODE (tmp
) == REG
1323 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1325 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1327 /* This may not have been assigned an equivalent address if it will
1328 be eliminated. In that case, it doesn't matter what we do. */
1334 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) != AND
;
1337 /* Accept a register, but not a subreg of any kind. This allows us to
1338 avoid pathological cases in reload wrt data movement common in
1339 int->fp conversion. */
1342 reg_no_subreg_operand (op
, mode
)
1344 enum machine_mode mode
;
1346 if (GET_CODE (op
) != REG
)
1348 return register_operand (op
, mode
);
1351 /* Recognize an addition operation that includes a constant. Used to
1352 convince reload to canonize (plus (plus reg c1) c2) during register
1356 addition_operation (op
, mode
)
1358 enum machine_mode mode
;
1360 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1362 if (GET_CODE (op
) == PLUS
1363 && register_operand (XEXP (op
, 0), mode
)
1364 && GET_CODE (XEXP (op
, 1)) == CONST_INT
1365 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op
, 1)), 'K'))
1370 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1371 the range defined for C in [I-P]. */
1374 alpha_const_ok_for_letter_p (value
, c
)
1375 HOST_WIDE_INT value
;
1381 /* An unsigned 8 bit constant. */
1382 return (unsigned HOST_WIDE_INT
) value
< 0x100;
1384 /* The constant zero. */
1387 /* A signed 16 bit constant. */
1388 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
1390 /* A shifted signed 16 bit constant appropriate for LDAH. */
1391 return ((value
& 0xffff) == 0
1392 && ((value
) >> 31 == -1 || value
>> 31 == 0));
1394 /* A constant that can be AND'ed with using a ZAP insn. */
1395 return zap_mask (value
);
1397 /* A complemented unsigned 8 bit constant. */
1398 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
1400 /* A negated unsigned 8 bit constant. */
1401 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
1403 /* The constant 1, 2 or 3. */
1404 return value
== 1 || value
== 2 || value
== 3;
1411 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1412 matches for C in [GH]. */
1415 alpha_const_double_ok_for_letter_p (value
, c
)
1422 /* The floating point zero constant. */
1423 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
1424 && value
== CONST0_RTX (GET_MODE (value
)));
1427 /* A valid operand of a ZAP insn. */
1428 return (GET_MODE (value
) == VOIDmode
1429 && zap_mask (CONST_DOUBLE_LOW (value
))
1430 && zap_mask (CONST_DOUBLE_HIGH (value
)));
1437 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1441 alpha_extra_constraint (value
, c
)
1448 return normal_memory_operand (value
, VOIDmode
);
1450 return direct_call_operand (value
, Pmode
);
1452 return (GET_CODE (value
) == CONST_INT
1453 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
1455 return GET_CODE (value
) == HIGH
;
1457 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
1464 /* Return 1 if this function can directly return via $26. */
1469 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
1471 && alpha_sa_size () == 0
1472 && get_frame_size () == 0
1473 && current_function_outgoing_args_size
== 0
1474 && current_function_pretend_args_size
== 0);
1477 /* Return the ADDR_VEC associated with a tablejump insn. */
1480 alpha_tablejump_addr_vec (insn
)
1485 tmp
= JUMP_LABEL (insn
);
1488 tmp
= NEXT_INSN (tmp
);
1491 if (GET_CODE (tmp
) == JUMP_INSN
1492 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
1493 return PATTERN (tmp
);
1497 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1500 alpha_tablejump_best_label (insn
)
1503 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
1504 rtx best_label
= NULL_RTX
;
1506 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1507 there for edge frequency counts from profile data. */
1511 int n_labels
= XVECLEN (jump_table
, 1);
1512 int best_count
= -1;
1515 for (i
= 0; i
< n_labels
; i
++)
1519 for (j
= i
+ 1; j
< n_labels
; j
++)
1520 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
1521 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
1524 if (count
> best_count
)
1525 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
1529 return best_label
? best_label
: const0_rtx
;
1532 /* Return true if the function DECL will be placed in the default text
1534 /* ??? Ideally we'd be able to always move from a SYMBOL_REF back to the
1535 decl, as that would allow us to determine if two functions are in the
1536 same section, which is what we really want to know. */
1539 decl_in_text_section (decl
)
1542 return (DECL_SECTION_NAME (decl
) == NULL_TREE
1543 && ! (flag_function_sections
1544 || (targetm
.have_named_sections
1545 && DECL_ONE_ONLY (decl
))));
1548 /* If we are referencing a function that is static, make the SYMBOL_REF
1549 special. We use this to see indicate we can branch to this function
1550 without setting PV or restoring GP.
1552 If this is a variable that is known to be defined locally, add "@v"
1553 to the name. If in addition the variable is to go in .sdata/.sbss,
1554 then add "@s" instead. */
1557 alpha_encode_section_info (decl
, first
)
1559 int first ATTRIBUTE_UNUSED
;
1561 const char *symbol_str
;
1562 bool is_local
, is_small
;
1564 if (TREE_CODE (decl
) == FUNCTION_DECL
)
1566 /* We mark public functions once they are emitted; otherwise we
1567 don't know that they exist in this unit of translation. */
1568 if (TREE_PUBLIC (decl
))
1571 /* Do not mark functions that are not in .text; otherwise we
1572 don't know that they are near enough for a direct branch. */
1573 if (! decl_in_text_section (decl
))
1576 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl
), 0)) = 1;
1580 /* Early out if we're not going to do anything with this data. */
1581 if (! TARGET_EXPLICIT_RELOCS
)
1584 /* Careful not to prod global register variables. */
1585 if (TREE_CODE (decl
) != VAR_DECL
1586 || GET_CODE (DECL_RTL (decl
)) != MEM
1587 || GET_CODE (XEXP (DECL_RTL (decl
), 0)) != SYMBOL_REF
)
1590 symbol_str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
1592 /* A variable is considered "local" if it is defined in this module. */
1594 /* Local binding occurs for any non-default visibility. */
1595 if (MODULE_LOCAL_P (decl
))
1597 /* Otherwise, variables defined outside this object may not be local. */
1598 else if (DECL_EXTERNAL (decl
))
1600 /* Linkonce and weak data is never local. */
1601 else if (DECL_ONE_ONLY (decl
) || DECL_WEAK (decl
))
1603 /* Static variables are always local. */
1604 else if (! TREE_PUBLIC (decl
))
1606 /* If PIC, then assume that any global name can be overridden by
1607 symbols resolved from other modules. */
1610 /* Uninitialized COMMON variable may be unified with symbols
1611 resolved from other modules. */
1612 else if (DECL_COMMON (decl
)
1613 && (DECL_INITIAL (decl
) == NULL
1614 || DECL_INITIAL (decl
) == error_mark_node
))
1616 /* Otherwise we're left with initialized (or non-common) global data
1617 which is of necessity defined locally. */
1621 /* Determine if DECL will wind up in .sdata/.sbss. */
1624 if (DECL_SECTION_NAME (decl
))
1626 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
1627 if (strcmp (section
, ".sdata") == 0
1628 || strcmp (section
, ".sbss") == 0)
1633 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
1635 /* If the variable has already been defined in the output file, then it
1636 is too late to put it in sdata if it wasn't put there in the first
1637 place. The test is here rather than above, because if it is already
1638 in sdata, then it can stay there. */
1640 if (TREE_ASM_WRITTEN (decl
))
1643 /* If this is an incomplete type with size 0, then we can't put it in
1644 sdata because it might be too big when completed. */
1645 else if (size
> 0 && size
<= g_switch_value
)
1649 /* Finally, encode this into the symbol string. */
1656 if (symbol_str
[0] == '@')
1658 if (symbol_str
[1] == (is_small
? 's' : 'v'))
1663 len
= strlen (symbol_str
) + 1;
1664 newstr
= alloca (len
+ 2);
1667 newstr
[1] = (is_small
? 's' : 'v');
1668 memcpy (newstr
+ 2, symbol_str
, len
);
1670 string
= ggc_alloc_string (newstr
, len
+ 2 - 1);
1671 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = string
;
1673 else if (symbol_str
[0] == '@')
1677 /* legitimate_address_p recognizes an RTL expression that is a valid
1678 memory address for an instruction. The MODE argument is the
1679 machine mode for the MEM expression that wants to use this address.
1681 For Alpha, we have either a constant address or the sum of a
1682 register and a constant address, or just a register. For DImode,
1683 any of those forms can be surrounded with an AND that clear the
1684 low-order three bits; this is an "unaligned" access. */
1687 alpha_legitimate_address_p (mode
, x
, strict
)
1688 enum machine_mode mode
;
1692 /* If this is an ldq_u type address, discard the outer AND. */
1694 && GET_CODE (x
) == AND
1695 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1696 && INTVAL (XEXP (x
, 1)) == -8)
1699 /* Discard non-paradoxical subregs. */
1700 if (GET_CODE (x
) == SUBREG
1701 && (GET_MODE_SIZE (GET_MODE (x
))
1702 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1705 /* Unadorned general registers are valid. */
1708 ? STRICT_REG_OK_FOR_BASE_P (x
)
1709 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
1712 /* Constant addresses (i.e. +/- 32k) are valid. */
1713 if (CONSTANT_ADDRESS_P (x
))
1716 /* Register plus a small constant offset is valid. */
1717 if (GET_CODE (x
) == PLUS
)
1719 rtx ofs
= XEXP (x
, 1);
1722 /* Discard non-paradoxical subregs. */
1723 if (GET_CODE (x
) == SUBREG
1724 && (GET_MODE_SIZE (GET_MODE (x
))
1725 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1731 && NONSTRICT_REG_OK_FP_BASE_P (x
)
1732 && GET_CODE (ofs
) == CONST_INT
)
1735 ? STRICT_REG_OK_FOR_BASE_P (x
)
1736 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
1737 && CONSTANT_ADDRESS_P (ofs
))
1740 else if (GET_CODE (x
) == ADDRESSOF
1741 && GET_CODE (ofs
) == CONST_INT
)
1745 /* If we're managing explicit relocations, LO_SUM is valid, as
1746 are small data symbols. */
1747 else if (TARGET_EXPLICIT_RELOCS
)
1749 if (small_symbolic_operand (x
, Pmode
))
1752 if (GET_CODE (x
) == LO_SUM
)
1754 rtx ofs
= XEXP (x
, 1);
1757 /* Discard non-paradoxical subregs. */
1758 if (GET_CODE (x
) == SUBREG
1759 && (GET_MODE_SIZE (GET_MODE (x
))
1760 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1763 /* Must have a valid base register. */
1766 ? STRICT_REG_OK_FOR_BASE_P (x
)
1767 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
1770 /* The symbol must be local. */
1771 if (local_symbolic_operand (ofs
, Pmode
))
1779 /* Try machine-dependent ways of modifying an illegitimate address
1780 to be legitimate. If we find one, return the new, valid address. */
1783 alpha_legitimize_address (x
, scratch
, mode
)
1786 enum machine_mode mode ATTRIBUTE_UNUSED
;
1788 HOST_WIDE_INT addend
;
1790 /* If the address is (plus reg const_int) and the CONST_INT is not a
1791 valid offset, compute the high part of the constant and add it to
1792 the register. Then our address is (plus temp low-part-const). */
1793 if (GET_CODE (x
) == PLUS
1794 && GET_CODE (XEXP (x
, 0)) == REG
1795 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1796 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
1798 addend
= INTVAL (XEXP (x
, 1));
1803 /* If the address is (const (plus FOO const_int)), find the low-order
1804 part of the CONST_INT. Then load FOO plus any high-order part of the
1805 CONST_INT into a register. Our address is (plus reg low-part-const).
1806 This is done to reduce the number of GOT entries. */
1808 && GET_CODE (x
) == CONST
1809 && GET_CODE (XEXP (x
, 0)) == PLUS
1810 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
1812 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
1813 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
1817 /* If we have a (plus reg const), emit the load as in (2), then add
1818 the two registers, and finally generate (plus reg low-part-const) as
1821 && GET_CODE (x
) == PLUS
1822 && GET_CODE (XEXP (x
, 0)) == REG
1823 && GET_CODE (XEXP (x
, 1)) == CONST
1824 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
1825 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
1827 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
1828 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
1829 XEXP (XEXP (XEXP (x
, 1), 0), 0),
1830 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1834 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1835 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
1837 if (local_symbolic_operand (x
, Pmode
))
1839 if (small_symbolic_operand (x
, Pmode
))
1843 if (!no_new_pseudos
)
1844 scratch
= gen_reg_rtx (Pmode
);
1845 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
1846 gen_rtx_HIGH (Pmode
, x
)));
1847 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
1856 HOST_WIDE_INT low
, high
;
1858 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
1860 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1864 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
1865 (no_new_pseudos
? scratch
: NULL_RTX
),
1866 1, OPTAB_LIB_WIDEN
);
1868 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
1869 (no_new_pseudos
? scratch
: NULL_RTX
),
1870 1, OPTAB_LIB_WIDEN
);
1872 return plus_constant (x
, low
);
1876 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1877 small symbolic operand until after reload. At which point we need
1878 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1879 so that sched2 has the proper dependency information. */
1882 some_small_symbolic_operand (x
, mode
)
1884 enum machine_mode mode ATTRIBUTE_UNUSED
;
1886 return for_each_rtx (&x
, some_small_symbolic_operand_1
, NULL
);
1890 some_small_symbolic_operand_1 (px
, data
)
1892 void *data ATTRIBUTE_UNUSED
;
1896 /* Don't re-split. */
1897 if (GET_CODE (x
) == LO_SUM
)
1900 return small_symbolic_operand (x
, Pmode
) != 0;
1904 split_small_symbolic_operand (x
)
1908 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
1913 split_small_symbolic_operand_1 (px
, data
)
1915 void *data ATTRIBUTE_UNUSED
;
1919 /* Don't re-split. */
1920 if (GET_CODE (x
) == LO_SUM
)
1923 if (small_symbolic_operand (x
, Pmode
))
1925 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
1933 /* Try a machine-dependent way of reloading an illegitimate address
1934 operand. If we find one, push the reload and return the new rtx. */
1937 alpha_legitimize_reload_address (x
, mode
, opnum
, type
, ind_levels
)
1939 enum machine_mode mode ATTRIBUTE_UNUSED
;
1942 int ind_levels ATTRIBUTE_UNUSED
;
1944 /* We must recognize output that we have already generated ourselves. */
1945 if (GET_CODE (x
) == PLUS
1946 && GET_CODE (XEXP (x
, 0)) == PLUS
1947 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1948 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1949 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1951 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1952 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1957 /* We wish to handle large displacements off a base register by
1958 splitting the addend across an ldah and the mem insn. This
1959 cuts number of extra insns needed from 3 to 1. */
1960 if (GET_CODE (x
) == PLUS
1961 && GET_CODE (XEXP (x
, 0)) == REG
1962 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
1963 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
1964 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1966 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
1967 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
1969 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
1971 /* Check for 32-bit overflow. */
1972 if (high
+ low
!= val
)
1975 /* Reload the high part into a base reg; leave the low part
1976 in the mem directly. */
1977 x
= gen_rtx_PLUS (GET_MODE (x
),
1978 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
1982 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1983 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1991 /* REF is an alignable memory location. Place an aligned SImode
1992 reference into *PALIGNED_MEM and the number of bits to shift into
1993 *PBITNUM. SCRATCH is a free register for use in reloading out
1994 of range stack slots. */
1997 get_aligned_mem (ref
, paligned_mem
, pbitnum
)
1999 rtx
*paligned_mem
, *pbitnum
;
2002 HOST_WIDE_INT offset
= 0;
2004 if (GET_CODE (ref
) != MEM
)
2007 if (reload_in_progress
2008 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2010 base
= find_replacement (&XEXP (ref
, 0));
2012 if (! memory_address_p (GET_MODE (ref
), base
))
2017 base
= XEXP (ref
, 0);
2020 if (GET_CODE (base
) == PLUS
)
2021 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2024 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
2026 if (WORDS_BIG_ENDIAN
)
2027 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
2028 + (offset
& 3) * 8));
2030 *pbitnum
= GEN_INT ((offset
& 3) * 8);
2033 /* Similar, but just get the address. Handle the two reload cases.
2034 Add EXTRA_OFFSET to the address we return. */
2037 get_unaligned_address (ref
, extra_offset
)
2042 HOST_WIDE_INT offset
= 0;
2044 if (GET_CODE (ref
) != MEM
)
2047 if (reload_in_progress
2048 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2050 base
= find_replacement (&XEXP (ref
, 0));
2052 if (! memory_address_p (GET_MODE (ref
), base
))
2057 base
= XEXP (ref
, 0);
2060 if (GET_CODE (base
) == PLUS
)
2061 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2063 return plus_constant (base
, offset
+ extra_offset
);
2066 /* On the Alpha, all (non-symbolic) constants except zero go into
2067 a floating-point register via memory. Note that we cannot
2068 return anything that is not a subset of CLASS, and that some
2069 symbolic constants cannot be dropped to memory. */
2072 alpha_preferred_reload_class(x
, class)
2074 enum reg_class
class;
2076 /* Zero is present in any register class. */
2077 if (x
== CONST0_RTX (GET_MODE (x
)))
2080 /* These sorts of constants we can easily drop to memory. */
2081 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2083 if (class == FLOAT_REGS
)
2085 if (class == ALL_REGS
)
2086 return GENERAL_REGS
;
2090 /* All other kinds of constants should not (and in the case of HIGH
2091 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2092 secondary reload. */
2094 return (class == ALL_REGS
? GENERAL_REGS
: class);
2099 /* Loading and storing HImode or QImode values to and from memory
2100 usually requires a scratch register. The exceptions are loading
2101 QImode and HImode from an aligned address to a general register
2102 unless byte instructions are permitted.
2104 We also cannot load an unaligned address or a paradoxical SUBREG
2105 into an FP register.
2107 We also cannot do integral arithmetic into FP regs, as might result
2108 from register elimination into a DImode fp register. */
2111 secondary_reload_class (class, mode
, x
, in
)
2112 enum reg_class
class;
2113 enum machine_mode mode
;
2117 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
2119 if (GET_CODE (x
) == MEM
2120 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
2121 || (GET_CODE (x
) == SUBREG
2122 && (GET_CODE (SUBREG_REG (x
)) == MEM
2123 || (GET_CODE (SUBREG_REG (x
)) == REG
2124 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
2126 if (!in
|| !aligned_memory_operand(x
, mode
))
2127 return GENERAL_REGS
;
2131 if (class == FLOAT_REGS
)
2133 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
2134 return GENERAL_REGS
;
2136 if (GET_CODE (x
) == SUBREG
2137 && (GET_MODE_SIZE (GET_MODE (x
))
2138 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2139 return GENERAL_REGS
;
2141 if (in
&& INTEGRAL_MODE_P (mode
)
2142 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
2143 return GENERAL_REGS
;
2149 /* Subfunction of the following function. Update the flags of any MEM
2150 found in part of X. */
2153 alpha_set_memflags_1 (x
, in_struct_p
, volatile_p
, unchanging_p
)
2155 int in_struct_p
, volatile_p
, unchanging_p
;
2159 switch (GET_CODE (x
))
2163 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2164 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
2169 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
2174 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
2176 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
2181 MEM_IN_STRUCT_P (x
) = in_struct_p
;
2182 MEM_VOLATILE_P (x
) = volatile_p
;
2183 RTX_UNCHANGING_P (x
) = unchanging_p
;
2184 /* Sadly, we cannot use alias sets because the extra aliasing
2185 produced by the AND interferes. Given that two-byte quantities
2186 are the only thing we would be able to differentiate anyway,
2187 there does not seem to be any point in convoluting the early
2188 out of the alias check. */
2196 /* Given INSN, which is either an INSN or a SEQUENCE generated to
2197 perform a memory operation, look for any MEMs in either a SET_DEST or
2198 a SET_SRC and copy the in-struct, unchanging, and volatile flags from
2199 REF into each of the MEMs found. If REF is not a MEM, don't do
2203 alpha_set_memflags (insn
, ref
)
2207 int in_struct_p
, volatile_p
, unchanging_p
;
2209 if (GET_CODE (ref
) != MEM
)
2212 in_struct_p
= MEM_IN_STRUCT_P (ref
);
2213 volatile_p
= MEM_VOLATILE_P (ref
);
2214 unchanging_p
= RTX_UNCHANGING_P (ref
);
2216 /* This is only called from alpha.md, after having had something
2217 generated from one of the insn patterns. So if everything is
2218 zero, the pattern is already up-to-date. */
2219 if (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
)
2222 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
2225 /* Try to output insns to set TARGET equal to the constant C if it can be
2226 done in less than N insns. Do all computations in MODE. Returns the place
2227 where the output has been placed if it can be done and the insns have been
2228 emitted. If it would take more than N insns, zero is returned and no
2229 insns and emitted. */
2232 alpha_emit_set_const (target
, mode
, c
, n
)
2234 enum machine_mode mode
;
2239 rtx orig_target
= target
;
2242 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2243 can't load this constant in one insn, do this in DImode. */
2244 if (no_new_pseudos
&& mode
== SImode
2245 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
2246 && (result
= alpha_emit_set_const_1 (target
, mode
, c
, 1)) == 0)
2248 target
= gen_lowpart (DImode
, target
);
2252 /* Try 1 insn, then 2, then up to N. */
2253 for (i
= 1; i
<= n
&& result
== 0; i
++)
2254 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
);
2256 /* Allow for the case where we changed the mode of TARGET. */
2257 if (result
== target
)
2258 result
= orig_target
;
2263 /* Internal routine for the above to check for N or below insns. */
2266 alpha_emit_set_const_1 (target
, mode
, c
, n
)
2268 enum machine_mode mode
;
2274 /* Use a pseudo if highly optimizing and still generating RTL. */
2276 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
2279 #if HOST_BITS_PER_WIDE_INT == 64
2280 /* We are only called for SImode and DImode. If this is SImode, ensure that
2281 we are sign extended to a full word. This does not make any sense when
2282 cross-compiling on a narrow machine. */
2285 c
= ((c
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2288 /* If this is a sign-extended 32-bit constant, we can do this in at most
2289 three insns, so do it if we have enough insns left. We always have
2290 a sign-extended 32-bit constant when compiling on a narrow machine. */
2292 if (HOST_BITS_PER_WIDE_INT
!= 64
2293 || c
>> 31 == -1 || c
>> 31 == 0)
2295 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
2296 HOST_WIDE_INT tmp1
= c
- low
;
2297 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
2298 HOST_WIDE_INT extra
= 0;
2300 /* If HIGH will be interpreted as negative but the constant is
2301 positive, we must adjust it to do two ldha insns. */
2303 if ((high
& 0x8000) != 0 && c
>= 0)
2307 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
2310 if (c
== low
|| (low
== 0 && extra
== 0))
2312 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2313 but that meant that we can't handle INT_MIN on 32-bit machines
2314 (like NT/Alpha), because we recurse indefinitely through
2315 emit_move_insn to gen_movdi. So instead, since we know exactly
2316 what we want, create it explicitly. */
2319 target
= gen_reg_rtx (mode
);
2320 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
2323 else if (n
>= 2 + (extra
!= 0))
2325 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16), subtarget
, mode
);
2327 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2328 This means that if we go through expand_binop, we'll try to
2329 generate extensions, etc, which will require new pseudos, which
2330 will fail during some split phases. The SImode add patterns
2331 still exist, but are not named. So build the insns by hand. */
2336 subtarget
= gen_reg_rtx (mode
);
2337 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
2338 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
2343 target
= gen_reg_rtx (mode
);
2344 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
2345 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
2351 /* If we couldn't do it that way, try some other methods. But if we have
2352 no instructions left, don't bother. Likewise, if this is SImode and
2353 we can't make pseudos, we can't do anything since the expand_binop
2354 and expand_unop calls will widen and try to make pseudos. */
2356 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
2359 /* Next, see if we can load a related constant and then shift and possibly
2360 negate it to get the constant we want. Try this once each increasing
2361 numbers of insns. */
2363 for (i
= 1; i
< n
; i
++)
2365 /* First, see if minus some low bits, we've an easy load of
2368 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
2370 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
2371 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
2372 target
, 0, OPTAB_WIDEN
);
2374 /* Next try complementing. */
2375 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
2376 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
2378 /* Next try to form a constant and do a left shift. We can do this
2379 if some low-order bits are zero; the exact_log2 call below tells
2380 us that information. The bits we are shifting out could be any
2381 value, but here we'll just try the 0- and sign-extended forms of
2382 the constant. To try to increase the chance of having the same
2383 constant in more than one insn, start at the highest number of
2384 bits to shift, but try all possibilities in case a ZAPNOT will
2387 if ((bits
= exact_log2 (c
& - c
)) > 0)
2388 for (; bits
> 0; bits
--)
2389 if ((temp
= (alpha_emit_set_const
2390 (subtarget
, mode
, c
>> bits
, i
))) != 0
2391 || ((temp
= (alpha_emit_set_const
2393 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
2395 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
2396 target
, 0, OPTAB_WIDEN
);
2398 /* Now try high-order zero bits. Here we try the shifted-in bits as
2399 all zero and all ones. Be careful to avoid shifting outside the
2400 mode and to avoid shifting outside the host wide int size. */
2401 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2402 confuse the recursive call and set all of the high 32 bits. */
2404 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2405 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
2406 for (; bits
> 0; bits
--)
2407 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2409 || ((temp
= (alpha_emit_set_const
2411 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2414 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
2415 target
, 1, OPTAB_WIDEN
);
2417 /* Now try high-order 1 bits. We get that with a sign-extension.
2418 But one bit isn't enough here. Be careful to avoid shifting outside
2419 the mode and to avoid shifting outside the host wide int size. */
2421 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2422 - floor_log2 (~ c
) - 2)) > 0)
2423 for (; bits
> 0; bits
--)
2424 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2426 || ((temp
= (alpha_emit_set_const
2428 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2431 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
2432 target
, 0, OPTAB_WIDEN
);
2435 #if HOST_BITS_PER_WIDE_INT == 64
2436 /* Finally, see if can load a value into the target that is the same as the
2437 constant except that all bytes that are 0 are changed to be 0xff. If we
2438 can, then we can do a ZAPNOT to obtain the desired constant. */
2441 for (i
= 0; i
< 64; i
+= 8)
2442 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
2443 new |= (HOST_WIDE_INT
) 0xff << i
;
2445 /* We are only called for SImode and DImode. If this is SImode, ensure that
2446 we are sign extended to a full word. */
2449 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2451 if (new != c
&& new != -1
2452 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
2453 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
2454 target
, 0, OPTAB_WIDEN
);
2460 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2461 fall back to a straight forward decomposition. We do this to avoid
2462 exponential run times encountered when looking for longer sequences
2463 with alpha_emit_set_const. */
2466 alpha_emit_set_long_const (target
, c1
, c2
)
2468 HOST_WIDE_INT c1
, c2
;
2470 HOST_WIDE_INT d1
, d2
, d3
, d4
;
2472 /* Decompose the entire word */
2473 #if HOST_BITS_PER_WIDE_INT >= 64
2474 if (c2
!= -(c1
< 0))
2476 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2478 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2479 c1
= (c1
- d2
) >> 32;
2480 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2482 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2486 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2488 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2492 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
2494 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2499 /* Construct the high word */
2502 emit_move_insn (target
, GEN_INT (d4
));
2504 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2507 emit_move_insn (target
, GEN_INT (d3
));
2509 /* Shift it into place */
2510 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2512 /* Add in the low bits. */
2514 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2516 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
2521 /* Expand a move instruction; return true if all work is done.
2522 We don't handle non-bwx subword loads here. */
2525 alpha_expand_mov (mode
, operands
)
2526 enum machine_mode mode
;
2529 /* If the output is not a register, the input must be. */
2530 if (GET_CODE (operands
[0]) == MEM
2531 && ! reg_or_0_operand (operands
[1], mode
))
2532 operands
[1] = force_reg (mode
, operands
[1]);
2534 /* Allow legitimize_address to perform some simplifications. */
2535 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2537 rtx tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
2545 /* Early out for non-constants and valid constants. */
2546 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2549 /* Split large integers. */
2550 if (GET_CODE (operands
[1]) == CONST_INT
2551 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
2553 HOST_WIDE_INT i0
, i1
;
2554 rtx temp
= NULL_RTX
;
2556 if (GET_CODE (operands
[1]) == CONST_INT
)
2558 i0
= INTVAL (operands
[1]);
2561 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2563 i0
= CONST_DOUBLE_LOW (operands
[1]);
2568 i0
= CONST_DOUBLE_LOW (operands
[1]);
2569 i1
= CONST_DOUBLE_HIGH (operands
[1]);
2572 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2573 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
2575 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2576 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
2580 if (rtx_equal_p (operands
[0], temp
))
2587 /* Otherwise we've nothing left but to drop the thing to memory. */
2588 operands
[1] = force_const_mem (DImode
, operands
[1]);
2589 if (reload_in_progress
)
2591 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
2592 operands
[1] = copy_rtx (operands
[1]);
2593 XEXP (operands
[1], 0) = operands
[0];
2596 operands
[1] = validize_mem (operands
[1]);
2600 /* Expand a non-bwx QImode or HImode move instruction;
2601 return true if all work is done. */
2604 alpha_expand_mov_nobwx (mode
, operands
)
2605 enum machine_mode mode
;
2608 /* If the output is not a register, the input must be. */
2609 if (GET_CODE (operands
[0]) == MEM
)
2610 operands
[1] = force_reg (mode
, operands
[1]);
2612 /* Handle four memory cases, unaligned and aligned for either the input
2613 or the output. The only case where we can be called during reload is
2614 for aligned loads; all other cases require temporaries. */
2616 if (GET_CODE (operands
[1]) == MEM
2617 || (GET_CODE (operands
[1]) == SUBREG
2618 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
2619 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
2620 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
2621 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
2622 && GET_CODE (SUBREG_REG (operands
[1])) == REG
2623 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
2625 if (aligned_memory_operand (operands
[1], mode
))
2627 if (reload_in_progress
)
2629 emit_insn ((mode
== QImode
2630 ? gen_reload_inqi_help
2631 : gen_reload_inhi_help
)
2632 (operands
[0], operands
[1],
2633 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
2637 rtx aligned_mem
, bitnum
;
2638 rtx scratch
= gen_reg_rtx (SImode
);
2640 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
2642 emit_insn ((mode
== QImode
2643 ? gen_aligned_loadqi
2644 : gen_aligned_loadhi
)
2645 (operands
[0], aligned_mem
, bitnum
, scratch
));
2650 /* Don't pass these as parameters since that makes the generated
2651 code depend on parameter evaluation order which will cause
2652 bootstrap failures. */
2654 rtx temp1
= gen_reg_rtx (DImode
);
2655 rtx temp2
= gen_reg_rtx (DImode
);
2656 rtx seq
= ((mode
== QImode
2657 ? gen_unaligned_loadqi
2658 : gen_unaligned_loadhi
)
2659 (operands
[0], get_unaligned_address (operands
[1], 0),
2662 alpha_set_memflags (seq
, operands
[1]);
2668 if (GET_CODE (operands
[0]) == MEM
2669 || (GET_CODE (operands
[0]) == SUBREG
2670 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
2671 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
2672 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
2673 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
2674 && GET_CODE (SUBREG_REG (operands
[0])) == REG
2675 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
2677 if (aligned_memory_operand (operands
[0], mode
))
2679 rtx aligned_mem
, bitnum
;
2680 rtx temp1
= gen_reg_rtx (SImode
);
2681 rtx temp2
= gen_reg_rtx (SImode
);
2683 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
2685 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
2690 rtx temp1
= gen_reg_rtx (DImode
);
2691 rtx temp2
= gen_reg_rtx (DImode
);
2692 rtx temp3
= gen_reg_rtx (DImode
);
2693 rtx seq
= ((mode
== QImode
2694 ? gen_unaligned_storeqi
2695 : gen_unaligned_storehi
)
2696 (get_unaligned_address (operands
[0], 0),
2697 operands
[1], temp1
, temp2
, temp3
));
2699 alpha_set_memflags (seq
, operands
[0]);
2708 /* Generate an unsigned DImode to FP conversion. This is the same code
2709 optabs would emit if we didn't have TFmode patterns.
2711 For SFmode, this is the only construction I've found that can pass
2712 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2713 intermediates will work, because you'll get intermediate rounding
2714 that ruins the end result. Some of this could be fixed by turning
2715 on round-to-positive-infinity, but that requires diddling the fpsr,
2716 which kills performance. I tried turning this around and converting
2717 to a negative number, so that I could turn on /m, but either I did
2718 it wrong or there's something else cause I wound up with the exact
2719 same single-bit error. There is a branch-less form of this same code:
2730 fcmoveq $f10,$f11,$f0
2732 I'm not using it because it's the same number of instructions as
2733 this branch-full form, and it has more serialized long latency
2734 instructions on the critical path.
2736 For DFmode, we can avoid rounding errors by breaking up the word
2737 into two pieces, converting them separately, and adding them back:
2739 LC0: .long 0,0x5f800000
2744 cpyse $f11,$f31,$f10
2745 cpyse $f31,$f11,$f11
2753 This doesn't seem to be a clear-cut win over the optabs form.
2754 It probably all depends on the distribution of numbers being
2755 converted -- in the optabs form, all but high-bit-set has a
2756 much lower minimum execution time. */
2759 alpha_emit_floatuns (operands
)
2762 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
2763 enum machine_mode mode
;
2766 in
= force_reg (DImode
, operands
[1]);
2767 mode
= GET_MODE (out
);
2768 neglab
= gen_label_rtx ();
2769 donelab
= gen_label_rtx ();
2770 i0
= gen_reg_rtx (DImode
);
2771 i1
= gen_reg_rtx (DImode
);
2772 f0
= gen_reg_rtx (mode
);
2774 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
2776 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
2777 emit_jump_insn (gen_jump (donelab
));
2780 emit_label (neglab
);
2782 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
2783 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
2784 emit_insn (gen_iordi3 (i0
, i0
, i1
));
2785 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
2786 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
2788 emit_label (donelab
);
2791 /* Generate the comparison for a conditional branch. */
2794 alpha_emit_conditional_branch (code
)
2797 enum rtx_code cmp_code
, branch_code
;
2798 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
2799 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
2802 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
2804 if (! TARGET_HAS_XFLOATING_LIBS
)
2807 /* X_floating library comparison functions return
2811 Convert the compare against the raw return value. */
2813 if (code
== UNORDERED
|| code
== ORDERED
)
2818 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
2820 alpha_compare
.fp_p
= 0;
2822 if (code
== UNORDERED
)
2824 else if (code
== ORDERED
)
2830 /* The general case: fold the comparison code to the types of compares
2831 that we have, choosing the branch as necessary. */
2834 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2836 /* We have these compares: */
2837 cmp_code
= code
, branch_code
= NE
;
2842 /* These must be reversed. */
2843 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
2846 case GE
: case GT
: case GEU
: case GTU
:
2847 /* For FP, we swap them, for INT, we reverse them. */
2848 if (alpha_compare
.fp_p
)
2850 cmp_code
= swap_condition (code
);
2852 tem
= op0
, op0
= op1
, op1
= tem
;
2856 cmp_code
= reverse_condition (code
);
2865 if (alpha_compare
.fp_p
)
2868 if (flag_unsafe_math_optimizations
)
2870 /* When we are not as concerned about non-finite values, and we
2871 are comparing against zero, we can branch directly. */
2872 if (op1
== CONST0_RTX (DFmode
))
2873 cmp_code
= NIL
, branch_code
= code
;
2874 else if (op0
== CONST0_RTX (DFmode
))
2876 /* Undo the swap we probably did just above. */
2877 tem
= op0
, op0
= op1
, op1
= tem
;
2878 branch_code
= swap_condition (cmp_code
);
2884 /* ??? We mark the the branch mode to be CCmode to prevent the
2885 compare and branch from being combined, since the compare
2886 insn follows IEEE rules that the branch does not. */
2887 branch_mode
= CCmode
;
2894 /* The following optimizations are only for signed compares. */
2895 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
2897 /* Whee. Compare and branch against 0 directly. */
2898 if (op1
== const0_rtx
)
2899 cmp_code
= NIL
, branch_code
= code
;
2901 /* We want to use cmpcc/bcc when we can, since there is a zero delay
2902 bypass between logicals and br/cmov on EV5. But we don't want to
2903 force valid immediate constants into registers needlessly. */
2904 else if (GET_CODE (op1
) == CONST_INT
)
2906 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
2908 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
2909 && (CONST_OK_FOR_LETTER_P (n
, 'K')
2910 || CONST_OK_FOR_LETTER_P (n
, 'L')))
2912 cmp_code
= PLUS
, branch_code
= code
;
2918 if (!reg_or_0_operand (op0
, DImode
))
2919 op0
= force_reg (DImode
, op0
);
2920 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
2921 op1
= force_reg (DImode
, op1
);
2924 /* Emit an initial compare instruction, if necessary. */
2926 if (cmp_code
!= NIL
)
2928 tem
= gen_reg_rtx (cmp_mode
);
2929 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
2932 /* Zero the operands. */
2933 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2935 /* Return the branch comparison. */
2936 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
2939 /* Certain simplifications can be done to make invalid setcc operations
2940 valid. Return the final comparison, or NULL if we can't work. */
2943 alpha_emit_setcc (code
)
2946 enum rtx_code cmp_code
;
2947 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
2948 int fp_p
= alpha_compare
.fp_p
;
2951 /* Zero the operands. */
2952 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2954 if (fp_p
&& GET_MODE (op0
) == TFmode
)
2956 if (! TARGET_HAS_XFLOATING_LIBS
)
2959 /* X_floating library comparison functions return
2963 Convert the compare against the raw return value. */
2965 if (code
== UNORDERED
|| code
== ORDERED
)
2970 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
2974 if (code
== UNORDERED
)
2976 else if (code
== ORDERED
)
2982 if (fp_p
&& !TARGET_FIX
)
2985 /* The general case: fold the comparison code to the types of compares
2986 that we have, choosing the branch as necessary. */
2991 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2993 /* We have these compares. */
2995 cmp_code
= code
, code
= NE
;
2999 if (!fp_p
&& op1
== const0_rtx
)
3004 cmp_code
= reverse_condition (code
);
3008 case GE
: case GT
: case GEU
: case GTU
:
3009 /* These normally need swapping, but for integer zero we have
3010 special patterns that recognize swapped operands. */
3011 if (!fp_p
&& op1
== const0_rtx
)
3013 code
= swap_condition (code
);
3015 cmp_code
= code
, code
= NE
;
3016 tmp
= op0
, op0
= op1
, op1
= tmp
;
3025 if (!register_operand (op0
, DImode
))
3026 op0
= force_reg (DImode
, op0
);
3027 if (!reg_or_8bit_operand (op1
, DImode
))
3028 op1
= force_reg (DImode
, op1
);
3031 /* Emit an initial compare instruction, if necessary. */
3032 if (cmp_code
!= NIL
)
3034 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
3036 tmp
= gen_reg_rtx (mode
);
3037 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
3038 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
3040 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
3044 /* Return the setcc comparison. */
3045 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
3049 /* Rewrite a comparison against zero CMP of the form
3050 (CODE (cc0) (const_int 0)) so it can be written validly in
3051 a conditional move (if_then_else CMP ...).
3052 If both of the operands that set cc0 are non-zero we must emit
3053 an insn to perform the compare (it can't be done within
3054 the conditional move). */
3056 alpha_emit_conditional_move (cmp
, mode
)
3058 enum machine_mode mode
;
3060 enum rtx_code code
= GET_CODE (cmp
);
3061 enum rtx_code cmov_code
= NE
;
3062 rtx op0
= alpha_compare
.op0
;
3063 rtx op1
= alpha_compare
.op1
;
3064 int fp_p
= alpha_compare
.fp_p
;
3065 enum machine_mode cmp_mode
3066 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
3067 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
3068 enum machine_mode cmov_mode
= VOIDmode
;
3069 int local_fast_math
= flag_unsafe_math_optimizations
;
3072 /* Zero the operands. */
3073 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3075 if (fp_p
!= FLOAT_MODE_P (mode
))
3077 enum rtx_code cmp_code
;
3082 /* If we have fp<->int register move instructions, do a cmov by
3083 performing the comparison in fp registers, and move the
3084 zero/non-zero value to integer registers, where we can then
3085 use a normal cmov, or vice-versa. */
3089 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3090 /* We have these compares. */
3091 cmp_code
= code
, code
= NE
;
3095 /* This must be reversed. */
3096 cmp_code
= EQ
, code
= EQ
;
3099 case GE
: case GT
: case GEU
: case GTU
:
3100 /* These normally need swapping, but for integer zero we have
3101 special patterns that recognize swapped operands. */
3102 if (!fp_p
&& op1
== const0_rtx
)
3103 cmp_code
= code
, code
= NE
;
3106 cmp_code
= swap_condition (code
);
3108 tem
= op0
, op0
= op1
, op1
= tem
;
3116 tem
= gen_reg_rtx (cmp_op_mode
);
3117 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
3118 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
3121 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
3122 op0
= gen_lowpart (cmp_op_mode
, tem
);
3123 op1
= CONST0_RTX (cmp_op_mode
);
3125 local_fast_math
= 1;
3128 /* We may be able to use a conditional move directly.
3129 This avoids emitting spurious compares. */
3130 if (signed_comparison_operator (cmp
, VOIDmode
)
3131 && (!fp_p
|| local_fast_math
)
3132 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
3133 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3135 /* We can't put the comparison inside the conditional move;
3136 emit a compare instruction and put that inside the
3137 conditional move. Make sure we emit only comparisons we have;
3138 swap or reverse as necessary. */
3145 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3146 /* We have these compares: */
3150 /* This must be reversed. */
3151 code
= reverse_condition (code
);
3155 case GE
: case GT
: case GEU
: case GTU
:
3156 /* These must be swapped. */
3157 if (op1
!= CONST0_RTX (cmp_mode
))
3159 code
= swap_condition (code
);
3160 tem
= op0
, op0
= op1
, op1
= tem
;
3170 if (!reg_or_0_operand (op0
, DImode
))
3171 op0
= force_reg (DImode
, op0
);
3172 if (!reg_or_8bit_operand (op1
, DImode
))
3173 op1
= force_reg (DImode
, op1
);
3176 /* ??? We mark the branch mode to be CCmode to prevent the compare
3177 and cmov from being combined, since the compare insn follows IEEE
3178 rules that the cmov does not. */
3179 if (fp_p
&& !local_fast_math
)
3182 tem
= gen_reg_rtx (cmp_op_mode
);
3183 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
3184 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
3187 /* Simplify a conditional move of two constants into a setcc with
3188 arithmetic. This is done with a splitter since combine would
3189 just undo the work if done during code generation. It also catches
3190 cases we wouldn't have before cse. */
3193 alpha_split_conditional_move (code
, dest
, cond
, t_rtx
, f_rtx
)
3195 rtx dest
, cond
, t_rtx
, f_rtx
;
3197 HOST_WIDE_INT t
, f
, diff
;
3198 enum machine_mode mode
;
3199 rtx target
, subtarget
, tmp
;
3201 mode
= GET_MODE (dest
);
3206 if (((code
== NE
|| code
== EQ
) && diff
< 0)
3207 || (code
== GE
|| code
== GT
))
3209 code
= reverse_condition (code
);
3210 diff
= t
, t
= f
, f
= diff
;
3214 subtarget
= target
= dest
;
3217 target
= gen_lowpart (DImode
, dest
);
3218 if (! no_new_pseudos
)
3219 subtarget
= gen_reg_rtx (DImode
);
3223 /* Below, we must be careful to use copy_rtx on target and subtarget
3224 in intermediate insns, as they may be a subreg rtx, which may not
3227 if (f
== 0 && exact_log2 (diff
) > 0
3228 /* On EV6, we've got enough shifters to make non-arithmatic shifts
3229 viable over a longer latency cmove. On EV5, the E0 slot is a
3230 scarce resource, and on EV4 shift has the same latency as a cmove. */
3231 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
3233 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3234 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3236 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
3237 GEN_INT (exact_log2 (t
)));
3238 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3240 else if (f
== 0 && t
== -1)
3242 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3243 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3245 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
3247 else if (diff
== 1 || diff
== 4 || diff
== 8)
3251 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3252 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3255 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
3258 add_op
= GEN_INT (f
);
3259 if (sext_add_operand (add_op
, mode
))
3261 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
3263 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
3264 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3276 /* Look up the function X_floating library function name for the
3280 alpha_lookup_xfloating_lib_func (code
)
3285 const enum rtx_code code
;
3286 const char *const func
;
3289 static const struct xfloating_op vms_xfloating_ops
[] =
3291 { PLUS
, "OTS$ADD_X" },
3292 { MINUS
, "OTS$SUB_X" },
3293 { MULT
, "OTS$MUL_X" },
3294 { DIV
, "OTS$DIV_X" },
3295 { EQ
, "OTS$EQL_X" },
3296 { NE
, "OTS$NEQ_X" },
3297 { LT
, "OTS$LSS_X" },
3298 { LE
, "OTS$LEQ_X" },
3299 { GT
, "OTS$GTR_X" },
3300 { GE
, "OTS$GEQ_X" },
3301 { FIX
, "OTS$CVTXQ" },
3302 { FLOAT
, "OTS$CVTQX" },
3303 { UNSIGNED_FLOAT
, "OTS$CVTQUX" },
3304 { FLOAT_EXTEND
, "OTS$CVT_FLOAT_T_X" },
3305 { FLOAT_TRUNCATE
, "OTS$CVT_FLOAT_X_T" },
3308 static const struct xfloating_op osf_xfloating_ops
[] =
3310 { PLUS
, "_OtsAddX" },
3311 { MINUS
, "_OtsSubX" },
3312 { MULT
, "_OtsMulX" },
3313 { DIV
, "_OtsDivX" },
3320 { FIX
, "_OtsCvtXQ" },
3321 { FLOAT
, "_OtsCvtQX" },
3322 { UNSIGNED_FLOAT
, "_OtsCvtQUX" },
3323 { FLOAT_EXTEND
, "_OtsConvertFloatTX" },
3324 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT" },
3327 const struct xfloating_op
*ops
;
3328 const long n
= ARRAY_SIZE (osf_xfloating_ops
);
3331 /* How irritating. Nothing to key off for the table. Hardcode
3332 knowledge of the G_floating routines. */
3333 if (TARGET_FLOAT_VAX
)
3335 if (TARGET_ABI_OPEN_VMS
)
3337 if (code
== FLOAT_EXTEND
)
3338 return "OTS$CVT_FLOAT_G_X";
3339 if (code
== FLOAT_TRUNCATE
)
3340 return "OTS$CVT_FLOAT_X_G";
3344 if (code
== FLOAT_EXTEND
)
3345 return "_OtsConvertFloatGX";
3346 if (code
== FLOAT_TRUNCATE
)
3347 return "_OtsConvertFloatXG";
3351 if (TARGET_ABI_OPEN_VMS
)
3352 ops
= vms_xfloating_ops
;
3354 ops
= osf_xfloating_ops
;
3356 for (i
= 0; i
< n
; ++i
)
3357 if (ops
[i
].code
== code
)
3363 /* Most X_floating operations take the rounding mode as an argument.
3364 Compute that here. */
3367 alpha_compute_xfloating_mode_arg (code
, round
)
3369 enum alpha_fp_rounding_mode round
;
3375 case ALPHA_FPRM_NORM
:
3378 case ALPHA_FPRM_MINF
:
3381 case ALPHA_FPRM_CHOP
:
3384 case ALPHA_FPRM_DYN
:
3390 /* XXX For reference, round to +inf is mode = 3. */
3393 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3399 /* Emit an X_floating library function call.
3401 Note that these functions do not follow normal calling conventions:
3402 TFmode arguments are passed in two integer registers (as opposed to
3403 indirect); TFmode return values appear in R16+R17.
3405 FUNC is the function name to call.
3406 TARGET is where the output belongs.
3407 OPERANDS are the inputs.
3408 NOPERANDS is the count of inputs.
3409 EQUIV is the expression equivalent for the function.
3413 alpha_emit_xfloating_libcall (func
, target
, operands
, noperands
, equiv
)
3420 rtx usage
= NULL_RTX
, tmp
, reg
;
3425 for (i
= 0; i
< noperands
; ++i
)
3427 switch (GET_MODE (operands
[i
]))
3430 reg
= gen_rtx_REG (TFmode
, regno
);
3435 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3440 if (GET_CODE (operands
[i
]) != CONST_INT
)
3444 reg
= gen_rtx_REG (DImode
, regno
);
3452 emit_move_insn (reg
, operands
[i
]);
3453 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3456 switch (GET_MODE (target
))
3459 reg
= gen_rtx_REG (TFmode
, 16);
3462 reg
= gen_rtx_REG (DFmode
, 32);
3465 reg
= gen_rtx_REG (DImode
, 0);
3471 tmp
= gen_rtx_MEM (QImode
, gen_rtx_SYMBOL_REF (Pmode
, (char *) func
));
3472 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3473 const0_rtx
, const0_rtx
));
3474 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3479 emit_libcall_block (tmp
, target
, reg
, equiv
);
3482 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3485 alpha_emit_xfloating_arith (code
, operands
)
3491 rtx out_operands
[3];
3493 func
= alpha_lookup_xfloating_lib_func (code
);
3494 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3496 out_operands
[0] = operands
[1];
3497 out_operands
[1] = operands
[2];
3498 out_operands
[2] = GEN_INT (mode
);
3499 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
3500 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
3504 /* Emit an X_floating library function call for a comparison. */
3507 alpha_emit_xfloating_compare (code
, op0
, op1
)
3512 rtx out
, operands
[2];
3514 func
= alpha_lookup_xfloating_lib_func (code
);
3518 out
= gen_reg_rtx (DImode
);
3520 /* ??? Strange mode for equiv because what's actually returned
3521 is -1,0,1, not a proper boolean value. */
3522 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
3523 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
3528 /* Emit an X_floating library function call for a conversion. */
3531 alpha_emit_xfloating_cvt (code
, operands
)
3535 int noperands
= 1, mode
;
3536 rtx out_operands
[2];
3539 func
= alpha_lookup_xfloating_lib_func (code
);
3541 out_operands
[0] = operands
[1];
3546 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3547 out_operands
[1] = GEN_INT (mode
);
3550 case FLOAT_TRUNCATE
:
3551 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3552 out_operands
[1] = GEN_INT (mode
);
3559 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3560 gen_rtx_fmt_e (code
, GET_MODE (operands
[0]),
3564 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3565 OP[0] into OP[0,1]. Naturally, output operand ordering is
3569 alpha_split_tfmode_pair (operands
)
3572 if (GET_CODE (operands
[1]) == REG
)
3574 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
3575 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
3577 else if (GET_CODE (operands
[1]) == MEM
)
3579 operands
[3] = adjust_address (operands
[1], DImode
, 8);
3580 operands
[2] = adjust_address (operands
[1], DImode
, 0);
3582 else if (operands
[1] == CONST0_RTX (TFmode
))
3583 operands
[2] = operands
[3] = const0_rtx
;
3587 if (GET_CODE (operands
[0]) == REG
)
3589 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
3590 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
3592 else if (GET_CODE (operands
[0]) == MEM
)
3594 operands
[1] = adjust_address (operands
[0], DImode
, 8);
3595 operands
[0] = adjust_address (operands
[0], DImode
, 0);
3601 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3602 op2 is a register containing the sign bit, operation is the
3603 logical operation to be performed. */
3606 alpha_split_tfmode_frobsign (operands
, operation
)
3608 rtx (*operation
) PARAMS ((rtx
, rtx
, rtx
));
3610 rtx high_bit
= operands
[2];
3614 alpha_split_tfmode_pair (operands
);
3616 /* Detect three flavours of operand overlap. */
3618 if (rtx_equal_p (operands
[0], operands
[2]))
3620 else if (rtx_equal_p (operands
[1], operands
[2]))
3622 if (rtx_equal_p (operands
[0], high_bit
))
3629 emit_move_insn (operands
[0], operands
[2]);
3631 /* ??? If the destination overlaps both source tf and high_bit, then
3632 assume source tf is dead in its entirety and use the other half
3633 for a scratch register. Otherwise "scratch" is just the proper
3634 destination register. */
3635 scratch
= operands
[move
< 2 ? 1 : 3];
3637 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
3641 emit_move_insn (operands
[0], operands
[2]);
3643 emit_move_insn (operands
[1], scratch
);
3647 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3651 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3652 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3653 lda r3,X(r11) lda r3,X+2(r11)
3654 extwl r1,r3,r1 extql r1,r3,r1
3655 extwh r2,r3,r2 extqh r2,r3,r2
3656 or r1.r2.r1 or r1,r2,r1
3659 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3660 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3661 lda r3,X(r11) lda r3,X(r11)
3662 extll r1,r3,r1 extll r1,r3,r1
3663 extlh r2,r3,r2 extlh r2,r3,r2
3664 or r1.r2.r1 addl r1,r2,r1
3666 quad: ldq_u r1,X(r11)
3675 alpha_expand_unaligned_load (tgt
, mem
, size
, ofs
, sign
)
3677 HOST_WIDE_INT size
, ofs
;
3680 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
3681 enum machine_mode mode
;
3683 meml
= gen_reg_rtx (DImode
);
3684 memh
= gen_reg_rtx (DImode
);
3685 addr
= gen_reg_rtx (DImode
);
3686 extl
= gen_reg_rtx (DImode
);
3687 exth
= gen_reg_rtx (DImode
);
3689 mema
= XEXP (mem
, 0);
3690 if (GET_CODE (mema
) == LO_SUM
)
3691 mema
= force_reg (Pmode
, mema
);
3693 /* AND addresses cannot be in any alias set, since they may implicitly
3694 alias surrounding code. Ideally we'd have some alias set that
3695 covered all types except those with alignment 8 or higher. */
3697 tmp
= change_address (mem
, DImode
,
3698 gen_rtx_AND (DImode
,
3699 plus_constant (mema
, ofs
),
3701 set_mem_alias_set (tmp
, 0);
3702 emit_move_insn (meml
, tmp
);
3704 tmp
= change_address (mem
, DImode
,
3705 gen_rtx_AND (DImode
,
3706 plus_constant (mema
, ofs
+ size
- 1),
3708 set_mem_alias_set (tmp
, 0);
3709 emit_move_insn (memh
, tmp
);
3711 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
3713 emit_move_insn (addr
, plus_constant (mema
, -1));
3715 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3716 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
3718 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3719 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
3720 addr
, 1, OPTAB_WIDEN
);
3722 else if (sign
&& size
== 2)
3724 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
3726 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
3727 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3729 /* We must use tgt here for the target. Alpha-vms port fails if we use
3730 addr for the target, because addr is marked as a pointer and combine
3731 knows that pointers are always sign-extended 32 bit values. */
3732 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3733 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
3734 addr
, 1, OPTAB_WIDEN
);
3738 if (WORDS_BIG_ENDIAN
)
3740 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
3744 emit_insn (gen_extwh_be (extl
, meml
, addr
));
3749 emit_insn (gen_extlh_be (extl
, meml
, addr
));
3754 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3761 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
3765 emit_move_insn (addr
, plus_constant (mema
, ofs
));
3766 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
3770 emit_insn (gen_extwh_le (exth
, memh
, addr
));
3775 emit_insn (gen_extlh_le (exth
, memh
, addr
));
3780 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3789 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
3790 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
3795 emit_move_insn (tgt
, gen_lowpart(GET_MODE (tgt
), addr
));
3798 /* Similarly, use ins and msk instructions to perform unaligned stores. */
3801 alpha_expand_unaligned_store (dst
, src
, size
, ofs
)
3803 HOST_WIDE_INT size
, ofs
;
3805 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
3807 dstl
= gen_reg_rtx (DImode
);
3808 dsth
= gen_reg_rtx (DImode
);
3809 insl
= gen_reg_rtx (DImode
);
3810 insh
= gen_reg_rtx (DImode
);
3812 dsta
= XEXP (dst
, 0);
3813 if (GET_CODE (dsta
) == LO_SUM
)
3814 dsta
= force_reg (Pmode
, dsta
);
3816 /* AND addresses cannot be in any alias set, since they may implicitly
3817 alias surrounding code. Ideally we'd have some alias set that
3818 covered all types except those with alignment 8 or higher. */
3820 meml
= change_address (dst
, DImode
,
3821 gen_rtx_AND (DImode
,
3822 plus_constant (dsta
, ofs
),
3824 set_mem_alias_set (meml
, 0);
3826 memh
= change_address (dst
, DImode
,
3827 gen_rtx_AND (DImode
,
3828 plus_constant (dsta
, ofs
+ size
- 1),
3830 set_mem_alias_set (memh
, 0);
3832 emit_move_insn (dsth
, memh
);
3833 emit_move_insn (dstl
, meml
);
3834 if (WORDS_BIG_ENDIAN
)
3836 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
3838 if (src
!= const0_rtx
)
3843 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
3846 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
3849 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
3852 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
3853 GEN_INT (size
*8), addr
));
3859 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
3862 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffffffff), addr
));
3866 #if HOST_BITS_PER_WIDE_INT == 32
3867 rtx msk
= immed_double_const (0xffffffff, 0xffffffff, DImode
);
3869 rtx msk
= constm1_rtx
;
3871 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
3876 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
3880 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
3882 if (src
!= const0_rtx
)
3884 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
3885 GEN_INT (size
*8), addr
));
3890 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
3893 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
3896 emit_insn (gen_insql_le (insl
, src
, addr
));
3901 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
3906 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
3909 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffffffff), addr
));
3913 #if HOST_BITS_PER_WIDE_INT == 32
3914 rtx msk
= immed_double_const (0xffffffff, 0xffffffff, DImode
);
3916 rtx msk
= constm1_rtx
;
3918 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
3924 if (src
!= const0_rtx
)
3926 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
3927 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
3930 if (WORDS_BIG_ENDIAN
)
3932 emit_move_insn (meml
, dstl
);
3933 emit_move_insn (memh
, dsth
);
3937 /* Must store high before low for degenerate case of aligned. */
3938 emit_move_insn (memh
, dsth
);
3939 emit_move_insn (meml
, dstl
);
3943 /* The block move code tries to maximize speed by separating loads and
3944 stores at the expense of register pressure: we load all of the data
3945 before we store it back out. There are two secondary effects worth
3946 mentioning, that this speeds copying to/from aligned and unaligned
3947 buffers, and that it makes the code significantly easier to write. */
3949 #define MAX_MOVE_WORDS 8
3951 /* Load an integral number of consecutive unaligned quadwords. */
3954 alpha_expand_unaligned_load_words (out_regs
, smem
, words
, ofs
)
3957 HOST_WIDE_INT words
, ofs
;
3959 rtx
const im8
= GEN_INT (-8);
3960 rtx
const i64
= GEN_INT (64);
3961 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
3962 rtx sreg
, areg
, tmp
, smema
;
3965 smema
= XEXP (smem
, 0);
3966 if (GET_CODE (smema
) == LO_SUM
)
3967 smema
= force_reg (Pmode
, smema
);
3969 /* Generate all the tmp registers we need. */
3970 for (i
= 0; i
< words
; ++i
)
3972 data_regs
[i
] = out_regs
[i
];
3973 ext_tmps
[i
] = gen_reg_rtx (DImode
);
3975 data_regs
[words
] = gen_reg_rtx (DImode
);
3978 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
3980 /* Load up all of the source data. */
3981 for (i
= 0; i
< words
; ++i
)
3983 tmp
= change_address (smem
, DImode
,
3984 gen_rtx_AND (DImode
,
3985 plus_constant (smema
, 8*i
),
3987 set_mem_alias_set (tmp
, 0);
3988 emit_move_insn (data_regs
[i
], tmp
);
3991 tmp
= change_address (smem
, DImode
,
3992 gen_rtx_AND (DImode
,
3993 plus_constant (smema
, 8*words
- 1),
3995 set_mem_alias_set (tmp
, 0);
3996 emit_move_insn (data_regs
[words
], tmp
);
3998 /* Extract the half-word fragments. Unfortunately DEC decided to make
3999 extxh with offset zero a noop instead of zeroing the register, so
4000 we must take care of that edge condition ourselves with cmov. */
4002 sreg
= copy_addr_to_reg (smema
);
4003 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
4005 if (WORDS_BIG_ENDIAN
)
4006 emit_move_insn (sreg
, plus_constant (sreg
, 7));
4007 for (i
= 0; i
< words
; ++i
)
4009 if (WORDS_BIG_ENDIAN
)
4011 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
4012 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
4016 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
4017 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
4019 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
4020 gen_rtx_IF_THEN_ELSE (DImode
,
4021 gen_rtx_EQ (DImode
, areg
,
4023 const0_rtx
, ext_tmps
[i
])));
4026 /* Merge the half-words into whole words. */
4027 for (i
= 0; i
< words
; ++i
)
4029 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4030 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
4034 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4035 may be NULL to store zeros. */
4038 alpha_expand_unaligned_store_words (data_regs
, dmem
, words
, ofs
)
4041 HOST_WIDE_INT words
, ofs
;
4043 rtx
const im8
= GEN_INT (-8);
4044 rtx
const i64
= GEN_INT (64);
4045 #if HOST_BITS_PER_WIDE_INT == 32
4046 rtx
const im1
= immed_double_const (0xffffffff, 0xffffffff, DImode
);
4048 rtx
const im1
= constm1_rtx
;
4050 rtx ins_tmps
[MAX_MOVE_WORDS
];
4051 rtx st_tmp_1
, st_tmp_2
, dreg
;
4052 rtx st_addr_1
, st_addr_2
, dmema
;
4055 dmema
= XEXP (dmem
, 0);
4056 if (GET_CODE (dmema
) == LO_SUM
)
4057 dmema
= force_reg (Pmode
, dmema
);
4059 /* Generate all the tmp registers we need. */
4060 if (data_regs
!= NULL
)
4061 for (i
= 0; i
< words
; ++i
)
4062 ins_tmps
[i
] = gen_reg_rtx(DImode
);
4063 st_tmp_1
= gen_reg_rtx(DImode
);
4064 st_tmp_2
= gen_reg_rtx(DImode
);
4067 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
4069 st_addr_2
= change_address (dmem
, DImode
,
4070 gen_rtx_AND (DImode
,
4071 plus_constant (dmema
, words
*8 - 1),
4073 set_mem_alias_set (st_addr_2
, 0);
4075 st_addr_1
= change_address (dmem
, DImode
,
4076 gen_rtx_AND (DImode
, dmema
, im8
));
4077 set_mem_alias_set (st_addr_1
, 0);
4079 /* Load up the destination end bits. */
4080 emit_move_insn (st_tmp_2
, st_addr_2
);
4081 emit_move_insn (st_tmp_1
, st_addr_1
);
4083 /* Shift the input data into place. */
4084 dreg
= copy_addr_to_reg (dmema
);
4085 if (WORDS_BIG_ENDIAN
)
4086 emit_move_insn (dreg
, plus_constant (dreg
, 7));
4087 if (data_regs
!= NULL
)
4089 for (i
= words
-1; i
>= 0; --i
)
4091 if (WORDS_BIG_ENDIAN
)
4093 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
4094 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
4098 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
4099 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
4102 for (i
= words
-1; i
> 0; --i
)
4104 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4105 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
4110 /* Split and merge the ends with the destination data. */
4111 if (WORDS_BIG_ENDIAN
)
4113 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, im1
, dreg
));
4114 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
4118 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
4119 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, im1
, dreg
));
4122 if (data_regs
!= NULL
)
4124 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
4125 st_tmp_2
, 1, OPTAB_WIDEN
);
4126 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
4127 st_tmp_1
, 1, OPTAB_WIDEN
);
4131 if (WORDS_BIG_ENDIAN
)
4132 emit_move_insn (st_addr_1
, st_tmp_1
);
4134 emit_move_insn (st_addr_2
, st_tmp_2
);
4135 for (i
= words
-1; i
> 0; --i
)
4137 rtx tmp
= change_address (dmem
, DImode
,
4138 gen_rtx_AND (DImode
,
4139 plus_constant(dmema
,
4140 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
4142 set_mem_alias_set (tmp
, 0);
4143 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
4145 if (WORDS_BIG_ENDIAN
)
4146 emit_move_insn (st_addr_2
, st_tmp_2
);
4148 emit_move_insn (st_addr_1
, st_tmp_1
);
4152 /* Expand string/block move operations.
4154 operands[0] is the pointer to the destination.
4155 operands[1] is the pointer to the source.
4156 operands[2] is the number of bytes to move.
4157 operands[3] is the alignment. */
4160 alpha_expand_block_move (operands
)
4163 rtx bytes_rtx
= operands
[2];
4164 rtx align_rtx
= operands
[3];
4165 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4166 HOST_WIDE_INT bytes
= orig_bytes
;
4167 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4168 HOST_WIDE_INT dst_align
= src_align
;
4169 rtx orig_src
= operands
[1];
4170 rtx orig_dst
= operands
[0];
4171 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
4173 unsigned int i
, words
, ofs
, nregs
= 0;
4175 if (orig_bytes
<= 0)
4177 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4180 /* Look for additional alignment information from recorded register info. */
4182 tmp
= XEXP (orig_src
, 0);
4183 if (GET_CODE (tmp
) == REG
)
4184 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4185 else if (GET_CODE (tmp
) == PLUS
4186 && GET_CODE (XEXP (tmp
, 0)) == REG
4187 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4189 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4190 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4194 if (a
>= 64 && c
% 8 == 0)
4196 else if (a
>= 32 && c
% 4 == 0)
4198 else if (a
>= 16 && c
% 2 == 0)
4203 tmp
= XEXP (orig_dst
, 0);
4204 if (GET_CODE (tmp
) == REG
)
4205 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4206 else if (GET_CODE (tmp
) == PLUS
4207 && GET_CODE (XEXP (tmp
, 0)) == REG
4208 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4210 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4211 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4215 if (a
>= 64 && c
% 8 == 0)
4217 else if (a
>= 32 && c
% 4 == 0)
4219 else if (a
>= 16 && c
% 2 == 0)
4224 /* Load the entire block into registers. */
4225 if (GET_CODE (XEXP (orig_src
, 0)) == ADDRESSOF
)
4227 enum machine_mode mode
;
4229 tmp
= XEXP (XEXP (orig_src
, 0), 0);
4231 /* Don't use the existing register if we're reading more than
4232 is held in the register. Nor if there is not a mode that
4233 handles the exact size. */
4234 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4236 && GET_MODE_SIZE (GET_MODE (tmp
)) >= bytes
)
4240 data_regs
[nregs
] = gen_lowpart (DImode
, tmp
);
4241 data_regs
[nregs
+ 1] = gen_highpart (DImode
, tmp
);
4245 data_regs
[nregs
++] = gen_lowpart (mode
, tmp
);
4250 /* No appropriate mode; fall back on memory. */
4251 orig_src
= replace_equiv_address (orig_src
,
4252 copy_addr_to_reg (XEXP (orig_src
, 0)));
4253 src_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4257 if (src_align
>= 64 && bytes
>= 8)
4261 for (i
= 0; i
< words
; ++i
)
4262 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4264 for (i
= 0; i
< words
; ++i
)
4265 emit_move_insn (data_regs
[nregs
+ i
],
4266 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
4273 if (src_align
>= 32 && bytes
>= 4)
4277 for (i
= 0; i
< words
; ++i
)
4278 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
4280 for (i
= 0; i
< words
; ++i
)
4281 emit_move_insn (data_regs
[nregs
+ i
],
4282 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
4293 for (i
= 0; i
< words
+1; ++i
)
4294 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4296 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
4304 if (! TARGET_BWX
&& bytes
>= 4)
4306 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
4307 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
4314 if (src_align
>= 16)
4317 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4318 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
4321 } while (bytes
>= 2);
4323 else if (! TARGET_BWX
)
4325 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4326 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
4334 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
4335 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
4342 if (nregs
> ARRAY_SIZE (data_regs
))
4345 /* Now save it back out again. */
4349 if (GET_CODE (XEXP (orig_dst
, 0)) == ADDRESSOF
)
4351 enum machine_mode mode
;
4352 tmp
= XEXP (XEXP (orig_dst
, 0), 0);
4354 mode
= mode_for_size (orig_bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4355 if (GET_MODE (tmp
) == mode
)
4359 emit_move_insn (tmp
, data_regs
[0]);
4364 else if (nregs
== 2 && mode
== TImode
)
4366 /* Undo the subregging done above when copying between
4367 two TImode registers. */
4368 if (GET_CODE (data_regs
[0]) == SUBREG
4369 && GET_MODE (SUBREG_REG (data_regs
[0])) == TImode
)
4370 emit_move_insn (tmp
, SUBREG_REG (data_regs
[0]));
4376 emit_move_insn (gen_lowpart (DImode
, tmp
), data_regs
[0]);
4377 emit_move_insn (gen_highpart (DImode
, tmp
), data_regs
[1]);
4381 emit_no_conflict_block (seq
, tmp
, data_regs
[0],
4382 data_regs
[1], NULL_RTX
);
4390 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4391 /* ??? Optimize mode < dst_mode with strict_low_part. */
4393 /* No appropriate mode; fall back on memory. We can speed things
4394 up by recognizing extra alignment information. */
4395 orig_dst
= replace_equiv_address (orig_dst
,
4396 copy_addr_to_reg (XEXP (orig_dst
, 0)));
4397 dst_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4400 /* Write out the data in whatever chunks reading the source allowed. */
4401 if (dst_align
>= 64)
4403 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4405 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
4412 if (dst_align
>= 32)
4414 /* If the source has remaining DImode regs, write them out in
4416 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4418 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
4419 NULL_RTX
, 1, OPTAB_WIDEN
);
4421 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4422 gen_lowpart (SImode
, data_regs
[i
]));
4423 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
4424 gen_lowpart (SImode
, tmp
));
4429 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4431 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4438 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4440 /* Write out a remaining block of words using unaligned methods. */
4442 for (words
= 1; i
+ words
< nregs
; words
++)
4443 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4447 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4449 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4456 /* Due to the above, this won't be aligned. */
4457 /* ??? If we have more than one of these, consider constructing full
4458 words in registers and using alpha_expand_unaligned_store_words. */
4459 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4461 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4466 if (dst_align
>= 16)
4467 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4469 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4474 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4476 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4481 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
4483 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4497 alpha_expand_block_clear (operands
)
4500 rtx bytes_rtx
= operands
[1];
4501 rtx align_rtx
= operands
[2];
4502 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4503 HOST_WIDE_INT bytes
= orig_bytes
;
4504 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4505 HOST_WIDE_INT alignofs
= 0;
4506 rtx orig_dst
= operands
[0];
4508 int i
, words
, ofs
= 0;
4510 if (orig_bytes
<= 0)
4512 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4515 /* Look for stricter alignment. */
4516 tmp
= XEXP (orig_dst
, 0);
4517 if (GET_CODE (tmp
) == REG
)
4518 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4519 else if (GET_CODE (tmp
) == PLUS
4520 && GET_CODE (XEXP (tmp
, 0)) == REG
4521 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4523 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4524 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4529 align
= a
, alignofs
= 8 - c
% 8;
4531 align
= a
, alignofs
= 4 - c
% 4;
4533 align
= a
, alignofs
= 2 - c
% 2;
4536 else if (GET_CODE (tmp
) == ADDRESSOF
)
4538 enum machine_mode mode
;
4540 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4541 if (GET_MODE (XEXP (tmp
, 0)) == mode
)
4543 emit_move_insn (XEXP (tmp
, 0), const0_rtx
);
4547 /* No appropriate mode; fall back on memory. */
4548 orig_dst
= replace_equiv_address (orig_dst
, copy_addr_to_reg (tmp
));
4549 align
= GET_MODE_BITSIZE (GET_MODE (XEXP (tmp
, 0)));
4552 /* Handle an unaligned prefix first. */
4556 #if HOST_BITS_PER_WIDE_INT >= 64
4557 /* Given that alignofs is bounded by align, the only time BWX could
4558 generate three stores is for a 7 byte fill. Prefer two individual
4559 stores over a load/mask/store sequence. */
4560 if ((!TARGET_BWX
|| alignofs
== 7)
4562 && !(alignofs
== 4 && bytes
>= 4))
4564 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
4565 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
4569 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
4570 set_mem_alias_set (mem
, 0);
4572 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
4573 if (bytes
< alignofs
)
4575 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
4586 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
4587 NULL_RTX
, 1, OPTAB_WIDEN
);
4589 emit_move_insn (mem
, tmp
);
4593 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
4595 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4600 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
4602 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
4607 if (alignofs
== 4 && bytes
>= 4)
4609 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4615 /* If we've not used the extra lead alignment information by now,
4616 we won't be able to. Downgrade align to match what's left over. */
4619 alignofs
= alignofs
& -alignofs
;
4620 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
4624 /* Handle a block of contiguous long-words. */
4626 if (align
>= 64 && bytes
>= 8)
4630 for (i
= 0; i
< words
; ++i
)
4631 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
4638 /* If the block is large and appropriately aligned, emit a single
4639 store followed by a sequence of stq_u insns. */
4641 if (align
>= 32 && bytes
> 16)
4645 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4649 orig_dsta
= XEXP (orig_dst
, 0);
4650 if (GET_CODE (orig_dsta
) == LO_SUM
)
4651 orig_dsta
= force_reg (Pmode
, orig_dsta
);
4654 for (i
= 0; i
< words
; ++i
)
4657 = change_address (orig_dst
, DImode
,
4658 gen_rtx_AND (DImode
,
4659 plus_constant (orig_dsta
, ofs
+ i
*8),
4661 set_mem_alias_set (mem
, 0);
4662 emit_move_insn (mem
, const0_rtx
);
4665 /* Depending on the alignment, the first stq_u may have overlapped
4666 with the initial stl, which means that the last stq_u didn't
4667 write as much as it would appear. Leave those questionable bytes
4669 bytes
-= words
* 8 - 4;
4670 ofs
+= words
* 8 - 4;
4673 /* Handle a smaller block of aligned words. */
4675 if ((align
>= 64 && bytes
== 4)
4676 || (align
== 32 && bytes
>= 4))
4680 for (i
= 0; i
< words
; ++i
)
4681 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
4688 /* An unaligned block uses stq_u stores for as many as possible. */
4694 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
4700 /* Next clean up any trailing pieces. */
4702 #if HOST_BITS_PER_WIDE_INT >= 64
4703 /* Count the number of bits in BYTES for which aligned stores could
4706 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
4710 /* If we have appropriate alignment (and it wouldn't take too many
4711 instructions otherwise), mask out the bytes we need. */
4712 if (TARGET_BWX
? words
> 2 : bytes
> 0)
4719 mem
= adjust_address (orig_dst
, DImode
, ofs
);
4720 set_mem_alias_set (mem
, 0);
4722 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4724 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
4725 NULL_RTX
, 1, OPTAB_WIDEN
);
4727 emit_move_insn (mem
, tmp
);
4730 else if (align
>= 32 && bytes
< 4)
4735 mem
= adjust_address (orig_dst
, SImode
, ofs
);
4736 set_mem_alias_set (mem
, 0);
4738 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4740 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
4741 NULL_RTX
, 1, OPTAB_WIDEN
);
4743 emit_move_insn (mem
, tmp
);
4749 if (!TARGET_BWX
&& bytes
>= 4)
4751 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
4761 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
4765 } while (bytes
>= 2);
4767 else if (! TARGET_BWX
)
4769 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
4777 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4785 /* Adjust the cost of a scheduling dependency. Return the new cost of
4786 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4789 alpha_adjust_cost (insn
, link
, dep_insn
, cost
)
4796 enum attr_type insn_type
, dep_insn_type
;
4798 /* If the dependence is an anti-dependence, there is no cost. For an
4799 output dependence, there is sometimes a cost, but it doesn't seem
4800 worth handling those few cases. */
4802 if (REG_NOTE_KIND (link
) != 0)
4805 /* If we can't recognize the insns, we can't really do anything. */
4806 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
4809 insn_type
= get_attr_type (insn
);
4810 dep_insn_type
= get_attr_type (dep_insn
);
4812 /* Bring in the user-defined memory latency. */
4813 if (dep_insn_type
== TYPE_ILD
4814 || dep_insn_type
== TYPE_FLD
4815 || dep_insn_type
== TYPE_LDSYM
)
4816 cost
+= alpha_memory_latency
-1;
4821 /* On EV4, if INSN is a store insn and DEP_INSN is setting the data
4822 being stored, we can sometimes lower the cost. */
4824 if ((insn_type
== TYPE_IST
|| insn_type
== TYPE_FST
)
4825 && (set
= single_set (dep_insn
)) != 0
4826 && GET_CODE (PATTERN (insn
)) == SET
4827 && rtx_equal_p (SET_DEST (set
), SET_SRC (PATTERN (insn
))))
4829 switch (dep_insn_type
)
4833 /* No savings here. */
4837 /* In these cases, we save one cycle. */
4841 /* In all other cases, we save two cycles. */
4842 return MAX (0, cost
- 2);
4846 /* Another case that needs adjustment is an arithmetic or logical
4847 operation. It's cost is usually one cycle, but we default it to
4848 two in the MD file. The only case that it is actually two is
4849 for the address in loads, stores, and jumps. */
4851 if (dep_insn_type
== TYPE_IADD
|| dep_insn_type
== TYPE_ILOG
)
4866 /* The final case is when a compare feeds into an integer branch;
4867 the cost is only one cycle in that case. */
4869 if (dep_insn_type
== TYPE_ICMP
&& insn_type
== TYPE_IBR
)
4874 /* And the lord DEC saith: "A special bypass provides an effective
4875 latency of 0 cycles for an ICMP or ILOG insn producing the test
4876 operand of an IBR or ICMOV insn." */
4878 if ((dep_insn_type
== TYPE_ICMP
|| dep_insn_type
== TYPE_ILOG
)
4879 && (set
= single_set (dep_insn
)) != 0)
4881 /* A branch only has one input. This must be it. */
4882 if (insn_type
== TYPE_IBR
)
4884 /* A conditional move has three, make sure it is the test. */
4885 if (insn_type
== TYPE_ICMOV
4886 && GET_CODE (set_src
= PATTERN (insn
)) == SET
4887 && GET_CODE (set_src
= SET_SRC (set_src
)) == IF_THEN_ELSE
4888 && rtx_equal_p (SET_DEST (set
), XEXP (set_src
, 0)))
4892 /* "The multiplier is unable to receive data from IEU bypass paths.
4893 The instruction issues at the expected time, but its latency is
4894 increased by the time it takes for the input data to become
4895 available to the multiplier" -- which happens in pipeline stage
4896 six, when results are comitted to the register file. */
4898 if (insn_type
== TYPE_IMUL
)
4900 switch (dep_insn_type
)
4902 /* These insns produce their results in pipeline stage five. */
4909 /* Other integer insns produce results in pipeline stage four. */
4917 /* There is additional latency to move the result of (most) FP
4918 operations anywhere but the FP register file. */
4920 if ((insn_type
== TYPE_FST
|| insn_type
== TYPE_FTOI
)
4921 && (dep_insn_type
== TYPE_FADD
||
4922 dep_insn_type
== TYPE_FMUL
||
4923 dep_insn_type
== TYPE_FCMOV
))
4929 /* Otherwise, return the default cost. */
4933 /* Function to initialize the issue rate used by the scheduler. */
4937 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
4941 alpha_variable_issue (dump
, verbose
, insn
, cim
)
4942 FILE *dump ATTRIBUTE_UNUSED
;
4943 int verbose ATTRIBUTE_UNUSED
;
4947 if (recog_memoized (insn
) < 0 || get_attr_type (insn
) == TYPE_MULTI
)
4954 /* Register global variables and machine-specific functions with the
4955 garbage collector. */
4957 #if TARGET_ABI_UNICOSMK
4959 alpha_init_machine_status (p
)
4963 (struct machine_function
*) xcalloc (1, sizeof (struct machine_function
));
4965 p
->machine
->first_ciw
= NULL_RTX
;
4966 p
->machine
->last_ciw
= NULL_RTX
;
4967 p
->machine
->ciw_count
= 0;
4968 p
->machine
->addr_list
= NULL_RTX
;
4972 alpha_mark_machine_status (p
)
4975 struct machine_function
*machine
= p
->machine
;
4979 ggc_mark_rtx (machine
->first_ciw
);
4980 ggc_mark_rtx (machine
->addr_list
);
4985 alpha_free_machine_status (p
)
4991 #endif /* TARGET_ABI_UNICOSMK */
4993 /* Functions to save and restore alpha_return_addr_rtx. */
4995 /* Start the ball rolling with RETURN_ADDR_RTX. */
4998 alpha_return_addr (count
, frame
)
5000 rtx frame ATTRIBUTE_UNUSED
;
5005 return get_hard_reg_initial_val (Pmode
, REG_RA
);
5008 /* Return or create a pseudo containing the gp value for the current
5009 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5012 alpha_gp_save_rtx ()
5014 return get_hard_reg_initial_val (DImode
, 29);
5018 alpha_ra_ever_killed ()
5022 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
5023 return regs_ever_live
[REG_RA
];
5025 push_topmost_sequence ();
5027 pop_topmost_sequence ();
5029 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
5033 /* Return the trap mode suffix applicable to the current
5034 instruction, or NULL. */
5037 get_trap_mode_suffix ()
5039 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
5043 case TRAP_SUFFIX_NONE
:
5046 case TRAP_SUFFIX_SU
:
5047 if (alpha_fptm
>= ALPHA_FPTM_SU
)
5051 case TRAP_SUFFIX_SUI
:
5052 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
5056 case TRAP_SUFFIX_V_SV
:
5064 case ALPHA_FPTM_SUI
:
5069 case TRAP_SUFFIX_V_SV_SVI
:
5078 case ALPHA_FPTM_SUI
:
5083 case TRAP_SUFFIX_U_SU_SUI
:
5092 case ALPHA_FPTM_SUI
:
5100 /* Return the rounding mode suffix applicable to the current
5101 instruction, or NULL. */
5104 get_round_mode_suffix ()
5106 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5110 case ROUND_SUFFIX_NONE
:
5112 case ROUND_SUFFIX_NORMAL
:
5115 case ALPHA_FPRM_NORM
:
5117 case ALPHA_FPRM_MINF
:
5119 case ALPHA_FPRM_CHOP
:
5121 case ALPHA_FPRM_DYN
:
5126 case ROUND_SUFFIX_C
:
5132 /* Print an operand. Recognize special options, documented below. */
5135 print_operand (file
, x
, code
)
5145 /* Print the assembler name of the current function. */
5146 assemble_name (file
, alpha_fnname
);
5151 const char *trap
= get_trap_mode_suffix ();
5152 const char *round
= get_round_mode_suffix ();
5155 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5156 (trap
? trap
: ""), (round
? round
: ""));
5161 /* Generates single precision instruction suffix. */
5162 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5166 /* Generates double precision instruction suffix. */
5167 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5171 if (alpha_this_literal_sequence_number
== 0)
5172 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5173 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5177 if (alpha_this_gpdisp_sequence_number
== 0)
5178 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5179 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5183 if (GET_CODE (x
) == HIGH
)
5184 output_addr_const (file
, XEXP (x
, 0));
5186 output_operand_lossage ("invalid %%H value");
5190 if (GET_CODE (x
) == CONST_INT
)
5192 if (INTVAL (x
) != 0)
5193 fprintf (file
, "\t\t!lituse_jsr!%d", (int) INTVAL (x
));
5196 output_operand_lossage ("invalid %%J value");
5200 /* If this operand is the constant zero, write it as "$31". */
5201 if (GET_CODE (x
) == REG
)
5202 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5203 else if (x
== CONST0_RTX (GET_MODE (x
)))
5204 fprintf (file
, "$31");
5206 output_operand_lossage ("invalid %%r value");
5210 /* Similar, but for floating-point. */
5211 if (GET_CODE (x
) == REG
)
5212 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5213 else if (x
== CONST0_RTX (GET_MODE (x
)))
5214 fprintf (file
, "$f31");
5216 output_operand_lossage ("invalid %%R value");
5220 /* Write the 1's complement of a constant. */
5221 if (GET_CODE (x
) != CONST_INT
)
5222 output_operand_lossage ("invalid %%N value");
5224 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5228 /* Write 1 << C, for a constant C. */
5229 if (GET_CODE (x
) != CONST_INT
)
5230 output_operand_lossage ("invalid %%P value");
5232 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5236 /* Write the high-order 16 bits of a constant, sign-extended. */
5237 if (GET_CODE (x
) != CONST_INT
)
5238 output_operand_lossage ("invalid %%h value");
5240 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5244 /* Write the low-order 16 bits of a constant, sign-extended. */
5245 if (GET_CODE (x
) != CONST_INT
)
5246 output_operand_lossage ("invalid %%L value");
5248 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5249 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5253 /* Write mask for ZAP insn. */
5254 if (GET_CODE (x
) == CONST_DOUBLE
)
5256 HOST_WIDE_INT mask
= 0;
5257 HOST_WIDE_INT value
;
5259 value
= CONST_DOUBLE_LOW (x
);
5260 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5265 value
= CONST_DOUBLE_HIGH (x
);
5266 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5269 mask
|= (1 << (i
+ sizeof (int)));
5271 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5274 else if (GET_CODE (x
) == CONST_INT
)
5276 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5278 for (i
= 0; i
< 8; i
++, value
>>= 8)
5282 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5285 output_operand_lossage ("invalid %%m value");
5289 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5290 if (GET_CODE (x
) != CONST_INT
5291 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5292 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5293 output_operand_lossage ("invalid %%M value");
5295 fprintf (file
, "%s",
5296 (INTVAL (x
) == 8 ? "b"
5297 : INTVAL (x
) == 16 ? "w"
5298 : INTVAL (x
) == 32 ? "l"
5303 /* Similar, except do it from the mask. */
5304 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0xff)
5305 fprintf (file
, "b");
5306 else if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0xffff)
5307 fprintf (file
, "w");
5308 else if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0xffffffff)
5309 fprintf (file
, "l");
5310 #if HOST_BITS_PER_WIDE_INT == 32
5311 else if (GET_CODE (x
) == CONST_DOUBLE
5312 && CONST_DOUBLE_HIGH (x
) == 0
5313 && CONST_DOUBLE_LOW (x
) == -1)
5314 fprintf (file
, "l");
5315 else if (GET_CODE (x
) == CONST_DOUBLE
5316 && CONST_DOUBLE_HIGH (x
) == -1
5317 && CONST_DOUBLE_LOW (x
) == -1)
5318 fprintf (file
, "q");
5320 else if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == -1)
5321 fprintf (file
, "q");
5322 else if (GET_CODE (x
) == CONST_DOUBLE
5323 && CONST_DOUBLE_HIGH (x
) == 0
5324 && CONST_DOUBLE_LOW (x
) == -1)
5325 fprintf (file
, "q");
5328 output_operand_lossage ("invalid %%U value");
5332 /* Write the constant value divided by 8 for little-endian mode or
5333 (56 - value) / 8 for big-endian mode. */
5335 if (GET_CODE (x
) != CONST_INT
5336 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5339 || (INTVAL (x
) & 7) != 0)
5340 output_operand_lossage ("invalid %%s value");
5342 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5344 ? (56 - INTVAL (x
)) / 8
5349 /* Same, except compute (64 - c) / 8 */
5351 if (GET_CODE (x
) != CONST_INT
5352 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5353 && (INTVAL (x
) & 7) != 8)
5354 output_operand_lossage ("invalid %%s value");
5356 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5361 /* On Unicos/Mk systems: use a DEX expression if the symbol
5362 clashes with a register name. */
5363 int dex
= unicosmk_need_dex (x
);
5365 fprintf (file
, "DEX(%d)", dex
);
5367 output_addr_const (file
, x
);
5371 case 'C': case 'D': case 'c': case 'd':
5372 /* Write out comparison name. */
5374 enum rtx_code c
= GET_CODE (x
);
5376 if (GET_RTX_CLASS (c
) != '<')
5377 output_operand_lossage ("invalid %%C value");
5379 else if (code
== 'D')
5380 c
= reverse_condition (c
);
5381 else if (code
== 'c')
5382 c
= swap_condition (c
);
5383 else if (code
== 'd')
5384 c
= swap_condition (reverse_condition (c
));
5387 fprintf (file
, "ule");
5389 fprintf (file
, "ult");
5390 else if (c
== UNORDERED
)
5391 fprintf (file
, "un");
5393 fprintf (file
, "%s", GET_RTX_NAME (c
));
5398 /* Write the divide or modulus operator. */
5399 switch (GET_CODE (x
))
5402 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5405 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5408 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5411 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5414 output_operand_lossage ("invalid %%E value");
5420 /* Write "_u" for unaligned access. */
5421 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
5422 fprintf (file
, "_u");
5426 if (GET_CODE (x
) == REG
)
5427 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5428 else if (GET_CODE (x
) == MEM
)
5429 output_address (XEXP (x
, 0));
5431 output_addr_const (file
, x
);
5435 output_operand_lossage ("invalid %%xn code");
5440 print_operand_address (file
, addr
)
5445 HOST_WIDE_INT offset
= 0;
5447 if (GET_CODE (addr
) == AND
)
5448 addr
= XEXP (addr
, 0);
5450 if (GET_CODE (addr
) == PLUS
5451 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5453 offset
= INTVAL (XEXP (addr
, 1));
5454 addr
= XEXP (addr
, 0);
5457 if (GET_CODE (addr
) == LO_SUM
)
5459 output_addr_const (file
, XEXP (addr
, 1));
5463 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
5466 addr
= XEXP (addr
, 0);
5467 if (GET_CODE (addr
) == REG
)
5468 basereg
= REGNO (addr
);
5469 else if (GET_CODE (addr
) == SUBREG
5470 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5471 basereg
= subreg_regno (addr
);
5475 fprintf (file
, "($%d)\t\t!%s", basereg
,
5476 (basereg
== 29 ? "gprel" : "gprellow"));
5480 if (GET_CODE (addr
) == REG
)
5481 basereg
= REGNO (addr
);
5482 else if (GET_CODE (addr
) == SUBREG
5483 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5484 basereg
= subreg_regno (addr
);
5485 else if (GET_CODE (addr
) == CONST_INT
)
5486 offset
= INTVAL (addr
);
5490 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
5491 fprintf (file
, "($%d)", basereg
);
5494 /* Emit RTL insns to initialize the variable parts of a trampoline at
5495 TRAMP. FNADDR is an RTX for the address of the function's pure
5496 code. CXT is an RTX for the static chain value for the function.
5498 The three offset parameters are for the individual template's
5499 layout. A JMPOFS < 0 indicates that the trampoline does not
5500 contain instructions at all.
5502 We assume here that a function will be called many more times than
5503 its address is taken (e.g., it might be passed to qsort), so we
5504 take the trouble to initialize the "hint" field in the JMP insn.
5505 Note that the hint field is PC (new) + 4 * bits 13:0. */
5508 alpha_initialize_trampoline (tramp
, fnaddr
, cxt
, fnofs
, cxtofs
, jmpofs
)
5509 rtx tramp
, fnaddr
, cxt
;
5510 int fnofs
, cxtofs
, jmpofs
;
5512 rtx temp
, temp1
, addr
;
5513 /* VMS really uses DImode pointers in memory at this point. */
5514 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
5516 #ifdef POINTERS_EXTEND_UNSIGNED
5517 fnaddr
= convert_memory_address (mode
, fnaddr
);
5518 cxt
= convert_memory_address (mode
, cxt
);
5521 /* Store function address and CXT. */
5522 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
5523 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
5524 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
5525 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
5527 /* This has been disabled since the hint only has a 32k range, and in
5528 no existing OS is the stack within 32k of the text segment. */
5529 if (0 && jmpofs
>= 0)
5531 /* Compute hint value. */
5532 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
5533 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
5535 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
5536 build_int_2 (2, 0), NULL_RTX
, 1);
5537 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
5538 GEN_INT (0x3fff), 0);
5540 /* Merge in the hint. */
5541 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
5542 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
5543 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
5544 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
5546 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
5549 #ifdef TRANSFER_FROM_TRAMPOLINE
5550 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
5551 0, VOIDmode
, 1, addr
, Pmode
);
5555 emit_insn (gen_imb ());
5558 /* Determine where to put an argument to a function.
5559 Value is zero to push the argument on the stack,
5560 or a hard register in which to store the argument.
5562 MODE is the argument's machine mode.
5563 TYPE is the data type of the argument (as a tree).
5564 This is null for libcalls where that information may
5566 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5567 the preceding args and about the function being called.
5568 NAMED is nonzero if this argument is a named parameter
5569 (otherwise it is an extra parameter matching an ellipsis).
5571 On Alpha the first 6 words of args are normally in registers
5572 and the rest are pushed. */
5575 function_arg (cum
, mode
, type
, named
)
5576 CUMULATIVE_ARGS cum
;
5577 enum machine_mode mode
;
5579 int named ATTRIBUTE_UNUSED
;
5584 /* Set up defaults for FP operands passed in FP registers, and
5585 integral operands passed in integer registers. */
5587 && (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5588 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
5593 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5594 the three platforms, so we can't avoid conditional compilation. */
5595 #if TARGET_ABI_OPEN_VMS
5597 if (mode
== VOIDmode
)
5598 return alpha_arg_info_reg_val (cum
);
5600 num_args
= cum
.num_args
;
5601 if (num_args
>= 6 || MUST_PASS_IN_STACK (mode
, type
))
5605 #if TARGET_ABI_UNICOSMK
5609 /* If this is the last argument, generate the call info word (CIW). */
5610 /* ??? We don't include the caller's line number in the CIW because
5611 I don't know how to determine it if debug infos are turned off. */
5612 if (mode
== VOIDmode
)
5621 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
5622 if (cum
.reg_args_type
[i
])
5623 lo
|= (1 << (7 - i
));
5625 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
5628 lo
|= cum
.num_reg_words
;
5630 #if HOST_BITS_PER_WIDE_INT == 32
5631 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
5633 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
5634 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
5637 ciw
= immed_double_const (lo
, hi
, DImode
);
5639 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
5640 UNSPEC_UMK_LOAD_CIW
);
5643 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
5644 num_args
= cum
.num_reg_words
;
5645 if (MUST_PASS_IN_STACK (mode
, type
)
5646 || cum
.num_reg_words
+ size
> 6 || cum
.force_stack
)
5648 else if (type
&& TYPE_MODE (type
) == BLKmode
)
5652 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
5653 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
5655 /* The argument fits in two registers. Note that we still need to
5656 reserve a register for empty structures. */
5660 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
5663 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
5664 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
5665 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
5675 /* VOID is passed as a special flag for "last argument". */
5676 if (type
== void_type_node
)
5678 else if (MUST_PASS_IN_STACK (mode
, type
))
5680 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum
, mode
, type
, named
))
5683 #endif /* TARGET_ABI_UNICOSMK */
5684 #endif /* TARGET_ABI_OPEN_VMS */
5686 return gen_rtx_REG (mode
, num_args
+ basereg
);
5690 alpha_build_va_list ()
5692 tree base
, ofs
, record
, type_decl
;
5694 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
5695 return ptr_type_node
;
5697 record
= make_lang_type (RECORD_TYPE
);
5698 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
5699 TREE_CHAIN (record
) = type_decl
;
5700 TYPE_NAME (record
) = type_decl
;
5702 /* C++? SET_IS_AGGR_TYPE (record, 1); */
5704 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
5706 DECL_FIELD_CONTEXT (ofs
) = record
;
5708 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
5710 DECL_FIELD_CONTEXT (base
) = record
;
5711 TREE_CHAIN (base
) = ofs
;
5713 TYPE_FIELDS (record
) = base
;
5714 layout_type (record
);
5720 alpha_va_start (stdarg_p
, valist
, nextarg
)
5723 rtx nextarg ATTRIBUTE_UNUSED
;
5725 HOST_WIDE_INT offset
;
5726 tree t
, offset_field
, base_field
;
5728 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
5731 if (TARGET_ABI_UNICOSMK
)
5732 std_expand_builtin_va_start (stdarg_p
, valist
, nextarg
);
5734 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
5735 up by 48, storing fp arg registers in the first 48 bytes, and the
5736 integer arg registers in the next 48 bytes. This is only done,
5737 however, if any integer registers need to be stored.
5739 If no integer registers need be stored, then we must subtract 48
5740 in order to account for the integer arg registers which are counted
5741 in argsize above, but which are not actually stored on the stack. */
5743 if (NUM_ARGS
<= 5 + stdarg_p
)
5744 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
5746 offset
= -6 * UNITS_PER_WORD
;
5748 if (TARGET_ABI_OPEN_VMS
)
5750 nextarg
= plus_constant (nextarg
, offset
);
5751 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
5752 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
5753 make_tree (ptr_type_node
, nextarg
));
5754 TREE_SIDE_EFFECTS (t
) = 1;
5756 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5760 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
5761 offset_field
= TREE_CHAIN (base_field
);
5763 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
5764 valist
, base_field
);
5765 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
5766 valist
, offset_field
);
5768 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
5769 t
= build (PLUS_EXPR
, ptr_type_node
, t
, build_int_2 (offset
, 0));
5770 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
5771 TREE_SIDE_EFFECTS (t
) = 1;
5772 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5774 t
= build_int_2 (NUM_ARGS
* UNITS_PER_WORD
, 0);
5775 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
5776 TREE_SIDE_EFFECTS (t
) = 1;
5777 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5782 alpha_va_arg (valist
, type
)
5786 tree t
, type_size
, rounded_size
;
5787 tree offset_field
, base_field
, addr_tree
, addend
;
5788 tree wide_type
, wide_ofs
;
5791 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
5792 return std_expand_builtin_va_arg (valist
, type
);
5794 if (type
== error_mark_node
5795 || (type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
))) == NULL
5796 || TREE_OVERFLOW (type_size
))
5797 rounded_size
= size_zero_node
;
5799 rounded_size
= fold (build (MULT_EXPR
, sizetype
,
5800 fold (build (TRUNC_DIV_EXPR
, sizetype
,
5801 fold (build (PLUS_EXPR
, sizetype
,
5807 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
5808 offset_field
= TREE_CHAIN (base_field
);
5810 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
5811 valist
, base_field
);
5812 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
5813 valist
, offset_field
);
5815 /* If the type could not be passed in registers, skip the block
5816 reserved for the registers. */
5817 if (MUST_PASS_IN_STACK (TYPE_MODE (type
), type
))
5819 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
5820 build (MAX_EXPR
, TREE_TYPE (offset_field
),
5821 offset_field
, build_int_2 (6*8, 0)));
5822 TREE_SIDE_EFFECTS (t
) = 1;
5823 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5826 wide_type
= make_signed_type (64);
5827 wide_ofs
= save_expr (build1 (CONVERT_EXPR
, wide_type
, offset_field
));
5831 if (TYPE_MODE (type
) == TFmode
|| TYPE_MODE (type
) == TCmode
)
5834 rounded_size
= size_int (UNITS_PER_WORD
);
5836 else if (FLOAT_TYPE_P (type
))
5838 tree fpaddend
, cond
;
5840 fpaddend
= fold (build (PLUS_EXPR
, TREE_TYPE (addend
),
5841 addend
, build_int_2 (-6*8, 0)));
5843 cond
= fold (build (LT_EXPR
, integer_type_node
,
5844 wide_ofs
, build_int_2 (6*8, 0)));
5846 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
5850 addr_tree
= build (PLUS_EXPR
, TREE_TYPE (base_field
),
5851 base_field
, addend
);
5853 addr
= expand_expr (addr_tree
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
5854 addr
= copy_to_reg (addr
);
5856 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
5857 build (PLUS_EXPR
, TREE_TYPE (offset_field
),
5858 offset_field
, rounded_size
));
5859 TREE_SIDE_EFFECTS (t
) = 1;
5860 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5864 addr
= force_reg (Pmode
, addr
);
5865 addr
= gen_rtx_MEM (Pmode
, addr
);
5871 /* This page contains routines that are used to determine what the function
5872 prologue and epilogue code will do and write them out. */
5874 /* Compute the size of the save area in the stack. */
5876 /* These variables are used for communication between the following functions.
5877 They indicate various things about the current function being compiled
5878 that are used to tell what kind of prologue, epilogue and procedure
5879 descriptior to generate. */
5881 /* Nonzero if we need a stack procedure. */
5882 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
5883 static enum alpha_procedure_types alpha_procedure_type
;
5885 /* Register number (either FP or SP) that is used to unwind the frame. */
5886 static int vms_unwind_regno
;
5888 /* Register number used to save FP. We need not have one for RA since
5889 we don't modify it for register procedures. This is only defined
5890 for register frame procedures. */
5891 static int vms_save_fp_regno
;
5893 /* Register number used to reference objects off our PV. */
5894 static int vms_base_regno
;
5896 /* Compute register masks for saved registers. */
5899 alpha_sa_mask (imaskP
, fmaskP
)
5900 unsigned long *imaskP
;
5901 unsigned long *fmaskP
;
5903 unsigned long imask
= 0;
5904 unsigned long fmask
= 0;
5907 /* Irritatingly, there are two kinds of thunks -- those created with
5908 ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go through
5909 the regular part of the compiler. In the ASM_OUTPUT_MI_THUNK case
5910 we don't have valid register life info, but assemble_start_function
5911 wants to output .frame and .mask directives. */
5912 if (current_function_is_thunk
&& !no_new_pseudos
)
5919 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
5920 imask
|= (1L << HARD_FRAME_POINTER_REGNUM
);
5922 /* One for every register we have to save. */
5923 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5924 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
5925 && regs_ever_live
[i
] && i
!= REG_RA
5926 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
5931 fmask
|= (1L << (i
- 32));
5934 /* We need to restore these for the handler. */
5935 if (current_function_calls_eh_return
)
5938 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
5939 if (regno
== INVALID_REGNUM
)
5941 imask
|= 1L << regno
;
5944 /* If any register spilled, then spill the return address also. */
5945 /* ??? This is required by the Digital stack unwind specification
5946 and isn't needed if we're doing Dwarf2 unwinding. */
5947 if (imask
|| fmask
|| alpha_ra_ever_killed ())
5948 imask
|= (1L << REG_RA
);
5957 unsigned long mask
[2];
5961 alpha_sa_mask (&mask
[0], &mask
[1]);
5963 if (TARGET_ABI_UNICOSMK
)
5965 if (mask
[0] || mask
[1])
5970 for (j
= 0; j
< 2; ++j
)
5971 for (i
= 0; i
< 32; ++i
)
5972 if ((mask
[j
] >> i
) & 1)
5976 if (TARGET_ABI_UNICOSMK
)
5978 /* We might not need to generate a frame if we don't make any calls
5979 (including calls to __T3E_MISMATCH if this is a vararg function),
5980 don't have any local variables which require stack slots, don't
5981 use alloca and have not determined that we need a frame for other
5984 alpha_procedure_type
5985 = (sa_size
|| get_frame_size() != 0
5986 || current_function_outgoing_args_size
|| current_function_varargs
5987 || current_function_stdarg
|| current_function_calls_alloca
5988 || frame_pointer_needed
)
5989 ? PT_STACK
: PT_REGISTER
;
5991 /* Always reserve space for saving callee-saved registers if we
5992 need a frame as required by the calling convention. */
5993 if (alpha_procedure_type
== PT_STACK
)
5996 else if (TARGET_ABI_OPEN_VMS
)
5998 /* Start by assuming we can use a register procedure if we don't
5999 make any calls (REG_RA not used) or need to save any
6000 registers and a stack procedure if we do. */
6001 if ((mask
[0] >> REG_RA
) & 1)
6002 alpha_procedure_type
= PT_STACK
;
6003 else if (get_frame_size() != 0)
6004 alpha_procedure_type
= PT_REGISTER
;
6006 alpha_procedure_type
= PT_NULL
;
6008 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6009 made the final decision on stack procedure vs register procedure. */
6010 if (alpha_procedure_type
== PT_STACK
)
6013 /* Decide whether to refer to objects off our PV via FP or PV.
6014 If we need FP for something else or if we receive a nonlocal
6015 goto (which expects PV to contain the value), we must use PV.
6016 Otherwise, start by assuming we can use FP. */
6019 = (frame_pointer_needed
6020 || current_function_has_nonlocal_label
6021 || alpha_procedure_type
== PT_STACK
6022 || current_function_outgoing_args_size
)
6023 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
6025 /* If we want to copy PV into FP, we need to find some register
6026 in which to save FP. */
6028 vms_save_fp_regno
= -1;
6029 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
6030 for (i
= 0; i
< 32; i
++)
6031 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
6032 vms_save_fp_regno
= i
;
6034 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
6035 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
6036 else if (alpha_procedure_type
== PT_NULL
)
6037 vms_base_regno
= REG_PV
;
6039 /* Stack unwinding should be done via FP unless we use it for PV. */
6040 vms_unwind_regno
= (vms_base_regno
== REG_PV
6041 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
6043 /* If this is a stack procedure, allow space for saving FP and RA. */
6044 if (alpha_procedure_type
== PT_STACK
)
6049 /* Our size must be even (multiple of 16 bytes). */
6058 alpha_pv_save_size ()
6061 return alpha_procedure_type
== PT_STACK
? 8 : 0;
6068 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
6071 #if TARGET_ABI_OPEN_VMS
6073 const struct attribute_spec vms_attribute_table
[] =
6075 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6076 { "overlaid", 0, 0, true, false, false, NULL
},
6077 { "global", 0, 0, true, false, false, NULL
},
6078 { "initialize", 0, 0, true, false, false, NULL
},
6079 { NULL
, 0, 0, false, false, false, NULL
}
6085 find_lo_sum (px
, data
)
6087 void *data ATTRIBUTE_UNUSED
;
6089 return GET_CODE (*px
) == LO_SUM
;
6093 alpha_does_function_need_gp ()
6097 /* The GP being variable is an OSF abi thing. */
6098 if (! TARGET_ABI_OSF
)
6101 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6104 if (current_function_is_thunk
)
6107 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6108 Even if we are a static function, we still need to do this in case
6109 our address is taken and passed to something like qsort. */
6111 push_topmost_sequence ();
6112 insn
= get_insns ();
6113 pop_topmost_sequence ();
6115 for (; insn
; insn
= NEXT_INSN (insn
))
6117 && GET_CODE (PATTERN (insn
)) != USE
6118 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6120 enum attr_type type
= get_attr_type (insn
);
6121 if (type
== TYPE_LDSYM
|| type
== TYPE_JSR
)
6123 if (TARGET_EXPLICIT_RELOCS
6124 && for_each_rtx (&PATTERN (insn
), find_lo_sum
, NULL
) > 0)
6131 /* Write a version stamp. Don't write anything if we are running as a
6132 cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
6139 alpha_write_verstamp (file
)
6140 FILE *file ATTRIBUTE_UNUSED
;
6143 fprintf (file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
6147 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6151 set_frame_related_p ()
6153 rtx seq
= gen_sequence ();
6156 if (GET_CODE (seq
) == SEQUENCE
)
6158 int i
= XVECLEN (seq
, 0);
6160 RTX_FRAME_RELATED_P (XVECEXP (seq
, 0, i
)) = 1;
6161 return emit_insn (seq
);
6165 seq
= emit_insn (seq
);
6166 RTX_FRAME_RELATED_P (seq
) = 1;
6171 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
6173 /* Write function prologue. */
6175 /* On vms we have two kinds of functions:
6177 - stack frame (PROC_STACK)
6178 these are 'normal' functions with local vars and which are
6179 calling other functions
6180 - register frame (PROC_REGISTER)
6181 keeps all data in registers, needs no stack
6183 We must pass this to the assembler so it can generate the
6184 proper pdsc (procedure descriptor)
6185 This is done with the '.pdesc' command.
6187 On not-vms, we don't really differentiate between the two, as we can
6188 simply allocate stack without saving registers. */
6191 alpha_expand_prologue ()
6193 /* Registers to save. */
6194 unsigned long imask
= 0;
6195 unsigned long fmask
= 0;
6196 /* Stack space needed for pushing registers clobbered by us. */
6197 HOST_WIDE_INT sa_size
;
6198 /* Complete stack size needed. */
6199 HOST_WIDE_INT frame_size
;
6200 /* Offset from base reg to register save area. */
6201 HOST_WIDE_INT reg_offset
;
6205 sa_size
= alpha_sa_size ();
6207 frame_size
= get_frame_size ();
6208 if (TARGET_ABI_OPEN_VMS
)
6209 frame_size
= ALPHA_ROUND (sa_size
6210 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
6212 + current_function_pretend_args_size
);
6213 else if (TARGET_ABI_UNICOSMK
)
6214 /* We have to allocate space for the DSIB if we generate a frame. */
6215 frame_size
= ALPHA_ROUND (sa_size
6216 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
6217 + ALPHA_ROUND (frame_size
6218 + current_function_outgoing_args_size
);
6220 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
6222 + ALPHA_ROUND (frame_size
6223 + current_function_pretend_args_size
));
6225 if (TARGET_ABI_OPEN_VMS
)
6228 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
6230 alpha_sa_mask (&imask
, &fmask
);
6232 /* Emit an insn to reload GP, if needed. */
6235 alpha_function_needs_gp
= alpha_does_function_need_gp ();
6236 if (alpha_function_needs_gp
)
6237 emit_insn (gen_prologue_ldgp ());
6240 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
6241 the call to mcount ourselves, rather than having the linker do it
6242 magically in response to -pg. Since _mcount has special linkage,
6243 don't represent the call as a call. */
6244 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6245 emit_insn (gen_prologue_mcount ());
6247 if (TARGET_ABI_UNICOSMK
)
6248 unicosmk_gen_dsib (&imask
);
6250 /* Adjust the stack by the frame size. If the frame size is > 4096
6251 bytes, we need to be sure we probe somewhere in the first and last
6252 4096 bytes (we can probably get away without the latter test) and
6253 every 8192 bytes in between. If the frame size is > 32768, we
6254 do this in a loop. Otherwise, we generate the explicit probe
6257 Note that we are only allowed to adjust sp once in the prologue. */
6259 if (frame_size
<= 32768)
6261 if (frame_size
> 4096)
6266 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
6269 while ((probed
+= 8192) < frame_size
);
6271 /* We only have to do this probe if we aren't saving registers. */
6272 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
6273 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
6276 if (frame_size
!= 0)
6277 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
6278 GEN_INT (TARGET_ABI_UNICOSMK
6284 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
6285 number of 8192 byte blocks to probe. We then probe each block
6286 in the loop and then set SP to the proper location. If the
6287 amount remaining is > 4096, we have to do one more probe if we
6288 are not saving any registers. */
6290 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
6291 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
6292 rtx ptr
= gen_rtx_REG (DImode
, 22);
6293 rtx count
= gen_rtx_REG (DImode
, 23);
6296 emit_move_insn (count
, GEN_INT (blocks
));
6297 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
6298 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
6300 /* Because of the difficulty in emitting a new basic block this
6301 late in the compilation, generate the loop as a single insn. */
6302 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
6304 if (leftover
> 4096 && sa_size
== 0)
6306 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
6307 MEM_VOLATILE_P (last
) = 1;
6308 emit_move_insn (last
, const0_rtx
);
6311 if (TARGET_ABI_WINDOWS_NT
)
6313 /* For NT stack unwind (done by 'reverse execution'), it's
6314 not OK to take the result of a loop, even though the value
6315 is already in ptr, so we reload it via a single operation
6316 and subtract it to sp.
6318 Yes, that's correct -- we have to reload the whole constant
6319 into a temporary via ldah+lda then subtract from sp. To
6320 ensure we get ldah+lda, we use a special pattern. */
6322 HOST_WIDE_INT lo
, hi
;
6323 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
6324 hi
= frame_size
- lo
;
6326 emit_move_insn (ptr
, GEN_INT (hi
));
6327 emit_insn (gen_nt_lda (ptr
, GEN_INT (lo
)));
6328 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
6333 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
6334 GEN_INT (-leftover
)));
6337 /* This alternative is special, because the DWARF code cannot
6338 possibly intuit through the loop above. So we invent this
6339 note it looks at instead. */
6340 RTX_FRAME_RELATED_P (seq
) = 1;
6342 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
6343 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
6344 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
6345 GEN_INT (TARGET_ABI_UNICOSMK
6351 if (!TARGET_ABI_UNICOSMK
)
6353 /* Cope with very large offsets to the register save area. */
6354 sa_reg
= stack_pointer_rtx
;
6355 if (reg_offset
+ sa_size
> 0x8000)
6357 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
6360 if (low
+ sa_size
<= 0x8000)
6361 bias
= reg_offset
- low
, reg_offset
= low
;
6363 bias
= reg_offset
, reg_offset
= 0;
6365 sa_reg
= gen_rtx_REG (DImode
, 24);
6366 FRP (emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
,
6370 /* Save regs in stack order. Beginning with VMS PV. */
6371 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6373 mem
= gen_rtx_MEM (DImode
, stack_pointer_rtx
);
6374 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6375 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_PV
)));
6378 /* Save register RA next. */
6379 if (imask
& (1L << REG_RA
))
6381 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
6382 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6383 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
6384 imask
&= ~(1L << REG_RA
);
6388 /* Now save any other registers required to be saved. */
6389 for (i
= 0; i
< 32; i
++)
6390 if (imask
& (1L << i
))
6392 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
6393 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6394 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
6398 for (i
= 0; i
< 32; i
++)
6399 if (fmask
& (1L << i
))
6401 mem
= gen_rtx_MEM (DFmode
, plus_constant (sa_reg
, reg_offset
));
6402 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6403 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
6407 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
6409 /* The standard frame on the T3E includes space for saving registers.
6410 We just have to use it. We don't have to save the return address and
6411 the old frame pointer here - they are saved in the DSIB. */
6414 for (i
= 9; i
< 15; i
++)
6415 if (imask
& (1L << i
))
6417 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
6419 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6420 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
6423 for (i
= 2; i
< 10; i
++)
6424 if (fmask
& (1L << i
))
6426 mem
= gen_rtx_MEM (DFmode
, plus_constant (hard_frame_pointer_rtx
,
6428 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6429 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
6434 if (TARGET_ABI_OPEN_VMS
)
6436 if (alpha_procedure_type
== PT_REGISTER
)
6437 /* Register frame procedures save the fp.
6438 ?? Ought to have a dwarf2 save for this. */
6439 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
6440 hard_frame_pointer_rtx
);
6442 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
6443 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
6444 gen_rtx_REG (DImode
, REG_PV
)));
6446 if (alpha_procedure_type
!= PT_NULL
6447 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
6448 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
6450 /* If we have to allocate space for outgoing args, do it now. */
6451 if (current_function_outgoing_args_size
!= 0)
6454 plus_constant (hard_frame_pointer_rtx
,
6456 (current_function_outgoing_args_size
)))));
6458 else if (!TARGET_ABI_UNICOSMK
)
6460 /* If we need a frame pointer, set it from the stack pointer. */
6461 if (frame_pointer_needed
)
6463 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
6464 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
6466 /* This must always be the last instruction in the
6467 prologue, thus we emit a special move + clobber. */
6468 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
6469 stack_pointer_rtx
, sa_reg
)));
6473 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
6474 the prologue, for exception handling reasons, we cannot do this for
6475 any insn that might fault. We could prevent this for mems with a
6476 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
6477 have to prevent all such scheduling with a blockage.
6479 Linux, on the other hand, never bothered to implement OSF/1's
6480 exception handling, and so doesn't care about such things. Anyone
6481 planning to use dwarf2 frame-unwind info can also omit the blockage. */
6483 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
6484 emit_insn (gen_blockage ());
6487 /* Output the textual info surrounding the prologue. */
6490 alpha_start_function (file
, fnname
, decl
)
6493 tree decl ATTRIBUTE_UNUSED
;
6495 unsigned long imask
= 0;
6496 unsigned long fmask
= 0;
6497 /* Stack space needed for pushing registers clobbered by us. */
6498 HOST_WIDE_INT sa_size
;
6499 /* Complete stack size needed. */
6500 HOST_WIDE_INT frame_size
;
6501 /* Offset from base reg to register save area. */
6502 HOST_WIDE_INT reg_offset
;
6503 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
6506 /* Don't emit an extern directive for functions defined in the same file. */
6507 if (TARGET_ABI_UNICOSMK
)
6510 name_tree
= get_identifier (fnname
);
6511 TREE_ASM_WRITTEN (name_tree
) = 1;
6514 alpha_fnname
= fnname
;
6515 sa_size
= alpha_sa_size ();
6517 frame_size
= get_frame_size ();
6518 if (TARGET_ABI_OPEN_VMS
)
6519 frame_size
= ALPHA_ROUND (sa_size
6520 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
6522 + current_function_pretend_args_size
);
6523 else if (TARGET_ABI_UNICOSMK
)
6524 frame_size
= ALPHA_ROUND (sa_size
6525 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
6526 + ALPHA_ROUND (frame_size
6527 + current_function_outgoing_args_size
);
6529 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
6531 + ALPHA_ROUND (frame_size
6532 + current_function_pretend_args_size
));
6534 if (TARGET_ABI_OPEN_VMS
)
6537 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
6539 alpha_sa_mask (&imask
, &fmask
);
6541 /* Ecoff can handle multiple .file directives, so put out file and lineno.
6542 We have to do that before the .ent directive as we cannot switch
6543 files within procedures with native ecoff because line numbers are
6544 linked to procedure descriptors.
6545 Outputting the lineno helps debugging of one line functions as they
6546 would otherwise get no line number at all. Please note that we would
6547 like to put out last_linenum from final.c, but it is not accessible. */
6549 if (write_symbols
== SDB_DEBUG
)
6551 #ifdef ASM_OUTPUT_SOURCE_FILENAME
6552 ASM_OUTPUT_SOURCE_FILENAME (file
,
6553 DECL_SOURCE_FILE (current_function_decl
));
6555 #ifdef ASM_OUTPUT_SOURCE_LINE
6556 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
6557 ASM_OUTPUT_SOURCE_LINE (file
,
6558 DECL_SOURCE_LINE (current_function_decl
));
6562 /* Issue function start and label. */
6563 if (TARGET_ABI_OPEN_VMS
6564 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
6566 fputs ("\t.ent ", file
);
6567 assemble_name (file
, fnname
);
6570 /* If the function needs GP, we'll write the "..ng" label there.
6571 Otherwise, do it here. */
6573 && ! alpha_function_needs_gp
6574 && ! current_function_is_thunk
)
6577 assemble_name (file
, fnname
);
6578 fputs ("..ng:\n", file
);
6582 strcpy (entry_label
, fnname
);
6583 if (TARGET_ABI_OPEN_VMS
)
6584 strcat (entry_label
, "..en");
6586 /* For public functions, the label must be globalized by appending an
6587 additional colon. */
6588 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
6589 strcat (entry_label
, ":");
6591 ASM_OUTPUT_LABEL (file
, entry_label
);
6592 inside_function
= TRUE
;
6594 if (TARGET_ABI_OPEN_VMS
)
6595 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
6597 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
6598 && !flag_inhibit_size_directive
)
6600 /* Set flags in procedure descriptor to request IEEE-conformant
6601 math-library routines. The value we set it to is PDSC_EXC_IEEE
6602 (/usr/include/pdsc.h). */
6603 fputs ("\t.eflag 48\n", file
);
6606 /* Set up offsets to alpha virtual arg/local debugging pointer. */
6607 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
6608 alpha_arg_offset
= -frame_size
+ 48;
6610 /* Describe our frame. If the frame size is larger than an integer,
6611 print it as zero to avoid an assembler error. We won't be
6612 properly describing such a frame, but that's the best we can do. */
6613 if (TARGET_ABI_UNICOSMK
)
6615 else if (TARGET_ABI_OPEN_VMS
)
6617 fprintf (file
, "\t.frame $%d,", vms_unwind_regno
);
6618 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6619 frame_size
>= ((HOST_WIDE_INT
) 1 << 31) ? 0 : frame_size
);
6620 fputs (",$26,", file
);
6621 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, reg_offset
);
6624 else if (!flag_inhibit_size_directive
)
6626 fprintf (file
, "\t.frame $%d,",
6627 (frame_pointer_needed
6628 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
));
6629 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6630 frame_size
>= (1l << 31) ? 0 : frame_size
);
6631 fprintf (file
, ",$26,%d\n", current_function_pretend_args_size
);
6634 /* Describe which registers were spilled. */
6635 if (TARGET_ABI_UNICOSMK
)
6637 else if (TARGET_ABI_OPEN_VMS
)
6640 /* ??? Does VMS care if mask contains ra? The old code didn't
6641 set it, so I don't here. */
6642 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1L << REG_RA
));
6644 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
6645 if (alpha_procedure_type
== PT_REGISTER
)
6646 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
6648 else if (!flag_inhibit_size_directive
)
6652 fprintf (file
, "\t.mask 0x%lx,", imask
);
6653 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6654 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
6657 for (i
= 0; i
< 32; ++i
)
6658 if (imask
& (1L << i
))
6664 fprintf (file
, "\t.fmask 0x%lx,", fmask
);
6665 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6666 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
6671 #if TARGET_ABI_OPEN_VMS
6672 /* Ifdef'ed cause readonly_section and link_section are only
6674 readonly_section ();
6675 fprintf (file
, "\t.align 3\n");
6676 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
6677 fputs ("\t.ascii \"", file
);
6678 assemble_name (file
, fnname
);
6679 fputs ("\\0\"\n", file
);
6682 fprintf (file
, "\t.align 3\n");
6683 fputs ("\t.name ", file
);
6684 assemble_name (file
, fnname
);
6685 fputs ("..na\n", file
);
6686 ASM_OUTPUT_LABEL (file
, fnname
);
6687 fprintf (file
, "\t.pdesc ");
6688 assemble_name (file
, fnname
);
6689 fprintf (file
, "..en,%s\n",
6690 alpha_procedure_type
== PT_STACK
? "stack"
6691 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
6692 alpha_need_linkage (fnname
, 1);
6697 /* Emit the .prologue note at the scheduled end of the prologue. */
6700 alpha_output_function_end_prologue (file
)
6703 if (TARGET_ABI_UNICOSMK
)
6705 else if (TARGET_ABI_OPEN_VMS
)
6706 fputs ("\t.prologue\n", file
);
6707 else if (TARGET_ABI_WINDOWS_NT
)
6708 fputs ("\t.prologue 0\n", file
);
6709 else if (!flag_inhibit_size_directive
)
6710 fprintf (file
, "\t.prologue %d\n",
6711 alpha_function_needs_gp
|| current_function_is_thunk
);
6714 /* Write function epilogue. */
6716 /* ??? At some point we will want to support full unwind, and so will
6717 need to mark the epilogue as well. At the moment, we just confuse
6720 #define FRP(exp) exp
6723 alpha_expand_epilogue ()
6725 /* Registers to save. */
6726 unsigned long imask
= 0;
6727 unsigned long fmask
= 0;
6728 /* Stack space needed for pushing registers clobbered by us. */
6729 HOST_WIDE_INT sa_size
;
6730 /* Complete stack size needed. */
6731 HOST_WIDE_INT frame_size
;
6732 /* Offset from base reg to register save area. */
6733 HOST_WIDE_INT reg_offset
;
6734 int fp_is_frame_pointer
, fp_offset
;
6735 rtx sa_reg
, sa_reg_exp
= NULL
;
6736 rtx sp_adj1
, sp_adj2
, mem
;
6740 sa_size
= alpha_sa_size ();
6742 frame_size
= get_frame_size ();
6743 if (TARGET_ABI_OPEN_VMS
)
6744 frame_size
= ALPHA_ROUND (sa_size
6745 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
6747 + current_function_pretend_args_size
);
6748 else if (TARGET_ABI_UNICOSMK
)
6749 frame_size
= ALPHA_ROUND (sa_size
6750 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
6751 + ALPHA_ROUND (frame_size
6752 + current_function_outgoing_args_size
);
6754 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
6756 + ALPHA_ROUND (frame_size
6757 + current_function_pretend_args_size
));
6759 if (TARGET_ABI_OPEN_VMS
)
6761 if (alpha_procedure_type
== PT_STACK
)
6767 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
6769 alpha_sa_mask (&imask
, &fmask
);
6772 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6773 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
6775 sa_reg
= stack_pointer_rtx
;
6777 if (current_function_calls_eh_return
)
6778 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
6782 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
6784 /* If we have a frame pointer, restore SP from it. */
6785 if ((TARGET_ABI_OPEN_VMS
6786 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
6787 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
6788 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
6790 /* Cope with very large offsets to the register save area. */
6791 if (reg_offset
+ sa_size
> 0x8000)
6793 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
6796 if (low
+ sa_size
<= 0x8000)
6797 bias
= reg_offset
- low
, reg_offset
= low
;
6799 bias
= reg_offset
, reg_offset
= 0;
6801 sa_reg
= gen_rtx_REG (DImode
, 22);
6802 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
6804 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
6807 /* Restore registers in order, excepting a true frame pointer. */
6809 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
6811 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6812 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
6815 imask
&= ~(1L << REG_RA
);
6817 for (i
= 0; i
< 32; ++i
)
6818 if (imask
& (1L << i
))
6820 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
6821 fp_offset
= reg_offset
;
6824 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
6825 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6826 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
6831 for (i
= 0; i
< 32; ++i
)
6832 if (fmask
& (1L << i
))
6834 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
6835 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6836 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
6840 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
6842 /* Restore callee-saved general-purpose registers. */
6846 for (i
= 9; i
< 15; i
++)
6847 if (imask
& (1L << i
))
6849 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
6851 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6852 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
6856 for (i
= 2; i
< 10; i
++)
6857 if (fmask
& (1L << i
))
6859 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
6861 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6862 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
6866 /* Restore the return address from the DSIB. */
6868 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
6869 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6870 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
6873 if (frame_size
|| eh_ofs
)
6875 sp_adj1
= stack_pointer_rtx
;
6879 sp_adj1
= gen_rtx_REG (DImode
, 23);
6880 emit_move_insn (sp_adj1
,
6881 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
6884 /* If the stack size is large, begin computation into a temporary
6885 register so as not to interfere with a potential fp restore,
6886 which must be consecutive with an SP restore. */
6887 if (frame_size
< 32768
6888 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
6889 sp_adj2
= GEN_INT (frame_size
);
6890 else if (TARGET_ABI_UNICOSMK
)
6892 sp_adj1
= gen_rtx_REG (DImode
, 23);
6893 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
6894 sp_adj2
= const0_rtx
;
6896 else if (frame_size
< 0x40007fffL
)
6898 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
6900 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
6901 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
6905 sp_adj1
= gen_rtx_REG (DImode
, 23);
6906 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
6908 sp_adj2
= GEN_INT (low
);
6912 rtx tmp
= gen_rtx_REG (DImode
, 23);
6913 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
6916 /* We can't drop new things to memory this late, afaik,
6917 so build it up by pieces. */
6918 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
6919 -(frame_size
< 0)));
6925 /* From now on, things must be in order. So emit blockages. */
6927 /* Restore the frame pointer. */
6928 if (TARGET_ABI_UNICOSMK
)
6930 emit_insn (gen_blockage ());
6931 mem
= gen_rtx_MEM (DImode
,
6932 plus_constant (hard_frame_pointer_rtx
, -16));
6933 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6934 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
6936 else if (fp_is_frame_pointer
)
6938 emit_insn (gen_blockage ());
6939 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
6940 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6941 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
6943 else if (TARGET_ABI_OPEN_VMS
)
6945 emit_insn (gen_blockage ());
6946 FRP (emit_move_insn (hard_frame_pointer_rtx
,
6947 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
6950 /* Restore the stack pointer. */
6951 emit_insn (gen_blockage ());
6952 if (sp_adj2
== const0_rtx
)
6953 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
6955 FRP (emit_move_insn (stack_pointer_rtx
,
6956 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
6960 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
6962 emit_insn (gen_blockage ());
6963 FRP (emit_move_insn (hard_frame_pointer_rtx
,
6964 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
6966 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
6968 /* Decrement the frame pointer if the function does not have a
6971 emit_insn (gen_blockage ());
6972 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
6973 hard_frame_pointer_rtx
, GEN_INT (-1))));
6978 /* Output the rest of the textual info surrounding the epilogue. */
6981 alpha_end_function (file
, fnname
, decl
)
6984 tree decl ATTRIBUTE_UNUSED
;
6986 /* End the function. */
6987 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
6989 fputs ("\t.end ", file
);
6990 assemble_name (file
, fnname
);
6993 inside_function
= FALSE
;
6995 /* Show that we know this function if it is called again.
6997 Don't do this for global functions in object files destined for a
6998 shared library because the function may be overridden by the application
6999 or other libraries. Similarly, don't do this for weak functions.
7001 Don't do this for functions not defined in the .text section, as
7002 otherwise it's not unlikely that the destination is out of range
7003 for a direct branch. */
7005 if (!DECL_WEAK (current_function_decl
)
7006 && (!flag_pic
|| !TREE_PUBLIC (current_function_decl
))
7007 && decl_in_text_section (current_function_decl
))
7008 SYMBOL_REF_FLAG (XEXP (DECL_RTL (current_function_decl
), 0)) = 1;
7010 /* Output jump tables and the static subroutine information block. */
7011 if (TARGET_ABI_UNICOSMK
)
7013 unicosmk_output_ssib (file
, fnname
);
7014 unicosmk_output_deferred_case_vectors (file
);
7018 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7020 In order to avoid the hordes of differences between generated code
7021 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7022 lots of code loading up large constants, generate rtl and emit it
7023 instead of going straight to text.
7025 Not sure why this idea hasn't been explored before... */
7028 alpha_output_mi_thunk_osf (file
, thunk_fndecl
, delta
, function
)
7030 tree thunk_fndecl ATTRIBUTE_UNUSED
;
7031 HOST_WIDE_INT delta
;
7034 HOST_WIDE_INT hi
, lo
;
7035 rtx
this, insn
, funexp
;
7037 /* We always require a valid GP. */
7038 emit_insn (gen_prologue_ldgp ());
7039 emit_note (NULL
, NOTE_INSN_PROLOGUE_END
);
7041 /* Find the "this" pointer. If the function returns a structure,
7042 the structure return pointer is in $16. */
7043 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
))))
7044 this = gen_rtx_REG (Pmode
, 17);
7046 this = gen_rtx_REG (Pmode
, 16);
7048 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7049 entire constant for the add. */
7050 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
7051 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7052 if (hi
+ lo
== delta
)
7055 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
7057 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
7061 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
7062 delta
, -(delta
< 0));
7063 emit_insn (gen_adddi3 (this, this, tmp
));
7066 /* Generate a tail call to the target function. */
7067 if (! TREE_USED (function
))
7069 assemble_external (function
);
7070 TREE_USED (function
) = 1;
7072 funexp
= XEXP (DECL_RTL (function
), 0);
7073 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
7074 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
7075 SIBLING_CALL_P (insn
) = 1;
7077 /* Run just enough of rest_of_compilation to get the insns emitted.
7078 There's not really enough bulk here to make other passes such as
7079 instruction scheduling worth while. Note that use_thunk calls
7080 assemble_start_function and assemble_end_function. */
7081 insn
= get_insns ();
7082 shorten_branches (insn
);
7083 final_start_function (insn
, file
, 1);
7084 final (insn
, file
, 1, 0);
7085 final_end_function ();
7088 /* Debugging support. */
7092 /* Count the number of sdb related labels are generated (to find block
7093 start and end boundaries). */
7095 int sdb_label_count
= 0;
7097 /* Next label # for each statement. */
7099 static int sym_lineno
= 0;
7101 /* Count the number of .file directives, so that .loc is up to date. */
7103 static int num_source_filenames
= 0;
7105 /* Name of the file containing the current function. */
7107 static const char *current_function_file
= "";
7109 /* Offsets to alpha virtual arg/local debugging pointers. */
7111 long alpha_arg_offset
;
7112 long alpha_auto_offset
;
7114 /* Emit a new filename to a stream. */
7117 alpha_output_filename (stream
, name
)
7121 static int first_time
= TRUE
;
7122 char ltext_label_name
[100];
7127 ++num_source_filenames
;
7128 current_function_file
= name
;
7129 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7130 output_quoted_string (stream
, name
);
7131 fprintf (stream
, "\n");
7132 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
7133 fprintf (stream
, "\t#@stabs\n");
7136 else if (write_symbols
== DBX_DEBUG
)
7138 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
7139 fprintf (stream
, "%s", ASM_STABS_OP
);
7140 output_quoted_string (stream
, name
);
7141 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
7144 else if (name
!= current_function_file
7145 && strcmp (name
, current_function_file
) != 0)
7147 if (inside_function
&& ! TARGET_GAS
)
7148 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
7151 ++num_source_filenames
;
7152 current_function_file
= name
;
7153 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7156 output_quoted_string (stream
, name
);
7157 fprintf (stream
, "\n");
7161 /* Emit a linenumber to a stream. */
7164 alpha_output_lineno (stream
, line
)
7168 if (write_symbols
== DBX_DEBUG
)
7170 /* mips-tfile doesn't understand .stabd directives. */
7172 fprintf (stream
, "$LM%d:\n%s%d,0,%d,$LM%d\n",
7173 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
7176 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
7179 /* Structure to show the current status of registers and memory. */
7181 struct shadow_summary
7184 unsigned int i
: 31; /* Mask of int regs */
7185 unsigned int fp
: 31; /* Mask of fp regs */
7186 unsigned int mem
: 1; /* mem == imem | fpmem */
7190 static void summarize_insn
PARAMS ((rtx
, struct shadow_summary
*, int));
7191 static void alpha_handle_trap_shadows
PARAMS ((rtx
));
7193 /* Summary the effects of expression X on the machine. Update SUM, a pointer
7194 to the summary structure. SET is nonzero if the insn is setting the
7195 object, otherwise zero. */
7198 summarize_insn (x
, sum
, set
)
7200 struct shadow_summary
*sum
;
7203 const char *format_ptr
;
7209 switch (GET_CODE (x
))
7211 /* ??? Note that this case would be incorrect if the Alpha had a
7212 ZERO_EXTRACT in SET_DEST. */
7214 summarize_insn (SET_SRC (x
), sum
, 0);
7215 summarize_insn (SET_DEST (x
), sum
, 1);
7219 summarize_insn (XEXP (x
, 0), sum
, 1);
7223 summarize_insn (XEXP (x
, 0), sum
, 0);
7227 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
7228 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
7232 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
7233 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
7237 summarize_insn (SUBREG_REG (x
), sum
, 0);
7242 int regno
= REGNO (x
);
7243 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
7245 if (regno
== 31 || regno
== 63)
7251 sum
->defd
.i
|= mask
;
7253 sum
->defd
.fp
|= mask
;
7258 sum
->used
.i
|= mask
;
7260 sum
->used
.fp
|= mask
;
7271 /* Find the regs used in memory address computation: */
7272 summarize_insn (XEXP (x
, 0), sum
, 0);
7275 case CONST_INT
: case CONST_DOUBLE
:
7276 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
7277 case SCRATCH
: case ASM_INPUT
:
7280 /* Handle common unary and binary ops for efficiency. */
7281 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
7282 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
7283 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
7284 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
7285 case NE
: case EQ
: case GE
: case GT
: case LE
:
7286 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
7287 summarize_insn (XEXP (x
, 0), sum
, 0);
7288 summarize_insn (XEXP (x
, 1), sum
, 0);
7291 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
7292 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
7293 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
7294 case SQRT
: case FFS
:
7295 summarize_insn (XEXP (x
, 0), sum
, 0);
7299 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
7300 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
7301 switch (format_ptr
[i
])
7304 summarize_insn (XEXP (x
, i
), sum
, 0);
7308 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7309 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
7321 /* Ensure a sufficient number of `trapb' insns are in the code when
7322 the user requests code with a trap precision of functions or
7325 In naive mode, when the user requests a trap-precision of
7326 "instruction", a trapb is needed after every instruction that may
7327 generate a trap. This ensures that the code is resumption safe but
7330 When optimizations are turned on, we delay issuing a trapb as long
7331 as possible. In this context, a trap shadow is the sequence of
7332 instructions that starts with a (potentially) trap generating
7333 instruction and extends to the next trapb or call_pal instruction
7334 (but GCC never generates call_pal by itself). We can delay (and
7335 therefore sometimes omit) a trapb subject to the following
7338 (a) On entry to the trap shadow, if any Alpha register or memory
7339 location contains a value that is used as an operand value by some
7340 instruction in the trap shadow (live on entry), then no instruction
7341 in the trap shadow may modify the register or memory location.
7343 (b) Within the trap shadow, the computation of the base register
7344 for a memory load or store instruction may not involve using the
7345 result of an instruction that might generate an UNPREDICTABLE
7348 (c) Within the trap shadow, no register may be used more than once
7349 as a destination register. (This is to make life easier for the
7352 (d) The trap shadow may not include any branch instructions. */
7355 alpha_handle_trap_shadows (insns
)
7358 struct shadow_summary shadow
;
7359 int trap_pending
, exception_nesting
;
7363 exception_nesting
= 0;
7366 shadow
.used
.mem
= 0;
7367 shadow
.defd
= shadow
.used
;
7369 for (i
= insns
; i
; i
= NEXT_INSN (i
))
7371 if (GET_CODE (i
) == NOTE
)
7373 switch (NOTE_LINE_NUMBER (i
))
7375 case NOTE_INSN_EH_REGION_BEG
:
7376 exception_nesting
++;
7381 case NOTE_INSN_EH_REGION_END
:
7382 exception_nesting
--;
7387 case NOTE_INSN_EPILOGUE_BEG
:
7388 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
7393 else if (trap_pending
)
7395 if (alpha_tp
== ALPHA_TP_FUNC
)
7397 if (GET_CODE (i
) == JUMP_INSN
7398 && GET_CODE (PATTERN (i
)) == RETURN
)
7401 else if (alpha_tp
== ALPHA_TP_INSN
)
7405 struct shadow_summary sum
;
7410 sum
.defd
= sum
.used
;
7412 switch (GET_CODE (i
))
7415 /* Annoyingly, get_attr_trap will abort on these. */
7416 if (GET_CODE (PATTERN (i
)) == USE
7417 || GET_CODE (PATTERN (i
)) == CLOBBER
)
7420 summarize_insn (PATTERN (i
), &sum
, 0);
7422 if ((sum
.defd
.i
& shadow
.defd
.i
)
7423 || (sum
.defd
.fp
& shadow
.defd
.fp
))
7425 /* (c) would be violated */
7429 /* Combine shadow with summary of current insn: */
7430 shadow
.used
.i
|= sum
.used
.i
;
7431 shadow
.used
.fp
|= sum
.used
.fp
;
7432 shadow
.used
.mem
|= sum
.used
.mem
;
7433 shadow
.defd
.i
|= sum
.defd
.i
;
7434 shadow
.defd
.fp
|= sum
.defd
.fp
;
7435 shadow
.defd
.mem
|= sum
.defd
.mem
;
7437 if ((sum
.defd
.i
& shadow
.used
.i
)
7438 || (sum
.defd
.fp
& shadow
.used
.fp
)
7439 || (sum
.defd
.mem
& shadow
.used
.mem
))
7441 /* (a) would be violated (also takes care of (b)) */
7442 if (get_attr_trap (i
) == TRAP_YES
7443 && ((sum
.defd
.i
& sum
.used
.i
)
7444 || (sum
.defd
.fp
& sum
.used
.fp
)))
7463 n
= emit_insn_before (gen_trapb (), i
);
7464 PUT_MODE (n
, TImode
);
7465 PUT_MODE (i
, TImode
);
7469 shadow
.used
.mem
= 0;
7470 shadow
.defd
= shadow
.used
;
7475 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
7476 && GET_CODE (i
) == INSN
7477 && GET_CODE (PATTERN (i
)) != USE
7478 && GET_CODE (PATTERN (i
)) != CLOBBER
7479 && get_attr_trap (i
) == TRAP_YES
)
7481 if (optimize
&& !trap_pending
)
7482 summarize_insn (PATTERN (i
), &shadow
, 0);
7488 /* Alpha can only issue instruction groups simultaneously if they are
7489 suitibly aligned. This is very processor-specific. */
7491 enum alphaev4_pipe
{
7498 enum alphaev5_pipe
{
7509 static enum alphaev4_pipe alphaev4_insn_pipe
PARAMS ((rtx
));
7510 static enum alphaev5_pipe alphaev5_insn_pipe
PARAMS ((rtx
));
7511 static rtx alphaev4_next_group
PARAMS ((rtx
, int *, int *));
7512 static rtx alphaev5_next_group
PARAMS ((rtx
, int *, int *));
7513 static rtx alphaev4_next_nop
PARAMS ((int *));
7514 static rtx alphaev5_next_nop
PARAMS ((int *));
7516 static void alpha_align_insns
7517 PARAMS ((rtx
, unsigned int, rtx (*)(rtx
, int *, int *), rtx (*)(int *)));
7519 static enum alphaev4_pipe
7520 alphaev4_insn_pipe (insn
)
7523 if (recog_memoized (insn
) < 0)
7525 if (get_attr_length (insn
) != 4)
7528 switch (get_attr_type (insn
))
7561 static enum alphaev5_pipe
7562 alphaev5_insn_pipe (insn
)
7565 if (recog_memoized (insn
) < 0)
7567 if (get_attr_length (insn
) != 4)
7570 switch (get_attr_type (insn
))
7610 /* IN_USE is a mask of the slots currently filled within the insn group.
7611 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
7612 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
7614 LEN is, of course, the length of the group in bytes. */
7617 alphaev4_next_group (insn
, pin_use
, plen
)
7619 int *pin_use
, *plen
;
7626 || GET_CODE (PATTERN (insn
)) == CLOBBER
7627 || GET_CODE (PATTERN (insn
)) == USE
)
7632 enum alphaev4_pipe pipe
;
7634 pipe
= alphaev4_insn_pipe (insn
);
7638 /* Force complex instructions to start new groups. */
7642 /* If this is a completely unrecognized insn, its an asm.
7643 We don't know how long it is, so record length as -1 to
7644 signal a needed realignment. */
7645 if (recog_memoized (insn
) < 0)
7648 len
= get_attr_length (insn
);
7652 if (in_use
& EV4_IB0
)
7654 if (in_use
& EV4_IB1
)
7659 in_use
|= EV4_IB0
| EV4_IBX
;
7663 if (in_use
& EV4_IB0
)
7665 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
7673 if (in_use
& EV4_IB1
)
7683 /* Haifa doesn't do well scheduling branches. */
7684 if (GET_CODE (insn
) == JUMP_INSN
)
7688 insn
= next_nonnote_insn (insn
);
7690 if (!insn
|| ! INSN_P (insn
))
7693 /* Let Haifa tell us where it thinks insn group boundaries are. */
7694 if (GET_MODE (insn
) == TImode
)
7697 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
7702 insn
= next_nonnote_insn (insn
);
7710 /* IN_USE is a mask of the slots currently filled within the insn group.
7711 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
7712 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
7714 LEN is, of course, the length of the group in bytes. */
7717 alphaev5_next_group (insn
, pin_use
, plen
)
7719 int *pin_use
, *plen
;
7726 || GET_CODE (PATTERN (insn
)) == CLOBBER
7727 || GET_CODE (PATTERN (insn
)) == USE
)
7732 enum alphaev5_pipe pipe
;
7734 pipe
= alphaev5_insn_pipe (insn
);
7738 /* Force complex instructions to start new groups. */
7742 /* If this is a completely unrecognized insn, its an asm.
7743 We don't know how long it is, so record length as -1 to
7744 signal a needed realignment. */
7745 if (recog_memoized (insn
) < 0)
7748 len
= get_attr_length (insn
);
7751 /* ??? Most of the places below, we would like to abort, as
7752 it would indicate an error either in Haifa, or in the
7753 scheduling description. Unfortunately, Haifa never
7754 schedules the last instruction of the BB, so we don't
7755 have an accurate TI bit to go off. */
7757 if (in_use
& EV5_E0
)
7759 if (in_use
& EV5_E1
)
7764 in_use
|= EV5_E0
| EV5_E01
;
7768 if (in_use
& EV5_E0
)
7770 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
7778 if (in_use
& EV5_E1
)
7784 if (in_use
& EV5_FA
)
7786 if (in_use
& EV5_FM
)
7791 in_use
|= EV5_FA
| EV5_FAM
;
7795 if (in_use
& EV5_FA
)
7801 if (in_use
& EV5_FM
)
7814 /* Haifa doesn't do well scheduling branches. */
7815 /* ??? If this is predicted not-taken, slotting continues, except
7816 that no more IBR, FBR, or JSR insns may be slotted. */
7817 if (GET_CODE (insn
) == JUMP_INSN
)
7821 insn
= next_nonnote_insn (insn
);
7823 if (!insn
|| ! INSN_P (insn
))
7826 /* Let Haifa tell us where it thinks insn group boundaries are. */
7827 if (GET_MODE (insn
) == TImode
)
7830 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
7835 insn
= next_nonnote_insn (insn
);
7844 alphaev4_next_nop (pin_use
)
7847 int in_use
= *pin_use
;
7850 if (!(in_use
& EV4_IB0
))
7855 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
7860 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
7873 alphaev5_next_nop (pin_use
)
7876 int in_use
= *pin_use
;
7879 if (!(in_use
& EV5_E1
))
7884 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
7889 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
7901 /* The instruction group alignment main loop. */
7904 alpha_align_insns (insns
, max_align
, next_group
, next_nop
)
7906 unsigned int max_align
;
7907 rtx (*next_group
) PARAMS ((rtx
, int *, int *));
7908 rtx (*next_nop
) PARAMS ((int *));
7910 /* ALIGN is the known alignment for the insn group. */
7912 /* OFS is the offset of the current insn in the insn group. */
7914 int prev_in_use
, in_use
, len
;
7917 /* Let shorten branches care for assigning alignments to code labels. */
7918 shorten_branches (insns
);
7920 if (align_functions
< 4)
7922 else if ((unsigned int) align_functions
< max_align
)
7923 align
= align_functions
;
7927 ofs
= prev_in_use
= 0;
7929 if (GET_CODE (i
) == NOTE
)
7930 i
= next_nonnote_insn (i
);
7934 next
= (*next_group
) (i
, &in_use
, &len
);
7936 /* When we see a label, resync alignment etc. */
7937 if (GET_CODE (i
) == CODE_LABEL
)
7939 unsigned int new_align
= 1 << label_to_alignment (i
);
7941 if (new_align
>= align
)
7943 align
= new_align
< max_align
? new_align
: max_align
;
7947 else if (ofs
& (new_align
-1))
7948 ofs
= (ofs
| (new_align
-1)) + 1;
7953 /* Handle complex instructions special. */
7954 else if (in_use
== 0)
7956 /* Asms will have length < 0. This is a signal that we have
7957 lost alignment knowledge. Assume, however, that the asm
7958 will not mis-align instructions. */
7967 /* If the known alignment is smaller than the recognized insn group,
7968 realign the output. */
7969 else if ((int) align
< len
)
7971 unsigned int new_log_align
= len
> 8 ? 4 : 3;
7974 where
= prev
= prev_nonnote_insn (i
);
7975 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
7978 /* Can't realign between a call and its gp reload. */
7979 if (! (TARGET_EXPLICIT_RELOCS
7980 && prev
&& GET_CODE (prev
) == CALL_INSN
))
7982 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
7983 align
= 1 << new_log_align
;
7988 /* If the group won't fit in the same INT16 as the previous,
7989 we need to add padding to keep the group together. Rather
7990 than simply leaving the insn filling to the assembler, we
7991 can make use of the knowledge of what sorts of instructions
7992 were issued in the previous group to make sure that all of
7993 the added nops are really free. */
7994 else if (ofs
+ len
> (int) align
)
7996 int nop_count
= (align
- ofs
) / 4;
7999 /* Insert nops before labels, branches, and calls to truely merge
8000 the execution of the nops with the previous instruction group. */
8001 where
= prev_nonnote_insn (i
);
8004 if (GET_CODE (where
) == CODE_LABEL
)
8006 rtx where2
= prev_nonnote_insn (where
);
8007 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
8010 else if (GET_CODE (where
) == INSN
)
8017 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
8018 while (--nop_count
);
8022 ofs
= (ofs
+ len
) & (align
- 1);
8023 prev_in_use
= in_use
;
8028 /* Machine dependent reorg pass. */
8034 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
8035 alpha_handle_trap_shadows (insns
);
8037 /* Due to the number of extra trapb insns, don't bother fixing up
8038 alignment when trap precision is instruction. Moreover, we can
8039 only do our job when sched2 is run. */
8040 if (optimize
&& !optimize_size
8041 && alpha_tp
!= ALPHA_TP_INSN
8042 && flag_schedule_insns_after_reload
)
8044 if (alpha_cpu
== PROCESSOR_EV4
)
8045 alpha_align_insns (insns
, 8, alphaev4_next_group
, alphaev4_next_nop
);
8046 else if (alpha_cpu
== PROCESSOR_EV5
)
8047 alpha_align_insns (insns
, 16, alphaev5_next_group
, alphaev5_next_nop
);
8051 /* Check a floating-point value for validity for a particular machine mode. */
8053 static const char * const float_strings
[] =
8055 /* These are for FLOAT_VAX. */
8056 "1.70141173319264430e+38", /* 2^127 (2^24 - 1) / 2^24 */
8057 "-1.70141173319264430e+38",
8058 "2.93873587705571877e-39", /* 2^-128 */
8059 "-2.93873587705571877e-39",
8060 /* These are for the default broken IEEE mode, which traps
8061 on infinity or denormal numbers. */
8062 "3.402823466385288598117e+38", /* 2^128 (1 - 2^-24) */
8063 "-3.402823466385288598117e+38",
8064 "1.1754943508222875079687e-38", /* 2^-126 */
8065 "-1.1754943508222875079687e-38",
8068 static REAL_VALUE_TYPE float_values
[8];
8069 static int inited_float_values
= 0;
8072 check_float_value (mode
, d
, overflow
)
8073 enum machine_mode mode
;
8075 int overflow ATTRIBUTE_UNUSED
;
8078 if (TARGET_IEEE
|| TARGET_IEEE_CONFORMANT
|| TARGET_IEEE_WITH_INEXACT
)
8081 if (inited_float_values
== 0)
8084 for (i
= 0; i
< 8; i
++)
8085 float_values
[i
] = REAL_VALUE_ATOF (float_strings
[i
], DFmode
);
8087 inited_float_values
= 1;
8093 REAL_VALUE_TYPE
*fvptr
;
8095 if (TARGET_FLOAT_VAX
)
8096 fvptr
= &float_values
[0];
8098 fvptr
= &float_values
[4];
8100 memcpy (&r
, d
, sizeof (REAL_VALUE_TYPE
));
8101 if (REAL_VALUES_LESS (fvptr
[0], r
))
8103 memcpy (d
, &fvptr
[0], sizeof (REAL_VALUE_TYPE
));
8106 else if (REAL_VALUES_LESS (r
, fvptr
[1]))
8108 memcpy (d
, &fvptr
[1], sizeof (REAL_VALUE_TYPE
));
8111 else if (REAL_VALUES_LESS (dconst0
, r
)
8112 && REAL_VALUES_LESS (r
, fvptr
[2]))
8114 memcpy (d
, &dconst0
, sizeof (REAL_VALUE_TYPE
));
8117 else if (REAL_VALUES_LESS (r
, dconst0
)
8118 && REAL_VALUES_LESS (fvptr
[3], r
))
8120 memcpy (d
, &dconst0
, sizeof (REAL_VALUE_TYPE
));
8128 #if TARGET_ABI_OPEN_VMS
8130 /* Return the VMS argument type corresponding to MODE. */
8133 alpha_arg_type (mode
)
8134 enum machine_mode mode
;
8139 return TARGET_FLOAT_VAX
? FF
: FS
;
8141 return TARGET_FLOAT_VAX
? FD
: FT
;
8147 /* Return an rtx for an integer representing the VMS Argument Information
8151 alpha_arg_info_reg_val (cum
)
8152 CUMULATIVE_ARGS cum
;
8154 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
8157 for (i
= 0; i
< 6; i
++)
8158 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
8160 return GEN_INT (regval
);
8163 #include <splay-tree.h>
8165 /* Structure to collect function names for final output
8168 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
8173 enum links_kind kind
;
8176 static splay_tree alpha_links
;
8178 static int mark_alpha_links_node
PARAMS ((splay_tree_node
, void *));
8179 static void mark_alpha_links
PARAMS ((void *));
8180 static int alpha_write_one_linkage
PARAMS ((splay_tree_node
, void *));
8182 /* Protect alpha_links from garbage collection. */
8185 mark_alpha_links_node (node
, data
)
8186 splay_tree_node node
;
8187 void *data ATTRIBUTE_UNUSED
;
8189 struct alpha_links
*links
= (struct alpha_links
*) node
->value
;
8190 ggc_mark_rtx (links
->linkage
);
8195 mark_alpha_links (ptr
)
8198 splay_tree tree
= *(splay_tree
*) ptr
;
8199 splay_tree_foreach (tree
, mark_alpha_links_node
, NULL
);
8202 /* Make (or fake) .linkage entry for function call.
8204 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
8206 Return an SYMBOL_REF rtx for the linkage. */
8209 alpha_need_linkage (name
, is_local
)
8213 splay_tree_node node
;
8214 struct alpha_links
*al
;
8221 /* Is this name already defined? */
8223 node
= splay_tree_lookup (alpha_links
, (splay_tree_key
) name
);
8226 al
= (struct alpha_links
*) node
->value
;
8229 /* Defined here but external assumed. */
8230 if (al
->kind
== KIND_EXTERN
)
8231 al
->kind
= KIND_LOCAL
;
8235 /* Used here but unused assumed. */
8236 if (al
->kind
== KIND_UNUSED
)
8237 al
->kind
= KIND_LOCAL
;
8244 alpha_links
= splay_tree_new ((splay_tree_compare_fn
) strcmp
,
8245 (splay_tree_delete_key_fn
) free
,
8246 (splay_tree_delete_key_fn
) free
);
8247 ggc_add_root (&alpha_links
, 1, 1, mark_alpha_links
);
8250 al
= (struct alpha_links
*) xmalloc (sizeof (struct alpha_links
));
8251 name
= xstrdup (name
);
8253 /* Assume external if no definition. */
8254 al
->kind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
8256 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
8257 get_identifier (name
);
8259 /* Construct a SYMBOL_REF for us to call. */
8261 size_t name_len
= strlen (name
);
8262 char *linksym
= alloca (name_len
+ 6);
8264 memcpy (linksym
+ 1, name
, name_len
);
8265 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
8266 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
8267 ggc_alloc_string (linksym
, name_len
+ 5));
8270 splay_tree_insert (alpha_links
, (splay_tree_key
) name
,
8271 (splay_tree_value
) al
);
8277 alpha_write_one_linkage (node
, data
)
8278 splay_tree_node node
;
8281 const char *const name
= (const char *) node
->key
;
8282 struct alpha_links
*links
= (struct alpha_links
*) node
->value
;
8283 FILE *stream
= (FILE *) data
;
8285 if (links
->kind
== KIND_UNUSED
8286 || ! TREE_SYMBOL_REFERENCED (get_identifier (name
)))
8289 fprintf (stream
, "$%s..lk:\n", name
);
8290 if (links
->kind
== KIND_LOCAL
)
8292 /* Local and used, build linkage pair. */
8293 fprintf (stream
, "\t.quad %s..en\n", name
);
8294 fprintf (stream
, "\t.quad %s\n", name
);
8298 /* External and used, request linkage pair. */
8299 fprintf (stream
, "\t.linkage %s\n", name
);
8306 alpha_write_linkage (stream
)
8311 readonly_section ();
8312 fprintf (stream
, "\t.align 3\n");
8313 splay_tree_foreach (alpha_links
, alpha_write_one_linkage
, stream
);
8317 /* Given a decl, a section name, and whether the decl initializer
8318 has relocs, choose attributes for the section. */
8320 #define SECTION_VMS_OVERLAY SECTION_FORGET
8321 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
8322 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
8325 vms_section_type_flags (decl
, name
, reloc
)
8330 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
8332 if (decl
&& DECL_ATTRIBUTES (decl
)
8333 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
8334 flags
|= SECTION_VMS_OVERLAY
;
8335 if (decl
&& DECL_ATTRIBUTES (decl
)
8336 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
8337 flags
|= SECTION_VMS_GLOBAL
;
8338 if (decl
&& DECL_ATTRIBUTES (decl
)
8339 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
8340 flags
|= SECTION_VMS_INITIALIZE
;
8345 /* Switch to an arbitrary section NAME with attributes as specified
8346 by FLAGS. ALIGN specifies any known alignment requirements for
8347 the section; 0 if the default should be used. */
8350 vms_asm_named_section (name
, flags
)
8354 fputc ('\n', asm_out_file
);
8355 fprintf (asm_out_file
, ".section\t%s", name
);
8357 if (flags
& SECTION_VMS_OVERLAY
)
8358 fprintf (asm_out_file
, ",OVR");
8359 if (flags
& SECTION_VMS_GLOBAL
)
8360 fprintf (asm_out_file
, ",GBL");
8361 if (flags
& SECTION_VMS_INITIALIZE
)
8362 fprintf (asm_out_file
, ",NOMOD");
8363 if (flags
& SECTION_DEBUG
)
8364 fprintf (asm_out_file
, ",NOWRT");
8366 fputc ('\n', asm_out_file
);
8369 /* Record an element in the table of global constructors. SYMBOL is
8370 a SYMBOL_REF of the function to be called; PRIORITY is a number
8371 between 0 and MAX_INIT_PRIORITY.
8373 Differs from default_ctors_section_asm_out_constructor in that the
8374 width of the .ctors entry is always 64 bits, rather than the 32 bits
8375 used by a normal pointer. */
8378 vms_asm_out_constructor (symbol
, priority
)
8380 int priority ATTRIBUTE_UNUSED
;
8383 assemble_align (BITS_PER_WORD
);
8384 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
8388 vms_asm_out_destructor (symbol
, priority
)
8390 int priority ATTRIBUTE_UNUSED
;
8393 assemble_align (BITS_PER_WORD
);
8394 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
8399 alpha_need_linkage (name
, is_local
)
8400 const char *name ATTRIBUTE_UNUSED
;
8401 int is_local ATTRIBUTE_UNUSED
;
8406 #endif /* TARGET_ABI_OPEN_VMS */
8408 #if TARGET_ABI_UNICOSMK
8410 static void unicosmk_output_module_name
PARAMS ((FILE *));
8411 static void unicosmk_output_default_externs
PARAMS ((FILE *));
8412 static void unicosmk_output_dex
PARAMS ((FILE *));
8413 static void unicosmk_output_externs
PARAMS ((FILE *));
8414 static void unicosmk_output_addr_vec
PARAMS ((FILE *, rtx
));
8415 static const char *unicosmk_ssib_name
PARAMS ((void));
8416 static int unicosmk_special_name
PARAMS ((const char *));
8418 /* Define the offset between two registers, one to be eliminated, and the
8419 other its replacement, at the start of a routine. */
8422 unicosmk_initial_elimination_offset (from
, to
)
8428 fixed_size
= alpha_sa_size();
8429 if (fixed_size
!= 0)
8432 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
8434 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
8436 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
8437 return (ALPHA_ROUND (current_function_outgoing_args_size
)
8438 + ALPHA_ROUND (get_frame_size()));
8439 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
8440 return (ALPHA_ROUND (fixed_size
)
8441 + ALPHA_ROUND (get_frame_size()
8442 + current_function_outgoing_args_size
));
8447 /* Output the module name for .ident and .end directives. We have to strip
8448 directories and add make sure that the module name starts with a letter
8452 unicosmk_output_module_name (file
)
8457 /* Strip directories. */
8459 name
= strrchr (main_input_filename
, '/');
8463 name
= main_input_filename
;
8465 /* CAM only accepts module names that start with a letter or '$'. We
8466 prefix the module name with a '$' if necessary. */
8468 if (!ISALPHA (*name
))
8469 fprintf (file
, "$%s", name
);
8474 /* Output text that to appear at the beginning of an assembler file. */
8477 unicosmk_asm_file_start (file
)
8482 fputs ("\t.ident\t", file
);
8483 unicosmk_output_module_name (file
);
8484 fputs ("\n\n", file
);
8486 /* The Unicos/Mk assembler uses different register names. Instead of trying
8487 to support them, we simply use micro definitions. */
8489 /* CAM has different register names: rN for the integer register N and fN
8490 for the floating-point register N. Instead of trying to use these in
8491 alpha.md, we define the symbols $N and $fN to refer to the appropriate
8494 for (i
= 0; i
< 32; ++i
)
8495 fprintf (file
, "$%d <- r%d\n", i
, i
);
8497 for (i
= 0; i
< 32; ++i
)
8498 fprintf (file
, "$f%d <- f%d\n", i
, i
);
8502 /* The .align directive fill unused space with zeroes which does not work
8503 in code sections. We define the macro 'gcc@code@align' which uses nops
8504 instead. Note that it assumes that code sections always have the
8505 biggest possible alignment since . refers to the current offset from
8506 the beginning of the section. */
8508 fputs ("\t.macro gcc@code@align n\n", file
);
8509 fputs ("gcc@n@bytes = 1 << n\n", file
);
8510 fputs ("gcc@here = . % gcc@n@bytes\n", file
);
8511 fputs ("\t.if ne, gcc@here, 0\n", file
);
8512 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", file
);
8513 fputs ("\tbis r31,r31,r31\n", file
);
8514 fputs ("\t.endr\n", file
);
8515 fputs ("\t.endif\n", file
);
8516 fputs ("\t.endm gcc@code@align\n\n", file
);
8518 /* Output extern declarations which should always be visible. */
8519 unicosmk_output_default_externs (file
);
8521 /* Open a dummy section. We always need to be inside a section for the
8522 section-switching code to work correctly.
8523 ??? This should be a module id or something like that. I still have to
8524 figure out what the rules for those are. */
8525 fputs ("\n\t.psect\t$SG00000,data\n", file
);
8528 /* Output text to appear at the end of an assembler file. This includes all
8529 pending extern declarations and DEX expressions. */
8532 unicosmk_asm_file_end (file
)
8535 fputs ("\t.endp\n\n", file
);
8537 /* Output all pending externs. */
8539 unicosmk_output_externs (file
);
8541 /* Output dex definitions used for functions whose names conflict with
8544 unicosmk_output_dex (file
);
8546 fputs ("\t.end\t", file
);
8547 unicosmk_output_module_name (file
);
8551 /* Output the definition of a common variable. */
8554 unicosmk_output_common (file
, name
, size
, align
)
8561 printf ("T3E__: common %s\n", name
);
8564 fputs("\t.endp\n\n\t.psect ", file
);
8565 assemble_name(file
, name
);
8566 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
8567 fprintf(file
, "\t.byte\t0:%d\n", size
);
8569 /* Mark the symbol as defined in this module. */
8570 name_tree
= get_identifier (name
);
8571 TREE_ASM_WRITTEN (name_tree
) = 1;
8574 #define SECTION_PUBLIC SECTION_MACH_DEP
8575 #define SECTION_MAIN (SECTION_PUBLIC << 1)
8576 static int current_section_align
;
8579 unicosmk_section_type_flags (decl
, name
, reloc
)
8582 int reloc ATTRIBUTE_UNUSED
;
8584 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
8589 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8591 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
8592 if (align_functions_log
> current_section_align
)
8593 current_section_align
= align_functions_log
;
8595 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
8596 flags
|= SECTION_MAIN
;
8599 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
8601 if (TREE_PUBLIC (decl
))
8602 flags
|= SECTION_PUBLIC
;
8607 /* Generate a section name for decl and associate it with the
8611 unicosmk_unique_section (decl
, reloc
)
8613 int reloc ATTRIBUTE_UNUSED
;
8621 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
8622 STRIP_NAME_ENCODING (name
, name
);
8623 len
= strlen (name
);
8625 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8629 /* It is essential that we prefix the section name here because
8630 otherwise the section names generated for constructors and
8631 destructors confuse collect2. */
8633 string
= alloca (len
+ 6);
8634 sprintf (string
, "code@%s", name
);
8635 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
8637 else if (TREE_PUBLIC (decl
))
8638 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
8643 string
= alloca (len
+ 6);
8644 sprintf (string
, "data@%s", name
);
8645 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
8649 /* Switch to an arbitrary section NAME with attributes as specified
8650 by FLAGS. ALIGN specifies any known alignment requirements for
8651 the section; 0 if the default should be used. */
8654 unicosmk_asm_named_section (name
, flags
)
8660 /* Close the previous section. */
8662 fputs ("\t.endp\n\n", asm_out_file
);
8664 /* Find out what kind of section we are opening. */
8666 if (flags
& SECTION_MAIN
)
8667 fputs ("\t.start\tmain\n", asm_out_file
);
8669 if (flags
& SECTION_CODE
)
8671 else if (flags
& SECTION_PUBLIC
)
8676 if (current_section_align
!= 0)
8677 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
8678 current_section_align
, kind
);
8680 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
8684 unicosmk_insert_attributes (decl
, attr_ptr
)
8686 tree
*attr_ptr ATTRIBUTE_UNUSED
;
8689 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
8690 UNIQUE_SECTION (decl
, 0);
8693 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
8694 in code sections because .align fill unused space with zeroes. */
8697 unicosmk_output_align (file
, align
)
8701 if (inside_function
)
8702 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
8704 fprintf (file
, "\t.align\t%d\n", align
);
8707 /* Add a case vector to the current function's list of deferred case
8708 vectors. Case vectors have to be put into a separate section because CAM
8709 does not allow data definitions in code sections. */
8712 unicosmk_defer_case_vector (lab
, vec
)
8716 struct machine_function
*machine
= cfun
->machine
;
8718 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
8719 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
8720 machine
->addr_list
);
8723 /* Output a case vector. */
8726 unicosmk_output_addr_vec (file
, vec
)
8730 rtx lab
= XEXP (vec
, 0);
8731 rtx body
= XEXP (vec
, 1);
8732 int vlen
= XVECLEN (body
, 0);
8735 ASM_OUTPUT_INTERNAL_LABEL (file
, "L", CODE_LABEL_NUMBER (lab
));
8737 for (idx
= 0; idx
< vlen
; idx
++)
8739 ASM_OUTPUT_ADDR_VEC_ELT
8740 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
8744 /* Output current function's deferred case vectors. */
8747 unicosmk_output_deferred_case_vectors (file
)
8750 struct machine_function
*machine
= cfun
->machine
;
8753 if (machine
->addr_list
== NULL_RTX
)
8757 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
8758 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
8761 /* Set up the dynamic subprogram information block (DSIB) and update the
8762 frame pointer register ($15) for subroutines which have a frame. If the
8763 subroutine doesn't have a frame, simply increment $15. */
8766 unicosmk_gen_dsib (imaskP
)
8767 unsigned long * imaskP
;
8769 if (alpha_procedure_type
== PT_STACK
)
8771 const char *ssib_name
;
8774 /* Allocate 64 bytes for the DSIB. */
8776 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8778 emit_insn (gen_blockage ());
8780 /* Save the return address. */
8782 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
8783 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8784 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
8785 (*imaskP
) &= ~(1L << REG_RA
);
8787 /* Save the old frame pointer. */
8789 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
8790 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8791 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
8792 (*imaskP
) &= ~(1L << HARD_FRAME_POINTER_REGNUM
);
8794 emit_insn (gen_blockage ());
8796 /* Store the SSIB pointer. */
8798 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
8799 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
8800 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8802 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
8803 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
8804 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
8806 /* Save the CIW index. */
8808 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
8809 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8810 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
8812 emit_insn (gen_blockage ());
8814 /* Set the new frame pointer. */
8816 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8817 stack_pointer_rtx
, GEN_INT (64))));
8822 /* Increment the frame pointer register to indicate that we do not
8825 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8826 hard_frame_pointer_rtx
, GEN_INT (1))));
8830 #define SSIB_PREFIX "__SSIB_"
8831 #define SSIB_PREFIX_LEN 7
8833 /* Generate the name of the SSIB section for the current function. */
8836 unicosmk_ssib_name ()
8838 /* This is ok since CAM won't be able to deal with names longer than that
8841 static char name
[256];
8847 x
= DECL_RTL (cfun
->decl
);
8848 if (GET_CODE (x
) != MEM
)
8851 if (GET_CODE (x
) != SYMBOL_REF
)
8853 fnname
= XSTR (x
, 0);
8854 STRIP_NAME_ENCODING (fnname
, fnname
);
8856 len
= strlen (fnname
);
8857 if (len
+ SSIB_PREFIX_LEN
> 255)
8858 len
= 255 - SSIB_PREFIX_LEN
;
8860 strcpy (name
, SSIB_PREFIX
);
8861 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
8862 name
[len
+ SSIB_PREFIX_LEN
] = 0;
8867 /* Output the static subroutine information block for the current
8871 unicosmk_output_ssib (file
, fnname
)
8879 struct machine_function
*machine
= cfun
->machine
;
8882 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
8883 unicosmk_ssib_name ());
8885 /* Some required stuff and the function name length. */
8887 len
= strlen (fnname
);
8888 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
8891 ??? We don't do that yet. */
8893 fputs ("\t.quad\t0\n", file
);
8895 /* Function address. */
8897 fputs ("\t.quad\t", file
);
8898 assemble_name (file
, fnname
);
8901 fputs ("\t.quad\t0\n", file
);
8902 fputs ("\t.quad\t0\n", file
);
8905 ??? We do it the same way Cray CC does it but this could be
8908 for( i
= 0; i
< len
; i
++ )
8909 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
8910 if( (len
% 8) == 0 )
8911 fputs ("\t.quad\t0\n", file
);
8913 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
8915 /* All call information words used in the function. */
8917 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
8920 fprintf (file
, "\t.quad\t");
8921 #if HOST_BITS_PER_WIDE_INT == 32
8922 fprintf (file
, HOST_WIDE_INT_PRINT_DOUBLE_HEX
,
8923 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
8925 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (ciw
));
8927 fprintf (file
, "\n");
8931 /* Add a call information word (CIW) to the list of the current function's
8932 CIWs and return its index.
8934 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
8937 unicosmk_add_call_info_word (x
)
8941 struct machine_function
*machine
= cfun
->machine
;
8943 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
8944 if (machine
->first_ciw
== NULL_RTX
)
8945 machine
->first_ciw
= node
;
8947 XEXP (machine
->last_ciw
, 1) = node
;
8949 machine
->last_ciw
= node
;
8950 ++machine
->ciw_count
;
8952 return GEN_INT (machine
->ciw_count
8953 + strlen (current_function_name
)/8 + 5);
8956 static char unicosmk_section_buf
[100];
8959 unicosmk_text_section ()
8961 static int count
= 0;
8962 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
8964 return unicosmk_section_buf
;
8968 unicosmk_data_section ()
8970 static int count
= 1;
8971 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
8973 return unicosmk_section_buf
;
8976 /* The Cray assembler doesn't accept extern declarations for symbols which
8977 are defined in the same file. We have to keep track of all global
8978 symbols which are referenced and/or defined in a source file and output
8979 extern declarations for those which are referenced but not defined at
8982 /* List of identifiers for which an extern declaration might have to be
8985 struct unicosmk_extern_list
8987 struct unicosmk_extern_list
*next
;
8991 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
8993 /* Output extern declarations which are required for every asm file. */
8996 unicosmk_output_default_externs (file
)
8999 static const char *const externs
[] =
9000 { "__T3E_MISMATCH" };
9005 n
= ARRAY_SIZE (externs
);
9007 for (i
= 0; i
< n
; i
++)
9008 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
9011 /* Output extern declarations for global symbols which are have been
9012 referenced but not defined. */
9015 unicosmk_output_externs (file
)
9018 struct unicosmk_extern_list
*p
;
9019 const char *real_name
;
9023 len
= strlen (user_label_prefix
);
9024 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
9026 /* We have to strip the encoding and possibly remove user_label_prefix
9027 from the identifier in order to handle -fleading-underscore and
9028 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9029 STRIP_NAME_ENCODING (real_name
, p
->name
);
9030 if (len
&& p
->name
[0] == '*'
9031 && !memcmp (real_name
, user_label_prefix
, len
))
9034 name_tree
= get_identifier (real_name
);
9035 if (! TREE_ASM_WRITTEN (name_tree
))
9037 TREE_ASM_WRITTEN (name_tree
) = 1;
9038 fputs ("\t.extern\t", file
);
9039 assemble_name (file
, p
->name
);
9045 /* Record an extern. */
9048 unicosmk_add_extern (name
)
9051 struct unicosmk_extern_list
*p
;
9053 p
= (struct unicosmk_extern_list
*)
9054 permalloc (sizeof (struct unicosmk_extern_list
));
9055 p
->next
= unicosmk_extern_head
;
9057 unicosmk_extern_head
= p
;
9060 /* The Cray assembler generates incorrect code if identifiers which
9061 conflict with register names are used as instruction operands. We have
9062 to replace such identifiers with DEX expressions. */
9064 /* Structure to collect identifiers which have been replaced by DEX
9067 struct unicosmk_dex
{
9068 struct unicosmk_dex
*next
;
9072 /* List of identifiers which have been replaced by DEX expressions. The DEX
9073 number is determined by the position in the list. */
9075 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
9077 /* The number of elements in the DEX list. */
9079 static int unicosmk_dex_count
= 0;
9081 /* Check if NAME must be replaced by a DEX expression. */
9084 unicosmk_special_name (name
)
9093 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
9099 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
9102 return (name
[2] == '\0'
9103 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
9106 return (ISDIGIT (name
[1]) && name
[2] == '\0');
9110 /* Return the DEX number if X must be replaced by a DEX expression and 0
9114 unicosmk_need_dex (x
)
9117 struct unicosmk_dex
*dex
;
9121 if (GET_CODE (x
) != SYMBOL_REF
)
9125 if (! unicosmk_special_name (name
))
9128 i
= unicosmk_dex_count
;
9129 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9131 if (! strcmp (name
, dex
->name
))
9136 dex
= (struct unicosmk_dex
*) permalloc (sizeof (struct unicosmk_dex
));
9138 dex
->next
= unicosmk_dex_list
;
9139 unicosmk_dex_list
= dex
;
9141 ++unicosmk_dex_count
;
9142 return unicosmk_dex_count
;
9145 /* Output the DEX definitions for this file. */
9148 unicosmk_output_dex (file
)
9151 struct unicosmk_dex
*dex
;
9154 if (unicosmk_dex_list
== NULL
)
9157 fprintf (file
, "\t.dexstart\n");
9159 i
= unicosmk_dex_count
;
9160 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9162 fprintf (file
, "\tDEX (%d) = ", i
);
9163 assemble_name (file
, dex
->name
);
9168 fprintf (file
, "\t.dexend\n");
9174 unicosmk_output_deferred_case_vectors (file
)
9175 FILE *file ATTRIBUTE_UNUSED
;
9179 unicosmk_gen_dsib (imaskP
)
9180 unsigned long * imaskP ATTRIBUTE_UNUSED
;
9184 unicosmk_output_ssib (file
, fnname
)
9185 FILE * file ATTRIBUTE_UNUSED
;
9186 const char * fnname ATTRIBUTE_UNUSED
;
9190 unicosmk_add_call_info_word (x
)
9191 rtx x ATTRIBUTE_UNUSED
;
9197 unicosmk_need_dex (x
)
9198 rtx x ATTRIBUTE_UNUSED
;
9203 #endif /* TARGET_ABI_UNICOSMK */