1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
54 /* Specify which cpu to schedule for. */
56 enum processor_type alpha_cpu
;
57 static const char * const alpha_cpu_name
[] =
62 /* Specify how accurate floating-point traps need to be. */
64 enum alpha_trap_precision alpha_tp
;
66 /* Specify the floating-point rounding mode. */
68 enum alpha_fp_rounding_mode alpha_fprm
;
70 /* Specify which things cause traps. */
72 enum alpha_fp_trap_mode alpha_fptm
;
74 /* Specify bit size of immediate TLS offsets. */
76 int alpha_tls_size
= 32;
78 /* Strings decoded into the above options. */
80 const char *alpha_cpu_string
; /* -mcpu= */
81 const char *alpha_tune_string
; /* -mtune= */
82 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
83 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
84 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
85 const char *alpha_mlat_string
; /* -mmemory-latency= */
86 const char *alpha_tls_size_string
; /* -mtls-size=[16|32|64] */
88 /* Save information from a "cmpxx" operation until the branch or scc is
91 struct alpha_compare alpha_compare
;
93 /* Nonzero if inside of a function, because the Alpha asm can't
94 handle .files inside of functions. */
96 static int inside_function
= FALSE
;
98 /* The number of cycles of latency we should assume on memory reads. */
100 int alpha_memory_latency
= 3;
102 /* Whether the function needs the GP. */
104 static int alpha_function_needs_gp
;
106 /* The alias set for prologue/epilogue register save/restore. */
108 static int alpha_sr_alias_set
;
110 /* The assembler name of the current function. */
112 static const char *alpha_fnname
;
114 /* The next explicit relocation sequence number. */
115 int alpha_next_sequence_number
= 1;
117 /* The literal and gpdisp sequence numbers for this insn, as printed
118 by %# and %* respectively. */
119 int alpha_this_literal_sequence_number
;
120 int alpha_this_gpdisp_sequence_number
;
122 /* Declarations of static functions. */
123 static bool alpha_function_ok_for_sibcall
124 PARAMS ((tree
, tree
));
125 static int tls_symbolic_operand_1
126 PARAMS ((rtx
, enum machine_mode
, int, int));
127 static enum tls_model tls_symbolic_operand_type
129 static bool decl_in_text_section
131 static bool decl_has_samegp
133 static bool alpha_in_small_data_p
135 static void alpha_encode_section_info
136 PARAMS ((tree
, int));
137 static const char *alpha_strip_name_encoding
138 PARAMS ((const char *));
139 static int some_small_symbolic_operand_1
140 PARAMS ((rtx
*, void *));
141 static int split_small_symbolic_operand_1
142 PARAMS ((rtx
*, void *));
143 static void alpha_set_memflags_1
144 PARAMS ((rtx
, int, int, int));
145 static rtx alpha_emit_set_const_1
146 PARAMS ((rtx
, enum machine_mode
, HOST_WIDE_INT
, int));
147 static void alpha_expand_unaligned_load_words
148 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
149 static void alpha_expand_unaligned_store_words
150 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
151 static void alpha_init_builtins
153 static rtx alpha_expand_builtin
154 PARAMS ((tree
, rtx
, rtx
, enum machine_mode
, int));
155 static void alpha_sa_mask
156 PARAMS ((unsigned long *imaskP
, unsigned long *fmaskP
));
157 static int find_lo_sum
158 PARAMS ((rtx
*, void *));
159 static int alpha_does_function_need_gp
161 static int alpha_ra_ever_killed
163 static const char *get_trap_mode_suffix
165 static const char *get_round_mode_suffix
167 static const char *get_some_local_dynamic_name
169 static int get_some_local_dynamic_name_1
170 PARAMS ((rtx
*, void *));
171 static rtx set_frame_related_p
173 static const char *alpha_lookup_xfloating_lib_func
174 PARAMS ((enum rtx_code
));
175 static int alpha_compute_xfloating_mode_arg
176 PARAMS ((enum rtx_code
, enum alpha_fp_rounding_mode
));
177 static void alpha_emit_xfloating_libcall
178 PARAMS ((const char *, rtx
, rtx
[], int, rtx
));
179 static rtx alpha_emit_xfloating_compare
180 PARAMS ((enum rtx_code
, rtx
, rtx
));
181 static void alpha_output_function_end_prologue
183 static int alpha_adjust_cost
184 PARAMS ((rtx
, rtx
, rtx
, int));
185 static int alpha_issue_rate
187 static int alpha_use_dfa_pipeline_interface
189 static int alpha_multipass_dfa_lookahead
192 #ifdef OBJECT_FORMAT_ELF
193 static void alpha_elf_select_rtx_section
194 PARAMS ((enum machine_mode
, rtx
, unsigned HOST_WIDE_INT
));
197 #if TARGET_ABI_OPEN_VMS
198 static bool alpha_linkage_symbol_p
199 PARAMS ((const char *symname
));
200 static void alpha_write_linkage
201 PARAMS ((FILE *, const char *, tree
));
205 static void alpha_output_mi_thunk_osf
206 PARAMS ((FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
));
209 static struct machine_function
* alpha_init_machine_status
212 static void unicosmk_output_deferred_case_vectors
PARAMS ((FILE *));
213 static void unicosmk_gen_dsib
PARAMS ((unsigned long *imaskP
));
214 static void unicosmk_output_ssib
PARAMS ((FILE *, const char *));
215 static int unicosmk_need_dex
PARAMS ((rtx
));
217 /* Get the number of args of a function in one of two ways. */
218 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
219 #define NUM_ARGS current_function_args_info.num_args
221 #define NUM_ARGS current_function_args_info
227 /* Initialize the GCC target structure. */
228 #if TARGET_ABI_OPEN_VMS
229 const struct attribute_spec vms_attribute_table
[];
230 static unsigned int vms_section_type_flags
PARAMS ((tree
, const char *, int));
231 static void vms_asm_named_section
PARAMS ((const char *, unsigned int));
232 static void vms_asm_out_constructor
PARAMS ((rtx
, int));
233 static void vms_asm_out_destructor
PARAMS ((rtx
, int));
234 # undef TARGET_ATTRIBUTE_TABLE
235 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
236 # undef TARGET_SECTION_TYPE_FLAGS
237 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
240 #undef TARGET_IN_SMALL_DATA_P
241 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
242 #undef TARGET_ENCODE_SECTION_INFO
243 #define TARGET_ENCODE_SECTION_INFO alpha_encode_section_info
244 #undef TARGET_STRIP_NAME_ENCODING
245 #define TARGET_STRIP_NAME_ENCODING alpha_strip_name_encoding
247 #if TARGET_ABI_UNICOSMK
248 static void unicosmk_asm_named_section
PARAMS ((const char *, unsigned int));
249 static void unicosmk_insert_attributes
PARAMS ((tree
, tree
*));
250 static unsigned int unicosmk_section_type_flags
PARAMS ((tree
, const char *,
252 static void unicosmk_unique_section
PARAMS ((tree
, int));
253 # undef TARGET_INSERT_ATTRIBUTES
254 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
255 # undef TARGET_SECTION_TYPE_FLAGS
256 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
257 # undef TARGET_ASM_UNIQUE_SECTION
258 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
259 # undef TARGET_ASM_GLOBALIZE_LABEL
260 # define TARGET_ASM_GLOBALIZE_LABEL hook_FILEptr_constcharptr_void
263 #undef TARGET_ASM_ALIGNED_HI_OP
264 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
265 #undef TARGET_ASM_ALIGNED_DI_OP
266 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
268 /* Default unaligned ops are provided for ELF systems. To get unaligned
269 data for non-ELF systems, we have to turn off auto alignment. */
270 #ifndef OBJECT_FORMAT_ELF
271 #undef TARGET_ASM_UNALIGNED_HI_OP
272 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
273 #undef TARGET_ASM_UNALIGNED_SI_OP
274 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
275 #undef TARGET_ASM_UNALIGNED_DI_OP
276 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
279 #ifdef OBJECT_FORMAT_ELF
280 #undef TARGET_ASM_SELECT_RTX_SECTION
281 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
284 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
285 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
287 #undef TARGET_SCHED_ADJUST_COST
288 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
289 #undef TARGET_SCHED_ISSUE_RATE
290 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
291 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
292 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
293 alpha_use_dfa_pipeline_interface
294 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
295 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
296 alpha_multipass_dfa_lookahead
298 #undef TARGET_HAVE_TLS
299 #define TARGET_HAVE_TLS HAVE_AS_TLS
301 #undef TARGET_INIT_BUILTINS
302 #define TARGET_INIT_BUILTINS alpha_init_builtins
303 #undef TARGET_EXPAND_BUILTIN
304 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
306 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
307 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
310 #undef TARGET_ASM_OUTPUT_MI_THUNK
311 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
312 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
313 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
316 struct gcc_target targetm
= TARGET_INITIALIZER
;
318 /* Parse target option strings. */
324 static const struct cpu_table
{
325 const char *const name
;
326 const enum processor_type processor
;
329 #define EV5_MASK (MASK_CPU_EV5)
330 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
331 { "ev4", PROCESSOR_EV4
, 0 },
332 { "ev45", PROCESSOR_EV4
, 0 },
333 { "21064", PROCESSOR_EV4
, 0 },
334 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
335 { "21164", PROCESSOR_EV5
, EV5_MASK
},
336 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
337 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
338 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
339 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
340 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
341 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
342 { "21264", PROCESSOR_EV6
, EV6_MASK
},
343 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
344 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
348 /* Unicos/Mk doesn't have shared libraries. */
349 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
351 warning ("-f%s ignored for Unicos/Mk (not supported)",
352 (flag_pic
> 1) ? "PIC" : "pic");
356 /* On Unicos/Mk, the native compiler consistenly generates /d suffices for
357 floating-point instructions. Make that the default for this target. */
358 if (TARGET_ABI_UNICOSMK
)
359 alpha_fprm
= ALPHA_FPRM_DYN
;
361 alpha_fprm
= ALPHA_FPRM_NORM
;
363 alpha_tp
= ALPHA_TP_PROG
;
364 alpha_fptm
= ALPHA_FPTM_N
;
366 /* We cannot use su and sui qualifiers for conversion instructions on
367 Unicos/Mk. I'm not sure if this is due to assembler or hardware
368 limitations. Right now, we issue a warning if -mieee is specified
369 and then ignore it; eventually, we should either get it right or
370 disable the option altogether. */
374 if (TARGET_ABI_UNICOSMK
)
375 warning ("-mieee not supported on Unicos/Mk");
378 alpha_tp
= ALPHA_TP_INSN
;
379 alpha_fptm
= ALPHA_FPTM_SU
;
383 if (TARGET_IEEE_WITH_INEXACT
)
385 if (TARGET_ABI_UNICOSMK
)
386 warning ("-mieee-with-inexact not supported on Unicos/Mk");
389 alpha_tp
= ALPHA_TP_INSN
;
390 alpha_fptm
= ALPHA_FPTM_SUI
;
396 if (! strcmp (alpha_tp_string
, "p"))
397 alpha_tp
= ALPHA_TP_PROG
;
398 else if (! strcmp (alpha_tp_string
, "f"))
399 alpha_tp
= ALPHA_TP_FUNC
;
400 else if (! strcmp (alpha_tp_string
, "i"))
401 alpha_tp
= ALPHA_TP_INSN
;
403 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string
);
406 if (alpha_fprm_string
)
408 if (! strcmp (alpha_fprm_string
, "n"))
409 alpha_fprm
= ALPHA_FPRM_NORM
;
410 else if (! strcmp (alpha_fprm_string
, "m"))
411 alpha_fprm
= ALPHA_FPRM_MINF
;
412 else if (! strcmp (alpha_fprm_string
, "c"))
413 alpha_fprm
= ALPHA_FPRM_CHOP
;
414 else if (! strcmp (alpha_fprm_string
,"d"))
415 alpha_fprm
= ALPHA_FPRM_DYN
;
417 error ("bad value `%s' for -mfp-rounding-mode switch",
421 if (alpha_fptm_string
)
423 if (strcmp (alpha_fptm_string
, "n") == 0)
424 alpha_fptm
= ALPHA_FPTM_N
;
425 else if (strcmp (alpha_fptm_string
, "u") == 0)
426 alpha_fptm
= ALPHA_FPTM_U
;
427 else if (strcmp (alpha_fptm_string
, "su") == 0)
428 alpha_fptm
= ALPHA_FPTM_SU
;
429 else if (strcmp (alpha_fptm_string
, "sui") == 0)
430 alpha_fptm
= ALPHA_FPTM_SUI
;
432 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string
);
435 if (alpha_tls_size_string
)
437 if (strcmp (alpha_tls_size_string
, "16") == 0)
439 else if (strcmp (alpha_tls_size_string
, "32") == 0)
441 else if (strcmp (alpha_tls_size_string
, "64") == 0)
444 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string
);
448 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
449 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
451 if (alpha_cpu_string
)
453 for (i
= 0; cpu_table
[i
].name
; i
++)
454 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
456 alpha_cpu
= cpu_table
[i
].processor
;
457 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
458 | MASK_CPU_EV5
| MASK_CPU_EV6
);
459 target_flags
|= cpu_table
[i
].flags
;
462 if (! cpu_table
[i
].name
)
463 error ("bad value `%s' for -mcpu switch", alpha_cpu_string
);
466 if (alpha_tune_string
)
468 for (i
= 0; cpu_table
[i
].name
; i
++)
469 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
471 alpha_cpu
= cpu_table
[i
].processor
;
474 if (! cpu_table
[i
].name
)
475 error ("bad value `%s' for -mcpu switch", alpha_tune_string
);
478 /* Do some sanity checks on the above options. */
480 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
482 warning ("trap mode not supported on Unicos/Mk");
483 alpha_fptm
= ALPHA_FPTM_N
;
486 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
487 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
489 warning ("fp software completion requires -mtrap-precision=i");
490 alpha_tp
= ALPHA_TP_INSN
;
495 /* Except for EV6 pass 1 (not released), we always have precise
496 arithmetic traps. Which means we can do software completion
497 without minding trap shadows. */
498 alpha_tp
= ALPHA_TP_PROG
;
501 if (TARGET_FLOAT_VAX
)
503 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
505 warning ("rounding mode not supported for VAX floats");
506 alpha_fprm
= ALPHA_FPRM_NORM
;
508 if (alpha_fptm
== ALPHA_FPTM_SUI
)
510 warning ("trap mode not supported for VAX floats");
511 alpha_fptm
= ALPHA_FPTM_SU
;
519 if (!alpha_mlat_string
)
520 alpha_mlat_string
= "L1";
522 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
523 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
525 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
526 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
527 && alpha_mlat_string
[2] == '\0')
529 static int const cache_latency
[][4] =
531 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
532 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
533 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
536 lat
= alpha_mlat_string
[1] - '0';
537 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
539 warning ("L%d cache latency unknown for %s",
540 lat
, alpha_cpu_name
[alpha_cpu
]);
544 lat
= cache_latency
[alpha_cpu
][lat
-1];
546 else if (! strcmp (alpha_mlat_string
, "main"))
548 /* Most current memories have about 370ns latency. This is
549 a reasonable guess for a fast cpu. */
554 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string
);
558 alpha_memory_latency
= lat
;
561 /* Default the definition of "small data" to 8 bytes. */
565 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
567 target_flags
|= MASK_SMALL_DATA
;
568 else if (flag_pic
== 2)
569 target_flags
&= ~MASK_SMALL_DATA
;
571 /* Align labels and loops for optimal branching. */
572 /* ??? Kludge these by not doing anything if we don't optimize and also if
573 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
574 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
576 if (align_loops
<= 0)
578 if (align_jumps
<= 0)
581 if (align_functions
<= 0)
582 align_functions
= 16;
584 /* Acquire a unique set number for our register saves and restores. */
585 alpha_sr_alias_set
= new_alias_set ();
587 /* Register variables and functions with the garbage collector. */
589 /* Set up function hooks. */
590 init_machine_status
= alpha_init_machine_status
;
592 /* Tell the compiler when we're using VAX floating point. */
593 if (TARGET_FLOAT_VAX
)
595 real_format_for_mode
[SFmode
- QFmode
] = &vax_f_format
;
596 real_format_for_mode
[DFmode
- QFmode
] = &vax_g_format
;
597 real_format_for_mode
[TFmode
- QFmode
] = NULL
;
601 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
609 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
611 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
617 /* Returns 1 if OP is either the constant zero or a register. If a
618 register, it must be in the proper mode unless MODE is VOIDmode. */
621 reg_or_0_operand (op
, mode
)
623 enum machine_mode mode
;
625 return op
== CONST0_RTX (mode
) || register_operand (op
, mode
);
628 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
632 reg_or_6bit_operand (op
, mode
)
634 enum machine_mode mode
;
636 return ((GET_CODE (op
) == CONST_INT
637 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64)
638 || register_operand (op
, mode
));
642 /* Return 1 if OP is an 8-bit constant or any register. */
645 reg_or_8bit_operand (op
, mode
)
647 enum machine_mode mode
;
649 return ((GET_CODE (op
) == CONST_INT
650 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
651 || register_operand (op
, mode
));
654 /* Return 1 if OP is a constant or any register. */
657 reg_or_const_int_operand (op
, mode
)
659 enum machine_mode mode
;
661 return GET_CODE (op
) == CONST_INT
|| register_operand (op
, mode
);
664 /* Return 1 if OP is an 8-bit constant. */
667 cint8_operand (op
, mode
)
669 enum machine_mode mode ATTRIBUTE_UNUSED
;
671 return ((GET_CODE (op
) == CONST_INT
672 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100));
675 /* Return 1 if the operand is a valid second operand to an add insn. */
678 add_operand (op
, mode
)
680 enum machine_mode mode
;
682 if (GET_CODE (op
) == CONST_INT
)
683 /* Constraints I, J, O and P are covered by K. */
684 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K')
685 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
687 return register_operand (op
, mode
);
690 /* Return 1 if the operand is a valid second operand to a sign-extending
694 sext_add_operand (op
, mode
)
696 enum machine_mode mode
;
698 if (GET_CODE (op
) == CONST_INT
)
699 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
700 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'));
702 return reg_not_elim_operand (op
, mode
);
705 /* Return 1 if OP is the constant 4 or 8. */
708 const48_operand (op
, mode
)
710 enum machine_mode mode ATTRIBUTE_UNUSED
;
712 return (GET_CODE (op
) == CONST_INT
713 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
716 /* Return 1 if OP is a valid first operand to an AND insn. */
719 and_operand (op
, mode
)
721 enum machine_mode mode
;
723 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
724 return (zap_mask (CONST_DOUBLE_LOW (op
))
725 && zap_mask (CONST_DOUBLE_HIGH (op
)));
727 if (GET_CODE (op
) == CONST_INT
)
728 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
729 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
730 || zap_mask (INTVAL (op
)));
732 return register_operand (op
, mode
);
735 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
738 or_operand (op
, mode
)
740 enum machine_mode mode
;
742 if (GET_CODE (op
) == CONST_INT
)
743 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
744 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100);
746 return register_operand (op
, mode
);
749 /* Return 1 if OP is a constant that is the width, in bits, of an integral
750 mode smaller than DImode. */
753 mode_width_operand (op
, mode
)
755 enum machine_mode mode ATTRIBUTE_UNUSED
;
757 return (GET_CODE (op
) == CONST_INT
758 && (INTVAL (op
) == 8 || INTVAL (op
) == 16
759 || INTVAL (op
) == 32 || INTVAL (op
) == 64));
762 /* Return 1 if OP is a constant that is the width of an integral machine mode
763 smaller than an integer. */
766 mode_mask_operand (op
, mode
)
768 enum machine_mode mode ATTRIBUTE_UNUSED
;
770 if (GET_CODE (op
) == CONST_INT
)
772 HOST_WIDE_INT value
= INTVAL (op
);
778 if (value
== 0xffffffff)
783 else if (HOST_BITS_PER_WIDE_INT
== 32 && GET_CODE (op
) == CONST_DOUBLE
)
785 if (CONST_DOUBLE_LOW (op
) == 0xffffffff && CONST_DOUBLE_HIGH (op
) == 0)
792 /* Return 1 if OP is a multiple of 8 less than 64. */
795 mul8_operand (op
, mode
)
797 enum machine_mode mode ATTRIBUTE_UNUSED
;
799 return (GET_CODE (op
) == CONST_INT
800 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
801 && (INTVAL (op
) & 7) == 0);
804 /* Return 1 if OP is the zero constant for MODE. */
807 const0_operand (op
, mode
)
809 enum machine_mode mode
;
811 return op
== CONST0_RTX (mode
);
814 /* Return 1 if OP is a hard floating-point register. */
817 hard_fp_register_operand (op
, mode
)
819 enum machine_mode mode
;
821 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
824 if (GET_CODE (op
) == SUBREG
)
825 op
= SUBREG_REG (op
);
826 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == FLOAT_REGS
;
829 /* Return 1 if OP is a hard general register. */
832 hard_int_register_operand (op
, mode
)
834 enum machine_mode mode
;
836 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
839 if (GET_CODE (op
) == SUBREG
)
840 op
= SUBREG_REG (op
);
841 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
;
844 /* Return 1 if OP is a register or a constant integer. */
848 reg_or_cint_operand (op
, mode
)
850 enum machine_mode mode
;
852 return (GET_CODE (op
) == CONST_INT
853 || register_operand (op
, mode
));
856 /* Return 1 if OP is something that can be reloaded into a register;
857 if it is a MEM, it need not be valid. */
860 some_operand (op
, mode
)
862 enum machine_mode mode
;
864 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
867 switch (GET_CODE (op
))
881 return some_operand (SUBREG_REG (op
), VOIDmode
);
890 /* Likewise, but don't accept constants. */
893 some_ni_operand (op
, mode
)
895 enum machine_mode mode
;
897 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
900 if (GET_CODE (op
) == SUBREG
)
901 op
= SUBREG_REG (op
);
903 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == MEM
);
906 /* Return 1 if OP is a valid operand for the source of a move insn. */
909 input_operand (op
, mode
)
911 enum machine_mode mode
;
913 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
916 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
919 switch (GET_CODE (op
))
924 if (TARGET_EXPLICIT_RELOCS
)
926 /* We don't split symbolic operands into something unintelligable
927 until after reload, but we do not wish non-small, non-global
928 symbolic operands to be reconstructed from their high/lo_sum
930 return (small_symbolic_operand (op
, mode
)
931 || global_symbolic_operand (op
, mode
)
932 || gotdtp_symbolic_operand (op
, mode
)
933 || gottp_symbolic_operand (op
, mode
));
936 /* This handles both the Windows/NT and OSF cases. */
937 return mode
== ptr_mode
|| mode
== DImode
;
940 return (TARGET_EXPLICIT_RELOCS
941 && local_symbolic_operand (XEXP (op
, 0), mode
));
948 if (register_operand (op
, mode
))
950 /* ... fall through ... */
952 return ((TARGET_BWX
|| (mode
!= HImode
&& mode
!= QImode
))
953 && general_operand (op
, mode
));
957 return op
== CONST0_RTX (mode
);
960 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
972 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
973 file, and in the same section as the current function. */
976 samegp_function_operand (op
, mode
)
978 enum machine_mode mode ATTRIBUTE_UNUSED
;
980 if (GET_CODE (op
) != SYMBOL_REF
)
983 /* Easy test for recursion. */
984 if (op
== XEXP (DECL_RTL (current_function_decl
), 0))
987 /* Otherwise, encode_section_info recorded whether we are to treat
988 this symbol as having the same GP. */
989 return SYMBOL_REF_FLAG (op
);
992 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
995 direct_call_operand (op
, mode
)
997 enum machine_mode mode
;
999 /* Must share the same GP. */
1000 if (!samegp_function_operand (op
, mode
))
1003 /* If profiling is implemented via linker tricks, we can't jump
1004 to the nogp alternate entry point. Note that current_function_profile
1005 would not be correct, since that doesn't indicate if the target
1006 function uses profiling. */
1007 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
1008 but is approximately correct for the OSF ABIs. Don't know
1009 what to do for VMS, NT, or UMK. */
1010 if (!TARGET_PROFILING_NEEDS_GP
&& profile_flag
)
1013 /* Must be "near" so that the branch is assumed to reach. With
1014 -msmall-text, this is true of all local symbols. */
1015 if (TARGET_SMALL_TEXT
)
1018 /* Otherwise, a decl is "near" if it is defined in the same section.
1019 See alpha_encode_section_info for commentary. */
1020 return op
->jump
&& decl_in_text_section (cfun
->decl
);
1023 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
1024 a (non-tls) variable known to be defined in this file. */
1027 local_symbolic_operand (op
, mode
)
1029 enum machine_mode mode
;
1033 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1036 if (GET_CODE (op
) == LABEL_REF
)
1039 if (GET_CODE (op
) == CONST
1040 && GET_CODE (XEXP (op
, 0)) == PLUS
1041 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1042 op
= XEXP (XEXP (op
, 0), 0);
1044 if (GET_CODE (op
) != SYMBOL_REF
)
1047 /* Easy pickings. */
1048 if (CONSTANT_POOL_ADDRESS_P (op
) || STRING_POOL_ADDRESS_P (op
))
1051 /* ??? SYMBOL_REF_FLAG is set for local function symbols, but we
1052 run into problems with the rtl inliner in that the symbol was
1053 once external, but is local after inlining, which results in
1054 unrecognizable insns. */
1058 /* If @[LS], then alpha_encode_section_info sez it's local. */
1059 if (str
[0] == '@' && (str
[1] == 'L' || str
[1] == 'S'))
1062 /* If *$, then ASM_GENERATE_INTERNAL_LABEL sez it's local. */
1063 if (str
[0] == '*' && str
[1] == '$')
1069 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1070 known to be defined in this file in the small data area. */
1073 small_symbolic_operand (op
, mode
)
1075 enum machine_mode mode ATTRIBUTE_UNUSED
;
1079 if (! TARGET_SMALL_DATA
)
1082 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1085 if (GET_CODE (op
) == CONST
1086 && GET_CODE (XEXP (op
, 0)) == PLUS
1087 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1088 op
= XEXP (XEXP (op
, 0), 0);
1090 if (GET_CODE (op
) != SYMBOL_REF
)
1093 if (CONSTANT_POOL_ADDRESS_P (op
))
1094 return GET_MODE_SIZE (get_pool_mode (op
)) <= (unsigned) g_switch_value
;
1098 return str
[0] == '@' && str
[1] == 'S';
1102 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1103 not known (or known not) to be defined in this file. */
1106 global_symbolic_operand (op
, mode
)
1108 enum machine_mode mode
;
1112 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1115 if (GET_CODE (op
) == CONST
1116 && GET_CODE (XEXP (op
, 0)) == PLUS
1117 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1118 op
= XEXP (XEXP (op
, 0), 0);
1120 if (GET_CODE (op
) != SYMBOL_REF
)
1123 if (local_symbolic_operand (op
, mode
))
1126 /* Also verify that it's not a TLS symbol. */
1128 return str
[0] != '%' && str
[0] != '@';
1131 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
1134 call_operand (op
, mode
)
1136 enum machine_mode mode
;
1141 if (GET_CODE (op
) == REG
)
1145 /* Disallow virtual registers to cope with pathalogical test cases
1146 such as compile/930117-1.c in which the virtual reg decomposes
1147 to the frame pointer. Which is a hard reg that is not $27. */
1148 return (REGNO (op
) == 27 || REGNO (op
) > LAST_VIRTUAL_REGISTER
);
1153 if (TARGET_ABI_UNICOSMK
)
1155 if (GET_CODE (op
) == SYMBOL_REF
)
1161 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1162 possibly with an offset. */
1165 symbolic_operand (op
, mode
)
1167 enum machine_mode mode
;
1169 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1171 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1173 if (GET_CODE (op
) == CONST
1174 && GET_CODE (XEXP (op
,0)) == PLUS
1175 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1176 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1181 /* Return true if OP is valid for a particular TLS relocation. */
1184 tls_symbolic_operand_1 (op
, mode
, size
, unspec
)
1186 enum machine_mode mode
;
1191 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1194 if (GET_CODE (op
) != CONST
)
1198 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
1200 op
= XVECEXP (op
, 0, 0);
1202 if (GET_CODE (op
) != SYMBOL_REF
)
1211 else if (str
[0] == '@')
1213 if (alpha_tls_size
> size
)
1222 return unspec
== UNSPEC_DTPREL
;
1224 return unspec
== UNSPEC_TPREL
&& size
== 64;
1226 return unspec
== UNSPEC_TPREL
&& size
< 64;
1232 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1235 dtp16_symbolic_operand (op
, mode
)
1237 enum machine_mode mode
;
1239 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_DTPREL
);
1242 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1245 dtp32_symbolic_operand (op
, mode
)
1247 enum machine_mode mode
;
1249 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_DTPREL
);
1252 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1255 gotdtp_symbolic_operand (op
, mode
)
1257 enum machine_mode mode
;
1259 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_DTPREL
);
1262 /* Return true if OP is valid for 16-bit TP relative relocations. */
1265 tp16_symbolic_operand (op
, mode
)
1267 enum machine_mode mode
;
1269 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_TPREL
);
1272 /* Return true if OP is valid for 32-bit TP relative relocations. */
1275 tp32_symbolic_operand (op
, mode
)
1277 enum machine_mode mode
;
1279 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_TPREL
);
1282 /* Return true if OP is valid for 64-bit TP relative relocations. */
1285 gottp_symbolic_operand (op
, mode
)
1287 enum machine_mode mode
;
1289 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_TPREL
);
1292 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1293 comparisons are valid in which insn. */
1296 alpha_comparison_operator (op
, mode
)
1298 enum machine_mode mode
;
1300 enum rtx_code code
= GET_CODE (op
);
1302 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1305 return (code
== EQ
|| code
== LE
|| code
== LT
1306 || code
== LEU
|| code
== LTU
);
1309 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1310 Here we know which comparisons are valid in which insn. */
1313 alpha_zero_comparison_operator (op
, mode
)
1315 enum machine_mode mode
;
1317 enum rtx_code code
= GET_CODE (op
);
1319 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1322 return (code
== EQ
|| code
== NE
|| code
== LE
|| code
== LT
1323 || code
== LEU
|| code
== LTU
);
1326 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1329 alpha_swapped_comparison_operator (op
, mode
)
1331 enum machine_mode mode
;
1333 enum rtx_code code
= GET_CODE (op
);
1335 if ((mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1336 || GET_RTX_CLASS (code
) != '<')
1339 code
= swap_condition (code
);
1340 return (code
== EQ
|| code
== LE
|| code
== LT
1341 || code
== LEU
|| code
== LTU
);
1344 /* Return 1 if OP is a signed comparison operation. */
1347 signed_comparison_operator (op
, mode
)
1349 enum machine_mode mode ATTRIBUTE_UNUSED
;
1351 enum rtx_code code
= GET_CODE (op
);
1353 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1356 return (code
== EQ
|| code
== NE
1357 || code
== LE
|| code
== LT
1358 || code
== GE
|| code
== GT
);
1361 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1362 Here we know which comparisons are valid in which insn. */
1365 alpha_fp_comparison_operator (op
, mode
)
1367 enum machine_mode mode
;
1369 enum rtx_code code
= GET_CODE (op
);
1371 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1374 return (code
== EQ
|| code
== LE
|| code
== LT
|| code
== UNORDERED
);
1377 /* Return 1 if this is a divide or modulus operator. */
1380 divmod_operator (op
, mode
)
1382 enum machine_mode mode ATTRIBUTE_UNUSED
;
1384 switch (GET_CODE (op
))
1386 case DIV
: case MOD
: case UDIV
: case UMOD
:
1396 /* Return 1 if this memory address is a known aligned register plus
1397 a constant. It must be a valid address. This means that we can do
1398 this as an aligned reference plus some offset.
1400 Take into account what reload will do. */
1403 aligned_memory_operand (op
, mode
)
1405 enum machine_mode mode
;
1409 if (reload_in_progress
)
1412 if (GET_CODE (tmp
) == SUBREG
)
1413 tmp
= SUBREG_REG (tmp
);
1414 if (GET_CODE (tmp
) == REG
1415 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1417 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1423 if (GET_CODE (op
) != MEM
1424 || GET_MODE (op
) != mode
)
1428 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1429 sorts of constructs. Dig for the real base register. */
1430 if (reload_in_progress
1431 && GET_CODE (op
) == PLUS
1432 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1433 base
= XEXP (XEXP (op
, 0), 0);
1436 if (! memory_address_p (mode
, op
))
1438 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1441 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) >= 32);
1444 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1447 unaligned_memory_operand (op
, mode
)
1449 enum machine_mode mode
;
1453 if (reload_in_progress
)
1456 if (GET_CODE (tmp
) == SUBREG
)
1457 tmp
= SUBREG_REG (tmp
);
1458 if (GET_CODE (tmp
) == REG
1459 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1461 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1467 if (GET_CODE (op
) != MEM
1468 || GET_MODE (op
) != mode
)
1472 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1473 sorts of constructs. Dig for the real base register. */
1474 if (reload_in_progress
1475 && GET_CODE (op
) == PLUS
1476 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1477 base
= XEXP (XEXP (op
, 0), 0);
1480 if (! memory_address_p (mode
, op
))
1482 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1485 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) < 32);
1488 /* Return 1 if OP is either a register or an unaligned memory location. */
1491 reg_or_unaligned_mem_operand (op
, mode
)
1493 enum machine_mode mode
;
1495 return register_operand (op
, mode
) || unaligned_memory_operand (op
, mode
);
1498 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1501 any_memory_operand (op
, mode
)
1503 enum machine_mode mode ATTRIBUTE_UNUSED
;
1505 return (GET_CODE (op
) == MEM
1506 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
1507 || (reload_in_progress
&& GET_CODE (op
) == REG
1508 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1509 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
1510 && GET_CODE (SUBREG_REG (op
)) == REG
1511 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
1514 /* Returns 1 if OP is not an eliminable register.
1516 This exists to cure a pathological abort in the s8addq (et al) patterns,
1518 long foo () { long t; bar(); return (long) &t * 26107; }
1520 which run afoul of a hack in reload to cure a (presumably) similar
1521 problem with lea-type instructions on other targets. But there is
1522 one of us and many of them, so work around the problem by selectively
1523 preventing combine from making the optimization. */
1526 reg_not_elim_operand (op
, mode
)
1528 enum machine_mode mode
;
1531 if (GET_CODE (op
) == SUBREG
)
1532 inner
= SUBREG_REG (op
);
1533 if (inner
== frame_pointer_rtx
|| inner
== arg_pointer_rtx
)
1536 return register_operand (op
, mode
);
1539 /* Return 1 is OP is a memory location that is not a reference (using
1540 an AND) to an unaligned location. Take into account what reload
1544 normal_memory_operand (op
, mode
)
1546 enum machine_mode mode ATTRIBUTE_UNUSED
;
1548 if (reload_in_progress
)
1551 if (GET_CODE (tmp
) == SUBREG
)
1552 tmp
= SUBREG_REG (tmp
);
1553 if (GET_CODE (tmp
) == REG
1554 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1556 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1558 /* This may not have been assigned an equivalent address if it will
1559 be eliminated. In that case, it doesn't matter what we do. */
1565 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) != AND
;
1568 /* Accept a register, but not a subreg of any kind. This allows us to
1569 avoid pathological cases in reload wrt data movement common in
1570 int->fp conversion. */
1573 reg_no_subreg_operand (op
, mode
)
1575 enum machine_mode mode
;
1577 if (GET_CODE (op
) != REG
)
1579 return register_operand (op
, mode
);
1582 /* Recognize an addition operation that includes a constant. Used to
1583 convince reload to canonize (plus (plus reg c1) c2) during register
1587 addition_operation (op
, mode
)
1589 enum machine_mode mode
;
1591 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1593 if (GET_CODE (op
) == PLUS
1594 && register_operand (XEXP (op
, 0), mode
)
1595 && GET_CODE (XEXP (op
, 1)) == CONST_INT
1596 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op
, 1)), 'K'))
1601 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1602 the range defined for C in [I-P]. */
1605 alpha_const_ok_for_letter_p (value
, c
)
1606 HOST_WIDE_INT value
;
1612 /* An unsigned 8 bit constant. */
1613 return (unsigned HOST_WIDE_INT
) value
< 0x100;
1615 /* The constant zero. */
1618 /* A signed 16 bit constant. */
1619 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
1621 /* A shifted signed 16 bit constant appropriate for LDAH. */
1622 return ((value
& 0xffff) == 0
1623 && ((value
) >> 31 == -1 || value
>> 31 == 0));
1625 /* A constant that can be AND'ed with using a ZAP insn. */
1626 return zap_mask (value
);
1628 /* A complemented unsigned 8 bit constant. */
1629 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
1631 /* A negated unsigned 8 bit constant. */
1632 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
1634 /* The constant 1, 2 or 3. */
1635 return value
== 1 || value
== 2 || value
== 3;
1642 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1643 matches for C in [GH]. */
1646 alpha_const_double_ok_for_letter_p (value
, c
)
1653 /* The floating point zero constant. */
1654 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
1655 && value
== CONST0_RTX (GET_MODE (value
)));
1658 /* A valid operand of a ZAP insn. */
1659 return (GET_MODE (value
) == VOIDmode
1660 && zap_mask (CONST_DOUBLE_LOW (value
))
1661 && zap_mask (CONST_DOUBLE_HIGH (value
)));
1668 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1672 alpha_extra_constraint (value
, c
)
1679 return normal_memory_operand (value
, VOIDmode
);
1681 return direct_call_operand (value
, Pmode
);
1683 return (GET_CODE (value
) == CONST_INT
1684 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
1686 return GET_CODE (value
) == HIGH
;
1688 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
1690 return (GET_CODE (value
) == CONST_VECTOR
1691 && value
== CONST0_RTX (GET_MODE (value
)));
1697 /* Return 1 if this function can directly return via $26. */
1702 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
1704 && alpha_sa_size () == 0
1705 && get_frame_size () == 0
1706 && current_function_outgoing_args_size
== 0
1707 && current_function_pretend_args_size
== 0);
1710 /* Return the ADDR_VEC associated with a tablejump insn. */
1713 alpha_tablejump_addr_vec (insn
)
1718 tmp
= JUMP_LABEL (insn
);
1721 tmp
= NEXT_INSN (tmp
);
1724 if (GET_CODE (tmp
) == JUMP_INSN
1725 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
1726 return PATTERN (tmp
);
1730 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1733 alpha_tablejump_best_label (insn
)
1736 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
1737 rtx best_label
= NULL_RTX
;
1739 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1740 there for edge frequency counts from profile data. */
1744 int n_labels
= XVECLEN (jump_table
, 1);
1745 int best_count
= -1;
1748 for (i
= 0; i
< n_labels
; i
++)
1752 for (j
= i
+ 1; j
< n_labels
; j
++)
1753 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
1754 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
1757 if (count
> best_count
)
1758 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
1762 return best_label
? best_label
: const0_rtx
;
1765 /* Return the TLS model to use for SYMBOL. */
1767 static enum tls_model
1768 tls_symbolic_operand_type (symbol
)
1773 if (GET_CODE (symbol
) != SYMBOL_REF
)
1775 str
= XSTR (symbol
, 0);
1779 /* ??? Be prepared for -ftls-model=local-dynamic. Perhaps we shouldn't
1780 have separately encoded local-ness. On well, maybe the user will use
1781 attribute visibility next time. At least we don't crash... */
1782 if (str
[1] == 'G' || str
[1] == 'D')
1783 return TLS_MODEL_GLOBAL_DYNAMIC
;
1785 return TLS_MODEL_INITIAL_EXEC
;
1787 else if (str
[0] == '@')
1791 /* Local dynamic is a waste if we're not going to combine
1792 the __tls_get_addr calls. So avoid it if not optimizing. */
1794 return TLS_MODEL_LOCAL_DYNAMIC
;
1796 return TLS_MODEL_GLOBAL_DYNAMIC
;
1799 return TLS_MODEL_INITIAL_EXEC
;
1801 return TLS_MODEL_LOCAL_EXEC
;
1808 /* Return true if the function DECL will be placed in the default text
1810 /* ??? Ideally we'd be able to always move from a SYMBOL_REF back to the
1811 decl, as that would allow us to determine if two functions are in the
1812 same section, which is what we really want to know. */
1815 decl_in_text_section (decl
)
1818 return (DECL_SECTION_NAME (decl
) == NULL_TREE
1819 && ! (flag_function_sections
1820 || (targetm
.have_named_sections
1821 && DECL_ONE_ONLY (decl
))));
1824 /* Return true if the function DECL will share the same GP as any
1825 function in the current unit of translation. */
1828 decl_has_samegp (decl
)
1831 /* Functions that are not local can be overridden, and thus may
1832 not share the same gp. */
1833 if (!(*targetm
.binds_local_p
) (decl
))
1836 /* If -msmall-data is in effect, assume that there is only one GP
1837 for the module, and so any local symbol has this property. We
1838 need explicit relocations to be able to enforce this for symbols
1839 not defined in this unit of translation, however. */
1840 if (TARGET_EXPLICIT_RELOCS
&& TARGET_SMALL_DATA
)
1843 /* Functions that are not external are defined in this UoT. */
1844 return !DECL_EXTERNAL (decl
);
1847 /* Return true if EXP should be placed in the small data section. */
1850 alpha_in_small_data_p (exp
)
1853 /* We want to merge strings, so we never consider them small data. */
1854 if (TREE_CODE (exp
) == STRING_CST
)
1857 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
1859 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
1860 if (strcmp (section
, ".sdata") == 0
1861 || strcmp (section
, ".sbss") == 0)
1866 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
1868 /* If this is an incomplete type with size 0, then we can't put it
1869 in sdata because it might be too big when completed. */
1870 if (size
> 0 && size
<= g_switch_value
)
1877 /* If we are referencing a function that is static, make the SYMBOL_REF
1878 special. We use this to see indicate we can branch to this function
1879 without setting PV or restoring GP.
1881 If this is a variable that is known to be defined locally, add "@v"
1882 to the name. If in addition the variable is to go in .sdata/.sbss,
1883 then add "@s" instead. */
1886 alpha_encode_section_info (decl
, first
)
1888 int first ATTRIBUTE_UNUSED
;
1890 const char *symbol_str
;
1895 rtl
= DECL_P (decl
) ? DECL_RTL (decl
) : TREE_CST_RTL (decl
);
1897 /* Careful not to prod global register variables. */
1898 if (GET_CODE (rtl
) != MEM
)
1900 symbol
= XEXP (rtl
, 0);
1901 if (GET_CODE (symbol
) != SYMBOL_REF
)
1904 /* A variable is considered "local" if it is defined in this module. */
1905 is_local
= (*targetm
.binds_local_p
) (decl
);
1907 if (TREE_CODE (decl
) == FUNCTION_DECL
)
1909 /* Mark whether the decl is "near" in distance. If -msmall-text is
1910 in effect, this is trivially true of all local symbols. */
1911 if (TARGET_SMALL_TEXT
)
1918 /* Otherwise, a decl is "near" if it is defined in this same
1919 section. What we really need is to be able to access the
1920 target decl of a call from the call_insn pattern, so that
1921 we can determine if the call is from the same section. We
1922 can't do that at present, so handle the common case and
1923 match up .text with .text.
1925 Delay marking public functions until they are emitted; otherwise
1926 we don't know that they exist in this unit of translation. */
1927 if (!TREE_PUBLIC (decl
) && decl_in_text_section (decl
))
1931 /* Indicate whether the target function shares the same GP as any
1932 function emitted in this unit of translation. */
1933 if (decl_has_samegp (decl
))
1934 SYMBOL_REF_FLAG (symbol
) = 1;
1938 /* Early out if we're not going to do anything with this data. */
1939 if (! TARGET_EXPLICIT_RELOCS
)
1942 symbol_str
= XSTR (symbol
, 0);
1944 /* Care for TLS variables. */
1945 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL (decl
))
1947 switch (decl_tls_model (decl
))
1949 case TLS_MODEL_GLOBAL_DYNAMIC
:
1952 case TLS_MODEL_LOCAL_DYNAMIC
:
1955 case TLS_MODEL_INITIAL_EXEC
:
1958 case TLS_MODEL_LOCAL_EXEC
:
1959 encoding
= (alpha_tls_size
== 64 ? 'T' : 't');
1965 /* Determine if DECL will wind up in .sdata/.sbss. */
1966 if (alpha_in_small_data_p (decl
))
1972 /* Finally, encode this into the symbol string. */
1977 char want_prefix
= (is_local
? '@' : '%');
1978 char other_prefix
= (is_local
? '%' : '@');
1980 if (symbol_str
[0] == want_prefix
)
1982 if (symbol_str
[1] == encoding
)
1986 else if (symbol_str
[0] == other_prefix
)
1989 len
= strlen (symbol_str
) + 1;
1990 newstr
= alloca (len
+ 2);
1992 newstr
[0] = want_prefix
;
1993 newstr
[1] = encoding
;
1994 memcpy (newstr
+ 2, symbol_str
, len
);
1996 XSTR (symbol
, 0) = ggc_alloc_string (newstr
, len
+ 2 - 1);
2000 /* Undo the effects of the above. */
2003 alpha_strip_name_encoding (str
)
2006 if (str
[0] == '@' || str
[0] == '%')
2013 #if TARGET_ABI_OPEN_VMS
2015 alpha_linkage_symbol_p (symname
)
2016 const char *symname
;
2018 int symlen
= strlen (symname
);
2021 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
2026 #define LINKAGE_SYMBOL_REF_P(X) \
2027 ((GET_CODE (X) == SYMBOL_REF \
2028 && alpha_linkage_symbol_p (XSTR (X, 0))) \
2029 || (GET_CODE (X) == CONST \
2030 && GET_CODE (XEXP (X, 0)) == PLUS \
2031 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
2032 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
2035 /* legitimate_address_p recognizes an RTL expression that is a valid
2036 memory address for an instruction. The MODE argument is the
2037 machine mode for the MEM expression that wants to use this address.
2039 For Alpha, we have either a constant address or the sum of a
2040 register and a constant address, or just a register. For DImode,
2041 any of those forms can be surrounded with an AND that clear the
2042 low-order three bits; this is an "unaligned" access. */
2045 alpha_legitimate_address_p (mode
, x
, strict
)
2046 enum machine_mode mode
;
2050 /* If this is an ldq_u type address, discard the outer AND. */
2052 && GET_CODE (x
) == AND
2053 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2054 && INTVAL (XEXP (x
, 1)) == -8)
2057 /* Discard non-paradoxical subregs. */
2058 if (GET_CODE (x
) == SUBREG
2059 && (GET_MODE_SIZE (GET_MODE (x
))
2060 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2063 /* Unadorned general registers are valid. */
2066 ? STRICT_REG_OK_FOR_BASE_P (x
)
2067 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
2070 /* Constant addresses (i.e. +/- 32k) are valid. */
2071 if (CONSTANT_ADDRESS_P (x
))
2074 #if TARGET_ABI_OPEN_VMS
2075 if (LINKAGE_SYMBOL_REF_P (x
))
2079 /* Register plus a small constant offset is valid. */
2080 if (GET_CODE (x
) == PLUS
)
2082 rtx ofs
= XEXP (x
, 1);
2085 /* Discard non-paradoxical subregs. */
2086 if (GET_CODE (x
) == SUBREG
2087 && (GET_MODE_SIZE (GET_MODE (x
))
2088 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2094 && NONSTRICT_REG_OK_FP_BASE_P (x
)
2095 && GET_CODE (ofs
) == CONST_INT
)
2098 ? STRICT_REG_OK_FOR_BASE_P (x
)
2099 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
2100 && CONSTANT_ADDRESS_P (ofs
))
2103 else if (GET_CODE (x
) == ADDRESSOF
2104 && GET_CODE (ofs
) == CONST_INT
)
2108 /* If we're managing explicit relocations, LO_SUM is valid, as
2109 are small data symbols. */
2110 else if (TARGET_EXPLICIT_RELOCS
)
2112 if (small_symbolic_operand (x
, Pmode
))
2115 if (GET_CODE (x
) == LO_SUM
)
2117 rtx ofs
= XEXP (x
, 1);
2120 /* Discard non-paradoxical subregs. */
2121 if (GET_CODE (x
) == SUBREG
2122 && (GET_MODE_SIZE (GET_MODE (x
))
2123 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2126 /* Must have a valid base register. */
2129 ? STRICT_REG_OK_FOR_BASE_P (x
)
2130 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
2133 /* The symbol must be local. */
2134 if (local_symbolic_operand (ofs
, Pmode
)
2135 || dtp32_symbolic_operand (ofs
, Pmode
)
2136 || tp32_symbolic_operand (ofs
, Pmode
))
2144 /* Try machine-dependent ways of modifying an illegitimate address
2145 to be legitimate. If we find one, return the new, valid address. */
2148 alpha_legitimize_address (x
, scratch
, mode
)
2151 enum machine_mode mode ATTRIBUTE_UNUSED
;
2153 HOST_WIDE_INT addend
;
2155 /* If the address is (plus reg const_int) and the CONST_INT is not a
2156 valid offset, compute the high part of the constant and add it to
2157 the register. Then our address is (plus temp low-part-const). */
2158 if (GET_CODE (x
) == PLUS
2159 && GET_CODE (XEXP (x
, 0)) == REG
2160 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2161 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
2163 addend
= INTVAL (XEXP (x
, 1));
2168 /* If the address is (const (plus FOO const_int)), find the low-order
2169 part of the CONST_INT. Then load FOO plus any high-order part of the
2170 CONST_INT into a register. Our address is (plus reg low-part-const).
2171 This is done to reduce the number of GOT entries. */
2173 && GET_CODE (x
) == CONST
2174 && GET_CODE (XEXP (x
, 0)) == PLUS
2175 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2177 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
2178 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
2182 /* If we have a (plus reg const), emit the load as in (2), then add
2183 the two registers, and finally generate (plus reg low-part-const) as
2186 && GET_CODE (x
) == PLUS
2187 && GET_CODE (XEXP (x
, 0)) == REG
2188 && GET_CODE (XEXP (x
, 1)) == CONST
2189 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
2190 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
2192 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
2193 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
2194 XEXP (XEXP (XEXP (x
, 1), 0), 0),
2195 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
2199 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
2200 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
2202 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
2204 switch (tls_symbolic_operand_type (x
))
2206 case TLS_MODEL_GLOBAL_DYNAMIC
:
2209 r0
= gen_rtx_REG (Pmode
, 0);
2210 r16
= gen_rtx_REG (Pmode
, 16);
2211 tga
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
2212 dest
= gen_reg_rtx (Pmode
);
2213 seq
= GEN_INT (alpha_next_sequence_number
++);
2215 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
2216 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
2217 insn
= emit_call_insn (insn
);
2218 CONST_OR_PURE_CALL_P (insn
) = 1;
2219 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2221 insn
= get_insns ();
2224 emit_libcall_block (insn
, dest
, r0
, x
);
2227 case TLS_MODEL_LOCAL_DYNAMIC
:
2230 r0
= gen_rtx_REG (Pmode
, 0);
2231 r16
= gen_rtx_REG (Pmode
, 16);
2232 tga
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
2233 scratch
= gen_reg_rtx (Pmode
);
2234 seq
= GEN_INT (alpha_next_sequence_number
++);
2236 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
2237 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
2238 insn
= emit_call_insn (insn
);
2239 CONST_OR_PURE_CALL_P (insn
) = 1;
2240 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2242 insn
= get_insns ();
2245 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2246 UNSPEC_TLSLDM_CALL
);
2247 emit_libcall_block (insn
, scratch
, r0
, eqv
);
2249 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
2250 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2252 if (alpha_tls_size
== 64)
2254 dest
= gen_reg_rtx (Pmode
);
2255 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
2256 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
2259 if (alpha_tls_size
== 32)
2261 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2262 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
2263 scratch
= gen_reg_rtx (Pmode
);
2264 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
2266 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
2268 case TLS_MODEL_INITIAL_EXEC
:
2269 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2270 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2271 tp
= gen_reg_rtx (Pmode
);
2272 scratch
= gen_reg_rtx (Pmode
);
2273 dest
= gen_reg_rtx (Pmode
);
2275 emit_insn (gen_load_tp (tp
));
2276 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
2277 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
2280 case TLS_MODEL_LOCAL_EXEC
:
2281 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2282 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2283 tp
= gen_reg_rtx (Pmode
);
2285 emit_insn (gen_load_tp (tp
));
2286 if (alpha_tls_size
== 32)
2288 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2289 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
2290 tp
= gen_reg_rtx (Pmode
);
2291 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
2293 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
2296 if (local_symbolic_operand (x
, Pmode
))
2298 if (small_symbolic_operand (x
, Pmode
))
2302 if (!no_new_pseudos
)
2303 scratch
= gen_reg_rtx (Pmode
);
2304 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
2305 gen_rtx_HIGH (Pmode
, x
)));
2306 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
2315 HOST_WIDE_INT low
, high
;
2317 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
2319 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2323 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
2324 (no_new_pseudos
? scratch
: NULL_RTX
),
2325 1, OPTAB_LIB_WIDEN
);
2327 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
2328 (no_new_pseudos
? scratch
: NULL_RTX
),
2329 1, OPTAB_LIB_WIDEN
);
2331 return plus_constant (x
, low
);
2335 /* We do not allow indirect calls to be optimized into sibling calls, nor
2336 can we allow a call to a function with a different GP to be optimized
2340 alpha_function_ok_for_sibcall (decl
, exp
)
2342 tree exp ATTRIBUTE_UNUSED
;
2344 /* Can't do indirect tail calls, since we don't know if the target
2345 uses the same GP. */
2349 /* Otherwise, we can make a tail call if the target function shares
2351 return decl_has_samegp (decl
);
2354 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
2355 small symbolic operand until after reload. At which point we need
2356 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
2357 so that sched2 has the proper dependency information. */
2360 some_small_symbolic_operand (x
, mode
)
2362 enum machine_mode mode ATTRIBUTE_UNUSED
;
2364 return for_each_rtx (&x
, some_small_symbolic_operand_1
, NULL
);
2368 some_small_symbolic_operand_1 (px
, data
)
2370 void *data ATTRIBUTE_UNUSED
;
2374 /* Don't re-split. */
2375 if (GET_CODE (x
) == LO_SUM
)
2378 return small_symbolic_operand (x
, Pmode
) != 0;
2382 split_small_symbolic_operand (x
)
2386 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
2391 split_small_symbolic_operand_1 (px
, data
)
2393 void *data ATTRIBUTE_UNUSED
;
2397 /* Don't re-split. */
2398 if (GET_CODE (x
) == LO_SUM
)
2401 if (small_symbolic_operand (x
, Pmode
))
2403 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
2411 /* Try a machine-dependent way of reloading an illegitimate address
2412 operand. If we find one, push the reload and return the new rtx. */
2415 alpha_legitimize_reload_address (x
, mode
, opnum
, type
, ind_levels
)
2417 enum machine_mode mode ATTRIBUTE_UNUSED
;
2420 int ind_levels ATTRIBUTE_UNUSED
;
2422 /* We must recognize output that we have already generated ourselves. */
2423 if (GET_CODE (x
) == PLUS
2424 && GET_CODE (XEXP (x
, 0)) == PLUS
2425 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2426 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2427 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2429 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2430 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2435 /* We wish to handle large displacements off a base register by
2436 splitting the addend across an ldah and the mem insn. This
2437 cuts number of extra insns needed from 3 to 1. */
2438 if (GET_CODE (x
) == PLUS
2439 && GET_CODE (XEXP (x
, 0)) == REG
2440 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2441 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
2442 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2444 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2445 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
2447 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2449 /* Check for 32-bit overflow. */
2450 if (high
+ low
!= val
)
2453 /* Reload the high part into a base reg; leave the low part
2454 in the mem directly. */
2455 x
= gen_rtx_PLUS (GET_MODE (x
),
2456 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
2460 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2461 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2469 /* REF is an alignable memory location. Place an aligned SImode
2470 reference into *PALIGNED_MEM and the number of bits to shift into
2471 *PBITNUM. SCRATCH is a free register for use in reloading out
2472 of range stack slots. */
2475 get_aligned_mem (ref
, paligned_mem
, pbitnum
)
2477 rtx
*paligned_mem
, *pbitnum
;
2480 HOST_WIDE_INT offset
= 0;
2482 if (GET_CODE (ref
) != MEM
)
2485 if (reload_in_progress
2486 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2488 base
= find_replacement (&XEXP (ref
, 0));
2490 if (! memory_address_p (GET_MODE (ref
), base
))
2495 base
= XEXP (ref
, 0);
2498 if (GET_CODE (base
) == PLUS
)
2499 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2502 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
2504 if (WORDS_BIG_ENDIAN
)
2505 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
2506 + (offset
& 3) * 8));
2508 *pbitnum
= GEN_INT ((offset
& 3) * 8);
2511 /* Similar, but just get the address. Handle the two reload cases.
2512 Add EXTRA_OFFSET to the address we return. */
2515 get_unaligned_address (ref
, extra_offset
)
2520 HOST_WIDE_INT offset
= 0;
2522 if (GET_CODE (ref
) != MEM
)
2525 if (reload_in_progress
2526 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2528 base
= find_replacement (&XEXP (ref
, 0));
2530 if (! memory_address_p (GET_MODE (ref
), base
))
2535 base
= XEXP (ref
, 0);
2538 if (GET_CODE (base
) == PLUS
)
2539 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2541 return plus_constant (base
, offset
+ extra_offset
);
2544 /* On the Alpha, all (non-symbolic) constants except zero go into
2545 a floating-point register via memory. Note that we cannot
2546 return anything that is not a subset of CLASS, and that some
2547 symbolic constants cannot be dropped to memory. */
2550 alpha_preferred_reload_class(x
, class)
2552 enum reg_class
class;
2554 /* Zero is present in any register class. */
2555 if (x
== CONST0_RTX (GET_MODE (x
)))
2558 /* These sorts of constants we can easily drop to memory. */
2559 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2561 if (class == FLOAT_REGS
)
2563 if (class == ALL_REGS
)
2564 return GENERAL_REGS
;
2568 /* All other kinds of constants should not (and in the case of HIGH
2569 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2570 secondary reload. */
2572 return (class == ALL_REGS
? GENERAL_REGS
: class);
2577 /* Loading and storing HImode or QImode values to and from memory
2578 usually requires a scratch register. The exceptions are loading
2579 QImode and HImode from an aligned address to a general register
2580 unless byte instructions are permitted.
2582 We also cannot load an unaligned address or a paradoxical SUBREG
2583 into an FP register.
2585 We also cannot do integral arithmetic into FP regs, as might result
2586 from register elimination into a DImode fp register. */
2589 secondary_reload_class (class, mode
, x
, in
)
2590 enum reg_class
class;
2591 enum machine_mode mode
;
2595 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
2597 if (GET_CODE (x
) == MEM
2598 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
2599 || (GET_CODE (x
) == SUBREG
2600 && (GET_CODE (SUBREG_REG (x
)) == MEM
2601 || (GET_CODE (SUBREG_REG (x
)) == REG
2602 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
2604 if (!in
|| !aligned_memory_operand(x
, mode
))
2605 return GENERAL_REGS
;
2609 if (class == FLOAT_REGS
)
2611 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
2612 return GENERAL_REGS
;
2614 if (GET_CODE (x
) == SUBREG
2615 && (GET_MODE_SIZE (GET_MODE (x
))
2616 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2617 return GENERAL_REGS
;
2619 if (in
&& INTEGRAL_MODE_P (mode
)
2620 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
2621 return GENERAL_REGS
;
2627 /* Subfunction of the following function. Update the flags of any MEM
2628 found in part of X. */
2631 alpha_set_memflags_1 (x
, in_struct_p
, volatile_p
, unchanging_p
)
2633 int in_struct_p
, volatile_p
, unchanging_p
;
2637 switch (GET_CODE (x
))
2643 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2644 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
2649 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
2654 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
2656 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
2661 MEM_IN_STRUCT_P (x
) = in_struct_p
;
2662 MEM_VOLATILE_P (x
) = volatile_p
;
2663 RTX_UNCHANGING_P (x
) = unchanging_p
;
2664 /* Sadly, we cannot use alias sets because the extra aliasing
2665 produced by the AND interferes. Given that two-byte quantities
2666 are the only thing we would be able to differentiate anyway,
2667 there does not seem to be any point in convoluting the early
2668 out of the alias check. */
2676 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2677 generated to perform a memory operation, look for any MEMs in either
2678 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2679 volatile flags from REF into each of the MEMs found. If REF is not
2680 a MEM, don't do anything. */
2683 alpha_set_memflags (insn
, ref
)
2687 int in_struct_p
, volatile_p
, unchanging_p
;
2689 if (GET_CODE (ref
) != MEM
)
2692 in_struct_p
= MEM_IN_STRUCT_P (ref
);
2693 volatile_p
= MEM_VOLATILE_P (ref
);
2694 unchanging_p
= RTX_UNCHANGING_P (ref
);
2696 /* This is only called from alpha.md, after having had something
2697 generated from one of the insn patterns. So if everything is
2698 zero, the pattern is already up-to-date. */
2699 if (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
)
2702 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
2705 /* Try to output insns to set TARGET equal to the constant C if it can be
2706 done in less than N insns. Do all computations in MODE. Returns the place
2707 where the output has been placed if it can be done and the insns have been
2708 emitted. If it would take more than N insns, zero is returned and no
2709 insns and emitted. */
2712 alpha_emit_set_const (target
, mode
, c
, n
)
2714 enum machine_mode mode
;
2719 rtx orig_target
= target
;
2722 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2723 can't load this constant in one insn, do this in DImode. */
2724 if (no_new_pseudos
&& mode
== SImode
2725 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
2726 && (result
= alpha_emit_set_const_1 (target
, mode
, c
, 1)) == 0)
2728 target
= gen_lowpart (DImode
, target
);
2732 /* Try 1 insn, then 2, then up to N. */
2733 for (i
= 1; i
<= n
; i
++)
2735 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
);
2738 rtx insn
= get_last_insn ();
2739 rtx set
= single_set (insn
);
2740 if (! CONSTANT_P (SET_SRC (set
)))
2741 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
2746 /* Allow for the case where we changed the mode of TARGET. */
2747 if (result
== target
)
2748 result
= orig_target
;
2753 /* Internal routine for the above to check for N or below insns. */
2756 alpha_emit_set_const_1 (target
, mode
, c
, n
)
2758 enum machine_mode mode
;
2764 /* Use a pseudo if highly optimizing and still generating RTL. */
2766 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
2769 /* If this is a sign-extended 32-bit constant, we can do this in at most
2770 three insns, so do it if we have enough insns left. We always have
2771 a sign-extended 32-bit constant when compiling on a narrow machine. */
2773 if (HOST_BITS_PER_WIDE_INT
!= 64
2774 || c
>> 31 == -1 || c
>> 31 == 0)
2776 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
2777 HOST_WIDE_INT tmp1
= c
- low
;
2778 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
2779 HOST_WIDE_INT extra
= 0;
2781 /* If HIGH will be interpreted as negative but the constant is
2782 positive, we must adjust it to do two ldha insns. */
2784 if ((high
& 0x8000) != 0 && c
>= 0)
2788 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
2791 if (c
== low
|| (low
== 0 && extra
== 0))
2793 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2794 but that meant that we can't handle INT_MIN on 32-bit machines
2795 (like NT/Alpha), because we recurse indefinitely through
2796 emit_move_insn to gen_movdi. So instead, since we know exactly
2797 what we want, create it explicitly. */
2800 target
= gen_reg_rtx (mode
);
2801 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
2804 else if (n
>= 2 + (extra
!= 0))
2806 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16), subtarget
, mode
);
2808 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2809 This means that if we go through expand_binop, we'll try to
2810 generate extensions, etc, which will require new pseudos, which
2811 will fail during some split phases. The SImode add patterns
2812 still exist, but are not named. So build the insns by hand. */
2817 subtarget
= gen_reg_rtx (mode
);
2818 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
2819 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
2825 target
= gen_reg_rtx (mode
);
2826 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
2827 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
2833 /* If we couldn't do it that way, try some other methods. But if we have
2834 no instructions left, don't bother. Likewise, if this is SImode and
2835 we can't make pseudos, we can't do anything since the expand_binop
2836 and expand_unop calls will widen and try to make pseudos. */
2838 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
2841 /* Next, see if we can load a related constant and then shift and possibly
2842 negate it to get the constant we want. Try this once each increasing
2843 numbers of insns. */
2845 for (i
= 1; i
< n
; i
++)
2847 /* First, see if minus some low bits, we've an easy load of
2850 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
2852 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
2853 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
2854 target
, 0, OPTAB_WIDEN
);
2856 /* Next try complementing. */
2857 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
2858 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
2860 /* Next try to form a constant and do a left shift. We can do this
2861 if some low-order bits are zero; the exact_log2 call below tells
2862 us that information. The bits we are shifting out could be any
2863 value, but here we'll just try the 0- and sign-extended forms of
2864 the constant. To try to increase the chance of having the same
2865 constant in more than one insn, start at the highest number of
2866 bits to shift, but try all possibilities in case a ZAPNOT will
2869 if ((bits
= exact_log2 (c
& - c
)) > 0)
2870 for (; bits
> 0; bits
--)
2871 if ((temp
= (alpha_emit_set_const
2872 (subtarget
, mode
, c
>> bits
, i
))) != 0
2873 || ((temp
= (alpha_emit_set_const
2875 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
2877 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
2878 target
, 0, OPTAB_WIDEN
);
2880 /* Now try high-order zero bits. Here we try the shifted-in bits as
2881 all zero and all ones. Be careful to avoid shifting outside the
2882 mode and to avoid shifting outside the host wide int size. */
2883 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2884 confuse the recursive call and set all of the high 32 bits. */
2886 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2887 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
2888 for (; bits
> 0; bits
--)
2889 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2891 || ((temp
= (alpha_emit_set_const
2893 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2896 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
2897 target
, 1, OPTAB_WIDEN
);
2899 /* Now try high-order 1 bits. We get that with a sign-extension.
2900 But one bit isn't enough here. Be careful to avoid shifting outside
2901 the mode and to avoid shifting outside the host wide int size. */
2903 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2904 - floor_log2 (~ c
) - 2)) > 0)
2905 for (; bits
> 0; bits
--)
2906 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2908 || ((temp
= (alpha_emit_set_const
2910 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2913 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
2914 target
, 0, OPTAB_WIDEN
);
2917 #if HOST_BITS_PER_WIDE_INT == 64
2918 /* Finally, see if can load a value into the target that is the same as the
2919 constant except that all bytes that are 0 are changed to be 0xff. If we
2920 can, then we can do a ZAPNOT to obtain the desired constant. */
2923 for (i
= 0; i
< 64; i
+= 8)
2924 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
2925 new |= (HOST_WIDE_INT
) 0xff << i
;
2927 /* We are only called for SImode and DImode. If this is SImode, ensure that
2928 we are sign extended to a full word. */
2931 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2933 if (new != c
&& new != -1
2934 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
2935 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
2936 target
, 0, OPTAB_WIDEN
);
2942 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2943 fall back to a straight forward decomposition. We do this to avoid
2944 exponential run times encountered when looking for longer sequences
2945 with alpha_emit_set_const. */
2948 alpha_emit_set_long_const (target
, c1
, c2
)
2950 HOST_WIDE_INT c1
, c2
;
2952 HOST_WIDE_INT d1
, d2
, d3
, d4
;
2954 /* Decompose the entire word */
2955 #if HOST_BITS_PER_WIDE_INT >= 64
2956 if (c2
!= -(c1
< 0))
2958 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2960 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2961 c1
= (c1
- d2
) >> 32;
2962 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2964 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2968 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2970 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2974 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
2976 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2981 /* Construct the high word */
2984 emit_move_insn (target
, GEN_INT (d4
));
2986 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2989 emit_move_insn (target
, GEN_INT (d3
));
2991 /* Shift it into place */
2992 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2994 /* Add in the low bits. */
2996 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2998 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
3003 /* Expand a move instruction; return true if all work is done.
3004 We don't handle non-bwx subword loads here. */
3007 alpha_expand_mov (mode
, operands
)
3008 enum machine_mode mode
;
3011 /* If the output is not a register, the input must be. */
3012 if (GET_CODE (operands
[0]) == MEM
3013 && ! reg_or_0_operand (operands
[1], mode
))
3014 operands
[1] = force_reg (mode
, operands
[1]);
3016 /* Allow legitimize_address to perform some simplifications. */
3017 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
3021 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
3022 compiled at the end of compilation. In the meantime, someone can
3023 re-encode-section-info on some symbol changing it e.g. from global
3024 to local-not-small. If this happens, we'd have emitted a plain
3025 load rather than a high+losum load and not recognize the insn.
3027 So if rtl inlining is in effect, we delay the global/not-global
3028 decision until rest_of_compilation by wrapping it in an
3030 if (TARGET_EXPLICIT_RELOCS
&& flag_inline_functions
3031 && rtx_equal_function_value_matters
3032 && global_symbolic_operand (operands
[1], mode
))
3034 emit_insn (gen_movdi_er_maybe_g (operands
[0], operands
[1]));
3038 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
3041 if (tmp
== operands
[0])
3048 /* Early out for non-constants and valid constants. */
3049 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
3052 /* Split large integers. */
3053 if (GET_CODE (operands
[1]) == CONST_INT
3054 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
3056 HOST_WIDE_INT i0
, i1
;
3057 rtx temp
= NULL_RTX
;
3059 if (GET_CODE (operands
[1]) == CONST_INT
)
3061 i0
= INTVAL (operands
[1]);
3064 else if (HOST_BITS_PER_WIDE_INT
>= 64)
3066 i0
= CONST_DOUBLE_LOW (operands
[1]);
3071 i0
= CONST_DOUBLE_LOW (operands
[1]);
3072 i1
= CONST_DOUBLE_HIGH (operands
[1]);
3075 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
3076 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
3078 if (!temp
&& TARGET_BUILD_CONSTANTS
)
3079 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
3083 if (rtx_equal_p (operands
[0], temp
))
3090 /* Otherwise we've nothing left but to drop the thing to memory. */
3091 operands
[1] = force_const_mem (DImode
, operands
[1]);
3092 if (reload_in_progress
)
3094 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
3095 operands
[1] = copy_rtx (operands
[1]);
3096 XEXP (operands
[1], 0) = operands
[0];
3099 operands
[1] = validize_mem (operands
[1]);
3103 /* Expand a non-bwx QImode or HImode move instruction;
3104 return true if all work is done. */
3107 alpha_expand_mov_nobwx (mode
, operands
)
3108 enum machine_mode mode
;
3111 /* If the output is not a register, the input must be. */
3112 if (GET_CODE (operands
[0]) == MEM
)
3113 operands
[1] = force_reg (mode
, operands
[1]);
3115 /* Handle four memory cases, unaligned and aligned for either the input
3116 or the output. The only case where we can be called during reload is
3117 for aligned loads; all other cases require temporaries. */
3119 if (GET_CODE (operands
[1]) == MEM
3120 || (GET_CODE (operands
[1]) == SUBREG
3121 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
3122 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
3123 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
3124 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
3125 && GET_CODE (SUBREG_REG (operands
[1])) == REG
3126 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
3128 if (aligned_memory_operand (operands
[1], mode
))
3130 if (reload_in_progress
)
3132 emit_insn ((mode
== QImode
3133 ? gen_reload_inqi_help
3134 : gen_reload_inhi_help
)
3135 (operands
[0], operands
[1],
3136 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
3140 rtx aligned_mem
, bitnum
;
3141 rtx scratch
= gen_reg_rtx (SImode
);
3143 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
3145 emit_insn ((mode
== QImode
3146 ? gen_aligned_loadqi
3147 : gen_aligned_loadhi
)
3148 (operands
[0], aligned_mem
, bitnum
, scratch
));
3153 /* Don't pass these as parameters since that makes the generated
3154 code depend on parameter evaluation order which will cause
3155 bootstrap failures. */
3157 rtx temp1
= gen_reg_rtx (DImode
);
3158 rtx temp2
= gen_reg_rtx (DImode
);
3159 rtx seq
= ((mode
== QImode
3160 ? gen_unaligned_loadqi
3161 : gen_unaligned_loadhi
)
3162 (operands
[0], get_unaligned_address (operands
[1], 0),
3165 alpha_set_memflags (seq
, operands
[1]);
3171 if (GET_CODE (operands
[0]) == MEM
3172 || (GET_CODE (operands
[0]) == SUBREG
3173 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
3174 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
3175 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
3176 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
3177 && GET_CODE (SUBREG_REG (operands
[0])) == REG
3178 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
3180 if (aligned_memory_operand (operands
[0], mode
))
3182 rtx aligned_mem
, bitnum
;
3183 rtx temp1
= gen_reg_rtx (SImode
);
3184 rtx temp2
= gen_reg_rtx (SImode
);
3186 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
3188 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
3193 rtx temp1
= gen_reg_rtx (DImode
);
3194 rtx temp2
= gen_reg_rtx (DImode
);
3195 rtx temp3
= gen_reg_rtx (DImode
);
3196 rtx seq
= ((mode
== QImode
3197 ? gen_unaligned_storeqi
3198 : gen_unaligned_storehi
)
3199 (get_unaligned_address (operands
[0], 0),
3200 operands
[1], temp1
, temp2
, temp3
));
3202 alpha_set_memflags (seq
, operands
[0]);
3211 /* Generate an unsigned DImode to FP conversion. This is the same code
3212 optabs would emit if we didn't have TFmode patterns.
3214 For SFmode, this is the only construction I've found that can pass
3215 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
3216 intermediates will work, because you'll get intermediate rounding
3217 that ruins the end result. Some of this could be fixed by turning
3218 on round-to-positive-infinity, but that requires diddling the fpsr,
3219 which kills performance. I tried turning this around and converting
3220 to a negative number, so that I could turn on /m, but either I did
3221 it wrong or there's something else cause I wound up with the exact
3222 same single-bit error. There is a branch-less form of this same code:
3233 fcmoveq $f10,$f11,$f0
3235 I'm not using it because it's the same number of instructions as
3236 this branch-full form, and it has more serialized long latency
3237 instructions on the critical path.
3239 For DFmode, we can avoid rounding errors by breaking up the word
3240 into two pieces, converting them separately, and adding them back:
3242 LC0: .long 0,0x5f800000
3247 cpyse $f11,$f31,$f10
3248 cpyse $f31,$f11,$f11
3256 This doesn't seem to be a clear-cut win over the optabs form.
3257 It probably all depends on the distribution of numbers being
3258 converted -- in the optabs form, all but high-bit-set has a
3259 much lower minimum execution time. */
3262 alpha_emit_floatuns (operands
)
3265 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
3266 enum machine_mode mode
;
3269 in
= force_reg (DImode
, operands
[1]);
3270 mode
= GET_MODE (out
);
3271 neglab
= gen_label_rtx ();
3272 donelab
= gen_label_rtx ();
3273 i0
= gen_reg_rtx (DImode
);
3274 i1
= gen_reg_rtx (DImode
);
3275 f0
= gen_reg_rtx (mode
);
3277 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
3279 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
3280 emit_jump_insn (gen_jump (donelab
));
3283 emit_label (neglab
);
3285 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
3286 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
3287 emit_insn (gen_iordi3 (i0
, i0
, i1
));
3288 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
3289 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
3291 emit_label (donelab
);
3294 /* Generate the comparison for a conditional branch. */
3297 alpha_emit_conditional_branch (code
)
3300 enum rtx_code cmp_code
, branch_code
;
3301 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
3302 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3305 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
3307 if (! TARGET_HAS_XFLOATING_LIBS
)
3310 /* X_floating library comparison functions return
3314 Convert the compare against the raw return value. */
3336 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3338 alpha_compare
.fp_p
= 0;
3341 /* The general case: fold the comparison code to the types of compares
3342 that we have, choosing the branch as necessary. */
3345 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3347 /* We have these compares: */
3348 cmp_code
= code
, branch_code
= NE
;
3353 /* These must be reversed. */
3354 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
3357 case GE
: case GT
: case GEU
: case GTU
:
3358 /* For FP, we swap them, for INT, we reverse them. */
3359 if (alpha_compare
.fp_p
)
3361 cmp_code
= swap_condition (code
);
3363 tem
= op0
, op0
= op1
, op1
= tem
;
3367 cmp_code
= reverse_condition (code
);
3376 if (alpha_compare
.fp_p
)
3379 if (flag_unsafe_math_optimizations
)
3381 /* When we are not as concerned about non-finite values, and we
3382 are comparing against zero, we can branch directly. */
3383 if (op1
== CONST0_RTX (DFmode
))
3384 cmp_code
= NIL
, branch_code
= code
;
3385 else if (op0
== CONST0_RTX (DFmode
))
3387 /* Undo the swap we probably did just above. */
3388 tem
= op0
, op0
= op1
, op1
= tem
;
3389 branch_code
= swap_condition (cmp_code
);
3395 /* ??? We mark the branch mode to be CCmode to prevent the
3396 compare and branch from being combined, since the compare
3397 insn follows IEEE rules that the branch does not. */
3398 branch_mode
= CCmode
;
3405 /* The following optimizations are only for signed compares. */
3406 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
3408 /* Whee. Compare and branch against 0 directly. */
3409 if (op1
== const0_rtx
)
3410 cmp_code
= NIL
, branch_code
= code
;
3412 /* We want to use cmpcc/bcc when we can, since there is a zero delay
3413 bypass between logicals and br/cmov on EV5. But we don't want to
3414 force valid immediate constants into registers needlessly. */
3415 else if (GET_CODE (op1
) == CONST_INT
)
3417 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
3419 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
3420 && (CONST_OK_FOR_LETTER_P (n
, 'K')
3421 || CONST_OK_FOR_LETTER_P (n
, 'L')))
3423 cmp_code
= PLUS
, branch_code
= code
;
3429 if (!reg_or_0_operand (op0
, DImode
))
3430 op0
= force_reg (DImode
, op0
);
3431 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
3432 op1
= force_reg (DImode
, op1
);
3435 /* Emit an initial compare instruction, if necessary. */
3437 if (cmp_code
!= NIL
)
3439 tem
= gen_reg_rtx (cmp_mode
);
3440 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
3443 /* Zero the operands. */
3444 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3446 /* Return the branch comparison. */
3447 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
3450 /* Certain simplifications can be done to make invalid setcc operations
3451 valid. Return the final comparison, or NULL if we can't work. */
3454 alpha_emit_setcc (code
)
3457 enum rtx_code cmp_code
;
3458 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3459 int fp_p
= alpha_compare
.fp_p
;
3462 /* Zero the operands. */
3463 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3465 if (fp_p
&& GET_MODE (op0
) == TFmode
)
3467 if (! TARGET_HAS_XFLOATING_LIBS
)
3470 /* X_floating library comparison functions return
3474 Convert the compare against the raw return value. */
3476 if (code
== UNORDERED
|| code
== ORDERED
)
3481 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3485 if (code
== UNORDERED
)
3487 else if (code
== ORDERED
)
3493 if (fp_p
&& !TARGET_FIX
)
3496 /* The general case: fold the comparison code to the types of compares
3497 that we have, choosing the branch as necessary. */
3502 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3504 /* We have these compares. */
3506 cmp_code
= code
, code
= NE
;
3510 if (!fp_p
&& op1
== const0_rtx
)
3515 cmp_code
= reverse_condition (code
);
3519 case GE
: case GT
: case GEU
: case GTU
:
3520 /* These normally need swapping, but for integer zero we have
3521 special patterns that recognize swapped operands. */
3522 if (!fp_p
&& op1
== const0_rtx
)
3524 code
= swap_condition (code
);
3526 cmp_code
= code
, code
= NE
;
3527 tmp
= op0
, op0
= op1
, op1
= tmp
;
3536 if (!register_operand (op0
, DImode
))
3537 op0
= force_reg (DImode
, op0
);
3538 if (!reg_or_8bit_operand (op1
, DImode
))
3539 op1
= force_reg (DImode
, op1
);
3542 /* Emit an initial compare instruction, if necessary. */
3543 if (cmp_code
!= NIL
)
3545 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
3547 tmp
= gen_reg_rtx (mode
);
3548 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
3549 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
3551 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
3555 /* Return the setcc comparison. */
3556 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
3560 /* Rewrite a comparison against zero CMP of the form
3561 (CODE (cc0) (const_int 0)) so it can be written validly in
3562 a conditional move (if_then_else CMP ...).
3563 If both of the operands that set cc0 are nonzero we must emit
3564 an insn to perform the compare (it can't be done within
3565 the conditional move). */
3567 alpha_emit_conditional_move (cmp
, mode
)
3569 enum machine_mode mode
;
3571 enum rtx_code code
= GET_CODE (cmp
);
3572 enum rtx_code cmov_code
= NE
;
3573 rtx op0
= alpha_compare
.op0
;
3574 rtx op1
= alpha_compare
.op1
;
3575 int fp_p
= alpha_compare
.fp_p
;
3576 enum machine_mode cmp_mode
3577 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
3578 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
3579 enum machine_mode cmov_mode
= VOIDmode
;
3580 int local_fast_math
= flag_unsafe_math_optimizations
;
3583 /* Zero the operands. */
3584 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3586 if (fp_p
!= FLOAT_MODE_P (mode
))
3588 enum rtx_code cmp_code
;
3593 /* If we have fp<->int register move instructions, do a cmov by
3594 performing the comparison in fp registers, and move the
3595 zero/nonzero value to integer registers, where we can then
3596 use a normal cmov, or vice-versa. */
3600 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3601 /* We have these compares. */
3602 cmp_code
= code
, code
= NE
;
3606 /* This must be reversed. */
3607 cmp_code
= EQ
, code
= EQ
;
3610 case GE
: case GT
: case GEU
: case GTU
:
3611 /* These normally need swapping, but for integer zero we have
3612 special patterns that recognize swapped operands. */
3613 if (!fp_p
&& op1
== const0_rtx
)
3614 cmp_code
= code
, code
= NE
;
3617 cmp_code
= swap_condition (code
);
3619 tem
= op0
, op0
= op1
, op1
= tem
;
3627 tem
= gen_reg_rtx (cmp_op_mode
);
3628 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
3629 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
3632 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
3633 op0
= gen_lowpart (cmp_op_mode
, tem
);
3634 op1
= CONST0_RTX (cmp_op_mode
);
3636 local_fast_math
= 1;
3639 /* We may be able to use a conditional move directly.
3640 This avoids emitting spurious compares. */
3641 if (signed_comparison_operator (cmp
, VOIDmode
)
3642 && (!fp_p
|| local_fast_math
)
3643 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
3644 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3646 /* We can't put the comparison inside the conditional move;
3647 emit a compare instruction and put that inside the
3648 conditional move. Make sure we emit only comparisons we have;
3649 swap or reverse as necessary. */
3656 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3657 /* We have these compares: */
3661 /* This must be reversed. */
3662 code
= reverse_condition (code
);
3666 case GE
: case GT
: case GEU
: case GTU
:
3667 /* These must be swapped. */
3668 if (op1
!= CONST0_RTX (cmp_mode
))
3670 code
= swap_condition (code
);
3671 tem
= op0
, op0
= op1
, op1
= tem
;
3681 if (!reg_or_0_operand (op0
, DImode
))
3682 op0
= force_reg (DImode
, op0
);
3683 if (!reg_or_8bit_operand (op1
, DImode
))
3684 op1
= force_reg (DImode
, op1
);
3687 /* ??? We mark the branch mode to be CCmode to prevent the compare
3688 and cmov from being combined, since the compare insn follows IEEE
3689 rules that the cmov does not. */
3690 if (fp_p
&& !local_fast_math
)
3693 tem
= gen_reg_rtx (cmp_op_mode
);
3694 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
3695 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
3698 /* Simplify a conditional move of two constants into a setcc with
3699 arithmetic. This is done with a splitter since combine would
3700 just undo the work if done during code generation. It also catches
3701 cases we wouldn't have before cse. */
3704 alpha_split_conditional_move (code
, dest
, cond
, t_rtx
, f_rtx
)
3706 rtx dest
, cond
, t_rtx
, f_rtx
;
3708 HOST_WIDE_INT t
, f
, diff
;
3709 enum machine_mode mode
;
3710 rtx target
, subtarget
, tmp
;
3712 mode
= GET_MODE (dest
);
3717 if (((code
== NE
|| code
== EQ
) && diff
< 0)
3718 || (code
== GE
|| code
== GT
))
3720 code
= reverse_condition (code
);
3721 diff
= t
, t
= f
, f
= diff
;
3725 subtarget
= target
= dest
;
3728 target
= gen_lowpart (DImode
, dest
);
3729 if (! no_new_pseudos
)
3730 subtarget
= gen_reg_rtx (DImode
);
3734 /* Below, we must be careful to use copy_rtx on target and subtarget
3735 in intermediate insns, as they may be a subreg rtx, which may not
3738 if (f
== 0 && exact_log2 (diff
) > 0
3739 /* On EV6, we've got enough shifters to make non-arithmatic shifts
3740 viable over a longer latency cmove. On EV5, the E0 slot is a
3741 scarce resource, and on EV4 shift has the same latency as a cmove. */
3742 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
3744 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3745 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3747 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
3748 GEN_INT (exact_log2 (t
)));
3749 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3751 else if (f
== 0 && t
== -1)
3753 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3754 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3756 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
3758 else if (diff
== 1 || diff
== 4 || diff
== 8)
3762 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3763 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3766 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
3769 add_op
= GEN_INT (f
);
3770 if (sext_add_operand (add_op
, mode
))
3772 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
3774 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
3775 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3787 /* Look up the function X_floating library function name for the
3791 alpha_lookup_xfloating_lib_func (code
)
3796 const enum rtx_code code
;
3797 const char *const func
;
3800 static const struct xfloating_op vms_xfloating_ops
[] =
3802 { PLUS
, "OTS$ADD_X" },
3803 { MINUS
, "OTS$SUB_X" },
3804 { MULT
, "OTS$MUL_X" },
3805 { DIV
, "OTS$DIV_X" },
3806 { EQ
, "OTS$EQL_X" },
3807 { NE
, "OTS$NEQ_X" },
3808 { LT
, "OTS$LSS_X" },
3809 { LE
, "OTS$LEQ_X" },
3810 { GT
, "OTS$GTR_X" },
3811 { GE
, "OTS$GEQ_X" },
3812 { FIX
, "OTS$CVTXQ" },
3813 { FLOAT
, "OTS$CVTQX" },
3814 { UNSIGNED_FLOAT
, "OTS$CVTQUX" },
3815 { FLOAT_EXTEND
, "OTS$CVT_FLOAT_T_X" },
3816 { FLOAT_TRUNCATE
, "OTS$CVT_FLOAT_X_T" },
3819 static const struct xfloating_op osf_xfloating_ops
[] =
3821 { PLUS
, "_OtsAddX" },
3822 { MINUS
, "_OtsSubX" },
3823 { MULT
, "_OtsMulX" },
3824 { DIV
, "_OtsDivX" },
3831 { FIX
, "_OtsCvtXQ" },
3832 { FLOAT
, "_OtsCvtQX" },
3833 { UNSIGNED_FLOAT
, "_OtsCvtQUX" },
3834 { FLOAT_EXTEND
, "_OtsConvertFloatTX" },
3835 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT" },
3838 const struct xfloating_op
*ops
;
3839 const long n
= ARRAY_SIZE (osf_xfloating_ops
);
3842 /* How irritating. Nothing to key off for the table. Hardcode
3843 knowledge of the G_floating routines. */
3844 if (TARGET_FLOAT_VAX
)
3846 if (TARGET_ABI_OPEN_VMS
)
3848 if (code
== FLOAT_EXTEND
)
3849 return "OTS$CVT_FLOAT_G_X";
3850 if (code
== FLOAT_TRUNCATE
)
3851 return "OTS$CVT_FLOAT_X_G";
3855 if (code
== FLOAT_EXTEND
)
3856 return "_OtsConvertFloatGX";
3857 if (code
== FLOAT_TRUNCATE
)
3858 return "_OtsConvertFloatXG";
3862 if (TARGET_ABI_OPEN_VMS
)
3863 ops
= vms_xfloating_ops
;
3865 ops
= osf_xfloating_ops
;
3867 for (i
= 0; i
< n
; ++i
)
3868 if (ops
[i
].code
== code
)
3874 /* Most X_floating operations take the rounding mode as an argument.
3875 Compute that here. */
3878 alpha_compute_xfloating_mode_arg (code
, round
)
3880 enum alpha_fp_rounding_mode round
;
3886 case ALPHA_FPRM_NORM
:
3889 case ALPHA_FPRM_MINF
:
3892 case ALPHA_FPRM_CHOP
:
3895 case ALPHA_FPRM_DYN
:
3901 /* XXX For reference, round to +inf is mode = 3. */
3904 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3910 /* Emit an X_floating library function call.
3912 Note that these functions do not follow normal calling conventions:
3913 TFmode arguments are passed in two integer registers (as opposed to
3914 indirect); TFmode return values appear in R16+R17.
3916 FUNC is the function name to call.
3917 TARGET is where the output belongs.
3918 OPERANDS are the inputs.
3919 NOPERANDS is the count of inputs.
3920 EQUIV is the expression equivalent for the function.
3924 alpha_emit_xfloating_libcall (func
, target
, operands
, noperands
, equiv
)
3931 rtx usage
= NULL_RTX
, tmp
, reg
;
3936 for (i
= 0; i
< noperands
; ++i
)
3938 switch (GET_MODE (operands
[i
]))
3941 reg
= gen_rtx_REG (TFmode
, regno
);
3946 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3951 if (GET_CODE (operands
[i
]) != CONST_INT
)
3955 reg
= gen_rtx_REG (DImode
, regno
);
3963 emit_move_insn (reg
, operands
[i
]);
3964 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3967 switch (GET_MODE (target
))
3970 reg
= gen_rtx_REG (TFmode
, 16);
3973 reg
= gen_rtx_REG (DFmode
, 32);
3976 reg
= gen_rtx_REG (DImode
, 0);
3982 tmp
= gen_rtx_MEM (QImode
, gen_rtx_SYMBOL_REF (Pmode
, (char *) func
));
3983 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3984 const0_rtx
, const0_rtx
));
3985 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3990 emit_libcall_block (tmp
, target
, reg
, equiv
);
3993 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3996 alpha_emit_xfloating_arith (code
, operands
)
4002 rtx out_operands
[3];
4004 func
= alpha_lookup_xfloating_lib_func (code
);
4005 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
4007 out_operands
[0] = operands
[1];
4008 out_operands
[1] = operands
[2];
4009 out_operands
[2] = GEN_INT (mode
);
4010 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
4011 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
4015 /* Emit an X_floating library function call for a comparison. */
4018 alpha_emit_xfloating_compare (code
, op0
, op1
)
4023 rtx out
, operands
[2];
4025 func
= alpha_lookup_xfloating_lib_func (code
);
4029 out
= gen_reg_rtx (DImode
);
4031 /* ??? Strange mode for equiv because what's actually returned
4032 is -1,0,1, not a proper boolean value. */
4033 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
4034 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
4039 /* Emit an X_floating library function call for a conversion. */
4042 alpha_emit_xfloating_cvt (code
, operands
)
4046 int noperands
= 1, mode
;
4047 rtx out_operands
[2];
4050 func
= alpha_lookup_xfloating_lib_func (code
);
4052 out_operands
[0] = operands
[1];
4057 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
4058 out_operands
[1] = GEN_INT (mode
);
4061 case FLOAT_TRUNCATE
:
4062 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
4063 out_operands
[1] = GEN_INT (mode
);
4070 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
4071 gen_rtx_fmt_e (code
, GET_MODE (operands
[0]),
4075 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
4076 OP[0] into OP[0,1]. Naturally, output operand ordering is
4080 alpha_split_tfmode_pair (operands
)
4083 if (GET_CODE (operands
[1]) == REG
)
4085 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
4086 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
4088 else if (GET_CODE (operands
[1]) == MEM
)
4090 operands
[3] = adjust_address (operands
[1], DImode
, 8);
4091 operands
[2] = adjust_address (operands
[1], DImode
, 0);
4093 else if (operands
[1] == CONST0_RTX (TFmode
))
4094 operands
[2] = operands
[3] = const0_rtx
;
4098 if (GET_CODE (operands
[0]) == REG
)
4100 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
4101 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
4103 else if (GET_CODE (operands
[0]) == MEM
)
4105 operands
[1] = adjust_address (operands
[0], DImode
, 8);
4106 operands
[0] = adjust_address (operands
[0], DImode
, 0);
4112 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
4113 op2 is a register containing the sign bit, operation is the
4114 logical operation to be performed. */
4117 alpha_split_tfmode_frobsign (operands
, operation
)
4119 rtx (*operation
) PARAMS ((rtx
, rtx
, rtx
));
4121 rtx high_bit
= operands
[2];
4125 alpha_split_tfmode_pair (operands
);
4127 /* Detect three flavors of operand overlap. */
4129 if (rtx_equal_p (operands
[0], operands
[2]))
4131 else if (rtx_equal_p (operands
[1], operands
[2]))
4133 if (rtx_equal_p (operands
[0], high_bit
))
4140 emit_move_insn (operands
[0], operands
[2]);
4142 /* ??? If the destination overlaps both source tf and high_bit, then
4143 assume source tf is dead in its entirety and use the other half
4144 for a scratch register. Otherwise "scratch" is just the proper
4145 destination register. */
4146 scratch
= operands
[move
< 2 ? 1 : 3];
4148 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
4152 emit_move_insn (operands
[0], operands
[2]);
4154 emit_move_insn (operands
[1], scratch
);
4158 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
4162 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
4163 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
4164 lda r3,X(r11) lda r3,X+2(r11)
4165 extwl r1,r3,r1 extql r1,r3,r1
4166 extwh r2,r3,r2 extqh r2,r3,r2
4167 or r1.r2.r1 or r1,r2,r1
4170 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
4171 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
4172 lda r3,X(r11) lda r3,X(r11)
4173 extll r1,r3,r1 extll r1,r3,r1
4174 extlh r2,r3,r2 extlh r2,r3,r2
4175 or r1.r2.r1 addl r1,r2,r1
4177 quad: ldq_u r1,X(r11)
4186 alpha_expand_unaligned_load (tgt
, mem
, size
, ofs
, sign
)
4188 HOST_WIDE_INT size
, ofs
;
4191 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
4192 enum machine_mode mode
;
4194 meml
= gen_reg_rtx (DImode
);
4195 memh
= gen_reg_rtx (DImode
);
4196 addr
= gen_reg_rtx (DImode
);
4197 extl
= gen_reg_rtx (DImode
);
4198 exth
= gen_reg_rtx (DImode
);
4200 mema
= XEXP (mem
, 0);
4201 if (GET_CODE (mema
) == LO_SUM
)
4202 mema
= force_reg (Pmode
, mema
);
4204 /* AND addresses cannot be in any alias set, since they may implicitly
4205 alias surrounding code. Ideally we'd have some alias set that
4206 covered all types except those with alignment 8 or higher. */
4208 tmp
= change_address (mem
, DImode
,
4209 gen_rtx_AND (DImode
,
4210 plus_constant (mema
, ofs
),
4212 set_mem_alias_set (tmp
, 0);
4213 emit_move_insn (meml
, tmp
);
4215 tmp
= change_address (mem
, DImode
,
4216 gen_rtx_AND (DImode
,
4217 plus_constant (mema
, ofs
+ size
- 1),
4219 set_mem_alias_set (tmp
, 0);
4220 emit_move_insn (memh
, tmp
);
4222 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
4224 emit_move_insn (addr
, plus_constant (mema
, -1));
4226 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4227 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
4229 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4230 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
4231 addr
, 1, OPTAB_WIDEN
);
4233 else if (sign
&& size
== 2)
4235 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
4237 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
4238 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4240 /* We must use tgt here for the target. Alpha-vms port fails if we use
4241 addr for the target, because addr is marked as a pointer and combine
4242 knows that pointers are always sign-extended 32 bit values. */
4243 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4244 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
4245 addr
, 1, OPTAB_WIDEN
);
4249 if (WORDS_BIG_ENDIAN
)
4251 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
4255 emit_insn (gen_extwh_be (extl
, meml
, addr
));
4260 emit_insn (gen_extlh_be (extl
, meml
, addr
));
4265 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4272 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
4276 emit_move_insn (addr
, plus_constant (mema
, ofs
));
4277 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
4281 emit_insn (gen_extwh_le (exth
, memh
, addr
));
4286 emit_insn (gen_extlh_le (exth
, memh
, addr
));
4291 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4300 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
4301 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
4306 emit_move_insn (tgt
, gen_lowpart(GET_MODE (tgt
), addr
));
4309 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4312 alpha_expand_unaligned_store (dst
, src
, size
, ofs
)
4314 HOST_WIDE_INT size
, ofs
;
4316 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
4318 dstl
= gen_reg_rtx (DImode
);
4319 dsth
= gen_reg_rtx (DImode
);
4320 insl
= gen_reg_rtx (DImode
);
4321 insh
= gen_reg_rtx (DImode
);
4323 dsta
= XEXP (dst
, 0);
4324 if (GET_CODE (dsta
) == LO_SUM
)
4325 dsta
= force_reg (Pmode
, dsta
);
4327 /* AND addresses cannot be in any alias set, since they may implicitly
4328 alias surrounding code. Ideally we'd have some alias set that
4329 covered all types except those with alignment 8 or higher. */
4331 meml
= change_address (dst
, DImode
,
4332 gen_rtx_AND (DImode
,
4333 plus_constant (dsta
, ofs
),
4335 set_mem_alias_set (meml
, 0);
4337 memh
= change_address (dst
, DImode
,
4338 gen_rtx_AND (DImode
,
4339 plus_constant (dsta
, ofs
+ size
- 1),
4341 set_mem_alias_set (memh
, 0);
4343 emit_move_insn (dsth
, memh
);
4344 emit_move_insn (dstl
, meml
);
4345 if (WORDS_BIG_ENDIAN
)
4347 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
4349 if (src
!= const0_rtx
)
4354 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
4357 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
4360 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
4363 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
4364 GEN_INT (size
*8), addr
));
4370 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
4374 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4375 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
4379 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
4383 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
4387 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
4389 if (src
!= const0_rtx
)
4391 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
4392 GEN_INT (size
*8), addr
));
4397 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
4400 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
4403 emit_insn (gen_insql_le (insl
, src
, addr
));
4408 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
4413 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
4417 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4418 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
4422 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
4427 if (src
!= const0_rtx
)
4429 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
4430 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
4433 if (WORDS_BIG_ENDIAN
)
4435 emit_move_insn (meml
, dstl
);
4436 emit_move_insn (memh
, dsth
);
4440 /* Must store high before low for degenerate case of aligned. */
4441 emit_move_insn (memh
, dsth
);
4442 emit_move_insn (meml
, dstl
);
4446 /* The block move code tries to maximize speed by separating loads and
4447 stores at the expense of register pressure: we load all of the data
4448 before we store it back out. There are two secondary effects worth
4449 mentioning, that this speeds copying to/from aligned and unaligned
4450 buffers, and that it makes the code significantly easier to write. */
4452 #define MAX_MOVE_WORDS 8
4454 /* Load an integral number of consecutive unaligned quadwords. */
4457 alpha_expand_unaligned_load_words (out_regs
, smem
, words
, ofs
)
4460 HOST_WIDE_INT words
, ofs
;
4462 rtx
const im8
= GEN_INT (-8);
4463 rtx
const i64
= GEN_INT (64);
4464 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
4465 rtx sreg
, areg
, tmp
, smema
;
4468 smema
= XEXP (smem
, 0);
4469 if (GET_CODE (smema
) == LO_SUM
)
4470 smema
= force_reg (Pmode
, smema
);
4472 /* Generate all the tmp registers we need. */
4473 for (i
= 0; i
< words
; ++i
)
4475 data_regs
[i
] = out_regs
[i
];
4476 ext_tmps
[i
] = gen_reg_rtx (DImode
);
4478 data_regs
[words
] = gen_reg_rtx (DImode
);
4481 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
4483 /* Load up all of the source data. */
4484 for (i
= 0; i
< words
; ++i
)
4486 tmp
= change_address (smem
, DImode
,
4487 gen_rtx_AND (DImode
,
4488 plus_constant (smema
, 8*i
),
4490 set_mem_alias_set (tmp
, 0);
4491 emit_move_insn (data_regs
[i
], tmp
);
4494 tmp
= change_address (smem
, DImode
,
4495 gen_rtx_AND (DImode
,
4496 plus_constant (smema
, 8*words
- 1),
4498 set_mem_alias_set (tmp
, 0);
4499 emit_move_insn (data_regs
[words
], tmp
);
4501 /* Extract the half-word fragments. Unfortunately DEC decided to make
4502 extxh with offset zero a noop instead of zeroing the register, so
4503 we must take care of that edge condition ourselves with cmov. */
4505 sreg
= copy_addr_to_reg (smema
);
4506 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
4508 if (WORDS_BIG_ENDIAN
)
4509 emit_move_insn (sreg
, plus_constant (sreg
, 7));
4510 for (i
= 0; i
< words
; ++i
)
4512 if (WORDS_BIG_ENDIAN
)
4514 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
4515 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
4519 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
4520 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
4522 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
4523 gen_rtx_IF_THEN_ELSE (DImode
,
4524 gen_rtx_EQ (DImode
, areg
,
4526 const0_rtx
, ext_tmps
[i
])));
4529 /* Merge the half-words into whole words. */
4530 for (i
= 0; i
< words
; ++i
)
4532 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4533 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
4537 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4538 may be NULL to store zeros. */
4541 alpha_expand_unaligned_store_words (data_regs
, dmem
, words
, ofs
)
4544 HOST_WIDE_INT words
, ofs
;
4546 rtx
const im8
= GEN_INT (-8);
4547 rtx
const i64
= GEN_INT (64);
4548 rtx ins_tmps
[MAX_MOVE_WORDS
];
4549 rtx st_tmp_1
, st_tmp_2
, dreg
;
4550 rtx st_addr_1
, st_addr_2
, dmema
;
4553 dmema
= XEXP (dmem
, 0);
4554 if (GET_CODE (dmema
) == LO_SUM
)
4555 dmema
= force_reg (Pmode
, dmema
);
4557 /* Generate all the tmp registers we need. */
4558 if (data_regs
!= NULL
)
4559 for (i
= 0; i
< words
; ++i
)
4560 ins_tmps
[i
] = gen_reg_rtx(DImode
);
4561 st_tmp_1
= gen_reg_rtx(DImode
);
4562 st_tmp_2
= gen_reg_rtx(DImode
);
4565 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
4567 st_addr_2
= change_address (dmem
, DImode
,
4568 gen_rtx_AND (DImode
,
4569 plus_constant (dmema
, words
*8 - 1),
4571 set_mem_alias_set (st_addr_2
, 0);
4573 st_addr_1
= change_address (dmem
, DImode
,
4574 gen_rtx_AND (DImode
, dmema
, im8
));
4575 set_mem_alias_set (st_addr_1
, 0);
4577 /* Load up the destination end bits. */
4578 emit_move_insn (st_tmp_2
, st_addr_2
);
4579 emit_move_insn (st_tmp_1
, st_addr_1
);
4581 /* Shift the input data into place. */
4582 dreg
= copy_addr_to_reg (dmema
);
4583 if (WORDS_BIG_ENDIAN
)
4584 emit_move_insn (dreg
, plus_constant (dreg
, 7));
4585 if (data_regs
!= NULL
)
4587 for (i
= words
-1; i
>= 0; --i
)
4589 if (WORDS_BIG_ENDIAN
)
4591 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
4592 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
4596 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
4597 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
4600 for (i
= words
-1; i
> 0; --i
)
4602 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4603 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
4608 /* Split and merge the ends with the destination data. */
4609 if (WORDS_BIG_ENDIAN
)
4611 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
4612 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
4616 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
4617 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
4620 if (data_regs
!= NULL
)
4622 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
4623 st_tmp_2
, 1, OPTAB_WIDEN
);
4624 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
4625 st_tmp_1
, 1, OPTAB_WIDEN
);
4629 if (WORDS_BIG_ENDIAN
)
4630 emit_move_insn (st_addr_1
, st_tmp_1
);
4632 emit_move_insn (st_addr_2
, st_tmp_2
);
4633 for (i
= words
-1; i
> 0; --i
)
4635 rtx tmp
= change_address (dmem
, DImode
,
4636 gen_rtx_AND (DImode
,
4637 plus_constant(dmema
,
4638 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
4640 set_mem_alias_set (tmp
, 0);
4641 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
4643 if (WORDS_BIG_ENDIAN
)
4644 emit_move_insn (st_addr_2
, st_tmp_2
);
4646 emit_move_insn (st_addr_1
, st_tmp_1
);
4650 /* Expand string/block move operations.
4652 operands[0] is the pointer to the destination.
4653 operands[1] is the pointer to the source.
4654 operands[2] is the number of bytes to move.
4655 operands[3] is the alignment. */
4658 alpha_expand_block_move (operands
)
4661 rtx bytes_rtx
= operands
[2];
4662 rtx align_rtx
= operands
[3];
4663 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4664 HOST_WIDE_INT bytes
= orig_bytes
;
4665 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4666 HOST_WIDE_INT dst_align
= src_align
;
4667 rtx orig_src
= operands
[1];
4668 rtx orig_dst
= operands
[0];
4669 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
4671 unsigned int i
, words
, ofs
, nregs
= 0;
4673 if (orig_bytes
<= 0)
4675 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4678 /* Look for additional alignment information from recorded register info. */
4680 tmp
= XEXP (orig_src
, 0);
4681 if (GET_CODE (tmp
) == REG
)
4682 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4683 else if (GET_CODE (tmp
) == PLUS
4684 && GET_CODE (XEXP (tmp
, 0)) == REG
4685 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4687 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4688 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4692 if (a
>= 64 && c
% 8 == 0)
4694 else if (a
>= 32 && c
% 4 == 0)
4696 else if (a
>= 16 && c
% 2 == 0)
4701 tmp
= XEXP (orig_dst
, 0);
4702 if (GET_CODE (tmp
) == REG
)
4703 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4704 else if (GET_CODE (tmp
) == PLUS
4705 && GET_CODE (XEXP (tmp
, 0)) == REG
4706 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4708 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4709 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4713 if (a
>= 64 && c
% 8 == 0)
4715 else if (a
>= 32 && c
% 4 == 0)
4717 else if (a
>= 16 && c
% 2 == 0)
4722 /* Load the entire block into registers. */
4723 if (GET_CODE (XEXP (orig_src
, 0)) == ADDRESSOF
)
4725 enum machine_mode mode
;
4727 tmp
= XEXP (XEXP (orig_src
, 0), 0);
4729 /* Don't use the existing register if we're reading more than
4730 is held in the register. Nor if there is not a mode that
4731 handles the exact size. */
4732 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4734 && GET_MODE_SIZE (GET_MODE (tmp
)) >= bytes
)
4738 data_regs
[nregs
] = gen_lowpart (DImode
, tmp
);
4739 data_regs
[nregs
+ 1] = gen_highpart (DImode
, tmp
);
4743 data_regs
[nregs
++] = gen_lowpart (mode
, tmp
);
4748 /* No appropriate mode; fall back on memory. */
4749 orig_src
= replace_equiv_address (orig_src
,
4750 copy_addr_to_reg (XEXP (orig_src
, 0)));
4751 src_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4755 if (src_align
>= 64 && bytes
>= 8)
4759 for (i
= 0; i
< words
; ++i
)
4760 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4762 for (i
= 0; i
< words
; ++i
)
4763 emit_move_insn (data_regs
[nregs
+ i
],
4764 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
4771 if (src_align
>= 32 && bytes
>= 4)
4775 for (i
= 0; i
< words
; ++i
)
4776 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
4778 for (i
= 0; i
< words
; ++i
)
4779 emit_move_insn (data_regs
[nregs
+ i
],
4780 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
4791 for (i
= 0; i
< words
+1; ++i
)
4792 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4794 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
4802 if (! TARGET_BWX
&& bytes
>= 4)
4804 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
4805 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
4812 if (src_align
>= 16)
4815 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4816 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
4819 } while (bytes
>= 2);
4821 else if (! TARGET_BWX
)
4823 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4824 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
4832 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
4833 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
4840 if (nregs
> ARRAY_SIZE (data_regs
))
4843 /* Now save it back out again. */
4847 if (GET_CODE (XEXP (orig_dst
, 0)) == ADDRESSOF
)
4849 enum machine_mode mode
;
4850 tmp
= XEXP (XEXP (orig_dst
, 0), 0);
4852 mode
= mode_for_size (orig_bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4853 if (GET_MODE (tmp
) == mode
)
4857 emit_move_insn (tmp
, data_regs
[0]);
4862 else if (nregs
== 2 && mode
== TImode
)
4864 /* Undo the subregging done above when copying between
4865 two TImode registers. */
4866 if (GET_CODE (data_regs
[0]) == SUBREG
4867 && GET_MODE (SUBREG_REG (data_regs
[0])) == TImode
)
4868 emit_move_insn (tmp
, SUBREG_REG (data_regs
[0]));
4874 emit_move_insn (gen_lowpart (DImode
, tmp
), data_regs
[0]);
4875 emit_move_insn (gen_highpart (DImode
, tmp
), data_regs
[1]);
4879 emit_no_conflict_block (seq
, tmp
, data_regs
[0],
4880 data_regs
[1], NULL_RTX
);
4888 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4889 /* ??? Optimize mode < dst_mode with strict_low_part. */
4891 /* No appropriate mode; fall back on memory. We can speed things
4892 up by recognizing extra alignment information. */
4893 orig_dst
= replace_equiv_address (orig_dst
,
4894 copy_addr_to_reg (XEXP (orig_dst
, 0)));
4895 dst_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4898 /* Write out the data in whatever chunks reading the source allowed. */
4899 if (dst_align
>= 64)
4901 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4903 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
4910 if (dst_align
>= 32)
4912 /* If the source has remaining DImode regs, write them out in
4914 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4916 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
4917 NULL_RTX
, 1, OPTAB_WIDEN
);
4919 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4920 gen_lowpart (SImode
, data_regs
[i
]));
4921 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
4922 gen_lowpart (SImode
, tmp
));
4927 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4929 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4936 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4938 /* Write out a remaining block of words using unaligned methods. */
4940 for (words
= 1; i
+ words
< nregs
; words
++)
4941 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4945 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4947 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4954 /* Due to the above, this won't be aligned. */
4955 /* ??? If we have more than one of these, consider constructing full
4956 words in registers and using alpha_expand_unaligned_store_words. */
4957 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4959 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4964 if (dst_align
>= 16)
4965 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4967 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4972 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4974 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4979 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
4981 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4995 alpha_expand_block_clear (operands
)
4998 rtx bytes_rtx
= operands
[1];
4999 rtx align_rtx
= operands
[2];
5000 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
5001 HOST_WIDE_INT bytes
= orig_bytes
;
5002 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
5003 HOST_WIDE_INT alignofs
= 0;
5004 rtx orig_dst
= operands
[0];
5006 int i
, words
, ofs
= 0;
5008 if (orig_bytes
<= 0)
5010 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
5013 /* Look for stricter alignment. */
5014 tmp
= XEXP (orig_dst
, 0);
5015 if (GET_CODE (tmp
) == REG
)
5016 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
5017 else if (GET_CODE (tmp
) == PLUS
5018 && GET_CODE (XEXP (tmp
, 0)) == REG
5019 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
5021 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
5022 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
5027 align
= a
, alignofs
= 8 - c
% 8;
5029 align
= a
, alignofs
= 4 - c
% 4;
5031 align
= a
, alignofs
= 2 - c
% 2;
5034 else if (GET_CODE (tmp
) == ADDRESSOF
)
5036 enum machine_mode mode
;
5038 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
5039 if (GET_MODE (XEXP (tmp
, 0)) == mode
)
5041 emit_move_insn (XEXP (tmp
, 0), const0_rtx
);
5045 /* No appropriate mode; fall back on memory. */
5046 orig_dst
= replace_equiv_address (orig_dst
, copy_addr_to_reg (tmp
));
5047 align
= GET_MODE_BITSIZE (GET_MODE (XEXP (tmp
, 0)));
5050 /* Handle an unaligned prefix first. */
5054 #if HOST_BITS_PER_WIDE_INT >= 64
5055 /* Given that alignofs is bounded by align, the only time BWX could
5056 generate three stores is for a 7 byte fill. Prefer two individual
5057 stores over a load/mask/store sequence. */
5058 if ((!TARGET_BWX
|| alignofs
== 7)
5060 && !(alignofs
== 4 && bytes
>= 4))
5062 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
5063 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
5067 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
5068 set_mem_alias_set (mem
, 0);
5070 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
5071 if (bytes
< alignofs
)
5073 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
5084 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
5085 NULL_RTX
, 1, OPTAB_WIDEN
);
5087 emit_move_insn (mem
, tmp
);
5091 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
5093 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5098 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
5100 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
5105 if (alignofs
== 4 && bytes
>= 4)
5107 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
5113 /* If we've not used the extra lead alignment information by now,
5114 we won't be able to. Downgrade align to match what's left over. */
5117 alignofs
= alignofs
& -alignofs
;
5118 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
5122 /* Handle a block of contiguous long-words. */
5124 if (align
>= 64 && bytes
>= 8)
5128 for (i
= 0; i
< words
; ++i
)
5129 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
5136 /* If the block is large and appropriately aligned, emit a single
5137 store followed by a sequence of stq_u insns. */
5139 if (align
>= 32 && bytes
> 16)
5143 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
5147 orig_dsta
= XEXP (orig_dst
, 0);
5148 if (GET_CODE (orig_dsta
) == LO_SUM
)
5149 orig_dsta
= force_reg (Pmode
, orig_dsta
);
5152 for (i
= 0; i
< words
; ++i
)
5155 = change_address (orig_dst
, DImode
,
5156 gen_rtx_AND (DImode
,
5157 plus_constant (orig_dsta
, ofs
+ i
*8),
5159 set_mem_alias_set (mem
, 0);
5160 emit_move_insn (mem
, const0_rtx
);
5163 /* Depending on the alignment, the first stq_u may have overlapped
5164 with the initial stl, which means that the last stq_u didn't
5165 write as much as it would appear. Leave those questionable bytes
5167 bytes
-= words
* 8 - 4;
5168 ofs
+= words
* 8 - 4;
5171 /* Handle a smaller block of aligned words. */
5173 if ((align
>= 64 && bytes
== 4)
5174 || (align
== 32 && bytes
>= 4))
5178 for (i
= 0; i
< words
; ++i
)
5179 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
5186 /* An unaligned block uses stq_u stores for as many as possible. */
5192 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
5198 /* Next clean up any trailing pieces. */
5200 #if HOST_BITS_PER_WIDE_INT >= 64
5201 /* Count the number of bits in BYTES for which aligned stores could
5204 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
5208 /* If we have appropriate alignment (and it wouldn't take too many
5209 instructions otherwise), mask out the bytes we need. */
5210 if (TARGET_BWX
? words
> 2 : bytes
> 0)
5217 mem
= adjust_address (orig_dst
, DImode
, ofs
);
5218 set_mem_alias_set (mem
, 0);
5220 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5222 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
5223 NULL_RTX
, 1, OPTAB_WIDEN
);
5225 emit_move_insn (mem
, tmp
);
5228 else if (align
>= 32 && bytes
< 4)
5233 mem
= adjust_address (orig_dst
, SImode
, ofs
);
5234 set_mem_alias_set (mem
, 0);
5236 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5238 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
5239 NULL_RTX
, 1, OPTAB_WIDEN
);
5241 emit_move_insn (mem
, tmp
);
5247 if (!TARGET_BWX
&& bytes
>= 4)
5249 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
5259 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
5263 } while (bytes
>= 2);
5265 else if (! TARGET_BWX
)
5267 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
5275 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5283 /* Returns a mask so that zap(x, value) == x & mask. */
5286 alpha_expand_zap_mask (value
)
5287 HOST_WIDE_INT value
;
5292 if (HOST_BITS_PER_WIDE_INT
>= 64)
5294 HOST_WIDE_INT mask
= 0;
5296 for (i
= 7; i
>= 0; --i
)
5299 if (!((value
>> i
) & 1))
5303 result
= gen_int_mode (mask
, DImode
);
5305 else if (HOST_BITS_PER_WIDE_INT
== 32)
5307 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
5309 for (i
= 7; i
>= 4; --i
)
5312 if (!((value
>> i
) & 1))
5316 for (i
= 3; i
>= 0; --i
)
5319 if (!((value
>> i
) & 1))
5323 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
5332 alpha_expand_builtin_vector_binop (gen
, mode
, op0
, op1
, op2
)
5333 rtx (*gen
) PARAMS ((rtx
, rtx
, rtx
));
5334 enum machine_mode mode
;
5337 op0
= gen_lowpart (mode
, op0
);
5339 if (op1
== const0_rtx
)
5340 op1
= CONST0_RTX (mode
);
5342 op1
= gen_lowpart (mode
, op1
);
5344 if (op2
== const0_rtx
)
5345 op2
= CONST0_RTX (mode
);
5347 op2
= gen_lowpart (mode
, op2
);
5349 emit_insn ((*gen
) (op0
, op1
, op2
));
5352 /* Adjust the cost of a scheduling dependency. Return the new cost of
5353 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5356 alpha_adjust_cost (insn
, link
, dep_insn
, cost
)
5362 enum attr_type insn_type
, dep_insn_type
;
5364 /* If the dependence is an anti-dependence, there is no cost. For an
5365 output dependence, there is sometimes a cost, but it doesn't seem
5366 worth handling those few cases. */
5367 if (REG_NOTE_KIND (link
) != 0)
5370 /* If we can't recognize the insns, we can't really do anything. */
5371 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
5374 insn_type
= get_attr_type (insn
);
5375 dep_insn_type
= get_attr_type (dep_insn
);
5377 /* Bring in the user-defined memory latency. */
5378 if (dep_insn_type
== TYPE_ILD
5379 || dep_insn_type
== TYPE_FLD
5380 || dep_insn_type
== TYPE_LDSYM
)
5381 cost
+= alpha_memory_latency
-1;
5383 /* Everything else handled in DFA bypasses now. */
5388 /* The number of instructions that can be issued per cycle. */
5393 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
5397 alpha_use_dfa_pipeline_interface ()
5402 /* How many alternative schedules to try. This should be as wide as the
5403 scheduling freedom in the DFA, but no wider. Making this value too
5404 large results extra work for the scheduler.
5406 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5407 alternative schedules. For EV5, we can choose between E0/E1 and
5408 FA/FM. For EV6, an arithmatic insn can be issued to U0/U1/L0/L1. */
5411 alpha_multipass_dfa_lookahead ()
5413 return (alpha_cpu
== PROCESSOR_EV6
? 4 : 2);
5416 /* Machine-specific function data. */
5418 struct machine_function
GTY(())
5421 /* List of call information words for calls from this function. */
5422 struct rtx_def
*first_ciw
;
5423 struct rtx_def
*last_ciw
;
5426 /* List of deferred case vectors. */
5427 struct rtx_def
*addr_list
;
5430 const char *some_ld_name
;
5433 /* How to allocate a 'struct machine_function'. */
5435 static struct machine_function
*
5436 alpha_init_machine_status ()
5438 return ((struct machine_function
*)
5439 ggc_alloc_cleared (sizeof (struct machine_function
)));
5442 /* Functions to save and restore alpha_return_addr_rtx. */
5444 /* Start the ball rolling with RETURN_ADDR_RTX. */
5447 alpha_return_addr (count
, frame
)
5449 rtx frame ATTRIBUTE_UNUSED
;
5454 return get_hard_reg_initial_val (Pmode
, REG_RA
);
5457 /* Return or create a pseudo containing the gp value for the current
5458 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5461 alpha_gp_save_rtx ()
5463 rtx r
= get_hard_reg_initial_val (DImode
, 29);
5464 if (GET_CODE (r
) != MEM
)
5465 r
= gen_mem_addressof (r
, NULL_TREE
);
5470 alpha_ra_ever_killed ()
5474 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
5475 return regs_ever_live
[REG_RA
];
5477 push_topmost_sequence ();
5479 pop_topmost_sequence ();
5481 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
5485 /* Return the trap mode suffix applicable to the current
5486 instruction, or NULL. */
5489 get_trap_mode_suffix ()
5491 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
5495 case TRAP_SUFFIX_NONE
:
5498 case TRAP_SUFFIX_SU
:
5499 if (alpha_fptm
>= ALPHA_FPTM_SU
)
5503 case TRAP_SUFFIX_SUI
:
5504 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
5508 case TRAP_SUFFIX_V_SV
:
5516 case ALPHA_FPTM_SUI
:
5521 case TRAP_SUFFIX_V_SV_SVI
:
5530 case ALPHA_FPTM_SUI
:
5535 case TRAP_SUFFIX_U_SU_SUI
:
5544 case ALPHA_FPTM_SUI
:
5552 /* Return the rounding mode suffix applicable to the current
5553 instruction, or NULL. */
5556 get_round_mode_suffix ()
5558 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5562 case ROUND_SUFFIX_NONE
:
5564 case ROUND_SUFFIX_NORMAL
:
5567 case ALPHA_FPRM_NORM
:
5569 case ALPHA_FPRM_MINF
:
5571 case ALPHA_FPRM_CHOP
:
5573 case ALPHA_FPRM_DYN
:
5578 case ROUND_SUFFIX_C
:
5584 /* Locate some local-dynamic symbol still in use by this function
5585 so that we can print its name in some movdi_er_tlsldm pattern. */
5588 get_some_local_dynamic_name ()
5592 if (cfun
->machine
->some_ld_name
)
5593 return cfun
->machine
->some_ld_name
;
5595 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5597 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5598 return cfun
->machine
->some_ld_name
;
5604 get_some_local_dynamic_name_1 (px
, data
)
5606 void *data ATTRIBUTE_UNUSED
;
5610 if (GET_CODE (x
) == SYMBOL_REF
)
5612 const char *str
= XSTR (x
, 0);
5613 if (str
[0] == '@' && str
[1] == 'D')
5615 cfun
->machine
->some_ld_name
= str
;
5623 /* Print an operand. Recognize special options, documented below. */
5626 print_operand (file
, x
, code
)
5636 /* Print the assembler name of the current function. */
5637 assemble_name (file
, alpha_fnname
);
5641 assemble_name (file
, get_some_local_dynamic_name ());
5646 const char *trap
= get_trap_mode_suffix ();
5647 const char *round
= get_round_mode_suffix ();
5650 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5651 (trap
? trap
: ""), (round
? round
: ""));
5656 /* Generates single precision instruction suffix. */
5657 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5661 /* Generates double precision instruction suffix. */
5662 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5666 if (alpha_this_literal_sequence_number
== 0)
5667 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5668 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5672 if (alpha_this_gpdisp_sequence_number
== 0)
5673 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5674 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5678 if (GET_CODE (x
) == HIGH
)
5679 output_addr_const (file
, XEXP (x
, 0));
5681 output_operand_lossage ("invalid %%H value");
5688 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5690 x
= XVECEXP (x
, 0, 0);
5691 lituse
= "lituse_tlsgd";
5693 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5695 x
= XVECEXP (x
, 0, 0);
5696 lituse
= "lituse_tlsldm";
5698 else if (GET_CODE (x
) == CONST_INT
)
5699 lituse
= "lituse_jsr";
5702 output_operand_lossage ("invalid %%J value");
5706 if (x
!= const0_rtx
)
5707 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5712 /* If this operand is the constant zero, write it as "$31". */
5713 if (GET_CODE (x
) == REG
)
5714 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5715 else if (x
== CONST0_RTX (GET_MODE (x
)))
5716 fprintf (file
, "$31");
5718 output_operand_lossage ("invalid %%r value");
5722 /* Similar, but for floating-point. */
5723 if (GET_CODE (x
) == REG
)
5724 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5725 else if (x
== CONST0_RTX (GET_MODE (x
)))
5726 fprintf (file
, "$f31");
5728 output_operand_lossage ("invalid %%R value");
5732 /* Write the 1's complement of a constant. */
5733 if (GET_CODE (x
) != CONST_INT
)
5734 output_operand_lossage ("invalid %%N value");
5736 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5740 /* Write 1 << C, for a constant C. */
5741 if (GET_CODE (x
) != CONST_INT
)
5742 output_operand_lossage ("invalid %%P value");
5744 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5748 /* Write the high-order 16 bits of a constant, sign-extended. */
5749 if (GET_CODE (x
) != CONST_INT
)
5750 output_operand_lossage ("invalid %%h value");
5752 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5756 /* Write the low-order 16 bits of a constant, sign-extended. */
5757 if (GET_CODE (x
) != CONST_INT
)
5758 output_operand_lossage ("invalid %%L value");
5760 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5761 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5765 /* Write mask for ZAP insn. */
5766 if (GET_CODE (x
) == CONST_DOUBLE
)
5768 HOST_WIDE_INT mask
= 0;
5769 HOST_WIDE_INT value
;
5771 value
= CONST_DOUBLE_LOW (x
);
5772 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5777 value
= CONST_DOUBLE_HIGH (x
);
5778 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5781 mask
|= (1 << (i
+ sizeof (int)));
5783 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5786 else if (GET_CODE (x
) == CONST_INT
)
5788 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5790 for (i
= 0; i
< 8; i
++, value
>>= 8)
5794 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5797 output_operand_lossage ("invalid %%m value");
5801 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5802 if (GET_CODE (x
) != CONST_INT
5803 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5804 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5805 output_operand_lossage ("invalid %%M value");
5807 fprintf (file
, "%s",
5808 (INTVAL (x
) == 8 ? "b"
5809 : INTVAL (x
) == 16 ? "w"
5810 : INTVAL (x
) == 32 ? "l"
5815 /* Similar, except do it from the mask. */
5816 if (GET_CODE (x
) == CONST_INT
)
5818 HOST_WIDE_INT value
= INTVAL (x
);
5825 if (value
== 0xffff)
5830 if (value
== 0xffffffff)
5841 else if (HOST_BITS_PER_WIDE_INT
== 32
5842 && GET_CODE (x
) == CONST_DOUBLE
5843 && CONST_DOUBLE_LOW (x
) == 0xffffffff
5844 && CONST_DOUBLE_HIGH (x
) == 0)
5849 output_operand_lossage ("invalid %%U value");
5853 /* Write the constant value divided by 8 for little-endian mode or
5854 (56 - value) / 8 for big-endian mode. */
5856 if (GET_CODE (x
) != CONST_INT
5857 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5860 || (INTVAL (x
) & 7) != 0)
5861 output_operand_lossage ("invalid %%s value");
5863 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5865 ? (56 - INTVAL (x
)) / 8
5870 /* Same, except compute (64 - c) / 8 */
5872 if (GET_CODE (x
) != CONST_INT
5873 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5874 && (INTVAL (x
) & 7) != 8)
5875 output_operand_lossage ("invalid %%s value");
5877 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5882 /* On Unicos/Mk systems: use a DEX expression if the symbol
5883 clashes with a register name. */
5884 int dex
= unicosmk_need_dex (x
);
5886 fprintf (file
, "DEX(%d)", dex
);
5888 output_addr_const (file
, x
);
5892 case 'C': case 'D': case 'c': case 'd':
5893 /* Write out comparison name. */
5895 enum rtx_code c
= GET_CODE (x
);
5897 if (GET_RTX_CLASS (c
) != '<')
5898 output_operand_lossage ("invalid %%C value");
5900 else if (code
== 'D')
5901 c
= reverse_condition (c
);
5902 else if (code
== 'c')
5903 c
= swap_condition (c
);
5904 else if (code
== 'd')
5905 c
= swap_condition (reverse_condition (c
));
5908 fprintf (file
, "ule");
5910 fprintf (file
, "ult");
5911 else if (c
== UNORDERED
)
5912 fprintf (file
, "un");
5914 fprintf (file
, "%s", GET_RTX_NAME (c
));
5919 /* Write the divide or modulus operator. */
5920 switch (GET_CODE (x
))
5923 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5926 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5929 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5932 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5935 output_operand_lossage ("invalid %%E value");
5941 /* Write "_u" for unaligned access. */
5942 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
5943 fprintf (file
, "_u");
5947 if (GET_CODE (x
) == REG
)
5948 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5949 else if (GET_CODE (x
) == MEM
)
5950 output_address (XEXP (x
, 0));
5951 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
5953 switch (XINT (XEXP (x
, 0), 1))
5957 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
5960 output_operand_lossage ("unknown relocation unspec");
5965 output_addr_const (file
, x
);
5969 output_operand_lossage ("invalid %%xn code");
5974 print_operand_address (file
, addr
)
5979 HOST_WIDE_INT offset
= 0;
5981 if (GET_CODE (addr
) == AND
)
5982 addr
= XEXP (addr
, 0);
5984 if (GET_CODE (addr
) == PLUS
5985 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5987 offset
= INTVAL (XEXP (addr
, 1));
5988 addr
= XEXP (addr
, 0);
5991 if (GET_CODE (addr
) == LO_SUM
)
5993 const char *reloc16
, *reloclo
;
5994 rtx op1
= XEXP (addr
, 1);
5996 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
5998 op1
= XEXP (op1
, 0);
5999 switch (XINT (op1
, 1))
6003 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
6007 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
6010 output_operand_lossage ("unknown relocation unspec");
6014 output_addr_const (file
, XVECEXP (op1
, 0, 0));
6019 reloclo
= "gprellow";
6020 output_addr_const (file
, op1
);
6026 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
6029 addr
= XEXP (addr
, 0);
6030 if (GET_CODE (addr
) == REG
)
6031 basereg
= REGNO (addr
);
6032 else if (GET_CODE (addr
) == SUBREG
6033 && GET_CODE (SUBREG_REG (addr
)) == REG
)
6034 basereg
= subreg_regno (addr
);
6038 fprintf (file
, "($%d)\t\t!%s", basereg
,
6039 (basereg
== 29 ? reloc16
: reloclo
));
6043 if (GET_CODE (addr
) == REG
)
6044 basereg
= REGNO (addr
);
6045 else if (GET_CODE (addr
) == SUBREG
6046 && GET_CODE (SUBREG_REG (addr
)) == REG
)
6047 basereg
= subreg_regno (addr
);
6048 else if (GET_CODE (addr
) == CONST_INT
)
6049 offset
= INTVAL (addr
);
6051 #if TARGET_ABI_OPEN_VMS
6052 else if (GET_CODE (addr
) == SYMBOL_REF
)
6054 fprintf (file
, "%s", XSTR (addr
, 0));
6057 else if (GET_CODE (addr
) == CONST
6058 && GET_CODE (XEXP (addr
, 0)) == PLUS
6059 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
6061 fprintf (file
, "%s+%d",
6062 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
6063 INTVAL (XEXP (XEXP (addr
, 0), 1)));
6071 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
6072 fprintf (file
, "($%d)", basereg
);
6075 /* Emit RTL insns to initialize the variable parts of a trampoline at
6076 TRAMP. FNADDR is an RTX for the address of the function's pure
6077 code. CXT is an RTX for the static chain value for the function.
6079 The three offset parameters are for the individual template's
6080 layout. A JMPOFS < 0 indicates that the trampoline does not
6081 contain instructions at all.
6083 We assume here that a function will be called many more times than
6084 its address is taken (e.g., it might be passed to qsort), so we
6085 take the trouble to initialize the "hint" field in the JMP insn.
6086 Note that the hint field is PC (new) + 4 * bits 13:0. */
6089 alpha_initialize_trampoline (tramp
, fnaddr
, cxt
, fnofs
, cxtofs
, jmpofs
)
6090 rtx tramp
, fnaddr
, cxt
;
6091 int fnofs
, cxtofs
, jmpofs
;
6093 rtx temp
, temp1
, addr
;
6094 /* VMS really uses DImode pointers in memory at this point. */
6095 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
6097 #ifdef POINTERS_EXTEND_UNSIGNED
6098 fnaddr
= convert_memory_address (mode
, fnaddr
);
6099 cxt
= convert_memory_address (mode
, cxt
);
6102 /* Store function address and CXT. */
6103 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
6104 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
6105 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
6106 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
6108 /* This has been disabled since the hint only has a 32k range, and in
6109 no existing OS is the stack within 32k of the text segment. */
6110 if (0 && jmpofs
>= 0)
6112 /* Compute hint value. */
6113 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
6114 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
6116 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
6117 build_int_2 (2, 0), NULL_RTX
, 1);
6118 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
6119 GEN_INT (0x3fff), 0);
6121 /* Merge in the hint. */
6122 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
6123 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
6124 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
6125 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
6127 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
6130 #ifdef TRANSFER_FROM_TRAMPOLINE
6131 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
6132 0, VOIDmode
, 1, tramp
, Pmode
);
6136 emit_insn (gen_imb ());
6139 /* Determine where to put an argument to a function.
6140 Value is zero to push the argument on the stack,
6141 or a hard register in which to store the argument.
6143 MODE is the argument's machine mode.
6144 TYPE is the data type of the argument (as a tree).
6145 This is null for libcalls where that information may
6147 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6148 the preceding args and about the function being called.
6149 NAMED is nonzero if this argument is a named parameter
6150 (otherwise it is an extra parameter matching an ellipsis).
6152 On Alpha the first 6 words of args are normally in registers
6153 and the rest are pushed. */
6156 function_arg (cum
, mode
, type
, named
)
6157 CUMULATIVE_ARGS cum
;
6158 enum machine_mode mode
;
6160 int named ATTRIBUTE_UNUSED
;
6165 /* Set up defaults for FP operands passed in FP registers, and
6166 integral operands passed in integer registers. */
6168 && (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
6169 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
6174 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
6175 the three platforms, so we can't avoid conditional compilation. */
6176 #if TARGET_ABI_OPEN_VMS
6178 if (mode
== VOIDmode
)
6179 return alpha_arg_info_reg_val (cum
);
6181 num_args
= cum
.num_args
;
6182 if (num_args
>= 6 || MUST_PASS_IN_STACK (mode
, type
))
6186 #if TARGET_ABI_UNICOSMK
6190 /* If this is the last argument, generate the call info word (CIW). */
6191 /* ??? We don't include the caller's line number in the CIW because
6192 I don't know how to determine it if debug infos are turned off. */
6193 if (mode
== VOIDmode
)
6202 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
6203 if (cum
.reg_args_type
[i
])
6204 lo
|= (1 << (7 - i
));
6206 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
6209 lo
|= cum
.num_reg_words
;
6211 #if HOST_BITS_PER_WIDE_INT == 32
6212 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
6214 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
6215 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
6218 ciw
= immed_double_const (lo
, hi
, DImode
);
6220 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
6221 UNSPEC_UMK_LOAD_CIW
);
6224 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
6225 num_args
= cum
.num_reg_words
;
6226 if (MUST_PASS_IN_STACK (mode
, type
)
6227 || cum
.num_reg_words
+ size
> 6 || cum
.force_stack
)
6229 else if (type
&& TYPE_MODE (type
) == BLKmode
)
6233 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
6234 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
6236 /* The argument fits in two registers. Note that we still need to
6237 reserve a register for empty structures. */
6241 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
6244 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
6245 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
6246 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
6256 /* VOID is passed as a special flag for "last argument". */
6257 if (type
== void_type_node
)
6259 else if (MUST_PASS_IN_STACK (mode
, type
))
6261 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum
, mode
, type
, named
))
6264 #endif /* TARGET_ABI_UNICOSMK */
6265 #endif /* TARGET_ABI_OPEN_VMS */
6267 return gen_rtx_REG (mode
, num_args
+ basereg
);
6271 alpha_build_va_list ()
6273 tree base
, ofs
, record
, type_decl
;
6275 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6276 return ptr_type_node
;
6278 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6279 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6280 TREE_CHAIN (record
) = type_decl
;
6281 TYPE_NAME (record
) = type_decl
;
6283 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6285 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
6287 DECL_FIELD_CONTEXT (ofs
) = record
;
6289 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
6291 DECL_FIELD_CONTEXT (base
) = record
;
6292 TREE_CHAIN (base
) = ofs
;
6294 TYPE_FIELDS (record
) = base
;
6295 layout_type (record
);
6301 alpha_va_start (valist
, nextarg
)
6303 rtx nextarg ATTRIBUTE_UNUSED
;
6305 HOST_WIDE_INT offset
;
6306 tree t
, offset_field
, base_field
;
6308 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6311 if (TARGET_ABI_UNICOSMK
)
6312 std_expand_builtin_va_start (valist
, nextarg
);
6314 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6315 up by 48, storing fp arg registers in the first 48 bytes, and the
6316 integer arg registers in the next 48 bytes. This is only done,
6317 however, if any integer registers need to be stored.
6319 If no integer registers need be stored, then we must subtract 48
6320 in order to account for the integer arg registers which are counted
6321 in argsize above, but which are not actually stored on the stack. */
6324 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6326 offset
= -6 * UNITS_PER_WORD
;
6328 if (TARGET_ABI_OPEN_VMS
)
6330 nextarg
= plus_constant (nextarg
, offset
);
6331 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
6332 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
6333 make_tree (ptr_type_node
, nextarg
));
6334 TREE_SIDE_EFFECTS (t
) = 1;
6336 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6340 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6341 offset_field
= TREE_CHAIN (base_field
);
6343 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6344 valist
, base_field
);
6345 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6346 valist
, offset_field
);
6348 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6349 t
= build (PLUS_EXPR
, ptr_type_node
, t
, build_int_2 (offset
, 0));
6350 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6351 TREE_SIDE_EFFECTS (t
) = 1;
6352 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6354 t
= build_int_2 (NUM_ARGS
* UNITS_PER_WORD
, 0);
6355 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6356 TREE_SIDE_EFFECTS (t
) = 1;
6357 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6362 alpha_va_arg (valist
, type
)
6366 tree t
, type_size
, rounded_size
;
6367 tree offset_field
, base_field
, addr_tree
, addend
;
6368 tree wide_type
, wide_ofs
;
6371 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6372 return std_expand_builtin_va_arg (valist
, type
);
6374 if (type
== error_mark_node
6375 || (type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
))) == NULL
6376 || TREE_OVERFLOW (type_size
))
6377 rounded_size
= size_zero_node
;
6379 rounded_size
= fold (build (MULT_EXPR
, sizetype
,
6380 fold (build (TRUNC_DIV_EXPR
, sizetype
,
6381 fold (build (PLUS_EXPR
, sizetype
,
6387 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6388 offset_field
= TREE_CHAIN (base_field
);
6390 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6391 valist
, base_field
);
6392 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6393 valist
, offset_field
);
6395 /* If the type could not be passed in registers, skip the block
6396 reserved for the registers. */
6397 if (MUST_PASS_IN_STACK (TYPE_MODE (type
), type
))
6399 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6400 build (MAX_EXPR
, TREE_TYPE (offset_field
),
6401 offset_field
, build_int_2 (6*8, 0)));
6402 TREE_SIDE_EFFECTS (t
) = 1;
6403 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6406 wide_type
= make_signed_type (64);
6407 wide_ofs
= save_expr (build1 (CONVERT_EXPR
, wide_type
, offset_field
));
6411 if (TYPE_MODE (type
) == TFmode
|| TYPE_MODE (type
) == TCmode
)
6414 rounded_size
= size_int (UNITS_PER_WORD
);
6416 else if (FLOAT_TYPE_P (type
))
6418 tree fpaddend
, cond
;
6420 fpaddend
= fold (build (PLUS_EXPR
, TREE_TYPE (addend
),
6421 addend
, build_int_2 (-6*8, 0)));
6423 cond
= fold (build (LT_EXPR
, integer_type_node
,
6424 wide_ofs
, build_int_2 (6*8, 0)));
6426 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
6430 addr_tree
= build (PLUS_EXPR
, TREE_TYPE (base_field
),
6431 base_field
, addend
);
6433 addr
= expand_expr (addr_tree
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
6434 addr
= copy_to_reg (addr
);
6436 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6437 build (PLUS_EXPR
, TREE_TYPE (offset_field
),
6438 offset_field
, rounded_size
));
6439 TREE_SIDE_EFFECTS (t
) = 1;
6440 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6444 addr
= force_reg (Pmode
, addr
);
6445 addr
= gen_rtx_MEM (Pmode
, addr
);
6455 ALPHA_BUILTIN_CMPBGE
,
6456 ALPHA_BUILTIN_EXTBL
,
6457 ALPHA_BUILTIN_EXTWL
,
6458 ALPHA_BUILTIN_EXTLL
,
6459 ALPHA_BUILTIN_EXTQL
,
6460 ALPHA_BUILTIN_EXTWH
,
6461 ALPHA_BUILTIN_EXTLH
,
6462 ALPHA_BUILTIN_EXTQH
,
6463 ALPHA_BUILTIN_INSBL
,
6464 ALPHA_BUILTIN_INSWL
,
6465 ALPHA_BUILTIN_INSLL
,
6466 ALPHA_BUILTIN_INSQL
,
6467 ALPHA_BUILTIN_INSWH
,
6468 ALPHA_BUILTIN_INSLH
,
6469 ALPHA_BUILTIN_INSQH
,
6470 ALPHA_BUILTIN_MSKBL
,
6471 ALPHA_BUILTIN_MSKWL
,
6472 ALPHA_BUILTIN_MSKLL
,
6473 ALPHA_BUILTIN_MSKQL
,
6474 ALPHA_BUILTIN_MSKWH
,
6475 ALPHA_BUILTIN_MSKLH
,
6476 ALPHA_BUILTIN_MSKQH
,
6477 ALPHA_BUILTIN_UMULH
,
6479 ALPHA_BUILTIN_ZAPNOT
,
6480 ALPHA_BUILTIN_AMASK
,
6481 ALPHA_BUILTIN_IMPLVER
,
6483 ALPHA_BUILTIN_THREAD_POINTER
,
6484 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6487 ALPHA_BUILTIN_MINUB8
,
6488 ALPHA_BUILTIN_MINSB8
,
6489 ALPHA_BUILTIN_MINUW4
,
6490 ALPHA_BUILTIN_MINSW4
,
6491 ALPHA_BUILTIN_MAXUB8
,
6492 ALPHA_BUILTIN_MAXSB8
,
6493 ALPHA_BUILTIN_MAXUW4
,
6494 ALPHA_BUILTIN_MAXSW4
,
6498 ALPHA_BUILTIN_UNPKBL
,
6499 ALPHA_BUILTIN_UNPKBW
,
6504 ALPHA_BUILTIN_CTPOP
,
6509 static unsigned int const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6510 CODE_FOR_builtin_cmpbge
,
6511 CODE_FOR_builtin_extbl
,
6512 CODE_FOR_builtin_extwl
,
6513 CODE_FOR_builtin_extll
,
6514 CODE_FOR_builtin_extql
,
6515 CODE_FOR_builtin_extwh
,
6516 CODE_FOR_builtin_extlh
,
6517 CODE_FOR_builtin_extqh
,
6518 CODE_FOR_builtin_insbl
,
6519 CODE_FOR_builtin_inswl
,
6520 CODE_FOR_builtin_insll
,
6521 CODE_FOR_builtin_insql
,
6522 CODE_FOR_builtin_inswh
,
6523 CODE_FOR_builtin_inslh
,
6524 CODE_FOR_builtin_insqh
,
6525 CODE_FOR_builtin_mskbl
,
6526 CODE_FOR_builtin_mskwl
,
6527 CODE_FOR_builtin_mskll
,
6528 CODE_FOR_builtin_mskql
,
6529 CODE_FOR_builtin_mskwh
,
6530 CODE_FOR_builtin_msklh
,
6531 CODE_FOR_builtin_mskqh
,
6532 CODE_FOR_umuldi3_highpart
,
6533 CODE_FOR_builtin_zap
,
6534 CODE_FOR_builtin_zapnot
,
6535 CODE_FOR_builtin_amask
,
6536 CODE_FOR_builtin_implver
,
6537 CODE_FOR_builtin_rpcc
,
6542 CODE_FOR_builtin_minub8
,
6543 CODE_FOR_builtin_minsb8
,
6544 CODE_FOR_builtin_minuw4
,
6545 CODE_FOR_builtin_minsw4
,
6546 CODE_FOR_builtin_maxub8
,
6547 CODE_FOR_builtin_maxsb8
,
6548 CODE_FOR_builtin_maxuw4
,
6549 CODE_FOR_builtin_maxsw4
,
6550 CODE_FOR_builtin_perr
,
6551 CODE_FOR_builtin_pklb
,
6552 CODE_FOR_builtin_pkwb
,
6553 CODE_FOR_builtin_unpkbl
,
6554 CODE_FOR_builtin_unpkbw
,
6557 CODE_FOR_builtin_cttz
,
6558 CODE_FOR_builtin_ctlz
,
6559 CODE_FOR_builtin_ctpop
6562 struct alpha_builtin_def
6565 enum alpha_builtin code
;
6566 unsigned int target_mask
;
6569 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6570 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0 },
6571 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0 }
6574 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6575 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0 },
6576 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
},
6577 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
},
6578 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
},
6579 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
},
6580 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
},
6581 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
},
6582 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
}
6585 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6586 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0 },
6587 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0 },
6588 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0 },
6589 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0 },
6590 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0 },
6591 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0 },
6592 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0 },
6593 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0 },
6594 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0 },
6595 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0 },
6596 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0 },
6597 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0 },
6598 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0 },
6599 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0 },
6600 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0 },
6601 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0 },
6602 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0 },
6603 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0 },
6604 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0 },
6605 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0 },
6606 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0 },
6607 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0 },
6608 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0 },
6609 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0 },
6610 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0 },
6611 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
},
6612 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
},
6613 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
},
6614 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
},
6615 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
},
6616 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
},
6617 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
},
6618 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
},
6619 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
}
6623 alpha_init_builtins ()
6625 const struct alpha_builtin_def
*p
;
6629 ftype
= build_function_type (long_integer_type_node
, void_list_node
);
6631 p
= zero_arg_builtins
;
6632 for (i
= 0; i
< ARRAY_SIZE (zero_arg_builtins
); ++i
, ++p
)
6633 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6634 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6637 ftype
= build_function_type_list (long_integer_type_node
,
6638 long_integer_type_node
, NULL_TREE
);
6640 p
= one_arg_builtins
;
6641 for (i
= 0; i
< ARRAY_SIZE (one_arg_builtins
); ++i
, ++p
)
6642 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6643 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6646 ftype
= build_function_type_list (long_integer_type_node
,
6647 long_integer_type_node
,
6648 long_integer_type_node
, NULL_TREE
);
6650 p
= two_arg_builtins
;
6651 for (i
= 0; i
< ARRAY_SIZE (two_arg_builtins
); ++i
, ++p
)
6652 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6653 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6656 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6657 builtin_function ("__builtin_thread_pointer", ftype
,
6658 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
6661 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6662 builtin_function ("__builtin_set_thread_pointer", ftype
,
6663 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
6667 /* Expand an expression EXP that calls a built-in function,
6668 with result going to TARGET if that's convenient
6669 (and in mode MODE if that's convenient).
6670 SUBTARGET may be used as the target for computing one of EXP's operands.
6671 IGNORE is nonzero if the value is to be ignored. */
6674 alpha_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
6677 rtx subtarget ATTRIBUTE_UNUSED
;
6678 enum machine_mode mode ATTRIBUTE_UNUSED
;
6679 int ignore ATTRIBUTE_UNUSED
;
6683 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6684 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6685 tree arglist
= TREE_OPERAND (exp
, 1);
6686 enum insn_code icode
;
6687 rtx op
[MAX_ARGS
], pat
;
6691 if (fcode
>= ALPHA_BUILTIN_max
)
6692 internal_error ("bad builtin fcode");
6693 icode
= code_for_builtin
[fcode
];
6695 internal_error ("bad builtin fcode");
6697 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6699 for (arglist
= TREE_OPERAND (exp
, 1), arity
= 0;
6701 arglist
= TREE_CHAIN (arglist
), arity
++)
6703 const struct insn_operand_data
*insn_op
;
6705 tree arg
= TREE_VALUE (arglist
);
6706 if (arg
== error_mark_node
)
6708 if (arity
> MAX_ARGS
)
6711 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6713 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
6715 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6716 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6721 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6723 || GET_MODE (target
) != tmode
6724 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6725 target
= gen_reg_rtx (tmode
);
6731 pat
= GEN_FCN (icode
) (target
);
6735 pat
= GEN_FCN (icode
) (target
, op
[0]);
6737 pat
= GEN_FCN (icode
) (op
[0]);
6740 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6755 /* This page contains routines that are used to determine what the function
6756 prologue and epilogue code will do and write them out. */
6758 /* Compute the size of the save area in the stack. */
6760 /* These variables are used for communication between the following functions.
6761 They indicate various things about the current function being compiled
6762 that are used to tell what kind of prologue, epilogue and procedure
6763 descriptior to generate. */
6765 /* Nonzero if we need a stack procedure. */
6766 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
6767 static enum alpha_procedure_types alpha_procedure_type
;
6769 /* Register number (either FP or SP) that is used to unwind the frame. */
6770 static int vms_unwind_regno
;
6772 /* Register number used to save FP. We need not have one for RA since
6773 we don't modify it for register procedures. This is only defined
6774 for register frame procedures. */
6775 static int vms_save_fp_regno
;
6777 /* Register number used to reference objects off our PV. */
6778 static int vms_base_regno
;
6780 /* Compute register masks for saved registers. */
6783 alpha_sa_mask (imaskP
, fmaskP
)
6784 unsigned long *imaskP
;
6785 unsigned long *fmaskP
;
6787 unsigned long imask
= 0;
6788 unsigned long fmask
= 0;
6791 /* Irritatingly, there are two kinds of thunks -- those created with
6792 TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go
6793 through the regular part of the compiler. In the
6794 TARGET_ASM_OUTPUT_MI_THUNK case we don't have valid register life
6795 info, but assemble_start_function wants to output .frame and
6796 .mask directives. */
6797 if (current_function_is_thunk
&& !no_new_pseudos
)
6804 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6805 imask
|= (1L << HARD_FRAME_POINTER_REGNUM
);
6807 /* One for every register we have to save. */
6808 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6809 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
6810 && regs_ever_live
[i
] && i
!= REG_RA
6811 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
6816 fmask
|= (1L << (i
- 32));
6819 /* We need to restore these for the handler. */
6820 if (current_function_calls_eh_return
)
6823 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
6824 if (regno
== INVALID_REGNUM
)
6826 imask
|= 1L << regno
;
6829 /* If any register spilled, then spill the return address also. */
6830 /* ??? This is required by the Digital stack unwind specification
6831 and isn't needed if we're doing Dwarf2 unwinding. */
6832 if (imask
|| fmask
|| alpha_ra_ever_killed ())
6833 imask
|= (1L << REG_RA
);
6842 unsigned long mask
[2];
6846 alpha_sa_mask (&mask
[0], &mask
[1]);
6848 if (TARGET_ABI_UNICOSMK
)
6850 if (mask
[0] || mask
[1])
6855 for (j
= 0; j
< 2; ++j
)
6856 for (i
= 0; i
< 32; ++i
)
6857 if ((mask
[j
] >> i
) & 1)
6861 if (TARGET_ABI_UNICOSMK
)
6863 /* We might not need to generate a frame if we don't make any calls
6864 (including calls to __T3E_MISMATCH if this is a vararg function),
6865 don't have any local variables which require stack slots, don't
6866 use alloca and have not determined that we need a frame for other
6869 alpha_procedure_type
6870 = (sa_size
|| get_frame_size() != 0
6871 || current_function_outgoing_args_size
6872 || current_function_stdarg
|| current_function_calls_alloca
6873 || frame_pointer_needed
)
6874 ? PT_STACK
: PT_REGISTER
;
6876 /* Always reserve space for saving callee-saved registers if we
6877 need a frame as required by the calling convention. */
6878 if (alpha_procedure_type
== PT_STACK
)
6881 else if (TARGET_ABI_OPEN_VMS
)
6883 /* Start by assuming we can use a register procedure if we don't
6884 make any calls (REG_RA not used) or need to save any
6885 registers and a stack procedure if we do. */
6886 if ((mask
[0] >> REG_RA
) & 1)
6887 alpha_procedure_type
= PT_STACK
;
6888 else if (get_frame_size() != 0)
6889 alpha_procedure_type
= PT_REGISTER
;
6891 alpha_procedure_type
= PT_NULL
;
6893 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6894 made the final decision on stack procedure vs register procedure. */
6895 if (alpha_procedure_type
== PT_STACK
)
6898 /* Decide whether to refer to objects off our PV via FP or PV.
6899 If we need FP for something else or if we receive a nonlocal
6900 goto (which expects PV to contain the value), we must use PV.
6901 Otherwise, start by assuming we can use FP. */
6904 = (frame_pointer_needed
6905 || current_function_has_nonlocal_label
6906 || alpha_procedure_type
== PT_STACK
6907 || current_function_outgoing_args_size
)
6908 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
6910 /* If we want to copy PV into FP, we need to find some register
6911 in which to save FP. */
6913 vms_save_fp_regno
= -1;
6914 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
6915 for (i
= 0; i
< 32; i
++)
6916 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
6917 vms_save_fp_regno
= i
;
6919 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
6920 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
6921 else if (alpha_procedure_type
== PT_NULL
)
6922 vms_base_regno
= REG_PV
;
6924 /* Stack unwinding should be done via FP unless we use it for PV. */
6925 vms_unwind_regno
= (vms_base_regno
== REG_PV
6926 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
6928 /* If this is a stack procedure, allow space for saving FP and RA. */
6929 if (alpha_procedure_type
== PT_STACK
)
6934 /* Our size must be even (multiple of 16 bytes). */
6943 alpha_pv_save_size ()
6946 return alpha_procedure_type
== PT_STACK
? 8 : 0;
6953 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
6956 #if TARGET_ABI_OPEN_VMS
6958 const struct attribute_spec vms_attribute_table
[] =
6960 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6961 { "overlaid", 0, 0, true, false, false, NULL
},
6962 { "global", 0, 0, true, false, false, NULL
},
6963 { "initialize", 0, 0, true, false, false, NULL
},
6964 { NULL
, 0, 0, false, false, false, NULL
}
6970 find_lo_sum (px
, data
)
6972 void *data ATTRIBUTE_UNUSED
;
6974 return GET_CODE (*px
) == LO_SUM
;
6978 alpha_does_function_need_gp ()
6982 /* The GP being variable is an OSF abi thing. */
6983 if (! TARGET_ABI_OSF
)
6986 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6989 if (current_function_is_thunk
)
6992 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6993 Even if we are a static function, we still need to do this in case
6994 our address is taken and passed to something like qsort. */
6996 push_topmost_sequence ();
6997 insn
= get_insns ();
6998 pop_topmost_sequence ();
7000 for (; insn
; insn
= NEXT_INSN (insn
))
7002 && GET_CODE (PATTERN (insn
)) != USE
7003 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
7005 enum attr_type type
= get_attr_type (insn
);
7006 if (type
== TYPE_LDSYM
|| type
== TYPE_JSR
)
7008 if (TARGET_EXPLICIT_RELOCS
7009 && for_each_rtx (&PATTERN (insn
), find_lo_sum
, NULL
) > 0)
7016 /* Write a version stamp. Don't write anything if we are running as a
7017 cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
7024 alpha_write_verstamp (file
)
7025 FILE *file ATTRIBUTE_UNUSED
;
7028 fprintf (file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
7032 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7036 set_frame_related_p ()
7038 rtx seq
= get_insns ();
7049 while (insn
!= NULL_RTX
)
7051 RTX_FRAME_RELATED_P (insn
) = 1;
7052 insn
= NEXT_INSN (insn
);
7054 seq
= emit_insn (seq
);
7058 seq
= emit_insn (seq
);
7059 RTX_FRAME_RELATED_P (seq
) = 1;
7064 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7066 /* Write function prologue. */
7068 /* On vms we have two kinds of functions:
7070 - stack frame (PROC_STACK)
7071 these are 'normal' functions with local vars and which are
7072 calling other functions
7073 - register frame (PROC_REGISTER)
7074 keeps all data in registers, needs no stack
7076 We must pass this to the assembler so it can generate the
7077 proper pdsc (procedure descriptor)
7078 This is done with the '.pdesc' command.
7080 On not-vms, we don't really differentiate between the two, as we can
7081 simply allocate stack without saving registers. */
7084 alpha_expand_prologue ()
7086 /* Registers to save. */
7087 unsigned long imask
= 0;
7088 unsigned long fmask
= 0;
7089 /* Stack space needed for pushing registers clobbered by us. */
7090 HOST_WIDE_INT sa_size
;
7091 /* Complete stack size needed. */
7092 HOST_WIDE_INT frame_size
;
7093 /* Offset from base reg to register save area. */
7094 HOST_WIDE_INT reg_offset
;
7098 sa_size
= alpha_sa_size ();
7100 frame_size
= get_frame_size ();
7101 if (TARGET_ABI_OPEN_VMS
)
7102 frame_size
= ALPHA_ROUND (sa_size
7103 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7105 + current_function_pretend_args_size
);
7106 else if (TARGET_ABI_UNICOSMK
)
7107 /* We have to allocate space for the DSIB if we generate a frame. */
7108 frame_size
= ALPHA_ROUND (sa_size
7109 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7110 + ALPHA_ROUND (frame_size
7111 + current_function_outgoing_args_size
);
7113 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7115 + ALPHA_ROUND (frame_size
7116 + current_function_pretend_args_size
));
7118 if (TARGET_ABI_OPEN_VMS
)
7121 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7123 alpha_sa_mask (&imask
, &fmask
);
7125 /* Emit an insn to reload GP, if needed. */
7128 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7129 if (alpha_function_needs_gp
)
7130 emit_insn (gen_prologue_ldgp ());
7133 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7134 the call to mcount ourselves, rather than having the linker do it
7135 magically in response to -pg. Since _mcount has special linkage,
7136 don't represent the call as a call. */
7137 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7138 emit_insn (gen_prologue_mcount ());
7140 if (TARGET_ABI_UNICOSMK
)
7141 unicosmk_gen_dsib (&imask
);
7143 /* Adjust the stack by the frame size. If the frame size is > 4096
7144 bytes, we need to be sure we probe somewhere in the first and last
7145 4096 bytes (we can probably get away without the latter test) and
7146 every 8192 bytes in between. If the frame size is > 32768, we
7147 do this in a loop. Otherwise, we generate the explicit probe
7150 Note that we are only allowed to adjust sp once in the prologue. */
7152 if (frame_size
<= 32768)
7154 if (frame_size
> 4096)
7159 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7162 while ((probed
+= 8192) < frame_size
);
7164 /* We only have to do this probe if we aren't saving registers. */
7165 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
7166 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
7169 if (frame_size
!= 0)
7170 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7171 GEN_INT (TARGET_ABI_UNICOSMK
7177 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7178 number of 8192 byte blocks to probe. We then probe each block
7179 in the loop and then set SP to the proper location. If the
7180 amount remaining is > 4096, we have to do one more probe if we
7181 are not saving any registers. */
7183 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
7184 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
7185 rtx ptr
= gen_rtx_REG (DImode
, 22);
7186 rtx count
= gen_rtx_REG (DImode
, 23);
7189 emit_move_insn (count
, GEN_INT (blocks
));
7190 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7191 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7193 /* Because of the difficulty in emitting a new basic block this
7194 late in the compilation, generate the loop as a single insn. */
7195 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7197 if (leftover
> 4096 && sa_size
== 0)
7199 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7200 MEM_VOLATILE_P (last
) = 1;
7201 emit_move_insn (last
, const0_rtx
);
7204 if (TARGET_ABI_WINDOWS_NT
)
7206 /* For NT stack unwind (done by 'reverse execution'), it's
7207 not OK to take the result of a loop, even though the value
7208 is already in ptr, so we reload it via a single operation
7209 and subtract it to sp.
7211 Yes, that's correct -- we have to reload the whole constant
7212 into a temporary via ldah+lda then subtract from sp. To
7213 ensure we get ldah+lda, we use a special pattern. */
7215 HOST_WIDE_INT lo
, hi
;
7216 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7217 hi
= frame_size
- lo
;
7219 emit_move_insn (ptr
, GEN_INT (hi
));
7220 emit_insn (gen_nt_lda (ptr
, GEN_INT (lo
)));
7221 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7226 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7227 GEN_INT (-leftover
)));
7230 /* This alternative is special, because the DWARF code cannot
7231 possibly intuit through the loop above. So we invent this
7232 note it looks at instead. */
7233 RTX_FRAME_RELATED_P (seq
) = 1;
7235 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7236 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7237 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7238 GEN_INT (TARGET_ABI_UNICOSMK
7244 if (!TARGET_ABI_UNICOSMK
)
7246 /* Cope with very large offsets to the register save area. */
7247 sa_reg
= stack_pointer_rtx
;
7248 if (reg_offset
+ sa_size
> 0x8000)
7250 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7253 if (low
+ sa_size
<= 0x8000)
7254 bias
= reg_offset
- low
, reg_offset
= low
;
7256 bias
= reg_offset
, reg_offset
= 0;
7258 sa_reg
= gen_rtx_REG (DImode
, 24);
7259 FRP (emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
,
7263 /* Save regs in stack order. Beginning with VMS PV. */
7264 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7266 mem
= gen_rtx_MEM (DImode
, stack_pointer_rtx
);
7267 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7268 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_PV
)));
7271 /* Save register RA next. */
7272 if (imask
& (1L << REG_RA
))
7274 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7275 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7276 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
7277 imask
&= ~(1L << REG_RA
);
7281 /* Now save any other registers required to be saved. */
7282 for (i
= 0; i
< 32; i
++)
7283 if (imask
& (1L << i
))
7285 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7286 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7287 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7291 for (i
= 0; i
< 32; i
++)
7292 if (fmask
& (1L << i
))
7294 mem
= gen_rtx_MEM (DFmode
, plus_constant (sa_reg
, reg_offset
));
7295 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7296 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7300 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7302 /* The standard frame on the T3E includes space for saving registers.
7303 We just have to use it. We don't have to save the return address and
7304 the old frame pointer here - they are saved in the DSIB. */
7307 for (i
= 9; i
< 15; i
++)
7308 if (imask
& (1L << i
))
7310 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7312 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7313 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7316 for (i
= 2; i
< 10; i
++)
7317 if (fmask
& (1L << i
))
7319 mem
= gen_rtx_MEM (DFmode
, plus_constant (hard_frame_pointer_rtx
,
7321 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7322 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7327 if (TARGET_ABI_OPEN_VMS
)
7329 if (alpha_procedure_type
== PT_REGISTER
)
7330 /* Register frame procedures save the fp.
7331 ?? Ought to have a dwarf2 save for this. */
7332 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7333 hard_frame_pointer_rtx
);
7335 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7336 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7337 gen_rtx_REG (DImode
, REG_PV
)));
7339 if (alpha_procedure_type
!= PT_NULL
7340 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7341 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7343 /* If we have to allocate space for outgoing args, do it now. */
7344 if (current_function_outgoing_args_size
!= 0)
7347 plus_constant (hard_frame_pointer_rtx
,
7349 (current_function_outgoing_args_size
)))));
7351 else if (!TARGET_ABI_UNICOSMK
)
7353 /* If we need a frame pointer, set it from the stack pointer. */
7354 if (frame_pointer_needed
)
7356 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7357 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7359 /* This must always be the last instruction in the
7360 prologue, thus we emit a special move + clobber. */
7361 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7362 stack_pointer_rtx
, sa_reg
)));
7366 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7367 the prologue, for exception handling reasons, we cannot do this for
7368 any insn that might fault. We could prevent this for mems with a
7369 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7370 have to prevent all such scheduling with a blockage.
7372 Linux, on the other hand, never bothered to implement OSF/1's
7373 exception handling, and so doesn't care about such things. Anyone
7374 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7376 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7377 emit_insn (gen_blockage ());
7380 /* Output the textual info surrounding the prologue. */
7383 alpha_start_function (file
, fnname
, decl
)
7386 tree decl ATTRIBUTE_UNUSED
;
7388 unsigned long imask
= 0;
7389 unsigned long fmask
= 0;
7390 /* Stack space needed for pushing registers clobbered by us. */
7391 HOST_WIDE_INT sa_size
;
7392 /* Complete stack size needed. */
7393 HOST_WIDE_INT frame_size
;
7394 /* Offset from base reg to register save area. */
7395 HOST_WIDE_INT reg_offset
;
7396 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7399 /* Don't emit an extern directive for functions defined in the same file. */
7400 if (TARGET_ABI_UNICOSMK
)
7403 name_tree
= get_identifier (fnname
);
7404 TREE_ASM_WRITTEN (name_tree
) = 1;
7407 alpha_fnname
= fnname
;
7408 sa_size
= alpha_sa_size ();
7410 frame_size
= get_frame_size ();
7411 if (TARGET_ABI_OPEN_VMS
)
7412 frame_size
= ALPHA_ROUND (sa_size
7413 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7415 + current_function_pretend_args_size
);
7416 else if (TARGET_ABI_UNICOSMK
)
7417 frame_size
= ALPHA_ROUND (sa_size
7418 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7419 + ALPHA_ROUND (frame_size
7420 + current_function_outgoing_args_size
);
7422 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7424 + ALPHA_ROUND (frame_size
7425 + current_function_pretend_args_size
));
7427 if (TARGET_ABI_OPEN_VMS
)
7430 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7432 alpha_sa_mask (&imask
, &fmask
);
7434 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7435 We have to do that before the .ent directive as we cannot switch
7436 files within procedures with native ecoff because line numbers are
7437 linked to procedure descriptors.
7438 Outputting the lineno helps debugging of one line functions as they
7439 would otherwise get no line number at all. Please note that we would
7440 like to put out last_linenum from final.c, but it is not accessible. */
7442 if (write_symbols
== SDB_DEBUG
)
7444 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7445 ASM_OUTPUT_SOURCE_FILENAME (file
,
7446 DECL_SOURCE_FILE (current_function_decl
));
7448 #ifdef ASM_OUTPUT_SOURCE_LINE
7449 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7450 ASM_OUTPUT_SOURCE_LINE (file
,
7451 DECL_SOURCE_LINE (current_function_decl
));
7455 /* Issue function start and label. */
7456 if (TARGET_ABI_OPEN_VMS
7457 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
7459 fputs ("\t.ent ", file
);
7460 assemble_name (file
, fnname
);
7463 /* If the function needs GP, we'll write the "..ng" label there.
7464 Otherwise, do it here. */
7466 && ! alpha_function_needs_gp
7467 && ! current_function_is_thunk
)
7470 assemble_name (file
, fnname
);
7471 fputs ("..ng:\n", file
);
7475 strcpy (entry_label
, fnname
);
7476 if (TARGET_ABI_OPEN_VMS
)
7477 strcat (entry_label
, "..en");
7479 /* For public functions, the label must be globalized by appending an
7480 additional colon. */
7481 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
7482 strcat (entry_label
, ":");
7484 ASM_OUTPUT_LABEL (file
, entry_label
);
7485 inside_function
= TRUE
;
7487 if (TARGET_ABI_OPEN_VMS
)
7488 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7490 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7491 && !flag_inhibit_size_directive
)
7493 /* Set flags in procedure descriptor to request IEEE-conformant
7494 math-library routines. The value we set it to is PDSC_EXC_IEEE
7495 (/usr/include/pdsc.h). */
7496 fputs ("\t.eflag 48\n", file
);
7499 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7500 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
7501 alpha_arg_offset
= -frame_size
+ 48;
7503 /* Describe our frame. If the frame size is larger than an integer,
7504 print it as zero to avoid an assembler error. We won't be
7505 properly describing such a frame, but that's the best we can do. */
7506 if (TARGET_ABI_UNICOSMK
)
7508 else if (TARGET_ABI_OPEN_VMS
)
7510 fprintf (file
, "\t.frame $%d,", vms_unwind_regno
);
7511 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7512 frame_size
>= ((HOST_WIDE_INT
) 1 << 31) ? 0 : frame_size
);
7513 fputs (",$26,", file
);
7514 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, reg_offset
);
7517 else if (!flag_inhibit_size_directive
)
7519 fprintf (file
, "\t.frame $%d,",
7520 (frame_pointer_needed
7521 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
));
7522 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7523 frame_size
>= (1l << 31) ? 0 : frame_size
);
7524 fprintf (file
, ",$26,%d\n", current_function_pretend_args_size
);
7527 /* Describe which registers were spilled. */
7528 if (TARGET_ABI_UNICOSMK
)
7530 else if (TARGET_ABI_OPEN_VMS
)
7533 /* ??? Does VMS care if mask contains ra? The old code didn't
7534 set it, so I don't here. */
7535 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1L << REG_RA
));
7537 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7538 if (alpha_procedure_type
== PT_REGISTER
)
7539 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7541 else if (!flag_inhibit_size_directive
)
7545 fprintf (file
, "\t.mask 0x%lx,", imask
);
7546 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7547 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
7550 for (i
= 0; i
< 32; ++i
)
7551 if (imask
& (1L << i
))
7557 fprintf (file
, "\t.fmask 0x%lx,", fmask
);
7558 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7559 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
7564 #if TARGET_ABI_OPEN_VMS
7565 /* Ifdef'ed cause link_section are only available then. */
7566 readonly_data_section ();
7567 fprintf (file
, "\t.align 3\n");
7568 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
7569 fputs ("\t.ascii \"", file
);
7570 assemble_name (file
, fnname
);
7571 fputs ("\\0\"\n", file
);
7572 alpha_need_linkage (fnname
, 1);
7577 /* Emit the .prologue note at the scheduled end of the prologue. */
7580 alpha_output_function_end_prologue (file
)
7583 if (TARGET_ABI_UNICOSMK
)
7585 else if (TARGET_ABI_OPEN_VMS
)
7586 fputs ("\t.prologue\n", file
);
7587 else if (TARGET_ABI_WINDOWS_NT
)
7588 fputs ("\t.prologue 0\n", file
);
7589 else if (!flag_inhibit_size_directive
)
7590 fprintf (file
, "\t.prologue %d\n",
7591 alpha_function_needs_gp
|| current_function_is_thunk
);
7594 /* Write function epilogue. */
7596 /* ??? At some point we will want to support full unwind, and so will
7597 need to mark the epilogue as well. At the moment, we just confuse
7600 #define FRP(exp) exp
7603 alpha_expand_epilogue ()
7605 /* Registers to save. */
7606 unsigned long imask
= 0;
7607 unsigned long fmask
= 0;
7608 /* Stack space needed for pushing registers clobbered by us. */
7609 HOST_WIDE_INT sa_size
;
7610 /* Complete stack size needed. */
7611 HOST_WIDE_INT frame_size
;
7612 /* Offset from base reg to register save area. */
7613 HOST_WIDE_INT reg_offset
;
7614 int fp_is_frame_pointer
, fp_offset
;
7615 rtx sa_reg
, sa_reg_exp
= NULL
;
7616 rtx sp_adj1
, sp_adj2
, mem
;
7620 sa_size
= alpha_sa_size ();
7622 frame_size
= get_frame_size ();
7623 if (TARGET_ABI_OPEN_VMS
)
7624 frame_size
= ALPHA_ROUND (sa_size
7625 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7627 + current_function_pretend_args_size
);
7628 else if (TARGET_ABI_UNICOSMK
)
7629 frame_size
= ALPHA_ROUND (sa_size
7630 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7631 + ALPHA_ROUND (frame_size
7632 + current_function_outgoing_args_size
);
7634 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7636 + ALPHA_ROUND (frame_size
7637 + current_function_pretend_args_size
));
7639 if (TARGET_ABI_OPEN_VMS
)
7641 if (alpha_procedure_type
== PT_STACK
)
7647 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7649 alpha_sa_mask (&imask
, &fmask
);
7652 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7653 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
7655 sa_reg
= stack_pointer_rtx
;
7657 if (current_function_calls_eh_return
)
7658 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7662 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
7664 /* If we have a frame pointer, restore SP from it. */
7665 if ((TARGET_ABI_OPEN_VMS
7666 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7667 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
7668 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7670 /* Cope with very large offsets to the register save area. */
7671 if (reg_offset
+ sa_size
> 0x8000)
7673 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7676 if (low
+ sa_size
<= 0x8000)
7677 bias
= reg_offset
- low
, reg_offset
= low
;
7679 bias
= reg_offset
, reg_offset
= 0;
7681 sa_reg
= gen_rtx_REG (DImode
, 22);
7682 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
7684 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
7687 /* Restore registers in order, excepting a true frame pointer. */
7689 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7691 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7692 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7695 imask
&= ~(1L << REG_RA
);
7697 for (i
= 0; i
< 32; ++i
)
7698 if (imask
& (1L << i
))
7700 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
7701 fp_offset
= reg_offset
;
7704 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
7705 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7706 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7711 for (i
= 0; i
< 32; ++i
)
7712 if (fmask
& (1L << i
))
7714 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
7715 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7716 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7720 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7722 /* Restore callee-saved general-purpose registers. */
7726 for (i
= 9; i
< 15; i
++)
7727 if (imask
& (1L << i
))
7729 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7731 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7732 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7736 for (i
= 2; i
< 10; i
++)
7737 if (fmask
& (1L << i
))
7739 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
7741 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7742 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7746 /* Restore the return address from the DSIB. */
7748 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
7749 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7750 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7753 if (frame_size
|| eh_ofs
)
7755 sp_adj1
= stack_pointer_rtx
;
7759 sp_adj1
= gen_rtx_REG (DImode
, 23);
7760 emit_move_insn (sp_adj1
,
7761 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
7764 /* If the stack size is large, begin computation into a temporary
7765 register so as not to interfere with a potential fp restore,
7766 which must be consecutive with an SP restore. */
7767 if (frame_size
< 32768
7768 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
7769 sp_adj2
= GEN_INT (frame_size
);
7770 else if (TARGET_ABI_UNICOSMK
)
7772 sp_adj1
= gen_rtx_REG (DImode
, 23);
7773 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
7774 sp_adj2
= const0_rtx
;
7776 else if (frame_size
< 0x40007fffL
)
7778 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7780 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
7781 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
7785 sp_adj1
= gen_rtx_REG (DImode
, 23);
7786 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
7788 sp_adj2
= GEN_INT (low
);
7792 rtx tmp
= gen_rtx_REG (DImode
, 23);
7793 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
7796 /* We can't drop new things to memory this late, afaik,
7797 so build it up by pieces. */
7798 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
7799 -(frame_size
< 0)));
7805 /* From now on, things must be in order. So emit blockages. */
7807 /* Restore the frame pointer. */
7808 if (TARGET_ABI_UNICOSMK
)
7810 emit_insn (gen_blockage ());
7811 mem
= gen_rtx_MEM (DImode
,
7812 plus_constant (hard_frame_pointer_rtx
, -16));
7813 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7814 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7816 else if (fp_is_frame_pointer
)
7818 emit_insn (gen_blockage ());
7819 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
7820 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7821 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7823 else if (TARGET_ABI_OPEN_VMS
)
7825 emit_insn (gen_blockage ());
7826 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7827 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7830 /* Restore the stack pointer. */
7831 emit_insn (gen_blockage ());
7832 if (sp_adj2
== const0_rtx
)
7833 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
7835 FRP (emit_move_insn (stack_pointer_rtx
,
7836 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
7840 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
7842 emit_insn (gen_blockage ());
7843 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7844 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7846 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
7848 /* Decrement the frame pointer if the function does not have a
7851 emit_insn (gen_blockage ());
7852 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7853 hard_frame_pointer_rtx
, GEN_INT (-1))));
7858 #if TARGET_ABI_OPEN_VMS
7859 #include <splay-tree.h>
7861 /* Structure to collect function names for final output
7864 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
7865 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
7877 enum links_kind lkind
;
7878 enum reloc_kind rkind
;
7881 static splay_tree alpha_funcs_tree
;
7882 static splay_tree alpha_links_tree
;
7884 static int mark_alpha_links_node
PARAMS ((splay_tree_node
, void *));
7885 static void mark_alpha_links
PARAMS ((void *));
7886 static int alpha_write_one_linkage
PARAMS ((splay_tree_node
, void *));
7888 static int alpha_funcs_num
;
7891 /* Output the rest of the textual info surrounding the epilogue. */
7894 alpha_end_function (file
, fnname
, decl
)
7899 /* End the function. */
7900 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
7902 fputs ("\t.end ", file
);
7903 assemble_name (file
, fnname
);
7906 inside_function
= FALSE
;
7908 #if TARGET_ABI_OPEN_VMS
7909 alpha_write_linkage (file
, fnname
, decl
);
7912 /* Show that we know this function if it is called again.
7913 This is only meaningful for symbols that bind locally. */
7914 if ((*targetm
.binds_local_p
) (decl
))
7916 rtx symbol
= XEXP (DECL_RTL (decl
), 0);
7918 /* Mark whether the decl is "near". See the commentary in
7919 alpha_encode_section_info wrt the .text section. */
7920 if (decl_in_text_section (decl
))
7923 /* Mark whether the decl shares a GP with other functions
7924 in this unit of translation. This is trivially true of
7926 SYMBOL_REF_FLAG (symbol
) = 1;
7929 /* Output jump tables and the static subroutine information block. */
7930 if (TARGET_ABI_UNICOSMK
)
7932 unicosmk_output_ssib (file
, fnname
);
7933 unicosmk_output_deferred_case_vectors (file
);
7938 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7940 In order to avoid the hordes of differences between generated code
7941 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7942 lots of code loading up large constants, generate rtl and emit it
7943 instead of going straight to text.
7945 Not sure why this idea hasn't been explored before... */
7948 alpha_output_mi_thunk_osf (file
, thunk_fndecl
, delta
, vcall_offset
, function
)
7950 tree thunk_fndecl ATTRIBUTE_UNUSED
;
7951 HOST_WIDE_INT delta
;
7952 HOST_WIDE_INT vcall_offset
;
7955 HOST_WIDE_INT hi
, lo
;
7956 rtx
this, insn
, funexp
;
7958 /* We always require a valid GP. */
7959 emit_insn (gen_prologue_ldgp ());
7960 emit_note (NULL
, NOTE_INSN_PROLOGUE_END
);
7962 /* Find the "this" pointer. If the function returns a structure,
7963 the structure return pointer is in $16. */
7964 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
))))
7965 this = gen_rtx_REG (Pmode
, 17);
7967 this = gen_rtx_REG (Pmode
, 16);
7969 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7970 entire constant for the add. */
7971 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
7972 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7973 if (hi
+ lo
== delta
)
7976 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
7978 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
7982 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
7983 delta
, -(delta
< 0));
7984 emit_insn (gen_adddi3 (this, this, tmp
));
7987 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7992 tmp
= gen_rtx_REG (Pmode
, 0);
7993 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
7995 lo
= ((vcall_offset
& 0xffff) ^ 0x8000) - 0x8000;
7996 hi
= (((vcall_offset
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7997 if (hi
+ lo
== vcall_offset
)
8000 emit_insn (gen_adddi3 (tmp
, tmp
, GEN_INT (hi
)));
8004 tmp2
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 1),
8005 vcall_offset
, -(vcall_offset
< 0));
8006 emit_insn (gen_adddi3 (tmp
, tmp
, tmp2
));
8010 tmp2
= gen_rtx_PLUS (Pmode
, tmp
, GEN_INT (lo
));
8013 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp2
));
8015 emit_insn (gen_adddi3 (this, this, tmp
));
8018 /* Generate a tail call to the target function. */
8019 if (! TREE_USED (function
))
8021 assemble_external (function
);
8022 TREE_USED (function
) = 1;
8024 funexp
= XEXP (DECL_RTL (function
), 0);
8025 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8026 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
8027 SIBLING_CALL_P (insn
) = 1;
8029 /* Run just enough of rest_of_compilation to get the insns emitted.
8030 There's not really enough bulk here to make other passes such as
8031 instruction scheduling worth while. Note that use_thunk calls
8032 assemble_start_function and assemble_end_function. */
8033 insn
= get_insns ();
8034 shorten_branches (insn
);
8035 final_start_function (insn
, file
, 1);
8036 final (insn
, file
, 1, 0);
8037 final_end_function ();
8039 #endif /* TARGET_ABI_OSF */
8041 /* Debugging support. */
8045 /* Count the number of sdb related labels are generated (to find block
8046 start and end boundaries). */
8048 int sdb_label_count
= 0;
8050 /* Next label # for each statement. */
8052 static int sym_lineno
= 0;
8054 /* Count the number of .file directives, so that .loc is up to date. */
8056 static int num_source_filenames
= 0;
8058 /* Name of the file containing the current function. */
8060 static const char *current_function_file
= "";
8062 /* Offsets to alpha virtual arg/local debugging pointers. */
8064 long alpha_arg_offset
;
8065 long alpha_auto_offset
;
8067 /* Emit a new filename to a stream. */
8070 alpha_output_filename (stream
, name
)
8074 static int first_time
= TRUE
;
8075 char ltext_label_name
[100];
8080 ++num_source_filenames
;
8081 current_function_file
= name
;
8082 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8083 output_quoted_string (stream
, name
);
8084 fprintf (stream
, "\n");
8085 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
8086 fprintf (stream
, "\t#@stabs\n");
8089 else if (write_symbols
== DBX_DEBUG
)
8091 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
8092 fprintf (stream
, "%s", ASM_STABS_OP
);
8093 output_quoted_string (stream
, name
);
8094 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
8097 else if (name
!= current_function_file
8098 && strcmp (name
, current_function_file
) != 0)
8100 if (inside_function
&& ! TARGET_GAS
)
8101 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
8104 ++num_source_filenames
;
8105 current_function_file
= name
;
8106 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8109 output_quoted_string (stream
, name
);
8110 fprintf (stream
, "\n");
8114 /* Emit a linenumber to a stream. */
8117 alpha_output_lineno (stream
, line
)
8121 if (write_symbols
== DBX_DEBUG
)
8123 /* mips-tfile doesn't understand .stabd directives. */
8125 fprintf (stream
, "$LM%d:\n%s%d,0,%d,$LM%d\n",
8126 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
8129 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
8132 /* Structure to show the current status of registers and memory. */
8134 struct shadow_summary
8137 unsigned int i
: 31; /* Mask of int regs */
8138 unsigned int fp
: 31; /* Mask of fp regs */
8139 unsigned int mem
: 1; /* mem == imem | fpmem */
8143 static void summarize_insn
PARAMS ((rtx
, struct shadow_summary
*, int));
8144 static void alpha_handle_trap_shadows
PARAMS ((rtx
));
8146 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8147 to the summary structure. SET is nonzero if the insn is setting the
8148 object, otherwise zero. */
8151 summarize_insn (x
, sum
, set
)
8153 struct shadow_summary
*sum
;
8156 const char *format_ptr
;
8162 switch (GET_CODE (x
))
8164 /* ??? Note that this case would be incorrect if the Alpha had a
8165 ZERO_EXTRACT in SET_DEST. */
8167 summarize_insn (SET_SRC (x
), sum
, 0);
8168 summarize_insn (SET_DEST (x
), sum
, 1);
8172 summarize_insn (XEXP (x
, 0), sum
, 1);
8176 summarize_insn (XEXP (x
, 0), sum
, 0);
8180 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8181 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8185 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8186 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8190 summarize_insn (SUBREG_REG (x
), sum
, 0);
8195 int regno
= REGNO (x
);
8196 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8198 if (regno
== 31 || regno
== 63)
8204 sum
->defd
.i
|= mask
;
8206 sum
->defd
.fp
|= mask
;
8211 sum
->used
.i
|= mask
;
8213 sum
->used
.fp
|= mask
;
8224 /* Find the regs used in memory address computation: */
8225 summarize_insn (XEXP (x
, 0), sum
, 0);
8228 case CONST_INT
: case CONST_DOUBLE
:
8229 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8230 case SCRATCH
: case ASM_INPUT
:
8233 /* Handle common unary and binary ops for efficiency. */
8234 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8235 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8236 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8237 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8238 case NE
: case EQ
: case GE
: case GT
: case LE
:
8239 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8240 summarize_insn (XEXP (x
, 0), sum
, 0);
8241 summarize_insn (XEXP (x
, 1), sum
, 0);
8244 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8245 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8246 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8247 case SQRT
: case FFS
:
8248 summarize_insn (XEXP (x
, 0), sum
, 0);
8252 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8253 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8254 switch (format_ptr
[i
])
8257 summarize_insn (XEXP (x
, i
), sum
, 0);
8261 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8262 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8274 /* Ensure a sufficient number of `trapb' insns are in the code when
8275 the user requests code with a trap precision of functions or
8278 In naive mode, when the user requests a trap-precision of
8279 "instruction", a trapb is needed after every instruction that may
8280 generate a trap. This ensures that the code is resumption safe but
8283 When optimizations are turned on, we delay issuing a trapb as long
8284 as possible. In this context, a trap shadow is the sequence of
8285 instructions that starts with a (potentially) trap generating
8286 instruction and extends to the next trapb or call_pal instruction
8287 (but GCC never generates call_pal by itself). We can delay (and
8288 therefore sometimes omit) a trapb subject to the following
8291 (a) On entry to the trap shadow, if any Alpha register or memory
8292 location contains a value that is used as an operand value by some
8293 instruction in the trap shadow (live on entry), then no instruction
8294 in the trap shadow may modify the register or memory location.
8296 (b) Within the trap shadow, the computation of the base register
8297 for a memory load or store instruction may not involve using the
8298 result of an instruction that might generate an UNPREDICTABLE
8301 (c) Within the trap shadow, no register may be used more than once
8302 as a destination register. (This is to make life easier for the
8305 (d) The trap shadow may not include any branch instructions. */
8308 alpha_handle_trap_shadows (insns
)
8311 struct shadow_summary shadow
;
8312 int trap_pending
, exception_nesting
;
8316 exception_nesting
= 0;
8319 shadow
.used
.mem
= 0;
8320 shadow
.defd
= shadow
.used
;
8322 for (i
= insns
; i
; i
= NEXT_INSN (i
))
8324 if (GET_CODE (i
) == NOTE
)
8326 switch (NOTE_LINE_NUMBER (i
))
8328 case NOTE_INSN_EH_REGION_BEG
:
8329 exception_nesting
++;
8334 case NOTE_INSN_EH_REGION_END
:
8335 exception_nesting
--;
8340 case NOTE_INSN_EPILOGUE_BEG
:
8341 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8346 else if (trap_pending
)
8348 if (alpha_tp
== ALPHA_TP_FUNC
)
8350 if (GET_CODE (i
) == JUMP_INSN
8351 && GET_CODE (PATTERN (i
)) == RETURN
)
8354 else if (alpha_tp
== ALPHA_TP_INSN
)
8358 struct shadow_summary sum
;
8363 sum
.defd
= sum
.used
;
8365 switch (GET_CODE (i
))
8368 /* Annoyingly, get_attr_trap will abort on these. */
8369 if (GET_CODE (PATTERN (i
)) == USE
8370 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8373 summarize_insn (PATTERN (i
), &sum
, 0);
8375 if ((sum
.defd
.i
& shadow
.defd
.i
)
8376 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8378 /* (c) would be violated */
8382 /* Combine shadow with summary of current insn: */
8383 shadow
.used
.i
|= sum
.used
.i
;
8384 shadow
.used
.fp
|= sum
.used
.fp
;
8385 shadow
.used
.mem
|= sum
.used
.mem
;
8386 shadow
.defd
.i
|= sum
.defd
.i
;
8387 shadow
.defd
.fp
|= sum
.defd
.fp
;
8388 shadow
.defd
.mem
|= sum
.defd
.mem
;
8390 if ((sum
.defd
.i
& shadow
.used
.i
)
8391 || (sum
.defd
.fp
& shadow
.used
.fp
)
8392 || (sum
.defd
.mem
& shadow
.used
.mem
))
8394 /* (a) would be violated (also takes care of (b)) */
8395 if (get_attr_trap (i
) == TRAP_YES
8396 && ((sum
.defd
.i
& sum
.used
.i
)
8397 || (sum
.defd
.fp
& sum
.used
.fp
)))
8416 n
= emit_insn_before (gen_trapb (), i
);
8417 PUT_MODE (n
, TImode
);
8418 PUT_MODE (i
, TImode
);
8422 shadow
.used
.mem
= 0;
8423 shadow
.defd
= shadow
.used
;
8428 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8429 && GET_CODE (i
) == INSN
8430 && GET_CODE (PATTERN (i
)) != USE
8431 && GET_CODE (PATTERN (i
)) != CLOBBER
8432 && get_attr_trap (i
) == TRAP_YES
)
8434 if (optimize
&& !trap_pending
)
8435 summarize_insn (PATTERN (i
), &shadow
, 0);
8441 /* Alpha can only issue instruction groups simultaneously if they are
8442 suitibly aligned. This is very processor-specific. */
8444 enum alphaev4_pipe
{
8451 enum alphaev5_pipe
{
8462 static enum alphaev4_pipe alphaev4_insn_pipe
PARAMS ((rtx
));
8463 static enum alphaev5_pipe alphaev5_insn_pipe
PARAMS ((rtx
));
8464 static rtx alphaev4_next_group
PARAMS ((rtx
, int *, int *));
8465 static rtx alphaev5_next_group
PARAMS ((rtx
, int *, int *));
8466 static rtx alphaev4_next_nop
PARAMS ((int *));
8467 static rtx alphaev5_next_nop
PARAMS ((int *));
8469 static void alpha_align_insns
8470 PARAMS ((rtx
, unsigned int, rtx (*)(rtx
, int *, int *), rtx (*)(int *)));
8472 static enum alphaev4_pipe
8473 alphaev4_insn_pipe (insn
)
8476 if (recog_memoized (insn
) < 0)
8478 if (get_attr_length (insn
) != 4)
8481 switch (get_attr_type (insn
))
8515 static enum alphaev5_pipe
8516 alphaev5_insn_pipe (insn
)
8519 if (recog_memoized (insn
) < 0)
8521 if (get_attr_length (insn
) != 4)
8524 switch (get_attr_type (insn
))
8565 /* IN_USE is a mask of the slots currently filled within the insn group.
8566 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8567 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8569 LEN is, of course, the length of the group in bytes. */
8572 alphaev4_next_group (insn
, pin_use
, plen
)
8574 int *pin_use
, *plen
;
8581 || GET_CODE (PATTERN (insn
)) == CLOBBER
8582 || GET_CODE (PATTERN (insn
)) == USE
)
8587 enum alphaev4_pipe pipe
;
8589 pipe
= alphaev4_insn_pipe (insn
);
8593 /* Force complex instructions to start new groups. */
8597 /* If this is a completely unrecognized insn, its an asm.
8598 We don't know how long it is, so record length as -1 to
8599 signal a needed realignment. */
8600 if (recog_memoized (insn
) < 0)
8603 len
= get_attr_length (insn
);
8607 if (in_use
& EV4_IB0
)
8609 if (in_use
& EV4_IB1
)
8614 in_use
|= EV4_IB0
| EV4_IBX
;
8618 if (in_use
& EV4_IB0
)
8620 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8628 if (in_use
& EV4_IB1
)
8638 /* Haifa doesn't do well scheduling branches. */
8639 if (GET_CODE (insn
) == JUMP_INSN
)
8643 insn
= next_nonnote_insn (insn
);
8645 if (!insn
|| ! INSN_P (insn
))
8648 /* Let Haifa tell us where it thinks insn group boundaries are. */
8649 if (GET_MODE (insn
) == TImode
)
8652 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8657 insn
= next_nonnote_insn (insn
);
8665 /* IN_USE is a mask of the slots currently filled within the insn group.
8666 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8667 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8669 LEN is, of course, the length of the group in bytes. */
8672 alphaev5_next_group (insn
, pin_use
, plen
)
8674 int *pin_use
, *plen
;
8681 || GET_CODE (PATTERN (insn
)) == CLOBBER
8682 || GET_CODE (PATTERN (insn
)) == USE
)
8687 enum alphaev5_pipe pipe
;
8689 pipe
= alphaev5_insn_pipe (insn
);
8693 /* Force complex instructions to start new groups. */
8697 /* If this is a completely unrecognized insn, its an asm.
8698 We don't know how long it is, so record length as -1 to
8699 signal a needed realignment. */
8700 if (recog_memoized (insn
) < 0)
8703 len
= get_attr_length (insn
);
8706 /* ??? Most of the places below, we would like to abort, as
8707 it would indicate an error either in Haifa, or in the
8708 scheduling description. Unfortunately, Haifa never
8709 schedules the last instruction of the BB, so we don't
8710 have an accurate TI bit to go off. */
8712 if (in_use
& EV5_E0
)
8714 if (in_use
& EV5_E1
)
8719 in_use
|= EV5_E0
| EV5_E01
;
8723 if (in_use
& EV5_E0
)
8725 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
8733 if (in_use
& EV5_E1
)
8739 if (in_use
& EV5_FA
)
8741 if (in_use
& EV5_FM
)
8746 in_use
|= EV5_FA
| EV5_FAM
;
8750 if (in_use
& EV5_FA
)
8756 if (in_use
& EV5_FM
)
8769 /* Haifa doesn't do well scheduling branches. */
8770 /* ??? If this is predicted not-taken, slotting continues, except
8771 that no more IBR, FBR, or JSR insns may be slotted. */
8772 if (GET_CODE (insn
) == JUMP_INSN
)
8776 insn
= next_nonnote_insn (insn
);
8778 if (!insn
|| ! INSN_P (insn
))
8781 /* Let Haifa tell us where it thinks insn group boundaries are. */
8782 if (GET_MODE (insn
) == TImode
)
8785 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8790 insn
= next_nonnote_insn (insn
);
8799 alphaev4_next_nop (pin_use
)
8802 int in_use
= *pin_use
;
8805 if (!(in_use
& EV4_IB0
))
8810 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
8815 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
8828 alphaev5_next_nop (pin_use
)
8831 int in_use
= *pin_use
;
8834 if (!(in_use
& EV5_E1
))
8839 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
8844 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
8856 /* The instruction group alignment main loop. */
8859 alpha_align_insns (insns
, max_align
, next_group
, next_nop
)
8861 unsigned int max_align
;
8862 rtx (*next_group
) PARAMS ((rtx
, int *, int *));
8863 rtx (*next_nop
) PARAMS ((int *));
8865 /* ALIGN is the known alignment for the insn group. */
8867 /* OFS is the offset of the current insn in the insn group. */
8869 int prev_in_use
, in_use
, len
;
8872 /* Let shorten branches care for assigning alignments to code labels. */
8873 shorten_branches (insns
);
8875 if (align_functions
< 4)
8877 else if ((unsigned int) align_functions
< max_align
)
8878 align
= align_functions
;
8882 ofs
= prev_in_use
= 0;
8884 if (GET_CODE (i
) == NOTE
)
8885 i
= next_nonnote_insn (i
);
8889 next
= (*next_group
) (i
, &in_use
, &len
);
8891 /* When we see a label, resync alignment etc. */
8892 if (GET_CODE (i
) == CODE_LABEL
)
8894 unsigned int new_align
= 1 << label_to_alignment (i
);
8896 if (new_align
>= align
)
8898 align
= new_align
< max_align
? new_align
: max_align
;
8902 else if (ofs
& (new_align
-1))
8903 ofs
= (ofs
| (new_align
-1)) + 1;
8908 /* Handle complex instructions special. */
8909 else if (in_use
== 0)
8911 /* Asms will have length < 0. This is a signal that we have
8912 lost alignment knowledge. Assume, however, that the asm
8913 will not mis-align instructions. */
8922 /* If the known alignment is smaller than the recognized insn group,
8923 realign the output. */
8924 else if ((int) align
< len
)
8926 unsigned int new_log_align
= len
> 8 ? 4 : 3;
8929 where
= prev
= prev_nonnote_insn (i
);
8930 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
8933 /* Can't realign between a call and its gp reload. */
8934 if (! (TARGET_EXPLICIT_RELOCS
8935 && prev
&& GET_CODE (prev
) == CALL_INSN
))
8937 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
8938 align
= 1 << new_log_align
;
8943 /* If the group won't fit in the same INT16 as the previous,
8944 we need to add padding to keep the group together. Rather
8945 than simply leaving the insn filling to the assembler, we
8946 can make use of the knowledge of what sorts of instructions
8947 were issued in the previous group to make sure that all of
8948 the added nops are really free. */
8949 else if (ofs
+ len
> (int) align
)
8951 int nop_count
= (align
- ofs
) / 4;
8954 /* Insert nops before labels, branches, and calls to truely merge
8955 the execution of the nops with the previous instruction group. */
8956 where
= prev_nonnote_insn (i
);
8959 if (GET_CODE (where
) == CODE_LABEL
)
8961 rtx where2
= prev_nonnote_insn (where
);
8962 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
8965 else if (GET_CODE (where
) == INSN
)
8972 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
8973 while (--nop_count
);
8977 ofs
= (ofs
+ len
) & (align
- 1);
8978 prev_in_use
= in_use
;
8983 /* Machine dependent reorg pass. */
8989 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
8990 alpha_handle_trap_shadows (insns
);
8992 /* Due to the number of extra trapb insns, don't bother fixing up
8993 alignment when trap precision is instruction. Moreover, we can
8994 only do our job when sched2 is run. */
8995 if (optimize
&& !optimize_size
8996 && alpha_tp
!= ALPHA_TP_INSN
8997 && flag_schedule_insns_after_reload
)
8999 if (alpha_cpu
== PROCESSOR_EV4
)
9000 alpha_align_insns (insns
, 8, alphaev4_next_group
, alphaev4_next_nop
);
9001 else if (alpha_cpu
== PROCESSOR_EV5
)
9002 alpha_align_insns (insns
, 16, alphaev5_next_group
, alphaev5_next_nop
);
9006 #ifdef OBJECT_FORMAT_ELF
9008 /* Switch to the section to which we should output X. The only thing
9009 special we do here is to honor small data. */
9012 alpha_elf_select_rtx_section (mode
, x
, align
)
9013 enum machine_mode mode
;
9015 unsigned HOST_WIDE_INT align
;
9017 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
9018 /* ??? Consider using mergable sdata sections. */
9021 default_elf_select_rtx_section (mode
, x
, align
);
9024 #endif /* OBJECT_FORMAT_ELF */
9026 #if TARGET_ABI_OPEN_VMS
9028 /* Return the VMS argument type corresponding to MODE. */
9031 alpha_arg_type (mode
)
9032 enum machine_mode mode
;
9037 return TARGET_FLOAT_VAX
? FF
: FS
;
9039 return TARGET_FLOAT_VAX
? FD
: FT
;
9045 /* Return an rtx for an integer representing the VMS Argument Information
9049 alpha_arg_info_reg_val (cum
)
9050 CUMULATIVE_ARGS cum
;
9052 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
9055 for (i
= 0; i
< 6; i
++)
9056 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
9058 return GEN_INT (regval
);
9061 /* Protect alpha_links from garbage collection. */
9064 mark_alpha_links_node (node
, data
)
9065 splay_tree_node node
;
9066 void *data ATTRIBUTE_UNUSED
;
9068 struct alpha_links
*links
= (struct alpha_links
*) node
->value
;
9069 ggc_mark_rtx (links
->linkage
);
9074 mark_alpha_links (ptr
)
9077 splay_tree tree
= *(splay_tree
*) ptr
;
9078 splay_tree_foreach (tree
, mark_alpha_links_node
, NULL
);
9081 /* Make (or fake) .linkage entry for function call.
9083 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
9085 Return an SYMBOL_REF rtx for the linkage. */
9088 alpha_need_linkage (name
, is_local
)
9092 splay_tree_node node
;
9093 struct alpha_links
*al
;
9094 struct alpha_funcs
*cfaf
;
9101 alpha_funcs_tree
= splay_tree_new
9102 ((splay_tree_compare_fn
) splay_tree_compare_pointers
,
9103 (splay_tree_delete_key_fn
) free
,
9104 (splay_tree_delete_key_fn
) free
);
9106 cfaf
= (struct alpha_funcs
*) xmalloc (sizeof (struct alpha_funcs
));
9109 cfaf
->num
= ++alpha_funcs_num
;
9111 splay_tree_insert (alpha_funcs_tree
,
9112 (splay_tree_key
) current_function_decl
,
9113 (splay_tree_value
) cfaf
);
9117 if (alpha_links_tree
)
9119 /* Is this name already defined? */
9121 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9124 al
= (struct alpha_links
*) node
->value
;
9127 /* Defined here but external assumed. */
9128 if (al
->lkind
== KIND_EXTERN
)
9129 al
->lkind
= KIND_LOCAL
;
9133 /* Used here but unused assumed. */
9134 if (al
->lkind
== KIND_UNUSED
)
9135 al
->lkind
= KIND_LOCAL
;
9142 alpha_links_tree
= splay_tree_new
9143 ((splay_tree_compare_fn
) strcmp
,
9144 (splay_tree_delete_key_fn
) free
,
9145 (splay_tree_delete_key_fn
) free
);
9147 ggc_add_root (&alpha_links_tree
, 1, 1, mark_alpha_links
);
9150 al
= (struct alpha_links
*) xmalloc (sizeof (struct alpha_links
));
9151 name
= xstrdup (name
);
9153 /* Assume external if no definition. */
9154 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9156 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9157 get_identifier (name
);
9159 /* Construct a SYMBOL_REF for us to call. */
9161 size_t name_len
= strlen (name
);
9162 char *linksym
= alloca (name_len
+ 6);
9164 memcpy (linksym
+ 1, name
, name_len
);
9165 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
9166 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
9167 ggc_alloc_string (linksym
, name_len
+ 5));
9170 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
9171 (splay_tree_value
) al
);
9177 alpha_use_linkage (linkage
, cfundecl
, lflag
, rflag
)
9183 splay_tree_node cfunnode
;
9184 struct alpha_funcs
*cfaf
;
9185 struct alpha_links
*al
;
9186 const char *name
= XSTR (linkage
, 0);
9188 cfaf
= (struct alpha_funcs
*) 0;
9189 al
= (struct alpha_links
*) 0;
9191 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
9192 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
9196 splay_tree_node lnode
;
9198 /* Is this name already defined? */
9200 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
9202 al
= (struct alpha_links
*) lnode
->value
;
9206 cfaf
->links
= splay_tree_new
9207 ((splay_tree_compare_fn
) strcmp
,
9208 (splay_tree_delete_key_fn
) free
,
9209 (splay_tree_delete_key_fn
) free
);
9210 ggc_add_root (&cfaf
->links
, 1, 1, mark_alpha_links
);
9219 splay_tree_node node
= 0;
9220 struct alpha_links
*anl
;
9225 name_len
= strlen (name
);
9227 al
= (struct alpha_links
*) xmalloc (sizeof (struct alpha_links
));
9228 al
->num
= cfaf
->num
;
9230 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9233 anl
= (struct alpha_links
*) node
->value
;
9234 al
->lkind
= anl
->lkind
;
9237 sprintf (buf
, "$%d..%s..lk", cfaf
->num
, name
);
9238 buflen
= strlen (buf
);
9239 linksym
= alloca (buflen
+ 1);
9240 memcpy (linksym
, buf
, buflen
+ 1);
9242 al
->linkage
= gen_rtx_SYMBOL_REF
9243 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
9245 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
9246 (splay_tree_value
) al
);
9250 al
->rkind
= KIND_CODEADDR
;
9252 al
->rkind
= KIND_LINKAGE
;
9255 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
9261 alpha_write_one_linkage (node
, data
)
9262 splay_tree_node node
;
9265 const char *const name
= (const char *) node
->key
;
9266 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
9267 FILE *stream
= (FILE *) data
;
9269 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
9270 if (link
->rkind
== KIND_CODEADDR
)
9272 if (link
->lkind
== KIND_LOCAL
)
9274 /* Local and used */
9275 fprintf (stream
, "\t.quad %s..en\n", name
);
9279 /* External and used, request code address. */
9280 fprintf (stream
, "\t.code_address %s\n", name
);
9285 if (link
->lkind
== KIND_LOCAL
)
9287 /* Local and used, build linkage pair. */
9288 fprintf (stream
, "\t.quad %s..en\n", name
);
9289 fprintf (stream
, "\t.quad %s\n", name
);
9293 /* External and used, request linkage pair. */
9294 fprintf (stream
, "\t.linkage %s\n", name
);
9302 alpha_write_linkage (stream
, funname
, fundecl
)
9304 const char *funname
;
9307 splay_tree_node node
;
9308 struct alpha_funcs
*func
;
9311 fprintf (stream
, "\t.align 3\n");
9312 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
9313 func
= (struct alpha_funcs
*) node
->value
;
9315 fputs ("\t.name ", stream
);
9316 assemble_name (stream
, funname
);
9317 fputs ("..na\n", stream
);
9318 ASM_OUTPUT_LABEL (stream
, funname
);
9319 fprintf (stream
, "\t.pdesc ");
9320 assemble_name (stream
, funname
);
9321 fprintf (stream
, "..en,%s\n",
9322 alpha_procedure_type
== PT_STACK
? "stack"
9323 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
9327 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
9328 /* splay_tree_delete (func->links); */
9332 /* Given a decl, a section name, and whether the decl initializer
9333 has relocs, choose attributes for the section. */
9335 #define SECTION_VMS_OVERLAY SECTION_FORGET
9336 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9337 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9340 vms_section_type_flags (decl
, name
, reloc
)
9345 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9347 if (decl
&& DECL_ATTRIBUTES (decl
)
9348 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
9349 flags
|= SECTION_VMS_OVERLAY
;
9350 if (decl
&& DECL_ATTRIBUTES (decl
)
9351 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
9352 flags
|= SECTION_VMS_GLOBAL
;
9353 if (decl
&& DECL_ATTRIBUTES (decl
)
9354 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
9355 flags
|= SECTION_VMS_INITIALIZE
;
9360 /* Switch to an arbitrary section NAME with attributes as specified
9361 by FLAGS. ALIGN specifies any known alignment requirements for
9362 the section; 0 if the default should be used. */
9365 vms_asm_named_section (name
, flags
)
9369 fputc ('\n', asm_out_file
);
9370 fprintf (asm_out_file
, ".section\t%s", name
);
9372 if (flags
& SECTION_VMS_OVERLAY
)
9373 fprintf (asm_out_file
, ",OVR");
9374 if (flags
& SECTION_VMS_GLOBAL
)
9375 fprintf (asm_out_file
, ",GBL");
9376 if (flags
& SECTION_VMS_INITIALIZE
)
9377 fprintf (asm_out_file
, ",NOMOD");
9378 if (flags
& SECTION_DEBUG
)
9379 fprintf (asm_out_file
, ",NOWRT");
9381 fputc ('\n', asm_out_file
);
9384 /* Record an element in the table of global constructors. SYMBOL is
9385 a SYMBOL_REF of the function to be called; PRIORITY is a number
9386 between 0 and MAX_INIT_PRIORITY.
9388 Differs from default_ctors_section_asm_out_constructor in that the
9389 width of the .ctors entry is always 64 bits, rather than the 32 bits
9390 used by a normal pointer. */
9393 vms_asm_out_constructor (symbol
, priority
)
9395 int priority ATTRIBUTE_UNUSED
;
9398 assemble_align (BITS_PER_WORD
);
9399 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9403 vms_asm_out_destructor (symbol
, priority
)
9405 int priority ATTRIBUTE_UNUSED
;
9408 assemble_align (BITS_PER_WORD
);
9409 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9414 alpha_need_linkage (name
, is_local
)
9415 const char *name ATTRIBUTE_UNUSED
;
9416 int is_local ATTRIBUTE_UNUSED
;
9422 alpha_use_linkage (linkage
, cfundecl
, lflag
, rflag
)
9423 rtx linkage ATTRIBUTE_UNUSED
;
9424 tree cfundecl ATTRIBUTE_UNUSED
;
9425 int lflag ATTRIBUTE_UNUSED
;
9426 int rflag ATTRIBUTE_UNUSED
;
9431 #endif /* TARGET_ABI_OPEN_VMS */
9433 #if TARGET_ABI_UNICOSMK
9435 static void unicosmk_output_module_name
PARAMS ((FILE *));
9436 static void unicosmk_output_default_externs
PARAMS ((FILE *));
9437 static void unicosmk_output_dex
PARAMS ((FILE *));
9438 static void unicosmk_output_externs
PARAMS ((FILE *));
9439 static void unicosmk_output_addr_vec
PARAMS ((FILE *, rtx
));
9440 static const char *unicosmk_ssib_name
PARAMS ((void));
9441 static int unicosmk_special_name
PARAMS ((const char *));
9443 /* Define the offset between two registers, one to be eliminated, and the
9444 other its replacement, at the start of a routine. */
9447 unicosmk_initial_elimination_offset (from
, to
)
9453 fixed_size
= alpha_sa_size();
9454 if (fixed_size
!= 0)
9457 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9459 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9461 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9462 return (ALPHA_ROUND (current_function_outgoing_args_size
)
9463 + ALPHA_ROUND (get_frame_size()));
9464 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9465 return (ALPHA_ROUND (fixed_size
)
9466 + ALPHA_ROUND (get_frame_size()
9467 + current_function_outgoing_args_size
));
9472 /* Output the module name for .ident and .end directives. We have to strip
9473 directories and add make sure that the module name starts with a letter
9477 unicosmk_output_module_name (file
)
9482 /* Strip directories. */
9484 name
= strrchr (main_input_filename
, '/');
9488 name
= main_input_filename
;
9490 /* CAM only accepts module names that start with a letter or '$'. We
9491 prefix the module name with a '$' if necessary. */
9493 if (!ISALPHA (*name
))
9495 output_clean_symbol_name (file
, name
);
9498 /* Output text that to appear at the beginning of an assembler file. */
9501 unicosmk_asm_file_start (file
)
9506 fputs ("\t.ident\t", file
);
9507 unicosmk_output_module_name (file
);
9508 fputs ("\n\n", file
);
9510 /* The Unicos/Mk assembler uses different register names. Instead of trying
9511 to support them, we simply use micro definitions. */
9513 /* CAM has different register names: rN for the integer register N and fN
9514 for the floating-point register N. Instead of trying to use these in
9515 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9518 for (i
= 0; i
< 32; ++i
)
9519 fprintf (file
, "$%d <- r%d\n", i
, i
);
9521 for (i
= 0; i
< 32; ++i
)
9522 fprintf (file
, "$f%d <- f%d\n", i
, i
);
9526 /* The .align directive fill unused space with zeroes which does not work
9527 in code sections. We define the macro 'gcc@code@align' which uses nops
9528 instead. Note that it assumes that code sections always have the
9529 biggest possible alignment since . refers to the current offset from
9530 the beginning of the section. */
9532 fputs ("\t.macro gcc@code@align n\n", file
);
9533 fputs ("gcc@n@bytes = 1 << n\n", file
);
9534 fputs ("gcc@here = . % gcc@n@bytes\n", file
);
9535 fputs ("\t.if ne, gcc@here, 0\n", file
);
9536 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", file
);
9537 fputs ("\tbis r31,r31,r31\n", file
);
9538 fputs ("\t.endr\n", file
);
9539 fputs ("\t.endif\n", file
);
9540 fputs ("\t.endm gcc@code@align\n\n", file
);
9542 /* Output extern declarations which should always be visible. */
9543 unicosmk_output_default_externs (file
);
9545 /* Open a dummy section. We always need to be inside a section for the
9546 section-switching code to work correctly.
9547 ??? This should be a module id or something like that. I still have to
9548 figure out what the rules for those are. */
9549 fputs ("\n\t.psect\t$SG00000,data\n", file
);
9552 /* Output text to appear at the end of an assembler file. This includes all
9553 pending extern declarations and DEX expressions. */
9556 unicosmk_asm_file_end (file
)
9559 fputs ("\t.endp\n\n", file
);
9561 /* Output all pending externs. */
9563 unicosmk_output_externs (file
);
9565 /* Output dex definitions used for functions whose names conflict with
9568 unicosmk_output_dex (file
);
9570 fputs ("\t.end\t", file
);
9571 unicosmk_output_module_name (file
);
9575 /* Output the definition of a common variable. */
9578 unicosmk_output_common (file
, name
, size
, align
)
9585 printf ("T3E__: common %s\n", name
);
9588 fputs("\t.endp\n\n\t.psect ", file
);
9589 assemble_name(file
, name
);
9590 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
9591 fprintf(file
, "\t.byte\t0:%d\n", size
);
9593 /* Mark the symbol as defined in this module. */
9594 name_tree
= get_identifier (name
);
9595 TREE_ASM_WRITTEN (name_tree
) = 1;
9598 #define SECTION_PUBLIC SECTION_MACH_DEP
9599 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9600 static int current_section_align
;
9603 unicosmk_section_type_flags (decl
, name
, reloc
)
9606 int reloc ATTRIBUTE_UNUSED
;
9608 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9613 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9615 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9616 if (align_functions_log
> current_section_align
)
9617 current_section_align
= align_functions_log
;
9619 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
9620 flags
|= SECTION_MAIN
;
9623 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
9625 if (TREE_PUBLIC (decl
))
9626 flags
|= SECTION_PUBLIC
;
9631 /* Generate a section name for decl and associate it with the
9635 unicosmk_unique_section (decl
, reloc
)
9637 int reloc ATTRIBUTE_UNUSED
;
9645 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9646 name
= alpha_strip_name_encoding (name
);
9647 len
= strlen (name
);
9649 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9653 /* It is essential that we prefix the section name here because
9654 otherwise the section names generated for constructors and
9655 destructors confuse collect2. */
9657 string
= alloca (len
+ 6);
9658 sprintf (string
, "code@%s", name
);
9659 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9661 else if (TREE_PUBLIC (decl
))
9662 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
9667 string
= alloca (len
+ 6);
9668 sprintf (string
, "data@%s", name
);
9669 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9673 /* Switch to an arbitrary section NAME with attributes as specified
9674 by FLAGS. ALIGN specifies any known alignment requirements for
9675 the section; 0 if the default should be used. */
9678 unicosmk_asm_named_section (name
, flags
)
9684 /* Close the previous section. */
9686 fputs ("\t.endp\n\n", asm_out_file
);
9688 /* Find out what kind of section we are opening. */
9690 if (flags
& SECTION_MAIN
)
9691 fputs ("\t.start\tmain\n", asm_out_file
);
9693 if (flags
& SECTION_CODE
)
9695 else if (flags
& SECTION_PUBLIC
)
9700 if (current_section_align
!= 0)
9701 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
9702 current_section_align
, kind
);
9704 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
9708 unicosmk_insert_attributes (decl
, attr_ptr
)
9710 tree
*attr_ptr ATTRIBUTE_UNUSED
;
9713 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
9714 unicosmk_unique_section (decl
, 0);
9717 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9718 in code sections because .align fill unused space with zeroes. */
9721 unicosmk_output_align (file
, align
)
9725 if (inside_function
)
9726 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
9728 fprintf (file
, "\t.align\t%d\n", align
);
9731 /* Add a case vector to the current function's list of deferred case
9732 vectors. Case vectors have to be put into a separate section because CAM
9733 does not allow data definitions in code sections. */
9736 unicosmk_defer_case_vector (lab
, vec
)
9740 struct machine_function
*machine
= cfun
->machine
;
9742 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9743 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
9744 machine
->addr_list
);
9747 /* Output a case vector. */
9750 unicosmk_output_addr_vec (file
, vec
)
9754 rtx lab
= XEXP (vec
, 0);
9755 rtx body
= XEXP (vec
, 1);
9756 int vlen
= XVECLEN (body
, 0);
9759 (*targetm
.asm_out
.internal_label
) (file
, "L", CODE_LABEL_NUMBER (lab
));
9761 for (idx
= 0; idx
< vlen
; idx
++)
9763 ASM_OUTPUT_ADDR_VEC_ELT
9764 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9768 /* Output current function's deferred case vectors. */
9771 unicosmk_output_deferred_case_vectors (file
)
9774 struct machine_function
*machine
= cfun
->machine
;
9777 if (machine
->addr_list
== NULL_RTX
)
9781 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
9782 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
9785 /* Set up the dynamic subprogram information block (DSIB) and update the
9786 frame pointer register ($15) for subroutines which have a frame. If the
9787 subroutine doesn't have a frame, simply increment $15. */
9790 unicosmk_gen_dsib (imaskP
)
9791 unsigned long * imaskP
;
9793 if (alpha_procedure_type
== PT_STACK
)
9795 const char *ssib_name
;
9798 /* Allocate 64 bytes for the DSIB. */
9800 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9802 emit_insn (gen_blockage ());
9804 /* Save the return address. */
9806 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
9807 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9808 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
9809 (*imaskP
) &= ~(1L << REG_RA
);
9811 /* Save the old frame pointer. */
9813 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
9814 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9815 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
9816 (*imaskP
) &= ~(1L << HARD_FRAME_POINTER_REGNUM
);
9818 emit_insn (gen_blockage ());
9820 /* Store the SSIB pointer. */
9822 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
9823 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
9824 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9826 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
9827 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
9828 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
9830 /* Save the CIW index. */
9832 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
9833 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9834 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
9836 emit_insn (gen_blockage ());
9838 /* Set the new frame pointer. */
9840 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9841 stack_pointer_rtx
, GEN_INT (64))));
9846 /* Increment the frame pointer register to indicate that we do not
9849 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9850 hard_frame_pointer_rtx
, GEN_INT (1))));
9854 #define SSIB_PREFIX "__SSIB_"
9855 #define SSIB_PREFIX_LEN 7
9857 /* Generate the name of the SSIB section for the current function. */
9860 unicosmk_ssib_name ()
9862 /* This is ok since CAM won't be able to deal with names longer than that
9865 static char name
[256];
9871 x
= DECL_RTL (cfun
->decl
);
9872 if (GET_CODE (x
) != MEM
)
9875 if (GET_CODE (x
) != SYMBOL_REF
)
9877 fnname
= alpha_strip_name_encoding (XSTR (x
, 0));
9879 len
= strlen (fnname
);
9880 if (len
+ SSIB_PREFIX_LEN
> 255)
9881 len
= 255 - SSIB_PREFIX_LEN
;
9883 strcpy (name
, SSIB_PREFIX
);
9884 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
9885 name
[len
+ SSIB_PREFIX_LEN
] = 0;
9890 /* Output the static subroutine information block for the current
9894 unicosmk_output_ssib (file
, fnname
)
9902 struct machine_function
*machine
= cfun
->machine
;
9905 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
9906 unicosmk_ssib_name ());
9908 /* Some required stuff and the function name length. */
9910 len
= strlen (fnname
);
9911 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
9914 ??? We don't do that yet. */
9916 fputs ("\t.quad\t0\n", file
);
9918 /* Function address. */
9920 fputs ("\t.quad\t", file
);
9921 assemble_name (file
, fnname
);
9924 fputs ("\t.quad\t0\n", file
);
9925 fputs ("\t.quad\t0\n", file
);
9928 ??? We do it the same way Cray CC does it but this could be
9931 for( i
= 0; i
< len
; i
++ )
9932 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
9933 if( (len
% 8) == 0 )
9934 fputs ("\t.quad\t0\n", file
);
9936 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
9938 /* All call information words used in the function. */
9940 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
9943 fprintf (file
, "\t.quad\t");
9944 #if HOST_BITS_PER_WIDE_INT == 32
9945 fprintf (file
, HOST_WIDE_INT_PRINT_DOUBLE_HEX
,
9946 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
9948 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (ciw
));
9950 fprintf (file
, "\n");
9954 /* Add a call information word (CIW) to the list of the current function's
9955 CIWs and return its index.
9957 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9960 unicosmk_add_call_info_word (x
)
9964 struct machine_function
*machine
= cfun
->machine
;
9966 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
9967 if (machine
->first_ciw
== NULL_RTX
)
9968 machine
->first_ciw
= node
;
9970 XEXP (machine
->last_ciw
, 1) = node
;
9972 machine
->last_ciw
= node
;
9973 ++machine
->ciw_count
;
9975 return GEN_INT (machine
->ciw_count
9976 + strlen (current_function_name
)/8 + 5);
9979 static char unicosmk_section_buf
[100];
9982 unicosmk_text_section ()
9984 static int count
= 0;
9985 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9987 return unicosmk_section_buf
;
9991 unicosmk_data_section ()
9993 static int count
= 1;
9994 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9996 return unicosmk_section_buf
;
9999 /* The Cray assembler doesn't accept extern declarations for symbols which
10000 are defined in the same file. We have to keep track of all global
10001 symbols which are referenced and/or defined in a source file and output
10002 extern declarations for those which are referenced but not defined at
10003 the end of file. */
10005 /* List of identifiers for which an extern declaration might have to be
10008 struct unicosmk_extern_list
10010 struct unicosmk_extern_list
*next
;
10014 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
10016 /* Output extern declarations which are required for every asm file. */
10019 unicosmk_output_default_externs (file
)
10022 static const char *const externs
[] =
10023 { "__T3E_MISMATCH" };
10028 n
= ARRAY_SIZE (externs
);
10030 for (i
= 0; i
< n
; i
++)
10031 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
10034 /* Output extern declarations for global symbols which are have been
10035 referenced but not defined. */
10038 unicosmk_output_externs (file
)
10041 struct unicosmk_extern_list
*p
;
10042 const char *real_name
;
10046 len
= strlen (user_label_prefix
);
10047 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
10049 /* We have to strip the encoding and possibly remove user_label_prefix
10050 from the identifier in order to handle -fleading-underscore and
10051 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
10052 real_name
= alpha_strip_name_encoding (p
->name
);
10053 if (len
&& p
->name
[0] == '*'
10054 && !memcmp (real_name
, user_label_prefix
, len
))
10057 name_tree
= get_identifier (real_name
);
10058 if (! TREE_ASM_WRITTEN (name_tree
))
10060 TREE_ASM_WRITTEN (name_tree
) = 1;
10061 fputs ("\t.extern\t", file
);
10062 assemble_name (file
, p
->name
);
10068 /* Record an extern. */
10071 unicosmk_add_extern (name
)
10074 struct unicosmk_extern_list
*p
;
10076 p
= (struct unicosmk_extern_list
*)
10077 xmalloc (sizeof (struct unicosmk_extern_list
));
10078 p
->next
= unicosmk_extern_head
;
10080 unicosmk_extern_head
= p
;
10083 /* The Cray assembler generates incorrect code if identifiers which
10084 conflict with register names are used as instruction operands. We have
10085 to replace such identifiers with DEX expressions. */
10087 /* Structure to collect identifiers which have been replaced by DEX
10090 struct unicosmk_dex
{
10091 struct unicosmk_dex
*next
;
10095 /* List of identifiers which have been replaced by DEX expressions. The DEX
10096 number is determined by the position in the list. */
10098 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
10100 /* The number of elements in the DEX list. */
10102 static int unicosmk_dex_count
= 0;
10104 /* Check if NAME must be replaced by a DEX expression. */
10107 unicosmk_special_name (name
)
10110 if (name
[0] == '*')
10113 if (name
[0] == '$')
10116 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
10121 case '1': case '2':
10122 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
10125 return (name
[2] == '\0'
10126 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
10129 return (ISDIGIT (name
[1]) && name
[2] == '\0');
10133 /* Return the DEX number if X must be replaced by a DEX expression and 0
10137 unicosmk_need_dex (x
)
10140 struct unicosmk_dex
*dex
;
10144 if (GET_CODE (x
) != SYMBOL_REF
)
10148 if (! unicosmk_special_name (name
))
10151 i
= unicosmk_dex_count
;
10152 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10154 if (! strcmp (name
, dex
->name
))
10159 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
10161 dex
->next
= unicosmk_dex_list
;
10162 unicosmk_dex_list
= dex
;
10164 ++unicosmk_dex_count
;
10165 return unicosmk_dex_count
;
10168 /* Output the DEX definitions for this file. */
10171 unicosmk_output_dex (file
)
10174 struct unicosmk_dex
*dex
;
10177 if (unicosmk_dex_list
== NULL
)
10180 fprintf (file
, "\t.dexstart\n");
10182 i
= unicosmk_dex_count
;
10183 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10185 fprintf (file
, "\tDEX (%d) = ", i
);
10186 assemble_name (file
, dex
->name
);
10191 fprintf (file
, "\t.dexend\n");
10197 unicosmk_output_deferred_case_vectors (file
)
10198 FILE *file ATTRIBUTE_UNUSED
;
10202 unicosmk_gen_dsib (imaskP
)
10203 unsigned long * imaskP ATTRIBUTE_UNUSED
;
10207 unicosmk_output_ssib (file
, fnname
)
10208 FILE * file ATTRIBUTE_UNUSED
;
10209 const char * fnname ATTRIBUTE_UNUSED
;
10213 unicosmk_add_call_info_word (x
)
10214 rtx x ATTRIBUTE_UNUSED
;
10220 unicosmk_need_dex (x
)
10221 rtx x ATTRIBUTE_UNUSED
;
10226 #endif /* TARGET_ABI_UNICOSMK */
10228 #include "gt-alpha.h"