1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
45 #include "integrate.h"
48 #include "target-def.h"
50 #include "langhooks.h"
52 /* Specify which cpu to schedule for. */
54 enum processor_type alpha_cpu
;
55 static const char * const alpha_cpu_name
[] =
60 /* Specify how accurate floating-point traps need to be. */
62 enum alpha_trap_precision alpha_tp
;
64 /* Specify the floating-point rounding mode. */
66 enum alpha_fp_rounding_mode alpha_fprm
;
68 /* Specify which things cause traps. */
70 enum alpha_fp_trap_mode alpha_fptm
;
72 /* Specify bit size of immediate TLS offsets. */
74 int alpha_tls_size
= 32;
76 /* Strings decoded into the above options. */
78 const char *alpha_cpu_string
; /* -mcpu= */
79 const char *alpha_tune_string
; /* -mtune= */
80 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
81 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
82 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
83 const char *alpha_mlat_string
; /* -mmemory-latency= */
84 const char *alpha_tls_size_string
; /* -mtls-size=[16|32|64] */
86 /* Save information from a "cmpxx" operation until the branch or scc is
89 struct alpha_compare alpha_compare
;
91 /* Nonzero if inside of a function, because the Alpha asm can't
92 handle .files inside of functions. */
94 static int inside_function
= FALSE
;
96 /* The number of cycles of latency we should assume on memory reads. */
98 int alpha_memory_latency
= 3;
100 /* Whether the function needs the GP. */
102 static int alpha_function_needs_gp
;
104 /* The alias set for prologue/epilogue register save/restore. */
106 static int alpha_sr_alias_set
;
108 /* The assembler name of the current function. */
110 static const char *alpha_fnname
;
112 /* The next explicit relocation sequence number. */
113 int alpha_next_sequence_number
= 1;
115 /* The literal and gpdisp sequence numbers for this insn, as printed
116 by %# and %* respectively. */
117 int alpha_this_literal_sequence_number
;
118 int alpha_this_gpdisp_sequence_number
;
120 /* Declarations of static functions. */
121 static int tls_symbolic_operand_1
122 PARAMS ((rtx
, enum machine_mode
, int, int));
123 static enum tls_model tls_symbolic_operand_type
125 static bool decl_in_text_section
127 static bool alpha_in_small_data_p
129 static void alpha_encode_section_info
130 PARAMS ((tree
, int));
131 static const char *alpha_strip_name_encoding
132 PARAMS ((const char *));
133 static int some_small_symbolic_operand_1
134 PARAMS ((rtx
*, void *));
135 static int split_small_symbolic_operand_1
136 PARAMS ((rtx
*, void *));
137 static void alpha_set_memflags_1
138 PARAMS ((rtx
, int, int, int));
139 static rtx alpha_emit_set_const_1
140 PARAMS ((rtx
, enum machine_mode
, HOST_WIDE_INT
, int));
141 static void alpha_expand_unaligned_load_words
142 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
143 static void alpha_expand_unaligned_store_words
144 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
145 static void alpha_init_builtins
147 static rtx alpha_expand_builtin
148 PARAMS ((tree
, rtx
, rtx
, enum machine_mode
, int));
149 static void alpha_sa_mask
150 PARAMS ((unsigned long *imaskP
, unsigned long *fmaskP
));
151 static int find_lo_sum
152 PARAMS ((rtx
*, void *));
153 static int alpha_does_function_need_gp
155 static int alpha_ra_ever_killed
157 static const char *get_trap_mode_suffix
159 static const char *get_round_mode_suffix
161 static const char *get_some_local_dynamic_name
163 static int get_some_local_dynamic_name_1
164 PARAMS ((rtx
*, void *));
165 static rtx set_frame_related_p
167 static const char *alpha_lookup_xfloating_lib_func
168 PARAMS ((enum rtx_code
));
169 static int alpha_compute_xfloating_mode_arg
170 PARAMS ((enum rtx_code
, enum alpha_fp_rounding_mode
));
171 static void alpha_emit_xfloating_libcall
172 PARAMS ((const char *, rtx
, rtx
[], int, rtx
));
173 static rtx alpha_emit_xfloating_compare
174 PARAMS ((enum rtx_code
, rtx
, rtx
));
175 static void alpha_output_function_end_prologue
177 static int alpha_adjust_cost
178 PARAMS ((rtx
, rtx
, rtx
, int));
179 static int alpha_issue_rate
181 static int alpha_use_dfa_pipeline_interface
183 static int alpha_multipass_dfa_lookahead
186 #ifdef OBJECT_FORMAT_ELF
187 static void alpha_elf_select_rtx_section
188 PARAMS ((enum machine_mode
, rtx
, unsigned HOST_WIDE_INT
));
191 #if TARGET_ABI_OPEN_VMS
192 static bool alpha_linkage_symbol_p
193 PARAMS ((const char *symname
));
194 static void alpha_write_linkage
195 PARAMS ((FILE *, const char *, tree
));
198 static struct machine_function
* alpha_init_machine_status
201 static void unicosmk_output_deferred_case_vectors
PARAMS ((FILE *));
202 static void unicosmk_gen_dsib
PARAMS ((unsigned long *imaskP
));
203 static void unicosmk_output_ssib
PARAMS ((FILE *, const char *));
204 static int unicosmk_need_dex
PARAMS ((rtx
));
206 /* Get the number of args of a function in one of two ways. */
207 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
208 #define NUM_ARGS current_function_args_info.num_args
210 #define NUM_ARGS current_function_args_info
216 /* Initialize the GCC target structure. */
217 #if TARGET_ABI_OPEN_VMS
218 const struct attribute_spec vms_attribute_table
[];
219 static unsigned int vms_section_type_flags
PARAMS ((tree
, const char *, int));
220 static void vms_asm_named_section
PARAMS ((const char *, unsigned int));
221 static void vms_asm_out_constructor
PARAMS ((rtx
, int));
222 static void vms_asm_out_destructor
PARAMS ((rtx
, int));
223 # undef TARGET_ATTRIBUTE_TABLE
224 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
225 # undef TARGET_SECTION_TYPE_FLAGS
226 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
229 #undef TARGET_IN_SMALL_DATA_P
230 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
231 #undef TARGET_ENCODE_SECTION_INFO
232 #define TARGET_ENCODE_SECTION_INFO alpha_encode_section_info
233 #undef TARGET_STRIP_NAME_ENCODING
234 #define TARGET_STRIP_NAME_ENCODING alpha_strip_name_encoding
236 #if TARGET_ABI_UNICOSMK
237 static void unicosmk_asm_named_section
PARAMS ((const char *, unsigned int));
238 static void unicosmk_insert_attributes
PARAMS ((tree
, tree
*));
239 static unsigned int unicosmk_section_type_flags
PARAMS ((tree
, const char *,
241 static void unicosmk_unique_section
PARAMS ((tree
, int));
242 # undef TARGET_INSERT_ATTRIBUTES
243 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
244 # undef TARGET_SECTION_TYPE_FLAGS
245 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
246 # undef TARGET_ASM_UNIQUE_SECTION
247 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
248 # undef TARGET_ASM_GLOBALIZE_LABEL
249 # define TARGET_ASM_GLOBALIZE_LABEL hook_FILEptr_constcharptr_void
252 #undef TARGET_ASM_ALIGNED_HI_OP
253 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
254 #undef TARGET_ASM_ALIGNED_DI_OP
255 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
257 /* Default unaligned ops are provided for ELF systems. To get unaligned
258 data for non-ELF systems, we have to turn off auto alignment. */
259 #ifndef OBJECT_FORMAT_ELF
260 #undef TARGET_ASM_UNALIGNED_HI_OP
261 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
262 #undef TARGET_ASM_UNALIGNED_SI_OP
263 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
264 #undef TARGET_ASM_UNALIGNED_DI_OP
265 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
268 #ifdef OBJECT_FORMAT_ELF
269 #undef TARGET_ASM_SELECT_RTX_SECTION
270 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
273 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
274 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
276 #undef TARGET_SCHED_ADJUST_COST
277 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
278 #undef TARGET_SCHED_ISSUE_RATE
279 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
280 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
281 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
282 alpha_use_dfa_pipeline_interface
283 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
284 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
285 alpha_multipass_dfa_lookahead
287 #undef TARGET_HAVE_TLS
288 #define TARGET_HAVE_TLS HAVE_AS_TLS
290 #undef TARGET_INIT_BUILTINS
291 #define TARGET_INIT_BUILTINS alpha_init_builtins
292 #undef TARGET_EXPAND_BUILTIN
293 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
295 struct gcc_target targetm
= TARGET_INITIALIZER
;
297 /* Parse target option strings. */
303 static const struct cpu_table
{
304 const char *const name
;
305 const enum processor_type processor
;
308 #define EV5_MASK (MASK_CPU_EV5)
309 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
310 { "ev4", PROCESSOR_EV4
, 0 },
311 { "ev45", PROCESSOR_EV4
, 0 },
312 { "21064", PROCESSOR_EV4
, 0 },
313 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
314 { "21164", PROCESSOR_EV5
, EV5_MASK
},
315 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
316 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
317 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
318 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
319 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
320 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
321 { "21264", PROCESSOR_EV6
, EV6_MASK
},
322 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
323 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
327 /* Unicos/Mk doesn't have shared libraries. */
328 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
330 warning ("-f%s ignored for Unicos/Mk (not supported)",
331 (flag_pic
> 1) ? "PIC" : "pic");
335 /* On Unicos/Mk, the native compiler consistenly generates /d suffices for
336 floating-point instructions. Make that the default for this target. */
337 if (TARGET_ABI_UNICOSMK
)
338 alpha_fprm
= ALPHA_FPRM_DYN
;
340 alpha_fprm
= ALPHA_FPRM_NORM
;
342 alpha_tp
= ALPHA_TP_PROG
;
343 alpha_fptm
= ALPHA_FPTM_N
;
345 /* We cannot use su and sui qualifiers for conversion instructions on
346 Unicos/Mk. I'm not sure if this is due to assembler or hardware
347 limitations. Right now, we issue a warning if -mieee is specified
348 and then ignore it; eventually, we should either get it right or
349 disable the option altogether. */
353 if (TARGET_ABI_UNICOSMK
)
354 warning ("-mieee not supported on Unicos/Mk");
357 alpha_tp
= ALPHA_TP_INSN
;
358 alpha_fptm
= ALPHA_FPTM_SU
;
362 if (TARGET_IEEE_WITH_INEXACT
)
364 if (TARGET_ABI_UNICOSMK
)
365 warning ("-mieee-with-inexact not supported on Unicos/Mk");
368 alpha_tp
= ALPHA_TP_INSN
;
369 alpha_fptm
= ALPHA_FPTM_SUI
;
375 if (! strcmp (alpha_tp_string
, "p"))
376 alpha_tp
= ALPHA_TP_PROG
;
377 else if (! strcmp (alpha_tp_string
, "f"))
378 alpha_tp
= ALPHA_TP_FUNC
;
379 else if (! strcmp (alpha_tp_string
, "i"))
380 alpha_tp
= ALPHA_TP_INSN
;
382 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string
);
385 if (alpha_fprm_string
)
387 if (! strcmp (alpha_fprm_string
, "n"))
388 alpha_fprm
= ALPHA_FPRM_NORM
;
389 else if (! strcmp (alpha_fprm_string
, "m"))
390 alpha_fprm
= ALPHA_FPRM_MINF
;
391 else if (! strcmp (alpha_fprm_string
, "c"))
392 alpha_fprm
= ALPHA_FPRM_CHOP
;
393 else if (! strcmp (alpha_fprm_string
,"d"))
394 alpha_fprm
= ALPHA_FPRM_DYN
;
396 error ("bad value `%s' for -mfp-rounding-mode switch",
400 if (alpha_fptm_string
)
402 if (strcmp (alpha_fptm_string
, "n") == 0)
403 alpha_fptm
= ALPHA_FPTM_N
;
404 else if (strcmp (alpha_fptm_string
, "u") == 0)
405 alpha_fptm
= ALPHA_FPTM_U
;
406 else if (strcmp (alpha_fptm_string
, "su") == 0)
407 alpha_fptm
= ALPHA_FPTM_SU
;
408 else if (strcmp (alpha_fptm_string
, "sui") == 0)
409 alpha_fptm
= ALPHA_FPTM_SUI
;
411 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string
);
414 if (alpha_tls_size_string
)
416 if (strcmp (alpha_tls_size_string
, "16") == 0)
418 else if (strcmp (alpha_tls_size_string
, "32") == 0)
420 else if (strcmp (alpha_tls_size_string
, "64") == 0)
423 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string
);
427 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
428 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
430 if (alpha_cpu_string
)
432 for (i
= 0; cpu_table
[i
].name
; i
++)
433 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
435 alpha_cpu
= cpu_table
[i
].processor
;
436 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
437 | MASK_CPU_EV5
| MASK_CPU_EV6
);
438 target_flags
|= cpu_table
[i
].flags
;
441 if (! cpu_table
[i
].name
)
442 error ("bad value `%s' for -mcpu switch", alpha_cpu_string
);
445 if (alpha_tune_string
)
447 for (i
= 0; cpu_table
[i
].name
; i
++)
448 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
450 alpha_cpu
= cpu_table
[i
].processor
;
453 if (! cpu_table
[i
].name
)
454 error ("bad value `%s' for -mcpu switch", alpha_tune_string
);
457 /* Do some sanity checks on the above options. */
459 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
461 warning ("trap mode not supported on Unicos/Mk");
462 alpha_fptm
= ALPHA_FPTM_N
;
465 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
466 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
468 warning ("fp software completion requires -mtrap-precision=i");
469 alpha_tp
= ALPHA_TP_INSN
;
474 /* Except for EV6 pass 1 (not released), we always have precise
475 arithmetic traps. Which means we can do software completion
476 without minding trap shadows. */
477 alpha_tp
= ALPHA_TP_PROG
;
480 if (TARGET_FLOAT_VAX
)
482 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
484 warning ("rounding mode not supported for VAX floats");
485 alpha_fprm
= ALPHA_FPRM_NORM
;
487 if (alpha_fptm
== ALPHA_FPTM_SUI
)
489 warning ("trap mode not supported for VAX floats");
490 alpha_fptm
= ALPHA_FPTM_SU
;
498 if (!alpha_mlat_string
)
499 alpha_mlat_string
= "L1";
501 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
502 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
504 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
505 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
506 && alpha_mlat_string
[2] == '\0')
508 static int const cache_latency
[][4] =
510 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
511 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
512 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
515 lat
= alpha_mlat_string
[1] - '0';
516 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
518 warning ("L%d cache latency unknown for %s",
519 lat
, alpha_cpu_name
[alpha_cpu
]);
523 lat
= cache_latency
[alpha_cpu
][lat
-1];
525 else if (! strcmp (alpha_mlat_string
, "main"))
527 /* Most current memories have about 370ns latency. This is
528 a reasonable guess for a fast cpu. */
533 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string
);
537 alpha_memory_latency
= lat
;
540 /* Default the definition of "small data" to 8 bytes. */
544 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
546 target_flags
|= MASK_SMALL_DATA
;
547 else if (flag_pic
== 2)
548 target_flags
&= ~MASK_SMALL_DATA
;
550 /* Align labels and loops for optimal branching. */
551 /* ??? Kludge these by not doing anything if we don't optimize and also if
552 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
553 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
555 if (align_loops
<= 0)
557 if (align_jumps
<= 0)
560 if (align_functions
<= 0)
561 align_functions
= 16;
563 /* Acquire a unique set number for our register saves and restores. */
564 alpha_sr_alias_set
= new_alias_set ();
566 /* Register variables and functions with the garbage collector. */
568 /* Set up function hooks. */
569 init_machine_status
= alpha_init_machine_status
;
571 /* Tell the compiler when we're using VAX floating point. */
572 if (TARGET_FLOAT_VAX
)
574 real_format_for_mode
[SFmode
- QFmode
] = &vax_f_format
;
575 real_format_for_mode
[DFmode
- QFmode
] = &vax_g_format
;
576 real_format_for_mode
[TFmode
- QFmode
] = NULL
;
580 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
588 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
590 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
596 /* Returns 1 if OP is either the constant zero or a register. If a
597 register, it must be in the proper mode unless MODE is VOIDmode. */
600 reg_or_0_operand (op
, mode
)
602 enum machine_mode mode
;
604 return op
== CONST0_RTX (mode
) || register_operand (op
, mode
);
607 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
611 reg_or_6bit_operand (op
, mode
)
613 enum machine_mode mode
;
615 return ((GET_CODE (op
) == CONST_INT
616 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64)
617 || register_operand (op
, mode
));
621 /* Return 1 if OP is an 8-bit constant or any register. */
624 reg_or_8bit_operand (op
, mode
)
626 enum machine_mode mode
;
628 return ((GET_CODE (op
) == CONST_INT
629 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
630 || register_operand (op
, mode
));
633 /* Return 1 if OP is a constant or any register. */
636 reg_or_const_int_operand (op
, mode
)
638 enum machine_mode mode
;
640 return GET_CODE (op
) == CONST_INT
|| register_operand (op
, mode
);
643 /* Return 1 if OP is an 8-bit constant. */
646 cint8_operand (op
, mode
)
648 enum machine_mode mode ATTRIBUTE_UNUSED
;
650 return ((GET_CODE (op
) == CONST_INT
651 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100));
654 /* Return 1 if the operand is a valid second operand to an add insn. */
657 add_operand (op
, mode
)
659 enum machine_mode mode
;
661 if (GET_CODE (op
) == CONST_INT
)
662 /* Constraints I, J, O and P are covered by K. */
663 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K')
664 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
666 return register_operand (op
, mode
);
669 /* Return 1 if the operand is a valid second operand to a sign-extending
673 sext_add_operand (op
, mode
)
675 enum machine_mode mode
;
677 if (GET_CODE (op
) == CONST_INT
)
678 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
679 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'));
681 return reg_not_elim_operand (op
, mode
);
684 /* Return 1 if OP is the constant 4 or 8. */
687 const48_operand (op
, mode
)
689 enum machine_mode mode ATTRIBUTE_UNUSED
;
691 return (GET_CODE (op
) == CONST_INT
692 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
695 /* Return 1 if OP is a valid first operand to an AND insn. */
698 and_operand (op
, mode
)
700 enum machine_mode mode
;
702 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
703 return (zap_mask (CONST_DOUBLE_LOW (op
))
704 && zap_mask (CONST_DOUBLE_HIGH (op
)));
706 if (GET_CODE (op
) == CONST_INT
)
707 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
708 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
709 || zap_mask (INTVAL (op
)));
711 return register_operand (op
, mode
);
714 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
717 or_operand (op
, mode
)
719 enum machine_mode mode
;
721 if (GET_CODE (op
) == CONST_INT
)
722 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
723 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100);
725 return register_operand (op
, mode
);
728 /* Return 1 if OP is a constant that is the width, in bits, of an integral
729 mode smaller than DImode. */
732 mode_width_operand (op
, mode
)
734 enum machine_mode mode ATTRIBUTE_UNUSED
;
736 return (GET_CODE (op
) == CONST_INT
737 && (INTVAL (op
) == 8 || INTVAL (op
) == 16
738 || INTVAL (op
) == 32 || INTVAL (op
) == 64));
741 /* Return 1 if OP is a constant that is the width of an integral machine mode
742 smaller than an integer. */
745 mode_mask_operand (op
, mode
)
747 enum machine_mode mode ATTRIBUTE_UNUSED
;
749 if (GET_CODE (op
) == CONST_INT
)
751 HOST_WIDE_INT value
= INTVAL (op
);
757 if (value
== 0xffffffff)
762 else if (HOST_BITS_PER_WIDE_INT
== 32 && GET_CODE (op
) == CONST_DOUBLE
)
764 if (CONST_DOUBLE_LOW (op
) == 0xffffffff && CONST_DOUBLE_HIGH (op
) == 0)
771 /* Return 1 if OP is a multiple of 8 less than 64. */
774 mul8_operand (op
, mode
)
776 enum machine_mode mode ATTRIBUTE_UNUSED
;
778 return (GET_CODE (op
) == CONST_INT
779 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
780 && (INTVAL (op
) & 7) == 0);
783 /* Return 1 if OP is the zero constant for MODE. */
786 const0_operand (op
, mode
)
788 enum machine_mode mode
;
790 return op
== CONST0_RTX (mode
);
793 /* Return 1 if OP is a hard floating-point register. */
796 hard_fp_register_operand (op
, mode
)
798 enum machine_mode mode
;
800 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
803 if (GET_CODE (op
) == SUBREG
)
804 op
= SUBREG_REG (op
);
805 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == FLOAT_REGS
;
808 /* Return 1 if OP is a hard general register. */
811 hard_int_register_operand (op
, mode
)
813 enum machine_mode mode
;
815 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
818 if (GET_CODE (op
) == SUBREG
)
819 op
= SUBREG_REG (op
);
820 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
;
823 /* Return 1 if OP is a register or a constant integer. */
827 reg_or_cint_operand (op
, mode
)
829 enum machine_mode mode
;
831 return (GET_CODE (op
) == CONST_INT
832 || register_operand (op
, mode
));
835 /* Return 1 if OP is something that can be reloaded into a register;
836 if it is a MEM, it need not be valid. */
839 some_operand (op
, mode
)
841 enum machine_mode mode
;
843 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
846 switch (GET_CODE (op
))
860 return some_operand (SUBREG_REG (op
), VOIDmode
);
869 /* Likewise, but don't accept constants. */
872 some_ni_operand (op
, mode
)
874 enum machine_mode mode
;
876 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
879 if (GET_CODE (op
) == SUBREG
)
880 op
= SUBREG_REG (op
);
882 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == MEM
);
885 /* Return 1 if OP is a valid operand for the source of a move insn. */
888 input_operand (op
, mode
)
890 enum machine_mode mode
;
892 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
895 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
898 switch (GET_CODE (op
))
903 if (TARGET_EXPLICIT_RELOCS
)
905 /* We don't split symbolic operands into something unintelligable
906 until after reload, but we do not wish non-small, non-global
907 symbolic operands to be reconstructed from their high/lo_sum
909 return (small_symbolic_operand (op
, mode
)
910 || global_symbolic_operand (op
, mode
)
911 || gotdtp_symbolic_operand (op
, mode
)
912 || gottp_symbolic_operand (op
, mode
));
915 /* This handles both the Windows/NT and OSF cases. */
916 return mode
== ptr_mode
|| mode
== DImode
;
919 return (TARGET_EXPLICIT_RELOCS
920 && local_symbolic_operand (XEXP (op
, 0), mode
));
927 if (register_operand (op
, mode
))
929 /* ... fall through ... */
931 return ((TARGET_BWX
|| (mode
!= HImode
&& mode
!= QImode
))
932 && general_operand (op
, mode
));
936 return op
== CONST0_RTX (mode
);
939 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
951 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
952 file, and in the same section as the current function. */
955 current_file_function_operand (op
, mode
)
957 enum machine_mode mode ATTRIBUTE_UNUSED
;
959 if (GET_CODE (op
) != SYMBOL_REF
)
962 /* Easy test for recursion. */
963 if (op
== XEXP (DECL_RTL (current_function_decl
), 0))
966 /* Otherwise, we need the DECL for the SYMBOL_REF, which we can't get.
967 So SYMBOL_REF_FLAG has been declared to imply that the function is
968 in the default text section. So we must also check that the current
969 function is also in the text section. */
970 if (SYMBOL_REF_FLAG (op
) && decl_in_text_section (current_function_decl
))
976 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
979 direct_call_operand (op
, mode
)
981 enum machine_mode mode
;
983 /* Must be defined in this file. */
984 if (! current_file_function_operand (op
, mode
))
987 /* If profiling is implemented via linker tricks, we can't jump
988 to the nogp alternate entry point. */
989 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
990 but is approximately correct for the OSF ABIs. Don't know
991 what to do for VMS, NT, or UMK. */
992 if (! TARGET_PROFILING_NEEDS_GP
993 && ! current_function_profile
)
999 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
1000 a (non-tls) variable known to be defined in this file. */
1003 local_symbolic_operand (op
, mode
)
1005 enum machine_mode mode
;
1009 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1012 if (GET_CODE (op
) == LABEL_REF
)
1015 if (GET_CODE (op
) == CONST
1016 && GET_CODE (XEXP (op
, 0)) == PLUS
1017 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1018 op
= XEXP (XEXP (op
, 0), 0);
1020 if (GET_CODE (op
) != SYMBOL_REF
)
1023 /* Easy pickings. */
1024 if (CONSTANT_POOL_ADDRESS_P (op
) || STRING_POOL_ADDRESS_P (op
))
1027 /* ??? SYMBOL_REF_FLAG is set for local function symbols, but we
1028 run into problems with the rtl inliner in that the symbol was
1029 once external, but is local after inlining, which results in
1030 unrecognizable insns. */
1034 /* If @[LS], then alpha_encode_section_info sez it's local. */
1035 if (str
[0] == '@' && (str
[1] == 'L' || str
[1] == 'S'))
1038 /* If *$, then ASM_GENERATE_INTERNAL_LABEL sez it's local. */
1039 if (str
[0] == '*' && str
[1] == '$')
1045 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1046 known to be defined in this file in the small data area. */
1049 small_symbolic_operand (op
, mode
)
1051 enum machine_mode mode ATTRIBUTE_UNUSED
;
1055 if (! TARGET_SMALL_DATA
)
1058 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1061 if (GET_CODE (op
) == CONST
1062 && GET_CODE (XEXP (op
, 0)) == PLUS
1063 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1064 op
= XEXP (XEXP (op
, 0), 0);
1066 if (GET_CODE (op
) != SYMBOL_REF
)
1069 if (CONSTANT_POOL_ADDRESS_P (op
))
1070 return GET_MODE_SIZE (get_pool_mode (op
)) <= (unsigned) g_switch_value
;
1074 return str
[0] == '@' && str
[1] == 'S';
1078 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1079 not known (or known not) to be defined in this file. */
1082 global_symbolic_operand (op
, mode
)
1084 enum machine_mode mode
;
1088 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1091 if (GET_CODE (op
) == CONST
1092 && GET_CODE (XEXP (op
, 0)) == PLUS
1093 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1094 op
= XEXP (XEXP (op
, 0), 0);
1096 if (GET_CODE (op
) != SYMBOL_REF
)
1099 if (local_symbolic_operand (op
, mode
))
1102 /* Also verify that it's not a TLS symbol. */
1104 return str
[0] != '%' && str
[0] != '@';
1107 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
1110 call_operand (op
, mode
)
1112 enum machine_mode mode
;
1117 if (GET_CODE (op
) == REG
)
1121 /* Disallow virtual registers to cope with pathalogical test cases
1122 such as compile/930117-1.c in which the virtual reg decomposes
1123 to the frame pointer. Which is a hard reg that is not $27. */
1124 return (REGNO (op
) == 27 || REGNO (op
) > LAST_VIRTUAL_REGISTER
);
1129 if (TARGET_ABI_UNICOSMK
)
1131 if (GET_CODE (op
) == SYMBOL_REF
)
1137 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1138 possibly with an offset. */
1141 symbolic_operand (op
, mode
)
1143 enum machine_mode mode
;
1145 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1147 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1149 if (GET_CODE (op
) == CONST
1150 && GET_CODE (XEXP (op
,0)) == PLUS
1151 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1152 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1157 /* Return true if OP is valid for a particular TLS relocation. */
1160 tls_symbolic_operand_1 (op
, mode
, size
, unspec
)
1162 enum machine_mode mode
;
1168 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1171 if (GET_CODE (op
) != CONST
)
1175 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
1177 op
= XVECEXP (op
, 0, 0);
1179 if (GET_CODE (op
) != SYMBOL_REF
)
1188 else if (str
[0] == '@')
1190 if (alpha_tls_size
> size
)
1196 letter
= (unspec
== UNSPEC_DTPREL
? 'D' : 'T');
1198 return str
[1] == letter
;
1201 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1204 dtp16_symbolic_operand (op
, mode
)
1206 enum machine_mode mode
;
1208 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_DTPREL
);
1211 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1214 dtp32_symbolic_operand (op
, mode
)
1216 enum machine_mode mode
;
1218 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_DTPREL
);
1221 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1224 gotdtp_symbolic_operand (op
, mode
)
1226 enum machine_mode mode
;
1228 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_DTPREL
);
1231 /* Return true if OP is valid for 16-bit TP relative relocations. */
1234 tp16_symbolic_operand (op
, mode
)
1236 enum machine_mode mode
;
1238 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_TPREL
);
1241 /* Return true if OP is valid for 32-bit TP relative relocations. */
1244 tp32_symbolic_operand (op
, mode
)
1246 enum machine_mode mode
;
1248 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_TPREL
);
1251 /* Return true if OP is valid for 64-bit TP relative relocations. */
1254 gottp_symbolic_operand (op
, mode
)
1256 enum machine_mode mode
;
1258 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_TPREL
);
1261 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1262 comparisons are valid in which insn. */
1265 alpha_comparison_operator (op
, mode
)
1267 enum machine_mode mode
;
1269 enum rtx_code code
= GET_CODE (op
);
1271 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1274 return (code
== EQ
|| code
== LE
|| code
== LT
1275 || code
== LEU
|| code
== LTU
);
1278 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1279 Here we know which comparisons are valid in which insn. */
1282 alpha_zero_comparison_operator (op
, mode
)
1284 enum machine_mode mode
;
1286 enum rtx_code code
= GET_CODE (op
);
1288 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1291 return (code
== EQ
|| code
== NE
|| code
== LE
|| code
== LT
1292 || code
== LEU
|| code
== LTU
);
1295 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1298 alpha_swapped_comparison_operator (op
, mode
)
1300 enum machine_mode mode
;
1302 enum rtx_code code
= GET_CODE (op
);
1304 if ((mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1305 || GET_RTX_CLASS (code
) != '<')
1308 code
= swap_condition (code
);
1309 return (code
== EQ
|| code
== LE
|| code
== LT
1310 || code
== LEU
|| code
== LTU
);
1313 /* Return 1 if OP is a signed comparison operation. */
1316 signed_comparison_operator (op
, mode
)
1318 enum machine_mode mode ATTRIBUTE_UNUSED
;
1320 enum rtx_code code
= GET_CODE (op
);
1322 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1325 return (code
== EQ
|| code
== NE
1326 || code
== LE
|| code
== LT
1327 || code
== GE
|| code
== GT
);
1330 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1331 Here we know which comparisons are valid in which insn. */
1334 alpha_fp_comparison_operator (op
, mode
)
1336 enum machine_mode mode
;
1338 enum rtx_code code
= GET_CODE (op
);
1340 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1343 return (code
== EQ
|| code
== LE
|| code
== LT
|| code
== UNORDERED
);
1346 /* Return 1 if this is a divide or modulus operator. */
1349 divmod_operator (op
, mode
)
1351 enum machine_mode mode ATTRIBUTE_UNUSED
;
1353 switch (GET_CODE (op
))
1355 case DIV
: case MOD
: case UDIV
: case UMOD
:
1365 /* Return 1 if this memory address is a known aligned register plus
1366 a constant. It must be a valid address. This means that we can do
1367 this as an aligned reference plus some offset.
1369 Take into account what reload will do. */
1372 aligned_memory_operand (op
, mode
)
1374 enum machine_mode mode
;
1378 if (reload_in_progress
)
1381 if (GET_CODE (tmp
) == SUBREG
)
1382 tmp
= SUBREG_REG (tmp
);
1383 if (GET_CODE (tmp
) == REG
1384 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1386 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1392 if (GET_CODE (op
) != MEM
1393 || GET_MODE (op
) != mode
)
1397 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1398 sorts of constructs. Dig for the real base register. */
1399 if (reload_in_progress
1400 && GET_CODE (op
) == PLUS
1401 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1402 base
= XEXP (XEXP (op
, 0), 0);
1405 if (! memory_address_p (mode
, op
))
1407 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1410 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) >= 32);
1413 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1416 unaligned_memory_operand (op
, mode
)
1418 enum machine_mode mode
;
1422 if (reload_in_progress
)
1425 if (GET_CODE (tmp
) == SUBREG
)
1426 tmp
= SUBREG_REG (tmp
);
1427 if (GET_CODE (tmp
) == REG
1428 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1430 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1436 if (GET_CODE (op
) != MEM
1437 || GET_MODE (op
) != mode
)
1441 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1442 sorts of constructs. Dig for the real base register. */
1443 if (reload_in_progress
1444 && GET_CODE (op
) == PLUS
1445 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1446 base
= XEXP (XEXP (op
, 0), 0);
1449 if (! memory_address_p (mode
, op
))
1451 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1454 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) < 32);
1457 /* Return 1 if OP is either a register or an unaligned memory location. */
1460 reg_or_unaligned_mem_operand (op
, mode
)
1462 enum machine_mode mode
;
1464 return register_operand (op
, mode
) || unaligned_memory_operand (op
, mode
);
1467 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1470 any_memory_operand (op
, mode
)
1472 enum machine_mode mode ATTRIBUTE_UNUSED
;
1474 return (GET_CODE (op
) == MEM
1475 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
1476 || (reload_in_progress
&& GET_CODE (op
) == REG
1477 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1478 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
1479 && GET_CODE (SUBREG_REG (op
)) == REG
1480 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
1483 /* Returns 1 if OP is not an eliminable register.
1485 This exists to cure a pathological abort in the s8addq (et al) patterns,
1487 long foo () { long t; bar(); return (long) &t * 26107; }
1489 which run afoul of a hack in reload to cure a (presumably) similar
1490 problem with lea-type instructions on other targets. But there is
1491 one of us and many of them, so work around the problem by selectively
1492 preventing combine from making the optimization. */
1495 reg_not_elim_operand (op
, mode
)
1497 enum machine_mode mode
;
1500 if (GET_CODE (op
) == SUBREG
)
1501 inner
= SUBREG_REG (op
);
1502 if (inner
== frame_pointer_rtx
|| inner
== arg_pointer_rtx
)
1505 return register_operand (op
, mode
);
1508 /* Return 1 is OP is a memory location that is not a reference (using
1509 an AND) to an unaligned location. Take into account what reload
1513 normal_memory_operand (op
, mode
)
1515 enum machine_mode mode ATTRIBUTE_UNUSED
;
1517 if (reload_in_progress
)
1520 if (GET_CODE (tmp
) == SUBREG
)
1521 tmp
= SUBREG_REG (tmp
);
1522 if (GET_CODE (tmp
) == REG
1523 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1525 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1527 /* This may not have been assigned an equivalent address if it will
1528 be eliminated. In that case, it doesn't matter what we do. */
1534 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) != AND
;
1537 /* Accept a register, but not a subreg of any kind. This allows us to
1538 avoid pathological cases in reload wrt data movement common in
1539 int->fp conversion. */
1542 reg_no_subreg_operand (op
, mode
)
1544 enum machine_mode mode
;
1546 if (GET_CODE (op
) != REG
)
1548 return register_operand (op
, mode
);
1551 /* Recognize an addition operation that includes a constant. Used to
1552 convince reload to canonize (plus (plus reg c1) c2) during register
1556 addition_operation (op
, mode
)
1558 enum machine_mode mode
;
1560 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1562 if (GET_CODE (op
) == PLUS
1563 && register_operand (XEXP (op
, 0), mode
)
1564 && GET_CODE (XEXP (op
, 1)) == CONST_INT
1565 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op
, 1)), 'K'))
1570 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1571 the range defined for C in [I-P]. */
1574 alpha_const_ok_for_letter_p (value
, c
)
1575 HOST_WIDE_INT value
;
1581 /* An unsigned 8 bit constant. */
1582 return (unsigned HOST_WIDE_INT
) value
< 0x100;
1584 /* The constant zero. */
1587 /* A signed 16 bit constant. */
1588 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
1590 /* A shifted signed 16 bit constant appropriate for LDAH. */
1591 return ((value
& 0xffff) == 0
1592 && ((value
) >> 31 == -1 || value
>> 31 == 0));
1594 /* A constant that can be AND'ed with using a ZAP insn. */
1595 return zap_mask (value
);
1597 /* A complemented unsigned 8 bit constant. */
1598 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
1600 /* A negated unsigned 8 bit constant. */
1601 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
1603 /* The constant 1, 2 or 3. */
1604 return value
== 1 || value
== 2 || value
== 3;
1611 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1612 matches for C in [GH]. */
1615 alpha_const_double_ok_for_letter_p (value
, c
)
1622 /* The floating point zero constant. */
1623 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
1624 && value
== CONST0_RTX (GET_MODE (value
)));
1627 /* A valid operand of a ZAP insn. */
1628 return (GET_MODE (value
) == VOIDmode
1629 && zap_mask (CONST_DOUBLE_LOW (value
))
1630 && zap_mask (CONST_DOUBLE_HIGH (value
)));
1637 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1641 alpha_extra_constraint (value
, c
)
1648 return normal_memory_operand (value
, VOIDmode
);
1650 return direct_call_operand (value
, Pmode
);
1652 return (GET_CODE (value
) == CONST_INT
1653 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
1655 return GET_CODE (value
) == HIGH
;
1657 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
1659 return (GET_CODE (value
) == CONST_VECTOR
1660 && value
== CONST0_RTX (GET_MODE (value
)));
1666 /* Return 1 if this function can directly return via $26. */
1671 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
1673 && alpha_sa_size () == 0
1674 && get_frame_size () == 0
1675 && current_function_outgoing_args_size
== 0
1676 && current_function_pretend_args_size
== 0);
1679 /* Return the ADDR_VEC associated with a tablejump insn. */
1682 alpha_tablejump_addr_vec (insn
)
1687 tmp
= JUMP_LABEL (insn
);
1690 tmp
= NEXT_INSN (tmp
);
1693 if (GET_CODE (tmp
) == JUMP_INSN
1694 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
1695 return PATTERN (tmp
);
1699 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1702 alpha_tablejump_best_label (insn
)
1705 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
1706 rtx best_label
= NULL_RTX
;
1708 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1709 there for edge frequency counts from profile data. */
1713 int n_labels
= XVECLEN (jump_table
, 1);
1714 int best_count
= -1;
1717 for (i
= 0; i
< n_labels
; i
++)
1721 for (j
= i
+ 1; j
< n_labels
; j
++)
1722 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
1723 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
1726 if (count
> best_count
)
1727 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
1731 return best_label
? best_label
: const0_rtx
;
1734 /* Return the TLS model to use for SYMBOL. */
1736 static enum tls_model
1737 tls_symbolic_operand_type (symbol
)
1742 if (GET_CODE (symbol
) != SYMBOL_REF
)
1744 str
= XSTR (symbol
, 0);
1748 /* ??? Be prepared for -ftls-model=local-dynamic. Perhaps we shouldn't
1749 have separately encoded local-ness. On well, maybe the user will use
1750 attribute visibility next time. At least we don't crash... */
1751 if (str
[1] == 'G' || str
[1] == 'D')
1752 return TLS_MODEL_GLOBAL_DYNAMIC
;
1754 return TLS_MODEL_INITIAL_EXEC
;
1756 else if (str
[0] == '@')
1760 /* Local dynamic is a waste if we're not going to combine
1761 the __tls_get_addr calls. So avoid it if not optimizing. */
1763 return TLS_MODEL_LOCAL_DYNAMIC
;
1765 return TLS_MODEL_GLOBAL_DYNAMIC
;
1769 /* 64-bit local exec is the same as initial exec except without
1770 the dynamic relocation. In either case we use a got entry. */
1771 if (alpha_tls_size
== 64)
1772 return TLS_MODEL_INITIAL_EXEC
;
1774 return TLS_MODEL_LOCAL_EXEC
;
1782 /* Return true if the function DECL will be placed in the default text
1784 /* ??? Ideally we'd be able to always move from a SYMBOL_REF back to the
1785 decl, as that would allow us to determine if two functions are in the
1786 same section, which is what we really want to know. */
1789 decl_in_text_section (decl
)
1792 return (DECL_SECTION_NAME (decl
) == NULL_TREE
1793 && ! (flag_function_sections
1794 || (targetm
.have_named_sections
1795 && DECL_ONE_ONLY (decl
))));
1798 /* Return true if EXP should be placed in the small data section. */
1801 alpha_in_small_data_p (exp
)
1804 /* We want to merge strings, so we never consider them small data. */
1805 if (TREE_CODE (exp
) == STRING_CST
)
1808 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
1810 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
1811 if (strcmp (section
, ".sdata") == 0
1812 || strcmp (section
, ".sbss") == 0)
1817 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
1819 /* If this is an incomplete type with size 0, then we can't put it
1820 in sdata because it might be too big when completed. */
1821 if (size
> 0 && size
<= g_switch_value
)
1828 /* If we are referencing a function that is static, make the SYMBOL_REF
1829 special. We use this to see indicate we can branch to this function
1830 without setting PV or restoring GP.
1832 If this is a variable that is known to be defined locally, add "@v"
1833 to the name. If in addition the variable is to go in .sdata/.sbss,
1834 then add "@s" instead. */
1837 alpha_encode_section_info (decl
, first
)
1839 int first ATTRIBUTE_UNUSED
;
1841 const char *symbol_str
;
1846 rtl
= DECL_P (decl
) ? DECL_RTL (decl
) : TREE_CST_RTL (decl
);
1848 /* Careful not to prod global register variables. */
1849 if (GET_CODE (rtl
) != MEM
)
1851 symbol
= XEXP (rtl
, 0);
1852 if (GET_CODE (symbol
) != SYMBOL_REF
)
1855 if (TREE_CODE (decl
) == FUNCTION_DECL
)
1857 /* We mark public functions once they are emitted; otherwise we
1858 don't know that they exist in this unit of translation. */
1859 if (TREE_PUBLIC (decl
))
1862 /* Do not mark functions that are not in .text; otherwise we
1863 don't know that they are near enough for a direct branch. */
1864 if (! decl_in_text_section (decl
))
1867 SYMBOL_REF_FLAG (symbol
) = 1;
1871 /* Early out if we're not going to do anything with this data. */
1872 if (! TARGET_EXPLICIT_RELOCS
)
1875 symbol_str
= XSTR (symbol
, 0);
1877 /* A variable is considered "local" if it is defined in this module. */
1878 is_local
= (*targetm
.binds_local_p
) (decl
);
1880 /* Care for TLS variables. */
1881 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL (decl
))
1883 enum tls_model kind
;
1887 kind
= TLS_MODEL_LOCAL_EXEC
;
1889 kind
= TLS_MODEL_INITIAL_EXEC
;
1892 kind
= TLS_MODEL_LOCAL_DYNAMIC
;
1894 kind
= TLS_MODEL_GLOBAL_DYNAMIC
;
1895 if (kind
< flag_tls_default
)
1896 kind
= flag_tls_default
;
1900 case TLS_MODEL_GLOBAL_DYNAMIC
:
1903 case TLS_MODEL_LOCAL_DYNAMIC
:
1906 case TLS_MODEL_INITIAL_EXEC
:
1907 case TLS_MODEL_LOCAL_EXEC
:
1914 /* Determine if DECL will wind up in .sdata/.sbss. */
1915 if (alpha_in_small_data_p (decl
))
1921 /* Finally, encode this into the symbol string. */
1927 if (symbol_str
[0] == (is_local
? '@' : '%'))
1929 if (symbol_str
[1] == encoding
)
1934 len
= strlen (symbol_str
) + 1;
1935 newstr
= alloca (len
+ 2);
1937 newstr
[0] = (is_local
? '@' : '%');
1938 newstr
[1] = encoding
;
1939 memcpy (newstr
+ 2, symbol_str
, len
);
1941 XSTR (symbol
, 0) = ggc_alloc_string (newstr
, len
+ 2 - 1);
1945 /* Undo the effects of the above. */
1948 alpha_strip_name_encoding (str
)
1951 if (str
[0] == '@' || str
[0] == '%')
1958 #if TARGET_ABI_OPEN_VMS
1960 alpha_linkage_symbol_p (symname
)
1961 const char *symname
;
1963 int symlen
= strlen (symname
);
1966 return strcmp (&symname
[symlen
- 4], "..lk") == 0;
1971 #define LINKAGE_SYMBOL_REF_P(X) \
1972 ((GET_CODE (X) == SYMBOL_REF \
1973 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1974 || (GET_CODE (X) == CONST \
1975 && GET_CODE (XEXP (X, 0)) == PLUS \
1976 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1977 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1980 /* legitimate_address_p recognizes an RTL expression that is a valid
1981 memory address for an instruction. The MODE argument is the
1982 machine mode for the MEM expression that wants to use this address.
1984 For Alpha, we have either a constant address or the sum of a
1985 register and a constant address, or just a register. For DImode,
1986 any of those forms can be surrounded with an AND that clear the
1987 low-order three bits; this is an "unaligned" access. */
1990 alpha_legitimate_address_p (mode
, x
, strict
)
1991 enum machine_mode mode
;
1995 /* If this is an ldq_u type address, discard the outer AND. */
1997 && GET_CODE (x
) == AND
1998 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1999 && INTVAL (XEXP (x
, 1)) == -8)
2002 /* Discard non-paradoxical subregs. */
2003 if (GET_CODE (x
) == SUBREG
2004 && (GET_MODE_SIZE (GET_MODE (x
))
2005 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2008 /* Unadorned general registers are valid. */
2011 ? STRICT_REG_OK_FOR_BASE_P (x
)
2012 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
2015 /* Constant addresses (i.e. +/- 32k) are valid. */
2016 if (CONSTANT_ADDRESS_P (x
))
2019 #if TARGET_ABI_OPEN_VMS
2020 if (LINKAGE_SYMBOL_REF_P (x
))
2024 /* Register plus a small constant offset is valid. */
2025 if (GET_CODE (x
) == PLUS
)
2027 rtx ofs
= XEXP (x
, 1);
2030 /* Discard non-paradoxical subregs. */
2031 if (GET_CODE (x
) == SUBREG
2032 && (GET_MODE_SIZE (GET_MODE (x
))
2033 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2039 && NONSTRICT_REG_OK_FP_BASE_P (x
)
2040 && GET_CODE (ofs
) == CONST_INT
)
2043 ? STRICT_REG_OK_FOR_BASE_P (x
)
2044 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
2045 && CONSTANT_ADDRESS_P (ofs
))
2048 else if (GET_CODE (x
) == ADDRESSOF
2049 && GET_CODE (ofs
) == CONST_INT
)
2053 /* If we're managing explicit relocations, LO_SUM is valid, as
2054 are small data symbols. */
2055 else if (TARGET_EXPLICIT_RELOCS
)
2057 if (small_symbolic_operand (x
, Pmode
))
2060 if (GET_CODE (x
) == LO_SUM
)
2062 rtx ofs
= XEXP (x
, 1);
2065 /* Discard non-paradoxical subregs. */
2066 if (GET_CODE (x
) == SUBREG
2067 && (GET_MODE_SIZE (GET_MODE (x
))
2068 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2071 /* Must have a valid base register. */
2074 ? STRICT_REG_OK_FOR_BASE_P (x
)
2075 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
2078 /* The symbol must be local. */
2079 if (local_symbolic_operand (ofs
, Pmode
)
2080 || dtp32_symbolic_operand (ofs
, Pmode
)
2081 || tp32_symbolic_operand (ofs
, Pmode
))
2089 /* Try machine-dependent ways of modifying an illegitimate address
2090 to be legitimate. If we find one, return the new, valid address. */
2093 alpha_legitimize_address (x
, scratch
, mode
)
2096 enum machine_mode mode ATTRIBUTE_UNUSED
;
2098 HOST_WIDE_INT addend
;
2100 /* If the address is (plus reg const_int) and the CONST_INT is not a
2101 valid offset, compute the high part of the constant and add it to
2102 the register. Then our address is (plus temp low-part-const). */
2103 if (GET_CODE (x
) == PLUS
2104 && GET_CODE (XEXP (x
, 0)) == REG
2105 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2106 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
2108 addend
= INTVAL (XEXP (x
, 1));
2113 /* If the address is (const (plus FOO const_int)), find the low-order
2114 part of the CONST_INT. Then load FOO plus any high-order part of the
2115 CONST_INT into a register. Our address is (plus reg low-part-const).
2116 This is done to reduce the number of GOT entries. */
2118 && GET_CODE (x
) == CONST
2119 && GET_CODE (XEXP (x
, 0)) == PLUS
2120 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2122 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
2123 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
2127 /* If we have a (plus reg const), emit the load as in (2), then add
2128 the two registers, and finally generate (plus reg low-part-const) as
2131 && GET_CODE (x
) == PLUS
2132 && GET_CODE (XEXP (x
, 0)) == REG
2133 && GET_CODE (XEXP (x
, 1)) == CONST
2134 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
2135 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
2137 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
2138 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
2139 XEXP (XEXP (XEXP (x
, 1), 0), 0),
2140 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
2144 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
2145 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
2147 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
2149 switch (tls_symbolic_operand_type (x
))
2151 case TLS_MODEL_GLOBAL_DYNAMIC
:
2154 r0
= gen_rtx_REG (Pmode
, 0);
2155 r16
= gen_rtx_REG (Pmode
, 16);
2156 tga
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
2157 dest
= gen_reg_rtx (Pmode
);
2158 seq
= GEN_INT (alpha_next_sequence_number
++);
2160 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
2161 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
2162 insn
= emit_call_insn (insn
);
2163 CONST_OR_PURE_CALL_P (insn
) = 1;
2164 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2166 insn
= get_insns ();
2169 emit_libcall_block (insn
, dest
, r0
, x
);
2172 case TLS_MODEL_LOCAL_DYNAMIC
:
2175 r0
= gen_rtx_REG (Pmode
, 0);
2176 r16
= gen_rtx_REG (Pmode
, 16);
2177 tga
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
2178 scratch
= gen_reg_rtx (Pmode
);
2179 seq
= GEN_INT (alpha_next_sequence_number
++);
2181 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
2182 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
2183 insn
= emit_call_insn (insn
);
2184 CONST_OR_PURE_CALL_P (insn
) = 1;
2185 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2187 insn
= get_insns ();
2190 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2191 UNSPEC_TLSLDM_CALL
);
2192 emit_libcall_block (insn
, scratch
, r0
, eqv
);
2194 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
2195 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2197 if (alpha_tls_size
== 64)
2199 dest
= gen_reg_rtx (Pmode
);
2200 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
2201 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
2204 if (alpha_tls_size
== 32)
2206 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2207 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
2208 scratch
= gen_reg_rtx (Pmode
);
2209 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
2211 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
2213 case TLS_MODEL_INITIAL_EXEC
:
2214 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2215 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2216 tp
= gen_reg_rtx (Pmode
);
2217 scratch
= gen_reg_rtx (Pmode
);
2218 dest
= gen_reg_rtx (Pmode
);
2220 emit_insn (gen_load_tp (tp
));
2221 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
2222 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
2225 case TLS_MODEL_LOCAL_EXEC
:
2226 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2227 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2228 tp
= gen_reg_rtx (Pmode
);
2230 emit_insn (gen_load_tp (tp
));
2231 if (alpha_tls_size
== 32)
2233 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2234 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
2235 tp
= gen_reg_rtx (Pmode
);
2236 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
2238 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
2241 if (local_symbolic_operand (x
, Pmode
))
2243 if (small_symbolic_operand (x
, Pmode
))
2247 if (!no_new_pseudos
)
2248 scratch
= gen_reg_rtx (Pmode
);
2249 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
2250 gen_rtx_HIGH (Pmode
, x
)));
2251 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
2260 HOST_WIDE_INT low
, high
;
2262 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
2264 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2268 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
2269 (no_new_pseudos
? scratch
: NULL_RTX
),
2270 1, OPTAB_LIB_WIDEN
);
2272 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
2273 (no_new_pseudos
? scratch
: NULL_RTX
),
2274 1, OPTAB_LIB_WIDEN
);
2276 return plus_constant (x
, low
);
2280 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
2281 small symbolic operand until after reload. At which point we need
2282 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
2283 so that sched2 has the proper dependency information. */
2286 some_small_symbolic_operand (x
, mode
)
2288 enum machine_mode mode ATTRIBUTE_UNUSED
;
2290 return for_each_rtx (&x
, some_small_symbolic_operand_1
, NULL
);
2294 some_small_symbolic_operand_1 (px
, data
)
2296 void *data ATTRIBUTE_UNUSED
;
2300 /* Don't re-split. */
2301 if (GET_CODE (x
) == LO_SUM
)
2304 return small_symbolic_operand (x
, Pmode
) != 0;
2308 split_small_symbolic_operand (x
)
2312 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
2317 split_small_symbolic_operand_1 (px
, data
)
2319 void *data ATTRIBUTE_UNUSED
;
2323 /* Don't re-split. */
2324 if (GET_CODE (x
) == LO_SUM
)
2327 if (small_symbolic_operand (x
, Pmode
))
2329 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
2337 /* Try a machine-dependent way of reloading an illegitimate address
2338 operand. If we find one, push the reload and return the new rtx. */
2341 alpha_legitimize_reload_address (x
, mode
, opnum
, type
, ind_levels
)
2343 enum machine_mode mode ATTRIBUTE_UNUSED
;
2346 int ind_levels ATTRIBUTE_UNUSED
;
2348 /* We must recognize output that we have already generated ourselves. */
2349 if (GET_CODE (x
) == PLUS
2350 && GET_CODE (XEXP (x
, 0)) == PLUS
2351 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2352 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2353 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2355 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2356 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2361 /* We wish to handle large displacements off a base register by
2362 splitting the addend across an ldah and the mem insn. This
2363 cuts number of extra insns needed from 3 to 1. */
2364 if (GET_CODE (x
) == PLUS
2365 && GET_CODE (XEXP (x
, 0)) == REG
2366 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2367 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
2368 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2370 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2371 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
2373 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2375 /* Check for 32-bit overflow. */
2376 if (high
+ low
!= val
)
2379 /* Reload the high part into a base reg; leave the low part
2380 in the mem directly. */
2381 x
= gen_rtx_PLUS (GET_MODE (x
),
2382 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
2386 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2387 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2395 /* REF is an alignable memory location. Place an aligned SImode
2396 reference into *PALIGNED_MEM and the number of bits to shift into
2397 *PBITNUM. SCRATCH is a free register for use in reloading out
2398 of range stack slots. */
2401 get_aligned_mem (ref
, paligned_mem
, pbitnum
)
2403 rtx
*paligned_mem
, *pbitnum
;
2406 HOST_WIDE_INT offset
= 0;
2408 if (GET_CODE (ref
) != MEM
)
2411 if (reload_in_progress
2412 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2414 base
= find_replacement (&XEXP (ref
, 0));
2416 if (! memory_address_p (GET_MODE (ref
), base
))
2421 base
= XEXP (ref
, 0);
2424 if (GET_CODE (base
) == PLUS
)
2425 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2428 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
2430 if (WORDS_BIG_ENDIAN
)
2431 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
2432 + (offset
& 3) * 8));
2434 *pbitnum
= GEN_INT ((offset
& 3) * 8);
2437 /* Similar, but just get the address. Handle the two reload cases.
2438 Add EXTRA_OFFSET to the address we return. */
2441 get_unaligned_address (ref
, extra_offset
)
2446 HOST_WIDE_INT offset
= 0;
2448 if (GET_CODE (ref
) != MEM
)
2451 if (reload_in_progress
2452 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2454 base
= find_replacement (&XEXP (ref
, 0));
2456 if (! memory_address_p (GET_MODE (ref
), base
))
2461 base
= XEXP (ref
, 0);
2464 if (GET_CODE (base
) == PLUS
)
2465 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2467 return plus_constant (base
, offset
+ extra_offset
);
2470 /* On the Alpha, all (non-symbolic) constants except zero go into
2471 a floating-point register via memory. Note that we cannot
2472 return anything that is not a subset of CLASS, and that some
2473 symbolic constants cannot be dropped to memory. */
2476 alpha_preferred_reload_class(x
, class)
2478 enum reg_class
class;
2480 /* Zero is present in any register class. */
2481 if (x
== CONST0_RTX (GET_MODE (x
)))
2484 /* These sorts of constants we can easily drop to memory. */
2485 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2487 if (class == FLOAT_REGS
)
2489 if (class == ALL_REGS
)
2490 return GENERAL_REGS
;
2494 /* All other kinds of constants should not (and in the case of HIGH
2495 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2496 secondary reload. */
2498 return (class == ALL_REGS
? GENERAL_REGS
: class);
2503 /* Loading and storing HImode or QImode values to and from memory
2504 usually requires a scratch register. The exceptions are loading
2505 QImode and HImode from an aligned address to a general register
2506 unless byte instructions are permitted.
2508 We also cannot load an unaligned address or a paradoxical SUBREG
2509 into an FP register.
2511 We also cannot do integral arithmetic into FP regs, as might result
2512 from register elimination into a DImode fp register. */
2515 secondary_reload_class (class, mode
, x
, in
)
2516 enum reg_class
class;
2517 enum machine_mode mode
;
2521 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
2523 if (GET_CODE (x
) == MEM
2524 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
2525 || (GET_CODE (x
) == SUBREG
2526 && (GET_CODE (SUBREG_REG (x
)) == MEM
2527 || (GET_CODE (SUBREG_REG (x
)) == REG
2528 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
2530 if (!in
|| !aligned_memory_operand(x
, mode
))
2531 return GENERAL_REGS
;
2535 if (class == FLOAT_REGS
)
2537 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
2538 return GENERAL_REGS
;
2540 if (GET_CODE (x
) == SUBREG
2541 && (GET_MODE_SIZE (GET_MODE (x
))
2542 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2543 return GENERAL_REGS
;
2545 if (in
&& INTEGRAL_MODE_P (mode
)
2546 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
2547 return GENERAL_REGS
;
2553 /* Subfunction of the following function. Update the flags of any MEM
2554 found in part of X. */
2557 alpha_set_memflags_1 (x
, in_struct_p
, volatile_p
, unchanging_p
)
2559 int in_struct_p
, volatile_p
, unchanging_p
;
2563 switch (GET_CODE (x
))
2569 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2570 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
2575 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
2580 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
2582 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
2587 MEM_IN_STRUCT_P (x
) = in_struct_p
;
2588 MEM_VOLATILE_P (x
) = volatile_p
;
2589 RTX_UNCHANGING_P (x
) = unchanging_p
;
2590 /* Sadly, we cannot use alias sets because the extra aliasing
2591 produced by the AND interferes. Given that two-byte quantities
2592 are the only thing we would be able to differentiate anyway,
2593 there does not seem to be any point in convoluting the early
2594 out of the alias check. */
2602 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2603 generated to perform a memory operation, look for any MEMs in either
2604 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2605 volatile flags from REF into each of the MEMs found. If REF is not
2606 a MEM, don't do anything. */
2609 alpha_set_memflags (insn
, ref
)
2613 int in_struct_p
, volatile_p
, unchanging_p
;
2615 if (GET_CODE (ref
) != MEM
)
2618 in_struct_p
= MEM_IN_STRUCT_P (ref
);
2619 volatile_p
= MEM_VOLATILE_P (ref
);
2620 unchanging_p
= RTX_UNCHANGING_P (ref
);
2622 /* This is only called from alpha.md, after having had something
2623 generated from one of the insn patterns. So if everything is
2624 zero, the pattern is already up-to-date. */
2625 if (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
)
2628 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
2631 /* Try to output insns to set TARGET equal to the constant C if it can be
2632 done in less than N insns. Do all computations in MODE. Returns the place
2633 where the output has been placed if it can be done and the insns have been
2634 emitted. If it would take more than N insns, zero is returned and no
2635 insns and emitted. */
2638 alpha_emit_set_const (target
, mode
, c
, n
)
2640 enum machine_mode mode
;
2645 rtx orig_target
= target
;
2648 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2649 can't load this constant in one insn, do this in DImode. */
2650 if (no_new_pseudos
&& mode
== SImode
2651 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
2652 && (result
= alpha_emit_set_const_1 (target
, mode
, c
, 1)) == 0)
2654 target
= gen_lowpart (DImode
, target
);
2658 /* Try 1 insn, then 2, then up to N. */
2659 for (i
= 1; i
<= n
; i
++)
2661 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
);
2664 rtx insn
= get_last_insn ();
2665 rtx set
= single_set (insn
);
2666 if (! CONSTANT_P (SET_SRC (set
)))
2667 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
2672 /* Allow for the case where we changed the mode of TARGET. */
2673 if (result
== target
)
2674 result
= orig_target
;
2679 /* Internal routine for the above to check for N or below insns. */
2682 alpha_emit_set_const_1 (target
, mode
, c
, n
)
2684 enum machine_mode mode
;
2690 /* Use a pseudo if highly optimizing and still generating RTL. */
2692 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
2695 /* If this is a sign-extended 32-bit constant, we can do this in at most
2696 three insns, so do it if we have enough insns left. We always have
2697 a sign-extended 32-bit constant when compiling on a narrow machine. */
2699 if (HOST_BITS_PER_WIDE_INT
!= 64
2700 || c
>> 31 == -1 || c
>> 31 == 0)
2702 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
2703 HOST_WIDE_INT tmp1
= c
- low
;
2704 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
2705 HOST_WIDE_INT extra
= 0;
2707 /* If HIGH will be interpreted as negative but the constant is
2708 positive, we must adjust it to do two ldha insns. */
2710 if ((high
& 0x8000) != 0 && c
>= 0)
2714 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
2717 if (c
== low
|| (low
== 0 && extra
== 0))
2719 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2720 but that meant that we can't handle INT_MIN on 32-bit machines
2721 (like NT/Alpha), because we recurse indefinitely through
2722 emit_move_insn to gen_movdi. So instead, since we know exactly
2723 what we want, create it explicitly. */
2726 target
= gen_reg_rtx (mode
);
2727 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
2730 else if (n
>= 2 + (extra
!= 0))
2732 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16), subtarget
, mode
);
2734 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2735 This means that if we go through expand_binop, we'll try to
2736 generate extensions, etc, which will require new pseudos, which
2737 will fail during some split phases. The SImode add patterns
2738 still exist, but are not named. So build the insns by hand. */
2743 subtarget
= gen_reg_rtx (mode
);
2744 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
2745 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
2751 target
= gen_reg_rtx (mode
);
2752 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
2753 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
2759 /* If we couldn't do it that way, try some other methods. But if we have
2760 no instructions left, don't bother. Likewise, if this is SImode and
2761 we can't make pseudos, we can't do anything since the expand_binop
2762 and expand_unop calls will widen and try to make pseudos. */
2764 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
2767 /* Next, see if we can load a related constant and then shift and possibly
2768 negate it to get the constant we want. Try this once each increasing
2769 numbers of insns. */
2771 for (i
= 1; i
< n
; i
++)
2773 /* First, see if minus some low bits, we've an easy load of
2776 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
2778 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
2779 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
2780 target
, 0, OPTAB_WIDEN
);
2782 /* Next try complementing. */
2783 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
2784 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
2786 /* Next try to form a constant and do a left shift. We can do this
2787 if some low-order bits are zero; the exact_log2 call below tells
2788 us that information. The bits we are shifting out could be any
2789 value, but here we'll just try the 0- and sign-extended forms of
2790 the constant. To try to increase the chance of having the same
2791 constant in more than one insn, start at the highest number of
2792 bits to shift, but try all possibilities in case a ZAPNOT will
2795 if ((bits
= exact_log2 (c
& - c
)) > 0)
2796 for (; bits
> 0; bits
--)
2797 if ((temp
= (alpha_emit_set_const
2798 (subtarget
, mode
, c
>> bits
, i
))) != 0
2799 || ((temp
= (alpha_emit_set_const
2801 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
2803 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
2804 target
, 0, OPTAB_WIDEN
);
2806 /* Now try high-order zero bits. Here we try the shifted-in bits as
2807 all zero and all ones. Be careful to avoid shifting outside the
2808 mode and to avoid shifting outside the host wide int size. */
2809 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2810 confuse the recursive call and set all of the high 32 bits. */
2812 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2813 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
2814 for (; bits
> 0; bits
--)
2815 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2817 || ((temp
= (alpha_emit_set_const
2819 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2822 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
2823 target
, 1, OPTAB_WIDEN
);
2825 /* Now try high-order 1 bits. We get that with a sign-extension.
2826 But one bit isn't enough here. Be careful to avoid shifting outside
2827 the mode and to avoid shifting outside the host wide int size. */
2829 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2830 - floor_log2 (~ c
) - 2)) > 0)
2831 for (; bits
> 0; bits
--)
2832 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2834 || ((temp
= (alpha_emit_set_const
2836 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2839 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
2840 target
, 0, OPTAB_WIDEN
);
2843 #if HOST_BITS_PER_WIDE_INT == 64
2844 /* Finally, see if can load a value into the target that is the same as the
2845 constant except that all bytes that are 0 are changed to be 0xff. If we
2846 can, then we can do a ZAPNOT to obtain the desired constant. */
2849 for (i
= 0; i
< 64; i
+= 8)
2850 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
2851 new |= (HOST_WIDE_INT
) 0xff << i
;
2853 /* We are only called for SImode and DImode. If this is SImode, ensure that
2854 we are sign extended to a full word. */
2857 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2859 if (new != c
&& new != -1
2860 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
2861 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
2862 target
, 0, OPTAB_WIDEN
);
2868 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2869 fall back to a straight forward decomposition. We do this to avoid
2870 exponential run times encountered when looking for longer sequences
2871 with alpha_emit_set_const. */
2874 alpha_emit_set_long_const (target
, c1
, c2
)
2876 HOST_WIDE_INT c1
, c2
;
2878 HOST_WIDE_INT d1
, d2
, d3
, d4
;
2880 /* Decompose the entire word */
2881 #if HOST_BITS_PER_WIDE_INT >= 64
2882 if (c2
!= -(c1
< 0))
2884 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2886 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2887 c1
= (c1
- d2
) >> 32;
2888 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2890 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2894 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2896 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2900 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
2902 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2907 /* Construct the high word */
2910 emit_move_insn (target
, GEN_INT (d4
));
2912 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2915 emit_move_insn (target
, GEN_INT (d3
));
2917 /* Shift it into place */
2918 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2920 /* Add in the low bits. */
2922 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2924 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
2929 /* Expand a move instruction; return true if all work is done.
2930 We don't handle non-bwx subword loads here. */
2933 alpha_expand_mov (mode
, operands
)
2934 enum machine_mode mode
;
2937 /* If the output is not a register, the input must be. */
2938 if (GET_CODE (operands
[0]) == MEM
2939 && ! reg_or_0_operand (operands
[1], mode
))
2940 operands
[1] = force_reg (mode
, operands
[1]);
2942 /* Allow legitimize_address to perform some simplifications. */
2943 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2947 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2948 compiled at the end of compilation. In the meantime, someone can
2949 re-encode-section-info on some symbol changing it e.g. from global
2950 to local-not-small. If this happens, we'd have emitted a plain
2951 load rather than a high+losum load and not recognize the insn.
2953 So if rtl inlining is in effect, we delay the global/not-global
2954 decision until rest_of_compilation by wrapping it in an
2956 if (TARGET_EXPLICIT_RELOCS
&& flag_inline_functions
2957 && rtx_equal_function_value_matters
2958 && global_symbolic_operand (operands
[1], mode
))
2960 emit_insn (gen_movdi_er_maybe_g (operands
[0], operands
[1]));
2964 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
2967 if (tmp
== operands
[0])
2974 /* Early out for non-constants and valid constants. */
2975 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2978 /* Split large integers. */
2979 if (GET_CODE (operands
[1]) == CONST_INT
2980 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
2982 HOST_WIDE_INT i0
, i1
;
2983 rtx temp
= NULL_RTX
;
2985 if (GET_CODE (operands
[1]) == CONST_INT
)
2987 i0
= INTVAL (operands
[1]);
2990 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2992 i0
= CONST_DOUBLE_LOW (operands
[1]);
2997 i0
= CONST_DOUBLE_LOW (operands
[1]);
2998 i1
= CONST_DOUBLE_HIGH (operands
[1]);
3001 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
3002 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
3004 if (!temp
&& TARGET_BUILD_CONSTANTS
)
3005 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
3009 if (rtx_equal_p (operands
[0], temp
))
3016 /* Otherwise we've nothing left but to drop the thing to memory. */
3017 operands
[1] = force_const_mem (DImode
, operands
[1]);
3018 if (reload_in_progress
)
3020 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
3021 operands
[1] = copy_rtx (operands
[1]);
3022 XEXP (operands
[1], 0) = operands
[0];
3025 operands
[1] = validize_mem (operands
[1]);
3029 /* Expand a non-bwx QImode or HImode move instruction;
3030 return true if all work is done. */
3033 alpha_expand_mov_nobwx (mode
, operands
)
3034 enum machine_mode mode
;
3037 /* If the output is not a register, the input must be. */
3038 if (GET_CODE (operands
[0]) == MEM
)
3039 operands
[1] = force_reg (mode
, operands
[1]);
3041 /* Handle four memory cases, unaligned and aligned for either the input
3042 or the output. The only case where we can be called during reload is
3043 for aligned loads; all other cases require temporaries. */
3045 if (GET_CODE (operands
[1]) == MEM
3046 || (GET_CODE (operands
[1]) == SUBREG
3047 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
3048 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
3049 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
3050 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
3051 && GET_CODE (SUBREG_REG (operands
[1])) == REG
3052 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
3054 if (aligned_memory_operand (operands
[1], mode
))
3056 if (reload_in_progress
)
3058 emit_insn ((mode
== QImode
3059 ? gen_reload_inqi_help
3060 : gen_reload_inhi_help
)
3061 (operands
[0], operands
[1],
3062 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
3066 rtx aligned_mem
, bitnum
;
3067 rtx scratch
= gen_reg_rtx (SImode
);
3069 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
3071 emit_insn ((mode
== QImode
3072 ? gen_aligned_loadqi
3073 : gen_aligned_loadhi
)
3074 (operands
[0], aligned_mem
, bitnum
, scratch
));
3079 /* Don't pass these as parameters since that makes the generated
3080 code depend on parameter evaluation order which will cause
3081 bootstrap failures. */
3083 rtx temp1
= gen_reg_rtx (DImode
);
3084 rtx temp2
= gen_reg_rtx (DImode
);
3085 rtx seq
= ((mode
== QImode
3086 ? gen_unaligned_loadqi
3087 : gen_unaligned_loadhi
)
3088 (operands
[0], get_unaligned_address (operands
[1], 0),
3091 alpha_set_memflags (seq
, operands
[1]);
3097 if (GET_CODE (operands
[0]) == MEM
3098 || (GET_CODE (operands
[0]) == SUBREG
3099 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
3100 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
3101 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
3102 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
3103 && GET_CODE (SUBREG_REG (operands
[0])) == REG
3104 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
3106 if (aligned_memory_operand (operands
[0], mode
))
3108 rtx aligned_mem
, bitnum
;
3109 rtx temp1
= gen_reg_rtx (SImode
);
3110 rtx temp2
= gen_reg_rtx (SImode
);
3112 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
3114 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
3119 rtx temp1
= gen_reg_rtx (DImode
);
3120 rtx temp2
= gen_reg_rtx (DImode
);
3121 rtx temp3
= gen_reg_rtx (DImode
);
3122 rtx seq
= ((mode
== QImode
3123 ? gen_unaligned_storeqi
3124 : gen_unaligned_storehi
)
3125 (get_unaligned_address (operands
[0], 0),
3126 operands
[1], temp1
, temp2
, temp3
));
3128 alpha_set_memflags (seq
, operands
[0]);
3137 /* Generate an unsigned DImode to FP conversion. This is the same code
3138 optabs would emit if we didn't have TFmode patterns.
3140 For SFmode, this is the only construction I've found that can pass
3141 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
3142 intermediates will work, because you'll get intermediate rounding
3143 that ruins the end result. Some of this could be fixed by turning
3144 on round-to-positive-infinity, but that requires diddling the fpsr,
3145 which kills performance. I tried turning this around and converting
3146 to a negative number, so that I could turn on /m, but either I did
3147 it wrong or there's something else cause I wound up with the exact
3148 same single-bit error. There is a branch-less form of this same code:
3159 fcmoveq $f10,$f11,$f0
3161 I'm not using it because it's the same number of instructions as
3162 this branch-full form, and it has more serialized long latency
3163 instructions on the critical path.
3165 For DFmode, we can avoid rounding errors by breaking up the word
3166 into two pieces, converting them separately, and adding them back:
3168 LC0: .long 0,0x5f800000
3173 cpyse $f11,$f31,$f10
3174 cpyse $f31,$f11,$f11
3182 This doesn't seem to be a clear-cut win over the optabs form.
3183 It probably all depends on the distribution of numbers being
3184 converted -- in the optabs form, all but high-bit-set has a
3185 much lower minimum execution time. */
3188 alpha_emit_floatuns (operands
)
3191 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
3192 enum machine_mode mode
;
3195 in
= force_reg (DImode
, operands
[1]);
3196 mode
= GET_MODE (out
);
3197 neglab
= gen_label_rtx ();
3198 donelab
= gen_label_rtx ();
3199 i0
= gen_reg_rtx (DImode
);
3200 i1
= gen_reg_rtx (DImode
);
3201 f0
= gen_reg_rtx (mode
);
3203 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
3205 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
3206 emit_jump_insn (gen_jump (donelab
));
3209 emit_label (neglab
);
3211 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
3212 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
3213 emit_insn (gen_iordi3 (i0
, i0
, i1
));
3214 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
3215 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
3217 emit_label (donelab
);
3220 /* Generate the comparison for a conditional branch. */
3223 alpha_emit_conditional_branch (code
)
3226 enum rtx_code cmp_code
, branch_code
;
3227 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
3228 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3231 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
3233 if (! TARGET_HAS_XFLOATING_LIBS
)
3236 /* X_floating library comparison functions return
3240 Convert the compare against the raw return value. */
3262 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3264 alpha_compare
.fp_p
= 0;
3267 /* The general case: fold the comparison code to the types of compares
3268 that we have, choosing the branch as necessary. */
3271 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3273 /* We have these compares: */
3274 cmp_code
= code
, branch_code
= NE
;
3279 /* These must be reversed. */
3280 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
3283 case GE
: case GT
: case GEU
: case GTU
:
3284 /* For FP, we swap them, for INT, we reverse them. */
3285 if (alpha_compare
.fp_p
)
3287 cmp_code
= swap_condition (code
);
3289 tem
= op0
, op0
= op1
, op1
= tem
;
3293 cmp_code
= reverse_condition (code
);
3302 if (alpha_compare
.fp_p
)
3305 if (flag_unsafe_math_optimizations
)
3307 /* When we are not as concerned about non-finite values, and we
3308 are comparing against zero, we can branch directly. */
3309 if (op1
== CONST0_RTX (DFmode
))
3310 cmp_code
= NIL
, branch_code
= code
;
3311 else if (op0
== CONST0_RTX (DFmode
))
3313 /* Undo the swap we probably did just above. */
3314 tem
= op0
, op0
= op1
, op1
= tem
;
3315 branch_code
= swap_condition (cmp_code
);
3321 /* ??? We mark the branch mode to be CCmode to prevent the
3322 compare and branch from being combined, since the compare
3323 insn follows IEEE rules that the branch does not. */
3324 branch_mode
= CCmode
;
3331 /* The following optimizations are only for signed compares. */
3332 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
3334 /* Whee. Compare and branch against 0 directly. */
3335 if (op1
== const0_rtx
)
3336 cmp_code
= NIL
, branch_code
= code
;
3338 /* We want to use cmpcc/bcc when we can, since there is a zero delay
3339 bypass between logicals and br/cmov on EV5. But we don't want to
3340 force valid immediate constants into registers needlessly. */
3341 else if (GET_CODE (op1
) == CONST_INT
)
3343 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
3345 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
3346 && (CONST_OK_FOR_LETTER_P (n
, 'K')
3347 || CONST_OK_FOR_LETTER_P (n
, 'L')))
3349 cmp_code
= PLUS
, branch_code
= code
;
3355 if (!reg_or_0_operand (op0
, DImode
))
3356 op0
= force_reg (DImode
, op0
);
3357 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
3358 op1
= force_reg (DImode
, op1
);
3361 /* Emit an initial compare instruction, if necessary. */
3363 if (cmp_code
!= NIL
)
3365 tem
= gen_reg_rtx (cmp_mode
);
3366 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
3369 /* Zero the operands. */
3370 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3372 /* Return the branch comparison. */
3373 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
3376 /* Certain simplifications can be done to make invalid setcc operations
3377 valid. Return the final comparison, or NULL if we can't work. */
3380 alpha_emit_setcc (code
)
3383 enum rtx_code cmp_code
;
3384 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3385 int fp_p
= alpha_compare
.fp_p
;
3388 /* Zero the operands. */
3389 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3391 if (fp_p
&& GET_MODE (op0
) == TFmode
)
3393 if (! TARGET_HAS_XFLOATING_LIBS
)
3396 /* X_floating library comparison functions return
3400 Convert the compare against the raw return value. */
3402 if (code
== UNORDERED
|| code
== ORDERED
)
3407 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3411 if (code
== UNORDERED
)
3413 else if (code
== ORDERED
)
3419 if (fp_p
&& !TARGET_FIX
)
3422 /* The general case: fold the comparison code to the types of compares
3423 that we have, choosing the branch as necessary. */
3428 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3430 /* We have these compares. */
3432 cmp_code
= code
, code
= NE
;
3436 if (!fp_p
&& op1
== const0_rtx
)
3441 cmp_code
= reverse_condition (code
);
3445 case GE
: case GT
: case GEU
: case GTU
:
3446 /* These normally need swapping, but for integer zero we have
3447 special patterns that recognize swapped operands. */
3448 if (!fp_p
&& op1
== const0_rtx
)
3450 code
= swap_condition (code
);
3452 cmp_code
= code
, code
= NE
;
3453 tmp
= op0
, op0
= op1
, op1
= tmp
;
3462 if (!register_operand (op0
, DImode
))
3463 op0
= force_reg (DImode
, op0
);
3464 if (!reg_or_8bit_operand (op1
, DImode
))
3465 op1
= force_reg (DImode
, op1
);
3468 /* Emit an initial compare instruction, if necessary. */
3469 if (cmp_code
!= NIL
)
3471 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
3473 tmp
= gen_reg_rtx (mode
);
3474 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
3475 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
3477 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
3481 /* Return the setcc comparison. */
3482 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
3486 /* Rewrite a comparison against zero CMP of the form
3487 (CODE (cc0) (const_int 0)) so it can be written validly in
3488 a conditional move (if_then_else CMP ...).
3489 If both of the operands that set cc0 are nonzero we must emit
3490 an insn to perform the compare (it can't be done within
3491 the conditional move). */
3493 alpha_emit_conditional_move (cmp
, mode
)
3495 enum machine_mode mode
;
3497 enum rtx_code code
= GET_CODE (cmp
);
3498 enum rtx_code cmov_code
= NE
;
3499 rtx op0
= alpha_compare
.op0
;
3500 rtx op1
= alpha_compare
.op1
;
3501 int fp_p
= alpha_compare
.fp_p
;
3502 enum machine_mode cmp_mode
3503 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
3504 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
3505 enum machine_mode cmov_mode
= VOIDmode
;
3506 int local_fast_math
= flag_unsafe_math_optimizations
;
3509 /* Zero the operands. */
3510 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3512 if (fp_p
!= FLOAT_MODE_P (mode
))
3514 enum rtx_code cmp_code
;
3519 /* If we have fp<->int register move instructions, do a cmov by
3520 performing the comparison in fp registers, and move the
3521 zero/nonzero value to integer registers, where we can then
3522 use a normal cmov, or vice-versa. */
3526 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3527 /* We have these compares. */
3528 cmp_code
= code
, code
= NE
;
3532 /* This must be reversed. */
3533 cmp_code
= EQ
, code
= EQ
;
3536 case GE
: case GT
: case GEU
: case GTU
:
3537 /* These normally need swapping, but for integer zero we have
3538 special patterns that recognize swapped operands. */
3539 if (!fp_p
&& op1
== const0_rtx
)
3540 cmp_code
= code
, code
= NE
;
3543 cmp_code
= swap_condition (code
);
3545 tem
= op0
, op0
= op1
, op1
= tem
;
3553 tem
= gen_reg_rtx (cmp_op_mode
);
3554 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
3555 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
3558 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
3559 op0
= gen_lowpart (cmp_op_mode
, tem
);
3560 op1
= CONST0_RTX (cmp_op_mode
);
3562 local_fast_math
= 1;
3565 /* We may be able to use a conditional move directly.
3566 This avoids emitting spurious compares. */
3567 if (signed_comparison_operator (cmp
, VOIDmode
)
3568 && (!fp_p
|| local_fast_math
)
3569 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
3570 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3572 /* We can't put the comparison inside the conditional move;
3573 emit a compare instruction and put that inside the
3574 conditional move. Make sure we emit only comparisons we have;
3575 swap or reverse as necessary. */
3582 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3583 /* We have these compares: */
3587 /* This must be reversed. */
3588 code
= reverse_condition (code
);
3592 case GE
: case GT
: case GEU
: case GTU
:
3593 /* These must be swapped. */
3594 if (op1
!= CONST0_RTX (cmp_mode
))
3596 code
= swap_condition (code
);
3597 tem
= op0
, op0
= op1
, op1
= tem
;
3607 if (!reg_or_0_operand (op0
, DImode
))
3608 op0
= force_reg (DImode
, op0
);
3609 if (!reg_or_8bit_operand (op1
, DImode
))
3610 op1
= force_reg (DImode
, op1
);
3613 /* ??? We mark the branch mode to be CCmode to prevent the compare
3614 and cmov from being combined, since the compare insn follows IEEE
3615 rules that the cmov does not. */
3616 if (fp_p
&& !local_fast_math
)
3619 tem
= gen_reg_rtx (cmp_op_mode
);
3620 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
3621 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
3624 /* Simplify a conditional move of two constants into a setcc with
3625 arithmetic. This is done with a splitter since combine would
3626 just undo the work if done during code generation. It also catches
3627 cases we wouldn't have before cse. */
3630 alpha_split_conditional_move (code
, dest
, cond
, t_rtx
, f_rtx
)
3632 rtx dest
, cond
, t_rtx
, f_rtx
;
3634 HOST_WIDE_INT t
, f
, diff
;
3635 enum machine_mode mode
;
3636 rtx target
, subtarget
, tmp
;
3638 mode
= GET_MODE (dest
);
3643 if (((code
== NE
|| code
== EQ
) && diff
< 0)
3644 || (code
== GE
|| code
== GT
))
3646 code
= reverse_condition (code
);
3647 diff
= t
, t
= f
, f
= diff
;
3651 subtarget
= target
= dest
;
3654 target
= gen_lowpart (DImode
, dest
);
3655 if (! no_new_pseudos
)
3656 subtarget
= gen_reg_rtx (DImode
);
3660 /* Below, we must be careful to use copy_rtx on target and subtarget
3661 in intermediate insns, as they may be a subreg rtx, which may not
3664 if (f
== 0 && exact_log2 (diff
) > 0
3665 /* On EV6, we've got enough shifters to make non-arithmatic shifts
3666 viable over a longer latency cmove. On EV5, the E0 slot is a
3667 scarce resource, and on EV4 shift has the same latency as a cmove. */
3668 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
3670 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3671 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3673 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
3674 GEN_INT (exact_log2 (t
)));
3675 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3677 else if (f
== 0 && t
== -1)
3679 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3680 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3682 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
3684 else if (diff
== 1 || diff
== 4 || diff
== 8)
3688 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3689 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3692 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
3695 add_op
= GEN_INT (f
);
3696 if (sext_add_operand (add_op
, mode
))
3698 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
3700 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
3701 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3713 /* Look up the function X_floating library function name for the
3717 alpha_lookup_xfloating_lib_func (code
)
3722 const enum rtx_code code
;
3723 const char *const func
;
3726 static const struct xfloating_op vms_xfloating_ops
[] =
3728 { PLUS
, "OTS$ADD_X" },
3729 { MINUS
, "OTS$SUB_X" },
3730 { MULT
, "OTS$MUL_X" },
3731 { DIV
, "OTS$DIV_X" },
3732 { EQ
, "OTS$EQL_X" },
3733 { NE
, "OTS$NEQ_X" },
3734 { LT
, "OTS$LSS_X" },
3735 { LE
, "OTS$LEQ_X" },
3736 { GT
, "OTS$GTR_X" },
3737 { GE
, "OTS$GEQ_X" },
3738 { FIX
, "OTS$CVTXQ" },
3739 { FLOAT
, "OTS$CVTQX" },
3740 { UNSIGNED_FLOAT
, "OTS$CVTQUX" },
3741 { FLOAT_EXTEND
, "OTS$CVT_FLOAT_T_X" },
3742 { FLOAT_TRUNCATE
, "OTS$CVT_FLOAT_X_T" },
3745 static const struct xfloating_op osf_xfloating_ops
[] =
3747 { PLUS
, "_OtsAddX" },
3748 { MINUS
, "_OtsSubX" },
3749 { MULT
, "_OtsMulX" },
3750 { DIV
, "_OtsDivX" },
3757 { FIX
, "_OtsCvtXQ" },
3758 { FLOAT
, "_OtsCvtQX" },
3759 { UNSIGNED_FLOAT
, "_OtsCvtQUX" },
3760 { FLOAT_EXTEND
, "_OtsConvertFloatTX" },
3761 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT" },
3764 const struct xfloating_op
*ops
;
3765 const long n
= ARRAY_SIZE (osf_xfloating_ops
);
3768 /* How irritating. Nothing to key off for the table. Hardcode
3769 knowledge of the G_floating routines. */
3770 if (TARGET_FLOAT_VAX
)
3772 if (TARGET_ABI_OPEN_VMS
)
3774 if (code
== FLOAT_EXTEND
)
3775 return "OTS$CVT_FLOAT_G_X";
3776 if (code
== FLOAT_TRUNCATE
)
3777 return "OTS$CVT_FLOAT_X_G";
3781 if (code
== FLOAT_EXTEND
)
3782 return "_OtsConvertFloatGX";
3783 if (code
== FLOAT_TRUNCATE
)
3784 return "_OtsConvertFloatXG";
3788 if (TARGET_ABI_OPEN_VMS
)
3789 ops
= vms_xfloating_ops
;
3791 ops
= osf_xfloating_ops
;
3793 for (i
= 0; i
< n
; ++i
)
3794 if (ops
[i
].code
== code
)
3800 /* Most X_floating operations take the rounding mode as an argument.
3801 Compute that here. */
3804 alpha_compute_xfloating_mode_arg (code
, round
)
3806 enum alpha_fp_rounding_mode round
;
3812 case ALPHA_FPRM_NORM
:
3815 case ALPHA_FPRM_MINF
:
3818 case ALPHA_FPRM_CHOP
:
3821 case ALPHA_FPRM_DYN
:
3827 /* XXX For reference, round to +inf is mode = 3. */
3830 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3836 /* Emit an X_floating library function call.
3838 Note that these functions do not follow normal calling conventions:
3839 TFmode arguments are passed in two integer registers (as opposed to
3840 indirect); TFmode return values appear in R16+R17.
3842 FUNC is the function name to call.
3843 TARGET is where the output belongs.
3844 OPERANDS are the inputs.
3845 NOPERANDS is the count of inputs.
3846 EQUIV is the expression equivalent for the function.
3850 alpha_emit_xfloating_libcall (func
, target
, operands
, noperands
, equiv
)
3857 rtx usage
= NULL_RTX
, tmp
, reg
;
3862 for (i
= 0; i
< noperands
; ++i
)
3864 switch (GET_MODE (operands
[i
]))
3867 reg
= gen_rtx_REG (TFmode
, regno
);
3872 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3877 if (GET_CODE (operands
[i
]) != CONST_INT
)
3881 reg
= gen_rtx_REG (DImode
, regno
);
3889 emit_move_insn (reg
, operands
[i
]);
3890 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3893 switch (GET_MODE (target
))
3896 reg
= gen_rtx_REG (TFmode
, 16);
3899 reg
= gen_rtx_REG (DFmode
, 32);
3902 reg
= gen_rtx_REG (DImode
, 0);
3908 tmp
= gen_rtx_MEM (QImode
, gen_rtx_SYMBOL_REF (Pmode
, (char *) func
));
3909 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3910 const0_rtx
, const0_rtx
));
3911 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3916 emit_libcall_block (tmp
, target
, reg
, equiv
);
3919 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3922 alpha_emit_xfloating_arith (code
, operands
)
3928 rtx out_operands
[3];
3930 func
= alpha_lookup_xfloating_lib_func (code
);
3931 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3933 out_operands
[0] = operands
[1];
3934 out_operands
[1] = operands
[2];
3935 out_operands
[2] = GEN_INT (mode
);
3936 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
3937 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
3941 /* Emit an X_floating library function call for a comparison. */
3944 alpha_emit_xfloating_compare (code
, op0
, op1
)
3949 rtx out
, operands
[2];
3951 func
= alpha_lookup_xfloating_lib_func (code
);
3955 out
= gen_reg_rtx (DImode
);
3957 /* ??? Strange mode for equiv because what's actually returned
3958 is -1,0,1, not a proper boolean value. */
3959 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
3960 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
3965 /* Emit an X_floating library function call for a conversion. */
3968 alpha_emit_xfloating_cvt (code
, operands
)
3972 int noperands
= 1, mode
;
3973 rtx out_operands
[2];
3976 func
= alpha_lookup_xfloating_lib_func (code
);
3978 out_operands
[0] = operands
[1];
3983 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3984 out_operands
[1] = GEN_INT (mode
);
3987 case FLOAT_TRUNCATE
:
3988 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3989 out_operands
[1] = GEN_INT (mode
);
3996 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3997 gen_rtx_fmt_e (code
, GET_MODE (operands
[0]),
4001 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
4002 OP[0] into OP[0,1]. Naturally, output operand ordering is
4006 alpha_split_tfmode_pair (operands
)
4009 if (GET_CODE (operands
[1]) == REG
)
4011 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
4012 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
4014 else if (GET_CODE (operands
[1]) == MEM
)
4016 operands
[3] = adjust_address (operands
[1], DImode
, 8);
4017 operands
[2] = adjust_address (operands
[1], DImode
, 0);
4019 else if (operands
[1] == CONST0_RTX (TFmode
))
4020 operands
[2] = operands
[3] = const0_rtx
;
4024 if (GET_CODE (operands
[0]) == REG
)
4026 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
4027 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
4029 else if (GET_CODE (operands
[0]) == MEM
)
4031 operands
[1] = adjust_address (operands
[0], DImode
, 8);
4032 operands
[0] = adjust_address (operands
[0], DImode
, 0);
4038 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
4039 op2 is a register containing the sign bit, operation is the
4040 logical operation to be performed. */
4043 alpha_split_tfmode_frobsign (operands
, operation
)
4045 rtx (*operation
) PARAMS ((rtx
, rtx
, rtx
));
4047 rtx high_bit
= operands
[2];
4051 alpha_split_tfmode_pair (operands
);
4053 /* Detect three flavors of operand overlap. */
4055 if (rtx_equal_p (operands
[0], operands
[2]))
4057 else if (rtx_equal_p (operands
[1], operands
[2]))
4059 if (rtx_equal_p (operands
[0], high_bit
))
4066 emit_move_insn (operands
[0], operands
[2]);
4068 /* ??? If the destination overlaps both source tf and high_bit, then
4069 assume source tf is dead in its entirety and use the other half
4070 for a scratch register. Otherwise "scratch" is just the proper
4071 destination register. */
4072 scratch
= operands
[move
< 2 ? 1 : 3];
4074 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
4078 emit_move_insn (operands
[0], operands
[2]);
4080 emit_move_insn (operands
[1], scratch
);
4084 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
4088 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
4089 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
4090 lda r3,X(r11) lda r3,X+2(r11)
4091 extwl r1,r3,r1 extql r1,r3,r1
4092 extwh r2,r3,r2 extqh r2,r3,r2
4093 or r1.r2.r1 or r1,r2,r1
4096 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
4097 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
4098 lda r3,X(r11) lda r3,X(r11)
4099 extll r1,r3,r1 extll r1,r3,r1
4100 extlh r2,r3,r2 extlh r2,r3,r2
4101 or r1.r2.r1 addl r1,r2,r1
4103 quad: ldq_u r1,X(r11)
4112 alpha_expand_unaligned_load (tgt
, mem
, size
, ofs
, sign
)
4114 HOST_WIDE_INT size
, ofs
;
4117 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
4118 enum machine_mode mode
;
4120 meml
= gen_reg_rtx (DImode
);
4121 memh
= gen_reg_rtx (DImode
);
4122 addr
= gen_reg_rtx (DImode
);
4123 extl
= gen_reg_rtx (DImode
);
4124 exth
= gen_reg_rtx (DImode
);
4126 mema
= XEXP (mem
, 0);
4127 if (GET_CODE (mema
) == LO_SUM
)
4128 mema
= force_reg (Pmode
, mema
);
4130 /* AND addresses cannot be in any alias set, since they may implicitly
4131 alias surrounding code. Ideally we'd have some alias set that
4132 covered all types except those with alignment 8 or higher. */
4134 tmp
= change_address (mem
, DImode
,
4135 gen_rtx_AND (DImode
,
4136 plus_constant (mema
, ofs
),
4138 set_mem_alias_set (tmp
, 0);
4139 emit_move_insn (meml
, tmp
);
4141 tmp
= change_address (mem
, DImode
,
4142 gen_rtx_AND (DImode
,
4143 plus_constant (mema
, ofs
+ size
- 1),
4145 set_mem_alias_set (tmp
, 0);
4146 emit_move_insn (memh
, tmp
);
4148 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
4150 emit_move_insn (addr
, plus_constant (mema
, -1));
4152 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4153 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
4155 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4156 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
4157 addr
, 1, OPTAB_WIDEN
);
4159 else if (sign
&& size
== 2)
4161 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
4163 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
4164 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4166 /* We must use tgt here for the target. Alpha-vms port fails if we use
4167 addr for the target, because addr is marked as a pointer and combine
4168 knows that pointers are always sign-extended 32 bit values. */
4169 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4170 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
4171 addr
, 1, OPTAB_WIDEN
);
4175 if (WORDS_BIG_ENDIAN
)
4177 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
4181 emit_insn (gen_extwh_be (extl
, meml
, addr
));
4186 emit_insn (gen_extlh_be (extl
, meml
, addr
));
4191 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4198 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
4202 emit_move_insn (addr
, plus_constant (mema
, ofs
));
4203 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
4207 emit_insn (gen_extwh_le (exth
, memh
, addr
));
4212 emit_insn (gen_extlh_le (exth
, memh
, addr
));
4217 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4226 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
4227 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
4232 emit_move_insn (tgt
, gen_lowpart(GET_MODE (tgt
), addr
));
4235 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4238 alpha_expand_unaligned_store (dst
, src
, size
, ofs
)
4240 HOST_WIDE_INT size
, ofs
;
4242 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
4244 dstl
= gen_reg_rtx (DImode
);
4245 dsth
= gen_reg_rtx (DImode
);
4246 insl
= gen_reg_rtx (DImode
);
4247 insh
= gen_reg_rtx (DImode
);
4249 dsta
= XEXP (dst
, 0);
4250 if (GET_CODE (dsta
) == LO_SUM
)
4251 dsta
= force_reg (Pmode
, dsta
);
4253 /* AND addresses cannot be in any alias set, since they may implicitly
4254 alias surrounding code. Ideally we'd have some alias set that
4255 covered all types except those with alignment 8 or higher. */
4257 meml
= change_address (dst
, DImode
,
4258 gen_rtx_AND (DImode
,
4259 plus_constant (dsta
, ofs
),
4261 set_mem_alias_set (meml
, 0);
4263 memh
= change_address (dst
, DImode
,
4264 gen_rtx_AND (DImode
,
4265 plus_constant (dsta
, ofs
+ size
- 1),
4267 set_mem_alias_set (memh
, 0);
4269 emit_move_insn (dsth
, memh
);
4270 emit_move_insn (dstl
, meml
);
4271 if (WORDS_BIG_ENDIAN
)
4273 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
4275 if (src
!= const0_rtx
)
4280 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
4283 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
4286 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
4289 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
4290 GEN_INT (size
*8), addr
));
4296 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
4300 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4301 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
4305 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
4309 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
4313 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
4315 if (src
!= const0_rtx
)
4317 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
4318 GEN_INT (size
*8), addr
));
4323 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
4326 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
4329 emit_insn (gen_insql_le (insl
, src
, addr
));
4334 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
4339 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
4343 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4344 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
4348 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
4353 if (src
!= const0_rtx
)
4355 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
4356 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
4359 if (WORDS_BIG_ENDIAN
)
4361 emit_move_insn (meml
, dstl
);
4362 emit_move_insn (memh
, dsth
);
4366 /* Must store high before low for degenerate case of aligned. */
4367 emit_move_insn (memh
, dsth
);
4368 emit_move_insn (meml
, dstl
);
4372 /* The block move code tries to maximize speed by separating loads and
4373 stores at the expense of register pressure: we load all of the data
4374 before we store it back out. There are two secondary effects worth
4375 mentioning, that this speeds copying to/from aligned and unaligned
4376 buffers, and that it makes the code significantly easier to write. */
4378 #define MAX_MOVE_WORDS 8
4380 /* Load an integral number of consecutive unaligned quadwords. */
4383 alpha_expand_unaligned_load_words (out_regs
, smem
, words
, ofs
)
4386 HOST_WIDE_INT words
, ofs
;
4388 rtx
const im8
= GEN_INT (-8);
4389 rtx
const i64
= GEN_INT (64);
4390 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
4391 rtx sreg
, areg
, tmp
, smema
;
4394 smema
= XEXP (smem
, 0);
4395 if (GET_CODE (smema
) == LO_SUM
)
4396 smema
= force_reg (Pmode
, smema
);
4398 /* Generate all the tmp registers we need. */
4399 for (i
= 0; i
< words
; ++i
)
4401 data_regs
[i
] = out_regs
[i
];
4402 ext_tmps
[i
] = gen_reg_rtx (DImode
);
4404 data_regs
[words
] = gen_reg_rtx (DImode
);
4407 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
4409 /* Load up all of the source data. */
4410 for (i
= 0; i
< words
; ++i
)
4412 tmp
= change_address (smem
, DImode
,
4413 gen_rtx_AND (DImode
,
4414 plus_constant (smema
, 8*i
),
4416 set_mem_alias_set (tmp
, 0);
4417 emit_move_insn (data_regs
[i
], tmp
);
4420 tmp
= change_address (smem
, DImode
,
4421 gen_rtx_AND (DImode
,
4422 plus_constant (smema
, 8*words
- 1),
4424 set_mem_alias_set (tmp
, 0);
4425 emit_move_insn (data_regs
[words
], tmp
);
4427 /* Extract the half-word fragments. Unfortunately DEC decided to make
4428 extxh with offset zero a noop instead of zeroing the register, so
4429 we must take care of that edge condition ourselves with cmov. */
4431 sreg
= copy_addr_to_reg (smema
);
4432 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
4434 if (WORDS_BIG_ENDIAN
)
4435 emit_move_insn (sreg
, plus_constant (sreg
, 7));
4436 for (i
= 0; i
< words
; ++i
)
4438 if (WORDS_BIG_ENDIAN
)
4440 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
4441 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
4445 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
4446 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
4448 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
4449 gen_rtx_IF_THEN_ELSE (DImode
,
4450 gen_rtx_EQ (DImode
, areg
,
4452 const0_rtx
, ext_tmps
[i
])));
4455 /* Merge the half-words into whole words. */
4456 for (i
= 0; i
< words
; ++i
)
4458 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4459 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
4463 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4464 may be NULL to store zeros. */
4467 alpha_expand_unaligned_store_words (data_regs
, dmem
, words
, ofs
)
4470 HOST_WIDE_INT words
, ofs
;
4472 rtx
const im8
= GEN_INT (-8);
4473 rtx
const i64
= GEN_INT (64);
4474 rtx ins_tmps
[MAX_MOVE_WORDS
];
4475 rtx st_tmp_1
, st_tmp_2
, dreg
;
4476 rtx st_addr_1
, st_addr_2
, dmema
;
4479 dmema
= XEXP (dmem
, 0);
4480 if (GET_CODE (dmema
) == LO_SUM
)
4481 dmema
= force_reg (Pmode
, dmema
);
4483 /* Generate all the tmp registers we need. */
4484 if (data_regs
!= NULL
)
4485 for (i
= 0; i
< words
; ++i
)
4486 ins_tmps
[i
] = gen_reg_rtx(DImode
);
4487 st_tmp_1
= gen_reg_rtx(DImode
);
4488 st_tmp_2
= gen_reg_rtx(DImode
);
4491 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
4493 st_addr_2
= change_address (dmem
, DImode
,
4494 gen_rtx_AND (DImode
,
4495 plus_constant (dmema
, words
*8 - 1),
4497 set_mem_alias_set (st_addr_2
, 0);
4499 st_addr_1
= change_address (dmem
, DImode
,
4500 gen_rtx_AND (DImode
, dmema
, im8
));
4501 set_mem_alias_set (st_addr_1
, 0);
4503 /* Load up the destination end bits. */
4504 emit_move_insn (st_tmp_2
, st_addr_2
);
4505 emit_move_insn (st_tmp_1
, st_addr_1
);
4507 /* Shift the input data into place. */
4508 dreg
= copy_addr_to_reg (dmema
);
4509 if (WORDS_BIG_ENDIAN
)
4510 emit_move_insn (dreg
, plus_constant (dreg
, 7));
4511 if (data_regs
!= NULL
)
4513 for (i
= words
-1; i
>= 0; --i
)
4515 if (WORDS_BIG_ENDIAN
)
4517 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
4518 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
4522 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
4523 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
4526 for (i
= words
-1; i
> 0; --i
)
4528 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4529 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
4534 /* Split and merge the ends with the destination data. */
4535 if (WORDS_BIG_ENDIAN
)
4537 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
4538 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
4542 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
4543 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
4546 if (data_regs
!= NULL
)
4548 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
4549 st_tmp_2
, 1, OPTAB_WIDEN
);
4550 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
4551 st_tmp_1
, 1, OPTAB_WIDEN
);
4555 if (WORDS_BIG_ENDIAN
)
4556 emit_move_insn (st_addr_1
, st_tmp_1
);
4558 emit_move_insn (st_addr_2
, st_tmp_2
);
4559 for (i
= words
-1; i
> 0; --i
)
4561 rtx tmp
= change_address (dmem
, DImode
,
4562 gen_rtx_AND (DImode
,
4563 plus_constant(dmema
,
4564 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
4566 set_mem_alias_set (tmp
, 0);
4567 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
4569 if (WORDS_BIG_ENDIAN
)
4570 emit_move_insn (st_addr_2
, st_tmp_2
);
4572 emit_move_insn (st_addr_1
, st_tmp_1
);
4576 /* Expand string/block move operations.
4578 operands[0] is the pointer to the destination.
4579 operands[1] is the pointer to the source.
4580 operands[2] is the number of bytes to move.
4581 operands[3] is the alignment. */
4584 alpha_expand_block_move (operands
)
4587 rtx bytes_rtx
= operands
[2];
4588 rtx align_rtx
= operands
[3];
4589 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4590 HOST_WIDE_INT bytes
= orig_bytes
;
4591 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4592 HOST_WIDE_INT dst_align
= src_align
;
4593 rtx orig_src
= operands
[1];
4594 rtx orig_dst
= operands
[0];
4595 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
4597 unsigned int i
, words
, ofs
, nregs
= 0;
4599 if (orig_bytes
<= 0)
4601 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4604 /* Look for additional alignment information from recorded register info. */
4606 tmp
= XEXP (orig_src
, 0);
4607 if (GET_CODE (tmp
) == REG
)
4608 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4609 else if (GET_CODE (tmp
) == PLUS
4610 && GET_CODE (XEXP (tmp
, 0)) == REG
4611 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4613 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4614 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4618 if (a
>= 64 && c
% 8 == 0)
4620 else if (a
>= 32 && c
% 4 == 0)
4622 else if (a
>= 16 && c
% 2 == 0)
4627 tmp
= XEXP (orig_dst
, 0);
4628 if (GET_CODE (tmp
) == REG
)
4629 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4630 else if (GET_CODE (tmp
) == PLUS
4631 && GET_CODE (XEXP (tmp
, 0)) == REG
4632 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4634 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4635 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4639 if (a
>= 64 && c
% 8 == 0)
4641 else if (a
>= 32 && c
% 4 == 0)
4643 else if (a
>= 16 && c
% 2 == 0)
4648 /* Load the entire block into registers. */
4649 if (GET_CODE (XEXP (orig_src
, 0)) == ADDRESSOF
)
4651 enum machine_mode mode
;
4653 tmp
= XEXP (XEXP (orig_src
, 0), 0);
4655 /* Don't use the existing register if we're reading more than
4656 is held in the register. Nor if there is not a mode that
4657 handles the exact size. */
4658 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4660 && GET_MODE_SIZE (GET_MODE (tmp
)) >= bytes
)
4664 data_regs
[nregs
] = gen_lowpart (DImode
, tmp
);
4665 data_regs
[nregs
+ 1] = gen_highpart (DImode
, tmp
);
4669 data_regs
[nregs
++] = gen_lowpart (mode
, tmp
);
4674 /* No appropriate mode; fall back on memory. */
4675 orig_src
= replace_equiv_address (orig_src
,
4676 copy_addr_to_reg (XEXP (orig_src
, 0)));
4677 src_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4681 if (src_align
>= 64 && bytes
>= 8)
4685 for (i
= 0; i
< words
; ++i
)
4686 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4688 for (i
= 0; i
< words
; ++i
)
4689 emit_move_insn (data_regs
[nregs
+ i
],
4690 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
4697 if (src_align
>= 32 && bytes
>= 4)
4701 for (i
= 0; i
< words
; ++i
)
4702 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
4704 for (i
= 0; i
< words
; ++i
)
4705 emit_move_insn (data_regs
[nregs
+ i
],
4706 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
4717 for (i
= 0; i
< words
+1; ++i
)
4718 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4720 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
4728 if (! TARGET_BWX
&& bytes
>= 4)
4730 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
4731 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
4738 if (src_align
>= 16)
4741 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4742 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
4745 } while (bytes
>= 2);
4747 else if (! TARGET_BWX
)
4749 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4750 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
4758 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
4759 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
4766 if (nregs
> ARRAY_SIZE (data_regs
))
4769 /* Now save it back out again. */
4773 if (GET_CODE (XEXP (orig_dst
, 0)) == ADDRESSOF
)
4775 enum machine_mode mode
;
4776 tmp
= XEXP (XEXP (orig_dst
, 0), 0);
4778 mode
= mode_for_size (orig_bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4779 if (GET_MODE (tmp
) == mode
)
4783 emit_move_insn (tmp
, data_regs
[0]);
4788 else if (nregs
== 2 && mode
== TImode
)
4790 /* Undo the subregging done above when copying between
4791 two TImode registers. */
4792 if (GET_CODE (data_regs
[0]) == SUBREG
4793 && GET_MODE (SUBREG_REG (data_regs
[0])) == TImode
)
4794 emit_move_insn (tmp
, SUBREG_REG (data_regs
[0]));
4800 emit_move_insn (gen_lowpart (DImode
, tmp
), data_regs
[0]);
4801 emit_move_insn (gen_highpart (DImode
, tmp
), data_regs
[1]);
4805 emit_no_conflict_block (seq
, tmp
, data_regs
[0],
4806 data_regs
[1], NULL_RTX
);
4814 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4815 /* ??? Optimize mode < dst_mode with strict_low_part. */
4817 /* No appropriate mode; fall back on memory. We can speed things
4818 up by recognizing extra alignment information. */
4819 orig_dst
= replace_equiv_address (orig_dst
,
4820 copy_addr_to_reg (XEXP (orig_dst
, 0)));
4821 dst_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4824 /* Write out the data in whatever chunks reading the source allowed. */
4825 if (dst_align
>= 64)
4827 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4829 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
4836 if (dst_align
>= 32)
4838 /* If the source has remaining DImode regs, write them out in
4840 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4842 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
4843 NULL_RTX
, 1, OPTAB_WIDEN
);
4845 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4846 gen_lowpart (SImode
, data_regs
[i
]));
4847 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
4848 gen_lowpart (SImode
, tmp
));
4853 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4855 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4862 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4864 /* Write out a remaining block of words using unaligned methods. */
4866 for (words
= 1; i
+ words
< nregs
; words
++)
4867 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4871 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4873 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4880 /* Due to the above, this won't be aligned. */
4881 /* ??? If we have more than one of these, consider constructing full
4882 words in registers and using alpha_expand_unaligned_store_words. */
4883 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4885 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4890 if (dst_align
>= 16)
4891 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4893 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4898 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4900 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4905 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
4907 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4921 alpha_expand_block_clear (operands
)
4924 rtx bytes_rtx
= operands
[1];
4925 rtx align_rtx
= operands
[2];
4926 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4927 HOST_WIDE_INT bytes
= orig_bytes
;
4928 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4929 HOST_WIDE_INT alignofs
= 0;
4930 rtx orig_dst
= operands
[0];
4932 int i
, words
, ofs
= 0;
4934 if (orig_bytes
<= 0)
4936 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4939 /* Look for stricter alignment. */
4940 tmp
= XEXP (orig_dst
, 0);
4941 if (GET_CODE (tmp
) == REG
)
4942 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4943 else if (GET_CODE (tmp
) == PLUS
4944 && GET_CODE (XEXP (tmp
, 0)) == REG
4945 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4947 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4948 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4953 align
= a
, alignofs
= 8 - c
% 8;
4955 align
= a
, alignofs
= 4 - c
% 4;
4957 align
= a
, alignofs
= 2 - c
% 2;
4960 else if (GET_CODE (tmp
) == ADDRESSOF
)
4962 enum machine_mode mode
;
4964 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4965 if (GET_MODE (XEXP (tmp
, 0)) == mode
)
4967 emit_move_insn (XEXP (tmp
, 0), const0_rtx
);
4971 /* No appropriate mode; fall back on memory. */
4972 orig_dst
= replace_equiv_address (orig_dst
, copy_addr_to_reg (tmp
));
4973 align
= GET_MODE_BITSIZE (GET_MODE (XEXP (tmp
, 0)));
4976 /* Handle an unaligned prefix first. */
4980 #if HOST_BITS_PER_WIDE_INT >= 64
4981 /* Given that alignofs is bounded by align, the only time BWX could
4982 generate three stores is for a 7 byte fill. Prefer two individual
4983 stores over a load/mask/store sequence. */
4984 if ((!TARGET_BWX
|| alignofs
== 7)
4986 && !(alignofs
== 4 && bytes
>= 4))
4988 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
4989 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
4993 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
4994 set_mem_alias_set (mem
, 0);
4996 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
4997 if (bytes
< alignofs
)
4999 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
5010 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
5011 NULL_RTX
, 1, OPTAB_WIDEN
);
5013 emit_move_insn (mem
, tmp
);
5017 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
5019 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5024 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
5026 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
5031 if (alignofs
== 4 && bytes
>= 4)
5033 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
5039 /* If we've not used the extra lead alignment information by now,
5040 we won't be able to. Downgrade align to match what's left over. */
5043 alignofs
= alignofs
& -alignofs
;
5044 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
5048 /* Handle a block of contiguous long-words. */
5050 if (align
>= 64 && bytes
>= 8)
5054 for (i
= 0; i
< words
; ++i
)
5055 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
5062 /* If the block is large and appropriately aligned, emit a single
5063 store followed by a sequence of stq_u insns. */
5065 if (align
>= 32 && bytes
> 16)
5069 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
5073 orig_dsta
= XEXP (orig_dst
, 0);
5074 if (GET_CODE (orig_dsta
) == LO_SUM
)
5075 orig_dsta
= force_reg (Pmode
, orig_dsta
);
5078 for (i
= 0; i
< words
; ++i
)
5081 = change_address (orig_dst
, DImode
,
5082 gen_rtx_AND (DImode
,
5083 plus_constant (orig_dsta
, ofs
+ i
*8),
5085 set_mem_alias_set (mem
, 0);
5086 emit_move_insn (mem
, const0_rtx
);
5089 /* Depending on the alignment, the first stq_u may have overlapped
5090 with the initial stl, which means that the last stq_u didn't
5091 write as much as it would appear. Leave those questionable bytes
5093 bytes
-= words
* 8 - 4;
5094 ofs
+= words
* 8 - 4;
5097 /* Handle a smaller block of aligned words. */
5099 if ((align
>= 64 && bytes
== 4)
5100 || (align
== 32 && bytes
>= 4))
5104 for (i
= 0; i
< words
; ++i
)
5105 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
5112 /* An unaligned block uses stq_u stores for as many as possible. */
5118 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
5124 /* Next clean up any trailing pieces. */
5126 #if HOST_BITS_PER_WIDE_INT >= 64
5127 /* Count the number of bits in BYTES for which aligned stores could
5130 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
5134 /* If we have appropriate alignment (and it wouldn't take too many
5135 instructions otherwise), mask out the bytes we need. */
5136 if (TARGET_BWX
? words
> 2 : bytes
> 0)
5143 mem
= adjust_address (orig_dst
, DImode
, ofs
);
5144 set_mem_alias_set (mem
, 0);
5146 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5148 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
5149 NULL_RTX
, 1, OPTAB_WIDEN
);
5151 emit_move_insn (mem
, tmp
);
5154 else if (align
>= 32 && bytes
< 4)
5159 mem
= adjust_address (orig_dst
, SImode
, ofs
);
5160 set_mem_alias_set (mem
, 0);
5162 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5164 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
5165 NULL_RTX
, 1, OPTAB_WIDEN
);
5167 emit_move_insn (mem
, tmp
);
5173 if (!TARGET_BWX
&& bytes
>= 4)
5175 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
5185 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
5189 } while (bytes
>= 2);
5191 else if (! TARGET_BWX
)
5193 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
5201 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5209 /* Returns a mask so that zap(x, value) == x & mask. */
5212 alpha_expand_zap_mask (value
)
5213 HOST_WIDE_INT value
;
5218 if (HOST_BITS_PER_WIDE_INT
>= 64)
5220 HOST_WIDE_INT mask
= 0;
5222 for (i
= 7; i
>= 0; --i
)
5225 if (!((value
>> i
) & 1))
5229 result
= gen_int_mode (mask
, DImode
);
5231 else if (HOST_BITS_PER_WIDE_INT
== 32)
5233 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
5235 for (i
= 7; i
>= 4; --i
)
5238 if (!((value
>> i
) & 1))
5242 for (i
= 3; i
>= 0; --i
)
5245 if (!((value
>> i
) & 1))
5249 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
5258 alpha_expand_builtin_vector_binop (gen
, mode
, op0
, op1
, op2
)
5259 rtx (*gen
) PARAMS ((rtx
, rtx
, rtx
));
5260 enum machine_mode mode
;
5263 op0
= gen_lowpart (mode
, op0
);
5265 if (op1
== const0_rtx
)
5266 op1
= CONST0_RTX (mode
);
5268 op1
= gen_lowpart (mode
, op1
);
5270 if (op2
== const0_rtx
)
5271 op2
= CONST0_RTX (mode
);
5273 op2
= gen_lowpart (mode
, op2
);
5275 emit_insn ((*gen
) (op0
, op1
, op2
));
5278 /* Adjust the cost of a scheduling dependency. Return the new cost of
5279 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5282 alpha_adjust_cost (insn
, link
, dep_insn
, cost
)
5288 enum attr_type insn_type
, dep_insn_type
;
5290 /* If the dependence is an anti-dependence, there is no cost. For an
5291 output dependence, there is sometimes a cost, but it doesn't seem
5292 worth handling those few cases. */
5293 if (REG_NOTE_KIND (link
) != 0)
5296 /* If we can't recognize the insns, we can't really do anything. */
5297 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
5300 insn_type
= get_attr_type (insn
);
5301 dep_insn_type
= get_attr_type (dep_insn
);
5303 /* Bring in the user-defined memory latency. */
5304 if (dep_insn_type
== TYPE_ILD
5305 || dep_insn_type
== TYPE_FLD
5306 || dep_insn_type
== TYPE_LDSYM
)
5307 cost
+= alpha_memory_latency
-1;
5309 /* Everything else handled in DFA bypasses now. */
5314 /* The number of instructions that can be issued per cycle. */
5319 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
5323 alpha_use_dfa_pipeline_interface ()
5328 /* How many alternative schedules to try. This should be as wide as the
5329 scheduling freedom in the DFA, but no wider. Making this value too
5330 large results extra work for the scheduler.
5332 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5333 alternative schedules. For EV5, we can choose between E0/E1 and
5334 FA/FM. For EV6, an arithmatic insn can be issued to U0/U1/L0/L1. */
5337 alpha_multipass_dfa_lookahead ()
5339 return (alpha_cpu
== PROCESSOR_EV6
? 4 : 2);
5342 /* Machine-specific function data. */
5344 struct machine_function
GTY(())
5347 /* List of call information words for calls from this function. */
5348 struct rtx_def
*first_ciw
;
5349 struct rtx_def
*last_ciw
;
5352 /* List of deferred case vectors. */
5353 struct rtx_def
*addr_list
;
5356 const char *some_ld_name
;
5359 /* How to allocate a 'struct machine_function'. */
5361 static struct machine_function
*
5362 alpha_init_machine_status ()
5364 return ((struct machine_function
*)
5365 ggc_alloc_cleared (sizeof (struct machine_function
)));
5368 /* Functions to save and restore alpha_return_addr_rtx. */
5370 /* Start the ball rolling with RETURN_ADDR_RTX. */
5373 alpha_return_addr (count
, frame
)
5375 rtx frame ATTRIBUTE_UNUSED
;
5380 return get_hard_reg_initial_val (Pmode
, REG_RA
);
5383 /* Return or create a pseudo containing the gp value for the current
5384 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5387 alpha_gp_save_rtx ()
5389 rtx r
= get_hard_reg_initial_val (DImode
, 29);
5390 if (GET_CODE (r
) != MEM
)
5391 r
= gen_mem_addressof (r
, NULL_TREE
);
5396 alpha_ra_ever_killed ()
5400 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
5401 return regs_ever_live
[REG_RA
];
5403 push_topmost_sequence ();
5405 pop_topmost_sequence ();
5407 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
5411 /* Return the trap mode suffix applicable to the current
5412 instruction, or NULL. */
5415 get_trap_mode_suffix ()
5417 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
5421 case TRAP_SUFFIX_NONE
:
5424 case TRAP_SUFFIX_SU
:
5425 if (alpha_fptm
>= ALPHA_FPTM_SU
)
5429 case TRAP_SUFFIX_SUI
:
5430 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
5434 case TRAP_SUFFIX_V_SV
:
5442 case ALPHA_FPTM_SUI
:
5447 case TRAP_SUFFIX_V_SV_SVI
:
5456 case ALPHA_FPTM_SUI
:
5461 case TRAP_SUFFIX_U_SU_SUI
:
5470 case ALPHA_FPTM_SUI
:
5478 /* Return the rounding mode suffix applicable to the current
5479 instruction, or NULL. */
5482 get_round_mode_suffix ()
5484 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5488 case ROUND_SUFFIX_NONE
:
5490 case ROUND_SUFFIX_NORMAL
:
5493 case ALPHA_FPRM_NORM
:
5495 case ALPHA_FPRM_MINF
:
5497 case ALPHA_FPRM_CHOP
:
5499 case ALPHA_FPRM_DYN
:
5504 case ROUND_SUFFIX_C
:
5510 /* Locate some local-dynamic symbol still in use by this function
5511 so that we can print its name in some movdi_er_tlsldm pattern. */
5514 get_some_local_dynamic_name ()
5518 if (cfun
->machine
->some_ld_name
)
5519 return cfun
->machine
->some_ld_name
;
5521 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5523 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5524 return cfun
->machine
->some_ld_name
;
5530 get_some_local_dynamic_name_1 (px
, data
)
5532 void *data ATTRIBUTE_UNUSED
;
5536 if (GET_CODE (x
) == SYMBOL_REF
)
5538 const char *str
= XSTR (x
, 0);
5539 if (str
[0] == '@' && str
[1] == 'D')
5541 cfun
->machine
->some_ld_name
= str
;
5549 /* Print an operand. Recognize special options, documented below. */
5552 print_operand (file
, x
, code
)
5562 /* Print the assembler name of the current function. */
5563 assemble_name (file
, alpha_fnname
);
5567 assemble_name (file
, get_some_local_dynamic_name ());
5572 const char *trap
= get_trap_mode_suffix ();
5573 const char *round
= get_round_mode_suffix ();
5576 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5577 (trap
? trap
: ""), (round
? round
: ""));
5582 /* Generates single precision instruction suffix. */
5583 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5587 /* Generates double precision instruction suffix. */
5588 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5592 if (alpha_this_literal_sequence_number
== 0)
5593 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5594 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5598 if (alpha_this_gpdisp_sequence_number
== 0)
5599 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5600 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5604 if (GET_CODE (x
) == HIGH
)
5605 output_addr_const (file
, XEXP (x
, 0));
5607 output_operand_lossage ("invalid %%H value");
5614 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5616 x
= XVECEXP (x
, 0, 0);
5617 lituse
= "lituse_tlsgd";
5619 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5621 x
= XVECEXP (x
, 0, 0);
5622 lituse
= "lituse_tlsldm";
5624 else if (GET_CODE (x
) == CONST_INT
)
5625 lituse
= "lituse_jsr";
5628 output_operand_lossage ("invalid %%J value");
5632 if (x
!= const0_rtx
)
5633 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5638 /* If this operand is the constant zero, write it as "$31". */
5639 if (GET_CODE (x
) == REG
)
5640 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5641 else if (x
== CONST0_RTX (GET_MODE (x
)))
5642 fprintf (file
, "$31");
5644 output_operand_lossage ("invalid %%r value");
5648 /* Similar, but for floating-point. */
5649 if (GET_CODE (x
) == REG
)
5650 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5651 else if (x
== CONST0_RTX (GET_MODE (x
)))
5652 fprintf (file
, "$f31");
5654 output_operand_lossage ("invalid %%R value");
5658 /* Write the 1's complement of a constant. */
5659 if (GET_CODE (x
) != CONST_INT
)
5660 output_operand_lossage ("invalid %%N value");
5662 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5666 /* Write 1 << C, for a constant C. */
5667 if (GET_CODE (x
) != CONST_INT
)
5668 output_operand_lossage ("invalid %%P value");
5670 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5674 /* Write the high-order 16 bits of a constant, sign-extended. */
5675 if (GET_CODE (x
) != CONST_INT
)
5676 output_operand_lossage ("invalid %%h value");
5678 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5682 /* Write the low-order 16 bits of a constant, sign-extended. */
5683 if (GET_CODE (x
) != CONST_INT
)
5684 output_operand_lossage ("invalid %%L value");
5686 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5687 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5691 /* Write mask for ZAP insn. */
5692 if (GET_CODE (x
) == CONST_DOUBLE
)
5694 HOST_WIDE_INT mask
= 0;
5695 HOST_WIDE_INT value
;
5697 value
= CONST_DOUBLE_LOW (x
);
5698 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5703 value
= CONST_DOUBLE_HIGH (x
);
5704 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5707 mask
|= (1 << (i
+ sizeof (int)));
5709 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5712 else if (GET_CODE (x
) == CONST_INT
)
5714 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5716 for (i
= 0; i
< 8; i
++, value
>>= 8)
5720 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5723 output_operand_lossage ("invalid %%m value");
5727 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5728 if (GET_CODE (x
) != CONST_INT
5729 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5730 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5731 output_operand_lossage ("invalid %%M value");
5733 fprintf (file
, "%s",
5734 (INTVAL (x
) == 8 ? "b"
5735 : INTVAL (x
) == 16 ? "w"
5736 : INTVAL (x
) == 32 ? "l"
5741 /* Similar, except do it from the mask. */
5742 if (GET_CODE (x
) == CONST_INT
)
5744 HOST_WIDE_INT value
= INTVAL (x
);
5751 if (value
== 0xffff)
5756 if (value
== 0xffffffff)
5767 else if (HOST_BITS_PER_WIDE_INT
== 32
5768 && GET_CODE (x
) == CONST_DOUBLE
5769 && CONST_DOUBLE_LOW (x
) == 0xffffffff
5770 && CONST_DOUBLE_HIGH (x
) == 0)
5775 output_operand_lossage ("invalid %%U value");
5779 /* Write the constant value divided by 8 for little-endian mode or
5780 (56 - value) / 8 for big-endian mode. */
5782 if (GET_CODE (x
) != CONST_INT
5783 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5786 || (INTVAL (x
) & 7) != 0)
5787 output_operand_lossage ("invalid %%s value");
5789 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5791 ? (56 - INTVAL (x
)) / 8
5796 /* Same, except compute (64 - c) / 8 */
5798 if (GET_CODE (x
) != CONST_INT
5799 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5800 && (INTVAL (x
) & 7) != 8)
5801 output_operand_lossage ("invalid %%s value");
5803 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5808 /* On Unicos/Mk systems: use a DEX expression if the symbol
5809 clashes with a register name. */
5810 int dex
= unicosmk_need_dex (x
);
5812 fprintf (file
, "DEX(%d)", dex
);
5814 output_addr_const (file
, x
);
5818 case 'C': case 'D': case 'c': case 'd':
5819 /* Write out comparison name. */
5821 enum rtx_code c
= GET_CODE (x
);
5823 if (GET_RTX_CLASS (c
) != '<')
5824 output_operand_lossage ("invalid %%C value");
5826 else if (code
== 'D')
5827 c
= reverse_condition (c
);
5828 else if (code
== 'c')
5829 c
= swap_condition (c
);
5830 else if (code
== 'd')
5831 c
= swap_condition (reverse_condition (c
));
5834 fprintf (file
, "ule");
5836 fprintf (file
, "ult");
5837 else if (c
== UNORDERED
)
5838 fprintf (file
, "un");
5840 fprintf (file
, "%s", GET_RTX_NAME (c
));
5845 /* Write the divide or modulus operator. */
5846 switch (GET_CODE (x
))
5849 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5852 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5855 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5858 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5861 output_operand_lossage ("invalid %%E value");
5867 /* Write "_u" for unaligned access. */
5868 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
5869 fprintf (file
, "_u");
5873 if (GET_CODE (x
) == REG
)
5874 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5875 else if (GET_CODE (x
) == MEM
)
5876 output_address (XEXP (x
, 0));
5877 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
5879 switch (XINT (XEXP (x
, 0), 1))
5883 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
5886 output_operand_lossage ("unknown relocation unspec");
5891 output_addr_const (file
, x
);
5895 output_operand_lossage ("invalid %%xn code");
5900 print_operand_address (file
, addr
)
5905 HOST_WIDE_INT offset
= 0;
5907 if (GET_CODE (addr
) == AND
)
5908 addr
= XEXP (addr
, 0);
5910 if (GET_CODE (addr
) == PLUS
5911 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5913 offset
= INTVAL (XEXP (addr
, 1));
5914 addr
= XEXP (addr
, 0);
5917 if (GET_CODE (addr
) == LO_SUM
)
5919 const char *reloc16
, *reloclo
;
5920 rtx op1
= XEXP (addr
, 1);
5922 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
5924 op1
= XEXP (op1
, 0);
5925 switch (XINT (op1
, 1))
5929 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
5933 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
5936 output_operand_lossage ("unknown relocation unspec");
5940 output_addr_const (file
, XVECEXP (op1
, 0, 0));
5945 reloclo
= "gprellow";
5946 output_addr_const (file
, op1
);
5952 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
5955 addr
= XEXP (addr
, 0);
5956 if (GET_CODE (addr
) == REG
)
5957 basereg
= REGNO (addr
);
5958 else if (GET_CODE (addr
) == SUBREG
5959 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5960 basereg
= subreg_regno (addr
);
5964 fprintf (file
, "($%d)\t\t!%s", basereg
,
5965 (basereg
== 29 ? reloc16
: reloclo
));
5969 if (GET_CODE (addr
) == REG
)
5970 basereg
= REGNO (addr
);
5971 else if (GET_CODE (addr
) == SUBREG
5972 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5973 basereg
= subreg_regno (addr
);
5974 else if (GET_CODE (addr
) == CONST_INT
)
5975 offset
= INTVAL (addr
);
5977 #if TARGET_ABI_OPEN_VMS
5978 else if (GET_CODE (addr
) == SYMBOL_REF
)
5980 fprintf (file
, "%s", XSTR (addr
, 0));
5983 else if (GET_CODE (addr
) == CONST
5984 && GET_CODE (XEXP (addr
, 0)) == PLUS
5985 && GET_CODE (XEXP (XEXP (addr
, 0), 0)) == SYMBOL_REF
)
5987 fprintf (file
, "%s+%d",
5988 XSTR (XEXP (XEXP (addr
, 0), 0), 0),
5989 INTVAL (XEXP (XEXP (addr
, 0), 1)));
5997 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
5998 fprintf (file
, "($%d)", basereg
);
6001 /* Emit RTL insns to initialize the variable parts of a trampoline at
6002 TRAMP. FNADDR is an RTX for the address of the function's pure
6003 code. CXT is an RTX for the static chain value for the function.
6005 The three offset parameters are for the individual template's
6006 layout. A JMPOFS < 0 indicates that the trampoline does not
6007 contain instructions at all.
6009 We assume here that a function will be called many more times than
6010 its address is taken (e.g., it might be passed to qsort), so we
6011 take the trouble to initialize the "hint" field in the JMP insn.
6012 Note that the hint field is PC (new) + 4 * bits 13:0. */
6015 alpha_initialize_trampoline (tramp
, fnaddr
, cxt
, fnofs
, cxtofs
, jmpofs
)
6016 rtx tramp
, fnaddr
, cxt
;
6017 int fnofs
, cxtofs
, jmpofs
;
6019 rtx temp
, temp1
, addr
;
6020 /* VMS really uses DImode pointers in memory at this point. */
6021 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
6023 #ifdef POINTERS_EXTEND_UNSIGNED
6024 fnaddr
= convert_memory_address (mode
, fnaddr
);
6025 cxt
= convert_memory_address (mode
, cxt
);
6028 /* Store function address and CXT. */
6029 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
6030 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
6031 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
6032 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
6034 /* This has been disabled since the hint only has a 32k range, and in
6035 no existing OS is the stack within 32k of the text segment. */
6036 if (0 && jmpofs
>= 0)
6038 /* Compute hint value. */
6039 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
6040 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
6042 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
6043 build_int_2 (2, 0), NULL_RTX
, 1);
6044 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
6045 GEN_INT (0x3fff), 0);
6047 /* Merge in the hint. */
6048 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
6049 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
6050 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
6051 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
6053 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
6056 #ifdef TRANSFER_FROM_TRAMPOLINE
6057 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
6058 0, VOIDmode
, 1, addr
, Pmode
);
6062 emit_insn (gen_imb ());
6065 /* Determine where to put an argument to a function.
6066 Value is zero to push the argument on the stack,
6067 or a hard register in which to store the argument.
6069 MODE is the argument's machine mode.
6070 TYPE is the data type of the argument (as a tree).
6071 This is null for libcalls where that information may
6073 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6074 the preceding args and about the function being called.
6075 NAMED is nonzero if this argument is a named parameter
6076 (otherwise it is an extra parameter matching an ellipsis).
6078 On Alpha the first 6 words of args are normally in registers
6079 and the rest are pushed. */
6082 function_arg (cum
, mode
, type
, named
)
6083 CUMULATIVE_ARGS cum
;
6084 enum machine_mode mode
;
6086 int named ATTRIBUTE_UNUSED
;
6091 /* Set up defaults for FP operands passed in FP registers, and
6092 integral operands passed in integer registers. */
6094 && (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
6095 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
6100 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
6101 the three platforms, so we can't avoid conditional compilation. */
6102 #if TARGET_ABI_OPEN_VMS
6104 if (mode
== VOIDmode
)
6105 return alpha_arg_info_reg_val (cum
);
6107 num_args
= cum
.num_args
;
6108 if (num_args
>= 6 || MUST_PASS_IN_STACK (mode
, type
))
6112 #if TARGET_ABI_UNICOSMK
6116 /* If this is the last argument, generate the call info word (CIW). */
6117 /* ??? We don't include the caller's line number in the CIW because
6118 I don't know how to determine it if debug infos are turned off. */
6119 if (mode
== VOIDmode
)
6128 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
6129 if (cum
.reg_args_type
[i
])
6130 lo
|= (1 << (7 - i
));
6132 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
6135 lo
|= cum
.num_reg_words
;
6137 #if HOST_BITS_PER_WIDE_INT == 32
6138 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
6140 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
6141 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
6144 ciw
= immed_double_const (lo
, hi
, DImode
);
6146 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
6147 UNSPEC_UMK_LOAD_CIW
);
6150 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
6151 num_args
= cum
.num_reg_words
;
6152 if (MUST_PASS_IN_STACK (mode
, type
)
6153 || cum
.num_reg_words
+ size
> 6 || cum
.force_stack
)
6155 else if (type
&& TYPE_MODE (type
) == BLKmode
)
6159 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
6160 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
6162 /* The argument fits in two registers. Note that we still need to
6163 reserve a register for empty structures. */
6167 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
6170 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
6171 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
6172 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
6182 /* VOID is passed as a special flag for "last argument". */
6183 if (type
== void_type_node
)
6185 else if (MUST_PASS_IN_STACK (mode
, type
))
6187 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum
, mode
, type
, named
))
6190 #endif /* TARGET_ABI_UNICOSMK */
6191 #endif /* TARGET_ABI_OPEN_VMS */
6193 return gen_rtx_REG (mode
, num_args
+ basereg
);
6197 alpha_build_va_list ()
6199 tree base
, ofs
, record
, type_decl
;
6201 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6202 return ptr_type_node
;
6204 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6205 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6206 TREE_CHAIN (record
) = type_decl
;
6207 TYPE_NAME (record
) = type_decl
;
6209 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6211 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
6213 DECL_FIELD_CONTEXT (ofs
) = record
;
6215 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
6217 DECL_FIELD_CONTEXT (base
) = record
;
6218 TREE_CHAIN (base
) = ofs
;
6220 TYPE_FIELDS (record
) = base
;
6221 layout_type (record
);
6227 alpha_va_start (valist
, nextarg
)
6229 rtx nextarg ATTRIBUTE_UNUSED
;
6231 HOST_WIDE_INT offset
;
6232 tree t
, offset_field
, base_field
;
6234 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6237 if (TARGET_ABI_UNICOSMK
)
6238 std_expand_builtin_va_start (valist
, nextarg
);
6240 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6241 up by 48, storing fp arg registers in the first 48 bytes, and the
6242 integer arg registers in the next 48 bytes. This is only done,
6243 however, if any integer registers need to be stored.
6245 If no integer registers need be stored, then we must subtract 48
6246 in order to account for the integer arg registers which are counted
6247 in argsize above, but which are not actually stored on the stack. */
6250 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6252 offset
= -6 * UNITS_PER_WORD
;
6254 if (TARGET_ABI_OPEN_VMS
)
6256 nextarg
= plus_constant (nextarg
, offset
);
6257 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
6258 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
6259 make_tree (ptr_type_node
, nextarg
));
6260 TREE_SIDE_EFFECTS (t
) = 1;
6262 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6266 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6267 offset_field
= TREE_CHAIN (base_field
);
6269 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6270 valist
, base_field
);
6271 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6272 valist
, offset_field
);
6274 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6275 t
= build (PLUS_EXPR
, ptr_type_node
, t
, build_int_2 (offset
, 0));
6276 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6277 TREE_SIDE_EFFECTS (t
) = 1;
6278 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6280 t
= build_int_2 (NUM_ARGS
* UNITS_PER_WORD
, 0);
6281 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6282 TREE_SIDE_EFFECTS (t
) = 1;
6283 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6288 alpha_va_arg (valist
, type
)
6292 tree t
, type_size
, rounded_size
;
6293 tree offset_field
, base_field
, addr_tree
, addend
;
6294 tree wide_type
, wide_ofs
;
6297 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6298 return std_expand_builtin_va_arg (valist
, type
);
6300 if (type
== error_mark_node
6301 || (type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
))) == NULL
6302 || TREE_OVERFLOW (type_size
))
6303 rounded_size
= size_zero_node
;
6305 rounded_size
= fold (build (MULT_EXPR
, sizetype
,
6306 fold (build (TRUNC_DIV_EXPR
, sizetype
,
6307 fold (build (PLUS_EXPR
, sizetype
,
6313 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6314 offset_field
= TREE_CHAIN (base_field
);
6316 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6317 valist
, base_field
);
6318 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6319 valist
, offset_field
);
6321 /* If the type could not be passed in registers, skip the block
6322 reserved for the registers. */
6323 if (MUST_PASS_IN_STACK (TYPE_MODE (type
), type
))
6325 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6326 build (MAX_EXPR
, TREE_TYPE (offset_field
),
6327 offset_field
, build_int_2 (6*8, 0)));
6328 TREE_SIDE_EFFECTS (t
) = 1;
6329 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6332 wide_type
= make_signed_type (64);
6333 wide_ofs
= save_expr (build1 (CONVERT_EXPR
, wide_type
, offset_field
));
6337 if (TYPE_MODE (type
) == TFmode
|| TYPE_MODE (type
) == TCmode
)
6340 rounded_size
= size_int (UNITS_PER_WORD
);
6342 else if (FLOAT_TYPE_P (type
))
6344 tree fpaddend
, cond
;
6346 fpaddend
= fold (build (PLUS_EXPR
, TREE_TYPE (addend
),
6347 addend
, build_int_2 (-6*8, 0)));
6349 cond
= fold (build (LT_EXPR
, integer_type_node
,
6350 wide_ofs
, build_int_2 (6*8, 0)));
6352 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
6356 addr_tree
= build (PLUS_EXPR
, TREE_TYPE (base_field
),
6357 base_field
, addend
);
6359 addr
= expand_expr (addr_tree
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
6360 addr
= copy_to_reg (addr
);
6362 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6363 build (PLUS_EXPR
, TREE_TYPE (offset_field
),
6364 offset_field
, rounded_size
));
6365 TREE_SIDE_EFFECTS (t
) = 1;
6366 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6370 addr
= force_reg (Pmode
, addr
);
6371 addr
= gen_rtx_MEM (Pmode
, addr
);
6381 ALPHA_BUILTIN_CMPBGE
,
6382 ALPHA_BUILTIN_EXTBL
,
6383 ALPHA_BUILTIN_EXTWL
,
6384 ALPHA_BUILTIN_EXTLL
,
6385 ALPHA_BUILTIN_EXTQL
,
6386 ALPHA_BUILTIN_EXTWH
,
6387 ALPHA_BUILTIN_EXTLH
,
6388 ALPHA_BUILTIN_EXTQH
,
6389 ALPHA_BUILTIN_INSBL
,
6390 ALPHA_BUILTIN_INSWL
,
6391 ALPHA_BUILTIN_INSLL
,
6392 ALPHA_BUILTIN_INSQL
,
6393 ALPHA_BUILTIN_INSWH
,
6394 ALPHA_BUILTIN_INSLH
,
6395 ALPHA_BUILTIN_INSQH
,
6396 ALPHA_BUILTIN_MSKBL
,
6397 ALPHA_BUILTIN_MSKWL
,
6398 ALPHA_BUILTIN_MSKLL
,
6399 ALPHA_BUILTIN_MSKQL
,
6400 ALPHA_BUILTIN_MSKWH
,
6401 ALPHA_BUILTIN_MSKLH
,
6402 ALPHA_BUILTIN_MSKQH
,
6403 ALPHA_BUILTIN_UMULH
,
6405 ALPHA_BUILTIN_ZAPNOT
,
6406 ALPHA_BUILTIN_AMASK
,
6407 ALPHA_BUILTIN_IMPLVER
,
6409 ALPHA_BUILTIN_THREAD_POINTER
,
6410 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6413 ALPHA_BUILTIN_MINUB8
,
6414 ALPHA_BUILTIN_MINSB8
,
6415 ALPHA_BUILTIN_MINUW4
,
6416 ALPHA_BUILTIN_MINSW4
,
6417 ALPHA_BUILTIN_MAXUB8
,
6418 ALPHA_BUILTIN_MAXSB8
,
6419 ALPHA_BUILTIN_MAXUW4
,
6420 ALPHA_BUILTIN_MAXSW4
,
6424 ALPHA_BUILTIN_UNPKBL
,
6425 ALPHA_BUILTIN_UNPKBW
,
6430 ALPHA_BUILTIN_CTPOP
,
6435 static unsigned int const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6436 CODE_FOR_builtin_cmpbge
,
6437 CODE_FOR_builtin_extbl
,
6438 CODE_FOR_builtin_extwl
,
6439 CODE_FOR_builtin_extll
,
6440 CODE_FOR_builtin_extql
,
6441 CODE_FOR_builtin_extwh
,
6442 CODE_FOR_builtin_extlh
,
6443 CODE_FOR_builtin_extqh
,
6444 CODE_FOR_builtin_insbl
,
6445 CODE_FOR_builtin_inswl
,
6446 CODE_FOR_builtin_insll
,
6447 CODE_FOR_builtin_insql
,
6448 CODE_FOR_builtin_inswh
,
6449 CODE_FOR_builtin_inslh
,
6450 CODE_FOR_builtin_insqh
,
6451 CODE_FOR_builtin_mskbl
,
6452 CODE_FOR_builtin_mskwl
,
6453 CODE_FOR_builtin_mskll
,
6454 CODE_FOR_builtin_mskql
,
6455 CODE_FOR_builtin_mskwh
,
6456 CODE_FOR_builtin_msklh
,
6457 CODE_FOR_builtin_mskqh
,
6458 CODE_FOR_umuldi3_highpart
,
6459 CODE_FOR_builtin_zap
,
6460 CODE_FOR_builtin_zapnot
,
6461 CODE_FOR_builtin_amask
,
6462 CODE_FOR_builtin_implver
,
6463 CODE_FOR_builtin_rpcc
,
6468 CODE_FOR_builtin_minub8
,
6469 CODE_FOR_builtin_minsb8
,
6470 CODE_FOR_builtin_minuw4
,
6471 CODE_FOR_builtin_minsw4
,
6472 CODE_FOR_builtin_maxub8
,
6473 CODE_FOR_builtin_maxsb8
,
6474 CODE_FOR_builtin_maxuw4
,
6475 CODE_FOR_builtin_maxsw4
,
6476 CODE_FOR_builtin_perr
,
6477 CODE_FOR_builtin_pklb
,
6478 CODE_FOR_builtin_pkwb
,
6479 CODE_FOR_builtin_unpkbl
,
6480 CODE_FOR_builtin_unpkbw
,
6483 CODE_FOR_builtin_cttz
,
6484 CODE_FOR_builtin_ctlz
,
6485 CODE_FOR_builtin_ctpop
6488 struct alpha_builtin_def
6491 enum alpha_builtin code
;
6492 unsigned int target_mask
;
6495 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6496 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0 },
6497 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0 }
6500 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6501 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0 },
6502 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
},
6503 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
},
6504 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
},
6505 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
},
6506 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
},
6507 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
},
6508 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
}
6511 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6512 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0 },
6513 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0 },
6514 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0 },
6515 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0 },
6516 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0 },
6517 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0 },
6518 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0 },
6519 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0 },
6520 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0 },
6521 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0 },
6522 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0 },
6523 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0 },
6524 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0 },
6525 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0 },
6526 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0 },
6527 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0 },
6528 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0 },
6529 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0 },
6530 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0 },
6531 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0 },
6532 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0 },
6533 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0 },
6534 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0 },
6535 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0 },
6536 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0 },
6537 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
},
6538 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
},
6539 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
},
6540 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
},
6541 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
},
6542 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
},
6543 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
},
6544 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
},
6545 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
}
6549 alpha_init_builtins ()
6551 const struct alpha_builtin_def
*p
;
6555 ftype
= build_function_type (long_integer_type_node
, void_list_node
);
6557 p
= zero_arg_builtins
;
6558 for (i
= 0; i
< ARRAY_SIZE (zero_arg_builtins
); ++i
, ++p
)
6559 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6560 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6563 ftype
= build_function_type_list (long_integer_type_node
,
6564 long_integer_type_node
, NULL_TREE
);
6566 p
= one_arg_builtins
;
6567 for (i
= 0; i
< ARRAY_SIZE (one_arg_builtins
); ++i
, ++p
)
6568 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6569 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6572 ftype
= build_function_type_list (long_integer_type_node
,
6573 long_integer_type_node
,
6574 long_integer_type_node
, NULL_TREE
);
6576 p
= two_arg_builtins
;
6577 for (i
= 0; i
< ARRAY_SIZE (two_arg_builtins
); ++i
, ++p
)
6578 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6579 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6582 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6583 builtin_function ("__builtin_thread_pointer", ftype
,
6584 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
6587 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6588 builtin_function ("__builtin_set_thread_pointer", ftype
,
6589 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
6593 /* Expand an expression EXP that calls a built-in function,
6594 with result going to TARGET if that's convenient
6595 (and in mode MODE if that's convenient).
6596 SUBTARGET may be used as the target for computing one of EXP's operands.
6597 IGNORE is nonzero if the value is to be ignored. */
6600 alpha_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
6603 rtx subtarget ATTRIBUTE_UNUSED
;
6604 enum machine_mode mode ATTRIBUTE_UNUSED
;
6605 int ignore ATTRIBUTE_UNUSED
;
6609 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6610 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6611 tree arglist
= TREE_OPERAND (exp
, 1);
6612 enum insn_code icode
;
6613 rtx op
[MAX_ARGS
], pat
;
6617 if (fcode
>= ALPHA_BUILTIN_max
)
6618 internal_error ("bad builtin fcode");
6619 icode
= code_for_builtin
[fcode
];
6621 internal_error ("bad builtin fcode");
6623 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6625 for (arglist
= TREE_OPERAND (exp
, 1), arity
= 0;
6627 arglist
= TREE_CHAIN (arglist
), arity
++)
6629 const struct insn_operand_data
*insn_op
;
6631 tree arg
= TREE_VALUE (arglist
);
6632 if (arg
== error_mark_node
)
6634 if (arity
> MAX_ARGS
)
6637 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6639 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
6641 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6642 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6647 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6649 || GET_MODE (target
) != tmode
6650 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6651 target
= gen_reg_rtx (tmode
);
6657 pat
= GEN_FCN (icode
) (target
);
6661 pat
= GEN_FCN (icode
) (target
, op
[0]);
6663 pat
= GEN_FCN (icode
) (op
[0]);
6666 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6681 /* This page contains routines that are used to determine what the function
6682 prologue and epilogue code will do and write them out. */
6684 /* Compute the size of the save area in the stack. */
6686 /* These variables are used for communication between the following functions.
6687 They indicate various things about the current function being compiled
6688 that are used to tell what kind of prologue, epilogue and procedure
6689 descriptior to generate. */
6691 /* Nonzero if we need a stack procedure. */
6692 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
6693 static enum alpha_procedure_types alpha_procedure_type
;
6695 /* Register number (either FP or SP) that is used to unwind the frame. */
6696 static int vms_unwind_regno
;
6698 /* Register number used to save FP. We need not have one for RA since
6699 we don't modify it for register procedures. This is only defined
6700 for register frame procedures. */
6701 static int vms_save_fp_regno
;
6703 /* Register number used to reference objects off our PV. */
6704 static int vms_base_regno
;
6706 /* Compute register masks for saved registers. */
6709 alpha_sa_mask (imaskP
, fmaskP
)
6710 unsigned long *imaskP
;
6711 unsigned long *fmaskP
;
6713 unsigned long imask
= 0;
6714 unsigned long fmask
= 0;
6717 /* Irritatingly, there are two kinds of thunks -- those created with
6718 ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go through
6719 the regular part of the compiler. In the ASM_OUTPUT_MI_THUNK case
6720 we don't have valid register life info, but assemble_start_function
6721 wants to output .frame and .mask directives. */
6722 if (current_function_is_thunk
&& !no_new_pseudos
)
6729 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6730 imask
|= (1L << HARD_FRAME_POINTER_REGNUM
);
6732 /* One for every register we have to save. */
6733 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6734 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
6735 && regs_ever_live
[i
] && i
!= REG_RA
6736 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
6741 fmask
|= (1L << (i
- 32));
6744 /* We need to restore these for the handler. */
6745 if (current_function_calls_eh_return
)
6748 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
6749 if (regno
== INVALID_REGNUM
)
6751 imask
|= 1L << regno
;
6754 /* If any register spilled, then spill the return address also. */
6755 /* ??? This is required by the Digital stack unwind specification
6756 and isn't needed if we're doing Dwarf2 unwinding. */
6757 if (imask
|| fmask
|| alpha_ra_ever_killed ())
6758 imask
|= (1L << REG_RA
);
6767 unsigned long mask
[2];
6771 alpha_sa_mask (&mask
[0], &mask
[1]);
6773 if (TARGET_ABI_UNICOSMK
)
6775 if (mask
[0] || mask
[1])
6780 for (j
= 0; j
< 2; ++j
)
6781 for (i
= 0; i
< 32; ++i
)
6782 if ((mask
[j
] >> i
) & 1)
6786 if (TARGET_ABI_UNICOSMK
)
6788 /* We might not need to generate a frame if we don't make any calls
6789 (including calls to __T3E_MISMATCH if this is a vararg function),
6790 don't have any local variables which require stack slots, don't
6791 use alloca and have not determined that we need a frame for other
6794 alpha_procedure_type
6795 = (sa_size
|| get_frame_size() != 0
6796 || current_function_outgoing_args_size
6797 || current_function_stdarg
|| current_function_calls_alloca
6798 || frame_pointer_needed
)
6799 ? PT_STACK
: PT_REGISTER
;
6801 /* Always reserve space for saving callee-saved registers if we
6802 need a frame as required by the calling convention. */
6803 if (alpha_procedure_type
== PT_STACK
)
6806 else if (TARGET_ABI_OPEN_VMS
)
6808 /* Start by assuming we can use a register procedure if we don't
6809 make any calls (REG_RA not used) or need to save any
6810 registers and a stack procedure if we do. */
6811 if ((mask
[0] >> REG_RA
) & 1)
6812 alpha_procedure_type
= PT_STACK
;
6813 else if (get_frame_size() != 0)
6814 alpha_procedure_type
= PT_REGISTER
;
6816 alpha_procedure_type
= PT_NULL
;
6818 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6819 made the final decision on stack procedure vs register procedure. */
6820 if (alpha_procedure_type
== PT_STACK
)
6823 /* Decide whether to refer to objects off our PV via FP or PV.
6824 If we need FP for something else or if we receive a nonlocal
6825 goto (which expects PV to contain the value), we must use PV.
6826 Otherwise, start by assuming we can use FP. */
6829 = (frame_pointer_needed
6830 || current_function_has_nonlocal_label
6831 || alpha_procedure_type
== PT_STACK
6832 || current_function_outgoing_args_size
)
6833 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
6835 /* If we want to copy PV into FP, we need to find some register
6836 in which to save FP. */
6838 vms_save_fp_regno
= -1;
6839 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
6840 for (i
= 0; i
< 32; i
++)
6841 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
6842 vms_save_fp_regno
= i
;
6844 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
6845 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
6846 else if (alpha_procedure_type
== PT_NULL
)
6847 vms_base_regno
= REG_PV
;
6849 /* Stack unwinding should be done via FP unless we use it for PV. */
6850 vms_unwind_regno
= (vms_base_regno
== REG_PV
6851 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
6853 /* If this is a stack procedure, allow space for saving FP and RA. */
6854 if (alpha_procedure_type
== PT_STACK
)
6859 /* Our size must be even (multiple of 16 bytes). */
6868 alpha_pv_save_size ()
6871 return alpha_procedure_type
== PT_STACK
? 8 : 0;
6878 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
6881 #if TARGET_ABI_OPEN_VMS
6883 const struct attribute_spec vms_attribute_table
[] =
6885 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6886 { "overlaid", 0, 0, true, false, false, NULL
},
6887 { "global", 0, 0, true, false, false, NULL
},
6888 { "initialize", 0, 0, true, false, false, NULL
},
6889 { NULL
, 0, 0, false, false, false, NULL
}
6895 find_lo_sum (px
, data
)
6897 void *data ATTRIBUTE_UNUSED
;
6899 return GET_CODE (*px
) == LO_SUM
;
6903 alpha_does_function_need_gp ()
6907 /* The GP being variable is an OSF abi thing. */
6908 if (! TARGET_ABI_OSF
)
6911 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6914 if (current_function_is_thunk
)
6917 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6918 Even if we are a static function, we still need to do this in case
6919 our address is taken and passed to something like qsort. */
6921 push_topmost_sequence ();
6922 insn
= get_insns ();
6923 pop_topmost_sequence ();
6925 for (; insn
; insn
= NEXT_INSN (insn
))
6927 && GET_CODE (PATTERN (insn
)) != USE
6928 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6930 enum attr_type type
= get_attr_type (insn
);
6931 if (type
== TYPE_LDSYM
|| type
== TYPE_JSR
)
6933 if (TARGET_EXPLICIT_RELOCS
6934 && for_each_rtx (&PATTERN (insn
), find_lo_sum
, NULL
) > 0)
6941 /* Write a version stamp. Don't write anything if we are running as a
6942 cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
6949 alpha_write_verstamp (file
)
6950 FILE *file ATTRIBUTE_UNUSED
;
6953 fprintf (file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
6957 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6961 set_frame_related_p ()
6963 rtx seq
= get_insns ();
6974 while (insn
!= NULL_RTX
)
6976 RTX_FRAME_RELATED_P (insn
) = 1;
6977 insn
= NEXT_INSN (insn
);
6979 seq
= emit_insn (seq
);
6983 seq
= emit_insn (seq
);
6984 RTX_FRAME_RELATED_P (seq
) = 1;
6989 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
6991 /* Write function prologue. */
6993 /* On vms we have two kinds of functions:
6995 - stack frame (PROC_STACK)
6996 these are 'normal' functions with local vars and which are
6997 calling other functions
6998 - register frame (PROC_REGISTER)
6999 keeps all data in registers, needs no stack
7001 We must pass this to the assembler so it can generate the
7002 proper pdsc (procedure descriptor)
7003 This is done with the '.pdesc' command.
7005 On not-vms, we don't really differentiate between the two, as we can
7006 simply allocate stack without saving registers. */
7009 alpha_expand_prologue ()
7011 /* Registers to save. */
7012 unsigned long imask
= 0;
7013 unsigned long fmask
= 0;
7014 /* Stack space needed for pushing registers clobbered by us. */
7015 HOST_WIDE_INT sa_size
;
7016 /* Complete stack size needed. */
7017 HOST_WIDE_INT frame_size
;
7018 /* Offset from base reg to register save area. */
7019 HOST_WIDE_INT reg_offset
;
7023 sa_size
= alpha_sa_size ();
7025 frame_size
= get_frame_size ();
7026 if (TARGET_ABI_OPEN_VMS
)
7027 frame_size
= ALPHA_ROUND (sa_size
7028 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7030 + current_function_pretend_args_size
);
7031 else if (TARGET_ABI_UNICOSMK
)
7032 /* We have to allocate space for the DSIB if we generate a frame. */
7033 frame_size
= ALPHA_ROUND (sa_size
7034 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7035 + ALPHA_ROUND (frame_size
7036 + current_function_outgoing_args_size
);
7038 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7040 + ALPHA_ROUND (frame_size
7041 + current_function_pretend_args_size
));
7043 if (TARGET_ABI_OPEN_VMS
)
7046 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7048 alpha_sa_mask (&imask
, &fmask
);
7050 /* Emit an insn to reload GP, if needed. */
7053 alpha_function_needs_gp
= alpha_does_function_need_gp ();
7054 if (alpha_function_needs_gp
)
7055 emit_insn (gen_prologue_ldgp ());
7058 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7059 the call to mcount ourselves, rather than having the linker do it
7060 magically in response to -pg. Since _mcount has special linkage,
7061 don't represent the call as a call. */
7062 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7063 emit_insn (gen_prologue_mcount ());
7065 if (TARGET_ABI_UNICOSMK
)
7066 unicosmk_gen_dsib (&imask
);
7068 /* Adjust the stack by the frame size. If the frame size is > 4096
7069 bytes, we need to be sure we probe somewhere in the first and last
7070 4096 bytes (we can probably get away without the latter test) and
7071 every 8192 bytes in between. If the frame size is > 32768, we
7072 do this in a loop. Otherwise, we generate the explicit probe
7075 Note that we are only allowed to adjust sp once in the prologue. */
7077 if (frame_size
<= 32768)
7079 if (frame_size
> 4096)
7084 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7087 while ((probed
+= 8192) < frame_size
);
7089 /* We only have to do this probe if we aren't saving registers. */
7090 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
7091 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
7094 if (frame_size
!= 0)
7095 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7096 GEN_INT (TARGET_ABI_UNICOSMK
7102 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7103 number of 8192 byte blocks to probe. We then probe each block
7104 in the loop and then set SP to the proper location. If the
7105 amount remaining is > 4096, we have to do one more probe if we
7106 are not saving any registers. */
7108 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
7109 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
7110 rtx ptr
= gen_rtx_REG (DImode
, 22);
7111 rtx count
= gen_rtx_REG (DImode
, 23);
7114 emit_move_insn (count
, GEN_INT (blocks
));
7115 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7116 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7118 /* Because of the difficulty in emitting a new basic block this
7119 late in the compilation, generate the loop as a single insn. */
7120 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7122 if (leftover
> 4096 && sa_size
== 0)
7124 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7125 MEM_VOLATILE_P (last
) = 1;
7126 emit_move_insn (last
, const0_rtx
);
7129 if (TARGET_ABI_WINDOWS_NT
)
7131 /* For NT stack unwind (done by 'reverse execution'), it's
7132 not OK to take the result of a loop, even though the value
7133 is already in ptr, so we reload it via a single operation
7134 and subtract it to sp.
7136 Yes, that's correct -- we have to reload the whole constant
7137 into a temporary via ldah+lda then subtract from sp. To
7138 ensure we get ldah+lda, we use a special pattern. */
7140 HOST_WIDE_INT lo
, hi
;
7141 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7142 hi
= frame_size
- lo
;
7144 emit_move_insn (ptr
, GEN_INT (hi
));
7145 emit_insn (gen_nt_lda (ptr
, GEN_INT (lo
)));
7146 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7151 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7152 GEN_INT (-leftover
)));
7155 /* This alternative is special, because the DWARF code cannot
7156 possibly intuit through the loop above. So we invent this
7157 note it looks at instead. */
7158 RTX_FRAME_RELATED_P (seq
) = 1;
7160 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7161 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7162 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7163 GEN_INT (TARGET_ABI_UNICOSMK
7169 if (!TARGET_ABI_UNICOSMK
)
7171 /* Cope with very large offsets to the register save area. */
7172 sa_reg
= stack_pointer_rtx
;
7173 if (reg_offset
+ sa_size
> 0x8000)
7175 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7178 if (low
+ sa_size
<= 0x8000)
7179 bias
= reg_offset
- low
, reg_offset
= low
;
7181 bias
= reg_offset
, reg_offset
= 0;
7183 sa_reg
= gen_rtx_REG (DImode
, 24);
7184 FRP (emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
,
7188 /* Save regs in stack order. Beginning with VMS PV. */
7189 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7191 mem
= gen_rtx_MEM (DImode
, stack_pointer_rtx
);
7192 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7193 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_PV
)));
7196 /* Save register RA next. */
7197 if (imask
& (1L << REG_RA
))
7199 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7200 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7201 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
7202 imask
&= ~(1L << REG_RA
);
7206 /* Now save any other registers required to be saved. */
7207 for (i
= 0; i
< 32; i
++)
7208 if (imask
& (1L << i
))
7210 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7211 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7212 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7216 for (i
= 0; i
< 32; i
++)
7217 if (fmask
& (1L << i
))
7219 mem
= gen_rtx_MEM (DFmode
, plus_constant (sa_reg
, reg_offset
));
7220 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7221 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7225 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7227 /* The standard frame on the T3E includes space for saving registers.
7228 We just have to use it. We don't have to save the return address and
7229 the old frame pointer here - they are saved in the DSIB. */
7232 for (i
= 9; i
< 15; i
++)
7233 if (imask
& (1L << i
))
7235 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7237 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7238 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7241 for (i
= 2; i
< 10; i
++)
7242 if (fmask
& (1L << i
))
7244 mem
= gen_rtx_MEM (DFmode
, plus_constant (hard_frame_pointer_rtx
,
7246 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7247 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7252 if (TARGET_ABI_OPEN_VMS
)
7254 if (alpha_procedure_type
== PT_REGISTER
)
7255 /* Register frame procedures save the fp.
7256 ?? Ought to have a dwarf2 save for this. */
7257 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7258 hard_frame_pointer_rtx
);
7260 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7261 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7262 gen_rtx_REG (DImode
, REG_PV
)));
7264 if (alpha_procedure_type
!= PT_NULL
7265 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7266 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7268 /* If we have to allocate space for outgoing args, do it now. */
7269 if (current_function_outgoing_args_size
!= 0)
7272 plus_constant (hard_frame_pointer_rtx
,
7274 (current_function_outgoing_args_size
)))));
7276 else if (!TARGET_ABI_UNICOSMK
)
7278 /* If we need a frame pointer, set it from the stack pointer. */
7279 if (frame_pointer_needed
)
7281 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7282 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7284 /* This must always be the last instruction in the
7285 prologue, thus we emit a special move + clobber. */
7286 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7287 stack_pointer_rtx
, sa_reg
)));
7291 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7292 the prologue, for exception handling reasons, we cannot do this for
7293 any insn that might fault. We could prevent this for mems with a
7294 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7295 have to prevent all such scheduling with a blockage.
7297 Linux, on the other hand, never bothered to implement OSF/1's
7298 exception handling, and so doesn't care about such things. Anyone
7299 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7301 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7302 emit_insn (gen_blockage ());
7305 /* Output the textual info surrounding the prologue. */
7308 alpha_start_function (file
, fnname
, decl
)
7311 tree decl ATTRIBUTE_UNUSED
;
7313 unsigned long imask
= 0;
7314 unsigned long fmask
= 0;
7315 /* Stack space needed for pushing registers clobbered by us. */
7316 HOST_WIDE_INT sa_size
;
7317 /* Complete stack size needed. */
7318 HOST_WIDE_INT frame_size
;
7319 /* Offset from base reg to register save area. */
7320 HOST_WIDE_INT reg_offset
;
7321 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7324 /* Don't emit an extern directive for functions defined in the same file. */
7325 if (TARGET_ABI_UNICOSMK
)
7328 name_tree
= get_identifier (fnname
);
7329 TREE_ASM_WRITTEN (name_tree
) = 1;
7332 alpha_fnname
= fnname
;
7333 sa_size
= alpha_sa_size ();
7335 frame_size
= get_frame_size ();
7336 if (TARGET_ABI_OPEN_VMS
)
7337 frame_size
= ALPHA_ROUND (sa_size
7338 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7340 + current_function_pretend_args_size
);
7341 else if (TARGET_ABI_UNICOSMK
)
7342 frame_size
= ALPHA_ROUND (sa_size
7343 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7344 + ALPHA_ROUND (frame_size
7345 + current_function_outgoing_args_size
);
7347 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7349 + ALPHA_ROUND (frame_size
7350 + current_function_pretend_args_size
));
7352 if (TARGET_ABI_OPEN_VMS
)
7355 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7357 alpha_sa_mask (&imask
, &fmask
);
7359 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7360 We have to do that before the .ent directive as we cannot switch
7361 files within procedures with native ecoff because line numbers are
7362 linked to procedure descriptors.
7363 Outputting the lineno helps debugging of one line functions as they
7364 would otherwise get no line number at all. Please note that we would
7365 like to put out last_linenum from final.c, but it is not accessible. */
7367 if (write_symbols
== SDB_DEBUG
)
7369 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7370 ASM_OUTPUT_SOURCE_FILENAME (file
,
7371 DECL_SOURCE_FILE (current_function_decl
));
7373 #ifdef ASM_OUTPUT_SOURCE_LINE
7374 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7375 ASM_OUTPUT_SOURCE_LINE (file
,
7376 DECL_SOURCE_LINE (current_function_decl
));
7380 /* Issue function start and label. */
7381 if (TARGET_ABI_OPEN_VMS
7382 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
7384 fputs ("\t.ent ", file
);
7385 assemble_name (file
, fnname
);
7388 /* If the function needs GP, we'll write the "..ng" label there.
7389 Otherwise, do it here. */
7391 && ! alpha_function_needs_gp
7392 && ! current_function_is_thunk
)
7395 assemble_name (file
, fnname
);
7396 fputs ("..ng:\n", file
);
7400 strcpy (entry_label
, fnname
);
7401 if (TARGET_ABI_OPEN_VMS
)
7402 strcat (entry_label
, "..en");
7404 /* For public functions, the label must be globalized by appending an
7405 additional colon. */
7406 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
7407 strcat (entry_label
, ":");
7409 ASM_OUTPUT_LABEL (file
, entry_label
);
7410 inside_function
= TRUE
;
7412 if (TARGET_ABI_OPEN_VMS
)
7413 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7415 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7416 && !flag_inhibit_size_directive
)
7418 /* Set flags in procedure descriptor to request IEEE-conformant
7419 math-library routines. The value we set it to is PDSC_EXC_IEEE
7420 (/usr/include/pdsc.h). */
7421 fputs ("\t.eflag 48\n", file
);
7424 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7425 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
7426 alpha_arg_offset
= -frame_size
+ 48;
7428 /* Describe our frame. If the frame size is larger than an integer,
7429 print it as zero to avoid an assembler error. We won't be
7430 properly describing such a frame, but that's the best we can do. */
7431 if (TARGET_ABI_UNICOSMK
)
7433 else if (TARGET_ABI_OPEN_VMS
)
7435 fprintf (file
, "\t.frame $%d,", vms_unwind_regno
);
7436 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7437 frame_size
>= ((HOST_WIDE_INT
) 1 << 31) ? 0 : frame_size
);
7438 fputs (",$26,", file
);
7439 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, reg_offset
);
7442 else if (!flag_inhibit_size_directive
)
7444 fprintf (file
, "\t.frame $%d,",
7445 (frame_pointer_needed
7446 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
));
7447 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7448 frame_size
>= (1l << 31) ? 0 : frame_size
);
7449 fprintf (file
, ",$26,%d\n", current_function_pretend_args_size
);
7452 /* Describe which registers were spilled. */
7453 if (TARGET_ABI_UNICOSMK
)
7455 else if (TARGET_ABI_OPEN_VMS
)
7458 /* ??? Does VMS care if mask contains ra? The old code didn't
7459 set it, so I don't here. */
7460 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1L << REG_RA
));
7462 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7463 if (alpha_procedure_type
== PT_REGISTER
)
7464 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7466 else if (!flag_inhibit_size_directive
)
7470 fprintf (file
, "\t.mask 0x%lx,", imask
);
7471 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7472 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
7475 for (i
= 0; i
< 32; ++i
)
7476 if (imask
& (1L << i
))
7482 fprintf (file
, "\t.fmask 0x%lx,", fmask
);
7483 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7484 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
7489 #if TARGET_ABI_OPEN_VMS
7490 /* Ifdef'ed cause link_section are only available then. */
7491 readonly_data_section ();
7492 fprintf (file
, "\t.align 3\n");
7493 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
7494 fputs ("\t.ascii \"", file
);
7495 assemble_name (file
, fnname
);
7496 fputs ("\\0\"\n", file
);
7497 alpha_need_linkage (fnname
, 1);
7502 /* Emit the .prologue note at the scheduled end of the prologue. */
7505 alpha_output_function_end_prologue (file
)
7508 if (TARGET_ABI_UNICOSMK
)
7510 else if (TARGET_ABI_OPEN_VMS
)
7511 fputs ("\t.prologue\n", file
);
7512 else if (TARGET_ABI_WINDOWS_NT
)
7513 fputs ("\t.prologue 0\n", file
);
7514 else if (!flag_inhibit_size_directive
)
7515 fprintf (file
, "\t.prologue %d\n",
7516 alpha_function_needs_gp
|| current_function_is_thunk
);
7519 /* Write function epilogue. */
7521 /* ??? At some point we will want to support full unwind, and so will
7522 need to mark the epilogue as well. At the moment, we just confuse
7525 #define FRP(exp) exp
7528 alpha_expand_epilogue ()
7530 /* Registers to save. */
7531 unsigned long imask
= 0;
7532 unsigned long fmask
= 0;
7533 /* Stack space needed for pushing registers clobbered by us. */
7534 HOST_WIDE_INT sa_size
;
7535 /* Complete stack size needed. */
7536 HOST_WIDE_INT frame_size
;
7537 /* Offset from base reg to register save area. */
7538 HOST_WIDE_INT reg_offset
;
7539 int fp_is_frame_pointer
, fp_offset
;
7540 rtx sa_reg
, sa_reg_exp
= NULL
;
7541 rtx sp_adj1
, sp_adj2
, mem
;
7545 sa_size
= alpha_sa_size ();
7547 frame_size
= get_frame_size ();
7548 if (TARGET_ABI_OPEN_VMS
)
7549 frame_size
= ALPHA_ROUND (sa_size
7550 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7552 + current_function_pretend_args_size
);
7553 else if (TARGET_ABI_UNICOSMK
)
7554 frame_size
= ALPHA_ROUND (sa_size
7555 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7556 + ALPHA_ROUND (frame_size
7557 + current_function_outgoing_args_size
);
7559 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7561 + ALPHA_ROUND (frame_size
7562 + current_function_pretend_args_size
));
7564 if (TARGET_ABI_OPEN_VMS
)
7566 if (alpha_procedure_type
== PT_STACK
)
7572 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7574 alpha_sa_mask (&imask
, &fmask
);
7577 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7578 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
7580 sa_reg
= stack_pointer_rtx
;
7582 if (current_function_calls_eh_return
)
7583 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7587 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
7589 /* If we have a frame pointer, restore SP from it. */
7590 if ((TARGET_ABI_OPEN_VMS
7591 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7592 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
7593 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7595 /* Cope with very large offsets to the register save area. */
7596 if (reg_offset
+ sa_size
> 0x8000)
7598 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7601 if (low
+ sa_size
<= 0x8000)
7602 bias
= reg_offset
- low
, reg_offset
= low
;
7604 bias
= reg_offset
, reg_offset
= 0;
7606 sa_reg
= gen_rtx_REG (DImode
, 22);
7607 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
7609 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
7612 /* Restore registers in order, excepting a true frame pointer. */
7614 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7616 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7617 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7620 imask
&= ~(1L << REG_RA
);
7622 for (i
= 0; i
< 32; ++i
)
7623 if (imask
& (1L << i
))
7625 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
7626 fp_offset
= reg_offset
;
7629 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
7630 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7631 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7636 for (i
= 0; i
< 32; ++i
)
7637 if (fmask
& (1L << i
))
7639 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
7640 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7641 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7645 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7647 /* Restore callee-saved general-purpose registers. */
7651 for (i
= 9; i
< 15; i
++)
7652 if (imask
& (1L << i
))
7654 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7656 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7657 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7661 for (i
= 2; i
< 10; i
++)
7662 if (fmask
& (1L << i
))
7664 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
7666 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7667 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7671 /* Restore the return address from the DSIB. */
7673 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
7674 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7675 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7678 if (frame_size
|| eh_ofs
)
7680 sp_adj1
= stack_pointer_rtx
;
7684 sp_adj1
= gen_rtx_REG (DImode
, 23);
7685 emit_move_insn (sp_adj1
,
7686 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
7689 /* If the stack size is large, begin computation into a temporary
7690 register so as not to interfere with a potential fp restore,
7691 which must be consecutive with an SP restore. */
7692 if (frame_size
< 32768
7693 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
7694 sp_adj2
= GEN_INT (frame_size
);
7695 else if (TARGET_ABI_UNICOSMK
)
7697 sp_adj1
= gen_rtx_REG (DImode
, 23);
7698 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
7699 sp_adj2
= const0_rtx
;
7701 else if (frame_size
< 0x40007fffL
)
7703 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7705 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
7706 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
7710 sp_adj1
= gen_rtx_REG (DImode
, 23);
7711 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
7713 sp_adj2
= GEN_INT (low
);
7717 rtx tmp
= gen_rtx_REG (DImode
, 23);
7718 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
7721 /* We can't drop new things to memory this late, afaik,
7722 so build it up by pieces. */
7723 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
7724 -(frame_size
< 0)));
7730 /* From now on, things must be in order. So emit blockages. */
7732 /* Restore the frame pointer. */
7733 if (TARGET_ABI_UNICOSMK
)
7735 emit_insn (gen_blockage ());
7736 mem
= gen_rtx_MEM (DImode
,
7737 plus_constant (hard_frame_pointer_rtx
, -16));
7738 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7739 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7741 else if (fp_is_frame_pointer
)
7743 emit_insn (gen_blockage ());
7744 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
7745 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7746 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7748 else if (TARGET_ABI_OPEN_VMS
)
7750 emit_insn (gen_blockage ());
7751 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7752 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7755 /* Restore the stack pointer. */
7756 emit_insn (gen_blockage ());
7757 if (sp_adj2
== const0_rtx
)
7758 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
7760 FRP (emit_move_insn (stack_pointer_rtx
,
7761 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
7765 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
7767 emit_insn (gen_blockage ());
7768 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7769 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7771 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
7773 /* Decrement the frame pointer if the function does not have a
7776 emit_insn (gen_blockage ());
7777 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7778 hard_frame_pointer_rtx
, GEN_INT (-1))));
7783 #if TARGET_ABI_OPEN_VMS
7784 #include <splay-tree.h>
7786 /* Structure to collect function names for final output
7789 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
7790 enum reloc_kind
{KIND_LINKAGE
, KIND_CODEADDR
};
7802 enum links_kind lkind
;
7803 enum reloc_kind rkind
;
7806 static splay_tree alpha_funcs_tree
;
7807 static splay_tree alpha_links_tree
;
7809 static int mark_alpha_links_node
PARAMS ((splay_tree_node
, void *));
7810 static void mark_alpha_links
PARAMS ((void *));
7811 static int alpha_write_one_linkage
PARAMS ((splay_tree_node
, void *));
7813 static int alpha_funcs_num
;
7816 /* Output the rest of the textual info surrounding the epilogue. */
7819 alpha_end_function (file
, fnname
, decl
)
7824 /* End the function. */
7825 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
7827 fputs ("\t.end ", file
);
7828 assemble_name (file
, fnname
);
7831 inside_function
= FALSE
;
7833 #if TARGET_ABI_OPEN_VMS
7834 alpha_write_linkage (file
, fnname
, decl
);
7837 /* Show that we know this function if it is called again.
7839 Do this only for functions whose symbols bind locally.
7841 Don't do this for functions not defined in the .text section, as
7842 otherwise it's not unlikely that the destination is out of range
7843 for a direct branch. */
7845 if ((*targetm
.binds_local_p
) (decl
) && decl_in_text_section (decl
))
7846 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl
), 0)) = 1;
7848 /* Output jump tables and the static subroutine information block. */
7849 if (TARGET_ABI_UNICOSMK
)
7851 unicosmk_output_ssib (file
, fnname
);
7852 unicosmk_output_deferred_case_vectors (file
);
7856 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7858 In order to avoid the hordes of differences between generated code
7859 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7860 lots of code loading up large constants, generate rtl and emit it
7861 instead of going straight to text.
7863 Not sure why this idea hasn't been explored before... */
7866 alpha_output_mi_thunk_osf (file
, thunk_fndecl
, delta
, function
)
7868 tree thunk_fndecl ATTRIBUTE_UNUSED
;
7869 HOST_WIDE_INT delta
;
7872 HOST_WIDE_INT hi
, lo
;
7873 rtx
this, insn
, funexp
;
7875 /* We always require a valid GP. */
7876 emit_insn (gen_prologue_ldgp ());
7877 emit_note (NULL
, NOTE_INSN_PROLOGUE_END
);
7879 /* Find the "this" pointer. If the function returns a structure,
7880 the structure return pointer is in $16. */
7881 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
))))
7882 this = gen_rtx_REG (Pmode
, 17);
7884 this = gen_rtx_REG (Pmode
, 16);
7886 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7887 entire constant for the add. */
7888 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
7889 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7890 if (hi
+ lo
== delta
)
7893 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
7895 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
7899 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
7900 delta
, -(delta
< 0));
7901 emit_insn (gen_adddi3 (this, this, tmp
));
7904 /* Generate a tail call to the target function. */
7905 if (! TREE_USED (function
))
7907 assemble_external (function
);
7908 TREE_USED (function
) = 1;
7910 funexp
= XEXP (DECL_RTL (function
), 0);
7911 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
7912 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
7913 SIBLING_CALL_P (insn
) = 1;
7915 /* Run just enough of rest_of_compilation to get the insns emitted.
7916 There's not really enough bulk here to make other passes such as
7917 instruction scheduling worth while. Note that use_thunk calls
7918 assemble_start_function and assemble_end_function. */
7919 insn
= get_insns ();
7920 shorten_branches (insn
);
7921 final_start_function (insn
, file
, 1);
7922 final (insn
, file
, 1, 0);
7923 final_end_function ();
7926 /* Debugging support. */
7930 /* Count the number of sdb related labels are generated (to find block
7931 start and end boundaries). */
7933 int sdb_label_count
= 0;
7935 /* Next label # for each statement. */
7937 static int sym_lineno
= 0;
7939 /* Count the number of .file directives, so that .loc is up to date. */
7941 static int num_source_filenames
= 0;
7943 /* Name of the file containing the current function. */
7945 static const char *current_function_file
= "";
7947 /* Offsets to alpha virtual arg/local debugging pointers. */
7949 long alpha_arg_offset
;
7950 long alpha_auto_offset
;
7952 /* Emit a new filename to a stream. */
7955 alpha_output_filename (stream
, name
)
7959 static int first_time
= TRUE
;
7960 char ltext_label_name
[100];
7965 ++num_source_filenames
;
7966 current_function_file
= name
;
7967 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7968 output_quoted_string (stream
, name
);
7969 fprintf (stream
, "\n");
7970 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
7971 fprintf (stream
, "\t#@stabs\n");
7974 else if (write_symbols
== DBX_DEBUG
)
7976 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
7977 fprintf (stream
, "%s", ASM_STABS_OP
);
7978 output_quoted_string (stream
, name
);
7979 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
7982 else if (name
!= current_function_file
7983 && strcmp (name
, current_function_file
) != 0)
7985 if (inside_function
&& ! TARGET_GAS
)
7986 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
7989 ++num_source_filenames
;
7990 current_function_file
= name
;
7991 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7994 output_quoted_string (stream
, name
);
7995 fprintf (stream
, "\n");
7999 /* Emit a linenumber to a stream. */
8002 alpha_output_lineno (stream
, line
)
8006 if (write_symbols
== DBX_DEBUG
)
8008 /* mips-tfile doesn't understand .stabd directives. */
8010 fprintf (stream
, "$LM%d:\n%s%d,0,%d,$LM%d\n",
8011 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
8014 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
8017 /* Structure to show the current status of registers and memory. */
8019 struct shadow_summary
8022 unsigned int i
: 31; /* Mask of int regs */
8023 unsigned int fp
: 31; /* Mask of fp regs */
8024 unsigned int mem
: 1; /* mem == imem | fpmem */
8028 static void summarize_insn
PARAMS ((rtx
, struct shadow_summary
*, int));
8029 static void alpha_handle_trap_shadows
PARAMS ((rtx
));
8031 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8032 to the summary structure. SET is nonzero if the insn is setting the
8033 object, otherwise zero. */
8036 summarize_insn (x
, sum
, set
)
8038 struct shadow_summary
*sum
;
8041 const char *format_ptr
;
8047 switch (GET_CODE (x
))
8049 /* ??? Note that this case would be incorrect if the Alpha had a
8050 ZERO_EXTRACT in SET_DEST. */
8052 summarize_insn (SET_SRC (x
), sum
, 0);
8053 summarize_insn (SET_DEST (x
), sum
, 1);
8057 summarize_insn (XEXP (x
, 0), sum
, 1);
8061 summarize_insn (XEXP (x
, 0), sum
, 0);
8065 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
8066 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
8070 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
8071 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
8075 summarize_insn (SUBREG_REG (x
), sum
, 0);
8080 int regno
= REGNO (x
);
8081 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
8083 if (regno
== 31 || regno
== 63)
8089 sum
->defd
.i
|= mask
;
8091 sum
->defd
.fp
|= mask
;
8096 sum
->used
.i
|= mask
;
8098 sum
->used
.fp
|= mask
;
8109 /* Find the regs used in memory address computation: */
8110 summarize_insn (XEXP (x
, 0), sum
, 0);
8113 case CONST_INT
: case CONST_DOUBLE
:
8114 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8115 case SCRATCH
: case ASM_INPUT
:
8118 /* Handle common unary and binary ops for efficiency. */
8119 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8120 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8121 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8122 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8123 case NE
: case EQ
: case GE
: case GT
: case LE
:
8124 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8125 summarize_insn (XEXP (x
, 0), sum
, 0);
8126 summarize_insn (XEXP (x
, 1), sum
, 0);
8129 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8130 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8131 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8132 case SQRT
: case FFS
:
8133 summarize_insn (XEXP (x
, 0), sum
, 0);
8137 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8138 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8139 switch (format_ptr
[i
])
8142 summarize_insn (XEXP (x
, i
), sum
, 0);
8146 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8147 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8159 /* Ensure a sufficient number of `trapb' insns are in the code when
8160 the user requests code with a trap precision of functions or
8163 In naive mode, when the user requests a trap-precision of
8164 "instruction", a trapb is needed after every instruction that may
8165 generate a trap. This ensures that the code is resumption safe but
8168 When optimizations are turned on, we delay issuing a trapb as long
8169 as possible. In this context, a trap shadow is the sequence of
8170 instructions that starts with a (potentially) trap generating
8171 instruction and extends to the next trapb or call_pal instruction
8172 (but GCC never generates call_pal by itself). We can delay (and
8173 therefore sometimes omit) a trapb subject to the following
8176 (a) On entry to the trap shadow, if any Alpha register or memory
8177 location contains a value that is used as an operand value by some
8178 instruction in the trap shadow (live on entry), then no instruction
8179 in the trap shadow may modify the register or memory location.
8181 (b) Within the trap shadow, the computation of the base register
8182 for a memory load or store instruction may not involve using the
8183 result of an instruction that might generate an UNPREDICTABLE
8186 (c) Within the trap shadow, no register may be used more than once
8187 as a destination register. (This is to make life easier for the
8190 (d) The trap shadow may not include any branch instructions. */
8193 alpha_handle_trap_shadows (insns
)
8196 struct shadow_summary shadow
;
8197 int trap_pending
, exception_nesting
;
8201 exception_nesting
= 0;
8204 shadow
.used
.mem
= 0;
8205 shadow
.defd
= shadow
.used
;
8207 for (i
= insns
; i
; i
= NEXT_INSN (i
))
8209 if (GET_CODE (i
) == NOTE
)
8211 switch (NOTE_LINE_NUMBER (i
))
8213 case NOTE_INSN_EH_REGION_BEG
:
8214 exception_nesting
++;
8219 case NOTE_INSN_EH_REGION_END
:
8220 exception_nesting
--;
8225 case NOTE_INSN_EPILOGUE_BEG
:
8226 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8231 else if (trap_pending
)
8233 if (alpha_tp
== ALPHA_TP_FUNC
)
8235 if (GET_CODE (i
) == JUMP_INSN
8236 && GET_CODE (PATTERN (i
)) == RETURN
)
8239 else if (alpha_tp
== ALPHA_TP_INSN
)
8243 struct shadow_summary sum
;
8248 sum
.defd
= sum
.used
;
8250 switch (GET_CODE (i
))
8253 /* Annoyingly, get_attr_trap will abort on these. */
8254 if (GET_CODE (PATTERN (i
)) == USE
8255 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8258 summarize_insn (PATTERN (i
), &sum
, 0);
8260 if ((sum
.defd
.i
& shadow
.defd
.i
)
8261 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8263 /* (c) would be violated */
8267 /* Combine shadow with summary of current insn: */
8268 shadow
.used
.i
|= sum
.used
.i
;
8269 shadow
.used
.fp
|= sum
.used
.fp
;
8270 shadow
.used
.mem
|= sum
.used
.mem
;
8271 shadow
.defd
.i
|= sum
.defd
.i
;
8272 shadow
.defd
.fp
|= sum
.defd
.fp
;
8273 shadow
.defd
.mem
|= sum
.defd
.mem
;
8275 if ((sum
.defd
.i
& shadow
.used
.i
)
8276 || (sum
.defd
.fp
& shadow
.used
.fp
)
8277 || (sum
.defd
.mem
& shadow
.used
.mem
))
8279 /* (a) would be violated (also takes care of (b)) */
8280 if (get_attr_trap (i
) == TRAP_YES
8281 && ((sum
.defd
.i
& sum
.used
.i
)
8282 || (sum
.defd
.fp
& sum
.used
.fp
)))
8301 n
= emit_insn_before (gen_trapb (), i
);
8302 PUT_MODE (n
, TImode
);
8303 PUT_MODE (i
, TImode
);
8307 shadow
.used
.mem
= 0;
8308 shadow
.defd
= shadow
.used
;
8313 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8314 && GET_CODE (i
) == INSN
8315 && GET_CODE (PATTERN (i
)) != USE
8316 && GET_CODE (PATTERN (i
)) != CLOBBER
8317 && get_attr_trap (i
) == TRAP_YES
)
8319 if (optimize
&& !trap_pending
)
8320 summarize_insn (PATTERN (i
), &shadow
, 0);
8326 /* Alpha can only issue instruction groups simultaneously if they are
8327 suitibly aligned. This is very processor-specific. */
8329 enum alphaev4_pipe
{
8336 enum alphaev5_pipe
{
8347 static enum alphaev4_pipe alphaev4_insn_pipe
PARAMS ((rtx
));
8348 static enum alphaev5_pipe alphaev5_insn_pipe
PARAMS ((rtx
));
8349 static rtx alphaev4_next_group
PARAMS ((rtx
, int *, int *));
8350 static rtx alphaev5_next_group
PARAMS ((rtx
, int *, int *));
8351 static rtx alphaev4_next_nop
PARAMS ((int *));
8352 static rtx alphaev5_next_nop
PARAMS ((int *));
8354 static void alpha_align_insns
8355 PARAMS ((rtx
, unsigned int, rtx (*)(rtx
, int *, int *), rtx (*)(int *)));
8357 static enum alphaev4_pipe
8358 alphaev4_insn_pipe (insn
)
8361 if (recog_memoized (insn
) < 0)
8363 if (get_attr_length (insn
) != 4)
8366 switch (get_attr_type (insn
))
8400 static enum alphaev5_pipe
8401 alphaev5_insn_pipe (insn
)
8404 if (recog_memoized (insn
) < 0)
8406 if (get_attr_length (insn
) != 4)
8409 switch (get_attr_type (insn
))
8450 /* IN_USE is a mask of the slots currently filled within the insn group.
8451 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8452 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8454 LEN is, of course, the length of the group in bytes. */
8457 alphaev4_next_group (insn
, pin_use
, plen
)
8459 int *pin_use
, *plen
;
8466 || GET_CODE (PATTERN (insn
)) == CLOBBER
8467 || GET_CODE (PATTERN (insn
)) == USE
)
8472 enum alphaev4_pipe pipe
;
8474 pipe
= alphaev4_insn_pipe (insn
);
8478 /* Force complex instructions to start new groups. */
8482 /* If this is a completely unrecognized insn, its an asm.
8483 We don't know how long it is, so record length as -1 to
8484 signal a needed realignment. */
8485 if (recog_memoized (insn
) < 0)
8488 len
= get_attr_length (insn
);
8492 if (in_use
& EV4_IB0
)
8494 if (in_use
& EV4_IB1
)
8499 in_use
|= EV4_IB0
| EV4_IBX
;
8503 if (in_use
& EV4_IB0
)
8505 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8513 if (in_use
& EV4_IB1
)
8523 /* Haifa doesn't do well scheduling branches. */
8524 if (GET_CODE (insn
) == JUMP_INSN
)
8528 insn
= next_nonnote_insn (insn
);
8530 if (!insn
|| ! INSN_P (insn
))
8533 /* Let Haifa tell us where it thinks insn group boundaries are. */
8534 if (GET_MODE (insn
) == TImode
)
8537 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8542 insn
= next_nonnote_insn (insn
);
8550 /* IN_USE is a mask of the slots currently filled within the insn group.
8551 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8552 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8554 LEN is, of course, the length of the group in bytes. */
8557 alphaev5_next_group (insn
, pin_use
, plen
)
8559 int *pin_use
, *plen
;
8566 || GET_CODE (PATTERN (insn
)) == CLOBBER
8567 || GET_CODE (PATTERN (insn
)) == USE
)
8572 enum alphaev5_pipe pipe
;
8574 pipe
= alphaev5_insn_pipe (insn
);
8578 /* Force complex instructions to start new groups. */
8582 /* If this is a completely unrecognized insn, its an asm.
8583 We don't know how long it is, so record length as -1 to
8584 signal a needed realignment. */
8585 if (recog_memoized (insn
) < 0)
8588 len
= get_attr_length (insn
);
8591 /* ??? Most of the places below, we would like to abort, as
8592 it would indicate an error either in Haifa, or in the
8593 scheduling description. Unfortunately, Haifa never
8594 schedules the last instruction of the BB, so we don't
8595 have an accurate TI bit to go off. */
8597 if (in_use
& EV5_E0
)
8599 if (in_use
& EV5_E1
)
8604 in_use
|= EV5_E0
| EV5_E01
;
8608 if (in_use
& EV5_E0
)
8610 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
8618 if (in_use
& EV5_E1
)
8624 if (in_use
& EV5_FA
)
8626 if (in_use
& EV5_FM
)
8631 in_use
|= EV5_FA
| EV5_FAM
;
8635 if (in_use
& EV5_FA
)
8641 if (in_use
& EV5_FM
)
8654 /* Haifa doesn't do well scheduling branches. */
8655 /* ??? If this is predicted not-taken, slotting continues, except
8656 that no more IBR, FBR, or JSR insns may be slotted. */
8657 if (GET_CODE (insn
) == JUMP_INSN
)
8661 insn
= next_nonnote_insn (insn
);
8663 if (!insn
|| ! INSN_P (insn
))
8666 /* Let Haifa tell us where it thinks insn group boundaries are. */
8667 if (GET_MODE (insn
) == TImode
)
8670 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8675 insn
= next_nonnote_insn (insn
);
8684 alphaev4_next_nop (pin_use
)
8687 int in_use
= *pin_use
;
8690 if (!(in_use
& EV4_IB0
))
8695 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
8700 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
8713 alphaev5_next_nop (pin_use
)
8716 int in_use
= *pin_use
;
8719 if (!(in_use
& EV5_E1
))
8724 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
8729 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
8741 /* The instruction group alignment main loop. */
8744 alpha_align_insns (insns
, max_align
, next_group
, next_nop
)
8746 unsigned int max_align
;
8747 rtx (*next_group
) PARAMS ((rtx
, int *, int *));
8748 rtx (*next_nop
) PARAMS ((int *));
8750 /* ALIGN is the known alignment for the insn group. */
8752 /* OFS is the offset of the current insn in the insn group. */
8754 int prev_in_use
, in_use
, len
;
8757 /* Let shorten branches care for assigning alignments to code labels. */
8758 shorten_branches (insns
);
8760 if (align_functions
< 4)
8762 else if ((unsigned int) align_functions
< max_align
)
8763 align
= align_functions
;
8767 ofs
= prev_in_use
= 0;
8769 if (GET_CODE (i
) == NOTE
)
8770 i
= next_nonnote_insn (i
);
8774 next
= (*next_group
) (i
, &in_use
, &len
);
8776 /* When we see a label, resync alignment etc. */
8777 if (GET_CODE (i
) == CODE_LABEL
)
8779 unsigned int new_align
= 1 << label_to_alignment (i
);
8781 if (new_align
>= align
)
8783 align
= new_align
< max_align
? new_align
: max_align
;
8787 else if (ofs
& (new_align
-1))
8788 ofs
= (ofs
| (new_align
-1)) + 1;
8793 /* Handle complex instructions special. */
8794 else if (in_use
== 0)
8796 /* Asms will have length < 0. This is a signal that we have
8797 lost alignment knowledge. Assume, however, that the asm
8798 will not mis-align instructions. */
8807 /* If the known alignment is smaller than the recognized insn group,
8808 realign the output. */
8809 else if ((int) align
< len
)
8811 unsigned int new_log_align
= len
> 8 ? 4 : 3;
8814 where
= prev
= prev_nonnote_insn (i
);
8815 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
8818 /* Can't realign between a call and its gp reload. */
8819 if (! (TARGET_EXPLICIT_RELOCS
8820 && prev
&& GET_CODE (prev
) == CALL_INSN
))
8822 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
8823 align
= 1 << new_log_align
;
8828 /* If the group won't fit in the same INT16 as the previous,
8829 we need to add padding to keep the group together. Rather
8830 than simply leaving the insn filling to the assembler, we
8831 can make use of the knowledge of what sorts of instructions
8832 were issued in the previous group to make sure that all of
8833 the added nops are really free. */
8834 else if (ofs
+ len
> (int) align
)
8836 int nop_count
= (align
- ofs
) / 4;
8839 /* Insert nops before labels, branches, and calls to truely merge
8840 the execution of the nops with the previous instruction group. */
8841 where
= prev_nonnote_insn (i
);
8844 if (GET_CODE (where
) == CODE_LABEL
)
8846 rtx where2
= prev_nonnote_insn (where
);
8847 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
8850 else if (GET_CODE (where
) == INSN
)
8857 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
8858 while (--nop_count
);
8862 ofs
= (ofs
+ len
) & (align
- 1);
8863 prev_in_use
= in_use
;
8868 /* Machine dependent reorg pass. */
8874 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
8875 alpha_handle_trap_shadows (insns
);
8877 /* Due to the number of extra trapb insns, don't bother fixing up
8878 alignment when trap precision is instruction. Moreover, we can
8879 only do our job when sched2 is run. */
8880 if (optimize
&& !optimize_size
8881 && alpha_tp
!= ALPHA_TP_INSN
8882 && flag_schedule_insns_after_reload
)
8884 if (alpha_cpu
== PROCESSOR_EV4
)
8885 alpha_align_insns (insns
, 8, alphaev4_next_group
, alphaev4_next_nop
);
8886 else if (alpha_cpu
== PROCESSOR_EV5
)
8887 alpha_align_insns (insns
, 16, alphaev5_next_group
, alphaev5_next_nop
);
8891 #ifdef OBJECT_FORMAT_ELF
8893 /* Switch to the section to which we should output X. The only thing
8894 special we do here is to honor small data. */
8897 alpha_elf_select_rtx_section (mode
, x
, align
)
8898 enum machine_mode mode
;
8900 unsigned HOST_WIDE_INT align
;
8902 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
8903 /* ??? Consider using mergable sdata sections. */
8906 default_elf_select_rtx_section (mode
, x
, align
);
8909 #endif /* OBJECT_FORMAT_ELF */
8911 #if TARGET_ABI_OPEN_VMS
8913 /* Return the VMS argument type corresponding to MODE. */
8916 alpha_arg_type (mode
)
8917 enum machine_mode mode
;
8922 return TARGET_FLOAT_VAX
? FF
: FS
;
8924 return TARGET_FLOAT_VAX
? FD
: FT
;
8930 /* Return an rtx for an integer representing the VMS Argument Information
8934 alpha_arg_info_reg_val (cum
)
8935 CUMULATIVE_ARGS cum
;
8937 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
8940 for (i
= 0; i
< 6; i
++)
8941 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
8943 return GEN_INT (regval
);
8946 /* Protect alpha_links from garbage collection. */
8949 mark_alpha_links_node (node
, data
)
8950 splay_tree_node node
;
8951 void *data ATTRIBUTE_UNUSED
;
8953 struct alpha_links
*links
= (struct alpha_links
*) node
->value
;
8954 ggc_mark_rtx (links
->linkage
);
8959 mark_alpha_links (ptr
)
8962 splay_tree tree
= *(splay_tree
*) ptr
;
8963 splay_tree_foreach (tree
, mark_alpha_links_node
, NULL
);
8966 /* Make (or fake) .linkage entry for function call.
8968 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
8970 Return an SYMBOL_REF rtx for the linkage. */
8973 alpha_need_linkage (name
, is_local
)
8977 splay_tree_node node
;
8978 struct alpha_links
*al
;
8979 struct alpha_funcs
*cfaf
;
8986 alpha_funcs_tree
= splay_tree_new
8987 ((splay_tree_compare_fn
) splay_tree_compare_pointers
,
8988 (splay_tree_delete_key_fn
) free
,
8989 (splay_tree_delete_key_fn
) free
);
8991 cfaf
= (struct alpha_funcs
*) xmalloc (sizeof (struct alpha_funcs
));
8994 cfaf
->num
= ++alpha_funcs_num
;
8996 splay_tree_insert (alpha_funcs_tree
,
8997 (splay_tree_key
) current_function_decl
,
8998 (splay_tree_value
) cfaf
);
9002 if (alpha_links_tree
)
9004 /* Is this name already defined? */
9006 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9009 al
= (struct alpha_links
*) node
->value
;
9012 /* Defined here but external assumed. */
9013 if (al
->lkind
== KIND_EXTERN
)
9014 al
->lkind
= KIND_LOCAL
;
9018 /* Used here but unused assumed. */
9019 if (al
->lkind
== KIND_UNUSED
)
9020 al
->lkind
= KIND_LOCAL
;
9027 alpha_links_tree
= splay_tree_new
9028 ((splay_tree_compare_fn
) strcmp
,
9029 (splay_tree_delete_key_fn
) free
,
9030 (splay_tree_delete_key_fn
) free
);
9032 ggc_add_root (&alpha_links_tree
, 1, 1, mark_alpha_links
);
9035 al
= (struct alpha_links
*) xmalloc (sizeof (struct alpha_links
));
9036 name
= xstrdup (name
);
9038 /* Assume external if no definition. */
9039 al
->lkind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9041 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9042 get_identifier (name
);
9044 /* Construct a SYMBOL_REF for us to call. */
9046 size_t name_len
= strlen (name
);
9047 char *linksym
= alloca (name_len
+ 6);
9049 memcpy (linksym
+ 1, name
, name_len
);
9050 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
9051 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
9052 ggc_alloc_string (linksym
, name_len
+ 5));
9055 splay_tree_insert (alpha_links_tree
, (splay_tree_key
) name
,
9056 (splay_tree_value
) al
);
9062 alpha_use_linkage (linkage
, cfundecl
, lflag
, rflag
)
9068 splay_tree_node cfunnode
;
9069 struct alpha_funcs
*cfaf
;
9070 struct alpha_links
*al
;
9071 const char *name
= XSTR (linkage
, 0);
9073 cfaf
= (struct alpha_funcs
*) 0;
9074 al
= (struct alpha_links
*) 0;
9076 cfunnode
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) cfundecl
);
9077 cfaf
= (struct alpha_funcs
*) cfunnode
->value
;
9081 splay_tree_node lnode
;
9083 /* Is this name already defined? */
9085 lnode
= splay_tree_lookup (cfaf
->links
, (splay_tree_key
) name
);
9087 al
= (struct alpha_links
*) lnode
->value
;
9091 cfaf
->links
= splay_tree_new
9092 ((splay_tree_compare_fn
) strcmp
,
9093 (splay_tree_delete_key_fn
) free
,
9094 (splay_tree_delete_key_fn
) free
);
9095 ggc_add_root (&cfaf
->links
, 1, 1, mark_alpha_links
);
9104 splay_tree_node node
= 0;
9105 struct alpha_links
*anl
;
9110 name_len
= strlen (name
);
9112 al
= (struct alpha_links
*) xmalloc (sizeof (struct alpha_links
));
9113 al
->num
= cfaf
->num
;
9115 node
= splay_tree_lookup (alpha_links_tree
, (splay_tree_key
) name
);
9118 anl
= (struct alpha_links
*) node
->value
;
9119 al
->lkind
= anl
->lkind
;
9122 sprintf (buf
, "$%d..%s..lk", cfaf
->num
, name
);
9123 buflen
= strlen (buf
);
9124 linksym
= alloca (buflen
+ 1);
9125 memcpy (linksym
, buf
, buflen
+ 1);
9127 al
->linkage
= gen_rtx_SYMBOL_REF
9128 (Pmode
, ggc_alloc_string (linksym
, buflen
+ 1));
9130 splay_tree_insert (cfaf
->links
, (splay_tree_key
) name
,
9131 (splay_tree_value
) al
);
9135 al
->rkind
= KIND_CODEADDR
;
9137 al
->rkind
= KIND_LINKAGE
;
9140 return gen_rtx_MEM (Pmode
, plus_constant (al
->linkage
, 8));
9146 alpha_write_one_linkage (node
, data
)
9147 splay_tree_node node
;
9150 const char *const name
= (const char *) node
->key
;
9151 struct alpha_links
*link
= (struct alpha_links
*) node
->value
;
9152 FILE *stream
= (FILE *) data
;
9154 fprintf (stream
, "$%d..%s..lk:\n", link
->num
, name
);
9155 if (link
->rkind
== KIND_CODEADDR
)
9157 if (link
->lkind
== KIND_LOCAL
)
9159 /* Local and used */
9160 fprintf (stream
, "\t.quad %s..en\n", name
);
9164 /* External and used, request code address. */
9165 fprintf (stream
, "\t.code_address %s\n", name
);
9170 if (link
->lkind
== KIND_LOCAL
)
9172 /* Local and used, build linkage pair. */
9173 fprintf (stream
, "\t.quad %s..en\n", name
);
9174 fprintf (stream
, "\t.quad %s\n", name
);
9178 /* External and used, request linkage pair. */
9179 fprintf (stream
, "\t.linkage %s\n", name
);
9187 alpha_write_linkage (stream
, funname
, fundecl
)
9189 const char *funname
;
9192 splay_tree_node node
;
9193 struct alpha_funcs
*func
;
9196 fprintf (stream
, "\t.align 3\n");
9197 node
= splay_tree_lookup (alpha_funcs_tree
, (splay_tree_key
) fundecl
);
9198 func
= (struct alpha_funcs
*) node
->value
;
9200 fputs ("\t.name ", stream
);
9201 assemble_name (stream
, funname
);
9202 fputs ("..na\n", stream
);
9203 ASM_OUTPUT_LABEL (stream
, funname
);
9204 fprintf (stream
, "\t.pdesc ");
9205 assemble_name (stream
, funname
);
9206 fprintf (stream
, "..en,%s\n",
9207 alpha_procedure_type
== PT_STACK
? "stack"
9208 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
9212 splay_tree_foreach (func
->links
, alpha_write_one_linkage
, stream
);
9213 /* splay_tree_delete (func->links); */
9217 /* Given a decl, a section name, and whether the decl initializer
9218 has relocs, choose attributes for the section. */
9220 #define SECTION_VMS_OVERLAY SECTION_FORGET
9221 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9222 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9225 vms_section_type_flags (decl
, name
, reloc
)
9230 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9232 if (decl
&& DECL_ATTRIBUTES (decl
)
9233 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
9234 flags
|= SECTION_VMS_OVERLAY
;
9235 if (decl
&& DECL_ATTRIBUTES (decl
)
9236 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
9237 flags
|= SECTION_VMS_GLOBAL
;
9238 if (decl
&& DECL_ATTRIBUTES (decl
)
9239 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
9240 flags
|= SECTION_VMS_INITIALIZE
;
9245 /* Switch to an arbitrary section NAME with attributes as specified
9246 by FLAGS. ALIGN specifies any known alignment requirements for
9247 the section; 0 if the default should be used. */
9250 vms_asm_named_section (name
, flags
)
9254 fputc ('\n', asm_out_file
);
9255 fprintf (asm_out_file
, ".section\t%s", name
);
9257 if (flags
& SECTION_VMS_OVERLAY
)
9258 fprintf (asm_out_file
, ",OVR");
9259 if (flags
& SECTION_VMS_GLOBAL
)
9260 fprintf (asm_out_file
, ",GBL");
9261 if (flags
& SECTION_VMS_INITIALIZE
)
9262 fprintf (asm_out_file
, ",NOMOD");
9263 if (flags
& SECTION_DEBUG
)
9264 fprintf (asm_out_file
, ",NOWRT");
9266 fputc ('\n', asm_out_file
);
9269 /* Record an element in the table of global constructors. SYMBOL is
9270 a SYMBOL_REF of the function to be called; PRIORITY is a number
9271 between 0 and MAX_INIT_PRIORITY.
9273 Differs from default_ctors_section_asm_out_constructor in that the
9274 width of the .ctors entry is always 64 bits, rather than the 32 bits
9275 used by a normal pointer. */
9278 vms_asm_out_constructor (symbol
, priority
)
9280 int priority ATTRIBUTE_UNUSED
;
9283 assemble_align (BITS_PER_WORD
);
9284 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9288 vms_asm_out_destructor (symbol
, priority
)
9290 int priority ATTRIBUTE_UNUSED
;
9293 assemble_align (BITS_PER_WORD
);
9294 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9299 alpha_need_linkage (name
, is_local
)
9300 const char *name ATTRIBUTE_UNUSED
;
9301 int is_local ATTRIBUTE_UNUSED
;
9307 alpha_use_linkage (linkage
, cfundecl
, lflag
, rflag
)
9308 rtx linkage ATTRIBUTE_UNUSED
;
9309 tree cfundecl ATTRIBUTE_UNUSED
;
9310 int lflag ATTRIBUTE_UNUSED
;
9311 int rflag ATTRIBUTE_UNUSED
;
9316 #endif /* TARGET_ABI_OPEN_VMS */
9318 #if TARGET_ABI_UNICOSMK
9320 static void unicosmk_output_module_name
PARAMS ((FILE *));
9321 static void unicosmk_output_default_externs
PARAMS ((FILE *));
9322 static void unicosmk_output_dex
PARAMS ((FILE *));
9323 static void unicosmk_output_externs
PARAMS ((FILE *));
9324 static void unicosmk_output_addr_vec
PARAMS ((FILE *, rtx
));
9325 static const char *unicosmk_ssib_name
PARAMS ((void));
9326 static int unicosmk_special_name
PARAMS ((const char *));
9328 /* Define the offset between two registers, one to be eliminated, and the
9329 other its replacement, at the start of a routine. */
9332 unicosmk_initial_elimination_offset (from
, to
)
9338 fixed_size
= alpha_sa_size();
9339 if (fixed_size
!= 0)
9342 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9344 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9346 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9347 return (ALPHA_ROUND (current_function_outgoing_args_size
)
9348 + ALPHA_ROUND (get_frame_size()));
9349 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9350 return (ALPHA_ROUND (fixed_size
)
9351 + ALPHA_ROUND (get_frame_size()
9352 + current_function_outgoing_args_size
));
9357 /* Output the module name for .ident and .end directives. We have to strip
9358 directories and add make sure that the module name starts with a letter
9362 unicosmk_output_module_name (file
)
9367 /* Strip directories. */
9369 name
= strrchr (main_input_filename
, '/');
9373 name
= main_input_filename
;
9375 /* CAM only accepts module names that start with a letter or '$'. We
9376 prefix the module name with a '$' if necessary. */
9378 if (!ISALPHA (*name
))
9380 output_clean_symbol_name (file
, name
);
9383 /* Output text that to appear at the beginning of an assembler file. */
9386 unicosmk_asm_file_start (file
)
9391 fputs ("\t.ident\t", file
);
9392 unicosmk_output_module_name (file
);
9393 fputs ("\n\n", file
);
9395 /* The Unicos/Mk assembler uses different register names. Instead of trying
9396 to support them, we simply use micro definitions. */
9398 /* CAM has different register names: rN for the integer register N and fN
9399 for the floating-point register N. Instead of trying to use these in
9400 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9403 for (i
= 0; i
< 32; ++i
)
9404 fprintf (file
, "$%d <- r%d\n", i
, i
);
9406 for (i
= 0; i
< 32; ++i
)
9407 fprintf (file
, "$f%d <- f%d\n", i
, i
);
9411 /* The .align directive fill unused space with zeroes which does not work
9412 in code sections. We define the macro 'gcc@code@align' which uses nops
9413 instead. Note that it assumes that code sections always have the
9414 biggest possible alignment since . refers to the current offset from
9415 the beginning of the section. */
9417 fputs ("\t.macro gcc@code@align n\n", file
);
9418 fputs ("gcc@n@bytes = 1 << n\n", file
);
9419 fputs ("gcc@here = . % gcc@n@bytes\n", file
);
9420 fputs ("\t.if ne, gcc@here, 0\n", file
);
9421 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", file
);
9422 fputs ("\tbis r31,r31,r31\n", file
);
9423 fputs ("\t.endr\n", file
);
9424 fputs ("\t.endif\n", file
);
9425 fputs ("\t.endm gcc@code@align\n\n", file
);
9427 /* Output extern declarations which should always be visible. */
9428 unicosmk_output_default_externs (file
);
9430 /* Open a dummy section. We always need to be inside a section for the
9431 section-switching code to work correctly.
9432 ??? This should be a module id or something like that. I still have to
9433 figure out what the rules for those are. */
9434 fputs ("\n\t.psect\t$SG00000,data\n", file
);
9437 /* Output text to appear at the end of an assembler file. This includes all
9438 pending extern declarations and DEX expressions. */
9441 unicosmk_asm_file_end (file
)
9444 fputs ("\t.endp\n\n", file
);
9446 /* Output all pending externs. */
9448 unicosmk_output_externs (file
);
9450 /* Output dex definitions used for functions whose names conflict with
9453 unicosmk_output_dex (file
);
9455 fputs ("\t.end\t", file
);
9456 unicosmk_output_module_name (file
);
9460 /* Output the definition of a common variable. */
9463 unicosmk_output_common (file
, name
, size
, align
)
9470 printf ("T3E__: common %s\n", name
);
9473 fputs("\t.endp\n\n\t.psect ", file
);
9474 assemble_name(file
, name
);
9475 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
9476 fprintf(file
, "\t.byte\t0:%d\n", size
);
9478 /* Mark the symbol as defined in this module. */
9479 name_tree
= get_identifier (name
);
9480 TREE_ASM_WRITTEN (name_tree
) = 1;
9483 #define SECTION_PUBLIC SECTION_MACH_DEP
9484 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9485 static int current_section_align
;
9488 unicosmk_section_type_flags (decl
, name
, reloc
)
9491 int reloc ATTRIBUTE_UNUSED
;
9493 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9498 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9500 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9501 if (align_functions_log
> current_section_align
)
9502 current_section_align
= align_functions_log
;
9504 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
9505 flags
|= SECTION_MAIN
;
9508 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
9510 if (TREE_PUBLIC (decl
))
9511 flags
|= SECTION_PUBLIC
;
9516 /* Generate a section name for decl and associate it with the
9520 unicosmk_unique_section (decl
, reloc
)
9522 int reloc ATTRIBUTE_UNUSED
;
9530 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9531 name
= alpha_strip_name_encoding (name
);
9532 len
= strlen (name
);
9534 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9538 /* It is essential that we prefix the section name here because
9539 otherwise the section names generated for constructors and
9540 destructors confuse collect2. */
9542 string
= alloca (len
+ 6);
9543 sprintf (string
, "code@%s", name
);
9544 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9546 else if (TREE_PUBLIC (decl
))
9547 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
9552 string
= alloca (len
+ 6);
9553 sprintf (string
, "data@%s", name
);
9554 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9558 /* Switch to an arbitrary section NAME with attributes as specified
9559 by FLAGS. ALIGN specifies any known alignment requirements for
9560 the section; 0 if the default should be used. */
9563 unicosmk_asm_named_section (name
, flags
)
9569 /* Close the previous section. */
9571 fputs ("\t.endp\n\n", asm_out_file
);
9573 /* Find out what kind of section we are opening. */
9575 if (flags
& SECTION_MAIN
)
9576 fputs ("\t.start\tmain\n", asm_out_file
);
9578 if (flags
& SECTION_CODE
)
9580 else if (flags
& SECTION_PUBLIC
)
9585 if (current_section_align
!= 0)
9586 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
9587 current_section_align
, kind
);
9589 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
9593 unicosmk_insert_attributes (decl
, attr_ptr
)
9595 tree
*attr_ptr ATTRIBUTE_UNUSED
;
9598 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
9599 unicosmk_unique_section (decl
, 0);
9602 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9603 in code sections because .align fill unused space with zeroes. */
9606 unicosmk_output_align (file
, align
)
9610 if (inside_function
)
9611 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
9613 fprintf (file
, "\t.align\t%d\n", align
);
9616 /* Add a case vector to the current function's list of deferred case
9617 vectors. Case vectors have to be put into a separate section because CAM
9618 does not allow data definitions in code sections. */
9621 unicosmk_defer_case_vector (lab
, vec
)
9625 struct machine_function
*machine
= cfun
->machine
;
9627 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9628 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
9629 machine
->addr_list
);
9632 /* Output a case vector. */
9635 unicosmk_output_addr_vec (file
, vec
)
9639 rtx lab
= XEXP (vec
, 0);
9640 rtx body
= XEXP (vec
, 1);
9641 int vlen
= XVECLEN (body
, 0);
9644 ASM_OUTPUT_INTERNAL_LABEL (file
, "L", CODE_LABEL_NUMBER (lab
));
9646 for (idx
= 0; idx
< vlen
; idx
++)
9648 ASM_OUTPUT_ADDR_VEC_ELT
9649 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9653 /* Output current function's deferred case vectors. */
9656 unicosmk_output_deferred_case_vectors (file
)
9659 struct machine_function
*machine
= cfun
->machine
;
9662 if (machine
->addr_list
== NULL_RTX
)
9666 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
9667 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
9670 /* Set up the dynamic subprogram information block (DSIB) and update the
9671 frame pointer register ($15) for subroutines which have a frame. If the
9672 subroutine doesn't have a frame, simply increment $15. */
9675 unicosmk_gen_dsib (imaskP
)
9676 unsigned long * imaskP
;
9678 if (alpha_procedure_type
== PT_STACK
)
9680 const char *ssib_name
;
9683 /* Allocate 64 bytes for the DSIB. */
9685 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9687 emit_insn (gen_blockage ());
9689 /* Save the return address. */
9691 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
9692 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9693 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
9694 (*imaskP
) &= ~(1L << REG_RA
);
9696 /* Save the old frame pointer. */
9698 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
9699 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9700 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
9701 (*imaskP
) &= ~(1L << HARD_FRAME_POINTER_REGNUM
);
9703 emit_insn (gen_blockage ());
9705 /* Store the SSIB pointer. */
9707 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
9708 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
9709 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9711 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
9712 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
9713 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
9715 /* Save the CIW index. */
9717 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
9718 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9719 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
9721 emit_insn (gen_blockage ());
9723 /* Set the new frame pointer. */
9725 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9726 stack_pointer_rtx
, GEN_INT (64))));
9731 /* Increment the frame pointer register to indicate that we do not
9734 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9735 hard_frame_pointer_rtx
, GEN_INT (1))));
9739 #define SSIB_PREFIX "__SSIB_"
9740 #define SSIB_PREFIX_LEN 7
9742 /* Generate the name of the SSIB section for the current function. */
9745 unicosmk_ssib_name ()
9747 /* This is ok since CAM won't be able to deal with names longer than that
9750 static char name
[256];
9756 x
= DECL_RTL (cfun
->decl
);
9757 if (GET_CODE (x
) != MEM
)
9760 if (GET_CODE (x
) != SYMBOL_REF
)
9762 fnname
= alpha_strip_name_encoding (XSTR (x
, 0));
9764 len
= strlen (fnname
);
9765 if (len
+ SSIB_PREFIX_LEN
> 255)
9766 len
= 255 - SSIB_PREFIX_LEN
;
9768 strcpy (name
, SSIB_PREFIX
);
9769 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
9770 name
[len
+ SSIB_PREFIX_LEN
] = 0;
9775 /* Output the static subroutine information block for the current
9779 unicosmk_output_ssib (file
, fnname
)
9787 struct machine_function
*machine
= cfun
->machine
;
9790 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
9791 unicosmk_ssib_name ());
9793 /* Some required stuff and the function name length. */
9795 len
= strlen (fnname
);
9796 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
9799 ??? We don't do that yet. */
9801 fputs ("\t.quad\t0\n", file
);
9803 /* Function address. */
9805 fputs ("\t.quad\t", file
);
9806 assemble_name (file
, fnname
);
9809 fputs ("\t.quad\t0\n", file
);
9810 fputs ("\t.quad\t0\n", file
);
9813 ??? We do it the same way Cray CC does it but this could be
9816 for( i
= 0; i
< len
; i
++ )
9817 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
9818 if( (len
% 8) == 0 )
9819 fputs ("\t.quad\t0\n", file
);
9821 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
9823 /* All call information words used in the function. */
9825 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
9828 fprintf (file
, "\t.quad\t");
9829 #if HOST_BITS_PER_WIDE_INT == 32
9830 fprintf (file
, HOST_WIDE_INT_PRINT_DOUBLE_HEX
,
9831 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
9833 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (ciw
));
9835 fprintf (file
, "\n");
9839 /* Add a call information word (CIW) to the list of the current function's
9840 CIWs and return its index.
9842 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9845 unicosmk_add_call_info_word (x
)
9849 struct machine_function
*machine
= cfun
->machine
;
9851 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
9852 if (machine
->first_ciw
== NULL_RTX
)
9853 machine
->first_ciw
= node
;
9855 XEXP (machine
->last_ciw
, 1) = node
;
9857 machine
->last_ciw
= node
;
9858 ++machine
->ciw_count
;
9860 return GEN_INT (machine
->ciw_count
9861 + strlen (current_function_name
)/8 + 5);
9864 static char unicosmk_section_buf
[100];
9867 unicosmk_text_section ()
9869 static int count
= 0;
9870 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9872 return unicosmk_section_buf
;
9876 unicosmk_data_section ()
9878 static int count
= 1;
9879 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9881 return unicosmk_section_buf
;
9884 /* The Cray assembler doesn't accept extern declarations for symbols which
9885 are defined in the same file. We have to keep track of all global
9886 symbols which are referenced and/or defined in a source file and output
9887 extern declarations for those which are referenced but not defined at
9890 /* List of identifiers for which an extern declaration might have to be
9893 struct unicosmk_extern_list
9895 struct unicosmk_extern_list
*next
;
9899 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
9901 /* Output extern declarations which are required for every asm file. */
9904 unicosmk_output_default_externs (file
)
9907 static const char *const externs
[] =
9908 { "__T3E_MISMATCH" };
9913 n
= ARRAY_SIZE (externs
);
9915 for (i
= 0; i
< n
; i
++)
9916 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
9919 /* Output extern declarations for global symbols which are have been
9920 referenced but not defined. */
9923 unicosmk_output_externs (file
)
9926 struct unicosmk_extern_list
*p
;
9927 const char *real_name
;
9931 len
= strlen (user_label_prefix
);
9932 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
9934 /* We have to strip the encoding and possibly remove user_label_prefix
9935 from the identifier in order to handle -fleading-underscore and
9936 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9937 real_name
= alpha_strip_name_encoding (p
->name
);
9938 if (len
&& p
->name
[0] == '*'
9939 && !memcmp (real_name
, user_label_prefix
, len
))
9942 name_tree
= get_identifier (real_name
);
9943 if (! TREE_ASM_WRITTEN (name_tree
))
9945 TREE_ASM_WRITTEN (name_tree
) = 1;
9946 fputs ("\t.extern\t", file
);
9947 assemble_name (file
, p
->name
);
9953 /* Record an extern. */
9956 unicosmk_add_extern (name
)
9959 struct unicosmk_extern_list
*p
;
9961 p
= (struct unicosmk_extern_list
*)
9962 xmalloc (sizeof (struct unicosmk_extern_list
));
9963 p
->next
= unicosmk_extern_head
;
9965 unicosmk_extern_head
= p
;
9968 /* The Cray assembler generates incorrect code if identifiers which
9969 conflict with register names are used as instruction operands. We have
9970 to replace such identifiers with DEX expressions. */
9972 /* Structure to collect identifiers which have been replaced by DEX
9975 struct unicosmk_dex
{
9976 struct unicosmk_dex
*next
;
9980 /* List of identifiers which have been replaced by DEX expressions. The DEX
9981 number is determined by the position in the list. */
9983 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
9985 /* The number of elements in the DEX list. */
9987 static int unicosmk_dex_count
= 0;
9989 /* Check if NAME must be replaced by a DEX expression. */
9992 unicosmk_special_name (name
)
10001 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
10006 case '1': case '2':
10007 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
10010 return (name
[2] == '\0'
10011 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
10014 return (ISDIGIT (name
[1]) && name
[2] == '\0');
10018 /* Return the DEX number if X must be replaced by a DEX expression and 0
10022 unicosmk_need_dex (x
)
10025 struct unicosmk_dex
*dex
;
10029 if (GET_CODE (x
) != SYMBOL_REF
)
10033 if (! unicosmk_special_name (name
))
10036 i
= unicosmk_dex_count
;
10037 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10039 if (! strcmp (name
, dex
->name
))
10044 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
10046 dex
->next
= unicosmk_dex_list
;
10047 unicosmk_dex_list
= dex
;
10049 ++unicosmk_dex_count
;
10050 return unicosmk_dex_count
;
10053 /* Output the DEX definitions for this file. */
10056 unicosmk_output_dex (file
)
10059 struct unicosmk_dex
*dex
;
10062 if (unicosmk_dex_list
== NULL
)
10065 fprintf (file
, "\t.dexstart\n");
10067 i
= unicosmk_dex_count
;
10068 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
10070 fprintf (file
, "\tDEX (%d) = ", i
);
10071 assemble_name (file
, dex
->name
);
10076 fprintf (file
, "\t.dexend\n");
10082 unicosmk_output_deferred_case_vectors (file
)
10083 FILE *file ATTRIBUTE_UNUSED
;
10087 unicosmk_gen_dsib (imaskP
)
10088 unsigned long * imaskP ATTRIBUTE_UNUSED
;
10092 unicosmk_output_ssib (file
, fnname
)
10093 FILE * file ATTRIBUTE_UNUSED
;
10094 const char * fnname ATTRIBUTE_UNUSED
;
10098 unicosmk_add_call_info_word (x
)
10099 rtx x ATTRIBUTE_UNUSED
;
10105 unicosmk_need_dex (x
)
10106 rtx x ATTRIBUTE_UNUSED
;
10111 #endif /* TARGET_ABI_UNICOSMK */
10113 #include "gt-alpha.h"