1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
45 #include "integrate.h"
48 #include "target-def.h"
50 #include "langhooks.h"
52 /* Specify which cpu to schedule for. */
54 enum processor_type alpha_cpu
;
55 static const char * const alpha_cpu_name
[] =
60 /* Specify how accurate floating-point traps need to be. */
62 enum alpha_trap_precision alpha_tp
;
64 /* Specify the floating-point rounding mode. */
66 enum alpha_fp_rounding_mode alpha_fprm
;
68 /* Specify which things cause traps. */
70 enum alpha_fp_trap_mode alpha_fptm
;
72 /* Specify bit size of immediate TLS offsets. */
74 int alpha_tls_size
= 32;
76 /* Strings decoded into the above options. */
78 const char *alpha_cpu_string
; /* -mcpu= */
79 const char *alpha_tune_string
; /* -mtune= */
80 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
81 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
82 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
83 const char *alpha_mlat_string
; /* -mmemory-latency= */
84 const char *alpha_tls_size_string
; /* -mtls-size=[16|32|64] */
86 /* Save information from a "cmpxx" operation until the branch or scc is
89 struct alpha_compare alpha_compare
;
91 /* Non-zero if inside of a function, because the Alpha asm can't
92 handle .files inside of functions. */
94 static int inside_function
= FALSE
;
96 /* The number of cycles of latency we should assume on memory reads. */
98 int alpha_memory_latency
= 3;
100 /* Whether the function needs the GP. */
102 static int alpha_function_needs_gp
;
104 /* The alias set for prologue/epilogue register save/restore. */
106 static int alpha_sr_alias_set
;
108 /* The assembler name of the current function. */
110 static const char *alpha_fnname
;
112 /* The next explicit relocation sequence number. */
113 int alpha_next_sequence_number
= 1;
115 /* The literal and gpdisp sequence numbers for this insn, as printed
116 by %# and %* respectively. */
117 int alpha_this_literal_sequence_number
;
118 int alpha_this_gpdisp_sequence_number
;
120 /* Declarations of static functions. */
121 static int tls_symbolic_operand_1
122 PARAMS ((rtx
, enum machine_mode
, int, int));
123 static enum tls_model tls_symbolic_operand_type
125 static bool decl_in_text_section
127 static bool alpha_in_small_data_p
129 static void alpha_encode_section_info
130 PARAMS ((tree
, int));
131 static const char *alpha_strip_name_encoding
132 PARAMS ((const char *));
133 static int some_small_symbolic_operand_1
134 PARAMS ((rtx
*, void *));
135 static int split_small_symbolic_operand_1
136 PARAMS ((rtx
*, void *));
137 static void alpha_set_memflags_1
138 PARAMS ((rtx
, int, int, int));
139 static rtx alpha_emit_set_const_1
140 PARAMS ((rtx
, enum machine_mode
, HOST_WIDE_INT
, int));
141 static void alpha_expand_unaligned_load_words
142 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
143 static void alpha_expand_unaligned_store_words
144 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
145 static void alpha_init_builtins
147 static rtx alpha_expand_builtin
148 PARAMS ((tree
, rtx
, rtx
, enum machine_mode
, int));
149 static void alpha_sa_mask
150 PARAMS ((unsigned long *imaskP
, unsigned long *fmaskP
));
151 static int find_lo_sum
152 PARAMS ((rtx
*, void *));
153 static int alpha_does_function_need_gp
155 static int alpha_ra_ever_killed
157 static const char *get_trap_mode_suffix
159 static const char *get_round_mode_suffix
161 static const char *get_some_local_dynamic_name
163 static int get_some_local_dynamic_name_1
164 PARAMS ((rtx
*, void *));
165 static rtx set_frame_related_p
167 static const char *alpha_lookup_xfloating_lib_func
168 PARAMS ((enum rtx_code
));
169 static int alpha_compute_xfloating_mode_arg
170 PARAMS ((enum rtx_code
, enum alpha_fp_rounding_mode
));
171 static void alpha_emit_xfloating_libcall
172 PARAMS ((const char *, rtx
, rtx
[], int, rtx
));
173 static rtx alpha_emit_xfloating_compare
174 PARAMS ((enum rtx_code
, rtx
, rtx
));
175 static void alpha_output_function_end_prologue
177 static int alpha_adjust_cost
178 PARAMS ((rtx
, rtx
, rtx
, int));
179 static int alpha_issue_rate
181 static int alpha_use_dfa_pipeline_interface
183 static int alpha_multipass_dfa_lookahead
186 #ifdef OBJECT_FORMAT_ELF
187 static void alpha_elf_select_rtx_section
188 PARAMS ((enum machine_mode
, rtx
, unsigned HOST_WIDE_INT
));
191 static struct machine_function
* alpha_init_machine_status
194 static void unicosmk_output_deferred_case_vectors
PARAMS ((FILE *));
195 static void unicosmk_gen_dsib
PARAMS ((unsigned long *imaskP
));
196 static void unicosmk_output_ssib
PARAMS ((FILE *, const char *));
197 static int unicosmk_need_dex
PARAMS ((rtx
));
199 /* Get the number of args of a function in one of two ways. */
200 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
201 #define NUM_ARGS current_function_args_info.num_args
203 #define NUM_ARGS current_function_args_info
209 /* Initialize the GCC target structure. */
210 #if TARGET_ABI_OPEN_VMS
211 const struct attribute_spec vms_attribute_table
[];
212 static unsigned int vms_section_type_flags
PARAMS ((tree
, const char *, int));
213 static void vms_asm_named_section
PARAMS ((const char *, unsigned int));
214 static void vms_asm_out_constructor
PARAMS ((rtx
, int));
215 static void vms_asm_out_destructor
PARAMS ((rtx
, int));
216 # undef TARGET_ATTRIBUTE_TABLE
217 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
218 # undef TARGET_SECTION_TYPE_FLAGS
219 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
222 #undef TARGET_IN_SMALL_DATA_P
223 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
224 #undef TARGET_ENCODE_SECTION_INFO
225 #define TARGET_ENCODE_SECTION_INFO alpha_encode_section_info
226 #undef TARGET_STRIP_NAME_ENCODING
227 #define TARGET_STRIP_NAME_ENCODING alpha_strip_name_encoding
229 #if TARGET_ABI_UNICOSMK
230 static void unicosmk_asm_named_section
PARAMS ((const char *, unsigned int));
231 static void unicosmk_insert_attributes
PARAMS ((tree
, tree
*));
232 static unsigned int unicosmk_section_type_flags
PARAMS ((tree
, const char *,
234 static void unicosmk_unique_section
PARAMS ((tree
, int));
235 # undef TARGET_INSERT_ATTRIBUTES
236 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
237 # undef TARGET_SECTION_TYPE_FLAGS
238 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
239 # undef TARGET_ASM_UNIQUE_SECTION
240 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
243 #undef TARGET_ASM_ALIGNED_HI_OP
244 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
245 #undef TARGET_ASM_ALIGNED_DI_OP
246 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
248 /* Default unaligned ops are provided for ELF systems. To get unaligned
249 data for non-ELF systems, we have to turn off auto alignment. */
250 #ifndef OBJECT_FORMAT_ELF
251 #undef TARGET_ASM_UNALIGNED_HI_OP
252 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
253 #undef TARGET_ASM_UNALIGNED_SI_OP
254 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
255 #undef TARGET_ASM_UNALIGNED_DI_OP
256 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
259 #ifdef OBJECT_FORMAT_ELF
260 #undef TARGET_ASM_SELECT_RTX_SECTION
261 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
264 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
265 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
267 #undef TARGET_SCHED_ADJUST_COST
268 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
269 #undef TARGET_SCHED_ISSUE_RATE
270 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
271 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
272 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
273 alpha_use_dfa_pipeline_interface
274 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
275 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
276 alpha_multipass_dfa_lookahead
278 #undef TARGET_HAVE_TLS
279 #define TARGET_HAVE_TLS HAVE_AS_TLS
281 #undef TARGET_INIT_BUILTINS
282 #define TARGET_INIT_BUILTINS alpha_init_builtins
283 #undef TARGET_EXPAND_BUILTIN
284 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
286 struct gcc_target targetm
= TARGET_INITIALIZER
;
288 /* Parse target option strings. */
294 static const struct cpu_table
{
295 const char *const name
;
296 const enum processor_type processor
;
299 #define EV5_MASK (MASK_CPU_EV5)
300 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
301 { "ev4", PROCESSOR_EV4
, 0 },
302 { "ev45", PROCESSOR_EV4
, 0 },
303 { "21064", PROCESSOR_EV4
, 0 },
304 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
305 { "21164", PROCESSOR_EV5
, EV5_MASK
},
306 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
307 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
308 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
309 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
310 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
311 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
312 { "21264", PROCESSOR_EV6
, EV6_MASK
},
313 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
314 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
318 /* Unicos/Mk doesn't have shared libraries. */
319 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
321 warning ("-f%s ignored for Unicos/Mk (not supported)",
322 (flag_pic
> 1) ? "PIC" : "pic");
326 /* On Unicos/Mk, the native compiler consistenly generates /d suffices for
327 floating-point instructions. Make that the default for this target. */
328 if (TARGET_ABI_UNICOSMK
)
329 alpha_fprm
= ALPHA_FPRM_DYN
;
331 alpha_fprm
= ALPHA_FPRM_NORM
;
333 alpha_tp
= ALPHA_TP_PROG
;
334 alpha_fptm
= ALPHA_FPTM_N
;
336 /* We cannot use su and sui qualifiers for conversion instructions on
337 Unicos/Mk. I'm not sure if this is due to assembler or hardware
338 limitations. Right now, we issue a warning if -mieee is specified
339 and then ignore it; eventually, we should either get it right or
340 disable the option altogether. */
344 if (TARGET_ABI_UNICOSMK
)
345 warning ("-mieee not supported on Unicos/Mk");
348 alpha_tp
= ALPHA_TP_INSN
;
349 alpha_fptm
= ALPHA_FPTM_SU
;
353 if (TARGET_IEEE_WITH_INEXACT
)
355 if (TARGET_ABI_UNICOSMK
)
356 warning ("-mieee-with-inexact not supported on Unicos/Mk");
359 alpha_tp
= ALPHA_TP_INSN
;
360 alpha_fptm
= ALPHA_FPTM_SUI
;
366 if (! strcmp (alpha_tp_string
, "p"))
367 alpha_tp
= ALPHA_TP_PROG
;
368 else if (! strcmp (alpha_tp_string
, "f"))
369 alpha_tp
= ALPHA_TP_FUNC
;
370 else if (! strcmp (alpha_tp_string
, "i"))
371 alpha_tp
= ALPHA_TP_INSN
;
373 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string
);
376 if (alpha_fprm_string
)
378 if (! strcmp (alpha_fprm_string
, "n"))
379 alpha_fprm
= ALPHA_FPRM_NORM
;
380 else if (! strcmp (alpha_fprm_string
, "m"))
381 alpha_fprm
= ALPHA_FPRM_MINF
;
382 else if (! strcmp (alpha_fprm_string
, "c"))
383 alpha_fprm
= ALPHA_FPRM_CHOP
;
384 else if (! strcmp (alpha_fprm_string
,"d"))
385 alpha_fprm
= ALPHA_FPRM_DYN
;
387 error ("bad value `%s' for -mfp-rounding-mode switch",
391 if (alpha_fptm_string
)
393 if (strcmp (alpha_fptm_string
, "n") == 0)
394 alpha_fptm
= ALPHA_FPTM_N
;
395 else if (strcmp (alpha_fptm_string
, "u") == 0)
396 alpha_fptm
= ALPHA_FPTM_U
;
397 else if (strcmp (alpha_fptm_string
, "su") == 0)
398 alpha_fptm
= ALPHA_FPTM_SU
;
399 else if (strcmp (alpha_fptm_string
, "sui") == 0)
400 alpha_fptm
= ALPHA_FPTM_SUI
;
402 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string
);
405 if (alpha_tls_size_string
)
407 if (strcmp (alpha_tls_size_string
, "16") == 0)
409 else if (strcmp (alpha_tls_size_string
, "32") == 0)
411 else if (strcmp (alpha_tls_size_string
, "64") == 0)
414 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string
);
418 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
419 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
421 if (alpha_cpu_string
)
423 for (i
= 0; cpu_table
[i
].name
; i
++)
424 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
426 alpha_cpu
= cpu_table
[i
].processor
;
427 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
428 | MASK_CPU_EV5
| MASK_CPU_EV6
);
429 target_flags
|= cpu_table
[i
].flags
;
432 if (! cpu_table
[i
].name
)
433 error ("bad value `%s' for -mcpu switch", alpha_cpu_string
);
436 if (alpha_tune_string
)
438 for (i
= 0; cpu_table
[i
].name
; i
++)
439 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
441 alpha_cpu
= cpu_table
[i
].processor
;
444 if (! cpu_table
[i
].name
)
445 error ("bad value `%s' for -mcpu switch", alpha_tune_string
);
448 /* Do some sanity checks on the above options. */
450 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
452 warning ("trap mode not supported on Unicos/Mk");
453 alpha_fptm
= ALPHA_FPTM_N
;
456 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
457 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
459 warning ("fp software completion requires -mtrap-precision=i");
460 alpha_tp
= ALPHA_TP_INSN
;
465 /* Except for EV6 pass 1 (not released), we always have precise
466 arithmetic traps. Which means we can do software completion
467 without minding trap shadows. */
468 alpha_tp
= ALPHA_TP_PROG
;
471 if (TARGET_FLOAT_VAX
)
473 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
475 warning ("rounding mode not supported for VAX floats");
476 alpha_fprm
= ALPHA_FPRM_NORM
;
478 if (alpha_fptm
== ALPHA_FPTM_SUI
)
480 warning ("trap mode not supported for VAX floats");
481 alpha_fptm
= ALPHA_FPTM_SU
;
489 if (!alpha_mlat_string
)
490 alpha_mlat_string
= "L1";
492 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
493 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
495 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
496 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
497 && alpha_mlat_string
[2] == '\0')
499 static int const cache_latency
[][4] =
501 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
502 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
503 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
506 lat
= alpha_mlat_string
[1] - '0';
507 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
509 warning ("L%d cache latency unknown for %s",
510 lat
, alpha_cpu_name
[alpha_cpu
]);
514 lat
= cache_latency
[alpha_cpu
][lat
-1];
516 else if (! strcmp (alpha_mlat_string
, "main"))
518 /* Most current memories have about 370ns latency. This is
519 a reasonable guess for a fast cpu. */
524 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string
);
528 alpha_memory_latency
= lat
;
531 /* Default the definition of "small data" to 8 bytes. */
535 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
537 target_flags
|= MASK_SMALL_DATA
;
538 else if (flag_pic
== 2)
539 target_flags
&= ~MASK_SMALL_DATA
;
541 /* Align labels and loops for optimal branching. */
542 /* ??? Kludge these by not doing anything if we don't optimize and also if
543 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
544 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
546 if (align_loops
<= 0)
548 if (align_jumps
<= 0)
551 if (align_functions
<= 0)
552 align_functions
= 16;
554 /* Acquire a unique set number for our register saves and restores. */
555 alpha_sr_alias_set
= new_alias_set ();
557 /* Register variables and functions with the garbage collector. */
559 /* Set up function hooks. */
560 init_machine_status
= alpha_init_machine_status
;
563 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
571 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
573 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
579 /* Returns 1 if OP is either the constant zero or a register. If a
580 register, it must be in the proper mode unless MODE is VOIDmode. */
583 reg_or_0_operand (op
, mode
)
585 enum machine_mode mode
;
587 return op
== CONST0_RTX (mode
) || register_operand (op
, mode
);
590 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
594 reg_or_6bit_operand (op
, mode
)
596 enum machine_mode mode
;
598 return ((GET_CODE (op
) == CONST_INT
599 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64)
600 || register_operand (op
, mode
));
604 /* Return 1 if OP is an 8-bit constant or any register. */
607 reg_or_8bit_operand (op
, mode
)
609 enum machine_mode mode
;
611 return ((GET_CODE (op
) == CONST_INT
612 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
613 || register_operand (op
, mode
));
616 /* Return 1 if OP is a constant or any register. */
619 reg_or_const_int_operand (op
, mode
)
621 enum machine_mode mode
;
623 return GET_CODE (op
) == CONST_INT
|| register_operand (op
, mode
);
626 /* Return 1 if OP is an 8-bit constant. */
629 cint8_operand (op
, mode
)
631 enum machine_mode mode ATTRIBUTE_UNUSED
;
633 return ((GET_CODE (op
) == CONST_INT
634 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100));
637 /* Return 1 if the operand is a valid second operand to an add insn. */
640 add_operand (op
, mode
)
642 enum machine_mode mode
;
644 if (GET_CODE (op
) == CONST_INT
)
645 /* Constraints I, J, O and P are covered by K. */
646 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K')
647 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
649 return register_operand (op
, mode
);
652 /* Return 1 if the operand is a valid second operand to a sign-extending
656 sext_add_operand (op
, mode
)
658 enum machine_mode mode
;
660 if (GET_CODE (op
) == CONST_INT
)
661 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
662 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'));
664 return reg_not_elim_operand (op
, mode
);
667 /* Return 1 if OP is the constant 4 or 8. */
670 const48_operand (op
, mode
)
672 enum machine_mode mode ATTRIBUTE_UNUSED
;
674 return (GET_CODE (op
) == CONST_INT
675 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
678 /* Return 1 if OP is a valid first operand to an AND insn. */
681 and_operand (op
, mode
)
683 enum machine_mode mode
;
685 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
686 return (zap_mask (CONST_DOUBLE_LOW (op
))
687 && zap_mask (CONST_DOUBLE_HIGH (op
)));
689 if (GET_CODE (op
) == CONST_INT
)
690 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
691 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
692 || zap_mask (INTVAL (op
)));
694 return register_operand (op
, mode
);
697 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
700 or_operand (op
, mode
)
702 enum machine_mode mode
;
704 if (GET_CODE (op
) == CONST_INT
)
705 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
706 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100);
708 return register_operand (op
, mode
);
711 /* Return 1 if OP is a constant that is the width, in bits, of an integral
712 mode smaller than DImode. */
715 mode_width_operand (op
, mode
)
717 enum machine_mode mode ATTRIBUTE_UNUSED
;
719 return (GET_CODE (op
) == CONST_INT
720 && (INTVAL (op
) == 8 || INTVAL (op
) == 16
721 || INTVAL (op
) == 32 || INTVAL (op
) == 64));
724 /* Return 1 if OP is a constant that is the width of an integral machine mode
725 smaller than an integer. */
728 mode_mask_operand (op
, mode
)
730 enum machine_mode mode ATTRIBUTE_UNUSED
;
732 if (GET_CODE (op
) == CONST_INT
)
734 HOST_WIDE_INT value
= INTVAL (op
);
740 if (value
== 0xffffffff)
745 else if (HOST_BITS_PER_WIDE_INT
== 32 && GET_CODE (op
) == CONST_DOUBLE
)
747 if (CONST_DOUBLE_LOW (op
) == 0xffffffff && CONST_DOUBLE_HIGH (op
) == 0)
754 /* Return 1 if OP is a multiple of 8 less than 64. */
757 mul8_operand (op
, mode
)
759 enum machine_mode mode ATTRIBUTE_UNUSED
;
761 return (GET_CODE (op
) == CONST_INT
762 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
763 && (INTVAL (op
) & 7) == 0);
766 /* Return 1 if OP is the zero constant for MODE. */
769 const0_operand (op
, mode
)
771 enum machine_mode mode
;
773 return op
== CONST0_RTX (mode
);
776 /* Return 1 if OP is a hard floating-point register. */
779 hard_fp_register_operand (op
, mode
)
781 enum machine_mode mode
;
783 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
786 if (GET_CODE (op
) == SUBREG
)
787 op
= SUBREG_REG (op
);
788 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == FLOAT_REGS
;
791 /* Return 1 if OP is a hard general register. */
794 hard_int_register_operand (op
, mode
)
796 enum machine_mode mode
;
798 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
801 if (GET_CODE (op
) == SUBREG
)
802 op
= SUBREG_REG (op
);
803 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
;
806 /* Return 1 if OP is a register or a constant integer. */
810 reg_or_cint_operand (op
, mode
)
812 enum machine_mode mode
;
814 return (GET_CODE (op
) == CONST_INT
815 || register_operand (op
, mode
));
818 /* Return 1 if OP is something that can be reloaded into a register;
819 if it is a MEM, it need not be valid. */
822 some_operand (op
, mode
)
824 enum machine_mode mode
;
826 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
829 switch (GET_CODE (op
))
843 return some_operand (SUBREG_REG (op
), VOIDmode
);
852 /* Likewise, but don't accept constants. */
855 some_ni_operand (op
, mode
)
857 enum machine_mode mode
;
859 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
862 if (GET_CODE (op
) == SUBREG
)
863 op
= SUBREG_REG (op
);
865 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == MEM
);
868 /* Return 1 if OP is a valid operand for the source of a move insn. */
871 input_operand (op
, mode
)
873 enum machine_mode mode
;
875 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
878 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
881 switch (GET_CODE (op
))
886 if (TARGET_EXPLICIT_RELOCS
)
888 /* We don't split symbolic operands into something unintelligable
889 until after reload, but we do not wish non-small, non-global
890 symbolic operands to be reconstructed from their high/lo_sum
892 return (small_symbolic_operand (op
, mode
)
893 || global_symbolic_operand (op
, mode
)
894 || gotdtp_symbolic_operand (op
, mode
)
895 || gottp_symbolic_operand (op
, mode
));
898 /* This handles both the Windows/NT and OSF cases. */
899 return mode
== ptr_mode
|| mode
== DImode
;
902 return (TARGET_EXPLICIT_RELOCS
903 && local_symbolic_operand (XEXP (op
, 0), mode
));
910 if (register_operand (op
, mode
))
912 /* ... fall through ... */
914 return ((TARGET_BWX
|| (mode
!= HImode
&& mode
!= QImode
))
915 && general_operand (op
, mode
));
919 return op
== CONST0_RTX (mode
);
922 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
934 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
935 file, and in the same section as the current function. */
938 current_file_function_operand (op
, mode
)
940 enum machine_mode mode ATTRIBUTE_UNUSED
;
942 if (GET_CODE (op
) != SYMBOL_REF
)
945 /* Easy test for recursion. */
946 if (op
== XEXP (DECL_RTL (current_function_decl
), 0))
949 /* Otherwise, we need the DECL for the SYMBOL_REF, which we can't get.
950 So SYMBOL_REF_FLAG has been declared to imply that the function is
951 in the default text section. So we must also check that the current
952 function is also in the text section. */
953 if (SYMBOL_REF_FLAG (op
) && decl_in_text_section (current_function_decl
))
959 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
962 direct_call_operand (op
, mode
)
964 enum machine_mode mode
;
966 /* Must be defined in this file. */
967 if (! current_file_function_operand (op
, mode
))
970 /* If profiling is implemented via linker tricks, we can't jump
971 to the nogp alternate entry point. */
972 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
973 but is approximately correct for the OSF ABIs. Don't know
974 what to do for VMS, NT, or UMK. */
975 if (! TARGET_PROFILING_NEEDS_GP
976 && ! current_function_profile
)
982 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
983 a (non-tls) variable known to be defined in this file. */
986 local_symbolic_operand (op
, mode
)
988 enum machine_mode mode
;
992 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
995 if (GET_CODE (op
) == LABEL_REF
)
998 if (GET_CODE (op
) == CONST
999 && GET_CODE (XEXP (op
, 0)) == PLUS
1000 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1001 op
= XEXP (XEXP (op
, 0), 0);
1003 if (GET_CODE (op
) != SYMBOL_REF
)
1006 /* Easy pickings. */
1007 if (CONSTANT_POOL_ADDRESS_P (op
) || STRING_POOL_ADDRESS_P (op
))
1010 /* ??? SYMBOL_REF_FLAG is set for local function symbols, but we
1011 run into problems with the rtl inliner in that the symbol was
1012 once external, but is local after inlining, which results in
1013 unrecognizable insns. */
1017 /* If @[LS], then alpha_encode_section_info sez it's local. */
1018 if (str
[0] == '@' && (str
[1] == 'L' || str
[1] == 'S'))
1021 /* If *$, then ASM_GENERATE_INTERNAL_LABEL sez it's local. */
1022 if (str
[0] == '*' && str
[1] == '$')
1028 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1029 known to be defined in this file in the small data area. */
1032 small_symbolic_operand (op
, mode
)
1034 enum machine_mode mode ATTRIBUTE_UNUSED
;
1038 if (! TARGET_SMALL_DATA
)
1041 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1044 if (GET_CODE (op
) == CONST
1045 && GET_CODE (XEXP (op
, 0)) == PLUS
1046 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1047 op
= XEXP (XEXP (op
, 0), 0);
1049 if (GET_CODE (op
) != SYMBOL_REF
)
1052 if (CONSTANT_POOL_ADDRESS_P (op
))
1053 return GET_MODE_SIZE (get_pool_mode (op
)) <= (unsigned) g_switch_value
;
1057 return str
[0] == '@' && str
[1] == 'S';
1061 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1062 not known (or known not) to be defined in this file. */
1065 global_symbolic_operand (op
, mode
)
1067 enum machine_mode mode
;
1071 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1074 if (GET_CODE (op
) == CONST
1075 && GET_CODE (XEXP (op
, 0)) == PLUS
1076 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1077 op
= XEXP (XEXP (op
, 0), 0);
1079 if (GET_CODE (op
) != SYMBOL_REF
)
1082 if (local_symbolic_operand (op
, mode
))
1085 /* Also verify that it's not a TLS symbol. */
1087 return str
[0] != '%' && str
[0] != '@';
1090 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
1093 call_operand (op
, mode
)
1095 enum machine_mode mode
;
1100 if (GET_CODE (op
) == REG
)
1104 /* Disallow virtual registers to cope with pathalogical test cases
1105 such as compile/930117-1.c in which the virtual reg decomposes
1106 to the frame pointer. Which is a hard reg that is not $27. */
1107 return (REGNO (op
) == 27 || REGNO (op
) > LAST_VIRTUAL_REGISTER
);
1112 if (TARGET_ABI_UNICOSMK
)
1114 if (GET_CODE (op
) == SYMBOL_REF
)
1120 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1121 possibly with an offset. */
1124 symbolic_operand (op
, mode
)
1126 enum machine_mode mode
;
1128 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1130 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1132 if (GET_CODE (op
) == CONST
1133 && GET_CODE (XEXP (op
,0)) == PLUS
1134 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1135 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1140 /* Return true if OP is valid for a particular TLS relocation. */
1143 tls_symbolic_operand_1 (op
, mode
, size
, unspec
)
1145 enum machine_mode mode
;
1151 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1154 if (GET_CODE (op
) != CONST
)
1158 if (GET_CODE (op
) != UNSPEC
|| XINT (op
, 1) != unspec
)
1160 op
= XVECEXP (op
, 0, 0);
1162 if (GET_CODE (op
) != SYMBOL_REF
)
1171 else if (str
[0] == '@')
1173 if (alpha_tls_size
> size
)
1179 letter
= (unspec
== UNSPEC_DTPREL
? 'D' : 'T');
1181 return str
[1] == letter
;
1184 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1187 dtp16_symbolic_operand (op
, mode
)
1189 enum machine_mode mode
;
1191 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_DTPREL
);
1194 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1197 dtp32_symbolic_operand (op
, mode
)
1199 enum machine_mode mode
;
1201 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_DTPREL
);
1204 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1207 gotdtp_symbolic_operand (op
, mode
)
1209 enum machine_mode mode
;
1211 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_DTPREL
);
1214 /* Return true if OP is valid for 16-bit TP relative relocations. */
1217 tp16_symbolic_operand (op
, mode
)
1219 enum machine_mode mode
;
1221 return tls_symbolic_operand_1 (op
, mode
, 16, UNSPEC_TPREL
);
1224 /* Return true if OP is valid for 32-bit TP relative relocations. */
1227 tp32_symbolic_operand (op
, mode
)
1229 enum machine_mode mode
;
1231 return tls_symbolic_operand_1 (op
, mode
, 32, UNSPEC_TPREL
);
1234 /* Return true if OP is valid for 64-bit TP relative relocations. */
1237 gottp_symbolic_operand (op
, mode
)
1239 enum machine_mode mode
;
1241 return tls_symbolic_operand_1 (op
, mode
, 64, UNSPEC_TPREL
);
1244 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1245 comparisons are valid in which insn. */
1248 alpha_comparison_operator (op
, mode
)
1250 enum machine_mode mode
;
1252 enum rtx_code code
= GET_CODE (op
);
1254 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1257 return (code
== EQ
|| code
== LE
|| code
== LT
1258 || code
== LEU
|| code
== LTU
);
1261 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1262 Here we know which comparisons are valid in which insn. */
1265 alpha_zero_comparison_operator (op
, mode
)
1267 enum machine_mode mode
;
1269 enum rtx_code code
= GET_CODE (op
);
1271 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1274 return (code
== EQ
|| code
== NE
|| code
== LE
|| code
== LT
1275 || code
== LEU
|| code
== LTU
);
1278 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1281 alpha_swapped_comparison_operator (op
, mode
)
1283 enum machine_mode mode
;
1285 enum rtx_code code
= GET_CODE (op
);
1287 if ((mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1288 || GET_RTX_CLASS (code
) != '<')
1291 code
= swap_condition (code
);
1292 return (code
== EQ
|| code
== LE
|| code
== LT
1293 || code
== LEU
|| code
== LTU
);
1296 /* Return 1 if OP is a signed comparison operation. */
1299 signed_comparison_operator (op
, mode
)
1301 enum machine_mode mode ATTRIBUTE_UNUSED
;
1303 enum rtx_code code
= GET_CODE (op
);
1305 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1308 return (code
== EQ
|| code
== NE
1309 || code
== LE
|| code
== LT
1310 || code
== GE
|| code
== GT
);
1313 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1314 Here we know which comparisons are valid in which insn. */
1317 alpha_fp_comparison_operator (op
, mode
)
1319 enum machine_mode mode
;
1321 enum rtx_code code
= GET_CODE (op
);
1323 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1326 return (code
== EQ
|| code
== LE
|| code
== LT
|| code
== UNORDERED
);
1329 /* Return 1 if this is a divide or modulus operator. */
1332 divmod_operator (op
, mode
)
1334 enum machine_mode mode ATTRIBUTE_UNUSED
;
1336 switch (GET_CODE (op
))
1338 case DIV
: case MOD
: case UDIV
: case UMOD
:
1348 /* Return 1 if this memory address is a known aligned register plus
1349 a constant. It must be a valid address. This means that we can do
1350 this as an aligned reference plus some offset.
1352 Take into account what reload will do. */
1355 aligned_memory_operand (op
, mode
)
1357 enum machine_mode mode
;
1361 if (reload_in_progress
)
1364 if (GET_CODE (tmp
) == SUBREG
)
1365 tmp
= SUBREG_REG (tmp
);
1366 if (GET_CODE (tmp
) == REG
1367 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1369 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1375 if (GET_CODE (op
) != MEM
1376 || GET_MODE (op
) != mode
)
1380 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1381 sorts of constructs. Dig for the real base register. */
1382 if (reload_in_progress
1383 && GET_CODE (op
) == PLUS
1384 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1385 base
= XEXP (XEXP (op
, 0), 0);
1388 if (! memory_address_p (mode
, op
))
1390 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1393 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) >= 32);
1396 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1399 unaligned_memory_operand (op
, mode
)
1401 enum machine_mode mode
;
1405 if (reload_in_progress
)
1408 if (GET_CODE (tmp
) == SUBREG
)
1409 tmp
= SUBREG_REG (tmp
);
1410 if (GET_CODE (tmp
) == REG
1411 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1413 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1419 if (GET_CODE (op
) != MEM
1420 || GET_MODE (op
) != mode
)
1424 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1425 sorts of constructs. Dig for the real base register. */
1426 if (reload_in_progress
1427 && GET_CODE (op
) == PLUS
1428 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1429 base
= XEXP (XEXP (op
, 0), 0);
1432 if (! memory_address_p (mode
, op
))
1434 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1437 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) < 32);
1440 /* Return 1 if OP is either a register or an unaligned memory location. */
1443 reg_or_unaligned_mem_operand (op
, mode
)
1445 enum machine_mode mode
;
1447 return register_operand (op
, mode
) || unaligned_memory_operand (op
, mode
);
1450 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1453 any_memory_operand (op
, mode
)
1455 enum machine_mode mode ATTRIBUTE_UNUSED
;
1457 return (GET_CODE (op
) == MEM
1458 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
1459 || (reload_in_progress
&& GET_CODE (op
) == REG
1460 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1461 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
1462 && GET_CODE (SUBREG_REG (op
)) == REG
1463 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
1466 /* Returns 1 if OP is not an eliminable register.
1468 This exists to cure a pathological abort in the s8addq (et al) patterns,
1470 long foo () { long t; bar(); return (long) &t * 26107; }
1472 which run afoul of a hack in reload to cure a (presumably) similar
1473 problem with lea-type instructions on other targets. But there is
1474 one of us and many of them, so work around the problem by selectively
1475 preventing combine from making the optimization. */
1478 reg_not_elim_operand (op
, mode
)
1480 enum machine_mode mode
;
1483 if (GET_CODE (op
) == SUBREG
)
1484 inner
= SUBREG_REG (op
);
1485 if (inner
== frame_pointer_rtx
|| inner
== arg_pointer_rtx
)
1488 return register_operand (op
, mode
);
1491 /* Return 1 is OP is a memory location that is not a reference (using
1492 an AND) to an unaligned location. Take into account what reload
1496 normal_memory_operand (op
, mode
)
1498 enum machine_mode mode ATTRIBUTE_UNUSED
;
1500 if (reload_in_progress
)
1503 if (GET_CODE (tmp
) == SUBREG
)
1504 tmp
= SUBREG_REG (tmp
);
1505 if (GET_CODE (tmp
) == REG
1506 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1508 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1510 /* This may not have been assigned an equivalent address if it will
1511 be eliminated. In that case, it doesn't matter what we do. */
1517 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) != AND
;
1520 /* Accept a register, but not a subreg of any kind. This allows us to
1521 avoid pathological cases in reload wrt data movement common in
1522 int->fp conversion. */
1525 reg_no_subreg_operand (op
, mode
)
1527 enum machine_mode mode
;
1529 if (GET_CODE (op
) != REG
)
1531 return register_operand (op
, mode
);
1534 /* Recognize an addition operation that includes a constant. Used to
1535 convince reload to canonize (plus (plus reg c1) c2) during register
1539 addition_operation (op
, mode
)
1541 enum machine_mode mode
;
1543 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1545 if (GET_CODE (op
) == PLUS
1546 && register_operand (XEXP (op
, 0), mode
)
1547 && GET_CODE (XEXP (op
, 1)) == CONST_INT
1548 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op
, 1)), 'K'))
1553 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1554 the range defined for C in [I-P]. */
1557 alpha_const_ok_for_letter_p (value
, c
)
1558 HOST_WIDE_INT value
;
1564 /* An unsigned 8 bit constant. */
1565 return (unsigned HOST_WIDE_INT
) value
< 0x100;
1567 /* The constant zero. */
1570 /* A signed 16 bit constant. */
1571 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
1573 /* A shifted signed 16 bit constant appropriate for LDAH. */
1574 return ((value
& 0xffff) == 0
1575 && ((value
) >> 31 == -1 || value
>> 31 == 0));
1577 /* A constant that can be AND'ed with using a ZAP insn. */
1578 return zap_mask (value
);
1580 /* A complemented unsigned 8 bit constant. */
1581 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
1583 /* A negated unsigned 8 bit constant. */
1584 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
1586 /* The constant 1, 2 or 3. */
1587 return value
== 1 || value
== 2 || value
== 3;
1594 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1595 matches for C in [GH]. */
1598 alpha_const_double_ok_for_letter_p (value
, c
)
1605 /* The floating point zero constant. */
1606 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
1607 && value
== CONST0_RTX (GET_MODE (value
)));
1610 /* A valid operand of a ZAP insn. */
1611 return (GET_MODE (value
) == VOIDmode
1612 && zap_mask (CONST_DOUBLE_LOW (value
))
1613 && zap_mask (CONST_DOUBLE_HIGH (value
)));
1620 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1624 alpha_extra_constraint (value
, c
)
1631 return normal_memory_operand (value
, VOIDmode
);
1633 return direct_call_operand (value
, Pmode
);
1635 return (GET_CODE (value
) == CONST_INT
1636 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
1638 return GET_CODE (value
) == HIGH
;
1640 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
1642 return (GET_CODE (value
) == CONST_VECTOR
1643 && value
== CONST0_RTX (GET_MODE (value
)));
1649 /* Return 1 if this function can directly return via $26. */
1654 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
1656 && alpha_sa_size () == 0
1657 && get_frame_size () == 0
1658 && current_function_outgoing_args_size
== 0
1659 && current_function_pretend_args_size
== 0);
1662 /* Return the ADDR_VEC associated with a tablejump insn. */
1665 alpha_tablejump_addr_vec (insn
)
1670 tmp
= JUMP_LABEL (insn
);
1673 tmp
= NEXT_INSN (tmp
);
1676 if (GET_CODE (tmp
) == JUMP_INSN
1677 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
1678 return PATTERN (tmp
);
1682 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1685 alpha_tablejump_best_label (insn
)
1688 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
1689 rtx best_label
= NULL_RTX
;
1691 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1692 there for edge frequency counts from profile data. */
1696 int n_labels
= XVECLEN (jump_table
, 1);
1697 int best_count
= -1;
1700 for (i
= 0; i
< n_labels
; i
++)
1704 for (j
= i
+ 1; j
< n_labels
; j
++)
1705 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
1706 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
1709 if (count
> best_count
)
1710 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
1714 return best_label
? best_label
: const0_rtx
;
1717 /* Return the TLS model to use for SYMBOL. */
1719 static enum tls_model
1720 tls_symbolic_operand_type (symbol
)
1725 if (GET_CODE (symbol
) != SYMBOL_REF
)
1727 str
= XSTR (symbol
, 0);
1731 /* ??? Be prepared for -ftls-model=local-dynamic. Perhaps we shouldn't
1732 have separately encoded local-ness. On well, maybe the user will use
1733 attribute visibility next time. At least we don't crash... */
1734 if (str
[1] == 'G' || str
[1] == 'D')
1735 return TLS_MODEL_GLOBAL_DYNAMIC
;
1737 return TLS_MODEL_INITIAL_EXEC
;
1739 else if (str
[0] == '@')
1743 /* Local dynamic is a waste if we're not going to combine
1744 the __tls_get_addr calls. So avoid it if not optimizing. */
1746 return TLS_MODEL_LOCAL_DYNAMIC
;
1748 return TLS_MODEL_GLOBAL_DYNAMIC
;
1752 /* 64-bit local exec is the same as initial exec except without
1753 the dynamic relocation. In either case we use a got entry. */
1754 if (alpha_tls_size
== 64)
1755 return TLS_MODEL_INITIAL_EXEC
;
1757 return TLS_MODEL_LOCAL_EXEC
;
1765 /* Return true if the function DECL will be placed in the default text
1767 /* ??? Ideally we'd be able to always move from a SYMBOL_REF back to the
1768 decl, as that would allow us to determine if two functions are in the
1769 same section, which is what we really want to know. */
1772 decl_in_text_section (decl
)
1775 return (DECL_SECTION_NAME (decl
) == NULL_TREE
1776 && ! (flag_function_sections
1777 || (targetm
.have_named_sections
1778 && DECL_ONE_ONLY (decl
))));
1781 /* Return true if EXP should be placed in the small data section. */
1784 alpha_in_small_data_p (exp
)
1787 /* We want to merge strings, so we never consider them small data. */
1788 if (TREE_CODE (exp
) == STRING_CST
)
1791 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
1793 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
1794 if (strcmp (section
, ".sdata") == 0
1795 || strcmp (section
, ".sbss") == 0)
1800 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
1802 /* If this is an incomplete type with size 0, then we can't put it
1803 in sdata because it might be too big when completed. */
1804 if (size
> 0 && size
<= g_switch_value
)
1811 /* If we are referencing a function that is static, make the SYMBOL_REF
1812 special. We use this to see indicate we can branch to this function
1813 without setting PV or restoring GP.
1815 If this is a variable that is known to be defined locally, add "@v"
1816 to the name. If in addition the variable is to go in .sdata/.sbss,
1817 then add "@s" instead. */
1820 alpha_encode_section_info (decl
, first
)
1822 int first ATTRIBUTE_UNUSED
;
1824 const char *symbol_str
;
1829 rtl
= DECL_P (decl
) ? DECL_RTL (decl
) : TREE_CST_RTL (decl
);
1831 /* Careful not to prod global register variables. */
1832 if (GET_CODE (rtl
) != MEM
)
1834 symbol
= XEXP (rtl
, 0);
1835 if (GET_CODE (symbol
) != SYMBOL_REF
)
1838 if (TREE_CODE (decl
) == FUNCTION_DECL
)
1840 /* We mark public functions once they are emitted; otherwise we
1841 don't know that they exist in this unit of translation. */
1842 if (TREE_PUBLIC (decl
))
1845 /* Do not mark functions that are not in .text; otherwise we
1846 don't know that they are near enough for a direct branch. */
1847 if (! decl_in_text_section (decl
))
1850 SYMBOL_REF_FLAG (symbol
) = 1;
1854 /* Early out if we're not going to do anything with this data. */
1855 if (! TARGET_EXPLICIT_RELOCS
)
1858 symbol_str
= XSTR (symbol
, 0);
1860 /* A variable is considered "local" if it is defined in this module. */
1861 is_local
= (*targetm
.binds_local_p
) (decl
);
1863 /* Care for TLS variables. */
1864 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL (decl
))
1866 enum tls_model kind
;
1870 kind
= TLS_MODEL_LOCAL_EXEC
;
1872 kind
= TLS_MODEL_INITIAL_EXEC
;
1875 kind
= TLS_MODEL_LOCAL_DYNAMIC
;
1877 kind
= TLS_MODEL_GLOBAL_DYNAMIC
;
1878 if (kind
< flag_tls_default
)
1879 kind
= flag_tls_default
;
1883 case TLS_MODEL_GLOBAL_DYNAMIC
:
1886 case TLS_MODEL_LOCAL_DYNAMIC
:
1889 case TLS_MODEL_INITIAL_EXEC
:
1890 case TLS_MODEL_LOCAL_EXEC
:
1897 /* Determine if DECL will wind up in .sdata/.sbss. */
1898 if (alpha_in_small_data_p (decl
))
1904 /* Finally, encode this into the symbol string. */
1910 if (symbol_str
[0] == (is_local
? '@' : '%'))
1912 if (symbol_str
[1] == encoding
)
1917 len
= strlen (symbol_str
) + 1;
1918 newstr
= alloca (len
+ 2);
1920 newstr
[0] = (is_local
? '@' : '%');
1921 newstr
[1] = encoding
;
1922 memcpy (newstr
+ 2, symbol_str
, len
);
1924 XSTR (symbol
, 0) = ggc_alloc_string (newstr
, len
+ 2 - 1);
1928 /* Undo the effects of the above. */
1931 alpha_strip_name_encoding (str
)
1934 if (str
[0] == '@' || str
[0] == '%')
1941 /* legitimate_address_p recognizes an RTL expression that is a valid
1942 memory address for an instruction. The MODE argument is the
1943 machine mode for the MEM expression that wants to use this address.
1945 For Alpha, we have either a constant address or the sum of a
1946 register and a constant address, or just a register. For DImode,
1947 any of those forms can be surrounded with an AND that clear the
1948 low-order three bits; this is an "unaligned" access. */
1951 alpha_legitimate_address_p (mode
, x
, strict
)
1952 enum machine_mode mode
;
1956 /* If this is an ldq_u type address, discard the outer AND. */
1958 && GET_CODE (x
) == AND
1959 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1960 && INTVAL (XEXP (x
, 1)) == -8)
1963 /* Discard non-paradoxical subregs. */
1964 if (GET_CODE (x
) == SUBREG
1965 && (GET_MODE_SIZE (GET_MODE (x
))
1966 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1969 /* Unadorned general registers are valid. */
1972 ? STRICT_REG_OK_FOR_BASE_P (x
)
1973 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
1976 /* Constant addresses (i.e. +/- 32k) are valid. */
1977 if (CONSTANT_ADDRESS_P (x
))
1980 /* Register plus a small constant offset is valid. */
1981 if (GET_CODE (x
) == PLUS
)
1983 rtx ofs
= XEXP (x
, 1);
1986 /* Discard non-paradoxical subregs. */
1987 if (GET_CODE (x
) == SUBREG
1988 && (GET_MODE_SIZE (GET_MODE (x
))
1989 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1995 && NONSTRICT_REG_OK_FP_BASE_P (x
)
1996 && GET_CODE (ofs
) == CONST_INT
)
1999 ? STRICT_REG_OK_FOR_BASE_P (x
)
2000 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
2001 && CONSTANT_ADDRESS_P (ofs
))
2004 else if (GET_CODE (x
) == ADDRESSOF
2005 && GET_CODE (ofs
) == CONST_INT
)
2009 /* If we're managing explicit relocations, LO_SUM is valid, as
2010 are small data symbols. */
2011 else if (TARGET_EXPLICIT_RELOCS
)
2013 if (small_symbolic_operand (x
, Pmode
))
2016 if (GET_CODE (x
) == LO_SUM
)
2018 rtx ofs
= XEXP (x
, 1);
2021 /* Discard non-paradoxical subregs. */
2022 if (GET_CODE (x
) == SUBREG
2023 && (GET_MODE_SIZE (GET_MODE (x
))
2024 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2027 /* Must have a valid base register. */
2030 ? STRICT_REG_OK_FOR_BASE_P (x
)
2031 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
2034 /* The symbol must be local. */
2035 if (local_symbolic_operand (ofs
, Pmode
)
2036 || dtp32_symbolic_operand (ofs
, Pmode
)
2037 || tp32_symbolic_operand (ofs
, Pmode
))
2045 /* Try machine-dependent ways of modifying an illegitimate address
2046 to be legitimate. If we find one, return the new, valid address. */
2049 alpha_legitimize_address (x
, scratch
, mode
)
2052 enum machine_mode mode ATTRIBUTE_UNUSED
;
2054 HOST_WIDE_INT addend
;
2056 /* If the address is (plus reg const_int) and the CONST_INT is not a
2057 valid offset, compute the high part of the constant and add it to
2058 the register. Then our address is (plus temp low-part-const). */
2059 if (GET_CODE (x
) == PLUS
2060 && GET_CODE (XEXP (x
, 0)) == REG
2061 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2062 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
2064 addend
= INTVAL (XEXP (x
, 1));
2069 /* If the address is (const (plus FOO const_int)), find the low-order
2070 part of the CONST_INT. Then load FOO plus any high-order part of the
2071 CONST_INT into a register. Our address is (plus reg low-part-const).
2072 This is done to reduce the number of GOT entries. */
2074 && GET_CODE (x
) == CONST
2075 && GET_CODE (XEXP (x
, 0)) == PLUS
2076 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2078 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
2079 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
2083 /* If we have a (plus reg const), emit the load as in (2), then add
2084 the two registers, and finally generate (plus reg low-part-const) as
2087 && GET_CODE (x
) == PLUS
2088 && GET_CODE (XEXP (x
, 0)) == REG
2089 && GET_CODE (XEXP (x
, 1)) == CONST
2090 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
2091 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
2093 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
2094 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
2095 XEXP (XEXP (XEXP (x
, 1), 0), 0),
2096 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
2100 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
2101 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
2103 rtx r0
, r16
, eqv
, tga
, tp
, insn
, dest
, seq
;
2105 switch (tls_symbolic_operand_type (x
))
2107 case TLS_MODEL_GLOBAL_DYNAMIC
:
2110 r0
= gen_rtx_REG (Pmode
, 0);
2111 r16
= gen_rtx_REG (Pmode
, 16);
2112 tga
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
2113 dest
= gen_reg_rtx (Pmode
);
2114 seq
= GEN_INT (alpha_next_sequence_number
++);
2116 emit_insn (gen_movdi_er_tlsgd (r16
, pic_offset_table_rtx
, x
, seq
));
2117 insn
= gen_call_value_osf_tlsgd (r0
, tga
, seq
);
2118 insn
= emit_call_insn (insn
);
2119 CONST_OR_PURE_CALL_P (insn
) = 1;
2120 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2122 insn
= get_insns ();
2125 emit_libcall_block (insn
, dest
, r0
, x
);
2128 case TLS_MODEL_LOCAL_DYNAMIC
:
2131 r0
= gen_rtx_REG (Pmode
, 0);
2132 r16
= gen_rtx_REG (Pmode
, 16);
2133 tga
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
2134 scratch
= gen_reg_rtx (Pmode
);
2135 seq
= GEN_INT (alpha_next_sequence_number
++);
2137 emit_insn (gen_movdi_er_tlsldm (r16
, pic_offset_table_rtx
, seq
));
2138 insn
= gen_call_value_osf_tlsldm (r0
, tga
, seq
);
2139 insn
= emit_call_insn (insn
);
2140 CONST_OR_PURE_CALL_P (insn
) = 1;
2141 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), r16
);
2143 insn
= get_insns ();
2146 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2147 UNSPEC_TLSLDM_CALL
);
2148 emit_libcall_block (insn
, scratch
, r0
, eqv
);
2150 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPREL
);
2151 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2153 if (alpha_tls_size
== 64)
2155 dest
= gen_reg_rtx (Pmode
);
2156 emit_insn (gen_rtx_SET (VOIDmode
, dest
, eqv
));
2157 emit_insn (gen_adddi3 (dest
, dest
, scratch
));
2160 if (alpha_tls_size
== 32)
2162 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2163 insn
= gen_rtx_PLUS (Pmode
, scratch
, insn
);
2164 scratch
= gen_reg_rtx (Pmode
);
2165 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, insn
));
2167 return gen_rtx_LO_SUM (Pmode
, scratch
, eqv
);
2169 case TLS_MODEL_INITIAL_EXEC
:
2170 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2171 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2172 tp
= gen_reg_rtx (Pmode
);
2173 scratch
= gen_reg_rtx (Pmode
);
2174 dest
= gen_reg_rtx (Pmode
);
2176 emit_insn (gen_load_tp (tp
));
2177 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, eqv
));
2178 emit_insn (gen_adddi3 (dest
, tp
, scratch
));
2181 case TLS_MODEL_LOCAL_EXEC
:
2182 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_TPREL
);
2183 eqv
= gen_rtx_CONST (Pmode
, eqv
);
2184 tp
= gen_reg_rtx (Pmode
);
2186 emit_insn (gen_load_tp (tp
));
2187 if (alpha_tls_size
== 32)
2189 insn
= gen_rtx_HIGH (Pmode
, eqv
);
2190 insn
= gen_rtx_PLUS (Pmode
, tp
, insn
);
2191 tp
= gen_reg_rtx (Pmode
);
2192 emit_insn (gen_rtx_SET (VOIDmode
, tp
, insn
));
2194 return gen_rtx_LO_SUM (Pmode
, tp
, eqv
);
2197 if (local_symbolic_operand (x
, Pmode
))
2199 if (small_symbolic_operand (x
, Pmode
))
2203 if (!no_new_pseudos
)
2204 scratch
= gen_reg_rtx (Pmode
);
2205 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
2206 gen_rtx_HIGH (Pmode
, x
)));
2207 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
2216 HOST_WIDE_INT low
, high
;
2218 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
2220 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2224 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
2225 (no_new_pseudos
? scratch
: NULL_RTX
),
2226 1, OPTAB_LIB_WIDEN
);
2228 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
2229 (no_new_pseudos
? scratch
: NULL_RTX
),
2230 1, OPTAB_LIB_WIDEN
);
2232 return plus_constant (x
, low
);
2236 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
2237 small symbolic operand until after reload. At which point we need
2238 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
2239 so that sched2 has the proper dependency information. */
2242 some_small_symbolic_operand (x
, mode
)
2244 enum machine_mode mode ATTRIBUTE_UNUSED
;
2246 return for_each_rtx (&x
, some_small_symbolic_operand_1
, NULL
);
2250 some_small_symbolic_operand_1 (px
, data
)
2252 void *data ATTRIBUTE_UNUSED
;
2256 /* Don't re-split. */
2257 if (GET_CODE (x
) == LO_SUM
)
2260 return small_symbolic_operand (x
, Pmode
) != 0;
2264 split_small_symbolic_operand (x
)
2268 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
2273 split_small_symbolic_operand_1 (px
, data
)
2275 void *data ATTRIBUTE_UNUSED
;
2279 /* Don't re-split. */
2280 if (GET_CODE (x
) == LO_SUM
)
2283 if (small_symbolic_operand (x
, Pmode
))
2285 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
2293 /* Try a machine-dependent way of reloading an illegitimate address
2294 operand. If we find one, push the reload and return the new rtx. */
2297 alpha_legitimize_reload_address (x
, mode
, opnum
, type
, ind_levels
)
2299 enum machine_mode mode ATTRIBUTE_UNUSED
;
2302 int ind_levels ATTRIBUTE_UNUSED
;
2304 /* We must recognize output that we have already generated ourselves. */
2305 if (GET_CODE (x
) == PLUS
2306 && GET_CODE (XEXP (x
, 0)) == PLUS
2307 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2308 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2309 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2311 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2312 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2317 /* We wish to handle large displacements off a base register by
2318 splitting the addend across an ldah and the mem insn. This
2319 cuts number of extra insns needed from 3 to 1. */
2320 if (GET_CODE (x
) == PLUS
2321 && GET_CODE (XEXP (x
, 0)) == REG
2322 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2323 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
2324 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2326 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
2327 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
2329 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2331 /* Check for 32-bit overflow. */
2332 if (high
+ low
!= val
)
2335 /* Reload the high part into a base reg; leave the low part
2336 in the mem directly. */
2337 x
= gen_rtx_PLUS (GET_MODE (x
),
2338 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
2342 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2343 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
2351 /* REF is an alignable memory location. Place an aligned SImode
2352 reference into *PALIGNED_MEM and the number of bits to shift into
2353 *PBITNUM. SCRATCH is a free register for use in reloading out
2354 of range stack slots. */
2357 get_aligned_mem (ref
, paligned_mem
, pbitnum
)
2359 rtx
*paligned_mem
, *pbitnum
;
2362 HOST_WIDE_INT offset
= 0;
2364 if (GET_CODE (ref
) != MEM
)
2367 if (reload_in_progress
2368 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2370 base
= find_replacement (&XEXP (ref
, 0));
2372 if (! memory_address_p (GET_MODE (ref
), base
))
2377 base
= XEXP (ref
, 0);
2380 if (GET_CODE (base
) == PLUS
)
2381 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2384 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
2386 if (WORDS_BIG_ENDIAN
)
2387 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
2388 + (offset
& 3) * 8));
2390 *pbitnum
= GEN_INT ((offset
& 3) * 8);
2393 /* Similar, but just get the address. Handle the two reload cases.
2394 Add EXTRA_OFFSET to the address we return. */
2397 get_unaligned_address (ref
, extra_offset
)
2402 HOST_WIDE_INT offset
= 0;
2404 if (GET_CODE (ref
) != MEM
)
2407 if (reload_in_progress
2408 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2410 base
= find_replacement (&XEXP (ref
, 0));
2412 if (! memory_address_p (GET_MODE (ref
), base
))
2417 base
= XEXP (ref
, 0);
2420 if (GET_CODE (base
) == PLUS
)
2421 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2423 return plus_constant (base
, offset
+ extra_offset
);
2426 /* On the Alpha, all (non-symbolic) constants except zero go into
2427 a floating-point register via memory. Note that we cannot
2428 return anything that is not a subset of CLASS, and that some
2429 symbolic constants cannot be dropped to memory. */
2432 alpha_preferred_reload_class(x
, class)
2434 enum reg_class
class;
2436 /* Zero is present in any register class. */
2437 if (x
== CONST0_RTX (GET_MODE (x
)))
2440 /* These sorts of constants we can easily drop to memory. */
2441 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2443 if (class == FLOAT_REGS
)
2445 if (class == ALL_REGS
)
2446 return GENERAL_REGS
;
2450 /* All other kinds of constants should not (and in the case of HIGH
2451 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2452 secondary reload. */
2454 return (class == ALL_REGS
? GENERAL_REGS
: class);
2459 /* Loading and storing HImode or QImode values to and from memory
2460 usually requires a scratch register. The exceptions are loading
2461 QImode and HImode from an aligned address to a general register
2462 unless byte instructions are permitted.
2464 We also cannot load an unaligned address or a paradoxical SUBREG
2465 into an FP register.
2467 We also cannot do integral arithmetic into FP regs, as might result
2468 from register elimination into a DImode fp register. */
2471 secondary_reload_class (class, mode
, x
, in
)
2472 enum reg_class
class;
2473 enum machine_mode mode
;
2477 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
2479 if (GET_CODE (x
) == MEM
2480 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
2481 || (GET_CODE (x
) == SUBREG
2482 && (GET_CODE (SUBREG_REG (x
)) == MEM
2483 || (GET_CODE (SUBREG_REG (x
)) == REG
2484 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
2486 if (!in
|| !aligned_memory_operand(x
, mode
))
2487 return GENERAL_REGS
;
2491 if (class == FLOAT_REGS
)
2493 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
2494 return GENERAL_REGS
;
2496 if (GET_CODE (x
) == SUBREG
2497 && (GET_MODE_SIZE (GET_MODE (x
))
2498 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2499 return GENERAL_REGS
;
2501 if (in
&& INTEGRAL_MODE_P (mode
)
2502 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
2503 return GENERAL_REGS
;
2509 /* Subfunction of the following function. Update the flags of any MEM
2510 found in part of X. */
2513 alpha_set_memflags_1 (x
, in_struct_p
, volatile_p
, unchanging_p
)
2515 int in_struct_p
, volatile_p
, unchanging_p
;
2519 switch (GET_CODE (x
))
2525 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2526 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
2531 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
2536 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
2538 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
2543 MEM_IN_STRUCT_P (x
) = in_struct_p
;
2544 MEM_VOLATILE_P (x
) = volatile_p
;
2545 RTX_UNCHANGING_P (x
) = unchanging_p
;
2546 /* Sadly, we cannot use alias sets because the extra aliasing
2547 produced by the AND interferes. Given that two-byte quantities
2548 are the only thing we would be able to differentiate anyway,
2549 there does not seem to be any point in convoluting the early
2550 out of the alias check. */
2558 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2559 generated to perform a memory operation, look for any MEMs in either
2560 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2561 volatile flags from REF into each of the MEMs found. If REF is not
2562 a MEM, don't do anything. */
2565 alpha_set_memflags (insn
, ref
)
2569 int in_struct_p
, volatile_p
, unchanging_p
;
2571 if (GET_CODE (ref
) != MEM
)
2574 in_struct_p
= MEM_IN_STRUCT_P (ref
);
2575 volatile_p
= MEM_VOLATILE_P (ref
);
2576 unchanging_p
= RTX_UNCHANGING_P (ref
);
2578 /* This is only called from alpha.md, after having had something
2579 generated from one of the insn patterns. So if everything is
2580 zero, the pattern is already up-to-date. */
2581 if (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
)
2584 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
2587 /* Try to output insns to set TARGET equal to the constant C if it can be
2588 done in less than N insns. Do all computations in MODE. Returns the place
2589 where the output has been placed if it can be done and the insns have been
2590 emitted. If it would take more than N insns, zero is returned and no
2591 insns and emitted. */
2594 alpha_emit_set_const (target
, mode
, c
, n
)
2596 enum machine_mode mode
;
2601 rtx orig_target
= target
;
2604 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2605 can't load this constant in one insn, do this in DImode. */
2606 if (no_new_pseudos
&& mode
== SImode
2607 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
2608 && (result
= alpha_emit_set_const_1 (target
, mode
, c
, 1)) == 0)
2610 target
= gen_lowpart (DImode
, target
);
2614 /* Try 1 insn, then 2, then up to N. */
2615 for (i
= 1; i
<= n
; i
++)
2617 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
);
2620 rtx insn
= get_last_insn ();
2621 rtx set
= single_set (insn
);
2622 if (! CONSTANT_P (SET_SRC (set
)))
2623 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
2628 /* Allow for the case where we changed the mode of TARGET. */
2629 if (result
== target
)
2630 result
= orig_target
;
2635 /* Internal routine for the above to check for N or below insns. */
2638 alpha_emit_set_const_1 (target
, mode
, c
, n
)
2640 enum machine_mode mode
;
2646 /* Use a pseudo if highly optimizing and still generating RTL. */
2648 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
2651 /* If this is a sign-extended 32-bit constant, we can do this in at most
2652 three insns, so do it if we have enough insns left. We always have
2653 a sign-extended 32-bit constant when compiling on a narrow machine. */
2655 if (HOST_BITS_PER_WIDE_INT
!= 64
2656 || c
>> 31 == -1 || c
>> 31 == 0)
2658 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
2659 HOST_WIDE_INT tmp1
= c
- low
;
2660 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
2661 HOST_WIDE_INT extra
= 0;
2663 /* If HIGH will be interpreted as negative but the constant is
2664 positive, we must adjust it to do two ldha insns. */
2666 if ((high
& 0x8000) != 0 && c
>= 0)
2670 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
2673 if (c
== low
|| (low
== 0 && extra
== 0))
2675 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2676 but that meant that we can't handle INT_MIN on 32-bit machines
2677 (like NT/Alpha), because we recurse indefinitely through
2678 emit_move_insn to gen_movdi. So instead, since we know exactly
2679 what we want, create it explicitly. */
2682 target
= gen_reg_rtx (mode
);
2683 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
2686 else if (n
>= 2 + (extra
!= 0))
2688 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16), subtarget
, mode
);
2690 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2691 This means that if we go through expand_binop, we'll try to
2692 generate extensions, etc, which will require new pseudos, which
2693 will fail during some split phases. The SImode add patterns
2694 still exist, but are not named. So build the insns by hand. */
2699 subtarget
= gen_reg_rtx (mode
);
2700 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
2701 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
2707 target
= gen_reg_rtx (mode
);
2708 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
2709 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
2715 /* If we couldn't do it that way, try some other methods. But if we have
2716 no instructions left, don't bother. Likewise, if this is SImode and
2717 we can't make pseudos, we can't do anything since the expand_binop
2718 and expand_unop calls will widen and try to make pseudos. */
2720 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
2723 /* Next, see if we can load a related constant and then shift and possibly
2724 negate it to get the constant we want. Try this once each increasing
2725 numbers of insns. */
2727 for (i
= 1; i
< n
; i
++)
2729 /* First, see if minus some low bits, we've an easy load of
2732 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
2734 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
2735 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
2736 target
, 0, OPTAB_WIDEN
);
2738 /* Next try complementing. */
2739 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
2740 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
2742 /* Next try to form a constant and do a left shift. We can do this
2743 if some low-order bits are zero; the exact_log2 call below tells
2744 us that information. The bits we are shifting out could be any
2745 value, but here we'll just try the 0- and sign-extended forms of
2746 the constant. To try to increase the chance of having the same
2747 constant in more than one insn, start at the highest number of
2748 bits to shift, but try all possibilities in case a ZAPNOT will
2751 if ((bits
= exact_log2 (c
& - c
)) > 0)
2752 for (; bits
> 0; bits
--)
2753 if ((temp
= (alpha_emit_set_const
2754 (subtarget
, mode
, c
>> bits
, i
))) != 0
2755 || ((temp
= (alpha_emit_set_const
2757 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
2759 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
2760 target
, 0, OPTAB_WIDEN
);
2762 /* Now try high-order zero bits. Here we try the shifted-in bits as
2763 all zero and all ones. Be careful to avoid shifting outside the
2764 mode and to avoid shifting outside the host wide int size. */
2765 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2766 confuse the recursive call and set all of the high 32 bits. */
2768 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2769 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
2770 for (; bits
> 0; bits
--)
2771 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2773 || ((temp
= (alpha_emit_set_const
2775 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2778 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
2779 target
, 1, OPTAB_WIDEN
);
2781 /* Now try high-order 1 bits. We get that with a sign-extension.
2782 But one bit isn't enough here. Be careful to avoid shifting outside
2783 the mode and to avoid shifting outside the host wide int size. */
2785 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2786 - floor_log2 (~ c
) - 2)) > 0)
2787 for (; bits
> 0; bits
--)
2788 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2790 || ((temp
= (alpha_emit_set_const
2792 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2795 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
2796 target
, 0, OPTAB_WIDEN
);
2799 #if HOST_BITS_PER_WIDE_INT == 64
2800 /* Finally, see if can load a value into the target that is the same as the
2801 constant except that all bytes that are 0 are changed to be 0xff. If we
2802 can, then we can do a ZAPNOT to obtain the desired constant. */
2805 for (i
= 0; i
< 64; i
+= 8)
2806 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
2807 new |= (HOST_WIDE_INT
) 0xff << i
;
2809 /* We are only called for SImode and DImode. If this is SImode, ensure that
2810 we are sign extended to a full word. */
2813 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2815 if (new != c
&& new != -1
2816 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
2817 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
2818 target
, 0, OPTAB_WIDEN
);
2824 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2825 fall back to a straight forward decomposition. We do this to avoid
2826 exponential run times encountered when looking for longer sequences
2827 with alpha_emit_set_const. */
2830 alpha_emit_set_long_const (target
, c1
, c2
)
2832 HOST_WIDE_INT c1
, c2
;
2834 HOST_WIDE_INT d1
, d2
, d3
, d4
;
2836 /* Decompose the entire word */
2837 #if HOST_BITS_PER_WIDE_INT >= 64
2838 if (c2
!= -(c1
< 0))
2840 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2842 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2843 c1
= (c1
- d2
) >> 32;
2844 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2846 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2850 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2852 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2856 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
2858 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2863 /* Construct the high word */
2866 emit_move_insn (target
, GEN_INT (d4
));
2868 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2871 emit_move_insn (target
, GEN_INT (d3
));
2873 /* Shift it into place */
2874 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2876 /* Add in the low bits. */
2878 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2880 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
2885 /* Expand a move instruction; return true if all work is done.
2886 We don't handle non-bwx subword loads here. */
2889 alpha_expand_mov (mode
, operands
)
2890 enum machine_mode mode
;
2893 /* If the output is not a register, the input must be. */
2894 if (GET_CODE (operands
[0]) == MEM
2895 && ! reg_or_0_operand (operands
[1], mode
))
2896 operands
[1] = force_reg (mode
, operands
[1]);
2898 /* Allow legitimize_address to perform some simplifications. */
2899 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2903 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2904 compiled at the end of compilation. In the meantime, someone can
2905 re-encode-section-info on some symbol changing it e.g. from global
2906 to local-not-small. If this happens, we'd have emitted a plain
2907 load rather than a high+losum load and not recognize the insn.
2909 So if rtl inlining is in effect, we delay the global/not-global
2910 decision until rest_of_compilation by wrapping it in an
2912 if (TARGET_EXPLICIT_RELOCS
&& flag_inline_functions
2913 && rtx_equal_function_value_matters
2914 && global_symbolic_operand (operands
[1], mode
))
2916 emit_insn (gen_movdi_er_maybe_g (operands
[0], operands
[1]));
2920 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
2923 if (tmp
== operands
[0])
2930 /* Early out for non-constants and valid constants. */
2931 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2934 /* Split large integers. */
2935 if (GET_CODE (operands
[1]) == CONST_INT
2936 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
2938 HOST_WIDE_INT i0
, i1
;
2939 rtx temp
= NULL_RTX
;
2941 if (GET_CODE (operands
[1]) == CONST_INT
)
2943 i0
= INTVAL (operands
[1]);
2946 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2948 i0
= CONST_DOUBLE_LOW (operands
[1]);
2953 i0
= CONST_DOUBLE_LOW (operands
[1]);
2954 i1
= CONST_DOUBLE_HIGH (operands
[1]);
2957 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2958 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
2960 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2961 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
2965 if (rtx_equal_p (operands
[0], temp
))
2972 /* Otherwise we've nothing left but to drop the thing to memory. */
2973 operands
[1] = force_const_mem (DImode
, operands
[1]);
2974 if (reload_in_progress
)
2976 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
2977 operands
[1] = copy_rtx (operands
[1]);
2978 XEXP (operands
[1], 0) = operands
[0];
2981 operands
[1] = validize_mem (operands
[1]);
2985 /* Expand a non-bwx QImode or HImode move instruction;
2986 return true if all work is done. */
2989 alpha_expand_mov_nobwx (mode
, operands
)
2990 enum machine_mode mode
;
2993 /* If the output is not a register, the input must be. */
2994 if (GET_CODE (operands
[0]) == MEM
)
2995 operands
[1] = force_reg (mode
, operands
[1]);
2997 /* Handle four memory cases, unaligned and aligned for either the input
2998 or the output. The only case where we can be called during reload is
2999 for aligned loads; all other cases require temporaries. */
3001 if (GET_CODE (operands
[1]) == MEM
3002 || (GET_CODE (operands
[1]) == SUBREG
3003 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
3004 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
3005 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
3006 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
3007 && GET_CODE (SUBREG_REG (operands
[1])) == REG
3008 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
3010 if (aligned_memory_operand (operands
[1], mode
))
3012 if (reload_in_progress
)
3014 emit_insn ((mode
== QImode
3015 ? gen_reload_inqi_help
3016 : gen_reload_inhi_help
)
3017 (operands
[0], operands
[1],
3018 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
3022 rtx aligned_mem
, bitnum
;
3023 rtx scratch
= gen_reg_rtx (SImode
);
3025 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
3027 emit_insn ((mode
== QImode
3028 ? gen_aligned_loadqi
3029 : gen_aligned_loadhi
)
3030 (operands
[0], aligned_mem
, bitnum
, scratch
));
3035 /* Don't pass these as parameters since that makes the generated
3036 code depend on parameter evaluation order which will cause
3037 bootstrap failures. */
3039 rtx temp1
= gen_reg_rtx (DImode
);
3040 rtx temp2
= gen_reg_rtx (DImode
);
3041 rtx seq
= ((mode
== QImode
3042 ? gen_unaligned_loadqi
3043 : gen_unaligned_loadhi
)
3044 (operands
[0], get_unaligned_address (operands
[1], 0),
3047 alpha_set_memflags (seq
, operands
[1]);
3053 if (GET_CODE (operands
[0]) == MEM
3054 || (GET_CODE (operands
[0]) == SUBREG
3055 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
3056 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
3057 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
3058 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
3059 && GET_CODE (SUBREG_REG (operands
[0])) == REG
3060 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
3062 if (aligned_memory_operand (operands
[0], mode
))
3064 rtx aligned_mem
, bitnum
;
3065 rtx temp1
= gen_reg_rtx (SImode
);
3066 rtx temp2
= gen_reg_rtx (SImode
);
3068 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
3070 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
3075 rtx temp1
= gen_reg_rtx (DImode
);
3076 rtx temp2
= gen_reg_rtx (DImode
);
3077 rtx temp3
= gen_reg_rtx (DImode
);
3078 rtx seq
= ((mode
== QImode
3079 ? gen_unaligned_storeqi
3080 : gen_unaligned_storehi
)
3081 (get_unaligned_address (operands
[0], 0),
3082 operands
[1], temp1
, temp2
, temp3
));
3084 alpha_set_memflags (seq
, operands
[0]);
3093 /* Generate an unsigned DImode to FP conversion. This is the same code
3094 optabs would emit if we didn't have TFmode patterns.
3096 For SFmode, this is the only construction I've found that can pass
3097 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
3098 intermediates will work, because you'll get intermediate rounding
3099 that ruins the end result. Some of this could be fixed by turning
3100 on round-to-positive-infinity, but that requires diddling the fpsr,
3101 which kills performance. I tried turning this around and converting
3102 to a negative number, so that I could turn on /m, but either I did
3103 it wrong or there's something else cause I wound up with the exact
3104 same single-bit error. There is a branch-less form of this same code:
3115 fcmoveq $f10,$f11,$f0
3117 I'm not using it because it's the same number of instructions as
3118 this branch-full form, and it has more serialized long latency
3119 instructions on the critical path.
3121 For DFmode, we can avoid rounding errors by breaking up the word
3122 into two pieces, converting them separately, and adding them back:
3124 LC0: .long 0,0x5f800000
3129 cpyse $f11,$f31,$f10
3130 cpyse $f31,$f11,$f11
3138 This doesn't seem to be a clear-cut win over the optabs form.
3139 It probably all depends on the distribution of numbers being
3140 converted -- in the optabs form, all but high-bit-set has a
3141 much lower minimum execution time. */
3144 alpha_emit_floatuns (operands
)
3147 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
3148 enum machine_mode mode
;
3151 in
= force_reg (DImode
, operands
[1]);
3152 mode
= GET_MODE (out
);
3153 neglab
= gen_label_rtx ();
3154 donelab
= gen_label_rtx ();
3155 i0
= gen_reg_rtx (DImode
);
3156 i1
= gen_reg_rtx (DImode
);
3157 f0
= gen_reg_rtx (mode
);
3159 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
3161 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
3162 emit_jump_insn (gen_jump (donelab
));
3165 emit_label (neglab
);
3167 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
3168 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
3169 emit_insn (gen_iordi3 (i0
, i0
, i1
));
3170 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
3171 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
3173 emit_label (donelab
);
3176 /* Generate the comparison for a conditional branch. */
3179 alpha_emit_conditional_branch (code
)
3182 enum rtx_code cmp_code
, branch_code
;
3183 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
3184 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3187 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
3189 if (! TARGET_HAS_XFLOATING_LIBS
)
3192 /* X_floating library comparison functions return
3196 Convert the compare against the raw return value. */
3218 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3220 alpha_compare
.fp_p
= 0;
3223 /* The general case: fold the comparison code to the types of compares
3224 that we have, choosing the branch as necessary. */
3227 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3229 /* We have these compares: */
3230 cmp_code
= code
, branch_code
= NE
;
3235 /* These must be reversed. */
3236 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
3239 case GE
: case GT
: case GEU
: case GTU
:
3240 /* For FP, we swap them, for INT, we reverse them. */
3241 if (alpha_compare
.fp_p
)
3243 cmp_code
= swap_condition (code
);
3245 tem
= op0
, op0
= op1
, op1
= tem
;
3249 cmp_code
= reverse_condition (code
);
3258 if (alpha_compare
.fp_p
)
3261 if (flag_unsafe_math_optimizations
)
3263 /* When we are not as concerned about non-finite values, and we
3264 are comparing against zero, we can branch directly. */
3265 if (op1
== CONST0_RTX (DFmode
))
3266 cmp_code
= NIL
, branch_code
= code
;
3267 else if (op0
== CONST0_RTX (DFmode
))
3269 /* Undo the swap we probably did just above. */
3270 tem
= op0
, op0
= op1
, op1
= tem
;
3271 branch_code
= swap_condition (cmp_code
);
3277 /* ??? We mark the the branch mode to be CCmode to prevent the
3278 compare and branch from being combined, since the compare
3279 insn follows IEEE rules that the branch does not. */
3280 branch_mode
= CCmode
;
3287 /* The following optimizations are only for signed compares. */
3288 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
3290 /* Whee. Compare and branch against 0 directly. */
3291 if (op1
== const0_rtx
)
3292 cmp_code
= NIL
, branch_code
= code
;
3294 /* We want to use cmpcc/bcc when we can, since there is a zero delay
3295 bypass between logicals and br/cmov on EV5. But we don't want to
3296 force valid immediate constants into registers needlessly. */
3297 else if (GET_CODE (op1
) == CONST_INT
)
3299 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
3301 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
3302 && (CONST_OK_FOR_LETTER_P (n
, 'K')
3303 || CONST_OK_FOR_LETTER_P (n
, 'L')))
3305 cmp_code
= PLUS
, branch_code
= code
;
3311 if (!reg_or_0_operand (op0
, DImode
))
3312 op0
= force_reg (DImode
, op0
);
3313 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
3314 op1
= force_reg (DImode
, op1
);
3317 /* Emit an initial compare instruction, if necessary. */
3319 if (cmp_code
!= NIL
)
3321 tem
= gen_reg_rtx (cmp_mode
);
3322 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
3325 /* Zero the operands. */
3326 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3328 /* Return the branch comparison. */
3329 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
3332 /* Certain simplifications can be done to make invalid setcc operations
3333 valid. Return the final comparison, or NULL if we can't work. */
3336 alpha_emit_setcc (code
)
3339 enum rtx_code cmp_code
;
3340 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
3341 int fp_p
= alpha_compare
.fp_p
;
3344 /* Zero the operands. */
3345 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3347 if (fp_p
&& GET_MODE (op0
) == TFmode
)
3349 if (! TARGET_HAS_XFLOATING_LIBS
)
3352 /* X_floating library comparison functions return
3356 Convert the compare against the raw return value. */
3358 if (code
== UNORDERED
|| code
== ORDERED
)
3363 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3367 if (code
== UNORDERED
)
3369 else if (code
== ORDERED
)
3375 if (fp_p
&& !TARGET_FIX
)
3378 /* The general case: fold the comparison code to the types of compares
3379 that we have, choosing the branch as necessary. */
3384 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3386 /* We have these compares. */
3388 cmp_code
= code
, code
= NE
;
3392 if (!fp_p
&& op1
== const0_rtx
)
3397 cmp_code
= reverse_condition (code
);
3401 case GE
: case GT
: case GEU
: case GTU
:
3402 /* These normally need swapping, but for integer zero we have
3403 special patterns that recognize swapped operands. */
3404 if (!fp_p
&& op1
== const0_rtx
)
3406 code
= swap_condition (code
);
3408 cmp_code
= code
, code
= NE
;
3409 tmp
= op0
, op0
= op1
, op1
= tmp
;
3418 if (!register_operand (op0
, DImode
))
3419 op0
= force_reg (DImode
, op0
);
3420 if (!reg_or_8bit_operand (op1
, DImode
))
3421 op1
= force_reg (DImode
, op1
);
3424 /* Emit an initial compare instruction, if necessary. */
3425 if (cmp_code
!= NIL
)
3427 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
3429 tmp
= gen_reg_rtx (mode
);
3430 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
3431 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
3433 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
3437 /* Return the setcc comparison. */
3438 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
3442 /* Rewrite a comparison against zero CMP of the form
3443 (CODE (cc0) (const_int 0)) so it can be written validly in
3444 a conditional move (if_then_else CMP ...).
3445 If both of the operands that set cc0 are non-zero we must emit
3446 an insn to perform the compare (it can't be done within
3447 the conditional move). */
3449 alpha_emit_conditional_move (cmp
, mode
)
3451 enum machine_mode mode
;
3453 enum rtx_code code
= GET_CODE (cmp
);
3454 enum rtx_code cmov_code
= NE
;
3455 rtx op0
= alpha_compare
.op0
;
3456 rtx op1
= alpha_compare
.op1
;
3457 int fp_p
= alpha_compare
.fp_p
;
3458 enum machine_mode cmp_mode
3459 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
3460 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
3461 enum machine_mode cmov_mode
= VOIDmode
;
3462 int local_fast_math
= flag_unsafe_math_optimizations
;
3465 /* Zero the operands. */
3466 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3468 if (fp_p
!= FLOAT_MODE_P (mode
))
3470 enum rtx_code cmp_code
;
3475 /* If we have fp<->int register move instructions, do a cmov by
3476 performing the comparison in fp registers, and move the
3477 zero/non-zero value to integer registers, where we can then
3478 use a normal cmov, or vice-versa. */
3482 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3483 /* We have these compares. */
3484 cmp_code
= code
, code
= NE
;
3488 /* This must be reversed. */
3489 cmp_code
= EQ
, code
= EQ
;
3492 case GE
: case GT
: case GEU
: case GTU
:
3493 /* These normally need swapping, but for integer zero we have
3494 special patterns that recognize swapped operands. */
3495 if (!fp_p
&& op1
== const0_rtx
)
3496 cmp_code
= code
, code
= NE
;
3499 cmp_code
= swap_condition (code
);
3501 tem
= op0
, op0
= op1
, op1
= tem
;
3509 tem
= gen_reg_rtx (cmp_op_mode
);
3510 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
3511 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
3514 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
3515 op0
= gen_lowpart (cmp_op_mode
, tem
);
3516 op1
= CONST0_RTX (cmp_op_mode
);
3518 local_fast_math
= 1;
3521 /* We may be able to use a conditional move directly.
3522 This avoids emitting spurious compares. */
3523 if (signed_comparison_operator (cmp
, VOIDmode
)
3524 && (!fp_p
|| local_fast_math
)
3525 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
3526 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3528 /* We can't put the comparison inside the conditional move;
3529 emit a compare instruction and put that inside the
3530 conditional move. Make sure we emit only comparisons we have;
3531 swap or reverse as necessary. */
3538 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3539 /* We have these compares: */
3543 /* This must be reversed. */
3544 code
= reverse_condition (code
);
3548 case GE
: case GT
: case GEU
: case GTU
:
3549 /* These must be swapped. */
3550 if (op1
!= CONST0_RTX (cmp_mode
))
3552 code
= swap_condition (code
);
3553 tem
= op0
, op0
= op1
, op1
= tem
;
3563 if (!reg_or_0_operand (op0
, DImode
))
3564 op0
= force_reg (DImode
, op0
);
3565 if (!reg_or_8bit_operand (op1
, DImode
))
3566 op1
= force_reg (DImode
, op1
);
3569 /* ??? We mark the branch mode to be CCmode to prevent the compare
3570 and cmov from being combined, since the compare insn follows IEEE
3571 rules that the cmov does not. */
3572 if (fp_p
&& !local_fast_math
)
3575 tem
= gen_reg_rtx (cmp_op_mode
);
3576 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
3577 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
3580 /* Simplify a conditional move of two constants into a setcc with
3581 arithmetic. This is done with a splitter since combine would
3582 just undo the work if done during code generation. It also catches
3583 cases we wouldn't have before cse. */
3586 alpha_split_conditional_move (code
, dest
, cond
, t_rtx
, f_rtx
)
3588 rtx dest
, cond
, t_rtx
, f_rtx
;
3590 HOST_WIDE_INT t
, f
, diff
;
3591 enum machine_mode mode
;
3592 rtx target
, subtarget
, tmp
;
3594 mode
= GET_MODE (dest
);
3599 if (((code
== NE
|| code
== EQ
) && diff
< 0)
3600 || (code
== GE
|| code
== GT
))
3602 code
= reverse_condition (code
);
3603 diff
= t
, t
= f
, f
= diff
;
3607 subtarget
= target
= dest
;
3610 target
= gen_lowpart (DImode
, dest
);
3611 if (! no_new_pseudos
)
3612 subtarget
= gen_reg_rtx (DImode
);
3616 /* Below, we must be careful to use copy_rtx on target and subtarget
3617 in intermediate insns, as they may be a subreg rtx, which may not
3620 if (f
== 0 && exact_log2 (diff
) > 0
3621 /* On EV6, we've got enough shifters to make non-arithmatic shifts
3622 viable over a longer latency cmove. On EV5, the E0 slot is a
3623 scarce resource, and on EV4 shift has the same latency as a cmove. */
3624 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
3626 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3627 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3629 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
3630 GEN_INT (exact_log2 (t
)));
3631 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3633 else if (f
== 0 && t
== -1)
3635 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3636 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3638 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
3640 else if (diff
== 1 || diff
== 4 || diff
== 8)
3644 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3645 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3648 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
3651 add_op
= GEN_INT (f
);
3652 if (sext_add_operand (add_op
, mode
))
3654 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
3656 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
3657 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3669 /* Look up the function X_floating library function name for the
3673 alpha_lookup_xfloating_lib_func (code
)
3678 const enum rtx_code code
;
3679 const char *const func
;
3682 static const struct xfloating_op vms_xfloating_ops
[] =
3684 { PLUS
, "OTS$ADD_X" },
3685 { MINUS
, "OTS$SUB_X" },
3686 { MULT
, "OTS$MUL_X" },
3687 { DIV
, "OTS$DIV_X" },
3688 { EQ
, "OTS$EQL_X" },
3689 { NE
, "OTS$NEQ_X" },
3690 { LT
, "OTS$LSS_X" },
3691 { LE
, "OTS$LEQ_X" },
3692 { GT
, "OTS$GTR_X" },
3693 { GE
, "OTS$GEQ_X" },
3694 { FIX
, "OTS$CVTXQ" },
3695 { FLOAT
, "OTS$CVTQX" },
3696 { UNSIGNED_FLOAT
, "OTS$CVTQUX" },
3697 { FLOAT_EXTEND
, "OTS$CVT_FLOAT_T_X" },
3698 { FLOAT_TRUNCATE
, "OTS$CVT_FLOAT_X_T" },
3701 static const struct xfloating_op osf_xfloating_ops
[] =
3703 { PLUS
, "_OtsAddX" },
3704 { MINUS
, "_OtsSubX" },
3705 { MULT
, "_OtsMulX" },
3706 { DIV
, "_OtsDivX" },
3713 { FIX
, "_OtsCvtXQ" },
3714 { FLOAT
, "_OtsCvtQX" },
3715 { UNSIGNED_FLOAT
, "_OtsCvtQUX" },
3716 { FLOAT_EXTEND
, "_OtsConvertFloatTX" },
3717 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT" },
3720 const struct xfloating_op
*ops
;
3721 const long n
= ARRAY_SIZE (osf_xfloating_ops
);
3724 /* How irritating. Nothing to key off for the table. Hardcode
3725 knowledge of the G_floating routines. */
3726 if (TARGET_FLOAT_VAX
)
3728 if (TARGET_ABI_OPEN_VMS
)
3730 if (code
== FLOAT_EXTEND
)
3731 return "OTS$CVT_FLOAT_G_X";
3732 if (code
== FLOAT_TRUNCATE
)
3733 return "OTS$CVT_FLOAT_X_G";
3737 if (code
== FLOAT_EXTEND
)
3738 return "_OtsConvertFloatGX";
3739 if (code
== FLOAT_TRUNCATE
)
3740 return "_OtsConvertFloatXG";
3744 if (TARGET_ABI_OPEN_VMS
)
3745 ops
= vms_xfloating_ops
;
3747 ops
= osf_xfloating_ops
;
3749 for (i
= 0; i
< n
; ++i
)
3750 if (ops
[i
].code
== code
)
3756 /* Most X_floating operations take the rounding mode as an argument.
3757 Compute that here. */
3760 alpha_compute_xfloating_mode_arg (code
, round
)
3762 enum alpha_fp_rounding_mode round
;
3768 case ALPHA_FPRM_NORM
:
3771 case ALPHA_FPRM_MINF
:
3774 case ALPHA_FPRM_CHOP
:
3777 case ALPHA_FPRM_DYN
:
3783 /* XXX For reference, round to +inf is mode = 3. */
3786 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3792 /* Emit an X_floating library function call.
3794 Note that these functions do not follow normal calling conventions:
3795 TFmode arguments are passed in two integer registers (as opposed to
3796 indirect); TFmode return values appear in R16+R17.
3798 FUNC is the function name to call.
3799 TARGET is where the output belongs.
3800 OPERANDS are the inputs.
3801 NOPERANDS is the count of inputs.
3802 EQUIV is the expression equivalent for the function.
3806 alpha_emit_xfloating_libcall (func
, target
, operands
, noperands
, equiv
)
3813 rtx usage
= NULL_RTX
, tmp
, reg
;
3818 for (i
= 0; i
< noperands
; ++i
)
3820 switch (GET_MODE (operands
[i
]))
3823 reg
= gen_rtx_REG (TFmode
, regno
);
3828 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3833 if (GET_CODE (operands
[i
]) != CONST_INT
)
3837 reg
= gen_rtx_REG (DImode
, regno
);
3845 emit_move_insn (reg
, operands
[i
]);
3846 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3849 switch (GET_MODE (target
))
3852 reg
= gen_rtx_REG (TFmode
, 16);
3855 reg
= gen_rtx_REG (DFmode
, 32);
3858 reg
= gen_rtx_REG (DImode
, 0);
3864 tmp
= gen_rtx_MEM (QImode
, gen_rtx_SYMBOL_REF (Pmode
, (char *) func
));
3865 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3866 const0_rtx
, const0_rtx
));
3867 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3872 emit_libcall_block (tmp
, target
, reg
, equiv
);
3875 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3878 alpha_emit_xfloating_arith (code
, operands
)
3884 rtx out_operands
[3];
3886 func
= alpha_lookup_xfloating_lib_func (code
);
3887 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3889 out_operands
[0] = operands
[1];
3890 out_operands
[1] = operands
[2];
3891 out_operands
[2] = GEN_INT (mode
);
3892 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
3893 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
3897 /* Emit an X_floating library function call for a comparison. */
3900 alpha_emit_xfloating_compare (code
, op0
, op1
)
3905 rtx out
, operands
[2];
3907 func
= alpha_lookup_xfloating_lib_func (code
);
3911 out
= gen_reg_rtx (DImode
);
3913 /* ??? Strange mode for equiv because what's actually returned
3914 is -1,0,1, not a proper boolean value. */
3915 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
3916 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
3921 /* Emit an X_floating library function call for a conversion. */
3924 alpha_emit_xfloating_cvt (code
, operands
)
3928 int noperands
= 1, mode
;
3929 rtx out_operands
[2];
3932 func
= alpha_lookup_xfloating_lib_func (code
);
3934 out_operands
[0] = operands
[1];
3939 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3940 out_operands
[1] = GEN_INT (mode
);
3943 case FLOAT_TRUNCATE
:
3944 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3945 out_operands
[1] = GEN_INT (mode
);
3952 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3953 gen_rtx_fmt_e (code
, GET_MODE (operands
[0]),
3957 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3958 OP[0] into OP[0,1]. Naturally, output operand ordering is
3962 alpha_split_tfmode_pair (operands
)
3965 if (GET_CODE (operands
[1]) == REG
)
3967 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
3968 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
3970 else if (GET_CODE (operands
[1]) == MEM
)
3972 operands
[3] = adjust_address (operands
[1], DImode
, 8);
3973 operands
[2] = adjust_address (operands
[1], DImode
, 0);
3975 else if (operands
[1] == CONST0_RTX (TFmode
))
3976 operands
[2] = operands
[3] = const0_rtx
;
3980 if (GET_CODE (operands
[0]) == REG
)
3982 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
3983 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
3985 else if (GET_CODE (operands
[0]) == MEM
)
3987 operands
[1] = adjust_address (operands
[0], DImode
, 8);
3988 operands
[0] = adjust_address (operands
[0], DImode
, 0);
3994 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3995 op2 is a register containing the sign bit, operation is the
3996 logical operation to be performed. */
3999 alpha_split_tfmode_frobsign (operands
, operation
)
4001 rtx (*operation
) PARAMS ((rtx
, rtx
, rtx
));
4003 rtx high_bit
= operands
[2];
4007 alpha_split_tfmode_pair (operands
);
4009 /* Detect three flavours of operand overlap. */
4011 if (rtx_equal_p (operands
[0], operands
[2]))
4013 else if (rtx_equal_p (operands
[1], operands
[2]))
4015 if (rtx_equal_p (operands
[0], high_bit
))
4022 emit_move_insn (operands
[0], operands
[2]);
4024 /* ??? If the destination overlaps both source tf and high_bit, then
4025 assume source tf is dead in its entirety and use the other half
4026 for a scratch register. Otherwise "scratch" is just the proper
4027 destination register. */
4028 scratch
= operands
[move
< 2 ? 1 : 3];
4030 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
4034 emit_move_insn (operands
[0], operands
[2]);
4036 emit_move_insn (operands
[1], scratch
);
4040 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
4044 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
4045 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
4046 lda r3,X(r11) lda r3,X+2(r11)
4047 extwl r1,r3,r1 extql r1,r3,r1
4048 extwh r2,r3,r2 extqh r2,r3,r2
4049 or r1.r2.r1 or r1,r2,r1
4052 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
4053 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
4054 lda r3,X(r11) lda r3,X(r11)
4055 extll r1,r3,r1 extll r1,r3,r1
4056 extlh r2,r3,r2 extlh r2,r3,r2
4057 or r1.r2.r1 addl r1,r2,r1
4059 quad: ldq_u r1,X(r11)
4068 alpha_expand_unaligned_load (tgt
, mem
, size
, ofs
, sign
)
4070 HOST_WIDE_INT size
, ofs
;
4073 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
4074 enum machine_mode mode
;
4076 meml
= gen_reg_rtx (DImode
);
4077 memh
= gen_reg_rtx (DImode
);
4078 addr
= gen_reg_rtx (DImode
);
4079 extl
= gen_reg_rtx (DImode
);
4080 exth
= gen_reg_rtx (DImode
);
4082 mema
= XEXP (mem
, 0);
4083 if (GET_CODE (mema
) == LO_SUM
)
4084 mema
= force_reg (Pmode
, mema
);
4086 /* AND addresses cannot be in any alias set, since they may implicitly
4087 alias surrounding code. Ideally we'd have some alias set that
4088 covered all types except those with alignment 8 or higher. */
4090 tmp
= change_address (mem
, DImode
,
4091 gen_rtx_AND (DImode
,
4092 plus_constant (mema
, ofs
),
4094 set_mem_alias_set (tmp
, 0);
4095 emit_move_insn (meml
, tmp
);
4097 tmp
= change_address (mem
, DImode
,
4098 gen_rtx_AND (DImode
,
4099 plus_constant (mema
, ofs
+ size
- 1),
4101 set_mem_alias_set (tmp
, 0);
4102 emit_move_insn (memh
, tmp
);
4104 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
4106 emit_move_insn (addr
, plus_constant (mema
, -1));
4108 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4109 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
4111 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4112 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
4113 addr
, 1, OPTAB_WIDEN
);
4115 else if (sign
&& size
== 2)
4117 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
4119 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
4120 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4122 /* We must use tgt here for the target. Alpha-vms port fails if we use
4123 addr for the target, because addr is marked as a pointer and combine
4124 knows that pointers are always sign-extended 32 bit values. */
4125 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
4126 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
4127 addr
, 1, OPTAB_WIDEN
);
4131 if (WORDS_BIG_ENDIAN
)
4133 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
4137 emit_insn (gen_extwh_be (extl
, meml
, addr
));
4142 emit_insn (gen_extlh_be (extl
, meml
, addr
));
4147 emit_insn (gen_extqh_be (extl
, meml
, addr
));
4154 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
4158 emit_move_insn (addr
, plus_constant (mema
, ofs
));
4159 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
4163 emit_insn (gen_extwh_le (exth
, memh
, addr
));
4168 emit_insn (gen_extlh_le (exth
, memh
, addr
));
4173 emit_insn (gen_extqh_le (exth
, memh
, addr
));
4182 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
4183 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
4188 emit_move_insn (tgt
, gen_lowpart(GET_MODE (tgt
), addr
));
4191 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4194 alpha_expand_unaligned_store (dst
, src
, size
, ofs
)
4196 HOST_WIDE_INT size
, ofs
;
4198 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
4200 dstl
= gen_reg_rtx (DImode
);
4201 dsth
= gen_reg_rtx (DImode
);
4202 insl
= gen_reg_rtx (DImode
);
4203 insh
= gen_reg_rtx (DImode
);
4205 dsta
= XEXP (dst
, 0);
4206 if (GET_CODE (dsta
) == LO_SUM
)
4207 dsta
= force_reg (Pmode
, dsta
);
4209 /* AND addresses cannot be in any alias set, since they may implicitly
4210 alias surrounding code. Ideally we'd have some alias set that
4211 covered all types except those with alignment 8 or higher. */
4213 meml
= change_address (dst
, DImode
,
4214 gen_rtx_AND (DImode
,
4215 plus_constant (dsta
, ofs
),
4217 set_mem_alias_set (meml
, 0);
4219 memh
= change_address (dst
, DImode
,
4220 gen_rtx_AND (DImode
,
4221 plus_constant (dsta
, ofs
+ size
- 1),
4223 set_mem_alias_set (memh
, 0);
4225 emit_move_insn (dsth
, memh
);
4226 emit_move_insn (dstl
, meml
);
4227 if (WORDS_BIG_ENDIAN
)
4229 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
4231 if (src
!= const0_rtx
)
4236 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
4239 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
4242 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
4245 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
4246 GEN_INT (size
*8), addr
));
4252 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
4256 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4257 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
4261 emit_insn (gen_mskxl_be (dsth
, dsth
, constm1_rtx
, addr
));
4265 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
4269 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
4271 if (src
!= const0_rtx
)
4273 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
4274 GEN_INT (size
*8), addr
));
4279 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
4282 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
4285 emit_insn (gen_insql_le (insl
, src
, addr
));
4290 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
4295 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
4299 rtx msk
= immed_double_const (0xffffffff, 0, DImode
);
4300 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
4304 emit_insn (gen_mskxl_le (dstl
, dstl
, constm1_rtx
, addr
));
4309 if (src
!= const0_rtx
)
4311 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
4312 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
4315 if (WORDS_BIG_ENDIAN
)
4317 emit_move_insn (meml
, dstl
);
4318 emit_move_insn (memh
, dsth
);
4322 /* Must store high before low for degenerate case of aligned. */
4323 emit_move_insn (memh
, dsth
);
4324 emit_move_insn (meml
, dstl
);
4328 /* The block move code tries to maximize speed by separating loads and
4329 stores at the expense of register pressure: we load all of the data
4330 before we store it back out. There are two secondary effects worth
4331 mentioning, that this speeds copying to/from aligned and unaligned
4332 buffers, and that it makes the code significantly easier to write. */
4334 #define MAX_MOVE_WORDS 8
4336 /* Load an integral number of consecutive unaligned quadwords. */
4339 alpha_expand_unaligned_load_words (out_regs
, smem
, words
, ofs
)
4342 HOST_WIDE_INT words
, ofs
;
4344 rtx
const im8
= GEN_INT (-8);
4345 rtx
const i64
= GEN_INT (64);
4346 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
4347 rtx sreg
, areg
, tmp
, smema
;
4350 smema
= XEXP (smem
, 0);
4351 if (GET_CODE (smema
) == LO_SUM
)
4352 smema
= force_reg (Pmode
, smema
);
4354 /* Generate all the tmp registers we need. */
4355 for (i
= 0; i
< words
; ++i
)
4357 data_regs
[i
] = out_regs
[i
];
4358 ext_tmps
[i
] = gen_reg_rtx (DImode
);
4360 data_regs
[words
] = gen_reg_rtx (DImode
);
4363 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
4365 /* Load up all of the source data. */
4366 for (i
= 0; i
< words
; ++i
)
4368 tmp
= change_address (smem
, DImode
,
4369 gen_rtx_AND (DImode
,
4370 plus_constant (smema
, 8*i
),
4372 set_mem_alias_set (tmp
, 0);
4373 emit_move_insn (data_regs
[i
], tmp
);
4376 tmp
= change_address (smem
, DImode
,
4377 gen_rtx_AND (DImode
,
4378 plus_constant (smema
, 8*words
- 1),
4380 set_mem_alias_set (tmp
, 0);
4381 emit_move_insn (data_regs
[words
], tmp
);
4383 /* Extract the half-word fragments. Unfortunately DEC decided to make
4384 extxh with offset zero a noop instead of zeroing the register, so
4385 we must take care of that edge condition ourselves with cmov. */
4387 sreg
= copy_addr_to_reg (smema
);
4388 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
4390 if (WORDS_BIG_ENDIAN
)
4391 emit_move_insn (sreg
, plus_constant (sreg
, 7));
4392 for (i
= 0; i
< words
; ++i
)
4394 if (WORDS_BIG_ENDIAN
)
4396 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
4397 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
4401 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
4402 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
4404 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
4405 gen_rtx_IF_THEN_ELSE (DImode
,
4406 gen_rtx_EQ (DImode
, areg
,
4408 const0_rtx
, ext_tmps
[i
])));
4411 /* Merge the half-words into whole words. */
4412 for (i
= 0; i
< words
; ++i
)
4414 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4415 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
4419 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4420 may be NULL to store zeros. */
4423 alpha_expand_unaligned_store_words (data_regs
, dmem
, words
, ofs
)
4426 HOST_WIDE_INT words
, ofs
;
4428 rtx
const im8
= GEN_INT (-8);
4429 rtx
const i64
= GEN_INT (64);
4430 rtx ins_tmps
[MAX_MOVE_WORDS
];
4431 rtx st_tmp_1
, st_tmp_2
, dreg
;
4432 rtx st_addr_1
, st_addr_2
, dmema
;
4435 dmema
= XEXP (dmem
, 0);
4436 if (GET_CODE (dmema
) == LO_SUM
)
4437 dmema
= force_reg (Pmode
, dmema
);
4439 /* Generate all the tmp registers we need. */
4440 if (data_regs
!= NULL
)
4441 for (i
= 0; i
< words
; ++i
)
4442 ins_tmps
[i
] = gen_reg_rtx(DImode
);
4443 st_tmp_1
= gen_reg_rtx(DImode
);
4444 st_tmp_2
= gen_reg_rtx(DImode
);
4447 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
4449 st_addr_2
= change_address (dmem
, DImode
,
4450 gen_rtx_AND (DImode
,
4451 plus_constant (dmema
, words
*8 - 1),
4453 set_mem_alias_set (st_addr_2
, 0);
4455 st_addr_1
= change_address (dmem
, DImode
,
4456 gen_rtx_AND (DImode
, dmema
, im8
));
4457 set_mem_alias_set (st_addr_1
, 0);
4459 /* Load up the destination end bits. */
4460 emit_move_insn (st_tmp_2
, st_addr_2
);
4461 emit_move_insn (st_tmp_1
, st_addr_1
);
4463 /* Shift the input data into place. */
4464 dreg
= copy_addr_to_reg (dmema
);
4465 if (WORDS_BIG_ENDIAN
)
4466 emit_move_insn (dreg
, plus_constant (dreg
, 7));
4467 if (data_regs
!= NULL
)
4469 for (i
= words
-1; i
>= 0; --i
)
4471 if (WORDS_BIG_ENDIAN
)
4473 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
4474 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
4478 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
4479 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
4482 for (i
= words
-1; i
> 0; --i
)
4484 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4485 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
4490 /* Split and merge the ends with the destination data. */
4491 if (WORDS_BIG_ENDIAN
)
4493 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, constm1_rtx
, dreg
));
4494 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
4498 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
4499 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, constm1_rtx
, dreg
));
4502 if (data_regs
!= NULL
)
4504 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
4505 st_tmp_2
, 1, OPTAB_WIDEN
);
4506 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
4507 st_tmp_1
, 1, OPTAB_WIDEN
);
4511 if (WORDS_BIG_ENDIAN
)
4512 emit_move_insn (st_addr_1
, st_tmp_1
);
4514 emit_move_insn (st_addr_2
, st_tmp_2
);
4515 for (i
= words
-1; i
> 0; --i
)
4517 rtx tmp
= change_address (dmem
, DImode
,
4518 gen_rtx_AND (DImode
,
4519 plus_constant(dmema
,
4520 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
4522 set_mem_alias_set (tmp
, 0);
4523 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
4525 if (WORDS_BIG_ENDIAN
)
4526 emit_move_insn (st_addr_2
, st_tmp_2
);
4528 emit_move_insn (st_addr_1
, st_tmp_1
);
4532 /* Expand string/block move operations.
4534 operands[0] is the pointer to the destination.
4535 operands[1] is the pointer to the source.
4536 operands[2] is the number of bytes to move.
4537 operands[3] is the alignment. */
4540 alpha_expand_block_move (operands
)
4543 rtx bytes_rtx
= operands
[2];
4544 rtx align_rtx
= operands
[3];
4545 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4546 HOST_WIDE_INT bytes
= orig_bytes
;
4547 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4548 HOST_WIDE_INT dst_align
= src_align
;
4549 rtx orig_src
= operands
[1];
4550 rtx orig_dst
= operands
[0];
4551 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
4553 unsigned int i
, words
, ofs
, nregs
= 0;
4555 if (orig_bytes
<= 0)
4557 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4560 /* Look for additional alignment information from recorded register info. */
4562 tmp
= XEXP (orig_src
, 0);
4563 if (GET_CODE (tmp
) == REG
)
4564 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4565 else if (GET_CODE (tmp
) == PLUS
4566 && GET_CODE (XEXP (tmp
, 0)) == REG
4567 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4569 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4570 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4574 if (a
>= 64 && c
% 8 == 0)
4576 else if (a
>= 32 && c
% 4 == 0)
4578 else if (a
>= 16 && c
% 2 == 0)
4583 tmp
= XEXP (orig_dst
, 0);
4584 if (GET_CODE (tmp
) == REG
)
4585 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4586 else if (GET_CODE (tmp
) == PLUS
4587 && GET_CODE (XEXP (tmp
, 0)) == REG
4588 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4590 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4591 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4595 if (a
>= 64 && c
% 8 == 0)
4597 else if (a
>= 32 && c
% 4 == 0)
4599 else if (a
>= 16 && c
% 2 == 0)
4604 /* Load the entire block into registers. */
4605 if (GET_CODE (XEXP (orig_src
, 0)) == ADDRESSOF
)
4607 enum machine_mode mode
;
4609 tmp
= XEXP (XEXP (orig_src
, 0), 0);
4611 /* Don't use the existing register if we're reading more than
4612 is held in the register. Nor if there is not a mode that
4613 handles the exact size. */
4614 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4616 && GET_MODE_SIZE (GET_MODE (tmp
)) >= bytes
)
4620 data_regs
[nregs
] = gen_lowpart (DImode
, tmp
);
4621 data_regs
[nregs
+ 1] = gen_highpart (DImode
, tmp
);
4625 data_regs
[nregs
++] = gen_lowpart (mode
, tmp
);
4630 /* No appropriate mode; fall back on memory. */
4631 orig_src
= replace_equiv_address (orig_src
,
4632 copy_addr_to_reg (XEXP (orig_src
, 0)));
4633 src_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4637 if (src_align
>= 64 && bytes
>= 8)
4641 for (i
= 0; i
< words
; ++i
)
4642 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4644 for (i
= 0; i
< words
; ++i
)
4645 emit_move_insn (data_regs
[nregs
+ i
],
4646 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
4653 if (src_align
>= 32 && bytes
>= 4)
4657 for (i
= 0; i
< words
; ++i
)
4658 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
4660 for (i
= 0; i
< words
; ++i
)
4661 emit_move_insn (data_regs
[nregs
+ i
],
4662 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
4673 for (i
= 0; i
< words
+1; ++i
)
4674 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4676 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
4684 if (! TARGET_BWX
&& bytes
>= 4)
4686 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
4687 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
4694 if (src_align
>= 16)
4697 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4698 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
4701 } while (bytes
>= 2);
4703 else if (! TARGET_BWX
)
4705 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4706 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
4714 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
4715 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
4722 if (nregs
> ARRAY_SIZE (data_regs
))
4725 /* Now save it back out again. */
4729 if (GET_CODE (XEXP (orig_dst
, 0)) == ADDRESSOF
)
4731 enum machine_mode mode
;
4732 tmp
= XEXP (XEXP (orig_dst
, 0), 0);
4734 mode
= mode_for_size (orig_bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4735 if (GET_MODE (tmp
) == mode
)
4739 emit_move_insn (tmp
, data_regs
[0]);
4744 else if (nregs
== 2 && mode
== TImode
)
4746 /* Undo the subregging done above when copying between
4747 two TImode registers. */
4748 if (GET_CODE (data_regs
[0]) == SUBREG
4749 && GET_MODE (SUBREG_REG (data_regs
[0])) == TImode
)
4750 emit_move_insn (tmp
, SUBREG_REG (data_regs
[0]));
4756 emit_move_insn (gen_lowpart (DImode
, tmp
), data_regs
[0]);
4757 emit_move_insn (gen_highpart (DImode
, tmp
), data_regs
[1]);
4761 emit_no_conflict_block (seq
, tmp
, data_regs
[0],
4762 data_regs
[1], NULL_RTX
);
4770 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4771 /* ??? Optimize mode < dst_mode with strict_low_part. */
4773 /* No appropriate mode; fall back on memory. We can speed things
4774 up by recognizing extra alignment information. */
4775 orig_dst
= replace_equiv_address (orig_dst
,
4776 copy_addr_to_reg (XEXP (orig_dst
, 0)));
4777 dst_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4780 /* Write out the data in whatever chunks reading the source allowed. */
4781 if (dst_align
>= 64)
4783 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4785 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
4792 if (dst_align
>= 32)
4794 /* If the source has remaining DImode regs, write them out in
4796 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4798 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
4799 NULL_RTX
, 1, OPTAB_WIDEN
);
4801 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4802 gen_lowpart (SImode
, data_regs
[i
]));
4803 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
4804 gen_lowpart (SImode
, tmp
));
4809 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4811 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4818 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4820 /* Write out a remaining block of words using unaligned methods. */
4822 for (words
= 1; i
+ words
< nregs
; words
++)
4823 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4827 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4829 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4836 /* Due to the above, this won't be aligned. */
4837 /* ??? If we have more than one of these, consider constructing full
4838 words in registers and using alpha_expand_unaligned_store_words. */
4839 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4841 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4846 if (dst_align
>= 16)
4847 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4849 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4854 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4856 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4861 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
4863 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4877 alpha_expand_block_clear (operands
)
4880 rtx bytes_rtx
= operands
[1];
4881 rtx align_rtx
= operands
[2];
4882 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4883 HOST_WIDE_INT bytes
= orig_bytes
;
4884 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4885 HOST_WIDE_INT alignofs
= 0;
4886 rtx orig_dst
= operands
[0];
4888 int i
, words
, ofs
= 0;
4890 if (orig_bytes
<= 0)
4892 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4895 /* Look for stricter alignment. */
4896 tmp
= XEXP (orig_dst
, 0);
4897 if (GET_CODE (tmp
) == REG
)
4898 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4899 else if (GET_CODE (tmp
) == PLUS
4900 && GET_CODE (XEXP (tmp
, 0)) == REG
4901 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4903 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4904 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4909 align
= a
, alignofs
= 8 - c
% 8;
4911 align
= a
, alignofs
= 4 - c
% 4;
4913 align
= a
, alignofs
= 2 - c
% 2;
4916 else if (GET_CODE (tmp
) == ADDRESSOF
)
4918 enum machine_mode mode
;
4920 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4921 if (GET_MODE (XEXP (tmp
, 0)) == mode
)
4923 emit_move_insn (XEXP (tmp
, 0), const0_rtx
);
4927 /* No appropriate mode; fall back on memory. */
4928 orig_dst
= replace_equiv_address (orig_dst
, copy_addr_to_reg (tmp
));
4929 align
= GET_MODE_BITSIZE (GET_MODE (XEXP (tmp
, 0)));
4932 /* Handle an unaligned prefix first. */
4936 #if HOST_BITS_PER_WIDE_INT >= 64
4937 /* Given that alignofs is bounded by align, the only time BWX could
4938 generate three stores is for a 7 byte fill. Prefer two individual
4939 stores over a load/mask/store sequence. */
4940 if ((!TARGET_BWX
|| alignofs
== 7)
4942 && !(alignofs
== 4 && bytes
>= 4))
4944 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
4945 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
4949 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
4950 set_mem_alias_set (mem
, 0);
4952 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
4953 if (bytes
< alignofs
)
4955 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
4966 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
4967 NULL_RTX
, 1, OPTAB_WIDEN
);
4969 emit_move_insn (mem
, tmp
);
4973 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
4975 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4980 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
4982 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
4987 if (alignofs
== 4 && bytes
>= 4)
4989 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4995 /* If we've not used the extra lead alignment information by now,
4996 we won't be able to. Downgrade align to match what's left over. */
4999 alignofs
= alignofs
& -alignofs
;
5000 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
5004 /* Handle a block of contiguous long-words. */
5006 if (align
>= 64 && bytes
>= 8)
5010 for (i
= 0; i
< words
; ++i
)
5011 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
5018 /* If the block is large and appropriately aligned, emit a single
5019 store followed by a sequence of stq_u insns. */
5021 if (align
>= 32 && bytes
> 16)
5025 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
5029 orig_dsta
= XEXP (orig_dst
, 0);
5030 if (GET_CODE (orig_dsta
) == LO_SUM
)
5031 orig_dsta
= force_reg (Pmode
, orig_dsta
);
5034 for (i
= 0; i
< words
; ++i
)
5037 = change_address (orig_dst
, DImode
,
5038 gen_rtx_AND (DImode
,
5039 plus_constant (orig_dsta
, ofs
+ i
*8),
5041 set_mem_alias_set (mem
, 0);
5042 emit_move_insn (mem
, const0_rtx
);
5045 /* Depending on the alignment, the first stq_u may have overlapped
5046 with the initial stl, which means that the last stq_u didn't
5047 write as much as it would appear. Leave those questionable bytes
5049 bytes
-= words
* 8 - 4;
5050 ofs
+= words
* 8 - 4;
5053 /* Handle a smaller block of aligned words. */
5055 if ((align
>= 64 && bytes
== 4)
5056 || (align
== 32 && bytes
>= 4))
5060 for (i
= 0; i
< words
; ++i
)
5061 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
5068 /* An unaligned block uses stq_u stores for as many as possible. */
5074 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
5080 /* Next clean up any trailing pieces. */
5082 #if HOST_BITS_PER_WIDE_INT >= 64
5083 /* Count the number of bits in BYTES for which aligned stores could
5086 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
5090 /* If we have appropriate alignment (and it wouldn't take too many
5091 instructions otherwise), mask out the bytes we need. */
5092 if (TARGET_BWX
? words
> 2 : bytes
> 0)
5099 mem
= adjust_address (orig_dst
, DImode
, ofs
);
5100 set_mem_alias_set (mem
, 0);
5102 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5104 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
5105 NULL_RTX
, 1, OPTAB_WIDEN
);
5107 emit_move_insn (mem
, tmp
);
5110 else if (align
>= 32 && bytes
< 4)
5115 mem
= adjust_address (orig_dst
, SImode
, ofs
);
5116 set_mem_alias_set (mem
, 0);
5118 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
5120 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
5121 NULL_RTX
, 1, OPTAB_WIDEN
);
5123 emit_move_insn (mem
, tmp
);
5129 if (!TARGET_BWX
&& bytes
>= 4)
5131 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
5141 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
5145 } while (bytes
>= 2);
5147 else if (! TARGET_BWX
)
5149 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
5157 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
5165 /* Returns a mask so that zap(x, value) == x & mask. */
5168 alpha_expand_zap_mask (value
)
5169 HOST_WIDE_INT value
;
5174 if (HOST_BITS_PER_WIDE_INT
>= 64)
5176 HOST_WIDE_INT mask
= 0;
5178 for (i
= 7; i
>= 0; --i
)
5181 if (!((value
>> i
) & 1))
5185 result
= gen_int_mode (mask
, DImode
);
5187 else if (HOST_BITS_PER_WIDE_INT
== 32)
5189 HOST_WIDE_INT mask_lo
= 0, mask_hi
= 0;
5191 for (i
= 7; i
>= 4; --i
)
5194 if (!((value
>> i
) & 1))
5198 for (i
= 3; i
>= 0; --i
)
5201 if (!((value
>> i
) & 1))
5205 result
= immed_double_const (mask_lo
, mask_hi
, DImode
);
5214 alpha_expand_builtin_vector_binop (gen
, mode
, op0
, op1
, op2
)
5215 rtx (*gen
) PARAMS ((rtx
, rtx
, rtx
));
5216 enum machine_mode mode
;
5219 op0
= gen_lowpart (mode
, op0
);
5221 if (op1
== const0_rtx
)
5222 op1
= CONST0_RTX (mode
);
5224 op1
= gen_lowpart (mode
, op1
);
5226 if (op2
== const0_rtx
)
5227 op2
= CONST0_RTX (mode
);
5229 op2
= gen_lowpart (mode
, op2
);
5231 emit_insn ((*gen
) (op0
, op1
, op2
));
5234 /* Adjust the cost of a scheduling dependency. Return the new cost of
5235 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5238 alpha_adjust_cost (insn
, link
, dep_insn
, cost
)
5244 enum attr_type insn_type
, dep_insn_type
;
5246 /* If the dependence is an anti-dependence, there is no cost. For an
5247 output dependence, there is sometimes a cost, but it doesn't seem
5248 worth handling those few cases. */
5249 if (REG_NOTE_KIND (link
) != 0)
5252 /* If we can't recognize the insns, we can't really do anything. */
5253 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
5256 insn_type
= get_attr_type (insn
);
5257 dep_insn_type
= get_attr_type (dep_insn
);
5259 /* Bring in the user-defined memory latency. */
5260 if (dep_insn_type
== TYPE_ILD
5261 || dep_insn_type
== TYPE_FLD
5262 || dep_insn_type
== TYPE_LDSYM
)
5263 cost
+= alpha_memory_latency
-1;
5265 /* Everything else handled in DFA bypasses now. */
5270 /* The number of instructions that can be issued per cycle. */
5275 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
5279 alpha_use_dfa_pipeline_interface ()
5284 /* How many alternative schedules to try. This should be as wide as the
5285 scheduling freedom in the DFA, but no wider. Making this value too
5286 large results extra work for the scheduler.
5288 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5289 alternative schedules. For EV5, we can choose between E0/E1 and
5290 FA/FM. For EV6, an arithmatic insn can be issued to U0/U1/L0/L1. */
5293 alpha_multipass_dfa_lookahead ()
5295 return (alpha_cpu
== PROCESSOR_EV6
? 4 : 2);
5298 /* Machine-specific function data. */
5300 struct machine_function
GTY(())
5303 /* List of call information words for calls from this function. */
5304 struct rtx_def
*first_ciw
;
5305 struct rtx_def
*last_ciw
;
5308 /* List of deferred case vectors. */
5309 struct rtx_def
*addr_list
;
5312 const char *some_ld_name
;
5315 /* How to allocate a 'struct machine_function'. */
5317 static struct machine_function
*
5318 alpha_init_machine_status ()
5320 return ((struct machine_function
*)
5321 ggc_alloc_cleared (sizeof (struct machine_function
)));
5324 /* Functions to save and restore alpha_return_addr_rtx. */
5326 /* Start the ball rolling with RETURN_ADDR_RTX. */
5329 alpha_return_addr (count
, frame
)
5331 rtx frame ATTRIBUTE_UNUSED
;
5336 return get_hard_reg_initial_val (Pmode
, REG_RA
);
5339 /* Return or create a pseudo containing the gp value for the current
5340 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5343 alpha_gp_save_rtx ()
5345 rtx r
= get_hard_reg_initial_val (DImode
, 29);
5346 if (GET_CODE (r
) != MEM
)
5347 r
= gen_mem_addressof (r
, NULL_TREE
);
5352 alpha_ra_ever_killed ()
5356 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
5357 return regs_ever_live
[REG_RA
];
5359 push_topmost_sequence ();
5361 pop_topmost_sequence ();
5363 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
5367 /* Return the trap mode suffix applicable to the current
5368 instruction, or NULL. */
5371 get_trap_mode_suffix ()
5373 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
5377 case TRAP_SUFFIX_NONE
:
5380 case TRAP_SUFFIX_SU
:
5381 if (alpha_fptm
>= ALPHA_FPTM_SU
)
5385 case TRAP_SUFFIX_SUI
:
5386 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
5390 case TRAP_SUFFIX_V_SV
:
5398 case ALPHA_FPTM_SUI
:
5403 case TRAP_SUFFIX_V_SV_SVI
:
5412 case ALPHA_FPTM_SUI
:
5417 case TRAP_SUFFIX_U_SU_SUI
:
5426 case ALPHA_FPTM_SUI
:
5434 /* Return the rounding mode suffix applicable to the current
5435 instruction, or NULL. */
5438 get_round_mode_suffix ()
5440 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5444 case ROUND_SUFFIX_NONE
:
5446 case ROUND_SUFFIX_NORMAL
:
5449 case ALPHA_FPRM_NORM
:
5451 case ALPHA_FPRM_MINF
:
5453 case ALPHA_FPRM_CHOP
:
5455 case ALPHA_FPRM_DYN
:
5460 case ROUND_SUFFIX_C
:
5466 /* Locate some local-dynamic symbol still in use by this function
5467 so that we can print its name in some movdi_er_tlsldm pattern. */
5470 get_some_local_dynamic_name ()
5474 if (cfun
->machine
->some_ld_name
)
5475 return cfun
->machine
->some_ld_name
;
5477 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5479 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5480 return cfun
->machine
->some_ld_name
;
5486 get_some_local_dynamic_name_1 (px
, data
)
5488 void *data ATTRIBUTE_UNUSED
;
5492 if (GET_CODE (x
) == SYMBOL_REF
)
5494 const char *str
= XSTR (x
, 0);
5495 if (str
[0] == '@' && str
[1] == 'D')
5497 cfun
->machine
->some_ld_name
= str
;
5505 /* Print an operand. Recognize special options, documented below. */
5508 print_operand (file
, x
, code
)
5518 /* Print the assembler name of the current function. */
5519 assemble_name (file
, alpha_fnname
);
5523 assemble_name (file
, get_some_local_dynamic_name ());
5528 const char *trap
= get_trap_mode_suffix ();
5529 const char *round
= get_round_mode_suffix ();
5532 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5533 (trap
? trap
: ""), (round
? round
: ""));
5538 /* Generates single precision instruction suffix. */
5539 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5543 /* Generates double precision instruction suffix. */
5544 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5548 if (alpha_this_literal_sequence_number
== 0)
5549 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5550 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5554 if (alpha_this_gpdisp_sequence_number
== 0)
5555 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5556 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5560 if (GET_CODE (x
) == HIGH
)
5561 output_addr_const (file
, XEXP (x
, 0));
5563 output_operand_lossage ("invalid %%H value");
5570 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD_CALL
)
5572 x
= XVECEXP (x
, 0, 0);
5573 lituse
= "lituse_tlsgd";
5575 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM_CALL
)
5577 x
= XVECEXP (x
, 0, 0);
5578 lituse
= "lituse_tlsldm";
5580 else if (GET_CODE (x
) == CONST_INT
)
5581 lituse
= "lituse_jsr";
5584 output_operand_lossage ("invalid %%J value");
5588 if (x
!= const0_rtx
)
5589 fprintf (file
, "\t\t!%s!%d", lituse
, (int) INTVAL (x
));
5594 /* If this operand is the constant zero, write it as "$31". */
5595 if (GET_CODE (x
) == REG
)
5596 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5597 else if (x
== CONST0_RTX (GET_MODE (x
)))
5598 fprintf (file
, "$31");
5600 output_operand_lossage ("invalid %%r value");
5604 /* Similar, but for floating-point. */
5605 if (GET_CODE (x
) == REG
)
5606 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5607 else if (x
== CONST0_RTX (GET_MODE (x
)))
5608 fprintf (file
, "$f31");
5610 output_operand_lossage ("invalid %%R value");
5614 /* Write the 1's complement of a constant. */
5615 if (GET_CODE (x
) != CONST_INT
)
5616 output_operand_lossage ("invalid %%N value");
5618 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5622 /* Write 1 << C, for a constant C. */
5623 if (GET_CODE (x
) != CONST_INT
)
5624 output_operand_lossage ("invalid %%P value");
5626 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5630 /* Write the high-order 16 bits of a constant, sign-extended. */
5631 if (GET_CODE (x
) != CONST_INT
)
5632 output_operand_lossage ("invalid %%h value");
5634 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5638 /* Write the low-order 16 bits of a constant, sign-extended. */
5639 if (GET_CODE (x
) != CONST_INT
)
5640 output_operand_lossage ("invalid %%L value");
5642 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5643 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5647 /* Write mask for ZAP insn. */
5648 if (GET_CODE (x
) == CONST_DOUBLE
)
5650 HOST_WIDE_INT mask
= 0;
5651 HOST_WIDE_INT value
;
5653 value
= CONST_DOUBLE_LOW (x
);
5654 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5659 value
= CONST_DOUBLE_HIGH (x
);
5660 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5663 mask
|= (1 << (i
+ sizeof (int)));
5665 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5668 else if (GET_CODE (x
) == CONST_INT
)
5670 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5672 for (i
= 0; i
< 8; i
++, value
>>= 8)
5676 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5679 output_operand_lossage ("invalid %%m value");
5683 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5684 if (GET_CODE (x
) != CONST_INT
5685 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5686 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5687 output_operand_lossage ("invalid %%M value");
5689 fprintf (file
, "%s",
5690 (INTVAL (x
) == 8 ? "b"
5691 : INTVAL (x
) == 16 ? "w"
5692 : INTVAL (x
) == 32 ? "l"
5697 /* Similar, except do it from the mask. */
5698 if (GET_CODE (x
) == CONST_INT
)
5700 HOST_WIDE_INT value
= INTVAL (x
);
5707 if (value
== 0xffff)
5712 if (value
== 0xffffffff)
5723 else if (HOST_BITS_PER_WIDE_INT
== 32
5724 && GET_CODE (x
) == CONST_DOUBLE
5725 && CONST_DOUBLE_LOW (x
) == 0xffffffff
5726 && CONST_DOUBLE_HIGH (x
) == 0)
5731 output_operand_lossage ("invalid %%U value");
5735 /* Write the constant value divided by 8 for little-endian mode or
5736 (56 - value) / 8 for big-endian mode. */
5738 if (GET_CODE (x
) != CONST_INT
5739 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5742 || (INTVAL (x
) & 7) != 0)
5743 output_operand_lossage ("invalid %%s value");
5745 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5747 ? (56 - INTVAL (x
)) / 8
5752 /* Same, except compute (64 - c) / 8 */
5754 if (GET_CODE (x
) != CONST_INT
5755 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5756 && (INTVAL (x
) & 7) != 8)
5757 output_operand_lossage ("invalid %%s value");
5759 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5764 /* On Unicos/Mk systems: use a DEX expression if the symbol
5765 clashes with a register name. */
5766 int dex
= unicosmk_need_dex (x
);
5768 fprintf (file
, "DEX(%d)", dex
);
5770 output_addr_const (file
, x
);
5774 case 'C': case 'D': case 'c': case 'd':
5775 /* Write out comparison name. */
5777 enum rtx_code c
= GET_CODE (x
);
5779 if (GET_RTX_CLASS (c
) != '<')
5780 output_operand_lossage ("invalid %%C value");
5782 else if (code
== 'D')
5783 c
= reverse_condition (c
);
5784 else if (code
== 'c')
5785 c
= swap_condition (c
);
5786 else if (code
== 'd')
5787 c
= swap_condition (reverse_condition (c
));
5790 fprintf (file
, "ule");
5792 fprintf (file
, "ult");
5793 else if (c
== UNORDERED
)
5794 fprintf (file
, "un");
5796 fprintf (file
, "%s", GET_RTX_NAME (c
));
5801 /* Write the divide or modulus operator. */
5802 switch (GET_CODE (x
))
5805 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5808 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5811 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5814 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5817 output_operand_lossage ("invalid %%E value");
5823 /* Write "_u" for unaligned access. */
5824 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
5825 fprintf (file
, "_u");
5829 if (GET_CODE (x
) == REG
)
5830 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5831 else if (GET_CODE (x
) == MEM
)
5832 output_address (XEXP (x
, 0));
5833 else if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == UNSPEC
)
5835 switch (XINT (XEXP (x
, 0), 1))
5839 output_addr_const (file
, XVECEXP (XEXP (x
, 0), 0, 0));
5842 output_operand_lossage ("unknown relocation unspec");
5847 output_addr_const (file
, x
);
5851 output_operand_lossage ("invalid %%xn code");
5856 print_operand_address (file
, addr
)
5861 HOST_WIDE_INT offset
= 0;
5863 if (GET_CODE (addr
) == AND
)
5864 addr
= XEXP (addr
, 0);
5866 if (GET_CODE (addr
) == PLUS
5867 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5869 offset
= INTVAL (XEXP (addr
, 1));
5870 addr
= XEXP (addr
, 0);
5873 if (GET_CODE (addr
) == LO_SUM
)
5875 const char *reloc16
, *reloclo
;
5876 rtx op1
= XEXP (addr
, 1);
5878 if (GET_CODE (op1
) == CONST
&& GET_CODE (XEXP (op1
, 0)) == UNSPEC
)
5880 op1
= XEXP (op1
, 0);
5881 switch (XINT (op1
, 1))
5885 reloclo
= (alpha_tls_size
== 16 ? "dtprel" : "dtprello");
5889 reloclo
= (alpha_tls_size
== 16 ? "tprel" : "tprello");
5892 output_operand_lossage ("unknown relocation unspec");
5896 output_addr_const (file
, XVECEXP (op1
, 0, 0));
5901 reloclo
= "gprellow";
5902 output_addr_const (file
, op1
);
5908 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
5911 addr
= XEXP (addr
, 0);
5912 if (GET_CODE (addr
) == REG
)
5913 basereg
= REGNO (addr
);
5914 else if (GET_CODE (addr
) == SUBREG
5915 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5916 basereg
= subreg_regno (addr
);
5920 fprintf (file
, "($%d)\t\t!%s", basereg
,
5921 (basereg
== 29 ? reloc16
: reloclo
));
5925 if (GET_CODE (addr
) == REG
)
5926 basereg
= REGNO (addr
);
5927 else if (GET_CODE (addr
) == SUBREG
5928 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5929 basereg
= subreg_regno (addr
);
5930 else if (GET_CODE (addr
) == CONST_INT
)
5931 offset
= INTVAL (addr
);
5935 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
5936 fprintf (file
, "($%d)", basereg
);
5939 /* Emit RTL insns to initialize the variable parts of a trampoline at
5940 TRAMP. FNADDR is an RTX for the address of the function's pure
5941 code. CXT is an RTX for the static chain value for the function.
5943 The three offset parameters are for the individual template's
5944 layout. A JMPOFS < 0 indicates that the trampoline does not
5945 contain instructions at all.
5947 We assume here that a function will be called many more times than
5948 its address is taken (e.g., it might be passed to qsort), so we
5949 take the trouble to initialize the "hint" field in the JMP insn.
5950 Note that the hint field is PC (new) + 4 * bits 13:0. */
5953 alpha_initialize_trampoline (tramp
, fnaddr
, cxt
, fnofs
, cxtofs
, jmpofs
)
5954 rtx tramp
, fnaddr
, cxt
;
5955 int fnofs
, cxtofs
, jmpofs
;
5957 rtx temp
, temp1
, addr
;
5958 /* VMS really uses DImode pointers in memory at this point. */
5959 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
5961 #ifdef POINTERS_EXTEND_UNSIGNED
5962 fnaddr
= convert_memory_address (mode
, fnaddr
);
5963 cxt
= convert_memory_address (mode
, cxt
);
5966 /* Store function address and CXT. */
5967 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
5968 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
5969 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
5970 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
5972 /* This has been disabled since the hint only has a 32k range, and in
5973 no existing OS is the stack within 32k of the text segment. */
5974 if (0 && jmpofs
>= 0)
5976 /* Compute hint value. */
5977 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
5978 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
5980 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
5981 build_int_2 (2, 0), NULL_RTX
, 1);
5982 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
5983 GEN_INT (0x3fff), 0);
5985 /* Merge in the hint. */
5986 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
5987 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
5988 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
5989 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
5991 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
5994 #ifdef TRANSFER_FROM_TRAMPOLINE
5995 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
5996 0, VOIDmode
, 1, addr
, Pmode
);
6000 emit_insn (gen_imb ());
6003 /* Determine where to put an argument to a function.
6004 Value is zero to push the argument on the stack,
6005 or a hard register in which to store the argument.
6007 MODE is the argument's machine mode.
6008 TYPE is the data type of the argument (as a tree).
6009 This is null for libcalls where that information may
6011 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6012 the preceding args and about the function being called.
6013 NAMED is nonzero if this argument is a named parameter
6014 (otherwise it is an extra parameter matching an ellipsis).
6016 On Alpha the first 6 words of args are normally in registers
6017 and the rest are pushed. */
6020 function_arg (cum
, mode
, type
, named
)
6021 CUMULATIVE_ARGS cum
;
6022 enum machine_mode mode
;
6024 int named ATTRIBUTE_UNUSED
;
6029 /* Set up defaults for FP operands passed in FP registers, and
6030 integral operands passed in integer registers. */
6032 && (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
6033 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
6038 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
6039 the three platforms, so we can't avoid conditional compilation. */
6040 #if TARGET_ABI_OPEN_VMS
6042 if (mode
== VOIDmode
)
6043 return alpha_arg_info_reg_val (cum
);
6045 num_args
= cum
.num_args
;
6046 if (num_args
>= 6 || MUST_PASS_IN_STACK (mode
, type
))
6050 #if TARGET_ABI_UNICOSMK
6054 /* If this is the last argument, generate the call info word (CIW). */
6055 /* ??? We don't include the caller's line number in the CIW because
6056 I don't know how to determine it if debug infos are turned off. */
6057 if (mode
== VOIDmode
)
6066 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
6067 if (cum
.reg_args_type
[i
])
6068 lo
|= (1 << (7 - i
));
6070 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
6073 lo
|= cum
.num_reg_words
;
6075 #if HOST_BITS_PER_WIDE_INT == 32
6076 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
6078 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
6079 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
6082 ciw
= immed_double_const (lo
, hi
, DImode
);
6084 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
6085 UNSPEC_UMK_LOAD_CIW
);
6088 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
6089 num_args
= cum
.num_reg_words
;
6090 if (MUST_PASS_IN_STACK (mode
, type
)
6091 || cum
.num_reg_words
+ size
> 6 || cum
.force_stack
)
6093 else if (type
&& TYPE_MODE (type
) == BLKmode
)
6097 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
6098 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
6100 /* The argument fits in two registers. Note that we still need to
6101 reserve a register for empty structures. */
6105 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
6108 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
6109 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
6110 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
6120 /* VOID is passed as a special flag for "last argument". */
6121 if (type
== void_type_node
)
6123 else if (MUST_PASS_IN_STACK (mode
, type
))
6125 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum
, mode
, type
, named
))
6128 #endif /* TARGET_ABI_UNICOSMK */
6129 #endif /* TARGET_ABI_OPEN_VMS */
6131 return gen_rtx_REG (mode
, num_args
+ basereg
);
6135 alpha_build_va_list ()
6137 tree base
, ofs
, record
, type_decl
;
6139 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6140 return ptr_type_node
;
6142 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
6143 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
6144 TREE_CHAIN (record
) = type_decl
;
6145 TYPE_NAME (record
) = type_decl
;
6147 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6149 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
6151 DECL_FIELD_CONTEXT (ofs
) = record
;
6153 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
6155 DECL_FIELD_CONTEXT (base
) = record
;
6156 TREE_CHAIN (base
) = ofs
;
6158 TYPE_FIELDS (record
) = base
;
6159 layout_type (record
);
6165 alpha_va_start (valist
, nextarg
)
6167 rtx nextarg ATTRIBUTE_UNUSED
;
6169 HOST_WIDE_INT offset
;
6170 tree t
, offset_field
, base_field
;
6172 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
6175 if (TARGET_ABI_UNICOSMK
)
6176 std_expand_builtin_va_start (valist
, nextarg
);
6178 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6179 up by 48, storing fp arg registers in the first 48 bytes, and the
6180 integer arg registers in the next 48 bytes. This is only done,
6181 however, if any integer registers need to be stored.
6183 If no integer registers need be stored, then we must subtract 48
6184 in order to account for the integer arg registers which are counted
6185 in argsize above, but which are not actually stored on the stack. */
6188 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
6190 offset
= -6 * UNITS_PER_WORD
;
6192 if (TARGET_ABI_OPEN_VMS
)
6194 nextarg
= plus_constant (nextarg
, offset
);
6195 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
6196 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
6197 make_tree (ptr_type_node
, nextarg
));
6198 TREE_SIDE_EFFECTS (t
) = 1;
6200 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6204 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6205 offset_field
= TREE_CHAIN (base_field
);
6207 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6208 valist
, base_field
);
6209 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6210 valist
, offset_field
);
6212 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
6213 t
= build (PLUS_EXPR
, ptr_type_node
, t
, build_int_2 (offset
, 0));
6214 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
6215 TREE_SIDE_EFFECTS (t
) = 1;
6216 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6218 t
= build_int_2 (NUM_ARGS
* UNITS_PER_WORD
, 0);
6219 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
6220 TREE_SIDE_EFFECTS (t
) = 1;
6221 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6226 alpha_va_arg (valist
, type
)
6230 tree t
, type_size
, rounded_size
;
6231 tree offset_field
, base_field
, addr_tree
, addend
;
6232 tree wide_type
, wide_ofs
;
6235 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
6236 return std_expand_builtin_va_arg (valist
, type
);
6238 if (type
== error_mark_node
6239 || (type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
))) == NULL
6240 || TREE_OVERFLOW (type_size
))
6241 rounded_size
= size_zero_node
;
6243 rounded_size
= fold (build (MULT_EXPR
, sizetype
,
6244 fold (build (TRUNC_DIV_EXPR
, sizetype
,
6245 fold (build (PLUS_EXPR
, sizetype
,
6251 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
6252 offset_field
= TREE_CHAIN (base_field
);
6254 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
6255 valist
, base_field
);
6256 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
6257 valist
, offset_field
);
6259 /* If the type could not be passed in registers, skip the block
6260 reserved for the registers. */
6261 if (MUST_PASS_IN_STACK (TYPE_MODE (type
), type
))
6263 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6264 build (MAX_EXPR
, TREE_TYPE (offset_field
),
6265 offset_field
, build_int_2 (6*8, 0)));
6266 TREE_SIDE_EFFECTS (t
) = 1;
6267 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6270 wide_type
= make_signed_type (64);
6271 wide_ofs
= save_expr (build1 (CONVERT_EXPR
, wide_type
, offset_field
));
6275 if (TYPE_MODE (type
) == TFmode
|| TYPE_MODE (type
) == TCmode
)
6278 rounded_size
= size_int (UNITS_PER_WORD
);
6280 else if (FLOAT_TYPE_P (type
))
6282 tree fpaddend
, cond
;
6284 fpaddend
= fold (build (PLUS_EXPR
, TREE_TYPE (addend
),
6285 addend
, build_int_2 (-6*8, 0)));
6287 cond
= fold (build (LT_EXPR
, integer_type_node
,
6288 wide_ofs
, build_int_2 (6*8, 0)));
6290 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
6294 addr_tree
= build (PLUS_EXPR
, TREE_TYPE (base_field
),
6295 base_field
, addend
);
6297 addr
= expand_expr (addr_tree
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
6298 addr
= copy_to_reg (addr
);
6300 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
6301 build (PLUS_EXPR
, TREE_TYPE (offset_field
),
6302 offset_field
, rounded_size
));
6303 TREE_SIDE_EFFECTS (t
) = 1;
6304 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6308 addr
= force_reg (Pmode
, addr
);
6309 addr
= gen_rtx_MEM (Pmode
, addr
);
6319 ALPHA_BUILTIN_CMPBGE
,
6320 ALPHA_BUILTIN_EXTBL
,
6321 ALPHA_BUILTIN_EXTWL
,
6322 ALPHA_BUILTIN_EXTLL
,
6323 ALPHA_BUILTIN_EXTQL
,
6324 ALPHA_BUILTIN_EXTWH
,
6325 ALPHA_BUILTIN_EXTLH
,
6326 ALPHA_BUILTIN_EXTQH
,
6327 ALPHA_BUILTIN_INSBL
,
6328 ALPHA_BUILTIN_INSWL
,
6329 ALPHA_BUILTIN_INSLL
,
6330 ALPHA_BUILTIN_INSQL
,
6331 ALPHA_BUILTIN_INSWH
,
6332 ALPHA_BUILTIN_INSLH
,
6333 ALPHA_BUILTIN_INSQH
,
6334 ALPHA_BUILTIN_MSKBL
,
6335 ALPHA_BUILTIN_MSKWL
,
6336 ALPHA_BUILTIN_MSKLL
,
6337 ALPHA_BUILTIN_MSKQL
,
6338 ALPHA_BUILTIN_MSKWH
,
6339 ALPHA_BUILTIN_MSKLH
,
6340 ALPHA_BUILTIN_MSKQH
,
6341 ALPHA_BUILTIN_UMULH
,
6343 ALPHA_BUILTIN_ZAPNOT
,
6344 ALPHA_BUILTIN_AMASK
,
6345 ALPHA_BUILTIN_IMPLVER
,
6347 ALPHA_BUILTIN_THREAD_POINTER
,
6348 ALPHA_BUILTIN_SET_THREAD_POINTER
,
6351 ALPHA_BUILTIN_MINUB8
,
6352 ALPHA_BUILTIN_MINSB8
,
6353 ALPHA_BUILTIN_MINUW4
,
6354 ALPHA_BUILTIN_MINSW4
,
6355 ALPHA_BUILTIN_MAXUB8
,
6356 ALPHA_BUILTIN_MAXSB8
,
6357 ALPHA_BUILTIN_MAXUW4
,
6358 ALPHA_BUILTIN_MAXSW4
,
6362 ALPHA_BUILTIN_UNPKBL
,
6363 ALPHA_BUILTIN_UNPKBW
,
6368 ALPHA_BUILTIN_CTPOP
,
6373 static unsigned int const code_for_builtin
[ALPHA_BUILTIN_max
] = {
6374 CODE_FOR_builtin_cmpbge
,
6375 CODE_FOR_builtin_extbl
,
6376 CODE_FOR_builtin_extwl
,
6377 CODE_FOR_builtin_extll
,
6378 CODE_FOR_builtin_extql
,
6379 CODE_FOR_builtin_extwh
,
6380 CODE_FOR_builtin_extlh
,
6381 CODE_FOR_builtin_extqh
,
6382 CODE_FOR_builtin_insbl
,
6383 CODE_FOR_builtin_inswl
,
6384 CODE_FOR_builtin_insll
,
6385 CODE_FOR_builtin_insql
,
6386 CODE_FOR_builtin_inswh
,
6387 CODE_FOR_builtin_inslh
,
6388 CODE_FOR_builtin_insqh
,
6389 CODE_FOR_builtin_mskbl
,
6390 CODE_FOR_builtin_mskwl
,
6391 CODE_FOR_builtin_mskll
,
6392 CODE_FOR_builtin_mskql
,
6393 CODE_FOR_builtin_mskwh
,
6394 CODE_FOR_builtin_msklh
,
6395 CODE_FOR_builtin_mskqh
,
6396 CODE_FOR_umuldi3_highpart
,
6397 CODE_FOR_builtin_zap
,
6398 CODE_FOR_builtin_zapnot
,
6399 CODE_FOR_builtin_amask
,
6400 CODE_FOR_builtin_implver
,
6401 CODE_FOR_builtin_rpcc
,
6406 CODE_FOR_builtin_minub8
,
6407 CODE_FOR_builtin_minsb8
,
6408 CODE_FOR_builtin_minuw4
,
6409 CODE_FOR_builtin_minsw4
,
6410 CODE_FOR_builtin_maxub8
,
6411 CODE_FOR_builtin_maxsb8
,
6412 CODE_FOR_builtin_maxuw4
,
6413 CODE_FOR_builtin_maxsw4
,
6414 CODE_FOR_builtin_perr
,
6415 CODE_FOR_builtin_pklb
,
6416 CODE_FOR_builtin_pkwb
,
6417 CODE_FOR_builtin_unpkbl
,
6418 CODE_FOR_builtin_unpkbw
,
6421 CODE_FOR_builtin_cttz
,
6422 CODE_FOR_builtin_ctlz
,
6423 CODE_FOR_builtin_ctpop
6426 struct alpha_builtin_def
6429 enum alpha_builtin code
;
6430 unsigned int target_mask
;
6433 static struct alpha_builtin_def
const zero_arg_builtins
[] = {
6434 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER
, 0 },
6435 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC
, 0 }
6438 static struct alpha_builtin_def
const one_arg_builtins
[] = {
6439 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK
, 0 },
6440 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB
, MASK_MAX
},
6441 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB
, MASK_MAX
},
6442 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL
, MASK_MAX
},
6443 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW
, MASK_MAX
},
6444 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ
, MASK_CIX
},
6445 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ
, MASK_CIX
},
6446 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP
, MASK_CIX
}
6449 static struct alpha_builtin_def
const two_arg_builtins
[] = {
6450 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE
, 0 },
6451 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL
, 0 },
6452 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL
, 0 },
6453 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL
, 0 },
6454 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL
, 0 },
6455 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH
, 0 },
6456 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH
, 0 },
6457 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH
, 0 },
6458 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL
, 0 },
6459 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL
, 0 },
6460 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL
, 0 },
6461 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL
, 0 },
6462 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH
, 0 },
6463 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH
, 0 },
6464 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH
, 0 },
6465 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL
, 0 },
6466 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL
, 0 },
6467 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL
, 0 },
6468 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL
, 0 },
6469 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH
, 0 },
6470 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH
, 0 },
6471 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH
, 0 },
6472 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH
, 0 },
6473 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP
, 0 },
6474 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT
, 0 },
6475 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8
, MASK_MAX
},
6476 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8
, MASK_MAX
},
6477 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4
, MASK_MAX
},
6478 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4
, MASK_MAX
},
6479 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8
, MASK_MAX
},
6480 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8
, MASK_MAX
},
6481 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4
, MASK_MAX
},
6482 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4
, MASK_MAX
},
6483 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR
, MASK_MAX
}
6487 alpha_init_builtins ()
6489 const struct alpha_builtin_def
*p
;
6493 ftype
= build_function_type (long_integer_type_node
, void_list_node
);
6495 p
= zero_arg_builtins
;
6496 for (i
= 0; i
< ARRAY_SIZE (zero_arg_builtins
); ++i
, ++p
)
6497 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6498 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6501 ftype
= build_function_type_list (long_integer_type_node
,
6502 long_integer_type_node
, NULL_TREE
);
6504 p
= one_arg_builtins
;
6505 for (i
= 0; i
< ARRAY_SIZE (one_arg_builtins
); ++i
, ++p
)
6506 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6507 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6510 ftype
= build_function_type_list (long_integer_type_node
,
6511 long_integer_type_node
,
6512 long_integer_type_node
, NULL_TREE
);
6514 p
= two_arg_builtins
;
6515 for (i
= 0; i
< ARRAY_SIZE (two_arg_builtins
); ++i
, ++p
)
6516 if ((target_flags
& p
->target_mask
) == p
->target_mask
)
6517 builtin_function (p
->name
, ftype
, p
->code
, BUILT_IN_MD
,
6520 ftype
= build_function_type (ptr_type_node
, void_list_node
);
6521 builtin_function ("__builtin_thread_pointer", ftype
,
6522 ALPHA_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
6525 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
6526 builtin_function ("__builtin_set_thread_pointer", ftype
,
6527 ALPHA_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
6531 /* Expand an expression EXP that calls a built-in function,
6532 with result going to TARGET if that's convenient
6533 (and in mode MODE if that's convenient).
6534 SUBTARGET may be used as the target for computing one of EXP's operands.
6535 IGNORE is nonzero if the value is to be ignored. */
6538 alpha_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
6541 rtx subtarget ATTRIBUTE_UNUSED
;
6542 enum machine_mode mode ATTRIBUTE_UNUSED
;
6543 int ignore ATTRIBUTE_UNUSED
;
6547 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
6548 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
6549 tree arglist
= TREE_OPERAND (exp
, 1);
6550 enum insn_code icode
;
6551 rtx op
[MAX_ARGS
], pat
;
6555 if (fcode
>= ALPHA_BUILTIN_max
)
6556 internal_error ("bad builtin fcode");
6557 icode
= code_for_builtin
[fcode
];
6559 internal_error ("bad builtin fcode");
6561 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
6563 for (arglist
= TREE_OPERAND (exp
, 1), arity
= 0;
6565 arglist
= TREE_CHAIN (arglist
), arity
++)
6567 const struct insn_operand_data
*insn_op
;
6569 tree arg
= TREE_VALUE (arglist
);
6570 if (arg
== error_mark_node
)
6572 if (arity
> MAX_ARGS
)
6575 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
6577 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
6579 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
6580 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
6585 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
6587 || GET_MODE (target
) != tmode
6588 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
6589 target
= gen_reg_rtx (tmode
);
6595 pat
= GEN_FCN (icode
) (target
);
6599 pat
= GEN_FCN (icode
) (target
, op
[0]);
6601 pat
= GEN_FCN (icode
) (op
[0]);
6604 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
6619 /* This page contains routines that are used to determine what the function
6620 prologue and epilogue code will do and write them out. */
6622 /* Compute the size of the save area in the stack. */
6624 /* These variables are used for communication between the following functions.
6625 They indicate various things about the current function being compiled
6626 that are used to tell what kind of prologue, epilogue and procedure
6627 descriptior to generate. */
6629 /* Nonzero if we need a stack procedure. */
6630 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
6631 static enum alpha_procedure_types alpha_procedure_type
;
6633 /* Register number (either FP or SP) that is used to unwind the frame. */
6634 static int vms_unwind_regno
;
6636 /* Register number used to save FP. We need not have one for RA since
6637 we don't modify it for register procedures. This is only defined
6638 for register frame procedures. */
6639 static int vms_save_fp_regno
;
6641 /* Register number used to reference objects off our PV. */
6642 static int vms_base_regno
;
6644 /* Compute register masks for saved registers. */
6647 alpha_sa_mask (imaskP
, fmaskP
)
6648 unsigned long *imaskP
;
6649 unsigned long *fmaskP
;
6651 unsigned long imask
= 0;
6652 unsigned long fmask
= 0;
6655 /* Irritatingly, there are two kinds of thunks -- those created with
6656 ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go through
6657 the regular part of the compiler. In the ASM_OUTPUT_MI_THUNK case
6658 we don't have valid register life info, but assemble_start_function
6659 wants to output .frame and .mask directives. */
6660 if (current_function_is_thunk
&& !no_new_pseudos
)
6667 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6668 imask
|= (1L << HARD_FRAME_POINTER_REGNUM
);
6670 /* One for every register we have to save. */
6671 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6672 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
6673 && regs_ever_live
[i
] && i
!= REG_RA
6674 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
6679 fmask
|= (1L << (i
- 32));
6682 /* We need to restore these for the handler. */
6683 if (current_function_calls_eh_return
)
6686 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
6687 if (regno
== INVALID_REGNUM
)
6689 imask
|= 1L << regno
;
6692 /* If any register spilled, then spill the return address also. */
6693 /* ??? This is required by the Digital stack unwind specification
6694 and isn't needed if we're doing Dwarf2 unwinding. */
6695 if (imask
|| fmask
|| alpha_ra_ever_killed ())
6696 imask
|= (1L << REG_RA
);
6705 unsigned long mask
[2];
6709 alpha_sa_mask (&mask
[0], &mask
[1]);
6711 if (TARGET_ABI_UNICOSMK
)
6713 if (mask
[0] || mask
[1])
6718 for (j
= 0; j
< 2; ++j
)
6719 for (i
= 0; i
< 32; ++i
)
6720 if ((mask
[j
] >> i
) & 1)
6724 if (TARGET_ABI_UNICOSMK
)
6726 /* We might not need to generate a frame if we don't make any calls
6727 (including calls to __T3E_MISMATCH if this is a vararg function),
6728 don't have any local variables which require stack slots, don't
6729 use alloca and have not determined that we need a frame for other
6732 alpha_procedure_type
6733 = (sa_size
|| get_frame_size() != 0
6734 || current_function_outgoing_args_size
6735 || current_function_stdarg
|| current_function_calls_alloca
6736 || frame_pointer_needed
)
6737 ? PT_STACK
: PT_REGISTER
;
6739 /* Always reserve space for saving callee-saved registers if we
6740 need a frame as required by the calling convention. */
6741 if (alpha_procedure_type
== PT_STACK
)
6744 else if (TARGET_ABI_OPEN_VMS
)
6746 /* Start by assuming we can use a register procedure if we don't
6747 make any calls (REG_RA not used) or need to save any
6748 registers and a stack procedure if we do. */
6749 if ((mask
[0] >> REG_RA
) & 1)
6750 alpha_procedure_type
= PT_STACK
;
6751 else if (get_frame_size() != 0)
6752 alpha_procedure_type
= PT_REGISTER
;
6754 alpha_procedure_type
= PT_NULL
;
6756 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6757 made the final decision on stack procedure vs register procedure. */
6758 if (alpha_procedure_type
== PT_STACK
)
6761 /* Decide whether to refer to objects off our PV via FP or PV.
6762 If we need FP for something else or if we receive a nonlocal
6763 goto (which expects PV to contain the value), we must use PV.
6764 Otherwise, start by assuming we can use FP. */
6767 = (frame_pointer_needed
6768 || current_function_has_nonlocal_label
6769 || alpha_procedure_type
== PT_STACK
6770 || current_function_outgoing_args_size
)
6771 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
6773 /* If we want to copy PV into FP, we need to find some register
6774 in which to save FP. */
6776 vms_save_fp_regno
= -1;
6777 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
6778 for (i
= 0; i
< 32; i
++)
6779 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
6780 vms_save_fp_regno
= i
;
6782 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
6783 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
6784 else if (alpha_procedure_type
== PT_NULL
)
6785 vms_base_regno
= REG_PV
;
6787 /* Stack unwinding should be done via FP unless we use it for PV. */
6788 vms_unwind_regno
= (vms_base_regno
== REG_PV
6789 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
6791 /* If this is a stack procedure, allow space for saving FP and RA. */
6792 if (alpha_procedure_type
== PT_STACK
)
6797 /* Our size must be even (multiple of 16 bytes). */
6806 alpha_pv_save_size ()
6809 return alpha_procedure_type
== PT_STACK
? 8 : 0;
6816 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
6819 #if TARGET_ABI_OPEN_VMS
6821 const struct attribute_spec vms_attribute_table
[] =
6823 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6824 { "overlaid", 0, 0, true, false, false, NULL
},
6825 { "global", 0, 0, true, false, false, NULL
},
6826 { "initialize", 0, 0, true, false, false, NULL
},
6827 { NULL
, 0, 0, false, false, false, NULL
}
6833 find_lo_sum (px
, data
)
6835 void *data ATTRIBUTE_UNUSED
;
6837 return GET_CODE (*px
) == LO_SUM
;
6841 alpha_does_function_need_gp ()
6845 /* The GP being variable is an OSF abi thing. */
6846 if (! TARGET_ABI_OSF
)
6849 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6852 if (current_function_is_thunk
)
6855 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6856 Even if we are a static function, we still need to do this in case
6857 our address is taken and passed to something like qsort. */
6859 push_topmost_sequence ();
6860 insn
= get_insns ();
6861 pop_topmost_sequence ();
6863 for (; insn
; insn
= NEXT_INSN (insn
))
6865 && GET_CODE (PATTERN (insn
)) != USE
6866 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6868 enum attr_type type
= get_attr_type (insn
);
6869 if (type
== TYPE_LDSYM
|| type
== TYPE_JSR
)
6871 if (TARGET_EXPLICIT_RELOCS
6872 && for_each_rtx (&PATTERN (insn
), find_lo_sum
, NULL
) > 0)
6879 /* Write a version stamp. Don't write anything if we are running as a
6880 cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
6887 alpha_write_verstamp (file
)
6888 FILE *file ATTRIBUTE_UNUSED
;
6891 fprintf (file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
6895 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6899 set_frame_related_p ()
6901 rtx seq
= get_insns ();
6912 while (insn
!= NULL_RTX
)
6914 RTX_FRAME_RELATED_P (insn
) = 1;
6915 insn
= NEXT_INSN (insn
);
6917 seq
= emit_insn (seq
);
6921 seq
= emit_insn (seq
);
6922 RTX_FRAME_RELATED_P (seq
) = 1;
6927 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
6929 /* Write function prologue. */
6931 /* On vms we have two kinds of functions:
6933 - stack frame (PROC_STACK)
6934 these are 'normal' functions with local vars and which are
6935 calling other functions
6936 - register frame (PROC_REGISTER)
6937 keeps all data in registers, needs no stack
6939 We must pass this to the assembler so it can generate the
6940 proper pdsc (procedure descriptor)
6941 This is done with the '.pdesc' command.
6943 On not-vms, we don't really differentiate between the two, as we can
6944 simply allocate stack without saving registers. */
6947 alpha_expand_prologue ()
6949 /* Registers to save. */
6950 unsigned long imask
= 0;
6951 unsigned long fmask
= 0;
6952 /* Stack space needed for pushing registers clobbered by us. */
6953 HOST_WIDE_INT sa_size
;
6954 /* Complete stack size needed. */
6955 HOST_WIDE_INT frame_size
;
6956 /* Offset from base reg to register save area. */
6957 HOST_WIDE_INT reg_offset
;
6961 sa_size
= alpha_sa_size ();
6963 frame_size
= get_frame_size ();
6964 if (TARGET_ABI_OPEN_VMS
)
6965 frame_size
= ALPHA_ROUND (sa_size
6966 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
6968 + current_function_pretend_args_size
);
6969 else if (TARGET_ABI_UNICOSMK
)
6970 /* We have to allocate space for the DSIB if we generate a frame. */
6971 frame_size
= ALPHA_ROUND (sa_size
6972 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
6973 + ALPHA_ROUND (frame_size
6974 + current_function_outgoing_args_size
);
6976 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
6978 + ALPHA_ROUND (frame_size
6979 + current_function_pretend_args_size
));
6981 if (TARGET_ABI_OPEN_VMS
)
6984 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
6986 alpha_sa_mask (&imask
, &fmask
);
6988 /* Emit an insn to reload GP, if needed. */
6991 alpha_function_needs_gp
= alpha_does_function_need_gp ();
6992 if (alpha_function_needs_gp
)
6993 emit_insn (gen_prologue_ldgp ());
6996 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
6997 the call to mcount ourselves, rather than having the linker do it
6998 magically in response to -pg. Since _mcount has special linkage,
6999 don't represent the call as a call. */
7000 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
7001 emit_insn (gen_prologue_mcount ());
7003 if (TARGET_ABI_UNICOSMK
)
7004 unicosmk_gen_dsib (&imask
);
7006 /* Adjust the stack by the frame size. If the frame size is > 4096
7007 bytes, we need to be sure we probe somewhere in the first and last
7008 4096 bytes (we can probably get away without the latter test) and
7009 every 8192 bytes in between. If the frame size is > 32768, we
7010 do this in a loop. Otherwise, we generate the explicit probe
7013 Note that we are only allowed to adjust sp once in the prologue. */
7015 if (frame_size
<= 32768)
7017 if (frame_size
> 4096)
7022 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7025 while ((probed
+= 8192) < frame_size
);
7027 /* We only have to do this probe if we aren't saving registers. */
7028 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
7029 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
7032 if (frame_size
!= 0)
7033 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7034 GEN_INT (TARGET_ABI_UNICOSMK
7040 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7041 number of 8192 byte blocks to probe. We then probe each block
7042 in the loop and then set SP to the proper location. If the
7043 amount remaining is > 4096, we have to do one more probe if we
7044 are not saving any registers. */
7046 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
7047 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
7048 rtx ptr
= gen_rtx_REG (DImode
, 22);
7049 rtx count
= gen_rtx_REG (DImode
, 23);
7052 emit_move_insn (count
, GEN_INT (blocks
));
7053 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
7054 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
7056 /* Because of the difficulty in emitting a new basic block this
7057 late in the compilation, generate the loop as a single insn. */
7058 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
7060 if (leftover
> 4096 && sa_size
== 0)
7062 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
7063 MEM_VOLATILE_P (last
) = 1;
7064 emit_move_insn (last
, const0_rtx
);
7067 if (TARGET_ABI_WINDOWS_NT
)
7069 /* For NT stack unwind (done by 'reverse execution'), it's
7070 not OK to take the result of a loop, even though the value
7071 is already in ptr, so we reload it via a single operation
7072 and subtract it to sp.
7074 Yes, that's correct -- we have to reload the whole constant
7075 into a temporary via ldah+lda then subtract from sp. To
7076 ensure we get ldah+lda, we use a special pattern. */
7078 HOST_WIDE_INT lo
, hi
;
7079 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7080 hi
= frame_size
- lo
;
7082 emit_move_insn (ptr
, GEN_INT (hi
));
7083 emit_insn (gen_nt_lda (ptr
, GEN_INT (lo
)));
7084 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7089 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
7090 GEN_INT (-leftover
)));
7093 /* This alternative is special, because the DWARF code cannot
7094 possibly intuit through the loop above. So we invent this
7095 note it looks at instead. */
7096 RTX_FRAME_RELATED_P (seq
) = 1;
7098 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7099 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7100 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7101 GEN_INT (TARGET_ABI_UNICOSMK
7107 if (!TARGET_ABI_UNICOSMK
)
7109 /* Cope with very large offsets to the register save area. */
7110 sa_reg
= stack_pointer_rtx
;
7111 if (reg_offset
+ sa_size
> 0x8000)
7113 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7116 if (low
+ sa_size
<= 0x8000)
7117 bias
= reg_offset
- low
, reg_offset
= low
;
7119 bias
= reg_offset
, reg_offset
= 0;
7121 sa_reg
= gen_rtx_REG (DImode
, 24);
7122 FRP (emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
,
7126 /* Save regs in stack order. Beginning with VMS PV. */
7127 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7129 mem
= gen_rtx_MEM (DImode
, stack_pointer_rtx
);
7130 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7131 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_PV
)));
7134 /* Save register RA next. */
7135 if (imask
& (1L << REG_RA
))
7137 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7138 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7139 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
7140 imask
&= ~(1L << REG_RA
);
7144 /* Now save any other registers required to be saved. */
7145 for (i
= 0; i
< 32; i
++)
7146 if (imask
& (1L << i
))
7148 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7149 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7150 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7154 for (i
= 0; i
< 32; i
++)
7155 if (fmask
& (1L << i
))
7157 mem
= gen_rtx_MEM (DFmode
, plus_constant (sa_reg
, reg_offset
));
7158 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7159 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7163 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7165 /* The standard frame on the T3E includes space for saving registers.
7166 We just have to use it. We don't have to save the return address and
7167 the old frame pointer here - they are saved in the DSIB. */
7170 for (i
= 9; i
< 15; i
++)
7171 if (imask
& (1L << i
))
7173 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7175 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7176 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
7179 for (i
= 2; i
< 10; i
++)
7180 if (fmask
& (1L << i
))
7182 mem
= gen_rtx_MEM (DFmode
, plus_constant (hard_frame_pointer_rtx
,
7184 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7185 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
7190 if (TARGET_ABI_OPEN_VMS
)
7192 if (alpha_procedure_type
== PT_REGISTER
)
7193 /* Register frame procedures save the fp.
7194 ?? Ought to have a dwarf2 save for this. */
7195 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
7196 hard_frame_pointer_rtx
);
7198 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
7199 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
7200 gen_rtx_REG (DImode
, REG_PV
)));
7202 if (alpha_procedure_type
!= PT_NULL
7203 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7204 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7206 /* If we have to allocate space for outgoing args, do it now. */
7207 if (current_function_outgoing_args_size
!= 0)
7210 plus_constant (hard_frame_pointer_rtx
,
7212 (current_function_outgoing_args_size
)))));
7214 else if (!TARGET_ABI_UNICOSMK
)
7216 /* If we need a frame pointer, set it from the stack pointer. */
7217 if (frame_pointer_needed
)
7219 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
7220 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
7222 /* This must always be the last instruction in the
7223 prologue, thus we emit a special move + clobber. */
7224 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
7225 stack_pointer_rtx
, sa_reg
)));
7229 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7230 the prologue, for exception handling reasons, we cannot do this for
7231 any insn that might fault. We could prevent this for mems with a
7232 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7233 have to prevent all such scheduling with a blockage.
7235 Linux, on the other hand, never bothered to implement OSF/1's
7236 exception handling, and so doesn't care about such things. Anyone
7237 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7239 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
7240 emit_insn (gen_blockage ());
7243 /* Output the textual info surrounding the prologue. */
7246 alpha_start_function (file
, fnname
, decl
)
7249 tree decl ATTRIBUTE_UNUSED
;
7251 unsigned long imask
= 0;
7252 unsigned long fmask
= 0;
7253 /* Stack space needed for pushing registers clobbered by us. */
7254 HOST_WIDE_INT sa_size
;
7255 /* Complete stack size needed. */
7256 HOST_WIDE_INT frame_size
;
7257 /* Offset from base reg to register save area. */
7258 HOST_WIDE_INT reg_offset
;
7259 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
7262 /* Don't emit an extern directive for functions defined in the same file. */
7263 if (TARGET_ABI_UNICOSMK
)
7266 name_tree
= get_identifier (fnname
);
7267 TREE_ASM_WRITTEN (name_tree
) = 1;
7270 alpha_fnname
= fnname
;
7271 sa_size
= alpha_sa_size ();
7273 frame_size
= get_frame_size ();
7274 if (TARGET_ABI_OPEN_VMS
)
7275 frame_size
= ALPHA_ROUND (sa_size
7276 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7278 + current_function_pretend_args_size
);
7279 else if (TARGET_ABI_UNICOSMK
)
7280 frame_size
= ALPHA_ROUND (sa_size
7281 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7282 + ALPHA_ROUND (frame_size
7283 + current_function_outgoing_args_size
);
7285 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7287 + ALPHA_ROUND (frame_size
7288 + current_function_pretend_args_size
));
7290 if (TARGET_ABI_OPEN_VMS
)
7293 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7295 alpha_sa_mask (&imask
, &fmask
);
7297 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7298 We have to do that before the .ent directive as we cannot switch
7299 files within procedures with native ecoff because line numbers are
7300 linked to procedure descriptors.
7301 Outputting the lineno helps debugging of one line functions as they
7302 would otherwise get no line number at all. Please note that we would
7303 like to put out last_linenum from final.c, but it is not accessible. */
7305 if (write_symbols
== SDB_DEBUG
)
7307 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7308 ASM_OUTPUT_SOURCE_FILENAME (file
,
7309 DECL_SOURCE_FILE (current_function_decl
));
7311 #ifdef ASM_OUTPUT_SOURCE_LINE
7312 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
7313 ASM_OUTPUT_SOURCE_LINE (file
,
7314 DECL_SOURCE_LINE (current_function_decl
));
7318 /* Issue function start and label. */
7319 if (TARGET_ABI_OPEN_VMS
7320 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
7322 fputs ("\t.ent ", file
);
7323 assemble_name (file
, fnname
);
7326 /* If the function needs GP, we'll write the "..ng" label there.
7327 Otherwise, do it here. */
7329 && ! alpha_function_needs_gp
7330 && ! current_function_is_thunk
)
7333 assemble_name (file
, fnname
);
7334 fputs ("..ng:\n", file
);
7338 strcpy (entry_label
, fnname
);
7339 if (TARGET_ABI_OPEN_VMS
)
7340 strcat (entry_label
, "..en");
7342 /* For public functions, the label must be globalized by appending an
7343 additional colon. */
7344 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
7345 strcat (entry_label
, ":");
7347 ASM_OUTPUT_LABEL (file
, entry_label
);
7348 inside_function
= TRUE
;
7350 if (TARGET_ABI_OPEN_VMS
)
7351 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
7353 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
7354 && !flag_inhibit_size_directive
)
7356 /* Set flags in procedure descriptor to request IEEE-conformant
7357 math-library routines. The value we set it to is PDSC_EXC_IEEE
7358 (/usr/include/pdsc.h). */
7359 fputs ("\t.eflag 48\n", file
);
7362 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7363 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
7364 alpha_arg_offset
= -frame_size
+ 48;
7366 /* Describe our frame. If the frame size is larger than an integer,
7367 print it as zero to avoid an assembler error. We won't be
7368 properly describing such a frame, but that's the best we can do. */
7369 if (TARGET_ABI_UNICOSMK
)
7371 else if (TARGET_ABI_OPEN_VMS
)
7373 fprintf (file
, "\t.frame $%d,", vms_unwind_regno
);
7374 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7375 frame_size
>= ((HOST_WIDE_INT
) 1 << 31) ? 0 : frame_size
);
7376 fputs (",$26,", file
);
7377 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, reg_offset
);
7380 else if (!flag_inhibit_size_directive
)
7382 fprintf (file
, "\t.frame $%d,",
7383 (frame_pointer_needed
7384 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
));
7385 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7386 frame_size
>= (1l << 31) ? 0 : frame_size
);
7387 fprintf (file
, ",$26,%d\n", current_function_pretend_args_size
);
7390 /* Describe which registers were spilled. */
7391 if (TARGET_ABI_UNICOSMK
)
7393 else if (TARGET_ABI_OPEN_VMS
)
7396 /* ??? Does VMS care if mask contains ra? The old code didn't
7397 set it, so I don't here. */
7398 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1L << REG_RA
));
7400 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
7401 if (alpha_procedure_type
== PT_REGISTER
)
7402 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
7404 else if (!flag_inhibit_size_directive
)
7408 fprintf (file
, "\t.mask 0x%lx,", imask
);
7409 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7410 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
7413 for (i
= 0; i
< 32; ++i
)
7414 if (imask
& (1L << i
))
7420 fprintf (file
, "\t.fmask 0x%lx,", fmask
);
7421 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7422 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
7427 #if TARGET_ABI_OPEN_VMS
7428 /* Ifdef'ed cause link_section are only available then. */
7429 readonly_data_section ();
7430 fprintf (file
, "\t.align 3\n");
7431 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
7432 fputs ("\t.ascii \"", file
);
7433 assemble_name (file
, fnname
);
7434 fputs ("\\0\"\n", file
);
7437 fprintf (file
, "\t.align 3\n");
7438 fputs ("\t.name ", file
);
7439 assemble_name (file
, fnname
);
7440 fputs ("..na\n", file
);
7441 ASM_OUTPUT_LABEL (file
, fnname
);
7442 fprintf (file
, "\t.pdesc ");
7443 assemble_name (file
, fnname
);
7444 fprintf (file
, "..en,%s\n",
7445 alpha_procedure_type
== PT_STACK
? "stack"
7446 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
7447 alpha_need_linkage (fnname
, 1);
7452 /* Emit the .prologue note at the scheduled end of the prologue. */
7455 alpha_output_function_end_prologue (file
)
7458 if (TARGET_ABI_UNICOSMK
)
7460 else if (TARGET_ABI_OPEN_VMS
)
7461 fputs ("\t.prologue\n", file
);
7462 else if (TARGET_ABI_WINDOWS_NT
)
7463 fputs ("\t.prologue 0\n", file
);
7464 else if (!flag_inhibit_size_directive
)
7465 fprintf (file
, "\t.prologue %d\n",
7466 alpha_function_needs_gp
|| current_function_is_thunk
);
7469 /* Write function epilogue. */
7471 /* ??? At some point we will want to support full unwind, and so will
7472 need to mark the epilogue as well. At the moment, we just confuse
7475 #define FRP(exp) exp
7478 alpha_expand_epilogue ()
7480 /* Registers to save. */
7481 unsigned long imask
= 0;
7482 unsigned long fmask
= 0;
7483 /* Stack space needed for pushing registers clobbered by us. */
7484 HOST_WIDE_INT sa_size
;
7485 /* Complete stack size needed. */
7486 HOST_WIDE_INT frame_size
;
7487 /* Offset from base reg to register save area. */
7488 HOST_WIDE_INT reg_offset
;
7489 int fp_is_frame_pointer
, fp_offset
;
7490 rtx sa_reg
, sa_reg_exp
= NULL
;
7491 rtx sp_adj1
, sp_adj2
, mem
;
7495 sa_size
= alpha_sa_size ();
7497 frame_size
= get_frame_size ();
7498 if (TARGET_ABI_OPEN_VMS
)
7499 frame_size
= ALPHA_ROUND (sa_size
7500 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
7502 + current_function_pretend_args_size
);
7503 else if (TARGET_ABI_UNICOSMK
)
7504 frame_size
= ALPHA_ROUND (sa_size
7505 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
7506 + ALPHA_ROUND (frame_size
7507 + current_function_outgoing_args_size
);
7509 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
7511 + ALPHA_ROUND (frame_size
7512 + current_function_pretend_args_size
));
7514 if (TARGET_ABI_OPEN_VMS
)
7516 if (alpha_procedure_type
== PT_STACK
)
7522 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
7524 alpha_sa_mask (&imask
, &fmask
);
7527 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
7528 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
7530 sa_reg
= stack_pointer_rtx
;
7532 if (current_function_calls_eh_return
)
7533 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7537 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
7539 /* If we have a frame pointer, restore SP from it. */
7540 if ((TARGET_ABI_OPEN_VMS
7541 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
7542 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
7543 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7545 /* Cope with very large offsets to the register save area. */
7546 if (reg_offset
+ sa_size
> 0x8000)
7548 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
7551 if (low
+ sa_size
<= 0x8000)
7552 bias
= reg_offset
- low
, reg_offset
= low
;
7554 bias
= reg_offset
, reg_offset
= 0;
7556 sa_reg
= gen_rtx_REG (DImode
, 22);
7557 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
7559 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
7562 /* Restore registers in order, excepting a true frame pointer. */
7564 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
7566 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7567 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7570 imask
&= ~(1L << REG_RA
);
7572 for (i
= 0; i
< 32; ++i
)
7573 if (imask
& (1L << i
))
7575 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
7576 fp_offset
= reg_offset
;
7579 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
7580 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7581 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7586 for (i
= 0; i
< 32; ++i
)
7587 if (fmask
& (1L << i
))
7589 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
7590 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7591 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7595 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
7597 /* Restore callee-saved general-purpose registers. */
7601 for (i
= 9; i
< 15; i
++)
7602 if (imask
& (1L << i
))
7604 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
7606 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7607 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
7611 for (i
= 2; i
< 10; i
++)
7612 if (fmask
& (1L << i
))
7614 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
7616 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7617 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
7621 /* Restore the return address from the DSIB. */
7623 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
7624 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7625 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
7628 if (frame_size
|| eh_ofs
)
7630 sp_adj1
= stack_pointer_rtx
;
7634 sp_adj1
= gen_rtx_REG (DImode
, 23);
7635 emit_move_insn (sp_adj1
,
7636 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
7639 /* If the stack size is large, begin computation into a temporary
7640 register so as not to interfere with a potential fp restore,
7641 which must be consecutive with an SP restore. */
7642 if (frame_size
< 32768
7643 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
7644 sp_adj2
= GEN_INT (frame_size
);
7645 else if (TARGET_ABI_UNICOSMK
)
7647 sp_adj1
= gen_rtx_REG (DImode
, 23);
7648 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
7649 sp_adj2
= const0_rtx
;
7651 else if (frame_size
< 0x40007fffL
)
7653 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
7655 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
7656 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
7660 sp_adj1
= gen_rtx_REG (DImode
, 23);
7661 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
7663 sp_adj2
= GEN_INT (low
);
7667 rtx tmp
= gen_rtx_REG (DImode
, 23);
7668 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
7671 /* We can't drop new things to memory this late, afaik,
7672 so build it up by pieces. */
7673 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
7674 -(frame_size
< 0)));
7680 /* From now on, things must be in order. So emit blockages. */
7682 /* Restore the frame pointer. */
7683 if (TARGET_ABI_UNICOSMK
)
7685 emit_insn (gen_blockage ());
7686 mem
= gen_rtx_MEM (DImode
,
7687 plus_constant (hard_frame_pointer_rtx
, -16));
7688 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7689 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7691 else if (fp_is_frame_pointer
)
7693 emit_insn (gen_blockage ());
7694 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
7695 set_mem_alias_set (mem
, alpha_sr_alias_set
);
7696 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
7698 else if (TARGET_ABI_OPEN_VMS
)
7700 emit_insn (gen_blockage ());
7701 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7702 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7705 /* Restore the stack pointer. */
7706 emit_insn (gen_blockage ());
7707 if (sp_adj2
== const0_rtx
)
7708 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
7710 FRP (emit_move_insn (stack_pointer_rtx
,
7711 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
7715 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
7717 emit_insn (gen_blockage ());
7718 FRP (emit_move_insn (hard_frame_pointer_rtx
,
7719 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
7721 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
7723 /* Decrement the frame pointer if the function does not have a
7726 emit_insn (gen_blockage ());
7727 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7728 hard_frame_pointer_rtx
, GEN_INT (-1))));
7733 /* Output the rest of the textual info surrounding the epilogue. */
7736 alpha_end_function (file
, fnname
, decl
)
7741 /* End the function. */
7742 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
7744 fputs ("\t.end ", file
);
7745 assemble_name (file
, fnname
);
7748 inside_function
= FALSE
;
7750 /* Show that we know this function if it is called again.
7752 Do this only for functions whose symbols bind locally.
7754 Don't do this for functions not defined in the .text section, as
7755 otherwise it's not unlikely that the destination is out of range
7756 for a direct branch. */
7758 if ((*targetm
.binds_local_p
) (decl
) && decl_in_text_section (decl
))
7759 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl
), 0)) = 1;
7761 /* Output jump tables and the static subroutine information block. */
7762 if (TARGET_ABI_UNICOSMK
)
7764 unicosmk_output_ssib (file
, fnname
);
7765 unicosmk_output_deferred_case_vectors (file
);
7769 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7771 In order to avoid the hordes of differences between generated code
7772 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7773 lots of code loading up large constants, generate rtl and emit it
7774 instead of going straight to text.
7776 Not sure why this idea hasn't been explored before... */
7779 alpha_output_mi_thunk_osf (file
, thunk_fndecl
, delta
, function
)
7781 tree thunk_fndecl ATTRIBUTE_UNUSED
;
7782 HOST_WIDE_INT delta
;
7785 HOST_WIDE_INT hi
, lo
;
7786 rtx
this, insn
, funexp
;
7788 /* We always require a valid GP. */
7789 emit_insn (gen_prologue_ldgp ());
7790 emit_note (NULL
, NOTE_INSN_PROLOGUE_END
);
7792 /* Find the "this" pointer. If the function returns a structure,
7793 the structure return pointer is in $16. */
7794 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
))))
7795 this = gen_rtx_REG (Pmode
, 17);
7797 this = gen_rtx_REG (Pmode
, 16);
7799 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7800 entire constant for the add. */
7801 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
7802 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7803 if (hi
+ lo
== delta
)
7806 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
7808 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
7812 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
7813 delta
, -(delta
< 0));
7814 emit_insn (gen_adddi3 (this, this, tmp
));
7817 /* Generate a tail call to the target function. */
7818 if (! TREE_USED (function
))
7820 assemble_external (function
);
7821 TREE_USED (function
) = 1;
7823 funexp
= XEXP (DECL_RTL (function
), 0);
7824 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
7825 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
7826 SIBLING_CALL_P (insn
) = 1;
7828 /* Run just enough of rest_of_compilation to get the insns emitted.
7829 There's not really enough bulk here to make other passes such as
7830 instruction scheduling worth while. Note that use_thunk calls
7831 assemble_start_function and assemble_end_function. */
7832 insn
= get_insns ();
7833 shorten_branches (insn
);
7834 final_start_function (insn
, file
, 1);
7835 final (insn
, file
, 1, 0);
7836 final_end_function ();
7839 /* Debugging support. */
7843 /* Count the number of sdb related labels are generated (to find block
7844 start and end boundaries). */
7846 int sdb_label_count
= 0;
7848 /* Next label # for each statement. */
7850 static int sym_lineno
= 0;
7852 /* Count the number of .file directives, so that .loc is up to date. */
7854 static int num_source_filenames
= 0;
7856 /* Name of the file containing the current function. */
7858 static const char *current_function_file
= "";
7860 /* Offsets to alpha virtual arg/local debugging pointers. */
7862 long alpha_arg_offset
;
7863 long alpha_auto_offset
;
7865 /* Emit a new filename to a stream. */
7868 alpha_output_filename (stream
, name
)
7872 static int first_time
= TRUE
;
7873 char ltext_label_name
[100];
7878 ++num_source_filenames
;
7879 current_function_file
= name
;
7880 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7881 output_quoted_string (stream
, name
);
7882 fprintf (stream
, "\n");
7883 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
7884 fprintf (stream
, "\t#@stabs\n");
7887 else if (write_symbols
== DBX_DEBUG
)
7889 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
7890 fprintf (stream
, "%s", ASM_STABS_OP
);
7891 output_quoted_string (stream
, name
);
7892 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
7895 else if (name
!= current_function_file
7896 && strcmp (name
, current_function_file
) != 0)
7898 if (inside_function
&& ! TARGET_GAS
)
7899 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
7902 ++num_source_filenames
;
7903 current_function_file
= name
;
7904 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7907 output_quoted_string (stream
, name
);
7908 fprintf (stream
, "\n");
7912 /* Emit a linenumber to a stream. */
7915 alpha_output_lineno (stream
, line
)
7919 if (write_symbols
== DBX_DEBUG
)
7921 /* mips-tfile doesn't understand .stabd directives. */
7923 fprintf (stream
, "$LM%d:\n%s%d,0,%d,$LM%d\n",
7924 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
7927 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
7930 /* Structure to show the current status of registers and memory. */
7932 struct shadow_summary
7935 unsigned int i
: 31; /* Mask of int regs */
7936 unsigned int fp
: 31; /* Mask of fp regs */
7937 unsigned int mem
: 1; /* mem == imem | fpmem */
7941 static void summarize_insn
PARAMS ((rtx
, struct shadow_summary
*, int));
7942 static void alpha_handle_trap_shadows
PARAMS ((rtx
));
7944 /* Summary the effects of expression X on the machine. Update SUM, a pointer
7945 to the summary structure. SET is nonzero if the insn is setting the
7946 object, otherwise zero. */
7949 summarize_insn (x
, sum
, set
)
7951 struct shadow_summary
*sum
;
7954 const char *format_ptr
;
7960 switch (GET_CODE (x
))
7962 /* ??? Note that this case would be incorrect if the Alpha had a
7963 ZERO_EXTRACT in SET_DEST. */
7965 summarize_insn (SET_SRC (x
), sum
, 0);
7966 summarize_insn (SET_DEST (x
), sum
, 1);
7970 summarize_insn (XEXP (x
, 0), sum
, 1);
7974 summarize_insn (XEXP (x
, 0), sum
, 0);
7978 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
7979 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
7983 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
7984 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
7988 summarize_insn (SUBREG_REG (x
), sum
, 0);
7993 int regno
= REGNO (x
);
7994 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
7996 if (regno
== 31 || regno
== 63)
8002 sum
->defd
.i
|= mask
;
8004 sum
->defd
.fp
|= mask
;
8009 sum
->used
.i
|= mask
;
8011 sum
->used
.fp
|= mask
;
8022 /* Find the regs used in memory address computation: */
8023 summarize_insn (XEXP (x
, 0), sum
, 0);
8026 case CONST_INT
: case CONST_DOUBLE
:
8027 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
8028 case SCRATCH
: case ASM_INPUT
:
8031 /* Handle common unary and binary ops for efficiency. */
8032 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
8033 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
8034 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
8035 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8036 case NE
: case EQ
: case GE
: case GT
: case LE
:
8037 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
8038 summarize_insn (XEXP (x
, 0), sum
, 0);
8039 summarize_insn (XEXP (x
, 1), sum
, 0);
8042 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
8043 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
8044 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
8045 case SQRT
: case FFS
:
8046 summarize_insn (XEXP (x
, 0), sum
, 0);
8050 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
8051 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8052 switch (format_ptr
[i
])
8055 summarize_insn (XEXP (x
, i
), sum
, 0);
8059 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8060 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
8072 /* Ensure a sufficient number of `trapb' insns are in the code when
8073 the user requests code with a trap precision of functions or
8076 In naive mode, when the user requests a trap-precision of
8077 "instruction", a trapb is needed after every instruction that may
8078 generate a trap. This ensures that the code is resumption safe but
8081 When optimizations are turned on, we delay issuing a trapb as long
8082 as possible. In this context, a trap shadow is the sequence of
8083 instructions that starts with a (potentially) trap generating
8084 instruction and extends to the next trapb or call_pal instruction
8085 (but GCC never generates call_pal by itself). We can delay (and
8086 therefore sometimes omit) a trapb subject to the following
8089 (a) On entry to the trap shadow, if any Alpha register or memory
8090 location contains a value that is used as an operand value by some
8091 instruction in the trap shadow (live on entry), then no instruction
8092 in the trap shadow may modify the register or memory location.
8094 (b) Within the trap shadow, the computation of the base register
8095 for a memory load or store instruction may not involve using the
8096 result of an instruction that might generate an UNPREDICTABLE
8099 (c) Within the trap shadow, no register may be used more than once
8100 as a destination register. (This is to make life easier for the
8103 (d) The trap shadow may not include any branch instructions. */
8106 alpha_handle_trap_shadows (insns
)
8109 struct shadow_summary shadow
;
8110 int trap_pending
, exception_nesting
;
8114 exception_nesting
= 0;
8117 shadow
.used
.mem
= 0;
8118 shadow
.defd
= shadow
.used
;
8120 for (i
= insns
; i
; i
= NEXT_INSN (i
))
8122 if (GET_CODE (i
) == NOTE
)
8124 switch (NOTE_LINE_NUMBER (i
))
8126 case NOTE_INSN_EH_REGION_BEG
:
8127 exception_nesting
++;
8132 case NOTE_INSN_EH_REGION_END
:
8133 exception_nesting
--;
8138 case NOTE_INSN_EPILOGUE_BEG
:
8139 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
8144 else if (trap_pending
)
8146 if (alpha_tp
== ALPHA_TP_FUNC
)
8148 if (GET_CODE (i
) == JUMP_INSN
8149 && GET_CODE (PATTERN (i
)) == RETURN
)
8152 else if (alpha_tp
== ALPHA_TP_INSN
)
8156 struct shadow_summary sum
;
8161 sum
.defd
= sum
.used
;
8163 switch (GET_CODE (i
))
8166 /* Annoyingly, get_attr_trap will abort on these. */
8167 if (GET_CODE (PATTERN (i
)) == USE
8168 || GET_CODE (PATTERN (i
)) == CLOBBER
)
8171 summarize_insn (PATTERN (i
), &sum
, 0);
8173 if ((sum
.defd
.i
& shadow
.defd
.i
)
8174 || (sum
.defd
.fp
& shadow
.defd
.fp
))
8176 /* (c) would be violated */
8180 /* Combine shadow with summary of current insn: */
8181 shadow
.used
.i
|= sum
.used
.i
;
8182 shadow
.used
.fp
|= sum
.used
.fp
;
8183 shadow
.used
.mem
|= sum
.used
.mem
;
8184 shadow
.defd
.i
|= sum
.defd
.i
;
8185 shadow
.defd
.fp
|= sum
.defd
.fp
;
8186 shadow
.defd
.mem
|= sum
.defd
.mem
;
8188 if ((sum
.defd
.i
& shadow
.used
.i
)
8189 || (sum
.defd
.fp
& shadow
.used
.fp
)
8190 || (sum
.defd
.mem
& shadow
.used
.mem
))
8192 /* (a) would be violated (also takes care of (b)) */
8193 if (get_attr_trap (i
) == TRAP_YES
8194 && ((sum
.defd
.i
& sum
.used
.i
)
8195 || (sum
.defd
.fp
& sum
.used
.fp
)))
8214 n
= emit_insn_before (gen_trapb (), i
);
8215 PUT_MODE (n
, TImode
);
8216 PUT_MODE (i
, TImode
);
8220 shadow
.used
.mem
= 0;
8221 shadow
.defd
= shadow
.used
;
8226 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
8227 && GET_CODE (i
) == INSN
8228 && GET_CODE (PATTERN (i
)) != USE
8229 && GET_CODE (PATTERN (i
)) != CLOBBER
8230 && get_attr_trap (i
) == TRAP_YES
)
8232 if (optimize
&& !trap_pending
)
8233 summarize_insn (PATTERN (i
), &shadow
, 0);
8239 /* Alpha can only issue instruction groups simultaneously if they are
8240 suitibly aligned. This is very processor-specific. */
8242 enum alphaev4_pipe
{
8249 enum alphaev5_pipe
{
8260 static enum alphaev4_pipe alphaev4_insn_pipe
PARAMS ((rtx
));
8261 static enum alphaev5_pipe alphaev5_insn_pipe
PARAMS ((rtx
));
8262 static rtx alphaev4_next_group
PARAMS ((rtx
, int *, int *));
8263 static rtx alphaev5_next_group
PARAMS ((rtx
, int *, int *));
8264 static rtx alphaev4_next_nop
PARAMS ((int *));
8265 static rtx alphaev5_next_nop
PARAMS ((int *));
8267 static void alpha_align_insns
8268 PARAMS ((rtx
, unsigned int, rtx (*)(rtx
, int *, int *), rtx (*)(int *)));
8270 static enum alphaev4_pipe
8271 alphaev4_insn_pipe (insn
)
8274 if (recog_memoized (insn
) < 0)
8276 if (get_attr_length (insn
) != 4)
8279 switch (get_attr_type (insn
))
8312 static enum alphaev5_pipe
8313 alphaev5_insn_pipe (insn
)
8316 if (recog_memoized (insn
) < 0)
8318 if (get_attr_length (insn
) != 4)
8321 switch (get_attr_type (insn
))
8361 /* IN_USE is a mask of the slots currently filled within the insn group.
8362 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8363 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8365 LEN is, of course, the length of the group in bytes. */
8368 alphaev4_next_group (insn
, pin_use
, plen
)
8370 int *pin_use
, *plen
;
8377 || GET_CODE (PATTERN (insn
)) == CLOBBER
8378 || GET_CODE (PATTERN (insn
)) == USE
)
8383 enum alphaev4_pipe pipe
;
8385 pipe
= alphaev4_insn_pipe (insn
);
8389 /* Force complex instructions to start new groups. */
8393 /* If this is a completely unrecognized insn, its an asm.
8394 We don't know how long it is, so record length as -1 to
8395 signal a needed realignment. */
8396 if (recog_memoized (insn
) < 0)
8399 len
= get_attr_length (insn
);
8403 if (in_use
& EV4_IB0
)
8405 if (in_use
& EV4_IB1
)
8410 in_use
|= EV4_IB0
| EV4_IBX
;
8414 if (in_use
& EV4_IB0
)
8416 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
8424 if (in_use
& EV4_IB1
)
8434 /* Haifa doesn't do well scheduling branches. */
8435 if (GET_CODE (insn
) == JUMP_INSN
)
8439 insn
= next_nonnote_insn (insn
);
8441 if (!insn
|| ! INSN_P (insn
))
8444 /* Let Haifa tell us where it thinks insn group boundaries are. */
8445 if (GET_MODE (insn
) == TImode
)
8448 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8453 insn
= next_nonnote_insn (insn
);
8461 /* IN_USE is a mask of the slots currently filled within the insn group.
8462 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8463 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8465 LEN is, of course, the length of the group in bytes. */
8468 alphaev5_next_group (insn
, pin_use
, plen
)
8470 int *pin_use
, *plen
;
8477 || GET_CODE (PATTERN (insn
)) == CLOBBER
8478 || GET_CODE (PATTERN (insn
)) == USE
)
8483 enum alphaev5_pipe pipe
;
8485 pipe
= alphaev5_insn_pipe (insn
);
8489 /* Force complex instructions to start new groups. */
8493 /* If this is a completely unrecognized insn, its an asm.
8494 We don't know how long it is, so record length as -1 to
8495 signal a needed realignment. */
8496 if (recog_memoized (insn
) < 0)
8499 len
= get_attr_length (insn
);
8502 /* ??? Most of the places below, we would like to abort, as
8503 it would indicate an error either in Haifa, or in the
8504 scheduling description. Unfortunately, Haifa never
8505 schedules the last instruction of the BB, so we don't
8506 have an accurate TI bit to go off. */
8508 if (in_use
& EV5_E0
)
8510 if (in_use
& EV5_E1
)
8515 in_use
|= EV5_E0
| EV5_E01
;
8519 if (in_use
& EV5_E0
)
8521 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
8529 if (in_use
& EV5_E1
)
8535 if (in_use
& EV5_FA
)
8537 if (in_use
& EV5_FM
)
8542 in_use
|= EV5_FA
| EV5_FAM
;
8546 if (in_use
& EV5_FA
)
8552 if (in_use
& EV5_FM
)
8565 /* Haifa doesn't do well scheduling branches. */
8566 /* ??? If this is predicted not-taken, slotting continues, except
8567 that no more IBR, FBR, or JSR insns may be slotted. */
8568 if (GET_CODE (insn
) == JUMP_INSN
)
8572 insn
= next_nonnote_insn (insn
);
8574 if (!insn
|| ! INSN_P (insn
))
8577 /* Let Haifa tell us where it thinks insn group boundaries are. */
8578 if (GET_MODE (insn
) == TImode
)
8581 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
8586 insn
= next_nonnote_insn (insn
);
8595 alphaev4_next_nop (pin_use
)
8598 int in_use
= *pin_use
;
8601 if (!(in_use
& EV4_IB0
))
8606 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
8611 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
8624 alphaev5_next_nop (pin_use
)
8627 int in_use
= *pin_use
;
8630 if (!(in_use
& EV5_E1
))
8635 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
8640 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
8652 /* The instruction group alignment main loop. */
8655 alpha_align_insns (insns
, max_align
, next_group
, next_nop
)
8657 unsigned int max_align
;
8658 rtx (*next_group
) PARAMS ((rtx
, int *, int *));
8659 rtx (*next_nop
) PARAMS ((int *));
8661 /* ALIGN is the known alignment for the insn group. */
8663 /* OFS is the offset of the current insn in the insn group. */
8665 int prev_in_use
, in_use
, len
;
8668 /* Let shorten branches care for assigning alignments to code labels. */
8669 shorten_branches (insns
);
8671 if (align_functions
< 4)
8673 else if ((unsigned int) align_functions
< max_align
)
8674 align
= align_functions
;
8678 ofs
= prev_in_use
= 0;
8680 if (GET_CODE (i
) == NOTE
)
8681 i
= next_nonnote_insn (i
);
8685 next
= (*next_group
) (i
, &in_use
, &len
);
8687 /* When we see a label, resync alignment etc. */
8688 if (GET_CODE (i
) == CODE_LABEL
)
8690 unsigned int new_align
= 1 << label_to_alignment (i
);
8692 if (new_align
>= align
)
8694 align
= new_align
< max_align
? new_align
: max_align
;
8698 else if (ofs
& (new_align
-1))
8699 ofs
= (ofs
| (new_align
-1)) + 1;
8704 /* Handle complex instructions special. */
8705 else if (in_use
== 0)
8707 /* Asms will have length < 0. This is a signal that we have
8708 lost alignment knowledge. Assume, however, that the asm
8709 will not mis-align instructions. */
8718 /* If the known alignment is smaller than the recognized insn group,
8719 realign the output. */
8720 else if ((int) align
< len
)
8722 unsigned int new_log_align
= len
> 8 ? 4 : 3;
8725 where
= prev
= prev_nonnote_insn (i
);
8726 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
8729 /* Can't realign between a call and its gp reload. */
8730 if (! (TARGET_EXPLICIT_RELOCS
8731 && prev
&& GET_CODE (prev
) == CALL_INSN
))
8733 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
8734 align
= 1 << new_log_align
;
8739 /* If the group won't fit in the same INT16 as the previous,
8740 we need to add padding to keep the group together. Rather
8741 than simply leaving the insn filling to the assembler, we
8742 can make use of the knowledge of what sorts of instructions
8743 were issued in the previous group to make sure that all of
8744 the added nops are really free. */
8745 else if (ofs
+ len
> (int) align
)
8747 int nop_count
= (align
- ofs
) / 4;
8750 /* Insert nops before labels, branches, and calls to truely merge
8751 the execution of the nops with the previous instruction group. */
8752 where
= prev_nonnote_insn (i
);
8755 if (GET_CODE (where
) == CODE_LABEL
)
8757 rtx where2
= prev_nonnote_insn (where
);
8758 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
8761 else if (GET_CODE (where
) == INSN
)
8768 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
8769 while (--nop_count
);
8773 ofs
= (ofs
+ len
) & (align
- 1);
8774 prev_in_use
= in_use
;
8779 /* Machine dependent reorg pass. */
8785 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
8786 alpha_handle_trap_shadows (insns
);
8788 /* Due to the number of extra trapb insns, don't bother fixing up
8789 alignment when trap precision is instruction. Moreover, we can
8790 only do our job when sched2 is run. */
8791 if (optimize
&& !optimize_size
8792 && alpha_tp
!= ALPHA_TP_INSN
8793 && flag_schedule_insns_after_reload
)
8795 if (alpha_cpu
== PROCESSOR_EV4
)
8796 alpha_align_insns (insns
, 8, alphaev4_next_group
, alphaev4_next_nop
);
8797 else if (alpha_cpu
== PROCESSOR_EV5
)
8798 alpha_align_insns (insns
, 16, alphaev5_next_group
, alphaev5_next_nop
);
8802 /* Check a floating-point value for validity for a particular machine mode. */
8804 static const char * const float_strings
[] =
8806 /* These are for FLOAT_VAX. */
8807 "1.70141173319264430e+38", /* 2^127 (2^24 - 1) / 2^24 */
8808 "-1.70141173319264430e+38",
8809 "2.93873587705571877e-39", /* 2^-128 */
8810 "-2.93873587705571877e-39",
8811 /* These are for the default broken IEEE mode, which traps
8812 on infinity or denormal numbers. */
8813 "3.402823466385288598117e+38", /* 2^128 (1 - 2^-24) */
8814 "-3.402823466385288598117e+38",
8815 "1.1754943508222875079687e-38", /* 2^-126 */
8816 "-1.1754943508222875079687e-38",
8819 static REAL_VALUE_TYPE float_values
[8];
8820 static int inited_float_values
= 0;
8823 check_float_value (mode
, d
, overflow
)
8824 enum machine_mode mode
;
8826 int overflow ATTRIBUTE_UNUSED
;
8829 if (TARGET_IEEE
|| TARGET_IEEE_CONFORMANT
|| TARGET_IEEE_WITH_INEXACT
)
8832 if (inited_float_values
== 0)
8835 for (i
= 0; i
< 8; i
++)
8836 float_values
[i
] = REAL_VALUE_ATOF (float_strings
[i
], DFmode
);
8838 inited_float_values
= 1;
8844 REAL_VALUE_TYPE
*fvptr
;
8846 if (TARGET_FLOAT_VAX
)
8847 fvptr
= &float_values
[0];
8849 fvptr
= &float_values
[4];
8851 memcpy (&r
, d
, sizeof (REAL_VALUE_TYPE
));
8852 if (REAL_VALUES_LESS (fvptr
[0], r
))
8854 memcpy (d
, &fvptr
[0], sizeof (REAL_VALUE_TYPE
));
8857 else if (REAL_VALUES_LESS (r
, fvptr
[1]))
8859 memcpy (d
, &fvptr
[1], sizeof (REAL_VALUE_TYPE
));
8862 else if (REAL_VALUES_LESS (dconst0
, r
)
8863 && REAL_VALUES_LESS (r
, fvptr
[2]))
8865 memcpy (d
, &dconst0
, sizeof (REAL_VALUE_TYPE
));
8868 else if (REAL_VALUES_LESS (r
, dconst0
)
8869 && REAL_VALUES_LESS (fvptr
[3], r
))
8871 memcpy (d
, &dconst0
, sizeof (REAL_VALUE_TYPE
));
8879 #ifdef OBJECT_FORMAT_ELF
8881 /* Switch to the section to which we should output X. The only thing
8882 special we do here is to honor small data. */
8885 alpha_elf_select_rtx_section (mode
, x
, align
)
8886 enum machine_mode mode
;
8888 unsigned HOST_WIDE_INT align
;
8890 if (TARGET_SMALL_DATA
&& GET_MODE_SIZE (mode
) <= g_switch_value
)
8891 /* ??? Consider using mergable sdata sections. */
8894 default_elf_select_rtx_section (mode
, x
, align
);
8897 #endif /* OBJECT_FORMAT_ELF */
8899 #if TARGET_ABI_OPEN_VMS
8901 /* Return the VMS argument type corresponding to MODE. */
8904 alpha_arg_type (mode
)
8905 enum machine_mode mode
;
8910 return TARGET_FLOAT_VAX
? FF
: FS
;
8912 return TARGET_FLOAT_VAX
? FD
: FT
;
8918 /* Return an rtx for an integer representing the VMS Argument Information
8922 alpha_arg_info_reg_val (cum
)
8923 CUMULATIVE_ARGS cum
;
8925 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
8928 for (i
= 0; i
< 6; i
++)
8929 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
8931 return GEN_INT (regval
);
8934 #include <splay-tree.h>
8936 /* Structure to collect function names for final output
8939 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
8944 enum links_kind kind
;
8947 static splay_tree alpha_links
;
8949 static int mark_alpha_links_node
PARAMS ((splay_tree_node
, void *));
8950 static void mark_alpha_links
PARAMS ((void *));
8951 static int alpha_write_one_linkage
PARAMS ((splay_tree_node
, void *));
8953 /* Protect alpha_links from garbage collection. */
8956 mark_alpha_links_node (node
, data
)
8957 splay_tree_node node
;
8958 void *data ATTRIBUTE_UNUSED
;
8960 struct alpha_links
*links
= (struct alpha_links
*) node
->value
;
8961 ggc_mark_rtx (links
->linkage
);
8966 mark_alpha_links (ptr
)
8969 splay_tree tree
= *(splay_tree
*) ptr
;
8970 splay_tree_foreach (tree
, mark_alpha_links_node
, NULL
);
8973 /* Make (or fake) .linkage entry for function call.
8975 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
8977 Return an SYMBOL_REF rtx for the linkage. */
8980 alpha_need_linkage (name
, is_local
)
8984 splay_tree_node node
;
8985 struct alpha_links
*al
;
8992 /* Is this name already defined? */
8994 node
= splay_tree_lookup (alpha_links
, (splay_tree_key
) name
);
8997 al
= (struct alpha_links
*) node
->value
;
9000 /* Defined here but external assumed. */
9001 if (al
->kind
== KIND_EXTERN
)
9002 al
->kind
= KIND_LOCAL
;
9006 /* Used here but unused assumed. */
9007 if (al
->kind
== KIND_UNUSED
)
9008 al
->kind
= KIND_LOCAL
;
9015 alpha_links
= splay_tree_new ((splay_tree_compare_fn
) strcmp
,
9016 (splay_tree_delete_key_fn
) free
,
9017 (splay_tree_delete_key_fn
) free
);
9018 ggc_add_root (&alpha_links
, 1, 1, mark_alpha_links
);
9021 al
= (struct alpha_links
*) xmalloc (sizeof (struct alpha_links
));
9022 name
= xstrdup (name
);
9024 /* Assume external if no definition. */
9025 al
->kind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
9027 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9028 get_identifier (name
);
9030 /* Construct a SYMBOL_REF for us to call. */
9032 size_t name_len
= strlen (name
);
9033 char *linksym
= alloca (name_len
+ 6);
9035 memcpy (linksym
+ 1, name
, name_len
);
9036 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
9037 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
9038 ggc_alloc_string (linksym
, name_len
+ 5));
9041 splay_tree_insert (alpha_links
, (splay_tree_key
) name
,
9042 (splay_tree_value
) al
);
9048 alpha_write_one_linkage (node
, data
)
9049 splay_tree_node node
;
9052 const char *const name
= (const char *) node
->key
;
9053 struct alpha_links
*links
= (struct alpha_links
*) node
->value
;
9054 FILE *stream
= (FILE *) data
;
9056 if (links
->kind
== KIND_UNUSED
9057 || ! TREE_SYMBOL_REFERENCED (get_identifier (name
)))
9060 fprintf (stream
, "$%s..lk:\n", name
);
9061 if (links
->kind
== KIND_LOCAL
)
9063 /* Local and used, build linkage pair. */
9064 fprintf (stream
, "\t.quad %s..en\n", name
);
9065 fprintf (stream
, "\t.quad %s\n", name
);
9069 /* External and used, request linkage pair. */
9070 fprintf (stream
, "\t.linkage %s\n", name
);
9077 alpha_write_linkage (stream
)
9082 readonly_data_section ();
9083 fprintf (stream
, "\t.align 3\n");
9084 splay_tree_foreach (alpha_links
, alpha_write_one_linkage
, stream
);
9088 /* Given a decl, a section name, and whether the decl initializer
9089 has relocs, choose attributes for the section. */
9091 #define SECTION_VMS_OVERLAY SECTION_FORGET
9092 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9093 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9096 vms_section_type_flags (decl
, name
, reloc
)
9101 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9103 if (decl
&& DECL_ATTRIBUTES (decl
)
9104 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
9105 flags
|= SECTION_VMS_OVERLAY
;
9106 if (decl
&& DECL_ATTRIBUTES (decl
)
9107 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
9108 flags
|= SECTION_VMS_GLOBAL
;
9109 if (decl
&& DECL_ATTRIBUTES (decl
)
9110 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
9111 flags
|= SECTION_VMS_INITIALIZE
;
9116 /* Switch to an arbitrary section NAME with attributes as specified
9117 by FLAGS. ALIGN specifies any known alignment requirements for
9118 the section; 0 if the default should be used. */
9121 vms_asm_named_section (name
, flags
)
9125 fputc ('\n', asm_out_file
);
9126 fprintf (asm_out_file
, ".section\t%s", name
);
9128 if (flags
& SECTION_VMS_OVERLAY
)
9129 fprintf (asm_out_file
, ",OVR");
9130 if (flags
& SECTION_VMS_GLOBAL
)
9131 fprintf (asm_out_file
, ",GBL");
9132 if (flags
& SECTION_VMS_INITIALIZE
)
9133 fprintf (asm_out_file
, ",NOMOD");
9134 if (flags
& SECTION_DEBUG
)
9135 fprintf (asm_out_file
, ",NOWRT");
9137 fputc ('\n', asm_out_file
);
9140 /* Record an element in the table of global constructors. SYMBOL is
9141 a SYMBOL_REF of the function to be called; PRIORITY is a number
9142 between 0 and MAX_INIT_PRIORITY.
9144 Differs from default_ctors_section_asm_out_constructor in that the
9145 width of the .ctors entry is always 64 bits, rather than the 32 bits
9146 used by a normal pointer. */
9149 vms_asm_out_constructor (symbol
, priority
)
9151 int priority ATTRIBUTE_UNUSED
;
9154 assemble_align (BITS_PER_WORD
);
9155 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9159 vms_asm_out_destructor (symbol
, priority
)
9161 int priority ATTRIBUTE_UNUSED
;
9164 assemble_align (BITS_PER_WORD
);
9165 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
9170 alpha_need_linkage (name
, is_local
)
9171 const char *name ATTRIBUTE_UNUSED
;
9172 int is_local ATTRIBUTE_UNUSED
;
9177 #endif /* TARGET_ABI_OPEN_VMS */
9179 #if TARGET_ABI_UNICOSMK
9181 static void unicosmk_output_module_name
PARAMS ((FILE *));
9182 static void unicosmk_output_default_externs
PARAMS ((FILE *));
9183 static void unicosmk_output_dex
PARAMS ((FILE *));
9184 static void unicosmk_output_externs
PARAMS ((FILE *));
9185 static void unicosmk_output_addr_vec
PARAMS ((FILE *, rtx
));
9186 static const char *unicosmk_ssib_name
PARAMS ((void));
9187 static int unicosmk_special_name
PARAMS ((const char *));
9189 /* Define the offset between two registers, one to be eliminated, and the
9190 other its replacement, at the start of a routine. */
9193 unicosmk_initial_elimination_offset (from
, to
)
9199 fixed_size
= alpha_sa_size();
9200 if (fixed_size
!= 0)
9203 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9205 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
9207 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9208 return (ALPHA_ROUND (current_function_outgoing_args_size
)
9209 + ALPHA_ROUND (get_frame_size()));
9210 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
9211 return (ALPHA_ROUND (fixed_size
)
9212 + ALPHA_ROUND (get_frame_size()
9213 + current_function_outgoing_args_size
));
9218 /* Output the module name for .ident and .end directives. We have to strip
9219 directories and add make sure that the module name starts with a letter
9223 unicosmk_output_module_name (file
)
9228 /* Strip directories. */
9230 name
= strrchr (main_input_filename
, '/');
9234 name
= main_input_filename
;
9236 /* CAM only accepts module names that start with a letter or '$'. We
9237 prefix the module name with a '$' if necessary. */
9239 if (!ISALPHA (*name
))
9241 output_clean_symbol_name (file
, name
);
9244 /* Output text that to appear at the beginning of an assembler file. */
9247 unicosmk_asm_file_start (file
)
9252 fputs ("\t.ident\t", file
);
9253 unicosmk_output_module_name (file
);
9254 fputs ("\n\n", file
);
9256 /* The Unicos/Mk assembler uses different register names. Instead of trying
9257 to support them, we simply use micro definitions. */
9259 /* CAM has different register names: rN for the integer register N and fN
9260 for the floating-point register N. Instead of trying to use these in
9261 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9264 for (i
= 0; i
< 32; ++i
)
9265 fprintf (file
, "$%d <- r%d\n", i
, i
);
9267 for (i
= 0; i
< 32; ++i
)
9268 fprintf (file
, "$f%d <- f%d\n", i
, i
);
9272 /* The .align directive fill unused space with zeroes which does not work
9273 in code sections. We define the macro 'gcc@code@align' which uses nops
9274 instead. Note that it assumes that code sections always have the
9275 biggest possible alignment since . refers to the current offset from
9276 the beginning of the section. */
9278 fputs ("\t.macro gcc@code@align n\n", file
);
9279 fputs ("gcc@n@bytes = 1 << n\n", file
);
9280 fputs ("gcc@here = . % gcc@n@bytes\n", file
);
9281 fputs ("\t.if ne, gcc@here, 0\n", file
);
9282 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", file
);
9283 fputs ("\tbis r31,r31,r31\n", file
);
9284 fputs ("\t.endr\n", file
);
9285 fputs ("\t.endif\n", file
);
9286 fputs ("\t.endm gcc@code@align\n\n", file
);
9288 /* Output extern declarations which should always be visible. */
9289 unicosmk_output_default_externs (file
);
9291 /* Open a dummy section. We always need to be inside a section for the
9292 section-switching code to work correctly.
9293 ??? This should be a module id or something like that. I still have to
9294 figure out what the rules for those are. */
9295 fputs ("\n\t.psect\t$SG00000,data\n", file
);
9298 /* Output text to appear at the end of an assembler file. This includes all
9299 pending extern declarations and DEX expressions. */
9302 unicosmk_asm_file_end (file
)
9305 fputs ("\t.endp\n\n", file
);
9307 /* Output all pending externs. */
9309 unicosmk_output_externs (file
);
9311 /* Output dex definitions used for functions whose names conflict with
9314 unicosmk_output_dex (file
);
9316 fputs ("\t.end\t", file
);
9317 unicosmk_output_module_name (file
);
9321 /* Output the definition of a common variable. */
9324 unicosmk_output_common (file
, name
, size
, align
)
9331 printf ("T3E__: common %s\n", name
);
9334 fputs("\t.endp\n\n\t.psect ", file
);
9335 assemble_name(file
, name
);
9336 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
9337 fprintf(file
, "\t.byte\t0:%d\n", size
);
9339 /* Mark the symbol as defined in this module. */
9340 name_tree
= get_identifier (name
);
9341 TREE_ASM_WRITTEN (name_tree
) = 1;
9344 #define SECTION_PUBLIC SECTION_MACH_DEP
9345 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9346 static int current_section_align
;
9349 unicosmk_section_type_flags (decl
, name
, reloc
)
9352 int reloc ATTRIBUTE_UNUSED
;
9354 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
9359 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9361 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9362 if (align_functions_log
> current_section_align
)
9363 current_section_align
= align_functions_log
;
9365 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
9366 flags
|= SECTION_MAIN
;
9369 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
9371 if (TREE_PUBLIC (decl
))
9372 flags
|= SECTION_PUBLIC
;
9377 /* Generate a section name for decl and associate it with the
9381 unicosmk_unique_section (decl
, reloc
)
9383 int reloc ATTRIBUTE_UNUSED
;
9391 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
9392 name
= alpha_strip_name_encoding (name
);
9393 len
= strlen (name
);
9395 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9399 /* It is essential that we prefix the section name here because
9400 otherwise the section names generated for constructors and
9401 destructors confuse collect2. */
9403 string
= alloca (len
+ 6);
9404 sprintf (string
, "code@%s", name
);
9405 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9407 else if (TREE_PUBLIC (decl
))
9408 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
9413 string
= alloca (len
+ 6);
9414 sprintf (string
, "data@%s", name
);
9415 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
9419 /* Switch to an arbitrary section NAME with attributes as specified
9420 by FLAGS. ALIGN specifies any known alignment requirements for
9421 the section; 0 if the default should be used. */
9424 unicosmk_asm_named_section (name
, flags
)
9430 /* Close the previous section. */
9432 fputs ("\t.endp\n\n", asm_out_file
);
9434 /* Find out what kind of section we are opening. */
9436 if (flags
& SECTION_MAIN
)
9437 fputs ("\t.start\tmain\n", asm_out_file
);
9439 if (flags
& SECTION_CODE
)
9441 else if (flags
& SECTION_PUBLIC
)
9446 if (current_section_align
!= 0)
9447 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
9448 current_section_align
, kind
);
9450 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
9454 unicosmk_insert_attributes (decl
, attr_ptr
)
9456 tree
*attr_ptr ATTRIBUTE_UNUSED
;
9459 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
9460 unicosmk_unique_section (decl
, 0);
9463 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9464 in code sections because .align fill unused space with zeroes. */
9467 unicosmk_output_align (file
, align
)
9471 if (inside_function
)
9472 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
9474 fprintf (file
, "\t.align\t%d\n", align
);
9477 /* Add a case vector to the current function's list of deferred case
9478 vectors. Case vectors have to be put into a separate section because CAM
9479 does not allow data definitions in code sections. */
9482 unicosmk_defer_case_vector (lab
, vec
)
9486 struct machine_function
*machine
= cfun
->machine
;
9488 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9489 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
9490 machine
->addr_list
);
9493 /* Output a case vector. */
9496 unicosmk_output_addr_vec (file
, vec
)
9500 rtx lab
= XEXP (vec
, 0);
9501 rtx body
= XEXP (vec
, 1);
9502 int vlen
= XVECLEN (body
, 0);
9505 ASM_OUTPUT_INTERNAL_LABEL (file
, "L", CODE_LABEL_NUMBER (lab
));
9507 for (idx
= 0; idx
< vlen
; idx
++)
9509 ASM_OUTPUT_ADDR_VEC_ELT
9510 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9514 /* Output current function's deferred case vectors. */
9517 unicosmk_output_deferred_case_vectors (file
)
9520 struct machine_function
*machine
= cfun
->machine
;
9523 if (machine
->addr_list
== NULL_RTX
)
9527 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
9528 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
9531 /* Set up the dynamic subprogram information block (DSIB) and update the
9532 frame pointer register ($15) for subroutines which have a frame. If the
9533 subroutine doesn't have a frame, simply increment $15. */
9536 unicosmk_gen_dsib (imaskP
)
9537 unsigned long * imaskP
;
9539 if (alpha_procedure_type
== PT_STACK
)
9541 const char *ssib_name
;
9544 /* Allocate 64 bytes for the DSIB. */
9546 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
9548 emit_insn (gen_blockage ());
9550 /* Save the return address. */
9552 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
9553 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9554 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
9555 (*imaskP
) &= ~(1L << REG_RA
);
9557 /* Save the old frame pointer. */
9559 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
9560 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9561 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
9562 (*imaskP
) &= ~(1L << HARD_FRAME_POINTER_REGNUM
);
9564 emit_insn (gen_blockage ());
9566 /* Store the SSIB pointer. */
9568 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
9569 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
9570 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9572 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
9573 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
9574 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
9576 /* Save the CIW index. */
9578 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
9579 set_mem_alias_set (mem
, alpha_sr_alias_set
);
9580 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
9582 emit_insn (gen_blockage ());
9584 /* Set the new frame pointer. */
9586 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9587 stack_pointer_rtx
, GEN_INT (64))));
9592 /* Increment the frame pointer register to indicate that we do not
9595 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
9596 hard_frame_pointer_rtx
, GEN_INT (1))));
9600 #define SSIB_PREFIX "__SSIB_"
9601 #define SSIB_PREFIX_LEN 7
9603 /* Generate the name of the SSIB section for the current function. */
9606 unicosmk_ssib_name ()
9608 /* This is ok since CAM won't be able to deal with names longer than that
9611 static char name
[256];
9617 x
= DECL_RTL (cfun
->decl
);
9618 if (GET_CODE (x
) != MEM
)
9621 if (GET_CODE (x
) != SYMBOL_REF
)
9623 fnname
= alpha_strip_name_encoding (XSTR (x
, 0));
9625 len
= strlen (fnname
);
9626 if (len
+ SSIB_PREFIX_LEN
> 255)
9627 len
= 255 - SSIB_PREFIX_LEN
;
9629 strcpy (name
, SSIB_PREFIX
);
9630 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
9631 name
[len
+ SSIB_PREFIX_LEN
] = 0;
9636 /* Output the static subroutine information block for the current
9640 unicosmk_output_ssib (file
, fnname
)
9648 struct machine_function
*machine
= cfun
->machine
;
9651 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
9652 unicosmk_ssib_name ());
9654 /* Some required stuff and the function name length. */
9656 len
= strlen (fnname
);
9657 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
9660 ??? We don't do that yet. */
9662 fputs ("\t.quad\t0\n", file
);
9664 /* Function address. */
9666 fputs ("\t.quad\t", file
);
9667 assemble_name (file
, fnname
);
9670 fputs ("\t.quad\t0\n", file
);
9671 fputs ("\t.quad\t0\n", file
);
9674 ??? We do it the same way Cray CC does it but this could be
9677 for( i
= 0; i
< len
; i
++ )
9678 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
9679 if( (len
% 8) == 0 )
9680 fputs ("\t.quad\t0\n", file
);
9682 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
9684 /* All call information words used in the function. */
9686 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
9689 fprintf (file
, "\t.quad\t");
9690 #if HOST_BITS_PER_WIDE_INT == 32
9691 fprintf (file
, HOST_WIDE_INT_PRINT_DOUBLE_HEX
,
9692 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
9694 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (ciw
));
9696 fprintf (file
, "\n");
9700 /* Add a call information word (CIW) to the list of the current function's
9701 CIWs and return its index.
9703 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9706 unicosmk_add_call_info_word (x
)
9710 struct machine_function
*machine
= cfun
->machine
;
9712 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
9713 if (machine
->first_ciw
== NULL_RTX
)
9714 machine
->first_ciw
= node
;
9716 XEXP (machine
->last_ciw
, 1) = node
;
9718 machine
->last_ciw
= node
;
9719 ++machine
->ciw_count
;
9721 return GEN_INT (machine
->ciw_count
9722 + strlen (current_function_name
)/8 + 5);
9725 static char unicosmk_section_buf
[100];
9728 unicosmk_text_section ()
9730 static int count
= 0;
9731 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9733 return unicosmk_section_buf
;
9737 unicosmk_data_section ()
9739 static int count
= 1;
9740 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9742 return unicosmk_section_buf
;
9745 /* The Cray assembler doesn't accept extern declarations for symbols which
9746 are defined in the same file. We have to keep track of all global
9747 symbols which are referenced and/or defined in a source file and output
9748 extern declarations for those which are referenced but not defined at
9751 /* List of identifiers for which an extern declaration might have to be
9754 struct unicosmk_extern_list
9756 struct unicosmk_extern_list
*next
;
9760 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
9762 /* Output extern declarations which are required for every asm file. */
9765 unicosmk_output_default_externs (file
)
9768 static const char *const externs
[] =
9769 { "__T3E_MISMATCH" };
9774 n
= ARRAY_SIZE (externs
);
9776 for (i
= 0; i
< n
; i
++)
9777 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
9780 /* Output extern declarations for global symbols which are have been
9781 referenced but not defined. */
9784 unicosmk_output_externs (file
)
9787 struct unicosmk_extern_list
*p
;
9788 const char *real_name
;
9792 len
= strlen (user_label_prefix
);
9793 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
9795 /* We have to strip the encoding and possibly remove user_label_prefix
9796 from the identifier in order to handle -fleading-underscore and
9797 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9798 real_name
= alpha_strip_name_encoding (p
->name
);
9799 if (len
&& p
->name
[0] == '*'
9800 && !memcmp (real_name
, user_label_prefix
, len
))
9803 name_tree
= get_identifier (real_name
);
9804 if (! TREE_ASM_WRITTEN (name_tree
))
9806 TREE_ASM_WRITTEN (name_tree
) = 1;
9807 fputs ("\t.extern\t", file
);
9808 assemble_name (file
, p
->name
);
9814 /* Record an extern. */
9817 unicosmk_add_extern (name
)
9820 struct unicosmk_extern_list
*p
;
9822 p
= (struct unicosmk_extern_list
*)
9823 xmalloc (sizeof (struct unicosmk_extern_list
));
9824 p
->next
= unicosmk_extern_head
;
9826 unicosmk_extern_head
= p
;
9829 /* The Cray assembler generates incorrect code if identifiers which
9830 conflict with register names are used as instruction operands. We have
9831 to replace such identifiers with DEX expressions. */
9833 /* Structure to collect identifiers which have been replaced by DEX
9836 struct unicosmk_dex
{
9837 struct unicosmk_dex
*next
;
9841 /* List of identifiers which have been replaced by DEX expressions. The DEX
9842 number is determined by the position in the list. */
9844 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
9846 /* The number of elements in the DEX list. */
9848 static int unicosmk_dex_count
= 0;
9850 /* Check if NAME must be replaced by a DEX expression. */
9853 unicosmk_special_name (name
)
9862 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
9868 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
9871 return (name
[2] == '\0'
9872 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
9875 return (ISDIGIT (name
[1]) && name
[2] == '\0');
9879 /* Return the DEX number if X must be replaced by a DEX expression and 0
9883 unicosmk_need_dex (x
)
9886 struct unicosmk_dex
*dex
;
9890 if (GET_CODE (x
) != SYMBOL_REF
)
9894 if (! unicosmk_special_name (name
))
9897 i
= unicosmk_dex_count
;
9898 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9900 if (! strcmp (name
, dex
->name
))
9905 dex
= (struct unicosmk_dex
*) xmalloc (sizeof (struct unicosmk_dex
));
9907 dex
->next
= unicosmk_dex_list
;
9908 unicosmk_dex_list
= dex
;
9910 ++unicosmk_dex_count
;
9911 return unicosmk_dex_count
;
9914 /* Output the DEX definitions for this file. */
9917 unicosmk_output_dex (file
)
9920 struct unicosmk_dex
*dex
;
9923 if (unicosmk_dex_list
== NULL
)
9926 fprintf (file
, "\t.dexstart\n");
9928 i
= unicosmk_dex_count
;
9929 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9931 fprintf (file
, "\tDEX (%d) = ", i
);
9932 assemble_name (file
, dex
->name
);
9937 fprintf (file
, "\t.dexend\n");
9943 unicosmk_output_deferred_case_vectors (file
)
9944 FILE *file ATTRIBUTE_UNUSED
;
9948 unicosmk_gen_dsib (imaskP
)
9949 unsigned long * imaskP ATTRIBUTE_UNUSED
;
9953 unicosmk_output_ssib (file
, fnname
)
9954 FILE * file ATTRIBUTE_UNUSED
;
9955 const char * fnname ATTRIBUTE_UNUSED
;
9959 unicosmk_add_call_info_word (x
)
9960 rtx x ATTRIBUTE_UNUSED
;
9966 unicosmk_need_dex (x
)
9967 rtx x ATTRIBUTE_UNUSED
;
9972 #endif /* TARGET_ABI_UNICOSMK */
9974 #include "gt-alpha.h"