1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
45 #include "integrate.h"
48 #include "target-def.h"
50 #include "langhooks.h"
52 /* Specify which cpu to schedule for. */
54 enum processor_type alpha_cpu
;
55 static const char * const alpha_cpu_name
[] =
60 /* Specify how accurate floating-point traps need to be. */
62 enum alpha_trap_precision alpha_tp
;
64 /* Specify the floating-point rounding mode. */
66 enum alpha_fp_rounding_mode alpha_fprm
;
68 /* Specify which things cause traps. */
70 enum alpha_fp_trap_mode alpha_fptm
;
72 /* Strings decoded into the above options. */
74 const char *alpha_cpu_string
; /* -mcpu= */
75 const char *alpha_tune_string
; /* -mtune= */
76 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
77 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
78 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
79 const char *alpha_mlat_string
; /* -mmemory-latency= */
81 /* Save information from a "cmpxx" operation until the branch or scc is
84 struct alpha_compare alpha_compare
;
86 /* Non-zero if inside of a function, because the Alpha asm can't
87 handle .files inside of functions. */
89 static int inside_function
= FALSE
;
91 /* The number of cycles of latency we should assume on memory reads. */
93 int alpha_memory_latency
= 3;
95 /* Whether the function needs the GP. */
97 static int alpha_function_needs_gp
;
99 /* The alias set for prologue/epilogue register save/restore. */
101 static int alpha_sr_alias_set
;
103 /* The assembler name of the current function. */
105 static const char *alpha_fnname
;
107 /* The next explicit relocation sequence number. */
108 int alpha_next_sequence_number
= 1;
110 /* The literal and gpdisp sequence numbers for this insn, as printed
111 by %# and %* respectively. */
112 int alpha_this_literal_sequence_number
;
113 int alpha_this_gpdisp_sequence_number
;
115 /* Declarations of static functions. */
116 static bool decl_in_text_section
118 static int some_small_symbolic_operand_1
119 PARAMS ((rtx
*, void *));
120 static int split_small_symbolic_operand_1
121 PARAMS ((rtx
*, void *));
122 static bool local_symbol_p
124 static void alpha_set_memflags_1
125 PARAMS ((rtx
, int, int, int));
126 static rtx alpha_emit_set_const_1
127 PARAMS ((rtx
, enum machine_mode
, HOST_WIDE_INT
, int));
128 static void alpha_expand_unaligned_load_words
129 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
130 static void alpha_expand_unaligned_store_words
131 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
132 static void alpha_sa_mask
133 PARAMS ((unsigned long *imaskP
, unsigned long *fmaskP
));
134 static int find_lo_sum
135 PARAMS ((rtx
*, void *));
136 static int alpha_does_function_need_gp
138 static int alpha_ra_ever_killed
140 static const char *get_trap_mode_suffix
142 static const char *get_round_mode_suffix
144 static rtx set_frame_related_p
146 static const char *alpha_lookup_xfloating_lib_func
147 PARAMS ((enum rtx_code
));
148 static int alpha_compute_xfloating_mode_arg
149 PARAMS ((enum rtx_code
, enum alpha_fp_rounding_mode
));
150 static void alpha_emit_xfloating_libcall
151 PARAMS ((const char *, rtx
, rtx
[], int, rtx
));
152 static rtx alpha_emit_xfloating_compare
153 PARAMS ((enum rtx_code
, rtx
, rtx
));
154 static void alpha_output_function_end_prologue
156 static int alpha_adjust_cost
157 PARAMS ((rtx
, rtx
, rtx
, int));
158 static int alpha_issue_rate
160 static int alpha_variable_issue
161 PARAMS ((FILE *, int, rtx
, int));
163 #if TARGET_ABI_UNICOSMK
164 static void alpha_init_machine_status
165 PARAMS ((struct function
*p
));
166 static void alpha_mark_machine_status
167 PARAMS ((struct function
*p
));
168 static void alpha_free_machine_status
169 PARAMS ((struct function
*p
));
172 static void unicosmk_output_deferred_case_vectors
PARAMS ((FILE *));
173 static void unicosmk_gen_dsib
PARAMS ((unsigned long *imaskP
));
174 static void unicosmk_output_ssib
PARAMS ((FILE *, const char *));
175 static int unicosmk_need_dex
PARAMS ((rtx
));
177 /* Get the number of args of a function in one of two ways. */
178 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
179 #define NUM_ARGS current_function_args_info.num_args
181 #define NUM_ARGS current_function_args_info
187 /* Initialize the GCC target structure. */
188 #if TARGET_ABI_OPEN_VMS
189 const struct attribute_spec vms_attribute_table
[];
190 static unsigned int vms_section_type_flags
PARAMS ((tree
, const char *, int));
191 static void vms_asm_named_section
PARAMS ((const char *, unsigned int));
192 static void vms_asm_out_constructor
PARAMS ((rtx
, int));
193 static void vms_asm_out_destructor
PARAMS ((rtx
, int));
194 # undef TARGET_ATTRIBUTE_TABLE
195 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
196 # undef TARGET_SECTION_TYPE_FLAGS
197 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
200 #if TARGET_ABI_UNICOSMK
201 static void unicosmk_asm_named_section
PARAMS ((const char *, unsigned int));
202 static void unicosmk_insert_attributes
PARAMS ((tree
, tree
*));
203 static unsigned int unicosmk_section_type_flags
PARAMS ((tree
, const char *,
205 # undef TARGET_INSERT_ATTRIBUTES
206 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
207 # undef TARGET_SECTION_TYPE_FLAGS
208 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
211 #undef TARGET_ASM_ALIGNED_HI_OP
212 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
213 #undef TARGET_ASM_ALIGNED_DI_OP
214 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
216 /* Default unaligned ops are provided for ELF systems. To get unaligned
217 data for non-ELF systems, we have to turn off auto alignment. */
218 #ifndef OBJECT_FORMAT_ELF
219 #undef TARGET_ASM_UNALIGNED_HI_OP
220 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
221 #undef TARGET_ASM_UNALIGNED_SI_OP
222 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
223 #undef TARGET_ASM_UNALIGNED_DI_OP
224 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
227 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
228 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
230 #undef TARGET_SCHED_ADJUST_COST
231 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
232 #undef TARGET_SCHED_ISSUE_RATE
233 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
234 #undef TARGET_SCHED_VARIABLE_ISSUE
235 #define TARGET_SCHED_VARIABLE_ISSUE alpha_variable_issue
237 struct gcc_target targetm
= TARGET_INITIALIZER
;
239 /* Parse target option strings. */
245 static const struct cpu_table
{
246 const char *const name
;
247 const enum processor_type processor
;
250 #define EV5_MASK (MASK_CPU_EV5)
251 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
252 { "ev4", PROCESSOR_EV4
, 0 },
253 { "ev45", PROCESSOR_EV4
, 0 },
254 { "21064", PROCESSOR_EV4
, 0 },
255 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
256 { "21164", PROCESSOR_EV5
, EV5_MASK
},
257 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
258 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
259 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
260 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
261 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
262 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
263 { "21264", PROCESSOR_EV6
, EV6_MASK
},
264 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
265 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
269 /* Unicos/Mk doesn't have shared libraries. */
270 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
272 warning ("-f%s ignored for Unicos/Mk (not supported)",
273 (flag_pic
> 1) ? "PIC" : "pic");
277 /* On Unicos/Mk, the native compiler consistenly generates /d suffices for
278 floating-point instructions. Make that the default for this target. */
279 if (TARGET_ABI_UNICOSMK
)
280 alpha_fprm
= ALPHA_FPRM_DYN
;
282 alpha_fprm
= ALPHA_FPRM_NORM
;
284 alpha_tp
= ALPHA_TP_PROG
;
285 alpha_fptm
= ALPHA_FPTM_N
;
287 /* We cannot use su and sui qualifiers for conversion instructions on
288 Unicos/Mk. I'm not sure if this is due to assembler or hardware
289 limitations. Right now, we issue a warning if -mieee is specified
290 and then ignore it; eventually, we should either get it right or
291 disable the option altogether. */
295 if (TARGET_ABI_UNICOSMK
)
296 warning ("-mieee not supported on Unicos/Mk");
299 alpha_tp
= ALPHA_TP_INSN
;
300 alpha_fptm
= ALPHA_FPTM_SU
;
304 if (TARGET_IEEE_WITH_INEXACT
)
306 if (TARGET_ABI_UNICOSMK
)
307 warning ("-mieee-with-inexact not supported on Unicos/Mk");
310 alpha_tp
= ALPHA_TP_INSN
;
311 alpha_fptm
= ALPHA_FPTM_SUI
;
317 if (! strcmp (alpha_tp_string
, "p"))
318 alpha_tp
= ALPHA_TP_PROG
;
319 else if (! strcmp (alpha_tp_string
, "f"))
320 alpha_tp
= ALPHA_TP_FUNC
;
321 else if (! strcmp (alpha_tp_string
, "i"))
322 alpha_tp
= ALPHA_TP_INSN
;
324 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string
);
327 if (alpha_fprm_string
)
329 if (! strcmp (alpha_fprm_string
, "n"))
330 alpha_fprm
= ALPHA_FPRM_NORM
;
331 else if (! strcmp (alpha_fprm_string
, "m"))
332 alpha_fprm
= ALPHA_FPRM_MINF
;
333 else if (! strcmp (alpha_fprm_string
, "c"))
334 alpha_fprm
= ALPHA_FPRM_CHOP
;
335 else if (! strcmp (alpha_fprm_string
,"d"))
336 alpha_fprm
= ALPHA_FPRM_DYN
;
338 error ("bad value `%s' for -mfp-rounding-mode switch",
342 if (alpha_fptm_string
)
344 if (strcmp (alpha_fptm_string
, "n") == 0)
345 alpha_fptm
= ALPHA_FPTM_N
;
346 else if (strcmp (alpha_fptm_string
, "u") == 0)
347 alpha_fptm
= ALPHA_FPTM_U
;
348 else if (strcmp (alpha_fptm_string
, "su") == 0)
349 alpha_fptm
= ALPHA_FPTM_SU
;
350 else if (strcmp (alpha_fptm_string
, "sui") == 0)
351 alpha_fptm
= ALPHA_FPTM_SUI
;
353 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string
);
357 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
358 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
360 if (alpha_cpu_string
)
362 for (i
= 0; cpu_table
[i
].name
; i
++)
363 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
365 alpha_cpu
= cpu_table
[i
].processor
;
366 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
367 | MASK_CPU_EV5
| MASK_CPU_EV6
);
368 target_flags
|= cpu_table
[i
].flags
;
371 if (! cpu_table
[i
].name
)
372 error ("bad value `%s' for -mcpu switch", alpha_cpu_string
);
375 if (alpha_tune_string
)
377 for (i
= 0; cpu_table
[i
].name
; i
++)
378 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
380 alpha_cpu
= cpu_table
[i
].processor
;
383 if (! cpu_table
[i
].name
)
384 error ("bad value `%s' for -mcpu switch", alpha_tune_string
);
387 /* Do some sanity checks on the above options. */
389 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
391 warning ("trap mode not supported on Unicos/Mk");
392 alpha_fptm
= ALPHA_FPTM_N
;
395 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
396 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
398 warning ("fp software completion requires -mtrap-precision=i");
399 alpha_tp
= ALPHA_TP_INSN
;
404 /* Except for EV6 pass 1 (not released), we always have precise
405 arithmetic traps. Which means we can do software completion
406 without minding trap shadows. */
407 alpha_tp
= ALPHA_TP_PROG
;
410 if (TARGET_FLOAT_VAX
)
412 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
414 warning ("rounding mode not supported for VAX floats");
415 alpha_fprm
= ALPHA_FPRM_NORM
;
417 if (alpha_fptm
== ALPHA_FPTM_SUI
)
419 warning ("trap mode not supported for VAX floats");
420 alpha_fptm
= ALPHA_FPTM_SU
;
428 if (!alpha_mlat_string
)
429 alpha_mlat_string
= "L1";
431 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
432 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
434 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
435 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
436 && alpha_mlat_string
[2] == '\0')
438 static int const cache_latency
[][4] =
440 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
441 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
442 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
445 lat
= alpha_mlat_string
[1] - '0';
446 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
448 warning ("L%d cache latency unknown for %s",
449 lat
, alpha_cpu_name
[alpha_cpu
]);
453 lat
= cache_latency
[alpha_cpu
][lat
-1];
455 else if (! strcmp (alpha_mlat_string
, "main"))
457 /* Most current memories have about 370ns latency. This is
458 a reasonable guess for a fast cpu. */
463 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string
);
467 alpha_memory_latency
= lat
;
470 /* Default the definition of "small data" to 8 bytes. */
474 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
476 target_flags
|= MASK_SMALL_DATA
;
477 else if (flag_pic
== 2)
478 target_flags
&= ~MASK_SMALL_DATA
;
480 /* Align labels and loops for optimal branching. */
481 /* ??? Kludge these by not doing anything if we don't optimize and also if
482 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
483 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
485 if (align_loops
<= 0)
487 if (align_jumps
<= 0)
490 if (align_functions
<= 0)
491 align_functions
= 16;
493 /* Acquire a unique set number for our register saves and restores. */
494 alpha_sr_alias_set
= new_alias_set ();
496 /* Register variables and functions with the garbage collector. */
498 #if TARGET_ABI_UNICOSMK
499 /* Set up function hooks. */
500 init_machine_status
= alpha_init_machine_status
;
501 mark_machine_status
= alpha_mark_machine_status
;
502 free_machine_status
= alpha_free_machine_status
;
506 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
514 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
516 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
522 /* Returns 1 if OP is either the constant zero or a register. If a
523 register, it must be in the proper mode unless MODE is VOIDmode. */
526 reg_or_0_operand (op
, mode
)
528 enum machine_mode mode
;
530 return op
== const0_rtx
|| register_operand (op
, mode
);
533 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
537 reg_or_6bit_operand (op
, mode
)
539 enum machine_mode mode
;
541 return ((GET_CODE (op
) == CONST_INT
542 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64)
543 || register_operand (op
, mode
));
547 /* Return 1 if OP is an 8-bit constant or any register. */
550 reg_or_8bit_operand (op
, mode
)
552 enum machine_mode mode
;
554 return ((GET_CODE (op
) == CONST_INT
555 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
556 || register_operand (op
, mode
));
559 /* Return 1 if OP is an 8-bit constant. */
562 cint8_operand (op
, mode
)
564 enum machine_mode mode ATTRIBUTE_UNUSED
;
566 return ((GET_CODE (op
) == CONST_INT
567 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100));
570 /* Return 1 if the operand is a valid second operand to an add insn. */
573 add_operand (op
, mode
)
575 enum machine_mode mode
;
577 if (GET_CODE (op
) == CONST_INT
)
578 /* Constraints I, J, O and P are covered by K. */
579 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K')
580 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
582 return register_operand (op
, mode
);
585 /* Return 1 if the operand is a valid second operand to a sign-extending
589 sext_add_operand (op
, mode
)
591 enum machine_mode mode
;
593 if (GET_CODE (op
) == CONST_INT
)
594 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
595 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'));
597 return reg_not_elim_operand (op
, mode
);
600 /* Return 1 if OP is the constant 4 or 8. */
603 const48_operand (op
, mode
)
605 enum machine_mode mode ATTRIBUTE_UNUSED
;
607 return (GET_CODE (op
) == CONST_INT
608 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
611 /* Return 1 if OP is a valid first operand to an AND insn. */
614 and_operand (op
, mode
)
616 enum machine_mode mode
;
618 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
619 return (zap_mask (CONST_DOUBLE_LOW (op
))
620 && zap_mask (CONST_DOUBLE_HIGH (op
)));
622 if (GET_CODE (op
) == CONST_INT
)
623 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
624 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
625 || zap_mask (INTVAL (op
)));
627 return register_operand (op
, mode
);
630 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
633 or_operand (op
, mode
)
635 enum machine_mode mode
;
637 if (GET_CODE (op
) == CONST_INT
)
638 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
639 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100);
641 return register_operand (op
, mode
);
644 /* Return 1 if OP is a constant that is the width, in bits, of an integral
645 mode smaller than DImode. */
648 mode_width_operand (op
, mode
)
650 enum machine_mode mode ATTRIBUTE_UNUSED
;
652 return (GET_CODE (op
) == CONST_INT
653 && (INTVAL (op
) == 8 || INTVAL (op
) == 16
654 || INTVAL (op
) == 32 || INTVAL (op
) == 64));
657 /* Return 1 if OP is a constant that is the width of an integral machine mode
658 smaller than an integer. */
661 mode_mask_operand (op
, mode
)
663 enum machine_mode mode ATTRIBUTE_UNUSED
;
665 #if HOST_BITS_PER_WIDE_INT == 32
666 if (GET_CODE (op
) == CONST_DOUBLE
)
667 return (CONST_DOUBLE_LOW (op
) == -1
668 && (CONST_DOUBLE_HIGH (op
) == -1
669 || CONST_DOUBLE_HIGH (op
) == 0));
671 if (GET_CODE (op
) == CONST_DOUBLE
)
672 return (CONST_DOUBLE_LOW (op
) == -1 && CONST_DOUBLE_HIGH (op
) == 0);
675 return (GET_CODE (op
) == CONST_INT
676 && (INTVAL (op
) == 0xff
677 || INTVAL (op
) == 0xffff
678 || INTVAL (op
) == (HOST_WIDE_INT
)0xffffffff
679 #if HOST_BITS_PER_WIDE_INT == 64
685 /* Return 1 if OP is a multiple of 8 less than 64. */
688 mul8_operand (op
, mode
)
690 enum machine_mode mode ATTRIBUTE_UNUSED
;
692 return (GET_CODE (op
) == CONST_INT
693 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
694 && (INTVAL (op
) & 7) == 0);
697 /* Return 1 if OP is the constant zero in floating-point. */
700 fp0_operand (op
, mode
)
702 enum machine_mode mode
;
704 return (GET_MODE (op
) == mode
705 && GET_MODE_CLASS (mode
) == MODE_FLOAT
&& op
== CONST0_RTX (mode
));
708 /* Return 1 if OP is the floating-point constant zero or a register. */
711 reg_or_fp0_operand (op
, mode
)
713 enum machine_mode mode
;
715 return fp0_operand (op
, mode
) || register_operand (op
, mode
);
718 /* Return 1 if OP is a hard floating-point register. */
721 hard_fp_register_operand (op
, mode
)
723 enum machine_mode mode
;
725 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
728 if (GET_CODE (op
) == SUBREG
)
729 op
= SUBREG_REG (op
);
730 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == FLOAT_REGS
;
733 /* Return 1 if OP is a hard general register. */
736 hard_int_register_operand (op
, mode
)
738 enum machine_mode mode
;
740 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
743 if (GET_CODE (op
) == SUBREG
)
744 op
= SUBREG_REG (op
);
745 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
;
748 /* Return 1 if OP is a register or a constant integer. */
752 reg_or_cint_operand (op
, mode
)
754 enum machine_mode mode
;
756 return (GET_CODE (op
) == CONST_INT
757 || register_operand (op
, mode
));
760 /* Return 1 if OP is something that can be reloaded into a register;
761 if it is a MEM, it need not be valid. */
764 some_operand (op
, mode
)
766 enum machine_mode mode
;
768 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
771 switch (GET_CODE (op
))
773 case REG
: case MEM
: case CONST_DOUBLE
: case CONST_INT
: case LABEL_REF
:
774 case SYMBOL_REF
: case CONST
: case HIGH
:
778 return some_operand (SUBREG_REG (op
), VOIDmode
);
787 /* Likewise, but don't accept constants. */
790 some_ni_operand (op
, mode
)
792 enum machine_mode mode
;
794 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
797 if (GET_CODE (op
) == SUBREG
)
798 op
= SUBREG_REG (op
);
800 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == MEM
);
803 /* Return 1 if OP is a valid operand for the source of a move insn. */
806 input_operand (op
, mode
)
808 enum machine_mode mode
;
810 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
813 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
816 switch (GET_CODE (op
))
821 if (TARGET_EXPLICIT_RELOCS
)
823 /* We don't split symbolic operands into something unintelligable
824 until after reload, but we do not wish non-small, non-global
825 symbolic operands to be reconstructed from their high/lo_sum
827 return (small_symbolic_operand (op
, mode
)
828 || global_symbolic_operand (op
, mode
));
831 /* This handles both the Windows/NT and OSF cases. */
832 return mode
== ptr_mode
|| mode
== DImode
;
835 return (TARGET_EXPLICIT_RELOCS
836 && local_symbolic_operand (XEXP (op
, 0), mode
));
843 if (register_operand (op
, mode
))
845 /* ... fall through ... */
847 return ((TARGET_BWX
|| (mode
!= HImode
&& mode
!= QImode
))
848 && general_operand (op
, mode
));
851 return GET_MODE_CLASS (mode
) == MODE_FLOAT
&& op
== CONST0_RTX (mode
);
854 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
866 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
867 file, and in the same section as the current function. */
870 current_file_function_operand (op
, mode
)
872 enum machine_mode mode ATTRIBUTE_UNUSED
;
874 if (GET_CODE (op
) != SYMBOL_REF
)
877 /* Easy test for recursion. */
878 if (op
== XEXP (DECL_RTL (current_function_decl
), 0))
881 /* Otherwise, we need the DECL for the SYMBOL_REF, which we can't get.
882 So SYMBOL_REF_FLAG has been declared to imply that the function is
883 in the default text section. So we must also check that the current
884 function is also in the text section. */
885 if (SYMBOL_REF_FLAG (op
) && decl_in_text_section (current_function_decl
))
891 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
894 direct_call_operand (op
, mode
)
896 enum machine_mode mode
;
898 /* Must be defined in this file. */
899 if (! current_file_function_operand (op
, mode
))
902 /* If profiling is implemented via linker tricks, we can't jump
903 to the nogp alternate entry point. */
904 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
905 but is approximately correct for the OSF ABIs. Don't know
906 what to do for VMS, NT, or UMK. */
907 if (! TARGET_PROFILING_NEEDS_GP
908 && ! current_function_profile
)
914 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
915 a variable known to be defined in this file. */
921 const char *str
= XSTR (op
, 0);
923 /* ??? SYMBOL_REF_FLAG is set for local function symbols, but we
924 run into problems with the rtl inliner in that the symbol was
925 once external, but is local after inlining, which results in
926 unrecognizable insns. */
928 return (CONSTANT_POOL_ADDRESS_P (op
)
929 /* If @, then ENCODE_SECTION_INFO sez it's local. */
931 /* If *$, then ASM_GENERATE_INTERNAL_LABEL sez it's local. */
932 || (str
[0] == '*' && str
[1] == '$'));
936 local_symbolic_operand (op
, mode
)
938 enum machine_mode mode
;
940 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
943 if (GET_CODE (op
) == LABEL_REF
)
946 if (GET_CODE (op
) == CONST
947 && GET_CODE (XEXP (op
, 0)) == PLUS
948 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
949 op
= XEXP (XEXP (op
, 0), 0);
951 if (GET_CODE (op
) != SYMBOL_REF
)
954 return local_symbol_p (op
);
957 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
958 known to be defined in this file in the small data area. */
961 small_symbolic_operand (op
, mode
)
963 enum machine_mode mode ATTRIBUTE_UNUSED
;
967 if (! TARGET_SMALL_DATA
)
970 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
973 if (GET_CODE (op
) == CONST
974 && GET_CODE (XEXP (op
, 0)) == PLUS
975 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
976 op
= XEXP (XEXP (op
, 0), 0);
978 if (GET_CODE (op
) != SYMBOL_REF
)
981 if (CONSTANT_POOL_ADDRESS_P (op
))
982 return GET_MODE_SIZE (get_pool_mode (op
)) <= (unsigned) g_switch_value
;
986 return str
[0] == '@' && str
[1] == 's';
990 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
991 not known (or known not) to be defined in this file. */
994 global_symbolic_operand (op
, mode
)
996 enum machine_mode mode
;
998 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1001 if (GET_CODE (op
) == CONST
1002 && GET_CODE (XEXP (op
, 0)) == PLUS
1003 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1004 op
= XEXP (XEXP (op
, 0), 0);
1006 if (GET_CODE (op
) != SYMBOL_REF
)
1009 return ! local_symbol_p (op
);
1012 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
1015 call_operand (op
, mode
)
1017 enum machine_mode mode
;
1022 if (GET_CODE (op
) == REG
)
1026 /* Disallow virtual registers to cope with pathalogical test cases
1027 such as compile/930117-1.c in which the virtual reg decomposes
1028 to the frame pointer. Which is a hard reg that is not $27. */
1029 return (REGNO (op
) == 27 || REGNO (op
) > LAST_VIRTUAL_REGISTER
);
1034 if (TARGET_ABI_UNICOSMK
)
1036 if (GET_CODE (op
) == SYMBOL_REF
)
1042 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1043 possibly with an offset. */
1046 symbolic_operand (op
, mode
)
1048 enum machine_mode mode
;
1050 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1052 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1054 if (GET_CODE (op
) == CONST
1055 && GET_CODE (XEXP (op
,0)) == PLUS
1056 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1057 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1062 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1063 comparisons are valid in which insn. */
1066 alpha_comparison_operator (op
, mode
)
1068 enum machine_mode mode
;
1070 enum rtx_code code
= GET_CODE (op
);
1072 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1075 return (code
== EQ
|| code
== LE
|| code
== LT
1076 || code
== LEU
|| code
== LTU
);
1079 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1080 Here we know which comparisons are valid in which insn. */
1083 alpha_zero_comparison_operator (op
, mode
)
1085 enum machine_mode mode
;
1087 enum rtx_code code
= GET_CODE (op
);
1089 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1092 return (code
== EQ
|| code
== NE
|| code
== LE
|| code
== LT
1093 || code
== LEU
|| code
== LTU
);
1096 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1099 alpha_swapped_comparison_operator (op
, mode
)
1101 enum machine_mode mode
;
1103 enum rtx_code code
= GET_CODE (op
);
1105 if ((mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1106 || GET_RTX_CLASS (code
) != '<')
1109 code
= swap_condition (code
);
1110 return (code
== EQ
|| code
== LE
|| code
== LT
1111 || code
== LEU
|| code
== LTU
);
1114 /* Return 1 if OP is a signed comparison operation. */
1117 signed_comparison_operator (op
, mode
)
1119 enum machine_mode mode ATTRIBUTE_UNUSED
;
1121 enum rtx_code code
= GET_CODE (op
);
1123 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1126 return (code
== EQ
|| code
== NE
1127 || code
== LE
|| code
== LT
1128 || code
== GE
|| code
== GT
);
1131 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1132 Here we know which comparisons are valid in which insn. */
1135 alpha_fp_comparison_operator (op
, mode
)
1137 enum machine_mode mode
;
1139 enum rtx_code code
= GET_CODE (op
);
1141 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1144 return (code
== EQ
|| code
== LE
|| code
== LT
|| code
== UNORDERED
);
1147 /* Return 1 if this is a divide or modulus operator. */
1150 divmod_operator (op
, mode
)
1152 enum machine_mode mode ATTRIBUTE_UNUSED
;
1154 switch (GET_CODE (op
))
1156 case DIV
: case MOD
: case UDIV
: case UMOD
:
1166 /* Return 1 if this memory address is a known aligned register plus
1167 a constant. It must be a valid address. This means that we can do
1168 this as an aligned reference plus some offset.
1170 Take into account what reload will do. */
1173 aligned_memory_operand (op
, mode
)
1175 enum machine_mode mode
;
1179 if (reload_in_progress
)
1182 if (GET_CODE (tmp
) == SUBREG
)
1183 tmp
= SUBREG_REG (tmp
);
1184 if (GET_CODE (tmp
) == REG
1185 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1187 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1193 if (GET_CODE (op
) != MEM
1194 || GET_MODE (op
) != mode
)
1198 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1199 sorts of constructs. Dig for the real base register. */
1200 if (reload_in_progress
1201 && GET_CODE (op
) == PLUS
1202 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1203 base
= XEXP (XEXP (op
, 0), 0);
1206 if (! memory_address_p (mode
, op
))
1208 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1211 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) >= 32);
1214 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1217 unaligned_memory_operand (op
, mode
)
1219 enum machine_mode mode
;
1223 if (reload_in_progress
)
1226 if (GET_CODE (tmp
) == SUBREG
)
1227 tmp
= SUBREG_REG (tmp
);
1228 if (GET_CODE (tmp
) == REG
1229 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1231 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1237 if (GET_CODE (op
) != MEM
1238 || GET_MODE (op
) != mode
)
1242 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1243 sorts of constructs. Dig for the real base register. */
1244 if (reload_in_progress
1245 && GET_CODE (op
) == PLUS
1246 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1247 base
= XEXP (XEXP (op
, 0), 0);
1250 if (! memory_address_p (mode
, op
))
1252 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1255 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) < 32);
1258 /* Return 1 if OP is either a register or an unaligned memory location. */
1261 reg_or_unaligned_mem_operand (op
, mode
)
1263 enum machine_mode mode
;
1265 return register_operand (op
, mode
) || unaligned_memory_operand (op
, mode
);
1268 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1271 any_memory_operand (op
, mode
)
1273 enum machine_mode mode ATTRIBUTE_UNUSED
;
1275 return (GET_CODE (op
) == MEM
1276 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
1277 || (reload_in_progress
&& GET_CODE (op
) == REG
1278 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1279 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
1280 && GET_CODE (SUBREG_REG (op
)) == REG
1281 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
1284 /* Returns 1 if OP is not an eliminable register.
1286 This exists to cure a pathological abort in the s8addq (et al) patterns,
1288 long foo () { long t; bar(); return (long) &t * 26107; }
1290 which run afoul of a hack in reload to cure a (presumably) similar
1291 problem with lea-type instructions on other targets. But there is
1292 one of us and many of them, so work around the problem by selectively
1293 preventing combine from making the optimization. */
1296 reg_not_elim_operand (op
, mode
)
1298 enum machine_mode mode
;
1301 if (GET_CODE (op
) == SUBREG
)
1302 inner
= SUBREG_REG (op
);
1303 if (inner
== frame_pointer_rtx
|| inner
== arg_pointer_rtx
)
1306 return register_operand (op
, mode
);
1309 /* Return 1 is OP is a memory location that is not a reference (using
1310 an AND) to an unaligned location. Take into account what reload
1314 normal_memory_operand (op
, mode
)
1316 enum machine_mode mode ATTRIBUTE_UNUSED
;
1318 if (reload_in_progress
)
1321 if (GET_CODE (tmp
) == SUBREG
)
1322 tmp
= SUBREG_REG (tmp
);
1323 if (GET_CODE (tmp
) == REG
1324 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1326 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1328 /* This may not have been assigned an equivalent address if it will
1329 be eliminated. In that case, it doesn't matter what we do. */
1335 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) != AND
;
1338 /* Accept a register, but not a subreg of any kind. This allows us to
1339 avoid pathological cases in reload wrt data movement common in
1340 int->fp conversion. */
1343 reg_no_subreg_operand (op
, mode
)
1345 enum machine_mode mode
;
1347 if (GET_CODE (op
) != REG
)
1349 return register_operand (op
, mode
);
1352 /* Recognize an addition operation that includes a constant. Used to
1353 convince reload to canonize (plus (plus reg c1) c2) during register
1357 addition_operation (op
, mode
)
1359 enum machine_mode mode
;
1361 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1363 if (GET_CODE (op
) == PLUS
1364 && register_operand (XEXP (op
, 0), mode
)
1365 && GET_CODE (XEXP (op
, 1)) == CONST_INT
1366 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op
, 1)), 'K'))
1371 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1372 the range defined for C in [I-P]. */
1375 alpha_const_ok_for_letter_p (value
, c
)
1376 HOST_WIDE_INT value
;
1382 /* An unsigned 8 bit constant. */
1383 return (unsigned HOST_WIDE_INT
) value
< 0x100;
1385 /* The constant zero. */
1388 /* A signed 16 bit constant. */
1389 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
1391 /* A shifted signed 16 bit constant appropriate for LDAH. */
1392 return ((value
& 0xffff) == 0
1393 && ((value
) >> 31 == -1 || value
>> 31 == 0));
1395 /* A constant that can be AND'ed with using a ZAP insn. */
1396 return zap_mask (value
);
1398 /* A complemented unsigned 8 bit constant. */
1399 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
1401 /* A negated unsigned 8 bit constant. */
1402 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
1404 /* The constant 1, 2 or 3. */
1405 return value
== 1 || value
== 2 || value
== 3;
1412 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1413 matches for C in [GH]. */
1416 alpha_const_double_ok_for_letter_p (value
, c
)
1423 /* The floating point zero constant. */
1424 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
1425 && value
== CONST0_RTX (GET_MODE (value
)));
1428 /* A valid operand of a ZAP insn. */
1429 return (GET_MODE (value
) == VOIDmode
1430 && zap_mask (CONST_DOUBLE_LOW (value
))
1431 && zap_mask (CONST_DOUBLE_HIGH (value
)));
1438 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1442 alpha_extra_constraint (value
, c
)
1449 return normal_memory_operand (value
, VOIDmode
);
1451 return direct_call_operand (value
, Pmode
);
1453 return (GET_CODE (value
) == CONST_INT
1454 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
1456 return GET_CODE (value
) == HIGH
;
1458 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
1465 /* Return 1 if this function can directly return via $26. */
1470 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
1472 && alpha_sa_size () == 0
1473 && get_frame_size () == 0
1474 && current_function_outgoing_args_size
== 0
1475 && current_function_pretend_args_size
== 0);
1478 /* Return the ADDR_VEC associated with a tablejump insn. */
1481 alpha_tablejump_addr_vec (insn
)
1486 tmp
= JUMP_LABEL (insn
);
1489 tmp
= NEXT_INSN (tmp
);
1492 if (GET_CODE (tmp
) == JUMP_INSN
1493 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
1494 return PATTERN (tmp
);
1498 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1501 alpha_tablejump_best_label (insn
)
1504 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
1505 rtx best_label
= NULL_RTX
;
1507 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1508 there for edge frequency counts from profile data. */
1512 int n_labels
= XVECLEN (jump_table
, 1);
1513 int best_count
= -1;
1516 for (i
= 0; i
< n_labels
; i
++)
1520 for (j
= i
+ 1; j
< n_labels
; j
++)
1521 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
1522 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
1525 if (count
> best_count
)
1526 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
1530 return best_label
? best_label
: const0_rtx
;
1533 /* Return true if the function DECL will be placed in the default text
1535 /* ??? Ideally we'd be able to always move from a SYMBOL_REF back to the
1536 decl, as that would allow us to determine if two functions are in the
1537 same section, which is what we really want to know. */
1540 decl_in_text_section (decl
)
1543 return (DECL_SECTION_NAME (decl
) == NULL_TREE
1544 && ! (flag_function_sections
1545 || (targetm
.have_named_sections
1546 && DECL_ONE_ONLY (decl
))));
1549 /* If we are referencing a function that is static, make the SYMBOL_REF
1550 special. We use this to see indicate we can branch to this function
1551 without setting PV or restoring GP.
1553 If this is a variable that is known to be defined locally, add "@v"
1554 to the name. If in addition the variable is to go in .sdata/.sbss,
1555 then add "@s" instead. */
1558 alpha_encode_section_info (decl
, first
)
1560 int first ATTRIBUTE_UNUSED
;
1562 const char *symbol_str
;
1563 bool is_local
, is_small
;
1565 if (TREE_CODE (decl
) == FUNCTION_DECL
)
1567 /* We mark public functions once they are emitted; otherwise we
1568 don't know that they exist in this unit of translation. */
1569 if (TREE_PUBLIC (decl
))
1572 /* Do not mark functions that are not in .text; otherwise we
1573 don't know that they are near enough for a direct branch. */
1574 if (! decl_in_text_section (decl
))
1577 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl
), 0)) = 1;
1581 /* Early out if we're not going to do anything with this data. */
1582 if (! TARGET_EXPLICIT_RELOCS
)
1585 /* Careful not to prod global register variables. */
1586 if (TREE_CODE (decl
) != VAR_DECL
1587 || GET_CODE (DECL_RTL (decl
)) != MEM
1588 || GET_CODE (XEXP (DECL_RTL (decl
), 0)) != SYMBOL_REF
)
1591 symbol_str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
1593 /* A variable is considered "local" if it is defined in this module. */
1595 /* Local binding occurs for any non-default visibility. */
1596 if (MODULE_LOCAL_P (decl
))
1598 /* Otherwise, variables defined outside this object may not be local. */
1599 else if (DECL_EXTERNAL (decl
))
1601 /* Linkonce and weak data is never local. */
1602 else if (DECL_ONE_ONLY (decl
) || DECL_WEAK (decl
))
1604 /* Static variables are always local. */
1605 else if (! TREE_PUBLIC (decl
))
1607 /* If PIC, then assume that any global name can be overridden by
1608 symbols resolved from other modules. */
1611 /* Uninitialized COMMON variable may be unified with symbols
1612 resolved from other modules. */
1613 else if (DECL_COMMON (decl
)
1614 && (DECL_INITIAL (decl
) == NULL
1615 || DECL_INITIAL (decl
) == error_mark_node
))
1617 /* Otherwise we're left with initialized (or non-common) global data
1618 which is of necessity defined locally. */
1622 /* Determine if DECL will wind up in .sdata/.sbss. */
1625 if (DECL_SECTION_NAME (decl
))
1627 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
1628 if (strcmp (section
, ".sdata") == 0
1629 || strcmp (section
, ".sbss") == 0)
1634 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
1636 /* If the variable has already been defined in the output file, then it
1637 is too late to put it in sdata if it wasn't put there in the first
1638 place. The test is here rather than above, because if it is already
1639 in sdata, then it can stay there. */
1641 if (TREE_ASM_WRITTEN (decl
))
1644 /* If this is an incomplete type with size 0, then we can't put it in
1645 sdata because it might be too big when completed. */
1646 else if (size
> 0 && size
<= g_switch_value
)
1650 /* Finally, encode this into the symbol string. */
1657 if (symbol_str
[0] == '@')
1659 if (symbol_str
[1] == (is_small
? 's' : 'v'))
1664 len
= strlen (symbol_str
) + 1;
1665 newstr
= alloca (len
+ 2);
1668 newstr
[1] = (is_small
? 's' : 'v');
1669 memcpy (newstr
+ 2, symbol_str
, len
);
1671 string
= ggc_alloc_string (newstr
, len
+ 2 - 1);
1672 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = string
;
1674 else if (symbol_str
[0] == '@')
1678 /* legitimate_address_p recognizes an RTL expression that is a valid
1679 memory address for an instruction. The MODE argument is the
1680 machine mode for the MEM expression that wants to use this address.
1682 For Alpha, we have either a constant address or the sum of a
1683 register and a constant address, or just a register. For DImode,
1684 any of those forms can be surrounded with an AND that clear the
1685 low-order three bits; this is an "unaligned" access. */
1688 alpha_legitimate_address_p (mode
, x
, strict
)
1689 enum machine_mode mode
;
1693 /* If this is an ldq_u type address, discard the outer AND. */
1695 && GET_CODE (x
) == AND
1696 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1697 && INTVAL (XEXP (x
, 1)) == -8)
1700 /* Discard non-paradoxical subregs. */
1701 if (GET_CODE (x
) == SUBREG
1702 && (GET_MODE_SIZE (GET_MODE (x
))
1703 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1706 /* Unadorned general registers are valid. */
1709 ? STRICT_REG_OK_FOR_BASE_P (x
)
1710 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
1713 /* Constant addresses (i.e. +/- 32k) are valid. */
1714 if (CONSTANT_ADDRESS_P (x
))
1717 /* Register plus a small constant offset is valid. */
1718 if (GET_CODE (x
) == PLUS
)
1720 rtx ofs
= XEXP (x
, 1);
1723 /* Discard non-paradoxical subregs. */
1724 if (GET_CODE (x
) == SUBREG
1725 && (GET_MODE_SIZE (GET_MODE (x
))
1726 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1732 && NONSTRICT_REG_OK_FP_BASE_P (x
)
1733 && GET_CODE (ofs
) == CONST_INT
)
1736 ? STRICT_REG_OK_FOR_BASE_P (x
)
1737 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
1738 && CONSTANT_ADDRESS_P (ofs
))
1741 else if (GET_CODE (x
) == ADDRESSOF
1742 && GET_CODE (ofs
) == CONST_INT
)
1746 /* If we're managing explicit relocations, LO_SUM is valid, as
1747 are small data symbols. */
1748 else if (TARGET_EXPLICIT_RELOCS
)
1750 if (small_symbolic_operand (x
, Pmode
))
1753 if (GET_CODE (x
) == LO_SUM
)
1755 rtx ofs
= XEXP (x
, 1);
1758 /* Discard non-paradoxical subregs. */
1759 if (GET_CODE (x
) == SUBREG
1760 && (GET_MODE_SIZE (GET_MODE (x
))
1761 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1764 /* Must have a valid base register. */
1767 ? STRICT_REG_OK_FOR_BASE_P (x
)
1768 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
1771 /* The symbol must be local. */
1772 if (local_symbolic_operand (ofs
, Pmode
))
1780 /* Try machine-dependent ways of modifying an illegitimate address
1781 to be legitimate. If we find one, return the new, valid address. */
1784 alpha_legitimize_address (x
, scratch
, mode
)
1787 enum machine_mode mode ATTRIBUTE_UNUSED
;
1789 HOST_WIDE_INT addend
;
1791 /* If the address is (plus reg const_int) and the CONST_INT is not a
1792 valid offset, compute the high part of the constant and add it to
1793 the register. Then our address is (plus temp low-part-const). */
1794 if (GET_CODE (x
) == PLUS
1795 && GET_CODE (XEXP (x
, 0)) == REG
1796 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1797 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
1799 addend
= INTVAL (XEXP (x
, 1));
1804 /* If the address is (const (plus FOO const_int)), find the low-order
1805 part of the CONST_INT. Then load FOO plus any high-order part of the
1806 CONST_INT into a register. Our address is (plus reg low-part-const).
1807 This is done to reduce the number of GOT entries. */
1809 && GET_CODE (x
) == CONST
1810 && GET_CODE (XEXP (x
, 0)) == PLUS
1811 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
1813 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
1814 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
1818 /* If we have a (plus reg const), emit the load as in (2), then add
1819 the two registers, and finally generate (plus reg low-part-const) as
1822 && GET_CODE (x
) == PLUS
1823 && GET_CODE (XEXP (x
, 0)) == REG
1824 && GET_CODE (XEXP (x
, 1)) == CONST
1825 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
1826 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
1828 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
1829 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
1830 XEXP (XEXP (XEXP (x
, 1), 0), 0),
1831 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1835 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1836 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
1838 if (local_symbolic_operand (x
, Pmode
))
1840 if (small_symbolic_operand (x
, Pmode
))
1844 if (!no_new_pseudos
)
1845 scratch
= gen_reg_rtx (Pmode
);
1846 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
1847 gen_rtx_HIGH (Pmode
, x
)));
1848 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
1857 HOST_WIDE_INT low
, high
;
1859 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
1861 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1865 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
1866 (no_new_pseudos
? scratch
: NULL_RTX
),
1867 1, OPTAB_LIB_WIDEN
);
1869 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
1870 (no_new_pseudos
? scratch
: NULL_RTX
),
1871 1, OPTAB_LIB_WIDEN
);
1873 return plus_constant (x
, low
);
1877 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1878 small symbolic operand until after reload. At which point we need
1879 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1880 so that sched2 has the proper dependency information. */
1883 some_small_symbolic_operand (x
, mode
)
1885 enum machine_mode mode ATTRIBUTE_UNUSED
;
1887 return for_each_rtx (&x
, some_small_symbolic_operand_1
, NULL
);
1891 some_small_symbolic_operand_1 (px
, data
)
1893 void *data ATTRIBUTE_UNUSED
;
1897 /* Don't re-split. */
1898 if (GET_CODE (x
) == LO_SUM
)
1901 return small_symbolic_operand (x
, Pmode
) != 0;
1905 split_small_symbolic_operand (x
)
1909 for_each_rtx (&x
, split_small_symbolic_operand_1
, NULL
);
1914 split_small_symbolic_operand_1 (px
, data
)
1916 void *data ATTRIBUTE_UNUSED
;
1920 /* Don't re-split. */
1921 if (GET_CODE (x
) == LO_SUM
)
1924 if (small_symbolic_operand (x
, Pmode
))
1926 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
1934 /* Try a machine-dependent way of reloading an illegitimate address
1935 operand. If we find one, push the reload and return the new rtx. */
1938 alpha_legitimize_reload_address (x
, mode
, opnum
, type
, ind_levels
)
1940 enum machine_mode mode ATTRIBUTE_UNUSED
;
1943 int ind_levels ATTRIBUTE_UNUSED
;
1945 /* We must recognize output that we have already generated ourselves. */
1946 if (GET_CODE (x
) == PLUS
1947 && GET_CODE (XEXP (x
, 0)) == PLUS
1948 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1949 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1950 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1952 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1953 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1958 /* We wish to handle large displacements off a base register by
1959 splitting the addend across an ldah and the mem insn. This
1960 cuts number of extra insns needed from 3 to 1. */
1961 if (GET_CODE (x
) == PLUS
1962 && GET_CODE (XEXP (x
, 0)) == REG
1963 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
1964 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
1965 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1967 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
1968 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
1970 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
1972 /* Check for 32-bit overflow. */
1973 if (high
+ low
!= val
)
1976 /* Reload the high part into a base reg; leave the low part
1977 in the mem directly. */
1978 x
= gen_rtx_PLUS (GET_MODE (x
),
1979 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
1983 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1984 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1992 /* REF is an alignable memory location. Place an aligned SImode
1993 reference into *PALIGNED_MEM and the number of bits to shift into
1994 *PBITNUM. SCRATCH is a free register for use in reloading out
1995 of range stack slots. */
1998 get_aligned_mem (ref
, paligned_mem
, pbitnum
)
2000 rtx
*paligned_mem
, *pbitnum
;
2003 HOST_WIDE_INT offset
= 0;
2005 if (GET_CODE (ref
) != MEM
)
2008 if (reload_in_progress
2009 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2011 base
= find_replacement (&XEXP (ref
, 0));
2013 if (! memory_address_p (GET_MODE (ref
), base
))
2018 base
= XEXP (ref
, 0);
2021 if (GET_CODE (base
) == PLUS
)
2022 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2025 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
2027 if (WORDS_BIG_ENDIAN
)
2028 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
2029 + (offset
& 3) * 8));
2031 *pbitnum
= GEN_INT ((offset
& 3) * 8);
2034 /* Similar, but just get the address. Handle the two reload cases.
2035 Add EXTRA_OFFSET to the address we return. */
2038 get_unaligned_address (ref
, extra_offset
)
2043 HOST_WIDE_INT offset
= 0;
2045 if (GET_CODE (ref
) != MEM
)
2048 if (reload_in_progress
2049 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2051 base
= find_replacement (&XEXP (ref
, 0));
2053 if (! memory_address_p (GET_MODE (ref
), base
))
2058 base
= XEXP (ref
, 0);
2061 if (GET_CODE (base
) == PLUS
)
2062 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2064 return plus_constant (base
, offset
+ extra_offset
);
2067 /* On the Alpha, all (non-symbolic) constants except zero go into
2068 a floating-point register via memory. Note that we cannot
2069 return anything that is not a subset of CLASS, and that some
2070 symbolic constants cannot be dropped to memory. */
2073 alpha_preferred_reload_class(x
, class)
2075 enum reg_class
class;
2077 /* Zero is present in any register class. */
2078 if (x
== CONST0_RTX (GET_MODE (x
)))
2081 /* These sorts of constants we can easily drop to memory. */
2082 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2084 if (class == FLOAT_REGS
)
2086 if (class == ALL_REGS
)
2087 return GENERAL_REGS
;
2091 /* All other kinds of constants should not (and in the case of HIGH
2092 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2093 secondary reload. */
2095 return (class == ALL_REGS
? GENERAL_REGS
: class);
2100 /* Loading and storing HImode or QImode values to and from memory
2101 usually requires a scratch register. The exceptions are loading
2102 QImode and HImode from an aligned address to a general register
2103 unless byte instructions are permitted.
2105 We also cannot load an unaligned address or a paradoxical SUBREG
2106 into an FP register.
2108 We also cannot do integral arithmetic into FP regs, as might result
2109 from register elimination into a DImode fp register. */
2112 secondary_reload_class (class, mode
, x
, in
)
2113 enum reg_class
class;
2114 enum machine_mode mode
;
2118 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
2120 if (GET_CODE (x
) == MEM
2121 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
2122 || (GET_CODE (x
) == SUBREG
2123 && (GET_CODE (SUBREG_REG (x
)) == MEM
2124 || (GET_CODE (SUBREG_REG (x
)) == REG
2125 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
2127 if (!in
|| !aligned_memory_operand(x
, mode
))
2128 return GENERAL_REGS
;
2132 if (class == FLOAT_REGS
)
2134 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
2135 return GENERAL_REGS
;
2137 if (GET_CODE (x
) == SUBREG
2138 && (GET_MODE_SIZE (GET_MODE (x
))
2139 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2140 return GENERAL_REGS
;
2142 if (in
&& INTEGRAL_MODE_P (mode
)
2143 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
2144 return GENERAL_REGS
;
2150 /* Subfunction of the following function. Update the flags of any MEM
2151 found in part of X. */
2154 alpha_set_memflags_1 (x
, in_struct_p
, volatile_p
, unchanging_p
)
2156 int in_struct_p
, volatile_p
, unchanging_p
;
2160 switch (GET_CODE (x
))
2164 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2165 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
2170 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
2175 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
2177 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
2182 MEM_IN_STRUCT_P (x
) = in_struct_p
;
2183 MEM_VOLATILE_P (x
) = volatile_p
;
2184 RTX_UNCHANGING_P (x
) = unchanging_p
;
2185 /* Sadly, we cannot use alias sets because the extra aliasing
2186 produced by the AND interferes. Given that two-byte quantities
2187 are the only thing we would be able to differentiate anyway,
2188 there does not seem to be any point in convoluting the early
2189 out of the alias check. */
2197 /* Given INSN, which is either an INSN or a SEQUENCE generated to
2198 perform a memory operation, look for any MEMs in either a SET_DEST or
2199 a SET_SRC and copy the in-struct, unchanging, and volatile flags from
2200 REF into each of the MEMs found. If REF is not a MEM, don't do
2204 alpha_set_memflags (insn
, ref
)
2208 int in_struct_p
, volatile_p
, unchanging_p
;
2210 if (GET_CODE (ref
) != MEM
)
2213 in_struct_p
= MEM_IN_STRUCT_P (ref
);
2214 volatile_p
= MEM_VOLATILE_P (ref
);
2215 unchanging_p
= RTX_UNCHANGING_P (ref
);
2217 /* This is only called from alpha.md, after having had something
2218 generated from one of the insn patterns. So if everything is
2219 zero, the pattern is already up-to-date. */
2220 if (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
)
2223 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
2226 /* Try to output insns to set TARGET equal to the constant C if it can be
2227 done in less than N insns. Do all computations in MODE. Returns the place
2228 where the output has been placed if it can be done and the insns have been
2229 emitted. If it would take more than N insns, zero is returned and no
2230 insns and emitted. */
2233 alpha_emit_set_const (target
, mode
, c
, n
)
2235 enum machine_mode mode
;
2240 rtx orig_target
= target
;
2243 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2244 can't load this constant in one insn, do this in DImode. */
2245 if (no_new_pseudos
&& mode
== SImode
2246 && GET_CODE (target
) == REG
&& REGNO (target
) < FIRST_PSEUDO_REGISTER
2247 && (result
= alpha_emit_set_const_1 (target
, mode
, c
, 1)) == 0)
2249 target
= gen_lowpart (DImode
, target
);
2253 /* Try 1 insn, then 2, then up to N. */
2254 for (i
= 1; i
<= n
; i
++)
2256 result
= alpha_emit_set_const_1 (target
, mode
, c
, i
);
2259 rtx insn
= get_last_insn ();
2260 rtx set
= single_set (insn
);
2261 if (! CONSTANT_P (SET_SRC (set
)))
2262 set_unique_reg_note (get_last_insn (), REG_EQUAL
, GEN_INT (c
));
2267 /* Allow for the case where we changed the mode of TARGET. */
2268 if (result
== target
)
2269 result
= orig_target
;
2274 /* Internal routine for the above to check for N or below insns. */
2277 alpha_emit_set_const_1 (target
, mode
, c
, n
)
2279 enum machine_mode mode
;
2285 /* Use a pseudo if highly optimizing and still generating RTL. */
2287 = (flag_expensive_optimizations
&& !no_new_pseudos
? 0 : target
);
2290 /* If this is a sign-extended 32-bit constant, we can do this in at most
2291 three insns, so do it if we have enough insns left. We always have
2292 a sign-extended 32-bit constant when compiling on a narrow machine. */
2294 if (HOST_BITS_PER_WIDE_INT
!= 64
2295 || c
>> 31 == -1 || c
>> 31 == 0)
2297 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
2298 HOST_WIDE_INT tmp1
= c
- low
;
2299 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
2300 HOST_WIDE_INT extra
= 0;
2302 /* If HIGH will be interpreted as negative but the constant is
2303 positive, we must adjust it to do two ldha insns. */
2305 if ((high
& 0x8000) != 0 && c
>= 0)
2309 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
2312 if (c
== low
|| (low
== 0 && extra
== 0))
2314 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2315 but that meant that we can't handle INT_MIN on 32-bit machines
2316 (like NT/Alpha), because we recurse indefinitely through
2317 emit_move_insn to gen_movdi. So instead, since we know exactly
2318 what we want, create it explicitly. */
2321 target
= gen_reg_rtx (mode
);
2322 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
2325 else if (n
>= 2 + (extra
!= 0))
2327 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16), subtarget
, mode
);
2329 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2330 This means that if we go through expand_binop, we'll try to
2331 generate extensions, etc, which will require new pseudos, which
2332 will fail during some split phases. The SImode add patterns
2333 still exist, but are not named. So build the insns by hand. */
2338 subtarget
= gen_reg_rtx (mode
);
2339 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (extra
<< 16));
2340 insn
= gen_rtx_SET (VOIDmode
, subtarget
, insn
);
2346 target
= gen_reg_rtx (mode
);
2347 insn
= gen_rtx_PLUS (mode
, temp
, GEN_INT (low
));
2348 insn
= gen_rtx_SET (VOIDmode
, target
, insn
);
2354 /* If we couldn't do it that way, try some other methods. But if we have
2355 no instructions left, don't bother. Likewise, if this is SImode and
2356 we can't make pseudos, we can't do anything since the expand_binop
2357 and expand_unop calls will widen and try to make pseudos. */
2359 if (n
== 1 || (mode
== SImode
&& no_new_pseudos
))
2362 /* Next, see if we can load a related constant and then shift and possibly
2363 negate it to get the constant we want. Try this once each increasing
2364 numbers of insns. */
2366 for (i
= 1; i
< n
; i
++)
2368 /* First, see if minus some low bits, we've an easy load of
2371 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
2373 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
2374 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
2375 target
, 0, OPTAB_WIDEN
);
2377 /* Next try complementing. */
2378 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
2379 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
2381 /* Next try to form a constant and do a left shift. We can do this
2382 if some low-order bits are zero; the exact_log2 call below tells
2383 us that information. The bits we are shifting out could be any
2384 value, but here we'll just try the 0- and sign-extended forms of
2385 the constant. To try to increase the chance of having the same
2386 constant in more than one insn, start at the highest number of
2387 bits to shift, but try all possibilities in case a ZAPNOT will
2390 if ((bits
= exact_log2 (c
& - c
)) > 0)
2391 for (; bits
> 0; bits
--)
2392 if ((temp
= (alpha_emit_set_const
2393 (subtarget
, mode
, c
>> bits
, i
))) != 0
2394 || ((temp
= (alpha_emit_set_const
2396 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
2398 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
2399 target
, 0, OPTAB_WIDEN
);
2401 /* Now try high-order zero bits. Here we try the shifted-in bits as
2402 all zero and all ones. Be careful to avoid shifting outside the
2403 mode and to avoid shifting outside the host wide int size. */
2404 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2405 confuse the recursive call and set all of the high 32 bits. */
2407 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2408 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
2409 for (; bits
> 0; bits
--)
2410 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2412 || ((temp
= (alpha_emit_set_const
2414 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2417 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
2418 target
, 1, OPTAB_WIDEN
);
2420 /* Now try high-order 1 bits. We get that with a sign-extension.
2421 But one bit isn't enough here. Be careful to avoid shifting outside
2422 the mode and to avoid shifting outside the host wide int size. */
2424 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2425 - floor_log2 (~ c
) - 2)) > 0)
2426 for (; bits
> 0; bits
--)
2427 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2429 || ((temp
= (alpha_emit_set_const
2431 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2434 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
2435 target
, 0, OPTAB_WIDEN
);
2438 #if HOST_BITS_PER_WIDE_INT == 64
2439 /* Finally, see if can load a value into the target that is the same as the
2440 constant except that all bytes that are 0 are changed to be 0xff. If we
2441 can, then we can do a ZAPNOT to obtain the desired constant. */
2444 for (i
= 0; i
< 64; i
+= 8)
2445 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
2446 new |= (HOST_WIDE_INT
) 0xff << i
;
2448 /* We are only called for SImode and DImode. If this is SImode, ensure that
2449 we are sign extended to a full word. */
2452 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2454 if (new != c
&& new != -1
2455 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
2456 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
2457 target
, 0, OPTAB_WIDEN
);
2463 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2464 fall back to a straight forward decomposition. We do this to avoid
2465 exponential run times encountered when looking for longer sequences
2466 with alpha_emit_set_const. */
2469 alpha_emit_set_long_const (target
, c1
, c2
)
2471 HOST_WIDE_INT c1
, c2
;
2473 HOST_WIDE_INT d1
, d2
, d3
, d4
;
2475 /* Decompose the entire word */
2476 #if HOST_BITS_PER_WIDE_INT >= 64
2477 if (c2
!= -(c1
< 0))
2479 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2481 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2482 c1
= (c1
- d2
) >> 32;
2483 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2485 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2489 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2491 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2495 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
2497 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2502 /* Construct the high word */
2505 emit_move_insn (target
, GEN_INT (d4
));
2507 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2510 emit_move_insn (target
, GEN_INT (d3
));
2512 /* Shift it into place */
2513 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2515 /* Add in the low bits. */
2517 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2519 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
2524 /* Expand a move instruction; return true if all work is done.
2525 We don't handle non-bwx subword loads here. */
2528 alpha_expand_mov (mode
, operands
)
2529 enum machine_mode mode
;
2532 /* If the output is not a register, the input must be. */
2533 if (GET_CODE (operands
[0]) == MEM
2534 && ! reg_or_0_operand (operands
[1], mode
))
2535 operands
[1] = force_reg (mode
, operands
[1]);
2537 /* Allow legitimize_address to perform some simplifications. */
2538 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2542 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2543 compiled at the end of compilation. In the meantime, someone can
2544 re-encode-section-info on some symbol changing it e.g. from global
2545 to local-not-small. If this happens, we'd have emitted a plain
2546 load rather than a high+losum load and not recognize the insn.
2548 So if rtl inlining is in effect, we delay the global/not-global
2549 decision until rest_of_compilation by wrapping it in an
2551 if (TARGET_EXPLICIT_RELOCS
&& flag_inline_functions
2552 && rtx_equal_function_value_matters
2553 && global_symbolic_operand (operands
[1], mode
))
2555 emit_insn (gen_movdi_er_maybe_g (operands
[0], operands
[1]));
2559 tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
2567 /* Early out for non-constants and valid constants. */
2568 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2571 /* Split large integers. */
2572 if (GET_CODE (operands
[1]) == CONST_INT
2573 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
2575 HOST_WIDE_INT i0
, i1
;
2576 rtx temp
= NULL_RTX
;
2578 if (GET_CODE (operands
[1]) == CONST_INT
)
2580 i0
= INTVAL (operands
[1]);
2583 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2585 i0
= CONST_DOUBLE_LOW (operands
[1]);
2590 i0
= CONST_DOUBLE_LOW (operands
[1]);
2591 i1
= CONST_DOUBLE_HIGH (operands
[1]);
2594 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2595 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
2597 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2598 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
2602 if (rtx_equal_p (operands
[0], temp
))
2609 /* Otherwise we've nothing left but to drop the thing to memory. */
2610 operands
[1] = force_const_mem (DImode
, operands
[1]);
2611 if (reload_in_progress
)
2613 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
2614 operands
[1] = copy_rtx (operands
[1]);
2615 XEXP (operands
[1], 0) = operands
[0];
2618 operands
[1] = validize_mem (operands
[1]);
2622 /* Expand a non-bwx QImode or HImode move instruction;
2623 return true if all work is done. */
2626 alpha_expand_mov_nobwx (mode
, operands
)
2627 enum machine_mode mode
;
2630 /* If the output is not a register, the input must be. */
2631 if (GET_CODE (operands
[0]) == MEM
)
2632 operands
[1] = force_reg (mode
, operands
[1]);
2634 /* Handle four memory cases, unaligned and aligned for either the input
2635 or the output. The only case where we can be called during reload is
2636 for aligned loads; all other cases require temporaries. */
2638 if (GET_CODE (operands
[1]) == MEM
2639 || (GET_CODE (operands
[1]) == SUBREG
2640 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
2641 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
2642 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
2643 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
2644 && GET_CODE (SUBREG_REG (operands
[1])) == REG
2645 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
2647 if (aligned_memory_operand (operands
[1], mode
))
2649 if (reload_in_progress
)
2651 emit_insn ((mode
== QImode
2652 ? gen_reload_inqi_help
2653 : gen_reload_inhi_help
)
2654 (operands
[0], operands
[1],
2655 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
2659 rtx aligned_mem
, bitnum
;
2660 rtx scratch
= gen_reg_rtx (SImode
);
2662 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
2664 emit_insn ((mode
== QImode
2665 ? gen_aligned_loadqi
2666 : gen_aligned_loadhi
)
2667 (operands
[0], aligned_mem
, bitnum
, scratch
));
2672 /* Don't pass these as parameters since that makes the generated
2673 code depend on parameter evaluation order which will cause
2674 bootstrap failures. */
2676 rtx temp1
= gen_reg_rtx (DImode
);
2677 rtx temp2
= gen_reg_rtx (DImode
);
2678 rtx seq
= ((mode
== QImode
2679 ? gen_unaligned_loadqi
2680 : gen_unaligned_loadhi
)
2681 (operands
[0], get_unaligned_address (operands
[1], 0),
2684 alpha_set_memflags (seq
, operands
[1]);
2690 if (GET_CODE (operands
[0]) == MEM
2691 || (GET_CODE (operands
[0]) == SUBREG
2692 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
2693 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
2694 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
2695 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
2696 && GET_CODE (SUBREG_REG (operands
[0])) == REG
2697 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
2699 if (aligned_memory_operand (operands
[0], mode
))
2701 rtx aligned_mem
, bitnum
;
2702 rtx temp1
= gen_reg_rtx (SImode
);
2703 rtx temp2
= gen_reg_rtx (SImode
);
2705 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
2707 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
2712 rtx temp1
= gen_reg_rtx (DImode
);
2713 rtx temp2
= gen_reg_rtx (DImode
);
2714 rtx temp3
= gen_reg_rtx (DImode
);
2715 rtx seq
= ((mode
== QImode
2716 ? gen_unaligned_storeqi
2717 : gen_unaligned_storehi
)
2718 (get_unaligned_address (operands
[0], 0),
2719 operands
[1], temp1
, temp2
, temp3
));
2721 alpha_set_memflags (seq
, operands
[0]);
2730 /* Generate an unsigned DImode to FP conversion. This is the same code
2731 optabs would emit if we didn't have TFmode patterns.
2733 For SFmode, this is the only construction I've found that can pass
2734 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2735 intermediates will work, because you'll get intermediate rounding
2736 that ruins the end result. Some of this could be fixed by turning
2737 on round-to-positive-infinity, but that requires diddling the fpsr,
2738 which kills performance. I tried turning this around and converting
2739 to a negative number, so that I could turn on /m, but either I did
2740 it wrong or there's something else cause I wound up with the exact
2741 same single-bit error. There is a branch-less form of this same code:
2752 fcmoveq $f10,$f11,$f0
2754 I'm not using it because it's the same number of instructions as
2755 this branch-full form, and it has more serialized long latency
2756 instructions on the critical path.
2758 For DFmode, we can avoid rounding errors by breaking up the word
2759 into two pieces, converting them separately, and adding them back:
2761 LC0: .long 0,0x5f800000
2766 cpyse $f11,$f31,$f10
2767 cpyse $f31,$f11,$f11
2775 This doesn't seem to be a clear-cut win over the optabs form.
2776 It probably all depends on the distribution of numbers being
2777 converted -- in the optabs form, all but high-bit-set has a
2778 much lower minimum execution time. */
2781 alpha_emit_floatuns (operands
)
2784 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
2785 enum machine_mode mode
;
2788 in
= force_reg (DImode
, operands
[1]);
2789 mode
= GET_MODE (out
);
2790 neglab
= gen_label_rtx ();
2791 donelab
= gen_label_rtx ();
2792 i0
= gen_reg_rtx (DImode
);
2793 i1
= gen_reg_rtx (DImode
);
2794 f0
= gen_reg_rtx (mode
);
2796 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
2798 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
2799 emit_jump_insn (gen_jump (donelab
));
2802 emit_label (neglab
);
2804 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
2805 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
2806 emit_insn (gen_iordi3 (i0
, i0
, i1
));
2807 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
2808 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
2810 emit_label (donelab
);
2813 /* Generate the comparison for a conditional branch. */
2816 alpha_emit_conditional_branch (code
)
2819 enum rtx_code cmp_code
, branch_code
;
2820 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
2821 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
2824 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
2826 if (! TARGET_HAS_XFLOATING_LIBS
)
2829 /* X_floating library comparison functions return
2833 Convert the compare against the raw return value. */
2855 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
2857 alpha_compare
.fp_p
= 0;
2860 /* The general case: fold the comparison code to the types of compares
2861 that we have, choosing the branch as necessary. */
2864 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2866 /* We have these compares: */
2867 cmp_code
= code
, branch_code
= NE
;
2872 /* These must be reversed. */
2873 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
2876 case GE
: case GT
: case GEU
: case GTU
:
2877 /* For FP, we swap them, for INT, we reverse them. */
2878 if (alpha_compare
.fp_p
)
2880 cmp_code
= swap_condition (code
);
2882 tem
= op0
, op0
= op1
, op1
= tem
;
2886 cmp_code
= reverse_condition (code
);
2895 if (alpha_compare
.fp_p
)
2898 if (flag_unsafe_math_optimizations
)
2900 /* When we are not as concerned about non-finite values, and we
2901 are comparing against zero, we can branch directly. */
2902 if (op1
== CONST0_RTX (DFmode
))
2903 cmp_code
= NIL
, branch_code
= code
;
2904 else if (op0
== CONST0_RTX (DFmode
))
2906 /* Undo the swap we probably did just above. */
2907 tem
= op0
, op0
= op1
, op1
= tem
;
2908 branch_code
= swap_condition (cmp_code
);
2914 /* ??? We mark the the branch mode to be CCmode to prevent the
2915 compare and branch from being combined, since the compare
2916 insn follows IEEE rules that the branch does not. */
2917 branch_mode
= CCmode
;
2924 /* The following optimizations are only for signed compares. */
2925 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
2927 /* Whee. Compare and branch against 0 directly. */
2928 if (op1
== const0_rtx
)
2929 cmp_code
= NIL
, branch_code
= code
;
2931 /* We want to use cmpcc/bcc when we can, since there is a zero delay
2932 bypass between logicals and br/cmov on EV5. But we don't want to
2933 force valid immediate constants into registers needlessly. */
2934 else if (GET_CODE (op1
) == CONST_INT
)
2936 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
2938 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
2939 && (CONST_OK_FOR_LETTER_P (n
, 'K')
2940 || CONST_OK_FOR_LETTER_P (n
, 'L')))
2942 cmp_code
= PLUS
, branch_code
= code
;
2948 if (!reg_or_0_operand (op0
, DImode
))
2949 op0
= force_reg (DImode
, op0
);
2950 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
2951 op1
= force_reg (DImode
, op1
);
2954 /* Emit an initial compare instruction, if necessary. */
2956 if (cmp_code
!= NIL
)
2958 tem
= gen_reg_rtx (cmp_mode
);
2959 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
2962 /* Zero the operands. */
2963 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2965 /* Return the branch comparison. */
2966 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
2969 /* Certain simplifications can be done to make invalid setcc operations
2970 valid. Return the final comparison, or NULL if we can't work. */
2973 alpha_emit_setcc (code
)
2976 enum rtx_code cmp_code
;
2977 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
2978 int fp_p
= alpha_compare
.fp_p
;
2981 /* Zero the operands. */
2982 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2984 if (fp_p
&& GET_MODE (op0
) == TFmode
)
2986 if (! TARGET_HAS_XFLOATING_LIBS
)
2989 /* X_floating library comparison functions return
2993 Convert the compare against the raw return value. */
2995 if (code
== UNORDERED
|| code
== ORDERED
)
3000 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
3004 if (code
== UNORDERED
)
3006 else if (code
== ORDERED
)
3012 if (fp_p
&& !TARGET_FIX
)
3015 /* The general case: fold the comparison code to the types of compares
3016 that we have, choosing the branch as necessary. */
3021 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3023 /* We have these compares. */
3025 cmp_code
= code
, code
= NE
;
3029 if (!fp_p
&& op1
== const0_rtx
)
3034 cmp_code
= reverse_condition (code
);
3038 case GE
: case GT
: case GEU
: case GTU
:
3039 /* These normally need swapping, but for integer zero we have
3040 special patterns that recognize swapped operands. */
3041 if (!fp_p
&& op1
== const0_rtx
)
3043 code
= swap_condition (code
);
3045 cmp_code
= code
, code
= NE
;
3046 tmp
= op0
, op0
= op1
, op1
= tmp
;
3055 if (!register_operand (op0
, DImode
))
3056 op0
= force_reg (DImode
, op0
);
3057 if (!reg_or_8bit_operand (op1
, DImode
))
3058 op1
= force_reg (DImode
, op1
);
3061 /* Emit an initial compare instruction, if necessary. */
3062 if (cmp_code
!= NIL
)
3064 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
3066 tmp
= gen_reg_rtx (mode
);
3067 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
3068 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
3070 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
3074 /* Return the setcc comparison. */
3075 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
3079 /* Rewrite a comparison against zero CMP of the form
3080 (CODE (cc0) (const_int 0)) so it can be written validly in
3081 a conditional move (if_then_else CMP ...).
3082 If both of the operands that set cc0 are non-zero we must emit
3083 an insn to perform the compare (it can't be done within
3084 the conditional move). */
3086 alpha_emit_conditional_move (cmp
, mode
)
3088 enum machine_mode mode
;
3090 enum rtx_code code
= GET_CODE (cmp
);
3091 enum rtx_code cmov_code
= NE
;
3092 rtx op0
= alpha_compare
.op0
;
3093 rtx op1
= alpha_compare
.op1
;
3094 int fp_p
= alpha_compare
.fp_p
;
3095 enum machine_mode cmp_mode
3096 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
3097 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
3098 enum machine_mode cmov_mode
= VOIDmode
;
3099 int local_fast_math
= flag_unsafe_math_optimizations
;
3102 /* Zero the operands. */
3103 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3105 if (fp_p
!= FLOAT_MODE_P (mode
))
3107 enum rtx_code cmp_code
;
3112 /* If we have fp<->int register move instructions, do a cmov by
3113 performing the comparison in fp registers, and move the
3114 zero/non-zero value to integer registers, where we can then
3115 use a normal cmov, or vice-versa. */
3119 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3120 /* We have these compares. */
3121 cmp_code
= code
, code
= NE
;
3125 /* This must be reversed. */
3126 cmp_code
= EQ
, code
= EQ
;
3129 case GE
: case GT
: case GEU
: case GTU
:
3130 /* These normally need swapping, but for integer zero we have
3131 special patterns that recognize swapped operands. */
3132 if (!fp_p
&& op1
== const0_rtx
)
3133 cmp_code
= code
, code
= NE
;
3136 cmp_code
= swap_condition (code
);
3138 tem
= op0
, op0
= op1
, op1
= tem
;
3146 tem
= gen_reg_rtx (cmp_op_mode
);
3147 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
3148 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
3151 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
3152 op0
= gen_lowpart (cmp_op_mode
, tem
);
3153 op1
= CONST0_RTX (cmp_op_mode
);
3155 local_fast_math
= 1;
3158 /* We may be able to use a conditional move directly.
3159 This avoids emitting spurious compares. */
3160 if (signed_comparison_operator (cmp
, VOIDmode
)
3161 && (!fp_p
|| local_fast_math
)
3162 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
3163 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3165 /* We can't put the comparison inside the conditional move;
3166 emit a compare instruction and put that inside the
3167 conditional move. Make sure we emit only comparisons we have;
3168 swap or reverse as necessary. */
3175 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3176 /* We have these compares: */
3180 /* This must be reversed. */
3181 code
= reverse_condition (code
);
3185 case GE
: case GT
: case GEU
: case GTU
:
3186 /* These must be swapped. */
3187 if (op1
!= CONST0_RTX (cmp_mode
))
3189 code
= swap_condition (code
);
3190 tem
= op0
, op0
= op1
, op1
= tem
;
3200 if (!reg_or_0_operand (op0
, DImode
))
3201 op0
= force_reg (DImode
, op0
);
3202 if (!reg_or_8bit_operand (op1
, DImode
))
3203 op1
= force_reg (DImode
, op1
);
3206 /* ??? We mark the branch mode to be CCmode to prevent the compare
3207 and cmov from being combined, since the compare insn follows IEEE
3208 rules that the cmov does not. */
3209 if (fp_p
&& !local_fast_math
)
3212 tem
= gen_reg_rtx (cmp_op_mode
);
3213 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
3214 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
3217 /* Simplify a conditional move of two constants into a setcc with
3218 arithmetic. This is done with a splitter since combine would
3219 just undo the work if done during code generation. It also catches
3220 cases we wouldn't have before cse. */
3223 alpha_split_conditional_move (code
, dest
, cond
, t_rtx
, f_rtx
)
3225 rtx dest
, cond
, t_rtx
, f_rtx
;
3227 HOST_WIDE_INT t
, f
, diff
;
3228 enum machine_mode mode
;
3229 rtx target
, subtarget
, tmp
;
3231 mode
= GET_MODE (dest
);
3236 if (((code
== NE
|| code
== EQ
) && diff
< 0)
3237 || (code
== GE
|| code
== GT
))
3239 code
= reverse_condition (code
);
3240 diff
= t
, t
= f
, f
= diff
;
3244 subtarget
= target
= dest
;
3247 target
= gen_lowpart (DImode
, dest
);
3248 if (! no_new_pseudos
)
3249 subtarget
= gen_reg_rtx (DImode
);
3253 /* Below, we must be careful to use copy_rtx on target and subtarget
3254 in intermediate insns, as they may be a subreg rtx, which may not
3257 if (f
== 0 && exact_log2 (diff
) > 0
3258 /* On EV6, we've got enough shifters to make non-arithmatic shifts
3259 viable over a longer latency cmove. On EV5, the E0 slot is a
3260 scarce resource, and on EV4 shift has the same latency as a cmove. */
3261 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
3263 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3264 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3266 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
3267 GEN_INT (exact_log2 (t
)));
3268 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3270 else if (f
== 0 && t
== -1)
3272 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3273 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3275 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
3277 else if (diff
== 1 || diff
== 4 || diff
== 8)
3281 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3282 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3285 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
3288 add_op
= GEN_INT (f
);
3289 if (sext_add_operand (add_op
, mode
))
3291 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
3293 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
3294 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3306 /* Look up the function X_floating library function name for the
3310 alpha_lookup_xfloating_lib_func (code
)
3315 const enum rtx_code code
;
3316 const char *const func
;
3319 static const struct xfloating_op vms_xfloating_ops
[] =
3321 { PLUS
, "OTS$ADD_X" },
3322 { MINUS
, "OTS$SUB_X" },
3323 { MULT
, "OTS$MUL_X" },
3324 { DIV
, "OTS$DIV_X" },
3325 { EQ
, "OTS$EQL_X" },
3326 { NE
, "OTS$NEQ_X" },
3327 { LT
, "OTS$LSS_X" },
3328 { LE
, "OTS$LEQ_X" },
3329 { GT
, "OTS$GTR_X" },
3330 { GE
, "OTS$GEQ_X" },
3331 { FIX
, "OTS$CVTXQ" },
3332 { FLOAT
, "OTS$CVTQX" },
3333 { UNSIGNED_FLOAT
, "OTS$CVTQUX" },
3334 { FLOAT_EXTEND
, "OTS$CVT_FLOAT_T_X" },
3335 { FLOAT_TRUNCATE
, "OTS$CVT_FLOAT_X_T" },
3338 static const struct xfloating_op osf_xfloating_ops
[] =
3340 { PLUS
, "_OtsAddX" },
3341 { MINUS
, "_OtsSubX" },
3342 { MULT
, "_OtsMulX" },
3343 { DIV
, "_OtsDivX" },
3350 { FIX
, "_OtsCvtXQ" },
3351 { FLOAT
, "_OtsCvtQX" },
3352 { UNSIGNED_FLOAT
, "_OtsCvtQUX" },
3353 { FLOAT_EXTEND
, "_OtsConvertFloatTX" },
3354 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT" },
3357 const struct xfloating_op
*ops
;
3358 const long n
= ARRAY_SIZE (osf_xfloating_ops
);
3361 /* How irritating. Nothing to key off for the table. Hardcode
3362 knowledge of the G_floating routines. */
3363 if (TARGET_FLOAT_VAX
)
3365 if (TARGET_ABI_OPEN_VMS
)
3367 if (code
== FLOAT_EXTEND
)
3368 return "OTS$CVT_FLOAT_G_X";
3369 if (code
== FLOAT_TRUNCATE
)
3370 return "OTS$CVT_FLOAT_X_G";
3374 if (code
== FLOAT_EXTEND
)
3375 return "_OtsConvertFloatGX";
3376 if (code
== FLOAT_TRUNCATE
)
3377 return "_OtsConvertFloatXG";
3381 if (TARGET_ABI_OPEN_VMS
)
3382 ops
= vms_xfloating_ops
;
3384 ops
= osf_xfloating_ops
;
3386 for (i
= 0; i
< n
; ++i
)
3387 if (ops
[i
].code
== code
)
3393 /* Most X_floating operations take the rounding mode as an argument.
3394 Compute that here. */
3397 alpha_compute_xfloating_mode_arg (code
, round
)
3399 enum alpha_fp_rounding_mode round
;
3405 case ALPHA_FPRM_NORM
:
3408 case ALPHA_FPRM_MINF
:
3411 case ALPHA_FPRM_CHOP
:
3414 case ALPHA_FPRM_DYN
:
3420 /* XXX For reference, round to +inf is mode = 3. */
3423 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3429 /* Emit an X_floating library function call.
3431 Note that these functions do not follow normal calling conventions:
3432 TFmode arguments are passed in two integer registers (as opposed to
3433 indirect); TFmode return values appear in R16+R17.
3435 FUNC is the function name to call.
3436 TARGET is where the output belongs.
3437 OPERANDS are the inputs.
3438 NOPERANDS is the count of inputs.
3439 EQUIV is the expression equivalent for the function.
3443 alpha_emit_xfloating_libcall (func
, target
, operands
, noperands
, equiv
)
3450 rtx usage
= NULL_RTX
, tmp
, reg
;
3455 for (i
= 0; i
< noperands
; ++i
)
3457 switch (GET_MODE (operands
[i
]))
3460 reg
= gen_rtx_REG (TFmode
, regno
);
3465 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3470 if (GET_CODE (operands
[i
]) != CONST_INT
)
3474 reg
= gen_rtx_REG (DImode
, regno
);
3482 emit_move_insn (reg
, operands
[i
]);
3483 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3486 switch (GET_MODE (target
))
3489 reg
= gen_rtx_REG (TFmode
, 16);
3492 reg
= gen_rtx_REG (DFmode
, 32);
3495 reg
= gen_rtx_REG (DImode
, 0);
3501 tmp
= gen_rtx_MEM (QImode
, gen_rtx_SYMBOL_REF (Pmode
, (char *) func
));
3502 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3503 const0_rtx
, const0_rtx
));
3504 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3509 emit_libcall_block (tmp
, target
, reg
, equiv
);
3512 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3515 alpha_emit_xfloating_arith (code
, operands
)
3521 rtx out_operands
[3];
3523 func
= alpha_lookup_xfloating_lib_func (code
);
3524 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3526 out_operands
[0] = operands
[1];
3527 out_operands
[1] = operands
[2];
3528 out_operands
[2] = GEN_INT (mode
);
3529 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
3530 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
3534 /* Emit an X_floating library function call for a comparison. */
3537 alpha_emit_xfloating_compare (code
, op0
, op1
)
3542 rtx out
, operands
[2];
3544 func
= alpha_lookup_xfloating_lib_func (code
);
3548 out
= gen_reg_rtx (DImode
);
3550 /* ??? Strange mode for equiv because what's actually returned
3551 is -1,0,1, not a proper boolean value. */
3552 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
3553 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
3558 /* Emit an X_floating library function call for a conversion. */
3561 alpha_emit_xfloating_cvt (code
, operands
)
3565 int noperands
= 1, mode
;
3566 rtx out_operands
[2];
3569 func
= alpha_lookup_xfloating_lib_func (code
);
3571 out_operands
[0] = operands
[1];
3576 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3577 out_operands
[1] = GEN_INT (mode
);
3580 case FLOAT_TRUNCATE
:
3581 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3582 out_operands
[1] = GEN_INT (mode
);
3589 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3590 gen_rtx_fmt_e (code
, GET_MODE (operands
[0]),
3594 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3595 OP[0] into OP[0,1]. Naturally, output operand ordering is
3599 alpha_split_tfmode_pair (operands
)
3602 if (GET_CODE (operands
[1]) == REG
)
3604 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
3605 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
3607 else if (GET_CODE (operands
[1]) == MEM
)
3609 operands
[3] = adjust_address (operands
[1], DImode
, 8);
3610 operands
[2] = adjust_address (operands
[1], DImode
, 0);
3612 else if (operands
[1] == CONST0_RTX (TFmode
))
3613 operands
[2] = operands
[3] = const0_rtx
;
3617 if (GET_CODE (operands
[0]) == REG
)
3619 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
3620 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
3622 else if (GET_CODE (operands
[0]) == MEM
)
3624 operands
[1] = adjust_address (operands
[0], DImode
, 8);
3625 operands
[0] = adjust_address (operands
[0], DImode
, 0);
3631 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3632 op2 is a register containing the sign bit, operation is the
3633 logical operation to be performed. */
3636 alpha_split_tfmode_frobsign (operands
, operation
)
3638 rtx (*operation
) PARAMS ((rtx
, rtx
, rtx
));
3640 rtx high_bit
= operands
[2];
3644 alpha_split_tfmode_pair (operands
);
3646 /* Detect three flavours of operand overlap. */
3648 if (rtx_equal_p (operands
[0], operands
[2]))
3650 else if (rtx_equal_p (operands
[1], operands
[2]))
3652 if (rtx_equal_p (operands
[0], high_bit
))
3659 emit_move_insn (operands
[0], operands
[2]);
3661 /* ??? If the destination overlaps both source tf and high_bit, then
3662 assume source tf is dead in its entirety and use the other half
3663 for a scratch register. Otherwise "scratch" is just the proper
3664 destination register. */
3665 scratch
= operands
[move
< 2 ? 1 : 3];
3667 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
3671 emit_move_insn (operands
[0], operands
[2]);
3673 emit_move_insn (operands
[1], scratch
);
3677 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3681 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3682 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3683 lda r3,X(r11) lda r3,X+2(r11)
3684 extwl r1,r3,r1 extql r1,r3,r1
3685 extwh r2,r3,r2 extqh r2,r3,r2
3686 or r1.r2.r1 or r1,r2,r1
3689 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3690 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3691 lda r3,X(r11) lda r3,X(r11)
3692 extll r1,r3,r1 extll r1,r3,r1
3693 extlh r2,r3,r2 extlh r2,r3,r2
3694 or r1.r2.r1 addl r1,r2,r1
3696 quad: ldq_u r1,X(r11)
3705 alpha_expand_unaligned_load (tgt
, mem
, size
, ofs
, sign
)
3707 HOST_WIDE_INT size
, ofs
;
3710 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
3711 enum machine_mode mode
;
3713 meml
= gen_reg_rtx (DImode
);
3714 memh
= gen_reg_rtx (DImode
);
3715 addr
= gen_reg_rtx (DImode
);
3716 extl
= gen_reg_rtx (DImode
);
3717 exth
= gen_reg_rtx (DImode
);
3719 mema
= XEXP (mem
, 0);
3720 if (GET_CODE (mema
) == LO_SUM
)
3721 mema
= force_reg (Pmode
, mema
);
3723 /* AND addresses cannot be in any alias set, since they may implicitly
3724 alias surrounding code. Ideally we'd have some alias set that
3725 covered all types except those with alignment 8 or higher. */
3727 tmp
= change_address (mem
, DImode
,
3728 gen_rtx_AND (DImode
,
3729 plus_constant (mema
, ofs
),
3731 set_mem_alias_set (tmp
, 0);
3732 emit_move_insn (meml
, tmp
);
3734 tmp
= change_address (mem
, DImode
,
3735 gen_rtx_AND (DImode
,
3736 plus_constant (mema
, ofs
+ size
- 1),
3738 set_mem_alias_set (tmp
, 0);
3739 emit_move_insn (memh
, tmp
);
3741 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
3743 emit_move_insn (addr
, plus_constant (mema
, -1));
3745 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3746 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
3748 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3749 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
3750 addr
, 1, OPTAB_WIDEN
);
3752 else if (sign
&& size
== 2)
3754 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
3756 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
3757 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3759 /* We must use tgt here for the target. Alpha-vms port fails if we use
3760 addr for the target, because addr is marked as a pointer and combine
3761 knows that pointers are always sign-extended 32 bit values. */
3762 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3763 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
3764 addr
, 1, OPTAB_WIDEN
);
3768 if (WORDS_BIG_ENDIAN
)
3770 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
3774 emit_insn (gen_extwh_be (extl
, meml
, addr
));
3779 emit_insn (gen_extlh_be (extl
, meml
, addr
));
3784 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3791 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
3795 emit_move_insn (addr
, plus_constant (mema
, ofs
));
3796 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
3800 emit_insn (gen_extwh_le (exth
, memh
, addr
));
3805 emit_insn (gen_extlh_le (exth
, memh
, addr
));
3810 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3819 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
3820 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
3825 emit_move_insn (tgt
, gen_lowpart(GET_MODE (tgt
), addr
));
3828 /* Similarly, use ins and msk instructions to perform unaligned stores. */
3831 alpha_expand_unaligned_store (dst
, src
, size
, ofs
)
3833 HOST_WIDE_INT size
, ofs
;
3835 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
3837 dstl
= gen_reg_rtx (DImode
);
3838 dsth
= gen_reg_rtx (DImode
);
3839 insl
= gen_reg_rtx (DImode
);
3840 insh
= gen_reg_rtx (DImode
);
3842 dsta
= XEXP (dst
, 0);
3843 if (GET_CODE (dsta
) == LO_SUM
)
3844 dsta
= force_reg (Pmode
, dsta
);
3846 /* AND addresses cannot be in any alias set, since they may implicitly
3847 alias surrounding code. Ideally we'd have some alias set that
3848 covered all types except those with alignment 8 or higher. */
3850 meml
= change_address (dst
, DImode
,
3851 gen_rtx_AND (DImode
,
3852 plus_constant (dsta
, ofs
),
3854 set_mem_alias_set (meml
, 0);
3856 memh
= change_address (dst
, DImode
,
3857 gen_rtx_AND (DImode
,
3858 plus_constant (dsta
, ofs
+ size
- 1),
3860 set_mem_alias_set (memh
, 0);
3862 emit_move_insn (dsth
, memh
);
3863 emit_move_insn (dstl
, meml
);
3864 if (WORDS_BIG_ENDIAN
)
3866 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
3868 if (src
!= const0_rtx
)
3873 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
3876 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
3879 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
3882 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
3883 GEN_INT (size
*8), addr
));
3889 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
3892 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffffffff), addr
));
3896 #if HOST_BITS_PER_WIDE_INT == 32
3897 rtx msk
= immed_double_const (0xffffffff, 0xffffffff, DImode
);
3899 rtx msk
= constm1_rtx
;
3901 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
3906 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
3910 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
3912 if (src
!= const0_rtx
)
3914 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
3915 GEN_INT (size
*8), addr
));
3920 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
3923 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
3926 emit_insn (gen_insql_le (insl
, src
, addr
));
3931 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
3936 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
3939 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffffffff), addr
));
3943 #if HOST_BITS_PER_WIDE_INT == 32
3944 rtx msk
= immed_double_const (0xffffffff, 0xffffffff, DImode
);
3946 rtx msk
= constm1_rtx
;
3948 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
3954 if (src
!= const0_rtx
)
3956 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
3957 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
3960 if (WORDS_BIG_ENDIAN
)
3962 emit_move_insn (meml
, dstl
);
3963 emit_move_insn (memh
, dsth
);
3967 /* Must store high before low for degenerate case of aligned. */
3968 emit_move_insn (memh
, dsth
);
3969 emit_move_insn (meml
, dstl
);
3973 /* The block move code tries to maximize speed by separating loads and
3974 stores at the expense of register pressure: we load all of the data
3975 before we store it back out. There are two secondary effects worth
3976 mentioning, that this speeds copying to/from aligned and unaligned
3977 buffers, and that it makes the code significantly easier to write. */
3979 #define MAX_MOVE_WORDS 8
3981 /* Load an integral number of consecutive unaligned quadwords. */
3984 alpha_expand_unaligned_load_words (out_regs
, smem
, words
, ofs
)
3987 HOST_WIDE_INT words
, ofs
;
3989 rtx
const im8
= GEN_INT (-8);
3990 rtx
const i64
= GEN_INT (64);
3991 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
3992 rtx sreg
, areg
, tmp
, smema
;
3995 smema
= XEXP (smem
, 0);
3996 if (GET_CODE (smema
) == LO_SUM
)
3997 smema
= force_reg (Pmode
, smema
);
3999 /* Generate all the tmp registers we need. */
4000 for (i
= 0; i
< words
; ++i
)
4002 data_regs
[i
] = out_regs
[i
];
4003 ext_tmps
[i
] = gen_reg_rtx (DImode
);
4005 data_regs
[words
] = gen_reg_rtx (DImode
);
4008 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
4010 /* Load up all of the source data. */
4011 for (i
= 0; i
< words
; ++i
)
4013 tmp
= change_address (smem
, DImode
,
4014 gen_rtx_AND (DImode
,
4015 plus_constant (smema
, 8*i
),
4017 set_mem_alias_set (tmp
, 0);
4018 emit_move_insn (data_regs
[i
], tmp
);
4021 tmp
= change_address (smem
, DImode
,
4022 gen_rtx_AND (DImode
,
4023 plus_constant (smema
, 8*words
- 1),
4025 set_mem_alias_set (tmp
, 0);
4026 emit_move_insn (data_regs
[words
], tmp
);
4028 /* Extract the half-word fragments. Unfortunately DEC decided to make
4029 extxh with offset zero a noop instead of zeroing the register, so
4030 we must take care of that edge condition ourselves with cmov. */
4032 sreg
= copy_addr_to_reg (smema
);
4033 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
4035 if (WORDS_BIG_ENDIAN
)
4036 emit_move_insn (sreg
, plus_constant (sreg
, 7));
4037 for (i
= 0; i
< words
; ++i
)
4039 if (WORDS_BIG_ENDIAN
)
4041 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
4042 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
4046 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
4047 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
4049 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
4050 gen_rtx_IF_THEN_ELSE (DImode
,
4051 gen_rtx_EQ (DImode
, areg
,
4053 const0_rtx
, ext_tmps
[i
])));
4056 /* Merge the half-words into whole words. */
4057 for (i
= 0; i
< words
; ++i
)
4059 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4060 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
4064 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4065 may be NULL to store zeros. */
4068 alpha_expand_unaligned_store_words (data_regs
, dmem
, words
, ofs
)
4071 HOST_WIDE_INT words
, ofs
;
4073 rtx
const im8
= GEN_INT (-8);
4074 rtx
const i64
= GEN_INT (64);
4075 #if HOST_BITS_PER_WIDE_INT == 32
4076 rtx
const im1
= immed_double_const (0xffffffff, 0xffffffff, DImode
);
4078 rtx
const im1
= constm1_rtx
;
4080 rtx ins_tmps
[MAX_MOVE_WORDS
];
4081 rtx st_tmp_1
, st_tmp_2
, dreg
;
4082 rtx st_addr_1
, st_addr_2
, dmema
;
4085 dmema
= XEXP (dmem
, 0);
4086 if (GET_CODE (dmema
) == LO_SUM
)
4087 dmema
= force_reg (Pmode
, dmema
);
4089 /* Generate all the tmp registers we need. */
4090 if (data_regs
!= NULL
)
4091 for (i
= 0; i
< words
; ++i
)
4092 ins_tmps
[i
] = gen_reg_rtx(DImode
);
4093 st_tmp_1
= gen_reg_rtx(DImode
);
4094 st_tmp_2
= gen_reg_rtx(DImode
);
4097 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
4099 st_addr_2
= change_address (dmem
, DImode
,
4100 gen_rtx_AND (DImode
,
4101 plus_constant (dmema
, words
*8 - 1),
4103 set_mem_alias_set (st_addr_2
, 0);
4105 st_addr_1
= change_address (dmem
, DImode
,
4106 gen_rtx_AND (DImode
, dmema
, im8
));
4107 set_mem_alias_set (st_addr_1
, 0);
4109 /* Load up the destination end bits. */
4110 emit_move_insn (st_tmp_2
, st_addr_2
);
4111 emit_move_insn (st_tmp_1
, st_addr_1
);
4113 /* Shift the input data into place. */
4114 dreg
= copy_addr_to_reg (dmema
);
4115 if (WORDS_BIG_ENDIAN
)
4116 emit_move_insn (dreg
, plus_constant (dreg
, 7));
4117 if (data_regs
!= NULL
)
4119 for (i
= words
-1; i
>= 0; --i
)
4121 if (WORDS_BIG_ENDIAN
)
4123 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
4124 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
4128 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
4129 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
4132 for (i
= words
-1; i
> 0; --i
)
4134 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4135 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
4140 /* Split and merge the ends with the destination data. */
4141 if (WORDS_BIG_ENDIAN
)
4143 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, im1
, dreg
));
4144 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
4148 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
4149 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, im1
, dreg
));
4152 if (data_regs
!= NULL
)
4154 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
4155 st_tmp_2
, 1, OPTAB_WIDEN
);
4156 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
4157 st_tmp_1
, 1, OPTAB_WIDEN
);
4161 if (WORDS_BIG_ENDIAN
)
4162 emit_move_insn (st_addr_1
, st_tmp_1
);
4164 emit_move_insn (st_addr_2
, st_tmp_2
);
4165 for (i
= words
-1; i
> 0; --i
)
4167 rtx tmp
= change_address (dmem
, DImode
,
4168 gen_rtx_AND (DImode
,
4169 plus_constant(dmema
,
4170 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
4172 set_mem_alias_set (tmp
, 0);
4173 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
4175 if (WORDS_BIG_ENDIAN
)
4176 emit_move_insn (st_addr_2
, st_tmp_2
);
4178 emit_move_insn (st_addr_1
, st_tmp_1
);
4182 /* Expand string/block move operations.
4184 operands[0] is the pointer to the destination.
4185 operands[1] is the pointer to the source.
4186 operands[2] is the number of bytes to move.
4187 operands[3] is the alignment. */
4190 alpha_expand_block_move (operands
)
4193 rtx bytes_rtx
= operands
[2];
4194 rtx align_rtx
= operands
[3];
4195 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4196 HOST_WIDE_INT bytes
= orig_bytes
;
4197 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4198 HOST_WIDE_INT dst_align
= src_align
;
4199 rtx orig_src
= operands
[1];
4200 rtx orig_dst
= operands
[0];
4201 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
4203 unsigned int i
, words
, ofs
, nregs
= 0;
4205 if (orig_bytes
<= 0)
4207 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4210 /* Look for additional alignment information from recorded register info. */
4212 tmp
= XEXP (orig_src
, 0);
4213 if (GET_CODE (tmp
) == REG
)
4214 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4215 else if (GET_CODE (tmp
) == PLUS
4216 && GET_CODE (XEXP (tmp
, 0)) == REG
4217 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4219 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4220 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4224 if (a
>= 64 && c
% 8 == 0)
4226 else if (a
>= 32 && c
% 4 == 0)
4228 else if (a
>= 16 && c
% 2 == 0)
4233 tmp
= XEXP (orig_dst
, 0);
4234 if (GET_CODE (tmp
) == REG
)
4235 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4236 else if (GET_CODE (tmp
) == PLUS
4237 && GET_CODE (XEXP (tmp
, 0)) == REG
4238 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4240 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4241 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4245 if (a
>= 64 && c
% 8 == 0)
4247 else if (a
>= 32 && c
% 4 == 0)
4249 else if (a
>= 16 && c
% 2 == 0)
4254 /* Load the entire block into registers. */
4255 if (GET_CODE (XEXP (orig_src
, 0)) == ADDRESSOF
)
4257 enum machine_mode mode
;
4259 tmp
= XEXP (XEXP (orig_src
, 0), 0);
4261 /* Don't use the existing register if we're reading more than
4262 is held in the register. Nor if there is not a mode that
4263 handles the exact size. */
4264 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4266 && GET_MODE_SIZE (GET_MODE (tmp
)) >= bytes
)
4270 data_regs
[nregs
] = gen_lowpart (DImode
, tmp
);
4271 data_regs
[nregs
+ 1] = gen_highpart (DImode
, tmp
);
4275 data_regs
[nregs
++] = gen_lowpart (mode
, tmp
);
4280 /* No appropriate mode; fall back on memory. */
4281 orig_src
= replace_equiv_address (orig_src
,
4282 copy_addr_to_reg (XEXP (orig_src
, 0)));
4283 src_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4287 if (src_align
>= 64 && bytes
>= 8)
4291 for (i
= 0; i
< words
; ++i
)
4292 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4294 for (i
= 0; i
< words
; ++i
)
4295 emit_move_insn (data_regs
[nregs
+ i
],
4296 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
4303 if (src_align
>= 32 && bytes
>= 4)
4307 for (i
= 0; i
< words
; ++i
)
4308 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
4310 for (i
= 0; i
< words
; ++i
)
4311 emit_move_insn (data_regs
[nregs
+ i
],
4312 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
4323 for (i
= 0; i
< words
+1; ++i
)
4324 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4326 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
4334 if (! TARGET_BWX
&& bytes
>= 4)
4336 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
4337 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
4344 if (src_align
>= 16)
4347 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4348 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
4351 } while (bytes
>= 2);
4353 else if (! TARGET_BWX
)
4355 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4356 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
4364 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
4365 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
4372 if (nregs
> ARRAY_SIZE (data_regs
))
4375 /* Now save it back out again. */
4379 if (GET_CODE (XEXP (orig_dst
, 0)) == ADDRESSOF
)
4381 enum machine_mode mode
;
4382 tmp
= XEXP (XEXP (orig_dst
, 0), 0);
4384 mode
= mode_for_size (orig_bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4385 if (GET_MODE (tmp
) == mode
)
4389 emit_move_insn (tmp
, data_regs
[0]);
4394 else if (nregs
== 2 && mode
== TImode
)
4396 /* Undo the subregging done above when copying between
4397 two TImode registers. */
4398 if (GET_CODE (data_regs
[0]) == SUBREG
4399 && GET_MODE (SUBREG_REG (data_regs
[0])) == TImode
)
4400 emit_move_insn (tmp
, SUBREG_REG (data_regs
[0]));
4406 emit_move_insn (gen_lowpart (DImode
, tmp
), data_regs
[0]);
4407 emit_move_insn (gen_highpart (DImode
, tmp
), data_regs
[1]);
4411 emit_no_conflict_block (seq
, tmp
, data_regs
[0],
4412 data_regs
[1], NULL_RTX
);
4420 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4421 /* ??? Optimize mode < dst_mode with strict_low_part. */
4423 /* No appropriate mode; fall back on memory. We can speed things
4424 up by recognizing extra alignment information. */
4425 orig_dst
= replace_equiv_address (orig_dst
,
4426 copy_addr_to_reg (XEXP (orig_dst
, 0)));
4427 dst_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4430 /* Write out the data in whatever chunks reading the source allowed. */
4431 if (dst_align
>= 64)
4433 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4435 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
4442 if (dst_align
>= 32)
4444 /* If the source has remaining DImode regs, write them out in
4446 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4448 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
4449 NULL_RTX
, 1, OPTAB_WIDEN
);
4451 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4452 gen_lowpart (SImode
, data_regs
[i
]));
4453 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
4454 gen_lowpart (SImode
, tmp
));
4459 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4461 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4468 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4470 /* Write out a remaining block of words using unaligned methods. */
4472 for (words
= 1; i
+ words
< nregs
; words
++)
4473 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4477 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4479 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4486 /* Due to the above, this won't be aligned. */
4487 /* ??? If we have more than one of these, consider constructing full
4488 words in registers and using alpha_expand_unaligned_store_words. */
4489 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4491 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4496 if (dst_align
>= 16)
4497 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4499 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4504 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4506 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4511 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
4513 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4527 alpha_expand_block_clear (operands
)
4530 rtx bytes_rtx
= operands
[1];
4531 rtx align_rtx
= operands
[2];
4532 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4533 HOST_WIDE_INT bytes
= orig_bytes
;
4534 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4535 HOST_WIDE_INT alignofs
= 0;
4536 rtx orig_dst
= operands
[0];
4538 int i
, words
, ofs
= 0;
4540 if (orig_bytes
<= 0)
4542 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4545 /* Look for stricter alignment. */
4546 tmp
= XEXP (orig_dst
, 0);
4547 if (GET_CODE (tmp
) == REG
)
4548 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4549 else if (GET_CODE (tmp
) == PLUS
4550 && GET_CODE (XEXP (tmp
, 0)) == REG
4551 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4553 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4554 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4559 align
= a
, alignofs
= 8 - c
% 8;
4561 align
= a
, alignofs
= 4 - c
% 4;
4563 align
= a
, alignofs
= 2 - c
% 2;
4566 else if (GET_CODE (tmp
) == ADDRESSOF
)
4568 enum machine_mode mode
;
4570 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4571 if (GET_MODE (XEXP (tmp
, 0)) == mode
)
4573 emit_move_insn (XEXP (tmp
, 0), const0_rtx
);
4577 /* No appropriate mode; fall back on memory. */
4578 orig_dst
= replace_equiv_address (orig_dst
, copy_addr_to_reg (tmp
));
4579 align
= GET_MODE_BITSIZE (GET_MODE (XEXP (tmp
, 0)));
4582 /* Handle an unaligned prefix first. */
4586 #if HOST_BITS_PER_WIDE_INT >= 64
4587 /* Given that alignofs is bounded by align, the only time BWX could
4588 generate three stores is for a 7 byte fill. Prefer two individual
4589 stores over a load/mask/store sequence. */
4590 if ((!TARGET_BWX
|| alignofs
== 7)
4592 && !(alignofs
== 4 && bytes
>= 4))
4594 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
4595 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
4599 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
4600 set_mem_alias_set (mem
, 0);
4602 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
4603 if (bytes
< alignofs
)
4605 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
4616 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
4617 NULL_RTX
, 1, OPTAB_WIDEN
);
4619 emit_move_insn (mem
, tmp
);
4623 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
4625 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4630 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
4632 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
4637 if (alignofs
== 4 && bytes
>= 4)
4639 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4645 /* If we've not used the extra lead alignment information by now,
4646 we won't be able to. Downgrade align to match what's left over. */
4649 alignofs
= alignofs
& -alignofs
;
4650 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
4654 /* Handle a block of contiguous long-words. */
4656 if (align
>= 64 && bytes
>= 8)
4660 for (i
= 0; i
< words
; ++i
)
4661 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
4668 /* If the block is large and appropriately aligned, emit a single
4669 store followed by a sequence of stq_u insns. */
4671 if (align
>= 32 && bytes
> 16)
4675 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4679 orig_dsta
= XEXP (orig_dst
, 0);
4680 if (GET_CODE (orig_dsta
) == LO_SUM
)
4681 orig_dsta
= force_reg (Pmode
, orig_dsta
);
4684 for (i
= 0; i
< words
; ++i
)
4687 = change_address (orig_dst
, DImode
,
4688 gen_rtx_AND (DImode
,
4689 plus_constant (orig_dsta
, ofs
+ i
*8),
4691 set_mem_alias_set (mem
, 0);
4692 emit_move_insn (mem
, const0_rtx
);
4695 /* Depending on the alignment, the first stq_u may have overlapped
4696 with the initial stl, which means that the last stq_u didn't
4697 write as much as it would appear. Leave those questionable bytes
4699 bytes
-= words
* 8 - 4;
4700 ofs
+= words
* 8 - 4;
4703 /* Handle a smaller block of aligned words. */
4705 if ((align
>= 64 && bytes
== 4)
4706 || (align
== 32 && bytes
>= 4))
4710 for (i
= 0; i
< words
; ++i
)
4711 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
4718 /* An unaligned block uses stq_u stores for as many as possible. */
4724 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
4730 /* Next clean up any trailing pieces. */
4732 #if HOST_BITS_PER_WIDE_INT >= 64
4733 /* Count the number of bits in BYTES for which aligned stores could
4736 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
4740 /* If we have appropriate alignment (and it wouldn't take too many
4741 instructions otherwise), mask out the bytes we need. */
4742 if (TARGET_BWX
? words
> 2 : bytes
> 0)
4749 mem
= adjust_address (orig_dst
, DImode
, ofs
);
4750 set_mem_alias_set (mem
, 0);
4752 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4754 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
4755 NULL_RTX
, 1, OPTAB_WIDEN
);
4757 emit_move_insn (mem
, tmp
);
4760 else if (align
>= 32 && bytes
< 4)
4765 mem
= adjust_address (orig_dst
, SImode
, ofs
);
4766 set_mem_alias_set (mem
, 0);
4768 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4770 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
4771 NULL_RTX
, 1, OPTAB_WIDEN
);
4773 emit_move_insn (mem
, tmp
);
4779 if (!TARGET_BWX
&& bytes
>= 4)
4781 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
4791 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
4795 } while (bytes
>= 2);
4797 else if (! TARGET_BWX
)
4799 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
4807 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4815 /* Adjust the cost of a scheduling dependency. Return the new cost of
4816 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4819 alpha_adjust_cost (insn
, link
, dep_insn
, cost
)
4826 enum attr_type insn_type
, dep_insn_type
;
4828 /* If the dependence is an anti-dependence, there is no cost. For an
4829 output dependence, there is sometimes a cost, but it doesn't seem
4830 worth handling those few cases. */
4832 if (REG_NOTE_KIND (link
) != 0)
4835 /* If we can't recognize the insns, we can't really do anything. */
4836 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
4839 insn_type
= get_attr_type (insn
);
4840 dep_insn_type
= get_attr_type (dep_insn
);
4842 /* Bring in the user-defined memory latency. */
4843 if (dep_insn_type
== TYPE_ILD
4844 || dep_insn_type
== TYPE_FLD
4845 || dep_insn_type
== TYPE_LDSYM
)
4846 cost
+= alpha_memory_latency
-1;
4851 /* On EV4, if INSN is a store insn and DEP_INSN is setting the data
4852 being stored, we can sometimes lower the cost. */
4854 if ((insn_type
== TYPE_IST
|| insn_type
== TYPE_FST
)
4855 && (set
= single_set (dep_insn
)) != 0
4856 && GET_CODE (PATTERN (insn
)) == SET
4857 && rtx_equal_p (SET_DEST (set
), SET_SRC (PATTERN (insn
))))
4859 switch (dep_insn_type
)
4863 /* No savings here. */
4867 /* In these cases, we save one cycle. */
4871 /* In all other cases, we save two cycles. */
4872 return MAX (0, cost
- 2);
4876 /* Another case that needs adjustment is an arithmetic or logical
4877 operation. It's cost is usually one cycle, but we default it to
4878 two in the MD file. The only case that it is actually two is
4879 for the address in loads, stores, and jumps. */
4881 if (dep_insn_type
== TYPE_IADD
|| dep_insn_type
== TYPE_ILOG
)
4896 /* The final case is when a compare feeds into an integer branch;
4897 the cost is only one cycle in that case. */
4899 if (dep_insn_type
== TYPE_ICMP
&& insn_type
== TYPE_IBR
)
4904 /* And the lord DEC saith: "A special bypass provides an effective
4905 latency of 0 cycles for an ICMP or ILOG insn producing the test
4906 operand of an IBR or ICMOV insn." */
4908 if ((dep_insn_type
== TYPE_ICMP
|| dep_insn_type
== TYPE_ILOG
)
4909 && (set
= single_set (dep_insn
)) != 0)
4911 /* A branch only has one input. This must be it. */
4912 if (insn_type
== TYPE_IBR
)
4914 /* A conditional move has three, make sure it is the test. */
4915 if (insn_type
== TYPE_ICMOV
4916 && GET_CODE (set_src
= PATTERN (insn
)) == SET
4917 && GET_CODE (set_src
= SET_SRC (set_src
)) == IF_THEN_ELSE
4918 && rtx_equal_p (SET_DEST (set
), XEXP (set_src
, 0)))
4922 /* "The multiplier is unable to receive data from IEU bypass paths.
4923 The instruction issues at the expected time, but its latency is
4924 increased by the time it takes for the input data to become
4925 available to the multiplier" -- which happens in pipeline stage
4926 six, when results are comitted to the register file. */
4928 if (insn_type
== TYPE_IMUL
)
4930 switch (dep_insn_type
)
4932 /* These insns produce their results in pipeline stage five. */
4939 /* Other integer insns produce results in pipeline stage four. */
4947 /* There is additional latency to move the result of (most) FP
4948 operations anywhere but the FP register file. */
4950 if ((insn_type
== TYPE_FST
|| insn_type
== TYPE_FTOI
)
4951 && (dep_insn_type
== TYPE_FADD
||
4952 dep_insn_type
== TYPE_FMUL
||
4953 dep_insn_type
== TYPE_FCMOV
))
4959 /* Otherwise, return the default cost. */
4963 /* Function to initialize the issue rate used by the scheduler. */
4967 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
4971 alpha_variable_issue (dump
, verbose
, insn
, cim
)
4972 FILE *dump ATTRIBUTE_UNUSED
;
4973 int verbose ATTRIBUTE_UNUSED
;
4977 if (recog_memoized (insn
) < 0 || get_attr_type (insn
) == TYPE_MULTI
)
4984 /* Register global variables and machine-specific functions with the
4985 garbage collector. */
4987 #if TARGET_ABI_UNICOSMK
4989 alpha_init_machine_status (p
)
4993 (struct machine_function
*) xcalloc (1, sizeof (struct machine_function
));
4995 p
->machine
->first_ciw
= NULL_RTX
;
4996 p
->machine
->last_ciw
= NULL_RTX
;
4997 p
->machine
->ciw_count
= 0;
4998 p
->machine
->addr_list
= NULL_RTX
;
5002 alpha_mark_machine_status (p
)
5005 struct machine_function
*machine
= p
->machine
;
5009 ggc_mark_rtx (machine
->first_ciw
);
5010 ggc_mark_rtx (machine
->addr_list
);
5015 alpha_free_machine_status (p
)
5021 #endif /* TARGET_ABI_UNICOSMK */
5023 /* Functions to save and restore alpha_return_addr_rtx. */
5025 /* Start the ball rolling with RETURN_ADDR_RTX. */
5028 alpha_return_addr (count
, frame
)
5030 rtx frame ATTRIBUTE_UNUSED
;
5035 return get_hard_reg_initial_val (Pmode
, REG_RA
);
5038 /* Return or create a pseudo containing the gp value for the current
5039 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5042 alpha_gp_save_rtx ()
5044 rtx r
= get_hard_reg_initial_val (DImode
, 29);
5045 if (GET_CODE (r
) != MEM
)
5046 r
= gen_mem_addressof (r
, NULL_TREE
);
5051 alpha_ra_ever_killed ()
5055 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
5056 return regs_ever_live
[REG_RA
];
5058 push_topmost_sequence ();
5060 pop_topmost_sequence ();
5062 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
5066 /* Return the trap mode suffix applicable to the current
5067 instruction, or NULL. */
5070 get_trap_mode_suffix ()
5072 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
5076 case TRAP_SUFFIX_NONE
:
5079 case TRAP_SUFFIX_SU
:
5080 if (alpha_fptm
>= ALPHA_FPTM_SU
)
5084 case TRAP_SUFFIX_SUI
:
5085 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
5089 case TRAP_SUFFIX_V_SV
:
5097 case ALPHA_FPTM_SUI
:
5102 case TRAP_SUFFIX_V_SV_SVI
:
5111 case ALPHA_FPTM_SUI
:
5116 case TRAP_SUFFIX_U_SU_SUI
:
5125 case ALPHA_FPTM_SUI
:
5133 /* Return the rounding mode suffix applicable to the current
5134 instruction, or NULL. */
5137 get_round_mode_suffix ()
5139 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5143 case ROUND_SUFFIX_NONE
:
5145 case ROUND_SUFFIX_NORMAL
:
5148 case ALPHA_FPRM_NORM
:
5150 case ALPHA_FPRM_MINF
:
5152 case ALPHA_FPRM_CHOP
:
5154 case ALPHA_FPRM_DYN
:
5159 case ROUND_SUFFIX_C
:
5165 /* Print an operand. Recognize special options, documented below. */
5168 print_operand (file
, x
, code
)
5178 /* Print the assembler name of the current function. */
5179 assemble_name (file
, alpha_fnname
);
5184 const char *trap
= get_trap_mode_suffix ();
5185 const char *round
= get_round_mode_suffix ();
5188 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5189 (trap
? trap
: ""), (round
? round
: ""));
5194 /* Generates single precision instruction suffix. */
5195 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5199 /* Generates double precision instruction suffix. */
5200 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5204 if (alpha_this_literal_sequence_number
== 0)
5205 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5206 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5210 if (alpha_this_gpdisp_sequence_number
== 0)
5211 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5212 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5216 if (GET_CODE (x
) == HIGH
)
5217 output_addr_const (file
, XEXP (x
, 0));
5219 output_operand_lossage ("invalid %%H value");
5223 if (GET_CODE (x
) == CONST_INT
)
5225 if (INTVAL (x
) != 0)
5226 fprintf (file
, "\t\t!lituse_jsr!%d", (int) INTVAL (x
));
5229 output_operand_lossage ("invalid %%J value");
5233 /* If this operand is the constant zero, write it as "$31". */
5234 if (GET_CODE (x
) == REG
)
5235 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5236 else if (x
== CONST0_RTX (GET_MODE (x
)))
5237 fprintf (file
, "$31");
5239 output_operand_lossage ("invalid %%r value");
5243 /* Similar, but for floating-point. */
5244 if (GET_CODE (x
) == REG
)
5245 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5246 else if (x
== CONST0_RTX (GET_MODE (x
)))
5247 fprintf (file
, "$f31");
5249 output_operand_lossage ("invalid %%R value");
5253 /* Write the 1's complement of a constant. */
5254 if (GET_CODE (x
) != CONST_INT
)
5255 output_operand_lossage ("invalid %%N value");
5257 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5261 /* Write 1 << C, for a constant C. */
5262 if (GET_CODE (x
) != CONST_INT
)
5263 output_operand_lossage ("invalid %%P value");
5265 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5269 /* Write the high-order 16 bits of a constant, sign-extended. */
5270 if (GET_CODE (x
) != CONST_INT
)
5271 output_operand_lossage ("invalid %%h value");
5273 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5277 /* Write the low-order 16 bits of a constant, sign-extended. */
5278 if (GET_CODE (x
) != CONST_INT
)
5279 output_operand_lossage ("invalid %%L value");
5281 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5282 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5286 /* Write mask for ZAP insn. */
5287 if (GET_CODE (x
) == CONST_DOUBLE
)
5289 HOST_WIDE_INT mask
= 0;
5290 HOST_WIDE_INT value
;
5292 value
= CONST_DOUBLE_LOW (x
);
5293 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5298 value
= CONST_DOUBLE_HIGH (x
);
5299 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5302 mask
|= (1 << (i
+ sizeof (int)));
5304 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5307 else if (GET_CODE (x
) == CONST_INT
)
5309 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5311 for (i
= 0; i
< 8; i
++, value
>>= 8)
5315 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5318 output_operand_lossage ("invalid %%m value");
5322 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5323 if (GET_CODE (x
) != CONST_INT
5324 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5325 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5326 output_operand_lossage ("invalid %%M value");
5328 fprintf (file
, "%s",
5329 (INTVAL (x
) == 8 ? "b"
5330 : INTVAL (x
) == 16 ? "w"
5331 : INTVAL (x
) == 32 ? "l"
5336 /* Similar, except do it from the mask. */
5337 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0xff)
5338 fprintf (file
, "b");
5339 else if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0xffff)
5340 fprintf (file
, "w");
5341 else if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0xffffffff)
5342 fprintf (file
, "l");
5343 #if HOST_BITS_PER_WIDE_INT == 32
5344 else if (GET_CODE (x
) == CONST_DOUBLE
5345 && CONST_DOUBLE_HIGH (x
) == 0
5346 && CONST_DOUBLE_LOW (x
) == -1)
5347 fprintf (file
, "l");
5348 else if (GET_CODE (x
) == CONST_DOUBLE
5349 && CONST_DOUBLE_HIGH (x
) == -1
5350 && CONST_DOUBLE_LOW (x
) == -1)
5351 fprintf (file
, "q");
5353 else if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == -1)
5354 fprintf (file
, "q");
5355 else if (GET_CODE (x
) == CONST_DOUBLE
5356 && CONST_DOUBLE_HIGH (x
) == 0
5357 && CONST_DOUBLE_LOW (x
) == -1)
5358 fprintf (file
, "q");
5361 output_operand_lossage ("invalid %%U value");
5365 /* Write the constant value divided by 8 for little-endian mode or
5366 (56 - value) / 8 for big-endian mode. */
5368 if (GET_CODE (x
) != CONST_INT
5369 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5372 || (INTVAL (x
) & 7) != 0)
5373 output_operand_lossage ("invalid %%s value");
5375 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5377 ? (56 - INTVAL (x
)) / 8
5382 /* Same, except compute (64 - c) / 8 */
5384 if (GET_CODE (x
) != CONST_INT
5385 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5386 && (INTVAL (x
) & 7) != 8)
5387 output_operand_lossage ("invalid %%s value");
5389 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5394 /* On Unicos/Mk systems: use a DEX expression if the symbol
5395 clashes with a register name. */
5396 int dex
= unicosmk_need_dex (x
);
5398 fprintf (file
, "DEX(%d)", dex
);
5400 output_addr_const (file
, x
);
5404 case 'C': case 'D': case 'c': case 'd':
5405 /* Write out comparison name. */
5407 enum rtx_code c
= GET_CODE (x
);
5409 if (GET_RTX_CLASS (c
) != '<')
5410 output_operand_lossage ("invalid %%C value");
5412 else if (code
== 'D')
5413 c
= reverse_condition (c
);
5414 else if (code
== 'c')
5415 c
= swap_condition (c
);
5416 else if (code
== 'd')
5417 c
= swap_condition (reverse_condition (c
));
5420 fprintf (file
, "ule");
5422 fprintf (file
, "ult");
5423 else if (c
== UNORDERED
)
5424 fprintf (file
, "un");
5426 fprintf (file
, "%s", GET_RTX_NAME (c
));
5431 /* Write the divide or modulus operator. */
5432 switch (GET_CODE (x
))
5435 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5438 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5441 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5444 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5447 output_operand_lossage ("invalid %%E value");
5453 /* Write "_u" for unaligned access. */
5454 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
5455 fprintf (file
, "_u");
5459 if (GET_CODE (x
) == REG
)
5460 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5461 else if (GET_CODE (x
) == MEM
)
5462 output_address (XEXP (x
, 0));
5464 output_addr_const (file
, x
);
5468 output_operand_lossage ("invalid %%xn code");
5473 print_operand_address (file
, addr
)
5478 HOST_WIDE_INT offset
= 0;
5480 if (GET_CODE (addr
) == AND
)
5481 addr
= XEXP (addr
, 0);
5483 if (GET_CODE (addr
) == PLUS
5484 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5486 offset
= INTVAL (XEXP (addr
, 1));
5487 addr
= XEXP (addr
, 0);
5490 if (GET_CODE (addr
) == LO_SUM
)
5492 output_addr_const (file
, XEXP (addr
, 1));
5496 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
5499 addr
= XEXP (addr
, 0);
5500 if (GET_CODE (addr
) == REG
)
5501 basereg
= REGNO (addr
);
5502 else if (GET_CODE (addr
) == SUBREG
5503 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5504 basereg
= subreg_regno (addr
);
5508 fprintf (file
, "($%d)\t\t!%s", basereg
,
5509 (basereg
== 29 ? "gprel" : "gprellow"));
5513 if (GET_CODE (addr
) == REG
)
5514 basereg
= REGNO (addr
);
5515 else if (GET_CODE (addr
) == SUBREG
5516 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5517 basereg
= subreg_regno (addr
);
5518 else if (GET_CODE (addr
) == CONST_INT
)
5519 offset
= INTVAL (addr
);
5523 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
5524 fprintf (file
, "($%d)", basereg
);
5527 /* Emit RTL insns to initialize the variable parts of a trampoline at
5528 TRAMP. FNADDR is an RTX for the address of the function's pure
5529 code. CXT is an RTX for the static chain value for the function.
5531 The three offset parameters are for the individual template's
5532 layout. A JMPOFS < 0 indicates that the trampoline does not
5533 contain instructions at all.
5535 We assume here that a function will be called many more times than
5536 its address is taken (e.g., it might be passed to qsort), so we
5537 take the trouble to initialize the "hint" field in the JMP insn.
5538 Note that the hint field is PC (new) + 4 * bits 13:0. */
5541 alpha_initialize_trampoline (tramp
, fnaddr
, cxt
, fnofs
, cxtofs
, jmpofs
)
5542 rtx tramp
, fnaddr
, cxt
;
5543 int fnofs
, cxtofs
, jmpofs
;
5545 rtx temp
, temp1
, addr
;
5546 /* VMS really uses DImode pointers in memory at this point. */
5547 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
5549 #ifdef POINTERS_EXTEND_UNSIGNED
5550 fnaddr
= convert_memory_address (mode
, fnaddr
);
5551 cxt
= convert_memory_address (mode
, cxt
);
5554 /* Store function address and CXT. */
5555 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
5556 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
5557 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
5558 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
5560 /* This has been disabled since the hint only has a 32k range, and in
5561 no existing OS is the stack within 32k of the text segment. */
5562 if (0 && jmpofs
>= 0)
5564 /* Compute hint value. */
5565 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
5566 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
5568 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
5569 build_int_2 (2, 0), NULL_RTX
, 1);
5570 temp
= expand_and (SImode
, gen_lowpart (SImode
, temp
),
5571 GEN_INT (0x3fff), 0);
5573 /* Merge in the hint. */
5574 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
5575 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
5576 temp1
= expand_and (SImode
, temp1
, GEN_INT (0xffffc000), NULL_RTX
);
5577 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
5579 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
5582 #ifdef TRANSFER_FROM_TRAMPOLINE
5583 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
5584 0, VOIDmode
, 1, addr
, Pmode
);
5588 emit_insn (gen_imb ());
5591 /* Determine where to put an argument to a function.
5592 Value is zero to push the argument on the stack,
5593 or a hard register in which to store the argument.
5595 MODE is the argument's machine mode.
5596 TYPE is the data type of the argument (as a tree).
5597 This is null for libcalls where that information may
5599 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5600 the preceding args and about the function being called.
5601 NAMED is nonzero if this argument is a named parameter
5602 (otherwise it is an extra parameter matching an ellipsis).
5604 On Alpha the first 6 words of args are normally in registers
5605 and the rest are pushed. */
5608 function_arg (cum
, mode
, type
, named
)
5609 CUMULATIVE_ARGS cum
;
5610 enum machine_mode mode
;
5612 int named ATTRIBUTE_UNUSED
;
5617 /* Set up defaults for FP operands passed in FP registers, and
5618 integral operands passed in integer registers. */
5620 && (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5621 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
5626 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5627 the three platforms, so we can't avoid conditional compilation. */
5628 #if TARGET_ABI_OPEN_VMS
5630 if (mode
== VOIDmode
)
5631 return alpha_arg_info_reg_val (cum
);
5633 num_args
= cum
.num_args
;
5634 if (num_args
>= 6 || MUST_PASS_IN_STACK (mode
, type
))
5638 #if TARGET_ABI_UNICOSMK
5642 /* If this is the last argument, generate the call info word (CIW). */
5643 /* ??? We don't include the caller's line number in the CIW because
5644 I don't know how to determine it if debug infos are turned off. */
5645 if (mode
== VOIDmode
)
5654 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
5655 if (cum
.reg_args_type
[i
])
5656 lo
|= (1 << (7 - i
));
5658 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
5661 lo
|= cum
.num_reg_words
;
5663 #if HOST_BITS_PER_WIDE_INT == 32
5664 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
5666 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
5667 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
5670 ciw
= immed_double_const (lo
, hi
, DImode
);
5672 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
5673 UNSPEC_UMK_LOAD_CIW
);
5676 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
5677 num_args
= cum
.num_reg_words
;
5678 if (MUST_PASS_IN_STACK (mode
, type
)
5679 || cum
.num_reg_words
+ size
> 6 || cum
.force_stack
)
5681 else if (type
&& TYPE_MODE (type
) == BLKmode
)
5685 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
5686 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
5688 /* The argument fits in two registers. Note that we still need to
5689 reserve a register for empty structures. */
5693 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
5696 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
5697 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
5698 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
5708 /* VOID is passed as a special flag for "last argument". */
5709 if (type
== void_type_node
)
5711 else if (MUST_PASS_IN_STACK (mode
, type
))
5713 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum
, mode
, type
, named
))
5716 #endif /* TARGET_ABI_UNICOSMK */
5717 #endif /* TARGET_ABI_OPEN_VMS */
5719 return gen_rtx_REG (mode
, num_args
+ basereg
);
5723 alpha_build_va_list ()
5725 tree base
, ofs
, record
, type_decl
;
5727 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
5728 return ptr_type_node
;
5730 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
5731 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
5732 TREE_CHAIN (record
) = type_decl
;
5733 TYPE_NAME (record
) = type_decl
;
5735 /* C++? SET_IS_AGGR_TYPE (record, 1); */
5737 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
5739 DECL_FIELD_CONTEXT (ofs
) = record
;
5741 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
5743 DECL_FIELD_CONTEXT (base
) = record
;
5744 TREE_CHAIN (base
) = ofs
;
5746 TYPE_FIELDS (record
) = base
;
5747 layout_type (record
);
5753 alpha_va_start (stdarg_p
, valist
, nextarg
)
5756 rtx nextarg ATTRIBUTE_UNUSED
;
5758 HOST_WIDE_INT offset
;
5759 tree t
, offset_field
, base_field
;
5761 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
5764 if (TARGET_ABI_UNICOSMK
)
5765 std_expand_builtin_va_start (stdarg_p
, valist
, nextarg
);
5767 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
5768 up by 48, storing fp arg registers in the first 48 bytes, and the
5769 integer arg registers in the next 48 bytes. This is only done,
5770 however, if any integer registers need to be stored.
5772 If no integer registers need be stored, then we must subtract 48
5773 in order to account for the integer arg registers which are counted
5774 in argsize above, but which are not actually stored on the stack. */
5776 if (NUM_ARGS
<= 5 + stdarg_p
)
5777 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
5779 offset
= -6 * UNITS_PER_WORD
;
5781 if (TARGET_ABI_OPEN_VMS
)
5783 nextarg
= plus_constant (nextarg
, offset
);
5784 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
5785 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
5786 make_tree (ptr_type_node
, nextarg
));
5787 TREE_SIDE_EFFECTS (t
) = 1;
5789 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5793 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
5794 offset_field
= TREE_CHAIN (base_field
);
5796 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
5797 valist
, base_field
);
5798 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
5799 valist
, offset_field
);
5801 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
5802 t
= build (PLUS_EXPR
, ptr_type_node
, t
, build_int_2 (offset
, 0));
5803 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
5804 TREE_SIDE_EFFECTS (t
) = 1;
5805 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5807 t
= build_int_2 (NUM_ARGS
* UNITS_PER_WORD
, 0);
5808 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
5809 TREE_SIDE_EFFECTS (t
) = 1;
5810 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5815 alpha_va_arg (valist
, type
)
5819 tree t
, type_size
, rounded_size
;
5820 tree offset_field
, base_field
, addr_tree
, addend
;
5821 tree wide_type
, wide_ofs
;
5824 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
5825 return std_expand_builtin_va_arg (valist
, type
);
5827 if (type
== error_mark_node
5828 || (type_size
= TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type
))) == NULL
5829 || TREE_OVERFLOW (type_size
))
5830 rounded_size
= size_zero_node
;
5832 rounded_size
= fold (build (MULT_EXPR
, sizetype
,
5833 fold (build (TRUNC_DIV_EXPR
, sizetype
,
5834 fold (build (PLUS_EXPR
, sizetype
,
5840 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
5841 offset_field
= TREE_CHAIN (base_field
);
5843 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
5844 valist
, base_field
);
5845 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
5846 valist
, offset_field
);
5848 /* If the type could not be passed in registers, skip the block
5849 reserved for the registers. */
5850 if (MUST_PASS_IN_STACK (TYPE_MODE (type
), type
))
5852 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
5853 build (MAX_EXPR
, TREE_TYPE (offset_field
),
5854 offset_field
, build_int_2 (6*8, 0)));
5855 TREE_SIDE_EFFECTS (t
) = 1;
5856 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5859 wide_type
= make_signed_type (64);
5860 wide_ofs
= save_expr (build1 (CONVERT_EXPR
, wide_type
, offset_field
));
5864 if (TYPE_MODE (type
) == TFmode
|| TYPE_MODE (type
) == TCmode
)
5867 rounded_size
= size_int (UNITS_PER_WORD
);
5869 else if (FLOAT_TYPE_P (type
))
5871 tree fpaddend
, cond
;
5873 fpaddend
= fold (build (PLUS_EXPR
, TREE_TYPE (addend
),
5874 addend
, build_int_2 (-6*8, 0)));
5876 cond
= fold (build (LT_EXPR
, integer_type_node
,
5877 wide_ofs
, build_int_2 (6*8, 0)));
5879 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
5883 addr_tree
= build (PLUS_EXPR
, TREE_TYPE (base_field
),
5884 base_field
, addend
);
5886 addr
= expand_expr (addr_tree
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
5887 addr
= copy_to_reg (addr
);
5889 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
5890 build (PLUS_EXPR
, TREE_TYPE (offset_field
),
5891 offset_field
, rounded_size
));
5892 TREE_SIDE_EFFECTS (t
) = 1;
5893 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5897 addr
= force_reg (Pmode
, addr
);
5898 addr
= gen_rtx_MEM (Pmode
, addr
);
5904 /* This page contains routines that are used to determine what the function
5905 prologue and epilogue code will do and write them out. */
5907 /* Compute the size of the save area in the stack. */
5909 /* These variables are used for communication between the following functions.
5910 They indicate various things about the current function being compiled
5911 that are used to tell what kind of prologue, epilogue and procedure
5912 descriptior to generate. */
5914 /* Nonzero if we need a stack procedure. */
5915 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
5916 static enum alpha_procedure_types alpha_procedure_type
;
5918 /* Register number (either FP or SP) that is used to unwind the frame. */
5919 static int vms_unwind_regno
;
5921 /* Register number used to save FP. We need not have one for RA since
5922 we don't modify it for register procedures. This is only defined
5923 for register frame procedures. */
5924 static int vms_save_fp_regno
;
5926 /* Register number used to reference objects off our PV. */
5927 static int vms_base_regno
;
5929 /* Compute register masks for saved registers. */
5932 alpha_sa_mask (imaskP
, fmaskP
)
5933 unsigned long *imaskP
;
5934 unsigned long *fmaskP
;
5936 unsigned long imask
= 0;
5937 unsigned long fmask
= 0;
5940 /* Irritatingly, there are two kinds of thunks -- those created with
5941 ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go through
5942 the regular part of the compiler. In the ASM_OUTPUT_MI_THUNK case
5943 we don't have valid register life info, but assemble_start_function
5944 wants to output .frame and .mask directives. */
5945 if (current_function_is_thunk
&& !no_new_pseudos
)
5952 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
5953 imask
|= (1L << HARD_FRAME_POINTER_REGNUM
);
5955 /* One for every register we have to save. */
5956 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5957 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
5958 && regs_ever_live
[i
] && i
!= REG_RA
5959 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
5964 fmask
|= (1L << (i
- 32));
5967 /* We need to restore these for the handler. */
5968 if (current_function_calls_eh_return
)
5971 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
5972 if (regno
== INVALID_REGNUM
)
5974 imask
|= 1L << regno
;
5977 /* If any register spilled, then spill the return address also. */
5978 /* ??? This is required by the Digital stack unwind specification
5979 and isn't needed if we're doing Dwarf2 unwinding. */
5980 if (imask
|| fmask
|| alpha_ra_ever_killed ())
5981 imask
|= (1L << REG_RA
);
5990 unsigned long mask
[2];
5994 alpha_sa_mask (&mask
[0], &mask
[1]);
5996 if (TARGET_ABI_UNICOSMK
)
5998 if (mask
[0] || mask
[1])
6003 for (j
= 0; j
< 2; ++j
)
6004 for (i
= 0; i
< 32; ++i
)
6005 if ((mask
[j
] >> i
) & 1)
6009 if (TARGET_ABI_UNICOSMK
)
6011 /* We might not need to generate a frame if we don't make any calls
6012 (including calls to __T3E_MISMATCH if this is a vararg function),
6013 don't have any local variables which require stack slots, don't
6014 use alloca and have not determined that we need a frame for other
6017 alpha_procedure_type
6018 = (sa_size
|| get_frame_size() != 0
6019 || current_function_outgoing_args_size
|| current_function_varargs
6020 || current_function_stdarg
|| current_function_calls_alloca
6021 || frame_pointer_needed
)
6022 ? PT_STACK
: PT_REGISTER
;
6024 /* Always reserve space for saving callee-saved registers if we
6025 need a frame as required by the calling convention. */
6026 if (alpha_procedure_type
== PT_STACK
)
6029 else if (TARGET_ABI_OPEN_VMS
)
6031 /* Start by assuming we can use a register procedure if we don't
6032 make any calls (REG_RA not used) or need to save any
6033 registers and a stack procedure if we do. */
6034 if ((mask
[0] >> REG_RA
) & 1)
6035 alpha_procedure_type
= PT_STACK
;
6036 else if (get_frame_size() != 0)
6037 alpha_procedure_type
= PT_REGISTER
;
6039 alpha_procedure_type
= PT_NULL
;
6041 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6042 made the final decision on stack procedure vs register procedure. */
6043 if (alpha_procedure_type
== PT_STACK
)
6046 /* Decide whether to refer to objects off our PV via FP or PV.
6047 If we need FP for something else or if we receive a nonlocal
6048 goto (which expects PV to contain the value), we must use PV.
6049 Otherwise, start by assuming we can use FP. */
6052 = (frame_pointer_needed
6053 || current_function_has_nonlocal_label
6054 || alpha_procedure_type
== PT_STACK
6055 || current_function_outgoing_args_size
)
6056 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
6058 /* If we want to copy PV into FP, we need to find some register
6059 in which to save FP. */
6061 vms_save_fp_regno
= -1;
6062 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
6063 for (i
= 0; i
< 32; i
++)
6064 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
6065 vms_save_fp_regno
= i
;
6067 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
6068 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
6069 else if (alpha_procedure_type
== PT_NULL
)
6070 vms_base_regno
= REG_PV
;
6072 /* Stack unwinding should be done via FP unless we use it for PV. */
6073 vms_unwind_regno
= (vms_base_regno
== REG_PV
6074 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
6076 /* If this is a stack procedure, allow space for saving FP and RA. */
6077 if (alpha_procedure_type
== PT_STACK
)
6082 /* Our size must be even (multiple of 16 bytes). */
6091 alpha_pv_save_size ()
6094 return alpha_procedure_type
== PT_STACK
? 8 : 0;
6101 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
6104 #if TARGET_ABI_OPEN_VMS
6106 const struct attribute_spec vms_attribute_table
[] =
6108 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6109 { "overlaid", 0, 0, true, false, false, NULL
},
6110 { "global", 0, 0, true, false, false, NULL
},
6111 { "initialize", 0, 0, true, false, false, NULL
},
6112 { NULL
, 0, 0, false, false, false, NULL
}
6118 find_lo_sum (px
, data
)
6120 void *data ATTRIBUTE_UNUSED
;
6122 return GET_CODE (*px
) == LO_SUM
;
6126 alpha_does_function_need_gp ()
6130 /* The GP being variable is an OSF abi thing. */
6131 if (! TARGET_ABI_OSF
)
6134 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6137 if (current_function_is_thunk
)
6140 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6141 Even if we are a static function, we still need to do this in case
6142 our address is taken and passed to something like qsort. */
6144 push_topmost_sequence ();
6145 insn
= get_insns ();
6146 pop_topmost_sequence ();
6148 for (; insn
; insn
= NEXT_INSN (insn
))
6150 && GET_CODE (PATTERN (insn
)) != USE
6151 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6153 enum attr_type type
= get_attr_type (insn
);
6154 if (type
== TYPE_LDSYM
|| type
== TYPE_JSR
)
6156 if (TARGET_EXPLICIT_RELOCS
6157 && for_each_rtx (&PATTERN (insn
), find_lo_sum
, NULL
) > 0)
6164 /* Write a version stamp. Don't write anything if we are running as a
6165 cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
6172 alpha_write_verstamp (file
)
6173 FILE *file ATTRIBUTE_UNUSED
;
6176 fprintf (file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
6180 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6184 set_frame_related_p ()
6186 rtx seq
= gen_sequence ();
6189 if (GET_CODE (seq
) == SEQUENCE
)
6191 int i
= XVECLEN (seq
, 0);
6193 RTX_FRAME_RELATED_P (XVECEXP (seq
, 0, i
)) = 1;
6194 return emit_insn (seq
);
6198 seq
= emit_insn (seq
);
6199 RTX_FRAME_RELATED_P (seq
) = 1;
6204 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
6206 /* Write function prologue. */
6208 /* On vms we have two kinds of functions:
6210 - stack frame (PROC_STACK)
6211 these are 'normal' functions with local vars and which are
6212 calling other functions
6213 - register frame (PROC_REGISTER)
6214 keeps all data in registers, needs no stack
6216 We must pass this to the assembler so it can generate the
6217 proper pdsc (procedure descriptor)
6218 This is done with the '.pdesc' command.
6220 On not-vms, we don't really differentiate between the two, as we can
6221 simply allocate stack without saving registers. */
6224 alpha_expand_prologue ()
6226 /* Registers to save. */
6227 unsigned long imask
= 0;
6228 unsigned long fmask
= 0;
6229 /* Stack space needed for pushing registers clobbered by us. */
6230 HOST_WIDE_INT sa_size
;
6231 /* Complete stack size needed. */
6232 HOST_WIDE_INT frame_size
;
6233 /* Offset from base reg to register save area. */
6234 HOST_WIDE_INT reg_offset
;
6238 sa_size
= alpha_sa_size ();
6240 frame_size
= get_frame_size ();
6241 if (TARGET_ABI_OPEN_VMS
)
6242 frame_size
= ALPHA_ROUND (sa_size
6243 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
6245 + current_function_pretend_args_size
);
6246 else if (TARGET_ABI_UNICOSMK
)
6247 /* We have to allocate space for the DSIB if we generate a frame. */
6248 frame_size
= ALPHA_ROUND (sa_size
6249 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
6250 + ALPHA_ROUND (frame_size
6251 + current_function_outgoing_args_size
);
6253 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
6255 + ALPHA_ROUND (frame_size
6256 + current_function_pretend_args_size
));
6258 if (TARGET_ABI_OPEN_VMS
)
6261 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
6263 alpha_sa_mask (&imask
, &fmask
);
6265 /* Emit an insn to reload GP, if needed. */
6268 alpha_function_needs_gp
= alpha_does_function_need_gp ();
6269 if (alpha_function_needs_gp
)
6270 emit_insn (gen_prologue_ldgp ());
6273 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
6274 the call to mcount ourselves, rather than having the linker do it
6275 magically in response to -pg. Since _mcount has special linkage,
6276 don't represent the call as a call. */
6277 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6278 emit_insn (gen_prologue_mcount ());
6280 if (TARGET_ABI_UNICOSMK
)
6281 unicosmk_gen_dsib (&imask
);
6283 /* Adjust the stack by the frame size. If the frame size is > 4096
6284 bytes, we need to be sure we probe somewhere in the first and last
6285 4096 bytes (we can probably get away without the latter test) and
6286 every 8192 bytes in between. If the frame size is > 32768, we
6287 do this in a loop. Otherwise, we generate the explicit probe
6290 Note that we are only allowed to adjust sp once in the prologue. */
6292 if (frame_size
<= 32768)
6294 if (frame_size
> 4096)
6299 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
6302 while ((probed
+= 8192) < frame_size
);
6304 /* We only have to do this probe if we aren't saving registers. */
6305 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
6306 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
6309 if (frame_size
!= 0)
6310 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
6311 GEN_INT (TARGET_ABI_UNICOSMK
6317 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
6318 number of 8192 byte blocks to probe. We then probe each block
6319 in the loop and then set SP to the proper location. If the
6320 amount remaining is > 4096, we have to do one more probe if we
6321 are not saving any registers. */
6323 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
6324 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
6325 rtx ptr
= gen_rtx_REG (DImode
, 22);
6326 rtx count
= gen_rtx_REG (DImode
, 23);
6329 emit_move_insn (count
, GEN_INT (blocks
));
6330 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
6331 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
6333 /* Because of the difficulty in emitting a new basic block this
6334 late in the compilation, generate the loop as a single insn. */
6335 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
6337 if (leftover
> 4096 && sa_size
== 0)
6339 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
6340 MEM_VOLATILE_P (last
) = 1;
6341 emit_move_insn (last
, const0_rtx
);
6344 if (TARGET_ABI_WINDOWS_NT
)
6346 /* For NT stack unwind (done by 'reverse execution'), it's
6347 not OK to take the result of a loop, even though the value
6348 is already in ptr, so we reload it via a single operation
6349 and subtract it to sp.
6351 Yes, that's correct -- we have to reload the whole constant
6352 into a temporary via ldah+lda then subtract from sp. To
6353 ensure we get ldah+lda, we use a special pattern. */
6355 HOST_WIDE_INT lo
, hi
;
6356 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
6357 hi
= frame_size
- lo
;
6359 emit_move_insn (ptr
, GEN_INT (hi
));
6360 emit_insn (gen_nt_lda (ptr
, GEN_INT (lo
)));
6361 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
6366 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
6367 GEN_INT (-leftover
)));
6370 /* This alternative is special, because the DWARF code cannot
6371 possibly intuit through the loop above. So we invent this
6372 note it looks at instead. */
6373 RTX_FRAME_RELATED_P (seq
) = 1;
6375 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
6376 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
6377 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
6378 GEN_INT (TARGET_ABI_UNICOSMK
6384 if (!TARGET_ABI_UNICOSMK
)
6386 /* Cope with very large offsets to the register save area. */
6387 sa_reg
= stack_pointer_rtx
;
6388 if (reg_offset
+ sa_size
> 0x8000)
6390 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
6393 if (low
+ sa_size
<= 0x8000)
6394 bias
= reg_offset
- low
, reg_offset
= low
;
6396 bias
= reg_offset
, reg_offset
= 0;
6398 sa_reg
= gen_rtx_REG (DImode
, 24);
6399 FRP (emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
,
6403 /* Save regs in stack order. Beginning with VMS PV. */
6404 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6406 mem
= gen_rtx_MEM (DImode
, stack_pointer_rtx
);
6407 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6408 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_PV
)));
6411 /* Save register RA next. */
6412 if (imask
& (1L << REG_RA
))
6414 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
6415 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6416 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
6417 imask
&= ~(1L << REG_RA
);
6421 /* Now save any other registers required to be saved. */
6422 for (i
= 0; i
< 32; i
++)
6423 if (imask
& (1L << i
))
6425 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
6426 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6427 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
6431 for (i
= 0; i
< 32; i
++)
6432 if (fmask
& (1L << i
))
6434 mem
= gen_rtx_MEM (DFmode
, plus_constant (sa_reg
, reg_offset
));
6435 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6436 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
6440 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
6442 /* The standard frame on the T3E includes space for saving registers.
6443 We just have to use it. We don't have to save the return address and
6444 the old frame pointer here - they are saved in the DSIB. */
6447 for (i
= 9; i
< 15; i
++)
6448 if (imask
& (1L << i
))
6450 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
6452 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6453 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
6456 for (i
= 2; i
< 10; i
++)
6457 if (fmask
& (1L << i
))
6459 mem
= gen_rtx_MEM (DFmode
, plus_constant (hard_frame_pointer_rtx
,
6461 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6462 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
6467 if (TARGET_ABI_OPEN_VMS
)
6469 if (alpha_procedure_type
== PT_REGISTER
)
6470 /* Register frame procedures save the fp.
6471 ?? Ought to have a dwarf2 save for this. */
6472 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
6473 hard_frame_pointer_rtx
);
6475 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
6476 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
6477 gen_rtx_REG (DImode
, REG_PV
)));
6479 if (alpha_procedure_type
!= PT_NULL
6480 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
6481 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
6483 /* If we have to allocate space for outgoing args, do it now. */
6484 if (current_function_outgoing_args_size
!= 0)
6487 plus_constant (hard_frame_pointer_rtx
,
6489 (current_function_outgoing_args_size
)))));
6491 else if (!TARGET_ABI_UNICOSMK
)
6493 /* If we need a frame pointer, set it from the stack pointer. */
6494 if (frame_pointer_needed
)
6496 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
6497 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
6499 /* This must always be the last instruction in the
6500 prologue, thus we emit a special move + clobber. */
6501 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
6502 stack_pointer_rtx
, sa_reg
)));
6506 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
6507 the prologue, for exception handling reasons, we cannot do this for
6508 any insn that might fault. We could prevent this for mems with a
6509 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
6510 have to prevent all such scheduling with a blockage.
6512 Linux, on the other hand, never bothered to implement OSF/1's
6513 exception handling, and so doesn't care about such things. Anyone
6514 planning to use dwarf2 frame-unwind info can also omit the blockage. */
6516 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
6517 emit_insn (gen_blockage ());
6520 /* Output the textual info surrounding the prologue. */
6523 alpha_start_function (file
, fnname
, decl
)
6526 tree decl ATTRIBUTE_UNUSED
;
6528 unsigned long imask
= 0;
6529 unsigned long fmask
= 0;
6530 /* Stack space needed for pushing registers clobbered by us. */
6531 HOST_WIDE_INT sa_size
;
6532 /* Complete stack size needed. */
6533 HOST_WIDE_INT frame_size
;
6534 /* Offset from base reg to register save area. */
6535 HOST_WIDE_INT reg_offset
;
6536 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
6539 /* Don't emit an extern directive for functions defined in the same file. */
6540 if (TARGET_ABI_UNICOSMK
)
6543 name_tree
= get_identifier (fnname
);
6544 TREE_ASM_WRITTEN (name_tree
) = 1;
6547 alpha_fnname
= fnname
;
6548 sa_size
= alpha_sa_size ();
6550 frame_size
= get_frame_size ();
6551 if (TARGET_ABI_OPEN_VMS
)
6552 frame_size
= ALPHA_ROUND (sa_size
6553 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
6555 + current_function_pretend_args_size
);
6556 else if (TARGET_ABI_UNICOSMK
)
6557 frame_size
= ALPHA_ROUND (sa_size
6558 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
6559 + ALPHA_ROUND (frame_size
6560 + current_function_outgoing_args_size
);
6562 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
6564 + ALPHA_ROUND (frame_size
6565 + current_function_pretend_args_size
));
6567 if (TARGET_ABI_OPEN_VMS
)
6570 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
6572 alpha_sa_mask (&imask
, &fmask
);
6574 /* Ecoff can handle multiple .file directives, so put out file and lineno.
6575 We have to do that before the .ent directive as we cannot switch
6576 files within procedures with native ecoff because line numbers are
6577 linked to procedure descriptors.
6578 Outputting the lineno helps debugging of one line functions as they
6579 would otherwise get no line number at all. Please note that we would
6580 like to put out last_linenum from final.c, but it is not accessible. */
6582 if (write_symbols
== SDB_DEBUG
)
6584 #ifdef ASM_OUTPUT_SOURCE_FILENAME
6585 ASM_OUTPUT_SOURCE_FILENAME (file
,
6586 DECL_SOURCE_FILE (current_function_decl
));
6588 #ifdef ASM_OUTPUT_SOURCE_LINE
6589 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
6590 ASM_OUTPUT_SOURCE_LINE (file
,
6591 DECL_SOURCE_LINE (current_function_decl
));
6595 /* Issue function start and label. */
6596 if (TARGET_ABI_OPEN_VMS
6597 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
6599 fputs ("\t.ent ", file
);
6600 assemble_name (file
, fnname
);
6603 /* If the function needs GP, we'll write the "..ng" label there.
6604 Otherwise, do it here. */
6606 && ! alpha_function_needs_gp
6607 && ! current_function_is_thunk
)
6610 assemble_name (file
, fnname
);
6611 fputs ("..ng:\n", file
);
6615 strcpy (entry_label
, fnname
);
6616 if (TARGET_ABI_OPEN_VMS
)
6617 strcat (entry_label
, "..en");
6619 /* For public functions, the label must be globalized by appending an
6620 additional colon. */
6621 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
6622 strcat (entry_label
, ":");
6624 ASM_OUTPUT_LABEL (file
, entry_label
);
6625 inside_function
= TRUE
;
6627 if (TARGET_ABI_OPEN_VMS
)
6628 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
6630 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
6631 && !flag_inhibit_size_directive
)
6633 /* Set flags in procedure descriptor to request IEEE-conformant
6634 math-library routines. The value we set it to is PDSC_EXC_IEEE
6635 (/usr/include/pdsc.h). */
6636 fputs ("\t.eflag 48\n", file
);
6639 /* Set up offsets to alpha virtual arg/local debugging pointer. */
6640 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
6641 alpha_arg_offset
= -frame_size
+ 48;
6643 /* Describe our frame. If the frame size is larger than an integer,
6644 print it as zero to avoid an assembler error. We won't be
6645 properly describing such a frame, but that's the best we can do. */
6646 if (TARGET_ABI_UNICOSMK
)
6648 else if (TARGET_ABI_OPEN_VMS
)
6650 fprintf (file
, "\t.frame $%d,", vms_unwind_regno
);
6651 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6652 frame_size
>= ((HOST_WIDE_INT
) 1 << 31) ? 0 : frame_size
);
6653 fputs (",$26,", file
);
6654 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, reg_offset
);
6657 else if (!flag_inhibit_size_directive
)
6659 fprintf (file
, "\t.frame $%d,",
6660 (frame_pointer_needed
6661 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
));
6662 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6663 frame_size
>= (1l << 31) ? 0 : frame_size
);
6664 fprintf (file
, ",$26,%d\n", current_function_pretend_args_size
);
6667 /* Describe which registers were spilled. */
6668 if (TARGET_ABI_UNICOSMK
)
6670 else if (TARGET_ABI_OPEN_VMS
)
6673 /* ??? Does VMS care if mask contains ra? The old code didn't
6674 set it, so I don't here. */
6675 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1L << REG_RA
));
6677 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
6678 if (alpha_procedure_type
== PT_REGISTER
)
6679 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
6681 else if (!flag_inhibit_size_directive
)
6685 fprintf (file
, "\t.mask 0x%lx,", imask
);
6686 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6687 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
6690 for (i
= 0; i
< 32; ++i
)
6691 if (imask
& (1L << i
))
6697 fprintf (file
, "\t.fmask 0x%lx,", fmask
);
6698 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6699 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
6704 #if TARGET_ABI_OPEN_VMS
6705 /* Ifdef'ed cause readonly_section and link_section are only
6707 readonly_section ();
6708 fprintf (file
, "\t.align 3\n");
6709 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
6710 fputs ("\t.ascii \"", file
);
6711 assemble_name (file
, fnname
);
6712 fputs ("\\0\"\n", file
);
6715 fprintf (file
, "\t.align 3\n");
6716 fputs ("\t.name ", file
);
6717 assemble_name (file
, fnname
);
6718 fputs ("..na\n", file
);
6719 ASM_OUTPUT_LABEL (file
, fnname
);
6720 fprintf (file
, "\t.pdesc ");
6721 assemble_name (file
, fnname
);
6722 fprintf (file
, "..en,%s\n",
6723 alpha_procedure_type
== PT_STACK
? "stack"
6724 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
6725 alpha_need_linkage (fnname
, 1);
6730 /* Emit the .prologue note at the scheduled end of the prologue. */
6733 alpha_output_function_end_prologue (file
)
6736 if (TARGET_ABI_UNICOSMK
)
6738 else if (TARGET_ABI_OPEN_VMS
)
6739 fputs ("\t.prologue\n", file
);
6740 else if (TARGET_ABI_WINDOWS_NT
)
6741 fputs ("\t.prologue 0\n", file
);
6742 else if (!flag_inhibit_size_directive
)
6743 fprintf (file
, "\t.prologue %d\n",
6744 alpha_function_needs_gp
|| current_function_is_thunk
);
6747 /* Write function epilogue. */
6749 /* ??? At some point we will want to support full unwind, and so will
6750 need to mark the epilogue as well. At the moment, we just confuse
6753 #define FRP(exp) exp
6756 alpha_expand_epilogue ()
6758 /* Registers to save. */
6759 unsigned long imask
= 0;
6760 unsigned long fmask
= 0;
6761 /* Stack space needed for pushing registers clobbered by us. */
6762 HOST_WIDE_INT sa_size
;
6763 /* Complete stack size needed. */
6764 HOST_WIDE_INT frame_size
;
6765 /* Offset from base reg to register save area. */
6766 HOST_WIDE_INT reg_offset
;
6767 int fp_is_frame_pointer
, fp_offset
;
6768 rtx sa_reg
, sa_reg_exp
= NULL
;
6769 rtx sp_adj1
, sp_adj2
, mem
;
6773 sa_size
= alpha_sa_size ();
6775 frame_size
= get_frame_size ();
6776 if (TARGET_ABI_OPEN_VMS
)
6777 frame_size
= ALPHA_ROUND (sa_size
6778 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
6780 + current_function_pretend_args_size
);
6781 else if (TARGET_ABI_UNICOSMK
)
6782 frame_size
= ALPHA_ROUND (sa_size
6783 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
6784 + ALPHA_ROUND (frame_size
6785 + current_function_outgoing_args_size
);
6787 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
6789 + ALPHA_ROUND (frame_size
6790 + current_function_pretend_args_size
));
6792 if (TARGET_ABI_OPEN_VMS
)
6794 if (alpha_procedure_type
== PT_STACK
)
6800 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
6802 alpha_sa_mask (&imask
, &fmask
);
6805 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6806 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
6808 sa_reg
= stack_pointer_rtx
;
6810 if (current_function_calls_eh_return
)
6811 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
6815 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
6817 /* If we have a frame pointer, restore SP from it. */
6818 if ((TARGET_ABI_OPEN_VMS
6819 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
6820 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
6821 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
6823 /* Cope with very large offsets to the register save area. */
6824 if (reg_offset
+ sa_size
> 0x8000)
6826 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
6829 if (low
+ sa_size
<= 0x8000)
6830 bias
= reg_offset
- low
, reg_offset
= low
;
6832 bias
= reg_offset
, reg_offset
= 0;
6834 sa_reg
= gen_rtx_REG (DImode
, 22);
6835 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
6837 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
6840 /* Restore registers in order, excepting a true frame pointer. */
6842 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
6844 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6845 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
6848 imask
&= ~(1L << REG_RA
);
6850 for (i
= 0; i
< 32; ++i
)
6851 if (imask
& (1L << i
))
6853 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
6854 fp_offset
= reg_offset
;
6857 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
6858 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6859 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
6864 for (i
= 0; i
< 32; ++i
)
6865 if (fmask
& (1L << i
))
6867 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
6868 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6869 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
6873 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
6875 /* Restore callee-saved general-purpose registers. */
6879 for (i
= 9; i
< 15; i
++)
6880 if (imask
& (1L << i
))
6882 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
6884 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6885 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
6889 for (i
= 2; i
< 10; i
++)
6890 if (fmask
& (1L << i
))
6892 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
6894 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6895 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
6899 /* Restore the return address from the DSIB. */
6901 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
6902 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6903 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
6906 if (frame_size
|| eh_ofs
)
6908 sp_adj1
= stack_pointer_rtx
;
6912 sp_adj1
= gen_rtx_REG (DImode
, 23);
6913 emit_move_insn (sp_adj1
,
6914 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
6917 /* If the stack size is large, begin computation into a temporary
6918 register so as not to interfere with a potential fp restore,
6919 which must be consecutive with an SP restore. */
6920 if (frame_size
< 32768
6921 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
6922 sp_adj2
= GEN_INT (frame_size
);
6923 else if (TARGET_ABI_UNICOSMK
)
6925 sp_adj1
= gen_rtx_REG (DImode
, 23);
6926 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
6927 sp_adj2
= const0_rtx
;
6929 else if (frame_size
< 0x40007fffL
)
6931 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
6933 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
6934 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
6938 sp_adj1
= gen_rtx_REG (DImode
, 23);
6939 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
6941 sp_adj2
= GEN_INT (low
);
6945 rtx tmp
= gen_rtx_REG (DImode
, 23);
6946 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
6949 /* We can't drop new things to memory this late, afaik,
6950 so build it up by pieces. */
6951 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
6952 -(frame_size
< 0)));
6958 /* From now on, things must be in order. So emit blockages. */
6960 /* Restore the frame pointer. */
6961 if (TARGET_ABI_UNICOSMK
)
6963 emit_insn (gen_blockage ());
6964 mem
= gen_rtx_MEM (DImode
,
6965 plus_constant (hard_frame_pointer_rtx
, -16));
6966 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6967 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
6969 else if (fp_is_frame_pointer
)
6971 emit_insn (gen_blockage ());
6972 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
6973 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6974 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
6976 else if (TARGET_ABI_OPEN_VMS
)
6978 emit_insn (gen_blockage ());
6979 FRP (emit_move_insn (hard_frame_pointer_rtx
,
6980 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
6983 /* Restore the stack pointer. */
6984 emit_insn (gen_blockage ());
6985 if (sp_adj2
== const0_rtx
)
6986 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
6988 FRP (emit_move_insn (stack_pointer_rtx
,
6989 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
6993 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
6995 emit_insn (gen_blockage ());
6996 FRP (emit_move_insn (hard_frame_pointer_rtx
,
6997 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
6999 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
7001 /* Decrement the frame pointer if the function does not have a
7004 emit_insn (gen_blockage ());
7005 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7006 hard_frame_pointer_rtx
, GEN_INT (-1))));
7011 /* Output the rest of the textual info surrounding the epilogue. */
7014 alpha_end_function (file
, fnname
, decl
)
7017 tree decl ATTRIBUTE_UNUSED
;
7019 /* End the function. */
7020 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
7022 fputs ("\t.end ", file
);
7023 assemble_name (file
, fnname
);
7026 inside_function
= FALSE
;
7028 /* Show that we know this function if it is called again.
7030 Don't do this for global functions in object files destined for a
7031 shared library because the function may be overridden by the application
7032 or other libraries. Similarly, don't do this for weak functions.
7034 Don't do this for functions not defined in the .text section, as
7035 otherwise it's not unlikely that the destination is out of range
7036 for a direct branch. */
7038 if (!DECL_WEAK (current_function_decl
)
7039 && (!flag_pic
|| !TREE_PUBLIC (current_function_decl
))
7040 && decl_in_text_section (current_function_decl
))
7041 SYMBOL_REF_FLAG (XEXP (DECL_RTL (current_function_decl
), 0)) = 1;
7043 /* Output jump tables and the static subroutine information block. */
7044 if (TARGET_ABI_UNICOSMK
)
7046 unicosmk_output_ssib (file
, fnname
);
7047 unicosmk_output_deferred_case_vectors (file
);
7051 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7053 In order to avoid the hordes of differences between generated code
7054 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7055 lots of code loading up large constants, generate rtl and emit it
7056 instead of going straight to text.
7058 Not sure why this idea hasn't been explored before... */
7061 alpha_output_mi_thunk_osf (file
, thunk_fndecl
, delta
, function
)
7063 tree thunk_fndecl ATTRIBUTE_UNUSED
;
7064 HOST_WIDE_INT delta
;
7067 HOST_WIDE_INT hi
, lo
;
7068 rtx
this, insn
, funexp
;
7070 /* We always require a valid GP. */
7071 emit_insn (gen_prologue_ldgp ());
7072 emit_note (NULL
, NOTE_INSN_PROLOGUE_END
);
7074 /* Find the "this" pointer. If the function returns a structure,
7075 the structure return pointer is in $16. */
7076 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
))))
7077 this = gen_rtx_REG (Pmode
, 17);
7079 this = gen_rtx_REG (Pmode
, 16);
7081 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7082 entire constant for the add. */
7083 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
7084 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7085 if (hi
+ lo
== delta
)
7088 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
7090 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
7094 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
7095 delta
, -(delta
< 0));
7096 emit_insn (gen_adddi3 (this, this, tmp
));
7099 /* Generate a tail call to the target function. */
7100 if (! TREE_USED (function
))
7102 assemble_external (function
);
7103 TREE_USED (function
) = 1;
7105 funexp
= XEXP (DECL_RTL (function
), 0);
7106 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
7107 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
7108 SIBLING_CALL_P (insn
) = 1;
7110 /* Run just enough of rest_of_compilation to get the insns emitted.
7111 There's not really enough bulk here to make other passes such as
7112 instruction scheduling worth while. Note that use_thunk calls
7113 assemble_start_function and assemble_end_function. */
7114 insn
= get_insns ();
7115 shorten_branches (insn
);
7116 final_start_function (insn
, file
, 1);
7117 final (insn
, file
, 1, 0);
7118 final_end_function ();
7121 /* Debugging support. */
7125 /* Count the number of sdb related labels are generated (to find block
7126 start and end boundaries). */
7128 int sdb_label_count
= 0;
7130 /* Next label # for each statement. */
7132 static int sym_lineno
= 0;
7134 /* Count the number of .file directives, so that .loc is up to date. */
7136 static int num_source_filenames
= 0;
7138 /* Name of the file containing the current function. */
7140 static const char *current_function_file
= "";
7142 /* Offsets to alpha virtual arg/local debugging pointers. */
7144 long alpha_arg_offset
;
7145 long alpha_auto_offset
;
7147 /* Emit a new filename to a stream. */
7150 alpha_output_filename (stream
, name
)
7154 static int first_time
= TRUE
;
7155 char ltext_label_name
[100];
7160 ++num_source_filenames
;
7161 current_function_file
= name
;
7162 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7163 output_quoted_string (stream
, name
);
7164 fprintf (stream
, "\n");
7165 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
7166 fprintf (stream
, "\t#@stabs\n");
7169 else if (write_symbols
== DBX_DEBUG
)
7171 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
7172 fprintf (stream
, "%s", ASM_STABS_OP
);
7173 output_quoted_string (stream
, name
);
7174 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
7177 else if (name
!= current_function_file
7178 && strcmp (name
, current_function_file
) != 0)
7180 if (inside_function
&& ! TARGET_GAS
)
7181 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
7184 ++num_source_filenames
;
7185 current_function_file
= name
;
7186 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7189 output_quoted_string (stream
, name
);
7190 fprintf (stream
, "\n");
7194 /* Emit a linenumber to a stream. */
7197 alpha_output_lineno (stream
, line
)
7201 if (write_symbols
== DBX_DEBUG
)
7203 /* mips-tfile doesn't understand .stabd directives. */
7205 fprintf (stream
, "$LM%d:\n%s%d,0,%d,$LM%d\n",
7206 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
7209 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
7212 /* Structure to show the current status of registers and memory. */
7214 struct shadow_summary
7217 unsigned int i
: 31; /* Mask of int regs */
7218 unsigned int fp
: 31; /* Mask of fp regs */
7219 unsigned int mem
: 1; /* mem == imem | fpmem */
7223 static void summarize_insn
PARAMS ((rtx
, struct shadow_summary
*, int));
7224 static void alpha_handle_trap_shadows
PARAMS ((rtx
));
7226 /* Summary the effects of expression X on the machine. Update SUM, a pointer
7227 to the summary structure. SET is nonzero if the insn is setting the
7228 object, otherwise zero. */
7231 summarize_insn (x
, sum
, set
)
7233 struct shadow_summary
*sum
;
7236 const char *format_ptr
;
7242 switch (GET_CODE (x
))
7244 /* ??? Note that this case would be incorrect if the Alpha had a
7245 ZERO_EXTRACT in SET_DEST. */
7247 summarize_insn (SET_SRC (x
), sum
, 0);
7248 summarize_insn (SET_DEST (x
), sum
, 1);
7252 summarize_insn (XEXP (x
, 0), sum
, 1);
7256 summarize_insn (XEXP (x
, 0), sum
, 0);
7260 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
7261 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
7265 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
7266 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
7270 summarize_insn (SUBREG_REG (x
), sum
, 0);
7275 int regno
= REGNO (x
);
7276 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
7278 if (regno
== 31 || regno
== 63)
7284 sum
->defd
.i
|= mask
;
7286 sum
->defd
.fp
|= mask
;
7291 sum
->used
.i
|= mask
;
7293 sum
->used
.fp
|= mask
;
7304 /* Find the regs used in memory address computation: */
7305 summarize_insn (XEXP (x
, 0), sum
, 0);
7308 case CONST_INT
: case CONST_DOUBLE
:
7309 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
7310 case SCRATCH
: case ASM_INPUT
:
7313 /* Handle common unary and binary ops for efficiency. */
7314 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
7315 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
7316 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
7317 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
7318 case NE
: case EQ
: case GE
: case GT
: case LE
:
7319 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
7320 summarize_insn (XEXP (x
, 0), sum
, 0);
7321 summarize_insn (XEXP (x
, 1), sum
, 0);
7324 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
7325 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
7326 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
7327 case SQRT
: case FFS
:
7328 summarize_insn (XEXP (x
, 0), sum
, 0);
7332 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
7333 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
7334 switch (format_ptr
[i
])
7337 summarize_insn (XEXP (x
, i
), sum
, 0);
7341 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7342 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
7354 /* Ensure a sufficient number of `trapb' insns are in the code when
7355 the user requests code with a trap precision of functions or
7358 In naive mode, when the user requests a trap-precision of
7359 "instruction", a trapb is needed after every instruction that may
7360 generate a trap. This ensures that the code is resumption safe but
7363 When optimizations are turned on, we delay issuing a trapb as long
7364 as possible. In this context, a trap shadow is the sequence of
7365 instructions that starts with a (potentially) trap generating
7366 instruction and extends to the next trapb or call_pal instruction
7367 (but GCC never generates call_pal by itself). We can delay (and
7368 therefore sometimes omit) a trapb subject to the following
7371 (a) On entry to the trap shadow, if any Alpha register or memory
7372 location contains a value that is used as an operand value by some
7373 instruction in the trap shadow (live on entry), then no instruction
7374 in the trap shadow may modify the register or memory location.
7376 (b) Within the trap shadow, the computation of the base register
7377 for a memory load or store instruction may not involve using the
7378 result of an instruction that might generate an UNPREDICTABLE
7381 (c) Within the trap shadow, no register may be used more than once
7382 as a destination register. (This is to make life easier for the
7385 (d) The trap shadow may not include any branch instructions. */
7388 alpha_handle_trap_shadows (insns
)
7391 struct shadow_summary shadow
;
7392 int trap_pending
, exception_nesting
;
7396 exception_nesting
= 0;
7399 shadow
.used
.mem
= 0;
7400 shadow
.defd
= shadow
.used
;
7402 for (i
= insns
; i
; i
= NEXT_INSN (i
))
7404 if (GET_CODE (i
) == NOTE
)
7406 switch (NOTE_LINE_NUMBER (i
))
7408 case NOTE_INSN_EH_REGION_BEG
:
7409 exception_nesting
++;
7414 case NOTE_INSN_EH_REGION_END
:
7415 exception_nesting
--;
7420 case NOTE_INSN_EPILOGUE_BEG
:
7421 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
7426 else if (trap_pending
)
7428 if (alpha_tp
== ALPHA_TP_FUNC
)
7430 if (GET_CODE (i
) == JUMP_INSN
7431 && GET_CODE (PATTERN (i
)) == RETURN
)
7434 else if (alpha_tp
== ALPHA_TP_INSN
)
7438 struct shadow_summary sum
;
7443 sum
.defd
= sum
.used
;
7445 switch (GET_CODE (i
))
7448 /* Annoyingly, get_attr_trap will abort on these. */
7449 if (GET_CODE (PATTERN (i
)) == USE
7450 || GET_CODE (PATTERN (i
)) == CLOBBER
)
7453 summarize_insn (PATTERN (i
), &sum
, 0);
7455 if ((sum
.defd
.i
& shadow
.defd
.i
)
7456 || (sum
.defd
.fp
& shadow
.defd
.fp
))
7458 /* (c) would be violated */
7462 /* Combine shadow with summary of current insn: */
7463 shadow
.used
.i
|= sum
.used
.i
;
7464 shadow
.used
.fp
|= sum
.used
.fp
;
7465 shadow
.used
.mem
|= sum
.used
.mem
;
7466 shadow
.defd
.i
|= sum
.defd
.i
;
7467 shadow
.defd
.fp
|= sum
.defd
.fp
;
7468 shadow
.defd
.mem
|= sum
.defd
.mem
;
7470 if ((sum
.defd
.i
& shadow
.used
.i
)
7471 || (sum
.defd
.fp
& shadow
.used
.fp
)
7472 || (sum
.defd
.mem
& shadow
.used
.mem
))
7474 /* (a) would be violated (also takes care of (b)) */
7475 if (get_attr_trap (i
) == TRAP_YES
7476 && ((sum
.defd
.i
& sum
.used
.i
)
7477 || (sum
.defd
.fp
& sum
.used
.fp
)))
7496 n
= emit_insn_before (gen_trapb (), i
);
7497 PUT_MODE (n
, TImode
);
7498 PUT_MODE (i
, TImode
);
7502 shadow
.used
.mem
= 0;
7503 shadow
.defd
= shadow
.used
;
7508 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
7509 && GET_CODE (i
) == INSN
7510 && GET_CODE (PATTERN (i
)) != USE
7511 && GET_CODE (PATTERN (i
)) != CLOBBER
7512 && get_attr_trap (i
) == TRAP_YES
)
7514 if (optimize
&& !trap_pending
)
7515 summarize_insn (PATTERN (i
), &shadow
, 0);
7521 /* Alpha can only issue instruction groups simultaneously if they are
7522 suitibly aligned. This is very processor-specific. */
7524 enum alphaev4_pipe
{
7531 enum alphaev5_pipe
{
7542 static enum alphaev4_pipe alphaev4_insn_pipe
PARAMS ((rtx
));
7543 static enum alphaev5_pipe alphaev5_insn_pipe
PARAMS ((rtx
));
7544 static rtx alphaev4_next_group
PARAMS ((rtx
, int *, int *));
7545 static rtx alphaev5_next_group
PARAMS ((rtx
, int *, int *));
7546 static rtx alphaev4_next_nop
PARAMS ((int *));
7547 static rtx alphaev5_next_nop
PARAMS ((int *));
7549 static void alpha_align_insns
7550 PARAMS ((rtx
, unsigned int, rtx (*)(rtx
, int *, int *), rtx (*)(int *)));
7552 static enum alphaev4_pipe
7553 alphaev4_insn_pipe (insn
)
7556 if (recog_memoized (insn
) < 0)
7558 if (get_attr_length (insn
) != 4)
7561 switch (get_attr_type (insn
))
7594 static enum alphaev5_pipe
7595 alphaev5_insn_pipe (insn
)
7598 if (recog_memoized (insn
) < 0)
7600 if (get_attr_length (insn
) != 4)
7603 switch (get_attr_type (insn
))
7643 /* IN_USE is a mask of the slots currently filled within the insn group.
7644 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
7645 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
7647 LEN is, of course, the length of the group in bytes. */
7650 alphaev4_next_group (insn
, pin_use
, plen
)
7652 int *pin_use
, *plen
;
7659 || GET_CODE (PATTERN (insn
)) == CLOBBER
7660 || GET_CODE (PATTERN (insn
)) == USE
)
7665 enum alphaev4_pipe pipe
;
7667 pipe
= alphaev4_insn_pipe (insn
);
7671 /* Force complex instructions to start new groups. */
7675 /* If this is a completely unrecognized insn, its an asm.
7676 We don't know how long it is, so record length as -1 to
7677 signal a needed realignment. */
7678 if (recog_memoized (insn
) < 0)
7681 len
= get_attr_length (insn
);
7685 if (in_use
& EV4_IB0
)
7687 if (in_use
& EV4_IB1
)
7692 in_use
|= EV4_IB0
| EV4_IBX
;
7696 if (in_use
& EV4_IB0
)
7698 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
7706 if (in_use
& EV4_IB1
)
7716 /* Haifa doesn't do well scheduling branches. */
7717 if (GET_CODE (insn
) == JUMP_INSN
)
7721 insn
= next_nonnote_insn (insn
);
7723 if (!insn
|| ! INSN_P (insn
))
7726 /* Let Haifa tell us where it thinks insn group boundaries are. */
7727 if (GET_MODE (insn
) == TImode
)
7730 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
7735 insn
= next_nonnote_insn (insn
);
7743 /* IN_USE is a mask of the slots currently filled within the insn group.
7744 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
7745 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
7747 LEN is, of course, the length of the group in bytes. */
7750 alphaev5_next_group (insn
, pin_use
, plen
)
7752 int *pin_use
, *plen
;
7759 || GET_CODE (PATTERN (insn
)) == CLOBBER
7760 || GET_CODE (PATTERN (insn
)) == USE
)
7765 enum alphaev5_pipe pipe
;
7767 pipe
= alphaev5_insn_pipe (insn
);
7771 /* Force complex instructions to start new groups. */
7775 /* If this is a completely unrecognized insn, its an asm.
7776 We don't know how long it is, so record length as -1 to
7777 signal a needed realignment. */
7778 if (recog_memoized (insn
) < 0)
7781 len
= get_attr_length (insn
);
7784 /* ??? Most of the places below, we would like to abort, as
7785 it would indicate an error either in Haifa, or in the
7786 scheduling description. Unfortunately, Haifa never
7787 schedules the last instruction of the BB, so we don't
7788 have an accurate TI bit to go off. */
7790 if (in_use
& EV5_E0
)
7792 if (in_use
& EV5_E1
)
7797 in_use
|= EV5_E0
| EV5_E01
;
7801 if (in_use
& EV5_E0
)
7803 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
7811 if (in_use
& EV5_E1
)
7817 if (in_use
& EV5_FA
)
7819 if (in_use
& EV5_FM
)
7824 in_use
|= EV5_FA
| EV5_FAM
;
7828 if (in_use
& EV5_FA
)
7834 if (in_use
& EV5_FM
)
7847 /* Haifa doesn't do well scheduling branches. */
7848 /* ??? If this is predicted not-taken, slotting continues, except
7849 that no more IBR, FBR, or JSR insns may be slotted. */
7850 if (GET_CODE (insn
) == JUMP_INSN
)
7854 insn
= next_nonnote_insn (insn
);
7856 if (!insn
|| ! INSN_P (insn
))
7859 /* Let Haifa tell us where it thinks insn group boundaries are. */
7860 if (GET_MODE (insn
) == TImode
)
7863 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
7868 insn
= next_nonnote_insn (insn
);
7877 alphaev4_next_nop (pin_use
)
7880 int in_use
= *pin_use
;
7883 if (!(in_use
& EV4_IB0
))
7888 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
7893 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
7906 alphaev5_next_nop (pin_use
)
7909 int in_use
= *pin_use
;
7912 if (!(in_use
& EV5_E1
))
7917 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
7922 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
7934 /* The instruction group alignment main loop. */
7937 alpha_align_insns (insns
, max_align
, next_group
, next_nop
)
7939 unsigned int max_align
;
7940 rtx (*next_group
) PARAMS ((rtx
, int *, int *));
7941 rtx (*next_nop
) PARAMS ((int *));
7943 /* ALIGN is the known alignment for the insn group. */
7945 /* OFS is the offset of the current insn in the insn group. */
7947 int prev_in_use
, in_use
, len
;
7950 /* Let shorten branches care for assigning alignments to code labels. */
7951 shorten_branches (insns
);
7953 if (align_functions
< 4)
7955 else if ((unsigned int) align_functions
< max_align
)
7956 align
= align_functions
;
7960 ofs
= prev_in_use
= 0;
7962 if (GET_CODE (i
) == NOTE
)
7963 i
= next_nonnote_insn (i
);
7967 next
= (*next_group
) (i
, &in_use
, &len
);
7969 /* When we see a label, resync alignment etc. */
7970 if (GET_CODE (i
) == CODE_LABEL
)
7972 unsigned int new_align
= 1 << label_to_alignment (i
);
7974 if (new_align
>= align
)
7976 align
= new_align
< max_align
? new_align
: max_align
;
7980 else if (ofs
& (new_align
-1))
7981 ofs
= (ofs
| (new_align
-1)) + 1;
7986 /* Handle complex instructions special. */
7987 else if (in_use
== 0)
7989 /* Asms will have length < 0. This is a signal that we have
7990 lost alignment knowledge. Assume, however, that the asm
7991 will not mis-align instructions. */
8000 /* If the known alignment is smaller than the recognized insn group,
8001 realign the output. */
8002 else if ((int) align
< len
)
8004 unsigned int new_log_align
= len
> 8 ? 4 : 3;
8007 where
= prev
= prev_nonnote_insn (i
);
8008 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
8011 /* Can't realign between a call and its gp reload. */
8012 if (! (TARGET_EXPLICIT_RELOCS
8013 && prev
&& GET_CODE (prev
) == CALL_INSN
))
8015 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
8016 align
= 1 << new_log_align
;
8021 /* If the group won't fit in the same INT16 as the previous,
8022 we need to add padding to keep the group together. Rather
8023 than simply leaving the insn filling to the assembler, we
8024 can make use of the knowledge of what sorts of instructions
8025 were issued in the previous group to make sure that all of
8026 the added nops are really free. */
8027 else if (ofs
+ len
> (int) align
)
8029 int nop_count
= (align
- ofs
) / 4;
8032 /* Insert nops before labels, branches, and calls to truely merge
8033 the execution of the nops with the previous instruction group. */
8034 where
= prev_nonnote_insn (i
);
8037 if (GET_CODE (where
) == CODE_LABEL
)
8039 rtx where2
= prev_nonnote_insn (where
);
8040 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
8043 else if (GET_CODE (where
) == INSN
)
8050 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
8051 while (--nop_count
);
8055 ofs
= (ofs
+ len
) & (align
- 1);
8056 prev_in_use
= in_use
;
8061 /* Machine dependent reorg pass. */
8067 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
8068 alpha_handle_trap_shadows (insns
);
8070 /* Due to the number of extra trapb insns, don't bother fixing up
8071 alignment when trap precision is instruction. Moreover, we can
8072 only do our job when sched2 is run. */
8073 if (optimize
&& !optimize_size
8074 && alpha_tp
!= ALPHA_TP_INSN
8075 && flag_schedule_insns_after_reload
)
8077 if (alpha_cpu
== PROCESSOR_EV4
)
8078 alpha_align_insns (insns
, 8, alphaev4_next_group
, alphaev4_next_nop
);
8079 else if (alpha_cpu
== PROCESSOR_EV5
)
8080 alpha_align_insns (insns
, 16, alphaev5_next_group
, alphaev5_next_nop
);
8084 /* Check a floating-point value for validity for a particular machine mode. */
8086 static const char * const float_strings
[] =
8088 /* These are for FLOAT_VAX. */
8089 "1.70141173319264430e+38", /* 2^127 (2^24 - 1) / 2^24 */
8090 "-1.70141173319264430e+38",
8091 "2.93873587705571877e-39", /* 2^-128 */
8092 "-2.93873587705571877e-39",
8093 /* These are for the default broken IEEE mode, which traps
8094 on infinity or denormal numbers. */
8095 "3.402823466385288598117e+38", /* 2^128 (1 - 2^-24) */
8096 "-3.402823466385288598117e+38",
8097 "1.1754943508222875079687e-38", /* 2^-126 */
8098 "-1.1754943508222875079687e-38",
8101 static REAL_VALUE_TYPE float_values
[8];
8102 static int inited_float_values
= 0;
8105 check_float_value (mode
, d
, overflow
)
8106 enum machine_mode mode
;
8108 int overflow ATTRIBUTE_UNUSED
;
8111 if (TARGET_IEEE
|| TARGET_IEEE_CONFORMANT
|| TARGET_IEEE_WITH_INEXACT
)
8114 if (inited_float_values
== 0)
8117 for (i
= 0; i
< 8; i
++)
8118 float_values
[i
] = REAL_VALUE_ATOF (float_strings
[i
], DFmode
);
8120 inited_float_values
= 1;
8126 REAL_VALUE_TYPE
*fvptr
;
8128 if (TARGET_FLOAT_VAX
)
8129 fvptr
= &float_values
[0];
8131 fvptr
= &float_values
[4];
8133 memcpy (&r
, d
, sizeof (REAL_VALUE_TYPE
));
8134 if (REAL_VALUES_LESS (fvptr
[0], r
))
8136 memcpy (d
, &fvptr
[0], sizeof (REAL_VALUE_TYPE
));
8139 else if (REAL_VALUES_LESS (r
, fvptr
[1]))
8141 memcpy (d
, &fvptr
[1], sizeof (REAL_VALUE_TYPE
));
8144 else if (REAL_VALUES_LESS (dconst0
, r
)
8145 && REAL_VALUES_LESS (r
, fvptr
[2]))
8147 memcpy (d
, &dconst0
, sizeof (REAL_VALUE_TYPE
));
8150 else if (REAL_VALUES_LESS (r
, dconst0
)
8151 && REAL_VALUES_LESS (fvptr
[3], r
))
8153 memcpy (d
, &dconst0
, sizeof (REAL_VALUE_TYPE
));
8161 #if TARGET_ABI_OPEN_VMS
8163 /* Return the VMS argument type corresponding to MODE. */
8166 alpha_arg_type (mode
)
8167 enum machine_mode mode
;
8172 return TARGET_FLOAT_VAX
? FF
: FS
;
8174 return TARGET_FLOAT_VAX
? FD
: FT
;
8180 /* Return an rtx for an integer representing the VMS Argument Information
8184 alpha_arg_info_reg_val (cum
)
8185 CUMULATIVE_ARGS cum
;
8187 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
8190 for (i
= 0; i
< 6; i
++)
8191 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
8193 return GEN_INT (regval
);
8196 #include <splay-tree.h>
8198 /* Structure to collect function names for final output
8201 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
8206 enum links_kind kind
;
8209 static splay_tree alpha_links
;
8211 static int mark_alpha_links_node
PARAMS ((splay_tree_node
, void *));
8212 static void mark_alpha_links
PARAMS ((void *));
8213 static int alpha_write_one_linkage
PARAMS ((splay_tree_node
, void *));
8215 /* Protect alpha_links from garbage collection. */
8218 mark_alpha_links_node (node
, data
)
8219 splay_tree_node node
;
8220 void *data ATTRIBUTE_UNUSED
;
8222 struct alpha_links
*links
= (struct alpha_links
*) node
->value
;
8223 ggc_mark_rtx (links
->linkage
);
8228 mark_alpha_links (ptr
)
8231 splay_tree tree
= *(splay_tree
*) ptr
;
8232 splay_tree_foreach (tree
, mark_alpha_links_node
, NULL
);
8235 /* Make (or fake) .linkage entry for function call.
8237 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
8239 Return an SYMBOL_REF rtx for the linkage. */
8242 alpha_need_linkage (name
, is_local
)
8246 splay_tree_node node
;
8247 struct alpha_links
*al
;
8254 /* Is this name already defined? */
8256 node
= splay_tree_lookup (alpha_links
, (splay_tree_key
) name
);
8259 al
= (struct alpha_links
*) node
->value
;
8262 /* Defined here but external assumed. */
8263 if (al
->kind
== KIND_EXTERN
)
8264 al
->kind
= KIND_LOCAL
;
8268 /* Used here but unused assumed. */
8269 if (al
->kind
== KIND_UNUSED
)
8270 al
->kind
= KIND_LOCAL
;
8277 alpha_links
= splay_tree_new ((splay_tree_compare_fn
) strcmp
,
8278 (splay_tree_delete_key_fn
) free
,
8279 (splay_tree_delete_key_fn
) free
);
8280 ggc_add_root (&alpha_links
, 1, 1, mark_alpha_links
);
8283 al
= (struct alpha_links
*) xmalloc (sizeof (struct alpha_links
));
8284 name
= xstrdup (name
);
8286 /* Assume external if no definition. */
8287 al
->kind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
8289 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
8290 get_identifier (name
);
8292 /* Construct a SYMBOL_REF for us to call. */
8294 size_t name_len
= strlen (name
);
8295 char *linksym
= alloca (name_len
+ 6);
8297 memcpy (linksym
+ 1, name
, name_len
);
8298 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
8299 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
8300 ggc_alloc_string (linksym
, name_len
+ 5));
8303 splay_tree_insert (alpha_links
, (splay_tree_key
) name
,
8304 (splay_tree_value
) al
);
8310 alpha_write_one_linkage (node
, data
)
8311 splay_tree_node node
;
8314 const char *const name
= (const char *) node
->key
;
8315 struct alpha_links
*links
= (struct alpha_links
*) node
->value
;
8316 FILE *stream
= (FILE *) data
;
8318 if (links
->kind
== KIND_UNUSED
8319 || ! TREE_SYMBOL_REFERENCED (get_identifier (name
)))
8322 fprintf (stream
, "$%s..lk:\n", name
);
8323 if (links
->kind
== KIND_LOCAL
)
8325 /* Local and used, build linkage pair. */
8326 fprintf (stream
, "\t.quad %s..en\n", name
);
8327 fprintf (stream
, "\t.quad %s\n", name
);
8331 /* External and used, request linkage pair. */
8332 fprintf (stream
, "\t.linkage %s\n", name
);
8339 alpha_write_linkage (stream
)
8344 readonly_section ();
8345 fprintf (stream
, "\t.align 3\n");
8346 splay_tree_foreach (alpha_links
, alpha_write_one_linkage
, stream
);
8350 /* Given a decl, a section name, and whether the decl initializer
8351 has relocs, choose attributes for the section. */
8353 #define SECTION_VMS_OVERLAY SECTION_FORGET
8354 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
8355 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
8358 vms_section_type_flags (decl
, name
, reloc
)
8363 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
8365 if (decl
&& DECL_ATTRIBUTES (decl
)
8366 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
8367 flags
|= SECTION_VMS_OVERLAY
;
8368 if (decl
&& DECL_ATTRIBUTES (decl
)
8369 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
8370 flags
|= SECTION_VMS_GLOBAL
;
8371 if (decl
&& DECL_ATTRIBUTES (decl
)
8372 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
8373 flags
|= SECTION_VMS_INITIALIZE
;
8378 /* Switch to an arbitrary section NAME with attributes as specified
8379 by FLAGS. ALIGN specifies any known alignment requirements for
8380 the section; 0 if the default should be used. */
8383 vms_asm_named_section (name
, flags
)
8387 fputc ('\n', asm_out_file
);
8388 fprintf (asm_out_file
, ".section\t%s", name
);
8390 if (flags
& SECTION_VMS_OVERLAY
)
8391 fprintf (asm_out_file
, ",OVR");
8392 if (flags
& SECTION_VMS_GLOBAL
)
8393 fprintf (asm_out_file
, ",GBL");
8394 if (flags
& SECTION_VMS_INITIALIZE
)
8395 fprintf (asm_out_file
, ",NOMOD");
8396 if (flags
& SECTION_DEBUG
)
8397 fprintf (asm_out_file
, ",NOWRT");
8399 fputc ('\n', asm_out_file
);
8402 /* Record an element in the table of global constructors. SYMBOL is
8403 a SYMBOL_REF of the function to be called; PRIORITY is a number
8404 between 0 and MAX_INIT_PRIORITY.
8406 Differs from default_ctors_section_asm_out_constructor in that the
8407 width of the .ctors entry is always 64 bits, rather than the 32 bits
8408 used by a normal pointer. */
8411 vms_asm_out_constructor (symbol
, priority
)
8413 int priority ATTRIBUTE_UNUSED
;
8416 assemble_align (BITS_PER_WORD
);
8417 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
8421 vms_asm_out_destructor (symbol
, priority
)
8423 int priority ATTRIBUTE_UNUSED
;
8426 assemble_align (BITS_PER_WORD
);
8427 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
8432 alpha_need_linkage (name
, is_local
)
8433 const char *name ATTRIBUTE_UNUSED
;
8434 int is_local ATTRIBUTE_UNUSED
;
8439 #endif /* TARGET_ABI_OPEN_VMS */
8441 #if TARGET_ABI_UNICOSMK
8443 static void unicosmk_output_module_name
PARAMS ((FILE *));
8444 static void unicosmk_output_default_externs
PARAMS ((FILE *));
8445 static void unicosmk_output_dex
PARAMS ((FILE *));
8446 static void unicosmk_output_externs
PARAMS ((FILE *));
8447 static void unicosmk_output_addr_vec
PARAMS ((FILE *, rtx
));
8448 static const char *unicosmk_ssib_name
PARAMS ((void));
8449 static int unicosmk_special_name
PARAMS ((const char *));
8451 /* Define the offset between two registers, one to be eliminated, and the
8452 other its replacement, at the start of a routine. */
8455 unicosmk_initial_elimination_offset (from
, to
)
8461 fixed_size
= alpha_sa_size();
8462 if (fixed_size
!= 0)
8465 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
8467 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
8469 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
8470 return (ALPHA_ROUND (current_function_outgoing_args_size
)
8471 + ALPHA_ROUND (get_frame_size()));
8472 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
8473 return (ALPHA_ROUND (fixed_size
)
8474 + ALPHA_ROUND (get_frame_size()
8475 + current_function_outgoing_args_size
));
8480 /* Output the module name for .ident and .end directives. We have to strip
8481 directories and add make sure that the module name starts with a letter
8485 unicosmk_output_module_name (file
)
8490 /* Strip directories. */
8492 name
= strrchr (main_input_filename
, '/');
8496 name
= main_input_filename
;
8498 /* CAM only accepts module names that start with a letter or '$'. We
8499 prefix the module name with a '$' if necessary. */
8501 if (!ISALPHA (*name
))
8502 fprintf (file
, "$%s", name
);
8507 /* Output text that to appear at the beginning of an assembler file. */
8510 unicosmk_asm_file_start (file
)
8515 fputs ("\t.ident\t", file
);
8516 unicosmk_output_module_name (file
);
8517 fputs ("\n\n", file
);
8519 /* The Unicos/Mk assembler uses different register names. Instead of trying
8520 to support them, we simply use micro definitions. */
8522 /* CAM has different register names: rN for the integer register N and fN
8523 for the floating-point register N. Instead of trying to use these in
8524 alpha.md, we define the symbols $N and $fN to refer to the appropriate
8527 for (i
= 0; i
< 32; ++i
)
8528 fprintf (file
, "$%d <- r%d\n", i
, i
);
8530 for (i
= 0; i
< 32; ++i
)
8531 fprintf (file
, "$f%d <- f%d\n", i
, i
);
8535 /* The .align directive fill unused space with zeroes which does not work
8536 in code sections. We define the macro 'gcc@code@align' which uses nops
8537 instead. Note that it assumes that code sections always have the
8538 biggest possible alignment since . refers to the current offset from
8539 the beginning of the section. */
8541 fputs ("\t.macro gcc@code@align n\n", file
);
8542 fputs ("gcc@n@bytes = 1 << n\n", file
);
8543 fputs ("gcc@here = . % gcc@n@bytes\n", file
);
8544 fputs ("\t.if ne, gcc@here, 0\n", file
);
8545 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", file
);
8546 fputs ("\tbis r31,r31,r31\n", file
);
8547 fputs ("\t.endr\n", file
);
8548 fputs ("\t.endif\n", file
);
8549 fputs ("\t.endm gcc@code@align\n\n", file
);
8551 /* Output extern declarations which should always be visible. */
8552 unicosmk_output_default_externs (file
);
8554 /* Open a dummy section. We always need to be inside a section for the
8555 section-switching code to work correctly.
8556 ??? This should be a module id or something like that. I still have to
8557 figure out what the rules for those are. */
8558 fputs ("\n\t.psect\t$SG00000,data\n", file
);
8561 /* Output text to appear at the end of an assembler file. This includes all
8562 pending extern declarations and DEX expressions. */
8565 unicosmk_asm_file_end (file
)
8568 fputs ("\t.endp\n\n", file
);
8570 /* Output all pending externs. */
8572 unicosmk_output_externs (file
);
8574 /* Output dex definitions used for functions whose names conflict with
8577 unicosmk_output_dex (file
);
8579 fputs ("\t.end\t", file
);
8580 unicosmk_output_module_name (file
);
8584 /* Output the definition of a common variable. */
8587 unicosmk_output_common (file
, name
, size
, align
)
8594 printf ("T3E__: common %s\n", name
);
8597 fputs("\t.endp\n\n\t.psect ", file
);
8598 assemble_name(file
, name
);
8599 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
8600 fprintf(file
, "\t.byte\t0:%d\n", size
);
8602 /* Mark the symbol as defined in this module. */
8603 name_tree
= get_identifier (name
);
8604 TREE_ASM_WRITTEN (name_tree
) = 1;
8607 #define SECTION_PUBLIC SECTION_MACH_DEP
8608 #define SECTION_MAIN (SECTION_PUBLIC << 1)
8609 static int current_section_align
;
8612 unicosmk_section_type_flags (decl
, name
, reloc
)
8615 int reloc ATTRIBUTE_UNUSED
;
8617 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
8622 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8624 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
8625 if (align_functions_log
> current_section_align
)
8626 current_section_align
= align_functions_log
;
8628 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
8629 flags
|= SECTION_MAIN
;
8632 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
8634 if (TREE_PUBLIC (decl
))
8635 flags
|= SECTION_PUBLIC
;
8640 /* Generate a section name for decl and associate it with the
8644 unicosmk_unique_section (decl
, reloc
)
8646 int reloc ATTRIBUTE_UNUSED
;
8654 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
8655 STRIP_NAME_ENCODING (name
, name
);
8656 len
= strlen (name
);
8658 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8662 /* It is essential that we prefix the section name here because
8663 otherwise the section names generated for constructors and
8664 destructors confuse collect2. */
8666 string
= alloca (len
+ 6);
8667 sprintf (string
, "code@%s", name
);
8668 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
8670 else if (TREE_PUBLIC (decl
))
8671 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
8676 string
= alloca (len
+ 6);
8677 sprintf (string
, "data@%s", name
);
8678 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
8682 /* Switch to an arbitrary section NAME with attributes as specified
8683 by FLAGS. ALIGN specifies any known alignment requirements for
8684 the section; 0 if the default should be used. */
8687 unicosmk_asm_named_section (name
, flags
)
8693 /* Close the previous section. */
8695 fputs ("\t.endp\n\n", asm_out_file
);
8697 /* Find out what kind of section we are opening. */
8699 if (flags
& SECTION_MAIN
)
8700 fputs ("\t.start\tmain\n", asm_out_file
);
8702 if (flags
& SECTION_CODE
)
8704 else if (flags
& SECTION_PUBLIC
)
8709 if (current_section_align
!= 0)
8710 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
8711 current_section_align
, kind
);
8713 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
8717 unicosmk_insert_attributes (decl
, attr_ptr
)
8719 tree
*attr_ptr ATTRIBUTE_UNUSED
;
8722 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
8723 UNIQUE_SECTION (decl
, 0);
8726 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
8727 in code sections because .align fill unused space with zeroes. */
8730 unicosmk_output_align (file
, align
)
8734 if (inside_function
)
8735 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
8737 fprintf (file
, "\t.align\t%d\n", align
);
8740 /* Add a case vector to the current function's list of deferred case
8741 vectors. Case vectors have to be put into a separate section because CAM
8742 does not allow data definitions in code sections. */
8745 unicosmk_defer_case_vector (lab
, vec
)
8749 struct machine_function
*machine
= cfun
->machine
;
8751 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
8752 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
8753 machine
->addr_list
);
8756 /* Output a case vector. */
8759 unicosmk_output_addr_vec (file
, vec
)
8763 rtx lab
= XEXP (vec
, 0);
8764 rtx body
= XEXP (vec
, 1);
8765 int vlen
= XVECLEN (body
, 0);
8768 ASM_OUTPUT_INTERNAL_LABEL (file
, "L", CODE_LABEL_NUMBER (lab
));
8770 for (idx
= 0; idx
< vlen
; idx
++)
8772 ASM_OUTPUT_ADDR_VEC_ELT
8773 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
8777 /* Output current function's deferred case vectors. */
8780 unicosmk_output_deferred_case_vectors (file
)
8783 struct machine_function
*machine
= cfun
->machine
;
8786 if (machine
->addr_list
== NULL_RTX
)
8790 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
8791 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
8794 /* Set up the dynamic subprogram information block (DSIB) and update the
8795 frame pointer register ($15) for subroutines which have a frame. If the
8796 subroutine doesn't have a frame, simply increment $15. */
8799 unicosmk_gen_dsib (imaskP
)
8800 unsigned long * imaskP
;
8802 if (alpha_procedure_type
== PT_STACK
)
8804 const char *ssib_name
;
8807 /* Allocate 64 bytes for the DSIB. */
8809 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8811 emit_insn (gen_blockage ());
8813 /* Save the return address. */
8815 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
8816 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8817 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
8818 (*imaskP
) &= ~(1L << REG_RA
);
8820 /* Save the old frame pointer. */
8822 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
8823 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8824 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
8825 (*imaskP
) &= ~(1L << HARD_FRAME_POINTER_REGNUM
);
8827 emit_insn (gen_blockage ());
8829 /* Store the SSIB pointer. */
8831 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
8832 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
8833 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8835 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
8836 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
8837 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
8839 /* Save the CIW index. */
8841 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
8842 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8843 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
8845 emit_insn (gen_blockage ());
8847 /* Set the new frame pointer. */
8849 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8850 stack_pointer_rtx
, GEN_INT (64))));
8855 /* Increment the frame pointer register to indicate that we do not
8858 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8859 hard_frame_pointer_rtx
, GEN_INT (1))));
8863 #define SSIB_PREFIX "__SSIB_"
8864 #define SSIB_PREFIX_LEN 7
8866 /* Generate the name of the SSIB section for the current function. */
8869 unicosmk_ssib_name ()
8871 /* This is ok since CAM won't be able to deal with names longer than that
8874 static char name
[256];
8880 x
= DECL_RTL (cfun
->decl
);
8881 if (GET_CODE (x
) != MEM
)
8884 if (GET_CODE (x
) != SYMBOL_REF
)
8886 fnname
= XSTR (x
, 0);
8887 STRIP_NAME_ENCODING (fnname
, fnname
);
8889 len
= strlen (fnname
);
8890 if (len
+ SSIB_PREFIX_LEN
> 255)
8891 len
= 255 - SSIB_PREFIX_LEN
;
8893 strcpy (name
, SSIB_PREFIX
);
8894 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
8895 name
[len
+ SSIB_PREFIX_LEN
] = 0;
8900 /* Output the static subroutine information block for the current
8904 unicosmk_output_ssib (file
, fnname
)
8912 struct machine_function
*machine
= cfun
->machine
;
8915 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
8916 unicosmk_ssib_name ());
8918 /* Some required stuff and the function name length. */
8920 len
= strlen (fnname
);
8921 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
8924 ??? We don't do that yet. */
8926 fputs ("\t.quad\t0\n", file
);
8928 /* Function address. */
8930 fputs ("\t.quad\t", file
);
8931 assemble_name (file
, fnname
);
8934 fputs ("\t.quad\t0\n", file
);
8935 fputs ("\t.quad\t0\n", file
);
8938 ??? We do it the same way Cray CC does it but this could be
8941 for( i
= 0; i
< len
; i
++ )
8942 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
8943 if( (len
% 8) == 0 )
8944 fputs ("\t.quad\t0\n", file
);
8946 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
8948 /* All call information words used in the function. */
8950 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
8953 fprintf (file
, "\t.quad\t");
8954 #if HOST_BITS_PER_WIDE_INT == 32
8955 fprintf (file
, HOST_WIDE_INT_PRINT_DOUBLE_HEX
,
8956 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
8958 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (ciw
));
8960 fprintf (file
, "\n");
8964 /* Add a call information word (CIW) to the list of the current function's
8965 CIWs and return its index.
8967 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
8970 unicosmk_add_call_info_word (x
)
8974 struct machine_function
*machine
= cfun
->machine
;
8976 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
8977 if (machine
->first_ciw
== NULL_RTX
)
8978 machine
->first_ciw
= node
;
8980 XEXP (machine
->last_ciw
, 1) = node
;
8982 machine
->last_ciw
= node
;
8983 ++machine
->ciw_count
;
8985 return GEN_INT (machine
->ciw_count
8986 + strlen (current_function_name
)/8 + 5);
8989 static char unicosmk_section_buf
[100];
8992 unicosmk_text_section ()
8994 static int count
= 0;
8995 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
8997 return unicosmk_section_buf
;
9001 unicosmk_data_section ()
9003 static int count
= 1;
9004 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9006 return unicosmk_section_buf
;
9009 /* The Cray assembler doesn't accept extern declarations for symbols which
9010 are defined in the same file. We have to keep track of all global
9011 symbols which are referenced and/or defined in a source file and output
9012 extern declarations for those which are referenced but not defined at
9015 /* List of identifiers for which an extern declaration might have to be
9018 struct unicosmk_extern_list
9020 struct unicosmk_extern_list
*next
;
9024 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
9026 /* Output extern declarations which are required for every asm file. */
9029 unicosmk_output_default_externs (file
)
9032 static const char *const externs
[] =
9033 { "__T3E_MISMATCH" };
9038 n
= ARRAY_SIZE (externs
);
9040 for (i
= 0; i
< n
; i
++)
9041 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
9044 /* Output extern declarations for global symbols which are have been
9045 referenced but not defined. */
9048 unicosmk_output_externs (file
)
9051 struct unicosmk_extern_list
*p
;
9052 const char *real_name
;
9056 len
= strlen (user_label_prefix
);
9057 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
9059 /* We have to strip the encoding and possibly remove user_label_prefix
9060 from the identifier in order to handle -fleading-underscore and
9061 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9062 STRIP_NAME_ENCODING (real_name
, p
->name
);
9063 if (len
&& p
->name
[0] == '*'
9064 && !memcmp (real_name
, user_label_prefix
, len
))
9067 name_tree
= get_identifier (real_name
);
9068 if (! TREE_ASM_WRITTEN (name_tree
))
9070 TREE_ASM_WRITTEN (name_tree
) = 1;
9071 fputs ("\t.extern\t", file
);
9072 assemble_name (file
, p
->name
);
9078 /* Record an extern. */
9081 unicosmk_add_extern (name
)
9084 struct unicosmk_extern_list
*p
;
9086 p
= (struct unicosmk_extern_list
*)
9087 permalloc (sizeof (struct unicosmk_extern_list
));
9088 p
->next
= unicosmk_extern_head
;
9090 unicosmk_extern_head
= p
;
9093 /* The Cray assembler generates incorrect code if identifiers which
9094 conflict with register names are used as instruction operands. We have
9095 to replace such identifiers with DEX expressions. */
9097 /* Structure to collect identifiers which have been replaced by DEX
9100 struct unicosmk_dex
{
9101 struct unicosmk_dex
*next
;
9105 /* List of identifiers which have been replaced by DEX expressions. The DEX
9106 number is determined by the position in the list. */
9108 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
9110 /* The number of elements in the DEX list. */
9112 static int unicosmk_dex_count
= 0;
9114 /* Check if NAME must be replaced by a DEX expression. */
9117 unicosmk_special_name (name
)
9126 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
9132 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
9135 return (name
[2] == '\0'
9136 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
9139 return (ISDIGIT (name
[1]) && name
[2] == '\0');
9143 /* Return the DEX number if X must be replaced by a DEX expression and 0
9147 unicosmk_need_dex (x
)
9150 struct unicosmk_dex
*dex
;
9154 if (GET_CODE (x
) != SYMBOL_REF
)
9158 if (! unicosmk_special_name (name
))
9161 i
= unicosmk_dex_count
;
9162 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9164 if (! strcmp (name
, dex
->name
))
9169 dex
= (struct unicosmk_dex
*) permalloc (sizeof (struct unicosmk_dex
));
9171 dex
->next
= unicosmk_dex_list
;
9172 unicosmk_dex_list
= dex
;
9174 ++unicosmk_dex_count
;
9175 return unicosmk_dex_count
;
9178 /* Output the DEX definitions for this file. */
9181 unicosmk_output_dex (file
)
9184 struct unicosmk_dex
*dex
;
9187 if (unicosmk_dex_list
== NULL
)
9190 fprintf (file
, "\t.dexstart\n");
9192 i
= unicosmk_dex_count
;
9193 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9195 fprintf (file
, "\tDEX (%d) = ", i
);
9196 assemble_name (file
, dex
->name
);
9201 fprintf (file
, "\t.dexend\n");
9207 unicosmk_output_deferred_case_vectors (file
)
9208 FILE *file ATTRIBUTE_UNUSED
;
9212 unicosmk_gen_dsib (imaskP
)
9213 unsigned long * imaskP ATTRIBUTE_UNUSED
;
9217 unicosmk_output_ssib (file
, fnname
)
9218 FILE * file ATTRIBUTE_UNUSED
;
9219 const char * fnname ATTRIBUTE_UNUSED
;
9223 unicosmk_add_call_info_word (x
)
9224 rtx x ATTRIBUTE_UNUSED
;
9230 unicosmk_need_dex (x
)
9231 rtx x ATTRIBUTE_UNUSED
;
9236 #endif /* TARGET_ABI_UNICOSMK */