1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
45 #include "integrate.h"
48 #include "target-def.h"
52 extern int rtx_equal_function_value_matters
;
54 /* Specify which cpu to schedule for. */
56 enum processor_type alpha_cpu
;
57 static const char * const alpha_cpu_name
[] =
62 /* Specify how accurate floating-point traps need to be. */
64 enum alpha_trap_precision alpha_tp
;
66 /* Specify the floating-point rounding mode. */
68 enum alpha_fp_rounding_mode alpha_fprm
;
70 /* Specify which things cause traps. */
72 enum alpha_fp_trap_mode alpha_fptm
;
74 /* Strings decoded into the above options. */
76 const char *alpha_cpu_string
; /* -mcpu= */
77 const char *alpha_tune_string
; /* -mtune= */
78 const char *alpha_tp_string
; /* -mtrap-precision=[p|s|i] */
79 const char *alpha_fprm_string
; /* -mfp-rounding-mode=[n|m|c|d] */
80 const char *alpha_fptm_string
; /* -mfp-trap-mode=[n|u|su|sui] */
81 const char *alpha_mlat_string
; /* -mmemory-latency= */
83 /* Save information from a "cmpxx" operation until the branch or scc is
86 struct alpha_compare alpha_compare
;
88 /* Non-zero if inside of a function, because the Alpha asm can't
89 handle .files inside of functions. */
91 static int inside_function
= FALSE
;
93 /* The number of cycles of latency we should assume on memory reads. */
95 int alpha_memory_latency
= 3;
97 /* Whether the function needs the GP. */
99 static int alpha_function_needs_gp
;
101 /* The alias set for prologue/epilogue register save/restore. */
103 static int alpha_sr_alias_set
;
105 /* The assembler name of the current function. */
107 static const char *alpha_fnname
;
109 /* The next explicit relocation sequence number. */
110 int alpha_next_sequence_number
= 1;
112 /* The literal and gpdisp sequence numbers for this insn, as printed
113 by %# and %* respectively. */
114 int alpha_this_literal_sequence_number
;
115 int alpha_this_gpdisp_sequence_number
;
117 /* Declarations of static functions. */
118 static bool decl_in_text_section
120 static int some_small_symbolic_mem_operand_1
121 PARAMS ((rtx
*, void *));
122 static int split_small_symbolic_mem_operand_1
123 PARAMS ((rtx
*, void *));
124 static bool local_symbol_p
126 static void alpha_set_memflags_1
127 PARAMS ((rtx
, int, int, int));
128 static rtx alpha_emit_set_const_1
129 PARAMS ((rtx
, enum machine_mode
, HOST_WIDE_INT
, int));
130 static void alpha_expand_unaligned_load_words
131 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
132 static void alpha_expand_unaligned_store_words
133 PARAMS ((rtx
*out_regs
, rtx smem
, HOST_WIDE_INT words
, HOST_WIDE_INT ofs
));
134 static void alpha_sa_mask
135 PARAMS ((unsigned long *imaskP
, unsigned long *fmaskP
));
136 static int find_lo_sum
137 PARAMS ((rtx
*, void *));
138 static int alpha_does_function_need_gp
140 static int alpha_ra_ever_killed
142 static const char *get_trap_mode_suffix
144 static const char *get_round_mode_suffix
146 static rtx set_frame_related_p
148 static const char *alpha_lookup_xfloating_lib_func
149 PARAMS ((enum rtx_code
));
150 static int alpha_compute_xfloating_mode_arg
151 PARAMS ((enum rtx_code
, enum alpha_fp_rounding_mode
));
152 static void alpha_emit_xfloating_libcall
153 PARAMS ((const char *, rtx
, rtx
[], int, rtx
));
154 static rtx alpha_emit_xfloating_compare
155 PARAMS ((enum rtx_code
, rtx
, rtx
));
156 static void alpha_output_function_end_prologue
158 static int alpha_adjust_cost
159 PARAMS ((rtx
, rtx
, rtx
, int));
160 static int alpha_issue_rate
162 static int alpha_variable_issue
163 PARAMS ((FILE *, int, rtx
, int));
165 #if TARGET_ABI_UNICOSMK
166 static void alpha_init_machine_status
167 PARAMS ((struct function
*p
));
168 static void alpha_mark_machine_status
169 PARAMS ((struct function
*p
));
170 static void alpha_free_machine_status
171 PARAMS ((struct function
*p
));
174 static void unicosmk_output_deferred_case_vectors
PARAMS ((FILE *));
175 static void unicosmk_gen_dsib
PARAMS ((unsigned long *imaskP
));
176 static void unicosmk_output_ssib
PARAMS ((FILE *, const char *));
177 static int unicosmk_need_dex
PARAMS ((rtx
));
179 /* Get the number of args of a function in one of two ways. */
180 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
181 #define NUM_ARGS current_function_args_info.num_args
183 #define NUM_ARGS current_function_args_info
189 /* Initialize the GCC target structure. */
190 #if TARGET_ABI_OPEN_VMS
191 const struct attribute_spec vms_attribute_table
[];
192 static unsigned int vms_section_type_flags
PARAMS ((tree
, const char *, int));
193 static void vms_asm_named_section
PARAMS ((const char *, unsigned int));
194 static void vms_asm_out_constructor
PARAMS ((rtx
, int));
195 static void vms_asm_out_destructor
PARAMS ((rtx
, int));
196 # undef TARGET_ATTRIBUTE_TABLE
197 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
198 # undef TARGET_SECTION_TYPE_FLAGS
199 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
202 #if TARGET_ABI_UNICOSMK
203 static void unicosmk_asm_named_section
PARAMS ((const char *, unsigned int));
204 static void unicosmk_insert_attributes
PARAMS ((tree
, tree
*));
205 static unsigned int unicosmk_section_type_flags
PARAMS ((tree
, const char *,
207 # undef TARGET_INSERT_ATTRIBUTES
208 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
209 # undef TARGET_SECTION_TYPE_FLAGS
210 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
213 #undef TARGET_ASM_ALIGNED_HI_OP
214 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
215 #undef TARGET_ASM_ALIGNED_DI_OP
216 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
218 /* Default unaligned ops are provided for ELF systems. To get unaligned
219 data for non-ELF systems, we have to turn off auto alignment. */
220 #ifndef OBJECT_FORMAT_ELF
221 #undef TARGET_ASM_UNALIGNED_HI_OP
222 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
223 #undef TARGET_ASM_UNALIGNED_SI_OP
224 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
225 #undef TARGET_ASM_UNALIGNED_DI_OP
226 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
229 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
230 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
232 #undef TARGET_SCHED_ADJUST_COST
233 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
234 #undef TARGET_SCHED_ISSUE_RATE
235 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
236 #undef TARGET_SCHED_VARIABLE_ISSUE
237 #define TARGET_SCHED_VARIABLE_ISSUE alpha_variable_issue
239 struct gcc_target targetm
= TARGET_INITIALIZER
;
241 /* Parse target option strings. */
247 static const struct cpu_table
{
248 const char *const name
;
249 const enum processor_type processor
;
252 #define EV5_MASK (MASK_CPU_EV5)
253 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
254 { "ev4", PROCESSOR_EV4
, 0 },
255 { "ev45", PROCESSOR_EV4
, 0 },
256 { "21064", PROCESSOR_EV4
, 0 },
257 { "ev5", PROCESSOR_EV5
, EV5_MASK
},
258 { "21164", PROCESSOR_EV5
, EV5_MASK
},
259 { "ev56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
260 { "21164a", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
},
261 { "pca56", PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
262 { "21164PC",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
263 { "21164pc",PROCESSOR_EV5
, EV5_MASK
|MASK_BWX
|MASK_MAX
},
264 { "ev6", PROCESSOR_EV6
, EV6_MASK
},
265 { "21264", PROCESSOR_EV6
, EV6_MASK
},
266 { "ev67", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
267 { "21264a", PROCESSOR_EV6
, EV6_MASK
|MASK_CIX
},
271 /* Unicos/Mk doesn't have shared libraries. */
272 if (TARGET_ABI_UNICOSMK
&& flag_pic
)
274 warning ("-f%s ignored for Unicos/Mk (not supported)",
275 (flag_pic
> 1) ? "PIC" : "pic");
279 /* On Unicos/Mk, the native compiler consistenly generates /d suffices for
280 floating-point instructions. Make that the default for this target. */
281 if (TARGET_ABI_UNICOSMK
)
282 alpha_fprm
= ALPHA_FPRM_DYN
;
284 alpha_fprm
= ALPHA_FPRM_NORM
;
286 alpha_tp
= ALPHA_TP_PROG
;
287 alpha_fptm
= ALPHA_FPTM_N
;
289 /* We cannot use su and sui qualifiers for conversion instructions on
290 Unicos/Mk. I'm not sure if this is due to assembler or hardware
291 limitations. Right now, we issue a warning if -mieee is specified
292 and then ignore it; eventually, we should either get it right or
293 disable the option altogether. */
297 if (TARGET_ABI_UNICOSMK
)
298 warning ("-mieee not supported on Unicos/Mk");
301 alpha_tp
= ALPHA_TP_INSN
;
302 alpha_fptm
= ALPHA_FPTM_SU
;
306 if (TARGET_IEEE_WITH_INEXACT
)
308 if (TARGET_ABI_UNICOSMK
)
309 warning ("-mieee-with-inexact not supported on Unicos/Mk");
312 alpha_tp
= ALPHA_TP_INSN
;
313 alpha_fptm
= ALPHA_FPTM_SUI
;
319 if (! strcmp (alpha_tp_string
, "p"))
320 alpha_tp
= ALPHA_TP_PROG
;
321 else if (! strcmp (alpha_tp_string
, "f"))
322 alpha_tp
= ALPHA_TP_FUNC
;
323 else if (! strcmp (alpha_tp_string
, "i"))
324 alpha_tp
= ALPHA_TP_INSN
;
326 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string
);
329 if (alpha_fprm_string
)
331 if (! strcmp (alpha_fprm_string
, "n"))
332 alpha_fprm
= ALPHA_FPRM_NORM
;
333 else if (! strcmp (alpha_fprm_string
, "m"))
334 alpha_fprm
= ALPHA_FPRM_MINF
;
335 else if (! strcmp (alpha_fprm_string
, "c"))
336 alpha_fprm
= ALPHA_FPRM_CHOP
;
337 else if (! strcmp (alpha_fprm_string
,"d"))
338 alpha_fprm
= ALPHA_FPRM_DYN
;
340 error ("bad value `%s' for -mfp-rounding-mode switch",
344 if (alpha_fptm_string
)
346 if (strcmp (alpha_fptm_string
, "n") == 0)
347 alpha_fptm
= ALPHA_FPTM_N
;
348 else if (strcmp (alpha_fptm_string
, "u") == 0)
349 alpha_fptm
= ALPHA_FPTM_U
;
350 else if (strcmp (alpha_fptm_string
, "su") == 0)
351 alpha_fptm
= ALPHA_FPTM_SU
;
352 else if (strcmp (alpha_fptm_string
, "sui") == 0)
353 alpha_fptm
= ALPHA_FPTM_SUI
;
355 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string
);
359 = TARGET_CPU_DEFAULT
& MASK_CPU_EV6
? PROCESSOR_EV6
360 : (TARGET_CPU_DEFAULT
& MASK_CPU_EV5
? PROCESSOR_EV5
: PROCESSOR_EV4
);
362 if (alpha_cpu_string
)
364 for (i
= 0; cpu_table
[i
].name
; i
++)
365 if (! strcmp (alpha_cpu_string
, cpu_table
[i
].name
))
367 alpha_cpu
= cpu_table
[i
].processor
;
368 target_flags
&= ~ (MASK_BWX
| MASK_MAX
| MASK_FIX
| MASK_CIX
369 | MASK_CPU_EV5
| MASK_CPU_EV6
);
370 target_flags
|= cpu_table
[i
].flags
;
373 if (! cpu_table
[i
].name
)
374 error ("bad value `%s' for -mcpu switch", alpha_cpu_string
);
377 if (alpha_tune_string
)
379 for (i
= 0; cpu_table
[i
].name
; i
++)
380 if (! strcmp (alpha_tune_string
, cpu_table
[i
].name
))
382 alpha_cpu
= cpu_table
[i
].processor
;
385 if (! cpu_table
[i
].name
)
386 error ("bad value `%s' for -mcpu switch", alpha_tune_string
);
389 /* Do some sanity checks on the above options. */
391 if (TARGET_ABI_UNICOSMK
&& alpha_fptm
!= ALPHA_FPTM_N
)
393 warning ("trap mode not supported on Unicos/Mk");
394 alpha_fptm
= ALPHA_FPTM_N
;
397 if ((alpha_fptm
== ALPHA_FPTM_SU
|| alpha_fptm
== ALPHA_FPTM_SUI
)
398 && alpha_tp
!= ALPHA_TP_INSN
&& ! TARGET_CPU_EV6
)
400 warning ("fp software completion requires -mtrap-precision=i");
401 alpha_tp
= ALPHA_TP_INSN
;
406 /* Except for EV6 pass 1 (not released), we always have precise
407 arithmetic traps. Which means we can do software completion
408 without minding trap shadows. */
409 alpha_tp
= ALPHA_TP_PROG
;
412 if (TARGET_FLOAT_VAX
)
414 if (alpha_fprm
== ALPHA_FPRM_MINF
|| alpha_fprm
== ALPHA_FPRM_DYN
)
416 warning ("rounding mode not supported for VAX floats");
417 alpha_fprm
= ALPHA_FPRM_NORM
;
419 if (alpha_fptm
== ALPHA_FPTM_SUI
)
421 warning ("trap mode not supported for VAX floats");
422 alpha_fptm
= ALPHA_FPTM_SU
;
430 if (!alpha_mlat_string
)
431 alpha_mlat_string
= "L1";
433 if (ISDIGIT ((unsigned char)alpha_mlat_string
[0])
434 && (lat
= strtol (alpha_mlat_string
, &end
, 10), *end
== '\0'))
436 else if ((alpha_mlat_string
[0] == 'L' || alpha_mlat_string
[0] == 'l')
437 && ISDIGIT ((unsigned char)alpha_mlat_string
[1])
438 && alpha_mlat_string
[2] == '\0')
440 static int const cache_latency
[][4] =
442 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
443 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
444 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
447 lat
= alpha_mlat_string
[1] - '0';
448 if (lat
<= 0 || lat
> 3 || cache_latency
[alpha_cpu
][lat
-1] == -1)
450 warning ("L%d cache latency unknown for %s",
451 lat
, alpha_cpu_name
[alpha_cpu
]);
455 lat
= cache_latency
[alpha_cpu
][lat
-1];
457 else if (! strcmp (alpha_mlat_string
, "main"))
459 /* Most current memories have about 370ns latency. This is
460 a reasonable guess for a fast cpu. */
465 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string
);
469 alpha_memory_latency
= lat
;
472 /* Default the definition of "small data" to 8 bytes. */
476 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
478 target_flags
|= MASK_SMALL_DATA
;
479 else if (flag_pic
== 2)
480 target_flags
&= ~MASK_SMALL_DATA
;
482 /* Align labels and loops for optimal branching. */
483 /* ??? Kludge these by not doing anything if we don't optimize and also if
484 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
485 if (optimize
> 0 && write_symbols
!= SDB_DEBUG
)
487 if (align_loops
<= 0)
489 if (align_jumps
<= 0)
492 if (align_functions
<= 0)
493 align_functions
= 16;
495 /* Acquire a unique set number for our register saves and restores. */
496 alpha_sr_alias_set
= new_alias_set ();
498 /* Register variables and functions with the garbage collector. */
500 #if TARGET_ABI_UNICOSMK
501 /* Set up function hooks. */
502 init_machine_status
= alpha_init_machine_status
;
503 mark_machine_status
= alpha_mark_machine_status
;
504 free_machine_status
= alpha_free_machine_status
;
508 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
516 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
518 if ((value
& 0xff) != 0 && (value
& 0xff) != 0xff)
524 /* Returns 1 if OP is either the constant zero or a register. If a
525 register, it must be in the proper mode unless MODE is VOIDmode. */
528 reg_or_0_operand (op
, mode
)
530 enum machine_mode mode
;
532 return op
== const0_rtx
|| register_operand (op
, mode
);
535 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
539 reg_or_6bit_operand (op
, mode
)
541 enum machine_mode mode
;
543 return ((GET_CODE (op
) == CONST_INT
544 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64)
545 || register_operand (op
, mode
));
549 /* Return 1 if OP is an 8-bit constant or any register. */
552 reg_or_8bit_operand (op
, mode
)
554 enum machine_mode mode
;
556 return ((GET_CODE (op
) == CONST_INT
557 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100)
558 || register_operand (op
, mode
));
561 /* Return 1 if OP is an 8-bit constant. */
564 cint8_operand (op
, mode
)
566 enum machine_mode mode ATTRIBUTE_UNUSED
;
568 return ((GET_CODE (op
) == CONST_INT
569 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100));
572 /* Return 1 if the operand is a valid second operand to an add insn. */
575 add_operand (op
, mode
)
577 enum machine_mode mode
;
579 if (GET_CODE (op
) == CONST_INT
)
580 /* Constraints I, J, O and P are covered by K. */
581 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K')
582 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'));
584 return register_operand (op
, mode
);
587 /* Return 1 if the operand is a valid second operand to a sign-extending
591 sext_add_operand (op
, mode
)
593 enum machine_mode mode
;
595 if (GET_CODE (op
) == CONST_INT
)
596 return (CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I')
597 || CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'));
599 return reg_not_elim_operand (op
, mode
);
602 /* Return 1 if OP is the constant 4 or 8. */
605 const48_operand (op
, mode
)
607 enum machine_mode mode ATTRIBUTE_UNUSED
;
609 return (GET_CODE (op
) == CONST_INT
610 && (INTVAL (op
) == 4 || INTVAL (op
) == 8));
613 /* Return 1 if OP is a valid first operand to an AND insn. */
616 and_operand (op
, mode
)
618 enum machine_mode mode
;
620 if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == VOIDmode
)
621 return (zap_mask (CONST_DOUBLE_LOW (op
))
622 && zap_mask (CONST_DOUBLE_HIGH (op
)));
624 if (GET_CODE (op
) == CONST_INT
)
625 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
626 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100
627 || zap_mask (INTVAL (op
)));
629 return register_operand (op
, mode
);
632 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
635 or_operand (op
, mode
)
637 enum machine_mode mode
;
639 if (GET_CODE (op
) == CONST_INT
)
640 return ((unsigned HOST_WIDE_INT
) INTVAL (op
) < 0x100
641 || (unsigned HOST_WIDE_INT
) ~ INTVAL (op
) < 0x100);
643 return register_operand (op
, mode
);
646 /* Return 1 if OP is a constant that is the width, in bits, of an integral
647 mode smaller than DImode. */
650 mode_width_operand (op
, mode
)
652 enum machine_mode mode ATTRIBUTE_UNUSED
;
654 return (GET_CODE (op
) == CONST_INT
655 && (INTVAL (op
) == 8 || INTVAL (op
) == 16
656 || INTVAL (op
) == 32 || INTVAL (op
) == 64));
659 /* Return 1 if OP is a constant that is the width of an integral machine mode
660 smaller than an integer. */
663 mode_mask_operand (op
, mode
)
665 enum machine_mode mode ATTRIBUTE_UNUSED
;
667 #if HOST_BITS_PER_WIDE_INT == 32
668 if (GET_CODE (op
) == CONST_DOUBLE
)
669 return (CONST_DOUBLE_LOW (op
) == -1
670 && (CONST_DOUBLE_HIGH (op
) == -1
671 || CONST_DOUBLE_HIGH (op
) == 0));
673 if (GET_CODE (op
) == CONST_DOUBLE
)
674 return (CONST_DOUBLE_LOW (op
) == -1 && CONST_DOUBLE_HIGH (op
) == 0);
677 return (GET_CODE (op
) == CONST_INT
678 && (INTVAL (op
) == 0xff
679 || INTVAL (op
) == 0xffff
680 || INTVAL (op
) == (HOST_WIDE_INT
)0xffffffff
681 #if HOST_BITS_PER_WIDE_INT == 64
687 /* Return 1 if OP is a multiple of 8 less than 64. */
690 mul8_operand (op
, mode
)
692 enum machine_mode mode ATTRIBUTE_UNUSED
;
694 return (GET_CODE (op
) == CONST_INT
695 && (unsigned HOST_WIDE_INT
) INTVAL (op
) < 64
696 && (INTVAL (op
) & 7) == 0);
699 /* Return 1 if OP is the constant zero in floating-point. */
702 fp0_operand (op
, mode
)
704 enum machine_mode mode
;
706 return (GET_MODE (op
) == mode
707 && GET_MODE_CLASS (mode
) == MODE_FLOAT
&& op
== CONST0_RTX (mode
));
710 /* Return 1 if OP is the floating-point constant zero or a register. */
713 reg_or_fp0_operand (op
, mode
)
715 enum machine_mode mode
;
717 return fp0_operand (op
, mode
) || register_operand (op
, mode
);
720 /* Return 1 if OP is a hard floating-point register. */
723 hard_fp_register_operand (op
, mode
)
725 enum machine_mode mode
;
727 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
730 if (GET_CODE (op
) == SUBREG
)
731 op
= SUBREG_REG (op
);
732 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == FLOAT_REGS
;
735 /* Return 1 if OP is a hard general register. */
738 hard_int_register_operand (op
, mode
)
740 enum machine_mode mode
;
742 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
745 if (GET_CODE (op
) == SUBREG
)
746 op
= SUBREG_REG (op
);
747 return GET_CODE (op
) == REG
&& REGNO_REG_CLASS (REGNO (op
)) == GENERAL_REGS
;
750 /* Return 1 if OP is a register or a constant integer. */
754 reg_or_cint_operand (op
, mode
)
756 enum machine_mode mode
;
758 return (GET_CODE (op
) == CONST_INT
759 || register_operand (op
, mode
));
762 /* Return 1 if OP is something that can be reloaded into a register;
763 if it is a MEM, it need not be valid. */
766 some_operand (op
, mode
)
768 enum machine_mode mode
;
770 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
773 switch (GET_CODE (op
))
775 case REG
: case MEM
: case CONST_DOUBLE
: case CONST_INT
: case LABEL_REF
:
776 case SYMBOL_REF
: case CONST
: case HIGH
:
780 return some_operand (SUBREG_REG (op
), VOIDmode
);
789 /* Likewise, but don't accept constants. */
792 some_ni_operand (op
, mode
)
794 enum machine_mode mode
;
796 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
799 if (GET_CODE (op
) == SUBREG
)
800 op
= SUBREG_REG (op
);
802 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == MEM
);
805 /* Return 1 if OP is a valid operand for the source of a move insn. */
808 input_operand (op
, mode
)
810 enum machine_mode mode
;
812 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
815 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& GET_MODE (op
) != mode
)
818 switch (GET_CODE (op
))
823 if (TARGET_EXPLICIT_RELOCS
)
825 /* We don't split symbolic operands into something unintelligable
826 until after reload, but we do not wish non-small, non-global
827 symbolic operands to be reconstructed from their high/lo_sum
829 return (small_symbolic_operand (op
, mode
)
830 || global_symbolic_operand (op
, mode
));
833 /* This handles both the Windows/NT and OSF cases. */
834 return mode
== ptr_mode
|| mode
== DImode
;
837 return (TARGET_EXPLICIT_RELOCS
838 && local_symbolic_operand (XEXP (op
, 0), mode
));
845 if (register_operand (op
, mode
))
847 /* ... fall through ... */
849 return ((TARGET_BWX
|| (mode
!= HImode
&& mode
!= QImode
))
850 && general_operand (op
, mode
));
853 return GET_MODE_CLASS (mode
) == MODE_FLOAT
&& op
== CONST0_RTX (mode
);
856 return mode
== QImode
|| mode
== HImode
|| add_operand (op
, mode
);
868 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
869 file, and in the same section as the current function. */
872 current_file_function_operand (op
, mode
)
874 enum machine_mode mode ATTRIBUTE_UNUSED
;
876 if (GET_CODE (op
) != SYMBOL_REF
)
879 /* Easy test for recursion. */
880 if (op
== XEXP (DECL_RTL (current_function_decl
), 0))
883 /* Otherwise, we need the DECL for the SYMBOL_REF, which we can't get.
884 So SYMBOL_REF_FLAG has been declared to imply that the function is
885 in the default text section. So we must also check that the current
886 function is also in the text section. */
887 if (SYMBOL_REF_FLAG (op
) && decl_in_text_section (current_function_decl
))
893 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
896 direct_call_operand (op
, mode
)
898 enum machine_mode mode
;
900 /* Must be defined in this file. */
901 if (! current_file_function_operand (op
, mode
))
904 /* If profiling is implemented via linker tricks, we can't jump
905 to the nogp alternate entry point. */
906 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
907 but is approximately correct for the OSF ABIs. Don't know
908 what to do for VMS, NT, or UMK. */
909 if (! TARGET_PROFILING_NEEDS_GP
910 && ! current_function_profile
)
916 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
917 a variable known to be defined in this file. */
923 const char *str
= XSTR (op
, 0);
925 /* ??? SYMBOL_REF_FLAG is set for local function symbols, but we
926 run into problems with the rtl inliner in that the symbol was
927 once external, but is local after inlining, which results in
928 unrecognizable insns. */
930 return (CONSTANT_POOL_ADDRESS_P (op
)
931 /* If @, then ENCODE_SECTION_INFO sez it's local. */
933 /* If *$, then ASM_GENERATE_INTERNAL_LABEL sez it's local. */
934 || (str
[0] == '*' && str
[1] == '$'));
938 local_symbolic_operand (op
, mode
)
940 enum machine_mode mode
;
942 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
945 if (GET_CODE (op
) == LABEL_REF
)
948 if (GET_CODE (op
) == CONST
949 && GET_CODE (XEXP (op
, 0)) == PLUS
950 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
951 op
= XEXP (XEXP (op
, 0), 0);
953 if (GET_CODE (op
) != SYMBOL_REF
)
956 return local_symbol_p (op
);
959 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
960 known to be defined in this file in the small data area. */
963 small_symbolic_operand (op
, mode
)
965 enum machine_mode mode ATTRIBUTE_UNUSED
;
969 if (! TARGET_SMALL_DATA
)
972 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
975 if (GET_CODE (op
) == CONST
976 && GET_CODE (XEXP (op
, 0)) == PLUS
977 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
978 op
= XEXP (XEXP (op
, 0), 0);
980 if (GET_CODE (op
) != SYMBOL_REF
)
983 if (CONSTANT_POOL_ADDRESS_P (op
))
984 return GET_MODE_SIZE (get_pool_mode (op
)) <= (unsigned) g_switch_value
;
988 return str
[0] == '@' && str
[1] == 's';
992 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
993 not known (or known not) to be defined in this file. */
996 global_symbolic_operand (op
, mode
)
998 enum machine_mode mode
;
1000 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1003 if (GET_CODE (op
) == CONST
1004 && GET_CODE (XEXP (op
, 0)) == PLUS
1005 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1006 op
= XEXP (XEXP (op
, 0), 0);
1008 if (GET_CODE (op
) != SYMBOL_REF
)
1011 return ! local_symbol_p (op
);
1014 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
1017 call_operand (op
, mode
)
1019 enum machine_mode mode
;
1024 if (GET_CODE (op
) == REG
)
1028 /* Disallow virtual registers to cope with pathalogical test cases
1029 such as compile/930117-1.c in which the virtual reg decomposes
1030 to the frame pointer. Which is a hard reg that is not $27. */
1031 return (REGNO (op
) == 27 || REGNO (op
) > LAST_VIRTUAL_REGISTER
);
1036 if (TARGET_ABI_UNICOSMK
)
1038 if (GET_CODE (op
) == SYMBOL_REF
)
1044 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1045 possibly with an offset. */
1048 symbolic_operand (op
, mode
)
1050 enum machine_mode mode
;
1052 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1054 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1056 if (GET_CODE (op
) == CONST
1057 && GET_CODE (XEXP (op
,0)) == PLUS
1058 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1059 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1064 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1065 comparisons are valid in which insn. */
1068 alpha_comparison_operator (op
, mode
)
1070 enum machine_mode mode
;
1072 enum rtx_code code
= GET_CODE (op
);
1074 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1077 return (code
== EQ
|| code
== LE
|| code
== LT
1078 || code
== LEU
|| code
== LTU
);
1081 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1082 Here we know which comparisons are valid in which insn. */
1085 alpha_zero_comparison_operator (op
, mode
)
1087 enum machine_mode mode
;
1089 enum rtx_code code
= GET_CODE (op
);
1091 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1094 return (code
== EQ
|| code
== NE
|| code
== LE
|| code
== LT
1095 || code
== LEU
|| code
== LTU
);
1098 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1101 alpha_swapped_comparison_operator (op
, mode
)
1103 enum machine_mode mode
;
1105 enum rtx_code code
= GET_CODE (op
);
1107 if ((mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1108 || GET_RTX_CLASS (code
) != '<')
1111 code
= swap_condition (code
);
1112 return (code
== EQ
|| code
== LE
|| code
== LT
1113 || code
== LEU
|| code
== LTU
);
1116 /* Return 1 if OP is a signed comparison operation. */
1119 signed_comparison_operator (op
, mode
)
1121 enum machine_mode mode ATTRIBUTE_UNUSED
;
1123 enum rtx_code code
= GET_CODE (op
);
1125 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1128 return (code
== EQ
|| code
== NE
1129 || code
== LE
|| code
== LT
1130 || code
== GE
|| code
== GT
);
1133 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1134 Here we know which comparisons are valid in which insn. */
1137 alpha_fp_comparison_operator (op
, mode
)
1139 enum machine_mode mode
;
1141 enum rtx_code code
= GET_CODE (op
);
1143 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
1146 return (code
== EQ
|| code
== LE
|| code
== LT
|| code
== UNORDERED
);
1149 /* Return 1 if this is a divide or modulus operator. */
1152 divmod_operator (op
, mode
)
1154 enum machine_mode mode ATTRIBUTE_UNUSED
;
1156 switch (GET_CODE (op
))
1158 case DIV
: case MOD
: case UDIV
: case UMOD
:
1168 /* Return 1 if this memory address is a known aligned register plus
1169 a constant. It must be a valid address. This means that we can do
1170 this as an aligned reference plus some offset.
1172 Take into account what reload will do. */
1175 aligned_memory_operand (op
, mode
)
1177 enum machine_mode mode
;
1181 if (reload_in_progress
)
1184 if (GET_CODE (tmp
) == SUBREG
)
1185 tmp
= SUBREG_REG (tmp
);
1186 if (GET_CODE (tmp
) == REG
1187 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1189 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1195 if (GET_CODE (op
) != MEM
1196 || GET_MODE (op
) != mode
)
1200 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1201 sorts of constructs. Dig for the real base register. */
1202 if (reload_in_progress
1203 && GET_CODE (op
) == PLUS
1204 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1205 base
= XEXP (XEXP (op
, 0), 0);
1208 if (! memory_address_p (mode
, op
))
1210 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1213 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) >= 32);
1216 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1219 unaligned_memory_operand (op
, mode
)
1221 enum machine_mode mode
;
1225 if (reload_in_progress
)
1228 if (GET_CODE (tmp
) == SUBREG
)
1229 tmp
= SUBREG_REG (tmp
);
1230 if (GET_CODE (tmp
) == REG
1231 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1233 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1239 if (GET_CODE (op
) != MEM
1240 || GET_MODE (op
) != mode
)
1244 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1245 sorts of constructs. Dig for the real base register. */
1246 if (reload_in_progress
1247 && GET_CODE (op
) == PLUS
1248 && GET_CODE (XEXP (op
, 0)) == PLUS
)
1249 base
= XEXP (XEXP (op
, 0), 0);
1252 if (! memory_address_p (mode
, op
))
1254 base
= (GET_CODE (op
) == PLUS
? XEXP (op
, 0) : op
);
1257 return (GET_CODE (base
) == REG
&& REGNO_POINTER_ALIGN (REGNO (base
)) < 32);
1260 /* Return 1 if OP is either a register or an unaligned memory location. */
1263 reg_or_unaligned_mem_operand (op
, mode
)
1265 enum machine_mode mode
;
1267 return register_operand (op
, mode
) || unaligned_memory_operand (op
, mode
);
1270 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1273 any_memory_operand (op
, mode
)
1275 enum machine_mode mode ATTRIBUTE_UNUSED
;
1277 return (GET_CODE (op
) == MEM
1278 || (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
1279 || (reload_in_progress
&& GET_CODE (op
) == REG
1280 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1281 || (reload_in_progress
&& GET_CODE (op
) == SUBREG
1282 && GET_CODE (SUBREG_REG (op
)) == REG
1283 && REGNO (SUBREG_REG (op
)) >= FIRST_PSEUDO_REGISTER
));
1286 /* Returns 1 if OP is not an eliminable register.
1288 This exists to cure a pathological abort in the s8addq (et al) patterns,
1290 long foo () { long t; bar(); return (long) &t * 26107; }
1292 which run afoul of a hack in reload to cure a (presumably) similar
1293 problem with lea-type instructions on other targets. But there is
1294 one of us and many of them, so work around the problem by selectively
1295 preventing combine from making the optimization. */
1298 reg_not_elim_operand (op
, mode
)
1300 enum machine_mode mode
;
1303 if (GET_CODE (op
) == SUBREG
)
1304 inner
= SUBREG_REG (op
);
1305 if (inner
== frame_pointer_rtx
|| inner
== arg_pointer_rtx
)
1308 return register_operand (op
, mode
);
1311 /* Return 1 is OP is a memory location that is not a reference (using
1312 an AND) to an unaligned location. Take into account what reload
1316 normal_memory_operand (op
, mode
)
1318 enum machine_mode mode ATTRIBUTE_UNUSED
;
1320 if (reload_in_progress
)
1323 if (GET_CODE (tmp
) == SUBREG
)
1324 tmp
= SUBREG_REG (tmp
);
1325 if (GET_CODE (tmp
) == REG
1326 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
)
1328 op
= reg_equiv_memory_loc
[REGNO (tmp
)];
1330 /* This may not have been assigned an equivalent address if it will
1331 be eliminated. In that case, it doesn't matter what we do. */
1337 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) != AND
;
1340 /* Accept a register, but not a subreg of any kind. This allows us to
1341 avoid pathological cases in reload wrt data movement common in
1342 int->fp conversion. */
1345 reg_no_subreg_operand (op
, mode
)
1347 enum machine_mode mode
;
1349 if (GET_CODE (op
) != REG
)
1351 return register_operand (op
, mode
);
1354 /* Recognize an addition operation that includes a constant. Used to
1355 convince reload to canonize (plus (plus reg c1) c2) during register
1359 addition_operation (op
, mode
)
1361 enum machine_mode mode
;
1363 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1365 if (GET_CODE (op
) == PLUS
1366 && register_operand (XEXP (op
, 0), mode
)
1367 && GET_CODE (XEXP (op
, 1)) == CONST_INT
1368 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op
, 1)), 'K'))
1373 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1374 the range defined for C in [I-P]. */
1377 alpha_const_ok_for_letter_p (value
, c
)
1378 HOST_WIDE_INT value
;
1384 /* An unsigned 8 bit constant. */
1385 return (unsigned HOST_WIDE_INT
) value
< 0x100;
1387 /* The constant zero. */
1390 /* A signed 16 bit constant. */
1391 return (unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000;
1393 /* A shifted signed 16 bit constant appropriate for LDAH. */
1394 return ((value
& 0xffff) == 0
1395 && ((value
) >> 31 == -1 || value
>> 31 == 0));
1397 /* A constant that can be AND'ed with using a ZAP insn. */
1398 return zap_mask (value
);
1400 /* A complemented unsigned 8 bit constant. */
1401 return (unsigned HOST_WIDE_INT
) (~ value
) < 0x100;
1403 /* A negated unsigned 8 bit constant. */
1404 return (unsigned HOST_WIDE_INT
) (- value
) < 0x100;
1406 /* The constant 1, 2 or 3. */
1407 return value
== 1 || value
== 2 || value
== 3;
1414 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1415 matches for C in [GH]. */
1418 alpha_const_double_ok_for_letter_p (value
, c
)
1425 /* The floating point zero constant. */
1426 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
1427 && value
== CONST0_RTX (GET_MODE (value
)));
1430 /* A valid operand of a ZAP insn. */
1431 return (GET_MODE (value
) == VOIDmode
1432 && zap_mask (CONST_DOUBLE_LOW (value
))
1433 && zap_mask (CONST_DOUBLE_HIGH (value
)));
1440 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1444 alpha_extra_constraint (value
, c
)
1451 return normal_memory_operand (value
, VOIDmode
);
1453 return direct_call_operand (value
, Pmode
);
1455 return (GET_CODE (value
) == CONST_INT
1456 && (unsigned HOST_WIDE_INT
) INTVAL (value
) < 64);
1458 return GET_CODE (value
) == HIGH
;
1460 return TARGET_ABI_UNICOSMK
&& symbolic_operand (value
, VOIDmode
);
1467 /* Return 1 if this function can directly return via $26. */
1472 return (! TARGET_ABI_OPEN_VMS
&& ! TARGET_ABI_UNICOSMK
1474 && alpha_sa_size () == 0
1475 && get_frame_size () == 0
1476 && current_function_outgoing_args_size
== 0
1477 && current_function_pretend_args_size
== 0);
1480 /* Return the ADDR_VEC associated with a tablejump insn. */
1483 alpha_tablejump_addr_vec (insn
)
1488 tmp
= JUMP_LABEL (insn
);
1491 tmp
= NEXT_INSN (tmp
);
1494 if (GET_CODE (tmp
) == JUMP_INSN
1495 && GET_CODE (PATTERN (tmp
)) == ADDR_DIFF_VEC
)
1496 return PATTERN (tmp
);
1500 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1503 alpha_tablejump_best_label (insn
)
1506 rtx jump_table
= alpha_tablejump_addr_vec (insn
);
1507 rtx best_label
= NULL_RTX
;
1509 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1510 there for edge frequency counts from profile data. */
1514 int n_labels
= XVECLEN (jump_table
, 1);
1515 int best_count
= -1;
1518 for (i
= 0; i
< n_labels
; i
++)
1522 for (j
= i
+ 1; j
< n_labels
; j
++)
1523 if (XEXP (XVECEXP (jump_table
, 1, i
), 0)
1524 == XEXP (XVECEXP (jump_table
, 1, j
), 0))
1527 if (count
> best_count
)
1528 best_count
= count
, best_label
= XVECEXP (jump_table
, 1, i
);
1532 return best_label
? best_label
: const0_rtx
;
1535 /* Return true if the function DECL will be placed in the default text
1537 /* ??? Ideally we'd be able to always move from a SYMBOL_REF back to the
1538 decl, as that would allow us to determine if two functions are in the
1539 same section, which is what we really want to know. */
1542 decl_in_text_section (decl
)
1545 return (DECL_SECTION_NAME (decl
) == NULL_TREE
1546 && ! (flag_function_sections
1547 || (targetm
.have_named_sections
1548 && DECL_ONE_ONLY (decl
))));
1551 /* If we are referencing a function that is static, make the SYMBOL_REF
1552 special. We use this to see indicate we can branch to this function
1553 without setting PV or restoring GP.
1555 If this is a variable that is known to be defined locally, add "@v"
1556 to the name. If in addition the variable is to go in .sdata/.sbss,
1557 then add "@s" instead. */
1560 alpha_encode_section_info (decl
)
1563 const char *symbol_str
;
1564 bool is_local
, is_small
;
1566 if (TREE_CODE (decl
) == FUNCTION_DECL
)
1568 /* We mark public functions once they are emitted; otherwise we
1569 don't know that they exist in this unit of translation. */
1570 if (TREE_PUBLIC (decl
))
1572 /* Do not mark functions that are not in .text; otherwise we
1573 don't know that they are near enough for a direct branch. */
1574 if (! decl_in_text_section (decl
))
1577 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl
), 0)) = 1;
1581 /* Early out if we're not going to do anything with this data. */
1582 if (! TARGET_EXPLICIT_RELOCS
)
1585 /* Careful not to prod global register variables. */
1586 if (TREE_CODE (decl
) != VAR_DECL
1587 || GET_CODE (DECL_RTL (decl
)) != MEM
1588 || GET_CODE (XEXP (DECL_RTL (decl
), 0)) != SYMBOL_REF
)
1591 symbol_str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
1593 /* A variable is considered "local" if it is defined in this module. */
1595 if (DECL_EXTERNAL (decl
))
1597 /* Linkonce and weak data is never local. */
1598 else if (DECL_ONE_ONLY (decl
) || DECL_WEAK (decl
))
1600 else if (! TREE_PUBLIC (decl
))
1602 /* If PIC, then assume that any global name can be overridden by
1603 symbols resolved from other modules. */
1606 /* Uninitialized COMMON variable may be unified with symbols
1607 resolved from other modules. */
1608 else if (DECL_COMMON (decl
)
1609 && (DECL_INITIAL (decl
) == NULL
1610 || DECL_INITIAL (decl
) == error_mark_node
))
1612 /* Otherwise we're left with initialized (or non-common) global data
1613 which is of necessity defined locally. */
1617 /* Determine if DECL will wind up in .sdata/.sbss. */
1620 if (DECL_SECTION_NAME (decl
))
1622 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
1623 if (strcmp (section
, ".sdata") == 0
1624 || strcmp (section
, ".sbss") == 0)
1629 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
1631 /* If the variable has already been defined in the output file, then it
1632 is too late to put it in sdata if it wasn't put there in the first
1633 place. The test is here rather than above, because if it is already
1634 in sdata, then it can stay there. */
1636 if (TREE_ASM_WRITTEN (decl
))
1639 /* If this is an incomplete type with size 0, then we can't put it in
1640 sdata because it might be too big when completed. */
1641 else if (size
> 0 && size
<= g_switch_value
)
1645 /* Finally, encode this into the symbol string. */
1652 if (symbol_str
[0] == '@')
1654 if (symbol_str
[1] == (is_small
? 's' : 'v'))
1659 len
= strlen (symbol_str
) + 1;
1660 newstr
= alloca (len
+ 2);
1663 newstr
[1] = (is_small
? 's' : 'v');
1664 memcpy (newstr
+ 2, symbol_str
, len
);
1666 string
= ggc_alloc_string (newstr
, len
+ 2 - 1);
1667 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = string
;
1669 else if (symbol_str
[0] == '@')
1673 /* legitimate_address_p recognizes an RTL expression that is a valid
1674 memory address for an instruction. The MODE argument is the
1675 machine mode for the MEM expression that wants to use this address.
1677 For Alpha, we have either a constant address or the sum of a
1678 register and a constant address, or just a register. For DImode,
1679 any of those forms can be surrounded with an AND that clear the
1680 low-order three bits; this is an "unaligned" access. */
1683 alpha_legitimate_address_p (mode
, x
, strict
)
1684 enum machine_mode mode
;
1688 /* If this is an ldq_u type address, discard the outer AND. */
1690 && GET_CODE (x
) == AND
1691 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1692 && INTVAL (XEXP (x
, 1)) == -8)
1695 /* Discard non-paradoxical subregs. */
1696 if (GET_CODE (x
) == SUBREG
1697 && (GET_MODE_SIZE (GET_MODE (x
))
1698 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1701 /* Unadorned general registers are valid. */
1704 ? STRICT_REG_OK_FOR_BASE_P (x
)
1705 : NONSTRICT_REG_OK_FOR_BASE_P (x
)))
1708 /* Constant addresses (i.e. +/- 32k) are valid. */
1709 if (CONSTANT_ADDRESS_P (x
))
1712 /* Register plus a small constant offset is valid. */
1713 if (GET_CODE (x
) == PLUS
)
1715 rtx ofs
= XEXP (x
, 1);
1718 /* Discard non-paradoxical subregs. */
1719 if (GET_CODE (x
) == SUBREG
1720 && (GET_MODE_SIZE (GET_MODE (x
))
1721 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1727 && NONSTRICT_REG_OK_FP_BASE_P (x
)
1728 && GET_CODE (ofs
) == CONST_INT
)
1731 ? STRICT_REG_OK_FOR_BASE_P (x
)
1732 : NONSTRICT_REG_OK_FOR_BASE_P (x
))
1733 && CONSTANT_ADDRESS_P (ofs
))
1736 else if (GET_CODE (x
) == ADDRESSOF
1737 && GET_CODE (ofs
) == CONST_INT
)
1741 /* If we're managing explicit relocations, LO_SUM is valid, as
1742 are small data symbols. */
1743 else if (TARGET_EXPLICIT_RELOCS
)
1745 if (small_symbolic_operand (x
, Pmode
))
1748 if (GET_CODE (x
) == LO_SUM
)
1750 rtx ofs
= XEXP (x
, 1);
1753 /* Discard non-paradoxical subregs. */
1754 if (GET_CODE (x
) == SUBREG
1755 && (GET_MODE_SIZE (GET_MODE (x
))
1756 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
1759 /* Must have a valid base register. */
1762 ? STRICT_REG_OK_FOR_BASE_P (x
)
1763 : NONSTRICT_REG_OK_FOR_BASE_P (x
))))
1766 /* The symbol must be local. */
1767 if (local_symbolic_operand (ofs
, Pmode
))
1775 /* Try machine-dependent ways of modifying an illegitimate address
1776 to be legitimate. If we find one, return the new, valid address. */
1779 alpha_legitimize_address (x
, scratch
, mode
)
1782 enum machine_mode mode ATTRIBUTE_UNUSED
;
1784 HOST_WIDE_INT addend
;
1786 /* If the address is (plus reg const_int) and the CONST_INT is not a
1787 valid offset, compute the high part of the constant and add it to
1788 the register. Then our address is (plus temp low-part-const). */
1789 if (GET_CODE (x
) == PLUS
1790 && GET_CODE (XEXP (x
, 0)) == REG
1791 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1792 && ! CONSTANT_ADDRESS_P (XEXP (x
, 1)))
1794 addend
= INTVAL (XEXP (x
, 1));
1799 /* If the address is (const (plus FOO const_int)), find the low-order
1800 part of the CONST_INT. Then load FOO plus any high-order part of the
1801 CONST_INT into a register. Our address is (plus reg low-part-const).
1802 This is done to reduce the number of GOT entries. */
1804 && GET_CODE (x
) == CONST
1805 && GET_CODE (XEXP (x
, 0)) == PLUS
1806 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
1808 addend
= INTVAL (XEXP (XEXP (x
, 0), 1));
1809 x
= force_reg (Pmode
, XEXP (XEXP (x
, 0), 0));
1813 /* If we have a (plus reg const), emit the load as in (2), then add
1814 the two registers, and finally generate (plus reg low-part-const) as
1817 && GET_CODE (x
) == PLUS
1818 && GET_CODE (XEXP (x
, 0)) == REG
1819 && GET_CODE (XEXP (x
, 1)) == CONST
1820 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == PLUS
1821 && GET_CODE (XEXP (XEXP (XEXP (x
, 1), 0), 1)) == CONST_INT
)
1823 addend
= INTVAL (XEXP (XEXP (XEXP (x
, 1), 0), 1));
1824 x
= expand_simple_binop (Pmode
, PLUS
, XEXP (x
, 0),
1825 XEXP (XEXP (XEXP (x
, 1), 0), 0),
1826 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1830 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1831 if (TARGET_EXPLICIT_RELOCS
&& symbolic_operand (x
, Pmode
))
1833 if (local_symbolic_operand (x
, Pmode
))
1835 if (small_symbolic_operand (x
, Pmode
))
1839 if (!no_new_pseudos
)
1840 scratch
= gen_reg_rtx (Pmode
);
1841 emit_insn (gen_rtx_SET (VOIDmode
, scratch
,
1842 gen_rtx_HIGH (Pmode
, x
)));
1843 return gen_rtx_LO_SUM (Pmode
, scratch
, x
);
1852 HOST_WIDE_INT low
, high
;
1854 low
= ((addend
& 0xffff) ^ 0x8000) - 0x8000;
1856 high
= ((addend
& 0xffffffff) ^ 0x80000000) - 0x80000000;
1860 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (addend
),
1861 (no_new_pseudos
? scratch
: NULL_RTX
),
1862 1, OPTAB_LIB_WIDEN
);
1864 x
= expand_simple_binop (Pmode
, PLUS
, x
, GEN_INT (high
),
1865 (no_new_pseudos
? scratch
: NULL_RTX
),
1866 1, OPTAB_LIB_WIDEN
);
1868 return plus_constant (x
, low
);
1872 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1873 small symbolic operand until after reload. At which point we need
1874 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1875 so that sched2 has the proper dependency information. */
1878 some_small_symbolic_mem_operand (x
, mode
)
1880 enum machine_mode mode ATTRIBUTE_UNUSED
;
1882 return for_each_rtx (&x
, some_small_symbolic_mem_operand_1
, NULL
);
1886 some_small_symbolic_mem_operand_1 (px
, data
)
1888 void *data ATTRIBUTE_UNUSED
;
1892 if (GET_CODE (x
) != MEM
)
1896 /* If this is an ldq_u type address, discard the outer AND. */
1897 if (GET_CODE (x
) == AND
)
1900 return small_symbolic_operand (x
, Pmode
) ? 1 : -1;
1904 split_small_symbolic_mem_operand (x
)
1908 for_each_rtx (&x
, split_small_symbolic_mem_operand_1
, NULL
);
1913 split_small_symbolic_mem_operand_1 (px
, data
)
1915 void *data ATTRIBUTE_UNUSED
;
1919 if (GET_CODE (x
) != MEM
)
1922 px
= &XEXP (x
, 0), x
= *px
;
1923 if (GET_CODE (x
) == AND
)
1924 px
= &XEXP (x
, 0), x
= *px
;
1926 if (small_symbolic_operand (x
, Pmode
))
1928 x
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, x
);
1935 /* Try a machine-dependent way of reloading an illegitimate address
1936 operand. If we find one, push the reload and return the new rtx. */
1939 alpha_legitimize_reload_address (x
, mode
, opnum
, type
, ind_levels
)
1941 enum machine_mode mode ATTRIBUTE_UNUSED
;
1944 int ind_levels ATTRIBUTE_UNUSED
;
1946 /* We must recognize output that we have already generated ourselves. */
1947 if (GET_CODE (x
) == PLUS
1948 && GET_CODE (XEXP (x
, 0)) == PLUS
1949 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1950 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1951 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1953 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1954 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1959 /* We wish to handle large displacements off a base register by
1960 splitting the addend across an ldah and the mem insn. This
1961 cuts number of extra insns needed from 3 to 1. */
1962 if (GET_CODE (x
) == PLUS
1963 && GET_CODE (XEXP (x
, 0)) == REG
1964 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
1965 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)))
1966 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1968 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
1969 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
1971 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
1973 /* Check for 32-bit overflow. */
1974 if (high
+ low
!= val
)
1977 /* Reload the high part into a base reg; leave the low part
1978 in the mem directly. */
1979 x
= gen_rtx_PLUS (GET_MODE (x
),
1980 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
1984 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
1985 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
1993 /* REF is an alignable memory location. Place an aligned SImode
1994 reference into *PALIGNED_MEM and the number of bits to shift into
1995 *PBITNUM. SCRATCH is a free register for use in reloading out
1996 of range stack slots. */
1999 get_aligned_mem (ref
, paligned_mem
, pbitnum
)
2001 rtx
*paligned_mem
, *pbitnum
;
2004 HOST_WIDE_INT offset
= 0;
2006 if (GET_CODE (ref
) != MEM
)
2009 if (reload_in_progress
2010 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2012 base
= find_replacement (&XEXP (ref
, 0));
2014 if (! memory_address_p (GET_MODE (ref
), base
))
2019 base
= XEXP (ref
, 0);
2022 if (GET_CODE (base
) == PLUS
)
2023 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2026 = widen_memory_access (ref
, SImode
, (offset
& ~3) - offset
);
2028 if (WORDS_BIG_ENDIAN
)
2029 *pbitnum
= GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref
))
2030 + (offset
& 3) * 8));
2032 *pbitnum
= GEN_INT ((offset
& 3) * 8);
2035 /* Similar, but just get the address. Handle the two reload cases.
2036 Add EXTRA_OFFSET to the address we return. */
2039 get_unaligned_address (ref
, extra_offset
)
2044 HOST_WIDE_INT offset
= 0;
2046 if (GET_CODE (ref
) != MEM
)
2049 if (reload_in_progress
2050 && ! memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
2052 base
= find_replacement (&XEXP (ref
, 0));
2054 if (! memory_address_p (GET_MODE (ref
), base
))
2059 base
= XEXP (ref
, 0);
2062 if (GET_CODE (base
) == PLUS
)
2063 offset
+= INTVAL (XEXP (base
, 1)), base
= XEXP (base
, 0);
2065 return plus_constant (base
, offset
+ extra_offset
);
2068 /* On the Alpha, all (non-symbolic) constants except zero go into
2069 a floating-point register via memory. Note that we cannot
2070 return anything that is not a subset of CLASS, and that some
2071 symbolic constants cannot be dropped to memory. */
2074 alpha_preferred_reload_class(x
, class)
2076 enum reg_class
class;
2078 /* Zero is present in any register class. */
2079 if (x
== CONST0_RTX (GET_MODE (x
)))
2082 /* These sorts of constants we can easily drop to memory. */
2083 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
2085 if (class == FLOAT_REGS
)
2087 if (class == ALL_REGS
)
2088 return GENERAL_REGS
;
2092 /* All other kinds of constants should not (and in the case of HIGH
2093 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2094 secondary reload. */
2096 return (class == ALL_REGS
? GENERAL_REGS
: class);
2101 /* Loading and storing HImode or QImode values to and from memory
2102 usually requires a scratch register. The exceptions are loading
2103 QImode and HImode from an aligned address to a general register
2104 unless byte instructions are permitted.
2106 We also cannot load an unaligned address or a paradoxical SUBREG
2107 into an FP register.
2109 We also cannot do integral arithmetic into FP regs, as might result
2110 from register elimination into a DImode fp register. */
2113 secondary_reload_class (class, mode
, x
, in
)
2114 enum reg_class
class;
2115 enum machine_mode mode
;
2119 if ((mode
== QImode
|| mode
== HImode
) && ! TARGET_BWX
)
2121 if (GET_CODE (x
) == MEM
2122 || (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
)
2123 || (GET_CODE (x
) == SUBREG
2124 && (GET_CODE (SUBREG_REG (x
)) == MEM
2125 || (GET_CODE (SUBREG_REG (x
)) == REG
2126 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
))))
2128 if (!in
|| !aligned_memory_operand(x
, mode
))
2129 return GENERAL_REGS
;
2133 if (class == FLOAT_REGS
)
2135 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
2136 return GENERAL_REGS
;
2138 if (GET_CODE (x
) == SUBREG
2139 && (GET_MODE_SIZE (GET_MODE (x
))
2140 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2141 return GENERAL_REGS
;
2143 if (in
&& INTEGRAL_MODE_P (mode
)
2144 && ! (memory_operand (x
, mode
) || x
== const0_rtx
))
2145 return GENERAL_REGS
;
2151 /* Subfunction of the following function. Update the flags of any MEM
2152 found in part of X. */
2155 alpha_set_memflags_1 (x
, in_struct_p
, volatile_p
, unchanging_p
)
2157 int in_struct_p
, volatile_p
, unchanging_p
;
2161 switch (GET_CODE (x
))
2165 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2166 alpha_set_memflags_1 (XVECEXP (x
, 0, i
), in_struct_p
, volatile_p
,
2171 alpha_set_memflags_1 (PATTERN (x
), in_struct_p
, volatile_p
,
2176 alpha_set_memflags_1 (SET_DEST (x
), in_struct_p
, volatile_p
,
2178 alpha_set_memflags_1 (SET_SRC (x
), in_struct_p
, volatile_p
,
2183 MEM_IN_STRUCT_P (x
) = in_struct_p
;
2184 MEM_VOLATILE_P (x
) = volatile_p
;
2185 RTX_UNCHANGING_P (x
) = unchanging_p
;
2186 /* Sadly, we cannot use alias sets because the extra aliasing
2187 produced by the AND interferes. Given that two-byte quantities
2188 are the only thing we would be able to differentiate anyway,
2189 there does not seem to be any point in convoluting the early
2190 out of the alias check. */
2198 /* Given INSN, which is either an INSN or a SEQUENCE generated to
2199 perform a memory operation, look for any MEMs in either a SET_DEST or
2200 a SET_SRC and copy the in-struct, unchanging, and volatile flags from
2201 REF into each of the MEMs found. If REF is not a MEM, don't do
2205 alpha_set_memflags (insn
, ref
)
2209 int in_struct_p
, volatile_p
, unchanging_p
;
2211 if (GET_CODE (ref
) != MEM
)
2214 in_struct_p
= MEM_IN_STRUCT_P (ref
);
2215 volatile_p
= MEM_VOLATILE_P (ref
);
2216 unchanging_p
= RTX_UNCHANGING_P (ref
);
2218 /* This is only called from alpha.md, after having had something
2219 generated from one of the insn patterns. So if everything is
2220 zero, the pattern is already up-to-date. */
2221 if (! in_struct_p
&& ! volatile_p
&& ! unchanging_p
)
2224 alpha_set_memflags_1 (insn
, in_struct_p
, volatile_p
, unchanging_p
);
2227 /* Try to output insns to set TARGET equal to the constant C if it can be
2228 done in less than N insns. Do all computations in MODE. Returns the place
2229 where the output has been placed if it can be done and the insns have been
2230 emitted. If it would take more than N insns, zero is returned and no
2231 insns and emitted. */
2234 alpha_emit_set_const (target
, mode
, c
, n
)
2236 enum machine_mode mode
;
2243 /* Try 1 insn, then 2, then up to N. */
2244 for (i
= 1; i
<= n
; i
++)
2245 if ((pat
= alpha_emit_set_const_1 (target
, mode
, c
, i
)) != 0)
2251 /* Internal routine for the above to check for N or below insns. */
2254 alpha_emit_set_const_1 (target
, mode
, c
, n
)
2256 enum machine_mode mode
;
2262 /* Use a pseudo if highly optimizing and still generating RTL. */
2264 = (flag_expensive_optimizations
&& rtx_equal_function_value_matters
2268 #if HOST_BITS_PER_WIDE_INT == 64
2269 /* We are only called for SImode and DImode. If this is SImode, ensure that
2270 we are sign extended to a full word. This does not make any sense when
2271 cross-compiling on a narrow machine. */
2274 c
= ((c
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2277 /* If this is a sign-extended 32-bit constant, we can do this in at most
2278 three insns, so do it if we have enough insns left. We always have
2279 a sign-extended 32-bit constant when compiling on a narrow machine. */
2281 if (HOST_BITS_PER_WIDE_INT
!= 64
2282 || c
>> 31 == -1 || c
>> 31 == 0)
2284 HOST_WIDE_INT low
= ((c
& 0xffff) ^ 0x8000) - 0x8000;
2285 HOST_WIDE_INT tmp1
= c
- low
;
2286 HOST_WIDE_INT high
= (((tmp1
>> 16) & 0xffff) ^ 0x8000) - 0x8000;
2287 HOST_WIDE_INT extra
= 0;
2289 /* If HIGH will be interpreted as negative but the constant is
2290 positive, we must adjust it to do two ldha insns. */
2292 if ((high
& 0x8000) != 0 && c
>= 0)
2296 high
= ((tmp1
>> 16) & 0xffff) - 2 * ((tmp1
>> 16) & 0x8000);
2299 if (c
== low
|| (low
== 0 && extra
== 0))
2301 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2302 but that meant that we can't handle INT_MIN on 32-bit machines
2303 (like NT/Alpha), because we recurse indefinitely through
2304 emit_move_insn to gen_movdi. So instead, since we know exactly
2305 what we want, create it explicitly. */
2308 target
= gen_reg_rtx (mode
);
2309 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (c
)));
2312 else if (n
>= 2 + (extra
!= 0))
2314 temp
= copy_to_suggested_reg (GEN_INT (high
<< 16), subtarget
, mode
);
2317 temp
= expand_binop (mode
, add_optab
, temp
, GEN_INT (extra
<< 16),
2318 subtarget
, 0, OPTAB_WIDEN
);
2320 return expand_binop (mode
, add_optab
, temp
, GEN_INT (low
),
2321 target
, 0, OPTAB_WIDEN
);
2325 /* If we couldn't do it that way, try some other methods. But if we have
2326 no instructions left, don't bother. Likewise, if this is SImode and
2327 we can't make pseudos, we can't do anything since the expand_binop
2328 and expand_unop calls will widen and try to make pseudos. */
2331 || (mode
== SImode
&& ! rtx_equal_function_value_matters
))
2334 /* Next, see if we can load a related constant and then shift and possibly
2335 negate it to get the constant we want. Try this once each increasing
2336 numbers of insns. */
2338 for (i
= 1; i
< n
; i
++)
2340 /* First, see if minus some low bits, we've an easy load of
2343 new = ((c
& 0xffff) ^ 0x8000) - 0x8000;
2345 && (temp
= alpha_emit_set_const (subtarget
, mode
, c
- new, i
)) != 0)
2346 return expand_binop (mode
, add_optab
, temp
, GEN_INT (new),
2347 target
, 0, OPTAB_WIDEN
);
2349 /* Next try complementing. */
2350 if ((temp
= alpha_emit_set_const (subtarget
, mode
, ~ c
, i
)) != 0)
2351 return expand_unop (mode
, one_cmpl_optab
, temp
, target
, 0);
2353 /* Next try to form a constant and do a left shift. We can do this
2354 if some low-order bits are zero; the exact_log2 call below tells
2355 us that information. The bits we are shifting out could be any
2356 value, but here we'll just try the 0- and sign-extended forms of
2357 the constant. To try to increase the chance of having the same
2358 constant in more than one insn, start at the highest number of
2359 bits to shift, but try all possibilities in case a ZAPNOT will
2362 if ((bits
= exact_log2 (c
& - c
)) > 0)
2363 for (; bits
> 0; bits
--)
2364 if ((temp
= (alpha_emit_set_const
2365 (subtarget
, mode
, c
>> bits
, i
))) != 0
2366 || ((temp
= (alpha_emit_set_const
2368 ((unsigned HOST_WIDE_INT
) c
) >> bits
, i
)))
2370 return expand_binop (mode
, ashl_optab
, temp
, GEN_INT (bits
),
2371 target
, 0, OPTAB_WIDEN
);
2373 /* Now try high-order zero bits. Here we try the shifted-in bits as
2374 all zero and all ones. Be careful to avoid shifting outside the
2375 mode and to avoid shifting outside the host wide int size. */
2376 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2377 confuse the recursive call and set all of the high 32 bits. */
2379 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2380 - floor_log2 (c
) - 1 - (HOST_BITS_PER_WIDE_INT
< 64))) > 0)
2381 for (; bits
> 0; bits
--)
2382 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2384 || ((temp
= (alpha_emit_set_const
2386 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2389 return expand_binop (mode
, lshr_optab
, temp
, GEN_INT (bits
),
2390 target
, 1, OPTAB_WIDEN
);
2392 /* Now try high-order 1 bits. We get that with a sign-extension.
2393 But one bit isn't enough here. Be careful to avoid shifting outside
2394 the mode and to avoid shifting outside the host wide int size. */
2396 if ((bits
= (MIN (HOST_BITS_PER_WIDE_INT
, GET_MODE_SIZE (mode
) * 8)
2397 - floor_log2 (~ c
) - 2)) > 0)
2398 for (; bits
> 0; bits
--)
2399 if ((temp
= alpha_emit_set_const (subtarget
, mode
,
2401 || ((temp
= (alpha_emit_set_const
2403 ((c
<< bits
) | (((HOST_WIDE_INT
) 1 << bits
) - 1)),
2406 return expand_binop (mode
, ashr_optab
, temp
, GEN_INT (bits
),
2407 target
, 0, OPTAB_WIDEN
);
2410 #if HOST_BITS_PER_WIDE_INT == 64
2411 /* Finally, see if can load a value into the target that is the same as the
2412 constant except that all bytes that are 0 are changed to be 0xff. If we
2413 can, then we can do a ZAPNOT to obtain the desired constant. */
2416 for (i
= 0; i
< 64; i
+= 8)
2417 if ((new & ((HOST_WIDE_INT
) 0xff << i
)) == 0)
2418 new |= (HOST_WIDE_INT
) 0xff << i
;
2420 /* We are only called for SImode and DImode. If this is SImode, ensure that
2421 we are sign extended to a full word. */
2424 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2426 if (new != c
&& new != -1
2427 && (temp
= alpha_emit_set_const (subtarget
, mode
, new, n
- 1)) != 0)
2428 return expand_binop (mode
, and_optab
, temp
, GEN_INT (c
| ~ new),
2429 target
, 0, OPTAB_WIDEN
);
2435 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2436 fall back to a straight forward decomposition. We do this to avoid
2437 exponential run times encountered when looking for longer sequences
2438 with alpha_emit_set_const. */
2441 alpha_emit_set_long_const (target
, c1
, c2
)
2443 HOST_WIDE_INT c1
, c2
;
2445 HOST_WIDE_INT d1
, d2
, d3
, d4
;
2447 /* Decompose the entire word */
2448 #if HOST_BITS_PER_WIDE_INT >= 64
2449 if (c2
!= -(c1
< 0))
2451 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2453 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2454 c1
= (c1
- d2
) >> 32;
2455 d3
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2457 d4
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2461 d1
= ((c1
& 0xffff) ^ 0x8000) - 0x8000;
2463 d2
= ((c1
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2467 d3
= ((c2
& 0xffff) ^ 0x8000) - 0x8000;
2469 d4
= ((c2
& 0xffffffff) ^ 0x80000000) - 0x80000000;
2474 /* Construct the high word */
2477 emit_move_insn (target
, GEN_INT (d4
));
2479 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d3
)));
2482 emit_move_insn (target
, GEN_INT (d3
));
2484 /* Shift it into place */
2485 emit_move_insn (target
, gen_rtx_ASHIFT (DImode
, target
, GEN_INT (32)));
2487 /* Add in the low bits. */
2489 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d2
)));
2491 emit_move_insn (target
, gen_rtx_PLUS (DImode
, target
, GEN_INT (d1
)));
2496 /* Expand a move instruction; return true if all work is done.
2497 We don't handle non-bwx subword loads here. */
2500 alpha_expand_mov (mode
, operands
)
2501 enum machine_mode mode
;
2504 /* If the output is not a register, the input must be. */
2505 if (GET_CODE (operands
[0]) == MEM
2506 && ! reg_or_0_operand (operands
[1], mode
))
2507 operands
[1] = force_reg (mode
, operands
[1]);
2509 /* Allow legitimize_address to perform some simplifications. */
2510 if (mode
== Pmode
&& symbolic_operand (operands
[1], mode
))
2512 rtx tmp
= alpha_legitimize_address (operands
[1], operands
[0], mode
);
2520 /* Early out for non-constants and valid constants. */
2521 if (! CONSTANT_P (operands
[1]) || input_operand (operands
[1], mode
))
2524 /* Split large integers. */
2525 if (GET_CODE (operands
[1]) == CONST_INT
2526 || GET_CODE (operands
[1]) == CONST_DOUBLE
)
2528 HOST_WIDE_INT i0
, i1
;
2529 rtx temp
= NULL_RTX
;
2531 if (GET_CODE (operands
[1]) == CONST_INT
)
2533 i0
= INTVAL (operands
[1]);
2536 else if (HOST_BITS_PER_WIDE_INT
>= 64)
2538 i0
= CONST_DOUBLE_LOW (operands
[1]);
2543 i0
= CONST_DOUBLE_LOW (operands
[1]);
2544 i1
= CONST_DOUBLE_HIGH (operands
[1]);
2547 if (HOST_BITS_PER_WIDE_INT
>= 64 || i1
== -(i0
< 0))
2548 temp
= alpha_emit_set_const (operands
[0], mode
, i0
, 3);
2550 if (!temp
&& TARGET_BUILD_CONSTANTS
)
2551 temp
= alpha_emit_set_long_const (operands
[0], i0
, i1
);
2555 if (rtx_equal_p (operands
[0], temp
))
2562 /* Otherwise we've nothing left but to drop the thing to memory. */
2563 operands
[1] = force_const_mem (DImode
, operands
[1]);
2564 if (reload_in_progress
)
2566 emit_move_insn (operands
[0], XEXP (operands
[1], 0));
2567 operands
[1] = copy_rtx (operands
[1]);
2568 XEXP (operands
[1], 0) = operands
[0];
2571 operands
[1] = validize_mem (operands
[1]);
2575 /* Expand a non-bwx QImode or HImode move instruction;
2576 return true if all work is done. */
2579 alpha_expand_mov_nobwx (mode
, operands
)
2580 enum machine_mode mode
;
2583 /* If the output is not a register, the input must be. */
2584 if (GET_CODE (operands
[0]) == MEM
)
2585 operands
[1] = force_reg (mode
, operands
[1]);
2587 /* Handle four memory cases, unaligned and aligned for either the input
2588 or the output. The only case where we can be called during reload is
2589 for aligned loads; all other cases require temporaries. */
2591 if (GET_CODE (operands
[1]) == MEM
2592 || (GET_CODE (operands
[1]) == SUBREG
2593 && GET_CODE (SUBREG_REG (operands
[1])) == MEM
)
2594 || (reload_in_progress
&& GET_CODE (operands
[1]) == REG
2595 && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
)
2596 || (reload_in_progress
&& GET_CODE (operands
[1]) == SUBREG
2597 && GET_CODE (SUBREG_REG (operands
[1])) == REG
2598 && REGNO (SUBREG_REG (operands
[1])) >= FIRST_PSEUDO_REGISTER
))
2600 if (aligned_memory_operand (operands
[1], mode
))
2602 if (reload_in_progress
)
2604 emit_insn ((mode
== QImode
2605 ? gen_reload_inqi_help
2606 : gen_reload_inhi_help
)
2607 (operands
[0], operands
[1],
2608 gen_rtx_REG (SImode
, REGNO (operands
[0]))));
2612 rtx aligned_mem
, bitnum
;
2613 rtx scratch
= gen_reg_rtx (SImode
);
2615 get_aligned_mem (operands
[1], &aligned_mem
, &bitnum
);
2617 emit_insn ((mode
== QImode
2618 ? gen_aligned_loadqi
2619 : gen_aligned_loadhi
)
2620 (operands
[0], aligned_mem
, bitnum
, scratch
));
2625 /* Don't pass these as parameters since that makes the generated
2626 code depend on parameter evaluation order which will cause
2627 bootstrap failures. */
2629 rtx temp1
= gen_reg_rtx (DImode
);
2630 rtx temp2
= gen_reg_rtx (DImode
);
2631 rtx seq
= ((mode
== QImode
2632 ? gen_unaligned_loadqi
2633 : gen_unaligned_loadhi
)
2634 (operands
[0], get_unaligned_address (operands
[1], 0),
2637 alpha_set_memflags (seq
, operands
[1]);
2643 if (GET_CODE (operands
[0]) == MEM
2644 || (GET_CODE (operands
[0]) == SUBREG
2645 && GET_CODE (SUBREG_REG (operands
[0])) == MEM
)
2646 || (reload_in_progress
&& GET_CODE (operands
[0]) == REG
2647 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
)
2648 || (reload_in_progress
&& GET_CODE (operands
[0]) == SUBREG
2649 && GET_CODE (SUBREG_REG (operands
[0])) == REG
2650 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
2652 if (aligned_memory_operand (operands
[0], mode
))
2654 rtx aligned_mem
, bitnum
;
2655 rtx temp1
= gen_reg_rtx (SImode
);
2656 rtx temp2
= gen_reg_rtx (SImode
);
2658 get_aligned_mem (operands
[0], &aligned_mem
, &bitnum
);
2660 emit_insn (gen_aligned_store (aligned_mem
, operands
[1], bitnum
,
2665 rtx temp1
= gen_reg_rtx (DImode
);
2666 rtx temp2
= gen_reg_rtx (DImode
);
2667 rtx temp3
= gen_reg_rtx (DImode
);
2668 rtx seq
= ((mode
== QImode
2669 ? gen_unaligned_storeqi
2670 : gen_unaligned_storehi
)
2671 (get_unaligned_address (operands
[0], 0),
2672 operands
[1], temp1
, temp2
, temp3
));
2674 alpha_set_memflags (seq
, operands
[0]);
2683 /* Generate an unsigned DImode to FP conversion. This is the same code
2684 optabs would emit if we didn't have TFmode patterns.
2686 For SFmode, this is the only construction I've found that can pass
2687 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2688 intermediates will work, because you'll get intermediate rounding
2689 that ruins the end result. Some of this could be fixed by turning
2690 on round-to-positive-infinity, but that requires diddling the fpsr,
2691 which kills performance. I tried turning this around and converting
2692 to a negative number, so that I could turn on /m, but either I did
2693 it wrong or there's something else cause I wound up with the exact
2694 same single-bit error. There is a branch-less form of this same code:
2705 fcmoveq $f10,$f11,$f0
2707 I'm not using it because it's the same number of instructions as
2708 this branch-full form, and it has more serialized long latency
2709 instructions on the critical path.
2711 For DFmode, we can avoid rounding errors by breaking up the word
2712 into two pieces, converting them separately, and adding them back:
2714 LC0: .long 0,0x5f800000
2719 cpyse $f11,$f31,$f10
2720 cpyse $f31,$f11,$f11
2728 This doesn't seem to be a clear-cut win over the optabs form.
2729 It probably all depends on the distribution of numbers being
2730 converted -- in the optabs form, all but high-bit-set has a
2731 much lower minimum execution time. */
2734 alpha_emit_floatuns (operands
)
2737 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
2738 enum machine_mode mode
;
2741 in
= force_reg (DImode
, operands
[1]);
2742 mode
= GET_MODE (out
);
2743 neglab
= gen_label_rtx ();
2744 donelab
= gen_label_rtx ();
2745 i0
= gen_reg_rtx (DImode
);
2746 i1
= gen_reg_rtx (DImode
);
2747 f0
= gen_reg_rtx (mode
);
2749 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
2751 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
2752 emit_jump_insn (gen_jump (donelab
));
2755 emit_label (neglab
);
2757 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
2758 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
2759 emit_insn (gen_iordi3 (i0
, i0
, i1
));
2760 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
2761 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
2763 emit_label (donelab
);
2766 /* Generate the comparison for a conditional branch. */
2769 alpha_emit_conditional_branch (code
)
2772 enum rtx_code cmp_code
, branch_code
;
2773 enum machine_mode cmp_mode
, branch_mode
= VOIDmode
;
2774 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
2777 if (alpha_compare
.fp_p
&& GET_MODE (op0
) == TFmode
)
2779 if (! TARGET_HAS_XFLOATING_LIBS
)
2782 /* X_floating library comparison functions return
2786 Convert the compare against the raw return value. */
2788 if (code
== UNORDERED
|| code
== ORDERED
)
2793 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
2795 alpha_compare
.fp_p
= 0;
2797 if (code
== UNORDERED
)
2799 else if (code
== ORDERED
)
2805 /* The general case: fold the comparison code to the types of compares
2806 that we have, choosing the branch as necessary. */
2809 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2811 /* We have these compares: */
2812 cmp_code
= code
, branch_code
= NE
;
2817 /* These must be reversed. */
2818 cmp_code
= reverse_condition (code
), branch_code
= EQ
;
2821 case GE
: case GT
: case GEU
: case GTU
:
2822 /* For FP, we swap them, for INT, we reverse them. */
2823 if (alpha_compare
.fp_p
)
2825 cmp_code
= swap_condition (code
);
2827 tem
= op0
, op0
= op1
, op1
= tem
;
2831 cmp_code
= reverse_condition (code
);
2840 if (alpha_compare
.fp_p
)
2843 if (flag_unsafe_math_optimizations
)
2845 /* When we are not as concerned about non-finite values, and we
2846 are comparing against zero, we can branch directly. */
2847 if (op1
== CONST0_RTX (DFmode
))
2848 cmp_code
= NIL
, branch_code
= code
;
2849 else if (op0
== CONST0_RTX (DFmode
))
2851 /* Undo the swap we probably did just above. */
2852 tem
= op0
, op0
= op1
, op1
= tem
;
2853 branch_code
= swap_condition (cmp_code
);
2859 /* ??? We mark the the branch mode to be CCmode to prevent the
2860 compare and branch from being combined, since the compare
2861 insn follows IEEE rules that the branch does not. */
2862 branch_mode
= CCmode
;
2869 /* The following optimizations are only for signed compares. */
2870 if (code
!= LEU
&& code
!= LTU
&& code
!= GEU
&& code
!= GTU
)
2872 /* Whee. Compare and branch against 0 directly. */
2873 if (op1
== const0_rtx
)
2874 cmp_code
= NIL
, branch_code
= code
;
2876 /* We want to use cmpcc/bcc when we can, since there is a zero delay
2877 bypass between logicals and br/cmov on EV5. But we don't want to
2878 force valid immediate constants into registers needlessly. */
2879 else if (GET_CODE (op1
) == CONST_INT
)
2881 HOST_WIDE_INT v
= INTVAL (op1
), n
= -v
;
2883 if (! CONST_OK_FOR_LETTER_P (v
, 'I')
2884 && (CONST_OK_FOR_LETTER_P (n
, 'K')
2885 || CONST_OK_FOR_LETTER_P (n
, 'L')))
2887 cmp_code
= PLUS
, branch_code
= code
;
2893 if (!reg_or_0_operand (op0
, DImode
))
2894 op0
= force_reg (DImode
, op0
);
2895 if (cmp_code
!= PLUS
&& !reg_or_8bit_operand (op1
, DImode
))
2896 op1
= force_reg (DImode
, op1
);
2899 /* Emit an initial compare instruction, if necessary. */
2901 if (cmp_code
!= NIL
)
2903 tem
= gen_reg_rtx (cmp_mode
);
2904 emit_move_insn (tem
, gen_rtx_fmt_ee (cmp_code
, cmp_mode
, op0
, op1
));
2907 /* Zero the operands. */
2908 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2910 /* Return the branch comparison. */
2911 return gen_rtx_fmt_ee (branch_code
, branch_mode
, tem
, CONST0_RTX (cmp_mode
));
2914 /* Certain simplifications can be done to make invalid setcc operations
2915 valid. Return the final comparison, or NULL if we can't work. */
2918 alpha_emit_setcc (code
)
2921 enum rtx_code cmp_code
;
2922 rtx op0
= alpha_compare
.op0
, op1
= alpha_compare
.op1
;
2923 int fp_p
= alpha_compare
.fp_p
;
2926 /* Zero the operands. */
2927 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
2929 if (fp_p
&& GET_MODE (op0
) == TFmode
)
2931 if (! TARGET_HAS_XFLOATING_LIBS
)
2934 /* X_floating library comparison functions return
2938 Convert the compare against the raw return value. */
2940 if (code
== UNORDERED
|| code
== ORDERED
)
2945 op0
= alpha_emit_xfloating_compare (cmp_code
, op0
, op1
);
2949 if (code
== UNORDERED
)
2951 else if (code
== ORDERED
)
2957 if (fp_p
&& !TARGET_FIX
)
2960 /* The general case: fold the comparison code to the types of compares
2961 that we have, choosing the branch as necessary. */
2966 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
2968 /* We have these compares. */
2970 cmp_code
= code
, code
= NE
;
2974 if (!fp_p
&& op1
== const0_rtx
)
2979 cmp_code
= reverse_condition (code
);
2983 case GE
: case GT
: case GEU
: case GTU
:
2984 /* These normally need swapping, but for integer zero we have
2985 special patterns that recognize swapped operands. */
2986 if (!fp_p
&& op1
== const0_rtx
)
2988 code
= swap_condition (code
);
2990 cmp_code
= code
, code
= NE
;
2991 tmp
= op0
, op0
= op1
, op1
= tmp
;
3000 if (!register_operand (op0
, DImode
))
3001 op0
= force_reg (DImode
, op0
);
3002 if (!reg_or_8bit_operand (op1
, DImode
))
3003 op1
= force_reg (DImode
, op1
);
3006 /* Emit an initial compare instruction, if necessary. */
3007 if (cmp_code
!= NIL
)
3009 enum machine_mode mode
= fp_p
? DFmode
: DImode
;
3011 tmp
= gen_reg_rtx (mode
);
3012 emit_insn (gen_rtx_SET (VOIDmode
, tmp
,
3013 gen_rtx_fmt_ee (cmp_code
, mode
, op0
, op1
)));
3015 op0
= fp_p
? gen_lowpart (DImode
, tmp
) : tmp
;
3019 /* Return the setcc comparison. */
3020 return gen_rtx_fmt_ee (code
, DImode
, op0
, op1
);
3024 /* Rewrite a comparison against zero CMP of the form
3025 (CODE (cc0) (const_int 0)) so it can be written validly in
3026 a conditional move (if_then_else CMP ...).
3027 If both of the operands that set cc0 are non-zero we must emit
3028 an insn to perform the compare (it can't be done within
3029 the conditional move). */
3031 alpha_emit_conditional_move (cmp
, mode
)
3033 enum machine_mode mode
;
3035 enum rtx_code code
= GET_CODE (cmp
);
3036 enum rtx_code cmov_code
= NE
;
3037 rtx op0
= alpha_compare
.op0
;
3038 rtx op1
= alpha_compare
.op1
;
3039 int fp_p
= alpha_compare
.fp_p
;
3040 enum machine_mode cmp_mode
3041 = (GET_MODE (op0
) == VOIDmode
? DImode
: GET_MODE (op0
));
3042 enum machine_mode cmp_op_mode
= fp_p
? DFmode
: DImode
;
3043 enum machine_mode cmov_mode
= VOIDmode
;
3044 int local_fast_math
= flag_unsafe_math_optimizations
;
3047 /* Zero the operands. */
3048 memset (&alpha_compare
, 0, sizeof (alpha_compare
));
3050 if (fp_p
!= FLOAT_MODE_P (mode
))
3052 enum rtx_code cmp_code
;
3057 /* If we have fp<->int register move instructions, do a cmov by
3058 performing the comparison in fp registers, and move the
3059 zero/non-zero value to integer registers, where we can then
3060 use a normal cmov, or vice-versa. */
3064 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3065 /* We have these compares. */
3066 cmp_code
= code
, code
= NE
;
3070 /* This must be reversed. */
3071 cmp_code
= EQ
, code
= EQ
;
3074 case GE
: case GT
: case GEU
: case GTU
:
3075 /* These normally need swapping, but for integer zero we have
3076 special patterns that recognize swapped operands. */
3077 if (!fp_p
&& op1
== const0_rtx
)
3078 cmp_code
= code
, code
= NE
;
3081 cmp_code
= swap_condition (code
);
3083 tem
= op0
, op0
= op1
, op1
= tem
;
3091 tem
= gen_reg_rtx (cmp_op_mode
);
3092 emit_insn (gen_rtx_SET (VOIDmode
, tem
,
3093 gen_rtx_fmt_ee (cmp_code
, cmp_op_mode
,
3096 cmp_mode
= cmp_op_mode
= fp_p
? DImode
: DFmode
;
3097 op0
= gen_lowpart (cmp_op_mode
, tem
);
3098 op1
= CONST0_RTX (cmp_op_mode
);
3100 local_fast_math
= 1;
3103 /* We may be able to use a conditional move directly.
3104 This avoids emitting spurious compares. */
3105 if (signed_comparison_operator (cmp
, VOIDmode
)
3106 && (!fp_p
|| local_fast_math
)
3107 && (op0
== CONST0_RTX (cmp_mode
) || op1
== CONST0_RTX (cmp_mode
)))
3108 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3110 /* We can't put the comparison inside the conditional move;
3111 emit a compare instruction and put that inside the
3112 conditional move. Make sure we emit only comparisons we have;
3113 swap or reverse as necessary. */
3120 case EQ
: case LE
: case LT
: case LEU
: case LTU
:
3121 /* We have these compares: */
3125 /* This must be reversed. */
3126 code
= reverse_condition (code
);
3130 case GE
: case GT
: case GEU
: case GTU
:
3131 /* These must be swapped. */
3132 if (op1
!= CONST0_RTX (cmp_mode
))
3134 code
= swap_condition (code
);
3135 tem
= op0
, op0
= op1
, op1
= tem
;
3145 if (!reg_or_0_operand (op0
, DImode
))
3146 op0
= force_reg (DImode
, op0
);
3147 if (!reg_or_8bit_operand (op1
, DImode
))
3148 op1
= force_reg (DImode
, op1
);
3151 /* ??? We mark the branch mode to be CCmode to prevent the compare
3152 and cmov from being combined, since the compare insn follows IEEE
3153 rules that the cmov does not. */
3154 if (fp_p
&& !local_fast_math
)
3157 tem
= gen_reg_rtx (cmp_op_mode
);
3158 emit_move_insn (tem
, gen_rtx_fmt_ee (code
, cmp_op_mode
, op0
, op1
));
3159 return gen_rtx_fmt_ee (cmov_code
, cmov_mode
, tem
, CONST0_RTX (cmp_op_mode
));
3162 /* Simplify a conditional move of two constants into a setcc with
3163 arithmetic. This is done with a splitter since combine would
3164 just undo the work if done during code generation. It also catches
3165 cases we wouldn't have before cse. */
3168 alpha_split_conditional_move (code
, dest
, cond
, t_rtx
, f_rtx
)
3170 rtx dest
, cond
, t_rtx
, f_rtx
;
3172 HOST_WIDE_INT t
, f
, diff
;
3173 enum machine_mode mode
;
3174 rtx target
, subtarget
, tmp
;
3176 mode
= GET_MODE (dest
);
3181 if (((code
== NE
|| code
== EQ
) && diff
< 0)
3182 || (code
== GE
|| code
== GT
))
3184 code
= reverse_condition (code
);
3185 diff
= t
, t
= f
, f
= diff
;
3189 subtarget
= target
= dest
;
3192 target
= gen_lowpart (DImode
, dest
);
3193 if (! no_new_pseudos
)
3194 subtarget
= gen_reg_rtx (DImode
);
3198 /* Below, we must be careful to use copy_rtx on target and subtarget
3199 in intermediate insns, as they may be a subreg rtx, which may not
3202 if (f
== 0 && exact_log2 (diff
) > 0
3203 /* On EV6, we've got enough shifters to make non-arithmatic shifts
3204 viable over a longer latency cmove. On EV5, the E0 slot is a
3205 scarce resource, and on EV4 shift has the same latency as a cmove. */
3206 && (diff
<= 8 || alpha_cpu
== PROCESSOR_EV6
))
3208 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3209 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3211 tmp
= gen_rtx_ASHIFT (DImode
, copy_rtx (subtarget
),
3212 GEN_INT (exact_log2 (t
)));
3213 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3215 else if (f
== 0 && t
== -1)
3217 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3218 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3220 emit_insn (gen_negdi2 (target
, copy_rtx (subtarget
)));
3222 else if (diff
== 1 || diff
== 4 || diff
== 8)
3226 tmp
= gen_rtx_fmt_ee (code
, DImode
, cond
, const0_rtx
);
3227 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (subtarget
), tmp
));
3230 emit_insn (gen_adddi3 (target
, copy_rtx (subtarget
), GEN_INT (f
)));
3233 add_op
= GEN_INT (f
);
3234 if (sext_add_operand (add_op
, mode
))
3236 tmp
= gen_rtx_MULT (DImode
, copy_rtx (subtarget
),
3238 tmp
= gen_rtx_PLUS (DImode
, tmp
, add_op
);
3239 emit_insn (gen_rtx_SET (VOIDmode
, target
, tmp
));
3251 /* Look up the function X_floating library function name for the
3255 alpha_lookup_xfloating_lib_func (code
)
3260 const enum rtx_code code
;
3261 const char *const func
;
3264 static const struct xfloating_op vms_xfloating_ops
[] =
3266 { PLUS
, "OTS$ADD_X" },
3267 { MINUS
, "OTS$SUB_X" },
3268 { MULT
, "OTS$MUL_X" },
3269 { DIV
, "OTS$DIV_X" },
3270 { EQ
, "OTS$EQL_X" },
3271 { NE
, "OTS$NEQ_X" },
3272 { LT
, "OTS$LSS_X" },
3273 { LE
, "OTS$LEQ_X" },
3274 { GT
, "OTS$GTR_X" },
3275 { GE
, "OTS$GEQ_X" },
3276 { FIX
, "OTS$CVTXQ" },
3277 { FLOAT
, "OTS$CVTQX" },
3278 { UNSIGNED_FLOAT
, "OTS$CVTQUX" },
3279 { FLOAT_EXTEND
, "OTS$CVT_FLOAT_T_X" },
3280 { FLOAT_TRUNCATE
, "OTS$CVT_FLOAT_X_T" },
3283 static const struct xfloating_op osf_xfloating_ops
[] =
3285 { PLUS
, "_OtsAddX" },
3286 { MINUS
, "_OtsSubX" },
3287 { MULT
, "_OtsMulX" },
3288 { DIV
, "_OtsDivX" },
3295 { FIX
, "_OtsCvtXQ" },
3296 { FLOAT
, "_OtsCvtQX" },
3297 { UNSIGNED_FLOAT
, "_OtsCvtQUX" },
3298 { FLOAT_EXTEND
, "_OtsConvertFloatTX" },
3299 { FLOAT_TRUNCATE
, "_OtsConvertFloatXT" },
3302 const struct xfloating_op
*ops
;
3303 const long n
= ARRAY_SIZE (osf_xfloating_ops
);
3306 /* How irritating. Nothing to key off for the table. Hardcode
3307 knowledge of the G_floating routines. */
3308 if (TARGET_FLOAT_VAX
)
3310 if (TARGET_ABI_OPEN_VMS
)
3312 if (code
== FLOAT_EXTEND
)
3313 return "OTS$CVT_FLOAT_G_X";
3314 if (code
== FLOAT_TRUNCATE
)
3315 return "OTS$CVT_FLOAT_X_G";
3319 if (code
== FLOAT_EXTEND
)
3320 return "_OtsConvertFloatGX";
3321 if (code
== FLOAT_TRUNCATE
)
3322 return "_OtsConvertFloatXG";
3326 if (TARGET_ABI_OPEN_VMS
)
3327 ops
= vms_xfloating_ops
;
3329 ops
= osf_xfloating_ops
;
3331 for (i
= 0; i
< n
; ++i
)
3332 if (ops
[i
].code
== code
)
3338 /* Most X_floating operations take the rounding mode as an argument.
3339 Compute that here. */
3342 alpha_compute_xfloating_mode_arg (code
, round
)
3344 enum alpha_fp_rounding_mode round
;
3350 case ALPHA_FPRM_NORM
:
3353 case ALPHA_FPRM_MINF
:
3356 case ALPHA_FPRM_CHOP
:
3359 case ALPHA_FPRM_DYN
:
3365 /* XXX For reference, round to +inf is mode = 3. */
3368 if (code
== FLOAT_TRUNCATE
&& alpha_fptm
== ALPHA_FPTM_N
)
3374 /* Emit an X_floating library function call.
3376 Note that these functions do not follow normal calling conventions:
3377 TFmode arguments are passed in two integer registers (as opposed to
3378 indirect); TFmode return values appear in R16+R17.
3380 FUNC is the function name to call.
3381 TARGET is where the output belongs.
3382 OPERANDS are the inputs.
3383 NOPERANDS is the count of inputs.
3384 EQUIV is the expression equivalent for the function.
3388 alpha_emit_xfloating_libcall (func
, target
, operands
, noperands
, equiv
)
3395 rtx usage
= NULL_RTX
, tmp
, reg
;
3400 for (i
= 0; i
< noperands
; ++i
)
3402 switch (GET_MODE (operands
[i
]))
3405 reg
= gen_rtx_REG (TFmode
, regno
);
3410 reg
= gen_rtx_REG (DFmode
, regno
+ 32);
3415 if (GET_CODE (operands
[i
]) != CONST_INT
)
3419 reg
= gen_rtx_REG (DImode
, regno
);
3427 emit_move_insn (reg
, operands
[i
]);
3428 usage
= alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode
, reg
), usage
);
3431 switch (GET_MODE (target
))
3434 reg
= gen_rtx_REG (TFmode
, 16);
3437 reg
= gen_rtx_REG (DFmode
, 32);
3440 reg
= gen_rtx_REG (DImode
, 0);
3446 tmp
= gen_rtx_MEM (QImode
, gen_rtx_SYMBOL_REF (Pmode
, (char *) func
));
3447 tmp
= emit_call_insn (GEN_CALL_VALUE (reg
, tmp
, const0_rtx
,
3448 const0_rtx
, const0_rtx
));
3449 CALL_INSN_FUNCTION_USAGE (tmp
) = usage
;
3454 emit_libcall_block (tmp
, target
, reg
, equiv
);
3457 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3460 alpha_emit_xfloating_arith (code
, operands
)
3466 rtx out_operands
[3];
3468 func
= alpha_lookup_xfloating_lib_func (code
);
3469 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3471 out_operands
[0] = operands
[1];
3472 out_operands
[1] = operands
[2];
3473 out_operands
[2] = GEN_INT (mode
);
3474 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, 3,
3475 gen_rtx_fmt_ee (code
, TFmode
, operands
[1],
3479 /* Emit an X_floating library function call for a comparison. */
3482 alpha_emit_xfloating_compare (code
, op0
, op1
)
3487 rtx out
, operands
[2];
3489 func
= alpha_lookup_xfloating_lib_func (code
);
3493 out
= gen_reg_rtx (DImode
);
3495 /* ??? Strange mode for equiv because what's actually returned
3496 is -1,0,1, not a proper boolean value. */
3497 alpha_emit_xfloating_libcall (func
, out
, operands
, 2,
3498 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
));
3503 /* Emit an X_floating library function call for a conversion. */
3506 alpha_emit_xfloating_cvt (code
, operands
)
3510 int noperands
= 1, mode
;
3511 rtx out_operands
[2];
3514 func
= alpha_lookup_xfloating_lib_func (code
);
3516 out_operands
[0] = operands
[1];
3521 mode
= alpha_compute_xfloating_mode_arg (code
, ALPHA_FPRM_CHOP
);
3522 out_operands
[1] = GEN_INT (mode
);
3525 case FLOAT_TRUNCATE
:
3526 mode
= alpha_compute_xfloating_mode_arg (code
, alpha_fprm
);
3527 out_operands
[1] = GEN_INT (mode
);
3534 alpha_emit_xfloating_libcall (func
, operands
[0], out_operands
, noperands
,
3535 gen_rtx_fmt_e (code
, GET_MODE (operands
[0]),
3539 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3540 OP[0] into OP[0,1]. Naturally, output operand ordering is
3544 alpha_split_tfmode_pair (operands
)
3547 if (GET_CODE (operands
[1]) == REG
)
3549 operands
[3] = gen_rtx_REG (DImode
, REGNO (operands
[1]) + 1);
3550 operands
[2] = gen_rtx_REG (DImode
, REGNO (operands
[1]));
3552 else if (GET_CODE (operands
[1]) == MEM
)
3554 operands
[3] = adjust_address (operands
[1], DImode
, 8);
3555 operands
[2] = adjust_address (operands
[1], DImode
, 0);
3557 else if (operands
[1] == CONST0_RTX (TFmode
))
3558 operands
[2] = operands
[3] = const0_rtx
;
3562 if (GET_CODE (operands
[0]) == REG
)
3564 operands
[1] = gen_rtx_REG (DImode
, REGNO (operands
[0]) + 1);
3565 operands
[0] = gen_rtx_REG (DImode
, REGNO (operands
[0]));
3567 else if (GET_CODE (operands
[0]) == MEM
)
3569 operands
[1] = adjust_address (operands
[0], DImode
, 8);
3570 operands
[0] = adjust_address (operands
[0], DImode
, 0);
3576 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3577 op2 is a register containing the sign bit, operation is the
3578 logical operation to be performed. */
3581 alpha_split_tfmode_frobsign (operands
, operation
)
3583 rtx (*operation
) PARAMS ((rtx
, rtx
, rtx
));
3585 rtx high_bit
= operands
[2];
3589 alpha_split_tfmode_pair (operands
);
3591 /* Detect three flavours of operand overlap. */
3593 if (rtx_equal_p (operands
[0], operands
[2]))
3595 else if (rtx_equal_p (operands
[1], operands
[2]))
3597 if (rtx_equal_p (operands
[0], high_bit
))
3604 emit_move_insn (operands
[0], operands
[2]);
3606 /* ??? If the destination overlaps both source tf and high_bit, then
3607 assume source tf is dead in its entirety and use the other half
3608 for a scratch register. Otherwise "scratch" is just the proper
3609 destination register. */
3610 scratch
= operands
[move
< 2 ? 1 : 3];
3612 emit_insn ((*operation
) (scratch
, high_bit
, operands
[3]));
3616 emit_move_insn (operands
[0], operands
[2]);
3618 emit_move_insn (operands
[1], scratch
);
3622 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3626 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3627 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3628 lda r3,X(r11) lda r3,X+2(r11)
3629 extwl r1,r3,r1 extql r1,r3,r1
3630 extwh r2,r3,r2 extqh r2,r3,r2
3631 or r1.r2.r1 or r1,r2,r1
3634 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3635 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3636 lda r3,X(r11) lda r3,X(r11)
3637 extll r1,r3,r1 extll r1,r3,r1
3638 extlh r2,r3,r2 extlh r2,r3,r2
3639 or r1.r2.r1 addl r1,r2,r1
3641 quad: ldq_u r1,X(r11)
3650 alpha_expand_unaligned_load (tgt
, mem
, size
, ofs
, sign
)
3652 HOST_WIDE_INT size
, ofs
;
3655 rtx meml
, memh
, addr
, extl
, exth
, tmp
, mema
;
3656 enum machine_mode mode
;
3658 meml
= gen_reg_rtx (DImode
);
3659 memh
= gen_reg_rtx (DImode
);
3660 addr
= gen_reg_rtx (DImode
);
3661 extl
= gen_reg_rtx (DImode
);
3662 exth
= gen_reg_rtx (DImode
);
3664 mema
= XEXP (mem
, 0);
3665 if (GET_CODE (mema
) == LO_SUM
)
3666 mema
= force_reg (Pmode
, mema
);
3668 /* AND addresses cannot be in any alias set, since they may implicitly
3669 alias surrounding code. Ideally we'd have some alias set that
3670 covered all types except those with alignment 8 or higher. */
3672 tmp
= change_address (mem
, DImode
,
3673 gen_rtx_AND (DImode
,
3674 plus_constant (mema
, ofs
),
3676 set_mem_alias_set (tmp
, 0);
3677 emit_move_insn (meml
, tmp
);
3679 tmp
= change_address (mem
, DImode
,
3680 gen_rtx_AND (DImode
,
3681 plus_constant (mema
, ofs
+ size
- 1),
3683 set_mem_alias_set (tmp
, 0);
3684 emit_move_insn (memh
, tmp
);
3686 if (WORDS_BIG_ENDIAN
&& sign
&& (size
== 2 || size
== 4))
3688 emit_move_insn (addr
, plus_constant (mema
, -1));
3690 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3691 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (64), addr
));
3693 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3694 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (64 - size
*8),
3695 addr
, 1, OPTAB_WIDEN
);
3697 else if (sign
&& size
== 2)
3699 emit_move_insn (addr
, plus_constant (mema
, ofs
+2));
3701 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (64), addr
));
3702 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3704 /* We must use tgt here for the target. Alpha-vms port fails if we use
3705 addr for the target, because addr is marked as a pointer and combine
3706 knows that pointers are always sign-extended 32 bit values. */
3707 addr
= expand_binop (DImode
, ior_optab
, extl
, exth
, tgt
, 1, OPTAB_WIDEN
);
3708 addr
= expand_binop (DImode
, ashr_optab
, addr
, GEN_INT (48),
3709 addr
, 1, OPTAB_WIDEN
);
3713 if (WORDS_BIG_ENDIAN
)
3715 emit_move_insn (addr
, plus_constant (mema
, ofs
+size
-1));
3719 emit_insn (gen_extwh_be (extl
, meml
, addr
));
3724 emit_insn (gen_extlh_be (extl
, meml
, addr
));
3729 emit_insn (gen_extqh_be (extl
, meml
, addr
));
3736 emit_insn (gen_extxl_be (exth
, memh
, GEN_INT (size
*8), addr
));
3740 emit_move_insn (addr
, plus_constant (mema
, ofs
));
3741 emit_insn (gen_extxl_le (extl
, meml
, GEN_INT (size
*8), addr
));
3745 emit_insn (gen_extwh_le (exth
, memh
, addr
));
3750 emit_insn (gen_extlh_le (exth
, memh
, addr
));
3755 emit_insn (gen_extqh_le (exth
, memh
, addr
));
3764 addr
= expand_binop (mode
, ior_optab
, gen_lowpart (mode
, extl
),
3765 gen_lowpart (mode
, exth
), gen_lowpart (mode
, tgt
),
3770 emit_move_insn (tgt
, gen_lowpart(GET_MODE (tgt
), addr
));
3773 /* Similarly, use ins and msk instructions to perform unaligned stores. */
3776 alpha_expand_unaligned_store (dst
, src
, size
, ofs
)
3778 HOST_WIDE_INT size
, ofs
;
3780 rtx dstl
, dsth
, addr
, insl
, insh
, meml
, memh
, dsta
;
3782 dstl
= gen_reg_rtx (DImode
);
3783 dsth
= gen_reg_rtx (DImode
);
3784 insl
= gen_reg_rtx (DImode
);
3785 insh
= gen_reg_rtx (DImode
);
3787 dsta
= XEXP (dst
, 0);
3788 if (GET_CODE (dsta
) == LO_SUM
)
3789 dsta
= force_reg (Pmode
, dsta
);
3791 /* AND addresses cannot be in any alias set, since they may implicitly
3792 alias surrounding code. Ideally we'd have some alias set that
3793 covered all types except those with alignment 8 or higher. */
3795 meml
= change_address (dst
, DImode
,
3796 gen_rtx_AND (DImode
,
3797 plus_constant (dsta
, ofs
),
3799 set_mem_alias_set (meml
, 0);
3801 memh
= change_address (dst
, DImode
,
3802 gen_rtx_AND (DImode
,
3803 plus_constant (dsta
, ofs
+ size
- 1),
3805 set_mem_alias_set (memh
, 0);
3807 emit_move_insn (dsth
, memh
);
3808 emit_move_insn (dstl
, meml
);
3809 if (WORDS_BIG_ENDIAN
)
3811 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
+size
-1));
3813 if (src
!= const0_rtx
)
3818 emit_insn (gen_inswl_be (insh
, gen_lowpart (HImode
,src
), addr
));
3821 emit_insn (gen_insll_be (insh
, gen_lowpart (SImode
,src
), addr
));
3824 emit_insn (gen_insql_be (insh
, gen_lowpart (DImode
,src
), addr
));
3827 emit_insn (gen_insxh (insl
, gen_lowpart (DImode
, src
),
3828 GEN_INT (size
*8), addr
));
3834 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffff), addr
));
3837 emit_insn (gen_mskxl_be (dsth
, dsth
, GEN_INT (0xffffffff), addr
));
3841 #if HOST_BITS_PER_WIDE_INT == 32
3842 rtx msk
= immed_double_const (0xffffffff, 0xffffffff, DImode
);
3844 rtx msk
= constm1_rtx
;
3846 emit_insn (gen_mskxl_be (dsth
, dsth
, msk
, addr
));
3851 emit_insn (gen_mskxh (dstl
, dstl
, GEN_INT (size
*8), addr
));
3855 addr
= copy_addr_to_reg (plus_constant (dsta
, ofs
));
3857 if (src
!= const0_rtx
)
3859 emit_insn (gen_insxh (insh
, gen_lowpart (DImode
, src
),
3860 GEN_INT (size
*8), addr
));
3865 emit_insn (gen_inswl_le (insl
, gen_lowpart (HImode
, src
), addr
));
3868 emit_insn (gen_insll_le (insl
, gen_lowpart (SImode
, src
), addr
));
3871 emit_insn (gen_insql_le (insl
, src
, addr
));
3876 emit_insn (gen_mskxh (dsth
, dsth
, GEN_INT (size
*8), addr
));
3881 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffff), addr
));
3884 emit_insn (gen_mskxl_le (dstl
, dstl
, GEN_INT (0xffffffff), addr
));
3888 #if HOST_BITS_PER_WIDE_INT == 32
3889 rtx msk
= immed_double_const (0xffffffff, 0xffffffff, DImode
);
3891 rtx msk
= constm1_rtx
;
3893 emit_insn (gen_mskxl_le (dstl
, dstl
, msk
, addr
));
3899 if (src
!= const0_rtx
)
3901 dsth
= expand_binop (DImode
, ior_optab
, insh
, dsth
, dsth
, 0, OPTAB_WIDEN
);
3902 dstl
= expand_binop (DImode
, ior_optab
, insl
, dstl
, dstl
, 0, OPTAB_WIDEN
);
3905 if (WORDS_BIG_ENDIAN
)
3907 emit_move_insn (meml
, dstl
);
3908 emit_move_insn (memh
, dsth
);
3912 /* Must store high before low for degenerate case of aligned. */
3913 emit_move_insn (memh
, dsth
);
3914 emit_move_insn (meml
, dstl
);
3918 /* The block move code tries to maximize speed by separating loads and
3919 stores at the expense of register pressure: we load all of the data
3920 before we store it back out. There are two secondary effects worth
3921 mentioning, that this speeds copying to/from aligned and unaligned
3922 buffers, and that it makes the code significantly easier to write. */
3924 #define MAX_MOVE_WORDS 8
3926 /* Load an integral number of consecutive unaligned quadwords. */
3929 alpha_expand_unaligned_load_words (out_regs
, smem
, words
, ofs
)
3932 HOST_WIDE_INT words
, ofs
;
3934 rtx
const im8
= GEN_INT (-8);
3935 rtx
const i64
= GEN_INT (64);
3936 rtx ext_tmps
[MAX_MOVE_WORDS
], data_regs
[MAX_MOVE_WORDS
+1];
3937 rtx sreg
, areg
, tmp
, smema
;
3940 smema
= XEXP (smem
, 0);
3941 if (GET_CODE (smema
) == LO_SUM
)
3942 smema
= force_reg (Pmode
, smema
);
3944 /* Generate all the tmp registers we need. */
3945 for (i
= 0; i
< words
; ++i
)
3947 data_regs
[i
] = out_regs
[i
];
3948 ext_tmps
[i
] = gen_reg_rtx (DImode
);
3950 data_regs
[words
] = gen_reg_rtx (DImode
);
3953 smem
= adjust_address (smem
, GET_MODE (smem
), ofs
);
3955 /* Load up all of the source data. */
3956 for (i
= 0; i
< words
; ++i
)
3958 tmp
= change_address (smem
, DImode
,
3959 gen_rtx_AND (DImode
,
3960 plus_constant (smema
, 8*i
),
3962 set_mem_alias_set (tmp
, 0);
3963 emit_move_insn (data_regs
[i
], tmp
);
3966 tmp
= change_address (smem
, DImode
,
3967 gen_rtx_AND (DImode
,
3968 plus_constant (smema
, 8*words
- 1),
3970 set_mem_alias_set (tmp
, 0);
3971 emit_move_insn (data_regs
[words
], tmp
);
3973 /* Extract the half-word fragments. Unfortunately DEC decided to make
3974 extxh with offset zero a noop instead of zeroing the register, so
3975 we must take care of that edge condition ourselves with cmov. */
3977 sreg
= copy_addr_to_reg (smema
);
3978 areg
= expand_binop (DImode
, and_optab
, sreg
, GEN_INT (7), NULL
,
3980 if (WORDS_BIG_ENDIAN
)
3981 emit_move_insn (sreg
, plus_constant (sreg
, 7));
3982 for (i
= 0; i
< words
; ++i
)
3984 if (WORDS_BIG_ENDIAN
)
3986 emit_insn (gen_extqh_be (data_regs
[i
], data_regs
[i
], sreg
));
3987 emit_insn (gen_extxl_be (ext_tmps
[i
], data_regs
[i
+1], i64
, sreg
));
3991 emit_insn (gen_extxl_le (data_regs
[i
], data_regs
[i
], i64
, sreg
));
3992 emit_insn (gen_extqh_le (ext_tmps
[i
], data_regs
[i
+1], sreg
));
3994 emit_insn (gen_rtx_SET (VOIDmode
, ext_tmps
[i
],
3995 gen_rtx_IF_THEN_ELSE (DImode
,
3996 gen_rtx_EQ (DImode
, areg
,
3998 const0_rtx
, ext_tmps
[i
])));
4001 /* Merge the half-words into whole words. */
4002 for (i
= 0; i
< words
; ++i
)
4004 out_regs
[i
] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4005 ext_tmps
[i
], data_regs
[i
], 1, OPTAB_WIDEN
);
4009 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4010 may be NULL to store zeros. */
4013 alpha_expand_unaligned_store_words (data_regs
, dmem
, words
, ofs
)
4016 HOST_WIDE_INT words
, ofs
;
4018 rtx
const im8
= GEN_INT (-8);
4019 rtx
const i64
= GEN_INT (64);
4020 #if HOST_BITS_PER_WIDE_INT == 32
4021 rtx
const im1
= immed_double_const (0xffffffff, 0xffffffff, DImode
);
4023 rtx
const im1
= constm1_rtx
;
4025 rtx ins_tmps
[MAX_MOVE_WORDS
];
4026 rtx st_tmp_1
, st_tmp_2
, dreg
;
4027 rtx st_addr_1
, st_addr_2
, dmema
;
4030 dmema
= XEXP (dmem
, 0);
4031 if (GET_CODE (dmema
) == LO_SUM
)
4032 dmema
= force_reg (Pmode
, dmema
);
4034 /* Generate all the tmp registers we need. */
4035 if (data_regs
!= NULL
)
4036 for (i
= 0; i
< words
; ++i
)
4037 ins_tmps
[i
] = gen_reg_rtx(DImode
);
4038 st_tmp_1
= gen_reg_rtx(DImode
);
4039 st_tmp_2
= gen_reg_rtx(DImode
);
4042 dmem
= adjust_address (dmem
, GET_MODE (dmem
), ofs
);
4044 st_addr_2
= change_address (dmem
, DImode
,
4045 gen_rtx_AND (DImode
,
4046 plus_constant (dmema
, words
*8 - 1),
4048 set_mem_alias_set (st_addr_2
, 0);
4050 st_addr_1
= change_address (dmem
, DImode
,
4051 gen_rtx_AND (DImode
, dmema
, im8
));
4052 set_mem_alias_set (st_addr_1
, 0);
4054 /* Load up the destination end bits. */
4055 emit_move_insn (st_tmp_2
, st_addr_2
);
4056 emit_move_insn (st_tmp_1
, st_addr_1
);
4058 /* Shift the input data into place. */
4059 dreg
= copy_addr_to_reg (dmema
);
4060 if (WORDS_BIG_ENDIAN
)
4061 emit_move_insn (dreg
, plus_constant (dreg
, 7));
4062 if (data_regs
!= NULL
)
4064 for (i
= words
-1; i
>= 0; --i
)
4066 if (WORDS_BIG_ENDIAN
)
4068 emit_insn (gen_insql_be (ins_tmps
[i
], data_regs
[i
], dreg
));
4069 emit_insn (gen_insxh (data_regs
[i
], data_regs
[i
], i64
, dreg
));
4073 emit_insn (gen_insxh (ins_tmps
[i
], data_regs
[i
], i64
, dreg
));
4074 emit_insn (gen_insql_le (data_regs
[i
], data_regs
[i
], dreg
));
4077 for (i
= words
-1; i
> 0; --i
)
4079 ins_tmps
[i
-1] = expand_binop (DImode
, ior_optab
, data_regs
[i
],
4080 ins_tmps
[i
-1], ins_tmps
[i
-1], 1,
4085 /* Split and merge the ends with the destination data. */
4086 if (WORDS_BIG_ENDIAN
)
4088 emit_insn (gen_mskxl_be (st_tmp_2
, st_tmp_2
, im1
, dreg
));
4089 emit_insn (gen_mskxh (st_tmp_1
, st_tmp_1
, i64
, dreg
));
4093 emit_insn (gen_mskxh (st_tmp_2
, st_tmp_2
, i64
, dreg
));
4094 emit_insn (gen_mskxl_le (st_tmp_1
, st_tmp_1
, im1
, dreg
));
4097 if (data_regs
!= NULL
)
4099 st_tmp_2
= expand_binop (DImode
, ior_optab
, st_tmp_2
, ins_tmps
[words
-1],
4100 st_tmp_2
, 1, OPTAB_WIDEN
);
4101 st_tmp_1
= expand_binop (DImode
, ior_optab
, st_tmp_1
, data_regs
[0],
4102 st_tmp_1
, 1, OPTAB_WIDEN
);
4106 if (WORDS_BIG_ENDIAN
)
4107 emit_move_insn (st_addr_1
, st_tmp_1
);
4109 emit_move_insn (st_addr_2
, st_tmp_2
);
4110 for (i
= words
-1; i
> 0; --i
)
4112 rtx tmp
= change_address (dmem
, DImode
,
4113 gen_rtx_AND (DImode
,
4114 plus_constant(dmema
,
4115 WORDS_BIG_ENDIAN
? i
*8-1 : i
*8),
4117 set_mem_alias_set (tmp
, 0);
4118 emit_move_insn (tmp
, data_regs
? ins_tmps
[i
-1] : const0_rtx
);
4120 if (WORDS_BIG_ENDIAN
)
4121 emit_move_insn (st_addr_2
, st_tmp_2
);
4123 emit_move_insn (st_addr_1
, st_tmp_1
);
4127 /* Expand string/block move operations.
4129 operands[0] is the pointer to the destination.
4130 operands[1] is the pointer to the source.
4131 operands[2] is the number of bytes to move.
4132 operands[3] is the alignment. */
4135 alpha_expand_block_move (operands
)
4138 rtx bytes_rtx
= operands
[2];
4139 rtx align_rtx
= operands
[3];
4140 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4141 HOST_WIDE_INT bytes
= orig_bytes
;
4142 HOST_WIDE_INT src_align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4143 HOST_WIDE_INT dst_align
= src_align
;
4144 rtx orig_src
= operands
[1];
4145 rtx orig_dst
= operands
[0];
4146 rtx data_regs
[2 * MAX_MOVE_WORDS
+ 16];
4148 unsigned int i
, words
, ofs
, nregs
= 0;
4150 if (orig_bytes
<= 0)
4152 else if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4155 /* Look for additional alignment information from recorded register info. */
4157 tmp
= XEXP (orig_src
, 0);
4158 if (GET_CODE (tmp
) == REG
)
4159 src_align
= MAX (src_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4160 else if (GET_CODE (tmp
) == PLUS
4161 && GET_CODE (XEXP (tmp
, 0)) == REG
4162 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4164 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4165 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4169 if (a
>= 64 && c
% 8 == 0)
4171 else if (a
>= 32 && c
% 4 == 0)
4173 else if (a
>= 16 && c
% 2 == 0)
4178 tmp
= XEXP (orig_dst
, 0);
4179 if (GET_CODE (tmp
) == REG
)
4180 dst_align
= MAX (dst_align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4181 else if (GET_CODE (tmp
) == PLUS
4182 && GET_CODE (XEXP (tmp
, 0)) == REG
4183 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4185 unsigned HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4186 unsigned int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4190 if (a
>= 64 && c
% 8 == 0)
4192 else if (a
>= 32 && c
% 4 == 0)
4194 else if (a
>= 16 && c
% 2 == 0)
4199 /* Load the entire block into registers. */
4200 if (GET_CODE (XEXP (orig_src
, 0)) == ADDRESSOF
)
4202 enum machine_mode mode
;
4204 tmp
= XEXP (XEXP (orig_src
, 0), 0);
4206 /* Don't use the existing register if we're reading more than
4207 is held in the register. Nor if there is not a mode that
4208 handles the exact size. */
4209 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4211 && GET_MODE_SIZE (GET_MODE (tmp
)) >= bytes
)
4215 data_regs
[nregs
] = gen_lowpart (DImode
, tmp
);
4216 data_regs
[nregs
+ 1] = gen_highpart (DImode
, tmp
);
4220 data_regs
[nregs
++] = gen_lowpart (mode
, tmp
);
4225 /* No appropriate mode; fall back on memory. */
4226 orig_src
= replace_equiv_address (orig_src
,
4227 copy_addr_to_reg (XEXP (orig_src
, 0)));
4228 src_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4232 if (src_align
>= 64 && bytes
>= 8)
4236 for (i
= 0; i
< words
; ++i
)
4237 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4239 for (i
= 0; i
< words
; ++i
)
4240 emit_move_insn (data_regs
[nregs
+ i
],
4241 adjust_address (orig_src
, DImode
, ofs
+ i
* 8));
4248 if (src_align
>= 32 && bytes
>= 4)
4252 for (i
= 0; i
< words
; ++i
)
4253 data_regs
[nregs
+ i
] = gen_reg_rtx (SImode
);
4255 for (i
= 0; i
< words
; ++i
)
4256 emit_move_insn (data_regs
[nregs
+ i
],
4257 adjust_address (orig_src
, SImode
, ofs
+ i
* 4));
4268 for (i
= 0; i
< words
+1; ++i
)
4269 data_regs
[nregs
+ i
] = gen_reg_rtx (DImode
);
4271 alpha_expand_unaligned_load_words (data_regs
+ nregs
, orig_src
,
4279 if (! TARGET_BWX
&& bytes
>= 4)
4281 data_regs
[nregs
++] = tmp
= gen_reg_rtx (SImode
);
4282 alpha_expand_unaligned_load (tmp
, orig_src
, 4, ofs
, 0);
4289 if (src_align
>= 16)
4292 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4293 emit_move_insn (tmp
, adjust_address (orig_src
, HImode
, ofs
));
4296 } while (bytes
>= 2);
4298 else if (! TARGET_BWX
)
4300 data_regs
[nregs
++] = tmp
= gen_reg_rtx (HImode
);
4301 alpha_expand_unaligned_load (tmp
, orig_src
, 2, ofs
, 0);
4309 data_regs
[nregs
++] = tmp
= gen_reg_rtx (QImode
);
4310 emit_move_insn (tmp
, adjust_address (orig_src
, QImode
, ofs
));
4317 if (nregs
> ARRAY_SIZE (data_regs
))
4320 /* Now save it back out again. */
4324 if (GET_CODE (XEXP (orig_dst
, 0)) == ADDRESSOF
)
4326 enum machine_mode mode
;
4327 tmp
= XEXP (XEXP (orig_dst
, 0), 0);
4329 mode
= mode_for_size (orig_bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4330 if (GET_MODE (tmp
) == mode
)
4334 emit_move_insn (tmp
, data_regs
[0]);
4339 else if (nregs
== 2 && mode
== TImode
)
4341 /* Undo the subregging done above when copying between
4342 two TImode registers. */
4343 if (GET_CODE (data_regs
[0]) == SUBREG
4344 && GET_MODE (SUBREG_REG (data_regs
[0])) == TImode
)
4345 emit_move_insn (tmp
, SUBREG_REG (data_regs
[0]));
4351 emit_move_insn (gen_lowpart (DImode
, tmp
), data_regs
[0]);
4352 emit_move_insn (gen_highpart (DImode
, tmp
), data_regs
[1]);
4356 emit_no_conflict_block (seq
, tmp
, data_regs
[0],
4357 data_regs
[1], NULL_RTX
);
4365 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4366 /* ??? Optimize mode < dst_mode with strict_low_part. */
4368 /* No appropriate mode; fall back on memory. We can speed things
4369 up by recognizing extra alignment information. */
4370 orig_dst
= replace_equiv_address (orig_dst
,
4371 copy_addr_to_reg (XEXP (orig_dst
, 0)));
4372 dst_align
= GET_MODE_BITSIZE (GET_MODE (tmp
));
4375 /* Write out the data in whatever chunks reading the source allowed. */
4376 if (dst_align
>= 64)
4378 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4380 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
),
4387 if (dst_align
>= 32)
4389 /* If the source has remaining DImode regs, write them out in
4391 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4393 tmp
= expand_binop (DImode
, lshr_optab
, data_regs
[i
], GEN_INT (32),
4394 NULL_RTX
, 1, OPTAB_WIDEN
);
4396 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4397 gen_lowpart (SImode
, data_regs
[i
]));
4398 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ 4),
4399 gen_lowpart (SImode
, tmp
));
4404 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4406 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
),
4413 if (i
< nregs
&& GET_MODE (data_regs
[i
]) == DImode
)
4415 /* Write out a remaining block of words using unaligned methods. */
4417 for (words
= 1; i
+ words
< nregs
; words
++)
4418 if (GET_MODE (data_regs
[i
+ words
]) != DImode
)
4422 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 8, ofs
);
4424 alpha_expand_unaligned_store_words (data_regs
+ i
, orig_dst
,
4431 /* Due to the above, this won't be aligned. */
4432 /* ??? If we have more than one of these, consider constructing full
4433 words in registers and using alpha_expand_unaligned_store_words. */
4434 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == SImode
)
4436 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 4, ofs
);
4441 if (dst_align
>= 16)
4442 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4444 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), data_regs
[i
]);
4449 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == HImode
)
4451 alpha_expand_unaligned_store (orig_dst
, data_regs
[i
], 2, ofs
);
4456 while (i
< nregs
&& GET_MODE (data_regs
[i
]) == QImode
)
4458 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), data_regs
[i
]);
4472 alpha_expand_block_clear (operands
)
4475 rtx bytes_rtx
= operands
[1];
4476 rtx align_rtx
= operands
[2];
4477 HOST_WIDE_INT orig_bytes
= INTVAL (bytes_rtx
);
4478 HOST_WIDE_INT bytes
= orig_bytes
;
4479 HOST_WIDE_INT align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
4480 HOST_WIDE_INT alignofs
= 0;
4481 rtx orig_dst
= operands
[0];
4483 int i
, words
, ofs
= 0;
4485 if (orig_bytes
<= 0)
4487 if (orig_bytes
> MAX_MOVE_WORDS
* UNITS_PER_WORD
)
4490 /* Look for stricter alignment. */
4491 tmp
= XEXP (orig_dst
, 0);
4492 if (GET_CODE (tmp
) == REG
)
4493 align
= MAX (align
, REGNO_POINTER_ALIGN (REGNO (tmp
)));
4494 else if (GET_CODE (tmp
) == PLUS
4495 && GET_CODE (XEXP (tmp
, 0)) == REG
4496 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
4498 HOST_WIDE_INT c
= INTVAL (XEXP (tmp
, 1));
4499 int a
= REGNO_POINTER_ALIGN (REGNO (XEXP (tmp
, 0)));
4504 align
= a
, alignofs
= 8 - c
% 8;
4506 align
= a
, alignofs
= 4 - c
% 4;
4508 align
= a
, alignofs
= 2 - c
% 2;
4511 else if (GET_CODE (tmp
) == ADDRESSOF
)
4513 enum machine_mode mode
;
4515 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 1);
4516 if (GET_MODE (XEXP (tmp
, 0)) == mode
)
4518 emit_move_insn (XEXP (tmp
, 0), const0_rtx
);
4522 /* No appropriate mode; fall back on memory. */
4523 orig_dst
= replace_equiv_address (orig_dst
, copy_addr_to_reg (tmp
));
4524 align
= GET_MODE_BITSIZE (GET_MODE (XEXP (tmp
, 0)));
4527 /* Handle an unaligned prefix first. */
4531 #if HOST_BITS_PER_WIDE_INT >= 64
4532 /* Given that alignofs is bounded by align, the only time BWX could
4533 generate three stores is for a 7 byte fill. Prefer two individual
4534 stores over a load/mask/store sequence. */
4535 if ((!TARGET_BWX
|| alignofs
== 7)
4537 && !(alignofs
== 4 && bytes
>= 4))
4539 enum machine_mode mode
= (align
>= 64 ? DImode
: SImode
);
4540 int inv_alignofs
= (align
>= 64 ? 8 : 4) - alignofs
;
4544 mem
= adjust_address (orig_dst
, mode
, ofs
- inv_alignofs
);
4545 set_mem_alias_set (mem
, 0);
4547 mask
= ~(~(HOST_WIDE_INT
)0 << (inv_alignofs
* 8));
4548 if (bytes
< alignofs
)
4550 mask
|= ~(HOST_WIDE_INT
)0 << ((inv_alignofs
+ bytes
) * 8);
4561 tmp
= expand_binop (mode
, and_optab
, mem
, GEN_INT (mask
),
4562 NULL_RTX
, 1, OPTAB_WIDEN
);
4564 emit_move_insn (mem
, tmp
);
4568 if (TARGET_BWX
&& (alignofs
& 1) && bytes
>= 1)
4570 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4575 if (TARGET_BWX
&& align
>= 16 && (alignofs
& 3) == 2 && bytes
>= 2)
4577 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
), const0_rtx
);
4582 if (alignofs
== 4 && bytes
>= 4)
4584 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4590 /* If we've not used the extra lead alignment information by now,
4591 we won't be able to. Downgrade align to match what's left over. */
4594 alignofs
= alignofs
& -alignofs
;
4595 align
= MIN (align
, alignofs
* BITS_PER_UNIT
);
4599 /* Handle a block of contiguous long-words. */
4601 if (align
>= 64 && bytes
>= 8)
4605 for (i
= 0; i
< words
; ++i
)
4606 emit_move_insn (adjust_address (orig_dst
, DImode
, ofs
+ i
* 8),
4613 /* If the block is large and appropriately aligned, emit a single
4614 store followed by a sequence of stq_u insns. */
4616 if (align
>= 32 && bytes
> 16)
4620 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
), const0_rtx
);
4624 orig_dsta
= XEXP (orig_dst
, 0);
4625 if (GET_CODE (orig_dsta
) == LO_SUM
)
4626 orig_dsta
= force_reg (Pmode
, orig_dsta
);
4629 for (i
= 0; i
< words
; ++i
)
4632 = change_address (orig_dst
, DImode
,
4633 gen_rtx_AND (DImode
,
4634 plus_constant (orig_dsta
, ofs
+ i
*8),
4636 set_mem_alias_set (mem
, 0);
4637 emit_move_insn (mem
, const0_rtx
);
4640 /* Depending on the alignment, the first stq_u may have overlapped
4641 with the initial stl, which means that the last stq_u didn't
4642 write as much as it would appear. Leave those questionable bytes
4644 bytes
-= words
* 8 - 4;
4645 ofs
+= words
* 8 - 4;
4648 /* Handle a smaller block of aligned words. */
4650 if ((align
>= 64 && bytes
== 4)
4651 || (align
== 32 && bytes
>= 4))
4655 for (i
= 0; i
< words
; ++i
)
4656 emit_move_insn (adjust_address (orig_dst
, SImode
, ofs
+ i
* 4),
4663 /* An unaligned block uses stq_u stores for as many as possible. */
4669 alpha_expand_unaligned_store_words (NULL
, orig_dst
, words
, ofs
);
4675 /* Next clean up any trailing pieces. */
4677 #if HOST_BITS_PER_WIDE_INT >= 64
4678 /* Count the number of bits in BYTES for which aligned stores could
4681 for (i
= (TARGET_BWX
? 1 : 4); i
* BITS_PER_UNIT
<= align
; i
<<= 1)
4685 /* If we have appropriate alignment (and it wouldn't take too many
4686 instructions otherwise), mask out the bytes we need. */
4687 if (TARGET_BWX
? words
> 2 : bytes
> 0)
4694 mem
= adjust_address (orig_dst
, DImode
, ofs
);
4695 set_mem_alias_set (mem
, 0);
4697 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4699 tmp
= expand_binop (DImode
, and_optab
, mem
, GEN_INT (mask
),
4700 NULL_RTX
, 1, OPTAB_WIDEN
);
4702 emit_move_insn (mem
, tmp
);
4705 else if (align
>= 32 && bytes
< 4)
4710 mem
= adjust_address (orig_dst
, SImode
, ofs
);
4711 set_mem_alias_set (mem
, 0);
4713 mask
= ~(HOST_WIDE_INT
)0 << (bytes
* 8);
4715 tmp
= expand_binop (SImode
, and_optab
, mem
, GEN_INT (mask
),
4716 NULL_RTX
, 1, OPTAB_WIDEN
);
4718 emit_move_insn (mem
, tmp
);
4724 if (!TARGET_BWX
&& bytes
>= 4)
4726 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 4, ofs
);
4736 emit_move_insn (adjust_address (orig_dst
, HImode
, ofs
),
4740 } while (bytes
>= 2);
4742 else if (! TARGET_BWX
)
4744 alpha_expand_unaligned_store (orig_dst
, const0_rtx
, 2, ofs
);
4752 emit_move_insn (adjust_address (orig_dst
, QImode
, ofs
), const0_rtx
);
4760 /* Adjust the cost of a scheduling dependency. Return the new cost of
4761 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4764 alpha_adjust_cost (insn
, link
, dep_insn
, cost
)
4771 enum attr_type insn_type
, dep_insn_type
;
4773 /* If the dependence is an anti-dependence, there is no cost. For an
4774 output dependence, there is sometimes a cost, but it doesn't seem
4775 worth handling those few cases. */
4777 if (REG_NOTE_KIND (link
) != 0)
4780 /* If we can't recognize the insns, we can't really do anything. */
4781 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
4784 insn_type
= get_attr_type (insn
);
4785 dep_insn_type
= get_attr_type (dep_insn
);
4787 /* Bring in the user-defined memory latency. */
4788 if (dep_insn_type
== TYPE_ILD
4789 || dep_insn_type
== TYPE_FLD
4790 || dep_insn_type
== TYPE_LDSYM
)
4791 cost
+= alpha_memory_latency
-1;
4796 /* On EV4, if INSN is a store insn and DEP_INSN is setting the data
4797 being stored, we can sometimes lower the cost. */
4799 if ((insn_type
== TYPE_IST
|| insn_type
== TYPE_FST
)
4800 && (set
= single_set (dep_insn
)) != 0
4801 && GET_CODE (PATTERN (insn
)) == SET
4802 && rtx_equal_p (SET_DEST (set
), SET_SRC (PATTERN (insn
))))
4804 switch (dep_insn_type
)
4808 /* No savings here. */
4812 /* In these cases, we save one cycle. */
4816 /* In all other cases, we save two cycles. */
4817 return MAX (0, cost
- 2);
4821 /* Another case that needs adjustment is an arithmetic or logical
4822 operation. It's cost is usually one cycle, but we default it to
4823 two in the MD file. The only case that it is actually two is
4824 for the address in loads, stores, and jumps. */
4826 if (dep_insn_type
== TYPE_IADD
|| dep_insn_type
== TYPE_ILOG
)
4841 /* The final case is when a compare feeds into an integer branch;
4842 the cost is only one cycle in that case. */
4844 if (dep_insn_type
== TYPE_ICMP
&& insn_type
== TYPE_IBR
)
4849 /* And the lord DEC saith: "A special bypass provides an effective
4850 latency of 0 cycles for an ICMP or ILOG insn producing the test
4851 operand of an IBR or ICMOV insn." */
4853 if ((dep_insn_type
== TYPE_ICMP
|| dep_insn_type
== TYPE_ILOG
)
4854 && (set
= single_set (dep_insn
)) != 0)
4856 /* A branch only has one input. This must be it. */
4857 if (insn_type
== TYPE_IBR
)
4859 /* A conditional move has three, make sure it is the test. */
4860 if (insn_type
== TYPE_ICMOV
4861 && GET_CODE (set_src
= PATTERN (insn
)) == SET
4862 && GET_CODE (set_src
= SET_SRC (set_src
)) == IF_THEN_ELSE
4863 && rtx_equal_p (SET_DEST (set
), XEXP (set_src
, 0)))
4867 /* "The multiplier is unable to receive data from IEU bypass paths.
4868 The instruction issues at the expected time, but its latency is
4869 increased by the time it takes for the input data to become
4870 available to the multiplier" -- which happens in pipeline stage
4871 six, when results are comitted to the register file. */
4873 if (insn_type
== TYPE_IMUL
)
4875 switch (dep_insn_type
)
4877 /* These insns produce their results in pipeline stage five. */
4884 /* Other integer insns produce results in pipeline stage four. */
4892 /* There is additional latency to move the result of (most) FP
4893 operations anywhere but the FP register file. */
4895 if ((insn_type
== TYPE_FST
|| insn_type
== TYPE_FTOI
)
4896 && (dep_insn_type
== TYPE_FADD
||
4897 dep_insn_type
== TYPE_FMUL
||
4898 dep_insn_type
== TYPE_FCMOV
))
4904 /* Otherwise, return the default cost. */
4908 /* Function to initialize the issue rate used by the scheduler. */
4912 return (alpha_cpu
== PROCESSOR_EV4
? 2 : 4);
4916 alpha_variable_issue (dump
, verbose
, insn
, cim
)
4917 FILE *dump ATTRIBUTE_UNUSED
;
4918 int verbose ATTRIBUTE_UNUSED
;
4922 if (recog_memoized (insn
) < 0 || get_attr_type (insn
) == TYPE_MULTI
)
4929 /* Register global variables and machine-specific functions with the
4930 garbage collector. */
4932 #if TARGET_ABI_UNICOSMK
4934 alpha_init_machine_status (p
)
4938 (struct machine_function
*) xcalloc (1, sizeof (struct machine_function
));
4940 p
->machine
->first_ciw
= NULL_RTX
;
4941 p
->machine
->last_ciw
= NULL_RTX
;
4942 p
->machine
->ciw_count
= 0;
4943 p
->machine
->addr_list
= NULL_RTX
;
4947 alpha_mark_machine_status (p
)
4950 struct machine_function
*machine
= p
->machine
;
4954 ggc_mark_rtx (machine
->first_ciw
);
4955 ggc_mark_rtx (machine
->addr_list
);
4960 alpha_free_machine_status (p
)
4966 #endif /* TARGET_ABI_UNICOSMK */
4968 /* Functions to save and restore alpha_return_addr_rtx. */
4970 /* Start the ball rolling with RETURN_ADDR_RTX. */
4973 alpha_return_addr (count
, frame
)
4975 rtx frame ATTRIBUTE_UNUSED
;
4980 return get_hard_reg_initial_val (Pmode
, REG_RA
);
4983 /* Return or create a pseudo containing the gp value for the current
4984 function. Needed only if TARGET_LD_BUGGY_LDGP. */
4987 alpha_gp_save_rtx ()
4989 return get_hard_reg_initial_val (DImode
, 29);
4993 alpha_ra_ever_killed ()
4997 if (!has_hard_reg_initial_val (Pmode
, REG_RA
))
4998 return regs_ever_live
[REG_RA
];
5000 push_topmost_sequence ();
5002 pop_topmost_sequence ();
5004 return reg_set_between_p (gen_rtx_REG (Pmode
, REG_RA
), top
, NULL_RTX
);
5008 /* Return the trap mode suffix applicable to the current
5009 instruction, or NULL. */
5012 get_trap_mode_suffix ()
5014 enum attr_trap_suffix s
= get_attr_trap_suffix (current_output_insn
);
5018 case TRAP_SUFFIX_NONE
:
5021 case TRAP_SUFFIX_SU
:
5022 if (alpha_fptm
>= ALPHA_FPTM_SU
)
5026 case TRAP_SUFFIX_SUI
:
5027 if (alpha_fptm
>= ALPHA_FPTM_SUI
)
5031 case TRAP_SUFFIX_V_SV
:
5039 case ALPHA_FPTM_SUI
:
5044 case TRAP_SUFFIX_V_SV_SVI
:
5053 case ALPHA_FPTM_SUI
:
5058 case TRAP_SUFFIX_U_SU_SUI
:
5067 case ALPHA_FPTM_SUI
:
5075 /* Return the rounding mode suffix applicable to the current
5076 instruction, or NULL. */
5079 get_round_mode_suffix ()
5081 enum attr_round_suffix s
= get_attr_round_suffix (current_output_insn
);
5085 case ROUND_SUFFIX_NONE
:
5087 case ROUND_SUFFIX_NORMAL
:
5090 case ALPHA_FPRM_NORM
:
5092 case ALPHA_FPRM_MINF
:
5094 case ALPHA_FPRM_CHOP
:
5096 case ALPHA_FPRM_DYN
:
5101 case ROUND_SUFFIX_C
:
5107 /* Print an operand. Recognize special options, documented below. */
5110 print_operand (file
, x
, code
)
5120 /* Print the assembler name of the current function. */
5121 assemble_name (file
, alpha_fnname
);
5126 const char *trap
= get_trap_mode_suffix ();
5127 const char *round
= get_round_mode_suffix ();
5130 fprintf (file
, (TARGET_AS_SLASH_BEFORE_SUFFIX
? "/%s%s" : "%s%s"),
5131 (trap
? trap
: ""), (round
? round
: ""));
5136 /* Generates single precision instruction suffix. */
5137 fputc ((TARGET_FLOAT_VAX
? 'f' : 's'), file
);
5141 /* Generates double precision instruction suffix. */
5142 fputc ((TARGET_FLOAT_VAX
? 'g' : 't'), file
);
5146 if (alpha_this_literal_sequence_number
== 0)
5147 alpha_this_literal_sequence_number
= alpha_next_sequence_number
++;
5148 fprintf (file
, "%d", alpha_this_literal_sequence_number
);
5152 if (alpha_this_gpdisp_sequence_number
== 0)
5153 alpha_this_gpdisp_sequence_number
= alpha_next_sequence_number
++;
5154 fprintf (file
, "%d", alpha_this_gpdisp_sequence_number
);
5158 if (GET_CODE (x
) == HIGH
)
5159 output_addr_const (file
, XEXP (x
, 0));
5161 output_operand_lossage ("invalid %%H value");
5165 if (GET_CODE (x
) == CONST_INT
)
5167 if (INTVAL (x
) != 0)
5168 fprintf (file
, "\t\t!lituse_jsr!%d", (int) INTVAL (x
));
5171 output_operand_lossage ("invalid %%J value");
5175 /* If this operand is the constant zero, write it as "$31". */
5176 if (GET_CODE (x
) == REG
)
5177 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5178 else if (x
== CONST0_RTX (GET_MODE (x
)))
5179 fprintf (file
, "$31");
5181 output_operand_lossage ("invalid %%r value");
5185 /* Similar, but for floating-point. */
5186 if (GET_CODE (x
) == REG
)
5187 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5188 else if (x
== CONST0_RTX (GET_MODE (x
)))
5189 fprintf (file
, "$f31");
5191 output_operand_lossage ("invalid %%R value");
5195 /* Write the 1's complement of a constant. */
5196 if (GET_CODE (x
) != CONST_INT
)
5197 output_operand_lossage ("invalid %%N value");
5199 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
5203 /* Write 1 << C, for a constant C. */
5204 if (GET_CODE (x
) != CONST_INT
)
5205 output_operand_lossage ("invalid %%P value");
5207 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (HOST_WIDE_INT
) 1 << INTVAL (x
));
5211 /* Write the high-order 16 bits of a constant, sign-extended. */
5212 if (GET_CODE (x
) != CONST_INT
)
5213 output_operand_lossage ("invalid %%h value");
5215 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) >> 16);
5219 /* Write the low-order 16 bits of a constant, sign-extended. */
5220 if (GET_CODE (x
) != CONST_INT
)
5221 output_operand_lossage ("invalid %%L value");
5223 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5224 (INTVAL (x
) & 0xffff) - 2 * (INTVAL (x
) & 0x8000));
5228 /* Write mask for ZAP insn. */
5229 if (GET_CODE (x
) == CONST_DOUBLE
)
5231 HOST_WIDE_INT mask
= 0;
5232 HOST_WIDE_INT value
;
5234 value
= CONST_DOUBLE_LOW (x
);
5235 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5240 value
= CONST_DOUBLE_HIGH (x
);
5241 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
/ HOST_BITS_PER_CHAR
;
5244 mask
|= (1 << (i
+ sizeof (int)));
5246 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
& 0xff);
5249 else if (GET_CODE (x
) == CONST_INT
)
5251 HOST_WIDE_INT mask
= 0, value
= INTVAL (x
);
5253 for (i
= 0; i
< 8; i
++, value
>>= 8)
5257 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, mask
);
5260 output_operand_lossage ("invalid %%m value");
5264 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5265 if (GET_CODE (x
) != CONST_INT
5266 || (INTVAL (x
) != 8 && INTVAL (x
) != 16
5267 && INTVAL (x
) != 32 && INTVAL (x
) != 64))
5268 output_operand_lossage ("invalid %%M value");
5270 fprintf (file
, "%s",
5271 (INTVAL (x
) == 8 ? "b"
5272 : INTVAL (x
) == 16 ? "w"
5273 : INTVAL (x
) == 32 ? "l"
5278 /* Similar, except do it from the mask. */
5279 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0xff)
5280 fprintf (file
, "b");
5281 else if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0xffff)
5282 fprintf (file
, "w");
5283 else if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0xffffffff)
5284 fprintf (file
, "l");
5285 #if HOST_BITS_PER_WIDE_INT == 32
5286 else if (GET_CODE (x
) == CONST_DOUBLE
5287 && CONST_DOUBLE_HIGH (x
) == 0
5288 && CONST_DOUBLE_LOW (x
) == -1)
5289 fprintf (file
, "l");
5290 else if (GET_CODE (x
) == CONST_DOUBLE
5291 && CONST_DOUBLE_HIGH (x
) == -1
5292 && CONST_DOUBLE_LOW (x
) == -1)
5293 fprintf (file
, "q");
5295 else if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == -1)
5296 fprintf (file
, "q");
5297 else if (GET_CODE (x
) == CONST_DOUBLE
5298 && CONST_DOUBLE_HIGH (x
) == 0
5299 && CONST_DOUBLE_LOW (x
) == -1)
5300 fprintf (file
, "q");
5303 output_operand_lossage ("invalid %%U value");
5307 /* Write the constant value divided by 8 for little-endian mode or
5308 (56 - value) / 8 for big-endian mode. */
5310 if (GET_CODE (x
) != CONST_INT
5311 || (unsigned HOST_WIDE_INT
) INTVAL (x
) >= (WORDS_BIG_ENDIAN
5314 || (INTVAL (x
) & 7) != 0)
5315 output_operand_lossage ("invalid %%s value");
5317 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5319 ? (56 - INTVAL (x
)) / 8
5324 /* Same, except compute (64 - c) / 8 */
5326 if (GET_CODE (x
) != CONST_INT
5327 && (unsigned HOST_WIDE_INT
) INTVAL (x
) >= 64
5328 && (INTVAL (x
) & 7) != 8)
5329 output_operand_lossage ("invalid %%s value");
5331 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (64 - INTVAL (x
)) / 8);
5336 /* On Unicos/Mk systems: use a DEX expression if the symbol
5337 clashes with a register name. */
5338 int dex
= unicosmk_need_dex (x
);
5340 fprintf (file
, "DEX(%d)", dex
);
5342 output_addr_const (file
, x
);
5346 case 'C': case 'D': case 'c': case 'd':
5347 /* Write out comparison name. */
5349 enum rtx_code c
= GET_CODE (x
);
5351 if (GET_RTX_CLASS (c
) != '<')
5352 output_operand_lossage ("invalid %%C value");
5354 else if (code
== 'D')
5355 c
= reverse_condition (c
);
5356 else if (code
== 'c')
5357 c
= swap_condition (c
);
5358 else if (code
== 'd')
5359 c
= swap_condition (reverse_condition (c
));
5362 fprintf (file
, "ule");
5364 fprintf (file
, "ult");
5365 else if (c
== UNORDERED
)
5366 fprintf (file
, "un");
5368 fprintf (file
, "%s", GET_RTX_NAME (c
));
5373 /* Write the divide or modulus operator. */
5374 switch (GET_CODE (x
))
5377 fprintf (file
, "div%s", GET_MODE (x
) == SImode
? "l" : "q");
5380 fprintf (file
, "div%su", GET_MODE (x
) == SImode
? "l" : "q");
5383 fprintf (file
, "rem%s", GET_MODE (x
) == SImode
? "l" : "q");
5386 fprintf (file
, "rem%su", GET_MODE (x
) == SImode
? "l" : "q");
5389 output_operand_lossage ("invalid %%E value");
5395 /* Write "_u" for unaligned access. */
5396 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == AND
)
5397 fprintf (file
, "_u");
5401 if (GET_CODE (x
) == REG
)
5402 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5403 else if (GET_CODE (x
) == MEM
)
5404 output_address (XEXP (x
, 0));
5406 output_addr_const (file
, x
);
5410 output_operand_lossage ("invalid %%xn code");
5415 print_operand_address (file
, addr
)
5420 HOST_WIDE_INT offset
= 0;
5422 if (GET_CODE (addr
) == AND
)
5423 addr
= XEXP (addr
, 0);
5425 if (GET_CODE (addr
) == PLUS
5426 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5428 offset
= INTVAL (XEXP (addr
, 1));
5429 addr
= XEXP (addr
, 0);
5432 if (GET_CODE (addr
) == LO_SUM
)
5434 output_addr_const (file
, XEXP (addr
, 1));
5438 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
5441 addr
= XEXP (addr
, 0);
5442 if (GET_CODE (addr
) == REG
)
5443 basereg
= REGNO (addr
);
5444 else if (GET_CODE (addr
) == SUBREG
5445 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5446 basereg
= subreg_regno (addr
);
5450 fprintf (file
, "($%d)\t\t!%s", basereg
,
5451 (basereg
== 29 ? "gprel" : "gprellow"));
5455 if (GET_CODE (addr
) == REG
)
5456 basereg
= REGNO (addr
);
5457 else if (GET_CODE (addr
) == SUBREG
5458 && GET_CODE (SUBREG_REG (addr
)) == REG
)
5459 basereg
= subreg_regno (addr
);
5460 else if (GET_CODE (addr
) == CONST_INT
)
5461 offset
= INTVAL (addr
);
5465 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
5466 fprintf (file
, "($%d)", basereg
);
5469 /* Emit RTL insns to initialize the variable parts of a trampoline at
5470 TRAMP. FNADDR is an RTX for the address of the function's pure
5471 code. CXT is an RTX for the static chain value for the function.
5473 The three offset parameters are for the individual template's
5474 layout. A JMPOFS < 0 indicates that the trampoline does not
5475 contain instructions at all.
5477 We assume here that a function will be called many more times than
5478 its address is taken (e.g., it might be passed to qsort), so we
5479 take the trouble to initialize the "hint" field in the JMP insn.
5480 Note that the hint field is PC (new) + 4 * bits 13:0. */
5483 alpha_initialize_trampoline (tramp
, fnaddr
, cxt
, fnofs
, cxtofs
, jmpofs
)
5484 rtx tramp
, fnaddr
, cxt
;
5485 int fnofs
, cxtofs
, jmpofs
;
5487 rtx temp
, temp1
, addr
;
5488 /* VMS really uses DImode pointers in memory at this point. */
5489 enum machine_mode mode
= TARGET_ABI_OPEN_VMS
? Pmode
: ptr_mode
;
5491 #ifdef POINTERS_EXTEND_UNSIGNED
5492 fnaddr
= convert_memory_address (mode
, fnaddr
);
5493 cxt
= convert_memory_address (mode
, cxt
);
5496 /* Store function address and CXT. */
5497 addr
= memory_address (mode
, plus_constant (tramp
, fnofs
));
5498 emit_move_insn (gen_rtx_MEM (mode
, addr
), fnaddr
);
5499 addr
= memory_address (mode
, plus_constant (tramp
, cxtofs
));
5500 emit_move_insn (gen_rtx_MEM (mode
, addr
), cxt
);
5502 /* This has been disabled since the hint only has a 32k range, and in
5503 no existing OS is the stack within 32k of the text segment. */
5504 if (0 && jmpofs
>= 0)
5506 /* Compute hint value. */
5507 temp
= force_operand (plus_constant (tramp
, jmpofs
+4), NULL_RTX
);
5508 temp
= expand_binop (DImode
, sub_optab
, fnaddr
, temp
, temp
, 1,
5510 temp
= expand_shift (RSHIFT_EXPR
, Pmode
, temp
,
5511 build_int_2 (2, 0), NULL_RTX
, 1);
5512 temp
= expand_and (gen_lowpart (SImode
, temp
), GEN_INT (0x3fff), 0);
5514 /* Merge in the hint. */
5515 addr
= memory_address (SImode
, plus_constant (tramp
, jmpofs
));
5516 temp1
= force_reg (SImode
, gen_rtx_MEM (SImode
, addr
));
5517 temp1
= expand_and (temp1
, GEN_INT (0xffffc000), NULL_RTX
);
5518 temp1
= expand_binop (SImode
, ior_optab
, temp1
, temp
, temp1
, 1,
5520 emit_move_insn (gen_rtx_MEM (SImode
, addr
), temp1
);
5523 #ifdef TRANSFER_FROM_TRAMPOLINE
5524 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
5525 0, VOIDmode
, 1, addr
, Pmode
);
5529 emit_insn (gen_imb ());
5532 /* Determine where to put an argument to a function.
5533 Value is zero to push the argument on the stack,
5534 or a hard register in which to store the argument.
5536 MODE is the argument's machine mode.
5537 TYPE is the data type of the argument (as a tree).
5538 This is null for libcalls where that information may
5540 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5541 the preceding args and about the function being called.
5542 NAMED is nonzero if this argument is a named parameter
5543 (otherwise it is an extra parameter matching an ellipsis).
5545 On Alpha the first 6 words of args are normally in registers
5546 and the rest are pushed. */
5549 function_arg (cum
, mode
, type
, named
)
5550 CUMULATIVE_ARGS cum
;
5551 enum machine_mode mode
;
5553 int named ATTRIBUTE_UNUSED
;
5558 /* Set up defaults for FP operands passed in FP registers, and
5559 integral operands passed in integer registers. */
5561 && (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5562 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
5567 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5568 the three platforms, so we can't avoid conditional compilation. */
5569 #if TARGET_ABI_OPEN_VMS
5571 if (mode
== VOIDmode
)
5572 return alpha_arg_info_reg_val (cum
);
5574 num_args
= cum
.num_args
;
5575 if (num_args
>= 6 || MUST_PASS_IN_STACK (mode
, type
))
5579 #if TARGET_ABI_UNICOSMK
5583 /* If this is the last argument, generate the call info word (CIW). */
5584 /* ??? We don't include the caller's line number in the CIW because
5585 I don't know how to determine it if debug infos are turned off. */
5586 if (mode
== VOIDmode
)
5595 for (i
= 0; i
< cum
.num_reg_words
&& i
< 5; i
++)
5596 if (cum
.reg_args_type
[i
])
5597 lo
|= (1 << (7 - i
));
5599 if (cum
.num_reg_words
== 6 && cum
.reg_args_type
[5])
5602 lo
|= cum
.num_reg_words
;
5604 #if HOST_BITS_PER_WIDE_INT == 32
5605 hi
= (cum
.num_args
<< 20) | cum
.num_arg_words
;
5607 lo
= lo
| ((HOST_WIDE_INT
) cum
.num_args
<< 52)
5608 | ((HOST_WIDE_INT
) cum
.num_arg_words
<< 32);
5611 ciw
= immed_double_const (lo
, hi
, DImode
);
5613 return gen_rtx_UNSPEC (DImode
, gen_rtvec (1, ciw
),
5614 UNSPEC_UMK_LOAD_CIW
);
5617 size
= ALPHA_ARG_SIZE (mode
, type
, named
);
5618 num_args
= cum
.num_reg_words
;
5619 if (MUST_PASS_IN_STACK (mode
, type
)
5620 || cum
.num_reg_words
+ size
> 6 || cum
.force_stack
)
5622 else if (type
&& TYPE_MODE (type
) == BLKmode
)
5626 reg1
= gen_rtx_REG (DImode
, num_args
+ 16);
5627 reg1
= gen_rtx_EXPR_LIST (DImode
, reg1
, const0_rtx
);
5629 /* The argument fits in two registers. Note that we still need to
5630 reserve a register for empty structures. */
5634 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, reg1
));
5637 reg2
= gen_rtx_REG (DImode
, num_args
+ 17);
5638 reg2
= gen_rtx_EXPR_LIST (DImode
, reg2
, GEN_INT (8));
5639 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, reg1
, reg2
));
5649 /* VOID is passed as a special flag for "last argument". */
5650 if (type
== void_type_node
)
5652 else if (MUST_PASS_IN_STACK (mode
, type
))
5654 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum
, mode
, type
, named
))
5657 #endif /* TARGET_ABI_UNICOSMK */
5658 #endif /* TARGET_ABI_OPEN_VMS */
5660 return gen_rtx_REG (mode
, num_args
+ basereg
);
5664 alpha_build_va_list ()
5666 tree base
, ofs
, record
, type_decl
;
5668 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
5669 return ptr_type_node
;
5671 record
= make_lang_type (RECORD_TYPE
);
5672 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
5673 TREE_CHAIN (record
) = type_decl
;
5674 TYPE_NAME (record
) = type_decl
;
5676 /* C++? SET_IS_AGGR_TYPE (record, 1); */
5678 ofs
= build_decl (FIELD_DECL
, get_identifier ("__offset"),
5680 DECL_FIELD_CONTEXT (ofs
) = record
;
5682 base
= build_decl (FIELD_DECL
, get_identifier ("__base"),
5684 DECL_FIELD_CONTEXT (base
) = record
;
5685 TREE_CHAIN (base
) = ofs
;
5687 TYPE_FIELDS (record
) = base
;
5688 layout_type (record
);
5694 alpha_va_start (stdarg_p
, valist
, nextarg
)
5697 rtx nextarg ATTRIBUTE_UNUSED
;
5699 HOST_WIDE_INT offset
;
5700 tree t
, offset_field
, base_field
;
5702 if (TREE_CODE (TREE_TYPE (valist
)) == ERROR_MARK
)
5705 if (TARGET_ABI_UNICOSMK
)
5706 std_expand_builtin_va_start (stdarg_p
, valist
, nextarg
);
5708 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
5709 up by 48, storing fp arg registers in the first 48 bytes, and the
5710 integer arg registers in the next 48 bytes. This is only done,
5711 however, if any integer registers need to be stored.
5713 If no integer registers need be stored, then we must subtract 48
5714 in order to account for the integer arg registers which are counted
5715 in argsize above, but which are not actually stored on the stack. */
5717 if (NUM_ARGS
<= 5 + stdarg_p
)
5718 offset
= TARGET_ABI_OPEN_VMS
? UNITS_PER_WORD
: 6 * UNITS_PER_WORD
;
5720 offset
= -6 * UNITS_PER_WORD
;
5722 if (TARGET_ABI_OPEN_VMS
)
5724 nextarg
= plus_constant (nextarg
, offset
);
5725 nextarg
= plus_constant (nextarg
, NUM_ARGS
* UNITS_PER_WORD
);
5726 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
5727 make_tree (ptr_type_node
, nextarg
));
5728 TREE_SIDE_EFFECTS (t
) = 1;
5730 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5734 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
5735 offset_field
= TREE_CHAIN (base_field
);
5737 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
5738 valist
, base_field
);
5739 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
5740 valist
, offset_field
);
5742 t
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
5743 t
= build (PLUS_EXPR
, ptr_type_node
, t
, build_int_2 (offset
, 0));
5744 t
= build (MODIFY_EXPR
, TREE_TYPE (base_field
), base_field
, t
);
5745 TREE_SIDE_EFFECTS (t
) = 1;
5746 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5748 t
= build_int_2 (NUM_ARGS
* UNITS_PER_WORD
, 0);
5749 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
, t
);
5750 TREE_SIDE_EFFECTS (t
) = 1;
5751 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5756 alpha_va_arg (valist
, type
)
5759 HOST_WIDE_INT tsize
;
5762 tree offset_field
, base_field
, addr_tree
, addend
;
5763 tree wide_type
, wide_ofs
;
5766 if (TARGET_ABI_OPEN_VMS
|| TARGET_ABI_UNICOSMK
)
5767 return std_expand_builtin_va_arg (valist
, type
);
5769 tsize
= ((TREE_INT_CST_LOW (TYPE_SIZE (type
)) / BITS_PER_UNIT
+ 7) / 8) * 8;
5771 base_field
= TYPE_FIELDS (TREE_TYPE (valist
));
5772 offset_field
= TREE_CHAIN (base_field
);
5774 base_field
= build (COMPONENT_REF
, TREE_TYPE (base_field
),
5775 valist
, base_field
);
5776 offset_field
= build (COMPONENT_REF
, TREE_TYPE (offset_field
),
5777 valist
, offset_field
);
5779 wide_type
= make_signed_type (64);
5780 wide_ofs
= save_expr (build1 (CONVERT_EXPR
, wide_type
, offset_field
));
5784 if (TYPE_MODE (type
) == TFmode
|| TYPE_MODE (type
) == TCmode
)
5787 tsize
= UNITS_PER_WORD
;
5789 else if (FLOAT_TYPE_P (type
))
5791 tree fpaddend
, cond
;
5793 fpaddend
= fold (build (PLUS_EXPR
, TREE_TYPE (addend
),
5794 addend
, build_int_2 (-6*8, 0)));
5796 cond
= fold (build (LT_EXPR
, integer_type_node
,
5797 wide_ofs
, build_int_2 (6*8, 0)));
5799 addend
= fold (build (COND_EXPR
, TREE_TYPE (addend
), cond
,
5803 addr_tree
= build (PLUS_EXPR
, TREE_TYPE (base_field
),
5804 base_field
, addend
);
5806 addr
= expand_expr (addr_tree
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
5807 addr
= copy_to_reg (addr
);
5809 t
= build (MODIFY_EXPR
, TREE_TYPE (offset_field
), offset_field
,
5810 build (PLUS_EXPR
, TREE_TYPE (offset_field
),
5811 offset_field
, build_int_2 (tsize
, 0)));
5812 TREE_SIDE_EFFECTS (t
) = 1;
5813 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5817 addr
= force_reg (Pmode
, addr
);
5818 addr
= gen_rtx_MEM (Pmode
, addr
);
5824 /* This page contains routines that are used to determine what the function
5825 prologue and epilogue code will do and write them out. */
5827 /* Compute the size of the save area in the stack. */
5829 /* These variables are used for communication between the following functions.
5830 They indicate various things about the current function being compiled
5831 that are used to tell what kind of prologue, epilogue and procedure
5832 descriptior to generate. */
5834 /* Nonzero if we need a stack procedure. */
5835 enum alpha_procedure_types
{PT_NULL
= 0, PT_REGISTER
= 1, PT_STACK
= 2};
5836 static enum alpha_procedure_types alpha_procedure_type
;
5838 /* Register number (either FP or SP) that is used to unwind the frame. */
5839 static int vms_unwind_regno
;
5841 /* Register number used to save FP. We need not have one for RA since
5842 we don't modify it for register procedures. This is only defined
5843 for register frame procedures. */
5844 static int vms_save_fp_regno
;
5846 /* Register number used to reference objects off our PV. */
5847 static int vms_base_regno
;
5849 /* Compute register masks for saved registers. */
5852 alpha_sa_mask (imaskP
, fmaskP
)
5853 unsigned long *imaskP
;
5854 unsigned long *fmaskP
;
5856 unsigned long imask
= 0;
5857 unsigned long fmask
= 0;
5860 /* Irritatingly, there are two kinds of thunks -- those created with
5861 ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go through
5862 the regular part of the compiler. In the ASM_OUTPUT_MI_THUNK case
5863 we don't have valid register life info, but assemble_start_function
5864 wants to output .frame and .mask directives. */
5865 if (current_function_is_thunk
&& rtx_equal_function_value_matters
)
5872 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
5873 imask
|= (1L << HARD_FRAME_POINTER_REGNUM
);
5875 /* One for every register we have to save. */
5876 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5877 if (! fixed_regs
[i
] && ! call_used_regs
[i
]
5878 && regs_ever_live
[i
] && i
!= REG_RA
5879 && (!TARGET_ABI_UNICOSMK
|| i
!= HARD_FRAME_POINTER_REGNUM
))
5884 fmask
|= (1L << (i
- 32));
5887 /* We need to restore these for the handler. */
5888 if (current_function_calls_eh_return
)
5891 unsigned regno
= EH_RETURN_DATA_REGNO (i
);
5892 if (regno
== INVALID_REGNUM
)
5894 imask
|= 1L << regno
;
5897 /* If any register spilled, then spill the return address also. */
5898 /* ??? This is required by the Digital stack unwind specification
5899 and isn't needed if we're doing Dwarf2 unwinding. */
5900 if (imask
|| fmask
|| alpha_ra_ever_killed ())
5901 imask
|= (1L << REG_RA
);
5910 unsigned long mask
[2];
5914 alpha_sa_mask (&mask
[0], &mask
[1]);
5916 if (TARGET_ABI_UNICOSMK
)
5918 if (mask
[0] || mask
[1])
5923 for (j
= 0; j
< 2; ++j
)
5924 for (i
= 0; i
< 32; ++i
)
5925 if ((mask
[j
] >> i
) & 1)
5929 if (TARGET_ABI_UNICOSMK
)
5931 /* We might not need to generate a frame if we don't make any calls
5932 (including calls to __T3E_MISMATCH if this is a vararg function),
5933 don't have any local variables which require stack slots, don't
5934 use alloca and have not determined that we need a frame for other
5937 alpha_procedure_type
5938 = (sa_size
|| get_frame_size() != 0
5939 || current_function_outgoing_args_size
|| current_function_varargs
5940 || current_function_stdarg
|| current_function_calls_alloca
5941 || frame_pointer_needed
)
5942 ? PT_STACK
: PT_REGISTER
;
5944 /* Always reserve space for saving callee-saved registers if we
5945 need a frame as required by the calling convention. */
5946 if (alpha_procedure_type
== PT_STACK
)
5949 else if (TARGET_ABI_OPEN_VMS
)
5951 /* Start by assuming we can use a register procedure if we don't
5952 make any calls (REG_RA not used) or need to save any
5953 registers and a stack procedure if we do. */
5954 if ((mask
[0] >> REG_RA
) & 1)
5955 alpha_procedure_type
= PT_STACK
;
5956 else if (get_frame_size() != 0)
5957 alpha_procedure_type
= PT_REGISTER
;
5959 alpha_procedure_type
= PT_NULL
;
5961 /* Don't reserve space for saving RA yet. Do that later after we've
5962 made the final decision on stack procedure vs register procedure. */
5963 if (alpha_procedure_type
== PT_STACK
)
5966 /* Decide whether to refer to objects off our PV via FP or PV.
5967 If we need FP for something else or if we receive a nonlocal
5968 goto (which expects PV to contain the value), we must use PV.
5969 Otherwise, start by assuming we can use FP. */
5972 = (frame_pointer_needed
5973 || current_function_has_nonlocal_label
5974 || alpha_procedure_type
== PT_STACK
5975 || current_function_outgoing_args_size
)
5976 ? REG_PV
: HARD_FRAME_POINTER_REGNUM
;
5978 /* If we want to copy PV into FP, we need to find some register
5979 in which to save FP. */
5981 vms_save_fp_regno
= -1;
5982 if (vms_base_regno
== HARD_FRAME_POINTER_REGNUM
)
5983 for (i
= 0; i
< 32; i
++)
5984 if (! fixed_regs
[i
] && call_used_regs
[i
] && ! regs_ever_live
[i
])
5985 vms_save_fp_regno
= i
;
5987 if (vms_save_fp_regno
== -1 && alpha_procedure_type
== PT_REGISTER
)
5988 vms_base_regno
= REG_PV
, alpha_procedure_type
= PT_STACK
;
5989 else if (alpha_procedure_type
== PT_NULL
)
5990 vms_base_regno
= REG_PV
;
5992 /* Stack unwinding should be done via FP unless we use it for PV. */
5993 vms_unwind_regno
= (vms_base_regno
== REG_PV
5994 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
5996 /* If this is a stack procedure, allow space for saving FP and RA. */
5997 if (alpha_procedure_type
== PT_STACK
)
6002 /* Our size must be even (multiple of 16 bytes). */
6011 alpha_pv_save_size ()
6014 return alpha_procedure_type
== PT_STACK
? 8 : 0;
6021 return vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
;
6024 #if TARGET_ABI_OPEN_VMS
6026 const struct attribute_spec vms_attribute_table
[] =
6028 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6029 { "overlaid", 0, 0, true, false, false, NULL
},
6030 { "global", 0, 0, true, false, false, NULL
},
6031 { "initialize", 0, 0, true, false, false, NULL
},
6032 { NULL
, 0, 0, false, false, false, NULL
}
6038 find_lo_sum (px
, data
)
6040 void *data ATTRIBUTE_UNUSED
;
6042 return GET_CODE (*px
) == LO_SUM
;
6046 alpha_does_function_need_gp ()
6050 /* The GP being variable is an OSF abi thing. */
6051 if (! TARGET_ABI_OSF
)
6054 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6057 if (current_function_is_thunk
)
6060 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6061 Even if we are a static function, we still need to do this in case
6062 our address is taken and passed to something like qsort. */
6064 push_topmost_sequence ();
6065 insn
= get_insns ();
6066 pop_topmost_sequence ();
6068 for (; insn
; insn
= NEXT_INSN (insn
))
6070 && GET_CODE (PATTERN (insn
)) != USE
6071 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6073 enum attr_type type
= get_attr_type (insn
);
6074 if (type
== TYPE_LDSYM
|| type
== TYPE_JSR
)
6076 if (TARGET_EXPLICIT_RELOCS
6077 && for_each_rtx (&PATTERN (insn
), find_lo_sum
, NULL
) > 0)
6084 /* Write a version stamp. Don't write anything if we are running as a
6085 cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
6092 alpha_write_verstamp (file
)
6093 FILE *file ATTRIBUTE_UNUSED
;
6096 fprintf (file
, "\t.verstamp %d %d\n", MS_STAMP
, LS_STAMP
);
6100 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6104 set_frame_related_p ()
6106 rtx seq
= gen_sequence ();
6109 if (GET_CODE (seq
) == SEQUENCE
)
6111 int i
= XVECLEN (seq
, 0);
6113 RTX_FRAME_RELATED_P (XVECEXP (seq
, 0, i
)) = 1;
6114 return emit_insn (seq
);
6118 seq
= emit_insn (seq
);
6119 RTX_FRAME_RELATED_P (seq
) = 1;
6124 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
6126 /* Write function prologue. */
6128 /* On vms we have two kinds of functions:
6130 - stack frame (PROC_STACK)
6131 these are 'normal' functions with local vars and which are
6132 calling other functions
6133 - register frame (PROC_REGISTER)
6134 keeps all data in registers, needs no stack
6136 We must pass this to the assembler so it can generate the
6137 proper pdsc (procedure descriptor)
6138 This is done with the '.pdesc' command.
6140 On not-vms, we don't really differentiate between the two, as we can
6141 simply allocate stack without saving registers. */
6144 alpha_expand_prologue ()
6146 /* Registers to save. */
6147 unsigned long imask
= 0;
6148 unsigned long fmask
= 0;
6149 /* Stack space needed for pushing registers clobbered by us. */
6150 HOST_WIDE_INT sa_size
;
6151 /* Complete stack size needed. */
6152 HOST_WIDE_INT frame_size
;
6153 /* Offset from base reg to register save area. */
6154 HOST_WIDE_INT reg_offset
;
6158 sa_size
= alpha_sa_size ();
6160 frame_size
= get_frame_size ();
6161 if (TARGET_ABI_OPEN_VMS
)
6162 frame_size
= ALPHA_ROUND (sa_size
6163 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
6165 + current_function_pretend_args_size
);
6166 else if (TARGET_ABI_UNICOSMK
)
6167 /* We have to allocate space for the DSIB if we generate a frame. */
6168 frame_size
= ALPHA_ROUND (sa_size
6169 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
6170 + ALPHA_ROUND (frame_size
6171 + current_function_outgoing_args_size
);
6173 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
6175 + ALPHA_ROUND (frame_size
6176 + current_function_pretend_args_size
));
6178 if (TARGET_ABI_OPEN_VMS
)
6181 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
6183 alpha_sa_mask (&imask
, &fmask
);
6185 /* Emit an insn to reload GP, if needed. */
6188 alpha_function_needs_gp
= alpha_does_function_need_gp ();
6189 if (alpha_function_needs_gp
)
6190 emit_insn (gen_prologue_ldgp ());
6193 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
6194 the call to mcount ourselves, rather than having the linker do it
6195 magically in response to -pg. Since _mcount has special linkage,
6196 don't represent the call as a call. */
6197 if (TARGET_PROFILING_NEEDS_GP
&& current_function_profile
)
6198 emit_insn (gen_prologue_mcount ());
6200 if (TARGET_ABI_UNICOSMK
)
6201 unicosmk_gen_dsib (&imask
);
6203 /* Adjust the stack by the frame size. If the frame size is > 4096
6204 bytes, we need to be sure we probe somewhere in the first and last
6205 4096 bytes (we can probably get away without the latter test) and
6206 every 8192 bytes in between. If the frame size is > 32768, we
6207 do this in a loop. Otherwise, we generate the explicit probe
6210 Note that we are only allowed to adjust sp once in the prologue. */
6212 if (frame_size
<= 32768)
6214 if (frame_size
> 4096)
6219 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
6222 while ((probed
+= 8192) < frame_size
);
6224 /* We only have to do this probe if we aren't saving registers. */
6225 if (sa_size
== 0 && probed
+ 4096 < frame_size
)
6226 emit_insn (gen_probe_stack (GEN_INT (-frame_size
)));
6229 if (frame_size
!= 0)
6230 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
6231 GEN_INT (TARGET_ABI_UNICOSMK
6237 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
6238 number of 8192 byte blocks to probe. We then probe each block
6239 in the loop and then set SP to the proper location. If the
6240 amount remaining is > 4096, we have to do one more probe if we
6241 are not saving any registers. */
6243 HOST_WIDE_INT blocks
= (frame_size
+ 4096) / 8192;
6244 HOST_WIDE_INT leftover
= frame_size
+ 4096 - blocks
* 8192;
6245 rtx ptr
= gen_rtx_REG (DImode
, 22);
6246 rtx count
= gen_rtx_REG (DImode
, 23);
6249 emit_move_insn (count
, GEN_INT (blocks
));
6250 emit_insn (gen_adddi3 (ptr
, stack_pointer_rtx
,
6251 GEN_INT (TARGET_ABI_UNICOSMK
? 4096 - 64 : 4096)));
6253 /* Because of the difficulty in emitting a new basic block this
6254 late in the compilation, generate the loop as a single insn. */
6255 emit_insn (gen_prologue_stack_probe_loop (count
, ptr
));
6257 if (leftover
> 4096 && sa_size
== 0)
6259 rtx last
= gen_rtx_MEM (DImode
, plus_constant (ptr
, -leftover
));
6260 MEM_VOLATILE_P (last
) = 1;
6261 emit_move_insn (last
, const0_rtx
);
6264 if (TARGET_ABI_WINDOWS_NT
)
6266 /* For NT stack unwind (done by 'reverse execution'), it's
6267 not OK to take the result of a loop, even though the value
6268 is already in ptr, so we reload it via a single operation
6269 and subtract it to sp.
6271 Yes, that's correct -- we have to reload the whole constant
6272 into a temporary via ldah+lda then subtract from sp. To
6273 ensure we get ldah+lda, we use a special pattern. */
6275 HOST_WIDE_INT lo
, hi
;
6276 lo
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
6277 hi
= frame_size
- lo
;
6279 emit_move_insn (ptr
, GEN_INT (hi
));
6280 emit_insn (gen_nt_lda (ptr
, GEN_INT (lo
)));
6281 seq
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
6286 seq
= emit_insn (gen_adddi3 (stack_pointer_rtx
, ptr
,
6287 GEN_INT (-leftover
)));
6290 /* This alternative is special, because the DWARF code cannot
6291 possibly intuit through the loop above. So we invent this
6292 note it looks at instead. */
6293 RTX_FRAME_RELATED_P (seq
) = 1;
6295 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
6296 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
6297 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
6298 GEN_INT (TARGET_ABI_UNICOSMK
6304 if (!TARGET_ABI_UNICOSMK
)
6306 /* Cope with very large offsets to the register save area. */
6307 sa_reg
= stack_pointer_rtx
;
6308 if (reg_offset
+ sa_size
> 0x8000)
6310 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
6313 if (low
+ sa_size
<= 0x8000)
6314 bias
= reg_offset
- low
, reg_offset
= low
;
6316 bias
= reg_offset
, reg_offset
= 0;
6318 sa_reg
= gen_rtx_REG (DImode
, 24);
6319 FRP (emit_insn (gen_adddi3 (sa_reg
, stack_pointer_rtx
,
6323 /* Save regs in stack order. Beginning with VMS PV. */
6324 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6326 mem
= gen_rtx_MEM (DImode
, stack_pointer_rtx
);
6327 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6328 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_PV
)));
6331 /* Save register RA next. */
6332 if (imask
& (1L << REG_RA
))
6334 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
6335 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6336 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
6337 imask
&= ~(1L << REG_RA
);
6341 /* Now save any other registers required to be saved. */
6342 for (i
= 0; i
< 32; i
++)
6343 if (imask
& (1L << i
))
6345 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
6346 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6347 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
6351 for (i
= 0; i
< 32; i
++)
6352 if (fmask
& (1L << i
))
6354 mem
= gen_rtx_MEM (DFmode
, plus_constant (sa_reg
, reg_offset
));
6355 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6356 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
6360 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
6362 /* The standard frame on the T3E includes space for saving registers.
6363 We just have to use it. We don't have to save the return address and
6364 the old frame pointer here - they are saved in the DSIB. */
6367 for (i
= 9; i
< 15; i
++)
6368 if (imask
& (1L << i
))
6370 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
6372 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6373 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, i
)));
6376 for (i
= 2; i
< 10; i
++)
6377 if (fmask
& (1L << i
))
6379 mem
= gen_rtx_MEM (DFmode
, plus_constant (hard_frame_pointer_rtx
,
6381 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6382 FRP (emit_move_insn (mem
, gen_rtx_REG (DFmode
, i
+32)));
6387 if (TARGET_ABI_OPEN_VMS
)
6389 if (alpha_procedure_type
== PT_REGISTER
)
6390 /* Register frame procedures save the fp.
6391 ?? Ought to have a dwarf2 save for this. */
6392 emit_move_insn (gen_rtx_REG (DImode
, vms_save_fp_regno
),
6393 hard_frame_pointer_rtx
);
6395 if (alpha_procedure_type
!= PT_NULL
&& vms_base_regno
!= REG_PV
)
6396 emit_insn (gen_force_movdi (gen_rtx_REG (DImode
, vms_base_regno
),
6397 gen_rtx_REG (DImode
, REG_PV
)));
6399 if (alpha_procedure_type
!= PT_NULL
6400 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
6401 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
6403 /* If we have to allocate space for outgoing args, do it now. */
6404 if (current_function_outgoing_args_size
!= 0)
6407 plus_constant (hard_frame_pointer_rtx
,
6409 (current_function_outgoing_args_size
)))));
6411 else if (!TARGET_ABI_UNICOSMK
)
6413 /* If we need a frame pointer, set it from the stack pointer. */
6414 if (frame_pointer_needed
)
6416 if (TARGET_CAN_FAULT_IN_PROLOGUE
)
6417 FRP (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
));
6419 /* This must always be the last instruction in the
6420 prologue, thus we emit a special move + clobber. */
6421 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx
,
6422 stack_pointer_rtx
, sa_reg
)));
6426 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
6427 the prologue, for exception handling reasons, we cannot do this for
6428 any insn that might fault. We could prevent this for mems with a
6429 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
6430 have to prevent all such scheduling with a blockage.
6432 Linux, on the other hand, never bothered to implement OSF/1's
6433 exception handling, and so doesn't care about such things. Anyone
6434 planning to use dwarf2 frame-unwind info can also omit the blockage. */
6436 if (! TARGET_CAN_FAULT_IN_PROLOGUE
)
6437 emit_insn (gen_blockage ());
6440 /* Output the textual info surrounding the prologue. */
6443 alpha_start_function (file
, fnname
, decl
)
6446 tree decl ATTRIBUTE_UNUSED
;
6448 unsigned long imask
= 0;
6449 unsigned long fmask
= 0;
6450 /* Stack space needed for pushing registers clobbered by us. */
6451 HOST_WIDE_INT sa_size
;
6452 /* Complete stack size needed. */
6453 HOST_WIDE_INT frame_size
;
6454 /* Offset from base reg to register save area. */
6455 HOST_WIDE_INT reg_offset
;
6456 char *entry_label
= (char *) alloca (strlen (fnname
) + 6);
6459 /* Don't emit an extern directive for functions defined in the same file. */
6460 if (TARGET_ABI_UNICOSMK
)
6463 name_tree
= get_identifier (fnname
);
6464 TREE_ASM_WRITTEN (name_tree
) = 1;
6467 alpha_fnname
= fnname
;
6468 sa_size
= alpha_sa_size ();
6470 frame_size
= get_frame_size ();
6471 if (TARGET_ABI_OPEN_VMS
)
6472 frame_size
= ALPHA_ROUND (sa_size
6473 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
6475 + current_function_pretend_args_size
);
6476 else if (TARGET_ABI_UNICOSMK
)
6477 frame_size
= ALPHA_ROUND (sa_size
6478 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
6479 + ALPHA_ROUND (frame_size
6480 + current_function_outgoing_args_size
);
6482 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
6484 + ALPHA_ROUND (frame_size
6485 + current_function_pretend_args_size
));
6487 if (TARGET_ABI_OPEN_VMS
)
6490 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
6492 alpha_sa_mask (&imask
, &fmask
);
6494 /* Ecoff can handle multiple .file directives, so put out file and lineno.
6495 We have to do that before the .ent directive as we cannot switch
6496 files within procedures with native ecoff because line numbers are
6497 linked to procedure descriptors.
6498 Outputting the lineno helps debugging of one line functions as they
6499 would otherwise get no line number at all. Please note that we would
6500 like to put out last_linenum from final.c, but it is not accessible. */
6502 if (write_symbols
== SDB_DEBUG
)
6504 #ifdef ASM_OUTPUT_SOURCE_FILENAME
6505 ASM_OUTPUT_SOURCE_FILENAME (file
,
6506 DECL_SOURCE_FILE (current_function_decl
));
6508 #ifdef ASM_OUTPUT_SOURCE_LINE
6509 if (debug_info_level
!= DINFO_LEVEL_TERSE
)
6510 ASM_OUTPUT_SOURCE_LINE (file
,
6511 DECL_SOURCE_LINE (current_function_decl
));
6515 /* Issue function start and label. */
6516 if (TARGET_ABI_OPEN_VMS
6517 || (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
))
6519 fputs ("\t.ent ", file
);
6520 assemble_name (file
, fnname
);
6523 /* If the function needs GP, we'll write the "..ng" label there.
6524 Otherwise, do it here. */
6526 && ! alpha_function_needs_gp
6527 && ! current_function_is_thunk
)
6530 assemble_name (file
, fnname
);
6531 fputs ("..ng:\n", file
);
6535 strcpy (entry_label
, fnname
);
6536 if (TARGET_ABI_OPEN_VMS
)
6537 strcat (entry_label
, "..en");
6539 /* For public functions, the label must be globalized by appending an
6540 additional colon. */
6541 if (TARGET_ABI_UNICOSMK
&& TREE_PUBLIC (decl
))
6542 strcat (entry_label
, ":");
6544 ASM_OUTPUT_LABEL (file
, entry_label
);
6545 inside_function
= TRUE
;
6547 if (TARGET_ABI_OPEN_VMS
)
6548 fprintf (file
, "\t.base $%d\n", vms_base_regno
);
6550 if (!TARGET_ABI_OPEN_VMS
&& !TARGET_ABI_UNICOSMK
&& TARGET_IEEE_CONFORMANT
6551 && !flag_inhibit_size_directive
)
6553 /* Set flags in procedure descriptor to request IEEE-conformant
6554 math-library routines. The value we set it to is PDSC_EXC_IEEE
6555 (/usr/include/pdsc.h). */
6556 fputs ("\t.eflag 48\n", file
);
6559 /* Set up offsets to alpha virtual arg/local debugging pointer. */
6560 alpha_auto_offset
= -frame_size
+ current_function_pretend_args_size
;
6561 alpha_arg_offset
= -frame_size
+ 48;
6563 /* Describe our frame. If the frame size is larger than an integer,
6564 print it as zero to avoid an assembler error. We won't be
6565 properly describing such a frame, but that's the best we can do. */
6566 if (TARGET_ABI_UNICOSMK
)
6568 else if (TARGET_ABI_OPEN_VMS
)
6570 fprintf (file
, "\t.frame $%d,", vms_unwind_regno
);
6571 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6572 frame_size
>= ((HOST_WIDE_INT
) 1 << 31) ? 0 : frame_size
);
6573 fputs (",$26,", file
);
6574 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, reg_offset
);
6577 else if (!flag_inhibit_size_directive
)
6579 fprintf (file
, "\t.frame $%d,",
6580 (frame_pointer_needed
6581 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
));
6582 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6583 frame_size
>= (1l << 31) ? 0 : frame_size
);
6584 fprintf (file
, ",$26,%d\n", current_function_pretend_args_size
);
6587 /* Describe which registers were spilled. */
6588 if (TARGET_ABI_UNICOSMK
)
6590 else if (TARGET_ABI_OPEN_VMS
)
6593 /* ??? Does VMS care if mask contains ra? The old code didn't
6594 set it, so I don't here. */
6595 fprintf (file
, "\t.mask 0x%lx,0\n", imask
& ~(1L << REG_RA
));
6597 fprintf (file
, "\t.fmask 0x%lx,0\n", fmask
);
6598 if (alpha_procedure_type
== PT_REGISTER
)
6599 fprintf (file
, "\t.fp_save $%d\n", vms_save_fp_regno
);
6601 else if (!flag_inhibit_size_directive
)
6605 fprintf (file
, "\t.mask 0x%lx,", imask
);
6606 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6607 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
6610 for (i
= 0; i
< 32; ++i
)
6611 if (imask
& (1L << i
))
6617 fprintf (file
, "\t.fmask 0x%lx,", fmask
);
6618 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6619 frame_size
>= (1l << 31) ? 0 : reg_offset
- frame_size
);
6624 #if TARGET_ABI_OPEN_VMS
6625 /* Ifdef'ed cause readonly_section and link_section are only
6627 readonly_section ();
6628 fprintf (file
, "\t.align 3\n");
6629 assemble_name (file
, fnname
); fputs ("..na:\n", file
);
6630 fputs ("\t.ascii \"", file
);
6631 assemble_name (file
, fnname
);
6632 fputs ("\\0\"\n", file
);
6635 fprintf (file
, "\t.align 3\n");
6636 fputs ("\t.name ", file
);
6637 assemble_name (file
, fnname
);
6638 fputs ("..na\n", file
);
6639 ASM_OUTPUT_LABEL (file
, fnname
);
6640 fprintf (file
, "\t.pdesc ");
6641 assemble_name (file
, fnname
);
6642 fprintf (file
, "..en,%s\n",
6643 alpha_procedure_type
== PT_STACK
? "stack"
6644 : alpha_procedure_type
== PT_REGISTER
? "reg" : "null");
6645 alpha_need_linkage (fnname
, 1);
6650 /* Emit the .prologue note at the scheduled end of the prologue. */
6653 alpha_output_function_end_prologue (file
)
6656 if (TARGET_ABI_UNICOSMK
)
6658 else if (TARGET_ABI_OPEN_VMS
)
6659 fputs ("\t.prologue\n", file
);
6660 else if (TARGET_ABI_WINDOWS_NT
)
6661 fputs ("\t.prologue 0\n", file
);
6662 else if (!flag_inhibit_size_directive
)
6663 fprintf (file
, "\t.prologue %d\n",
6664 alpha_function_needs_gp
|| current_function_is_thunk
);
6667 /* Write function epilogue. */
6669 /* ??? At some point we will want to support full unwind, and so will
6670 need to mark the epilogue as well. At the moment, we just confuse
6673 #define FRP(exp) exp
6676 alpha_expand_epilogue ()
6678 /* Registers to save. */
6679 unsigned long imask
= 0;
6680 unsigned long fmask
= 0;
6681 /* Stack space needed for pushing registers clobbered by us. */
6682 HOST_WIDE_INT sa_size
;
6683 /* Complete stack size needed. */
6684 HOST_WIDE_INT frame_size
;
6685 /* Offset from base reg to register save area. */
6686 HOST_WIDE_INT reg_offset
;
6687 int fp_is_frame_pointer
, fp_offset
;
6688 rtx sa_reg
, sa_reg_exp
= NULL
;
6689 rtx sp_adj1
, sp_adj2
, mem
;
6693 sa_size
= alpha_sa_size ();
6695 frame_size
= get_frame_size ();
6696 if (TARGET_ABI_OPEN_VMS
)
6697 frame_size
= ALPHA_ROUND (sa_size
6698 + (alpha_procedure_type
== PT_STACK
? 8 : 0)
6700 + current_function_pretend_args_size
);
6701 else if (TARGET_ABI_UNICOSMK
)
6702 frame_size
= ALPHA_ROUND (sa_size
6703 + (alpha_procedure_type
== PT_STACK
? 48 : 0))
6704 + ALPHA_ROUND (frame_size
6705 + current_function_outgoing_args_size
);
6707 frame_size
= (ALPHA_ROUND (current_function_outgoing_args_size
)
6709 + ALPHA_ROUND (frame_size
6710 + current_function_pretend_args_size
));
6712 if (TARGET_ABI_OPEN_VMS
)
6714 if (alpha_procedure_type
== PT_STACK
)
6720 reg_offset
= ALPHA_ROUND (current_function_outgoing_args_size
);
6722 alpha_sa_mask (&imask
, &fmask
);
6725 = ((TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_STACK
)
6726 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
));
6728 sa_reg
= stack_pointer_rtx
;
6730 if (current_function_calls_eh_return
)
6731 eh_ofs
= EH_RETURN_STACKADJ_RTX
;
6735 if (!TARGET_ABI_UNICOSMK
&& sa_size
)
6737 /* If we have a frame pointer, restore SP from it. */
6738 if ((TARGET_ABI_OPEN_VMS
6739 && vms_unwind_regno
== HARD_FRAME_POINTER_REGNUM
)
6740 || (!TARGET_ABI_OPEN_VMS
&& frame_pointer_needed
))
6741 FRP (emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
));
6743 /* Cope with very large offsets to the register save area. */
6744 if (reg_offset
+ sa_size
> 0x8000)
6746 int low
= ((reg_offset
& 0xffff) ^ 0x8000) - 0x8000;
6749 if (low
+ sa_size
<= 0x8000)
6750 bias
= reg_offset
- low
, reg_offset
= low
;
6752 bias
= reg_offset
, reg_offset
= 0;
6754 sa_reg
= gen_rtx_REG (DImode
, 22);
6755 sa_reg_exp
= plus_constant (stack_pointer_rtx
, bias
);
6757 FRP (emit_move_insn (sa_reg
, sa_reg_exp
));
6760 /* Restore registers in order, excepting a true frame pointer. */
6762 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, reg_offset
));
6764 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6765 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
6768 imask
&= ~(1L << REG_RA
);
6770 for (i
= 0; i
< 32; ++i
)
6771 if (imask
& (1L << i
))
6773 if (i
== HARD_FRAME_POINTER_REGNUM
&& fp_is_frame_pointer
)
6774 fp_offset
= reg_offset
;
6777 mem
= gen_rtx_MEM (DImode
, plus_constant(sa_reg
, reg_offset
));
6778 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6779 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
6784 for (i
= 0; i
< 32; ++i
)
6785 if (fmask
& (1L << i
))
6787 mem
= gen_rtx_MEM (DFmode
, plus_constant(sa_reg
, reg_offset
));
6788 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6789 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
6793 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
== PT_STACK
)
6795 /* Restore callee-saved general-purpose registers. */
6799 for (i
= 9; i
< 15; i
++)
6800 if (imask
& (1L << i
))
6802 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
,
6804 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6805 FRP (emit_move_insn (gen_rtx_REG (DImode
, i
), mem
));
6809 for (i
= 2; i
< 10; i
++)
6810 if (fmask
& (1L << i
))
6812 mem
= gen_rtx_MEM (DFmode
, plus_constant(hard_frame_pointer_rtx
,
6814 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6815 FRP (emit_move_insn (gen_rtx_REG (DFmode
, i
+32), mem
));
6819 /* Restore the return address from the DSIB. */
6821 mem
= gen_rtx_MEM (DImode
, plus_constant(hard_frame_pointer_rtx
, -8));
6822 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6823 FRP (emit_move_insn (gen_rtx_REG (DImode
, REG_RA
), mem
));
6826 if (frame_size
|| eh_ofs
)
6828 sp_adj1
= stack_pointer_rtx
;
6832 sp_adj1
= gen_rtx_REG (DImode
, 23);
6833 emit_move_insn (sp_adj1
,
6834 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, eh_ofs
));
6837 /* If the stack size is large, begin computation into a temporary
6838 register so as not to interfere with a potential fp restore,
6839 which must be consecutive with an SP restore. */
6840 if (frame_size
< 32768
6841 && ! (TARGET_ABI_UNICOSMK
&& current_function_calls_alloca
))
6842 sp_adj2
= GEN_INT (frame_size
);
6843 else if (TARGET_ABI_UNICOSMK
)
6845 sp_adj1
= gen_rtx_REG (DImode
, 23);
6846 FRP (emit_move_insn (sp_adj1
, hard_frame_pointer_rtx
));
6847 sp_adj2
= const0_rtx
;
6849 else if (frame_size
< 0x40007fffL
)
6851 int low
= ((frame_size
& 0xffff) ^ 0x8000) - 0x8000;
6853 sp_adj2
= plus_constant (sp_adj1
, frame_size
- low
);
6854 if (sa_reg_exp
&& rtx_equal_p (sa_reg_exp
, sp_adj2
))
6858 sp_adj1
= gen_rtx_REG (DImode
, 23);
6859 FRP (emit_move_insn (sp_adj1
, sp_adj2
));
6861 sp_adj2
= GEN_INT (low
);
6865 rtx tmp
= gen_rtx_REG (DImode
, 23);
6866 FRP (sp_adj2
= alpha_emit_set_const (tmp
, DImode
, frame_size
, 3));
6869 /* We can't drop new things to memory this late, afaik,
6870 so build it up by pieces. */
6871 FRP (sp_adj2
= alpha_emit_set_long_const (tmp
, frame_size
,
6872 -(frame_size
< 0)));
6878 /* From now on, things must be in order. So emit blockages. */
6880 /* Restore the frame pointer. */
6881 if (TARGET_ABI_UNICOSMK
)
6883 emit_insn (gen_blockage ());
6884 mem
= gen_rtx_MEM (DImode
,
6885 plus_constant (hard_frame_pointer_rtx
, -16));
6886 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6887 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
6889 else if (fp_is_frame_pointer
)
6891 emit_insn (gen_blockage ());
6892 mem
= gen_rtx_MEM (DImode
, plus_constant (sa_reg
, fp_offset
));
6893 set_mem_alias_set (mem
, alpha_sr_alias_set
);
6894 FRP (emit_move_insn (hard_frame_pointer_rtx
, mem
));
6896 else if (TARGET_ABI_OPEN_VMS
)
6898 emit_insn (gen_blockage ());
6899 FRP (emit_move_insn (hard_frame_pointer_rtx
,
6900 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
6903 /* Restore the stack pointer. */
6904 emit_insn (gen_blockage ());
6905 if (sp_adj2
== const0_rtx
)
6906 FRP (emit_move_insn (stack_pointer_rtx
, sp_adj1
));
6908 FRP (emit_move_insn (stack_pointer_rtx
,
6909 gen_rtx_PLUS (DImode
, sp_adj1
, sp_adj2
)));
6913 if (TARGET_ABI_OPEN_VMS
&& alpha_procedure_type
== PT_REGISTER
)
6915 emit_insn (gen_blockage ());
6916 FRP (emit_move_insn (hard_frame_pointer_rtx
,
6917 gen_rtx_REG (DImode
, vms_save_fp_regno
)));
6919 else if (TARGET_ABI_UNICOSMK
&& alpha_procedure_type
!= PT_STACK
)
6921 /* Decrement the frame pointer if the function does not have a
6924 emit_insn (gen_blockage ());
6925 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
6926 hard_frame_pointer_rtx
, GEN_INT (-1))));
6931 /* Output the rest of the textual info surrounding the epilogue. */
6934 alpha_end_function (file
, fnname
, decl
)
6937 tree decl ATTRIBUTE_UNUSED
;
6939 /* End the function. */
6940 if (!TARGET_ABI_UNICOSMK
&& !flag_inhibit_size_directive
)
6942 fputs ("\t.end ", file
);
6943 assemble_name (file
, fnname
);
6946 inside_function
= FALSE
;
6948 /* Show that we know this function if it is called again.
6950 Don't do this for global functions in object files destined for a
6951 shared library because the function may be overridden by the application
6952 or other libraries. Similarly, don't do this for weak functions.
6954 Don't do this for functions not defined in the .text section, as
6955 otherwise it's not unlikely that the destination is out of range
6956 for a direct branch. */
6958 if (!DECL_WEAK (current_function_decl
)
6959 && (!flag_pic
|| !TREE_PUBLIC (current_function_decl
))
6960 && decl_in_text_section (current_function_decl
))
6961 SYMBOL_REF_FLAG (XEXP (DECL_RTL (current_function_decl
), 0)) = 1;
6963 /* Output jump tables and the static subroutine information block. */
6964 if (TARGET_ABI_UNICOSMK
)
6966 unicosmk_output_ssib (file
, fnname
);
6967 unicosmk_output_deferred_case_vectors (file
);
6971 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
6973 In order to avoid the hordes of differences between generated code
6974 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
6975 lots of code loading up large constants, generate rtl and emit it
6976 instead of going straight to text.
6978 Not sure why this idea hasn't been explored before... */
6981 alpha_output_mi_thunk_osf (file
, thunk_fndecl
, delta
, function
)
6983 tree thunk_fndecl ATTRIBUTE_UNUSED
;
6984 HOST_WIDE_INT delta
;
6987 HOST_WIDE_INT hi
, lo
;
6988 rtx
this, insn
, funexp
;
6990 /* We always require a valid GP. */
6991 emit_insn (gen_prologue_ldgp ());
6992 emit_note (NULL
, NOTE_INSN_PROLOGUE_END
);
6994 /* Find the "this" pointer. If the function returns a structure,
6995 the structure return pointer is in $16. */
6996 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
))))
6997 this = gen_rtx_REG (Pmode
, 17);
6999 this = gen_rtx_REG (Pmode
, 16);
7001 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7002 entire constant for the add. */
7003 lo
= ((delta
& 0xffff) ^ 0x8000) - 0x8000;
7004 hi
= (((delta
- lo
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7005 if (hi
+ lo
== delta
)
7008 emit_insn (gen_adddi3 (this, this, GEN_INT (hi
)));
7010 emit_insn (gen_adddi3 (this, this, GEN_INT (lo
)));
7014 rtx tmp
= alpha_emit_set_long_const (gen_rtx_REG (Pmode
, 0),
7015 delta
, -(delta
< 0));
7016 emit_insn (gen_adddi3 (this, this, tmp
));
7019 /* Generate a tail call to the target function. */
7020 if (! TREE_USED (function
))
7022 assemble_external (function
);
7023 TREE_USED (function
) = 1;
7025 funexp
= XEXP (DECL_RTL (function
), 0);
7026 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
7027 insn
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
));
7028 SIBLING_CALL_P (insn
) = 1;
7030 /* Run just enough of rest_of_compilation to get the insns emitted.
7031 There's not really enough bulk here to make other passes such as
7032 instruction scheduling worth while. Note that use_thunk calls
7033 assemble_start_function and assemble_end_function. */
7034 insn
= get_insns ();
7035 shorten_branches (insn
);
7036 final_start_function (insn
, file
, 1);
7037 final (insn
, file
, 1, 0);
7038 final_end_function ();
7041 /* Debugging support. */
7045 /* Count the number of sdb related labels are generated (to find block
7046 start and end boundaries). */
7048 int sdb_label_count
= 0;
7050 /* Next label # for each statement. */
7052 static int sym_lineno
= 0;
7054 /* Count the number of .file directives, so that .loc is up to date. */
7056 static int num_source_filenames
= 0;
7058 /* Name of the file containing the current function. */
7060 static const char *current_function_file
= "";
7062 /* Offsets to alpha virtual arg/local debugging pointers. */
7064 long alpha_arg_offset
;
7065 long alpha_auto_offset
;
7067 /* Emit a new filename to a stream. */
7070 alpha_output_filename (stream
, name
)
7074 static int first_time
= TRUE
;
7075 char ltext_label_name
[100];
7080 ++num_source_filenames
;
7081 current_function_file
= name
;
7082 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7083 output_quoted_string (stream
, name
);
7084 fprintf (stream
, "\n");
7085 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
7086 fprintf (stream
, "\t#@stabs\n");
7089 else if (write_symbols
== DBX_DEBUG
)
7091 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
7092 fprintf (stream
, "%s", ASM_STABS_OP
);
7093 output_quoted_string (stream
, name
);
7094 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
7097 else if (name
!= current_function_file
7098 && strcmp (name
, current_function_file
) != 0)
7100 if (inside_function
&& ! TARGET_GAS
)
7101 fprintf (stream
, "\t#.file\t%d ", num_source_filenames
);
7104 ++num_source_filenames
;
7105 current_function_file
= name
;
7106 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7109 output_quoted_string (stream
, name
);
7110 fprintf (stream
, "\n");
7114 /* Emit a linenumber to a stream. */
7117 alpha_output_lineno (stream
, line
)
7121 if (write_symbols
== DBX_DEBUG
)
7123 /* mips-tfile doesn't understand .stabd directives. */
7125 fprintf (stream
, "$LM%d:\n%s%d,0,%d,$LM%d\n",
7126 sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
, sym_lineno
);
7129 fprintf (stream
, "\n\t.loc\t%d %d\n", num_source_filenames
, line
);
7132 /* Structure to show the current status of registers and memory. */
7134 struct shadow_summary
7137 unsigned int i
: 31; /* Mask of int regs */
7138 unsigned int fp
: 31; /* Mask of fp regs */
7139 unsigned int mem
: 1; /* mem == imem | fpmem */
7143 static void summarize_insn
PARAMS ((rtx
, struct shadow_summary
*, int));
7144 static void alpha_handle_trap_shadows
PARAMS ((rtx
));
7146 /* Summary the effects of expression X on the machine. Update SUM, a pointer
7147 to the summary structure. SET is nonzero if the insn is setting the
7148 object, otherwise zero. */
7151 summarize_insn (x
, sum
, set
)
7153 struct shadow_summary
*sum
;
7156 const char *format_ptr
;
7162 switch (GET_CODE (x
))
7164 /* ??? Note that this case would be incorrect if the Alpha had a
7165 ZERO_EXTRACT in SET_DEST. */
7167 summarize_insn (SET_SRC (x
), sum
, 0);
7168 summarize_insn (SET_DEST (x
), sum
, 1);
7172 summarize_insn (XEXP (x
, 0), sum
, 1);
7176 summarize_insn (XEXP (x
, 0), sum
, 0);
7180 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; i
--)
7181 summarize_insn (ASM_OPERANDS_INPUT (x
, i
), sum
, 0);
7185 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
7186 summarize_insn (XVECEXP (x
, 0, i
), sum
, 0);
7190 summarize_insn (SUBREG_REG (x
), sum
, 0);
7195 int regno
= REGNO (x
);
7196 unsigned long mask
= ((unsigned long) 1) << (regno
% 32);
7198 if (regno
== 31 || regno
== 63)
7204 sum
->defd
.i
|= mask
;
7206 sum
->defd
.fp
|= mask
;
7211 sum
->used
.i
|= mask
;
7213 sum
->used
.fp
|= mask
;
7224 /* Find the regs used in memory address computation: */
7225 summarize_insn (XEXP (x
, 0), sum
, 0);
7228 case CONST_INT
: case CONST_DOUBLE
:
7229 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
7230 case SCRATCH
: case ASM_INPUT
:
7233 /* Handle common unary and binary ops for efficiency. */
7234 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
7235 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
7236 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
7237 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
7238 case NE
: case EQ
: case GE
: case GT
: case LE
:
7239 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
7240 summarize_insn (XEXP (x
, 0), sum
, 0);
7241 summarize_insn (XEXP (x
, 1), sum
, 0);
7244 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
7245 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
7246 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
7247 case SQRT
: case FFS
:
7248 summarize_insn (XEXP (x
, 0), sum
, 0);
7252 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
7253 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
7254 switch (format_ptr
[i
])
7257 summarize_insn (XEXP (x
, i
), sum
, 0);
7261 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7262 summarize_insn (XVECEXP (x
, i
, j
), sum
, 0);
7274 /* Ensure a sufficient number of `trapb' insns are in the code when
7275 the user requests code with a trap precision of functions or
7278 In naive mode, when the user requests a trap-precision of
7279 "instruction", a trapb is needed after every instruction that may
7280 generate a trap. This ensures that the code is resumption safe but
7283 When optimizations are turned on, we delay issuing a trapb as long
7284 as possible. In this context, a trap shadow is the sequence of
7285 instructions that starts with a (potentially) trap generating
7286 instruction and extends to the next trapb or call_pal instruction
7287 (but GCC never generates call_pal by itself). We can delay (and
7288 therefore sometimes omit) a trapb subject to the following
7291 (a) On entry to the trap shadow, if any Alpha register or memory
7292 location contains a value that is used as an operand value by some
7293 instruction in the trap shadow (live on entry), then no instruction
7294 in the trap shadow may modify the register or memory location.
7296 (b) Within the trap shadow, the computation of the base register
7297 for a memory load or store instruction may not involve using the
7298 result of an instruction that might generate an UNPREDICTABLE
7301 (c) Within the trap shadow, no register may be used more than once
7302 as a destination register. (This is to make life easier for the
7305 (d) The trap shadow may not include any branch instructions. */
7308 alpha_handle_trap_shadows (insns
)
7311 struct shadow_summary shadow
;
7312 int trap_pending
, exception_nesting
;
7316 exception_nesting
= 0;
7319 shadow
.used
.mem
= 0;
7320 shadow
.defd
= shadow
.used
;
7322 for (i
= insns
; i
; i
= NEXT_INSN (i
))
7324 if (GET_CODE (i
) == NOTE
)
7326 switch (NOTE_LINE_NUMBER (i
))
7328 case NOTE_INSN_EH_REGION_BEG
:
7329 exception_nesting
++;
7334 case NOTE_INSN_EH_REGION_END
:
7335 exception_nesting
--;
7340 case NOTE_INSN_EPILOGUE_BEG
:
7341 if (trap_pending
&& alpha_tp
>= ALPHA_TP_FUNC
)
7346 else if (trap_pending
)
7348 if (alpha_tp
== ALPHA_TP_FUNC
)
7350 if (GET_CODE (i
) == JUMP_INSN
7351 && GET_CODE (PATTERN (i
)) == RETURN
)
7354 else if (alpha_tp
== ALPHA_TP_INSN
)
7358 struct shadow_summary sum
;
7363 sum
.defd
= sum
.used
;
7365 switch (GET_CODE (i
))
7368 /* Annoyingly, get_attr_trap will abort on these. */
7369 if (GET_CODE (PATTERN (i
)) == USE
7370 || GET_CODE (PATTERN (i
)) == CLOBBER
)
7373 summarize_insn (PATTERN (i
), &sum
, 0);
7375 if ((sum
.defd
.i
& shadow
.defd
.i
)
7376 || (sum
.defd
.fp
& shadow
.defd
.fp
))
7378 /* (c) would be violated */
7382 /* Combine shadow with summary of current insn: */
7383 shadow
.used
.i
|= sum
.used
.i
;
7384 shadow
.used
.fp
|= sum
.used
.fp
;
7385 shadow
.used
.mem
|= sum
.used
.mem
;
7386 shadow
.defd
.i
|= sum
.defd
.i
;
7387 shadow
.defd
.fp
|= sum
.defd
.fp
;
7388 shadow
.defd
.mem
|= sum
.defd
.mem
;
7390 if ((sum
.defd
.i
& shadow
.used
.i
)
7391 || (sum
.defd
.fp
& shadow
.used
.fp
)
7392 || (sum
.defd
.mem
& shadow
.used
.mem
))
7394 /* (a) would be violated (also takes care of (b)) */
7395 if (get_attr_trap (i
) == TRAP_YES
7396 && ((sum
.defd
.i
& sum
.used
.i
)
7397 || (sum
.defd
.fp
& sum
.used
.fp
)))
7416 n
= emit_insn_before (gen_trapb (), i
);
7417 PUT_MODE (n
, TImode
);
7418 PUT_MODE (i
, TImode
);
7422 shadow
.used
.mem
= 0;
7423 shadow
.defd
= shadow
.used
;
7428 if ((exception_nesting
> 0 || alpha_tp
>= ALPHA_TP_FUNC
)
7429 && GET_CODE (i
) == INSN
7430 && GET_CODE (PATTERN (i
)) != USE
7431 && GET_CODE (PATTERN (i
)) != CLOBBER
7432 && get_attr_trap (i
) == TRAP_YES
)
7434 if (optimize
&& !trap_pending
)
7435 summarize_insn (PATTERN (i
), &shadow
, 0);
7441 /* Alpha can only issue instruction groups simultaneously if they are
7442 suitibly aligned. This is very processor-specific. */
7444 enum alphaev4_pipe
{
7451 enum alphaev5_pipe
{
7462 static enum alphaev4_pipe alphaev4_insn_pipe
PARAMS ((rtx
));
7463 static enum alphaev5_pipe alphaev5_insn_pipe
PARAMS ((rtx
));
7464 static rtx alphaev4_next_group
PARAMS ((rtx
, int *, int *));
7465 static rtx alphaev5_next_group
PARAMS ((rtx
, int *, int *));
7466 static rtx alphaev4_next_nop
PARAMS ((int *));
7467 static rtx alphaev5_next_nop
PARAMS ((int *));
7469 static void alpha_align_insns
7470 PARAMS ((rtx
, unsigned int, rtx (*)(rtx
, int *, int *), rtx (*)(int *)));
7472 static enum alphaev4_pipe
7473 alphaev4_insn_pipe (insn
)
7476 if (recog_memoized (insn
) < 0)
7478 if (get_attr_length (insn
) != 4)
7481 switch (get_attr_type (insn
))
7514 static enum alphaev5_pipe
7515 alphaev5_insn_pipe (insn
)
7518 if (recog_memoized (insn
) < 0)
7520 if (get_attr_length (insn
) != 4)
7523 switch (get_attr_type (insn
))
7563 /* IN_USE is a mask of the slots currently filled within the insn group.
7564 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
7565 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
7567 LEN is, of course, the length of the group in bytes. */
7570 alphaev4_next_group (insn
, pin_use
, plen
)
7572 int *pin_use
, *plen
;
7579 || GET_CODE (PATTERN (insn
)) == CLOBBER
7580 || GET_CODE (PATTERN (insn
)) == USE
)
7585 enum alphaev4_pipe pipe
;
7587 pipe
= alphaev4_insn_pipe (insn
);
7591 /* Force complex instructions to start new groups. */
7595 /* If this is a completely unrecognized insn, its an asm.
7596 We don't know how long it is, so record length as -1 to
7597 signal a needed realignment. */
7598 if (recog_memoized (insn
) < 0)
7601 len
= get_attr_length (insn
);
7605 if (in_use
& EV4_IB0
)
7607 if (in_use
& EV4_IB1
)
7612 in_use
|= EV4_IB0
| EV4_IBX
;
7616 if (in_use
& EV4_IB0
)
7618 if (!(in_use
& EV4_IBX
) || (in_use
& EV4_IB1
))
7626 if (in_use
& EV4_IB1
)
7636 /* Haifa doesn't do well scheduling branches. */
7637 if (GET_CODE (insn
) == JUMP_INSN
)
7641 insn
= next_nonnote_insn (insn
);
7643 if (!insn
|| ! INSN_P (insn
))
7646 /* Let Haifa tell us where it thinks insn group boundaries are. */
7647 if (GET_MODE (insn
) == TImode
)
7650 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
7655 insn
= next_nonnote_insn (insn
);
7663 /* IN_USE is a mask of the slots currently filled within the insn group.
7664 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
7665 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
7667 LEN is, of course, the length of the group in bytes. */
7670 alphaev5_next_group (insn
, pin_use
, plen
)
7672 int *pin_use
, *plen
;
7679 || GET_CODE (PATTERN (insn
)) == CLOBBER
7680 || GET_CODE (PATTERN (insn
)) == USE
)
7685 enum alphaev5_pipe pipe
;
7687 pipe
= alphaev5_insn_pipe (insn
);
7691 /* Force complex instructions to start new groups. */
7695 /* If this is a completely unrecognized insn, its an asm.
7696 We don't know how long it is, so record length as -1 to
7697 signal a needed realignment. */
7698 if (recog_memoized (insn
) < 0)
7701 len
= get_attr_length (insn
);
7704 /* ??? Most of the places below, we would like to abort, as
7705 it would indicate an error either in Haifa, or in the
7706 scheduling description. Unfortunately, Haifa never
7707 schedules the last instruction of the BB, so we don't
7708 have an accurate TI bit to go off. */
7710 if (in_use
& EV5_E0
)
7712 if (in_use
& EV5_E1
)
7717 in_use
|= EV5_E0
| EV5_E01
;
7721 if (in_use
& EV5_E0
)
7723 if (!(in_use
& EV5_E01
) || (in_use
& EV5_E1
))
7731 if (in_use
& EV5_E1
)
7737 if (in_use
& EV5_FA
)
7739 if (in_use
& EV5_FM
)
7744 in_use
|= EV5_FA
| EV5_FAM
;
7748 if (in_use
& EV5_FA
)
7754 if (in_use
& EV5_FM
)
7767 /* Haifa doesn't do well scheduling branches. */
7768 /* ??? If this is predicted not-taken, slotting continues, except
7769 that no more IBR, FBR, or JSR insns may be slotted. */
7770 if (GET_CODE (insn
) == JUMP_INSN
)
7774 insn
= next_nonnote_insn (insn
);
7776 if (!insn
|| ! INSN_P (insn
))
7779 /* Let Haifa tell us where it thinks insn group boundaries are. */
7780 if (GET_MODE (insn
) == TImode
)
7783 if (GET_CODE (insn
) == CLOBBER
|| GET_CODE (insn
) == USE
)
7788 insn
= next_nonnote_insn (insn
);
7797 alphaev4_next_nop (pin_use
)
7800 int in_use
= *pin_use
;
7803 if (!(in_use
& EV4_IB0
))
7808 else if ((in_use
& (EV4_IBX
|EV4_IB1
)) == EV4_IBX
)
7813 else if (TARGET_FP
&& !(in_use
& EV4_IB1
))
7826 alphaev5_next_nop (pin_use
)
7829 int in_use
= *pin_use
;
7832 if (!(in_use
& EV5_E1
))
7837 else if (TARGET_FP
&& !(in_use
& EV5_FA
))
7842 else if (TARGET_FP
&& !(in_use
& EV5_FM
))
7854 /* The instruction group alignment main loop. */
7857 alpha_align_insns (insns
, max_align
, next_group
, next_nop
)
7859 unsigned int max_align
;
7860 rtx (*next_group
) PARAMS ((rtx
, int *, int *));
7861 rtx (*next_nop
) PARAMS ((int *));
7863 /* ALIGN is the known alignment for the insn group. */
7865 /* OFS is the offset of the current insn in the insn group. */
7867 int prev_in_use
, in_use
, len
;
7870 /* Let shorten branches care for assigning alignments to code labels. */
7871 shorten_branches (insns
);
7873 if (align_functions
< 4)
7875 else if ((unsigned int) align_functions
< max_align
)
7876 align
= align_functions
;
7880 ofs
= prev_in_use
= 0;
7882 if (GET_CODE (i
) == NOTE
)
7883 i
= next_nonnote_insn (i
);
7887 next
= (*next_group
) (i
, &in_use
, &len
);
7889 /* When we see a label, resync alignment etc. */
7890 if (GET_CODE (i
) == CODE_LABEL
)
7892 unsigned int new_align
= 1 << label_to_alignment (i
);
7894 if (new_align
>= align
)
7896 align
= new_align
< max_align
? new_align
: max_align
;
7900 else if (ofs
& (new_align
-1))
7901 ofs
= (ofs
| (new_align
-1)) + 1;
7906 /* Handle complex instructions special. */
7907 else if (in_use
== 0)
7909 /* Asms will have length < 0. This is a signal that we have
7910 lost alignment knowledge. Assume, however, that the asm
7911 will not mis-align instructions. */
7920 /* If the known alignment is smaller than the recognized insn group,
7921 realign the output. */
7922 else if ((int) align
< len
)
7924 unsigned int new_log_align
= len
> 8 ? 4 : 3;
7927 where
= prev
= prev_nonnote_insn (i
);
7928 if (!where
|| GET_CODE (where
) != CODE_LABEL
)
7931 /* Can't realign between a call and its gp reload. */
7932 if (! (TARGET_EXPLICIT_RELOCS
7933 && prev
&& GET_CODE (prev
) == CALL_INSN
))
7935 emit_insn_before (gen_realign (GEN_INT (new_log_align
)), where
);
7936 align
= 1 << new_log_align
;
7941 /* If the group won't fit in the same INT16 as the previous,
7942 we need to add padding to keep the group together. Rather
7943 than simply leaving the insn filling to the assembler, we
7944 can make use of the knowledge of what sorts of instructions
7945 were issued in the previous group to make sure that all of
7946 the added nops are really free. */
7947 else if (ofs
+ len
> (int) align
)
7949 int nop_count
= (align
- ofs
) / 4;
7952 /* Insert nops before labels, branches, and calls to truely merge
7953 the execution of the nops with the previous instruction group. */
7954 where
= prev_nonnote_insn (i
);
7957 if (GET_CODE (where
) == CODE_LABEL
)
7959 rtx where2
= prev_nonnote_insn (where
);
7960 if (where2
&& GET_CODE (where2
) == JUMP_INSN
)
7963 else if (GET_CODE (where
) == INSN
)
7970 emit_insn_before ((*next_nop
)(&prev_in_use
), where
);
7971 while (--nop_count
);
7975 ofs
= (ofs
+ len
) & (align
- 1);
7976 prev_in_use
= in_use
;
7981 /* Machine dependent reorg pass. */
7987 if (alpha_tp
!= ALPHA_TP_PROG
|| flag_exceptions
)
7988 alpha_handle_trap_shadows (insns
);
7990 /* Due to the number of extra trapb insns, don't bother fixing up
7991 alignment when trap precision is instruction. Moreover, we can
7992 only do our job when sched2 is run. */
7993 if (optimize
&& !optimize_size
7994 && alpha_tp
!= ALPHA_TP_INSN
7995 && flag_schedule_insns_after_reload
)
7997 if (alpha_cpu
== PROCESSOR_EV4
)
7998 alpha_align_insns (insns
, 8, alphaev4_next_group
, alphaev4_next_nop
);
7999 else if (alpha_cpu
== PROCESSOR_EV5
)
8000 alpha_align_insns (insns
, 16, alphaev5_next_group
, alphaev5_next_nop
);
8004 /* Check a floating-point value for validity for a particular machine mode. */
8006 static const char * const float_strings
[] =
8008 /* These are for FLOAT_VAX. */
8009 "1.70141173319264430e+38", /* 2^127 (2^24 - 1) / 2^24 */
8010 "-1.70141173319264430e+38",
8011 "2.93873587705571877e-39", /* 2^-128 */
8012 "-2.93873587705571877e-39",
8013 /* These are for the default broken IEEE mode, which traps
8014 on infinity or denormal numbers. */
8015 "3.402823466385288598117e+38", /* 2^128 (1 - 2^-24) */
8016 "-3.402823466385288598117e+38",
8017 "1.1754943508222875079687e-38", /* 2^-126 */
8018 "-1.1754943508222875079687e-38",
8021 static REAL_VALUE_TYPE float_values
[8];
8022 static int inited_float_values
= 0;
8025 check_float_value (mode
, d
, overflow
)
8026 enum machine_mode mode
;
8028 int overflow ATTRIBUTE_UNUSED
;
8031 if (TARGET_IEEE
|| TARGET_IEEE_CONFORMANT
|| TARGET_IEEE_WITH_INEXACT
)
8034 if (inited_float_values
== 0)
8037 for (i
= 0; i
< 8; i
++)
8038 float_values
[i
] = REAL_VALUE_ATOF (float_strings
[i
], DFmode
);
8040 inited_float_values
= 1;
8046 REAL_VALUE_TYPE
*fvptr
;
8048 if (TARGET_FLOAT_VAX
)
8049 fvptr
= &float_values
[0];
8051 fvptr
= &float_values
[4];
8053 memcpy (&r
, d
, sizeof (REAL_VALUE_TYPE
));
8054 if (REAL_VALUES_LESS (fvptr
[0], r
))
8056 memcpy (d
, &fvptr
[0], sizeof (REAL_VALUE_TYPE
));
8059 else if (REAL_VALUES_LESS (r
, fvptr
[1]))
8061 memcpy (d
, &fvptr
[1], sizeof (REAL_VALUE_TYPE
));
8064 else if (REAL_VALUES_LESS (dconst0
, r
)
8065 && REAL_VALUES_LESS (r
, fvptr
[2]))
8067 memcpy (d
, &dconst0
, sizeof (REAL_VALUE_TYPE
));
8070 else if (REAL_VALUES_LESS (r
, dconst0
)
8071 && REAL_VALUES_LESS (fvptr
[3], r
))
8073 memcpy (d
, &dconst0
, sizeof (REAL_VALUE_TYPE
));
8081 #if TARGET_ABI_OPEN_VMS
8083 /* Return the VMS argument type corresponding to MODE. */
8086 alpha_arg_type (mode
)
8087 enum machine_mode mode
;
8092 return TARGET_FLOAT_VAX
? FF
: FS
;
8094 return TARGET_FLOAT_VAX
? FD
: FT
;
8100 /* Return an rtx for an integer representing the VMS Argument Information
8104 alpha_arg_info_reg_val (cum
)
8105 CUMULATIVE_ARGS cum
;
8107 unsigned HOST_WIDE_INT regval
= cum
.num_args
;
8110 for (i
= 0; i
< 6; i
++)
8111 regval
|= ((int) cum
.atypes
[i
]) << (i
* 3 + 8);
8113 return GEN_INT (regval
);
8116 #include <splay-tree.h>
8118 /* Structure to collect function names for final output
8121 enum links_kind
{KIND_UNUSED
, KIND_LOCAL
, KIND_EXTERN
};
8126 enum links_kind kind
;
8129 static splay_tree alpha_links
;
8131 static int mark_alpha_links_node
PARAMS ((splay_tree_node
, void *));
8132 static void mark_alpha_links
PARAMS ((void *));
8133 static int alpha_write_one_linkage
PARAMS ((splay_tree_node
, void *));
8135 /* Protect alpha_links from garbage collection. */
8138 mark_alpha_links_node (node
, data
)
8139 splay_tree_node node
;
8140 void *data ATTRIBUTE_UNUSED
;
8142 struct alpha_links
*links
= (struct alpha_links
*) node
->value
;
8143 ggc_mark_rtx (links
->linkage
);
8148 mark_alpha_links (ptr
)
8151 splay_tree tree
= *(splay_tree
*) ptr
;
8152 splay_tree_foreach (tree
, mark_alpha_links_node
, NULL
);
8155 /* Make (or fake) .linkage entry for function call.
8157 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
8159 Return an SYMBOL_REF rtx for the linkage. */
8162 alpha_need_linkage (name
, is_local
)
8166 splay_tree_node node
;
8167 struct alpha_links
*al
;
8174 /* Is this name already defined? */
8176 node
= splay_tree_lookup (alpha_links
, (splay_tree_key
) name
);
8179 al
= (struct alpha_links
*) node
->value
;
8182 /* Defined here but external assumed. */
8183 if (al
->kind
== KIND_EXTERN
)
8184 al
->kind
= KIND_LOCAL
;
8188 /* Used here but unused assumed. */
8189 if (al
->kind
== KIND_UNUSED
)
8190 al
->kind
= KIND_LOCAL
;
8197 alpha_links
= splay_tree_new ((splay_tree_compare_fn
) strcmp
,
8198 (splay_tree_delete_key_fn
) free
,
8199 (splay_tree_delete_key_fn
) free
);
8200 ggc_add_root (&alpha_links
, 1, 1, mark_alpha_links
);
8203 al
= (struct alpha_links
*) xmalloc (sizeof (struct alpha_links
));
8204 name
= xstrdup (name
);
8206 /* Assume external if no definition. */
8207 al
->kind
= (is_local
? KIND_UNUSED
: KIND_EXTERN
);
8209 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
8210 get_identifier (name
);
8212 /* Construct a SYMBOL_REF for us to call. */
8214 size_t name_len
= strlen (name
);
8215 char *linksym
= alloca (name_len
+ 6);
8217 memcpy (linksym
+ 1, name
, name_len
);
8218 memcpy (linksym
+ 1 + name_len
, "..lk", 5);
8219 al
->linkage
= gen_rtx_SYMBOL_REF (Pmode
,
8220 ggc_alloc_string (linksym
, name_len
+ 5));
8223 splay_tree_insert (alpha_links
, (splay_tree_key
) name
,
8224 (splay_tree_value
) al
);
8230 alpha_write_one_linkage (node
, data
)
8231 splay_tree_node node
;
8234 const char *const name
= (const char *) node
->key
;
8235 struct alpha_links
*links
= (struct alpha_links
*) node
->value
;
8236 FILE *stream
= (FILE *) data
;
8238 if (links
->kind
== KIND_UNUSED
8239 || ! TREE_SYMBOL_REFERENCED (get_identifier (name
)))
8242 fprintf (stream
, "$%s..lk:\n", name
);
8243 if (links
->kind
== KIND_LOCAL
)
8245 /* Local and used, build linkage pair. */
8246 fprintf (stream
, "\t.quad %s..en\n", name
);
8247 fprintf (stream
, "\t.quad %s\n", name
);
8251 /* External and used, request linkage pair. */
8252 fprintf (stream
, "\t.linkage %s\n", name
);
8259 alpha_write_linkage (stream
)
8264 readonly_section ();
8265 fprintf (stream
, "\t.align 3\n");
8266 splay_tree_foreach (alpha_links
, alpha_write_one_linkage
, stream
);
8270 /* Given a decl, a section name, and whether the decl initializer
8271 has relocs, choose attributes for the section. */
8273 #define SECTION_VMS_OVERLAY SECTION_FORGET
8274 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
8275 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
8278 vms_section_type_flags (decl
, name
, reloc
)
8283 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
8285 if (decl
&& DECL_ATTRIBUTES (decl
)
8286 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl
)))
8287 flags
|= SECTION_VMS_OVERLAY
;
8288 if (decl
&& DECL_ATTRIBUTES (decl
)
8289 && lookup_attribute ("global", DECL_ATTRIBUTES (decl
)))
8290 flags
|= SECTION_VMS_GLOBAL
;
8291 if (decl
&& DECL_ATTRIBUTES (decl
)
8292 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl
)))
8293 flags
|= SECTION_VMS_INITIALIZE
;
8298 /* Switch to an arbitrary section NAME with attributes as specified
8299 by FLAGS. ALIGN specifies any known alignment requirements for
8300 the section; 0 if the default should be used. */
8303 vms_asm_named_section (name
, flags
)
8307 fputc ('\n', asm_out_file
);
8308 fprintf (asm_out_file
, ".section\t%s", name
);
8310 if (flags
& SECTION_VMS_OVERLAY
)
8311 fprintf (asm_out_file
, ",OVR");
8312 if (flags
& SECTION_VMS_GLOBAL
)
8313 fprintf (asm_out_file
, ",GBL");
8314 if (flags
& SECTION_VMS_INITIALIZE
)
8315 fprintf (asm_out_file
, ",NOMOD");
8316 if (flags
& SECTION_DEBUG
)
8317 fprintf (asm_out_file
, ",NOWRT");
8319 fputc ('\n', asm_out_file
);
8322 /* Record an element in the table of global constructors. SYMBOL is
8323 a SYMBOL_REF of the function to be called; PRIORITY is a number
8324 between 0 and MAX_INIT_PRIORITY.
8326 Differs from default_ctors_section_asm_out_constructor in that the
8327 width of the .ctors entry is always 64 bits, rather than the 32 bits
8328 used by a normal pointer. */
8331 vms_asm_out_constructor (symbol
, priority
)
8333 int priority ATTRIBUTE_UNUSED
;
8336 assemble_align (BITS_PER_WORD
);
8337 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
8341 vms_asm_out_destructor (symbol
, priority
)
8343 int priority ATTRIBUTE_UNUSED
;
8346 assemble_align (BITS_PER_WORD
);
8347 assemble_integer (symbol
, UNITS_PER_WORD
, BITS_PER_WORD
, 1);
8352 alpha_need_linkage (name
, is_local
)
8353 const char *name ATTRIBUTE_UNUSED
;
8354 int is_local ATTRIBUTE_UNUSED
;
8359 #endif /* TARGET_ABI_OPEN_VMS */
8361 #if TARGET_ABI_UNICOSMK
8363 static void unicosmk_output_module_name
PARAMS ((FILE *));
8364 static void unicosmk_output_default_externs
PARAMS ((FILE *));
8365 static void unicosmk_output_dex
PARAMS ((FILE *));
8366 static void unicosmk_output_externs
PARAMS ((FILE *));
8367 static void unicosmk_output_addr_vec
PARAMS ((FILE *, rtx
));
8368 static const char *unicosmk_ssib_name
PARAMS ((void));
8369 static int unicosmk_special_name
PARAMS ((const char *));
8371 /* Define the offset between two registers, one to be eliminated, and the
8372 other its replacement, at the start of a routine. */
8375 unicosmk_initial_elimination_offset (from
, to
)
8381 fixed_size
= alpha_sa_size();
8382 if (fixed_size
!= 0)
8385 if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
8387 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
8389 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
8390 return (ALPHA_ROUND (current_function_outgoing_args_size
)
8391 + ALPHA_ROUND (get_frame_size()));
8392 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
8393 return (ALPHA_ROUND (fixed_size
)
8394 + ALPHA_ROUND (get_frame_size()
8395 + current_function_outgoing_args_size
));
8400 /* Output the module name for .ident and .end directives. We have to strip
8401 directories and add make sure that the module name starts with a letter
8405 unicosmk_output_module_name (file
)
8410 /* Strip directories. */
8412 name
= strrchr (main_input_filename
, '/');
8416 name
= main_input_filename
;
8418 /* CAM only accepts module names that start with a letter or '$'. We
8419 prefix the module name with a '$' if necessary. */
8421 if (!ISALPHA (*name
))
8422 fprintf (file
, "$%s", name
);
8427 /* Output text that to appear at the beginning of an assembler file. */
8430 unicosmk_asm_file_start (file
)
8435 fputs ("\t.ident\t", file
);
8436 unicosmk_output_module_name (file
);
8437 fputs ("\n\n", file
);
8439 /* The Unicos/Mk assembler uses different register names. Instead of trying
8440 to support them, we simply use micro definitions. */
8442 /* CAM has different register names: rN for the integer register N and fN
8443 for the floating-point register N. Instead of trying to use these in
8444 alpha.md, we define the symbols $N and $fN to refer to the appropriate
8447 for (i
= 0; i
< 32; ++i
)
8448 fprintf (file
, "$%d <- r%d\n", i
, i
);
8450 for (i
= 0; i
< 32; ++i
)
8451 fprintf (file
, "$f%d <- f%d\n", i
, i
);
8455 /* The .align directive fill unused space with zeroes which does not work
8456 in code sections. We define the macro 'gcc@code@align' which uses nops
8457 instead. Note that it assumes that code sections always have the
8458 biggest possible alignment since . refers to the current offset from
8459 the beginning of the section. */
8461 fputs ("\t.macro gcc@code@align n\n", file
);
8462 fputs ("gcc@n@bytes = 1 << n\n", file
);
8463 fputs ("gcc@here = . % gcc@n@bytes\n", file
);
8464 fputs ("\t.if ne, gcc@here, 0\n", file
);
8465 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", file
);
8466 fputs ("\tbis r31,r31,r31\n", file
);
8467 fputs ("\t.endr\n", file
);
8468 fputs ("\t.endif\n", file
);
8469 fputs ("\t.endm gcc@code@align\n\n", file
);
8471 /* Output extern declarations which should always be visible. */
8472 unicosmk_output_default_externs (file
);
8474 /* Open a dummy section. We always need to be inside a section for the
8475 section-switching code to work correctly.
8476 ??? This should be a module id or something like that. I still have to
8477 figure out what the rules for those are. */
8478 fputs ("\n\t.psect\t$SG00000,data\n", file
);
8481 /* Output text to appear at the end of an assembler file. This includes all
8482 pending extern declarations and DEX expressions. */
8485 unicosmk_asm_file_end (file
)
8488 fputs ("\t.endp\n\n", file
);
8490 /* Output all pending externs. */
8492 unicosmk_output_externs (file
);
8494 /* Output dex definitions used for functions whose names conflict with
8497 unicosmk_output_dex (file
);
8499 fputs ("\t.end\t", file
);
8500 unicosmk_output_module_name (file
);
8504 /* Output the definition of a common variable. */
8507 unicosmk_output_common (file
, name
, size
, align
)
8514 printf ("T3E__: common %s\n", name
);
8517 fputs("\t.endp\n\n\t.psect ", file
);
8518 assemble_name(file
, name
);
8519 fprintf(file
, ",%d,common\n", floor_log2 (align
/ BITS_PER_UNIT
));
8520 fprintf(file
, "\t.byte\t0:%d\n", size
);
8522 /* Mark the symbol as defined in this module. */
8523 name_tree
= get_identifier (name
);
8524 TREE_ASM_WRITTEN (name_tree
) = 1;
8527 #define SECTION_PUBLIC SECTION_MACH_DEP
8528 #define SECTION_MAIN (SECTION_PUBLIC << 1)
8529 static int current_section_align
;
8532 unicosmk_section_type_flags (decl
, name
, reloc
)
8535 int reloc ATTRIBUTE_UNUSED
;
8537 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
8542 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8544 current_section_align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
8545 if (align_functions_log
> current_section_align
)
8546 current_section_align
= align_functions_log
;
8548 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
)), "main"))
8549 flags
|= SECTION_MAIN
;
8552 current_section_align
= floor_log2 (DECL_ALIGN (decl
) / BITS_PER_UNIT
);
8554 if (TREE_PUBLIC (decl
))
8555 flags
|= SECTION_PUBLIC
;
8560 /* Generate a section name for decl and associate it with the
8564 unicosmk_unique_section (decl
, reloc
)
8566 int reloc ATTRIBUTE_UNUSED
;
8574 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
8575 STRIP_NAME_ENCODING (name
, name
);
8576 len
= strlen (name
);
8578 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8582 /* It is essential that we prefix the section name here because
8583 otherwise the section names generated for constructors and
8584 destructors confuse collect2. */
8586 string
= alloca (len
+ 6);
8587 sprintf (string
, "code@%s", name
);
8588 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
8590 else if (TREE_PUBLIC (decl
))
8591 DECL_SECTION_NAME (decl
) = build_string (len
, name
);
8596 string
= alloca (len
+ 6);
8597 sprintf (string
, "data@%s", name
);
8598 DECL_SECTION_NAME (decl
) = build_string (len
+ 5, string
);
8602 /* Switch to an arbitrary section NAME with attributes as specified
8603 by FLAGS. ALIGN specifies any known alignment requirements for
8604 the section; 0 if the default should be used. */
8607 unicosmk_asm_named_section (name
, flags
)
8613 /* Close the previous section. */
8615 fputs ("\t.endp\n\n", asm_out_file
);
8617 /* Find out what kind of section we are opening. */
8619 if (flags
& SECTION_MAIN
)
8620 fputs ("\t.start\tmain\n", asm_out_file
);
8622 if (flags
& SECTION_CODE
)
8624 else if (flags
& SECTION_PUBLIC
)
8629 if (current_section_align
!= 0)
8630 fprintf (asm_out_file
, "\t.psect\t%s,%d,%s\n", name
,
8631 current_section_align
, kind
);
8633 fprintf (asm_out_file
, "\t.psect\t%s,%s\n", name
, kind
);
8637 unicosmk_insert_attributes (decl
, attr_ptr
)
8639 tree
*attr_ptr ATTRIBUTE_UNUSED
;
8642 && (TREE_PUBLIC (decl
) || TREE_CODE (decl
) == FUNCTION_DECL
))
8643 UNIQUE_SECTION (decl
, 0);
8646 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
8647 in code sections because .align fill unused space with zeroes. */
8650 unicosmk_output_align (file
, align
)
8654 if (inside_function
)
8655 fprintf (file
, "\tgcc@code@align\t%d\n", align
);
8657 fprintf (file
, "\t.align\t%d\n", align
);
8660 /* Add a case vector to the current function's list of deferred case
8661 vectors. Case vectors have to be put into a separate section because CAM
8662 does not allow data definitions in code sections. */
8665 unicosmk_defer_case_vector (lab
, vec
)
8669 struct machine_function
*machine
= cfun
->machine
;
8671 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
8672 machine
->addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
,
8673 machine
->addr_list
);
8676 /* Output a case vector. */
8679 unicosmk_output_addr_vec (file
, vec
)
8683 rtx lab
= XEXP (vec
, 0);
8684 rtx body
= XEXP (vec
, 1);
8685 int vlen
= XVECLEN (body
, 0);
8688 ASM_OUTPUT_INTERNAL_LABEL (file
, "L", CODE_LABEL_NUMBER (lab
));
8690 for (idx
= 0; idx
< vlen
; idx
++)
8692 ASM_OUTPUT_ADDR_VEC_ELT
8693 (file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
8697 /* Output current function's deferred case vectors. */
8700 unicosmk_output_deferred_case_vectors (file
)
8703 struct machine_function
*machine
= cfun
->machine
;
8706 if (machine
->addr_list
== NULL_RTX
)
8710 for (t
= machine
->addr_list
; t
; t
= XEXP (t
, 1))
8711 unicosmk_output_addr_vec (file
, XEXP (t
, 0));
8714 /* Set up the dynamic subprogram information block (DSIB) and update the
8715 frame pointer register ($15) for subroutines which have a frame. If the
8716 subroutine doesn't have a frame, simply increment $15. */
8719 unicosmk_gen_dsib (imaskP
)
8720 unsigned long * imaskP
;
8722 if (alpha_procedure_type
== PT_STACK
)
8724 const char *ssib_name
;
8727 /* Allocate 64 bytes for the DSIB. */
8729 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8731 emit_insn (gen_blockage ());
8733 /* Save the return address. */
8735 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 56));
8736 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8737 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, REG_RA
)));
8738 (*imaskP
) &= ~(1L << REG_RA
);
8740 /* Save the old frame pointer. */
8742 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 48));
8743 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8744 FRP (emit_move_insn (mem
, hard_frame_pointer_rtx
));
8745 (*imaskP
) &= ~(1L << HARD_FRAME_POINTER_REGNUM
);
8747 emit_insn (gen_blockage ());
8749 /* Store the SSIB pointer. */
8751 ssib_name
= ggc_strdup (unicosmk_ssib_name ());
8752 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 32));
8753 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8755 FRP (emit_move_insn (gen_rtx_REG (DImode
, 5),
8756 gen_rtx_SYMBOL_REF (Pmode
, ssib_name
)));
8757 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 5)));
8759 /* Save the CIW index. */
8761 mem
= gen_rtx_MEM (DImode
, plus_constant (stack_pointer_rtx
, 24));
8762 set_mem_alias_set (mem
, alpha_sr_alias_set
);
8763 FRP (emit_move_insn (mem
, gen_rtx_REG (DImode
, 25)));
8765 emit_insn (gen_blockage ());
8767 /* Set the new frame pointer. */
8769 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8770 stack_pointer_rtx
, GEN_INT (64))));
8775 /* Increment the frame pointer register to indicate that we do not
8778 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
8779 hard_frame_pointer_rtx
, GEN_INT (1))));
8783 #define SSIB_PREFIX "__SSIB_"
8784 #define SSIB_PREFIX_LEN 7
8786 /* Generate the name of the SSIB section for the current function. */
8789 unicosmk_ssib_name ()
8791 /* This is ok since CAM won't be able to deal with names longer than that
8794 static char name
[256];
8800 x
= DECL_RTL (cfun
->decl
);
8801 if (GET_CODE (x
) != MEM
)
8804 if (GET_CODE (x
) != SYMBOL_REF
)
8806 fnname
= XSTR (x
, 0);
8807 STRIP_NAME_ENCODING (fnname
, fnname
);
8809 len
= strlen (fnname
);
8810 if (len
+ SSIB_PREFIX_LEN
> 255)
8811 len
= 255 - SSIB_PREFIX_LEN
;
8813 strcpy (name
, SSIB_PREFIX
);
8814 strncpy (name
+ SSIB_PREFIX_LEN
, fnname
, len
);
8815 name
[len
+ SSIB_PREFIX_LEN
] = 0;
8820 /* Output the static subroutine information block for the current
8824 unicosmk_output_ssib (file
, fnname
)
8832 struct machine_function
*machine
= cfun
->machine
;
8835 fprintf (file
, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix
,
8836 unicosmk_ssib_name ());
8838 /* Some required stuff and the function name length. */
8840 len
= strlen (fnname
);
8841 fprintf (file
, "\t.quad\t^X20008%2.2X28\n", len
);
8844 ??? We don't do that yet. */
8846 fputs ("\t.quad\t0\n", file
);
8848 /* Function address. */
8850 fputs ("\t.quad\t", file
);
8851 assemble_name (file
, fnname
);
8854 fputs ("\t.quad\t0\n", file
);
8855 fputs ("\t.quad\t0\n", file
);
8858 ??? We do it the same way Cray CC does it but this could be
8861 for( i
= 0; i
< len
; i
++ )
8862 fprintf (file
, "\t.byte\t%d\n", (int)(fnname
[i
]));
8863 if( (len
% 8) == 0 )
8864 fputs ("\t.quad\t0\n", file
);
8866 fprintf (file
, "\t.bits\t%d : 0\n", (8 - (len
% 8))*8);
8868 /* All call information words used in the function. */
8870 for (x
= machine
->first_ciw
; x
; x
= XEXP (x
, 1))
8873 fprintf (file
, "\t.quad\t");
8874 #if HOST_BITS_PER_WIDE_INT == 32
8875 fprintf (file
, HOST_WIDE_INT_PRINT_DOUBLE_HEX
,
8876 CONST_DOUBLE_HIGH (ciw
), CONST_DOUBLE_LOW (ciw
));
8878 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (ciw
));
8880 fprintf (file
, "\n");
8884 /* Add a call information word (CIW) to the list of the current function's
8885 CIWs and return its index.
8887 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
8890 unicosmk_add_call_info_word (x
)
8894 struct machine_function
*machine
= cfun
->machine
;
8896 node
= gen_rtx_EXPR_LIST (VOIDmode
, x
, NULL_RTX
);
8897 if (machine
->first_ciw
== NULL_RTX
)
8898 machine
->first_ciw
= node
;
8900 XEXP (machine
->last_ciw
, 1) = node
;
8902 machine
->last_ciw
= node
;
8903 ++machine
->ciw_count
;
8905 return GEN_INT (machine
->ciw_count
8906 + strlen (current_function_name
)/8 + 5);
8909 static char unicosmk_section_buf
[100];
8912 unicosmk_text_section ()
8914 static int count
= 0;
8915 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
8917 return unicosmk_section_buf
;
8921 unicosmk_data_section ()
8923 static int count
= 1;
8924 sprintf (unicosmk_section_buf
, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
8926 return unicosmk_section_buf
;
8929 /* The Cray assembler doesn't accept extern declarations for symbols which
8930 are defined in the same file. We have to keep track of all global
8931 symbols which are referenced and/or defined in a source file and output
8932 extern declarations for those which are referenced but not defined at
8935 /* List of identifiers for which an extern declaration might have to be
8938 struct unicosmk_extern_list
8940 struct unicosmk_extern_list
*next
;
8944 static struct unicosmk_extern_list
*unicosmk_extern_head
= 0;
8946 /* Output extern declarations which are required for every asm file. */
8949 unicosmk_output_default_externs (file
)
8952 static const char *const externs
[] =
8953 { "__T3E_MISMATCH" };
8958 n
= ARRAY_SIZE (externs
);
8960 for (i
= 0; i
< n
; i
++)
8961 fprintf (file
, "\t.extern\t%s\n", externs
[i
]);
8964 /* Output extern declarations for global symbols which are have been
8965 referenced but not defined. */
8968 unicosmk_output_externs (file
)
8971 struct unicosmk_extern_list
*p
;
8972 const char *real_name
;
8976 len
= strlen (user_label_prefix
);
8977 for (p
= unicosmk_extern_head
; p
!= 0; p
= p
->next
)
8979 /* We have to strip the encoding and possibly remove user_label_prefix
8980 from the identifier in order to handle -fleading-underscore and
8981 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
8982 STRIP_NAME_ENCODING (real_name
, p
->name
);
8983 if (len
&& p
->name
[0] == '*'
8984 && !memcmp (real_name
, user_label_prefix
, len
))
8987 name_tree
= get_identifier (real_name
);
8988 if (! TREE_ASM_WRITTEN (name_tree
))
8990 TREE_ASM_WRITTEN (name_tree
) = 1;
8991 fputs ("\t.extern\t", file
);
8992 assemble_name (file
, p
->name
);
8998 /* Record an extern. */
9001 unicosmk_add_extern (name
)
9004 struct unicosmk_extern_list
*p
;
9006 p
= (struct unicosmk_extern_list
*)
9007 permalloc (sizeof (struct unicosmk_extern_list
));
9008 p
->next
= unicosmk_extern_head
;
9010 unicosmk_extern_head
= p
;
9013 /* The Cray assembler generates incorrect code if identifiers which
9014 conflict with register names are used as instruction operands. We have
9015 to replace such identifiers with DEX expressions. */
9017 /* Structure to collect identifiers which have been replaced by DEX
9020 struct unicosmk_dex
{
9021 struct unicosmk_dex
*next
;
9025 /* List of identifiers which have been replaced by DEX expressions. The DEX
9026 number is determined by the position in the list. */
9028 static struct unicosmk_dex
*unicosmk_dex_list
= NULL
;
9030 /* The number of elements in the DEX list. */
9032 static int unicosmk_dex_count
= 0;
9034 /* Check if NAME must be replaced by a DEX expression. */
9037 unicosmk_special_name (name
)
9046 if (name
[0] != 'r' && name
[0] != 'f' && name
[0] != 'R' && name
[0] != 'F')
9052 return (name
[2] == '\0' || (ISDIGIT (name
[2]) && name
[3] == '\0'));
9055 return (name
[2] == '\0'
9056 || ((name
[2] == '0' || name
[2] == '1') && name
[3] == '\0'));
9059 return (ISDIGIT (name
[1]) && name
[2] == '\0');
9063 /* Return the DEX number if X must be replaced by a DEX expression and 0
9067 unicosmk_need_dex (x
)
9070 struct unicosmk_dex
*dex
;
9074 if (GET_CODE (x
) != SYMBOL_REF
)
9078 if (! unicosmk_special_name (name
))
9081 i
= unicosmk_dex_count
;
9082 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9084 if (! strcmp (name
, dex
->name
))
9089 dex
= (struct unicosmk_dex
*) permalloc (sizeof (struct unicosmk_dex
));
9091 dex
->next
= unicosmk_dex_list
;
9092 unicosmk_dex_list
= dex
;
9094 ++unicosmk_dex_count
;
9095 return unicosmk_dex_count
;
9098 /* Output the DEX definitions for this file. */
9101 unicosmk_output_dex (file
)
9104 struct unicosmk_dex
*dex
;
9107 if (unicosmk_dex_list
== NULL
)
9110 fprintf (file
, "\t.dexstart\n");
9112 i
= unicosmk_dex_count
;
9113 for (dex
= unicosmk_dex_list
; dex
; dex
= dex
->next
)
9115 fprintf (file
, "\tDEX (%d) = ", i
);
9116 assemble_name (file
, dex
->name
);
9121 fprintf (file
, "\t.dexend\n");
9127 unicosmk_output_deferred_case_vectors (file
)
9128 FILE *file ATTRIBUTE_UNUSED
;
9132 unicosmk_gen_dsib (imaskP
)
9133 unsigned long * imaskP ATTRIBUTE_UNUSED
;
9137 unicosmk_output_ssib (file
, fnname
)
9138 FILE * file ATTRIBUTE_UNUSED
;
9139 const char * fnname ATTRIBUTE_UNUSED
;
9143 unicosmk_add_call_info_word (x
)
9144 rtx x ATTRIBUTE_UNUSED
;
9150 unicosmk_need_dex (x
)
9151 rtx x ATTRIBUTE_UNUSED
;
9156 #endif /* TARGET_ABI_UNICOSMK */