gcc/config/aarch64/predicates.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2019 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_special_predicate "cc_register"
  22   (and (match_code "reg")
  23        (and (match_test "REGNO (op) == CC_REGNUM")
  24             (ior (match_test "mode == GET_MODE (op)")
  25                  (match_test "mode == VOIDmode
  26                               && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))
  27 )
  28
  29 (define_predicate "aarch64_call_insn_operand"
  30   (ior (match_code "symbol_ref")
  31        (match_operand 0 "register_operand")))
  32
  33 (define_predicate "aarch64_general_reg"
  34   (and (match_operand 0 "register_operand")
  35        (match_test "REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS")))
  36
  37 ;; Return true if OP a (const_int 0) operand.
  38 (define_predicate "const0_operand"
  39   (and (match_code "const_int")
  40        (match_test "op == CONST0_RTX (mode)")))
  41
  42 (define_predicate "const_1_to_3_operand"
  43   (match_code "const_int,const_vector")
  44 {
  45   op = unwrap_const_vec_duplicate (op);
  46   return CONST_INT_P (op) && IN_RANGE (INTVAL (op), 1, 3);
  47 })
  48
  49 (define_special_predicate "subreg_lowpart_operator"
  50   (and (match_code "subreg")
  51        (match_test "subreg_lowpart_p (op)")))
  52
  53 (define_predicate "aarch64_ccmp_immediate"
  54   (and (match_code "const_int")
  55        (match_test "IN_RANGE (INTVAL (op), -31, 31)")))
  56
  57 (define_predicate "aarch64_ccmp_operand"
  58   (ior (match_operand 0 "register_operand")
  59        (match_operand 0 "aarch64_ccmp_immediate")))
  60
  61 (define_predicate "aarch64_simd_register"
  62   (and (match_code "reg")
  63        (match_test "FP_REGNUM_P (REGNO (op))")))
  64
  65 (define_predicate "aarch64_reg_or_zero"
  66   (and (match_code "reg,subreg,const_int,const_double")
  67        (ior (match_operand 0 "register_operand")
  68             (match_test "op == CONST0_RTX (GET_MODE (op))"))))
  69
  70 (define_predicate "aarch64_reg_or_fp_zero"
  71   (ior (match_operand 0 "register_operand")
  72         (and (match_code "const_double")
  73              (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  74
  75 (define_predicate "aarch64_reg_zero_or_fp_zero"
  76   (ior (match_operand 0 "aarch64_reg_or_fp_zero")
  77        (match_operand 0 "aarch64_reg_or_zero")))
  78
  79 (define_predicate "aarch64_reg_zero_or_m1_or_1"
  80   (and (match_code "reg,subreg,const_int")
  81        (ior (match_operand 0 "register_operand")
  82             (ior (match_test "op == const0_rtx")
  83                  (ior (match_test "op == constm1_rtx")
  84                       (match_test "op == const1_rtx"))))))
  85
  86 (define_predicate "aarch64_reg_or_orr_imm"
  87    (ior (match_operand 0 "register_operand")
  88         (and (match_code "const_vector")
  89              (match_test "aarch64_simd_valid_immediate (op, NULL,
  90                                                         AARCH64_CHECK_ORR)"))))
  91
  92 (define_predicate "aarch64_reg_or_bic_imm"
  93    (ior (match_operand 0 "register_operand")
  94         (and (match_code "const_vector")
  95              (match_test "aarch64_simd_valid_immediate (op, NULL,
  96                                                         AARCH64_CHECK_BIC)"))))
  97
  98 (define_predicate "aarch64_fp_compare_operand"
  99   (ior (match_operand 0 "register_operand")
 100        (and (match_code "const_double")
 101             (match_test "aarch64_float_const_zero_rtx_p (op)"))))
 102
 103 (define_predicate "aarch64_fp_pow2"
 104   (and (match_code "const_double")
 105         (match_test "aarch64_fpconst_pow_of_2 (op) > 0")))
 106
 107 (define_predicate "aarch64_fp_vec_pow2"
 108   (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0"))
 109
 110 (define_predicate "aarch64_sve_cnt_immediate"
 111   (and (match_code "const_poly_int")
 112        (match_test "aarch64_sve_cnt_immediate_p (op)")))
 113
 114 (define_predicate "aarch64_sub_immediate"
 115   (and (match_code "const_int")
 116        (match_test "aarch64_uimm12_shift (-INTVAL (op))")))
 117
 118 (define_predicate "aarch64_plus_immediate"
 119   (and (match_code "const_int")
 120        (ior (match_test "aarch64_uimm12_shift (INTVAL (op))")
 121             (match_test "aarch64_uimm12_shift (-INTVAL (op))"))))
 122
 123 (define_predicate "aarch64_plus_operand"
 124   (ior (match_operand 0 "register_operand")
 125        (match_operand 0 "aarch64_plus_immediate")))
 126
 127 (define_predicate "aarch64_plushi_immediate"
 128   (match_code "const_int")
 129 {
 130   HOST_WIDE_INT val = INTVAL (op);
 131   /* The HImode value must be zero-extendable to an SImode plus_operand.  */
 132   return ((val & 0xfff) == val || sext_hwi (val & 0xf000, 16) == val);
 133 })
 134
 135 (define_predicate "aarch64_plushi_operand"
 136   (ior (match_operand 0 "register_operand")
 137        (match_operand 0 "aarch64_plushi_immediate")))
 138
 139 (define_predicate "aarch64_pluslong_immediate"
 140   (and (match_code "const_int")
 141        (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)")))
 142
 143 (define_predicate "aarch64_pluslong_strict_immedate"
 144   (and (match_operand 0 "aarch64_pluslong_immediate")
 145        (not (match_operand 0 "aarch64_plus_immediate"))))
 146
 147 (define_predicate "aarch64_sve_scalar_inc_dec_immediate"
 148   (and (match_code "const_poly_int")
 149        (match_test "aarch64_sve_scalar_inc_dec_immediate_p (op)")))
 150
 151 (define_predicate "aarch64_sve_addvl_addpl_immediate"
 152   (and (match_code "const_poly_int")
 153        (match_test "aarch64_sve_addvl_addpl_immediate_p (op)")))
 154
 155 (define_predicate "aarch64_sve_plus_immediate"
 156   (ior (match_operand 0 "aarch64_sve_scalar_inc_dec_immediate")
 157        (match_operand 0 "aarch64_sve_addvl_addpl_immediate")))
 158
 159 (define_predicate "aarch64_split_add_offset_immediate"
 160   (and (match_code "const_poly_int")
 161        (match_test "aarch64_add_offset_temporaries (op) == 1")))
 162
 163 (define_predicate "aarch64_pluslong_operand"
 164   (ior (match_operand 0 "register_operand")
 165        (match_operand 0 "aarch64_pluslong_immediate")
 166        (and (match_test "TARGET_SVE")
 167             (match_operand 0 "aarch64_sve_plus_immediate"))))
 168
 169 (define_predicate "aarch64_pluslong_or_poly_operand"
 170   (ior (match_operand 0 "aarch64_pluslong_operand")
 171        (match_operand 0 "aarch64_split_add_offset_immediate")))
 172
 173 (define_predicate "aarch64_logical_immediate"
 174   (and (match_code "const_int")
 175        (match_test "aarch64_bitmask_imm (INTVAL (op), mode)")))
 176
 177 (define_predicate "aarch64_logical_operand"
 178   (ior (match_operand 0 "register_operand")
 179        (match_operand 0 "aarch64_logical_immediate")))
 180
 181 (define_predicate "aarch64_mov_imm_operand"
 182   (and (match_code "const_int")
 183        (match_test "aarch64_move_imm (INTVAL (op), mode)")))
 184
 185 (define_predicate "aarch64_logical_and_immediate"
 186   (and (match_code "const_int")
 187        (match_test "aarch64_and_bitmask_imm (INTVAL (op), mode)")))
 188
 189 (define_predicate "aarch64_shift_imm_si"
 190   (and (match_code "const_int")
 191        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32")))
 192
 193 (define_predicate "aarch64_shift_imm_di"
 194   (and (match_code "const_int")
 195        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64")))
 196
 197 (define_predicate "aarch64_shift_imm64_di"
 198   (and (match_code "const_int")
 199        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 64")))
 200
 201 (define_predicate "aarch64_reg_or_shift_imm_si"
 202   (ior (match_operand 0 "register_operand")
 203        (match_operand 0 "aarch64_shift_imm_si")))
 204
 205 (define_predicate "aarch64_reg_or_shift_imm_di"
 206   (ior (match_operand 0 "register_operand")
 207        (match_operand 0 "aarch64_shift_imm_di")))
 208
 209 ;; The imm3 field is a 3-bit field that only accepts immediates in the
 210 ;; range 0..4.
 211 (define_predicate "aarch64_imm3"
 212   (and (match_code "const_int")
 213        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4")))
 214
 215 ;; The imm2 field is a 2-bit field that only accepts immediates in the
 216 ;; range 0..3.
 217 (define_predicate "aarch64_imm2"
 218   (and (match_code "const_int")
 219        (match_test "UINTVAL (op) <= 3")))
 220
 221 ;; The imm3 field is a 3-bit field that only accepts immediates in the
 222 ;; range 0..7.
 223 (define_predicate "aarch64_lane_imm3"
 224   (and (match_code "const_int")
 225        (match_test "UINTVAL (op) <= 7")))
 226
 227 ;; An immediate that fits into 24 bits.
 228 (define_predicate "aarch64_imm24"
 229   (and (match_code "const_int")
 230        (match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)")))
 231
 232 (define_predicate "aarch64_pwr_imm3"
 233   (and (match_code "const_int")
 234        (match_test "INTVAL (op) != 0
 235                     && (unsigned) exact_log2 (INTVAL (op)) <= 4")))
 236
 237 (define_predicate "aarch64_pwr_2_si"
 238   (and (match_code "const_int")
 239        (match_test "INTVAL (op) != 0
 240                     && (unsigned) exact_log2 (INTVAL (op)) < 32")))
 241
 242 (define_predicate "aarch64_pwr_2_di"
 243   (and (match_code "const_int")
 244        (match_test "INTVAL (op) != 0
 245                     && (unsigned) exact_log2 (INTVAL (op)) < 64")))
 246
 247 (define_predicate "aarch64_mem_pair_offset"
 248   (and (match_code "const_int")
 249        (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
 250
 251 (define_predicate "aarch64_mem_pair_operand"
 252   (and (match_code "mem")
 253        (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), false,
 254                                                   ADDR_QUERY_LDP_STP)")))
 255
 256 ;; Used for storing two 64-bit values in an AdvSIMD register using an STP
 257 ;; as a 128-bit vec_concat.
 258 (define_predicate "aarch64_mem_pair_lanes_operand"
 259   (and (match_code "mem")
 260        (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
 261                                                   false,
 262                                                   ADDR_QUERY_LDP_STP_N)")))
 263
 264 (define_predicate "aarch64_prefetch_operand"
 265   (match_test "aarch64_address_valid_for_prefetch_p (op, false)"))
 266
 267 (define_predicate "aarch64_valid_symref"
 268   (match_code "const, symbol_ref, label_ref")
 269 {
 270   return (aarch64_classify_symbolic_expression (op)
 271           != SYMBOL_FORCE_TO_MEM);
 272 })
 273
 274 (define_predicate "aarch64_tls_ie_symref"
 275   (match_code "const, symbol_ref, label_ref")
 276 {
 277   switch (GET_CODE (op))
 278     {
 279     case CONST:
 280       op = XEXP (op, 0);
 281       if (GET_CODE (op) != PLUS
 282           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 283           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 284         return false;
 285       op = XEXP (op, 0);
 286       /* FALLTHRU */
 287
 288     case SYMBOL_REF:
 289       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC;
 290
 291     default:
 292       gcc_unreachable ();
 293     }
 294 })
 295
 296 (define_predicate "aarch64_tls_le_symref"
 297   (match_code "const, symbol_ref, label_ref")
 298 {
 299   switch (GET_CODE (op))
 300     {
 301     case CONST:
 302       op = XEXP (op, 0);
 303       if (GET_CODE (op) != PLUS
 304           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 305           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 306         return false;
 307       op = XEXP (op, 0);
 308       /* FALLTHRU */
 309
 310     case SYMBOL_REF:
 311       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC;
 312
 313     default:
 314       gcc_unreachable ();
 315     }
 316 })
 317
 318 (define_predicate "aarch64_mov_operand"
 319   (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high,
 320                     const_poly_int,const_vector")
 321        (ior (match_operand 0 "register_operand")
 322             (ior (match_operand 0 "memory_operand")
 323                  (match_test "aarch64_mov_operand_p (op, mode)")))))
 324
 325 (define_predicate "aarch64_nonmemory_operand"
 326   (and (match_code "reg,subreg,const,const_int,symbol_ref,label_ref,high,
 327                     const_poly_int,const_vector")
 328        (ior (match_operand 0 "register_operand")
 329             (match_test "aarch64_mov_operand_p (op, mode)"))))
 330
 331 (define_predicate "aarch64_movti_operand"
 332   (ior (match_operand 0 "register_operand")
 333        (match_operand 0 "memory_operand")
 334        (and (match_operand 0 "const_scalar_int_operand")
 335             (match_test "aarch64_mov128_immediate (op)"))))
 336
 337 (define_predicate "aarch64_reg_or_imm"
 338   (ior (match_operand 0 "register_operand")
 339        (match_operand 0 "const_scalar_int_operand")))
 340
 341 ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ.
 342 (define_special_predicate "aarch64_comparison_operator"
 343   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 344                ordered,unlt,unle,unge,ungt"))
 345
 346 ;; Same as aarch64_comparison_operator but don't ignore the mode.
 347 ;; RTL SET operations require their operands source and destination have
 348 ;; the same modes, so we can't ignore the modes there.  See PR target/69161.
 349 (define_predicate "aarch64_comparison_operator_mode"
 350   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 351                ordered,unlt,unle,unge,ungt"))
 352
 353 (define_special_predicate "aarch64_comparison_operation"
 354   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 355                ordered,unlt,unle,unge,ungt")
 356 {
 357   if (XEXP (op, 1) != const0_rtx)
 358     return false;
 359   rtx op0 = XEXP (op, 0);
 360   if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 361     return false;
 362   return aarch64_get_condition_code (op) >= 0;
 363 })
 364
 365 (define_special_predicate "aarch64_equality_operator"
 366   (match_code "eq,ne"))
 367
 368 (define_special_predicate "aarch64_carry_operation"
 369   (match_code "ltu,geu")
 370 {
 371   if (XEXP (op, 1) != const0_rtx)
 372     return false;
 373   rtx op0 = XEXP (op, 0);
 374   if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 375     return false;
 376   machine_mode ccmode = GET_MODE (op0);
 377   if (ccmode == CC_Cmode)
 378     return GET_CODE (op) == LTU;
 379   if (ccmode == CC_ADCmode || ccmode == CCmode)
 380     return GET_CODE (op) == GEU;
 381   return false;
 382 })
 383
 384 ; borrow is essentially the inverse of carry since the sense of the C flag
 385 ; is inverted during subtraction.  See the note in aarch64-modes.def.
 386 (define_special_predicate "aarch64_borrow_operation"
 387   (match_code "geu,ltu")
 388 {
 389   if (XEXP (op, 1) != const0_rtx)
 390     return false;
 391   rtx op0 = XEXP (op, 0);
 392   if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 393     return false;
 394   machine_mode ccmode = GET_MODE (op0);
 395   if (ccmode == CC_Cmode)
 396     return GET_CODE (op) == GEU;
 397   if (ccmode == CC_ADCmode || ccmode == CCmode)
 398     return GET_CODE (op) == LTU;
 399   return false;
 400 })
 401
 402 ;; True if the operand is memory reference suitable for a load/store exclusive.
 403 (define_predicate "aarch64_sync_memory_operand"
 404   (and (match_operand 0 "memory_operand")
 405        (match_code "reg" "0")))
 406
 407 (define_predicate "aarch64_9bit_offset_memory_operand"
 408   (and (match_operand 0 "memory_operand")
 409        (ior (match_code "reg" "0")
 410             (and (match_code "plus" "0")
 411                  (match_code "reg"  "00")
 412                  (match_code "const_int" "01"))))
 413 {
 414   rtx mem_op = XEXP (op, 0);
 415
 416   if (REG_P (mem_op))
 417     return GET_MODE (mem_op) == DImode;
 418
 419   rtx plus_op0 = XEXP (mem_op, 0);
 420   rtx plus_op1 = XEXP (mem_op, 1);
 421
 422   if (GET_MODE (plus_op0) != DImode)
 423     return false;
 424
 425   poly_int64 offset;
 426   if (!poly_int_rtx_p (plus_op1, &offset))
 427     gcc_unreachable ();
 428
 429   return aarch64_offset_9bit_signed_unscaled_p (mode, offset);
 430 })
 431
 432 (define_predicate "aarch64_rcpc_memory_operand"
 433   (if_then_else (match_test "AARCH64_ISA_RCPC8_4")
 434     (match_operand 0 "aarch64_9bit_offset_memory_operand")
 435     (match_operand 0 "aarch64_sync_memory_operand")))
 436
 437 ;; Predicates for parallel expanders based on mode.
 438 (define_special_predicate "vect_par_cnst_hi_half"
 439   (match_code "parallel")
 440 {
 441   return aarch64_simd_check_vect_par_cnst_half (op, mode, true);
 442 })
 443
 444 (define_special_predicate "vect_par_cnst_lo_half"
 445   (match_code "parallel")
 446 {
 447   return aarch64_simd_check_vect_par_cnst_half (op, mode, false);
 448 })
 449
 450 (define_predicate "descending_int_parallel"
 451   (match_code "parallel")
 452 {
 453   return aarch64_stepped_int_parallel_p (op, -1);
 454 })
 455
 456 (define_special_predicate "aarch64_simd_lshift_imm"
 457   (match_code "const,const_vector")
 458 {
 459   return aarch64_simd_shift_imm_p (op, mode, true);
 460 })
 461
 462 (define_special_predicate "aarch64_simd_rshift_imm"
 463   (match_code "const,const_vector")
 464 {
 465   return aarch64_simd_shift_imm_p (op, mode, false);
 466 })
 467
 468 (define_predicate "aarch64_simd_imm_zero"
 469   (and (match_code "const,const_vector")
 470        (match_test "op == CONST0_RTX (GET_MODE (op))")))
 471
 472 (define_predicate "aarch64_simd_imm_one"
 473   (and (match_code "const_vector")
 474        (match_test "op == CONST1_RTX (GET_MODE (op))")))
 475
 476 (define_predicate "aarch64_simd_or_scalar_imm_zero"
 477   (and (match_code "const_int,const_double,const,const_vector")
 478        (match_test "op == CONST0_RTX (GET_MODE (op))")))
 479
 480 (define_predicate "aarch64_simd_imm_minus_one"
 481   (and (match_code "const,const_vector")
 482        (match_test "op == CONSTM1_RTX (GET_MODE (op))")))
 483
 484 (define_predicate "aarch64_simd_reg_or_zero"
 485   (and (match_code "reg,subreg,const_int,const_double,const,const_vector")
 486        (ior (match_operand 0 "register_operand")
 487             (match_test "op == const0_rtx")
 488             (match_operand 0 "aarch64_simd_or_scalar_imm_zero"))))
 489
 490 (define_predicate "aarch64_simd_struct_operand"
 491   (and (match_code "mem")
 492        (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)")))
 493
 494 ;; Like general_operand but allow only valid SIMD addressing modes.
 495 (define_predicate "aarch64_simd_general_operand"
 496   (and (match_operand 0 "general_operand")
 497        (match_test "!MEM_P (op)
 498                     || GET_CODE (XEXP (op, 0)) == POST_INC
 499                     || GET_CODE (XEXP (op, 0)) == REG")))
 500
 501 ;; Like nonimmediate_operand but allow only valid SIMD addressing modes.
 502 (define_predicate "aarch64_simd_nonimmediate_operand"
 503   (and (match_operand 0 "nonimmediate_operand")
 504        (match_test "!MEM_P (op)
 505                     || GET_CODE (XEXP (op, 0)) == POST_INC
 506                     || GET_CODE (XEXP (op, 0)) == REG")))
 507
 508 ;; Predicates used by the various SIMD shift operations.  These
 509 ;; fall in to 3 categories.
 510 ;;   Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm)
 511 ;;   Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset)
 512 ;;   Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize)
 513 (define_predicate "aarch64_simd_shift_imm_qi"
 514   (and (match_code "const_int")
 515        (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
 516
 517 (define_predicate "aarch64_simd_shift_imm_hi"
 518   (and (match_code "const_int")
 519        (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
 520
 521 (define_predicate "aarch64_simd_shift_imm_si"
 522   (and (match_code "const_int")
 523        (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
 524
 525 (define_predicate "aarch64_simd_shift_imm_di"
 526   (and (match_code "const_int")
 527        (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
 528
 529 (define_predicate "aarch64_simd_shift_imm_offset_qi"
 530   (and (match_code "const_int")
 531        (match_test "IN_RANGE (INTVAL (op), 1, 8)")))
 532
 533 (define_predicate "aarch64_simd_shift_imm_offset_hi"
 534   (and (match_code "const_int")
 535        (match_test "IN_RANGE (INTVAL (op), 1, 16)")))
 536
 537 (define_predicate "aarch64_simd_shift_imm_offset_si"
 538   (and (match_code "const_int")
 539        (match_test "IN_RANGE (INTVAL (op), 1, 32)")))
 540
 541 (define_predicate "aarch64_simd_shift_imm_offset_di"
 542   (and (match_code "const_int")
 543        (match_test "IN_RANGE (INTVAL (op), 1, 64)")))
 544
 545 (define_predicate "aarch64_simd_shift_imm_bitsize_qi"
 546   (and (match_code "const_int")
 547        (match_test "IN_RANGE (INTVAL (op), 0, 8)")))
 548
 549 (define_predicate "aarch64_simd_shift_imm_bitsize_hi"
 550   (and (match_code "const_int")
 551        (match_test "IN_RANGE (INTVAL (op), 0, 16)")))
 552
 553 (define_predicate "aarch64_simd_shift_imm_bitsize_si"
 554   (and (match_code "const_int")
 555        (match_test "IN_RANGE (INTVAL (op), 0, 32)")))
 556
 557 (define_predicate "aarch64_simd_shift_imm_bitsize_di"
 558   (and (match_code "const_int")
 559        (match_test "IN_RANGE (INTVAL (op), 0, 64)")))
 560
 561 (define_predicate "aarch64_constant_pool_symref"
 562    (and (match_code "symbol_ref")
 563         (match_test "CONSTANT_POOL_ADDRESS_P (op)")))
 564
 565 (define_predicate "aarch64_constant_vector_operand"
 566   (match_code "const,const_vector"))
 567
 568 (define_predicate "aarch64_sve_ld1r_operand"
 569   (and (match_operand 0 "memory_operand")
 570        (match_test "aarch64_sve_ld1r_operand_p (op)")))
 571
 572 (define_predicate "aarch64_sve_ld1rq_operand"
 573   (and (match_code "mem")
 574        (match_test "aarch64_sve_ld1rq_operand_p (op)")))
 575
 576 ;; Like memory_operand, but restricted to addresses that are valid for
 577 ;; SVE LDR and STR instructions.
 578 (define_predicate "aarch64_sve_ldr_operand"
 579   (and (match_code "mem")
 580        (match_test "aarch64_sve_ldr_operand_p (op)")))
 581
 582 (define_predicate "aarch64_sve_nonimmediate_operand"
 583   (ior (match_operand 0 "register_operand")
 584        (match_operand 0 "aarch64_sve_ldr_operand")))
 585
 586 (define_predicate "aarch64_sve_general_operand"
 587   (and (match_code "reg,subreg,mem,const,const_vector")
 588        (ior (match_operand 0 "register_operand")
 589             (match_operand 0 "aarch64_sve_ldr_operand")
 590             (match_test "aarch64_mov_operand_p (op, mode)"))))
 591
 592 (define_predicate "aarch64_sve_struct_memory_operand"
 593   (and (match_code "mem")
 594        (match_test "aarch64_sve_struct_memory_operand_p (op)")))
 595
 596 (define_predicate "aarch64_sve_struct_nonimmediate_operand"
 597   (ior (match_operand 0 "register_operand")
 598        (match_operand 0 "aarch64_sve_struct_memory_operand")))
 599
 600 ;; Doesn't include immediates, since those are handled by the move
 601 ;; patterns instead.
 602 (define_predicate "aarch64_sve_dup_operand"
 603   (ior (match_operand 0 "register_operand")
 604        (match_operand 0 "aarch64_sve_ld1r_operand")))
 605
 606 (define_predicate "aarch64_sve_arith_immediate"
 607   (and (match_code "const,const_vector")
 608        (match_test "aarch64_sve_arith_immediate_p (op, false)")))
 609
 610 (define_predicate "aarch64_sve_sub_arith_immediate"
 611   (and (match_code "const,const_vector")
 612        (match_test "aarch64_sve_arith_immediate_p (op, true)")))
 613
 614 (define_predicate "aarch64_sve_vector_inc_dec_immediate"
 615   (and (match_code "const,const_vector")
 616        (match_test "aarch64_sve_vector_inc_dec_immediate_p (op)")))
 617
 618 (define_predicate "aarch64_sve_uxtb_immediate"
 619   (and (match_code "const_vector")
 620        (match_test "GET_MODE_UNIT_BITSIZE (GET_MODE (op)) > 8")
 621        (match_test "aarch64_const_vec_all_same_int_p (op, 0xff)")))
 622
 623 (define_predicate "aarch64_sve_uxth_immediate"
 624   (and (match_code "const_vector")
 625        (match_test "GET_MODE_UNIT_BITSIZE (GET_MODE (op)) > 16")
 626        (match_test "aarch64_const_vec_all_same_int_p (op, 0xffff)")))
 627
 628 (define_predicate "aarch64_sve_uxtw_immediate"
 629   (and (match_code "const_vector")
 630        (match_test "GET_MODE_UNIT_BITSIZE (GET_MODE (op)) > 32")
 631        (match_test "aarch64_const_vec_all_same_int_p (op, 0xffffffff)")))
 632
 633 (define_predicate "aarch64_sve_uxt_immediate"
 634   (ior (match_operand 0 "aarch64_sve_uxtb_immediate")
 635        (match_operand 0 "aarch64_sve_uxth_immediate")
 636        (match_operand 0 "aarch64_sve_uxtw_immediate")))
 637
 638 (define_predicate "aarch64_sve_logical_immediate"
 639   (and (match_code "const,const_vector")
 640        (match_test "aarch64_sve_bitmask_immediate_p (op)")))
 641
 642 ;; Used for SVE UMAX and UMIN.
 643 (define_predicate "aarch64_sve_vsb_immediate"
 644   (and (match_code "const_vector")
 645        (match_test "GET_MODE_INNER (GET_MODE (op)) == QImode
 646                     ? aarch64_const_vec_all_same_in_range_p (op, -128, 127)
 647                     : aarch64_const_vec_all_same_in_range_p (op, 0, 255)")))
 648
 649 ;; Used for SVE MUL, SMAX and SMIN.
 650 (define_predicate "aarch64_sve_vsm_immediate"
 651   (and (match_code "const,const_vector")
 652        (match_test "aarch64_const_vec_all_same_in_range_p (op, -128, 127)")))
 653
 654 (define_predicate "aarch64_sve_dup_immediate"
 655   (and (match_code "const,const_vector")
 656        (ior (match_test "aarch64_sve_dup_immediate_p (op)")
 657             (match_test "aarch64_float_const_representable_p (op)"))))
 658
 659 (define_predicate "aarch64_sve_cmp_vsc_immediate"
 660   (and (match_code "const,const_vector")
 661        (match_test "aarch64_sve_cmp_immediate_p (op, true)")))
 662
 663 (define_predicate "aarch64_sve_cmp_vsd_immediate"
 664   (and (match_code "const,const_vector")
 665        (match_test "aarch64_sve_cmp_immediate_p (op, false)")))
 666
 667 (define_predicate "aarch64_sve_index_immediate"
 668   (and (match_code "const_int")
 669        (match_test "aarch64_sve_index_immediate_p (op)")))
 670
 671 (define_predicate "aarch64_sve_float_arith_immediate"
 672   (and (match_code "const,const_vector")
 673        (match_test "aarch64_sve_float_arith_immediate_p (op, false)")))
 674
 675 (define_predicate "aarch64_sve_float_negated_arith_immediate"
 676   (and (match_code "const,const_vector")
 677        (match_test "aarch64_sve_float_arith_immediate_p (op, true)")))
 678
 679 (define_predicate "aarch64_sve_float_arith_with_sub_immediate"
 680   (ior (match_operand 0 "aarch64_sve_float_arith_immediate")
 681        (match_operand 0 "aarch64_sve_float_negated_arith_immediate")))
 682
 683 (define_predicate "aarch64_sve_float_mul_immediate"
 684   (and (match_code "const,const_vector")
 685        (match_test "aarch64_sve_float_mul_immediate_p (op)")))
 686
 687 (define_predicate "aarch64_sve_float_maxmin_immediate"
 688   (and (match_code "const_vector")
 689        (ior (match_test "op == CONST0_RTX (GET_MODE (op))")
 690             (match_test "op == CONST1_RTX (GET_MODE (op))"))))
 691
 692 (define_predicate "aarch64_sve_arith_operand"
 693   (ior (match_operand 0 "register_operand")
 694        (match_operand 0 "aarch64_sve_arith_immediate")))
 695
 696 (define_predicate "aarch64_sve_add_operand"
 697   (ior (match_operand 0 "aarch64_sve_arith_operand")
 698        (match_operand 0 "aarch64_sve_sub_arith_immediate")
 699        (match_operand 0 "aarch64_sve_vector_inc_dec_immediate")))
 700
 701 (define_predicate "aarch64_sve_pred_and_operand"
 702   (ior (match_operand 0 "register_operand")
 703        (match_operand 0 "aarch64_sve_uxt_immediate")))
 704
 705 (define_predicate "aarch64_sve_logical_operand"
 706   (ior (match_operand 0 "register_operand")
 707        (match_operand 0 "aarch64_sve_logical_immediate")))
 708
 709 (define_predicate "aarch64_sve_lshift_operand"
 710   (ior (match_operand 0 "register_operand")
 711        (match_operand 0 "aarch64_simd_lshift_imm")))
 712
 713 (define_predicate "aarch64_sve_rshift_operand"
 714   (ior (match_operand 0 "register_operand")
 715        (match_operand 0 "aarch64_simd_rshift_imm")))
 716
 717 (define_predicate "aarch64_sve_vsb_operand"
 718   (ior (match_operand 0 "register_operand")
 719        (match_operand 0 "aarch64_sve_vsb_immediate")))
 720
 721 (define_predicate "aarch64_sve_vsm_operand"
 722   (ior (match_operand 0 "register_operand")
 723        (match_operand 0 "aarch64_sve_vsm_immediate")))
 724
 725 (define_predicate "aarch64_sve_reg_or_dup_imm"
 726   (ior (match_operand 0 "register_operand")
 727        (match_operand 0 "aarch64_sve_dup_immediate")))
 728
 729 (define_predicate "aarch64_sve_cmp_vsc_operand"
 730   (ior (match_operand 0 "register_operand")
 731        (match_operand 0 "aarch64_sve_cmp_vsc_immediate")))
 732
 733 (define_predicate "aarch64_sve_cmp_vsd_operand"
 734   (ior (match_operand 0 "register_operand")
 735        (match_operand 0 "aarch64_sve_cmp_vsd_immediate")))
 736
 737 (define_predicate "aarch64_sve_index_operand"
 738   (ior (match_operand 0 "register_operand")
 739        (match_operand 0 "aarch64_sve_index_immediate")))
 740
 741 (define_predicate "aarch64_sve_float_arith_operand"
 742   (ior (match_operand 0 "register_operand")
 743        (match_operand 0 "aarch64_sve_float_arith_immediate")))
 744
 745 (define_predicate "aarch64_sve_float_arith_with_sub_operand"
 746   (ior (match_operand 0 "register_operand")
 747        (match_operand 0 "aarch64_sve_float_arith_with_sub_immediate")))
 748
 749 (define_predicate "aarch64_sve_float_mul_operand"
 750   (ior (match_operand 0 "register_operand")
 751        (match_operand 0 "aarch64_sve_float_mul_immediate")))
 752
 753 (define_predicate "aarch64_sve_float_maxmin_operand"
 754   (ior (match_operand 0 "register_operand")
 755        (match_operand 0 "aarch64_sve_float_maxmin_immediate")))
 756
 757 (define_predicate "aarch64_sve_vec_perm_operand"
 758   (ior (match_operand 0 "register_operand")
 759        (match_operand 0 "aarch64_constant_vector_operand")))
 760
 761 (define_predicate "aarch64_sve_ptrue_flag"
 762   (and (match_code "const_int")
 763        (ior (match_test "INTVAL (op) == SVE_MAYBE_NOT_PTRUE")
 764             (match_test "INTVAL (op) == SVE_KNOWN_PTRUE"))))
 765
 766 (define_predicate "aarch64_sve_gp_strictness"
 767   (and (match_code "const_int")
 768        (ior (match_test "INTVAL (op) == SVE_RELAXED_GP")
 769             (match_test "INTVAL (op) == SVE_STRICT_GP"))))
 770
 771 (define_predicate "aarch64_gather_scale_operand_w"
 772   (and (match_code "const_int")
 773        (match_test "INTVAL (op) == 1 || INTVAL (op) == 4")))
 774
 775 (define_predicate "aarch64_gather_scale_operand_d"
 776   (and (match_code "const_int")
 777        (match_test "INTVAL (op) == 1 || INTVAL (op) == 8")))
 778
 779 ;; A special predicate that doesn't match a particular mode.
 780 (define_special_predicate "aarch64_any_register_operand"
 781   (match_code "reg"))
 782
 783 (define_predicate "aarch64_sve_any_binary_operator"
 784   (match_code "plus,minus,mult,div,udiv,smax,umax,smin,umin,and,ior,xor"))