gcc/config/aarch64/aarch64.h

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2009-2023 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 #ifndef GCC_AARCH64_H
  23 #define GCC_AARCH64_H
  24
  25 /* Make these flags read-only so that all uses go via
  26    aarch64_set_asm_isa_flags.  */
  27 #ifndef GENERATOR_FILE
  28 #undef aarch64_asm_isa_flags
  29 #define aarch64_asm_isa_flags \
  30   ((aarch64_feature_flags) global_options.x_aarch64_asm_isa_flags)
  31 #undef aarch64_isa_flags
  32 #define aarch64_isa_flags \
  33   ((aarch64_feature_flags) global_options.x_aarch64_isa_flags)
  34 #endif
  35
  36 /* Target CPU builtins.  */
  37 #define TARGET_CPU_CPP_BUILTINS()       \
  38   aarch64_cpu_cpp_builtins (pfile)
  39
  40 \f
  41
  42 #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas ()
  43
  44 /* Target machine storage layout.  */
  45
  46 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
  47   if (GET_MODE_CLASS (MODE) == MODE_INT         \
  48       && GET_MODE_SIZE (MODE) < 4)              \
  49     {                                           \
  50       if (MODE == QImode || MODE == HImode)     \
  51         {                                       \
  52           MODE = SImode;                        \
  53         }                                       \
  54     }
  55
  56 /* Bits are always numbered from the LSBit.  */
  57 #define BITS_BIG_ENDIAN 0
  58
  59 /* Big/little-endian flavour.  */
  60 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
  61 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
  62
  63 /* AdvSIMD is supported in the default configuration, unless disabled by
  64    -mgeneral-regs-only or by the +nosimd extension.  */
  65 #define TARGET_SIMD (AARCH64_ISA_SIMD)
  66 #define TARGET_FLOAT (AARCH64_ISA_FP)
  67
  68 #define UNITS_PER_WORD          8
  69
  70 #define UNITS_PER_VREG          16
  71
  72 #define PARM_BOUNDARY           64
  73
  74 #define STACK_BOUNDARY          128
  75
  76 #define FUNCTION_BOUNDARY       32
  77
  78 #define EMPTY_FIELD_BOUNDARY    32
  79
  80 #define BIGGEST_ALIGNMENT       128
  81
  82 #define SHORT_TYPE_SIZE         16
  83
  84 #define INT_TYPE_SIZE           32
  85
  86 #define LONG_TYPE_SIZE          (TARGET_ILP32 ? 32 : 64)
  87
  88 #define POINTER_SIZE            (TARGET_ILP32 ? 32 : 64)
  89
  90 #define LONG_LONG_TYPE_SIZE     64
  91
  92 #define FLOAT_TYPE_SIZE         32
  93
  94 #define DOUBLE_TYPE_SIZE        64
  95
  96 #define LONG_DOUBLE_TYPE_SIZE   128
  97
  98 /* This value is the amount of bytes a caller is allowed to drop the stack
  99    before probing has to be done for stack clash protection.  */
 100 #define STACK_CLASH_CALLER_GUARD 1024
 101
 102 /* This value represents the minimum amount of bytes we expect the function's
 103    outgoing arguments to be when stack-clash is enabled.  */
 104 #define STACK_CLASH_MIN_BYTES_OUTGOING_ARGS 8
 105
 106 /* This value controls how many pages we manually unroll the loop for when
 107    generating stack clash probes.  */
 108 #define STACK_CLASH_MAX_UNROLL_PAGES 4
 109
 110 /* The architecture reserves all bits of the address for hardware use,
 111    so the vbit must go into the delta field of pointers to member
 112    functions.  This is the same config as that in the AArch32
 113    port.  */
 114 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
 115
 116
 117 /* Emit calls to libgcc helpers for atomic operations for runtime detection
 118    of LSE instructions.  */
 119 #define TARGET_OUTLINE_ATOMICS (aarch64_flag_outline_atomics)
 120
 121 /* Align definitions of arrays, unions and structures so that
 122    initializations and copies can be made more efficient.  This is not
 123    ABI-changing, so it only affects places where we can see the
 124    definition.  Increasing the alignment tends to introduce padding,
 125    so don't do this when optimizing for size/conserving stack space.  */
 126 #define AARCH64_EXPAND_ALIGNMENT(COND, EXP, ALIGN)                      \
 127   (((COND) && ((ALIGN) < BITS_PER_WORD)                                 \
 128     && (TREE_CODE (EXP) == ARRAY_TYPE                                   \
 129         || TREE_CODE (EXP) == UNION_TYPE                                \
 130         || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 131
 132 /* Align global data.  */
 133 #define DATA_ALIGNMENT(EXP, ALIGN)                      \
 134   AARCH64_EXPAND_ALIGNMENT (!optimize_size, EXP, ALIGN)
 135
 136 /* Similarly, make sure that objects on the stack are sensibly aligned.  */
 137 #define LOCAL_ALIGNMENT(EXP, ALIGN)                             \
 138   AARCH64_EXPAND_ALIGNMENT (!flag_conserve_stack, EXP, ALIGN)
 139
 140 #define STRUCTURE_SIZE_BOUNDARY         8
 141
 142 /* Heap alignment (same as BIGGEST_ALIGNMENT and STACK_BOUNDARY).  */
 143 #define MALLOC_ABI_ALIGNMENT  128
 144
 145 /* Defined by the ABI */
 146 #define WCHAR_TYPE "unsigned int"
 147 #define WCHAR_TYPE_SIZE                 32
 148
 149 /* Using long long breaks -ansi and -std=c90, so these will need to be
 150    made conditional for an LLP64 ABI.  */
 151
 152 #define SIZE_TYPE       "long unsigned int"
 153
 154 #define PTRDIFF_TYPE    "long int"
 155
 156 #define PCC_BITFIELD_TYPE_MATTERS       1
 157
 158 #ifndef USED_FOR_TARGET
 159
 160 /* Define an enum of all features (architectures and extensions).  */
 161 enum class aarch64_feature : unsigned char {
 162 #define AARCH64_OPT_EXTENSION(A, IDENT, C, D, E, F) IDENT,
 163 #define AARCH64_ARCH(A, B, IDENT, D, E) IDENT,
 164 #include "aarch64-option-extensions.def"
 165 #include "aarch64-arches.def"
 166 };
 167
 168 /* Define unique flags for each of the above.  */
 169 #define HANDLE(IDENT) \
 170   constexpr auto AARCH64_FL_##IDENT \
 171     = aarch64_feature_flags (1) << int (aarch64_feature::IDENT);
 172 #define AARCH64_OPT_EXTENSION(A, IDENT, C, D, E, F) HANDLE (IDENT)
 173 #define AARCH64_ARCH(A, B, IDENT, D, E) HANDLE (IDENT)
 174 #include "aarch64-option-extensions.def"
 175 #include "aarch64-arches.def"
 176 #undef HANDLE
 177
 178 #endif
 179
 180 /* Macros to test ISA flags.  */
 181
 182 #define AARCH64_ISA_CRC            (aarch64_isa_flags & AARCH64_FL_CRC)
 183 #define AARCH64_ISA_CRYPTO         (aarch64_isa_flags & AARCH64_FL_CRYPTO)
 184 #define AARCH64_ISA_FP             (aarch64_isa_flags & AARCH64_FL_FP)
 185 #define AARCH64_ISA_SIMD           (aarch64_isa_flags & AARCH64_FL_SIMD)
 186 #define AARCH64_ISA_LSE            (aarch64_isa_flags & AARCH64_FL_LSE)
 187 #define AARCH64_ISA_RDMA           (aarch64_isa_flags & AARCH64_FL_RDMA)
 188 #define AARCH64_ISA_V8_2A          (aarch64_isa_flags & AARCH64_FL_V8_2A)
 189 #define AARCH64_ISA_F16            (aarch64_isa_flags & AARCH64_FL_F16)
 190 #define AARCH64_ISA_SVE            (aarch64_isa_flags & AARCH64_FL_SVE)
 191 #define AARCH64_ISA_SVE2           (aarch64_isa_flags & AARCH64_FL_SVE2)
 192 #define AARCH64_ISA_SVE2_AES       (aarch64_isa_flags & AARCH64_FL_SVE2_AES)
 193 #define AARCH64_ISA_SVE2_BITPERM  (aarch64_isa_flags & AARCH64_FL_SVE2_BITPERM)
 194 #define AARCH64_ISA_SVE2_SHA3      (aarch64_isa_flags & AARCH64_FL_SVE2_SHA3)
 195 #define AARCH64_ISA_SVE2_SM4       (aarch64_isa_flags & AARCH64_FL_SVE2_SM4)
 196 #define AARCH64_ISA_V8_3A          (aarch64_isa_flags & AARCH64_FL_V8_3A)
 197 #define AARCH64_ISA_DOTPROD        (aarch64_isa_flags & AARCH64_FL_DOTPROD)
 198 #define AARCH64_ISA_AES            (aarch64_isa_flags & AARCH64_FL_AES)
 199 #define AARCH64_ISA_SHA2           (aarch64_isa_flags & AARCH64_FL_SHA2)
 200 #define AARCH64_ISA_V8_4A          (aarch64_isa_flags & AARCH64_FL_V8_4A)
 201 #define AARCH64_ISA_SM4            (aarch64_isa_flags & AARCH64_FL_SM4)
 202 #define AARCH64_ISA_SHA3           (aarch64_isa_flags & AARCH64_FL_SHA3)
 203 #define AARCH64_ISA_F16FML         (aarch64_isa_flags & AARCH64_FL_F16FML)
 204 #define AARCH64_ISA_RCPC           (aarch64_isa_flags & AARCH64_FL_RCPC)
 205 #define AARCH64_ISA_RCPC8_4        (aarch64_isa_flags & AARCH64_FL_V8_4A)
 206 #define AARCH64_ISA_RNG            (aarch64_isa_flags & AARCH64_FL_RNG)
 207 #define AARCH64_ISA_V8_5A          (aarch64_isa_flags & AARCH64_FL_V8_5A)
 208 #define AARCH64_ISA_TME            (aarch64_isa_flags & AARCH64_FL_TME)
 209 #define AARCH64_ISA_MEMTAG         (aarch64_isa_flags & AARCH64_FL_MEMTAG)
 210 #define AARCH64_ISA_V8_6A          (aarch64_isa_flags & AARCH64_FL_V8_6A)
 211 #define AARCH64_ISA_I8MM           (aarch64_isa_flags & AARCH64_FL_I8MM)
 212 #define AARCH64_ISA_F32MM          (aarch64_isa_flags & AARCH64_FL_F32MM)
 213 #define AARCH64_ISA_F64MM          (aarch64_isa_flags & AARCH64_FL_F64MM)
 214 #define AARCH64_ISA_BF16           (aarch64_isa_flags & AARCH64_FL_BF16)
 215 #define AARCH64_ISA_SB             (aarch64_isa_flags & AARCH64_FL_SB)
 216 #define AARCH64_ISA_V8R            (aarch64_isa_flags & AARCH64_FL_V8R)
 217 #define AARCH64_ISA_PAUTH          (aarch64_isa_flags & AARCH64_FL_PAUTH)
 218 #define AARCH64_ISA_V9A            (aarch64_isa_flags & AARCH64_FL_V9A)
 219 #define AARCH64_ISA_V9_1A          (aarch64_isa_flags & AARCH64_FL_V9_1A)
 220 #define AARCH64_ISA_V9_2A          (aarch64_isa_flags & AARCH64_FL_V9_2A)
 221 #define AARCH64_ISA_V9_3A          (aarch64_isa_flags & AARCH64_FL_V9_3A)
 222 #define AARCH64_ISA_MOPS           (aarch64_isa_flags & AARCH64_FL_MOPS)
 223 #define AARCH64_ISA_LS64           (aarch64_isa_flags & AARCH64_FL_LS64)
 224 #define AARCH64_ISA_CSSC           (aarch64_isa_flags & AARCH64_FL_CSSC)
 225
 226 /* Crypto is an optional extension to AdvSIMD.  */
 227 #define TARGET_CRYPTO (AARCH64_ISA_CRYPTO)
 228
 229 /* SHA2 is an optional extension to AdvSIMD.  */
 230 #define TARGET_SHA2 (AARCH64_ISA_SHA2)
 231
 232 /* SHA3 is an optional extension to AdvSIMD.  */
 233 #define TARGET_SHA3 (AARCH64_ISA_SHA3)
 234
 235 /* AES is an optional extension to AdvSIMD.  */
 236 #define TARGET_AES (AARCH64_ISA_AES)
 237
 238 /* SM is an optional extension to AdvSIMD.  */
 239 #define TARGET_SM4 (AARCH64_ISA_SM4)
 240
 241 /* FP16FML is an optional extension to AdvSIMD.  */
 242 #define TARGET_F16FML (TARGET_SIMD && AARCH64_ISA_F16FML && TARGET_FP_F16INST)
 243
 244 /* CRC instructions that can be enabled through +crc arch extension.  */
 245 #define TARGET_CRC32 (AARCH64_ISA_CRC)
 246
 247 /* Atomic instructions that can be enabled through the +lse extension.  */
 248 #define TARGET_LSE (AARCH64_ISA_LSE)
 249
 250 /* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension.  */
 251 #define TARGET_FP_F16INST (AARCH64_ISA_F16)
 252 #define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16)
 253
 254 /* Dot Product is an optional extension to AdvSIMD enabled through +dotprod.  */
 255 #define TARGET_DOTPROD (AARCH64_ISA_DOTPROD)
 256
 257 /* SVE instructions, enabled through +sve.  */
 258 #define TARGET_SVE (AARCH64_ISA_SVE)
 259
 260 /* SVE2 instructions, enabled through +sve2.  */
 261 #define TARGET_SVE2 (AARCH64_ISA_SVE2)
 262
 263 /* SVE2 AES instructions, enabled through +sve2-aes.  */
 264 #define TARGET_SVE2_AES (AARCH64_ISA_SVE2_AES)
 265
 266 /* SVE2 BITPERM instructions, enabled through +sve2-bitperm.  */
 267 #define TARGET_SVE2_BITPERM (AARCH64_ISA_SVE2_BITPERM)
 268
 269 /* SVE2 SHA3 instructions, enabled through +sve2-sha3.  */
 270 #define TARGET_SVE2_SHA3 (AARCH64_ISA_SVE2_SHA3)
 271
 272 /* SVE2 SM4 instructions, enabled through +sve2-sm4.  */
 273 #define TARGET_SVE2_SM4 (AARCH64_ISA_SVE2_SM4)
 274
 275 /* ARMv8.3-A features.  */
 276 #define TARGET_ARMV8_3  (AARCH64_ISA_V8_3A)
 277
 278 /* Javascript conversion instruction from Armv8.3-a.  */
 279 #define TARGET_JSCVT    (TARGET_FLOAT && AARCH64_ISA_V8_3A)
 280
 281 /* Armv8.3-a Complex number extension to AdvSIMD extensions.  */
 282 #define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3)
 283
 284 /* Floating-point rounding instructions from Armv8.5-a.  */
 285 #define TARGET_FRINT (AARCH64_ISA_V8_5A && TARGET_FLOAT)
 286
 287 /* TME instructions are enabled.  */
 288 #define TARGET_TME (AARCH64_ISA_TME)
 289
 290 /* Random number instructions from Armv8.5-a.  */
 291 #define TARGET_RNG (AARCH64_ISA_RNG)
 292
 293 /* Memory Tagging instructions optional to Armv8.5 enabled through +memtag.  */
 294 #define TARGET_MEMTAG (AARCH64_ISA_MEMTAG)
 295
 296 /* I8MM instructions are enabled through +i8mm.  */
 297 #define TARGET_I8MM (AARCH64_ISA_I8MM)
 298 #define TARGET_SVE_I8MM (TARGET_SVE && AARCH64_ISA_I8MM)
 299
 300 /* F32MM instructions are enabled through +f32mm.  */
 301 #define TARGET_SVE_F32MM (AARCH64_ISA_F32MM)
 302
 303 /* F64MM instructions are enabled through +f64mm.  */
 304 #define TARGET_SVE_F64MM (AARCH64_ISA_F64MM)
 305
 306 /* BF16 instructions are enabled through +bf16.  */
 307 #define TARGET_BF16_FP (AARCH64_ISA_BF16)
 308 #define TARGET_BF16_SIMD (AARCH64_ISA_BF16 && TARGET_SIMD)
 309 #define TARGET_SVE_BF16 (TARGET_SVE && AARCH64_ISA_BF16)
 310
 311 /* PAUTH instructions are enabled through +pauth.  */
 312 #define TARGET_PAUTH (AARCH64_ISA_PAUTH)
 313
 314 /* BTI instructions exist from Armv8.5-a onwards.  Their automatic use is
 315    enabled through -mbranch-protection by using NOP-space instructions,
 316    but this TARGET_ is used for defining BTI-related ACLE things.  */
 317 #define TARGET_BTI (AARCH64_ISA_V8_5A)
 318
 319 /* MOPS instructions are enabled through +mops.  */
 320 #define TARGET_MOPS (AARCH64_ISA_MOPS)
 321
 322 /* LS64 instructions are enabled through +ls64.  */
 323 #define TARGET_LS64 (AARCH64_ISA_LS64)
 324
 325 /* CSSC instructions are enabled through +cssc.  */
 326 #define TARGET_CSSC (AARCH64_ISA_CSSC)
 327
 328 /* Make sure this is always defined so we don't have to check for ifdefs
 329    but rather use normal ifs.  */
 330 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
 331 #define TARGET_FIX_ERR_A53_835769_DEFAULT 0
 332 #else
 333 #undef TARGET_FIX_ERR_A53_835769_DEFAULT
 334 #define TARGET_FIX_ERR_A53_835769_DEFAULT 1
 335 #endif
 336
 337 /* SB instruction is enabled through +sb.  */
 338 #define TARGET_SB (AARCH64_ISA_SB)
 339
 340 /* RCPC loads from Armv8.3-a.  */
 341 #define TARGET_RCPC (AARCH64_ISA_RCPC)
 342
 343 /* The RCPC2 extensions from Armv8.4-a that allow immediate offsets to LDAPR
 344    and sign-extending versions.*/
 345 #define TARGET_RCPC2 (AARCH64_ISA_RCPC8_4)
 346
 347 /* Apply the workaround for Cortex-A53 erratum 835769.  */
 348 #define TARGET_FIX_ERR_A53_835769       \
 349   ((aarch64_fix_a53_err835769 == 2)     \
 350   ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769)
 351
 352 /* Make sure this is always defined so we don't have to check for ifdefs
 353    but rather use normal ifs.  */
 354 #ifndef TARGET_FIX_ERR_A53_843419_DEFAULT
 355 #define TARGET_FIX_ERR_A53_843419_DEFAULT 0
 356 #else
 357 #undef TARGET_FIX_ERR_A53_843419_DEFAULT
 358 #define TARGET_FIX_ERR_A53_843419_DEFAULT 1
 359 #endif
 360
 361 /* Apply the workaround for Cortex-A53 erratum 843419.  */
 362 #define TARGET_FIX_ERR_A53_843419       \
 363   ((aarch64_fix_a53_err843419 == 2)     \
 364   ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419)
 365
 366 /* ARMv8.1-A Adv.SIMD support.  */
 367 #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA)
 368
 369 /* Standard register usage.  */
 370
 371 /* 31 64-bit general purpose registers R0-R30:
 372    R30          LR (link register)
 373    R29          FP (frame pointer)
 374    R19-R28      Callee-saved registers
 375    R18          The platform register; use as temporary register.
 376    R17          IP1 The second intra-procedure-call temporary register
 377                 (can be used by call veneers and PLT code); otherwise use
 378                 as a temporary register
 379    R16          IP0 The first intra-procedure-call temporary register (can
 380                 be used by call veneers and PLT code); otherwise use as a
 381                 temporary register
 382    R9-R15       Temporary registers
 383    R8           Structure value parameter / temporary register
 384    R0-R7        Parameter/result registers
 385
 386    SP           stack pointer, encoded as X/R31 where permitted.
 387    ZR           zero register, encoded as X/R31 elsewhere
 388
 389    32 x 128-bit floating-point/vector registers
 390    V16-V31      Caller-saved (temporary) registers
 391    V8-V15       Callee-saved registers
 392    V0-V7        Parameter/result registers
 393
 394    The vector register V0 holds scalar B0, H0, S0 and D0 in its least
 395    significant bits.  Unlike AArch32 S1 is not packed into D0, etc.
 396
 397    P0-P7        Predicate low registers: valid in all predicate contexts
 398    P8-P15       Predicate high registers: used as scratch space
 399
 400    FFR          First Fault Register, a fixed-use SVE predicate register
 401    FFRT         FFR token: a fake register used for modelling dependencies
 402
 403    VG           Pseudo "vector granules" register
 404
 405    VG is the number of 64-bit elements in an SVE vector.  We define
 406    it as a hard register so that we can easily map it to the DWARF VG
 407    register.  GCC internally uses the poly_int variable aarch64_sve_vg
 408    instead.  */
 409
 410 #define FIXED_REGISTERS                                 \
 411   {                                                     \
 412     0, 0, 0, 0,   0, 0, 0, 0,   /* R0 - R7 */           \
 413     0, 0, 0, 0,   0, 0, 0, 0,   /* R8 - R15 */          \
 414     0, 0, 0, 0,   0, 0, 0, 0,   /* R16 - R23 */         \
 415     0, 0, 0, 0,   0, 1, 0, 1,   /* R24 - R30, SP */     \
 416     0, 0, 0, 0,   0, 0, 0, 0,   /* V0 - V7 */           \
 417     0, 0, 0, 0,   0, 0, 0, 0,   /* V8 - V15 */          \
 418     0, 0, 0, 0,   0, 0, 0, 0,   /* V16 - V23 */         \
 419     0, 0, 0, 0,   0, 0, 0, 0,   /* V24 - V31 */         \
 420     1, 1, 1, 1,                 /* SFP, AP, CC, VG */   \
 421     0, 0, 0, 0,   0, 0, 0, 0,   /* P0 - P7 */           \
 422     0, 0, 0, 0,   0, 0, 0, 0,   /* P8 - P15 */          \
 423     1, 1                        /* FFR and FFRT */      \
 424   }
 425
 426 /* X30 is marked as caller-saved which is in line with regular function call
 427    behavior since the call instructions clobber it; AARCH64_EXPAND_CALL does
 428    that for regular function calls and avoids it for sibcalls.  X30 is
 429    considered live for sibcalls; EPILOGUE_USES helps achieve that by returning
 430    true but not until function epilogues have been generated.  This ensures
 431    that X30 is available for use in leaf functions if needed.  */
 432
 433 #define CALL_USED_REGISTERS                             \
 434   {                                                     \
 435     1, 1, 1, 1,   1, 1, 1, 1,   /* R0 - R7 */           \
 436     1, 1, 1, 1,   1, 1, 1, 1,   /* R8 - R15 */          \
 437     1, 1, 1, 0,   0, 0, 0, 0,   /* R16 - R23 */         \
 438     0, 0, 0, 0,   0, 1, 1, 1,   /* R24 - R30, SP */     \
 439     1, 1, 1, 1,   1, 1, 1, 1,   /* V0 - V7 */           \
 440     0, 0, 0, 0,   0, 0, 0, 0,   /* V8 - V15 */          \
 441     1, 1, 1, 1,   1, 1, 1, 1,   /* V16 - V23 */         \
 442     1, 1, 1, 1,   1, 1, 1, 1,   /* V24 - V31 */         \
 443     1, 1, 1, 1,                 /* SFP, AP, CC, VG */   \
 444     1, 1, 1, 1,   1, 1, 1, 1,   /* P0 - P7 */           \
 445     1, 1, 1, 1,   1, 1, 1, 1,   /* P8 - P15 */          \
 446     1, 1                        /* FFR and FFRT */      \
 447   }
 448
 449 #define REGISTER_NAMES                                          \
 450   {                                                             \
 451     "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",      \
 452     "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",     \
 453     "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",     \
 454     "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp",      \
 455     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",      \
 456     "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",     \
 457     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",     \
 458     "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",     \
 459     "sfp", "ap",  "cc",  "vg",                                  \
 460     "p0",  "p1",  "p2",  "p3",  "p4",  "p5",  "p6",  "p7",      \
 461     "p8",  "p9",  "p10", "p11", "p12", "p13", "p14", "p15",     \
 462     "ffr", "ffrt"                                               \
 463   }
 464
 465 /* Generate the register aliases for core register N */
 466 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \
 467                      {"w" # N, R0_REGNUM + (N)}
 468
 469 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \
 470                      {"d" # N, V0_REGNUM + (N)}, \
 471                      {"s" # N, V0_REGNUM + (N)}, \
 472                      {"h" # N, V0_REGNUM + (N)}, \
 473                      {"b" # N, V0_REGNUM + (N)}, \
 474                      {"z" # N, V0_REGNUM + (N)}
 475
 476 /* Provide aliases for all of the ISA defined register name forms.
 477    These aliases are convenient for use in the clobber lists of inline
 478    asm statements.  */
 479
 480 #define ADDITIONAL_REGISTER_NAMES \
 481   { R_ALIASES(0),  R_ALIASES(1),  R_ALIASES(2),  R_ALIASES(3),  \
 482     R_ALIASES(4),  R_ALIASES(5),  R_ALIASES(6),  R_ALIASES(7),  \
 483     R_ALIASES(8),  R_ALIASES(9),  R_ALIASES(10), R_ALIASES(11), \
 484     R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \
 485     R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \
 486     R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \
 487     R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \
 488     R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \
 489     V_ALIASES(0),  V_ALIASES(1),  V_ALIASES(2),  V_ALIASES(3),  \
 490     V_ALIASES(4),  V_ALIASES(5),  V_ALIASES(6),  V_ALIASES(7),  \
 491     V_ALIASES(8),  V_ALIASES(9),  V_ALIASES(10), V_ALIASES(11), \
 492     V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \
 493     V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \
 494     V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \
 495     V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \
 496     V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31)  \
 497   }
 498
 499 #define EPILOGUE_USES(REGNO) (aarch64_epilogue_uses (REGNO))
 500
 501 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 502    the stack pointer does not matter.  This is only true if the function
 503    uses alloca.  */
 504 #define EXIT_IGNORE_STACK       (cfun->calls_alloca)
 505
 506 #define STATIC_CHAIN_REGNUM             R18_REGNUM
 507 #define HARD_FRAME_POINTER_REGNUM       R29_REGNUM
 508 #define FRAME_POINTER_REGNUM            SFP_REGNUM
 509 #define STACK_POINTER_REGNUM            SP_REGNUM
 510 #define ARG_POINTER_REGNUM              AP_REGNUM
 511 #define FIRST_PSEUDO_REGISTER           (FFRT_REGNUM + 1)
 512
 513 /* The number of argument registers available for each class.  */
 514 #define NUM_ARG_REGS                    8
 515 #define NUM_FP_ARG_REGS                 8
 516 #define NUM_PR_ARG_REGS                 4
 517
 518 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
 519    four members.  */
 520 #define HA_MAX_NUM_FLDS         4
 521
 522 /* External dwarf register number scheme.  These number are used to
 523    identify registers in dwarf debug information, the values are
 524    defined by the AArch64 ABI.  The numbering scheme is independent of
 525    GCC's internal register numbering scheme.  */
 526
 527 #define AARCH64_DWARF_R0        0
 528
 529 /* The number of R registers, note 31! not 32.  */
 530 #define AARCH64_DWARF_NUMBER_R 31
 531
 532 #define AARCH64_DWARF_SP       31
 533 #define AARCH64_DWARF_VG       46
 534 #define AARCH64_DWARF_P0       48
 535 #define AARCH64_DWARF_V0       64
 536
 537 /* The number of V registers.  */
 538 #define AARCH64_DWARF_NUMBER_V 32
 539
 540 /* For signal frames we need to use an alternative return column.  This
 541    value must not correspond to a hard register and must be out of the
 542    range of DWARF_FRAME_REGNUM().  */
 543 #define DWARF_ALT_FRAME_RETURN_COLUMN   \
 544   (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V)
 545
 546 /* We add 1 extra frame register for use as the
 547    DWARF_ALT_FRAME_RETURN_COLUMN.  */
 548 #define DWARF_FRAME_REGISTERS           (DWARF_ALT_FRAME_RETURN_COLUMN + 1)
 549
 550
 551 #define DEBUGGER_REGNO(REGNO)   aarch64_debugger_regno (REGNO)
 552 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders
 553    can use DWARF_ALT_FRAME_RETURN_COLUMN defined below.  This is just the same
 554    as the default definition in dwarf2out.cc.  */
 555 #undef DWARF_FRAME_REGNUM
 556 #define DWARF_FRAME_REGNUM(REGNO)       DEBUGGER_REGNO (REGNO)
 557
 558 #define DWARF_FRAME_RETURN_COLUMN       DWARF_FRAME_REGNUM (LR_REGNUM)
 559
 560 #define DWARF2_UNWIND_INFO 1
 561
 562 /* Use R0 through R3 to pass exception handling information.  */
 563 #define EH_RETURN_DATA_REGNO(N) \
 564   ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM)
 565
 566 /* Select a format to encode pointers in exception handling data.  */
 567 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
 568   aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL))
 569
 570 /* Output the assembly strings we want to add to a function definition.  */
 571 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL)      \
 572   aarch64_declare_function_name (STR, NAME, DECL)
 573
 574 /* Output assembly strings for alias definition.  */
 575 #define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET) \
 576   aarch64_asm_output_alias (STR, DECL, TARGET)
 577
 578 /* Output assembly strings for undefined extern symbols.  */
 579 #undef ASM_OUTPUT_EXTERNAL
 580 #define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME) \
 581   aarch64_asm_output_external (STR, DECL, NAME)
 582
 583 /* Output assembly strings after .cfi_startproc is emitted.  */
 584 #define ASM_POST_CFI_STARTPROC  aarch64_post_cfi_startproc
 585
 586 /* For EH returns X4 contains the stack adjustment.  */
 587 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, R4_REGNUM)
 588 #define EH_RETURN_HANDLER_RTX  aarch64_eh_return_handler_rtx ()
 589
 590 #undef TARGET_COMPUTE_FRAME_LAYOUT
 591 #define TARGET_COMPUTE_FRAME_LAYOUT aarch64_layout_frame
 592
 593 /* Register in which the structure value is to be returned.  */
 594 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM
 595
 596 /* Non-zero if REGNO is part of the Core register set.
 597
 598    The rather unusual way of expressing this check is to avoid
 599    warnings when building the compiler when R0_REGNUM is 0 and REGNO
 600    is unsigned.  */
 601 #define GP_REGNUM_P(REGNO)                                              \
 602   (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM))
 603
 604 /* Registers known to be preserved over a BL instruction.  This consists of the
 605    GENERAL_REGS without x16, x17, and x30.  The x30 register is changed by the
 606    BL instruction itself, while the x16 and x17 registers may be used by
 607    veneers which can be inserted by the linker.  */
 608 #define STUB_REGNUM_P(REGNO) \
 609   (GP_REGNUM_P (REGNO) \
 610    && (REGNO) != R16_REGNUM \
 611    && (REGNO) != R17_REGNUM \
 612    && (REGNO) != R30_REGNUM) \
 613
 614 #define FP_REGNUM_P(REGNO)                      \
 615   (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM))
 616
 617 #define FP_LO_REGNUM_P(REGNO)            \
 618   (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM))
 619
 620 #define FP_LO8_REGNUM_P(REGNO)            \
 621   (((unsigned) (REGNO - V0_REGNUM)) <= (V7_REGNUM - V0_REGNUM))
 622
 623 #define PR_REGNUM_P(REGNO)\
 624   (((unsigned) (REGNO - P0_REGNUM)) <= (P15_REGNUM - P0_REGNUM))
 625
 626 #define PR_LO_REGNUM_P(REGNO)\
 627   (((unsigned) (REGNO - P0_REGNUM)) <= (P7_REGNUM - P0_REGNUM))
 628
 629 #define FP_SIMD_SAVED_REGNUM_P(REGNO)                   \
 630   (((unsigned) (REGNO - V8_REGNUM)) <= (V23_REGNUM - V8_REGNUM))
 631 \f
 632 /* Register and constant classes.  */
 633
 634 enum reg_class
 635 {
 636   NO_REGS,
 637   TAILCALL_ADDR_REGS,
 638   STUB_REGS,
 639   GENERAL_REGS,
 640   STACK_REG,
 641   POINTER_REGS,
 642   FP_LO8_REGS,
 643   FP_LO_REGS,
 644   FP_REGS,
 645   POINTER_AND_FP_REGS,
 646   PR_LO_REGS,
 647   PR_HI_REGS,
 648   PR_REGS,
 649   FFR_REGS,
 650   PR_AND_FFR_REGS,
 651   ALL_REGS,
 652   LIM_REG_CLASSES               /* Last */
 653 };
 654
 655 #define N_REG_CLASSES   ((int) LIM_REG_CLASSES)
 656
 657 #define REG_CLASS_NAMES                         \
 658 {                                               \
 659   "NO_REGS",                                    \
 660   "TAILCALL_ADDR_REGS",                         \
 661   "STUB_REGS",                                  \
 662   "GENERAL_REGS",                               \
 663   "STACK_REG",                                  \
 664   "POINTER_REGS",                               \
 665   "FP_LO8_REGS",                                \
 666   "FP_LO_REGS",                                 \
 667   "FP_REGS",                                    \
 668   "POINTER_AND_FP_REGS",                        \
 669   "PR_LO_REGS",                                 \
 670   "PR_HI_REGS",                                 \
 671   "PR_REGS",                                    \
 672   "FFR_REGS",                                   \
 673   "PR_AND_FFR_REGS",                            \
 674   "ALL_REGS"                                    \
 675 }
 676
 677 #define REG_CLASS_CONTENTS                                              \
 678 {                                                                       \
 679   { 0x00000000, 0x00000000, 0x00000000 },       /* NO_REGS */           \
 680   { 0x00030000, 0x00000000, 0x00000000 },       /* TAILCALL_ADDR_REGS */\
 681   { 0x3ffcffff, 0x00000000, 0x00000000 },       /* STUB_REGS */         \
 682   { 0x7fffffff, 0x00000000, 0x00000003 },       /* GENERAL_REGS */      \
 683   { 0x80000000, 0x00000000, 0x00000000 },       /* STACK_REG */         \
 684   { 0xffffffff, 0x00000000, 0x00000003 },       /* POINTER_REGS */      \
 685   { 0x00000000, 0x000000ff, 0x00000000 },       /* FP_LO8_REGS  */      \
 686   { 0x00000000, 0x0000ffff, 0x00000000 },       /* FP_LO_REGS  */       \
 687   { 0x00000000, 0xffffffff, 0x00000000 },       /* FP_REGS  */          \
 688   { 0xffffffff, 0xffffffff, 0x00000003 },       /* POINTER_AND_FP_REGS */\
 689   { 0x00000000, 0x00000000, 0x00000ff0 },       /* PR_LO_REGS */        \
 690   { 0x00000000, 0x00000000, 0x000ff000 },       /* PR_HI_REGS */        \
 691   { 0x00000000, 0x00000000, 0x000ffff0 },       /* PR_REGS */           \
 692   { 0x00000000, 0x00000000, 0x00300000 },       /* FFR_REGS */          \
 693   { 0x00000000, 0x00000000, 0x003ffff0 },       /* PR_AND_FFR_REGS */   \
 694   { 0xffffffff, 0xffffffff, 0x000fffff }        /* ALL_REGS */          \
 695 }
 696
 697 #define REGNO_REG_CLASS(REGNO)  aarch64_regno_regclass (REGNO)
 698
 699 #define INDEX_REG_CLASS GENERAL_REGS
 700 #define BASE_REG_CLASS  POINTER_REGS
 701
 702 /* Register pairs used to eliminate unneeded registers that point into
 703    the stack frame.  */
 704 #define ELIMINABLE_REGS                                                 \
 705 {                                                                       \
 706   { ARG_POINTER_REGNUM,         STACK_POINTER_REGNUM            },      \
 707   { ARG_POINTER_REGNUM,         HARD_FRAME_POINTER_REGNUM       },      \
 708   { FRAME_POINTER_REGNUM,       STACK_POINTER_REGNUM            },      \
 709   { FRAME_POINTER_REGNUM,       HARD_FRAME_POINTER_REGNUM       },      \
 710 }
 711
 712 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 713   (OFFSET) = aarch64_initial_elimination_offset (FROM, TO)
 714
 715 /* CPU/ARCH option handling.  */
 716 #include "config/aarch64/aarch64-opts.h"
 717
 718 enum target_cpus
 719 {
 720 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
 721   TARGET_CPU_##INTERNAL_IDENT,
 722 #include "aarch64-cores.def"
 723   TARGET_CPU_generic
 724 };
 725
 726 /* If there is no CPU defined at configure, use generic as default.  */
 727 #ifndef TARGET_CPU_DEFAULT
 728 # define TARGET_CPU_DEFAULT TARGET_CPU_generic
 729 #endif
 730
 731 /* If inserting NOP before a mult-accumulate insn remember to adjust the
 732    length so that conditional branching code is updated appropriately.  */
 733 #define ADJUST_INSN_LENGTH(insn, length)        \
 734   do                                            \
 735     {                                           \
 736        if (aarch64_madd_needs_nop (insn))       \
 737          length += 4;                           \
 738     } while (0)
 739
 740 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)      \
 741     aarch64_final_prescan_insn (INSN);                  \
 742
 743 /* The processor for which instructions should be scheduled.  */
 744 extern enum aarch64_processor aarch64_tune;
 745
 746 /* RTL generation support.  */
 747 #define INIT_EXPANDERS aarch64_init_expanders ()
 748 \f
 749
 750 /* Stack layout; function entry, exit and calling.  */
 751 #define STACK_GROWS_DOWNWARD    1
 752
 753 #define FRAME_GROWS_DOWNWARD    1
 754
 755 #define ACCUMULATE_OUTGOING_ARGS        1
 756
 757 #define FIRST_PARM_OFFSET(FNDECL) 0
 758
 759 /* Fix for VFP */
 760 #define LIBCALL_VALUE(MODE)  \
 761   gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM)
 762
 763 #define DEFAULT_PCC_STRUCT_RETURN 0
 764
 765 #ifdef HAVE_POLY_INT_H
 766 struct GTY (()) aarch64_frame
 767 {
 768   /* The offset from the bottom of the static frame (the bottom of the
 769      outgoing arguments) of each register save slot, or -2 if no save is
 770      needed.  */
 771   poly_int64 reg_offset[LAST_SAVED_REGNUM + 1];
 772
 773   /* The number of extra stack bytes taken up by register varargs.
 774      This area is allocated by the callee at the very top of the
 775      frame.  This value is rounded up to a multiple of
 776      STACK_BOUNDARY.  */
 777   HOST_WIDE_INT saved_varargs_size;
 778
 779   /* The number of bytes between the bottom of the static frame (the bottom
 780      of the outgoing arguments) and the bottom of the register save area.
 781      This value is always a multiple of STACK_BOUNDARY.  */
 782   poly_int64 bytes_below_saved_regs;
 783
 784   /* The number of bytes between the bottom of the static frame (the bottom
 785      of the outgoing arguments) and the hard frame pointer.  This value is
 786      always a multiple of STACK_BOUNDARY.  */
 787   poly_int64 bytes_below_hard_fp;
 788
 789   /* The number of bytes between the top of the locals area and the top
 790      of the frame (the incomming SP).  This value is always a multiple of
 791      STACK_BOUNDARY.  */
 792   poly_int64 bytes_above_locals;
 793
 794   /* The number of bytes between the hard_frame_pointer and the top of
 795      the frame (the incomming SP).  This value is always a multiple of
 796      STACK_BOUNDARY.  */
 797   poly_int64 bytes_above_hard_fp;
 798
 799   /* The size of the frame, i.e. the number of bytes between the bottom
 800      of the outgoing arguments and the incoming SP.  This value is always
 801      a multiple of STACK_BOUNDARY.  */
 802   poly_int64 frame_size;
 803
 804   /* The size of the initial stack adjustment before saving callee-saves.  */
 805   poly_int64 initial_adjust;
 806
 807   /* The writeback value when pushing callee-save registers.
 808      It is zero when no push is used.  */
 809   HOST_WIDE_INT callee_adjust;
 810
 811   /* The size of the stack adjustment before saving or after restoring
 812      SVE registers.  */
 813   poly_int64 sve_callee_adjust;
 814
 815   /* The size of the stack adjustment after saving callee-saves.  */
 816   poly_int64 final_adjust;
 817
 818   /* Store FP,LR and setup a frame pointer.  */
 819   bool emit_frame_chain;
 820
 821   /* In each frame, we can associate up to two register saves with the
 822      initial stack allocation.  This happens in one of two ways:
 823
 824      (1) Using an STR or STP with writeback to perform the initial
 825          stack allocation.  When EMIT_FRAME_CHAIN, the registers will
 826          be those needed to create a frame chain.
 827
 828          Indicated by CALLEE_ADJUST != 0.
 829
 830      (2) Using a separate STP to set up the frame record, after the
 831          initial stack allocation but before setting up the frame pointer.
 832          This is used if the offset is too large to use writeback.
 833
 834          Indicated by CALLEE_ADJUST == 0 && EMIT_FRAME_CHAIN.
 835
 836      These fields indicate which registers we've decided to handle using
 837      (1) or (2), or INVALID_REGNUM if none.
 838
 839      In some cases we don't always need to pop all registers in the push
 840      candidates, pop candidates record which registers need to be popped
 841      eventually.  The initial value of a pop candidate is copied from its
 842      corresponding push candidate.
 843
 844      Currently, different pop candidates are only used for shadow call
 845      stack.  When "-fsanitize=shadow-call-stack" is specified, we replace
 846      x30 in the pop candidate with INVALID_REGNUM to ensure that x30 is
 847      not popped twice.  */
 848   unsigned wb_push_candidate1;
 849   unsigned wb_push_candidate2;
 850   unsigned wb_pop_candidate1;
 851   unsigned wb_pop_candidate2;
 852
 853   /* Big-endian SVE frames need a spare predicate register in order
 854      to save vector registers in the correct layout for unwinding.
 855      This is the register they should use.  */
 856   unsigned spare_pred_reg;
 857
 858   /* An SVE register that is saved below the hard frame pointer and that acts
 859      as a probe for later allocations, or INVALID_REGNUM if none.  */
 860   unsigned sve_save_and_probe;
 861
 862   /* A register that is saved at the hard frame pointer and that acts
 863      as a probe for later allocations, or INVALID_REGNUM if none.  */
 864   unsigned hard_fp_save_and_probe;
 865
 866   bool laid_out;
 867
 868   /* True if shadow call stack should be enabled for the current function.  */
 869   bool is_scs_enabled;
 870 };
 871
 872 #ifdef hash_set_h
 873 typedef struct GTY (()) machine_function
 874 {
 875   struct aarch64_frame frame;
 876   /* One entry for each hard register.  */
 877   bool reg_is_wrapped_separately[LAST_SAVED_REGNUM];
 878   /* One entry for each general purpose register.  */
 879   rtx call_via[SP_REGNUM];
 880   bool label_is_assembled;
 881   /* A set of all decls that have been passed to a vld1 intrinsic in the
 882      current function.  This is used to help guide the vector cost model.  */
 883   hash_set<tree> *vector_load_decls;
 884 } machine_function;
 885 #endif
 886 #endif
 887
 888 /* Which ABI to use.  */
 889 enum aarch64_abi_type
 890 {
 891   AARCH64_ABI_LP64 = 0,
 892   AARCH64_ABI_ILP32 = 1
 893 };
 894
 895 #ifndef AARCH64_ABI_DEFAULT
 896 #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64
 897 #endif
 898
 899 #define TARGET_ILP32    (aarch64_abi & AARCH64_ABI_ILP32)
 900
 901 enum arm_pcs
 902 {
 903   ARM_PCS_AAPCS64,              /* Base standard AAPCS for 64 bit.  */
 904   ARM_PCS_SIMD,                 /* For aarch64_vector_pcs functions.  */
 905   ARM_PCS_SVE,                  /* For functions that pass or return
 906                                    values in SVE registers.  */
 907   ARM_PCS_TLSDESC,              /* For targets of tlsdesc calls.  */
 908   ARM_PCS_UNKNOWN
 909 };
 910
 911
 912
 913
 914 /* We can't use machine_mode inside a generator file because it
 915    hasn't been created yet; we shouldn't be using any code that
 916    needs the real definition though, so this ought to be safe.  */
 917 #ifdef GENERATOR_FILE
 918 #define MACHMODE int
 919 #else
 920 #include "insn-modes.h"
 921 #define MACHMODE machine_mode
 922 #endif
 923
 924 #ifndef USED_FOR_TARGET
 925 /* AAPCS related state tracking.  */
 926 typedef struct
 927 {
 928   enum arm_pcs pcs_variant;
 929   int aapcs_arg_processed;      /* No need to lay out this argument again.  */
 930   int aapcs_ncrn;               /* Next Core register number.  */
 931   int aapcs_nextncrn;           /* Next next core register number.  */
 932   int aapcs_nvrn;               /* Next Vector register number.  */
 933   int aapcs_nextnvrn;           /* Next Next Vector register number.  */
 934   int aapcs_nprn;               /* Next Predicate register number.  */
 935   int aapcs_nextnprn;           /* Next Next Predicate register number.  */
 936   rtx aapcs_reg;                /* Register assigned to this argument.  This
 937                                    is NULL_RTX if this parameter goes on
 938                                    the stack.  */
 939   MACHMODE aapcs_vfp_rmode;
 940   int aapcs_stack_words;        /* If the argument is passed on the stack, this
 941                                    is the number of words needed, after rounding
 942                                    up.  Only meaningful when
 943                                    aapcs_reg == NULL_RTX.  */
 944   int aapcs_stack_size;         /* The total size (in words, per 8 byte) of the
 945                                    stack arg area so far.  */
 946   bool silent_p;                /* True if we should act silently, rather than
 947                                    raise an error for invalid calls.  */
 948 } CUMULATIVE_ARGS;
 949 #endif
 950
 951 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
 952   (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD)
 953
 954 #define PAD_VARARGS_DOWN        0
 955
 956 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
 957   aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS)
 958
 959 #define FUNCTION_ARG_REGNO_P(REGNO) \
 960   aarch64_function_arg_regno_p(REGNO)
 961 \f
 962
 963 /* ISA Features.  */
 964
 965 /* Addressing modes, etc.  */
 966 #define HAVE_POST_INCREMENT     1
 967 #define HAVE_PRE_INCREMENT      1
 968 #define HAVE_POST_DECREMENT     1
 969 #define HAVE_PRE_DECREMENT      1
 970 #define HAVE_POST_MODIFY_DISP   1
 971 #define HAVE_PRE_MODIFY_DISP    1
 972
 973 #define MAX_REGS_PER_ADDRESS    2
 974
 975 #define CONSTANT_ADDRESS_P(X)           aarch64_constant_address_p(X)
 976
 977 #define REGNO_OK_FOR_BASE_P(REGNO)      \
 978   aarch64_regno_ok_for_base_p (REGNO, true)
 979
 980 #define REGNO_OK_FOR_INDEX_P(REGNO) \
 981   aarch64_regno_ok_for_index_p (REGNO, true)
 982
 983 #define LEGITIMATE_PIC_OPERAND_P(X) \
 984   aarch64_legitimate_pic_operand_p (X)
 985
 986 #define CASE_VECTOR_MODE Pmode
 987
 988 #define DEFAULT_SIGNED_CHAR 0
 989
 990 /* An integer expression for the size in bits of the largest integer machine
 991    mode that should actually be used.  We allow pairs of registers.  */
 992 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
 993
 994 /* Maximum bytes moved by a single instruction (load/store pair).  */
 995 #define MOVE_MAX (UNITS_PER_WORD * 2)
 996
 997 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends.  */
 998 #define AARCH64_CALL_RATIO 8
 999
1000 /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure.
1001    move_by_pieces will continually copy the largest safe chunks.  So a
1002    7-byte copy is a 4-byte + 2-byte + byte copy.  This proves inefficient
1003    for both size and speed of copy, so we will instead use the "cpymem"
1004    standard name to implement the copy.  This logic does not apply when
1005    targeting -mstrict-align or TARGET_MOPS, so keep a sensible default in
1006    that case.  */
1007 #define MOVE_RATIO(speed) \
1008   ((!STRICT_ALIGNMENT || TARGET_MOPS) ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2))
1009
1010 /* Like MOVE_RATIO, without -mstrict-align, make decisions in "setmem" when
1011    we would use more than 3 scalar instructions.
1012    Otherwise follow a sensible default: when optimizing for size, give a better
1013    estimate of the length of a memset call, but use the default otherwise.  */
1014 #define CLEAR_RATIO(speed) \
1015   (!STRICT_ALIGNMENT ? (TARGET_MOPS ? 0 : 4) : (speed) ? 15 : AARCH64_CALL_RATIO)
1016
1017 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant.  Without
1018    -mstrict-align, make decisions in "setmem".  Otherwise follow a sensible
1019    default: when optimizing for size adjust the ratio to account for the
1020    overhead of loading the constant.  */
1021 #define SET_RATIO(speed) \
1022   ((!STRICT_ALIGNMENT || TARGET_MOPS) ? 0 : (speed) ? 15 : AARCH64_CALL_RATIO - 2)
1023
1024 /* Disable auto-increment in move_by_pieces et al.  Use of auto-increment is
1025    rarely a good idea in straight-line code since it adds an extra address
1026    dependency between each instruction.  Better to use incrementing offsets.  */
1027 #define USE_LOAD_POST_INCREMENT(MODE)   0
1028 #define USE_LOAD_POST_DECREMENT(MODE)   0
1029 #define USE_LOAD_PRE_INCREMENT(MODE)    0
1030 #define USE_LOAD_PRE_DECREMENT(MODE)    0
1031 #define USE_STORE_POST_INCREMENT(MODE)  0
1032 #define USE_STORE_POST_DECREMENT(MODE)  0
1033 #define USE_STORE_PRE_INCREMENT(MODE)   0
1034 #define USE_STORE_PRE_DECREMENT(MODE)   0
1035
1036 /* WORD_REGISTER_OPERATIONS does not hold for AArch64.
1037    The assigned word_mode is DImode but operations narrower than SImode
1038    behave as 32-bit operations if using the W-form of the registers rather
1039    than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS
1040    expects.  */
1041 #define WORD_REGISTER_OPERATIONS 0
1042
1043 /* Define if loading from memory in MODE, an integral mode narrower than
1044    BITS_PER_WORD will either zero-extend or sign-extend.  The value of this
1045    macro should be the code that says which one of the two operations is
1046    implicitly done, or UNKNOWN if none.  */
1047 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1048
1049 /* Define this macro to be non-zero if instructions will fail to work
1050    if given data not on the nominal alignment.  */
1051 #define STRICT_ALIGNMENT                TARGET_STRICT_ALIGN
1052
1053 /* Enable wide bitfield accesses for more efficient bitfield code.  */
1054 #define SLOW_BYTE_ACCESS 1
1055
1056 #define NO_FUNCTION_CSE 1
1057
1058 /* Specify the machine mode that the hardware addresses have.
1059    After generation of rtl, the compiler makes no further distinction
1060    between pointers and any other objects of this machine mode.  */
1061 #define Pmode           DImode
1062
1063 /* A C expression whose value is zero if pointers that need to be extended
1064    from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
1065    greater then zero if they are zero-extended and less then zero if the
1066    ptr_extend instruction should be used.  */
1067 #define POINTERS_EXTEND_UNSIGNED 1
1068
1069 /* Mode of a function address in a call instruction (for indexing purposes).  */
1070 #define FUNCTION_MODE   Pmode
1071
1072 #define SELECT_CC_MODE(OP, X, Y)        aarch64_select_cc_mode (OP, X, Y)
1073
1074 /* Having an integer comparison mode guarantees that we can use
1075    reverse_condition, but the usual restrictions apply to floating-point
1076    comparisons.  */
1077 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPmode && (MODE) != CCFPEmode)
1078
1079 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1080   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1081 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1082   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1083
1084 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
1085
1086 #define RETURN_ADDR_RTX aarch64_return_addr
1087
1088 /* BTI c + 3 insns
1089    + sls barrier of DSB + ISB.
1090    + 2 pointer-sized entries.  */
1091 #define TRAMPOLINE_SIZE (24 + (TARGET_ILP32 ? 8 : 16))
1092
1093 /* Trampolines contain dwords, so must be dword aligned.  */
1094 #define TRAMPOLINE_ALIGNMENT 64
1095
1096 /* Put trampolines in the text section so that mapping symbols work
1097    correctly.  */
1098 #define TRAMPOLINE_SECTION text_section
1099
1100 /* To start with.  */
1101 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \
1102   (aarch64_branch_cost (SPEED_P, PREDICTABLE_P))
1103 \f
1104
1105 /* Assembly output.  */
1106
1107 /* For now we'll make all jump tables pc-relative.  */
1108 #define CASE_VECTOR_PC_RELATIVE 1
1109
1110 #define CASE_VECTOR_SHORTEN_MODE(min, max, body)        \
1111   ((min < -0x1fff0 || max > 0x1fff0) ? SImode           \
1112    : (min < -0x1f0 || max > 0x1f0) ? HImode             \
1113    : QImode)
1114
1115 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL.  */
1116 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
1117
1118 #define MCOUNT_NAME "_mcount"
1119
1120 #define NO_PROFILE_COUNTERS 1
1121
1122 /* Emit rtl for profiling.  Output assembler code to FILE
1123    to call "_mcount" for profiling a function entry.  */
1124 #define PROFILE_HOOK(LABEL)                                             \
1125   {                                                                     \
1126     rtx fun, lr;                                                        \
1127     lr = aarch64_return_addr_rtx ();                                    \
1128     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
1129     emit_library_call (fun, LCT_NORMAL, VOIDmode, lr, Pmode);           \
1130   }
1131
1132 /* All the work done in PROFILE_HOOK, but still required.  */
1133 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
1134
1135 /* For some reason, the Linux headers think they know how to define
1136    these macros.  They don't!!!  */
1137 #undef ASM_APP_ON
1138 #undef ASM_APP_OFF
1139 #define ASM_APP_ON      "\t" ASM_COMMENT_START " Start of user assembly\n"
1140 #define ASM_APP_OFF     "\t" ASM_COMMENT_START " End of user assembly\n"
1141
1142 #define CONSTANT_POOL_BEFORE_FUNCTION 0
1143
1144 /* This definition should be relocated to aarch64-elf-raw.h.  This macro
1145    should be undefined in aarch64-linux.h and a clear_cache pattern
1146    implmented to emit either the call to __aarch64_sync_cache_range()
1147    directly or preferably the appropriate sycall or cache clear
1148    instructions inline.  */
1149 #define CLEAR_INSN_CACHE(beg, end)                              \
1150   extern void  __aarch64_sync_cache_range (void *, void *);     \
1151   __aarch64_sync_cache_range (beg, end)
1152
1153 #define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD)
1154
1155 /* Choose appropriate mode for caller saves, so we do the minimum
1156    required size of load/store.  */
1157 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1158   aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE))
1159
1160 #undef SWITCHABLE_TARGET
1161 #define SWITCHABLE_TARGET 1
1162
1163 /* Check TLS Descriptors mechanism is selected.  */
1164 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS)
1165
1166 extern enum aarch64_code_model aarch64_cmodel;
1167
1168 /* When using the tiny addressing model conditional and unconditional branches
1169    can span the whole of the available address space (1MB).  */
1170 #define HAS_LONG_COND_BRANCH                            \
1171   (aarch64_cmodel == AARCH64_CMODEL_TINY                \
1172    || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
1173
1174 #define HAS_LONG_UNCOND_BRANCH                          \
1175   (aarch64_cmodel == AARCH64_CMODEL_TINY                \
1176    || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
1177
1178 #define TARGET_SUPPORTS_WIDE_INT 1
1179
1180 /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register.  */
1181 #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \
1182   ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1183    || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \
1184    || (MODE) == DFmode || (MODE) == V4BFmode)
1185
1186 /* Modes valid for AdvSIMD Q registers.  */
1187 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \
1188   ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1189    || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \
1190    || (MODE) == V2DFmode || (MODE) == V8BFmode)
1191
1192 #define ENDIAN_LANE_N(NUNITS, N) \
1193   (BYTES_BIG_ENDIAN ? NUNITS - 1 - N : N)
1194
1195 /* Extra specs when building a native AArch64-hosted compiler.
1196    Option rewriting rules based on host system.  */
1197 #if defined(__aarch64__)
1198 extern const char *host_detect_local_cpu (int argc, const char **argv);
1199 #define HAVE_LOCAL_CPU_DETECT
1200 # define EXTRA_SPEC_FUNCTIONS                                           \
1201   { "local_cpu_detect", host_detect_local_cpu },                        \
1202   MCPU_TO_MARCH_SPEC_FUNCTIONS
1203
1204 /* Rewrite -m{arch,cpu,tune}=native based on the host system information.
1205    When rewriting -march=native convert it into an -mcpu option if no other
1206    -mcpu or -mtune was given.  */
1207 # define MCPU_MTUNE_NATIVE_SPECS                                        \
1208    " %{march=native:%<march=native %:local_cpu_detect(%{mcpu=*|mtune=*:arch;:cpu})}"            \
1209    " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}"              \
1210    " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
1211 /* This will be used in OPTION_DEFAULT_SPECS below.
1212    When GCC is configured with --with-tune we don't want to materialize an
1213    implicit -mtune would prevent the rewriting of -march=native into
1214    -mcpu=native as per the above rules.  */
1215 #define CONFIG_TUNE_SPEC                                                \
1216  { "tune", "%{!mcpu=*:%{!mtune=*:%{!march=native:-mtune=%(VALUE)}}}" },
1217 #else
1218 # define MCPU_MTUNE_NATIVE_SPECS ""
1219 # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS
1220 # define CONFIG_TUNE_SPEC                                                \
1221   {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}"},
1222 #endif
1223
1224 /* Support for configure-time --with-arch, --with-cpu and --with-tune.
1225    --with-arch and --with-cpu are ignored if either -mcpu or -march is used.
1226    --with-tune is ignored if either -mtune or -mcpu is used (but is not
1227    affected by -march, except in the -march=native case as per the
1228    CONFIG_TUNE_SPEC above).  */
1229 #define OPTION_DEFAULT_SPECS                            \
1230   {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" },  \
1231   {"cpu",  "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" },   \
1232   CONFIG_TUNE_SPEC
1233
1234 #define MCPU_TO_MARCH_SPEC \
1235    " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}"
1236
1237 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv);
1238 #define MCPU_TO_MARCH_SPEC_FUNCTIONS \
1239   { "rewrite_mcpu", aarch64_rewrite_mcpu },
1240
1241 #define ASM_CPU_SPEC \
1242    MCPU_TO_MARCH_SPEC
1243
1244 #define EXTRA_SPECS                                             \
1245   { "asm_cpu_spec",             ASM_CPU_SPEC }
1246
1247 #define ASM_OUTPUT_POOL_EPILOGUE  aarch64_asm_output_pool_epilogue
1248
1249 /* This type is the user-visible __fp16, and a pointer to that type.  We
1250    need it in many places in the backend.  Defined in aarch64-builtins.cc.  */
1251 extern GTY(()) tree aarch64_fp16_type_node;
1252 extern GTY(()) tree aarch64_fp16_ptr_type_node;
1253
1254 /* Pointer to the user-visible __bf16 type.  __bf16 itself is generic
1255    bfloat16_type_node.  Defined in aarch64-builtins.cc.  */
1256 extern GTY(()) tree aarch64_bf16_ptr_type_node;
1257
1258 /* The generic unwind code in libgcc does not initialize the frame pointer.
1259    So in order to unwind a function using a frame pointer, the very first
1260    function that is unwound must save the frame pointer.  That way the frame
1261    pointer is restored and its value is now valid - otherwise _Unwind_GetGR
1262    crashes.  Libgcc can now be safely built with -fomit-frame-pointer.  */
1263 #define LIBGCC2_UNWIND_ATTRIBUTE \
1264   __attribute__((optimize ("no-omit-frame-pointer")))
1265
1266 #ifndef USED_FOR_TARGET
1267 extern poly_uint16 aarch64_sve_vg;
1268
1269 /* The number of bits and bytes in an SVE vector.  */
1270 #define BITS_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 64))
1271 #define BYTES_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 8))
1272
1273 /* The number of bits and bytes in an SVE predicate.  */
1274 #define BITS_PER_SVE_PRED BYTES_PER_SVE_VECTOR
1275 #define BYTES_PER_SVE_PRED aarch64_sve_vg
1276
1277 /* The SVE mode for a vector of bytes.  */
1278 #define SVE_BYTE_MODE VNx16QImode
1279
1280 /* The maximum number of bytes in a fixed-size vector.  This is 256 bytes
1281    (for -msve-vector-bits=2048) multiplied by the maximum number of
1282    vectors in a structure mode (4).
1283
1284    This limit must not be used for variable-size vectors, since
1285    VL-agnostic code must work with arbitary vector lengths.  */
1286 #define MAX_COMPILE_TIME_VEC_BYTES (256 * 4)
1287 #endif
1288
1289 #define REGMODE_NATURAL_SIZE(MODE) aarch64_regmode_natural_size (MODE)
1290
1291 /* Allocate a minimum of STACK_CLASH_MIN_BYTES_OUTGOING_ARGS bytes for the
1292    outgoing arguments if stack clash protection is enabled.  This is essential
1293    as the extra arg space allows us to skip a check in alloca.  */
1294 #undef STACK_DYNAMIC_OFFSET
1295 #define STACK_DYNAMIC_OFFSET(FUNDECL)                      \
1296    ((flag_stack_clash_protection                           \
1297      && cfun->calls_alloca                                 \
1298      && known_lt (crtl->outgoing_args_size,                \
1299                   STACK_CLASH_MIN_BYTES_OUTGOING_ARGS))    \
1300     ? ROUND_UP (STACK_CLASH_MIN_BYTES_OUTGOING_ARGS,       \
1301                 STACK_BOUNDARY / BITS_PER_UNIT)            \
1302     : (crtl->outgoing_args_size + STACK_POINTER_OFFSET))
1303
1304 /* Filled in by aarch64_adjust_reg_alloc_order, which is called before
1305    the first relevant use.  */
1306 #define REG_ALLOC_ORDER {}
1307 #define ADJUST_REG_ALLOC_ORDER aarch64_adjust_reg_alloc_order ()
1308
1309 #define AARCH64_VALID_SHRN_OP(T,S)                      \
1310 ((T) == TRUNCATE                                        \
1311  || ((T) == US_TRUNCATE && (S) == LSHIFTRT)             \
1312  || ((T) == SS_TRUNCATE && (S) == ASHIFTRT))
1313
1314 #endif /* GCC_AARCH64_H */