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1 ;;- Machine description for GNU compiler, MIL-STD-1750A version.
2 ;; Copyright (C) 1994 Free Software Foundation, Inc.
3 ;; Contributed by O.M.Kellogg, Deutsche Aerospace (okellogg@salyko.cube.net).
4
5 ;; This file is part of GNU CC.
6
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 1, or (at your option)
10 ;; any later version.
11
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21
22 ;;- instruction definitions
23
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25
26 ;;- When naming insn's (operand 0 of define_insn) be careful about using
27 ;;- names from other targets machine descriptions.
28
29 ;; MIL-STD-1750 specific remarks:
30 ;;
31 ;; 1) BITS_PER_UNIT = 16
32 ;;
33 ;; 2) GCC to MIL-STD-1750 data type mappings:
34 ;; QImode => single integer (16 bits or 1 reg).
35 ;; HImode => double integer (32 bits or 2 regs).
36 ;; HFmode => single precision float (32 bits or 2 regs).
37 ;; TQFmode => extended precision float (48 bits or 3 regs).
38 ;;
39 ;; 3) Immediate integer operands Constraints:
40 ;; 'I' 1 .. 16
41 ;; 'J' -1 ..-16
42 ;; 'K' 0 .. 15
43 ;; 'L' 0 .. 255
44 ;; 'M' -32768 .. 32767
45 ;; 'O' => 0 (for optimizations and GCC quirks)
46 ;;
47 ;; Further notes:
48 ;;- Assembly output ending in ".M" are macros in file M1750.INC
49
50
51 ;; stackpush
52 (define_insn ""
53 [(set (match_operand:QI 0 "push_operand" "=<")
54 (match_operand:QI 1 "general_operand" "r"))]
55 ""
56 "PSHM R%1,R%1")
57
58 (define_insn ""
59 [(set (match_operand:HI 0 "push_operand" "=<")
60 (match_operand:HI 1 "general_operand" "r"))]
61 ""
62 "*
63 {
64 rtx new_operands[2];
65 new_operands[0] = operands[1];
66 new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1);
67 } ")
68
69 (define_insn ""
70 [(set (match_operand:HF 0 "push_operand" "=<")
71 (match_operand:HF 1 "general_operand" "r"))]
72 ""
73 "*
74 {
75 rtx new_operands[2];
76 new_operands[0] = operands[1];
77 new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1);
78 output_asm_insn(\"PSHM R%0,R%1\",new_operands);
79 return \"\;\";
80 } ")
81
82 (define_insn ""
83 [(set (match_operand:TQF 0 "push_operand" "=<")
84 (match_operand:TQF 1 "general_operand" "r"))]
85 ""
86 "*
87 {
88 rtx new_operands[2];
89 new_operands[0] = operands[1];
90 new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+2);
91 output_asm_insn(\"PSHM R%0,R%1\",new_operands);
92 return \"\;\";
93 } ")
94
95 ;; stackpop
96 (define_insn ""
97 [(set (match_operand:QI 0 "general_operand" "=r")
98 (match_operand:QI 1 "push_operand" ">"))]
99 ""
100 "POPM R%1,R%1")
101
102 (define_insn ""
103 [(set (match_operand:HI 0 "general_operand" "=r")
104 (match_operand:HI 1 "push_operand" ">"))]
105 ""
106 "*
107 {
108 rtx new_operands[2];
109 new_operands[0] = operands[0];
110 new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1);
111 output_asm_insn(\"POPM R%0,R%1\",new_operands);
112 return \"\;\";
113 } ")
114
115 (define_insn ""
116 [(set (match_operand:HF 0 "general_operand" "=r")
117 (match_operand:HF 1 "push_operand" ">"))]
118 ""
119 "*
120 {
121 rtx new_operands[2];
122 new_operands[0] = operands[0];
123 new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1);
124 output_asm_insn(\"POPM R%0,R%1\",new_operands);
125 return \"\;\";
126 } ")
127
128 (define_insn ""
129 [(set (match_operand:TQF 0 "general_operand" "=r")
130 (match_operand:TQF 1 "push_operand" ">"))]
131 ""
132 "*
133 {
134 rtx new_operands[2];
135 new_operands[0] = operands[0];
136 new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+2);
137 output_asm_insn(\"POPM R%0,R%1\",new_operands);
138 return \"\;\";
139 } ")
140
141 ;; Test operations. These shouldn't really occur for 1750:
142 ;; all important instructions set the cc's (see NOTICE_UPDATE_CC)
143
144 (define_insn "tstqi"
145 [(set (cc0)
146 (match_operand:QI 0 "register_operand" "r"))]
147 ""
148 "LR R%0,R%0 ; from tstqi")
149
150 (define_insn "tsthi"
151 [(set (cc0)
152 (match_operand:HI 0 "register_operand" "r"))]
153 ""
154 "DLR R%0,R%0 ; from tsthi")
155
156 (define_insn "tsthf"
157 [(set (cc0)
158 (match_operand:HF 0 "register_operand" "r"))]
159 ""
160 "DLR R%0,R%0 ; from tsthf")
161
162 ;; This one is happy with "roughly zero" :-) (should be improved)
163 (define_insn "tsttqf"
164 [(set (cc0)
165 (match_operand:TQF 0 "register_operand" "r"))]
166 ""
167 "DLR R%0,R%0 ; from tsttqf")
168
169
170 ;; block move.
171
172 ; there is a problem with this insn in gcc-2.2.3
173 ; (clobber (match_dup 2)) does not prevent use of this operand later
174 ;
175 (define_insn "movstrqi"
176 [(set (mem:BLK (match_operand:QI 0 "register_operand" "r"))
177 (mem:BLK (match_operand:QI 1 "register_operand" "r")))
178 (use (match_operand:QI 2 "register_operand" "r"))
179 (use (match_operand:QI 3 "immediate_operand" ""))
180 (clobber (match_dup 0))
181 (clobber (match_dup 1))
182 (clobber (match_dup 2))]
183 ""
184 "* return (char *)movcnt_regno_adjust(operands); ")
185
186
187 ;; compare instructions.
188
189 (define_insn "cmpqi"
190 [(set (cc0)
191 (compare (match_operand:QI 0 "register_operand" "r,r,r,r,r")
192 (match_operand:QI 1 "general_operand" "I,J,i,r,m")))]
193 ""
194 "@
195 CISP R%0,%1
196 CISN R%0,%J1
197 CIM R%0,%1
198 CR R%0,R%1
199 C R%0,%1 ")
200
201 (define_insn "cmphi"
202 [(set (cc0)
203 (compare (match_operand:HI 0 "general_operand" "r,r")
204 (match_operand:HI 1 "general_operand" "r,m")))]
205 ""
206 "@
207 DCR R%0,R%1
208 DC R%0,%1 ")
209
210 (define_insn "cmphf"
211 [(set (cc0)
212 (compare (match_operand:HF 0 "general_operand" "r,r")
213 (match_operand:HF 1 "general_operand" "r,m")))]
214 ""
215 "@
216 FCR R%0,R%1
217 FC R%0,%1 ")
218
219 (define_insn "cmptqf"
220 [(set (cc0)
221 (compare (match_operand:TQF 0 "general_operand" "r,r")
222 (match_operand:TQF 1 "general_operand" "r,m")))]
223 ""
224 "@
225 EFCR R%0,R%1
226 EFC R%0,%1 ")
227
228
229 ;; truncation instructions
230 ;;- 1750: any needed?
231
232 (define_insn "trunchiqi2"
233 [(set (match_operand:QI 0 "register_operand" "=r")
234 (truncate:QI
235 (match_operand:HI 1 "register_operand" "r")))]
236 ""
237 "*
238 {
239 REGNO(operands[1]) += 1;
240 return \"LR R%0,R%1 ;trunchiqi2\";
241 } ")
242
243 ;; zero extension instructions
244
245 (define_insn "zero_extendqihi2"
246 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
247 (zero_extend:HI (match_operand:QI 1 "general_operand" "r,m,i")))]
248 ""
249 "*
250 {
251 output_asm_insn(\"XORR R%0,R%0 ;zero_extendqihi2\",operands);
252 REGNO(operands[0]) += 1;
253 switch (which_alternative)
254 {
255 case 0:
256 return \"LR R%0,R%1\";
257 case 1:
258 return \"L R%0,%1\";
259 case 2:
260 return \"LIM R%0,%1\";
261 }
262 } ")
263
264 ;; sign extension instructions
265
266 (define_insn "extendqihi2"
267 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
268 (sign_extend:HI (match_operand:QI 1 "general_operand" "r,m,i")) )]
269 ""
270 "@
271 LR R%0,R%1 ;extendqihi2\;DSRA R%0,16
272 L R%0,%1 ;extendqihi2\;DSRA R%0,16
273 LIM R%0,%1 ;extendqihi2\;DSRA R%0,16 ")
274
275
276 ;; Conversions between float and double.
277
278 ; 1750 HF-to-TQF extend: just append 16 bits (least signif.) with all bits zero
279 (define_insn "extendhftqf2"
280 [(set (match_operand:TQF 0 "register_operand" "=r,r")
281 (float_extend:TQF
282 (match_operand:HF 1 "general_operand" "r,m")))]
283 ""
284 "*
285 {
286 REGNO(operands[0]) += 2;
287 output_asm_insn(\"XORR R%0,R%0 ;extendhftqf2\",operands);
288 REGNO(operands[0]) -= 2;
289 if (which_alternative == 0)
290 return \"DLR R%0,R%1\";
291 else
292 return \"DL R%0,%1\";
293 } ")
294
295 ; 1750 TQF-to-HF truncate is a no-op: just leave away the least signif. 16 bits
296 (define_insn "trunctqfhf2"
297 [(set (match_operand:HF 0 "register_operand" "=r,r")
298 (float_truncate:HF
299 (match_operand:TQF 1 "general_operand" "r,m")))]
300 ""
301 "@
302 DLR R%0,R%1 ;trunctqfhf2
303 DL R%0,%1 ;trunctqfhf2 ")
304
305
306 ;; Conversion between fixed point and floating point.
307
308 (define_insn "floatqihf2"
309 [(set (match_operand:HF 0 "register_operand" "=r")
310 (float:HF (match_operand:QI 1 "register_operand" "r")))]
311 ""
312 "FLT R%0,R%1")
313
314 (define_insn "floathitqf2"
315 [(set (match_operand:TQF 0 "register_operand" "=r")
316 (float:TQF (match_operand:HI 1 "register_operand" "r")))]
317 ""
318 "EFLT R%0,R%1")
319
320
321 ;; Convert floats to ints
322
323 (define_insn "fix_trunchfqi2"
324 [(set (match_operand:QI 0 "register_operand" "=r")
325 (fix:QI (fix:HF (match_operand:HF 1 "register_operand" "r"))))]
326 ""
327 "FIX R%0,R%1")
328
329 (define_insn "fix_trunctqfhi2"
330 [(set (match_operand:HI 0 "register_operand" "=r")
331 (fix:HI (fix:TQF (match_operand:TQF 1 "register_operand" "r"))))]
332 ""
333 "EFIX R%0,R%1")
334
335
336 ;; Move instructions
337
338 ;; We can't deal with normal byte-size characters, only with WIDE characters!
339 ;; This may appear as a serious restriction, but it also opens the doors
340 ;; for ISO 10646 :-)
341
342 ;; 16-bit moves
343
344 (define_insn "movqi"
345 [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,r,m,m")
346 (match_operand:QI 1 "general_operand" "O,I,J,M,i,r,m,r,K"))]
347 ""
348 "@
349 XORR R%0,R%0
350 LISP R%0,%1
351 LISN R%0,%J1
352 LIM R%0,%1 ; 'M' constraint
353 LIM R%0,%1 ; 'i' constraint
354 LR R%0,R%1
355 L R%0,%1
356 ST R%1,%0
357 STC %1,%0 ")
358
359 ;; 32-bit moves
360
361 ;; Set HIreg to constant
362 (define_insn ""
363 [(set (match_operand:HI 0 "register_operand" "=r")
364 (match_operand 1 "immediate_operand" "i"))]
365 ""
366 "*
367 if (GET_CODE(operands[1]) == CONST_INT)
368 {
369 int val = INTVAL(operands[1]);
370 if (val >= 0)
371 {
372 if (val <= 65535)
373 {
374 output_asm_insn(\"XORR R%0,R%0 ;movhi cst->reg\",operands);
375 operands[0] = gen_rtx(REG,QImode,REGNO(operands[0]) + 1);
376 if (val == 0)
377 return \"XORR R%0,R%0\";
378 else if (val <= 16)
379 return \"LISP R%0,%1\";
380 else
381 return \"LIM R%0,%1\";
382 }
383 }
384 else if (val >= -16)
385 return \"LISN R%0,%J1\;DSRA R%0,16 ;movhi cst\";
386 INTVAL(operands[1]) >>= 16;
387 output_asm_insn(\"LIM R%0,%1 ;movhi cst->reg\",operands);
388 REGNO(operands[0]) += 1;
389 INTVAL(operands[1]) = val & 0xFFFF;
390 return \"LIM R%0,%1\";
391 }
392 return \"LIM R%0,%1\;DSRA R%0,16 ;movhi cst\";
393 ")
394
395 (define_insn "movhi"
396 [(set (match_operand:HI 0 "general_operand" "=r,r,m")
397 (match_operand:HI 1 "general_operand" "r,m,r"))]
398 ""
399 "@
400 DLR R%0,R%1
401 DL R%0,%1
402 DST R%1,%0 ")
403
404
405 ;; Single-Float moves are *same* as HImode moves:
406
407 (define_insn "movhf"
408 [(set (match_operand:HF 0 "general_operand" "=r,r,r,r,m")
409 (match_operand:HF 1 "general_operand" "G,F,r,m,r"))]
410 ""
411 "@
412 DXRR.M %0,%0 ; movhf const(0.0)
413 %E1\;DL R%0,%F1
414 DLR R%0,R%1
415 DL R%0,%1
416 DST R%1,%0 ")
417
418
419 ;; Longfloat moves
420
421 (define_insn "movtqf"
422 [(set (match_operand:TQF 0 "general_operand" "=r,r,r,m")
423 (match_operand:TQF 1 "general_operand" "F,r,m,r"))]
424 ""
425 "@
426 %D1\;EFL R%0,%F1
427 EFLR.M %0,%1
428 EFL R%0,%1
429 EFST R%1,%0 ")
430
431
432 ;; add instructions
433
434 ;; single integer
435
436 ;; Use "LIM Ra,sym,Rb" for adding a symbol value to a register and
437 ;; transferring the result to a different register.
438 ;(define_insn ""
439 ; [(set (match_operand:QI 0 "register_operand" "=r")
440 ; (plus:QI (match_operand:QI 1 "register_operand" "b")
441 ; (match_operand:QI 2 "immediate_operand" "i")))]
442 ; "REGNO(operands[0]) != REGNO(operands[1])"
443 ; "LIM R%0,%2,R%1 ;md special addqi")
444
445 (define_insn "addqi3"
446 [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,m,m")
447 (plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0,0")
448 (match_operand:QI 2 "general_operand" "I,J,i,r,m,I,J")))]
449 ""
450 "*
451 switch (which_alternative)
452 {
453 case 0:
454 return \"AISP R%0,%2\";
455 case 1:
456 return \"SISP R%0,%J2\";
457 case 2:
458 if (INTVAL(operands[2]) < 0)
459 return \"SIM R%0,%J2\";
460 else
461 return \"AIM R%0,%2\";
462 case 3:
463 return \"AR R%0,R%2\";
464 case 4:
465 return \"A R%0,%2\";
466 case 5:
467 return \"INCM %2,%0\";
468 case 6:
469 return \"DECM %J2,%0\";
470 } ")
471
472 ;; double integer
473 (define_insn "addhi3"
474 [(set (match_operand:HI 0 "register_operand" "=r,r")
475 (plus:HI (match_operand:HI 1 "register_operand" "%0,0")
476 (match_operand:HI 2 "general_operand" "r,m")))]
477 ""
478 "@
479 DAR R%0,R%2
480 DA R%0,%2 ")
481
482 (define_insn "addhf3"
483 [(set (match_operand:HF 0 "register_operand" "=r,r")
484 (plus:HF (match_operand:HF 1 "register_operand" "%0,0")
485 (match_operand:HF 2 "general_operand" "m,r")))]
486 ""
487 "@
488 FA R%0,%2
489 FAR R%0,R%2 ")
490
491 (define_insn "addtqf3"
492 [(set (match_operand:TQF 0 "register_operand" "=r,r")
493 (plus:TQF (match_operand:TQF 1 "register_operand" "%0,0")
494 (match_operand:TQF 2 "general_operand" "m,r")))]
495 ""
496 "@
497 EFA R%0,%2
498 EFAR R%0,R%2 ")
499
500
501 ;; subtract instructions
502
503 ;; single integer
504 (define_insn "subqi3"
505 [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,m")
506 (minus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0")
507 (match_operand:QI 2 "general_operand" "I,i,r,m,I")))]
508 ""
509 "@
510 SISP R%0,%2
511 SIM R%0,%2
512 SR R%0,R%2
513 S R%0,%2
514 DECM %2,%0 ")
515
516 ;; double integer
517 (define_insn "subhi3"
518 [(set (match_operand:HI 0 "register_operand" "=r,r")
519 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
520 (match_operand:HI 2 "general_operand" "r,m")))]
521 ""
522 "@
523 DSR R%0,R%2
524 DS R%0,%2 ")
525
526 (define_insn "subhf3"
527 [(set (match_operand:HF 0 "register_operand" "=r,r")
528 (minus:HF (match_operand:HF 1 "register_operand" "0,0")
529 (match_operand:HF 2 "general_operand" "r,m")))]
530 ""
531 "@
532 FSR R%0,R%2
533 FS R%0,%2 ")
534
535 (define_insn "subtqf3"
536 [(set (match_operand:TQF 0 "register_operand" "=r,r")
537 (minus:TQF (match_operand:TQF 1 "register_operand" "0,0")
538 (match_operand:TQF 2 "general_operand" "r,m")))]
539 ""
540 "@
541 EFSR R%0,R%2
542 EFS R%0,%2 ")
543
544
545 ;; multiply instructions
546
547 (define_insn "mulqi3"
548 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
549 (mult:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
550 (match_operand:QI 2 "general_operand" "I,J,M,r,m")))]
551 ""
552 "@
553 MISP R%0,%2
554 MISN R%0,%J2
555 MSIM R%0,%2
556 MSR R%0,R%2
557 MS R%0,%2 ")
558
559
560 ; 32-bit product
561 (define_insn "mulqihi3"
562 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
563 (mult:HI (match_operand:QI 1 "register_operand" "%0,0,0")
564 (match_operand:QI 2 "general_operand" "M,r,m")))]
565 ""
566 "@
567 MIM R%0,%1
568 MR R%0,R%2
569 M R%0,%2 ")
570
571 (define_insn "mulhi3"
572 [(set (match_operand:HI 0 "register_operand" "=r,r")
573 (mult:HI (match_operand:HI 1 "register_operand" "%0,0")
574 (match_operand:HI 2 "general_operand" "r,m")))]
575 ""
576 "@
577 DMR R%0,R%2
578 DM R%0,%2 ")
579
580 ; not available on 1750: "umulhi3","umulhisi3","umulsi3" (unsigned multiply's)
581
582 (define_insn "mulhf3"
583 [(set (match_operand:HF 0 "register_operand" "=r,r")
584 (mult:HF (match_operand:HF 1 "register_operand" "%0,0")
585 (match_operand:HF 2 "general_operand" "r,m")))]
586 ""
587 "@
588 FMR R%0,R%2
589 FM R%0,%2 ")
590
591 (define_insn "multqf3"
592 [(set (match_operand:TQF 0 "register_operand" "=r,r")
593 (mult:TQF (match_operand:TQF 1 "register_operand" "%0,0")
594 (match_operand:TQF 2 "general_operand" "r,m")))]
595 ""
596 "@
597 EFMR R%0,R%2
598 EFM R%0,%2 ")
599
600
601 ;; divide instructions
602 ;; The 1750 16bit integer division instructions deliver a 16-bit
603 ;; quotient and a 16-bit remainder, where the remainder is in the next higher
604 ;; register number above the quotient. For now, we haven't found a way
605 ;; to give the reload pass knowledge of this property. So we make do with
606 ;; whatever registers the allocator wants, and willy-nilly output a pair of
607 ;; register-copy ops when needed. (See mod_regno_adjust() in file aux-output.c)
608 ;; A comment in the description of `divmodM4' suggests that one leave the divM3
609 ;; undefined when there is a divmodM4 available.
610
611 (define_insn "divmodqi4"
612 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
613 (div:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0")
614 (match_operand:QI 2 "general_operand" "I,J,M,r,m")))
615 (set (match_operand:QI 3 "register_operand" "=r,r,r,r,r")
616 (mod:QI (match_dup 1) (match_dup 2)))]
617 ""
618 "*
619 {
620 char *istr;
621 switch(which_alternative)
622 {
623 case 0:
624 istr = \"DISP\";
625 break;
626 case 1:
627 INTVAL(operands[2]) = - INTVAL(operands[2]); /* to be corrected */
628 istr = \"DISN\";
629 break;
630 case 2:
631 istr = \"DVIM\";
632 break;
633 case 3:
634 istr = \"DVR \";
635 break;
636 case 4:
637 istr = \"DV \";
638 break;
639 }
640 return (char *)mod_regno_adjust(istr,operands);
641 }")
642
643 ;; Division for other types is straightforward.
644
645 (define_insn "divhi3"
646 [(set (match_operand:HI 0 "register_operand" "=r,r")
647 (div:HI (match_operand:HI 1 "register_operand" "0,0")
648 (match_operand:HI 2 "general_operand" "r,m")))]
649 ""
650 "@
651 DDR R%0,R%2
652 DD R%0,%2 ")
653
654 (define_insn "divhf3"
655 [(set (match_operand:HF 0 "register_operand" "=r,r")
656 (div:HF (match_operand:HF 1 "register_operand" "0,0")
657 (match_operand:HF 2 "general_operand" "r,m")))]
658 ""
659 "@
660 FDR R%0,R%2
661 FD R%0,%2 ")
662
663 (define_insn "divtqf3"
664 [(set (match_operand:TQF 0 "register_operand" "=r,r")
665 (div:TQF (match_operand:TQF 1 "register_operand" "0,0")
666 (match_operand:TQF 2 "general_operand" "r,m")))]
667 ""
668 "@
669 EFDR R%0,R%2
670 EFD R%0,%2 ")
671
672
673 ;; Other arithmetic instructions:
674
675 ;; Absolute value
676
677 (define_insn "absqi2"
678 [(set (match_operand:QI 0 "register_operand" "=r")
679 (abs:QI (match_operand:QI 1 "register_operand" "r")))]
680 ""
681 "ABS R%0,R%1")
682
683 (define_insn "abshi2"
684 [(set (match_operand:HI 0 "register_operand" "=r")
685 (abs:HI (match_operand:HI 1 "register_operand" "r")))]
686 ""
687 "DABS R%0,R%1")
688
689 (define_insn "abshf2"
690 [(set (match_operand:HF 0 "register_operand" "=r")
691 (abs:HF (match_operand:HF 1 "register_operand" "r")))]
692 ""
693 "FABS R%0,R%1")
694
695
696 ;; Negation
697
698 (define_insn "negqi2"
699 [(set (match_operand:QI 0 "register_operand" "=r")
700 (neg:QI (match_operand:QI 1 "register_operand" "r")))]
701 ""
702 "NEG R%0,R%1")
703
704 (define_insn "neghi2"
705 [(set (match_operand:HI 0 "register_operand" "=r")
706 (neg:HI (match_operand:HI 1 "register_operand" "r")))]
707 ""
708 "DNEG R%0,R%1")
709
710 (define_insn "neghf2"
711 [(set (match_operand:HF 0 "register_operand" "=r")
712 (neg:HF (match_operand:HF 1 "register_operand" "r")))]
713 ""
714 "FNEG R%0,R%1")
715
716 ; The 1750A does not have an extended float negate instruction, so simulate.
717 ;(define_expand "negtqf2"
718 ; [(set (match_operand:TQF 0 "register_operand" "=&r")
719 ; (neg:TQF (match_operand:TQF 1 "register_operand" "r")))]
720 ; ""
721 ; "
722 ; emit_insn(gen_rtx(SET,VOIDmode,operands[0],CONST0_RTX(TQFmode)));
723 ; emit_insn(gen_rtx(SET,VOIDmode,operands[0],
724 ; gen_rtx(MINUS,TQFmode,operands[0],operands[1])));
725 ; DONE;
726 ; ")
727
728
729 ;; bit-logical instructions
730
731 ;; AND
732
733 (define_insn "andqi3"
734 [(set (match_operand:QI 0 "general_operand" "=r,r,r")
735 (and:QI (match_operand:QI 1 "general_operand" "%0,0,0")
736 (match_operand:QI 2 "general_operand" "M,r,m")))]
737 ""
738 "@
739 ANDM R%0,%2
740 ANDR R%0,R%2
741 AND R%0,%2 ")
742
743 ; This sets incorrect condition codes. See notice_update_cc()
744 (define_insn "andhi3"
745 [(set (match_operand:HI 0 "register_operand" "=r")
746 (and:HI (match_operand:HI 1 "register_operand" "%0")
747 (match_operand:HI 2 "register_operand" "r")))]
748 ""
749 "DANR.M %0,%2")
750
751 ;; OR
752
753 (define_insn "iorqi3"
754 [(set (match_operand:QI 0 "general_operand" "=r,r,r")
755 (ior:QI (match_operand:QI 1 "general_operand" "%0,0,0")
756 (match_operand:QI 2 "general_operand" "M,r,m")))]
757 ""
758 "@
759 ORIM R%0,%2
760 ORR R%0,R%2
761 OR R%0,%2 ")
762
763 ; This sets incorrect condition codes. See notice_update_cc()
764 (define_insn "iorhi3"
765 [(set (match_operand:HI 0 "register_operand" "=r")
766 (ior:HI (match_operand:HI 1 "register_operand" "%0")
767 (match_operand:HI 2 "register_operand" "r")))]
768 ""
769 "DORR.M %0,%2")
770
771 ;; XOR
772
773 (define_insn "xorqi3"
774 [(set (match_operand:QI 0 "register_operand" "=r,r,r")
775 (xor:QI (match_operand:QI 1 "register_operand" "%0,0,0")
776 (match_operand:QI 2 "general_operand" "M,r,m")))]
777 ""
778 "@
779 XORM R%0,%2
780 XORR R%0,R%2
781 XOR R%0,%2 ")
782
783 ; This sets incorrect condition codes. See notice_update_cc()
784 (define_insn "xorhi3"
785 [(set (match_operand:HI 0 "register_operand" "=r")
786 (xor:HI (match_operand:HI 1 "register_operand" "%0")
787 (match_operand:HI 2 "register_operand" "r")))]
788 ""
789 "DXRR.M %0,%2")
790
791 ;; NAND
792
793 (define_insn ""
794 [(set (match_operand:QI 0 "register_operand" "=r,r,r")
795 (ior:QI (not:QI (match_operand:QI 1 "register_operand" "%0,0,0"))
796 (not:QI (match_operand:QI 2 "general_operand" "M,r,m"))))]
797 ""
798 "@
799 NIM R%0,%2
800 NR R%0,R%2
801 N R%0,%2 ")
802
803 ; This sets incorrect condition codes. See notice_update_cc()
804 (define_insn ""
805 [(set (match_operand:HI 0 "register_operand" "=r")
806 (ior:HI (not:HI (match_operand:HI 1 "register_operand" "%0"))
807 (not:HI (match_operand:HI 2 "register_operand" "r"))))]
808 ""
809 "DNR.M %0,%2")
810
811 ;; NOT
812
813 (define_insn "one_cmplqi2"
814 [(set (match_operand:QI 0 "register_operand" "=r")
815 (not:QI (match_operand:QI 1 "register_operand" "0")))]
816 ""
817 "NR R%0,R%0")
818
819 ; This sets incorrect condition codes. See notice_update_cc()
820 (define_insn "one_cmplhi2"
821 [(set (match_operand:HI 0 "register_operand" "=r")
822 (not:HI (match_operand:HI 1 "register_operand" "0")))]
823 ""
824 "DNR.M %0,%0")
825
826
827 ;; Shift instructions
828
829 ; (What to the 1750 is logical-shift-left, GCC likes to call "arithmetic")
830 (define_insn "ashlqi3"
831 [(set (match_operand:QI 0 "register_operand" "=r,r,r")
832 (ashift:QI (match_operand:QI 1 "register_operand" "0,0,0")
833 (match_operand:QI 2 "general_operand" "O,I,r")))]
834 ""
835 "@
836 ; optimized away an SLL R%0,0
837 SLL R%0,%2
838 SLR R%0,R%2 ")
839
840 (define_insn "ashlhi3"
841 [(set (match_operand:HI 0 "register_operand" "=r,r")
842 (ashift:HI (match_operand:HI 1 "register_operand" "0,0")
843 (match_operand:QI 2 "general_operand" "L,r")))]
844 "" ; the 'L' constraint is a slight imprecise...
845 "@
846 DSLL R%0,%2
847 DSLR R%0,R%2 ")
848
849 (define_insn "lshrqi3"
850 [(set (match_operand:QI 0 "register_operand" "=r,r")
851 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0")
852 (match_operand:QI 2 "general_operand" "I,r")))]
853 ""
854 "@
855 SRL R%0,%2
856 NEG R%2,R%2\;SLR R%0,R%2 ")
857
858 (define_insn "lshrhi3"
859 [(set (match_operand:HI 0 "register_operand" "=r,r")
860 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0")
861 (match_operand:QI 2 "general_operand" "L,r")))]
862 "" ; the 'L' constraint is a slight imprecise...
863 "@
864 DSRL R%0,%2
865 NEG R%2,R%2\;DSLR R%0,R%2 ")
866
867 (define_insn "ashrqi3"
868 [(set (match_operand:QI 0 "register_operand" "=r,r")
869 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0")
870 (match_operand:QI 2 "general_operand" "I,r")))]
871 ""
872 "@
873 SRA R%0,%2
874 NEG R%2,R%2\;SAR R%0,R%2 ")
875
876 (define_insn "ashrhi3"
877 [(set (match_operand:HI 0 "register_operand" "=r,r")
878 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0")
879 (match_operand:QI 2 "general_operand" "I,r")))]
880 ""
881 "@
882 DSRA R%0,%2
883 NEG R%2,R%2\;DSAR R%0,R%2 ")
884
885
886 ;; rotate instructions
887
888 (define_insn "rotlqi3"
889 [(set (match_operand:QI 0 "register_operand" "=r,r")
890 (rotate:QI (match_operand:QI 1 "register_operand" "0,0")
891 (match_operand:QI 2 "general_operand" "I,r")))]
892 ""
893 "@
894 SLC R%0,%2
895 SCR R%0,R%2 ")
896
897 (define_insn "rotlhi3"
898 [(set (match_operand:HI 0 "register_operand" "=r,r")
899 (rotate:HI (match_operand:HI 1 "register_operand" "0,0")
900 (match_operand:QI 2 "general_operand" "I,r")))]
901 ""
902 "@
903 DSLC R%0,%2
904 DSCR R%0,R%2 ")
905
906 (define_insn "rotrqi3"
907 [(set (match_operand:QI 0 "register_operand" "=r,r")
908 (rotatert:QI (match_operand:QI 1 "register_operand" "0,0")
909 (match_operand:QI 2 "general_operand" "I,r")))]
910 ""
911 "@
912 SLC R%0,%2
913 NEG R%2,R%2\;SCR R%0,R%2 ")
914
915 (define_insn "rotrhi3"
916 [(set (match_operand:HI 0 "register_operand" "=r,r")
917 (rotatert:HI (match_operand:HI 1 "register_operand" "0,0")
918 (match_operand:QI 2 "general_operand" "I,r")))]
919 ""
920 "@
921 DSLC R%0,%2
922 NEG R%2,R%2\;DSCR R%0,R%2 ")
923
924
925
926 ;; Special cases of bit-field insns which we should
927 ;; recognize in preference to the general case.
928 ;; These handle aligned 8-bit and 16-bit fields,
929 ;; which can usually be done with move instructions.
930 ; 1750: t.b.d.
931 ;********************
932
933 ;; Bit field instructions, general cases.
934 ;; "o,d" constraint causes a nonoffsetable memref to match the "o"
935 ;; so that its address is reloaded.
936
937 ;; (define_insn "extv" ...
938
939 ;; (define_insn "extzv" ...
940
941 ;; (define_insn "insv" ...
942
943 ;; Now recognize bit field insns that operate on registers
944 ;; (or at least were intended to do so).
945 ;[unnamed only]
946
947 ;; Special patterns for optimizing bit-field instructions.
948 ;**************************************
949
950 ; cc status test ops n.a. on 1750 ......... e.g. "sleu" on 68k:
951 ; [(set (match_operand:QI 0 "general_operand" "=d")
952 ; (leu (cc0) (const_int 0)))]
953 ; ""
954 ; "* cc_status = cc_prev_status;
955 ; return \"sls %0\"; ")
956
957
958 ;; Basic conditional jump instructions.
959
960 (define_insn "beq"
961 [(set (pc)
962 (if_then_else (eq (cc0)
963 (const_int 0))
964 (label_ref (match_operand 0 "" ""))
965 (pc)))]
966 ""
967 "* return (char *)branch_or_jump(\"EZ\",CODE_LABEL_NUMBER(operands[0]));
968 ")
969
970 (define_insn "bne"
971 [(set (pc)
972 (if_then_else (ne (cc0)
973 (const_int 0))
974 (label_ref (match_operand 0 "" ""))
975 (pc)))]
976 ""
977 "* return (char *)branch_or_jump(\"NZ\",CODE_LABEL_NUMBER(operands[0]));
978 ")
979
980 (define_insn "bgt"
981 [(set (pc)
982 (if_then_else (gt (cc0)
983 (const_int 0))
984 (label_ref (match_operand 0 "" ""))
985 (pc)))]
986 ""
987 "* return (char *)branch_or_jump(\"GT\",CODE_LABEL_NUMBER(operands[0]));
988 ")
989
990 (define_insn "blt"
991 [(set (pc)
992 (if_then_else (lt (cc0)
993 (const_int 0))
994 (label_ref (match_operand 0 "" ""))
995 (pc)))]
996 ""
997 "* return (char *)branch_or_jump(\"LT\",CODE_LABEL_NUMBER(operands[0]));
998 ")
999
1000 (define_insn "bge"
1001 [(set (pc)
1002 (if_then_else (ge (cc0)
1003 (const_int 0))
1004 (label_ref (match_operand 0 "" ""))
1005 (pc)))]
1006 ""
1007 "* return (char *)branch_or_jump(\"GE\",CODE_LABEL_NUMBER(operands[0]));
1008 ")
1009
1010 (define_insn "ble"
1011 [(set (pc)
1012 (if_then_else (le (cc0)
1013 (const_int 0))
1014 (label_ref (match_operand 0 "" ""))
1015 (pc)))]
1016 ""
1017 "* return (char *)branch_or_jump(\"LE\",CODE_LABEL_NUMBER(operands[0]));
1018 ")
1019
1020
1021 ; no unsigned branches available on 1750. But GCC still needs them, so faking:
1022
1023 (define_insn "bgtu"
1024 [(set (pc)
1025 (if_then_else (gtu (cc0)
1026 (const_int 0))
1027 (label_ref (match_operand 0 "" ""))
1028 (pc)))]
1029 ""
1030 "JC GT,%l0 ; Warning: this should be an *unsigned* test!")
1031
1032 (define_insn "bltu"
1033 [(set (pc)
1034 (if_then_else (ltu (cc0)
1035 (const_int 0))
1036 (label_ref (match_operand 0 "" ""))
1037 (pc)))]
1038 ""
1039 "JC LT,%l0 ; Warning: this should be an *unsigned* test!")
1040
1041 (define_insn "bgeu"
1042 [(set (pc)
1043 (if_then_else (geu (cc0)
1044 (const_int 0))
1045 (label_ref (match_operand 0 "" ""))
1046 (pc)))]
1047 ""
1048 "JC GE,%l0 ; Warning: this should be an *unsigned* test!")
1049
1050 (define_insn "bleu"
1051 [(set (pc)
1052 (if_then_else (leu (cc0)
1053 (const_int 0))
1054 (label_ref (match_operand 0 "" ""))
1055 (pc)))]
1056 ""
1057 "JC LE,%l0 ; Warning: this should be an *unsigned* test!")
1058
1059
1060 ;; Negated conditional jump instructions.
1061
1062 (define_insn ""
1063 [(set (pc)
1064 (if_then_else (eq (cc0)
1065 (const_int 0))
1066 (pc)
1067 (label_ref (match_operand 0 "" ""))))]
1068 ""
1069 "* return (char *)branch_or_jump(\"NZ\",CODE_LABEL_NUMBER(operands[0]));
1070 ")
1071
1072 (define_insn ""
1073 [(set (pc)
1074 (if_then_else (ne (cc0)
1075 (const_int 0))
1076 (pc)
1077 (label_ref (match_operand 0 "" ""))))]
1078 ""
1079 "* return (char *)branch_or_jump(\"EZ\",CODE_LABEL_NUMBER(operands[0]));
1080 ")
1081
1082 (define_insn ""
1083 [(set (pc)
1084 (if_then_else (gt (cc0)
1085 (const_int 0))
1086 (pc)
1087 (label_ref (match_operand 0 "" ""))))]
1088 ""
1089 "* return (char *)branch_or_jump(\"LE\",CODE_LABEL_NUMBER(operands[0]));
1090 ")
1091
1092 (define_insn ""
1093 [(set (pc)
1094 (if_then_else (lt (cc0)
1095 (const_int 0))
1096 (pc)
1097 (label_ref (match_operand 0 "" ""))))]
1098 ""
1099 "* return (char *)branch_or_jump(\"GE\",CODE_LABEL_NUMBER(operands[0]));
1100 ")
1101
1102 (define_insn ""
1103 [(set (pc)
1104 (if_then_else (ge (cc0)
1105 (const_int 0))
1106 (pc)
1107 (label_ref (match_operand 0 "" ""))))]
1108 ""
1109 "* return (char *)branch_or_jump(\"LT\",CODE_LABEL_NUMBER(operands[0]));
1110 ")
1111
1112 (define_insn ""
1113 [(set (pc)
1114 (if_then_else (le (cc0)
1115 (const_int 0))
1116 (pc)
1117 (label_ref (match_operand 0 "" ""))))]
1118 ""
1119 "* return (char *)branch_or_jump(\"GT\",CODE_LABEL_NUMBER(operands[0]));
1120 ")
1121
1122
1123 ;; Negated unsigned conditional jump instructions (faked for 1750).
1124
1125 (define_insn ""
1126 [(set (pc)
1127 (if_then_else (gtu (cc0)
1128 (const_int 0))
1129 (pc)
1130 (label_ref (match_operand 0 "" ""))))]
1131 ""
1132 "JC LE,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
1133
1134 (define_insn ""
1135 [(set (pc)
1136 (if_then_else (ltu (cc0)
1137 (const_int 0))
1138 (pc)
1139 (label_ref (match_operand 0 "" ""))))]
1140 ""
1141 "JC GE,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
1142
1143 (define_insn ""
1144 [(set (pc)
1145 (if_then_else (geu (cc0)
1146 (const_int 0))
1147 (pc)
1148 (label_ref (match_operand 0 "" ""))))]
1149 ""
1150 "JC LT,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
1151
1152 (define_insn ""
1153 [(set (pc)
1154 (if_then_else (leu (cc0)
1155 (const_int 0))
1156 (pc)
1157 (label_ref (match_operand 0 "" ""))))]
1158 ""
1159 "JC GT,%l0 ;inv.cond. ;Warning: this should be an *unsigned* test!")
1160
1161 ;; Tablejump
1162 ;; 1750 note: CASE_VECTOR_PC_RELATIVE is not defined
1163 (define_insn "tablejump"
1164 [(set (pc)
1165 (match_operand:QI 0 "register_operand" "b"))
1166 (use (label_ref (match_operand 1 "" "")))]
1167 ""
1168 "JC 15,0,R%0 ; tablejump label_ref=%1")
1169
1170
1171 ;; Unconditional jump
1172 (define_insn "jump"
1173 [(set (pc)
1174 (label_ref (match_operand 0 "" "")))]
1175 ""
1176 "JC UC,%0")
1177
1178 ;; Call subroutine, returning value in operand 0
1179 ;; (which must be a hard register).
1180 (define_insn "call_value"
1181 [(set (match_operand 0 "register_operand" "r")
1182 (call (match_operand:QI 1 "memory_operand" "m")
1183 (match_operand:QI 2 "general_operand" "g")))]
1184 ;; Operand 2 not really used for 1750.
1185 ""
1186 "SJS R15,%1 ; return value in R0")
1187
1188 ;; Call subroutine with no return value.
1189
1190 ;; Operand 1 not really used in MIL-STD-1750.
1191 (define_insn ""
1192 [(call (match_operand:QI 0 "memory_operand" "mp")
1193 (match_operand:QI 1 "general_operand" ""))]
1194 ""
1195 "SJS R15,%0 ; no return value")
1196
1197 ;;;;;;;;;;;; 1750: NOT READY YET.
1198 (define_insn "call"
1199 [(call (match_operand:QI 0 "" "")
1200 (match_operand:QI 1 "" ""))]
1201 ""
1202 "ANYCALL %0")
1203
1204
1205 ; (define_insn "return"
1206 ; [(return)]
1207 ; ""
1208 ; "*
1209 ; {
1210 ; rtx oprnd = gen_rtx(CONST_INT,VOIDmode,get_frame_size());
1211 ; output_asm_insn(\"RET.M %0\",&oprnd);
1212 ; return \"\;\";
1213 ; } ")
1214
1215 (define_insn "indirect_jump"
1216 [(set (pc) (match_operand:QI 0 "address_operand" "p"))]
1217 ""
1218 "JCI 15,%0")
1219
1220 (define_insn "nop"
1221 [(const_int 0)]
1222 ""
1223 "nop")
1224
1225
1226 ;; Subtract One and Jump (if non-zero)
1227 (define_peephole
1228 [(set (match_operand:QI 0 "register_operand" "=r")
1229 (plus:QI (match_operand:QI 1 "register_operand" "%0")
1230 (match_operand:QI 2 "immediate_operand" "J")))
1231 (set (cc0) (match_dup 0))
1232 (set (pc)
1233 (if_then_else (ne (cc0) (const_int 0))
1234 (label_ref (match_operand 3 "" ""))
1235 (pc)))
1236 ]
1237 "INTVAL(operands[2]) == -1"
1238 "SOJ R%0,%3")
1239
1240 ;;;End.
1241
GNU Compiler Collection
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