1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2024 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 We check (with modified_between_p) to avoid combining in such a way
37 as to move a computation to a place where its value would be different.
39 Combination is done by mathematically substituting the previous
40 insn(s) values for the regs they set into the expressions in
41 the later insns that refer to these regs. If the result is a valid insn
42 for our target machine, according to the machine description,
43 we install it, delete the earlier insns, and update the data flow
44 information (LOG_LINKS and REG_NOTES) for what we did.
46 There are a few exceptions where the dataflow information isn't
47 completely updated (however this is only a local issue since it is
48 regenerated before the next pass that uses it):
50 - reg_live_length is not updated
51 - reg_n_refs is not adjusted in the rare case when a register is
52 no longer required in a computation
53 - there are extremely rare cases (see distribute_notes) when a
55 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
56 removed because there is no way to know which register it was
59 To simplify substitution, we combine only when the earlier insn(s)
60 consist of only a single assignment. To simplify updating afterward,
61 we never combine when a subroutine call appears in the middle. */
65 #include "coretypes.h"
80 #include "stor-layout.h"
82 #include "cfgcleanup.h"
83 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
85 #include "insn-attr.h"
86 #include "rtlhooks-def.h"
88 #include "tree-pass.h"
91 #include "print-rtl.h"
92 #include "function-abi.h"
95 /* Number of attempts to combine instructions in this function. */
97 static int combine_attempts
;
99 /* Number of attempts that got as far as substitution in this function. */
101 static int combine_merges
;
103 /* Number of instructions combined with added SETs in this function. */
105 static int combine_extras
;
107 /* Number of instructions combined in this function. */
109 static int combine_successes
;
111 /* combine_instructions may try to replace the right hand side of the
112 second instruction with the value of an associated REG_EQUAL note
113 before throwing it at try_combine. That is problematic when there
114 is a REG_DEAD note for a register used in the old right hand side
115 and can cause distribute_notes to do wrong things. This is the
116 second instruction if it has been so modified, null otherwise. */
118 static rtx_insn
*i2mod
;
120 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
122 static rtx i2mod_old_rhs
;
124 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
126 static rtx i2mod_new_rhs
;
128 struct reg_stat_type
{
129 /* Record last point of death of (hard or pseudo) register n. */
130 rtx_insn
*last_death
;
132 /* Record last point of modification of (hard or pseudo) register n. */
135 /* The next group of fields allows the recording of the last value assigned
136 to (hard or pseudo) register n. We use this information to see if an
137 operation being processed is redundant given a prior operation performed
138 on the register. For example, an `and' with a constant is redundant if
139 all the zero bits are already known to be turned off.
141 We use an approach similar to that used by cse, but change it in the
144 (1) We do not want to reinitialize at each label.
145 (2) It is useful, but not critical, to know the actual value assigned
146 to a register. Often just its form is helpful.
148 Therefore, we maintain the following fields:
150 last_set_value the last value assigned
151 last_set_label records the value of label_tick when the
152 register was assigned
153 last_set_table_tick records the value of label_tick when a
154 value using the register is assigned
155 last_set_invalid set to true when it is not valid
156 to use the value of this register in some
159 To understand the usage of these tables, it is important to understand
160 the distinction between the value in last_set_value being valid and
161 the register being validly contained in some other expression in the
164 (The next two parameters are out of date).
166 reg_stat[i].last_set_value is valid if it is nonzero, and either
167 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
169 Register I may validly appear in any expression returned for the value
170 of another register if reg_n_sets[i] is 1. It may also appear in the
171 value for register J if reg_stat[j].last_set_invalid is zero, or
172 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
174 If an expression is found in the table containing a register which may
175 not validly appear in an expression, the register is replaced by
176 something that won't match, (clobber (const_int 0)). */
178 /* Record last value assigned to (hard or pseudo) register n. */
182 /* Record the value of label_tick when an expression involving register n
183 is placed in last_set_value. */
185 int last_set_table_tick
;
187 /* Record the value of label_tick when the value for register n is placed in
192 /* These fields are maintained in parallel with last_set_value and are
193 used to store the mode in which the register was last set, the bits
194 that were known to be zero when it was last set, and the number of
195 sign bits copies it was known to have when it was last set. */
197 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
198 char last_set_sign_bit_copies
;
199 ENUM_BITFIELD(machine_mode
) last_set_mode
: MACHINE_MODE_BITSIZE
;
201 /* Set to true if references to register n in expressions should not be
202 used. last_set_invalid is set nonzero when this register is being
203 assigned to and last_set_table_tick == label_tick. */
205 bool last_set_invalid
;
207 /* Some registers that are set more than once and used in more than one
208 basic block are nevertheless always set in similar ways. For example,
209 a QImode register may be loaded from memory in two places on a machine
210 where byte loads zero extend.
212 We record in the following fields if a register has some leading bits
213 that are always equal to the sign bit, and what we know about the
214 nonzero bits of a register, specifically which bits are known to be
217 If an entry is zero, it means that we don't know anything special. */
219 unsigned char sign_bit_copies
;
221 unsigned HOST_WIDE_INT nonzero_bits
;
223 /* Record the value of the label_tick when the last truncation
224 happened. The field truncated_to_mode is only valid if
225 truncation_label == label_tick. */
227 int truncation_label
;
229 /* Record the last truncation seen for this register. If truncation
230 is not a nop to this mode we might be able to save an explicit
231 truncation if we know that value already contains a truncated
234 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: MACHINE_MODE_BITSIZE
;
238 static vec
<reg_stat_type
> reg_stat
;
240 /* One plus the highest pseudo for which we track REG_N_SETS.
241 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
242 but during combine_split_insns new pseudos can be created. As we don't have
243 updated DF information in that case, it is hard to initialize the array
244 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
245 so instead of growing the arrays, just assume all newly created pseudos
246 during combine might be set multiple times. */
248 static unsigned int reg_n_sets_max
;
250 /* Record the luid of the last insn that invalidated memory
251 (anything that writes memory, and subroutine calls, but not pushes). */
253 static int mem_last_set
;
255 /* Record the luid of the last CALL_INSN
256 so we can tell whether a potential combination crosses any calls. */
258 static int last_call_luid
;
260 /* When `subst' is called, this is the insn that is being modified
261 (by combining in a previous insn). The PATTERN of this insn
262 is still the old pattern partially modified and it should not be
263 looked at, but this may be used to examine the successors of the insn
264 to judge whether a simplification is valid. */
266 static rtx_insn
*subst_insn
;
268 /* This is the lowest LUID that `subst' is currently dealing with.
269 get_last_value will not return a value if the register was set at or
270 after this LUID. If not for this mechanism, we could get confused if
271 I2 or I1 in try_combine were an insn that used the old value of a register
272 to obtain a new value. In that case, we might erroneously get the
273 new value of the register when we wanted the old one. */
275 static int subst_low_luid
;
277 /* This contains any hard registers that are used in newpat; reg_dead_at_p
278 must consider all these registers to be always live. */
280 static HARD_REG_SET newpat_used_regs
;
282 /* This is an insn to which a LOG_LINKS entry has been added. If this
283 insn is the earlier than I2 or I3, combine should rescan starting at
286 static rtx_insn
*added_links_insn
;
288 /* And similarly, for notes. */
290 static rtx_insn
*added_notes_insn
;
292 /* Basic block in which we are performing combines. */
293 static basic_block this_basic_block
;
294 static bool optimize_this_for_speed_p
;
297 /* Length of the currently allocated uid_insn_cost array. */
299 static int max_uid_known
;
301 /* The following array records the insn_cost for every insn
302 in the instruction stream. */
304 static int *uid_insn_cost
;
306 /* The following array records the LOG_LINKS for every insn in the
307 instruction stream as struct insn_link pointers. */
312 struct insn_link
*next
;
315 static struct insn_link
**uid_log_links
;
318 insn_uid_check (const_rtx insn
)
320 int uid
= INSN_UID (insn
);
321 gcc_checking_assert (uid
<= max_uid_known
);
325 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
326 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
328 #define FOR_EACH_LOG_LINK(L, INSN) \
329 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
331 /* Links for LOG_LINKS are allocated from this obstack. */
333 static struct obstack insn_link_obstack
;
335 /* Allocate a link. */
337 static inline struct insn_link
*
338 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
341 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
342 sizeof (struct insn_link
));
349 /* Incremented for each basic block. */
351 static int label_tick
;
353 /* Reset to label_tick for each extended basic block in scanning order. */
355 static int label_tick_ebb_start
;
357 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
358 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
360 static scalar_int_mode nonzero_bits_mode
;
362 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
363 be safely used. It is zero while computing them and after combine has
364 completed. This former test prevents propagating values based on
365 previously set values, which can be incorrect if a variable is modified
368 static int nonzero_sign_valid
;
371 /* Record one modification to rtl structure
372 to be undone by storing old_contents into *where. */
374 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
380 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
381 union { rtx
*r
; int *i
; int regno
; struct insn_link
**l
; } where
;
384 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
385 num_undo says how many are currently recorded.
387 other_insn is nonzero if we have modified some other insn in the process
388 of working on subst_insn. It must be verified too. */
394 rtx_insn
*other_insn
;
397 static struct undobuf undobuf
;
399 /* Number of times the pseudo being substituted for
400 was found and replaced. */
402 static int n_occurrences
;
404 static rtx
reg_nonzero_bits_for_combine (const_rtx
, scalar_int_mode
,
406 unsigned HOST_WIDE_INT
*);
407 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, scalar_int_mode
,
410 static void do_SUBST (rtx
*, rtx
);
411 static void do_SUBST_INT (int *, int);
412 static void init_reg_last (void);
413 static void setup_incoming_promotions (rtx_insn
*);
414 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
415 static bool cant_combine_insn_p (rtx_insn
*);
416 static bool can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
417 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
418 static bool combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
,
420 static bool contains_muldiv (rtx
);
421 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
423 static void undo_all (void);
424 static void undo_commit (void);
425 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
426 static rtx
subst (rtx
, rtx
, rtx
, bool, bool, bool);
427 static rtx
combine_simplify_rtx (rtx
, machine_mode
, bool, bool);
428 static rtx
simplify_if_then_else (rtx
);
429 static rtx
simplify_set (rtx
);
430 static rtx
simplify_logical (rtx
);
431 static rtx
expand_compound_operation (rtx
);
432 static const_rtx
expand_field_assignment (const_rtx
);
433 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
, rtx
,
434 unsigned HOST_WIDE_INT
, bool, bool, bool);
435 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
436 unsigned HOST_WIDE_INT
*);
437 static rtx
canon_reg_for_combine (rtx
, rtx
);
438 static rtx
force_int_to_mode (rtx
, scalar_int_mode
, scalar_int_mode
,
439 scalar_int_mode
, unsigned HOST_WIDE_INT
, bool);
440 static rtx
force_to_mode (rtx
, machine_mode
,
441 unsigned HOST_WIDE_INT
, bool);
442 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
443 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
444 static bool rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
445 static rtx
make_field_assignment (rtx
);
446 static rtx
apply_distributive_law (rtx
);
447 static rtx
distribute_and_simplify_rtx (rtx
, int);
448 static rtx
simplify_and_const_int_1 (scalar_int_mode
, rtx
,
449 unsigned HOST_WIDE_INT
);
450 static rtx
simplify_and_const_int (rtx
, scalar_int_mode
, rtx
,
451 unsigned HOST_WIDE_INT
);
452 static bool merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
453 HOST_WIDE_INT
, machine_mode
, bool *);
454 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
455 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
457 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
458 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
459 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
461 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
462 static void update_table_tick (rtx
);
463 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
464 static void check_promoted_subreg (rtx_insn
*, rtx
);
465 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
466 static void record_dead_and_set_regs (rtx_insn
*);
467 static bool get_last_value_validate (rtx
*, rtx_insn
*, int, bool);
468 static rtx
get_last_value (const_rtx
);
469 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
470 static bool reg_dead_at_p (rtx
, rtx_insn
*);
471 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
472 static bool reg_bitfield_target_p (rtx
, rtx
);
473 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*,
475 static void distribute_links (struct insn_link
*);
476 static void mark_used_regs_combine (rtx
);
477 static void record_promoted_value (rtx_insn
*, rtx
);
478 static bool unmentioned_reg_p (rtx
, rtx
);
479 static void record_truncated_values (rtx
*, void *);
480 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
481 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
484 /* It is not safe to use ordinary gen_lowpart in combine.
485 See comments in gen_lowpart_for_combine. */
486 #undef RTL_HOOKS_GEN_LOWPART
487 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
489 /* Our implementation of gen_lowpart never emits a new pseudo. */
490 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
491 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
493 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
494 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
496 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
497 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
499 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
500 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
502 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
505 /* Convenience wrapper for the canonicalize_comparison target hook.
506 Target hooks cannot use enum rtx_code. */
508 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
509 bool op0_preserve_value
)
511 int code_int
= (int)*code
;
512 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
513 *code
= (enum rtx_code
)code_int
;
516 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
517 PATTERN cannot be split. Otherwise, it returns an insn sequence.
518 This is a wrapper around split_insns which ensures that the
519 reg_stat vector is made larger if the splitter creates a new
523 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
528 ret
= split_insns (pattern
, insn
);
529 nregs
= max_reg_num ();
530 if (nregs
> reg_stat
.length ())
531 reg_stat
.safe_grow_cleared (nregs
, true);
535 /* This is used by find_single_use to locate an rtx in LOC that
536 contains exactly one use of DEST, which is typically a REG.
537 It returns a pointer to the innermost rtx expression
538 containing DEST. Appearances of DEST that are being used to
539 totally replace it are not counted. */
542 find_single_use_1 (rtx dest
, rtx
*loc
)
545 enum rtx_code code
= GET_CODE (x
);
561 /* If the destination is anything other than PC, a REG or a SUBREG
562 of a REG that occupies all of the REG, the insn uses DEST if
563 it is mentioned in the destination or the source. Otherwise, we
564 need just check the source. */
565 if (GET_CODE (SET_DEST (x
)) != PC
566 && !REG_P (SET_DEST (x
))
567 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
568 && REG_P (SUBREG_REG (SET_DEST (x
)))
569 && !read_modify_subreg_p (SET_DEST (x
))))
572 return find_single_use_1 (dest
, &SET_SRC (x
));
576 return find_single_use_1 (dest
, &XEXP (x
, 0));
582 /* If it wasn't one of the common cases above, check each expression and
583 vector of this code. Look for a unique usage of DEST. */
585 fmt
= GET_RTX_FORMAT (code
);
586 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
590 if (dest
== XEXP (x
, i
)
591 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
592 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
595 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
598 result
= this_result
;
599 else if (this_result
)
600 /* Duplicate usage. */
603 else if (fmt
[i
] == 'E')
607 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
609 if (XVECEXP (x
, i
, j
) == dest
611 && REG_P (XVECEXP (x
, i
, j
))
612 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
615 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
618 result
= this_result
;
619 else if (this_result
)
629 /* See if DEST, produced in INSN, is used only a single time in the
630 sequel. If so, return a pointer to the innermost rtx expression in which
633 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
635 Otherwise, we find the single use by finding an insn that has a
636 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
637 only referenced once in that insn, we know that it must be the first
638 and last insn referencing DEST. */
641 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
646 struct insn_link
*link
;
651 bb
= BLOCK_FOR_INSN (insn
);
652 for (next
= NEXT_INSN (insn
);
653 next
&& BLOCK_FOR_INSN (next
) == bb
;
654 next
= NEXT_INSN (next
))
655 if (NONDEBUG_INSN_P (next
) && dead_or_set_p (next
, dest
))
657 FOR_EACH_LOG_LINK (link
, next
)
658 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
663 result
= find_single_use_1 (dest
, &PATTERN (next
));
673 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
674 insn. The substitution can be undone by undo_all. If INTO is already
675 set to NEWVAL, do not record this change. Because computing NEWVAL might
676 also call SUBST, we have to compute it before we put anything into
680 do_SUBST (rtx
*into
, rtx newval
)
685 if (oldval
== newval
)
688 /* We'd like to catch as many invalid transformations here as
689 possible. Unfortunately, there are way too many mode changes
690 that are perfectly valid, so we'd waste too much effort for
691 little gain doing the checks here. Focus on catching invalid
692 transformations involving integer constants. */
693 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
694 && CONST_INT_P (newval
))
696 /* Sanity check that we're replacing oldval with a CONST_INT
697 that is a valid sign-extension for the original mode. */
698 gcc_assert (INTVAL (newval
)
699 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
701 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
702 CONST_INT is not valid, because after the replacement, the
703 original mode would be gone. Unfortunately, we can't tell
704 when do_SUBST is called to replace the operand thereof, so we
705 perform this test on oldval instead, checking whether an
706 invalid replacement took place before we got here. */
707 gcc_assert (!(GET_CODE (oldval
) == SUBREG
708 && CONST_INT_P (SUBREG_REG (oldval
))));
709 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
710 && CONST_INT_P (XEXP (oldval
, 0))));
714 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
716 buf
= XNEW (struct undo
);
718 buf
->kind
= UNDO_RTX
;
720 buf
->old_contents
.r
= oldval
;
723 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
726 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
728 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
729 for the value of a HOST_WIDE_INT value (including CONST_INT) is
733 do_SUBST_INT (int *into
, int newval
)
738 if (oldval
== newval
)
742 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
744 buf
= XNEW (struct undo
);
746 buf
->kind
= UNDO_INT
;
748 buf
->old_contents
.i
= oldval
;
751 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
754 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
756 /* Similar to SUBST, but just substitute the mode. This is used when
757 changing the mode of a pseudo-register, so that any other
758 references to the entry in the regno_reg_rtx array will change as
762 subst_mode (int regno
, machine_mode newval
)
765 rtx reg
= regno_reg_rtx
[regno
];
766 machine_mode oldval
= GET_MODE (reg
);
768 if (oldval
== newval
)
772 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
774 buf
= XNEW (struct undo
);
776 buf
->kind
= UNDO_MODE
;
777 buf
->where
.regno
= regno
;
778 buf
->old_contents
.m
= oldval
;
779 adjust_reg_mode (reg
, newval
);
781 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
784 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
787 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
790 struct insn_link
* oldval
= *into
;
792 if (oldval
== newval
)
796 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
798 buf
= XNEW (struct undo
);
800 buf
->kind
= UNDO_LINKS
;
802 buf
->old_contents
.l
= oldval
;
805 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
808 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
810 /* Subroutine of try_combine. Determine whether the replacement patterns
811 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
812 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
813 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
814 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
815 of all the instructions can be estimated and the replacements are more
816 expensive than the original sequence. */
819 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
820 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
822 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
823 int new_i2_cost
, new_i3_cost
;
824 int old_cost
, new_cost
;
826 /* Lookup the original insn_costs. */
827 i2_cost
= INSN_COST (i2
);
828 i3_cost
= INSN_COST (i3
);
832 i1_cost
= INSN_COST (i1
);
835 i0_cost
= INSN_COST (i0
);
836 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
837 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
841 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
842 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
848 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
849 i1_cost
= i0_cost
= 0;
852 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
854 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
858 /* Calculate the replacement insn_costs. */
859 rtx tmp
= PATTERN (i3
);
860 PATTERN (i3
) = newpat
;
861 int tmpi
= INSN_CODE (i3
);
863 new_i3_cost
= insn_cost (i3
, optimize_this_for_speed_p
);
865 INSN_CODE (i3
) = tmpi
;
869 PATTERN (i2
) = newi2pat
;
870 tmpi
= INSN_CODE (i2
);
872 new_i2_cost
= insn_cost (i2
, optimize_this_for_speed_p
);
874 INSN_CODE (i2
) = tmpi
;
875 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
876 ? new_i2_cost
+ new_i3_cost
: 0;
880 new_cost
= new_i3_cost
;
884 if (undobuf
.other_insn
)
886 int old_other_cost
, new_other_cost
;
888 old_other_cost
= INSN_COST (undobuf
.other_insn
);
889 tmp
= PATTERN (undobuf
.other_insn
);
890 PATTERN (undobuf
.other_insn
) = newotherpat
;
891 tmpi
= INSN_CODE (undobuf
.other_insn
);
892 INSN_CODE (undobuf
.other_insn
) = -1;
893 new_other_cost
= insn_cost (undobuf
.other_insn
,
894 optimize_this_for_speed_p
);
895 PATTERN (undobuf
.other_insn
) = tmp
;
896 INSN_CODE (undobuf
.other_insn
) = tmpi
;
897 if (old_other_cost
> 0 && new_other_cost
> 0)
899 old_cost
+= old_other_cost
;
900 new_cost
+= new_other_cost
;
906 /* Disallow this combination if both new_cost and old_cost are greater than
907 zero, and new_cost is greater than old cost. */
908 bool reject
= old_cost
> 0 && new_cost
> old_cost
;
912 fprintf (dump_file
, "%s combination of insns ",
913 reject
? "rejecting" : "allowing");
915 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
916 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
917 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
918 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
920 fprintf (dump_file
, "original costs ");
922 fprintf (dump_file
, "%d + ", i0_cost
);
923 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
924 fprintf (dump_file
, "%d + ", i1_cost
);
925 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
928 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
929 new_i2_cost
, new_i3_cost
, new_cost
);
931 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
937 /* Update the uid_insn_cost array with the replacement costs. */
938 INSN_COST (i2
) = new_i2_cost
;
939 INSN_COST (i3
) = new_i3_cost
;
951 /* Delete any insns that copy a register to itself.
952 Return true if the CFG was changed. */
955 delete_noop_moves (void)
957 rtx_insn
*insn
, *next
;
960 bool edges_deleted
= false;
962 FOR_EACH_BB_FN (bb
, cfun
)
964 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
966 next
= NEXT_INSN (insn
);
967 if (INSN_P (insn
) && noop_move_p (insn
))
970 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
972 edges_deleted
|= delete_insn_and_edges (insn
);
977 return edges_deleted
;
981 /* Return false if we do not want to (or cannot) combine DEF. */
983 can_combine_def_p (df_ref def
)
985 /* Do not consider if it is pre/post modification in MEM. */
986 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
989 unsigned int regno
= DF_REF_REGNO (def
);
991 /* Do not combine frame pointer adjustments. */
992 if ((regno
== FRAME_POINTER_REGNUM
993 && (!reload_completed
|| frame_pointer_needed
))
994 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
995 && regno
== HARD_FRAME_POINTER_REGNUM
996 && (!reload_completed
|| frame_pointer_needed
))
997 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
998 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1004 /* Return false if we do not want to (or cannot) combine USE. */
1006 can_combine_use_p (df_ref use
)
1008 /* Do not consider the usage of the stack pointer by function call. */
1009 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1015 /* Fill in log links field for all insns. */
1018 create_log_links (void)
1021 rtx_insn
**next_use
;
1025 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1027 /* Pass through each block from the end, recording the uses of each
1028 register and establishing log links when def is encountered.
1029 Note that we do not clear next_use array in order to save time,
1030 so we have to test whether the use is in the same basic block as def.
1032 There are a few cases below when we do not consider the definition or
1033 usage -- these are taken from original flow.c did. Don't ask me why it is
1034 done this way; I don't know and if it works, I don't want to know. */
1036 FOR_EACH_BB_FN (bb
, cfun
)
1038 FOR_BB_INSNS_REVERSE (bb
, insn
)
1040 if (!NONDEBUG_INSN_P (insn
))
1043 /* Log links are created only once. */
1044 gcc_assert (!LOG_LINKS (insn
));
1046 FOR_EACH_INSN_DEF (def
, insn
)
1048 unsigned int regno
= DF_REF_REGNO (def
);
1051 if (!next_use
[regno
])
1054 if (!can_combine_def_p (def
))
1057 use_insn
= next_use
[regno
];
1058 next_use
[regno
] = NULL
;
1060 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1065 We don't build a LOG_LINK for hard registers contained
1066 in ASM_OPERANDs. If these registers get replaced,
1067 we might wind up changing the semantics of the insn,
1068 even if reload can make what appear to be valid
1069 assignments later. */
1070 if (regno
< FIRST_PSEUDO_REGISTER
1071 && asm_noperands (PATTERN (use_insn
)) >= 0)
1074 /* Don't add duplicate links between instructions. */
1075 struct insn_link
*links
;
1076 FOR_EACH_LOG_LINK (links
, use_insn
)
1077 if (insn
== links
->insn
&& regno
== links
->regno
)
1081 LOG_LINKS (use_insn
)
1082 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1085 FOR_EACH_INSN_USE (use
, insn
)
1086 if (can_combine_use_p (use
))
1087 next_use
[DF_REF_REGNO (use
)] = insn
;
1094 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1095 true if we found a LOG_LINK that proves that A feeds B. This only works
1096 if there are no instructions between A and B which could have a link
1097 depending on A, since in that case we would not record a link for B. */
1100 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1102 struct insn_link
*links
;
1103 FOR_EACH_LOG_LINK (links
, b
)
1104 if (links
->insn
== a
)
1109 /* Main entry point for combiner. F is the first insn of the function.
1110 NREGS is the first unused pseudo-reg number.
1112 Return nonzero if the CFG was changed (e.g. if the combiner has
1113 turned an indirect jump instruction into a direct jump). */
1115 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1117 rtx_insn
*insn
, *next
;
1118 struct insn_link
*links
, *nextlinks
;
1120 basic_block last_bb
;
1122 bool new_direct_jump_p
= false;
1124 for (first
= f
; first
&& !NONDEBUG_INSN_P (first
); )
1125 first
= NEXT_INSN (first
);
1129 combine_attempts
= 0;
1132 combine_successes
= 0;
1134 rtl_hooks
= combine_rtl_hooks
;
1136 reg_stat
.safe_grow_cleared (nregs
, true);
1138 init_recog_no_volatile ();
1140 /* Allocate array for insn info. */
1141 max_uid_known
= get_max_uid ();
1142 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1143 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1144 gcc_obstack_init (&insn_link_obstack
);
1146 nonzero_bits_mode
= int_mode_for_size (HOST_BITS_PER_WIDE_INT
, 0).require ();
1148 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1149 problems when, for example, we have j <<= 1 in a loop. */
1151 nonzero_sign_valid
= 0;
1152 label_tick
= label_tick_ebb_start
= 1;
1154 /* Scan all SETs and see if we can deduce anything about what
1155 bits are known to be zero for some registers and how many copies
1156 of the sign bit are known to exist for those registers.
1158 Also set any known values so that we can use it while searching
1159 for what bits are known to be set. */
1161 setup_incoming_promotions (first
);
1162 /* Allow the entry block and the first block to fall into the same EBB.
1163 Conceptually the incoming promotions are assigned to the entry block. */
1164 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1166 create_log_links ();
1167 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1169 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1174 if (!single_pred_p (this_basic_block
)
1175 || single_pred (this_basic_block
) != last_bb
)
1176 label_tick_ebb_start
= label_tick
;
1177 last_bb
= this_basic_block
;
1179 FOR_BB_INSNS (this_basic_block
, insn
)
1180 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1184 subst_low_luid
= DF_INSN_LUID (insn
);
1187 note_stores (insn
, set_nonzero_bits_and_sign_copies
, insn
);
1188 record_dead_and_set_regs (insn
);
1191 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1192 if (REG_NOTE_KIND (links
) == REG_INC
)
1193 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1196 /* Record the current insn_cost of this instruction. */
1197 INSN_COST (insn
) = insn_cost (insn
, optimize_this_for_speed_p
);
1200 fprintf (dump_file
, "insn_cost %d for ", INSN_COST (insn
));
1201 dump_insn_slim (dump_file
, insn
);
1206 nonzero_sign_valid
= 1;
1208 /* Now scan all the insns in forward order. */
1209 label_tick
= label_tick_ebb_start
= 1;
1211 setup_incoming_promotions (first
);
1212 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1213 int max_combine
= param_max_combine_insns
;
1215 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1217 rtx_insn
*last_combined_insn
= NULL
;
1219 /* Ignore instruction combination in basic blocks that are going to
1220 be removed as unreachable anyway. See PR82386. */
1221 if (EDGE_COUNT (this_basic_block
->preds
) == 0)
1224 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1229 if (!single_pred_p (this_basic_block
)
1230 || single_pred (this_basic_block
) != last_bb
)
1231 label_tick_ebb_start
= label_tick
;
1232 last_bb
= this_basic_block
;
1234 rtl_profile_for_bb (this_basic_block
);
1235 for (insn
= BB_HEAD (this_basic_block
);
1236 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1237 insn
= next
? next
: NEXT_INSN (insn
))
1240 if (!NONDEBUG_INSN_P (insn
))
1243 while (last_combined_insn
1244 && (!NONDEBUG_INSN_P (last_combined_insn
)
1245 || last_combined_insn
->deleted ()))
1246 last_combined_insn
= PREV_INSN (last_combined_insn
);
1247 if (last_combined_insn
== NULL_RTX
1248 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1249 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1250 last_combined_insn
= insn
;
1252 /* See if we know about function return values before this
1253 insn based upon SUBREG flags. */
1254 check_promoted_subreg (insn
, PATTERN (insn
));
1256 /* See if we can find hardregs and subreg of pseudos in
1257 narrower modes. This could help turning TRUNCATEs
1259 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1261 /* Try this insn with each insn it links back to. */
1263 FOR_EACH_LOG_LINK (links
, insn
)
1264 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1265 NULL
, &new_direct_jump_p
,
1266 last_combined_insn
)) != 0)
1268 statistics_counter_event (cfun
, "two-insn combine", 1);
1272 /* Try each sequence of three linked insns ending with this one. */
1274 if (max_combine
>= 3)
1275 FOR_EACH_LOG_LINK (links
, insn
)
1277 rtx_insn
*link
= links
->insn
;
1279 /* If the linked insn has been replaced by a note, then there
1280 is no point in pursuing this chain any further. */
1284 FOR_EACH_LOG_LINK (nextlinks
, link
)
1285 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1286 NULL
, &new_direct_jump_p
,
1287 last_combined_insn
)) != 0)
1289 statistics_counter_event (cfun
, "three-insn combine", 1);
1294 /* Try combining an insn with two different insns whose results it
1296 if (max_combine
>= 3)
1297 FOR_EACH_LOG_LINK (links
, insn
)
1298 for (nextlinks
= links
->next
; nextlinks
;
1299 nextlinks
= nextlinks
->next
)
1300 if ((next
= try_combine (insn
, links
->insn
,
1301 nextlinks
->insn
, NULL
,
1303 last_combined_insn
)) != 0)
1306 statistics_counter_event (cfun
, "three-insn combine", 1);
1310 /* Try four-instruction combinations. */
1311 if (max_combine
>= 4)
1312 FOR_EACH_LOG_LINK (links
, insn
)
1314 struct insn_link
*next1
;
1315 rtx_insn
*link
= links
->insn
;
1317 /* If the linked insn has been replaced by a note, then there
1318 is no point in pursuing this chain any further. */
1322 FOR_EACH_LOG_LINK (next1
, link
)
1324 rtx_insn
*link1
= next1
->insn
;
1327 /* I0 -> I1 -> I2 -> I3. */
1328 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1329 if ((next
= try_combine (insn
, link
, link1
,
1332 last_combined_insn
)) != 0)
1334 statistics_counter_event (cfun
, "four-insn combine", 1);
1337 /* I0, I1 -> I2, I2 -> I3. */
1338 for (nextlinks
= next1
->next
; nextlinks
;
1339 nextlinks
= nextlinks
->next
)
1340 if ((next
= try_combine (insn
, link
, link1
,
1343 last_combined_insn
)) != 0)
1345 statistics_counter_event (cfun
, "four-insn combine", 1);
1350 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1352 rtx_insn
*link1
= next1
->insn
;
1355 /* I0 -> I2; I1, I2 -> I3. */
1356 FOR_EACH_LOG_LINK (nextlinks
, link
)
1357 if ((next
= try_combine (insn
, link
, link1
,
1360 last_combined_insn
)) != 0)
1362 statistics_counter_event (cfun
, "four-insn combine", 1);
1365 /* I0 -> I1; I1, I2 -> I3. */
1366 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1367 if ((next
= try_combine (insn
, link
, link1
,
1370 last_combined_insn
)) != 0)
1372 statistics_counter_event (cfun
, "four-insn combine", 1);
1378 /* Try this insn with each REG_EQUAL note it links back to. */
1379 FOR_EACH_LOG_LINK (links
, insn
)
1382 rtx_insn
*temp
= links
->insn
;
1383 if ((set
= single_set (temp
)) != 0
1384 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1385 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1386 && ! side_effects_p (SET_SRC (set
))
1387 /* Avoid using a register that may already been marked
1388 dead by an earlier instruction. */
1389 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1390 && (GET_MODE (note
) == VOIDmode
1391 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1392 : (GET_MODE (SET_DEST (set
)) == GET_MODE (note
)
1393 && (GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
1394 || (GET_MODE (XEXP (SET_DEST (set
), 0))
1395 == GET_MODE (note
))))))
1397 /* Temporarily replace the set's source with the
1398 contents of the REG_EQUAL note. The insn will
1399 be deleted or recognized by try_combine. */
1400 rtx orig_src
= SET_SRC (set
);
1401 rtx orig_dest
= SET_DEST (set
);
1402 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
)
1403 SET_DEST (set
) = XEXP (SET_DEST (set
), 0);
1404 SET_SRC (set
) = note
;
1406 i2mod_old_rhs
= copy_rtx (orig_src
);
1407 i2mod_new_rhs
= copy_rtx (note
);
1408 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1410 last_combined_insn
);
1414 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1417 INSN_CODE (temp
) = -1;
1418 SET_SRC (set
) = orig_src
;
1419 SET_DEST (set
) = orig_dest
;
1424 record_dead_and_set_regs (insn
);
1431 default_rtl_profile ();
1434 if (purge_all_dead_edges ())
1435 new_direct_jump_p
= true;
1436 if (delete_noop_moves ())
1437 new_direct_jump_p
= true;
1440 obstack_free (&insn_link_obstack
, NULL
);
1441 free (uid_log_links
);
1442 free (uid_insn_cost
);
1443 reg_stat
.release ();
1446 struct undo
*undo
, *next
;
1447 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1455 statistics_counter_event (cfun
, "attempts", combine_attempts
);
1456 statistics_counter_event (cfun
, "merges", combine_merges
);
1457 statistics_counter_event (cfun
, "extras", combine_extras
);
1458 statistics_counter_event (cfun
, "successes", combine_successes
);
1460 nonzero_sign_valid
= 0;
1461 rtl_hooks
= general_rtl_hooks
;
1463 /* Make recognizer allow volatile MEMs again. */
1466 return new_direct_jump_p
;
1469 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1472 init_reg_last (void)
1477 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1478 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1481 /* Set up any promoted values for incoming argument registers. */
1484 setup_incoming_promotions (rtx_insn
*first
)
1487 bool strictly_local
= false;
1489 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1490 arg
= DECL_CHAIN (arg
))
1492 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1494 machine_mode mode1
, mode2
, mode3
, mode4
;
1496 /* Only continue if the incoming argument is in a register. */
1500 /* Determine, if possible, whether all call sites of the current
1501 function lie within the current compilation unit. (This does
1502 take into account the exporting of a function via taking its
1503 address, and so forth.) */
1505 = cgraph_node::local_info_node (current_function_decl
)->local
;
1507 /* The mode and signedness of the argument before any promotions happen
1508 (equal to the mode of the pseudo holding it at that stage). */
1509 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1510 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1512 /* The mode and signedness of the argument after any source language and
1513 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1514 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1515 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1517 /* The mode and signedness of the argument as it is actually passed,
1518 see assign_parm_setup_reg in function.cc. */
1519 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1520 TREE_TYPE (cfun
->decl
), 0);
1522 /* The mode of the register in which the argument is being passed. */
1523 mode4
= GET_MODE (reg
);
1525 /* Eliminate sign extensions in the callee when:
1526 (a) A mode promotion has occurred; */
1529 /* (b) The mode of the register is the same as the mode of
1530 the argument as it is passed; */
1533 /* (c) There's no language level extension; */
1536 /* (c.1) All callers are from the current compilation unit. If that's
1537 the case we don't have to rely on an ABI, we only have to know
1538 what we're generating right now, and we know that we will do the
1539 mode1 to mode2 promotion with the given sign. */
1540 else if (!strictly_local
)
1542 /* (c.2) The combination of the two promotions is useful. This is
1543 true when the signs match, or if the first promotion is unsigned.
1544 In the later case, (sign_extend (zero_extend x)) is the same as
1545 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1551 /* Record that the value was promoted from mode1 to mode3,
1552 so that any sign extension at the head of the current
1553 function may be eliminated. */
1554 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1555 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1556 record_value_for_reg (reg
, first
, x
);
1560 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1561 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1562 because some machines (maybe most) will actually do the sign-extension and
1563 this is the conservative approach.
1565 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1569 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1571 scalar_int_mode int_mode
;
1572 if (CONST_INT_P (src
)
1573 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1574 && GET_MODE_PRECISION (int_mode
) < prec
1576 && val_signbit_known_set_p (int_mode
, INTVAL (src
)))
1577 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (int_mode
));
1582 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1586 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1589 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1590 unsigned HOST_WIDE_INT bits
= 0;
1591 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1592 unsigned int num
= 0;
1595 reg_equal
= XEXP (reg_equal_note
, 0);
1597 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
1599 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1601 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1604 /* Don't call nonzero_bits if it cannot change anything. */
1605 if (rsp
->nonzero_bits
!= HOST_WIDE_INT_M1U
)
1607 machine_mode mode
= GET_MODE (x
);
1608 if (GET_MODE_CLASS (mode
) == MODE_INT
1609 && HWI_COMPUTABLE_MODE_P (mode
))
1610 mode
= nonzero_bits_mode
;
1611 bits
= nonzero_bits (src
, mode
);
1612 if (reg_equal
&& bits
)
1613 bits
&= nonzero_bits (reg_equal
, mode
);
1614 rsp
->nonzero_bits
|= bits
;
1617 /* Don't call num_sign_bit_copies if it cannot change anything. */
1618 if (rsp
->sign_bit_copies
!= 1)
1620 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1621 if (reg_equal
&& maybe_ne (num
, GET_MODE_PRECISION (GET_MODE (x
))))
1623 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1624 if (num
== 0 || numeq
> num
)
1627 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1628 rsp
->sign_bit_copies
= num
;
1632 /* Called via note_stores. If X is a pseudo that is narrower than
1633 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1635 If we are setting only a portion of X and we can't figure out what
1636 portion, assume all bits will be used since we don't know what will
1639 Similarly, set how many bits of X are known to be copies of the sign bit
1640 at all locations in the function. This is the smallest number implied
1644 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1646 rtx_insn
*insn
= (rtx_insn
*) data
;
1647 scalar_int_mode mode
;
1650 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1651 /* If this register is undefined at the start of the file, we can't
1652 say what its contents were. */
1653 && ! REGNO_REG_SET_P
1654 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1655 && is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
)
1656 && HWI_COMPUTABLE_MODE_P (mode
))
1658 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1660 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1662 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1663 rsp
->sign_bit_copies
= 1;
1667 /* If this register is being initialized using itself, and the
1668 register is uninitialized in this basic block, and there are
1669 no LOG_LINKS which set the register, then part of the
1670 register is uninitialized. In that case we can't assume
1671 anything about the number of nonzero bits.
1673 ??? We could do better if we checked this in
1674 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1675 could avoid making assumptions about the insn which initially
1676 sets the register, while still using the information in other
1677 insns. We would have to be careful to check every insn
1678 involved in the combination. */
1681 && reg_referenced_p (x
, PATTERN (insn
))
1682 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1685 struct insn_link
*link
;
1687 FOR_EACH_LOG_LINK (link
, insn
)
1688 if (dead_or_set_p (link
->insn
, x
))
1692 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1693 rsp
->sign_bit_copies
= 1;
1698 /* If this is a complex assignment, see if we can convert it into a
1699 simple assignment. */
1700 set
= expand_field_assignment (set
);
1702 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1703 set what we know about X. */
1705 if (SET_DEST (set
) == x
1706 || (paradoxical_subreg_p (SET_DEST (set
))
1707 && SUBREG_REG (SET_DEST (set
)) == x
))
1708 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1711 rsp
->nonzero_bits
= GET_MODE_MASK (mode
);
1712 rsp
->sign_bit_copies
= 1;
1717 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1718 optionally insns that were previously combined into I3 or that will be
1719 combined into the merger of INSN and I3. The order is PRED, PRED2,
1720 INSN, SUCC, SUCC2, I3.
1722 Return false if the combination is not allowed for any reason.
1724 If the combination is allowed, *PDEST will be set to the single
1725 destination of INSN and *PSRC to the single source, and this function
1726 will return true. */
1729 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1730 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1731 rtx
*pdest
, rtx
*psrc
)
1738 bool all_adjacent
= true;
1739 bool (*is_volatile_p
) (const_rtx
);
1745 if (next_active_insn (succ2
) != i3
)
1746 all_adjacent
= false;
1747 if (next_active_insn (succ
) != succ2
)
1748 all_adjacent
= false;
1750 else if (next_active_insn (succ
) != i3
)
1751 all_adjacent
= false;
1752 if (next_active_insn (insn
) != succ
)
1753 all_adjacent
= false;
1755 else if (next_active_insn (insn
) != i3
)
1756 all_adjacent
= false;
1758 /* Can combine only if previous insn is a SET of a REG or a SUBREG,
1759 or a PARALLEL consisting of such a SET and CLOBBERs.
1761 If INSN has CLOBBER parallel parts, ignore them for our processing.
1762 By definition, these happen during the execution of the insn. When it
1763 is merged with another insn, all bets are off. If they are, in fact,
1764 needed and aren't also supplied in I3, they may be added by
1765 recog_for_combine. Otherwise, it won't match.
1767 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1770 Get the source and destination of INSN. If more than one, can't
1773 if (GET_CODE (PATTERN (insn
)) == SET
)
1774 set
= PATTERN (insn
);
1775 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1776 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1778 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1780 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1782 switch (GET_CODE (elt
))
1784 /* This is important to combine floating point insns
1785 for the SH4 port. */
1787 /* Combining an isolated USE doesn't make sense.
1788 We depend here on combinable_i3pat to reject them. */
1789 /* The code below this loop only verifies that the inputs of
1790 the SET in INSN do not change. We call reg_set_between_p
1791 to verify that the REG in the USE does not change between
1793 If the USE in INSN was for a pseudo register, the matching
1794 insn pattern will likely match any register; combining this
1795 with any other USE would only be safe if we knew that the
1796 used registers have identical values, or if there was
1797 something to tell them apart, e.g. different modes. For
1798 now, we forgo such complicated tests and simply disallow
1799 combining of USES of pseudo registers with any other USE. */
1800 if (REG_P (XEXP (elt
, 0))
1801 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1803 rtx i3pat
= PATTERN (i3
);
1804 int i
= XVECLEN (i3pat
, 0) - 1;
1805 unsigned int regno
= REGNO (XEXP (elt
, 0));
1809 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1811 if (GET_CODE (i3elt
) == USE
1812 && REG_P (XEXP (i3elt
, 0))
1813 && (REGNO (XEXP (i3elt
, 0)) == regno
1814 ? reg_set_between_p (XEXP (elt
, 0),
1815 PREV_INSN (insn
), i3
)
1816 : regno
>= FIRST_PSEUDO_REGISTER
))
1823 /* We can ignore CLOBBERs. */
1828 /* Ignore SETs whose result isn't used but not those that
1829 have side-effects. */
1830 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1831 && insn_nothrow_p (insn
)
1832 && !side_effects_p (elt
))
1835 /* If we have already found a SET, this is a second one and
1836 so we cannot combine with this insn. */
1844 /* Anything else means we can't combine. */
1850 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1851 so don't do anything with it. */
1852 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1861 /* The simplification in expand_field_assignment may call back to
1862 get_last_value, so set safe guard here. */
1863 subst_low_luid
= DF_INSN_LUID (insn
);
1865 set
= expand_field_assignment (set
);
1866 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1868 /* Do not eliminate user-specified register if it is in an
1869 asm input because we may break the register asm usage defined
1870 in GCC manual if allow to do so.
1871 Be aware that this may cover more cases than we expect but this
1872 should be harmless. */
1873 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1874 && extract_asm_operands (PATTERN (i3
)))
1877 /* Don't eliminate a store in the stack pointer. */
1878 if (dest
== stack_pointer_rtx
1879 /* Don't combine with an insn that sets a register to itself if it has
1880 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1881 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1882 /* Can't merge an ASM_OPERANDS. */
1883 || GET_CODE (src
) == ASM_OPERANDS
1884 /* Can't merge a function call. */
1885 || GET_CODE (src
) == CALL
1886 /* Don't eliminate a function call argument. */
1888 && (find_reg_fusage (i3
, USE
, dest
)
1890 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1891 && global_regs
[REGNO (dest
)])))
1892 /* Don't substitute into an incremented register. */
1893 || FIND_REG_INC_NOTE (i3
, dest
)
1894 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1895 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1896 /* Don't substitute into a non-local goto, this confuses CFG. */
1897 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1898 /* Make sure that DEST is not used after INSN but before SUCC, or
1899 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1902 && (reg_used_between_p (dest
, succ2
, i3
)
1903 || reg_used_between_p (dest
, succ
, succ2
)))
1904 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))
1905 || (!succ2
&& !succ
&& reg_used_between_p (dest
, insn
, i3
))
1907 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1908 that case SUCC is not in the insn stream, so use SUCC2
1909 instead for this test. */
1910 && reg_used_between_p (dest
, insn
,
1912 && INSN_UID (succ
) == INSN_UID (succ2
)
1914 /* Make sure that the value that is to be substituted for the register
1915 does not use any registers whose values alter in between. However,
1916 If the insns are adjacent, a use can't cross a set even though we
1917 think it might (this can happen for a sequence of insns each setting
1918 the same destination; last_set of that register might point to
1919 a NOTE). If INSN has a REG_EQUIV note, the register is always
1920 equivalent to the memory so the substitution is valid even if there
1921 are intervening stores. Also, don't move a volatile asm or
1922 UNSPEC_VOLATILE across any other insns. */
1925 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1926 && modified_between_p (src
, insn
, i3
))
1927 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1928 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1929 /* Don't combine across a CALL_INSN, because that would possibly
1930 change whether the life span of some REGs crosses calls or not,
1931 and it is a pain to update that information.
1932 Exception: if source is a constant, moving it later can't hurt.
1933 Accept that as a special case. */
1934 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1937 /* DEST must be a REG. */
1940 /* If register alignment is being enforced for multi-word items in all
1941 cases except for parameters, it is possible to have a register copy
1942 insn referencing a hard register that is not allowed to contain the
1943 mode being copied and which would not be valid as an operand of most
1944 insns. Eliminate this problem by not combining with such an insn.
1946 Also, on some machines we don't want to extend the life of a hard
1950 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1951 && !targetm
.hard_regno_mode_ok (REGNO (dest
), GET_MODE (dest
)))
1952 /* Don't extend the life of a hard register unless it is
1953 user variable (if we have few registers) or it can't
1954 fit into the desired register (meaning something special
1956 Also avoid substituting a return register into I3, because
1957 reload can't handle a conflict with constraints of other
1959 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1960 && !targetm
.hard_regno_mode_ok (REGNO (src
),
1968 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1969 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1970 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1972 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1974 /* If the clobber represents an earlyclobber operand, we must not
1975 substitute an expression containing the clobbered register.
1976 As we do not analyze the constraint strings here, we have to
1977 make the conservative assumption. However, if the register is
1978 a fixed hard reg, the clobber cannot represent any operand;
1979 we leave it up to the machine description to either accept or
1980 reject use-and-clobber patterns. */
1982 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1983 || !fixed_regs
[REGNO (reg
)])
1984 if (reg_overlap_mentioned_p (reg
, src
))
1988 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1989 or not), reject, unless nothing volatile comes between it and I3 */
1991 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1993 /* Make sure neither succ nor succ2 contains a volatile reference. */
1994 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1996 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1998 /* We'll check insns between INSN and I3 below. */
2001 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2002 to be an explicit register variable, and was chosen for a reason. */
2004 if (GET_CODE (src
) == ASM_OPERANDS
2005 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2008 /* If INSN contains volatile references (specifically volatile MEMs),
2009 we cannot combine across any other volatile references.
2010 Even if INSN doesn't contain volatile references, any intervening
2011 volatile insn might affect machine state. */
2013 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2017 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2018 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2021 /* If INSN contains an autoincrement or autodecrement, make sure that
2022 register is not used between there and I3, and not already used in
2023 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2024 Also insist that I3 not be a jump if using LRA; if it were one
2025 and the incremented register were spilled, we would lose.
2026 Reload handles this correctly. */
2029 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2030 if (REG_NOTE_KIND (link
) == REG_INC
2031 && ((JUMP_P (i3
) && targetm
.lra_p ())
2032 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2033 || (pred
!= NULL_RTX
2034 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2035 || (pred2
!= NULL_RTX
2036 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2037 || (succ
!= NULL_RTX
2038 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2039 || (succ2
!= NULL_RTX
2040 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2041 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2044 /* If we get here, we have passed all the tests and the combination is
2053 /* LOC is the location within I3 that contains its pattern or the component
2054 of a PARALLEL of the pattern. We validate that it is valid for combining.
2056 One problem is if I3 modifies its output, as opposed to replacing it
2057 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2058 doing so would produce an insn that is not equivalent to the original insns.
2062 (set (reg:DI 101) (reg:DI 100))
2063 (set (subreg:SI (reg:DI 101) 0) <foo>)
2065 This is NOT equivalent to:
2067 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2068 (set (reg:DI 101) (reg:DI 100))])
2070 Not only does this modify 100 (in which case it might still be valid
2071 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2073 We can also run into a problem if I2 sets a register that I1
2074 uses and I1 gets directly substituted into I3 (not via I2). In that
2075 case, we would be getting the wrong value of I2DEST into I3, so we
2076 must reject the combination. This case occurs when I2 and I1 both
2077 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2078 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2079 of a SET must prevent combination from occurring. The same situation
2080 can occur for I0, in which case I0_NOT_IN_SRC is set.
2082 Before doing the above check, we first try to expand a field assignment
2083 into a set of logical operations.
2085 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2086 we place a register that is both set and used within I3. If more than one
2087 such register is detected, we fail.
2089 Return true if the combination is valid, false otherwise. */
2092 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2093 bool i1_not_in_src
, bool i0_not_in_src
, rtx
*pi3dest_killed
)
2097 if (GET_CODE (x
) == SET
)
2100 rtx dest
= SET_DEST (set
);
2101 rtx src
= SET_SRC (set
);
2102 rtx inner_dest
= dest
;
2105 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2106 || GET_CODE (inner_dest
) == SUBREG
2107 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2108 inner_dest
= XEXP (inner_dest
, 0);
2110 /* Check for the case where I3 modifies its output, as discussed
2111 above. We don't want to prevent pseudos from being combined
2112 into the address of a MEM, so only prevent the combination if
2113 i1 or i2 set the same MEM. */
2114 if ((inner_dest
!= dest
&&
2115 (!MEM_P (inner_dest
)
2116 || rtx_equal_p (i2dest
, inner_dest
)
2117 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2118 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2119 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2120 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2121 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2123 /* This is the same test done in can_combine_p except we can't test
2124 all_adjacent; we don't have to, since this instruction will stay
2125 in place, thus we are not considering increasing the lifetime of
2128 Also, if this insn sets a function argument, combining it with
2129 something that might need a spill could clobber a previous
2130 function argument; the all_adjacent test in can_combine_p also
2131 checks this; here, we do a more specific test for this case. */
2133 || (REG_P (inner_dest
)
2134 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2135 && !targetm
.hard_regno_mode_ok (REGNO (inner_dest
),
2136 GET_MODE (inner_dest
)))
2137 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2138 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2141 /* If DEST is used in I3, it is being killed in this insn, so
2142 record that for later. We have to consider paradoxical
2143 subregs here, since they kill the whole register, but we
2144 ignore partial subregs, STRICT_LOW_PART, etc.
2145 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2146 STACK_POINTER_REGNUM, since these are always considered to be
2147 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2149 if (GET_CODE (subdest
) == SUBREG
&& !partial_subreg_p (subdest
))
2150 subdest
= SUBREG_REG (subdest
);
2153 && reg_referenced_p (subdest
, PATTERN (i3
))
2154 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2155 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2156 || REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
)
2157 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2158 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2159 || ! fixed_regs
[REGNO (subdest
)]))
2160 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2162 if (*pi3dest_killed
)
2165 *pi3dest_killed
= subdest
;
2169 else if (GET_CODE (x
) == PARALLEL
)
2173 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2174 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2175 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2182 /* Return true if X is an arithmetic expression that contains a multiplication
2183 and division. We don't count multiplications by powers of two here. */
2186 contains_muldiv (rtx x
)
2188 switch (GET_CODE (x
))
2190 case MOD
: case DIV
: case UMOD
: case UDIV
:
2194 return ! (CONST_INT_P (XEXP (x
, 1))
2195 && pow2p_hwi (UINTVAL (XEXP (x
, 1))));
2198 return contains_muldiv (XEXP (x
, 0))
2199 || contains_muldiv (XEXP (x
, 1));
2202 return contains_muldiv (XEXP (x
, 0));
2208 /* Determine whether INSN can be used in a combination. Return true if
2209 not. This is used in try_combine to detect early some cases where we
2210 can't perform combinations. */
2213 cant_combine_insn_p (rtx_insn
*insn
)
2218 /* If this isn't really an insn, we can't do anything.
2219 This can occur when flow deletes an insn that it has merged into an
2220 auto-increment address. */
2221 if (!NONDEBUG_INSN_P (insn
))
2224 /* Never combine loads and stores involving hard regs that are likely
2225 to be spilled. The register allocator can usually handle such
2226 reg-reg moves by tying. If we allow the combiner to make
2227 substitutions of likely-spilled regs, reload might die.
2228 As an exception, we allow combinations involving fixed regs; these are
2229 not available to the register allocator so there's no risk involved. */
2231 set
= single_set (insn
);
2234 src
= SET_SRC (set
);
2235 dest
= SET_DEST (set
);
2236 if (GET_CODE (src
) == SUBREG
)
2237 src
= SUBREG_REG (src
);
2238 if (GET_CODE (dest
) == SUBREG
)
2239 dest
= SUBREG_REG (dest
);
2240 if (REG_P (src
) && REG_P (dest
)
2241 && ((HARD_REGISTER_P (src
)
2242 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2243 #ifdef LEAF_REGISTERS
2244 && ! LEAF_REGISTERS
[REGNO (src
)])
2248 || (HARD_REGISTER_P (dest
)
2249 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2250 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2256 struct likely_spilled_retval_info
2258 unsigned regno
, nregs
;
2262 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2263 hard registers that are known to be written to / clobbered in full. */
2265 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2267 struct likely_spilled_retval_info
*const info
=
2268 (struct likely_spilled_retval_info
*) data
;
2269 unsigned regno
, nregs
;
2272 if (!REG_P (XEXP (set
, 0)))
2275 if (regno
>= info
->regno
+ info
->nregs
)
2277 nregs
= REG_NREGS (x
);
2278 if (regno
+ nregs
<= info
->regno
)
2280 new_mask
= (2U << (nregs
- 1)) - 1;
2281 if (regno
< info
->regno
)
2282 new_mask
>>= info
->regno
- regno
;
2284 new_mask
<<= regno
- info
->regno
;
2285 info
->mask
&= ~new_mask
;
2288 /* Return true iff part of the return value is live during INSN, and
2289 it is likely spilled. This can happen when more than one insn is needed
2290 to copy the return value, e.g. when we consider to combine into the
2291 second copy insn for a complex value. */
2294 likely_spilled_retval_p (rtx_insn
*insn
)
2296 rtx_insn
*use
= BB_END (this_basic_block
);
2299 unsigned regno
, nregs
;
2300 /* We assume here that no machine mode needs more than
2301 32 hard registers when the value overlaps with a register
2302 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2304 struct likely_spilled_retval_info info
;
2306 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2308 reg
= XEXP (PATTERN (use
), 0);
2309 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2311 regno
= REGNO (reg
);
2312 nregs
= REG_NREGS (reg
);
2315 mask
= (2U << (nregs
- 1)) - 1;
2317 /* Disregard parts of the return value that are set later. */
2321 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2323 note_stores (p
, likely_spilled_retval_1
, &info
);
2326 /* Check if any of the (probably) live return value registers is
2331 if ((mask
& 1 << nregs
)
2332 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2338 /* Adjust INSN after we made a change to its destination.
2340 Changing the destination can invalidate notes that say something about
2341 the results of the insn and a LOG_LINK pointing to the insn. */
2344 adjust_for_new_dest (rtx_insn
*insn
)
2346 /* For notes, be conservative and simply remove them. */
2347 remove_reg_equal_equiv_notes (insn
, true);
2349 /* The new insn will have a destination that was previously the destination
2350 of an insn just above it. Call distribute_links to make a LOG_LINK from
2351 the next use of that destination. */
2353 rtx set
= single_set (insn
);
2356 rtx reg
= SET_DEST (set
);
2358 while (GET_CODE (reg
) == ZERO_EXTRACT
2359 || GET_CODE (reg
) == STRICT_LOW_PART
2360 || GET_CODE (reg
) == SUBREG
)
2361 reg
= XEXP (reg
, 0);
2362 gcc_assert (REG_P (reg
));
2364 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2366 df_insn_rescan (insn
);
2369 /* Return TRUE if combine can reuse reg X in mode MODE.
2370 ADDED_SETS is trueif the original set is still required. */
2372 can_change_dest_mode (rtx x
, bool added_sets
, machine_mode mode
)
2379 /* Don't change between modes with different underlying register sizes,
2380 since this could lead to invalid subregs. */
2381 if (maybe_ne (REGMODE_NATURAL_SIZE (mode
),
2382 REGMODE_NATURAL_SIZE (GET_MODE (x
))))
2386 /* Allow hard registers if the new mode is legal, and occupies no more
2387 registers than the old mode. */
2388 if (regno
< FIRST_PSEUDO_REGISTER
)
2389 return (targetm
.hard_regno_mode_ok (regno
, mode
)
2390 && REG_NREGS (x
) >= hard_regno_nregs (regno
, mode
));
2392 /* Or a pseudo that is only used once. */
2393 return (regno
< reg_n_sets_max
2394 && REG_N_SETS (regno
) == 1
2396 && !REG_USERVAR_P (x
));
2400 /* Check whether X, the destination of a set, refers to part of
2401 the register specified by REG. */
2404 reg_subword_p (rtx x
, rtx reg
)
2406 /* Check that reg is an integer mode register. */
2407 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2410 if (GET_CODE (x
) == STRICT_LOW_PART
2411 || GET_CODE (x
) == ZERO_EXTRACT
)
2414 return GET_CODE (x
) == SUBREG
2415 && !paradoxical_subreg_p (x
)
2416 && SUBREG_REG (x
) == reg
2417 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2420 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2421 by an arbitrary number of CLOBBERs. */
2423 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2425 if (GET_CODE (pat
) != PARALLEL
)
2428 int len
= XVECLEN (pat
, 0);
2433 for (i
= 0; i
< n
; i
++)
2434 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2435 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2437 for ( ; i
< len
; i
++)
2438 switch (GET_CODE (XVECEXP (pat
, 0, i
)))
2441 if (XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
2450 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2451 CLOBBERs), can be split into individual SETs in that order, without
2452 changing semantics. */
2454 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2456 if (!insn_nothrow_p (insn
))
2459 rtx pat
= PATTERN (insn
);
2462 for (i
= 0; i
< n
; i
++)
2464 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2467 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2469 for (j
= i
+ 1; j
< n
; j
++)
2470 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2477 /* Return whether X is just a single_set, with the source
2478 a general_operand. */
2480 is_just_move (rtx_insn
*x
)
2482 rtx set
= single_set (x
);
2486 return general_operand (SET_SRC (set
), VOIDmode
);
2489 /* Callback function to count autoincs. */
2492 count_auto_inc (rtx
, rtx
, rtx
, rtx
, rtx
, void *arg
)
2499 /* Try to combine the insns I0, I1 and I2 into I3.
2500 Here I0, I1 and I2 appear earlier than I3.
2501 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2504 If we are combining more than two insns and the resulting insn is not
2505 recognized, try splitting it into two insns. If that happens, I2 and I3
2506 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2507 Otherwise, I0, I1 and I2 are pseudo-deleted.
2509 Return 0 if the combination does not work. Then nothing is changed.
2510 If we did the combination, return the insn at which combine should
2513 Set NEW_DIRECT_JUMP_P to true if try_combine creates a
2514 new direct jump instruction.
2516 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2517 been I3 passed to an earlier try_combine within the same basic
2521 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2522 bool *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2524 /* New patterns for I3 and I2, respectively. */
2525 rtx newpat
, newi2pat
= 0;
2526 rtvec newpat_vec_with_clobbers
= 0;
2527 bool substed_i2
= false, substed_i1
= false, substed_i0
= false;
2528 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2530 bool added_sets_0
, added_sets_1
, added_sets_2
;
2531 /* Total number of SETs to put into I3. */
2533 /* Nonzero if I2's or I1's body now appears in I3. */
2534 int i2_is_used
= 0, i1_is_used
= 0;
2535 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2536 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2537 /* Contains I3 if the destination of I3 is used in its source, which means
2538 that the old life of I3 is being killed. If that usage is placed into
2539 I2 and not in I3, a REG_DEAD note must be made. */
2540 rtx i3dest_killed
= 0;
2541 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2542 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2543 /* Copy of SET_SRC of I1 and I0, if needed. */
2544 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2545 /* Set if I2DEST was reused as a scratch register. */
2546 bool i2scratch
= false;
2547 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2548 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2549 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2550 bool i2dest_in_i2src
= false, i1dest_in_i1src
= false;
2551 bool i2dest_in_i1src
= false, i0dest_in_i0src
= false;
2552 bool i1dest_in_i0src
= false, i2dest_in_i0src
= false;;
2553 bool i2dest_killed
= false, i1dest_killed
= false, i0dest_killed
= false;
2554 bool i1_feeds_i2_n
= false, i0_feeds_i2_n
= false, i0_feeds_i1_n
= false;
2555 /* Notes that must be added to REG_NOTES in I3 and I2. */
2556 rtx new_i3_notes
, new_i2_notes
;
2557 /* Notes that we substituted I3 into I2 instead of the normal case. */
2558 bool i3_subst_into_i2
= false;
2559 /* Notes that I1, I2 or I3 is a MULT operation. */
2560 bool have_mult
= false;
2561 bool swap_i2i3
= false;
2562 bool split_i2i3
= false;
2563 bool changed_i3_dest
= false;
2564 bool i2_was_move
= false, i3_was_move
= false;
2568 rtx_insn
*temp_insn
;
2570 struct insn_link
*link
;
2572 rtx new_other_notes
;
2574 scalar_int_mode dest_mode
, temp_mode
;
2575 bool has_non_call_exception
= false;
2577 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2579 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2582 /* Only try four-insn combinations when there's high likelihood of
2583 success. Look for simple insns, such as loads of constants or
2584 binary operations involving a constant. */
2592 if (!flag_expensive_optimizations
)
2595 for (i
= 0; i
< 4; i
++)
2597 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2598 rtx set
= single_set (insn
);
2602 src
= SET_SRC (set
);
2603 if (CONSTANT_P (src
))
2608 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2610 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2611 || GET_CODE (src
) == LSHIFTRT
)
2615 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2616 are likely manipulating its value. Ideally we'll be able to combine
2617 all four insns into a bitfield insertion of some kind.
2619 Note the source in I0 might be inside a sign/zero extension and the
2620 memory modes in I0 and I3 might be different. So extract the address
2621 from the destination of I3 and search for it in the source of I0.
2623 In the event that there's a match but the source/dest do not actually
2624 refer to the same memory, the worst that happens is we try some
2625 combinations that we wouldn't have otherwise. */
2626 if ((set0
= single_set (i0
))
2627 /* Ensure the source of SET0 is a MEM, possibly buried inside
2629 && (GET_CODE (SET_SRC (set0
)) == MEM
2630 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2631 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2632 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2633 && (set3
= single_set (i3
))
2634 /* Ensure the destination of SET3 is a MEM. */
2635 && GET_CODE (SET_DEST (set3
)) == MEM
2636 /* Would it be better to extract the base address for the MEM
2637 in SET3 and look for that? I don't have cases where it matters
2638 but I could envision such cases. */
2639 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2642 if (ngood
< 2 && nshift
< 2)
2646 /* Exit early if one of the insns involved can't be used for
2649 || (i1
&& CALL_P (i1
))
2650 || (i0
&& CALL_P (i0
))
2651 || cant_combine_insn_p (i3
)
2652 || cant_combine_insn_p (i2
)
2653 || (i1
&& cant_combine_insn_p (i1
))
2654 || (i0
&& cant_combine_insn_p (i0
))
2655 || likely_spilled_retval_p (i3
))
2659 undobuf
.other_insn
= 0;
2661 /* Reset the hard register usage information. */
2662 CLEAR_HARD_REG_SET (newpat_used_regs
);
2664 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2667 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2668 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2670 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2671 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2673 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2674 INSN_UID (i2
), INSN_UID (i3
));
2677 dump_insn_slim (dump_file
, i0
);
2679 dump_insn_slim (dump_file
, i1
);
2680 dump_insn_slim (dump_file
, i2
);
2681 dump_insn_slim (dump_file
, i3
);
2684 /* If multiple insns feed into one of I2 or I3, they can be in any
2685 order. To simplify the code below, reorder them in sequence. */
2686 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2688 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2690 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2693 added_links_insn
= 0;
2694 added_notes_insn
= 0;
2696 /* First check for one important special case that the code below will
2697 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2698 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2699 we may be able to replace that destination with the destination of I3.
2700 This occurs in the common code where we compute both a quotient and
2701 remainder into a structure, in which case we want to do the computation
2702 directly into the structure to avoid register-register copies.
2704 Note that this case handles both multiple sets in I2 and also cases
2705 where I2 has a number of CLOBBERs inside the PARALLEL.
2707 We make very conservative checks below and only try to handle the
2708 most common cases of this. For example, we only handle the case
2709 where I2 and I3 are adjacent to avoid making difficult register
2712 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2713 && REG_P (SET_SRC (PATTERN (i3
)))
2714 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2715 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2716 && GET_CODE (PATTERN (i2
)) == PARALLEL
2717 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2718 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2719 below would need to check what is inside (and reg_overlap_mentioned_p
2720 doesn't support those codes anyway). Don't allow those destinations;
2721 the resulting insn isn't likely to be recognized anyway. */
2722 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2723 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2724 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2725 SET_DEST (PATTERN (i3
)))
2726 && next_active_insn (i2
) == i3
)
2728 rtx p2
= PATTERN (i2
);
2730 /* Make sure that the destination of I3,
2731 which we are going to substitute into one output of I2,
2732 is not used within another output of I2. We must avoid making this:
2733 (parallel [(set (mem (reg 69)) ...)
2734 (set (reg 69) ...)])
2735 which is not well-defined as to order of actions.
2736 (Besides, reload can't handle output reloads for this.)
2738 The problem can also happen if the dest of I3 is a memory ref,
2739 if another dest in I2 is an indirect memory ref.
2741 Neither can this PARALLEL be an asm. We do not allow combining
2742 that usually (see can_combine_p), so do not here either. */
2744 for (i
= 0; ok
&& i
< XVECLEN (p2
, 0); i
++)
2746 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2747 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2748 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2749 SET_DEST (XVECEXP (p2
, 0, i
))))
2751 else if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2752 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2757 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2758 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2759 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2764 subst_low_luid
= DF_INSN_LUID (i2
);
2766 added_sets_2
= added_sets_1
= added_sets_0
= false;
2767 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2768 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2769 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2771 /* Replace the dest in I2 with our dest and make the resulting
2772 insn the new pattern for I3. Then skip to where we validate
2773 the pattern. Everything was set up above. */
2774 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2776 i3_subst_into_i2
= true;
2777 goto validate_replacement
;
2781 /* If I2 is setting a pseudo to a constant and I3 is setting some
2782 sub-part of it to another constant, merge them by making a new
2785 && (temp_expr
= single_set (i2
)) != 0
2786 && is_a
<scalar_int_mode
> (GET_MODE (SET_DEST (temp_expr
)), &temp_mode
)
2787 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2788 && GET_CODE (PATTERN (i3
)) == SET
2789 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2790 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2792 rtx dest
= SET_DEST (PATTERN (i3
));
2793 rtx temp_dest
= SET_DEST (temp_expr
);
2797 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2799 if (CONST_INT_P (XEXP (dest
, 1))
2800 && CONST_INT_P (XEXP (dest
, 2))
2801 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (dest
, 0)),
2804 width
= INTVAL (XEXP (dest
, 1));
2805 offset
= INTVAL (XEXP (dest
, 2));
2806 dest
= XEXP (dest
, 0);
2807 if (BITS_BIG_ENDIAN
)
2808 offset
= GET_MODE_PRECISION (dest_mode
) - width
- offset
;
2813 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2814 dest
= XEXP (dest
, 0);
2815 if (is_a
<scalar_int_mode
> (GET_MODE (dest
), &dest_mode
))
2817 width
= GET_MODE_PRECISION (dest_mode
);
2824 /* If this is the low part, we're done. */
2825 if (subreg_lowpart_p (dest
))
2827 /* Handle the case where inner is twice the size of outer. */
2828 else if (GET_MODE_PRECISION (temp_mode
)
2829 == 2 * GET_MODE_PRECISION (dest_mode
))
2830 offset
+= GET_MODE_PRECISION (dest_mode
);
2831 /* Otherwise give up for now. */
2838 rtx inner
= SET_SRC (PATTERN (i3
));
2839 rtx outer
= SET_SRC (temp_expr
);
2841 wide_int o
= wi::insert (rtx_mode_t (outer
, temp_mode
),
2842 rtx_mode_t (inner
, dest_mode
),
2847 subst_low_luid
= DF_INSN_LUID (i2
);
2848 added_sets_2
= added_sets_1
= added_sets_0
= false;
2850 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2852 /* Replace the source in I2 with the new constant and make the
2853 resulting insn the new pattern for I3. Then skip to where we
2854 validate the pattern. Everything was set up above. */
2855 SUBST (SET_SRC (temp_expr
),
2856 immed_wide_int_const (o
, temp_mode
));
2858 newpat
= PATTERN (i2
);
2860 /* The dest of I3 has been replaced with the dest of I2. */
2861 changed_i3_dest
= true;
2862 goto validate_replacement
;
2866 /* If we have no I1 and I2 looks like:
2867 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2869 make up a dummy I1 that is
2872 (set (reg:CC X) (compare:CC Y (const_int 0)))
2874 (We can ignore any trailing CLOBBERs.)
2876 This undoes a previous combination and allows us to match a branch-and-
2880 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2881 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2883 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2884 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2885 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2886 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
2887 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2888 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2890 /* We make I1 with the same INSN_UID as I2. This gives it
2891 the same DF_INSN_LUID for value tracking. Our fake I1 will
2892 never appear in the insn stream so giving it the same INSN_UID
2893 as I2 will not cause a problem. */
2895 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2896 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2898 INSN_UID (i1
) = INSN_UID (i2
);
2900 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2901 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2902 SET_DEST (PATTERN (i1
)));
2903 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
2904 SUBST_LINK (LOG_LINKS (i2
),
2905 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
2908 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2909 make those two SETs separate I1 and I2 insns, and make an I0 that is
2912 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2913 && can_split_parallel_of_n_reg_sets (i2
, 2)
2914 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2915 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
)
2916 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2917 && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2919 /* If there is no I1, there is no I0 either. */
2922 /* We make I1 with the same INSN_UID as I2. This gives it
2923 the same DF_INSN_LUID for value tracking. Our fake I1 will
2924 never appear in the insn stream so giving it the same INSN_UID
2925 as I2 will not cause a problem. */
2927 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2928 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
2930 INSN_UID (i1
) = INSN_UID (i2
);
2932 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
2935 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
2936 if (!can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
))
2938 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2939 fprintf (dump_file
, "Can't combine i2 into i3\n");
2943 if (i1
&& !can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
, &i1dest
, &i1src
))
2945 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2946 fprintf (dump_file
, "Can't combine i1 into i3\n");
2950 if (i0
&& !can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
, &i0dest
, &i0src
))
2952 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2953 fprintf (dump_file
, "Can't combine i0 into i3\n");
2958 /* With non-call exceptions we can end up trying to combine multiple
2959 insns with possible EH side effects. Make sure we can combine
2960 that to a single insn which means there must be at most one insn
2961 in the combination with an EH side effect. */
2962 if (cfun
->can_throw_non_call_exceptions
)
2964 if (find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
)
2965 || find_reg_note (i2
, REG_EH_REGION
, NULL_RTX
)
2966 || (i1
&& find_reg_note (i1
, REG_EH_REGION
, NULL_RTX
))
2967 || (i0
&& find_reg_note (i0
, REG_EH_REGION
, NULL_RTX
)))
2969 has_non_call_exception
= true;
2970 if (insn_could_throw_p (i3
)
2971 + insn_could_throw_p (i2
)
2972 + (i1
? insn_could_throw_p (i1
) : 0)
2973 + (i0
? insn_could_throw_p (i0
) : 0) > 1)
2975 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2976 fprintf (dump_file
, "Can't combine multiple insns with EH "
2984 /* Record whether i2 and i3 are trivial moves. */
2985 i2_was_move
= is_just_move (i2
);
2986 i3_was_move
= is_just_move (i3
);
2988 /* Record whether I2DEST is used in I2SRC and similarly for the other
2989 cases. Knowing this will help in register status updating below. */
2990 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2991 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2992 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2993 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2994 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2995 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2996 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2997 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2998 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
3000 /* For the earlier insns, determine which of the subsequent ones they
3002 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
3003 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
3004 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
3005 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
3006 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3008 /* Ensure that I3's pattern can be the destination of combines. */
3009 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3010 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3011 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3012 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3019 /* See if any of the insns is a MULT operation. Unless one is, we will
3020 reject a combination that is, since it must be slower. Be conservative
3022 if (GET_CODE (i2src
) == MULT
3023 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3024 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3025 || (GET_CODE (PATTERN (i3
)) == SET
3026 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3029 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3030 We used to do this EXCEPT in one case: I3 has a post-inc in an
3031 output operand. However, that exception can give rise to insns like
3033 which is a famous insn on the PDP-11 where the value of r3 used as the
3034 source was model-dependent. Avoid this sort of thing. */
3037 if (!(GET_CODE (PATTERN (i3
)) == SET
3038 && REG_P (SET_SRC (PATTERN (i3
)))
3039 && MEM_P (SET_DEST (PATTERN (i3
)))
3040 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3041 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3042 /* It's not the exception. */
3047 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3048 if (REG_NOTE_KIND (link
) == REG_INC
3049 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3051 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3058 /* See if the SETs in I1 or I2 need to be kept around in the merged
3059 instruction: whenever the value set there is still needed past I3.
3060 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3062 For the SET in I1, we have two cases: if I1 and I2 independently feed
3063 into I3, the set in I1 needs to be kept around unless I1DEST dies
3064 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3065 in I1 needs to be kept around unless I1DEST dies or is set in either
3066 I2 or I3. The same considerations apply to I0. */
3068 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3071 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3072 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3074 added_sets_1
= false;
3077 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3078 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3079 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3080 && dead_or_set_p (i2
, i0dest
)));
3082 added_sets_0
= false;
3084 /* We are about to copy insns for the case where they need to be kept
3085 around. Check that they can be copied in the merged instruction. */
3087 if (targetm
.cannot_copy_insn_p
3088 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3089 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3090 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3096 /* We cannot safely duplicate volatile references in any case. */
3098 if ((added_sets_2
&& volatile_refs_p (PATTERN (i2
)))
3099 || (added_sets_1
&& volatile_refs_p (PATTERN (i1
)))
3100 || (added_sets_0
&& volatile_refs_p (PATTERN (i0
))))
3106 /* Count how many auto_inc expressions there were in the original insns;
3107 we need to have the same number in the resulting patterns. */
3110 for_each_inc_dec (PATTERN (i0
), count_auto_inc
, &n_auto_inc
);
3112 for_each_inc_dec (PATTERN (i1
), count_auto_inc
, &n_auto_inc
);
3113 for_each_inc_dec (PATTERN (i2
), count_auto_inc
, &n_auto_inc
);
3114 for_each_inc_dec (PATTERN (i3
), count_auto_inc
, &n_auto_inc
);
3116 /* If the set in I2 needs to be kept around, we must make a copy of
3117 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3118 PATTERN (I2), we are only substituting for the original I1DEST, not into
3119 an already-substituted copy. This also prevents making self-referential
3120 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3125 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3126 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3128 i2pat
= copy_rtx (PATTERN (i2
));
3133 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3134 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3136 i1pat
= copy_rtx (PATTERN (i1
));
3141 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3142 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3144 i0pat
= copy_rtx (PATTERN (i0
));
3149 /* Substitute in the latest insn for the regs set by the earlier ones. */
3151 maxreg
= max_reg_num ();
3155 /* Many machines have insns that can both perform an
3156 arithmetic operation and set the condition code. These operations will
3157 be represented as a PARALLEL with the first element of the vector
3158 being a COMPARE of an arithmetic operation with the constant zero.
3159 The second element of the vector will set some pseudo to the result
3160 of the same arithmetic operation. If we simplify the COMPARE, we won't
3161 match such a pattern and so will generate an extra insn. Here we test
3162 for this case, where both the comparison and the operation result are
3163 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3164 I2SRC. Later we will make the PARALLEL that contains I2. */
3166 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3167 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3168 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3169 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3172 rtx
*cc_use_loc
= NULL
;
3173 rtx_insn
*cc_use_insn
= NULL
;
3174 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3175 machine_mode compare_mode
, orig_compare_mode
;
3176 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3177 scalar_int_mode mode
;
3179 newpat
= PATTERN (i3
);
3180 newpat_dest
= SET_DEST (newpat
);
3181 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3183 if (undobuf
.other_insn
== 0
3184 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3187 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3188 if (is_a
<scalar_int_mode
> (GET_MODE (i2dest
), &mode
))
3189 compare_code
= simplify_compare_const (compare_code
, mode
,
3191 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3194 /* Do the rest only if op1 is const0_rtx, which may be the
3195 result of simplification. */
3196 if (op1
== const0_rtx
)
3198 /* If a single use of the CC is found, prepare to modify it
3199 when SELECT_CC_MODE returns a new CC-class mode, or when
3200 the above simplify_compare_const() returned a new comparison
3201 operator. undobuf.other_insn is assigned the CC use insn
3202 when modifying it. */
3205 #ifdef SELECT_CC_MODE
3206 machine_mode new_mode
3207 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3208 if (new_mode
!= orig_compare_mode
3209 && can_change_dest_mode (SET_DEST (newpat
),
3210 added_sets_2
, new_mode
))
3212 unsigned int regno
= REGNO (newpat_dest
);
3213 compare_mode
= new_mode
;
3214 if (regno
< FIRST_PSEUDO_REGISTER
)
3215 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3218 subst_mode (regno
, compare_mode
);
3219 newpat_dest
= regno_reg_rtx
[regno
];
3223 /* Cases for modifying the CC-using comparison. */
3224 if (compare_code
!= orig_compare_code
3225 && COMPARISON_P (*cc_use_loc
))
3227 /* Replace cc_use_loc with entire new RTX. */
3229 gen_rtx_fmt_ee (compare_code
, GET_MODE (*cc_use_loc
),
3230 newpat_dest
, const0_rtx
));
3231 undobuf
.other_insn
= cc_use_insn
;
3233 else if (compare_mode
!= orig_compare_mode
)
3235 subrtx_ptr_iterator::array_type array
;
3237 /* Just replace the CC reg with a new mode. */
3238 FOR_EACH_SUBRTX_PTR (iter
, array
, cc_use_loc
, NONCONST
)
3242 && REGNO (*loc
) == REGNO (newpat_dest
))
3244 SUBST (*loc
, newpat_dest
);
3245 iter
.skip_subrtxes ();
3248 undobuf
.other_insn
= cc_use_insn
;
3252 /* Now we modify the current newpat:
3253 First, SET_DEST(newpat) is updated if the CC mode has been
3254 altered. For targets without SELECT_CC_MODE, this should be
3256 if (compare_mode
!= orig_compare_mode
)
3257 SUBST (SET_DEST (newpat
), newpat_dest
);
3258 /* This is always done to propagate i2src into newpat. */
3259 SUBST (SET_SRC (newpat
),
3260 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3261 /* Create new version of i2pat if needed; the below PARALLEL
3262 creation needs this to work correctly. */
3263 if (! rtx_equal_p (i2src
, op0
))
3264 i2pat
= gen_rtx_SET (i2dest
, op0
);
3269 if (i2_is_used
== 0)
3271 /* It is possible that the source of I2 or I1 may be performing
3272 an unneeded operation, such as a ZERO_EXTEND of something
3273 that is known to have the high part zero. Handle that case
3274 by letting subst look at the inner insns.
3276 Another way to do this would be to have a function that tries
3277 to simplify a single insn instead of merging two or more
3278 insns. We don't do this because of the potential of infinite
3279 loops and because of the potential extra memory required.
3280 However, doing it the way we are is a bit of a kludge and
3281 doesn't catch all cases.
3283 But only do this if -fexpensive-optimizations since it slows
3284 things down and doesn't usually win.
3286 This is not done in the COMPARE case above because the
3287 unmodified I2PAT is used in the PARALLEL and so a pattern
3288 with a modified I2SRC would not match. */
3290 if (flag_expensive_optimizations
)
3292 /* Pass pc_rtx so no substitutions are done, just
3296 subst_low_luid
= DF_INSN_LUID (i1
);
3297 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, false, false, false);
3300 subst_low_luid
= DF_INSN_LUID (i2
);
3301 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, false, false, false);
3304 n_occurrences
= 0; /* `subst' counts here */
3305 subst_low_luid
= DF_INSN_LUID (i2
);
3307 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3308 copy of I2SRC each time we substitute it, in order to avoid creating
3309 self-referential RTL when we will be substituting I1SRC for I1DEST
3310 later. Likewise if I0 feeds into I2, either directly or indirectly
3311 through I1, and I0DEST is in I0SRC. */
3312 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, false, false,
3313 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3314 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3315 && i0dest_in_i0src
));
3318 /* Record whether I2's body now appears within I3's body. */
3319 i2_is_used
= n_occurrences
;
3322 /* If we already got a failure, don't try to do more. Otherwise, try to
3323 substitute I1 if we have it. */
3325 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3327 /* Before we can do this substitution, we must redo the test done
3328 above (see detailed comments there) that ensures I1DEST isn't
3329 mentioned in any SETs in NEWPAT that are field assignments. */
3330 if (!combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3338 subst_low_luid
= DF_INSN_LUID (i1
);
3340 /* If the following substitution will modify I1SRC, make a copy of it
3341 for the case where it is substituted for I1DEST in I2PAT later. */
3342 if (added_sets_2
&& i1_feeds_i2_n
)
3343 i1src_copy
= copy_rtx (i1src
);
3345 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3346 copy of I1SRC each time we substitute it, in order to avoid creating
3347 self-referential RTL when we will be substituting I0SRC for I0DEST
3349 newpat
= subst (newpat
, i1dest
, i1src
, false, false,
3350 i0_feeds_i1_n
&& i0dest_in_i0src
);
3353 /* Record whether I1's body now appears within I3's body. */
3354 i1_is_used
= n_occurrences
;
3357 /* Likewise for I0 if we have it. */
3359 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3361 if (!combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3368 /* If the following substitution will modify I0SRC, make a copy of it
3369 for the case where it is substituted for I0DEST in I1PAT later. */
3370 if (added_sets_1
&& i0_feeds_i1_n
)
3371 i0src_copy
= copy_rtx (i0src
);
3372 /* And a copy for I0DEST in I2PAT substitution. */
3373 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3374 || (i0_feeds_i2_n
)))
3375 i0src_copy2
= copy_rtx (i0src
);
3378 subst_low_luid
= DF_INSN_LUID (i0
);
3379 newpat
= subst (newpat
, i0dest
, i0src
, false, false, false);
3385 int new_n_auto_inc
= 0;
3386 for_each_inc_dec (newpat
, count_auto_inc
, &new_n_auto_inc
);
3388 if (n_auto_inc
!= new_n_auto_inc
)
3390 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
3391 fprintf (dump_file
, "Number of auto_inc expressions changed\n");
3397 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3398 to count all the ways that I2SRC and I1SRC can be used. */
3399 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3400 && i2_is_used
+ added_sets_2
> 1)
3401 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3402 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
) > 1))
3403 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3404 && (n_occurrences
+ added_sets_0
3405 + (added_sets_1
&& i0_feeds_i1_n
)
3406 + (added_sets_2
&& i0_feeds_i2_n
) > 1))
3407 /* Fail if we tried to make a new register. */
3408 || max_reg_num () != maxreg
3409 /* Fail if we couldn't do something and have a CLOBBER. */
3410 || GET_CODE (newpat
) == CLOBBER
3411 /* Fail if this new pattern is a MULT and we didn't have one before
3412 at the outer level. */
3413 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3420 /* If the actions of the earlier insns must be kept
3421 in addition to substituting them into the latest one,
3422 we must make a new PARALLEL for the latest insn
3423 to hold additional the SETs. */
3425 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3427 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3430 if (GET_CODE (newpat
) == PARALLEL
)
3432 rtvec old
= XVEC (newpat
, 0);
3433 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3434 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3435 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3436 sizeof (old
->elem
[0]) * old
->num_elem
);
3441 total_sets
= 1 + extra_sets
;
3442 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3443 XVECEXP (newpat
, 0, 0) = old
;
3447 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3453 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
,
3454 false, false, false);
3456 XVECEXP (newpat
, 0, --total_sets
) = t
;
3462 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, false, false,
3463 i0_feeds_i1_n
&& i0dest_in_i0src
);
3464 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3465 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
,
3466 false, false, false);
3468 XVECEXP (newpat
, 0, --total_sets
) = t
;
3472 validate_replacement
:
3474 /* Note which hard regs this insn has as inputs. */
3475 mark_used_regs_combine (newpat
);
3477 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3478 consider splitting this pattern, we might need these clobbers. */
3479 if (i1
&& GET_CODE (newpat
) == PARALLEL
3480 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3482 int len
= XVECLEN (newpat
, 0);
3484 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3485 for (i
= 0; i
< len
; i
++)
3486 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3489 /* We have recognized nothing yet. */
3490 insn_code_number
= -1;
3492 /* See if this is a PARALLEL of two SETs where one SET's destination is
3493 a register that is unused and this isn't marked as an instruction that
3494 might trap in an EH region. In that case, we just need the other SET.
3495 We prefer this over the PARALLEL.
3497 This can occur when simplifying a divmod insn. We *must* test for this
3498 case here because the code below that splits two independent SETs doesn't
3499 handle this case correctly when it updates the register status.
3501 It's pointless doing this if we originally had two sets, one from
3502 i3, and one from i2. Combining then splitting the parallel results
3503 in the original i2 again plus an invalid insn (which we delete).
3504 The net effect is only to move instructions around, which makes
3505 debug info less accurate.
3507 If the remaining SET came from I2 its destination should not be used
3508 between I2 and I3. See PR82024. */
3510 if (!(added_sets_2
&& i1
== 0)
3511 && is_parallel_of_n_reg_sets (newpat
, 2)
3512 && asm_noperands (newpat
) < 0)
3514 rtx set0
= XVECEXP (newpat
, 0, 0);
3515 rtx set1
= XVECEXP (newpat
, 0, 1);
3516 rtx oldpat
= newpat
;
3518 if (((REG_P (SET_DEST (set1
))
3519 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3520 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3521 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3522 && insn_nothrow_p (i3
)
3523 && !side_effects_p (SET_SRC (set1
)))
3526 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3529 else if (((REG_P (SET_DEST (set0
))
3530 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3531 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3532 && find_reg_note (i3
, REG_UNUSED
,
3533 SUBREG_REG (SET_DEST (set0
)))))
3534 && insn_nothrow_p (i3
)
3535 && !side_effects_p (SET_SRC (set0
)))
3537 rtx dest
= SET_DEST (set1
);
3538 if (GET_CODE (dest
) == SUBREG
)
3539 dest
= SUBREG_REG (dest
);
3540 if (!reg_used_between_p (dest
, i2
, i3
))
3543 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3545 if (insn_code_number
>= 0)
3546 changed_i3_dest
= true;
3550 if (insn_code_number
< 0)
3554 /* Is the result of combination a valid instruction? */
3555 if (insn_code_number
< 0)
3556 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3558 /* If we were combining three insns and the result is a simple SET
3559 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3560 insns. There are two ways to do this. It can be split using a
3561 machine-specific method (like when you have an addition of a large
3562 constant) or by combine in the function find_split_point. */
3564 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3565 && asm_noperands (newpat
) < 0)
3567 rtx parallel
, *split
;
3568 rtx_insn
*m_split_insn
;
3570 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3571 use I2DEST as a scratch register will help. In the latter case,
3572 convert I2DEST to the mode of the source of NEWPAT if we can. */
3574 m_split_insn
= combine_split_insns (newpat
, i3
);
3576 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3577 inputs of NEWPAT. */
3579 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3580 possible to try that as a scratch reg. This would require adding
3581 more code to make it work though. */
3583 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3585 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3587 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3588 (temporarily, until we are committed to this instruction
3589 combination) does not work: for example, any call to nonzero_bits
3590 on the register (from a splitter in the MD file, for example)
3591 will get the old information, which is invalid.
3593 Since nowadays we can create registers during combine just fine,
3594 we should just create a new one here, not reuse i2dest. */
3596 /* First try to split using the original register as a
3597 scratch register. */
3598 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3599 gen_rtvec (2, newpat
,
3600 gen_rtx_CLOBBER (VOIDmode
,
3602 m_split_insn
= combine_split_insns (parallel
, i3
);
3604 /* If that didn't work, try changing the mode of I2DEST if
3606 if (m_split_insn
== 0
3607 && new_mode
!= GET_MODE (i2dest
)
3608 && new_mode
!= VOIDmode
3609 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3611 machine_mode old_mode
= GET_MODE (i2dest
);
3614 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3615 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3618 subst_mode (REGNO (i2dest
), new_mode
);
3619 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3622 parallel
= (gen_rtx_PARALLEL
3624 gen_rtvec (2, newpat
,
3625 gen_rtx_CLOBBER (VOIDmode
,
3627 m_split_insn
= combine_split_insns (parallel
, i3
);
3629 if (m_split_insn
== 0
3630 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3634 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3635 buf
= undobuf
.undos
;
3636 undobuf
.undos
= buf
->next
;
3637 buf
->next
= undobuf
.frees
;
3638 undobuf
.frees
= buf
;
3642 i2scratch
= m_split_insn
!= 0;
3645 /* If recog_for_combine has discarded clobbers, try to use them
3646 again for the split. */
3647 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3649 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3650 m_split_insn
= combine_split_insns (parallel
, i3
);
3653 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3655 rtx m_split_pat
= PATTERN (m_split_insn
);
3656 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3657 if (insn_code_number
>= 0)
3658 newpat
= m_split_pat
;
3660 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3661 && (next_nonnote_nondebug_insn (i2
) == i3
3662 || !modified_between_p (PATTERN (m_split_insn
), i2
, i3
)))
3665 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3666 newi2pat
= PATTERN (m_split_insn
);
3668 i3set
= single_set (NEXT_INSN (m_split_insn
));
3669 i2set
= single_set (m_split_insn
);
3671 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3673 /* If I2 or I3 has multiple SETs, we won't know how to track
3674 register status, so don't use these insns. If I2's destination
3675 is used between I2 and I3, we also can't use these insns. */
3677 if (i2_code_number
>= 0 && i2set
&& i3set
3678 && (next_nonnote_nondebug_insn (i2
) == i3
3679 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3680 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3682 if (insn_code_number
>= 0)
3685 /* It is possible that both insns now set the destination of I3.
3686 If so, we must show an extra use of it. */
3688 if (insn_code_number
>= 0)
3690 rtx new_i3_dest
= SET_DEST (i3set
);
3691 rtx new_i2_dest
= SET_DEST (i2set
);
3693 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3694 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3695 || GET_CODE (new_i3_dest
) == SUBREG
)
3696 new_i3_dest
= XEXP (new_i3_dest
, 0);
3698 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3699 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3700 || GET_CODE (new_i2_dest
) == SUBREG
)
3701 new_i2_dest
= XEXP (new_i2_dest
, 0);
3703 if (REG_P (new_i3_dest
)
3704 && REG_P (new_i2_dest
)
3705 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3706 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3707 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3711 /* If we can split it and use I2DEST, go ahead and see if that
3712 helps things be recognized. Verify that none of the registers
3713 are set between I2 and I3. */
3714 if (insn_code_number
< 0
3715 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3716 /* We need I2DEST in the proper mode. If it is a hard register
3717 or the only use of a pseudo, we can change its mode.
3718 Make sure we don't change a hard register to have a mode that
3719 isn't valid for it, or change the number of registers. */
3720 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3721 || GET_MODE (*split
) == VOIDmode
3722 || can_change_dest_mode (i2dest
, added_sets_2
,
3724 && (next_nonnote_nondebug_insn (i2
) == i3
3725 || !modified_between_p (*split
, i2
, i3
))
3726 /* We can't overwrite I2DEST if its value is still used by
3728 && ! reg_referenced_p (i2dest
, newpat
)
3729 /* We should not split a possibly trapping part when we
3730 care about non-call EH and have REG_EH_REGION notes
3732 && ! (cfun
->can_throw_non_call_exceptions
3733 && has_non_call_exception
3734 && may_trap_p (*split
)))
3736 rtx newdest
= i2dest
;
3737 enum rtx_code split_code
= GET_CODE (*split
);
3738 machine_mode split_mode
= GET_MODE (*split
);
3739 bool subst_done
= false;
3740 newi2pat
= NULL_RTX
;
3744 /* *SPLIT may be part of I2SRC, so make sure we have the
3745 original expression around for later debug processing.
3746 We should not need I2SRC any more in other cases. */
3747 if (MAY_HAVE_DEBUG_BIND_INSNS
)
3748 i2src
= copy_rtx (i2src
);
3752 /* Get NEWDEST as a register in the proper mode. We have already
3753 validated that we can do this. */
3754 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3756 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3757 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3760 subst_mode (REGNO (i2dest
), split_mode
);
3761 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3765 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3766 an ASHIFT. This can occur if it was inside a PLUS and hence
3767 appeared to be a memory address. This is a kludge. */
3768 if (split_code
== MULT
3769 && CONST_INT_P (XEXP (*split
, 1))
3770 && INTVAL (XEXP (*split
, 1)) > 0
3771 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3773 rtx i_rtx
= gen_int_shift_amount (split_mode
, i
);
3774 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3775 XEXP (*split
, 0), i_rtx
));
3776 /* Update split_code because we may not have a multiply
3778 split_code
= GET_CODE (*split
);
3781 /* Similarly for (plus (mult FOO (const_int pow2))). */
3782 if (split_code
== PLUS
3783 && GET_CODE (XEXP (*split
, 0)) == MULT
3784 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3785 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3786 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3788 rtx nsplit
= XEXP (*split
, 0);
3789 rtx i_rtx
= gen_int_shift_amount (GET_MODE (nsplit
), i
);
3790 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3793 /* Update split_code because we may not have a multiply
3795 split_code
= GET_CODE (*split
);
3798 #ifdef INSN_SCHEDULING
3799 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3800 be written as a ZERO_EXTEND. */
3801 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3803 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3804 what it really is. */
3805 if (load_extend_op (GET_MODE (SUBREG_REG (*split
)))
3807 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3808 SUBREG_REG (*split
)));
3810 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3811 SUBREG_REG (*split
)));
3815 /* Attempt to split binary operators using arithmetic identities. */
3816 if (BINARY_P (SET_SRC (newpat
))
3817 && split_mode
== GET_MODE (SET_SRC (newpat
))
3818 && ! side_effects_p (SET_SRC (newpat
)))
3820 rtx setsrc
= SET_SRC (newpat
);
3821 machine_mode mode
= GET_MODE (setsrc
);
3822 enum rtx_code code
= GET_CODE (setsrc
);
3823 rtx src_op0
= XEXP (setsrc
, 0);
3824 rtx src_op1
= XEXP (setsrc
, 1);
3826 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3827 if (rtx_equal_p (src_op0
, src_op1
))
3829 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3830 SUBST (XEXP (setsrc
, 0), newdest
);
3831 SUBST (XEXP (setsrc
, 1), newdest
);
3834 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3835 else if ((code
== PLUS
|| code
== MULT
)
3836 && GET_CODE (src_op0
) == code
3837 && GET_CODE (XEXP (src_op0
, 0)) == code
3838 && (INTEGRAL_MODE_P (mode
)
3839 || (FLOAT_MODE_P (mode
)
3840 && flag_unsafe_math_optimizations
)))
3842 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3843 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3844 rtx r
= XEXP (src_op0
, 1);
3847 /* Split both "((X op Y) op X) op Y" and
3848 "((X op Y) op Y) op X" as "T op T" where T is
3850 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3851 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3853 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3854 SUBST (XEXP (setsrc
, 0), newdest
);
3855 SUBST (XEXP (setsrc
, 1), newdest
);
3858 /* Split "((X op X) op Y) op Y)" as "T op T" where
3860 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3862 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3863 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3864 SUBST (XEXP (setsrc
, 0), newdest
);
3865 SUBST (XEXP (setsrc
, 1), newdest
);
3873 newi2pat
= gen_rtx_SET (newdest
, *split
);
3874 SUBST (*split
, newdest
);
3877 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3879 /* recog_for_combine might have added CLOBBERs to newi2pat.
3880 Make sure NEWPAT does not depend on the clobbered regs. */
3881 if (GET_CODE (newi2pat
) == PARALLEL
)
3882 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3883 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3885 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3886 if (reg_overlap_mentioned_p (reg
, newpat
))
3893 /* If the split point was a MULT and we didn't have one before,
3894 don't use one now. */
3895 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3896 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3900 /* Check for a case where we loaded from memory in a narrow mode and
3901 then sign extended it, but we need both registers. In that case,
3902 we have a PARALLEL with both loads from the same memory location.
3903 We can split this into a load from memory followed by a register-register
3904 copy. This saves at least one insn, more if register allocation can
3907 We cannot do this if the destination of the first assignment is a
3908 condition code register. We eliminate this case by making sure
3909 the SET_DEST and SET_SRC have the same mode.
3911 We cannot do this if the destination of the second assignment is
3912 a register that we have already assumed is zero-extended. Similarly
3913 for a SUBREG of such a register. */
3915 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3916 && GET_CODE (newpat
) == PARALLEL
3917 && XVECLEN (newpat
, 0) == 2
3918 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3919 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3920 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3921 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3922 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3923 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3924 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3925 && !modified_between_p (SET_SRC (XVECEXP (newpat
, 0, 1)), i2
, i3
)
3926 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3927 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3928 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3930 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3931 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
3933 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
3935 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3936 != GET_MODE_MASK (word_mode
))))
3937 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3938 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3940 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3941 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
3943 && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr
)),
3945 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3946 != GET_MODE_MASK (word_mode
)))))
3947 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3948 SET_SRC (XVECEXP (newpat
, 0, 1)))
3949 && ! find_reg_note (i3
, REG_UNUSED
,
3950 SET_DEST (XVECEXP (newpat
, 0, 0))))
3954 newi2pat
= XVECEXP (newpat
, 0, 0);
3955 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3956 newpat
= XVECEXP (newpat
, 0, 1);
3957 SUBST (SET_SRC (newpat
),
3958 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3959 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3961 if (i2_code_number
>= 0)
3962 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3964 if (insn_code_number
>= 0)
3968 /* Similarly, check for a case where we have a PARALLEL of two independent
3969 SETs but we started with three insns. In this case, we can do the sets
3970 as two separate insns. This case occurs when some SET allows two
3971 other insns to combine, but the destination of that SET is still live.
3973 Also do this if we started with two insns and (at least) one of the
3974 resulting sets is a noop; this noop will be deleted later.
3976 Also do this if we started with two insns neither of which was a simple
3979 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
3980 && GET_CODE (newpat
) == PARALLEL
3981 && XVECLEN (newpat
, 0) == 2
3982 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3983 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3985 || set_noop_p (XVECEXP (newpat
, 0, 0))
3986 || set_noop_p (XVECEXP (newpat
, 0, 1))
3987 || (!i2_was_move
&& !i3_was_move
))
3988 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3989 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3990 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3991 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3992 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3993 XVECEXP (newpat
, 0, 0))
3994 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3995 XVECEXP (newpat
, 0, 1))
3996 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3997 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3999 rtx set0
= XVECEXP (newpat
, 0, 0);
4000 rtx set1
= XVECEXP (newpat
, 0, 1);
4002 /* Normally, it doesn't matter which of the two is done first, but
4003 one which uses any regs/memory set in between i2 and i3 can't
4004 be first. The PARALLEL might also have been pre-existing in i3,
4005 so we need to make sure that we won't wrongly hoist a SET to i2
4006 that would conflict with a death note present in there, or would
4007 have its dest modified between i2 and i3. */
4008 if (!modified_between_p (SET_SRC (set1
), i2
, i3
)
4009 && !(REG_P (SET_DEST (set1
))
4010 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
4011 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
4012 && find_reg_note (i2
, REG_DEAD
,
4013 SUBREG_REG (SET_DEST (set1
))))
4014 && !modified_between_p (SET_DEST (set1
), i2
, i3
)
4015 /* If I3 is a jump, ensure that set0 is a jump so that
4016 we do not create invalid RTL. */
4017 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
4023 else if (!modified_between_p (SET_SRC (set0
), i2
, i3
)
4024 && !(REG_P (SET_DEST (set0
))
4025 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
4026 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
4027 && find_reg_note (i2
, REG_DEAD
,
4028 SUBREG_REG (SET_DEST (set0
))))
4029 && !modified_between_p (SET_DEST (set0
), i2
, i3
)
4030 /* If I3 is a jump, ensure that set1 is a jump so that
4031 we do not create invalid RTL. */
4032 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
4044 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
4046 if (i2_code_number
>= 0)
4048 /* recog_for_combine might have added CLOBBERs to newi2pat.
4049 Make sure NEWPAT does not depend on the clobbered regs. */
4050 if (GET_CODE (newi2pat
) == PARALLEL
)
4052 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
4053 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
4055 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
4056 if (reg_overlap_mentioned_p (reg
, newpat
))
4064 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
4066 /* Likewise, recog_for_combine might have added clobbers to NEWPAT.
4067 Checking that the SET0's SET_DEST and SET1's SET_DEST aren't
4068 mentioned/clobbered, ensures NEWI2PAT's SET_DEST is live. */
4069 if (insn_code_number
>= 0 && GET_CODE (newpat
) == PARALLEL
)
4071 for (i
= XVECLEN (newpat
, 0) - 1; i
>= 0; i
--)
4072 if (GET_CODE (XVECEXP (newpat
, 0, i
)) == CLOBBER
)
4074 rtx reg
= XEXP (XVECEXP (newpat
, 0, i
), 0);
4075 if (reg_overlap_mentioned_p (reg
, SET_DEST (set0
))
4076 || reg_overlap_mentioned_p (reg
, SET_DEST (set1
)))
4084 if (insn_code_number
>= 0)
4089 /* If it still isn't recognized, fail and change things back the way they
4091 if ((insn_code_number
< 0
4092 /* Is the result a reasonable ASM_OPERANDS? */
4093 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4099 /* If we had to change another insn, make sure it is valid also. */
4100 if (undobuf
.other_insn
)
4102 CLEAR_HARD_REG_SET (newpat_used_regs
);
4104 other_pat
= PATTERN (undobuf
.other_insn
);
4105 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4108 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4115 /* Only allow this combination if insn_cost reports that the
4116 replacement instructions are cheaper than the originals. */
4117 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4123 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4127 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4128 if (undo
->kind
== UNDO_MODE
)
4130 rtx reg
= regno_reg_rtx
[undo
->where
.regno
];
4131 machine_mode new_mode
= GET_MODE (reg
);
4132 machine_mode old_mode
= undo
->old_contents
.m
;
4134 /* Temporarily revert mode back. */
4135 adjust_reg_mode (reg
, old_mode
);
4137 if (reg
== i2dest
&& i2scratch
)
4139 /* If we used i2dest as a scratch register with a
4140 different mode, substitute it for the original
4141 i2src while its original mode is temporarily
4142 restored, and then clear i2scratch so that we don't
4143 do it again later. */
4144 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4147 /* Put back the new mode. */
4148 adjust_reg_mode (reg
, new_mode
);
4152 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4153 rtx_insn
*first
, *last
;
4158 last
= last_combined_insn
;
4163 last
= undobuf
.other_insn
;
4165 if (DF_INSN_LUID (last
)
4166 < DF_INSN_LUID (last_combined_insn
))
4167 last
= last_combined_insn
;
4170 /* We're dealing with a reg that changed mode but not
4171 meaning, so we want to turn it into a subreg for
4172 the new mode. However, because of REG sharing and
4173 because its mode had already changed, we have to do
4174 it in two steps. First, replace any debug uses of
4175 reg, with its original mode temporarily restored,
4176 with this copy we have created; then, replace the
4177 copy with the SUBREG of the original shared reg,
4178 once again changed to the new mode. */
4179 propagate_for_debug (first
, last
, reg
, tempreg
,
4181 adjust_reg_mode (reg
, new_mode
);
4182 propagate_for_debug (first
, last
, tempreg
,
4183 lowpart_subreg (old_mode
, reg
, new_mode
),
4189 /* If we will be able to accept this, we have made a
4190 change to the destination of I3. This requires us to
4191 do a few adjustments. */
4193 if (changed_i3_dest
)
4195 PATTERN (i3
) = newpat
;
4196 adjust_for_new_dest (i3
);
4199 /* If I2 didn't change, this is not a combination (but a simplification or
4200 canonicalisation with context), which should not be done here. Doing
4201 it here explodes the algorithm. Don't. */
4202 if (rtx_equal_p (newi2pat
, PATTERN (i2
)))
4205 fprintf (dump_file
, "i2 didn't change, not doing this\n");
4210 /* We now know that we can do this combination. Merge the insns and
4211 update the status of registers and LOG_LINKS. */
4213 if (undobuf
.other_insn
)
4217 PATTERN (undobuf
.other_insn
) = other_pat
;
4219 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4220 ensure that they are still valid. Then add any non-duplicate
4221 notes added by recog_for_combine. */
4222 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4224 next
= XEXP (note
, 1);
4226 if ((REG_NOTE_KIND (note
) == REG_DEAD
4227 && !reg_referenced_p (XEXP (note
, 0),
4228 PATTERN (undobuf
.other_insn
)))
4229 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4230 && !reg_set_p (XEXP (note
, 0),
4231 PATTERN (undobuf
.other_insn
)))
4232 /* Simply drop equal note since it may be no longer valid
4233 for other_insn. It may be possible to record that CC
4234 register is changed and only discard those notes, but
4235 in practice it's unnecessary complication and doesn't
4236 give any meaningful improvement.
4239 || REG_NOTE_KIND (note
) == REG_EQUAL
4240 || REG_NOTE_KIND (note
) == REG_EQUIV
)
4241 remove_note (undobuf
.other_insn
, note
);
4244 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4245 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4251 /* I3 now uses what used to be its destination and which is now
4252 I2's destination. This requires us to do a few adjustments. */
4253 PATTERN (i3
) = newpat
;
4254 adjust_for_new_dest (i3
);
4257 if (swap_i2i3
|| split_i2i3
)
4259 /* We might need a LOG_LINK from I3 to I2. But then we used to
4260 have one, so we still will.
4262 However, some later insn might be using I2's dest and have
4263 a LOG_LINK pointing at I3. We should change it to point at
4266 /* newi2pat is usually a SET here; however, recog_for_combine might
4267 have added some clobbers. */
4269 if (GET_CODE (x
) == PARALLEL
)
4270 x
= XVECEXP (newi2pat
, 0, 0);
4272 if (REG_P (SET_DEST (x
))
4273 || (GET_CODE (SET_DEST (x
)) == SUBREG
4274 && REG_P (SUBREG_REG (SET_DEST (x
)))))
4276 unsigned int regno
= reg_or_subregno (SET_DEST (x
));
4279 for (rtx_insn
*insn
= NEXT_INSN (i3
);
4283 && BLOCK_FOR_INSN (insn
) == this_basic_block
;
4284 insn
= NEXT_INSN (insn
))
4286 if (DEBUG_INSN_P (insn
))
4288 struct insn_link
*link
;
4289 FOR_EACH_LOG_LINK (link
, insn
)
4290 if (link
->insn
== i3
&& link
->regno
== regno
)
4301 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4302 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4305 /* Compute which registers we expect to eliminate. newi2pat may be setting
4306 either i3dest or i2dest, so we must check it. */
4307 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4308 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4311 /* For i1, we need to compute both local elimination and global
4312 elimination information with respect to newi2pat because i1dest
4313 may be the same as i3dest, in which case newi2pat may be setting
4314 i1dest. Global information is used when distributing REG_DEAD
4315 note for i2 and i3, in which case it does matter if newi2pat sets
4318 Local information is used when distributing REG_DEAD note for i1,
4319 in which case it doesn't matter if newi2pat sets i1dest or not.
4320 See PR62151, if we have four insns combination:
4322 i1: r1 <- i1src (using r0)
4324 i2: r0 <- i2src (using r1)
4325 i3: r3 <- i3src (using r0)
4327 From i1's point of view, r0 is eliminated, no matter if it is set
4328 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4329 should be discarded.
4331 Note local information only affects cases in forms like "I1->I2->I3",
4332 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4333 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4335 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4338 rtx elim_i1
= (local_elim_i1
== 0
4339 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4341 /* Same case as i1. */
4342 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4344 rtx elim_i0
= (local_elim_i0
== 0
4345 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4348 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4350 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4351 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4353 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4355 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4357 /* Ensure that we do not have something that should not be shared but
4358 occurs multiple times in the new insns. Check this by first
4359 resetting all the `used' flags and then copying anything is shared. */
4361 reset_used_flags (i3notes
);
4362 reset_used_flags (i2notes
);
4363 reset_used_flags (i1notes
);
4364 reset_used_flags (i0notes
);
4365 reset_used_flags (newpat
);
4366 reset_used_flags (newi2pat
);
4367 if (undobuf
.other_insn
)
4368 reset_used_flags (PATTERN (undobuf
.other_insn
));
4370 i3notes
= copy_rtx_if_shared (i3notes
);
4371 i2notes
= copy_rtx_if_shared (i2notes
);
4372 i1notes
= copy_rtx_if_shared (i1notes
);
4373 i0notes
= copy_rtx_if_shared (i0notes
);
4374 newpat
= copy_rtx_if_shared (newpat
);
4375 newi2pat
= copy_rtx_if_shared (newi2pat
);
4376 if (undobuf
.other_insn
)
4377 reset_used_flags (PATTERN (undobuf
.other_insn
));
4379 INSN_CODE (i3
) = insn_code_number
;
4380 PATTERN (i3
) = newpat
;
4382 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4384 for (rtx link
= CALL_INSN_FUNCTION_USAGE (i3
); link
;
4385 link
= XEXP (link
, 1))
4389 /* I2SRC must still be meaningful at this point. Some
4390 splitting operations can invalidate I2SRC, but those
4391 operations do not apply to calls. */
4393 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4397 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4400 XEXP (link
, 0) = simplify_replace_rtx (XEXP (link
, 0),
4405 if (undobuf
.other_insn
)
4406 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4408 /* We had one special case above where I2 had more than one set and
4409 we replaced a destination of one of those sets with the destination
4410 of I3. In that case, we have to update LOG_LINKS of insns later
4411 in this basic block. Note that this (expensive) case is rare.
4413 Also, in this case, we must pretend that all REG_NOTEs for I2
4414 actually came from I3, so that REG_UNUSED notes from I2 will be
4415 properly handled. */
4417 if (i3_subst_into_i2
)
4419 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4420 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4421 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4422 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4423 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4424 && ! find_reg_note (i2
, REG_UNUSED
,
4425 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4426 for (temp_insn
= NEXT_INSN (i2
);
4428 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4429 || BB_HEAD (this_basic_block
) != temp_insn
);
4430 temp_insn
= NEXT_INSN (temp_insn
))
4431 if (temp_insn
!= i3
&& NONDEBUG_INSN_P (temp_insn
))
4432 FOR_EACH_LOG_LINK (link
, temp_insn
)
4433 if (link
->insn
== i2
)
4439 while (XEXP (link
, 1))
4440 link
= XEXP (link
, 1);
4441 XEXP (link
, 1) = i2notes
;
4448 LOG_LINKS (i3
) = NULL
;
4450 LOG_LINKS (i2
) = NULL
;
4455 if (MAY_HAVE_DEBUG_BIND_INSNS
&& i2scratch
)
4456 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4458 INSN_CODE (i2
) = i2_code_number
;
4459 PATTERN (i2
) = newi2pat
;
4463 if (MAY_HAVE_DEBUG_BIND_INSNS
&& i2src
)
4464 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4466 SET_INSN_DELETED (i2
);
4471 LOG_LINKS (i1
) = NULL
;
4473 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4474 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4476 SET_INSN_DELETED (i1
);
4481 LOG_LINKS (i0
) = NULL
;
4483 if (MAY_HAVE_DEBUG_BIND_INSNS
)
4484 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4486 SET_INSN_DELETED (i0
);
4489 /* Get death notes for everything that is now used in either I3 or
4490 I2 and used to die in a previous insn. If we built two new
4491 patterns, move from I1 to I2 then I2 to I3 so that we get the
4492 proper movement on registers that I2 modifies. */
4495 from_luid
= DF_INSN_LUID (i0
);
4497 from_luid
= DF_INSN_LUID (i1
);
4499 from_luid
= DF_INSN_LUID (i2
);
4501 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4502 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4504 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4506 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4507 elim_i2
, elim_i1
, elim_i0
);
4509 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4510 elim_i2
, elim_i1
, elim_i0
);
4512 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4513 elim_i2
, local_elim_i1
, local_elim_i0
);
4515 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4516 elim_i2
, elim_i1
, local_elim_i0
);
4518 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4519 elim_i2
, elim_i1
, elim_i0
);
4521 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4522 know these are REG_UNUSED and want them to go to the desired insn,
4523 so we always pass it as i3. */
4525 if (newi2pat
&& new_i2_notes
)
4526 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4530 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4533 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4534 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4535 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4536 in that case, it might delete I2. Similarly for I2 and I1.
4537 Show an additional death due to the REG_DEAD note we make here. If
4538 we discard it in distribute_notes, we will decrement it again. */
4542 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4543 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4544 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4547 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4548 elim_i2
, elim_i1
, elim_i0
);
4551 if (i2dest_in_i2src
)
4553 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4554 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4555 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4556 NULL_RTX
, NULL_RTX
);
4558 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4559 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4562 if (i1dest_in_i1src
)
4564 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4565 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4566 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4567 NULL_RTX
, NULL_RTX
);
4569 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4570 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4573 if (i0dest_in_i0src
)
4575 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4576 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4577 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4578 NULL_RTX
, NULL_RTX
);
4580 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4581 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4584 distribute_links (i3links
);
4585 distribute_links (i2links
);
4586 distribute_links (i1links
);
4587 distribute_links (i0links
);
4591 struct insn_link
*link
;
4592 rtx_insn
*i2_insn
= 0;
4593 rtx i2_val
= 0, set
;
4595 /* The insn that used to set this register doesn't exist, and
4596 this life of the register may not exist either. See if one of
4597 I3's links points to an insn that sets I2DEST. If it does,
4598 that is now the last known value for I2DEST. If we don't update
4599 this and I2 set the register to a value that depended on its old
4600 contents, we will get confused. If this insn is used, thing
4601 will be set correctly in combine_instructions. */
4602 FOR_EACH_LOG_LINK (link
, i3
)
4603 if ((set
= single_set (link
->insn
)) != 0
4604 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4605 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4607 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4609 /* If the reg formerly set in I2 died only once and that was in I3,
4610 zero its use count so it won't make `reload' do any work. */
4612 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4613 && ! i2dest_in_i2src
4614 && REGNO (i2dest
) < reg_n_sets_max
)
4615 INC_REG_N_SETS (REGNO (i2dest
), -1);
4618 if (i1
&& REG_P (i1dest
))
4620 struct insn_link
*link
;
4621 rtx_insn
*i1_insn
= 0;
4622 rtx i1_val
= 0, set
;
4624 FOR_EACH_LOG_LINK (link
, i3
)
4625 if ((set
= single_set (link
->insn
)) != 0
4626 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4627 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4629 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4632 && ! i1dest_in_i1src
4633 && REGNO (i1dest
) < reg_n_sets_max
)
4634 INC_REG_N_SETS (REGNO (i1dest
), -1);
4637 if (i0
&& REG_P (i0dest
))
4639 struct insn_link
*link
;
4640 rtx_insn
*i0_insn
= 0;
4641 rtx i0_val
= 0, set
;
4643 FOR_EACH_LOG_LINK (link
, i3
)
4644 if ((set
= single_set (link
->insn
)) != 0
4645 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4646 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4648 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4651 && ! i0dest_in_i0src
4652 && REGNO (i0dest
) < reg_n_sets_max
)
4653 INC_REG_N_SETS (REGNO (i0dest
), -1);
4656 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4657 been made to this insn. The order is important, because newi2pat
4658 can affect nonzero_bits of newpat. */
4660 note_pattern_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4661 note_pattern_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4664 if (undobuf
.other_insn
!= NULL_RTX
)
4668 fprintf (dump_file
, "modifying other_insn ");
4669 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4671 df_insn_rescan (undobuf
.other_insn
);
4674 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4678 fprintf (dump_file
, "modifying insn i0 ");
4679 dump_insn_slim (dump_file
, i0
);
4681 df_insn_rescan (i0
);
4684 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4688 fprintf (dump_file
, "modifying insn i1 ");
4689 dump_insn_slim (dump_file
, i1
);
4691 df_insn_rescan (i1
);
4694 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4698 fprintf (dump_file
, "modifying insn i2 ");
4699 dump_insn_slim (dump_file
, i2
);
4701 df_insn_rescan (i2
);
4704 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4708 fprintf (dump_file
, "modifying insn i3 ");
4709 dump_insn_slim (dump_file
, i3
);
4711 df_insn_rescan (i3
);
4714 /* Set new_direct_jump_p if a new return or simple jump instruction
4715 has been created. Adjust the CFG accordingly. */
4716 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4718 *new_direct_jump_p
= 1;
4719 mark_jump_label (PATTERN (i3
), i3
, 0);
4720 update_cfg_for_uncondjump (i3
);
4723 if (undobuf
.other_insn
!= NULL_RTX
4724 && (returnjump_p (undobuf
.other_insn
)
4725 || any_uncondjump_p (undobuf
.other_insn
)))
4727 *new_direct_jump_p
= 1;
4728 update_cfg_for_uncondjump (undobuf
.other_insn
);
4731 if (GET_CODE (PATTERN (i3
)) == TRAP_IF
4732 && XEXP (PATTERN (i3
), 0) == const1_rtx
)
4734 basic_block bb
= BLOCK_FOR_INSN (i3
);
4736 remove_edge (split_block (bb
, i3
));
4737 emit_barrier_after_bb (bb
);
4738 *new_direct_jump_p
= 1;
4741 if (undobuf
.other_insn
4742 && GET_CODE (PATTERN (undobuf
.other_insn
)) == TRAP_IF
4743 && XEXP (PATTERN (undobuf
.other_insn
), 0) == const1_rtx
)
4745 basic_block bb
= BLOCK_FOR_INSN (undobuf
.other_insn
);
4747 remove_edge (split_block (bb
, undobuf
.other_insn
));
4748 emit_barrier_after_bb (bb
);
4749 *new_direct_jump_p
= 1;
4752 /* A noop might also need cleaning up of CFG, if it comes from the
4753 simplification of a jump. */
4755 && GET_CODE (newpat
) == SET
4756 && SET_SRC (newpat
) == pc_rtx
4757 && SET_DEST (newpat
) == pc_rtx
)
4759 *new_direct_jump_p
= 1;
4760 update_cfg_for_uncondjump (i3
);
4763 if (undobuf
.other_insn
!= NULL_RTX
4764 && JUMP_P (undobuf
.other_insn
)
4765 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4766 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4767 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4769 *new_direct_jump_p
= 1;
4770 update_cfg_for_uncondjump (undobuf
.other_insn
);
4773 combine_successes
++;
4776 rtx_insn
*ret
= newi2pat
? i2
: i3
;
4777 if (added_links_insn
&& DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (ret
))
4778 ret
= added_links_insn
;
4779 if (added_notes_insn
&& DF_INSN_LUID (added_notes_insn
) < DF_INSN_LUID (ret
))
4780 ret
= added_notes_insn
;
4785 /* Get a marker for undoing to the current state. */
4788 get_undo_marker (void)
4790 return undobuf
.undos
;
4793 /* Undo the modifications up to the marker. */
4796 undo_to_marker (void *marker
)
4798 struct undo
*undo
, *next
;
4800 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4808 *undo
->where
.r
= undo
->old_contents
.r
;
4811 *undo
->where
.i
= undo
->old_contents
.i
;
4814 adjust_reg_mode (regno_reg_rtx
[undo
->where
.regno
],
4815 undo
->old_contents
.m
);
4818 *undo
->where
.l
= undo
->old_contents
.l
;
4824 undo
->next
= undobuf
.frees
;
4825 undobuf
.frees
= undo
;
4828 undobuf
.undos
= (struct undo
*) marker
;
4831 /* Undo all the modifications recorded in undobuf. */
4839 /* We've committed to accepting the changes we made. Move all
4840 of the undos to the free list. */
4845 struct undo
*undo
, *next
;
4847 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4850 undo
->next
= undobuf
.frees
;
4851 undobuf
.frees
= undo
;
4856 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4857 where we have an arithmetic expression and return that point. LOC will
4860 try_combine will call this function to see if an insn can be split into
4864 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4867 enum rtx_code code
= GET_CODE (x
);
4869 unsigned HOST_WIDE_INT len
= 0;
4870 HOST_WIDE_INT pos
= 0;
4871 bool unsignedp
= false;
4872 rtx inner
= NULL_RTX
;
4873 scalar_int_mode mode
, inner_mode
;
4875 /* First special-case some codes. */
4879 #ifdef INSN_SCHEDULING
4880 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4882 if (MEM_P (SUBREG_REG (x
)))
4885 return find_split_point (&SUBREG_REG (x
), insn
, false);
4888 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4889 using LO_SUM and HIGH. */
4890 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4891 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4893 machine_mode address_mode
= get_address_mode (x
);
4896 gen_rtx_LO_SUM (address_mode
,
4897 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4899 return &XEXP (XEXP (x
, 0), 0);
4902 /* If we have a PLUS whose second operand is a constant and the
4903 address is not valid, perhaps we can split it up using
4904 the machine-specific way to split large constants. We use
4905 the first pseudo-reg (one of the virtual regs) as a placeholder;
4906 it will not remain in the result. */
4907 if (GET_CODE (XEXP (x
, 0)) == PLUS
4908 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4909 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4910 MEM_ADDR_SPACE (x
)))
4912 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4913 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4916 /* This should have produced two insns, each of which sets our
4917 placeholder. If the source of the second is a valid address,
4918 we can put both sources together and make a split point
4922 && NEXT_INSN (seq
) != NULL_RTX
4923 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4924 && NONJUMP_INSN_P (seq
)
4925 && GET_CODE (PATTERN (seq
)) == SET
4926 && SET_DEST (PATTERN (seq
)) == reg
4927 && ! reg_mentioned_p (reg
,
4928 SET_SRC (PATTERN (seq
)))
4929 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4930 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4931 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4932 && memory_address_addr_space_p
4933 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4934 MEM_ADDR_SPACE (x
)))
4936 rtx src1
= SET_SRC (PATTERN (seq
));
4937 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4939 /* Replace the placeholder in SRC2 with SRC1. If we can
4940 find where in SRC2 it was placed, that can become our
4941 split point and we can replace this address with SRC2.
4942 Just try two obvious places. */
4944 src2
= replace_rtx (src2
, reg
, src1
);
4946 if (XEXP (src2
, 0) == src1
)
4947 split
= &XEXP (src2
, 0);
4948 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4949 && XEXP (XEXP (src2
, 0), 0) == src1
)
4950 split
= &XEXP (XEXP (src2
, 0), 0);
4954 SUBST (XEXP (x
, 0), src2
);
4959 /* If that didn't work and we have a nested plus, like:
4960 ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
4961 is valid address, try to split (REG1 * CONST1). */
4962 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
4963 && !OBJECT_P (XEXP (XEXP (XEXP (x
, 0), 0), 0))
4964 && OBJECT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4965 && ! (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SUBREG
4966 && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x
, 0),
4969 rtx tem
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4970 XEXP (XEXP (XEXP (x
, 0), 0), 0) = reg
;
4971 if (memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4972 MEM_ADDR_SPACE (x
)))
4974 XEXP (XEXP (XEXP (x
, 0), 0), 0) = tem
;
4975 return &XEXP (XEXP (XEXP (x
, 0), 0), 0);
4977 XEXP (XEXP (XEXP (x
, 0), 0), 0) = tem
;
4979 else if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
4980 && OBJECT_P (XEXP (XEXP (XEXP (x
, 0), 0), 0))
4981 && !OBJECT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4982 && ! (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == SUBREG
4983 && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x
, 0),
4986 rtx tem
= XEXP (XEXP (XEXP (x
, 0), 0), 1);
4987 XEXP (XEXP (XEXP (x
, 0), 0), 1) = reg
;
4988 if (memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4989 MEM_ADDR_SPACE (x
)))
4991 XEXP (XEXP (XEXP (x
, 0), 0), 1) = tem
;
4992 return &XEXP (XEXP (XEXP (x
, 0), 0), 1);
4994 XEXP (XEXP (XEXP (x
, 0), 0), 1) = tem
;
4997 /* If that didn't work, perhaps the first operand is complex and
4998 needs to be computed separately, so make a split point there.
4999 This will occur on machines that just support REG + CONST
5000 and have a constant moved through some previous computation. */
5001 if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
5002 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
5003 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
5004 return &XEXP (XEXP (x
, 0), 0);
5007 /* If we have a PLUS whose first operand is complex, try computing it
5008 separately by making a split there. */
5009 if (GET_CODE (XEXP (x
, 0)) == PLUS
5010 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
5012 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
5013 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
5014 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
5015 return &XEXP (XEXP (x
, 0), 0);
5019 /* See if we can split SET_SRC as it stands. */
5020 split
= find_split_point (&SET_SRC (x
), insn
, true);
5021 if (split
&& split
!= &SET_SRC (x
))
5024 /* See if we can split SET_DEST as it stands. */
5025 split
= find_split_point (&SET_DEST (x
), insn
, false);
5026 if (split
&& split
!= &SET_DEST (x
))
5029 /* See if this is a bitfield assignment with everything constant. If
5030 so, this is an IOR of an AND, so split it into that. */
5031 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5032 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (SET_DEST (x
), 0)),
5034 && HWI_COMPUTABLE_MODE_P (inner_mode
)
5035 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
5036 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
5037 && CONST_INT_P (SET_SRC (x
))
5038 && ((INTVAL (XEXP (SET_DEST (x
), 1))
5039 + INTVAL (XEXP (SET_DEST (x
), 2)))
5040 <= GET_MODE_PRECISION (inner_mode
))
5041 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
5043 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
5044 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
5045 rtx dest
= XEXP (SET_DEST (x
), 0);
5046 unsigned HOST_WIDE_INT mask
= (HOST_WIDE_INT_1U
<< len
) - 1;
5047 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
)) & mask
;
5050 if (BITS_BIG_ENDIAN
)
5051 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
5053 or_mask
= gen_int_mode (src
<< pos
, inner_mode
);
5056 simplify_gen_binary (IOR
, inner_mode
, dest
, or_mask
));
5059 rtx negmask
= gen_int_mode (~(mask
<< pos
), inner_mode
);
5061 simplify_gen_binary (IOR
, inner_mode
,
5062 simplify_gen_binary (AND
, inner_mode
,
5067 SUBST (SET_DEST (x
), dest
);
5069 split
= find_split_point (&SET_SRC (x
), insn
, true);
5070 if (split
&& split
!= &SET_SRC (x
))
5074 /* Otherwise, see if this is an operation that we can split into two.
5075 If so, try to split that. */
5076 code
= GET_CODE (SET_SRC (x
));
5081 /* If we are AND'ing with a large constant that is only a single
5082 bit and the result is only being used in a context where we
5083 need to know if it is zero or nonzero, replace it with a bit
5084 extraction. This will avoid the large constant, which might
5085 have taken more than one insn to make. If the constant were
5086 not a valid argument to the AND but took only one insn to make,
5087 this is no worse, but if it took more than one insn, it will
5090 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
5091 && REG_P (XEXP (SET_SRC (x
), 0))
5092 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
5093 && REG_P (SET_DEST (x
))
5094 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
5095 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
5096 && XEXP (*split
, 0) == SET_DEST (x
)
5097 && XEXP (*split
, 1) == const0_rtx
)
5099 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
5100 XEXP (SET_SRC (x
), 0),
5102 true, false, false);
5103 if (extraction
!= 0)
5105 SUBST (SET_SRC (x
), extraction
);
5106 return find_split_point (loc
, insn
, false);
5112 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5113 is known to be on, this can be converted into a NEG of a shift. */
5114 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
5115 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
5116 && ((pos
= exact_log2 (nonzero_bits (XEXP (SET_SRC (x
), 0),
5117 GET_MODE (XEXP (SET_SRC (x
),
5120 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
5121 rtx pos_rtx
= gen_int_shift_amount (mode
, pos
);
5124 gen_rtx_LSHIFTRT (mode
,
5125 XEXP (SET_SRC (x
), 0),
5128 split
= find_split_point (&SET_SRC (x
), insn
, true);
5129 if (split
&& split
!= &SET_SRC (x
))
5135 inner
= XEXP (SET_SRC (x
), 0);
5137 /* We can't optimize if either mode is a partial integer
5138 mode as we don't know how many bits are significant
5140 if (!is_int_mode (GET_MODE (inner
), &inner_mode
)
5141 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
5145 len
= GET_MODE_PRECISION (inner_mode
);
5151 if (is_a
<scalar_int_mode
> (GET_MODE (XEXP (SET_SRC (x
), 0)),
5153 && CONST_INT_P (XEXP (SET_SRC (x
), 1))
5154 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
5156 inner
= XEXP (SET_SRC (x
), 0);
5157 len
= INTVAL (XEXP (SET_SRC (x
), 1));
5158 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
5160 if (BITS_BIG_ENDIAN
)
5161 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
5162 unsignedp
= (code
== ZERO_EXTRACT
);
5171 && known_subrange_p (pos
, len
,
5172 0, GET_MODE_PRECISION (GET_MODE (inner
)))
5173 && is_a
<scalar_int_mode
> (GET_MODE (SET_SRC (x
)), &mode
))
5175 /* For unsigned, we have a choice of a shift followed by an
5176 AND or two shifts. Use two shifts for field sizes where the
5177 constant might be too large. We assume here that we can
5178 always at least get 8-bit constants in an AND insn, which is
5179 true for every current RISC. */
5181 if (unsignedp
&& len
<= 8)
5183 unsigned HOST_WIDE_INT mask
5184 = (HOST_WIDE_INT_1U
<< len
) - 1;
5185 rtx pos_rtx
= gen_int_shift_amount (mode
, pos
);
5189 (mode
, gen_lowpart (mode
, inner
), pos_rtx
),
5190 gen_int_mode (mask
, mode
)));
5192 split
= find_split_point (&SET_SRC (x
), insn
, true);
5193 if (split
&& split
!= &SET_SRC (x
))
5198 int left_bits
= GET_MODE_PRECISION (mode
) - len
- pos
;
5199 int right_bits
= GET_MODE_PRECISION (mode
) - len
;
5202 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5203 gen_rtx_ASHIFT (mode
,
5204 gen_lowpart (mode
, inner
),
5205 gen_int_shift_amount (mode
, left_bits
)),
5206 gen_int_shift_amount (mode
, right_bits
)));
5208 split
= find_split_point (&SET_SRC (x
), insn
, true);
5209 if (split
&& split
!= &SET_SRC (x
))
5214 /* See if this is a simple operation with a constant as the second
5215 operand. It might be that this constant is out of range and hence
5216 could be used as a split point. */
5217 if (BINARY_P (SET_SRC (x
))
5218 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5219 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5220 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5221 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5222 return &XEXP (SET_SRC (x
), 1);
5224 /* Finally, see if this is a simple operation with its first operand
5225 not in a register. The operation might require this operand in a
5226 register, so return it as a split point. We can always do this
5227 because if the first operand were another operation, we would have
5228 already found it as a split point. */
5229 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5230 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5231 return &XEXP (SET_SRC (x
), 0);
5237 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5238 it is better to write this as (not (ior A B)) so we can split it.
5239 Similarly for IOR. */
5240 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5243 gen_rtx_NOT (GET_MODE (x
),
5244 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5246 XEXP (XEXP (x
, 0), 0),
5247 XEXP (XEXP (x
, 1), 0))));
5248 return find_split_point (loc
, insn
, set_src
);
5251 /* Many RISC machines have a large set of logical insns. If the
5252 second operand is a NOT, put it first so we will try to split the
5253 other operand first. */
5254 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5256 rtx tem
= XEXP (x
, 0);
5257 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5258 SUBST (XEXP (x
, 1), tem
);
5264 /* Canonicalization can produce (minus A (mult B C)), where C is a
5265 constant. It may be better to try splitting (plus (mult B -C) A)
5266 instead if this isn't a multiply by a power of two. */
5267 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5268 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5269 && !pow2p_hwi (INTVAL (XEXP (XEXP (x
, 1), 1))))
5271 machine_mode mode
= GET_MODE (x
);
5272 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5273 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5274 SUBST (*loc
, gen_rtx_PLUS (mode
,
5276 XEXP (XEXP (x
, 1), 0),
5277 gen_int_mode (other_int
,
5280 return find_split_point (loc
, insn
, set_src
);
5283 /* Split at a multiply-accumulate instruction. However if this is
5284 the SET_SRC, we likely do not have such an instruction and it's
5285 worthless to try this split. */
5287 && (GET_CODE (XEXP (x
, 0)) == MULT
5288 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5289 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5296 /* Otherwise, select our actions depending on our rtx class. */
5297 switch (GET_RTX_CLASS (code
))
5299 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5301 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5306 case RTX_COMM_ARITH
:
5308 case RTX_COMM_COMPARE
:
5309 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5314 /* Some machines have (and (shift ...) ...) insns. If X is not
5315 an AND, but XEXP (X, 0) is, use it as our split point. */
5316 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5317 return &XEXP (x
, 0);
5319 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5325 /* Otherwise, we don't have a split point. */
5330 /* Throughout X, replace FROM with TO, and return the result.
5331 The result is TO if X is FROM;
5332 otherwise the result is X, but its contents may have been modified.
5333 If they were modified, a record was made in undobuf so that
5334 undo_all will (among other things) return X to its original state.
5336 If the number of changes necessary is too much to record to undo,
5337 the excess changes are not made, so the result is invalid.
5338 The changes already made can still be undone.
5339 undobuf.num_undo is incremented for such changes, so by testing that
5340 the caller can tell whether the result is valid.
5342 `n_occurrences' is incremented each time FROM is replaced.
5344 IN_DEST is true if we are processing the SET_DEST of a SET.
5346 IN_COND is true if we are at the top level of a condition.
5348 UNIQUE_COPY is true if each substitution must be unique. We do this
5349 by copying if `n_occurrences' is nonzero. */
5352 subst (rtx x
, rtx from
, rtx to
, bool in_dest
, bool in_cond
, bool unique_copy
)
5354 enum rtx_code code
= GET_CODE (x
);
5355 machine_mode op0_mode
= VOIDmode
;
5360 /* Two expressions are equal if they are identical copies of a shared
5361 RTX or if they are both registers with the same register number
5364 #define COMBINE_RTX_EQUAL_P(X,Y) \
5366 || (REG_P (X) && REG_P (Y) \
5367 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5369 /* Do not substitute into clobbers of regs -- this will never result in
5371 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5374 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5377 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5380 /* If X and FROM are the same register but different modes, they
5381 will not have been seen as equal above. However, the log links code
5382 will make a LOG_LINKS entry for that case. If we do nothing, we
5383 will try to rerecognize our original insn and, when it succeeds,
5384 we will delete the feeding insn, which is incorrect.
5386 So force this insn not to match in this (rare) case. */
5387 if (! in_dest
&& code
== REG
&& REG_P (from
)
5388 && reg_overlap_mentioned_p (x
, from
))
5389 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5391 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5392 of which may contain things that can be combined. */
5393 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5396 /* It is possible to have a subexpression appear twice in the insn.
5397 Suppose that FROM is a register that appears within TO.
5398 Then, after that subexpression has been scanned once by `subst',
5399 the second time it is scanned, TO may be found. If we were
5400 to scan TO here, we would find FROM within it and create a
5401 self-referent rtl structure which is completely wrong. */
5402 if (COMBINE_RTX_EQUAL_P (x
, to
))
5405 /* Parallel asm_operands need special attention because all of the
5406 inputs are shared across the arms. Furthermore, unsharing the
5407 rtl results in recognition failures. Failure to handle this case
5408 specially can result in circular rtl.
5410 Solve this by doing a normal pass across the first entry of the
5411 parallel, and only processing the SET_DESTs of the subsequent
5414 if (code
== PARALLEL
5415 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5416 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5418 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, false, false, unique_copy
);
5420 /* If this substitution failed, this whole thing fails. */
5421 if (GET_CODE (new_rtx
) == CLOBBER
5422 && XEXP (new_rtx
, 0) == const0_rtx
)
5425 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5427 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5429 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5431 if (!REG_P (dest
) && GET_CODE (dest
) != PC
)
5433 new_rtx
= subst (dest
, from
, to
, false, false, unique_copy
);
5435 /* If this substitution failed, this whole thing fails. */
5436 if (GET_CODE (new_rtx
) == CLOBBER
5437 && XEXP (new_rtx
, 0) == const0_rtx
)
5440 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5446 len
= GET_RTX_LENGTH (code
);
5447 fmt
= GET_RTX_FORMAT (code
);
5449 /* We don't need to process a SET_DEST that is a register or PC, so
5450 set up to skip this common case. All other cases where we want
5451 to suppress replacing something inside a SET_SRC are handled via
5452 the IN_DEST operand. */
5454 && (REG_P (SET_DEST (x
))
5455 || GET_CODE (SET_DEST (x
)) == PC
))
5458 /* Trying to simplify the operands of a widening MULT is not likely
5459 to create RTL matching a machine insn. */
5461 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5462 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
5463 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
5464 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
5465 && REG_P (XEXP (XEXP (x
, 0), 0))
5466 && REG_P (XEXP (XEXP (x
, 1), 0))
5471 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5474 op0_mode
= GET_MODE (XEXP (x
, 0));
5476 for (i
= 0; i
< len
; i
++)
5481 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5483 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5485 new_rtx
= (unique_copy
&& n_occurrences
5486 ? copy_rtx (to
) : to
);
5491 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
,
5492 false, false, unique_copy
);
5494 /* If this substitution failed, this whole thing
5496 if (GET_CODE (new_rtx
) == CLOBBER
5497 && XEXP (new_rtx
, 0) == const0_rtx
)
5501 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5504 else if (fmt
[i
] == 'e')
5506 /* If this is a register being set, ignore it. */
5507 new_rtx
= XEXP (x
, i
);
5510 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5512 || code
== STRICT_LOW_PART
))
5515 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5517 /* In general, don't install a subreg involving two
5518 modes not tieable. It can worsen register
5519 allocation, and can even make invalid reload
5520 insns, since the reg inside may need to be copied
5521 from in the outside mode, and that may be invalid
5522 if it is an fp reg copied in integer mode.
5524 We allow an exception to this: It is valid if
5525 it is inside another SUBREG and the mode of that
5526 SUBREG and the mode of the inside of TO is
5529 if (GET_CODE (to
) == SUBREG
5530 && !targetm
.modes_tieable_p (GET_MODE (to
),
5531 GET_MODE (SUBREG_REG (to
)))
5532 && ! (code
== SUBREG
5533 && (targetm
.modes_tieable_p
5534 (GET_MODE (x
), GET_MODE (SUBREG_REG (to
))))))
5535 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5539 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5540 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5543 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5545 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5549 /* If we are in a SET_DEST, suppress most cases unless we
5550 have gone inside a MEM, in which case we want to
5551 simplify the address. We assume here that things that
5552 are actually part of the destination have their inner
5553 parts in the first expression. This is true for SUBREG,
5554 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5555 things aside from REG and MEM that should appear in a
5557 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5559 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5560 || code
== ZERO_EXTRACT
))
5563 code
== IF_THEN_ELSE
&& i
== 0,
5566 /* If we found that we will have to reject this combination,
5567 indicate that by returning the CLOBBER ourselves, rather than
5568 an expression containing it. This will speed things up as
5569 well as prevent accidents where two CLOBBERs are considered
5570 to be equal, thus producing an incorrect simplification. */
5572 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5575 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5577 machine_mode mode
= GET_MODE (x
);
5579 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5580 GET_MODE (SUBREG_REG (x
)),
5583 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5585 else if (CONST_SCALAR_INT_P (new_rtx
)
5586 && (GET_CODE (x
) == ZERO_EXTEND
5587 || GET_CODE (x
) == SIGN_EXTEND
5588 || GET_CODE (x
) == FLOAT
5589 || GET_CODE (x
) == UNSIGNED_FLOAT
))
5591 x
= simplify_unary_operation (GET_CODE (x
), GET_MODE (x
),
5593 GET_MODE (XEXP (x
, 0)));
5595 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5597 /* CONST_INTs shouldn't be substituted into PRE_DEC, PRE_MODIFY
5598 etc. arguments, otherwise we can ICE before trying to recog
5599 it. See PR104446. */
5600 else if (CONST_SCALAR_INT_P (new_rtx
)
5601 && GET_RTX_CLASS (GET_CODE (x
)) == RTX_AUTOINC
)
5602 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5604 SUBST (XEXP (x
, i
), new_rtx
);
5609 /* Check if we are loading something from the constant pool via float
5610 extension; in this case we would undo compress_float_constant
5611 optimization and degenerate constant load to an immediate value. */
5612 if (GET_CODE (x
) == FLOAT_EXTEND
5613 && MEM_P (XEXP (x
, 0))
5614 && MEM_READONLY_P (XEXP (x
, 0)))
5616 rtx tmp
= avoid_constant_pool_reference (x
);
5621 /* Try to simplify X. If the simplification changed the code, it is likely
5622 that further simplification will help, so loop, but limit the number
5623 of repetitions that will be performed. */
5625 for (i
= 0; i
< 4; i
++)
5627 /* If X is sufficiently simple, don't bother trying to do anything
5629 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5630 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5632 if (GET_CODE (x
) == code
)
5635 code
= GET_CODE (x
);
5637 /* We no longer know the original mode of operand 0 since we
5638 have changed the form of X) */
5639 op0_mode
= VOIDmode
;
5645 /* If X is a commutative operation whose operands are not in the canonical
5646 order, use substitutions to swap them. */
5649 maybe_swap_commutative_operands (rtx x
)
5651 if (COMMUTATIVE_ARITH_P (x
)
5652 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5654 rtx temp
= XEXP (x
, 0);
5655 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5656 SUBST (XEXP (x
, 1), temp
);
5659 unsigned n_elts
= 0;
5660 if (GET_CODE (x
) == VEC_MERGE
5661 && CONST_INT_P (XEXP (x
, 2))
5662 && GET_MODE_NUNITS (GET_MODE (x
)).is_constant (&n_elts
)
5663 && (swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1))
5664 /* Two operands have same precedence, then
5665 first bit of mask select first operand. */
5666 || (!swap_commutative_operands_p (XEXP (x
, 1), XEXP (x
, 0))
5667 && !(UINTVAL (XEXP (x
, 2)) & 1))))
5669 rtx temp
= XEXP (x
, 0);
5670 unsigned HOST_WIDE_INT sel
= UINTVAL (XEXP (x
, 2));
5671 unsigned HOST_WIDE_INT mask
= HOST_WIDE_INT_1U
;
5672 if (n_elts
== HOST_BITS_PER_WIDE_INT
)
5675 mask
= (HOST_WIDE_INT_1U
<< n_elts
) - 1;
5676 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5677 SUBST (XEXP (x
, 1), temp
);
5678 SUBST (XEXP (x
, 2), GEN_INT (~sel
& mask
));
5682 /* Simplify X, a piece of RTL. We just operate on the expression at the
5683 outer level; call `subst' to simplify recursively. Return the new
5686 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is true
5687 if we are inside a SET_DEST. IN_COND is true if we are at the top level
5691 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, bool in_dest
, bool in_cond
)
5693 enum rtx_code code
= GET_CODE (x
);
5694 machine_mode mode
= GET_MODE (x
);
5695 scalar_int_mode int_mode
;
5699 /* If this is a commutative operation, put a constant last and a complex
5700 expression first. We don't need to do this for comparisons here. */
5701 maybe_swap_commutative_operands (x
);
5703 /* Try to fold this expression in case we have constants that weren't
5706 switch (GET_RTX_CLASS (code
))
5709 if (op0_mode
== VOIDmode
)
5710 op0_mode
= GET_MODE (XEXP (x
, 0));
5711 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5714 case RTX_COMM_COMPARE
:
5716 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5717 if (cmp_mode
== VOIDmode
)
5719 cmp_mode
= GET_MODE (XEXP (x
, 1));
5720 if (cmp_mode
== VOIDmode
)
5721 cmp_mode
= op0_mode
;
5723 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5724 XEXP (x
, 0), XEXP (x
, 1));
5727 case RTX_COMM_ARITH
:
5729 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5731 case RTX_BITFIELD_OPS
:
5733 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5734 XEXP (x
, 1), XEXP (x
, 2));
5743 code
= GET_CODE (temp
);
5744 op0_mode
= VOIDmode
;
5745 mode
= GET_MODE (temp
);
5748 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5749 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5750 things. Check for cases where both arms are testing the same
5753 Don't do anything if all operands are very simple. */
5756 && ((!OBJECT_P (XEXP (x
, 0))
5757 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5758 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5759 || (!OBJECT_P (XEXP (x
, 1))
5760 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5761 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5763 && (!OBJECT_P (XEXP (x
, 0))
5764 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5765 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5767 rtx cond
, true_rtx
, false_rtx
;
5769 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5771 /* If everything is a comparison, what we have is highly unlikely
5772 to be simpler, so don't use it. */
5773 && ! (COMPARISON_P (x
)
5774 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
)))
5775 /* Similarly, if we end up with one of the expressions the same
5776 as the original, it is certainly not simpler. */
5777 && ! rtx_equal_p (x
, true_rtx
)
5778 && ! rtx_equal_p (x
, false_rtx
))
5780 rtx cop1
= const0_rtx
;
5781 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5783 if (cond_code
== NE
&& COMPARISON_P (cond
))
5786 /* Simplify the alternative arms; this may collapse the true and
5787 false arms to store-flag values. Be careful to use copy_rtx
5788 here since true_rtx or false_rtx might share RTL with x as a
5789 result of the if_then_else_cond call above. */
5790 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
,
5791 false, false, false);
5792 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
,
5793 false, false, false);
5795 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5796 is unlikely to be simpler. */
5797 if (general_operand (true_rtx
, VOIDmode
)
5798 && general_operand (false_rtx
, VOIDmode
))
5800 enum rtx_code reversed
;
5802 /* Restarting if we generate a store-flag expression will cause
5803 us to loop. Just drop through in this case. */
5805 /* If the result values are STORE_FLAG_VALUE and zero, we can
5806 just make the comparison operation. */
5807 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5808 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5810 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5811 && ((reversed
= reversed_comparison_code_parts
5812 (cond_code
, cond
, cop1
, NULL
))
5814 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5817 /* Likewise, we can make the negate of a comparison operation
5818 if the result values are - STORE_FLAG_VALUE and zero. */
5819 else if (CONST_INT_P (true_rtx
)
5820 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5821 && false_rtx
== const0_rtx
)
5822 x
= simplify_gen_unary (NEG
, mode
,
5823 simplify_gen_relational (cond_code
,
5827 else if (CONST_INT_P (false_rtx
)
5828 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5829 && true_rtx
== const0_rtx
5830 && ((reversed
= reversed_comparison_code_parts
5831 (cond_code
, cond
, cop1
, NULL
))
5833 x
= simplify_gen_unary (NEG
, mode
,
5834 simplify_gen_relational (reversed
,
5839 code
= GET_CODE (x
);
5840 op0_mode
= VOIDmode
;
5845 /* First see if we can apply the inverse distributive law. */
5846 if (code
== PLUS
|| code
== MINUS
5847 || code
== AND
|| code
== IOR
|| code
== XOR
)
5849 x
= apply_distributive_law (x
);
5850 code
= GET_CODE (x
);
5851 op0_mode
= VOIDmode
;
5854 /* If CODE is an associative operation not otherwise handled, see if we
5855 can associate some operands. This can win if they are constants or
5856 if they are logically related (i.e. (a & b) & a). */
5857 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5858 || code
== AND
|| code
== IOR
|| code
== XOR
5859 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5860 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5861 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5863 if (GET_CODE (XEXP (x
, 0)) == code
)
5865 rtx other
= XEXP (XEXP (x
, 0), 0);
5866 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5867 rtx inner_op1
= XEXP (x
, 1);
5870 /* Make sure we pass the constant operand if any as the second
5871 one if this is a commutative operation. */
5872 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5873 std::swap (inner_op0
, inner_op1
);
5874 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5875 : code
== DIV
? MULT
5877 mode
, inner_op0
, inner_op1
);
5879 /* For commutative operations, try the other pair if that one
5881 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5883 other
= XEXP (XEXP (x
, 0), 1);
5884 inner
= simplify_binary_operation (code
, mode
,
5885 XEXP (XEXP (x
, 0), 0),
5890 return simplify_gen_binary (code
, mode
, other
, inner
);
5894 /* A little bit of algebraic simplification here. */
5898 /* Ensure that our address has any ASHIFTs converted to MULT in case
5899 address-recognizing predicates are called later. */
5900 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5901 SUBST (XEXP (x
, 0), temp
);
5905 if (op0_mode
== VOIDmode
)
5906 op0_mode
= GET_MODE (SUBREG_REG (x
));
5908 /* See if this can be moved to simplify_subreg. */
5909 if (CONSTANT_P (SUBREG_REG (x
))
5910 && known_eq (subreg_lowpart_offset (mode
, op0_mode
), SUBREG_BYTE (x
))
5911 /* Don't call gen_lowpart if the inner mode
5912 is VOIDmode and we cannot simplify it, as SUBREG without
5913 inner mode is invalid. */
5914 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5915 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5916 return gen_lowpart (mode
, SUBREG_REG (x
));
5918 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5922 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5927 /* If op is known to have all lower bits zero, the result is zero. */
5928 scalar_int_mode int_mode
, int_op0_mode
;
5930 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5931 && is_a
<scalar_int_mode
> (op0_mode
, &int_op0_mode
)
5932 && (GET_MODE_PRECISION (int_mode
)
5933 < GET_MODE_PRECISION (int_op0_mode
))
5934 && known_eq (subreg_lowpart_offset (int_mode
, int_op0_mode
),
5936 && HWI_COMPUTABLE_MODE_P (int_op0_mode
)
5937 && ((nonzero_bits (SUBREG_REG (x
), int_op0_mode
)
5938 & GET_MODE_MASK (int_mode
)) == 0)
5939 && !side_effects_p (SUBREG_REG (x
)))
5940 return CONST0_RTX (int_mode
);
5943 /* Don't change the mode of the MEM if that would change the meaning
5945 if (MEM_P (SUBREG_REG (x
))
5946 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5947 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5948 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5949 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5951 /* Note that we cannot do any narrowing for non-constants since
5952 we might have been counting on using the fact that some bits were
5953 zero. We now do this in the SET. */
5958 temp
= expand_compound_operation (XEXP (x
, 0));
5960 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5961 replaced by (lshiftrt X C). This will convert
5962 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5964 if (GET_CODE (temp
) == ASHIFTRT
5965 && CONST_INT_P (XEXP (temp
, 1))
5966 && INTVAL (XEXP (temp
, 1)) == GET_MODE_UNIT_PRECISION (mode
) - 1)
5967 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5968 INTVAL (XEXP (temp
, 1)));
5970 /* If X has only a single bit that might be nonzero, say, bit I, convert
5971 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5972 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5973 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5974 or a SUBREG of one since we'd be making the expression more
5975 complex if it was just a register. */
5978 && ! (GET_CODE (temp
) == SUBREG
5979 && REG_P (SUBREG_REG (temp
)))
5980 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
5981 && (i
= exact_log2 (nonzero_bits (temp
, int_mode
))) >= 0)
5983 rtx temp1
= simplify_shift_const
5984 (NULL_RTX
, ASHIFTRT
, int_mode
,
5985 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
, temp
,
5986 GET_MODE_PRECISION (int_mode
) - 1 - i
),
5987 GET_MODE_PRECISION (int_mode
) - 1 - i
);
5989 /* If all we did was surround TEMP with the two shifts, we
5990 haven't improved anything, so don't use it. Otherwise,
5991 we are better off with TEMP1. */
5992 if (GET_CODE (temp1
) != ASHIFTRT
5993 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5994 || XEXP (XEXP (temp1
, 0), 0) != temp
)
6000 /* We can't handle truncation to a partial integer mode here
6001 because we don't know the real bitsize of the partial
6003 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
6006 if (HWI_COMPUTABLE_MODE_P (mode
))
6008 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
6009 GET_MODE_MASK (mode
), false));
6011 /* We can truncate a constant value and return it. */
6014 if (poly_int_rtx_p (XEXP (x
, 0), &c
))
6015 return gen_int_mode (c
, mode
);
6018 /* Similarly to what we do in simplify-rtx.cc, a truncate of a register
6019 whose value is a comparison can be replaced with a subreg if
6020 STORE_FLAG_VALUE permits. */
6021 if (HWI_COMPUTABLE_MODE_P (mode
)
6022 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
6023 && (temp
= get_last_value (XEXP (x
, 0)))
6024 && COMPARISON_P (temp
)
6025 && TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (XEXP (x
, 0))))
6026 return gen_lowpart (mode
, XEXP (x
, 0));
6030 /* (const (const X)) can become (const X). Do it this way rather than
6031 returning the inner CONST since CONST can be shared with a
6033 if (GET_CODE (XEXP (x
, 0)) == CONST
)
6034 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
6038 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6039 can add in an offset. find_split_point will split this address up
6040 again if it doesn't match. */
6041 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
6042 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
6047 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6048 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6049 bit-field and can be replaced by either a sign_extend or a
6050 sign_extract. The `and' may be a zero_extend and the two
6051 <c>, -<c> constants may be reversed. */
6052 if (GET_CODE (XEXP (x
, 0)) == XOR
6053 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6054 && CONST_INT_P (XEXP (x
, 1))
6055 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
6056 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
6057 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
6058 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
6059 && HWI_COMPUTABLE_MODE_P (int_mode
)
6060 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
6061 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
6062 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
6063 == (HOST_WIDE_INT_1U
<< (i
+ 1)) - 1))
6064 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
6065 && known_eq ((GET_MODE_PRECISION
6066 (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))),
6067 (unsigned int) i
+ 1))))
6068 return simplify_shift_const
6069 (NULL_RTX
, ASHIFTRT
, int_mode
,
6070 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6071 XEXP (XEXP (XEXP (x
, 0), 0), 0),
6072 GET_MODE_PRECISION (int_mode
) - (i
+ 1)),
6073 GET_MODE_PRECISION (int_mode
) - (i
+ 1));
6075 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6076 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6077 the bitsize of the mode - 1. This allows simplification of
6078 "a = (b & 8) == 0;" */
6079 if (XEXP (x
, 1) == constm1_rtx
6080 && !REG_P (XEXP (x
, 0))
6081 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
6082 && REG_P (SUBREG_REG (XEXP (x
, 0))))
6083 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6084 && nonzero_bits (XEXP (x
, 0), int_mode
) == 1)
6085 return simplify_shift_const
6086 (NULL_RTX
, ASHIFTRT
, int_mode
,
6087 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6088 gen_rtx_XOR (int_mode
, XEXP (x
, 0),
6090 GET_MODE_PRECISION (int_mode
) - 1),
6091 GET_MODE_PRECISION (int_mode
) - 1);
6093 /* If we are adding two things that have no bits in common, convert
6094 the addition into an IOR. This will often be further simplified,
6095 for example in cases like ((a & 1) + (a & 2)), which can
6098 if (HWI_COMPUTABLE_MODE_P (mode
)
6099 && (nonzero_bits (XEXP (x
, 0), mode
)
6100 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
6102 /* Try to simplify the expression further. */
6103 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
6104 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, false);
6106 /* If we could, great. If not, do not go ahead with the IOR
6107 replacement, since PLUS appears in many special purpose
6108 address arithmetic instructions. */
6109 if (GET_CODE (temp
) != CLOBBER
6110 && (GET_CODE (temp
) != IOR
6111 || ((XEXP (temp
, 0) != XEXP (x
, 0)
6112 || XEXP (temp
, 1) != XEXP (x
, 1))
6113 && (XEXP (temp
, 0) != XEXP (x
, 1)
6114 || XEXP (temp
, 1) != XEXP (x
, 0)))))
6118 /* Canonicalize x + x into x << 1. */
6119 if (GET_MODE_CLASS (mode
) == MODE_INT
6120 && rtx_equal_p (XEXP (x
, 0), XEXP (x
, 1))
6121 && !side_effects_p (XEXP (x
, 0)))
6122 return simplify_gen_binary (ASHIFT
, mode
, XEXP (x
, 0), const1_rtx
);
6127 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6128 (and <foo> (const_int pow2-1)) */
6129 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
6130 && GET_CODE (XEXP (x
, 1)) == AND
6131 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
6132 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x
, 1), 1)))
6133 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
6134 return simplify_and_const_int (NULL_RTX
, int_mode
, XEXP (x
, 0),
6135 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
6139 /* If we have (mult (plus A B) C), apply the distributive law and then
6140 the inverse distributive law to see if things simplify. This
6141 occurs mostly in addresses, often when unrolling loops. */
6143 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
6145 rtx result
= distribute_and_simplify_rtx (x
, 0);
6150 /* Try simplify a*(b/c) as (a*b)/c. */
6151 if (FLOAT_MODE_P (mode
) && flag_associative_math
6152 && GET_CODE (XEXP (x
, 0)) == DIV
)
6154 rtx tem
= simplify_binary_operation (MULT
, mode
,
6155 XEXP (XEXP (x
, 0), 0),
6158 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
6163 /* If this is a divide by a power of two, treat it as a shift if
6164 its first operand is a shift. */
6165 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
6166 && CONST_INT_P (XEXP (x
, 1))
6167 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
6168 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
6169 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6170 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
6171 || GET_CODE (XEXP (x
, 0)) == ROTATE
6172 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
6173 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, int_mode
,
6178 case GT
: case GTU
: case GE
: case GEU
:
6179 case LT
: case LTU
: case LE
: case LEU
:
6180 case UNEQ
: case LTGT
:
6181 case UNGT
: case UNGE
:
6182 case UNLT
: case UNLE
:
6183 case UNORDERED
: case ORDERED
:
6184 /* If the first operand is a condition code, we can't do anything
6186 if (GET_CODE (XEXP (x
, 0)) == COMPARE
6187 || GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
)
6189 rtx op0
= XEXP (x
, 0);
6190 rtx op1
= XEXP (x
, 1);
6191 enum rtx_code new_code
;
6193 if (GET_CODE (op0
) == COMPARE
)
6194 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
6196 /* Simplify our comparison, if possible. */
6197 new_code
= simplify_comparison (code
, &op0
, &op1
);
6199 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6200 if only the low-order bit is possibly nonzero in X (such as when
6201 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6202 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6203 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6206 Remove any ZERO_EXTRACT we made when thinking this was a
6207 comparison. It may now be simpler to use, e.g., an AND. If a
6208 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6209 the call to make_compound_operation in the SET case.
6211 Don't apply these optimizations if the caller would
6212 prefer a comparison rather than a value.
6213 E.g., for the condition in an IF_THEN_ELSE most targets need
6214 an explicit comparison. */
6219 else if (STORE_FLAG_VALUE
== 1
6221 && is_int_mode (mode
, &int_mode
)
6222 && op1
== const0_rtx
6223 && int_mode
== GET_MODE (op0
)
6224 && nonzero_bits (op0
, int_mode
) == 1)
6225 return gen_lowpart (int_mode
,
6226 expand_compound_operation (op0
));
6228 else if (STORE_FLAG_VALUE
== 1
6230 && is_int_mode (mode
, &int_mode
)
6231 && op1
== const0_rtx
6232 && int_mode
== GET_MODE (op0
)
6233 && (num_sign_bit_copies (op0
, int_mode
)
6234 == GET_MODE_PRECISION (int_mode
)))
6236 op0
= expand_compound_operation (op0
);
6237 return simplify_gen_unary (NEG
, int_mode
,
6238 gen_lowpart (int_mode
, op0
),
6242 else if (STORE_FLAG_VALUE
== 1
6244 && is_int_mode (mode
, &int_mode
)
6245 && op1
== const0_rtx
6246 && int_mode
== GET_MODE (op0
)
6247 && nonzero_bits (op0
, int_mode
) == 1)
6249 op0
= expand_compound_operation (op0
);
6250 return simplify_gen_binary (XOR
, int_mode
,
6251 gen_lowpart (int_mode
, op0
),
6255 else if (STORE_FLAG_VALUE
== 1
6257 && is_int_mode (mode
, &int_mode
)
6258 && op1
== const0_rtx
6259 && int_mode
== GET_MODE (op0
)
6260 && (num_sign_bit_copies (op0
, int_mode
)
6261 == GET_MODE_PRECISION (int_mode
)))
6263 op0
= expand_compound_operation (op0
);
6264 return plus_constant (int_mode
, gen_lowpart (int_mode
, op0
), 1);
6267 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6272 else if (STORE_FLAG_VALUE
== -1
6274 && is_int_mode (mode
, &int_mode
)
6275 && op1
== const0_rtx
6276 && int_mode
== GET_MODE (op0
)
6277 && (num_sign_bit_copies (op0
, int_mode
)
6278 == GET_MODE_PRECISION (int_mode
)))
6279 return gen_lowpart (int_mode
, expand_compound_operation (op0
));
6281 else if (STORE_FLAG_VALUE
== -1
6283 && is_int_mode (mode
, &int_mode
)
6284 && op1
== const0_rtx
6285 && int_mode
== GET_MODE (op0
)
6286 && nonzero_bits (op0
, int_mode
) == 1)
6288 op0
= expand_compound_operation (op0
);
6289 return simplify_gen_unary (NEG
, int_mode
,
6290 gen_lowpart (int_mode
, op0
),
6294 else if (STORE_FLAG_VALUE
== -1
6296 && is_int_mode (mode
, &int_mode
)
6297 && op1
== const0_rtx
6298 && int_mode
== GET_MODE (op0
)
6299 && (num_sign_bit_copies (op0
, int_mode
)
6300 == GET_MODE_PRECISION (int_mode
)))
6302 op0
= expand_compound_operation (op0
);
6303 return simplify_gen_unary (NOT
, int_mode
,
6304 gen_lowpart (int_mode
, op0
),
6308 /* If X is 0/1, (eq X 0) is X-1. */
6309 else if (STORE_FLAG_VALUE
== -1
6311 && is_int_mode (mode
, &int_mode
)
6312 && op1
== const0_rtx
6313 && int_mode
== GET_MODE (op0
)
6314 && nonzero_bits (op0
, int_mode
) == 1)
6316 op0
= expand_compound_operation (op0
);
6317 return plus_constant (int_mode
, gen_lowpart (int_mode
, op0
), -1);
6320 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6321 one bit that might be nonzero, we can convert (ne x 0) to
6322 (ashift x c) where C puts the bit in the sign bit. Remove any
6323 AND with STORE_FLAG_VALUE when we are done, since we are only
6324 going to test the sign bit. */
6326 && is_int_mode (mode
, &int_mode
)
6327 && HWI_COMPUTABLE_MODE_P (int_mode
)
6328 && val_signbit_p (int_mode
, STORE_FLAG_VALUE
)
6329 && op1
== const0_rtx
6330 && int_mode
== GET_MODE (op0
)
6331 && (i
= exact_log2 (nonzero_bits (op0
, int_mode
))) >= 0)
6333 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6334 expand_compound_operation (op0
),
6335 GET_MODE_PRECISION (int_mode
) - 1 - i
);
6336 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6342 /* If the code changed, return a whole new comparison.
6343 We also need to avoid using SUBST in cases where
6344 simplify_comparison has widened a comparison with a CONST_INT,
6345 since in that case the wider CONST_INT may fail the sanity
6346 checks in do_SUBST. */
6347 if (new_code
!= code
6348 || (CONST_INT_P (op1
)
6349 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6350 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6351 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6353 /* Otherwise, keep this operation, but maybe change its operands.
6354 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6355 SUBST (XEXP (x
, 0), op0
);
6356 SUBST (XEXP (x
, 1), op1
);
6361 return simplify_if_then_else (x
);
6367 /* If we are processing SET_DEST, we are done. */
6371 return expand_compound_operation (x
);
6374 return simplify_set (x
);
6378 return simplify_logical (x
);
6385 /* If this is a shift by a constant amount, simplify it. */
6386 if (CONST_INT_P (XEXP (x
, 1)))
6387 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6388 INTVAL (XEXP (x
, 1)));
6390 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6392 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6394 << exact_log2 (GET_MODE_UNIT_BITSIZE
6395 (GET_MODE (x
)))) - 1, false));
6399 rtx trueop0
= XEXP (x
, 0);
6400 mode
= GET_MODE (trueop0
);
6401 rtx trueop1
= XEXP (x
, 1);
6402 /* If we select a low-part subreg, return that. */
6403 if (vec_series_lowpart_p (GET_MODE (x
), mode
, trueop1
))
6405 rtx new_rtx
= lowpart_subreg (GET_MODE (x
), trueop0
, mode
);
6406 if (new_rtx
!= NULL_RTX
)
6418 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6421 simplify_if_then_else (rtx x
)
6423 machine_mode mode
= GET_MODE (x
);
6424 rtx cond
= XEXP (x
, 0);
6425 rtx true_rtx
= XEXP (x
, 1);
6426 rtx false_rtx
= XEXP (x
, 2);
6427 enum rtx_code true_code
= GET_CODE (cond
);
6428 bool comparison_p
= COMPARISON_P (cond
);
6431 enum rtx_code false_code
;
6433 scalar_int_mode int_mode
, inner_mode
;
6435 /* Simplify storing of the truth value. */
6436 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6437 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6438 XEXP (cond
, 0), XEXP (cond
, 1));
6440 /* Also when the truth value has to be reversed. */
6442 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6443 && (reversed
= reversed_comparison (cond
, mode
)))
6446 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6447 in it is being compared against certain values. Get the true and false
6448 comparisons and see if that says anything about the value of each arm. */
6451 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6453 && REG_P (XEXP (cond
, 0)))
6456 rtx from
= XEXP (cond
, 0);
6457 rtx true_val
= XEXP (cond
, 1);
6458 rtx false_val
= true_val
;
6459 bool swapped
= false;
6461 /* If FALSE_CODE is EQ, swap the codes and arms. */
6463 if (false_code
== EQ
)
6465 swapped
= true, true_code
= EQ
, false_code
= NE
;
6466 std::swap (true_rtx
, false_rtx
);
6469 scalar_int_mode from_mode
;
6470 if (is_a
<scalar_int_mode
> (GET_MODE (from
), &from_mode
))
6472 /* If we are comparing against zero and the expression being
6473 tested has only a single bit that might be nonzero, that is
6474 its value when it is not equal to zero. Similarly if it is
6475 known to be -1 or 0. */
6477 && true_val
== const0_rtx
6478 && pow2p_hwi (nzb
= nonzero_bits (from
, from_mode
)))
6481 false_val
= gen_int_mode (nzb
, from_mode
);
6483 else if (true_code
== EQ
6484 && true_val
== const0_rtx
6485 && (num_sign_bit_copies (from
, from_mode
)
6486 == GET_MODE_PRECISION (from_mode
)))
6489 false_val
= constm1_rtx
;
6493 /* Now simplify an arm if we know the value of the register in the
6494 branch and it is used in the arm. Be careful due to the potential
6495 of locally-shared RTL. */
6497 if (reg_mentioned_p (from
, true_rtx
))
6498 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6500 pc_rtx
, pc_rtx
, false, false, false);
6501 if (reg_mentioned_p (from
, false_rtx
))
6502 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6504 pc_rtx
, pc_rtx
, false, false, false);
6506 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6507 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6509 true_rtx
= XEXP (x
, 1);
6510 false_rtx
= XEXP (x
, 2);
6511 true_code
= GET_CODE (cond
);
6514 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6515 reversed, do so to avoid needing two sets of patterns for
6516 subtract-and-branch insns. Similarly if we have a constant in the true
6517 arm, the false arm is the same as the first operand of the comparison, or
6518 the false arm is more complicated than the true arm. */
6521 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6522 && (true_rtx
== pc_rtx
6523 || (CONSTANT_P (true_rtx
)
6524 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6525 || true_rtx
== const0_rtx
6526 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6527 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6528 && !OBJECT_P (false_rtx
))
6529 || reg_mentioned_p (true_rtx
, false_rtx
)
6530 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6532 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6533 SUBST (XEXP (x
, 1), false_rtx
);
6534 SUBST (XEXP (x
, 2), true_rtx
);
6536 std::swap (true_rtx
, false_rtx
);
6539 /* It is possible that the conditional has been simplified out. */
6540 true_code
= GET_CODE (cond
);
6541 comparison_p
= COMPARISON_P (cond
);
6544 /* If the two arms are identical, we don't need the comparison. */
6546 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6549 /* Convert a == b ? b : a to "a". */
6550 if (true_code
== EQ
&& ! side_effects_p (cond
)
6551 && !HONOR_NANS (mode
)
6552 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6553 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6555 else if (true_code
== NE
&& ! side_effects_p (cond
)
6556 && !HONOR_NANS (mode
)
6557 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6558 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6561 /* Look for cases where we have (abs x) or (neg (abs X)). */
6563 if (GET_MODE_CLASS (mode
) == MODE_INT
6565 && XEXP (cond
, 1) == const0_rtx
6566 && GET_CODE (false_rtx
) == NEG
6567 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6568 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6569 && ! side_effects_p (true_rtx
))
6574 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6578 simplify_gen_unary (NEG
, mode
,
6579 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6585 /* Look for MIN or MAX. */
6587 if ((! FLOAT_MODE_P (mode
)
6588 || (flag_unsafe_math_optimizations
6589 && !HONOR_NANS (mode
)
6590 && !HONOR_SIGNED_ZEROS (mode
)))
6592 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6593 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6594 && ! side_effects_p (cond
))
6599 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6602 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6605 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6608 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6613 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6614 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6615 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6616 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6617 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6618 neither 1 or -1, but it isn't worth checking for. */
6620 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6622 && is_int_mode (mode
, &int_mode
)
6623 && ! side_effects_p (x
))
6625 rtx t
= make_compound_operation (true_rtx
, SET
);
6626 rtx f
= make_compound_operation (false_rtx
, SET
);
6627 rtx cond_op0
= XEXP (cond
, 0);
6628 rtx cond_op1
= XEXP (cond
, 1);
6629 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6630 scalar_int_mode m
= int_mode
;
6631 rtx z
= 0, c1
= NULL_RTX
;
6633 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6634 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6635 || GET_CODE (t
) == ASHIFT
6636 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6637 && rtx_equal_p (XEXP (t
, 0), f
))
6638 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6640 /* If an identity-zero op is commutative, check whether there
6641 would be a match if we swapped the operands. */
6642 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6643 || GET_CODE (t
) == XOR
)
6644 && rtx_equal_p (XEXP (t
, 1), f
))
6645 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6646 else if (GET_CODE (t
) == SIGN_EXTEND
6647 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6648 && (GET_CODE (XEXP (t
, 0)) == PLUS
6649 || GET_CODE (XEXP (t
, 0)) == MINUS
6650 || GET_CODE (XEXP (t
, 0)) == IOR
6651 || GET_CODE (XEXP (t
, 0)) == XOR
6652 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6653 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6654 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6655 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6656 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6657 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6658 && (num_sign_bit_copies (f
, GET_MODE (f
))
6660 (GET_MODE_PRECISION (int_mode
)
6661 - GET_MODE_PRECISION (inner_mode
))))
6663 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6664 extend_op
= SIGN_EXTEND
;
6667 else if (GET_CODE (t
) == SIGN_EXTEND
6668 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6669 && (GET_CODE (XEXP (t
, 0)) == PLUS
6670 || GET_CODE (XEXP (t
, 0)) == IOR
6671 || GET_CODE (XEXP (t
, 0)) == XOR
)
6672 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6673 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6674 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6675 && (num_sign_bit_copies (f
, GET_MODE (f
))
6677 (GET_MODE_PRECISION (int_mode
)
6678 - GET_MODE_PRECISION (inner_mode
))))
6680 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6681 extend_op
= SIGN_EXTEND
;
6684 else if (GET_CODE (t
) == ZERO_EXTEND
6685 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6686 && (GET_CODE (XEXP (t
, 0)) == PLUS
6687 || GET_CODE (XEXP (t
, 0)) == MINUS
6688 || GET_CODE (XEXP (t
, 0)) == IOR
6689 || GET_CODE (XEXP (t
, 0)) == XOR
6690 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6691 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6692 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6693 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6694 && HWI_COMPUTABLE_MODE_P (int_mode
)
6695 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6696 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6697 && ((nonzero_bits (f
, GET_MODE (f
))
6698 & ~GET_MODE_MASK (inner_mode
))
6701 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6702 extend_op
= ZERO_EXTEND
;
6705 else if (GET_CODE (t
) == ZERO_EXTEND
6706 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (t
, 0)), &inner_mode
)
6707 && (GET_CODE (XEXP (t
, 0)) == PLUS
6708 || GET_CODE (XEXP (t
, 0)) == IOR
6709 || GET_CODE (XEXP (t
, 0)) == XOR
)
6710 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6711 && HWI_COMPUTABLE_MODE_P (int_mode
)
6712 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6713 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6714 && ((nonzero_bits (f
, GET_MODE (f
))
6715 & ~GET_MODE_MASK (inner_mode
))
6718 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6719 extend_op
= ZERO_EXTEND
;
6725 machine_mode cm
= m
;
6726 if ((op
== ASHIFT
|| op
== LSHIFTRT
|| op
== ASHIFTRT
)
6727 && GET_MODE (c1
) != VOIDmode
)
6729 temp
= subst (simplify_gen_relational (true_code
, cm
, VOIDmode
,
6730 cond_op0
, cond_op1
),
6731 pc_rtx
, pc_rtx
, false, false, false);
6732 temp
= simplify_gen_binary (MULT
, cm
, temp
,
6733 simplify_gen_binary (MULT
, cm
, c1
,
6735 temp
= subst (temp
, pc_rtx
, pc_rtx
, false, false, false);
6736 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6738 if (extend_op
!= UNKNOWN
)
6739 temp
= simplify_gen_unary (extend_op
, int_mode
, temp
, m
);
6745 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6746 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6747 negation of a single bit, we can convert this operation to a shift. We
6748 can actually do this more generally, but it doesn't seem worth it. */
6751 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6752 && XEXP (cond
, 1) == const0_rtx
6753 && false_rtx
== const0_rtx
6754 && CONST_INT_P (true_rtx
)
6755 && ((nonzero_bits (XEXP (cond
, 0), int_mode
) == 1
6756 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6757 || ((num_sign_bit_copies (XEXP (cond
, 0), int_mode
)
6758 == GET_MODE_PRECISION (int_mode
))
6759 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6761 simplify_shift_const (NULL_RTX
, ASHIFT
, int_mode
,
6762 gen_lowpart (int_mode
, XEXP (cond
, 0)), i
);
6764 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6765 non-zero bit in A is C1. */
6766 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6767 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6768 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
6769 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (cond
, 0)), &inner_mode
)
6770 && (UINTVAL (true_rtx
) & GET_MODE_MASK (int_mode
))
6771 == nonzero_bits (XEXP (cond
, 0), inner_mode
)
6772 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (int_mode
))) >= 0)
6774 rtx val
= XEXP (cond
, 0);
6775 if (inner_mode
== int_mode
)
6777 else if (GET_MODE_PRECISION (inner_mode
) < GET_MODE_PRECISION (int_mode
))
6778 return simplify_gen_unary (ZERO_EXTEND
, int_mode
, val
, inner_mode
);
6784 /* Simplify X, a SET expression. Return the new expression. */
6787 simplify_set (rtx x
)
6789 rtx src
= SET_SRC (x
);
6790 rtx dest
= SET_DEST (x
);
6792 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6793 rtx_insn
*other_insn
;
6795 scalar_int_mode int_mode
;
6797 /* (set (pc) (return)) gets written as (return). */
6798 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6801 /* Now that we know for sure which bits of SRC we are using, see if we can
6802 simplify the expression for the object knowing that we only need the
6805 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6807 src
= force_to_mode (src
, mode
, HOST_WIDE_INT_M1U
, false);
6808 SUBST (SET_SRC (x
), src
);
6811 /* If the source is a COMPARE, look for the use of the comparison result
6812 and try to simplify it unless we already have used undobuf.other_insn. */
6813 if ((GET_MODE_CLASS (mode
) == MODE_CC
|| GET_CODE (src
) == COMPARE
)
6814 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6815 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6816 && COMPARISON_P (*cc_use
)
6817 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6819 enum rtx_code old_code
= GET_CODE (*cc_use
);
6820 enum rtx_code new_code
;
6822 bool other_changed
= false;
6823 rtx inner_compare
= NULL_RTX
;
6824 machine_mode compare_mode
= GET_MODE (dest
);
6826 if (GET_CODE (src
) == COMPARE
)
6828 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6829 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6831 inner_compare
= op0
;
6832 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6836 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6838 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6841 new_code
= old_code
;
6842 else if (!CONSTANT_P (tmp
))
6844 new_code
= GET_CODE (tmp
);
6845 op0
= XEXP (tmp
, 0);
6846 op1
= XEXP (tmp
, 1);
6850 rtx pat
= PATTERN (other_insn
);
6851 undobuf
.other_insn
= other_insn
;
6852 SUBST (*cc_use
, tmp
);
6854 /* Attempt to simplify CC user. */
6855 if (GET_CODE (pat
) == SET
)
6857 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6858 if (new_rtx
!= NULL_RTX
)
6859 SUBST (SET_SRC (pat
), new_rtx
);
6862 /* Convert X into a no-op move. */
6863 SUBST (SET_DEST (x
), pc_rtx
);
6864 SUBST (SET_SRC (x
), pc_rtx
);
6868 /* Simplify our comparison, if possible. */
6869 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6871 #ifdef SELECT_CC_MODE
6872 /* If this machine has CC modes other than CCmode, check to see if we
6873 need to use a different CC mode here. */
6874 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6875 compare_mode
= GET_MODE (op0
);
6876 else if (inner_compare
6877 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6878 && new_code
== old_code
6879 && op0
== XEXP (inner_compare
, 0)
6880 && op1
== XEXP (inner_compare
, 1))
6881 compare_mode
= GET_MODE (inner_compare
);
6883 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6885 /* If the mode changed, we have to change SET_DEST, the mode in the
6886 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6887 a hard register, just build new versions with the proper mode. If it
6888 is a pseudo, we lose unless it is only time we set the pseudo, in
6889 which case we can safely change its mode. */
6890 if (compare_mode
!= GET_MODE (dest
))
6892 if (can_change_dest_mode (dest
, 0, compare_mode
))
6894 unsigned int regno
= REGNO (dest
);
6897 if (regno
< FIRST_PSEUDO_REGISTER
)
6898 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6901 subst_mode (regno
, compare_mode
);
6902 new_dest
= regno_reg_rtx
[regno
];
6905 SUBST (SET_DEST (x
), new_dest
);
6906 SUBST (XEXP (*cc_use
, 0), new_dest
);
6907 other_changed
= true;
6912 #endif /* SELECT_CC_MODE */
6914 /* If the code changed, we have to build a new comparison in
6915 undobuf.other_insn. */
6916 if (new_code
!= old_code
)
6918 bool other_changed_previously
= other_changed
;
6919 unsigned HOST_WIDE_INT mask
;
6920 rtx old_cc_use
= *cc_use
;
6922 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6924 other_changed
= true;
6926 /* If the only change we made was to change an EQ into an NE or
6927 vice versa, OP0 has only one bit that might be nonzero, and OP1
6928 is zero, check if changing the user of the condition code will
6929 produce a valid insn. If it won't, we can keep the original code
6930 in that insn by surrounding our operation with an XOR. */
6932 if (((old_code
== NE
&& new_code
== EQ
)
6933 || (old_code
== EQ
&& new_code
== NE
))
6934 && ! other_changed_previously
&& op1
== const0_rtx
6935 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6936 && pow2p_hwi (mask
= nonzero_bits (op0
, GET_MODE (op0
))))
6938 rtx pat
= PATTERN (other_insn
), note
= 0;
6940 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6941 && ! check_asm_operands (pat
)))
6943 *cc_use
= old_cc_use
;
6944 other_changed
= false;
6946 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6954 undobuf
.other_insn
= other_insn
;
6956 /* Don't generate a compare of a CC with 0, just use that CC. */
6957 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6959 SUBST (SET_SRC (x
), op0
);
6962 /* Otherwise, if we didn't previously have the same COMPARE we
6963 want, create it from scratch. */
6964 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
6965 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6967 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6973 /* Get SET_SRC in a form where we have placed back any
6974 compound expressions. Then do the checks below. */
6975 src
= make_compound_operation (src
, SET
);
6976 SUBST (SET_SRC (x
), src
);
6979 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6980 and X being a REG or (subreg (reg)), we may be able to convert this to
6981 (set (subreg:m2 x) (op)).
6983 We can always do this if M1 is narrower than M2 because that means that
6984 we only care about the low bits of the result.
6986 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6987 perform a narrower operation than requested since the high-order bits will
6988 be undefined. On machine where it is defined, this transformation is safe
6989 as long as M1 and M2 have the same number of words. */
6991 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6992 && !OBJECT_P (SUBREG_REG (src
))
6993 && (known_equal_after_align_up
6994 (GET_MODE_SIZE (GET_MODE (src
)),
6995 GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))),
6997 && (WORD_REGISTER_OPERATIONS
|| !paradoxical_subreg_p (src
))
6998 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6999 && !REG_CAN_CHANGE_MODE_P (REGNO (dest
),
7000 GET_MODE (SUBREG_REG (src
)),
7003 || (GET_CODE (dest
) == SUBREG
7004 && REG_P (SUBREG_REG (dest
)))))
7006 SUBST (SET_DEST (x
),
7007 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
7009 SUBST (SET_SRC (x
), SUBREG_REG (src
));
7011 src
= SET_SRC (x
), dest
= SET_DEST (x
);
7014 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
7015 would require a paradoxical subreg. Replace the subreg with a
7016 zero_extend to avoid the reload that would otherwise be required.
7017 Don't do this unless we have a scalar integer mode, otherwise the
7018 transformation is incorrect. */
7020 enum rtx_code extend_op
;
7021 if (paradoxical_subreg_p (src
)
7022 && MEM_P (SUBREG_REG (src
))
7023 && SCALAR_INT_MODE_P (GET_MODE (src
))
7024 && (extend_op
= load_extend_op (GET_MODE (SUBREG_REG (src
)))) != UNKNOWN
)
7027 gen_rtx_fmt_e (extend_op
, GET_MODE (src
), SUBREG_REG (src
)));
7032 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7033 are comparing an item known to be 0 or -1 against 0, use a logical
7034 operation instead. Check for one of the arms being an IOR of the other
7035 arm with some value. We compute three terms to be IOR'ed together. In
7036 practice, at most two will be nonzero. Then we do the IOR's. */
7038 if (GET_CODE (dest
) != PC
7039 && GET_CODE (src
) == IF_THEN_ELSE
7040 && is_int_mode (GET_MODE (src
), &int_mode
)
7041 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
7042 && XEXP (XEXP (src
, 0), 1) == const0_rtx
7043 && int_mode
== GET_MODE (XEXP (XEXP (src
, 0), 0))
7044 && (!HAVE_conditional_move
7045 || ! can_conditionally_move_p (int_mode
))
7046 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0), int_mode
)
7047 == GET_MODE_PRECISION (int_mode
))
7048 && ! side_effects_p (src
))
7050 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
7051 ? XEXP (src
, 1) : XEXP (src
, 2));
7052 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
7053 ? XEXP (src
, 2) : XEXP (src
, 1));
7054 rtx term1
= const0_rtx
, term2
, term3
;
7056 if (GET_CODE (true_rtx
) == IOR
7057 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
7058 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
7059 else if (GET_CODE (true_rtx
) == IOR
7060 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
7061 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
7062 else if (GET_CODE (false_rtx
) == IOR
7063 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
7064 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
7065 else if (GET_CODE (false_rtx
) == IOR
7066 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
7067 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
7069 term2
= simplify_gen_binary (AND
, int_mode
,
7070 XEXP (XEXP (src
, 0), 0), true_rtx
);
7071 term3
= simplify_gen_binary (AND
, int_mode
,
7072 simplify_gen_unary (NOT
, int_mode
,
7073 XEXP (XEXP (src
, 0), 0),
7078 simplify_gen_binary (IOR
, int_mode
,
7079 simplify_gen_binary (IOR
, int_mode
,
7086 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7087 whole thing fail. */
7088 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
7090 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
7093 /* Convert this into a field assignment operation, if possible. */
7094 return make_field_assignment (x
);
7097 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7101 simplify_logical (rtx x
)
7103 rtx op0
= XEXP (x
, 0);
7104 rtx op1
= XEXP (x
, 1);
7105 scalar_int_mode mode
;
7107 switch (GET_CODE (x
))
7110 /* We can call simplify_and_const_int only if we don't lose
7111 any (sign) bits when converting INTVAL (op1) to
7112 "unsigned HOST_WIDE_INT". */
7113 if (is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
)
7114 && CONST_INT_P (op1
)
7115 && (HWI_COMPUTABLE_MODE_P (mode
)
7116 || INTVAL (op1
) > 0))
7118 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
7119 if (GET_CODE (x
) != AND
)
7126 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7127 apply the distributive law and then the inverse distributive
7128 law to see if things simplify. */
7129 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
7131 rtx result
= distribute_and_simplify_rtx (x
, 0);
7135 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
7137 rtx result
= distribute_and_simplify_rtx (x
, 1);
7144 /* If we have (ior (and A B) C), apply the distributive law and then
7145 the inverse distributive law to see if things simplify. */
7147 if (GET_CODE (op0
) == AND
)
7149 rtx result
= distribute_and_simplify_rtx (x
, 0);
7154 if (GET_CODE (op1
) == AND
)
7156 rtx result
= distribute_and_simplify_rtx (x
, 1);
7169 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7170 operations" because they can be replaced with two more basic operations.
7171 ZERO_EXTEND is also considered "compound" because it can be replaced with
7172 an AND operation, which is simpler, though only one operation.
7174 The function expand_compound_operation is called with an rtx expression
7175 and will convert it to the appropriate shifts and AND operations,
7176 simplifying at each stage.
7178 The function make_compound_operation is called to convert an expression
7179 consisting of shifts and ANDs into the equivalent compound expression.
7180 It is the inverse of this function, loosely speaking. */
7183 expand_compound_operation (rtx x
)
7185 unsigned HOST_WIDE_INT pos
= 0, len
;
7186 bool unsignedp
= false;
7187 unsigned int modewidth
;
7189 scalar_int_mode inner_mode
;
7191 switch (GET_CODE (x
))
7197 /* We can't necessarily use a const_int for a multiword mode;
7198 it depends on implicitly extending the value.
7199 Since we don't know the right way to extend it,
7200 we can't tell whether the implicit way is right.
7202 Even for a mode that is no wider than a const_int,
7203 we can't win, because we need to sign extend one of its bits through
7204 the rest of it, and we don't know which bit. */
7205 if (CONST_INT_P (XEXP (x
, 0)))
7208 /* Reject modes that aren't scalar integers because turning vector
7209 or complex modes into shifts causes problems. */
7210 if (!is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
7213 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7214 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7215 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7216 reloaded. If not for that, MEM's would very rarely be safe.
7218 Reject modes bigger than a word, because we might not be able
7219 to reference a two-register group starting with an arbitrary register
7220 (and currently gen_lowpart might crash for a SUBREG). */
7222 if (GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7225 len
= GET_MODE_PRECISION (inner_mode
);
7226 /* If the inner object has VOIDmode (the only way this can happen
7227 is if it is an ASM_OPERANDS), we can't do anything since we don't
7228 know how much masking to do. */
7240 /* If the operand is a CLOBBER, just return it. */
7241 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7244 if (!CONST_INT_P (XEXP (x
, 1))
7245 || !CONST_INT_P (XEXP (x
, 2)))
7248 /* Reject modes that aren't scalar integers because turning vector
7249 or complex modes into shifts causes problems. */
7250 if (!is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
))
7253 len
= INTVAL (XEXP (x
, 1));
7254 pos
= INTVAL (XEXP (x
, 2));
7256 /* This should stay within the object being extracted, fail otherwise. */
7257 if (len
+ pos
> GET_MODE_PRECISION (inner_mode
))
7260 if (BITS_BIG_ENDIAN
)
7261 pos
= GET_MODE_PRECISION (inner_mode
) - len
- pos
;
7269 /* We've rejected non-scalar operations by now. */
7270 scalar_int_mode mode
= as_a
<scalar_int_mode
> (GET_MODE (x
));
7272 /* Convert sign extension to zero extension, if we know that the high
7273 bit is not set, as this is easier to optimize. It will be converted
7274 back to cheaper alternative in make_extraction. */
7275 if (GET_CODE (x
) == SIGN_EXTEND
7276 && HWI_COMPUTABLE_MODE_P (mode
)
7277 && ((nonzero_bits (XEXP (x
, 0), inner_mode
)
7278 & ~(((unsigned HOST_WIDE_INT
) GET_MODE_MASK (inner_mode
)) >> 1))
7281 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, XEXP (x
, 0));
7282 rtx temp2
= expand_compound_operation (temp
);
7284 /* Make sure this is a profitable operation. */
7285 if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7286 > set_src_cost (temp2
, mode
, optimize_this_for_speed_p
))
7288 else if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7289 > set_src_cost (temp
, mode
, optimize_this_for_speed_p
))
7295 /* We can optimize some special cases of ZERO_EXTEND. */
7296 if (GET_CODE (x
) == ZERO_EXTEND
)
7298 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7299 know that the last value didn't have any inappropriate bits
7301 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7302 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
7303 && HWI_COMPUTABLE_MODE_P (mode
)
7304 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
)
7305 & ~GET_MODE_MASK (inner_mode
)) == 0)
7306 return XEXP (XEXP (x
, 0), 0);
7308 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7309 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7310 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
7311 && subreg_lowpart_p (XEXP (x
, 0))
7312 && HWI_COMPUTABLE_MODE_P (mode
)
7313 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), mode
)
7314 & ~GET_MODE_MASK (inner_mode
)) == 0)
7315 return SUBREG_REG (XEXP (x
, 0));
7317 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7318 is a comparison and STORE_FLAG_VALUE permits. This is like
7319 the first case, but it works even when MODE is larger
7320 than HOST_WIDE_INT. */
7321 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7322 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
7323 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7324 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
7325 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (inner_mode
)) == 0)
7326 return XEXP (XEXP (x
, 0), 0);
7328 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7329 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7330 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
7331 && subreg_lowpart_p (XEXP (x
, 0))
7332 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7333 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
7334 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (inner_mode
)) == 0)
7335 return SUBREG_REG (XEXP (x
, 0));
7339 /* If we reach here, we want to return a pair of shifts. The inner
7340 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7341 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7342 logical depending on the value of UNSIGNEDP.
7344 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7345 converted into an AND of a shift.
7347 We must check for the case where the left shift would have a negative
7348 count. This can happen in a case like (x >> 31) & 255 on machines
7349 that can't shift by a constant. On those machines, we would first
7350 combine the shift with the AND to produce a variable-position
7351 extraction. Then the constant of 31 would be substituted in
7352 to produce such a position. */
7354 modewidth
= GET_MODE_PRECISION (mode
);
7355 if (modewidth
>= pos
+ len
)
7357 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7358 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7360 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7361 tem
, modewidth
- pos
- len
);
7362 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7363 mode
, tem
, modewidth
- len
);
7365 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7367 tem
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, inner_mode
,
7369 tem
= gen_lowpart (mode
, tem
);
7370 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7372 tem
= simplify_and_const_int (NULL_RTX
, mode
, tem
,
7373 (HOST_WIDE_INT_1U
<< len
) - 1);
7376 /* Any other cases we can't handle. */
7379 /* If we couldn't do this for some reason, return the original
7381 if (GET_CODE (tem
) == CLOBBER
)
7387 /* X is a SET which contains an assignment of one object into
7388 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7389 or certain SUBREGS). If possible, convert it into a series of
7392 We half-heartedly support variable positions, but do not at all
7393 support variable lengths. */
7396 expand_field_assignment (const_rtx x
)
7399 rtx pos
; /* Always counts from low bit. */
7401 rtx mask
, cleared
, masked
;
7402 scalar_int_mode compute_mode
;
7404 /* Loop until we find something we can't simplify. */
7407 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7408 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7410 rtx x0
= XEXP (SET_DEST (x
), 0);
7411 if (!GET_MODE_PRECISION (GET_MODE (x0
)).is_constant (&len
))
7413 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7414 pos
= gen_int_mode (subreg_lsb (XEXP (SET_DEST (x
), 0)),
7417 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7418 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7420 inner
= XEXP (SET_DEST (x
), 0);
7421 if (!GET_MODE_PRECISION (GET_MODE (inner
)).is_constant (&inner_len
))
7424 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7425 pos
= XEXP (SET_DEST (x
), 2);
7427 /* A constant position should stay within the width of INNER. */
7428 if (CONST_INT_P (pos
) && INTVAL (pos
) + len
> inner_len
)
7431 if (BITS_BIG_ENDIAN
)
7433 if (CONST_INT_P (pos
))
7434 pos
= GEN_INT (inner_len
- len
- INTVAL (pos
));
7435 else if (GET_CODE (pos
) == MINUS
7436 && CONST_INT_P (XEXP (pos
, 1))
7437 && INTVAL (XEXP (pos
, 1)) == inner_len
- len
)
7438 /* If position is ADJUST - X, new position is X. */
7439 pos
= XEXP (pos
, 0);
7441 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7442 gen_int_mode (inner_len
- len
,
7448 /* If the destination is a subreg that overwrites the whole of the inner
7449 register, we can move the subreg to the source. */
7450 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7451 /* We need SUBREGs to compute nonzero_bits properly. */
7452 && nonzero_sign_valid
7453 && !read_modify_subreg_p (SET_DEST (x
)))
7455 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7457 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7464 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7465 inner
= SUBREG_REG (inner
);
7467 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7468 if (!is_a
<scalar_int_mode
> (GET_MODE (inner
), &compute_mode
))
7470 /* Don't do anything for vector or complex integral types. */
7471 if (! FLOAT_MODE_P (GET_MODE (inner
)))
7474 /* Try to find an integral mode to pun with. */
7475 if (!int_mode_for_size (GET_MODE_BITSIZE (GET_MODE (inner
)), 0)
7476 .exists (&compute_mode
))
7479 inner
= gen_lowpart (compute_mode
, inner
);
7482 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7483 if (len
>= HOST_BITS_PER_WIDE_INT
)
7486 /* Don't try to compute in too wide unsupported modes. */
7487 if (!targetm
.scalar_mode_supported_p (compute_mode
))
7490 /* gen_lowpart_for_combine returns CLOBBER on failure. */
7491 rtx lowpart
= gen_lowpart (compute_mode
, SET_SRC (x
));
7492 if (GET_CODE (lowpart
) == CLOBBER
)
7495 /* Now compute the equivalent expression. Make a copy of INNER
7496 for the SET_DEST in case it is a MEM into which we will substitute;
7497 we don't want shared RTL in that case. */
7498 mask
= gen_int_mode ((HOST_WIDE_INT_1U
<< len
) - 1,
7500 cleared
= simplify_gen_binary (AND
, compute_mode
,
7501 simplify_gen_unary (NOT
, compute_mode
,
7502 simplify_gen_binary (ASHIFT
,
7507 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7508 simplify_gen_binary (
7509 AND
, compute_mode
, lowpart
, mask
),
7512 x
= gen_rtx_SET (copy_rtx (inner
),
7513 simplify_gen_binary (IOR
, compute_mode
,
7520 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7521 it is an RTX that represents the (variable) starting position; otherwise,
7522 POS is the (constant) starting bit position. Both are counted from the LSB.
7524 UNSIGNEDP is true for an unsigned reference and zero for a signed one.
7526 IN_DEST is true if this is a reference in the destination of a SET.
7527 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7528 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7531 IN_COMPARE is true if we are in a COMPARE. This means that a
7532 ZERO_EXTRACT should be built even for bits starting at bit 0.
7534 MODE is the desired mode of the result (if IN_DEST == 0).
7536 The result is an RTX for the extraction or NULL_RTX if the target
7540 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7541 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, bool unsignedp
,
7542 bool in_dest
, bool in_compare
)
7544 /* This mode describes the size of the storage area
7545 to fetch the overall value from. Within that, we
7546 ignore the POS lowest bits, etc. */
7547 machine_mode is_mode
= GET_MODE (inner
);
7548 machine_mode inner_mode
;
7549 scalar_int_mode wanted_inner_mode
;
7550 scalar_int_mode wanted_inner_reg_mode
= word_mode
;
7551 scalar_int_mode pos_mode
= word_mode
;
7552 machine_mode extraction_mode
= word_mode
;
7554 rtx orig_pos_rtx
= pos_rtx
;
7555 HOST_WIDE_INT orig_pos
;
7557 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7558 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7560 if (GET_CODE (inner
) == SUBREG
7561 && subreg_lowpart_p (inner
)
7562 && (paradoxical_subreg_p (inner
)
7563 /* If trying or potentionally trying to extract
7564 bits outside of is_mode, don't look through
7565 non-paradoxical SUBREGs. See PR82192. */
7566 || (pos_rtx
== NULL_RTX
7567 && known_le (pos
+ len
, GET_MODE_PRECISION (is_mode
)))))
7569 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7570 consider just the QI as the memory to extract from.
7571 The subreg adds or removes high bits; its mode is
7572 irrelevant to the meaning of this extraction,
7573 since POS and LEN count from the lsb. */
7574 if (MEM_P (SUBREG_REG (inner
)))
7575 is_mode
= GET_MODE (SUBREG_REG (inner
));
7576 inner
= SUBREG_REG (inner
);
7578 else if (GET_CODE (inner
) == ASHIFT
7579 && CONST_INT_P (XEXP (inner
, 1))
7580 && pos_rtx
== 0 && pos
== 0
7581 && len
> UINTVAL (XEXP (inner
, 1)))
7583 /* We're extracting the least significant bits of an rtx
7584 (ashift X (const_int C)), where LEN > C. Extract the
7585 least significant (LEN - C) bits of X, giving an rtx
7586 whose mode is MODE, then shift it left C times. */
7587 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7588 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7589 unsignedp
, in_dest
, in_compare
);
7591 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7593 else if (GET_CODE (inner
) == MULT
7594 && CONST_INT_P (XEXP (inner
, 1))
7595 && pos_rtx
== 0 && pos
== 0)
7597 /* We're extracting the least significant bits of an rtx
7598 (mult X (const_int 2^C)), where LEN > C. Extract the
7599 least significant (LEN - C) bits of X, giving an rtx
7600 whose mode is MODE, then multiply it by 2^C. */
7601 const HOST_WIDE_INT shift_amt
= exact_log2 (INTVAL (XEXP (inner
, 1)));
7602 if (IN_RANGE (shift_amt
, 1, len
- 1))
7604 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7605 0, 0, len
- shift_amt
,
7606 unsignedp
, in_dest
, in_compare
);
7608 return gen_rtx_MULT (mode
, new_rtx
, XEXP (inner
, 1));
7611 else if (GET_CODE (inner
) == TRUNCATE
7612 /* If trying or potentionally trying to extract
7613 bits outside of is_mode, don't look through
7614 TRUNCATE. See PR82192. */
7615 && pos_rtx
== NULL_RTX
7616 && known_le (pos
+ len
, GET_MODE_PRECISION (is_mode
)))
7617 inner
= XEXP (inner
, 0);
7619 inner_mode
= GET_MODE (inner
);
7621 /* See if this can be done without an extraction. We never can if the
7622 width of the field is not the same as that of some integer mode. For
7623 registers, we can only avoid the extraction if the position is at the
7624 low-order bit and this is either not in the destination or we have the
7625 appropriate STRICT_LOW_PART operation available.
7627 For MEM, we can avoid an extract if the field starts on an appropriate
7628 boundary and we can change the mode of the memory reference. */
7630 scalar_int_mode tmode
;
7631 if (int_mode_for_size (len
, 1).exists (&tmode
)
7632 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7634 && (pos
== 0 || REG_P (inner
))
7635 && (inner_mode
== tmode
7637 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7638 || reg_truncated_to_mode (tmode
, inner
))
7641 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7642 || (MEM_P (inner
) && pos_rtx
== 0
7644 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7645 : BITS_PER_UNIT
)) == 0
7646 /* We can't do this if we are widening INNER_MODE (it
7647 may not be aligned, for one thing). */
7648 && !paradoxical_subreg_p (tmode
, inner_mode
)
7649 && known_le (pos
+ len
, GET_MODE_PRECISION (is_mode
))
7650 && (inner_mode
== tmode
7651 || (! mode_dependent_address_p (XEXP (inner
, 0),
7652 MEM_ADDR_SPACE (inner
))
7653 && ! MEM_VOLATILE_P (inner
))))))
7655 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7656 field. If the original and current mode are the same, we need not
7657 adjust the offset. Otherwise, we do if bytes big endian.
7659 If INNER is not a MEM, get a piece consisting of just the field
7660 of interest (in this case POS % BITS_PER_WORD must be 0). */
7666 /* POS counts from lsb, but make OFFSET count in memory order. */
7667 if (BYTES_BIG_ENDIAN
)
7668 offset
= bits_to_bytes_round_down (GET_MODE_PRECISION (is_mode
)
7671 offset
= pos
/ BITS_PER_UNIT
;
7673 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7675 else if (REG_P (inner
))
7677 if (tmode
!= inner_mode
)
7679 /* We can't call gen_lowpart in a DEST since we
7680 always want a SUBREG (see below) and it would sometimes
7681 return a new hard register. */
7685 = subreg_offset_from_lsb (tmode
, inner_mode
, pos
);
7687 /* Avoid creating invalid subregs, for example when
7688 simplifying (x>>32)&255. */
7689 if (!validate_subreg (tmode
, inner_mode
, inner
, offset
))
7692 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, offset
);
7695 new_rtx
= gen_lowpart (tmode
, inner
);
7701 new_rtx
= force_to_mode (inner
, tmode
,
7702 len
>= HOST_BITS_PER_WIDE_INT
7704 : (HOST_WIDE_INT_1U
<< len
) - 1, false);
7706 /* If this extraction is going into the destination of a SET,
7707 make a STRICT_LOW_PART unless we made a MEM. */
7710 return (MEM_P (new_rtx
) ? new_rtx
7711 : (GET_CODE (new_rtx
) != SUBREG
7712 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7713 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7718 if (CONST_SCALAR_INT_P (new_rtx
))
7719 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7720 mode
, new_rtx
, tmode
);
7722 /* If we know that no extraneous bits are set, and that the high
7723 bit is not set, convert the extraction to the cheaper of
7724 sign and zero extension, that are equivalent in these cases. */
7725 if (flag_expensive_optimizations
7726 && (HWI_COMPUTABLE_MODE_P (tmode
)
7727 && ((nonzero_bits (new_rtx
, tmode
)
7728 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7731 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7732 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7734 /* Prefer ZERO_EXTENSION, since it gives more information to
7736 if (set_src_cost (temp
, mode
, optimize_this_for_speed_p
)
7737 <= set_src_cost (temp1
, mode
, optimize_this_for_speed_p
))
7742 /* Otherwise, sign- or zero-extend unless we already are in the
7745 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7749 /* Unless this is a COMPARE or we have a funny memory reference,
7750 don't do anything with zero-extending field extracts starting at
7751 the low-order bit since they are simple AND operations. */
7752 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7753 && ! in_compare
&& unsignedp
)
7756 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7757 if the position is not a constant and the length is not 1. In all
7758 other cases, we would only be going outside our object in cases when
7759 an original shift would have been undefined. */
7761 && ((pos_rtx
== 0 && maybe_gt (pos
+ len
, GET_MODE_PRECISION (is_mode
)))
7762 || (pos_rtx
!= 0 && len
!= 1)))
7765 enum extraction_pattern pattern
= (in_dest
? EP_insv
7766 : unsignedp
? EP_extzv
: EP_extv
);
7768 /* If INNER is not from memory, we want it to have the mode of a register
7769 extraction pattern's structure operand, or word_mode if there is no
7770 such pattern. The same applies to extraction_mode and pos_mode
7771 and their respective operands.
7773 For memory, assume that the desired extraction_mode and pos_mode
7774 are the same as for a register operation, since at present we don't
7775 have named patterns for aligned memory structures. */
7776 class extraction_insn insn
;
7777 unsigned int inner_size
;
7778 if (GET_MODE_BITSIZE (inner_mode
).is_constant (&inner_size
)
7779 && get_best_reg_extraction_insn (&insn
, pattern
, inner_size
, mode
))
7781 wanted_inner_reg_mode
= insn
.struct_mode
.require ();
7782 pos_mode
= insn
.pos_mode
;
7783 extraction_mode
= insn
.field_mode
;
7786 /* Never narrow an object, since that might not be safe. */
7788 if (mode
!= VOIDmode
7789 && partial_subreg_p (extraction_mode
, mode
))
7790 extraction_mode
= mode
;
7792 /* Punt if len is too large for extraction_mode. */
7793 if (maybe_gt (len
, GET_MODE_PRECISION (extraction_mode
)))
7797 wanted_inner_mode
= wanted_inner_reg_mode
;
7800 /* Be careful not to go beyond the extracted object and maintain the
7801 natural alignment of the memory. */
7802 wanted_inner_mode
= smallest_int_mode_for_size (len
);
7803 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7804 > GET_MODE_BITSIZE (wanted_inner_mode
))
7805 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
).require ();
7810 if (BITS_BIG_ENDIAN
)
7812 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7813 BITS_BIG_ENDIAN style. If position is constant, compute new
7814 position. Otherwise, build subtraction.
7815 Note that POS is relative to the mode of the original argument.
7816 If it's a MEM we need to recompute POS relative to that.
7817 However, if we're extracting from (or inserting into) a register,
7818 we want to recompute POS relative to wanted_inner_mode. */
7821 width
= GET_MODE_BITSIZE (wanted_inner_mode
);
7822 else if (!GET_MODE_BITSIZE (is_mode
).is_constant (&width
))
7826 pos
= width
- len
- pos
;
7829 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7830 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7832 /* POS may be less than 0 now, but we check for that below.
7833 Note that it can only be less than 0 if !MEM_P (inner). */
7836 /* If INNER has a wider mode, and this is a constant extraction, try to
7837 make it smaller and adjust the byte to point to the byte containing
7839 if (wanted_inner_mode
!= VOIDmode
7840 && inner_mode
!= wanted_inner_mode
7842 && partial_subreg_p (wanted_inner_mode
, is_mode
)
7844 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7845 && ! MEM_VOLATILE_P (inner
))
7847 poly_int64 offset
= 0;
7849 /* The computations below will be correct if the machine is big
7850 endian in both bits and bytes or little endian in bits and bytes.
7851 If it is mixed, we must adjust. */
7853 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7854 adjust OFFSET to compensate. */
7855 if (BYTES_BIG_ENDIAN
7856 && paradoxical_subreg_p (is_mode
, inner_mode
))
7857 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7859 /* We can now move to the desired byte. */
7860 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7861 * GET_MODE_SIZE (wanted_inner_mode
);
7862 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7864 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7865 && is_mode
!= wanted_inner_mode
)
7866 offset
= (GET_MODE_SIZE (is_mode
)
7867 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7869 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7872 /* If INNER is not memory, get it into the proper mode. If we are changing
7873 its mode, POS must be a constant and smaller than the size of the new
7875 else if (!MEM_P (inner
))
7877 /* On the LHS, don't create paradoxical subregs implicitely truncating
7878 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7880 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7884 if (GET_MODE (inner
) != wanted_inner_mode
7886 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7892 inner
= force_to_mode (inner
, wanted_inner_mode
,
7894 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7896 : (((HOST_WIDE_INT_1U
<< len
) - 1)
7897 << orig_pos
), false);
7900 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7901 have to zero extend. Otherwise, we can just use a SUBREG.
7903 We dealt with constant rtxes earlier, so pos_rtx cannot
7904 have VOIDmode at this point. */
7906 && (GET_MODE_SIZE (pos_mode
)
7907 > GET_MODE_SIZE (as_a
<scalar_int_mode
> (GET_MODE (pos_rtx
)))))
7909 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7910 GET_MODE (pos_rtx
));
7912 /* If we know that no extraneous bits are set, and that the high
7913 bit is not set, convert extraction to cheaper one - either
7914 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7916 if (flag_expensive_optimizations
7917 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7918 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7919 & ~(((unsigned HOST_WIDE_INT
)
7920 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7924 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7925 GET_MODE (pos_rtx
));
7927 /* Prefer ZERO_EXTENSION, since it gives more information to
7929 if (set_src_cost (temp1
, pos_mode
, optimize_this_for_speed_p
)
7930 < set_src_cost (temp
, pos_mode
, optimize_this_for_speed_p
))
7936 /* Make POS_RTX unless we already have it and it is correct. If we don't
7937 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7939 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7940 pos_rtx
= orig_pos_rtx
;
7942 else if (pos_rtx
== 0)
7943 pos_rtx
= GEN_INT (pos
);
7945 /* Make the required operation. See if we can use existing rtx. */
7946 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7947 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7949 new_rtx
= gen_lowpart (mode
, new_rtx
);
7954 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7955 can be commuted with any other operations in X. Return X without
7956 that shift if so. */
7959 extract_left_shift (scalar_int_mode mode
, rtx x
, int count
)
7961 enum rtx_code code
= GET_CODE (x
);
7967 /* This is the shift itself. If it is wide enough, we will return
7968 either the value being shifted if the shift count is equal to
7969 COUNT or a shift for the difference. */
7970 if (CONST_INT_P (XEXP (x
, 1))
7971 && INTVAL (XEXP (x
, 1)) >= count
)
7972 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7973 INTVAL (XEXP (x
, 1)) - count
);
7977 if ((tem
= extract_left_shift (mode
, XEXP (x
, 0), count
)) != 0)
7978 return simplify_gen_unary (code
, mode
, tem
, mode
);
7982 case PLUS
: case IOR
: case XOR
: case AND
:
7983 /* If we can safely shift this constant and we find the inner shift,
7984 make a new operation. */
7985 if (CONST_INT_P (XEXP (x
, 1))
7986 && (UINTVAL (XEXP (x
, 1))
7987 & (((HOST_WIDE_INT_1U
<< count
)) - 1)) == 0
7988 && (tem
= extract_left_shift (mode
, XEXP (x
, 0), count
)) != 0)
7990 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7991 return simplify_gen_binary (code
, mode
, tem
,
7992 gen_int_mode (val
, mode
));
8003 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
8004 level of the expression and MODE is its mode. IN_CODE is as for
8005 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
8006 that should be used when recursing on operands of *X_PTR.
8008 There are two possible actions:
8010 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
8011 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
8013 - Return a new rtx, which the caller returns directly. */
8016 make_compound_operation_int (scalar_int_mode mode
, rtx
*x_ptr
,
8017 enum rtx_code in_code
,
8018 enum rtx_code
*next_code_ptr
)
8021 enum rtx_code next_code
= *next_code_ptr
;
8022 enum rtx_code code
= GET_CODE (x
);
8023 int mode_width
= GET_MODE_PRECISION (mode
);
8028 scalar_int_mode inner_mode
;
8029 bool equality_comparison
= false;
8033 equality_comparison
= true;
8037 /* Process depending on the code of this operation. If NEW is set
8038 nonzero, it will be returned. */
8043 /* Convert shifts by constants into multiplications if inside
8045 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
8046 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8047 && INTVAL (XEXP (x
, 1)) >= 0)
8049 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
8050 HOST_WIDE_INT multval
= HOST_WIDE_INT_1
<< count
;
8052 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8053 if (GET_CODE (new_rtx
) == NEG
)
8055 new_rtx
= XEXP (new_rtx
, 0);
8058 multval
= trunc_int_for_mode (multval
, mode
);
8059 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
8066 lhs
= make_compound_operation (lhs
, next_code
);
8067 rhs
= make_compound_operation (rhs
, next_code
);
8068 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
)
8070 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
8072 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
8074 else if (GET_CODE (lhs
) == MULT
8075 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
8077 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
8078 simplify_gen_unary (NEG
, mode
,
8081 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
8085 SUBST (XEXP (x
, 0), lhs
);
8086 SUBST (XEXP (x
, 1), rhs
);
8088 maybe_swap_commutative_operands (x
);
8094 lhs
= make_compound_operation (lhs
, next_code
);
8095 rhs
= make_compound_operation (rhs
, next_code
);
8096 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
)
8098 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
8100 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
8102 else if (GET_CODE (rhs
) == MULT
8103 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
8105 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
8106 simplify_gen_unary (NEG
, mode
,
8109 return simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
8113 SUBST (XEXP (x
, 0), lhs
);
8114 SUBST (XEXP (x
, 1), rhs
);
8119 /* If the second operand is not a constant, we can't do anything
8121 if (!CONST_INT_P (XEXP (x
, 1)))
8124 /* If the constant is a power of two minus one and the first operand
8125 is a logical right shift, make an extraction. */
8126 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8127 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8129 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8130 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1),
8131 i
, true, false, in_code
== COMPARE
);
8134 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8135 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
8136 && subreg_lowpart_p (XEXP (x
, 0))
8137 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (XEXP (x
, 0))),
8139 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
8140 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8142 rtx inner_x0
= SUBREG_REG (XEXP (x
, 0));
8143 new_rtx
= make_compound_operation (XEXP (inner_x0
, 0), next_code
);
8144 new_rtx
= make_extraction (inner_mode
, new_rtx
, 0,
8146 i
, true, false, in_code
== COMPARE
);
8148 /* If we narrowed the mode when dropping the subreg, then we lose. */
8149 if (GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (mode
))
8152 /* If that didn't give anything, see if the AND simplifies on
8154 if (!new_rtx
&& i
>= 0)
8156 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8157 new_rtx
= make_extraction (mode
, new_rtx
, 0, NULL_RTX
, i
,
8158 true, false, in_code
== COMPARE
);
8161 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8162 else if ((GET_CODE (XEXP (x
, 0)) == XOR
8163 || GET_CODE (XEXP (x
, 0)) == IOR
)
8164 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
8165 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
8166 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8168 /* Apply the distributive law, and then try to make extractions. */
8169 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
8170 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
8172 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
8174 new_rtx
= make_compound_operation (new_rtx
, in_code
);
8177 /* If we are have (and (rotate X C) M) and C is larger than the number
8178 of bits in M, this is an extraction. */
8180 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
8181 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8182 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
8183 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
8185 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
8186 new_rtx
= make_extraction (mode
, new_rtx
,
8187 (GET_MODE_PRECISION (mode
)
8188 - INTVAL (XEXP (XEXP (x
, 0), 1))),
8189 NULL_RTX
, i
, true, false,
8190 in_code
== COMPARE
);
8193 /* On machines without logical shifts, if the operand of the AND is
8194 a logical shift and our mask turns off all the propagated sign
8195 bits, we can replace the logical shift with an arithmetic shift. */
8196 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8197 && !have_insn_for (LSHIFTRT
, mode
)
8198 && have_insn_for (ASHIFTRT
, mode
)
8199 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8200 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8201 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8202 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8204 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
8206 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
8207 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
8209 gen_rtx_ASHIFTRT (mode
,
8210 make_compound_operation (XEXP (XEXP (x
,
8214 XEXP (XEXP (x
, 0), 1)));
8217 /* If the constant is one less than a power of two, this might be
8218 representable by an extraction even if no shift is present.
8219 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8220 we are in a COMPARE. */
8221 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
8222 new_rtx
= make_extraction (mode
,
8223 make_compound_operation (XEXP (x
, 0),
8226 true, false, in_code
== COMPARE
);
8228 /* If we are in a comparison and this is an AND with a power of two,
8229 convert this into the appropriate bit extract. */
8230 else if (in_code
== COMPARE
8231 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
8232 && (equality_comparison
|| i
< GET_MODE_PRECISION (mode
) - 1))
8233 new_rtx
= make_extraction (mode
,
8234 make_compound_operation (XEXP (x
, 0),
8236 i
, NULL_RTX
, 1, true, false, true);
8238 /* If the one operand is a paradoxical subreg of a register or memory and
8239 the constant (limited to the smaller mode) has only zero bits where
8240 the sub expression has known zero bits, this can be expressed as
8242 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
)
8246 sub
= XEXP (XEXP (x
, 0), 0);
8247 machine_mode sub_mode
= GET_MODE (sub
);
8249 if ((REG_P (sub
) || MEM_P (sub
))
8250 && GET_MODE_PRECISION (sub_mode
).is_constant (&sub_width
)
8251 && sub_width
< mode_width
8252 && (!WORD_REGISTER_OPERATIONS
8253 || sub_width
>= BITS_PER_WORD
8254 /* On WORD_REGISTER_OPERATIONS targets the bits
8255 beyond sub_mode aren't considered undefined,
8256 so optimize only if it is a MEM load when MEM loads
8257 zero extend, because then the upper bits are all zero. */
8259 && load_extend_op (sub_mode
) == ZERO_EXTEND
)))
8261 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (sub_mode
);
8262 unsigned HOST_WIDE_INT mask
;
8264 /* Original AND constant with all the known zero bits set. */
8265 mask
= UINTVAL (XEXP (x
, 1)) | (~nonzero_bits (sub
, sub_mode
));
8266 if ((mask
& mode_mask
) == mode_mask
)
8268 new_rtx
= make_compound_operation (sub
, next_code
);
8269 new_rtx
= make_extraction (mode
, new_rtx
, 0, 0, sub_width
,
8270 true, false, in_code
== COMPARE
);
8278 /* If the sign bit is known to be zero, replace this with an
8279 arithmetic shift. */
8280 if (have_insn_for (ASHIFTRT
, mode
)
8281 && ! have_insn_for (LSHIFTRT
, mode
)
8282 && mode_width
<= HOST_BITS_PER_WIDE_INT
8283 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
8285 new_rtx
= gen_rtx_ASHIFTRT (mode
,
8286 make_compound_operation (XEXP (x
, 0),
8298 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8299 this is a SIGN_EXTRACT. */
8300 if (CONST_INT_P (rhs
)
8301 && GET_CODE (lhs
) == ASHIFT
8302 && CONST_INT_P (XEXP (lhs
, 1))
8303 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
8304 && INTVAL (XEXP (lhs
, 1)) >= 0
8305 && INTVAL (rhs
) < mode_width
)
8307 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8308 new_rtx
= make_extraction (mode
, new_rtx
,
8309 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8310 NULL_RTX
, mode_width
- INTVAL (rhs
),
8311 code
== LSHIFTRT
, false,
8312 in_code
== COMPARE
);
8316 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8317 If so, try to merge the shifts into a SIGN_EXTEND. We could
8318 also do this for some cases of SIGN_EXTRACT, but it doesn't
8319 seem worth the effort; the case checked for occurs on Alpha. */
8322 && ! (GET_CODE (lhs
) == SUBREG
8323 && (OBJECT_P (SUBREG_REG (lhs
))))
8324 && CONST_INT_P (rhs
)
8325 && INTVAL (rhs
) >= 0
8326 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8327 && INTVAL (rhs
) < mode_width
8328 && (new_rtx
= extract_left_shift (mode
, lhs
, INTVAL (rhs
))) != 0)
8329 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
,
8331 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8332 code
== LSHIFTRT
, false, in_code
== COMPARE
);
8337 /* Call ourselves recursively on the inner expression. If we are
8338 narrowing the object and it has a different RTL code from
8339 what it originally did, do this SUBREG as a force_to_mode. */
8341 rtx inner
= SUBREG_REG (x
), simplified
;
8342 enum rtx_code subreg_code
= in_code
;
8344 /* If the SUBREG is masking of a logical right shift,
8345 make an extraction. */
8346 if (GET_CODE (inner
) == LSHIFTRT
8347 && is_a
<scalar_int_mode
> (GET_MODE (inner
), &inner_mode
)
8348 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (inner_mode
)
8349 && CONST_INT_P (XEXP (inner
, 1))
8350 && UINTVAL (XEXP (inner
, 1)) < GET_MODE_PRECISION (inner_mode
)
8351 && subreg_lowpart_p (x
))
8353 new_rtx
= make_compound_operation (XEXP (inner
, 0), next_code
);
8354 int width
= GET_MODE_PRECISION (inner_mode
)
8355 - INTVAL (XEXP (inner
, 1));
8356 if (width
> mode_width
)
8358 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (inner
, 1),
8359 width
, true, false, in_code
== COMPARE
);
8363 /* If in_code is COMPARE, it isn't always safe to pass it through
8364 to the recursive make_compound_operation call. */
8365 if (subreg_code
== COMPARE
8366 && (!subreg_lowpart_p (x
)
8367 || GET_CODE (inner
) == SUBREG
8368 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8369 is (const_int 0), rather than
8370 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8371 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8372 for non-equality comparisons against 0 is not equivalent
8373 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8374 || (GET_CODE (inner
) == AND
8375 && CONST_INT_P (XEXP (inner
, 1))
8376 && partial_subreg_p (x
)
8377 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8378 >= GET_MODE_BITSIZE (mode
) - 1)))
8381 tem
= make_compound_operation (inner
, subreg_code
);
8384 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8388 if (GET_CODE (tem
) != GET_CODE (inner
)
8389 && partial_subreg_p (x
)
8390 && subreg_lowpart_p (x
))
8393 = force_to_mode (tem
, mode
, HOST_WIDE_INT_M1U
, false);
8395 /* If we have something other than a SUBREG, we might have
8396 done an expansion, so rerun ourselves. */
8397 if (GET_CODE (newer
) != SUBREG
)
8398 newer
= make_compound_operation (newer
, in_code
);
8400 /* force_to_mode can expand compounds. If it just re-expanded
8401 the compound, use gen_lowpart to convert to the desired
8403 if (rtx_equal_p (newer
, x
)
8404 /* Likewise if it re-expanded the compound only partially.
8405 This happens for SUBREG of ZERO_EXTRACT if they extract
8406 the same number of bits. */
8407 || (GET_CODE (newer
) == SUBREG
8408 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8409 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8410 && GET_CODE (inner
) == AND
8411 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8412 return gen_lowpart (GET_MODE (x
), tem
);
8427 *x_ptr
= gen_lowpart (mode
, new_rtx
);
8428 *next_code_ptr
= next_code
;
8432 /* Look at the expression rooted at X. Look for expressions
8433 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8434 Form these expressions.
8436 Return the new rtx, usually just X.
8438 Also, for machines like the VAX that don't have logical shift insns,
8439 try to convert logical to arithmetic shift operations in cases where
8440 they are equivalent. This undoes the canonicalizations to logical
8441 shifts done elsewhere.
8443 We try, as much as possible, to re-use rtl expressions to save memory.
8445 IN_CODE says what kind of expression we are processing. Normally, it is
8446 SET. In a memory address it is MEM. When processing the arguments of
8447 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8448 precisely it is an equality comparison against zero. */
8451 make_compound_operation (rtx x
, enum rtx_code in_code
)
8453 enum rtx_code code
= GET_CODE (x
);
8456 enum rtx_code next_code
;
8459 /* Select the code to be used in recursive calls. Once we are inside an
8460 address, we stay there. If we have a comparison, set to COMPARE,
8461 but once inside, go back to our default of SET. */
8463 next_code
= (code
== MEM
? MEM
8464 : ((code
== COMPARE
|| COMPARISON_P (x
))
8465 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
8466 : in_code
== COMPARE
|| in_code
== EQ
? SET
: in_code
);
8468 scalar_int_mode mode
;
8469 if (is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
))
8471 rtx new_rtx
= make_compound_operation_int (mode
, &x
, in_code
,
8475 code
= GET_CODE (x
);
8478 /* Now recursively process each operand of this operation. We need to
8479 handle ZERO_EXTEND specially so that we don't lose track of the
8481 if (code
== ZERO_EXTEND
)
8483 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8484 tem
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8485 new_rtx
, GET_MODE (XEXP (x
, 0)));
8488 SUBST (XEXP (x
, 0), new_rtx
);
8492 fmt
= GET_RTX_FORMAT (code
);
8493 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8496 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8497 SUBST (XEXP (x
, i
), new_rtx
);
8499 else if (fmt
[i
] == 'E')
8500 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8502 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8503 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8506 maybe_swap_commutative_operands (x
);
8510 /* Given M see if it is a value that would select a field of bits
8511 within an item, but not the entire word. Return -1 if not.
8512 Otherwise, return the starting position of the field, where 0 is the
8515 *PLEN is set to the length of the field. */
8518 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8520 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8521 int pos
= m
? ctz_hwi (m
) : -1;
8525 /* Now shift off the low-order zero bits and see if we have a
8526 power of two minus 1. */
8527 len
= exact_log2 ((m
>> pos
) + 1);
8536 /* If X refers to a register that equals REG in value, replace these
8537 references with REG. */
8539 canon_reg_for_combine (rtx x
, rtx reg
)
8546 enum rtx_code code
= GET_CODE (x
);
8547 switch (GET_RTX_CLASS (code
))
8550 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8551 if (op0
!= XEXP (x
, 0))
8552 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8557 case RTX_COMM_ARITH
:
8558 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8559 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8560 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8561 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8565 case RTX_COMM_COMPARE
:
8566 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8567 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8568 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8569 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8570 GET_MODE (op0
), op0
, op1
);
8574 case RTX_BITFIELD_OPS
:
8575 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8576 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8577 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8578 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8579 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8580 GET_MODE (op0
), op0
, op1
, op2
);
8586 if (rtx_equal_p (get_last_value (reg
), x
)
8587 || rtx_equal_p (reg
, get_last_value (x
)))
8596 fmt
= GET_RTX_FORMAT (code
);
8598 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8601 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8602 if (op
!= XEXP (x
, i
))
8612 else if (fmt
[i
] == 'E')
8615 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8617 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8618 if (op
!= XVECEXP (x
, i
, j
))
8625 XVECEXP (x
, i
, j
) = op
;
8636 /* Return X converted to MODE. If the value is already truncated to
8637 MODE we can just return a subreg even though in the general case we
8638 would need an explicit truncation. */
8641 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8643 if (!CONST_INT_P (x
)
8644 && partial_subreg_p (mode
, GET_MODE (x
))
8645 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8646 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8648 /* Bit-cast X into an integer mode. */
8649 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8650 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)).require (), x
);
8651 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
).require (),
8655 return gen_lowpart (mode
, x
);
8658 /* See if X can be simplified knowing that we will only refer to it in
8659 MODE and will only refer to those bits that are nonzero in MASK.
8660 If other bits are being computed or if masking operations are done
8661 that select a superset of the bits in MASK, they can sometimes be
8664 Return a possibly simplified expression, but always convert X to
8665 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8667 If JUST_SELECT is true, don't optimize by noticing that bits in MASK
8668 are all off in X. This is used when X will be complemented, by either
8669 NOT, NEG, or XOR. */
8672 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8675 enum rtx_code code
= GET_CODE (x
);
8676 bool next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8677 machine_mode op_mode
;
8678 unsigned HOST_WIDE_INT nonzero
;
8680 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8681 code below will do the wrong thing since the mode of such an
8682 expression is VOIDmode.
8684 Also do nothing if X is a CLOBBER; this can happen if X was
8685 the return value from a call to gen_lowpart. */
8686 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8689 /* We want to perform the operation in its present mode unless we know
8690 that the operation is valid in MODE, in which case we do the operation
8692 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8693 && have_insn_for (code
, mode
))
8694 ? mode
: GET_MODE (x
));
8696 /* It is not valid to do a right-shift in a narrower mode
8697 than the one it came in with. */
8698 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8699 && partial_subreg_p (mode
, GET_MODE (x
)))
8700 op_mode
= GET_MODE (x
);
8702 /* Truncate MASK to fit OP_MODE. */
8704 mask
&= GET_MODE_MASK (op_mode
);
8706 /* Determine what bits of X are guaranteed to be (non)zero. */
8707 nonzero
= nonzero_bits (x
, mode
);
8709 /* If none of the bits in X are needed, return a zero. */
8710 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8713 /* If X is a CONST_INT, return a new one. Do this here since the
8714 test below will fail. */
8715 if (CONST_INT_P (x
))
8717 if (SCALAR_INT_MODE_P (mode
))
8718 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8721 x
= GEN_INT (INTVAL (x
) & mask
);
8722 return gen_lowpart_common (mode
, x
);
8726 /* If X is narrower than MODE and we want all the bits in X's mode, just
8727 get X in the proper mode. */
8728 if (paradoxical_subreg_p (mode
, GET_MODE (x
))
8729 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8730 return gen_lowpart (mode
, x
);
8732 /* We can ignore the effect of a SUBREG if it narrows the mode or
8733 if the constant masks to zero all the bits the mode doesn't have. */
8734 if (GET_CODE (x
) == SUBREG
8735 && subreg_lowpart_p (x
)
8736 && (partial_subreg_p (x
)
8738 & GET_MODE_MASK (GET_MODE (x
))
8739 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))) == 0))
8740 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8742 scalar_int_mode int_mode
, xmode
;
8743 if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
8744 && is_a
<scalar_int_mode
> (GET_MODE (x
), &xmode
))
8745 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8747 return force_int_to_mode (x
, int_mode
, xmode
,
8748 as_a
<scalar_int_mode
> (op_mode
),
8751 return gen_lowpart_or_truncate (mode
, x
);
8754 /* Subroutine of force_to_mode that handles cases in which both X and
8755 the result are scalar integers. MODE is the mode of the result,
8756 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8757 is preferred for simplified versions of X. The other arguments
8758 are as for force_to_mode. */
8761 force_int_to_mode (rtx x
, scalar_int_mode mode
, scalar_int_mode xmode
,
8762 scalar_int_mode op_mode
, unsigned HOST_WIDE_INT mask
,
8765 enum rtx_code code
= GET_CODE (x
);
8766 bool next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8767 unsigned HOST_WIDE_INT fuller_mask
;
8769 poly_int64 const_op0
;
8771 /* When we have an arithmetic operation, or a shift whose count we
8772 do not know, we need to assume that all bits up to the highest-order
8773 bit in MASK will be needed. This is how we form such a mask. */
8774 if (mask
& (HOST_WIDE_INT_1U
<< (HOST_BITS_PER_WIDE_INT
- 1)))
8775 fuller_mask
= HOST_WIDE_INT_M1U
;
8777 fuller_mask
= ((HOST_WIDE_INT_1U
<< (floor_log2 (mask
) + 1)) - 1);
8782 /* If X is a (clobber (const_int)), return it since we know we are
8783 generating something that won't match. */
8790 x
= expand_compound_operation (x
);
8791 if (GET_CODE (x
) != code
)
8792 return force_to_mode (x
, mode
, mask
, next_select
);
8796 /* Similarly for a truncate. */
8797 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8800 /* If this is an AND with a constant, convert it into an AND
8801 whose constant is the AND of that constant with MASK. If it
8802 remains an AND of MASK, delete it since it is redundant. */
8804 if (CONST_INT_P (XEXP (x
, 1)))
8806 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8807 mask
& INTVAL (XEXP (x
, 1)));
8810 /* If X is still an AND, see if it is an AND with a mask that
8811 is just some low-order bits. If so, and it is MASK, we don't
8814 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8815 && (INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (xmode
)) == mask
)
8818 /* If it remains an AND, try making another AND with the bits
8819 in the mode mask that aren't in MASK turned on. If the
8820 constant in the AND is wide enough, this might make a
8821 cheaper constant. */
8823 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8824 && GET_MODE_MASK (xmode
) != mask
8825 && HWI_COMPUTABLE_MODE_P (xmode
))
8827 unsigned HOST_WIDE_INT cval
8828 = UINTVAL (XEXP (x
, 1)) | (GET_MODE_MASK (xmode
) & ~mask
);
8831 y
= simplify_gen_binary (AND
, xmode
, XEXP (x
, 0),
8832 gen_int_mode (cval
, xmode
));
8833 if (set_src_cost (y
, xmode
, optimize_this_for_speed_p
)
8834 < set_src_cost (x
, xmode
, optimize_this_for_speed_p
))
8844 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8845 low-order bits (as in an alignment operation) and FOO is already
8846 aligned to that boundary, mask C1 to that boundary as well.
8847 This may eliminate that PLUS and, later, the AND. */
8850 unsigned int width
= GET_MODE_PRECISION (mode
);
8851 unsigned HOST_WIDE_INT smask
= mask
;
8853 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8854 number, sign extend it. */
8856 if (width
< HOST_BITS_PER_WIDE_INT
8857 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8858 smask
|= HOST_WIDE_INT_M1U
<< width
;
8860 if (CONST_INT_P (XEXP (x
, 1))
8861 && pow2p_hwi (- smask
)
8862 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8863 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8864 return force_to_mode (plus_constant (xmode
, XEXP (x
, 0),
8865 (INTVAL (XEXP (x
, 1)) & smask
)),
8866 mode
, smask
, next_select
);
8872 /* Substituting into the operands of a widening MULT is not likely to
8873 create RTL matching a machine insn. */
8875 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
8876 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
8877 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
8878 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
8879 && REG_P (XEXP (XEXP (x
, 0), 0))
8880 && REG_P (XEXP (XEXP (x
, 1), 0)))
8881 return gen_lowpart_or_truncate (mode
, x
);
8883 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8884 most significant bit in MASK since carries from those bits will
8885 affect the bits we are interested in. */
8890 /* If X is (minus C Y) where C's least set bit is larger than any bit
8891 in the mask, then we may replace with (neg Y). */
8892 if (poly_int_rtx_p (XEXP (x
, 0), &const_op0
)
8893 && known_alignment (poly_uint64 (const_op0
)) > mask
)
8895 x
= simplify_gen_unary (NEG
, xmode
, XEXP (x
, 1), xmode
);
8896 return force_to_mode (x
, mode
, mask
, next_select
);
8899 /* Similarly, if C contains every bit in the fuller_mask, then we may
8900 replace with (not Y). */
8901 if (CONST_INT_P (XEXP (x
, 0))
8902 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8904 x
= simplify_gen_unary (NOT
, xmode
, XEXP (x
, 1), xmode
);
8905 return force_to_mode (x
, mode
, mask
, next_select
);
8913 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8914 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8915 operation which may be a bitfield extraction. Ensure that the
8916 constant we form is not wider than the mode of X. */
8918 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8919 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8920 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8921 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8922 && CONST_INT_P (XEXP (x
, 1))
8923 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8924 + floor_log2 (INTVAL (XEXP (x
, 1))))
8925 < GET_MODE_PRECISION (xmode
))
8926 && (UINTVAL (XEXP (x
, 1))
8927 & ~nonzero_bits (XEXP (x
, 0), xmode
)) == 0)
8929 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8930 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8932 temp
= simplify_gen_binary (GET_CODE (x
), xmode
,
8933 XEXP (XEXP (x
, 0), 0), temp
);
8934 x
= simplify_gen_binary (LSHIFTRT
, xmode
, temp
,
8935 XEXP (XEXP (x
, 0), 1));
8936 return force_to_mode (x
, mode
, mask
, next_select
);
8940 /* For most binary operations, just propagate into the operation and
8941 change the mode if we have an operation of that mode. */
8943 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8944 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8946 /* If we ended up truncating both operands, truncate the result of the
8947 operation instead. */
8948 if (GET_CODE (op0
) == TRUNCATE
8949 && GET_CODE (op1
) == TRUNCATE
)
8951 op0
= XEXP (op0
, 0);
8952 op1
= XEXP (op1
, 0);
8955 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8956 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8958 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8960 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8966 /* For left shifts, do the same, but just for the first operand.
8967 However, we cannot do anything with shifts where we cannot
8968 guarantee that the counts are smaller than the size of the mode
8969 because such a count will have a different meaning in a
8972 if (! (CONST_INT_P (XEXP (x
, 1))
8973 && INTVAL (XEXP (x
, 1)) >= 0
8974 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8975 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8976 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8977 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8980 /* If the shift count is a constant and we can do arithmetic in
8981 the mode of the shift, refine which bits we need. Otherwise, use the
8982 conservative form of the mask. */
8983 if (CONST_INT_P (XEXP (x
, 1))
8984 && INTVAL (XEXP (x
, 1)) >= 0
8985 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8986 && HWI_COMPUTABLE_MODE_P (op_mode
))
8987 mask
>>= INTVAL (XEXP (x
, 1));
8991 op0
= gen_lowpart_or_truncate (op_mode
,
8992 force_to_mode (XEXP (x
, 0), mode
,
8993 mask
, next_select
));
8995 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0))
8997 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
9003 /* Here we can only do something if the shift count is a constant,
9004 this shift constant is valid for the host, and we can do arithmetic
9007 if (CONST_INT_P (XEXP (x
, 1))
9008 && INTVAL (XEXP (x
, 1)) >= 0
9009 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
9010 && HWI_COMPUTABLE_MODE_P (op_mode
))
9012 rtx inner
= XEXP (x
, 0);
9013 unsigned HOST_WIDE_INT inner_mask
;
9015 /* Select the mask of the bits we need for the shift operand. */
9016 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
9018 /* We can only change the mode of the shift if we can do arithmetic
9019 in the mode of the shift and INNER_MASK is no wider than the
9020 width of X's mode. */
9021 if ((inner_mask
& ~GET_MODE_MASK (xmode
)) != 0)
9024 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
9026 if (xmode
!= op_mode
|| inner
!= XEXP (x
, 0))
9028 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
9033 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
9034 shift and AND produces only copies of the sign bit (C2 is one less
9035 than a power of two), we can do this with just a shift. */
9037 if (GET_CODE (x
) == LSHIFTRT
9038 && CONST_INT_P (XEXP (x
, 1))
9039 /* The shift puts one of the sign bit copies in the least significant
9041 && ((INTVAL (XEXP (x
, 1))
9042 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
9043 >= GET_MODE_PRECISION (xmode
))
9044 && pow2p_hwi (mask
+ 1)
9045 /* Number of bits left after the shift must be more than the mask
9047 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
9048 <= GET_MODE_PRECISION (xmode
))
9049 /* Must be more sign bit copies than the mask needs. */
9050 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
9051 >= exact_log2 (mask
+ 1)))
9053 int nbits
= GET_MODE_PRECISION (xmode
) - exact_log2 (mask
+ 1);
9054 x
= simplify_gen_binary (LSHIFTRT
, xmode
, XEXP (x
, 0),
9055 gen_int_shift_amount (xmode
, nbits
));
9060 /* If we are just looking for the sign bit, we don't need this shift at
9061 all, even if it has a variable count. */
9062 if (val_signbit_p (xmode
, mask
))
9063 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
9065 /* If this is a shift by a constant, get a mask that contains those bits
9066 that are not copies of the sign bit. We then have two cases: If
9067 MASK only includes those bits, this can be a logical shift, which may
9068 allow simplifications. If MASK is a single-bit field not within
9069 those bits, we are requesting a copy of the sign bit and hence can
9070 shift the sign bit to the appropriate location. */
9072 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
9073 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
9075 unsigned HOST_WIDE_INT nonzero
;
9078 /* If the considered data is wider than HOST_WIDE_INT, we can't
9079 represent a mask for all its bits in a single scalar.
9080 But we only care about the lower bits, so calculate these. */
9082 if (GET_MODE_PRECISION (xmode
) > HOST_BITS_PER_WIDE_INT
)
9084 nonzero
= HOST_WIDE_INT_M1U
;
9086 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9087 is the number of bits a full-width mask would have set.
9088 We need only shift if these are fewer than nonzero can
9089 hold. If not, we must keep all bits set in nonzero. */
9091 if (GET_MODE_PRECISION (xmode
) - INTVAL (XEXP (x
, 1))
9092 < HOST_BITS_PER_WIDE_INT
)
9093 nonzero
>>= INTVAL (XEXP (x
, 1))
9094 + HOST_BITS_PER_WIDE_INT
9095 - GET_MODE_PRECISION (xmode
);
9099 nonzero
= GET_MODE_MASK (xmode
);
9100 nonzero
>>= INTVAL (XEXP (x
, 1));
9103 if ((mask
& ~nonzero
) == 0)
9105 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, xmode
,
9106 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
9107 if (GET_CODE (x
) != ASHIFTRT
)
9108 return force_to_mode (x
, mode
, mask
, next_select
);
9111 else if ((i
= exact_log2 (mask
)) >= 0)
9113 x
= simplify_shift_const
9114 (NULL_RTX
, LSHIFTRT
, xmode
, XEXP (x
, 0),
9115 GET_MODE_PRECISION (xmode
) - 1 - i
);
9117 if (GET_CODE (x
) != ASHIFTRT
)
9118 return force_to_mode (x
, mode
, mask
, next_select
);
9122 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9123 even if the shift count isn't a constant. */
9125 x
= simplify_gen_binary (LSHIFTRT
, xmode
, XEXP (x
, 0), XEXP (x
, 1));
9129 /* If this is a zero- or sign-extension operation that just affects bits
9130 we don't care about, remove it. Be sure the call above returned
9131 something that is still a shift. */
9133 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
9134 && CONST_INT_P (XEXP (x
, 1))
9135 && INTVAL (XEXP (x
, 1)) >= 0
9136 && (INTVAL (XEXP (x
, 1))
9137 <= GET_MODE_PRECISION (xmode
) - (floor_log2 (mask
) + 1))
9138 && GET_CODE (XEXP (x
, 0)) == ASHIFT
9139 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
9140 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
, next_select
);
9146 /* If the shift count is constant and we can do computations
9147 in the mode of X, compute where the bits we care about are.
9148 Otherwise, we can't do anything. Don't change the mode of
9149 the shift or propagate MODE into the shift, though. */
9150 if (CONST_INT_P (XEXP (x
, 1))
9151 && INTVAL (XEXP (x
, 1)) >= 0)
9153 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
9154 xmode
, gen_int_mode (mask
, xmode
),
9156 if (temp
&& CONST_INT_P (temp
))
9157 x
= simplify_gen_binary (code
, xmode
,
9158 force_to_mode (XEXP (x
, 0), xmode
,
9159 INTVAL (temp
), next_select
),
9165 /* If we just want the low-order bit, the NEG isn't needed since it
9166 won't change the low-order bit. */
9168 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
9170 /* We need any bits less significant than the most significant bit in
9171 MASK since carries from those bits will affect the bits we are
9177 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9178 same as the XOR case above. Ensure that the constant we form is not
9179 wider than the mode of X. */
9181 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
9182 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
9183 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
9184 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
9185 < GET_MODE_PRECISION (xmode
))
9186 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
9188 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)), xmode
);
9189 temp
= simplify_gen_binary (XOR
, xmode
, XEXP (XEXP (x
, 0), 0), temp
);
9190 x
= simplify_gen_binary (LSHIFTRT
, xmode
,
9191 temp
, XEXP (XEXP (x
, 0), 1));
9193 return force_to_mode (x
, mode
, mask
, next_select
);
9196 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9197 use the full mask inside the NOT. */
9201 op0
= gen_lowpart_or_truncate (op_mode
,
9202 force_to_mode (XEXP (x
, 0), mode
, mask
,
9204 if (op_mode
!= xmode
|| op0
!= XEXP (x
, 0))
9206 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
9212 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9213 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9214 which is equal to STORE_FLAG_VALUE. */
9215 if ((mask
& ~STORE_FLAG_VALUE
) == 0
9216 && XEXP (x
, 1) == const0_rtx
9217 && GET_MODE (XEXP (x
, 0)) == mode
9218 && pow2p_hwi (nonzero_bits (XEXP (x
, 0), mode
))
9219 && (nonzero_bits (XEXP (x
, 0), mode
)
9220 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
9221 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
9226 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9227 written in a narrower mode. We play it safe and do not do so. */
9229 op0
= gen_lowpart_or_truncate (xmode
,
9230 force_to_mode (XEXP (x
, 1), mode
,
9231 mask
, next_select
));
9232 op1
= gen_lowpart_or_truncate (xmode
,
9233 force_to_mode (XEXP (x
, 2), mode
,
9234 mask
, next_select
));
9235 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
9236 x
= simplify_gen_ternary (IF_THEN_ELSE
, xmode
,
9237 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
9245 /* Ensure we return a value of the proper mode. */
9246 return gen_lowpart_or_truncate (mode
, x
);
9249 /* Return nonzero if X is an expression that has one of two values depending on
9250 whether some other value is zero or nonzero. In that case, we return the
9251 value that is being tested, *PTRUE is set to the value if the rtx being
9252 returned has a nonzero value, and *PFALSE is set to the other alternative.
9254 If we return zero, we set *PTRUE and *PFALSE to X. */
9257 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
9259 machine_mode mode
= GET_MODE (x
);
9260 enum rtx_code code
= GET_CODE (x
);
9261 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
9262 unsigned HOST_WIDE_INT nz
;
9263 scalar_int_mode int_mode
;
9265 /* If we are comparing a value against zero, we are done. */
9266 if ((code
== NE
|| code
== EQ
)
9267 && XEXP (x
, 1) == const0_rtx
)
9269 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
9270 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
9274 /* If this is a unary operation whose operand has one of two values, apply
9275 our opcode to compute those values. */
9276 else if (UNARY_P (x
)
9277 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
9279 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
9280 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
9281 GET_MODE (XEXP (x
, 0)));
9285 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9286 make can't possibly match and would suppress other optimizations. */
9287 else if (code
== COMPARE
)
9290 /* If this is a binary operation, see if either side has only one of two
9291 values. If either one does or if both do and they are conditional on
9292 the same value, compute the new true and false values. */
9293 else if (BINARY_P (x
))
9295 rtx op0
= XEXP (x
, 0);
9296 rtx op1
= XEXP (x
, 1);
9297 cond0
= if_then_else_cond (op0
, &true0
, &false0
);
9298 cond1
= if_then_else_cond (op1
, &true1
, &false1
);
9300 if ((cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
))
9301 && (REG_P (op0
) || REG_P (op1
)))
9303 /* Try to enable a simplification by undoing work done by
9304 if_then_else_cond if it converted a REG into something more
9309 true0
= false0
= op0
;
9314 true1
= false1
= op1
;
9318 if ((cond0
!= 0 || cond1
!= 0)
9319 && ! (cond0
!= 0 && cond1
!= 0 && !rtx_equal_p (cond0
, cond1
)))
9321 /* If if_then_else_cond returned zero, then true/false are the
9322 same rtl. We must copy one of them to prevent invalid rtl
9325 true0
= copy_rtx (true0
);
9326 else if (cond1
== 0)
9327 true1
= copy_rtx (true1
);
9329 if (COMPARISON_P (x
))
9331 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
9333 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
9338 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
9339 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
9342 return cond0
? cond0
: cond1
;
9345 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9346 operands is zero when the other is nonzero, and vice-versa,
9347 and STORE_FLAG_VALUE is 1 or -1. */
9349 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9350 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
9352 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9354 rtx op0
= XEXP (XEXP (x
, 0), 1);
9355 rtx op1
= XEXP (XEXP (x
, 1), 1);
9357 cond0
= XEXP (XEXP (x
, 0), 0);
9358 cond1
= XEXP (XEXP (x
, 1), 0);
9360 if (COMPARISON_P (cond0
)
9361 && COMPARISON_P (cond1
)
9362 && SCALAR_INT_MODE_P (mode
)
9363 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9364 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9365 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9366 || ((swap_condition (GET_CODE (cond0
))
9367 == reversed_comparison_code (cond1
, NULL
))
9368 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9369 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9370 && ! side_effects_p (x
))
9372 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
9373 *pfalse
= simplify_gen_binary (MULT
, mode
,
9375 ? simplify_gen_unary (NEG
, mode
,
9383 /* Similarly for MULT, AND and UMIN, except that for these the result
9385 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9386 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
9387 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9389 cond0
= XEXP (XEXP (x
, 0), 0);
9390 cond1
= XEXP (XEXP (x
, 1), 0);
9392 if (COMPARISON_P (cond0
)
9393 && COMPARISON_P (cond1
)
9394 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9395 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9396 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9397 || ((swap_condition (GET_CODE (cond0
))
9398 == reversed_comparison_code (cond1
, NULL
))
9399 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9400 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9401 && ! side_effects_p (x
))
9403 *ptrue
= *pfalse
= const0_rtx
;
9409 else if (code
== IF_THEN_ELSE
)
9411 /* If we have IF_THEN_ELSE already, extract the condition and
9412 canonicalize it if it is NE or EQ. */
9413 cond0
= XEXP (x
, 0);
9414 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
9415 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
9416 return XEXP (cond0
, 0);
9417 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
9419 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
9420 return XEXP (cond0
, 0);
9426 /* If X is a SUBREG, we can narrow both the true and false values
9427 if the inner expression, if there is a condition. */
9428 else if (code
== SUBREG
9429 && (cond0
= if_then_else_cond (SUBREG_REG (x
), &true0
,
9432 true0
= simplify_gen_subreg (mode
, true0
,
9433 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9434 false0
= simplify_gen_subreg (mode
, false0
,
9435 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9436 if (true0
&& false0
)
9444 /* If X is a constant, this isn't special and will cause confusions
9445 if we treat it as such. Likewise if it is equivalent to a constant. */
9446 else if (CONSTANT_P (x
)
9447 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9450 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9451 will be least confusing to the rest of the compiler. */
9452 else if (mode
== BImode
)
9454 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9458 /* If X is known to be either 0 or -1, those are the true and
9459 false values when testing X. */
9460 else if (x
== constm1_rtx
|| x
== const0_rtx
9461 || (is_a
<scalar_int_mode
> (mode
, &int_mode
)
9462 && (num_sign_bit_copies (x
, int_mode
)
9463 == GET_MODE_PRECISION (int_mode
))))
9465 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9469 /* Likewise for 0 or a single bit. */
9470 else if (HWI_COMPUTABLE_MODE_P (mode
)
9471 && pow2p_hwi (nz
= nonzero_bits (x
, mode
)))
9473 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9477 /* Otherwise fail; show no condition with true and false values the same. */
9478 *ptrue
= *pfalse
= x
;
9482 /* Return the value of expression X given the fact that condition COND
9483 is known to be true when applied to REG as its first operand and VAL
9484 as its second. X is known to not be shared and so can be modified in
9487 We only handle the simplest cases, and specifically those cases that
9488 arise with IF_THEN_ELSE expressions. */
9491 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9493 enum rtx_code code
= GET_CODE (x
);
9497 if (side_effects_p (x
))
9500 /* If either operand of the condition is a floating point value,
9501 then we have to avoid collapsing an EQ comparison. */
9503 && rtx_equal_p (x
, reg
)
9504 && ! FLOAT_MODE_P (GET_MODE (x
))
9505 && ! FLOAT_MODE_P (GET_MODE (val
)))
9508 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9511 /* If X is (abs REG) and we know something about REG's relationship
9512 with zero, we may be able to simplify this. */
9514 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9517 case GE
: case GT
: case EQ
:
9520 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9522 GET_MODE (XEXP (x
, 0)));
9527 /* The only other cases we handle are MIN, MAX, and comparisons if the
9528 operands are the same as REG and VAL. */
9530 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9532 if (rtx_equal_p (XEXP (x
, 0), val
))
9534 std::swap (val
, reg
);
9535 cond
= swap_condition (cond
);
9538 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9540 if (COMPARISON_P (x
))
9542 if (comparison_dominates_p (cond
, code
))
9543 return VECTOR_MODE_P (GET_MODE (x
)) ? x
: const_true_rtx
;
9545 code
= reversed_comparison_code (x
, NULL
);
9547 && comparison_dominates_p (cond
, code
))
9548 return CONST0_RTX (GET_MODE (x
));
9552 else if (code
== SMAX
|| code
== SMIN
9553 || code
== UMIN
|| code
== UMAX
)
9555 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9557 /* Do not reverse the condition when it is NE or EQ.
9558 This is because we cannot conclude anything about
9559 the value of 'SMAX (x, y)' when x is not equal to y,
9560 but we can when x equals y. */
9561 if ((code
== SMAX
|| code
== UMAX
)
9562 && ! (cond
== EQ
|| cond
== NE
))
9563 cond
= reverse_condition (cond
);
9568 return unsignedp
? x
: XEXP (x
, 1);
9570 return unsignedp
? x
: XEXP (x
, 0);
9572 return unsignedp
? XEXP (x
, 1) : x
;
9574 return unsignedp
? XEXP (x
, 0) : x
;
9581 else if (code
== SUBREG
)
9583 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9584 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9586 if (SUBREG_REG (x
) != r
)
9588 /* We must simplify subreg here, before we lose track of the
9589 original inner_mode. */
9590 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9591 inner_mode
, SUBREG_BYTE (x
));
9595 SUBST (SUBREG_REG (x
), r
);
9600 /* We don't have to handle SIGN_EXTEND here, because even in the
9601 case of replacing something with a modeless CONST_INT, a
9602 CONST_INT is already (supposed to be) a valid sign extension for
9603 its narrower mode, which implies it's already properly
9604 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9605 story is different. */
9606 else if (code
== ZERO_EXTEND
)
9608 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9609 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9611 if (XEXP (x
, 0) != r
)
9613 /* We must simplify the zero_extend here, before we lose
9614 track of the original inner_mode. */
9615 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9620 SUBST (XEXP (x
, 0), r
);
9626 fmt
= GET_RTX_FORMAT (code
);
9627 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9630 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9631 else if (fmt
[i
] == 'E')
9632 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9633 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9640 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9641 assignment as a field assignment. */
9644 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9646 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9648 if (paradoxical_subreg_p (GET_MODE (x
), GET_MODE (y
)))
9650 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9652 x
= adjust_address_nv (x
, GET_MODE (y
),
9653 byte_lowpart_offset (GET_MODE (y
),
9657 if (x
== y
|| rtx_equal_p (x
, y
))
9660 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9663 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9664 Note that all SUBREGs of MEM are paradoxical; otherwise they
9665 would have been rewritten. */
9666 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9667 && MEM_P (SUBREG_REG (y
))
9668 && rtx_equal_p (SUBREG_REG (y
),
9669 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9672 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9673 && MEM_P (SUBREG_REG (x
))
9674 && rtx_equal_p (SUBREG_REG (x
),
9675 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9678 /* We used to see if get_last_value of X and Y were the same but that's
9679 not correct. In one direction, we'll cause the assignment to have
9680 the wrong destination and in the case, we'll import a register into this
9681 insn that might have already have been dead. So fail if none of the
9682 above cases are true. */
9686 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9687 Return that assignment if so.
9689 We only handle the most common cases. */
9692 make_field_assignment (rtx x
)
9694 rtx dest
= SET_DEST (x
);
9695 rtx src
= SET_SRC (x
);
9700 unsigned HOST_WIDE_INT len
;
9703 /* All the rules in this function are specific to scalar integers. */
9704 scalar_int_mode mode
;
9705 if (!is_a
<scalar_int_mode
> (GET_MODE (dest
), &mode
))
9708 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9709 a clear of a one-bit field. We will have changed it to
9710 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9713 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9714 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9715 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9716 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9718 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9719 1, true, true, false);
9721 return gen_rtx_SET (assign
, const0_rtx
);
9725 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9726 && subreg_lowpart_p (XEXP (src
, 0))
9727 && partial_subreg_p (XEXP (src
, 0))
9728 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9729 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9730 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9731 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9733 assign
= make_extraction (VOIDmode
, dest
, 0,
9734 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9735 1, true, true, false);
9737 return gen_rtx_SET (assign
, const0_rtx
);
9741 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9743 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9744 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9745 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9747 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9748 1, true, true, false);
9750 return gen_rtx_SET (assign
, const1_rtx
);
9754 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9755 SRC is an AND with all bits of that field set, then we can discard
9757 if (GET_CODE (dest
) == ZERO_EXTRACT
9758 && CONST_INT_P (XEXP (dest
, 1))
9759 && GET_CODE (src
) == AND
9760 && CONST_INT_P (XEXP (src
, 1)))
9762 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9763 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9764 unsigned HOST_WIDE_INT ze_mask
;
9766 if (width
>= HOST_BITS_PER_WIDE_INT
)
9769 ze_mask
= (HOST_WIDE_INT_1U
<< width
) - 1;
9771 /* Complete overlap. We can remove the source AND. */
9772 if ((and_mask
& ze_mask
) == ze_mask
)
9773 return gen_rtx_SET (dest
, XEXP (src
, 0));
9775 /* Partial overlap. We can reduce the source AND. */
9776 if ((and_mask
& ze_mask
) != and_mask
)
9778 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9779 gen_int_mode (and_mask
& ze_mask
, mode
));
9780 return gen_rtx_SET (dest
, src
);
9784 /* The other case we handle is assignments into a constant-position
9785 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9786 a mask that has all one bits except for a group of zero bits and
9787 OTHER is known to have zeros where C1 has ones, this is such an
9788 assignment. Compute the position and length from C1. Shift OTHER
9789 to the appropriate position, force it to the required mode, and
9790 make the extraction. Check for the AND in both operands. */
9792 /* One or more SUBREGs might obscure the constant-position field
9793 assignment. The first one we are likely to encounter is an outer
9794 narrowing SUBREG, which we can just strip for the purposes of
9795 identifying the constant-field assignment. */
9796 scalar_int_mode src_mode
= mode
;
9797 if (GET_CODE (src
) == SUBREG
9798 && subreg_lowpart_p (src
)
9799 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (src
)), &src_mode
))
9800 src
= SUBREG_REG (src
);
9802 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9805 rhs
= expand_compound_operation (XEXP (src
, 0));
9806 lhs
= expand_compound_operation (XEXP (src
, 1));
9808 if (GET_CODE (rhs
) == AND
9809 && CONST_INT_P (XEXP (rhs
, 1))
9810 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9811 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9812 /* The second SUBREG that might get in the way is a paradoxical
9813 SUBREG around the first operand of the AND. We want to
9814 pretend the operand is as wide as the destination here. We
9815 do this by adjusting the MEM to wider mode for the sole
9816 purpose of the call to rtx_equal_for_field_assignment_p. Also
9817 note this trick only works for MEMs. */
9818 else if (GET_CODE (rhs
) == AND
9819 && paradoxical_subreg_p (XEXP (rhs
, 0))
9820 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9821 && CONST_INT_P (XEXP (rhs
, 1))
9822 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9824 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9825 else if (GET_CODE (lhs
) == AND
9826 && CONST_INT_P (XEXP (lhs
, 1))
9827 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9828 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9829 /* The second SUBREG that might get in the way is a paradoxical
9830 SUBREG around the first operand of the AND. We want to
9831 pretend the operand is as wide as the destination here. We
9832 do this by adjusting the MEM to wider mode for the sole
9833 purpose of the call to rtx_equal_for_field_assignment_p. Also
9834 note this trick only works for MEMs. */
9835 else if (GET_CODE (lhs
) == AND
9836 && paradoxical_subreg_p (XEXP (lhs
, 0))
9837 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9838 && CONST_INT_P (XEXP (lhs
, 1))
9839 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9841 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9845 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (mode
), &len
);
9847 || pos
+ len
> GET_MODE_PRECISION (mode
)
9848 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
9849 || (c1
& nonzero_bits (other
, mode
)) != 0)
9852 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
,
9857 /* The mode to use for the source is the mode of the assignment, or of
9858 what is inside a possible STRICT_LOW_PART. */
9859 machine_mode new_mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9860 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9862 /* Shift OTHER right POS places and make it the source, restricting it
9863 to the proper length and mode. */
9865 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9866 src_mode
, other
, pos
),
9868 src
= force_to_mode (src
, new_mode
,
9869 len
>= HOST_BITS_PER_WIDE_INT
9871 : (HOST_WIDE_INT_1U
<< len
) - 1, false);
9873 /* If SRC is masked by an AND that does not make a difference in
9874 the value being stored, strip it. */
9875 if (GET_CODE (assign
) == ZERO_EXTRACT
9876 && CONST_INT_P (XEXP (assign
, 1))
9877 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9878 && GET_CODE (src
) == AND
9879 && CONST_INT_P (XEXP (src
, 1))
9880 && UINTVAL (XEXP (src
, 1))
9881 == (HOST_WIDE_INT_1U
<< INTVAL (XEXP (assign
, 1))) - 1)
9882 src
= XEXP (src
, 0);
9884 return gen_rtx_SET (assign
, src
);
9887 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9891 apply_distributive_law (rtx x
)
9893 enum rtx_code code
= GET_CODE (x
);
9894 enum rtx_code inner_code
;
9895 rtx lhs
, rhs
, other
;
9898 /* Distributivity is not true for floating point as it can change the
9899 value. So we don't do it unless -funsafe-math-optimizations. */
9900 if (FLOAT_MODE_P (GET_MODE (x
))
9901 && ! flag_unsafe_math_optimizations
)
9904 /* The outer operation can only be one of the following: */
9905 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9906 && code
!= PLUS
&& code
!= MINUS
)
9912 /* If either operand is a primitive we can't do anything, so get out
9914 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9917 lhs
= expand_compound_operation (lhs
);
9918 rhs
= expand_compound_operation (rhs
);
9919 inner_code
= GET_CODE (lhs
);
9920 if (inner_code
!= GET_CODE (rhs
))
9923 /* See if the inner and outer operations distribute. */
9930 /* These all distribute except over PLUS. */
9931 if (code
== PLUS
|| code
== MINUS
)
9936 if (code
!= PLUS
&& code
!= MINUS
)
9941 /* This is also a multiply, so it distributes over everything. */
9944 /* This used to handle SUBREG, but this turned out to be counter-
9945 productive, since (subreg (op ...)) usually is not handled by
9946 insn patterns, and this "optimization" therefore transformed
9947 recognizable patterns into unrecognizable ones. Therefore the
9948 SUBREG case was removed from here.
9950 It is possible that distributing SUBREG over arithmetic operations
9951 leads to an intermediate result than can then be optimized further,
9952 e.g. by moving the outer SUBREG to the other side of a SET as done
9953 in simplify_set. This seems to have been the original intent of
9954 handling SUBREGs here.
9956 However, with current GCC this does not appear to actually happen,
9957 at least on major platforms. If some case is found where removing
9958 the SUBREG case here prevents follow-on optimizations, distributing
9959 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9965 /* Set LHS and RHS to the inner operands (A and B in the example
9966 above) and set OTHER to the common operand (C in the example).
9967 There is only one way to do this unless the inner operation is
9969 if (COMMUTATIVE_ARITH_P (lhs
)
9970 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9971 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9972 else if (COMMUTATIVE_ARITH_P (lhs
)
9973 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9974 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9975 else if (COMMUTATIVE_ARITH_P (lhs
)
9976 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9977 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9978 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9979 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9983 /* Form the new inner operation, seeing if it simplifies first. */
9984 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9986 /* There is one exception to the general way of distributing:
9987 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9988 if (code
== XOR
&& inner_code
== IOR
)
9991 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9994 /* We may be able to continuing distributing the result, so call
9995 ourselves recursively on the inner operation before forming the
9996 outer operation, which we return. */
9997 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9998 apply_distributive_law (tem
), other
);
10001 /* See if X is of the form (* (+ A B) C), and if so convert to
10002 (+ (* A C) (* B C)) and try to simplify.
10004 Most of the time, this results in no change. However, if some of
10005 the operands are the same or inverses of each other, simplifications
10008 For example, (and (ior A B) (not B)) can occur as the result of
10009 expanding a bit field assignment. When we apply the distributive
10010 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
10011 which then simplifies to (and (A (not B))).
10013 Note that no checks happen on the validity of applying the inverse
10014 distributive law. This is pointless since we can do it in the
10015 few places where this routine is called.
10017 N is the index of the term that is decomposed (the arithmetic operation,
10018 i.e. (+ A B) in the first example above). !N is the index of the term that
10019 is distributed, i.e. of C in the first example above. */
10021 distribute_and_simplify_rtx (rtx x
, int n
)
10024 enum rtx_code outer_code
, inner_code
;
10025 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
10027 /* Distributivity is not true for floating point as it can change the
10028 value. So we don't do it unless -funsafe-math-optimizations. */
10029 if (FLOAT_MODE_P (GET_MODE (x
))
10030 && ! flag_unsafe_math_optimizations
)
10033 decomposed
= XEXP (x
, n
);
10034 if (!ARITHMETIC_P (decomposed
))
10037 mode
= GET_MODE (x
);
10038 outer_code
= GET_CODE (x
);
10039 distributed
= XEXP (x
, !n
);
10041 inner_code
= GET_CODE (decomposed
);
10042 inner_op0
= XEXP (decomposed
, 0);
10043 inner_op1
= XEXP (decomposed
, 1);
10045 /* Special case (and (xor B C) (not A)), which is equivalent to
10046 (xor (ior A B) (ior A C)) */
10047 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
10049 distributed
= XEXP (distributed
, 0);
10055 /* Distribute the second term. */
10056 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
10057 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
10061 /* Distribute the first term. */
10062 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
10063 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
10066 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
10067 new_op0
, new_op1
));
10068 if (GET_CODE (tmp
) != outer_code
10069 && (set_src_cost (tmp
, mode
, optimize_this_for_speed_p
)
10070 < set_src_cost (x
, mode
, optimize_this_for_speed_p
)))
10076 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10077 in MODE. Return an equivalent form, if different from (and VAROP
10078 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10081 simplify_and_const_int_1 (scalar_int_mode mode
, rtx varop
,
10082 unsigned HOST_WIDE_INT constop
)
10084 unsigned HOST_WIDE_INT nonzero
;
10085 unsigned HOST_WIDE_INT orig_constop
;
10089 orig_varop
= varop
;
10090 orig_constop
= constop
;
10091 if (GET_CODE (varop
) == CLOBBER
)
10094 /* Simplify VAROP knowing that we will be only looking at some of the
10097 Note by passing in CONSTOP, we guarantee that the bits not set in
10098 CONSTOP are not significant and will never be examined. We must
10099 ensure that is the case by explicitly masking out those bits
10100 before returning. */
10101 varop
= force_to_mode (varop
, mode
, constop
, false);
10103 /* If VAROP is a CLOBBER, we will fail so return it. */
10104 if (GET_CODE (varop
) == CLOBBER
)
10107 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10108 to VAROP and return the new constant. */
10109 if (CONST_INT_P (varop
))
10110 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
10112 /* See what bits may be nonzero in VAROP. Unlike the general case of
10113 a call to nonzero_bits, here we don't care about bits outside
10114 MODE unless WORD_REGISTER_OPERATIONS is true. */
10116 scalar_int_mode tmode
= mode
;
10117 if (WORD_REGISTER_OPERATIONS
&& GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
10119 nonzero
= nonzero_bits (varop
, tmode
) & GET_MODE_MASK (tmode
);
10121 /* Turn off all bits in the constant that are known to already be zero.
10122 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10123 which is tested below. */
10125 constop
&= nonzero
;
10127 /* If we don't have any bits left, return zero. */
10128 if (constop
== 0 && !side_effects_p (varop
))
10131 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10132 a power of two, we can replace this with an ASHIFT. */
10133 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), tmode
) == 1
10134 && (i
= exact_log2 (constop
)) >= 0)
10135 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
10137 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10138 or XOR, then try to apply the distributive law. This may eliminate
10139 operations if either branch can be simplified because of the AND.
10140 It may also make some cases more complex, but those cases probably
10141 won't match a pattern either with or without this. */
10143 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
10145 scalar_int_mode varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10149 apply_distributive_law
10150 (simplify_gen_binary (GET_CODE (varop
), varop_mode
,
10151 simplify_and_const_int (NULL_RTX
, varop_mode
,
10154 simplify_and_const_int (NULL_RTX
, varop_mode
,
10159 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10160 the AND and see if one of the operands simplifies to zero. If so, we
10161 may eliminate it. */
10163 if (GET_CODE (varop
) == PLUS
10164 && pow2p_hwi (constop
+ 1))
10168 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
10169 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
10170 if (o0
== const0_rtx
)
10172 if (o1
== const0_rtx
)
10176 /* Make a SUBREG if necessary. If we can't make it, fail. */
10177 varop
= gen_lowpart (mode
, varop
);
10178 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10181 /* If we are only masking insignificant bits, return VAROP. */
10182 if (constop
== nonzero
)
10185 if (varop
== orig_varop
&& constop
== orig_constop
)
10188 /* Otherwise, return an AND. */
10189 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
10193 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10196 Return an equivalent form, if different from X. Otherwise, return X. If
10197 X is zero, we are to always construct the equivalent form. */
10200 simplify_and_const_int (rtx x
, scalar_int_mode mode
, rtx varop
,
10201 unsigned HOST_WIDE_INT constop
)
10203 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
10208 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
10209 gen_int_mode (constop
, mode
));
10210 if (GET_MODE (x
) != mode
)
10211 x
= gen_lowpart (mode
, x
);
10215 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10216 We don't care about bits outside of those defined in MODE.
10217 We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
10219 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10220 a shift, AND, or zero_extract, we can do better. */
10223 reg_nonzero_bits_for_combine (const_rtx x
, scalar_int_mode xmode
,
10224 scalar_int_mode mode
,
10225 unsigned HOST_WIDE_INT
*nonzero
)
10228 reg_stat_type
*rsp
;
10230 /* If X is a register whose nonzero bits value is current, use it.
10231 Otherwise, if X is a register whose value we can find, use that
10232 value. Otherwise, use the previously-computed global nonzero bits
10233 for this register. */
10235 rsp
= ®_stat
[REGNO (x
)];
10236 if (rsp
->last_set_value
!= 0
10237 && (rsp
->last_set_mode
== mode
10238 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10239 && GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
10240 && GET_MODE_CLASS (mode
) == MODE_INT
))
10241 && ((rsp
->last_set_label
>= label_tick_ebb_start
10242 && rsp
->last_set_label
< label_tick
)
10243 || (rsp
->last_set_label
== label_tick
10244 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10245 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10246 && REGNO (x
) < reg_n_sets_max
10247 && REG_N_SETS (REGNO (x
)) == 1
10248 && !REGNO_REG_SET_P
10249 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10252 /* Note that, even if the precision of last_set_mode is lower than that
10253 of mode, record_value_for_reg invoked nonzero_bits on the register
10254 with nonzero_bits_mode (because last_set_mode is necessarily integral
10255 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10256 are all valid, hence in mode too since nonzero_bits_mode is defined
10257 to the largest HWI_COMPUTABLE_MODE_P mode. */
10258 *nonzero
&= rsp
->last_set_nonzero_bits
;
10262 tem
= get_last_value (x
);
10265 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
10266 tem
= sign_extend_short_imm (tem
, xmode
, GET_MODE_PRECISION (mode
));
10271 if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
10273 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
10275 if (GET_MODE_PRECISION (xmode
) < GET_MODE_PRECISION (mode
))
10276 /* We don't know anything about the upper bits. */
10277 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (xmode
);
10285 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10286 end of X that are known to be equal to the sign bit. X will be used
10287 in mode MODE; the returned value will always be between 1 and the
10288 number of bits in MODE. */
10291 reg_num_sign_bit_copies_for_combine (const_rtx x
, scalar_int_mode xmode
,
10292 scalar_int_mode mode
,
10293 unsigned int *result
)
10296 reg_stat_type
*rsp
;
10298 rsp
= ®_stat
[REGNO (x
)];
10299 if (rsp
->last_set_value
!= 0
10300 && rsp
->last_set_mode
== mode
10301 && ((rsp
->last_set_label
>= label_tick_ebb_start
10302 && rsp
->last_set_label
< label_tick
)
10303 || (rsp
->last_set_label
== label_tick
10304 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
10305 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
10306 && REGNO (x
) < reg_n_sets_max
10307 && REG_N_SETS (REGNO (x
)) == 1
10308 && !REGNO_REG_SET_P
10309 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
10312 *result
= rsp
->last_set_sign_bit_copies
;
10316 tem
= get_last_value (x
);
10320 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
10321 && GET_MODE_PRECISION (xmode
) == GET_MODE_PRECISION (mode
))
10322 *result
= rsp
->sign_bit_copies
;
10327 /* Return the number of "extended" bits there are in X, when interpreted
10328 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10329 unsigned quantities, this is the number of high-order zero bits.
10330 For signed quantities, this is the number of copies of the sign bit
10331 minus 1. In both case, this function returns the number of "spare"
10332 bits. For example, if two quantities for which this function returns
10333 at least 1 are added, the addition is known not to overflow.
10335 This function will always return 0 unless called during combine, which
10336 implies that it must be called from a define_split. */
10339 extended_count (const_rtx x
, machine_mode mode
, bool unsignedp
)
10341 if (nonzero_sign_valid
== 0)
10344 scalar_int_mode int_mode
;
10346 ? (is_a
<scalar_int_mode
> (mode
, &int_mode
)
10347 && HWI_COMPUTABLE_MODE_P (int_mode
)
10348 ? (unsigned int) (GET_MODE_PRECISION (int_mode
) - 1
10349 - floor_log2 (nonzero_bits (x
, int_mode
)))
10351 : num_sign_bit_copies (x
, mode
) - 1);
10354 /* This function is called from `simplify_shift_const' to merge two
10355 outer operations. Specifically, we have already found that we need
10356 to perform operation *POP0 with constant *PCONST0 at the outermost
10357 position. We would now like to also perform OP1 with constant CONST1
10358 (with *POP0 being done last).
10360 Return true if we can do the operation and update *POP0 and *PCONST0 with
10361 the resulting operation. *PCOMP_P is set to true if we would need to
10362 complement the innermost operand, otherwise it is unchanged.
10364 MODE is the mode in which the operation will be done. No bits outside
10365 the width of this mode matter. It is assumed that the width of this mode
10366 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10368 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10369 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10370 result is simply *PCONST0.
10372 If the resulting operation cannot be expressed as one operation, we
10373 return false and do not change *POP0, *PCONST0, and *PCOMP_P. */
10376 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
,
10377 enum rtx_code op1
, HOST_WIDE_INT const1
,
10378 machine_mode mode
, bool *pcomp_p
)
10380 enum rtx_code op0
= *pop0
;
10381 HOST_WIDE_INT const0
= *pconst0
;
10383 const0
&= GET_MODE_MASK (mode
);
10384 const1
&= GET_MODE_MASK (mode
);
10386 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10390 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10393 if (op1
== UNKNOWN
|| op0
== SET
)
10396 else if (op0
== UNKNOWN
)
10397 op0
= op1
, const0
= const1
;
10399 else if (op0
== op1
)
10423 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10424 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
10427 /* If the two constants aren't the same, we can't do anything. The
10428 remaining six cases can all be done. */
10429 else if (const0
!= const1
)
10437 /* (a & b) | b == b */
10439 else /* op1 == XOR */
10440 /* (a ^ b) | b == a | b */
10446 /* (a & b) ^ b == (~a) & b */
10447 op0
= AND
, *pcomp_p
= true;
10448 else /* op1 == IOR */
10449 /* (a | b) ^ b == a & ~b */
10450 op0
= AND
, const0
= ~const0
;
10455 /* (a | b) & b == b */
10457 else /* op1 == XOR */
10458 /* (a ^ b) & b) == (~a) & b */
10465 /* Check for NO-OP cases. */
10466 const0
&= GET_MODE_MASK (mode
);
10468 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10470 else if (const0
== 0 && op0
== AND
)
10472 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10478 /* ??? Slightly redundant with the above mask, but not entirely.
10479 Moving this above means we'd have to sign-extend the mode mask
10480 for the final test. */
10481 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10482 *pconst0
= trunc_int_for_mode (const0
, mode
);
10487 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10488 the shift in. The original shift operation CODE is performed on OP in
10489 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10490 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10491 result of the shift is subject to operation OUTER_CODE with operand
10494 static scalar_int_mode
10495 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10496 scalar_int_mode orig_mode
, scalar_int_mode mode
,
10497 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10499 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10501 /* In general we can't perform in wider mode for right shift and rotate. */
10505 /* We can still widen if the bits brought in from the left are identical
10506 to the sign bit of ORIG_MODE. */
10507 if (num_sign_bit_copies (op
, mode
)
10508 > (unsigned) (GET_MODE_PRECISION (mode
)
10509 - GET_MODE_PRECISION (orig_mode
)))
10514 /* Similarly here but with zero bits. */
10515 if (HWI_COMPUTABLE_MODE_P (mode
)
10516 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10519 /* We can also widen if the bits brought in will be masked off. This
10520 operation is performed in ORIG_MODE. */
10521 if (outer_code
== AND
)
10523 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10526 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10535 gcc_unreachable ();
10542 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10543 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10544 if we cannot simplify it. Otherwise, return a simplified value.
10546 The shift is normally computed in the widest mode we find in VAROP, as
10547 long as it isn't a different number of words than RESULT_MODE. Exceptions
10548 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10551 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10552 rtx varop
, int orig_count
)
10554 enum rtx_code orig_code
= code
;
10555 rtx orig_varop
= varop
;
10557 machine_mode mode
= result_mode
;
10558 machine_mode shift_mode
;
10559 scalar_int_mode tmode
, inner_mode
, int_mode
, int_varop_mode
, int_result_mode
;
10560 /* We form (outer_op (code varop count) (outer_const)). */
10561 enum rtx_code outer_op
= UNKNOWN
;
10562 HOST_WIDE_INT outer_const
= 0;
10563 bool complement_p
= false;
10566 /* Make sure and truncate the "natural" shift on the way in. We don't
10567 want to do this inside the loop as it makes it more difficult to
10569 if (SHIFT_COUNT_TRUNCATED
)
10570 orig_count
&= GET_MODE_UNIT_BITSIZE (mode
) - 1;
10572 /* If we were given an invalid count, don't do anything except exactly
10573 what was requested. */
10575 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_UNIT_PRECISION (mode
))
10578 count
= orig_count
;
10580 /* Unless one of the branches of the `if' in this loop does a `continue',
10581 we will `break' the loop after the `if'. */
10585 /* If we have an operand of (clobber (const_int 0)), fail. */
10586 if (GET_CODE (varop
) == CLOBBER
)
10589 /* Convert ROTATERT to ROTATE. */
10590 if (code
== ROTATERT
)
10592 unsigned int bitsize
= GET_MODE_UNIT_PRECISION (result_mode
);
10594 count
= bitsize
- count
;
10597 shift_mode
= result_mode
;
10598 if (shift_mode
!= mode
)
10600 /* We only change the modes of scalar shifts. */
10601 int_mode
= as_a
<scalar_int_mode
> (mode
);
10602 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
10603 shift_mode
= try_widen_shift_mode (code
, varop
, count
,
10604 int_result_mode
, int_mode
,
10605 outer_op
, outer_const
);
10608 scalar_int_mode shift_unit_mode
10609 = as_a
<scalar_int_mode
> (GET_MODE_INNER (shift_mode
));
10611 /* Handle cases where the count is greater than the size of the mode
10612 minus 1. For ASHIFT, use the size minus one as the count (this can
10613 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10614 take the count modulo the size. For other shifts, the result is
10617 Since these shifts are being produced by the compiler by combining
10618 multiple operations, each of which are defined, we know what the
10619 result is supposed to be. */
10621 if (count
> (GET_MODE_PRECISION (shift_unit_mode
) - 1))
10623 if (code
== ASHIFTRT
)
10624 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10625 else if (code
== ROTATE
|| code
== ROTATERT
)
10626 count
%= GET_MODE_PRECISION (shift_unit_mode
);
10629 /* We can't simply return zero because there may be an
10631 varop
= const0_rtx
;
10637 /* If we discovered we had to complement VAROP, leave. Making a NOT
10638 here would cause an infinite loop. */
10642 if (shift_mode
== shift_unit_mode
)
10644 /* An arithmetic right shift of a quantity known to be -1 or 0
10646 if (code
== ASHIFTRT
10647 && (num_sign_bit_copies (varop
, shift_unit_mode
)
10648 == GET_MODE_PRECISION (shift_unit_mode
)))
10654 /* If we are doing an arithmetic right shift and discarding all but
10655 the sign bit copies, this is equivalent to doing a shift by the
10656 bitsize minus one. Convert it into that shift because it will
10657 often allow other simplifications. */
10659 if (code
== ASHIFTRT
10660 && (count
+ num_sign_bit_copies (varop
, shift_unit_mode
)
10661 >= GET_MODE_PRECISION (shift_unit_mode
)))
10662 count
= GET_MODE_PRECISION (shift_unit_mode
) - 1;
10664 /* We simplify the tests below and elsewhere by converting
10665 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10666 `make_compound_operation' will convert it to an ASHIFTRT for
10667 those machines (such as VAX) that don't have an LSHIFTRT. */
10668 if (code
== ASHIFTRT
10669 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10670 && val_signbit_known_clear_p (shift_unit_mode
,
10671 nonzero_bits (varop
,
10675 if (((code
== LSHIFTRT
10676 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10677 && !(nonzero_bits (varop
, shift_unit_mode
) >> count
))
10679 && HWI_COMPUTABLE_MODE_P (shift_unit_mode
)
10680 && !((nonzero_bits (varop
, shift_unit_mode
) << count
)
10681 & GET_MODE_MASK (shift_unit_mode
))))
10682 && !side_effects_p (varop
))
10683 varop
= const0_rtx
;
10686 switch (GET_CODE (varop
))
10692 new_rtx
= expand_compound_operation (varop
);
10693 if (new_rtx
!= varop
)
10701 /* The following rules apply only to scalars. */
10702 if (shift_mode
!= shift_unit_mode
)
10704 int_mode
= as_a
<scalar_int_mode
> (mode
);
10706 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10707 minus the width of a smaller mode, we can do this with a
10708 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10709 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10710 && ! mode_dependent_address_p (XEXP (varop
, 0),
10711 MEM_ADDR_SPACE (varop
))
10712 && ! MEM_VOLATILE_P (varop
)
10713 && (int_mode_for_size (GET_MODE_BITSIZE (int_mode
) - count
, 1)
10716 new_rtx
= adjust_address_nv (varop
, tmode
,
10717 BYTES_BIG_ENDIAN
? 0
10718 : count
/ BITS_PER_UNIT
);
10720 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10721 : ZERO_EXTEND
, int_mode
, new_rtx
);
10728 /* The following rules apply only to scalars. */
10729 if (shift_mode
!= shift_unit_mode
)
10731 int_mode
= as_a
<scalar_int_mode
> (mode
);
10732 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10734 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10735 the same number of words as what we've seen so far. Then store
10736 the widest mode in MODE. */
10737 if (subreg_lowpart_p (varop
)
10738 && is_int_mode (GET_MODE (SUBREG_REG (varop
)), &inner_mode
)
10739 && GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (int_varop_mode
)
10740 && (CEIL (GET_MODE_SIZE (inner_mode
), UNITS_PER_WORD
)
10741 == CEIL (GET_MODE_SIZE (int_mode
), UNITS_PER_WORD
))
10742 && GET_MODE_CLASS (int_varop_mode
) == MODE_INT
)
10744 varop
= SUBREG_REG (varop
);
10745 if (GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (int_mode
))
10752 /* Some machines use MULT instead of ASHIFT because MULT
10753 is cheaper. But it is still better on those machines to
10754 merge two shifts into one. */
10755 if (CONST_INT_P (XEXP (varop
, 1))
10756 && (log2
= exact_log2 (UINTVAL (XEXP (varop
, 1)))) >= 0)
10758 rtx log2_rtx
= gen_int_shift_amount (GET_MODE (varop
), log2
);
10759 varop
= simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10760 XEXP (varop
, 0), log2_rtx
);
10766 /* Similar, for when divides are cheaper. */
10767 if (CONST_INT_P (XEXP (varop
, 1))
10768 && (log2
= exact_log2 (UINTVAL (XEXP (varop
, 1)))) >= 0)
10770 rtx log2_rtx
= gen_int_shift_amount (GET_MODE (varop
), log2
);
10771 varop
= simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10772 XEXP (varop
, 0), log2_rtx
);
10778 /* If we are extracting just the sign bit of an arithmetic
10779 right shift, that shift is not needed. However, the sign
10780 bit of a wider mode may be different from what would be
10781 interpreted as the sign bit in a narrower mode, so, if
10782 the result is narrower, don't discard the shift. */
10783 if (code
== LSHIFTRT
10784 && count
== (GET_MODE_UNIT_BITSIZE (result_mode
) - 1)
10785 && (GET_MODE_UNIT_BITSIZE (result_mode
)
10786 >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop
))))
10788 varop
= XEXP (varop
, 0);
10797 /* The following rules apply only to scalars. */
10798 if (shift_mode
!= shift_unit_mode
)
10800 int_mode
= as_a
<scalar_int_mode
> (mode
);
10801 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10802 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
10804 /* Here we have two nested shifts. The result is usually the
10805 AND of a new shift with a mask. We compute the result below. */
10806 if (CONST_INT_P (XEXP (varop
, 1))
10807 && INTVAL (XEXP (varop
, 1)) >= 0
10808 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (int_varop_mode
)
10809 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
10810 && HWI_COMPUTABLE_MODE_P (int_mode
))
10812 enum rtx_code first_code
= GET_CODE (varop
);
10813 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10814 unsigned HOST_WIDE_INT mask
;
10817 /* We have one common special case. We can't do any merging if
10818 the inner code is an ASHIFTRT of a smaller mode. However, if
10819 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10820 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10821 we can convert it to
10822 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10823 This simplifies certain SIGN_EXTEND operations. */
10824 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10825 && count
== (GET_MODE_PRECISION (int_result_mode
)
10826 - GET_MODE_PRECISION (int_varop_mode
)))
10828 /* C3 has the low-order C1 bits zero. */
10830 mask
= GET_MODE_MASK (int_mode
)
10831 & ~((HOST_WIDE_INT_1U
<< first_count
) - 1);
10833 varop
= simplify_and_const_int (NULL_RTX
, int_result_mode
,
10834 XEXP (varop
, 0), mask
);
10835 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
,
10836 int_result_mode
, varop
, count
);
10837 count
= first_count
;
10842 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10843 than C1 high-order bits equal to the sign bit, we can convert
10844 this to either an ASHIFT or an ASHIFTRT depending on the
10847 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10849 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10850 && int_varop_mode
== shift_unit_mode
10851 && (num_sign_bit_copies (XEXP (varop
, 0), shift_unit_mode
)
10854 varop
= XEXP (varop
, 0);
10855 count
-= first_count
;
10865 /* There are some cases we can't do. If CODE is ASHIFTRT,
10866 we can only do this if FIRST_CODE is also ASHIFTRT.
10868 We can't do the case when CODE is ROTATE and FIRST_CODE is
10871 If the mode of this shift is not the mode of the outer shift,
10872 we can't do this if either shift is a right shift or ROTATE.
10874 Finally, we can't do any of these if the mode is too wide
10875 unless the codes are the same.
10877 Handle the case where the shift codes are the same
10880 if (code
== first_code
)
10882 if (int_varop_mode
!= int_result_mode
10883 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10884 || code
== ROTATE
))
10887 count
+= first_count
;
10888 varop
= XEXP (varop
, 0);
10892 if (code
== ASHIFTRT
10893 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10894 || GET_MODE_PRECISION (int_mode
) > HOST_BITS_PER_WIDE_INT
10895 || (int_varop_mode
!= int_result_mode
10896 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10897 || first_code
== ROTATE
10898 || code
== ROTATE
)))
10901 /* To compute the mask to apply after the shift, shift the
10902 nonzero bits of the inner shift the same way the
10903 outer shift will. */
10905 mask_rtx
= gen_int_mode (nonzero_bits (varop
, int_varop_mode
),
10907 rtx count_rtx
= gen_int_shift_amount (int_result_mode
, count
);
10909 = simplify_const_binary_operation (code
, int_result_mode
,
10910 mask_rtx
, count_rtx
);
10912 /* Give up if we can't compute an outer operation to use. */
10914 || !CONST_INT_P (mask_rtx
)
10915 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10917 int_result_mode
, &complement_p
))
10920 /* If the shifts are in the same direction, we add the
10921 counts. Otherwise, we subtract them. */
10922 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10923 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10924 count
+= first_count
;
10926 count
-= first_count
;
10928 /* If COUNT is positive, the new shift is usually CODE,
10929 except for the two exceptions below, in which case it is
10930 FIRST_CODE. If the count is negative, FIRST_CODE should
10933 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10934 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10936 else if (count
< 0)
10937 code
= first_code
, count
= -count
;
10939 varop
= XEXP (varop
, 0);
10943 /* If we have (A << B << C) for any shift, we can convert this to
10944 (A << C << B). This wins if A is a constant. Only try this if
10945 B is not a constant. */
10947 else if (GET_CODE (varop
) == code
10948 && CONST_INT_P (XEXP (varop
, 0))
10949 && !CONST_INT_P (XEXP (varop
, 1)))
10951 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10952 sure the result will be masked. See PR70222. */
10953 if (code
== LSHIFTRT
10954 && int_mode
!= int_result_mode
10955 && !merge_outer_ops (&outer_op
, &outer_const
, AND
,
10956 GET_MODE_MASK (int_result_mode
)
10957 >> orig_count
, int_result_mode
,
10960 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10961 up outer sign extension (often left and right shift) is
10962 hardly more efficient than the original. See PR70429.
10963 Similarly punt for rotates with different modes.
10965 if ((code
== ASHIFTRT
|| code
== ROTATE
)
10966 && int_mode
!= int_result_mode
)
10969 rtx count_rtx
= gen_int_shift_amount (int_result_mode
, count
);
10970 rtx new_rtx
= simplify_const_binary_operation (code
, int_mode
,
10973 varop
= gen_rtx_fmt_ee (code
, int_mode
, new_rtx
, XEXP (varop
, 1));
10980 /* The following rules apply only to scalars. */
10981 if (shift_mode
!= shift_unit_mode
)
10984 /* Make this fit the case below. */
10985 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10991 /* The following rules apply only to scalars. */
10992 if (shift_mode
!= shift_unit_mode
)
10994 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
10995 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
10997 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10998 with C the size of VAROP - 1 and the shift is logical if
10999 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11000 we have an (le X 0) operation. If we have an arithmetic shift
11001 and STORE_FLAG_VALUE is 1 or we have a logical shift with
11002 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
11004 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
11005 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
11006 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
11007 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
11008 && count
== (GET_MODE_PRECISION (int_varop_mode
) - 1)
11009 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
11012 varop
= gen_rtx_LE (int_varop_mode
, XEXP (varop
, 1),
11015 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
11016 varop
= gen_rtx_NEG (int_varop_mode
, varop
);
11021 /* If we have (shift (logical)), move the logical to the outside
11022 to allow it to possibly combine with another logical and the
11023 shift to combine with another shift. This also canonicalizes to
11024 what a ZERO_EXTRACT looks like. Also, some machines have
11025 (and (shift)) insns. */
11027 if (CONST_INT_P (XEXP (varop
, 1))
11028 /* We can't do this if we have (ashiftrt (xor)) and the
11029 constant has its sign bit set in shift_unit_mode with
11030 shift_unit_mode wider than result_mode. */
11031 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
11032 && int_result_mode
!= shift_unit_mode
11033 && trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
11034 shift_unit_mode
) < 0)
11035 && (new_rtx
= simplify_const_binary_operation
11036 (code
, int_result_mode
,
11037 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
11038 gen_int_shift_amount (int_result_mode
, count
))) != 0
11039 && CONST_INT_P (new_rtx
)
11040 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
11041 INTVAL (new_rtx
), int_result_mode
,
11044 varop
= XEXP (varop
, 0);
11048 /* If we can't do that, try to simplify the shift in each arm of the
11049 logical expression, make a new logical expression, and apply
11050 the inverse distributive law. This also can't be done for
11051 (ashiftrt (xor)) where we've widened the shift and the constant
11052 changes the sign bit. */
11053 if (CONST_INT_P (XEXP (varop
, 1))
11054 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
11055 && int_result_mode
!= shift_unit_mode
11056 && trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
11057 shift_unit_mode
) < 0))
11059 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_unit_mode
,
11060 XEXP (varop
, 0), count
);
11061 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_unit_mode
,
11062 XEXP (varop
, 1), count
);
11064 varop
= simplify_gen_binary (GET_CODE (varop
), shift_unit_mode
,
11066 varop
= apply_distributive_law (varop
);
11074 /* The following rules apply only to scalars. */
11075 if (shift_mode
!= shift_unit_mode
)
11077 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11079 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11080 says that the sign bit can be tested, FOO has mode MODE, C is
11081 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11082 that may be nonzero. */
11083 if (code
== LSHIFTRT
11084 && XEXP (varop
, 1) == const0_rtx
11085 && GET_MODE (XEXP (varop
, 0)) == int_result_mode
11086 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
11087 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
11088 && STORE_FLAG_VALUE
== -1
11089 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1
11090 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1,
11091 int_result_mode
, &complement_p
))
11093 varop
= XEXP (varop
, 0);
11100 /* The following rules apply only to scalars. */
11101 if (shift_mode
!= shift_unit_mode
)
11103 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11105 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11106 than the number of bits in the mode is equivalent to A. */
11107 if (code
== LSHIFTRT
11108 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
11109 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1)
11111 varop
= XEXP (varop
, 0);
11116 /* NEG commutes with ASHIFT since it is multiplication. Move the
11117 NEG outside to allow shifts to combine. */
11119 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0,
11120 int_result_mode
, &complement_p
))
11122 varop
= XEXP (varop
, 0);
11128 /* The following rules apply only to scalars. */
11129 if (shift_mode
!= shift_unit_mode
)
11131 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11133 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11134 is one less than the number of bits in the mode is
11135 equivalent to (xor A 1). */
11136 if (code
== LSHIFTRT
11137 && count
== (GET_MODE_PRECISION (int_result_mode
) - 1)
11138 && XEXP (varop
, 1) == constm1_rtx
11139 && nonzero_bits (XEXP (varop
, 0), int_result_mode
) == 1
11140 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1,
11141 int_result_mode
, &complement_p
))
11144 varop
= XEXP (varop
, 0);
11148 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11149 that might be nonzero in BAR are those being shifted out and those
11150 bits are known zero in FOO, we can replace the PLUS with FOO.
11151 Similarly in the other operand order. This code occurs when
11152 we are computing the size of a variable-size array. */
11154 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
11155 && count
< HOST_BITS_PER_WIDE_INT
11156 && nonzero_bits (XEXP (varop
, 1), int_result_mode
) >> count
== 0
11157 && (nonzero_bits (XEXP (varop
, 1), int_result_mode
)
11158 & nonzero_bits (XEXP (varop
, 0), int_result_mode
)) == 0)
11160 varop
= XEXP (varop
, 0);
11163 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
11164 && count
< HOST_BITS_PER_WIDE_INT
11165 && HWI_COMPUTABLE_MODE_P (int_result_mode
)
11166 && (nonzero_bits (XEXP (varop
, 0), int_result_mode
)
11168 && (nonzero_bits (XEXP (varop
, 0), int_result_mode
)
11169 & nonzero_bits (XEXP (varop
, 1), int_result_mode
)) == 0)
11171 varop
= XEXP (varop
, 1);
11175 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11177 && CONST_INT_P (XEXP (varop
, 1))
11178 && (new_rtx
= simplify_const_binary_operation
11179 (ASHIFT
, int_result_mode
,
11180 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
11181 gen_int_shift_amount (int_result_mode
, count
))) != 0
11182 && CONST_INT_P (new_rtx
)
11183 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
11184 INTVAL (new_rtx
), int_result_mode
,
11187 varop
= XEXP (varop
, 0);
11191 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11192 signbit', and attempt to change the PLUS to an XOR and move it to
11193 the outer operation as is done above in the AND/IOR/XOR case
11194 leg for shift(logical). See details in logical handling above
11195 for reasoning in doing so. */
11196 if (code
== LSHIFTRT
11197 && CONST_INT_P (XEXP (varop
, 1))
11198 && mode_signbit_p (int_result_mode
, XEXP (varop
, 1))
11199 && (new_rtx
= simplify_const_binary_operation
11200 (code
, int_result_mode
,
11201 gen_int_mode (INTVAL (XEXP (varop
, 1)), int_result_mode
),
11202 gen_int_shift_amount (int_result_mode
, count
))) != 0
11203 && CONST_INT_P (new_rtx
)
11204 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
11205 INTVAL (new_rtx
), int_result_mode
,
11208 varop
= XEXP (varop
, 0);
11215 /* The following rules apply only to scalars. */
11216 if (shift_mode
!= shift_unit_mode
)
11218 int_varop_mode
= as_a
<scalar_int_mode
> (GET_MODE (varop
));
11220 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11221 with C the size of VAROP - 1 and the shift is logical if
11222 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11223 we have a (gt X 0) operation. If the shift is arithmetic with
11224 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11225 we have a (neg (gt X 0)) operation. */
11227 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
11228 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
11229 && count
== (GET_MODE_PRECISION (int_varop_mode
) - 1)
11230 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
11231 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11232 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
11233 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
11236 varop
= gen_rtx_GT (int_varop_mode
, XEXP (varop
, 1),
11239 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
11240 varop
= gen_rtx_NEG (int_varop_mode
, varop
);
11247 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11248 if the truncate does not affect the value. */
11249 if (code
== LSHIFTRT
11250 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
11251 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
11252 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
11253 >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop
, 0)))
11254 - GET_MODE_UNIT_PRECISION (GET_MODE (varop
)))))
11256 rtx varop_inner
= XEXP (varop
, 0);
11257 int new_count
= count
+ INTVAL (XEXP (varop_inner
, 1));
11258 rtx new_count_rtx
= gen_int_shift_amount (GET_MODE (varop_inner
),
11260 varop_inner
= gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
11261 XEXP (varop_inner
, 0),
11263 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
11276 shift_mode
= result_mode
;
11277 if (shift_mode
!= mode
)
11279 /* We only change the modes of scalar shifts. */
11280 int_mode
= as_a
<scalar_int_mode
> (mode
);
11281 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11282 shift_mode
= try_widen_shift_mode (code
, varop
, count
, int_result_mode
,
11283 int_mode
, outer_op
, outer_const
);
11286 /* We have now finished analyzing the shift. The result should be
11287 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11288 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11289 to the result of the shift. OUTER_CONST is the relevant constant,
11290 but we must turn off all bits turned off in the shift. */
11292 if (outer_op
== UNKNOWN
11293 && orig_code
== code
&& orig_count
== count
11294 && varop
== orig_varop
11295 && shift_mode
== GET_MODE (varop
))
11298 /* Make a SUBREG if necessary. If we can't make it, fail. */
11299 varop
= gen_lowpart (shift_mode
, varop
);
11300 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
11303 /* If we have an outer operation and we just made a shift, it is
11304 possible that we could have simplified the shift were it not
11305 for the outer operation. So try to do the simplification
11308 if (outer_op
!= UNKNOWN
)
11309 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
11314 x
= simplify_gen_binary (code
, shift_mode
, varop
,
11315 gen_int_shift_amount (shift_mode
, count
));
11317 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11318 turn off all the bits that the shift would have turned off. */
11319 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
11320 /* We only change the modes of scalar shifts. */
11321 x
= simplify_and_const_int (NULL_RTX
, as_a
<scalar_int_mode
> (shift_mode
),
11322 x
, GET_MODE_MASK (result_mode
) >> orig_count
);
11324 /* Do the remainder of the processing in RESULT_MODE. */
11325 x
= gen_lowpart_or_truncate (result_mode
, x
);
11327 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11330 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
11332 if (outer_op
!= UNKNOWN
)
11334 int_result_mode
= as_a
<scalar_int_mode
> (result_mode
);
11336 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
11337 && GET_MODE_PRECISION (int_result_mode
) < HOST_BITS_PER_WIDE_INT
)
11338 outer_const
= trunc_int_for_mode (outer_const
, int_result_mode
);
11340 if (outer_op
== AND
)
11341 x
= simplify_and_const_int (NULL_RTX
, int_result_mode
, x
, outer_const
);
11342 else if (outer_op
== SET
)
11344 /* This means that we have determined that the result is
11345 equivalent to a constant. This should be rare. */
11346 if (!side_effects_p (x
))
11347 x
= GEN_INT (outer_const
);
11349 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
11350 x
= simplify_gen_unary (outer_op
, int_result_mode
, x
, int_result_mode
);
11352 x
= simplify_gen_binary (outer_op
, int_result_mode
, x
,
11353 GEN_INT (outer_const
));
11359 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11360 The result of the shift is RESULT_MODE. If we cannot simplify it,
11361 return X or, if it is NULL, synthesize the expression with
11362 simplify_gen_binary. Otherwise, return a simplified value.
11364 The shift is normally computed in the widest mode we find in VAROP, as
11365 long as it isn't a different number of words than RESULT_MODE. Exceptions
11366 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11369 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
11370 rtx varop
, int count
)
11372 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
11377 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
,
11378 gen_int_shift_amount (GET_MODE (varop
), count
));
11379 if (GET_MODE (x
) != result_mode
)
11380 x
= gen_lowpart (result_mode
, x
);
11385 /* A subroutine of recog_for_combine. See there for arguments and
11389 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11391 rtx pat
= *pnewpat
;
11392 rtx pat_without_clobbers
;
11393 int insn_code_number
;
11394 int num_clobbers_to_add
= 0;
11396 rtx notes
= NULL_RTX
;
11397 rtx old_notes
, old_pat
;
11400 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11401 we use to indicate that something didn't match. If we find such a
11402 thing, force rejection. */
11403 if (GET_CODE (pat
) == PARALLEL
)
11404 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
11405 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
11406 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
11409 old_pat
= PATTERN (insn
);
11410 old_notes
= REG_NOTES (insn
);
11411 PATTERN (insn
) = pat
;
11412 REG_NOTES (insn
) = NULL_RTX
;
11414 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11415 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11417 if (insn_code_number
< 0)
11418 fputs ("Failed to match this instruction:\n", dump_file
);
11420 fputs ("Successfully matched this instruction:\n", dump_file
);
11421 print_rtl_single (dump_file
, pat
);
11424 /* If it isn't, there is the possibility that we previously had an insn
11425 that clobbered some register as a side effect, but the combined
11426 insn doesn't need to do that. So try once more without the clobbers
11427 unless this represents an ASM insn. */
11429 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
11430 && GET_CODE (pat
) == PARALLEL
)
11434 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
11435 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
11438 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
11442 SUBST_INT (XVECLEN (pat
, 0), pos
);
11445 pat
= XVECEXP (pat
, 0, 0);
11447 PATTERN (insn
) = pat
;
11448 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11449 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11451 if (insn_code_number
< 0)
11452 fputs ("Failed to match this instruction:\n", dump_file
);
11454 fputs ("Successfully matched this instruction:\n", dump_file
);
11455 print_rtl_single (dump_file
, pat
);
11459 pat_without_clobbers
= pat
;
11461 PATTERN (insn
) = old_pat
;
11462 REG_NOTES (insn
) = old_notes
;
11464 /* Recognize all noop sets, these will be killed by followup pass. */
11465 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
11466 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
11468 /* If we had any clobbers to add, make a new pattern than contains
11469 them. Then check to make sure that all of them are dead. */
11470 if (num_clobbers_to_add
)
11472 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
11473 rtvec_alloc (GET_CODE (pat
) == PARALLEL
11474 ? (XVECLEN (pat
, 0)
11475 + num_clobbers_to_add
)
11476 : num_clobbers_to_add
+ 1));
11478 if (GET_CODE (pat
) == PARALLEL
)
11479 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11480 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
11482 XVECEXP (newpat
, 0, 0) = pat
;
11484 add_clobbers (newpat
, insn_code_number
);
11486 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
11487 i
< XVECLEN (newpat
, 0); i
++)
11489 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
11490 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
11492 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
11494 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
11495 notes
= alloc_reg_note (REG_UNUSED
,
11496 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
11502 if (insn_code_number
>= 0
11503 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
11505 old_pat
= PATTERN (insn
);
11506 old_notes
= REG_NOTES (insn
);
11507 old_icode
= INSN_CODE (insn
);
11508 PATTERN (insn
) = pat
;
11509 REG_NOTES (insn
) = notes
;
11510 INSN_CODE (insn
) = insn_code_number
;
11512 /* Allow targets to reject combined insn. */
11513 if (!targetm
.legitimate_combined_insn (insn
))
11515 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11516 fputs ("Instruction not appropriate for target.",
11519 /* Callers expect recog_for_combine to strip
11520 clobbers from the pattern on failure. */
11521 pat
= pat_without_clobbers
;
11524 insn_code_number
= -1;
11527 PATTERN (insn
) = old_pat
;
11528 REG_NOTES (insn
) = old_notes
;
11529 INSN_CODE (insn
) = old_icode
;
11535 return insn_code_number
;
11538 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11539 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11540 Return whether anything was so changed. */
11543 change_zero_ext (rtx pat
)
11545 bool changed
= false;
11546 rtx
*src
= &SET_SRC (pat
);
11548 subrtx_ptr_iterator::array_type array
;
11549 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11552 scalar_int_mode mode
, inner_mode
;
11553 if (!is_a
<scalar_int_mode
> (GET_MODE (x
), &mode
))
11557 if (GET_CODE (x
) == ZERO_EXTRACT
11558 && CONST_INT_P (XEXP (x
, 1))
11559 && CONST_INT_P (XEXP (x
, 2))
11560 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &inner_mode
)
11561 && GET_MODE_PRECISION (inner_mode
) <= GET_MODE_PRECISION (mode
))
11563 size
= INTVAL (XEXP (x
, 1));
11565 int start
= INTVAL (XEXP (x
, 2));
11566 if (BITS_BIG_ENDIAN
)
11567 start
= GET_MODE_PRECISION (inner_mode
) - size
- start
;
11570 x
= gen_rtx_LSHIFTRT (inner_mode
, XEXP (x
, 0),
11571 gen_int_shift_amount (inner_mode
, start
));
11575 if (mode
!= inner_mode
)
11577 if (REG_P (x
) && HARD_REGISTER_P (x
)
11578 && !can_change_dest_mode (x
, 0, mode
))
11581 x
= gen_lowpart_SUBREG (mode
, x
);
11584 else if (GET_CODE (x
) == ZERO_EXTEND
11585 && GET_CODE (XEXP (x
, 0)) == SUBREG
11586 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x
, 0))))
11587 && !paradoxical_subreg_p (XEXP (x
, 0))
11588 && subreg_lowpart_p (XEXP (x
, 0)))
11590 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
11591 size
= GET_MODE_PRECISION (inner_mode
);
11592 x
= SUBREG_REG (XEXP (x
, 0));
11593 if (GET_MODE (x
) != mode
)
11595 if (REG_P (x
) && HARD_REGISTER_P (x
)
11596 && !can_change_dest_mode (x
, 0, mode
))
11599 x
= gen_lowpart_SUBREG (mode
, x
);
11602 else if (GET_CODE (x
) == ZERO_EXTEND
11603 && REG_P (XEXP (x
, 0))
11604 && HARD_REGISTER_P (XEXP (x
, 0))
11605 && can_change_dest_mode (XEXP (x
, 0), 0, mode
))
11607 inner_mode
= as_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)));
11608 size
= GET_MODE_PRECISION (inner_mode
);
11609 x
= gen_rtx_REG (mode
, REGNO (XEXP (x
, 0)));
11614 if (!(GET_CODE (x
) == LSHIFTRT
11615 && CONST_INT_P (XEXP (x
, 1))
11616 && size
+ INTVAL (XEXP (x
, 1)) == GET_MODE_PRECISION (mode
)))
11618 wide_int mask
= wi::mask (size
, false, GET_MODE_PRECISION (mode
));
11619 x
= gen_rtx_AND (mode
, x
, immed_wide_int_const (mask
, mode
));
11627 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11628 maybe_swap_commutative_operands (**iter
);
11630 rtx
*dst
= &SET_DEST (pat
);
11631 scalar_int_mode mode
;
11632 if (GET_CODE (*dst
) == ZERO_EXTRACT
11633 && REG_P (XEXP (*dst
, 0))
11634 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (*dst
, 0)), &mode
)
11635 && CONST_INT_P (XEXP (*dst
, 1))
11636 && CONST_INT_P (XEXP (*dst
, 2)))
11638 rtx reg
= XEXP (*dst
, 0);
11639 int width
= INTVAL (XEXP (*dst
, 1));
11640 int offset
= INTVAL (XEXP (*dst
, 2));
11641 int reg_width
= GET_MODE_PRECISION (mode
);
11642 if (BITS_BIG_ENDIAN
)
11643 offset
= reg_width
- width
- offset
;
11646 wide_int mask
= wi::shifted_mask (offset
, width
, true, reg_width
);
11647 wide_int mask2
= wi::shifted_mask (offset
, width
, false, reg_width
);
11648 x
= gen_rtx_AND (mode
, reg
, immed_wide_int_const (mask
, mode
));
11650 y
= gen_rtx_ASHIFT (mode
, SET_SRC (pat
), GEN_INT (offset
));
11653 z
= gen_rtx_AND (mode
, y
, immed_wide_int_const (mask2
, mode
));
11654 w
= gen_rtx_IOR (mode
, x
, z
);
11655 SUBST (SET_DEST (pat
), reg
);
11656 SUBST (SET_SRC (pat
), w
);
11664 /* Like recog, but we receive the address of a pointer to a new pattern.
11665 We try to match the rtx that the pointer points to.
11666 If that fails, we may try to modify or replace the pattern,
11667 storing the replacement into the same pointer object.
11669 Modifications include deletion or addition of CLOBBERs. If the
11670 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11671 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11672 (and undo if that fails).
11674 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11675 the CLOBBERs are placed.
11677 The value is the final insn code from the pattern ultimately matched,
11681 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11683 rtx pat
= *pnewpat
;
11684 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11685 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11686 return insn_code_number
;
11688 void *marker
= get_undo_marker ();
11689 bool changed
= false;
11691 if (GET_CODE (pat
) == SET
)
11693 /* For an unrecognized single set of a constant, try placing it in
11694 the constant pool, if this function already uses one. */
11695 rtx src
= SET_SRC (pat
);
11696 if (CONSTANT_P (src
)
11697 && !CONST_INT_P (src
)
11698 && crtl
->uses_const_pool
)
11700 machine_mode mode
= GET_MODE (src
);
11701 if (mode
== VOIDmode
)
11702 mode
= GET_MODE (SET_DEST (pat
));
11703 src
= force_const_mem (mode
, src
);
11706 SUBST (SET_SRC (pat
), src
);
11711 changed
= change_zero_ext (pat
);
11713 else if (GET_CODE (pat
) == PARALLEL
)
11716 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11718 rtx set
= XVECEXP (pat
, 0, i
);
11719 if (GET_CODE (set
) == SET
)
11720 changed
|= change_zero_ext (set
);
11726 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11728 if (insn_code_number
< 0)
11729 undo_to_marker (marker
);
11732 return insn_code_number
;
11735 /* Like gen_lowpart_general but for use by combine. In combine it
11736 is not possible to create any new pseudoregs. However, it is
11737 safe to create invalid memory addresses, because combine will
11738 try to recognize them and all they will do is make the combine
11741 If for some reason this cannot do its job, an rtx
11742 (clobber (const_int 0)) is returned.
11743 An insn containing that will not be recognized. */
11746 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11748 machine_mode imode
= GET_MODE (x
);
11751 if (omode
== imode
)
11754 /* We can only support MODE being wider than a word if X is a
11755 constant integer or has a mode the same size. */
11756 if (maybe_gt (GET_MODE_SIZE (omode
), UNITS_PER_WORD
)
11757 && ! (CONST_SCALAR_INT_P (x
)
11758 || known_eq (GET_MODE_SIZE (imode
), GET_MODE_SIZE (omode
))))
11761 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11762 won't know what to do. So we will strip off the SUBREG here and
11763 process normally. */
11764 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11766 x
= SUBREG_REG (x
);
11768 /* For use in case we fall down into the address adjustments
11769 further below, we need to adjust the known mode and size of
11770 x; imode and isize, since we just adjusted x. */
11771 imode
= GET_MODE (x
);
11773 if (imode
== omode
)
11777 result
= gen_lowpart_common (omode
, x
);
11784 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11786 if (MEM_VOLATILE_P (x
)
11787 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11790 /* If we want to refer to something bigger than the original memref,
11791 generate a paradoxical subreg instead. That will force a reload
11792 of the original memref X. */
11793 if (paradoxical_subreg_p (omode
, imode
))
11794 return gen_rtx_SUBREG (omode
, x
, 0);
11796 poly_int64 offset
= byte_lowpart_offset (omode
, imode
);
11797 return adjust_address_nv (x
, omode
, offset
);
11800 /* If X is a comparison operator, rewrite it in a new mode. This
11801 probably won't match, but may allow further simplifications. */
11802 else if (COMPARISON_P (x
)
11803 && SCALAR_INT_MODE_P (imode
)
11804 && SCALAR_INT_MODE_P (omode
))
11805 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11807 /* If we couldn't simplify X any other way, just enclose it in a
11808 SUBREG. Normally, this SUBREG won't match, but some patterns may
11809 include an explicit SUBREG or we may simplify it further in combine. */
11814 if (imode
== VOIDmode
)
11816 imode
= int_mode_for_mode (omode
).require ();
11817 x
= gen_lowpart_common (imode
, x
);
11821 res
= lowpart_subreg (omode
, x
, imode
);
11827 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11830 /* Try to simplify a comparison between OP0 and a constant OP1,
11831 where CODE is the comparison code that will be tested, into a
11832 (CODE OP0 const0_rtx) form.
11834 The result is a possibly different comparison code to use.
11835 *POP0 and *POP1 may be updated. */
11837 static enum rtx_code
11838 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11839 rtx
*pop0
, rtx
*pop1
)
11841 scalar_int_mode int_mode
;
11843 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11845 /* Get the constant we are comparing against and turn off all bits
11846 not on in our mode. */
11847 if (mode
!= VOIDmode
)
11848 const_op
= trunc_int_for_mode (const_op
, mode
);
11850 /* If we are comparing against a constant power of two and the value
11851 being compared can only have that single bit nonzero (e.g., it was
11852 `and'ed with that bit), we can replace this with a comparison
11855 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11856 || code
== LT
|| code
== LTU
)
11857 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11858 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11859 && pow2p_hwi (const_op
& GET_MODE_MASK (int_mode
))
11860 && (nonzero_bits (op0
, int_mode
)
11861 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (int_mode
))))
11863 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11867 /* Similarly, if we are comparing a value known to be either -1 or
11868 0 with -1, change it to the opposite comparison against zero. */
11870 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11871 || code
== GEU
|| code
== LTU
)
11872 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11873 && num_sign_bit_copies (op0
, int_mode
) == GET_MODE_PRECISION (int_mode
))
11875 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11879 /* Do some canonicalizations based on the comparison code. We prefer
11880 comparisons against zero and then prefer equality comparisons.
11881 If we can reduce the size of a constant, we will do that too. */
11885 /* < C is equivalent to <= (C - 1) */
11890 /* ... fall through to LE case below. */
11891 gcc_fallthrough ();
11897 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11904 /* If we are doing a <= 0 comparison on a value known to have
11905 a zero sign bit, we can replace this with == 0. */
11906 else if (const_op
== 0
11907 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11908 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11909 && (nonzero_bits (op0
, int_mode
)
11910 & (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11916 /* >= C is equivalent to > (C - 1). */
11921 /* ... fall through to GT below. */
11922 gcc_fallthrough ();
11928 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11935 /* If we are doing a > 0 comparison on a value known to have
11936 a zero sign bit, we can replace this with != 0. */
11937 else if (const_op
== 0
11938 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
11939 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11940 && (nonzero_bits (op0
, int_mode
)
11941 & (HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11947 /* < C is equivalent to <= (C - 1). */
11952 /* ... fall through ... */
11953 gcc_fallthrough ();
11955 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11956 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11957 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11958 && (((unsigned HOST_WIDE_INT
) const_op
& GET_MODE_MASK (int_mode
))
11959 == HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
11969 /* unsigned <= 0 is equivalent to == 0 */
11972 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11973 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11974 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11975 && ((unsigned HOST_WIDE_INT
) const_op
11976 == ((HOST_WIDE_INT_1U
11977 << (GET_MODE_PRECISION (int_mode
) - 1)) - 1)))
11985 /* >= C is equivalent to > (C - 1). */
11990 /* ... fall through ... */
11991 gcc_fallthrough ();
11994 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11995 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
11996 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
11997 && (((unsigned HOST_WIDE_INT
) const_op
& GET_MODE_MASK (int_mode
))
11998 == HOST_WIDE_INT_1U
<< (GET_MODE_PRECISION (int_mode
) - 1)))
12008 /* unsigned > 0 is equivalent to != 0 */
12011 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
12012 else if (is_a
<scalar_int_mode
> (mode
, &int_mode
)
12013 && GET_MODE_PRECISION (int_mode
) - 1 < HOST_BITS_PER_WIDE_INT
12014 && ((unsigned HOST_WIDE_INT
) const_op
12015 == (HOST_WIDE_INT_1U
12016 << (GET_MODE_PRECISION (int_mode
) - 1)) - 1))
12027 /* Narrow non-symmetric comparison of memory and constant as e.g.
12028 x0...x7 <= 0x3fffffffffffffff into x0 <= 0x3f where x0 is the most
12029 significant byte. Likewise, transform x0...x7 >= 0x4000000000000000 into
12031 if ((code
== LEU
|| code
== LTU
|| code
== GEU
|| code
== GTU
)
12032 && is_a
<scalar_int_mode
> (GET_MODE (op0
), &int_mode
)
12033 && HWI_COMPUTABLE_MODE_P (int_mode
)
12035 && !MEM_VOLATILE_P (op0
)
12036 /* The optimization makes only sense for constants which are big enough
12037 so that we have a chance to chop off something at all. */
12038 && ((unsigned HOST_WIDE_INT
) const_op
& GET_MODE_MASK (int_mode
)) > 0xff
12039 /* Ensure that we do not overflow during normalization. */
12041 || ((unsigned HOST_WIDE_INT
) const_op
& GET_MODE_MASK (int_mode
))
12042 < HOST_WIDE_INT_M1U
)
12043 && trunc_int_for_mode (const_op
, int_mode
) == const_op
)
12045 unsigned HOST_WIDE_INT n
12046 = (unsigned HOST_WIDE_INT
) const_op
& GET_MODE_MASK (int_mode
);
12047 enum rtx_code adjusted_code
;
12049 /* Normalize code to either LEU or GEU. */
12053 adjusted_code
= LEU
;
12055 else if (code
== GTU
)
12058 adjusted_code
= GEU
;
12061 adjusted_code
= code
;
12063 scalar_int_mode narrow_mode_iter
;
12064 FOR_EACH_MODE_UNTIL (narrow_mode_iter
, int_mode
)
12066 unsigned nbits
= GET_MODE_PRECISION (int_mode
)
12067 - GET_MODE_PRECISION (narrow_mode_iter
);
12068 unsigned HOST_WIDE_INT mask
= (HOST_WIDE_INT_1U
<< nbits
) - 1;
12069 unsigned HOST_WIDE_INT lower_bits
= n
& mask
;
12070 if ((adjusted_code
== LEU
&& lower_bits
== mask
)
12071 || (adjusted_code
== GEU
&& lower_bits
== 0))
12078 if (narrow_mode_iter
< int_mode
)
12080 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
12083 dump_file
, "narrow comparison from mode %s to %s: (MEM %s "
12084 HOST_WIDE_INT_PRINT_HEX
") to (MEM %s "
12085 HOST_WIDE_INT_PRINT_HEX
").\n", GET_MODE_NAME (int_mode
),
12086 GET_MODE_NAME (narrow_mode_iter
), GET_RTX_NAME (code
),
12087 (unsigned HOST_WIDE_INT
) const_op
& GET_MODE_MASK (int_mode
),
12088 GET_RTX_NAME (adjusted_code
), n
);
12090 poly_int64 offset
= (BYTES_BIG_ENDIAN
12092 : (GET_MODE_SIZE (int_mode
)
12093 - GET_MODE_SIZE (narrow_mode_iter
)));
12094 *pop0
= adjust_address_nv (op0
, narrow_mode_iter
, offset
);
12095 *pop1
= gen_int_mode (n
, narrow_mode_iter
);
12096 return adjusted_code
;
12100 *pop1
= GEN_INT (const_op
);
12104 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
12105 comparison code that will be tested.
12107 The result is a possibly different comparison code to use. *POP0 and
12108 *POP1 may be updated.
12110 It is possible that we might detect that a comparison is either always
12111 true or always false. However, we do not perform general constant
12112 folding in combine, so this knowledge isn't useful. Such tautologies
12113 should have been detected earlier. Hence we ignore all such cases. */
12115 static enum rtx_code
12116 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
12122 scalar_int_mode mode
, inner_mode
, tmode
;
12123 opt_scalar_int_mode tmode_iter
;
12125 /* Try a few ways of applying the same transformation to both operands. */
12128 /* The test below this one won't handle SIGN_EXTENDs on these machines,
12129 so check specially. */
12130 if (!WORD_REGISTER_OPERATIONS
12131 && code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
12132 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
12133 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12134 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
12135 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
12136 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
12137 && is_a
<scalar_int_mode
> (GET_MODE (op0
), &mode
)
12138 && (is_a
<scalar_int_mode
>
12139 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))), &inner_mode
))
12140 && inner_mode
== GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0)))
12141 && CONST_INT_P (XEXP (op0
, 1))
12142 && XEXP (op0
, 1) == XEXP (op1
, 1)
12143 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12144 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
12145 && (INTVAL (XEXP (op0
, 1))
12146 == (GET_MODE_PRECISION (mode
)
12147 - GET_MODE_PRECISION (inner_mode
))))
12149 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
12150 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
12153 /* If both operands are the same constant shift, see if we can ignore the
12154 shift. We can if the shift is a rotate or if the bits shifted out of
12155 this shift are known to be zero for both inputs and if the type of
12156 comparison is compatible with the shift. */
12157 if (GET_CODE (op0
) == GET_CODE (op1
)
12158 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
12159 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
12160 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
12161 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
12162 || (GET_CODE (op0
) == ASHIFTRT
12163 && (code
!= GTU
&& code
!= LTU
12164 && code
!= GEU
&& code
!= LEU
)))
12165 && CONST_INT_P (XEXP (op0
, 1))
12166 && INTVAL (XEXP (op0
, 1)) >= 0
12167 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12168 && XEXP (op0
, 1) == XEXP (op1
, 1))
12170 machine_mode mode
= GET_MODE (op0
);
12171 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
12172 int shift_count
= INTVAL (XEXP (op0
, 1));
12174 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
12175 mask
&= (mask
>> shift_count
) << shift_count
;
12176 else if (GET_CODE (op0
) == ASHIFT
)
12177 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
12179 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
12180 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
12181 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
12186 /* If both operands are AND's of a paradoxical SUBREG by constant, the
12187 SUBREGs are of the same mode, and, in both cases, the AND would
12188 be redundant if the comparison was done in the narrower mode,
12189 do the comparison in the narrower mode (e.g., we are AND'ing with 1
12190 and the operand's possibly nonzero bits are 0xffffff01; in that case
12191 if we only care about QImode, we don't need the AND). This case
12192 occurs if the output mode of an scc insn is not SImode and
12193 STORE_FLAG_VALUE == 1 (e.g., the 386).
12195 Similarly, check for a case where the AND's are ZERO_EXTEND
12196 operations from some narrower mode even though a SUBREG is not
12199 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
12200 && CONST_INT_P (XEXP (op0
, 1))
12201 && CONST_INT_P (XEXP (op1
, 1)))
12203 rtx inner_op0
= XEXP (op0
, 0);
12204 rtx inner_op1
= XEXP (op1
, 0);
12205 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
12206 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
12207 bool changed
= false;
12209 if (paradoxical_subreg_p (inner_op0
)
12210 && GET_CODE (inner_op1
) == SUBREG
12211 && HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0
)))
12212 && (GET_MODE (SUBREG_REG (inner_op0
))
12213 == GET_MODE (SUBREG_REG (inner_op1
)))
12214 && ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
12215 GET_MODE (SUBREG_REG (inner_op0
)))) == 0
12216 && ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
12217 GET_MODE (SUBREG_REG (inner_op1
)))) == 0)
12219 op0
= SUBREG_REG (inner_op0
);
12220 op1
= SUBREG_REG (inner_op1
);
12222 /* The resulting comparison is always unsigned since we masked
12223 off the original sign bit. */
12224 code
= unsigned_condition (code
);
12230 FOR_EACH_MODE_UNTIL (tmode
,
12231 as_a
<scalar_int_mode
> (GET_MODE (op0
)))
12232 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
12234 op0
= gen_lowpart_or_truncate (tmode
, inner_op0
);
12235 op1
= gen_lowpart_or_truncate (tmode
, inner_op1
);
12236 code
= unsigned_condition (code
);
12245 /* If both operands are NOT, we can strip off the outer operation
12246 and adjust the comparison code for swapped operands; similarly for
12247 NEG, except that this must be an equality comparison. */
12248 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
12249 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
12250 && (code
== EQ
|| code
== NE
)))
12251 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
12257 /* If the first operand is a constant, swap the operands and adjust the
12258 comparison code appropriately, but don't do this if the second operand
12259 is already a constant integer. */
12260 if (swap_commutative_operands_p (op0
, op1
))
12262 std::swap (op0
, op1
);
12263 code
= swap_condition (code
);
12266 /* We now enter a loop during which we will try to simplify the comparison.
12267 For the most part, we only are concerned with comparisons with zero,
12268 but some things may really be comparisons with zero but not start
12269 out looking that way. */
12271 while (CONST_INT_P (op1
))
12273 machine_mode raw_mode
= GET_MODE (op0
);
12274 scalar_int_mode int_mode
;
12275 int equality_comparison_p
;
12276 int sign_bit_comparison_p
;
12277 int unsigned_comparison_p
;
12278 HOST_WIDE_INT const_op
;
12280 /* We only want to handle integral modes. This catches VOIDmode,
12281 CCmode, and the floating-point modes. An exception is that we
12282 can handle VOIDmode if OP0 is a COMPARE or a comparison
12285 if (GET_MODE_CLASS (raw_mode
) != MODE_INT
12286 && ! (raw_mode
== VOIDmode
12287 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
12290 /* Try to simplify the compare to constant, possibly changing the
12291 comparison op, and/or changing op1 to zero. */
12292 code
= simplify_compare_const (code
, raw_mode
, &op0
, &op1
);
12293 const_op
= INTVAL (op1
);
12295 /* Compute some predicates to simplify code below. */
12297 equality_comparison_p
= (code
== EQ
|| code
== NE
);
12298 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
12299 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
12302 /* If this is a sign bit comparison and we can do arithmetic in
12303 MODE, say that we will only be needing the sign bit of OP0. */
12304 if (sign_bit_comparison_p
12305 && is_a
<scalar_int_mode
> (raw_mode
, &int_mode
)
12306 && HWI_COMPUTABLE_MODE_P (int_mode
))
12307 op0
= force_to_mode (op0
, int_mode
,
12309 << (GET_MODE_PRECISION (int_mode
) - 1), false);
12311 if (COMPARISON_P (op0
))
12313 /* We can't do anything if OP0 is a condition code value, rather
12314 than an actual data value. */
12316 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
12319 /* Get the two operands being compared. */
12320 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
12321 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
12323 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
12325 /* Check for the cases where we simply want the result of the
12326 earlier test or the opposite of that result. */
12327 if (code
== NE
|| code
== EQ
12328 || (val_signbit_known_set_p (raw_mode
, STORE_FLAG_VALUE
)
12329 && (code
== LT
|| code
== GE
)))
12331 enum rtx_code new_code
;
12332 if (code
== LT
|| code
== NE
)
12333 new_code
= GET_CODE (op0
);
12335 new_code
= reversed_comparison_code (op0
, NULL
);
12337 if (new_code
!= UNKNOWN
)
12348 if (raw_mode
== VOIDmode
)
12350 scalar_int_mode mode
= as_a
<scalar_int_mode
> (raw_mode
);
12352 /* Now try cases based on the opcode of OP0. If none of the cases
12353 does a "continue", we exit this loop immediately after the
12356 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
12357 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
12358 switch (GET_CODE (op0
))
12361 /* If we are extracting a single bit from a variable position in
12362 a constant that has only a single bit set and are comparing it
12363 with zero, we can convert this into an equality comparison
12364 between the position and the location of the single bit. */
12365 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12366 have already reduced the shift count modulo the word size. */
12367 if (!SHIFT_COUNT_TRUNCATED
12368 && CONST_INT_P (XEXP (op0
, 0))
12369 && XEXP (op0
, 1) == const1_rtx
12370 && equality_comparison_p
&& const_op
== 0
12371 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
12373 if (BITS_BIG_ENDIAN
)
12374 i
= BITS_PER_WORD
- 1 - i
;
12376 op0
= XEXP (op0
, 2);
12380 /* Result is nonzero iff shift count is equal to I. */
12381 code
= reverse_condition (code
);
12388 tem
= expand_compound_operation (op0
);
12397 /* If testing for equality, we can take the NOT of the constant. */
12398 if (equality_comparison_p
12399 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
12401 op0
= XEXP (op0
, 0);
12406 /* If just looking at the sign bit, reverse the sense of the
12408 if (sign_bit_comparison_p
)
12410 op0
= XEXP (op0
, 0);
12411 code
= (code
== GE
? LT
: GE
);
12417 /* If testing for equality, we can take the NEG of the constant. */
12418 if (equality_comparison_p
12419 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
12421 op0
= XEXP (op0
, 0);
12426 /* The remaining cases only apply to comparisons with zero. */
12430 /* When X is ABS or is known positive,
12431 (neg X) is < 0 if and only if X != 0. */
12433 if (sign_bit_comparison_p
12434 && (GET_CODE (XEXP (op0
, 0)) == ABS
12435 || (mode_width
<= HOST_BITS_PER_WIDE_INT
12436 && (nonzero_bits (XEXP (op0
, 0), mode
)
12437 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12440 op0
= XEXP (op0
, 0);
12441 code
= (code
== LT
? NE
: EQ
);
12445 /* If we have NEG of something whose two high-order bits are the
12446 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12447 if (num_sign_bit_copies (op0
, mode
) >= 2)
12449 op0
= XEXP (op0
, 0);
12450 code
= swap_condition (code
);
12456 /* If we are testing equality and our count is a constant, we
12457 can perform the inverse operation on our RHS. */
12458 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12459 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
12460 op1
, XEXP (op0
, 1))) != 0)
12462 op0
= XEXP (op0
, 0);
12467 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12468 a particular bit. Convert it to an AND of a constant of that
12469 bit. This will be converted into a ZERO_EXTRACT. */
12470 if (const_op
== 0 && sign_bit_comparison_p
12471 && CONST_INT_P (XEXP (op0
, 1))
12472 && mode_width
<= HOST_BITS_PER_WIDE_INT
12473 && UINTVAL (XEXP (op0
, 1)) < mode_width
)
12475 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12478 - INTVAL (XEXP (op0
, 1)))));
12479 code
= (code
== LT
? NE
: EQ
);
12483 /* Fall through. */
12486 /* ABS is ignorable inside an equality comparison with zero. */
12487 if (const_op
== 0 && equality_comparison_p
)
12489 op0
= XEXP (op0
, 0);
12495 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12496 (compare FOO CONST) if CONST fits in FOO's mode and we
12497 are either testing inequality or have an unsigned
12498 comparison with ZERO_EXTEND or a signed comparison with
12499 SIGN_EXTEND. But don't do it if we don't have a compare
12500 insn of the given mode, since we'd have to revert it
12501 later on, and then we wouldn't know whether to sign- or
12503 if (is_int_mode (GET_MODE (XEXP (op0
, 0)), &mode
)
12504 && ! unsigned_comparison_p
12505 && HWI_COMPUTABLE_MODE_P (mode
)
12506 && trunc_int_for_mode (const_op
, mode
) == const_op
12507 && have_insn_for (COMPARE
, mode
))
12509 op0
= XEXP (op0
, 0);
12515 /* Check for the case where we are comparing A - C1 with C2, that is
12517 (subreg:MODE (plus (A) (-C1))) op (C2)
12519 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12520 comparison in the wider mode. One of the following two conditions
12521 must be true in order for this to be valid:
12523 1. The mode extension results in the same bit pattern being added
12524 on both sides and the comparison is equality or unsigned. As
12525 C2 has been truncated to fit in MODE, the pattern can only be
12528 2. The mode extension results in the sign bit being copied on
12531 The difficulty here is that we have predicates for A but not for
12532 (A - C1) so we need to check that C1 is within proper bounds so
12533 as to perturbate A as little as possible. */
12535 if (mode_width
<= HOST_BITS_PER_WIDE_INT
12536 && subreg_lowpart_p (op0
)
12537 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (op0
)),
12539 && GET_MODE_PRECISION (inner_mode
) > mode_width
12540 && GET_CODE (SUBREG_REG (op0
)) == PLUS
12541 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
12543 rtx a
= XEXP (SUBREG_REG (op0
), 0);
12544 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
12547 && (unsigned HOST_WIDE_INT
) c1
12548 < HOST_WIDE_INT_1U
<< (mode_width
- 1)
12549 && (equality_comparison_p
|| unsigned_comparison_p
)
12550 /* (A - C1) zero-extends if it is positive and sign-extends
12551 if it is negative, C2 both zero- and sign-extends. */
12552 && (((nonzero_bits (a
, inner_mode
)
12553 & ~GET_MODE_MASK (mode
)) == 0
12555 /* (A - C1) sign-extends if it is positive and 1-extends
12556 if it is negative, C2 both sign- and 1-extends. */
12557 || (num_sign_bit_copies (a
, inner_mode
)
12558 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12561 || ((unsigned HOST_WIDE_INT
) c1
12562 < HOST_WIDE_INT_1U
<< (mode_width
- 2)
12563 /* (A - C1) always sign-extends, like C2. */
12564 && num_sign_bit_copies (a
, inner_mode
)
12565 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
12566 - (mode_width
- 1))))
12568 op0
= SUBREG_REG (op0
);
12573 /* If the inner mode is narrower and we are extracting the low part,
12574 we can treat the SUBREG as if it were a ZERO_EXTEND ... */
12575 if (paradoxical_subreg_p (op0
))
12577 if (WORD_REGISTER_OPERATIONS
12578 && is_a
<scalar_int_mode
> (GET_MODE (SUBREG_REG (op0
)),
12580 && GET_MODE_PRECISION (inner_mode
) < BITS_PER_WORD
12581 /* On WORD_REGISTER_OPERATIONS targets the bits
12582 beyond sub_mode aren't considered undefined,
12583 so optimize only if it is a MEM load when MEM loads
12584 zero extend, because then the upper bits are all zero. */
12585 && !(MEM_P (SUBREG_REG (op0
))
12586 && load_extend_op (inner_mode
) == ZERO_EXTEND
))
12588 /* FALLTHROUGH to case ZERO_EXTEND */
12590 else if (subreg_lowpart_p (op0
)
12591 && GET_MODE_CLASS (mode
) == MODE_INT
12592 && is_int_mode (GET_MODE (SUBREG_REG (op0
)), &inner_mode
)
12593 && (code
== NE
|| code
== EQ
)
12594 && GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
12595 && !paradoxical_subreg_p (op0
)
12596 && (nonzero_bits (SUBREG_REG (op0
), inner_mode
)
12597 & ~GET_MODE_MASK (mode
)) == 0)
12599 /* Remove outer subregs that don't do anything. */
12600 tem
= gen_lowpart (inner_mode
, op1
);
12602 if ((nonzero_bits (tem
, inner_mode
)
12603 & ~GET_MODE_MASK (mode
)) == 0)
12605 op0
= SUBREG_REG (op0
);
12617 if (is_int_mode (GET_MODE (XEXP (op0
, 0)), &mode
)
12618 && (unsigned_comparison_p
|| equality_comparison_p
)
12619 && HWI_COMPUTABLE_MODE_P (mode
)
12620 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
12622 && have_insn_for (COMPARE
, mode
))
12624 op0
= XEXP (op0
, 0);
12630 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12631 this for equality comparisons due to pathological cases involving
12633 if (equality_comparison_p
12634 && (tem
= simplify_binary_operation (MINUS
, mode
,
12635 op1
, XEXP (op0
, 1))) != 0)
12637 op0
= XEXP (op0
, 0);
12642 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12643 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
12644 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
12646 op0
= XEXP (XEXP (op0
, 0), 0);
12647 code
= (code
== LT
? EQ
: NE
);
12653 /* We used to optimize signed comparisons against zero, but that
12654 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12655 arrive here as equality comparisons, or (GEU, LTU) are
12656 optimized away. No need to special-case them. */
12658 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12659 (eq B (minus A C)), whichever simplifies. We can only do
12660 this for equality comparisons due to pathological cases involving
12662 if (equality_comparison_p
12663 && (tem
= simplify_binary_operation (PLUS
, mode
,
12664 XEXP (op0
, 1), op1
)) != 0)
12666 op0
= XEXP (op0
, 0);
12671 if (equality_comparison_p
12672 && (tem
= simplify_binary_operation (MINUS
, mode
,
12673 XEXP (op0
, 0), op1
)) != 0)
12675 op0
= XEXP (op0
, 1);
12680 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12681 of bits in X minus 1, is one iff X > 0. */
12682 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
12683 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12684 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
12685 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12687 op0
= XEXP (op0
, 1);
12688 code
= (code
== GE
? LE
: GT
);
12694 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12695 if C is zero or B is a constant. */
12696 if (equality_comparison_p
12697 && (tem
= simplify_binary_operation (XOR
, mode
,
12698 XEXP (op0
, 1), op1
)) != 0)
12700 op0
= XEXP (op0
, 0);
12708 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12710 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
12711 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
12712 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12714 op0
= XEXP (op0
, 1);
12715 code
= (code
== GE
? GT
: LE
);
12721 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12722 will be converted to a ZERO_EXTRACT later. */
12723 if (const_op
== 0 && equality_comparison_p
12724 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12725 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12727 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12728 XEXP (XEXP (op0
, 0), 1));
12729 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12733 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12734 zero and X is a comparison and C1 and C2 describe only bits set
12735 in STORE_FLAG_VALUE, we can compare with X. */
12736 if (const_op
== 0 && equality_comparison_p
12737 && mode_width
<= HOST_BITS_PER_WIDE_INT
12738 && CONST_INT_P (XEXP (op0
, 1))
12739 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12740 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12741 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12742 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12744 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12745 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12746 if ((~STORE_FLAG_VALUE
& mask
) == 0
12747 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12748 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12749 && COMPARISON_P (tem
))))
12751 op0
= XEXP (XEXP (op0
, 0), 0);
12756 /* If we are doing an equality comparison of an AND of a bit equal
12757 to the sign bit, replace this with a LT or GE comparison of
12758 the underlying value. */
12759 if (equality_comparison_p
12761 && CONST_INT_P (XEXP (op0
, 1))
12762 && mode_width
<= HOST_BITS_PER_WIDE_INT
12763 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12764 == HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12766 op0
= XEXP (op0
, 0);
12767 code
= (code
== EQ
? GE
: LT
);
12771 /* If this AND operation is really a ZERO_EXTEND from a narrower
12772 mode, the constant fits within that mode, and this is either an
12773 equality or unsigned comparison, try to do this comparison in
12778 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12779 -> (ne:DI (reg:SI 4) (const_int 0))
12781 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12782 known to hold a value of the required mode the
12783 transformation is invalid. */
12784 if ((equality_comparison_p
|| unsigned_comparison_p
)
12785 && CONST_INT_P (XEXP (op0
, 1))
12786 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12787 & GET_MODE_MASK (mode
))
12789 && const_op
>> i
== 0
12790 && int_mode_for_size (i
, 1).exists (&tmode
))
12792 op0
= gen_lowpart_or_truncate (tmode
, XEXP (op0
, 0));
12796 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12797 fits in both M1 and M2 and the SUBREG is either paradoxical
12798 or represents the low part, permute the SUBREG and the AND
12800 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
12801 && CONST_INT_P (XEXP (op0
, 1)))
12803 unsigned HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
12804 /* Require an integral mode, to avoid creating something like
12806 if ((is_a
<scalar_int_mode
>
12807 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))), &tmode
))
12808 /* It is unsafe to commute the AND into the SUBREG if the
12809 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12810 not defined. As originally written the upper bits
12811 have a defined value due to the AND operation.
12812 However, if we commute the AND inside the SUBREG then
12813 they no longer have defined values and the meaning of
12814 the code has been changed.
12815 Also C1 should not change value in the smaller mode,
12816 see PR67028 (a positive C1 can become negative in the
12817 smaller mode, so that the AND does no longer mask the
12819 && ((WORD_REGISTER_OPERATIONS
12820 && mode_width
> GET_MODE_PRECISION (tmode
)
12821 && mode_width
<= BITS_PER_WORD
12822 && trunc_int_for_mode (c1
, tmode
) == (HOST_WIDE_INT
) c1
)
12823 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12824 && subreg_lowpart_p (XEXP (op0
, 0))))
12825 && mode_width
<= HOST_BITS_PER_WIDE_INT
12826 && HWI_COMPUTABLE_MODE_P (tmode
)
12827 && (c1
& ~mask
) == 0
12828 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12830 && c1
!= GET_MODE_MASK (tmode
))
12832 op0
= simplify_gen_binary (AND
, tmode
,
12833 SUBREG_REG (XEXP (op0
, 0)),
12834 gen_int_mode (c1
, tmode
));
12835 op0
= gen_lowpart (mode
, op0
);
12840 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12841 if (const_op
== 0 && equality_comparison_p
12842 && XEXP (op0
, 1) == const1_rtx
12843 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12845 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12846 XEXP (XEXP (op0
, 0), 0), 1);
12847 code
= (code
== NE
? EQ
: NE
);
12851 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12852 (eq (and (lshiftrt X) 1) 0).
12853 Also handle the case where (not X) is expressed using xor. */
12854 if (const_op
== 0 && equality_comparison_p
12855 && XEXP (op0
, 1) == const1_rtx
12856 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12858 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12859 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12861 if (GET_CODE (shift_op
) == NOT
12862 || (GET_CODE (shift_op
) == XOR
12863 && CONST_INT_P (XEXP (shift_op
, 1))
12864 && CONST_INT_P (shift_count
)
12865 && HWI_COMPUTABLE_MODE_P (mode
)
12866 && (UINTVAL (XEXP (shift_op
, 1))
12867 == HOST_WIDE_INT_1U
12868 << INTVAL (shift_count
))))
12871 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12872 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12873 code
= (code
== NE
? EQ
: NE
);
12880 /* If we have (compare (ashift FOO N) (const_int C)) and
12881 the high order N bits of FOO (N+1 if an inequality comparison)
12882 are known to be zero, we can do this by comparing FOO with C
12883 shifted right N bits so long as the low-order N bits of C are
12885 if (CONST_INT_P (XEXP (op0
, 1))
12886 && INTVAL (XEXP (op0
, 1)) >= 0
12887 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12888 < HOST_BITS_PER_WIDE_INT
)
12889 && (((unsigned HOST_WIDE_INT
) const_op
12890 & ((HOST_WIDE_INT_1U
<< INTVAL (XEXP (op0
, 1)))
12892 && mode_width
<= HOST_BITS_PER_WIDE_INT
12893 && (nonzero_bits (XEXP (op0
, 0), mode
)
12894 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12895 + ! equality_comparison_p
))) == 0)
12897 /* We must perform a logical shift, not an arithmetic one,
12898 as we want the top N bits of C to be zero. */
12899 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12901 temp
>>= INTVAL (XEXP (op0
, 1));
12902 op1
= gen_int_mode (temp
, mode
);
12903 op0
= XEXP (op0
, 0);
12907 /* If we are doing a sign bit comparison, it means we are testing
12908 a particular bit. Convert it to the appropriate AND. */
12909 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12910 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12912 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12915 - INTVAL (XEXP (op0
, 1)))));
12916 code
= (code
== LT
? NE
: EQ
);
12920 /* If this an equality comparison with zero and we are shifting
12921 the low bit to the sign bit, we can convert this to an AND of the
12923 if (const_op
== 0 && equality_comparison_p
12924 && CONST_INT_P (XEXP (op0
, 1))
12925 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12927 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12933 /* If this is an equality comparison with zero, we can do this
12934 as a logical shift, which might be much simpler. */
12935 if (equality_comparison_p
&& const_op
== 0
12936 && CONST_INT_P (XEXP (op0
, 1)))
12938 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12940 INTVAL (XEXP (op0
, 1)));
12944 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12945 do the comparison in a narrower mode. */
12946 if (! unsigned_comparison_p
12947 && CONST_INT_P (XEXP (op0
, 1))
12948 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12949 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12950 && (int_mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)), 1)
12952 && (((unsigned HOST_WIDE_INT
) const_op
12953 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12954 <= GET_MODE_MASK (tmode
)))
12956 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12960 /* Likewise if OP0 is a PLUS of a sign extension with a
12961 constant, which is usually represented with the PLUS
12962 between the shifts. */
12963 if (! unsigned_comparison_p
12964 && CONST_INT_P (XEXP (op0
, 1))
12965 && GET_CODE (XEXP (op0
, 0)) == PLUS
12966 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12967 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12968 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12969 && (int_mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)), 1)
12971 && (((unsigned HOST_WIDE_INT
) const_op
12972 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12973 <= GET_MODE_MASK (tmode
)))
12975 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12976 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12977 rtx new_const
= simplify_gen_binary (ASHIFTRT
, mode
,
12978 add_const
, XEXP (op0
, 1));
12980 op0
= simplify_gen_binary (PLUS
, tmode
,
12981 gen_lowpart (tmode
, inner
),
12988 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12989 the low order N bits of FOO are known to be zero, we can do this
12990 by comparing FOO with C shifted left N bits so long as no
12991 overflow occurs. Even if the low order N bits of FOO aren't known
12992 to be zero, if the comparison is >= or < we can use the same
12993 optimization and for > or <= by setting all the low
12994 order N bits in the comparison constant. */
12995 if (CONST_INT_P (XEXP (op0
, 1))
12996 && INTVAL (XEXP (op0
, 1)) > 0
12997 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12998 && mode_width
<= HOST_BITS_PER_WIDE_INT
12999 && (((unsigned HOST_WIDE_INT
) const_op
13000 + (GET_CODE (op0
) != LSHIFTRT
13001 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
13004 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
13006 unsigned HOST_WIDE_INT low_bits
13007 = (nonzero_bits (XEXP (op0
, 0), mode
)
13008 & ((HOST_WIDE_INT_1U
13009 << INTVAL (XEXP (op0
, 1))) - 1));
13010 if (low_bits
== 0 || !equality_comparison_p
)
13012 /* If the shift was logical, then we must make the condition
13014 if (GET_CODE (op0
) == LSHIFTRT
)
13015 code
= unsigned_condition (code
);
13017 const_op
= (unsigned HOST_WIDE_INT
) const_op
13018 << INTVAL (XEXP (op0
, 1));
13020 && (code
== GT
|| code
== GTU
13021 || code
== LE
|| code
== LEU
))
13023 |= ((HOST_WIDE_INT_1
<< INTVAL (XEXP (op0
, 1))) - 1);
13024 op1
= GEN_INT (const_op
);
13025 op0
= XEXP (op0
, 0);
13030 /* If we are using this shift to extract just the sign bit, we
13031 can replace this with an LT or GE comparison. */
13033 && (equality_comparison_p
|| sign_bit_comparison_p
)
13034 && CONST_INT_P (XEXP (op0
, 1))
13035 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
13037 op0
= XEXP (op0
, 0);
13038 code
= (code
== NE
|| code
== GT
? LT
: GE
);
13050 /* Now make any compound operations involved in this comparison. Then,
13051 check for an outmost SUBREG on OP0 that is not doing anything or is
13052 paradoxical. The latter transformation must only be performed when
13053 it is known that the "extra" bits will be the same in op0 and op1 or
13054 that they don't matter. There are three cases to consider:
13056 1. SUBREG_REG (op0) is a register. In this case the bits are don't
13057 care bits and we can assume they have any convenient value. So
13058 making the transformation is safe.
13060 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
13061 In this case the upper bits of op0 are undefined. We should not make
13062 the simplification in that case as we do not know the contents of
13065 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
13066 In that case we know those bits are zeros or ones. We must also be
13067 sure that they are the same as the upper bits of op1.
13069 We can never remove a SUBREG for a non-equality comparison because
13070 the sign bit is in a different place in the underlying object. */
13072 rtx_code op0_mco_code
= SET
;
13073 if (op1
== const0_rtx
)
13074 op0_mco_code
= code
== NE
|| code
== EQ
? EQ
: COMPARE
;
13076 op0
= make_compound_operation (op0
, op0_mco_code
);
13077 op1
= make_compound_operation (op1
, SET
);
13079 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
13080 && is_int_mode (GET_MODE (op0
), &mode
)
13081 && is_int_mode (GET_MODE (SUBREG_REG (op0
)), &inner_mode
)
13082 && (code
== NE
|| code
== EQ
))
13084 if (paradoxical_subreg_p (op0
))
13086 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
13088 if (REG_P (SUBREG_REG (op0
)))
13090 op0
= SUBREG_REG (op0
);
13091 op1
= gen_lowpart (inner_mode
, op1
);
13094 else if (GET_MODE_PRECISION (inner_mode
) <= HOST_BITS_PER_WIDE_INT
13095 && (nonzero_bits (SUBREG_REG (op0
), inner_mode
)
13096 & ~GET_MODE_MASK (mode
)) == 0)
13098 tem
= gen_lowpart (inner_mode
, op1
);
13100 if ((nonzero_bits (tem
, inner_mode
) & ~GET_MODE_MASK (mode
)) == 0)
13101 op0
= SUBREG_REG (op0
), op1
= tem
;
13105 /* We now do the opposite procedure: Some machines don't have compare
13106 insns in all modes. If OP0's mode is an integer mode smaller than a
13107 word and we can't do a compare in that mode, see if there is a larger
13108 mode for which we can do the compare. There are a number of cases in
13109 which we can use the wider mode. */
13111 if (is_int_mode (GET_MODE (op0
), &mode
)
13112 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
13113 && ! have_insn_for (COMPARE
, mode
))
13114 FOR_EACH_WIDER_MODE (tmode_iter
, mode
)
13116 tmode
= tmode_iter
.require ();
13117 if (!HWI_COMPUTABLE_MODE_P (tmode
))
13119 if (have_insn_for (COMPARE
, tmode
))
13123 /* If this is a test for negative, we can make an explicit
13124 test of the sign bit. Test this first so we can use
13125 a paradoxical subreg to extend OP0. */
13127 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
13128 && HWI_COMPUTABLE_MODE_P (mode
))
13130 unsigned HOST_WIDE_INT sign
13131 = HOST_WIDE_INT_1U
<< (GET_MODE_BITSIZE (mode
) - 1);
13132 op0
= simplify_gen_binary (AND
, tmode
,
13133 gen_lowpart (tmode
, op0
),
13134 gen_int_mode (sign
, tmode
));
13135 code
= (code
== LT
) ? NE
: EQ
;
13139 /* If the only nonzero bits in OP0 and OP1 are those in the
13140 narrower mode and this is an equality or unsigned comparison,
13141 we can use the wider mode. Similarly for sign-extended
13142 values, in which case it is true for all comparisons. */
13143 zero_extended
= ((code
== EQ
|| code
== NE
13144 || code
== GEU
|| code
== GTU
13145 || code
== LEU
|| code
== LTU
)
13146 && (nonzero_bits (op0
, tmode
)
13147 & ~GET_MODE_MASK (mode
)) == 0
13148 && ((CONST_INT_P (op1
)
13149 || (nonzero_bits (op1
, tmode
)
13150 & ~GET_MODE_MASK (mode
)) == 0)));
13153 || ((num_sign_bit_copies (op0
, tmode
)
13154 > (unsigned int) (GET_MODE_PRECISION (tmode
)
13155 - GET_MODE_PRECISION (mode
)))
13156 && (num_sign_bit_copies (op1
, tmode
)
13157 > (unsigned int) (GET_MODE_PRECISION (tmode
)
13158 - GET_MODE_PRECISION (mode
)))))
13160 /* If OP0 is an AND and we don't have an AND in MODE either,
13161 make a new AND in the proper mode. */
13162 if (GET_CODE (op0
) == AND
13163 && !have_insn_for (AND
, mode
))
13164 op0
= simplify_gen_binary (AND
, tmode
,
13165 gen_lowpart (tmode
,
13167 gen_lowpart (tmode
,
13173 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
,
13175 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
,
13180 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
,
13182 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
,
13191 /* We may have changed the comparison operands. Re-canonicalize. */
13192 if (swap_commutative_operands_p (op0
, op1
))
13194 std::swap (op0
, op1
);
13195 code
= swap_condition (code
);
13198 /* If this machine only supports a subset of valid comparisons, see if we
13199 can convert an unsupported one into a supported one. */
13200 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
13208 /* Utility function for record_value_for_reg. Count number of
13213 enum rtx_code code
= GET_CODE (x
);
13217 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
13218 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
13220 rtx x0
= XEXP (x
, 0);
13221 rtx x1
= XEXP (x
, 1);
13224 return 1 + 2 * count_rtxs (x0
);
13226 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
13227 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
13228 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13229 return 2 + 2 * count_rtxs (x0
)
13230 + count_rtxs (x
== XEXP (x1
, 0)
13231 ? XEXP (x1
, 1) : XEXP (x1
, 0));
13233 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
13234 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
13235 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13236 return 2 + 2 * count_rtxs (x1
)
13237 + count_rtxs (x
== XEXP (x0
, 0)
13238 ? XEXP (x0
, 1) : XEXP (x0
, 0));
13241 fmt
= GET_RTX_FORMAT (code
);
13242 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13244 ret
+= count_rtxs (XEXP (x
, i
));
13245 else if (fmt
[i
] == 'E')
13246 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13247 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
13252 /* Utility function for following routine. Called when X is part of a value
13253 being stored into last_set_value. Sets last_set_table_tick
13254 for each register mentioned. Similar to mention_regs in cse.cc */
13257 update_table_tick (rtx x
)
13259 enum rtx_code code
= GET_CODE (x
);
13260 const char *fmt
= GET_RTX_FORMAT (code
);
13265 unsigned int regno
= REGNO (x
);
13266 unsigned int endregno
= END_REGNO (x
);
13269 for (r
= regno
; r
< endregno
; r
++)
13271 reg_stat_type
*rsp
= ®_stat
[r
];
13272 rsp
->last_set_table_tick
= label_tick
;
13278 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13281 /* Check for identical subexpressions. If x contains
13282 identical subexpression we only have to traverse one of
13284 if (i
== 0 && ARITHMETIC_P (x
))
13286 /* Note that at this point x1 has already been
13288 rtx x0
= XEXP (x
, 0);
13289 rtx x1
= XEXP (x
, 1);
13291 /* If x0 and x1 are identical then there is no need to
13296 /* If x0 is identical to a subexpression of x1 then while
13297 processing x1, x0 has already been processed. Thus we
13298 are done with x. */
13299 if (ARITHMETIC_P (x1
)
13300 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13303 /* If x1 is identical to a subexpression of x0 then we
13304 still have to process the rest of x0. */
13305 if (ARITHMETIC_P (x0
)
13306 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13308 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
13313 update_table_tick (XEXP (x
, i
));
13315 else if (fmt
[i
] == 'E')
13316 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13317 update_table_tick (XVECEXP (x
, i
, j
));
13320 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13321 are saying that the register is clobbered and we no longer know its
13322 value. If INSN is zero, don't update reg_stat[].last_set; this is
13323 only permitted with VALUE also zero and is used to invalidate the
13327 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
13329 unsigned int regno
= REGNO (reg
);
13330 unsigned int endregno
= END_REGNO (reg
);
13332 reg_stat_type
*rsp
;
13334 /* If VALUE contains REG and we have a previous value for REG, substitute
13335 the previous value. */
13336 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
13340 /* Set things up so get_last_value is allowed to see anything set up to
13342 subst_low_luid
= DF_INSN_LUID (insn
);
13343 tem
= get_last_value (reg
);
13345 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13346 it isn't going to be useful and will take a lot of time to process,
13347 so just use the CLOBBER. */
13351 if (ARITHMETIC_P (tem
)
13352 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
13353 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
13354 tem
= XEXP (tem
, 0);
13355 else if (count_occurrences (value
, reg
, 1) >= 2)
13357 /* If there are two or more occurrences of REG in VALUE,
13358 prevent the value from growing too much. */
13359 if (count_rtxs (tem
) > param_max_last_value_rtl
)
13360 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
13363 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
13367 /* For each register modified, show we don't know its value, that
13368 we don't know about its bitwise content, that its value has been
13369 updated, and that we don't know the location of the death of the
13371 for (i
= regno
; i
< endregno
; i
++)
13373 rsp
= ®_stat
[i
];
13376 rsp
->last_set
= insn
;
13378 rsp
->last_set_value
= 0;
13379 rsp
->last_set_mode
= VOIDmode
;
13380 rsp
->last_set_nonzero_bits
= 0;
13381 rsp
->last_set_sign_bit_copies
= 0;
13382 rsp
->last_death
= 0;
13383 rsp
->truncated_to_mode
= VOIDmode
;
13386 /* Mark registers that are being referenced in this value. */
13388 update_table_tick (value
);
13390 /* Now update the status of each register being set.
13391 If someone is using this register in this block, set this register
13392 to invalid since we will get confused between the two lives in this
13393 basic block. This makes using this register always invalid. In cse, we
13394 scan the table to invalidate all entries using this register, but this
13395 is too much work for us. */
13397 for (i
= regno
; i
< endregno
; i
++)
13399 rsp
= ®_stat
[i
];
13400 rsp
->last_set_label
= label_tick
;
13402 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
13403 rsp
->last_set_invalid
= true;
13405 rsp
->last_set_invalid
= false;
13408 /* The value being assigned might refer to X (like in "x++;"). In that
13409 case, we must replace it with (clobber (const_int 0)) to prevent
13411 rsp
= ®_stat
[regno
];
13412 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, false))
13414 value
= copy_rtx (value
);
13415 if (!get_last_value_validate (&value
, insn
, label_tick
, true))
13419 /* For the main register being modified, update the value, the mode, the
13420 nonzero bits, and the number of sign bit copies. */
13422 rsp
->last_set_value
= value
;
13426 machine_mode mode
= GET_MODE (reg
);
13427 subst_low_luid
= DF_INSN_LUID (insn
);
13428 rsp
->last_set_mode
= mode
;
13429 if (GET_MODE_CLASS (mode
) == MODE_INT
13430 && HWI_COMPUTABLE_MODE_P (mode
))
13431 mode
= nonzero_bits_mode
;
13432 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
13433 rsp
->last_set_sign_bit_copies
13434 = num_sign_bit_copies (value
, GET_MODE (reg
));
13438 /* Called via note_stores from record_dead_and_set_regs to handle one
13439 SET or CLOBBER in an insn. DATA is the instruction in which the
13440 set is occurring. */
13443 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
13445 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
13447 if (GET_CODE (dest
) == SUBREG
)
13448 dest
= SUBREG_REG (dest
);
13450 if (!record_dead_insn
)
13453 record_value_for_reg (dest
, NULL
, NULL_RTX
);
13459 /* If we are setting the whole register, we know its value. */
13460 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
13461 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
13462 /* We can handle a SUBREG if it's the low part, but we must be
13463 careful with paradoxical SUBREGs on RISC architectures because
13464 we cannot strip e.g. an extension around a load and record the
13465 naked load since the RTL middle-end considers that the upper bits
13466 are defined according to LOAD_EXTEND_OP. */
13467 else if (GET_CODE (setter
) == SET
13468 && GET_CODE (SET_DEST (setter
)) == SUBREG
13469 && SUBREG_REG (SET_DEST (setter
)) == dest
13470 && known_le (GET_MODE_PRECISION (GET_MODE (dest
)),
13472 && subreg_lowpart_p (SET_DEST (setter
)))
13474 if (WORD_REGISTER_OPERATIONS
13475 && word_register_operation_p (SET_SRC (setter
))
13476 && paradoxical_subreg_p (SET_DEST (setter
)))
13477 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
13478 else if (!partial_subreg_p (SET_DEST (setter
)))
13479 record_value_for_reg (dest
, record_dead_insn
,
13480 gen_lowpart (GET_MODE (dest
),
13481 SET_SRC (setter
)));
13484 record_value_for_reg (dest
, record_dead_insn
,
13485 gen_lowpart (GET_MODE (dest
),
13486 SET_SRC (setter
)));
13488 unsigned HOST_WIDE_INT mask
;
13489 reg_stat_type
*rsp
= ®_stat
[REGNO (dest
)];
13490 mask
= GET_MODE_MASK (GET_MODE (SET_DEST (setter
)));
13491 rsp
->last_set_nonzero_bits
|= ~mask
;
13492 rsp
->last_set_sign_bit_copies
= 1;
13495 /* Otherwise show that we don't know the value. */
13497 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
13499 else if (MEM_P (dest
)
13500 /* Ignore pushes, they clobber nothing. */
13501 && ! push_operand (dest
, GET_MODE (dest
)))
13502 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
13505 /* Update the records of when each REG was most recently set or killed
13506 for the things done by INSN. This is the last thing done in processing
13507 INSN in the combiner loop.
13509 We update reg_stat[], in particular fields last_set, last_set_value,
13510 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13511 last_death, and also the similar information mem_last_set (which insn
13512 most recently modified memory) and last_call_luid (which insn was the
13513 most recent subroutine call). */
13516 record_dead_and_set_regs (rtx_insn
*insn
)
13521 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
13523 if (REG_NOTE_KIND (link
) == REG_DEAD
13524 && REG_P (XEXP (link
, 0)))
13526 unsigned int regno
= REGNO (XEXP (link
, 0));
13527 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
13529 for (i
= regno
; i
< endregno
; i
++)
13531 reg_stat_type
*rsp
;
13533 rsp
= ®_stat
[i
];
13534 rsp
->last_death
= insn
;
13537 else if (REG_NOTE_KIND (link
) == REG_INC
)
13538 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
13543 HARD_REG_SET callee_clobbers
13544 = insn_callee_abi (insn
).full_and_partial_reg_clobbers ();
13545 hard_reg_set_iterator hrsi
;
13546 EXECUTE_IF_SET_IN_HARD_REG_SET (callee_clobbers
, 0, i
, hrsi
)
13548 reg_stat_type
*rsp
;
13550 /* ??? We could try to preserve some information from the last
13551 set of register I if the call doesn't actually clobber
13552 (reg:last_set_mode I), which might be true for ABIs with
13553 partial clobbers. However, it would be difficult to
13554 update last_set_nonzero_bits and last_sign_bit_copies
13555 to account for the part of I that actually was clobbered.
13556 It wouldn't help much anyway, since we rarely see this
13557 situation before RA. */
13558 rsp
= ®_stat
[i
];
13559 rsp
->last_set_invalid
= true;
13560 rsp
->last_set
= insn
;
13561 rsp
->last_set_value
= 0;
13562 rsp
->last_set_mode
= VOIDmode
;
13563 rsp
->last_set_nonzero_bits
= 0;
13564 rsp
->last_set_sign_bit_copies
= 0;
13565 rsp
->last_death
= 0;
13566 rsp
->truncated_to_mode
= VOIDmode
;
13569 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
13571 /* We can't combine into a call pattern. Remember, though, that
13572 the return value register is set at this LUID. We could
13573 still replace a register with the return value from the
13574 wrong subroutine call! */
13575 note_stores (insn
, record_dead_and_set_regs_1
, NULL_RTX
);
13578 note_stores (insn
, record_dead_and_set_regs_1
, insn
);
13581 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13582 register present in the SUBREG, so for each such SUBREG go back and
13583 adjust nonzero and sign bit information of the registers that are
13584 known to have some zero/sign bits set.
13586 This is needed because when combine blows the SUBREGs away, the
13587 information on zero/sign bits is lost and further combines can be
13588 missed because of that. */
13591 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
13593 struct insn_link
*links
;
13595 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
13596 machine_mode mode
= GET_MODE (subreg
);
13598 if (!HWI_COMPUTABLE_MODE_P (mode
))
13601 for (links
= LOG_LINKS (insn
); links
;)
13603 reg_stat_type
*rsp
;
13605 insn
= links
->insn
;
13606 set
= single_set (insn
);
13608 if (! set
|| !REG_P (SET_DEST (set
))
13609 || REGNO (SET_DEST (set
)) != regno
13610 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
13612 links
= links
->next
;
13616 rsp
= ®_stat
[regno
];
13617 if (rsp
->last_set
== insn
)
13619 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
13620 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
13623 if (REG_P (SET_SRC (set
)))
13625 regno
= REGNO (SET_SRC (set
));
13626 links
= LOG_LINKS (insn
);
13633 /* Check if X, a register, is known to contain a value already
13634 truncated to MODE. In this case we can use a subreg to refer to
13635 the truncated value even though in the generic case we would need
13636 an explicit truncation. */
13639 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
13641 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
13642 machine_mode truncated
= rsp
->truncated_to_mode
;
13645 || rsp
->truncation_label
< label_tick_ebb_start
)
13647 if (!partial_subreg_p (mode
, truncated
))
13649 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
13654 /* If X is a hard reg or a subreg record the mode that the register is
13655 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13656 able to turn a truncate into a subreg using this information. Return true
13657 if traversing X is complete. */
13660 record_truncated_value (rtx x
)
13662 machine_mode truncated_mode
;
13663 reg_stat_type
*rsp
;
13665 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
13667 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
13668 truncated_mode
= GET_MODE (x
);
13670 if (!partial_subreg_p (truncated_mode
, original_mode
))
13673 truncated_mode
= GET_MODE (x
);
13674 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
13677 x
= SUBREG_REG (x
);
13679 /* ??? For hard-regs we now record everything. We might be able to
13680 optimize this using last_set_mode. */
13681 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
13682 truncated_mode
= GET_MODE (x
);
13686 rsp
= ®_stat
[REGNO (x
)];
13687 if (rsp
->truncated_to_mode
== 0
13688 || rsp
->truncation_label
< label_tick_ebb_start
13689 || partial_subreg_p (truncated_mode
, rsp
->truncated_to_mode
))
13691 rsp
->truncated_to_mode
= truncated_mode
;
13692 rsp
->truncation_label
= label_tick
;
13698 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13699 the modes they are used in. This can help truning TRUNCATEs into
13703 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
13705 subrtx_var_iterator::array_type array
;
13706 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
13707 if (record_truncated_value (*iter
))
13708 iter
.skip_subrtxes ();
13711 /* Scan X for promoted SUBREGs. For each one found,
13712 note what it implies to the registers used in it. */
13715 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
13717 if (GET_CODE (x
) == SUBREG
13718 && SUBREG_PROMOTED_VAR_P (x
)
13719 && REG_P (SUBREG_REG (x
)))
13720 record_promoted_value (insn
, x
);
13723 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
13726 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
13730 check_promoted_subreg (insn
, XEXP (x
, i
));
13734 if (XVEC (x
, i
) != 0)
13735 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13736 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
13742 /* Verify that all the registers and memory references mentioned in *LOC are
13743 still valid. *LOC was part of a value set in INSN when label_tick was
13744 equal to TICK. Return false if some are not. If REPLACE is true, replace
13745 the invalid references with (clobber (const_int 0)) and return true. This
13746 replacement is useful because we often can get useful information about
13747 the form of a value (e.g., if it was produced by a shift that always
13748 produces -1 or 0) even though we don't know exactly what registers it
13749 was produced from. */
13752 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, bool replace
)
13755 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13756 int len
= GET_RTX_LENGTH (GET_CODE (x
));
13761 unsigned int regno
= REGNO (x
);
13762 unsigned int endregno
= END_REGNO (x
);
13765 for (j
= regno
; j
< endregno
; j
++)
13767 reg_stat_type
*rsp
= ®_stat
[j
];
13768 if (rsp
->last_set_invalid
13769 /* If this is a pseudo-register that was only set once and not
13770 live at the beginning of the function, it is always valid. */
13771 || (! (regno
>= FIRST_PSEUDO_REGISTER
13772 && regno
< reg_n_sets_max
13773 && REG_N_SETS (regno
) == 1
13774 && (!REGNO_REG_SET_P
13775 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13777 && rsp
->last_set_label
> tick
))
13780 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13787 /* If this is a memory reference, make sure that there were no stores after
13788 it that might have clobbered the value. We don't have alias info, so we
13789 assume any store invalidates it. Moreover, we only have local UIDs, so
13790 we also assume that there were stores in the intervening basic blocks. */
13791 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13792 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13795 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13799 for (i
= 0; i
< len
; i
++)
13803 /* Check for identical subexpressions. If x contains
13804 identical subexpression we only have to traverse one of
13806 if (i
== 1 && ARITHMETIC_P (x
))
13808 /* Note that at this point x0 has already been checked
13809 and found valid. */
13810 rtx x0
= XEXP (x
, 0);
13811 rtx x1
= XEXP (x
, 1);
13813 /* If x0 and x1 are identical then x is also valid. */
13817 /* If x1 is identical to a subexpression of x0 then
13818 while checking x0, x1 has already been checked. Thus
13819 it is valid and so as x. */
13820 if (ARITHMETIC_P (x0
)
13821 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13824 /* If x0 is identical to a subexpression of x1 then x is
13825 valid iff the rest of x1 is valid. */
13826 if (ARITHMETIC_P (x1
)
13827 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13829 get_last_value_validate (&XEXP (x1
,
13830 x0
== XEXP (x1
, 0) ? 1 : 0),
13831 insn
, tick
, replace
);
13834 if (!get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
))
13837 else if (fmt
[i
] == 'E')
13838 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13839 if (!get_last_value_validate (&XVECEXP (x
, i
, j
),
13840 insn
, tick
, replace
))
13844 /* If we haven't found a reason for it to be invalid, it is valid. */
13848 /* Get the last value assigned to X, if known. Some registers
13849 in the value may be replaced with (clobber (const_int 0)) if their value
13850 is known longer known reliably. */
13853 get_last_value (const_rtx x
)
13855 unsigned int regno
;
13857 reg_stat_type
*rsp
;
13859 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13860 then convert it to the desired mode. If this is a paradoxical SUBREG,
13861 we cannot predict what values the "extra" bits might have. */
13862 if (GET_CODE (x
) == SUBREG
13863 && subreg_lowpart_p (x
)
13864 && !paradoxical_subreg_p (x
)
13865 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13866 return gen_lowpart (GET_MODE (x
), value
);
13872 rsp
= ®_stat
[regno
];
13873 value
= rsp
->last_set_value
;
13875 /* If we don't have a value, or if it isn't for this basic block and
13876 it's either a hard register, set more than once, or it's a live
13877 at the beginning of the function, return 0.
13879 Because if it's not live at the beginning of the function then the reg
13880 is always set before being used (is never used without being set).
13881 And, if it's set only once, and it's always set before use, then all
13882 uses must have the same last value, even if it's not from this basic
13886 || (rsp
->last_set_label
< label_tick_ebb_start
13887 && (regno
< FIRST_PSEUDO_REGISTER
13888 || regno
>= reg_n_sets_max
13889 || REG_N_SETS (regno
) != 1
13891 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13894 /* If the value was set in a later insn than the ones we are processing,
13895 we can't use it even if the register was only set once. */
13896 if (rsp
->last_set_label
== label_tick
13897 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13900 /* If fewer bits were set than what we are asked for now, we cannot use
13902 if (maybe_lt (GET_MODE_PRECISION (rsp
->last_set_mode
),
13903 GET_MODE_PRECISION (GET_MODE (x
))))
13906 /* If the value has all its registers valid, return it. */
13907 if (get_last_value_validate (&value
, rsp
->last_set
,
13908 rsp
->last_set_label
, false))
13911 /* Otherwise, make a copy and replace any invalid register with
13912 (clobber (const_int 0)). If that fails for some reason, return 0. */
13914 value
= copy_rtx (value
);
13915 if (get_last_value_validate (&value
, rsp
->last_set
,
13916 rsp
->last_set_label
, true))
13922 /* Define three variables used for communication between the following
13925 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13926 static int reg_dead_flag
;
13929 /* Function called via note_stores from reg_dead_at_p.
13931 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13932 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13935 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13937 unsigned int regno
, endregno
;
13942 regno
= REGNO (dest
);
13943 endregno
= END_REGNO (dest
);
13944 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13945 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13948 /* Return true if REG is known to be dead at INSN.
13950 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13951 referencing REG, it is dead. If we hit a SET referencing REG, it is
13952 live. Otherwise, see if it is live or dead at the start of the basic
13953 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13954 must be assumed to be always live. */
13957 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13962 /* Set variables for reg_dead_at_p_1. */
13963 reg_dead_regno
= REGNO (reg
);
13964 reg_dead_endregno
= END_REGNO (reg
);
13965 reg_dead_reg
= reg
;
13969 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13970 we allow the machine description to decide whether use-and-clobber
13971 patterns are OK. */
13972 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13974 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13975 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13979 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13980 beginning of basic block. */
13981 block
= BLOCK_FOR_INSN (insn
);
13986 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13989 note_stores (insn
, reg_dead_at_p_1
, NULL
);
13991 return reg_dead_flag
== 1 ? 1 : 0;
13993 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13997 if (insn
== BB_HEAD (block
))
14000 insn
= PREV_INSN (insn
);
14003 /* Look at live-in sets for the basic block that we were in. */
14004 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
14005 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
14011 /* Note hard registers in X that are used. */
14014 mark_used_regs_combine (rtx x
)
14016 RTX_CODE code
= GET_CODE (x
);
14017 unsigned int regno
;
14028 case ADDR_DIFF_VEC
:
14033 /* If we are clobbering a MEM, mark any hard registers inside the
14034 address as used. */
14035 if (MEM_P (XEXP (x
, 0)))
14036 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
14041 /* A hard reg in a wide mode may really be multiple registers.
14042 If so, mark all of them just like the first. */
14043 if (regno
< FIRST_PSEUDO_REGISTER
)
14045 /* None of this applies to the stack, frame or arg pointers. */
14046 if (regno
== STACK_POINTER_REGNUM
14047 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
14048 && regno
== HARD_FRAME_POINTER_REGNUM
)
14049 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
14050 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
14051 || regno
== FRAME_POINTER_REGNUM
)
14054 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
14060 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
14062 rtx testreg
= SET_DEST (x
);
14064 while (GET_CODE (testreg
) == SUBREG
14065 || GET_CODE (testreg
) == ZERO_EXTRACT
14066 || GET_CODE (testreg
) == STRICT_LOW_PART
)
14067 testreg
= XEXP (testreg
, 0);
14069 if (MEM_P (testreg
))
14070 mark_used_regs_combine (XEXP (testreg
, 0));
14072 mark_used_regs_combine (SET_SRC (x
));
14080 /* Recursively scan the operands of this expression. */
14083 const char *fmt
= GET_RTX_FORMAT (code
);
14085 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
14088 mark_used_regs_combine (XEXP (x
, i
));
14089 else if (fmt
[i
] == 'E')
14093 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
14094 mark_used_regs_combine (XVECEXP (x
, i
, j
));
14100 /* Remove register number REGNO from the dead registers list of INSN.
14102 Return the note used to record the death, if there was one. */
14105 remove_death (unsigned int regno
, rtx_insn
*insn
)
14107 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
14110 remove_note (insn
, note
);
14115 /* For each register (hardware or pseudo) used within expression X, if its
14116 death is in an instruction with luid between FROM_LUID (inclusive) and
14117 TO_INSN (exclusive), put a REG_DEAD note for that register in the
14118 list headed by PNOTES.
14120 That said, don't move registers killed by maybe_kill_insn.
14122 This is done when X is being merged by combination into TO_INSN. These
14123 notes will then be distributed as needed. */
14126 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
14131 enum rtx_code code
= GET_CODE (x
);
14135 unsigned int regno
= REGNO (x
);
14136 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
14138 /* If we do not know where the register died, it may still die between
14139 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
14140 if (!where_dead
|| DF_INSN_LUID (where_dead
) >= DF_INSN_LUID (to_insn
))
14142 rtx_insn
*insn
= prev_real_nondebug_insn (to_insn
);
14144 && BLOCK_FOR_INSN (insn
) == BLOCK_FOR_INSN (to_insn
)
14145 && DF_INSN_LUID (insn
) >= from_luid
)
14147 if (dead_or_set_regno_p (insn
, regno
))
14149 if (find_regno_note (insn
, REG_DEAD
, regno
))
14154 insn
= prev_real_nondebug_insn (insn
);
14158 /* Don't move the register if it gets killed in between from and to. */
14159 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
14160 && ! reg_referenced_p (x
, maybe_kill_insn
))
14164 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
14165 && DF_INSN_LUID (where_dead
) >= from_luid
14166 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
14168 rtx note
= remove_death (regno
, where_dead
);
14170 /* It is possible for the call above to return 0. This can occur
14171 when last_death points to I2 or I1 that we combined with.
14172 In that case make a new note.
14174 We must also check for the case where X is a hard register
14175 and NOTE is a death note for a range of hard registers
14176 including X. In that case, we must put REG_DEAD notes for
14177 the remaining registers in place of NOTE. */
14179 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
14180 && partial_subreg_p (GET_MODE (x
), GET_MODE (XEXP (note
, 0))))
14182 unsigned int deadregno
= REGNO (XEXP (note
, 0));
14183 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
14184 unsigned int ourend
= END_REGNO (x
);
14187 for (i
= deadregno
; i
< deadend
; i
++)
14188 if (i
< regno
|| i
>= ourend
)
14189 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
14192 /* If we didn't find any note, or if we found a REG_DEAD note that
14193 covers only part of the given reg, and we have a multi-reg hard
14194 register, then to be safe we must check for REG_DEAD notes
14195 for each register other than the first. They could have
14196 their own REG_DEAD notes lying around. */
14197 else if ((note
== 0
14199 && partial_subreg_p (GET_MODE (XEXP (note
, 0)),
14201 && regno
< FIRST_PSEUDO_REGISTER
14202 && REG_NREGS (x
) > 1)
14204 unsigned int ourend
= END_REGNO (x
);
14205 unsigned int i
, offset
;
14209 offset
= hard_regno_nregs (regno
, GET_MODE (XEXP (note
, 0)));
14213 for (i
= regno
+ offset
; i
< ourend
; i
++)
14214 move_deaths (regno_reg_rtx
[i
],
14215 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
14218 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
14220 XEXP (note
, 1) = *pnotes
;
14224 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
14230 else if (GET_CODE (x
) == SET
)
14232 rtx dest
= SET_DEST (x
);
14234 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14236 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14237 that accesses one word of a multi-word item, some
14238 piece of everything register in the expression is used by
14239 this insn, so remove any old death. */
14240 /* ??? So why do we test for equality of the sizes? */
14242 if (GET_CODE (dest
) == ZERO_EXTRACT
14243 || GET_CODE (dest
) == STRICT_LOW_PART
14244 || (GET_CODE (dest
) == SUBREG
14245 && !read_modify_subreg_p (dest
)))
14247 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14251 /* If this is some other SUBREG, we know it replaces the entire
14252 value, so use that as the destination. */
14253 if (GET_CODE (dest
) == SUBREG
)
14254 dest
= SUBREG_REG (dest
);
14256 /* If this is a MEM, adjust deaths of anything used in the address.
14257 For a REG (the only other possibility), the entire value is
14258 being replaced so the old value is not used in this insn. */
14261 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
14266 else if (GET_CODE (x
) == CLOBBER
)
14269 len
= GET_RTX_LENGTH (code
);
14270 fmt
= GET_RTX_FORMAT (code
);
14272 for (i
= 0; i
< len
; i
++)
14277 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
14278 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
14281 else if (fmt
[i
] == 'e')
14282 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
14286 /* Return true if X is the target of a bit-field assignment in BODY, the
14287 pattern of an insn. X must be a REG. */
14290 reg_bitfield_target_p (rtx x
, rtx body
)
14294 if (GET_CODE (body
) == SET
)
14296 rtx dest
= SET_DEST (body
);
14298 unsigned int regno
, tregno
, endregno
, endtregno
;
14300 if (GET_CODE (dest
) == ZERO_EXTRACT
)
14301 target
= XEXP (dest
, 0);
14302 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
14303 target
= SUBREG_REG (XEXP (dest
, 0));
14307 if (GET_CODE (target
) == SUBREG
)
14308 target
= SUBREG_REG (target
);
14310 if (!REG_P (target
))
14313 tregno
= REGNO (target
), regno
= REGNO (x
);
14314 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
14315 return target
== x
;
14317 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
14318 endregno
= end_hard_regno (GET_MODE (x
), regno
);
14320 return endregno
> tregno
&& regno
< endtregno
;
14323 else if (GET_CODE (body
) == PARALLEL
)
14324 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
14325 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
14331 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14332 as appropriate. I3 and I2 are the insns resulting from the combination
14333 insns including FROM (I2 may be zero).
14335 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14336 not need REG_DEAD notes because they are being substituted for. This
14337 saves searching in the most common cases.
14339 Each note in the list is either ignored or placed on some insns, depending
14340 on the type of note. */
14343 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
14344 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
14346 rtx note
, next_note
;
14348 rtx_insn
*tem_insn
;
14350 for (note
= notes
; note
; note
= next_note
)
14352 rtx_insn
*place
= 0, *place2
= 0;
14354 next_note
= XEXP (note
, 1);
14355 switch (REG_NOTE_KIND (note
))
14359 /* Doesn't matter much where we put this, as long as it's somewhere.
14360 It is preferable to keep these notes on branches, which is most
14361 likely to be i3. */
14365 case REG_NON_LOCAL_GOTO
:
14370 gcc_assert (i2
&& JUMP_P (i2
));
14375 case REG_EH_REGION
:
14377 /* The landing pad handling needs to be kept in sync with the
14378 prerequisite checking in try_combine. */
14379 int lp_nr
= INTVAL (XEXP (note
, 0));
14380 /* A REG_EH_REGION note transfering control can only ever come
14383 gcc_assert (from_insn
== i3
);
14384 /* We are making sure there is a single effective REG_EH_REGION
14385 note and it's valid to put it on i3. */
14386 if (!insn_could_throw_p (from_insn
)
14387 && !(lp_nr
== INT_MIN
&& can_nonlocal_goto (from_insn
)))
14388 /* Throw away stray notes on insns that can never throw or
14389 make a nonlocal goto. */
14397 gcc_assert (cfun
->can_throw_non_call_exceptions
);
14398 /* If i3 can still trap preserve the note, otherwise we've
14399 combined things such that we can now prove that the
14400 instructions can't trap. Drop the note in this case. */
14401 if (may_trap_p (i3
))
14408 case REG_ARGS_SIZE
:
14409 /* ??? How to distribute between i3-i1. Assume i3 contains the
14410 entire adjustment. Assert i3 contains at least some adjust. */
14411 if (!noop_move_p (i3
))
14413 poly_int64 old_size
, args_size
= get_args_size (note
);
14414 /* fixup_args_size_notes looks at REG_NORETURN note,
14415 so ensure the note is placed there first. */
14419 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
14420 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
14424 XEXP (n
, 1) = REG_NOTES (i3
);
14425 REG_NOTES (i3
) = n
;
14429 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
14430 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14431 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14432 gcc_assert (maybe_ne (old_size
, args_size
)
14434 && !ACCUMULATE_OUTGOING_ARGS
14435 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
14442 case REG_CALL_DECL
:
14443 case REG_UNTYPED_CALL
:
14444 case REG_CALL_NOCF_CHECK
:
14445 /* These notes must remain with the call. It should not be
14446 possible for both I2 and I3 to be a call. */
14451 gcc_assert (i2
&& CALL_P (i2
));
14457 /* Any clobbers for i3 may still exist, and so we must process
14458 REG_UNUSED notes from that insn.
14460 Any clobbers from i2 or i1 can only exist if they were added by
14461 recog_for_combine. In that case, recog_for_combine created the
14462 necessary REG_UNUSED notes. Trying to keep any original
14463 REG_UNUSED notes from these insns can cause incorrect output
14464 if it is for the same register as the original i3 dest.
14465 In that case, we will notice that the register is set in i3,
14466 and then add a REG_UNUSED note for the destination of i3, which
14467 is wrong. However, it is possible to have REG_UNUSED notes from
14468 i2 or i1 for register which were both used and clobbered, so
14469 we keep notes from i2 or i1 if they will turn into REG_DEAD
14472 /* If this register is set or clobbered between FROM_INSN and I3,
14473 we should not create a note for it. */
14474 if (reg_set_between_p (XEXP (note
, 0), from_insn
, i3
))
14477 /* If this register is set or clobbered in I3, put the note there
14478 unless there is one already. */
14479 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
14481 if (from_insn
!= i3
)
14484 if (! (REG_P (XEXP (note
, 0))
14485 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
14486 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
14489 /* Otherwise, if this register is used by I3, then this register
14490 now dies here, so we must put a REG_DEAD note here unless there
14492 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
14493 && ! (REG_P (XEXP (note
, 0))
14494 ? find_regno_note (i3
, REG_DEAD
,
14495 REGNO (XEXP (note
, 0)))
14496 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
14498 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14502 /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14503 but we can't tell which at this point. We must reset any
14504 expectations we had about the value that was previously
14505 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14506 and, if appropriate, restore its previous value, but we
14507 don't have enough information for that at this point. */
14510 record_value_for_reg (XEXP (note
, 0), NULL
, NULL_RTX
);
14512 /* Otherwise, if this register is now referenced in i2
14513 then the register used to be modified in one of the
14514 original insns. If it was i3 (say, in an unused
14515 parallel), it's now completely gone, so the note can
14516 be discarded. But if it was modified in i2, i1 or i0
14517 and we still reference it in i2, then we're
14518 referencing the previous value, and since the
14519 register was modified and REG_UNUSED, we know that
14520 the previous value is now dead. So, if we only
14521 reference the register in i2, we change the note to
14522 REG_DEAD, to reflect the previous value. However, if
14523 we're also setting or clobbering the register as
14524 scratch, we know (because the register was not
14525 referenced in i3) that it's unused, just as it was
14526 unused before, and we place the note in i2. */
14527 if (from_insn
!= i3
&& i2
&& INSN_P (i2
)
14528 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14530 if (!reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14531 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
14532 if (! (REG_P (XEXP (note
, 0))
14533 ? find_regno_note (i2
, REG_NOTE_KIND (note
),
14534 REGNO (XEXP (note
, 0)))
14535 : find_reg_note (i2
, REG_NOTE_KIND (note
),
14546 /* These notes say something about results of an insn. We can
14547 only support them if they used to be on I3 in which case they
14548 remain on I3. Otherwise they are ignored.
14550 If the note refers to an expression that is not a constant, we
14551 must also ignore the note since we cannot tell whether the
14552 equivalence is still true. It might be possible to do
14553 slightly better than this (we only have a problem if I2DEST
14554 or I1DEST is present in the expression), but it doesn't
14555 seem worth the trouble. */
14557 if (from_insn
== i3
14558 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
14563 /* These notes say something about how a register is used. They must
14564 be present on any use of the register in I2 or I3. */
14565 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
14568 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
14577 case REG_LABEL_TARGET
:
14578 case REG_LABEL_OPERAND
:
14579 /* This can show up in several ways -- either directly in the
14580 pattern, or hidden off in the constant pool with (or without?)
14581 a REG_EQUAL note. */
14582 /* ??? Ignore the without-reg_equal-note problem for now. */
14583 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
14584 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
14585 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14586 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
14590 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
14591 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
14592 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
14593 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
14601 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14602 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14604 if (place
&& JUMP_P (place
)
14605 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14606 && (JUMP_LABEL (place
) == NULL
14607 || JUMP_LABEL (place
) == XEXP (note
, 0)))
14609 rtx label
= JUMP_LABEL (place
);
14612 JUMP_LABEL (place
) = XEXP (note
, 0);
14613 else if (LABEL_P (label
))
14614 LABEL_NUSES (label
)--;
14617 if (place2
&& JUMP_P (place2
)
14618 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
14619 && (JUMP_LABEL (place2
) == NULL
14620 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
14622 rtx label
= JUMP_LABEL (place2
);
14625 JUMP_LABEL (place2
) = XEXP (note
, 0);
14626 else if (LABEL_P (label
))
14627 LABEL_NUSES (label
)--;
14633 /* This note says something about the value of a register prior
14634 to the execution of an insn. It is too much trouble to see
14635 if the note is still correct in all situations. It is better
14636 to simply delete it. */
14640 /* If we replaced the right hand side of FROM_INSN with a
14641 REG_EQUAL note, the original use of the dying register
14642 will not have been combined into I3 and I2. In such cases,
14643 FROM_INSN is guaranteed to be the first of the combined
14644 instructions, so we simply need to search back before
14645 FROM_INSN for the previous use or set of this register,
14646 then alter the notes there appropriately.
14648 If the register is used as an input in I3, it dies there.
14649 Similarly for I2, if it is nonzero and adjacent to I3.
14651 If the register is not used as an input in either I3 or I2
14652 and it is not one of the registers we were supposed to eliminate,
14653 there are two possibilities. We might have a non-adjacent I2
14654 or we might have somehow eliminated an additional register
14655 from a computation. For example, we might have had A & B where
14656 we discover that B will always be zero. In this case we will
14657 eliminate the reference to A.
14659 In both cases, we must search to see if we can find a previous
14660 use of A and put the death note there. */
14663 && from_insn
== i2mod
14664 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
14665 tem_insn
= from_insn
;
14669 && CALL_P (from_insn
)
14670 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
14672 else if (i2
&& reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
14674 /* If the new I2 sets the same register that is marked
14675 dead in the note, we do not in general know where to
14676 put the note. One important case we _can_ handle is
14677 when the note comes from I3. */
14678 if (from_insn
== i3
)
14683 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
14685 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
14686 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14688 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
14690 && reg_overlap_mentioned_p (XEXP (note
, 0),
14692 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
14693 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
14700 basic_block bb
= this_basic_block
;
14702 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
14704 if (!NONDEBUG_INSN_P (tem_insn
))
14706 if (tem_insn
== BB_HEAD (bb
))
14711 /* If the register is being set at TEM_INSN, see if that is all
14712 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14713 into a REG_UNUSED note instead. Don't delete sets to
14714 global register vars. */
14715 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
14716 || !global_regs
[REGNO (XEXP (note
, 0))])
14717 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
14719 rtx set
= single_set (tem_insn
);
14720 rtx inner_dest
= 0;
14723 for (inner_dest
= SET_DEST (set
);
14724 (GET_CODE (inner_dest
) == STRICT_LOW_PART
14725 || GET_CODE (inner_dest
) == SUBREG
14726 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
14727 inner_dest
= XEXP (inner_dest
, 0))
14730 /* Verify that it was the set, and not a clobber that
14731 modified the register.
14733 If we cannot delete the setter due to side
14734 effects, mark the user with an UNUSED note instead
14737 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
14738 && rtx_equal_p (XEXP (note
, 0), inner_dest
))
14740 /* Move the notes and links of TEM_INSN elsewhere.
14741 This might delete other dead insns recursively.
14742 First set the pattern to something that won't use
14744 rtx old_notes
= REG_NOTES (tem_insn
);
14746 PATTERN (tem_insn
) = pc_rtx
;
14747 REG_NOTES (tem_insn
) = NULL
;
14749 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
14750 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14751 distribute_links (LOG_LINKS (tem_insn
));
14753 unsigned int regno
= REGNO (XEXP (note
, 0));
14754 reg_stat_type
*rsp
= ®_stat
[regno
];
14755 if (rsp
->last_set
== tem_insn
)
14756 record_value_for_reg (XEXP (note
, 0), NULL
, NULL_RTX
);
14758 SET_INSN_DELETED (tem_insn
);
14759 if (tem_insn
== i2
)
14764 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
14766 /* If there isn't already a REG_UNUSED note, put one
14767 here. Do not place a REG_DEAD note, even if
14768 the register is also used here; that would not
14769 match the algorithm used in lifetime analysis
14770 and can cause the consistency check in the
14771 scheduler to fail. */
14772 if (! find_regno_note (tem_insn
, REG_UNUSED
,
14773 REGNO (XEXP (note
, 0))))
14778 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
14779 || (CALL_P (tem_insn
)
14780 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14784 /* If we are doing a 3->2 combination, and we have a
14785 register which formerly died in i3 and was not used
14786 by i2, which now no longer dies in i3 and is used in
14787 i2 but does not die in i2, and place is between i2
14788 and i3, then we may need to move a link from place to
14790 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14792 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14793 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14795 struct insn_link
*links
= LOG_LINKS (place
);
14796 LOG_LINKS (place
) = NULL
;
14797 distribute_links (links
);
14802 if (tem_insn
== BB_HEAD (bb
))
14808 /* If the register is set or already dead at PLACE, we needn't do
14809 anything with this note if it is still a REG_DEAD note.
14810 We check here if it is set at all, not if is it totally replaced,
14811 which is what `dead_or_set_p' checks, so also check for it being
14814 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14816 unsigned int regno
= REGNO (XEXP (note
, 0));
14817 reg_stat_type
*rsp
= ®_stat
[regno
];
14819 if (dead_or_set_p (place
, XEXP (note
, 0))
14820 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14822 /* Unless the register previously died in PLACE, clear
14823 last_death. [I no longer understand why this is
14825 if (rsp
->last_death
!= place
)
14826 rsp
->last_death
= 0;
14830 rsp
->last_death
= place
;
14832 /* If this is a death note for a hard reg that is occupying
14833 multiple registers, ensure that we are still using all
14834 parts of the object. If we find a piece of the object
14835 that is unused, we must arrange for an appropriate REG_DEAD
14836 note to be added for it. However, we can't just emit a USE
14837 and tag the note to it, since the register might actually
14838 be dead; so we recourse, and the recursive call then finds
14839 the previous insn that used this register. */
14841 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14843 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14844 bool all_used
= true;
14847 for (i
= regno
; i
< endregno
; i
++)
14848 if ((! refers_to_regno_p (i
, PATTERN (place
))
14849 && ! find_regno_fusage (place
, USE
, i
))
14850 || dead_or_set_regno_p (place
, i
))
14858 /* Put only REG_DEAD notes for pieces that are
14859 not already dead or set. */
14861 for (i
= regno
; i
< endregno
;
14862 i
+= hard_regno_nregs (i
, reg_raw_mode
[i
]))
14864 rtx piece
= regno_reg_rtx
[i
];
14865 basic_block bb
= this_basic_block
;
14867 if (! dead_or_set_p (place
, piece
)
14868 && ! reg_bitfield_target_p (piece
,
14871 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14874 distribute_notes (new_note
, place
, place
,
14875 NULL
, NULL_RTX
, NULL_RTX
,
14878 else if (! refers_to_regno_p (i
, PATTERN (place
))
14879 && ! find_regno_fusage (place
, USE
, i
))
14880 for (tem_insn
= PREV_INSN (place
); ;
14881 tem_insn
= PREV_INSN (tem_insn
))
14883 if (!NONDEBUG_INSN_P (tem_insn
))
14885 if (tem_insn
== BB_HEAD (bb
))
14889 if (dead_or_set_p (tem_insn
, piece
)
14890 || reg_bitfield_target_p (piece
,
14891 PATTERN (tem_insn
)))
14893 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14906 /* Any other notes should not be present at this point in the
14908 gcc_unreachable ();
14913 XEXP (note
, 1) = REG_NOTES (place
);
14914 REG_NOTES (place
) = note
;
14916 /* Set added_notes_insn to the earliest insn we added a note to. */
14917 if (added_notes_insn
== 0
14918 || DF_INSN_LUID (added_notes_insn
) > DF_INSN_LUID (place
))
14919 added_notes_insn
= place
;
14924 add_shallow_copy_of_reg_note (place2
, note
);
14926 /* Set added_notes_insn to the earliest insn we added a note to. */
14927 if (added_notes_insn
== 0
14928 || DF_INSN_LUID (added_notes_insn
) > DF_INSN_LUID (place2
))
14929 added_notes_insn
= place2
;
14934 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14935 I3, I2, and I1 to new locations. This is also called to add a link
14936 pointing at I3 when I3's destination is changed. */
14939 distribute_links (struct insn_link
*links
)
14941 struct insn_link
*link
, *next_link
;
14943 for (link
= links
; link
; link
= next_link
)
14945 rtx_insn
*place
= 0;
14949 next_link
= link
->next
;
14951 /* If the insn that this link points to is a NOTE, ignore it. */
14952 if (NOTE_P (link
->insn
))
14956 rtx pat
= PATTERN (link
->insn
);
14957 if (GET_CODE (pat
) == SET
)
14959 else if (GET_CODE (pat
) == PARALLEL
)
14962 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14964 set
= XVECEXP (pat
, 0, i
);
14965 if (GET_CODE (set
) != SET
)
14968 reg
= SET_DEST (set
);
14969 while (GET_CODE (reg
) == ZERO_EXTRACT
14970 || GET_CODE (reg
) == STRICT_LOW_PART
14971 || GET_CODE (reg
) == SUBREG
)
14972 reg
= XEXP (reg
, 0);
14977 if (REGNO (reg
) == link
->regno
)
14980 if (i
== XVECLEN (pat
, 0))
14986 reg
= SET_DEST (set
);
14988 while (GET_CODE (reg
) == ZERO_EXTRACT
14989 || GET_CODE (reg
) == STRICT_LOW_PART
14990 || GET_CODE (reg
) == SUBREG
)
14991 reg
= XEXP (reg
, 0);
14996 /* A LOG_LINK is defined as being placed on the first insn that uses
14997 a register and points to the insn that sets the register. Start
14998 searching at the next insn after the target of the link and stop
14999 when we reach a set of the register or the end of the basic block.
15001 Note that this correctly handles the link that used to point from
15002 I3 to I2. Also note that not much searching is typically done here
15003 since most links don't point very far away. */
15005 for (insn
= NEXT_INSN (link
->insn
);
15006 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
15007 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
15008 insn
= NEXT_INSN (insn
))
15009 if (DEBUG_INSN_P (insn
))
15011 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
15013 if (reg_referenced_p (reg
, PATTERN (insn
)))
15017 else if (CALL_P (insn
)
15018 && find_reg_fusage (insn
, USE
, reg
))
15023 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
15026 /* If we found a place to put the link, place it there unless there
15027 is already a link to the same insn as LINK at that point. */
15031 struct insn_link
*link2
;
15033 FOR_EACH_LOG_LINK (link2
, place
)
15034 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
15039 link
->next
= LOG_LINKS (place
);
15040 LOG_LINKS (place
) = link
;
15042 /* Set added_links_insn to the earliest insn we added a
15044 if (added_links_insn
== 0
15045 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
15046 added_links_insn
= place
;
15052 /* Check for any register or memory mentioned in EQUIV that is not
15053 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
15054 of EXPR where some registers may have been replaced by constants. */
15057 unmentioned_reg_p (rtx equiv
, rtx expr
)
15059 subrtx_iterator::array_type array
;
15060 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
15062 const_rtx x
= *iter
;
15063 if ((REG_P (x
) || MEM_P (x
))
15064 && !reg_mentioned_p (x
, expr
))
15070 /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
15071 the reg-to-reg copy can usefully combine with later instructions, but we
15072 do not want to combine the hard reg into later instructions, for that
15073 restricts register allocation. */
15075 make_more_copies (void)
15079 FOR_EACH_BB_FN (bb
, cfun
)
15083 FOR_BB_INSNS (bb
, insn
)
15085 if (!NONDEBUG_INSN_P (insn
))
15088 rtx set
= single_set (insn
);
15092 rtx dest
= SET_DEST (set
);
15093 if (!(REG_P (dest
) && !HARD_REGISTER_P (dest
)))
15096 rtx src
= SET_SRC (set
);
15097 if (!(REG_P (src
) && HARD_REGISTER_P (src
)))
15099 if (TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
)))
15102 rtx new_reg
= gen_reg_rtx (GET_MODE (dest
));
15103 rtx_insn
*new_insn
= gen_move_insn (new_reg
, src
);
15104 SET_SRC (set
) = new_reg
;
15105 emit_insn_before (new_insn
, insn
);
15106 df_insn_rescan (insn
);
15111 /* Try combining insns through substitution. */
15113 rest_of_handle_combine (void)
15115 make_more_copies ();
15117 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
15118 df_note_add_problem ();
15121 regstat_init_n_sets_and_refs ();
15122 reg_n_sets_max
= max_reg_num ();
15124 bool rebuild_jump_labels_after_combine
15125 = combine_instructions (get_insns (), max_reg_num ());
15127 /* Combining insns may have turned an indirect jump into a
15128 direct jump. Rebuild the JUMP_LABEL fields of jumping
15130 if (rebuild_jump_labels_after_combine
)
15132 if (dom_info_available_p (CDI_DOMINATORS
))
15133 free_dominance_info (CDI_DOMINATORS
);
15134 timevar_push (TV_JUMP
);
15135 rebuild_jump_labels (get_insns ());
15137 timevar_pop (TV_JUMP
);
15140 regstat_free_n_sets_and_refs ();
15145 const pass_data pass_data_combine
=
15147 RTL_PASS
, /* type */
15148 "combine", /* name */
15149 OPTGROUP_NONE
, /* optinfo_flags */
15150 TV_COMBINE
, /* tv_id */
15151 PROP_cfglayout
, /* properties_required */
15152 0, /* properties_provided */
15153 0, /* properties_destroyed */
15154 0, /* todo_flags_start */
15155 TODO_df_finish
, /* todo_flags_finish */
15158 class pass_combine
: public rtl_opt_pass
15161 pass_combine (gcc::context
*ctxt
)
15162 : rtl_opt_pass (pass_data_combine
, ctxt
)
15165 /* opt_pass methods: */
15166 bool gate (function
*) final override
{ return (optimize
> 0); }
15167 unsigned int execute (function
*) final override
15169 rest_of_handle_combine ();
15173 }; // class pass_combine
15175 } // anon namespace
15178 make_pass_combine (gcc::context
*ctxt
)
15180 return new pass_combine (ctxt
);