1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This module is essentially the "combiner" phase of the U. of Arizona
22 Portable Optimizer, but redone to work on our list-structured
23 representation for RTL instead of their string representation.
25 The LOG_LINKS of each insn identify the most recent assignment
26 to each REG used in the insn. It is a list of previous insns,
27 each of which contains a SET for a REG that is used in this insn
28 and not used or set in between. LOG_LINKs never cross basic blocks.
29 They were set up by the preceding pass (lifetime analysis).
31 We try to combine each pair of insns joined by a logical link.
32 We also try to combine triples of insns A, B and C when
33 C has a link back to B and B has a link back to A.
35 LOG_LINKS does not have links for use of the CC0. They don't
36 need to, because the insn that sets the CC0 is always immediately
37 before the insn that tests it. So we always regard a branch
38 insn as having a logical link to the preceding insn. The same is true
39 for an insn explicitly using CC0.
41 We check (with use_crosses_set_p) to avoid combining in such a way
42 as to move a computation to a place where its value would be different.
44 Combination is done by mathematically substituting the previous
45 insn(s) values for the regs they set into the expressions in
46 the later insns that refer to these regs. If the result is a valid insn
47 for our target machine, according to the machine description,
48 we install it, delete the earlier insns, and update the data flow
49 information (LOG_LINKS and REG_NOTES) for what we did.
51 There are a few exceptions where the dataflow information created by
52 flow.c aren't completely updated:
54 - reg_live_length is not updated
55 - reg_n_refs is not adjusted in the rare case when a register is
56 no longer required in a computation
57 - there are extremely rare cases (see distribute_regnotes) when a
59 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
60 removed because there is no way to know which register it was
63 To simplify substitution, we combine only when the earlier insn(s)
64 consist of only a single assignment. To simplify updating afterward,
65 we never combine when a subroutine call appears in the middle.
67 Since we do not represent assignments to CC0 explicitly except when that
68 is all an insn does, there is no LOG_LINKS entry in an insn that uses
69 the condition code for the insn that set the condition code.
70 Fortunately, these two insns must be consecutive.
71 Therefore, every JUMP_INSN is taken to have an implicit logical link
72 to the preceding insn. This is not quite right, since non-jumps can
73 also use the condition code; but in practice such insns would not
84 #include "basic-block.h"
85 #include "insn-config.h"
86 #include "insn-flags.h"
87 #include "insn-codes.h"
88 #include "insn-attr.h"
92 /* It is not safe to use ordinary gen_lowpart in combine.
93 Use gen_lowpart_for_combine instead. See comments there. */
94 #define gen_lowpart dont_use_gen_lowpart_you_dummy
96 /* Number of attempts to combine instructions in this function. */
98 static int combine_attempts
;
100 /* Number of attempts that got as far as substitution in this function. */
102 static int combine_merges
;
104 /* Number of instructions combined with added SETs in this function. */
106 static int combine_extras
;
108 /* Number of instructions combined in this function. */
110 static int combine_successes
;
112 /* Totals over entire compilation. */
114 static int total_attempts
, total_merges
, total_extras
, total_successes
;
116 /* Vector mapping INSN_UIDs to cuids.
117 The cuids are like uids but increase monotonically always.
118 Combine always uses cuids so that it can compare them.
119 But actually renumbering the uids, which we used to do,
120 proves to be a bad idea because it makes it hard to compare
121 the dumps produced by earlier passes with those from later passes. */
123 static int *uid_cuid
;
125 /* Get the cuid of an insn. */
127 #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
129 /* Maximum register number, which is the size of the tables below. */
131 static int combine_max_regno
;
133 /* Record last point of death of (hard or pseudo) register n. */
135 static rtx
*reg_last_death
;
137 /* Record last point of modification of (hard or pseudo) register n. */
139 static rtx
*reg_last_set
;
141 /* Record the cuid of the last insn that invalidated memory
142 (anything that writes memory, and subroutine calls, but not pushes). */
144 static int mem_last_set
;
146 /* Record the cuid of the last CALL_INSN
147 so we can tell whether a potential combination crosses any calls. */
149 static int last_call_cuid
;
151 /* When `subst' is called, this is the insn that is being modified
152 (by combining in a previous insn). The PATTERN of this insn
153 is still the old pattern partially modified and it should not be
154 looked at, but this may be used to examine the successors of the insn
155 to judge whether a simplification is valid. */
157 static rtx subst_insn
;
159 /* This is the lowest CUID that `subst' is currently dealing with.
160 get_last_value will not return a value if the register was set at or
161 after this CUID. If not for this mechanism, we could get confused if
162 I2 or I1 in try_combine were an insn that used the old value of a register
163 to obtain a new value. In that case, we might erroneously get the
164 new value of the register when we wanted the old one. */
166 static int subst_low_cuid
;
168 /* This is the value of undobuf.num_undo when we started processing this
169 substitution. This will prevent gen_rtx_combine from re-used a piece
170 from the previous expression. Doing so can produce circular rtl
173 static int previous_num_undos
;
175 /* The next group of arrays allows the recording of the last value assigned
176 to (hard or pseudo) register n. We use this information to see if a
177 operation being processed is redundant given a prior operation performed
178 on the register. For example, an `and' with a constant is redundant if
179 all the zero bits are already known to be turned off.
181 We use an approach similar to that used by cse, but change it in the
184 (1) We do not want to reinitialize at each label.
185 (2) It is useful, but not critical, to know the actual value assigned
186 to a register. Often just its form is helpful.
188 Therefore, we maintain the following arrays:
190 reg_last_set_value the last value assigned
191 reg_last_set_label records the value of label_tick when the
192 register was assigned
193 reg_last_set_table_tick records the value of label_tick when a
194 value using the register is assigned
195 reg_last_set_invalid set to non-zero when it is not valid
196 to use the value of this register in some
199 To understand the usage of these tables, it is important to understand
200 the distinction between the value in reg_last_set_value being valid
201 and the register being validly contained in some other expression in the
204 Entry I in reg_last_set_value is valid if it is non-zero, and either
205 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
207 Register I may validly appear in any expression returned for the value
208 of another register if reg_n_sets[i] is 1. It may also appear in the
209 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
210 reg_last_set_invalid[j] is zero.
212 If an expression is found in the table containing a register which may
213 not validly appear in an expression, the register is replaced by
214 something that won't match, (clobber (const_int 0)).
216 reg_last_set_invalid[i] is set non-zero when register I is being assigned
217 to and reg_last_set_table_tick[i] == label_tick. */
219 /* Record last value assigned to (hard or pseudo) register n. */
221 static rtx
*reg_last_set_value
;
223 /* Record the value of label_tick when the value for register n is placed in
224 reg_last_set_value[n]. */
226 static short *reg_last_set_label
;
228 /* Record the value of label_tick when an expression involving register n
229 is placed in reg_last_set_value. */
231 static short *reg_last_set_table_tick
;
233 /* Set non-zero if references to register n in expressions should not be
236 static char *reg_last_set_invalid
;
238 /* Incremented for each label. */
240 static short label_tick
;
242 /* Some registers that are set more than once and used in more than one
243 basic block are nevertheless always set in similar ways. For example,
244 a QImode register may be loaded from memory in two places on a machine
245 where byte loads zero extend.
247 We record in the following array what we know about the significant
248 bits of a register, specifically which bits are known to be zero.
250 If an entry is zero, it means that we don't know anything special. */
252 static int *reg_significant
;
254 /* Mode used to compute significance in reg_significant. It is the largest
255 integer mode that can fit in HOST_BITS_PER_INT. */
257 static enum machine_mode significant_mode
;
259 /* Nonzero when reg_significant can be safely used. It is zero while
260 computing reg_significant. This prevents propagating values based
261 on previously set values, which can be incorrect if a variable
262 is modified in a loop. */
264 static int significant_valid
;
266 /* Record one modification to rtl structure
267 to be undone by storing old_contents into *where.
268 is_int is 1 if the contents are an int. */
284 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
285 num_undo says how many are currently recorded.
287 storage is nonzero if we must undo the allocation of new storage.
288 The value of storage is what to pass to obfree.
290 other_insn is nonzero if we have modified some other insn in the process
291 of working on subst_insn. It must be verified too. */
299 struct undo undo
[MAX_UNDO
];
303 static struct undobuf undobuf
;
305 /* Substitute NEWVAL, an rtx expression, into INTO, a place in a some
306 insn. The substitution can be undone by undo_all. If INTO is already
307 set to NEWVAL, do not record this change. */
309 #define SUBST(INTO, NEWVAL) \
310 do { if (undobuf.num_undo < MAX_UNDO) \
312 undobuf.undo[undobuf.num_undo].where = &INTO; \
313 undobuf.undo[undobuf.num_undo].old_contents = INTO; \
314 undobuf.undo[undobuf.num_undo].is_int = 0; \
316 if (undobuf.undo[undobuf.num_undo].old_contents != INTO) \
317 undobuf.num_undo++; \
321 /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
323 Note that substitution for the value of a CONST_INT is not safe. */
325 #define SUBST_INT(INTO, NEWVAL) \
326 do { if (undobuf.num_undo < MAX_UNDO) \
329 = (struct undo_int *)&undobuf.undo[undobuf.num_undo]; \
330 u->where = (int *) &INTO; \
331 u->old_contents = INTO; \
334 if (u->old_contents != INTO) \
335 undobuf.num_undo++; \
339 /* Number of times the pseudo being substituted for
340 was found and replaced. */
342 static int n_occurrences
;
344 static void set_significant ();
345 static void move_deaths ();
347 static void record_value_for_reg ();
348 static void record_dead_and_set_regs ();
349 static int use_crosses_set_p ();
350 static rtx
try_combine ();
351 static rtx
*find_split_point ();
353 static void undo_all ();
354 static int reg_dead_at_p ();
355 static rtx
expand_compound_operation ();
356 static rtx
expand_field_assignment ();
357 static rtx
make_extraction ();
358 static int get_pos_from_mask ();
359 static rtx
force_to_mode ();
360 static rtx
make_field_assignment ();
361 static rtx
make_compound_operation ();
362 static rtx
apply_distributive_law ();
363 static rtx
simplify_and_const_int ();
364 static unsigned significant_bits ();
365 static int merge_outer_ops ();
366 static rtx
simplify_shift_const ();
367 static int recog_for_combine ();
368 static rtx
gen_lowpart_for_combine ();
369 static rtx
gen_rtx_combine ();
370 static rtx
gen_binary ();
371 static rtx
gen_unary ();
372 static enum rtx_code
simplify_comparison ();
373 static int reversible_comparison_p ();
374 static int get_last_value_validate ();
375 static rtx
get_last_value ();
376 static void distribute_notes ();
377 static void distribute_links ();
379 /* Main entry point for combiner. F is the first insn of the function.
380 NREGS is the first unused pseudo-reg number. */
383 combine_instructions (f
, nregs
)
387 register rtx insn
, next
, prev
;
389 register rtx links
, nextlinks
;
391 combine_attempts
= 0;
394 combine_successes
= 0;
396 combine_max_regno
= nregs
;
398 reg_last_death
= (rtx
*) alloca (nregs
* sizeof (rtx
));
399 reg_last_set
= (rtx
*) alloca (nregs
* sizeof (rtx
));
400 reg_last_set_value
= (rtx
*) alloca (nregs
* sizeof (rtx
));
401 reg_last_set_table_tick
= (short *) alloca (nregs
* sizeof (short));
402 reg_last_set_label
= (short *) alloca (nregs
* sizeof (short));
403 reg_last_set_invalid
= (char *) alloca (nregs
* sizeof (short));
404 reg_significant
= (int *) alloca (nregs
* sizeof (int));
406 bzero (reg_last_death
, nregs
* sizeof (rtx
));
407 bzero (reg_last_set
, nregs
* sizeof (rtx
));
408 bzero (reg_last_set_value
, nregs
* sizeof (rtx
));
409 bzero (reg_last_set_table_tick
, nregs
* sizeof (short));
410 bzero (reg_last_set_invalid
, nregs
* sizeof (char));
411 bzero (reg_significant
, nregs
* sizeof (int));
413 init_recog_no_volatile ();
415 /* Compute maximum uid value so uid_cuid can be allocated. */
417 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
418 if (INSN_UID (insn
) > i
)
421 uid_cuid
= (int *) alloca ((i
+ 1) * sizeof (int));
423 significant_mode
= mode_for_size (HOST_BITS_PER_INT
, MODE_INT
, 0);
425 /* Don't use reg_significant when computing it. This can cause problems
426 when, for example, we have j <<= 1 in a loop. */
428 significant_valid
= 0;
430 /* Compute the mapping from uids to cuids.
431 Cuids are numbers assigned to insns, like uids,
432 except that cuids increase monotonically through the code.
434 Scan all SETs and see if we can deduce anything about what
435 bits are significant for some registers. */
437 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
439 INSN_CUID (insn
) = ++i
;
440 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
441 note_stores (PATTERN (insn
), set_significant
);
444 significant_valid
= 1;
446 /* Now scan all the insns in forward order. */
452 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
456 if (GET_CODE (insn
) == CODE_LABEL
)
459 else if (GET_CODE (insn
) == INSN
460 || GET_CODE (insn
) == CALL_INSN
461 || GET_CODE (insn
) == JUMP_INSN
)
463 /* Try this insn with each insn it links back to. */
465 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
466 if ((next
= try_combine (insn
, XEXP (links
, 0), 0)) != 0)
469 /* Try each sequence of three linked insns ending with this one. */
471 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
472 for (nextlinks
= LOG_LINKS (XEXP (links
, 0)); nextlinks
;
473 nextlinks
= XEXP (nextlinks
, 1))
474 if ((next
= try_combine (insn
, XEXP (links
, 0),
475 XEXP (nextlinks
, 0))) != 0)
479 /* Try to combine a jump insn that uses CC0
480 with a preceding insn that sets CC0, and maybe with its
481 logical predecessor as well.
482 This is how we make decrement-and-branch insns.
483 We need this special code because data flow connections
484 via CC0 do not get entered in LOG_LINKS. */
486 if (GET_CODE (insn
) == JUMP_INSN
487 && (prev
= prev_nonnote_insn (insn
)) != 0
488 && GET_CODE (prev
) == INSN
489 && sets_cc0_p (PATTERN (prev
)))
491 if ((next
= try_combine (insn
, prev
, 0)) != 0)
494 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
495 nextlinks
= XEXP (nextlinks
, 1))
496 if ((next
= try_combine (insn
, prev
,
497 XEXP (nextlinks
, 0))) != 0)
501 /* Do the same for an insn that explicitly references CC0. */
502 if (GET_CODE (insn
) == INSN
503 && (prev
= prev_nonnote_insn (insn
)) != 0
504 && GET_CODE (prev
) == INSN
505 && sets_cc0_p (PATTERN (prev
))
506 && GET_CODE (PATTERN (insn
)) == SET
507 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
509 if ((next
= try_combine (insn
, prev
, 0)) != 0)
512 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
513 nextlinks
= XEXP (nextlinks
, 1))
514 if ((next
= try_combine (insn
, prev
,
515 XEXP (nextlinks
, 0))) != 0)
519 /* Finally, see if any of the insns that this insn links to
520 explicitly references CC0. If so, try this insn, that insn,
521 and its predecessor if it sets CC0. */
522 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
523 if (GET_CODE (XEXP (links
, 0)) == INSN
524 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
525 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
526 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
527 && GET_CODE (prev
) == INSN
528 && sets_cc0_p (PATTERN (prev
))
529 && (next
= try_combine (insn
, XEXP (links
, 0), prev
)) != 0)
533 /* Try combining an insn with two different insns whose results it
535 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
536 for (nextlinks
= XEXP (links
, 1); nextlinks
;
537 nextlinks
= XEXP (nextlinks
, 1))
538 if ((next
= try_combine (insn
, XEXP (links
, 0),
539 XEXP (nextlinks
, 0))) != 0)
542 if (GET_CODE (insn
) != NOTE
)
543 record_dead_and_set_regs (insn
);
550 total_attempts
+= combine_attempts
;
551 total_merges
+= combine_merges
;
552 total_extras
+= combine_extras
;
553 total_successes
+= combine_successes
;
556 /* Called via note_stores. If X is a pseudo that is used in more than
557 one basic block, is narrower that HOST_BITS_PER_INT, and is being
558 set, record what bits are significant. If we are clobbering X,
559 ignore this "set" because the clobbered value won't be used.
561 If we are setting only a portion of X and we can't figure out what
562 portion, assume all bits will be used since we don't know what will
566 set_significant (x
, set
)
570 if (GET_CODE (x
) == REG
571 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
572 && reg_n_sets
[REGNO (x
)] > 1
573 && reg_basic_block
[REGNO (x
)] < 0
574 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_INT
)
576 if (GET_CODE (set
) == CLOBBER
)
579 /* If this is a complex assignment, see if we can convert it into a
580 simple assignment. */
581 set
= expand_field_assignment (set
);
582 if (SET_DEST (set
) == x
)
583 reg_significant
[REGNO (x
)]
584 |= significant_bits (SET_SRC (set
), significant_mode
);
586 reg_significant
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
590 /* See if INSN can be combined into I3. PRED and SUCC are optionally
591 insns that were previously combined into I3 or that will be combined
592 into the merger of INSN and I3.
594 Return 0 if the combination is not allowed for any reason.
596 If the combination is allowed, *PDEST will be set to the single
597 destination of INSN and *PSRC to the single source, and this function
601 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
608 rtx set
= 0, src
, dest
;
610 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
611 && next_active_insn (succ
) == i3
)
612 : next_active_insn (insn
) == i3
);
614 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
615 or a PARALLEL consisting of such a SET and CLOBBERs.
617 If INSN has CLOBBER parallel parts, ignore them for our processing.
618 By definition, these happen during the execution of the insn. When it
619 is merged with another insn, all bets are off. If they are, in fact,
620 needed and aren't also supplied in I3, they may be added by
621 recog_for_combine. Otherwise, it won't match.
623 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
626 Get the source and destination of INSN. If more than one, can't
629 if (GET_CODE (PATTERN (insn
)) == SET
)
630 set
= PATTERN (insn
);
631 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
632 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
634 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
636 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
638 switch (GET_CODE (elt
))
640 /* We can ignore CLOBBERs. */
645 /* Ignore SETs whose result isn't used but not those that
646 have side-effects. */
647 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
648 && ! side_effects_p (elt
))
651 /* If we have already found a SET, this is a second one and
652 so we cannot combine with this insn. */
660 /* Anything else means we can't combine. */
666 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
667 so don't do anything with it. */
668 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
677 set
= expand_field_assignment (set
);
678 src
= SET_SRC (set
), dest
= SET_DEST (set
);
680 /* Don't eliminate a store in the stack pointer. */
681 if (dest
== stack_pointer_rtx
682 /* Don't install a subreg involving two modes not tieable.
683 It can worsen register allocation, and can even make invalid reload
684 insns, since the reg inside may need to be copied from in the
685 outside mode, and that may be invalid if it is an fp reg copied in
686 integer mode. As a special exception, we can allow this if
687 I3 is simply copying DEST, a REG, to CC0. */
688 || (GET_CODE (src
) == SUBREG
689 && ! MODES_TIEABLE_P (GET_MODE (src
), GET_MODE (SUBREG_REG (src
)))
691 && ! (GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
692 && SET_DEST (PATTERN (i3
)) == cc0_rtx
693 && GET_CODE (dest
) == REG
&& dest
== SET_SRC (PATTERN (i3
)))
696 /* If we couldn't eliminate a field assignment, we can't combine. */
697 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
698 /* Don't combine with an insn that sets a register to itself if it has
699 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
700 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, 0))
701 /* Can't merge a function call. */
702 || GET_CODE (src
) == CALL
703 /* Don't substitute into an incremented register. */
704 || FIND_REG_INC_NOTE (i3
, dest
)
705 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
706 /* Don't combine the end of a libcall into anything. */
707 || find_reg_note (insn
, REG_RETVAL
, 0)
708 /* Make sure that DEST is not used after SUCC but before I3. */
709 || (succ
&& ! all_adjacent
710 && reg_used_between_p (dest
, succ
, i3
))
711 /* Make sure that the value that is to be substituted for the register
712 does not use any registers whose values alter in between. However,
713 If the insns are adjacent, a use can't cross a set even though we
714 think it might (this can happen for a sequence of insns each setting
715 the same destination; reg_last_set of that register might point to
716 a NOTE). Also, don't move a volatile asm across any other insns. */
718 && (use_crosses_set_p (src
, INSN_CUID (insn
))
719 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))))
720 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
721 better register allocation by not doing the combine. */
722 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
723 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
724 /* Don't combine across a CALL_INSN, because that would possibly
725 change whether the life span of some REGs crosses calls or not,
726 and it is a pain to update that information.
727 Exception: if source is a constant, moving it later can't hurt.
728 Accept that special case, because it helps -fforce-addr a lot. */
729 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
732 /* DEST must either be a REG or CC0. */
733 if (GET_CODE (dest
) == REG
)
735 /* If register alignment is being enforced for multi-word items in all
736 cases except for parameters, it is possible to have a register copy
737 insn referencing a hard register that is not allowed to contain the
738 mode being copied and which would not be valid as an operand of most
739 insns. Eliminate this problem by not combining with such an insn.
741 Also, on some machines we don't want to extend the life of a hard
744 if (GET_CODE (src
) == REG
745 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
746 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
747 #ifdef SMALL_REGISTER_CLASSES
748 /* Don't extend the life of a hard register. */
749 || REGNO (src
) < FIRST_PSEUDO_REGISTER
751 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
752 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))
757 else if (GET_CODE (dest
) != CC0
)
760 /* Don't substitute for a register intended as a clobberable operand. */
761 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
762 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
763 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
764 && rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
))
767 /* If INSN contains anything volatile, or is an `asm' (whether volatile
768 or not), reject, unless nothing volatile comes between it and I3,
769 with the exception of SUCC. */
771 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
772 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
773 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
774 && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
777 /* If INSN or I2 contains an autoincrement or autodecrement,
778 make sure that register is not used between there and I3,
779 and not already used in I3 either.
780 Also insist that I3 not be a jump; if it were one
781 and the incremented register were spilled, we would lose. */
784 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
785 if (REG_NOTE_KIND (link
) == REG_INC
786 && (GET_CODE (i3
) == JUMP_INSN
787 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
788 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
793 /* Don't combine an insn that follows a CC0-setting insn.
794 An insn that uses CC0 must not be separated from the one that sets it.
795 We do, however, allow I2 to follow a CC0-setting insn if that insn
796 is passed as I1; in that case it will be deleted also.
797 We also allow combining in this case if all the insns are adjacent
798 because that would leave the two CC0 insns adjacent as well.
799 It would be more logical to test whether CC0 occurs inside I1 or I2,
800 but that would be much slower, and this ought to be equivalent. */
802 p
= prev_nonnote_insn (insn
);
803 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
808 /* If we get here, we have passed all the tests and the combination is
817 /* LOC is the location within I3 that contains its pattern or the component
818 of a PARALLEL of the pattern. We validate that it is valid for combining.
820 One problem is if I3 modifies its output, as opposed to replacing it
821 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
822 so would produce an insn that is not equivalent to the original insns.
826 (set (reg:DI 101) (reg:DI 100))
827 (set (subreg:SI (reg:DI 101) 0) <foo>)
829 This is NOT equivalent to:
831 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
832 (set (reg:DI 101) (reg:DI 100))])
834 Not only does this modify 100 (in which case it might still be valid
835 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
837 We can also run into a problem if I2 sets a register that I1
838 uses and I1 gets directly substituted into I3 (not via I2). In that
839 case, we would be getting the wrong value of I2DEST into I3, so we
840 must reject the combination. This case occurs when I2 and I1 both
841 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
842 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
843 of a SET must prevent combination from occurring.
845 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
846 if the destination of a SET is a hard register.
848 Before doing the above check, we first try to expand a field assignment
849 into a set of logical operations.
851 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
852 we place a register that is both set and used within I3. If more than one
853 such register is detected, we fail.
855 Return 1 if the combination is valid, zero otherwise. */
858 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
868 if (GET_CODE (x
) == SET
)
870 rtx set
= expand_field_assignment (x
);
871 rtx dest
= SET_DEST (set
);
872 rtx src
= SET_SRC (set
);
873 rtx inner_dest
= dest
, inner_src
= src
;
877 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
878 || GET_CODE (inner_dest
) == SUBREG
879 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
880 inner_dest
= XEXP (inner_dest
, 0);
882 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
885 while (GET_CODE (inner_src
) == STRICT_LOW_PART
886 || GET_CODE (inner_src
) == SUBREG
887 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
888 inner_src
= XEXP (inner_src
, 0);
890 /* If it is better that two different modes keep two different pseudos,
891 avoid combining them. This avoids producing the following pattern
893 (set (subreg:SI (reg/v:QI 21) 0)
894 (lshiftrt:SI (reg/v:SI 20)
896 If that were made, reload could not handle the pair of
897 reg 20/21, since it would try to get any GENERAL_REGS
898 but some of them don't handle QImode. */
900 if (rtx_equal_p (inner_src
, i2dest
)
901 && GET_CODE (inner_dest
) == REG
902 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
906 /* Check for the case where I3 modifies its output, as
908 if ((inner_dest
!= dest
909 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
910 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
911 /* This is the same test done in can_combine_p except that we
912 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
914 || (GET_CODE (inner_dest
) == REG
915 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
916 #ifdef SMALL_REGISTER_CLASSES
917 && GET_CODE (src
) != CALL
919 && ! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
920 GET_MODE (inner_dest
))
924 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
927 /* If DEST is used in I3, it is being killed in this insn,
928 so record that for later. */
929 if (pi3dest_killed
&& GET_CODE (dest
) == REG
930 && reg_referenced_p (dest
, PATTERN (i3
)))
935 *pi3dest_killed
= dest
;
939 else if (GET_CODE (x
) == PARALLEL
)
943 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
944 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
945 i1_not_in_src
, pi3dest_killed
))
952 /* Try to combine the insns I1 and I2 into I3.
953 Here I1 and I2 appear earlier than I3.
954 I1 can be zero; then we combine just I2 into I3.
956 It we are combining three insns and the resulting insn is not recognized,
957 try splitting it into two insns. If that happens, I2 and I3 are retained
958 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
961 If we created two insns, return I2; otherwise return I3.
962 Return 0 if the combination does not work. Then nothing is changed. */
965 try_combine (i3
, i2
, i1
)
966 register rtx i3
, i2
, i1
;
968 /* New patterns for I3 and I3, respectively. */
969 rtx newpat
, newi2pat
= 0;
970 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
971 int added_sets_1
, added_sets_2
;
972 /* Total number of SETs to put into I3. */
974 /* Nonzero is I2's body now appears in I3. */
976 /* INSN_CODEs for new I3, new I2, and user of condition code. */
977 int insn_code_number
, i2_code_number
, other_code_number
;
978 /* Contains I3 if the destination of I3 is used in its source, which means
979 that the old life of I3 is being killed. If that usage is placed into
980 I2 and not in I3, a REG_DEAD note must be made. */
981 rtx i3dest_killed
= 0;
982 /* SET_DEST and SET_SRC of I2 and I1. */
983 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
984 /* PATTERN (I2), or a copy of it in certain cases. */
986 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
987 int i2dest_in_i2src
, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
989 /* Notes that must be added to REG_NOTES in I3 and I2. */
990 rtx new_i3_notes
, new_i2_notes
;
997 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
998 This can occur when flow deletes an insn that it has merged into an
999 auto-increment address. We also can't do anything if I3 has a
1000 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1003 if (GET_RTX_CLASS (GET_CODE (i3
)) != 'i'
1004 || GET_RTX_CLASS (GET_CODE (i2
)) != 'i'
1005 || (i1
&& GET_RTX_CLASS (GET_CODE (i1
)) != 'i')
1006 || find_reg_note (i3
, REG_LIBCALL
, 0))
1011 undobuf
.num_undo
= previous_num_undos
= 0;
1012 undobuf
.other_insn
= 0;
1014 /* Save the current high-water-mark so we can free storage if we didn't
1015 accept this combination. */
1016 undobuf
.storage
= (char *) oballoc (0);
1018 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1019 code below, set I1 to be the earlier of the two insns. */
1020 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1021 temp
= i1
, i1
= i2
, i2
= temp
;
1023 /* First check for one important special-case that the code below will
1024 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1025 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1026 we may be able to replace that destination with the destination of I3.
1027 This occurs in the common code where we compute both a quotient and
1028 remainder into a structure, in which case we want to do the computation
1029 directly into the structure to avoid register-register copies.
1031 We make very conservative checks below and only try to handle the
1032 most common cases of this. For example, we only handle the case
1033 where I2 and I3 are adjacent to avoid making difficult register
1036 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1037 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1038 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1039 #ifdef SMALL_REGISTER_CLASSES
1040 && (GET_CODE (SET_DEST (PATTERN (i3
))) != REG
1041 || REGNO (SET_DEST (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
)
1043 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1044 && GET_CODE (PATTERN (i2
)) == PARALLEL
1045 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1046 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1047 below would need to check what is inside (and reg_overlap_mentioned_p
1048 doesn't support those codes anyway). Don't allow those destinations;
1049 the resulting insn isn't likely to be recognized anyway. */
1050 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1051 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1052 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1053 SET_DEST (PATTERN (i3
)))
1054 && next_real_insn (i2
) == i3
)
1056 rtx p2
= PATTERN (i2
);
1058 /* Make sure that the destination of I3,
1059 which we are going to substitute into one output of I2,
1060 is not used within another output of I2. We must avoid making this:
1061 (parallel [(set (mem (reg 69)) ...)
1062 (set (reg 69) ...)])
1063 which is not well-defined as to order of actions.
1064 (Besides, reload can't handle output reloads for this.)
1066 The problem can also happen if the dest of I3 is a memory ref,
1067 if another dest in I2 is an indirect memory ref. */
1068 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1069 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1070 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1071 SET_DEST (XVECEXP (p2
, 0, i
))))
1074 if (i
== XVECLEN (p2
, 0))
1075 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1076 if (SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1081 subst_low_cuid
= INSN_CUID (i2
);
1084 i2dest
= SET_SRC (PATTERN (i3
));
1086 /* Replace the dest in I2 with our dest and make the resulting
1087 insn the new pattern for I3. Then skip to where we
1088 validate the pattern. Everything was set up above. */
1089 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1090 SET_DEST (PATTERN (i3
)));
1093 goto validate_replacement
;
1098 /* If we have no I1 and I2 looks like:
1099 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1101 make up a dummy I1 that is
1104 (set (reg:CC X) (compare:CC Y (const_int 0)))
1106 (We can ignore any trailing CLOBBERs.)
1108 This undoes a previous combination and allows us to match a branch-and-
1111 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1112 && XVECLEN (PATTERN (i2
), 0) >= 2
1113 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1114 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1116 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1117 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1118 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1119 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1120 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1121 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1123 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1124 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1129 /* We make I1 with the same INSN_UID as I2. This gives it
1130 the same INSN_CUID for value tracking. Our fake I1 will
1131 never appear in the insn stream so giving it the same INSN_UID
1132 as I2 will not cause a problem. */
1134 i1
= gen_rtx (INSN
, VOIDmode
, INSN_UID (i2
), 0, i2
,
1135 XVECEXP (PATTERN (i2
), 0, 1), -1, 0, 0);
1137 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1138 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1139 SET_DEST (PATTERN (i1
)));
1144 /* Verify that I2 and I1 are valid for combining. */
1145 if (! can_combine_p (i2
, i3
, i1
, 0, &i2dest
, &i2src
)
1146 || (i1
&& ! can_combine_p (i1
, i3
, 0, i2
, &i1dest
, &i1src
)))
1152 /* Record whether I2DEST is used in I2SRC and similarly for the other
1153 cases. Knowing this will help in register status updating below. */
1154 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1155 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1156 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1158 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1160 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1162 /* Ensure that I3's pattern can be the destination of combines. */
1163 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1164 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1171 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1172 We used to do this EXCEPT in one case: I3 has a post-inc in an
1173 output operand. However, that exception can give rise to insns like
1175 which is a famous insn on the PDP-11 where the value of r3 used as the
1176 source was model-dependent. Avoid this sort of thing. */
1179 if (!(GET_CODE (PATTERN (i3
)) == SET
1180 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1181 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1182 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1183 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1184 /* It's not the exception. */
1187 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1188 if (REG_NOTE_KIND (link
) == REG_INC
1189 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1191 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1198 /* See if the SETs in I1 or I2 need to be kept around in the merged
1199 instruction: whenever the value set there is still needed past I3.
1200 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1202 For the SET in I1, we have two cases: If I1 and I2 independently
1203 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1204 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1205 in I1 needs to be kept around unless I1DEST dies or is set in either
1206 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1207 I1DEST. If so, we know I1 feeds into I2. */
1209 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1212 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1213 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1215 /* If the set in I2 needs to be kept around, we must make a copy of
1216 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1217 PATTERN (I2), we are only substituting for the original I1DEST, not into
1218 an already-substituted copy. This also prevents making self-referential
1219 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1222 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1223 ? gen_rtx (SET
, VOIDmode
, i2dest
, i2src
)
1227 i2pat
= copy_rtx (i2pat
);
1231 /* Substitute in the latest insn for the regs set by the earlier ones. */
1233 maxreg
= max_reg_num ();
1236 subst_low_cuid
= i1
? INSN_CUID (i1
) : INSN_CUID (i2
);
1238 /* It is possible that the source of I2 or I1 may be performing an
1239 unneeded operation, such as a ZERO_EXTEND of something that is known
1240 to have the high part zero. Handle that case by letting subst look at
1241 the innermost one of them.
1243 Another way to do this would be to have a function that tries to
1244 simplify a single insn instead of merging two or more insns. We don't
1245 do this because of the potential of infinite loops and because
1246 of the potential extra memory required. However, doing it the way
1247 we are is a bit of a kludge and doesn't catch all cases.
1249 But only do this if -fexpensive-optimizations since it slows things down
1250 and doesn't usually win. */
1252 if (flag_expensive_optimizations
)
1254 /* Pass pc_rtx so no substitutions are done, just simplifications.
1255 The cases that we are interested in here do not involve the few
1256 cases were is_replaced is checked. */
1258 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1260 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1262 previous_num_undos
= undobuf
.num_undo
;
1266 /* Many machines that don't use CC0 have insns that can both perform an
1267 arithmetic operation and set the condition code. These operations will
1268 be represented as a PARALLEL with the first element of the vector
1269 being a COMPARE of an arithmetic operation with the constant zero.
1270 The second element of the vector will set some pseudo to the result
1271 of the same arithmetic operation. If we simplify the COMPARE, we won't
1272 match such a pattern and so will generate an extra insn. Here we test
1273 for this case, where both the comparison and the operation result are
1274 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1275 I2SRC. Later we will make the PARALLEL that contains I2. */
1277 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1278 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1279 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1280 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1283 enum machine_mode compare_mode
;
1285 newpat
= PATTERN (i3
);
1286 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1290 #ifdef EXTRA_CC_MODES
1291 /* See if a COMPARE with the operand we substituted in should be done
1292 with the mode that is currently being used. If not, do the same
1293 processing we do in `subst' for a SET; namely, if the destination
1294 is used only once, try to replace it with a register of the proper
1295 mode and also replace the COMPARE. */
1296 if (undobuf
.other_insn
== 0
1297 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1298 &undobuf
.other_insn
))
1299 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1301 != GET_MODE (SET_DEST (newpat
))))
1303 int regno
= REGNO (SET_DEST (newpat
));
1304 rtx new_dest
= gen_rtx (REG
, compare_mode
, regno
);
1306 if (regno
< FIRST_PSEUDO_REGISTER
1307 || (reg_n_sets
[regno
] == 1 && ! added_sets_2
1308 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1310 if (regno
>= FIRST_PSEUDO_REGISTER
)
1311 SUBST (regno_reg_rtx
[regno
], new_dest
);
1313 SUBST (SET_DEST (newpat
), new_dest
);
1314 SUBST (XEXP (*cc_use
, 0), new_dest
);
1315 SUBST (SET_SRC (newpat
),
1316 gen_rtx_combine (COMPARE
, compare_mode
,
1317 i2src
, const0_rtx
));
1320 undobuf
.other_insn
= 0;
1327 n_occurrences
= 0; /* `subst' counts here */
1329 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1330 need to make a unique copy of I2SRC each time we substitute it
1331 to avoid self-referential rtl. */
1333 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1334 ! i1_feeds_i3
&& i1dest_in_i1src
);
1335 previous_num_undos
= undobuf
.num_undo
;
1337 /* Record whether i2's body now appears within i3's body. */
1338 i2_is_used
= n_occurrences
;
1341 /* If we already got a failure, don't try to do more. Otherwise,
1342 try to substitute in I1 if we have it. */
1344 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1346 /* Before we can do this substitution, we must redo the test done
1347 above (see detailed comments there) that ensures that I1DEST
1348 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1350 if (! combinable_i3pat (0, &newpat
, i1dest
, 0, 0, 0))
1357 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1358 previous_num_undos
= undobuf
.num_undo
;
1361 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1362 to count all the ways that I2SRC and I1SRC can be used. */
1363 if ((FIND_REG_INC_NOTE (i2
, 0) != 0
1364 && i2_is_used
+ added_sets_2
> 1)
1365 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, 0) != 0
1366 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1368 /* Fail if we tried to make a new register (we used to abort, but there's
1369 really no reason to). */
1370 || max_reg_num () != maxreg
1371 /* Fail if we couldn't do something and have a CLOBBER. */
1372 || GET_CODE (newpat
) == CLOBBER
)
1378 /* If the actions of the earlier insns must be kept
1379 in addition to substituting them into the latest one,
1380 we must make a new PARALLEL for the latest insn
1381 to hold additional the SETs. */
1383 if (added_sets_1
|| added_sets_2
)
1387 if (GET_CODE (newpat
) == PARALLEL
)
1389 rtvec old
= XVEC (newpat
, 0);
1390 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1391 newpat
= gen_rtx (PARALLEL
, VOIDmode
, rtvec_alloc (total_sets
));
1392 bcopy (&old
->elem
[0], &XVECEXP (newpat
, 0, 0),
1393 sizeof (old
->elem
[0]) * old
->num_elem
);
1398 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1399 newpat
= gen_rtx (PARALLEL
, VOIDmode
, rtvec_alloc (total_sets
));
1400 XVECEXP (newpat
, 0, 0) = old
;
1404 XVECEXP (newpat
, 0, --total_sets
)
1405 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1406 ? gen_rtx (SET
, VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1410 /* If there is no I1, use I2's body as is. We used to also not do
1411 the subst call below if I2 was substituted into I3,
1412 but that could lose a simplification. */
1414 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
1416 /* See comment where i2pat is assigned. */
1417 XVECEXP (newpat
, 0, --total_sets
)
1418 = subst (i2pat
, i1dest
, i1src
, 0, 0);
1422 /* We come here when we are replacing a destination in I2 with the
1423 destination of I3. */
1424 validate_replacement
:
1426 /* Is the result of combination a valid instruction? */
1427 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1429 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1430 the second SET's destination is a register that is unused. In that case,
1431 we just need the first SET. This can occur when simplifying a divmod
1432 insn. We *must* test for this case here because the code below that
1433 splits two independent SETs doesn't handle this case correctly when it
1434 updates the register status. Also check the case where the first
1435 SET's destination is unused. That would not cause incorrect code, but
1436 does cause an unneeded insn to remain. */
1438 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
1439 && XVECLEN (newpat
, 0) == 2
1440 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1441 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1442 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
1443 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
1444 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
1445 && asm_noperands (newpat
) < 0)
1447 newpat
= XVECEXP (newpat
, 0, 0);
1448 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1451 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
1452 && XVECLEN (newpat
, 0) == 2
1453 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1454 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1455 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
1456 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
1457 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
1458 && asm_noperands (newpat
) < 0)
1460 newpat
= XVECEXP (newpat
, 0, 1);
1461 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1464 /* If we were combining three insns and the result is a simple SET
1465 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1466 insns. There are two ways to do this. It can be split using a
1467 machine-specific method (like when you have an addition of a large
1468 constant) or by combine in the function find_split_point. */
1470 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
1471 && asm_noperands (newpat
) < 0)
1473 rtx m_split
, *split
;
1475 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1476 use I2DEST as a scratch register will help. */
1478 m_split
= split_insns (newpat
, i3
);
1480 m_split
= split_insns (gen_rtx (PARALLEL
, VOIDmode
,
1481 gen_rtvec (2, newpat
,
1482 gen_rtx (CLOBBER
, VOIDmode
,
1486 if (m_split
&& GET_CODE (m_split
) == SEQUENCE
1487 && XVECLEN (m_split
, 0) == 2
1488 && (next_real_insn (i2
) == i3
1489 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
1492 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
1493 newpat
= PATTERN (XVECEXP (m_split
, 0, 1));
1495 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
1496 if (i2_code_number
>= 0)
1497 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1500 /* If we can split it and use I2DEST, go ahead and see if that
1501 helps things be recognized. Verify that none of the registers
1502 are set between I2 and I3. */
1503 else if ((split
= find_split_point (&newpat
)) != 0
1505 && GET_CODE (i2dest
) == REG
1507 /* We need I2DEST in the proper mode. If it is a hard register
1508 or the only use of a pseudo, we can change its mode. */
1509 && (GET_MODE (*split
) == GET_MODE (i2dest
)
1510 || GET_MODE (*split
) == VOIDmode
1511 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
1512 || (reg_n_sets
[REGNO (i2dest
)] == 1 && ! added_sets_2
1513 && ! REG_USERVAR_P (i2dest
)))
1514 && (next_real_insn (i2
) == i3
1515 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
1516 /* We can't overwrite I2DEST if its value is still used by
1518 && ! reg_referenced_p (i2dest
, newpat
))
1520 rtx newdest
= i2dest
;
1522 /* Get NEWDEST as a register in the proper mode. We have already
1523 validated that we can do this. */
1524 if (GET_MODE (i2dest
) != GET_MODE (*split
)
1525 && GET_MODE (*split
) != VOIDmode
)
1527 newdest
= gen_rtx (REG
, GET_MODE (*split
), REGNO (i2dest
));
1529 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
1530 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
1533 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1534 an ASHIFT. This can occur if it was inside a PLUS and hence
1535 appeared to be a memory address. This is a kludge. */
1536 if (GET_CODE (*split
) == MULT
1537 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
1538 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
1539 SUBST (*split
, gen_rtx_combine (ASHIFT
, GET_MODE (*split
),
1541 gen_rtx (CONST_INT
, VOIDmode
, i
)));
1543 #ifdef INSN_SCHEDULING
1544 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1545 be written as a ZERO_EXTEND. */
1546 if (GET_CODE (*split
) == SUBREG
1547 && GET_CODE (SUBREG_REG (*split
)) == MEM
)
1548 SUBST (*split
, gen_rtx_combine (ZERO_EXTEND
, GET_MODE (*split
),
1552 newi2pat
= gen_rtx_combine (SET
, VOIDmode
, newdest
, *split
);
1553 SUBST (*split
, newdest
);
1554 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
1555 if (i2_code_number
>= 0)
1556 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1560 /* Check for a case where we loaded from memory in a narrow mode and
1561 then sign extended it, but we need both registers. In that case,
1562 we have a PARALLEL with both loads from the same memory location.
1563 We can split this into a load from memory followed by a register-register
1564 copy. This saves at least one insn, more if register allocation can
1565 eliminate the copy. */
1567 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
1568 && GET_CODE (newpat
) == PARALLEL
1569 && XVECLEN (newpat
, 0) == 2
1570 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1571 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
1572 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1573 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
1574 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
1575 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
1577 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
1578 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
1579 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
1580 SET_SRC (XVECEXP (newpat
, 0, 1)))
1581 && ! find_reg_note (i3
, REG_UNUSED
,
1582 SET_DEST (XVECEXP (newpat
, 0, 0))))
1584 newi2pat
= XVECEXP (newpat
, 0, 0);
1585 newpat
= XVECEXP (newpat
, 0, 1);
1586 SUBST (SET_SRC (newpat
),
1587 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)),
1588 SET_DEST (newi2pat
)));
1589 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
1590 if (i2_code_number
>= 0)
1591 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1593 if (insn_code_number
>= 0)
1598 /* If we will be able to accept this, we have made a change to the
1599 destination of I3. This can invalidate a LOG_LINKS pointing
1600 to I3. No other part of combine.c makes such a transformation.
1602 The new I3 will have a destination that was previously the
1603 destination of I1 or I2 and which was used in i2 or I3. Call
1604 distribute_links to make a LOG_LINK from the next use of
1605 that destination. */
1607 PATTERN (i3
) = newpat
;
1608 distribute_links (gen_rtx (INSN_LIST
, VOIDmode
, i3
, 0));
1610 /* I3 now uses what used to be its destination and which is
1611 now I2's destination. That means we need a LOG_LINK from
1612 I3 to I2. But we used to have one, so we still will.
1614 However, some later insn might be using I2's dest and have
1615 a LOG_LINK pointing at I3. We must remove this link.
1616 The simplest way to remove the link is to point it at I1,
1617 which we know will be a NOTE. */
1619 for (insn
= NEXT_INSN (i3
);
1620 insn
&& GET_CODE (insn
) != CODE_LABEL
1621 && GET_CODE (PREV_INSN (insn
)) != JUMP_INSN
;
1622 insn
= NEXT_INSN (insn
))
1624 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
1625 && reg_referenced_p (SET_DEST (newi2pat
), PATTERN (insn
)))
1627 for (link
= LOG_LINKS (insn
); link
;
1628 link
= XEXP (link
, 1))
1629 if (XEXP (link
, 0) == i3
)
1630 XEXP (link
, 0) = i1
;
1638 /* Similarly, check for a case where we have a PARALLEL of two independent
1639 SETs but we started with three insns. In this case, we can do the sets
1640 as two separate insns. This case occurs when some SET allows two
1641 other insns to combine, but the destination of that SET is still live. */
1643 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
1644 && GET_CODE (newpat
) == PARALLEL
1645 && XVECLEN (newpat
, 0) == 2
1646 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1647 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
1648 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
1649 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1650 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
1651 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
1652 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
1654 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
1655 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
1656 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
1657 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
1658 XVECEXP (newpat
, 0, 0))
1659 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
1660 XVECEXP (newpat
, 0, 1)))
1662 newi2pat
= XVECEXP (newpat
, 0, 1);
1663 newpat
= XVECEXP (newpat
, 0, 0);
1665 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
1666 if (i2_code_number
>= 0)
1667 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1670 /* If it still isn't recognized, fail and change things back the way they
1672 if ((insn_code_number
< 0
1673 /* Is the result a reasonable ASM_OPERANDS? */
1674 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
1680 /* If we had to change another insn, make sure it is valid also. */
1681 if (undobuf
.other_insn
)
1683 rtx other_notes
= REG_NOTES (undobuf
.other_insn
);
1684 rtx other_pat
= PATTERN (undobuf
.other_insn
);
1685 rtx new_other_notes
;
1688 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
1691 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
1697 PATTERN (undobuf
.other_insn
) = other_pat
;
1699 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
1700 are still valid. Then add any non-duplicate notes added by
1701 recog_for_combine. */
1702 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
1704 next
= XEXP (note
, 1);
1706 if (REG_NOTE_KIND (note
) == REG_UNUSED
1707 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
1708 remove_note (undobuf
.other_insn
, note
);
1711 distribute_notes (new_other_notes
, undobuf
.other_insn
,
1712 undobuf
.other_insn
, 0, 0, 0);
1715 /* We now know that we can do this combination. Merge the insns and
1716 update the status of registers and LOG_LINKS. */
1719 rtx i3notes
, i2notes
, i1notes
= 0;
1720 rtx i3links
, i2links
, i1links
= 0;
1722 int all_adjacent
= (next_real_insn (i2
) == i3
1723 && (i1
== 0 || next_real_insn (i1
) == i2
));
1725 /* Compute which registers we expect to eliminate. */
1726 rtx elim_i2
= (newi2pat
|| i2dest_in_i2src
|| i2dest_in_i1src
1728 rtx elim_i1
= i1
== 0 || i1dest_in_i1src
? 0 : i1dest
;
1730 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
1732 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
1733 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
1735 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
1737 /* Ensure that we do not have something that should not be shared but
1738 occurs multiple times in the new insns. Check this by first
1739 resetting all the `used' flags and then copying anything is shared. */
1741 reset_used_flags (i3notes
);
1742 reset_used_flags (i2notes
);
1743 reset_used_flags (i1notes
);
1744 reset_used_flags (newpat
);
1745 reset_used_flags (newi2pat
);
1746 if (undobuf
.other_insn
)
1747 reset_used_flags (PATTERN (undobuf
.other_insn
));
1749 i3notes
= copy_rtx_if_shared (i3notes
);
1750 i2notes
= copy_rtx_if_shared (i2notes
);
1751 i1notes
= copy_rtx_if_shared (i1notes
);
1752 newpat
= copy_rtx_if_shared (newpat
);
1753 newi2pat
= copy_rtx_if_shared (newi2pat
);
1754 if (undobuf
.other_insn
)
1755 reset_used_flags (PATTERN (undobuf
.other_insn
));
1757 INSN_CODE (i3
) = insn_code_number
;
1758 PATTERN (i3
) = newpat
;
1759 if (undobuf
.other_insn
)
1760 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
1762 /* We had one special case above where I2 had more than one set and
1763 we replaced a destination of one of those sets with the destination
1764 of I3. In that case, we have to update LOG_LINKS of insns later
1765 in this basic block. Note that this (expensive) case is rare. */
1767 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
1768 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
1769 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
1770 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
1771 && ! find_reg_note (i2
, REG_UNUSED
,
1772 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
1776 for (insn
= NEXT_INSN (i2
); insn
; insn
= NEXT_INSN (insn
))
1778 if (insn
!= i3
&& GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1779 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
1780 if (XEXP (link
, 0) == i2
)
1781 XEXP (link
, 0) = i3
;
1783 if (GET_CODE (insn
) == CODE_LABEL
1784 || GET_CODE (insn
) == JUMP_INSN
)
1796 INSN_CODE (i2
) = i2_code_number
;
1797 PATTERN (i2
) = newi2pat
;
1801 PUT_CODE (i2
, NOTE
);
1802 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
1803 NOTE_SOURCE_FILE (i2
) = 0;
1810 PUT_CODE (i1
, NOTE
);
1811 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
1812 NOTE_SOURCE_FILE (i1
) = 0;
1815 /* Get death notes for everything that is now used in either I3 or
1816 I2 and used to die in a previous insn. */
1818 move_deaths (newpat
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
), i3
, &midnotes
);
1820 move_deaths (newi2pat
, INSN_CUID (i1
), i2
, &midnotes
);
1822 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
1824 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: 0, elim_i2
, elim_i1
);
1826 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: 0, elim_i2
, elim_i1
);
1828 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: 0, elim_i2
, elim_i1
);
1830 distribute_notes (midnotes
, 0, i3
, newi2pat
? i2
: 0, elim_i2
, elim_i1
);
1832 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
1833 know these are REG_UNUSED and want them to go to the desired insn,
1834 so we always pass it as i3. */
1835 if (newi2pat
&& new_i2_notes
)
1836 distribute_notes (new_i2_notes
, i2
, i2
, 0, 0, 0);
1838 distribute_notes (new_i3_notes
, i3
, i3
, 0, 0, 0);
1840 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
1841 put a REG_DEAD note for it somewhere. Similarly for I2 and I1. */
1843 distribute_notes (gen_rtx (EXPR_LIST
, REG_DEAD
, i3dest_killed
, 0),
1844 0, i3
, newi2pat
? i2
: 0, 0, 0);
1845 if (i2dest_in_i2src
)
1846 distribute_notes (gen_rtx (EXPR_LIST
, REG_DEAD
, i2dest
, 0),
1847 0, i3
, newi2pat
? i2
: 0, 0, 0);
1848 if (i1dest_in_i1src
)
1849 distribute_notes (gen_rtx (EXPR_LIST
, REG_DEAD
, i1dest
, 0),
1850 0, i3
, newi2pat
? i2
: 0, 0, 0);
1852 distribute_links (i3links
);
1853 distribute_links (i2links
);
1854 distribute_links (i1links
);
1856 if (GET_CODE (i2dest
) == REG
)
1858 /* The insn that previously set this register doesn't exist, and
1859 this life of the register may not exist either. Show that
1860 we don't know its value any more. If we don't do this and
1861 I2 set the register to a value that depended on its old
1862 contents, we will get confused. If this insn is used, thing
1863 will be set correctly in combine_instructions. */
1864 record_value_for_reg (i2dest
, 0, 0);
1866 /* If the reg formerly set in I2 died only once and that was in I3,
1867 zero its use count so it won't make `reload' do any work. */
1868 if (! added_sets_2
&& newi2pat
== 0)
1870 regno
= REGNO (i2dest
);
1871 reg_n_sets
[regno
]--;
1872 if (reg_n_sets
[regno
] == 0
1873 && ! (basic_block_live_at_start
[0][regno
/ HOST_BITS_PER_INT
]
1874 & (1 << (regno
% HOST_BITS_PER_INT
))))
1875 reg_n_refs
[regno
] = 0;
1879 if (i1
&& GET_CODE (i1dest
) == REG
)
1881 record_value_for_reg (i1dest
, 0, 0);
1882 regno
= REGNO (i1dest
);
1885 reg_n_sets
[regno
]--;
1886 if (reg_n_sets
[regno
] == 0
1887 && ! (basic_block_live_at_start
[0][regno
/ HOST_BITS_PER_INT
]
1888 & (1 << (regno
% HOST_BITS_PER_INT
))))
1889 reg_n_refs
[regno
] = 0;
1893 /* If I3 is now an unconditional jump, ensure that it has a
1894 BARRIER following it since it may have initially been a
1895 conditional jump. */
1897 if ((GET_CODE (newpat
) == RETURN
|| simplejump_p (i3
))
1898 && GET_CODE (next_nonnote_insn (i3
)) != BARRIER
)
1899 emit_barrier_after (i3
);
1902 combine_successes
++;
1904 return newi2pat
? i2
: i3
;
1907 /* Undo all the modifications recorded in undobuf. */
1913 if (undobuf
.num_undo
> MAX_UNDO
)
1914 undobuf
.num_undo
= MAX_UNDO
;
1915 for (i
= undobuf
.num_undo
- 1; i
>= 0; i
--)
1916 *undobuf
.undo
[i
].where
= undobuf
.undo
[i
].old_contents
;
1918 obfree (undobuf
.storage
);
1919 undobuf
.num_undo
= 0;
1922 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
1923 where we have an arithmetic expression and return that point.
1925 try_combine will call this function to see if an insn can be split into
1929 find_split_point (loc
)
1933 enum rtx_code code
= GET_CODE (x
);
1935 int len
= 0, pos
, unsignedp
;
1938 /* First special-case some codes. */
1942 #ifdef INSN_SCHEDULING
1943 /* If we are making a paradoxical SUBREG invalid, it becomes a split
1945 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
1948 return find_split_point (&SUBREG_REG (x
));
1952 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
1953 using LO_SUM and HIGH. */
1954 if (GET_CODE (XEXP (x
, 0)) == CONST
1955 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
1958 gen_rtx_combine (LO_SUM
, Pmode
,
1959 gen_rtx_combine (HIGH
, Pmode
, XEXP (x
, 0)),
1961 return &XEXP (XEXP (x
, 0), 0);
1965 /* If we have a PLUS whose second operand is a constant and the
1966 address is not valid, perhaps will can split it up using
1967 the machine-specific way to split large constants. We use
1968 the first pseudo-reg (one of the virtual regs) as a placeholder;
1969 it will not remain in the result. */
1970 if (GET_CODE (XEXP (x
, 0)) == PLUS
1971 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1972 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
1974 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
1975 rtx seq
= split_insns (gen_rtx (SET
, VOIDmode
, reg
, XEXP (x
, 0)),
1978 /* This should have produced two insns, each of which sets our
1979 placeholder. If the source of the second is a valid address,
1980 we can make put both sources together and make a split point
1983 if (seq
&& XVECLEN (seq
, 0) == 2
1984 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
1985 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
1986 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
1987 && ! reg_mentioned_p (reg
,
1988 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
1989 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
1990 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
1991 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
1992 && memory_address_p (GET_MODE (x
),
1993 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
1995 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
1996 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
1998 /* Replace the placeholder in SRC2 with SRC1. If we can
1999 find where in SRC2 it was placed, that can become our
2000 split point and we can replace this address with SRC2.
2001 Just try two obvious places. */
2003 src2
= replace_rtx (src2
, reg
, src1
);
2005 if (XEXP (src2
, 0) == src1
)
2006 split
= &XEXP (src2
, 0);
2007 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2008 && XEXP (XEXP (src2
, 0), 0) == src1
)
2009 split
= &XEXP (XEXP (src2
, 0), 0);
2013 SUBST (XEXP (x
, 0), src2
);
2022 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2023 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2024 we need to put the operand into a register. So split at that
2027 if (SET_DEST (x
) == cc0_rtx
2028 && GET_CODE (SET_SRC (x
)) != COMPARE
2029 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2030 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2031 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2032 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2033 return &SET_SRC (x
);
2036 /* See if we can split SET_SRC as it stands. */
2037 split
= find_split_point (&SET_SRC (x
));
2038 if (split
&& split
!= &SET_SRC (x
))
2041 /* See if this is a bitfield assignment with everything constant. If
2042 so, this is an IOR of an AND, so split it into that. */
2043 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2044 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2045 <= HOST_BITS_PER_INT
)
2046 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2047 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2048 && GET_CODE (SET_SRC (x
)) == CONST_INT
2049 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2050 + INTVAL (XEXP (SET_DEST (x
), 2)))
2051 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2052 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2054 int pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2055 int len
= INTVAL (XEXP (SET_DEST (x
), 1));
2056 int src
= INTVAL (SET_SRC (x
));
2057 rtx dest
= XEXP (SET_DEST (x
), 0);
2058 enum machine_mode mode
= GET_MODE (dest
);
2059 unsigned int mask
= (1 << len
) - 1;
2062 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
2067 gen_binary (IOR
, mode
, dest
,
2068 gen_rtx (CONST_INT
, VOIDmode
, src
<< pos
)));
2071 gen_binary (IOR
, mode
,
2072 gen_binary (AND
, mode
, dest
,
2073 gen_rtx (CONST_INT
, VOIDmode
,
2075 & GET_MODE_MASK (mode
)))),
2076 gen_rtx (CONST_INT
, VOIDmode
, src
<< pos
)));
2078 SUBST (SET_DEST (x
), dest
);
2080 split
= find_split_point (&SET_SRC (x
));
2081 if (split
&& split
!= &SET_SRC (x
))
2085 /* Otherwise, see if this is an operation that we can split into two.
2086 If so, try to split that. */
2087 code
= GET_CODE (SET_SRC (x
));
2092 inner
= XEXP (SET_SRC (x
), 0);
2094 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
2100 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2101 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
2103 inner
= XEXP (SET_SRC (x
), 0);
2104 len
= INTVAL (XEXP (SET_SRC (x
), 1));
2105 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
2108 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
2110 unsignedp
= (code
== ZERO_EXTRACT
);
2115 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
2117 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
2119 if (unsignedp
&& len
< HOST_BITS_PER_INT
)
2124 gen_rtx_combine (LSHIFTRT
, mode
,
2125 gen_lowpart_for_combine (mode
, inner
),
2126 gen_rtx (CONST_INT
, VOIDmode
, pos
)),
2127 gen_rtx (CONST_INT
, VOIDmode
, (1 << len
) - 1)));
2129 split
= find_split_point (&SET_SRC (x
));
2130 if (split
&& split
!= &SET_SRC (x
))
2138 gen_rtx_combine (ASHIFT
, mode
,
2139 gen_lowpart_for_combine (mode
, inner
),
2140 gen_rtx (CONST_INT
, VOIDmode
,
2141 (GET_MODE_BITSIZE (mode
)
2143 gen_rtx (CONST_INT
, VOIDmode
,
2144 GET_MODE_BITSIZE (mode
) - len
)));
2146 split
= find_split_point (&SET_SRC (x
));
2147 if (split
&& split
!= &SET_SRC (x
))
2152 /* See if this is a simple operation with a constant as the second
2153 operand. It might be that this constant is out of range and hence
2154 could be used as a split point. */
2155 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
2156 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
2157 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
2158 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
2159 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
2160 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
2161 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
2163 return &XEXP (SET_SRC (x
), 1);
2165 /* Finally, see if this is a simple operation with its first operand
2166 not in a register. The operation might require this operand in a
2167 register, so return it as a split point. We can always do this
2168 because if the first operand were another operation, we would have
2169 already found it as a split point. */
2170 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
2171 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
2172 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
2173 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
2174 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
2175 return &XEXP (SET_SRC (x
), 0);
2181 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2182 it is better to write this as (not (ior A B)) so we can split it.
2183 Similarly for IOR. */
2184 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
2187 gen_rtx_combine (NOT
, GET_MODE (x
),
2188 gen_rtx_combine (code
== IOR
? AND
: IOR
,
2190 XEXP (XEXP (x
, 0), 0),
2191 XEXP (XEXP (x
, 1), 0))));
2192 return find_split_point (loc
);
2195 /* Many RISC machines have a large set of logical insns. If the
2196 second operand is a NOT, put it first so we will try to split the
2197 other operand first. */
2198 if (GET_CODE (XEXP (x
, 1)) == NOT
)
2200 rtx tem
= XEXP (x
, 0);
2201 SUBST (XEXP (x
, 0), XEXP (x
, 1));
2202 SUBST (XEXP (x
, 1), tem
);
2207 /* Otherwise, select our actions depending on our rtx class. */
2208 switch (GET_RTX_CLASS (code
))
2210 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2212 split
= find_split_point (&XEXP (x
, 2));
2215 /* ... fall through ... */
2219 split
= find_split_point (&XEXP (x
, 1));
2222 /* ... fall through ... */
2224 /* Some machines have (and (shift ...) ...) insns. If X is not
2225 an AND, but XEXP (X, 0) is, use it as our split point. */
2226 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
2227 return &XEXP (x
, 0);
2229 split
= find_split_point (&XEXP (x
, 0));
2235 /* Otherwise, we don't have a split point. */
2239 /* Throughout X, replace FROM with TO, and return the result.
2240 The result is TO if X is FROM;
2241 otherwise the result is X, but its contents may have been modified.
2242 If they were modified, a record was made in undobuf so that
2243 undo_all will (among other things) return X to its original state.
2245 If the number of changes necessary is too much to record to undo,
2246 the excess changes are not made, so the result is invalid.
2247 The changes already made can still be undone.
2248 undobuf.num_undo is incremented for such changes, so by testing that
2249 the caller can tell whether the result is valid.
2251 `n_occurrences' is incremented each time FROM is replaced.
2253 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2255 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2256 by copying if `n_occurrences' is non-zero. */
2259 subst (x
, from
, to
, in_dest
, unique_copy
)
2260 register rtx x
, from
, to
;
2265 register int len
, i
;
2266 register enum rtx_code code
= GET_CODE (x
), orig_code
= code
;
2268 enum machine_mode mode
= GET_MODE (x
);
2269 enum machine_mode op0_mode
= VOIDmode
;
2274 /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe
2275 replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM).
2276 If it is 0, that cannot be done. We can now do this for any MEM
2277 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded.
2278 If not for that, MEM's would very rarely be safe. */
2280 /* Reject MODEs bigger than a word, because we might not be able
2281 to reference a two-register group starting with an arbitrary register
2282 (and currently gen_lowpart might crash for a SUBREG). */
2284 #define FAKE_EXTEND_SAFE_P(MODE, FROM) \
2285 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
2287 /* Two expressions are equal if they are identical copies of a shared
2288 RTX or if they are both registers with the same register number
2291 #define COMBINE_RTX_EQUAL_P(X,Y) \
2293 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2294 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2296 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
2299 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
2302 /* If X and FROM are the same register but different modes, they will
2303 not have been seen as equal above. However, flow.c will make a
2304 LOG_LINKS entry for that case. If we do nothing, we will try to
2305 rerecognize our original insn and, when it succeeds, we will
2306 delete the feeding insn, which is incorrect.
2308 So force this insn not to match in this (rare) case. */
2309 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
2310 && REGNO (x
) == REGNO (from
))
2311 return gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
2313 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2314 of which may contain things that can be combined. */
2315 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
2318 /* It is possible to have a subexpression appear twice in the insn.
2319 Suppose that FROM is a register that appears within TO.
2320 Then, after that subexpression has been scanned once by `subst',
2321 the second time it is scanned, TO may be found. If we were
2322 to scan TO here, we would find FROM within it and create a
2323 self-referent rtl structure which is completely wrong. */
2324 if (COMBINE_RTX_EQUAL_P (x
, to
))
2327 len
= GET_RTX_LENGTH (code
);
2328 fmt
= GET_RTX_FORMAT (code
);
2330 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2331 set up to skip this common case. All other cases where we want to
2332 suppress replacing something inside a SET_SRC are handled via the
2335 && (GET_CODE (SET_DEST (x
)) == REG
2336 || GET_CODE (SET_DEST (x
)) == CC0
2337 || GET_CODE (SET_DEST (x
)) == PC
))
2340 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2342 op0_mode
= GET_MODE (XEXP (x
, 0));
2344 for (i
= 0; i
< len
; i
++)
2349 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2352 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
2354 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
2359 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0, unique_copy
);
2361 /* If this substitution failed, this whole thing fails. */
2362 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
2366 SUBST (XVECEXP (x
, i
, j
), new);
2369 else if (fmt
[i
] == 'e')
2373 if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
2375 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
2379 /* If we are in a SET_DEST, suppress most cases unless we
2380 have gone inside a MEM, in which case we want to
2381 simplify the address. We assume here that things that
2382 are actually part of the destination have their inner
2383 parts in the first expression. This is true for SUBREG,
2384 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2385 things aside from REG and MEM that should appear in a
2387 new = subst (XEXP (x
, i
), from
, to
,
2389 && (code
== SUBREG
|| code
== STRICT_LOW_PART
2390 || code
== ZERO_EXTRACT
))
2392 && i
== 0), unique_copy
);
2394 /* If we found that we will have to reject this combination,
2395 indicate that by returning the CLOBBER ourselves, rather than
2396 an expression containing it. This will speed things up as
2397 well as prevent accidents where two CLOBBERs are considered
2398 to be equal, thus producing an incorrect simplification. */
2400 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
2403 SUBST (XEXP (x
, i
), new);
2407 /* If this is a commutative operation, put a constant last and a complex
2408 expression first. We don't need to do this for comparisons here. */
2409 if (GET_RTX_CLASS (code
) == 'c'
2410 && ((CONSTANT_P (XEXP (x
, 0)) && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
2411 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == 'o'
2412 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')
2413 || (GET_CODE (XEXP (x
, 0)) == SUBREG
2414 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == 'o'
2415 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')))
2418 SUBST (XEXP (x
, 0), XEXP (x
, 1));
2419 SUBST (XEXP (x
, 1), temp
);
2422 /* Try to fold this expression in case we have constants that weren't
2425 switch (GET_RTX_CLASS (code
))
2428 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
2431 temp
= simplify_relational_operation (code
, op0_mode
,
2432 XEXP (x
, 0), XEXP (x
, 1));
2433 #ifdef FLOAT_STORE_FLAG_VALUE
2434 if (temp
!= 0 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2435 temp
= ((temp
== const0_rtx
) ? CONST0_RTX (GET_MODE (x
))
2436 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE
, GET_MODE (x
)));
2441 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
2445 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
2446 XEXP (x
, 1), XEXP (x
, 2));
2453 /* We come back to here if we have replaced the expression with one of
2454 a different code and it is likely that further simplification will be
2459 /* If we have restarted more than 4 times, we are probably looping, so
2461 if (++n_restarts
> 4)
2464 code
= GET_CODE (x
);
2466 /* First see if we can apply the inverse distributive law. */
2467 if (code
== PLUS
|| code
== MINUS
|| code
== IOR
|| code
== XOR
)
2469 x
= apply_distributive_law (x
);
2470 code
= GET_CODE (x
);
2473 /* If CODE is an associative operation not otherwise handled, see if we
2474 can associate some operands. This can win if they are constants or
2475 if they are logically related (i.e. (a & b) & a. */
2476 if ((code
== PLUS
|| code
== MINUS
2477 || code
== MULT
|| code
== AND
|| code
== IOR
|| code
== XOR
2478 || code
== DIV
|| code
== UDIV
2479 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
2480 && GET_MODE_CLASS (mode
) == MODE_INT
)
2482 if (GET_CODE (XEXP (x
, 0)) == code
)
2484 rtx other
= XEXP (XEXP (x
, 0), 0);
2485 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
2486 rtx inner_op1
= XEXP (x
, 1);
2489 /* Make sure we pass the constant operand if any as the second
2490 one if this is a commutative operation. */
2491 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
2493 rtx tem
= inner_op0
;
2494 inner_op0
= inner_op1
;
2497 inner
= simplify_binary_operation (code
== MINUS
? PLUS
2498 : code
== DIV
? MULT
2499 : code
== UDIV
? MULT
2501 mode
, inner_op0
, inner_op1
);
2503 /* For commutative operations, try the other pair if that one
2505 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
2507 other
= XEXP (XEXP (x
, 0), 1);
2508 inner
= simplify_binary_operation (code
, mode
,
2509 XEXP (XEXP (x
, 0), 0),
2515 x
= gen_binary (code
, mode
, other
, inner
);
2522 /* A little bit of algebraic simplification here. */
2526 /* Ensure that our address has any ASHIFTs converted to MULT in case
2527 address-recognizing predicates are called later. */
2528 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
2529 SUBST (XEXP (x
, 0), temp
);
2533 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
2534 is paradoxical. If we can't do that safely, then it becomes
2535 something nonsensical so that this combination won't take place. */
2537 if (GET_CODE (SUBREG_REG (x
)) == MEM
2538 && (GET_MODE_SIZE (mode
)
2539 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2541 rtx inner
= SUBREG_REG (x
);
2542 int endian_offset
= 0;
2543 /* Don't change the mode of the MEM
2544 if that would change the meaning of the address. */
2545 if (MEM_VOLATILE_P (SUBREG_REG (x
))
2546 || mode_dependent_address_p (XEXP (inner
, 0)))
2547 return gen_rtx (CLOBBER
, mode
, const0_rtx
);
2549 #if BYTES_BIG_ENDIAN
2550 if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
2551 endian_offset
+= UNITS_PER_WORD
- GET_MODE_SIZE (mode
);
2552 if (GET_MODE_SIZE (GET_MODE (inner
)) < UNITS_PER_WORD
)
2553 endian_offset
-= UNITS_PER_WORD
- GET_MODE_SIZE (GET_MODE (inner
));
2555 /* Note if the plus_constant doesn't make a valid address
2556 then this combination won't be accepted. */
2557 x
= gen_rtx (MEM
, mode
,
2558 plus_constant (XEXP (inner
, 0),
2559 (SUBREG_WORD (x
) * UNITS_PER_WORD
2561 MEM_VOLATILE_P (x
) = MEM_VOLATILE_P (inner
);
2562 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (inner
);
2563 MEM_IN_STRUCT_P (x
) = MEM_IN_STRUCT_P (inner
);
2567 /* If we are in a SET_DEST, these other cases can't apply. */
2571 /* Changing mode twice with SUBREG => just change it once,
2572 or not at all if changing back to starting mode. */
2573 if (GET_CODE (SUBREG_REG (x
)) == SUBREG
)
2575 if (mode
== GET_MODE (SUBREG_REG (SUBREG_REG (x
)))
2576 && SUBREG_WORD (x
) == 0 && SUBREG_WORD (SUBREG_REG (x
)) == 0)
2577 return SUBREG_REG (SUBREG_REG (x
));
2579 SUBST_INT (SUBREG_WORD (x
),
2580 SUBREG_WORD (x
) + SUBREG_WORD (SUBREG_REG (x
)));
2581 SUBST (SUBREG_REG (x
), SUBREG_REG (SUBREG_REG (x
)));
2584 /* SUBREG of a hard register => just change the register number
2585 and/or mode. If the hard register is not valid in that mode,
2586 suppress this combination. */
2588 if (GET_CODE (SUBREG_REG (x
)) == REG
2589 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
)
2591 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
),
2593 return gen_rtx (REG
, mode
,
2594 REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
));
2596 return gen_rtx (CLOBBER
, mode
, const0_rtx
);
2599 /* For a constant, try to pick up the part we want. Handle a full
2600 word and low-order part. Only do this if we are narrowing
2601 the constant; if it is being widened, we have no idea what
2602 the extra bits will have been set to. */
2604 if (CONSTANT_P (SUBREG_REG (x
)) && op0_mode
!= VOIDmode
2605 && GET_MODE_SIZE (mode
) == UNITS_PER_WORD
2606 && GET_MODE_SIZE (op0_mode
) < UNITS_PER_WORD
2607 && GET_MODE_CLASS (mode
) == MODE_INT
)
2609 temp
= operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
),
2615 if (CONSTANT_P (SUBREG_REG (x
)) && subreg_lowpart_p (x
)
2616 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (op0_mode
))
2617 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
2619 /* If we are narrowing the object, we need to see if we can simplify
2620 the expression for the object knowing that we only need the
2621 low-order bits. We do this by computing an AND of the object
2622 with only the bits we care about. That will produce any needed
2623 simplifications. If the resulting computation is just the
2624 AND with the significant bits, our operand is the first operand
2625 of the AND. Otherwise, it is the resulting expression. */
2626 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))
2627 && subreg_lowpart_p (x
)
2628 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= HOST_BITS_PER_INT
)
2630 temp
= simplify_and_const_int (0, GET_MODE (SUBREG_REG (x
)),
2631 SUBREG_REG (x
), GET_MODE_MASK (mode
));
2632 if (GET_CODE (temp
) == AND
&& GET_CODE (XEXP (temp
, 1)) == CONST_INT
2633 && INTVAL (XEXP (temp
, 1)) == GET_MODE_MASK (mode
))
2634 temp
= XEXP (temp
, 0);
2635 return gen_lowpart_for_combine (mode
, temp
);
2641 /* (not (plus X -1)) can become (neg X). */
2642 if (GET_CODE (XEXP (x
, 0)) == PLUS
2643 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
2645 x
= gen_rtx_combine (NEG
, mode
, XEXP (XEXP (x
, 0), 0));
2649 /* Similarly, (not (neg X)) is (plus X -1). */
2650 if (GET_CODE (XEXP (x
, 0)) == NEG
)
2652 x
= gen_rtx_combine (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
2656 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
2657 other than 1, but that is not valid. We could do a similar
2658 simplification for (not (lshiftrt C X)) where C is just the sign bit,
2659 but this doesn't seem common enough to bother with. */
2660 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
2661 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
2663 x
= gen_rtx (ROTATE
, mode
, gen_unary (NOT
, mode
, const1_rtx
),
2664 XEXP (XEXP (x
, 0), 1));
2668 if (GET_CODE (XEXP (x
, 0)) == SUBREG
2669 && subreg_lowpart_p (XEXP (x
, 0))
2670 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
2671 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
2672 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
2673 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
2675 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
2677 x
= gen_rtx (ROTATE
, inner_mode
,
2678 gen_unary (NOT
, inner_mode
, const1_rtx
),
2679 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
2680 x
= gen_lowpart_for_combine (mode
, x
);
2684 #if STORE_FLAG_VALUE == -1
2685 /* (not (comparison foo bar)) can be done by reversing the comparison
2687 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
2688 && reversible_comparison_p (XEXP (x
, 0)))
2689 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x
, 0))),
2690 mode
, XEXP (XEXP (x
, 0), 0),
2691 XEXP (XEXP (x
, 0), 1));
2694 /* Apply De Morgan's laws to reduce number of patterns for machines
2695 with negating logical insns (and-not, nand, etc.). If result has
2696 only one NOT, put it first, since that is how the patterns are
2699 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
2701 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
2703 if (GET_CODE (in1
) == NOT
)
2704 in1
= XEXP (in1
, 0);
2706 in1
= gen_rtx_combine (NOT
, GET_MODE (in1
), in1
);
2708 if (GET_CODE (in2
) == NOT
)
2709 in2
= XEXP (in2
, 0);
2710 else if (GET_CODE (in2
) == CONST_INT
2711 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_INT
)
2712 in2
= gen_rtx (CONST_INT
, VOIDmode
,
2713 GET_MODE_MASK (mode
) & ~ INTVAL (in2
));
2715 in2
= gen_rtx_combine (NOT
, GET_MODE (in2
), in2
);
2717 if (GET_CODE (in2
) == NOT
)
2720 in2
= in1
; in1
= tem
;
2723 x
= gen_rtx_combine (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
2730 /* (neg (plus X 1)) can become (not X). */
2731 if (GET_CODE (XEXP (x
, 0)) == PLUS
2732 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
2734 x
= gen_rtx_combine (NOT
, mode
, XEXP (XEXP (x
, 0), 0));
2738 /* Similarly, (neg (not X)) is (plus X 1). */
2739 if (GET_CODE (XEXP (x
, 0)) == NOT
)
2741 x
= gen_rtx_combine (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), const1_rtx
);
2745 /* (neg (abs X)) is X if X is a value known to be either -1 or 0. */
2746 if (GET_CODE (XEXP (x
, 0)) == ABS
2747 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTRACT
2748 && XEXP (XEXP (XEXP (x
, 0), 0), 1) == const1_rtx
)
2749 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ASHIFTRT
2750 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
2751 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
2752 == GET_MODE_BITSIZE (mode
) - 1))
2753 || ((temp
= get_last_value (XEXP (XEXP (x
, 0), 0))) != 0
2754 && ((GET_CODE (temp
) == SIGN_EXTRACT
2755 && XEXP (temp
, 1) == const1_rtx
)
2756 || (GET_CODE (temp
) == ASHIFTRT
2757 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
2758 && (INTVAL (XEXP (temp
, 1))
2759 == GET_MODE_BITSIZE (mode
) - 1))))))
2760 return XEXP (XEXP (x
, 0), 0);
2762 /* (neg (minus X Y)) can become (minus Y X). */
2763 if (GET_CODE (XEXP (x
, 0)) == MINUS
2764 && (GET_MODE_CLASS (mode
) != MODE_FLOAT
2765 /* x-y != -(y-x) with IEEE floating point. */
2766 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
))
2768 x
= gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
2769 XEXP (XEXP (x
, 0), 0));
2773 /* NEG commutes with ASHIFT since it is multiplication. Only do this
2774 if we can then eliminate the NEG (e.g.,
2775 if the operand is a constant). */
2777 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
2779 temp
= simplify_unary_operation (NEG
, mode
,
2780 XEXP (XEXP (x
, 0), 0), mode
);
2783 SUBST (XEXP (XEXP (x
, 0), 0), temp
);
2788 temp
= expand_compound_operation (XEXP (x
, 0));
2790 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
2791 replaced by (lshiftrt X C). This will convert
2792 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
2794 if (GET_CODE (temp
) == ASHIFTRT
2795 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
2796 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
2798 x
= simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
2799 INTVAL (XEXP (temp
, 1)));
2803 /* If X has only a single bit significant, say, bit I, convert
2804 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
2805 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
2806 (sign_extract X 1 Y). But only do this if TEMP isn't a register
2807 or a SUBREG of one since we'd be making the expression more
2808 complex if it was just a register. */
2810 if (GET_CODE (temp
) != REG
2811 && ! (GET_CODE (temp
) == SUBREG
2812 && GET_CODE (SUBREG_REG (temp
)) == REG
)
2813 && (i
= exact_log2 (significant_bits (temp
, mode
))) >= 0)
2815 rtx temp1
= simplify_shift_const
2817 simplify_shift_const (0, ASHIFT
, mode
, temp
,
2818 GET_MODE_BITSIZE (mode
) - 1 - i
),
2819 GET_MODE_BITSIZE (mode
) - 1 - i
);
2821 /* If all we did was surround TEMP with the two shifts, we
2822 haven't improved anything, so don't use it. Otherwise,
2823 we are better off with TEMP1. */
2824 if (GET_CODE (temp1
) != ASHIFTRT
2825 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
2826 || XEXP (XEXP (temp1
, 0), 0) != temp
)
2834 case FLOAT_TRUNCATE
:
2835 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
2836 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
2837 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
2838 return XEXP (XEXP (x
, 0), 0);
2843 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
2844 using cc0, in which case we want to leave it as a COMPARE
2845 so we can distinguish it from a register-register-copy. */
2846 if (XEXP (x
, 1) == const0_rtx
)
2849 /* In IEEE floating point, x-0 is not the same as x. */
2850 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
2851 || GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) == MODE_INT
)
2852 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
2858 /* (const (const X)) can become (const X). Do it this way rather than
2859 returning the inner CONST since CONST can be shared with a
2861 if (GET_CODE (XEXP (x
, 0)) == CONST
)
2862 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
2867 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
2868 can add in an offset. find_split_point will split this address up
2869 again if it doesn't match. */
2870 if (GET_CODE (XEXP (x
, 0)) == HIGH
2871 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
2877 /* If we have (plus (plus (A const) B)), associate it so that CONST is
2878 outermost. That's because that's the way indexed addresses are
2879 supposed to appear. This code used to check many more cases, but
2880 they are now checked elsewhere. */
2881 if (GET_CODE (XEXP (x
, 0)) == PLUS
2882 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
2883 return gen_binary (PLUS
, mode
,
2884 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
2886 XEXP (XEXP (x
, 0), 1));
2888 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
2889 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
2890 bit-field and can be replaced by either a sign_extend or a
2891 sign_extract. The `and' may be a zero_extend. */
2892 if (GET_CODE (XEXP (x
, 0)) == XOR
2893 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2894 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2895 && INTVAL (XEXP (x
, 1)) == - INTVAL (XEXP (XEXP (x
, 0), 1))
2896 && (i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
2897 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_INT
2898 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
2899 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
2900 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
2901 == (1 << (i
+ 1)) - 1))
2902 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
2903 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
2906 x
= simplify_shift_const
2908 simplify_shift_const (0, ASHIFT
, mode
,
2909 XEXP (XEXP (XEXP (x
, 0), 0), 0),
2910 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
2911 GET_MODE_BITSIZE (mode
) - (i
+ 1));
2915 /* If only the low-order bit of X is significant, (plus x -1)
2916 can become (ashiftrt (ashift (xor x 1) C) C) where C is
2917 the bitsize of the mode - 1. This allows simplification of
2918 "a = (b & 8) == 0;" */
2919 if (XEXP (x
, 1) == constm1_rtx
2920 && GET_CODE (XEXP (x
, 0)) != REG
2921 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
2922 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
2923 && significant_bits (XEXP (x
, 0), mode
) == 1)
2925 x
= simplify_shift_const
2927 simplify_shift_const (0, ASHIFT
, mode
,
2928 gen_rtx_combine (XOR
, mode
,
2929 XEXP (x
, 0), const1_rtx
),
2930 GET_MODE_BITSIZE (mode
) - 1),
2931 GET_MODE_BITSIZE (mode
) - 1);
2937 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
2938 (and <foo> (const_int pow2-1)) */
2939 if (GET_CODE (XEXP (x
, 1)) == AND
2940 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
2941 && exact_log2 (- INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
2942 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
2944 x
= simplify_and_const_int (0, mode
, XEXP (x
, 0),
2945 - INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
2951 /* If we have (mult (plus A B) C), apply the distributive law and then
2952 the inverse distributive law to see if things simplify. This
2953 occurs mostly in addresses, often when unrolling loops. */
2955 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
2957 x
= apply_distributive_law
2958 (gen_binary (PLUS
, mode
,
2959 gen_binary (MULT
, mode
,
2960 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
2961 gen_binary (MULT
, mode
,
2962 XEXP (XEXP (x
, 0), 1), XEXP (x
, 1))));
2964 if (GET_CODE (x
) != MULT
)
2968 /* If this is multiplication by a power of two and its first operand is
2969 a shift, treat the multiply as a shift to allow the shifts to
2970 possibly combine. */
2971 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2972 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
2973 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
2974 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
2975 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
2976 || GET_CODE (XEXP (x
, 0)) == ROTATE
2977 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
2979 x
= simplify_shift_const (0, ASHIFT
, mode
, XEXP (x
, 0), i
);
2983 /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */
2984 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
2985 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
2986 return gen_rtx_combine (ASHIFT
, mode
, XEXP (x
, 1),
2987 XEXP (XEXP (x
, 0), 1));
2991 /* If this is a divide by a power of two, treat it as a shift if
2992 its first operand is a shift. */
2993 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2994 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
2995 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
2996 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
2997 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
2998 || GET_CODE (XEXP (x
, 0)) == ROTATE
2999 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
3001 x
= simplify_shift_const (0, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
3007 case GT
: case GTU
: case GE
: case GEU
:
3008 case LT
: case LTU
: case LE
: case LEU
:
3009 /* If the first operand is a condition code, we can't do anything
3011 if (GET_CODE (XEXP (x
, 0)) == COMPARE
3012 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
3014 && XEXP (x
, 0) != cc0_rtx
3018 rtx op0
= XEXP (x
, 0);
3019 rtx op1
= XEXP (x
, 1);
3020 enum rtx_code new_code
;
3022 if (GET_CODE (op0
) == COMPARE
)
3023 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
3025 /* Simplify our comparison, if possible. */
3026 new_code
= simplify_comparison (code
, &op0
, &op1
);
3028 #if STORE_FLAG_VALUE == 1
3029 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3030 if only the low-order bit is significant in X (such as when
3031 X is a ZERO_EXTRACT of one bit. Similarly, we can convert
3033 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
3034 && op1
== const0_rtx
3035 && significant_bits (op0
, GET_MODE (op0
)) == 1)
3036 return gen_lowpart_for_combine (mode
, op0
);
3037 else if (new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
3038 && op1
== const0_rtx
3039 && significant_bits (op0
, GET_MODE (op0
)) == 1)
3040 return gen_rtx_combine (XOR
, mode
,
3041 gen_lowpart_for_combine (mode
, op0
),
3045 #if STORE_FLAG_VALUE == -1
3046 /* If STORE_FLAG_VALUE is -1, we can convert (ne x 0)
3047 to (neg x) if only the low-order bit of X is significant.
3048 This converts (ne (zero_extract X 1 Y) 0) to
3049 (sign_extract X 1 Y). */
3050 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
3051 && op1
== const0_rtx
3052 && significant_bits (op0
, GET_MODE (op0
)) == 1)
3054 x
= gen_rtx_combine (NEG
, mode
,
3055 gen_lowpart_for_combine (mode
, op0
));
3060 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3061 one significant bit, we can convert (ne x 0) to (ashift x c)
3062 where C puts the bit in the sign bit. Remove any AND with
3063 STORE_FLAG_VALUE when we are done, since we are only going to
3064 test the sign bit. */
3065 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
3066 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_INT
3067 && STORE_FLAG_VALUE
== 1 << (GET_MODE_BITSIZE (mode
) - 1)
3068 && op1
== const0_rtx
3069 && mode
== GET_MODE (op0
)
3070 && (i
= exact_log2 (significant_bits (op0
, GET_MODE (op0
)))) >= 0)
3072 x
= simplify_shift_const (0, ASHIFT
, mode
, op0
,
3073 GET_MODE_BITSIZE (mode
) - 1 - i
);
3074 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
3080 /* If the code changed, return a whole new comparison. */
3081 if (new_code
!= code
)
3082 return gen_rtx_combine (new_code
, mode
, op0
, op1
);
3084 /* Otherwise, keep this operation, but maybe change its operands.
3085 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3086 SUBST (XEXP (x
, 0), op0
);
3087 SUBST (XEXP (x
, 1), op1
);
3092 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
3093 reversed, do so to avoid needing two sets of patterns for
3094 subtract-and-branch insns. */
3095 if (XEXP (x
, 1) == pc_rtx
3096 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3097 && reversible_comparison_p (XEXP (x
, 0)))
3100 gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x
, 0))),
3101 GET_MODE (XEXP (x
, 0)),
3102 XEXP (XEXP (x
, 0), 0),
3103 XEXP (XEXP (x
, 0), 1)));
3104 SUBST (XEXP (x
, 1), XEXP (x
, 2));
3105 SUBST (XEXP (x
, 2), pc_rtx
);
3113 /* If we are processing SET_DEST, we are done. */
3117 x
= expand_compound_operation (x
);
3118 if (GET_CODE (x
) != code
)
3123 /* (set (pc) (return)) gets written as (return). */
3124 if (GET_CODE (SET_DEST (x
)) == PC
&& GET_CODE (SET_SRC (x
)) == RETURN
)
3127 /* Convert this into a field assignment operation, if possible. */
3128 x
= make_field_assignment (x
);
3130 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some
3131 operation, and X being a REG or (subreg (reg)), we may be able to
3132 convert this to (set (subreg:m2 x) (op)).
3134 We can always do this if M1 is narrower than M2 because that
3135 means that we only care about the low bits of the result.
3137 However, on most machines (those with BYTE_LOADS_ZERO_EXTEND
3138 not defined), we cannot perform a narrower operation that
3139 requested since the high-order bits will be undefined. On
3140 machine where BYTE_LOADS_ZERO_EXTEND are defined, however, this
3141 transformation is safe as long as M1 and M2 have the same number
3144 if (GET_CODE (SET_SRC (x
)) == SUBREG
3145 && subreg_lowpart_p (SET_SRC (x
))
3146 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) != 'o'
3147 && (((GET_MODE_SIZE (GET_MODE (SET_SRC (x
))) + (UNITS_PER_WORD
- 1))
3149 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x
))))
3150 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
3151 #ifndef BYTE_LOADS_ZERO_EXTEND
3152 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x
)))
3153 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x
)))))
3155 && (GET_CODE (SET_DEST (x
)) == REG
3156 || (GET_CODE (SET_DEST (x
)) == SUBREG
3157 && GET_CODE (SUBREG_REG (SET_DEST (x
))) == REG
)))
3159 /* Get the object that will be the SUBREG_REG of the
3160 SUBREG we are making. Note that SUBREG_WORD will always
3161 be zero because this will either be a paradoxical SUBREG
3162 or a SUBREG with the same number of words on the outside and
3164 rtx object
= (GET_CODE (SET_DEST (x
)) == REG
? SET_DEST (x
)
3165 : SUBREG_REG (SET_DEST (x
)));
3167 SUBST (SET_DEST (x
),
3168 gen_rtx (SUBREG
, GET_MODE (SUBREG_REG (SET_SRC (x
))),
3170 SUBST (SET_SRC (x
), SUBREG_REG (SET_SRC (x
)));
3173 /* If we are setting CC0 or if the source is a COMPARE, look for the
3174 use of the comparison result and try to simplify it unless we already
3175 have used undobuf.other_insn. */
3176 if ((GET_CODE (SET_SRC (x
)) == COMPARE
3178 || SET_DEST (x
) == cc0_rtx
3181 && (cc_use
= find_single_use (SET_DEST (x
), subst_insn
,
3183 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
3184 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
3185 && XEXP (*cc_use
, 0) == SET_DEST (x
))
3187 enum rtx_code old_code
= GET_CODE (*cc_use
);
3188 enum rtx_code new_code
;
3190 int other_changed
= 0;
3191 enum machine_mode compare_mode
= GET_MODE (SET_DEST (x
));
3193 if (GET_CODE (SET_SRC (x
)) == COMPARE
)
3194 op0
= XEXP (SET_SRC (x
), 0), op1
= XEXP (SET_SRC (x
), 1);
3196 op0
= SET_SRC (x
), op1
= const0_rtx
;
3198 /* Simplify our comparison, if possible. */
3199 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
3201 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
3202 /* If this machine has CC modes other than CCmode, check to see
3203 if we need to use a different CC mode here. */
3204 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
3206 /* If the mode changed, we have to change SET_DEST, the mode
3207 in the compare, and the mode in the place SET_DEST is used.
3208 If SET_DEST is a hard register, just build new versions with
3209 the proper mode. If it is a pseudo, we lose unless it is only
3210 time we set the pseudo, in which case we can safely change
3212 if (compare_mode
!= GET_MODE (SET_DEST (x
)))
3214 int regno
= REGNO (SET_DEST (x
));
3215 rtx new_dest
= gen_rtx (REG
, compare_mode
, regno
);
3217 if (regno
< FIRST_PSEUDO_REGISTER
3218 || (reg_n_sets
[regno
] == 1
3219 && ! REG_USERVAR_P (SET_DEST (x
))))
3221 if (regno
>= FIRST_PSEUDO_REGISTER
)
3222 SUBST (regno_reg_rtx
[regno
], new_dest
);
3224 SUBST (SET_DEST (x
), new_dest
);
3225 SUBST (XEXP (*cc_use
, 0), new_dest
);
3231 /* If the code changed, we have to build a new comparison
3232 in undobuf.other_insn. */
3233 if (new_code
!= old_code
)
3237 SUBST (*cc_use
, gen_rtx_combine (new_code
, GET_MODE (*cc_use
),
3238 SET_DEST (x
), const0_rtx
));
3240 /* If the only change we made was to change an EQ into an
3241 NE or vice versa, OP0 has only one significant bit,
3242 and OP1 is zero, check if changing the user of the condition
3243 code will produce a valid insn. If it won't, we can keep
3244 the original code in that insn by surrounding our operation
3247 if (((old_code
== NE
&& new_code
== EQ
)
3248 || (old_code
== EQ
&& new_code
== NE
))
3249 && ! other_changed
&& op1
== const0_rtx
3250 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_INT
3251 && (exact_log2 (mask
= significant_bits (op0
,
3255 rtx pat
= PATTERN (other_insn
), note
= 0;
3257 if ((recog_for_combine (&pat
, undobuf
.other_insn
, ¬e
) < 0
3258 && ! check_asm_operands (pat
)))
3260 PUT_CODE (*cc_use
, old_code
);
3263 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
,
3264 gen_rtx (CONST_INT
, VOIDmode
, mask
));
3272 undobuf
.other_insn
= other_insn
;
3275 /* If we are now comparing against zero, change our source if
3276 needed. If we do not use cc0, we always have a COMPARE. */
3277 if (op1
== const0_rtx
&& SET_DEST (x
) == cc0_rtx
)
3278 SUBST (SET_SRC (x
), op0
);
3282 /* Otherwise, if we didn't previously have a COMPARE in the
3283 correct mode, we need one. */
3284 if (GET_CODE (SET_SRC (x
)) != COMPARE
3285 || GET_MODE (SET_SRC (x
)) != compare_mode
)
3286 SUBST (SET_SRC (x
), gen_rtx_combine (COMPARE
, compare_mode
,
3290 /* Otherwise, update the COMPARE if needed. */
3291 SUBST (XEXP (SET_SRC (x
), 0), op0
);
3292 SUBST (XEXP (SET_SRC (x
), 1), op1
);
3297 /* Get SET_SRC in a form where we have placed back any
3298 compound expressions. Then do the checks below. */
3299 temp
= make_compound_operation (SET_SRC (x
), SET
);
3300 SUBST (SET_SRC (x
), temp
);
3303 #ifdef BYTE_LOADS_ZERO_EXTEND
3304 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with
3305 M wider than N, this would require a paradoxical subreg.
3306 Replace the subreg with a zero_extend to avoid the reload that
3307 would otherwise be required. */
3308 if (GET_CODE (SET_SRC (x
)) == SUBREG
3309 && subreg_lowpart_p (SET_SRC (x
))
3310 && SUBREG_WORD (SET_SRC (x
)) == 0
3311 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x
)))
3312 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x
)))))
3313 && GET_CODE (SUBREG_REG (SET_SRC (x
))) == MEM
)
3314 SUBST (SET_SRC (x
), gen_rtx_combine (ZERO_EXTEND
,
3315 GET_MODE (SET_SRC (x
)),
3316 XEXP (SET_SRC (x
), 0)));
3322 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3324 x
= simplify_and_const_int (x
, mode
, XEXP (x
, 0),
3325 INTVAL (XEXP (x
, 1)));
3327 /* If we have (ior (and (X C1) C2)) and the next restart would be
3328 the last, simplify this by making C1 as small as possible
3330 if (n_restarts
>= 3 && GET_CODE (x
) == IOR
3331 && GET_CODE (XEXP (x
, 0)) == AND
3332 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3333 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3335 temp
= gen_binary (AND
, mode
, XEXP (XEXP (x
, 0), 0),
3336 gen_rtx (CONST_INT
, VOIDmode
,
3337 (INTVAL (XEXP (XEXP (x
, 0), 1))
3338 & ~ INTVAL (XEXP (x
, 1)))));
3339 return gen_binary (IOR
, mode
, temp
, XEXP (x
, 1));
3342 if (GET_CODE (x
) != AND
)
3346 /* Convert (A | B) & A to A. */
3347 if (GET_CODE (XEXP (x
, 0)) == IOR
3348 && (rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1))
3349 || rtx_equal_p (XEXP (XEXP (x
, 0), 1), XEXP (x
, 1)))
3350 && ! side_effects_p (XEXP (XEXP (x
, 0), 0))
3351 && ! side_effects_p (XEXP (XEXP (x
, 0), 1)))
3354 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
3355 insn (and may simplify more). */
3356 else if (GET_CODE (XEXP (x
, 0)) == XOR
3357 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1))
3358 && ! side_effects_p (XEXP (x
, 1)))
3360 x
= gen_binary (AND
, mode
,
3361 gen_unary (NOT
, mode
, XEXP (XEXP (x
, 0), 1)),
3365 else if (GET_CODE (XEXP (x
, 0)) == XOR
3366 && rtx_equal_p (XEXP (XEXP (x
, 0), 1), XEXP (x
, 1))
3367 && ! side_effects_p (XEXP (x
, 1)))
3369 x
= gen_binary (AND
, mode
,
3370 gen_unary (NOT
, mode
, XEXP (XEXP (x
, 0), 0)),
3375 /* Similarly for (~ (A ^ B)) & A. */
3376 else if (GET_CODE (XEXP (x
, 0)) == NOT
3377 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == XOR
3378 && rtx_equal_p (XEXP (XEXP (XEXP (x
, 0), 0), 0), XEXP (x
, 1))
3379 && ! side_effects_p (XEXP (x
, 1)))
3381 x
= gen_binary (AND
, mode
, XEXP (XEXP (XEXP (x
, 0), 0), 1),
3385 else if (GET_CODE (XEXP (x
, 0)) == NOT
3386 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == XOR
3387 && rtx_equal_p (XEXP (XEXP (XEXP (x
, 0), 0), 1), XEXP (x
, 1))
3388 && ! side_effects_p (XEXP (x
, 1)))
3390 x
= gen_binary (AND
, mode
, XEXP (XEXP (XEXP (x
, 0), 0), 0),
3395 /* In the follow group of tests (and those in case IOR below),
3396 we start with some combination of logical operations and apply
3397 the distributive law followed by the inverse distributive law.
3398 Most of the time, this results in no change. However, if some of
3399 the operands are the same or inverses of each other, simplifications
3402 For example, (and (ior A B) (not B)) can occur as the result of
3403 expanding a bit field assignment. When we apply the distributive
3404 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
3405 which then simplifies to (and (A (not B))). */
3407 /* If we have (and (ior A B) C), apply the distributive law and then
3408 the inverse distributive law to see if things simplify. */
3410 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == XOR
)
3412 x
= apply_distributive_law
3413 (gen_binary (GET_CODE (XEXP (x
, 0)), mode
,
3414 gen_binary (AND
, mode
,
3415 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
3416 gen_binary (AND
, mode
,
3417 XEXP (XEXP (x
, 0), 1), XEXP (x
, 1))));
3418 if (GET_CODE (x
) != AND
)
3422 if (GET_CODE (XEXP (x
, 1)) == IOR
|| GET_CODE (XEXP (x
, 1)) == XOR
)
3424 x
= apply_distributive_law
3425 (gen_binary (GET_CODE (XEXP (x
, 1)), mode
,
3426 gen_binary (AND
, mode
,
3427 XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)),
3428 gen_binary (AND
, mode
,
3429 XEXP (XEXP (x
, 1), 1), XEXP (x
, 0))));
3430 if (GET_CODE (x
) != AND
)
3434 /* Similarly, taking advantage of the fact that
3435 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
3437 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == XOR
)
3439 x
= apply_distributive_law
3440 (gen_binary (XOR
, mode
,
3441 gen_binary (IOR
, mode
, XEXP (XEXP (x
, 0), 0),
3442 XEXP (XEXP (x
, 1), 0)),
3443 gen_binary (IOR
, mode
, XEXP (XEXP (x
, 0), 0),
3444 XEXP (XEXP (x
, 1), 1))));
3445 if (GET_CODE (x
) != AND
)
3449 else if (GET_CODE (XEXP (x
, 1)) == NOT
&& GET_CODE (XEXP (x
, 0)) == XOR
)
3451 x
= apply_distributive_law
3452 (gen_binary (XOR
, mode
,
3453 gen_binary (IOR
, mode
, XEXP (XEXP (x
, 1), 0),
3454 XEXP (XEXP (x
, 0), 0)),
3455 gen_binary (IOR
, mode
, XEXP (XEXP (x
, 1), 0),
3456 XEXP (XEXP (x
, 0), 1))));
3457 if (GET_CODE (x
) != AND
)
3463 /* Convert (A & B) | A to A. */
3464 if (GET_CODE (XEXP (x
, 0)) == AND
3465 && (rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1))
3466 || rtx_equal_p (XEXP (XEXP (x
, 0), 1), XEXP (x
, 1)))
3467 && ! side_effects_p (XEXP (XEXP (x
, 0), 0))
3468 && ! side_effects_p (XEXP (XEXP (x
, 0), 1)))
3471 /* If we have (ior (and A B) C), apply the distributive law and then
3472 the inverse distributive law to see if things simplify. */
3474 if (GET_CODE (XEXP (x
, 0)) == AND
)
3476 x
= apply_distributive_law
3477 (gen_binary (AND
, mode
,
3478 gen_binary (IOR
, mode
,
3479 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
3480 gen_binary (IOR
, mode
,
3481 XEXP (XEXP (x
, 0), 1), XEXP (x
, 1))));
3483 if (GET_CODE (x
) != IOR
)
3487 if (GET_CODE (XEXP (x
, 1)) == AND
)
3489 x
= apply_distributive_law
3490 (gen_binary (AND
, mode
,
3491 gen_binary (IOR
, mode
,
3492 XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)),
3493 gen_binary (IOR
, mode
,
3494 XEXP (XEXP (x
, 1), 1), XEXP (x
, 0))));
3496 if (GET_CODE (x
) != IOR
)
3500 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
3501 mode size to (rotate A CX). */
3503 if (((GET_CODE (XEXP (x
, 0)) == ASHIFT
3504 && GET_CODE (XEXP (x
, 1)) == LSHIFTRT
)
3505 || (GET_CODE (XEXP (x
, 1)) == ASHIFT
3506 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
))
3507 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (XEXP (x
, 1), 0))
3508 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3509 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
3510 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + INTVAL (XEXP (XEXP (x
, 1), 1))
3511 == GET_MODE_BITSIZE (mode
)))
3515 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
3516 shift_count
= XEXP (XEXP (x
, 0), 1);
3518 shift_count
= XEXP (XEXP (x
, 1), 1);
3519 x
= gen_rtx (ROTATE
, mode
, XEXP (XEXP (x
, 0), 0), shift_count
);
3525 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
3526 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
3529 int num_negated
= 0;
3530 rtx in1
= XEXP (x
, 0), in2
= XEXP (x
, 1);
3532 if (GET_CODE (in1
) == NOT
)
3533 num_negated
++, in1
= XEXP (in1
, 0);
3534 if (GET_CODE (in2
) == NOT
)
3535 num_negated
++, in2
= XEXP (in2
, 0);
3537 if (num_negated
== 2)
3539 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3540 SUBST (XEXP (x
, 1), XEXP (XEXP (x
, 1), 0));
3542 else if (num_negated
== 1)
3543 return gen_rtx_combine (NOT
, mode
,
3544 gen_rtx_combine (XOR
, mode
, in1
, in2
));
3547 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
3548 correspond to a machine insn or result in further simplifications
3549 if B is a constant. */
3551 if (GET_CODE (XEXP (x
, 0)) == AND
3552 && rtx_equal_p (XEXP (XEXP (x
, 0), 1), XEXP (x
, 1))
3553 && ! side_effects_p (XEXP (x
, 1)))
3555 x
= gen_binary (AND
, mode
,
3556 gen_unary (NOT
, mode
, XEXP (XEXP (x
, 0), 0)),
3560 else if (GET_CODE (XEXP (x
, 0)) == AND
3561 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1))
3562 && ! side_effects_p (XEXP (x
, 1)))
3564 x
= gen_binary (AND
, mode
,
3565 gen_unary (NOT
, mode
, XEXP (XEXP (x
, 0), 1)),
3571 #if STORE_FLAG_VALUE == 1
3572 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
3574 if (XEXP (x
, 1) == const1_rtx
3575 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3576 && reversible_comparison_p (XEXP (x
, 0)))
3577 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x
, 0))),
3578 mode
, XEXP (XEXP (x
, 0), 0),
3579 XEXP (XEXP (x
, 0), 1));
3582 /* (xor (comparison foo bar) (const_int sign-bit))
3583 when STORE_FLAG_VALUE is the sign bit. */
3584 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_INT
3585 && STORE_FLAG_VALUE
== 1 << (GET_MODE_BITSIZE (mode
) - 1)
3586 && XEXP (x
, 1) == const_true_rtx
3587 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3588 && reversible_comparison_p (XEXP (x
, 0)))
3589 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x
, 0))),
3590 mode
, XEXP (XEXP (x
, 0), 0),
3591 XEXP (XEXP (x
, 0), 1));
3595 /* (abs (neg <foo>)) -> (abs <foo>) */
3596 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3597 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3599 /* If operand is something known to be positive, ignore the ABS. */
3600 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
3601 || (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) <= HOST_BITS_PER_INT
3602 && ((significant_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
3603 & (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
3608 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
3609 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTRACT
3610 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3611 || (GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3612 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3613 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3614 || ((temp
= get_last_value (XEXP (x
, 0))) != 0
3615 && ((GET_CODE (temp
) == SIGN_EXTRACT
3616 && XEXP (temp
, 1) == const1_rtx
)
3617 || (GET_CODE (temp
) == ASHIFTRT
3618 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3619 && (INTVAL (XEXP (temp
, 1))
3620 == GET_MODE_BITSIZE (mode
) - 1)))))
3622 x
= gen_rtx_combine (NEG
, mode
, XEXP (x
, 0));
3628 /* (ffs (*_extend <X>)) = (ffs <X>) */
3629 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3630 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3631 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3635 /* (float (sign_extend <X>)) = (float <X>). */
3636 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
3637 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3646 /* If this is a shift by a constant amount, simplify it. */
3647 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3649 x
= simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
3650 INTVAL (XEXP (x
, 1)));
3651 if (GET_CODE (x
) != code
)
3655 #ifdef SHIFT_COUNT_TRUNCATED
3656 else if (GET_CODE (XEXP (x
, 1)) != REG
)
3658 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
3659 exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))),
3669 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
3670 operations" because they can be replaced with two more basic operations.
3671 ZERO_EXTEND is also considered "compound" because it can be replaced with
3672 an AND operation, which is simpler, though only one operation.
3674 The function expand_compound_operation is called with an rtx expression
3675 and will convert it to the appropriate shifts and AND operations,
3676 simplifying at each stage.
3678 The function make_compound_operation is called to convert an expression
3679 consisting of shifts and ANDs into the equivalent compound expression.
3680 It is the inverse of this function, loosely speaking. */
3683 expand_compound_operation (x
)
3691 switch (GET_CODE (x
))
3696 /* We can't necessarily use a const_int for a multiword mode;
3697 it depends on implicitly extending the value.
3698 Since we don't know the right way to extend it,
3699 we can't tell whether the implicit way is right.
3701 Even for a mode that is no wider than a const_int,
3702 we can't win, because we need to sign extend one of its bits through
3703 the rest of it, and we don't know which bit. */
3704 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
3707 if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x
, 0)), XEXP (x
, 0)))
3710 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
3711 /* If the inner object has VOIDmode (the only way this can happen
3712 is if it is a ASM_OPERANDS), we can't do anything since we don't
3713 know how much masking to do. */
3722 /* If the operand is a CLOBBER, just return it. */
3723 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
3726 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
3727 || GET_CODE (XEXP (x
, 2)) != CONST_INT
3728 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
3731 len
= INTVAL (XEXP (x
, 1));
3732 pos
= INTVAL (XEXP (x
, 2));
3734 /* If this goes outside the object being extracted, replace the object
3735 with a (use (mem ...)) construct that only combine understands
3736 and is used only for this purpose. */
3737 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
3738 SUBST (XEXP (x
, 0), gen_rtx (USE
, GET_MODE (x
), XEXP (x
, 0)));
3741 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
3749 /* If we reach here, we want to return a pair of shifts. The inner
3750 shift is a left shift of BITSIZE - POS - LEN bits. The outer
3751 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
3752 logical depending on the value of UNSIGNEDP.
3754 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
3755 converted into an AND of a shift.
3757 We must check for the case where the left shift would have a negative
3758 count. This can happen in a case like (x >> 31) & 255 on machines
3759 that can't shift by a constant. On those machines, we would first
3760 combine the shift with the AND to produce a variable-position
3761 extraction. Then the constant of 31 would be substituted in to produce
3762 a such a position. */
3764 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
3765 if (modewidth
>= pos
- len
)
3766 tem
= simplify_shift_const (0, unsignedp
? LSHIFTRT
: ASHIFTRT
,
3768 simplify_shift_const (0, ASHIFT
, GET_MODE (x
),
3770 modewidth
- pos
- len
),
3773 else if (unsignedp
&& len
< HOST_BITS_PER_INT
)
3774 tem
= simplify_and_const_int (0, GET_MODE (x
),
3775 simplify_shift_const (0, LSHIFTRT
,
3780 /* Any other cases we can't handle. */
3784 /* If we couldn't do this for some reason, return the original
3786 if (GET_CODE (tem
) == CLOBBER
)
3792 /* X is a SET which contains an assignment of one object into
3793 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
3794 or certain SUBREGS). If possible, convert it into a series of
3797 We half-heartedly support variable positions, but do not at all
3798 support variable lengths. */
3801 expand_field_assignment (x
)
3805 rtx pos
; /* Always counts from low bit. */
3808 enum machine_mode compute_mode
;
3810 /* Loop until we find something we can't simplify. */
3813 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
3814 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
3816 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
3817 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
3820 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3821 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
3823 inner
= XEXP (SET_DEST (x
), 0);
3824 len
= INTVAL (XEXP (SET_DEST (x
), 1));
3825 pos
= XEXP (SET_DEST (x
), 2);
3827 /* If the position is constant and spans the width of INNER,
3828 surround INNER with a USE to indicate this. */
3829 if (GET_CODE (pos
) == CONST_INT
3830 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
3831 inner
= gen_rtx (USE
, GET_MODE (SET_DEST (x
)), inner
);
3834 if (GET_CODE (pos
) == CONST_INT
)
3835 pos
= gen_rtx (CONST_INT
, VOIDmode
,
3836 (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
3838 else if (GET_CODE (pos
) == MINUS
3839 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
3840 && (INTVAL (XEXP (pos
, 1))
3841 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
3842 /* If position is ADJUST - X, new position is X. */
3843 pos
= XEXP (pos
, 0);
3845 pos
= gen_binary (MINUS
, GET_MODE (pos
),
3846 gen_rtx (CONST_INT
, VOIDmode
,
3847 (GET_MODE_BITSIZE (GET_MODE (inner
))
3852 /* A SUBREG between two modes that occupy the same numbers of words
3853 can be done by moving the SUBREG to the source. */
3854 else if (GET_CODE (SET_DEST (x
)) == SUBREG
3855 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
3856 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
3857 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
3858 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
3860 x
= gen_rtx (SET
, VOIDmode
, SUBREG_REG (SET_DEST (x
)),
3861 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x
))),
3868 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
3869 inner
= SUBREG_REG (inner
);
3871 compute_mode
= GET_MODE (inner
);
3873 /* Compute a mask of LEN bits, if we can do this on the host machine. */
3874 if (len
< HOST_BITS_PER_INT
)
3875 mask
= gen_rtx (CONST_INT
, VOIDmode
, (1 << len
) - 1);
3879 /* Now compute the equivalent expression. Make a copy of INNER
3880 for the SET_DEST in case it is a MEM into which we will substitute;
3881 we don't want shared RTL in that case. */
3882 x
= gen_rtx (SET
, VOIDmode
, copy_rtx (inner
),
3883 gen_binary (IOR
, compute_mode
,
3884 gen_binary (AND
, compute_mode
,
3885 gen_unary (NOT
, compute_mode
,
3890 gen_binary (ASHIFT
, compute_mode
,
3891 gen_binary (AND
, compute_mode
,
3892 gen_lowpart_for_combine
3902 /* Return an RTX for a reference to LEN bits of INNER. POS is the starting
3903 bit position (counted from the LSB) if >= 0; otherwise POS_RTX represents
3904 the starting bit position.
3906 INNER may be a USE. This will occur when we started with a bitfield
3907 that went outside the boundary of the object in memory, which is
3908 allowed on most machines. To isolate this case, we produce a USE
3909 whose mode is wide enough and surround the MEM with it. The only
3910 code that understands the USE is this routine. If it is not removed,
3911 it will cause the resulting insn not to match.
3913 UNSIGNEDP is non-zero for an unsigned reference and zero for a
3916 IN_DEST is non-zero if this is a reference in the destination of a
3917 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
3918 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
3921 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
3922 ZERO_EXTRACT should be built even for bits starting at bit 0.
3924 MODE is the desired mode of the result (if IN_DEST == 0). */
3927 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
3928 unsignedp
, in_dest
, in_compare
)
3929 enum machine_mode mode
;
3935 int in_dest
, in_compare
;
3937 enum machine_mode is_mode
= GET_MODE (inner
);
3938 enum machine_mode inner_mode
;
3939 enum machine_mode wanted_mem_mode
= byte_mode
;
3940 enum machine_mode pos_mode
= word_mode
;
3941 enum machine_mode extraction_mode
= word_mode
;
3942 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
3946 /* Get some information about INNER and get the innermost object. */
3947 if (GET_CODE (inner
) == USE
)
3948 /* We don't need to adjust the position because we set up the USE
3949 to pretend that it was a full-word object. */
3950 spans_byte
= 1, inner
= XEXP (inner
, 0);
3951 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
3952 inner
= SUBREG_REG (inner
);
3954 inner_mode
= GET_MODE (inner
);
3956 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
3957 pos
= INTVAL (pos_rtx
);
3959 /* See if this can be done without an extraction. We never can if the
3960 width of the field is not the same as that of some integer mode. For
3961 registers, we can only avoid the extraction if the position is at the
3962 low-order bit and this is either not in the destination or we have the
3963 appropriate STRICT_LOW_PART operation available.
3965 For MEM, we can avoid an extract if the field starts on an appropriate
3966 boundary and we can change the mode of the memory reference. However,
3967 we cannot directly access the MEM if we have a USE and the underlying
3968 MEM is not TMODE. This combination means that MEM was being used in a
3969 context where bits outside its mode were being referenced; that is only
3970 valid in bit-field insns. */
3972 if (tmode
!= BLKmode
3973 && ! (spans_byte
&& inner_mode
!= tmode
)
3974 && ((pos
== 0 && GET_CODE (inner
) == REG
3976 || (movstrict_optab
->handlers
[(int) tmode
].insn_code
3977 != CODE_FOR_nothing
)))
3978 || (GET_CODE (inner
) == MEM
&& pos
>= 0
3980 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
3981 : BITS_PER_UNIT
)) == 0
3982 /* We can't do this if we are widening INNER_MODE (it
3983 may not be aligned, for one thing). */
3984 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
3985 && (inner_mode
== tmode
3986 || (! mode_dependent_address_p (XEXP (inner
, 0))
3987 && ! MEM_VOLATILE_P (inner
))))))
3989 int offset
= pos
/ BITS_PER_UNIT
;
3991 /* If INNER is a MEM, make a new MEM that encompasses just the desired
3992 field. If the original and current mode are the same, we need not
3993 adjust the offset. Otherwise, we do if bytes big endian.
3995 If INNER is not a MEM, get a piece consisting of the just the field
3996 of interest (in this case INNER must be a REG and POS must be 0). */
3998 if (GET_CODE (inner
) == MEM
)
4000 #if BYTES_BIG_ENDIAN
4001 if (inner_mode
!= tmode
)
4002 offset
= (GET_MODE_SIZE (inner_mode
)
4003 - GET_MODE_SIZE (tmode
) - offset
);
4006 new = gen_rtx (MEM
, tmode
, plus_constant (XEXP (inner
, 0), offset
));
4007 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner
);
4008 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner
);
4009 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner
);
4011 else if (GET_MODE (inner
) == REG
)
4012 /* We can't call gen_lowpart_for_combine here since we always want
4013 a SUBREG and it would sometimes return a new hard register. */
4014 new = gen_rtx (SUBREG
, tmode
, inner
,
4016 && GET_MODE_SIZE (is_mode
) > UNITS_PER_WORD
)
4017 ? ((GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (tmode
)
4021 new = gen_lowpart_for_combine (tmode
, inner
);
4023 /* If this extraction is going into the destination of a SET,
4024 make a STRICT_LOW_PART unless we made a MEM. */
4027 return (GET_CODE (new) == MEM
? new
4028 : (GET_CODE (new) != SUBREG
4029 ? gen_rtx (CLOBBER
, tmode
, const0_rtx
)
4030 : gen_rtx_combine (STRICT_LOW_PART
, VOIDmode
, new)));
4032 /* Otherwise, sign- or zero-extend unless we already are in the
4035 return (mode
== tmode
? new
4036 : gen_rtx_combine (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
4040 /* Unless this is in a COMPARE or we have a funny memory reference,
4041 don't do anything with field extracts starting at the low-order
4042 bit since they are simple AND operations. */
4043 if (pos
== 0 && ! in_dest
&& ! in_compare
&& ! spans_byte
)
4046 /* Get the mode to use should INNER be a MEM, the mode for the position,
4047 and the mode for the result. */
4051 wanted_mem_mode
= insn_operand_mode
[(int) CODE_FOR_insv
][0];
4052 pos_mode
= insn_operand_mode
[(int) CODE_FOR_insv
][2];
4053 extraction_mode
= insn_operand_mode
[(int) CODE_FOR_insv
][3];
4058 if (! in_dest
&& unsignedp
)
4060 wanted_mem_mode
= insn_operand_mode
[(int) CODE_FOR_extzv
][1];
4061 pos_mode
= insn_operand_mode
[(int) CODE_FOR_extzv
][3];
4062 extraction_mode
= insn_operand_mode
[(int) CODE_FOR_extzv
][0];
4067 if (! in_dest
&& ! unsignedp
)
4069 wanted_mem_mode
= insn_operand_mode
[(int) CODE_FOR_extv
][1];
4070 pos_mode
= insn_operand_mode
[(int) CODE_FOR_extv
][3];
4071 extraction_mode
= insn_operand_mode
[(int) CODE_FOR_extv
][0];
4075 /* Never narrow an object, since that might not be safe. */
4077 if (mode
!= VOIDmode
4078 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
4079 extraction_mode
= mode
;
4081 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
4082 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
4083 pos_mode
= GET_MODE (pos_rtx
);
4085 /* If this is not from memory or we have to change the mode of memory and
4086 cannot, the desired mode is EXTRACTION_MODE. */
4087 if (GET_CODE (inner
) != MEM
4088 || (inner_mode
!= wanted_mem_mode
4089 && (mode_dependent_address_p (XEXP (inner
, 0))
4090 || MEM_VOLATILE_P (inner
))))
4091 wanted_mem_mode
= extraction_mode
;
4094 /* If position is constant, compute new position. Otherwise, build
4097 pos
= (MAX (GET_MODE_BITSIZE (is_mode
), GET_MODE_BITSIZE (wanted_mem_mode
))
4101 = gen_rtx_combine (MINUS
, GET_MODE (pos_rtx
),
4102 gen_rtx (CONST_INT
, VOIDmode
,
4103 (MAX (GET_MODE_BITSIZE (is_mode
),
4104 GET_MODE_BITSIZE (wanted_mem_mode
))
4108 /* If INNER has a wider mode, make it smaller. If this is a constant
4109 extract, try to adjust the byte to point to the byte containing
4111 if (wanted_mem_mode
!= VOIDmode
4112 && GET_MODE_SIZE (wanted_mem_mode
) < GET_MODE_SIZE (is_mode
)
4113 && ((GET_CODE (inner
) == MEM
4114 && (inner_mode
== wanted_mem_mode
4115 || (! mode_dependent_address_p (XEXP (inner
, 0))
4116 && ! MEM_VOLATILE_P (inner
))))))
4120 /* The computations below will be correct if the machine is big
4121 endian in both bits and bytes or little endian in bits and bytes.
4122 If it is mixed, we must adjust. */
4124 #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
4125 if (! spans_byte
&& is_mode
!= wanted_mem_mode
)
4126 offset
= (GET_MODE_SIZE (is_mode
)
4127 - GET_MODE_SIZE (wanted_mem_mode
) - offset
);
4130 /* If bytes are big endian and we had a paradoxical SUBREG, we must
4131 adjust OFFSET to compensate. */
4132 #if BYTES_BIG_ENDIAN
4134 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
4135 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
4138 /* If this is a constant position, we can move to the desired byte. */
4141 offset
+= pos
/ BITS_PER_UNIT
;
4142 pos
%= GET_MODE_BITSIZE (wanted_mem_mode
);
4145 if (offset
!= 0 || inner_mode
!= wanted_mem_mode
)
4147 rtx newmem
= gen_rtx (MEM
, wanted_mem_mode
,
4148 plus_constant (XEXP (inner
, 0), offset
));
4149 RTX_UNCHANGING_P (newmem
) = RTX_UNCHANGING_P (inner
);
4150 MEM_VOLATILE_P (newmem
) = MEM_VOLATILE_P (inner
);
4151 MEM_IN_STRUCT_P (newmem
) = MEM_IN_STRUCT_P (inner
);
4156 /* If INNER is not memory, we can always get it into the proper mode. */
4157 else if (GET_CODE (inner
) != MEM
)
4158 inner
= gen_lowpart_for_combine (extraction_mode
, inner
);
4160 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
4161 have to zero extend. Otherwise, we can just use a SUBREG. */
4163 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
4164 pos_rtx
= gen_rtx_combine (ZERO_EXTEND
, pos_mode
, pos_rtx
);
4166 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
4167 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
4169 /* Make POS_RTX unless we already have it and it is correct. */
4170 if (pos_rtx
== 0 || (pos
>= 0 && INTVAL (pos_rtx
) != pos
))
4171 pos_rtx
= gen_rtx (CONST_INT
, VOIDmode
, pos
);
4173 /* Make the required operation. See if we can use existing rtx. */
4174 new = gen_rtx_combine (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
4175 extraction_mode
, inner
,
4176 gen_rtx (CONST_INT
, VOIDmode
, len
), pos_rtx
);
4178 new = gen_lowpart_for_combine (mode
, new);
4183 /* Look at the expression rooted at X. Look for expressions
4184 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
4185 Form these expressions.
4187 Return the new rtx, usually just X.
4189 Also, for machines like the Vax that don't have logical shift insns,
4190 try to convert logical to arithmetic shift operations in cases where
4191 they are equivalent. This undoes the canonicalizations to logical
4192 shifts done elsewhere.
4194 We try, as much as possible, to re-use rtl expressions to save memory.
4196 IN_CODE says what kind of expression we are processing. Normally, it is
4197 SET. In a memory address (inside a MEM or PLUS, the latter being a
4198 kludge), it is MEM. When processing the arguments of a comparison
4199 or a COMPARE against zero, it is COMPARE. */
4202 make_compound_operation (x
, in_code
)
4204 enum rtx_code in_code
;
4206 enum rtx_code code
= GET_CODE (x
);
4207 enum machine_mode mode
= GET_MODE (x
);
4208 int mode_width
= GET_MODE_BITSIZE (mode
);
4209 enum rtx_code next_code
;
4214 /* Select the code to be used in recursive calls. Once we are inside an
4215 address, we stay there. If we have a comparison, set to COMPARE,
4216 but once inside, go back to our default of SET. */
4218 next_code
= (code
== MEM
|| code
== PLUS
? MEM
4219 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
4220 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
4221 : in_code
== COMPARE
? SET
: in_code
);
4223 /* Process depending on the code of this operation. If NEW is set
4224 non-zero, it will be returned. */
4230 /* Convert shifts by constants into multiplications if inside
4232 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
4233 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_INT
4234 && INTVAL (XEXP (x
, 1)) >= 0)
4235 new = gen_rtx_combine (MULT
, mode
, XEXP (x
, 0),
4236 gen_rtx (CONST_INT
, VOIDmode
,
4237 1 << INTVAL (XEXP (x
, 1))));
4241 /* If the second operand is not a constant, we can't do anything
4243 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4246 /* If the constant is a power of two minus one and the first operand
4247 is a logical right shift, make an extraction. */
4248 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4249 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
4250 new = make_extraction (mode
, XEXP (XEXP (x
, 0), 0), -1,
4251 XEXP (XEXP (x
, 0), 1), i
, 1,
4252 0, in_code
== COMPARE
);
4254 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
4255 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
4256 && subreg_lowpart_p (XEXP (x
, 0))
4257 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
4258 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
4259 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))),
4260 XEXP (SUBREG_REG (XEXP (x
, 0)), 0), -1,
4261 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
4262 0, in_code
== COMPARE
);
4265 /* If we are have (and (rotate X C) M) and C is larger than the number
4266 of bits in M, this is an extraction. */
4268 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
4269 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4270 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
4271 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
4272 new = make_extraction (mode
, XEXP (XEXP (x
, 0), 0),
4273 (GET_MODE_BITSIZE (mode
)
4274 - INTVAL (XEXP (XEXP (x
, 0), 1))),
4275 0, i
, 1, 0, in_code
== COMPARE
);
4277 /* On machines without logical shifts, if the operand of the AND is
4278 a logical shift and our mask turns off all the propagated sign
4279 bits, we can replace the logical shift with an arithmetic shift. */
4291 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4292 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4293 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
4294 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_INT
4295 && mode_width
<= HOST_BITS_PER_INT
)
4297 unsigned mask
= GET_MODE_MASK (mode
);
4299 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
4300 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
4302 gen_rtx_combine (ASHIFTRT
, mode
, XEXP (XEXP (x
, 0), 0),
4303 XEXP (XEXP (x
, 0), 1)));
4306 /* If the constant is one less than a power of two, this might be
4307 representable by an extraction even if no shift is present.
4308 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
4309 we are in a COMPARE. */
4310 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
4311 new = make_extraction (mode
, XEXP (x
, 0), 0, 0, i
, 1,
4312 0, in_code
== COMPARE
);
4314 /* If we are in a comparison and this is an AND with a power of two,
4315 convert this into the appropriate bit extract. */
4316 else if (in_code
== COMPARE
4317 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4318 new = make_extraction (mode
, XEXP (x
, 0), i
, 0, 1, 1, 0, 1);
4323 /* If the sign bit is known to be zero, replace this with an
4324 arithmetic shift. */
4336 && mode_width
<= HOST_BITS_PER_INT
4337 && (significant_bits (XEXP (x
, 0), mode
)
4338 & (1 << (mode_width
- 1))) == 0)
4340 new = gen_rtx_combine (ASHIFTRT
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4344 /* ... fall through ... */
4347 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
4348 this is a SIGN_EXTRACT. */
4349 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4350 && GET_CODE (XEXP (x
, 0)) == ASHIFT
4351 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4352 && INTVAL (XEXP (x
, 1)) >= INTVAL (XEXP (XEXP (x
, 0), 1)))
4353 new = make_extraction (mode
, XEXP (XEXP (x
, 0), 0),
4354 (INTVAL (XEXP (x
, 1))
4355 - INTVAL (XEXP (XEXP (x
, 0), 1))),
4356 0, mode_width
- INTVAL (XEXP (x
, 1)),
4357 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
4364 code
= GET_CODE (x
);
4367 /* Now recursively process each operand of this operation. */
4368 fmt
= GET_RTX_FORMAT (code
);
4369 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
4372 new = make_compound_operation (XEXP (x
, i
), next_code
);
4373 SUBST (XEXP (x
, i
), new);
4379 /* Given M see if it is a value that would select a field of bits
4380 within an item, but not the entire word. Return -1 if not.
4381 Otherwise, return the starting position of the field, where 0 is the
4384 *PLEN is set to the length of the field. */
4387 get_pos_from_mask (m
, plen
)
4391 /* Get the bit number of the first 1 bit from the right, -1 if none. */
4392 int pos
= exact_log2 (m
& - m
);
4397 /* Now shift off the low-order zero bits and see if we have a power of
4399 *plen
= exact_log2 ((m
>> pos
) + 1);
4407 /* Rewrite X so that it is an expression in MODE. We only care about the
4408 low-order BITS bits so we can ignore AND operations that just clear
4411 Also, if REG is non-zero and X is a register equal in value to REG,
4412 replace X with REG. */
4415 force_to_mode (x
, mode
, bits
, reg
)
4417 enum machine_mode mode
;
4421 enum rtx_code code
= GET_CODE (x
);
4423 /* If X is narrower than MODE or if BITS is larger than the size of MODE,
4424 just get X in the proper mode. */
4426 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
4427 || bits
> GET_MODE_BITSIZE (mode
))
4428 return gen_lowpart_for_combine (mode
, x
);
4436 x
= expand_compound_operation (x
);
4437 if (GET_CODE (x
) != code
)
4438 return force_to_mode (x
, mode
, bits
, reg
);
4442 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
4443 || rtx_equal_p (reg
, get_last_value (x
))))
4448 if (bits
< HOST_BITS_PER_INT
)
4449 x
= gen_rtx (CONST_INT
, VOIDmode
, INTVAL (x
) & ((1 << bits
) - 1));
4453 /* Ignore low-order SUBREGs. */
4454 if (subreg_lowpart_p (x
))
4455 return force_to_mode (SUBREG_REG (x
), mode
, bits
, reg
);
4459 /* If this is an AND with a constant. Otherwise, we fall through to
4460 do the general binary case. */
4462 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4464 int mask
= INTVAL (XEXP (x
, 1));
4465 int len
= exact_log2 (mask
+ 1);
4466 rtx op
= XEXP (x
, 0);
4468 /* If this is masking some low-order bits, we may be able to
4469 impose a stricter constraint on what bits of the operand are
4472 op
= force_to_mode (op
, mode
, len
> 0 ? MIN (len
, bits
) : bits
,
4475 if (bits
< HOST_BITS_PER_INT
)
4476 mask
&= (1 << bits
) - 1;
4478 x
= simplify_and_const_int (x
, mode
, op
, mask
);
4480 /* If X is still an AND, see if it is an AND with a mask that
4481 is just some low-order bits. If so, and it is BITS wide (it
4482 can't be wider), we don't need it. */
4484 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
4485 && bits
< HOST_BITS_PER_INT
4486 && INTVAL (XEXP (x
, 1)) == (1 << bits
) - 1)
4491 /* ... fall through ... */
4498 /* For most binary operations, just propagate into the operation and
4501 return gen_binary (code
, mode
,
4502 force_to_mode (XEXP (x
, 0), mode
, bits
, reg
),
4503 force_to_mode (XEXP (x
, 1), mode
, bits
, reg
));
4507 /* For left shifts, do the same, but just for the first operand.
4508 If the shift count is a constant, we need even fewer bits of the
4511 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) < bits
)
4512 bits
-= INTVAL (XEXP (x
, 1));
4514 return gen_binary (code
, mode
,
4515 force_to_mode (XEXP (x
, 0), mode
, bits
, reg
),
4519 /* Here we can only do something if the shift count is a constant and
4520 the count plus BITS is no larger than the width of MODE, we can do
4521 the shift in MODE. */
4523 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4524 && INTVAL (XEXP (x
, 1)) + bits
<= GET_MODE_BITSIZE (mode
))
4525 return gen_binary (LSHIFTRT
, mode
,
4526 force_to_mode (XEXP (x
, 0), mode
,
4527 bits
+ INTVAL (XEXP (x
, 1)), reg
),
4533 /* Handle these similarly to the way we handle most binary operations. */
4534 return gen_unary (code
, mode
,
4535 force_to_mode (XEXP (x
, 0), mode
, bits
, reg
));
4538 /* Otherwise, just do the operation canonically. */
4539 return gen_lowpart_for_combine (mode
, x
);
4542 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
4543 Return that assignment if so.
4545 We only handle the most common cases. */
4548 make_field_assignment (x
)
4551 rtx dest
= SET_DEST (x
);
4552 rtx src
= SET_SRC (x
);
4557 enum machine_mode mode
;
4559 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
4560 a clear of a one-bit field. We will have changed it to
4561 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
4564 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
4565 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
4566 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
4567 && (rtx_equal_p (dest
, XEXP (src
, 1))
4568 || rtx_equal_p (dest
, get_last_value (XEXP (src
, 1)))
4569 || rtx_equal_p (get_last_value (dest
), XEXP (src
, 1))))
4571 assign
= make_extraction (VOIDmode
, dest
, -1, XEXP (XEXP (src
, 0), 1),
4573 return gen_rtx (SET
, VOIDmode
, assign
, const0_rtx
);
4576 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
4577 && subreg_lowpart_p (XEXP (src
, 0))
4578 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
4579 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
4580 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
4581 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
4582 && (rtx_equal_p (dest
, XEXP (src
, 1))
4583 || rtx_equal_p (dest
, get_last_value (XEXP (src
, 1)))
4584 || rtx_equal_p (get_last_value (dest
), XEXP (src
, 1))))
4586 assign
= make_extraction (VOIDmode
, dest
, -1,
4587 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
4589 return gen_rtx (SET
, VOIDmode
, assign
, const0_rtx
);
4592 /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
4594 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
4595 && XEXP (XEXP (src
, 0), 0) == const1_rtx
4596 && (rtx_equal_p (dest
, XEXP (src
, 1))
4597 || rtx_equal_p (dest
, get_last_value (XEXP (src
, 1)))
4598 || rtx_equal_p (get_last_value (dest
), XEXP (src
, 1))))
4600 assign
= make_extraction (VOIDmode
, dest
, -1, XEXP (XEXP (src
, 0), 1),
4602 return gen_rtx (SET
, VOIDmode
, assign
, const1_rtx
);
4605 /* The other case we handle is assignments into a constant-position
4606 field. They look like (ior (and DEST C1) OTHER). If C1 represents
4607 a mask that has all one bits except for a group of zero bits and
4608 OTHER is known to have zeros where C1 has ones, this is such an
4609 assignment. Compute the position and length from C1. Shift OTHER
4610 to the appropriate position, force it to the required mode, and
4611 make the extraction. Check for the AND in both operands. */
4613 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == AND
4614 && GET_CODE (XEXP (XEXP (src
, 0), 1)) == CONST_INT
4615 && (rtx_equal_p (XEXP (XEXP (src
, 0), 0), dest
)
4616 || rtx_equal_p (XEXP (XEXP (src
, 0), 0), get_last_value (dest
))
4617 || rtx_equal_p (get_last_value (XEXP (XEXP (src
, 0), 1)), dest
)))
4618 c1
= INTVAL (XEXP (XEXP (src
, 0), 1)), other
= XEXP (src
, 1);
4619 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 1)) == AND
4620 && GET_CODE (XEXP (XEXP (src
, 1), 1)) == CONST_INT
4621 && (rtx_equal_p (XEXP (XEXP (src
, 1), 0), dest
)
4622 || rtx_equal_p (XEXP (XEXP (src
, 1), 0), get_last_value (dest
))
4623 || rtx_equal_p (get_last_value (XEXP (XEXP (src
, 1), 0)),
4625 c1
= INTVAL (XEXP (XEXP (src
, 1), 1)), other
= XEXP (src
, 0);
4629 pos
= get_pos_from_mask (~c1
, &len
);
4630 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
4631 || (c1
& significant_bits (other
, GET_MODE (other
))) != 0)
4634 assign
= make_extraction (VOIDmode
, dest
, pos
, 0, len
, 1, 1, 0);
4636 /* The mode to use for the source is the mode of the assignment, or of
4637 what is inside a possible STRICT_LOW_PART. */
4638 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
4639 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
4641 /* Shift OTHER right POS places and make it the source, restricting it
4642 to the proper length and mode. */
4644 src
= force_to_mode (simplify_shift_const (0, LSHIFTRT
, GET_MODE (src
),
4648 return gen_rtx_combine (SET
, VOIDmode
, assign
, src
);
4651 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
4655 apply_distributive_law (x
)
4658 enum rtx_code code
= GET_CODE (x
);
4659 rtx lhs
, rhs
, other
;
4661 enum rtx_code inner_code
;
4663 /* The outer operation can only be one of the following: */
4664 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
4665 && code
!= PLUS
&& code
!= MINUS
)
4668 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
4670 /* If either operand is a primitive we can't do anything, so get out fast. */
4671 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
4672 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
4675 lhs
= expand_compound_operation (lhs
);
4676 rhs
= expand_compound_operation (rhs
);
4677 inner_code
= GET_CODE (lhs
);
4678 if (inner_code
!= GET_CODE (rhs
))
4681 /* See if the inner and outer operations distribute. */
4688 /* These all distribute except over PLUS. */
4689 if (code
== PLUS
|| code
== MINUS
)
4694 if (code
!= PLUS
&& code
!= MINUS
)
4700 /* These are also multiplies, so they distribute over everything. */
4704 /* Non-paradoxical SUBREGs distributes over all operations, provided
4705 the inner modes and word numbers are the same, this is an extraction
4706 of a low-order part, we don't convert an fp operation to int or
4707 vice versa, and we would not be converting a single-word
4708 operation into a multi-word operation. The latter test is not
4709 required, but it prevents generating unneeded multi-word operations.
4710 Some of the previous tests are redundant given the latter test, but
4711 are retained because they are required for correctness.
4713 We produce the result slightly differently in this case. */
4715 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
4716 || SUBREG_WORD (lhs
) != SUBREG_WORD (rhs
)
4717 || ! subreg_lowpart_p (lhs
)
4718 || (GET_MODE_CLASS (GET_MODE (lhs
))
4719 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
4720 || (GET_MODE_SIZE (GET_MODE (lhs
))
4721 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
4722 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
4725 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
4726 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
4727 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
4733 /* Set LHS and RHS to the inner operands (A and B in the example
4734 above) and set OTHER to the common operand (C in the example).
4735 These is only one way to do this unless the inner operation is
4737 if (GET_RTX_CLASS (inner_code
) == 'c'
4738 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
4739 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
4740 else if (GET_RTX_CLASS (inner_code
) == 'c'
4741 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
4742 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
4743 else if (GET_RTX_CLASS (inner_code
) == 'c'
4744 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
4745 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
4746 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
4747 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
4751 /* Form the new inner operation, seeing if it simplifies first. */
4752 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
4754 /* There is one exception to the general way of distributing:
4755 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
4756 if (code
== XOR
&& inner_code
== IOR
)
4759 other
= gen_unary (NOT
, GET_MODE (x
), other
);
4762 /* We may be able to continuing distributing the result, so call
4763 ourselves recursively on the inner operation before forming the
4764 outer operation, which we return. */
4765 return gen_binary (inner_code
, GET_MODE (x
),
4766 apply_distributive_law (tem
), other
);
4769 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
4772 Return an equivalent form, if different from X. Otherwise, return X. If
4773 X is zero, we are to always construct the equivalent form. */
4776 simplify_and_const_int (x
, mode
, varop
, constop
)
4778 enum machine_mode mode
;
4782 register enum machine_mode tmode
;
4784 unsigned significant
;
4786 /* There is a large class of optimizations based on the principle that
4787 some operations produce results where certain bits are known to be zero,
4788 and hence are not significant to the AND. For example, if we have just
4789 done a left shift of one bit, the low-order bit is known to be zero and
4790 hence an AND with a mask of ~1 would not do anything.
4792 At the end of the following loop, we set:
4794 VAROP to be the item to be AND'ed with;
4795 CONSTOP to the constant value to AND it with. */
4799 /* If we ever encounter a mode wider than the host machine's word
4800 size, we can't compute the masks accurately, so give up. */
4801 if (GET_MODE_BITSIZE (GET_MODE (varop
)) > HOST_BITS_PER_INT
)
4804 /* Unless one of the cases below does a `continue',
4805 a `break' will be executed to exit the loop. */
4807 switch (GET_CODE (varop
))
4810 /* If VAROP is a (clobber (const_int)), return it since we know
4811 we are generating something that won't match. */
4814 #if ! BITS_BIG_ENDIAN
4816 /* VAROP is a (use (mem ..)) that was made from a bit-field
4817 extraction that spanned the boundary of the MEM. If we are
4818 now masking so it is within that boundary, we don't need the
4820 if ((constop
& ~ GET_MODE_MASK (GET_MODE (XEXP (varop
, 0)))) == 0)
4822 varop
= XEXP (varop
, 0);
4829 if (subreg_lowpart_p (varop
)
4830 /* We can ignore the effect this SUBREG if it narrows the mode
4831 or, on machines where byte operations zero extend, if the
4832 constant masks to zero all the bits the mode doesn't have. */
4833 && ((GET_MODE_SIZE (GET_MODE (varop
))
4834 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
))))
4835 #ifdef BYTE_LOADS_ZERO_EXTEND
4837 & GET_MODE_MASK (GET_MODE (varop
))
4838 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (varop
)))))
4842 varop
= SUBREG_REG (varop
);
4851 /* Try to expand these into a series of shifts and then work
4852 with that result. If we can't, for example, if the extract
4853 isn't at a fixed position, give up. */
4854 temp
= expand_compound_operation (varop
);
4863 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
)
4865 constop
&= INTVAL (XEXP (varop
, 1));
4866 varop
= XEXP (varop
, 0);
4873 /* If VAROP is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
4874 LSHIFT so we end up with an (and (lshiftrt (ior ...) ...) ...)
4875 operation which may be a bitfield extraction. */
4877 if (GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
4878 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
4879 && INTVAL (XEXP (XEXP (varop
, 0), 1)) >= 0
4880 && INTVAL (XEXP (XEXP (varop
, 0), 1)) < HOST_BITS_PER_INT
4881 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
4882 && (INTVAL (XEXP (varop
, 1))
4883 & ~ significant_bits (XEXP (varop
, 0),
4884 GET_MODE (varop
)) == 0))
4886 temp
= gen_rtx (CONST_INT
, VOIDmode
,
4887 ((INTVAL (XEXP (varop
, 1)) & constop
)
4888 << INTVAL (XEXP (XEXP (varop
, 0), 1))));
4889 temp
= gen_binary (GET_CODE (varop
), GET_MODE (varop
),
4890 XEXP (XEXP (varop
, 0), 0), temp
);
4891 varop
= gen_rtx_combine (LSHIFTRT
, GET_MODE (varop
),
4892 temp
, XEXP (varop
, 1));
4896 /* Apply the AND to both branches of the IOR or XOR, then try to
4897 apply the distributive law. This may eliminate operations
4898 if either branch can be simplified because of the AND.
4899 It may also make some cases more complex, but those cases
4900 probably won't match a pattern either with or without this. */
4902 gen_lowpart_for_combine
4903 (mode
, apply_distributive_law
4905 (GET_CODE (varop
), GET_MODE (varop
),
4906 simplify_and_const_int (0, GET_MODE (varop
),
4907 XEXP (varop
, 0), constop
),
4908 simplify_and_const_int (0, GET_MODE (varop
),
4909 XEXP (varop
, 1), constop
))));
4912 /* (and (not FOO)) is (and (xor FOO CONST_OP)) so if FOO is an
4913 LSHIFTRT we can do the same as above. */
4915 if (GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
4916 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
4917 && INTVAL (XEXP (XEXP (varop
, 0), 1)) >= 0
4918 && INTVAL (XEXP (XEXP (varop
, 0), 1)) < HOST_BITS_PER_INT
)
4920 temp
= gen_rtx (CONST_INT
, VOIDmode
,
4921 constop
<< INTVAL (XEXP (XEXP (varop
, 0), 1)));
4922 temp
= gen_binary (XOR
, GET_MODE (varop
),
4923 XEXP (XEXP (varop
, 0), 0), temp
);
4924 varop
= gen_rtx_combine (LSHIFTRT
, GET_MODE (varop
),
4925 temp
, XEXP (XEXP (varop
, 0), 1));
4931 /* If we are just looking for the sign bit, we don't need this
4932 shift at all, even if it has a variable count. */
4933 if (constop
== 1 << (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1))
4935 varop
= XEXP (varop
, 0);
4939 /* If this is a shift by a constant, get a mask that contains
4940 those bits that are not copies of the sign bit. We then have
4941 two cases: If CONSTOP only includes those bits, this can be
4942 a logical shift, which may allow simplifications. If CONSTOP
4943 is a single-bit field not within those bits, we are requesting
4944 a copy of the sign bit and hence can shift the sign bit to
4945 the appropriate location. */
4946 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
4947 && INTVAL (XEXP (varop
, 1)) >= 0
4948 && INTVAL (XEXP (varop
, 1)) < HOST_BITS_PER_INT
)
4952 significant
= GET_MODE_MASK (GET_MODE (varop
));
4953 significant
>>= INTVAL (XEXP (varop
, 1));
4955 if ((constop
& ~significant
) == 0
4956 || (i
= exact_log2 (constop
)) >= 0)
4958 varop
= simplify_shift_const
4959 (varop
, LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
4960 i
< 0 ? INTVAL (XEXP (varop
, 1))
4961 : GET_MODE_BITSIZE (GET_MODE (varop
)) - 1 - i
);
4962 if (GET_CODE (varop
) != ASHIFTRT
)
4967 /* If our mask is 1, convert this to a LSHIFTRT. This can be done
4968 even if the shift count isn't a constant. */
4970 varop
= gen_rtx_combine (LSHIFTRT
, GET_MODE (varop
),
4971 XEXP (varop
, 0), XEXP (varop
, 1));
4975 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is
4976 included in STORE_FLAG_VALUE and FOO has no significant bits
4978 if ((constop
& ~ STORE_FLAG_VALUE
) == 0
4979 && XEXP (varop
, 0) == const0_rtx
4980 && (significant_bits (XEXP (varop
, 0), mode
) & ~ constop
) == 0)
4982 varop
= XEXP (varop
, 0);
4988 /* In (and (plus FOO C1) M), if M is a mask that just turns off
4989 low-order bits (as in an alignment operation) and FOO is already
4990 aligned to that boundary, we can convert remove this AND
4991 and possibly the PLUS if it is now adding zero. */
4992 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
4993 && exact_log2 (-constop
) >= 0
4994 && (significant_bits (XEXP (varop
, 0), mode
) & ~ constop
) == 0)
4996 varop
= plus_constant (XEXP (varop
, 0),
4997 INTVAL (XEXP (varop
, 1)) & constop
);
5002 /* ... fall through ... */
5005 /* In (and (plus (and FOO M1) BAR) M2), if M1 and M2 are one
5006 less than powers of two and M2 is narrower than M1, we can
5007 eliminate the inner AND. This occurs when incrementing
5010 if (GET_CODE (XEXP (varop
, 0)) == ZERO_EXTRACT
5011 || GET_CODE (XEXP (varop
, 0)) == ZERO_EXTEND
)
5012 SUBST (XEXP (varop
, 0),
5013 expand_compound_operation (XEXP (varop
, 0)));
5015 if (GET_CODE (XEXP (varop
, 0)) == AND
5016 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
5017 && exact_log2 (constop
+ 1) >= 0
5018 && exact_log2 (INTVAL (XEXP (XEXP (varop
, 0), 1)) + 1) >= 0
5019 && (~ INTVAL (XEXP (XEXP (varop
, 0), 1)) & constop
) == 0)
5020 SUBST (XEXP (varop
, 0), XEXP (XEXP (varop
, 0), 0));
5027 /* If we have reached a constant, this whole thing is constant. */
5028 if (GET_CODE (varop
) == CONST_INT
)
5029 return gen_rtx (CONST_INT
, VOIDmode
, constop
& INTVAL (varop
));
5031 /* See what bits are significant in VAROP. */
5032 significant
= significant_bits (varop
, mode
);
5034 /* Turn off all bits in the constant that are known to already be zero.
5035 Thus, if the AND isn't needed at all, we will have CONSTOP == SIGNIFICANT
5036 which is tested below. */
5038 constop
&= significant
;
5040 /* If we don't have any bits left, return zero. */
5044 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
5045 if we already had one (just check for the simplest cases). */
5046 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
5047 && GET_MODE (XEXP (x
, 0)) == mode
5048 && SUBREG_REG (XEXP (x
, 0)) == varop
)
5049 varop
= XEXP (x
, 0);
5051 varop
= gen_lowpart_for_combine (mode
, varop
);
5053 /* If we can't make the SUBREG, try to return what we were given. */
5054 if (GET_CODE (varop
) == CLOBBER
)
5055 return x
? x
: varop
;
5057 /* If we are only masking insignificant bits, return VAROP. */
5058 if (constop
== significant
)
5061 /* Otherwise, return an AND. See how much, if any, of X we can use. */
5062 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
5063 x
= gen_rtx_combine (AND
, mode
, varop
,
5064 gen_rtx (CONST_INT
, VOIDmode
, constop
));
5068 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5069 || INTVAL (XEXP (x
, 1)) != constop
)
5070 SUBST (XEXP (x
, 1), gen_rtx (CONST_INT
, VOIDmode
, constop
));
5072 SUBST (XEXP (x
, 0), varop
);
5078 /* Given an expression, X, compute which bits in X can be non-zero.
5079 We don't care about bits outside of those defined in MODE.
5081 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
5082 a shift, AND, or zero_extract, we can do better. */
5085 significant_bits (x
, mode
)
5087 enum machine_mode mode
;
5089 unsigned significant
= GET_MODE_MASK (mode
);
5092 int mode_width
= GET_MODE_BITSIZE (mode
);
5095 /* If X is wider than MODE, use its mode instead. */
5096 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
5098 mode
= GET_MODE (x
);
5099 significant
= GET_MODE_MASK (mode
);
5100 mode_width
= GET_MODE_BITSIZE (mode
);
5103 if (mode_width
> HOST_BITS_PER_INT
)
5104 /* Our only callers in this case look for single bit values. So
5105 just return the mode mask. Those tests will then be false. */
5108 code
= GET_CODE (x
);
5112 #ifdef STACK_BOUNDARY
5113 /* If this is the stack pointer, we may know something about its
5114 alignment. If PUSH_ROUNDING is defined, it is possible for the
5115 stack to be momentarily aligned only to that amount, so we pick
5116 the least alignment. */
5118 if (x
== stack_pointer_rtx
)
5120 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
5122 #ifdef PUSH_ROUNDING
5123 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
5126 return significant
& ~ (sp_alignment
- 1);
5130 /* If X is a register whose value we can find, use that value.
5131 Otherwise, use the previously-computed significant bits for this
5134 tem
= get_last_value (x
);
5136 return significant_bits (tem
, mode
);
5137 else if (significant_valid
&& reg_significant
[REGNO (x
)])
5138 return reg_significant
[REGNO (x
)] & significant
;
5145 #ifdef BYTE_LOADS_ZERO_EXTEND
5147 /* In many, if not most, RISC machines, reading a byte from memory
5148 zeros the rest of the register. Noticing that fact saves a lot
5149 of extra zero-extends. */
5150 significant
&= GET_MODE_MASK (GET_MODE (x
));
5154 #if STORE_FLAG_VALUE == 1
5161 if (GET_MODE_CLASS (mode
) == MODE_INT
)
5164 /* A comparison operation only sets the bits given by its mode. The
5165 rest are set undefined. */
5166 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
5167 significant
|= (GET_MODE_MASK (mode
) & ~ GET_MODE_MASK (GET_MODE (x
)));
5171 #if STORE_FLAG_VALUE == -1
5173 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
5174 || ((tem
= get_last_value (XEXP (x
, 0))) != 0
5175 && GET_RTX_CLASS (GET_CODE (tem
)) == '<'))
5178 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
5179 significant
|= (GET_MODE_MASK (mode
) & ~ GET_MODE_MASK (GET_MODE (x
)));
5184 significant
&= (significant_bits (XEXP (x
, 0), mode
)
5185 & GET_MODE_MASK (mode
));
5189 significant
&= significant_bits (XEXP (x
, 0), mode
);
5190 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
5191 significant
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
5195 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
5196 Otherwise, show all the bits in the outer mode but not the inner
5198 inner_sig
= significant_bits (XEXP (x
, 0), mode
);
5199 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
5201 inner_sig
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
5203 (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
5204 inner_sig
|= (GET_MODE_MASK (mode
)
5205 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
5208 significant
&= inner_sig
;
5212 significant
&= (significant_bits (XEXP (x
, 0), mode
)
5213 & significant_bits (XEXP (x
, 1), mode
));
5218 significant
&= (significant_bits (XEXP (x
, 0), mode
)
5219 | significant_bits (XEXP (x
, 1), mode
));
5222 case PLUS
: case MINUS
:
5224 case DIV
: case UDIV
:
5225 case MOD
: case UMOD
:
5226 /* We can apply the rules of arithmetic to compute the number of
5227 high- and low-order zero bits of these operations. We start by
5228 computing the width (position of the highest-order non-zero bit)
5229 and the number of low-order zero bits for each value. */
5231 unsigned sig0
= significant_bits (XEXP (x
, 0), mode
);
5232 unsigned sig1
= significant_bits (XEXP (x
, 1), mode
);
5233 int width0
= floor_log2 (sig0
) + 1;
5234 int width1
= floor_log2 (sig1
) + 1;
5235 int low0
= floor_log2 (sig0
& -sig0
);
5236 int low1
= floor_log2 (sig1
& -sig1
);
5237 int op0_maybe_minusp
= (sig0
& (1 << (mode_width
- 1)));
5238 int op1_maybe_minusp
= (sig1
& (1 << (mode_width
- 1)));
5239 int result_width
= mode_width
;
5245 result_width
= MAX (width0
, width1
) + 1;
5246 result_low
= MIN (low0
, low1
);
5249 result_low
= MIN (low0
, low1
);
5252 result_width
= width0
+ width1
;
5253 result_low
= low0
+ low1
;
5256 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
5257 result_width
= width0
;
5260 result_width
= width0
;
5263 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
5264 result_width
= MIN (width0
, width1
);
5265 result_low
= MIN (low0
, low1
);
5268 result_width
= MIN (width0
, width1
);
5269 result_low
= MIN (low0
, low1
);
5273 if (result_width
< mode_width
)
5274 significant
&= (1 << result_width
) - 1;
5277 significant
&= ~ ((1 << result_low
) - 1);
5282 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
5283 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_INT
)
5284 significant
&= (1 << INTVAL (XEXP (x
, 1))) - 1;
5288 /* If the inner mode is a single word for both the host and target
5289 machines, we can compute this from which bits of the inner
5290 object are known significant. */
5291 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
5292 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= HOST_BITS_PER_INT
)
5294 significant
&= significant_bits (SUBREG_REG (x
), mode
);
5295 #ifndef BYTE_LOADS_ZERO_EXTEND
5296 /* On many CISC machines, accessing an object in a wider mode
5297 causes the high-order bits to become undefined. So they are
5298 not known to be zero. */
5299 if (GET_MODE_SIZE (GET_MODE (x
))
5300 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
5301 significant
|= (GET_MODE_MASK (GET_MODE (x
))
5302 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
5312 /* The significant bits are in two classes: any bits within MODE
5313 that aren't in GET_MODE (x) are always significant. The rest of the
5314 significant bits are those that are significant in the operand of
5315 the shift when shifted the appropriate number of bits. This
5316 shows that high-order bits are cleared by the right shift and
5317 low-order bits by left shifts. */
5318 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
5319 && INTVAL (XEXP (x
, 1)) >= 0
5320 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_INT
)
5322 enum machine_mode inner_mode
= GET_MODE (x
);
5323 int width
= GET_MODE_BITSIZE (inner_mode
);
5324 int count
= INTVAL (XEXP (x
, 1));
5325 unsigned mode_mask
= GET_MODE_MASK (inner_mode
);
5326 unsigned op_significant
= significant_bits (XEXP (x
, 0), mode
);
5327 unsigned inner
= op_significant
& mode_mask
;
5330 if (mode_width
> width
)
5331 outer
= (op_significant
& significant
& ~ mode_mask
);
5333 if (code
== LSHIFTRT
)
5335 else if (code
== ASHIFTRT
)
5339 /* If the sign bit was significant at before the shift, we
5340 need to mark all the places it could have been copied to
5341 by the shift significant. */
5342 if (inner
& (1 << (width
- 1 - count
)))
5343 inner
|= ((1 << count
) - 1) << (width
- count
);
5345 else if (code
== LSHIFT
|| code
== ASHIFT
)
5348 inner
= ((inner
<< (count
% width
)
5349 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
5351 significant
&= (outer
| inner
);
5356 /* This is at most the number of bits in the mode. */
5357 significant
= (1 << (floor_log2 (mode_width
) + 1)) - 1;
5364 /* This function is called from `simplify_shift_const' to merge two
5365 outer operations. Specifically, we have already found that we need
5366 to perform operation *POP0 with constant *PCONST0 at the outermost
5367 position. We would now like to also perform OP1 with constant CONST1
5368 (with *POP0 being done last).
5370 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
5371 the resulting operation. *PCOMP_P is set to 1 if we would need to
5372 complement the innermost operand, otherwise it is unchanged.
5374 MODE is the mode in which the operation will be done. No bits outside
5375 the width of this mode matter. It is assumed that the width of this mode
5376 is smaller than or equal to HOST_BITS_PER_INT.
5378 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
5379 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
5380 result is simply *PCONST0.
5382 If the resulting operation cannot be expressed as one operation, we
5383 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
5386 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
5387 enum rtx_code
*pop0
;
5391 enum machine_mode mode
;
5394 enum rtx_code op0
= *pop0
;
5395 int const0
= *pconst0
;
5397 const0
&= GET_MODE_MASK (mode
);
5398 const1
&= GET_MODE_MASK (mode
);
5400 /* If OP0 is an AND, clear unimportant bits in CONST1. */
5404 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
5407 if (op1
== NIL
|| op0
== SET
)
5410 else if (op0
== NIL
)
5411 op0
= op1
, const0
= const1
;
5413 else if (op0
== op1
)
5435 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
5436 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
5439 /* If the two constants aren't the same, we can't do anything. The
5440 remaining six cases can all be done. */
5441 else if (const0
!= const1
)
5449 /* (a & b) | b == b */
5451 else /* op1 == XOR */
5452 /* (a ^ b) | b == a | b */
5458 /* (a & b) ^ b == (~a) & b */
5459 op0
= AND
, *pcomp_p
= 1;
5460 else /* op1 == IOR */
5461 /* (a | b) ^ b == a & ~b */
5462 op0
= AND
, *pconst0
= ~ const0
;
5467 /* (a | b) & b == b */
5469 else /* op1 == XOR */
5470 /* (a ^ b) & b) == (~a) & b */
5475 /* Check for NO-OP cases. */
5476 const0
&= GET_MODE_MASK (mode
);
5478 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
5480 else if (const0
== 0 && op0
== AND
)
5482 else if (const0
== GET_MODE_MASK (mode
) && op0
== AND
)
5491 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
5492 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
5493 that we started with.
5495 The shift is normally computed in the widest mode we find in VAROP, as
5496 long as it isn't a different number of words than RESULT_MODE. Exceptions
5497 are ASHIFTRT and ROTATE, which are always done in their original mode, */
5500 simplify_shift_const (x
, code
, result_mode
, varop
, count
)
5503 enum machine_mode result_mode
;
5507 enum rtx_code orig_code
= code
;
5508 int orig_count
= count
;
5509 enum machine_mode mode
= result_mode
;
5510 enum machine_mode shift_mode
, tmode
;
5512 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
5513 /* We form (outer_op (code varop count) (outer_const)). */
5514 enum rtx_code outer_op
= NIL
;
5517 int complement_p
= 0;
5520 /* If we were given an invalid count, don't do anything except exactly
5521 what was requested. */
5523 if (count
< 0 || count
> GET_MODE_BITSIZE (mode
))
5528 return gen_rtx (code
, mode
, varop
, gen_rtx (CONST_INT
, VOIDmode
, count
));
5531 /* Unless one of the branches of the `if' in this loop does a `continue',
5532 we will `break' the loop after the `if'. */
5536 /* If we have an operand of (clobber (const_int 0)), just return that
5538 if (GET_CODE (varop
) == CLOBBER
)
5541 /* If we discovered we had to complement VAROP, leave. Making a NOT
5542 here would cause an infinite loop. */
5546 /* Convert ROTATETRT to ROTATE. */
5547 if (code
== ROTATERT
)
5548 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
5550 /* Canonicalize LSHIFT to ASHIFT. */
5554 /* We need to determine what mode we will do the shift in. If the
5555 shift is a ASHIFTRT or ROTATE, we must always do it in the mode it
5556 was originally done in. Otherwise, we can do it in MODE, the widest
5557 mode encountered. */
5558 shift_mode
= (code
== ASHIFTRT
|| code
== ROTATE
? result_mode
: mode
);
5560 /* Handle cases where the count is greater than the size of the mode
5561 minus 1. For ASHIFT, use the size minus one as the count (this can
5562 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
5563 take the count modulo the size. For other shifts, the result is
5566 Since these shifts are being produced by the compiler by combining
5567 multiple operations, each of which are defined, we know what the
5568 result is supposed to be. */
5570 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
5572 if (code
== ASHIFTRT
)
5573 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
5574 else if (code
== ROTATE
|| code
== ROTATERT
)
5575 count
%= GET_MODE_BITSIZE (shift_mode
);
5578 /* We can't simply return zero because there may be an
5586 /* Negative counts are invalid and should not have been made (a
5587 programmer-specified negative count should have been handled
5592 /* We simplify the tests below and elsewhere by converting
5593 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
5594 `make_compound_operation' will convert it to a ASHIFTRT for
5595 those machines (such as Vax) that don't have a LSHIFTRT. */
5596 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_INT
5598 && (significant_bits (varop
, shift_mode
)
5599 & (1 << (GET_MODE_BITSIZE (shift_mode
) - 1))) == 0)
5602 switch (GET_CODE (varop
))
5608 new = expand_compound_operation (varop
);
5617 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
5618 minus the width of a smaller mode, we can do this with a
5619 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
5620 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
5621 && ! mode_dependent_address_p (XEXP (varop
, 0))
5622 && ! MEM_VOLATILE_P (varop
)
5623 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
5624 MODE_INT
, 1)) != BLKmode
)
5626 #if BYTES_BIG_ENDIAN
5627 new = gen_rtx (MEM
, tmode
, XEXP (varop
, 0));
5629 new = gen_rtx (MEM
, tmode
,
5630 plus_constant (XEXP (varop
, 0),
5631 count
/ BITS_PER_UNIT
));
5632 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop
);
5633 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop
);
5634 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop
);
5636 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
5637 : ZERO_EXTEND
, mode
, new);
5644 /* Similar to the case above, except that we can only do this if
5645 the resulting mode is the same as that of the underlying
5646 MEM and adjust the address depending on the *bits* endianness
5647 because of the way that bit-field extract insns are defined. */
5648 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
5649 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
5650 MODE_INT
, 1)) != BLKmode
5651 && tmode
== GET_MODE (XEXP (varop
, 0)))
5654 new = XEXP (varop
, 0);
5656 new = copy_rtx (XEXP (varop
, 0));
5657 SUBST (XEXP (new, 0),
5658 plus_constant (XEXP (new, 0),
5659 count
/ BITS_PER_UNIT
));
5662 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
5663 : ZERO_EXTEND
, mode
, new);
5670 /* If VAROP is a SUBREG, strip it as long as the inner operand has
5671 the same number of words as what we've seen so far. Then store
5672 the widest mode in MODE. */
5673 if (SUBREG_WORD (varop
) == 0
5674 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
5675 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5678 varop
= SUBREG_REG (varop
);
5679 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
5680 mode
= GET_MODE (varop
);
5686 /* Some machines use MULT instead of ASHIFT because MULT
5687 is cheaper. But it is still better on those machines to
5688 merge two shifts into one. */
5689 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
5690 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
5692 varop
= gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
5693 gen_rtx (CONST_INT
, VOIDmode
,
5694 exact_log2 (INTVAL (XEXP (varop
, 1)))));
5700 /* Similar, for when divides are cheaper. */
5701 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
5702 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
5704 varop
= gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
5705 gen_rtx (CONST_INT
, VOIDmode
,
5706 exact_log2 (INTVAL (XEXP (varop
, 1)))));
5712 /* If we are extracting just the sign bit of an arithmetic right
5713 shift, that shift is not needed. */
5714 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1)
5716 varop
= XEXP (varop
, 0);
5720 /* ... fall through ... */
5726 /* Here we have two nested shifts. The result is usually the
5727 AND of a new shift with a mask. We compute the result below. */
5728 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
5729 && INTVAL (XEXP (varop
, 1)) >= 0
5730 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
5731 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_INT
5732 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_INT
)
5734 enum rtx_code first_code
= GET_CODE (varop
);
5735 int first_count
= INTVAL (XEXP (varop
, 1));
5740 if (first_code
== LSHIFT
)
5741 first_code
= ASHIFT
;
5743 /* We have one common special case. We can't do any merging if
5744 the inner code is an ASHIFTRT of a smaller mode. However, if
5745 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
5746 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
5747 we can convert it to
5748 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
5749 This simplifies certain SIGN_EXTEND operations. */
5750 if (code
== ASHIFT
&& first_code
== ASHIFTRT
5751 && (GET_MODE_BITSIZE (result_mode
)
5752 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
5754 /* C3 has the low-order C1 bits zero. */
5756 mask
= GET_MODE_MASK (mode
) & ~ ((1 << first_count
) - 1);
5758 varop
= simplify_and_const_int (0, result_mode
,
5759 XEXP (varop
, 0), mask
);
5760 varop
= simplify_shift_const (0, ASHIFT
, result_mode
,
5762 count
= first_count
;
5767 /* If this was (ashiftrt (ashift foo C1) C2) and we know
5768 something about FOO's previous value, we may be able to
5769 optimize this even though the code below can't handle this
5772 If FOO has J high-order bits equal to the sign bit with
5773 J > C1, then we can convert this to either an ASHIFT or
5774 a ASHIFTRT depending on the two counts.
5776 We cannot do this if VAROP's mode is not SHIFT_MODE. */
5778 if (code
== ASHIFTRT
&& first_code
== ASHIFT
5779 && GET_MODE (varop
) == shift_mode
5780 && (inner
= get_last_value (XEXP (varop
, 0))) != 0)
5782 if ((GET_CODE (inner
) == CONST_INT
5783 && (INTVAL (inner
) >> (HOST_BITS_PER_INT
- (first_count
+ 1)) == 0
5784 || (INTVAL (inner
) >> (HOST_BITS_PER_INT
- (first_count
+ 1)) == -1)))
5785 || (GET_CODE (inner
) == SIGN_EXTEND
5786 && ((GET_MODE_BITSIZE (GET_MODE (inner
))
5787 - GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner
))))
5789 || (GET_CODE (inner
) == ASHIFTRT
5790 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
5791 && INTVAL (XEXP (inner
, 1)) >= first_count
))
5793 count
-= first_count
;
5795 count
= - count
, code
= ASHIFT
;
5796 varop
= XEXP (varop
, 0);
5801 /* There are some cases we can't do. If CODE is ASHIFTRT,
5802 we can only do this if FIRST_CODE is also ASHIFTRT.
5804 We can't do the case when CODE is ROTATE and FIRST_CODE is
5807 If the mode of this shift is not the mode of the outer shift,
5808 we can't do this if either shift is ASHIFTRT or ROTATE.
5810 Finally, we can't do any of these if the mode is too wide
5811 unless the codes are the same.
5813 Handle the case where the shift codes are the same
5816 if (code
== first_code
)
5818 if (GET_MODE (varop
) != result_mode
5819 && (code
== ASHIFTRT
|| code
== ROTATE
))
5822 count
+= first_count
;
5823 varop
= XEXP (varop
, 0);
5827 if (code
== ASHIFTRT
5828 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
5829 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_INT
5830 || (GET_MODE (varop
) != result_mode
5831 && (first_code
== ASHIFTRT
|| first_code
== ROTATE
5832 || code
== ROTATE
)))
5835 /* To compute the mask to apply after the shift, shift the
5836 significant bits of the inner shift the same way the
5837 outer shift will. */
5839 mask_rtx
= gen_rtx (CONST_INT
, VOIDmode
,
5840 significant_bits (varop
, GET_MODE (varop
)));
5843 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
5844 gen_rtx (CONST_INT
, VOIDmode
,
5847 /* Give up if we can't compute an outer operation to use. */
5849 || GET_CODE (mask_rtx
) != CONST_INT
5850 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
5852 result_mode
, &complement_p
))
5855 /* If the shifts are in the same direction, we add the
5856 counts. Otherwise, we subtract them. */
5857 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
5858 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
5859 count
+= first_count
;
5861 count
-= first_count
;
5863 /* If COUNT is positive, the new shift is usually CODE,
5864 except for the two exceptions below, in which case it is
5865 FIRST_CODE. If the count is negative, FIRST_CODE should
5868 && ((first_code
== ROTATE
&& code
== ASHIFT
)
5869 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
5872 code
= first_code
, count
= - count
;
5874 varop
= XEXP (varop
, 0);
5878 /* If we have (A << B << C) for any shift, we can convert this to
5879 (A << C << B). This wins if A is a constant. Only try this if
5880 B is not a constant. */
5882 else if (GET_CODE (varop
) == code
5883 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
5885 = simplify_binary_operation (code
, mode
,
5891 varop
= gen_rtx_combine (code
, mode
, new, XEXP (varop
, 1));
5898 /* Make this fit the case below. */
5899 varop
= gen_rtx_combine (XOR
, mode
, XEXP (varop
, 0),
5900 gen_rtx (CONST_INT
, VOIDmode
,
5901 GET_MODE_MASK (mode
)));
5907 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
5908 with C the size of VAROP - 1 and the shift is logical if
5909 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
5910 we have an (le X 0) operation. If we have an arithmetic shift
5911 and STORE_FLAG_VALUE is 1 or we have a logical shift with
5912 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
5914 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
5915 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
5916 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5917 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
5918 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
5919 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
5922 varop
= gen_rtx_combine (LE
, GET_MODE (varop
), XEXP (varop
, 1),
5925 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
5926 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
5931 /* If we have (shift (logical)), move the logical to the outside
5932 to allow it to possibly combine with another logical and the
5933 shift to combine with another shift. This also canonicalizes to
5934 what a ZERO_EXTRACT looks like. Also, some machines have
5935 (and (shift)) insns. */
5937 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
5938 && (new = simplify_binary_operation (code
, result_mode
,
5943 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
5944 INTVAL (new), result_mode
, &complement_p
))
5946 varop
= XEXP (varop
, 0);
5950 /* If we can't do that, try to simplify the shift in each arm of the
5951 logical expression, make a new logical expression, and apply
5952 the inverse distributive law. */
5954 rtx lhs
= simplify_shift_const (0, code
, result_mode
,
5955 XEXP (varop
, 0), count
);
5956 rtx rhs
= simplify_shift_const (0, code
, result_mode
,
5957 XEXP (varop
, 1), count
);
5959 varop
= gen_binary (GET_CODE (varop
), result_mode
, lhs
, rhs
);
5960 varop
= apply_distributive_law (varop
);
5967 /* convert (lshift (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
5968 says that the sign bit can be tested, FOO has mode MODE, C is
5969 GET_MODE_BITSIZE (MODE) - 1, and FOO has only the low-order bit
5972 && XEXP (varop
, 1) == const0_rtx
5973 && GET_MODE (XEXP (varop
, 0)) == result_mode
5974 && count
== GET_MODE_BITSIZE (result_mode
) - 1
5975 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_INT
5976 && ((STORE_FLAG_VALUE
5977 & (1 << (GET_MODE_BITSIZE (result_mode
) - 1))))
5978 && significant_bits (XEXP (varop
, 0), result_mode
) == 1
5979 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1,
5980 result_mode
, &complement_p
))
5982 varop
= XEXP (varop
, 0);
5989 /* If we are doing an arithmetic right shift of something known
5990 to be -1 or 0, we don't need the shift. */
5991 if (code
== ASHIFTRT
5992 && significant_bits (XEXP (varop
, 0), result_mode
) == 1)
5998 /* NEG commutes with ASHIFT since it is multiplication. Move the
5999 NEG outside to allow shifts to combine. */
6001 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0,
6002 result_mode
, &complement_p
))
6004 varop
= XEXP (varop
, 0);
6010 /* Similar to case above. If X is 0 or 1 then X - 1 is -1 or 0. */
6011 if (XEXP (varop
, 1) == constm1_rtx
&& code
== ASHIFTRT
6012 && significant_bits (XEXP (varop
, 0), result_mode
) == 1)
6018 /* If we have the same operands as above but we are shifting the
6019 sign bit into the low-order bit, we are exclusive-or'ing
6020 the operand of the PLUS with a one. */
6021 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
6022 && XEXP (varop
, 1) == constm1_rtx
6023 && significant_bits (XEXP (varop
, 0), result_mode
) == 1
6024 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1,
6025 result_mode
, &complement_p
))
6028 varop
= XEXP (varop
, 0);
6032 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
6033 significant in BAR are those being shifted out and those
6034 bits are known zero in FOO, we can replace the PLUS with FOO.
6035 Similarly in the other operand order. This code occurs when
6036 we are computing the size of a variable-size array. */
6038 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
6039 && count
< HOST_BITS_PER_INT
6040 && significant_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
6041 && (significant_bits (XEXP (varop
, 1), result_mode
)
6042 & significant_bits (XEXP (varop
, 0), result_mode
)) == 0)
6044 varop
= XEXP (varop
, 0);
6047 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
6048 && count
< HOST_BITS_PER_INT
6049 && 0 == (significant_bits (XEXP (varop
, 0), result_mode
)
6051 && 0 == (significant_bits (XEXP (varop
, 0), result_mode
)
6052 & significant_bits (XEXP (varop
, 1),
6055 varop
= XEXP (varop
, 1);
6059 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
6061 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
6062 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
6067 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
6068 INTVAL (new), result_mode
, &complement_p
))
6070 varop
= XEXP (varop
, 0);
6076 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
6077 with C the size of VAROP - 1 and the shift is logical if
6078 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
6079 we have a (gt X 0) operation. If the shift is arithmetic with
6080 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
6081 we have a (neg (gt X 0)) operation. */
6083 if (GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
6084 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
6085 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6086 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
6087 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
6088 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
6089 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
6092 varop
= gen_rtx_combine (GT
, GET_MODE (varop
), XEXP (varop
, 1),
6095 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
6096 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
6106 /* We need to determine what mode to do the shift in. If the shift is
6107 a ASHIFTRT or ROTATE, we must always do it in the mode it was originally
6108 done in. Otherwise, we can do it in MODE, the widest mode encountered.
6109 The code we care about is that of the shift that will actually be done,
6110 not the shift that was originally requested. */
6111 shift_mode
= (code
== ASHIFTRT
|| code
== ROTATE
? result_mode
: mode
);
6113 /* We have now finished analyzing the shift. The result should be
6114 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
6115 OUTER_OP is non-NIL, it is an operation that needs to be applied
6116 to the result of the shift. OUTER_CONST is the relevant constant,
6117 but we must turn off all bits turned off in the shift.
6119 If we were passed a value for X, see if we can use any pieces of
6120 it. If not, make new rtx. */
6122 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
6123 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6124 && INTVAL (XEXP (x
, 1)) == count
)
6125 const_rtx
= XEXP (x
, 1);
6127 const_rtx
= gen_rtx (CONST_INT
, VOIDmode
, count
);
6129 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
6130 && GET_MODE (XEXP (x
, 0)) == shift_mode
6131 && SUBREG_REG (XEXP (x
, 0)) == varop
)
6132 varop
= XEXP (x
, 0);
6133 else if (GET_MODE (varop
) != shift_mode
)
6134 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
6136 /* If we can't make the SUBREG, try to return what we were given. */
6137 if (GET_CODE (varop
) == CLOBBER
)
6138 return x
? x
: varop
;
6140 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
6145 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
6146 x
= gen_rtx_combine (code
, shift_mode
, varop
, const_rtx
);
6148 SUBST (XEXP (x
, 0), varop
);
6149 SUBST (XEXP (x
, 1), const_rtx
);
6152 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
6153 turn off all the bits that the shift would have turned off. */
6154 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
6155 x
= simplify_and_const_int (0, shift_mode
, x
,
6156 GET_MODE_MASK (result_mode
) >> orig_count
);
6158 /* Do the remainder of the processing in RESULT_MODE. */
6159 x
= gen_lowpart_for_combine (result_mode
, x
);
6161 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
6164 x
= gen_unary (NOT
, result_mode
, x
);
6166 if (outer_op
!= NIL
)
6168 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_INT
)
6169 outer_const
&= GET_MODE_MASK (result_mode
);
6171 if (outer_op
== AND
)
6172 x
= simplify_and_const_int (0, result_mode
, x
, outer_const
);
6173 else if (outer_op
== SET
)
6174 /* This means that we have determined that the result is
6175 equivalent to a constant. This should be rare. */
6176 x
= gen_rtx (CONST_INT
, VOIDmode
, outer_const
);
6177 else if (GET_RTX_CLASS (outer_op
) == '1')
6178 x
= gen_unary (outer_op
, result_mode
, x
);
6180 x
= gen_binary (outer_op
, result_mode
, x
,
6181 gen_rtx (CONST_INT
, VOIDmode
, outer_const
));
6187 /* Like recog, but we receive the address of a pointer to a new pattern.
6188 We try to match the rtx that the pointer points to.
6189 If that fails, we may try to modify or replace the pattern,
6190 storing the replacement into the same pointer object.
6192 Modifications include deletion or addition of CLOBBERs.
6194 PNOTES is a pointer to a location where any REG_UNUSED notes added for
6195 the CLOBBERs are placed.
6197 The value is the final insn code from the pattern ultimately matched,
6201 recog_for_combine (pnewpat
, insn
, pnotes
)
6206 register rtx pat
= *pnewpat
;
6207 int insn_code_number
;
6208 int num_clobbers_to_add
= 0;
6212 /* Is the result of combination a valid instruction? */
6213 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
6215 /* If it isn't, there is the possibility that we previously had an insn
6216 that clobbered some register as a side effect, but the combined
6217 insn doesn't need to do that. So try once more without the clobbers
6218 unless this represents an ASM insn. */
6220 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
6221 && GET_CODE (pat
) == PARALLEL
)
6225 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
6226 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
6229 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
6233 SUBST_INT (XVECLEN (pat
, 0), pos
);
6236 pat
= XVECEXP (pat
, 0, 0);
6238 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
6241 /* If we had any clobbers to add, make a new pattern than contains
6242 them. Then check to make sure that all of them are dead. */
6243 if (num_clobbers_to_add
)
6245 rtx newpat
= gen_rtx (PARALLEL
, VOIDmode
,
6246 gen_rtvec (GET_CODE (pat
) == PARALLEL
6247 ? XVECLEN (pat
, 0) + num_clobbers_to_add
6248 : num_clobbers_to_add
+ 1));
6250 if (GET_CODE (pat
) == PARALLEL
)
6251 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
6252 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
6254 XVECEXP (newpat
, 0, 0) = pat
;
6256 add_clobbers (newpat
, insn_code_number
);
6258 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
6259 i
< XVECLEN (newpat
, 0); i
++)
6261 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
6262 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
6264 notes
= gen_rtx (EXPR_LIST
, REG_UNUSED
,
6265 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
6273 return insn_code_number
;
6276 /* Like gen_lowpart but for use by combine. In combine it is not possible
6277 to create any new pseudoregs. However, it is safe to create
6278 invalid memory addresses, because combine will try to recognize
6279 them and all they will do is make the combine attempt fail.
6281 If for some reason this cannot do its job, an rtx
6282 (clobber (const_int 0)) is returned.
6283 An insn containing that will not be recognized. */
6288 gen_lowpart_for_combine (mode
, x
)
6289 enum machine_mode mode
;
6294 if (GET_MODE (x
) == mode
)
6297 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
6298 return gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
6300 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
6301 won't know what to do. So we will strip off the SUBREG here and
6302 process normally. */
6303 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
6306 if (GET_MODE (x
) == mode
)
6310 result
= gen_lowpart_common (mode
, x
);
6314 if (GET_CODE (x
) == MEM
)
6316 register int offset
= 0;
6319 /* Refuse to work on a volatile memory ref or one with a mode-dependent
6321 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
6322 return gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
6324 /* If we want to refer to something bigger than the original memref,
6325 generate a perverse subreg instead. That will force a reload
6326 of the original memref X. */
6327 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
6328 return gen_rtx (SUBREG
, mode
, x
, 0);
6330 #if WORDS_BIG_ENDIAN
6331 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
6332 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
6334 #if BYTES_BIG_ENDIAN
6335 /* Adjust the address so that the address-after-the-data
6337 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
6338 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
6340 new = gen_rtx (MEM
, mode
, plus_constant (XEXP (x
, 0), offset
));
6341 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x
);
6342 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x
);
6343 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x
);
6347 /* If X is a comparison operator, rewrite it in a new mode. This
6348 probably won't match, but may allow further simplifications. */
6349 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
6350 return gen_rtx_combine (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
6352 /* If we couldn't simplify X any other way, just enclose it in a
6353 SUBREG. Normally, this SUBREG won't match, but some patterns may
6354 include an explicit SUBREG or we may simplify it further in combine. */
6359 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
6360 word
= ((GET_MODE_SIZE (GET_MODE (x
))
6361 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
6363 return gen_rtx (SUBREG
, mode
, x
, word
);
6367 /* Make an rtx expression. This is a subset of gen_rtx and only supports
6368 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
6370 If the identical expression was previously in the insn (in the undobuf),
6371 it will be returned. Only if it is not found will a new expression
6376 gen_rtx_combine (va_alist
)
6381 enum machine_mode mode
;
6389 code
= va_arg (p
, enum rtx_code
);
6390 mode
= va_arg (p
, enum machine_mode
);
6391 n_args
= GET_RTX_LENGTH (code
);
6392 fmt
= GET_RTX_FORMAT (code
);
6394 if (n_args
== 0 || n_args
> 3)
6397 /* Get each arg and verify that it is supposed to be an expression. */
6398 for (j
= 0; j
< n_args
; j
++)
6403 args
[j
] = va_arg (p
, rtx
);
6406 /* See if this is in undobuf. Be sure we don't use objects that came
6407 from another insn; this could produce circular rtl structures. */
6409 for (i
= previous_num_undos
; i
< undobuf
.num_undo
; i
++)
6410 if (!undobuf
.undo
[i
].is_int
6411 && GET_CODE (undobuf
.undo
[i
].old_contents
) == code
6412 && GET_MODE (undobuf
.undo
[i
].old_contents
) == mode
)
6414 for (j
= 0; j
< n_args
; j
++)
6415 if (XEXP (undobuf
.undo
[i
].old_contents
, j
) != args
[j
])
6419 return undobuf
.undo
[i
].old_contents
;
6422 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
6423 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
6424 rt
= rtx_alloc (code
);
6425 PUT_MODE (rt
, mode
);
6426 XEXP (rt
, 0) = args
[0];
6429 XEXP (rt
, 1) = args
[1];
6431 XEXP (rt
, 2) = args
[2];
6436 /* These routines make binary and unary operations by first seeing if they
6437 fold; if not, a new expression is allocated. */
6440 gen_binary (code
, mode
, op0
, op1
)
6442 enum machine_mode mode
;
6447 if (GET_RTX_CLASS (code
) == '<')
6449 enum machine_mode op_mode
= GET_MODE (op0
);
6450 if (op_mode
== VOIDmode
)
6451 op_mode
= GET_MODE (op1
);
6452 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
6455 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
6460 /* Put complex operands first and constants second. */
6461 if (GET_RTX_CLASS (code
) == 'c'
6462 && ((CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
6463 || (GET_RTX_CLASS (GET_CODE (op0
)) == 'o'
6464 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')
6465 || (GET_CODE (op0
) == SUBREG
6466 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0
))) == 'o'
6467 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')))
6468 return gen_rtx_combine (code
, mode
, op1
, op0
);
6470 return gen_rtx_combine (code
, mode
, op0
, op1
);
6474 gen_unary (code
, mode
, op0
)
6476 enum machine_mode mode
;
6479 rtx result
= simplify_unary_operation (code
, mode
, op0
, mode
);
6484 return gen_rtx_combine (code
, mode
, op0
);
6487 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
6488 comparison code that will be tested.
6490 The result is a possibly different comparison code to use. *POP0 and
6491 *POP1 may be updated.
6493 It is possible that we might detect that a comparison is either always
6494 true or always false. However, we do not perform general constant
6495 folding in combine, so this knowledge isn't useful. Such tautologies
6496 should have been detected earlier. Hence we ignore all such cases. */
6498 static enum rtx_code
6499 simplify_comparison (code
, pop0
, pop1
)
6508 enum machine_mode mode
, tmode
;
6510 /* Try a few ways of applying the same transformation to both operands. */
6513 /* If both operands are the same constant shift, see if we can ignore the
6514 shift. We can if the shift is a rotate or if the bits shifted out of
6515 this shift are not significant for either input and if the type of
6516 comparison is compatible with the shift. */
6517 if (GET_CODE (op0
) == GET_CODE (op1
)
6518 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_INT
6519 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
6520 || ((GET_CODE (op0
) == LSHIFTRT
6521 || GET_CODE (op0
) == ASHIFT
|| GET_CODE (op0
) == LSHIFT
)
6522 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
6523 || (GET_CODE (op0
) == ASHIFTRT
6524 && (code
!= GTU
&& code
!= LTU
6525 && code
!= GEU
&& code
!= GEU
)))
6526 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
6527 && INTVAL (XEXP (op0
, 1)) >= 0
6528 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_INT
6529 && XEXP (op0
, 1) == XEXP (op1
, 1))
6531 enum machine_mode mode
= GET_MODE (op0
);
6532 unsigned mask
= GET_MODE_MASK (mode
);
6533 int shift_count
= INTVAL (XEXP (op0
, 1));
6535 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
6536 mask
&= (mask
>> shift_count
) << shift_count
;
6537 else if (GET_CODE (op0
) == ASHIFT
|| GET_CODE (op0
) == LSHIFT
)
6538 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
6540 if ((significant_bits (XEXP (op0
, 0), mode
) & ~ mask
) == 0
6541 && (significant_bits (XEXP (op1
, 0), mode
) & ~ mask
) == 0)
6542 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
6547 /* If both operands are AND's of a paradoxical SUBREG by constant, the
6548 SUBREGs are of the same mode, and, in both cases, the AND would
6549 be redundant if the comparison was done in the narrower mode,
6550 do the comparison in the narrower mode (e.g., we are AND'ing with 1
6551 and the operand's significant bits are 0xffffff01; in that case if
6552 we only care about QImode, we don't need the AND). This case occurs
6553 if the output mode of an scc insn is not SImode and
6554 STORE_FLAG_VALUE == 1 (e.g., the 386). */
6556 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
6557 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
6558 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
6559 && GET_CODE (XEXP (op0
, 0)) == SUBREG
6560 && GET_CODE (XEXP (op1
, 0)) == SUBREG
6561 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
6562 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
6563 && (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))
6564 == GET_MODE (SUBREG_REG (XEXP (op1
, 0))))
6565 && (significant_bits (SUBREG_REG (XEXP (op0
, 0)),
6566 GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
6567 & ~ INTVAL (XEXP (op0
, 1))) == 0
6568 && (significant_bits (SUBREG_REG (XEXP (op1
, 0)),
6569 GET_MODE (SUBREG_REG (XEXP (op1
, 0))))
6570 & ~ INTVAL (XEXP (op1
, 1))) == 0)
6572 op0
= SUBREG_REG (XEXP (op0
, 0));
6573 op1
= SUBREG_REG (XEXP (op1
, 0));
6575 /* the resulting comparison is always unsigned since we masked off
6576 the original sign bit. */
6577 code
= unsigned_condition (code
);
6583 /* If the first operand is a constant, swap the operands and adjust the
6584 comparison code appropriately. */
6585 if (CONSTANT_P (op0
))
6587 tem
= op0
, op0
= op1
, op1
= tem
;
6588 code
= swap_condition (code
);
6591 /* We now enter a loop during which we will try to simplify the comparison.
6592 For the most part, we only are concerned with comparisons with zero,
6593 but some things may really be comparisons with zero but not start
6594 out looking that way. */
6596 while (GET_CODE (op1
) == CONST_INT
)
6598 enum machine_mode mode
= GET_MODE (op0
);
6599 int mode_width
= GET_MODE_BITSIZE (mode
);
6600 unsigned mask
= GET_MODE_MASK (mode
);
6601 int equality_comparison_p
;
6602 int sign_bit_comparison_p
;
6603 int unsigned_comparison_p
;
6606 /* We only want to handle integral modes. This catches VOIDmode,
6607 CCmode, and the floating-point modes. An exception is that we
6608 can handle VOIDmode if OP0 is a COMPARE or a comparison
6611 if (GET_MODE_CLASS (mode
) != MODE_INT
6612 && ! (mode
== VOIDmode
6613 && (GET_CODE (op0
) == COMPARE
6614 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
6617 /* Get the constant we are comparing against and turn off all bits
6618 not on in our mode. */
6619 const_op
= INTVAL (op1
);
6620 if (mode_width
<= HOST_BITS_PER_INT
)
6623 /* If we are comparing against a constant power of two and the value
6624 being compared has only that single significant bit (e.g., it was
6625 `and'ed with that bit), we can replace this with a comparison
6628 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
6629 || code
== LT
|| code
== LTU
)
6630 && mode_width
<= HOST_BITS_PER_INT
6631 && exact_log2 (const_op
) >= 0
6632 && significant_bits (op0
, mode
) == const_op
)
6634 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
6635 op1
= const0_rtx
, const_op
= 0;
6638 /* Do some canonicalizations based on the comparison code. We prefer
6639 comparisons against zero and then prefer equality comparisons.
6640 If we can reduce the size of a constant, we will do that too. */
6645 /* < C is equivalent to <= (C - 1) */
6649 op1
= gen_rtx (CONST_INT
, VOIDmode
, const_op
);
6651 /* ... fall through to LE case below. */
6657 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
6661 op1
= gen_rtx (CONST_INT
, VOIDmode
, const_op
);
6665 /* If we are doing a <= 0 comparison on a value known to have
6666 a zero sign bit, we can replace this with == 0. */
6667 else if (const_op
== 0
6668 && mode_width
<= HOST_BITS_PER_INT
6669 && (significant_bits (op0
, mode
)
6670 & (1 << (mode_width
- 1))) == 0)
6675 /* >= C is equivalent to > (C - 1). */
6679 op1
= gen_rtx (CONST_INT
, VOIDmode
, const_op
);
6681 /* ... fall through to GT below. */
6687 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
6691 op1
= gen_rtx (CONST_INT
, VOIDmode
, const_op
);
6695 /* If we are doing a > 0 comparison on a value known to have
6696 a zero sign bit, we can replace this with != 0. */
6697 else if (const_op
== 0
6698 && mode_width
<= HOST_BITS_PER_INT
6699 && (significant_bits (op0
, mode
)
6700 & (1 << (mode_width
- 1))) == 0)
6705 /* < C is equivalent to <= (C - 1). */
6709 op1
= gen_rtx (CONST_INT
, VOIDmode
, const_op
);
6711 /* ... fall through ... */
6717 /* unsigned <= 0 is equivalent to == 0 */
6723 /* >= C is equivalent to < (C - 1). */
6727 op1
= gen_rtx (CONST_INT
, VOIDmode
, const_op
);
6729 /* ... fall through ... */
6735 /* unsigned > 0 is equivalent to != 0 */
6741 /* Compute some predicates to simplify code below. */
6743 equality_comparison_p
= (code
== EQ
|| code
== NE
);
6744 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
6745 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
6748 /* Now try cases based on the opcode of OP0. If none of the cases
6749 does a "continue", we exit this loop immediately after the
6752 switch (GET_CODE (op0
))
6755 /* If we are extracting a single bit from a variable position in
6756 a constant that has only a single bit set and are comparing it
6757 with zero, we can convert this into an equality comparison
6758 between the position and the location of the single bit. We can't
6759 do this if bit endian and we don't have an extzv since we then
6760 can't know what mode to use for the endianness adjustment. */
6762 #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv)
6763 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
6764 && XEXP (op0
, 1) == const1_rtx
6765 && equality_comparison_p
&& const_op
== 0
6766 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
6769 i
= (GET_MODE_BITSIZE
6770 (insn_operand_mode
[(int) CODE_FOR_extzv
][1]) - 1 - i
);
6773 op0
= XEXP (op0
, 2);
6774 op1
= gen_rtx (CONST_INT
, VOIDmode
, i
);
6777 /* Result is nonzero iff shift count is equal to I. */
6778 code
= reverse_condition (code
);
6783 /* ... fall through ... */
6786 tem
= expand_compound_operation (op0
);
6795 /* If testing for equality, we can take the NOT of the constant. */
6796 if (equality_comparison_p
6797 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
6799 op0
= XEXP (op0
, 0);
6804 /* If just looking at the sign bit, reverse the sense of the
6806 if (sign_bit_comparison_p
)
6808 op0
= XEXP (op0
, 0);
6809 code
= (code
== GE
? LT
: GE
);
6815 /* If testing for equality, we can take the NEG of the constant. */
6816 if (equality_comparison_p
6817 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
6819 op0
= XEXP (op0
, 0);
6824 /* The remaining cases only apply to comparisons with zero. */
6828 /* When X is ABS or is known positive,
6829 (neg X) is < 0 if and only if X != 0. */
6831 if (sign_bit_comparison_p
6832 && (GET_CODE (XEXP (op0
, 0)) == ABS
6833 || (mode_width
<= HOST_BITS_PER_INT
6834 && (significant_bits (XEXP (op0
, 0), mode
)
6835 & (1 << (mode_width
- 1))) == 0)))
6837 op0
= XEXP (op0
, 0);
6838 code
= (code
== LT
? NE
: EQ
);
6842 /* If we have NEG of something that is the result of a
6843 SIGN_EXTEND, SIGN_EXTRACT, or ASHIFTRT, we know that the
6844 two high-order bits must be the same and hence that
6845 "(-a) < 0" is equivalent to "a > 0". Otherwise, we can't
6847 if (GET_CODE (XEXP (op0
, 0)) == SIGN_EXTEND
6848 || (GET_CODE (XEXP (op0
, 0)) == SIGN_EXTRACT
6849 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
6850 && (INTVAL (XEXP (XEXP (op0
, 0), 1))
6851 < GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (op0
, 0), 0)))))
6852 || (GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
6853 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
6854 && XEXP (XEXP (op0
, 0), 1) != const0_rtx
)
6855 || ((tem
= get_last_value (XEXP (op0
, 0))) != 0
6856 && (GET_CODE (tem
) == SIGN_EXTEND
6857 || (GET_CODE (tem
) == SIGN_EXTRACT
6858 && GET_CODE (XEXP (tem
, 1)) == CONST_INT
6859 && (INTVAL (XEXP (tem
, 1))
6860 < GET_MODE_BITSIZE (GET_MODE (XEXP (tem
, 0)))))
6861 || (GET_CODE (tem
) == ASHIFTRT
6862 && GET_CODE (XEXP (tem
, 1)) == CONST_INT
6863 && XEXP (tem
, 1) != const0_rtx
))))
6865 op0
= XEXP (op0
, 0);
6866 code
= swap_condition (code
);
6872 /* If we are testing equality and our count is a constant, we
6873 can perform the inverse operation on our RHS. */
6874 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
6875 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
6876 op1
, XEXP (op0
, 1))) != 0)
6878 op0
= XEXP (op0
, 0);
6883 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
6884 a particular bit. Convert it to an AND of a constant of that
6885 bit. This will be converted into a ZERO_EXTRACT. */
6886 if (const_op
== 0 && sign_bit_comparison_p
6887 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
6888 && mode_width
<= HOST_BITS_PER_INT
)
6890 op0
= simplify_and_const_int (0, mode
, XEXP (op0
, 0),
6891 1 << (mode_width
- 1
6892 - INTVAL (XEXP (op0
, 1))));
6893 code
= (code
== LT
? NE
: EQ
);
6897 /* ... fall through ... */
6900 /* ABS is ignorable inside an equality comparison with zero. */
6901 if (const_op
== 0 && equality_comparison_p
)
6903 op0
= XEXP (op0
, 0);
6910 /* Can simplify (compare (zero/sign_extend FOO) CONST)
6911 to (compare FOO CONST) if CONST fits in FOO's mode and we
6912 are either testing inequality or have an unsigned comparison
6913 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
6914 if (! unsigned_comparison_p
6915 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
6916 <= HOST_BITS_PER_INT
)
6917 && ((unsigned) const_op
6918 < (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1))))
6920 op0
= XEXP (op0
, 0);
6926 /* If the inner mode is smaller and we are extracting the low
6927 part, we can treat the SUBREG as if it were a ZERO_EXTEND. */
6928 if (! subreg_lowpart_p (op0
)
6929 || GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) >= mode_width
)
6932 /* ... fall through ... */
6935 if ((unsigned_comparison_p
|| equality_comparison_p
)
6936 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
6937 <= HOST_BITS_PER_INT
)
6938 && ((unsigned) const_op
6939 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
6941 op0
= XEXP (op0
, 0);
6947 /* (eq (plus X C1) C2) -> (eq X (minus C2 C1)). We can only do
6948 this for equality comparisons due to pathological cases involving
6950 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
6951 && (tem
= simplify_binary_operation (MINUS
, mode
, op1
,
6952 XEXP (op0
, 1))) != 0)
6954 op0
= XEXP (op0
, 0);
6959 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
6960 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
6961 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
6963 op0
= XEXP (XEXP (op0
, 0), 0);
6964 code
= (code
== LT
? EQ
: NE
);
6970 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
6971 of bits in X minus 1, is one iff X > 0. */
6972 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
6973 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
6974 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
6975 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
6977 op0
= XEXP (op0
, 1);
6978 code
= (code
== GE
? LE
: GT
);
6984 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
6985 if C is zero or B is a constant. */
6986 if (equality_comparison_p
6987 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
6988 XEXP (op0
, 1), op1
)))
6990 op0
= XEXP (op0
, 0);
6997 case LT
: case LTU
: case LE
: case LEU
:
6998 case GT
: case GTU
: case GE
: case GEU
:
6999 /* We can't do anything if OP0 is a condition code value, rather
7000 than an actual data value. */
7003 || XEXP (op0
, 0) == cc0_rtx
7005 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
7008 /* Get the two operands being compared. */
7009 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
7010 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
7012 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
7014 /* Check for the cases where we simply want the result of the
7015 earlier test or the opposite of that result. */
7017 || (code
== EQ
&& reversible_comparison_p (op0
))
7018 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_INT
7019 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
7020 && (STORE_FLAG_VALUE
7021 & (1 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1)))
7023 || (code
== GE
&& reversible_comparison_p (op0
)))))
7025 code
= (code
== LT
|| code
== NE
7026 ? GET_CODE (op0
) : reverse_condition (GET_CODE (op0
)));
7027 op0
= tem
, op1
= tem1
;
7033 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
7035 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
7036 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
7037 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
7039 op0
= XEXP (op0
, 1);
7040 code
= (code
== GE
? GT
: LE
);
7046 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
7047 will be converted to a ZERO_EXTRACT later. */
7048 if (const_op
== 0 && equality_comparison_p
7049 && (GET_CODE (XEXP (op0
, 0)) == ASHIFT
7050 || GET_CODE (XEXP (op0
, 0)) == LSHIFT
)
7051 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
7053 op0
= simplify_and_const_int
7054 (op0
, mode
, gen_rtx_combine (LSHIFTRT
, mode
,
7056 XEXP (XEXP (op0
, 0), 1)),
7061 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
7062 zero and X is a comparison and C1 and C2 describe only bits set
7063 in STORE_FLAG_VALUE, we can compare with X. */
7064 if (const_op
== 0 && equality_comparison_p
7065 && mode_width
<= HOST_BITS_PER_INT
7066 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
7067 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
7068 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
7069 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
7070 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_INT
)
7072 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
7073 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
7074 if ((~ STORE_FLAG_VALUE
& mask
) == 0
7075 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
7076 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
7077 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
7079 op0
= XEXP (XEXP (op0
, 0), 0);
7084 /* If we are doing an equality comparison of an AND of a bit equal
7085 to the sign bit, replace this with a LT or GE comparison of
7086 the underlying value. */
7087 if (equality_comparison_p
7089 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
7090 && mode_width
<= HOST_BITS_PER_INT
7091 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
7092 == 1 << (mode_width
- 1)))
7094 op0
= XEXP (op0
, 0);
7095 code
= (code
== EQ
? GE
: LT
);
7099 /* If this AND operation is really a ZERO_EXTEND from a narrower
7100 mode, the constant fits within that mode, and this is either an
7101 equality or unsigned comparison, try to do this comparison in
7102 the narrower mode. */
7103 if ((equality_comparison_p
|| unsigned_comparison_p
)
7104 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
7105 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
7106 & GET_MODE_MASK (mode
))
7108 && const_op
>> i
== 0
7109 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
7111 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
7118 /* If we have (compare (xshift FOO N) (const_int C)) and
7119 the high order N bits of FOO (N+1 if an inequality comparison)
7120 are not significant, we can do this by comparing FOO with C
7121 shifted right N bits so long as the low-order N bits of C are
7123 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
7124 && INTVAL (XEXP (op0
, 1)) >= 0
7125 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
7126 < HOST_BITS_PER_INT
)
7127 && (const_op
& ~ ((1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
7128 && mode_width
<= HOST_BITS_PER_INT
7129 && (significant_bits (XEXP (op0
, 0), mode
)
7130 & ~ (mask
>> (INTVAL (XEXP (op0
, 1))
7131 + ! equality_comparison_p
))) == 0)
7133 const_op
>>= INTVAL (XEXP (op0
, 1));
7134 op1
= gen_rtx (CONST_INT
, VOIDmode
, const_op
);
7135 op0
= XEXP (op0
, 0);
7139 /* If we are doing a sign bit comparison, it means we are testing
7140 a particular bit. Convert it to the appropriate AND. */
7141 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
7142 && mode_width
<= HOST_BITS_PER_INT
)
7144 op0
= simplify_and_const_int (0, mode
, XEXP (op0
, 0),
7145 1 << ( mode_width
- 1
7146 - INTVAL (XEXP (op0
, 1))));
7147 code
= (code
== LT
? NE
: EQ
);
7151 /* If this an equality comparison with zero and we are shifting
7152 the low bit to the sign bit, we can convert this to an AND of the
7154 if (const_op
== 0 && equality_comparison_p
7155 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
7156 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
7158 op0
= simplify_and_const_int (0, mode
, XEXP (op0
, 0), 1);
7164 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
7165 do the comparison in a narrower mode. */
7166 if (! unsigned_comparison_p
7167 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
7168 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
7169 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
7170 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
7171 MODE_INT
, 1)) != VOIDmode
7172 && ((unsigned) const_op
<= GET_MODE_MASK (tmode
)
7173 || (unsigned) - const_op
<= GET_MODE_MASK (tmode
)))
7175 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
7179 /* ... fall through ... */
7181 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
7182 the low order N bits of FOO are not significant, we can do this
7183 by comparing FOO with C shifted left N bits so long as no
7185 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
7186 && INTVAL (XEXP (op0
, 1)) >= 0
7187 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_INT
7188 && mode_width
<= HOST_BITS_PER_INT
7189 && (significant_bits (XEXP (op0
, 0), mode
)
7190 & ((1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
7192 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
7195 const_op
<<= INTVAL (XEXP (op0
, 1));
7196 op1
= gen_rtx (CONST_INT
, VOIDmode
, const_op
);
7197 op0
= XEXP (op0
, 0);
7201 /* If we are using this shift to extract just the sign bit, we
7202 can replace this with an LT or GE comparison. */
7204 && (equality_comparison_p
|| sign_bit_comparison_p
)
7205 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
7206 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
7208 op0
= XEXP (op0
, 0);
7209 code
= (code
== NE
|| code
== GT
? LT
: GE
);
7218 /* Now make any compound operations involved in this comparison. Then,
7219 check for an outmost SUBREG on OP0 that isn't doing anything or is
7220 paradoxical. The latter case can only occur when it is known that the
7221 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
7222 We can never remove a SUBREG for a non-equality comparison because the
7223 sign bit is in a different place in the underlying object. */
7225 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
7226 op1
= make_compound_operation (op1
, SET
);
7228 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
7229 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
7230 && (code
== NE
|| code
== EQ
)
7231 && ((GET_MODE_SIZE (GET_MODE (op0
))
7232 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
7234 op0
= SUBREG_REG (op0
);
7235 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
7238 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
7239 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
7240 && (code
== NE
|| code
== EQ
)
7241 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_INT
7242 && (significant_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
7243 & ~ GET_MODE_MASK (GET_MODE (op0
))) == 0
7244 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
7246 (significant_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
7247 & ~ GET_MODE_MASK (GET_MODE (op0
))) == 0))
7248 op0
= SUBREG_REG (op0
), op1
= tem
;
7250 /* We now do the opposite procedure: Some machines don't have compare
7251 insns in all modes. If OP0's mode is an integer mode smaller than a
7252 word and we can't do a compare in that mode, see if there is a larger
7253 mode for which we can do the compare and where the only significant
7254 bits in OP0 and OP1 are those in the narrower mode. We can do
7255 this if this is an equality comparison, in which case we can
7256 merely widen the operation, or if we are testing the sign bit, in
7257 which case we can explicitly put in the test. */
7259 mode
= GET_MODE (op0
);
7260 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
7261 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
7262 && cmp_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
)
7263 for (tmode
= GET_MODE_WIDER_MODE (mode
);
7264 tmode
!= VOIDmode
&& GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_INT
;
7265 tmode
= GET_MODE_WIDER_MODE (tmode
))
7266 if (cmp_optab
->handlers
[(int) tmode
].insn_code
!= CODE_FOR_nothing
7267 && (significant_bits (op0
, tmode
) & ~ GET_MODE_MASK (mode
)) == 0
7268 && (significant_bits (op1
, tmode
) & ~ GET_MODE_MASK (mode
)) == 0
7269 && (code
== EQ
|| code
== NE
7270 || (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
7271 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_INT
)))
7273 op0
= gen_lowpart_for_combine (tmode
, op0
);
7274 op1
= gen_lowpart_for_combine (tmode
, op1
);
7276 if (code
== LT
|| code
== GE
)
7278 op0
= gen_binary (AND
, tmode
, op0
,
7279 gen_rtx (CONST_INT
, VOIDmode
,
7280 1 << (GET_MODE_BITSIZE (mode
) - 1)));
7281 code
= (code
== LT
) ? NE
: EQ
;
7293 /* Return 1 if we know that X, a comparison operation, is not operating
7294 on a floating-point value or is EQ or NE, meaning that we can safely
7298 reversible_comparison_p (x
)
7301 if (TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
7302 || GET_CODE (x
) == NE
|| GET_CODE (x
) == EQ
)
7305 switch (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))))
7311 x
= get_last_value (XEXP (x
, 0));
7312 return (x
&& GET_CODE (x
) == COMPARE
7313 && GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) == MODE_INT
);
7319 /* Utility function for following routine. Called when X is part of a value
7320 being stored into reg_last_set_value. Sets reg_last_set_table_tick
7321 for each register mentioned. Similar to mention_regs in cse.c */
7324 update_table_tick (x
)
7327 register enum rtx_code code
= GET_CODE (x
);
7328 register char *fmt
= GET_RTX_FORMAT (code
);
7333 int regno
= REGNO (x
);
7334 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
7335 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
7337 for (i
= regno
; i
< endregno
; i
++)
7338 reg_last_set_table_tick
[i
] = label_tick
;
7343 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7344 /* Note that we can't have an "E" in values stored; see
7345 get_last_value_validate. */
7347 update_table_tick (XEXP (x
, i
));
7350 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
7351 are saying that the register is clobbered and we no longer know its
7352 value. If INSN is zero, don't update reg_last_set; this call is normally
7353 done with VALUE also zero to invalidate the register. */
7356 record_value_for_reg (reg
, insn
, value
)
7361 int regno
= REGNO (reg
);
7362 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
7363 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
7366 /* If VALUE contains REG and we have a previous value for REG, substitute
7367 the previous value. */
7368 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
7372 /* Set things up so get_last_value is allowed to see anything set up to
7374 subst_low_cuid
= INSN_CUID (insn
);
7375 tem
= get_last_value (reg
);
7378 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
7381 /* For each register modified, show we don't know its value, that
7382 its value has been updated, and that we don't know the location of
7383 the death of the register. */
7384 for (i
= regno
; i
< endregno
; i
++)
7387 reg_last_set
[i
] = insn
;
7388 reg_last_set_value
[i
] = 0;
7389 reg_last_death
[i
] = 0;
7392 /* Mark registers that are being referenced in this value. */
7394 update_table_tick (value
);
7396 /* Now update the status of each register being set.
7397 If someone is using this register in this block, set this register
7398 to invalid since we will get confused between the two lives in this
7399 basic block. This makes using this register always invalid. In cse, we
7400 scan the table to invalidate all entries using this register, but this
7401 is too much work for us. */
7403 for (i
= regno
; i
< endregno
; i
++)
7405 reg_last_set_label
[i
] = label_tick
;
7406 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
7407 reg_last_set_invalid
[i
] = 1;
7409 reg_last_set_invalid
[i
] = 0;
7412 /* The value being assigned might refer to X (like in "x++;"). In that
7413 case, we must replace it with (clobber (const_int 0)) to prevent
7415 if (value
&& ! get_last_value_validate (&value
,
7416 reg_last_set_label
[regno
], 0))
7418 value
= copy_rtx (value
);
7419 if (! get_last_value_validate (&value
, reg_last_set_label
[regno
], 1))
7423 /* For the main register being modified, update the value. */
7424 reg_last_set_value
[regno
] = value
;
7428 /* Used for communication between the following two routines. */
7429 static rtx record_dead_insn
;
7431 /* Called via note_stores from record_dead_and_set_regs to handle one
7432 SET or CLOBBER in an insn. */
7435 record_dead_and_set_regs_1 (dest
, setter
)
7438 if (GET_CODE (dest
) == REG
)
7440 /* If we are setting the whole register, we know its value. Otherwise
7441 show that we don't know the value. We can handle SUBREG in
7443 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
7444 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
7445 else if (GET_CODE (setter
) == SET
7446 && GET_CODE (SET_DEST (setter
)) == SUBREG
7447 && SUBREG_REG (SET_DEST (setter
)) == dest
7448 && subreg_lowpart_p (SET_DEST (setter
)))
7449 record_value_for_reg
7450 (dest
, record_dead_insn
,
7451 gen_lowpart_for_combine (GET_MODE (SET_DEST (setter
)),
7454 record_value_for_reg (dest
, record_dead_insn
, 0);
7456 else if (GET_CODE (dest
) == MEM
7457 /* Ignore pushes, they clobber nothing. */
7458 && ! push_operand (dest
, GET_MODE (dest
)))
7459 mem_last_set
= INSN_CUID (record_dead_insn
);
7462 /* Update the records of when each REG was most recently set or killed
7463 for the things done by INSN. This is the last thing done in processing
7464 INSN in the combiner loop.
7466 We update reg_last_set, reg_last_set_value, reg_last_death, and also the
7467 similar information mem_last_set (which insn most recently modified memory)
7468 and last_call_cuid (which insn was the most recent subroutine call). */
7471 record_dead_and_set_regs (insn
)
7475 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
7477 if (REG_NOTE_KIND (link
) == REG_DEAD
)
7478 reg_last_death
[REGNO (XEXP (link
, 0))] = insn
;
7479 else if (REG_NOTE_KIND (link
) == REG_INC
)
7480 record_value_for_reg (XEXP (link
, 0), insn
, 0);
7483 if (GET_CODE (insn
) == CALL_INSN
)
7484 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
7486 record_dead_insn
= insn
;
7487 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
);
7490 /* Utility routine for the following function. Verify that all the registers
7491 mentioned in *LOC are valid when *LOC was part of a value set when
7492 label_tick == TICK. Return 0 if some are not.
7494 If REPLACE is non-zero, replace the invalid reference with
7495 (clobber (const_int 0)) and return 1. This replacement is useful because
7496 we often can get useful information about the form of a value (e.g., if
7497 it was produced by a shift that always produces -1 or 0) even though
7498 we don't know exactly what registers it was produced from. */
7501 get_last_value_validate (loc
, tick
, replace
)
7507 char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
7508 int len
= GET_RTX_LENGTH (GET_CODE (x
));
7511 if (GET_CODE (x
) == REG
)
7513 int regno
= REGNO (x
);
7514 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
7515 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
7518 for (j
= regno
; j
< endregno
; j
++)
7519 if (reg_last_set_invalid
[j
]
7520 /* If this is a pseudo-register that was only set once, it is
7522 || (! (regno
>= FIRST_PSEUDO_REGISTER
&& reg_n_sets
[regno
] == 1)
7523 && reg_last_set_label
[j
] > tick
))
7526 *loc
= gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
7533 for (i
= 0; i
< len
; i
++)
7535 && get_last_value_validate (&XEXP (x
, i
), tick
, replace
) == 0)
7536 /* Don't bother with these. They shouldn't occur anyway. */
7540 /* If we haven't found a reason for it to be invalid, it is valid. */
7544 /* Get the last value assigned to X, if known. Some registers
7545 in the value may be replaced with (clobber (const_int 0)) if their value
7546 is known longer known reliably. */
7555 /* If this is a non-paradoxical SUBREG, get the value of its operand and
7556 then convert it to the desired mode. If this is a paradoxical SUBREG,
7557 we cannot predict what values the "extra" bits might have. */
7558 if (GET_CODE (x
) == SUBREG
7559 && subreg_lowpart_p (x
)
7560 && (GET_MODE_SIZE (GET_MODE (x
))
7561 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
7562 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
7563 return gen_lowpart_for_combine (GET_MODE (x
), value
);
7565 if (GET_CODE (x
) != REG
)
7569 value
= reg_last_set_value
[regno
];
7571 /* If we don't have a value, it isn't for this basic block, or if it was
7572 set in a later insn that the ones we are processing, return 0. */
7575 || (reg_n_sets
[regno
] != 1
7576 && (reg_last_set_label
[regno
] != label_tick
7577 || INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)))
7580 /* If the value has all its register valid, return it. */
7581 if (get_last_value_validate (&value
, reg_last_set_label
[regno
], 0))
7584 /* Otherwise, make a copy and replace any invalid register with
7585 (clobber (const_int 0)). If that fails for some reason, return 0. */
7587 value
= copy_rtx (value
);
7588 if (get_last_value_validate (&value
, reg_last_set_label
[regno
], 1))
7594 /* Return nonzero if expression X refers to a REG or to memory
7595 that is set in an instruction more recent than FROM_CUID. */
7598 use_crosses_set_p (x
, from_cuid
)
7604 register enum rtx_code code
= GET_CODE (x
);
7608 register int regno
= REGNO (x
);
7609 #ifdef PUSH_ROUNDING
7610 /* Don't allow uses of the stack pointer to be moved,
7611 because we don't know whether the move crosses a push insn. */
7612 if (regno
== STACK_POINTER_REGNUM
)
7615 return (reg_last_set
[regno
]
7616 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
);
7619 if (code
== MEM
&& mem_last_set
> from_cuid
)
7622 fmt
= GET_RTX_FORMAT (code
);
7624 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7629 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7630 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
7633 else if (fmt
[i
] == 'e'
7634 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
7640 /* Define three variables used for communication between the following
7643 static int reg_dead_regno
, reg_dead_endregno
;
7644 static int reg_dead_flag
;
7646 /* Function called via note_stores from reg_dead_at_p.
7648 If DEST is within [reg_dead_rengno, reg_dead_endregno), set
7649 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
7652 reg_dead_at_p_1 (dest
, x
)
7656 int regno
, endregno
;
7658 if (GET_CODE (dest
) != REG
)
7661 regno
= REGNO (dest
);
7662 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
7663 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
7665 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
7666 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
7669 /* Return non-zero if REG is known to be dead at INSN.
7671 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
7672 referencing REG, it is dead. If we hit a SET referencing REG, it is
7673 live. Otherwise, see if it is live or dead at the start of the basic
7677 reg_dead_at_p (reg
, insn
)
7683 /* Set variables for reg_dead_at_p_1. */
7684 reg_dead_regno
= REGNO (reg
);
7685 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
7686 ? HARD_REGNO_NREGS (reg_dead_regno
,
7692 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
7693 beginning of function. */
7694 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
;
7695 insn
= prev_nonnote_insn (insn
))
7697 note_stores (PATTERN (insn
), reg_dead_at_p_1
);
7699 return reg_dead_flag
== 1 ? 1 : 0;
7701 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
7705 /* Get the basic block number that we were in. */
7710 for (block
= 0; block
< n_basic_blocks
; block
++)
7711 if (insn
== basic_block_head
[block
])
7714 if (block
== n_basic_blocks
)
7718 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
7719 if (basic_block_live_at_start
[block
][i
/ HOST_BITS_PER_INT
]
7720 & (1 << (i
% HOST_BITS_PER_INT
)))
7726 /* Remove register number REGNO from the dead registers list of INSN.
7728 Return the note used to record the death, if there was one. */
7731 remove_death (regno
, insn
)
7735 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
7738 remove_note (insn
, note
);
7743 /* For each register (hardware or pseudo) used within expression X, if its
7744 death is in an instruction with cuid between FROM_CUID (inclusive) and
7745 TO_INSN (exclusive), put a REG_DEAD note for that register in the
7746 list headed by PNOTES.
7748 This is done when X is being merged by combination into TO_INSN. These
7749 notes will then be distributed as needed. */
7752 move_deaths (x
, from_cuid
, to_insn
, pnotes
)
7759 register int len
, i
;
7760 register enum rtx_code code
= GET_CODE (x
);
7764 register int regno
= REGNO (x
);
7765 register rtx where_dead
= reg_last_death
[regno
];
7767 if (where_dead
&& INSN_CUID (where_dead
) >= from_cuid
7768 && INSN_CUID (where_dead
) < INSN_CUID (to_insn
))
7770 rtx note
= remove_death (regno
, reg_last_death
[regno
]);
7772 /* It is possible for the call above to return 0. This can occur
7773 when reg_last_death points to I2 or I1 that we combined with.
7774 In that case make a new note. */
7778 XEXP (note
, 1) = *pnotes
;
7782 *pnotes
= gen_rtx (EXPR_LIST
, REG_DEAD
, x
, *pnotes
);
7788 else if (GET_CODE (x
) == SET
)
7790 rtx dest
= SET_DEST (x
);
7792 move_deaths (SET_SRC (x
), from_cuid
, to_insn
, pnotes
);
7794 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
7795 that accesses one word of a multi-word item, some
7796 piece of everything register in the expression is used by
7797 this insn, so remove any old death. */
7799 if (GET_CODE (dest
) == ZERO_EXTRACT
7800 || GET_CODE (dest
) == STRICT_LOW_PART
7801 || (GET_CODE (dest
) == SUBREG
7802 && (((GET_MODE_SIZE (GET_MODE (dest
))
7803 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
7804 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
7805 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
7807 move_deaths (dest
, from_cuid
, to_insn
, pnotes
);
7811 /* If this is some other SUBREG, we know it replaces the entire
7812 value, so use that as the destination. */
7813 if (GET_CODE (dest
) == SUBREG
)
7814 dest
= SUBREG_REG (dest
);
7816 /* If this is a MEM, adjust deaths of anything used in the address.
7817 For a REG (the only other possibility), the entire value is
7818 being replaced so the old value is not used in this insn. */
7820 if (GET_CODE (dest
) == MEM
)
7821 move_deaths (XEXP (dest
, 0), from_cuid
, to_insn
, pnotes
);
7825 else if (GET_CODE (x
) == CLOBBER
)
7828 len
= GET_RTX_LENGTH (code
);
7829 fmt
= GET_RTX_FORMAT (code
);
7831 for (i
= 0; i
< len
; i
++)
7836 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7837 move_deaths (XVECEXP (x
, i
, j
), from_cuid
, to_insn
, pnotes
);
7839 else if (fmt
[i
] == 'e')
7840 move_deaths (XEXP (x
, i
), from_cuid
, to_insn
, pnotes
);
7844 /* Return 1 if X is the target of a bit-field assignment in BODY, the
7845 pattern of an insn. X must be a REG. */
7848 reg_bitfield_target_p (x
, body
)
7854 if (GET_CODE (body
) == SET
)
7856 rtx dest
= SET_DEST (body
);
7858 int regno
, tregno
, endregno
, endtregno
;
7860 if (GET_CODE (dest
) == ZERO_EXTRACT
)
7861 target
= XEXP (dest
, 0);
7862 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
7863 target
= SUBREG_REG (XEXP (dest
, 0));
7867 if (GET_CODE (target
) == SUBREG
)
7868 target
= SUBREG_REG (target
);
7870 if (GET_CODE (target
) != REG
)
7873 tregno
= REGNO (target
), regno
= REGNO (x
);
7874 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
7877 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
7878 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
7880 return endregno
> tregno
&& regno
< endtregno
;
7883 else if (GET_CODE (body
) == PARALLEL
)
7884 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
7885 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
7891 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
7892 as appropriate. I3 and I2 are the insns resulting from the combination
7893 insns including FROM (I2 may be zero).
7895 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
7896 not need REG_DEAD notes because they are being substituted for. This
7897 saves searching in the most common cases.
7899 Each note in the list is either ignored or placed on some insns, depending
7900 on the type of note. */
7903 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
7907 rtx elim_i2
, elim_i1
;
7909 rtx note
, next_note
;
7912 for (note
= notes
; note
; note
= next_note
)
7914 rtx place
= 0, place2
= 0;
7916 /* If this NOTE references a pseudo register, ensure it references
7917 the latest copy of that register. */
7918 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
7919 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
7920 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
7922 next_note
= XEXP (note
, 1);
7923 switch (REG_NOTE_KIND (note
))
7926 /* If this register is set or clobbered in I3, put the note there
7927 unless there is one already. */
7928 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
7930 if (! (GET_CODE (XEXP (note
, 0)) == REG
7931 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
7932 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
7935 /* Otherwise, if this register is used by I3, then this register
7936 now dies here, so we must put a REG_DEAD note here unless there
7938 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
7939 && ! (GET_CODE (XEXP (note
, 0)) == REG
7940 ? find_regno_note (i3
, REG_DEAD
, REGNO (XEXP (note
, 0)))
7941 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
7943 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
7951 /* These notes say something about results of an insn. We can
7952 only support them if they used to be on I3 in which case they
7953 remain on I3. Otherwise they are ignored. */
7954 if (from_insn
== i3
)
7959 case REG_NO_CONFLICT
:
7961 /* These notes say something about how a register is used. They must
7962 be present on any use of the register in I2 or I3. */
7963 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
7966 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
7976 /* It is too much trouble to try to see if this note is still
7977 correct in all situations. It is better to simply delete it. */
7981 /* If the insn previously containing this note still exists,
7982 put it back where it was. Otherwise move it to the previous
7983 insn. Adjust the corresponding REG_LIBCALL note. */
7984 if (GET_CODE (from_insn
) != NOTE
)
7988 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, 0);
7989 place
= prev_real_insn (from_insn
);
7991 XEXP (tem
, 0) = place
;
7996 /* This is handled similarly to REG_RETVAL. */
7997 if (GET_CODE (from_insn
) != NOTE
)
8001 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, 0);
8002 place
= next_real_insn (from_insn
);
8004 XEXP (tem
, 0) = place
;
8009 /* If the register is used as an input in I3, it dies there.
8010 Similarly for I2, if it is non-zero and adjacent to I3.
8012 If the register is not used as an input in either I3 or I2
8013 and it is not one of the registers we were supposed to eliminate,
8014 there are two possibilities. We might have a non-adjacent I2
8015 or we might have somehow eliminated an additional register
8016 from a computation. For example, we might have had A & B where
8017 we discover that B will always be zero. In this case we will
8018 eliminate the reference to A.
8020 In both cases, we must search to see if we can find a previous
8021 use of A and put the death note there. */
8023 if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
8025 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
8026 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
8029 if (XEXP (note
, 0) == elim_i2
|| XEXP (note
, 0) == elim_i1
)
8033 for (tem
= prev_nonnote_insn (i3
);
8034 tem
&& (GET_CODE (tem
) == INSN
8035 || GET_CODE (tem
) == CALL_INSN
);
8036 tem
= prev_nonnote_insn (tem
))
8038 /* If the register is being set at TEM, see if that is all
8039 TEM is doing. If so, delete TEM. Otherwise, make this
8040 into a REG_UNUSED note instead. */
8041 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
8043 rtx set
= single_set (tem
);
8045 /* Verify that it was the set, and not a clobber that
8046 modified the register. */
8048 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
8049 && rtx_equal_p (XEXP (note
, 0), SET_DEST (set
)))
8051 /* Move the notes and links of TEM elsewhere.
8052 This might delete other dead insns recursively.
8053 First set the pattern to something that won't use
8056 PATTERN (tem
) = pc_rtx
;
8058 distribute_notes (REG_NOTES (tem
), tem
, tem
, 0, 0, 0);
8059 distribute_links (LOG_LINKS (tem
));
8061 PUT_CODE (tem
, NOTE
);
8062 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
8063 NOTE_SOURCE_FILE (tem
) = 0;
8067 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
8069 /* If there isn't already a REG_UNUSED note, put one
8071 if (! find_regno_note (tem
, REG_UNUSED
,
8072 REGNO (XEXP (note
, 0))))
8077 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
)))
8084 /* If the register is set or already dead at PLACE, we needn't do
8085 anything with this note if it is still a REG_DEAD note.
8087 Note that we cannot use just `dead_or_set_p' here since we can
8088 convert an assignment to a register into a bit-field assignment.
8089 Therefore, we must also omit the note if the register is the
8090 target of a bitfield assignment. */
8092 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
8094 int regno
= REGNO (XEXP (note
, 0));
8096 if (dead_or_set_p (place
, XEXP (note
, 0))
8097 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
8099 /* Unless the register previously died in PLACE, clear
8100 reg_last_death. [I no longer understand why this is
8102 if (reg_last_death
[regno
] != place
)
8103 reg_last_death
[regno
] = 0;
8107 reg_last_death
[regno
] = place
;
8109 /* If this is a death note for a hard reg that is occupying
8110 multiple registers, ensure that we are still using all
8111 parts of the object. If we find a piece of the object
8112 that is unused, we must add a USE for that piece before
8113 PLACE and put the appropriate REG_DEAD note on it.
8115 An alternative would be to put a REG_UNUSED for the pieces
8116 on the insn that set the register, but that can't be done if
8117 it is not in the same block. It is simpler, though less
8118 efficient, to add the USE insns. */
8120 if (place
&& regno
< FIRST_PSEUDO_REGISTER
8121 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
8124 = regno
+ HARD_REGNO_NREGS (regno
,
8125 GET_MODE (XEXP (note
, 0)));
8129 for (i
= regno
; i
< endregno
; i
++)
8130 if (! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0))
8132 rtx piece
= gen_rtx (REG
, word_mode
, i
);
8135 /* See if we already placed a USE note for this
8136 register in front of PLACE. */
8138 GET_CODE (PREV_INSN (p
)) == INSN
8139 && GET_CODE (PATTERN (PREV_INSN (p
))) == USE
;
8141 if (rtx_equal_p (piece
,
8142 XEXP (PATTERN (PREV_INSN (p
)), 0)))
8151 = emit_insn_before (gen_rtx (USE
, VOIDmode
,
8154 REG_NOTES (use_insn
)
8155 = gen_rtx (EXPR_LIST
, REG_DEAD
, piece
,
8156 REG_NOTES (use_insn
));
8164 /* Put only REG_DEAD notes for pieces that are
8165 still used and that are not already dead or set. */
8167 for (i
= regno
; i
< endregno
; i
++)
8169 rtx piece
= gen_rtx (REG
, word_mode
, i
);
8171 if (reg_referenced_p (piece
, PATTERN (place
))
8172 && ! dead_or_set_p (place
, piece
)
8173 && ! reg_bitfield_target_p (piece
,
8175 REG_NOTES (place
) = gen_rtx (EXPR_LIST
, REG_DEAD
,
8187 /* Any other notes should not be present at this point in the
8194 XEXP (note
, 1) = REG_NOTES (place
);
8195 REG_NOTES (place
) = note
;
8199 REG_NOTES (place2
) = gen_rtx (GET_CODE (note
), REG_NOTE_KIND (note
),
8200 XEXP (note
, 0), REG_NOTES (place2
));
8204 /* Similarly to above, distribute the LOG_LINKS that used to be present on
8205 I3, I2, and I1 to new locations. This is also called in one case to
8206 add a link pointing at I3 when I3's destination is changed. */
8209 distribute_links (links
)
8212 rtx link
, next_link
;
8214 for (link
= links
; link
; link
= next_link
)
8220 next_link
= XEXP (link
, 1);
8222 /* If the insn that this link points to is a NOTE or isn't a single
8223 set, ignore it. In the latter case, it isn't clear what we
8224 can do other than ignore the link, since we can't tell which
8225 register it was for. Such links wouldn't be used by combine
8228 It is not possible for the destination of the target of the link to
8229 have been changed by combine. The only potential of this is if we
8230 replace I3, I2, and I1 by I3 and I2. But in that case the
8231 destination of I2 also remains unchanged. */
8233 if (GET_CODE (XEXP (link
, 0)) == NOTE
8234 || (set
= single_set (XEXP (link
, 0))) == 0)
8237 reg
= SET_DEST (set
);
8238 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
8239 || GET_CODE (reg
) == SIGN_EXTRACT
8240 || GET_CODE (reg
) == STRICT_LOW_PART
)
8241 reg
= XEXP (reg
, 0);
8243 /* A LOG_LINK is defined as being placed on the first insn that uses
8244 a register and points to the insn that sets the register. Start
8245 searching at the next insn after the target of the link and stop
8246 when we reach a set of the register or the end of the basic block.
8248 Note that this correctly handles the link that used to point from
8249 I3 to I2. Also note that not much searching is typically done here
8250 since most links don't point very far away. */
8252 for (insn
= NEXT_INSN (XEXP (link
, 0));
8253 (insn
&& GET_CODE (insn
) != CODE_LABEL
8254 && GET_CODE (PREV_INSN (insn
)) != JUMP_INSN
);
8255 insn
= NEXT_INSN (insn
))
8256 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
8257 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
8259 if (reg_referenced_p (reg
, PATTERN (insn
)))
8264 /* If we found a place to put the link, place it there unless there
8265 is already a link to the same insn as LINK at that point. */
8271 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
8272 if (XEXP (link2
, 0) == XEXP (link
, 0))
8277 XEXP (link
, 1) = LOG_LINKS (place
);
8278 LOG_LINKS (place
) = link
;
8285 dump_combine_stats (file
)
8290 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
8291 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
8295 dump_combine_total_stats (file
)
8300 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
8301 total_attempts
, total_merges
, total_extras
, total_successes
);