1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This module is essentially the "combiner" phase of the U. of Arizona
22 Portable Optimizer, but redone to work on our list-structured
23 representation for RTL instead of their string representation.
25 The LOG_LINKS of each insn identify the most recent assignment
26 to each REG used in the insn. It is a list of previous insns,
27 each of which contains a SET for a REG that is used in this insn
28 and not used or set in between. LOG_LINKs never cross basic blocks.
29 They were set up by the preceding pass (lifetime analysis).
31 We try to combine each pair of insns joined by a logical link.
32 We also try to combine triples of insns A, B and C when
33 C has a link back to B and B has a link back to A.
35 LOG_LINKS does not have links for use of the CC0. They don't
36 need to, because the insn that sets the CC0 is always immediately
37 before the insn that tests it. So we always regard a branch
38 insn as having a logical link to the preceding insn. The same is true
39 for an insn explicitly using CC0.
41 We check (with use_crosses_set_p) to avoid combining in such a way
42 as to move a computation to a place where its value would be different.
44 Combination is done by mathematically substituting the previous
45 insn(s) values for the regs they set into the expressions in
46 the later insns that refer to these regs. If the result is a valid insn
47 for our target machine, according to the machine description,
48 we install it, delete the earlier insns, and update the data flow
49 information (LOG_LINKS and REG_NOTES) for what we did.
51 There are a few exceptions where the dataflow information created by
52 flow.c aren't completely updated:
54 - reg_live_length is not updated
55 - reg_n_refs is not adjusted in the rare case when a register is
56 no longer required in a computation
57 - there are extremely rare cases (see distribute_regnotes) when a
59 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
60 removed because there is no way to know which register it was
63 To simplify substitution, we combine only when the earlier insn(s)
64 consist of only a single assignment. To simplify updating afterward,
65 we never combine when a subroutine call appears in the middle.
67 Since we do not represent assignments to CC0 explicitly except when that
68 is all an insn does, there is no LOG_LINKS entry in an insn that uses
69 the condition code for the insn that set the condition code.
70 Fortunately, these two insns must be consecutive.
71 Therefore, every JUMP_INSN is taken to have an implicit logical link
72 to the preceding insn. This is not quite right, since non-jumps can
73 also use the condition code; but in practice such insns would not
84 #include "basic-block.h"
85 #include "insn-config.h"
86 #include "insn-flags.h"
87 #include "insn-codes.h"
88 #include "insn-attr.h"
92 /* It is not safe to use ordinary gen_lowpart in combine.
93 Use gen_lowpart_for_combine instead. See comments there. */
94 #define gen_lowpart dont_use_gen_lowpart_you_dummy
96 /* Number of attempts to combine instructions in this function. */
98 static int combine_attempts
;
100 /* Number of attempts that got as far as substitution in this function. */
102 static int combine_merges
;
104 /* Number of instructions combined with added SETs in this function. */
106 static int combine_extras
;
108 /* Number of instructions combined in this function. */
110 static int combine_successes
;
112 /* Totals over entire compilation. */
114 static int total_attempts
, total_merges
, total_extras
, total_successes
;
116 /* Vector mapping INSN_UIDs to cuids.
117 The cuids are like uids but increase monotonically always.
118 Combine always uses cuids so that it can compare them.
119 But actually renumbering the uids, which we used to do,
120 proves to be a bad idea because it makes it hard to compare
121 the dumps produced by earlier passes with those from later passes. */
123 static int *uid_cuid
;
125 /* Get the cuid of an insn. */
127 #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
129 /* Maximum register number, which is the size of the tables below. */
131 static int combine_max_regno
;
133 /* Record last point of death of (hard or pseudo) register n. */
135 static rtx
*reg_last_death
;
137 /* Record last point of modification of (hard or pseudo) register n. */
139 static rtx
*reg_last_set
;
141 /* Record the cuid of the last insn that invalidated memory
142 (anything that writes memory, and subroutine calls, but not pushes). */
144 static int mem_last_set
;
146 /* Record the cuid of the last CALL_INSN
147 so we can tell whether a potential combination crosses any calls. */
149 static int last_call_cuid
;
151 /* When `subst' is called, this is the insn that is being modified
152 (by combining in a previous insn). The PATTERN of this insn
153 is still the old pattern partially modified and it should not be
154 looked at, but this may be used to examine the successors of the insn
155 to judge whether a simplification is valid. */
157 static rtx subst_insn
;
159 /* This is the lowest CUID that `subst' is currently dealing with.
160 get_last_value will not return a value if the register was set at or
161 after this CUID. If not for this mechanism, we could get confused if
162 I2 or I1 in try_combine were an insn that used the old value of a register
163 to obtain a new value. In that case, we might erroneously get the
164 new value of the register when we wanted the old one. */
166 static int subst_low_cuid
;
168 /* This is the value of undobuf.num_undo when we started processing this
169 substitution. This will prevent gen_rtx_combine from re-used a piece
170 from the previous expression. Doing so can produce circular rtl
173 static int previous_num_undos
;
175 /* The next group of arrays allows the recording of the last value assigned
176 to (hard or pseudo) register n. We use this information to see if a
177 operation being processed is redundant given a prior operation performed
178 on the register. For example, an `and' with a constant is redundant if
179 all the zero bits are already known to be turned off.
181 We use an approach similar to that used by cse, but change it in the
184 (1) We do not want to reinitialize at each label.
185 (2) It is useful, but not critical, to know the actual value assigned
186 to a register. Often just its form is helpful.
188 Therefore, we maintain the following arrays:
190 reg_last_set_value the last value assigned
191 reg_last_set_label records the value of label_tick when the
192 register was assigned
193 reg_last_set_table_tick records the value of label_tick when a
194 value using the register is assigned
195 reg_last_set_invalid set to non-zero when it is not valid
196 to use the value of this register in some
199 To understand the usage of these tables, it is important to understand
200 the distinction between the value in reg_last_set_value being valid
201 and the register being validly contained in some other expression in the
204 Entry I in reg_last_set_value is valid if it is non-zero, and either
205 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
207 Register I may validly appear in any expression returned for the value
208 of another register if reg_n_sets[i] is 1. It may also appear in the
209 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
210 reg_last_set_invalid[j] is zero.
212 If an expression is found in the table containing a register which may
213 not validly appear in an expression, the register is replaced by
214 something that won't match, (clobber (const_int 0)).
216 reg_last_set_invalid[i] is set non-zero when register I is being assigned
217 to and reg_last_set_table_tick[i] == label_tick. */
219 /* Record last value assigned to (hard or pseudo) register n. */
221 static rtx
*reg_last_set_value
;
223 /* Record the value of label_tick when the value for register n is placed in
224 reg_last_set_value[n]. */
226 static short *reg_last_set_label
;
228 /* Record the value of label_tick when an expression involving register n
229 is placed in reg_last_set_value. */
231 static short *reg_last_set_table_tick
;
233 /* Set non-zero if references to register n in expressions should not be
236 static char *reg_last_set_invalid
;
238 /* Incremented for each label. */
240 static short label_tick
;
242 /* Some registers that are set more than once and used in more than one
243 basic block are nevertheless always set in similar ways. For example,
244 a QImode register may be loaded from memory in two places on a machine
245 where byte loads zero extend.
247 We record in the following array what we know about the significant
248 bits of a register, specifically which bits are known to be zero.
250 If an entry is zero, it means that we don't know anything special. */
252 static int *reg_significant
;
254 /* Mode used to compute significance in reg_significant. It is the largest
255 integer mode that can fit in HOST_BITS_PER_INT. */
257 static enum machine_mode significant_mode
;
259 /* Nonzero when reg_significant can be safely used. It is zero while
260 computing reg_significant. This prevents propagating values based
261 on previously set values, which can be incorrect if a variable
262 is modified in a loop. */
264 static int significant_valid
;
266 /* Record one modification to rtl structure
267 to be undone by storing old_contents into *where.
268 is_int is 1 if the contents are an int. */
284 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
285 num_undo says how many are currently recorded.
287 storage is nonzero if we must undo the allocation of new storage.
288 The value of storage is what to pass to obfree.
290 other_insn is nonzero if we have modified some other insn in the process
291 of working on subst_insn. It must be verified too. */
299 struct undo undo
[MAX_UNDO
];
303 static struct undobuf undobuf
;
305 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
306 insn. The substitution can be undone by undo_all. If INTO is already
307 set to NEWVAL, do not record this change. Because computing NEWVAL might
308 also call SUBST, we have to compute it before we put anything into
311 #define SUBST(INTO, NEWVAL) \
312 do { rtx _new = (NEWVAL); \
313 if (undobuf.num_undo < MAX_UNDO) \
315 undobuf.undo[undobuf.num_undo].where = &INTO; \
316 undobuf.undo[undobuf.num_undo].old_contents = INTO; \
317 undobuf.undo[undobuf.num_undo].is_int = 0; \
319 if (undobuf.undo[undobuf.num_undo].old_contents != INTO) \
320 undobuf.num_undo++; \
324 /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
326 Note that substitution for the value of a CONST_INT is not safe. */
328 #define SUBST_INT(INTO, NEWVAL) \
329 do { if (undobuf.num_undo < MAX_UNDO) \
332 = (struct undo_int *)&undobuf.undo[undobuf.num_undo]; \
333 u->where = (int *) &INTO; \
334 u->old_contents = INTO; \
337 if (u->old_contents != INTO) \
338 undobuf.num_undo++; \
342 /* Number of times the pseudo being substituted for
343 was found and replaced. */
345 static int n_occurrences
;
347 static void set_significant ();
348 static void move_deaths ();
350 static void record_value_for_reg ();
351 static void record_dead_and_set_regs ();
352 static int use_crosses_set_p ();
353 static rtx
try_combine ();
354 static rtx
*find_split_point ();
356 static void undo_all ();
357 static int reg_dead_at_p ();
358 static rtx
expand_compound_operation ();
359 static rtx
expand_field_assignment ();
360 static rtx
make_extraction ();
361 static int get_pos_from_mask ();
362 static rtx
force_to_mode ();
363 static rtx
make_field_assignment ();
364 static rtx
make_compound_operation ();
365 static rtx
apply_distributive_law ();
366 static rtx
simplify_and_const_int ();
367 static unsigned significant_bits ();
368 static int merge_outer_ops ();
369 static rtx
simplify_shift_const ();
370 static int recog_for_combine ();
371 static rtx
gen_lowpart_for_combine ();
372 static rtx
gen_rtx_combine ();
373 static rtx
gen_binary ();
374 static rtx
gen_unary ();
375 static enum rtx_code
simplify_comparison ();
376 static int reversible_comparison_p ();
377 static int get_last_value_validate ();
378 static rtx
get_last_value ();
379 static void distribute_notes ();
380 static void distribute_links ();
382 /* Main entry point for combiner. F is the first insn of the function.
383 NREGS is the first unused pseudo-reg number. */
386 combine_instructions (f
, nregs
)
390 register rtx insn
, next
, prev
;
392 register rtx links
, nextlinks
;
394 combine_attempts
= 0;
397 combine_successes
= 0;
399 combine_max_regno
= nregs
;
401 reg_last_death
= (rtx
*) alloca (nregs
* sizeof (rtx
));
402 reg_last_set
= (rtx
*) alloca (nregs
* sizeof (rtx
));
403 reg_last_set_value
= (rtx
*) alloca (nregs
* sizeof (rtx
));
404 reg_last_set_table_tick
= (short *) alloca (nregs
* sizeof (short));
405 reg_last_set_label
= (short *) alloca (nregs
* sizeof (short));
406 reg_last_set_invalid
= (char *) alloca (nregs
* sizeof (short));
407 reg_significant
= (int *) alloca (nregs
* sizeof (int));
409 bzero (reg_last_death
, nregs
* sizeof (rtx
));
410 bzero (reg_last_set
, nregs
* sizeof (rtx
));
411 bzero (reg_last_set_value
, nregs
* sizeof (rtx
));
412 bzero (reg_last_set_table_tick
, nregs
* sizeof (short));
413 bzero (reg_last_set_invalid
, nregs
* sizeof (char));
414 bzero (reg_significant
, nregs
* sizeof (int));
416 init_recog_no_volatile ();
418 /* Compute maximum uid value so uid_cuid can be allocated. */
420 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
421 if (INSN_UID (insn
) > i
)
424 uid_cuid
= (int *) alloca ((i
+ 1) * sizeof (int));
426 significant_mode
= mode_for_size (HOST_BITS_PER_INT
, MODE_INT
, 0);
428 /* Don't use reg_significant when computing it. This can cause problems
429 when, for example, we have j <<= 1 in a loop. */
431 significant_valid
= 0;
433 /* Compute the mapping from uids to cuids.
434 Cuids are numbers assigned to insns, like uids,
435 except that cuids increase monotonically through the code.
437 Scan all SETs and see if we can deduce anything about what
438 bits are significant for some registers. */
440 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
442 INSN_CUID (insn
) = ++i
;
443 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
444 note_stores (PATTERN (insn
), set_significant
);
447 significant_valid
= 1;
449 /* Now scan all the insns in forward order. */
455 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
459 if (GET_CODE (insn
) == CODE_LABEL
)
462 else if (GET_CODE (insn
) == INSN
463 || GET_CODE (insn
) == CALL_INSN
464 || GET_CODE (insn
) == JUMP_INSN
)
466 /* Try this insn with each insn it links back to. */
468 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
469 if ((next
= try_combine (insn
, XEXP (links
, 0), 0)) != 0)
472 /* Try each sequence of three linked insns ending with this one. */
474 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
475 for (nextlinks
= LOG_LINKS (XEXP (links
, 0)); nextlinks
;
476 nextlinks
= XEXP (nextlinks
, 1))
477 if ((next
= try_combine (insn
, XEXP (links
, 0),
478 XEXP (nextlinks
, 0))) != 0)
482 /* Try to combine a jump insn that uses CC0
483 with a preceding insn that sets CC0, and maybe with its
484 logical predecessor as well.
485 This is how we make decrement-and-branch insns.
486 We need this special code because data flow connections
487 via CC0 do not get entered in LOG_LINKS. */
489 if (GET_CODE (insn
) == JUMP_INSN
490 && (prev
= prev_nonnote_insn (insn
)) != 0
491 && GET_CODE (prev
) == INSN
492 && sets_cc0_p (PATTERN (prev
)))
494 if ((next
= try_combine (insn
, prev
, 0)) != 0)
497 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
498 nextlinks
= XEXP (nextlinks
, 1))
499 if ((next
= try_combine (insn
, prev
,
500 XEXP (nextlinks
, 0))) != 0)
504 /* Do the same for an insn that explicitly references CC0. */
505 if (GET_CODE (insn
) == INSN
506 && (prev
= prev_nonnote_insn (insn
)) != 0
507 && GET_CODE (prev
) == INSN
508 && sets_cc0_p (PATTERN (prev
))
509 && GET_CODE (PATTERN (insn
)) == SET
510 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
512 if ((next
= try_combine (insn
, prev
, 0)) != 0)
515 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
516 nextlinks
= XEXP (nextlinks
, 1))
517 if ((next
= try_combine (insn
, prev
,
518 XEXP (nextlinks
, 0))) != 0)
522 /* Finally, see if any of the insns that this insn links to
523 explicitly references CC0. If so, try this insn, that insn,
524 and its predecessor if it sets CC0. */
525 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
526 if (GET_CODE (XEXP (links
, 0)) == INSN
527 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
528 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
529 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
530 && GET_CODE (prev
) == INSN
531 && sets_cc0_p (PATTERN (prev
))
532 && (next
= try_combine (insn
, XEXP (links
, 0), prev
)) != 0)
536 /* Try combining an insn with two different insns whose results it
538 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
539 for (nextlinks
= XEXP (links
, 1); nextlinks
;
540 nextlinks
= XEXP (nextlinks
, 1))
541 if ((next
= try_combine (insn
, XEXP (links
, 0),
542 XEXP (nextlinks
, 0))) != 0)
545 if (GET_CODE (insn
) != NOTE
)
546 record_dead_and_set_regs (insn
);
553 total_attempts
+= combine_attempts
;
554 total_merges
+= combine_merges
;
555 total_extras
+= combine_extras
;
556 total_successes
+= combine_successes
;
559 /* Called via note_stores. If X is a pseudo that is used in more than
560 one basic block, is narrower that HOST_BITS_PER_INT, and is being
561 set, record what bits are significant. If we are clobbering X,
562 ignore this "set" because the clobbered value won't be used.
564 If we are setting only a portion of X and we can't figure out what
565 portion, assume all bits will be used since we don't know what will
569 set_significant (x
, set
)
573 if (GET_CODE (x
) == REG
574 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
575 && reg_n_sets
[REGNO (x
)] > 1
576 && reg_basic_block
[REGNO (x
)] < 0
577 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_INT
)
579 if (GET_CODE (set
) == CLOBBER
)
582 /* If this is a complex assignment, see if we can convert it into a
583 simple assignment. */
584 set
= expand_field_assignment (set
);
585 if (SET_DEST (set
) == x
)
586 reg_significant
[REGNO (x
)]
587 |= significant_bits (SET_SRC (set
), significant_mode
);
589 reg_significant
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
593 /* See if INSN can be combined into I3. PRED and SUCC are optionally
594 insns that were previously combined into I3 or that will be combined
595 into the merger of INSN and I3.
597 Return 0 if the combination is not allowed for any reason.
599 If the combination is allowed, *PDEST will be set to the single
600 destination of INSN and *PSRC to the single source, and this function
604 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
611 rtx set
= 0, src
, dest
;
613 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
614 && next_active_insn (succ
) == i3
)
615 : next_active_insn (insn
) == i3
);
617 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
618 or a PARALLEL consisting of such a SET and CLOBBERs.
620 If INSN has CLOBBER parallel parts, ignore them for our processing.
621 By definition, these happen during the execution of the insn. When it
622 is merged with another insn, all bets are off. If they are, in fact,
623 needed and aren't also supplied in I3, they may be added by
624 recog_for_combine. Otherwise, it won't match.
626 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
629 Get the source and destination of INSN. If more than one, can't
632 if (GET_CODE (PATTERN (insn
)) == SET
)
633 set
= PATTERN (insn
);
634 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
635 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
637 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
639 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
641 switch (GET_CODE (elt
))
643 /* We can ignore CLOBBERs. */
648 /* Ignore SETs whose result isn't used but not those that
649 have side-effects. */
650 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
651 && ! side_effects_p (elt
))
654 /* If we have already found a SET, this is a second one and
655 so we cannot combine with this insn. */
663 /* Anything else means we can't combine. */
669 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
670 so don't do anything with it. */
671 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
680 set
= expand_field_assignment (set
);
681 src
= SET_SRC (set
), dest
= SET_DEST (set
);
683 /* Don't eliminate a store in the stack pointer. */
684 if (dest
== stack_pointer_rtx
685 /* Don't install a subreg involving two modes not tieable.
686 It can worsen register allocation, and can even make invalid reload
687 insns, since the reg inside may need to be copied from in the
688 outside mode, and that may be invalid if it is an fp reg copied in
689 integer mode. As a special exception, we can allow this if
690 I3 is simply copying DEST, a REG, to CC0. */
691 || (GET_CODE (src
) == SUBREG
692 && ! MODES_TIEABLE_P (GET_MODE (src
), GET_MODE (SUBREG_REG (src
)))
694 && ! (GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
695 && SET_DEST (PATTERN (i3
)) == cc0_rtx
696 && GET_CODE (dest
) == REG
&& dest
== SET_SRC (PATTERN (i3
)))
699 /* If we couldn't eliminate a field assignment, we can't combine. */
700 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
701 /* Don't combine with an insn that sets a register to itself if it has
702 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
703 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, 0))
704 /* Can't merge a function call. */
705 || GET_CODE (src
) == CALL
706 /* Don't substitute into an incremented register. */
707 || FIND_REG_INC_NOTE (i3
, dest
)
708 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
709 /* Don't combine the end of a libcall into anything. */
710 || find_reg_note (insn
, REG_RETVAL
, 0)
711 /* Make sure that DEST is not used after SUCC but before I3. */
712 || (succ
&& ! all_adjacent
713 && reg_used_between_p (dest
, succ
, i3
))
714 /* Make sure that the value that is to be substituted for the register
715 does not use any registers whose values alter in between. However,
716 If the insns are adjacent, a use can't cross a set even though we
717 think it might (this can happen for a sequence of insns each setting
718 the same destination; reg_last_set of that register might point to
719 a NOTE). Also, don't move a volatile asm across any other insns. */
721 && (use_crosses_set_p (src
, INSN_CUID (insn
))
722 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))))
723 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
724 better register allocation by not doing the combine. */
725 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
726 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
727 /* Don't combine across a CALL_INSN, because that would possibly
728 change whether the life span of some REGs crosses calls or not,
729 and it is a pain to update that information.
730 Exception: if source is a constant, moving it later can't hurt.
731 Accept that special case, because it helps -fforce-addr a lot. */
732 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
735 /* DEST must either be a REG or CC0. */
736 if (GET_CODE (dest
) == REG
)
738 /* If register alignment is being enforced for multi-word items in all
739 cases except for parameters, it is possible to have a register copy
740 insn referencing a hard register that is not allowed to contain the
741 mode being copied and which would not be valid as an operand of most
742 insns. Eliminate this problem by not combining with such an insn.
744 Also, on some machines we don't want to extend the life of a hard
747 if (GET_CODE (src
) == REG
748 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
749 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
750 #ifdef SMALL_REGISTER_CLASSES
751 /* Don't extend the life of a hard register. */
752 || REGNO (src
) < FIRST_PSEUDO_REGISTER
754 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
755 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))
760 else if (GET_CODE (dest
) != CC0
)
763 /* Don't substitute for a register intended as a clobberable operand. */
764 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
765 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
766 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
767 && rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
))
770 /* If INSN contains anything volatile, or is an `asm' (whether volatile
771 or not), reject, unless nothing volatile comes between it and I3,
772 with the exception of SUCC. */
774 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
775 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
776 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
777 && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
780 /* If INSN or I2 contains an autoincrement or autodecrement,
781 make sure that register is not used between there and I3,
782 and not already used in I3 either.
783 Also insist that I3 not be a jump; if it were one
784 and the incremented register were spilled, we would lose. */
787 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
788 if (REG_NOTE_KIND (link
) == REG_INC
789 && (GET_CODE (i3
) == JUMP_INSN
790 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
791 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
796 /* Don't combine an insn that follows a CC0-setting insn.
797 An insn that uses CC0 must not be separated from the one that sets it.
798 We do, however, allow I2 to follow a CC0-setting insn if that insn
799 is passed as I1; in that case it will be deleted also.
800 We also allow combining in this case if all the insns are adjacent
801 because that would leave the two CC0 insns adjacent as well.
802 It would be more logical to test whether CC0 occurs inside I1 or I2,
803 but that would be much slower, and this ought to be equivalent. */
805 p
= prev_nonnote_insn (insn
);
806 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
811 /* If we get here, we have passed all the tests and the combination is
820 /* LOC is the location within I3 that contains its pattern or the component
821 of a PARALLEL of the pattern. We validate that it is valid for combining.
823 One problem is if I3 modifies its output, as opposed to replacing it
824 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
825 so would produce an insn that is not equivalent to the original insns.
829 (set (reg:DI 101) (reg:DI 100))
830 (set (subreg:SI (reg:DI 101) 0) <foo>)
832 This is NOT equivalent to:
834 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
835 (set (reg:DI 101) (reg:DI 100))])
837 Not only does this modify 100 (in which case it might still be valid
838 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
840 We can also run into a problem if I2 sets a register that I1
841 uses and I1 gets directly substituted into I3 (not via I2). In that
842 case, we would be getting the wrong value of I2DEST into I3, so we
843 must reject the combination. This case occurs when I2 and I1 both
844 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
845 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
846 of a SET must prevent combination from occurring.
848 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
849 if the destination of a SET is a hard register.
851 Before doing the above check, we first try to expand a field assignment
852 into a set of logical operations.
854 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
855 we place a register that is both set and used within I3. If more than one
856 such register is detected, we fail.
858 Return 1 if the combination is valid, zero otherwise. */
861 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
871 if (GET_CODE (x
) == SET
)
873 rtx set
= expand_field_assignment (x
);
874 rtx dest
= SET_DEST (set
);
875 rtx src
= SET_SRC (set
);
876 rtx inner_dest
= dest
, inner_src
= src
;
880 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
881 || GET_CODE (inner_dest
) == SUBREG
882 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
883 inner_dest
= XEXP (inner_dest
, 0);
885 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
888 while (GET_CODE (inner_src
) == STRICT_LOW_PART
889 || GET_CODE (inner_src
) == SUBREG
890 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
891 inner_src
= XEXP (inner_src
, 0);
893 /* If it is better that two different modes keep two different pseudos,
894 avoid combining them. This avoids producing the following pattern
896 (set (subreg:SI (reg/v:QI 21) 0)
897 (lshiftrt:SI (reg/v:SI 20)
899 If that were made, reload could not handle the pair of
900 reg 20/21, since it would try to get any GENERAL_REGS
901 but some of them don't handle QImode. */
903 if (rtx_equal_p (inner_src
, i2dest
)
904 && GET_CODE (inner_dest
) == REG
905 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
909 /* Check for the case where I3 modifies its output, as
911 if ((inner_dest
!= dest
912 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
913 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
914 /* This is the same test done in can_combine_p except that we
915 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
917 || (GET_CODE (inner_dest
) == REG
918 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
919 #ifdef SMALL_REGISTER_CLASSES
920 && GET_CODE (src
) != CALL
922 && ! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
923 GET_MODE (inner_dest
))
927 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
930 /* If DEST is used in I3, it is being killed in this insn,
931 so record that for later. */
932 if (pi3dest_killed
&& GET_CODE (dest
) == REG
933 && reg_referenced_p (dest
, PATTERN (i3
)))
938 *pi3dest_killed
= dest
;
942 else if (GET_CODE (x
) == PARALLEL
)
946 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
947 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
948 i1_not_in_src
, pi3dest_killed
))
955 /* Try to combine the insns I1 and I2 into I3.
956 Here I1 and I2 appear earlier than I3.
957 I1 can be zero; then we combine just I2 into I3.
959 It we are combining three insns and the resulting insn is not recognized,
960 try splitting it into two insns. If that happens, I2 and I3 are retained
961 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
964 If we created two insns, return I2; otherwise return I3.
965 Return 0 if the combination does not work. Then nothing is changed. */
968 try_combine (i3
, i2
, i1
)
969 register rtx i3
, i2
, i1
;
971 /* New patterns for I3 and I3, respectively. */
972 rtx newpat
, newi2pat
= 0;
973 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
974 int added_sets_1
, added_sets_2
;
975 /* Total number of SETs to put into I3. */
977 /* Nonzero is I2's body now appears in I3. */
979 /* INSN_CODEs for new I3, new I2, and user of condition code. */
980 int insn_code_number
, i2_code_number
, other_code_number
;
981 /* Contains I3 if the destination of I3 is used in its source, which means
982 that the old life of I3 is being killed. If that usage is placed into
983 I2 and not in I3, a REG_DEAD note must be made. */
984 rtx i3dest_killed
= 0;
985 /* SET_DEST and SET_SRC of I2 and I1. */
986 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
987 /* PATTERN (I2), or a copy of it in certain cases. */
989 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
990 int i2dest_in_i2src
, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
992 /* Notes that must be added to REG_NOTES in I3 and I2. */
993 rtx new_i3_notes
, new_i2_notes
;
1000 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1001 This can occur when flow deletes an insn that it has merged into an
1002 auto-increment address. We also can't do anything if I3 has a
1003 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1006 if (GET_RTX_CLASS (GET_CODE (i3
)) != 'i'
1007 || GET_RTX_CLASS (GET_CODE (i2
)) != 'i'
1008 || (i1
&& GET_RTX_CLASS (GET_CODE (i1
)) != 'i')
1009 || find_reg_note (i3
, REG_LIBCALL
, 0))
1014 undobuf
.num_undo
= previous_num_undos
= 0;
1015 undobuf
.other_insn
= 0;
1017 /* Save the current high-water-mark so we can free storage if we didn't
1018 accept this combination. */
1019 undobuf
.storage
= (char *) oballoc (0);
1021 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1022 code below, set I1 to be the earlier of the two insns. */
1023 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1024 temp
= i1
, i1
= i2
, i2
= temp
;
1026 /* First check for one important special-case that the code below will
1027 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1028 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1029 we may be able to replace that destination with the destination of I3.
1030 This occurs in the common code where we compute both a quotient and
1031 remainder into a structure, in which case we want to do the computation
1032 directly into the structure to avoid register-register copies.
1034 We make very conservative checks below and only try to handle the
1035 most common cases of this. For example, we only handle the case
1036 where I2 and I3 are adjacent to avoid making difficult register
1039 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1040 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1041 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1042 #ifdef SMALL_REGISTER_CLASSES
1043 && (GET_CODE (SET_DEST (PATTERN (i3
))) != REG
1044 || REGNO (SET_DEST (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
)
1046 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1047 && GET_CODE (PATTERN (i2
)) == PARALLEL
1048 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1049 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1050 below would need to check what is inside (and reg_overlap_mentioned_p
1051 doesn't support those codes anyway). Don't allow those destinations;
1052 the resulting insn isn't likely to be recognized anyway. */
1053 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1054 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1055 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1056 SET_DEST (PATTERN (i3
)))
1057 && next_real_insn (i2
) == i3
)
1059 rtx p2
= PATTERN (i2
);
1061 /* Make sure that the destination of I3,
1062 which we are going to substitute into one output of I2,
1063 is not used within another output of I2. We must avoid making this:
1064 (parallel [(set (mem (reg 69)) ...)
1065 (set (reg 69) ...)])
1066 which is not well-defined as to order of actions.
1067 (Besides, reload can't handle output reloads for this.)
1069 The problem can also happen if the dest of I3 is a memory ref,
1070 if another dest in I2 is an indirect memory ref. */
1071 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1072 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1073 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1074 SET_DEST (XVECEXP (p2
, 0, i
))))
1077 if (i
== XVECLEN (p2
, 0))
1078 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1079 if (SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1084 subst_low_cuid
= INSN_CUID (i2
);
1087 i2dest
= SET_SRC (PATTERN (i3
));
1089 /* Replace the dest in I2 with our dest and make the resulting
1090 insn the new pattern for I3. Then skip to where we
1091 validate the pattern. Everything was set up above. */
1092 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1093 SET_DEST (PATTERN (i3
)));
1096 goto validate_replacement
;
1101 /* If we have no I1 and I2 looks like:
1102 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1104 make up a dummy I1 that is
1107 (set (reg:CC X) (compare:CC Y (const_int 0)))
1109 (We can ignore any trailing CLOBBERs.)
1111 This undoes a previous combination and allows us to match a branch-and-
1114 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1115 && XVECLEN (PATTERN (i2
), 0) >= 2
1116 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1117 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1119 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1120 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1121 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1122 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1123 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1124 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1126 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1127 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1132 /* We make I1 with the same INSN_UID as I2. This gives it
1133 the same INSN_CUID for value tracking. Our fake I1 will
1134 never appear in the insn stream so giving it the same INSN_UID
1135 as I2 will not cause a problem. */
1137 i1
= gen_rtx (INSN
, VOIDmode
, INSN_UID (i2
), 0, i2
,
1138 XVECEXP (PATTERN (i2
), 0, 1), -1, 0, 0);
1140 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1141 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1142 SET_DEST (PATTERN (i1
)));
1147 /* Verify that I2 and I1 are valid for combining. */
1148 if (! can_combine_p (i2
, i3
, i1
, 0, &i2dest
, &i2src
)
1149 || (i1
&& ! can_combine_p (i1
, i3
, 0, i2
, &i1dest
, &i1src
)))
1155 /* Record whether I2DEST is used in I2SRC and similarly for the other
1156 cases. Knowing this will help in register status updating below. */
1157 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1158 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1159 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1161 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1163 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1165 /* Ensure that I3's pattern can be the destination of combines. */
1166 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1167 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1174 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1175 We used to do this EXCEPT in one case: I3 has a post-inc in an
1176 output operand. However, that exception can give rise to insns like
1178 which is a famous insn on the PDP-11 where the value of r3 used as the
1179 source was model-dependent. Avoid this sort of thing. */
1182 if (!(GET_CODE (PATTERN (i3
)) == SET
1183 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1184 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1185 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1186 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1187 /* It's not the exception. */
1190 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1191 if (REG_NOTE_KIND (link
) == REG_INC
1192 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1194 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1201 /* See if the SETs in I1 or I2 need to be kept around in the merged
1202 instruction: whenever the value set there is still needed past I3.
1203 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1205 For the SET in I1, we have two cases: If I1 and I2 independently
1206 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1207 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1208 in I1 needs to be kept around unless I1DEST dies or is set in either
1209 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1210 I1DEST. If so, we know I1 feeds into I2. */
1212 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1215 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1216 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1218 /* If the set in I2 needs to be kept around, we must make a copy of
1219 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1220 PATTERN (I2), we are only substituting for the original I1DEST, not into
1221 an already-substituted copy. This also prevents making self-referential
1222 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1225 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1226 ? gen_rtx (SET
, VOIDmode
, i2dest
, i2src
)
1230 i2pat
= copy_rtx (i2pat
);
1234 /* Substitute in the latest insn for the regs set by the earlier ones. */
1236 maxreg
= max_reg_num ();
1239 subst_low_cuid
= i1
? INSN_CUID (i1
) : INSN_CUID (i2
);
1241 /* It is possible that the source of I2 or I1 may be performing an
1242 unneeded operation, such as a ZERO_EXTEND of something that is known
1243 to have the high part zero. Handle that case by letting subst look at
1244 the innermost one of them.
1246 Another way to do this would be to have a function that tries to
1247 simplify a single insn instead of merging two or more insns. We don't
1248 do this because of the potential of infinite loops and because
1249 of the potential extra memory required. However, doing it the way
1250 we are is a bit of a kludge and doesn't catch all cases.
1252 But only do this if -fexpensive-optimizations since it slows things down
1253 and doesn't usually win. */
1255 if (flag_expensive_optimizations
)
1257 /* Pass pc_rtx so no substitutions are done, just simplifications.
1258 The cases that we are interested in here do not involve the few
1259 cases were is_replaced is checked. */
1261 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1263 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1265 previous_num_undos
= undobuf
.num_undo
;
1269 /* Many machines that don't use CC0 have insns that can both perform an
1270 arithmetic operation and set the condition code. These operations will
1271 be represented as a PARALLEL with the first element of the vector
1272 being a COMPARE of an arithmetic operation with the constant zero.
1273 The second element of the vector will set some pseudo to the result
1274 of the same arithmetic operation. If we simplify the COMPARE, we won't
1275 match such a pattern and so will generate an extra insn. Here we test
1276 for this case, where both the comparison and the operation result are
1277 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1278 I2SRC. Later we will make the PARALLEL that contains I2. */
1280 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1281 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1282 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1283 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1286 enum machine_mode compare_mode
;
1288 newpat
= PATTERN (i3
);
1289 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1293 #ifdef EXTRA_CC_MODES
1294 /* See if a COMPARE with the operand we substituted in should be done
1295 with the mode that is currently being used. If not, do the same
1296 processing we do in `subst' for a SET; namely, if the destination
1297 is used only once, try to replace it with a register of the proper
1298 mode and also replace the COMPARE. */
1299 if (undobuf
.other_insn
== 0
1300 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1301 &undobuf
.other_insn
))
1302 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1304 != GET_MODE (SET_DEST (newpat
))))
1306 int regno
= REGNO (SET_DEST (newpat
));
1307 rtx new_dest
= gen_rtx (REG
, compare_mode
, regno
);
1309 if (regno
< FIRST_PSEUDO_REGISTER
1310 || (reg_n_sets
[regno
] == 1 && ! added_sets_2
1311 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1313 if (regno
>= FIRST_PSEUDO_REGISTER
)
1314 SUBST (regno_reg_rtx
[regno
], new_dest
);
1316 SUBST (SET_DEST (newpat
), new_dest
);
1317 SUBST (XEXP (*cc_use
, 0), new_dest
);
1318 SUBST (SET_SRC (newpat
),
1319 gen_rtx_combine (COMPARE
, compare_mode
,
1320 i2src
, const0_rtx
));
1323 undobuf
.other_insn
= 0;
1330 n_occurrences
= 0; /* `subst' counts here */
1332 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1333 need to make a unique copy of I2SRC each time we substitute it
1334 to avoid self-referential rtl. */
1336 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1337 ! i1_feeds_i3
&& i1dest_in_i1src
);
1338 previous_num_undos
= undobuf
.num_undo
;
1340 /* Record whether i2's body now appears within i3's body. */
1341 i2_is_used
= n_occurrences
;
1344 /* If we already got a failure, don't try to do more. Otherwise,
1345 try to substitute in I1 if we have it. */
1347 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1349 /* Before we can do this substitution, we must redo the test done
1350 above (see detailed comments there) that ensures that I1DEST
1351 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1353 if (! combinable_i3pat (0, &newpat
, i1dest
, 0, 0, 0))
1360 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1361 previous_num_undos
= undobuf
.num_undo
;
1364 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1365 to count all the ways that I2SRC and I1SRC can be used. */
1366 if ((FIND_REG_INC_NOTE (i2
, 0) != 0
1367 && i2_is_used
+ added_sets_2
> 1)
1368 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, 0) != 0
1369 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1371 /* Fail if we tried to make a new register (we used to abort, but there's
1372 really no reason to). */
1373 || max_reg_num () != maxreg
1374 /* Fail if we couldn't do something and have a CLOBBER. */
1375 || GET_CODE (newpat
) == CLOBBER
)
1381 /* If the actions of the earlier insns must be kept
1382 in addition to substituting them into the latest one,
1383 we must make a new PARALLEL for the latest insn
1384 to hold additional the SETs. */
1386 if (added_sets_1
|| added_sets_2
)
1390 if (GET_CODE (newpat
) == PARALLEL
)
1392 rtvec old
= XVEC (newpat
, 0);
1393 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1394 newpat
= gen_rtx (PARALLEL
, VOIDmode
, rtvec_alloc (total_sets
));
1395 bcopy (&old
->elem
[0], &XVECEXP (newpat
, 0, 0),
1396 sizeof (old
->elem
[0]) * old
->num_elem
);
1401 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1402 newpat
= gen_rtx (PARALLEL
, VOIDmode
, rtvec_alloc (total_sets
));
1403 XVECEXP (newpat
, 0, 0) = old
;
1407 XVECEXP (newpat
, 0, --total_sets
)
1408 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1409 ? gen_rtx (SET
, VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1413 /* If there is no I1, use I2's body as is. We used to also not do
1414 the subst call below if I2 was substituted into I3,
1415 but that could lose a simplification. */
1417 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
1419 /* See comment where i2pat is assigned. */
1420 XVECEXP (newpat
, 0, --total_sets
)
1421 = subst (i2pat
, i1dest
, i1src
, 0, 0);
1425 /* We come here when we are replacing a destination in I2 with the
1426 destination of I3. */
1427 validate_replacement
:
1429 /* Is the result of combination a valid instruction? */
1430 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1432 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1433 the second SET's destination is a register that is unused. In that case,
1434 we just need the first SET. This can occur when simplifying a divmod
1435 insn. We *must* test for this case here because the code below that
1436 splits two independent SETs doesn't handle this case correctly when it
1437 updates the register status. Also check the case where the first
1438 SET's destination is unused. That would not cause incorrect code, but
1439 does cause an unneeded insn to remain. */
1441 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
1442 && XVECLEN (newpat
, 0) == 2
1443 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1444 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1445 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
1446 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
1447 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
1448 && asm_noperands (newpat
) < 0)
1450 newpat
= XVECEXP (newpat
, 0, 0);
1451 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1454 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
1455 && XVECLEN (newpat
, 0) == 2
1456 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1457 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1458 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
1459 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
1460 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
1461 && asm_noperands (newpat
) < 0)
1463 newpat
= XVECEXP (newpat
, 0, 1);
1464 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1467 /* If we were combining three insns and the result is a simple SET
1468 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1469 insns. There are two ways to do this. It can be split using a
1470 machine-specific method (like when you have an addition of a large
1471 constant) or by combine in the function find_split_point. */
1473 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
1474 && asm_noperands (newpat
) < 0)
1476 rtx m_split
, *split
;
1477 rtx ni2dest
= i2dest
;
1479 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1480 use I2DEST as a scratch register will help. In the latter case,
1481 convert I2DEST to the mode of the source of NEWPAT if we can. */
1483 m_split
= split_insns (newpat
, i3
);
1486 /* If I2DEST is a hard register or the only use of a pseudo,
1487 we can change its mode. */
1488 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
1489 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
1490 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
1491 || (reg_n_sets
[REGNO (i2dest
)] == 1 && ! added_sets_2
1492 && ! REG_USERVAR_P (i2dest
))))
1493 ni2dest
= gen_rtx (REG
, GET_MODE (SET_DEST (newpat
)),
1496 m_split
= split_insns (gen_rtx (PARALLEL
, VOIDmode
,
1497 gen_rtvec (2, newpat
,
1504 if (m_split
&& GET_CODE (m_split
) == SEQUENCE
1505 && XVECLEN (m_split
, 0) == 2
1506 && (next_real_insn (i2
) == i3
1507 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
1510 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
1511 newpat
= PATTERN (XVECEXP (m_split
, 0, 1));
1513 /* In case we changed the mode of I2DEST, replace it in the
1514 pseudo-register table here. We can't do it above in case this
1515 code doesn't get executed and we do a split the other way. */
1517 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
1518 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
1520 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
1521 if (i2_code_number
>= 0)
1522 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1525 /* If we can split it and use I2DEST, go ahead and see if that
1526 helps things be recognized. Verify that none of the registers
1527 are set between I2 and I3. */
1528 else if ((split
= find_split_point (&newpat
)) != 0
1530 && GET_CODE (i2dest
) == REG
1532 /* We need I2DEST in the proper mode. If it is a hard register
1533 or the only use of a pseudo, we can change its mode. */
1534 && (GET_MODE (*split
) == GET_MODE (i2dest
)
1535 || GET_MODE (*split
) == VOIDmode
1536 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
1537 || (reg_n_sets
[REGNO (i2dest
)] == 1 && ! added_sets_2
1538 && ! REG_USERVAR_P (i2dest
)))
1539 && (next_real_insn (i2
) == i3
1540 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
1541 /* We can't overwrite I2DEST if its value is still used by
1543 && ! reg_referenced_p (i2dest
, newpat
))
1545 rtx newdest
= i2dest
;
1547 /* Get NEWDEST as a register in the proper mode. We have already
1548 validated that we can do this. */
1549 if (GET_MODE (i2dest
) != GET_MODE (*split
)
1550 && GET_MODE (*split
) != VOIDmode
)
1552 newdest
= gen_rtx (REG
, GET_MODE (*split
), REGNO (i2dest
));
1554 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
1555 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
1558 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1559 an ASHIFT. This can occur if it was inside a PLUS and hence
1560 appeared to be a memory address. This is a kludge. */
1561 if (GET_CODE (*split
) == MULT
1562 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
1563 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
1564 SUBST (*split
, gen_rtx_combine (ASHIFT
, GET_MODE (*split
),
1566 gen_rtx (CONST_INT
, VOIDmode
, i
)));
1568 #ifdef INSN_SCHEDULING
1569 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1570 be written as a ZERO_EXTEND. */
1571 if (GET_CODE (*split
) == SUBREG
1572 && GET_CODE (SUBREG_REG (*split
)) == MEM
)
1573 SUBST (*split
, gen_rtx_combine (ZERO_EXTEND
, GET_MODE (*split
),
1577 newi2pat
= gen_rtx_combine (SET
, VOIDmode
, newdest
, *split
);
1578 SUBST (*split
, newdest
);
1579 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
1580 if (i2_code_number
>= 0)
1581 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1585 /* Check for a case where we loaded from memory in a narrow mode and
1586 then sign extended it, but we need both registers. In that case,
1587 we have a PARALLEL with both loads from the same memory location.
1588 We can split this into a load from memory followed by a register-register
1589 copy. This saves at least one insn, more if register allocation can
1590 eliminate the copy. */
1592 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
1593 && GET_CODE (newpat
) == PARALLEL
1594 && XVECLEN (newpat
, 0) == 2
1595 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1596 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
1597 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1598 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
1599 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
1600 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
1602 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
1603 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
1604 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
1605 SET_SRC (XVECEXP (newpat
, 0, 1)))
1606 && ! find_reg_note (i3
, REG_UNUSED
,
1607 SET_DEST (XVECEXP (newpat
, 0, 0))))
1609 newi2pat
= XVECEXP (newpat
, 0, 0);
1610 newpat
= XVECEXP (newpat
, 0, 1);
1611 SUBST (SET_SRC (newpat
),
1612 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)),
1613 SET_DEST (newi2pat
)));
1614 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
1615 if (i2_code_number
>= 0)
1616 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1618 if (insn_code_number
>= 0)
1623 /* If we will be able to accept this, we have made a change to the
1624 destination of I3. This can invalidate a LOG_LINKS pointing
1625 to I3. No other part of combine.c makes such a transformation.
1627 The new I3 will have a destination that was previously the
1628 destination of I1 or I2 and which was used in i2 or I3. Call
1629 distribute_links to make a LOG_LINK from the next use of
1630 that destination. */
1632 PATTERN (i3
) = newpat
;
1633 distribute_links (gen_rtx (INSN_LIST
, VOIDmode
, i3
, 0));
1635 /* I3 now uses what used to be its destination and which is
1636 now I2's destination. That means we need a LOG_LINK from
1637 I3 to I2. But we used to have one, so we still will.
1639 However, some later insn might be using I2's dest and have
1640 a LOG_LINK pointing at I3. We must remove this link.
1641 The simplest way to remove the link is to point it at I1,
1642 which we know will be a NOTE. */
1644 for (insn
= NEXT_INSN (i3
);
1645 insn
&& GET_CODE (insn
) != CODE_LABEL
1646 && GET_CODE (PREV_INSN (insn
)) != JUMP_INSN
;
1647 insn
= NEXT_INSN (insn
))
1649 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
1650 && reg_referenced_p (SET_DEST (newi2pat
), PATTERN (insn
)))
1652 for (link
= LOG_LINKS (insn
); link
;
1653 link
= XEXP (link
, 1))
1654 if (XEXP (link
, 0) == i3
)
1655 XEXP (link
, 0) = i1
;
1663 /* Similarly, check for a case where we have a PARALLEL of two independent
1664 SETs but we started with three insns. In this case, we can do the sets
1665 as two separate insns. This case occurs when some SET allows two
1666 other insns to combine, but the destination of that SET is still live. */
1668 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
1669 && GET_CODE (newpat
) == PARALLEL
1670 && XVECLEN (newpat
, 0) == 2
1671 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
1672 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
1673 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
1674 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
1675 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
1676 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
1677 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
1679 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
1680 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
1681 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
1682 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
1683 XVECEXP (newpat
, 0, 0))
1684 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
1685 XVECEXP (newpat
, 0, 1)))
1687 newi2pat
= XVECEXP (newpat
, 0, 1);
1688 newpat
= XVECEXP (newpat
, 0, 0);
1690 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
1691 if (i2_code_number
>= 0)
1692 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
1695 /* If it still isn't recognized, fail and change things back the way they
1697 if ((insn_code_number
< 0
1698 /* Is the result a reasonable ASM_OPERANDS? */
1699 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
1705 /* If we had to change another insn, make sure it is valid also. */
1706 if (undobuf
.other_insn
)
1708 rtx other_notes
= REG_NOTES (undobuf
.other_insn
);
1709 rtx other_pat
= PATTERN (undobuf
.other_insn
);
1710 rtx new_other_notes
;
1713 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
1716 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
1722 PATTERN (undobuf
.other_insn
) = other_pat
;
1724 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
1725 are still valid. Then add any non-duplicate notes added by
1726 recog_for_combine. */
1727 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
1729 next
= XEXP (note
, 1);
1731 if (REG_NOTE_KIND (note
) == REG_UNUSED
1732 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
1733 remove_note (undobuf
.other_insn
, note
);
1736 distribute_notes (new_other_notes
, undobuf
.other_insn
,
1737 undobuf
.other_insn
, 0, 0, 0);
1740 /* We now know that we can do this combination. Merge the insns and
1741 update the status of registers and LOG_LINKS. */
1744 rtx i3notes
, i2notes
, i1notes
= 0;
1745 rtx i3links
, i2links
, i1links
= 0;
1747 int all_adjacent
= (next_real_insn (i2
) == i3
1748 && (i1
== 0 || next_real_insn (i1
) == i2
));
1750 /* Compute which registers we expect to eliminate. */
1751 rtx elim_i2
= (newi2pat
|| i2dest_in_i2src
|| i2dest_in_i1src
1753 rtx elim_i1
= i1
== 0 || i1dest_in_i1src
? 0 : i1dest
;
1755 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
1757 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
1758 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
1760 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
1762 /* Ensure that we do not have something that should not be shared but
1763 occurs multiple times in the new insns. Check this by first
1764 resetting all the `used' flags and then copying anything is shared. */
1766 reset_used_flags (i3notes
);
1767 reset_used_flags (i2notes
);
1768 reset_used_flags (i1notes
);
1769 reset_used_flags (newpat
);
1770 reset_used_flags (newi2pat
);
1771 if (undobuf
.other_insn
)
1772 reset_used_flags (PATTERN (undobuf
.other_insn
));
1774 i3notes
= copy_rtx_if_shared (i3notes
);
1775 i2notes
= copy_rtx_if_shared (i2notes
);
1776 i1notes
= copy_rtx_if_shared (i1notes
);
1777 newpat
= copy_rtx_if_shared (newpat
);
1778 newi2pat
= copy_rtx_if_shared (newi2pat
);
1779 if (undobuf
.other_insn
)
1780 reset_used_flags (PATTERN (undobuf
.other_insn
));
1782 INSN_CODE (i3
) = insn_code_number
;
1783 PATTERN (i3
) = newpat
;
1784 if (undobuf
.other_insn
)
1785 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
1787 /* We had one special case above where I2 had more than one set and
1788 we replaced a destination of one of those sets with the destination
1789 of I3. In that case, we have to update LOG_LINKS of insns later
1790 in this basic block. Note that this (expensive) case is rare. */
1792 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
1793 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
1794 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
1795 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
1796 && ! find_reg_note (i2
, REG_UNUSED
,
1797 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
1801 for (insn
= NEXT_INSN (i2
); insn
; insn
= NEXT_INSN (insn
))
1803 if (insn
!= i3
&& GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1804 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
1805 if (XEXP (link
, 0) == i2
)
1806 XEXP (link
, 0) = i3
;
1808 if (GET_CODE (insn
) == CODE_LABEL
1809 || GET_CODE (insn
) == JUMP_INSN
)
1821 INSN_CODE (i2
) = i2_code_number
;
1822 PATTERN (i2
) = newi2pat
;
1826 PUT_CODE (i2
, NOTE
);
1827 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
1828 NOTE_SOURCE_FILE (i2
) = 0;
1835 PUT_CODE (i1
, NOTE
);
1836 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
1837 NOTE_SOURCE_FILE (i1
) = 0;
1840 /* Get death notes for everything that is now used in either I3 or
1841 I2 and used to die in a previous insn. */
1843 move_deaths (newpat
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
), i3
, &midnotes
);
1845 move_deaths (newi2pat
, INSN_CUID (i1
), i2
, &midnotes
);
1847 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
1849 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: 0, elim_i2
, elim_i1
);
1851 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: 0, elim_i2
, elim_i1
);
1853 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: 0, elim_i2
, elim_i1
);
1855 distribute_notes (midnotes
, 0, i3
, newi2pat
? i2
: 0, elim_i2
, elim_i1
);
1857 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
1858 know these are REG_UNUSED and want them to go to the desired insn,
1859 so we always pass it as i3. */
1860 if (newi2pat
&& new_i2_notes
)
1861 distribute_notes (new_i2_notes
, i2
, i2
, 0, 0, 0);
1863 distribute_notes (new_i3_notes
, i3
, i3
, 0, 0, 0);
1865 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
1866 put a REG_DEAD note for it somewhere. Similarly for I2 and I1. */
1868 distribute_notes (gen_rtx (EXPR_LIST
, REG_DEAD
, i3dest_killed
, 0),
1869 0, i3
, newi2pat
? i2
: 0, 0, 0);
1870 if (i2dest_in_i2src
)
1871 distribute_notes (gen_rtx (EXPR_LIST
, REG_DEAD
, i2dest
, 0),
1872 0, i3
, newi2pat
? i2
: 0, 0, 0);
1873 if (i1dest_in_i1src
)
1874 distribute_notes (gen_rtx (EXPR_LIST
, REG_DEAD
, i1dest
, 0),
1875 0, i3
, newi2pat
? i2
: 0, 0, 0);
1877 distribute_links (i3links
);
1878 distribute_links (i2links
);
1879 distribute_links (i1links
);
1881 if (GET_CODE (i2dest
) == REG
)
1883 /* The insn that previously set this register doesn't exist, and
1884 this life of the register may not exist either. Show that
1885 we don't know its value any more. If we don't do this and
1886 I2 set the register to a value that depended on its old
1887 contents, we will get confused. If this insn is used, thing
1888 will be set correctly in combine_instructions. */
1889 record_value_for_reg (i2dest
, 0, 0);
1891 /* If the reg formerly set in I2 died only once and that was in I3,
1892 zero its use count so it won't make `reload' do any work. */
1893 if (! added_sets_2
&& newi2pat
== 0)
1895 regno
= REGNO (i2dest
);
1896 reg_n_sets
[regno
]--;
1897 if (reg_n_sets
[regno
] == 0
1898 && ! (basic_block_live_at_start
[0][regno
/ HOST_BITS_PER_INT
]
1899 & (1 << (regno
% HOST_BITS_PER_INT
))))
1900 reg_n_refs
[regno
] = 0;
1904 if (i1
&& GET_CODE (i1dest
) == REG
)
1906 record_value_for_reg (i1dest
, 0, 0);
1907 regno
= REGNO (i1dest
);
1910 reg_n_sets
[regno
]--;
1911 if (reg_n_sets
[regno
] == 0
1912 && ! (basic_block_live_at_start
[0][regno
/ HOST_BITS_PER_INT
]
1913 & (1 << (regno
% HOST_BITS_PER_INT
))))
1914 reg_n_refs
[regno
] = 0;
1918 /* If I3 is now an unconditional jump, ensure that it has a
1919 BARRIER following it since it may have initially been a
1920 conditional jump. */
1922 if ((GET_CODE (newpat
) == RETURN
|| simplejump_p (i3
))
1923 && GET_CODE (next_nonnote_insn (i3
)) != BARRIER
)
1924 emit_barrier_after (i3
);
1927 combine_successes
++;
1929 return newi2pat
? i2
: i3
;
1932 /* Undo all the modifications recorded in undobuf. */
1938 if (undobuf
.num_undo
> MAX_UNDO
)
1939 undobuf
.num_undo
= MAX_UNDO
;
1940 for (i
= undobuf
.num_undo
- 1; i
>= 0; i
--)
1941 *undobuf
.undo
[i
].where
= undobuf
.undo
[i
].old_contents
;
1943 obfree (undobuf
.storage
);
1944 undobuf
.num_undo
= 0;
1947 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
1948 where we have an arithmetic expression and return that point.
1950 try_combine will call this function to see if an insn can be split into
1954 find_split_point (loc
)
1958 enum rtx_code code
= GET_CODE (x
);
1960 int len
= 0, pos
, unsignedp
;
1963 /* First special-case some codes. */
1967 #ifdef INSN_SCHEDULING
1968 /* If we are making a paradoxical SUBREG invalid, it becomes a split
1970 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
1973 return find_split_point (&SUBREG_REG (x
));
1977 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
1978 using LO_SUM and HIGH. */
1979 if (GET_CODE (XEXP (x
, 0)) == CONST
1980 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
1983 gen_rtx_combine (LO_SUM
, Pmode
,
1984 gen_rtx_combine (HIGH
, Pmode
, XEXP (x
, 0)),
1986 return &XEXP (XEXP (x
, 0), 0);
1990 /* If we have a PLUS whose second operand is a constant and the
1991 address is not valid, perhaps will can split it up using
1992 the machine-specific way to split large constants. We use
1993 the first pseudo-reg (one of the virtual regs) as a placeholder;
1994 it will not remain in the result. */
1995 if (GET_CODE (XEXP (x
, 0)) == PLUS
1996 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1997 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
1999 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2000 rtx seq
= split_insns (gen_rtx (SET
, VOIDmode
, reg
, XEXP (x
, 0)),
2003 /* This should have produced two insns, each of which sets our
2004 placeholder. If the source of the second is a valid address,
2005 we can make put both sources together and make a split point
2008 if (seq
&& XVECLEN (seq
, 0) == 2
2009 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
2010 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
2011 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
2012 && ! reg_mentioned_p (reg
,
2013 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
2014 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
2015 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
2016 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
2017 && memory_address_p (GET_MODE (x
),
2018 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
2020 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
2021 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
2023 /* Replace the placeholder in SRC2 with SRC1. If we can
2024 find where in SRC2 it was placed, that can become our
2025 split point and we can replace this address with SRC2.
2026 Just try two obvious places. */
2028 src2
= replace_rtx (src2
, reg
, src1
);
2030 if (XEXP (src2
, 0) == src1
)
2031 split
= &XEXP (src2
, 0);
2032 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2033 && XEXP (XEXP (src2
, 0), 0) == src1
)
2034 split
= &XEXP (XEXP (src2
, 0), 0);
2038 SUBST (XEXP (x
, 0), src2
);
2047 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2048 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2049 we need to put the operand into a register. So split at that
2052 if (SET_DEST (x
) == cc0_rtx
2053 && GET_CODE (SET_SRC (x
)) != COMPARE
2054 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2055 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2056 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2057 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2058 return &SET_SRC (x
);
2061 /* See if we can split SET_SRC as it stands. */
2062 split
= find_split_point (&SET_SRC (x
));
2063 if (split
&& split
!= &SET_SRC (x
))
2066 /* See if this is a bitfield assignment with everything constant. If
2067 so, this is an IOR of an AND, so split it into that. */
2068 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2069 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2070 <= HOST_BITS_PER_INT
)
2071 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2072 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2073 && GET_CODE (SET_SRC (x
)) == CONST_INT
2074 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2075 + INTVAL (XEXP (SET_DEST (x
), 2)))
2076 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2077 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2079 int pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2080 int len
= INTVAL (XEXP (SET_DEST (x
), 1));
2081 int src
= INTVAL (SET_SRC (x
));
2082 rtx dest
= XEXP (SET_DEST (x
), 0);
2083 enum machine_mode mode
= GET_MODE (dest
);
2084 unsigned int mask
= (1 << len
) - 1;
2087 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
2092 gen_binary (IOR
, mode
, dest
,
2093 gen_rtx (CONST_INT
, VOIDmode
, src
<< pos
)));
2096 gen_binary (IOR
, mode
,
2097 gen_binary (AND
, mode
, dest
,
2098 gen_rtx (CONST_INT
, VOIDmode
,
2100 & GET_MODE_MASK (mode
)))),
2101 gen_rtx (CONST_INT
, VOIDmode
, src
<< pos
)));
2103 SUBST (SET_DEST (x
), dest
);
2105 split
= find_split_point (&SET_SRC (x
));
2106 if (split
&& split
!= &SET_SRC (x
))
2110 /* Otherwise, see if this is an operation that we can split into two.
2111 If so, try to split that. */
2112 code
= GET_CODE (SET_SRC (x
));
2117 inner
= XEXP (SET_SRC (x
), 0);
2119 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
2125 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2126 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
2128 inner
= XEXP (SET_SRC (x
), 0);
2129 len
= INTVAL (XEXP (SET_SRC (x
), 1));
2130 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
2133 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
2135 unsignedp
= (code
== ZERO_EXTRACT
);
2140 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
2142 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
2144 if (unsignedp
&& len
< HOST_BITS_PER_INT
)
2149 gen_rtx_combine (LSHIFTRT
, mode
,
2150 gen_lowpart_for_combine (mode
, inner
),
2151 gen_rtx (CONST_INT
, VOIDmode
, pos
)),
2152 gen_rtx (CONST_INT
, VOIDmode
, (1 << len
) - 1)));
2154 split
= find_split_point (&SET_SRC (x
));
2155 if (split
&& split
!= &SET_SRC (x
))
2163 gen_rtx_combine (ASHIFT
, mode
,
2164 gen_lowpart_for_combine (mode
, inner
),
2165 gen_rtx (CONST_INT
, VOIDmode
,
2166 (GET_MODE_BITSIZE (mode
)
2168 gen_rtx (CONST_INT
, VOIDmode
,
2169 GET_MODE_BITSIZE (mode
) - len
)));
2171 split
= find_split_point (&SET_SRC (x
));
2172 if (split
&& split
!= &SET_SRC (x
))
2177 /* See if this is a simple operation with a constant as the second
2178 operand. It might be that this constant is out of range and hence
2179 could be used as a split point. */
2180 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
2181 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
2182 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
2183 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
2184 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
2185 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
2186 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
2188 return &XEXP (SET_SRC (x
), 1);
2190 /* Finally, see if this is a simple operation with its first operand
2191 not in a register. The operation might require this operand in a
2192 register, so return it as a split point. We can always do this
2193 because if the first operand were another operation, we would have
2194 already found it as a split point. */
2195 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
2196 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
2197 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
2198 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
2199 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
2200 return &XEXP (SET_SRC (x
), 0);
2206 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2207 it is better to write this as (not (ior A B)) so we can split it.
2208 Similarly for IOR. */
2209 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
2212 gen_rtx_combine (NOT
, GET_MODE (x
),
2213 gen_rtx_combine (code
== IOR
? AND
: IOR
,
2215 XEXP (XEXP (x
, 0), 0),
2216 XEXP (XEXP (x
, 1), 0))));
2217 return find_split_point (loc
);
2220 /* Many RISC machines have a large set of logical insns. If the
2221 second operand is a NOT, put it first so we will try to split the
2222 other operand first. */
2223 if (GET_CODE (XEXP (x
, 1)) == NOT
)
2225 rtx tem
= XEXP (x
, 0);
2226 SUBST (XEXP (x
, 0), XEXP (x
, 1));
2227 SUBST (XEXP (x
, 1), tem
);
2232 /* Otherwise, select our actions depending on our rtx class. */
2233 switch (GET_RTX_CLASS (code
))
2235 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2237 split
= find_split_point (&XEXP (x
, 2));
2240 /* ... fall through ... */
2244 split
= find_split_point (&XEXP (x
, 1));
2247 /* ... fall through ... */
2249 /* Some machines have (and (shift ...) ...) insns. If X is not
2250 an AND, but XEXP (X, 0) is, use it as our split point. */
2251 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
2252 return &XEXP (x
, 0);
2254 split
= find_split_point (&XEXP (x
, 0));
2260 /* Otherwise, we don't have a split point. */
2264 /* Throughout X, replace FROM with TO, and return the result.
2265 The result is TO if X is FROM;
2266 otherwise the result is X, but its contents may have been modified.
2267 If they were modified, a record was made in undobuf so that
2268 undo_all will (among other things) return X to its original state.
2270 If the number of changes necessary is too much to record to undo,
2271 the excess changes are not made, so the result is invalid.
2272 The changes already made can still be undone.
2273 undobuf.num_undo is incremented for such changes, so by testing that
2274 the caller can tell whether the result is valid.
2276 `n_occurrences' is incremented each time FROM is replaced.
2278 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2280 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2281 by copying if `n_occurrences' is non-zero. */
2284 subst (x
, from
, to
, in_dest
, unique_copy
)
2285 register rtx x
, from
, to
;
2290 register int len
, i
;
2291 register enum rtx_code code
= GET_CODE (x
), orig_code
= code
;
2293 enum machine_mode mode
= GET_MODE (x
);
2294 enum machine_mode op0_mode
= VOIDmode
;
2299 /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe
2300 replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM).
2301 If it is 0, that cannot be done. We can now do this for any MEM
2302 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded.
2303 If not for that, MEM's would very rarely be safe. */
2305 /* Reject MODEs bigger than a word, because we might not be able
2306 to reference a two-register group starting with an arbitrary register
2307 (and currently gen_lowpart might crash for a SUBREG). */
2309 #define FAKE_EXTEND_SAFE_P(MODE, FROM) \
2310 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
2312 /* Two expressions are equal if they are identical copies of a shared
2313 RTX or if they are both registers with the same register number
2316 #define COMBINE_RTX_EQUAL_P(X,Y) \
2318 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2319 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2321 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
2324 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
2327 /* If X and FROM are the same register but different modes, they will
2328 not have been seen as equal above. However, flow.c will make a
2329 LOG_LINKS entry for that case. If we do nothing, we will try to
2330 rerecognize our original insn and, when it succeeds, we will
2331 delete the feeding insn, which is incorrect.
2333 So force this insn not to match in this (rare) case. */
2334 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
2335 && REGNO (x
) == REGNO (from
))
2336 return gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
2338 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2339 of which may contain things that can be combined. */
2340 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
2343 /* It is possible to have a subexpression appear twice in the insn.
2344 Suppose that FROM is a register that appears within TO.
2345 Then, after that subexpression has been scanned once by `subst',
2346 the second time it is scanned, TO may be found. If we were
2347 to scan TO here, we would find FROM within it and create a
2348 self-referent rtl structure which is completely wrong. */
2349 if (COMBINE_RTX_EQUAL_P (x
, to
))
2352 len
= GET_RTX_LENGTH (code
);
2353 fmt
= GET_RTX_FORMAT (code
);
2355 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2356 set up to skip this common case. All other cases where we want to
2357 suppress replacing something inside a SET_SRC are handled via the
2360 && (GET_CODE (SET_DEST (x
)) == REG
2361 || GET_CODE (SET_DEST (x
)) == CC0
2362 || GET_CODE (SET_DEST (x
)) == PC
))
2365 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2367 op0_mode
= GET_MODE (XEXP (x
, 0));
2369 for (i
= 0; i
< len
; i
++)
2374 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2377 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
2379 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
2384 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0, unique_copy
);
2386 /* If this substitution failed, this whole thing fails. */
2387 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
2391 SUBST (XVECEXP (x
, i
, j
), new);
2394 else if (fmt
[i
] == 'e')
2398 if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
2400 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
2404 /* If we are in a SET_DEST, suppress most cases unless we
2405 have gone inside a MEM, in which case we want to
2406 simplify the address. We assume here that things that
2407 are actually part of the destination have their inner
2408 parts in the first expression. This is true for SUBREG,
2409 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2410 things aside from REG and MEM that should appear in a
2412 new = subst (XEXP (x
, i
), from
, to
,
2414 && (code
== SUBREG
|| code
== STRICT_LOW_PART
2415 || code
== ZERO_EXTRACT
))
2417 && i
== 0), unique_copy
);
2419 /* If we found that we will have to reject this combination,
2420 indicate that by returning the CLOBBER ourselves, rather than
2421 an expression containing it. This will speed things up as
2422 well as prevent accidents where two CLOBBERs are considered
2423 to be equal, thus producing an incorrect simplification. */
2425 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
2428 SUBST (XEXP (x
, i
), new);
2432 /* If this is a commutative operation, put a constant last and a complex
2433 expression first. We don't need to do this for comparisons here. */
2434 if (GET_RTX_CLASS (code
) == 'c'
2435 && ((CONSTANT_P (XEXP (x
, 0)) && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
2436 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == 'o'
2437 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')
2438 || (GET_CODE (XEXP (x
, 0)) == SUBREG
2439 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == 'o'
2440 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')))
2443 SUBST (XEXP (x
, 0), XEXP (x
, 1));
2444 SUBST (XEXP (x
, 1), temp
);
2447 /* Try to fold this expression in case we have constants that weren't
2450 switch (GET_RTX_CLASS (code
))
2453 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
2456 temp
= simplify_relational_operation (code
, op0_mode
,
2457 XEXP (x
, 0), XEXP (x
, 1));
2458 #ifdef FLOAT_STORE_FLAG_VALUE
2459 if (temp
!= 0 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2460 temp
= ((temp
== const0_rtx
) ? CONST0_RTX (GET_MODE (x
))
2461 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE
, GET_MODE (x
)));
2466 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
2470 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
2471 XEXP (x
, 1), XEXP (x
, 2));
2478 /* We come back to here if we have replaced the expression with one of
2479 a different code and it is likely that further simplification will be
2484 /* If we have restarted more than 4 times, we are probably looping, so
2486 if (++n_restarts
> 4)
2489 code
= GET_CODE (x
);
2491 /* First see if we can apply the inverse distributive law. */
2492 if (code
== PLUS
|| code
== MINUS
|| code
== IOR
|| code
== XOR
)
2494 x
= apply_distributive_law (x
);
2495 code
= GET_CODE (x
);
2498 /* If CODE is an associative operation not otherwise handled, see if we
2499 can associate some operands. This can win if they are constants or
2500 if they are logically related (i.e. (a & b) & a. */
2501 if ((code
== PLUS
|| code
== MINUS
2502 || code
== MULT
|| code
== AND
|| code
== IOR
|| code
== XOR
2503 || code
== DIV
|| code
== UDIV
2504 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
2505 && GET_MODE_CLASS (mode
) == MODE_INT
)
2507 if (GET_CODE (XEXP (x
, 0)) == code
)
2509 rtx other
= XEXP (XEXP (x
, 0), 0);
2510 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
2511 rtx inner_op1
= XEXP (x
, 1);
2514 /* Make sure we pass the constant operand if any as the second
2515 one if this is a commutative operation. */
2516 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
2518 rtx tem
= inner_op0
;
2519 inner_op0
= inner_op1
;
2522 inner
= simplify_binary_operation (code
== MINUS
? PLUS
2523 : code
== DIV
? MULT
2524 : code
== UDIV
? MULT
2526 mode
, inner_op0
, inner_op1
);
2528 /* For commutative operations, try the other pair if that one
2530 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
2532 other
= XEXP (XEXP (x
, 0), 1);
2533 inner
= simplify_binary_operation (code
, mode
,
2534 XEXP (XEXP (x
, 0), 0),
2540 x
= gen_binary (code
, mode
, other
, inner
);
2547 /* A little bit of algebraic simplification here. */
2551 /* Ensure that our address has any ASHIFTs converted to MULT in case
2552 address-recognizing predicates are called later. */
2553 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
2554 SUBST (XEXP (x
, 0), temp
);
2558 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
2559 is paradoxical. If we can't do that safely, then it becomes
2560 something nonsensical so that this combination won't take place. */
2562 if (GET_CODE (SUBREG_REG (x
)) == MEM
2563 && (GET_MODE_SIZE (mode
)
2564 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
2566 rtx inner
= SUBREG_REG (x
);
2567 int endian_offset
= 0;
2568 /* Don't change the mode of the MEM
2569 if that would change the meaning of the address. */
2570 if (MEM_VOLATILE_P (SUBREG_REG (x
))
2571 || mode_dependent_address_p (XEXP (inner
, 0)))
2572 return gen_rtx (CLOBBER
, mode
, const0_rtx
);
2574 #if BYTES_BIG_ENDIAN
2575 if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
2576 endian_offset
+= UNITS_PER_WORD
- GET_MODE_SIZE (mode
);
2577 if (GET_MODE_SIZE (GET_MODE (inner
)) < UNITS_PER_WORD
)
2578 endian_offset
-= UNITS_PER_WORD
- GET_MODE_SIZE (GET_MODE (inner
));
2580 /* Note if the plus_constant doesn't make a valid address
2581 then this combination won't be accepted. */
2582 x
= gen_rtx (MEM
, mode
,
2583 plus_constant (XEXP (inner
, 0),
2584 (SUBREG_WORD (x
) * UNITS_PER_WORD
2586 MEM_VOLATILE_P (x
) = MEM_VOLATILE_P (inner
);
2587 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (inner
);
2588 MEM_IN_STRUCT_P (x
) = MEM_IN_STRUCT_P (inner
);
2592 /* If we are in a SET_DEST, these other cases can't apply. */
2596 /* Changing mode twice with SUBREG => just change it once,
2597 or not at all if changing back to starting mode. */
2598 if (GET_CODE (SUBREG_REG (x
)) == SUBREG
)
2600 if (mode
== GET_MODE (SUBREG_REG (SUBREG_REG (x
)))
2601 && SUBREG_WORD (x
) == 0 && SUBREG_WORD (SUBREG_REG (x
)) == 0)
2602 return SUBREG_REG (SUBREG_REG (x
));
2604 SUBST_INT (SUBREG_WORD (x
),
2605 SUBREG_WORD (x
) + SUBREG_WORD (SUBREG_REG (x
)));
2606 SUBST (SUBREG_REG (x
), SUBREG_REG (SUBREG_REG (x
)));
2609 /* SUBREG of a hard register => just change the register number
2610 and/or mode. If the hard register is not valid in that mode,
2611 suppress this combination. */
2613 if (GET_CODE (SUBREG_REG (x
)) == REG
2614 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
)
2616 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
),
2618 return gen_rtx (REG
, mode
,
2619 REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
));
2621 return gen_rtx (CLOBBER
, mode
, const0_rtx
);
2624 /* For a constant, try to pick up the part we want. Handle a full
2625 word and low-order part. Only do this if we are narrowing
2626 the constant; if it is being widened, we have no idea what
2627 the extra bits will have been set to. */
2629 if (CONSTANT_P (SUBREG_REG (x
)) && op0_mode
!= VOIDmode
2630 && GET_MODE_SIZE (mode
) == UNITS_PER_WORD
2631 && GET_MODE_SIZE (op0_mode
) < UNITS_PER_WORD
2632 && GET_MODE_CLASS (mode
) == MODE_INT
)
2634 temp
= operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
),
2640 if (CONSTANT_P (SUBREG_REG (x
)) && subreg_lowpart_p (x
)
2641 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (op0_mode
))
2642 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
2644 /* If we are narrowing the object, we need to see if we can simplify
2645 the expression for the object knowing that we only need the
2646 low-order bits. We do this by computing an AND of the object
2647 with only the bits we care about. That will produce any needed
2648 simplifications. If the resulting computation is just the
2649 AND with the significant bits, our operand is the first operand
2650 of the AND. Otherwise, it is the resulting expression. */
2651 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))
2652 && subreg_lowpart_p (x
)
2653 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= HOST_BITS_PER_INT
)
2655 temp
= simplify_and_const_int (0, GET_MODE (SUBREG_REG (x
)),
2656 SUBREG_REG (x
), GET_MODE_MASK (mode
));
2657 if (GET_CODE (temp
) == AND
&& GET_CODE (XEXP (temp
, 1)) == CONST_INT
2658 && INTVAL (XEXP (temp
, 1)) == GET_MODE_MASK (mode
))
2659 temp
= XEXP (temp
, 0);
2660 return gen_lowpart_for_combine (mode
, temp
);
2666 /* (not (plus X -1)) can become (neg X). */
2667 if (GET_CODE (XEXP (x
, 0)) == PLUS
2668 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
2670 x
= gen_rtx_combine (NEG
, mode
, XEXP (XEXP (x
, 0), 0));
2674 /* Similarly, (not (neg X)) is (plus X -1). */
2675 if (GET_CODE (XEXP (x
, 0)) == NEG
)
2677 x
= gen_rtx_combine (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
2681 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
2682 other than 1, but that is not valid. We could do a similar
2683 simplification for (not (lshiftrt C X)) where C is just the sign bit,
2684 but this doesn't seem common enough to bother with. */
2685 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
2686 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
2688 x
= gen_rtx (ROTATE
, mode
, gen_unary (NOT
, mode
, const1_rtx
),
2689 XEXP (XEXP (x
, 0), 1));
2693 if (GET_CODE (XEXP (x
, 0)) == SUBREG
2694 && subreg_lowpart_p (XEXP (x
, 0))
2695 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
2696 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
2697 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
2698 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
2700 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
2702 x
= gen_rtx (ROTATE
, inner_mode
,
2703 gen_unary (NOT
, inner_mode
, const1_rtx
),
2704 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
2705 x
= gen_lowpart_for_combine (mode
, x
);
2709 #if STORE_FLAG_VALUE == -1
2710 /* (not (comparison foo bar)) can be done by reversing the comparison
2712 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
2713 && reversible_comparison_p (XEXP (x
, 0)))
2714 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x
, 0))),
2715 mode
, XEXP (XEXP (x
, 0), 0),
2716 XEXP (XEXP (x
, 0), 1));
2719 /* Apply De Morgan's laws to reduce number of patterns for machines
2720 with negating logical insns (and-not, nand, etc.). If result has
2721 only one NOT, put it first, since that is how the patterns are
2724 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
2726 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
2728 if (GET_CODE (in1
) == NOT
)
2729 in1
= XEXP (in1
, 0);
2731 in1
= gen_rtx_combine (NOT
, GET_MODE (in1
), in1
);
2733 if (GET_CODE (in2
) == NOT
)
2734 in2
= XEXP (in2
, 0);
2735 else if (GET_CODE (in2
) == CONST_INT
2736 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_INT
)
2737 in2
= gen_rtx (CONST_INT
, VOIDmode
,
2738 GET_MODE_MASK (mode
) & ~ INTVAL (in2
));
2740 in2
= gen_rtx_combine (NOT
, GET_MODE (in2
), in2
);
2742 if (GET_CODE (in2
) == NOT
)
2745 in2
= in1
; in1
= tem
;
2748 x
= gen_rtx_combine (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
2755 /* (neg (plus X 1)) can become (not X). */
2756 if (GET_CODE (XEXP (x
, 0)) == PLUS
2757 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
2759 x
= gen_rtx_combine (NOT
, mode
, XEXP (XEXP (x
, 0), 0));
2763 /* Similarly, (neg (not X)) is (plus X 1). */
2764 if (GET_CODE (XEXP (x
, 0)) == NOT
)
2766 x
= gen_rtx_combine (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), const1_rtx
);
2770 /* (neg (abs X)) is X if X is a value known to be either -1 or 0. */
2771 if (GET_CODE (XEXP (x
, 0)) == ABS
2772 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTRACT
2773 && XEXP (XEXP (XEXP (x
, 0), 0), 1) == const1_rtx
)
2774 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ASHIFTRT
2775 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
2776 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
2777 == GET_MODE_BITSIZE (mode
) - 1))
2778 || ((temp
= get_last_value (XEXP (XEXP (x
, 0), 0))) != 0
2779 && ((GET_CODE (temp
) == SIGN_EXTRACT
2780 && XEXP (temp
, 1) == const1_rtx
)
2781 || (GET_CODE (temp
) == ASHIFTRT
2782 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
2783 && (INTVAL (XEXP (temp
, 1))
2784 == GET_MODE_BITSIZE (mode
) - 1))))))
2785 return XEXP (XEXP (x
, 0), 0);
2787 /* (neg (minus X Y)) can become (minus Y X). */
2788 if (GET_CODE (XEXP (x
, 0)) == MINUS
2789 && (GET_MODE_CLASS (mode
) != MODE_FLOAT
2790 /* x-y != -(y-x) with IEEE floating point. */
2791 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
))
2793 x
= gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
2794 XEXP (XEXP (x
, 0), 0));
2798 /* NEG commutes with ASHIFT since it is multiplication. Only do this
2799 if we can then eliminate the NEG (e.g.,
2800 if the operand is a constant). */
2802 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
2804 temp
= simplify_unary_operation (NEG
, mode
,
2805 XEXP (XEXP (x
, 0), 0), mode
);
2808 SUBST (XEXP (XEXP (x
, 0), 0), temp
);
2813 temp
= expand_compound_operation (XEXP (x
, 0));
2815 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
2816 replaced by (lshiftrt X C). This will convert
2817 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
2819 if (GET_CODE (temp
) == ASHIFTRT
2820 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
2821 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
2823 x
= simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
2824 INTVAL (XEXP (temp
, 1)));
2828 /* If X has only a single bit significant, say, bit I, convert
2829 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
2830 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
2831 (sign_extract X 1 Y). But only do this if TEMP isn't a register
2832 or a SUBREG of one since we'd be making the expression more
2833 complex if it was just a register. */
2835 if (GET_CODE (temp
) != REG
2836 && ! (GET_CODE (temp
) == SUBREG
2837 && GET_CODE (SUBREG_REG (temp
)) == REG
)
2838 && (i
= exact_log2 (significant_bits (temp
, mode
))) >= 0)
2840 rtx temp1
= simplify_shift_const
2842 simplify_shift_const (0, ASHIFT
, mode
, temp
,
2843 GET_MODE_BITSIZE (mode
) - 1 - i
),
2844 GET_MODE_BITSIZE (mode
) - 1 - i
);
2846 /* If all we did was surround TEMP with the two shifts, we
2847 haven't improved anything, so don't use it. Otherwise,
2848 we are better off with TEMP1. */
2849 if (GET_CODE (temp1
) != ASHIFTRT
2850 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
2851 || XEXP (XEXP (temp1
, 0), 0) != temp
)
2859 case FLOAT_TRUNCATE
:
2860 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
2861 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
2862 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
2863 return XEXP (XEXP (x
, 0), 0);
2868 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
2869 using cc0, in which case we want to leave it as a COMPARE
2870 so we can distinguish it from a register-register-copy. */
2871 if (XEXP (x
, 1) == const0_rtx
)
2874 /* In IEEE floating point, x-0 is not the same as x. */
2875 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
2876 || GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) == MODE_INT
)
2877 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
2883 /* (const (const X)) can become (const X). Do it this way rather than
2884 returning the inner CONST since CONST can be shared with a
2886 if (GET_CODE (XEXP (x
, 0)) == CONST
)
2887 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
2892 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
2893 can add in an offset. find_split_point will split this address up
2894 again if it doesn't match. */
2895 if (GET_CODE (XEXP (x
, 0)) == HIGH
2896 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
2902 /* If we have (plus (plus (A const) B)), associate it so that CONST is
2903 outermost. That's because that's the way indexed addresses are
2904 supposed to appear. This code used to check many more cases, but
2905 they are now checked elsewhere. */
2906 if (GET_CODE (XEXP (x
, 0)) == PLUS
2907 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
2908 return gen_binary (PLUS
, mode
,
2909 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
2911 XEXP (XEXP (x
, 0), 1));
2913 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
2914 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
2915 bit-field and can be replaced by either a sign_extend or a
2916 sign_extract. The `and' may be a zero_extend. */
2917 if (GET_CODE (XEXP (x
, 0)) == XOR
2918 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2919 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2920 && INTVAL (XEXP (x
, 1)) == - INTVAL (XEXP (XEXP (x
, 0), 1))
2921 && (i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
2922 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_INT
2923 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
2924 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
2925 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
2926 == (1 << (i
+ 1)) - 1))
2927 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
2928 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
2931 x
= simplify_shift_const
2933 simplify_shift_const (0, ASHIFT
, mode
,
2934 XEXP (XEXP (XEXP (x
, 0), 0), 0),
2935 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
2936 GET_MODE_BITSIZE (mode
) - (i
+ 1));
2940 /* If only the low-order bit of X is significant, (plus x -1)
2941 can become (ashiftrt (ashift (xor x 1) C) C) where C is
2942 the bitsize of the mode - 1. This allows simplification of
2943 "a = (b & 8) == 0;" */
2944 if (XEXP (x
, 1) == constm1_rtx
2945 && GET_CODE (XEXP (x
, 0)) != REG
2946 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
2947 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
2948 && significant_bits (XEXP (x
, 0), mode
) == 1)
2950 x
= simplify_shift_const
2952 simplify_shift_const (0, ASHIFT
, mode
,
2953 gen_rtx_combine (XOR
, mode
,
2954 XEXP (x
, 0), const1_rtx
),
2955 GET_MODE_BITSIZE (mode
) - 1),
2956 GET_MODE_BITSIZE (mode
) - 1);
2960 /* If we are adding two things that have no bits in common, convert
2961 the addition into an IOR. This will often be further simplified,
2962 for example in cases like ((a & 1) + (a & 2)), which can
2965 if ((significant_bits (XEXP (x
, 0), mode
)
2966 & significant_bits (XEXP (x
, 1), mode
)) == 0)
2968 x
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
2974 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
2975 (and <foo> (const_int pow2-1)) */
2976 if (GET_CODE (XEXP (x
, 1)) == AND
2977 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
2978 && exact_log2 (- INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
2979 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
2981 x
= simplify_and_const_int (0, mode
, XEXP (x
, 0),
2982 - INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
2988 /* If we have (mult (plus A B) C), apply the distributive law and then
2989 the inverse distributive law to see if things simplify. This
2990 occurs mostly in addresses, often when unrolling loops. */
2992 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
2994 x
= apply_distributive_law
2995 (gen_binary (PLUS
, mode
,
2996 gen_binary (MULT
, mode
,
2997 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
2998 gen_binary (MULT
, mode
,
2999 XEXP (XEXP (x
, 0), 1), XEXP (x
, 1))));
3001 if (GET_CODE (x
) != MULT
)
3005 /* If this is multiplication by a power of two and its first operand is
3006 a shift, treat the multiply as a shift to allow the shifts to
3007 possibly combine. */
3008 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
3009 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
3010 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
3011 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3012 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3013 || GET_CODE (XEXP (x
, 0)) == ROTATE
3014 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
3016 x
= simplify_shift_const (0, ASHIFT
, mode
, XEXP (x
, 0), i
);
3020 /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */
3021 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3022 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3023 return gen_rtx_combine (ASHIFT
, mode
, XEXP (x
, 1),
3024 XEXP (XEXP (x
, 0), 1));
3028 /* If this is a divide by a power of two, treat it as a shift if
3029 its first operand is a shift. */
3030 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
3031 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
3032 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
3033 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3034 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3035 || GET_CODE (XEXP (x
, 0)) == ROTATE
3036 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
3038 x
= simplify_shift_const (0, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
3044 case GT
: case GTU
: case GE
: case GEU
:
3045 case LT
: case LTU
: case LE
: case LEU
:
3046 /* If the first operand is a condition code, we can't do anything
3048 if (GET_CODE (XEXP (x
, 0)) == COMPARE
3049 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
3051 && XEXP (x
, 0) != cc0_rtx
3055 rtx op0
= XEXP (x
, 0);
3056 rtx op1
= XEXP (x
, 1);
3057 enum rtx_code new_code
;
3059 if (GET_CODE (op0
) == COMPARE
)
3060 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
3062 /* Simplify our comparison, if possible. */
3063 new_code
= simplify_comparison (code
, &op0
, &op1
);
3065 #if STORE_FLAG_VALUE == 1
3066 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3067 if only the low-order bit is significant in X (such as when
3068 X is a ZERO_EXTRACT of one bit. Similarly, we can convert
3070 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
3071 && op1
== const0_rtx
3072 && significant_bits (op0
, GET_MODE (op0
)) == 1)
3073 return gen_lowpart_for_combine (mode
, op0
);
3074 else if (new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
3075 && op1
== const0_rtx
3076 && significant_bits (op0
, GET_MODE (op0
)) == 1)
3077 return gen_rtx_combine (XOR
, mode
,
3078 gen_lowpart_for_combine (mode
, op0
),
3082 #if STORE_FLAG_VALUE == -1
3083 /* If STORE_FLAG_VALUE is -1, we can convert (ne x 0)
3084 to (neg x) if only the low-order bit of X is significant.
3085 This converts (ne (zero_extract X 1 Y) 0) to
3086 (sign_extract X 1 Y). */
3087 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
3088 && op1
== const0_rtx
3089 && significant_bits (op0
, GET_MODE (op0
)) == 1)
3091 x
= gen_rtx_combine (NEG
, mode
,
3092 gen_lowpart_for_combine (mode
, op0
));
3097 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3098 one significant bit, we can convert (ne x 0) to (ashift x c)
3099 where C puts the bit in the sign bit. Remove any AND with
3100 STORE_FLAG_VALUE when we are done, since we are only going to
3101 test the sign bit. */
3102 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
3103 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_INT
3104 && STORE_FLAG_VALUE
== 1 << (GET_MODE_BITSIZE (mode
) - 1)
3105 && op1
== const0_rtx
3106 && mode
== GET_MODE (op0
)
3107 && (i
= exact_log2 (significant_bits (op0
, GET_MODE (op0
)))) >= 0)
3109 x
= simplify_shift_const (0, ASHIFT
, mode
, op0
,
3110 GET_MODE_BITSIZE (mode
) - 1 - i
);
3111 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
3117 /* If the code changed, return a whole new comparison. */
3118 if (new_code
!= code
)
3119 return gen_rtx_combine (new_code
, mode
, op0
, op1
);
3121 /* Otherwise, keep this operation, but maybe change its operands.
3122 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3123 SUBST (XEXP (x
, 0), op0
);
3124 SUBST (XEXP (x
, 1), op1
);
3129 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
3130 reversed, do so to avoid needing two sets of patterns for
3131 subtract-and-branch insns. */
3132 if (XEXP (x
, 1) == pc_rtx
3133 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3134 && reversible_comparison_p (XEXP (x
, 0)))
3137 gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x
, 0))),
3138 GET_MODE (XEXP (x
, 0)),
3139 XEXP (XEXP (x
, 0), 0),
3140 XEXP (XEXP (x
, 0), 1)));
3141 SUBST (XEXP (x
, 1), XEXP (x
, 2));
3142 SUBST (XEXP (x
, 2), pc_rtx
);
3150 /* If we are processing SET_DEST, we are done. */
3154 x
= expand_compound_operation (x
);
3155 if (GET_CODE (x
) != code
)
3160 /* (set (pc) (return)) gets written as (return). */
3161 if (GET_CODE (SET_DEST (x
)) == PC
&& GET_CODE (SET_SRC (x
)) == RETURN
)
3164 /* Convert this into a field assignment operation, if possible. */
3165 x
= make_field_assignment (x
);
3167 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some
3168 operation, and X being a REG or (subreg (reg)), we may be able to
3169 convert this to (set (subreg:m2 x) (op)).
3171 We can always do this if M1 is narrower than M2 because that
3172 means that we only care about the low bits of the result.
3174 However, on most machines (those with BYTE_LOADS_ZERO_EXTEND
3175 not defined), we cannot perform a narrower operation that
3176 requested since the high-order bits will be undefined. On
3177 machine where BYTE_LOADS_ZERO_EXTEND are defined, however, this
3178 transformation is safe as long as M1 and M2 have the same number
3181 if (GET_CODE (SET_SRC (x
)) == SUBREG
3182 && subreg_lowpart_p (SET_SRC (x
))
3183 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) != 'o'
3184 && (((GET_MODE_SIZE (GET_MODE (SET_SRC (x
))) + (UNITS_PER_WORD
- 1))
3186 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x
))))
3187 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
3188 #ifndef BYTE_LOADS_ZERO_EXTEND
3189 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x
)))
3190 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x
)))))
3192 && (GET_CODE (SET_DEST (x
)) == REG
3193 || (GET_CODE (SET_DEST (x
)) == SUBREG
3194 && GET_CODE (SUBREG_REG (SET_DEST (x
))) == REG
)))
3196 /* Get the object that will be the SUBREG_REG of the
3197 SUBREG we are making. Note that SUBREG_WORD will always
3198 be zero because this will either be a paradoxical SUBREG
3199 or a SUBREG with the same number of words on the outside and
3201 rtx object
= (GET_CODE (SET_DEST (x
)) == REG
? SET_DEST (x
)
3202 : SUBREG_REG (SET_DEST (x
)));
3204 SUBST (SET_DEST (x
),
3205 gen_rtx (SUBREG
, GET_MODE (SUBREG_REG (SET_SRC (x
))),
3207 SUBST (SET_SRC (x
), SUBREG_REG (SET_SRC (x
)));
3210 /* If we are setting CC0 or if the source is a COMPARE, look for the
3211 use of the comparison result and try to simplify it unless we already
3212 have used undobuf.other_insn. */
3213 if ((GET_CODE (SET_SRC (x
)) == COMPARE
3215 || SET_DEST (x
) == cc0_rtx
3218 && (cc_use
= find_single_use (SET_DEST (x
), subst_insn
,
3220 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
3221 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
3222 && XEXP (*cc_use
, 0) == SET_DEST (x
))
3224 enum rtx_code old_code
= GET_CODE (*cc_use
);
3225 enum rtx_code new_code
;
3227 int other_changed
= 0;
3228 enum machine_mode compare_mode
= GET_MODE (SET_DEST (x
));
3230 if (GET_CODE (SET_SRC (x
)) == COMPARE
)
3231 op0
= XEXP (SET_SRC (x
), 0), op1
= XEXP (SET_SRC (x
), 1);
3233 op0
= SET_SRC (x
), op1
= const0_rtx
;
3235 /* Simplify our comparison, if possible. */
3236 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
3238 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
3239 /* If this machine has CC modes other than CCmode, check to see
3240 if we need to use a different CC mode here. */
3241 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
3243 /* If the mode changed, we have to change SET_DEST, the mode
3244 in the compare, and the mode in the place SET_DEST is used.
3245 If SET_DEST is a hard register, just build new versions with
3246 the proper mode. If it is a pseudo, we lose unless it is only
3247 time we set the pseudo, in which case we can safely change
3249 if (compare_mode
!= GET_MODE (SET_DEST (x
)))
3251 int regno
= REGNO (SET_DEST (x
));
3252 rtx new_dest
= gen_rtx (REG
, compare_mode
, regno
);
3254 if (regno
< FIRST_PSEUDO_REGISTER
3255 || (reg_n_sets
[regno
] == 1
3256 && ! REG_USERVAR_P (SET_DEST (x
))))
3258 if (regno
>= FIRST_PSEUDO_REGISTER
)
3259 SUBST (regno_reg_rtx
[regno
], new_dest
);
3261 SUBST (SET_DEST (x
), new_dest
);
3262 SUBST (XEXP (*cc_use
, 0), new_dest
);
3268 /* If the code changed, we have to build a new comparison
3269 in undobuf.other_insn. */
3270 if (new_code
!= old_code
)
3274 SUBST (*cc_use
, gen_rtx_combine (new_code
, GET_MODE (*cc_use
),
3275 SET_DEST (x
), const0_rtx
));
3277 /* If the only change we made was to change an EQ into an
3278 NE or vice versa, OP0 has only one significant bit,
3279 and OP1 is zero, check if changing the user of the condition
3280 code will produce a valid insn. If it won't, we can keep
3281 the original code in that insn by surrounding our operation
3284 if (((old_code
== NE
&& new_code
== EQ
)
3285 || (old_code
== EQ
&& new_code
== NE
))
3286 && ! other_changed
&& op1
== const0_rtx
3287 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_INT
3288 && (exact_log2 (mask
= significant_bits (op0
,
3292 rtx pat
= PATTERN (other_insn
), note
= 0;
3294 if ((recog_for_combine (&pat
, undobuf
.other_insn
, ¬e
) < 0
3295 && ! check_asm_operands (pat
)))
3297 PUT_CODE (*cc_use
, old_code
);
3300 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
,
3301 gen_rtx (CONST_INT
, VOIDmode
, mask
));
3309 undobuf
.other_insn
= other_insn
;
3312 /* If we are now comparing against zero, change our source if
3313 needed. If we do not use cc0, we always have a COMPARE. */
3314 if (op1
== const0_rtx
&& SET_DEST (x
) == cc0_rtx
)
3315 SUBST (SET_SRC (x
), op0
);
3319 /* Otherwise, if we didn't previously have a COMPARE in the
3320 correct mode, we need one. */
3321 if (GET_CODE (SET_SRC (x
)) != COMPARE
3322 || GET_MODE (SET_SRC (x
)) != compare_mode
)
3323 SUBST (SET_SRC (x
), gen_rtx_combine (COMPARE
, compare_mode
,
3327 /* Otherwise, update the COMPARE if needed. */
3328 SUBST (XEXP (SET_SRC (x
), 0), op0
);
3329 SUBST (XEXP (SET_SRC (x
), 1), op1
);
3334 /* Get SET_SRC in a form where we have placed back any
3335 compound expressions. Then do the checks below. */
3336 temp
= make_compound_operation (SET_SRC (x
), SET
);
3337 SUBST (SET_SRC (x
), temp
);
3340 #ifdef BYTE_LOADS_ZERO_EXTEND
3341 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with
3342 M wider than N, this would require a paradoxical subreg.
3343 Replace the subreg with a zero_extend to avoid the reload that
3344 would otherwise be required. */
3345 if (GET_CODE (SET_SRC (x
)) == SUBREG
3346 && subreg_lowpart_p (SET_SRC (x
))
3347 && SUBREG_WORD (SET_SRC (x
)) == 0
3348 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x
)))
3349 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x
)))))
3350 && GET_CODE (SUBREG_REG (SET_SRC (x
))) == MEM
)
3351 SUBST (SET_SRC (x
), gen_rtx_combine (ZERO_EXTEND
,
3352 GET_MODE (SET_SRC (x
)),
3353 XEXP (SET_SRC (x
), 0)));
3359 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3361 x
= simplify_and_const_int (x
, mode
, XEXP (x
, 0),
3362 INTVAL (XEXP (x
, 1)));
3364 /* If we have (ior (and (X C1) C2)) and the next restart would be
3365 the last, simplify this by making C1 as small as possible
3367 if (n_restarts
>= 3 && GET_CODE (x
) == IOR
3368 && GET_CODE (XEXP (x
, 0)) == AND
3369 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3370 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3372 temp
= gen_binary (AND
, mode
, XEXP (XEXP (x
, 0), 0),
3373 gen_rtx (CONST_INT
, VOIDmode
,
3374 (INTVAL (XEXP (XEXP (x
, 0), 1))
3375 & ~ INTVAL (XEXP (x
, 1)))));
3376 return gen_binary (IOR
, mode
, temp
, XEXP (x
, 1));
3379 if (GET_CODE (x
) != AND
)
3383 /* Convert (A | B) & A to A. */
3384 if (GET_CODE (XEXP (x
, 0)) == IOR
3385 && (rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1))
3386 || rtx_equal_p (XEXP (XEXP (x
, 0), 1), XEXP (x
, 1)))
3387 && ! side_effects_p (XEXP (XEXP (x
, 0), 0))
3388 && ! side_effects_p (XEXP (XEXP (x
, 0), 1)))
3391 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
3392 insn (and may simplify more). */
3393 else if (GET_CODE (XEXP (x
, 0)) == XOR
3394 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1))
3395 && ! side_effects_p (XEXP (x
, 1)))
3397 x
= gen_binary (AND
, mode
,
3398 gen_unary (NOT
, mode
, XEXP (XEXP (x
, 0), 1)),
3402 else if (GET_CODE (XEXP (x
, 0)) == XOR
3403 && rtx_equal_p (XEXP (XEXP (x
, 0), 1), XEXP (x
, 1))
3404 && ! side_effects_p (XEXP (x
, 1)))
3406 x
= gen_binary (AND
, mode
,
3407 gen_unary (NOT
, mode
, XEXP (XEXP (x
, 0), 0)),
3412 /* Similarly for (~ (A ^ B)) & A. */
3413 else if (GET_CODE (XEXP (x
, 0)) == NOT
3414 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == XOR
3415 && rtx_equal_p (XEXP (XEXP (XEXP (x
, 0), 0), 0), XEXP (x
, 1))
3416 && ! side_effects_p (XEXP (x
, 1)))
3418 x
= gen_binary (AND
, mode
, XEXP (XEXP (XEXP (x
, 0), 0), 1),
3422 else if (GET_CODE (XEXP (x
, 0)) == NOT
3423 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == XOR
3424 && rtx_equal_p (XEXP (XEXP (XEXP (x
, 0), 0), 1), XEXP (x
, 1))
3425 && ! side_effects_p (XEXP (x
, 1)))
3427 x
= gen_binary (AND
, mode
, XEXP (XEXP (XEXP (x
, 0), 0), 0),
3432 /* In the follow group of tests (and those in case IOR below),
3433 we start with some combination of logical operations and apply
3434 the distributive law followed by the inverse distributive law.
3435 Most of the time, this results in no change. However, if some of
3436 the operands are the same or inverses of each other, simplifications
3439 For example, (and (ior A B) (not B)) can occur as the result of
3440 expanding a bit field assignment. When we apply the distributive
3441 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
3442 which then simplifies to (and (A (not B))). */
3444 /* If we have (and (ior A B) C), apply the distributive law and then
3445 the inverse distributive law to see if things simplify. */
3447 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == XOR
)
3449 x
= apply_distributive_law
3450 (gen_binary (GET_CODE (XEXP (x
, 0)), mode
,
3451 gen_binary (AND
, mode
,
3452 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
3453 gen_binary (AND
, mode
,
3454 XEXP (XEXP (x
, 0), 1), XEXP (x
, 1))));
3455 if (GET_CODE (x
) != AND
)
3459 if (GET_CODE (XEXP (x
, 1)) == IOR
|| GET_CODE (XEXP (x
, 1)) == XOR
)
3461 x
= apply_distributive_law
3462 (gen_binary (GET_CODE (XEXP (x
, 1)), mode
,
3463 gen_binary (AND
, mode
,
3464 XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)),
3465 gen_binary (AND
, mode
,
3466 XEXP (XEXP (x
, 1), 1), XEXP (x
, 0))));
3467 if (GET_CODE (x
) != AND
)
3471 /* Similarly, taking advantage of the fact that
3472 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
3474 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == XOR
)
3476 x
= apply_distributive_law
3477 (gen_binary (XOR
, mode
,
3478 gen_binary (IOR
, mode
, XEXP (XEXP (x
, 0), 0),
3479 XEXP (XEXP (x
, 1), 0)),
3480 gen_binary (IOR
, mode
, XEXP (XEXP (x
, 0), 0),
3481 XEXP (XEXP (x
, 1), 1))));
3482 if (GET_CODE (x
) != AND
)
3486 else if (GET_CODE (XEXP (x
, 1)) == NOT
&& GET_CODE (XEXP (x
, 0)) == XOR
)
3488 x
= apply_distributive_law
3489 (gen_binary (XOR
, mode
,
3490 gen_binary (IOR
, mode
, XEXP (XEXP (x
, 1), 0),
3491 XEXP (XEXP (x
, 0), 0)),
3492 gen_binary (IOR
, mode
, XEXP (XEXP (x
, 1), 0),
3493 XEXP (XEXP (x
, 0), 1))));
3494 if (GET_CODE (x
) != AND
)
3500 /* Convert (A & B) | A to A. */
3501 if (GET_CODE (XEXP (x
, 0)) == AND
3502 && (rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1))
3503 || rtx_equal_p (XEXP (XEXP (x
, 0), 1), XEXP (x
, 1)))
3504 && ! side_effects_p (XEXP (XEXP (x
, 0), 0))
3505 && ! side_effects_p (XEXP (XEXP (x
, 0), 1)))
3508 /* If we have (ior (and A B) C), apply the distributive law and then
3509 the inverse distributive law to see if things simplify. */
3511 if (GET_CODE (XEXP (x
, 0)) == AND
)
3513 x
= apply_distributive_law
3514 (gen_binary (AND
, mode
,
3515 gen_binary (IOR
, mode
,
3516 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
3517 gen_binary (IOR
, mode
,
3518 XEXP (XEXP (x
, 0), 1), XEXP (x
, 1))));
3520 if (GET_CODE (x
) != IOR
)
3524 if (GET_CODE (XEXP (x
, 1)) == AND
)
3526 x
= apply_distributive_law
3527 (gen_binary (AND
, mode
,
3528 gen_binary (IOR
, mode
,
3529 XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)),
3530 gen_binary (IOR
, mode
,
3531 XEXP (XEXP (x
, 1), 1), XEXP (x
, 0))));
3533 if (GET_CODE (x
) != IOR
)
3537 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
3538 mode size to (rotate A CX). */
3540 if (((GET_CODE (XEXP (x
, 0)) == ASHIFT
3541 && GET_CODE (XEXP (x
, 1)) == LSHIFTRT
)
3542 || (GET_CODE (XEXP (x
, 1)) == ASHIFT
3543 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
))
3544 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (XEXP (x
, 1), 0))
3545 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3546 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
3547 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + INTVAL (XEXP (XEXP (x
, 1), 1))
3548 == GET_MODE_BITSIZE (mode
)))
3552 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
3553 shift_count
= XEXP (XEXP (x
, 0), 1);
3555 shift_count
= XEXP (XEXP (x
, 1), 1);
3556 x
= gen_rtx (ROTATE
, mode
, XEXP (XEXP (x
, 0), 0), shift_count
);
3562 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
3563 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
3566 int num_negated
= 0;
3567 rtx in1
= XEXP (x
, 0), in2
= XEXP (x
, 1);
3569 if (GET_CODE (in1
) == NOT
)
3570 num_negated
++, in1
= XEXP (in1
, 0);
3571 if (GET_CODE (in2
) == NOT
)
3572 num_negated
++, in2
= XEXP (in2
, 0);
3574 if (num_negated
== 2)
3576 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3577 SUBST (XEXP (x
, 1), XEXP (XEXP (x
, 1), 0));
3579 else if (num_negated
== 1)
3580 return gen_rtx_combine (NOT
, mode
,
3581 gen_rtx_combine (XOR
, mode
, in1
, in2
));
3584 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
3585 correspond to a machine insn or result in further simplifications
3586 if B is a constant. */
3588 if (GET_CODE (XEXP (x
, 0)) == AND
3589 && rtx_equal_p (XEXP (XEXP (x
, 0), 1), XEXP (x
, 1))
3590 && ! side_effects_p (XEXP (x
, 1)))
3592 x
= gen_binary (AND
, mode
,
3593 gen_unary (NOT
, mode
, XEXP (XEXP (x
, 0), 0)),
3597 else if (GET_CODE (XEXP (x
, 0)) == AND
3598 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1))
3599 && ! side_effects_p (XEXP (x
, 1)))
3601 x
= gen_binary (AND
, mode
,
3602 gen_unary (NOT
, mode
, XEXP (XEXP (x
, 0), 1)),
3608 #if STORE_FLAG_VALUE == 1
3609 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
3611 if (XEXP (x
, 1) == const1_rtx
3612 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3613 && reversible_comparison_p (XEXP (x
, 0)))
3614 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x
, 0))),
3615 mode
, XEXP (XEXP (x
, 0), 0),
3616 XEXP (XEXP (x
, 0), 1));
3619 /* (xor (comparison foo bar) (const_int sign-bit))
3620 when STORE_FLAG_VALUE is the sign bit. */
3621 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_INT
3622 && STORE_FLAG_VALUE
== 1 << (GET_MODE_BITSIZE (mode
) - 1)
3623 && XEXP (x
, 1) == const_true_rtx
3624 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3625 && reversible_comparison_p (XEXP (x
, 0)))
3626 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x
, 0))),
3627 mode
, XEXP (XEXP (x
, 0), 0),
3628 XEXP (XEXP (x
, 0), 1));
3632 /* (abs (neg <foo>)) -> (abs <foo>) */
3633 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3634 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3636 /* If operand is something known to be positive, ignore the ABS. */
3637 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
3638 || (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) <= HOST_BITS_PER_INT
3639 && ((significant_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
3640 & (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
3645 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
3646 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTRACT
3647 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3648 || (GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3649 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3650 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3651 || ((temp
= get_last_value (XEXP (x
, 0))) != 0
3652 && ((GET_CODE (temp
) == SIGN_EXTRACT
3653 && XEXP (temp
, 1) == const1_rtx
)
3654 || (GET_CODE (temp
) == ASHIFTRT
3655 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3656 && (INTVAL (XEXP (temp
, 1))
3657 == GET_MODE_BITSIZE (mode
) - 1)))))
3659 x
= gen_rtx_combine (NEG
, mode
, XEXP (x
, 0));
3665 /* (ffs (*_extend <X>)) = (ffs <X>) */
3666 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3667 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3668 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3672 /* (float (sign_extend <X>)) = (float <X>). */
3673 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
3674 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
3683 /* If this is a shift by a constant amount, simplify it. */
3684 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3686 x
= simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
3687 INTVAL (XEXP (x
, 1)));
3688 if (GET_CODE (x
) != code
)
3692 #ifdef SHIFT_COUNT_TRUNCATED
3693 else if (GET_CODE (XEXP (x
, 1)) != REG
)
3695 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
3696 exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))),
3706 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
3707 operations" because they can be replaced with two more basic operations.
3708 ZERO_EXTEND is also considered "compound" because it can be replaced with
3709 an AND operation, which is simpler, though only one operation.
3711 The function expand_compound_operation is called with an rtx expression
3712 and will convert it to the appropriate shifts and AND operations,
3713 simplifying at each stage.
3715 The function make_compound_operation is called to convert an expression
3716 consisting of shifts and ANDs into the equivalent compound expression.
3717 It is the inverse of this function, loosely speaking. */
3720 expand_compound_operation (x
)
3728 switch (GET_CODE (x
))
3733 /* We can't necessarily use a const_int for a multiword mode;
3734 it depends on implicitly extending the value.
3735 Since we don't know the right way to extend it,
3736 we can't tell whether the implicit way is right.
3738 Even for a mode that is no wider than a const_int,
3739 we can't win, because we need to sign extend one of its bits through
3740 the rest of it, and we don't know which bit. */
3741 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
3744 if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x
, 0)), XEXP (x
, 0)))
3747 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
3748 /* If the inner object has VOIDmode (the only way this can happen
3749 is if it is a ASM_OPERANDS), we can't do anything since we don't
3750 know how much masking to do. */
3759 /* If the operand is a CLOBBER, just return it. */
3760 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
3763 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
3764 || GET_CODE (XEXP (x
, 2)) != CONST_INT
3765 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
3768 len
= INTVAL (XEXP (x
, 1));
3769 pos
= INTVAL (XEXP (x
, 2));
3771 /* If this goes outside the object being extracted, replace the object
3772 with a (use (mem ...)) construct that only combine understands
3773 and is used only for this purpose. */
3774 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
3775 SUBST (XEXP (x
, 0), gen_rtx (USE
, GET_MODE (x
), XEXP (x
, 0)));
3778 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
3786 /* If we reach here, we want to return a pair of shifts. The inner
3787 shift is a left shift of BITSIZE - POS - LEN bits. The outer
3788 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
3789 logical depending on the value of UNSIGNEDP.
3791 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
3792 converted into an AND of a shift.
3794 We must check for the case where the left shift would have a negative
3795 count. This can happen in a case like (x >> 31) & 255 on machines
3796 that can't shift by a constant. On those machines, we would first
3797 combine the shift with the AND to produce a variable-position
3798 extraction. Then the constant of 31 would be substituted in to produce
3799 a such a position. */
3801 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
3802 if (modewidth
>= pos
- len
)
3803 tem
= simplify_shift_const (0, unsignedp
? LSHIFTRT
: ASHIFTRT
,
3805 simplify_shift_const (0, ASHIFT
, GET_MODE (x
),
3807 modewidth
- pos
- len
),
3810 else if (unsignedp
&& len
< HOST_BITS_PER_INT
)
3811 tem
= simplify_and_const_int (0, GET_MODE (x
),
3812 simplify_shift_const (0, LSHIFTRT
,
3817 /* Any other cases we can't handle. */
3821 /* If we couldn't do this for some reason, return the original
3823 if (GET_CODE (tem
) == CLOBBER
)
3829 /* X is a SET which contains an assignment of one object into
3830 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
3831 or certain SUBREGS). If possible, convert it into a series of
3834 We half-heartedly support variable positions, but do not at all
3835 support variable lengths. */
3838 expand_field_assignment (x
)
3842 rtx pos
; /* Always counts from low bit. */
3845 enum machine_mode compute_mode
;
3847 /* Loop until we find something we can't simplify. */
3850 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
3851 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
3853 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
3854 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
3857 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3858 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
3860 inner
= XEXP (SET_DEST (x
), 0);
3861 len
= INTVAL (XEXP (SET_DEST (x
), 1));
3862 pos
= XEXP (SET_DEST (x
), 2);
3864 /* If the position is constant and spans the width of INNER,
3865 surround INNER with a USE to indicate this. */
3866 if (GET_CODE (pos
) == CONST_INT
3867 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
3868 inner
= gen_rtx (USE
, GET_MODE (SET_DEST (x
)), inner
);
3871 if (GET_CODE (pos
) == CONST_INT
)
3872 pos
= gen_rtx (CONST_INT
, VOIDmode
,
3873 (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
3875 else if (GET_CODE (pos
) == MINUS
3876 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
3877 && (INTVAL (XEXP (pos
, 1))
3878 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
3879 /* If position is ADJUST - X, new position is X. */
3880 pos
= XEXP (pos
, 0);
3882 pos
= gen_binary (MINUS
, GET_MODE (pos
),
3883 gen_rtx (CONST_INT
, VOIDmode
,
3884 (GET_MODE_BITSIZE (GET_MODE (inner
))
3889 /* A SUBREG between two modes that occupy the same numbers of words
3890 can be done by moving the SUBREG to the source. */
3891 else if (GET_CODE (SET_DEST (x
)) == SUBREG
3892 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
3893 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
3894 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
3895 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
3897 x
= gen_rtx (SET
, VOIDmode
, SUBREG_REG (SET_DEST (x
)),
3898 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x
))),
3905 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
3906 inner
= SUBREG_REG (inner
);
3908 compute_mode
= GET_MODE (inner
);
3910 /* Compute a mask of LEN bits, if we can do this on the host machine. */
3911 if (len
< HOST_BITS_PER_INT
)
3912 mask
= gen_rtx (CONST_INT
, VOIDmode
, (1 << len
) - 1);
3916 /* Now compute the equivalent expression. Make a copy of INNER
3917 for the SET_DEST in case it is a MEM into which we will substitute;
3918 we don't want shared RTL in that case. */
3919 x
= gen_rtx (SET
, VOIDmode
, copy_rtx (inner
),
3920 gen_binary (IOR
, compute_mode
,
3921 gen_binary (AND
, compute_mode
,
3922 gen_unary (NOT
, compute_mode
,
3927 gen_binary (ASHIFT
, compute_mode
,
3928 gen_binary (AND
, compute_mode
,
3929 gen_lowpart_for_combine
3939 /* Return an RTX for a reference to LEN bits of INNER. POS is the starting
3940 bit position (counted from the LSB) if >= 0; otherwise POS_RTX represents
3941 the starting bit position.
3943 INNER may be a USE. This will occur when we started with a bitfield
3944 that went outside the boundary of the object in memory, which is
3945 allowed on most machines. To isolate this case, we produce a USE
3946 whose mode is wide enough and surround the MEM with it. The only
3947 code that understands the USE is this routine. If it is not removed,
3948 it will cause the resulting insn not to match.
3950 UNSIGNEDP is non-zero for an unsigned reference and zero for a
3953 IN_DEST is non-zero if this is a reference in the destination of a
3954 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
3955 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
3958 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
3959 ZERO_EXTRACT should be built even for bits starting at bit 0.
3961 MODE is the desired mode of the result (if IN_DEST == 0). */
3964 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
3965 unsignedp
, in_dest
, in_compare
)
3966 enum machine_mode mode
;
3972 int in_dest
, in_compare
;
3974 enum machine_mode is_mode
= GET_MODE (inner
);
3975 enum machine_mode inner_mode
;
3976 enum machine_mode wanted_mem_mode
= byte_mode
;
3977 enum machine_mode pos_mode
= word_mode
;
3978 enum machine_mode extraction_mode
= word_mode
;
3979 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
3983 /* Get some information about INNER and get the innermost object. */
3984 if (GET_CODE (inner
) == USE
)
3985 /* We don't need to adjust the position because we set up the USE
3986 to pretend that it was a full-word object. */
3987 spans_byte
= 1, inner
= XEXP (inner
, 0);
3988 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
3989 inner
= SUBREG_REG (inner
);
3991 inner_mode
= GET_MODE (inner
);
3993 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
3994 pos
= INTVAL (pos_rtx
);
3996 /* See if this can be done without an extraction. We never can if the
3997 width of the field is not the same as that of some integer mode. For
3998 registers, we can only avoid the extraction if the position is at the
3999 low-order bit and this is either not in the destination or we have the
4000 appropriate STRICT_LOW_PART operation available.
4002 For MEM, we can avoid an extract if the field starts on an appropriate
4003 boundary and we can change the mode of the memory reference. However,
4004 we cannot directly access the MEM if we have a USE and the underlying
4005 MEM is not TMODE. This combination means that MEM was being used in a
4006 context where bits outside its mode were being referenced; that is only
4007 valid in bit-field insns. */
4009 if (tmode
!= BLKmode
4010 && ! (spans_byte
&& inner_mode
!= tmode
)
4011 && ((pos
== 0 && GET_CODE (inner
) == REG
4013 || (movstrict_optab
->handlers
[(int) tmode
].insn_code
4014 != CODE_FOR_nothing
)))
4015 || (GET_CODE (inner
) == MEM
&& pos
>= 0
4017 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
4018 : BITS_PER_UNIT
)) == 0
4019 /* We can't do this if we are widening INNER_MODE (it
4020 may not be aligned, for one thing). */
4021 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
4022 && (inner_mode
== tmode
4023 || (! mode_dependent_address_p (XEXP (inner
, 0))
4024 && ! MEM_VOLATILE_P (inner
))))))
4026 int offset
= pos
/ BITS_PER_UNIT
;
4028 /* If INNER is a MEM, make a new MEM that encompasses just the desired
4029 field. If the original and current mode are the same, we need not
4030 adjust the offset. Otherwise, we do if bytes big endian.
4032 If INNER is not a MEM, get a piece consisting of the just the field
4033 of interest (in this case INNER must be a REG and POS must be 0). */
4035 if (GET_CODE (inner
) == MEM
)
4037 #if BYTES_BIG_ENDIAN
4038 if (inner_mode
!= tmode
)
4039 offset
= (GET_MODE_SIZE (inner_mode
)
4040 - GET_MODE_SIZE (tmode
) - offset
);
4043 new = gen_rtx (MEM
, tmode
, plus_constant (XEXP (inner
, 0), offset
));
4044 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner
);
4045 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner
);
4046 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner
);
4048 else if (GET_MODE (inner
) == REG
)
4049 /* We can't call gen_lowpart_for_combine here since we always want
4050 a SUBREG and it would sometimes return a new hard register. */
4051 new = gen_rtx (SUBREG
, tmode
, inner
,
4053 && GET_MODE_SIZE (is_mode
) > UNITS_PER_WORD
)
4054 ? ((GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (tmode
)
4058 new = gen_lowpart_for_combine (tmode
, inner
);
4060 /* If this extraction is going into the destination of a SET,
4061 make a STRICT_LOW_PART unless we made a MEM. */
4064 return (GET_CODE (new) == MEM
? new
4065 : (GET_CODE (new) != SUBREG
4066 ? gen_rtx (CLOBBER
, tmode
, const0_rtx
)
4067 : gen_rtx_combine (STRICT_LOW_PART
, VOIDmode
, new)));
4069 /* Otherwise, sign- or zero-extend unless we already are in the
4072 return (mode
== tmode
? new
4073 : gen_rtx_combine (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
4077 /* Unless this is in a COMPARE or we have a funny memory reference,
4078 don't do anything with field extracts starting at the low-order
4079 bit since they are simple AND operations. */
4080 if (pos
== 0 && ! in_dest
&& ! in_compare
&& ! spans_byte
)
4083 /* Get the mode to use should INNER be a MEM, the mode for the position,
4084 and the mode for the result. */
4088 wanted_mem_mode
= insn_operand_mode
[(int) CODE_FOR_insv
][0];
4089 pos_mode
= insn_operand_mode
[(int) CODE_FOR_insv
][2];
4090 extraction_mode
= insn_operand_mode
[(int) CODE_FOR_insv
][3];
4095 if (! in_dest
&& unsignedp
)
4097 wanted_mem_mode
= insn_operand_mode
[(int) CODE_FOR_extzv
][1];
4098 pos_mode
= insn_operand_mode
[(int) CODE_FOR_extzv
][3];
4099 extraction_mode
= insn_operand_mode
[(int) CODE_FOR_extzv
][0];
4104 if (! in_dest
&& ! unsignedp
)
4106 wanted_mem_mode
= insn_operand_mode
[(int) CODE_FOR_extv
][1];
4107 pos_mode
= insn_operand_mode
[(int) CODE_FOR_extv
][3];
4108 extraction_mode
= insn_operand_mode
[(int) CODE_FOR_extv
][0];
4112 /* Never narrow an object, since that might not be safe. */
4114 if (mode
!= VOIDmode
4115 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
4116 extraction_mode
= mode
;
4118 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
4119 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
4120 pos_mode
= GET_MODE (pos_rtx
);
4122 /* If this is not from memory or we have to change the mode of memory and
4123 cannot, the desired mode is EXTRACTION_MODE. */
4124 if (GET_CODE (inner
) != MEM
4125 || (inner_mode
!= wanted_mem_mode
4126 && (mode_dependent_address_p (XEXP (inner
, 0))
4127 || MEM_VOLATILE_P (inner
))))
4128 wanted_mem_mode
= extraction_mode
;
4131 /* If position is constant, compute new position. Otherwise, build
4134 pos
= (MAX (GET_MODE_BITSIZE (is_mode
), GET_MODE_BITSIZE (wanted_mem_mode
))
4138 = gen_rtx_combine (MINUS
, GET_MODE (pos_rtx
),
4139 gen_rtx (CONST_INT
, VOIDmode
,
4140 (MAX (GET_MODE_BITSIZE (is_mode
),
4141 GET_MODE_BITSIZE (wanted_mem_mode
))
4145 /* If INNER has a wider mode, make it smaller. If this is a constant
4146 extract, try to adjust the byte to point to the byte containing
4148 if (wanted_mem_mode
!= VOIDmode
4149 && GET_MODE_SIZE (wanted_mem_mode
) < GET_MODE_SIZE (is_mode
)
4150 && ((GET_CODE (inner
) == MEM
4151 && (inner_mode
== wanted_mem_mode
4152 || (! mode_dependent_address_p (XEXP (inner
, 0))
4153 && ! MEM_VOLATILE_P (inner
))))))
4157 /* The computations below will be correct if the machine is big
4158 endian in both bits and bytes or little endian in bits and bytes.
4159 If it is mixed, we must adjust. */
4161 #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
4162 if (! spans_byte
&& is_mode
!= wanted_mem_mode
)
4163 offset
= (GET_MODE_SIZE (is_mode
)
4164 - GET_MODE_SIZE (wanted_mem_mode
) - offset
);
4167 /* If bytes are big endian and we had a paradoxical SUBREG, we must
4168 adjust OFFSET to compensate. */
4169 #if BYTES_BIG_ENDIAN
4171 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
4172 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
4175 /* If this is a constant position, we can move to the desired byte. */
4178 offset
+= pos
/ BITS_PER_UNIT
;
4179 pos
%= GET_MODE_BITSIZE (wanted_mem_mode
);
4182 if (offset
!= 0 || inner_mode
!= wanted_mem_mode
)
4184 rtx newmem
= gen_rtx (MEM
, wanted_mem_mode
,
4185 plus_constant (XEXP (inner
, 0), offset
));
4186 RTX_UNCHANGING_P (newmem
) = RTX_UNCHANGING_P (inner
);
4187 MEM_VOLATILE_P (newmem
) = MEM_VOLATILE_P (inner
);
4188 MEM_IN_STRUCT_P (newmem
) = MEM_IN_STRUCT_P (inner
);
4193 /* If INNER is not memory, we can always get it into the proper mode. */
4194 else if (GET_CODE (inner
) != MEM
)
4195 inner
= gen_lowpart_for_combine (extraction_mode
, inner
);
4197 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
4198 have to zero extend. Otherwise, we can just use a SUBREG. */
4200 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
4201 pos_rtx
= gen_rtx_combine (ZERO_EXTEND
, pos_mode
, pos_rtx
);
4203 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
4204 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
4206 /* Make POS_RTX unless we already have it and it is correct. */
4207 if (pos_rtx
== 0 || (pos
>= 0 && INTVAL (pos_rtx
) != pos
))
4208 pos_rtx
= gen_rtx (CONST_INT
, VOIDmode
, pos
);
4210 /* Make the required operation. See if we can use existing rtx. */
4211 new = gen_rtx_combine (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
4212 extraction_mode
, inner
,
4213 gen_rtx (CONST_INT
, VOIDmode
, len
), pos_rtx
);
4215 new = gen_lowpart_for_combine (mode
, new);
4220 /* Look at the expression rooted at X. Look for expressions
4221 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
4222 Form these expressions.
4224 Return the new rtx, usually just X.
4226 Also, for machines like the Vax that don't have logical shift insns,
4227 try to convert logical to arithmetic shift operations in cases where
4228 they are equivalent. This undoes the canonicalizations to logical
4229 shifts done elsewhere.
4231 We try, as much as possible, to re-use rtl expressions to save memory.
4233 IN_CODE says what kind of expression we are processing. Normally, it is
4234 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
4235 being kludges), it is MEM. When processing the arguments of a comparison
4236 or a COMPARE against zero, it is COMPARE. */
4239 make_compound_operation (x
, in_code
)
4241 enum rtx_code in_code
;
4243 enum rtx_code code
= GET_CODE (x
);
4244 enum machine_mode mode
= GET_MODE (x
);
4245 int mode_width
= GET_MODE_BITSIZE (mode
);
4246 enum rtx_code next_code
;
4251 /* Select the code to be used in recursive calls. Once we are inside an
4252 address, we stay there. If we have a comparison, set to COMPARE,
4253 but once inside, go back to our default of SET. */
4255 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
4256 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
4257 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
4258 : in_code
== COMPARE
? SET
: in_code
);
4260 /* Process depending on the code of this operation. If NEW is set
4261 non-zero, it will be returned. */
4267 /* Convert shifts by constants into multiplications if inside
4269 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
4270 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_INT
4271 && INTVAL (XEXP (x
, 1)) >= 0)
4272 new = gen_rtx_combine (MULT
, mode
, XEXP (x
, 0),
4273 gen_rtx (CONST_INT
, VOIDmode
,
4274 1 << INTVAL (XEXP (x
, 1))));
4278 /* If the second operand is not a constant, we can't do anything
4280 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4283 /* If the constant is a power of two minus one and the first operand
4284 is a logical right shift, make an extraction. */
4285 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4286 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
4287 new = make_extraction (mode
, XEXP (XEXP (x
, 0), 0), -1,
4288 XEXP (XEXP (x
, 0), 1), i
, 1,
4289 0, in_code
== COMPARE
);
4291 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
4292 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
4293 && subreg_lowpart_p (XEXP (x
, 0))
4294 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
4295 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
4296 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))),
4297 XEXP (SUBREG_REG (XEXP (x
, 0)), 0), -1,
4298 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
4299 0, in_code
== COMPARE
);
4302 /* If we are have (and (rotate X C) M) and C is larger than the number
4303 of bits in M, this is an extraction. */
4305 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
4306 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4307 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
4308 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
4309 new = make_extraction (mode
, XEXP (XEXP (x
, 0), 0),
4310 (GET_MODE_BITSIZE (mode
)
4311 - INTVAL (XEXP (XEXP (x
, 0), 1))),
4312 0, i
, 1, 0, in_code
== COMPARE
);
4314 /* On machines without logical shifts, if the operand of the AND is
4315 a logical shift and our mask turns off all the propagated sign
4316 bits, we can replace the logical shift with an arithmetic shift. */
4328 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4329 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4330 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
4331 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_INT
4332 && mode_width
<= HOST_BITS_PER_INT
)
4334 unsigned mask
= GET_MODE_MASK (mode
);
4336 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
4337 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
4339 gen_rtx_combine (ASHIFTRT
, mode
, XEXP (XEXP (x
, 0), 0),
4340 XEXP (XEXP (x
, 0), 1)));
4343 /* If the constant is one less than a power of two, this might be
4344 representable by an extraction even if no shift is present.
4345 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
4346 we are in a COMPARE. */
4347 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
4348 new = make_extraction (mode
, XEXP (x
, 0), 0, 0, i
, 1,
4349 0, in_code
== COMPARE
);
4351 /* If we are in a comparison and this is an AND with a power of two,
4352 convert this into the appropriate bit extract. */
4353 else if (in_code
== COMPARE
4354 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4355 new = make_extraction (mode
, XEXP (x
, 0), i
, 0, 1, 1, 0, 1);
4360 /* If the sign bit is known to be zero, replace this with an
4361 arithmetic shift. */
4373 && mode_width
<= HOST_BITS_PER_INT
4374 && (significant_bits (XEXP (x
, 0), mode
)
4375 & (1 << (mode_width
- 1))) == 0)
4377 new = gen_rtx_combine (ASHIFTRT
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4381 /* ... fall through ... */
4384 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
4385 this is a SIGN_EXTRACT. */
4386 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4387 && GET_CODE (XEXP (x
, 0)) == ASHIFT
4388 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4389 && INTVAL (XEXP (x
, 1)) >= INTVAL (XEXP (XEXP (x
, 0), 1)))
4390 new = make_extraction (mode
, XEXP (XEXP (x
, 0), 0),
4391 (INTVAL (XEXP (x
, 1))
4392 - INTVAL (XEXP (XEXP (x
, 0), 1))),
4393 0, mode_width
- INTVAL (XEXP (x
, 1)),
4394 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
4401 code
= GET_CODE (x
);
4404 /* Now recursively process each operand of this operation. */
4405 fmt
= GET_RTX_FORMAT (code
);
4406 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
4409 new = make_compound_operation (XEXP (x
, i
), next_code
);
4410 SUBST (XEXP (x
, i
), new);
4416 /* Given M see if it is a value that would select a field of bits
4417 within an item, but not the entire word. Return -1 if not.
4418 Otherwise, return the starting position of the field, where 0 is the
4421 *PLEN is set to the length of the field. */
4424 get_pos_from_mask (m
, plen
)
4428 /* Get the bit number of the first 1 bit from the right, -1 if none. */
4429 int pos
= exact_log2 (m
& - m
);
4434 /* Now shift off the low-order zero bits and see if we have a power of
4436 *plen
= exact_log2 ((m
>> pos
) + 1);
4444 /* Rewrite X so that it is an expression in MODE. We only care about the
4445 low-order BITS bits so we can ignore AND operations that just clear
4448 Also, if REG is non-zero and X is a register equal in value to REG,
4449 replace X with REG. */
4452 force_to_mode (x
, mode
, bits
, reg
)
4454 enum machine_mode mode
;
4458 enum rtx_code code
= GET_CODE (x
);
4460 /* If X is narrower than MODE or if BITS is larger than the size of MODE,
4461 just get X in the proper mode. */
4463 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
4464 || bits
> GET_MODE_BITSIZE (mode
))
4465 return gen_lowpart_for_combine (mode
, x
);
4473 x
= expand_compound_operation (x
);
4474 if (GET_CODE (x
) != code
)
4475 return force_to_mode (x
, mode
, bits
, reg
);
4479 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
4480 || rtx_equal_p (reg
, get_last_value (x
))))
4485 if (bits
< HOST_BITS_PER_INT
)
4486 x
= gen_rtx (CONST_INT
, VOIDmode
, INTVAL (x
) & ((1 << bits
) - 1));
4490 /* Ignore low-order SUBREGs. */
4491 if (subreg_lowpart_p (x
))
4492 return force_to_mode (SUBREG_REG (x
), mode
, bits
, reg
);
4496 /* If this is an AND with a constant. Otherwise, we fall through to
4497 do the general binary case. */
4499 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4501 int mask
= INTVAL (XEXP (x
, 1));
4502 int len
= exact_log2 (mask
+ 1);
4503 rtx op
= XEXP (x
, 0);
4505 /* If this is masking some low-order bits, we may be able to
4506 impose a stricter constraint on what bits of the operand are
4509 op
= force_to_mode (op
, mode
, len
> 0 ? MIN (len
, bits
) : bits
,
4512 if (bits
< HOST_BITS_PER_INT
)
4513 mask
&= (1 << bits
) - 1;
4515 x
= simplify_and_const_int (x
, mode
, op
, mask
);
4517 /* If X is still an AND, see if it is an AND with a mask that
4518 is just some low-order bits. If so, and it is BITS wide (it
4519 can't be wider), we don't need it. */
4521 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
4522 && bits
< HOST_BITS_PER_INT
4523 && INTVAL (XEXP (x
, 1)) == (1 << bits
) - 1)
4528 /* ... fall through ... */
4535 /* For most binary operations, just propagate into the operation and
4538 return gen_binary (code
, mode
,
4539 force_to_mode (XEXP (x
, 0), mode
, bits
, reg
),
4540 force_to_mode (XEXP (x
, 1), mode
, bits
, reg
));
4544 /* For left shifts, do the same, but just for the first operand.
4545 If the shift count is a constant, we need even fewer bits of the
4548 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) < bits
)
4549 bits
-= INTVAL (XEXP (x
, 1));
4551 return gen_binary (code
, mode
,
4552 force_to_mode (XEXP (x
, 0), mode
, bits
, reg
),
4556 /* Here we can only do something if the shift count is a constant and
4557 the count plus BITS is no larger than the width of MODE, we can do
4558 the shift in MODE. */
4560 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4561 && INTVAL (XEXP (x
, 1)) + bits
<= GET_MODE_BITSIZE (mode
))
4562 return gen_binary (LSHIFTRT
, mode
,
4563 force_to_mode (XEXP (x
, 0), mode
,
4564 bits
+ INTVAL (XEXP (x
, 1)), reg
),
4570 /* Handle these similarly to the way we handle most binary operations. */
4571 return gen_unary (code
, mode
,
4572 force_to_mode (XEXP (x
, 0), mode
, bits
, reg
));
4575 /* Otherwise, just do the operation canonically. */
4576 return gen_lowpart_for_combine (mode
, x
);
4579 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
4580 Return that assignment if so.
4582 We only handle the most common cases. */
4585 make_field_assignment (x
)
4588 rtx dest
= SET_DEST (x
);
4589 rtx src
= SET_SRC (x
);
4594 enum machine_mode mode
;
4596 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
4597 a clear of a one-bit field. We will have changed it to
4598 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
4601 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
4602 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
4603 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
4604 && (rtx_equal_p (dest
, XEXP (src
, 1))
4605 || rtx_equal_p (dest
, get_last_value (XEXP (src
, 1)))
4606 || rtx_equal_p (get_last_value (dest
), XEXP (src
, 1))))
4608 assign
= make_extraction (VOIDmode
, dest
, -1, XEXP (XEXP (src
, 0), 1),
4610 return gen_rtx (SET
, VOIDmode
, assign
, const0_rtx
);
4613 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
4614 && subreg_lowpart_p (XEXP (src
, 0))
4615 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
4616 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
4617 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
4618 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
4619 && (rtx_equal_p (dest
, XEXP (src
, 1))
4620 || rtx_equal_p (dest
, get_last_value (XEXP (src
, 1)))
4621 || rtx_equal_p (get_last_value (dest
), XEXP (src
, 1))))
4623 assign
= make_extraction (VOIDmode
, dest
, -1,
4624 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
4626 return gen_rtx (SET
, VOIDmode
, assign
, const0_rtx
);
4629 /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
4631 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
4632 && XEXP (XEXP (src
, 0), 0) == const1_rtx
4633 && (rtx_equal_p (dest
, XEXP (src
, 1))
4634 || rtx_equal_p (dest
, get_last_value (XEXP (src
, 1)))
4635 || rtx_equal_p (get_last_value (dest
), XEXP (src
, 1))))
4637 assign
= make_extraction (VOIDmode
, dest
, -1, XEXP (XEXP (src
, 0), 1),
4639 return gen_rtx (SET
, VOIDmode
, assign
, const1_rtx
);
4642 /* The other case we handle is assignments into a constant-position
4643 field. They look like (ior (and DEST C1) OTHER). If C1 represents
4644 a mask that has all one bits except for a group of zero bits and
4645 OTHER is known to have zeros where C1 has ones, this is such an
4646 assignment. Compute the position and length from C1. Shift OTHER
4647 to the appropriate position, force it to the required mode, and
4648 make the extraction. Check for the AND in both operands. */
4650 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == AND
4651 && GET_CODE (XEXP (XEXP (src
, 0), 1)) == CONST_INT
4652 && (rtx_equal_p (XEXP (XEXP (src
, 0), 0), dest
)
4653 || rtx_equal_p (XEXP (XEXP (src
, 0), 0), get_last_value (dest
))
4654 || rtx_equal_p (get_last_value (XEXP (XEXP (src
, 0), 1)), dest
)))
4655 c1
= INTVAL (XEXP (XEXP (src
, 0), 1)), other
= XEXP (src
, 1);
4656 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 1)) == AND
4657 && GET_CODE (XEXP (XEXP (src
, 1), 1)) == CONST_INT
4658 && (rtx_equal_p (XEXP (XEXP (src
, 1), 0), dest
)
4659 || rtx_equal_p (XEXP (XEXP (src
, 1), 0), get_last_value (dest
))
4660 || rtx_equal_p (get_last_value (XEXP (XEXP (src
, 1), 0)),
4662 c1
= INTVAL (XEXP (XEXP (src
, 1), 1)), other
= XEXP (src
, 0);
4666 pos
= get_pos_from_mask (~c1
, &len
);
4667 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
4668 || (c1
& significant_bits (other
, GET_MODE (other
))) != 0)
4671 assign
= make_extraction (VOIDmode
, dest
, pos
, 0, len
, 1, 1, 0);
4673 /* The mode to use for the source is the mode of the assignment, or of
4674 what is inside a possible STRICT_LOW_PART. */
4675 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
4676 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
4678 /* Shift OTHER right POS places and make it the source, restricting it
4679 to the proper length and mode. */
4681 src
= force_to_mode (simplify_shift_const (0, LSHIFTRT
, GET_MODE (src
),
4685 return gen_rtx_combine (SET
, VOIDmode
, assign
, src
);
4688 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
4692 apply_distributive_law (x
)
4695 enum rtx_code code
= GET_CODE (x
);
4696 rtx lhs
, rhs
, other
;
4698 enum rtx_code inner_code
;
4700 /* The outer operation can only be one of the following: */
4701 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
4702 && code
!= PLUS
&& code
!= MINUS
)
4705 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
4707 /* If either operand is a primitive we can't do anything, so get out fast. */
4708 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
4709 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
4712 lhs
= expand_compound_operation (lhs
);
4713 rhs
= expand_compound_operation (rhs
);
4714 inner_code
= GET_CODE (lhs
);
4715 if (inner_code
!= GET_CODE (rhs
))
4718 /* See if the inner and outer operations distribute. */
4725 /* These all distribute except over PLUS. */
4726 if (code
== PLUS
|| code
== MINUS
)
4731 if (code
!= PLUS
&& code
!= MINUS
)
4737 /* These are also multiplies, so they distribute over everything. */
4741 /* Non-paradoxical SUBREGs distributes over all operations, provided
4742 the inner modes and word numbers are the same, this is an extraction
4743 of a low-order part, we don't convert an fp operation to int or
4744 vice versa, and we would not be converting a single-word
4745 operation into a multi-word operation. The latter test is not
4746 required, but it prevents generating unneeded multi-word operations.
4747 Some of the previous tests are redundant given the latter test, but
4748 are retained because they are required for correctness.
4750 We produce the result slightly differently in this case. */
4752 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
4753 || SUBREG_WORD (lhs
) != SUBREG_WORD (rhs
)
4754 || ! subreg_lowpart_p (lhs
)
4755 || (GET_MODE_CLASS (GET_MODE (lhs
))
4756 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
4757 || (GET_MODE_SIZE (GET_MODE (lhs
))
4758 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
4759 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
4762 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
4763 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
4764 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
4770 /* Set LHS and RHS to the inner operands (A and B in the example
4771 above) and set OTHER to the common operand (C in the example).
4772 These is only one way to do this unless the inner operation is
4774 if (GET_RTX_CLASS (inner_code
) == 'c'
4775 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
4776 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
4777 else if (GET_RTX_CLASS (inner_code
) == 'c'
4778 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
4779 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
4780 else if (GET_RTX_CLASS (inner_code
) == 'c'
4781 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
4782 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
4783 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
4784 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
4788 /* Form the new inner operation, seeing if it simplifies first. */
4789 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
4791 /* There is one exception to the general way of distributing:
4792 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
4793 if (code
== XOR
&& inner_code
== IOR
)
4796 other
= gen_unary (NOT
, GET_MODE (x
), other
);
4799 /* We may be able to continuing distributing the result, so call
4800 ourselves recursively on the inner operation before forming the
4801 outer operation, which we return. */
4802 return gen_binary (inner_code
, GET_MODE (x
),
4803 apply_distributive_law (tem
), other
);
4806 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
4809 Return an equivalent form, if different from X. Otherwise, return X. If
4810 X is zero, we are to always construct the equivalent form. */
4813 simplify_and_const_int (x
, mode
, varop
, constop
)
4815 enum machine_mode mode
;
4819 register enum machine_mode tmode
;
4821 unsigned significant
;
4823 /* There is a large class of optimizations based on the principle that
4824 some operations produce results where certain bits are known to be zero,
4825 and hence are not significant to the AND. For example, if we have just
4826 done a left shift of one bit, the low-order bit is known to be zero and
4827 hence an AND with a mask of ~1 would not do anything.
4829 At the end of the following loop, we set:
4831 VAROP to be the item to be AND'ed with;
4832 CONSTOP to the constant value to AND it with. */
4836 /* If we ever encounter a mode wider than the host machine's word
4837 size, we can't compute the masks accurately, so give up. */
4838 if (GET_MODE_BITSIZE (GET_MODE (varop
)) > HOST_BITS_PER_INT
)
4841 /* Unless one of the cases below does a `continue',
4842 a `break' will be executed to exit the loop. */
4844 switch (GET_CODE (varop
))
4847 /* If VAROP is a (clobber (const_int)), return it since we know
4848 we are generating something that won't match. */
4851 #if ! BITS_BIG_ENDIAN
4853 /* VAROP is a (use (mem ..)) that was made from a bit-field
4854 extraction that spanned the boundary of the MEM. If we are
4855 now masking so it is within that boundary, we don't need the
4857 if ((constop
& ~ GET_MODE_MASK (GET_MODE (XEXP (varop
, 0)))) == 0)
4859 varop
= XEXP (varop
, 0);
4866 if (subreg_lowpart_p (varop
)
4867 /* We can ignore the effect this SUBREG if it narrows the mode
4868 or, on machines where byte operations zero extend, if the
4869 constant masks to zero all the bits the mode doesn't have. */
4870 && ((GET_MODE_SIZE (GET_MODE (varop
))
4871 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
))))
4872 #ifdef BYTE_LOADS_ZERO_EXTEND
4874 & GET_MODE_MASK (GET_MODE (varop
))
4875 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (varop
)))))
4879 varop
= SUBREG_REG (varop
);
4888 /* Try to expand these into a series of shifts and then work
4889 with that result. If we can't, for example, if the extract
4890 isn't at a fixed position, give up. */
4891 temp
= expand_compound_operation (varop
);
4900 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
)
4902 constop
&= INTVAL (XEXP (varop
, 1));
4903 varop
= XEXP (varop
, 0);
4910 /* If VAROP is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
4911 LSHIFT so we end up with an (and (lshiftrt (ior ...) ...) ...)
4912 operation which may be a bitfield extraction. */
4914 if (GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
4915 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
4916 && INTVAL (XEXP (XEXP (varop
, 0), 1)) >= 0
4917 && INTVAL (XEXP (XEXP (varop
, 0), 1)) < HOST_BITS_PER_INT
4918 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
4919 && (INTVAL (XEXP (varop
, 1))
4920 & ~ significant_bits (XEXP (varop
, 0),
4921 GET_MODE (varop
)) == 0))
4923 temp
= gen_rtx (CONST_INT
, VOIDmode
,
4924 ((INTVAL (XEXP (varop
, 1)) & constop
)
4925 << INTVAL (XEXP (XEXP (varop
, 0), 1))));
4926 temp
= gen_binary (GET_CODE (varop
), GET_MODE (varop
),
4927 XEXP (XEXP (varop
, 0), 0), temp
);
4928 varop
= gen_rtx_combine (LSHIFTRT
, GET_MODE (varop
),
4929 temp
, XEXP (varop
, 1));
4933 /* Apply the AND to both branches of the IOR or XOR, then try to
4934 apply the distributive law. This may eliminate operations
4935 if either branch can be simplified because of the AND.
4936 It may also make some cases more complex, but those cases
4937 probably won't match a pattern either with or without this. */
4939 gen_lowpart_for_combine
4940 (mode
, apply_distributive_law
4942 (GET_CODE (varop
), GET_MODE (varop
),
4943 simplify_and_const_int (0, GET_MODE (varop
),
4944 XEXP (varop
, 0), constop
),
4945 simplify_and_const_int (0, GET_MODE (varop
),
4946 XEXP (varop
, 1), constop
))));
4949 /* (and (not FOO)) is (and (xor FOO CONST_OP)) so if FOO is an
4950 LSHIFTRT we can do the same as above. */
4952 if (GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
4953 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
4954 && INTVAL (XEXP (XEXP (varop
, 0), 1)) >= 0
4955 && INTVAL (XEXP (XEXP (varop
, 0), 1)) < HOST_BITS_PER_INT
)
4957 temp
= gen_rtx (CONST_INT
, VOIDmode
,
4958 constop
<< INTVAL (XEXP (XEXP (varop
, 0), 1)));
4959 temp
= gen_binary (XOR
, GET_MODE (varop
),
4960 XEXP (XEXP (varop
, 0), 0), temp
);
4961 varop
= gen_rtx_combine (LSHIFTRT
, GET_MODE (varop
),
4962 temp
, XEXP (XEXP (varop
, 0), 1));
4968 /* If we are just looking for the sign bit, we don't need this
4969 shift at all, even if it has a variable count. */
4970 if (constop
== 1 << (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1))
4972 varop
= XEXP (varop
, 0);
4976 /* If this is a shift by a constant, get a mask that contains
4977 those bits that are not copies of the sign bit. We then have
4978 two cases: If CONSTOP only includes those bits, this can be
4979 a logical shift, which may allow simplifications. If CONSTOP
4980 is a single-bit field not within those bits, we are requesting
4981 a copy of the sign bit and hence can shift the sign bit to
4982 the appropriate location. */
4983 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
4984 && INTVAL (XEXP (varop
, 1)) >= 0
4985 && INTVAL (XEXP (varop
, 1)) < HOST_BITS_PER_INT
)
4989 significant
= GET_MODE_MASK (GET_MODE (varop
));
4990 significant
>>= INTVAL (XEXP (varop
, 1));
4992 if ((constop
& ~significant
) == 0
4993 || (i
= exact_log2 (constop
)) >= 0)
4995 varop
= simplify_shift_const
4996 (varop
, LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
4997 i
< 0 ? INTVAL (XEXP (varop
, 1))
4998 : GET_MODE_BITSIZE (GET_MODE (varop
)) - 1 - i
);
4999 if (GET_CODE (varop
) != ASHIFTRT
)
5004 /* If our mask is 1, convert this to a LSHIFTRT. This can be done
5005 even if the shift count isn't a constant. */
5007 varop
= gen_rtx_combine (LSHIFTRT
, GET_MODE (varop
),
5008 XEXP (varop
, 0), XEXP (varop
, 1));
5012 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is
5013 included in STORE_FLAG_VALUE and FOO has no significant bits
5015 if ((constop
& ~ STORE_FLAG_VALUE
) == 0
5016 && XEXP (varop
, 0) == const0_rtx
5017 && (significant_bits (XEXP (varop
, 0), mode
) & ~ constop
) == 0)
5019 varop
= XEXP (varop
, 0);
5025 /* In (and (plus FOO C1) M), if M is a mask that just turns off
5026 low-order bits (as in an alignment operation) and FOO is already
5027 aligned to that boundary, we can convert remove this AND
5028 and possibly the PLUS if it is now adding zero. */
5029 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
5030 && exact_log2 (-constop
) >= 0
5031 && (significant_bits (XEXP (varop
, 0), mode
) & ~ constop
) == 0)
5033 varop
= plus_constant (XEXP (varop
, 0),
5034 INTVAL (XEXP (varop
, 1)) & constop
);
5039 /* ... fall through ... */
5042 /* In (and (plus (and FOO M1) BAR) M2), if M1 and M2 are one
5043 less than powers of two and M2 is narrower than M1, we can
5044 eliminate the inner AND. This occurs when incrementing
5047 if (GET_CODE (XEXP (varop
, 0)) == ZERO_EXTRACT
5048 || GET_CODE (XEXP (varop
, 0)) == ZERO_EXTEND
)
5049 SUBST (XEXP (varop
, 0),
5050 expand_compound_operation (XEXP (varop
, 0)));
5052 if (GET_CODE (XEXP (varop
, 0)) == AND
5053 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
5054 && exact_log2 (constop
+ 1) >= 0
5055 && exact_log2 (INTVAL (XEXP (XEXP (varop
, 0), 1)) + 1) >= 0
5056 && (~ INTVAL (XEXP (XEXP (varop
, 0), 1)) & constop
) == 0)
5057 SUBST (XEXP (varop
, 0), XEXP (XEXP (varop
, 0), 0));
5064 /* If we have reached a constant, this whole thing is constant. */
5065 if (GET_CODE (varop
) == CONST_INT
)
5066 return gen_rtx (CONST_INT
, VOIDmode
, constop
& INTVAL (varop
));
5068 /* See what bits are significant in VAROP. */
5069 significant
= significant_bits (varop
, mode
);
5071 /* Turn off all bits in the constant that are known to already be zero.
5072 Thus, if the AND isn't needed at all, we will have CONSTOP == SIGNIFICANT
5073 which is tested below. */
5075 constop
&= significant
;
5077 /* If we don't have any bits left, return zero. */
5081 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
5082 if we already had one (just check for the simplest cases). */
5083 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
5084 && GET_MODE (XEXP (x
, 0)) == mode
5085 && SUBREG_REG (XEXP (x
, 0)) == varop
)
5086 varop
= XEXP (x
, 0);
5088 varop
= gen_lowpart_for_combine (mode
, varop
);
5090 /* If we can't make the SUBREG, try to return what we were given. */
5091 if (GET_CODE (varop
) == CLOBBER
)
5092 return x
? x
: varop
;
5094 /* If we are only masking insignificant bits, return VAROP. */
5095 if (constop
== significant
)
5098 /* Otherwise, return an AND. See how much, if any, of X we can use. */
5099 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
5100 x
= gen_rtx_combine (AND
, mode
, varop
,
5101 gen_rtx (CONST_INT
, VOIDmode
, constop
));
5105 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5106 || INTVAL (XEXP (x
, 1)) != constop
)
5107 SUBST (XEXP (x
, 1), gen_rtx (CONST_INT
, VOIDmode
, constop
));
5109 SUBST (XEXP (x
, 0), varop
);
5115 /* Given an expression, X, compute which bits in X can be non-zero.
5116 We don't care about bits outside of those defined in MODE.
5118 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
5119 a shift, AND, or zero_extract, we can do better. */
5122 significant_bits (x
, mode
)
5124 enum machine_mode mode
;
5126 unsigned significant
= GET_MODE_MASK (mode
);
5129 int mode_width
= GET_MODE_BITSIZE (mode
);
5132 /* If X is wider than MODE, use its mode instead. */
5133 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
5135 mode
= GET_MODE (x
);
5136 significant
= GET_MODE_MASK (mode
);
5137 mode_width
= GET_MODE_BITSIZE (mode
);
5140 if (mode_width
> HOST_BITS_PER_INT
)
5141 /* Our only callers in this case look for single bit values. So
5142 just return the mode mask. Those tests will then be false. */
5145 code
= GET_CODE (x
);
5149 #ifdef STACK_BOUNDARY
5150 /* If this is the stack pointer, we may know something about its
5151 alignment. If PUSH_ROUNDING is defined, it is possible for the
5152 stack to be momentarily aligned only to that amount, so we pick
5153 the least alignment. */
5155 if (x
== stack_pointer_rtx
)
5157 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
5159 #ifdef PUSH_ROUNDING
5160 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
5163 return significant
& ~ (sp_alignment
- 1);
5167 /* If X is a register whose value we can find, use that value.
5168 Otherwise, use the previously-computed significant bits for this
5171 tem
= get_last_value (x
);
5173 return significant_bits (tem
, mode
);
5174 else if (significant_valid
&& reg_significant
[REGNO (x
)])
5175 return reg_significant
[REGNO (x
)] & significant
;
5182 #ifdef BYTE_LOADS_ZERO_EXTEND
5184 /* In many, if not most, RISC machines, reading a byte from memory
5185 zeros the rest of the register. Noticing that fact saves a lot
5186 of extra zero-extends. */
5187 significant
&= GET_MODE_MASK (GET_MODE (x
));
5191 #if STORE_FLAG_VALUE == 1
5198 if (GET_MODE_CLASS (mode
) == MODE_INT
)
5201 /* A comparison operation only sets the bits given by its mode. The
5202 rest are set undefined. */
5203 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
5204 significant
|= (GET_MODE_MASK (mode
) & ~ GET_MODE_MASK (GET_MODE (x
)));
5208 #if STORE_FLAG_VALUE == -1
5210 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
5211 || ((tem
= get_last_value (XEXP (x
, 0))) != 0
5212 && GET_RTX_CLASS (GET_CODE (tem
)) == '<'))
5215 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
5216 significant
|= (GET_MODE_MASK (mode
) & ~ GET_MODE_MASK (GET_MODE (x
)));
5221 significant
&= (significant_bits (XEXP (x
, 0), mode
)
5222 & GET_MODE_MASK (mode
));
5226 significant
&= significant_bits (XEXP (x
, 0), mode
);
5227 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
5228 significant
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
5232 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
5233 Otherwise, show all the bits in the outer mode but not the inner
5235 inner_sig
= significant_bits (XEXP (x
, 0), mode
);
5236 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
5238 inner_sig
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
5240 (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
5241 inner_sig
|= (GET_MODE_MASK (mode
)
5242 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
5245 significant
&= inner_sig
;
5249 significant
&= (significant_bits (XEXP (x
, 0), mode
)
5250 & significant_bits (XEXP (x
, 1), mode
));
5255 significant
&= (significant_bits (XEXP (x
, 0), mode
)
5256 | significant_bits (XEXP (x
, 1), mode
));
5259 case PLUS
: case MINUS
:
5261 case DIV
: case UDIV
:
5262 case MOD
: case UMOD
:
5263 /* We can apply the rules of arithmetic to compute the number of
5264 high- and low-order zero bits of these operations. We start by
5265 computing the width (position of the highest-order non-zero bit)
5266 and the number of low-order zero bits for each value. */
5268 unsigned sig0
= significant_bits (XEXP (x
, 0), mode
);
5269 unsigned sig1
= significant_bits (XEXP (x
, 1), mode
);
5270 int width0
= floor_log2 (sig0
) + 1;
5271 int width1
= floor_log2 (sig1
) + 1;
5272 int low0
= floor_log2 (sig0
& -sig0
);
5273 int low1
= floor_log2 (sig1
& -sig1
);
5274 int op0_maybe_minusp
= (sig0
& (1 << (mode_width
- 1)));
5275 int op1_maybe_minusp
= (sig1
& (1 << (mode_width
- 1)));
5276 int result_width
= mode_width
;
5282 result_width
= MAX (width0
, width1
) + 1;
5283 result_low
= MIN (low0
, low1
);
5286 result_low
= MIN (low0
, low1
);
5289 result_width
= width0
+ width1
;
5290 result_low
= low0
+ low1
;
5293 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
5294 result_width
= width0
;
5297 result_width
= width0
;
5300 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
5301 result_width
= MIN (width0
, width1
);
5302 result_low
= MIN (low0
, low1
);
5305 result_width
= MIN (width0
, width1
);
5306 result_low
= MIN (low0
, low1
);
5310 if (result_width
< mode_width
)
5311 significant
&= (1 << result_width
) - 1;
5314 significant
&= ~ ((1 << result_low
) - 1);
5319 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
5320 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_INT
)
5321 significant
&= (1 << INTVAL (XEXP (x
, 1))) - 1;
5325 /* If the inner mode is a single word for both the host and target
5326 machines, we can compute this from which bits of the inner
5327 object are known significant. */
5328 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
5329 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= HOST_BITS_PER_INT
)
5331 significant
&= significant_bits (SUBREG_REG (x
), mode
);
5332 #ifndef BYTE_LOADS_ZERO_EXTEND
5333 /* On many CISC machines, accessing an object in a wider mode
5334 causes the high-order bits to become undefined. So they are
5335 not known to be zero. */
5336 if (GET_MODE_SIZE (GET_MODE (x
))
5337 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
5338 significant
|= (GET_MODE_MASK (GET_MODE (x
))
5339 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
5349 /* The significant bits are in two classes: any bits within MODE
5350 that aren't in GET_MODE (x) are always significant. The rest of the
5351 significant bits are those that are significant in the operand of
5352 the shift when shifted the appropriate number of bits. This
5353 shows that high-order bits are cleared by the right shift and
5354 low-order bits by left shifts. */
5355 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
5356 && INTVAL (XEXP (x
, 1)) >= 0
5357 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_INT
)
5359 enum machine_mode inner_mode
= GET_MODE (x
);
5360 int width
= GET_MODE_BITSIZE (inner_mode
);
5361 int count
= INTVAL (XEXP (x
, 1));
5362 unsigned mode_mask
= GET_MODE_MASK (inner_mode
);
5363 unsigned op_significant
= significant_bits (XEXP (x
, 0), mode
);
5364 unsigned inner
= op_significant
& mode_mask
;
5367 if (mode_width
> width
)
5368 outer
= (op_significant
& significant
& ~ mode_mask
);
5370 if (code
== LSHIFTRT
)
5372 else if (code
== ASHIFTRT
)
5376 /* If the sign bit was significant at before the shift, we
5377 need to mark all the places it could have been copied to
5378 by the shift significant. */
5379 if (inner
& (1 << (width
- 1 - count
)))
5380 inner
|= ((1 << count
) - 1) << (width
- count
);
5382 else if (code
== LSHIFT
|| code
== ASHIFT
)
5385 inner
= ((inner
<< (count
% width
)
5386 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
5388 significant
&= (outer
| inner
);
5393 /* This is at most the number of bits in the mode. */
5394 significant
= (1 << (floor_log2 (mode_width
) + 1)) - 1;
5401 /* This function is called from `simplify_shift_const' to merge two
5402 outer operations. Specifically, we have already found that we need
5403 to perform operation *POP0 with constant *PCONST0 at the outermost
5404 position. We would now like to also perform OP1 with constant CONST1
5405 (with *POP0 being done last).
5407 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
5408 the resulting operation. *PCOMP_P is set to 1 if we would need to
5409 complement the innermost operand, otherwise it is unchanged.
5411 MODE is the mode in which the operation will be done. No bits outside
5412 the width of this mode matter. It is assumed that the width of this mode
5413 is smaller than or equal to HOST_BITS_PER_INT.
5415 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
5416 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
5417 result is simply *PCONST0.
5419 If the resulting operation cannot be expressed as one operation, we
5420 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
5423 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
5424 enum rtx_code
*pop0
;
5428 enum machine_mode mode
;
5431 enum rtx_code op0
= *pop0
;
5432 int const0
= *pconst0
;
5434 const0
&= GET_MODE_MASK (mode
);
5435 const1
&= GET_MODE_MASK (mode
);
5437 /* If OP0 is an AND, clear unimportant bits in CONST1. */
5441 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
5444 if (op1
== NIL
|| op0
== SET
)
5447 else if (op0
== NIL
)
5448 op0
= op1
, const0
= const1
;
5450 else if (op0
== op1
)
5472 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
5473 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
5476 /* If the two constants aren't the same, we can't do anything. The
5477 remaining six cases can all be done. */
5478 else if (const0
!= const1
)
5486 /* (a & b) | b == b */
5488 else /* op1 == XOR */
5489 /* (a ^ b) | b == a | b */
5495 /* (a & b) ^ b == (~a) & b */
5496 op0
= AND
, *pcomp_p
= 1;
5497 else /* op1 == IOR */
5498 /* (a | b) ^ b == a & ~b */
5499 op0
= AND
, *pconst0
= ~ const0
;
5504 /* (a | b) & b == b */
5506 else /* op1 == XOR */
5507 /* (a ^ b) & b) == (~a) & b */
5512 /* Check for NO-OP cases. */
5513 const0
&= GET_MODE_MASK (mode
);
5515 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
5517 else if (const0
== 0 && op0
== AND
)
5519 else if (const0
== GET_MODE_MASK (mode
) && op0
== AND
)
5528 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
5529 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
5530 that we started with.
5532 The shift is normally computed in the widest mode we find in VAROP, as
5533 long as it isn't a different number of words than RESULT_MODE. Exceptions
5534 are ASHIFTRT and ROTATE, which are always done in their original mode, */
5537 simplify_shift_const (x
, code
, result_mode
, varop
, count
)
5540 enum machine_mode result_mode
;
5544 enum rtx_code orig_code
= code
;
5545 int orig_count
= count
;
5546 enum machine_mode mode
= result_mode
;
5547 enum machine_mode shift_mode
, tmode
;
5549 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
5550 /* We form (outer_op (code varop count) (outer_const)). */
5551 enum rtx_code outer_op
= NIL
;
5554 int complement_p
= 0;
5557 /* If we were given an invalid count, don't do anything except exactly
5558 what was requested. */
5560 if (count
< 0 || count
> GET_MODE_BITSIZE (mode
))
5565 return gen_rtx (code
, mode
, varop
, gen_rtx (CONST_INT
, VOIDmode
, count
));
5568 /* Unless one of the branches of the `if' in this loop does a `continue',
5569 we will `break' the loop after the `if'. */
5573 /* If we have an operand of (clobber (const_int 0)), just return that
5575 if (GET_CODE (varop
) == CLOBBER
)
5578 /* If we discovered we had to complement VAROP, leave. Making a NOT
5579 here would cause an infinite loop. */
5583 /* Convert ROTATETRT to ROTATE. */
5584 if (code
== ROTATERT
)
5585 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
5587 /* Canonicalize LSHIFT to ASHIFT. */
5591 /* We need to determine what mode we will do the shift in. If the
5592 shift is a ASHIFTRT or ROTATE, we must always do it in the mode it
5593 was originally done in. Otherwise, we can do it in MODE, the widest
5594 mode encountered. */
5595 shift_mode
= (code
== ASHIFTRT
|| code
== ROTATE
? result_mode
: mode
);
5597 /* Handle cases where the count is greater than the size of the mode
5598 minus 1. For ASHIFT, use the size minus one as the count (this can
5599 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
5600 take the count modulo the size. For other shifts, the result is
5603 Since these shifts are being produced by the compiler by combining
5604 multiple operations, each of which are defined, we know what the
5605 result is supposed to be. */
5607 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
5609 if (code
== ASHIFTRT
)
5610 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
5611 else if (code
== ROTATE
|| code
== ROTATERT
)
5612 count
%= GET_MODE_BITSIZE (shift_mode
);
5615 /* We can't simply return zero because there may be an
5623 /* Negative counts are invalid and should not have been made (a
5624 programmer-specified negative count should have been handled
5629 /* We simplify the tests below and elsewhere by converting
5630 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
5631 `make_compound_operation' will convert it to a ASHIFTRT for
5632 those machines (such as Vax) that don't have a LSHIFTRT. */
5633 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_INT
5635 && (significant_bits (varop
, shift_mode
)
5636 & (1 << (GET_MODE_BITSIZE (shift_mode
) - 1))) == 0)
5639 switch (GET_CODE (varop
))
5645 new = expand_compound_operation (varop
);
5654 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
5655 minus the width of a smaller mode, we can do this with a
5656 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
5657 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
5658 && ! mode_dependent_address_p (XEXP (varop
, 0))
5659 && ! MEM_VOLATILE_P (varop
)
5660 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
5661 MODE_INT
, 1)) != BLKmode
)
5663 #if BYTES_BIG_ENDIAN
5664 new = gen_rtx (MEM
, tmode
, XEXP (varop
, 0));
5666 new = gen_rtx (MEM
, tmode
,
5667 plus_constant (XEXP (varop
, 0),
5668 count
/ BITS_PER_UNIT
));
5669 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop
);
5670 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop
);
5671 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop
);
5673 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
5674 : ZERO_EXTEND
, mode
, new);
5681 /* Similar to the case above, except that we can only do this if
5682 the resulting mode is the same as that of the underlying
5683 MEM and adjust the address depending on the *bits* endianness
5684 because of the way that bit-field extract insns are defined. */
5685 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
5686 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
5687 MODE_INT
, 1)) != BLKmode
5688 && tmode
== GET_MODE (XEXP (varop
, 0)))
5691 new = XEXP (varop
, 0);
5693 new = copy_rtx (XEXP (varop
, 0));
5694 SUBST (XEXP (new, 0),
5695 plus_constant (XEXP (new, 0),
5696 count
/ BITS_PER_UNIT
));
5699 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
5700 : ZERO_EXTEND
, mode
, new);
5707 /* If VAROP is a SUBREG, strip it as long as the inner operand has
5708 the same number of words as what we've seen so far. Then store
5709 the widest mode in MODE. */
5710 if (SUBREG_WORD (varop
) == 0
5711 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
5712 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5715 varop
= SUBREG_REG (varop
);
5716 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
5717 mode
= GET_MODE (varop
);
5723 /* Some machines use MULT instead of ASHIFT because MULT
5724 is cheaper. But it is still better on those machines to
5725 merge two shifts into one. */
5726 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
5727 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
5729 varop
= gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
5730 gen_rtx (CONST_INT
, VOIDmode
,
5731 exact_log2 (INTVAL (XEXP (varop
, 1)))));
5737 /* Similar, for when divides are cheaper. */
5738 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
5739 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
5741 varop
= gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
5742 gen_rtx (CONST_INT
, VOIDmode
,
5743 exact_log2 (INTVAL (XEXP (varop
, 1)))));
5749 /* If we are extracting just the sign bit of an arithmetic right
5750 shift, that shift is not needed. */
5751 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1)
5753 varop
= XEXP (varop
, 0);
5757 /* ... fall through ... */
5763 /* Here we have two nested shifts. The result is usually the
5764 AND of a new shift with a mask. We compute the result below. */
5765 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
5766 && INTVAL (XEXP (varop
, 1)) >= 0
5767 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
5768 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_INT
5769 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_INT
)
5771 enum rtx_code first_code
= GET_CODE (varop
);
5772 int first_count
= INTVAL (XEXP (varop
, 1));
5777 if (first_code
== LSHIFT
)
5778 first_code
= ASHIFT
;
5780 /* We have one common special case. We can't do any merging if
5781 the inner code is an ASHIFTRT of a smaller mode. However, if
5782 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
5783 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
5784 we can convert it to
5785 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
5786 This simplifies certain SIGN_EXTEND operations. */
5787 if (code
== ASHIFT
&& first_code
== ASHIFTRT
5788 && (GET_MODE_BITSIZE (result_mode
)
5789 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
5791 /* C3 has the low-order C1 bits zero. */
5793 mask
= GET_MODE_MASK (mode
) & ~ ((1 << first_count
) - 1);
5795 varop
= simplify_and_const_int (0, result_mode
,
5796 XEXP (varop
, 0), mask
);
5797 varop
= simplify_shift_const (0, ASHIFT
, result_mode
,
5799 count
= first_count
;
5804 /* If this was (ashiftrt (ashift foo C1) C2) and we know
5805 something about FOO's previous value, we may be able to
5806 optimize this even though the code below can't handle this
5809 If FOO has J high-order bits equal to the sign bit with
5810 J > C1, then we can convert this to either an ASHIFT or
5811 a ASHIFTRT depending on the two counts.
5813 We cannot do this if VAROP's mode is not SHIFT_MODE. */
5815 if (code
== ASHIFTRT
&& first_code
== ASHIFT
5816 && GET_MODE (varop
) == shift_mode
5817 && (inner
= get_last_value (XEXP (varop
, 0))) != 0)
5819 if ((GET_CODE (inner
) == CONST_INT
5820 && (INTVAL (inner
) >> (HOST_BITS_PER_INT
- (first_count
+ 1)) == 0
5821 || (INTVAL (inner
) >> (HOST_BITS_PER_INT
- (first_count
+ 1)) == -1)))
5822 || (GET_CODE (inner
) == SIGN_EXTEND
5823 && ((GET_MODE_BITSIZE (GET_MODE (inner
))
5824 - GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner
))))
5826 || (GET_CODE (inner
) == ASHIFTRT
5827 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
5828 && INTVAL (XEXP (inner
, 1)) >= first_count
))
5830 count
-= first_count
;
5832 count
= - count
, code
= ASHIFT
;
5833 varop
= XEXP (varop
, 0);
5838 /* There are some cases we can't do. If CODE is ASHIFTRT,
5839 we can only do this if FIRST_CODE is also ASHIFTRT.
5841 We can't do the case when CODE is ROTATE and FIRST_CODE is
5844 If the mode of this shift is not the mode of the outer shift,
5845 we can't do this if either shift is ASHIFTRT or ROTATE.
5847 Finally, we can't do any of these if the mode is too wide
5848 unless the codes are the same.
5850 Handle the case where the shift codes are the same
5853 if (code
== first_code
)
5855 if (GET_MODE (varop
) != result_mode
5856 && (code
== ASHIFTRT
|| code
== ROTATE
))
5859 count
+= first_count
;
5860 varop
= XEXP (varop
, 0);
5864 if (code
== ASHIFTRT
5865 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
5866 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_INT
5867 || (GET_MODE (varop
) != result_mode
5868 && (first_code
== ASHIFTRT
|| first_code
== ROTATE
5869 || code
== ROTATE
)))
5872 /* To compute the mask to apply after the shift, shift the
5873 significant bits of the inner shift the same way the
5874 outer shift will. */
5876 mask_rtx
= gen_rtx (CONST_INT
, VOIDmode
,
5877 significant_bits (varop
, GET_MODE (varop
)));
5880 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
5881 gen_rtx (CONST_INT
, VOIDmode
,
5884 /* Give up if we can't compute an outer operation to use. */
5886 || GET_CODE (mask_rtx
) != CONST_INT
5887 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
5889 result_mode
, &complement_p
))
5892 /* If the shifts are in the same direction, we add the
5893 counts. Otherwise, we subtract them. */
5894 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
5895 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
5896 count
+= first_count
;
5898 count
-= first_count
;
5900 /* If COUNT is positive, the new shift is usually CODE,
5901 except for the two exceptions below, in which case it is
5902 FIRST_CODE. If the count is negative, FIRST_CODE should
5905 && ((first_code
== ROTATE
&& code
== ASHIFT
)
5906 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
5909 code
= first_code
, count
= - count
;
5911 varop
= XEXP (varop
, 0);
5915 /* If we have (A << B << C) for any shift, we can convert this to
5916 (A << C << B). This wins if A is a constant. Only try this if
5917 B is not a constant. */
5919 else if (GET_CODE (varop
) == code
5920 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
5922 = simplify_binary_operation (code
, mode
,
5928 varop
= gen_rtx_combine (code
, mode
, new, XEXP (varop
, 1));
5935 /* Make this fit the case below. */
5936 varop
= gen_rtx_combine (XOR
, mode
, XEXP (varop
, 0),
5937 gen_rtx (CONST_INT
, VOIDmode
,
5938 GET_MODE_MASK (mode
)));
5944 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
5945 with C the size of VAROP - 1 and the shift is logical if
5946 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
5947 we have an (le X 0) operation. If we have an arithmetic shift
5948 and STORE_FLAG_VALUE is 1 or we have a logical shift with
5949 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
5951 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
5952 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
5953 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5954 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
5955 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
5956 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
5959 varop
= gen_rtx_combine (LE
, GET_MODE (varop
), XEXP (varop
, 1),
5962 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
5963 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
5968 /* If we have (shift (logical)), move the logical to the outside
5969 to allow it to possibly combine with another logical and the
5970 shift to combine with another shift. This also canonicalizes to
5971 what a ZERO_EXTRACT looks like. Also, some machines have
5972 (and (shift)) insns. */
5974 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
5975 && (new = simplify_binary_operation (code
, result_mode
,
5980 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
5981 INTVAL (new), result_mode
, &complement_p
))
5983 varop
= XEXP (varop
, 0);
5987 /* If we can't do that, try to simplify the shift in each arm of the
5988 logical expression, make a new logical expression, and apply
5989 the inverse distributive law. */
5991 rtx lhs
= simplify_shift_const (0, code
, result_mode
,
5992 XEXP (varop
, 0), count
);
5993 rtx rhs
= simplify_shift_const (0, code
, result_mode
,
5994 XEXP (varop
, 1), count
);
5996 varop
= gen_binary (GET_CODE (varop
), result_mode
, lhs
, rhs
);
5997 varop
= apply_distributive_law (varop
);
6004 /* convert (lshift (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
6005 says that the sign bit can be tested, FOO has mode MODE, C is
6006 GET_MODE_BITSIZE (MODE) - 1, and FOO has only the low-order bit
6009 && XEXP (varop
, 1) == const0_rtx
6010 && GET_MODE (XEXP (varop
, 0)) == result_mode
6011 && count
== GET_MODE_BITSIZE (result_mode
) - 1
6012 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_INT
6013 && ((STORE_FLAG_VALUE
6014 & (1 << (GET_MODE_BITSIZE (result_mode
) - 1))))
6015 && significant_bits (XEXP (varop
, 0), result_mode
) == 1
6016 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1,
6017 result_mode
, &complement_p
))
6019 varop
= XEXP (varop
, 0);
6026 /* If we are doing an arithmetic right shift of something known
6027 to be -1 or 0, we don't need the shift. */
6028 if (code
== ASHIFTRT
6029 && significant_bits (XEXP (varop
, 0), result_mode
) == 1)
6035 /* NEG commutes with ASHIFT since it is multiplication. Move the
6036 NEG outside to allow shifts to combine. */
6038 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0,
6039 result_mode
, &complement_p
))
6041 varop
= XEXP (varop
, 0);
6047 /* Similar to case above. If X is 0 or 1 then X - 1 is -1 or 0. */
6048 if (XEXP (varop
, 1) == constm1_rtx
&& code
== ASHIFTRT
6049 && significant_bits (XEXP (varop
, 0), result_mode
) == 1)
6055 /* If we have the same operands as above but we are shifting the
6056 sign bit into the low-order bit, we are exclusive-or'ing
6057 the operand of the PLUS with a one. */
6058 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
6059 && XEXP (varop
, 1) == constm1_rtx
6060 && significant_bits (XEXP (varop
, 0), result_mode
) == 1
6061 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1,
6062 result_mode
, &complement_p
))
6065 varop
= XEXP (varop
, 0);
6069 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
6070 significant in BAR are those being shifted out and those
6071 bits are known zero in FOO, we can replace the PLUS with FOO.
6072 Similarly in the other operand order. This code occurs when
6073 we are computing the size of a variable-size array. */
6075 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
6076 && count
< HOST_BITS_PER_INT
6077 && significant_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
6078 && (significant_bits (XEXP (varop
, 1), result_mode
)
6079 & significant_bits (XEXP (varop
, 0), result_mode
)) == 0)
6081 varop
= XEXP (varop
, 0);
6084 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
6085 && count
< HOST_BITS_PER_INT
6086 && 0 == (significant_bits (XEXP (varop
, 0), result_mode
)
6088 && 0 == (significant_bits (XEXP (varop
, 0), result_mode
)
6089 & significant_bits (XEXP (varop
, 1),
6092 varop
= XEXP (varop
, 1);
6096 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
6098 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
6099 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
6104 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
6105 INTVAL (new), result_mode
, &complement_p
))
6107 varop
= XEXP (varop
, 0);
6113 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
6114 with C the size of VAROP - 1 and the shift is logical if
6115 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
6116 we have a (gt X 0) operation. If the shift is arithmetic with
6117 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
6118 we have a (neg (gt X 0)) operation. */
6120 if (GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
6121 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
6122 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6123 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
6124 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
6125 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
6126 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
6129 varop
= gen_rtx_combine (GT
, GET_MODE (varop
), XEXP (varop
, 1),
6132 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
6133 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
6143 /* We need to determine what mode to do the shift in. If the shift is
6144 a ASHIFTRT or ROTATE, we must always do it in the mode it was originally
6145 done in. Otherwise, we can do it in MODE, the widest mode encountered.
6146 The code we care about is that of the shift that will actually be done,
6147 not the shift that was originally requested. */
6148 shift_mode
= (code
== ASHIFTRT
|| code
== ROTATE
? result_mode
: mode
);
6150 /* We have now finished analyzing the shift. The result should be
6151 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
6152 OUTER_OP is non-NIL, it is an operation that needs to be applied
6153 to the result of the shift. OUTER_CONST is the relevant constant,
6154 but we must turn off all bits turned off in the shift.
6156 If we were passed a value for X, see if we can use any pieces of
6157 it. If not, make new rtx. */
6159 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
6160 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6161 && INTVAL (XEXP (x
, 1)) == count
)
6162 const_rtx
= XEXP (x
, 1);
6164 const_rtx
= gen_rtx (CONST_INT
, VOIDmode
, count
);
6166 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
6167 && GET_MODE (XEXP (x
, 0)) == shift_mode
6168 && SUBREG_REG (XEXP (x
, 0)) == varop
)
6169 varop
= XEXP (x
, 0);
6170 else if (GET_MODE (varop
) != shift_mode
)
6171 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
6173 /* If we can't make the SUBREG, try to return what we were given. */
6174 if (GET_CODE (varop
) == CLOBBER
)
6175 return x
? x
: varop
;
6177 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
6182 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
6183 x
= gen_rtx_combine (code
, shift_mode
, varop
, const_rtx
);
6185 SUBST (XEXP (x
, 0), varop
);
6186 SUBST (XEXP (x
, 1), const_rtx
);
6189 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
6190 turn off all the bits that the shift would have turned off. */
6191 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
6192 x
= simplify_and_const_int (0, shift_mode
, x
,
6193 GET_MODE_MASK (result_mode
) >> orig_count
);
6195 /* Do the remainder of the processing in RESULT_MODE. */
6196 x
= gen_lowpart_for_combine (result_mode
, x
);
6198 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
6201 x
= gen_unary (NOT
, result_mode
, x
);
6203 if (outer_op
!= NIL
)
6205 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_INT
)
6206 outer_const
&= GET_MODE_MASK (result_mode
);
6208 if (outer_op
== AND
)
6209 x
= simplify_and_const_int (0, result_mode
, x
, outer_const
);
6210 else if (outer_op
== SET
)
6211 /* This means that we have determined that the result is
6212 equivalent to a constant. This should be rare. */
6213 x
= gen_rtx (CONST_INT
, VOIDmode
, outer_const
);
6214 else if (GET_RTX_CLASS (outer_op
) == '1')
6215 x
= gen_unary (outer_op
, result_mode
, x
);
6217 x
= gen_binary (outer_op
, result_mode
, x
,
6218 gen_rtx (CONST_INT
, VOIDmode
, outer_const
));
6224 /* Like recog, but we receive the address of a pointer to a new pattern.
6225 We try to match the rtx that the pointer points to.
6226 If that fails, we may try to modify or replace the pattern,
6227 storing the replacement into the same pointer object.
6229 Modifications include deletion or addition of CLOBBERs.
6231 PNOTES is a pointer to a location where any REG_UNUSED notes added for
6232 the CLOBBERs are placed.
6234 The value is the final insn code from the pattern ultimately matched,
6238 recog_for_combine (pnewpat
, insn
, pnotes
)
6243 register rtx pat
= *pnewpat
;
6244 int insn_code_number
;
6245 int num_clobbers_to_add
= 0;
6249 /* Is the result of combination a valid instruction? */
6250 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
6252 /* If it isn't, there is the possibility that we previously had an insn
6253 that clobbered some register as a side effect, but the combined
6254 insn doesn't need to do that. So try once more without the clobbers
6255 unless this represents an ASM insn. */
6257 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
6258 && GET_CODE (pat
) == PARALLEL
)
6262 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
6263 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
6266 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
6270 SUBST_INT (XVECLEN (pat
, 0), pos
);
6273 pat
= XVECEXP (pat
, 0, 0);
6275 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
6278 /* If we had any clobbers to add, make a new pattern than contains
6279 them. Then check to make sure that all of them are dead. */
6280 if (num_clobbers_to_add
)
6282 rtx newpat
= gen_rtx (PARALLEL
, VOIDmode
,
6283 gen_rtvec (GET_CODE (pat
) == PARALLEL
6284 ? XVECLEN (pat
, 0) + num_clobbers_to_add
6285 : num_clobbers_to_add
+ 1));
6287 if (GET_CODE (pat
) == PARALLEL
)
6288 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
6289 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
6291 XVECEXP (newpat
, 0, 0) = pat
;
6293 add_clobbers (newpat
, insn_code_number
);
6295 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
6296 i
< XVECLEN (newpat
, 0); i
++)
6298 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
6299 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
6301 notes
= gen_rtx (EXPR_LIST
, REG_UNUSED
,
6302 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
6310 return insn_code_number
;
6313 /* Like gen_lowpart but for use by combine. In combine it is not possible
6314 to create any new pseudoregs. However, it is safe to create
6315 invalid memory addresses, because combine will try to recognize
6316 them and all they will do is make the combine attempt fail.
6318 If for some reason this cannot do its job, an rtx
6319 (clobber (const_int 0)) is returned.
6320 An insn containing that will not be recognized. */
6325 gen_lowpart_for_combine (mode
, x
)
6326 enum machine_mode mode
;
6331 if (GET_MODE (x
) == mode
)
6334 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
6335 return gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
6337 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
6338 won't know what to do. So we will strip off the SUBREG here and
6339 process normally. */
6340 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
6343 if (GET_MODE (x
) == mode
)
6347 result
= gen_lowpart_common (mode
, x
);
6351 if (GET_CODE (x
) == MEM
)
6353 register int offset
= 0;
6356 /* Refuse to work on a volatile memory ref or one with a mode-dependent
6358 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
6359 return gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
6361 /* If we want to refer to something bigger than the original memref,
6362 generate a perverse subreg instead. That will force a reload
6363 of the original memref X. */
6364 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
6365 return gen_rtx (SUBREG
, mode
, x
, 0);
6367 #if WORDS_BIG_ENDIAN
6368 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
6369 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
6371 #if BYTES_BIG_ENDIAN
6372 /* Adjust the address so that the address-after-the-data
6374 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
6375 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
6377 new = gen_rtx (MEM
, mode
, plus_constant (XEXP (x
, 0), offset
));
6378 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x
);
6379 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x
);
6380 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x
);
6384 /* If X is a comparison operator, rewrite it in a new mode. This
6385 probably won't match, but may allow further simplifications. */
6386 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
6387 return gen_rtx_combine (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
6389 /* If we couldn't simplify X any other way, just enclose it in a
6390 SUBREG. Normally, this SUBREG won't match, but some patterns may
6391 include an explicit SUBREG or we may simplify it further in combine. */
6396 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
6397 word
= ((GET_MODE_SIZE (GET_MODE (x
))
6398 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
6400 return gen_rtx (SUBREG
, mode
, x
, word
);
6404 /* Make an rtx expression. This is a subset of gen_rtx and only supports
6405 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
6407 If the identical expression was previously in the insn (in the undobuf),
6408 it will be returned. Only if it is not found will a new expression
6413 gen_rtx_combine (va_alist
)
6418 enum machine_mode mode
;
6426 code
= va_arg (p
, enum rtx_code
);
6427 mode
= va_arg (p
, enum machine_mode
);
6428 n_args
= GET_RTX_LENGTH (code
);
6429 fmt
= GET_RTX_FORMAT (code
);
6431 if (n_args
== 0 || n_args
> 3)
6434 /* Get each arg and verify that it is supposed to be an expression. */
6435 for (j
= 0; j
< n_args
; j
++)
6440 args
[j
] = va_arg (p
, rtx
);
6443 /* See if this is in undobuf. Be sure we don't use objects that came
6444 from another insn; this could produce circular rtl structures. */
6446 for (i
= previous_num_undos
; i
< undobuf
.num_undo
; i
++)
6447 if (!undobuf
.undo
[i
].is_int
6448 && GET_CODE (undobuf
.undo
[i
].old_contents
) == code
6449 && GET_MODE (undobuf
.undo
[i
].old_contents
) == mode
)
6451 for (j
= 0; j
< n_args
; j
++)
6452 if (XEXP (undobuf
.undo
[i
].old_contents
, j
) != args
[j
])
6456 return undobuf
.undo
[i
].old_contents
;
6459 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
6460 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
6461 rt
= rtx_alloc (code
);
6462 PUT_MODE (rt
, mode
);
6463 XEXP (rt
, 0) = args
[0];
6466 XEXP (rt
, 1) = args
[1];
6468 XEXP (rt
, 2) = args
[2];
6473 /* These routines make binary and unary operations by first seeing if they
6474 fold; if not, a new expression is allocated. */
6477 gen_binary (code
, mode
, op0
, op1
)
6479 enum machine_mode mode
;
6484 if (GET_RTX_CLASS (code
) == '<')
6486 enum machine_mode op_mode
= GET_MODE (op0
);
6487 if (op_mode
== VOIDmode
)
6488 op_mode
= GET_MODE (op1
);
6489 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
6492 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
6497 /* Put complex operands first and constants second. */
6498 if (GET_RTX_CLASS (code
) == 'c'
6499 && ((CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
6500 || (GET_RTX_CLASS (GET_CODE (op0
)) == 'o'
6501 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')
6502 || (GET_CODE (op0
) == SUBREG
6503 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0
))) == 'o'
6504 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')))
6505 return gen_rtx_combine (code
, mode
, op1
, op0
);
6507 return gen_rtx_combine (code
, mode
, op0
, op1
);
6511 gen_unary (code
, mode
, op0
)
6513 enum machine_mode mode
;
6516 rtx result
= simplify_unary_operation (code
, mode
, op0
, mode
);
6521 return gen_rtx_combine (code
, mode
, op0
);
6524 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
6525 comparison code that will be tested.
6527 The result is a possibly different comparison code to use. *POP0 and
6528 *POP1 may be updated.
6530 It is possible that we might detect that a comparison is either always
6531 true or always false. However, we do not perform general constant
6532 folding in combine, so this knowledge isn't useful. Such tautologies
6533 should have been detected earlier. Hence we ignore all such cases. */
6535 static enum rtx_code
6536 simplify_comparison (code
, pop0
, pop1
)
6545 enum machine_mode mode
, tmode
;
6547 /* Try a few ways of applying the same transformation to both operands. */
6550 /* If both operands are the same constant shift, see if we can ignore the
6551 shift. We can if the shift is a rotate or if the bits shifted out of
6552 this shift are not significant for either input and if the type of
6553 comparison is compatible with the shift. */
6554 if (GET_CODE (op0
) == GET_CODE (op1
)
6555 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_INT
6556 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
6557 || ((GET_CODE (op0
) == LSHIFTRT
6558 || GET_CODE (op0
) == ASHIFT
|| GET_CODE (op0
) == LSHIFT
)
6559 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
6560 || (GET_CODE (op0
) == ASHIFTRT
6561 && (code
!= GTU
&& code
!= LTU
6562 && code
!= GEU
&& code
!= GEU
)))
6563 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
6564 && INTVAL (XEXP (op0
, 1)) >= 0
6565 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_INT
6566 && XEXP (op0
, 1) == XEXP (op1
, 1))
6568 enum machine_mode mode
= GET_MODE (op0
);
6569 unsigned mask
= GET_MODE_MASK (mode
);
6570 int shift_count
= INTVAL (XEXP (op0
, 1));
6572 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
6573 mask
&= (mask
>> shift_count
) << shift_count
;
6574 else if (GET_CODE (op0
) == ASHIFT
|| GET_CODE (op0
) == LSHIFT
)
6575 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
6577 if ((significant_bits (XEXP (op0
, 0), mode
) & ~ mask
) == 0
6578 && (significant_bits (XEXP (op1
, 0), mode
) & ~ mask
) == 0)
6579 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
6584 /* If both operands are AND's of a paradoxical SUBREG by constant, the
6585 SUBREGs are of the same mode, and, in both cases, the AND would
6586 be redundant if the comparison was done in the narrower mode,
6587 do the comparison in the narrower mode (e.g., we are AND'ing with 1
6588 and the operand's significant bits are 0xffffff01; in that case if
6589 we only care about QImode, we don't need the AND). This case occurs
6590 if the output mode of an scc insn is not SImode and
6591 STORE_FLAG_VALUE == 1 (e.g., the 386). */
6593 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
6594 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
6595 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
6596 && GET_CODE (XEXP (op0
, 0)) == SUBREG
6597 && GET_CODE (XEXP (op1
, 0)) == SUBREG
6598 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
6599 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
6600 && (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))
6601 == GET_MODE (SUBREG_REG (XEXP (op1
, 0))))
6602 && (significant_bits (SUBREG_REG (XEXP (op0
, 0)),
6603 GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
6604 & ~ INTVAL (XEXP (op0
, 1))) == 0
6605 && (significant_bits (SUBREG_REG (XEXP (op1
, 0)),
6606 GET_MODE (SUBREG_REG (XEXP (op1
, 0))))
6607 & ~ INTVAL (XEXP (op1
, 1))) == 0)
6609 op0
= SUBREG_REG (XEXP (op0
, 0));
6610 op1
= SUBREG_REG (XEXP (op1
, 0));
6612 /* the resulting comparison is always unsigned since we masked off
6613 the original sign bit. */
6614 code
= unsigned_condition (code
);
6620 /* If the first operand is a constant, swap the operands and adjust the
6621 comparison code appropriately. */
6622 if (CONSTANT_P (op0
))
6624 tem
= op0
, op0
= op1
, op1
= tem
;
6625 code
= swap_condition (code
);
6628 /* We now enter a loop during which we will try to simplify the comparison.
6629 For the most part, we only are concerned with comparisons with zero,
6630 but some things may really be comparisons with zero but not start
6631 out looking that way. */
6633 while (GET_CODE (op1
) == CONST_INT
)
6635 enum machine_mode mode
= GET_MODE (op0
);
6636 int mode_width
= GET_MODE_BITSIZE (mode
);
6637 unsigned mask
= GET_MODE_MASK (mode
);
6638 int equality_comparison_p
;
6639 int sign_bit_comparison_p
;
6640 int unsigned_comparison_p
;
6643 /* We only want to handle integral modes. This catches VOIDmode,
6644 CCmode, and the floating-point modes. An exception is that we
6645 can handle VOIDmode if OP0 is a COMPARE or a comparison
6648 if (GET_MODE_CLASS (mode
) != MODE_INT
6649 && ! (mode
== VOIDmode
6650 && (GET_CODE (op0
) == COMPARE
6651 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
6654 /* Get the constant we are comparing against and turn off all bits
6655 not on in our mode. */
6656 const_op
= INTVAL (op1
);
6657 if (mode_width
<= HOST_BITS_PER_INT
)
6660 /* If we are comparing against a constant power of two and the value
6661 being compared has only that single significant bit (e.g., it was
6662 `and'ed with that bit), we can replace this with a comparison
6665 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
6666 || code
== LT
|| code
== LTU
)
6667 && mode_width
<= HOST_BITS_PER_INT
6668 && exact_log2 (const_op
) >= 0
6669 && significant_bits (op0
, mode
) == const_op
)
6671 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
6672 op1
= const0_rtx
, const_op
= 0;
6675 /* Do some canonicalizations based on the comparison code. We prefer
6676 comparisons against zero and then prefer equality comparisons.
6677 If we can reduce the size of a constant, we will do that too. */
6682 /* < C is equivalent to <= (C - 1) */
6686 op1
= gen_rtx (CONST_INT
, VOIDmode
, const_op
);
6688 /* ... fall through to LE case below. */
6694 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
6698 op1
= gen_rtx (CONST_INT
, VOIDmode
, const_op
);
6702 /* If we are doing a <= 0 comparison on a value known to have
6703 a zero sign bit, we can replace this with == 0. */
6704 else if (const_op
== 0
6705 && mode_width
<= HOST_BITS_PER_INT
6706 && (significant_bits (op0
, mode
)
6707 & (1 << (mode_width
- 1))) == 0)
6712 /* >= C is equivalent to > (C - 1). */
6716 op1
= gen_rtx (CONST_INT
, VOIDmode
, const_op
);
6718 /* ... fall through to GT below. */
6724 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
6728 op1
= gen_rtx (CONST_INT
, VOIDmode
, const_op
);
6732 /* If we are doing a > 0 comparison on a value known to have
6733 a zero sign bit, we can replace this with != 0. */
6734 else if (const_op
== 0
6735 && mode_width
<= HOST_BITS_PER_INT
6736 && (significant_bits (op0
, mode
)
6737 & (1 << (mode_width
- 1))) == 0)
6742 /* < C is equivalent to <= (C - 1). */
6746 op1
= gen_rtx (CONST_INT
, VOIDmode
, const_op
);
6748 /* ... fall through ... */
6754 /* unsigned <= 0 is equivalent to == 0 */
6760 /* >= C is equivalent to < (C - 1). */
6764 op1
= gen_rtx (CONST_INT
, VOIDmode
, const_op
);
6766 /* ... fall through ... */
6772 /* unsigned > 0 is equivalent to != 0 */
6778 /* Compute some predicates to simplify code below. */
6780 equality_comparison_p
= (code
== EQ
|| code
== NE
);
6781 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
6782 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
6785 /* Now try cases based on the opcode of OP0. If none of the cases
6786 does a "continue", we exit this loop immediately after the
6789 switch (GET_CODE (op0
))
6792 /* If we are extracting a single bit from a variable position in
6793 a constant that has only a single bit set and are comparing it
6794 with zero, we can convert this into an equality comparison
6795 between the position and the location of the single bit. We can't
6796 do this if bit endian and we don't have an extzv since we then
6797 can't know what mode to use for the endianness adjustment. */
6799 #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv)
6800 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
6801 && XEXP (op0
, 1) == const1_rtx
6802 && equality_comparison_p
&& const_op
== 0
6803 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
6806 i
= (GET_MODE_BITSIZE
6807 (insn_operand_mode
[(int) CODE_FOR_extzv
][1]) - 1 - i
);
6810 op0
= XEXP (op0
, 2);
6811 op1
= gen_rtx (CONST_INT
, VOIDmode
, i
);
6814 /* Result is nonzero iff shift count is equal to I. */
6815 code
= reverse_condition (code
);
6820 /* ... fall through ... */
6823 tem
= expand_compound_operation (op0
);
6832 /* If testing for equality, we can take the NOT of the constant. */
6833 if (equality_comparison_p
6834 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
6836 op0
= XEXP (op0
, 0);
6841 /* If just looking at the sign bit, reverse the sense of the
6843 if (sign_bit_comparison_p
)
6845 op0
= XEXP (op0
, 0);
6846 code
= (code
== GE
? LT
: GE
);
6852 /* If testing for equality, we can take the NEG of the constant. */
6853 if (equality_comparison_p
6854 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
6856 op0
= XEXP (op0
, 0);
6861 /* The remaining cases only apply to comparisons with zero. */
6865 /* When X is ABS or is known positive,
6866 (neg X) is < 0 if and only if X != 0. */
6868 if (sign_bit_comparison_p
6869 && (GET_CODE (XEXP (op0
, 0)) == ABS
6870 || (mode_width
<= HOST_BITS_PER_INT
6871 && (significant_bits (XEXP (op0
, 0), mode
)
6872 & (1 << (mode_width
- 1))) == 0)))
6874 op0
= XEXP (op0
, 0);
6875 code
= (code
== LT
? NE
: EQ
);
6879 /* If we have NEG of something that is the result of a
6880 SIGN_EXTEND, SIGN_EXTRACT, or ASHIFTRT, we know that the
6881 two high-order bits must be the same and hence that
6882 "(-a) < 0" is equivalent to "a > 0". Otherwise, we can't
6884 if (GET_CODE (XEXP (op0
, 0)) == SIGN_EXTEND
6885 || (GET_CODE (XEXP (op0
, 0)) == SIGN_EXTRACT
6886 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
6887 && (INTVAL (XEXP (XEXP (op0
, 0), 1))
6888 < GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (op0
, 0), 0)))))
6889 || (GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
6890 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
6891 && XEXP (XEXP (op0
, 0), 1) != const0_rtx
)
6892 || ((tem
= get_last_value (XEXP (op0
, 0))) != 0
6893 && (GET_CODE (tem
) == SIGN_EXTEND
6894 || (GET_CODE (tem
) == SIGN_EXTRACT
6895 && GET_CODE (XEXP (tem
, 1)) == CONST_INT
6896 && (INTVAL (XEXP (tem
, 1))
6897 < GET_MODE_BITSIZE (GET_MODE (XEXP (tem
, 0)))))
6898 || (GET_CODE (tem
) == ASHIFTRT
6899 && GET_CODE (XEXP (tem
, 1)) == CONST_INT
6900 && XEXP (tem
, 1) != const0_rtx
))))
6902 op0
= XEXP (op0
, 0);
6903 code
= swap_condition (code
);
6909 /* If we are testing equality and our count is a constant, we
6910 can perform the inverse operation on our RHS. */
6911 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
6912 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
6913 op1
, XEXP (op0
, 1))) != 0)
6915 op0
= XEXP (op0
, 0);
6920 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
6921 a particular bit. Convert it to an AND of a constant of that
6922 bit. This will be converted into a ZERO_EXTRACT. */
6923 if (const_op
== 0 && sign_bit_comparison_p
6924 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
6925 && mode_width
<= HOST_BITS_PER_INT
)
6927 op0
= simplify_and_const_int (0, mode
, XEXP (op0
, 0),
6928 1 << (mode_width
- 1
6929 - INTVAL (XEXP (op0
, 1))));
6930 code
= (code
== LT
? NE
: EQ
);
6934 /* ... fall through ... */
6937 /* ABS is ignorable inside an equality comparison with zero. */
6938 if (const_op
== 0 && equality_comparison_p
)
6940 op0
= XEXP (op0
, 0);
6947 /* Can simplify (compare (zero/sign_extend FOO) CONST)
6948 to (compare FOO CONST) if CONST fits in FOO's mode and we
6949 are either testing inequality or have an unsigned comparison
6950 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
6951 if (! unsigned_comparison_p
6952 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
6953 <= HOST_BITS_PER_INT
)
6954 && ((unsigned) const_op
6955 < (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1))))
6957 op0
= XEXP (op0
, 0);
6963 /* If the inner mode is smaller and we are extracting the low
6964 part, we can treat the SUBREG as if it were a ZERO_EXTEND. */
6965 if (! subreg_lowpart_p (op0
)
6966 || GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) >= mode_width
)
6969 /* ... fall through ... */
6972 if ((unsigned_comparison_p
|| equality_comparison_p
)
6973 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
6974 <= HOST_BITS_PER_INT
)
6975 && ((unsigned) const_op
6976 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
6978 op0
= XEXP (op0
, 0);
6984 /* (eq (plus X C1) C2) -> (eq X (minus C2 C1)). We can only do
6985 this for equality comparisons due to pathological cases involving
6987 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
6988 && (tem
= simplify_binary_operation (MINUS
, mode
, op1
,
6989 XEXP (op0
, 1))) != 0)
6991 op0
= XEXP (op0
, 0);
6996 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
6997 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
6998 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
7000 op0
= XEXP (XEXP (op0
, 0), 0);
7001 code
= (code
== LT
? EQ
: NE
);
7007 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
7008 of bits in X minus 1, is one iff X > 0. */
7009 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
7010 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
7011 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
7012 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
7014 op0
= XEXP (op0
, 1);
7015 code
= (code
== GE
? LE
: GT
);
7021 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
7022 if C is zero or B is a constant. */
7023 if (equality_comparison_p
7024 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
7025 XEXP (op0
, 1), op1
)))
7027 op0
= XEXP (op0
, 0);
7034 case LT
: case LTU
: case LE
: case LEU
:
7035 case GT
: case GTU
: case GE
: case GEU
:
7036 /* We can't do anything if OP0 is a condition code value, rather
7037 than an actual data value. */
7040 || XEXP (op0
, 0) == cc0_rtx
7042 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
7045 /* Get the two operands being compared. */
7046 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
7047 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
7049 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
7051 /* Check for the cases where we simply want the result of the
7052 earlier test or the opposite of that result. */
7054 || (code
== EQ
&& reversible_comparison_p (op0
))
7055 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_INT
7056 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
7057 && (STORE_FLAG_VALUE
7058 & (1 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1)))
7060 || (code
== GE
&& reversible_comparison_p (op0
)))))
7062 code
= (code
== LT
|| code
== NE
7063 ? GET_CODE (op0
) : reverse_condition (GET_CODE (op0
)));
7064 op0
= tem
, op1
= tem1
;
7070 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
7072 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
7073 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
7074 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
7076 op0
= XEXP (op0
, 1);
7077 code
= (code
== GE
? GT
: LE
);
7083 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
7084 will be converted to a ZERO_EXTRACT later. */
7085 if (const_op
== 0 && equality_comparison_p
7086 && (GET_CODE (XEXP (op0
, 0)) == ASHIFT
7087 || GET_CODE (XEXP (op0
, 0)) == LSHIFT
)
7088 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
7090 op0
= simplify_and_const_int
7091 (op0
, mode
, gen_rtx_combine (LSHIFTRT
, mode
,
7093 XEXP (XEXP (op0
, 0), 1)),
7098 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
7099 zero and X is a comparison and C1 and C2 describe only bits set
7100 in STORE_FLAG_VALUE, we can compare with X. */
7101 if (const_op
== 0 && equality_comparison_p
7102 && mode_width
<= HOST_BITS_PER_INT
7103 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
7104 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
7105 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
7106 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
7107 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_INT
)
7109 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
7110 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
7111 if ((~ STORE_FLAG_VALUE
& mask
) == 0
7112 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
7113 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
7114 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
7116 op0
= XEXP (XEXP (op0
, 0), 0);
7121 /* If we are doing an equality comparison of an AND of a bit equal
7122 to the sign bit, replace this with a LT or GE comparison of
7123 the underlying value. */
7124 if (equality_comparison_p
7126 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
7127 && mode_width
<= HOST_BITS_PER_INT
7128 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
7129 == 1 << (mode_width
- 1)))
7131 op0
= XEXP (op0
, 0);
7132 code
= (code
== EQ
? GE
: LT
);
7136 /* If this AND operation is really a ZERO_EXTEND from a narrower
7137 mode, the constant fits within that mode, and this is either an
7138 equality or unsigned comparison, try to do this comparison in
7139 the narrower mode. */
7140 if ((equality_comparison_p
|| unsigned_comparison_p
)
7141 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
7142 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
7143 & GET_MODE_MASK (mode
))
7145 && const_op
>> i
== 0
7146 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
7148 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
7155 /* If we have (compare (xshift FOO N) (const_int C)) and
7156 the high order N bits of FOO (N+1 if an inequality comparison)
7157 are not significant, we can do this by comparing FOO with C
7158 shifted right N bits so long as the low-order N bits of C are
7160 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
7161 && INTVAL (XEXP (op0
, 1)) >= 0
7162 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
7163 < HOST_BITS_PER_INT
)
7164 && (const_op
& ~ ((1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
7165 && mode_width
<= HOST_BITS_PER_INT
7166 && (significant_bits (XEXP (op0
, 0), mode
)
7167 & ~ (mask
>> (INTVAL (XEXP (op0
, 1))
7168 + ! equality_comparison_p
))) == 0)
7170 const_op
>>= INTVAL (XEXP (op0
, 1));
7171 op1
= gen_rtx (CONST_INT
, VOIDmode
, const_op
);
7172 op0
= XEXP (op0
, 0);
7176 /* If we are doing a sign bit comparison, it means we are testing
7177 a particular bit. Convert it to the appropriate AND. */
7178 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
7179 && mode_width
<= HOST_BITS_PER_INT
)
7181 op0
= simplify_and_const_int (0, mode
, XEXP (op0
, 0),
7182 1 << ( mode_width
- 1
7183 - INTVAL (XEXP (op0
, 1))));
7184 code
= (code
== LT
? NE
: EQ
);
7188 /* If this an equality comparison with zero and we are shifting
7189 the low bit to the sign bit, we can convert this to an AND of the
7191 if (const_op
== 0 && equality_comparison_p
7192 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
7193 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
7195 op0
= simplify_and_const_int (0, mode
, XEXP (op0
, 0), 1);
7201 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
7202 do the comparison in a narrower mode. */
7203 if (! unsigned_comparison_p
7204 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
7205 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
7206 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
7207 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
7208 MODE_INT
, 1)) != VOIDmode
7209 && ((unsigned) const_op
<= GET_MODE_MASK (tmode
)
7210 || (unsigned) - const_op
<= GET_MODE_MASK (tmode
)))
7212 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
7216 /* ... fall through ... */
7218 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
7219 the low order N bits of FOO are not significant, we can do this
7220 by comparing FOO with C shifted left N bits so long as no
7222 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
7223 && INTVAL (XEXP (op0
, 1)) >= 0
7224 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_INT
7225 && mode_width
<= HOST_BITS_PER_INT
7226 && (significant_bits (XEXP (op0
, 0), mode
)
7227 & ((1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
7229 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
7232 const_op
<<= INTVAL (XEXP (op0
, 1));
7233 op1
= gen_rtx (CONST_INT
, VOIDmode
, const_op
);
7234 op0
= XEXP (op0
, 0);
7238 /* If we are using this shift to extract just the sign bit, we
7239 can replace this with an LT or GE comparison. */
7241 && (equality_comparison_p
|| sign_bit_comparison_p
)
7242 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
7243 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
7245 op0
= XEXP (op0
, 0);
7246 code
= (code
== NE
|| code
== GT
? LT
: GE
);
7255 /* Now make any compound operations involved in this comparison. Then,
7256 check for an outmost SUBREG on OP0 that isn't doing anything or is
7257 paradoxical. The latter case can only occur when it is known that the
7258 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
7259 We can never remove a SUBREG for a non-equality comparison because the
7260 sign bit is in a different place in the underlying object. */
7262 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
7263 op1
= make_compound_operation (op1
, SET
);
7265 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
7266 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
7267 && (code
== NE
|| code
== EQ
)
7268 && ((GET_MODE_SIZE (GET_MODE (op0
))
7269 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
7271 op0
= SUBREG_REG (op0
);
7272 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
7275 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
7276 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
7277 && (code
== NE
|| code
== EQ
)
7278 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_INT
7279 && (significant_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
7280 & ~ GET_MODE_MASK (GET_MODE (op0
))) == 0
7281 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
7283 (significant_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
7284 & ~ GET_MODE_MASK (GET_MODE (op0
))) == 0))
7285 op0
= SUBREG_REG (op0
), op1
= tem
;
7287 /* We now do the opposite procedure: Some machines don't have compare
7288 insns in all modes. If OP0's mode is an integer mode smaller than a
7289 word and we can't do a compare in that mode, see if there is a larger
7290 mode for which we can do the compare and where the only significant
7291 bits in OP0 and OP1 are those in the narrower mode. We can do
7292 this if this is an equality comparison, in which case we can
7293 merely widen the operation, or if we are testing the sign bit, in
7294 which case we can explicitly put in the test. */
7296 mode
= GET_MODE (op0
);
7297 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
7298 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
7299 && cmp_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
)
7300 for (tmode
= GET_MODE_WIDER_MODE (mode
);
7301 tmode
!= VOIDmode
&& GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_INT
;
7302 tmode
= GET_MODE_WIDER_MODE (tmode
))
7303 if (cmp_optab
->handlers
[(int) tmode
].insn_code
!= CODE_FOR_nothing
7304 && (significant_bits (op0
, tmode
) & ~ GET_MODE_MASK (mode
)) == 0
7305 && (significant_bits (op1
, tmode
) & ~ GET_MODE_MASK (mode
)) == 0
7306 && (code
== EQ
|| code
== NE
7307 || (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
7308 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_INT
)))
7310 op0
= gen_lowpart_for_combine (tmode
, op0
);
7311 op1
= gen_lowpart_for_combine (tmode
, op1
);
7313 if (code
== LT
|| code
== GE
)
7315 op0
= gen_binary (AND
, tmode
, op0
,
7316 gen_rtx (CONST_INT
, VOIDmode
,
7317 1 << (GET_MODE_BITSIZE (mode
) - 1)));
7318 code
= (code
== LT
) ? NE
: EQ
;
7330 /* Return 1 if we know that X, a comparison operation, is not operating
7331 on a floating-point value or is EQ or NE, meaning that we can safely
7335 reversible_comparison_p (x
)
7338 if (TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
7339 || GET_CODE (x
) == NE
|| GET_CODE (x
) == EQ
)
7342 switch (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))))
7348 x
= get_last_value (XEXP (x
, 0));
7349 return (x
&& GET_CODE (x
) == COMPARE
7350 && GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) == MODE_INT
);
7356 /* Utility function for following routine. Called when X is part of a value
7357 being stored into reg_last_set_value. Sets reg_last_set_table_tick
7358 for each register mentioned. Similar to mention_regs in cse.c */
7361 update_table_tick (x
)
7364 register enum rtx_code code
= GET_CODE (x
);
7365 register char *fmt
= GET_RTX_FORMAT (code
);
7370 int regno
= REGNO (x
);
7371 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
7372 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
7374 for (i
= regno
; i
< endregno
; i
++)
7375 reg_last_set_table_tick
[i
] = label_tick
;
7380 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7381 /* Note that we can't have an "E" in values stored; see
7382 get_last_value_validate. */
7384 update_table_tick (XEXP (x
, i
));
7387 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
7388 are saying that the register is clobbered and we no longer know its
7389 value. If INSN is zero, don't update reg_last_set; this call is normally
7390 done with VALUE also zero to invalidate the register. */
7393 record_value_for_reg (reg
, insn
, value
)
7398 int regno
= REGNO (reg
);
7399 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
7400 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
7403 /* If VALUE contains REG and we have a previous value for REG, substitute
7404 the previous value. */
7405 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
7409 /* Set things up so get_last_value is allowed to see anything set up to
7411 subst_low_cuid
= INSN_CUID (insn
);
7412 tem
= get_last_value (reg
);
7415 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
7418 /* For each register modified, show we don't know its value, that
7419 its value has been updated, and that we don't know the location of
7420 the death of the register. */
7421 for (i
= regno
; i
< endregno
; i
++)
7424 reg_last_set
[i
] = insn
;
7425 reg_last_set_value
[i
] = 0;
7426 reg_last_death
[i
] = 0;
7429 /* Mark registers that are being referenced in this value. */
7431 update_table_tick (value
);
7433 /* Now update the status of each register being set.
7434 If someone is using this register in this block, set this register
7435 to invalid since we will get confused between the two lives in this
7436 basic block. This makes using this register always invalid. In cse, we
7437 scan the table to invalidate all entries using this register, but this
7438 is too much work for us. */
7440 for (i
= regno
; i
< endregno
; i
++)
7442 reg_last_set_label
[i
] = label_tick
;
7443 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
7444 reg_last_set_invalid
[i
] = 1;
7446 reg_last_set_invalid
[i
] = 0;
7449 /* The value being assigned might refer to X (like in "x++;"). In that
7450 case, we must replace it with (clobber (const_int 0)) to prevent
7452 if (value
&& ! get_last_value_validate (&value
,
7453 reg_last_set_label
[regno
], 0))
7455 value
= copy_rtx (value
);
7456 if (! get_last_value_validate (&value
, reg_last_set_label
[regno
], 1))
7460 /* For the main register being modified, update the value. */
7461 reg_last_set_value
[regno
] = value
;
7465 /* Used for communication between the following two routines. */
7466 static rtx record_dead_insn
;
7468 /* Called via note_stores from record_dead_and_set_regs to handle one
7469 SET or CLOBBER in an insn. */
7472 record_dead_and_set_regs_1 (dest
, setter
)
7475 if (GET_CODE (dest
) == REG
)
7477 /* If we are setting the whole register, we know its value. Otherwise
7478 show that we don't know the value. We can handle SUBREG in
7480 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
7481 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
7482 else if (GET_CODE (setter
) == SET
7483 && GET_CODE (SET_DEST (setter
)) == SUBREG
7484 && SUBREG_REG (SET_DEST (setter
)) == dest
7485 && subreg_lowpart_p (SET_DEST (setter
)))
7486 record_value_for_reg
7487 (dest
, record_dead_insn
,
7488 gen_lowpart_for_combine (GET_MODE (SET_DEST (setter
)),
7491 record_value_for_reg (dest
, record_dead_insn
, 0);
7493 else if (GET_CODE (dest
) == MEM
7494 /* Ignore pushes, they clobber nothing. */
7495 && ! push_operand (dest
, GET_MODE (dest
)))
7496 mem_last_set
= INSN_CUID (record_dead_insn
);
7499 /* Update the records of when each REG was most recently set or killed
7500 for the things done by INSN. This is the last thing done in processing
7501 INSN in the combiner loop.
7503 We update reg_last_set, reg_last_set_value, reg_last_death, and also the
7504 similar information mem_last_set (which insn most recently modified memory)
7505 and last_call_cuid (which insn was the most recent subroutine call). */
7508 record_dead_and_set_regs (insn
)
7512 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
7514 if (REG_NOTE_KIND (link
) == REG_DEAD
)
7515 reg_last_death
[REGNO (XEXP (link
, 0))] = insn
;
7516 else if (REG_NOTE_KIND (link
) == REG_INC
)
7517 record_value_for_reg (XEXP (link
, 0), insn
, 0);
7520 if (GET_CODE (insn
) == CALL_INSN
)
7521 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
7523 record_dead_insn
= insn
;
7524 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
);
7527 /* Utility routine for the following function. Verify that all the registers
7528 mentioned in *LOC are valid when *LOC was part of a value set when
7529 label_tick == TICK. Return 0 if some are not.
7531 If REPLACE is non-zero, replace the invalid reference with
7532 (clobber (const_int 0)) and return 1. This replacement is useful because
7533 we often can get useful information about the form of a value (e.g., if
7534 it was produced by a shift that always produces -1 or 0) even though
7535 we don't know exactly what registers it was produced from. */
7538 get_last_value_validate (loc
, tick
, replace
)
7544 char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
7545 int len
= GET_RTX_LENGTH (GET_CODE (x
));
7548 if (GET_CODE (x
) == REG
)
7550 int regno
= REGNO (x
);
7551 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
7552 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
7555 for (j
= regno
; j
< endregno
; j
++)
7556 if (reg_last_set_invalid
[j
]
7557 /* If this is a pseudo-register that was only set once, it is
7559 || (! (regno
>= FIRST_PSEUDO_REGISTER
&& reg_n_sets
[regno
] == 1)
7560 && reg_last_set_label
[j
] > tick
))
7563 *loc
= gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
7570 for (i
= 0; i
< len
; i
++)
7572 && get_last_value_validate (&XEXP (x
, i
), tick
, replace
) == 0)
7573 /* Don't bother with these. They shouldn't occur anyway. */
7577 /* If we haven't found a reason for it to be invalid, it is valid. */
7581 /* Get the last value assigned to X, if known. Some registers
7582 in the value may be replaced with (clobber (const_int 0)) if their value
7583 is known longer known reliably. */
7592 /* If this is a non-paradoxical SUBREG, get the value of its operand and
7593 then convert it to the desired mode. If this is a paradoxical SUBREG,
7594 we cannot predict what values the "extra" bits might have. */
7595 if (GET_CODE (x
) == SUBREG
7596 && subreg_lowpart_p (x
)
7597 && (GET_MODE_SIZE (GET_MODE (x
))
7598 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
7599 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
7600 return gen_lowpart_for_combine (GET_MODE (x
), value
);
7602 if (GET_CODE (x
) != REG
)
7606 value
= reg_last_set_value
[regno
];
7608 /* If we don't have a value, it isn't for this basic block, or if it was
7609 set in a later insn that the ones we are processing, return 0. */
7612 || (reg_n_sets
[regno
] != 1
7613 && (reg_last_set_label
[regno
] != label_tick
7614 || INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)))
7617 /* If the value has all its register valid, return it. */
7618 if (get_last_value_validate (&value
, reg_last_set_label
[regno
], 0))
7621 /* Otherwise, make a copy and replace any invalid register with
7622 (clobber (const_int 0)). If that fails for some reason, return 0. */
7624 value
= copy_rtx (value
);
7625 if (get_last_value_validate (&value
, reg_last_set_label
[regno
], 1))
7631 /* Return nonzero if expression X refers to a REG or to memory
7632 that is set in an instruction more recent than FROM_CUID. */
7635 use_crosses_set_p (x
, from_cuid
)
7641 register enum rtx_code code
= GET_CODE (x
);
7645 register int regno
= REGNO (x
);
7646 #ifdef PUSH_ROUNDING
7647 /* Don't allow uses of the stack pointer to be moved,
7648 because we don't know whether the move crosses a push insn. */
7649 if (regno
== STACK_POINTER_REGNUM
)
7652 return (reg_last_set
[regno
]
7653 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
);
7656 if (code
== MEM
&& mem_last_set
> from_cuid
)
7659 fmt
= GET_RTX_FORMAT (code
);
7661 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7666 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7667 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
7670 else if (fmt
[i
] == 'e'
7671 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
7677 /* Define three variables used for communication between the following
7680 static int reg_dead_regno
, reg_dead_endregno
;
7681 static int reg_dead_flag
;
7683 /* Function called via note_stores from reg_dead_at_p.
7685 If DEST is within [reg_dead_rengno, reg_dead_endregno), set
7686 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
7689 reg_dead_at_p_1 (dest
, x
)
7693 int regno
, endregno
;
7695 if (GET_CODE (dest
) != REG
)
7698 regno
= REGNO (dest
);
7699 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
7700 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
7702 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
7703 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
7706 /* Return non-zero if REG is known to be dead at INSN.
7708 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
7709 referencing REG, it is dead. If we hit a SET referencing REG, it is
7710 live. Otherwise, see if it is live or dead at the start of the basic
7714 reg_dead_at_p (reg
, insn
)
7720 /* Set variables for reg_dead_at_p_1. */
7721 reg_dead_regno
= REGNO (reg
);
7722 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
7723 ? HARD_REGNO_NREGS (reg_dead_regno
,
7729 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
7730 beginning of function. */
7731 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
;
7732 insn
= prev_nonnote_insn (insn
))
7734 note_stores (PATTERN (insn
), reg_dead_at_p_1
);
7736 return reg_dead_flag
== 1 ? 1 : 0;
7738 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
7742 /* Get the basic block number that we were in. */
7747 for (block
= 0; block
< n_basic_blocks
; block
++)
7748 if (insn
== basic_block_head
[block
])
7751 if (block
== n_basic_blocks
)
7755 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
7756 if (basic_block_live_at_start
[block
][i
/ HOST_BITS_PER_INT
]
7757 & (1 << (i
% HOST_BITS_PER_INT
)))
7763 /* Remove register number REGNO from the dead registers list of INSN.
7765 Return the note used to record the death, if there was one. */
7768 remove_death (regno
, insn
)
7772 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
7775 remove_note (insn
, note
);
7780 /* For each register (hardware or pseudo) used within expression X, if its
7781 death is in an instruction with cuid between FROM_CUID (inclusive) and
7782 TO_INSN (exclusive), put a REG_DEAD note for that register in the
7783 list headed by PNOTES.
7785 This is done when X is being merged by combination into TO_INSN. These
7786 notes will then be distributed as needed. */
7789 move_deaths (x
, from_cuid
, to_insn
, pnotes
)
7796 register int len
, i
;
7797 register enum rtx_code code
= GET_CODE (x
);
7801 register int regno
= REGNO (x
);
7802 register rtx where_dead
= reg_last_death
[regno
];
7804 if (where_dead
&& INSN_CUID (where_dead
) >= from_cuid
7805 && INSN_CUID (where_dead
) < INSN_CUID (to_insn
))
7807 rtx note
= remove_death (regno
, reg_last_death
[regno
]);
7809 /* It is possible for the call above to return 0. This can occur
7810 when reg_last_death points to I2 or I1 that we combined with.
7811 In that case make a new note. */
7815 XEXP (note
, 1) = *pnotes
;
7819 *pnotes
= gen_rtx (EXPR_LIST
, REG_DEAD
, x
, *pnotes
);
7825 else if (GET_CODE (x
) == SET
)
7827 rtx dest
= SET_DEST (x
);
7829 move_deaths (SET_SRC (x
), from_cuid
, to_insn
, pnotes
);
7831 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
7832 that accesses one word of a multi-word item, some
7833 piece of everything register in the expression is used by
7834 this insn, so remove any old death. */
7836 if (GET_CODE (dest
) == ZERO_EXTRACT
7837 || GET_CODE (dest
) == STRICT_LOW_PART
7838 || (GET_CODE (dest
) == SUBREG
7839 && (((GET_MODE_SIZE (GET_MODE (dest
))
7840 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
7841 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
7842 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
7844 move_deaths (dest
, from_cuid
, to_insn
, pnotes
);
7848 /* If this is some other SUBREG, we know it replaces the entire
7849 value, so use that as the destination. */
7850 if (GET_CODE (dest
) == SUBREG
)
7851 dest
= SUBREG_REG (dest
);
7853 /* If this is a MEM, adjust deaths of anything used in the address.
7854 For a REG (the only other possibility), the entire value is
7855 being replaced so the old value is not used in this insn. */
7857 if (GET_CODE (dest
) == MEM
)
7858 move_deaths (XEXP (dest
, 0), from_cuid
, to_insn
, pnotes
);
7862 else if (GET_CODE (x
) == CLOBBER
)
7865 len
= GET_RTX_LENGTH (code
);
7866 fmt
= GET_RTX_FORMAT (code
);
7868 for (i
= 0; i
< len
; i
++)
7873 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7874 move_deaths (XVECEXP (x
, i
, j
), from_cuid
, to_insn
, pnotes
);
7876 else if (fmt
[i
] == 'e')
7877 move_deaths (XEXP (x
, i
), from_cuid
, to_insn
, pnotes
);
7881 /* Return 1 if X is the target of a bit-field assignment in BODY, the
7882 pattern of an insn. X must be a REG. */
7885 reg_bitfield_target_p (x
, body
)
7891 if (GET_CODE (body
) == SET
)
7893 rtx dest
= SET_DEST (body
);
7895 int regno
, tregno
, endregno
, endtregno
;
7897 if (GET_CODE (dest
) == ZERO_EXTRACT
)
7898 target
= XEXP (dest
, 0);
7899 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
7900 target
= SUBREG_REG (XEXP (dest
, 0));
7904 if (GET_CODE (target
) == SUBREG
)
7905 target
= SUBREG_REG (target
);
7907 if (GET_CODE (target
) != REG
)
7910 tregno
= REGNO (target
), regno
= REGNO (x
);
7911 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
7914 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
7915 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
7917 return endregno
> tregno
&& regno
< endtregno
;
7920 else if (GET_CODE (body
) == PARALLEL
)
7921 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
7922 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
7928 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
7929 as appropriate. I3 and I2 are the insns resulting from the combination
7930 insns including FROM (I2 may be zero).
7932 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
7933 not need REG_DEAD notes because they are being substituted for. This
7934 saves searching in the most common cases.
7936 Each note in the list is either ignored or placed on some insns, depending
7937 on the type of note. */
7940 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
7944 rtx elim_i2
, elim_i1
;
7946 rtx note
, next_note
;
7949 for (note
= notes
; note
; note
= next_note
)
7951 rtx place
= 0, place2
= 0;
7953 /* If this NOTE references a pseudo register, ensure it references
7954 the latest copy of that register. */
7955 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
7956 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
7957 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
7959 next_note
= XEXP (note
, 1);
7960 switch (REG_NOTE_KIND (note
))
7963 /* If this register is set or clobbered in I3, put the note there
7964 unless there is one already. */
7965 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
7967 if (! (GET_CODE (XEXP (note
, 0)) == REG
7968 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
7969 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
7972 /* Otherwise, if this register is used by I3, then this register
7973 now dies here, so we must put a REG_DEAD note here unless there
7975 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
7976 && ! (GET_CODE (XEXP (note
, 0)) == REG
7977 ? find_regno_note (i3
, REG_DEAD
, REGNO (XEXP (note
, 0)))
7978 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
7980 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
7988 /* These notes say something about results of an insn. We can
7989 only support them if they used to be on I3 in which case they
7990 remain on I3. Otherwise they are ignored. */
7991 if (from_insn
== i3
)
7996 case REG_NO_CONFLICT
:
7998 /* These notes say something about how a register is used. They must
7999 be present on any use of the register in I2 or I3. */
8000 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
8003 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
8013 /* It is too much trouble to try to see if this note is still
8014 correct in all situations. It is better to simply delete it. */
8018 /* If the insn previously containing this note still exists,
8019 put it back where it was. Otherwise move it to the previous
8020 insn. Adjust the corresponding REG_LIBCALL note. */
8021 if (GET_CODE (from_insn
) != NOTE
)
8025 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, 0);
8026 place
= prev_real_insn (from_insn
);
8028 XEXP (tem
, 0) = place
;
8033 /* This is handled similarly to REG_RETVAL. */
8034 if (GET_CODE (from_insn
) != NOTE
)
8038 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, 0);
8039 place
= next_real_insn (from_insn
);
8041 XEXP (tem
, 0) = place
;
8046 /* If the register is used as an input in I3, it dies there.
8047 Similarly for I2, if it is non-zero and adjacent to I3.
8049 If the register is not used as an input in either I3 or I2
8050 and it is not one of the registers we were supposed to eliminate,
8051 there are two possibilities. We might have a non-adjacent I2
8052 or we might have somehow eliminated an additional register
8053 from a computation. For example, we might have had A & B where
8054 we discover that B will always be zero. In this case we will
8055 eliminate the reference to A.
8057 In both cases, we must search to see if we can find a previous
8058 use of A and put the death note there. */
8060 if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
8062 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
8063 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
8066 if (XEXP (note
, 0) == elim_i2
|| XEXP (note
, 0) == elim_i1
)
8070 for (tem
= prev_nonnote_insn (i3
);
8071 tem
&& (GET_CODE (tem
) == INSN
8072 || GET_CODE (tem
) == CALL_INSN
);
8073 tem
= prev_nonnote_insn (tem
))
8075 /* If the register is being set at TEM, see if that is all
8076 TEM is doing. If so, delete TEM. Otherwise, make this
8077 into a REG_UNUSED note instead. */
8078 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
8080 rtx set
= single_set (tem
);
8082 /* Verify that it was the set, and not a clobber that
8083 modified the register. */
8085 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
8086 && rtx_equal_p (XEXP (note
, 0), SET_DEST (set
)))
8088 /* Move the notes and links of TEM elsewhere.
8089 This might delete other dead insns recursively.
8090 First set the pattern to something that won't use
8093 PATTERN (tem
) = pc_rtx
;
8095 distribute_notes (REG_NOTES (tem
), tem
, tem
, 0, 0, 0);
8096 distribute_links (LOG_LINKS (tem
));
8098 PUT_CODE (tem
, NOTE
);
8099 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
8100 NOTE_SOURCE_FILE (tem
) = 0;
8104 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
8106 /* If there isn't already a REG_UNUSED note, put one
8108 if (! find_regno_note (tem
, REG_UNUSED
,
8109 REGNO (XEXP (note
, 0))))
8114 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
)))
8121 /* If the register is set or already dead at PLACE, we needn't do
8122 anything with this note if it is still a REG_DEAD note.
8124 Note that we cannot use just `dead_or_set_p' here since we can
8125 convert an assignment to a register into a bit-field assignment.
8126 Therefore, we must also omit the note if the register is the
8127 target of a bitfield assignment. */
8129 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
8131 int regno
= REGNO (XEXP (note
, 0));
8133 if (dead_or_set_p (place
, XEXP (note
, 0))
8134 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
8136 /* Unless the register previously died in PLACE, clear
8137 reg_last_death. [I no longer understand why this is
8139 if (reg_last_death
[regno
] != place
)
8140 reg_last_death
[regno
] = 0;
8144 reg_last_death
[regno
] = place
;
8146 /* If this is a death note for a hard reg that is occupying
8147 multiple registers, ensure that we are still using all
8148 parts of the object. If we find a piece of the object
8149 that is unused, we must add a USE for that piece before
8150 PLACE and put the appropriate REG_DEAD note on it.
8152 An alternative would be to put a REG_UNUSED for the pieces
8153 on the insn that set the register, but that can't be done if
8154 it is not in the same block. It is simpler, though less
8155 efficient, to add the USE insns. */
8157 if (place
&& regno
< FIRST_PSEUDO_REGISTER
8158 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
8161 = regno
+ HARD_REGNO_NREGS (regno
,
8162 GET_MODE (XEXP (note
, 0)));
8166 for (i
= regno
; i
< endregno
; i
++)
8167 if (! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0))
8169 rtx piece
= gen_rtx (REG
, word_mode
, i
);
8172 /* See if we already placed a USE note for this
8173 register in front of PLACE. */
8175 GET_CODE (PREV_INSN (p
)) == INSN
8176 && GET_CODE (PATTERN (PREV_INSN (p
))) == USE
;
8178 if (rtx_equal_p (piece
,
8179 XEXP (PATTERN (PREV_INSN (p
)), 0)))
8188 = emit_insn_before (gen_rtx (USE
, VOIDmode
,
8191 REG_NOTES (use_insn
)
8192 = gen_rtx (EXPR_LIST
, REG_DEAD
, piece
,
8193 REG_NOTES (use_insn
));
8201 /* Put only REG_DEAD notes for pieces that are
8202 still used and that are not already dead or set. */
8204 for (i
= regno
; i
< endregno
; i
++)
8206 rtx piece
= gen_rtx (REG
, word_mode
, i
);
8208 if (reg_referenced_p (piece
, PATTERN (place
))
8209 && ! dead_or_set_p (place
, piece
)
8210 && ! reg_bitfield_target_p (piece
,
8212 REG_NOTES (place
) = gen_rtx (EXPR_LIST
, REG_DEAD
,
8224 /* Any other notes should not be present at this point in the
8231 XEXP (note
, 1) = REG_NOTES (place
);
8232 REG_NOTES (place
) = note
;
8236 REG_NOTES (place2
) = gen_rtx (GET_CODE (note
), REG_NOTE_KIND (note
),
8237 XEXP (note
, 0), REG_NOTES (place2
));
8241 /* Similarly to above, distribute the LOG_LINKS that used to be present on
8242 I3, I2, and I1 to new locations. This is also called in one case to
8243 add a link pointing at I3 when I3's destination is changed. */
8246 distribute_links (links
)
8249 rtx link
, next_link
;
8251 for (link
= links
; link
; link
= next_link
)
8257 next_link
= XEXP (link
, 1);
8259 /* If the insn that this link points to is a NOTE or isn't a single
8260 set, ignore it. In the latter case, it isn't clear what we
8261 can do other than ignore the link, since we can't tell which
8262 register it was for. Such links wouldn't be used by combine
8265 It is not possible for the destination of the target of the link to
8266 have been changed by combine. The only potential of this is if we
8267 replace I3, I2, and I1 by I3 and I2. But in that case the
8268 destination of I2 also remains unchanged. */
8270 if (GET_CODE (XEXP (link
, 0)) == NOTE
8271 || (set
= single_set (XEXP (link
, 0))) == 0)
8274 reg
= SET_DEST (set
);
8275 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
8276 || GET_CODE (reg
) == SIGN_EXTRACT
8277 || GET_CODE (reg
) == STRICT_LOW_PART
)
8278 reg
= XEXP (reg
, 0);
8280 /* A LOG_LINK is defined as being placed on the first insn that uses
8281 a register and points to the insn that sets the register. Start
8282 searching at the next insn after the target of the link and stop
8283 when we reach a set of the register or the end of the basic block.
8285 Note that this correctly handles the link that used to point from
8286 I3 to I2. Also note that not much searching is typically done here
8287 since most links don't point very far away. */
8289 for (insn
= NEXT_INSN (XEXP (link
, 0));
8290 (insn
&& GET_CODE (insn
) != CODE_LABEL
8291 && GET_CODE (PREV_INSN (insn
)) != JUMP_INSN
);
8292 insn
= NEXT_INSN (insn
))
8293 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
8294 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
8296 if (reg_referenced_p (reg
, PATTERN (insn
)))
8301 /* If we found a place to put the link, place it there unless there
8302 is already a link to the same insn as LINK at that point. */
8308 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
8309 if (XEXP (link2
, 0) == XEXP (link
, 0))
8314 XEXP (link
, 1) = LOG_LINKS (place
);
8315 LOG_LINKS (place
) = link
;
8322 dump_combine_stats (file
)
8327 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
8328 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
8332 dump_combine_total_stats (file
)
8337 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
8338 total_attempts
, total_merges
, total_extras
, total_successes
);