1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 #include "insn-codes.h"
95 #include "rtlhooks-def.h"
96 /* Include output.h for dump_file. */
100 #include "tree-pass.h"
102 /* Number of attempts to combine instructions in this function. */
104 static int combine_attempts
;
106 /* Number of attempts that got as far as substitution in this function. */
108 static int combine_merges
;
110 /* Number of instructions combined with added SETs in this function. */
112 static int combine_extras
;
114 /* Number of instructions combined in this function. */
116 static int combine_successes
;
118 /* Totals over entire compilation. */
120 static int total_attempts
, total_merges
, total_extras
, total_successes
;
123 /* Vector mapping INSN_UIDs to cuids.
124 The cuids are like uids but increase monotonically always.
125 Combine always uses cuids so that it can compare them.
126 But actually renumbering the uids, which we used to do,
127 proves to be a bad idea because it makes it hard to compare
128 the dumps produced by earlier passes with those from later passes. */
130 static int *uid_cuid
;
131 static int max_uid_cuid
;
133 /* Get the cuid of an insn. */
135 #define INSN_CUID(INSN) \
136 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
138 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
139 BITS_PER_WORD would invoke undefined behavior. Work around it. */
141 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
142 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
144 /* Maximum register number, which is the size of the tables below. */
146 static unsigned int combine_max_regno
;
149 /* Record last point of death of (hard or pseudo) register n. */
152 /* Record last point of modification of (hard or pseudo) register n. */
155 /* The next group of fields allows the recording of the last value assigned
156 to (hard or pseudo) register n. We use this information to see if an
157 operation being processed is redundant given a prior operation performed
158 on the register. For example, an `and' with a constant is redundant if
159 all the zero bits are already known to be turned off.
161 We use an approach similar to that used by cse, but change it in the
164 (1) We do not want to reinitialize at each label.
165 (2) It is useful, but not critical, to know the actual value assigned
166 to a register. Often just its form is helpful.
168 Therefore, we maintain the following fields:
170 last_set_value the last value assigned
171 last_set_label records the value of label_tick when the
172 register was assigned
173 last_set_table_tick records the value of label_tick when a
174 value using the register is assigned
175 last_set_invalid set to nonzero when it is not valid
176 to use the value of this register in some
179 To understand the usage of these tables, it is important to understand
180 the distinction between the value in last_set_value being valid and
181 the register being validly contained in some other expression in the
184 (The next two parameters are out of date).
186 reg_stat[i].last_set_value is valid if it is nonzero, and either
187 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
189 Register I may validly appear in any expression returned for the value
190 of another register if reg_n_sets[i] is 1. It may also appear in the
191 value for register J if reg_stat[j].last_set_invalid is zero, or
192 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
194 If an expression is found in the table containing a register which may
195 not validly appear in an expression, the register is replaced by
196 something that won't match, (clobber (const_int 0)). */
198 /* Record last value assigned to (hard or pseudo) register n. */
202 /* Record the value of label_tick when an expression involving register n
203 is placed in last_set_value. */
205 int last_set_table_tick
;
207 /* Record the value of label_tick when the value for register n is placed in
212 /* These fields are maintained in parallel with last_set_value and are
213 used to store the mode in which the register was last set, the bits
214 that were known to be zero when it was last set, and the number of
215 sign bits copies it was known to have when it was last set. */
217 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
218 char last_set_sign_bit_copies
;
219 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
221 /* Set nonzero if references to register n in expressions should not be
222 used. last_set_invalid is set nonzero when this register is being
223 assigned to and last_set_table_tick == label_tick. */
225 char last_set_invalid
;
227 /* Some registers that are set more than once and used in more than one
228 basic block are nevertheless always set in similar ways. For example,
229 a QImode register may be loaded from memory in two places on a machine
230 where byte loads zero extend.
232 We record in the following fields if a register has some leading bits
233 that are always equal to the sign bit, and what we know about the
234 nonzero bits of a register, specifically which bits are known to be
237 If an entry is zero, it means that we don't know anything special. */
239 unsigned char sign_bit_copies
;
241 unsigned HOST_WIDE_INT nonzero_bits
;
244 static struct reg_stat
*reg_stat
;
246 /* Record the cuid of the last insn that invalidated memory
247 (anything that writes memory, and subroutine calls, but not pushes). */
249 static int mem_last_set
;
251 /* Record the cuid of the last CALL_INSN
252 so we can tell whether a potential combination crosses any calls. */
254 static int last_call_cuid
;
256 /* When `subst' is called, this is the insn that is being modified
257 (by combining in a previous insn). The PATTERN of this insn
258 is still the old pattern partially modified and it should not be
259 looked at, but this may be used to examine the successors of the insn
260 to judge whether a simplification is valid. */
262 static rtx subst_insn
;
264 /* This is the lowest CUID that `subst' is currently dealing with.
265 get_last_value will not return a value if the register was set at or
266 after this CUID. If not for this mechanism, we could get confused if
267 I2 or I1 in try_combine were an insn that used the old value of a register
268 to obtain a new value. In that case, we might erroneously get the
269 new value of the register when we wanted the old one. */
271 static int subst_low_cuid
;
273 /* This contains any hard registers that are used in newpat; reg_dead_at_p
274 must consider all these registers to be always live. */
276 static HARD_REG_SET newpat_used_regs
;
278 /* This is an insn to which a LOG_LINKS entry has been added. If this
279 insn is the earlier than I2 or I3, combine should rescan starting at
282 static rtx added_links_insn
;
284 /* Basic block in which we are performing combines. */
285 static basic_block this_basic_block
;
287 /* A bitmap indicating which blocks had registers go dead at entry.
288 After combine, we'll need to re-do global life analysis with
289 those blocks as starting points. */
290 static sbitmap refresh_blocks
;
292 /* The following array records the insn_rtx_cost for every insn
293 in the instruction stream. */
295 static int *uid_insn_cost
;
297 /* Length of the currently allocated uid_insn_cost array. */
299 static int last_insn_cost
;
301 /* Incremented for each label. */
303 static int label_tick
;
305 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
306 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
308 static enum machine_mode nonzero_bits_mode
;
310 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
311 be safely used. It is zero while computing them and after combine has
312 completed. This former test prevents propagating values based on
313 previously set values, which can be incorrect if a variable is modified
316 static int nonzero_sign_valid
;
319 /* Record one modification to rtl structure
320 to be undone by storing old_contents into *where.
321 is_int is 1 if the contents are an int. */
327 union {rtx r
; int i
;} old_contents
;
328 union {rtx
*r
; int *i
;} where
;
331 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
332 num_undo says how many are currently recorded.
334 other_insn is nonzero if we have modified some other insn in the process
335 of working on subst_insn. It must be verified too. */
344 static struct undobuf undobuf
;
346 /* Number of times the pseudo being substituted for
347 was found and replaced. */
349 static int n_occurrences
;
351 static rtx
reg_nonzero_bits_for_combine (rtx
, enum machine_mode
, rtx
,
353 unsigned HOST_WIDE_INT
,
354 unsigned HOST_WIDE_INT
*);
355 static rtx
reg_num_sign_bit_copies_for_combine (rtx
, enum machine_mode
, rtx
,
357 unsigned int, unsigned int *);
358 static void do_SUBST (rtx
*, rtx
);
359 static void do_SUBST_INT (int *, int);
360 static void init_reg_last (void);
361 static void setup_incoming_promotions (void);
362 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
363 static int cant_combine_insn_p (rtx
);
364 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
365 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
366 static int contains_muldiv (rtx
);
367 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
368 static void undo_all (void);
369 static void undo_commit (void);
370 static rtx
*find_split_point (rtx
*, rtx
);
371 static rtx
subst (rtx
, rtx
, rtx
, int, int);
372 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
373 static rtx
simplify_if_then_else (rtx
);
374 static rtx
simplify_set (rtx
);
375 static rtx
simplify_logical (rtx
);
376 static rtx
expand_compound_operation (rtx
);
377 static rtx
expand_field_assignment (rtx
);
378 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
379 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
380 static rtx
extract_left_shift (rtx
, int);
381 static rtx
make_compound_operation (rtx
, enum rtx_code
);
382 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
383 unsigned HOST_WIDE_INT
*);
384 static rtx
force_to_mode (rtx
, enum machine_mode
,
385 unsigned HOST_WIDE_INT
, rtx
, int);
386 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
387 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
388 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
389 static rtx
make_field_assignment (rtx
);
390 static rtx
apply_distributive_law (rtx
);
391 static rtx
distribute_and_simplify_rtx (rtx
, int);
392 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
393 unsigned HOST_WIDE_INT
);
394 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
395 HOST_WIDE_INT
, enum machine_mode
, int *);
396 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
398 static int recog_for_combine (rtx
*, rtx
, rtx
*);
399 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
400 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
401 static void update_table_tick (rtx
);
402 static void record_value_for_reg (rtx
, rtx
, rtx
);
403 static void check_promoted_subreg (rtx
, rtx
);
404 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
405 static void record_dead_and_set_regs (rtx
);
406 static int get_last_value_validate (rtx
*, rtx
, int, int);
407 static rtx
get_last_value (rtx
);
408 static int use_crosses_set_p (rtx
, int);
409 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
410 static int reg_dead_at_p (rtx
, rtx
);
411 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
412 static int reg_bitfield_target_p (rtx
, rtx
);
413 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
414 static void distribute_links (rtx
);
415 static void mark_used_regs_combine (rtx
);
416 static int insn_cuid (rtx
);
417 static void record_promoted_value (rtx
, rtx
);
418 static int unmentioned_reg_p_1 (rtx
*, void *);
419 static bool unmentioned_reg_p (rtx
, rtx
);
422 /* It is not safe to use ordinary gen_lowpart in combine.
423 See comments in gen_lowpart_for_combine. */
424 #undef RTL_HOOKS_GEN_LOWPART
425 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
427 /* Our implementation of gen_lowpart never emits a new pseudo. */
428 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
429 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
431 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
432 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
434 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
435 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
437 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
440 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
441 insn. The substitution can be undone by undo_all. If INTO is already
442 set to NEWVAL, do not record this change. Because computing NEWVAL might
443 also call SUBST, we have to compute it before we put anything into
447 do_SUBST (rtx
*into
, rtx newval
)
452 if (oldval
== newval
)
455 /* We'd like to catch as many invalid transformations here as
456 possible. Unfortunately, there are way too many mode changes
457 that are perfectly valid, so we'd waste too much effort for
458 little gain doing the checks here. Focus on catching invalid
459 transformations involving integer constants. */
460 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
461 && GET_CODE (newval
) == CONST_INT
)
463 /* Sanity check that we're replacing oldval with a CONST_INT
464 that is a valid sign-extension for the original mode. */
465 gcc_assert (INTVAL (newval
)
466 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
468 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
469 CONST_INT is not valid, because after the replacement, the
470 original mode would be gone. Unfortunately, we can't tell
471 when do_SUBST is called to replace the operand thereof, so we
472 perform this test on oldval instead, checking whether an
473 invalid replacement took place before we got here. */
474 gcc_assert (!(GET_CODE (oldval
) == SUBREG
475 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
));
476 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
477 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
));
481 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
483 buf
= xmalloc (sizeof (struct undo
));
487 buf
->old_contents
.r
= oldval
;
490 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
493 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
495 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
496 for the value of a HOST_WIDE_INT value (including CONST_INT) is
500 do_SUBST_INT (int *into
, int newval
)
505 if (oldval
== newval
)
509 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
511 buf
= xmalloc (sizeof (struct undo
));
515 buf
->old_contents
.i
= oldval
;
518 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
521 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
523 /* Subroutine of try_combine. Determine whether the combine replacement
524 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
525 that the original instruction sequence I1, I2 and I3. Note that I1
526 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
527 costs of all instructions can be estimated, and the replacements are
528 more expensive than the original sequence. */
531 combine_validate_cost (rtx i1
, rtx i2
, rtx i3
, rtx newpat
, rtx newi2pat
)
533 int i1_cost
, i2_cost
, i3_cost
;
534 int new_i2_cost
, new_i3_cost
;
535 int old_cost
, new_cost
;
537 /* Lookup the original insn_rtx_costs. */
538 i2_cost
= INSN_UID (i2
) <= last_insn_cost
539 ? uid_insn_cost
[INSN_UID (i2
)] : 0;
540 i3_cost
= INSN_UID (i3
) <= last_insn_cost
541 ? uid_insn_cost
[INSN_UID (i3
)] : 0;
545 i1_cost
= INSN_UID (i1
) <= last_insn_cost
546 ? uid_insn_cost
[INSN_UID (i1
)] : 0;
547 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0)
548 ? i1_cost
+ i2_cost
+ i3_cost
: 0;
552 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
556 /* Calculate the replacement insn_rtx_costs. */
557 new_i3_cost
= insn_rtx_cost (newpat
);
560 new_i2_cost
= insn_rtx_cost (newi2pat
);
561 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
562 ? new_i2_cost
+ new_i3_cost
: 0;
566 new_cost
= new_i3_cost
;
570 if (undobuf
.other_insn
)
572 int old_other_cost
, new_other_cost
;
574 old_other_cost
= (INSN_UID (undobuf
.other_insn
) <= last_insn_cost
575 ? uid_insn_cost
[INSN_UID (undobuf
.other_insn
)] : 0);
576 new_other_cost
= insn_rtx_cost (PATTERN (undobuf
.other_insn
));
577 if (old_other_cost
> 0 && new_other_cost
> 0)
579 old_cost
+= old_other_cost
;
580 new_cost
+= new_other_cost
;
586 /* Disallow this recombination if both new_cost and old_cost are
587 greater than zero, and new_cost is greater than old cost. */
589 && new_cost
> old_cost
)
596 "rejecting combination of insns %d, %d and %d\n",
597 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
598 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
599 i1_cost
, i2_cost
, i3_cost
, old_cost
);
604 "rejecting combination of insns %d and %d\n",
605 INSN_UID (i2
), INSN_UID (i3
));
606 fprintf (dump_file
, "original costs %d + %d = %d\n",
607 i2_cost
, i3_cost
, old_cost
);
612 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
613 new_i2_cost
, new_i3_cost
, new_cost
);
616 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
622 /* Update the uid_insn_cost array with the replacement costs. */
623 uid_insn_cost
[INSN_UID (i2
)] = new_i2_cost
;
624 uid_insn_cost
[INSN_UID (i3
)] = new_i3_cost
;
626 uid_insn_cost
[INSN_UID (i1
)] = 0;
631 /* Main entry point for combiner. F is the first insn of the function.
632 NREGS is the first unused pseudo-reg number.
634 Return nonzero if the combiner has turned an indirect jump
635 instruction into a direct jump. */
637 combine_instructions (rtx f
, unsigned int nregs
)
645 rtx links
, nextlinks
;
646 sbitmap_iterator sbi
;
648 int new_direct_jump_p
= 0;
650 combine_attempts
= 0;
653 combine_successes
= 0;
655 combine_max_regno
= nregs
;
657 rtl_hooks
= combine_rtl_hooks
;
659 reg_stat
= xcalloc (nregs
, sizeof (struct reg_stat
));
661 init_recog_no_volatile ();
663 /* Compute maximum uid value so uid_cuid can be allocated. */
665 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
666 if (INSN_UID (insn
) > i
)
669 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
672 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
674 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
675 problems when, for example, we have j <<= 1 in a loop. */
677 nonzero_sign_valid
= 0;
679 /* Compute the mapping from uids to cuids.
680 Cuids are numbers assigned to insns, like uids,
681 except that cuids increase monotonically through the code.
683 Scan all SETs and see if we can deduce anything about what
684 bits are known to be zero for some registers and how many copies
685 of the sign bit are known to exist for those registers.
687 Also set any known values so that we can use it while searching
688 for what bits are known to be set. */
692 setup_incoming_promotions ();
694 refresh_blocks
= sbitmap_alloc (last_basic_block
);
695 sbitmap_zero (refresh_blocks
);
697 /* Allocate array of current insn_rtx_costs. */
698 uid_insn_cost
= xcalloc (max_uid_cuid
+ 1, sizeof (int));
699 last_insn_cost
= max_uid_cuid
;
701 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
703 uid_cuid
[INSN_UID (insn
)] = ++i
;
709 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
711 record_dead_and_set_regs (insn
);
714 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
715 if (REG_NOTE_KIND (links
) == REG_INC
)
716 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
720 /* Record the current insn_rtx_cost of this instruction. */
721 if (NONJUMP_INSN_P (insn
))
722 uid_insn_cost
[INSN_UID (insn
)] = insn_rtx_cost (PATTERN (insn
));
724 fprintf(dump_file
, "insn_cost %d: %d\n",
725 INSN_UID (insn
), uid_insn_cost
[INSN_UID (insn
)]);
732 nonzero_sign_valid
= 1;
734 /* Now scan all the insns in forward order. */
740 setup_incoming_promotions ();
742 FOR_EACH_BB (this_basic_block
)
744 for (insn
= BB_HEAD (this_basic_block
);
745 insn
!= NEXT_INSN (BB_END (this_basic_block
));
746 insn
= next
? next
: NEXT_INSN (insn
))
753 else if (INSN_P (insn
))
755 /* See if we know about function return values before this
756 insn based upon SUBREG flags. */
757 check_promoted_subreg (insn
, PATTERN (insn
));
759 /* Try this insn with each insn it links back to. */
761 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
762 if ((next
= try_combine (insn
, XEXP (links
, 0),
763 NULL_RTX
, &new_direct_jump_p
)) != 0)
766 /* Try each sequence of three linked insns ending with this one. */
768 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
770 rtx link
= XEXP (links
, 0);
772 /* If the linked insn has been replaced by a note, then there
773 is no point in pursuing this chain any further. */
777 for (nextlinks
= LOG_LINKS (link
);
779 nextlinks
= XEXP (nextlinks
, 1))
780 if ((next
= try_combine (insn
, link
,
782 &new_direct_jump_p
)) != 0)
787 /* Try to combine a jump insn that uses CC0
788 with a preceding insn that sets CC0, and maybe with its
789 logical predecessor as well.
790 This is how we make decrement-and-branch insns.
791 We need this special code because data flow connections
792 via CC0 do not get entered in LOG_LINKS. */
795 && (prev
= prev_nonnote_insn (insn
)) != 0
796 && NONJUMP_INSN_P (prev
)
797 && sets_cc0_p (PATTERN (prev
)))
799 if ((next
= try_combine (insn
, prev
,
800 NULL_RTX
, &new_direct_jump_p
)) != 0)
803 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
804 nextlinks
= XEXP (nextlinks
, 1))
805 if ((next
= try_combine (insn
, prev
,
807 &new_direct_jump_p
)) != 0)
811 /* Do the same for an insn that explicitly references CC0. */
812 if (NONJUMP_INSN_P (insn
)
813 && (prev
= prev_nonnote_insn (insn
)) != 0
814 && NONJUMP_INSN_P (prev
)
815 && sets_cc0_p (PATTERN (prev
))
816 && GET_CODE (PATTERN (insn
)) == SET
817 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
819 if ((next
= try_combine (insn
, prev
,
820 NULL_RTX
, &new_direct_jump_p
)) != 0)
823 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
824 nextlinks
= XEXP (nextlinks
, 1))
825 if ((next
= try_combine (insn
, prev
,
827 &new_direct_jump_p
)) != 0)
831 /* Finally, see if any of the insns that this insn links to
832 explicitly references CC0. If so, try this insn, that insn,
833 and its predecessor if it sets CC0. */
834 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
835 if (NONJUMP_INSN_P (XEXP (links
, 0))
836 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
837 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
838 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
839 && NONJUMP_INSN_P (prev
)
840 && sets_cc0_p (PATTERN (prev
))
841 && (next
= try_combine (insn
, XEXP (links
, 0),
842 prev
, &new_direct_jump_p
)) != 0)
846 /* Try combining an insn with two different insns whose results it
848 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
849 for (nextlinks
= XEXP (links
, 1); nextlinks
;
850 nextlinks
= XEXP (nextlinks
, 1))
851 if ((next
= try_combine (insn
, XEXP (links
, 0),
853 &new_direct_jump_p
)) != 0)
856 /* Try this insn with each REG_EQUAL note it links back to. */
857 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
860 rtx temp
= XEXP (links
, 0);
861 if ((set
= single_set (temp
)) != 0
862 && (note
= find_reg_equal_equiv_note (temp
)) != 0
863 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
864 /* Avoid using a register that may already been marked
865 dead by an earlier instruction. */
866 && ! unmentioned_reg_p (note
, SET_SRC (set
))
867 && (GET_MODE (note
) == VOIDmode
868 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
869 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
871 /* Temporarily replace the set's source with the
872 contents of the REG_EQUAL note. The insn will
873 be deleted or recognized by try_combine. */
874 rtx orig
= SET_SRC (set
);
875 SET_SRC (set
) = note
;
876 next
= try_combine (insn
, temp
, NULL_RTX
,
880 SET_SRC (set
) = orig
;
885 record_dead_and_set_regs (insn
);
894 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, j
, sbi
)
895 BASIC_BLOCK (j
)->flags
|= BB_DIRTY
;
896 new_direct_jump_p
|= purge_all_dead_edges ();
897 delete_noop_moves ();
899 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
900 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
901 | PROP_KILL_DEAD_CODE
);
904 sbitmap_free (refresh_blocks
);
905 free (uid_insn_cost
);
910 struct undo
*undo
, *next
;
911 for (undo
= undobuf
.frees
; undo
; undo
= next
)
919 total_attempts
+= combine_attempts
;
920 total_merges
+= combine_merges
;
921 total_extras
+= combine_extras
;
922 total_successes
+= combine_successes
;
924 nonzero_sign_valid
= 0;
925 rtl_hooks
= general_rtl_hooks
;
927 /* Make recognizer allow volatile MEMs again. */
930 return new_direct_jump_p
;
933 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
939 for (i
= 0; i
< combine_max_regno
; i
++)
940 memset (reg_stat
+ i
, 0, offsetof (struct reg_stat
, sign_bit_copies
));
943 /* Set up any promoted values for incoming argument registers. */
946 setup_incoming_promotions (void)
950 enum machine_mode mode
;
952 rtx first
= get_insns ();
954 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
956 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
957 /* Check whether this register can hold an incoming pointer
958 argument. FUNCTION_ARG_REGNO_P tests outgoing register
959 numbers, so translate if necessary due to register windows. */
960 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
961 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
964 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
967 gen_rtx_CLOBBER (mode
, const0_rtx
)));
972 /* Called via note_stores. If X is a pseudo that is narrower than
973 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
975 If we are setting only a portion of X and we can't figure out what
976 portion, assume all bits will be used since we don't know what will
979 Similarly, set how many bits of X are known to be copies of the sign bit
980 at all locations in the function. This is the smallest number implied
984 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
985 void *data ATTRIBUTE_UNUSED
)
990 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
991 /* If this register is undefined at the start of the file, we can't
992 say what its contents were. */
994 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
, REGNO (x
))
995 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
997 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
999 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1000 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
1004 /* If this is a complex assignment, see if we can convert it into a
1005 simple assignment. */
1006 set
= expand_field_assignment (set
);
1008 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1009 set what we know about X. */
1011 if (SET_DEST (set
) == x
1012 || (GET_CODE (SET_DEST (set
)) == SUBREG
1013 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1014 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
1015 && SUBREG_REG (SET_DEST (set
)) == x
))
1017 rtx src
= SET_SRC (set
);
1019 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1020 /* If X is narrower than a word and SRC is a non-negative
1021 constant that would appear negative in the mode of X,
1022 sign-extend it for use in reg_stat[].nonzero_bits because some
1023 machines (maybe most) will actually do the sign-extension
1024 and this is the conservative approach.
1026 ??? For 2.5, try to tighten up the MD files in this regard
1027 instead of this kludge. */
1029 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
1030 && GET_CODE (src
) == CONST_INT
1032 && 0 != (INTVAL (src
)
1033 & ((HOST_WIDE_INT
) 1
1034 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
1035 src
= GEN_INT (INTVAL (src
)
1036 | ((HOST_WIDE_INT
) (-1)
1037 << GET_MODE_BITSIZE (GET_MODE (x
))));
1040 /* Don't call nonzero_bits if it cannot change anything. */
1041 if (reg_stat
[REGNO (x
)].nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1042 reg_stat
[REGNO (x
)].nonzero_bits
1043 |= nonzero_bits (src
, nonzero_bits_mode
);
1044 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1045 if (reg_stat
[REGNO (x
)].sign_bit_copies
== 0
1046 || reg_stat
[REGNO (x
)].sign_bit_copies
> num
)
1047 reg_stat
[REGNO (x
)].sign_bit_copies
= num
;
1051 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1052 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
1057 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1058 insns that were previously combined into I3 or that will be combined
1059 into the merger of INSN and I3.
1061 Return 0 if the combination is not allowed for any reason.
1063 If the combination is allowed, *PDEST will be set to the single
1064 destination of INSN and *PSRC to the single source, and this function
1068 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
1069 rtx
*pdest
, rtx
*psrc
)
1072 rtx set
= 0, src
, dest
;
1077 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
1078 && next_active_insn (succ
) == i3
)
1079 : next_active_insn (insn
) == i3
);
1081 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1082 or a PARALLEL consisting of such a SET and CLOBBERs.
1084 If INSN has CLOBBER parallel parts, ignore them for our processing.
1085 By definition, these happen during the execution of the insn. When it
1086 is merged with another insn, all bets are off. If they are, in fact,
1087 needed and aren't also supplied in I3, they may be added by
1088 recog_for_combine. Otherwise, it won't match.
1090 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1093 Get the source and destination of INSN. If more than one, can't
1096 if (GET_CODE (PATTERN (insn
)) == SET
)
1097 set
= PATTERN (insn
);
1098 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1099 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1101 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1103 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1106 switch (GET_CODE (elt
))
1108 /* This is important to combine floating point insns
1109 for the SH4 port. */
1111 /* Combining an isolated USE doesn't make sense.
1112 We depend here on combinable_i3pat to reject them. */
1113 /* The code below this loop only verifies that the inputs of
1114 the SET in INSN do not change. We call reg_set_between_p
1115 to verify that the REG in the USE does not change between
1117 If the USE in INSN was for a pseudo register, the matching
1118 insn pattern will likely match any register; combining this
1119 with any other USE would only be safe if we knew that the
1120 used registers have identical values, or if there was
1121 something to tell them apart, e.g. different modes. For
1122 now, we forgo such complicated tests and simply disallow
1123 combining of USES of pseudo registers with any other USE. */
1124 if (REG_P (XEXP (elt
, 0))
1125 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1127 rtx i3pat
= PATTERN (i3
);
1128 int i
= XVECLEN (i3pat
, 0) - 1;
1129 unsigned int regno
= REGNO (XEXP (elt
, 0));
1133 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1135 if (GET_CODE (i3elt
) == USE
1136 && REG_P (XEXP (i3elt
, 0))
1137 && (REGNO (XEXP (i3elt
, 0)) == regno
1138 ? reg_set_between_p (XEXP (elt
, 0),
1139 PREV_INSN (insn
), i3
)
1140 : regno
>= FIRST_PSEUDO_REGISTER
))
1147 /* We can ignore CLOBBERs. */
1152 /* Ignore SETs whose result isn't used but not those that
1153 have side-effects. */
1154 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1155 && (!(note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
1156 || INTVAL (XEXP (note
, 0)) <= 0)
1157 && ! side_effects_p (elt
))
1160 /* If we have already found a SET, this is a second one and
1161 so we cannot combine with this insn. */
1169 /* Anything else means we can't combine. */
1175 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1176 so don't do anything with it. */
1177 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1186 set
= expand_field_assignment (set
);
1187 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1189 /* Don't eliminate a store in the stack pointer. */
1190 if (dest
== stack_pointer_rtx
1191 /* Don't combine with an insn that sets a register to itself if it has
1192 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1193 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1194 /* Can't merge an ASM_OPERANDS. */
1195 || GET_CODE (src
) == ASM_OPERANDS
1196 /* Can't merge a function call. */
1197 || GET_CODE (src
) == CALL
1198 /* Don't eliminate a function call argument. */
1200 && (find_reg_fusage (i3
, USE
, dest
)
1202 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1203 && global_regs
[REGNO (dest
)])))
1204 /* Don't substitute into an incremented register. */
1205 || FIND_REG_INC_NOTE (i3
, dest
)
1206 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1207 /* Don't substitute into a non-local goto, this confuses CFG. */
1208 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1210 /* Don't combine the end of a libcall into anything. */
1211 /* ??? This gives worse code, and appears to be unnecessary, since no
1212 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1213 use REG_RETVAL notes for noconflict blocks, but other code here
1214 makes sure that those insns don't disappear. */
1215 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1217 /* Make sure that DEST is not used after SUCC but before I3. */
1218 || (succ
&& ! all_adjacent
1219 && reg_used_between_p (dest
, succ
, i3
))
1220 /* Make sure that the value that is to be substituted for the register
1221 does not use any registers whose values alter in between. However,
1222 If the insns are adjacent, a use can't cross a set even though we
1223 think it might (this can happen for a sequence of insns each setting
1224 the same destination; last_set of that register might point to
1225 a NOTE). If INSN has a REG_EQUIV note, the register is always
1226 equivalent to the memory so the substitution is valid even if there
1227 are intervening stores. Also, don't move a volatile asm or
1228 UNSPEC_VOLATILE across any other insns. */
1231 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1232 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1233 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1234 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1235 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1236 better register allocation by not doing the combine. */
1237 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1238 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1239 /* Don't combine across a CALL_INSN, because that would possibly
1240 change whether the life span of some REGs crosses calls or not,
1241 and it is a pain to update that information.
1242 Exception: if source is a constant, moving it later can't hurt.
1243 Accept that special case, because it helps -fforce-addr a lot. */
1244 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1247 /* DEST must either be a REG or CC0. */
1250 /* If register alignment is being enforced for multi-word items in all
1251 cases except for parameters, it is possible to have a register copy
1252 insn referencing a hard register that is not allowed to contain the
1253 mode being copied and which would not be valid as an operand of most
1254 insns. Eliminate this problem by not combining with such an insn.
1256 Also, on some machines we don't want to extend the life of a hard
1260 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1261 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1262 /* Don't extend the life of a hard register unless it is
1263 user variable (if we have few registers) or it can't
1264 fit into the desired register (meaning something special
1266 Also avoid substituting a return register into I3, because
1267 reload can't handle a conflict with constraints of other
1269 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1270 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1273 else if (GET_CODE (dest
) != CC0
)
1277 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1278 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1279 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1281 /* Don't substitute for a register intended as a clobberable
1283 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1284 if (rtx_equal_p (reg
, dest
))
1287 /* If the clobber represents an earlyclobber operand, we must not
1288 substitute an expression containing the clobbered register.
1289 As we do not analyze the constraint strings here, we have to
1290 make the conservative assumption. However, if the register is
1291 a fixed hard reg, the clobber cannot represent any operand;
1292 we leave it up to the machine description to either accept or
1293 reject use-and-clobber patterns. */
1295 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1296 || !fixed_regs
[REGNO (reg
)])
1297 if (reg_overlap_mentioned_p (reg
, src
))
1301 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1302 or not), reject, unless nothing volatile comes between it and I3 */
1304 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1306 /* Make sure succ doesn't contain a volatile reference. */
1307 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1310 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1311 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1315 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1316 to be an explicit register variable, and was chosen for a reason. */
1318 if (GET_CODE (src
) == ASM_OPERANDS
1319 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1322 /* If there are any volatile insns between INSN and I3, reject, because
1323 they might affect machine state. */
1325 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1326 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1329 /* If INSN contains an autoincrement or autodecrement, make sure that
1330 register is not used between there and I3, and not already used in
1331 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1332 Also insist that I3 not be a jump; if it were one
1333 and the incremented register were spilled, we would lose. */
1336 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1337 if (REG_NOTE_KIND (link
) == REG_INC
1339 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1340 || (pred
!= NULL_RTX
1341 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1342 || (succ
!= NULL_RTX
1343 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1344 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1349 /* Don't combine an insn that follows a CC0-setting insn.
1350 An insn that uses CC0 must not be separated from the one that sets it.
1351 We do, however, allow I2 to follow a CC0-setting insn if that insn
1352 is passed as I1; in that case it will be deleted also.
1353 We also allow combining in this case if all the insns are adjacent
1354 because that would leave the two CC0 insns adjacent as well.
1355 It would be more logical to test whether CC0 occurs inside I1 or I2,
1356 but that would be much slower, and this ought to be equivalent. */
1358 p
= prev_nonnote_insn (insn
);
1359 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1364 /* If we get here, we have passed all the tests and the combination is
1373 /* LOC is the location within I3 that contains its pattern or the component
1374 of a PARALLEL of the pattern. We validate that it is valid for combining.
1376 One problem is if I3 modifies its output, as opposed to replacing it
1377 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1378 so would produce an insn that is not equivalent to the original insns.
1382 (set (reg:DI 101) (reg:DI 100))
1383 (set (subreg:SI (reg:DI 101) 0) <foo>)
1385 This is NOT equivalent to:
1387 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1388 (set (reg:DI 101) (reg:DI 100))])
1390 Not only does this modify 100 (in which case it might still be valid
1391 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1393 We can also run into a problem if I2 sets a register that I1
1394 uses and I1 gets directly substituted into I3 (not via I2). In that
1395 case, we would be getting the wrong value of I2DEST into I3, so we
1396 must reject the combination. This case occurs when I2 and I1 both
1397 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1398 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1399 of a SET must prevent combination from occurring.
1401 Before doing the above check, we first try to expand a field assignment
1402 into a set of logical operations.
1404 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1405 we place a register that is both set and used within I3. If more than one
1406 such register is detected, we fail.
1408 Return 1 if the combination is valid, zero otherwise. */
1411 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1412 int i1_not_in_src
, rtx
*pi3dest_killed
)
1416 if (GET_CODE (x
) == SET
)
1419 rtx dest
= SET_DEST (set
);
1420 rtx src
= SET_SRC (set
);
1421 rtx inner_dest
= dest
;
1423 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1424 || GET_CODE (inner_dest
) == SUBREG
1425 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1426 inner_dest
= XEXP (inner_dest
, 0);
1428 /* Check for the case where I3 modifies its output, as discussed
1429 above. We don't want to prevent pseudos from being combined
1430 into the address of a MEM, so only prevent the combination if
1431 i1 or i2 set the same MEM. */
1432 if ((inner_dest
!= dest
&&
1433 (!MEM_P (inner_dest
)
1434 || rtx_equal_p (i2dest
, inner_dest
)
1435 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1436 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1437 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1439 /* This is the same test done in can_combine_p except we can't test
1440 all_adjacent; we don't have to, since this instruction will stay
1441 in place, thus we are not considering increasing the lifetime of
1444 Also, if this insn sets a function argument, combining it with
1445 something that might need a spill could clobber a previous
1446 function argument; the all_adjacent test in can_combine_p also
1447 checks this; here, we do a more specific test for this case. */
1449 || (REG_P (inner_dest
)
1450 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1451 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1452 GET_MODE (inner_dest
))))
1453 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1456 /* If DEST is used in I3, it is being killed in this insn,
1457 so record that for later.
1458 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1459 STACK_POINTER_REGNUM, since these are always considered to be
1460 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1461 if (pi3dest_killed
&& REG_P (dest
)
1462 && reg_referenced_p (dest
, PATTERN (i3
))
1463 && REGNO (dest
) != FRAME_POINTER_REGNUM
1464 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1465 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1467 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1468 && (REGNO (dest
) != ARG_POINTER_REGNUM
1469 || ! fixed_regs
[REGNO (dest
)])
1471 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1473 if (*pi3dest_killed
)
1476 *pi3dest_killed
= dest
;
1480 else if (GET_CODE (x
) == PARALLEL
)
1484 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1485 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1486 i1_not_in_src
, pi3dest_killed
))
1493 /* Return 1 if X is an arithmetic expression that contains a multiplication
1494 and division. We don't count multiplications by powers of two here. */
1497 contains_muldiv (rtx x
)
1499 switch (GET_CODE (x
))
1501 case MOD
: case DIV
: case UMOD
: case UDIV
:
1505 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1506 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1509 return contains_muldiv (XEXP (x
, 0))
1510 || contains_muldiv (XEXP (x
, 1));
1513 return contains_muldiv (XEXP (x
, 0));
1519 /* Determine whether INSN can be used in a combination. Return nonzero if
1520 not. This is used in try_combine to detect early some cases where we
1521 can't perform combinations. */
1524 cant_combine_insn_p (rtx insn
)
1529 /* If this isn't really an insn, we can't do anything.
1530 This can occur when flow deletes an insn that it has merged into an
1531 auto-increment address. */
1532 if (! INSN_P (insn
))
1535 /* Never combine loads and stores involving hard regs that are likely
1536 to be spilled. The register allocator can usually handle such
1537 reg-reg moves by tying. If we allow the combiner to make
1538 substitutions of likely-spilled regs, reload might die.
1539 As an exception, we allow combinations involving fixed regs; these are
1540 not available to the register allocator so there's no risk involved. */
1542 set
= single_set (insn
);
1545 src
= SET_SRC (set
);
1546 dest
= SET_DEST (set
);
1547 if (GET_CODE (src
) == SUBREG
)
1548 src
= SUBREG_REG (src
);
1549 if (GET_CODE (dest
) == SUBREG
)
1550 dest
= SUBREG_REG (dest
);
1551 if (REG_P (src
) && REG_P (dest
)
1552 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1553 && ! fixed_regs
[REGNO (src
)]
1554 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1555 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1556 && ! fixed_regs
[REGNO (dest
)]
1557 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1563 struct likely_spilled_retval_info
1565 unsigned regno
, nregs
;
1569 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
1570 hard registers that are known to be written to / clobbered in full. */
1572 likely_spilled_retval_1 (rtx x
, rtx set
, void *data
)
1574 struct likely_spilled_retval_info
*info
= data
;
1575 unsigned regno
, nregs
;
1578 if (!REG_P (XEXP (set
, 0)))
1581 if (regno
>= info
->regno
+ info
->nregs
)
1583 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
1584 if (regno
+ nregs
<= info
->regno
)
1586 new_mask
= (2U << (nregs
- 1)) - 1;
1587 if (regno
< info
->regno
)
1588 new_mask
>>= info
->regno
- regno
;
1590 new_mask
<<= regno
- info
->regno
;
1591 info
->mask
&= new_mask
;
1594 /* Return nonzero iff part of the return value is live during INSN, and
1595 it is likely spilled. This can happen when more than one insn is needed
1596 to copy the return value, e.g. when we consider to combine into the
1597 second copy insn for a complex value. */
1600 likely_spilled_retval_p (rtx insn
)
1602 rtx use
= BB_END (this_basic_block
);
1604 unsigned regno
, nregs
;
1605 /* We assume here that no machine mode needs more than
1606 32 hard registers when the value overlaps with a register
1607 for which FUNCTION_VALUE_REGNO_P is true. */
1609 struct likely_spilled_retval_info info
;
1611 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
1613 reg
= XEXP (PATTERN (use
), 0);
1614 if (!REG_P (reg
) || !FUNCTION_VALUE_REGNO_P (REGNO (reg
)))
1616 regno
= REGNO (reg
);
1617 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
1620 mask
= (2U << (nregs
- 1)) - 1;
1622 /* Disregard parts of the return value that are set later. */
1626 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
1627 note_stores (PATTERN (insn
), likely_spilled_retval_1
, &info
);
1630 /* Check if any of the (probably) live return value registers is
1635 if ((mask
& 1 << nregs
)
1636 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno
+ nregs
)))
1642 /* Adjust INSN after we made a change to its destination.
1644 Changing the destination can invalidate notes that say something about
1645 the results of the insn and a LOG_LINK pointing to the insn. */
1648 adjust_for_new_dest (rtx insn
)
1652 /* For notes, be conservative and simply remove them. */
1653 loc
= ®_NOTES (insn
);
1656 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1657 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1658 *loc
= XEXP (*loc
, 1);
1660 loc
= &XEXP (*loc
, 1);
1663 /* The new insn will have a destination that was previously the destination
1664 of an insn just above it. Call distribute_links to make a LOG_LINK from
1665 the next use of that destination. */
1666 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1669 /* Try to combine the insns I1 and I2 into I3.
1670 Here I1 and I2 appear earlier than I3.
1671 I1 can be zero; then we combine just I2 into I3.
1673 If we are combining three insns and the resulting insn is not recognized,
1674 try splitting it into two insns. If that happens, I2 and I3 are retained
1675 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1678 Return 0 if the combination does not work. Then nothing is changed.
1679 If we did the combination, return the insn at which combine should
1682 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1683 new direct jump instruction. */
1686 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1688 /* New patterns for I3 and I2, respectively. */
1689 rtx newpat
, newi2pat
= 0;
1690 rtvec newpat_vec_with_clobbers
= 0;
1691 int substed_i2
= 0, substed_i1
= 0;
1692 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1693 int added_sets_1
, added_sets_2
;
1694 /* Total number of SETs to put into I3. */
1696 /* Nonzero if I2's body now appears in I3. */
1698 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1699 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1700 /* Contains I3 if the destination of I3 is used in its source, which means
1701 that the old life of I3 is being killed. If that usage is placed into
1702 I2 and not in I3, a REG_DEAD note must be made. */
1703 rtx i3dest_killed
= 0;
1704 /* SET_DEST and SET_SRC of I2 and I1. */
1705 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1706 /* PATTERN (I2), or a copy of it in certain cases. */
1708 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1709 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1710 int i1_feeds_i3
= 0;
1711 /* Notes that must be added to REG_NOTES in I3 and I2. */
1712 rtx new_i3_notes
, new_i2_notes
;
1713 /* Notes that we substituted I3 into I2 instead of the normal case. */
1714 int i3_subst_into_i2
= 0;
1715 /* Notes that I1, I2 or I3 is a MULT operation. */
1724 /* Exit early if one of the insns involved can't be used for
1726 if (cant_combine_insn_p (i3
)
1727 || cant_combine_insn_p (i2
)
1728 || (i1
&& cant_combine_insn_p (i1
))
1729 || likely_spilled_retval_p (i3
)
1730 /* We also can't do anything if I3 has a
1731 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1734 /* ??? This gives worse code, and appears to be unnecessary, since no
1735 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1736 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1742 undobuf
.other_insn
= 0;
1744 /* Reset the hard register usage information. */
1745 CLEAR_HARD_REG_SET (newpat_used_regs
);
1747 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1748 code below, set I1 to be the earlier of the two insns. */
1749 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1750 temp
= i1
, i1
= i2
, i2
= temp
;
1752 added_links_insn
= 0;
1754 /* First check for one important special-case that the code below will
1755 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1756 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1757 we may be able to replace that destination with the destination of I3.
1758 This occurs in the common code where we compute both a quotient and
1759 remainder into a structure, in which case we want to do the computation
1760 directly into the structure to avoid register-register copies.
1762 Note that this case handles both multiple sets in I2 and also
1763 cases where I2 has a number of CLOBBER or PARALLELs.
1765 We make very conservative checks below and only try to handle the
1766 most common cases of this. For example, we only handle the case
1767 where I2 and I3 are adjacent to avoid making difficult register
1770 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
1771 && REG_P (SET_SRC (PATTERN (i3
)))
1772 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1773 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1774 && GET_CODE (PATTERN (i2
)) == PARALLEL
1775 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1776 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1777 below would need to check what is inside (and reg_overlap_mentioned_p
1778 doesn't support those codes anyway). Don't allow those destinations;
1779 the resulting insn isn't likely to be recognized anyway. */
1780 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1781 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1782 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1783 SET_DEST (PATTERN (i3
)))
1784 && next_real_insn (i2
) == i3
)
1786 rtx p2
= PATTERN (i2
);
1788 /* Make sure that the destination of I3,
1789 which we are going to substitute into one output of I2,
1790 is not used within another output of I2. We must avoid making this:
1791 (parallel [(set (mem (reg 69)) ...)
1792 (set (reg 69) ...)])
1793 which is not well-defined as to order of actions.
1794 (Besides, reload can't handle output reloads for this.)
1796 The problem can also happen if the dest of I3 is a memory ref,
1797 if another dest in I2 is an indirect memory ref. */
1798 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1799 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1800 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1801 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1802 SET_DEST (XVECEXP (p2
, 0, i
))))
1805 if (i
== XVECLEN (p2
, 0))
1806 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1807 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1808 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1809 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1814 subst_low_cuid
= INSN_CUID (i2
);
1816 added_sets_2
= added_sets_1
= 0;
1817 i2dest
= SET_SRC (PATTERN (i3
));
1819 /* Replace the dest in I2 with our dest and make the resulting
1820 insn the new pattern for I3. Then skip to where we
1821 validate the pattern. Everything was set up above. */
1822 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1823 SET_DEST (PATTERN (i3
)));
1826 i3_subst_into_i2
= 1;
1827 goto validate_replacement
;
1831 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1832 one of those words to another constant, merge them by making a new
1835 && (temp
= single_set (i2
)) != 0
1836 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1837 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1838 && REG_P (SET_DEST (temp
))
1839 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1840 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1841 && GET_CODE (PATTERN (i3
)) == SET
1842 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1843 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1844 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1845 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1846 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1848 HOST_WIDE_INT lo
, hi
;
1850 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1851 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1854 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1855 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1858 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1860 /* We don't handle the case of the target word being wider
1861 than a host wide int. */
1862 gcc_assert (HOST_BITS_PER_WIDE_INT
>= BITS_PER_WORD
);
1864 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1865 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1866 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1868 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1869 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1870 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1872 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1873 >> (HOST_BITS_PER_WIDE_INT
- 1));
1875 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1876 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1877 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1878 (INTVAL (SET_SRC (PATTERN (i3
)))));
1880 hi
= lo
< 0 ? -1 : 0;
1883 /* We don't handle the case of the higher word not fitting
1884 entirely in either hi or lo. */
1889 subst_low_cuid
= INSN_CUID (i2
);
1890 added_sets_2
= added_sets_1
= 0;
1891 i2dest
= SET_DEST (temp
);
1893 SUBST (SET_SRC (temp
),
1894 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1896 newpat
= PATTERN (i2
);
1897 goto validate_replacement
;
1901 /* If we have no I1 and I2 looks like:
1902 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1904 make up a dummy I1 that is
1907 (set (reg:CC X) (compare:CC Y (const_int 0)))
1909 (We can ignore any trailing CLOBBERs.)
1911 This undoes a previous combination and allows us to match a branch-and-
1914 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1915 && XVECLEN (PATTERN (i2
), 0) >= 2
1916 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1917 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1919 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1920 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1921 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1922 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
1923 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1924 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1926 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1927 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1932 /* We make I1 with the same INSN_UID as I2. This gives it
1933 the same INSN_CUID for value tracking. Our fake I1 will
1934 never appear in the insn stream so giving it the same INSN_UID
1935 as I2 will not cause a problem. */
1937 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1938 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1939 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1942 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1943 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1944 SET_DEST (PATTERN (i1
)));
1949 /* Verify that I2 and I1 are valid for combining. */
1950 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1951 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1957 /* Record whether I2DEST is used in I2SRC and similarly for the other
1958 cases. Knowing this will help in register status updating below. */
1959 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1960 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1961 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1963 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1965 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1967 /* Ensure that I3's pattern can be the destination of combines. */
1968 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1969 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1976 /* See if any of the insns is a MULT operation. Unless one is, we will
1977 reject a combination that is, since it must be slower. Be conservative
1979 if (GET_CODE (i2src
) == MULT
1980 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1981 || (GET_CODE (PATTERN (i3
)) == SET
1982 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1985 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1986 We used to do this EXCEPT in one case: I3 has a post-inc in an
1987 output operand. However, that exception can give rise to insns like
1989 which is a famous insn on the PDP-11 where the value of r3 used as the
1990 source was model-dependent. Avoid this sort of thing. */
1993 if (!(GET_CODE (PATTERN (i3
)) == SET
1994 && REG_P (SET_SRC (PATTERN (i3
)))
1995 && MEM_P (SET_DEST (PATTERN (i3
)))
1996 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1997 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1998 /* It's not the exception. */
2001 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2002 if (REG_NOTE_KIND (link
) == REG_INC
2003 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2005 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2012 /* See if the SETs in I1 or I2 need to be kept around in the merged
2013 instruction: whenever the value set there is still needed past I3.
2014 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2016 For the SET in I1, we have two cases: If I1 and I2 independently
2017 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2018 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2019 in I1 needs to be kept around unless I1DEST dies or is set in either
2020 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2021 I1DEST. If so, we know I1 feeds into I2. */
2023 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
2026 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
2027 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
2029 /* If the set in I2 needs to be kept around, we must make a copy of
2030 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2031 PATTERN (I2), we are only substituting for the original I1DEST, not into
2032 an already-substituted copy. This also prevents making self-referential
2033 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2036 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
2037 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
2041 i2pat
= copy_rtx (i2pat
);
2045 /* Substitute in the latest insn for the regs set by the earlier ones. */
2047 maxreg
= max_reg_num ();
2051 /* It is possible that the source of I2 or I1 may be performing an
2052 unneeded operation, such as a ZERO_EXTEND of something that is known
2053 to have the high part zero. Handle that case by letting subst look at
2054 the innermost one of them.
2056 Another way to do this would be to have a function that tries to
2057 simplify a single insn instead of merging two or more insns. We don't
2058 do this because of the potential of infinite loops and because
2059 of the potential extra memory required. However, doing it the way
2060 we are is a bit of a kludge and doesn't catch all cases.
2062 But only do this if -fexpensive-optimizations since it slows things down
2063 and doesn't usually win. */
2065 if (flag_expensive_optimizations
)
2067 /* Pass pc_rtx so no substitutions are done, just simplifications. */
2070 subst_low_cuid
= INSN_CUID (i1
);
2071 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
2075 subst_low_cuid
= INSN_CUID (i2
);
2076 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
2081 /* Many machines that don't use CC0 have insns that can both perform an
2082 arithmetic operation and set the condition code. These operations will
2083 be represented as a PARALLEL with the first element of the vector
2084 being a COMPARE of an arithmetic operation with the constant zero.
2085 The second element of the vector will set some pseudo to the result
2086 of the same arithmetic operation. If we simplify the COMPARE, we won't
2087 match such a pattern and so will generate an extra insn. Here we test
2088 for this case, where both the comparison and the operation result are
2089 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2090 I2SRC. Later we will make the PARALLEL that contains I2. */
2092 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2093 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2094 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
2095 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2097 #ifdef SELECT_CC_MODE
2099 enum machine_mode compare_mode
;
2102 newpat
= PATTERN (i3
);
2103 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
2107 #ifdef SELECT_CC_MODE
2108 /* See if a COMPARE with the operand we substituted in should be done
2109 with the mode that is currently being used. If not, do the same
2110 processing we do in `subst' for a SET; namely, if the destination
2111 is used only once, try to replace it with a register of the proper
2112 mode and also replace the COMPARE. */
2113 if (undobuf
.other_insn
== 0
2114 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
2115 &undobuf
.other_insn
))
2116 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
2118 != GET_MODE (SET_DEST (newpat
))))
2120 unsigned int regno
= REGNO (SET_DEST (newpat
));
2121 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
2123 if (regno
< FIRST_PSEUDO_REGISTER
2124 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
2125 && ! REG_USERVAR_P (SET_DEST (newpat
))))
2127 if (regno
>= FIRST_PSEUDO_REGISTER
)
2128 SUBST (regno_reg_rtx
[regno
], new_dest
);
2130 SUBST (SET_DEST (newpat
), new_dest
);
2131 SUBST (XEXP (*cc_use
, 0), new_dest
);
2132 SUBST (SET_SRC (newpat
),
2133 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
2136 undobuf
.other_insn
= 0;
2143 n_occurrences
= 0; /* `subst' counts here */
2145 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2146 need to make a unique copy of I2SRC each time we substitute it
2147 to avoid self-referential rtl. */
2149 subst_low_cuid
= INSN_CUID (i2
);
2150 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
2151 ! i1_feeds_i3
&& i1dest_in_i1src
);
2154 /* Record whether i2's body now appears within i3's body. */
2155 i2_is_used
= n_occurrences
;
2158 /* If we already got a failure, don't try to do more. Otherwise,
2159 try to substitute in I1 if we have it. */
2161 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
2163 /* Before we can do this substitution, we must redo the test done
2164 above (see detailed comments there) that ensures that I1DEST
2165 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2167 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
2175 subst_low_cuid
= INSN_CUID (i1
);
2176 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
2180 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2181 to count all the ways that I2SRC and I1SRC can be used. */
2182 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
2183 && i2_is_used
+ added_sets_2
> 1)
2184 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2185 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
2187 /* Fail if we tried to make a new register. */
2188 || max_reg_num () != maxreg
2189 /* Fail if we couldn't do something and have a CLOBBER. */
2190 || GET_CODE (newpat
) == CLOBBER
2191 /* Fail if this new pattern is a MULT and we didn't have one before
2192 at the outer level. */
2193 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2200 /* If the actions of the earlier insns must be kept
2201 in addition to substituting them into the latest one,
2202 we must make a new PARALLEL for the latest insn
2203 to hold additional the SETs. */
2205 if (added_sets_1
|| added_sets_2
)
2209 if (GET_CODE (newpat
) == PARALLEL
)
2211 rtvec old
= XVEC (newpat
, 0);
2212 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2213 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2214 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2215 sizeof (old
->elem
[0]) * old
->num_elem
);
2220 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2221 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2222 XVECEXP (newpat
, 0, 0) = old
;
2226 XVECEXP (newpat
, 0, --total_sets
)
2227 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2228 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2232 /* If there is no I1, use I2's body as is. We used to also not do
2233 the subst call below if I2 was substituted into I3,
2234 but that could lose a simplification. */
2236 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2238 /* See comment where i2pat is assigned. */
2239 XVECEXP (newpat
, 0, --total_sets
)
2240 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2244 /* We come here when we are replacing a destination in I2 with the
2245 destination of I3. */
2246 validate_replacement
:
2248 /* Note which hard regs this insn has as inputs. */
2249 mark_used_regs_combine (newpat
);
2251 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2252 consider splitting this pattern, we might need these clobbers. */
2253 if (i1
&& GET_CODE (newpat
) == PARALLEL
2254 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
2256 int len
= XVECLEN (newpat
, 0);
2258 newpat_vec_with_clobbers
= rtvec_alloc (len
);
2259 for (i
= 0; i
< len
; i
++)
2260 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
2263 /* Is the result of combination a valid instruction? */
2264 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2266 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2267 the second SET's destination is a register that is unused and isn't
2268 marked as an instruction that might trap in an EH region. In that case,
2269 we just need the first SET. This can occur when simplifying a divmod
2270 insn. We *must* test for this case here because the code below that
2271 splits two independent SETs doesn't handle this case correctly when it
2272 updates the register status.
2274 It's pointless doing this if we originally had two sets, one from
2275 i3, and one from i2. Combining then splitting the parallel results
2276 in the original i2 again plus an invalid insn (which we delete).
2277 The net effect is only to move instructions around, which makes
2278 debug info less accurate.
2280 Also check the case where the first SET's destination is unused.
2281 That would not cause incorrect code, but does cause an unneeded
2284 if (insn_code_number
< 0
2285 && !(added_sets_2
&& i1
== 0)
2286 && GET_CODE (newpat
) == PARALLEL
2287 && XVECLEN (newpat
, 0) == 2
2288 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2289 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2290 && asm_noperands (newpat
) < 0)
2292 rtx set0
= XVECEXP (newpat
, 0, 0);
2293 rtx set1
= XVECEXP (newpat
, 0, 1);
2296 if (((REG_P (SET_DEST (set1
))
2297 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2298 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2299 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2300 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2301 || INTVAL (XEXP (note
, 0)) <= 0)
2302 && ! side_effects_p (SET_SRC (set1
)))
2305 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2308 else if (((REG_P (SET_DEST (set0
))
2309 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2310 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2311 && find_reg_note (i3
, REG_UNUSED
,
2312 SUBREG_REG (SET_DEST (set0
)))))
2313 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2314 || INTVAL (XEXP (note
, 0)) <= 0)
2315 && ! side_effects_p (SET_SRC (set0
)))
2318 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2320 if (insn_code_number
>= 0)
2322 /* If we will be able to accept this, we have made a
2323 change to the destination of I3. This requires us to
2324 do a few adjustments. */
2326 PATTERN (i3
) = newpat
;
2327 adjust_for_new_dest (i3
);
2332 /* If we were combining three insns and the result is a simple SET
2333 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2334 insns. There are two ways to do this. It can be split using a
2335 machine-specific method (like when you have an addition of a large
2336 constant) or by combine in the function find_split_point. */
2338 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2339 && asm_noperands (newpat
) < 0)
2341 rtx m_split
, *split
;
2342 rtx ni2dest
= i2dest
;
2344 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2345 use I2DEST as a scratch register will help. In the latter case,
2346 convert I2DEST to the mode of the source of NEWPAT if we can. */
2348 m_split
= split_insns (newpat
, i3
);
2350 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2351 inputs of NEWPAT. */
2353 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2354 possible to try that as a scratch reg. This would require adding
2355 more code to make it work though. */
2357 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2359 /* If I2DEST is a hard register or the only use of a pseudo,
2360 we can change its mode. */
2361 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2362 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2364 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2365 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2366 && ! REG_USERVAR_P (i2dest
))))
2367 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2370 m_split
= split_insns (gen_rtx_PARALLEL
2372 gen_rtvec (2, newpat
,
2373 gen_rtx_CLOBBER (VOIDmode
,
2376 /* If the split with the mode-changed register didn't work, try
2377 the original register. */
2378 if (! m_split
&& ni2dest
!= i2dest
)
2381 m_split
= split_insns (gen_rtx_PARALLEL
2383 gen_rtvec (2, newpat
,
2384 gen_rtx_CLOBBER (VOIDmode
,
2390 /* If recog_for_combine has discarded clobbers, try to use them
2391 again for the split. */
2392 if (m_split
== 0 && newpat_vec_with_clobbers
)
2394 = split_insns (gen_rtx_PARALLEL (VOIDmode
,
2395 newpat_vec_with_clobbers
), i3
);
2397 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2399 m_split
= PATTERN (m_split
);
2400 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2401 if (insn_code_number
>= 0)
2404 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2405 && (next_real_insn (i2
) == i3
2406 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2409 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2410 newi2pat
= PATTERN (m_split
);
2412 i3set
= single_set (NEXT_INSN (m_split
));
2413 i2set
= single_set (m_split
);
2415 /* In case we changed the mode of I2DEST, replace it in the
2416 pseudo-register table here. We can't do it above in case this
2417 code doesn't get executed and we do a split the other way. */
2419 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2420 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2422 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2424 /* If I2 or I3 has multiple SETs, we won't know how to track
2425 register status, so don't use these insns. If I2's destination
2426 is used between I2 and I3, we also can't use these insns. */
2428 if (i2_code_number
>= 0 && i2set
&& i3set
2429 && (next_real_insn (i2
) == i3
2430 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2431 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2433 if (insn_code_number
>= 0)
2436 /* It is possible that both insns now set the destination of I3.
2437 If so, we must show an extra use of it. */
2439 if (insn_code_number
>= 0)
2441 rtx new_i3_dest
= SET_DEST (i3set
);
2442 rtx new_i2_dest
= SET_DEST (i2set
);
2444 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2445 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2446 || GET_CODE (new_i3_dest
) == SUBREG
)
2447 new_i3_dest
= XEXP (new_i3_dest
, 0);
2449 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2450 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2451 || GET_CODE (new_i2_dest
) == SUBREG
)
2452 new_i2_dest
= XEXP (new_i2_dest
, 0);
2454 if (REG_P (new_i3_dest
)
2455 && REG_P (new_i2_dest
)
2456 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2457 REG_N_SETS (REGNO (new_i2_dest
))++;
2461 /* If we can split it and use I2DEST, go ahead and see if that
2462 helps things be recognized. Verify that none of the registers
2463 are set between I2 and I3. */
2464 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2468 /* We need I2DEST in the proper mode. If it is a hard register
2469 or the only use of a pseudo, we can change its mode.
2470 Make sure we don't change a hard register to have a mode that
2471 isn't valid for it, or change the number of registers. */
2472 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2473 || GET_MODE (*split
) == VOIDmode
2474 || (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2475 && HARD_REGNO_MODE_OK (REGNO (i2dest
), GET_MODE (*split
))
2476 && (hard_regno_nregs
[REGNO (i2dest
)][GET_MODE (i2dest
)]
2477 == hard_regno_nregs
[REGNO (i2dest
)][GET_MODE (*split
)]))
2478 || (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
2479 && REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2480 && ! REG_USERVAR_P (i2dest
)))
2481 && (next_real_insn (i2
) == i3
2482 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2483 /* We can't overwrite I2DEST if its value is still used by
2485 && ! reg_referenced_p (i2dest
, newpat
))
2487 rtx newdest
= i2dest
;
2488 enum rtx_code split_code
= GET_CODE (*split
);
2489 enum machine_mode split_mode
= GET_MODE (*split
);
2491 /* Get NEWDEST as a register in the proper mode. We have already
2492 validated that we can do this. */
2493 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2495 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2497 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2498 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2501 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2502 an ASHIFT. This can occur if it was inside a PLUS and hence
2503 appeared to be a memory address. This is a kludge. */
2504 if (split_code
== MULT
2505 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2506 && INTVAL (XEXP (*split
, 1)) > 0
2507 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2509 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2510 XEXP (*split
, 0), GEN_INT (i
)));
2511 /* Update split_code because we may not have a multiply
2513 split_code
= GET_CODE (*split
);
2516 #ifdef INSN_SCHEDULING
2517 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2518 be written as a ZERO_EXTEND. */
2519 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
2521 #ifdef LOAD_EXTEND_OP
2522 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2523 what it really is. */
2524 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2526 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2527 SUBREG_REG (*split
)));
2530 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2531 SUBREG_REG (*split
)));
2535 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2536 SUBST (*split
, newdest
);
2537 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2539 /* recog_for_combine might have added CLOBBERs to newi2pat.
2540 Make sure NEWPAT does not depend on the clobbered regs. */
2541 if (GET_CODE (newi2pat
) == PARALLEL
)
2542 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
2543 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
2545 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
2546 if (reg_overlap_mentioned_p (reg
, newpat
))
2553 /* If the split point was a MULT and we didn't have one before,
2554 don't use one now. */
2555 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2556 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2560 /* Check for a case where we loaded from memory in a narrow mode and
2561 then sign extended it, but we need both registers. In that case,
2562 we have a PARALLEL with both loads from the same memory location.
2563 We can split this into a load from memory followed by a register-register
2564 copy. This saves at least one insn, more if register allocation can
2567 We cannot do this if the destination of the first assignment is a
2568 condition code register or cc0. We eliminate this case by making sure
2569 the SET_DEST and SET_SRC have the same mode.
2571 We cannot do this if the destination of the second assignment is
2572 a register that we have already assumed is zero-extended. Similarly
2573 for a SUBREG of such a register. */
2575 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2576 && GET_CODE (newpat
) == PARALLEL
2577 && XVECLEN (newpat
, 0) == 2
2578 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2579 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2580 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2581 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2582 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2583 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2584 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2585 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2587 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2588 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2589 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2591 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2592 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2593 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2594 && (reg_stat
[REGNO (temp
)].nonzero_bits
2595 != GET_MODE_MASK (word_mode
))))
2596 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2597 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2599 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2600 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2601 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2602 && (reg_stat
[REGNO (temp
)].nonzero_bits
2603 != GET_MODE_MASK (word_mode
)))))
2604 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2605 SET_SRC (XVECEXP (newpat
, 0, 1)))
2606 && ! find_reg_note (i3
, REG_UNUSED
,
2607 SET_DEST (XVECEXP (newpat
, 0, 0))))
2611 newi2pat
= XVECEXP (newpat
, 0, 0);
2612 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2613 newpat
= XVECEXP (newpat
, 0, 1);
2614 SUBST (SET_SRC (newpat
),
2615 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2616 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2618 if (i2_code_number
>= 0)
2619 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2621 if (insn_code_number
>= 0)
2625 /* Similarly, check for a case where we have a PARALLEL of two independent
2626 SETs but we started with three insns. In this case, we can do the sets
2627 as two separate insns. This case occurs when some SET allows two
2628 other insns to combine, but the destination of that SET is still live. */
2630 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2631 && GET_CODE (newpat
) == PARALLEL
2632 && XVECLEN (newpat
, 0) == 2
2633 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2634 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2635 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2636 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2637 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2638 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2639 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2641 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2642 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2643 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2644 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2645 XVECEXP (newpat
, 0, 0))
2646 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2647 XVECEXP (newpat
, 0, 1))
2648 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2649 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2651 /* Normally, it doesn't matter which of the two is done first,
2652 but it does if one references cc0. In that case, it has to
2655 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2657 newi2pat
= XVECEXP (newpat
, 0, 0);
2658 newpat
= XVECEXP (newpat
, 0, 1);
2663 newi2pat
= XVECEXP (newpat
, 0, 1);
2664 newpat
= XVECEXP (newpat
, 0, 0);
2667 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2669 if (i2_code_number
>= 0)
2670 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2673 /* If it still isn't recognized, fail and change things back the way they
2675 if ((insn_code_number
< 0
2676 /* Is the result a reasonable ASM_OPERANDS? */
2677 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2683 /* If we had to change another insn, make sure it is valid also. */
2684 if (undobuf
.other_insn
)
2686 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2687 rtx new_other_notes
;
2690 CLEAR_HARD_REG_SET (newpat_used_regs
);
2692 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2695 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2701 PATTERN (undobuf
.other_insn
) = other_pat
;
2703 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2704 are still valid. Then add any non-duplicate notes added by
2705 recog_for_combine. */
2706 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2708 next
= XEXP (note
, 1);
2710 if (REG_NOTE_KIND (note
) == REG_UNUSED
2711 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2713 if (REG_P (XEXP (note
, 0)))
2714 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2716 remove_note (undobuf
.other_insn
, note
);
2720 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2721 if (REG_P (XEXP (note
, 0)))
2722 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2724 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2725 undobuf
.other_insn
, NULL_RTX
);
2728 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2729 they are adjacent to each other or not. */
2731 rtx p
= prev_nonnote_insn (i3
);
2732 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
2733 && sets_cc0_p (newi2pat
))
2741 /* Only allow this combination if insn_rtx_costs reports that the
2742 replacement instructions are cheaper than the originals. */
2743 if (!combine_validate_cost (i1
, i2
, i3
, newpat
, newi2pat
))
2749 /* We now know that we can do this combination. Merge the insns and
2750 update the status of registers and LOG_LINKS. */
2758 /* I3 now uses what used to be its destination and which is now
2759 I2's destination. This requires us to do a few adjustments. */
2760 PATTERN (i3
) = newpat
;
2761 adjust_for_new_dest (i3
);
2763 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2766 However, some later insn might be using I2's dest and have
2767 a LOG_LINK pointing at I3. We must remove this link.
2768 The simplest way to remove the link is to point it at I1,
2769 which we know will be a NOTE. */
2771 /* newi2pat is usually a SET here; however, recog_for_combine might
2772 have added some clobbers. */
2773 if (GET_CODE (newi2pat
) == PARALLEL
)
2774 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
2776 ni2dest
= SET_DEST (newi2pat
);
2778 for (insn
= NEXT_INSN (i3
);
2779 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2780 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
2781 insn
= NEXT_INSN (insn
))
2783 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2785 for (link
= LOG_LINKS (insn
); link
;
2786 link
= XEXP (link
, 1))
2787 if (XEXP (link
, 0) == i3
)
2788 XEXP (link
, 0) = i1
;
2796 rtx i3notes
, i2notes
, i1notes
= 0;
2797 rtx i3links
, i2links
, i1links
= 0;
2801 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2803 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2804 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2806 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2808 /* Ensure that we do not have something that should not be shared but
2809 occurs multiple times in the new insns. Check this by first
2810 resetting all the `used' flags and then copying anything is shared. */
2812 reset_used_flags (i3notes
);
2813 reset_used_flags (i2notes
);
2814 reset_used_flags (i1notes
);
2815 reset_used_flags (newpat
);
2816 reset_used_flags (newi2pat
);
2817 if (undobuf
.other_insn
)
2818 reset_used_flags (PATTERN (undobuf
.other_insn
));
2820 i3notes
= copy_rtx_if_shared (i3notes
);
2821 i2notes
= copy_rtx_if_shared (i2notes
);
2822 i1notes
= copy_rtx_if_shared (i1notes
);
2823 newpat
= copy_rtx_if_shared (newpat
);
2824 newi2pat
= copy_rtx_if_shared (newi2pat
);
2825 if (undobuf
.other_insn
)
2826 reset_used_flags (PATTERN (undobuf
.other_insn
));
2828 INSN_CODE (i3
) = insn_code_number
;
2829 PATTERN (i3
) = newpat
;
2831 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
2833 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2835 reset_used_flags (call_usage
);
2836 call_usage
= copy_rtx (call_usage
);
2839 replace_rtx (call_usage
, i2dest
, i2src
);
2842 replace_rtx (call_usage
, i1dest
, i1src
);
2844 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2847 if (undobuf
.other_insn
)
2848 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2850 /* We had one special case above where I2 had more than one set and
2851 we replaced a destination of one of those sets with the destination
2852 of I3. In that case, we have to update LOG_LINKS of insns later
2853 in this basic block. Note that this (expensive) case is rare.
2855 Also, in this case, we must pretend that all REG_NOTEs for I2
2856 actually came from I3, so that REG_UNUSED notes from I2 will be
2857 properly handled. */
2859 if (i3_subst_into_i2
)
2861 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2862 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2863 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
2864 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2865 && ! find_reg_note (i2
, REG_UNUSED
,
2866 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2867 for (temp
= NEXT_INSN (i2
);
2868 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2869 || BB_HEAD (this_basic_block
) != temp
);
2870 temp
= NEXT_INSN (temp
))
2871 if (temp
!= i3
&& INSN_P (temp
))
2872 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2873 if (XEXP (link
, 0) == i2
)
2874 XEXP (link
, 0) = i3
;
2879 while (XEXP (link
, 1))
2880 link
= XEXP (link
, 1);
2881 XEXP (link
, 1) = i2notes
;
2895 INSN_CODE (i2
) = i2_code_number
;
2896 PATTERN (i2
) = newi2pat
;
2899 SET_INSN_DELETED (i2
);
2905 SET_INSN_DELETED (i1
);
2908 /* Get death notes for everything that is now used in either I3 or
2909 I2 and used to die in a previous insn. If we built two new
2910 patterns, move from I1 to I2 then I2 to I3 so that we get the
2911 proper movement on registers that I2 modifies. */
2915 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2916 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2919 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2922 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2924 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2926 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2928 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2930 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2932 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2933 know these are REG_UNUSED and want them to go to the desired insn,
2934 so we always pass it as i3. We have not counted the notes in
2935 reg_n_deaths yet, so we need to do so now. */
2937 if (newi2pat
&& new_i2_notes
)
2939 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2940 if (REG_P (XEXP (temp
, 0)))
2941 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2943 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2948 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2949 if (REG_P (XEXP (temp
, 0)))
2950 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2952 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2955 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2956 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2957 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2958 in that case, it might delete I2. Similarly for I2 and I1.
2959 Show an additional death due to the REG_DEAD note we make here. If
2960 we discard it in distribute_notes, we will decrement it again. */
2964 if (REG_P (i3dest_killed
))
2965 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2967 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2968 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2970 NULL_RTX
, i2
, NULL_RTX
);
2972 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2974 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2977 if (i2dest_in_i2src
)
2980 REG_N_DEATHS (REGNO (i2dest
))++;
2982 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2983 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2984 NULL_RTX
, i2
, NULL_RTX
);
2986 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2987 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2990 if (i1dest_in_i1src
)
2993 REG_N_DEATHS (REGNO (i1dest
))++;
2995 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2996 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2997 NULL_RTX
, i2
, NULL_RTX
);
2999 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
3000 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
3003 distribute_links (i3links
);
3004 distribute_links (i2links
);
3005 distribute_links (i1links
);
3010 rtx i2_insn
= 0, i2_val
= 0, set
;
3012 /* The insn that used to set this register doesn't exist, and
3013 this life of the register may not exist either. See if one of
3014 I3's links points to an insn that sets I2DEST. If it does,
3015 that is now the last known value for I2DEST. If we don't update
3016 this and I2 set the register to a value that depended on its old
3017 contents, we will get confused. If this insn is used, thing
3018 will be set correctly in combine_instructions. */
3020 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
3021 if ((set
= single_set (XEXP (link
, 0))) != 0
3022 && rtx_equal_p (i2dest
, SET_DEST (set
)))
3023 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
3025 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
3027 /* If the reg formerly set in I2 died only once and that was in I3,
3028 zero its use count so it won't make `reload' do any work. */
3030 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
3031 && ! i2dest_in_i2src
)
3033 regno
= REGNO (i2dest
);
3034 REG_N_SETS (regno
)--;
3038 if (i1
&& REG_P (i1dest
))
3041 rtx i1_insn
= 0, i1_val
= 0, set
;
3043 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
3044 if ((set
= single_set (XEXP (link
, 0))) != 0
3045 && rtx_equal_p (i1dest
, SET_DEST (set
)))
3046 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
3048 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
3050 regno
= REGNO (i1dest
);
3051 if (! added_sets_1
&& ! i1dest_in_i1src
)
3052 REG_N_SETS (regno
)--;
3055 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3056 been made to this insn. The order of
3057 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3058 can affect nonzero_bits of newpat */
3060 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
3061 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
3063 /* Set new_direct_jump_p if a new return or simple jump instruction
3066 If I3 is now an unconditional jump, ensure that it has a
3067 BARRIER following it since it may have initially been a
3068 conditional jump. It may also be the last nonnote insn. */
3070 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
3072 *new_direct_jump_p
= 1;
3073 mark_jump_label (PATTERN (i3
), i3
, 0);
3075 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
3076 || !BARRIER_P (temp
))
3077 emit_barrier_after (i3
);
3080 if (undobuf
.other_insn
!= NULL_RTX
3081 && (returnjump_p (undobuf
.other_insn
)
3082 || any_uncondjump_p (undobuf
.other_insn
)))
3084 *new_direct_jump_p
= 1;
3086 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
3087 || !BARRIER_P (temp
))
3088 emit_barrier_after (undobuf
.other_insn
);
3091 /* An NOOP jump does not need barrier, but it does need cleaning up
3093 if (GET_CODE (newpat
) == SET
3094 && SET_SRC (newpat
) == pc_rtx
3095 && SET_DEST (newpat
) == pc_rtx
)
3096 *new_direct_jump_p
= 1;
3099 combine_successes
++;
3102 if (added_links_insn
3103 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
3104 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
3105 return added_links_insn
;
3107 return newi2pat
? i2
: i3
;
3110 /* Undo all the modifications recorded in undobuf. */
3115 struct undo
*undo
, *next
;
3117 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3121 *undo
->where
.i
= undo
->old_contents
.i
;
3123 *undo
->where
.r
= undo
->old_contents
.r
;
3125 undo
->next
= undobuf
.frees
;
3126 undobuf
.frees
= undo
;
3132 /* We've committed to accepting the changes we made. Move all
3133 of the undos to the free list. */
3138 struct undo
*undo
, *next
;
3140 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3143 undo
->next
= undobuf
.frees
;
3144 undobuf
.frees
= undo
;
3150 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3151 where we have an arithmetic expression and return that point. LOC will
3154 try_combine will call this function to see if an insn can be split into
3158 find_split_point (rtx
*loc
, rtx insn
)
3161 enum rtx_code code
= GET_CODE (x
);
3163 unsigned HOST_WIDE_INT len
= 0;
3164 HOST_WIDE_INT pos
= 0;
3166 rtx inner
= NULL_RTX
;
3168 /* First special-case some codes. */
3172 #ifdef INSN_SCHEDULING
3173 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3175 if (MEM_P (SUBREG_REG (x
)))
3178 return find_split_point (&SUBREG_REG (x
), insn
);
3182 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3183 using LO_SUM and HIGH. */
3184 if (GET_CODE (XEXP (x
, 0)) == CONST
3185 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
3188 gen_rtx_LO_SUM (Pmode
,
3189 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
3191 return &XEXP (XEXP (x
, 0), 0);
3195 /* If we have a PLUS whose second operand is a constant and the
3196 address is not valid, perhaps will can split it up using
3197 the machine-specific way to split large constants. We use
3198 the first pseudo-reg (one of the virtual regs) as a placeholder;
3199 it will not remain in the result. */
3200 if (GET_CODE (XEXP (x
, 0)) == PLUS
3201 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3202 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
3204 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
3205 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
3208 /* This should have produced two insns, each of which sets our
3209 placeholder. If the source of the second is a valid address,
3210 we can make put both sources together and make a split point
3214 && NEXT_INSN (seq
) != NULL_RTX
3215 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
3216 && NONJUMP_INSN_P (seq
)
3217 && GET_CODE (PATTERN (seq
)) == SET
3218 && SET_DEST (PATTERN (seq
)) == reg
3219 && ! reg_mentioned_p (reg
,
3220 SET_SRC (PATTERN (seq
)))
3221 && NONJUMP_INSN_P (NEXT_INSN (seq
))
3222 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
3223 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
3224 && memory_address_p (GET_MODE (x
),
3225 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
3227 rtx src1
= SET_SRC (PATTERN (seq
));
3228 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
3230 /* Replace the placeholder in SRC2 with SRC1. If we can
3231 find where in SRC2 it was placed, that can become our
3232 split point and we can replace this address with SRC2.
3233 Just try two obvious places. */
3235 src2
= replace_rtx (src2
, reg
, src1
);
3237 if (XEXP (src2
, 0) == src1
)
3238 split
= &XEXP (src2
, 0);
3239 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
3240 && XEXP (XEXP (src2
, 0), 0) == src1
)
3241 split
= &XEXP (XEXP (src2
, 0), 0);
3245 SUBST (XEXP (x
, 0), src2
);
3250 /* If that didn't work, perhaps the first operand is complex and
3251 needs to be computed separately, so make a split point there.
3252 This will occur on machines that just support REG + CONST
3253 and have a constant moved through some previous computation. */
3255 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
3256 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
3257 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
3258 return &XEXP (XEXP (x
, 0), 0);
3264 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3265 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3266 we need to put the operand into a register. So split at that
3269 if (SET_DEST (x
) == cc0_rtx
3270 && GET_CODE (SET_SRC (x
)) != COMPARE
3271 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
3272 && !OBJECT_P (SET_SRC (x
))
3273 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
3274 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
3275 return &SET_SRC (x
);
3278 /* See if we can split SET_SRC as it stands. */
3279 split
= find_split_point (&SET_SRC (x
), insn
);
3280 if (split
&& split
!= &SET_SRC (x
))
3283 /* See if we can split SET_DEST as it stands. */
3284 split
= find_split_point (&SET_DEST (x
), insn
);
3285 if (split
&& split
!= &SET_DEST (x
))
3288 /* See if this is a bitfield assignment with everything constant. If
3289 so, this is an IOR of an AND, so split it into that. */
3290 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3291 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
3292 <= HOST_BITS_PER_WIDE_INT
)
3293 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3294 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3295 && GET_CODE (SET_SRC (x
)) == CONST_INT
3296 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3297 + INTVAL (XEXP (SET_DEST (x
), 2)))
3298 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3299 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3301 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3302 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3303 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3304 rtx dest
= XEXP (SET_DEST (x
), 0);
3305 enum machine_mode mode
= GET_MODE (dest
);
3306 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3308 if (BITS_BIG_ENDIAN
)
3309 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3313 simplify_gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3316 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
3318 simplify_gen_binary (IOR
, mode
,
3319 simplify_gen_binary (AND
, mode
,
3321 GEN_INT (src
<< pos
)));
3324 SUBST (SET_DEST (x
), dest
);
3326 split
= find_split_point (&SET_SRC (x
), insn
);
3327 if (split
&& split
!= &SET_SRC (x
))
3331 /* Otherwise, see if this is an operation that we can split into two.
3332 If so, try to split that. */
3333 code
= GET_CODE (SET_SRC (x
));
3338 /* If we are AND'ing with a large constant that is only a single
3339 bit and the result is only being used in a context where we
3340 need to know if it is zero or nonzero, replace it with a bit
3341 extraction. This will avoid the large constant, which might
3342 have taken more than one insn to make. If the constant were
3343 not a valid argument to the AND but took only one insn to make,
3344 this is no worse, but if it took more than one insn, it will
3347 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3348 && REG_P (XEXP (SET_SRC (x
), 0))
3349 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3350 && REG_P (SET_DEST (x
))
3351 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3352 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3353 && XEXP (*split
, 0) == SET_DEST (x
)
3354 && XEXP (*split
, 1) == const0_rtx
)
3356 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3357 XEXP (SET_SRC (x
), 0),
3358 pos
, NULL_RTX
, 1, 1, 0, 0);
3359 if (extraction
!= 0)
3361 SUBST (SET_SRC (x
), extraction
);
3362 return find_split_point (loc
, insn
);
3368 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3369 is known to be on, this can be converted into a NEG of a shift. */
3370 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3371 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3372 && 1 <= (pos
= exact_log2
3373 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3374 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3376 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3380 gen_rtx_LSHIFTRT (mode
,
3381 XEXP (SET_SRC (x
), 0),
3384 split
= find_split_point (&SET_SRC (x
), insn
);
3385 if (split
&& split
!= &SET_SRC (x
))
3391 inner
= XEXP (SET_SRC (x
), 0);
3393 /* We can't optimize if either mode is a partial integer
3394 mode as we don't know how many bits are significant
3396 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3397 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3401 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3407 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3408 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3410 inner
= XEXP (SET_SRC (x
), 0);
3411 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3412 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3414 if (BITS_BIG_ENDIAN
)
3415 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3416 unsignedp
= (code
== ZERO_EXTRACT
);
3424 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3426 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3428 /* For unsigned, we have a choice of a shift followed by an
3429 AND or two shifts. Use two shifts for field sizes where the
3430 constant might be too large. We assume here that we can
3431 always at least get 8-bit constants in an AND insn, which is
3432 true for every current RISC. */
3434 if (unsignedp
&& len
<= 8)
3439 (mode
, gen_lowpart (mode
, inner
),
3441 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3443 split
= find_split_point (&SET_SRC (x
), insn
);
3444 if (split
&& split
!= &SET_SRC (x
))
3451 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3452 gen_rtx_ASHIFT (mode
,
3453 gen_lowpart (mode
, inner
),
3454 GEN_INT (GET_MODE_BITSIZE (mode
)
3456 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3458 split
= find_split_point (&SET_SRC (x
), insn
);
3459 if (split
&& split
!= &SET_SRC (x
))
3464 /* See if this is a simple operation with a constant as the second
3465 operand. It might be that this constant is out of range and hence
3466 could be used as a split point. */
3467 if (BINARY_P (SET_SRC (x
))
3468 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3469 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
3470 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3471 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
3472 return &XEXP (SET_SRC (x
), 1);
3474 /* Finally, see if this is a simple operation with its first operand
3475 not in a register. The operation might require this operand in a
3476 register, so return it as a split point. We can always do this
3477 because if the first operand were another operation, we would have
3478 already found it as a split point. */
3479 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
3480 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3481 return &XEXP (SET_SRC (x
), 0);
3487 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3488 it is better to write this as (not (ior A B)) so we can split it.
3489 Similarly for IOR. */
3490 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3493 gen_rtx_NOT (GET_MODE (x
),
3494 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3496 XEXP (XEXP (x
, 0), 0),
3497 XEXP (XEXP (x
, 1), 0))));
3498 return find_split_point (loc
, insn
);
3501 /* Many RISC machines have a large set of logical insns. If the
3502 second operand is a NOT, put it first so we will try to split the
3503 other operand first. */
3504 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3506 rtx tem
= XEXP (x
, 0);
3507 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3508 SUBST (XEXP (x
, 1), tem
);
3516 /* Otherwise, select our actions depending on our rtx class. */
3517 switch (GET_RTX_CLASS (code
))
3519 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3521 split
= find_split_point (&XEXP (x
, 2), insn
);
3524 /* ... fall through ... */
3526 case RTX_COMM_ARITH
:
3528 case RTX_COMM_COMPARE
:
3529 split
= find_split_point (&XEXP (x
, 1), insn
);
3532 /* ... fall through ... */
3534 /* Some machines have (and (shift ...) ...) insns. If X is not
3535 an AND, but XEXP (X, 0) is, use it as our split point. */
3536 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3537 return &XEXP (x
, 0);
3539 split
= find_split_point (&XEXP (x
, 0), insn
);
3545 /* Otherwise, we don't have a split point. */
3550 /* Throughout X, replace FROM with TO, and return the result.
3551 The result is TO if X is FROM;
3552 otherwise the result is X, but its contents may have been modified.
3553 If they were modified, a record was made in undobuf so that
3554 undo_all will (among other things) return X to its original state.
3556 If the number of changes necessary is too much to record to undo,
3557 the excess changes are not made, so the result is invalid.
3558 The changes already made can still be undone.
3559 undobuf.num_undo is incremented for such changes, so by testing that
3560 the caller can tell whether the result is valid.
3562 `n_occurrences' is incremented each time FROM is replaced.
3564 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3566 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3567 by copying if `n_occurrences' is nonzero. */
3570 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3572 enum rtx_code code
= GET_CODE (x
);
3573 enum machine_mode op0_mode
= VOIDmode
;
3578 /* Two expressions are equal if they are identical copies of a shared
3579 RTX or if they are both registers with the same register number
3582 #define COMBINE_RTX_EQUAL_P(X,Y) \
3584 || (REG_P (X) && REG_P (Y) \
3585 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3587 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3590 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3593 /* If X and FROM are the same register but different modes, they will
3594 not have been seen as equal above. However, flow.c will make a
3595 LOG_LINKS entry for that case. If we do nothing, we will try to
3596 rerecognize our original insn and, when it succeeds, we will
3597 delete the feeding insn, which is incorrect.
3599 So force this insn not to match in this (rare) case. */
3600 if (! in_dest
&& code
== REG
&& REG_P (from
)
3601 && REGNO (x
) == REGNO (from
))
3602 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3604 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3605 of which may contain things that can be combined. */
3606 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
3609 /* It is possible to have a subexpression appear twice in the insn.
3610 Suppose that FROM is a register that appears within TO.
3611 Then, after that subexpression has been scanned once by `subst',
3612 the second time it is scanned, TO may be found. If we were
3613 to scan TO here, we would find FROM within it and create a
3614 self-referent rtl structure which is completely wrong. */
3615 if (COMBINE_RTX_EQUAL_P (x
, to
))
3618 /* Parallel asm_operands need special attention because all of the
3619 inputs are shared across the arms. Furthermore, unsharing the
3620 rtl results in recognition failures. Failure to handle this case
3621 specially can result in circular rtl.
3623 Solve this by doing a normal pass across the first entry of the
3624 parallel, and only processing the SET_DESTs of the subsequent
3627 if (code
== PARALLEL
3628 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3629 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3631 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3633 /* If this substitution failed, this whole thing fails. */
3634 if (GET_CODE (new) == CLOBBER
3635 && XEXP (new, 0) == const0_rtx
)
3638 SUBST (XVECEXP (x
, 0, 0), new);
3640 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3642 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3645 && GET_CODE (dest
) != CC0
3646 && GET_CODE (dest
) != PC
)
3648 new = subst (dest
, from
, to
, 0, unique_copy
);
3650 /* If this substitution failed, this whole thing fails. */
3651 if (GET_CODE (new) == CLOBBER
3652 && XEXP (new, 0) == const0_rtx
)
3655 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3661 len
= GET_RTX_LENGTH (code
);
3662 fmt
= GET_RTX_FORMAT (code
);
3664 /* We don't need to process a SET_DEST that is a register, CC0,
3665 or PC, so set up to skip this common case. All other cases
3666 where we want to suppress replacing something inside a
3667 SET_SRC are handled via the IN_DEST operand. */
3669 && (REG_P (SET_DEST (x
))
3670 || GET_CODE (SET_DEST (x
)) == CC0
3671 || GET_CODE (SET_DEST (x
)) == PC
))
3674 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3677 op0_mode
= GET_MODE (XEXP (x
, 0));
3679 for (i
= 0; i
< len
; i
++)
3684 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3686 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3688 new = (unique_copy
&& n_occurrences
3689 ? copy_rtx (to
) : to
);
3694 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3697 /* If this substitution failed, this whole thing
3699 if (GET_CODE (new) == CLOBBER
3700 && XEXP (new, 0) == const0_rtx
)
3704 SUBST (XVECEXP (x
, i
, j
), new);
3707 else if (fmt
[i
] == 'e')
3709 /* If this is a register being set, ignore it. */
3713 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
3715 || code
== STRICT_LOW_PART
))
3718 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3720 /* In general, don't install a subreg involving two
3721 modes not tieable. It can worsen register
3722 allocation, and can even make invalid reload
3723 insns, since the reg inside may need to be copied
3724 from in the outside mode, and that may be invalid
3725 if it is an fp reg copied in integer mode.
3727 We allow two exceptions to this: It is valid if
3728 it is inside another SUBREG and the mode of that
3729 SUBREG and the mode of the inside of TO is
3730 tieable and it is valid if X is a SET that copies
3733 if (GET_CODE (to
) == SUBREG
3734 && ! MODES_TIEABLE_P (GET_MODE (to
),
3735 GET_MODE (SUBREG_REG (to
)))
3736 && ! (code
== SUBREG
3737 && MODES_TIEABLE_P (GET_MODE (x
),
3738 GET_MODE (SUBREG_REG (to
))))
3740 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3743 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3745 #ifdef CANNOT_CHANGE_MODE_CLASS
3748 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3749 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3752 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3755 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3759 /* If we are in a SET_DEST, suppress most cases unless we
3760 have gone inside a MEM, in which case we want to
3761 simplify the address. We assume here that things that
3762 are actually part of the destination have their inner
3763 parts in the first expression. This is true for SUBREG,
3764 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3765 things aside from REG and MEM that should appear in a
3767 new = subst (XEXP (x
, i
), from
, to
,
3769 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3770 || code
== ZERO_EXTRACT
))
3772 && i
== 0), unique_copy
);
3774 /* If we found that we will have to reject this combination,
3775 indicate that by returning the CLOBBER ourselves, rather than
3776 an expression containing it. This will speed things up as
3777 well as prevent accidents where two CLOBBERs are considered
3778 to be equal, thus producing an incorrect simplification. */
3780 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3783 if (GET_CODE (x
) == SUBREG
3784 && (GET_CODE (new) == CONST_INT
3785 || GET_CODE (new) == CONST_DOUBLE
))
3787 enum machine_mode mode
= GET_MODE (x
);
3789 x
= simplify_subreg (GET_MODE (x
), new,
3790 GET_MODE (SUBREG_REG (x
)),
3793 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3795 else if (GET_CODE (new) == CONST_INT
3796 && GET_CODE (x
) == ZERO_EXTEND
)
3798 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3799 new, GET_MODE (XEXP (x
, 0)));
3803 SUBST (XEXP (x
, i
), new);
3808 /* Try to simplify X. If the simplification changed the code, it is likely
3809 that further simplification will help, so loop, but limit the number
3810 of repetitions that will be performed. */
3812 for (i
= 0; i
< 4; i
++)
3814 /* If X is sufficiently simple, don't bother trying to do anything
3816 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3817 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
3819 if (GET_CODE (x
) == code
)
3822 code
= GET_CODE (x
);
3824 /* We no longer know the original mode of operand 0 since we
3825 have changed the form of X) */
3826 op0_mode
= VOIDmode
;
3832 /* Simplify X, a piece of RTL. We just operate on the expression at the
3833 outer level; call `subst' to simplify recursively. Return the new
3836 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3837 if we are inside a SET_DEST. */
3840 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
3842 enum rtx_code code
= GET_CODE (x
);
3843 enum machine_mode mode
= GET_MODE (x
);
3848 /* If this is a commutative operation, put a constant last and a complex
3849 expression first. We don't need to do this for comparisons here. */
3850 if (COMMUTATIVE_ARITH_P (x
)
3851 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3854 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3855 SUBST (XEXP (x
, 1), temp
);
3858 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3859 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3860 things. Check for cases where both arms are testing the same
3863 Don't do anything if all operands are very simple. */
3866 && ((!OBJECT_P (XEXP (x
, 0))
3867 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3868 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
3869 || (!OBJECT_P (XEXP (x
, 1))
3870 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3871 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
3873 && (!OBJECT_P (XEXP (x
, 0))
3874 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3875 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
3877 rtx cond
, true_rtx
, false_rtx
;
3879 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3881 /* If everything is a comparison, what we have is highly unlikely
3882 to be simpler, so don't use it. */
3883 && ! (COMPARISON_P (x
)
3884 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
3886 rtx cop1
= const0_rtx
;
3887 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3889 if (cond_code
== NE
&& COMPARISON_P (cond
))
3892 /* Simplify the alternative arms; this may collapse the true and
3893 false arms to store-flag values. Be careful to use copy_rtx
3894 here since true_rtx or false_rtx might share RTL with x as a
3895 result of the if_then_else_cond call above. */
3896 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3897 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3899 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3900 is unlikely to be simpler. */
3901 if (general_operand (true_rtx
, VOIDmode
)
3902 && general_operand (false_rtx
, VOIDmode
))
3904 enum rtx_code reversed
;
3906 /* Restarting if we generate a store-flag expression will cause
3907 us to loop. Just drop through in this case. */
3909 /* If the result values are STORE_FLAG_VALUE and zero, we can
3910 just make the comparison operation. */
3911 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3912 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
3914 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3915 && ((reversed
= reversed_comparison_code_parts
3916 (cond_code
, cond
, cop1
, NULL
))
3918 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
3921 /* Likewise, we can make the negate of a comparison operation
3922 if the result values are - STORE_FLAG_VALUE and zero. */
3923 else if (GET_CODE (true_rtx
) == CONST_INT
3924 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3925 && false_rtx
== const0_rtx
)
3926 x
= simplify_gen_unary (NEG
, mode
,
3927 simplify_gen_relational (cond_code
,
3931 else if (GET_CODE (false_rtx
) == CONST_INT
3932 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3933 && true_rtx
== const0_rtx
3934 && ((reversed
= reversed_comparison_code_parts
3935 (cond_code
, cond
, cop1
, NULL
))
3937 x
= simplify_gen_unary (NEG
, mode
,
3938 simplify_gen_relational (reversed
,
3943 return gen_rtx_IF_THEN_ELSE (mode
,
3944 simplify_gen_relational (cond_code
,
3949 true_rtx
, false_rtx
);
3951 code
= GET_CODE (x
);
3952 op0_mode
= VOIDmode
;
3957 /* Try to fold this expression in case we have constants that weren't
3960 switch (GET_RTX_CLASS (code
))
3963 if (op0_mode
== VOIDmode
)
3964 op0_mode
= GET_MODE (XEXP (x
, 0));
3965 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3968 case RTX_COMM_COMPARE
:
3970 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3971 if (cmp_mode
== VOIDmode
)
3973 cmp_mode
= GET_MODE (XEXP (x
, 1));
3974 if (cmp_mode
== VOIDmode
)
3975 cmp_mode
= op0_mode
;
3977 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
3978 XEXP (x
, 0), XEXP (x
, 1));
3981 case RTX_COMM_ARITH
:
3983 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3985 case RTX_BITFIELD_OPS
:
3987 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3988 XEXP (x
, 1), XEXP (x
, 2));
3997 code
= GET_CODE (temp
);
3998 op0_mode
= VOIDmode
;
3999 mode
= GET_MODE (temp
);
4002 /* First see if we can apply the inverse distributive law. */
4003 if (code
== PLUS
|| code
== MINUS
4004 || code
== AND
|| code
== IOR
|| code
== XOR
)
4006 x
= apply_distributive_law (x
);
4007 code
= GET_CODE (x
);
4008 op0_mode
= VOIDmode
;
4011 /* If CODE is an associative operation not otherwise handled, see if we
4012 can associate some operands. This can win if they are constants or
4013 if they are logically related (i.e. (a & b) & a). */
4014 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
4015 || code
== AND
|| code
== IOR
|| code
== XOR
4016 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
4017 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
4018 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
4020 if (GET_CODE (XEXP (x
, 0)) == code
)
4022 rtx other
= XEXP (XEXP (x
, 0), 0);
4023 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
4024 rtx inner_op1
= XEXP (x
, 1);
4027 /* Make sure we pass the constant operand if any as the second
4028 one if this is a commutative operation. */
4029 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
4031 rtx tem
= inner_op0
;
4032 inner_op0
= inner_op1
;
4035 inner
= simplify_binary_operation (code
== MINUS
? PLUS
4036 : code
== DIV
? MULT
4038 mode
, inner_op0
, inner_op1
);
4040 /* For commutative operations, try the other pair if that one
4042 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
4044 other
= XEXP (XEXP (x
, 0), 1);
4045 inner
= simplify_binary_operation (code
, mode
,
4046 XEXP (XEXP (x
, 0), 0),
4051 return simplify_gen_binary (code
, mode
, other
, inner
);
4055 /* A little bit of algebraic simplification here. */
4059 /* Ensure that our address has any ASHIFTs converted to MULT in case
4060 address-recognizing predicates are called later. */
4061 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
4062 SUBST (XEXP (x
, 0), temp
);
4066 if (op0_mode
== VOIDmode
)
4067 op0_mode
= GET_MODE (SUBREG_REG (x
));
4069 /* See if this can be moved to simplify_subreg. */
4070 if (CONSTANT_P (SUBREG_REG (x
))
4071 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
4072 /* Don't call gen_lowpart if the inner mode
4073 is VOIDmode and we cannot simplify it, as SUBREG without
4074 inner mode is invalid. */
4075 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
4076 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
4077 return gen_lowpart (mode
, SUBREG_REG (x
));
4079 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
4083 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
4089 /* Don't change the mode of the MEM if that would change the meaning
4091 if (MEM_P (SUBREG_REG (x
))
4092 && (MEM_VOLATILE_P (SUBREG_REG (x
))
4093 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
4094 return gen_rtx_CLOBBER (mode
, const0_rtx
);
4096 /* Note that we cannot do any narrowing for non-constants since
4097 we might have been counting on using the fact that some bits were
4098 zero. We now do this in the SET. */
4103 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4104 && subreg_lowpart_p (XEXP (x
, 0))
4105 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
4106 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
4107 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
4108 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
4110 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
4112 x
= gen_rtx_ROTATE (inner_mode
,
4113 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
4115 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
4116 return gen_lowpart (mode
, x
);
4119 /* Apply De Morgan's laws to reduce number of patterns for machines
4120 with negating logical insns (and-not, nand, etc.). If result has
4121 only one NOT, put it first, since that is how the patterns are
4124 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
4126 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
4127 enum machine_mode op_mode
;
4129 op_mode
= GET_MODE (in1
);
4130 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
4132 op_mode
= GET_MODE (in2
);
4133 if (op_mode
== VOIDmode
)
4135 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
4137 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
4140 in2
= in1
; in1
= tem
;
4143 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
4149 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4150 if (GET_CODE (XEXP (x
, 0)) == XOR
4151 && XEXP (XEXP (x
, 0), 1) == const1_rtx
4152 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
4153 return simplify_gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4156 temp
= expand_compound_operation (XEXP (x
, 0));
4158 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4159 replaced by (lshiftrt X C). This will convert
4160 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4162 if (GET_CODE (temp
) == ASHIFTRT
4163 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4164 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4165 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4166 INTVAL (XEXP (temp
, 1)));
4168 /* If X has only a single bit that might be nonzero, say, bit I, convert
4169 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4170 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4171 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4172 or a SUBREG of one since we'd be making the expression more
4173 complex if it was just a register. */
4176 && ! (GET_CODE (temp
) == SUBREG
4177 && REG_P (SUBREG_REG (temp
)))
4178 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4180 rtx temp1
= simplify_shift_const
4181 (NULL_RTX
, ASHIFTRT
, mode
,
4182 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4183 GET_MODE_BITSIZE (mode
) - 1 - i
),
4184 GET_MODE_BITSIZE (mode
) - 1 - i
);
4186 /* If all we did was surround TEMP with the two shifts, we
4187 haven't improved anything, so don't use it. Otherwise,
4188 we are better off with TEMP1. */
4189 if (GET_CODE (temp1
) != ASHIFTRT
4190 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4191 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4197 /* We can't handle truncation to a partial integer mode here
4198 because we don't know the real bitsize of the partial
4200 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4203 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4204 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4205 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4207 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4208 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4210 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4211 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4212 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4213 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4214 return XEXP (XEXP (x
, 0), 0);
4216 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4217 (OP:SI foo:SI) if OP is NEG or ABS. */
4218 if ((GET_CODE (XEXP (x
, 0)) == ABS
4219 || GET_CODE (XEXP (x
, 0)) == NEG
)
4220 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4221 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4222 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4223 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4224 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4226 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4228 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4229 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4230 && subreg_lowpart_p (XEXP (x
, 0)))
4231 return SUBREG_REG (XEXP (x
, 0));
4233 /* If we know that the value is already truncated, we can
4234 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4235 is nonzero for the corresponding modes. But don't do this
4236 for an (LSHIFTRT (MULT ...)) since this will cause problems
4237 with the umulXi3_highpart patterns. */
4238 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4239 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4240 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4241 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
4242 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4243 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4244 return gen_lowpart (mode
, XEXP (x
, 0));
4246 /* A truncate of a comparison can be replaced with a subreg if
4247 STORE_FLAG_VALUE permits. This is like the previous test,
4248 but it works even if the comparison is done in a mode larger
4249 than HOST_BITS_PER_WIDE_INT. */
4250 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4251 && COMPARISON_P (XEXP (x
, 0))
4252 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4253 return gen_lowpart (mode
, XEXP (x
, 0));
4255 /* Similarly, a truncate of a register whose value is a
4256 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4258 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4259 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4260 && (temp
= get_last_value (XEXP (x
, 0)))
4261 && COMPARISON_P (temp
))
4262 return gen_lowpart (mode
, XEXP (x
, 0));
4266 case FLOAT_TRUNCATE
:
4267 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4268 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4269 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4270 return XEXP (XEXP (x
, 0), 0);
4272 /* (float_truncate:SF (float_truncate:DF foo:XF))
4273 = (float_truncate:SF foo:XF).
4274 This may eliminate double rounding, so it is unsafe.
4276 (float_truncate:SF (float_extend:XF foo:DF))
4277 = (float_truncate:SF foo:DF).
4279 (float_truncate:DF (float_extend:XF foo:SF))
4280 = (float_extend:SF foo:DF). */
4281 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4282 && flag_unsafe_math_optimizations
)
4283 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4284 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4286 > GET_MODE_SIZE (mode
)
4287 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4289 XEXP (XEXP (x
, 0), 0), mode
);
4291 /* (float_truncate (float x)) is (float x) */
4292 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4293 && (flag_unsafe_math_optimizations
4294 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4295 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4296 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4297 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4298 return simplify_gen_unary (FLOAT
, mode
,
4299 XEXP (XEXP (x
, 0), 0),
4300 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4302 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4303 (OP:SF foo:SF) if OP is NEG or ABS. */
4304 if ((GET_CODE (XEXP (x
, 0)) == ABS
4305 || GET_CODE (XEXP (x
, 0)) == NEG
)
4306 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4307 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4308 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4309 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4311 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4312 is (float_truncate:SF x). */
4313 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4314 && subreg_lowpart_p (XEXP (x
, 0))
4315 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4316 return SUBREG_REG (XEXP (x
, 0));
4319 /* (float_extend (float_extend x)) is (float_extend x)
4321 (float_extend (float x)) is (float x) assuming that double
4322 rounding can't happen.
4324 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4325 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4326 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4327 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4328 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4329 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4330 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4331 XEXP (XEXP (x
, 0), 0),
4332 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4337 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4338 using cc0, in which case we want to leave it as a COMPARE
4339 so we can distinguish it from a register-register-copy. */
4340 if (XEXP (x
, 1) == const0_rtx
)
4343 /* x - 0 is the same as x unless x's mode has signed zeros and
4344 allows rounding towards -infinity. Under those conditions,
4346 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4347 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4348 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4354 /* (const (const X)) can become (const X). Do it this way rather than
4355 returning the inner CONST since CONST can be shared with a
4357 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4358 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4363 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4364 can add in an offset. find_split_point will split this address up
4365 again if it doesn't match. */
4366 if (GET_CODE (XEXP (x
, 0)) == HIGH
4367 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4373 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4375 if (GET_CODE (XEXP (x
, 0)) == MULT
4376 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4380 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4381 in2
= XEXP (XEXP (x
, 0), 1);
4382 return simplify_gen_binary (MINUS
, mode
, XEXP (x
, 1),
4383 simplify_gen_binary (MULT
, mode
,
4387 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4388 outermost. That's because that's the way indexed addresses are
4389 supposed to appear. This code used to check many more cases, but
4390 they are now checked elsewhere. */
4391 if (GET_CODE (XEXP (x
, 0)) == PLUS
4392 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4393 return simplify_gen_binary (PLUS
, mode
,
4394 simplify_gen_binary (PLUS
, mode
,
4395 XEXP (XEXP (x
, 0), 0),
4397 XEXP (XEXP (x
, 0), 1));
4399 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4400 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4401 bit-field and can be replaced by either a sign_extend or a
4402 sign_extract. The `and' may be a zero_extend and the two
4403 <c>, -<c> constants may be reversed. */
4404 if (GET_CODE (XEXP (x
, 0)) == XOR
4405 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4406 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4407 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4408 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4409 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4410 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4411 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4412 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4413 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4414 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4415 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4416 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4417 == (unsigned int) i
+ 1))))
4418 return simplify_shift_const
4419 (NULL_RTX
, ASHIFTRT
, mode
,
4420 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4421 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4422 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4423 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4425 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4426 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4427 is 1. This produces better code than the alternative immediately
4429 if (COMPARISON_P (XEXP (x
, 0))
4430 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4431 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4432 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
)))
4434 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4436 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4437 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4438 the bitsize of the mode - 1. This allows simplification of
4439 "a = (b & 8) == 0;" */
4440 if (XEXP (x
, 1) == constm1_rtx
4441 && !REG_P (XEXP (x
, 0))
4442 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4443 && REG_P (SUBREG_REG (XEXP (x
, 0))))
4444 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4445 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4446 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4447 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4448 GET_MODE_BITSIZE (mode
) - 1),
4449 GET_MODE_BITSIZE (mode
) - 1);
4451 /* If we are adding two things that have no bits in common, convert
4452 the addition into an IOR. This will often be further simplified,
4453 for example in cases like ((a & 1) + (a & 2)), which can
4456 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4457 && (nonzero_bits (XEXP (x
, 0), mode
)
4458 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4460 /* Try to simplify the expression further. */
4461 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4462 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
4464 /* If we could, great. If not, do not go ahead with the IOR
4465 replacement, since PLUS appears in many special purpose
4466 address arithmetic instructions. */
4467 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4473 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4474 by reversing the comparison code if valid. */
4475 if (STORE_FLAG_VALUE
== 1
4476 && XEXP (x
, 0) == const1_rtx
4477 && COMPARISON_P (XEXP (x
, 1))
4478 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
)))
4481 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4482 (and <foo> (const_int pow2-1)) */
4483 if (GET_CODE (XEXP (x
, 1)) == AND
4484 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4485 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4486 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4487 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4488 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4490 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4492 if (GET_CODE (XEXP (x
, 1)) == MULT
4493 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4497 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4498 in2
= XEXP (XEXP (x
, 1), 1);
4499 return simplify_gen_binary (PLUS
, mode
,
4500 simplify_gen_binary (MULT
, mode
,
4505 /* Canonicalize (minus (neg A) (mult B C)) to
4506 (minus (mult (neg B) C) A). */
4507 if (GET_CODE (XEXP (x
, 1)) == MULT
4508 && GET_CODE (XEXP (x
, 0)) == NEG
)
4512 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4513 in2
= XEXP (XEXP (x
, 1), 1);
4514 return simplify_gen_binary (MINUS
, mode
,
4515 simplify_gen_binary (MULT
, mode
,
4517 XEXP (XEXP (x
, 0), 0));
4520 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4522 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4523 return simplify_gen_binary (MINUS
, mode
,
4524 simplify_gen_binary (MINUS
, mode
,
4526 XEXP (XEXP (x
, 1), 0)),
4527 XEXP (XEXP (x
, 1), 1));
4531 /* If we have (mult (plus A B) C), apply the distributive law and then
4532 the inverse distributive law to see if things simplify. This
4533 occurs mostly in addresses, often when unrolling loops. */
4535 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4537 rtx result
= distribute_and_simplify_rtx (x
, 0);
4542 /* Try simplify a*(b/c) as (a*b)/c. */
4543 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4544 && GET_CODE (XEXP (x
, 0)) == DIV
)
4546 rtx tem
= simplify_binary_operation (MULT
, mode
,
4547 XEXP (XEXP (x
, 0), 0),
4550 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4555 /* If this is a divide by a power of two, treat it as a shift if
4556 its first operand is a shift. */
4557 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4558 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4559 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4560 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4561 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4562 || GET_CODE (XEXP (x
, 0)) == ROTATE
4563 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4564 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4568 case GT
: case GTU
: case GE
: case GEU
:
4569 case LT
: case LTU
: case LE
: case LEU
:
4570 case UNEQ
: case LTGT
:
4571 case UNGT
: case UNGE
:
4572 case UNLT
: case UNLE
:
4573 case UNORDERED
: case ORDERED
:
4574 /* If the first operand is a condition code, we can't do anything
4576 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4577 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4578 && ! CC0_P (XEXP (x
, 0))))
4580 rtx op0
= XEXP (x
, 0);
4581 rtx op1
= XEXP (x
, 1);
4582 enum rtx_code new_code
;
4584 if (GET_CODE (op0
) == COMPARE
)
4585 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4587 /* Simplify our comparison, if possible. */
4588 new_code
= simplify_comparison (code
, &op0
, &op1
);
4590 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4591 if only the low-order bit is possibly nonzero in X (such as when
4592 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4593 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4594 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4597 Remove any ZERO_EXTRACT we made when thinking this was a
4598 comparison. It may now be simpler to use, e.g., an AND. If a
4599 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4600 the call to make_compound_operation in the SET case. */
4602 if (STORE_FLAG_VALUE
== 1
4603 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4604 && op1
== const0_rtx
4605 && mode
== GET_MODE (op0
)
4606 && nonzero_bits (op0
, mode
) == 1)
4607 return gen_lowpart (mode
,
4608 expand_compound_operation (op0
));
4610 else if (STORE_FLAG_VALUE
== 1
4611 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4612 && op1
== const0_rtx
4613 && mode
== GET_MODE (op0
)
4614 && (num_sign_bit_copies (op0
, mode
)
4615 == GET_MODE_BITSIZE (mode
)))
4617 op0
= expand_compound_operation (op0
);
4618 return simplify_gen_unary (NEG
, mode
,
4619 gen_lowpart (mode
, op0
),
4623 else if (STORE_FLAG_VALUE
== 1
4624 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4625 && op1
== const0_rtx
4626 && mode
== GET_MODE (op0
)
4627 && nonzero_bits (op0
, mode
) == 1)
4629 op0
= expand_compound_operation (op0
);
4630 return simplify_gen_binary (XOR
, mode
,
4631 gen_lowpart (mode
, op0
),
4635 else if (STORE_FLAG_VALUE
== 1
4636 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4637 && op1
== const0_rtx
4638 && mode
== GET_MODE (op0
)
4639 && (num_sign_bit_copies (op0
, mode
)
4640 == GET_MODE_BITSIZE (mode
)))
4642 op0
= expand_compound_operation (op0
);
4643 return plus_constant (gen_lowpart (mode
, op0
), 1);
4646 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4648 if (STORE_FLAG_VALUE
== -1
4649 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4650 && op1
== const0_rtx
4651 && (num_sign_bit_copies (op0
, mode
)
4652 == GET_MODE_BITSIZE (mode
)))
4653 return gen_lowpart (mode
,
4654 expand_compound_operation (op0
));
4656 else if (STORE_FLAG_VALUE
== -1
4657 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4658 && op1
== const0_rtx
4659 && mode
== GET_MODE (op0
)
4660 && nonzero_bits (op0
, mode
) == 1)
4662 op0
= expand_compound_operation (op0
);
4663 return simplify_gen_unary (NEG
, mode
,
4664 gen_lowpart (mode
, op0
),
4668 else if (STORE_FLAG_VALUE
== -1
4669 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4670 && op1
== const0_rtx
4671 && mode
== GET_MODE (op0
)
4672 && (num_sign_bit_copies (op0
, mode
)
4673 == GET_MODE_BITSIZE (mode
)))
4675 op0
= expand_compound_operation (op0
);
4676 return simplify_gen_unary (NOT
, mode
,
4677 gen_lowpart (mode
, op0
),
4681 /* If X is 0/1, (eq X 0) is X-1. */
4682 else if (STORE_FLAG_VALUE
== -1
4683 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4684 && op1
== const0_rtx
4685 && mode
== GET_MODE (op0
)
4686 && nonzero_bits (op0
, mode
) == 1)
4688 op0
= expand_compound_operation (op0
);
4689 return plus_constant (gen_lowpart (mode
, op0
), -1);
4692 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4693 one bit that might be nonzero, we can convert (ne x 0) to
4694 (ashift x c) where C puts the bit in the sign bit. Remove any
4695 AND with STORE_FLAG_VALUE when we are done, since we are only
4696 going to test the sign bit. */
4697 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4698 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4699 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4700 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4701 && op1
== const0_rtx
4702 && mode
== GET_MODE (op0
)
4703 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4705 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4706 expand_compound_operation (op0
),
4707 GET_MODE_BITSIZE (mode
) - 1 - i
);
4708 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4714 /* If the code changed, return a whole new comparison. */
4715 if (new_code
!= code
)
4716 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4718 /* Otherwise, keep this operation, but maybe change its operands.
4719 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4720 SUBST (XEXP (x
, 0), op0
);
4721 SUBST (XEXP (x
, 1), op1
);
4726 return simplify_if_then_else (x
);
4732 /* If we are processing SET_DEST, we are done. */
4736 return expand_compound_operation (x
);
4739 return simplify_set (x
);
4744 return simplify_logical (x
);
4747 /* (abs (neg <foo>)) -> (abs <foo>) */
4748 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4749 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4751 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4753 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4756 /* If operand is something known to be positive, ignore the ABS. */
4757 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4758 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4759 <= HOST_BITS_PER_WIDE_INT
)
4760 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4761 & ((HOST_WIDE_INT
) 1
4762 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4766 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4767 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4768 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4773 /* (ffs (*_extend <X>)) = (ffs <X>) */
4774 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4775 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4776 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4781 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4782 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4783 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4787 /* (float (sign_extend <X>)) = (float <X>). */
4788 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4789 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4797 /* If this is a shift by a constant amount, simplify it. */
4798 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4799 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4800 INTVAL (XEXP (x
, 1)));
4802 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
4804 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4806 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4813 rtx op0
= XEXP (x
, 0);
4814 rtx op1
= XEXP (x
, 1);
4817 gcc_assert (GET_CODE (op1
) == PARALLEL
);
4818 len
= XVECLEN (op1
, 0);
4820 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4821 && GET_CODE (op0
) == VEC_CONCAT
)
4823 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4825 /* Try to find the element in the VEC_CONCAT. */
4828 if (GET_MODE (op0
) == GET_MODE (x
))
4830 if (GET_CODE (op0
) == VEC_CONCAT
)
4832 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4833 if (offset
< op0_size
)
4834 op0
= XEXP (op0
, 0);
4838 op0
= XEXP (op0
, 1);
4856 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4859 simplify_if_then_else (rtx x
)
4861 enum machine_mode mode
= GET_MODE (x
);
4862 rtx cond
= XEXP (x
, 0);
4863 rtx true_rtx
= XEXP (x
, 1);
4864 rtx false_rtx
= XEXP (x
, 2);
4865 enum rtx_code true_code
= GET_CODE (cond
);
4866 int comparison_p
= COMPARISON_P (cond
);
4869 enum rtx_code false_code
;
4872 /* Simplify storing of the truth value. */
4873 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4874 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
4875 XEXP (cond
, 0), XEXP (cond
, 1));
4877 /* Also when the truth value has to be reversed. */
4879 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4880 && (reversed
= reversed_comparison (cond
, mode
)))
4883 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4884 in it is being compared against certain values. Get the true and false
4885 comparisons and see if that says anything about the value of each arm. */
4888 && ((false_code
= reversed_comparison_code (cond
, NULL
))
4890 && REG_P (XEXP (cond
, 0)))
4893 rtx from
= XEXP (cond
, 0);
4894 rtx true_val
= XEXP (cond
, 1);
4895 rtx false_val
= true_val
;
4898 /* If FALSE_CODE is EQ, swap the codes and arms. */
4900 if (false_code
== EQ
)
4902 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4903 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4906 /* If we are comparing against zero and the expression being tested has
4907 only a single bit that might be nonzero, that is its value when it is
4908 not equal to zero. Similarly if it is known to be -1 or 0. */
4910 if (true_code
== EQ
&& true_val
== const0_rtx
4911 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4912 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4913 else if (true_code
== EQ
&& true_val
== const0_rtx
4914 && (num_sign_bit_copies (from
, GET_MODE (from
))
4915 == GET_MODE_BITSIZE (GET_MODE (from
))))
4916 false_code
= EQ
, false_val
= constm1_rtx
;
4918 /* Now simplify an arm if we know the value of the register in the
4919 branch and it is used in the arm. Be careful due to the potential
4920 of locally-shared RTL. */
4922 if (reg_mentioned_p (from
, true_rtx
))
4923 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4925 pc_rtx
, pc_rtx
, 0, 0);
4926 if (reg_mentioned_p (from
, false_rtx
))
4927 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4929 pc_rtx
, pc_rtx
, 0, 0);
4931 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4932 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4934 true_rtx
= XEXP (x
, 1);
4935 false_rtx
= XEXP (x
, 2);
4936 true_code
= GET_CODE (cond
);
4939 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4940 reversed, do so to avoid needing two sets of patterns for
4941 subtract-and-branch insns. Similarly if we have a constant in the true
4942 arm, the false arm is the same as the first operand of the comparison, or
4943 the false arm is more complicated than the true arm. */
4946 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
4947 && (true_rtx
== pc_rtx
4948 || (CONSTANT_P (true_rtx
)
4949 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4950 || true_rtx
== const0_rtx
4951 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
4952 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
4953 && !OBJECT_P (false_rtx
))
4954 || reg_mentioned_p (true_rtx
, false_rtx
)
4955 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4957 true_code
= reversed_comparison_code (cond
, NULL
);
4958 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
4959 SUBST (XEXP (x
, 1), false_rtx
);
4960 SUBST (XEXP (x
, 2), true_rtx
);
4962 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4965 /* It is possible that the conditional has been simplified out. */
4966 true_code
= GET_CODE (cond
);
4967 comparison_p
= COMPARISON_P (cond
);
4970 /* If the two arms are identical, we don't need the comparison. */
4972 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4975 /* Convert a == b ? b : a to "a". */
4976 if (true_code
== EQ
&& ! side_effects_p (cond
)
4977 && !HONOR_NANS (mode
)
4978 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4979 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4981 else if (true_code
== NE
&& ! side_effects_p (cond
)
4982 && !HONOR_NANS (mode
)
4983 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4984 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4987 /* Look for cases where we have (abs x) or (neg (abs X)). */
4989 if (GET_MODE_CLASS (mode
) == MODE_INT
4990 && GET_CODE (false_rtx
) == NEG
4991 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4993 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4994 && ! side_effects_p (true_rtx
))
4999 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
5003 simplify_gen_unary (NEG
, mode
,
5004 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
5010 /* Look for MIN or MAX. */
5012 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
5014 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5015 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
5016 && ! side_effects_p (cond
))
5021 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
5024 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
5027 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
5030 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
5035 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5036 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5037 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5038 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5039 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5040 neither 1 or -1, but it isn't worth checking for. */
5042 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5044 && GET_MODE_CLASS (mode
) == MODE_INT
5045 && ! side_effects_p (x
))
5047 rtx t
= make_compound_operation (true_rtx
, SET
);
5048 rtx f
= make_compound_operation (false_rtx
, SET
);
5049 rtx cond_op0
= XEXP (cond
, 0);
5050 rtx cond_op1
= XEXP (cond
, 1);
5051 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
5052 enum machine_mode m
= mode
;
5053 rtx z
= 0, c1
= NULL_RTX
;
5055 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
5056 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
5057 || GET_CODE (t
) == ASHIFT
5058 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
5059 && rtx_equal_p (XEXP (t
, 0), f
))
5060 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
5062 /* If an identity-zero op is commutative, check whether there
5063 would be a match if we swapped the operands. */
5064 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
5065 || GET_CODE (t
) == XOR
)
5066 && rtx_equal_p (XEXP (t
, 1), f
))
5067 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
5068 else if (GET_CODE (t
) == SIGN_EXTEND
5069 && (GET_CODE (XEXP (t
, 0)) == PLUS
5070 || GET_CODE (XEXP (t
, 0)) == MINUS
5071 || GET_CODE (XEXP (t
, 0)) == IOR
5072 || GET_CODE (XEXP (t
, 0)) == XOR
5073 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5074 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5075 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5076 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5077 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5078 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5079 && (num_sign_bit_copies (f
, GET_MODE (f
))
5081 (GET_MODE_BITSIZE (mode
)
5082 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
5084 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5085 extend_op
= SIGN_EXTEND
;
5086 m
= GET_MODE (XEXP (t
, 0));
5088 else if (GET_CODE (t
) == SIGN_EXTEND
5089 && (GET_CODE (XEXP (t
, 0)) == PLUS
5090 || GET_CODE (XEXP (t
, 0)) == IOR
5091 || GET_CODE (XEXP (t
, 0)) == XOR
)
5092 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5093 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5094 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5095 && (num_sign_bit_copies (f
, GET_MODE (f
))
5097 (GET_MODE_BITSIZE (mode
)
5098 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
5100 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5101 extend_op
= SIGN_EXTEND
;
5102 m
= GET_MODE (XEXP (t
, 0));
5104 else if (GET_CODE (t
) == ZERO_EXTEND
5105 && (GET_CODE (XEXP (t
, 0)) == PLUS
5106 || GET_CODE (XEXP (t
, 0)) == MINUS
5107 || GET_CODE (XEXP (t
, 0)) == IOR
5108 || GET_CODE (XEXP (t
, 0)) == XOR
5109 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5110 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5111 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5112 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5113 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5114 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5115 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5116 && ((nonzero_bits (f
, GET_MODE (f
))
5117 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
5120 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5121 extend_op
= ZERO_EXTEND
;
5122 m
= GET_MODE (XEXP (t
, 0));
5124 else if (GET_CODE (t
) == ZERO_EXTEND
5125 && (GET_CODE (XEXP (t
, 0)) == PLUS
5126 || GET_CODE (XEXP (t
, 0)) == IOR
5127 || GET_CODE (XEXP (t
, 0)) == XOR
)
5128 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5129 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5130 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5131 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5132 && ((nonzero_bits (f
, GET_MODE (f
))
5133 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
5136 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5137 extend_op
= ZERO_EXTEND
;
5138 m
= GET_MODE (XEXP (t
, 0));
5143 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
5144 cond_op0
, cond_op1
),
5145 pc_rtx
, pc_rtx
, 0, 0);
5146 temp
= simplify_gen_binary (MULT
, m
, temp
,
5147 simplify_gen_binary (MULT
, m
, c1
,
5149 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
5150 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
5152 if (extend_op
!= UNKNOWN
)
5153 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
5159 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5160 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5161 negation of a single bit, we can convert this operation to a shift. We
5162 can actually do this more generally, but it doesn't seem worth it. */
5164 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5165 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5166 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
5167 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
5168 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
5169 == GET_MODE_BITSIZE (mode
))
5170 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
5172 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5173 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
5175 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5176 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5177 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5178 && GET_MODE (XEXP (cond
, 0)) == mode
5179 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
5180 == nonzero_bits (XEXP (cond
, 0), mode
)
5181 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
5182 return XEXP (cond
, 0);
5187 /* Simplify X, a SET expression. Return the new expression. */
5190 simplify_set (rtx x
)
5192 rtx src
= SET_SRC (x
);
5193 rtx dest
= SET_DEST (x
);
5194 enum machine_mode mode
5195 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5199 /* (set (pc) (return)) gets written as (return). */
5200 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5203 /* Now that we know for sure which bits of SRC we are using, see if we can
5204 simplify the expression for the object knowing that we only need the
5207 if (GET_MODE_CLASS (mode
) == MODE_INT
5208 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5210 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
5211 SUBST (SET_SRC (x
), src
);
5214 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5215 the comparison result and try to simplify it unless we already have used
5216 undobuf.other_insn. */
5217 if ((GET_MODE_CLASS (mode
) == MODE_CC
5218 || GET_CODE (src
) == COMPARE
5220 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5221 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5222 && COMPARISON_P (*cc_use
)
5223 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5225 enum rtx_code old_code
= GET_CODE (*cc_use
);
5226 enum rtx_code new_code
;
5228 int other_changed
= 0;
5229 enum machine_mode compare_mode
= GET_MODE (dest
);
5231 if (GET_CODE (src
) == COMPARE
)
5232 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5234 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
5236 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
5239 new_code
= old_code
;
5240 else if (!CONSTANT_P (tmp
))
5242 new_code
= GET_CODE (tmp
);
5243 op0
= XEXP (tmp
, 0);
5244 op1
= XEXP (tmp
, 1);
5248 rtx pat
= PATTERN (other_insn
);
5249 undobuf
.other_insn
= other_insn
;
5250 SUBST (*cc_use
, tmp
);
5252 /* Attempt to simplify CC user. */
5253 if (GET_CODE (pat
) == SET
)
5255 rtx
new = simplify_rtx (SET_SRC (pat
));
5256 if (new != NULL_RTX
)
5257 SUBST (SET_SRC (pat
), new);
5260 /* Convert X into a no-op move. */
5261 SUBST (SET_DEST (x
), pc_rtx
);
5262 SUBST (SET_SRC (x
), pc_rtx
);
5266 /* Simplify our comparison, if possible. */
5267 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
5269 #ifdef SELECT_CC_MODE
5270 /* If this machine has CC modes other than CCmode, check to see if we
5271 need to use a different CC mode here. */
5272 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5273 compare_mode
= GET_MODE (op0
);
5275 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5278 /* If the mode changed, we have to change SET_DEST, the mode in the
5279 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5280 a hard register, just build new versions with the proper mode. If it
5281 is a pseudo, we lose unless it is only time we set the pseudo, in
5282 which case we can safely change its mode. */
5283 if (compare_mode
!= GET_MODE (dest
))
5285 unsigned int regno
= REGNO (dest
);
5286 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5288 if (regno
< FIRST_PSEUDO_REGISTER
5289 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5291 if (regno
>= FIRST_PSEUDO_REGISTER
)
5292 SUBST (regno_reg_rtx
[regno
], new_dest
);
5294 SUBST (SET_DEST (x
), new_dest
);
5295 SUBST (XEXP (*cc_use
, 0), new_dest
);
5302 #endif /* SELECT_CC_MODE */
5304 /* If the code changed, we have to build a new comparison in
5305 undobuf.other_insn. */
5306 if (new_code
!= old_code
)
5308 int other_changed_previously
= other_changed
;
5309 unsigned HOST_WIDE_INT mask
;
5311 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5315 /* If the only change we made was to change an EQ into an NE or
5316 vice versa, OP0 has only one bit that might be nonzero, and OP1
5317 is zero, check if changing the user of the condition code will
5318 produce a valid insn. If it won't, we can keep the original code
5319 in that insn by surrounding our operation with an XOR. */
5321 if (((old_code
== NE
&& new_code
== EQ
)
5322 || (old_code
== EQ
&& new_code
== NE
))
5323 && ! other_changed_previously
&& op1
== const0_rtx
5324 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5325 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5327 rtx pat
= PATTERN (other_insn
), note
= 0;
5329 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5330 && ! check_asm_operands (pat
)))
5332 PUT_CODE (*cc_use
, old_code
);
5335 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
5336 op0
, GEN_INT (mask
));
5342 undobuf
.other_insn
= other_insn
;
5345 /* If we are now comparing against zero, change our source if
5346 needed. If we do not use cc0, we always have a COMPARE. */
5347 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5349 SUBST (SET_SRC (x
), op0
);
5355 /* Otherwise, if we didn't previously have a COMPARE in the
5356 correct mode, we need one. */
5357 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5359 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5362 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
5364 SUBST(SET_SRC (x
), op0
);
5369 /* Otherwise, update the COMPARE if needed. */
5370 SUBST (XEXP (src
, 0), op0
);
5371 SUBST (XEXP (src
, 1), op1
);
5376 /* Get SET_SRC in a form where we have placed back any
5377 compound expressions. Then do the checks below. */
5378 src
= make_compound_operation (src
, SET
);
5379 SUBST (SET_SRC (x
), src
);
5382 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5383 and X being a REG or (subreg (reg)), we may be able to convert this to
5384 (set (subreg:m2 x) (op)).
5386 We can always do this if M1 is narrower than M2 because that means that
5387 we only care about the low bits of the result.
5389 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5390 perform a narrower operation than requested since the high-order bits will
5391 be undefined. On machine where it is defined, this transformation is safe
5392 as long as M1 and M2 have the same number of words. */
5394 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5395 && !OBJECT_P (SUBREG_REG (src
))
5396 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5398 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5399 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5400 #ifndef WORD_REGISTER_OPERATIONS
5401 && (GET_MODE_SIZE (GET_MODE (src
))
5402 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5404 #ifdef CANNOT_CHANGE_MODE_CLASS
5405 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
5406 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5407 GET_MODE (SUBREG_REG (src
)),
5411 || (GET_CODE (dest
) == SUBREG
5412 && REG_P (SUBREG_REG (dest
)))))
5414 SUBST (SET_DEST (x
),
5415 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5417 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5419 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5423 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5426 && GET_CODE (src
) == SUBREG
5427 && subreg_lowpart_p (src
)
5428 && (GET_MODE_BITSIZE (GET_MODE (src
))
5429 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5431 rtx inner
= SUBREG_REG (src
);
5432 enum machine_mode inner_mode
= GET_MODE (inner
);
5434 /* Here we make sure that we don't have a sign bit on. */
5435 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5436 && (nonzero_bits (inner
, inner_mode
)
5437 < ((unsigned HOST_WIDE_INT
) 1
5438 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5440 SUBST (SET_SRC (x
), inner
);
5446 #ifdef LOAD_EXTEND_OP
5447 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5448 would require a paradoxical subreg. Replace the subreg with a
5449 zero_extend to avoid the reload that would otherwise be required. */
5451 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5452 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
5453 && SUBREG_BYTE (src
) == 0
5454 && (GET_MODE_SIZE (GET_MODE (src
))
5455 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5456 && MEM_P (SUBREG_REG (src
)))
5459 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5460 GET_MODE (src
), SUBREG_REG (src
)));
5466 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5467 are comparing an item known to be 0 or -1 against 0, use a logical
5468 operation instead. Check for one of the arms being an IOR of the other
5469 arm with some value. We compute three terms to be IOR'ed together. In
5470 practice, at most two will be nonzero. Then we do the IOR's. */
5472 if (GET_CODE (dest
) != PC
5473 && GET_CODE (src
) == IF_THEN_ELSE
5474 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5475 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5476 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5477 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5478 #ifdef HAVE_conditional_move
5479 && ! can_conditionally_move_p (GET_MODE (src
))
5481 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5482 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5483 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5484 && ! side_effects_p (src
))
5486 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5487 ? XEXP (src
, 1) : XEXP (src
, 2));
5488 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5489 ? XEXP (src
, 2) : XEXP (src
, 1));
5490 rtx term1
= const0_rtx
, term2
, term3
;
5492 if (GET_CODE (true_rtx
) == IOR
5493 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5494 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5495 else if (GET_CODE (true_rtx
) == IOR
5496 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5497 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5498 else if (GET_CODE (false_rtx
) == IOR
5499 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5500 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5501 else if (GET_CODE (false_rtx
) == IOR
5502 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5503 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5505 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
5506 XEXP (XEXP (src
, 0), 0), true_rtx
);
5507 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
5508 simplify_gen_unary (NOT
, GET_MODE (src
),
5509 XEXP (XEXP (src
, 0), 0),
5514 simplify_gen_binary (IOR
, GET_MODE (src
),
5515 simplify_gen_binary (IOR
, GET_MODE (src
),
5522 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5523 whole thing fail. */
5524 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5526 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5529 /* Convert this into a field assignment operation, if possible. */
5530 return make_field_assignment (x
);
5533 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5537 simplify_logical (rtx x
)
5539 enum machine_mode mode
= GET_MODE (x
);
5540 rtx op0
= XEXP (x
, 0);
5541 rtx op1
= XEXP (x
, 1);
5544 switch (GET_CODE (x
))
5547 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5548 insn (and may simplify more). */
5549 if (GET_CODE (op0
) == XOR
5550 && rtx_equal_p (XEXP (op0
, 0), op1
)
5551 && ! side_effects_p (op1
))
5552 x
= simplify_gen_binary (AND
, mode
,
5553 simplify_gen_unary (NOT
, mode
,
5554 XEXP (op0
, 1), mode
),
5557 if (GET_CODE (op0
) == XOR
5558 && rtx_equal_p (XEXP (op0
, 1), op1
)
5559 && ! side_effects_p (op1
))
5560 x
= simplify_gen_binary (AND
, mode
,
5561 simplify_gen_unary (NOT
, mode
,
5562 XEXP (op0
, 0), mode
),
5565 /* Similarly for (~(A ^ B)) & A. */
5566 if (GET_CODE (op0
) == NOT
5567 && GET_CODE (XEXP (op0
, 0)) == XOR
5568 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5569 && ! side_effects_p (op1
))
5570 x
= simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5572 if (GET_CODE (op0
) == NOT
5573 && GET_CODE (XEXP (op0
, 0)) == XOR
5574 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5575 && ! side_effects_p (op1
))
5576 x
= simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5578 /* We can call simplify_and_const_int only if we don't lose
5579 any (sign) bits when converting INTVAL (op1) to
5580 "unsigned HOST_WIDE_INT". */
5581 if (GET_CODE (op1
) == CONST_INT
5582 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5583 || INTVAL (op1
) > 0))
5585 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5587 /* If we have (ior (and (X C1) C2)) and the next restart would be
5588 the last, simplify this by making C1 as small as possible
5589 and then exit. Only do this if C1 actually changes: for now
5590 this only saves memory but, should this transformation be
5591 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5592 if (GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5593 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5594 && GET_CODE (op1
) == CONST_INT
5595 && (INTVAL (XEXP (op0
, 1)) & INTVAL (op1
)) != 0)
5596 return simplify_gen_binary (IOR
, mode
,
5598 (AND
, mode
, XEXP (op0
, 0),
5599 GEN_INT (INTVAL (XEXP (op0
, 1))
5600 & ~INTVAL (op1
))), op1
);
5602 if (GET_CODE (x
) != AND
)
5609 /* Convert (A | B) & A to A. */
5610 if (GET_CODE (op0
) == IOR
5611 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5612 || rtx_equal_p (XEXP (op0
, 1), op1
))
5613 && ! side_effects_p (XEXP (op0
, 0))
5614 && ! side_effects_p (XEXP (op0
, 1)))
5617 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5618 apply the distributive law and then the inverse distributive
5619 law to see if things simplify. */
5620 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5622 rtx result
= distribute_and_simplify_rtx (x
, 0);
5626 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5628 rtx result
= distribute_and_simplify_rtx (x
, 1);
5635 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5636 if (GET_CODE (op1
) == CONST_INT
5637 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5638 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5641 /* Convert (A & B) | A to A. */
5642 if (GET_CODE (op0
) == AND
5643 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5644 || rtx_equal_p (XEXP (op0
, 1), op1
))
5645 && ! side_effects_p (XEXP (op0
, 0))
5646 && ! side_effects_p (XEXP (op0
, 1)))
5649 /* If we have (ior (and A B) C), apply the distributive law and then
5650 the inverse distributive law to see if things simplify. */
5652 if (GET_CODE (op0
) == AND
)
5654 rtx result
= distribute_and_simplify_rtx (x
, 0);
5659 if (GET_CODE (op1
) == AND
)
5661 rtx result
= distribute_and_simplify_rtx (x
, 1);
5666 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5667 mode size to (rotate A CX). */
5669 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5670 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5671 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5672 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5673 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5674 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5675 == GET_MODE_BITSIZE (mode
)))
5676 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5677 (GET_CODE (op0
) == ASHIFT
5678 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5680 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5681 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5682 does not affect any of the bits in OP1, it can really be done
5683 as a PLUS and we can associate. We do this by seeing if OP1
5684 can be safely shifted left C bits. */
5685 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5686 && GET_CODE (XEXP (op0
, 0)) == PLUS
5687 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5688 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5689 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5691 int count
= INTVAL (XEXP (op0
, 1));
5692 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5694 if (mask
>> count
== INTVAL (op1
)
5695 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5697 SUBST (XEXP (XEXP (op0
, 0), 1),
5698 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5705 /* If we are XORing two things that have no bits in common,
5706 convert them into an IOR. This helps to detect rotation encoded
5707 using those methods and possibly other simplifications. */
5709 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5710 && (nonzero_bits (op0
, mode
)
5711 & nonzero_bits (op1
, mode
)) == 0)
5712 return (simplify_gen_binary (IOR
, mode
, op0
, op1
));
5714 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5715 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5718 int num_negated
= 0;
5720 if (GET_CODE (op0
) == NOT
)
5721 num_negated
++, op0
= XEXP (op0
, 0);
5722 if (GET_CODE (op1
) == NOT
)
5723 num_negated
++, op1
= XEXP (op1
, 0);
5725 if (num_negated
== 2)
5727 SUBST (XEXP (x
, 0), op0
);
5728 SUBST (XEXP (x
, 1), op1
);
5730 else if (num_negated
== 1)
5732 simplify_gen_unary (NOT
, mode
,
5733 simplify_gen_binary (XOR
, mode
, op0
, op1
),
5737 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5738 correspond to a machine insn or result in further simplifications
5739 if B is a constant. */
5741 if (GET_CODE (op0
) == AND
5742 && rtx_equal_p (XEXP (op0
, 1), op1
)
5743 && ! side_effects_p (op1
))
5744 return simplify_gen_binary (AND
, mode
,
5745 simplify_gen_unary (NOT
, mode
,
5746 XEXP (op0
, 0), mode
),
5749 else if (GET_CODE (op0
) == AND
5750 && rtx_equal_p (XEXP (op0
, 0), op1
)
5751 && ! side_effects_p (op1
))
5752 return simplify_gen_binary (AND
, mode
,
5753 simplify_gen_unary (NOT
, mode
,
5754 XEXP (op0
, 1), mode
),
5757 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5758 comparison if STORE_FLAG_VALUE is 1. */
5759 if (STORE_FLAG_VALUE
== 1
5760 && op1
== const1_rtx
5761 && COMPARISON_P (op0
)
5762 && (reversed
= reversed_comparison (op0
, mode
)))
5765 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5766 is (lt foo (const_int 0)), so we can perform the above
5767 simplification if STORE_FLAG_VALUE is 1. */
5769 if (STORE_FLAG_VALUE
== 1
5770 && op1
== const1_rtx
5771 && GET_CODE (op0
) == LSHIFTRT
5772 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5773 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5774 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5776 /* (xor (comparison foo bar) (const_int sign-bit))
5777 when STORE_FLAG_VALUE is the sign bit. */
5778 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5779 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5780 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5781 && op1
== const_true_rtx
5782 && COMPARISON_P (op0
)
5783 && (reversed
= reversed_comparison (op0
, mode
)))
5795 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5796 operations" because they can be replaced with two more basic operations.
5797 ZERO_EXTEND is also considered "compound" because it can be replaced with
5798 an AND operation, which is simpler, though only one operation.
5800 The function expand_compound_operation is called with an rtx expression
5801 and will convert it to the appropriate shifts and AND operations,
5802 simplifying at each stage.
5804 The function make_compound_operation is called to convert an expression
5805 consisting of shifts and ANDs into the equivalent compound expression.
5806 It is the inverse of this function, loosely speaking. */
5809 expand_compound_operation (rtx x
)
5811 unsigned HOST_WIDE_INT pos
= 0, len
;
5813 unsigned int modewidth
;
5816 switch (GET_CODE (x
))
5821 /* We can't necessarily use a const_int for a multiword mode;
5822 it depends on implicitly extending the value.
5823 Since we don't know the right way to extend it,
5824 we can't tell whether the implicit way is right.
5826 Even for a mode that is no wider than a const_int,
5827 we can't win, because we need to sign extend one of its bits through
5828 the rest of it, and we don't know which bit. */
5829 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5832 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5833 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5834 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5835 reloaded. If not for that, MEM's would very rarely be safe.
5837 Reject MODEs bigger than a word, because we might not be able
5838 to reference a two-register group starting with an arbitrary register
5839 (and currently gen_lowpart might crash for a SUBREG). */
5841 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5844 /* Reject MODEs that aren't scalar integers because turning vector
5845 or complex modes into shifts causes problems. */
5847 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5850 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5851 /* If the inner object has VOIDmode (the only way this can happen
5852 is if it is an ASM_OPERANDS), we can't do anything since we don't
5853 know how much masking to do. */
5862 /* ... fall through ... */
5865 /* If the operand is a CLOBBER, just return it. */
5866 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5869 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5870 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5871 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5874 /* Reject MODEs that aren't scalar integers because turning vector
5875 or complex modes into shifts causes problems. */
5877 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5880 len
= INTVAL (XEXP (x
, 1));
5881 pos
= INTVAL (XEXP (x
, 2));
5883 /* If this goes outside the object being extracted, replace the object
5884 with a (use (mem ...)) construct that only combine understands
5885 and is used only for this purpose. */
5886 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5887 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5889 if (BITS_BIG_ENDIAN
)
5890 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5897 /* Convert sign extension to zero extension, if we know that the high
5898 bit is not set, as this is easier to optimize. It will be converted
5899 back to cheaper alternative in make_extraction. */
5900 if (GET_CODE (x
) == SIGN_EXTEND
5901 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5902 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5903 & ~(((unsigned HOST_WIDE_INT
)
5904 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5908 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5909 rtx temp2
= expand_compound_operation (temp
);
5911 /* Make sure this is a profitable operation. */
5912 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5914 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5920 /* We can optimize some special cases of ZERO_EXTEND. */
5921 if (GET_CODE (x
) == ZERO_EXTEND
)
5923 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5924 know that the last value didn't have any inappropriate bits
5926 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5927 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5928 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5929 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5930 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5931 return XEXP (XEXP (x
, 0), 0);
5933 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5934 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5935 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5936 && subreg_lowpart_p (XEXP (x
, 0))
5937 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5938 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5939 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5940 return SUBREG_REG (XEXP (x
, 0));
5942 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5943 is a comparison and STORE_FLAG_VALUE permits. This is like
5944 the first case, but it works even when GET_MODE (x) is larger
5945 than HOST_WIDE_INT. */
5946 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5947 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5948 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
5949 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5950 <= HOST_BITS_PER_WIDE_INT
)
5951 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5952 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5953 return XEXP (XEXP (x
, 0), 0);
5955 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5956 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5957 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5958 && subreg_lowpart_p (XEXP (x
, 0))
5959 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
5960 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5961 <= HOST_BITS_PER_WIDE_INT
)
5962 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5963 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5964 return SUBREG_REG (XEXP (x
, 0));
5968 /* If we reach here, we want to return a pair of shifts. The inner
5969 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5970 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5971 logical depending on the value of UNSIGNEDP.
5973 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5974 converted into an AND of a shift.
5976 We must check for the case where the left shift would have a negative
5977 count. This can happen in a case like (x >> 31) & 255 on machines
5978 that can't shift by a constant. On those machines, we would first
5979 combine the shift with the AND to produce a variable-position
5980 extraction. Then the constant of 31 would be substituted in to produce
5981 a such a position. */
5983 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5984 if (modewidth
+ len
>= pos
)
5985 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5987 simplify_shift_const (NULL_RTX
, ASHIFT
,
5990 modewidth
- pos
- len
),
5993 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5994 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5995 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5998 ((HOST_WIDE_INT
) 1 << len
) - 1);
6000 /* Any other cases we can't handle. */
6003 /* If we couldn't do this for some reason, return the original
6005 if (GET_CODE (tem
) == CLOBBER
)
6011 /* X is a SET which contains an assignment of one object into
6012 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6013 or certain SUBREGS). If possible, convert it into a series of
6016 We half-heartedly support variable positions, but do not at all
6017 support variable lengths. */
6020 expand_field_assignment (rtx x
)
6023 rtx pos
; /* Always counts from low bit. */
6025 rtx mask
, cleared
, masked
;
6026 enum machine_mode compute_mode
;
6028 /* Loop until we find something we can't simplify. */
6031 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6032 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6034 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6035 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
6036 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6038 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6039 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
6041 inner
= XEXP (SET_DEST (x
), 0);
6042 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6043 pos
= XEXP (SET_DEST (x
), 2);
6045 /* If the position is constant and spans the width of INNER,
6046 surround INNER with a USE to indicate this. */
6047 if (GET_CODE (pos
) == CONST_INT
6048 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
6049 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
6051 if (BITS_BIG_ENDIAN
)
6053 if (GET_CODE (pos
) == CONST_INT
)
6054 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
6056 else if (GET_CODE (pos
) == MINUS
6057 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
6058 && (INTVAL (XEXP (pos
, 1))
6059 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
6060 /* If position is ADJUST - X, new position is X. */
6061 pos
= XEXP (pos
, 0);
6063 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6064 GEN_INT (GET_MODE_BITSIZE (
6071 /* A SUBREG between two modes that occupy the same numbers of words
6072 can be done by moving the SUBREG to the source. */
6073 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6074 /* We need SUBREGs to compute nonzero_bits properly. */
6075 && nonzero_sign_valid
6076 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6077 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6078 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6079 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6081 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6083 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6090 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6091 inner
= SUBREG_REG (inner
);
6093 compute_mode
= GET_MODE (inner
);
6095 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6096 if (! SCALAR_INT_MODE_P (compute_mode
))
6098 enum machine_mode imode
;
6100 /* Don't do anything for vector or complex integral types. */
6101 if (! FLOAT_MODE_P (compute_mode
))
6104 /* Try to find an integral mode to pun with. */
6105 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6106 if (imode
== BLKmode
)
6109 compute_mode
= imode
;
6110 inner
= gen_lowpart (imode
, inner
);
6113 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6114 if (len
>= HOST_BITS_PER_WIDE_INT
)
6117 /* Now compute the equivalent expression. Make a copy of INNER
6118 for the SET_DEST in case it is a MEM into which we will substitute;
6119 we don't want shared RTL in that case. */
6120 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
6121 cleared
= simplify_gen_binary (AND
, compute_mode
,
6122 simplify_gen_unary (NOT
, compute_mode
,
6123 simplify_gen_binary (ASHIFT
,
6128 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6129 simplify_gen_binary (
6131 gen_lowpart (compute_mode
, SET_SRC (x
)),
6135 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6136 simplify_gen_binary (IOR
, compute_mode
,
6143 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6144 it is an RTX that represents a variable starting position; otherwise,
6145 POS is the (constant) starting bit position (counted from the LSB).
6147 INNER may be a USE. This will occur when we started with a bitfield
6148 that went outside the boundary of the object in memory, which is
6149 allowed on most machines. To isolate this case, we produce a USE
6150 whose mode is wide enough and surround the MEM with it. The only
6151 code that understands the USE is this routine. If it is not removed,
6152 it will cause the resulting insn not to match.
6154 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6157 IN_DEST is nonzero if this is a reference in the destination of a
6158 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6159 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6162 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6163 ZERO_EXTRACT should be built even for bits starting at bit 0.
6165 MODE is the desired mode of the result (if IN_DEST == 0).
6167 The result is an RTX for the extraction or NULL_RTX if the target
6171 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6172 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6173 int in_dest
, int in_compare
)
6175 /* This mode describes the size of the storage area
6176 to fetch the overall value from. Within that, we
6177 ignore the POS lowest bits, etc. */
6178 enum machine_mode is_mode
= GET_MODE (inner
);
6179 enum machine_mode inner_mode
;
6180 enum machine_mode wanted_inner_mode
= byte_mode
;
6181 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6182 enum machine_mode pos_mode
= word_mode
;
6183 enum machine_mode extraction_mode
= word_mode
;
6184 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6187 rtx orig_pos_rtx
= pos_rtx
;
6188 HOST_WIDE_INT orig_pos
;
6190 /* Get some information about INNER and get the innermost object. */
6191 if (GET_CODE (inner
) == USE
)
6192 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6193 /* We don't need to adjust the position because we set up the USE
6194 to pretend that it was a full-word object. */
6195 spans_byte
= 1, inner
= XEXP (inner
, 0);
6196 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6198 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6199 consider just the QI as the memory to extract from.
6200 The subreg adds or removes high bits; its mode is
6201 irrelevant to the meaning of this extraction,
6202 since POS and LEN count from the lsb. */
6203 if (MEM_P (SUBREG_REG (inner
)))
6204 is_mode
= GET_MODE (SUBREG_REG (inner
));
6205 inner
= SUBREG_REG (inner
);
6207 else if (GET_CODE (inner
) == ASHIFT
6208 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
6209 && pos_rtx
== 0 && pos
== 0
6210 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6212 /* We're extracting the least significant bits of an rtx
6213 (ashift X (const_int C)), where LEN > C. Extract the
6214 least significant (LEN - C) bits of X, giving an rtx
6215 whose mode is MODE, then shift it left C times. */
6216 new = make_extraction (mode
, XEXP (inner
, 0),
6217 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6218 unsignedp
, in_dest
, in_compare
);
6220 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6223 inner_mode
= GET_MODE (inner
);
6225 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6226 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6228 /* See if this can be done without an extraction. We never can if the
6229 width of the field is not the same as that of some integer mode. For
6230 registers, we can only avoid the extraction if the position is at the
6231 low-order bit and this is either not in the destination or we have the
6232 appropriate STRICT_LOW_PART operation available.
6234 For MEM, we can avoid an extract if the field starts on an appropriate
6235 boundary and we can change the mode of the memory reference. However,
6236 we cannot directly access the MEM if we have a USE and the underlying
6237 MEM is not TMODE. This combination means that MEM was being used in a
6238 context where bits outside its mode were being referenced; that is only
6239 valid in bit-field insns. */
6241 if (tmode
!= BLKmode
6242 && ! (spans_byte
&& inner_mode
!= tmode
)
6243 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6247 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6248 || (MEM_P (inner
) && pos_rtx
== 0
6250 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6251 : BITS_PER_UNIT
)) == 0
6252 /* We can't do this if we are widening INNER_MODE (it
6253 may not be aligned, for one thing). */
6254 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6255 && (inner_mode
== tmode
6256 || (! mode_dependent_address_p (XEXP (inner
, 0))
6257 && ! MEM_VOLATILE_P (inner
))))))
6259 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6260 field. If the original and current mode are the same, we need not
6261 adjust the offset. Otherwise, we do if bytes big endian.
6263 If INNER is not a MEM, get a piece consisting of just the field
6264 of interest (in this case POS % BITS_PER_WORD must be 0). */
6268 HOST_WIDE_INT offset
;
6270 /* POS counts from lsb, but make OFFSET count in memory order. */
6271 if (BYTES_BIG_ENDIAN
)
6272 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6274 offset
= pos
/ BITS_PER_UNIT
;
6276 new = adjust_address_nv (inner
, tmode
, offset
);
6278 else if (REG_P (inner
))
6280 if (tmode
!= inner_mode
)
6282 /* We can't call gen_lowpart in a DEST since we
6283 always want a SUBREG (see below) and it would sometimes
6284 return a new hard register. */
6287 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6289 if (WORDS_BIG_ENDIAN
6290 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6291 final_word
= ((GET_MODE_SIZE (inner_mode
)
6292 - GET_MODE_SIZE (tmode
))
6293 / UNITS_PER_WORD
) - final_word
;
6295 final_word
*= UNITS_PER_WORD
;
6296 if (BYTES_BIG_ENDIAN
&&
6297 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6298 final_word
+= (GET_MODE_SIZE (inner_mode
)
6299 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6301 /* Avoid creating invalid subregs, for example when
6302 simplifying (x>>32)&255. */
6303 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6306 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6309 new = gen_lowpart (tmode
, inner
);
6315 new = force_to_mode (inner
, tmode
,
6316 len
>= HOST_BITS_PER_WIDE_INT
6317 ? ~(unsigned HOST_WIDE_INT
) 0
6318 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6321 /* If this extraction is going into the destination of a SET,
6322 make a STRICT_LOW_PART unless we made a MEM. */
6325 return (MEM_P (new) ? new
6326 : (GET_CODE (new) != SUBREG
6327 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6328 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6333 if (GET_CODE (new) == CONST_INT
)
6334 return gen_int_mode (INTVAL (new), mode
);
6336 /* If we know that no extraneous bits are set, and that the high
6337 bit is not set, convert the extraction to the cheaper of
6338 sign and zero extension, that are equivalent in these cases. */
6339 if (flag_expensive_optimizations
6340 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6341 && ((nonzero_bits (new, tmode
)
6342 & ~(((unsigned HOST_WIDE_INT
)
6343 GET_MODE_MASK (tmode
))
6347 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6348 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6350 /* Prefer ZERO_EXTENSION, since it gives more information to
6352 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6357 /* Otherwise, sign- or zero-extend unless we already are in the
6360 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6364 /* Unless this is a COMPARE or we have a funny memory reference,
6365 don't do anything with zero-extending field extracts starting at
6366 the low-order bit since they are simple AND operations. */
6367 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6368 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6371 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6372 we would be spanning bytes or if the position is not a constant and the
6373 length is not 1. In all other cases, we would only be going outside
6374 our object in cases when an original shift would have been
6376 if (! spans_byte
&& MEM_P (inner
)
6377 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6378 || (pos_rtx
!= 0 && len
!= 1)))
6381 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6382 and the mode for the result. */
6383 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6385 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6386 pos_mode
= mode_for_extraction (EP_insv
, 2);
6387 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6390 if (! in_dest
&& unsignedp
6391 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6393 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6394 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6395 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6398 if (! in_dest
&& ! unsignedp
6399 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6401 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6402 pos_mode
= mode_for_extraction (EP_extv
, 3);
6403 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6406 /* Never narrow an object, since that might not be safe. */
6408 if (mode
!= VOIDmode
6409 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6410 extraction_mode
= mode
;
6412 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6413 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6414 pos_mode
= GET_MODE (pos_rtx
);
6416 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6417 if we have to change the mode of memory and cannot, the desired mode is
6420 wanted_inner_mode
= wanted_inner_reg_mode
;
6421 else if (inner_mode
!= wanted_inner_mode
6422 && (mode_dependent_address_p (XEXP (inner
, 0))
6423 || MEM_VOLATILE_P (inner
)))
6424 wanted_inner_mode
= extraction_mode
;
6428 if (BITS_BIG_ENDIAN
)
6430 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6431 BITS_BIG_ENDIAN style. If position is constant, compute new
6432 position. Otherwise, build subtraction.
6433 Note that POS is relative to the mode of the original argument.
6434 If it's a MEM we need to recompute POS relative to that.
6435 However, if we're extracting from (or inserting into) a register,
6436 we want to recompute POS relative to wanted_inner_mode. */
6437 int width
= (MEM_P (inner
)
6438 ? GET_MODE_BITSIZE (is_mode
)
6439 : GET_MODE_BITSIZE (wanted_inner_mode
));
6442 pos
= width
- len
- pos
;
6445 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6446 /* POS may be less than 0 now, but we check for that below.
6447 Note that it can only be less than 0 if !MEM_P (inner). */
6450 /* If INNER has a wider mode, make it smaller. If this is a constant
6451 extract, try to adjust the byte to point to the byte containing
6453 if (wanted_inner_mode
!= VOIDmode
6454 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6456 && (inner_mode
== wanted_inner_mode
6457 || (! mode_dependent_address_p (XEXP (inner
, 0))
6458 && ! MEM_VOLATILE_P (inner
))))))
6462 /* The computations below will be correct if the machine is big
6463 endian in both bits and bytes or little endian in bits and bytes.
6464 If it is mixed, we must adjust. */
6466 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6467 adjust OFFSET to compensate. */
6468 if (BYTES_BIG_ENDIAN
6470 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6471 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6473 /* If this is a constant position, we can move to the desired byte. */
6476 offset
+= pos
/ BITS_PER_UNIT
;
6477 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6480 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6482 && is_mode
!= wanted_inner_mode
)
6483 offset
= (GET_MODE_SIZE (is_mode
)
6484 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6486 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6487 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6490 /* If INNER is not memory, we can always get it into the proper mode. If we
6491 are changing its mode, POS must be a constant and smaller than the size
6493 else if (!MEM_P (inner
))
6495 if (GET_MODE (inner
) != wanted_inner_mode
6497 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6500 inner
= force_to_mode (inner
, wanted_inner_mode
,
6502 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6503 ? ~(unsigned HOST_WIDE_INT
) 0
6504 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6509 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6510 have to zero extend. Otherwise, we can just use a SUBREG. */
6512 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6514 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6516 /* If we know that no extraneous bits are set, and that the high
6517 bit is not set, convert extraction to cheaper one - either
6518 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6520 if (flag_expensive_optimizations
6521 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6522 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6523 & ~(((unsigned HOST_WIDE_INT
)
6524 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6528 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6530 /* Prefer ZERO_EXTENSION, since it gives more information to
6532 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6537 else if (pos_rtx
!= 0
6538 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6539 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6541 /* Make POS_RTX unless we already have it and it is correct. If we don't
6542 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6544 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6545 pos_rtx
= orig_pos_rtx
;
6547 else if (pos_rtx
== 0)
6548 pos_rtx
= GEN_INT (pos
);
6550 /* Make the required operation. See if we can use existing rtx. */
6551 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6552 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6554 new = gen_lowpart (mode
, new);
6559 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6560 with any other operations in X. Return X without that shift if so. */
6563 extract_left_shift (rtx x
, int count
)
6565 enum rtx_code code
= GET_CODE (x
);
6566 enum machine_mode mode
= GET_MODE (x
);
6572 /* This is the shift itself. If it is wide enough, we will return
6573 either the value being shifted if the shift count is equal to
6574 COUNT or a shift for the difference. */
6575 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6576 && INTVAL (XEXP (x
, 1)) >= count
)
6577 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6578 INTVAL (XEXP (x
, 1)) - count
);
6582 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6583 return simplify_gen_unary (code
, mode
, tem
, mode
);
6587 case PLUS
: case IOR
: case XOR
: case AND
:
6588 /* If we can safely shift this constant and we find the inner shift,
6589 make a new operation. */
6590 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6591 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6592 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6593 return simplify_gen_binary (code
, mode
, tem
,
6594 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6605 /* Look at the expression rooted at X. Look for expressions
6606 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6607 Form these expressions.
6609 Return the new rtx, usually just X.
6611 Also, for machines like the VAX that don't have logical shift insns,
6612 try to convert logical to arithmetic shift operations in cases where
6613 they are equivalent. This undoes the canonicalizations to logical
6614 shifts done elsewhere.
6616 We try, as much as possible, to re-use rtl expressions to save memory.
6618 IN_CODE says what kind of expression we are processing. Normally, it is
6619 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6620 being kludges), it is MEM. When processing the arguments of a comparison
6621 or a COMPARE against zero, it is COMPARE. */
6624 make_compound_operation (rtx x
, enum rtx_code in_code
)
6626 enum rtx_code code
= GET_CODE (x
);
6627 enum machine_mode mode
= GET_MODE (x
);
6628 int mode_width
= GET_MODE_BITSIZE (mode
);
6630 enum rtx_code next_code
;
6636 /* Select the code to be used in recursive calls. Once we are inside an
6637 address, we stay there. If we have a comparison, set to COMPARE,
6638 but once inside, go back to our default of SET. */
6640 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6641 : ((code
== COMPARE
|| COMPARISON_P (x
))
6642 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6643 : in_code
== COMPARE
? SET
: in_code
);
6645 /* Process depending on the code of this operation. If NEW is set
6646 nonzero, it will be returned. */
6651 /* Convert shifts by constants into multiplications if inside
6653 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6654 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6655 && INTVAL (XEXP (x
, 1)) >= 0)
6657 new = make_compound_operation (XEXP (x
, 0), next_code
);
6658 new = gen_rtx_MULT (mode
, new,
6659 GEN_INT ((HOST_WIDE_INT
) 1
6660 << INTVAL (XEXP (x
, 1))));
6665 /* If the second operand is not a constant, we can't do anything
6667 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6670 /* If the constant is a power of two minus one and the first operand
6671 is a logical right shift, make an extraction. */
6672 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6673 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6675 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6676 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6677 0, in_code
== COMPARE
);
6680 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6681 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6682 && subreg_lowpart_p (XEXP (x
, 0))
6683 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6684 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6686 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6688 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6689 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6690 0, in_code
== COMPARE
);
6692 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6693 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6694 || GET_CODE (XEXP (x
, 0)) == IOR
)
6695 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6696 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6697 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6699 /* Apply the distributive law, and then try to make extractions. */
6700 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6701 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6703 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6705 new = make_compound_operation (new, in_code
);
6708 /* If we are have (and (rotate X C) M) and C is larger than the number
6709 of bits in M, this is an extraction. */
6711 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6712 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6713 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6714 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6716 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6717 new = make_extraction (mode
, new,
6718 (GET_MODE_BITSIZE (mode
)
6719 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6720 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6723 /* On machines without logical shifts, if the operand of the AND is
6724 a logical shift and our mask turns off all the propagated sign
6725 bits, we can replace the logical shift with an arithmetic shift. */
6726 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6727 && !have_insn_for (LSHIFTRT
, mode
)
6728 && have_insn_for (ASHIFTRT
, mode
)
6729 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6730 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6731 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6732 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6734 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6736 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6737 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6739 gen_rtx_ASHIFTRT (mode
,
6740 make_compound_operation
6741 (XEXP (XEXP (x
, 0), 0), next_code
),
6742 XEXP (XEXP (x
, 0), 1)));
6745 /* If the constant is one less than a power of two, this might be
6746 representable by an extraction even if no shift is present.
6747 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6748 we are in a COMPARE. */
6749 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6750 new = make_extraction (mode
,
6751 make_compound_operation (XEXP (x
, 0),
6753 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6755 /* If we are in a comparison and this is an AND with a power of two,
6756 convert this into the appropriate bit extract. */
6757 else if (in_code
== COMPARE
6758 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6759 new = make_extraction (mode
,
6760 make_compound_operation (XEXP (x
, 0),
6762 i
, NULL_RTX
, 1, 1, 0, 1);
6767 /* If the sign bit is known to be zero, replace this with an
6768 arithmetic shift. */
6769 if (have_insn_for (ASHIFTRT
, mode
)
6770 && ! have_insn_for (LSHIFTRT
, mode
)
6771 && mode_width
<= HOST_BITS_PER_WIDE_INT
6772 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6774 new = gen_rtx_ASHIFTRT (mode
,
6775 make_compound_operation (XEXP (x
, 0),
6781 /* ... fall through ... */
6787 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6788 this is a SIGN_EXTRACT. */
6789 if (GET_CODE (rhs
) == CONST_INT
6790 && GET_CODE (lhs
) == ASHIFT
6791 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6792 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6794 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6795 new = make_extraction (mode
, new,
6796 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6797 NULL_RTX
, mode_width
- INTVAL (rhs
),
6798 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6802 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6803 If so, try to merge the shifts into a SIGN_EXTEND. We could
6804 also do this for some cases of SIGN_EXTRACT, but it doesn't
6805 seem worth the effort; the case checked for occurs on Alpha. */
6808 && ! (GET_CODE (lhs
) == SUBREG
6809 && (OBJECT_P (SUBREG_REG (lhs
))))
6810 && GET_CODE (rhs
) == CONST_INT
6811 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6812 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6813 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6814 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6815 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6820 /* Call ourselves recursively on the inner expression. If we are
6821 narrowing the object and it has a different RTL code from
6822 what it originally did, do this SUBREG as a force_to_mode. */
6824 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6828 simplified
= simplify_subreg (GET_MODE (x
), tem
, GET_MODE (tem
),
6834 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6835 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6836 && subreg_lowpart_p (x
))
6838 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6841 /* If we have something other than a SUBREG, we might have
6842 done an expansion, so rerun ourselves. */
6843 if (GET_CODE (newer
) != SUBREG
)
6844 newer
= make_compound_operation (newer
, in_code
);
6860 x
= gen_lowpart (mode
, new);
6861 code
= GET_CODE (x
);
6864 /* Now recursively process each operand of this operation. */
6865 fmt
= GET_RTX_FORMAT (code
);
6866 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6869 new = make_compound_operation (XEXP (x
, i
), next_code
);
6870 SUBST (XEXP (x
, i
), new);
6876 /* Given M see if it is a value that would select a field of bits
6877 within an item, but not the entire word. Return -1 if not.
6878 Otherwise, return the starting position of the field, where 0 is the
6881 *PLEN is set to the length of the field. */
6884 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6886 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6887 int pos
= exact_log2 (m
& -m
);
6891 /* Now shift off the low-order zero bits and see if we have a
6892 power of two minus 1. */
6893 len
= exact_log2 ((m
>> pos
) + 1);
6902 /* See if X can be simplified knowing that we will only refer to it in
6903 MODE and will only refer to those bits that are nonzero in MASK.
6904 If other bits are being computed or if masking operations are done
6905 that select a superset of the bits in MASK, they can sometimes be
6908 Return a possibly simplified expression, but always convert X to
6909 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6911 Also, if REG is nonzero and X is a register equal in value to REG,
6914 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6915 are all off in X. This is used when X will be complemented, by either
6916 NOT, NEG, or XOR. */
6919 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6920 rtx reg
, int just_select
)
6922 enum rtx_code code
= GET_CODE (x
);
6923 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6924 enum machine_mode op_mode
;
6925 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6928 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6929 code below will do the wrong thing since the mode of such an
6930 expression is VOIDmode.
6932 Also do nothing if X is a CLOBBER; this can happen if X was
6933 the return value from a call to gen_lowpart. */
6934 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6937 /* We want to perform the operation is its present mode unless we know
6938 that the operation is valid in MODE, in which case we do the operation
6940 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6941 && have_insn_for (code
, mode
))
6942 ? mode
: GET_MODE (x
));
6944 /* It is not valid to do a right-shift in a narrower mode
6945 than the one it came in with. */
6946 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6947 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6948 op_mode
= GET_MODE (x
);
6950 /* Truncate MASK to fit OP_MODE. */
6952 mask
&= GET_MODE_MASK (op_mode
);
6954 /* When we have an arithmetic operation, or a shift whose count we
6955 do not know, we need to assume that all bits up to the highest-order
6956 bit in MASK will be needed. This is how we form such a mask. */
6957 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6958 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6960 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6963 /* Determine what bits of X are guaranteed to be (non)zero. */
6964 nonzero
= nonzero_bits (x
, mode
);
6966 /* If none of the bits in X are needed, return a zero. */
6967 if (! just_select
&& (nonzero
& mask
) == 0)
6970 /* If X is a CONST_INT, return a new one. Do this here since the
6971 test below will fail. */
6972 if (GET_CODE (x
) == CONST_INT
)
6974 if (SCALAR_INT_MODE_P (mode
))
6975 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6978 x
= GEN_INT (INTVAL (x
) & mask
);
6979 return gen_lowpart_common (mode
, x
);
6983 /* If X is narrower than MODE and we want all the bits in X's mode, just
6984 get X in the proper mode. */
6985 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6986 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6987 return gen_lowpart (mode
, x
);
6992 /* If X is a (clobber (const_int)), return it since we know we are
6993 generating something that won't match. */
6997 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6998 spanned the boundary of the MEM. If we are now masking so it is
6999 within that boundary, we don't need the USE any more. */
7000 if (! BITS_BIG_ENDIAN
7001 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7002 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7009 x
= expand_compound_operation (x
);
7010 if (GET_CODE (x
) != code
)
7011 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7015 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
7016 || rtx_equal_p (reg
, get_last_value (x
))))
7021 if (subreg_lowpart_p (x
)
7022 /* We can ignore the effect of this SUBREG if it narrows the mode or
7023 if the constant masks to zero all the bits the mode doesn't
7025 && ((GET_MODE_SIZE (GET_MODE (x
))
7026 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
7028 & GET_MODE_MASK (GET_MODE (x
))
7029 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
7030 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
7034 /* If this is an AND with a constant, convert it into an AND
7035 whose constant is the AND of that constant with MASK. If it
7036 remains an AND of MASK, delete it since it is redundant. */
7038 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7040 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
7041 mask
& INTVAL (XEXP (x
, 1)));
7043 /* If X is still an AND, see if it is an AND with a mask that
7044 is just some low-order bits. If so, and it is MASK, we don't
7047 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
7048 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
7052 /* If it remains an AND, try making another AND with the bits
7053 in the mode mask that aren't in MASK turned on. If the
7054 constant in the AND is wide enough, this might make a
7055 cheaper constant. */
7057 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
7058 && GET_MODE_MASK (GET_MODE (x
)) != mask
7059 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
7061 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
7062 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
7063 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
7066 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7067 number, sign extend it. */
7068 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
7069 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7070 cval
|= (HOST_WIDE_INT
) -1 << width
;
7072 y
= simplify_gen_binary (AND
, GET_MODE (x
),
7073 XEXP (x
, 0), GEN_INT (cval
));
7074 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
7084 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7085 low-order bits (as in an alignment operation) and FOO is already
7086 aligned to that boundary, mask C1 to that boundary as well.
7087 This may eliminate that PLUS and, later, the AND. */
7090 unsigned int width
= GET_MODE_BITSIZE (mode
);
7091 unsigned HOST_WIDE_INT smask
= mask
;
7093 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7094 number, sign extend it. */
7096 if (width
< HOST_BITS_PER_WIDE_INT
7097 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7098 smask
|= (HOST_WIDE_INT
) -1 << width
;
7100 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7101 && exact_log2 (- smask
) >= 0
7102 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
7103 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
7104 return force_to_mode (plus_constant (XEXP (x
, 0),
7105 (INTVAL (XEXP (x
, 1)) & smask
)),
7106 mode
, smask
, reg
, next_select
);
7109 /* ... fall through ... */
7112 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7113 most significant bit in MASK since carries from those bits will
7114 affect the bits we are interested in. */
7119 /* If X is (minus C Y) where C's least set bit is larger than any bit
7120 in the mask, then we may replace with (neg Y). */
7121 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7122 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
7123 & -INTVAL (XEXP (x
, 0))))
7126 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
7128 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7131 /* Similarly, if C contains every bit in the fuller_mask, then we may
7132 replace with (not Y). */
7133 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7134 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
7135 == INTVAL (XEXP (x
, 0))))
7137 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
7138 XEXP (x
, 1), GET_MODE (x
));
7139 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7147 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7148 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7149 operation which may be a bitfield extraction. Ensure that the
7150 constant we form is not wider than the mode of X. */
7152 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7153 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7154 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7155 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7156 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7157 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
7158 + floor_log2 (INTVAL (XEXP (x
, 1))))
7159 < GET_MODE_BITSIZE (GET_MODE (x
)))
7160 && (INTVAL (XEXP (x
, 1))
7161 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7163 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7164 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7165 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
7166 XEXP (XEXP (x
, 0), 0), temp
);
7167 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7168 XEXP (XEXP (x
, 0), 1));
7169 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7173 /* For most binary operations, just propagate into the operation and
7174 change the mode if we have an operation of that mode. */
7176 op0
= gen_lowpart (op_mode
,
7177 force_to_mode (XEXP (x
, 0), mode
, mask
,
7179 op1
= gen_lowpart (op_mode
,
7180 force_to_mode (XEXP (x
, 1), mode
, mask
,
7183 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7184 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
7188 /* For left shifts, do the same, but just for the first operand.
7189 However, we cannot do anything with shifts where we cannot
7190 guarantee that the counts are smaller than the size of the mode
7191 because such a count will have a different meaning in a
7194 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7195 && INTVAL (XEXP (x
, 1)) >= 0
7196 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7197 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7198 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7199 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7202 /* If the shift count is a constant and we can do arithmetic in
7203 the mode of the shift, refine which bits we need. Otherwise, use the
7204 conservative form of the mask. */
7205 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7206 && INTVAL (XEXP (x
, 1)) >= 0
7207 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7208 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7209 mask
>>= INTVAL (XEXP (x
, 1));
7213 op0
= gen_lowpart (op_mode
,
7214 force_to_mode (XEXP (x
, 0), op_mode
,
7215 mask
, reg
, next_select
));
7217 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7218 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7222 /* Here we can only do something if the shift count is a constant,
7223 this shift constant is valid for the host, and we can do arithmetic
7226 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7227 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7228 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7230 rtx inner
= XEXP (x
, 0);
7231 unsigned HOST_WIDE_INT inner_mask
;
7233 /* Select the mask of the bits we need for the shift operand. */
7234 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7236 /* We can only change the mode of the shift if we can do arithmetic
7237 in the mode of the shift and INNER_MASK is no wider than the
7238 width of X's mode. */
7239 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
7240 op_mode
= GET_MODE (x
);
7242 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7244 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7245 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7248 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7249 shift and AND produces only copies of the sign bit (C2 is one less
7250 than a power of two), we can do this with just a shift. */
7252 if (GET_CODE (x
) == LSHIFTRT
7253 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7254 /* The shift puts one of the sign bit copies in the least significant
7256 && ((INTVAL (XEXP (x
, 1))
7257 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7258 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7259 && exact_log2 (mask
+ 1) >= 0
7260 /* Number of bits left after the shift must be more than the mask
7262 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7263 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7264 /* Must be more sign bit copies than the mask needs. */
7265 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7266 >= exact_log2 (mask
+ 1)))
7267 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7268 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7269 - exact_log2 (mask
+ 1)));
7274 /* If we are just looking for the sign bit, we don't need this shift at
7275 all, even if it has a variable count. */
7276 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7277 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7278 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7279 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7281 /* If this is a shift by a constant, get a mask that contains those bits
7282 that are not copies of the sign bit. We then have two cases: If
7283 MASK only includes those bits, this can be a logical shift, which may
7284 allow simplifications. If MASK is a single-bit field not within
7285 those bits, we are requesting a copy of the sign bit and hence can
7286 shift the sign bit to the appropriate location. */
7288 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7289 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7293 /* If the considered data is wider than HOST_WIDE_INT, we can't
7294 represent a mask for all its bits in a single scalar.
7295 But we only care about the lower bits, so calculate these. */
7297 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7299 nonzero
= ~(HOST_WIDE_INT
) 0;
7301 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7302 is the number of bits a full-width mask would have set.
7303 We need only shift if these are fewer than nonzero can
7304 hold. If not, we must keep all bits set in nonzero. */
7306 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7307 < HOST_BITS_PER_WIDE_INT
)
7308 nonzero
>>= INTVAL (XEXP (x
, 1))
7309 + HOST_BITS_PER_WIDE_INT
7310 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7314 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7315 nonzero
>>= INTVAL (XEXP (x
, 1));
7318 if ((mask
& ~nonzero
) == 0
7319 || (i
= exact_log2 (mask
)) >= 0)
7321 x
= simplify_shift_const
7322 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7323 i
< 0 ? INTVAL (XEXP (x
, 1))
7324 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7326 if (GET_CODE (x
) != ASHIFTRT
)
7327 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7331 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7332 even if the shift count isn't a constant. */
7334 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
7335 XEXP (x
, 0), XEXP (x
, 1));
7339 /* If this is a zero- or sign-extension operation that just affects bits
7340 we don't care about, remove it. Be sure the call above returned
7341 something that is still a shift. */
7343 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7344 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7345 && INTVAL (XEXP (x
, 1)) >= 0
7346 && (INTVAL (XEXP (x
, 1))
7347 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7348 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7349 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7350 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7357 /* If the shift count is constant and we can do computations
7358 in the mode of X, compute where the bits we care about are.
7359 Otherwise, we can't do anything. Don't change the mode of
7360 the shift or propagate MODE into the shift, though. */
7361 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7362 && INTVAL (XEXP (x
, 1)) >= 0)
7364 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7365 GET_MODE (x
), GEN_INT (mask
),
7367 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7369 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7370 INTVAL (temp
), reg
, next_select
));
7375 /* If we just want the low-order bit, the NEG isn't needed since it
7376 won't change the low-order bit. */
7378 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7380 /* We need any bits less significant than the most significant bit in
7381 MASK since carries from those bits will affect the bits we are
7387 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7388 same as the XOR case above. Ensure that the constant we form is not
7389 wider than the mode of X. */
7391 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7392 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7393 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7394 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7395 < GET_MODE_BITSIZE (GET_MODE (x
)))
7396 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7398 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7400 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
7401 XEXP (XEXP (x
, 0), 0), temp
);
7402 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
7403 temp
, XEXP (XEXP (x
, 0), 1));
7405 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7408 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7409 use the full mask inside the NOT. */
7413 op0
= gen_lowpart (op_mode
,
7414 force_to_mode (XEXP (x
, 0), mode
, mask
,
7416 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7417 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7421 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7422 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7423 which is equal to STORE_FLAG_VALUE. */
7424 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7425 && GET_MODE (XEXP (x
, 0)) == mode
7426 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7427 && (nonzero_bits (XEXP (x
, 0), mode
)
7428 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7429 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7434 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7435 written in a narrower mode. We play it safe and do not do so. */
7438 gen_lowpart (GET_MODE (x
),
7439 force_to_mode (XEXP (x
, 1), mode
,
7440 mask
, reg
, next_select
)));
7442 gen_lowpart (GET_MODE (x
),
7443 force_to_mode (XEXP (x
, 2), mode
,
7444 mask
, reg
, next_select
)));
7451 /* Ensure we return a value of the proper mode. */
7452 return gen_lowpart (mode
, x
);
7455 /* Return nonzero if X is an expression that has one of two values depending on
7456 whether some other value is zero or nonzero. In that case, we return the
7457 value that is being tested, *PTRUE is set to the value if the rtx being
7458 returned has a nonzero value, and *PFALSE is set to the other alternative.
7460 If we return zero, we set *PTRUE and *PFALSE to X. */
7463 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7465 enum machine_mode mode
= GET_MODE (x
);
7466 enum rtx_code code
= GET_CODE (x
);
7467 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7468 unsigned HOST_WIDE_INT nz
;
7470 /* If we are comparing a value against zero, we are done. */
7471 if ((code
== NE
|| code
== EQ
)
7472 && XEXP (x
, 1) == const0_rtx
)
7474 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7475 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7479 /* If this is a unary operation whose operand has one of two values, apply
7480 our opcode to compute those values. */
7481 else if (UNARY_P (x
)
7482 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7484 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7485 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7486 GET_MODE (XEXP (x
, 0)));
7490 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7491 make can't possibly match and would suppress other optimizations. */
7492 else if (code
== COMPARE
)
7495 /* If this is a binary operation, see if either side has only one of two
7496 values. If either one does or if both do and they are conditional on
7497 the same value, compute the new true and false values. */
7498 else if (BINARY_P (x
))
7500 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7501 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7503 if ((cond0
!= 0 || cond1
!= 0)
7504 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7506 /* If if_then_else_cond returned zero, then true/false are the
7507 same rtl. We must copy one of them to prevent invalid rtl
7510 true0
= copy_rtx (true0
);
7511 else if (cond1
== 0)
7512 true1
= copy_rtx (true1
);
7514 if (COMPARISON_P (x
))
7516 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
7518 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
7523 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
7524 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
7527 return cond0
? cond0
: cond1
;
7530 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7531 operands is zero when the other is nonzero, and vice-versa,
7532 and STORE_FLAG_VALUE is 1 or -1. */
7534 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7535 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7537 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7539 rtx op0
= XEXP (XEXP (x
, 0), 1);
7540 rtx op1
= XEXP (XEXP (x
, 1), 1);
7542 cond0
= XEXP (XEXP (x
, 0), 0);
7543 cond1
= XEXP (XEXP (x
, 1), 0);
7545 if (COMPARISON_P (cond0
)
7546 && COMPARISON_P (cond1
)
7547 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
7548 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7549 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7550 || ((swap_condition (GET_CODE (cond0
))
7551 == reversed_comparison_code (cond1
, NULL
))
7552 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7553 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7554 && ! side_effects_p (x
))
7556 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7557 *pfalse
= simplify_gen_binary (MULT
, mode
,
7559 ? simplify_gen_unary (NEG
, mode
,
7567 /* Similarly for MULT, AND and UMIN, except that for these the result
7569 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7570 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7571 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7573 cond0
= XEXP (XEXP (x
, 0), 0);
7574 cond1
= XEXP (XEXP (x
, 1), 0);
7576 if (COMPARISON_P (cond0
)
7577 && COMPARISON_P (cond1
)
7578 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
7579 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7580 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7581 || ((swap_condition (GET_CODE (cond0
))
7582 == reversed_comparison_code (cond1
, NULL
))
7583 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7584 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7585 && ! side_effects_p (x
))
7587 *ptrue
= *pfalse
= const0_rtx
;
7593 else if (code
== IF_THEN_ELSE
)
7595 /* If we have IF_THEN_ELSE already, extract the condition and
7596 canonicalize it if it is NE or EQ. */
7597 cond0
= XEXP (x
, 0);
7598 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7599 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7600 return XEXP (cond0
, 0);
7601 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7603 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7604 return XEXP (cond0
, 0);
7610 /* If X is a SUBREG, we can narrow both the true and false values
7611 if the inner expression, if there is a condition. */
7612 else if (code
== SUBREG
7613 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7616 true0
= simplify_gen_subreg (mode
, true0
,
7617 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7618 false0
= simplify_gen_subreg (mode
, false0
,
7619 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7620 if (true0
&& false0
)
7628 /* If X is a constant, this isn't special and will cause confusions
7629 if we treat it as such. Likewise if it is equivalent to a constant. */
7630 else if (CONSTANT_P (x
)
7631 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7634 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7635 will be least confusing to the rest of the compiler. */
7636 else if (mode
== BImode
)
7638 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7642 /* If X is known to be either 0 or -1, those are the true and
7643 false values when testing X. */
7644 else if (x
== constm1_rtx
|| x
== const0_rtx
7645 || (mode
!= VOIDmode
7646 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7648 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7652 /* Likewise for 0 or a single bit. */
7653 else if (SCALAR_INT_MODE_P (mode
)
7654 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7655 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7657 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7661 /* Otherwise fail; show no condition with true and false values the same. */
7662 *ptrue
= *pfalse
= x
;
7666 /* Return the value of expression X given the fact that condition COND
7667 is known to be true when applied to REG as its first operand and VAL
7668 as its second. X is known to not be shared and so can be modified in
7671 We only handle the simplest cases, and specifically those cases that
7672 arise with IF_THEN_ELSE expressions. */
7675 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7677 enum rtx_code code
= GET_CODE (x
);
7682 if (side_effects_p (x
))
7685 /* If either operand of the condition is a floating point value,
7686 then we have to avoid collapsing an EQ comparison. */
7688 && rtx_equal_p (x
, reg
)
7689 && ! FLOAT_MODE_P (GET_MODE (x
))
7690 && ! FLOAT_MODE_P (GET_MODE (val
)))
7693 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7696 /* If X is (abs REG) and we know something about REG's relationship
7697 with zero, we may be able to simplify this. */
7699 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7702 case GE
: case GT
: case EQ
:
7705 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7707 GET_MODE (XEXP (x
, 0)));
7712 /* The only other cases we handle are MIN, MAX, and comparisons if the
7713 operands are the same as REG and VAL. */
7715 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
7717 if (rtx_equal_p (XEXP (x
, 0), val
))
7718 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7720 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7722 if (COMPARISON_P (x
))
7724 if (comparison_dominates_p (cond
, code
))
7725 return const_true_rtx
;
7727 code
= reversed_comparison_code (x
, NULL
);
7729 && comparison_dominates_p (cond
, code
))
7734 else if (code
== SMAX
|| code
== SMIN
7735 || code
== UMIN
|| code
== UMAX
)
7737 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7739 /* Do not reverse the condition when it is NE or EQ.
7740 This is because we cannot conclude anything about
7741 the value of 'SMAX (x, y)' when x is not equal to y,
7742 but we can when x equals y. */
7743 if ((code
== SMAX
|| code
== UMAX
)
7744 && ! (cond
== EQ
|| cond
== NE
))
7745 cond
= reverse_condition (cond
);
7750 return unsignedp
? x
: XEXP (x
, 1);
7752 return unsignedp
? x
: XEXP (x
, 0);
7754 return unsignedp
? XEXP (x
, 1) : x
;
7756 return unsignedp
? XEXP (x
, 0) : x
;
7763 else if (code
== SUBREG
)
7765 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7766 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7768 if (SUBREG_REG (x
) != r
)
7770 /* We must simplify subreg here, before we lose track of the
7771 original inner_mode. */
7772 new = simplify_subreg (GET_MODE (x
), r
,
7773 inner_mode
, SUBREG_BYTE (x
));
7777 SUBST (SUBREG_REG (x
), r
);
7782 /* We don't have to handle SIGN_EXTEND here, because even in the
7783 case of replacing something with a modeless CONST_INT, a
7784 CONST_INT is already (supposed to be) a valid sign extension for
7785 its narrower mode, which implies it's already properly
7786 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7787 story is different. */
7788 else if (code
== ZERO_EXTEND
)
7790 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7791 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7793 if (XEXP (x
, 0) != r
)
7795 /* We must simplify the zero_extend here, before we lose
7796 track of the original inner_mode. */
7797 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7802 SUBST (XEXP (x
, 0), r
);
7808 fmt
= GET_RTX_FORMAT (code
);
7809 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7812 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7813 else if (fmt
[i
] == 'E')
7814 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7815 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7822 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7823 assignment as a field assignment. */
7826 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7828 if (x
== y
|| rtx_equal_p (x
, y
))
7831 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7834 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7835 Note that all SUBREGs of MEM are paradoxical; otherwise they
7836 would have been rewritten. */
7837 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
7838 && MEM_P (SUBREG_REG (y
))
7839 && rtx_equal_p (SUBREG_REG (y
),
7840 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
7843 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
7844 && MEM_P (SUBREG_REG (x
))
7845 && rtx_equal_p (SUBREG_REG (x
),
7846 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
7849 /* We used to see if get_last_value of X and Y were the same but that's
7850 not correct. In one direction, we'll cause the assignment to have
7851 the wrong destination and in the case, we'll import a register into this
7852 insn that might have already have been dead. So fail if none of the
7853 above cases are true. */
7857 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7858 Return that assignment if so.
7860 We only handle the most common cases. */
7863 make_field_assignment (rtx x
)
7865 rtx dest
= SET_DEST (x
);
7866 rtx src
= SET_SRC (x
);
7871 unsigned HOST_WIDE_INT len
;
7873 enum machine_mode mode
;
7875 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7876 a clear of a one-bit field. We will have changed it to
7877 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7880 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7881 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7882 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7883 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7885 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7888 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7892 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7893 && subreg_lowpart_p (XEXP (src
, 0))
7894 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7895 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7896 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7897 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7898 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7899 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7901 assign
= make_extraction (VOIDmode
, dest
, 0,
7902 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7905 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7909 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7911 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7912 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7913 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7915 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7918 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7922 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7923 SRC is an AND with all bits of that field set, then we can discard
7925 if (GET_CODE (dest
) == ZERO_EXTRACT
7926 && GET_CODE (XEXP (dest
, 1)) == CONST_INT
7927 && GET_CODE (src
) == AND
7928 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
7930 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
7931 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
7932 unsigned HOST_WIDE_INT ze_mask
;
7934 if (width
>= HOST_BITS_PER_WIDE_INT
)
7937 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
7939 /* Complete overlap. We can remove the source AND. */
7940 if ((and_mask
& ze_mask
) == ze_mask
)
7941 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
7943 /* Partial overlap. We can reduce the source AND. */
7944 if ((and_mask
& ze_mask
) != and_mask
)
7946 mode
= GET_MODE (src
);
7947 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
7948 gen_int_mode (and_mask
& ze_mask
, mode
));
7949 return gen_rtx_SET (VOIDmode
, dest
, src
);
7953 /* The other case we handle is assignments into a constant-position
7954 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7955 a mask that has all one bits except for a group of zero bits and
7956 OTHER is known to have zeros where C1 has ones, this is such an
7957 assignment. Compute the position and length from C1. Shift OTHER
7958 to the appropriate position, force it to the required mode, and
7959 make the extraction. Check for the AND in both operands. */
7961 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7964 rhs
= expand_compound_operation (XEXP (src
, 0));
7965 lhs
= expand_compound_operation (XEXP (src
, 1));
7967 if (GET_CODE (rhs
) == AND
7968 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7969 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7970 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7971 else if (GET_CODE (lhs
) == AND
7972 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7973 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7974 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7978 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7979 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7980 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7981 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7984 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7988 /* The mode to use for the source is the mode of the assignment, or of
7989 what is inside a possible STRICT_LOW_PART. */
7990 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7991 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7993 /* Shift OTHER right POS places and make it the source, restricting it
7994 to the proper length and mode. */
7996 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7997 GET_MODE (src
), other
, pos
),
7999 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
8000 ? ~(unsigned HOST_WIDE_INT
) 0
8001 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
8004 /* If SRC is masked by an AND that does not make a difference in
8005 the value being stored, strip it. */
8006 if (GET_CODE (assign
) == ZERO_EXTRACT
8007 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
8008 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
8009 && GET_CODE (src
) == AND
8010 && GET_CODE (XEXP (src
, 1)) == CONST_INT
8011 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
8012 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
8013 src
= XEXP (src
, 0);
8015 return gen_rtx_SET (VOIDmode
, assign
, src
);
8018 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8022 apply_distributive_law (rtx x
)
8024 enum rtx_code code
= GET_CODE (x
);
8025 enum rtx_code inner_code
;
8026 rtx lhs
, rhs
, other
;
8029 /* Distributivity is not true for floating point as it can change the
8030 value. So we don't do it unless -funsafe-math-optimizations. */
8031 if (FLOAT_MODE_P (GET_MODE (x
))
8032 && ! flag_unsafe_math_optimizations
)
8035 /* The outer operation can only be one of the following: */
8036 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
8037 && code
!= PLUS
&& code
!= MINUS
)
8043 /* If either operand is a primitive we can't do anything, so get out
8045 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
8048 lhs
= expand_compound_operation (lhs
);
8049 rhs
= expand_compound_operation (rhs
);
8050 inner_code
= GET_CODE (lhs
);
8051 if (inner_code
!= GET_CODE (rhs
))
8054 /* See if the inner and outer operations distribute. */
8061 /* These all distribute except over PLUS. */
8062 if (code
== PLUS
|| code
== MINUS
)
8067 if (code
!= PLUS
&& code
!= MINUS
)
8072 /* This is also a multiply, so it distributes over everything. */
8076 /* Non-paradoxical SUBREGs distributes over all operations, provided
8077 the inner modes and byte offsets are the same, this is an extraction
8078 of a low-order part, we don't convert an fp operation to int or
8079 vice versa, and we would not be converting a single-word
8080 operation into a multi-word operation. The latter test is not
8081 required, but it prevents generating unneeded multi-word operations.
8082 Some of the previous tests are redundant given the latter test, but
8083 are retained because they are required for correctness.
8085 We produce the result slightly differently in this case. */
8087 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
8088 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
8089 || ! subreg_lowpart_p (lhs
)
8090 || (GET_MODE_CLASS (GET_MODE (lhs
))
8091 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
8092 || (GET_MODE_SIZE (GET_MODE (lhs
))
8093 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
8094 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
8097 tem
= simplify_gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
8098 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
8099 return gen_lowpart (GET_MODE (x
), tem
);
8105 /* Set LHS and RHS to the inner operands (A and B in the example
8106 above) and set OTHER to the common operand (C in the example).
8107 There is only one way to do this unless the inner operation is
8109 if (COMMUTATIVE_ARITH_P (lhs
)
8110 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
8111 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
8112 else if (COMMUTATIVE_ARITH_P (lhs
)
8113 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
8114 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
8115 else if (COMMUTATIVE_ARITH_P (lhs
)
8116 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
8117 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
8118 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
8119 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
8123 /* Form the new inner operation, seeing if it simplifies first. */
8124 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
8126 /* There is one exception to the general way of distributing:
8127 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8128 if (code
== XOR
&& inner_code
== IOR
)
8131 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
8134 /* We may be able to continuing distributing the result, so call
8135 ourselves recursively on the inner operation before forming the
8136 outer operation, which we return. */
8137 return simplify_gen_binary (inner_code
, GET_MODE (x
),
8138 apply_distributive_law (tem
), other
);
8141 /* See if X is of the form (* (+ A B) C), and if so convert to
8142 (+ (* A C) (* B C)) and try to simplify.
8144 Most of the time, this results in no change. However, if some of
8145 the operands are the same or inverses of each other, simplifications
8148 For example, (and (ior A B) (not B)) can occur as the result of
8149 expanding a bit field assignment. When we apply the distributive
8150 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8151 which then simplifies to (and (A (not B))).
8153 Note that no checks happen on the validity of applying the inverse
8154 distributive law. This is pointless since we can do it in the
8155 few places where this routine is called.
8157 N is the index of the term that is decomposed (the arithmetic operation,
8158 i.e. (+ A B) in the first example above). !N is the index of the term that
8159 is distributed, i.e. of C in the first example above. */
8161 distribute_and_simplify_rtx (rtx x
, int n
)
8163 enum machine_mode mode
;
8164 enum rtx_code outer_code
, inner_code
;
8165 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
8167 decomposed
= XEXP (x
, n
);
8168 if (!ARITHMETIC_P (decomposed
))
8171 mode
= GET_MODE (x
);
8172 outer_code
= GET_CODE (x
);
8173 distributed
= XEXP (x
, !n
);
8175 inner_code
= GET_CODE (decomposed
);
8176 inner_op0
= XEXP (decomposed
, 0);
8177 inner_op1
= XEXP (decomposed
, 1);
8179 /* Special case (and (xor B C) (not A)), which is equivalent to
8180 (xor (ior A B) (ior A C)) */
8181 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
8183 distributed
= XEXP (distributed
, 0);
8189 /* Distribute the second term. */
8190 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
8191 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
8195 /* Distribute the first term. */
8196 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
8197 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
8200 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
8202 if (GET_CODE (tmp
) != outer_code
8203 && rtx_cost (tmp
, SET
) < rtx_cost (x
, SET
))
8209 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8212 Return an equivalent form, if different from X. Otherwise, return X. If
8213 X is zero, we are to always construct the equivalent form. */
8216 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
8217 unsigned HOST_WIDE_INT constop
)
8219 unsigned HOST_WIDE_INT nonzero
;
8222 /* Simplify VAROP knowing that we will be only looking at some of the
8225 Note by passing in CONSTOP, we guarantee that the bits not set in
8226 CONSTOP are not significant and will never be examined. We must
8227 ensure that is the case by explicitly masking out those bits
8228 before returning. */
8229 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
8231 /* If VAROP is a CLOBBER, we will fail so return it. */
8232 if (GET_CODE (varop
) == CLOBBER
)
8235 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8236 to VAROP and return the new constant. */
8237 if (GET_CODE (varop
) == CONST_INT
)
8238 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
8240 /* See what bits may be nonzero in VAROP. Unlike the general case of
8241 a call to nonzero_bits, here we don't care about bits outside
8244 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
8246 /* Turn off all bits in the constant that are known to already be zero.
8247 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8248 which is tested below. */
8252 /* If we don't have any bits left, return zero. */
8256 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8257 a power of two, we can replace this with an ASHIFT. */
8258 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
8259 && (i
= exact_log2 (constop
)) >= 0)
8260 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
8262 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8263 or XOR, then try to apply the distributive law. This may eliminate
8264 operations if either branch can be simplified because of the AND.
8265 It may also make some cases more complex, but those cases probably
8266 won't match a pattern either with or without this. */
8268 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
8272 apply_distributive_law
8273 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
8274 simplify_and_const_int (NULL_RTX
,
8278 simplify_and_const_int (NULL_RTX
,
8283 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8284 the AND and see if one of the operands simplifies to zero. If so, we
8285 may eliminate it. */
8287 if (GET_CODE (varop
) == PLUS
8288 && exact_log2 (constop
+ 1) >= 0)
8292 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8293 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8294 if (o0
== const0_rtx
)
8296 if (o1
== const0_rtx
)
8300 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8301 if we already had one (just check for the simplest cases). */
8302 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
8303 && GET_MODE (XEXP (x
, 0)) == mode
8304 && SUBREG_REG (XEXP (x
, 0)) == varop
)
8305 varop
= XEXP (x
, 0);
8307 varop
= gen_lowpart (mode
, varop
);
8309 /* If we can't make the SUBREG, try to return what we were given. */
8310 if (GET_CODE (varop
) == CLOBBER
)
8311 return x
? x
: varop
;
8313 /* If we are only masking insignificant bits, return VAROP. */
8314 if (constop
== nonzero
)
8318 /* Otherwise, return an AND. */
8319 constop
= trunc_int_for_mode (constop
, mode
);
8320 /* See how much, if any, of X we can use. */
8321 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
8322 x
= simplify_gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8326 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8327 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8328 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8330 SUBST (XEXP (x
, 0), varop
);
8337 /* Given a REG, X, compute which bits in X can be nonzero.
8338 We don't care about bits outside of those defined in MODE.
8340 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8341 a shift, AND, or zero_extract, we can do better. */
8344 reg_nonzero_bits_for_combine (rtx x
, enum machine_mode mode
,
8345 rtx known_x ATTRIBUTE_UNUSED
,
8346 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
8347 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
8348 unsigned HOST_WIDE_INT
*nonzero
)
8352 /* If X is a register whose nonzero bits value is current, use it.
8353 Otherwise, if X is a register whose value we can find, use that
8354 value. Otherwise, use the previously-computed global nonzero bits
8355 for this register. */
8357 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8358 && (reg_stat
[REGNO (x
)].last_set_mode
== mode
8359 || (GET_MODE_CLASS (reg_stat
[REGNO (x
)].last_set_mode
) == MODE_INT
8360 && GET_MODE_CLASS (mode
) == MODE_INT
))
8361 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8362 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8363 && REG_N_SETS (REGNO (x
)) == 1
8364 && ! REGNO_REG_SET_P
8365 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
,
8367 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8369 *nonzero
&= reg_stat
[REGNO (x
)].last_set_nonzero_bits
;
8373 tem
= get_last_value (x
);
8377 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8378 /* If X is narrower than MODE and TEM is a non-negative
8379 constant that would appear negative in the mode of X,
8380 sign-extend it for use in reg_nonzero_bits because some
8381 machines (maybe most) will actually do the sign-extension
8382 and this is the conservative approach.
8384 ??? For 2.5, try to tighten up the MD files in this regard
8385 instead of this kludge. */
8387 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
8388 && GET_CODE (tem
) == CONST_INT
8390 && 0 != (INTVAL (tem
)
8391 & ((HOST_WIDE_INT
) 1
8392 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8393 tem
= GEN_INT (INTVAL (tem
)
8394 | ((HOST_WIDE_INT
) (-1)
8395 << GET_MODE_BITSIZE (GET_MODE (x
))));
8399 else if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].nonzero_bits
)
8401 unsigned HOST_WIDE_INT mask
= reg_stat
[REGNO (x
)].nonzero_bits
;
8403 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
8404 /* We don't know anything about the upper bits. */
8405 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8412 /* Return the number of bits at the high-order end of X that are known to
8413 be equal to the sign bit. X will be used in mode MODE; if MODE is
8414 VOIDmode, X will be used in its own mode. The returned value will always
8415 be between 1 and the number of bits in MODE. */
8418 reg_num_sign_bit_copies_for_combine (rtx x
, enum machine_mode mode
,
8419 rtx known_x ATTRIBUTE_UNUSED
,
8420 enum machine_mode known_mode
8422 unsigned int known_ret ATTRIBUTE_UNUSED
,
8423 unsigned int *result
)
8427 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8428 && reg_stat
[REGNO (x
)].last_set_mode
== mode
8429 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8430 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8431 && REG_N_SETS (REGNO (x
)) == 1
8432 && ! REGNO_REG_SET_P
8433 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
,
8435 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8437 *result
= reg_stat
[REGNO (x
)].last_set_sign_bit_copies
;
8441 tem
= get_last_value (x
);
8445 if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].sign_bit_copies
!= 0
8446 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
8447 *result
= reg_stat
[REGNO (x
)].sign_bit_copies
;
8452 /* Return the number of "extended" bits there are in X, when interpreted
8453 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8454 unsigned quantities, this is the number of high-order zero bits.
8455 For signed quantities, this is the number of copies of the sign bit
8456 minus 1. In both case, this function returns the number of "spare"
8457 bits. For example, if two quantities for which this function returns
8458 at least 1 are added, the addition is known not to overflow.
8460 This function will always return 0 unless called during combine, which
8461 implies that it must be called from a define_split. */
8464 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8466 if (nonzero_sign_valid
== 0)
8470 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8471 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8472 - floor_log2 (nonzero_bits (x
, mode
)))
8474 : num_sign_bit_copies (x
, mode
) - 1);
8477 /* This function is called from `simplify_shift_const' to merge two
8478 outer operations. Specifically, we have already found that we need
8479 to perform operation *POP0 with constant *PCONST0 at the outermost
8480 position. We would now like to also perform OP1 with constant CONST1
8481 (with *POP0 being done last).
8483 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8484 the resulting operation. *PCOMP_P is set to 1 if we would need to
8485 complement the innermost operand, otherwise it is unchanged.
8487 MODE is the mode in which the operation will be done. No bits outside
8488 the width of this mode matter. It is assumed that the width of this mode
8489 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8491 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8492 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8493 result is simply *PCONST0.
8495 If the resulting operation cannot be expressed as one operation, we
8496 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8499 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8501 enum rtx_code op0
= *pop0
;
8502 HOST_WIDE_INT const0
= *pconst0
;
8504 const0
&= GET_MODE_MASK (mode
);
8505 const1
&= GET_MODE_MASK (mode
);
8507 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8511 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8514 if (op1
== UNKNOWN
|| op0
== SET
)
8517 else if (op0
== UNKNOWN
)
8518 op0
= op1
, const0
= const1
;
8520 else if (op0
== op1
)
8544 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8545 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8548 /* If the two constants aren't the same, we can't do anything. The
8549 remaining six cases can all be done. */
8550 else if (const0
!= const1
)
8558 /* (a & b) | b == b */
8560 else /* op1 == XOR */
8561 /* (a ^ b) | b == a | b */
8567 /* (a & b) ^ b == (~a) & b */
8568 op0
= AND
, *pcomp_p
= 1;
8569 else /* op1 == IOR */
8570 /* (a | b) ^ b == a & ~b */
8571 op0
= AND
, const0
= ~const0
;
8576 /* (a | b) & b == b */
8578 else /* op1 == XOR */
8579 /* (a ^ b) & b) == (~a) & b */
8586 /* Check for NO-OP cases. */
8587 const0
&= GET_MODE_MASK (mode
);
8589 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8591 else if (const0
== 0 && op0
== AND
)
8593 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8597 /* ??? Slightly redundant with the above mask, but not entirely.
8598 Moving this above means we'd have to sign-extend the mode mask
8599 for the final test. */
8600 const0
= trunc_int_for_mode (const0
, mode
);
8608 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8609 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8610 that we started with.
8612 The shift is normally computed in the widest mode we find in VAROP, as
8613 long as it isn't a different number of words than RESULT_MODE. Exceptions
8614 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8617 simplify_shift_const (rtx x
, enum rtx_code code
,
8618 enum machine_mode result_mode
, rtx varop
,
8621 enum rtx_code orig_code
= code
;
8624 enum machine_mode mode
= result_mode
;
8625 enum machine_mode shift_mode
, tmode
;
8626 unsigned int mode_words
8627 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8628 /* We form (outer_op (code varop count) (outer_const)). */
8629 enum rtx_code outer_op
= UNKNOWN
;
8630 HOST_WIDE_INT outer_const
= 0;
8632 int complement_p
= 0;
8635 /* Make sure and truncate the "natural" shift on the way in. We don't
8636 want to do this inside the loop as it makes it more difficult to
8638 if (SHIFT_COUNT_TRUNCATED
)
8639 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
8641 /* If we were given an invalid count, don't do anything except exactly
8642 what was requested. */
8644 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
8649 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
8654 /* Unless one of the branches of the `if' in this loop does a `continue',
8655 we will `break' the loop after the `if'. */
8659 /* If we have an operand of (clobber (const_int 0)), just return that
8661 if (GET_CODE (varop
) == CLOBBER
)
8664 /* If we discovered we had to complement VAROP, leave. Making a NOT
8665 here would cause an infinite loop. */
8669 /* Convert ROTATERT to ROTATE. */
8670 if (code
== ROTATERT
)
8672 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
8674 if (VECTOR_MODE_P (result_mode
))
8675 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
8677 count
= bitsize
- count
;
8680 /* We need to determine what mode we will do the shift in. If the
8681 shift is a right shift or a ROTATE, we must always do it in the mode
8682 it was originally done in. Otherwise, we can do it in MODE, the
8683 widest mode encountered. */
8685 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8686 ? result_mode
: mode
);
8688 /* Handle cases where the count is greater than the size of the mode
8689 minus 1. For ASHIFT, use the size minus one as the count (this can
8690 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8691 take the count modulo the size. For other shifts, the result is
8694 Since these shifts are being produced by the compiler by combining
8695 multiple operations, each of which are defined, we know what the
8696 result is supposed to be. */
8698 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
8700 if (code
== ASHIFTRT
)
8701 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8702 else if (code
== ROTATE
|| code
== ROTATERT
)
8703 count
%= GET_MODE_BITSIZE (shift_mode
);
8706 /* We can't simply return zero because there may be an
8714 /* An arithmetic right shift of a quantity known to be -1 or 0
8716 if (code
== ASHIFTRT
8717 && (num_sign_bit_copies (varop
, shift_mode
)
8718 == GET_MODE_BITSIZE (shift_mode
)))
8724 /* If we are doing an arithmetic right shift and discarding all but
8725 the sign bit copies, this is equivalent to doing a shift by the
8726 bitsize minus one. Convert it into that shift because it will often
8727 allow other simplifications. */
8729 if (code
== ASHIFTRT
8730 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8731 >= GET_MODE_BITSIZE (shift_mode
)))
8732 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8734 /* We simplify the tests below and elsewhere by converting
8735 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8736 `make_compound_operation' will convert it to an ASHIFTRT for
8737 those machines (such as VAX) that don't have an LSHIFTRT. */
8738 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8740 && ((nonzero_bits (varop
, shift_mode
)
8741 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8745 if (code
== LSHIFTRT
8746 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8747 && !(nonzero_bits (varop
, shift_mode
) >> count
))
8750 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8751 && !((nonzero_bits (varop
, shift_mode
) << count
)
8752 & GET_MODE_MASK (shift_mode
)))
8755 switch (GET_CODE (varop
))
8761 new = expand_compound_operation (varop
);
8770 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8771 minus the width of a smaller mode, we can do this with a
8772 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8773 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8774 && ! mode_dependent_address_p (XEXP (varop
, 0))
8775 && ! MEM_VOLATILE_P (varop
)
8776 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8777 MODE_INT
, 1)) != BLKmode
)
8779 new = adjust_address_nv (varop
, tmode
,
8780 BYTES_BIG_ENDIAN
? 0
8781 : count
/ BITS_PER_UNIT
);
8783 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8784 : ZERO_EXTEND
, mode
, new);
8791 /* Similar to the case above, except that we can only do this if
8792 the resulting mode is the same as that of the underlying
8793 MEM and adjust the address depending on the *bits* endianness
8794 because of the way that bit-field extract insns are defined. */
8795 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8796 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8797 MODE_INT
, 1)) != BLKmode
8798 && tmode
== GET_MODE (XEXP (varop
, 0)))
8800 if (BITS_BIG_ENDIAN
)
8801 new = XEXP (varop
, 0);
8804 new = copy_rtx (XEXP (varop
, 0));
8805 SUBST (XEXP (new, 0),
8806 plus_constant (XEXP (new, 0),
8807 count
/ BITS_PER_UNIT
));
8810 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8811 : ZERO_EXTEND
, mode
, new);
8818 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8819 the same number of words as what we've seen so far. Then store
8820 the widest mode in MODE. */
8821 if (subreg_lowpart_p (varop
)
8822 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8823 > GET_MODE_SIZE (GET_MODE (varop
)))
8824 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8825 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
8828 varop
= SUBREG_REG (varop
);
8829 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
8830 mode
= GET_MODE (varop
);
8836 /* Some machines use MULT instead of ASHIFT because MULT
8837 is cheaper. But it is still better on those machines to
8838 merge two shifts into one. */
8839 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8840 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8843 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
8845 GEN_INT (exact_log2 (
8846 INTVAL (XEXP (varop
, 1)))));
8852 /* Similar, for when divides are cheaper. */
8853 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8854 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8857 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
8859 GEN_INT (exact_log2 (
8860 INTVAL (XEXP (varop
, 1)))));
8866 /* If we are extracting just the sign bit of an arithmetic
8867 right shift, that shift is not needed. However, the sign
8868 bit of a wider mode may be different from what would be
8869 interpreted as the sign bit in a narrower mode, so, if
8870 the result is narrower, don't discard the shift. */
8871 if (code
== LSHIFTRT
8872 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8873 && (GET_MODE_BITSIZE (result_mode
)
8874 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
8876 varop
= XEXP (varop
, 0);
8880 /* ... fall through ... */
8885 /* Here we have two nested shifts. The result is usually the
8886 AND of a new shift with a mask. We compute the result below. */
8887 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8888 && INTVAL (XEXP (varop
, 1)) >= 0
8889 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
8890 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8891 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8893 enum rtx_code first_code
= GET_CODE (varop
);
8894 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
8895 unsigned HOST_WIDE_INT mask
;
8898 /* We have one common special case. We can't do any merging if
8899 the inner code is an ASHIFTRT of a smaller mode. However, if
8900 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8901 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8902 we can convert it to
8903 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8904 This simplifies certain SIGN_EXTEND operations. */
8905 if (code
== ASHIFT
&& first_code
== ASHIFTRT
8906 && count
== (unsigned int)
8907 (GET_MODE_BITSIZE (result_mode
)
8908 - GET_MODE_BITSIZE (GET_MODE (varop
))))
8910 /* C3 has the low-order C1 bits zero. */
8912 mask
= (GET_MODE_MASK (mode
)
8913 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
8915 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
8916 XEXP (varop
, 0), mask
);
8917 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
8919 count
= first_count
;
8924 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8925 than C1 high-order bits equal to the sign bit, we can convert
8926 this to either an ASHIFT or an ASHIFTRT depending on the
8929 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8931 if (code
== ASHIFTRT
&& first_code
== ASHIFT
8932 && GET_MODE (varop
) == shift_mode
8933 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
8936 varop
= XEXP (varop
, 0);
8938 signed_count
= count
- first_count
;
8939 if (signed_count
< 0)
8940 count
= -signed_count
, code
= ASHIFT
;
8942 count
= signed_count
;
8947 /* There are some cases we can't do. If CODE is ASHIFTRT,
8948 we can only do this if FIRST_CODE is also ASHIFTRT.
8950 We can't do the case when CODE is ROTATE and FIRST_CODE is
8953 If the mode of this shift is not the mode of the outer shift,
8954 we can't do this if either shift is a right shift or ROTATE.
8956 Finally, we can't do any of these if the mode is too wide
8957 unless the codes are the same.
8959 Handle the case where the shift codes are the same
8962 if (code
== first_code
)
8964 if (GET_MODE (varop
) != result_mode
8965 && (code
== ASHIFTRT
|| code
== LSHIFTRT
8969 count
+= first_count
;
8970 varop
= XEXP (varop
, 0);
8974 if (code
== ASHIFTRT
8975 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
8976 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
8977 || (GET_MODE (varop
) != result_mode
8978 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
8979 || first_code
== ROTATE
8980 || code
== ROTATE
)))
8983 /* To compute the mask to apply after the shift, shift the
8984 nonzero bits of the inner shift the same way the
8985 outer shift will. */
8987 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
8990 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
8993 /* Give up if we can't compute an outer operation to use. */
8995 || GET_CODE (mask_rtx
) != CONST_INT
8996 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
8998 result_mode
, &complement_p
))
9001 /* If the shifts are in the same direction, we add the
9002 counts. Otherwise, we subtract them. */
9003 signed_count
= count
;
9004 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9005 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9006 signed_count
+= first_count
;
9008 signed_count
-= first_count
;
9010 /* If COUNT is positive, the new shift is usually CODE,
9011 except for the two exceptions below, in which case it is
9012 FIRST_CODE. If the count is negative, FIRST_CODE should
9014 if (signed_count
> 0
9015 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9016 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9017 code
= first_code
, count
= signed_count
;
9018 else if (signed_count
< 0)
9019 code
= first_code
, count
= -signed_count
;
9021 count
= signed_count
;
9023 varop
= XEXP (varop
, 0);
9027 /* If we have (A << B << C) for any shift, we can convert this to
9028 (A << C << B). This wins if A is a constant. Only try this if
9029 B is not a constant. */
9031 else if (GET_CODE (varop
) == code
9032 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9034 = simplify_binary_operation (code
, mode
,
9038 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9045 /* Make this fit the case below. */
9046 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9047 GEN_INT (GET_MODE_MASK (mode
)));
9053 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9054 with C the size of VAROP - 1 and the shift is logical if
9055 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9056 we have an (le X 0) operation. If we have an arithmetic shift
9057 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9058 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9060 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9061 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9062 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9063 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9064 && count
== (unsigned int)
9065 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9066 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9069 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9072 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9073 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9078 /* If we have (shift (logical)), move the logical to the outside
9079 to allow it to possibly combine with another logical and the
9080 shift to combine with another shift. This also canonicalizes to
9081 what a ZERO_EXTRACT looks like. Also, some machines have
9082 (and (shift)) insns. */
9084 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9085 /* We can't do this if we have (ashiftrt (xor)) and the
9086 constant has its sign bit set in shift_mode. */
9087 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9088 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9090 && (new = simplify_binary_operation (code
, result_mode
,
9092 GEN_INT (count
))) != 0
9093 && GET_CODE (new) == CONST_INT
9094 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9095 INTVAL (new), result_mode
, &complement_p
))
9097 varop
= XEXP (varop
, 0);
9101 /* If we can't do that, try to simplify the shift in each arm of the
9102 logical expression, make a new logical expression, and apply
9103 the inverse distributive law. This also can't be done
9104 for some (ashiftrt (xor)). */
9105 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9106 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
9107 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
9110 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9111 XEXP (varop
, 0), count
);
9112 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9113 XEXP (varop
, 1), count
);
9115 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
9117 varop
= apply_distributive_law (varop
);
9125 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9126 says that the sign bit can be tested, FOO has mode MODE, C is
9127 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9128 that may be nonzero. */
9129 if (code
== LSHIFTRT
9130 && XEXP (varop
, 1) == const0_rtx
9131 && GET_MODE (XEXP (varop
, 0)) == result_mode
9132 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9133 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9134 && ((STORE_FLAG_VALUE
9135 & ((HOST_WIDE_INT
) 1
9136 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9137 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9138 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9139 (HOST_WIDE_INT
) 1, result_mode
,
9142 varop
= XEXP (varop
, 0);
9149 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9150 than the number of bits in the mode is equivalent to A. */
9151 if (code
== LSHIFTRT
9152 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9153 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9155 varop
= XEXP (varop
, 0);
9160 /* NEG commutes with ASHIFT since it is multiplication. Move the
9161 NEG outside to allow shifts to combine. */
9163 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9164 (HOST_WIDE_INT
) 0, result_mode
,
9167 varop
= XEXP (varop
, 0);
9173 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9174 is one less than the number of bits in the mode is
9175 equivalent to (xor A 1). */
9176 if (code
== LSHIFTRT
9177 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9178 && XEXP (varop
, 1) == constm1_rtx
9179 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9180 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9181 (HOST_WIDE_INT
) 1, result_mode
,
9185 varop
= XEXP (varop
, 0);
9189 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9190 that might be nonzero in BAR are those being shifted out and those
9191 bits are known zero in FOO, we can replace the PLUS with FOO.
9192 Similarly in the other operand order. This code occurs when
9193 we are computing the size of a variable-size array. */
9195 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9196 && count
< HOST_BITS_PER_WIDE_INT
9197 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9198 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9199 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9201 varop
= XEXP (varop
, 0);
9204 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9205 && count
< HOST_BITS_PER_WIDE_INT
9206 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9207 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9209 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9210 & nonzero_bits (XEXP (varop
, 1),
9213 varop
= XEXP (varop
, 1);
9217 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9219 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9220 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9222 GEN_INT (count
))) != 0
9223 && GET_CODE (new) == CONST_INT
9224 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9225 INTVAL (new), result_mode
, &complement_p
))
9227 varop
= XEXP (varop
, 0);
9231 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9232 signbit', and attempt to change the PLUS to an XOR and move it to
9233 the outer operation as is done above in the AND/IOR/XOR case
9234 leg for shift(logical). See details in logical handling above
9235 for reasoning in doing so. */
9236 if (code
== LSHIFTRT
9237 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9238 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
9239 && (new = simplify_binary_operation (code
, result_mode
,
9241 GEN_INT (count
))) != 0
9242 && GET_CODE (new) == CONST_INT
9243 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9244 INTVAL (new), result_mode
, &complement_p
))
9246 varop
= XEXP (varop
, 0);
9253 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9254 with C the size of VAROP - 1 and the shift is logical if
9255 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9256 we have a (gt X 0) operation. If the shift is arithmetic with
9257 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9258 we have a (neg (gt X 0)) operation. */
9260 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9261 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9262 && count
== (unsigned int)
9263 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9264 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9265 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9266 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9268 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9271 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9274 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9275 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9282 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9283 if the truncate does not affect the value. */
9284 if (code
== LSHIFTRT
9285 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9286 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9287 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9288 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9289 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9291 rtx varop_inner
= XEXP (varop
, 0);
9294 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9295 XEXP (varop_inner
, 0),
9297 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9298 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9311 /* We need to determine what mode to do the shift in. If the shift is
9312 a right shift or ROTATE, we must always do it in the mode it was
9313 originally done in. Otherwise, we can do it in MODE, the widest mode
9314 encountered. The code we care about is that of the shift that will
9315 actually be done, not the shift that was originally requested. */
9317 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9318 ? result_mode
: mode
);
9320 /* We have now finished analyzing the shift. The result should be
9321 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9322 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9323 to the result of the shift. OUTER_CONST is the relevant constant,
9324 but we must turn off all bits turned off in the shift.
9326 If we were passed a value for X, see if we can use any pieces of
9327 it. If not, make new rtx. */
9329 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == RTX_BIN_ARITH
9330 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9331 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9332 const_rtx
= XEXP (x
, 1);
9334 const_rtx
= GEN_INT (count
);
9336 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9337 && GET_MODE (XEXP (x
, 0)) == shift_mode
9338 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9339 varop
= XEXP (x
, 0);
9340 else if (GET_MODE (varop
) != shift_mode
)
9341 varop
= gen_lowpart (shift_mode
, varop
);
9343 /* If we can't make the SUBREG, try to return what we were given. */
9344 if (GET_CODE (varop
) == CLOBBER
)
9345 return x
? x
: varop
;
9347 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9351 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9353 /* If we have an outer operation and we just made a shift, it is
9354 possible that we could have simplified the shift were it not
9355 for the outer operation. So try to do the simplification
9358 if (outer_op
!= UNKNOWN
&& GET_CODE (x
) == code
9359 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9360 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9361 INTVAL (XEXP (x
, 1)));
9363 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9364 turn off all the bits that the shift would have turned off. */
9365 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9366 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9367 GET_MODE_MASK (result_mode
) >> orig_count
);
9369 /* Do the remainder of the processing in RESULT_MODE. */
9370 x
= gen_lowpart (result_mode
, x
);
9372 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9375 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9377 if (outer_op
!= UNKNOWN
)
9379 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9380 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9382 if (outer_op
== AND
)
9383 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9384 else if (outer_op
== SET
)
9385 /* This means that we have determined that the result is
9386 equivalent to a constant. This should be rare. */
9387 x
= GEN_INT (outer_const
);
9388 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
9389 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9391 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
9392 GEN_INT (outer_const
));
9398 /* Like recog, but we receive the address of a pointer to a new pattern.
9399 We try to match the rtx that the pointer points to.
9400 If that fails, we may try to modify or replace the pattern,
9401 storing the replacement into the same pointer object.
9403 Modifications include deletion or addition of CLOBBERs.
9405 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9406 the CLOBBERs are placed.
9408 The value is the final insn code from the pattern ultimately matched,
9412 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9415 int insn_code_number
;
9416 int num_clobbers_to_add
= 0;
9419 rtx old_notes
, old_pat
;
9421 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9422 we use to indicate that something didn't match. If we find such a
9423 thing, force rejection. */
9424 if (GET_CODE (pat
) == PARALLEL
)
9425 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9426 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9427 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9430 old_pat
= PATTERN (insn
);
9431 old_notes
= REG_NOTES (insn
);
9432 PATTERN (insn
) = pat
;
9433 REG_NOTES (insn
) = 0;
9435 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9437 /* If it isn't, there is the possibility that we previously had an insn
9438 that clobbered some register as a side effect, but the combined
9439 insn doesn't need to do that. So try once more without the clobbers
9440 unless this represents an ASM insn. */
9442 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9443 && GET_CODE (pat
) == PARALLEL
)
9447 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9448 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9451 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9455 SUBST_INT (XVECLEN (pat
, 0), pos
);
9458 pat
= XVECEXP (pat
, 0, 0);
9460 PATTERN (insn
) = pat
;
9461 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9463 PATTERN (insn
) = old_pat
;
9464 REG_NOTES (insn
) = old_notes
;
9466 /* Recognize all noop sets, these will be killed by followup pass. */
9467 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9468 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9470 /* If we had any clobbers to add, make a new pattern than contains
9471 them. Then check to make sure that all of them are dead. */
9472 if (num_clobbers_to_add
)
9474 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9475 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9477 + num_clobbers_to_add
)
9478 : num_clobbers_to_add
+ 1));
9480 if (GET_CODE (pat
) == PARALLEL
)
9481 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9482 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9484 XVECEXP (newpat
, 0, 0) = pat
;
9486 add_clobbers (newpat
, insn_code_number
);
9488 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9489 i
< XVECLEN (newpat
, 0); i
++)
9491 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
9492 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9494 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9495 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9503 return insn_code_number
;
9506 /* Like gen_lowpart_general but for use by combine. In combine it
9507 is not possible to create any new pseudoregs. However, it is
9508 safe to create invalid memory addresses, because combine will
9509 try to recognize them and all they will do is make the combine
9512 If for some reason this cannot do its job, an rtx
9513 (clobber (const_int 0)) is returned.
9514 An insn containing that will not be recognized. */
9517 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
9519 enum machine_mode imode
= GET_MODE (x
);
9520 unsigned int osize
= GET_MODE_SIZE (omode
);
9521 unsigned int isize
= GET_MODE_SIZE (imode
);
9527 /* Return identity if this is a CONST or symbolic reference. */
9529 && (GET_CODE (x
) == CONST
9530 || GET_CODE (x
) == SYMBOL_REF
9531 || GET_CODE (x
) == LABEL_REF
))
9534 /* We can only support MODE being wider than a word if X is a
9535 constant integer or has a mode the same size. */
9536 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
9537 && ! ((imode
== VOIDmode
9538 && (GET_CODE (x
) == CONST_INT
9539 || GET_CODE (x
) == CONST_DOUBLE
))
9543 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9544 won't know what to do. So we will strip off the SUBREG here and
9545 process normally. */
9546 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
9550 /* For use in case we fall down into the address adjustments
9551 further below, we need to adjust the known mode and size of
9552 x; imode and isize, since we just adjusted x. */
9553 imode
= GET_MODE (x
);
9558 isize
= GET_MODE_SIZE (imode
);
9561 result
= gen_lowpart_common (omode
, x
);
9563 #ifdef CANNOT_CHANGE_MODE_CLASS
9564 if (result
!= 0 && GET_CODE (result
) == SUBREG
)
9565 record_subregs_of_mode (result
);
9575 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9577 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9580 /* If we want to refer to something bigger than the original memref,
9581 generate a paradoxical subreg instead. That will force a reload
9582 of the original memref X. */
9584 return gen_rtx_SUBREG (omode
, x
, 0);
9586 if (WORDS_BIG_ENDIAN
)
9587 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
9589 /* Adjust the address so that the address-after-the-data is
9591 if (BYTES_BIG_ENDIAN
)
9592 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
9594 return adjust_address_nv (x
, omode
, offset
);
9597 /* If X is a comparison operator, rewrite it in a new mode. This
9598 probably won't match, but may allow further simplifications. */
9599 else if (COMPARISON_P (x
))
9600 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
9602 /* If we couldn't simplify X any other way, just enclose it in a
9603 SUBREG. Normally, this SUBREG won't match, but some patterns may
9604 include an explicit SUBREG or we may simplify it further in combine. */
9610 offset
= subreg_lowpart_offset (omode
, imode
);
9611 if (imode
== VOIDmode
)
9613 imode
= int_mode_for_mode (omode
);
9614 x
= gen_lowpart_common (imode
, x
);
9618 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
9624 return gen_rtx_CLOBBER (imode
, const0_rtx
);
9627 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9628 comparison code that will be tested.
9630 The result is a possibly different comparison code to use. *POP0 and
9631 *POP1 may be updated.
9633 It is possible that we might detect that a comparison is either always
9634 true or always false. However, we do not perform general constant
9635 folding in combine, so this knowledge isn't useful. Such tautologies
9636 should have been detected earlier. Hence we ignore all such cases. */
9638 static enum rtx_code
9639 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
9645 enum machine_mode mode
, tmode
;
9647 /* Try a few ways of applying the same transformation to both operands. */
9650 #ifndef WORD_REGISTER_OPERATIONS
9651 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9652 so check specially. */
9653 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9654 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9655 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9656 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9657 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9658 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9659 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9660 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9661 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9662 && XEXP (op0
, 1) == XEXP (op1
, 1)
9663 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
9664 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
9665 && (INTVAL (XEXP (op0
, 1))
9666 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9668 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9670 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9671 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9675 /* If both operands are the same constant shift, see if we can ignore the
9676 shift. We can if the shift is a rotate or if the bits shifted out of
9677 this shift are known to be zero for both inputs and if the type of
9678 comparison is compatible with the shift. */
9679 if (GET_CODE (op0
) == GET_CODE (op1
)
9680 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9681 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9682 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9683 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9684 || (GET_CODE (op0
) == ASHIFTRT
9685 && (code
!= GTU
&& code
!= LTU
9686 && code
!= GEU
&& code
!= LEU
)))
9687 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9688 && INTVAL (XEXP (op0
, 1)) >= 0
9689 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9690 && XEXP (op0
, 1) == XEXP (op1
, 1))
9692 enum machine_mode mode
= GET_MODE (op0
);
9693 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9694 int shift_count
= INTVAL (XEXP (op0
, 1));
9696 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9697 mask
&= (mask
>> shift_count
) << shift_count
;
9698 else if (GET_CODE (op0
) == ASHIFT
)
9699 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9701 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
9702 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
9703 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9708 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9709 SUBREGs are of the same mode, and, in both cases, the AND would
9710 be redundant if the comparison was done in the narrower mode,
9711 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9712 and the operand's possibly nonzero bits are 0xffffff01; in that case
9713 if we only care about QImode, we don't need the AND). This case
9714 occurs if the output mode of an scc insn is not SImode and
9715 STORE_FLAG_VALUE == 1 (e.g., the 386).
9717 Similarly, check for a case where the AND's are ZERO_EXTEND
9718 operations from some narrower mode even though a SUBREG is not
9721 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9722 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9723 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9725 rtx inner_op0
= XEXP (op0
, 0);
9726 rtx inner_op1
= XEXP (op1
, 0);
9727 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9728 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9731 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9732 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9733 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9734 && (GET_MODE (SUBREG_REG (inner_op0
))
9735 == GET_MODE (SUBREG_REG (inner_op1
)))
9736 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9737 <= HOST_BITS_PER_WIDE_INT
)
9738 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9739 GET_MODE (SUBREG_REG (inner_op0
)))))
9740 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9741 GET_MODE (SUBREG_REG (inner_op1
))))))
9743 op0
= SUBREG_REG (inner_op0
);
9744 op1
= SUBREG_REG (inner_op1
);
9746 /* The resulting comparison is always unsigned since we masked
9747 off the original sign bit. */
9748 code
= unsigned_condition (code
);
9754 for (tmode
= GET_CLASS_NARROWEST_MODE
9755 (GET_MODE_CLASS (GET_MODE (op0
)));
9756 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9757 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9759 op0
= gen_lowpart (tmode
, inner_op0
);
9760 op1
= gen_lowpart (tmode
, inner_op1
);
9761 code
= unsigned_condition (code
);
9770 /* If both operands are NOT, we can strip off the outer operation
9771 and adjust the comparison code for swapped operands; similarly for
9772 NEG, except that this must be an equality comparison. */
9773 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9774 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9775 && (code
== EQ
|| code
== NE
)))
9776 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9782 /* If the first operand is a constant, swap the operands and adjust the
9783 comparison code appropriately, but don't do this if the second operand
9784 is already a constant integer. */
9785 if (swap_commutative_operands_p (op0
, op1
))
9787 tem
= op0
, op0
= op1
, op1
= tem
;
9788 code
= swap_condition (code
);
9791 /* We now enter a loop during which we will try to simplify the comparison.
9792 For the most part, we only are concerned with comparisons with zero,
9793 but some things may really be comparisons with zero but not start
9794 out looking that way. */
9796 while (GET_CODE (op1
) == CONST_INT
)
9798 enum machine_mode mode
= GET_MODE (op0
);
9799 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
9800 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9801 int equality_comparison_p
;
9802 int sign_bit_comparison_p
;
9803 int unsigned_comparison_p
;
9804 HOST_WIDE_INT const_op
;
9806 /* We only want to handle integral modes. This catches VOIDmode,
9807 CCmode, and the floating-point modes. An exception is that we
9808 can handle VOIDmode if OP0 is a COMPARE or a comparison
9811 if (GET_MODE_CLASS (mode
) != MODE_INT
9812 && ! (mode
== VOIDmode
9813 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
9816 /* Get the constant we are comparing against and turn off all bits
9817 not on in our mode. */
9818 const_op
= INTVAL (op1
);
9819 if (mode
!= VOIDmode
)
9820 const_op
= trunc_int_for_mode (const_op
, mode
);
9821 op1
= GEN_INT (const_op
);
9823 /* If we are comparing against a constant power of two and the value
9824 being compared can only have that single bit nonzero (e.g., it was
9825 `and'ed with that bit), we can replace this with a comparison
9828 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
9829 || code
== LT
|| code
== LTU
)
9830 && mode_width
<= HOST_BITS_PER_WIDE_INT
9831 && exact_log2 (const_op
) >= 0
9832 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
9834 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
9835 op1
= const0_rtx
, const_op
= 0;
9838 /* Similarly, if we are comparing a value known to be either -1 or
9839 0 with -1, change it to the opposite comparison against zero. */
9842 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
9843 || code
== GEU
|| code
== LTU
)
9844 && num_sign_bit_copies (op0
, mode
) == mode_width
)
9846 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
9847 op1
= const0_rtx
, const_op
= 0;
9850 /* Do some canonicalizations based on the comparison code. We prefer
9851 comparisons against zero and then prefer equality comparisons.
9852 If we can reduce the size of a constant, we will do that too. */
9857 /* < C is equivalent to <= (C - 1) */
9861 op1
= GEN_INT (const_op
);
9863 /* ... fall through to LE case below. */
9869 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9873 op1
= GEN_INT (const_op
);
9877 /* If we are doing a <= 0 comparison on a value known to have
9878 a zero sign bit, we can replace this with == 0. */
9879 else if (const_op
== 0
9880 && mode_width
<= HOST_BITS_PER_WIDE_INT
9881 && (nonzero_bits (op0
, mode
)
9882 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9887 /* >= C is equivalent to > (C - 1). */
9891 op1
= GEN_INT (const_op
);
9893 /* ... fall through to GT below. */
9899 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9903 op1
= GEN_INT (const_op
);
9907 /* If we are doing a > 0 comparison on a value known to have
9908 a zero sign bit, we can replace this with != 0. */
9909 else if (const_op
== 0
9910 && mode_width
<= HOST_BITS_PER_WIDE_INT
9911 && (nonzero_bits (op0
, mode
)
9912 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9917 /* < C is equivalent to <= (C - 1). */
9921 op1
= GEN_INT (const_op
);
9923 /* ... fall through ... */
9926 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9927 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9928 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9930 const_op
= 0, op1
= const0_rtx
;
9938 /* unsigned <= 0 is equivalent to == 0 */
9942 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9943 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9944 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9946 const_op
= 0, op1
= const0_rtx
;
9952 /* >= C is equivalent to > (C - 1). */
9956 op1
= GEN_INT (const_op
);
9958 /* ... fall through ... */
9961 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9962 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9963 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9965 const_op
= 0, op1
= const0_rtx
;
9973 /* unsigned > 0 is equivalent to != 0 */
9977 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9978 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9979 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9981 const_op
= 0, op1
= const0_rtx
;
9990 /* Compute some predicates to simplify code below. */
9992 equality_comparison_p
= (code
== EQ
|| code
== NE
);
9993 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
9994 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
9997 /* If this is a sign bit comparison and we can do arithmetic in
9998 MODE, say that we will only be needing the sign bit of OP0. */
9999 if (sign_bit_comparison_p
10000 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10001 op0
= force_to_mode (op0
, mode
,
10003 << (GET_MODE_BITSIZE (mode
) - 1)),
10006 /* Now try cases based on the opcode of OP0. If none of the cases
10007 does a "continue", we exit this loop immediately after the
10010 switch (GET_CODE (op0
))
10013 /* If we are extracting a single bit from a variable position in
10014 a constant that has only a single bit set and are comparing it
10015 with zero, we can convert this into an equality comparison
10016 between the position and the location of the single bit. */
10017 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10018 have already reduced the shift count modulo the word size. */
10019 if (!SHIFT_COUNT_TRUNCATED
10020 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
10021 && XEXP (op0
, 1) == const1_rtx
10022 && equality_comparison_p
&& const_op
== 0
10023 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10025 if (BITS_BIG_ENDIAN
)
10027 enum machine_mode new_mode
10028 = mode_for_extraction (EP_extzv
, 1);
10029 if (new_mode
== MAX_MACHINE_MODE
)
10030 i
= BITS_PER_WORD
- 1 - i
;
10034 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10038 op0
= XEXP (op0
, 2);
10042 /* Result is nonzero iff shift count is equal to I. */
10043 code
= reverse_condition (code
);
10047 /* ... fall through ... */
10050 tem
= expand_compound_operation (op0
);
10059 /* If testing for equality, we can take the NOT of the constant. */
10060 if (equality_comparison_p
10061 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10063 op0
= XEXP (op0
, 0);
10068 /* If just looking at the sign bit, reverse the sense of the
10070 if (sign_bit_comparison_p
)
10072 op0
= XEXP (op0
, 0);
10073 code
= (code
== GE
? LT
: GE
);
10079 /* If testing for equality, we can take the NEG of the constant. */
10080 if (equality_comparison_p
10081 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10083 op0
= XEXP (op0
, 0);
10088 /* The remaining cases only apply to comparisons with zero. */
10092 /* When X is ABS or is known positive,
10093 (neg X) is < 0 if and only if X != 0. */
10095 if (sign_bit_comparison_p
10096 && (GET_CODE (XEXP (op0
, 0)) == ABS
10097 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10098 && (nonzero_bits (XEXP (op0
, 0), mode
)
10099 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10101 op0
= XEXP (op0
, 0);
10102 code
= (code
== LT
? NE
: EQ
);
10106 /* If we have NEG of something whose two high-order bits are the
10107 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10108 if (num_sign_bit_copies (op0
, mode
) >= 2)
10110 op0
= XEXP (op0
, 0);
10111 code
= swap_condition (code
);
10117 /* If we are testing equality and our count is a constant, we
10118 can perform the inverse operation on our RHS. */
10119 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10120 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10121 op1
, XEXP (op0
, 1))) != 0)
10123 op0
= XEXP (op0
, 0);
10128 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10129 a particular bit. Convert it to an AND of a constant of that
10130 bit. This will be converted into a ZERO_EXTRACT. */
10131 if (const_op
== 0 && sign_bit_comparison_p
10132 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10133 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10135 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10138 - INTVAL (XEXP (op0
, 1)))));
10139 code
= (code
== LT
? NE
: EQ
);
10143 /* Fall through. */
10146 /* ABS is ignorable inside an equality comparison with zero. */
10147 if (const_op
== 0 && equality_comparison_p
)
10149 op0
= XEXP (op0
, 0);
10155 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10156 (compare FOO CONST) if CONST fits in FOO's mode and we
10157 are either testing inequality or have an unsigned
10158 comparison with ZERO_EXTEND or a signed comparison with
10159 SIGN_EXTEND. But don't do it if we don't have a compare
10160 insn of the given mode, since we'd have to revert it
10161 later on, and then we wouldn't know whether to sign- or
10163 mode
= GET_MODE (XEXP (op0
, 0));
10164 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10165 && ! unsigned_comparison_p
10166 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10167 && ((unsigned HOST_WIDE_INT
) const_op
10168 < (((unsigned HOST_WIDE_INT
) 1
10169 << (GET_MODE_BITSIZE (mode
) - 1))))
10170 && cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
10172 op0
= XEXP (op0
, 0);
10178 /* Check for the case where we are comparing A - C1 with C2, that is
10180 (subreg:MODE (plus (A) (-C1))) op (C2)
10182 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10183 comparison in the wider mode. One of the following two conditions
10184 must be true in order for this to be valid:
10186 1. The mode extension results in the same bit pattern being added
10187 on both sides and the comparison is equality or unsigned. As
10188 C2 has been truncated to fit in MODE, the pattern can only be
10191 2. The mode extension results in the sign bit being copied on
10194 The difficulty here is that we have predicates for A but not for
10195 (A - C1) so we need to check that C1 is within proper bounds so
10196 as to perturbate A as little as possible. */
10198 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10199 && subreg_lowpart_p (op0
)
10200 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) > mode_width
10201 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10202 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
)
10204 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
10205 rtx a
= XEXP (SUBREG_REG (op0
), 0);
10206 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
10209 && (unsigned HOST_WIDE_INT
) c1
10210 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
10211 && (equality_comparison_p
|| unsigned_comparison_p
)
10212 /* (A - C1) zero-extends if it is positive and sign-extends
10213 if it is negative, C2 both zero- and sign-extends. */
10214 && ((0 == (nonzero_bits (a
, inner_mode
)
10215 & ~GET_MODE_MASK (mode
))
10217 /* (A - C1) sign-extends if it is positive and 1-extends
10218 if it is negative, C2 both sign- and 1-extends. */
10219 || (num_sign_bit_copies (a
, inner_mode
)
10220 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10223 || ((unsigned HOST_WIDE_INT
) c1
10224 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
10225 /* (A - C1) always sign-extends, like C2. */
10226 && num_sign_bit_copies (a
, inner_mode
)
10227 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10228 - mode_width
- 1)))
10230 op0
= SUBREG_REG (op0
);
10235 /* If the inner mode is narrower and we are extracting the low part,
10236 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10237 if (subreg_lowpart_p (op0
)
10238 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10239 /* Fall through */ ;
10243 /* ... fall through ... */
10246 mode
= GET_MODE (XEXP (op0
, 0));
10247 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10248 && (unsigned_comparison_p
|| equality_comparison_p
)
10249 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10250 && ((unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
))
10251 && cmp_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
10253 op0
= XEXP (op0
, 0);
10259 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10260 this for equality comparisons due to pathological cases involving
10262 if (equality_comparison_p
10263 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10264 op1
, XEXP (op0
, 1))))
10266 op0
= XEXP (op0
, 0);
10271 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10272 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10273 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10275 op0
= XEXP (XEXP (op0
, 0), 0);
10276 code
= (code
== LT
? EQ
: NE
);
10282 /* We used to optimize signed comparisons against zero, but that
10283 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10284 arrive here as equality comparisons, or (GEU, LTU) are
10285 optimized away. No need to special-case them. */
10287 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10288 (eq B (minus A C)), whichever simplifies. We can only do
10289 this for equality comparisons due to pathological cases involving
10291 if (equality_comparison_p
10292 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10293 XEXP (op0
, 1), op1
)))
10295 op0
= XEXP (op0
, 0);
10300 if (equality_comparison_p
10301 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10302 XEXP (op0
, 0), op1
)))
10304 op0
= XEXP (op0
, 1);
10309 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10310 of bits in X minus 1, is one iff X > 0. */
10311 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10312 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10313 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10315 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10317 op0
= XEXP (op0
, 1);
10318 code
= (code
== GE
? LE
: GT
);
10324 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10325 if C is zero or B is a constant. */
10326 if (equality_comparison_p
10327 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10328 XEXP (op0
, 1), op1
)))
10330 op0
= XEXP (op0
, 0);
10337 case UNEQ
: case LTGT
:
10338 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10339 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10340 case UNORDERED
: case ORDERED
:
10341 /* We can't do anything if OP0 is a condition code value, rather
10342 than an actual data value. */
10344 || CC0_P (XEXP (op0
, 0))
10345 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10348 /* Get the two operands being compared. */
10349 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10350 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10352 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10354 /* Check for the cases where we simply want the result of the
10355 earlier test or the opposite of that result. */
10356 if (code
== NE
|| code
== EQ
10357 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10358 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10359 && (STORE_FLAG_VALUE
10360 & (((HOST_WIDE_INT
) 1
10361 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10362 && (code
== LT
|| code
== GE
)))
10364 enum rtx_code new_code
;
10365 if (code
== LT
|| code
== NE
)
10366 new_code
= GET_CODE (op0
);
10368 new_code
= reversed_comparison_code (op0
, NULL
);
10370 if (new_code
!= UNKNOWN
)
10381 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10383 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10384 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10385 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10387 op0
= XEXP (op0
, 1);
10388 code
= (code
== GE
? GT
: LE
);
10394 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10395 will be converted to a ZERO_EXTRACT later. */
10396 if (const_op
== 0 && equality_comparison_p
10397 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10398 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10400 op0
= simplify_and_const_int
10401 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10403 XEXP (XEXP (op0
, 0), 1)),
10404 (HOST_WIDE_INT
) 1);
10408 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10409 zero and X is a comparison and C1 and C2 describe only bits set
10410 in STORE_FLAG_VALUE, we can compare with X. */
10411 if (const_op
== 0 && equality_comparison_p
10412 && mode_width
<= HOST_BITS_PER_WIDE_INT
10413 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10414 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10415 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10416 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10417 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10419 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10420 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10421 if ((~STORE_FLAG_VALUE
& mask
) == 0
10422 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
10423 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10424 && COMPARISON_P (tem
))))
10426 op0
= XEXP (XEXP (op0
, 0), 0);
10431 /* If we are doing an equality comparison of an AND of a bit equal
10432 to the sign bit, replace this with a LT or GE comparison of
10433 the underlying value. */
10434 if (equality_comparison_p
10436 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10437 && mode_width
<= HOST_BITS_PER_WIDE_INT
10438 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10439 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10441 op0
= XEXP (op0
, 0);
10442 code
= (code
== EQ
? GE
: LT
);
10446 /* If this AND operation is really a ZERO_EXTEND from a narrower
10447 mode, the constant fits within that mode, and this is either an
10448 equality or unsigned comparison, try to do this comparison in
10449 the narrower mode. */
10450 if ((equality_comparison_p
|| unsigned_comparison_p
)
10451 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10452 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10453 & GET_MODE_MASK (mode
))
10455 && const_op
>> i
== 0
10456 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10458 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10462 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10463 fits in both M1 and M2 and the SUBREG is either paradoxical
10464 or represents the low part, permute the SUBREG and the AND
10466 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10468 unsigned HOST_WIDE_INT c1
;
10469 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10470 /* Require an integral mode, to avoid creating something like
10472 if (SCALAR_INT_MODE_P (tmode
)
10473 /* It is unsafe to commute the AND into the SUBREG if the
10474 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10475 not defined. As originally written the upper bits
10476 have a defined value due to the AND operation.
10477 However, if we commute the AND inside the SUBREG then
10478 they no longer have defined values and the meaning of
10479 the code has been changed. */
10481 #ifdef WORD_REGISTER_OPERATIONS
10482 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10483 && mode_width
<= BITS_PER_WORD
)
10485 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10486 && subreg_lowpart_p (XEXP (op0
, 0))))
10487 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10488 && mode_width
<= HOST_BITS_PER_WIDE_INT
10489 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10490 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10491 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10493 && c1
!= GET_MODE_MASK (tmode
))
10495 op0
= simplify_gen_binary (AND
, tmode
,
10496 SUBREG_REG (XEXP (op0
, 0)),
10497 gen_int_mode (c1
, tmode
));
10498 op0
= gen_lowpart (mode
, op0
);
10503 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10504 if (const_op
== 0 && equality_comparison_p
10505 && XEXP (op0
, 1) == const1_rtx
10506 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10508 op0
= simplify_and_const_int
10509 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10510 code
= (code
== NE
? EQ
: NE
);
10514 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10515 (eq (and (lshiftrt X) 1) 0).
10516 Also handle the case where (not X) is expressed using xor. */
10517 if (const_op
== 0 && equality_comparison_p
10518 && XEXP (op0
, 1) == const1_rtx
10519 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
10521 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
10522 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
10524 if (GET_CODE (shift_op
) == NOT
10525 || (GET_CODE (shift_op
) == XOR
10526 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
10527 && GET_CODE (shift_count
) == CONST_INT
10528 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10529 && (INTVAL (XEXP (shift_op
, 1))
10530 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
10532 op0
= simplify_and_const_int
10534 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
10535 (HOST_WIDE_INT
) 1);
10536 code
= (code
== NE
? EQ
: NE
);
10543 /* If we have (compare (ashift FOO N) (const_int C)) and
10544 the high order N bits of FOO (N+1 if an inequality comparison)
10545 are known to be zero, we can do this by comparing FOO with C
10546 shifted right N bits so long as the low-order N bits of C are
10548 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10549 && INTVAL (XEXP (op0
, 1)) >= 0
10550 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10551 < HOST_BITS_PER_WIDE_INT
)
10553 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10554 && mode_width
<= HOST_BITS_PER_WIDE_INT
10555 && (nonzero_bits (XEXP (op0
, 0), mode
)
10556 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10557 + ! equality_comparison_p
))) == 0)
10559 /* We must perform a logical shift, not an arithmetic one,
10560 as we want the top N bits of C to be zero. */
10561 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10563 temp
>>= INTVAL (XEXP (op0
, 1));
10564 op1
= gen_int_mode (temp
, mode
);
10565 op0
= XEXP (op0
, 0);
10569 /* If we are doing a sign bit comparison, it means we are testing
10570 a particular bit. Convert it to the appropriate AND. */
10571 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10572 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10574 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10577 - INTVAL (XEXP (op0
, 1)))));
10578 code
= (code
== LT
? NE
: EQ
);
10582 /* If this an equality comparison with zero and we are shifting
10583 the low bit to the sign bit, we can convert this to an AND of the
10585 if (const_op
== 0 && equality_comparison_p
10586 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10587 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10590 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10591 (HOST_WIDE_INT
) 1);
10597 /* If this is an equality comparison with zero, we can do this
10598 as a logical shift, which might be much simpler. */
10599 if (equality_comparison_p
&& const_op
== 0
10600 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10602 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10604 INTVAL (XEXP (op0
, 1)));
10608 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10609 do the comparison in a narrower mode. */
10610 if (! unsigned_comparison_p
10611 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10612 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10613 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10614 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10615 MODE_INT
, 1)) != BLKmode
10616 && (((unsigned HOST_WIDE_INT
) const_op
10617 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10618 <= GET_MODE_MASK (tmode
)))
10620 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
10624 /* Likewise if OP0 is a PLUS of a sign extension with a
10625 constant, which is usually represented with the PLUS
10626 between the shifts. */
10627 if (! unsigned_comparison_p
10628 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10629 && GET_CODE (XEXP (op0
, 0)) == PLUS
10630 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10631 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10632 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10633 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10634 MODE_INT
, 1)) != BLKmode
10635 && (((unsigned HOST_WIDE_INT
) const_op
10636 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10637 <= GET_MODE_MASK (tmode
)))
10639 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10640 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10641 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
10642 add_const
, XEXP (op0
, 1));
10644 op0
= simplify_gen_binary (PLUS
, tmode
,
10645 gen_lowpart (tmode
, inner
),
10650 /* ... fall through ... */
10652 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10653 the low order N bits of FOO are known to be zero, we can do this
10654 by comparing FOO with C shifted left N bits so long as no
10655 overflow occurs. */
10656 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10657 && INTVAL (XEXP (op0
, 1)) >= 0
10658 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10659 && mode_width
<= HOST_BITS_PER_WIDE_INT
10660 && (nonzero_bits (XEXP (op0
, 0), mode
)
10661 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10662 && (((unsigned HOST_WIDE_INT
) const_op
10663 + (GET_CODE (op0
) != LSHIFTRT
10664 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
10667 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
10669 /* If the shift was logical, then we must make the condition
10671 if (GET_CODE (op0
) == LSHIFTRT
)
10672 code
= unsigned_condition (code
);
10674 const_op
<<= INTVAL (XEXP (op0
, 1));
10675 op1
= GEN_INT (const_op
);
10676 op0
= XEXP (op0
, 0);
10680 /* If we are using this shift to extract just the sign bit, we
10681 can replace this with an LT or GE comparison. */
10683 && (equality_comparison_p
|| sign_bit_comparison_p
)
10684 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10685 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10688 op0
= XEXP (op0
, 0);
10689 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10701 /* Now make any compound operations involved in this comparison. Then,
10702 check for an outmost SUBREG on OP0 that is not doing anything or is
10703 paradoxical. The latter transformation must only be performed when
10704 it is known that the "extra" bits will be the same in op0 and op1 or
10705 that they don't matter. There are three cases to consider:
10707 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10708 care bits and we can assume they have any convenient value. So
10709 making the transformation is safe.
10711 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10712 In this case the upper bits of op0 are undefined. We should not make
10713 the simplification in that case as we do not know the contents of
10716 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10717 UNKNOWN. In that case we know those bits are zeros or ones. We must
10718 also be sure that they are the same as the upper bits of op1.
10720 We can never remove a SUBREG for a non-equality comparison because
10721 the sign bit is in a different place in the underlying object. */
10723 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10724 op1
= make_compound_operation (op1
, SET
);
10726 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10727 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10728 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
10729 && (code
== NE
|| code
== EQ
))
10731 if (GET_MODE_SIZE (GET_MODE (op0
))
10732 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
10734 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10736 if (REG_P (SUBREG_REG (op0
)))
10738 op0
= SUBREG_REG (op0
);
10739 op1
= gen_lowpart (GET_MODE (op0
), op1
);
10742 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10743 <= HOST_BITS_PER_WIDE_INT
)
10744 && (nonzero_bits (SUBREG_REG (op0
),
10745 GET_MODE (SUBREG_REG (op0
)))
10746 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10748 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
10750 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10751 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10752 op0
= SUBREG_REG (op0
), op1
= tem
;
10756 /* We now do the opposite procedure: Some machines don't have compare
10757 insns in all modes. If OP0's mode is an integer mode smaller than a
10758 word and we can't do a compare in that mode, see if there is a larger
10759 mode for which we can do the compare. There are a number of cases in
10760 which we can use the wider mode. */
10762 mode
= GET_MODE (op0
);
10763 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10764 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10765 && ! have_insn_for (COMPARE
, mode
))
10766 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10768 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10769 tmode
= GET_MODE_WIDER_MODE (tmode
))
10770 if (have_insn_for (COMPARE
, tmode
))
10774 /* If the only nonzero bits in OP0 and OP1 are those in the
10775 narrower mode and this is an equality or unsigned comparison,
10776 we can use the wider mode. Similarly for sign-extended
10777 values, in which case it is true for all comparisons. */
10778 zero_extended
= ((code
== EQ
|| code
== NE
10779 || code
== GEU
|| code
== GTU
10780 || code
== LEU
|| code
== LTU
)
10781 && (nonzero_bits (op0
, tmode
)
10782 & ~GET_MODE_MASK (mode
)) == 0
10783 && ((GET_CODE (op1
) == CONST_INT
10784 || (nonzero_bits (op1
, tmode
)
10785 & ~GET_MODE_MASK (mode
)) == 0)));
10788 || ((num_sign_bit_copies (op0
, tmode
)
10789 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10790 - GET_MODE_BITSIZE (mode
)))
10791 && (num_sign_bit_copies (op1
, tmode
)
10792 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10793 - GET_MODE_BITSIZE (mode
)))))
10795 /* If OP0 is an AND and we don't have an AND in MODE either,
10796 make a new AND in the proper mode. */
10797 if (GET_CODE (op0
) == AND
10798 && !have_insn_for (AND
, mode
))
10799 op0
= simplify_gen_binary (AND
, tmode
,
10800 gen_lowpart (tmode
,
10802 gen_lowpart (tmode
,
10805 op0
= gen_lowpart (tmode
, op0
);
10806 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
10807 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
10808 op1
= gen_lowpart (tmode
, op1
);
10812 /* If this is a test for negative, we can make an explicit
10813 test of the sign bit. */
10815 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10816 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10818 op0
= simplify_gen_binary (AND
, tmode
,
10819 gen_lowpart (tmode
, op0
),
10820 GEN_INT ((HOST_WIDE_INT
) 1
10821 << (GET_MODE_BITSIZE (mode
)
10823 code
= (code
== LT
) ? NE
: EQ
;
10828 #ifdef CANONICALIZE_COMPARISON
10829 /* If this machine only supports a subset of valid comparisons, see if we
10830 can convert an unsupported one into a supported one. */
10831 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10840 /* Utility function for record_value_for_reg. Count number of
10845 enum rtx_code code
= GET_CODE (x
);
10849 if (GET_RTX_CLASS (code
) == '2'
10850 || GET_RTX_CLASS (code
) == 'c')
10852 rtx x0
= XEXP (x
, 0);
10853 rtx x1
= XEXP (x
, 1);
10856 return 1 + 2 * count_rtxs (x0
);
10858 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
10859 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
10860 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
10861 return 2 + 2 * count_rtxs (x0
)
10862 + count_rtxs (x
== XEXP (x1
, 0)
10863 ? XEXP (x1
, 1) : XEXP (x1
, 0));
10865 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
10866 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
10867 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
10868 return 2 + 2 * count_rtxs (x1
)
10869 + count_rtxs (x
== XEXP (x0
, 0)
10870 ? XEXP (x0
, 1) : XEXP (x0
, 0));
10873 fmt
= GET_RTX_FORMAT (code
);
10874 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10876 ret
+= count_rtxs (XEXP (x
, i
));
10881 /* Utility function for following routine. Called when X is part of a value
10882 being stored into last_set_value. Sets last_set_table_tick
10883 for each register mentioned. Similar to mention_regs in cse.c */
10886 update_table_tick (rtx x
)
10888 enum rtx_code code
= GET_CODE (x
);
10889 const char *fmt
= GET_RTX_FORMAT (code
);
10894 unsigned int regno
= REGNO (x
);
10895 unsigned int endregno
10896 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10897 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
10900 for (r
= regno
; r
< endregno
; r
++)
10901 reg_stat
[r
].last_set_table_tick
= label_tick
;
10906 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10907 /* Note that we can't have an "E" in values stored; see
10908 get_last_value_validate. */
10911 /* Check for identical subexpressions. If x contains
10912 identical subexpression we only have to traverse one of
10914 if (i
== 0 && ARITHMETIC_P (x
))
10916 /* Note that at this point x1 has already been
10918 rtx x0
= XEXP (x
, 0);
10919 rtx x1
= XEXP (x
, 1);
10921 /* If x0 and x1 are identical then there is no need to
10926 /* If x0 is identical to a subexpression of x1 then while
10927 processing x1, x0 has already been processed. Thus we
10928 are done with x. */
10929 if (ARITHMETIC_P (x1
)
10930 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
10933 /* If x1 is identical to a subexpression of x0 then we
10934 still have to process the rest of x0. */
10935 if (ARITHMETIC_P (x0
)
10936 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
10938 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
10943 update_table_tick (XEXP (x
, i
));
10947 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10948 are saying that the register is clobbered and we no longer know its
10949 value. If INSN is zero, don't update reg_stat[].last_set; this is
10950 only permitted with VALUE also zero and is used to invalidate the
10954 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
10956 unsigned int regno
= REGNO (reg
);
10957 unsigned int endregno
10958 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10959 ? hard_regno_nregs
[regno
][GET_MODE (reg
)] : 1);
10962 /* If VALUE contains REG and we have a previous value for REG, substitute
10963 the previous value. */
10964 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
10968 /* Set things up so get_last_value is allowed to see anything set up to
10970 subst_low_cuid
= INSN_CUID (insn
);
10971 tem
= get_last_value (reg
);
10973 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10974 it isn't going to be useful and will take a lot of time to process,
10975 so just use the CLOBBER. */
10979 if (ARITHMETIC_P (tem
)
10980 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
10981 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
10982 tem
= XEXP (tem
, 0);
10983 else if (count_occurrences (value
, reg
, 1) >= 2)
10985 /* If there are two or more occurrences of REG in VALUE,
10986 prevent the value from growing too much. */
10987 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
10988 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
10991 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
10995 /* For each register modified, show we don't know its value, that
10996 we don't know about its bitwise content, that its value has been
10997 updated, and that we don't know the location of the death of the
10999 for (i
= regno
; i
< endregno
; i
++)
11002 reg_stat
[i
].last_set
= insn
;
11004 reg_stat
[i
].last_set_value
= 0;
11005 reg_stat
[i
].last_set_mode
= 0;
11006 reg_stat
[i
].last_set_nonzero_bits
= 0;
11007 reg_stat
[i
].last_set_sign_bit_copies
= 0;
11008 reg_stat
[i
].last_death
= 0;
11011 /* Mark registers that are being referenced in this value. */
11013 update_table_tick (value
);
11015 /* Now update the status of each register being set.
11016 If someone is using this register in this block, set this register
11017 to invalid since we will get confused between the two lives in this
11018 basic block. This makes using this register always invalid. In cse, we
11019 scan the table to invalidate all entries using this register, but this
11020 is too much work for us. */
11022 for (i
= regno
; i
< endregno
; i
++)
11024 reg_stat
[i
].last_set_label
= label_tick
;
11025 if (value
&& reg_stat
[i
].last_set_table_tick
== label_tick
)
11026 reg_stat
[i
].last_set_invalid
= 1;
11028 reg_stat
[i
].last_set_invalid
= 0;
11031 /* The value being assigned might refer to X (like in "x++;"). In that
11032 case, we must replace it with (clobber (const_int 0)) to prevent
11034 if (value
&& ! get_last_value_validate (&value
, insn
,
11035 reg_stat
[regno
].last_set_label
, 0))
11037 value
= copy_rtx (value
);
11038 if (! get_last_value_validate (&value
, insn
,
11039 reg_stat
[regno
].last_set_label
, 1))
11043 /* For the main register being modified, update the value, the mode, the
11044 nonzero bits, and the number of sign bit copies. */
11046 reg_stat
[regno
].last_set_value
= value
;
11050 enum machine_mode mode
= GET_MODE (reg
);
11051 subst_low_cuid
= INSN_CUID (insn
);
11052 reg_stat
[regno
].last_set_mode
= mode
;
11053 if (GET_MODE_CLASS (mode
) == MODE_INT
11054 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11055 mode
= nonzero_bits_mode
;
11056 reg_stat
[regno
].last_set_nonzero_bits
= nonzero_bits (value
, mode
);
11057 reg_stat
[regno
].last_set_sign_bit_copies
11058 = num_sign_bit_copies (value
, GET_MODE (reg
));
11062 /* Called via note_stores from record_dead_and_set_regs to handle one
11063 SET or CLOBBER in an insn. DATA is the instruction in which the
11064 set is occurring. */
11067 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
11069 rtx record_dead_insn
= (rtx
) data
;
11071 if (GET_CODE (dest
) == SUBREG
)
11072 dest
= SUBREG_REG (dest
);
11076 /* If we are setting the whole register, we know its value. Otherwise
11077 show that we don't know the value. We can handle SUBREG in
11079 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11080 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11081 else if (GET_CODE (setter
) == SET
11082 && GET_CODE (SET_DEST (setter
)) == SUBREG
11083 && SUBREG_REG (SET_DEST (setter
)) == dest
11084 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11085 && subreg_lowpart_p (SET_DEST (setter
)))
11086 record_value_for_reg (dest
, record_dead_insn
,
11087 gen_lowpart (GET_MODE (dest
),
11088 SET_SRC (setter
)));
11090 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11092 else if (MEM_P (dest
)
11093 /* Ignore pushes, they clobber nothing. */
11094 && ! push_operand (dest
, GET_MODE (dest
)))
11095 mem_last_set
= INSN_CUID (record_dead_insn
);
11098 /* Update the records of when each REG was most recently set or killed
11099 for the things done by INSN. This is the last thing done in processing
11100 INSN in the combiner loop.
11102 We update reg_stat[], in particular fields last_set, last_set_value,
11103 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11104 last_death, and also the similar information mem_last_set (which insn
11105 most recently modified memory) and last_call_cuid (which insn was the
11106 most recent subroutine call). */
11109 record_dead_and_set_regs (rtx insn
)
11114 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11116 if (REG_NOTE_KIND (link
) == REG_DEAD
11117 && REG_P (XEXP (link
, 0)))
11119 unsigned int regno
= REGNO (XEXP (link
, 0));
11120 unsigned int endregno
11121 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11122 ? hard_regno_nregs
[regno
][GET_MODE (XEXP (link
, 0))]
11125 for (i
= regno
; i
< endregno
; i
++)
11126 reg_stat
[i
].last_death
= insn
;
11128 else if (REG_NOTE_KIND (link
) == REG_INC
)
11129 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11134 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11135 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11137 reg_stat
[i
].last_set_value
= 0;
11138 reg_stat
[i
].last_set_mode
= 0;
11139 reg_stat
[i
].last_set_nonzero_bits
= 0;
11140 reg_stat
[i
].last_set_sign_bit_copies
= 0;
11141 reg_stat
[i
].last_death
= 0;
11144 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11146 /* Don't bother recording what this insn does. It might set the
11147 return value register, but we can't combine into a call
11148 pattern anyway, so there's no point trying (and it may cause
11149 a crash, if e.g. we wind up asking for last_set_value of a
11150 SUBREG of the return value register). */
11154 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11157 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11158 register present in the SUBREG, so for each such SUBREG go back and
11159 adjust nonzero and sign bit information of the registers that are
11160 known to have some zero/sign bits set.
11162 This is needed because when combine blows the SUBREGs away, the
11163 information on zero/sign bits is lost and further combines can be
11164 missed because of that. */
11167 record_promoted_value (rtx insn
, rtx subreg
)
11170 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11171 enum machine_mode mode
= GET_MODE (subreg
);
11173 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11176 for (links
= LOG_LINKS (insn
); links
;)
11178 insn
= XEXP (links
, 0);
11179 set
= single_set (insn
);
11181 if (! set
|| !REG_P (SET_DEST (set
))
11182 || REGNO (SET_DEST (set
)) != regno
11183 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11185 links
= XEXP (links
, 1);
11189 if (reg_stat
[regno
].last_set
== insn
)
11191 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11192 reg_stat
[regno
].last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
11195 if (REG_P (SET_SRC (set
)))
11197 regno
= REGNO (SET_SRC (set
));
11198 links
= LOG_LINKS (insn
);
11205 /* Scan X for promoted SUBREGs. For each one found,
11206 note what it implies to the registers used in it. */
11209 check_promoted_subreg (rtx insn
, rtx x
)
11211 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11212 && REG_P (SUBREG_REG (x
)))
11213 record_promoted_value (insn
, x
);
11216 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11219 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11223 check_promoted_subreg (insn
, XEXP (x
, i
));
11227 if (XVEC (x
, i
) != 0)
11228 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11229 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11235 /* Utility routine for the following function. Verify that all the registers
11236 mentioned in *LOC are valid when *LOC was part of a value set when
11237 label_tick == TICK. Return 0 if some are not.
11239 If REPLACE is nonzero, replace the invalid reference with
11240 (clobber (const_int 0)) and return 1. This replacement is useful because
11241 we often can get useful information about the form of a value (e.g., if
11242 it was produced by a shift that always produces -1 or 0) even though
11243 we don't know exactly what registers it was produced from. */
11246 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11249 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11250 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11255 unsigned int regno
= REGNO (x
);
11256 unsigned int endregno
11257 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11258 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11261 for (j
= regno
; j
< endregno
; j
++)
11262 if (reg_stat
[j
].last_set_invalid
11263 /* If this is a pseudo-register that was only set once and not
11264 live at the beginning of the function, it is always valid. */
11265 || (! (regno
>= FIRST_PSEUDO_REGISTER
11266 && REG_N_SETS (regno
) == 1
11267 && (! REGNO_REG_SET_P
11268 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
,
11270 && reg_stat
[j
].last_set_label
> tick
))
11273 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11279 /* If this is a memory reference, make sure that there were
11280 no stores after it that might have clobbered the value. We don't
11281 have alias info, so we assume any store invalidates it. */
11282 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
11283 && INSN_CUID (insn
) <= mem_last_set
)
11286 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11290 for (i
= 0; i
< len
; i
++)
11294 /* Check for identical subexpressions. If x contains
11295 identical subexpression we only have to traverse one of
11297 if (i
== 1 && ARITHMETIC_P (x
))
11299 /* Note that at this point x0 has already been checked
11300 and found valid. */
11301 rtx x0
= XEXP (x
, 0);
11302 rtx x1
= XEXP (x
, 1);
11304 /* If x0 and x1 are identical then x is also valid. */
11308 /* If x1 is identical to a subexpression of x0 then
11309 while checking x0, x1 has already been checked. Thus
11310 it is valid and so as x. */
11311 if (ARITHMETIC_P (x0
)
11312 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11315 /* If x0 is identical to a subexpression of x1 then x is
11316 valid iff the rest of x1 is valid. */
11317 if (ARITHMETIC_P (x1
)
11318 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11320 get_last_value_validate (&XEXP (x1
,
11321 x0
== XEXP (x1
, 0) ? 1 : 0),
11322 insn
, tick
, replace
);
11325 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11329 /* Don't bother with these. They shouldn't occur anyway. */
11330 else if (fmt
[i
] == 'E')
11334 /* If we haven't found a reason for it to be invalid, it is valid. */
11338 /* Get the last value assigned to X, if known. Some registers
11339 in the value may be replaced with (clobber (const_int 0)) if their value
11340 is known longer known reliably. */
11343 get_last_value (rtx x
)
11345 unsigned int regno
;
11348 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11349 then convert it to the desired mode. If this is a paradoxical SUBREG,
11350 we cannot predict what values the "extra" bits might have. */
11351 if (GET_CODE (x
) == SUBREG
11352 && subreg_lowpart_p (x
)
11353 && (GET_MODE_SIZE (GET_MODE (x
))
11354 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11355 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11356 return gen_lowpart (GET_MODE (x
), value
);
11362 value
= reg_stat
[regno
].last_set_value
;
11364 /* If we don't have a value, or if it isn't for this basic block and
11365 it's either a hard register, set more than once, or it's a live
11366 at the beginning of the function, return 0.
11368 Because if it's not live at the beginning of the function then the reg
11369 is always set before being used (is never used without being set).
11370 And, if it's set only once, and it's always set before use, then all
11371 uses must have the same last value, even if it's not from this basic
11375 || (reg_stat
[regno
].last_set_label
!= label_tick
11376 && (regno
< FIRST_PSEUDO_REGISTER
11377 || REG_N_SETS (regno
) != 1
11378 || (REGNO_REG_SET_P
11379 (ENTRY_BLOCK_PTR
->next_bb
->il
.rtl
->global_live_at_start
,
11383 /* If the value was set in a later insn than the ones we are processing,
11384 we can't use it even if the register was only set once. */
11385 if (INSN_CUID (reg_stat
[regno
].last_set
) >= subst_low_cuid
)
11388 /* If the value has all its registers valid, return it. */
11389 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11390 reg_stat
[regno
].last_set_label
, 0))
11393 /* Otherwise, make a copy and replace any invalid register with
11394 (clobber (const_int 0)). If that fails for some reason, return 0. */
11396 value
= copy_rtx (value
);
11397 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11398 reg_stat
[regno
].last_set_label
, 1))
11404 /* Return nonzero if expression X refers to a REG or to memory
11405 that is set in an instruction more recent than FROM_CUID. */
11408 use_crosses_set_p (rtx x
, int from_cuid
)
11412 enum rtx_code code
= GET_CODE (x
);
11416 unsigned int regno
= REGNO (x
);
11417 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11418 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11420 #ifdef PUSH_ROUNDING
11421 /* Don't allow uses of the stack pointer to be moved,
11422 because we don't know whether the move crosses a push insn. */
11423 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11426 for (; regno
< endreg
; regno
++)
11427 if (reg_stat
[regno
].last_set
11428 && INSN_CUID (reg_stat
[regno
].last_set
) > from_cuid
)
11433 if (code
== MEM
&& mem_last_set
> from_cuid
)
11436 fmt
= GET_RTX_FORMAT (code
);
11438 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11443 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11444 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11447 else if (fmt
[i
] == 'e'
11448 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11454 /* Define three variables used for communication between the following
11457 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11458 static int reg_dead_flag
;
11460 /* Function called via note_stores from reg_dead_at_p.
11462 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11463 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11466 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11468 unsigned int regno
, endregno
;
11473 regno
= REGNO (dest
);
11474 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11475 ? hard_regno_nregs
[regno
][GET_MODE (dest
)] : 1);
11477 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11478 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11481 /* Return nonzero if REG is known to be dead at INSN.
11483 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11484 referencing REG, it is dead. If we hit a SET referencing REG, it is
11485 live. Otherwise, see if it is live or dead at the start of the basic
11486 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11487 must be assumed to be always live. */
11490 reg_dead_at_p (rtx reg
, rtx insn
)
11495 /* Set variables for reg_dead_at_p_1. */
11496 reg_dead_regno
= REGNO (reg
);
11497 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11498 ? hard_regno_nregs
[reg_dead_regno
]
11504 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11505 we allow the machine description to decide whether use-and-clobber
11506 patterns are OK. */
11507 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11509 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11510 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11514 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11515 beginning of function. */
11516 for (; insn
&& !LABEL_P (insn
) && !BARRIER_P (insn
);
11517 insn
= prev_nonnote_insn (insn
))
11519 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11521 return reg_dead_flag
== 1 ? 1 : 0;
11523 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11527 /* Get the basic block that we were in. */
11529 block
= ENTRY_BLOCK_PTR
->next_bb
;
11532 FOR_EACH_BB (block
)
11533 if (insn
== BB_HEAD (block
))
11536 if (block
== EXIT_BLOCK_PTR
)
11540 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11541 if (REGNO_REG_SET_P (block
->il
.rtl
->global_live_at_start
, i
))
11547 /* Note hard registers in X that are used. This code is similar to
11548 that in flow.c, but much simpler since we don't care about pseudos. */
11551 mark_used_regs_combine (rtx x
)
11553 RTX_CODE code
= GET_CODE (x
);
11554 unsigned int regno
;
11567 case ADDR_DIFF_VEC
:
11570 /* CC0 must die in the insn after it is set, so we don't need to take
11571 special note of it here. */
11577 /* If we are clobbering a MEM, mark any hard registers inside the
11578 address as used. */
11579 if (MEM_P (XEXP (x
, 0)))
11580 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11585 /* A hard reg in a wide mode may really be multiple registers.
11586 If so, mark all of them just like the first. */
11587 if (regno
< FIRST_PSEUDO_REGISTER
)
11589 unsigned int endregno
, r
;
11591 /* None of this applies to the stack, frame or arg pointers. */
11592 if (regno
== STACK_POINTER_REGNUM
11593 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11594 || regno
== HARD_FRAME_POINTER_REGNUM
11596 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11597 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11599 || regno
== FRAME_POINTER_REGNUM
)
11602 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11603 for (r
= regno
; r
< endregno
; r
++)
11604 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11610 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11612 rtx testreg
= SET_DEST (x
);
11614 while (GET_CODE (testreg
) == SUBREG
11615 || GET_CODE (testreg
) == ZERO_EXTRACT
11616 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11617 testreg
= XEXP (testreg
, 0);
11619 if (MEM_P (testreg
))
11620 mark_used_regs_combine (XEXP (testreg
, 0));
11622 mark_used_regs_combine (SET_SRC (x
));
11630 /* Recursively scan the operands of this expression. */
11633 const char *fmt
= GET_RTX_FORMAT (code
);
11635 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11638 mark_used_regs_combine (XEXP (x
, i
));
11639 else if (fmt
[i
] == 'E')
11643 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11644 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11650 /* Remove register number REGNO from the dead registers list of INSN.
11652 Return the note used to record the death, if there was one. */
11655 remove_death (unsigned int regno
, rtx insn
)
11657 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11661 REG_N_DEATHS (regno
)--;
11662 remove_note (insn
, note
);
11668 /* For each register (hardware or pseudo) used within expression X, if its
11669 death is in an instruction with cuid between FROM_CUID (inclusive) and
11670 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11671 list headed by PNOTES.
11673 That said, don't move registers killed by maybe_kill_insn.
11675 This is done when X is being merged by combination into TO_INSN. These
11676 notes will then be distributed as needed. */
11679 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
11684 enum rtx_code code
= GET_CODE (x
);
11688 unsigned int regno
= REGNO (x
);
11689 rtx where_dead
= reg_stat
[regno
].last_death
;
11690 rtx before_dead
, after_dead
;
11692 /* Don't move the register if it gets killed in between from and to. */
11693 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11694 && ! reg_referenced_p (x
, maybe_kill_insn
))
11697 /* WHERE_DEAD could be a USE insn made by combine, so first we
11698 make sure that we have insns with valid INSN_CUID values. */
11699 before_dead
= where_dead
;
11700 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11701 before_dead
= PREV_INSN (before_dead
);
11703 after_dead
= where_dead
;
11704 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11705 after_dead
= NEXT_INSN (after_dead
);
11707 if (before_dead
&& after_dead
11708 && INSN_CUID (before_dead
) >= from_cuid
11709 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11710 || (where_dead
!= after_dead
11711 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11713 rtx note
= remove_death (regno
, where_dead
);
11715 /* It is possible for the call above to return 0. This can occur
11716 when last_death points to I2 or I1 that we combined with.
11717 In that case make a new note.
11719 We must also check for the case where X is a hard register
11720 and NOTE is a death note for a range of hard registers
11721 including X. In that case, we must put REG_DEAD notes for
11722 the remaining registers in place of NOTE. */
11724 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11725 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11726 > GET_MODE_SIZE (GET_MODE (x
))))
11728 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11729 unsigned int deadend
11730 = (deadregno
+ hard_regno_nregs
[deadregno
]
11731 [GET_MODE (XEXP (note
, 0))]);
11732 unsigned int ourend
11733 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11736 for (i
= deadregno
; i
< deadend
; i
++)
11737 if (i
< regno
|| i
>= ourend
)
11738 REG_NOTES (where_dead
)
11739 = gen_rtx_EXPR_LIST (REG_DEAD
,
11741 REG_NOTES (where_dead
));
11744 /* If we didn't find any note, or if we found a REG_DEAD note that
11745 covers only part of the given reg, and we have a multi-reg hard
11746 register, then to be safe we must check for REG_DEAD notes
11747 for each register other than the first. They could have
11748 their own REG_DEAD notes lying around. */
11749 else if ((note
== 0
11751 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11752 < GET_MODE_SIZE (GET_MODE (x
)))))
11753 && regno
< FIRST_PSEUDO_REGISTER
11754 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
11756 unsigned int ourend
11757 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11758 unsigned int i
, offset
;
11762 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
11766 for (i
= regno
+ offset
; i
< ourend
; i
++)
11767 move_deaths (regno_reg_rtx
[i
],
11768 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11771 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11773 XEXP (note
, 1) = *pnotes
;
11777 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11779 REG_N_DEATHS (regno
)++;
11785 else if (GET_CODE (x
) == SET
)
11787 rtx dest
= SET_DEST (x
);
11789 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11791 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11792 that accesses one word of a multi-word item, some
11793 piece of everything register in the expression is used by
11794 this insn, so remove any old death. */
11795 /* ??? So why do we test for equality of the sizes? */
11797 if (GET_CODE (dest
) == ZERO_EXTRACT
11798 || GET_CODE (dest
) == STRICT_LOW_PART
11799 || (GET_CODE (dest
) == SUBREG
11800 && (((GET_MODE_SIZE (GET_MODE (dest
))
11801 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11802 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11803 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11805 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11809 /* If this is some other SUBREG, we know it replaces the entire
11810 value, so use that as the destination. */
11811 if (GET_CODE (dest
) == SUBREG
)
11812 dest
= SUBREG_REG (dest
);
11814 /* If this is a MEM, adjust deaths of anything used in the address.
11815 For a REG (the only other possibility), the entire value is
11816 being replaced so the old value is not used in this insn. */
11819 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11824 else if (GET_CODE (x
) == CLOBBER
)
11827 len
= GET_RTX_LENGTH (code
);
11828 fmt
= GET_RTX_FORMAT (code
);
11830 for (i
= 0; i
< len
; i
++)
11835 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11836 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11839 else if (fmt
[i
] == 'e')
11840 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11844 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11845 pattern of an insn. X must be a REG. */
11848 reg_bitfield_target_p (rtx x
, rtx body
)
11852 if (GET_CODE (body
) == SET
)
11854 rtx dest
= SET_DEST (body
);
11856 unsigned int regno
, tregno
, endregno
, endtregno
;
11858 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11859 target
= XEXP (dest
, 0);
11860 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11861 target
= SUBREG_REG (XEXP (dest
, 0));
11865 if (GET_CODE (target
) == SUBREG
)
11866 target
= SUBREG_REG (target
);
11868 if (!REG_P (target
))
11871 tregno
= REGNO (target
), regno
= REGNO (x
);
11872 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11873 return target
== x
;
11875 endtregno
= tregno
+ hard_regno_nregs
[tregno
][GET_MODE (target
)];
11876 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11878 return endregno
> tregno
&& regno
< endtregno
;
11881 else if (GET_CODE (body
) == PARALLEL
)
11882 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11883 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11889 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11890 as appropriate. I3 and I2 are the insns resulting from the combination
11891 insns including FROM (I2 may be zero).
11893 Each note in the list is either ignored or placed on some insns, depending
11894 on the type of note. */
11897 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
11899 rtx note
, next_note
;
11902 for (note
= notes
; note
; note
= next_note
)
11904 rtx place
= 0, place2
= 0;
11906 /* If this NOTE references a pseudo register, ensure it references
11907 the latest copy of that register. */
11908 if (XEXP (note
, 0) && REG_P (XEXP (note
, 0))
11909 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
11910 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
11912 next_note
= XEXP (note
, 1);
11913 switch (REG_NOTE_KIND (note
))
11917 /* Doesn't matter much where we put this, as long as it's somewhere.
11918 It is preferable to keep these notes on branches, which is most
11919 likely to be i3. */
11923 case REG_VALUE_PROFILE
:
11924 /* Just get rid of this note, as it is unused later anyway. */
11927 case REG_NON_LOCAL_GOTO
:
11932 gcc_assert (i2
&& JUMP_P (i2
));
11937 case REG_EH_REGION
:
11938 /* These notes must remain with the call or trapping instruction. */
11941 else if (i2
&& CALL_P (i2
))
11945 gcc_assert (flag_non_call_exceptions
);
11946 if (may_trap_p (i3
))
11948 else if (i2
&& may_trap_p (i2
))
11950 /* ??? Otherwise assume we've combined things such that we
11951 can now prove that the instructions can't trap. Drop the
11952 note in this case. */
11958 /* These notes must remain with the call. It should not be
11959 possible for both I2 and I3 to be a call. */
11964 gcc_assert (i2
&& CALL_P (i2
));
11970 /* Any clobbers for i3 may still exist, and so we must process
11971 REG_UNUSED notes from that insn.
11973 Any clobbers from i2 or i1 can only exist if they were added by
11974 recog_for_combine. In that case, recog_for_combine created the
11975 necessary REG_UNUSED notes. Trying to keep any original
11976 REG_UNUSED notes from these insns can cause incorrect output
11977 if it is for the same register as the original i3 dest.
11978 In that case, we will notice that the register is set in i3,
11979 and then add a REG_UNUSED note for the destination of i3, which
11980 is wrong. However, it is possible to have REG_UNUSED notes from
11981 i2 or i1 for register which were both used and clobbered, so
11982 we keep notes from i2 or i1 if they will turn into REG_DEAD
11985 /* If this register is set or clobbered in I3, put the note there
11986 unless there is one already. */
11987 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
11989 if (from_insn
!= i3
)
11992 if (! (REG_P (XEXP (note
, 0))
11993 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
11994 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
11997 /* Otherwise, if this register is used by I3, then this register
11998 now dies here, so we must put a REG_DEAD note here unless there
12000 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12001 && ! (REG_P (XEXP (note
, 0))
12002 ? find_regno_note (i3
, REG_DEAD
,
12003 REGNO (XEXP (note
, 0)))
12004 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12006 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12014 /* These notes say something about results of an insn. We can
12015 only support them if they used to be on I3 in which case they
12016 remain on I3. Otherwise they are ignored.
12018 If the note refers to an expression that is not a constant, we
12019 must also ignore the note since we cannot tell whether the
12020 equivalence is still true. It might be possible to do
12021 slightly better than this (we only have a problem if I2DEST
12022 or I1DEST is present in the expression), but it doesn't
12023 seem worth the trouble. */
12025 if (from_insn
== i3
12026 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12031 case REG_NO_CONFLICT
:
12032 /* These notes say something about how a register is used. They must
12033 be present on any use of the register in I2 or I3. */
12034 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12037 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12047 /* This can show up in several ways -- either directly in the
12048 pattern, or hidden off in the constant pool with (or without?)
12049 a REG_EQUAL note. */
12050 /* ??? Ignore the without-reg_equal-note problem for now. */
12051 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12052 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12053 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12054 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12058 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12059 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12060 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12061 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12069 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
12070 a JUMP_LABEL instead or decrement LABEL_NUSES. */
12071 if (place
&& JUMP_P (place
))
12073 rtx label
= JUMP_LABEL (place
);
12076 JUMP_LABEL (place
) = XEXP (note
, 0);
12079 gcc_assert (label
== XEXP (note
, 0));
12080 if (LABEL_P (label
))
12081 LABEL_NUSES (label
)--;
12085 if (place2
&& JUMP_P (place2
))
12087 rtx label
= JUMP_LABEL (place2
);
12090 JUMP_LABEL (place2
) = XEXP (note
, 0);
12093 gcc_assert (label
== XEXP (note
, 0));
12094 if (LABEL_P (label
))
12095 LABEL_NUSES (label
)--;
12102 /* This note says something about the value of a register prior
12103 to the execution of an insn. It is too much trouble to see
12104 if the note is still correct in all situations. It is better
12105 to simply delete it. */
12109 /* If the insn previously containing this note still exists,
12110 put it back where it was. Otherwise move it to the previous
12111 insn. Adjust the corresponding REG_LIBCALL note. */
12112 if (!NOTE_P (from_insn
))
12116 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12117 place
= prev_real_insn (from_insn
);
12119 XEXP (tem
, 0) = place
;
12120 /* If we're deleting the last remaining instruction of a
12121 libcall sequence, don't add the notes. */
12122 else if (XEXP (note
, 0) == from_insn
)
12124 /* Don't add the dangling REG_RETVAL note. */
12131 /* This is handled similarly to REG_RETVAL. */
12132 if (!NOTE_P (from_insn
))
12136 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12137 place
= next_real_insn (from_insn
);
12139 XEXP (tem
, 0) = place
;
12140 /* If we're deleting the last remaining instruction of a
12141 libcall sequence, don't add the notes. */
12142 else if (XEXP (note
, 0) == from_insn
)
12144 /* Don't add the dangling REG_LIBCALL note. */
12151 /* If the register is used as an input in I3, it dies there.
12152 Similarly for I2, if it is nonzero and adjacent to I3.
12154 If the register is not used as an input in either I3 or I2
12155 and it is not one of the registers we were supposed to eliminate,
12156 there are two possibilities. We might have a non-adjacent I2
12157 or we might have somehow eliminated an additional register
12158 from a computation. For example, we might have had A & B where
12159 we discover that B will always be zero. In this case we will
12160 eliminate the reference to A.
12162 In both cases, we must search to see if we can find a previous
12163 use of A and put the death note there. */
12166 && CALL_P (from_insn
)
12167 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12169 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12171 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12172 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12177 basic_block bb
= this_basic_block
;
12179 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12181 if (! INSN_P (tem
))
12183 if (tem
== BB_HEAD (bb
))
12188 /* If the register is being set at TEM, see if that is all
12189 TEM is doing. If so, delete TEM. Otherwise, make this
12190 into a REG_UNUSED note instead. Don't delete sets to
12191 global register vars. */
12192 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
12193 || !global_regs
[REGNO (XEXP (note
, 0))])
12194 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12196 rtx set
= single_set (tem
);
12197 rtx inner_dest
= 0;
12199 rtx cc0_setter
= NULL_RTX
;
12203 for (inner_dest
= SET_DEST (set
);
12204 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12205 || GET_CODE (inner_dest
) == SUBREG
12206 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12207 inner_dest
= XEXP (inner_dest
, 0))
12210 /* Verify that it was the set, and not a clobber that
12211 modified the register.
12213 CC0 targets must be careful to maintain setter/user
12214 pairs. If we cannot delete the setter due to side
12215 effects, mark the user with an UNUSED note instead
12218 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12219 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12221 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12222 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12223 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12227 /* Move the notes and links of TEM elsewhere.
12228 This might delete other dead insns recursively.
12229 First set the pattern to something that won't use
12231 rtx old_notes
= REG_NOTES (tem
);
12233 PATTERN (tem
) = pc_rtx
;
12234 REG_NOTES (tem
) = NULL
;
12236 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
);
12237 distribute_links (LOG_LINKS (tem
));
12239 SET_INSN_DELETED (tem
);
12242 /* Delete the setter too. */
12245 PATTERN (cc0_setter
) = pc_rtx
;
12246 old_notes
= REG_NOTES (cc0_setter
);
12247 REG_NOTES (cc0_setter
) = NULL
;
12249 distribute_notes (old_notes
, cc0_setter
,
12250 cc0_setter
, NULL_RTX
);
12251 distribute_links (LOG_LINKS (cc0_setter
));
12253 SET_INSN_DELETED (cc0_setter
);
12259 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12261 /* If there isn't already a REG_UNUSED note, put one
12262 here. Do not place a REG_DEAD note, even if
12263 the register is also used here; that would not
12264 match the algorithm used in lifetime analysis
12265 and can cause the consistency check in the
12266 scheduler to fail. */
12267 if (! find_regno_note (tem
, REG_UNUSED
,
12268 REGNO (XEXP (note
, 0))))
12273 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12275 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12279 /* If we are doing a 3->2 combination, and we have a
12280 register which formerly died in i3 and was not used
12281 by i2, which now no longer dies in i3 and is used in
12282 i2 but does not die in i2, and place is between i2
12283 and i3, then we may need to move a link from place to
12285 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12286 && INSN_CUID (place
) > INSN_CUID (i2
)
12288 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12289 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12291 rtx links
= LOG_LINKS (place
);
12292 LOG_LINKS (place
) = 0;
12293 distribute_links (links
);
12298 if (tem
== BB_HEAD (bb
))
12302 /* We haven't found an insn for the death note and it
12303 is still a REG_DEAD note, but we have hit the beginning
12304 of the block. If the existing life info says the reg
12305 was dead, there's nothing left to do. Otherwise, we'll
12306 need to do a global life update after combine. */
12307 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12308 && REGNO_REG_SET_P (bb
->il
.rtl
->global_live_at_start
,
12309 REGNO (XEXP (note
, 0))))
12310 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12313 /* If the register is set or already dead at PLACE, we needn't do
12314 anything with this note if it is still a REG_DEAD note.
12315 We check here if it is set at all, not if is it totally replaced,
12316 which is what `dead_or_set_p' checks, so also check for it being
12319 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12321 unsigned int regno
= REGNO (XEXP (note
, 0));
12323 /* Similarly, if the instruction on which we want to place
12324 the note is a noop, we'll need do a global live update
12325 after we remove them in delete_noop_moves. */
12326 if (noop_move_p (place
))
12327 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12329 if (dead_or_set_p (place
, XEXP (note
, 0))
12330 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12332 /* Unless the register previously died in PLACE, clear
12333 last_death. [I no longer understand why this is
12335 if (reg_stat
[regno
].last_death
!= place
)
12336 reg_stat
[regno
].last_death
= 0;
12340 reg_stat
[regno
].last_death
= place
;
12342 /* If this is a death note for a hard reg that is occupying
12343 multiple registers, ensure that we are still using all
12344 parts of the object. If we find a piece of the object
12345 that is unused, we must arrange for an appropriate REG_DEAD
12346 note to be added for it. However, we can't just emit a USE
12347 and tag the note to it, since the register might actually
12348 be dead; so we recourse, and the recursive call then finds
12349 the previous insn that used this register. */
12351 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12352 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
12354 unsigned int endregno
12355 = regno
+ hard_regno_nregs
[regno
]
12356 [GET_MODE (XEXP (note
, 0))];
12360 for (i
= regno
; i
< endregno
; i
++)
12361 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12362 && ! find_regno_fusage (place
, USE
, i
))
12363 || dead_or_set_regno_p (place
, i
))
12368 /* Put only REG_DEAD notes for pieces that are
12369 not already dead or set. */
12371 for (i
= regno
; i
< endregno
;
12372 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12374 rtx piece
= regno_reg_rtx
[i
];
12375 basic_block bb
= this_basic_block
;
12377 if (! dead_or_set_p (place
, piece
)
12378 && ! reg_bitfield_target_p (piece
,
12382 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12384 distribute_notes (new_note
, place
, place
,
12387 else if (! refers_to_regno_p (i
, i
+ 1,
12388 PATTERN (place
), 0)
12389 && ! find_regno_fusage (place
, USE
, i
))
12390 for (tem
= PREV_INSN (place
); ;
12391 tem
= PREV_INSN (tem
))
12393 if (! INSN_P (tem
))
12395 if (tem
== BB_HEAD (bb
))
12397 SET_BIT (refresh_blocks
,
12398 this_basic_block
->index
);
12403 if (dead_or_set_p (tem
, piece
)
12404 || reg_bitfield_target_p (piece
,
12408 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12423 /* Any other notes should not be present at this point in the
12425 gcc_unreachable ();
12430 XEXP (note
, 1) = REG_NOTES (place
);
12431 REG_NOTES (place
) = note
;
12433 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12434 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12435 && REG_P (XEXP (note
, 0)))
12436 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12440 if ((REG_NOTE_KIND (note
) == REG_DEAD
12441 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12442 && REG_P (XEXP (note
, 0)))
12443 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12445 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12446 REG_NOTE_KIND (note
),
12448 REG_NOTES (place2
));
12453 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12454 I3, I2, and I1 to new locations. This is also called to add a link
12455 pointing at I3 when I3's destination is changed. */
12458 distribute_links (rtx links
)
12460 rtx link
, next_link
;
12462 for (link
= links
; link
; link
= next_link
)
12468 next_link
= XEXP (link
, 1);
12470 /* If the insn that this link points to is a NOTE or isn't a single
12471 set, ignore it. In the latter case, it isn't clear what we
12472 can do other than ignore the link, since we can't tell which
12473 register it was for. Such links wouldn't be used by combine
12476 It is not possible for the destination of the target of the link to
12477 have been changed by combine. The only potential of this is if we
12478 replace I3, I2, and I1 by I3 and I2. But in that case the
12479 destination of I2 also remains unchanged. */
12481 if (NOTE_P (XEXP (link
, 0))
12482 || (set
= single_set (XEXP (link
, 0))) == 0)
12485 reg
= SET_DEST (set
);
12486 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12487 || GET_CODE (reg
) == STRICT_LOW_PART
)
12488 reg
= XEXP (reg
, 0);
12490 /* A LOG_LINK is defined as being placed on the first insn that uses
12491 a register and points to the insn that sets the register. Start
12492 searching at the next insn after the target of the link and stop
12493 when we reach a set of the register or the end of the basic block.
12495 Note that this correctly handles the link that used to point from
12496 I3 to I2. Also note that not much searching is typically done here
12497 since most links don't point very far away. */
12499 for (insn
= NEXT_INSN (XEXP (link
, 0));
12500 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12501 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12502 insn
= NEXT_INSN (insn
))
12503 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12505 if (reg_referenced_p (reg
, PATTERN (insn
)))
12509 else if (CALL_P (insn
)
12510 && find_reg_fusage (insn
, USE
, reg
))
12515 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12518 /* If we found a place to put the link, place it there unless there
12519 is already a link to the same insn as LINK at that point. */
12525 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12526 if (XEXP (link2
, 0) == XEXP (link
, 0))
12531 XEXP (link
, 1) = LOG_LINKS (place
);
12532 LOG_LINKS (place
) = link
;
12534 /* Set added_links_insn to the earliest insn we added a
12536 if (added_links_insn
== 0
12537 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12538 added_links_insn
= place
;
12544 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12545 Check whether the expression pointer to by LOC is a register or
12546 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12547 Otherwise return zero. */
12550 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
12555 && (REG_P (x
) || MEM_P (x
))
12556 && ! reg_mentioned_p (x
, (rtx
) expr
))
12561 /* Check for any register or memory mentioned in EQUIV that is not
12562 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12563 of EXPR where some registers may have been replaced by constants. */
12566 unmentioned_reg_p (rtx equiv
, rtx expr
)
12568 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
12571 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12574 insn_cuid (rtx insn
)
12576 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12577 && NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
)
12578 insn
= NEXT_INSN (insn
);
12580 gcc_assert (INSN_UID (insn
) <= max_uid_cuid
);
12582 return INSN_CUID (insn
);
12586 dump_combine_stats (FILE *file
)
12590 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12591 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12595 dump_combine_total_stats (FILE *file
)
12599 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12600 total_attempts
, total_merges
, total_extras
, total_successes
);
12605 gate_handle_combine (void)
12607 return (optimize
> 0);
12610 /* Try combining insns through substitution. */
12612 rest_of_handle_combine (void)
12614 int rebuild_jump_labels_after_combine
12615 = combine_instructions (get_insns (), max_reg_num ());
12617 /* Combining insns may have turned an indirect jump into a
12618 direct jump. Rebuild the JUMP_LABEL fields of jumping
12620 if (rebuild_jump_labels_after_combine
)
12622 timevar_push (TV_JUMP
);
12623 rebuild_jump_labels (get_insns ());
12624 timevar_pop (TV_JUMP
);
12626 delete_dead_jumptables ();
12627 cleanup_cfg (CLEANUP_EXPENSIVE
| CLEANUP_UPDATE_LIFE
);
12631 struct tree_opt_pass pass_combine
=
12633 "combine", /* name */
12634 gate_handle_combine
, /* gate */
12635 rest_of_handle_combine
, /* execute */
12638 0, /* static_pass_number */
12639 TV_COMBINE
, /* tv_id */
12640 0, /* properties_required */
12641 0, /* properties_provided */
12642 0, /* properties_destroyed */
12643 0, /* todo_flags_start */
12645 TODO_ggc_collect
, /* todo_flags_finish */