1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
93 #include "rtlhooks-def.h"
94 /* Include output.h for dump_file. */
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts
;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges
;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras
;
110 /* Number of instructions combined in this function. */
112 static int combine_successes
;
114 /* Totals over entire compilation. */
116 static int total_attempts
, total_merges
, total_extras
, total_successes
;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid
;
127 static int max_uid_cuid
;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno
;
145 /* Record last point of death of (hard or pseudo) register n. */
148 /* Record last point of modification of (hard or pseudo) register n. */
151 /* The next group of fields allows the recording of the last value assigned
152 to (hard or pseudo) register n. We use this information to see if an
153 operation being processed is redundant given a prior operation performed
154 on the register. For example, an `and' with a constant is redundant if
155 all the zero bits are already known to be turned off.
157 We use an approach similar to that used by cse, but change it in the
160 (1) We do not want to reinitialize at each label.
161 (2) It is useful, but not critical, to know the actual value assigned
162 to a register. Often just its form is helpful.
164 Therefore, we maintain the following fields:
166 last_set_value the last value assigned
167 last_set_label records the value of label_tick when the
168 register was assigned
169 last_set_table_tick records the value of label_tick when a
170 value using the register is assigned
171 last_set_invalid set to nonzero when it is not valid
172 to use the value of this register in some
175 To understand the usage of these tables, it is important to understand
176 the distinction between the value in last_set_value being valid and
177 the register being validly contained in some other expression in the
180 (The next two parameters are out of date).
182 reg_stat[i].last_set_value is valid if it is nonzero, and either
183 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
185 Register I may validly appear in any expression returned for the value
186 of another register if reg_n_sets[i] is 1. It may also appear in the
187 value for register J if reg_stat[j].last_set_invalid is zero, or
188 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
190 If an expression is found in the table containing a register which may
191 not validly appear in an expression, the register is replaced by
192 something that won't match, (clobber (const_int 0)). */
194 /* Record last value assigned to (hard or pseudo) register n. */
198 /* Record the value of label_tick when an expression involving register n
199 is placed in last_set_value. */
201 int last_set_table_tick
;
203 /* Record the value of label_tick when the value for register n is placed in
208 /* These fields are maintained in parallel with last_set_value and are
209 used to store the mode in which the register was last set, the bits
210 that were known to be zero when it was last set, and the number of
211 sign bits copies it was known to have when it was last set. */
213 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
214 char last_set_sign_bit_copies
;
215 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
217 /* Set nonzero if references to register n in expressions should not be
218 used. last_set_invalid is set nonzero when this register is being
219 assigned to and last_set_table_tick == label_tick. */
221 char last_set_invalid
;
223 /* Some registers that are set more than once and used in more than one
224 basic block are nevertheless always set in similar ways. For example,
225 a QImode register may be loaded from memory in two places on a machine
226 where byte loads zero extend.
228 We record in the following fields if a register has some leading bits
229 that are always equal to the sign bit, and what we know about the
230 nonzero bits of a register, specifically which bits are known to be
233 If an entry is zero, it means that we don't know anything special. */
235 unsigned char sign_bit_copies
;
237 unsigned HOST_WIDE_INT nonzero_bits
;
240 static struct reg_stat
*reg_stat
;
242 /* Record the cuid of the last insn that invalidated memory
243 (anything that writes memory, and subroutine calls, but not pushes). */
245 static int mem_last_set
;
247 /* Record the cuid of the last CALL_INSN
248 so we can tell whether a potential combination crosses any calls. */
250 static int last_call_cuid
;
252 /* When `subst' is called, this is the insn that is being modified
253 (by combining in a previous insn). The PATTERN of this insn
254 is still the old pattern partially modified and it should not be
255 looked at, but this may be used to examine the successors of the insn
256 to judge whether a simplification is valid. */
258 static rtx subst_insn
;
260 /* This is the lowest CUID that `subst' is currently dealing with.
261 get_last_value will not return a value if the register was set at or
262 after this CUID. If not for this mechanism, we could get confused if
263 I2 or I1 in try_combine were an insn that used the old value of a register
264 to obtain a new value. In that case, we might erroneously get the
265 new value of the register when we wanted the old one. */
267 static int subst_low_cuid
;
269 /* This contains any hard registers that are used in newpat; reg_dead_at_p
270 must consider all these registers to be always live. */
272 static HARD_REG_SET newpat_used_regs
;
274 /* This is an insn to which a LOG_LINKS entry has been added. If this
275 insn is the earlier than I2 or I3, combine should rescan starting at
278 static rtx added_links_insn
;
280 /* Basic block in which we are performing combines. */
281 static basic_block this_basic_block
;
283 /* A bitmap indicating which blocks had registers go dead at entry.
284 After combine, we'll need to re-do global life analysis with
285 those blocks as starting points. */
286 static sbitmap refresh_blocks
;
288 /* The following array records the insn_rtx_cost for every insn
289 in the instruction stream. */
291 static int *uid_insn_cost
;
293 /* Length of the currently allocated uid_insn_cost array. */
295 static int last_insn_cost
;
297 /* Incremented for each label. */
299 static int label_tick
;
301 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
302 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
304 static enum machine_mode nonzero_bits_mode
;
306 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
307 be safely used. It is zero while computing them and after combine has
308 completed. This former test prevents propagating values based on
309 previously set values, which can be incorrect if a variable is modified
312 static int nonzero_sign_valid
;
315 /* Record one modification to rtl structure
316 to be undone by storing old_contents into *where.
317 is_int is 1 if the contents are an int. */
323 union {rtx r
; int i
;} old_contents
;
324 union {rtx
*r
; int *i
;} where
;
327 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
328 num_undo says how many are currently recorded.
330 other_insn is nonzero if we have modified some other insn in the process
331 of working on subst_insn. It must be verified too. */
340 static struct undobuf undobuf
;
342 /* Number of times the pseudo being substituted for
343 was found and replaced. */
345 static int n_occurrences
;
347 static rtx
reg_nonzero_bits_for_combine (rtx
, enum machine_mode
, rtx
,
349 unsigned HOST_WIDE_INT
,
350 unsigned HOST_WIDE_INT
*);
351 static rtx
reg_num_sign_bit_copies_for_combine (rtx
, enum machine_mode
, rtx
,
353 unsigned int, unsigned int *);
354 static void do_SUBST (rtx
*, rtx
);
355 static void do_SUBST_INT (int *, int);
356 static void init_reg_last (void);
357 static void setup_incoming_promotions (void);
358 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
359 static int cant_combine_insn_p (rtx
);
360 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
361 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
362 static int contains_muldiv (rtx
);
363 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
364 static void undo_all (void);
365 static void undo_commit (void);
366 static rtx
*find_split_point (rtx
*, rtx
);
367 static rtx
subst (rtx
, rtx
, rtx
, int, int);
368 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
369 static rtx
simplify_if_then_else (rtx
);
370 static rtx
simplify_set (rtx
);
371 static rtx
simplify_logical (rtx
);
372 static rtx
expand_compound_operation (rtx
);
373 static rtx
expand_field_assignment (rtx
);
374 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
375 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
376 static rtx
extract_left_shift (rtx
, int);
377 static rtx
make_compound_operation (rtx
, enum rtx_code
);
378 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
379 unsigned HOST_WIDE_INT
*);
380 static rtx
force_to_mode (rtx
, enum machine_mode
,
381 unsigned HOST_WIDE_INT
, rtx
, int);
382 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
383 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
384 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
385 static rtx
make_field_assignment (rtx
);
386 static rtx
apply_distributive_law (rtx
);
387 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
388 unsigned HOST_WIDE_INT
);
389 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
390 HOST_WIDE_INT
, enum machine_mode
, int *);
391 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
393 static int recog_for_combine (rtx
*, rtx
, rtx
*);
394 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
395 static rtx
gen_binary (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
396 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
397 static void update_table_tick (rtx
);
398 static void record_value_for_reg (rtx
, rtx
, rtx
);
399 static void check_promoted_subreg (rtx
, rtx
);
400 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
401 static void record_dead_and_set_regs (rtx
);
402 static int get_last_value_validate (rtx
*, rtx
, int, int);
403 static rtx
get_last_value (rtx
);
404 static int use_crosses_set_p (rtx
, int);
405 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
406 static int reg_dead_at_p (rtx
, rtx
);
407 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
408 static int reg_bitfield_target_p (rtx
, rtx
);
409 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
410 static void distribute_links (rtx
);
411 static void mark_used_regs_combine (rtx
);
412 static int insn_cuid (rtx
);
413 static void record_promoted_value (rtx
, rtx
);
414 static rtx
reversed_comparison (rtx
, enum machine_mode
, rtx
, rtx
);
415 static enum rtx_code
combine_reversed_comparison_code (rtx
);
416 static int unmentioned_reg_p_1 (rtx
*, void *);
417 static bool unmentioned_reg_p (rtx
, rtx
);
420 /* It is not safe to use ordinary gen_lowpart in combine.
421 See comments in gen_lowpart_for_combine. */
422 #undef RTL_HOOKS_GEN_LOWPART
423 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
425 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
426 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
428 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
429 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
431 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
434 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
435 insn. The substitution can be undone by undo_all. If INTO is already
436 set to NEWVAL, do not record this change. Because computing NEWVAL might
437 also call SUBST, we have to compute it before we put anything into
441 do_SUBST (rtx
*into
, rtx newval
)
446 if (oldval
== newval
)
449 /* We'd like to catch as many invalid transformations here as
450 possible. Unfortunately, there are way too many mode changes
451 that are perfectly valid, so we'd waste too much effort for
452 little gain doing the checks here. Focus on catching invalid
453 transformations involving integer constants. */
454 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
455 && GET_CODE (newval
) == CONST_INT
)
457 /* Sanity check that we're replacing oldval with a CONST_INT
458 that is a valid sign-extension for the original mode. */
459 gcc_assert (INTVAL (newval
)
460 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
462 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
463 CONST_INT is not valid, because after the replacement, the
464 original mode would be gone. Unfortunately, we can't tell
465 when do_SUBST is called to replace the operand thereof, so we
466 perform this test on oldval instead, checking whether an
467 invalid replacement took place before we got here. */
468 gcc_assert (!(GET_CODE (oldval
) == SUBREG
469 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
));
470 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
471 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
));
475 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
477 buf
= xmalloc (sizeof (struct undo
));
481 buf
->old_contents
.r
= oldval
;
484 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
487 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
489 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
490 for the value of a HOST_WIDE_INT value (including CONST_INT) is
494 do_SUBST_INT (int *into
, int newval
)
499 if (oldval
== newval
)
503 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
505 buf
= xmalloc (sizeof (struct undo
));
509 buf
->old_contents
.i
= oldval
;
512 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
515 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
517 /* Subroutine of try_combine. Determine whether the combine replacement
518 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
519 that the original instruction sequence I1, I2 and I3. Note that I1
520 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
521 costs of all instructions can be estimated, and the replacements are
522 more expensive than the original sequence. */
525 combine_validate_cost (rtx i1
, rtx i2
, rtx i3
, rtx newpat
, rtx newi2pat
)
527 int i1_cost
, i2_cost
, i3_cost
;
528 int new_i2_cost
, new_i3_cost
;
529 int old_cost
, new_cost
;
531 /* Lookup the original insn_rtx_costs. */
532 i2_cost
= INSN_UID (i2
) <= last_insn_cost
533 ? uid_insn_cost
[INSN_UID (i2
)] : 0;
534 i3_cost
= INSN_UID (i3
) <= last_insn_cost
535 ? uid_insn_cost
[INSN_UID (i3
)] : 0;
539 i1_cost
= INSN_UID (i1
) <= last_insn_cost
540 ? uid_insn_cost
[INSN_UID (i1
)] : 0;
541 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0)
542 ? i1_cost
+ i2_cost
+ i3_cost
: 0;
546 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
550 /* Calculate the replacement insn_rtx_costs. */
551 new_i3_cost
= insn_rtx_cost (newpat
);
554 new_i2_cost
= insn_rtx_cost (newi2pat
);
555 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
556 ? new_i2_cost
+ new_i3_cost
: 0;
560 new_cost
= new_i3_cost
;
564 if (undobuf
.other_insn
)
566 int old_other_cost
, new_other_cost
;
568 old_other_cost
= (INSN_UID (undobuf
.other_insn
) <= last_insn_cost
569 ? uid_insn_cost
[INSN_UID (undobuf
.other_insn
)] : 0);
570 new_other_cost
= insn_rtx_cost (PATTERN (undobuf
.other_insn
));
571 if (old_other_cost
> 0 && new_other_cost
> 0)
573 old_cost
+= old_other_cost
;
574 new_cost
+= new_other_cost
;
580 /* Disallow this recombination if both new_cost and old_cost are
581 greater than zero, and new_cost is greater than old cost. */
583 && new_cost
> old_cost
)
590 "rejecting combination of insns %d, %d and %d\n",
591 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
592 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
593 i1_cost
, i2_cost
, i3_cost
, old_cost
);
598 "rejecting combination of insns %d and %d\n",
599 INSN_UID (i2
), INSN_UID (i3
));
600 fprintf (dump_file
, "original costs %d + %d = %d\n",
601 i2_cost
, i3_cost
, old_cost
);
606 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
607 new_i2_cost
, new_i3_cost
, new_cost
);
610 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
616 /* Update the uid_insn_cost array with the replacement costs. */
617 uid_insn_cost
[INSN_UID (i2
)] = new_i2_cost
;
618 uid_insn_cost
[INSN_UID (i3
)] = new_i3_cost
;
620 uid_insn_cost
[INSN_UID (i1
)] = 0;
625 /* Main entry point for combiner. F is the first insn of the function.
626 NREGS is the first unused pseudo-reg number.
628 Return nonzero if the combiner has turned an indirect jump
629 instruction into a direct jump. */
631 combine_instructions (rtx f
, unsigned int nregs
)
638 rtx links
, nextlinks
;
640 int new_direct_jump_p
= 0;
642 combine_attempts
= 0;
645 combine_successes
= 0;
647 combine_max_regno
= nregs
;
649 rtl_hooks
= combine_rtl_hooks
;
651 reg_stat
= xcalloc (nregs
, sizeof (struct reg_stat
));
653 init_recog_no_volatile ();
655 /* Compute maximum uid value so uid_cuid can be allocated. */
657 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
658 if (INSN_UID (insn
) > i
)
661 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
664 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
666 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
667 problems when, for example, we have j <<= 1 in a loop. */
669 nonzero_sign_valid
= 0;
671 /* Compute the mapping from uids to cuids.
672 Cuids are numbers assigned to insns, like uids,
673 except that cuids increase monotonically through the code.
675 Scan all SETs and see if we can deduce anything about what
676 bits are known to be zero for some registers and how many copies
677 of the sign bit are known to exist for those registers.
679 Also set any known values so that we can use it while searching
680 for what bits are known to be set. */
684 setup_incoming_promotions ();
686 refresh_blocks
= sbitmap_alloc (last_basic_block
);
687 sbitmap_zero (refresh_blocks
);
689 /* Allocate array of current insn_rtx_costs. */
690 uid_insn_cost
= xcalloc (max_uid_cuid
+ 1, sizeof (int));
691 last_insn_cost
= max_uid_cuid
;
693 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
695 uid_cuid
[INSN_UID (insn
)] = ++i
;
701 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
703 record_dead_and_set_regs (insn
);
706 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
707 if (REG_NOTE_KIND (links
) == REG_INC
)
708 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
712 /* Record the current insn_rtx_cost of this instruction. */
713 if (NONJUMP_INSN_P (insn
))
714 uid_insn_cost
[INSN_UID (insn
)] = insn_rtx_cost (PATTERN (insn
));
716 fprintf(dump_file
, "insn_cost %d: %d\n",
717 INSN_UID (insn
), uid_insn_cost
[INSN_UID (insn
)]);
724 nonzero_sign_valid
= 1;
726 /* Now scan all the insns in forward order. */
732 setup_incoming_promotions ();
734 FOR_EACH_BB (this_basic_block
)
736 for (insn
= BB_HEAD (this_basic_block
);
737 insn
!= NEXT_INSN (BB_END (this_basic_block
));
738 insn
= next
? next
: NEXT_INSN (insn
))
745 else if (INSN_P (insn
))
747 /* See if we know about function return values before this
748 insn based upon SUBREG flags. */
749 check_promoted_subreg (insn
, PATTERN (insn
));
751 /* Try this insn with each insn it links back to. */
753 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
754 if ((next
= try_combine (insn
, XEXP (links
, 0),
755 NULL_RTX
, &new_direct_jump_p
)) != 0)
758 /* Try each sequence of three linked insns ending with this one. */
760 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
762 rtx link
= XEXP (links
, 0);
764 /* If the linked insn has been replaced by a note, then there
765 is no point in pursuing this chain any further. */
769 for (nextlinks
= LOG_LINKS (link
);
771 nextlinks
= XEXP (nextlinks
, 1))
772 if ((next
= try_combine (insn
, link
,
774 &new_direct_jump_p
)) != 0)
779 /* Try to combine a jump insn that uses CC0
780 with a preceding insn that sets CC0, and maybe with its
781 logical predecessor as well.
782 This is how we make decrement-and-branch insns.
783 We need this special code because data flow connections
784 via CC0 do not get entered in LOG_LINKS. */
787 && (prev
= prev_nonnote_insn (insn
)) != 0
788 && NONJUMP_INSN_P (prev
)
789 && sets_cc0_p (PATTERN (prev
)))
791 if ((next
= try_combine (insn
, prev
,
792 NULL_RTX
, &new_direct_jump_p
)) != 0)
795 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
796 nextlinks
= XEXP (nextlinks
, 1))
797 if ((next
= try_combine (insn
, prev
,
799 &new_direct_jump_p
)) != 0)
803 /* Do the same for an insn that explicitly references CC0. */
804 if (NONJUMP_INSN_P (insn
)
805 && (prev
= prev_nonnote_insn (insn
)) != 0
806 && NONJUMP_INSN_P (prev
)
807 && sets_cc0_p (PATTERN (prev
))
808 && GET_CODE (PATTERN (insn
)) == SET
809 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
811 if ((next
= try_combine (insn
, prev
,
812 NULL_RTX
, &new_direct_jump_p
)) != 0)
815 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
816 nextlinks
= XEXP (nextlinks
, 1))
817 if ((next
= try_combine (insn
, prev
,
819 &new_direct_jump_p
)) != 0)
823 /* Finally, see if any of the insns that this insn links to
824 explicitly references CC0. If so, try this insn, that insn,
825 and its predecessor if it sets CC0. */
826 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
827 if (NONJUMP_INSN_P (XEXP (links
, 0))
828 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
829 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
830 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
831 && NONJUMP_INSN_P (prev
)
832 && sets_cc0_p (PATTERN (prev
))
833 && (next
= try_combine (insn
, XEXP (links
, 0),
834 prev
, &new_direct_jump_p
)) != 0)
838 /* Try combining an insn with two different insns whose results it
840 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
841 for (nextlinks
= XEXP (links
, 1); nextlinks
;
842 nextlinks
= XEXP (nextlinks
, 1))
843 if ((next
= try_combine (insn
, XEXP (links
, 0),
845 &new_direct_jump_p
)) != 0)
848 /* Try this insn with each REG_EQUAL note it links back to. */
849 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
852 rtx temp
= XEXP (links
, 0);
853 if ((set
= single_set (temp
)) != 0
854 && (note
= find_reg_equal_equiv_note (temp
)) != 0
855 && GET_CODE (XEXP (note
, 0)) != EXPR_LIST
856 /* Avoid using a register that may already been marked
857 dead by an earlier instruction. */
858 && ! unmentioned_reg_p (XEXP (note
, 0), SET_SRC (set
)))
860 /* Temporarily replace the set's source with the
861 contents of the REG_EQUAL note. The insn will
862 be deleted or recognized by try_combine. */
863 rtx orig
= SET_SRC (set
);
864 SET_SRC (set
) = XEXP (note
, 0);
865 next
= try_combine (insn
, temp
, NULL_RTX
,
869 SET_SRC (set
) = orig
;
874 record_dead_and_set_regs (insn
);
883 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
884 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
885 new_direct_jump_p
|= purge_all_dead_edges (0);
886 delete_noop_moves ();
888 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
889 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
890 | PROP_KILL_DEAD_CODE
);
893 sbitmap_free (refresh_blocks
);
894 free (uid_insn_cost
);
899 struct undo
*undo
, *next
;
900 for (undo
= undobuf
.frees
; undo
; undo
= next
)
908 total_attempts
+= combine_attempts
;
909 total_merges
+= combine_merges
;
910 total_extras
+= combine_extras
;
911 total_successes
+= combine_successes
;
913 nonzero_sign_valid
= 0;
914 rtl_hooks
= general_rtl_hooks
;
916 /* Make recognizer allow volatile MEMs again. */
919 return new_direct_jump_p
;
922 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
928 for (i
= 0; i
< combine_max_regno
; i
++)
929 memset (reg_stat
+ i
, 0, offsetof (struct reg_stat
, sign_bit_copies
));
932 /* Set up any promoted values for incoming argument registers. */
935 setup_incoming_promotions (void)
939 enum machine_mode mode
;
941 rtx first
= get_insns ();
943 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
945 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
946 /* Check whether this register can hold an incoming pointer
947 argument. FUNCTION_ARG_REGNO_P tests outgoing register
948 numbers, so translate if necessary due to register windows. */
949 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
950 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
953 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
956 gen_rtx_CLOBBER (mode
, const0_rtx
)));
961 /* Called via note_stores. If X is a pseudo that is narrower than
962 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
964 If we are setting only a portion of X and we can't figure out what
965 portion, assume all bits will be used since we don't know what will
968 Similarly, set how many bits of X are known to be copies of the sign bit
969 at all locations in the function. This is the smallest number implied
973 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
974 void *data ATTRIBUTE_UNUSED
)
979 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
980 /* If this register is undefined at the start of the file, we can't
981 say what its contents were. */
982 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
983 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
985 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
987 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
988 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
992 /* If this is a complex assignment, see if we can convert it into a
993 simple assignment. */
994 set
= expand_field_assignment (set
);
996 /* If this is a simple assignment, or we have a paradoxical SUBREG,
997 set what we know about X. */
999 if (SET_DEST (set
) == x
1000 || (GET_CODE (SET_DEST (set
)) == SUBREG
1001 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1002 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
1003 && SUBREG_REG (SET_DEST (set
)) == x
))
1005 rtx src
= SET_SRC (set
);
1007 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1008 /* If X is narrower than a word and SRC is a non-negative
1009 constant that would appear negative in the mode of X,
1010 sign-extend it for use in reg_stat[].nonzero_bits because some
1011 machines (maybe most) will actually do the sign-extension
1012 and this is the conservative approach.
1014 ??? For 2.5, try to tighten up the MD files in this regard
1015 instead of this kludge. */
1017 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
1018 && GET_CODE (src
) == CONST_INT
1020 && 0 != (INTVAL (src
)
1021 & ((HOST_WIDE_INT
) 1
1022 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
1023 src
= GEN_INT (INTVAL (src
)
1024 | ((HOST_WIDE_INT
) (-1)
1025 << GET_MODE_BITSIZE (GET_MODE (x
))));
1028 /* Don't call nonzero_bits if it cannot change anything. */
1029 if (reg_stat
[REGNO (x
)].nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1030 reg_stat
[REGNO (x
)].nonzero_bits
1031 |= nonzero_bits (src
, nonzero_bits_mode
);
1032 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1033 if (reg_stat
[REGNO (x
)].sign_bit_copies
== 0
1034 || reg_stat
[REGNO (x
)].sign_bit_copies
> num
)
1035 reg_stat
[REGNO (x
)].sign_bit_copies
= num
;
1039 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1040 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
1045 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1046 insns that were previously combined into I3 or that will be combined
1047 into the merger of INSN and I3.
1049 Return 0 if the combination is not allowed for any reason.
1051 If the combination is allowed, *PDEST will be set to the single
1052 destination of INSN and *PSRC to the single source, and this function
1056 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
1057 rtx
*pdest
, rtx
*psrc
)
1060 rtx set
= 0, src
, dest
;
1065 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
1066 && next_active_insn (succ
) == i3
)
1067 : next_active_insn (insn
) == i3
);
1069 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1070 or a PARALLEL consisting of such a SET and CLOBBERs.
1072 If INSN has CLOBBER parallel parts, ignore them for our processing.
1073 By definition, these happen during the execution of the insn. When it
1074 is merged with another insn, all bets are off. If they are, in fact,
1075 needed and aren't also supplied in I3, they may be added by
1076 recog_for_combine. Otherwise, it won't match.
1078 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1081 Get the source and destination of INSN. If more than one, can't
1084 if (GET_CODE (PATTERN (insn
)) == SET
)
1085 set
= PATTERN (insn
);
1086 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1087 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1089 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1091 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1094 switch (GET_CODE (elt
))
1096 /* This is important to combine floating point insns
1097 for the SH4 port. */
1099 /* Combining an isolated USE doesn't make sense.
1100 We depend here on combinable_i3pat to reject them. */
1101 /* The code below this loop only verifies that the inputs of
1102 the SET in INSN do not change. We call reg_set_between_p
1103 to verify that the REG in the USE does not change between
1105 If the USE in INSN was for a pseudo register, the matching
1106 insn pattern will likely match any register; combining this
1107 with any other USE would only be safe if we knew that the
1108 used registers have identical values, or if there was
1109 something to tell them apart, e.g. different modes. For
1110 now, we forgo such complicated tests and simply disallow
1111 combining of USES of pseudo registers with any other USE. */
1112 if (REG_P (XEXP (elt
, 0))
1113 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1115 rtx i3pat
= PATTERN (i3
);
1116 int i
= XVECLEN (i3pat
, 0) - 1;
1117 unsigned int regno
= REGNO (XEXP (elt
, 0));
1121 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1123 if (GET_CODE (i3elt
) == USE
1124 && REG_P (XEXP (i3elt
, 0))
1125 && (REGNO (XEXP (i3elt
, 0)) == regno
1126 ? reg_set_between_p (XEXP (elt
, 0),
1127 PREV_INSN (insn
), i3
)
1128 : regno
>= FIRST_PSEUDO_REGISTER
))
1135 /* We can ignore CLOBBERs. */
1140 /* Ignore SETs whose result isn't used but not those that
1141 have side-effects. */
1142 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1143 && (!(note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
1144 || INTVAL (XEXP (note
, 0)) <= 0)
1145 && ! side_effects_p (elt
))
1148 /* If we have already found a SET, this is a second one and
1149 so we cannot combine with this insn. */
1157 /* Anything else means we can't combine. */
1163 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1164 so don't do anything with it. */
1165 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1174 set
= expand_field_assignment (set
);
1175 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1177 /* Don't eliminate a store in the stack pointer. */
1178 if (dest
== stack_pointer_rtx
1179 /* Don't combine with an insn that sets a register to itself if it has
1180 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1181 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1182 /* Can't merge an ASM_OPERANDS. */
1183 || GET_CODE (src
) == ASM_OPERANDS
1184 /* Can't merge a function call. */
1185 || GET_CODE (src
) == CALL
1186 /* Don't eliminate a function call argument. */
1188 && (find_reg_fusage (i3
, USE
, dest
)
1190 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1191 && global_regs
[REGNO (dest
)])))
1192 /* Don't substitute into an incremented register. */
1193 || FIND_REG_INC_NOTE (i3
, dest
)
1194 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1195 /* Don't substitute into a non-local goto, this confuses CFG. */
1196 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1198 /* Don't combine the end of a libcall into anything. */
1199 /* ??? This gives worse code, and appears to be unnecessary, since no
1200 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1201 use REG_RETVAL notes for noconflict blocks, but other code here
1202 makes sure that those insns don't disappear. */
1203 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1205 /* Make sure that DEST is not used after SUCC but before I3. */
1206 || (succ
&& ! all_adjacent
1207 && reg_used_between_p (dest
, succ
, i3
))
1208 /* Make sure that the value that is to be substituted for the register
1209 does not use any registers whose values alter in between. However,
1210 If the insns are adjacent, a use can't cross a set even though we
1211 think it might (this can happen for a sequence of insns each setting
1212 the same destination; last_set of that register might point to
1213 a NOTE). If INSN has a REG_EQUIV note, the register is always
1214 equivalent to the memory so the substitution is valid even if there
1215 are intervening stores. Also, don't move a volatile asm or
1216 UNSPEC_VOLATILE across any other insns. */
1219 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1220 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1221 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1222 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1223 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1224 better register allocation by not doing the combine. */
1225 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1226 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1227 /* Don't combine across a CALL_INSN, because that would possibly
1228 change whether the life span of some REGs crosses calls or not,
1229 and it is a pain to update that information.
1230 Exception: if source is a constant, moving it later can't hurt.
1231 Accept that special case, because it helps -fforce-addr a lot. */
1232 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1235 /* DEST must either be a REG or CC0. */
1238 /* If register alignment is being enforced for multi-word items in all
1239 cases except for parameters, it is possible to have a register copy
1240 insn referencing a hard register that is not allowed to contain the
1241 mode being copied and which would not be valid as an operand of most
1242 insns. Eliminate this problem by not combining with such an insn.
1244 Also, on some machines we don't want to extend the life of a hard
1248 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1249 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1250 /* Don't extend the life of a hard register unless it is
1251 user variable (if we have few registers) or it can't
1252 fit into the desired register (meaning something special
1254 Also avoid substituting a return register into I3, because
1255 reload can't handle a conflict with constraints of other
1257 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1258 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1261 else if (GET_CODE (dest
) != CC0
)
1265 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1266 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1267 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1269 /* Don't substitute for a register intended as a clobberable
1271 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1272 if (rtx_equal_p (reg
, dest
))
1275 /* If the clobber represents an earlyclobber operand, we must not
1276 substitute an expression containing the clobbered register.
1277 As we do not analyse the constraint strings here, we have to
1278 make the conservative assumption. However, if the register is
1279 a fixed hard reg, the clobber cannot represent any operand;
1280 we leave it up to the machine description to either accept or
1281 reject use-and-clobber patterns. */
1283 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1284 || !fixed_regs
[REGNO (reg
)])
1285 if (reg_overlap_mentioned_p (reg
, src
))
1289 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1290 or not), reject, unless nothing volatile comes between it and I3 */
1292 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1294 /* Make sure succ doesn't contain a volatile reference. */
1295 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1298 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1299 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1303 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1304 to be an explicit register variable, and was chosen for a reason. */
1306 if (GET_CODE (src
) == ASM_OPERANDS
1307 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1310 /* If there are any volatile insns between INSN and I3, reject, because
1311 they might affect machine state. */
1313 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1314 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1317 /* If INSN or I2 contains an autoincrement or autodecrement,
1318 make sure that register is not used between there and I3,
1319 and not already used in I3 either.
1320 Also insist that I3 not be a jump; if it were one
1321 and the incremented register were spilled, we would lose. */
1324 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1325 if (REG_NOTE_KIND (link
) == REG_INC
1327 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1328 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1333 /* Don't combine an insn that follows a CC0-setting insn.
1334 An insn that uses CC0 must not be separated from the one that sets it.
1335 We do, however, allow I2 to follow a CC0-setting insn if that insn
1336 is passed as I1; in that case it will be deleted also.
1337 We also allow combining in this case if all the insns are adjacent
1338 because that would leave the two CC0 insns adjacent as well.
1339 It would be more logical to test whether CC0 occurs inside I1 or I2,
1340 but that would be much slower, and this ought to be equivalent. */
1342 p
= prev_nonnote_insn (insn
);
1343 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1348 /* If we get here, we have passed all the tests and the combination is
1357 /* LOC is the location within I3 that contains its pattern or the component
1358 of a PARALLEL of the pattern. We validate that it is valid for combining.
1360 One problem is if I3 modifies its output, as opposed to replacing it
1361 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1362 so would produce an insn that is not equivalent to the original insns.
1366 (set (reg:DI 101) (reg:DI 100))
1367 (set (subreg:SI (reg:DI 101) 0) <foo>)
1369 This is NOT equivalent to:
1371 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1372 (set (reg:DI 101) (reg:DI 100))])
1374 Not only does this modify 100 (in which case it might still be valid
1375 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1377 We can also run into a problem if I2 sets a register that I1
1378 uses and I1 gets directly substituted into I3 (not via I2). In that
1379 case, we would be getting the wrong value of I2DEST into I3, so we
1380 must reject the combination. This case occurs when I2 and I1 both
1381 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1382 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1383 of a SET must prevent combination from occurring.
1385 Before doing the above check, we first try to expand a field assignment
1386 into a set of logical operations.
1388 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1389 we place a register that is both set and used within I3. If more than one
1390 such register is detected, we fail.
1392 Return 1 if the combination is valid, zero otherwise. */
1395 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1396 int i1_not_in_src
, rtx
*pi3dest_killed
)
1400 if (GET_CODE (x
) == SET
)
1403 rtx dest
= SET_DEST (set
);
1404 rtx src
= SET_SRC (set
);
1405 rtx inner_dest
= dest
;
1407 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1408 || GET_CODE (inner_dest
) == SUBREG
1409 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1410 inner_dest
= XEXP (inner_dest
, 0);
1412 /* Check for the case where I3 modifies its output, as discussed
1413 above. We don't want to prevent pseudos from being combined
1414 into the address of a MEM, so only prevent the combination if
1415 i1 or i2 set the same MEM. */
1416 if ((inner_dest
!= dest
&&
1417 (!MEM_P (inner_dest
)
1418 || rtx_equal_p (i2dest
, inner_dest
)
1419 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1420 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1421 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1423 /* This is the same test done in can_combine_p except we can't test
1424 all_adjacent; we don't have to, since this instruction will stay
1425 in place, thus we are not considering increasing the lifetime of
1428 Also, if this insn sets a function argument, combining it with
1429 something that might need a spill could clobber a previous
1430 function argument; the all_adjacent test in can_combine_p also
1431 checks this; here, we do a more specific test for this case. */
1433 || (REG_P (inner_dest
)
1434 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1435 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1436 GET_MODE (inner_dest
))))
1437 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1440 /* If DEST is used in I3, it is being killed in this insn,
1441 so record that for later.
1442 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1443 STACK_POINTER_REGNUM, since these are always considered to be
1444 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1445 if (pi3dest_killed
&& REG_P (dest
)
1446 && reg_referenced_p (dest
, PATTERN (i3
))
1447 && REGNO (dest
) != FRAME_POINTER_REGNUM
1448 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1449 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1451 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1452 && (REGNO (dest
) != ARG_POINTER_REGNUM
1453 || ! fixed_regs
[REGNO (dest
)])
1455 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1457 if (*pi3dest_killed
)
1460 *pi3dest_killed
= dest
;
1464 else if (GET_CODE (x
) == PARALLEL
)
1468 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1469 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1470 i1_not_in_src
, pi3dest_killed
))
1477 /* Return 1 if X is an arithmetic expression that contains a multiplication
1478 and division. We don't count multiplications by powers of two here. */
1481 contains_muldiv (rtx x
)
1483 switch (GET_CODE (x
))
1485 case MOD
: case DIV
: case UMOD
: case UDIV
:
1489 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1490 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1493 return contains_muldiv (XEXP (x
, 0))
1494 || contains_muldiv (XEXP (x
, 1));
1497 return contains_muldiv (XEXP (x
, 0));
1503 /* Determine whether INSN can be used in a combination. Return nonzero if
1504 not. This is used in try_combine to detect early some cases where we
1505 can't perform combinations. */
1508 cant_combine_insn_p (rtx insn
)
1513 /* If this isn't really an insn, we can't do anything.
1514 This can occur when flow deletes an insn that it has merged into an
1515 auto-increment address. */
1516 if (! INSN_P (insn
))
1519 /* Never combine loads and stores involving hard regs that are likely
1520 to be spilled. The register allocator can usually handle such
1521 reg-reg moves by tying. If we allow the combiner to make
1522 substitutions of likely-spilled regs, we may abort in reload.
1523 As an exception, we allow combinations involving fixed regs; these are
1524 not available to the register allocator so there's no risk involved. */
1526 set
= single_set (insn
);
1529 src
= SET_SRC (set
);
1530 dest
= SET_DEST (set
);
1531 if (GET_CODE (src
) == SUBREG
)
1532 src
= SUBREG_REG (src
);
1533 if (GET_CODE (dest
) == SUBREG
)
1534 dest
= SUBREG_REG (dest
);
1535 if (REG_P (src
) && REG_P (dest
)
1536 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1537 && ! fixed_regs
[REGNO (src
)]
1538 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1539 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1540 && ! fixed_regs
[REGNO (dest
)]
1541 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1547 /* Adjust INSN after we made a change to its destination.
1549 Changing the destination can invalidate notes that say something about
1550 the results of the insn and a LOG_LINK pointing to the insn. */
1553 adjust_for_new_dest (rtx insn
)
1557 /* For notes, be conservative and simply remove them. */
1558 loc
= ®_NOTES (insn
);
1561 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1562 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1563 *loc
= XEXP (*loc
, 1);
1565 loc
= &XEXP (*loc
, 1);
1568 /* The new insn will have a destination that was previously the destination
1569 of an insn just above it. Call distribute_links to make a LOG_LINK from
1570 the next use of that destination. */
1571 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1574 /* Try to combine the insns I1 and I2 into I3.
1575 Here I1 and I2 appear earlier than I3.
1576 I1 can be zero; then we combine just I2 into I3.
1578 If we are combining three insns and the resulting insn is not recognized,
1579 try splitting it into two insns. If that happens, I2 and I3 are retained
1580 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1583 Return 0 if the combination does not work. Then nothing is changed.
1584 If we did the combination, return the insn at which combine should
1587 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1588 new direct jump instruction. */
1591 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1593 /* New patterns for I3 and I2, respectively. */
1594 rtx newpat
, newi2pat
= 0;
1595 int substed_i2
= 0, substed_i1
= 0;
1596 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1597 int added_sets_1
, added_sets_2
;
1598 /* Total number of SETs to put into I3. */
1600 /* Nonzero if I2's body now appears in I3. */
1602 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1603 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1604 /* Contains I3 if the destination of I3 is used in its source, which means
1605 that the old life of I3 is being killed. If that usage is placed into
1606 I2 and not in I3, a REG_DEAD note must be made. */
1607 rtx i3dest_killed
= 0;
1608 /* SET_DEST and SET_SRC of I2 and I1. */
1609 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1610 /* PATTERN (I2), or a copy of it in certain cases. */
1612 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1613 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1614 int i1_feeds_i3
= 0;
1615 /* Notes that must be added to REG_NOTES in I3 and I2. */
1616 rtx new_i3_notes
, new_i2_notes
;
1617 /* Notes that we substituted I3 into I2 instead of the normal case. */
1618 int i3_subst_into_i2
= 0;
1619 /* Notes that I1, I2 or I3 is a MULT operation. */
1628 /* Exit early if one of the insns involved can't be used for
1630 if (cant_combine_insn_p (i3
)
1631 || cant_combine_insn_p (i2
)
1632 || (i1
&& cant_combine_insn_p (i1
))
1633 /* We also can't do anything if I3 has a
1634 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1637 /* ??? This gives worse code, and appears to be unnecessary, since no
1638 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1639 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1645 undobuf
.other_insn
= 0;
1647 /* Reset the hard register usage information. */
1648 CLEAR_HARD_REG_SET (newpat_used_regs
);
1650 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1651 code below, set I1 to be the earlier of the two insns. */
1652 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1653 temp
= i1
, i1
= i2
, i2
= temp
;
1655 added_links_insn
= 0;
1657 /* First check for one important special-case that the code below will
1658 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1659 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1660 we may be able to replace that destination with the destination of I3.
1661 This occurs in the common code where we compute both a quotient and
1662 remainder into a structure, in which case we want to do the computation
1663 directly into the structure to avoid register-register copies.
1665 Note that this case handles both multiple sets in I2 and also
1666 cases where I2 has a number of CLOBBER or PARALLELs.
1668 We make very conservative checks below and only try to handle the
1669 most common cases of this. For example, we only handle the case
1670 where I2 and I3 are adjacent to avoid making difficult register
1673 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
1674 && REG_P (SET_SRC (PATTERN (i3
)))
1675 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1676 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1677 && GET_CODE (PATTERN (i2
)) == PARALLEL
1678 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1679 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1680 below would need to check what is inside (and reg_overlap_mentioned_p
1681 doesn't support those codes anyway). Don't allow those destinations;
1682 the resulting insn isn't likely to be recognized anyway. */
1683 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1684 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1685 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1686 SET_DEST (PATTERN (i3
)))
1687 && next_real_insn (i2
) == i3
)
1689 rtx p2
= PATTERN (i2
);
1691 /* Make sure that the destination of I3,
1692 which we are going to substitute into one output of I2,
1693 is not used within another output of I2. We must avoid making this:
1694 (parallel [(set (mem (reg 69)) ...)
1695 (set (reg 69) ...)])
1696 which is not well-defined as to order of actions.
1697 (Besides, reload can't handle output reloads for this.)
1699 The problem can also happen if the dest of I3 is a memory ref,
1700 if another dest in I2 is an indirect memory ref. */
1701 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1702 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1703 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1704 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1705 SET_DEST (XVECEXP (p2
, 0, i
))))
1708 if (i
== XVECLEN (p2
, 0))
1709 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1710 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1711 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1712 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1717 subst_low_cuid
= INSN_CUID (i2
);
1719 added_sets_2
= added_sets_1
= 0;
1720 i2dest
= SET_SRC (PATTERN (i3
));
1722 /* Replace the dest in I2 with our dest and make the resulting
1723 insn the new pattern for I3. Then skip to where we
1724 validate the pattern. Everything was set up above. */
1725 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1726 SET_DEST (PATTERN (i3
)));
1729 i3_subst_into_i2
= 1;
1730 goto validate_replacement
;
1734 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1735 one of those words to another constant, merge them by making a new
1738 && (temp
= single_set (i2
)) != 0
1739 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1740 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1741 && REG_P (SET_DEST (temp
))
1742 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1743 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1744 && GET_CODE (PATTERN (i3
)) == SET
1745 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1746 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1747 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1748 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1749 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1751 HOST_WIDE_INT lo
, hi
;
1753 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1754 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1757 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1758 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1761 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1763 /* We don't handle the case of the target word being wider
1764 than a host wide int. */
1765 gcc_assert (HOST_BITS_PER_WIDE_INT
>= BITS_PER_WORD
);
1767 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1768 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1769 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1771 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1772 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1773 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1775 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1776 >> (HOST_BITS_PER_WIDE_INT
- 1));
1778 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1779 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1780 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1781 (INTVAL (SET_SRC (PATTERN (i3
)))));
1783 hi
= lo
< 0 ? -1 : 0;
1786 /* We don't handle the case of the higher word not fitting
1787 entirely in either hi or lo. */
1792 subst_low_cuid
= INSN_CUID (i2
);
1793 added_sets_2
= added_sets_1
= 0;
1794 i2dest
= SET_DEST (temp
);
1796 SUBST (SET_SRC (temp
),
1797 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1799 newpat
= PATTERN (i2
);
1800 goto validate_replacement
;
1804 /* If we have no I1 and I2 looks like:
1805 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1807 make up a dummy I1 that is
1810 (set (reg:CC X) (compare:CC Y (const_int 0)))
1812 (We can ignore any trailing CLOBBERs.)
1814 This undoes a previous combination and allows us to match a branch-and-
1817 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1818 && XVECLEN (PATTERN (i2
), 0) >= 2
1819 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1820 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1822 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1823 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1824 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1825 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
1826 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1827 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1829 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1830 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1835 /* We make I1 with the same INSN_UID as I2. This gives it
1836 the same INSN_CUID for value tracking. Our fake I1 will
1837 never appear in the insn stream so giving it the same INSN_UID
1838 as I2 will not cause a problem. */
1840 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1841 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1842 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1845 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1846 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1847 SET_DEST (PATTERN (i1
)));
1852 /* Verify that I2 and I1 are valid for combining. */
1853 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1854 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1860 /* Record whether I2DEST is used in I2SRC and similarly for the other
1861 cases. Knowing this will help in register status updating below. */
1862 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1863 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1864 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1866 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1868 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1870 /* Ensure that I3's pattern can be the destination of combines. */
1871 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1872 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1879 /* See if any of the insns is a MULT operation. Unless one is, we will
1880 reject a combination that is, since it must be slower. Be conservative
1882 if (GET_CODE (i2src
) == MULT
1883 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1884 || (GET_CODE (PATTERN (i3
)) == SET
1885 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1888 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1889 We used to do this EXCEPT in one case: I3 has a post-inc in an
1890 output operand. However, that exception can give rise to insns like
1892 which is a famous insn on the PDP-11 where the value of r3 used as the
1893 source was model-dependent. Avoid this sort of thing. */
1896 if (!(GET_CODE (PATTERN (i3
)) == SET
1897 && REG_P (SET_SRC (PATTERN (i3
)))
1898 && MEM_P (SET_DEST (PATTERN (i3
)))
1899 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1900 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1901 /* It's not the exception. */
1904 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1905 if (REG_NOTE_KIND (link
) == REG_INC
1906 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1908 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1915 /* See if the SETs in I1 or I2 need to be kept around in the merged
1916 instruction: whenever the value set there is still needed past I3.
1917 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1919 For the SET in I1, we have two cases: If I1 and I2 independently
1920 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1921 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1922 in I1 needs to be kept around unless I1DEST dies or is set in either
1923 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1924 I1DEST. If so, we know I1 feeds into I2. */
1926 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1929 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1930 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1932 /* If the set in I2 needs to be kept around, we must make a copy of
1933 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1934 PATTERN (I2), we are only substituting for the original I1DEST, not into
1935 an already-substituted copy. This also prevents making self-referential
1936 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1939 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1940 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1944 i2pat
= copy_rtx (i2pat
);
1948 /* Substitute in the latest insn for the regs set by the earlier ones. */
1950 maxreg
= max_reg_num ();
1954 /* It is possible that the source of I2 or I1 may be performing an
1955 unneeded operation, such as a ZERO_EXTEND of something that is known
1956 to have the high part zero. Handle that case by letting subst look at
1957 the innermost one of them.
1959 Another way to do this would be to have a function that tries to
1960 simplify a single insn instead of merging two or more insns. We don't
1961 do this because of the potential of infinite loops and because
1962 of the potential extra memory required. However, doing it the way
1963 we are is a bit of a kludge and doesn't catch all cases.
1965 But only do this if -fexpensive-optimizations since it slows things down
1966 and doesn't usually win. */
1968 if (flag_expensive_optimizations
)
1970 /* Pass pc_rtx so no substitutions are done, just simplifications. */
1973 subst_low_cuid
= INSN_CUID (i1
);
1974 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1978 subst_low_cuid
= INSN_CUID (i2
);
1979 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1984 /* Many machines that don't use CC0 have insns that can both perform an
1985 arithmetic operation and set the condition code. These operations will
1986 be represented as a PARALLEL with the first element of the vector
1987 being a COMPARE of an arithmetic operation with the constant zero.
1988 The second element of the vector will set some pseudo to the result
1989 of the same arithmetic operation. If we simplify the COMPARE, we won't
1990 match such a pattern and so will generate an extra insn. Here we test
1991 for this case, where both the comparison and the operation result are
1992 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1993 I2SRC. Later we will make the PARALLEL that contains I2. */
1995 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1996 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1997 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1998 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2000 #ifdef SELECT_CC_MODE
2002 enum machine_mode compare_mode
;
2005 newpat
= PATTERN (i3
);
2006 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
2010 #ifdef SELECT_CC_MODE
2011 /* See if a COMPARE with the operand we substituted in should be done
2012 with the mode that is currently being used. If not, do the same
2013 processing we do in `subst' for a SET; namely, if the destination
2014 is used only once, try to replace it with a register of the proper
2015 mode and also replace the COMPARE. */
2016 if (undobuf
.other_insn
== 0
2017 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
2018 &undobuf
.other_insn
))
2019 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
2021 != GET_MODE (SET_DEST (newpat
))))
2023 unsigned int regno
= REGNO (SET_DEST (newpat
));
2024 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
2026 if (regno
< FIRST_PSEUDO_REGISTER
2027 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
2028 && ! REG_USERVAR_P (SET_DEST (newpat
))))
2030 if (regno
>= FIRST_PSEUDO_REGISTER
)
2031 SUBST (regno_reg_rtx
[regno
], new_dest
);
2033 SUBST (SET_DEST (newpat
), new_dest
);
2034 SUBST (XEXP (*cc_use
, 0), new_dest
);
2035 SUBST (SET_SRC (newpat
),
2036 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
2039 undobuf
.other_insn
= 0;
2046 n_occurrences
= 0; /* `subst' counts here */
2048 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2049 need to make a unique copy of I2SRC each time we substitute it
2050 to avoid self-referential rtl. */
2052 subst_low_cuid
= INSN_CUID (i2
);
2053 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
2054 ! i1_feeds_i3
&& i1dest_in_i1src
);
2057 /* Record whether i2's body now appears within i3's body. */
2058 i2_is_used
= n_occurrences
;
2061 /* If we already got a failure, don't try to do more. Otherwise,
2062 try to substitute in I1 if we have it. */
2064 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
2066 /* Before we can do this substitution, we must redo the test done
2067 above (see detailed comments there) that ensures that I1DEST
2068 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2070 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
2078 subst_low_cuid
= INSN_CUID (i1
);
2079 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
2083 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2084 to count all the ways that I2SRC and I1SRC can be used. */
2085 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
2086 && i2_is_used
+ added_sets_2
> 1)
2087 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2088 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
2090 /* Fail if we tried to make a new register (we used to abort, but there's
2091 really no reason to). */
2092 || max_reg_num () != maxreg
2093 /* Fail if we couldn't do something and have a CLOBBER. */
2094 || GET_CODE (newpat
) == CLOBBER
2095 /* Fail if this new pattern is a MULT and we didn't have one before
2096 at the outer level. */
2097 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2104 /* If the actions of the earlier insns must be kept
2105 in addition to substituting them into the latest one,
2106 we must make a new PARALLEL for the latest insn
2107 to hold additional the SETs. */
2109 if (added_sets_1
|| added_sets_2
)
2113 if (GET_CODE (newpat
) == PARALLEL
)
2115 rtvec old
= XVEC (newpat
, 0);
2116 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2117 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2118 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2119 sizeof (old
->elem
[0]) * old
->num_elem
);
2124 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2125 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2126 XVECEXP (newpat
, 0, 0) = old
;
2130 XVECEXP (newpat
, 0, --total_sets
)
2131 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2132 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2136 /* If there is no I1, use I2's body as is. We used to also not do
2137 the subst call below if I2 was substituted into I3,
2138 but that could lose a simplification. */
2140 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2142 /* See comment where i2pat is assigned. */
2143 XVECEXP (newpat
, 0, --total_sets
)
2144 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2148 /* We come here when we are replacing a destination in I2 with the
2149 destination of I3. */
2150 validate_replacement
:
2152 /* Note which hard regs this insn has as inputs. */
2153 mark_used_regs_combine (newpat
);
2155 /* Is the result of combination a valid instruction? */
2156 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2158 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2159 the second SET's destination is a register that is unused and isn't
2160 marked as an instruction that might trap in an EH region. In that case,
2161 we just need the first SET. This can occur when simplifying a divmod
2162 insn. We *must* test for this case here because the code below that
2163 splits two independent SETs doesn't handle this case correctly when it
2164 updates the register status.
2166 It's pointless doing this if we originally had two sets, one from
2167 i3, and one from i2. Combining then splitting the parallel results
2168 in the original i2 again plus an invalid insn (which we delete).
2169 The net effect is only to move instructions around, which makes
2170 debug info less accurate.
2172 Also check the case where the first SET's destination is unused.
2173 That would not cause incorrect code, but does cause an unneeded
2176 if (insn_code_number
< 0
2177 && !(added_sets_2
&& i1
== 0)
2178 && GET_CODE (newpat
) == PARALLEL
2179 && XVECLEN (newpat
, 0) == 2
2180 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2181 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2182 && asm_noperands (newpat
) < 0)
2184 rtx set0
= XVECEXP (newpat
, 0, 0);
2185 rtx set1
= XVECEXP (newpat
, 0, 1);
2188 if (((REG_P (SET_DEST (set1
))
2189 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2190 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2191 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2192 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2193 || INTVAL (XEXP (note
, 0)) <= 0)
2194 && ! side_effects_p (SET_SRC (set1
)))
2197 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2200 else if (((REG_P (SET_DEST (set0
))
2201 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2202 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2203 && find_reg_note (i3
, REG_UNUSED
,
2204 SUBREG_REG (SET_DEST (set0
)))))
2205 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2206 || INTVAL (XEXP (note
, 0)) <= 0)
2207 && ! side_effects_p (SET_SRC (set0
)))
2210 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2212 if (insn_code_number
>= 0)
2214 /* If we will be able to accept this, we have made a
2215 change to the destination of I3. This requires us to
2216 do a few adjustments. */
2218 PATTERN (i3
) = newpat
;
2219 adjust_for_new_dest (i3
);
2224 /* If we were combining three insns and the result is a simple SET
2225 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2226 insns. There are two ways to do this. It can be split using a
2227 machine-specific method (like when you have an addition of a large
2228 constant) or by combine in the function find_split_point. */
2230 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2231 && asm_noperands (newpat
) < 0)
2233 rtx m_split
, *split
;
2234 rtx ni2dest
= i2dest
;
2236 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2237 use I2DEST as a scratch register will help. In the latter case,
2238 convert I2DEST to the mode of the source of NEWPAT if we can. */
2240 m_split
= split_insns (newpat
, i3
);
2242 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2243 inputs of NEWPAT. */
2245 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2246 possible to try that as a scratch reg. This would require adding
2247 more code to make it work though. */
2249 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2251 /* If I2DEST is a hard register or the only use of a pseudo,
2252 we can change its mode. */
2253 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2254 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2256 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2257 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2258 && ! REG_USERVAR_P (i2dest
))))
2259 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2262 m_split
= split_insns (gen_rtx_PARALLEL
2264 gen_rtvec (2, newpat
,
2265 gen_rtx_CLOBBER (VOIDmode
,
2268 /* If the split with the mode-changed register didn't work, try
2269 the original register. */
2270 if (! m_split
&& ni2dest
!= i2dest
)
2273 m_split
= split_insns (gen_rtx_PARALLEL
2275 gen_rtvec (2, newpat
,
2276 gen_rtx_CLOBBER (VOIDmode
,
2282 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2284 m_split
= PATTERN (m_split
);
2285 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2286 if (insn_code_number
>= 0)
2289 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2290 && (next_real_insn (i2
) == i3
2291 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2294 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2295 newi2pat
= PATTERN (m_split
);
2297 i3set
= single_set (NEXT_INSN (m_split
));
2298 i2set
= single_set (m_split
);
2300 /* In case we changed the mode of I2DEST, replace it in the
2301 pseudo-register table here. We can't do it above in case this
2302 code doesn't get executed and we do a split the other way. */
2304 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2305 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2307 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2309 /* If I2 or I3 has multiple SETs, we won't know how to track
2310 register status, so don't use these insns. If I2's destination
2311 is used between I2 and I3, we also can't use these insns. */
2313 if (i2_code_number
>= 0 && i2set
&& i3set
2314 && (next_real_insn (i2
) == i3
2315 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2316 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2318 if (insn_code_number
>= 0)
2321 /* It is possible that both insns now set the destination of I3.
2322 If so, we must show an extra use of it. */
2324 if (insn_code_number
>= 0)
2326 rtx new_i3_dest
= SET_DEST (i3set
);
2327 rtx new_i2_dest
= SET_DEST (i2set
);
2329 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2330 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2331 || GET_CODE (new_i3_dest
) == SUBREG
)
2332 new_i3_dest
= XEXP (new_i3_dest
, 0);
2334 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2335 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2336 || GET_CODE (new_i2_dest
) == SUBREG
)
2337 new_i2_dest
= XEXP (new_i2_dest
, 0);
2339 if (REG_P (new_i3_dest
)
2340 && REG_P (new_i2_dest
)
2341 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2342 REG_N_SETS (REGNO (new_i2_dest
))++;
2346 /* If we can split it and use I2DEST, go ahead and see if that
2347 helps things be recognized. Verify that none of the registers
2348 are set between I2 and I3. */
2349 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2353 /* We need I2DEST in the proper mode. If it is a hard register
2354 or the only use of a pseudo, we can change its mode. */
2355 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2356 || GET_MODE (*split
) == VOIDmode
2357 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2358 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2359 && ! REG_USERVAR_P (i2dest
)))
2360 && (next_real_insn (i2
) == i3
2361 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2362 /* We can't overwrite I2DEST if its value is still used by
2364 && ! reg_referenced_p (i2dest
, newpat
))
2366 rtx newdest
= i2dest
;
2367 enum rtx_code split_code
= GET_CODE (*split
);
2368 enum machine_mode split_mode
= GET_MODE (*split
);
2370 /* Get NEWDEST as a register in the proper mode. We have already
2371 validated that we can do this. */
2372 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2374 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2376 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2377 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2380 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2381 an ASHIFT. This can occur if it was inside a PLUS and hence
2382 appeared to be a memory address. This is a kludge. */
2383 if (split_code
== MULT
2384 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2385 && INTVAL (XEXP (*split
, 1)) > 0
2386 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2388 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2389 XEXP (*split
, 0), GEN_INT (i
)));
2390 /* Update split_code because we may not have a multiply
2392 split_code
= GET_CODE (*split
);
2395 #ifdef INSN_SCHEDULING
2396 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2397 be written as a ZERO_EXTEND. */
2398 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
2400 #ifdef LOAD_EXTEND_OP
2401 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2402 what it really is. */
2403 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2405 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2406 SUBREG_REG (*split
)));
2409 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2410 SUBREG_REG (*split
)));
2414 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2415 SUBST (*split
, newdest
);
2416 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2418 /* If the split point was a MULT and we didn't have one before,
2419 don't use one now. */
2420 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2421 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2425 /* Check for a case where we loaded from memory in a narrow mode and
2426 then sign extended it, but we need both registers. In that case,
2427 we have a PARALLEL with both loads from the same memory location.
2428 We can split this into a load from memory followed by a register-register
2429 copy. This saves at least one insn, more if register allocation can
2432 We cannot do this if the destination of the first assignment is a
2433 condition code register or cc0. We eliminate this case by making sure
2434 the SET_DEST and SET_SRC have the same mode.
2436 We cannot do this if the destination of the second assignment is
2437 a register that we have already assumed is zero-extended. Similarly
2438 for a SUBREG of such a register. */
2440 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2441 && GET_CODE (newpat
) == PARALLEL
2442 && XVECLEN (newpat
, 0) == 2
2443 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2444 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2445 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2446 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2447 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2448 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2449 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2450 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2452 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2453 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2454 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2456 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2457 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2458 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2459 && (reg_stat
[REGNO (temp
)].nonzero_bits
2460 != GET_MODE_MASK (word_mode
))))
2461 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2462 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2464 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2465 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2466 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2467 && (reg_stat
[REGNO (temp
)].nonzero_bits
2468 != GET_MODE_MASK (word_mode
)))))
2469 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2470 SET_SRC (XVECEXP (newpat
, 0, 1)))
2471 && ! find_reg_note (i3
, REG_UNUSED
,
2472 SET_DEST (XVECEXP (newpat
, 0, 0))))
2476 newi2pat
= XVECEXP (newpat
, 0, 0);
2477 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2478 newpat
= XVECEXP (newpat
, 0, 1);
2479 SUBST (SET_SRC (newpat
),
2480 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2481 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2483 if (i2_code_number
>= 0)
2484 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2486 if (insn_code_number
>= 0)
2490 /* Similarly, check for a case where we have a PARALLEL of two independent
2491 SETs but we started with three insns. In this case, we can do the sets
2492 as two separate insns. This case occurs when some SET allows two
2493 other insns to combine, but the destination of that SET is still live. */
2495 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2496 && GET_CODE (newpat
) == PARALLEL
2497 && XVECLEN (newpat
, 0) == 2
2498 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2499 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2500 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2501 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2502 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2503 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2504 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2506 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2507 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2508 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2509 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2510 XVECEXP (newpat
, 0, 0))
2511 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2512 XVECEXP (newpat
, 0, 1))
2513 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2514 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2516 /* Normally, it doesn't matter which of the two is done first,
2517 but it does if one references cc0. In that case, it has to
2520 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2522 newi2pat
= XVECEXP (newpat
, 0, 0);
2523 newpat
= XVECEXP (newpat
, 0, 1);
2528 newi2pat
= XVECEXP (newpat
, 0, 1);
2529 newpat
= XVECEXP (newpat
, 0, 0);
2532 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2534 if (i2_code_number
>= 0)
2535 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2538 /* If it still isn't recognized, fail and change things back the way they
2540 if ((insn_code_number
< 0
2541 /* Is the result a reasonable ASM_OPERANDS? */
2542 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2548 /* If we had to change another insn, make sure it is valid also. */
2549 if (undobuf
.other_insn
)
2551 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2552 rtx new_other_notes
;
2555 CLEAR_HARD_REG_SET (newpat_used_regs
);
2557 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2560 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2566 PATTERN (undobuf
.other_insn
) = other_pat
;
2568 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2569 are still valid. Then add any non-duplicate notes added by
2570 recog_for_combine. */
2571 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2573 next
= XEXP (note
, 1);
2575 if (REG_NOTE_KIND (note
) == REG_UNUSED
2576 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2578 if (REG_P (XEXP (note
, 0)))
2579 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2581 remove_note (undobuf
.other_insn
, note
);
2585 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2586 if (REG_P (XEXP (note
, 0)))
2587 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2589 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2590 undobuf
.other_insn
, NULL_RTX
);
2593 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2594 they are adjacent to each other or not. */
2596 rtx p
= prev_nonnote_insn (i3
);
2597 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
2598 && sets_cc0_p (newi2pat
))
2606 /* Only allow this combination if insn_rtx_costs reports that the
2607 replacement instructions are cheaper than the originals. */
2608 if (!combine_validate_cost (i1
, i2
, i3
, newpat
, newi2pat
))
2614 /* We now know that we can do this combination. Merge the insns and
2615 update the status of registers and LOG_LINKS. */
2623 /* I3 now uses what used to be its destination and which is now
2624 I2's destination. This requires us to do a few adjustments. */
2625 PATTERN (i3
) = newpat
;
2626 adjust_for_new_dest (i3
);
2628 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2631 However, some later insn might be using I2's dest and have
2632 a LOG_LINK pointing at I3. We must remove this link.
2633 The simplest way to remove the link is to point it at I1,
2634 which we know will be a NOTE. */
2636 /* newi2pat is usually a SET here; however, recog_for_combine might
2637 have added some clobbers. */
2638 if (GET_CODE (newi2pat
) == PARALLEL
)
2639 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
2641 ni2dest
= SET_DEST (newi2pat
);
2643 for (insn
= NEXT_INSN (i3
);
2644 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2645 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
2646 insn
= NEXT_INSN (insn
))
2648 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2650 for (link
= LOG_LINKS (insn
); link
;
2651 link
= XEXP (link
, 1))
2652 if (XEXP (link
, 0) == i3
)
2653 XEXP (link
, 0) = i1
;
2661 rtx i3notes
, i2notes
, i1notes
= 0;
2662 rtx i3links
, i2links
, i1links
= 0;
2666 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2668 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2669 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2671 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2673 /* Ensure that we do not have something that should not be shared but
2674 occurs multiple times in the new insns. Check this by first
2675 resetting all the `used' flags and then copying anything is shared. */
2677 reset_used_flags (i3notes
);
2678 reset_used_flags (i2notes
);
2679 reset_used_flags (i1notes
);
2680 reset_used_flags (newpat
);
2681 reset_used_flags (newi2pat
);
2682 if (undobuf
.other_insn
)
2683 reset_used_flags (PATTERN (undobuf
.other_insn
));
2685 i3notes
= copy_rtx_if_shared (i3notes
);
2686 i2notes
= copy_rtx_if_shared (i2notes
);
2687 i1notes
= copy_rtx_if_shared (i1notes
);
2688 newpat
= copy_rtx_if_shared (newpat
);
2689 newi2pat
= copy_rtx_if_shared (newi2pat
);
2690 if (undobuf
.other_insn
)
2691 reset_used_flags (PATTERN (undobuf
.other_insn
));
2693 INSN_CODE (i3
) = insn_code_number
;
2694 PATTERN (i3
) = newpat
;
2696 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
2698 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2700 reset_used_flags (call_usage
);
2701 call_usage
= copy_rtx (call_usage
);
2704 replace_rtx (call_usage
, i2dest
, i2src
);
2707 replace_rtx (call_usage
, i1dest
, i1src
);
2709 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2712 if (undobuf
.other_insn
)
2713 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2715 /* We had one special case above where I2 had more than one set and
2716 we replaced a destination of one of those sets with the destination
2717 of I3. In that case, we have to update LOG_LINKS of insns later
2718 in this basic block. Note that this (expensive) case is rare.
2720 Also, in this case, we must pretend that all REG_NOTEs for I2
2721 actually came from I3, so that REG_UNUSED notes from I2 will be
2722 properly handled. */
2724 if (i3_subst_into_i2
)
2726 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2727 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2728 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
2729 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2730 && ! find_reg_note (i2
, REG_UNUSED
,
2731 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2732 for (temp
= NEXT_INSN (i2
);
2733 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2734 || BB_HEAD (this_basic_block
) != temp
);
2735 temp
= NEXT_INSN (temp
))
2736 if (temp
!= i3
&& INSN_P (temp
))
2737 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2738 if (XEXP (link
, 0) == i2
)
2739 XEXP (link
, 0) = i3
;
2744 while (XEXP (link
, 1))
2745 link
= XEXP (link
, 1);
2746 XEXP (link
, 1) = i2notes
;
2760 INSN_CODE (i2
) = i2_code_number
;
2761 PATTERN (i2
) = newi2pat
;
2764 SET_INSN_DELETED (i2
);
2770 SET_INSN_DELETED (i1
);
2773 /* Get death notes for everything that is now used in either I3 or
2774 I2 and used to die in a previous insn. If we built two new
2775 patterns, move from I1 to I2 then I2 to I3 so that we get the
2776 proper movement on registers that I2 modifies. */
2780 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2781 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2784 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2787 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2789 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2791 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2793 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2795 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2797 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2798 know these are REG_UNUSED and want them to go to the desired insn,
2799 so we always pass it as i3. We have not counted the notes in
2800 reg_n_deaths yet, so we need to do so now. */
2802 if (newi2pat
&& new_i2_notes
)
2804 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2805 if (REG_P (XEXP (temp
, 0)))
2806 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2808 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2813 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2814 if (REG_P (XEXP (temp
, 0)))
2815 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2817 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2820 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2821 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2822 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2823 in that case, it might delete I2. Similarly for I2 and I1.
2824 Show an additional death due to the REG_DEAD note we make here. If
2825 we discard it in distribute_notes, we will decrement it again. */
2829 if (REG_P (i3dest_killed
))
2830 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2832 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2833 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2835 NULL_RTX
, i2
, NULL_RTX
);
2837 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2839 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2842 if (i2dest_in_i2src
)
2845 REG_N_DEATHS (REGNO (i2dest
))++;
2847 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2848 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2849 NULL_RTX
, i2
, NULL_RTX
);
2851 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2852 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2855 if (i1dest_in_i1src
)
2858 REG_N_DEATHS (REGNO (i1dest
))++;
2860 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2861 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2862 NULL_RTX
, i2
, NULL_RTX
);
2864 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2865 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2868 distribute_links (i3links
);
2869 distribute_links (i2links
);
2870 distribute_links (i1links
);
2875 rtx i2_insn
= 0, i2_val
= 0, set
;
2877 /* The insn that used to set this register doesn't exist, and
2878 this life of the register may not exist either. See if one of
2879 I3's links points to an insn that sets I2DEST. If it does,
2880 that is now the last known value for I2DEST. If we don't update
2881 this and I2 set the register to a value that depended on its old
2882 contents, we will get confused. If this insn is used, thing
2883 will be set correctly in combine_instructions. */
2885 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2886 if ((set
= single_set (XEXP (link
, 0))) != 0
2887 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2888 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2890 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2892 /* If the reg formerly set in I2 died only once and that was in I3,
2893 zero its use count so it won't make `reload' do any work. */
2895 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2896 && ! i2dest_in_i2src
)
2898 regno
= REGNO (i2dest
);
2899 REG_N_SETS (regno
)--;
2903 if (i1
&& REG_P (i1dest
))
2906 rtx i1_insn
= 0, i1_val
= 0, set
;
2908 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2909 if ((set
= single_set (XEXP (link
, 0))) != 0
2910 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2911 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2913 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2915 regno
= REGNO (i1dest
);
2916 if (! added_sets_1
&& ! i1dest_in_i1src
)
2917 REG_N_SETS (regno
)--;
2920 /* Update reg_stat[].nonzero_bits et al for any changes that may have
2921 been made to this insn. The order of
2922 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
2923 can affect nonzero_bits of newpat */
2925 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2926 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2928 /* Set new_direct_jump_p if a new return or simple jump instruction
2931 If I3 is now an unconditional jump, ensure that it has a
2932 BARRIER following it since it may have initially been a
2933 conditional jump. It may also be the last nonnote insn. */
2935 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2937 *new_direct_jump_p
= 1;
2938 mark_jump_label (PATTERN (i3
), i3
, 0);
2940 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2941 || !BARRIER_P (temp
))
2942 emit_barrier_after (i3
);
2945 if (undobuf
.other_insn
!= NULL_RTX
2946 && (returnjump_p (undobuf
.other_insn
)
2947 || any_uncondjump_p (undobuf
.other_insn
)))
2949 *new_direct_jump_p
= 1;
2951 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2952 || !BARRIER_P (temp
))
2953 emit_barrier_after (undobuf
.other_insn
);
2956 /* An NOOP jump does not need barrier, but it does need cleaning up
2958 if (GET_CODE (newpat
) == SET
2959 && SET_SRC (newpat
) == pc_rtx
2960 && SET_DEST (newpat
) == pc_rtx
)
2961 *new_direct_jump_p
= 1;
2964 combine_successes
++;
2967 if (added_links_insn
2968 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2969 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2970 return added_links_insn
;
2972 return newi2pat
? i2
: i3
;
2975 /* Undo all the modifications recorded in undobuf. */
2980 struct undo
*undo
, *next
;
2982 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2986 *undo
->where
.i
= undo
->old_contents
.i
;
2988 *undo
->where
.r
= undo
->old_contents
.r
;
2990 undo
->next
= undobuf
.frees
;
2991 undobuf
.frees
= undo
;
2997 /* We've committed to accepting the changes we made. Move all
2998 of the undos to the free list. */
3003 struct undo
*undo
, *next
;
3005 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3008 undo
->next
= undobuf
.frees
;
3009 undobuf
.frees
= undo
;
3015 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3016 where we have an arithmetic expression and return that point. LOC will
3019 try_combine will call this function to see if an insn can be split into
3023 find_split_point (rtx
*loc
, rtx insn
)
3026 enum rtx_code code
= GET_CODE (x
);
3028 unsigned HOST_WIDE_INT len
= 0;
3029 HOST_WIDE_INT pos
= 0;
3031 rtx inner
= NULL_RTX
;
3033 /* First special-case some codes. */
3037 #ifdef INSN_SCHEDULING
3038 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3040 if (MEM_P (SUBREG_REG (x
)))
3043 return find_split_point (&SUBREG_REG (x
), insn
);
3047 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3048 using LO_SUM and HIGH. */
3049 if (GET_CODE (XEXP (x
, 0)) == CONST
3050 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
3053 gen_rtx_LO_SUM (Pmode
,
3054 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
3056 return &XEXP (XEXP (x
, 0), 0);
3060 /* If we have a PLUS whose second operand is a constant and the
3061 address is not valid, perhaps will can split it up using
3062 the machine-specific way to split large constants. We use
3063 the first pseudo-reg (one of the virtual regs) as a placeholder;
3064 it will not remain in the result. */
3065 if (GET_CODE (XEXP (x
, 0)) == PLUS
3066 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3067 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
3069 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
3070 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
3073 /* This should have produced two insns, each of which sets our
3074 placeholder. If the source of the second is a valid address,
3075 we can make put both sources together and make a split point
3079 && NEXT_INSN (seq
) != NULL_RTX
3080 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
3081 && NONJUMP_INSN_P (seq
)
3082 && GET_CODE (PATTERN (seq
)) == SET
3083 && SET_DEST (PATTERN (seq
)) == reg
3084 && ! reg_mentioned_p (reg
,
3085 SET_SRC (PATTERN (seq
)))
3086 && NONJUMP_INSN_P (NEXT_INSN (seq
))
3087 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
3088 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
3089 && memory_address_p (GET_MODE (x
),
3090 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
3092 rtx src1
= SET_SRC (PATTERN (seq
));
3093 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
3095 /* Replace the placeholder in SRC2 with SRC1. If we can
3096 find where in SRC2 it was placed, that can become our
3097 split point and we can replace this address with SRC2.
3098 Just try two obvious places. */
3100 src2
= replace_rtx (src2
, reg
, src1
);
3102 if (XEXP (src2
, 0) == src1
)
3103 split
= &XEXP (src2
, 0);
3104 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
3105 && XEXP (XEXP (src2
, 0), 0) == src1
)
3106 split
= &XEXP (XEXP (src2
, 0), 0);
3110 SUBST (XEXP (x
, 0), src2
);
3115 /* If that didn't work, perhaps the first operand is complex and
3116 needs to be computed separately, so make a split point there.
3117 This will occur on machines that just support REG + CONST
3118 and have a constant moved through some previous computation. */
3120 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
3121 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
3122 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
3123 return &XEXP (XEXP (x
, 0), 0);
3129 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3130 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3131 we need to put the operand into a register. So split at that
3134 if (SET_DEST (x
) == cc0_rtx
3135 && GET_CODE (SET_SRC (x
)) != COMPARE
3136 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
3137 && !OBJECT_P (SET_SRC (x
))
3138 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
3139 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
3140 return &SET_SRC (x
);
3143 /* See if we can split SET_SRC as it stands. */
3144 split
= find_split_point (&SET_SRC (x
), insn
);
3145 if (split
&& split
!= &SET_SRC (x
))
3148 /* See if we can split SET_DEST as it stands. */
3149 split
= find_split_point (&SET_DEST (x
), insn
);
3150 if (split
&& split
!= &SET_DEST (x
))
3153 /* See if this is a bitfield assignment with everything constant. If
3154 so, this is an IOR of an AND, so split it into that. */
3155 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3156 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
3157 <= HOST_BITS_PER_WIDE_INT
)
3158 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3159 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3160 && GET_CODE (SET_SRC (x
)) == CONST_INT
3161 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3162 + INTVAL (XEXP (SET_DEST (x
), 2)))
3163 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3164 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3166 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3167 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3168 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3169 rtx dest
= XEXP (SET_DEST (x
), 0);
3170 enum machine_mode mode
= GET_MODE (dest
);
3171 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3173 if (BITS_BIG_ENDIAN
)
3174 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3178 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3181 gen_binary (IOR
, mode
,
3182 gen_binary (AND
, mode
, dest
,
3183 gen_int_mode (~(mask
<< pos
),
3185 GEN_INT (src
<< pos
)));
3187 SUBST (SET_DEST (x
), dest
);
3189 split
= find_split_point (&SET_SRC (x
), insn
);
3190 if (split
&& split
!= &SET_SRC (x
))
3194 /* Otherwise, see if this is an operation that we can split into two.
3195 If so, try to split that. */
3196 code
= GET_CODE (SET_SRC (x
));
3201 /* If we are AND'ing with a large constant that is only a single
3202 bit and the result is only being used in a context where we
3203 need to know if it is zero or nonzero, replace it with a bit
3204 extraction. This will avoid the large constant, which might
3205 have taken more than one insn to make. If the constant were
3206 not a valid argument to the AND but took only one insn to make,
3207 this is no worse, but if it took more than one insn, it will
3210 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3211 && REG_P (XEXP (SET_SRC (x
), 0))
3212 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3213 && REG_P (SET_DEST (x
))
3214 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3215 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3216 && XEXP (*split
, 0) == SET_DEST (x
)
3217 && XEXP (*split
, 1) == const0_rtx
)
3219 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3220 XEXP (SET_SRC (x
), 0),
3221 pos
, NULL_RTX
, 1, 1, 0, 0);
3222 if (extraction
!= 0)
3224 SUBST (SET_SRC (x
), extraction
);
3225 return find_split_point (loc
, insn
);
3231 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3232 is known to be on, this can be converted into a NEG of a shift. */
3233 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3234 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3235 && 1 <= (pos
= exact_log2
3236 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3237 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3239 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3243 gen_rtx_LSHIFTRT (mode
,
3244 XEXP (SET_SRC (x
), 0),
3247 split
= find_split_point (&SET_SRC (x
), insn
);
3248 if (split
&& split
!= &SET_SRC (x
))
3254 inner
= XEXP (SET_SRC (x
), 0);
3256 /* We can't optimize if either mode is a partial integer
3257 mode as we don't know how many bits are significant
3259 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3260 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3264 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3270 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3271 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3273 inner
= XEXP (SET_SRC (x
), 0);
3274 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3275 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3277 if (BITS_BIG_ENDIAN
)
3278 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3279 unsignedp
= (code
== ZERO_EXTRACT
);
3287 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3289 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3291 /* For unsigned, we have a choice of a shift followed by an
3292 AND or two shifts. Use two shifts for field sizes where the
3293 constant might be too large. We assume here that we can
3294 always at least get 8-bit constants in an AND insn, which is
3295 true for every current RISC. */
3297 if (unsignedp
&& len
<= 8)
3302 (mode
, gen_lowpart (mode
, inner
),
3304 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3306 split
= find_split_point (&SET_SRC (x
), insn
);
3307 if (split
&& split
!= &SET_SRC (x
))
3314 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3315 gen_rtx_ASHIFT (mode
,
3316 gen_lowpart (mode
, inner
),
3317 GEN_INT (GET_MODE_BITSIZE (mode
)
3319 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3321 split
= find_split_point (&SET_SRC (x
), insn
);
3322 if (split
&& split
!= &SET_SRC (x
))
3327 /* See if this is a simple operation with a constant as the second
3328 operand. It might be that this constant is out of range and hence
3329 could be used as a split point. */
3330 if (BINARY_P (SET_SRC (x
))
3331 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3332 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
3333 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3334 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
3335 return &XEXP (SET_SRC (x
), 1);
3337 /* Finally, see if this is a simple operation with its first operand
3338 not in a register. The operation might require this operand in a
3339 register, so return it as a split point. We can always do this
3340 because if the first operand were another operation, we would have
3341 already found it as a split point. */
3342 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
3343 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3344 return &XEXP (SET_SRC (x
), 0);
3350 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3351 it is better to write this as (not (ior A B)) so we can split it.
3352 Similarly for IOR. */
3353 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3356 gen_rtx_NOT (GET_MODE (x
),
3357 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3359 XEXP (XEXP (x
, 0), 0),
3360 XEXP (XEXP (x
, 1), 0))));
3361 return find_split_point (loc
, insn
);
3364 /* Many RISC machines have a large set of logical insns. If the
3365 second operand is a NOT, put it first so we will try to split the
3366 other operand first. */
3367 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3369 rtx tem
= XEXP (x
, 0);
3370 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3371 SUBST (XEXP (x
, 1), tem
);
3379 /* Otherwise, select our actions depending on our rtx class. */
3380 switch (GET_RTX_CLASS (code
))
3382 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3384 split
= find_split_point (&XEXP (x
, 2), insn
);
3387 /* ... fall through ... */
3389 case RTX_COMM_ARITH
:
3391 case RTX_COMM_COMPARE
:
3392 split
= find_split_point (&XEXP (x
, 1), insn
);
3395 /* ... fall through ... */
3397 /* Some machines have (and (shift ...) ...) insns. If X is not
3398 an AND, but XEXP (X, 0) is, use it as our split point. */
3399 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3400 return &XEXP (x
, 0);
3402 split
= find_split_point (&XEXP (x
, 0), insn
);
3408 /* Otherwise, we don't have a split point. */
3413 /* Throughout X, replace FROM with TO, and return the result.
3414 The result is TO if X is FROM;
3415 otherwise the result is X, but its contents may have been modified.
3416 If they were modified, a record was made in undobuf so that
3417 undo_all will (among other things) return X to its original state.
3419 If the number of changes necessary is too much to record to undo,
3420 the excess changes are not made, so the result is invalid.
3421 The changes already made can still be undone.
3422 undobuf.num_undo is incremented for such changes, so by testing that
3423 the caller can tell whether the result is valid.
3425 `n_occurrences' is incremented each time FROM is replaced.
3427 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3429 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3430 by copying if `n_occurrences' is nonzero. */
3433 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3435 enum rtx_code code
= GET_CODE (x
);
3436 enum machine_mode op0_mode
= VOIDmode
;
3441 /* Two expressions are equal if they are identical copies of a shared
3442 RTX or if they are both registers with the same register number
3445 #define COMBINE_RTX_EQUAL_P(X,Y) \
3447 || (REG_P (X) && REG_P (Y) \
3448 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3450 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3453 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3456 /* If X and FROM are the same register but different modes, they will
3457 not have been seen as equal above. However, flow.c will make a
3458 LOG_LINKS entry for that case. If we do nothing, we will try to
3459 rerecognize our original insn and, when it succeeds, we will
3460 delete the feeding insn, which is incorrect.
3462 So force this insn not to match in this (rare) case. */
3463 if (! in_dest
&& code
== REG
&& REG_P (from
)
3464 && REGNO (x
) == REGNO (from
))
3465 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3467 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3468 of which may contain things that can be combined. */
3469 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
3472 /* It is possible to have a subexpression appear twice in the insn.
3473 Suppose that FROM is a register that appears within TO.
3474 Then, after that subexpression has been scanned once by `subst',
3475 the second time it is scanned, TO may be found. If we were
3476 to scan TO here, we would find FROM within it and create a
3477 self-referent rtl structure which is completely wrong. */
3478 if (COMBINE_RTX_EQUAL_P (x
, to
))
3481 /* Parallel asm_operands need special attention because all of the
3482 inputs are shared across the arms. Furthermore, unsharing the
3483 rtl results in recognition failures. Failure to handle this case
3484 specially can result in circular rtl.
3486 Solve this by doing a normal pass across the first entry of the
3487 parallel, and only processing the SET_DESTs of the subsequent
3490 if (code
== PARALLEL
3491 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3492 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3494 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3496 /* If this substitution failed, this whole thing fails. */
3497 if (GET_CODE (new) == CLOBBER
3498 && XEXP (new, 0) == const0_rtx
)
3501 SUBST (XVECEXP (x
, 0, 0), new);
3503 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3505 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3508 && GET_CODE (dest
) != CC0
3509 && GET_CODE (dest
) != PC
)
3511 new = subst (dest
, from
, to
, 0, unique_copy
);
3513 /* If this substitution failed, this whole thing fails. */
3514 if (GET_CODE (new) == CLOBBER
3515 && XEXP (new, 0) == const0_rtx
)
3518 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3524 len
= GET_RTX_LENGTH (code
);
3525 fmt
= GET_RTX_FORMAT (code
);
3527 /* We don't need to process a SET_DEST that is a register, CC0,
3528 or PC, so set up to skip this common case. All other cases
3529 where we want to suppress replacing something inside a
3530 SET_SRC are handled via the IN_DEST operand. */
3532 && (REG_P (SET_DEST (x
))
3533 || GET_CODE (SET_DEST (x
)) == CC0
3534 || GET_CODE (SET_DEST (x
)) == PC
))
3537 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3540 op0_mode
= GET_MODE (XEXP (x
, 0));
3542 for (i
= 0; i
< len
; i
++)
3547 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3549 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3551 new = (unique_copy
&& n_occurrences
3552 ? copy_rtx (to
) : to
);
3557 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3560 /* If this substitution failed, this whole thing
3562 if (GET_CODE (new) == CLOBBER
3563 && XEXP (new, 0) == const0_rtx
)
3567 SUBST (XVECEXP (x
, i
, j
), new);
3570 else if (fmt
[i
] == 'e')
3572 /* If this is a register being set, ignore it. */
3576 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
3578 || code
== STRICT_LOW_PART
))
3581 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3583 /* In general, don't install a subreg involving two
3584 modes not tieable. It can worsen register
3585 allocation, and can even make invalid reload
3586 insns, since the reg inside may need to be copied
3587 from in the outside mode, and that may be invalid
3588 if it is an fp reg copied in integer mode.
3590 We allow two exceptions to this: It is valid if
3591 it is inside another SUBREG and the mode of that
3592 SUBREG and the mode of the inside of TO is
3593 tieable and it is valid if X is a SET that copies
3596 if (GET_CODE (to
) == SUBREG
3597 && ! MODES_TIEABLE_P (GET_MODE (to
),
3598 GET_MODE (SUBREG_REG (to
)))
3599 && ! (code
== SUBREG
3600 && MODES_TIEABLE_P (GET_MODE (x
),
3601 GET_MODE (SUBREG_REG (to
))))
3603 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3606 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3608 #ifdef CANNOT_CHANGE_MODE_CLASS
3611 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3612 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3615 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3618 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3622 /* If we are in a SET_DEST, suppress most cases unless we
3623 have gone inside a MEM, in which case we want to
3624 simplify the address. We assume here that things that
3625 are actually part of the destination have their inner
3626 parts in the first expression. This is true for SUBREG,
3627 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3628 things aside from REG and MEM that should appear in a
3630 new = subst (XEXP (x
, i
), from
, to
,
3632 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3633 || code
== ZERO_EXTRACT
))
3635 && i
== 0), unique_copy
);
3637 /* If we found that we will have to reject this combination,
3638 indicate that by returning the CLOBBER ourselves, rather than
3639 an expression containing it. This will speed things up as
3640 well as prevent accidents where two CLOBBERs are considered
3641 to be equal, thus producing an incorrect simplification. */
3643 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3646 if (GET_CODE (x
) == SUBREG
3647 && (GET_CODE (new) == CONST_INT
3648 || GET_CODE (new) == CONST_DOUBLE
))
3650 enum machine_mode mode
= GET_MODE (x
);
3652 x
= simplify_subreg (GET_MODE (x
), new,
3653 GET_MODE (SUBREG_REG (x
)),
3656 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3658 else if (GET_CODE (new) == CONST_INT
3659 && GET_CODE (x
) == ZERO_EXTEND
)
3661 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3662 new, GET_MODE (XEXP (x
, 0)));
3666 SUBST (XEXP (x
, i
), new);
3671 /* Try to simplify X. If the simplification changed the code, it is likely
3672 that further simplification will help, so loop, but limit the number
3673 of repetitions that will be performed. */
3675 for (i
= 0; i
< 4; i
++)
3677 /* If X is sufficiently simple, don't bother trying to do anything
3679 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3680 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
3682 if (GET_CODE (x
) == code
)
3685 code
= GET_CODE (x
);
3687 /* We no longer know the original mode of operand 0 since we
3688 have changed the form of X) */
3689 op0_mode
= VOIDmode
;
3695 /* Simplify X, a piece of RTL. We just operate on the expression at the
3696 outer level; call `subst' to simplify recursively. Return the new
3699 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3700 if we are inside a SET_DEST. */
3703 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
3705 enum rtx_code code
= GET_CODE (x
);
3706 enum machine_mode mode
= GET_MODE (x
);
3711 /* If this is a commutative operation, put a constant last and a complex
3712 expression first. We don't need to do this for comparisons here. */
3713 if (COMMUTATIVE_ARITH_P (x
)
3714 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3717 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3718 SUBST (XEXP (x
, 1), temp
);
3721 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3722 sign extension of a PLUS with a constant, reverse the order of the sign
3723 extension and the addition. Note that this not the same as the original
3724 code, but overflow is undefined for signed values. Also note that the
3725 PLUS will have been partially moved "inside" the sign-extension, so that
3726 the first operand of X will really look like:
3727 (ashiftrt (plus (ashift A C4) C5) C4).
3729 (plus (ashiftrt (ashift A C4) C2) C4)
3730 and replace the first operand of X with that expression. Later parts
3731 of this function may simplify the expression further.
3733 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3734 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3735 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3737 We do this to simplify address expressions. */
3739 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3740 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3741 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3742 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3743 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3744 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3745 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3746 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3747 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3748 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3749 XEXP (XEXP (x
, 0), 1))) != 0)
3752 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3753 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3754 INTVAL (XEXP (XEXP (x
, 0), 1)));
3756 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3757 INTVAL (XEXP (XEXP (x
, 0), 1)));
3759 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3762 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3763 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3764 things. Check for cases where both arms are testing the same
3767 Don't do anything if all operands are very simple. */
3770 && ((!OBJECT_P (XEXP (x
, 0))
3771 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3772 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
3773 || (!OBJECT_P (XEXP (x
, 1))
3774 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3775 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
3777 && (!OBJECT_P (XEXP (x
, 0))
3778 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3779 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
3781 rtx cond
, true_rtx
, false_rtx
;
3783 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3785 /* If everything is a comparison, what we have is highly unlikely
3786 to be simpler, so don't use it. */
3787 && ! (COMPARISON_P (x
)
3788 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
3790 rtx cop1
= const0_rtx
;
3791 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3793 if (cond_code
== NE
&& COMPARISON_P (cond
))
3796 /* Simplify the alternative arms; this may collapse the true and
3797 false arms to store-flag values. Be careful to use copy_rtx
3798 here since true_rtx or false_rtx might share RTL with x as a
3799 result of the if_then_else_cond call above. */
3800 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3801 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3803 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3804 is unlikely to be simpler. */
3805 if (general_operand (true_rtx
, VOIDmode
)
3806 && general_operand (false_rtx
, VOIDmode
))
3808 enum rtx_code reversed
;
3810 /* Restarting if we generate a store-flag expression will cause
3811 us to loop. Just drop through in this case. */
3813 /* If the result values are STORE_FLAG_VALUE and zero, we can
3814 just make the comparison operation. */
3815 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3816 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3817 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3818 && ((reversed
= reversed_comparison_code_parts
3819 (cond_code
, cond
, cop1
, NULL
))
3821 x
= gen_binary (reversed
, mode
, cond
, cop1
);
3823 /* Likewise, we can make the negate of a comparison operation
3824 if the result values are - STORE_FLAG_VALUE and zero. */
3825 else if (GET_CODE (true_rtx
) == CONST_INT
3826 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3827 && false_rtx
== const0_rtx
)
3828 x
= simplify_gen_unary (NEG
, mode
,
3829 gen_binary (cond_code
, mode
, cond
,
3832 else if (GET_CODE (false_rtx
) == CONST_INT
3833 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3834 && true_rtx
== const0_rtx
3835 && ((reversed
= reversed_comparison_code_parts
3836 (cond_code
, cond
, cop1
, NULL
))
3838 x
= simplify_gen_unary (NEG
, mode
,
3839 gen_binary (reversed
, mode
,
3843 return gen_rtx_IF_THEN_ELSE (mode
,
3844 gen_binary (cond_code
, VOIDmode
,
3846 true_rtx
, false_rtx
);
3848 code
= GET_CODE (x
);
3849 op0_mode
= VOIDmode
;
3854 /* Try to fold this expression in case we have constants that weren't
3857 switch (GET_RTX_CLASS (code
))
3860 if (op0_mode
== VOIDmode
)
3861 op0_mode
= GET_MODE (XEXP (x
, 0));
3862 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3865 case RTX_COMM_COMPARE
:
3867 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3868 if (cmp_mode
== VOIDmode
)
3870 cmp_mode
= GET_MODE (XEXP (x
, 1));
3871 if (cmp_mode
== VOIDmode
)
3872 cmp_mode
= op0_mode
;
3874 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
3875 XEXP (x
, 0), XEXP (x
, 1));
3878 case RTX_COMM_ARITH
:
3880 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3882 case RTX_BITFIELD_OPS
:
3884 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3885 XEXP (x
, 1), XEXP (x
, 2));
3894 code
= GET_CODE (temp
);
3895 op0_mode
= VOIDmode
;
3896 mode
= GET_MODE (temp
);
3899 /* First see if we can apply the inverse distributive law. */
3900 if (code
== PLUS
|| code
== MINUS
3901 || code
== AND
|| code
== IOR
|| code
== XOR
)
3903 x
= apply_distributive_law (x
);
3904 code
= GET_CODE (x
);
3905 op0_mode
= VOIDmode
;
3908 /* If CODE is an associative operation not otherwise handled, see if we
3909 can associate some operands. This can win if they are constants or
3910 if they are logically related (i.e. (a & b) & a). */
3911 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3912 || code
== AND
|| code
== IOR
|| code
== XOR
3913 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3914 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3915 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3917 if (GET_CODE (XEXP (x
, 0)) == code
)
3919 rtx other
= XEXP (XEXP (x
, 0), 0);
3920 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3921 rtx inner_op1
= XEXP (x
, 1);
3924 /* Make sure we pass the constant operand if any as the second
3925 one if this is a commutative operation. */
3926 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
3928 rtx tem
= inner_op0
;
3929 inner_op0
= inner_op1
;
3932 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3933 : code
== DIV
? MULT
3935 mode
, inner_op0
, inner_op1
);
3937 /* For commutative operations, try the other pair if that one
3939 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
3941 other
= XEXP (XEXP (x
, 0), 1);
3942 inner
= simplify_binary_operation (code
, mode
,
3943 XEXP (XEXP (x
, 0), 0),
3948 return gen_binary (code
, mode
, other
, inner
);
3952 /* A little bit of algebraic simplification here. */
3956 /* Ensure that our address has any ASHIFTs converted to MULT in case
3957 address-recognizing predicates are called later. */
3958 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3959 SUBST (XEXP (x
, 0), temp
);
3963 if (op0_mode
== VOIDmode
)
3964 op0_mode
= GET_MODE (SUBREG_REG (x
));
3966 /* See if this can be moved to simplify_subreg. */
3967 if (CONSTANT_P (SUBREG_REG (x
))
3968 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3969 /* Don't call gen_lowpart if the inner mode
3970 is VOIDmode and we cannot simplify it, as SUBREG without
3971 inner mode is invalid. */
3972 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3973 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3974 return gen_lowpart (mode
, SUBREG_REG (x
));
3976 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3980 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3986 /* Don't change the mode of the MEM if that would change the meaning
3988 if (MEM_P (SUBREG_REG (x
))
3989 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3990 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3991 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3993 /* Note that we cannot do any narrowing for non-constants since
3994 we might have been counting on using the fact that some bits were
3995 zero. We now do this in the SET. */
4000 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4001 && subreg_lowpart_p (XEXP (x
, 0))
4002 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
4003 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
4004 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
4005 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
4007 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
4009 x
= gen_rtx_ROTATE (inner_mode
,
4010 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
4012 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
4013 return gen_lowpart (mode
, x
);
4016 /* Apply De Morgan's laws to reduce number of patterns for machines
4017 with negating logical insns (and-not, nand, etc.). If result has
4018 only one NOT, put it first, since that is how the patterns are
4021 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
4023 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
4024 enum machine_mode op_mode
;
4026 op_mode
= GET_MODE (in1
);
4027 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
4029 op_mode
= GET_MODE (in2
);
4030 if (op_mode
== VOIDmode
)
4032 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
4034 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
4037 in2
= in1
; in1
= tem
;
4040 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
4046 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4047 if (GET_CODE (XEXP (x
, 0)) == XOR
4048 && XEXP (XEXP (x
, 0), 1) == const1_rtx
4049 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
4050 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
4052 temp
= expand_compound_operation (XEXP (x
, 0));
4054 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4055 replaced by (lshiftrt X C). This will convert
4056 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4058 if (GET_CODE (temp
) == ASHIFTRT
4059 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4060 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4061 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4062 INTVAL (XEXP (temp
, 1)));
4064 /* If X has only a single bit that might be nonzero, say, bit I, convert
4065 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4066 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4067 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4068 or a SUBREG of one since we'd be making the expression more
4069 complex if it was just a register. */
4072 && ! (GET_CODE (temp
) == SUBREG
4073 && REG_P (SUBREG_REG (temp
)))
4074 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4076 rtx temp1
= simplify_shift_const
4077 (NULL_RTX
, ASHIFTRT
, mode
,
4078 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4079 GET_MODE_BITSIZE (mode
) - 1 - i
),
4080 GET_MODE_BITSIZE (mode
) - 1 - i
);
4082 /* If all we did was surround TEMP with the two shifts, we
4083 haven't improved anything, so don't use it. Otherwise,
4084 we are better off with TEMP1. */
4085 if (GET_CODE (temp1
) != ASHIFTRT
4086 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4087 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4093 /* We can't handle truncation to a partial integer mode here
4094 because we don't know the real bitsize of the partial
4096 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4099 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4100 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4101 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4103 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4104 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4106 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4107 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4108 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4109 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4110 return XEXP (XEXP (x
, 0), 0);
4112 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4113 (OP:SI foo:SI) if OP is NEG or ABS. */
4114 if ((GET_CODE (XEXP (x
, 0)) == ABS
4115 || GET_CODE (XEXP (x
, 0)) == NEG
)
4116 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4117 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4118 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4119 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4120 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4122 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4124 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4125 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4126 && subreg_lowpart_p (XEXP (x
, 0)))
4127 return SUBREG_REG (XEXP (x
, 0));
4129 /* If we know that the value is already truncated, we can
4130 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4131 is nonzero for the corresponding modes. But don't do this
4132 for an (LSHIFTRT (MULT ...)) since this will cause problems
4133 with the umulXi3_highpart patterns. */
4134 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4135 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4136 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4137 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
4138 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4139 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4140 return gen_lowpart (mode
, XEXP (x
, 0));
4142 /* A truncate of a comparison can be replaced with a subreg if
4143 STORE_FLAG_VALUE permits. This is like the previous test,
4144 but it works even if the comparison is done in a mode larger
4145 than HOST_BITS_PER_WIDE_INT. */
4146 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4147 && COMPARISON_P (XEXP (x
, 0))
4148 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4149 return gen_lowpart (mode
, XEXP (x
, 0));
4151 /* Similarly, a truncate of a register whose value is a
4152 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4154 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4155 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4156 && (temp
= get_last_value (XEXP (x
, 0)))
4157 && COMPARISON_P (temp
))
4158 return gen_lowpart (mode
, XEXP (x
, 0));
4162 case FLOAT_TRUNCATE
:
4163 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4164 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4165 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4166 return XEXP (XEXP (x
, 0), 0);
4168 /* (float_truncate:SF (float_truncate:DF foo:XF))
4169 = (float_truncate:SF foo:XF).
4170 This may eliminate double rounding, so it is unsafe.
4172 (float_truncate:SF (float_extend:XF foo:DF))
4173 = (float_truncate:SF foo:DF).
4175 (float_truncate:DF (float_extend:XF foo:SF))
4176 = (float_extend:SF foo:DF). */
4177 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4178 && flag_unsafe_math_optimizations
)
4179 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4180 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4182 > GET_MODE_SIZE (mode
)
4183 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4185 XEXP (XEXP (x
, 0), 0), mode
);
4187 /* (float_truncate (float x)) is (float x) */
4188 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4189 && (flag_unsafe_math_optimizations
4190 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4191 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4192 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4193 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4194 return simplify_gen_unary (FLOAT
, mode
,
4195 XEXP (XEXP (x
, 0), 0),
4196 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4198 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4199 (OP:SF foo:SF) if OP is NEG or ABS. */
4200 if ((GET_CODE (XEXP (x
, 0)) == ABS
4201 || GET_CODE (XEXP (x
, 0)) == NEG
)
4202 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4203 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4204 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4205 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4207 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4208 is (float_truncate:SF x). */
4209 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4210 && subreg_lowpart_p (XEXP (x
, 0))
4211 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4212 return SUBREG_REG (XEXP (x
, 0));
4215 /* (float_extend (float_extend x)) is (float_extend x)
4217 (float_extend (float x)) is (float x) assuming that double
4218 rounding can't happen.
4220 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4221 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4222 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4223 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4224 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4225 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4226 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4227 XEXP (XEXP (x
, 0), 0),
4228 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4233 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4234 using cc0, in which case we want to leave it as a COMPARE
4235 so we can distinguish it from a register-register-copy. */
4236 if (XEXP (x
, 1) == const0_rtx
)
4239 /* x - 0 is the same as x unless x's mode has signed zeros and
4240 allows rounding towards -infinity. Under those conditions,
4242 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4243 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4244 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4250 /* (const (const X)) can become (const X). Do it this way rather than
4251 returning the inner CONST since CONST can be shared with a
4253 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4254 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4259 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4260 can add in an offset. find_split_point will split this address up
4261 again if it doesn't match. */
4262 if (GET_CODE (XEXP (x
, 0)) == HIGH
4263 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4269 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4271 if (GET_CODE (XEXP (x
, 0)) == MULT
4272 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4276 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4277 in2
= XEXP (XEXP (x
, 0), 1);
4278 return gen_binary (MINUS
, mode
, XEXP (x
, 1),
4279 gen_binary (MULT
, mode
, in1
, in2
));
4282 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4283 outermost. That's because that's the way indexed addresses are
4284 supposed to appear. This code used to check many more cases, but
4285 they are now checked elsewhere. */
4286 if (GET_CODE (XEXP (x
, 0)) == PLUS
4287 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4288 return gen_binary (PLUS
, mode
,
4289 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4291 XEXP (XEXP (x
, 0), 1));
4293 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4294 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4295 bit-field and can be replaced by either a sign_extend or a
4296 sign_extract. The `and' may be a zero_extend and the two
4297 <c>, -<c> constants may be reversed. */
4298 if (GET_CODE (XEXP (x
, 0)) == XOR
4299 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4300 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4301 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4302 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4303 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4304 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4305 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4306 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4307 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4308 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4309 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4310 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4311 == (unsigned int) i
+ 1))))
4312 return simplify_shift_const
4313 (NULL_RTX
, ASHIFTRT
, mode
,
4314 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4315 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4316 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4317 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4319 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4320 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4321 is 1. This produces better code than the alternative immediately
4323 if (COMPARISON_P (XEXP (x
, 0))
4324 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4325 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4326 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4327 XEXP (XEXP (x
, 0), 0),
4328 XEXP (XEXP (x
, 0), 1))))
4330 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4332 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4333 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4334 the bitsize of the mode - 1. This allows simplification of
4335 "a = (b & 8) == 0;" */
4336 if (XEXP (x
, 1) == constm1_rtx
4337 && !REG_P (XEXP (x
, 0))
4338 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4339 && REG_P (SUBREG_REG (XEXP (x
, 0))))
4340 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4341 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4342 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4343 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4344 GET_MODE_BITSIZE (mode
) - 1),
4345 GET_MODE_BITSIZE (mode
) - 1);
4347 /* If we are adding two things that have no bits in common, convert
4348 the addition into an IOR. This will often be further simplified,
4349 for example in cases like ((a & 1) + (a & 2)), which can
4352 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4353 && (nonzero_bits (XEXP (x
, 0), mode
)
4354 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4356 /* Try to simplify the expression further. */
4357 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4358 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
4360 /* If we could, great. If not, do not go ahead with the IOR
4361 replacement, since PLUS appears in many special purpose
4362 address arithmetic instructions. */
4363 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4369 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4370 by reversing the comparison code if valid. */
4371 if (STORE_FLAG_VALUE
== 1
4372 && XEXP (x
, 0) == const1_rtx
4373 && COMPARISON_P (XEXP (x
, 1))
4374 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4375 XEXP (XEXP (x
, 1), 0),
4376 XEXP (XEXP (x
, 1), 1))))
4379 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4380 (and <foo> (const_int pow2-1)) */
4381 if (GET_CODE (XEXP (x
, 1)) == AND
4382 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4383 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4384 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4385 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4386 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4388 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4390 if (GET_CODE (XEXP (x
, 1)) == MULT
4391 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4395 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4396 in2
= XEXP (XEXP (x
, 1), 1);
4397 return gen_binary (PLUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4401 /* Canonicalize (minus (neg A) (mult B C)) to
4402 (minus (mult (neg B) C) A). */
4403 if (GET_CODE (XEXP (x
, 1)) == MULT
4404 && GET_CODE (XEXP (x
, 0)) == NEG
)
4408 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4409 in2
= XEXP (XEXP (x
, 1), 1);
4410 return gen_binary (MINUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4411 XEXP (XEXP (x
, 0), 0));
4414 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4416 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4417 return gen_binary (MINUS
, mode
,
4418 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4419 XEXP (XEXP (x
, 1), 0)),
4420 XEXP (XEXP (x
, 1), 1));
4424 /* If we have (mult (plus A B) C), apply the distributive law and then
4425 the inverse distributive law to see if things simplify. This
4426 occurs mostly in addresses, often when unrolling loops. */
4428 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4430 x
= apply_distributive_law
4431 (gen_binary (PLUS
, mode
,
4432 gen_binary (MULT
, mode
,
4433 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4434 gen_binary (MULT
, mode
,
4435 XEXP (XEXP (x
, 0), 1),
4436 copy_rtx (XEXP (x
, 1)))));
4438 if (GET_CODE (x
) != MULT
)
4441 /* Try simplify a*(b/c) as (a*b)/c. */
4442 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4443 && GET_CODE (XEXP (x
, 0)) == DIV
)
4445 rtx tem
= simplify_binary_operation (MULT
, mode
,
4446 XEXP (XEXP (x
, 0), 0),
4449 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4454 /* If this is a divide by a power of two, treat it as a shift if
4455 its first operand is a shift. */
4456 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4457 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4458 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4459 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4460 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4461 || GET_CODE (XEXP (x
, 0)) == ROTATE
4462 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4463 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4467 case GT
: case GTU
: case GE
: case GEU
:
4468 case LT
: case LTU
: case LE
: case LEU
:
4469 case UNEQ
: case LTGT
:
4470 case UNGT
: case UNGE
:
4471 case UNLT
: case UNLE
:
4472 case UNORDERED
: case ORDERED
:
4473 /* If the first operand is a condition code, we can't do anything
4475 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4476 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4477 && ! CC0_P (XEXP (x
, 0))))
4479 rtx op0
= XEXP (x
, 0);
4480 rtx op1
= XEXP (x
, 1);
4481 enum rtx_code new_code
;
4483 if (GET_CODE (op0
) == COMPARE
)
4484 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4486 /* Simplify our comparison, if possible. */
4487 new_code
= simplify_comparison (code
, &op0
, &op1
);
4489 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4490 if only the low-order bit is possibly nonzero in X (such as when
4491 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4492 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4493 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4496 Remove any ZERO_EXTRACT we made when thinking this was a
4497 comparison. It may now be simpler to use, e.g., an AND. If a
4498 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4499 the call to make_compound_operation in the SET case. */
4501 if (STORE_FLAG_VALUE
== 1
4502 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4503 && op1
== const0_rtx
4504 && mode
== GET_MODE (op0
)
4505 && nonzero_bits (op0
, mode
) == 1)
4506 return gen_lowpart (mode
,
4507 expand_compound_operation (op0
));
4509 else if (STORE_FLAG_VALUE
== 1
4510 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4511 && op1
== const0_rtx
4512 && mode
== GET_MODE (op0
)
4513 && (num_sign_bit_copies (op0
, mode
)
4514 == GET_MODE_BITSIZE (mode
)))
4516 op0
= expand_compound_operation (op0
);
4517 return simplify_gen_unary (NEG
, mode
,
4518 gen_lowpart (mode
, op0
),
4522 else if (STORE_FLAG_VALUE
== 1
4523 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4524 && op1
== const0_rtx
4525 && mode
== GET_MODE (op0
)
4526 && nonzero_bits (op0
, mode
) == 1)
4528 op0
= expand_compound_operation (op0
);
4529 return gen_binary (XOR
, mode
,
4530 gen_lowpart (mode
, op0
),
4534 else if (STORE_FLAG_VALUE
== 1
4535 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4536 && op1
== const0_rtx
4537 && mode
== GET_MODE (op0
)
4538 && (num_sign_bit_copies (op0
, mode
)
4539 == GET_MODE_BITSIZE (mode
)))
4541 op0
= expand_compound_operation (op0
);
4542 return plus_constant (gen_lowpart (mode
, op0
), 1);
4545 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4547 if (STORE_FLAG_VALUE
== -1
4548 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4549 && op1
== const0_rtx
4550 && (num_sign_bit_copies (op0
, mode
)
4551 == GET_MODE_BITSIZE (mode
)))
4552 return gen_lowpart (mode
,
4553 expand_compound_operation (op0
));
4555 else if (STORE_FLAG_VALUE
== -1
4556 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4557 && op1
== const0_rtx
4558 && mode
== GET_MODE (op0
)
4559 && nonzero_bits (op0
, mode
) == 1)
4561 op0
= expand_compound_operation (op0
);
4562 return simplify_gen_unary (NEG
, mode
,
4563 gen_lowpart (mode
, op0
),
4567 else if (STORE_FLAG_VALUE
== -1
4568 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4569 && op1
== const0_rtx
4570 && mode
== GET_MODE (op0
)
4571 && (num_sign_bit_copies (op0
, mode
)
4572 == GET_MODE_BITSIZE (mode
)))
4574 op0
= expand_compound_operation (op0
);
4575 return simplify_gen_unary (NOT
, mode
,
4576 gen_lowpart (mode
, op0
),
4580 /* If X is 0/1, (eq X 0) is X-1. */
4581 else if (STORE_FLAG_VALUE
== -1
4582 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4583 && op1
== const0_rtx
4584 && mode
== GET_MODE (op0
)
4585 && nonzero_bits (op0
, mode
) == 1)
4587 op0
= expand_compound_operation (op0
);
4588 return plus_constant (gen_lowpart (mode
, op0
), -1);
4591 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4592 one bit that might be nonzero, we can convert (ne x 0) to
4593 (ashift x c) where C puts the bit in the sign bit. Remove any
4594 AND with STORE_FLAG_VALUE when we are done, since we are only
4595 going to test the sign bit. */
4596 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4597 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4598 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4599 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4600 && op1
== const0_rtx
4601 && mode
== GET_MODE (op0
)
4602 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4604 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4605 expand_compound_operation (op0
),
4606 GET_MODE_BITSIZE (mode
) - 1 - i
);
4607 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4613 /* If the code changed, return a whole new comparison. */
4614 if (new_code
!= code
)
4615 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4617 /* Otherwise, keep this operation, but maybe change its operands.
4618 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4619 SUBST (XEXP (x
, 0), op0
);
4620 SUBST (XEXP (x
, 1), op1
);
4625 return simplify_if_then_else (x
);
4631 /* If we are processing SET_DEST, we are done. */
4635 return expand_compound_operation (x
);
4638 return simplify_set (x
);
4643 return simplify_logical (x
);
4646 /* (abs (neg <foo>)) -> (abs <foo>) */
4647 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4648 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4650 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4652 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4655 /* If operand is something known to be positive, ignore the ABS. */
4656 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4657 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4658 <= HOST_BITS_PER_WIDE_INT
)
4659 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4660 & ((HOST_WIDE_INT
) 1
4661 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4665 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4666 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4667 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4672 /* (ffs (*_extend <X>)) = (ffs <X>) */
4673 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4674 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4675 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4680 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4681 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4682 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4686 /* (float (sign_extend <X>)) = (float <X>). */
4687 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4688 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4696 /* If this is a shift by a constant amount, simplify it. */
4697 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4698 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4699 INTVAL (XEXP (x
, 1)));
4701 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
4703 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4705 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4712 rtx op0
= XEXP (x
, 0);
4713 rtx op1
= XEXP (x
, 1);
4716 gcc_assert (GET_CODE (op1
) == PARALLEL
);
4717 len
= XVECLEN (op1
, 0);
4719 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4720 && GET_CODE (op0
) == VEC_CONCAT
)
4722 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4724 /* Try to find the element in the VEC_CONCAT. */
4727 if (GET_MODE (op0
) == GET_MODE (x
))
4729 if (GET_CODE (op0
) == VEC_CONCAT
)
4731 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4732 if (op0_size
< offset
)
4733 op0
= XEXP (op0
, 0);
4737 op0
= XEXP (op0
, 1);
4755 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4758 simplify_if_then_else (rtx x
)
4760 enum machine_mode mode
= GET_MODE (x
);
4761 rtx cond
= XEXP (x
, 0);
4762 rtx true_rtx
= XEXP (x
, 1);
4763 rtx false_rtx
= XEXP (x
, 2);
4764 enum rtx_code true_code
= GET_CODE (cond
);
4765 int comparison_p
= COMPARISON_P (cond
);
4768 enum rtx_code false_code
;
4771 /* Simplify storing of the truth value. */
4772 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4773 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4775 /* Also when the truth value has to be reversed. */
4777 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4778 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4782 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4783 in it is being compared against certain values. Get the true and false
4784 comparisons and see if that says anything about the value of each arm. */
4787 && ((false_code
= combine_reversed_comparison_code (cond
))
4789 && REG_P (XEXP (cond
, 0)))
4792 rtx from
= XEXP (cond
, 0);
4793 rtx true_val
= XEXP (cond
, 1);
4794 rtx false_val
= true_val
;
4797 /* If FALSE_CODE is EQ, swap the codes and arms. */
4799 if (false_code
== EQ
)
4801 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4802 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4805 /* If we are comparing against zero and the expression being tested has
4806 only a single bit that might be nonzero, that is its value when it is
4807 not equal to zero. Similarly if it is known to be -1 or 0. */
4809 if (true_code
== EQ
&& true_val
== const0_rtx
4810 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4811 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4812 else if (true_code
== EQ
&& true_val
== const0_rtx
4813 && (num_sign_bit_copies (from
, GET_MODE (from
))
4814 == GET_MODE_BITSIZE (GET_MODE (from
))))
4815 false_code
= EQ
, false_val
= constm1_rtx
;
4817 /* Now simplify an arm if we know the value of the register in the
4818 branch and it is used in the arm. Be careful due to the potential
4819 of locally-shared RTL. */
4821 if (reg_mentioned_p (from
, true_rtx
))
4822 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4824 pc_rtx
, pc_rtx
, 0, 0);
4825 if (reg_mentioned_p (from
, false_rtx
))
4826 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4828 pc_rtx
, pc_rtx
, 0, 0);
4830 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4831 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4833 true_rtx
= XEXP (x
, 1);
4834 false_rtx
= XEXP (x
, 2);
4835 true_code
= GET_CODE (cond
);
4838 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4839 reversed, do so to avoid needing two sets of patterns for
4840 subtract-and-branch insns. Similarly if we have a constant in the true
4841 arm, the false arm is the same as the first operand of the comparison, or
4842 the false arm is more complicated than the true arm. */
4845 && combine_reversed_comparison_code (cond
) != UNKNOWN
4846 && (true_rtx
== pc_rtx
4847 || (CONSTANT_P (true_rtx
)
4848 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4849 || true_rtx
== const0_rtx
4850 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
4851 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
4852 && !OBJECT_P (false_rtx
))
4853 || reg_mentioned_p (true_rtx
, false_rtx
)
4854 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4856 true_code
= reversed_comparison_code (cond
, NULL
);
4858 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4861 SUBST (XEXP (x
, 1), false_rtx
);
4862 SUBST (XEXP (x
, 2), true_rtx
);
4864 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4867 /* It is possible that the conditional has been simplified out. */
4868 true_code
= GET_CODE (cond
);
4869 comparison_p
= COMPARISON_P (cond
);
4872 /* If the two arms are identical, we don't need the comparison. */
4874 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4877 /* Convert a == b ? b : a to "a". */
4878 if (true_code
== EQ
&& ! side_effects_p (cond
)
4879 && !HONOR_NANS (mode
)
4880 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4881 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4883 else if (true_code
== NE
&& ! side_effects_p (cond
)
4884 && !HONOR_NANS (mode
)
4885 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4886 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4889 /* Look for cases where we have (abs x) or (neg (abs X)). */
4891 if (GET_MODE_CLASS (mode
) == MODE_INT
4892 && GET_CODE (false_rtx
) == NEG
4893 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4895 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4896 && ! side_effects_p (true_rtx
))
4901 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4905 simplify_gen_unary (NEG
, mode
,
4906 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4912 /* Look for MIN or MAX. */
4914 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4916 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4917 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4918 && ! side_effects_p (cond
))
4923 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4926 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4929 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4932 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4937 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4938 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4939 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4940 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4941 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4942 neither 1 or -1, but it isn't worth checking for. */
4944 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4946 && GET_MODE_CLASS (mode
) == MODE_INT
4947 && ! side_effects_p (x
))
4949 rtx t
= make_compound_operation (true_rtx
, SET
);
4950 rtx f
= make_compound_operation (false_rtx
, SET
);
4951 rtx cond_op0
= XEXP (cond
, 0);
4952 rtx cond_op1
= XEXP (cond
, 1);
4953 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
4954 enum machine_mode m
= mode
;
4955 rtx z
= 0, c1
= NULL_RTX
;
4957 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4958 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4959 || GET_CODE (t
) == ASHIFT
4960 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4961 && rtx_equal_p (XEXP (t
, 0), f
))
4962 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4964 /* If an identity-zero op is commutative, check whether there
4965 would be a match if we swapped the operands. */
4966 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4967 || GET_CODE (t
) == XOR
)
4968 && rtx_equal_p (XEXP (t
, 1), f
))
4969 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4970 else if (GET_CODE (t
) == SIGN_EXTEND
4971 && (GET_CODE (XEXP (t
, 0)) == PLUS
4972 || GET_CODE (XEXP (t
, 0)) == MINUS
4973 || GET_CODE (XEXP (t
, 0)) == IOR
4974 || GET_CODE (XEXP (t
, 0)) == XOR
4975 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4976 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4977 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4978 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4979 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4980 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4981 && (num_sign_bit_copies (f
, GET_MODE (f
))
4983 (GET_MODE_BITSIZE (mode
)
4984 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4986 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4987 extend_op
= SIGN_EXTEND
;
4988 m
= GET_MODE (XEXP (t
, 0));
4990 else if (GET_CODE (t
) == SIGN_EXTEND
4991 && (GET_CODE (XEXP (t
, 0)) == PLUS
4992 || GET_CODE (XEXP (t
, 0)) == IOR
4993 || GET_CODE (XEXP (t
, 0)) == XOR
)
4994 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4995 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4996 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4997 && (num_sign_bit_copies (f
, GET_MODE (f
))
4999 (GET_MODE_BITSIZE (mode
)
5000 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
5002 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5003 extend_op
= SIGN_EXTEND
;
5004 m
= GET_MODE (XEXP (t
, 0));
5006 else if (GET_CODE (t
) == ZERO_EXTEND
5007 && (GET_CODE (XEXP (t
, 0)) == PLUS
5008 || GET_CODE (XEXP (t
, 0)) == MINUS
5009 || GET_CODE (XEXP (t
, 0)) == IOR
5010 || GET_CODE (XEXP (t
, 0)) == XOR
5011 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5012 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5013 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5014 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5015 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5016 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5017 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5018 && ((nonzero_bits (f
, GET_MODE (f
))
5019 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
5022 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5023 extend_op
= ZERO_EXTEND
;
5024 m
= GET_MODE (XEXP (t
, 0));
5026 else if (GET_CODE (t
) == ZERO_EXTEND
5027 && (GET_CODE (XEXP (t
, 0)) == PLUS
5028 || GET_CODE (XEXP (t
, 0)) == IOR
5029 || GET_CODE (XEXP (t
, 0)) == XOR
)
5030 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5031 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5032 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5033 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5034 && ((nonzero_bits (f
, GET_MODE (f
))
5035 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
5038 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5039 extend_op
= ZERO_EXTEND
;
5040 m
= GET_MODE (XEXP (t
, 0));
5045 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
5046 pc_rtx
, pc_rtx
, 0, 0);
5047 temp
= gen_binary (MULT
, m
, temp
,
5048 gen_binary (MULT
, m
, c1
, const_true_rtx
));
5049 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
5050 temp
= gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
5052 if (extend_op
!= UNKNOWN
)
5053 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
5059 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5060 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5061 negation of a single bit, we can convert this operation to a shift. We
5062 can actually do this more generally, but it doesn't seem worth it. */
5064 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5065 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5066 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
5067 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
5068 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
5069 == GET_MODE_BITSIZE (mode
))
5070 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
5072 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5073 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
5075 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5076 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5077 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5078 && GET_MODE (XEXP (cond
, 0)) == mode
5079 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
5080 == nonzero_bits (XEXP (cond
, 0), mode
)
5081 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
5082 return XEXP (cond
, 0);
5087 /* Simplify X, a SET expression. Return the new expression. */
5090 simplify_set (rtx x
)
5092 rtx src
= SET_SRC (x
);
5093 rtx dest
= SET_DEST (x
);
5094 enum machine_mode mode
5095 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5099 /* (set (pc) (return)) gets written as (return). */
5100 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5103 /* Now that we know for sure which bits of SRC we are using, see if we can
5104 simplify the expression for the object knowing that we only need the
5107 if (GET_MODE_CLASS (mode
) == MODE_INT
5108 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5110 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
5111 SUBST (SET_SRC (x
), src
);
5114 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5115 the comparison result and try to simplify it unless we already have used
5116 undobuf.other_insn. */
5117 if ((GET_MODE_CLASS (mode
) == MODE_CC
5118 || GET_CODE (src
) == COMPARE
5120 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5121 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5122 && COMPARISON_P (*cc_use
)
5123 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5125 enum rtx_code old_code
= GET_CODE (*cc_use
);
5126 enum rtx_code new_code
;
5128 int other_changed
= 0;
5129 enum machine_mode compare_mode
= GET_MODE (dest
);
5131 if (GET_CODE (src
) == COMPARE
)
5132 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5134 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
5136 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
5139 new_code
= old_code
;
5140 else if (!CONSTANT_P (tmp
))
5142 new_code
= GET_CODE (tmp
);
5143 op0
= XEXP (tmp
, 0);
5144 op1
= XEXP (tmp
, 1);
5148 rtx pat
= PATTERN (other_insn
);
5149 undobuf
.other_insn
= other_insn
;
5150 SUBST (*cc_use
, tmp
);
5152 /* Attempt to simplify CC user. */
5153 if (GET_CODE (pat
) == SET
)
5155 rtx
new = simplify_rtx (SET_SRC (pat
));
5156 if (new != NULL_RTX
)
5157 SUBST (SET_SRC (pat
), new);
5160 /* Convert X into a no-op move. */
5161 SUBST (SET_DEST (x
), pc_rtx
);
5162 SUBST (SET_SRC (x
), pc_rtx
);
5166 /* Simplify our comparison, if possible. */
5167 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
5169 #ifdef SELECT_CC_MODE
5170 /* If this machine has CC modes other than CCmode, check to see if we
5171 need to use a different CC mode here. */
5172 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5173 compare_mode
= GET_MODE (op0
);
5175 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5178 /* If the mode changed, we have to change SET_DEST, the mode in the
5179 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5180 a hard register, just build new versions with the proper mode. If it
5181 is a pseudo, we lose unless it is only time we set the pseudo, in
5182 which case we can safely change its mode. */
5183 if (compare_mode
!= GET_MODE (dest
))
5185 unsigned int regno
= REGNO (dest
);
5186 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5188 if (regno
< FIRST_PSEUDO_REGISTER
5189 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5191 if (regno
>= FIRST_PSEUDO_REGISTER
)
5192 SUBST (regno_reg_rtx
[regno
], new_dest
);
5194 SUBST (SET_DEST (x
), new_dest
);
5195 SUBST (XEXP (*cc_use
, 0), new_dest
);
5202 #endif /* SELECT_CC_MODE */
5204 /* If the code changed, we have to build a new comparison in
5205 undobuf.other_insn. */
5206 if (new_code
!= old_code
)
5208 int other_changed_previously
= other_changed
;
5209 unsigned HOST_WIDE_INT mask
;
5211 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5215 /* If the only change we made was to change an EQ into an NE or
5216 vice versa, OP0 has only one bit that might be nonzero, and OP1
5217 is zero, check if changing the user of the condition code will
5218 produce a valid insn. If it won't, we can keep the original code
5219 in that insn by surrounding our operation with an XOR. */
5221 if (((old_code
== NE
&& new_code
== EQ
)
5222 || (old_code
== EQ
&& new_code
== NE
))
5223 && ! other_changed_previously
&& op1
== const0_rtx
5224 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5225 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5227 rtx pat
= PATTERN (other_insn
), note
= 0;
5229 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5230 && ! check_asm_operands (pat
)))
5232 PUT_CODE (*cc_use
, old_code
);
5235 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5241 undobuf
.other_insn
= other_insn
;
5244 /* If we are now comparing against zero, change our source if
5245 needed. If we do not use cc0, we always have a COMPARE. */
5246 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5248 SUBST (SET_SRC (x
), op0
);
5254 /* Otherwise, if we didn't previously have a COMPARE in the
5255 correct mode, we need one. */
5256 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5258 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5263 /* Otherwise, update the COMPARE if needed. */
5264 SUBST (XEXP (src
, 0), op0
);
5265 SUBST (XEXP (src
, 1), op1
);
5270 /* Get SET_SRC in a form where we have placed back any
5271 compound expressions. Then do the checks below. */
5272 src
= make_compound_operation (src
, SET
);
5273 SUBST (SET_SRC (x
), src
);
5276 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5277 and X being a REG or (subreg (reg)), we may be able to convert this to
5278 (set (subreg:m2 x) (op)).
5280 We can always do this if M1 is narrower than M2 because that means that
5281 we only care about the low bits of the result.
5283 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5284 perform a narrower operation than requested since the high-order bits will
5285 be undefined. On machine where it is defined, this transformation is safe
5286 as long as M1 and M2 have the same number of words. */
5288 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5289 && !OBJECT_P (SUBREG_REG (src
))
5290 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5292 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5293 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5294 #ifndef WORD_REGISTER_OPERATIONS
5295 && (GET_MODE_SIZE (GET_MODE (src
))
5296 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5298 #ifdef CANNOT_CHANGE_MODE_CLASS
5299 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
5300 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5301 GET_MODE (SUBREG_REG (src
)),
5305 || (GET_CODE (dest
) == SUBREG
5306 && REG_P (SUBREG_REG (dest
)))))
5308 SUBST (SET_DEST (x
),
5309 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5311 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5313 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5317 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5320 && GET_CODE (src
) == SUBREG
5321 && subreg_lowpart_p (src
)
5322 && (GET_MODE_BITSIZE (GET_MODE (src
))
5323 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5325 rtx inner
= SUBREG_REG (src
);
5326 enum machine_mode inner_mode
= GET_MODE (inner
);
5328 /* Here we make sure that we don't have a sign bit on. */
5329 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5330 && (nonzero_bits (inner
, inner_mode
)
5331 < ((unsigned HOST_WIDE_INT
) 1
5332 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5334 SUBST (SET_SRC (x
), inner
);
5340 #ifdef LOAD_EXTEND_OP
5341 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5342 would require a paradoxical subreg. Replace the subreg with a
5343 zero_extend to avoid the reload that would otherwise be required. */
5345 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5346 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
5347 && SUBREG_BYTE (src
) == 0
5348 && (GET_MODE_SIZE (GET_MODE (src
))
5349 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5350 && MEM_P (SUBREG_REG (src
)))
5353 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5354 GET_MODE (src
), SUBREG_REG (src
)));
5360 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5361 are comparing an item known to be 0 or -1 against 0, use a logical
5362 operation instead. Check for one of the arms being an IOR of the other
5363 arm with some value. We compute three terms to be IOR'ed together. In
5364 practice, at most two will be nonzero. Then we do the IOR's. */
5366 if (GET_CODE (dest
) != PC
5367 && GET_CODE (src
) == IF_THEN_ELSE
5368 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5369 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5370 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5371 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5372 #ifdef HAVE_conditional_move
5373 && ! can_conditionally_move_p (GET_MODE (src
))
5375 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5376 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5377 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5378 && ! side_effects_p (src
))
5380 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5381 ? XEXP (src
, 1) : XEXP (src
, 2));
5382 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5383 ? XEXP (src
, 2) : XEXP (src
, 1));
5384 rtx term1
= const0_rtx
, term2
, term3
;
5386 if (GET_CODE (true_rtx
) == IOR
5387 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5388 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5389 else if (GET_CODE (true_rtx
) == IOR
5390 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5391 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5392 else if (GET_CODE (false_rtx
) == IOR
5393 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5394 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5395 else if (GET_CODE (false_rtx
) == IOR
5396 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5397 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5399 term2
= gen_binary (AND
, GET_MODE (src
),
5400 XEXP (XEXP (src
, 0), 0), true_rtx
);
5401 term3
= gen_binary (AND
, GET_MODE (src
),
5402 simplify_gen_unary (NOT
, GET_MODE (src
),
5403 XEXP (XEXP (src
, 0), 0),
5408 gen_binary (IOR
, GET_MODE (src
),
5409 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5415 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5416 whole thing fail. */
5417 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5419 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5422 /* Convert this into a field assignment operation, if possible. */
5423 return make_field_assignment (x
);
5426 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5430 simplify_logical (rtx x
)
5432 enum machine_mode mode
= GET_MODE (x
);
5433 rtx op0
= XEXP (x
, 0);
5434 rtx op1
= XEXP (x
, 1);
5437 switch (GET_CODE (x
))
5440 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5441 insn (and may simplify more). */
5442 if (GET_CODE (op0
) == XOR
5443 && rtx_equal_p (XEXP (op0
, 0), op1
)
5444 && ! side_effects_p (op1
))
5445 x
= gen_binary (AND
, mode
,
5446 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5449 if (GET_CODE (op0
) == XOR
5450 && rtx_equal_p (XEXP (op0
, 1), op1
)
5451 && ! side_effects_p (op1
))
5452 x
= gen_binary (AND
, mode
,
5453 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5456 /* Similarly for (~(A ^ B)) & A. */
5457 if (GET_CODE (op0
) == NOT
5458 && GET_CODE (XEXP (op0
, 0)) == XOR
5459 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5460 && ! side_effects_p (op1
))
5461 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5463 if (GET_CODE (op0
) == NOT
5464 && GET_CODE (XEXP (op0
, 0)) == XOR
5465 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5466 && ! side_effects_p (op1
))
5467 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5469 /* We can call simplify_and_const_int only if we don't lose
5470 any (sign) bits when converting INTVAL (op1) to
5471 "unsigned HOST_WIDE_INT". */
5472 if (GET_CODE (op1
) == CONST_INT
5473 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5474 || INTVAL (op1
) > 0))
5476 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5478 /* If we have (ior (and (X C1) C2)) and the next restart would be
5479 the last, simplify this by making C1 as small as possible
5480 and then exit. Only do this if C1 actually changes: for now
5481 this only saves memory but, should this transformation be
5482 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5483 if (GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5484 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5485 && GET_CODE (op1
) == CONST_INT
5486 && (INTVAL (XEXP (op0
, 1)) & INTVAL (op1
)) != 0)
5487 return gen_binary (IOR
, mode
,
5488 gen_binary (AND
, mode
, XEXP (op0
, 0),
5489 GEN_INT (INTVAL (XEXP (op0
, 1))
5490 & ~INTVAL (op1
))), op1
);
5492 if (GET_CODE (x
) != AND
)
5499 /* Convert (A | B) & A to A. */
5500 if (GET_CODE (op0
) == IOR
5501 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5502 || rtx_equal_p (XEXP (op0
, 1), op1
))
5503 && ! side_effects_p (XEXP (op0
, 0))
5504 && ! side_effects_p (XEXP (op0
, 1)))
5507 /* In the following group of tests (and those in case IOR below),
5508 we start with some combination of logical operations and apply
5509 the distributive law followed by the inverse distributive law.
5510 Most of the time, this results in no change. However, if some of
5511 the operands are the same or inverses of each other, simplifications
5514 For example, (and (ior A B) (not B)) can occur as the result of
5515 expanding a bit field assignment. When we apply the distributive
5516 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5517 which then simplifies to (and (A (not B))).
5519 If we have (and (ior A B) C), apply the distributive law and then
5520 the inverse distributive law to see if things simplify. */
5522 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5524 x
= apply_distributive_law
5525 (gen_binary (GET_CODE (op0
), mode
,
5526 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5527 gen_binary (AND
, mode
, XEXP (op0
, 1),
5529 if (GET_CODE (x
) != AND
)
5533 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5534 return apply_distributive_law
5535 (gen_binary (GET_CODE (op1
), mode
,
5536 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5537 gen_binary (AND
, mode
, XEXP (op1
, 1),
5540 /* Similarly, taking advantage of the fact that
5541 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5543 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5544 return apply_distributive_law
5545 (gen_binary (XOR
, mode
,
5546 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5547 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5550 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5551 return apply_distributive_law
5552 (gen_binary (XOR
, mode
,
5553 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5554 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5558 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5559 if (GET_CODE (op1
) == CONST_INT
5560 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5561 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5564 /* Convert (A & B) | A to A. */
5565 if (GET_CODE (op0
) == AND
5566 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5567 || rtx_equal_p (XEXP (op0
, 1), op1
))
5568 && ! side_effects_p (XEXP (op0
, 0))
5569 && ! side_effects_p (XEXP (op0
, 1)))
5572 /* If we have (ior (and A B) C), apply the distributive law and then
5573 the inverse distributive law to see if things simplify. */
5575 if (GET_CODE (op0
) == AND
)
5577 x
= apply_distributive_law
5578 (gen_binary (AND
, mode
,
5579 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5580 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5583 if (GET_CODE (x
) != IOR
)
5587 if (GET_CODE (op1
) == AND
)
5589 x
= apply_distributive_law
5590 (gen_binary (AND
, mode
,
5591 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5592 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5595 if (GET_CODE (x
) != IOR
)
5599 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5600 mode size to (rotate A CX). */
5602 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5603 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5604 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5605 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5606 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5607 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5608 == GET_MODE_BITSIZE (mode
)))
5609 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5610 (GET_CODE (op0
) == ASHIFT
5611 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5613 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5614 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5615 does not affect any of the bits in OP1, it can really be done
5616 as a PLUS and we can associate. We do this by seeing if OP1
5617 can be safely shifted left C bits. */
5618 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5619 && GET_CODE (XEXP (op0
, 0)) == PLUS
5620 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5621 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5622 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5624 int count
= INTVAL (XEXP (op0
, 1));
5625 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5627 if (mask
>> count
== INTVAL (op1
)
5628 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5630 SUBST (XEXP (XEXP (op0
, 0), 1),
5631 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5638 /* If we are XORing two things that have no bits in common,
5639 convert them into an IOR. This helps to detect rotation encoded
5640 using those methods and possibly other simplifications. */
5642 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5643 && (nonzero_bits (op0
, mode
)
5644 & nonzero_bits (op1
, mode
)) == 0)
5645 return (gen_binary (IOR
, mode
, op0
, op1
));
5647 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5648 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5651 int num_negated
= 0;
5653 if (GET_CODE (op0
) == NOT
)
5654 num_negated
++, op0
= XEXP (op0
, 0);
5655 if (GET_CODE (op1
) == NOT
)
5656 num_negated
++, op1
= XEXP (op1
, 0);
5658 if (num_negated
== 2)
5660 SUBST (XEXP (x
, 0), op0
);
5661 SUBST (XEXP (x
, 1), op1
);
5663 else if (num_negated
== 1)
5665 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5669 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5670 correspond to a machine insn or result in further simplifications
5671 if B is a constant. */
5673 if (GET_CODE (op0
) == AND
5674 && rtx_equal_p (XEXP (op0
, 1), op1
)
5675 && ! side_effects_p (op1
))
5676 return gen_binary (AND
, mode
,
5677 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5680 else if (GET_CODE (op0
) == AND
5681 && rtx_equal_p (XEXP (op0
, 0), op1
)
5682 && ! side_effects_p (op1
))
5683 return gen_binary (AND
, mode
,
5684 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5687 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5688 comparison if STORE_FLAG_VALUE is 1. */
5689 if (STORE_FLAG_VALUE
== 1
5690 && op1
== const1_rtx
5691 && COMPARISON_P (op0
)
5692 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5696 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5697 is (lt foo (const_int 0)), so we can perform the above
5698 simplification if STORE_FLAG_VALUE is 1. */
5700 if (STORE_FLAG_VALUE
== 1
5701 && op1
== const1_rtx
5702 && GET_CODE (op0
) == LSHIFTRT
5703 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5704 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5705 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5707 /* (xor (comparison foo bar) (const_int sign-bit))
5708 when STORE_FLAG_VALUE is the sign bit. */
5709 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5710 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5711 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5712 && op1
== const_true_rtx
5713 && COMPARISON_P (op0
)
5714 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5727 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5728 operations" because they can be replaced with two more basic operations.
5729 ZERO_EXTEND is also considered "compound" because it can be replaced with
5730 an AND operation, which is simpler, though only one operation.
5732 The function expand_compound_operation is called with an rtx expression
5733 and will convert it to the appropriate shifts and AND operations,
5734 simplifying at each stage.
5736 The function make_compound_operation is called to convert an expression
5737 consisting of shifts and ANDs into the equivalent compound expression.
5738 It is the inverse of this function, loosely speaking. */
5741 expand_compound_operation (rtx x
)
5743 unsigned HOST_WIDE_INT pos
= 0, len
;
5745 unsigned int modewidth
;
5748 switch (GET_CODE (x
))
5753 /* We can't necessarily use a const_int for a multiword mode;
5754 it depends on implicitly extending the value.
5755 Since we don't know the right way to extend it,
5756 we can't tell whether the implicit way is right.
5758 Even for a mode that is no wider than a const_int,
5759 we can't win, because we need to sign extend one of its bits through
5760 the rest of it, and we don't know which bit. */
5761 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5764 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5765 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5766 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5767 reloaded. If not for that, MEM's would very rarely be safe.
5769 Reject MODEs bigger than a word, because we might not be able
5770 to reference a two-register group starting with an arbitrary register
5771 (and currently gen_lowpart might crash for a SUBREG). */
5773 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5776 /* Reject MODEs that aren't scalar integers because turning vector
5777 or complex modes into shifts causes problems. */
5779 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5782 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5783 /* If the inner object has VOIDmode (the only way this can happen
5784 is if it is an ASM_OPERANDS), we can't do anything since we don't
5785 know how much masking to do. */
5794 /* ... fall through ... */
5797 /* If the operand is a CLOBBER, just return it. */
5798 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5801 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5802 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5803 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5806 /* Reject MODEs that aren't scalar integers because turning vector
5807 or complex modes into shifts causes problems. */
5809 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5812 len
= INTVAL (XEXP (x
, 1));
5813 pos
= INTVAL (XEXP (x
, 2));
5815 /* If this goes outside the object being extracted, replace the object
5816 with a (use (mem ...)) construct that only combine understands
5817 and is used only for this purpose. */
5818 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5819 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5821 if (BITS_BIG_ENDIAN
)
5822 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5829 /* Convert sign extension to zero extension, if we know that the high
5830 bit is not set, as this is easier to optimize. It will be converted
5831 back to cheaper alternative in make_extraction. */
5832 if (GET_CODE (x
) == SIGN_EXTEND
5833 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5834 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5835 & ~(((unsigned HOST_WIDE_INT
)
5836 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5840 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5841 rtx temp2
= expand_compound_operation (temp
);
5843 /* Make sure this is a profitable operation. */
5844 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5846 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5852 /* We can optimize some special cases of ZERO_EXTEND. */
5853 if (GET_CODE (x
) == ZERO_EXTEND
)
5855 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5856 know that the last value didn't have any inappropriate bits
5858 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5859 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5860 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5861 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5862 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5863 return XEXP (XEXP (x
, 0), 0);
5865 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5866 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5867 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5868 && subreg_lowpart_p (XEXP (x
, 0))
5869 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5870 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5871 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5872 return SUBREG_REG (XEXP (x
, 0));
5874 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5875 is a comparison and STORE_FLAG_VALUE permits. This is like
5876 the first case, but it works even when GET_MODE (x) is larger
5877 than HOST_WIDE_INT. */
5878 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5879 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5880 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
5881 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5882 <= HOST_BITS_PER_WIDE_INT
)
5883 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5884 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5885 return XEXP (XEXP (x
, 0), 0);
5887 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5888 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5889 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5890 && subreg_lowpart_p (XEXP (x
, 0))
5891 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
5892 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5893 <= HOST_BITS_PER_WIDE_INT
)
5894 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5895 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5896 return SUBREG_REG (XEXP (x
, 0));
5900 /* If we reach here, we want to return a pair of shifts. The inner
5901 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5902 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5903 logical depending on the value of UNSIGNEDP.
5905 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5906 converted into an AND of a shift.
5908 We must check for the case where the left shift would have a negative
5909 count. This can happen in a case like (x >> 31) & 255 on machines
5910 that can't shift by a constant. On those machines, we would first
5911 combine the shift with the AND to produce a variable-position
5912 extraction. Then the constant of 31 would be substituted in to produce
5913 a such a position. */
5915 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5916 if (modewidth
+ len
>= pos
)
5917 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5919 simplify_shift_const (NULL_RTX
, ASHIFT
,
5922 modewidth
- pos
- len
),
5925 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5926 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5927 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5930 ((HOST_WIDE_INT
) 1 << len
) - 1);
5932 /* Any other cases we can't handle. */
5935 /* If we couldn't do this for some reason, return the original
5937 if (GET_CODE (tem
) == CLOBBER
)
5943 /* X is a SET which contains an assignment of one object into
5944 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5945 or certain SUBREGS). If possible, convert it into a series of
5948 We half-heartedly support variable positions, but do not at all
5949 support variable lengths. */
5952 expand_field_assignment (rtx x
)
5955 rtx pos
; /* Always counts from low bit. */
5958 enum machine_mode compute_mode
;
5960 /* Loop until we find something we can't simplify. */
5963 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5964 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5966 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5967 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5968 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5970 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5971 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5973 inner
= XEXP (SET_DEST (x
), 0);
5974 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5975 pos
= XEXP (SET_DEST (x
), 2);
5977 /* If the position is constant and spans the width of INNER,
5978 surround INNER with a USE to indicate this. */
5979 if (GET_CODE (pos
) == CONST_INT
5980 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5981 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5983 if (BITS_BIG_ENDIAN
)
5985 if (GET_CODE (pos
) == CONST_INT
)
5986 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5988 else if (GET_CODE (pos
) == MINUS
5989 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5990 && (INTVAL (XEXP (pos
, 1))
5991 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5992 /* If position is ADJUST - X, new position is X. */
5993 pos
= XEXP (pos
, 0);
5995 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5996 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
6002 /* A SUBREG between two modes that occupy the same numbers of words
6003 can be done by moving the SUBREG to the source. */
6004 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6005 /* We need SUBREGs to compute nonzero_bits properly. */
6006 && nonzero_sign_valid
6007 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6008 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6009 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6010 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6012 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6014 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6021 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6022 inner
= SUBREG_REG (inner
);
6024 compute_mode
= GET_MODE (inner
);
6026 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6027 if (! SCALAR_INT_MODE_P (compute_mode
))
6029 enum machine_mode imode
;
6031 /* Don't do anything for vector or complex integral types. */
6032 if (! FLOAT_MODE_P (compute_mode
))
6035 /* Try to find an integral mode to pun with. */
6036 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6037 if (imode
== BLKmode
)
6040 compute_mode
= imode
;
6041 inner
= gen_lowpart (imode
, inner
);
6044 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6045 if (len
< HOST_BITS_PER_WIDE_INT
)
6046 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
6050 /* Now compute the equivalent expression. Make a copy of INNER
6051 for the SET_DEST in case it is a MEM into which we will substitute;
6052 we don't want shared RTL in that case. */
6054 (VOIDmode
, copy_rtx (inner
),
6055 gen_binary (IOR
, compute_mode
,
6056 gen_binary (AND
, compute_mode
,
6057 simplify_gen_unary (NOT
, compute_mode
,
6063 gen_binary (ASHIFT
, compute_mode
,
6064 gen_binary (AND
, compute_mode
,
6066 (compute_mode
, SET_SRC (x
)),
6074 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6075 it is an RTX that represents a variable starting position; otherwise,
6076 POS is the (constant) starting bit position (counted from the LSB).
6078 INNER may be a USE. This will occur when we started with a bitfield
6079 that went outside the boundary of the object in memory, which is
6080 allowed on most machines. To isolate this case, we produce a USE
6081 whose mode is wide enough and surround the MEM with it. The only
6082 code that understands the USE is this routine. If it is not removed,
6083 it will cause the resulting insn not to match.
6085 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6088 IN_DEST is nonzero if this is a reference in the destination of a
6089 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6090 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6093 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6094 ZERO_EXTRACT should be built even for bits starting at bit 0.
6096 MODE is the desired mode of the result (if IN_DEST == 0).
6098 The result is an RTX for the extraction or NULL_RTX if the target
6102 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6103 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6104 int in_dest
, int in_compare
)
6106 /* This mode describes the size of the storage area
6107 to fetch the overall value from. Within that, we
6108 ignore the POS lowest bits, etc. */
6109 enum machine_mode is_mode
= GET_MODE (inner
);
6110 enum machine_mode inner_mode
;
6111 enum machine_mode wanted_inner_mode
= byte_mode
;
6112 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6113 enum machine_mode pos_mode
= word_mode
;
6114 enum machine_mode extraction_mode
= word_mode
;
6115 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6118 rtx orig_pos_rtx
= pos_rtx
;
6119 HOST_WIDE_INT orig_pos
;
6121 /* Get some information about INNER and get the innermost object. */
6122 if (GET_CODE (inner
) == USE
)
6123 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6124 /* We don't need to adjust the position because we set up the USE
6125 to pretend that it was a full-word object. */
6126 spans_byte
= 1, inner
= XEXP (inner
, 0);
6127 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6129 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6130 consider just the QI as the memory to extract from.
6131 The subreg adds or removes high bits; its mode is
6132 irrelevant to the meaning of this extraction,
6133 since POS and LEN count from the lsb. */
6134 if (MEM_P (SUBREG_REG (inner
)))
6135 is_mode
= GET_MODE (SUBREG_REG (inner
));
6136 inner
= SUBREG_REG (inner
);
6138 else if (GET_CODE (inner
) == ASHIFT
6139 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
6140 && pos_rtx
== 0 && pos
== 0
6141 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6143 /* We're extracting the least significant bits of an rtx
6144 (ashift X (const_int C)), where LEN > C. Extract the
6145 least significant (LEN - C) bits of X, giving an rtx
6146 whose mode is MODE, then shift it left C times. */
6147 new = make_extraction (mode
, XEXP (inner
, 0),
6148 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6149 unsignedp
, in_dest
, in_compare
);
6151 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6154 inner_mode
= GET_MODE (inner
);
6156 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6157 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6159 /* See if this can be done without an extraction. We never can if the
6160 width of the field is not the same as that of some integer mode. For
6161 registers, we can only avoid the extraction if the position is at the
6162 low-order bit and this is either not in the destination or we have the
6163 appropriate STRICT_LOW_PART operation available.
6165 For MEM, we can avoid an extract if the field starts on an appropriate
6166 boundary and we can change the mode of the memory reference. However,
6167 we cannot directly access the MEM if we have a USE and the underlying
6168 MEM is not TMODE. This combination means that MEM was being used in a
6169 context where bits outside its mode were being referenced; that is only
6170 valid in bit-field insns. */
6172 if (tmode
!= BLKmode
6173 && ! (spans_byte
&& inner_mode
!= tmode
)
6174 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6178 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6179 || (MEM_P (inner
) && pos_rtx
== 0
6181 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6182 : BITS_PER_UNIT
)) == 0
6183 /* We can't do this if we are widening INNER_MODE (it
6184 may not be aligned, for one thing). */
6185 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6186 && (inner_mode
== tmode
6187 || (! mode_dependent_address_p (XEXP (inner
, 0))
6188 && ! MEM_VOLATILE_P (inner
))))))
6190 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6191 field. If the original and current mode are the same, we need not
6192 adjust the offset. Otherwise, we do if bytes big endian.
6194 If INNER is not a MEM, get a piece consisting of just the field
6195 of interest (in this case POS % BITS_PER_WORD must be 0). */
6199 HOST_WIDE_INT offset
;
6201 /* POS counts from lsb, but make OFFSET count in memory order. */
6202 if (BYTES_BIG_ENDIAN
)
6203 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6205 offset
= pos
/ BITS_PER_UNIT
;
6207 new = adjust_address_nv (inner
, tmode
, offset
);
6209 else if (REG_P (inner
))
6211 if (tmode
!= inner_mode
)
6213 /* We can't call gen_lowpart in a DEST since we
6214 always want a SUBREG (see below) and it would sometimes
6215 return a new hard register. */
6218 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6220 if (WORDS_BIG_ENDIAN
6221 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6222 final_word
= ((GET_MODE_SIZE (inner_mode
)
6223 - GET_MODE_SIZE (tmode
))
6224 / UNITS_PER_WORD
) - final_word
;
6226 final_word
*= UNITS_PER_WORD
;
6227 if (BYTES_BIG_ENDIAN
&&
6228 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6229 final_word
+= (GET_MODE_SIZE (inner_mode
)
6230 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6232 /* Avoid creating invalid subregs, for example when
6233 simplifying (x>>32)&255. */
6234 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6237 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6240 new = gen_lowpart (tmode
, inner
);
6246 new = force_to_mode (inner
, tmode
,
6247 len
>= HOST_BITS_PER_WIDE_INT
6248 ? ~(unsigned HOST_WIDE_INT
) 0
6249 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6252 /* If this extraction is going into the destination of a SET,
6253 make a STRICT_LOW_PART unless we made a MEM. */
6256 return (MEM_P (new) ? new
6257 : (GET_CODE (new) != SUBREG
6258 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6259 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6264 if (GET_CODE (new) == CONST_INT
)
6265 return gen_int_mode (INTVAL (new), mode
);
6267 /* If we know that no extraneous bits are set, and that the high
6268 bit is not set, convert the extraction to the cheaper of
6269 sign and zero extension, that are equivalent in these cases. */
6270 if (flag_expensive_optimizations
6271 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6272 && ((nonzero_bits (new, tmode
)
6273 & ~(((unsigned HOST_WIDE_INT
)
6274 GET_MODE_MASK (tmode
))
6278 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6279 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6281 /* Prefer ZERO_EXTENSION, since it gives more information to
6283 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6288 /* Otherwise, sign- or zero-extend unless we already are in the
6291 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6295 /* Unless this is a COMPARE or we have a funny memory reference,
6296 don't do anything with zero-extending field extracts starting at
6297 the low-order bit since they are simple AND operations. */
6298 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6299 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6302 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6303 we would be spanning bytes or if the position is not a constant and the
6304 length is not 1. In all other cases, we would only be going outside
6305 our object in cases when an original shift would have been
6307 if (! spans_byte
&& MEM_P (inner
)
6308 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6309 || (pos_rtx
!= 0 && len
!= 1)))
6312 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6313 and the mode for the result. */
6314 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6316 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6317 pos_mode
= mode_for_extraction (EP_insv
, 2);
6318 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6321 if (! in_dest
&& unsignedp
6322 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6324 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6325 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6326 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6329 if (! in_dest
&& ! unsignedp
6330 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6332 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6333 pos_mode
= mode_for_extraction (EP_extv
, 3);
6334 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6337 /* Never narrow an object, since that might not be safe. */
6339 if (mode
!= VOIDmode
6340 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6341 extraction_mode
= mode
;
6343 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6344 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6345 pos_mode
= GET_MODE (pos_rtx
);
6347 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6348 if we have to change the mode of memory and cannot, the desired mode is
6351 wanted_inner_mode
= wanted_inner_reg_mode
;
6352 else if (inner_mode
!= wanted_inner_mode
6353 && (mode_dependent_address_p (XEXP (inner
, 0))
6354 || MEM_VOLATILE_P (inner
)))
6355 wanted_inner_mode
= extraction_mode
;
6359 if (BITS_BIG_ENDIAN
)
6361 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6362 BITS_BIG_ENDIAN style. If position is constant, compute new
6363 position. Otherwise, build subtraction.
6364 Note that POS is relative to the mode of the original argument.
6365 If it's a MEM we need to recompute POS relative to that.
6366 However, if we're extracting from (or inserting into) a register,
6367 we want to recompute POS relative to wanted_inner_mode. */
6368 int width
= (MEM_P (inner
)
6369 ? GET_MODE_BITSIZE (is_mode
)
6370 : GET_MODE_BITSIZE (wanted_inner_mode
));
6373 pos
= width
- len
- pos
;
6376 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6377 /* POS may be less than 0 now, but we check for that below.
6378 Note that it can only be less than 0 if !MEM_P (inner). */
6381 /* If INNER has a wider mode, make it smaller. If this is a constant
6382 extract, try to adjust the byte to point to the byte containing
6384 if (wanted_inner_mode
!= VOIDmode
6385 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6387 && (inner_mode
== wanted_inner_mode
6388 || (! mode_dependent_address_p (XEXP (inner
, 0))
6389 && ! MEM_VOLATILE_P (inner
))))))
6393 /* The computations below will be correct if the machine is big
6394 endian in both bits and bytes or little endian in bits and bytes.
6395 If it is mixed, we must adjust. */
6397 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6398 adjust OFFSET to compensate. */
6399 if (BYTES_BIG_ENDIAN
6401 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6402 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6404 /* If this is a constant position, we can move to the desired byte. */
6407 offset
+= pos
/ BITS_PER_UNIT
;
6408 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6411 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6413 && is_mode
!= wanted_inner_mode
)
6414 offset
= (GET_MODE_SIZE (is_mode
)
6415 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6417 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6418 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6421 /* If INNER is not memory, we can always get it into the proper mode. If we
6422 are changing its mode, POS must be a constant and smaller than the size
6424 else if (!MEM_P (inner
))
6426 if (GET_MODE (inner
) != wanted_inner_mode
6428 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6431 inner
= force_to_mode (inner
, wanted_inner_mode
,
6433 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6434 ? ~(unsigned HOST_WIDE_INT
) 0
6435 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6440 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6441 have to zero extend. Otherwise, we can just use a SUBREG. */
6443 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6445 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6447 /* If we know that no extraneous bits are set, and that the high
6448 bit is not set, convert extraction to cheaper one - either
6449 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6451 if (flag_expensive_optimizations
6452 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6453 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6454 & ~(((unsigned HOST_WIDE_INT
)
6455 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6459 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6461 /* Prefer ZERO_EXTENSION, since it gives more information to
6463 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6468 else if (pos_rtx
!= 0
6469 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6470 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6472 /* Make POS_RTX unless we already have it and it is correct. If we don't
6473 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6475 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6476 pos_rtx
= orig_pos_rtx
;
6478 else if (pos_rtx
== 0)
6479 pos_rtx
= GEN_INT (pos
);
6481 /* Make the required operation. See if we can use existing rtx. */
6482 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6483 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6485 new = gen_lowpart (mode
, new);
6490 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6491 with any other operations in X. Return X without that shift if so. */
6494 extract_left_shift (rtx x
, int count
)
6496 enum rtx_code code
= GET_CODE (x
);
6497 enum machine_mode mode
= GET_MODE (x
);
6503 /* This is the shift itself. If it is wide enough, we will return
6504 either the value being shifted if the shift count is equal to
6505 COUNT or a shift for the difference. */
6506 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6507 && INTVAL (XEXP (x
, 1)) >= count
)
6508 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6509 INTVAL (XEXP (x
, 1)) - count
);
6513 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6514 return simplify_gen_unary (code
, mode
, tem
, mode
);
6518 case PLUS
: case IOR
: case XOR
: case AND
:
6519 /* If we can safely shift this constant and we find the inner shift,
6520 make a new operation. */
6521 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6522 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6523 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6524 return gen_binary (code
, mode
, tem
,
6525 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6536 /* Look at the expression rooted at X. Look for expressions
6537 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6538 Form these expressions.
6540 Return the new rtx, usually just X.
6542 Also, for machines like the VAX that don't have logical shift insns,
6543 try to convert logical to arithmetic shift operations in cases where
6544 they are equivalent. This undoes the canonicalizations to logical
6545 shifts done elsewhere.
6547 We try, as much as possible, to re-use rtl expressions to save memory.
6549 IN_CODE says what kind of expression we are processing. Normally, it is
6550 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6551 being kludges), it is MEM. When processing the arguments of a comparison
6552 or a COMPARE against zero, it is COMPARE. */
6555 make_compound_operation (rtx x
, enum rtx_code in_code
)
6557 enum rtx_code code
= GET_CODE (x
);
6558 enum machine_mode mode
= GET_MODE (x
);
6559 int mode_width
= GET_MODE_BITSIZE (mode
);
6561 enum rtx_code next_code
;
6567 /* Select the code to be used in recursive calls. Once we are inside an
6568 address, we stay there. If we have a comparison, set to COMPARE,
6569 but once inside, go back to our default of SET. */
6571 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6572 : ((code
== COMPARE
|| COMPARISON_P (x
))
6573 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6574 : in_code
== COMPARE
? SET
: in_code
);
6576 /* Process depending on the code of this operation. If NEW is set
6577 nonzero, it will be returned. */
6582 /* Convert shifts by constants into multiplications if inside
6584 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6585 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6586 && INTVAL (XEXP (x
, 1)) >= 0)
6588 new = make_compound_operation (XEXP (x
, 0), next_code
);
6589 new = gen_rtx_MULT (mode
, new,
6590 GEN_INT ((HOST_WIDE_INT
) 1
6591 << INTVAL (XEXP (x
, 1))));
6596 /* If the second operand is not a constant, we can't do anything
6598 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6601 /* If the constant is a power of two minus one and the first operand
6602 is a logical right shift, make an extraction. */
6603 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6604 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6606 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6607 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6608 0, in_code
== COMPARE
);
6611 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6612 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6613 && subreg_lowpart_p (XEXP (x
, 0))
6614 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6615 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6617 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6619 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6620 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6621 0, in_code
== COMPARE
);
6623 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6624 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6625 || GET_CODE (XEXP (x
, 0)) == IOR
)
6626 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6627 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6628 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6630 /* Apply the distributive law, and then try to make extractions. */
6631 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6632 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6634 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6636 new = make_compound_operation (new, in_code
);
6639 /* If we are have (and (rotate X C) M) and C is larger than the number
6640 of bits in M, this is an extraction. */
6642 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6643 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6644 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6645 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6647 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6648 new = make_extraction (mode
, new,
6649 (GET_MODE_BITSIZE (mode
)
6650 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6651 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6654 /* On machines without logical shifts, if the operand of the AND is
6655 a logical shift and our mask turns off all the propagated sign
6656 bits, we can replace the logical shift with an arithmetic shift. */
6657 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6658 && !have_insn_for (LSHIFTRT
, mode
)
6659 && have_insn_for (ASHIFTRT
, mode
)
6660 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6661 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6662 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6663 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6665 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6667 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6668 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6670 gen_rtx_ASHIFTRT (mode
,
6671 make_compound_operation
6672 (XEXP (XEXP (x
, 0), 0), next_code
),
6673 XEXP (XEXP (x
, 0), 1)));
6676 /* If the constant is one less than a power of two, this might be
6677 representable by an extraction even if no shift is present.
6678 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6679 we are in a COMPARE. */
6680 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6681 new = make_extraction (mode
,
6682 make_compound_operation (XEXP (x
, 0),
6684 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6686 /* If we are in a comparison and this is an AND with a power of two,
6687 convert this into the appropriate bit extract. */
6688 else if (in_code
== COMPARE
6689 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6690 new = make_extraction (mode
,
6691 make_compound_operation (XEXP (x
, 0),
6693 i
, NULL_RTX
, 1, 1, 0, 1);
6698 /* If the sign bit is known to be zero, replace this with an
6699 arithmetic shift. */
6700 if (have_insn_for (ASHIFTRT
, mode
)
6701 && ! have_insn_for (LSHIFTRT
, mode
)
6702 && mode_width
<= HOST_BITS_PER_WIDE_INT
6703 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6705 new = gen_rtx_ASHIFTRT (mode
,
6706 make_compound_operation (XEXP (x
, 0),
6712 /* ... fall through ... */
6718 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6719 this is a SIGN_EXTRACT. */
6720 if (GET_CODE (rhs
) == CONST_INT
6721 && GET_CODE (lhs
) == ASHIFT
6722 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6723 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6725 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6726 new = make_extraction (mode
, new,
6727 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6728 NULL_RTX
, mode_width
- INTVAL (rhs
),
6729 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6733 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6734 If so, try to merge the shifts into a SIGN_EXTEND. We could
6735 also do this for some cases of SIGN_EXTRACT, but it doesn't
6736 seem worth the effort; the case checked for occurs on Alpha. */
6739 && ! (GET_CODE (lhs
) == SUBREG
6740 && (OBJECT_P (SUBREG_REG (lhs
))))
6741 && GET_CODE (rhs
) == CONST_INT
6742 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6743 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6744 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6745 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6746 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6751 /* Call ourselves recursively on the inner expression. If we are
6752 narrowing the object and it has a different RTL code from
6753 what it originally did, do this SUBREG as a force_to_mode. */
6755 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6756 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6757 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6758 && subreg_lowpart_p (x
))
6760 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6763 /* If we have something other than a SUBREG, we might have
6764 done an expansion, so rerun ourselves. */
6765 if (GET_CODE (newer
) != SUBREG
)
6766 newer
= make_compound_operation (newer
, in_code
);
6771 /* If this is a paradoxical subreg, and the new code is a sign or
6772 zero extension, omit the subreg and widen the extension. If it
6773 is a regular subreg, we can still get rid of the subreg by not
6774 widening so much, or in fact removing the extension entirely. */
6775 if ((GET_CODE (tem
) == SIGN_EXTEND
6776 || GET_CODE (tem
) == ZERO_EXTEND
)
6777 && subreg_lowpart_p (x
))
6779 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6780 || (GET_MODE_SIZE (mode
) >
6781 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6783 if (! SCALAR_INT_MODE_P (mode
))
6785 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6788 tem
= gen_lowpart (mode
, XEXP (tem
, 0));
6799 x
= gen_lowpart (mode
, new);
6800 code
= GET_CODE (x
);
6803 /* Now recursively process each operand of this operation. */
6804 fmt
= GET_RTX_FORMAT (code
);
6805 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6808 new = make_compound_operation (XEXP (x
, i
), next_code
);
6809 SUBST (XEXP (x
, i
), new);
6815 /* Given M see if it is a value that would select a field of bits
6816 within an item, but not the entire word. Return -1 if not.
6817 Otherwise, return the starting position of the field, where 0 is the
6820 *PLEN is set to the length of the field. */
6823 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6825 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6826 int pos
= exact_log2 (m
& -m
);
6830 /* Now shift off the low-order zero bits and see if we have a
6831 power of two minus 1. */
6832 len
= exact_log2 ((m
>> pos
) + 1);
6841 /* See if X can be simplified knowing that we will only refer to it in
6842 MODE and will only refer to those bits that are nonzero in MASK.
6843 If other bits are being computed or if masking operations are done
6844 that select a superset of the bits in MASK, they can sometimes be
6847 Return a possibly simplified expression, but always convert X to
6848 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6850 Also, if REG is nonzero and X is a register equal in value to REG,
6853 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6854 are all off in X. This is used when X will be complemented, by either
6855 NOT, NEG, or XOR. */
6858 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6859 rtx reg
, int just_select
)
6861 enum rtx_code code
= GET_CODE (x
);
6862 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6863 enum machine_mode op_mode
;
6864 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6867 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6868 code below will do the wrong thing since the mode of such an
6869 expression is VOIDmode.
6871 Also do nothing if X is a CLOBBER; this can happen if X was
6872 the return value from a call to gen_lowpart. */
6873 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6876 /* We want to perform the operation is its present mode unless we know
6877 that the operation is valid in MODE, in which case we do the operation
6879 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6880 && have_insn_for (code
, mode
))
6881 ? mode
: GET_MODE (x
));
6883 /* It is not valid to do a right-shift in a narrower mode
6884 than the one it came in with. */
6885 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6886 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6887 op_mode
= GET_MODE (x
);
6889 /* Truncate MASK to fit OP_MODE. */
6891 mask
&= GET_MODE_MASK (op_mode
);
6893 /* When we have an arithmetic operation, or a shift whose count we
6894 do not know, we need to assume that all bits up to the highest-order
6895 bit in MASK will be needed. This is how we form such a mask. */
6896 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6897 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6899 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6902 /* Determine what bits of X are guaranteed to be (non)zero. */
6903 nonzero
= nonzero_bits (x
, mode
);
6905 /* If none of the bits in X are needed, return a zero. */
6906 if (! just_select
&& (nonzero
& mask
) == 0)
6909 /* If X is a CONST_INT, return a new one. Do this here since the
6910 test below will fail. */
6911 if (GET_CODE (x
) == CONST_INT
)
6913 if (SCALAR_INT_MODE_P (mode
))
6914 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6917 x
= GEN_INT (INTVAL (x
) & mask
);
6918 return gen_lowpart_common (mode
, x
);
6922 /* If X is narrower than MODE and we want all the bits in X's mode, just
6923 get X in the proper mode. */
6924 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6925 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6926 return gen_lowpart (mode
, x
);
6931 /* If X is a (clobber (const_int)), return it since we know we are
6932 generating something that won't match. */
6936 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6937 spanned the boundary of the MEM. If we are now masking so it is
6938 within that boundary, we don't need the USE any more. */
6939 if (! BITS_BIG_ENDIAN
6940 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6941 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6948 x
= expand_compound_operation (x
);
6949 if (GET_CODE (x
) != code
)
6950 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6954 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6955 || rtx_equal_p (reg
, get_last_value (x
))))
6960 if (subreg_lowpart_p (x
)
6961 /* We can ignore the effect of this SUBREG if it narrows the mode or
6962 if the constant masks to zero all the bits the mode doesn't
6964 && ((GET_MODE_SIZE (GET_MODE (x
))
6965 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6967 & GET_MODE_MASK (GET_MODE (x
))
6968 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6969 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6973 /* If this is an AND with a constant, convert it into an AND
6974 whose constant is the AND of that constant with MASK. If it
6975 remains an AND of MASK, delete it since it is redundant. */
6977 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6979 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6980 mask
& INTVAL (XEXP (x
, 1)));
6982 /* If X is still an AND, see if it is an AND with a mask that
6983 is just some low-order bits. If so, and it is MASK, we don't
6986 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6987 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6991 /* If it remains an AND, try making another AND with the bits
6992 in the mode mask that aren't in MASK turned on. If the
6993 constant in the AND is wide enough, this might make a
6994 cheaper constant. */
6996 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6997 && GET_MODE_MASK (GET_MODE (x
)) != mask
6998 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
7000 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
7001 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
7002 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
7005 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7006 number, sign extend it. */
7007 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
7008 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7009 cval
|= (HOST_WIDE_INT
) -1 << width
;
7011 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
7012 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
7022 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7023 low-order bits (as in an alignment operation) and FOO is already
7024 aligned to that boundary, mask C1 to that boundary as well.
7025 This may eliminate that PLUS and, later, the AND. */
7028 unsigned int width
= GET_MODE_BITSIZE (mode
);
7029 unsigned HOST_WIDE_INT smask
= mask
;
7031 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7032 number, sign extend it. */
7034 if (width
< HOST_BITS_PER_WIDE_INT
7035 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7036 smask
|= (HOST_WIDE_INT
) -1 << width
;
7038 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7039 && exact_log2 (- smask
) >= 0
7040 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
7041 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
7042 return force_to_mode (plus_constant (XEXP (x
, 0),
7043 (INTVAL (XEXP (x
, 1)) & smask
)),
7044 mode
, smask
, reg
, next_select
);
7047 /* ... fall through ... */
7050 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7051 most significant bit in MASK since carries from those bits will
7052 affect the bits we are interested in. */
7057 /* If X is (minus C Y) where C's least set bit is larger than any bit
7058 in the mask, then we may replace with (neg Y). */
7059 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7060 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
7061 & -INTVAL (XEXP (x
, 0))))
7064 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
7066 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7069 /* Similarly, if C contains every bit in the fuller_mask, then we may
7070 replace with (not Y). */
7071 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7072 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
7073 == INTVAL (XEXP (x
, 0))))
7075 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
7076 XEXP (x
, 1), GET_MODE (x
));
7077 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7085 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7086 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7087 operation which may be a bitfield extraction. Ensure that the
7088 constant we form is not wider than the mode of X. */
7090 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7091 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7092 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7093 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7094 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7095 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
7096 + floor_log2 (INTVAL (XEXP (x
, 1))))
7097 < GET_MODE_BITSIZE (GET_MODE (x
)))
7098 && (INTVAL (XEXP (x
, 1))
7099 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7101 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7102 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7103 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
7104 XEXP (XEXP (x
, 0), 0), temp
);
7105 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7106 XEXP (XEXP (x
, 0), 1));
7107 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7111 /* For most binary operations, just propagate into the operation and
7112 change the mode if we have an operation of that mode. */
7114 op0
= gen_lowpart (op_mode
,
7115 force_to_mode (XEXP (x
, 0), mode
, mask
,
7117 op1
= gen_lowpart (op_mode
,
7118 force_to_mode (XEXP (x
, 1), mode
, mask
,
7121 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7122 x
= gen_binary (code
, op_mode
, op0
, op1
);
7126 /* For left shifts, do the same, but just for the first operand.
7127 However, we cannot do anything with shifts where we cannot
7128 guarantee that the counts are smaller than the size of the mode
7129 because such a count will have a different meaning in a
7132 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7133 && INTVAL (XEXP (x
, 1)) >= 0
7134 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7135 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7136 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7137 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7140 /* If the shift count is a constant and we can do arithmetic in
7141 the mode of the shift, refine which bits we need. Otherwise, use the
7142 conservative form of the mask. */
7143 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7144 && INTVAL (XEXP (x
, 1)) >= 0
7145 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7146 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7147 mask
>>= INTVAL (XEXP (x
, 1));
7151 op0
= gen_lowpart (op_mode
,
7152 force_to_mode (XEXP (x
, 0), op_mode
,
7153 mask
, reg
, next_select
));
7155 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7156 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7160 /* Here we can only do something if the shift count is a constant,
7161 this shift constant is valid for the host, and we can do arithmetic
7164 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7165 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7166 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7168 rtx inner
= XEXP (x
, 0);
7169 unsigned HOST_WIDE_INT inner_mask
;
7171 /* Select the mask of the bits we need for the shift operand. */
7172 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7174 /* We can only change the mode of the shift if we can do arithmetic
7175 in the mode of the shift and INNER_MASK is no wider than the
7176 width of X's mode. */
7177 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
7178 op_mode
= GET_MODE (x
);
7180 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7182 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7183 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7186 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7187 shift and AND produces only copies of the sign bit (C2 is one less
7188 than a power of two), we can do this with just a shift. */
7190 if (GET_CODE (x
) == LSHIFTRT
7191 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7192 /* The shift puts one of the sign bit copies in the least significant
7194 && ((INTVAL (XEXP (x
, 1))
7195 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7196 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7197 && exact_log2 (mask
+ 1) >= 0
7198 /* Number of bits left after the shift must be more than the mask
7200 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7201 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7202 /* Must be more sign bit copies than the mask needs. */
7203 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7204 >= exact_log2 (mask
+ 1)))
7205 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7206 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7207 - exact_log2 (mask
+ 1)));
7212 /* If we are just looking for the sign bit, we don't need this shift at
7213 all, even if it has a variable count. */
7214 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7215 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7216 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7217 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7219 /* If this is a shift by a constant, get a mask that contains those bits
7220 that are not copies of the sign bit. We then have two cases: If
7221 MASK only includes those bits, this can be a logical shift, which may
7222 allow simplifications. If MASK is a single-bit field not within
7223 those bits, we are requesting a copy of the sign bit and hence can
7224 shift the sign bit to the appropriate location. */
7226 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7227 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7231 /* If the considered data is wider than HOST_WIDE_INT, we can't
7232 represent a mask for all its bits in a single scalar.
7233 But we only care about the lower bits, so calculate these. */
7235 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7237 nonzero
= ~(HOST_WIDE_INT
) 0;
7239 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7240 is the number of bits a full-width mask would have set.
7241 We need only shift if these are fewer than nonzero can
7242 hold. If not, we must keep all bits set in nonzero. */
7244 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7245 < HOST_BITS_PER_WIDE_INT
)
7246 nonzero
>>= INTVAL (XEXP (x
, 1))
7247 + HOST_BITS_PER_WIDE_INT
7248 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7252 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7253 nonzero
>>= INTVAL (XEXP (x
, 1));
7256 if ((mask
& ~nonzero
) == 0
7257 || (i
= exact_log2 (mask
)) >= 0)
7259 x
= simplify_shift_const
7260 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7261 i
< 0 ? INTVAL (XEXP (x
, 1))
7262 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7264 if (GET_CODE (x
) != ASHIFTRT
)
7265 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7269 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7270 even if the shift count isn't a constant. */
7272 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7276 /* If this is a zero- or sign-extension operation that just affects bits
7277 we don't care about, remove it. Be sure the call above returned
7278 something that is still a shift. */
7280 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7281 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7282 && INTVAL (XEXP (x
, 1)) >= 0
7283 && (INTVAL (XEXP (x
, 1))
7284 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7285 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7286 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7287 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7294 /* If the shift count is constant and we can do computations
7295 in the mode of X, compute where the bits we care about are.
7296 Otherwise, we can't do anything. Don't change the mode of
7297 the shift or propagate MODE into the shift, though. */
7298 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7299 && INTVAL (XEXP (x
, 1)) >= 0)
7301 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7302 GET_MODE (x
), GEN_INT (mask
),
7304 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7306 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7307 INTVAL (temp
), reg
, next_select
));
7312 /* If we just want the low-order bit, the NEG isn't needed since it
7313 won't change the low-order bit. */
7315 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7317 /* We need any bits less significant than the most significant bit in
7318 MASK since carries from those bits will affect the bits we are
7324 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7325 same as the XOR case above. Ensure that the constant we form is not
7326 wider than the mode of X. */
7328 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7329 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7330 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7331 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7332 < GET_MODE_BITSIZE (GET_MODE (x
)))
7333 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7335 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7337 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7338 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7340 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7343 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7344 use the full mask inside the NOT. */
7348 op0
= gen_lowpart (op_mode
,
7349 force_to_mode (XEXP (x
, 0), mode
, mask
,
7351 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7352 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7356 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7357 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7358 which is equal to STORE_FLAG_VALUE. */
7359 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7360 && GET_MODE (XEXP (x
, 0)) == mode
7361 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7362 && (nonzero_bits (XEXP (x
, 0), mode
)
7363 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7364 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7369 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7370 written in a narrower mode. We play it safe and do not do so. */
7373 gen_lowpart (GET_MODE (x
),
7374 force_to_mode (XEXP (x
, 1), mode
,
7375 mask
, reg
, next_select
)));
7377 gen_lowpart (GET_MODE (x
),
7378 force_to_mode (XEXP (x
, 2), mode
,
7379 mask
, reg
, next_select
)));
7386 /* Ensure we return a value of the proper mode. */
7387 return gen_lowpart (mode
, x
);
7390 /* Return nonzero if X is an expression that has one of two values depending on
7391 whether some other value is zero or nonzero. In that case, we return the
7392 value that is being tested, *PTRUE is set to the value if the rtx being
7393 returned has a nonzero value, and *PFALSE is set to the other alternative.
7395 If we return zero, we set *PTRUE and *PFALSE to X. */
7398 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7400 enum machine_mode mode
= GET_MODE (x
);
7401 enum rtx_code code
= GET_CODE (x
);
7402 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7403 unsigned HOST_WIDE_INT nz
;
7405 /* If we are comparing a value against zero, we are done. */
7406 if ((code
== NE
|| code
== EQ
)
7407 && XEXP (x
, 1) == const0_rtx
)
7409 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7410 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7414 /* If this is a unary operation whose operand has one of two values, apply
7415 our opcode to compute those values. */
7416 else if (UNARY_P (x
)
7417 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7419 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7420 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7421 GET_MODE (XEXP (x
, 0)));
7425 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7426 make can't possibly match and would suppress other optimizations. */
7427 else if (code
== COMPARE
)
7430 /* If this is a binary operation, see if either side has only one of two
7431 values. If either one does or if both do and they are conditional on
7432 the same value, compute the new true and false values. */
7433 else if (BINARY_P (x
))
7435 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7436 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7438 if ((cond0
!= 0 || cond1
!= 0)
7439 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7441 /* If if_then_else_cond returned zero, then true/false are the
7442 same rtl. We must copy one of them to prevent invalid rtl
7445 true0
= copy_rtx (true0
);
7446 else if (cond1
== 0)
7447 true1
= copy_rtx (true1
);
7449 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7450 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7451 return cond0
? cond0
: cond1
;
7454 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7455 operands is zero when the other is nonzero, and vice-versa,
7456 and STORE_FLAG_VALUE is 1 or -1. */
7458 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7459 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7461 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7463 rtx op0
= XEXP (XEXP (x
, 0), 1);
7464 rtx op1
= XEXP (XEXP (x
, 1), 1);
7466 cond0
= XEXP (XEXP (x
, 0), 0);
7467 cond1
= XEXP (XEXP (x
, 1), 0);
7469 if (COMPARISON_P (cond0
)
7470 && COMPARISON_P (cond1
)
7471 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7472 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7473 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7474 || ((swap_condition (GET_CODE (cond0
))
7475 == combine_reversed_comparison_code (cond1
))
7476 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7477 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7478 && ! side_effects_p (x
))
7480 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7481 *pfalse
= gen_binary (MULT
, mode
,
7483 ? simplify_gen_unary (NEG
, mode
, op1
,
7491 /* Similarly for MULT, AND and UMIN, except that for these the result
7493 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7494 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7495 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7497 cond0
= XEXP (XEXP (x
, 0), 0);
7498 cond1
= XEXP (XEXP (x
, 1), 0);
7500 if (COMPARISON_P (cond0
)
7501 && COMPARISON_P (cond1
)
7502 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7503 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7504 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7505 || ((swap_condition (GET_CODE (cond0
))
7506 == combine_reversed_comparison_code (cond1
))
7507 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7508 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7509 && ! side_effects_p (x
))
7511 *ptrue
= *pfalse
= const0_rtx
;
7517 else if (code
== IF_THEN_ELSE
)
7519 /* If we have IF_THEN_ELSE already, extract the condition and
7520 canonicalize it if it is NE or EQ. */
7521 cond0
= XEXP (x
, 0);
7522 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7523 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7524 return XEXP (cond0
, 0);
7525 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7527 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7528 return XEXP (cond0
, 0);
7534 /* If X is a SUBREG, we can narrow both the true and false values
7535 if the inner expression, if there is a condition. */
7536 else if (code
== SUBREG
7537 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7540 true0
= simplify_gen_subreg (mode
, true0
,
7541 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7542 false0
= simplify_gen_subreg (mode
, false0
,
7543 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7544 if (true0
&& false0
)
7552 /* If X is a constant, this isn't special and will cause confusions
7553 if we treat it as such. Likewise if it is equivalent to a constant. */
7554 else if (CONSTANT_P (x
)
7555 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7558 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7559 will be least confusing to the rest of the compiler. */
7560 else if (mode
== BImode
)
7562 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7566 /* If X is known to be either 0 or -1, those are the true and
7567 false values when testing X. */
7568 else if (x
== constm1_rtx
|| x
== const0_rtx
7569 || (mode
!= VOIDmode
7570 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7572 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7576 /* Likewise for 0 or a single bit. */
7577 else if (SCALAR_INT_MODE_P (mode
)
7578 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7579 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7581 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7585 /* Otherwise fail; show no condition with true and false values the same. */
7586 *ptrue
= *pfalse
= x
;
7590 /* Return the value of expression X given the fact that condition COND
7591 is known to be true when applied to REG as its first operand and VAL
7592 as its second. X is known to not be shared and so can be modified in
7595 We only handle the simplest cases, and specifically those cases that
7596 arise with IF_THEN_ELSE expressions. */
7599 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7601 enum rtx_code code
= GET_CODE (x
);
7606 if (side_effects_p (x
))
7609 /* If either operand of the condition is a floating point value,
7610 then we have to avoid collapsing an EQ comparison. */
7612 && rtx_equal_p (x
, reg
)
7613 && ! FLOAT_MODE_P (GET_MODE (x
))
7614 && ! FLOAT_MODE_P (GET_MODE (val
)))
7617 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7620 /* If X is (abs REG) and we know something about REG's relationship
7621 with zero, we may be able to simplify this. */
7623 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7626 case GE
: case GT
: case EQ
:
7629 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7631 GET_MODE (XEXP (x
, 0)));
7636 /* The only other cases we handle are MIN, MAX, and comparisons if the
7637 operands are the same as REG and VAL. */
7639 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
7641 if (rtx_equal_p (XEXP (x
, 0), val
))
7642 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7644 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7646 if (COMPARISON_P (x
))
7648 if (comparison_dominates_p (cond
, code
))
7649 return const_true_rtx
;
7651 code
= combine_reversed_comparison_code (x
);
7653 && comparison_dominates_p (cond
, code
))
7658 else if (code
== SMAX
|| code
== SMIN
7659 || code
== UMIN
|| code
== UMAX
)
7661 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7663 /* Do not reverse the condition when it is NE or EQ.
7664 This is because we cannot conclude anything about
7665 the value of 'SMAX (x, y)' when x is not equal to y,
7666 but we can when x equals y. */
7667 if ((code
== SMAX
|| code
== UMAX
)
7668 && ! (cond
== EQ
|| cond
== NE
))
7669 cond
= reverse_condition (cond
);
7674 return unsignedp
? x
: XEXP (x
, 1);
7676 return unsignedp
? x
: XEXP (x
, 0);
7678 return unsignedp
? XEXP (x
, 1) : x
;
7680 return unsignedp
? XEXP (x
, 0) : x
;
7687 else if (code
== SUBREG
)
7689 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7690 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7692 if (SUBREG_REG (x
) != r
)
7694 /* We must simplify subreg here, before we lose track of the
7695 original inner_mode. */
7696 new = simplify_subreg (GET_MODE (x
), r
,
7697 inner_mode
, SUBREG_BYTE (x
));
7701 SUBST (SUBREG_REG (x
), r
);
7706 /* We don't have to handle SIGN_EXTEND here, because even in the
7707 case of replacing something with a modeless CONST_INT, a
7708 CONST_INT is already (supposed to be) a valid sign extension for
7709 its narrower mode, which implies it's already properly
7710 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7711 story is different. */
7712 else if (code
== ZERO_EXTEND
)
7714 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7715 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7717 if (XEXP (x
, 0) != r
)
7719 /* We must simplify the zero_extend here, before we lose
7720 track of the original inner_mode. */
7721 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7726 SUBST (XEXP (x
, 0), r
);
7732 fmt
= GET_RTX_FORMAT (code
);
7733 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7736 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7737 else if (fmt
[i
] == 'E')
7738 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7739 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7746 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7747 assignment as a field assignment. */
7750 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7752 if (x
== y
|| rtx_equal_p (x
, y
))
7755 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7758 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7759 Note that all SUBREGs of MEM are paradoxical; otherwise they
7760 would have been rewritten. */
7761 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
7762 && MEM_P (SUBREG_REG (y
))
7763 && rtx_equal_p (SUBREG_REG (y
),
7764 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
7767 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
7768 && MEM_P (SUBREG_REG (x
))
7769 && rtx_equal_p (SUBREG_REG (x
),
7770 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
7773 /* We used to see if get_last_value of X and Y were the same but that's
7774 not correct. In one direction, we'll cause the assignment to have
7775 the wrong destination and in the case, we'll import a register into this
7776 insn that might have already have been dead. So fail if none of the
7777 above cases are true. */
7781 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7782 Return that assignment if so.
7784 We only handle the most common cases. */
7787 make_field_assignment (rtx x
)
7789 rtx dest
= SET_DEST (x
);
7790 rtx src
= SET_SRC (x
);
7795 unsigned HOST_WIDE_INT len
;
7797 enum machine_mode mode
;
7799 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7800 a clear of a one-bit field. We will have changed it to
7801 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7804 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7805 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7806 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7807 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7809 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7812 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7816 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7817 && subreg_lowpart_p (XEXP (src
, 0))
7818 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7819 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7820 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7821 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7822 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7823 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7825 assign
= make_extraction (VOIDmode
, dest
, 0,
7826 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7829 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7833 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7835 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7836 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7837 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7839 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7842 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7846 /* The other case we handle is assignments into a constant-position
7847 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7848 a mask that has all one bits except for a group of zero bits and
7849 OTHER is known to have zeros where C1 has ones, this is such an
7850 assignment. Compute the position and length from C1. Shift OTHER
7851 to the appropriate position, force it to the required mode, and
7852 make the extraction. Check for the AND in both operands. */
7854 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7857 rhs
= expand_compound_operation (XEXP (src
, 0));
7858 lhs
= expand_compound_operation (XEXP (src
, 1));
7860 if (GET_CODE (rhs
) == AND
7861 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7862 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7863 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7864 else if (GET_CODE (lhs
) == AND
7865 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7866 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7867 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7871 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7872 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7873 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7874 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7877 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7881 /* The mode to use for the source is the mode of the assignment, or of
7882 what is inside a possible STRICT_LOW_PART. */
7883 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7884 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7886 /* Shift OTHER right POS places and make it the source, restricting it
7887 to the proper length and mode. */
7889 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7890 GET_MODE (src
), other
, pos
),
7892 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7893 ? ~(unsigned HOST_WIDE_INT
) 0
7894 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7897 /* If SRC is masked by an AND that does not make a difference in
7898 the value being stored, strip it. */
7899 if (GET_CODE (assign
) == ZERO_EXTRACT
7900 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7901 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7902 && GET_CODE (src
) == AND
7903 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7904 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7905 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7906 src
= XEXP (src
, 0);
7908 return gen_rtx_SET (VOIDmode
, assign
, src
);
7911 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7915 apply_distributive_law (rtx x
)
7917 enum rtx_code code
= GET_CODE (x
);
7918 enum rtx_code inner_code
;
7919 rtx lhs
, rhs
, other
;
7922 /* Distributivity is not true for floating point as it can change the
7923 value. So we don't do it unless -funsafe-math-optimizations. */
7924 if (FLOAT_MODE_P (GET_MODE (x
))
7925 && ! flag_unsafe_math_optimizations
)
7928 /* The outer operation can only be one of the following: */
7929 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7930 && code
!= PLUS
&& code
!= MINUS
)
7936 /* If either operand is a primitive we can't do anything, so get out
7938 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
7941 lhs
= expand_compound_operation (lhs
);
7942 rhs
= expand_compound_operation (rhs
);
7943 inner_code
= GET_CODE (lhs
);
7944 if (inner_code
!= GET_CODE (rhs
))
7947 /* See if the inner and outer operations distribute. */
7954 /* These all distribute except over PLUS. */
7955 if (code
== PLUS
|| code
== MINUS
)
7960 if (code
!= PLUS
&& code
!= MINUS
)
7965 /* This is also a multiply, so it distributes over everything. */
7969 /* Non-paradoxical SUBREGs distributes over all operations, provided
7970 the inner modes and byte offsets are the same, this is an extraction
7971 of a low-order part, we don't convert an fp operation to int or
7972 vice versa, and we would not be converting a single-word
7973 operation into a multi-word operation. The latter test is not
7974 required, but it prevents generating unneeded multi-word operations.
7975 Some of the previous tests are redundant given the latter test, but
7976 are retained because they are required for correctness.
7978 We produce the result slightly differently in this case. */
7980 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7981 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7982 || ! subreg_lowpart_p (lhs
)
7983 || (GET_MODE_CLASS (GET_MODE (lhs
))
7984 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7985 || (GET_MODE_SIZE (GET_MODE (lhs
))
7986 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7987 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7990 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7991 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7992 return gen_lowpart (GET_MODE (x
), tem
);
7998 /* Set LHS and RHS to the inner operands (A and B in the example
7999 above) and set OTHER to the common operand (C in the example).
8000 There is only one way to do this unless the inner operation is
8002 if (COMMUTATIVE_ARITH_P (lhs
)
8003 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
8004 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
8005 else if (COMMUTATIVE_ARITH_P (lhs
)
8006 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
8007 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
8008 else if (COMMUTATIVE_ARITH_P (lhs
)
8009 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
8010 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
8011 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
8012 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
8016 /* Form the new inner operation, seeing if it simplifies first. */
8017 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
8019 /* There is one exception to the general way of distributing:
8020 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8021 if (code
== XOR
&& inner_code
== IOR
)
8024 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
8027 /* We may be able to continuing distributing the result, so call
8028 ourselves recursively on the inner operation before forming the
8029 outer operation, which we return. */
8030 return gen_binary (inner_code
, GET_MODE (x
),
8031 apply_distributive_law (tem
), other
);
8034 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8037 Return an equivalent form, if different from X. Otherwise, return X. If
8038 X is zero, we are to always construct the equivalent form. */
8041 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
8042 unsigned HOST_WIDE_INT constop
)
8044 unsigned HOST_WIDE_INT nonzero
;
8047 /* Simplify VAROP knowing that we will be only looking at some of the
8050 Note by passing in CONSTOP, we guarantee that the bits not set in
8051 CONSTOP are not significant and will never be examined. We must
8052 ensure that is the case by explicitly masking out those bits
8053 before returning. */
8054 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
8056 /* If VAROP is a CLOBBER, we will fail so return it. */
8057 if (GET_CODE (varop
) == CLOBBER
)
8060 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8061 to VAROP and return the new constant. */
8062 if (GET_CODE (varop
) == CONST_INT
)
8063 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
8065 /* See what bits may be nonzero in VAROP. Unlike the general case of
8066 a call to nonzero_bits, here we don't care about bits outside
8069 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
8071 /* Turn off all bits in the constant that are known to already be zero.
8072 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8073 which is tested below. */
8077 /* If we don't have any bits left, return zero. */
8081 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8082 a power of two, we can replace this with an ASHIFT. */
8083 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
8084 && (i
= exact_log2 (constop
)) >= 0)
8085 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
8087 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8088 or XOR, then try to apply the distributive law. This may eliminate
8089 operations if either branch can be simplified because of the AND.
8090 It may also make some cases more complex, but those cases probably
8091 won't match a pattern either with or without this. */
8093 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
8097 apply_distributive_law
8098 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
8099 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
8100 XEXP (varop
, 0), constop
),
8101 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
8102 XEXP (varop
, 1), constop
))));
8104 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8105 the AND and see if one of the operands simplifies to zero. If so, we
8106 may eliminate it. */
8108 if (GET_CODE (varop
) == PLUS
8109 && exact_log2 (constop
+ 1) >= 0)
8113 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8114 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8115 if (o0
== const0_rtx
)
8117 if (o1
== const0_rtx
)
8121 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8122 if we already had one (just check for the simplest cases). */
8123 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
8124 && GET_MODE (XEXP (x
, 0)) == mode
8125 && SUBREG_REG (XEXP (x
, 0)) == varop
)
8126 varop
= XEXP (x
, 0);
8128 varop
= gen_lowpart (mode
, varop
);
8130 /* If we can't make the SUBREG, try to return what we were given. */
8131 if (GET_CODE (varop
) == CLOBBER
)
8132 return x
? x
: varop
;
8134 /* If we are only masking insignificant bits, return VAROP. */
8135 if (constop
== nonzero
)
8139 /* Otherwise, return an AND. */
8140 constop
= trunc_int_for_mode (constop
, mode
);
8141 /* See how much, if any, of X we can use. */
8142 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
8143 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8147 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8148 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8149 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8151 SUBST (XEXP (x
, 0), varop
);
8158 /* Given a REG, X, compute which bits in X can be nonzero.
8159 We don't care about bits outside of those defined in MODE.
8161 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8162 a shift, AND, or zero_extract, we can do better. */
8165 reg_nonzero_bits_for_combine (rtx x
, enum machine_mode mode
,
8166 rtx known_x ATTRIBUTE_UNUSED
,
8167 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
8168 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
8169 unsigned HOST_WIDE_INT
*nonzero
)
8173 /* If X is a register whose nonzero bits value is current, use it.
8174 Otherwise, if X is a register whose value we can find, use that
8175 value. Otherwise, use the previously-computed global nonzero bits
8176 for this register. */
8178 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8179 && (reg_stat
[REGNO (x
)].last_set_mode
== mode
8180 || (GET_MODE_CLASS (reg_stat
[REGNO (x
)].last_set_mode
) == MODE_INT
8181 && GET_MODE_CLASS (mode
) == MODE_INT
))
8182 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8183 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8184 && REG_N_SETS (REGNO (x
)) == 1
8185 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8187 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8189 *nonzero
&= reg_stat
[REGNO (x
)].last_set_nonzero_bits
;
8193 tem
= get_last_value (x
);
8197 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8198 /* If X is narrower than MODE and TEM is a non-negative
8199 constant that would appear negative in the mode of X,
8200 sign-extend it for use in reg_nonzero_bits because some
8201 machines (maybe most) will actually do the sign-extension
8202 and this is the conservative approach.
8204 ??? For 2.5, try to tighten up the MD files in this regard
8205 instead of this kludge. */
8207 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
8208 && GET_CODE (tem
) == CONST_INT
8210 && 0 != (INTVAL (tem
)
8211 & ((HOST_WIDE_INT
) 1
8212 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8213 tem
= GEN_INT (INTVAL (tem
)
8214 | ((HOST_WIDE_INT
) (-1)
8215 << GET_MODE_BITSIZE (GET_MODE (x
))));
8219 else if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].nonzero_bits
)
8221 unsigned HOST_WIDE_INT mask
= reg_stat
[REGNO (x
)].nonzero_bits
;
8223 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
8224 /* We don't know anything about the upper bits. */
8225 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8232 /* Return the number of bits at the high-order end of X that are known to
8233 be equal to the sign bit. X will be used in mode MODE; if MODE is
8234 VOIDmode, X will be used in its own mode. The returned value will always
8235 be between 1 and the number of bits in MODE. */
8238 reg_num_sign_bit_copies_for_combine (rtx x
, enum machine_mode mode
,
8239 rtx known_x ATTRIBUTE_UNUSED
,
8240 enum machine_mode known_mode
8242 unsigned int known_ret ATTRIBUTE_UNUSED
,
8243 unsigned int *result
)
8247 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8248 && reg_stat
[REGNO (x
)].last_set_mode
== mode
8249 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8250 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8251 && REG_N_SETS (REGNO (x
)) == 1
8252 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8254 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8256 *result
= reg_stat
[REGNO (x
)].last_set_sign_bit_copies
;
8260 tem
= get_last_value (x
);
8264 if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].sign_bit_copies
!= 0
8265 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
8266 *result
= reg_stat
[REGNO (x
)].sign_bit_copies
;
8271 /* Return the number of "extended" bits there are in X, when interpreted
8272 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8273 unsigned quantities, this is the number of high-order zero bits.
8274 For signed quantities, this is the number of copies of the sign bit
8275 minus 1. In both case, this function returns the number of "spare"
8276 bits. For example, if two quantities for which this function returns
8277 at least 1 are added, the addition is known not to overflow.
8279 This function will always return 0 unless called during combine, which
8280 implies that it must be called from a define_split. */
8283 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8285 if (nonzero_sign_valid
== 0)
8289 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8290 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8291 - floor_log2 (nonzero_bits (x
, mode
)))
8293 : num_sign_bit_copies (x
, mode
) - 1);
8296 /* This function is called from `simplify_shift_const' to merge two
8297 outer operations. Specifically, we have already found that we need
8298 to perform operation *POP0 with constant *PCONST0 at the outermost
8299 position. We would now like to also perform OP1 with constant CONST1
8300 (with *POP0 being done last).
8302 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8303 the resulting operation. *PCOMP_P is set to 1 if we would need to
8304 complement the innermost operand, otherwise it is unchanged.
8306 MODE is the mode in which the operation will be done. No bits outside
8307 the width of this mode matter. It is assumed that the width of this mode
8308 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8310 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8311 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8312 result is simply *PCONST0.
8314 If the resulting operation cannot be expressed as one operation, we
8315 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8318 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8320 enum rtx_code op0
= *pop0
;
8321 HOST_WIDE_INT const0
= *pconst0
;
8323 const0
&= GET_MODE_MASK (mode
);
8324 const1
&= GET_MODE_MASK (mode
);
8326 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8330 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8333 if (op1
== UNKNOWN
|| op0
== SET
)
8336 else if (op0
== UNKNOWN
)
8337 op0
= op1
, const0
= const1
;
8339 else if (op0
== op1
)
8363 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8364 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8367 /* If the two constants aren't the same, we can't do anything. The
8368 remaining six cases can all be done. */
8369 else if (const0
!= const1
)
8377 /* (a & b) | b == b */
8379 else /* op1 == XOR */
8380 /* (a ^ b) | b == a | b */
8386 /* (a & b) ^ b == (~a) & b */
8387 op0
= AND
, *pcomp_p
= 1;
8388 else /* op1 == IOR */
8389 /* (a | b) ^ b == a & ~b */
8390 op0
= AND
, const0
= ~const0
;
8395 /* (a | b) & b == b */
8397 else /* op1 == XOR */
8398 /* (a ^ b) & b) == (~a) & b */
8405 /* Check for NO-OP cases. */
8406 const0
&= GET_MODE_MASK (mode
);
8408 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8410 else if (const0
== 0 && op0
== AND
)
8412 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8416 /* ??? Slightly redundant with the above mask, but not entirely.
8417 Moving this above means we'd have to sign-extend the mode mask
8418 for the final test. */
8419 const0
= trunc_int_for_mode (const0
, mode
);
8427 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8428 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8429 that we started with.
8431 The shift is normally computed in the widest mode we find in VAROP, as
8432 long as it isn't a different number of words than RESULT_MODE. Exceptions
8433 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8436 simplify_shift_const (rtx x
, enum rtx_code code
,
8437 enum machine_mode result_mode
, rtx varop
,
8440 enum rtx_code orig_code
= code
;
8443 enum machine_mode mode
= result_mode
;
8444 enum machine_mode shift_mode
, tmode
;
8445 unsigned int mode_words
8446 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8447 /* We form (outer_op (code varop count) (outer_const)). */
8448 enum rtx_code outer_op
= UNKNOWN
;
8449 HOST_WIDE_INT outer_const
= 0;
8451 int complement_p
= 0;
8454 /* Make sure and truncate the "natural" shift on the way in. We don't
8455 want to do this inside the loop as it makes it more difficult to
8457 if (SHIFT_COUNT_TRUNCATED
)
8458 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
8460 /* If we were given an invalid count, don't do anything except exactly
8461 what was requested. */
8463 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
8468 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
8473 /* Unless one of the branches of the `if' in this loop does a `continue',
8474 we will `break' the loop after the `if'. */
8478 /* If we have an operand of (clobber (const_int 0)), just return that
8480 if (GET_CODE (varop
) == CLOBBER
)
8483 /* If we discovered we had to complement VAROP, leave. Making a NOT
8484 here would cause an infinite loop. */
8488 /* Convert ROTATERT to ROTATE. */
8489 if (code
== ROTATERT
)
8491 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
8493 if (VECTOR_MODE_P (result_mode
))
8494 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
8496 count
= bitsize
- count
;
8499 /* We need to determine what mode we will do the shift in. If the
8500 shift is a right shift or a ROTATE, we must always do it in the mode
8501 it was originally done in. Otherwise, we can do it in MODE, the
8502 widest mode encountered. */
8504 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8505 ? result_mode
: mode
);
8507 /* Handle cases where the count is greater than the size of the mode
8508 minus 1. For ASHIFT, use the size minus one as the count (this can
8509 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8510 take the count modulo the size. For other shifts, the result is
8513 Since these shifts are being produced by the compiler by combining
8514 multiple operations, each of which are defined, we know what the
8515 result is supposed to be. */
8517 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
8519 if (code
== ASHIFTRT
)
8520 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8521 else if (code
== ROTATE
|| code
== ROTATERT
)
8522 count
%= GET_MODE_BITSIZE (shift_mode
);
8525 /* We can't simply return zero because there may be an
8533 /* An arithmetic right shift of a quantity known to be -1 or 0
8535 if (code
== ASHIFTRT
8536 && (num_sign_bit_copies (varop
, shift_mode
)
8537 == GET_MODE_BITSIZE (shift_mode
)))
8543 /* If we are doing an arithmetic right shift and discarding all but
8544 the sign bit copies, this is equivalent to doing a shift by the
8545 bitsize minus one. Convert it into that shift because it will often
8546 allow other simplifications. */
8548 if (code
== ASHIFTRT
8549 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8550 >= GET_MODE_BITSIZE (shift_mode
)))
8551 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8553 /* We simplify the tests below and elsewhere by converting
8554 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8555 `make_compound_operation' will convert it to an ASHIFTRT for
8556 those machines (such as VAX) that don't have an LSHIFTRT. */
8557 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8559 && ((nonzero_bits (varop
, shift_mode
)
8560 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8564 if (code
== LSHIFTRT
8565 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8566 && !(nonzero_bits (varop
, shift_mode
) >> count
))
8569 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8570 && !((nonzero_bits (varop
, shift_mode
) << count
)
8571 & GET_MODE_MASK (shift_mode
)))
8574 switch (GET_CODE (varop
))
8580 new = expand_compound_operation (varop
);
8589 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8590 minus the width of a smaller mode, we can do this with a
8591 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8592 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8593 && ! mode_dependent_address_p (XEXP (varop
, 0))
8594 && ! MEM_VOLATILE_P (varop
)
8595 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8596 MODE_INT
, 1)) != BLKmode
)
8598 new = adjust_address_nv (varop
, tmode
,
8599 BYTES_BIG_ENDIAN
? 0
8600 : count
/ BITS_PER_UNIT
);
8602 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8603 : ZERO_EXTEND
, mode
, new);
8610 /* Similar to the case above, except that we can only do this if
8611 the resulting mode is the same as that of the underlying
8612 MEM and adjust the address depending on the *bits* endianness
8613 because of the way that bit-field extract insns are defined. */
8614 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8615 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8616 MODE_INT
, 1)) != BLKmode
8617 && tmode
== GET_MODE (XEXP (varop
, 0)))
8619 if (BITS_BIG_ENDIAN
)
8620 new = XEXP (varop
, 0);
8623 new = copy_rtx (XEXP (varop
, 0));
8624 SUBST (XEXP (new, 0),
8625 plus_constant (XEXP (new, 0),
8626 count
/ BITS_PER_UNIT
));
8629 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8630 : ZERO_EXTEND
, mode
, new);
8637 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8638 the same number of words as what we've seen so far. Then store
8639 the widest mode in MODE. */
8640 if (subreg_lowpart_p (varop
)
8641 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8642 > GET_MODE_SIZE (GET_MODE (varop
)))
8643 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8644 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
8647 varop
= SUBREG_REG (varop
);
8648 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
8649 mode
= GET_MODE (varop
);
8655 /* Some machines use MULT instead of ASHIFT because MULT
8656 is cheaper. But it is still better on those machines to
8657 merge two shifts into one. */
8658 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8659 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8662 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
8663 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
8669 /* Similar, for when divides are cheaper. */
8670 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8671 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8674 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
8675 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
8681 /* If we are extracting just the sign bit of an arithmetic
8682 right shift, that shift is not needed. However, the sign
8683 bit of a wider mode may be different from what would be
8684 interpreted as the sign bit in a narrower mode, so, if
8685 the result is narrower, don't discard the shift. */
8686 if (code
== LSHIFTRT
8687 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8688 && (GET_MODE_BITSIZE (result_mode
)
8689 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
8691 varop
= XEXP (varop
, 0);
8695 /* ... fall through ... */
8700 /* Here we have two nested shifts. The result is usually the
8701 AND of a new shift with a mask. We compute the result below. */
8702 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8703 && INTVAL (XEXP (varop
, 1)) >= 0
8704 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
8705 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8706 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8708 enum rtx_code first_code
= GET_CODE (varop
);
8709 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
8710 unsigned HOST_WIDE_INT mask
;
8713 /* We have one common special case. We can't do any merging if
8714 the inner code is an ASHIFTRT of a smaller mode. However, if
8715 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8716 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8717 we can convert it to
8718 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8719 This simplifies certain SIGN_EXTEND operations. */
8720 if (code
== ASHIFT
&& first_code
== ASHIFTRT
8721 && count
== (unsigned int)
8722 (GET_MODE_BITSIZE (result_mode
)
8723 - GET_MODE_BITSIZE (GET_MODE (varop
))))
8725 /* C3 has the low-order C1 bits zero. */
8727 mask
= (GET_MODE_MASK (mode
)
8728 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
8730 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
8731 XEXP (varop
, 0), mask
);
8732 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
8734 count
= first_count
;
8739 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8740 than C1 high-order bits equal to the sign bit, we can convert
8741 this to either an ASHIFT or an ASHIFTRT depending on the
8744 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8746 if (code
== ASHIFTRT
&& first_code
== ASHIFT
8747 && GET_MODE (varop
) == shift_mode
8748 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
8751 varop
= XEXP (varop
, 0);
8753 signed_count
= count
- first_count
;
8754 if (signed_count
< 0)
8755 count
= -signed_count
, code
= ASHIFT
;
8757 count
= signed_count
;
8762 /* There are some cases we can't do. If CODE is ASHIFTRT,
8763 we can only do this if FIRST_CODE is also ASHIFTRT.
8765 We can't do the case when CODE is ROTATE and FIRST_CODE is
8768 If the mode of this shift is not the mode of the outer shift,
8769 we can't do this if either shift is a right shift or ROTATE.
8771 Finally, we can't do any of these if the mode is too wide
8772 unless the codes are the same.
8774 Handle the case where the shift codes are the same
8777 if (code
== first_code
)
8779 if (GET_MODE (varop
) != result_mode
8780 && (code
== ASHIFTRT
|| code
== LSHIFTRT
8784 count
+= first_count
;
8785 varop
= XEXP (varop
, 0);
8789 if (code
== ASHIFTRT
8790 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
8791 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
8792 || (GET_MODE (varop
) != result_mode
8793 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
8794 || first_code
== ROTATE
8795 || code
== ROTATE
)))
8798 /* To compute the mask to apply after the shift, shift the
8799 nonzero bits of the inner shift the same way the
8800 outer shift will. */
8802 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
8805 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
8808 /* Give up if we can't compute an outer operation to use. */
8810 || GET_CODE (mask_rtx
) != CONST_INT
8811 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
8813 result_mode
, &complement_p
))
8816 /* If the shifts are in the same direction, we add the
8817 counts. Otherwise, we subtract them. */
8818 signed_count
= count
;
8819 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8820 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
8821 signed_count
+= first_count
;
8823 signed_count
-= first_count
;
8825 /* If COUNT is positive, the new shift is usually CODE,
8826 except for the two exceptions below, in which case it is
8827 FIRST_CODE. If the count is negative, FIRST_CODE should
8829 if (signed_count
> 0
8830 && ((first_code
== ROTATE
&& code
== ASHIFT
)
8831 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
8832 code
= first_code
, count
= signed_count
;
8833 else if (signed_count
< 0)
8834 code
= first_code
, count
= -signed_count
;
8836 count
= signed_count
;
8838 varop
= XEXP (varop
, 0);
8842 /* If we have (A << B << C) for any shift, we can convert this to
8843 (A << C << B). This wins if A is a constant. Only try this if
8844 B is not a constant. */
8846 else if (GET_CODE (varop
) == code
8847 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
8849 = simplify_binary_operation (code
, mode
,
8853 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
8860 /* Make this fit the case below. */
8861 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
8862 GEN_INT (GET_MODE_MASK (mode
)));
8868 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8869 with C the size of VAROP - 1 and the shift is logical if
8870 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8871 we have an (le X 0) operation. If we have an arithmetic shift
8872 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8873 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8875 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
8876 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
8877 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8878 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
8879 && count
== (unsigned int)
8880 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
8881 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
8884 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
8887 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
8888 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
8893 /* If we have (shift (logical)), move the logical to the outside
8894 to allow it to possibly combine with another logical and the
8895 shift to combine with another shift. This also canonicalizes to
8896 what a ZERO_EXTRACT looks like. Also, some machines have
8897 (and (shift)) insns. */
8899 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8900 /* We can't do this if we have (ashiftrt (xor)) and the
8901 constant has its sign bit set in shift_mode. */
8902 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
8903 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
8905 && (new = simplify_binary_operation (code
, result_mode
,
8907 GEN_INT (count
))) != 0
8908 && GET_CODE (new) == CONST_INT
8909 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
8910 INTVAL (new), result_mode
, &complement_p
))
8912 varop
= XEXP (varop
, 0);
8916 /* If we can't do that, try to simplify the shift in each arm of the
8917 logical expression, make a new logical expression, and apply
8918 the inverse distributive law. This also can't be done
8919 for some (ashiftrt (xor)). */
8920 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8921 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
8922 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
8925 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
8926 XEXP (varop
, 0), count
);
8927 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
8928 XEXP (varop
, 1), count
);
8930 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
8931 varop
= apply_distributive_law (varop
);
8939 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8940 says that the sign bit can be tested, FOO has mode MODE, C is
8941 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8942 that may be nonzero. */
8943 if (code
== LSHIFTRT
8944 && XEXP (varop
, 1) == const0_rtx
8945 && GET_MODE (XEXP (varop
, 0)) == result_mode
8946 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8947 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8948 && ((STORE_FLAG_VALUE
8949 & ((HOST_WIDE_INT
) 1
8950 < (GET_MODE_BITSIZE (result_mode
) - 1))))
8951 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
8952 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
8953 (HOST_WIDE_INT
) 1, result_mode
,
8956 varop
= XEXP (varop
, 0);
8963 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8964 than the number of bits in the mode is equivalent to A. */
8965 if (code
== LSHIFTRT
8966 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8967 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
8969 varop
= XEXP (varop
, 0);
8974 /* NEG commutes with ASHIFT since it is multiplication. Move the
8975 NEG outside to allow shifts to combine. */
8977 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
8978 (HOST_WIDE_INT
) 0, result_mode
,
8981 varop
= XEXP (varop
, 0);
8987 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8988 is one less than the number of bits in the mode is
8989 equivalent to (xor A 1). */
8990 if (code
== LSHIFTRT
8991 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8992 && XEXP (varop
, 1) == constm1_rtx
8993 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
8994 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
8995 (HOST_WIDE_INT
) 1, result_mode
,
8999 varop
= XEXP (varop
, 0);
9003 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9004 that might be nonzero in BAR are those being shifted out and those
9005 bits are known zero in FOO, we can replace the PLUS with FOO.
9006 Similarly in the other operand order. This code occurs when
9007 we are computing the size of a variable-size array. */
9009 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9010 && count
< HOST_BITS_PER_WIDE_INT
9011 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9012 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9013 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9015 varop
= XEXP (varop
, 0);
9018 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9019 && count
< HOST_BITS_PER_WIDE_INT
9020 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9021 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9023 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9024 & nonzero_bits (XEXP (varop
, 1),
9027 varop
= XEXP (varop
, 1);
9031 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9033 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9034 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9036 GEN_INT (count
))) != 0
9037 && GET_CODE (new) == CONST_INT
9038 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9039 INTVAL (new), result_mode
, &complement_p
))
9041 varop
= XEXP (varop
, 0);
9045 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9046 signbit', and attempt to change the PLUS to an XOR and move it to
9047 the outer operation as is done above in the AND/IOR/XOR case
9048 leg for shift(logical). See details in logical handling above
9049 for reasoning in doing so. */
9050 if (code
== LSHIFTRT
9051 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9052 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
9053 && (new = simplify_binary_operation (code
, result_mode
,
9055 GEN_INT (count
))) != 0
9056 && GET_CODE (new) == CONST_INT
9057 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9058 INTVAL (new), result_mode
, &complement_p
))
9060 varop
= XEXP (varop
, 0);
9067 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9068 with C the size of VAROP - 1 and the shift is logical if
9069 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9070 we have a (gt X 0) operation. If the shift is arithmetic with
9071 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9072 we have a (neg (gt X 0)) operation. */
9074 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9075 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9076 && count
== (unsigned int)
9077 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9078 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9079 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9080 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9082 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9085 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9088 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9089 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9096 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9097 if the truncate does not affect the value. */
9098 if (code
== LSHIFTRT
9099 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9100 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9101 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9102 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9103 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9105 rtx varop_inner
= XEXP (varop
, 0);
9108 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9109 XEXP (varop_inner
, 0),
9111 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9112 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9125 /* We need to determine what mode to do the shift in. If the shift is
9126 a right shift or ROTATE, we must always do it in the mode it was
9127 originally done in. Otherwise, we can do it in MODE, the widest mode
9128 encountered. The code we care about is that of the shift that will
9129 actually be done, not the shift that was originally requested. */
9131 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9132 ? result_mode
: mode
);
9134 /* We have now finished analyzing the shift. The result should be
9135 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9136 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9137 to the result of the shift. OUTER_CONST is the relevant constant,
9138 but we must turn off all bits turned off in the shift.
9140 If we were passed a value for X, see if we can use any pieces of
9141 it. If not, make new rtx. */
9143 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == RTX_BIN_ARITH
9144 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9145 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9146 const_rtx
= XEXP (x
, 1);
9148 const_rtx
= GEN_INT (count
);
9150 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9151 && GET_MODE (XEXP (x
, 0)) == shift_mode
9152 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9153 varop
= XEXP (x
, 0);
9154 else if (GET_MODE (varop
) != shift_mode
)
9155 varop
= gen_lowpart (shift_mode
, varop
);
9157 /* If we can't make the SUBREG, try to return what we were given. */
9158 if (GET_CODE (varop
) == CLOBBER
)
9159 return x
? x
: varop
;
9161 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9165 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9167 /* If we have an outer operation and we just made a shift, it is
9168 possible that we could have simplified the shift were it not
9169 for the outer operation. So try to do the simplification
9172 if (outer_op
!= UNKNOWN
&& GET_CODE (x
) == code
9173 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9174 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9175 INTVAL (XEXP (x
, 1)));
9177 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9178 turn off all the bits that the shift would have turned off. */
9179 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9180 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9181 GET_MODE_MASK (result_mode
) >> orig_count
);
9183 /* Do the remainder of the processing in RESULT_MODE. */
9184 x
= gen_lowpart (result_mode
, x
);
9186 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9189 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9191 if (outer_op
!= UNKNOWN
)
9193 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9194 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9196 if (outer_op
== AND
)
9197 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9198 else if (outer_op
== SET
)
9199 /* This means that we have determined that the result is
9200 equivalent to a constant. This should be rare. */
9201 x
= GEN_INT (outer_const
);
9202 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
9203 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9205 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9211 /* Like recog, but we receive the address of a pointer to a new pattern.
9212 We try to match the rtx that the pointer points to.
9213 If that fails, we may try to modify or replace the pattern,
9214 storing the replacement into the same pointer object.
9216 Modifications include deletion or addition of CLOBBERs.
9218 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9219 the CLOBBERs are placed.
9221 The value is the final insn code from the pattern ultimately matched,
9225 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9228 int insn_code_number
;
9229 int num_clobbers_to_add
= 0;
9232 rtx old_notes
, old_pat
;
9234 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9235 we use to indicate that something didn't match. If we find such a
9236 thing, force rejection. */
9237 if (GET_CODE (pat
) == PARALLEL
)
9238 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9239 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9240 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9243 old_pat
= PATTERN (insn
);
9244 old_notes
= REG_NOTES (insn
);
9245 PATTERN (insn
) = pat
;
9246 REG_NOTES (insn
) = 0;
9248 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9250 /* If it isn't, there is the possibility that we previously had an insn
9251 that clobbered some register as a side effect, but the combined
9252 insn doesn't need to do that. So try once more without the clobbers
9253 unless this represents an ASM insn. */
9255 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9256 && GET_CODE (pat
) == PARALLEL
)
9260 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9261 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9264 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9268 SUBST_INT (XVECLEN (pat
, 0), pos
);
9271 pat
= XVECEXP (pat
, 0, 0);
9273 PATTERN (insn
) = pat
;
9274 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9276 PATTERN (insn
) = old_pat
;
9277 REG_NOTES (insn
) = old_notes
;
9279 /* Recognize all noop sets, these will be killed by followup pass. */
9280 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9281 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9283 /* If we had any clobbers to add, make a new pattern than contains
9284 them. Then check to make sure that all of them are dead. */
9285 if (num_clobbers_to_add
)
9287 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9288 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9290 + num_clobbers_to_add
)
9291 : num_clobbers_to_add
+ 1));
9293 if (GET_CODE (pat
) == PARALLEL
)
9294 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9295 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9297 XVECEXP (newpat
, 0, 0) = pat
;
9299 add_clobbers (newpat
, insn_code_number
);
9301 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9302 i
< XVECLEN (newpat
, 0); i
++)
9304 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
9305 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9307 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9308 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9316 return insn_code_number
;
9319 /* Like gen_lowpart_general but for use by combine. In combine it
9320 is not possible to create any new pseudoregs. However, it is
9321 safe to create invalid memory addresses, because combine will
9322 try to recognize them and all they will do is make the combine
9325 If for some reason this cannot do its job, an rtx
9326 (clobber (const_int 0)) is returned.
9327 An insn containing that will not be recognized. */
9330 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
9332 enum machine_mode imode
= GET_MODE (x
);
9333 unsigned int osize
= GET_MODE_SIZE (omode
);
9334 unsigned int isize
= GET_MODE_SIZE (imode
);
9340 /* Return identity if this is a CONST or symbolic reference. */
9342 && (GET_CODE (x
) == CONST
9343 || GET_CODE (x
) == SYMBOL_REF
9344 || GET_CODE (x
) == LABEL_REF
))
9347 /* We can only support MODE being wider than a word if X is a
9348 constant integer or has a mode the same size. */
9349 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
9350 && ! ((imode
== VOIDmode
9351 && (GET_CODE (x
) == CONST_INT
9352 || GET_CODE (x
) == CONST_DOUBLE
))
9356 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9357 won't know what to do. So we will strip off the SUBREG here and
9358 process normally. */
9359 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
9363 /* For use in case we fall down into the address adjustments
9364 further below, we need to adjust the known mode and size of
9365 x; imode and isize, since we just adjusted x. */
9366 imode
= GET_MODE (x
);
9371 isize
= GET_MODE_SIZE (imode
);
9374 result
= gen_lowpart_common (omode
, x
);
9376 #ifdef CANNOT_CHANGE_MODE_CLASS
9377 if (result
!= 0 && GET_CODE (result
) == SUBREG
)
9378 record_subregs_of_mode (result
);
9388 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9390 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9393 /* If we want to refer to something bigger than the original memref,
9394 generate a paradoxical subreg instead. That will force a reload
9395 of the original memref X. */
9397 return gen_rtx_SUBREG (omode
, x
, 0);
9399 if (WORDS_BIG_ENDIAN
)
9400 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
9402 /* Adjust the address so that the address-after-the-data is unchanged. */
9403 if (BYTES_BIG_ENDIAN
)
9404 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
9406 return adjust_address_nv (x
, omode
, offset
);
9409 /* If X is a comparison operator, rewrite it in a new mode. This
9410 probably won't match, but may allow further simplifications. */
9411 else if (COMPARISON_P (x
))
9412 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
9414 /* If we couldn't simplify X any other way, just enclose it in a
9415 SUBREG. Normally, this SUBREG won't match, but some patterns may
9416 include an explicit SUBREG or we may simplify it further in combine. */
9422 offset
= subreg_lowpart_offset (omode
, imode
);
9423 if (imode
== VOIDmode
)
9425 imode
= int_mode_for_mode (omode
);
9426 x
= gen_lowpart_common (imode
, x
);
9430 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
9436 return gen_rtx_CLOBBER (imode
, const0_rtx
);
9439 /* These routines make binary and unary operations by first seeing if they
9440 fold; if not, a new expression is allocated. */
9443 gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
, rtx op1
)
9448 if (GET_CODE (op0
) == CLOBBER
)
9450 else if (GET_CODE (op1
) == CLOBBER
)
9453 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
9454 && swap_commutative_operands_p (op0
, op1
))
9455 tem
= op0
, op0
= op1
, op1
= tem
;
9457 if (GET_RTX_CLASS (code
) == RTX_COMPARE
9458 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
9460 enum machine_mode op_mode
= GET_MODE (op0
);
9462 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9463 just (REL_OP X Y). */
9464 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
9466 op1
= XEXP (op0
, 1);
9467 op0
= XEXP (op0
, 0);
9468 op_mode
= GET_MODE (op0
);
9471 if (op_mode
== VOIDmode
)
9472 op_mode
= GET_MODE (op1
);
9473 result
= simplify_relational_operation (code
, mode
, op_mode
, op0
, op1
);
9476 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
9481 /* Put complex operands first and constants second. */
9482 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
9483 && swap_commutative_operands_p (op0
, op1
))
9484 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
9486 /* If we are turning off bits already known off in OP0, we need not do
9488 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
9489 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9490 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
9493 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
9496 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9497 comparison code that will be tested.
9499 The result is a possibly different comparison code to use. *POP0 and
9500 *POP1 may be updated.
9502 It is possible that we might detect that a comparison is either always
9503 true or always false. However, we do not perform general constant
9504 folding in combine, so this knowledge isn't useful. Such tautologies
9505 should have been detected earlier. Hence we ignore all such cases. */
9507 static enum rtx_code
9508 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
9514 enum machine_mode mode
, tmode
;
9516 /* Try a few ways of applying the same transformation to both operands. */
9519 #ifndef WORD_REGISTER_OPERATIONS
9520 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9521 so check specially. */
9522 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9523 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9524 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9525 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9526 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9527 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9528 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9529 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9530 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9531 && XEXP (op0
, 1) == XEXP (op1
, 1)
9532 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
9533 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
9534 && (INTVAL (XEXP (op0
, 1))
9535 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9537 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9539 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9540 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9544 /* If both operands are the same constant shift, see if we can ignore the
9545 shift. We can if the shift is a rotate or if the bits shifted out of
9546 this shift are known to be zero for both inputs and if the type of
9547 comparison is compatible with the shift. */
9548 if (GET_CODE (op0
) == GET_CODE (op1
)
9549 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9550 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9551 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9552 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9553 || (GET_CODE (op0
) == ASHIFTRT
9554 && (code
!= GTU
&& code
!= LTU
9555 && code
!= GEU
&& code
!= LEU
)))
9556 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9557 && INTVAL (XEXP (op0
, 1)) >= 0
9558 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9559 && XEXP (op0
, 1) == XEXP (op1
, 1))
9561 enum machine_mode mode
= GET_MODE (op0
);
9562 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9563 int shift_count
= INTVAL (XEXP (op0
, 1));
9565 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9566 mask
&= (mask
>> shift_count
) << shift_count
;
9567 else if (GET_CODE (op0
) == ASHIFT
)
9568 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9570 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
9571 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
9572 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9577 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9578 SUBREGs are of the same mode, and, in both cases, the AND would
9579 be redundant if the comparison was done in the narrower mode,
9580 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9581 and the operand's possibly nonzero bits are 0xffffff01; in that case
9582 if we only care about QImode, we don't need the AND). This case
9583 occurs if the output mode of an scc insn is not SImode and
9584 STORE_FLAG_VALUE == 1 (e.g., the 386).
9586 Similarly, check for a case where the AND's are ZERO_EXTEND
9587 operations from some narrower mode even though a SUBREG is not
9590 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9591 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9592 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9594 rtx inner_op0
= XEXP (op0
, 0);
9595 rtx inner_op1
= XEXP (op1
, 0);
9596 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9597 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9600 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9601 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9602 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9603 && (GET_MODE (SUBREG_REG (inner_op0
))
9604 == GET_MODE (SUBREG_REG (inner_op1
)))
9605 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9606 <= HOST_BITS_PER_WIDE_INT
)
9607 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9608 GET_MODE (SUBREG_REG (inner_op0
)))))
9609 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9610 GET_MODE (SUBREG_REG (inner_op1
))))))
9612 op0
= SUBREG_REG (inner_op0
);
9613 op1
= SUBREG_REG (inner_op1
);
9615 /* The resulting comparison is always unsigned since we masked
9616 off the original sign bit. */
9617 code
= unsigned_condition (code
);
9623 for (tmode
= GET_CLASS_NARROWEST_MODE
9624 (GET_MODE_CLASS (GET_MODE (op0
)));
9625 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9626 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9628 op0
= gen_lowpart (tmode
, inner_op0
);
9629 op1
= gen_lowpart (tmode
, inner_op1
);
9630 code
= unsigned_condition (code
);
9639 /* If both operands are NOT, we can strip off the outer operation
9640 and adjust the comparison code for swapped operands; similarly for
9641 NEG, except that this must be an equality comparison. */
9642 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9643 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9644 && (code
== EQ
|| code
== NE
)))
9645 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9651 /* If the first operand is a constant, swap the operands and adjust the
9652 comparison code appropriately, but don't do this if the second operand
9653 is already a constant integer. */
9654 if (swap_commutative_operands_p (op0
, op1
))
9656 tem
= op0
, op0
= op1
, op1
= tem
;
9657 code
= swap_condition (code
);
9660 /* We now enter a loop during which we will try to simplify the comparison.
9661 For the most part, we only are concerned with comparisons with zero,
9662 but some things may really be comparisons with zero but not start
9663 out looking that way. */
9665 while (GET_CODE (op1
) == CONST_INT
)
9667 enum machine_mode mode
= GET_MODE (op0
);
9668 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
9669 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9670 int equality_comparison_p
;
9671 int sign_bit_comparison_p
;
9672 int unsigned_comparison_p
;
9673 HOST_WIDE_INT const_op
;
9675 /* We only want to handle integral modes. This catches VOIDmode,
9676 CCmode, and the floating-point modes. An exception is that we
9677 can handle VOIDmode if OP0 is a COMPARE or a comparison
9680 if (GET_MODE_CLASS (mode
) != MODE_INT
9681 && ! (mode
== VOIDmode
9682 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
9685 /* Get the constant we are comparing against and turn off all bits
9686 not on in our mode. */
9687 const_op
= INTVAL (op1
);
9688 if (mode
!= VOIDmode
)
9689 const_op
= trunc_int_for_mode (const_op
, mode
);
9690 op1
= GEN_INT (const_op
);
9692 /* If we are comparing against a constant power of two and the value
9693 being compared can only have that single bit nonzero (e.g., it was
9694 `and'ed with that bit), we can replace this with a comparison
9697 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
9698 || code
== LT
|| code
== LTU
)
9699 && mode_width
<= HOST_BITS_PER_WIDE_INT
9700 && exact_log2 (const_op
) >= 0
9701 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
9703 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
9704 op1
= const0_rtx
, const_op
= 0;
9707 /* Similarly, if we are comparing a value known to be either -1 or
9708 0 with -1, change it to the opposite comparison against zero. */
9711 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
9712 || code
== GEU
|| code
== LTU
)
9713 && num_sign_bit_copies (op0
, mode
) == mode_width
)
9715 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
9716 op1
= const0_rtx
, const_op
= 0;
9719 /* Do some canonicalizations based on the comparison code. We prefer
9720 comparisons against zero and then prefer equality comparisons.
9721 If we can reduce the size of a constant, we will do that too. */
9726 /* < C is equivalent to <= (C - 1) */
9730 op1
= GEN_INT (const_op
);
9732 /* ... fall through to LE case below. */
9738 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9742 op1
= GEN_INT (const_op
);
9746 /* If we are doing a <= 0 comparison on a value known to have
9747 a zero sign bit, we can replace this with == 0. */
9748 else if (const_op
== 0
9749 && mode_width
<= HOST_BITS_PER_WIDE_INT
9750 && (nonzero_bits (op0
, mode
)
9751 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9756 /* >= C is equivalent to > (C - 1). */
9760 op1
= GEN_INT (const_op
);
9762 /* ... fall through to GT below. */
9768 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9772 op1
= GEN_INT (const_op
);
9776 /* If we are doing a > 0 comparison on a value known to have
9777 a zero sign bit, we can replace this with != 0. */
9778 else if (const_op
== 0
9779 && mode_width
<= HOST_BITS_PER_WIDE_INT
9780 && (nonzero_bits (op0
, mode
)
9781 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9786 /* < C is equivalent to <= (C - 1). */
9790 op1
= GEN_INT (const_op
);
9792 /* ... fall through ... */
9795 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9796 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9797 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9799 const_op
= 0, op1
= const0_rtx
;
9807 /* unsigned <= 0 is equivalent to == 0 */
9811 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9812 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9813 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9815 const_op
= 0, op1
= const0_rtx
;
9821 /* >= C is equivalent to > (C - 1). */
9825 op1
= GEN_INT (const_op
);
9827 /* ... fall through ... */
9830 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9831 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9832 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9834 const_op
= 0, op1
= const0_rtx
;
9842 /* unsigned > 0 is equivalent to != 0 */
9846 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9847 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9848 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9850 const_op
= 0, op1
= const0_rtx
;
9859 /* Compute some predicates to simplify code below. */
9861 equality_comparison_p
= (code
== EQ
|| code
== NE
);
9862 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
9863 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
9866 /* If this is a sign bit comparison and we can do arithmetic in
9867 MODE, say that we will only be needing the sign bit of OP0. */
9868 if (sign_bit_comparison_p
9869 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9870 op0
= force_to_mode (op0
, mode
,
9872 << (GET_MODE_BITSIZE (mode
) - 1)),
9875 /* Now try cases based on the opcode of OP0. If none of the cases
9876 does a "continue", we exit this loop immediately after the
9879 switch (GET_CODE (op0
))
9882 /* If we are extracting a single bit from a variable position in
9883 a constant that has only a single bit set and are comparing it
9884 with zero, we can convert this into an equality comparison
9885 between the position and the location of the single bit. */
9886 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9887 have already reduced the shift count modulo the word size. */
9888 if (!SHIFT_COUNT_TRUNCATED
9889 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
9890 && XEXP (op0
, 1) == const1_rtx
9891 && equality_comparison_p
&& const_op
== 0
9892 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
9894 if (BITS_BIG_ENDIAN
)
9896 enum machine_mode new_mode
9897 = mode_for_extraction (EP_extzv
, 1);
9898 if (new_mode
== MAX_MACHINE_MODE
)
9899 i
= BITS_PER_WORD
- 1 - i
;
9903 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
9907 op0
= XEXP (op0
, 2);
9911 /* Result is nonzero iff shift count is equal to I. */
9912 code
= reverse_condition (code
);
9916 /* ... fall through ... */
9919 tem
= expand_compound_operation (op0
);
9928 /* If testing for equality, we can take the NOT of the constant. */
9929 if (equality_comparison_p
9930 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
9932 op0
= XEXP (op0
, 0);
9937 /* If just looking at the sign bit, reverse the sense of the
9939 if (sign_bit_comparison_p
)
9941 op0
= XEXP (op0
, 0);
9942 code
= (code
== GE
? LT
: GE
);
9948 /* If testing for equality, we can take the NEG of the constant. */
9949 if (equality_comparison_p
9950 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
9952 op0
= XEXP (op0
, 0);
9957 /* The remaining cases only apply to comparisons with zero. */
9961 /* When X is ABS or is known positive,
9962 (neg X) is < 0 if and only if X != 0. */
9964 if (sign_bit_comparison_p
9965 && (GET_CODE (XEXP (op0
, 0)) == ABS
9966 || (mode_width
<= HOST_BITS_PER_WIDE_INT
9967 && (nonzero_bits (XEXP (op0
, 0), mode
)
9968 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
9970 op0
= XEXP (op0
, 0);
9971 code
= (code
== LT
? NE
: EQ
);
9975 /* If we have NEG of something whose two high-order bits are the
9976 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9977 if (num_sign_bit_copies (op0
, mode
) >= 2)
9979 op0
= XEXP (op0
, 0);
9980 code
= swap_condition (code
);
9986 /* If we are testing equality and our count is a constant, we
9987 can perform the inverse operation on our RHS. */
9988 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
9989 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
9990 op1
, XEXP (op0
, 1))) != 0)
9992 op0
= XEXP (op0
, 0);
9997 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9998 a particular bit. Convert it to an AND of a constant of that
9999 bit. This will be converted into a ZERO_EXTRACT. */
10000 if (const_op
== 0 && sign_bit_comparison_p
10001 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10002 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10004 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10007 - INTVAL (XEXP (op0
, 1)))));
10008 code
= (code
== LT
? NE
: EQ
);
10012 /* Fall through. */
10015 /* ABS is ignorable inside an equality comparison with zero. */
10016 if (const_op
== 0 && equality_comparison_p
)
10018 op0
= XEXP (op0
, 0);
10024 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10025 to (compare FOO CONST) if CONST fits in FOO's mode and we
10026 are either testing inequality or have an unsigned comparison
10027 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10028 if (! unsigned_comparison_p
10029 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10030 <= HOST_BITS_PER_WIDE_INT
)
10031 && ((unsigned HOST_WIDE_INT
) const_op
10032 < (((unsigned HOST_WIDE_INT
) 1
10033 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10035 op0
= XEXP (op0
, 0);
10041 /* Check for the case where we are comparing A - C1 with C2, that is
10043 (subreg:MODE (plus (A) (-C1))) op (C2)
10045 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10046 comparison in the wider mode. One of the following two conditions
10047 must be true in order for this to be valid:
10049 1. The mode extension results in the same bit pattern being added
10050 on both sides and the comparison is equality or unsigned. As
10051 C2 has been truncated to fit in MODE, the pattern can only be
10054 2. The mode extension results in the sign bit being copied on
10057 The difficulty here is that we have predicates for A but not for
10058 (A - C1) so we need to check that C1 is within proper bounds so
10059 as to perturbate A as little as possible. */
10061 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10062 && subreg_lowpart_p (op0
)
10063 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) > mode_width
10064 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10065 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
)
10067 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
10068 rtx a
= XEXP (SUBREG_REG (op0
), 0);
10069 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
10072 && (unsigned HOST_WIDE_INT
) c1
10073 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
10074 && (equality_comparison_p
|| unsigned_comparison_p
)
10075 /* (A - C1) zero-extends if it is positive and sign-extends
10076 if it is negative, C2 both zero- and sign-extends. */
10077 && ((0 == (nonzero_bits (a
, inner_mode
)
10078 & ~GET_MODE_MASK (mode
))
10080 /* (A - C1) sign-extends if it is positive and 1-extends
10081 if it is negative, C2 both sign- and 1-extends. */
10082 || (num_sign_bit_copies (a
, inner_mode
)
10083 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10086 || ((unsigned HOST_WIDE_INT
) c1
10087 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
10088 /* (A - C1) always sign-extends, like C2. */
10089 && num_sign_bit_copies (a
, inner_mode
)
10090 > (unsigned int) (GET_MODE_BITSIZE (inner_mode
)
10091 - mode_width
- 1)))
10093 op0
= SUBREG_REG (op0
);
10098 /* If the inner mode is narrower and we are extracting the low part,
10099 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10100 if (subreg_lowpart_p (op0
)
10101 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10102 /* Fall through */ ;
10106 /* ... fall through ... */
10109 if ((unsigned_comparison_p
|| equality_comparison_p
)
10110 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10111 <= HOST_BITS_PER_WIDE_INT
)
10112 && ((unsigned HOST_WIDE_INT
) const_op
10113 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10115 op0
= XEXP (op0
, 0);
10121 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10122 this for equality comparisons due to pathological cases involving
10124 if (equality_comparison_p
10125 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10126 op1
, XEXP (op0
, 1))))
10128 op0
= XEXP (op0
, 0);
10133 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10134 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10135 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10137 op0
= XEXP (XEXP (op0
, 0), 0);
10138 code
= (code
== LT
? EQ
: NE
);
10144 /* We used to optimize signed comparisons against zero, but that
10145 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10146 arrive here as equality comparisons, or (GEU, LTU) are
10147 optimized away. No need to special-case them. */
10149 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10150 (eq B (minus A C)), whichever simplifies. We can only do
10151 this for equality comparisons due to pathological cases involving
10153 if (equality_comparison_p
10154 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10155 XEXP (op0
, 1), op1
)))
10157 op0
= XEXP (op0
, 0);
10162 if (equality_comparison_p
10163 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10164 XEXP (op0
, 0), op1
)))
10166 op0
= XEXP (op0
, 1);
10171 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10172 of bits in X minus 1, is one iff X > 0. */
10173 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10174 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10175 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10177 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10179 op0
= XEXP (op0
, 1);
10180 code
= (code
== GE
? LE
: GT
);
10186 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10187 if C is zero or B is a constant. */
10188 if (equality_comparison_p
10189 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10190 XEXP (op0
, 1), op1
)))
10192 op0
= XEXP (op0
, 0);
10199 case UNEQ
: case LTGT
:
10200 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10201 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10202 case UNORDERED
: case ORDERED
:
10203 /* We can't do anything if OP0 is a condition code value, rather
10204 than an actual data value. */
10206 || CC0_P (XEXP (op0
, 0))
10207 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10210 /* Get the two operands being compared. */
10211 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10212 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10214 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10216 /* Check for the cases where we simply want the result of the
10217 earlier test or the opposite of that result. */
10218 if (code
== NE
|| code
== EQ
10219 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10220 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10221 && (STORE_FLAG_VALUE
10222 & (((HOST_WIDE_INT
) 1
10223 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10224 && (code
== LT
|| code
== GE
)))
10226 enum rtx_code new_code
;
10227 if (code
== LT
|| code
== NE
)
10228 new_code
= GET_CODE (op0
);
10230 new_code
= combine_reversed_comparison_code (op0
);
10232 if (new_code
!= UNKNOWN
)
10243 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10245 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10246 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10247 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10249 op0
= XEXP (op0
, 1);
10250 code
= (code
== GE
? GT
: LE
);
10256 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10257 will be converted to a ZERO_EXTRACT later. */
10258 if (const_op
== 0 && equality_comparison_p
10259 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10260 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10262 op0
= simplify_and_const_int
10263 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10265 XEXP (XEXP (op0
, 0), 1)),
10266 (HOST_WIDE_INT
) 1);
10270 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10271 zero and X is a comparison and C1 and C2 describe only bits set
10272 in STORE_FLAG_VALUE, we can compare with X. */
10273 if (const_op
== 0 && equality_comparison_p
10274 && mode_width
<= HOST_BITS_PER_WIDE_INT
10275 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10276 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10277 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10278 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10279 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10281 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10282 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10283 if ((~STORE_FLAG_VALUE
& mask
) == 0
10284 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
10285 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10286 && COMPARISON_P (tem
))))
10288 op0
= XEXP (XEXP (op0
, 0), 0);
10293 /* If we are doing an equality comparison of an AND of a bit equal
10294 to the sign bit, replace this with a LT or GE comparison of
10295 the underlying value. */
10296 if (equality_comparison_p
10298 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10299 && mode_width
<= HOST_BITS_PER_WIDE_INT
10300 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10301 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10303 op0
= XEXP (op0
, 0);
10304 code
= (code
== EQ
? GE
: LT
);
10308 /* If this AND operation is really a ZERO_EXTEND from a narrower
10309 mode, the constant fits within that mode, and this is either an
10310 equality or unsigned comparison, try to do this comparison in
10311 the narrower mode. */
10312 if ((equality_comparison_p
|| unsigned_comparison_p
)
10313 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10314 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10315 & GET_MODE_MASK (mode
))
10317 && const_op
>> i
== 0
10318 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10320 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10324 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10325 fits in both M1 and M2 and the SUBREG is either paradoxical
10326 or represents the low part, permute the SUBREG and the AND
10328 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10330 unsigned HOST_WIDE_INT c1
;
10331 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10332 /* Require an integral mode, to avoid creating something like
10334 if (SCALAR_INT_MODE_P (tmode
)
10335 /* It is unsafe to commute the AND into the SUBREG if the
10336 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10337 not defined. As originally written the upper bits
10338 have a defined value due to the AND operation.
10339 However, if we commute the AND inside the SUBREG then
10340 they no longer have defined values and the meaning of
10341 the code has been changed. */
10343 #ifdef WORD_REGISTER_OPERATIONS
10344 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10345 && mode_width
<= BITS_PER_WORD
)
10347 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10348 && subreg_lowpart_p (XEXP (op0
, 0))))
10349 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10350 && mode_width
<= HOST_BITS_PER_WIDE_INT
10351 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10352 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10353 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10355 && c1
!= GET_MODE_MASK (tmode
))
10357 op0
= gen_binary (AND
, tmode
,
10358 SUBREG_REG (XEXP (op0
, 0)),
10359 gen_int_mode (c1
, tmode
));
10360 op0
= gen_lowpart (mode
, op0
);
10365 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10366 if (const_op
== 0 && equality_comparison_p
10367 && XEXP (op0
, 1) == const1_rtx
10368 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10370 op0
= simplify_and_const_int
10371 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10372 code
= (code
== NE
? EQ
: NE
);
10376 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10377 (eq (and (lshiftrt X) 1) 0).
10378 Also handle the case where (not X) is expressed using xor. */
10379 if (const_op
== 0 && equality_comparison_p
10380 && XEXP (op0
, 1) == const1_rtx
10381 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
10383 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
10384 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
10386 if (GET_CODE (shift_op
) == NOT
10387 || (GET_CODE (shift_op
) == XOR
10388 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
10389 && GET_CODE (shift_count
) == CONST_INT
10390 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10391 && (INTVAL (XEXP (shift_op
, 1))
10392 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
10394 op0
= simplify_and_const_int
10396 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
10397 (HOST_WIDE_INT
) 1);
10398 code
= (code
== NE
? EQ
: NE
);
10405 /* If we have (compare (ashift FOO N) (const_int C)) and
10406 the high order N bits of FOO (N+1 if an inequality comparison)
10407 are known to be zero, we can do this by comparing FOO with C
10408 shifted right N bits so long as the low-order N bits of C are
10410 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10411 && INTVAL (XEXP (op0
, 1)) >= 0
10412 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10413 < HOST_BITS_PER_WIDE_INT
)
10415 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10416 && mode_width
<= HOST_BITS_PER_WIDE_INT
10417 && (nonzero_bits (XEXP (op0
, 0), mode
)
10418 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10419 + ! equality_comparison_p
))) == 0)
10421 /* We must perform a logical shift, not an arithmetic one,
10422 as we want the top N bits of C to be zero. */
10423 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10425 temp
>>= INTVAL (XEXP (op0
, 1));
10426 op1
= gen_int_mode (temp
, mode
);
10427 op0
= XEXP (op0
, 0);
10431 /* If we are doing a sign bit comparison, it means we are testing
10432 a particular bit. Convert it to the appropriate AND. */
10433 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10434 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10436 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10439 - INTVAL (XEXP (op0
, 1)))));
10440 code
= (code
== LT
? NE
: EQ
);
10444 /* If this an equality comparison with zero and we are shifting
10445 the low bit to the sign bit, we can convert this to an AND of the
10447 if (const_op
== 0 && equality_comparison_p
10448 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10449 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10452 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10453 (HOST_WIDE_INT
) 1);
10459 /* If this is an equality comparison with zero, we can do this
10460 as a logical shift, which might be much simpler. */
10461 if (equality_comparison_p
&& const_op
== 0
10462 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10464 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10466 INTVAL (XEXP (op0
, 1)));
10470 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10471 do the comparison in a narrower mode. */
10472 if (! unsigned_comparison_p
10473 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10474 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10475 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10476 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10477 MODE_INT
, 1)) != BLKmode
10478 && (((unsigned HOST_WIDE_INT
) const_op
10479 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10480 <= GET_MODE_MASK (tmode
)))
10482 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
10486 /* Likewise if OP0 is a PLUS of a sign extension with a
10487 constant, which is usually represented with the PLUS
10488 between the shifts. */
10489 if (! unsigned_comparison_p
10490 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10491 && GET_CODE (XEXP (op0
, 0)) == PLUS
10492 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10493 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10494 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10495 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10496 MODE_INT
, 1)) != BLKmode
10497 && (((unsigned HOST_WIDE_INT
) const_op
10498 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10499 <= GET_MODE_MASK (tmode
)))
10501 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10502 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10503 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
10506 op0
= gen_binary (PLUS
, tmode
,
10507 gen_lowpart (tmode
, inner
),
10512 /* ... fall through ... */
10514 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10515 the low order N bits of FOO are known to be zero, we can do this
10516 by comparing FOO with C shifted left N bits so long as no
10517 overflow occurs. */
10518 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10519 && INTVAL (XEXP (op0
, 1)) >= 0
10520 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10521 && mode_width
<= HOST_BITS_PER_WIDE_INT
10522 && (nonzero_bits (XEXP (op0
, 0), mode
)
10523 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10524 && (((unsigned HOST_WIDE_INT
) const_op
10525 + (GET_CODE (op0
) != LSHIFTRT
10526 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
10529 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
10531 /* If the shift was logical, then we must make the condition
10533 if (GET_CODE (op0
) == LSHIFTRT
)
10534 code
= unsigned_condition (code
);
10536 const_op
<<= INTVAL (XEXP (op0
, 1));
10537 op1
= GEN_INT (const_op
);
10538 op0
= XEXP (op0
, 0);
10542 /* If we are using this shift to extract just the sign bit, we
10543 can replace this with an LT or GE comparison. */
10545 && (equality_comparison_p
|| sign_bit_comparison_p
)
10546 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10547 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10550 op0
= XEXP (op0
, 0);
10551 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10563 /* Now make any compound operations involved in this comparison. Then,
10564 check for an outmost SUBREG on OP0 that is not doing anything or is
10565 paradoxical. The latter transformation must only be performed when
10566 it is known that the "extra" bits will be the same in op0 and op1 or
10567 that they don't matter. There are three cases to consider:
10569 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10570 care bits and we can assume they have any convenient value. So
10571 making the transformation is safe.
10573 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10574 In this case the upper bits of op0 are undefined. We should not make
10575 the simplification in that case as we do not know the contents of
10578 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10579 UNKNOWN. In that case we know those bits are zeros or ones. We must
10580 also be sure that they are the same as the upper bits of op1.
10582 We can never remove a SUBREG for a non-equality comparison because
10583 the sign bit is in a different place in the underlying object. */
10585 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10586 op1
= make_compound_operation (op1
, SET
);
10588 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10589 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10590 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
10591 && (code
== NE
|| code
== EQ
))
10593 if (GET_MODE_SIZE (GET_MODE (op0
))
10594 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
10596 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10598 if (REG_P (SUBREG_REG (op0
)))
10600 op0
= SUBREG_REG (op0
);
10601 op1
= gen_lowpart (GET_MODE (op0
), op1
);
10604 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10605 <= HOST_BITS_PER_WIDE_INT
)
10606 && (nonzero_bits (SUBREG_REG (op0
),
10607 GET_MODE (SUBREG_REG (op0
)))
10608 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10610 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
10612 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10613 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10614 op0
= SUBREG_REG (op0
), op1
= tem
;
10618 /* We now do the opposite procedure: Some machines don't have compare
10619 insns in all modes. If OP0's mode is an integer mode smaller than a
10620 word and we can't do a compare in that mode, see if there is a larger
10621 mode for which we can do the compare. There are a number of cases in
10622 which we can use the wider mode. */
10624 mode
= GET_MODE (op0
);
10625 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10626 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10627 && ! have_insn_for (COMPARE
, mode
))
10628 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10630 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10631 tmode
= GET_MODE_WIDER_MODE (tmode
))
10632 if (have_insn_for (COMPARE
, tmode
))
10636 /* If the only nonzero bits in OP0 and OP1 are those in the
10637 narrower mode and this is an equality or unsigned comparison,
10638 we can use the wider mode. Similarly for sign-extended
10639 values, in which case it is true for all comparisons. */
10640 zero_extended
= ((code
== EQ
|| code
== NE
10641 || code
== GEU
|| code
== GTU
10642 || code
== LEU
|| code
== LTU
)
10643 && (nonzero_bits (op0
, tmode
)
10644 & ~GET_MODE_MASK (mode
)) == 0
10645 && ((GET_CODE (op1
) == CONST_INT
10646 || (nonzero_bits (op1
, tmode
)
10647 & ~GET_MODE_MASK (mode
)) == 0)));
10650 || ((num_sign_bit_copies (op0
, tmode
)
10651 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10652 - GET_MODE_BITSIZE (mode
)))
10653 && (num_sign_bit_copies (op1
, tmode
)
10654 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10655 - GET_MODE_BITSIZE (mode
)))))
10657 /* If OP0 is an AND and we don't have an AND in MODE either,
10658 make a new AND in the proper mode. */
10659 if (GET_CODE (op0
) == AND
10660 && !have_insn_for (AND
, mode
))
10661 op0
= gen_binary (AND
, tmode
,
10662 gen_lowpart (tmode
,
10664 gen_lowpart (tmode
,
10667 op0
= gen_lowpart (tmode
, op0
);
10668 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
10669 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
10670 op1
= gen_lowpart (tmode
, op1
);
10674 /* If this is a test for negative, we can make an explicit
10675 test of the sign bit. */
10677 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10678 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10680 op0
= gen_binary (AND
, tmode
,
10681 gen_lowpart (tmode
, op0
),
10682 GEN_INT ((HOST_WIDE_INT
) 1
10683 << (GET_MODE_BITSIZE (mode
) - 1)));
10684 code
= (code
== LT
) ? NE
: EQ
;
10689 #ifdef CANONICALIZE_COMPARISON
10690 /* If this machine only supports a subset of valid comparisons, see if we
10691 can convert an unsupported one into a supported one. */
10692 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10701 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10702 searching backward. */
10703 static enum rtx_code
10704 combine_reversed_comparison_code (rtx exp
)
10706 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
10709 if (code1
!= UNKNOWN
10710 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
10712 /* Otherwise try and find where the condition codes were last set and
10714 x
= get_last_value (XEXP (exp
, 0));
10715 if (!x
|| GET_CODE (x
) != COMPARE
)
10717 return reversed_comparison_code_parts (GET_CODE (exp
),
10718 XEXP (x
, 0), XEXP (x
, 1), NULL
);
10721 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10722 Return NULL_RTX in case we fail to do the reversal. */
10724 reversed_comparison (rtx exp
, enum machine_mode mode
, rtx op0
, rtx op1
)
10726 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
10727 if (reversed_code
== UNKNOWN
)
10730 return gen_binary (reversed_code
, mode
, op0
, op1
);
10733 /* Utility function for record_value_for_reg. Count number of
10738 enum rtx_code code
= GET_CODE (x
);
10742 if (GET_RTX_CLASS (code
) == '2'
10743 || GET_RTX_CLASS (code
) == 'c')
10745 rtx x0
= XEXP (x
, 0);
10746 rtx x1
= XEXP (x
, 1);
10749 return 1 + 2 * count_rtxs (x0
);
10751 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
10752 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
10753 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
10754 return 2 + 2 * count_rtxs (x0
)
10755 + count_rtxs (x
== XEXP (x1
, 0)
10756 ? XEXP (x1
, 1) : XEXP (x1
, 0));
10758 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
10759 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
10760 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
10761 return 2 + 2 * count_rtxs (x1
)
10762 + count_rtxs (x
== XEXP (x0
, 0)
10763 ? XEXP (x0
, 1) : XEXP (x0
, 0));
10766 fmt
= GET_RTX_FORMAT (code
);
10767 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10769 ret
+= count_rtxs (XEXP (x
, i
));
10774 /* Utility function for following routine. Called when X is part of a value
10775 being stored into last_set_value. Sets last_set_table_tick
10776 for each register mentioned. Similar to mention_regs in cse.c */
10779 update_table_tick (rtx x
)
10781 enum rtx_code code
= GET_CODE (x
);
10782 const char *fmt
= GET_RTX_FORMAT (code
);
10787 unsigned int regno
= REGNO (x
);
10788 unsigned int endregno
10789 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10790 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
10793 for (r
= regno
; r
< endregno
; r
++)
10794 reg_stat
[r
].last_set_table_tick
= label_tick
;
10799 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10800 /* Note that we can't have an "E" in values stored; see
10801 get_last_value_validate. */
10804 /* Check for identical subexpressions. If x contains
10805 identical subexpression we only have to traverse one of
10807 if (i
== 0 && ARITHMETIC_P (x
))
10809 /* Note that at this point x1 has already been
10811 rtx x0
= XEXP (x
, 0);
10812 rtx x1
= XEXP (x
, 1);
10814 /* If x0 and x1 are identical then there is no need to
10819 /* If x0 is identical to a subexpression of x1 then while
10820 processing x1, x0 has already been processed. Thus we
10821 are done with x. */
10822 if (ARITHMETIC_P (x1
)
10823 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
10826 /* If x1 is identical to a subexpression of x0 then we
10827 still have to process the rest of x0. */
10828 if (ARITHMETIC_P (x0
)
10829 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
10831 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
10836 update_table_tick (XEXP (x
, i
));
10840 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10841 are saying that the register is clobbered and we no longer know its
10842 value. If INSN is zero, don't update reg_stat[].last_set; this is
10843 only permitted with VALUE also zero and is used to invalidate the
10847 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
10849 unsigned int regno
= REGNO (reg
);
10850 unsigned int endregno
10851 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10852 ? hard_regno_nregs
[regno
][GET_MODE (reg
)] : 1);
10855 /* If VALUE contains REG and we have a previous value for REG, substitute
10856 the previous value. */
10857 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
10861 /* Set things up so get_last_value is allowed to see anything set up to
10863 subst_low_cuid
= INSN_CUID (insn
);
10864 tem
= get_last_value (reg
);
10866 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10867 it isn't going to be useful and will take a lot of time to process,
10868 so just use the CLOBBER. */
10872 if (ARITHMETIC_P (tem
)
10873 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
10874 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
10875 tem
= XEXP (tem
, 0);
10876 else if (count_occurrences (value
, reg
, 1) >= 2)
10878 /* If there are two or more occurrences of REG in VALUE,
10879 prevent the value from growing too much. */
10880 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
10881 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
10884 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
10888 /* For each register modified, show we don't know its value, that
10889 we don't know about its bitwise content, that its value has been
10890 updated, and that we don't know the location of the death of the
10892 for (i
= regno
; i
< endregno
; i
++)
10895 reg_stat
[i
].last_set
= insn
;
10897 reg_stat
[i
].last_set_value
= 0;
10898 reg_stat
[i
].last_set_mode
= 0;
10899 reg_stat
[i
].last_set_nonzero_bits
= 0;
10900 reg_stat
[i
].last_set_sign_bit_copies
= 0;
10901 reg_stat
[i
].last_death
= 0;
10904 /* Mark registers that are being referenced in this value. */
10906 update_table_tick (value
);
10908 /* Now update the status of each register being set.
10909 If someone is using this register in this block, set this register
10910 to invalid since we will get confused between the two lives in this
10911 basic block. This makes using this register always invalid. In cse, we
10912 scan the table to invalidate all entries using this register, but this
10913 is too much work for us. */
10915 for (i
= regno
; i
< endregno
; i
++)
10917 reg_stat
[i
].last_set_label
= label_tick
;
10918 if (value
&& reg_stat
[i
].last_set_table_tick
== label_tick
)
10919 reg_stat
[i
].last_set_invalid
= 1;
10921 reg_stat
[i
].last_set_invalid
= 0;
10924 /* The value being assigned might refer to X (like in "x++;"). In that
10925 case, we must replace it with (clobber (const_int 0)) to prevent
10927 if (value
&& ! get_last_value_validate (&value
, insn
,
10928 reg_stat
[regno
].last_set_label
, 0))
10930 value
= copy_rtx (value
);
10931 if (! get_last_value_validate (&value
, insn
,
10932 reg_stat
[regno
].last_set_label
, 1))
10936 /* For the main register being modified, update the value, the mode, the
10937 nonzero bits, and the number of sign bit copies. */
10939 reg_stat
[regno
].last_set_value
= value
;
10943 enum machine_mode mode
= GET_MODE (reg
);
10944 subst_low_cuid
= INSN_CUID (insn
);
10945 reg_stat
[regno
].last_set_mode
= mode
;
10946 if (GET_MODE_CLASS (mode
) == MODE_INT
10947 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10948 mode
= nonzero_bits_mode
;
10949 reg_stat
[regno
].last_set_nonzero_bits
= nonzero_bits (value
, mode
);
10950 reg_stat
[regno
].last_set_sign_bit_copies
10951 = num_sign_bit_copies (value
, GET_MODE (reg
));
10955 /* Called via note_stores from record_dead_and_set_regs to handle one
10956 SET or CLOBBER in an insn. DATA is the instruction in which the
10957 set is occurring. */
10960 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
10962 rtx record_dead_insn
= (rtx
) data
;
10964 if (GET_CODE (dest
) == SUBREG
)
10965 dest
= SUBREG_REG (dest
);
10969 /* If we are setting the whole register, we know its value. Otherwise
10970 show that we don't know the value. We can handle SUBREG in
10972 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
10973 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
10974 else if (GET_CODE (setter
) == SET
10975 && GET_CODE (SET_DEST (setter
)) == SUBREG
10976 && SUBREG_REG (SET_DEST (setter
)) == dest
10977 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
10978 && subreg_lowpart_p (SET_DEST (setter
)))
10979 record_value_for_reg (dest
, record_dead_insn
,
10980 gen_lowpart (GET_MODE (dest
),
10981 SET_SRC (setter
)));
10983 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
10985 else if (MEM_P (dest
)
10986 /* Ignore pushes, they clobber nothing. */
10987 && ! push_operand (dest
, GET_MODE (dest
)))
10988 mem_last_set
= INSN_CUID (record_dead_insn
);
10991 /* Update the records of when each REG was most recently set or killed
10992 for the things done by INSN. This is the last thing done in processing
10993 INSN in the combiner loop.
10995 We update reg_stat[], in particular fields last_set, last_set_value,
10996 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10997 last_death, and also the similar information mem_last_set (which insn
10998 most recently modified memory) and last_call_cuid (which insn was the
10999 most recent subroutine call). */
11002 record_dead_and_set_regs (rtx insn
)
11007 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11009 if (REG_NOTE_KIND (link
) == REG_DEAD
11010 && REG_P (XEXP (link
, 0)))
11012 unsigned int regno
= REGNO (XEXP (link
, 0));
11013 unsigned int endregno
11014 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11015 ? hard_regno_nregs
[regno
][GET_MODE (XEXP (link
, 0))]
11018 for (i
= regno
; i
< endregno
; i
++)
11019 reg_stat
[i
].last_death
= insn
;
11021 else if (REG_NOTE_KIND (link
) == REG_INC
)
11022 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11027 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11028 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11030 reg_stat
[i
].last_set_value
= 0;
11031 reg_stat
[i
].last_set_mode
= 0;
11032 reg_stat
[i
].last_set_nonzero_bits
= 0;
11033 reg_stat
[i
].last_set_sign_bit_copies
= 0;
11034 reg_stat
[i
].last_death
= 0;
11037 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11039 /* Don't bother recording what this insn does. It might set the
11040 return value register, but we can't combine into a call
11041 pattern anyway, so there's no point trying (and it may cause
11042 a crash, if e.g. we wind up asking for last_set_value of a
11043 SUBREG of the return value register). */
11047 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11050 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11051 register present in the SUBREG, so for each such SUBREG go back and
11052 adjust nonzero and sign bit information of the registers that are
11053 known to have some zero/sign bits set.
11055 This is needed because when combine blows the SUBREGs away, the
11056 information on zero/sign bits is lost and further combines can be
11057 missed because of that. */
11060 record_promoted_value (rtx insn
, rtx subreg
)
11063 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11064 enum machine_mode mode
= GET_MODE (subreg
);
11066 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11069 for (links
= LOG_LINKS (insn
); links
;)
11071 insn
= XEXP (links
, 0);
11072 set
= single_set (insn
);
11074 if (! set
|| !REG_P (SET_DEST (set
))
11075 || REGNO (SET_DEST (set
)) != regno
11076 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11078 links
= XEXP (links
, 1);
11082 if (reg_stat
[regno
].last_set
== insn
)
11084 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11085 reg_stat
[regno
].last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
11088 if (REG_P (SET_SRC (set
)))
11090 regno
= REGNO (SET_SRC (set
));
11091 links
= LOG_LINKS (insn
);
11098 /* Scan X for promoted SUBREGs. For each one found,
11099 note what it implies to the registers used in it. */
11102 check_promoted_subreg (rtx insn
, rtx x
)
11104 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11105 && REG_P (SUBREG_REG (x
)))
11106 record_promoted_value (insn
, x
);
11109 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11112 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11116 check_promoted_subreg (insn
, XEXP (x
, i
));
11120 if (XVEC (x
, i
) != 0)
11121 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11122 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11128 /* Utility routine for the following function. Verify that all the registers
11129 mentioned in *LOC are valid when *LOC was part of a value set when
11130 label_tick == TICK. Return 0 if some are not.
11132 If REPLACE is nonzero, replace the invalid reference with
11133 (clobber (const_int 0)) and return 1. This replacement is useful because
11134 we often can get useful information about the form of a value (e.g., if
11135 it was produced by a shift that always produces -1 or 0) even though
11136 we don't know exactly what registers it was produced from. */
11139 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11142 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11143 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11148 unsigned int regno
= REGNO (x
);
11149 unsigned int endregno
11150 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11151 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11154 for (j
= regno
; j
< endregno
; j
++)
11155 if (reg_stat
[j
].last_set_invalid
11156 /* If this is a pseudo-register that was only set once and not
11157 live at the beginning of the function, it is always valid. */
11158 || (! (regno
>= FIRST_PSEUDO_REGISTER
11159 && REG_N_SETS (regno
) == 1
11160 && (! REGNO_REG_SET_P
11161 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11162 && reg_stat
[j
].last_set_label
> tick
))
11165 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11171 /* If this is a memory reference, make sure that there were
11172 no stores after it that might have clobbered the value. We don't
11173 have alias info, so we assume any store invalidates it. */
11174 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
11175 && INSN_CUID (insn
) <= mem_last_set
)
11178 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11182 for (i
= 0; i
< len
; i
++)
11186 /* Check for identical subexpressions. If x contains
11187 identical subexpression we only have to traverse one of
11189 if (i
== 1 && ARITHMETIC_P (x
))
11191 /* Note that at this point x0 has already been checked
11192 and found valid. */
11193 rtx x0
= XEXP (x
, 0);
11194 rtx x1
= XEXP (x
, 1);
11196 /* If x0 and x1 are identical then x is also valid. */
11200 /* If x1 is identical to a subexpression of x0 then
11201 while checking x0, x1 has already been checked. Thus
11202 it is valid and so as x. */
11203 if (ARITHMETIC_P (x0
)
11204 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11207 /* If x0 is identical to a subexpression of x1 then x is
11208 valid iff the rest of x1 is valid. */
11209 if (ARITHMETIC_P (x1
)
11210 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11212 get_last_value_validate (&XEXP (x1
,
11213 x0
== XEXP (x1
, 0) ? 1 : 0),
11214 insn
, tick
, replace
);
11217 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11221 /* Don't bother with these. They shouldn't occur anyway. */
11222 else if (fmt
[i
] == 'E')
11226 /* If we haven't found a reason for it to be invalid, it is valid. */
11230 /* Get the last value assigned to X, if known. Some registers
11231 in the value may be replaced with (clobber (const_int 0)) if their value
11232 is known longer known reliably. */
11235 get_last_value (rtx x
)
11237 unsigned int regno
;
11240 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11241 then convert it to the desired mode. If this is a paradoxical SUBREG,
11242 we cannot predict what values the "extra" bits might have. */
11243 if (GET_CODE (x
) == SUBREG
11244 && subreg_lowpart_p (x
)
11245 && (GET_MODE_SIZE (GET_MODE (x
))
11246 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11247 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11248 return gen_lowpart (GET_MODE (x
), value
);
11254 value
= reg_stat
[regno
].last_set_value
;
11256 /* If we don't have a value, or if it isn't for this basic block and
11257 it's either a hard register, set more than once, or it's a live
11258 at the beginning of the function, return 0.
11260 Because if it's not live at the beginning of the function then the reg
11261 is always set before being used (is never used without being set).
11262 And, if it's set only once, and it's always set before use, then all
11263 uses must have the same last value, even if it's not from this basic
11267 || (reg_stat
[regno
].last_set_label
!= label_tick
11268 && (regno
< FIRST_PSEUDO_REGISTER
11269 || REG_N_SETS (regno
) != 1
11270 || (REGNO_REG_SET_P
11271 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11274 /* If the value was set in a later insn than the ones we are processing,
11275 we can't use it even if the register was only set once. */
11276 if (INSN_CUID (reg_stat
[regno
].last_set
) >= subst_low_cuid
)
11279 /* If the value has all its registers valid, return it. */
11280 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11281 reg_stat
[regno
].last_set_label
, 0))
11284 /* Otherwise, make a copy and replace any invalid register with
11285 (clobber (const_int 0)). If that fails for some reason, return 0. */
11287 value
= copy_rtx (value
);
11288 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11289 reg_stat
[regno
].last_set_label
, 1))
11295 /* Return nonzero if expression X refers to a REG or to memory
11296 that is set in an instruction more recent than FROM_CUID. */
11299 use_crosses_set_p (rtx x
, int from_cuid
)
11303 enum rtx_code code
= GET_CODE (x
);
11307 unsigned int regno
= REGNO (x
);
11308 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11309 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11311 #ifdef PUSH_ROUNDING
11312 /* Don't allow uses of the stack pointer to be moved,
11313 because we don't know whether the move crosses a push insn. */
11314 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11317 for (; regno
< endreg
; regno
++)
11318 if (reg_stat
[regno
].last_set
11319 && INSN_CUID (reg_stat
[regno
].last_set
) > from_cuid
)
11324 if (code
== MEM
&& mem_last_set
> from_cuid
)
11327 fmt
= GET_RTX_FORMAT (code
);
11329 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11334 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11335 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11338 else if (fmt
[i
] == 'e'
11339 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11345 /* Define three variables used for communication between the following
11348 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11349 static int reg_dead_flag
;
11351 /* Function called via note_stores from reg_dead_at_p.
11353 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11354 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11357 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11359 unsigned int regno
, endregno
;
11364 regno
= REGNO (dest
);
11365 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11366 ? hard_regno_nregs
[regno
][GET_MODE (dest
)] : 1);
11368 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11369 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11372 /* Return nonzero if REG is known to be dead at INSN.
11374 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11375 referencing REG, it is dead. If we hit a SET referencing REG, it is
11376 live. Otherwise, see if it is live or dead at the start of the basic
11377 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11378 must be assumed to be always live. */
11381 reg_dead_at_p (rtx reg
, rtx insn
)
11386 /* Set variables for reg_dead_at_p_1. */
11387 reg_dead_regno
= REGNO (reg
);
11388 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11389 ? hard_regno_nregs
[reg_dead_regno
]
11395 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11396 we allow the machine description to decide whether use-and-clobber
11397 patterns are OK. */
11398 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11400 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11401 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11405 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11406 beginning of function. */
11407 for (; insn
&& !LABEL_P (insn
) && !BARRIER_P (insn
);
11408 insn
= prev_nonnote_insn (insn
))
11410 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11412 return reg_dead_flag
== 1 ? 1 : 0;
11414 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11418 /* Get the basic block that we were in. */
11420 block
= ENTRY_BLOCK_PTR
->next_bb
;
11423 FOR_EACH_BB (block
)
11424 if (insn
== BB_HEAD (block
))
11427 if (block
== EXIT_BLOCK_PTR
)
11431 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11432 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
11438 /* Note hard registers in X that are used. This code is similar to
11439 that in flow.c, but much simpler since we don't care about pseudos. */
11442 mark_used_regs_combine (rtx x
)
11444 RTX_CODE code
= GET_CODE (x
);
11445 unsigned int regno
;
11458 case ADDR_DIFF_VEC
:
11461 /* CC0 must die in the insn after it is set, so we don't need to take
11462 special note of it here. */
11468 /* If we are clobbering a MEM, mark any hard registers inside the
11469 address as used. */
11470 if (MEM_P (XEXP (x
, 0)))
11471 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11476 /* A hard reg in a wide mode may really be multiple registers.
11477 If so, mark all of them just like the first. */
11478 if (regno
< FIRST_PSEUDO_REGISTER
)
11480 unsigned int endregno
, r
;
11482 /* None of this applies to the stack, frame or arg pointers. */
11483 if (regno
== STACK_POINTER_REGNUM
11484 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11485 || regno
== HARD_FRAME_POINTER_REGNUM
11487 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11488 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11490 || regno
== FRAME_POINTER_REGNUM
)
11493 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11494 for (r
= regno
; r
< endregno
; r
++)
11495 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11501 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11503 rtx testreg
= SET_DEST (x
);
11505 while (GET_CODE (testreg
) == SUBREG
11506 || GET_CODE (testreg
) == ZERO_EXTRACT
11507 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11508 testreg
= XEXP (testreg
, 0);
11510 if (MEM_P (testreg
))
11511 mark_used_regs_combine (XEXP (testreg
, 0));
11513 mark_used_regs_combine (SET_SRC (x
));
11521 /* Recursively scan the operands of this expression. */
11524 const char *fmt
= GET_RTX_FORMAT (code
);
11526 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11529 mark_used_regs_combine (XEXP (x
, i
));
11530 else if (fmt
[i
] == 'E')
11534 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11535 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11541 /* Remove register number REGNO from the dead registers list of INSN.
11543 Return the note used to record the death, if there was one. */
11546 remove_death (unsigned int regno
, rtx insn
)
11548 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11552 REG_N_DEATHS (regno
)--;
11553 remove_note (insn
, note
);
11559 /* For each register (hardware or pseudo) used within expression X, if its
11560 death is in an instruction with cuid between FROM_CUID (inclusive) and
11561 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11562 list headed by PNOTES.
11564 That said, don't move registers killed by maybe_kill_insn.
11566 This is done when X is being merged by combination into TO_INSN. These
11567 notes will then be distributed as needed. */
11570 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
11575 enum rtx_code code
= GET_CODE (x
);
11579 unsigned int regno
= REGNO (x
);
11580 rtx where_dead
= reg_stat
[regno
].last_death
;
11581 rtx before_dead
, after_dead
;
11583 /* Don't move the register if it gets killed in between from and to. */
11584 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11585 && ! reg_referenced_p (x
, maybe_kill_insn
))
11588 /* WHERE_DEAD could be a USE insn made by combine, so first we
11589 make sure that we have insns with valid INSN_CUID values. */
11590 before_dead
= where_dead
;
11591 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11592 before_dead
= PREV_INSN (before_dead
);
11594 after_dead
= where_dead
;
11595 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11596 after_dead
= NEXT_INSN (after_dead
);
11598 if (before_dead
&& after_dead
11599 && INSN_CUID (before_dead
) >= from_cuid
11600 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11601 || (where_dead
!= after_dead
11602 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11604 rtx note
= remove_death (regno
, where_dead
);
11606 /* It is possible for the call above to return 0. This can occur
11607 when last_death points to I2 or I1 that we combined with.
11608 In that case make a new note.
11610 We must also check for the case where X is a hard register
11611 and NOTE is a death note for a range of hard registers
11612 including X. In that case, we must put REG_DEAD notes for
11613 the remaining registers in place of NOTE. */
11615 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11616 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11617 > GET_MODE_SIZE (GET_MODE (x
))))
11619 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11620 unsigned int deadend
11621 = (deadregno
+ hard_regno_nregs
[deadregno
]
11622 [GET_MODE (XEXP (note
, 0))]);
11623 unsigned int ourend
11624 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11627 for (i
= deadregno
; i
< deadend
; i
++)
11628 if (i
< regno
|| i
>= ourend
)
11629 REG_NOTES (where_dead
)
11630 = gen_rtx_EXPR_LIST (REG_DEAD
,
11632 REG_NOTES (where_dead
));
11635 /* If we didn't find any note, or if we found a REG_DEAD note that
11636 covers only part of the given reg, and we have a multi-reg hard
11637 register, then to be safe we must check for REG_DEAD notes
11638 for each register other than the first. They could have
11639 their own REG_DEAD notes lying around. */
11640 else if ((note
== 0
11642 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11643 < GET_MODE_SIZE (GET_MODE (x
)))))
11644 && regno
< FIRST_PSEUDO_REGISTER
11645 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
11647 unsigned int ourend
11648 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11649 unsigned int i
, offset
;
11653 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
11657 for (i
= regno
+ offset
; i
< ourend
; i
++)
11658 move_deaths (regno_reg_rtx
[i
],
11659 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11662 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11664 XEXP (note
, 1) = *pnotes
;
11668 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11670 REG_N_DEATHS (regno
)++;
11676 else if (GET_CODE (x
) == SET
)
11678 rtx dest
= SET_DEST (x
);
11680 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11682 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11683 that accesses one word of a multi-word item, some
11684 piece of everything register in the expression is used by
11685 this insn, so remove any old death. */
11686 /* ??? So why do we test for equality of the sizes? */
11688 if (GET_CODE (dest
) == ZERO_EXTRACT
11689 || GET_CODE (dest
) == STRICT_LOW_PART
11690 || (GET_CODE (dest
) == SUBREG
11691 && (((GET_MODE_SIZE (GET_MODE (dest
))
11692 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11693 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11694 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11696 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11700 /* If this is some other SUBREG, we know it replaces the entire
11701 value, so use that as the destination. */
11702 if (GET_CODE (dest
) == SUBREG
)
11703 dest
= SUBREG_REG (dest
);
11705 /* If this is a MEM, adjust deaths of anything used in the address.
11706 For a REG (the only other possibility), the entire value is
11707 being replaced so the old value is not used in this insn. */
11710 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11715 else if (GET_CODE (x
) == CLOBBER
)
11718 len
= GET_RTX_LENGTH (code
);
11719 fmt
= GET_RTX_FORMAT (code
);
11721 for (i
= 0; i
< len
; i
++)
11726 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11727 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11730 else if (fmt
[i
] == 'e')
11731 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11735 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11736 pattern of an insn. X must be a REG. */
11739 reg_bitfield_target_p (rtx x
, rtx body
)
11743 if (GET_CODE (body
) == SET
)
11745 rtx dest
= SET_DEST (body
);
11747 unsigned int regno
, tregno
, endregno
, endtregno
;
11749 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11750 target
= XEXP (dest
, 0);
11751 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11752 target
= SUBREG_REG (XEXP (dest
, 0));
11756 if (GET_CODE (target
) == SUBREG
)
11757 target
= SUBREG_REG (target
);
11759 if (!REG_P (target
))
11762 tregno
= REGNO (target
), regno
= REGNO (x
);
11763 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11764 return target
== x
;
11766 endtregno
= tregno
+ hard_regno_nregs
[tregno
][GET_MODE (target
)];
11767 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11769 return endregno
> tregno
&& regno
< endtregno
;
11772 else if (GET_CODE (body
) == PARALLEL
)
11773 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11774 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11780 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11781 as appropriate. I3 and I2 are the insns resulting from the combination
11782 insns including FROM (I2 may be zero).
11784 Each note in the list is either ignored or placed on some insns, depending
11785 on the type of note. */
11788 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
11790 rtx note
, next_note
;
11793 for (note
= notes
; note
; note
= next_note
)
11795 rtx place
= 0, place2
= 0;
11797 /* If this NOTE references a pseudo register, ensure it references
11798 the latest copy of that register. */
11799 if (XEXP (note
, 0) && REG_P (XEXP (note
, 0))
11800 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
11801 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
11803 next_note
= XEXP (note
, 1);
11804 switch (REG_NOTE_KIND (note
))
11808 /* Doesn't matter much where we put this, as long as it's somewhere.
11809 It is preferable to keep these notes on branches, which is most
11810 likely to be i3. */
11814 case REG_VALUE_PROFILE
:
11815 /* Just get rid of this note, as it is unused later anyway. */
11818 case REG_NON_LOCAL_GOTO
:
11823 gcc_assert (i2
&& JUMP_P (i2
));
11828 case REG_EH_REGION
:
11829 /* These notes must remain with the call or trapping instruction. */
11832 else if (i2
&& CALL_P (i2
))
11836 gcc_assert (flag_non_call_exceptions
);
11837 if (may_trap_p (i3
))
11839 else if (i2
&& may_trap_p (i2
))
11841 /* ??? Otherwise assume we've combined things such that we
11842 can now prove that the instructions can't trap. Drop the
11843 note in this case. */
11847 case REG_ALWAYS_RETURN
:
11850 /* These notes must remain with the call. It should not be
11851 possible for both I2 and I3 to be a call. */
11856 gcc_assert (i2
&& CALL_P (i2
));
11862 /* Any clobbers for i3 may still exist, and so we must process
11863 REG_UNUSED notes from that insn.
11865 Any clobbers from i2 or i1 can only exist if they were added by
11866 recog_for_combine. In that case, recog_for_combine created the
11867 necessary REG_UNUSED notes. Trying to keep any original
11868 REG_UNUSED notes from these insns can cause incorrect output
11869 if it is for the same register as the original i3 dest.
11870 In that case, we will notice that the register is set in i3,
11871 and then add a REG_UNUSED note for the destination of i3, which
11872 is wrong. However, it is possible to have REG_UNUSED notes from
11873 i2 or i1 for register which were both used and clobbered, so
11874 we keep notes from i2 or i1 if they will turn into REG_DEAD
11877 /* If this register is set or clobbered in I3, put the note there
11878 unless there is one already. */
11879 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
11881 if (from_insn
!= i3
)
11884 if (! (REG_P (XEXP (note
, 0))
11885 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
11886 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
11889 /* Otherwise, if this register is used by I3, then this register
11890 now dies here, so we must put a REG_DEAD note here unless there
11892 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
11893 && ! (REG_P (XEXP (note
, 0))
11894 ? find_regno_note (i3
, REG_DEAD
,
11895 REGNO (XEXP (note
, 0)))
11896 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
11898 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
11906 /* These notes say something about results of an insn. We can
11907 only support them if they used to be on I3 in which case they
11908 remain on I3. Otherwise they are ignored.
11910 If the note refers to an expression that is not a constant, we
11911 must also ignore the note since we cannot tell whether the
11912 equivalence is still true. It might be possible to do
11913 slightly better than this (we only have a problem if I2DEST
11914 or I1DEST is present in the expression), but it doesn't
11915 seem worth the trouble. */
11917 if (from_insn
== i3
11918 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
11923 case REG_NO_CONFLICT
:
11924 /* These notes say something about how a register is used. They must
11925 be present on any use of the register in I2 or I3. */
11926 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
11929 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
11939 /* This can show up in several ways -- either directly in the
11940 pattern, or hidden off in the constant pool with (or without?)
11941 a REG_EQUAL note. */
11942 /* ??? Ignore the without-reg_equal-note problem for now. */
11943 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
11944 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
11945 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
11946 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
11950 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
11951 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
11952 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
11953 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
11961 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
11962 a JUMP_LABEL instead or decrement LABEL_NUSES. */
11963 if (place
&& JUMP_P (place
))
11965 rtx label
= JUMP_LABEL (place
);
11968 JUMP_LABEL (place
) = XEXP (note
, 0);
11971 gcc_assert (label
== XEXP (note
, 0));
11972 if (LABEL_P (label
))
11973 LABEL_NUSES (label
)--;
11977 if (place2
&& JUMP_P (place2
))
11979 rtx label
= JUMP_LABEL (place2
);
11982 JUMP_LABEL (place2
) = XEXP (note
, 0);
11985 gcc_assert (label
== XEXP (note
, 0));
11986 if (LABEL_P (label
))
11987 LABEL_NUSES (label
)--;
11994 /* This note says something about the value of a register prior
11995 to the execution of an insn. It is too much trouble to see
11996 if the note is still correct in all situations. It is better
11997 to simply delete it. */
12001 /* If the insn previously containing this note still exists,
12002 put it back where it was. Otherwise move it to the previous
12003 insn. Adjust the corresponding REG_LIBCALL note. */
12004 if (!NOTE_P (from_insn
))
12008 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12009 place
= prev_real_insn (from_insn
);
12011 XEXP (tem
, 0) = place
;
12012 /* If we're deleting the last remaining instruction of a
12013 libcall sequence, don't add the notes. */
12014 else if (XEXP (note
, 0) == from_insn
)
12016 /* Don't add the dangling REG_RETVAL note. */
12023 /* This is handled similarly to REG_RETVAL. */
12024 if (!NOTE_P (from_insn
))
12028 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12029 place
= next_real_insn (from_insn
);
12031 XEXP (tem
, 0) = place
;
12032 /* If we're deleting the last remaining instruction of a
12033 libcall sequence, don't add the notes. */
12034 else if (XEXP (note
, 0) == from_insn
)
12036 /* Don't add the dangling REG_LIBCALL note. */
12043 /* If the register is used as an input in I3, it dies there.
12044 Similarly for I2, if it is nonzero and adjacent to I3.
12046 If the register is not used as an input in either I3 or I2
12047 and it is not one of the registers we were supposed to eliminate,
12048 there are two possibilities. We might have a non-adjacent I2
12049 or we might have somehow eliminated an additional register
12050 from a computation. For example, we might have had A & B where
12051 we discover that B will always be zero. In this case we will
12052 eliminate the reference to A.
12054 In both cases, we must search to see if we can find a previous
12055 use of A and put the death note there. */
12058 && CALL_P (from_insn
)
12059 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12061 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12063 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12064 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12069 basic_block bb
= this_basic_block
;
12071 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12073 if (! INSN_P (tem
))
12075 if (tem
== BB_HEAD (bb
))
12080 /* If the register is being set at TEM, see if that is all
12081 TEM is doing. If so, delete TEM. Otherwise, make this
12082 into a REG_UNUSED note instead. Don't delete sets to
12083 global register vars. */
12084 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
12085 || !global_regs
[REGNO (XEXP (note
, 0))])
12086 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12088 rtx set
= single_set (tem
);
12089 rtx inner_dest
= 0;
12091 rtx cc0_setter
= NULL_RTX
;
12095 for (inner_dest
= SET_DEST (set
);
12096 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12097 || GET_CODE (inner_dest
) == SUBREG
12098 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12099 inner_dest
= XEXP (inner_dest
, 0))
12102 /* Verify that it was the set, and not a clobber that
12103 modified the register.
12105 CC0 targets must be careful to maintain setter/user
12106 pairs. If we cannot delete the setter due to side
12107 effects, mark the user with an UNUSED note instead
12110 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12111 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12113 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12114 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12115 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12119 /* Move the notes and links of TEM elsewhere.
12120 This might delete other dead insns recursively.
12121 First set the pattern to something that won't use
12123 rtx old_notes
= REG_NOTES (tem
);
12125 PATTERN (tem
) = pc_rtx
;
12126 REG_NOTES (tem
) = NULL
;
12128 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
);
12129 distribute_links (LOG_LINKS (tem
));
12131 SET_INSN_DELETED (tem
);
12134 /* Delete the setter too. */
12137 PATTERN (cc0_setter
) = pc_rtx
;
12138 old_notes
= REG_NOTES (cc0_setter
);
12139 REG_NOTES (cc0_setter
) = NULL
;
12141 distribute_notes (old_notes
, cc0_setter
,
12142 cc0_setter
, NULL_RTX
);
12143 distribute_links (LOG_LINKS (cc0_setter
));
12145 SET_INSN_DELETED (cc0_setter
);
12151 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12153 /* If there isn't already a REG_UNUSED note, put one
12154 here. Do not place a REG_DEAD note, even if
12155 the register is also used here; that would not
12156 match the algorithm used in lifetime analysis
12157 and can cause the consistency check in the
12158 scheduler to fail. */
12159 if (! find_regno_note (tem
, REG_UNUSED
,
12160 REGNO (XEXP (note
, 0))))
12165 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12167 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12171 /* If we are doing a 3->2 combination, and we have a
12172 register which formerly died in i3 and was not used
12173 by i2, which now no longer dies in i3 and is used in
12174 i2 but does not die in i2, and place is between i2
12175 and i3, then we may need to move a link from place to
12177 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12178 && INSN_CUID (place
) > INSN_CUID (i2
)
12180 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12181 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12183 rtx links
= LOG_LINKS (place
);
12184 LOG_LINKS (place
) = 0;
12185 distribute_links (links
);
12190 if (tem
== BB_HEAD (bb
))
12194 /* We haven't found an insn for the death note and it
12195 is still a REG_DEAD note, but we have hit the beginning
12196 of the block. If the existing life info says the reg
12197 was dead, there's nothing left to do. Otherwise, we'll
12198 need to do a global life update after combine. */
12199 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12200 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12201 REGNO (XEXP (note
, 0))))
12202 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12205 /* If the register is set or already dead at PLACE, we needn't do
12206 anything with this note if it is still a REG_DEAD note.
12207 We check here if it is set at all, not if is it totally replaced,
12208 which is what `dead_or_set_p' checks, so also check for it being
12211 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12213 unsigned int regno
= REGNO (XEXP (note
, 0));
12215 /* Similarly, if the instruction on which we want to place
12216 the note is a noop, we'll need do a global live update
12217 after we remove them in delete_noop_moves. */
12218 if (noop_move_p (place
))
12219 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12221 if (dead_or_set_p (place
, XEXP (note
, 0))
12222 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12224 /* Unless the register previously died in PLACE, clear
12225 last_death. [I no longer understand why this is
12227 if (reg_stat
[regno
].last_death
!= place
)
12228 reg_stat
[regno
].last_death
= 0;
12232 reg_stat
[regno
].last_death
= place
;
12234 /* If this is a death note for a hard reg that is occupying
12235 multiple registers, ensure that we are still using all
12236 parts of the object. If we find a piece of the object
12237 that is unused, we must arrange for an appropriate REG_DEAD
12238 note to be added for it. However, we can't just emit a USE
12239 and tag the note to it, since the register might actually
12240 be dead; so we recourse, and the recursive call then finds
12241 the previous insn that used this register. */
12243 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12244 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
12246 unsigned int endregno
12247 = regno
+ hard_regno_nregs
[regno
]
12248 [GET_MODE (XEXP (note
, 0))];
12252 for (i
= regno
; i
< endregno
; i
++)
12253 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12254 && ! find_regno_fusage (place
, USE
, i
))
12255 || dead_or_set_regno_p (place
, i
))
12260 /* Put only REG_DEAD notes for pieces that are
12261 not already dead or set. */
12263 for (i
= regno
; i
< endregno
;
12264 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12266 rtx piece
= regno_reg_rtx
[i
];
12267 basic_block bb
= this_basic_block
;
12269 if (! dead_or_set_p (place
, piece
)
12270 && ! reg_bitfield_target_p (piece
,
12274 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12276 distribute_notes (new_note
, place
, place
,
12279 else if (! refers_to_regno_p (i
, i
+ 1,
12280 PATTERN (place
), 0)
12281 && ! find_regno_fusage (place
, USE
, i
))
12282 for (tem
= PREV_INSN (place
); ;
12283 tem
= PREV_INSN (tem
))
12285 if (! INSN_P (tem
))
12287 if (tem
== BB_HEAD (bb
))
12289 SET_BIT (refresh_blocks
,
12290 this_basic_block
->index
);
12295 if (dead_or_set_p (tem
, piece
)
12296 || reg_bitfield_target_p (piece
,
12300 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12315 /* Any other notes should not be present at this point in the
12317 gcc_unreachable ();
12322 XEXP (note
, 1) = REG_NOTES (place
);
12323 REG_NOTES (place
) = note
;
12325 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12326 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12327 && REG_P (XEXP (note
, 0)))
12328 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12332 if ((REG_NOTE_KIND (note
) == REG_DEAD
12333 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12334 && REG_P (XEXP (note
, 0)))
12335 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12337 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12338 REG_NOTE_KIND (note
),
12340 REG_NOTES (place2
));
12345 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12346 I3, I2, and I1 to new locations. This is also called to add a link
12347 pointing at I3 when I3's destination is changed. */
12350 distribute_links (rtx links
)
12352 rtx link
, next_link
;
12354 for (link
= links
; link
; link
= next_link
)
12360 next_link
= XEXP (link
, 1);
12362 /* If the insn that this link points to is a NOTE or isn't a single
12363 set, ignore it. In the latter case, it isn't clear what we
12364 can do other than ignore the link, since we can't tell which
12365 register it was for. Such links wouldn't be used by combine
12368 It is not possible for the destination of the target of the link to
12369 have been changed by combine. The only potential of this is if we
12370 replace I3, I2, and I1 by I3 and I2. But in that case the
12371 destination of I2 also remains unchanged. */
12373 if (NOTE_P (XEXP (link
, 0))
12374 || (set
= single_set (XEXP (link
, 0))) == 0)
12377 reg
= SET_DEST (set
);
12378 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12379 || GET_CODE (reg
) == STRICT_LOW_PART
)
12380 reg
= XEXP (reg
, 0);
12382 /* A LOG_LINK is defined as being placed on the first insn that uses
12383 a register and points to the insn that sets the register. Start
12384 searching at the next insn after the target of the link and stop
12385 when we reach a set of the register or the end of the basic block.
12387 Note that this correctly handles the link that used to point from
12388 I3 to I2. Also note that not much searching is typically done here
12389 since most links don't point very far away. */
12391 for (insn
= NEXT_INSN (XEXP (link
, 0));
12392 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12393 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12394 insn
= NEXT_INSN (insn
))
12395 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12397 if (reg_referenced_p (reg
, PATTERN (insn
)))
12401 else if (CALL_P (insn
)
12402 && find_reg_fusage (insn
, USE
, reg
))
12407 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12410 /* If we found a place to put the link, place it there unless there
12411 is already a link to the same insn as LINK at that point. */
12417 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12418 if (XEXP (link2
, 0) == XEXP (link
, 0))
12423 XEXP (link
, 1) = LOG_LINKS (place
);
12424 LOG_LINKS (place
) = link
;
12426 /* Set added_links_insn to the earliest insn we added a
12428 if (added_links_insn
== 0
12429 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12430 added_links_insn
= place
;
12436 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12437 Check whether the expression pointer to by LOC is a register or
12438 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12439 Otherwise return zero. */
12442 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
12447 && (REG_P (x
) || MEM_P (x
))
12448 && ! reg_mentioned_p (x
, (rtx
) expr
))
12453 /* Check for any register or memory mentioned in EQUIV that is not
12454 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12455 of EXPR where some registers may have been replaced by constants. */
12458 unmentioned_reg_p (rtx equiv
, rtx expr
)
12460 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
12463 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12466 insn_cuid (rtx insn
)
12468 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12469 && NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
)
12470 insn
= NEXT_INSN (insn
);
12472 gcc_assert (INSN_UID (insn
) <= max_uid_cuid
);
12474 return INSN_CUID (insn
);
12478 dump_combine_stats (FILE *file
)
12482 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12483 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12487 dump_combine_total_stats (FILE *file
)
12491 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12492 total_attempts
, total_merges
, total_extras
, total_successes
);