1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
93 #include "rtlhooks-def.h"
94 /* Include output.h for dump_file. */
97 /* Number of attempts to combine instructions in this function. */
99 static int combine_attempts
;
101 /* Number of attempts that got as far as substitution in this function. */
103 static int combine_merges
;
105 /* Number of instructions combined with added SETs in this function. */
107 static int combine_extras
;
109 /* Number of instructions combined in this function. */
111 static int combine_successes
;
113 /* Totals over entire compilation. */
115 static int total_attempts
, total_merges
, total_extras
, total_successes
;
118 /* Vector mapping INSN_UIDs to cuids.
119 The cuids are like uids but increase monotonically always.
120 Combine always uses cuids so that it can compare them.
121 But actually renumbering the uids, which we used to do,
122 proves to be a bad idea because it makes it hard to compare
123 the dumps produced by earlier passes with those from later passes. */
125 static int *uid_cuid
;
126 static int max_uid_cuid
;
128 /* Get the cuid of an insn. */
130 #define INSN_CUID(INSN) \
131 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
133 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
134 BITS_PER_WORD would invoke undefined behavior. Work around it. */
136 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
137 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
139 /* Maximum register number, which is the size of the tables below. */
141 static unsigned int combine_max_regno
;
144 /* Record last point of death of (hard or pseudo) register n. */
147 /* Record last point of modification of (hard or pseudo) register n. */
150 /* The next group of fields allows the recording of the last value assigned
151 to (hard or pseudo) register n. We use this information to see if an
152 operation being processed is redundant given a prior operation performed
153 on the register. For example, an `and' with a constant is redundant if
154 all the zero bits are already known to be turned off.
156 We use an approach similar to that used by cse, but change it in the
159 (1) We do not want to reinitialize at each label.
160 (2) It is useful, but not critical, to know the actual value assigned
161 to a register. Often just its form is helpful.
163 Therefore, we maintain the following fields:
165 last_set_value the last value assigned
166 last_set_label records the value of label_tick when the
167 register was assigned
168 last_set_table_tick records the value of label_tick when a
169 value using the register is assigned
170 last_set_invalid set to nonzero when it is not valid
171 to use the value of this register in some
174 To understand the usage of these tables, it is important to understand
175 the distinction between the value in last_set_value being valid and
176 the register being validly contained in some other expression in the
179 (The next two parameters are out of date).
181 reg_stat[i].last_set_value is valid if it is nonzero, and either
182 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
184 Register I may validly appear in any expression returned for the value
185 of another register if reg_n_sets[i] is 1. It may also appear in the
186 value for register J if reg_stat[j].last_set_invalid is zero, or
187 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
189 If an expression is found in the table containing a register which may
190 not validly appear in an expression, the register is replaced by
191 something that won't match, (clobber (const_int 0)). */
193 /* Record last value assigned to (hard or pseudo) register n. */
197 /* Record the value of label_tick when an expression involving register n
198 is placed in last_set_value. */
200 int last_set_table_tick
;
202 /* Record the value of label_tick when the value for register n is placed in
207 /* These fields are maintained in parallel with last_set_value and are
208 used to store the mode in which the register was last set, the bits
209 that were known to be zero when it was last set, and the number of
210 sign bits copies it was known to have when it was last set. */
212 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
213 char last_set_sign_bit_copies
;
214 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
216 /* Set nonzero if references to register n in expressions should not be
217 used. last_set_invalid is set nonzero when this register is being
218 assigned to and last_set_table_tick == label_tick. */
220 char last_set_invalid
;
222 /* Some registers that are set more than once and used in more than one
223 basic block are nevertheless always set in similar ways. For example,
224 a QImode register may be loaded from memory in two places on a machine
225 where byte loads zero extend.
227 We record in the following fields if a register has some leading bits
228 that are always equal to the sign bit, and what we know about the
229 nonzero bits of a register, specifically which bits are known to be
232 If an entry is zero, it means that we don't know anything special. */
234 unsigned char sign_bit_copies
;
236 unsigned HOST_WIDE_INT nonzero_bits
;
239 static struct reg_stat
*reg_stat
;
241 /* Record the cuid of the last insn that invalidated memory
242 (anything that writes memory, and subroutine calls, but not pushes). */
244 static int mem_last_set
;
246 /* Record the cuid of the last CALL_INSN
247 so we can tell whether a potential combination crosses any calls. */
249 static int last_call_cuid
;
251 /* When `subst' is called, this is the insn that is being modified
252 (by combining in a previous insn). The PATTERN of this insn
253 is still the old pattern partially modified and it should not be
254 looked at, but this may be used to examine the successors of the insn
255 to judge whether a simplification is valid. */
257 static rtx subst_insn
;
259 /* This is the lowest CUID that `subst' is currently dealing with.
260 get_last_value will not return a value if the register was set at or
261 after this CUID. If not for this mechanism, we could get confused if
262 I2 or I1 in try_combine were an insn that used the old value of a register
263 to obtain a new value. In that case, we might erroneously get the
264 new value of the register when we wanted the old one. */
266 static int subst_low_cuid
;
268 /* This contains any hard registers that are used in newpat; reg_dead_at_p
269 must consider all these registers to be always live. */
271 static HARD_REG_SET newpat_used_regs
;
273 /* This is an insn to which a LOG_LINKS entry has been added. If this
274 insn is the earlier than I2 or I3, combine should rescan starting at
277 static rtx added_links_insn
;
279 /* Basic block in which we are performing combines. */
280 static basic_block this_basic_block
;
282 /* A bitmap indicating which blocks had registers go dead at entry.
283 After combine, we'll need to re-do global life analysis with
284 those blocks as starting points. */
285 static sbitmap refresh_blocks
;
287 /* The following array records the insn_rtx_cost for every insn
288 in the instruction stream. */
290 static int *uid_insn_cost
;
292 /* Length of the currently allocated uid_insn_cost array. */
294 static int last_insn_cost
;
296 /* Incremented for each label. */
298 static int label_tick
;
300 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
301 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
303 static enum machine_mode nonzero_bits_mode
;
305 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
306 be safely used. It is zero while computing them and after combine has
307 completed. This former test prevents propagating values based on
308 previously set values, which can be incorrect if a variable is modified
311 static int nonzero_sign_valid
;
314 /* Record one modification to rtl structure
315 to be undone by storing old_contents into *where.
316 is_int is 1 if the contents are an int. */
322 union {rtx r
; int i
;} old_contents
;
323 union {rtx
*r
; int *i
;} where
;
326 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
327 num_undo says how many are currently recorded.
329 other_insn is nonzero if we have modified some other insn in the process
330 of working on subst_insn. It must be verified too. */
339 static struct undobuf undobuf
;
341 /* Number of times the pseudo being substituted for
342 was found and replaced. */
344 static int n_occurrences
;
346 static rtx
reg_nonzero_bits_for_combine (rtx
, enum machine_mode
, rtx
,
348 unsigned HOST_WIDE_INT
,
349 unsigned HOST_WIDE_INT
*);
350 static rtx
reg_num_sign_bit_copies_for_combine (rtx
, enum machine_mode
, rtx
,
352 unsigned int, unsigned int *);
353 static void do_SUBST (rtx
*, rtx
);
354 static void do_SUBST_INT (int *, int);
355 static void init_reg_last (void);
356 static void setup_incoming_promotions (void);
357 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
358 static int cant_combine_insn_p (rtx
);
359 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
360 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
361 static int contains_muldiv (rtx
);
362 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
363 static void undo_all (void);
364 static void undo_commit (void);
365 static rtx
*find_split_point (rtx
*, rtx
);
366 static rtx
subst (rtx
, rtx
, rtx
, int, int);
367 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int);
368 static rtx
simplify_if_then_else (rtx
);
369 static rtx
simplify_set (rtx
);
370 static rtx
simplify_logical (rtx
);
371 static rtx
expand_compound_operation (rtx
);
372 static rtx
expand_field_assignment (rtx
);
373 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
374 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
375 static rtx
extract_left_shift (rtx
, int);
376 static rtx
make_compound_operation (rtx
, enum rtx_code
);
377 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
378 unsigned HOST_WIDE_INT
*);
379 static rtx
force_to_mode (rtx
, enum machine_mode
,
380 unsigned HOST_WIDE_INT
, rtx
, int);
381 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
382 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
383 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
384 static rtx
make_field_assignment (rtx
);
385 static rtx
apply_distributive_law (rtx
);
386 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
387 unsigned HOST_WIDE_INT
);
388 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
389 HOST_WIDE_INT
, enum machine_mode
, int *);
390 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
392 static int recog_for_combine (rtx
*, rtx
, rtx
*);
393 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
394 static rtx
gen_binary (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
395 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
396 static void update_table_tick (rtx
);
397 static void record_value_for_reg (rtx
, rtx
, rtx
);
398 static void check_promoted_subreg (rtx
, rtx
);
399 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
400 static void record_dead_and_set_regs (rtx
);
401 static int get_last_value_validate (rtx
*, rtx
, int, int);
402 static rtx
get_last_value (rtx
);
403 static int use_crosses_set_p (rtx
, int);
404 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
405 static int reg_dead_at_p (rtx
, rtx
);
406 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
407 static int reg_bitfield_target_p (rtx
, rtx
);
408 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
409 static void distribute_links (rtx
);
410 static void mark_used_regs_combine (rtx
);
411 static int insn_cuid (rtx
);
412 static void record_promoted_value (rtx
, rtx
);
413 static rtx
reversed_comparison (rtx
, enum machine_mode
, rtx
, rtx
);
414 static enum rtx_code
combine_reversed_comparison_code (rtx
);
415 static int unmentioned_reg_p_1 (rtx
*, void *);
416 static bool unmentioned_reg_p (rtx
, rtx
);
419 /* It is not safe to use ordinary gen_lowpart in combine.
420 See comments in gen_lowpart_for_combine. */
421 #undef RTL_HOOKS_GEN_LOWPART
422 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
424 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
425 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
427 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
428 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
430 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
433 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
434 insn. The substitution can be undone by undo_all. If INTO is already
435 set to NEWVAL, do not record this change. Because computing NEWVAL might
436 also call SUBST, we have to compute it before we put anything into
440 do_SUBST (rtx
*into
, rtx newval
)
445 if (oldval
== newval
)
448 /* We'd like to catch as many invalid transformations here as
449 possible. Unfortunately, there are way too many mode changes
450 that are perfectly valid, so we'd waste too much effort for
451 little gain doing the checks here. Focus on catching invalid
452 transformations involving integer constants. */
453 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
454 && GET_CODE (newval
) == CONST_INT
)
456 /* Sanity check that we're replacing oldval with a CONST_INT
457 that is a valid sign-extension for the original mode. */
458 gcc_assert (INTVAL (newval
)
459 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
461 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
462 CONST_INT is not valid, because after the replacement, the
463 original mode would be gone. Unfortunately, we can't tell
464 when do_SUBST is called to replace the operand thereof, so we
465 perform this test on oldval instead, checking whether an
466 invalid replacement took place before we got here. */
467 gcc_assert (!(GET_CODE (oldval
) == SUBREG
468 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
));
469 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
470 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
));
474 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
476 buf
= xmalloc (sizeof (struct undo
));
480 buf
->old_contents
.r
= oldval
;
483 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
486 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
488 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
489 for the value of a HOST_WIDE_INT value (including CONST_INT) is
493 do_SUBST_INT (int *into
, int newval
)
498 if (oldval
== newval
)
502 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
504 buf
= xmalloc (sizeof (struct undo
));
508 buf
->old_contents
.i
= oldval
;
511 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
514 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
516 /* Subroutine of try_combine. Determine whether the combine replacement
517 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
518 that the original instruction sequence I1, I2 and I3. Note that I1
519 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
520 costs of all instructions can be estimated, and the replacements are
521 more expensive than the original sequence. */
524 combine_validate_cost (rtx i1
, rtx i2
, rtx i3
, rtx newpat
, rtx newi2pat
)
526 int i1_cost
, i2_cost
, i3_cost
;
527 int new_i2_cost
, new_i3_cost
;
528 int old_cost
, new_cost
;
530 /* Lookup the original insn_rtx_costs. */
531 i2_cost
= INSN_UID (i2
) <= last_insn_cost
532 ? uid_insn_cost
[INSN_UID (i2
)] : 0;
533 i3_cost
= INSN_UID (i3
) <= last_insn_cost
534 ? uid_insn_cost
[INSN_UID (i3
)] : 0;
538 i1_cost
= INSN_UID (i1
) <= last_insn_cost
539 ? uid_insn_cost
[INSN_UID (i1
)] : 0;
540 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0)
541 ? i1_cost
+ i2_cost
+ i3_cost
: 0;
545 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
549 /* Calculate the replacement insn_rtx_costs. */
550 new_i3_cost
= insn_rtx_cost (newpat
);
553 new_i2_cost
= insn_rtx_cost (newi2pat
);
554 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
555 ? new_i2_cost
+ new_i3_cost
: 0;
559 new_cost
= new_i3_cost
;
563 if (undobuf
.other_insn
)
565 int old_other_cost
, new_other_cost
;
567 old_other_cost
= (INSN_UID (undobuf
.other_insn
) <= last_insn_cost
568 ? uid_insn_cost
[INSN_UID (undobuf
.other_insn
)] : 0);
569 new_other_cost
= insn_rtx_cost (PATTERN (undobuf
.other_insn
));
570 if (old_other_cost
> 0 && new_other_cost
> 0)
572 old_cost
+= old_other_cost
;
573 new_cost
+= new_other_cost
;
579 /* Disallow this recombination if both new_cost and old_cost are
580 greater than zero, and new_cost is greater than old cost. */
582 && new_cost
> old_cost
)
589 "rejecting combination of insns %d, %d and %d\n",
590 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
591 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
592 i1_cost
, i2_cost
, i3_cost
, old_cost
);
597 "rejecting combination of insns %d and %d\n",
598 INSN_UID (i2
), INSN_UID (i3
));
599 fprintf (dump_file
, "original costs %d + %d = %d\n",
600 i2_cost
, i3_cost
, old_cost
);
605 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
606 new_i2_cost
, new_i3_cost
, new_cost
);
609 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
615 /* Update the uid_insn_cost array with the replacement costs. */
616 uid_insn_cost
[INSN_UID (i2
)] = new_i2_cost
;
617 uid_insn_cost
[INSN_UID (i3
)] = new_i3_cost
;
619 uid_insn_cost
[INSN_UID (i1
)] = 0;
624 /* Main entry point for combiner. F is the first insn of the function.
625 NREGS is the first unused pseudo-reg number.
627 Return nonzero if the combiner has turned an indirect jump
628 instruction into a direct jump. */
630 combine_instructions (rtx f
, unsigned int nregs
)
637 rtx links
, nextlinks
;
639 int new_direct_jump_p
= 0;
641 combine_attempts
= 0;
644 combine_successes
= 0;
646 combine_max_regno
= nregs
;
648 rtl_hooks
= combine_rtl_hooks
;
650 reg_stat
= xcalloc (nregs
, sizeof (struct reg_stat
));
652 init_recog_no_volatile ();
654 /* Compute maximum uid value so uid_cuid can be allocated. */
656 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
657 if (INSN_UID (insn
) > i
)
660 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
663 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
665 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
666 problems when, for example, we have j <<= 1 in a loop. */
668 nonzero_sign_valid
= 0;
670 /* Compute the mapping from uids to cuids.
671 Cuids are numbers assigned to insns, like uids,
672 except that cuids increase monotonically through the code.
674 Scan all SETs and see if we can deduce anything about what
675 bits are known to be zero for some registers and how many copies
676 of the sign bit are known to exist for those registers.
678 Also set any known values so that we can use it while searching
679 for what bits are known to be set. */
683 setup_incoming_promotions ();
685 refresh_blocks
= sbitmap_alloc (last_basic_block
);
686 sbitmap_zero (refresh_blocks
);
688 /* Allocate array of current insn_rtx_costs. */
689 uid_insn_cost
= xcalloc (max_uid_cuid
+ 1, sizeof (int));
690 last_insn_cost
= max_uid_cuid
;
692 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
694 uid_cuid
[INSN_UID (insn
)] = ++i
;
700 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
702 record_dead_and_set_regs (insn
);
705 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
706 if (REG_NOTE_KIND (links
) == REG_INC
)
707 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
711 /* Record the current insn_rtx_cost of this instruction. */
712 if (NONJUMP_INSN_P (insn
))
713 uid_insn_cost
[INSN_UID (insn
)] = insn_rtx_cost (PATTERN (insn
));
715 fprintf(dump_file
, "insn_cost %d: %d\n",
716 INSN_UID (insn
), uid_insn_cost
[INSN_UID (insn
)]);
723 nonzero_sign_valid
= 1;
725 /* Now scan all the insns in forward order. */
731 setup_incoming_promotions ();
733 FOR_EACH_BB (this_basic_block
)
735 for (insn
= BB_HEAD (this_basic_block
);
736 insn
!= NEXT_INSN (BB_END (this_basic_block
));
737 insn
= next
? next
: NEXT_INSN (insn
))
744 else if (INSN_P (insn
))
746 /* See if we know about function return values before this
747 insn based upon SUBREG flags. */
748 check_promoted_subreg (insn
, PATTERN (insn
));
750 /* Try this insn with each insn it links back to. */
752 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
753 if ((next
= try_combine (insn
, XEXP (links
, 0),
754 NULL_RTX
, &new_direct_jump_p
)) != 0)
757 /* Try each sequence of three linked insns ending with this one. */
759 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
761 rtx link
= XEXP (links
, 0);
763 /* If the linked insn has been replaced by a note, then there
764 is no point in pursuing this chain any further. */
768 for (nextlinks
= LOG_LINKS (link
);
770 nextlinks
= XEXP (nextlinks
, 1))
771 if ((next
= try_combine (insn
, link
,
773 &new_direct_jump_p
)) != 0)
778 /* Try to combine a jump insn that uses CC0
779 with a preceding insn that sets CC0, and maybe with its
780 logical predecessor as well.
781 This is how we make decrement-and-branch insns.
782 We need this special code because data flow connections
783 via CC0 do not get entered in LOG_LINKS. */
786 && (prev
= prev_nonnote_insn (insn
)) != 0
787 && NONJUMP_INSN_P (prev
)
788 && sets_cc0_p (PATTERN (prev
)))
790 if ((next
= try_combine (insn
, prev
,
791 NULL_RTX
, &new_direct_jump_p
)) != 0)
794 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
795 nextlinks
= XEXP (nextlinks
, 1))
796 if ((next
= try_combine (insn
, prev
,
798 &new_direct_jump_p
)) != 0)
802 /* Do the same for an insn that explicitly references CC0. */
803 if (NONJUMP_INSN_P (insn
)
804 && (prev
= prev_nonnote_insn (insn
)) != 0
805 && NONJUMP_INSN_P (prev
)
806 && sets_cc0_p (PATTERN (prev
))
807 && GET_CODE (PATTERN (insn
)) == SET
808 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
810 if ((next
= try_combine (insn
, prev
,
811 NULL_RTX
, &new_direct_jump_p
)) != 0)
814 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
815 nextlinks
= XEXP (nextlinks
, 1))
816 if ((next
= try_combine (insn
, prev
,
818 &new_direct_jump_p
)) != 0)
822 /* Finally, see if any of the insns that this insn links to
823 explicitly references CC0. If so, try this insn, that insn,
824 and its predecessor if it sets CC0. */
825 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
826 if (NONJUMP_INSN_P (XEXP (links
, 0))
827 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
828 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
829 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
830 && NONJUMP_INSN_P (prev
)
831 && sets_cc0_p (PATTERN (prev
))
832 && (next
= try_combine (insn
, XEXP (links
, 0),
833 prev
, &new_direct_jump_p
)) != 0)
837 /* Try combining an insn with two different insns whose results it
839 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
840 for (nextlinks
= XEXP (links
, 1); nextlinks
;
841 nextlinks
= XEXP (nextlinks
, 1))
842 if ((next
= try_combine (insn
, XEXP (links
, 0),
844 &new_direct_jump_p
)) != 0)
847 /* Try this insn with each REG_EQUAL note it links back to. */
848 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
851 rtx temp
= XEXP (links
, 0);
852 if ((set
= single_set (temp
)) != 0
853 && (note
= find_reg_equal_equiv_note (temp
)) != 0
854 && GET_CODE (XEXP (note
, 0)) != EXPR_LIST
855 /* Avoid using a register that may already been marked
856 dead by an earlier instruction. */
857 && ! unmentioned_reg_p (XEXP (note
, 0), SET_SRC (set
)))
859 /* Temporarily replace the set's source with the
860 contents of the REG_EQUAL note. The insn will
861 be deleted or recognized by try_combine. */
862 rtx orig
= SET_SRC (set
);
863 SET_SRC (set
) = XEXP (note
, 0);
864 next
= try_combine (insn
, temp
, NULL_RTX
,
868 SET_SRC (set
) = orig
;
873 record_dead_and_set_regs (insn
);
882 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
883 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
884 new_direct_jump_p
|= purge_all_dead_edges (0);
885 delete_noop_moves ();
887 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
888 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
889 | PROP_KILL_DEAD_CODE
);
892 sbitmap_free (refresh_blocks
);
893 free (uid_insn_cost
);
898 struct undo
*undo
, *next
;
899 for (undo
= undobuf
.frees
; undo
; undo
= next
)
907 total_attempts
+= combine_attempts
;
908 total_merges
+= combine_merges
;
909 total_extras
+= combine_extras
;
910 total_successes
+= combine_successes
;
912 nonzero_sign_valid
= 0;
913 rtl_hooks
= general_rtl_hooks
;
915 /* Make recognizer allow volatile MEMs again. */
918 return new_direct_jump_p
;
921 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
927 for (i
= 0; i
< combine_max_regno
; i
++)
928 memset (reg_stat
+ i
, 0, offsetof (struct reg_stat
, sign_bit_copies
));
931 /* Set up any promoted values for incoming argument registers. */
934 setup_incoming_promotions (void)
938 enum machine_mode mode
;
940 rtx first
= get_insns ();
942 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
944 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
945 /* Check whether this register can hold an incoming pointer
946 argument. FUNCTION_ARG_REGNO_P tests outgoing register
947 numbers, so translate if necessary due to register windows. */
948 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
949 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
952 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
955 gen_rtx_CLOBBER (mode
, const0_rtx
)));
960 /* Called via note_stores. If X is a pseudo that is narrower than
961 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
963 If we are setting only a portion of X and we can't figure out what
964 portion, assume all bits will be used since we don't know what will
967 Similarly, set how many bits of X are known to be copies of the sign bit
968 at all locations in the function. This is the smallest number implied
972 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
973 void *data ATTRIBUTE_UNUSED
)
978 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
979 /* If this register is undefined at the start of the file, we can't
980 say what its contents were. */
981 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
982 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
984 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
986 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
987 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
991 /* If this is a complex assignment, see if we can convert it into a
992 simple assignment. */
993 set
= expand_field_assignment (set
);
995 /* If this is a simple assignment, or we have a paradoxical SUBREG,
996 set what we know about X. */
998 if (SET_DEST (set
) == x
999 || (GET_CODE (SET_DEST (set
)) == SUBREG
1000 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1001 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
1002 && SUBREG_REG (SET_DEST (set
)) == x
))
1004 rtx src
= SET_SRC (set
);
1006 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1007 /* If X is narrower than a word and SRC is a non-negative
1008 constant that would appear negative in the mode of X,
1009 sign-extend it for use in reg_stat[].nonzero_bits because some
1010 machines (maybe most) will actually do the sign-extension
1011 and this is the conservative approach.
1013 ??? For 2.5, try to tighten up the MD files in this regard
1014 instead of this kludge. */
1016 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
1017 && GET_CODE (src
) == CONST_INT
1019 && 0 != (INTVAL (src
)
1020 & ((HOST_WIDE_INT
) 1
1021 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
1022 src
= GEN_INT (INTVAL (src
)
1023 | ((HOST_WIDE_INT
) (-1)
1024 << GET_MODE_BITSIZE (GET_MODE (x
))));
1027 /* Don't call nonzero_bits if it cannot change anything. */
1028 if (reg_stat
[REGNO (x
)].nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1029 reg_stat
[REGNO (x
)].nonzero_bits
1030 |= nonzero_bits (src
, nonzero_bits_mode
);
1031 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1032 if (reg_stat
[REGNO (x
)].sign_bit_copies
== 0
1033 || reg_stat
[REGNO (x
)].sign_bit_copies
> num
)
1034 reg_stat
[REGNO (x
)].sign_bit_copies
= num
;
1038 reg_stat
[REGNO (x
)].nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1039 reg_stat
[REGNO (x
)].sign_bit_copies
= 1;
1044 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1045 insns that were previously combined into I3 or that will be combined
1046 into the merger of INSN and I3.
1048 Return 0 if the combination is not allowed for any reason.
1050 If the combination is allowed, *PDEST will be set to the single
1051 destination of INSN and *PSRC to the single source, and this function
1055 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
1056 rtx
*pdest
, rtx
*psrc
)
1059 rtx set
= 0, src
, dest
;
1064 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
1065 && next_active_insn (succ
) == i3
)
1066 : next_active_insn (insn
) == i3
);
1068 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1069 or a PARALLEL consisting of such a SET and CLOBBERs.
1071 If INSN has CLOBBER parallel parts, ignore them for our processing.
1072 By definition, these happen during the execution of the insn. When it
1073 is merged with another insn, all bets are off. If they are, in fact,
1074 needed and aren't also supplied in I3, they may be added by
1075 recog_for_combine. Otherwise, it won't match.
1077 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1080 Get the source and destination of INSN. If more than one, can't
1083 if (GET_CODE (PATTERN (insn
)) == SET
)
1084 set
= PATTERN (insn
);
1085 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1086 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1088 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1090 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1093 switch (GET_CODE (elt
))
1095 /* This is important to combine floating point insns
1096 for the SH4 port. */
1098 /* Combining an isolated USE doesn't make sense.
1099 We depend here on combinable_i3pat to reject them. */
1100 /* The code below this loop only verifies that the inputs of
1101 the SET in INSN do not change. We call reg_set_between_p
1102 to verify that the REG in the USE does not change between
1104 If the USE in INSN was for a pseudo register, the matching
1105 insn pattern will likely match any register; combining this
1106 with any other USE would only be safe if we knew that the
1107 used registers have identical values, or if there was
1108 something to tell them apart, e.g. different modes. For
1109 now, we forgo such complicated tests and simply disallow
1110 combining of USES of pseudo registers with any other USE. */
1111 if (REG_P (XEXP (elt
, 0))
1112 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1114 rtx i3pat
= PATTERN (i3
);
1115 int i
= XVECLEN (i3pat
, 0) - 1;
1116 unsigned int regno
= REGNO (XEXP (elt
, 0));
1120 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1122 if (GET_CODE (i3elt
) == USE
1123 && REG_P (XEXP (i3elt
, 0))
1124 && (REGNO (XEXP (i3elt
, 0)) == regno
1125 ? reg_set_between_p (XEXP (elt
, 0),
1126 PREV_INSN (insn
), i3
)
1127 : regno
>= FIRST_PSEUDO_REGISTER
))
1134 /* We can ignore CLOBBERs. */
1139 /* Ignore SETs whose result isn't used but not those that
1140 have side-effects. */
1141 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1142 && (!(note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
))
1143 || INTVAL (XEXP (note
, 0)) <= 0)
1144 && ! side_effects_p (elt
))
1147 /* If we have already found a SET, this is a second one and
1148 so we cannot combine with this insn. */
1156 /* Anything else means we can't combine. */
1162 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1163 so don't do anything with it. */
1164 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1173 set
= expand_field_assignment (set
);
1174 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1176 /* Don't eliminate a store in the stack pointer. */
1177 if (dest
== stack_pointer_rtx
1178 /* Don't combine with an insn that sets a register to itself if it has
1179 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1180 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1181 /* Can't merge an ASM_OPERANDS. */
1182 || GET_CODE (src
) == ASM_OPERANDS
1183 /* Can't merge a function call. */
1184 || GET_CODE (src
) == CALL
1185 /* Don't eliminate a function call argument. */
1187 && (find_reg_fusage (i3
, USE
, dest
)
1189 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1190 && global_regs
[REGNO (dest
)])))
1191 /* Don't substitute into an incremented register. */
1192 || FIND_REG_INC_NOTE (i3
, dest
)
1193 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1194 /* Don't substitute into a non-local goto, this confuses CFG. */
1195 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1197 /* Don't combine the end of a libcall into anything. */
1198 /* ??? This gives worse code, and appears to be unnecessary, since no
1199 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1200 use REG_RETVAL notes for noconflict blocks, but other code here
1201 makes sure that those insns don't disappear. */
1202 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1204 /* Make sure that DEST is not used after SUCC but before I3. */
1205 || (succ
&& ! all_adjacent
1206 && reg_used_between_p (dest
, succ
, i3
))
1207 /* Make sure that the value that is to be substituted for the register
1208 does not use any registers whose values alter in between. However,
1209 If the insns are adjacent, a use can't cross a set even though we
1210 think it might (this can happen for a sequence of insns each setting
1211 the same destination; last_set of that register might point to
1212 a NOTE). If INSN has a REG_EQUIV note, the register is always
1213 equivalent to the memory so the substitution is valid even if there
1214 are intervening stores. Also, don't move a volatile asm or
1215 UNSPEC_VOLATILE across any other insns. */
1218 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1219 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1220 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1221 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1222 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1223 better register allocation by not doing the combine. */
1224 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1225 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1226 /* Don't combine across a CALL_INSN, because that would possibly
1227 change whether the life span of some REGs crosses calls or not,
1228 and it is a pain to update that information.
1229 Exception: if source is a constant, moving it later can't hurt.
1230 Accept that special case, because it helps -fforce-addr a lot. */
1231 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1234 /* DEST must either be a REG or CC0. */
1237 /* If register alignment is being enforced for multi-word items in all
1238 cases except for parameters, it is possible to have a register copy
1239 insn referencing a hard register that is not allowed to contain the
1240 mode being copied and which would not be valid as an operand of most
1241 insns. Eliminate this problem by not combining with such an insn.
1243 Also, on some machines we don't want to extend the life of a hard
1247 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1248 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1249 /* Don't extend the life of a hard register unless it is
1250 user variable (if we have few registers) or it can't
1251 fit into the desired register (meaning something special
1253 Also avoid substituting a return register into I3, because
1254 reload can't handle a conflict with constraints of other
1256 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1257 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1260 else if (GET_CODE (dest
) != CC0
)
1264 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1265 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1266 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1268 /* Don't substitute for a register intended as a clobberable
1270 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1271 if (rtx_equal_p (reg
, dest
))
1274 /* If the clobber represents an earlyclobber operand, we must not
1275 substitute an expression containing the clobbered register.
1276 As we do not analyse the constraint strings here, we have to
1277 make the conservative assumption. However, if the register is
1278 a fixed hard reg, the clobber cannot represent any operand;
1279 we leave it up to the machine description to either accept or
1280 reject use-and-clobber patterns. */
1282 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1283 || !fixed_regs
[REGNO (reg
)])
1284 if (reg_overlap_mentioned_p (reg
, src
))
1288 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1289 or not), reject, unless nothing volatile comes between it and I3 */
1291 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1293 /* Make sure succ doesn't contain a volatile reference. */
1294 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1297 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1298 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1302 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1303 to be an explicit register variable, and was chosen for a reason. */
1305 if (GET_CODE (src
) == ASM_OPERANDS
1306 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1309 /* If there are any volatile insns between INSN and I3, reject, because
1310 they might affect machine state. */
1312 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1313 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1316 /* If INSN or I2 contains an autoincrement or autodecrement,
1317 make sure that register is not used between there and I3,
1318 and not already used in I3 either.
1319 Also insist that I3 not be a jump; if it were one
1320 and the incremented register were spilled, we would lose. */
1323 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1324 if (REG_NOTE_KIND (link
) == REG_INC
1326 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1327 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1332 /* Don't combine an insn that follows a CC0-setting insn.
1333 An insn that uses CC0 must not be separated from the one that sets it.
1334 We do, however, allow I2 to follow a CC0-setting insn if that insn
1335 is passed as I1; in that case it will be deleted also.
1336 We also allow combining in this case if all the insns are adjacent
1337 because that would leave the two CC0 insns adjacent as well.
1338 It would be more logical to test whether CC0 occurs inside I1 or I2,
1339 but that would be much slower, and this ought to be equivalent. */
1341 p
= prev_nonnote_insn (insn
);
1342 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
1347 /* If we get here, we have passed all the tests and the combination is
1356 /* LOC is the location within I3 that contains its pattern or the component
1357 of a PARALLEL of the pattern. We validate that it is valid for combining.
1359 One problem is if I3 modifies its output, as opposed to replacing it
1360 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1361 so would produce an insn that is not equivalent to the original insns.
1365 (set (reg:DI 101) (reg:DI 100))
1366 (set (subreg:SI (reg:DI 101) 0) <foo>)
1368 This is NOT equivalent to:
1370 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1371 (set (reg:DI 101) (reg:DI 100))])
1373 Not only does this modify 100 (in which case it might still be valid
1374 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1376 We can also run into a problem if I2 sets a register that I1
1377 uses and I1 gets directly substituted into I3 (not via I2). In that
1378 case, we would be getting the wrong value of I2DEST into I3, so we
1379 must reject the combination. This case occurs when I2 and I1 both
1380 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1381 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1382 of a SET must prevent combination from occurring.
1384 Before doing the above check, we first try to expand a field assignment
1385 into a set of logical operations.
1387 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1388 we place a register that is both set and used within I3. If more than one
1389 such register is detected, we fail.
1391 Return 1 if the combination is valid, zero otherwise. */
1394 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1395 int i1_not_in_src
, rtx
*pi3dest_killed
)
1399 if (GET_CODE (x
) == SET
)
1402 rtx dest
= SET_DEST (set
);
1403 rtx src
= SET_SRC (set
);
1404 rtx inner_dest
= dest
;
1406 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1407 || GET_CODE (inner_dest
) == SUBREG
1408 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1409 inner_dest
= XEXP (inner_dest
, 0);
1411 /* Check for the case where I3 modifies its output, as discussed
1412 above. We don't want to prevent pseudos from being combined
1413 into the address of a MEM, so only prevent the combination if
1414 i1 or i2 set the same MEM. */
1415 if ((inner_dest
!= dest
&&
1416 (!MEM_P (inner_dest
)
1417 || rtx_equal_p (i2dest
, inner_dest
)
1418 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1419 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1420 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1422 /* This is the same test done in can_combine_p except we can't test
1423 all_adjacent; we don't have to, since this instruction will stay
1424 in place, thus we are not considering increasing the lifetime of
1427 Also, if this insn sets a function argument, combining it with
1428 something that might need a spill could clobber a previous
1429 function argument; the all_adjacent test in can_combine_p also
1430 checks this; here, we do a more specific test for this case. */
1432 || (REG_P (inner_dest
)
1433 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1434 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1435 GET_MODE (inner_dest
))))
1436 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1439 /* If DEST is used in I3, it is being killed in this insn,
1440 so record that for later.
1441 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1442 STACK_POINTER_REGNUM, since these are always considered to be
1443 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1444 if (pi3dest_killed
&& REG_P (dest
)
1445 && reg_referenced_p (dest
, PATTERN (i3
))
1446 && REGNO (dest
) != FRAME_POINTER_REGNUM
1447 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1448 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1450 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1451 && (REGNO (dest
) != ARG_POINTER_REGNUM
1452 || ! fixed_regs
[REGNO (dest
)])
1454 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1456 if (*pi3dest_killed
)
1459 *pi3dest_killed
= dest
;
1463 else if (GET_CODE (x
) == PARALLEL
)
1467 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1468 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1469 i1_not_in_src
, pi3dest_killed
))
1476 /* Return 1 if X is an arithmetic expression that contains a multiplication
1477 and division. We don't count multiplications by powers of two here. */
1480 contains_muldiv (rtx x
)
1482 switch (GET_CODE (x
))
1484 case MOD
: case DIV
: case UMOD
: case UDIV
:
1488 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1489 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1492 return contains_muldiv (XEXP (x
, 0))
1493 || contains_muldiv (XEXP (x
, 1));
1496 return contains_muldiv (XEXP (x
, 0));
1502 /* Determine whether INSN can be used in a combination. Return nonzero if
1503 not. This is used in try_combine to detect early some cases where we
1504 can't perform combinations. */
1507 cant_combine_insn_p (rtx insn
)
1512 /* If this isn't really an insn, we can't do anything.
1513 This can occur when flow deletes an insn that it has merged into an
1514 auto-increment address. */
1515 if (! INSN_P (insn
))
1518 /* Never combine loads and stores involving hard regs that are likely
1519 to be spilled. The register allocator can usually handle such
1520 reg-reg moves by tying. If we allow the combiner to make
1521 substitutions of likely-spilled regs, we may abort in reload.
1522 As an exception, we allow combinations involving fixed regs; these are
1523 not available to the register allocator so there's no risk involved. */
1525 set
= single_set (insn
);
1528 src
= SET_SRC (set
);
1529 dest
= SET_DEST (set
);
1530 if (GET_CODE (src
) == SUBREG
)
1531 src
= SUBREG_REG (src
);
1532 if (GET_CODE (dest
) == SUBREG
)
1533 dest
= SUBREG_REG (dest
);
1534 if (REG_P (src
) && REG_P (dest
)
1535 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1536 && ! fixed_regs
[REGNO (src
)]
1537 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1538 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1539 && ! fixed_regs
[REGNO (dest
)]
1540 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1546 /* Adjust INSN after we made a change to its destination.
1548 Changing the destination can invalidate notes that say something about
1549 the results of the insn and a LOG_LINK pointing to the insn. */
1552 adjust_for_new_dest (rtx insn
)
1556 /* For notes, be conservative and simply remove them. */
1557 loc
= ®_NOTES (insn
);
1560 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1561 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1562 *loc
= XEXP (*loc
, 1);
1564 loc
= &XEXP (*loc
, 1);
1567 /* The new insn will have a destination that was previously the destination
1568 of an insn just above it. Call distribute_links to make a LOG_LINK from
1569 the next use of that destination. */
1570 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1573 /* Try to combine the insns I1 and I2 into I3.
1574 Here I1 and I2 appear earlier than I3.
1575 I1 can be zero; then we combine just I2 into I3.
1577 If we are combining three insns and the resulting insn is not recognized,
1578 try splitting it into two insns. If that happens, I2 and I3 are retained
1579 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1582 Return 0 if the combination does not work. Then nothing is changed.
1583 If we did the combination, return the insn at which combine should
1586 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1587 new direct jump instruction. */
1590 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1592 /* New patterns for I3 and I2, respectively. */
1593 rtx newpat
, newi2pat
= 0;
1594 int substed_i2
= 0, substed_i1
= 0;
1595 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1596 int added_sets_1
, added_sets_2
;
1597 /* Total number of SETs to put into I3. */
1599 /* Nonzero if I2's body now appears in I3. */
1601 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1602 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1603 /* Contains I3 if the destination of I3 is used in its source, which means
1604 that the old life of I3 is being killed. If that usage is placed into
1605 I2 and not in I3, a REG_DEAD note must be made. */
1606 rtx i3dest_killed
= 0;
1607 /* SET_DEST and SET_SRC of I2 and I1. */
1608 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1609 /* PATTERN (I2), or a copy of it in certain cases. */
1611 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1612 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1613 int i1_feeds_i3
= 0;
1614 /* Notes that must be added to REG_NOTES in I3 and I2. */
1615 rtx new_i3_notes
, new_i2_notes
;
1616 /* Notes that we substituted I3 into I2 instead of the normal case. */
1617 int i3_subst_into_i2
= 0;
1618 /* Notes that I1, I2 or I3 is a MULT operation. */
1627 /* Exit early if one of the insns involved can't be used for
1629 if (cant_combine_insn_p (i3
)
1630 || cant_combine_insn_p (i2
)
1631 || (i1
&& cant_combine_insn_p (i1
))
1632 /* We also can't do anything if I3 has a
1633 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1636 /* ??? This gives worse code, and appears to be unnecessary, since no
1637 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1638 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1644 undobuf
.other_insn
= 0;
1646 /* Reset the hard register usage information. */
1647 CLEAR_HARD_REG_SET (newpat_used_regs
);
1649 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1650 code below, set I1 to be the earlier of the two insns. */
1651 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1652 temp
= i1
, i1
= i2
, i2
= temp
;
1654 added_links_insn
= 0;
1656 /* First check for one important special-case that the code below will
1657 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1658 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1659 we may be able to replace that destination with the destination of I3.
1660 This occurs in the common code where we compute both a quotient and
1661 remainder into a structure, in which case we want to do the computation
1662 directly into the structure to avoid register-register copies.
1664 Note that this case handles both multiple sets in I2 and also
1665 cases where I2 has a number of CLOBBER or PARALLELs.
1667 We make very conservative checks below and only try to handle the
1668 most common cases of this. For example, we only handle the case
1669 where I2 and I3 are adjacent to avoid making difficult register
1672 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
1673 && REG_P (SET_SRC (PATTERN (i3
)))
1674 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1675 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1676 && GET_CODE (PATTERN (i2
)) == PARALLEL
1677 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1678 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1679 below would need to check what is inside (and reg_overlap_mentioned_p
1680 doesn't support those codes anyway). Don't allow those destinations;
1681 the resulting insn isn't likely to be recognized anyway. */
1682 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1683 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1684 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1685 SET_DEST (PATTERN (i3
)))
1686 && next_real_insn (i2
) == i3
)
1688 rtx p2
= PATTERN (i2
);
1690 /* Make sure that the destination of I3,
1691 which we are going to substitute into one output of I2,
1692 is not used within another output of I2. We must avoid making this:
1693 (parallel [(set (mem (reg 69)) ...)
1694 (set (reg 69) ...)])
1695 which is not well-defined as to order of actions.
1696 (Besides, reload can't handle output reloads for this.)
1698 The problem can also happen if the dest of I3 is a memory ref,
1699 if another dest in I2 is an indirect memory ref. */
1700 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1701 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1702 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1703 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1704 SET_DEST (XVECEXP (p2
, 0, i
))))
1707 if (i
== XVECLEN (p2
, 0))
1708 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1709 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1710 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1711 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1716 subst_low_cuid
= INSN_CUID (i2
);
1718 added_sets_2
= added_sets_1
= 0;
1719 i2dest
= SET_SRC (PATTERN (i3
));
1721 /* Replace the dest in I2 with our dest and make the resulting
1722 insn the new pattern for I3. Then skip to where we
1723 validate the pattern. Everything was set up above. */
1724 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1725 SET_DEST (PATTERN (i3
)));
1728 i3_subst_into_i2
= 1;
1729 goto validate_replacement
;
1733 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1734 one of those words to another constant, merge them by making a new
1737 && (temp
= single_set (i2
)) != 0
1738 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1739 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1740 && REG_P (SET_DEST (temp
))
1741 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1742 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1743 && GET_CODE (PATTERN (i3
)) == SET
1744 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1745 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1746 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1747 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1748 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1750 HOST_WIDE_INT lo
, hi
;
1752 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1753 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1756 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1757 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1760 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1762 /* We don't handle the case of the target word being wider
1763 than a host wide int. */
1764 gcc_assert (HOST_BITS_PER_WIDE_INT
>= BITS_PER_WORD
);
1766 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1767 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1768 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1770 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1771 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1772 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1774 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1775 >> (HOST_BITS_PER_WIDE_INT
- 1));
1777 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1778 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1779 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1780 (INTVAL (SET_SRC (PATTERN (i3
)))));
1782 hi
= lo
< 0 ? -1 : 0;
1785 /* We don't handle the case of the higher word not fitting
1786 entirely in either hi or lo. */
1791 subst_low_cuid
= INSN_CUID (i2
);
1792 added_sets_2
= added_sets_1
= 0;
1793 i2dest
= SET_DEST (temp
);
1795 SUBST (SET_SRC (temp
),
1796 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1798 newpat
= PATTERN (i2
);
1799 goto validate_replacement
;
1803 /* If we have no I1 and I2 looks like:
1804 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1806 make up a dummy I1 that is
1809 (set (reg:CC X) (compare:CC Y (const_int 0)))
1811 (We can ignore any trailing CLOBBERs.)
1813 This undoes a previous combination and allows us to match a branch-and-
1816 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1817 && XVECLEN (PATTERN (i2
), 0) >= 2
1818 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1819 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1821 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1822 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1823 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1824 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
1825 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1826 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1828 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1829 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1834 /* We make I1 with the same INSN_UID as I2. This gives it
1835 the same INSN_CUID for value tracking. Our fake I1 will
1836 never appear in the insn stream so giving it the same INSN_UID
1837 as I2 will not cause a problem. */
1839 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1840 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1841 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1844 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1845 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1846 SET_DEST (PATTERN (i1
)));
1851 /* Verify that I2 and I1 are valid for combining. */
1852 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1853 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1859 /* Record whether I2DEST is used in I2SRC and similarly for the other
1860 cases. Knowing this will help in register status updating below. */
1861 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1862 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1863 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1865 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1867 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1869 /* Ensure that I3's pattern can be the destination of combines. */
1870 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1871 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1878 /* See if any of the insns is a MULT operation. Unless one is, we will
1879 reject a combination that is, since it must be slower. Be conservative
1881 if (GET_CODE (i2src
) == MULT
1882 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1883 || (GET_CODE (PATTERN (i3
)) == SET
1884 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1887 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1888 We used to do this EXCEPT in one case: I3 has a post-inc in an
1889 output operand. However, that exception can give rise to insns like
1891 which is a famous insn on the PDP-11 where the value of r3 used as the
1892 source was model-dependent. Avoid this sort of thing. */
1895 if (!(GET_CODE (PATTERN (i3
)) == SET
1896 && REG_P (SET_SRC (PATTERN (i3
)))
1897 && MEM_P (SET_DEST (PATTERN (i3
)))
1898 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1899 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1900 /* It's not the exception. */
1903 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1904 if (REG_NOTE_KIND (link
) == REG_INC
1905 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1907 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1914 /* See if the SETs in I1 or I2 need to be kept around in the merged
1915 instruction: whenever the value set there is still needed past I3.
1916 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1918 For the SET in I1, we have two cases: If I1 and I2 independently
1919 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1920 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1921 in I1 needs to be kept around unless I1DEST dies or is set in either
1922 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1923 I1DEST. If so, we know I1 feeds into I2. */
1925 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1928 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1929 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1931 /* If the set in I2 needs to be kept around, we must make a copy of
1932 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1933 PATTERN (I2), we are only substituting for the original I1DEST, not into
1934 an already-substituted copy. This also prevents making self-referential
1935 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1938 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1939 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1943 i2pat
= copy_rtx (i2pat
);
1947 /* Substitute in the latest insn for the regs set by the earlier ones. */
1949 maxreg
= max_reg_num ();
1953 /* It is possible that the source of I2 or I1 may be performing an
1954 unneeded operation, such as a ZERO_EXTEND of something that is known
1955 to have the high part zero. Handle that case by letting subst look at
1956 the innermost one of them.
1958 Another way to do this would be to have a function that tries to
1959 simplify a single insn instead of merging two or more insns. We don't
1960 do this because of the potential of infinite loops and because
1961 of the potential extra memory required. However, doing it the way
1962 we are is a bit of a kludge and doesn't catch all cases.
1964 But only do this if -fexpensive-optimizations since it slows things down
1965 and doesn't usually win. */
1967 if (flag_expensive_optimizations
)
1969 /* Pass pc_rtx so no substitutions are done, just simplifications. */
1972 subst_low_cuid
= INSN_CUID (i1
);
1973 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1977 subst_low_cuid
= INSN_CUID (i2
);
1978 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1983 /* Many machines that don't use CC0 have insns that can both perform an
1984 arithmetic operation and set the condition code. These operations will
1985 be represented as a PARALLEL with the first element of the vector
1986 being a COMPARE of an arithmetic operation with the constant zero.
1987 The second element of the vector will set some pseudo to the result
1988 of the same arithmetic operation. If we simplify the COMPARE, we won't
1989 match such a pattern and so will generate an extra insn. Here we test
1990 for this case, where both the comparison and the operation result are
1991 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1992 I2SRC. Later we will make the PARALLEL that contains I2. */
1994 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1995 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1996 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1997 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1999 #ifdef SELECT_CC_MODE
2001 enum machine_mode compare_mode
;
2004 newpat
= PATTERN (i3
);
2005 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
2009 #ifdef SELECT_CC_MODE
2010 /* See if a COMPARE with the operand we substituted in should be done
2011 with the mode that is currently being used. If not, do the same
2012 processing we do in `subst' for a SET; namely, if the destination
2013 is used only once, try to replace it with a register of the proper
2014 mode and also replace the COMPARE. */
2015 if (undobuf
.other_insn
== 0
2016 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
2017 &undobuf
.other_insn
))
2018 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
2020 != GET_MODE (SET_DEST (newpat
))))
2022 unsigned int regno
= REGNO (SET_DEST (newpat
));
2023 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
2025 if (regno
< FIRST_PSEUDO_REGISTER
2026 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
2027 && ! REG_USERVAR_P (SET_DEST (newpat
))))
2029 if (regno
>= FIRST_PSEUDO_REGISTER
)
2030 SUBST (regno_reg_rtx
[regno
], new_dest
);
2032 SUBST (SET_DEST (newpat
), new_dest
);
2033 SUBST (XEXP (*cc_use
, 0), new_dest
);
2034 SUBST (SET_SRC (newpat
),
2035 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
2038 undobuf
.other_insn
= 0;
2045 n_occurrences
= 0; /* `subst' counts here */
2047 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2048 need to make a unique copy of I2SRC each time we substitute it
2049 to avoid self-referential rtl. */
2051 subst_low_cuid
= INSN_CUID (i2
);
2052 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
2053 ! i1_feeds_i3
&& i1dest_in_i1src
);
2056 /* Record whether i2's body now appears within i3's body. */
2057 i2_is_used
= n_occurrences
;
2060 /* If we already got a failure, don't try to do more. Otherwise,
2061 try to substitute in I1 if we have it. */
2063 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
2065 /* Before we can do this substitution, we must redo the test done
2066 above (see detailed comments there) that ensures that I1DEST
2067 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2069 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
2077 subst_low_cuid
= INSN_CUID (i1
);
2078 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
2082 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2083 to count all the ways that I2SRC and I1SRC can be used. */
2084 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
2085 && i2_is_used
+ added_sets_2
> 1)
2086 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
2087 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
2089 /* Fail if we tried to make a new register (we used to abort, but there's
2090 really no reason to). */
2091 || max_reg_num () != maxreg
2092 /* Fail if we couldn't do something and have a CLOBBER. */
2093 || GET_CODE (newpat
) == CLOBBER
2094 /* Fail if this new pattern is a MULT and we didn't have one before
2095 at the outer level. */
2096 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2103 /* If the actions of the earlier insns must be kept
2104 in addition to substituting them into the latest one,
2105 we must make a new PARALLEL for the latest insn
2106 to hold additional the SETs. */
2108 if (added_sets_1
|| added_sets_2
)
2112 if (GET_CODE (newpat
) == PARALLEL
)
2114 rtvec old
= XVEC (newpat
, 0);
2115 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2116 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2117 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2118 sizeof (old
->elem
[0]) * old
->num_elem
);
2123 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2124 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2125 XVECEXP (newpat
, 0, 0) = old
;
2129 XVECEXP (newpat
, 0, --total_sets
)
2130 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2131 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2135 /* If there is no I1, use I2's body as is. We used to also not do
2136 the subst call below if I2 was substituted into I3,
2137 but that could lose a simplification. */
2139 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2141 /* See comment where i2pat is assigned. */
2142 XVECEXP (newpat
, 0, --total_sets
)
2143 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2147 /* We come here when we are replacing a destination in I2 with the
2148 destination of I3. */
2149 validate_replacement
:
2151 /* Note which hard regs this insn has as inputs. */
2152 mark_used_regs_combine (newpat
);
2154 /* Is the result of combination a valid instruction? */
2155 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2157 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2158 the second SET's destination is a register that is unused and isn't
2159 marked as an instruction that might trap in an EH region. In that case,
2160 we just need the first SET. This can occur when simplifying a divmod
2161 insn. We *must* test for this case here because the code below that
2162 splits two independent SETs doesn't handle this case correctly when it
2163 updates the register status.
2165 It's pointless doing this if we originally had two sets, one from
2166 i3, and one from i2. Combining then splitting the parallel results
2167 in the original i2 again plus an invalid insn (which we delete).
2168 The net effect is only to move instructions around, which makes
2169 debug info less accurate.
2171 Also check the case where the first SET's destination is unused.
2172 That would not cause incorrect code, but does cause an unneeded
2175 if (insn_code_number
< 0
2176 && !(added_sets_2
&& i1
== 0)
2177 && GET_CODE (newpat
) == PARALLEL
2178 && XVECLEN (newpat
, 0) == 2
2179 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2180 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2181 && asm_noperands (newpat
) < 0)
2183 rtx set0
= XVECEXP (newpat
, 0, 0);
2184 rtx set1
= XVECEXP (newpat
, 0, 1);
2187 if (((REG_P (SET_DEST (set1
))
2188 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2189 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2190 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2191 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2192 || INTVAL (XEXP (note
, 0)) <= 0)
2193 && ! side_effects_p (SET_SRC (set1
)))
2196 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2199 else if (((REG_P (SET_DEST (set0
))
2200 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2201 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2202 && find_reg_note (i3
, REG_UNUSED
,
2203 SUBREG_REG (SET_DEST (set0
)))))
2204 && (!(note
= find_reg_note (i3
, REG_EH_REGION
, NULL_RTX
))
2205 || INTVAL (XEXP (note
, 0)) <= 0)
2206 && ! side_effects_p (SET_SRC (set0
)))
2209 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2211 if (insn_code_number
>= 0)
2213 /* If we will be able to accept this, we have made a
2214 change to the destination of I3. This requires us to
2215 do a few adjustments. */
2217 PATTERN (i3
) = newpat
;
2218 adjust_for_new_dest (i3
);
2223 /* If we were combining three insns and the result is a simple SET
2224 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2225 insns. There are two ways to do this. It can be split using a
2226 machine-specific method (like when you have an addition of a large
2227 constant) or by combine in the function find_split_point. */
2229 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2230 && asm_noperands (newpat
) < 0)
2232 rtx m_split
, *split
;
2233 rtx ni2dest
= i2dest
;
2235 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2236 use I2DEST as a scratch register will help. In the latter case,
2237 convert I2DEST to the mode of the source of NEWPAT if we can. */
2239 m_split
= split_insns (newpat
, i3
);
2241 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2242 inputs of NEWPAT. */
2244 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2245 possible to try that as a scratch reg. This would require adding
2246 more code to make it work though. */
2248 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2250 /* If I2DEST is a hard register or the only use of a pseudo,
2251 we can change its mode. */
2252 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2253 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2255 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2256 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2257 && ! REG_USERVAR_P (i2dest
))))
2258 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2261 m_split
= split_insns (gen_rtx_PARALLEL
2263 gen_rtvec (2, newpat
,
2264 gen_rtx_CLOBBER (VOIDmode
,
2267 /* If the split with the mode-changed register didn't work, try
2268 the original register. */
2269 if (! m_split
&& ni2dest
!= i2dest
)
2272 m_split
= split_insns (gen_rtx_PARALLEL
2274 gen_rtvec (2, newpat
,
2275 gen_rtx_CLOBBER (VOIDmode
,
2281 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2283 m_split
= PATTERN (m_split
);
2284 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2285 if (insn_code_number
>= 0)
2288 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2289 && (next_real_insn (i2
) == i3
2290 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2293 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2294 newi2pat
= PATTERN (m_split
);
2296 i3set
= single_set (NEXT_INSN (m_split
));
2297 i2set
= single_set (m_split
);
2299 /* In case we changed the mode of I2DEST, replace it in the
2300 pseudo-register table here. We can't do it above in case this
2301 code doesn't get executed and we do a split the other way. */
2303 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2304 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2306 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2308 /* If I2 or I3 has multiple SETs, we won't know how to track
2309 register status, so don't use these insns. If I2's destination
2310 is used between I2 and I3, we also can't use these insns. */
2312 if (i2_code_number
>= 0 && i2set
&& i3set
2313 && (next_real_insn (i2
) == i3
2314 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2315 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2317 if (insn_code_number
>= 0)
2320 /* It is possible that both insns now set the destination of I3.
2321 If so, we must show an extra use of it. */
2323 if (insn_code_number
>= 0)
2325 rtx new_i3_dest
= SET_DEST (i3set
);
2326 rtx new_i2_dest
= SET_DEST (i2set
);
2328 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2329 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2330 || GET_CODE (new_i3_dest
) == SUBREG
)
2331 new_i3_dest
= XEXP (new_i3_dest
, 0);
2333 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2334 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2335 || GET_CODE (new_i2_dest
) == SUBREG
)
2336 new_i2_dest
= XEXP (new_i2_dest
, 0);
2338 if (REG_P (new_i3_dest
)
2339 && REG_P (new_i2_dest
)
2340 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2341 REG_N_SETS (REGNO (new_i2_dest
))++;
2345 /* If we can split it and use I2DEST, go ahead and see if that
2346 helps things be recognized. Verify that none of the registers
2347 are set between I2 and I3. */
2348 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2352 /* We need I2DEST in the proper mode. If it is a hard register
2353 or the only use of a pseudo, we can change its mode. */
2354 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2355 || GET_MODE (*split
) == VOIDmode
2356 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2357 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2358 && ! REG_USERVAR_P (i2dest
)))
2359 && (next_real_insn (i2
) == i3
2360 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2361 /* We can't overwrite I2DEST if its value is still used by
2363 && ! reg_referenced_p (i2dest
, newpat
))
2365 rtx newdest
= i2dest
;
2366 enum rtx_code split_code
= GET_CODE (*split
);
2367 enum machine_mode split_mode
= GET_MODE (*split
);
2369 /* Get NEWDEST as a register in the proper mode. We have already
2370 validated that we can do this. */
2371 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2373 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2375 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2376 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2379 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2380 an ASHIFT. This can occur if it was inside a PLUS and hence
2381 appeared to be a memory address. This is a kludge. */
2382 if (split_code
== MULT
2383 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2384 && INTVAL (XEXP (*split
, 1)) > 0
2385 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2387 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2388 XEXP (*split
, 0), GEN_INT (i
)));
2389 /* Update split_code because we may not have a multiply
2391 split_code
= GET_CODE (*split
);
2394 #ifdef INSN_SCHEDULING
2395 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2396 be written as a ZERO_EXTEND. */
2397 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
2399 #ifdef LOAD_EXTEND_OP
2400 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2401 what it really is. */
2402 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2404 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2405 SUBREG_REG (*split
)));
2408 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2409 SUBREG_REG (*split
)));
2413 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2414 SUBST (*split
, newdest
);
2415 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2417 /* If the split point was a MULT and we didn't have one before,
2418 don't use one now. */
2419 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2420 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2424 /* Check for a case where we loaded from memory in a narrow mode and
2425 then sign extended it, but we need both registers. In that case,
2426 we have a PARALLEL with both loads from the same memory location.
2427 We can split this into a load from memory followed by a register-register
2428 copy. This saves at least one insn, more if register allocation can
2431 We cannot do this if the destination of the first assignment is a
2432 condition code register or cc0. We eliminate this case by making sure
2433 the SET_DEST and SET_SRC have the same mode.
2435 We cannot do this if the destination of the second assignment is
2436 a register that we have already assumed is zero-extended. Similarly
2437 for a SUBREG of such a register. */
2439 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2440 && GET_CODE (newpat
) == PARALLEL
2441 && XVECLEN (newpat
, 0) == 2
2442 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2443 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2444 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2445 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2446 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2447 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2448 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2449 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2451 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2452 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2453 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2455 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2456 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2457 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2458 && (reg_stat
[REGNO (temp
)].nonzero_bits
2459 != GET_MODE_MASK (word_mode
))))
2460 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2461 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2463 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
2464 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2465 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2466 && (reg_stat
[REGNO (temp
)].nonzero_bits
2467 != GET_MODE_MASK (word_mode
)))))
2468 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2469 SET_SRC (XVECEXP (newpat
, 0, 1)))
2470 && ! find_reg_note (i3
, REG_UNUSED
,
2471 SET_DEST (XVECEXP (newpat
, 0, 0))))
2475 newi2pat
= XVECEXP (newpat
, 0, 0);
2476 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2477 newpat
= XVECEXP (newpat
, 0, 1);
2478 SUBST (SET_SRC (newpat
),
2479 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2480 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2482 if (i2_code_number
>= 0)
2483 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2485 if (insn_code_number
>= 0)
2489 /* Similarly, check for a case where we have a PARALLEL of two independent
2490 SETs but we started with three insns. In this case, we can do the sets
2491 as two separate insns. This case occurs when some SET allows two
2492 other insns to combine, but the destination of that SET is still live. */
2494 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2495 && GET_CODE (newpat
) == PARALLEL
2496 && XVECLEN (newpat
, 0) == 2
2497 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2498 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2499 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2500 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2501 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2502 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2503 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2505 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2506 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2507 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2508 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2509 XVECEXP (newpat
, 0, 0))
2510 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2511 XVECEXP (newpat
, 0, 1))
2512 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2513 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2515 /* Normally, it doesn't matter which of the two is done first,
2516 but it does if one references cc0. In that case, it has to
2519 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2521 newi2pat
= XVECEXP (newpat
, 0, 0);
2522 newpat
= XVECEXP (newpat
, 0, 1);
2527 newi2pat
= XVECEXP (newpat
, 0, 1);
2528 newpat
= XVECEXP (newpat
, 0, 0);
2531 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2533 if (i2_code_number
>= 0)
2534 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2537 /* If it still isn't recognized, fail and change things back the way they
2539 if ((insn_code_number
< 0
2540 /* Is the result a reasonable ASM_OPERANDS? */
2541 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2547 /* If we had to change another insn, make sure it is valid also. */
2548 if (undobuf
.other_insn
)
2550 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2551 rtx new_other_notes
;
2554 CLEAR_HARD_REG_SET (newpat_used_regs
);
2556 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2559 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2565 PATTERN (undobuf
.other_insn
) = other_pat
;
2567 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2568 are still valid. Then add any non-duplicate notes added by
2569 recog_for_combine. */
2570 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2572 next
= XEXP (note
, 1);
2574 if (REG_NOTE_KIND (note
) == REG_UNUSED
2575 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2577 if (REG_P (XEXP (note
, 0)))
2578 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2580 remove_note (undobuf
.other_insn
, note
);
2584 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2585 if (REG_P (XEXP (note
, 0)))
2586 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2588 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2589 undobuf
.other_insn
, NULL_RTX
);
2592 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2593 they are adjacent to each other or not. */
2595 rtx p
= prev_nonnote_insn (i3
);
2596 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
2597 && sets_cc0_p (newi2pat
))
2605 /* Only allow this combination if insn_rtx_costs reports that the
2606 replacement instructions are cheaper than the originals. */
2607 if (!combine_validate_cost (i1
, i2
, i3
, newpat
, newi2pat
))
2613 /* We now know that we can do this combination. Merge the insns and
2614 update the status of registers and LOG_LINKS. */
2622 /* I3 now uses what used to be its destination and which is now
2623 I2's destination. This requires us to do a few adjustments. */
2624 PATTERN (i3
) = newpat
;
2625 adjust_for_new_dest (i3
);
2627 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2630 However, some later insn might be using I2's dest and have
2631 a LOG_LINK pointing at I3. We must remove this link.
2632 The simplest way to remove the link is to point it at I1,
2633 which we know will be a NOTE. */
2635 /* newi2pat is usually a SET here; however, recog_for_combine might
2636 have added some clobbers. */
2637 if (GET_CODE (newi2pat
) == PARALLEL
)
2638 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
2640 ni2dest
= SET_DEST (newi2pat
);
2642 for (insn
= NEXT_INSN (i3
);
2643 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2644 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
2645 insn
= NEXT_INSN (insn
))
2647 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2649 for (link
= LOG_LINKS (insn
); link
;
2650 link
= XEXP (link
, 1))
2651 if (XEXP (link
, 0) == i3
)
2652 XEXP (link
, 0) = i1
;
2660 rtx i3notes
, i2notes
, i1notes
= 0;
2661 rtx i3links
, i2links
, i1links
= 0;
2665 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2667 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2668 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2670 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2672 /* Ensure that we do not have something that should not be shared but
2673 occurs multiple times in the new insns. Check this by first
2674 resetting all the `used' flags and then copying anything is shared. */
2676 reset_used_flags (i3notes
);
2677 reset_used_flags (i2notes
);
2678 reset_used_flags (i1notes
);
2679 reset_used_flags (newpat
);
2680 reset_used_flags (newi2pat
);
2681 if (undobuf
.other_insn
)
2682 reset_used_flags (PATTERN (undobuf
.other_insn
));
2684 i3notes
= copy_rtx_if_shared (i3notes
);
2685 i2notes
= copy_rtx_if_shared (i2notes
);
2686 i1notes
= copy_rtx_if_shared (i1notes
);
2687 newpat
= copy_rtx_if_shared (newpat
);
2688 newi2pat
= copy_rtx_if_shared (newi2pat
);
2689 if (undobuf
.other_insn
)
2690 reset_used_flags (PATTERN (undobuf
.other_insn
));
2692 INSN_CODE (i3
) = insn_code_number
;
2693 PATTERN (i3
) = newpat
;
2695 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
2697 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2699 reset_used_flags (call_usage
);
2700 call_usage
= copy_rtx (call_usage
);
2703 replace_rtx (call_usage
, i2dest
, i2src
);
2706 replace_rtx (call_usage
, i1dest
, i1src
);
2708 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2711 if (undobuf
.other_insn
)
2712 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2714 /* We had one special case above where I2 had more than one set and
2715 we replaced a destination of one of those sets with the destination
2716 of I3. In that case, we have to update LOG_LINKS of insns later
2717 in this basic block. Note that this (expensive) case is rare.
2719 Also, in this case, we must pretend that all REG_NOTEs for I2
2720 actually came from I3, so that REG_UNUSED notes from I2 will be
2721 properly handled. */
2723 if (i3_subst_into_i2
)
2725 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2726 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2727 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
2728 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2729 && ! find_reg_note (i2
, REG_UNUSED
,
2730 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2731 for (temp
= NEXT_INSN (i2
);
2732 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2733 || BB_HEAD (this_basic_block
) != temp
);
2734 temp
= NEXT_INSN (temp
))
2735 if (temp
!= i3
&& INSN_P (temp
))
2736 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2737 if (XEXP (link
, 0) == i2
)
2738 XEXP (link
, 0) = i3
;
2743 while (XEXP (link
, 1))
2744 link
= XEXP (link
, 1);
2745 XEXP (link
, 1) = i2notes
;
2759 INSN_CODE (i2
) = i2_code_number
;
2760 PATTERN (i2
) = newi2pat
;
2763 SET_INSN_DELETED (i2
);
2769 SET_INSN_DELETED (i1
);
2772 /* Get death notes for everything that is now used in either I3 or
2773 I2 and used to die in a previous insn. If we built two new
2774 patterns, move from I1 to I2 then I2 to I3 so that we get the
2775 proper movement on registers that I2 modifies. */
2779 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2780 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2783 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2786 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2788 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2790 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2792 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2794 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2796 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2797 know these are REG_UNUSED and want them to go to the desired insn,
2798 so we always pass it as i3. We have not counted the notes in
2799 reg_n_deaths yet, so we need to do so now. */
2801 if (newi2pat
&& new_i2_notes
)
2803 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2804 if (REG_P (XEXP (temp
, 0)))
2805 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2807 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2812 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2813 if (REG_P (XEXP (temp
, 0)))
2814 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2816 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2819 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2820 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2821 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2822 in that case, it might delete I2. Similarly for I2 and I1.
2823 Show an additional death due to the REG_DEAD note we make here. If
2824 we discard it in distribute_notes, we will decrement it again. */
2828 if (REG_P (i3dest_killed
))
2829 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2831 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2832 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2834 NULL_RTX
, i2
, NULL_RTX
);
2836 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2838 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2841 if (i2dest_in_i2src
)
2844 REG_N_DEATHS (REGNO (i2dest
))++;
2846 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2847 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2848 NULL_RTX
, i2
, NULL_RTX
);
2850 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2851 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2854 if (i1dest_in_i1src
)
2857 REG_N_DEATHS (REGNO (i1dest
))++;
2859 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2860 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2861 NULL_RTX
, i2
, NULL_RTX
);
2863 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2864 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2867 distribute_links (i3links
);
2868 distribute_links (i2links
);
2869 distribute_links (i1links
);
2874 rtx i2_insn
= 0, i2_val
= 0, set
;
2876 /* The insn that used to set this register doesn't exist, and
2877 this life of the register may not exist either. See if one of
2878 I3's links points to an insn that sets I2DEST. If it does,
2879 that is now the last known value for I2DEST. If we don't update
2880 this and I2 set the register to a value that depended on its old
2881 contents, we will get confused. If this insn is used, thing
2882 will be set correctly in combine_instructions. */
2884 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2885 if ((set
= single_set (XEXP (link
, 0))) != 0
2886 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2887 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2889 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2891 /* If the reg formerly set in I2 died only once and that was in I3,
2892 zero its use count so it won't make `reload' do any work. */
2894 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2895 && ! i2dest_in_i2src
)
2897 regno
= REGNO (i2dest
);
2898 REG_N_SETS (regno
)--;
2902 if (i1
&& REG_P (i1dest
))
2905 rtx i1_insn
= 0, i1_val
= 0, set
;
2907 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2908 if ((set
= single_set (XEXP (link
, 0))) != 0
2909 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2910 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2912 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2914 regno
= REGNO (i1dest
);
2915 if (! added_sets_1
&& ! i1dest_in_i1src
)
2916 REG_N_SETS (regno
)--;
2919 /* Update reg_stat[].nonzero_bits et al for any changes that may have
2920 been made to this insn. The order of
2921 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
2922 can affect nonzero_bits of newpat */
2924 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2925 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2927 /* Set new_direct_jump_p if a new return or simple jump instruction
2930 If I3 is now an unconditional jump, ensure that it has a
2931 BARRIER following it since it may have initially been a
2932 conditional jump. It may also be the last nonnote insn. */
2934 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2936 *new_direct_jump_p
= 1;
2937 mark_jump_label (PATTERN (i3
), i3
, 0);
2939 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2940 || !BARRIER_P (temp
))
2941 emit_barrier_after (i3
);
2944 if (undobuf
.other_insn
!= NULL_RTX
2945 && (returnjump_p (undobuf
.other_insn
)
2946 || any_uncondjump_p (undobuf
.other_insn
)))
2948 *new_direct_jump_p
= 1;
2950 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2951 || !BARRIER_P (temp
))
2952 emit_barrier_after (undobuf
.other_insn
);
2955 /* An NOOP jump does not need barrier, but it does need cleaning up
2957 if (GET_CODE (newpat
) == SET
2958 && SET_SRC (newpat
) == pc_rtx
2959 && SET_DEST (newpat
) == pc_rtx
)
2960 *new_direct_jump_p
= 1;
2963 combine_successes
++;
2966 if (added_links_insn
2967 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2968 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2969 return added_links_insn
;
2971 return newi2pat
? i2
: i3
;
2974 /* Undo all the modifications recorded in undobuf. */
2979 struct undo
*undo
, *next
;
2981 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2985 *undo
->where
.i
= undo
->old_contents
.i
;
2987 *undo
->where
.r
= undo
->old_contents
.r
;
2989 undo
->next
= undobuf
.frees
;
2990 undobuf
.frees
= undo
;
2996 /* We've committed to accepting the changes we made. Move all
2997 of the undos to the free list. */
3002 struct undo
*undo
, *next
;
3004 for (undo
= undobuf
.undos
; undo
; undo
= next
)
3007 undo
->next
= undobuf
.frees
;
3008 undobuf
.frees
= undo
;
3014 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3015 where we have an arithmetic expression and return that point. LOC will
3018 try_combine will call this function to see if an insn can be split into
3022 find_split_point (rtx
*loc
, rtx insn
)
3025 enum rtx_code code
= GET_CODE (x
);
3027 unsigned HOST_WIDE_INT len
= 0;
3028 HOST_WIDE_INT pos
= 0;
3030 rtx inner
= NULL_RTX
;
3032 /* First special-case some codes. */
3036 #ifdef INSN_SCHEDULING
3037 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3039 if (MEM_P (SUBREG_REG (x
)))
3042 return find_split_point (&SUBREG_REG (x
), insn
);
3046 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3047 using LO_SUM and HIGH. */
3048 if (GET_CODE (XEXP (x
, 0)) == CONST
3049 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
3052 gen_rtx_LO_SUM (Pmode
,
3053 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
3055 return &XEXP (XEXP (x
, 0), 0);
3059 /* If we have a PLUS whose second operand is a constant and the
3060 address is not valid, perhaps will can split it up using
3061 the machine-specific way to split large constants. We use
3062 the first pseudo-reg (one of the virtual regs) as a placeholder;
3063 it will not remain in the result. */
3064 if (GET_CODE (XEXP (x
, 0)) == PLUS
3065 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3066 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
3068 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
3069 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
3072 /* This should have produced two insns, each of which sets our
3073 placeholder. If the source of the second is a valid address,
3074 we can make put both sources together and make a split point
3078 && NEXT_INSN (seq
) != NULL_RTX
3079 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
3080 && NONJUMP_INSN_P (seq
)
3081 && GET_CODE (PATTERN (seq
)) == SET
3082 && SET_DEST (PATTERN (seq
)) == reg
3083 && ! reg_mentioned_p (reg
,
3084 SET_SRC (PATTERN (seq
)))
3085 && NONJUMP_INSN_P (NEXT_INSN (seq
))
3086 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
3087 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
3088 && memory_address_p (GET_MODE (x
),
3089 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
3091 rtx src1
= SET_SRC (PATTERN (seq
));
3092 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
3094 /* Replace the placeholder in SRC2 with SRC1. If we can
3095 find where in SRC2 it was placed, that can become our
3096 split point and we can replace this address with SRC2.
3097 Just try two obvious places. */
3099 src2
= replace_rtx (src2
, reg
, src1
);
3101 if (XEXP (src2
, 0) == src1
)
3102 split
= &XEXP (src2
, 0);
3103 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
3104 && XEXP (XEXP (src2
, 0), 0) == src1
)
3105 split
= &XEXP (XEXP (src2
, 0), 0);
3109 SUBST (XEXP (x
, 0), src2
);
3114 /* If that didn't work, perhaps the first operand is complex and
3115 needs to be computed separately, so make a split point there.
3116 This will occur on machines that just support REG + CONST
3117 and have a constant moved through some previous computation. */
3119 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
3120 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
3121 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
3122 return &XEXP (XEXP (x
, 0), 0);
3128 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3129 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3130 we need to put the operand into a register. So split at that
3133 if (SET_DEST (x
) == cc0_rtx
3134 && GET_CODE (SET_SRC (x
)) != COMPARE
3135 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
3136 && !OBJECT_P (SET_SRC (x
))
3137 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
3138 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
3139 return &SET_SRC (x
);
3142 /* See if we can split SET_SRC as it stands. */
3143 split
= find_split_point (&SET_SRC (x
), insn
);
3144 if (split
&& split
!= &SET_SRC (x
))
3147 /* See if we can split SET_DEST as it stands. */
3148 split
= find_split_point (&SET_DEST (x
), insn
);
3149 if (split
&& split
!= &SET_DEST (x
))
3152 /* See if this is a bitfield assignment with everything constant. If
3153 so, this is an IOR of an AND, so split it into that. */
3154 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3155 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
3156 <= HOST_BITS_PER_WIDE_INT
)
3157 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3158 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3159 && GET_CODE (SET_SRC (x
)) == CONST_INT
3160 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3161 + INTVAL (XEXP (SET_DEST (x
), 2)))
3162 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3163 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3165 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3166 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3167 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3168 rtx dest
= XEXP (SET_DEST (x
), 0);
3169 enum machine_mode mode
= GET_MODE (dest
);
3170 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3172 if (BITS_BIG_ENDIAN
)
3173 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3177 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3180 gen_binary (IOR
, mode
,
3181 gen_binary (AND
, mode
, dest
,
3182 gen_int_mode (~(mask
<< pos
),
3184 GEN_INT (src
<< pos
)));
3186 SUBST (SET_DEST (x
), dest
);
3188 split
= find_split_point (&SET_SRC (x
), insn
);
3189 if (split
&& split
!= &SET_SRC (x
))
3193 /* Otherwise, see if this is an operation that we can split into two.
3194 If so, try to split that. */
3195 code
= GET_CODE (SET_SRC (x
));
3200 /* If we are AND'ing with a large constant that is only a single
3201 bit and the result is only being used in a context where we
3202 need to know if it is zero or nonzero, replace it with a bit
3203 extraction. This will avoid the large constant, which might
3204 have taken more than one insn to make. If the constant were
3205 not a valid argument to the AND but took only one insn to make,
3206 this is no worse, but if it took more than one insn, it will
3209 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3210 && REG_P (XEXP (SET_SRC (x
), 0))
3211 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3212 && REG_P (SET_DEST (x
))
3213 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3214 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3215 && XEXP (*split
, 0) == SET_DEST (x
)
3216 && XEXP (*split
, 1) == const0_rtx
)
3218 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3219 XEXP (SET_SRC (x
), 0),
3220 pos
, NULL_RTX
, 1, 1, 0, 0);
3221 if (extraction
!= 0)
3223 SUBST (SET_SRC (x
), extraction
);
3224 return find_split_point (loc
, insn
);
3230 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3231 is known to be on, this can be converted into a NEG of a shift. */
3232 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3233 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3234 && 1 <= (pos
= exact_log2
3235 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3236 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3238 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3242 gen_rtx_LSHIFTRT (mode
,
3243 XEXP (SET_SRC (x
), 0),
3246 split
= find_split_point (&SET_SRC (x
), insn
);
3247 if (split
&& split
!= &SET_SRC (x
))
3253 inner
= XEXP (SET_SRC (x
), 0);
3255 /* We can't optimize if either mode is a partial integer
3256 mode as we don't know how many bits are significant
3258 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3259 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3263 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3269 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3270 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3272 inner
= XEXP (SET_SRC (x
), 0);
3273 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3274 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3276 if (BITS_BIG_ENDIAN
)
3277 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3278 unsignedp
= (code
== ZERO_EXTRACT
);
3286 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3288 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3290 /* For unsigned, we have a choice of a shift followed by an
3291 AND or two shifts. Use two shifts for field sizes where the
3292 constant might be too large. We assume here that we can
3293 always at least get 8-bit constants in an AND insn, which is
3294 true for every current RISC. */
3296 if (unsignedp
&& len
<= 8)
3301 (mode
, gen_lowpart (mode
, inner
),
3303 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3305 split
= find_split_point (&SET_SRC (x
), insn
);
3306 if (split
&& split
!= &SET_SRC (x
))
3313 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3314 gen_rtx_ASHIFT (mode
,
3315 gen_lowpart (mode
, inner
),
3316 GEN_INT (GET_MODE_BITSIZE (mode
)
3318 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3320 split
= find_split_point (&SET_SRC (x
), insn
);
3321 if (split
&& split
!= &SET_SRC (x
))
3326 /* See if this is a simple operation with a constant as the second
3327 operand. It might be that this constant is out of range and hence
3328 could be used as a split point. */
3329 if (BINARY_P (SET_SRC (x
))
3330 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3331 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
3332 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3333 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
3334 return &XEXP (SET_SRC (x
), 1);
3336 /* Finally, see if this is a simple operation with its first operand
3337 not in a register. The operation might require this operand in a
3338 register, so return it as a split point. We can always do this
3339 because if the first operand were another operation, we would have
3340 already found it as a split point. */
3341 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
3342 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3343 return &XEXP (SET_SRC (x
), 0);
3349 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3350 it is better to write this as (not (ior A B)) so we can split it.
3351 Similarly for IOR. */
3352 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3355 gen_rtx_NOT (GET_MODE (x
),
3356 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3358 XEXP (XEXP (x
, 0), 0),
3359 XEXP (XEXP (x
, 1), 0))));
3360 return find_split_point (loc
, insn
);
3363 /* Many RISC machines have a large set of logical insns. If the
3364 second operand is a NOT, put it first so we will try to split the
3365 other operand first. */
3366 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3368 rtx tem
= XEXP (x
, 0);
3369 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3370 SUBST (XEXP (x
, 1), tem
);
3378 /* Otherwise, select our actions depending on our rtx class. */
3379 switch (GET_RTX_CLASS (code
))
3381 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3383 split
= find_split_point (&XEXP (x
, 2), insn
);
3386 /* ... fall through ... */
3388 case RTX_COMM_ARITH
:
3390 case RTX_COMM_COMPARE
:
3391 split
= find_split_point (&XEXP (x
, 1), insn
);
3394 /* ... fall through ... */
3396 /* Some machines have (and (shift ...) ...) insns. If X is not
3397 an AND, but XEXP (X, 0) is, use it as our split point. */
3398 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3399 return &XEXP (x
, 0);
3401 split
= find_split_point (&XEXP (x
, 0), insn
);
3407 /* Otherwise, we don't have a split point. */
3412 /* Throughout X, replace FROM with TO, and return the result.
3413 The result is TO if X is FROM;
3414 otherwise the result is X, but its contents may have been modified.
3415 If they were modified, a record was made in undobuf so that
3416 undo_all will (among other things) return X to its original state.
3418 If the number of changes necessary is too much to record to undo,
3419 the excess changes are not made, so the result is invalid.
3420 The changes already made can still be undone.
3421 undobuf.num_undo is incremented for such changes, so by testing that
3422 the caller can tell whether the result is valid.
3424 `n_occurrences' is incremented each time FROM is replaced.
3426 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3428 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3429 by copying if `n_occurrences' is nonzero. */
3432 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3434 enum rtx_code code
= GET_CODE (x
);
3435 enum machine_mode op0_mode
= VOIDmode
;
3440 /* Two expressions are equal if they are identical copies of a shared
3441 RTX or if they are both registers with the same register number
3444 #define COMBINE_RTX_EQUAL_P(X,Y) \
3446 || (REG_P (X) && REG_P (Y) \
3447 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3449 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3452 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3455 /* If X and FROM are the same register but different modes, they will
3456 not have been seen as equal above. However, flow.c will make a
3457 LOG_LINKS entry for that case. If we do nothing, we will try to
3458 rerecognize our original insn and, when it succeeds, we will
3459 delete the feeding insn, which is incorrect.
3461 So force this insn not to match in this (rare) case. */
3462 if (! in_dest
&& code
== REG
&& REG_P (from
)
3463 && REGNO (x
) == REGNO (from
))
3464 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3466 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3467 of which may contain things that can be combined. */
3468 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
3471 /* It is possible to have a subexpression appear twice in the insn.
3472 Suppose that FROM is a register that appears within TO.
3473 Then, after that subexpression has been scanned once by `subst',
3474 the second time it is scanned, TO may be found. If we were
3475 to scan TO here, we would find FROM within it and create a
3476 self-referent rtl structure which is completely wrong. */
3477 if (COMBINE_RTX_EQUAL_P (x
, to
))
3480 /* Parallel asm_operands need special attention because all of the
3481 inputs are shared across the arms. Furthermore, unsharing the
3482 rtl results in recognition failures. Failure to handle this case
3483 specially can result in circular rtl.
3485 Solve this by doing a normal pass across the first entry of the
3486 parallel, and only processing the SET_DESTs of the subsequent
3489 if (code
== PARALLEL
3490 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3491 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3493 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3495 /* If this substitution failed, this whole thing fails. */
3496 if (GET_CODE (new) == CLOBBER
3497 && XEXP (new, 0) == const0_rtx
)
3500 SUBST (XVECEXP (x
, 0, 0), new);
3502 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3504 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3507 && GET_CODE (dest
) != CC0
3508 && GET_CODE (dest
) != PC
)
3510 new = subst (dest
, from
, to
, 0, unique_copy
);
3512 /* If this substitution failed, this whole thing fails. */
3513 if (GET_CODE (new) == CLOBBER
3514 && XEXP (new, 0) == const0_rtx
)
3517 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3523 len
= GET_RTX_LENGTH (code
);
3524 fmt
= GET_RTX_FORMAT (code
);
3526 /* We don't need to process a SET_DEST that is a register, CC0,
3527 or PC, so set up to skip this common case. All other cases
3528 where we want to suppress replacing something inside a
3529 SET_SRC are handled via the IN_DEST operand. */
3531 && (REG_P (SET_DEST (x
))
3532 || GET_CODE (SET_DEST (x
)) == CC0
3533 || GET_CODE (SET_DEST (x
)) == PC
))
3536 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3539 op0_mode
= GET_MODE (XEXP (x
, 0));
3541 for (i
= 0; i
< len
; i
++)
3546 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3548 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3550 new = (unique_copy
&& n_occurrences
3551 ? copy_rtx (to
) : to
);
3556 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3559 /* If this substitution failed, this whole thing
3561 if (GET_CODE (new) == CLOBBER
3562 && XEXP (new, 0) == const0_rtx
)
3566 SUBST (XVECEXP (x
, i
, j
), new);
3569 else if (fmt
[i
] == 'e')
3571 /* If this is a register being set, ignore it. */
3575 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
3577 || code
== STRICT_LOW_PART
))
3580 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3582 /* In general, don't install a subreg involving two
3583 modes not tieable. It can worsen register
3584 allocation, and can even make invalid reload
3585 insns, since the reg inside may need to be copied
3586 from in the outside mode, and that may be invalid
3587 if it is an fp reg copied in integer mode.
3589 We allow two exceptions to this: It is valid if
3590 it is inside another SUBREG and the mode of that
3591 SUBREG and the mode of the inside of TO is
3592 tieable and it is valid if X is a SET that copies
3595 if (GET_CODE (to
) == SUBREG
3596 && ! MODES_TIEABLE_P (GET_MODE (to
),
3597 GET_MODE (SUBREG_REG (to
)))
3598 && ! (code
== SUBREG
3599 && MODES_TIEABLE_P (GET_MODE (x
),
3600 GET_MODE (SUBREG_REG (to
))))
3602 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3605 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3607 #ifdef CANNOT_CHANGE_MODE_CLASS
3610 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3611 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3614 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3617 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3621 /* If we are in a SET_DEST, suppress most cases unless we
3622 have gone inside a MEM, in which case we want to
3623 simplify the address. We assume here that things that
3624 are actually part of the destination have their inner
3625 parts in the first expression. This is true for SUBREG,
3626 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3627 things aside from REG and MEM that should appear in a
3629 new = subst (XEXP (x
, i
), from
, to
,
3631 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3632 || code
== ZERO_EXTRACT
))
3634 && i
== 0), unique_copy
);
3636 /* If we found that we will have to reject this combination,
3637 indicate that by returning the CLOBBER ourselves, rather than
3638 an expression containing it. This will speed things up as
3639 well as prevent accidents where two CLOBBERs are considered
3640 to be equal, thus producing an incorrect simplification. */
3642 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3645 if (GET_CODE (x
) == SUBREG
3646 && (GET_CODE (new) == CONST_INT
3647 || GET_CODE (new) == CONST_DOUBLE
))
3649 enum machine_mode mode
= GET_MODE (x
);
3651 x
= simplify_subreg (GET_MODE (x
), new,
3652 GET_MODE (SUBREG_REG (x
)),
3655 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3657 else if (GET_CODE (new) == CONST_INT
3658 && GET_CODE (x
) == ZERO_EXTEND
)
3660 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3661 new, GET_MODE (XEXP (x
, 0)));
3665 SUBST (XEXP (x
, i
), new);
3670 /* Try to simplify X. If the simplification changed the code, it is likely
3671 that further simplification will help, so loop, but limit the number
3672 of repetitions that will be performed. */
3674 for (i
= 0; i
< 4; i
++)
3676 /* If X is sufficiently simple, don't bother trying to do anything
3678 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3679 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
);
3681 if (GET_CODE (x
) == code
)
3684 code
= GET_CODE (x
);
3686 /* We no longer know the original mode of operand 0 since we
3687 have changed the form of X) */
3688 op0_mode
= VOIDmode
;
3694 /* Simplify X, a piece of RTL. We just operate on the expression at the
3695 outer level; call `subst' to simplify recursively. Return the new
3698 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3699 if we are inside a SET_DEST. */
3702 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
)
3704 enum rtx_code code
= GET_CODE (x
);
3705 enum machine_mode mode
= GET_MODE (x
);
3710 /* If this is a commutative operation, put a constant last and a complex
3711 expression first. We don't need to do this for comparisons here. */
3712 if (COMMUTATIVE_ARITH_P (x
)
3713 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3716 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3717 SUBST (XEXP (x
, 1), temp
);
3720 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3721 sign extension of a PLUS with a constant, reverse the order of the sign
3722 extension and the addition. Note that this not the same as the original
3723 code, but overflow is undefined for signed values. Also note that the
3724 PLUS will have been partially moved "inside" the sign-extension, so that
3725 the first operand of X will really look like:
3726 (ashiftrt (plus (ashift A C4) C5) C4).
3728 (plus (ashiftrt (ashift A C4) C2) C4)
3729 and replace the first operand of X with that expression. Later parts
3730 of this function may simplify the expression further.
3732 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3733 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3734 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3736 We do this to simplify address expressions. */
3738 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3739 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3740 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3741 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3742 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3743 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3744 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3745 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3746 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3747 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3748 XEXP (XEXP (x
, 0), 1))) != 0)
3751 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3752 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3753 INTVAL (XEXP (XEXP (x
, 0), 1)));
3755 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3756 INTVAL (XEXP (XEXP (x
, 0), 1)));
3758 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3761 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3762 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3763 things. Check for cases where both arms are testing the same
3766 Don't do anything if all operands are very simple. */
3769 && ((!OBJECT_P (XEXP (x
, 0))
3770 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3771 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
3772 || (!OBJECT_P (XEXP (x
, 1))
3773 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3774 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
3776 && (!OBJECT_P (XEXP (x
, 0))
3777 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3778 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
3780 rtx cond
, true_rtx
, false_rtx
;
3782 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3784 /* If everything is a comparison, what we have is highly unlikely
3785 to be simpler, so don't use it. */
3786 && ! (COMPARISON_P (x
)
3787 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
3789 rtx cop1
= const0_rtx
;
3790 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3792 if (cond_code
== NE
&& COMPARISON_P (cond
))
3795 /* Simplify the alternative arms; this may collapse the true and
3796 false arms to store-flag values. Be careful to use copy_rtx
3797 here since true_rtx or false_rtx might share RTL with x as a
3798 result of the if_then_else_cond call above. */
3799 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3800 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3802 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3803 is unlikely to be simpler. */
3804 if (general_operand (true_rtx
, VOIDmode
)
3805 && general_operand (false_rtx
, VOIDmode
))
3807 enum rtx_code reversed
;
3809 /* Restarting if we generate a store-flag expression will cause
3810 us to loop. Just drop through in this case. */
3812 /* If the result values are STORE_FLAG_VALUE and zero, we can
3813 just make the comparison operation. */
3814 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3815 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3816 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3817 && ((reversed
= reversed_comparison_code_parts
3818 (cond_code
, cond
, cop1
, NULL
))
3820 x
= gen_binary (reversed
, mode
, cond
, cop1
);
3822 /* Likewise, we can make the negate of a comparison operation
3823 if the result values are - STORE_FLAG_VALUE and zero. */
3824 else if (GET_CODE (true_rtx
) == CONST_INT
3825 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3826 && false_rtx
== const0_rtx
)
3827 x
= simplify_gen_unary (NEG
, mode
,
3828 gen_binary (cond_code
, mode
, cond
,
3831 else if (GET_CODE (false_rtx
) == CONST_INT
3832 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3833 && true_rtx
== const0_rtx
3834 && ((reversed
= reversed_comparison_code_parts
3835 (cond_code
, cond
, cop1
, NULL
))
3837 x
= simplify_gen_unary (NEG
, mode
,
3838 gen_binary (reversed
, mode
,
3842 return gen_rtx_IF_THEN_ELSE (mode
,
3843 gen_binary (cond_code
, VOIDmode
,
3845 true_rtx
, false_rtx
);
3847 code
= GET_CODE (x
);
3848 op0_mode
= VOIDmode
;
3853 /* Try to fold this expression in case we have constants that weren't
3856 switch (GET_RTX_CLASS (code
))
3859 if (op0_mode
== VOIDmode
)
3860 op0_mode
= GET_MODE (XEXP (x
, 0));
3861 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3864 case RTX_COMM_COMPARE
:
3866 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3867 if (cmp_mode
== VOIDmode
)
3869 cmp_mode
= GET_MODE (XEXP (x
, 1));
3870 if (cmp_mode
== VOIDmode
)
3871 cmp_mode
= op0_mode
;
3873 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
3874 XEXP (x
, 0), XEXP (x
, 1));
3877 case RTX_COMM_ARITH
:
3879 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3881 case RTX_BITFIELD_OPS
:
3883 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3884 XEXP (x
, 1), XEXP (x
, 2));
3893 code
= GET_CODE (temp
);
3894 op0_mode
= VOIDmode
;
3895 mode
= GET_MODE (temp
);
3898 /* First see if we can apply the inverse distributive law. */
3899 if (code
== PLUS
|| code
== MINUS
3900 || code
== AND
|| code
== IOR
|| code
== XOR
)
3902 x
= apply_distributive_law (x
);
3903 code
= GET_CODE (x
);
3904 op0_mode
= VOIDmode
;
3907 /* If CODE is an associative operation not otherwise handled, see if we
3908 can associate some operands. This can win if they are constants or
3909 if they are logically related (i.e. (a & b) & a). */
3910 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3911 || code
== AND
|| code
== IOR
|| code
== XOR
3912 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3913 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3914 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3916 if (GET_CODE (XEXP (x
, 0)) == code
)
3918 rtx other
= XEXP (XEXP (x
, 0), 0);
3919 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3920 rtx inner_op1
= XEXP (x
, 1);
3923 /* Make sure we pass the constant operand if any as the second
3924 one if this is a commutative operation. */
3925 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
3927 rtx tem
= inner_op0
;
3928 inner_op0
= inner_op1
;
3931 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3932 : code
== DIV
? MULT
3934 mode
, inner_op0
, inner_op1
);
3936 /* For commutative operations, try the other pair if that one
3938 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
3940 other
= XEXP (XEXP (x
, 0), 1);
3941 inner
= simplify_binary_operation (code
, mode
,
3942 XEXP (XEXP (x
, 0), 0),
3947 return gen_binary (code
, mode
, other
, inner
);
3951 /* A little bit of algebraic simplification here. */
3955 /* Ensure that our address has any ASHIFTs converted to MULT in case
3956 address-recognizing predicates are called later. */
3957 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3958 SUBST (XEXP (x
, 0), temp
);
3962 if (op0_mode
== VOIDmode
)
3963 op0_mode
= GET_MODE (SUBREG_REG (x
));
3965 /* See if this can be moved to simplify_subreg. */
3966 if (CONSTANT_P (SUBREG_REG (x
))
3967 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3968 /* Don't call gen_lowpart if the inner mode
3969 is VOIDmode and we cannot simplify it, as SUBREG without
3970 inner mode is invalid. */
3971 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3972 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3973 return gen_lowpart (mode
, SUBREG_REG (x
));
3975 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3979 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3985 /* Don't change the mode of the MEM if that would change the meaning
3987 if (MEM_P (SUBREG_REG (x
))
3988 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3989 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3990 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3992 /* Note that we cannot do any narrowing for non-constants since
3993 we might have been counting on using the fact that some bits were
3994 zero. We now do this in the SET. */
3999 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4000 && subreg_lowpart_p (XEXP (x
, 0))
4001 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
4002 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
4003 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
4004 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
4006 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
4008 x
= gen_rtx_ROTATE (inner_mode
,
4009 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
4011 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
4012 return gen_lowpart (mode
, x
);
4015 /* Apply De Morgan's laws to reduce number of patterns for machines
4016 with negating logical insns (and-not, nand, etc.). If result has
4017 only one NOT, put it first, since that is how the patterns are
4020 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
4022 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
4023 enum machine_mode op_mode
;
4025 op_mode
= GET_MODE (in1
);
4026 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
4028 op_mode
= GET_MODE (in2
);
4029 if (op_mode
== VOIDmode
)
4031 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
4033 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
4036 in2
= in1
; in1
= tem
;
4039 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
4045 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4046 if (GET_CODE (XEXP (x
, 0)) == XOR
4047 && XEXP (XEXP (x
, 0), 1) == const1_rtx
4048 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
4049 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
4051 temp
= expand_compound_operation (XEXP (x
, 0));
4053 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4054 replaced by (lshiftrt X C). This will convert
4055 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4057 if (GET_CODE (temp
) == ASHIFTRT
4058 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4059 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4060 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4061 INTVAL (XEXP (temp
, 1)));
4063 /* If X has only a single bit that might be nonzero, say, bit I, convert
4064 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4065 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4066 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4067 or a SUBREG of one since we'd be making the expression more
4068 complex if it was just a register. */
4071 && ! (GET_CODE (temp
) == SUBREG
4072 && REG_P (SUBREG_REG (temp
)))
4073 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4075 rtx temp1
= simplify_shift_const
4076 (NULL_RTX
, ASHIFTRT
, mode
,
4077 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4078 GET_MODE_BITSIZE (mode
) - 1 - i
),
4079 GET_MODE_BITSIZE (mode
) - 1 - i
);
4081 /* If all we did was surround TEMP with the two shifts, we
4082 haven't improved anything, so don't use it. Otherwise,
4083 we are better off with TEMP1. */
4084 if (GET_CODE (temp1
) != ASHIFTRT
4085 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4086 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4092 /* We can't handle truncation to a partial integer mode here
4093 because we don't know the real bitsize of the partial
4095 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4098 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4099 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4100 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4102 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4103 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4105 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4106 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4107 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4108 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4109 return XEXP (XEXP (x
, 0), 0);
4111 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4112 (OP:SI foo:SI) if OP is NEG or ABS. */
4113 if ((GET_CODE (XEXP (x
, 0)) == ABS
4114 || GET_CODE (XEXP (x
, 0)) == NEG
)
4115 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4116 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4117 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4118 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4119 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4121 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4123 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4124 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4125 && subreg_lowpart_p (XEXP (x
, 0)))
4126 return SUBREG_REG (XEXP (x
, 0));
4128 /* If we know that the value is already truncated, we can
4129 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4130 is nonzero for the corresponding modes. But don't do this
4131 for an (LSHIFTRT (MULT ...)) since this will cause problems
4132 with the umulXi3_highpart patterns. */
4133 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4134 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4135 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4136 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
4137 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4138 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4139 return gen_lowpart (mode
, XEXP (x
, 0));
4141 /* A truncate of a comparison can be replaced with a subreg if
4142 STORE_FLAG_VALUE permits. This is like the previous test,
4143 but it works even if the comparison is done in a mode larger
4144 than HOST_BITS_PER_WIDE_INT. */
4145 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4146 && COMPARISON_P (XEXP (x
, 0))
4147 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4148 return gen_lowpart (mode
, XEXP (x
, 0));
4150 /* Similarly, a truncate of a register whose value is a
4151 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4153 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4154 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4155 && (temp
= get_last_value (XEXP (x
, 0)))
4156 && COMPARISON_P (temp
))
4157 return gen_lowpart (mode
, XEXP (x
, 0));
4161 case FLOAT_TRUNCATE
:
4162 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4163 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4164 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4165 return XEXP (XEXP (x
, 0), 0);
4167 /* (float_truncate:SF (float_truncate:DF foo:XF))
4168 = (float_truncate:SF foo:XF).
4169 This may eliminate double rounding, so it is unsafe.
4171 (float_truncate:SF (float_extend:XF foo:DF))
4172 = (float_truncate:SF foo:DF).
4174 (float_truncate:DF (float_extend:XF foo:SF))
4175 = (float_extend:SF foo:DF). */
4176 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4177 && flag_unsafe_math_optimizations
)
4178 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4179 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4181 > GET_MODE_SIZE (mode
)
4182 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4184 XEXP (XEXP (x
, 0), 0), mode
);
4186 /* (float_truncate (float x)) is (float x) */
4187 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4188 && (flag_unsafe_math_optimizations
4189 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4190 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4191 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4192 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4193 return simplify_gen_unary (FLOAT
, mode
,
4194 XEXP (XEXP (x
, 0), 0),
4195 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4197 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4198 (OP:SF foo:SF) if OP is NEG or ABS. */
4199 if ((GET_CODE (XEXP (x
, 0)) == ABS
4200 || GET_CODE (XEXP (x
, 0)) == NEG
)
4201 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4202 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4203 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4204 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4206 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4207 is (float_truncate:SF x). */
4208 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4209 && subreg_lowpart_p (XEXP (x
, 0))
4210 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4211 return SUBREG_REG (XEXP (x
, 0));
4214 /* (float_extend (float_extend x)) is (float_extend x)
4216 (float_extend (float x)) is (float x) assuming that double
4217 rounding can't happen.
4219 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4220 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4221 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4222 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4223 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4224 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4225 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4226 XEXP (XEXP (x
, 0), 0),
4227 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4232 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4233 using cc0, in which case we want to leave it as a COMPARE
4234 so we can distinguish it from a register-register-copy. */
4235 if (XEXP (x
, 1) == const0_rtx
)
4238 /* x - 0 is the same as x unless x's mode has signed zeros and
4239 allows rounding towards -infinity. Under those conditions,
4241 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4242 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4243 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4249 /* (const (const X)) can become (const X). Do it this way rather than
4250 returning the inner CONST since CONST can be shared with a
4252 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4253 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4258 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4259 can add in an offset. find_split_point will split this address up
4260 again if it doesn't match. */
4261 if (GET_CODE (XEXP (x
, 0)) == HIGH
4262 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4268 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4270 if (GET_CODE (XEXP (x
, 0)) == MULT
4271 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4275 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4276 in2
= XEXP (XEXP (x
, 0), 1);
4277 return gen_binary (MINUS
, mode
, XEXP (x
, 1),
4278 gen_binary (MULT
, mode
, in1
, in2
));
4281 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4282 outermost. That's because that's the way indexed addresses are
4283 supposed to appear. This code used to check many more cases, but
4284 they are now checked elsewhere. */
4285 if (GET_CODE (XEXP (x
, 0)) == PLUS
4286 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4287 return gen_binary (PLUS
, mode
,
4288 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4290 XEXP (XEXP (x
, 0), 1));
4292 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4293 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4294 bit-field and can be replaced by either a sign_extend or a
4295 sign_extract. The `and' may be a zero_extend and the two
4296 <c>, -<c> constants may be reversed. */
4297 if (GET_CODE (XEXP (x
, 0)) == XOR
4298 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4299 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4300 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4301 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4302 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4303 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4304 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4305 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4306 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4307 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4308 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4309 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4310 == (unsigned int) i
+ 1))))
4311 return simplify_shift_const
4312 (NULL_RTX
, ASHIFTRT
, mode
,
4313 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4314 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4315 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4316 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4318 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4319 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4320 is 1. This produces better code than the alternative immediately
4322 if (COMPARISON_P (XEXP (x
, 0))
4323 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4324 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4325 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4326 XEXP (XEXP (x
, 0), 0),
4327 XEXP (XEXP (x
, 0), 1))))
4329 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4331 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4332 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4333 the bitsize of the mode - 1. This allows simplification of
4334 "a = (b & 8) == 0;" */
4335 if (XEXP (x
, 1) == constm1_rtx
4336 && !REG_P (XEXP (x
, 0))
4337 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4338 && REG_P (SUBREG_REG (XEXP (x
, 0))))
4339 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4340 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4341 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4342 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4343 GET_MODE_BITSIZE (mode
) - 1),
4344 GET_MODE_BITSIZE (mode
) - 1);
4346 /* If we are adding two things that have no bits in common, convert
4347 the addition into an IOR. This will often be further simplified,
4348 for example in cases like ((a & 1) + (a & 2)), which can
4351 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4352 && (nonzero_bits (XEXP (x
, 0), mode
)
4353 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4355 /* Try to simplify the expression further. */
4356 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4357 temp
= combine_simplify_rtx (tor
, mode
, in_dest
);
4359 /* If we could, great. If not, do not go ahead with the IOR
4360 replacement, since PLUS appears in many special purpose
4361 address arithmetic instructions. */
4362 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4368 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4369 by reversing the comparison code if valid. */
4370 if (STORE_FLAG_VALUE
== 1
4371 && XEXP (x
, 0) == const1_rtx
4372 && COMPARISON_P (XEXP (x
, 1))
4373 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4374 XEXP (XEXP (x
, 1), 0),
4375 XEXP (XEXP (x
, 1), 1))))
4378 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4379 (and <foo> (const_int pow2-1)) */
4380 if (GET_CODE (XEXP (x
, 1)) == AND
4381 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4382 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4383 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4384 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4385 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4387 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4389 if (GET_CODE (XEXP (x
, 1)) == MULT
4390 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4394 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4395 in2
= XEXP (XEXP (x
, 1), 1);
4396 return gen_binary (PLUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4400 /* Canonicalize (minus (neg A) (mult B C)) to
4401 (minus (mult (neg B) C) A). */
4402 if (GET_CODE (XEXP (x
, 1)) == MULT
4403 && GET_CODE (XEXP (x
, 0)) == NEG
)
4407 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4408 in2
= XEXP (XEXP (x
, 1), 1);
4409 return gen_binary (MINUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4410 XEXP (XEXP (x
, 0), 0));
4413 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4415 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4416 return gen_binary (MINUS
, mode
,
4417 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4418 XEXP (XEXP (x
, 1), 0)),
4419 XEXP (XEXP (x
, 1), 1));
4423 /* If we have (mult (plus A B) C), apply the distributive law and then
4424 the inverse distributive law to see if things simplify. This
4425 occurs mostly in addresses, often when unrolling loops. */
4427 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4429 x
= apply_distributive_law
4430 (gen_binary (PLUS
, mode
,
4431 gen_binary (MULT
, mode
,
4432 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4433 gen_binary (MULT
, mode
,
4434 XEXP (XEXP (x
, 0), 1),
4435 copy_rtx (XEXP (x
, 1)))));
4437 if (GET_CODE (x
) != MULT
)
4440 /* Try simplify a*(b/c) as (a*b)/c. */
4441 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4442 && GET_CODE (XEXP (x
, 0)) == DIV
)
4444 rtx tem
= simplify_binary_operation (MULT
, mode
,
4445 XEXP (XEXP (x
, 0), 0),
4448 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4453 /* If this is a divide by a power of two, treat it as a shift if
4454 its first operand is a shift. */
4455 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4456 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4457 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4458 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4459 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4460 || GET_CODE (XEXP (x
, 0)) == ROTATE
4461 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4462 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4466 case GT
: case GTU
: case GE
: case GEU
:
4467 case LT
: case LTU
: case LE
: case LEU
:
4468 case UNEQ
: case LTGT
:
4469 case UNGT
: case UNGE
:
4470 case UNLT
: case UNLE
:
4471 case UNORDERED
: case ORDERED
:
4472 /* If the first operand is a condition code, we can't do anything
4474 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4475 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4476 && ! CC0_P (XEXP (x
, 0))))
4478 rtx op0
= XEXP (x
, 0);
4479 rtx op1
= XEXP (x
, 1);
4480 enum rtx_code new_code
;
4482 if (GET_CODE (op0
) == COMPARE
)
4483 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4485 /* Simplify our comparison, if possible. */
4486 new_code
= simplify_comparison (code
, &op0
, &op1
);
4488 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4489 if only the low-order bit is possibly nonzero in X (such as when
4490 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4491 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4492 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4495 Remove any ZERO_EXTRACT we made when thinking this was a
4496 comparison. It may now be simpler to use, e.g., an AND. If a
4497 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4498 the call to make_compound_operation in the SET case. */
4500 if (STORE_FLAG_VALUE
== 1
4501 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4502 && op1
== const0_rtx
4503 && mode
== GET_MODE (op0
)
4504 && nonzero_bits (op0
, mode
) == 1)
4505 return gen_lowpart (mode
,
4506 expand_compound_operation (op0
));
4508 else if (STORE_FLAG_VALUE
== 1
4509 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4510 && op1
== const0_rtx
4511 && mode
== GET_MODE (op0
)
4512 && (num_sign_bit_copies (op0
, mode
)
4513 == GET_MODE_BITSIZE (mode
)))
4515 op0
= expand_compound_operation (op0
);
4516 return simplify_gen_unary (NEG
, mode
,
4517 gen_lowpart (mode
, op0
),
4521 else if (STORE_FLAG_VALUE
== 1
4522 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4523 && op1
== const0_rtx
4524 && mode
== GET_MODE (op0
)
4525 && nonzero_bits (op0
, mode
) == 1)
4527 op0
= expand_compound_operation (op0
);
4528 return gen_binary (XOR
, mode
,
4529 gen_lowpart (mode
, op0
),
4533 else if (STORE_FLAG_VALUE
== 1
4534 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4535 && op1
== const0_rtx
4536 && mode
== GET_MODE (op0
)
4537 && (num_sign_bit_copies (op0
, mode
)
4538 == GET_MODE_BITSIZE (mode
)))
4540 op0
= expand_compound_operation (op0
);
4541 return plus_constant (gen_lowpart (mode
, op0
), 1);
4544 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4546 if (STORE_FLAG_VALUE
== -1
4547 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4548 && op1
== const0_rtx
4549 && (num_sign_bit_copies (op0
, mode
)
4550 == GET_MODE_BITSIZE (mode
)))
4551 return gen_lowpart (mode
,
4552 expand_compound_operation (op0
));
4554 else if (STORE_FLAG_VALUE
== -1
4555 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4556 && op1
== const0_rtx
4557 && mode
== GET_MODE (op0
)
4558 && nonzero_bits (op0
, mode
) == 1)
4560 op0
= expand_compound_operation (op0
);
4561 return simplify_gen_unary (NEG
, mode
,
4562 gen_lowpart (mode
, op0
),
4566 else if (STORE_FLAG_VALUE
== -1
4567 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4568 && op1
== const0_rtx
4569 && mode
== GET_MODE (op0
)
4570 && (num_sign_bit_copies (op0
, mode
)
4571 == GET_MODE_BITSIZE (mode
)))
4573 op0
= expand_compound_operation (op0
);
4574 return simplify_gen_unary (NOT
, mode
,
4575 gen_lowpart (mode
, op0
),
4579 /* If X is 0/1, (eq X 0) is X-1. */
4580 else if (STORE_FLAG_VALUE
== -1
4581 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4582 && op1
== const0_rtx
4583 && mode
== GET_MODE (op0
)
4584 && nonzero_bits (op0
, mode
) == 1)
4586 op0
= expand_compound_operation (op0
);
4587 return plus_constant (gen_lowpart (mode
, op0
), -1);
4590 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4591 one bit that might be nonzero, we can convert (ne x 0) to
4592 (ashift x c) where C puts the bit in the sign bit. Remove any
4593 AND with STORE_FLAG_VALUE when we are done, since we are only
4594 going to test the sign bit. */
4595 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4596 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4597 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4598 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4599 && op1
== const0_rtx
4600 && mode
== GET_MODE (op0
)
4601 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4603 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4604 expand_compound_operation (op0
),
4605 GET_MODE_BITSIZE (mode
) - 1 - i
);
4606 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4612 /* If the code changed, return a whole new comparison. */
4613 if (new_code
!= code
)
4614 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4616 /* Otherwise, keep this operation, but maybe change its operands.
4617 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4618 SUBST (XEXP (x
, 0), op0
);
4619 SUBST (XEXP (x
, 1), op1
);
4624 return simplify_if_then_else (x
);
4630 /* If we are processing SET_DEST, we are done. */
4634 return expand_compound_operation (x
);
4637 return simplify_set (x
);
4642 return simplify_logical (x
);
4645 /* (abs (neg <foo>)) -> (abs <foo>) */
4646 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4647 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4649 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4651 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4654 /* If operand is something known to be positive, ignore the ABS. */
4655 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4656 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4657 <= HOST_BITS_PER_WIDE_INT
)
4658 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4659 & ((HOST_WIDE_INT
) 1
4660 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4664 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4665 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4666 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4671 /* (ffs (*_extend <X>)) = (ffs <X>) */
4672 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4673 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4674 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4679 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4680 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4681 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4685 /* (float (sign_extend <X>)) = (float <X>). */
4686 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4687 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4695 /* If this is a shift by a constant amount, simplify it. */
4696 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4697 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4698 INTVAL (XEXP (x
, 1)));
4700 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
4702 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4704 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4711 rtx op0
= XEXP (x
, 0);
4712 rtx op1
= XEXP (x
, 1);
4715 gcc_assert (GET_CODE (op1
) == PARALLEL
);
4716 len
= XVECLEN (op1
, 0);
4718 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4719 && GET_CODE (op0
) == VEC_CONCAT
)
4721 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4723 /* Try to find the element in the VEC_CONCAT. */
4726 if (GET_MODE (op0
) == GET_MODE (x
))
4728 if (GET_CODE (op0
) == VEC_CONCAT
)
4730 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4731 if (op0_size
< offset
)
4732 op0
= XEXP (op0
, 0);
4736 op0
= XEXP (op0
, 1);
4754 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4757 simplify_if_then_else (rtx x
)
4759 enum machine_mode mode
= GET_MODE (x
);
4760 rtx cond
= XEXP (x
, 0);
4761 rtx true_rtx
= XEXP (x
, 1);
4762 rtx false_rtx
= XEXP (x
, 2);
4763 enum rtx_code true_code
= GET_CODE (cond
);
4764 int comparison_p
= COMPARISON_P (cond
);
4767 enum rtx_code false_code
;
4770 /* Simplify storing of the truth value. */
4771 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4772 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4774 /* Also when the truth value has to be reversed. */
4776 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4777 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4781 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4782 in it is being compared against certain values. Get the true and false
4783 comparisons and see if that says anything about the value of each arm. */
4786 && ((false_code
= combine_reversed_comparison_code (cond
))
4788 && REG_P (XEXP (cond
, 0)))
4791 rtx from
= XEXP (cond
, 0);
4792 rtx true_val
= XEXP (cond
, 1);
4793 rtx false_val
= true_val
;
4796 /* If FALSE_CODE is EQ, swap the codes and arms. */
4798 if (false_code
== EQ
)
4800 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4801 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4804 /* If we are comparing against zero and the expression being tested has
4805 only a single bit that might be nonzero, that is its value when it is
4806 not equal to zero. Similarly if it is known to be -1 or 0. */
4808 if (true_code
== EQ
&& true_val
== const0_rtx
4809 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4810 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4811 else if (true_code
== EQ
&& true_val
== const0_rtx
4812 && (num_sign_bit_copies (from
, GET_MODE (from
))
4813 == GET_MODE_BITSIZE (GET_MODE (from
))))
4814 false_code
= EQ
, false_val
= constm1_rtx
;
4816 /* Now simplify an arm if we know the value of the register in the
4817 branch and it is used in the arm. Be careful due to the potential
4818 of locally-shared RTL. */
4820 if (reg_mentioned_p (from
, true_rtx
))
4821 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4823 pc_rtx
, pc_rtx
, 0, 0);
4824 if (reg_mentioned_p (from
, false_rtx
))
4825 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4827 pc_rtx
, pc_rtx
, 0, 0);
4829 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4830 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4832 true_rtx
= XEXP (x
, 1);
4833 false_rtx
= XEXP (x
, 2);
4834 true_code
= GET_CODE (cond
);
4837 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4838 reversed, do so to avoid needing two sets of patterns for
4839 subtract-and-branch insns. Similarly if we have a constant in the true
4840 arm, the false arm is the same as the first operand of the comparison, or
4841 the false arm is more complicated than the true arm. */
4844 && combine_reversed_comparison_code (cond
) != UNKNOWN
4845 && (true_rtx
== pc_rtx
4846 || (CONSTANT_P (true_rtx
)
4847 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4848 || true_rtx
== const0_rtx
4849 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
4850 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
4851 && !OBJECT_P (false_rtx
))
4852 || reg_mentioned_p (true_rtx
, false_rtx
)
4853 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4855 true_code
= reversed_comparison_code (cond
, NULL
);
4857 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4860 SUBST (XEXP (x
, 1), false_rtx
);
4861 SUBST (XEXP (x
, 2), true_rtx
);
4863 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4866 /* It is possible that the conditional has been simplified out. */
4867 true_code
= GET_CODE (cond
);
4868 comparison_p
= COMPARISON_P (cond
);
4871 /* If the two arms are identical, we don't need the comparison. */
4873 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4876 /* Convert a == b ? b : a to "a". */
4877 if (true_code
== EQ
&& ! side_effects_p (cond
)
4878 && !HONOR_NANS (mode
)
4879 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4880 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4882 else if (true_code
== NE
&& ! side_effects_p (cond
)
4883 && !HONOR_NANS (mode
)
4884 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4885 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4888 /* Look for cases where we have (abs x) or (neg (abs X)). */
4890 if (GET_MODE_CLASS (mode
) == MODE_INT
4891 && GET_CODE (false_rtx
) == NEG
4892 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4894 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4895 && ! side_effects_p (true_rtx
))
4900 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4904 simplify_gen_unary (NEG
, mode
,
4905 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4911 /* Look for MIN or MAX. */
4913 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4915 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4916 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4917 && ! side_effects_p (cond
))
4922 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4925 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4928 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4931 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4936 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4937 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4938 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4939 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4940 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4941 neither 1 or -1, but it isn't worth checking for. */
4943 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4945 && GET_MODE_CLASS (mode
) == MODE_INT
4946 && ! side_effects_p (x
))
4948 rtx t
= make_compound_operation (true_rtx
, SET
);
4949 rtx f
= make_compound_operation (false_rtx
, SET
);
4950 rtx cond_op0
= XEXP (cond
, 0);
4951 rtx cond_op1
= XEXP (cond
, 1);
4952 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
4953 enum machine_mode m
= mode
;
4954 rtx z
= 0, c1
= NULL_RTX
;
4956 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4957 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4958 || GET_CODE (t
) == ASHIFT
4959 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4960 && rtx_equal_p (XEXP (t
, 0), f
))
4961 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4963 /* If an identity-zero op is commutative, check whether there
4964 would be a match if we swapped the operands. */
4965 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4966 || GET_CODE (t
) == XOR
)
4967 && rtx_equal_p (XEXP (t
, 1), f
))
4968 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4969 else if (GET_CODE (t
) == SIGN_EXTEND
4970 && (GET_CODE (XEXP (t
, 0)) == PLUS
4971 || GET_CODE (XEXP (t
, 0)) == MINUS
4972 || GET_CODE (XEXP (t
, 0)) == IOR
4973 || GET_CODE (XEXP (t
, 0)) == XOR
4974 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4975 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4976 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4977 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4978 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4979 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4980 && (num_sign_bit_copies (f
, GET_MODE (f
))
4982 (GET_MODE_BITSIZE (mode
)
4983 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4985 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4986 extend_op
= SIGN_EXTEND
;
4987 m
= GET_MODE (XEXP (t
, 0));
4989 else if (GET_CODE (t
) == SIGN_EXTEND
4990 && (GET_CODE (XEXP (t
, 0)) == PLUS
4991 || GET_CODE (XEXP (t
, 0)) == IOR
4992 || GET_CODE (XEXP (t
, 0)) == XOR
)
4993 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4994 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4995 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4996 && (num_sign_bit_copies (f
, GET_MODE (f
))
4998 (GET_MODE_BITSIZE (mode
)
4999 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
5001 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5002 extend_op
= SIGN_EXTEND
;
5003 m
= GET_MODE (XEXP (t
, 0));
5005 else if (GET_CODE (t
) == ZERO_EXTEND
5006 && (GET_CODE (XEXP (t
, 0)) == PLUS
5007 || GET_CODE (XEXP (t
, 0)) == MINUS
5008 || GET_CODE (XEXP (t
, 0)) == IOR
5009 || GET_CODE (XEXP (t
, 0)) == XOR
5010 || GET_CODE (XEXP (t
, 0)) == ASHIFT
5011 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
5012 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
5013 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
5014 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5015 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
5016 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
5017 && ((nonzero_bits (f
, GET_MODE (f
))
5018 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
5021 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5022 extend_op
= ZERO_EXTEND
;
5023 m
= GET_MODE (XEXP (t
, 0));
5025 else if (GET_CODE (t
) == ZERO_EXTEND
5026 && (GET_CODE (XEXP (t
, 0)) == PLUS
5027 || GET_CODE (XEXP (t
, 0)) == IOR
5028 || GET_CODE (XEXP (t
, 0)) == XOR
)
5029 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
5030 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5031 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
5032 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
5033 && ((nonzero_bits (f
, GET_MODE (f
))
5034 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
5037 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
5038 extend_op
= ZERO_EXTEND
;
5039 m
= GET_MODE (XEXP (t
, 0));
5044 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
5045 pc_rtx
, pc_rtx
, 0, 0);
5046 temp
= gen_binary (MULT
, m
, temp
,
5047 gen_binary (MULT
, m
, c1
, const_true_rtx
));
5048 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
5049 temp
= gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
5051 if (extend_op
!= UNKNOWN
)
5052 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
5058 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5059 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5060 negation of a single bit, we can convert this operation to a shift. We
5061 can actually do this more generally, but it doesn't seem worth it. */
5063 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5064 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5065 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
5066 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
5067 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
5068 == GET_MODE_BITSIZE (mode
))
5069 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
5071 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5072 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
5074 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5075 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
5076 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
5077 && GET_MODE (XEXP (cond
, 0)) == mode
5078 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
5079 == nonzero_bits (XEXP (cond
, 0), mode
)
5080 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
5081 return XEXP (cond
, 0);
5086 /* Simplify X, a SET expression. Return the new expression. */
5089 simplify_set (rtx x
)
5091 rtx src
= SET_SRC (x
);
5092 rtx dest
= SET_DEST (x
);
5093 enum machine_mode mode
5094 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
5098 /* (set (pc) (return)) gets written as (return). */
5099 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
5102 /* Now that we know for sure which bits of SRC we are using, see if we can
5103 simplify the expression for the object knowing that we only need the
5106 if (GET_MODE_CLASS (mode
) == MODE_INT
5107 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
5109 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
5110 SUBST (SET_SRC (x
), src
);
5113 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5114 the comparison result and try to simplify it unless we already have used
5115 undobuf.other_insn. */
5116 if ((GET_MODE_CLASS (mode
) == MODE_CC
5117 || GET_CODE (src
) == COMPARE
5119 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5120 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5121 && COMPARISON_P (*cc_use
)
5122 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5124 enum rtx_code old_code
= GET_CODE (*cc_use
);
5125 enum rtx_code new_code
;
5127 int other_changed
= 0;
5128 enum machine_mode compare_mode
= GET_MODE (dest
);
5130 if (GET_CODE (src
) == COMPARE
)
5131 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5133 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
5135 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
5138 new_code
= old_code
;
5139 else if (!CONSTANT_P (tmp
))
5141 new_code
= GET_CODE (tmp
);
5142 op0
= XEXP (tmp
, 0);
5143 op1
= XEXP (tmp
, 1);
5147 rtx pat
= PATTERN (other_insn
);
5148 undobuf
.other_insn
= other_insn
;
5149 SUBST (*cc_use
, tmp
);
5151 /* Attempt to simplify CC user. */
5152 if (GET_CODE (pat
) == SET
)
5154 rtx
new = simplify_rtx (SET_SRC (pat
));
5155 if (new != NULL_RTX
)
5156 SUBST (SET_SRC (pat
), new);
5159 /* Convert X into a no-op move. */
5160 SUBST (SET_DEST (x
), pc_rtx
);
5161 SUBST (SET_SRC (x
), pc_rtx
);
5165 /* Simplify our comparison, if possible. */
5166 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
5168 #ifdef SELECT_CC_MODE
5169 /* If this machine has CC modes other than CCmode, check to see if we
5170 need to use a different CC mode here. */
5171 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
5172 compare_mode
= GET_MODE (op0
);
5174 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5177 /* If the mode changed, we have to change SET_DEST, the mode in the
5178 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5179 a hard register, just build new versions with the proper mode. If it
5180 is a pseudo, we lose unless it is only time we set the pseudo, in
5181 which case we can safely change its mode. */
5182 if (compare_mode
!= GET_MODE (dest
))
5184 unsigned int regno
= REGNO (dest
);
5185 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5187 if (regno
< FIRST_PSEUDO_REGISTER
5188 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5190 if (regno
>= FIRST_PSEUDO_REGISTER
)
5191 SUBST (regno_reg_rtx
[regno
], new_dest
);
5193 SUBST (SET_DEST (x
), new_dest
);
5194 SUBST (XEXP (*cc_use
, 0), new_dest
);
5201 #endif /* SELECT_CC_MODE */
5203 /* If the code changed, we have to build a new comparison in
5204 undobuf.other_insn. */
5205 if (new_code
!= old_code
)
5207 int other_changed_previously
= other_changed
;
5208 unsigned HOST_WIDE_INT mask
;
5210 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5214 /* If the only change we made was to change an EQ into an NE or
5215 vice versa, OP0 has only one bit that might be nonzero, and OP1
5216 is zero, check if changing the user of the condition code will
5217 produce a valid insn. If it won't, we can keep the original code
5218 in that insn by surrounding our operation with an XOR. */
5220 if (((old_code
== NE
&& new_code
== EQ
)
5221 || (old_code
== EQ
&& new_code
== NE
))
5222 && ! other_changed_previously
&& op1
== const0_rtx
5223 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5224 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5226 rtx pat
= PATTERN (other_insn
), note
= 0;
5228 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5229 && ! check_asm_operands (pat
)))
5231 PUT_CODE (*cc_use
, old_code
);
5234 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5240 undobuf
.other_insn
= other_insn
;
5243 /* If we are now comparing against zero, change our source if
5244 needed. If we do not use cc0, we always have a COMPARE. */
5245 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5247 SUBST (SET_SRC (x
), op0
);
5253 /* Otherwise, if we didn't previously have a COMPARE in the
5254 correct mode, we need one. */
5255 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5257 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5262 /* Otherwise, update the COMPARE if needed. */
5263 SUBST (XEXP (src
, 0), op0
);
5264 SUBST (XEXP (src
, 1), op1
);
5269 /* Get SET_SRC in a form where we have placed back any
5270 compound expressions. Then do the checks below. */
5271 src
= make_compound_operation (src
, SET
);
5272 SUBST (SET_SRC (x
), src
);
5275 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5276 and X being a REG or (subreg (reg)), we may be able to convert this to
5277 (set (subreg:m2 x) (op)).
5279 We can always do this if M1 is narrower than M2 because that means that
5280 we only care about the low bits of the result.
5282 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5283 perform a narrower operation than requested since the high-order bits will
5284 be undefined. On machine where it is defined, this transformation is safe
5285 as long as M1 and M2 have the same number of words. */
5287 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5288 && !OBJECT_P (SUBREG_REG (src
))
5289 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5291 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5292 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5293 #ifndef WORD_REGISTER_OPERATIONS
5294 && (GET_MODE_SIZE (GET_MODE (src
))
5295 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5297 #ifdef CANNOT_CHANGE_MODE_CLASS
5298 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
5299 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5300 GET_MODE (SUBREG_REG (src
)),
5304 || (GET_CODE (dest
) == SUBREG
5305 && REG_P (SUBREG_REG (dest
)))))
5307 SUBST (SET_DEST (x
),
5308 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
5310 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5312 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5316 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5319 && GET_CODE (src
) == SUBREG
5320 && subreg_lowpart_p (src
)
5321 && (GET_MODE_BITSIZE (GET_MODE (src
))
5322 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5324 rtx inner
= SUBREG_REG (src
);
5325 enum machine_mode inner_mode
= GET_MODE (inner
);
5327 /* Here we make sure that we don't have a sign bit on. */
5328 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5329 && (nonzero_bits (inner
, inner_mode
)
5330 < ((unsigned HOST_WIDE_INT
) 1
5331 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5333 SUBST (SET_SRC (x
), inner
);
5339 #ifdef LOAD_EXTEND_OP
5340 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5341 would require a paradoxical subreg. Replace the subreg with a
5342 zero_extend to avoid the reload that would otherwise be required. */
5344 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5345 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
5346 && SUBREG_BYTE (src
) == 0
5347 && (GET_MODE_SIZE (GET_MODE (src
))
5348 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5349 && MEM_P (SUBREG_REG (src
)))
5352 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5353 GET_MODE (src
), SUBREG_REG (src
)));
5359 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5360 are comparing an item known to be 0 or -1 against 0, use a logical
5361 operation instead. Check for one of the arms being an IOR of the other
5362 arm with some value. We compute three terms to be IOR'ed together. In
5363 practice, at most two will be nonzero. Then we do the IOR's. */
5365 if (GET_CODE (dest
) != PC
5366 && GET_CODE (src
) == IF_THEN_ELSE
5367 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5368 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5369 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5370 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5371 #ifdef HAVE_conditional_move
5372 && ! can_conditionally_move_p (GET_MODE (src
))
5374 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5375 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5376 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5377 && ! side_effects_p (src
))
5379 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5380 ? XEXP (src
, 1) : XEXP (src
, 2));
5381 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5382 ? XEXP (src
, 2) : XEXP (src
, 1));
5383 rtx term1
= const0_rtx
, term2
, term3
;
5385 if (GET_CODE (true_rtx
) == IOR
5386 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5387 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5388 else if (GET_CODE (true_rtx
) == IOR
5389 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5390 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5391 else if (GET_CODE (false_rtx
) == IOR
5392 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5393 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5394 else if (GET_CODE (false_rtx
) == IOR
5395 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5396 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5398 term2
= gen_binary (AND
, GET_MODE (src
),
5399 XEXP (XEXP (src
, 0), 0), true_rtx
);
5400 term3
= gen_binary (AND
, GET_MODE (src
),
5401 simplify_gen_unary (NOT
, GET_MODE (src
),
5402 XEXP (XEXP (src
, 0), 0),
5407 gen_binary (IOR
, GET_MODE (src
),
5408 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5414 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5415 whole thing fail. */
5416 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5418 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5421 /* Convert this into a field assignment operation, if possible. */
5422 return make_field_assignment (x
);
5425 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5429 simplify_logical (rtx x
)
5431 enum machine_mode mode
= GET_MODE (x
);
5432 rtx op0
= XEXP (x
, 0);
5433 rtx op1
= XEXP (x
, 1);
5436 switch (GET_CODE (x
))
5439 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5440 insn (and may simplify more). */
5441 if (GET_CODE (op0
) == XOR
5442 && rtx_equal_p (XEXP (op0
, 0), op1
)
5443 && ! side_effects_p (op1
))
5444 x
= gen_binary (AND
, mode
,
5445 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5448 if (GET_CODE (op0
) == XOR
5449 && rtx_equal_p (XEXP (op0
, 1), op1
)
5450 && ! side_effects_p (op1
))
5451 x
= gen_binary (AND
, mode
,
5452 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5455 /* Similarly for (~(A ^ B)) & A. */
5456 if (GET_CODE (op0
) == NOT
5457 && GET_CODE (XEXP (op0
, 0)) == XOR
5458 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5459 && ! side_effects_p (op1
))
5460 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5462 if (GET_CODE (op0
) == NOT
5463 && GET_CODE (XEXP (op0
, 0)) == XOR
5464 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5465 && ! side_effects_p (op1
))
5466 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5468 /* We can call simplify_and_const_int only if we don't lose
5469 any (sign) bits when converting INTVAL (op1) to
5470 "unsigned HOST_WIDE_INT". */
5471 if (GET_CODE (op1
) == CONST_INT
5472 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5473 || INTVAL (op1
) > 0))
5475 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5477 /* If we have (ior (and (X C1) C2)) and the next restart would be
5478 the last, simplify this by making C1 as small as possible
5479 and then exit. Only do this if C1 actually changes: for now
5480 this only saves memory but, should this transformation be
5481 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5482 if (GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5483 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5484 && GET_CODE (op1
) == CONST_INT
5485 && (INTVAL (XEXP (op0
, 1)) & INTVAL (op1
)) != 0)
5486 return gen_binary (IOR
, mode
,
5487 gen_binary (AND
, mode
, XEXP (op0
, 0),
5488 GEN_INT (INTVAL (XEXP (op0
, 1))
5489 & ~INTVAL (op1
))), op1
);
5491 if (GET_CODE (x
) != AND
)
5498 /* Convert (A | B) & A to A. */
5499 if (GET_CODE (op0
) == IOR
5500 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5501 || rtx_equal_p (XEXP (op0
, 1), op1
))
5502 && ! side_effects_p (XEXP (op0
, 0))
5503 && ! side_effects_p (XEXP (op0
, 1)))
5506 /* In the following group of tests (and those in case IOR below),
5507 we start with some combination of logical operations and apply
5508 the distributive law followed by the inverse distributive law.
5509 Most of the time, this results in no change. However, if some of
5510 the operands are the same or inverses of each other, simplifications
5513 For example, (and (ior A B) (not B)) can occur as the result of
5514 expanding a bit field assignment. When we apply the distributive
5515 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5516 which then simplifies to (and (A (not B))).
5518 If we have (and (ior A B) C), apply the distributive law and then
5519 the inverse distributive law to see if things simplify. */
5521 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5523 x
= apply_distributive_law
5524 (gen_binary (GET_CODE (op0
), mode
,
5525 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5526 gen_binary (AND
, mode
, XEXP (op0
, 1),
5528 if (GET_CODE (x
) != AND
)
5532 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5533 return apply_distributive_law
5534 (gen_binary (GET_CODE (op1
), mode
,
5535 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5536 gen_binary (AND
, mode
, XEXP (op1
, 1),
5539 /* Similarly, taking advantage of the fact that
5540 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5542 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5543 return apply_distributive_law
5544 (gen_binary (XOR
, mode
,
5545 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5546 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5549 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5550 return apply_distributive_law
5551 (gen_binary (XOR
, mode
,
5552 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5553 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5557 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5558 if (GET_CODE (op1
) == CONST_INT
5559 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5560 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5563 /* Convert (A & B) | A to A. */
5564 if (GET_CODE (op0
) == AND
5565 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5566 || rtx_equal_p (XEXP (op0
, 1), op1
))
5567 && ! side_effects_p (XEXP (op0
, 0))
5568 && ! side_effects_p (XEXP (op0
, 1)))
5571 /* If we have (ior (and A B) C), apply the distributive law and then
5572 the inverse distributive law to see if things simplify. */
5574 if (GET_CODE (op0
) == AND
)
5576 x
= apply_distributive_law
5577 (gen_binary (AND
, mode
,
5578 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5579 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5582 if (GET_CODE (x
) != IOR
)
5586 if (GET_CODE (op1
) == AND
)
5588 x
= apply_distributive_law
5589 (gen_binary (AND
, mode
,
5590 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5591 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5594 if (GET_CODE (x
) != IOR
)
5598 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5599 mode size to (rotate A CX). */
5601 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5602 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5603 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5604 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5605 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5606 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5607 == GET_MODE_BITSIZE (mode
)))
5608 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5609 (GET_CODE (op0
) == ASHIFT
5610 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5612 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5613 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5614 does not affect any of the bits in OP1, it can really be done
5615 as a PLUS and we can associate. We do this by seeing if OP1
5616 can be safely shifted left C bits. */
5617 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5618 && GET_CODE (XEXP (op0
, 0)) == PLUS
5619 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5620 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5621 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5623 int count
= INTVAL (XEXP (op0
, 1));
5624 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5626 if (mask
>> count
== INTVAL (op1
)
5627 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5629 SUBST (XEXP (XEXP (op0
, 0), 1),
5630 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5637 /* If we are XORing two things that have no bits in common,
5638 convert them into an IOR. This helps to detect rotation encoded
5639 using those methods and possibly other simplifications. */
5641 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5642 && (nonzero_bits (op0
, mode
)
5643 & nonzero_bits (op1
, mode
)) == 0)
5644 return (gen_binary (IOR
, mode
, op0
, op1
));
5646 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5647 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5650 int num_negated
= 0;
5652 if (GET_CODE (op0
) == NOT
)
5653 num_negated
++, op0
= XEXP (op0
, 0);
5654 if (GET_CODE (op1
) == NOT
)
5655 num_negated
++, op1
= XEXP (op1
, 0);
5657 if (num_negated
== 2)
5659 SUBST (XEXP (x
, 0), op0
);
5660 SUBST (XEXP (x
, 1), op1
);
5662 else if (num_negated
== 1)
5664 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5668 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5669 correspond to a machine insn or result in further simplifications
5670 if B is a constant. */
5672 if (GET_CODE (op0
) == AND
5673 && rtx_equal_p (XEXP (op0
, 1), op1
)
5674 && ! side_effects_p (op1
))
5675 return gen_binary (AND
, mode
,
5676 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5679 else if (GET_CODE (op0
) == AND
5680 && rtx_equal_p (XEXP (op0
, 0), op1
)
5681 && ! side_effects_p (op1
))
5682 return gen_binary (AND
, mode
,
5683 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5686 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5687 comparison if STORE_FLAG_VALUE is 1. */
5688 if (STORE_FLAG_VALUE
== 1
5689 && op1
== const1_rtx
5690 && COMPARISON_P (op0
)
5691 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5695 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5696 is (lt foo (const_int 0)), so we can perform the above
5697 simplification if STORE_FLAG_VALUE is 1. */
5699 if (STORE_FLAG_VALUE
== 1
5700 && op1
== const1_rtx
5701 && GET_CODE (op0
) == LSHIFTRT
5702 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5703 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5704 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5706 /* (xor (comparison foo bar) (const_int sign-bit))
5707 when STORE_FLAG_VALUE is the sign bit. */
5708 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5709 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5710 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5711 && op1
== const_true_rtx
5712 && COMPARISON_P (op0
)
5713 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5726 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5727 operations" because they can be replaced with two more basic operations.
5728 ZERO_EXTEND is also considered "compound" because it can be replaced with
5729 an AND operation, which is simpler, though only one operation.
5731 The function expand_compound_operation is called with an rtx expression
5732 and will convert it to the appropriate shifts and AND operations,
5733 simplifying at each stage.
5735 The function make_compound_operation is called to convert an expression
5736 consisting of shifts and ANDs into the equivalent compound expression.
5737 It is the inverse of this function, loosely speaking. */
5740 expand_compound_operation (rtx x
)
5742 unsigned HOST_WIDE_INT pos
= 0, len
;
5744 unsigned int modewidth
;
5747 switch (GET_CODE (x
))
5752 /* We can't necessarily use a const_int for a multiword mode;
5753 it depends on implicitly extending the value.
5754 Since we don't know the right way to extend it,
5755 we can't tell whether the implicit way is right.
5757 Even for a mode that is no wider than a const_int,
5758 we can't win, because we need to sign extend one of its bits through
5759 the rest of it, and we don't know which bit. */
5760 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5763 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5764 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5765 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5766 reloaded. If not for that, MEM's would very rarely be safe.
5768 Reject MODEs bigger than a word, because we might not be able
5769 to reference a two-register group starting with an arbitrary register
5770 (and currently gen_lowpart might crash for a SUBREG). */
5772 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5775 /* Reject MODEs that aren't scalar integers because turning vector
5776 or complex modes into shifts causes problems. */
5778 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5781 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5782 /* If the inner object has VOIDmode (the only way this can happen
5783 is if it is an ASM_OPERANDS), we can't do anything since we don't
5784 know how much masking to do. */
5793 /* If the operand is a CLOBBER, just return it. */
5794 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5797 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5798 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5799 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5802 /* Reject MODEs that aren't scalar integers because turning vector
5803 or complex modes into shifts causes problems. */
5805 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5808 len
= INTVAL (XEXP (x
, 1));
5809 pos
= INTVAL (XEXP (x
, 2));
5811 /* If this goes outside the object being extracted, replace the object
5812 with a (use (mem ...)) construct that only combine understands
5813 and is used only for this purpose. */
5814 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5815 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5817 if (BITS_BIG_ENDIAN
)
5818 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5825 /* Convert sign extension to zero extension, if we know that the high
5826 bit is not set, as this is easier to optimize. It will be converted
5827 back to cheaper alternative in make_extraction. */
5828 if (GET_CODE (x
) == SIGN_EXTEND
5829 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5830 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5831 & ~(((unsigned HOST_WIDE_INT
)
5832 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5836 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5837 rtx temp2
= expand_compound_operation (temp
);
5839 /* Make sure this is a profitable operation. */
5840 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5842 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5848 /* We can optimize some special cases of ZERO_EXTEND. */
5849 if (GET_CODE (x
) == ZERO_EXTEND
)
5851 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5852 know that the last value didn't have any inappropriate bits
5854 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5855 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5856 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5857 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5858 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5859 return XEXP (XEXP (x
, 0), 0);
5861 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5862 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5863 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5864 && subreg_lowpart_p (XEXP (x
, 0))
5865 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5866 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5867 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5868 return SUBREG_REG (XEXP (x
, 0));
5870 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5871 is a comparison and STORE_FLAG_VALUE permits. This is like
5872 the first case, but it works even when GET_MODE (x) is larger
5873 than HOST_WIDE_INT. */
5874 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5875 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5876 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
5877 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5878 <= HOST_BITS_PER_WIDE_INT
)
5879 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5880 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5881 return XEXP (XEXP (x
, 0), 0);
5883 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5884 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5885 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5886 && subreg_lowpart_p (XEXP (x
, 0))
5887 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
5888 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5889 <= HOST_BITS_PER_WIDE_INT
)
5890 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5891 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5892 return SUBREG_REG (XEXP (x
, 0));
5896 /* If we reach here, we want to return a pair of shifts. The inner
5897 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5898 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5899 logical depending on the value of UNSIGNEDP.
5901 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5902 converted into an AND of a shift.
5904 We must check for the case where the left shift would have a negative
5905 count. This can happen in a case like (x >> 31) & 255 on machines
5906 that can't shift by a constant. On those machines, we would first
5907 combine the shift with the AND to produce a variable-position
5908 extraction. Then the constant of 31 would be substituted in to produce
5909 a such a position. */
5911 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5912 if (modewidth
+ len
>= pos
)
5913 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5915 simplify_shift_const (NULL_RTX
, ASHIFT
,
5918 modewidth
- pos
- len
),
5921 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5922 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5923 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5926 ((HOST_WIDE_INT
) 1 << len
) - 1);
5928 /* Any other cases we can't handle. */
5931 /* If we couldn't do this for some reason, return the original
5933 if (GET_CODE (tem
) == CLOBBER
)
5939 /* X is a SET which contains an assignment of one object into
5940 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5941 or certain SUBREGS). If possible, convert it into a series of
5944 We half-heartedly support variable positions, but do not at all
5945 support variable lengths. */
5948 expand_field_assignment (rtx x
)
5951 rtx pos
; /* Always counts from low bit. */
5954 enum machine_mode compute_mode
;
5956 /* Loop until we find something we can't simplify. */
5959 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5960 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5962 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5963 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5964 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5966 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5967 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5969 inner
= XEXP (SET_DEST (x
), 0);
5970 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5971 pos
= XEXP (SET_DEST (x
), 2);
5973 /* If the position is constant and spans the width of INNER,
5974 surround INNER with a USE to indicate this. */
5975 if (GET_CODE (pos
) == CONST_INT
5976 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5977 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5979 if (BITS_BIG_ENDIAN
)
5981 if (GET_CODE (pos
) == CONST_INT
)
5982 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5984 else if (GET_CODE (pos
) == MINUS
5985 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5986 && (INTVAL (XEXP (pos
, 1))
5987 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5988 /* If position is ADJUST - X, new position is X. */
5989 pos
= XEXP (pos
, 0);
5991 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5992 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5998 /* A SUBREG between two modes that occupy the same numbers of words
5999 can be done by moving the SUBREG to the source. */
6000 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6001 /* We need SUBREGs to compute nonzero_bits properly. */
6002 && nonzero_sign_valid
6003 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6004 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6005 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6006 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6008 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6010 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6017 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6018 inner
= SUBREG_REG (inner
);
6020 compute_mode
= GET_MODE (inner
);
6022 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6023 if (! SCALAR_INT_MODE_P (compute_mode
))
6025 enum machine_mode imode
;
6027 /* Don't do anything for vector or complex integral types. */
6028 if (! FLOAT_MODE_P (compute_mode
))
6031 /* Try to find an integral mode to pun with. */
6032 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6033 if (imode
== BLKmode
)
6036 compute_mode
= imode
;
6037 inner
= gen_lowpart (imode
, inner
);
6040 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6041 if (len
< HOST_BITS_PER_WIDE_INT
)
6042 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
6046 /* Now compute the equivalent expression. Make a copy of INNER
6047 for the SET_DEST in case it is a MEM into which we will substitute;
6048 we don't want shared RTL in that case. */
6050 (VOIDmode
, copy_rtx (inner
),
6051 gen_binary (IOR
, compute_mode
,
6052 gen_binary (AND
, compute_mode
,
6053 simplify_gen_unary (NOT
, compute_mode
,
6059 gen_binary (ASHIFT
, compute_mode
,
6060 gen_binary (AND
, compute_mode
,
6062 (compute_mode
, SET_SRC (x
)),
6070 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6071 it is an RTX that represents a variable starting position; otherwise,
6072 POS is the (constant) starting bit position (counted from the LSB).
6074 INNER may be a USE. This will occur when we started with a bitfield
6075 that went outside the boundary of the object in memory, which is
6076 allowed on most machines. To isolate this case, we produce a USE
6077 whose mode is wide enough and surround the MEM with it. The only
6078 code that understands the USE is this routine. If it is not removed,
6079 it will cause the resulting insn not to match.
6081 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6084 IN_DEST is nonzero if this is a reference in the destination of a
6085 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6086 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6089 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6090 ZERO_EXTRACT should be built even for bits starting at bit 0.
6092 MODE is the desired mode of the result (if IN_DEST == 0).
6094 The result is an RTX for the extraction or NULL_RTX if the target
6098 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6099 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6100 int in_dest
, int in_compare
)
6102 /* This mode describes the size of the storage area
6103 to fetch the overall value from. Within that, we
6104 ignore the POS lowest bits, etc. */
6105 enum machine_mode is_mode
= GET_MODE (inner
);
6106 enum machine_mode inner_mode
;
6107 enum machine_mode wanted_inner_mode
= byte_mode
;
6108 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6109 enum machine_mode pos_mode
= word_mode
;
6110 enum machine_mode extraction_mode
= word_mode
;
6111 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6114 rtx orig_pos_rtx
= pos_rtx
;
6115 HOST_WIDE_INT orig_pos
;
6117 /* Get some information about INNER and get the innermost object. */
6118 if (GET_CODE (inner
) == USE
)
6119 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6120 /* We don't need to adjust the position because we set up the USE
6121 to pretend that it was a full-word object. */
6122 spans_byte
= 1, inner
= XEXP (inner
, 0);
6123 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6125 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6126 consider just the QI as the memory to extract from.
6127 The subreg adds or removes high bits; its mode is
6128 irrelevant to the meaning of this extraction,
6129 since POS and LEN count from the lsb. */
6130 if (MEM_P (SUBREG_REG (inner
)))
6131 is_mode
= GET_MODE (SUBREG_REG (inner
));
6132 inner
= SUBREG_REG (inner
);
6134 else if (GET_CODE (inner
) == ASHIFT
6135 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
6136 && pos_rtx
== 0 && pos
== 0
6137 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6139 /* We're extracting the least significant bits of an rtx
6140 (ashift X (const_int C)), where LEN > C. Extract the
6141 least significant (LEN - C) bits of X, giving an rtx
6142 whose mode is MODE, then shift it left C times. */
6143 new = make_extraction (mode
, XEXP (inner
, 0),
6144 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6145 unsignedp
, in_dest
, in_compare
);
6147 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6150 inner_mode
= GET_MODE (inner
);
6152 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6153 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6155 /* See if this can be done without an extraction. We never can if the
6156 width of the field is not the same as that of some integer mode. For
6157 registers, we can only avoid the extraction if the position is at the
6158 low-order bit and this is either not in the destination or we have the
6159 appropriate STRICT_LOW_PART operation available.
6161 For MEM, we can avoid an extract if the field starts on an appropriate
6162 boundary and we can change the mode of the memory reference. However,
6163 we cannot directly access the MEM if we have a USE and the underlying
6164 MEM is not TMODE. This combination means that MEM was being used in a
6165 context where bits outside its mode were being referenced; that is only
6166 valid in bit-field insns. */
6168 if (tmode
!= BLKmode
6169 && ! (spans_byte
&& inner_mode
!= tmode
)
6170 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6174 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6175 || (MEM_P (inner
) && pos_rtx
== 0
6177 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6178 : BITS_PER_UNIT
)) == 0
6179 /* We can't do this if we are widening INNER_MODE (it
6180 may not be aligned, for one thing). */
6181 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6182 && (inner_mode
== tmode
6183 || (! mode_dependent_address_p (XEXP (inner
, 0))
6184 && ! MEM_VOLATILE_P (inner
))))))
6186 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6187 field. If the original and current mode are the same, we need not
6188 adjust the offset. Otherwise, we do if bytes big endian.
6190 If INNER is not a MEM, get a piece consisting of just the field
6191 of interest (in this case POS % BITS_PER_WORD must be 0). */
6195 HOST_WIDE_INT offset
;
6197 /* POS counts from lsb, but make OFFSET count in memory order. */
6198 if (BYTES_BIG_ENDIAN
)
6199 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6201 offset
= pos
/ BITS_PER_UNIT
;
6203 new = adjust_address_nv (inner
, tmode
, offset
);
6205 else if (REG_P (inner
))
6207 if (tmode
!= inner_mode
)
6209 /* We can't call gen_lowpart in a DEST since we
6210 always want a SUBREG (see below) and it would sometimes
6211 return a new hard register. */
6214 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6216 if (WORDS_BIG_ENDIAN
6217 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6218 final_word
= ((GET_MODE_SIZE (inner_mode
)
6219 - GET_MODE_SIZE (tmode
))
6220 / UNITS_PER_WORD
) - final_word
;
6222 final_word
*= UNITS_PER_WORD
;
6223 if (BYTES_BIG_ENDIAN
&&
6224 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6225 final_word
+= (GET_MODE_SIZE (inner_mode
)
6226 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6228 /* Avoid creating invalid subregs, for example when
6229 simplifying (x>>32)&255. */
6230 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6233 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6236 new = gen_lowpart (tmode
, inner
);
6242 new = force_to_mode (inner
, tmode
,
6243 len
>= HOST_BITS_PER_WIDE_INT
6244 ? ~(unsigned HOST_WIDE_INT
) 0
6245 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6248 /* If this extraction is going into the destination of a SET,
6249 make a STRICT_LOW_PART unless we made a MEM. */
6252 return (MEM_P (new) ? new
6253 : (GET_CODE (new) != SUBREG
6254 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6255 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6260 if (GET_CODE (new) == CONST_INT
)
6261 return gen_int_mode (INTVAL (new), mode
);
6263 /* If we know that no extraneous bits are set, and that the high
6264 bit is not set, convert the extraction to the cheaper of
6265 sign and zero extension, that are equivalent in these cases. */
6266 if (flag_expensive_optimizations
6267 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6268 && ((nonzero_bits (new, tmode
)
6269 & ~(((unsigned HOST_WIDE_INT
)
6270 GET_MODE_MASK (tmode
))
6274 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6275 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6277 /* Prefer ZERO_EXTENSION, since it gives more information to
6279 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6284 /* Otherwise, sign- or zero-extend unless we already are in the
6287 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6291 /* Unless this is a COMPARE or we have a funny memory reference,
6292 don't do anything with zero-extending field extracts starting at
6293 the low-order bit since they are simple AND operations. */
6294 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6295 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6298 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6299 we would be spanning bytes or if the position is not a constant and the
6300 length is not 1. In all other cases, we would only be going outside
6301 our object in cases when an original shift would have been
6303 if (! spans_byte
&& MEM_P (inner
)
6304 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6305 || (pos_rtx
!= 0 && len
!= 1)))
6308 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6309 and the mode for the result. */
6310 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6312 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6313 pos_mode
= mode_for_extraction (EP_insv
, 2);
6314 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6317 if (! in_dest
&& unsignedp
6318 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6320 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6321 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6322 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6325 if (! in_dest
&& ! unsignedp
6326 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6328 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6329 pos_mode
= mode_for_extraction (EP_extv
, 3);
6330 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6333 /* Never narrow an object, since that might not be safe. */
6335 if (mode
!= VOIDmode
6336 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6337 extraction_mode
= mode
;
6339 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6340 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6341 pos_mode
= GET_MODE (pos_rtx
);
6343 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6344 if we have to change the mode of memory and cannot, the desired mode is
6347 wanted_inner_mode
= wanted_inner_reg_mode
;
6348 else if (inner_mode
!= wanted_inner_mode
6349 && (mode_dependent_address_p (XEXP (inner
, 0))
6350 || MEM_VOLATILE_P (inner
)))
6351 wanted_inner_mode
= extraction_mode
;
6355 if (BITS_BIG_ENDIAN
)
6357 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6358 BITS_BIG_ENDIAN style. If position is constant, compute new
6359 position. Otherwise, build subtraction.
6360 Note that POS is relative to the mode of the original argument.
6361 If it's a MEM we need to recompute POS relative to that.
6362 However, if we're extracting from (or inserting into) a register,
6363 we want to recompute POS relative to wanted_inner_mode. */
6364 int width
= (MEM_P (inner
)
6365 ? GET_MODE_BITSIZE (is_mode
)
6366 : GET_MODE_BITSIZE (wanted_inner_mode
));
6369 pos
= width
- len
- pos
;
6372 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6373 /* POS may be less than 0 now, but we check for that below.
6374 Note that it can only be less than 0 if !MEM_P (inner). */
6377 /* If INNER has a wider mode, make it smaller. If this is a constant
6378 extract, try to adjust the byte to point to the byte containing
6380 if (wanted_inner_mode
!= VOIDmode
6381 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6383 && (inner_mode
== wanted_inner_mode
6384 || (! mode_dependent_address_p (XEXP (inner
, 0))
6385 && ! MEM_VOLATILE_P (inner
))))))
6389 /* The computations below will be correct if the machine is big
6390 endian in both bits and bytes or little endian in bits and bytes.
6391 If it is mixed, we must adjust. */
6393 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6394 adjust OFFSET to compensate. */
6395 if (BYTES_BIG_ENDIAN
6397 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6398 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6400 /* If this is a constant position, we can move to the desired byte. */
6403 offset
+= pos
/ BITS_PER_UNIT
;
6404 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6407 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6409 && is_mode
!= wanted_inner_mode
)
6410 offset
= (GET_MODE_SIZE (is_mode
)
6411 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6413 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6414 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6417 /* If INNER is not memory, we can always get it into the proper mode. If we
6418 are changing its mode, POS must be a constant and smaller than the size
6420 else if (!MEM_P (inner
))
6422 if (GET_MODE (inner
) != wanted_inner_mode
6424 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6427 inner
= force_to_mode (inner
, wanted_inner_mode
,
6429 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6430 ? ~(unsigned HOST_WIDE_INT
) 0
6431 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6436 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6437 have to zero extend. Otherwise, we can just use a SUBREG. */
6439 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6441 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6443 /* If we know that no extraneous bits are set, and that the high
6444 bit is not set, convert extraction to cheaper one - either
6445 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6447 if (flag_expensive_optimizations
6448 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6449 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6450 & ~(((unsigned HOST_WIDE_INT
)
6451 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6455 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6457 /* Prefer ZERO_EXTENSION, since it gives more information to
6459 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6464 else if (pos_rtx
!= 0
6465 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6466 pos_rtx
= gen_lowpart (pos_mode
, pos_rtx
);
6468 /* Make POS_RTX unless we already have it and it is correct. If we don't
6469 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6471 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6472 pos_rtx
= orig_pos_rtx
;
6474 else if (pos_rtx
== 0)
6475 pos_rtx
= GEN_INT (pos
);
6477 /* Make the required operation. See if we can use existing rtx. */
6478 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6479 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6481 new = gen_lowpart (mode
, new);
6486 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6487 with any other operations in X. Return X without that shift if so. */
6490 extract_left_shift (rtx x
, int count
)
6492 enum rtx_code code
= GET_CODE (x
);
6493 enum machine_mode mode
= GET_MODE (x
);
6499 /* This is the shift itself. If it is wide enough, we will return
6500 either the value being shifted if the shift count is equal to
6501 COUNT or a shift for the difference. */
6502 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6503 && INTVAL (XEXP (x
, 1)) >= count
)
6504 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6505 INTVAL (XEXP (x
, 1)) - count
);
6509 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6510 return simplify_gen_unary (code
, mode
, tem
, mode
);
6514 case PLUS
: case IOR
: case XOR
: case AND
:
6515 /* If we can safely shift this constant and we find the inner shift,
6516 make a new operation. */
6517 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6518 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6519 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6520 return gen_binary (code
, mode
, tem
,
6521 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6532 /* Look at the expression rooted at X. Look for expressions
6533 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6534 Form these expressions.
6536 Return the new rtx, usually just X.
6538 Also, for machines like the VAX that don't have logical shift insns,
6539 try to convert logical to arithmetic shift operations in cases where
6540 they are equivalent. This undoes the canonicalizations to logical
6541 shifts done elsewhere.
6543 We try, as much as possible, to re-use rtl expressions to save memory.
6545 IN_CODE says what kind of expression we are processing. Normally, it is
6546 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6547 being kludges), it is MEM. When processing the arguments of a comparison
6548 or a COMPARE against zero, it is COMPARE. */
6551 make_compound_operation (rtx x
, enum rtx_code in_code
)
6553 enum rtx_code code
= GET_CODE (x
);
6554 enum machine_mode mode
= GET_MODE (x
);
6555 int mode_width
= GET_MODE_BITSIZE (mode
);
6557 enum rtx_code next_code
;
6563 /* Select the code to be used in recursive calls. Once we are inside an
6564 address, we stay there. If we have a comparison, set to COMPARE,
6565 but once inside, go back to our default of SET. */
6567 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6568 : ((code
== COMPARE
|| COMPARISON_P (x
))
6569 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6570 : in_code
== COMPARE
? SET
: in_code
);
6572 /* Process depending on the code of this operation. If NEW is set
6573 nonzero, it will be returned. */
6578 /* Convert shifts by constants into multiplications if inside
6580 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6581 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6582 && INTVAL (XEXP (x
, 1)) >= 0)
6584 new = make_compound_operation (XEXP (x
, 0), next_code
);
6585 new = gen_rtx_MULT (mode
, new,
6586 GEN_INT ((HOST_WIDE_INT
) 1
6587 << INTVAL (XEXP (x
, 1))));
6592 /* If the second operand is not a constant, we can't do anything
6594 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6597 /* If the constant is a power of two minus one and the first operand
6598 is a logical right shift, make an extraction. */
6599 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6600 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6602 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6603 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6604 0, in_code
== COMPARE
);
6607 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6608 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6609 && subreg_lowpart_p (XEXP (x
, 0))
6610 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6611 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6613 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6615 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6616 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6617 0, in_code
== COMPARE
);
6619 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6620 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6621 || GET_CODE (XEXP (x
, 0)) == IOR
)
6622 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6623 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6624 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6626 /* Apply the distributive law, and then try to make extractions. */
6627 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6628 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6630 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6632 new = make_compound_operation (new, in_code
);
6635 /* If we are have (and (rotate X C) M) and C is larger than the number
6636 of bits in M, this is an extraction. */
6638 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6639 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6640 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6641 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6643 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6644 new = make_extraction (mode
, new,
6645 (GET_MODE_BITSIZE (mode
)
6646 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6647 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6650 /* On machines without logical shifts, if the operand of the AND is
6651 a logical shift and our mask turns off all the propagated sign
6652 bits, we can replace the logical shift with an arithmetic shift. */
6653 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6654 && !have_insn_for (LSHIFTRT
, mode
)
6655 && have_insn_for (ASHIFTRT
, mode
)
6656 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6657 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6658 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6659 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6661 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6663 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6664 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6666 gen_rtx_ASHIFTRT (mode
,
6667 make_compound_operation
6668 (XEXP (XEXP (x
, 0), 0), next_code
),
6669 XEXP (XEXP (x
, 0), 1)));
6672 /* If the constant is one less than a power of two, this might be
6673 representable by an extraction even if no shift is present.
6674 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6675 we are in a COMPARE. */
6676 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6677 new = make_extraction (mode
,
6678 make_compound_operation (XEXP (x
, 0),
6680 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6682 /* If we are in a comparison and this is an AND with a power of two,
6683 convert this into the appropriate bit extract. */
6684 else if (in_code
== COMPARE
6685 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6686 new = make_extraction (mode
,
6687 make_compound_operation (XEXP (x
, 0),
6689 i
, NULL_RTX
, 1, 1, 0, 1);
6694 /* If the sign bit is known to be zero, replace this with an
6695 arithmetic shift. */
6696 if (have_insn_for (ASHIFTRT
, mode
)
6697 && ! have_insn_for (LSHIFTRT
, mode
)
6698 && mode_width
<= HOST_BITS_PER_WIDE_INT
6699 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6701 new = gen_rtx_ASHIFTRT (mode
,
6702 make_compound_operation (XEXP (x
, 0),
6708 /* ... fall through ... */
6714 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6715 this is a SIGN_EXTRACT. */
6716 if (GET_CODE (rhs
) == CONST_INT
6717 && GET_CODE (lhs
) == ASHIFT
6718 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6719 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6721 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6722 new = make_extraction (mode
, new,
6723 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6724 NULL_RTX
, mode_width
- INTVAL (rhs
),
6725 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6729 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6730 If so, try to merge the shifts into a SIGN_EXTEND. We could
6731 also do this for some cases of SIGN_EXTRACT, but it doesn't
6732 seem worth the effort; the case checked for occurs on Alpha. */
6735 && ! (GET_CODE (lhs
) == SUBREG
6736 && (OBJECT_P (SUBREG_REG (lhs
))))
6737 && GET_CODE (rhs
) == CONST_INT
6738 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6739 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6740 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6741 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6742 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6747 /* Call ourselves recursively on the inner expression. If we are
6748 narrowing the object and it has a different RTL code from
6749 what it originally did, do this SUBREG as a force_to_mode. */
6751 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6752 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6753 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6754 && subreg_lowpart_p (x
))
6756 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6759 /* If we have something other than a SUBREG, we might have
6760 done an expansion, so rerun ourselves. */
6761 if (GET_CODE (newer
) != SUBREG
)
6762 newer
= make_compound_operation (newer
, in_code
);
6767 /* If this is a paradoxical subreg, and the new code is a sign or
6768 zero extension, omit the subreg and widen the extension. If it
6769 is a regular subreg, we can still get rid of the subreg by not
6770 widening so much, or in fact removing the extension entirely. */
6771 if ((GET_CODE (tem
) == SIGN_EXTEND
6772 || GET_CODE (tem
) == ZERO_EXTEND
)
6773 && subreg_lowpart_p (x
))
6775 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6776 || (GET_MODE_SIZE (mode
) >
6777 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6779 if (! SCALAR_INT_MODE_P (mode
))
6781 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6784 tem
= gen_lowpart (mode
, XEXP (tem
, 0));
6795 x
= gen_lowpart (mode
, new);
6796 code
= GET_CODE (x
);
6799 /* Now recursively process each operand of this operation. */
6800 fmt
= GET_RTX_FORMAT (code
);
6801 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6804 new = make_compound_operation (XEXP (x
, i
), next_code
);
6805 SUBST (XEXP (x
, i
), new);
6811 /* Given M see if it is a value that would select a field of bits
6812 within an item, but not the entire word. Return -1 if not.
6813 Otherwise, return the starting position of the field, where 0 is the
6816 *PLEN is set to the length of the field. */
6819 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6821 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6822 int pos
= exact_log2 (m
& -m
);
6826 /* Now shift off the low-order zero bits and see if we have a
6827 power of two minus 1. */
6828 len
= exact_log2 ((m
>> pos
) + 1);
6837 /* See if X can be simplified knowing that we will only refer to it in
6838 MODE and will only refer to those bits that are nonzero in MASK.
6839 If other bits are being computed or if masking operations are done
6840 that select a superset of the bits in MASK, they can sometimes be
6843 Return a possibly simplified expression, but always convert X to
6844 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6846 Also, if REG is nonzero and X is a register equal in value to REG,
6849 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6850 are all off in X. This is used when X will be complemented, by either
6851 NOT, NEG, or XOR. */
6854 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6855 rtx reg
, int just_select
)
6857 enum rtx_code code
= GET_CODE (x
);
6858 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6859 enum machine_mode op_mode
;
6860 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6863 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6864 code below will do the wrong thing since the mode of such an
6865 expression is VOIDmode.
6867 Also do nothing if X is a CLOBBER; this can happen if X was
6868 the return value from a call to gen_lowpart. */
6869 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6872 /* We want to perform the operation is its present mode unless we know
6873 that the operation is valid in MODE, in which case we do the operation
6875 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6876 && have_insn_for (code
, mode
))
6877 ? mode
: GET_MODE (x
));
6879 /* It is not valid to do a right-shift in a narrower mode
6880 than the one it came in with. */
6881 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6882 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6883 op_mode
= GET_MODE (x
);
6885 /* Truncate MASK to fit OP_MODE. */
6887 mask
&= GET_MODE_MASK (op_mode
);
6889 /* When we have an arithmetic operation, or a shift whose count we
6890 do not know, we need to assume that all bits up to the highest-order
6891 bit in MASK will be needed. This is how we form such a mask. */
6892 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6893 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6895 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6898 /* Determine what bits of X are guaranteed to be (non)zero. */
6899 nonzero
= nonzero_bits (x
, mode
);
6901 /* If none of the bits in X are needed, return a zero. */
6902 if (! just_select
&& (nonzero
& mask
) == 0)
6905 /* If X is a CONST_INT, return a new one. Do this here since the
6906 test below will fail. */
6907 if (GET_CODE (x
) == CONST_INT
)
6909 if (SCALAR_INT_MODE_P (mode
))
6910 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6913 x
= GEN_INT (INTVAL (x
) & mask
);
6914 return gen_lowpart_common (mode
, x
);
6918 /* If X is narrower than MODE and we want all the bits in X's mode, just
6919 get X in the proper mode. */
6920 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6921 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6922 return gen_lowpart (mode
, x
);
6927 /* If X is a (clobber (const_int)), return it since we know we are
6928 generating something that won't match. */
6932 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6933 spanned the boundary of the MEM. If we are now masking so it is
6934 within that boundary, we don't need the USE any more. */
6935 if (! BITS_BIG_ENDIAN
6936 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6937 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6944 x
= expand_compound_operation (x
);
6945 if (GET_CODE (x
) != code
)
6946 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6950 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6951 || rtx_equal_p (reg
, get_last_value (x
))))
6956 if (subreg_lowpart_p (x
)
6957 /* We can ignore the effect of this SUBREG if it narrows the mode or
6958 if the constant masks to zero all the bits the mode doesn't
6960 && ((GET_MODE_SIZE (GET_MODE (x
))
6961 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6963 & GET_MODE_MASK (GET_MODE (x
))
6964 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6965 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6969 /* If this is an AND with a constant, convert it into an AND
6970 whose constant is the AND of that constant with MASK. If it
6971 remains an AND of MASK, delete it since it is redundant. */
6973 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6975 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6976 mask
& INTVAL (XEXP (x
, 1)));
6978 /* If X is still an AND, see if it is an AND with a mask that
6979 is just some low-order bits. If so, and it is MASK, we don't
6982 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6983 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6987 /* If it remains an AND, try making another AND with the bits
6988 in the mode mask that aren't in MASK turned on. If the
6989 constant in the AND is wide enough, this might make a
6990 cheaper constant. */
6992 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6993 && GET_MODE_MASK (GET_MODE (x
)) != mask
6994 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6996 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6997 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6998 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
7001 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7002 number, sign extend it. */
7003 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
7004 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7005 cval
|= (HOST_WIDE_INT
) -1 << width
;
7007 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
7008 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
7018 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7019 low-order bits (as in an alignment operation) and FOO is already
7020 aligned to that boundary, mask C1 to that boundary as well.
7021 This may eliminate that PLUS and, later, the AND. */
7024 unsigned int width
= GET_MODE_BITSIZE (mode
);
7025 unsigned HOST_WIDE_INT smask
= mask
;
7027 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7028 number, sign extend it. */
7030 if (width
< HOST_BITS_PER_WIDE_INT
7031 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
7032 smask
|= (HOST_WIDE_INT
) -1 << width
;
7034 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7035 && exact_log2 (- smask
) >= 0
7036 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
7037 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
7038 return force_to_mode (plus_constant (XEXP (x
, 0),
7039 (INTVAL (XEXP (x
, 1)) & smask
)),
7040 mode
, smask
, reg
, next_select
);
7043 /* ... fall through ... */
7046 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7047 most significant bit in MASK since carries from those bits will
7048 affect the bits we are interested in. */
7053 /* If X is (minus C Y) where C's least set bit is larger than any bit
7054 in the mask, then we may replace with (neg Y). */
7055 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7056 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
7057 & -INTVAL (XEXP (x
, 0))))
7060 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
7062 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7065 /* Similarly, if C contains every bit in the fuller_mask, then we may
7066 replace with (not Y). */
7067 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7068 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
7069 == INTVAL (XEXP (x
, 0))))
7071 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
7072 XEXP (x
, 1), GET_MODE (x
));
7073 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7081 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7082 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7083 operation which may be a bitfield extraction. Ensure that the
7084 constant we form is not wider than the mode of X. */
7086 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7087 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7088 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7089 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7090 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7091 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
7092 + floor_log2 (INTVAL (XEXP (x
, 1))))
7093 < GET_MODE_BITSIZE (GET_MODE (x
)))
7094 && (INTVAL (XEXP (x
, 1))
7095 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
7097 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
7098 << INTVAL (XEXP (XEXP (x
, 0), 1)));
7099 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
7100 XEXP (XEXP (x
, 0), 0), temp
);
7101 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7102 XEXP (XEXP (x
, 0), 1));
7103 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7107 /* For most binary operations, just propagate into the operation and
7108 change the mode if we have an operation of that mode. */
7110 op0
= gen_lowpart (op_mode
,
7111 force_to_mode (XEXP (x
, 0), mode
, mask
,
7113 op1
= gen_lowpart (op_mode
,
7114 force_to_mode (XEXP (x
, 1), mode
, mask
,
7117 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7118 x
= gen_binary (code
, op_mode
, op0
, op1
);
7122 /* For left shifts, do the same, but just for the first operand.
7123 However, we cannot do anything with shifts where we cannot
7124 guarantee that the counts are smaller than the size of the mode
7125 because such a count will have a different meaning in a
7128 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7129 && INTVAL (XEXP (x
, 1)) >= 0
7130 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7131 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7132 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7133 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7136 /* If the shift count is a constant and we can do arithmetic in
7137 the mode of the shift, refine which bits we need. Otherwise, use the
7138 conservative form of the mask. */
7139 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7140 && INTVAL (XEXP (x
, 1)) >= 0
7141 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7142 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7143 mask
>>= INTVAL (XEXP (x
, 1));
7147 op0
= gen_lowpart (op_mode
,
7148 force_to_mode (XEXP (x
, 0), op_mode
,
7149 mask
, reg
, next_select
));
7151 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7152 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7156 /* Here we can only do something if the shift count is a constant,
7157 this shift constant is valid for the host, and we can do arithmetic
7160 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7161 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7162 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7164 rtx inner
= XEXP (x
, 0);
7165 unsigned HOST_WIDE_INT inner_mask
;
7167 /* Select the mask of the bits we need for the shift operand. */
7168 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7170 /* We can only change the mode of the shift if we can do arithmetic
7171 in the mode of the shift and INNER_MASK is no wider than the
7172 width of X's mode. */
7173 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
7174 op_mode
= GET_MODE (x
);
7176 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7178 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7179 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7182 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7183 shift and AND produces only copies of the sign bit (C2 is one less
7184 than a power of two), we can do this with just a shift. */
7186 if (GET_CODE (x
) == LSHIFTRT
7187 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7188 /* The shift puts one of the sign bit copies in the least significant
7190 && ((INTVAL (XEXP (x
, 1))
7191 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7192 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7193 && exact_log2 (mask
+ 1) >= 0
7194 /* Number of bits left after the shift must be more than the mask
7196 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7197 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7198 /* Must be more sign bit copies than the mask needs. */
7199 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7200 >= exact_log2 (mask
+ 1)))
7201 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7202 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7203 - exact_log2 (mask
+ 1)));
7208 /* If we are just looking for the sign bit, we don't need this shift at
7209 all, even if it has a variable count. */
7210 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7211 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7212 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7213 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7215 /* If this is a shift by a constant, get a mask that contains those bits
7216 that are not copies of the sign bit. We then have two cases: If
7217 MASK only includes those bits, this can be a logical shift, which may
7218 allow simplifications. If MASK is a single-bit field not within
7219 those bits, we are requesting a copy of the sign bit and hence can
7220 shift the sign bit to the appropriate location. */
7222 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7223 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7227 /* If the considered data is wider than HOST_WIDE_INT, we can't
7228 represent a mask for all its bits in a single scalar.
7229 But we only care about the lower bits, so calculate these. */
7231 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7233 nonzero
= ~(HOST_WIDE_INT
) 0;
7235 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7236 is the number of bits a full-width mask would have set.
7237 We need only shift if these are fewer than nonzero can
7238 hold. If not, we must keep all bits set in nonzero. */
7240 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7241 < HOST_BITS_PER_WIDE_INT
)
7242 nonzero
>>= INTVAL (XEXP (x
, 1))
7243 + HOST_BITS_PER_WIDE_INT
7244 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7248 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7249 nonzero
>>= INTVAL (XEXP (x
, 1));
7252 if ((mask
& ~nonzero
) == 0
7253 || (i
= exact_log2 (mask
)) >= 0)
7255 x
= simplify_shift_const
7256 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7257 i
< 0 ? INTVAL (XEXP (x
, 1))
7258 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7260 if (GET_CODE (x
) != ASHIFTRT
)
7261 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7265 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7266 even if the shift count isn't a constant. */
7268 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7272 /* If this is a zero- or sign-extension operation that just affects bits
7273 we don't care about, remove it. Be sure the call above returned
7274 something that is still a shift. */
7276 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7277 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7278 && INTVAL (XEXP (x
, 1)) >= 0
7279 && (INTVAL (XEXP (x
, 1))
7280 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7281 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7282 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7283 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7290 /* If the shift count is constant and we can do computations
7291 in the mode of X, compute where the bits we care about are.
7292 Otherwise, we can't do anything. Don't change the mode of
7293 the shift or propagate MODE into the shift, though. */
7294 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7295 && INTVAL (XEXP (x
, 1)) >= 0)
7297 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7298 GET_MODE (x
), GEN_INT (mask
),
7300 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7302 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7303 INTVAL (temp
), reg
, next_select
));
7308 /* If we just want the low-order bit, the NEG isn't needed since it
7309 won't change the low-order bit. */
7311 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7313 /* We need any bits less significant than the most significant bit in
7314 MASK since carries from those bits will affect the bits we are
7320 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7321 same as the XOR case above. Ensure that the constant we form is not
7322 wider than the mode of X. */
7324 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7325 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7326 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7327 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7328 < GET_MODE_BITSIZE (GET_MODE (x
)))
7329 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7331 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7333 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7334 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7336 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7339 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7340 use the full mask inside the NOT. */
7344 op0
= gen_lowpart (op_mode
,
7345 force_to_mode (XEXP (x
, 0), mode
, mask
,
7347 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7348 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7352 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7353 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7354 which is equal to STORE_FLAG_VALUE. */
7355 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7356 && GET_MODE (XEXP (x
, 0)) == mode
7357 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7358 && (nonzero_bits (XEXP (x
, 0), mode
)
7359 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7360 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7365 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7366 written in a narrower mode. We play it safe and do not do so. */
7369 gen_lowpart (GET_MODE (x
),
7370 force_to_mode (XEXP (x
, 1), mode
,
7371 mask
, reg
, next_select
)));
7373 gen_lowpart (GET_MODE (x
),
7374 force_to_mode (XEXP (x
, 2), mode
,
7375 mask
, reg
, next_select
)));
7382 /* Ensure we return a value of the proper mode. */
7383 return gen_lowpart (mode
, x
);
7386 /* Return nonzero if X is an expression that has one of two values depending on
7387 whether some other value is zero or nonzero. In that case, we return the
7388 value that is being tested, *PTRUE is set to the value if the rtx being
7389 returned has a nonzero value, and *PFALSE is set to the other alternative.
7391 If we return zero, we set *PTRUE and *PFALSE to X. */
7394 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7396 enum machine_mode mode
= GET_MODE (x
);
7397 enum rtx_code code
= GET_CODE (x
);
7398 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7399 unsigned HOST_WIDE_INT nz
;
7401 /* If we are comparing a value against zero, we are done. */
7402 if ((code
== NE
|| code
== EQ
)
7403 && XEXP (x
, 1) == const0_rtx
)
7405 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7406 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7410 /* If this is a unary operation whose operand has one of two values, apply
7411 our opcode to compute those values. */
7412 else if (UNARY_P (x
)
7413 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7415 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7416 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7417 GET_MODE (XEXP (x
, 0)));
7421 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7422 make can't possibly match and would suppress other optimizations. */
7423 else if (code
== COMPARE
)
7426 /* If this is a binary operation, see if either side has only one of two
7427 values. If either one does or if both do and they are conditional on
7428 the same value, compute the new true and false values. */
7429 else if (BINARY_P (x
))
7431 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7432 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7434 if ((cond0
!= 0 || cond1
!= 0)
7435 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7437 /* If if_then_else_cond returned zero, then true/false are the
7438 same rtl. We must copy one of them to prevent invalid rtl
7441 true0
= copy_rtx (true0
);
7442 else if (cond1
== 0)
7443 true1
= copy_rtx (true1
);
7445 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7446 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7447 return cond0
? cond0
: cond1
;
7450 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7451 operands is zero when the other is nonzero, and vice-versa,
7452 and STORE_FLAG_VALUE is 1 or -1. */
7454 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7455 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7457 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7459 rtx op0
= XEXP (XEXP (x
, 0), 1);
7460 rtx op1
= XEXP (XEXP (x
, 1), 1);
7462 cond0
= XEXP (XEXP (x
, 0), 0);
7463 cond1
= XEXP (XEXP (x
, 1), 0);
7465 if (COMPARISON_P (cond0
)
7466 && COMPARISON_P (cond1
)
7467 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7468 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7469 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7470 || ((swap_condition (GET_CODE (cond0
))
7471 == combine_reversed_comparison_code (cond1
))
7472 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7473 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7474 && ! side_effects_p (x
))
7476 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7477 *pfalse
= gen_binary (MULT
, mode
,
7479 ? simplify_gen_unary (NEG
, mode
, op1
,
7487 /* Similarly for MULT, AND and UMIN, except that for these the result
7489 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7490 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7491 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7493 cond0
= XEXP (XEXP (x
, 0), 0);
7494 cond1
= XEXP (XEXP (x
, 1), 0);
7496 if (COMPARISON_P (cond0
)
7497 && COMPARISON_P (cond1
)
7498 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7499 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7500 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7501 || ((swap_condition (GET_CODE (cond0
))
7502 == combine_reversed_comparison_code (cond1
))
7503 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7504 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7505 && ! side_effects_p (x
))
7507 *ptrue
= *pfalse
= const0_rtx
;
7513 else if (code
== IF_THEN_ELSE
)
7515 /* If we have IF_THEN_ELSE already, extract the condition and
7516 canonicalize it if it is NE or EQ. */
7517 cond0
= XEXP (x
, 0);
7518 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7519 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7520 return XEXP (cond0
, 0);
7521 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7523 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7524 return XEXP (cond0
, 0);
7530 /* If X is a SUBREG, we can narrow both the true and false values
7531 if the inner expression, if there is a condition. */
7532 else if (code
== SUBREG
7533 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7536 true0
= simplify_gen_subreg (mode
, true0
,
7537 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7538 false0
= simplify_gen_subreg (mode
, false0
,
7539 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7540 if (true0
&& false0
)
7548 /* If X is a constant, this isn't special and will cause confusions
7549 if we treat it as such. Likewise if it is equivalent to a constant. */
7550 else if (CONSTANT_P (x
)
7551 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7554 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7555 will be least confusing to the rest of the compiler. */
7556 else if (mode
== BImode
)
7558 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7562 /* If X is known to be either 0 or -1, those are the true and
7563 false values when testing X. */
7564 else if (x
== constm1_rtx
|| x
== const0_rtx
7565 || (mode
!= VOIDmode
7566 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7568 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7572 /* Likewise for 0 or a single bit. */
7573 else if (SCALAR_INT_MODE_P (mode
)
7574 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7575 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7577 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7581 /* Otherwise fail; show no condition with true and false values the same. */
7582 *ptrue
= *pfalse
= x
;
7586 /* Return the value of expression X given the fact that condition COND
7587 is known to be true when applied to REG as its first operand and VAL
7588 as its second. X is known to not be shared and so can be modified in
7591 We only handle the simplest cases, and specifically those cases that
7592 arise with IF_THEN_ELSE expressions. */
7595 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7597 enum rtx_code code
= GET_CODE (x
);
7602 if (side_effects_p (x
))
7605 /* If either operand of the condition is a floating point value,
7606 then we have to avoid collapsing an EQ comparison. */
7608 && rtx_equal_p (x
, reg
)
7609 && ! FLOAT_MODE_P (GET_MODE (x
))
7610 && ! FLOAT_MODE_P (GET_MODE (val
)))
7613 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7616 /* If X is (abs REG) and we know something about REG's relationship
7617 with zero, we may be able to simplify this. */
7619 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7622 case GE
: case GT
: case EQ
:
7625 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7627 GET_MODE (XEXP (x
, 0)));
7632 /* The only other cases we handle are MIN, MAX, and comparisons if the
7633 operands are the same as REG and VAL. */
7635 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
7637 if (rtx_equal_p (XEXP (x
, 0), val
))
7638 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7640 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7642 if (COMPARISON_P (x
))
7644 if (comparison_dominates_p (cond
, code
))
7645 return const_true_rtx
;
7647 code
= combine_reversed_comparison_code (x
);
7649 && comparison_dominates_p (cond
, code
))
7654 else if (code
== SMAX
|| code
== SMIN
7655 || code
== UMIN
|| code
== UMAX
)
7657 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7659 /* Do not reverse the condition when it is NE or EQ.
7660 This is because we cannot conclude anything about
7661 the value of 'SMAX (x, y)' when x is not equal to y,
7662 but we can when x equals y. */
7663 if ((code
== SMAX
|| code
== UMAX
)
7664 && ! (cond
== EQ
|| cond
== NE
))
7665 cond
= reverse_condition (cond
);
7670 return unsignedp
? x
: XEXP (x
, 1);
7672 return unsignedp
? x
: XEXP (x
, 0);
7674 return unsignedp
? XEXP (x
, 1) : x
;
7676 return unsignedp
? XEXP (x
, 0) : x
;
7683 else if (code
== SUBREG
)
7685 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7686 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7688 if (SUBREG_REG (x
) != r
)
7690 /* We must simplify subreg here, before we lose track of the
7691 original inner_mode. */
7692 new = simplify_subreg (GET_MODE (x
), r
,
7693 inner_mode
, SUBREG_BYTE (x
));
7697 SUBST (SUBREG_REG (x
), r
);
7702 /* We don't have to handle SIGN_EXTEND here, because even in the
7703 case of replacing something with a modeless CONST_INT, a
7704 CONST_INT is already (supposed to be) a valid sign extension for
7705 its narrower mode, which implies it's already properly
7706 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7707 story is different. */
7708 else if (code
== ZERO_EXTEND
)
7710 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7711 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7713 if (XEXP (x
, 0) != r
)
7715 /* We must simplify the zero_extend here, before we lose
7716 track of the original inner_mode. */
7717 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7722 SUBST (XEXP (x
, 0), r
);
7728 fmt
= GET_RTX_FORMAT (code
);
7729 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7732 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7733 else if (fmt
[i
] == 'E')
7734 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7735 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7742 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7743 assignment as a field assignment. */
7746 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7748 if (x
== y
|| rtx_equal_p (x
, y
))
7751 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7754 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7755 Note that all SUBREGs of MEM are paradoxical; otherwise they
7756 would have been rewritten. */
7757 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
7758 && MEM_P (SUBREG_REG (y
))
7759 && rtx_equal_p (SUBREG_REG (y
),
7760 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
7763 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
7764 && MEM_P (SUBREG_REG (x
))
7765 && rtx_equal_p (SUBREG_REG (x
),
7766 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
7769 /* We used to see if get_last_value of X and Y were the same but that's
7770 not correct. In one direction, we'll cause the assignment to have
7771 the wrong destination and in the case, we'll import a register into this
7772 insn that might have already have been dead. So fail if none of the
7773 above cases are true. */
7777 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7778 Return that assignment if so.
7780 We only handle the most common cases. */
7783 make_field_assignment (rtx x
)
7785 rtx dest
= SET_DEST (x
);
7786 rtx src
= SET_SRC (x
);
7791 unsigned HOST_WIDE_INT len
;
7793 enum machine_mode mode
;
7795 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7796 a clear of a one-bit field. We will have changed it to
7797 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7800 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7801 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7802 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7803 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7805 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7808 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7812 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7813 && subreg_lowpart_p (XEXP (src
, 0))
7814 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7815 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7816 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7817 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7818 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7819 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7821 assign
= make_extraction (VOIDmode
, dest
, 0,
7822 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7825 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7829 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7831 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7832 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7833 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7835 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7838 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7842 /* The other case we handle is assignments into a constant-position
7843 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7844 a mask that has all one bits except for a group of zero bits and
7845 OTHER is known to have zeros where C1 has ones, this is such an
7846 assignment. Compute the position and length from C1. Shift OTHER
7847 to the appropriate position, force it to the required mode, and
7848 make the extraction. Check for the AND in both operands. */
7850 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7853 rhs
= expand_compound_operation (XEXP (src
, 0));
7854 lhs
= expand_compound_operation (XEXP (src
, 1));
7856 if (GET_CODE (rhs
) == AND
7857 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7858 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7859 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7860 else if (GET_CODE (lhs
) == AND
7861 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7862 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7863 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7867 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7868 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7869 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7870 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7873 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7877 /* The mode to use for the source is the mode of the assignment, or of
7878 what is inside a possible STRICT_LOW_PART. */
7879 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7880 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7882 /* Shift OTHER right POS places and make it the source, restricting it
7883 to the proper length and mode. */
7885 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7886 GET_MODE (src
), other
, pos
),
7888 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7889 ? ~(unsigned HOST_WIDE_INT
) 0
7890 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7893 /* If SRC is masked by an AND that does not make a difference in
7894 the value being stored, strip it. */
7895 if (GET_CODE (assign
) == ZERO_EXTRACT
7896 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7897 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7898 && GET_CODE (src
) == AND
7899 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7900 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7901 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7902 src
= XEXP (src
, 0);
7904 return gen_rtx_SET (VOIDmode
, assign
, src
);
7907 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7911 apply_distributive_law (rtx x
)
7913 enum rtx_code code
= GET_CODE (x
);
7914 enum rtx_code inner_code
;
7915 rtx lhs
, rhs
, other
;
7918 /* Distributivity is not true for floating point as it can change the
7919 value. So we don't do it unless -funsafe-math-optimizations. */
7920 if (FLOAT_MODE_P (GET_MODE (x
))
7921 && ! flag_unsafe_math_optimizations
)
7924 /* The outer operation can only be one of the following: */
7925 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7926 && code
!= PLUS
&& code
!= MINUS
)
7932 /* If either operand is a primitive we can't do anything, so get out
7934 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
7937 lhs
= expand_compound_operation (lhs
);
7938 rhs
= expand_compound_operation (rhs
);
7939 inner_code
= GET_CODE (lhs
);
7940 if (inner_code
!= GET_CODE (rhs
))
7943 /* See if the inner and outer operations distribute. */
7950 /* These all distribute except over PLUS. */
7951 if (code
== PLUS
|| code
== MINUS
)
7956 if (code
!= PLUS
&& code
!= MINUS
)
7961 /* This is also a multiply, so it distributes over everything. */
7965 /* Non-paradoxical SUBREGs distributes over all operations, provided
7966 the inner modes and byte offsets are the same, this is an extraction
7967 of a low-order part, we don't convert an fp operation to int or
7968 vice versa, and we would not be converting a single-word
7969 operation into a multi-word operation. The latter test is not
7970 required, but it prevents generating unneeded multi-word operations.
7971 Some of the previous tests are redundant given the latter test, but
7972 are retained because they are required for correctness.
7974 We produce the result slightly differently in this case. */
7976 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7977 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7978 || ! subreg_lowpart_p (lhs
)
7979 || (GET_MODE_CLASS (GET_MODE (lhs
))
7980 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7981 || (GET_MODE_SIZE (GET_MODE (lhs
))
7982 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7983 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7986 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7987 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7988 return gen_lowpart (GET_MODE (x
), tem
);
7994 /* Set LHS and RHS to the inner operands (A and B in the example
7995 above) and set OTHER to the common operand (C in the example).
7996 There is only one way to do this unless the inner operation is
7998 if (COMMUTATIVE_ARITH_P (lhs
)
7999 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
8000 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
8001 else if (COMMUTATIVE_ARITH_P (lhs
)
8002 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
8003 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
8004 else if (COMMUTATIVE_ARITH_P (lhs
)
8005 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
8006 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
8007 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
8008 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
8012 /* Form the new inner operation, seeing if it simplifies first. */
8013 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
8015 /* There is one exception to the general way of distributing:
8016 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8017 if (code
== XOR
&& inner_code
== IOR
)
8020 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
8023 /* We may be able to continuing distributing the result, so call
8024 ourselves recursively on the inner operation before forming the
8025 outer operation, which we return. */
8026 return gen_binary (inner_code
, GET_MODE (x
),
8027 apply_distributive_law (tem
), other
);
8030 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8033 Return an equivalent form, if different from X. Otherwise, return X. If
8034 X is zero, we are to always construct the equivalent form. */
8037 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
8038 unsigned HOST_WIDE_INT constop
)
8040 unsigned HOST_WIDE_INT nonzero
;
8043 /* Simplify VAROP knowing that we will be only looking at some of the
8046 Note by passing in CONSTOP, we guarantee that the bits not set in
8047 CONSTOP are not significant and will never be examined. We must
8048 ensure that is the case by explicitly masking out those bits
8049 before returning. */
8050 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
8052 /* If VAROP is a CLOBBER, we will fail so return it. */
8053 if (GET_CODE (varop
) == CLOBBER
)
8056 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8057 to VAROP and return the new constant. */
8058 if (GET_CODE (varop
) == CONST_INT
)
8059 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
8061 /* See what bits may be nonzero in VAROP. Unlike the general case of
8062 a call to nonzero_bits, here we don't care about bits outside
8065 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
8067 /* Turn off all bits in the constant that are known to already be zero.
8068 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8069 which is tested below. */
8073 /* If we don't have any bits left, return zero. */
8077 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8078 a power of two, we can replace this with an ASHIFT. */
8079 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
8080 && (i
= exact_log2 (constop
)) >= 0)
8081 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
8083 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8084 or XOR, then try to apply the distributive law. This may eliminate
8085 operations if either branch can be simplified because of the AND.
8086 It may also make some cases more complex, but those cases probably
8087 won't match a pattern either with or without this. */
8089 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
8093 apply_distributive_law
8094 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
8095 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
8096 XEXP (varop
, 0), constop
),
8097 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
8098 XEXP (varop
, 1), constop
))));
8100 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8101 the AND and see if one of the operands simplifies to zero. If so, we
8102 may eliminate it. */
8104 if (GET_CODE (varop
) == PLUS
8105 && exact_log2 (constop
+ 1) >= 0)
8109 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
8110 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
8111 if (o0
== const0_rtx
)
8113 if (o1
== const0_rtx
)
8117 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8118 if we already had one (just check for the simplest cases). */
8119 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
8120 && GET_MODE (XEXP (x
, 0)) == mode
8121 && SUBREG_REG (XEXP (x
, 0)) == varop
)
8122 varop
= XEXP (x
, 0);
8124 varop
= gen_lowpart (mode
, varop
);
8126 /* If we can't make the SUBREG, try to return what we were given. */
8127 if (GET_CODE (varop
) == CLOBBER
)
8128 return x
? x
: varop
;
8130 /* If we are only masking insignificant bits, return VAROP. */
8131 if (constop
== nonzero
)
8135 /* Otherwise, return an AND. */
8136 constop
= trunc_int_for_mode (constop
, mode
);
8137 /* See how much, if any, of X we can use. */
8138 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
8139 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8143 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8144 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8145 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8147 SUBST (XEXP (x
, 0), varop
);
8154 /* Given a REG, X, compute which bits in X can be nonzero.
8155 We don't care about bits outside of those defined in MODE.
8157 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8158 a shift, AND, or zero_extract, we can do better. */
8161 reg_nonzero_bits_for_combine (rtx x
, enum machine_mode mode
,
8162 rtx known_x ATTRIBUTE_UNUSED
,
8163 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
8164 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
8165 unsigned HOST_WIDE_INT
*nonzero
)
8169 /* If X is a register whose nonzero bits value is current, use it.
8170 Otherwise, if X is a register whose value we can find, use that
8171 value. Otherwise, use the previously-computed global nonzero bits
8172 for this register. */
8174 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8175 && (reg_stat
[REGNO (x
)].last_set_mode
== mode
8176 || (GET_MODE_CLASS (reg_stat
[REGNO (x
)].last_set_mode
) == MODE_INT
8177 && GET_MODE_CLASS (mode
) == MODE_INT
))
8178 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8179 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8180 && REG_N_SETS (REGNO (x
)) == 1
8181 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8183 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8185 *nonzero
&= reg_stat
[REGNO (x
)].last_set_nonzero_bits
;
8189 tem
= get_last_value (x
);
8193 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8194 /* If X is narrower than MODE and TEM is a non-negative
8195 constant that would appear negative in the mode of X,
8196 sign-extend it for use in reg_nonzero_bits because some
8197 machines (maybe most) will actually do the sign-extension
8198 and this is the conservative approach.
8200 ??? For 2.5, try to tighten up the MD files in this regard
8201 instead of this kludge. */
8203 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
)
8204 && GET_CODE (tem
) == CONST_INT
8206 && 0 != (INTVAL (tem
)
8207 & ((HOST_WIDE_INT
) 1
8208 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8209 tem
= GEN_INT (INTVAL (tem
)
8210 | ((HOST_WIDE_INT
) (-1)
8211 << GET_MODE_BITSIZE (GET_MODE (x
))));
8215 else if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].nonzero_bits
)
8217 unsigned HOST_WIDE_INT mask
= reg_stat
[REGNO (x
)].nonzero_bits
;
8219 if (GET_MODE_BITSIZE (GET_MODE (x
)) < GET_MODE_BITSIZE (mode
))
8220 /* We don't know anything about the upper bits. */
8221 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8228 /* Return the number of bits at the high-order end of X that are known to
8229 be equal to the sign bit. X will be used in mode MODE; if MODE is
8230 VOIDmode, X will be used in its own mode. The returned value will always
8231 be between 1 and the number of bits in MODE. */
8234 reg_num_sign_bit_copies_for_combine (rtx x
, enum machine_mode mode
,
8235 rtx known_x ATTRIBUTE_UNUSED
,
8236 enum machine_mode known_mode
8238 unsigned int known_ret ATTRIBUTE_UNUSED
,
8239 unsigned int *result
)
8243 if (reg_stat
[REGNO (x
)].last_set_value
!= 0
8244 && reg_stat
[REGNO (x
)].last_set_mode
== mode
8245 && (reg_stat
[REGNO (x
)].last_set_label
== label_tick
8246 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8247 && REG_N_SETS (REGNO (x
)) == 1
8248 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8250 && INSN_CUID (reg_stat
[REGNO (x
)].last_set
) < subst_low_cuid
)
8252 *result
= reg_stat
[REGNO (x
)].last_set_sign_bit_copies
;
8256 tem
= get_last_value (x
);
8260 if (nonzero_sign_valid
&& reg_stat
[REGNO (x
)].sign_bit_copies
!= 0
8261 && GET_MODE_BITSIZE (GET_MODE (x
)) == GET_MODE_BITSIZE (mode
))
8262 *result
= reg_stat
[REGNO (x
)].sign_bit_copies
;
8267 /* Return the number of "extended" bits there are in X, when interpreted
8268 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8269 unsigned quantities, this is the number of high-order zero bits.
8270 For signed quantities, this is the number of copies of the sign bit
8271 minus 1. In both case, this function returns the number of "spare"
8272 bits. For example, if two quantities for which this function returns
8273 at least 1 are added, the addition is known not to overflow.
8275 This function will always return 0 unless called during combine, which
8276 implies that it must be called from a define_split. */
8279 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8281 if (nonzero_sign_valid
== 0)
8285 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8286 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8287 - floor_log2 (nonzero_bits (x
, mode
)))
8289 : num_sign_bit_copies (x
, mode
) - 1);
8292 /* This function is called from `simplify_shift_const' to merge two
8293 outer operations. Specifically, we have already found that we need
8294 to perform operation *POP0 with constant *PCONST0 at the outermost
8295 position. We would now like to also perform OP1 with constant CONST1
8296 (with *POP0 being done last).
8298 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8299 the resulting operation. *PCOMP_P is set to 1 if we would need to
8300 complement the innermost operand, otherwise it is unchanged.
8302 MODE is the mode in which the operation will be done. No bits outside
8303 the width of this mode matter. It is assumed that the width of this mode
8304 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8306 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8307 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8308 result is simply *PCONST0.
8310 If the resulting operation cannot be expressed as one operation, we
8311 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8314 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8316 enum rtx_code op0
= *pop0
;
8317 HOST_WIDE_INT const0
= *pconst0
;
8319 const0
&= GET_MODE_MASK (mode
);
8320 const1
&= GET_MODE_MASK (mode
);
8322 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8326 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8329 if (op1
== UNKNOWN
|| op0
== SET
)
8332 else if (op0
== UNKNOWN
)
8333 op0
= op1
, const0
= const1
;
8335 else if (op0
== op1
)
8359 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8360 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8363 /* If the two constants aren't the same, we can't do anything. The
8364 remaining six cases can all be done. */
8365 else if (const0
!= const1
)
8373 /* (a & b) | b == b */
8375 else /* op1 == XOR */
8376 /* (a ^ b) | b == a | b */
8382 /* (a & b) ^ b == (~a) & b */
8383 op0
= AND
, *pcomp_p
= 1;
8384 else /* op1 == IOR */
8385 /* (a | b) ^ b == a & ~b */
8386 op0
= AND
, const0
= ~const0
;
8391 /* (a | b) & b == b */
8393 else /* op1 == XOR */
8394 /* (a ^ b) & b) == (~a) & b */
8401 /* Check for NO-OP cases. */
8402 const0
&= GET_MODE_MASK (mode
);
8404 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8406 else if (const0
== 0 && op0
== AND
)
8408 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8412 /* ??? Slightly redundant with the above mask, but not entirely.
8413 Moving this above means we'd have to sign-extend the mode mask
8414 for the final test. */
8415 const0
= trunc_int_for_mode (const0
, mode
);
8423 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8424 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8425 that we started with.
8427 The shift is normally computed in the widest mode we find in VAROP, as
8428 long as it isn't a different number of words than RESULT_MODE. Exceptions
8429 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8432 simplify_shift_const (rtx x
, enum rtx_code code
,
8433 enum machine_mode result_mode
, rtx varop
,
8436 enum rtx_code orig_code
= code
;
8439 enum machine_mode mode
= result_mode
;
8440 enum machine_mode shift_mode
, tmode
;
8441 unsigned int mode_words
8442 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8443 /* We form (outer_op (code varop count) (outer_const)). */
8444 enum rtx_code outer_op
= UNKNOWN
;
8445 HOST_WIDE_INT outer_const
= 0;
8447 int complement_p
= 0;
8450 /* Make sure and truncate the "natural" shift on the way in. We don't
8451 want to do this inside the loop as it makes it more difficult to
8453 if (SHIFT_COUNT_TRUNCATED
)
8454 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
8456 /* If we were given an invalid count, don't do anything except exactly
8457 what was requested. */
8459 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
8464 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
8469 /* Unless one of the branches of the `if' in this loop does a `continue',
8470 we will `break' the loop after the `if'. */
8474 /* If we have an operand of (clobber (const_int 0)), just return that
8476 if (GET_CODE (varop
) == CLOBBER
)
8479 /* If we discovered we had to complement VAROP, leave. Making a NOT
8480 here would cause an infinite loop. */
8484 /* Convert ROTATERT to ROTATE. */
8485 if (code
== ROTATERT
)
8487 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
8489 if (VECTOR_MODE_P (result_mode
))
8490 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
8492 count
= bitsize
- count
;
8495 /* We need to determine what mode we will do the shift in. If the
8496 shift is a right shift or a ROTATE, we must always do it in the mode
8497 it was originally done in. Otherwise, we can do it in MODE, the
8498 widest mode encountered. */
8500 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8501 ? result_mode
: mode
);
8503 /* Handle cases where the count is greater than the size of the mode
8504 minus 1. For ASHIFT, use the size minus one as the count (this can
8505 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8506 take the count modulo the size. For other shifts, the result is
8509 Since these shifts are being produced by the compiler by combining
8510 multiple operations, each of which are defined, we know what the
8511 result is supposed to be. */
8513 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
8515 if (code
== ASHIFTRT
)
8516 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8517 else if (code
== ROTATE
|| code
== ROTATERT
)
8518 count
%= GET_MODE_BITSIZE (shift_mode
);
8521 /* We can't simply return zero because there may be an
8529 /* An arithmetic right shift of a quantity known to be -1 or 0
8531 if (code
== ASHIFTRT
8532 && (num_sign_bit_copies (varop
, shift_mode
)
8533 == GET_MODE_BITSIZE (shift_mode
)))
8539 /* If we are doing an arithmetic right shift and discarding all but
8540 the sign bit copies, this is equivalent to doing a shift by the
8541 bitsize minus one. Convert it into that shift because it will often
8542 allow other simplifications. */
8544 if (code
== ASHIFTRT
8545 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8546 >= GET_MODE_BITSIZE (shift_mode
)))
8547 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8549 /* We simplify the tests below and elsewhere by converting
8550 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8551 `make_compound_operation' will convert it to an ASHIFTRT for
8552 those machines (such as VAX) that don't have an LSHIFTRT. */
8553 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8555 && ((nonzero_bits (varop
, shift_mode
)
8556 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8560 if (code
== LSHIFTRT
8561 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8562 && !(nonzero_bits (varop
, shift_mode
) >> count
))
8565 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8566 && !((nonzero_bits (varop
, shift_mode
) << count
)
8567 & GET_MODE_MASK (shift_mode
)))
8570 switch (GET_CODE (varop
))
8576 new = expand_compound_operation (varop
);
8585 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8586 minus the width of a smaller mode, we can do this with a
8587 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8588 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8589 && ! mode_dependent_address_p (XEXP (varop
, 0))
8590 && ! MEM_VOLATILE_P (varop
)
8591 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8592 MODE_INT
, 1)) != BLKmode
)
8594 new = adjust_address_nv (varop
, tmode
,
8595 BYTES_BIG_ENDIAN
? 0
8596 : count
/ BITS_PER_UNIT
);
8598 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8599 : ZERO_EXTEND
, mode
, new);
8606 /* Similar to the case above, except that we can only do this if
8607 the resulting mode is the same as that of the underlying
8608 MEM and adjust the address depending on the *bits* endianness
8609 because of the way that bit-field extract insns are defined. */
8610 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8611 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8612 MODE_INT
, 1)) != BLKmode
8613 && tmode
== GET_MODE (XEXP (varop
, 0)))
8615 if (BITS_BIG_ENDIAN
)
8616 new = XEXP (varop
, 0);
8619 new = copy_rtx (XEXP (varop
, 0));
8620 SUBST (XEXP (new, 0),
8621 plus_constant (XEXP (new, 0),
8622 count
/ BITS_PER_UNIT
));
8625 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
8626 : ZERO_EXTEND
, mode
, new);
8633 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8634 the same number of words as what we've seen so far. Then store
8635 the widest mode in MODE. */
8636 if (subreg_lowpart_p (varop
)
8637 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8638 > GET_MODE_SIZE (GET_MODE (varop
)))
8639 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8640 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
8643 varop
= SUBREG_REG (varop
);
8644 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
8645 mode
= GET_MODE (varop
);
8651 /* Some machines use MULT instead of ASHIFT because MULT
8652 is cheaper. But it is still better on those machines to
8653 merge two shifts into one. */
8654 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8655 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8658 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
8659 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
8665 /* Similar, for when divides are cheaper. */
8666 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8667 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8670 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
8671 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
8677 /* If we are extracting just the sign bit of an arithmetic
8678 right shift, that shift is not needed. However, the sign
8679 bit of a wider mode may be different from what would be
8680 interpreted as the sign bit in a narrower mode, so, if
8681 the result is narrower, don't discard the shift. */
8682 if (code
== LSHIFTRT
8683 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8684 && (GET_MODE_BITSIZE (result_mode
)
8685 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
8687 varop
= XEXP (varop
, 0);
8691 /* ... fall through ... */
8696 /* Here we have two nested shifts. The result is usually the
8697 AND of a new shift with a mask. We compute the result below. */
8698 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8699 && INTVAL (XEXP (varop
, 1)) >= 0
8700 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
8701 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8702 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8704 enum rtx_code first_code
= GET_CODE (varop
);
8705 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
8706 unsigned HOST_WIDE_INT mask
;
8709 /* We have one common special case. We can't do any merging if
8710 the inner code is an ASHIFTRT of a smaller mode. However, if
8711 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8712 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8713 we can convert it to
8714 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8715 This simplifies certain SIGN_EXTEND operations. */
8716 if (code
== ASHIFT
&& first_code
== ASHIFTRT
8717 && count
== (unsigned int)
8718 (GET_MODE_BITSIZE (result_mode
)
8719 - GET_MODE_BITSIZE (GET_MODE (varop
))))
8721 /* C3 has the low-order C1 bits zero. */
8723 mask
= (GET_MODE_MASK (mode
)
8724 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
8726 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
8727 XEXP (varop
, 0), mask
);
8728 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
8730 count
= first_count
;
8735 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8736 than C1 high-order bits equal to the sign bit, we can convert
8737 this to either an ASHIFT or an ASHIFTRT depending on the
8740 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8742 if (code
== ASHIFTRT
&& first_code
== ASHIFT
8743 && GET_MODE (varop
) == shift_mode
8744 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
8747 varop
= XEXP (varop
, 0);
8749 signed_count
= count
- first_count
;
8750 if (signed_count
< 0)
8751 count
= -signed_count
, code
= ASHIFT
;
8753 count
= signed_count
;
8758 /* There are some cases we can't do. If CODE is ASHIFTRT,
8759 we can only do this if FIRST_CODE is also ASHIFTRT.
8761 We can't do the case when CODE is ROTATE and FIRST_CODE is
8764 If the mode of this shift is not the mode of the outer shift,
8765 we can't do this if either shift is a right shift or ROTATE.
8767 Finally, we can't do any of these if the mode is too wide
8768 unless the codes are the same.
8770 Handle the case where the shift codes are the same
8773 if (code
== first_code
)
8775 if (GET_MODE (varop
) != result_mode
8776 && (code
== ASHIFTRT
|| code
== LSHIFTRT
8780 count
+= first_count
;
8781 varop
= XEXP (varop
, 0);
8785 if (code
== ASHIFTRT
8786 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
8787 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
8788 || (GET_MODE (varop
) != result_mode
8789 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
8790 || first_code
== ROTATE
8791 || code
== ROTATE
)))
8794 /* To compute the mask to apply after the shift, shift the
8795 nonzero bits of the inner shift the same way the
8796 outer shift will. */
8798 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
8801 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
8804 /* Give up if we can't compute an outer operation to use. */
8806 || GET_CODE (mask_rtx
) != CONST_INT
8807 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
8809 result_mode
, &complement_p
))
8812 /* If the shifts are in the same direction, we add the
8813 counts. Otherwise, we subtract them. */
8814 signed_count
= count
;
8815 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8816 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
8817 signed_count
+= first_count
;
8819 signed_count
-= first_count
;
8821 /* If COUNT is positive, the new shift is usually CODE,
8822 except for the two exceptions below, in which case it is
8823 FIRST_CODE. If the count is negative, FIRST_CODE should
8825 if (signed_count
> 0
8826 && ((first_code
== ROTATE
&& code
== ASHIFT
)
8827 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
8828 code
= first_code
, count
= signed_count
;
8829 else if (signed_count
< 0)
8830 code
= first_code
, count
= -signed_count
;
8832 count
= signed_count
;
8834 varop
= XEXP (varop
, 0);
8838 /* If we have (A << B << C) for any shift, we can convert this to
8839 (A << C << B). This wins if A is a constant. Only try this if
8840 B is not a constant. */
8842 else if (GET_CODE (varop
) == code
8843 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
8845 = simplify_binary_operation (code
, mode
,
8849 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
8856 /* Make this fit the case below. */
8857 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
8858 GEN_INT (GET_MODE_MASK (mode
)));
8864 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8865 with C the size of VAROP - 1 and the shift is logical if
8866 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8867 we have an (le X 0) operation. If we have an arithmetic shift
8868 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8869 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8871 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
8872 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
8873 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8874 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
8875 && count
== (unsigned int)
8876 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
8877 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
8880 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
8883 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
8884 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
8889 /* If we have (shift (logical)), move the logical to the outside
8890 to allow it to possibly combine with another logical and the
8891 shift to combine with another shift. This also canonicalizes to
8892 what a ZERO_EXTRACT looks like. Also, some machines have
8893 (and (shift)) insns. */
8895 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8896 /* We can't do this if we have (ashiftrt (xor)) and the
8897 constant has its sign bit set in shift_mode. */
8898 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
8899 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
8901 && (new = simplify_binary_operation (code
, result_mode
,
8903 GEN_INT (count
))) != 0
8904 && GET_CODE (new) == CONST_INT
8905 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
8906 INTVAL (new), result_mode
, &complement_p
))
8908 varop
= XEXP (varop
, 0);
8912 /* If we can't do that, try to simplify the shift in each arm of the
8913 logical expression, make a new logical expression, and apply
8914 the inverse distributive law. This also can't be done
8915 for some (ashiftrt (xor)). */
8916 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8917 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
8918 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
8921 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
8922 XEXP (varop
, 0), count
);
8923 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
8924 XEXP (varop
, 1), count
);
8926 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
8927 varop
= apply_distributive_law (varop
);
8935 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8936 says that the sign bit can be tested, FOO has mode MODE, C is
8937 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8938 that may be nonzero. */
8939 if (code
== LSHIFTRT
8940 && XEXP (varop
, 1) == const0_rtx
8941 && GET_MODE (XEXP (varop
, 0)) == result_mode
8942 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8943 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8944 && ((STORE_FLAG_VALUE
8945 & ((HOST_WIDE_INT
) 1
8946 < (GET_MODE_BITSIZE (result_mode
) - 1))))
8947 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
8948 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
8949 (HOST_WIDE_INT
) 1, result_mode
,
8952 varop
= XEXP (varop
, 0);
8959 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8960 than the number of bits in the mode is equivalent to A. */
8961 if (code
== LSHIFTRT
8962 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8963 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
8965 varop
= XEXP (varop
, 0);
8970 /* NEG commutes with ASHIFT since it is multiplication. Move the
8971 NEG outside to allow shifts to combine. */
8973 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
8974 (HOST_WIDE_INT
) 0, result_mode
,
8977 varop
= XEXP (varop
, 0);
8983 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8984 is one less than the number of bits in the mode is
8985 equivalent to (xor A 1). */
8986 if (code
== LSHIFTRT
8987 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
8988 && XEXP (varop
, 1) == constm1_rtx
8989 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
8990 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
8991 (HOST_WIDE_INT
) 1, result_mode
,
8995 varop
= XEXP (varop
, 0);
8999 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9000 that might be nonzero in BAR are those being shifted out and those
9001 bits are known zero in FOO, we can replace the PLUS with FOO.
9002 Similarly in the other operand order. This code occurs when
9003 we are computing the size of a variable-size array. */
9005 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9006 && count
< HOST_BITS_PER_WIDE_INT
9007 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9008 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9009 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9011 varop
= XEXP (varop
, 0);
9014 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9015 && count
< HOST_BITS_PER_WIDE_INT
9016 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9017 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9019 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9020 & nonzero_bits (XEXP (varop
, 1),
9023 varop
= XEXP (varop
, 1);
9027 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9029 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9030 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9032 GEN_INT (count
))) != 0
9033 && GET_CODE (new) == CONST_INT
9034 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9035 INTVAL (new), result_mode
, &complement_p
))
9037 varop
= XEXP (varop
, 0);
9041 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9042 signbit', and attempt to change the PLUS to an XOR and move it to
9043 the outer operation as is done above in the AND/IOR/XOR case
9044 leg for shift(logical). See details in logical handling above
9045 for reasoning in doing so. */
9046 if (code
== LSHIFTRT
9047 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9048 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
9049 && (new = simplify_binary_operation (code
, result_mode
,
9051 GEN_INT (count
))) != 0
9052 && GET_CODE (new) == CONST_INT
9053 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9054 INTVAL (new), result_mode
, &complement_p
))
9056 varop
= XEXP (varop
, 0);
9063 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9064 with C the size of VAROP - 1 and the shift is logical if
9065 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9066 we have a (gt X 0) operation. If the shift is arithmetic with
9067 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9068 we have a (neg (gt X 0)) operation. */
9070 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9071 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9072 && count
== (unsigned int)
9073 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9074 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9075 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9076 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9078 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9081 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9084 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9085 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9092 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9093 if the truncate does not affect the value. */
9094 if (code
== LSHIFTRT
9095 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9096 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9097 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9098 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9099 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9101 rtx varop_inner
= XEXP (varop
, 0);
9104 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9105 XEXP (varop_inner
, 0),
9107 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9108 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9121 /* We need to determine what mode to do the shift in. If the shift is
9122 a right shift or ROTATE, we must always do it in the mode it was
9123 originally done in. Otherwise, we can do it in MODE, the widest mode
9124 encountered. The code we care about is that of the shift that will
9125 actually be done, not the shift that was originally requested. */
9127 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9128 ? result_mode
: mode
);
9130 /* We have now finished analyzing the shift. The result should be
9131 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9132 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9133 to the result of the shift. OUTER_CONST is the relevant constant,
9134 but we must turn off all bits turned off in the shift.
9136 If we were passed a value for X, see if we can use any pieces of
9137 it. If not, make new rtx. */
9139 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == RTX_BIN_ARITH
9140 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9141 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9142 const_rtx
= XEXP (x
, 1);
9144 const_rtx
= GEN_INT (count
);
9146 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9147 && GET_MODE (XEXP (x
, 0)) == shift_mode
9148 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9149 varop
= XEXP (x
, 0);
9150 else if (GET_MODE (varop
) != shift_mode
)
9151 varop
= gen_lowpart (shift_mode
, varop
);
9153 /* If we can't make the SUBREG, try to return what we were given. */
9154 if (GET_CODE (varop
) == CLOBBER
)
9155 return x
? x
: varop
;
9157 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9161 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9163 /* If we have an outer operation and we just made a shift, it is
9164 possible that we could have simplified the shift were it not
9165 for the outer operation. So try to do the simplification
9168 if (outer_op
!= UNKNOWN
&& GET_CODE (x
) == code
9169 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9170 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9171 INTVAL (XEXP (x
, 1)));
9173 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9174 turn off all the bits that the shift would have turned off. */
9175 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9176 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9177 GET_MODE_MASK (result_mode
) >> orig_count
);
9179 /* Do the remainder of the processing in RESULT_MODE. */
9180 x
= gen_lowpart (result_mode
, x
);
9182 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9185 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9187 if (outer_op
!= UNKNOWN
)
9189 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9190 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9192 if (outer_op
== AND
)
9193 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9194 else if (outer_op
== SET
)
9195 /* This means that we have determined that the result is
9196 equivalent to a constant. This should be rare. */
9197 x
= GEN_INT (outer_const
);
9198 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
9199 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9201 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9207 /* Like recog, but we receive the address of a pointer to a new pattern.
9208 We try to match the rtx that the pointer points to.
9209 If that fails, we may try to modify or replace the pattern,
9210 storing the replacement into the same pointer object.
9212 Modifications include deletion or addition of CLOBBERs.
9214 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9215 the CLOBBERs are placed.
9217 The value is the final insn code from the pattern ultimately matched,
9221 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9224 int insn_code_number
;
9225 int num_clobbers_to_add
= 0;
9228 rtx old_notes
, old_pat
;
9230 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9231 we use to indicate that something didn't match. If we find such a
9232 thing, force rejection. */
9233 if (GET_CODE (pat
) == PARALLEL
)
9234 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9235 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9236 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9239 old_pat
= PATTERN (insn
);
9240 old_notes
= REG_NOTES (insn
);
9241 PATTERN (insn
) = pat
;
9242 REG_NOTES (insn
) = 0;
9244 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9246 /* If it isn't, there is the possibility that we previously had an insn
9247 that clobbered some register as a side effect, but the combined
9248 insn doesn't need to do that. So try once more without the clobbers
9249 unless this represents an ASM insn. */
9251 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9252 && GET_CODE (pat
) == PARALLEL
)
9256 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9257 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9260 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9264 SUBST_INT (XVECLEN (pat
, 0), pos
);
9267 pat
= XVECEXP (pat
, 0, 0);
9269 PATTERN (insn
) = pat
;
9270 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9272 PATTERN (insn
) = old_pat
;
9273 REG_NOTES (insn
) = old_notes
;
9275 /* Recognize all noop sets, these will be killed by followup pass. */
9276 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9277 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9279 /* If we had any clobbers to add, make a new pattern than contains
9280 them. Then check to make sure that all of them are dead. */
9281 if (num_clobbers_to_add
)
9283 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9284 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9286 + num_clobbers_to_add
)
9287 : num_clobbers_to_add
+ 1));
9289 if (GET_CODE (pat
) == PARALLEL
)
9290 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9291 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9293 XVECEXP (newpat
, 0, 0) = pat
;
9295 add_clobbers (newpat
, insn_code_number
);
9297 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9298 i
< XVECLEN (newpat
, 0); i
++)
9300 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
9301 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9303 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9304 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9312 return insn_code_number
;
9315 /* Like gen_lowpart_general but for use by combine. In combine it
9316 is not possible to create any new pseudoregs. However, it is
9317 safe to create invalid memory addresses, because combine will
9318 try to recognize them and all they will do is make the combine
9321 If for some reason this cannot do its job, an rtx
9322 (clobber (const_int 0)) is returned.
9323 An insn containing that will not be recognized. */
9326 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
9328 enum machine_mode imode
= GET_MODE (x
);
9329 unsigned int osize
= GET_MODE_SIZE (omode
);
9330 unsigned int isize
= GET_MODE_SIZE (imode
);
9336 /* Return identity if this is a CONST or symbolic reference. */
9338 && (GET_CODE (x
) == CONST
9339 || GET_CODE (x
) == SYMBOL_REF
9340 || GET_CODE (x
) == LABEL_REF
))
9343 /* We can only support MODE being wider than a word if X is a
9344 constant integer or has a mode the same size. */
9345 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
9346 && ! ((imode
== VOIDmode
9347 && (GET_CODE (x
) == CONST_INT
9348 || GET_CODE (x
) == CONST_DOUBLE
))
9352 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9353 won't know what to do. So we will strip off the SUBREG here and
9354 process normally. */
9355 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
9359 /* For use in case we fall down into the address adjustments
9360 further below, we need to adjust the known mode and size of
9361 x; imode and isize, since we just adjusted x. */
9362 imode
= GET_MODE (x
);
9367 isize
= GET_MODE_SIZE (imode
);
9370 result
= gen_lowpart_common (omode
, x
);
9372 #ifdef CANNOT_CHANGE_MODE_CLASS
9373 if (result
!= 0 && GET_CODE (result
) == SUBREG
)
9374 record_subregs_of_mode (result
);
9384 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9386 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9389 /* If we want to refer to something bigger than the original memref,
9390 generate a paradoxical subreg instead. That will force a reload
9391 of the original memref X. */
9393 return gen_rtx_SUBREG (omode
, x
, 0);
9395 if (WORDS_BIG_ENDIAN
)
9396 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
9398 /* Adjust the address so that the address-after-the-data is unchanged. */
9399 if (BYTES_BIG_ENDIAN
)
9400 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
9402 return adjust_address_nv (x
, omode
, offset
);
9405 /* If X is a comparison operator, rewrite it in a new mode. This
9406 probably won't match, but may allow further simplifications. */
9407 else if (COMPARISON_P (x
))
9408 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
9410 /* If we couldn't simplify X any other way, just enclose it in a
9411 SUBREG. Normally, this SUBREG won't match, but some patterns may
9412 include an explicit SUBREG or we may simplify it further in combine. */
9418 offset
= subreg_lowpart_offset (omode
, imode
);
9419 if (imode
== VOIDmode
)
9421 imode
= int_mode_for_mode (omode
);
9422 x
= gen_lowpart_common (imode
, x
);
9426 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
9432 return gen_rtx_CLOBBER (imode
, const0_rtx
);
9435 /* These routines make binary and unary operations by first seeing if they
9436 fold; if not, a new expression is allocated. */
9439 gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
, rtx op1
)
9444 if (GET_CODE (op0
) == CLOBBER
)
9446 else if (GET_CODE (op1
) == CLOBBER
)
9449 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
9450 && swap_commutative_operands_p (op0
, op1
))
9451 tem
= op0
, op0
= op1
, op1
= tem
;
9453 if (GET_RTX_CLASS (code
) == RTX_COMPARE
9454 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
9456 enum machine_mode op_mode
= GET_MODE (op0
);
9458 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9459 just (REL_OP X Y). */
9460 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
9462 op1
= XEXP (op0
, 1);
9463 op0
= XEXP (op0
, 0);
9464 op_mode
= GET_MODE (op0
);
9467 if (op_mode
== VOIDmode
)
9468 op_mode
= GET_MODE (op1
);
9469 result
= simplify_relational_operation (code
, mode
, op_mode
, op0
, op1
);
9472 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
9477 /* Put complex operands first and constants second. */
9478 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
9479 && swap_commutative_operands_p (op0
, op1
))
9480 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
9482 /* If we are turning off bits already known off in OP0, we need not do
9484 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
9485 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9486 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
9489 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
9492 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9493 comparison code that will be tested.
9495 The result is a possibly different comparison code to use. *POP0 and
9496 *POP1 may be updated.
9498 It is possible that we might detect that a comparison is either always
9499 true or always false. However, we do not perform general constant
9500 folding in combine, so this knowledge isn't useful. Such tautologies
9501 should have been detected earlier. Hence we ignore all such cases. */
9503 static enum rtx_code
9504 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
9510 enum machine_mode mode
, tmode
;
9512 /* Try a few ways of applying the same transformation to both operands. */
9515 #ifndef WORD_REGISTER_OPERATIONS
9516 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9517 so check specially. */
9518 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9519 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9520 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9521 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9522 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9523 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9524 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9525 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9526 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9527 && XEXP (op0
, 1) == XEXP (op1
, 1)
9528 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
9529 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
9530 && (INTVAL (XEXP (op0
, 1))
9531 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9533 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9535 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9536 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9540 /* If both operands are the same constant shift, see if we can ignore the
9541 shift. We can if the shift is a rotate or if the bits shifted out of
9542 this shift are known to be zero for both inputs and if the type of
9543 comparison is compatible with the shift. */
9544 if (GET_CODE (op0
) == GET_CODE (op1
)
9545 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9546 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9547 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9548 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9549 || (GET_CODE (op0
) == ASHIFTRT
9550 && (code
!= GTU
&& code
!= LTU
9551 && code
!= GEU
&& code
!= LEU
)))
9552 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9553 && INTVAL (XEXP (op0
, 1)) >= 0
9554 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9555 && XEXP (op0
, 1) == XEXP (op1
, 1))
9557 enum machine_mode mode
= GET_MODE (op0
);
9558 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9559 int shift_count
= INTVAL (XEXP (op0
, 1));
9561 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9562 mask
&= (mask
>> shift_count
) << shift_count
;
9563 else if (GET_CODE (op0
) == ASHIFT
)
9564 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9566 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
9567 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
9568 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9573 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9574 SUBREGs are of the same mode, and, in both cases, the AND would
9575 be redundant if the comparison was done in the narrower mode,
9576 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9577 and the operand's possibly nonzero bits are 0xffffff01; in that case
9578 if we only care about QImode, we don't need the AND). This case
9579 occurs if the output mode of an scc insn is not SImode and
9580 STORE_FLAG_VALUE == 1 (e.g., the 386).
9582 Similarly, check for a case where the AND's are ZERO_EXTEND
9583 operations from some narrower mode even though a SUBREG is not
9586 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9587 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9588 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9590 rtx inner_op0
= XEXP (op0
, 0);
9591 rtx inner_op1
= XEXP (op1
, 0);
9592 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9593 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9596 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9597 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9598 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9599 && (GET_MODE (SUBREG_REG (inner_op0
))
9600 == GET_MODE (SUBREG_REG (inner_op1
)))
9601 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9602 <= HOST_BITS_PER_WIDE_INT
)
9603 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9604 GET_MODE (SUBREG_REG (inner_op0
)))))
9605 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9606 GET_MODE (SUBREG_REG (inner_op1
))))))
9608 op0
= SUBREG_REG (inner_op0
);
9609 op1
= SUBREG_REG (inner_op1
);
9611 /* The resulting comparison is always unsigned since we masked
9612 off the original sign bit. */
9613 code
= unsigned_condition (code
);
9619 for (tmode
= GET_CLASS_NARROWEST_MODE
9620 (GET_MODE_CLASS (GET_MODE (op0
)));
9621 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9622 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9624 op0
= gen_lowpart (tmode
, inner_op0
);
9625 op1
= gen_lowpart (tmode
, inner_op1
);
9626 code
= unsigned_condition (code
);
9635 /* If both operands are NOT, we can strip off the outer operation
9636 and adjust the comparison code for swapped operands; similarly for
9637 NEG, except that this must be an equality comparison. */
9638 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9639 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9640 && (code
== EQ
|| code
== NE
)))
9641 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9647 /* If the first operand is a constant, swap the operands and adjust the
9648 comparison code appropriately, but don't do this if the second operand
9649 is already a constant integer. */
9650 if (swap_commutative_operands_p (op0
, op1
))
9652 tem
= op0
, op0
= op1
, op1
= tem
;
9653 code
= swap_condition (code
);
9656 /* We now enter a loop during which we will try to simplify the comparison.
9657 For the most part, we only are concerned with comparisons with zero,
9658 but some things may really be comparisons with zero but not start
9659 out looking that way. */
9661 while (GET_CODE (op1
) == CONST_INT
)
9663 enum machine_mode mode
= GET_MODE (op0
);
9664 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
9665 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9666 int equality_comparison_p
;
9667 int sign_bit_comparison_p
;
9668 int unsigned_comparison_p
;
9669 HOST_WIDE_INT const_op
;
9671 /* We only want to handle integral modes. This catches VOIDmode,
9672 CCmode, and the floating-point modes. An exception is that we
9673 can handle VOIDmode if OP0 is a COMPARE or a comparison
9676 if (GET_MODE_CLASS (mode
) != MODE_INT
9677 && ! (mode
== VOIDmode
9678 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
9681 /* Get the constant we are comparing against and turn off all bits
9682 not on in our mode. */
9683 const_op
= INTVAL (op1
);
9684 if (mode
!= VOIDmode
)
9685 const_op
= trunc_int_for_mode (const_op
, mode
);
9686 op1
= GEN_INT (const_op
);
9688 /* If we are comparing against a constant power of two and the value
9689 being compared can only have that single bit nonzero (e.g., it was
9690 `and'ed with that bit), we can replace this with a comparison
9693 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
9694 || code
== LT
|| code
== LTU
)
9695 && mode_width
<= HOST_BITS_PER_WIDE_INT
9696 && exact_log2 (const_op
) >= 0
9697 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
9699 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
9700 op1
= const0_rtx
, const_op
= 0;
9703 /* Similarly, if we are comparing a value known to be either -1 or
9704 0 with -1, change it to the opposite comparison against zero. */
9707 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
9708 || code
== GEU
|| code
== LTU
)
9709 && num_sign_bit_copies (op0
, mode
) == mode_width
)
9711 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
9712 op1
= const0_rtx
, const_op
= 0;
9715 /* Do some canonicalizations based on the comparison code. We prefer
9716 comparisons against zero and then prefer equality comparisons.
9717 If we can reduce the size of a constant, we will do that too. */
9722 /* < C is equivalent to <= (C - 1) */
9726 op1
= GEN_INT (const_op
);
9728 /* ... fall through to LE case below. */
9734 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9738 op1
= GEN_INT (const_op
);
9742 /* If we are doing a <= 0 comparison on a value known to have
9743 a zero sign bit, we can replace this with == 0. */
9744 else if (const_op
== 0
9745 && mode_width
<= HOST_BITS_PER_WIDE_INT
9746 && (nonzero_bits (op0
, mode
)
9747 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9752 /* >= C is equivalent to > (C - 1). */
9756 op1
= GEN_INT (const_op
);
9758 /* ... fall through to GT below. */
9764 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9768 op1
= GEN_INT (const_op
);
9772 /* If we are doing a > 0 comparison on a value known to have
9773 a zero sign bit, we can replace this with != 0. */
9774 else if (const_op
== 0
9775 && mode_width
<= HOST_BITS_PER_WIDE_INT
9776 && (nonzero_bits (op0
, mode
)
9777 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
9782 /* < C is equivalent to <= (C - 1). */
9786 op1
= GEN_INT (const_op
);
9788 /* ... fall through ... */
9791 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9792 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9793 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9795 const_op
= 0, op1
= const0_rtx
;
9803 /* unsigned <= 0 is equivalent to == 0 */
9807 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9808 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9809 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9811 const_op
= 0, op1
= const0_rtx
;
9817 /* >= C is equivalent to > (C - 1). */
9821 op1
= GEN_INT (const_op
);
9823 /* ... fall through ... */
9826 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9827 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9828 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
9830 const_op
= 0, op1
= const0_rtx
;
9838 /* unsigned > 0 is equivalent to != 0 */
9842 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9843 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
9844 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
9846 const_op
= 0, op1
= const0_rtx
;
9855 /* Compute some predicates to simplify code below. */
9857 equality_comparison_p
= (code
== EQ
|| code
== NE
);
9858 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
9859 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
9862 /* If this is a sign bit comparison and we can do arithmetic in
9863 MODE, say that we will only be needing the sign bit of OP0. */
9864 if (sign_bit_comparison_p
9865 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9866 op0
= force_to_mode (op0
, mode
,
9868 << (GET_MODE_BITSIZE (mode
) - 1)),
9871 /* Now try cases based on the opcode of OP0. If none of the cases
9872 does a "continue", we exit this loop immediately after the
9875 switch (GET_CODE (op0
))
9878 /* If we are extracting a single bit from a variable position in
9879 a constant that has only a single bit set and are comparing it
9880 with zero, we can convert this into an equality comparison
9881 between the position and the location of the single bit. */
9882 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9883 have already reduced the shift count modulo the word size. */
9884 if (!SHIFT_COUNT_TRUNCATED
9885 && GET_CODE (XEXP (op0
, 0)) == CONST_INT
9886 && XEXP (op0
, 1) == const1_rtx
9887 && equality_comparison_p
&& const_op
== 0
9888 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
9890 if (BITS_BIG_ENDIAN
)
9892 enum machine_mode new_mode
9893 = mode_for_extraction (EP_extzv
, 1);
9894 if (new_mode
== MAX_MACHINE_MODE
)
9895 i
= BITS_PER_WORD
- 1 - i
;
9899 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
9903 op0
= XEXP (op0
, 2);
9907 /* Result is nonzero iff shift count is equal to I. */
9908 code
= reverse_condition (code
);
9912 /* ... fall through ... */
9915 tem
= expand_compound_operation (op0
);
9924 /* If testing for equality, we can take the NOT of the constant. */
9925 if (equality_comparison_p
9926 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
9928 op0
= XEXP (op0
, 0);
9933 /* If just looking at the sign bit, reverse the sense of the
9935 if (sign_bit_comparison_p
)
9937 op0
= XEXP (op0
, 0);
9938 code
= (code
== GE
? LT
: GE
);
9944 /* If testing for equality, we can take the NEG of the constant. */
9945 if (equality_comparison_p
9946 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
9948 op0
= XEXP (op0
, 0);
9953 /* The remaining cases only apply to comparisons with zero. */
9957 /* When X is ABS or is known positive,
9958 (neg X) is < 0 if and only if X != 0. */
9960 if (sign_bit_comparison_p
9961 && (GET_CODE (XEXP (op0
, 0)) == ABS
9962 || (mode_width
<= HOST_BITS_PER_WIDE_INT
9963 && (nonzero_bits (XEXP (op0
, 0), mode
)
9964 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
9966 op0
= XEXP (op0
, 0);
9967 code
= (code
== LT
? NE
: EQ
);
9971 /* If we have NEG of something whose two high-order bits are the
9972 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9973 if (num_sign_bit_copies (op0
, mode
) >= 2)
9975 op0
= XEXP (op0
, 0);
9976 code
= swap_condition (code
);
9982 /* If we are testing equality and our count is a constant, we
9983 can perform the inverse operation on our RHS. */
9984 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
9985 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
9986 op1
, XEXP (op0
, 1))) != 0)
9988 op0
= XEXP (op0
, 0);
9993 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9994 a particular bit. Convert it to an AND of a constant of that
9995 bit. This will be converted into a ZERO_EXTRACT. */
9996 if (const_op
== 0 && sign_bit_comparison_p
9997 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9998 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10000 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10003 - INTVAL (XEXP (op0
, 1)))));
10004 code
= (code
== LT
? NE
: EQ
);
10008 /* Fall through. */
10011 /* ABS is ignorable inside an equality comparison with zero. */
10012 if (const_op
== 0 && equality_comparison_p
)
10014 op0
= XEXP (op0
, 0);
10020 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10021 to (compare FOO CONST) if CONST fits in FOO's mode and we
10022 are either testing inequality or have an unsigned comparison
10023 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10024 if (! unsigned_comparison_p
10025 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10026 <= HOST_BITS_PER_WIDE_INT
)
10027 && ((unsigned HOST_WIDE_INT
) const_op
10028 < (((unsigned HOST_WIDE_INT
) 1
10029 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10031 op0
= XEXP (op0
, 0);
10037 /* Check for the case where we are comparing A - C1 with C2,
10038 both constants are smaller than 1/2 the maximum positive
10039 value in MODE, and the comparison is equality or unsigned.
10040 In that case, if A is either zero-extended to MODE or has
10041 sufficient sign bits so that the high-order bit in MODE
10042 is a copy of the sign in the inner mode, we can prove that it is
10043 safe to do the operation in the wider mode. This simplifies
10044 many range checks. */
10046 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10047 && subreg_lowpart_p (op0
)
10048 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10049 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10050 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10051 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10052 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10053 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10054 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10055 GET_MODE (SUBREG_REG (op0
)))
10056 & ~GET_MODE_MASK (mode
))
10057 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10058 GET_MODE (SUBREG_REG (op0
)))
10060 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10061 - GET_MODE_BITSIZE (mode
)))))
10063 op0
= SUBREG_REG (op0
);
10067 /* If the inner mode is narrower and we are extracting the low part,
10068 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10069 if (subreg_lowpart_p (op0
)
10070 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10071 /* Fall through */ ;
10075 /* ... fall through ... */
10078 if ((unsigned_comparison_p
|| equality_comparison_p
)
10079 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10080 <= HOST_BITS_PER_WIDE_INT
)
10081 && ((unsigned HOST_WIDE_INT
) const_op
10082 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10084 op0
= XEXP (op0
, 0);
10090 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10091 this for equality comparisons due to pathological cases involving
10093 if (equality_comparison_p
10094 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10095 op1
, XEXP (op0
, 1))))
10097 op0
= XEXP (op0
, 0);
10102 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10103 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10104 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10106 op0
= XEXP (XEXP (op0
, 0), 0);
10107 code
= (code
== LT
? EQ
: NE
);
10113 /* We used to optimize signed comparisons against zero, but that
10114 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10115 arrive here as equality comparisons, or (GEU, LTU) are
10116 optimized away. No need to special-case them. */
10118 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10119 (eq B (minus A C)), whichever simplifies. We can only do
10120 this for equality comparisons due to pathological cases involving
10122 if (equality_comparison_p
10123 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10124 XEXP (op0
, 1), op1
)))
10126 op0
= XEXP (op0
, 0);
10131 if (equality_comparison_p
10132 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10133 XEXP (op0
, 0), op1
)))
10135 op0
= XEXP (op0
, 1);
10140 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10141 of bits in X minus 1, is one iff X > 0. */
10142 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10143 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10144 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10146 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10148 op0
= XEXP (op0
, 1);
10149 code
= (code
== GE
? LE
: GT
);
10155 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10156 if C is zero or B is a constant. */
10157 if (equality_comparison_p
10158 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10159 XEXP (op0
, 1), op1
)))
10161 op0
= XEXP (op0
, 0);
10168 case UNEQ
: case LTGT
:
10169 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10170 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10171 case UNORDERED
: case ORDERED
:
10172 /* We can't do anything if OP0 is a condition code value, rather
10173 than an actual data value. */
10175 || CC0_P (XEXP (op0
, 0))
10176 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10179 /* Get the two operands being compared. */
10180 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10181 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10183 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10185 /* Check for the cases where we simply want the result of the
10186 earlier test or the opposite of that result. */
10187 if (code
== NE
|| code
== EQ
10188 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10189 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10190 && (STORE_FLAG_VALUE
10191 & (((HOST_WIDE_INT
) 1
10192 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10193 && (code
== LT
|| code
== GE
)))
10195 enum rtx_code new_code
;
10196 if (code
== LT
|| code
== NE
)
10197 new_code
= GET_CODE (op0
);
10199 new_code
= combine_reversed_comparison_code (op0
);
10201 if (new_code
!= UNKNOWN
)
10212 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10214 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10215 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10216 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10218 op0
= XEXP (op0
, 1);
10219 code
= (code
== GE
? GT
: LE
);
10225 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10226 will be converted to a ZERO_EXTRACT later. */
10227 if (const_op
== 0 && equality_comparison_p
10228 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10229 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10231 op0
= simplify_and_const_int
10232 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10234 XEXP (XEXP (op0
, 0), 1)),
10235 (HOST_WIDE_INT
) 1);
10239 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10240 zero and X is a comparison and C1 and C2 describe only bits set
10241 in STORE_FLAG_VALUE, we can compare with X. */
10242 if (const_op
== 0 && equality_comparison_p
10243 && mode_width
<= HOST_BITS_PER_WIDE_INT
10244 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10245 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10246 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10247 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10248 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10250 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10251 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10252 if ((~STORE_FLAG_VALUE
& mask
) == 0
10253 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
10254 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10255 && COMPARISON_P (tem
))))
10257 op0
= XEXP (XEXP (op0
, 0), 0);
10262 /* If we are doing an equality comparison of an AND of a bit equal
10263 to the sign bit, replace this with a LT or GE comparison of
10264 the underlying value. */
10265 if (equality_comparison_p
10267 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10268 && mode_width
<= HOST_BITS_PER_WIDE_INT
10269 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10270 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10272 op0
= XEXP (op0
, 0);
10273 code
= (code
== EQ
? GE
: LT
);
10277 /* If this AND operation is really a ZERO_EXTEND from a narrower
10278 mode, the constant fits within that mode, and this is either an
10279 equality or unsigned comparison, try to do this comparison in
10280 the narrower mode. */
10281 if ((equality_comparison_p
|| unsigned_comparison_p
)
10282 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10283 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10284 & GET_MODE_MASK (mode
))
10286 && const_op
>> i
== 0
10287 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10289 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
10293 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10294 fits in both M1 and M2 and the SUBREG is either paradoxical
10295 or represents the low part, permute the SUBREG and the AND
10297 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10299 unsigned HOST_WIDE_INT c1
;
10300 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10301 /* Require an integral mode, to avoid creating something like
10303 if (SCALAR_INT_MODE_P (tmode
)
10304 /* It is unsafe to commute the AND into the SUBREG if the
10305 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10306 not defined. As originally written the upper bits
10307 have a defined value due to the AND operation.
10308 However, if we commute the AND inside the SUBREG then
10309 they no longer have defined values and the meaning of
10310 the code has been changed. */
10312 #ifdef WORD_REGISTER_OPERATIONS
10313 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10314 && mode_width
<= BITS_PER_WORD
)
10316 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10317 && subreg_lowpart_p (XEXP (op0
, 0))))
10318 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10319 && mode_width
<= HOST_BITS_PER_WIDE_INT
10320 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10321 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10322 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10324 && c1
!= GET_MODE_MASK (tmode
))
10326 op0
= gen_binary (AND
, tmode
,
10327 SUBREG_REG (XEXP (op0
, 0)),
10328 gen_int_mode (c1
, tmode
));
10329 op0
= gen_lowpart (mode
, op0
);
10334 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10335 if (const_op
== 0 && equality_comparison_p
10336 && XEXP (op0
, 1) == const1_rtx
10337 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10339 op0
= simplify_and_const_int
10340 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10341 code
= (code
== NE
? EQ
: NE
);
10345 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10346 (eq (and (lshiftrt X) 1) 0).
10347 Also handle the case where (not X) is expressed using xor. */
10348 if (const_op
== 0 && equality_comparison_p
10349 && XEXP (op0
, 1) == const1_rtx
10350 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
10352 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
10353 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
10355 if (GET_CODE (shift_op
) == NOT
10356 || (GET_CODE (shift_op
) == XOR
10357 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
10358 && GET_CODE (shift_count
) == CONST_INT
10359 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10360 && (INTVAL (XEXP (shift_op
, 1))
10361 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
10363 op0
= simplify_and_const_int
10365 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
10366 (HOST_WIDE_INT
) 1);
10367 code
= (code
== NE
? EQ
: NE
);
10374 /* If we have (compare (ashift FOO N) (const_int C)) and
10375 the high order N bits of FOO (N+1 if an inequality comparison)
10376 are known to be zero, we can do this by comparing FOO with C
10377 shifted right N bits so long as the low-order N bits of C are
10379 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10380 && INTVAL (XEXP (op0
, 1)) >= 0
10381 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10382 < HOST_BITS_PER_WIDE_INT
)
10384 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10385 && mode_width
<= HOST_BITS_PER_WIDE_INT
10386 && (nonzero_bits (XEXP (op0
, 0), mode
)
10387 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10388 + ! equality_comparison_p
))) == 0)
10390 /* We must perform a logical shift, not an arithmetic one,
10391 as we want the top N bits of C to be zero. */
10392 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10394 temp
>>= INTVAL (XEXP (op0
, 1));
10395 op1
= gen_int_mode (temp
, mode
);
10396 op0
= XEXP (op0
, 0);
10400 /* If we are doing a sign bit comparison, it means we are testing
10401 a particular bit. Convert it to the appropriate AND. */
10402 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10403 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10405 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10408 - INTVAL (XEXP (op0
, 1)))));
10409 code
= (code
== LT
? NE
: EQ
);
10413 /* If this an equality comparison with zero and we are shifting
10414 the low bit to the sign bit, we can convert this to an AND of the
10416 if (const_op
== 0 && equality_comparison_p
10417 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10418 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10421 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10422 (HOST_WIDE_INT
) 1);
10428 /* If this is an equality comparison with zero, we can do this
10429 as a logical shift, which might be much simpler. */
10430 if (equality_comparison_p
&& const_op
== 0
10431 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10433 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10435 INTVAL (XEXP (op0
, 1)));
10439 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10440 do the comparison in a narrower mode. */
10441 if (! unsigned_comparison_p
10442 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10443 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10444 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10445 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10446 MODE_INT
, 1)) != BLKmode
10447 && (((unsigned HOST_WIDE_INT
) const_op
10448 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10449 <= GET_MODE_MASK (tmode
)))
10451 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
10455 /* Likewise if OP0 is a PLUS of a sign extension with a
10456 constant, which is usually represented with the PLUS
10457 between the shifts. */
10458 if (! unsigned_comparison_p
10459 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10460 && GET_CODE (XEXP (op0
, 0)) == PLUS
10461 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10462 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10463 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10464 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10465 MODE_INT
, 1)) != BLKmode
10466 && (((unsigned HOST_WIDE_INT
) const_op
10467 + (GET_MODE_MASK (tmode
) >> 1) + 1)
10468 <= GET_MODE_MASK (tmode
)))
10470 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10471 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10472 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
10475 op0
= gen_binary (PLUS
, tmode
,
10476 gen_lowpart (tmode
, inner
),
10481 /* ... fall through ... */
10483 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10484 the low order N bits of FOO are known to be zero, we can do this
10485 by comparing FOO with C shifted left N bits so long as no
10486 overflow occurs. */
10487 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10488 && INTVAL (XEXP (op0
, 1)) >= 0
10489 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10490 && mode_width
<= HOST_BITS_PER_WIDE_INT
10491 && (nonzero_bits (XEXP (op0
, 0), mode
)
10492 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10493 && (((unsigned HOST_WIDE_INT
) const_op
10494 + (GET_CODE (op0
) != LSHIFTRT
10495 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
10498 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
10500 /* If the shift was logical, then we must make the condition
10502 if (GET_CODE (op0
) == LSHIFTRT
)
10503 code
= unsigned_condition (code
);
10505 const_op
<<= INTVAL (XEXP (op0
, 1));
10506 op1
= GEN_INT (const_op
);
10507 op0
= XEXP (op0
, 0);
10511 /* If we are using this shift to extract just the sign bit, we
10512 can replace this with an LT or GE comparison. */
10514 && (equality_comparison_p
|| sign_bit_comparison_p
)
10515 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10516 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10519 op0
= XEXP (op0
, 0);
10520 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10532 /* Now make any compound operations involved in this comparison. Then,
10533 check for an outmost SUBREG on OP0 that is not doing anything or is
10534 paradoxical. The latter transformation must only be performed when
10535 it is known that the "extra" bits will be the same in op0 and op1 or
10536 that they don't matter. There are three cases to consider:
10538 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10539 care bits and we can assume they have any convenient value. So
10540 making the transformation is safe.
10542 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10543 In this case the upper bits of op0 are undefined. We should not make
10544 the simplification in that case as we do not know the contents of
10547 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10548 UNKNOWN. In that case we know those bits are zeros or ones. We must
10549 also be sure that they are the same as the upper bits of op1.
10551 We can never remove a SUBREG for a non-equality comparison because
10552 the sign bit is in a different place in the underlying object. */
10554 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10555 op1
= make_compound_operation (op1
, SET
);
10557 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10558 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10559 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
10560 && (code
== NE
|| code
== EQ
))
10562 if (GET_MODE_SIZE (GET_MODE (op0
))
10563 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
10565 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10567 if (REG_P (SUBREG_REG (op0
)))
10569 op0
= SUBREG_REG (op0
);
10570 op1
= gen_lowpart (GET_MODE (op0
), op1
);
10573 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10574 <= HOST_BITS_PER_WIDE_INT
)
10575 && (nonzero_bits (SUBREG_REG (op0
),
10576 GET_MODE (SUBREG_REG (op0
)))
10577 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10579 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
10581 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10582 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
10583 op0
= SUBREG_REG (op0
), op1
= tem
;
10587 /* We now do the opposite procedure: Some machines don't have compare
10588 insns in all modes. If OP0's mode is an integer mode smaller than a
10589 word and we can't do a compare in that mode, see if there is a larger
10590 mode for which we can do the compare. There are a number of cases in
10591 which we can use the wider mode. */
10593 mode
= GET_MODE (op0
);
10594 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10595 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10596 && ! have_insn_for (COMPARE
, mode
))
10597 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10599 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10600 tmode
= GET_MODE_WIDER_MODE (tmode
))
10601 if (have_insn_for (COMPARE
, tmode
))
10605 /* If the only nonzero bits in OP0 and OP1 are those in the
10606 narrower mode and this is an equality or unsigned comparison,
10607 we can use the wider mode. Similarly for sign-extended
10608 values, in which case it is true for all comparisons. */
10609 zero_extended
= ((code
== EQ
|| code
== NE
10610 || code
== GEU
|| code
== GTU
10611 || code
== LEU
|| code
== LTU
)
10612 && (nonzero_bits (op0
, tmode
)
10613 & ~GET_MODE_MASK (mode
)) == 0
10614 && ((GET_CODE (op1
) == CONST_INT
10615 || (nonzero_bits (op1
, tmode
)
10616 & ~GET_MODE_MASK (mode
)) == 0)));
10619 || ((num_sign_bit_copies (op0
, tmode
)
10620 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10621 - GET_MODE_BITSIZE (mode
)))
10622 && (num_sign_bit_copies (op1
, tmode
)
10623 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
10624 - GET_MODE_BITSIZE (mode
)))))
10626 /* If OP0 is an AND and we don't have an AND in MODE either,
10627 make a new AND in the proper mode. */
10628 if (GET_CODE (op0
) == AND
10629 && !have_insn_for (AND
, mode
))
10630 op0
= gen_binary (AND
, tmode
,
10631 gen_lowpart (tmode
,
10633 gen_lowpart (tmode
,
10636 op0
= gen_lowpart (tmode
, op0
);
10637 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
10638 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
10639 op1
= gen_lowpart (tmode
, op1
);
10643 /* If this is a test for negative, we can make an explicit
10644 test of the sign bit. */
10646 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10647 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10649 op0
= gen_binary (AND
, tmode
,
10650 gen_lowpart (tmode
, op0
),
10651 GEN_INT ((HOST_WIDE_INT
) 1
10652 << (GET_MODE_BITSIZE (mode
) - 1)));
10653 code
= (code
== LT
) ? NE
: EQ
;
10658 #ifdef CANONICALIZE_COMPARISON
10659 /* If this machine only supports a subset of valid comparisons, see if we
10660 can convert an unsupported one into a supported one. */
10661 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10670 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10671 searching backward. */
10672 static enum rtx_code
10673 combine_reversed_comparison_code (rtx exp
)
10675 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
10678 if (code1
!= UNKNOWN
10679 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
10681 /* Otherwise try and find where the condition codes were last set and
10683 x
= get_last_value (XEXP (exp
, 0));
10684 if (!x
|| GET_CODE (x
) != COMPARE
)
10686 return reversed_comparison_code_parts (GET_CODE (exp
),
10687 XEXP (x
, 0), XEXP (x
, 1), NULL
);
10690 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10691 Return NULL_RTX in case we fail to do the reversal. */
10693 reversed_comparison (rtx exp
, enum machine_mode mode
, rtx op0
, rtx op1
)
10695 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
10696 if (reversed_code
== UNKNOWN
)
10699 return gen_binary (reversed_code
, mode
, op0
, op1
);
10702 /* Utility function for following routine. Called when X is part of a value
10703 being stored into last_set_value. Sets last_set_table_tick
10704 for each register mentioned. Similar to mention_regs in cse.c */
10707 update_table_tick (rtx x
)
10709 enum rtx_code code
= GET_CODE (x
);
10710 const char *fmt
= GET_RTX_FORMAT (code
);
10715 unsigned int regno
= REGNO (x
);
10716 unsigned int endregno
10717 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10718 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
10721 for (r
= regno
; r
< endregno
; r
++)
10722 reg_stat
[r
].last_set_table_tick
= label_tick
;
10727 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10728 /* Note that we can't have an "E" in values stored; see
10729 get_last_value_validate. */
10732 /* Check for identical subexpressions. If x contains
10733 identical subexpression we only have to traverse one of
10735 if (i
== 0 && ARITHMETIC_P (x
))
10737 /* Note that at this point x1 has already been
10739 rtx x0
= XEXP (x
, 0);
10740 rtx x1
= XEXP (x
, 1);
10742 /* If x0 and x1 are identical then there is no need to
10747 /* If x0 is identical to a subexpression of x1 then while
10748 processing x1, x0 has already been processed. Thus we
10749 are done with x. */
10750 if (ARITHMETIC_P (x1
)
10751 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
10754 /* If x1 is identical to a subexpression of x0 then we
10755 still have to process the rest of x0. */
10756 if (ARITHMETIC_P (x0
)
10757 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
10759 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
10764 update_table_tick (XEXP (x
, i
));
10768 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10769 are saying that the register is clobbered and we no longer know its
10770 value. If INSN is zero, don't update reg_stat[].last_set; this is
10771 only permitted with VALUE also zero and is used to invalidate the
10775 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
10777 unsigned int regno
= REGNO (reg
);
10778 unsigned int endregno
10779 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10780 ? hard_regno_nregs
[regno
][GET_MODE (reg
)] : 1);
10783 /* If VALUE contains REG and we have a previous value for REG, substitute
10784 the previous value. */
10785 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
10789 /* Set things up so get_last_value is allowed to see anything set up to
10791 subst_low_cuid
= INSN_CUID (insn
);
10792 tem
= get_last_value (reg
);
10794 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10795 it isn't going to be useful and will take a lot of time to process,
10796 so just use the CLOBBER. */
10800 if (ARITHMETIC_P (tem
)
10801 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
10802 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
10803 tem
= XEXP (tem
, 0);
10805 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
10809 /* For each register modified, show we don't know its value, that
10810 we don't know about its bitwise content, that its value has been
10811 updated, and that we don't know the location of the death of the
10813 for (i
= regno
; i
< endregno
; i
++)
10816 reg_stat
[i
].last_set
= insn
;
10818 reg_stat
[i
].last_set_value
= 0;
10819 reg_stat
[i
].last_set_mode
= 0;
10820 reg_stat
[i
].last_set_nonzero_bits
= 0;
10821 reg_stat
[i
].last_set_sign_bit_copies
= 0;
10822 reg_stat
[i
].last_death
= 0;
10825 /* Mark registers that are being referenced in this value. */
10827 update_table_tick (value
);
10829 /* Now update the status of each register being set.
10830 If someone is using this register in this block, set this register
10831 to invalid since we will get confused between the two lives in this
10832 basic block. This makes using this register always invalid. In cse, we
10833 scan the table to invalidate all entries using this register, but this
10834 is too much work for us. */
10836 for (i
= regno
; i
< endregno
; i
++)
10838 reg_stat
[i
].last_set_label
= label_tick
;
10839 if (value
&& reg_stat
[i
].last_set_table_tick
== label_tick
)
10840 reg_stat
[i
].last_set_invalid
= 1;
10842 reg_stat
[i
].last_set_invalid
= 0;
10845 /* The value being assigned might refer to X (like in "x++;"). In that
10846 case, we must replace it with (clobber (const_int 0)) to prevent
10848 if (value
&& ! get_last_value_validate (&value
, insn
,
10849 reg_stat
[regno
].last_set_label
, 0))
10851 value
= copy_rtx (value
);
10852 if (! get_last_value_validate (&value
, insn
,
10853 reg_stat
[regno
].last_set_label
, 1))
10857 /* For the main register being modified, update the value, the mode, the
10858 nonzero bits, and the number of sign bit copies. */
10860 reg_stat
[regno
].last_set_value
= value
;
10864 enum machine_mode mode
= GET_MODE (reg
);
10865 subst_low_cuid
= INSN_CUID (insn
);
10866 reg_stat
[regno
].last_set_mode
= mode
;
10867 if (GET_MODE_CLASS (mode
) == MODE_INT
10868 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10869 mode
= nonzero_bits_mode
;
10870 reg_stat
[regno
].last_set_nonzero_bits
= nonzero_bits (value
, mode
);
10871 reg_stat
[regno
].last_set_sign_bit_copies
10872 = num_sign_bit_copies (value
, GET_MODE (reg
));
10876 /* Called via note_stores from record_dead_and_set_regs to handle one
10877 SET or CLOBBER in an insn. DATA is the instruction in which the
10878 set is occurring. */
10881 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
10883 rtx record_dead_insn
= (rtx
) data
;
10885 if (GET_CODE (dest
) == SUBREG
)
10886 dest
= SUBREG_REG (dest
);
10890 /* If we are setting the whole register, we know its value. Otherwise
10891 show that we don't know the value. We can handle SUBREG in
10893 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
10894 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
10895 else if (GET_CODE (setter
) == SET
10896 && GET_CODE (SET_DEST (setter
)) == SUBREG
10897 && SUBREG_REG (SET_DEST (setter
)) == dest
10898 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
10899 && subreg_lowpart_p (SET_DEST (setter
)))
10900 record_value_for_reg (dest
, record_dead_insn
,
10901 gen_lowpart (GET_MODE (dest
),
10902 SET_SRC (setter
)));
10904 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
10906 else if (MEM_P (dest
)
10907 /* Ignore pushes, they clobber nothing. */
10908 && ! push_operand (dest
, GET_MODE (dest
)))
10909 mem_last_set
= INSN_CUID (record_dead_insn
);
10912 /* Update the records of when each REG was most recently set or killed
10913 for the things done by INSN. This is the last thing done in processing
10914 INSN in the combiner loop.
10916 We update reg_stat[], in particular fields last_set, last_set_value,
10917 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10918 last_death, and also the similar information mem_last_set (which insn
10919 most recently modified memory) and last_call_cuid (which insn was the
10920 most recent subroutine call). */
10923 record_dead_and_set_regs (rtx insn
)
10928 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
10930 if (REG_NOTE_KIND (link
) == REG_DEAD
10931 && REG_P (XEXP (link
, 0)))
10933 unsigned int regno
= REGNO (XEXP (link
, 0));
10934 unsigned int endregno
10935 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
10936 ? hard_regno_nregs
[regno
][GET_MODE (XEXP (link
, 0))]
10939 for (i
= regno
; i
< endregno
; i
++)
10940 reg_stat
[i
].last_death
= insn
;
10942 else if (REG_NOTE_KIND (link
) == REG_INC
)
10943 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
10948 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
10949 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
10951 reg_stat
[i
].last_set_value
= 0;
10952 reg_stat
[i
].last_set_mode
= 0;
10953 reg_stat
[i
].last_set_nonzero_bits
= 0;
10954 reg_stat
[i
].last_set_sign_bit_copies
= 0;
10955 reg_stat
[i
].last_death
= 0;
10958 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
10960 /* Don't bother recording what this insn does. It might set the
10961 return value register, but we can't combine into a call
10962 pattern anyway, so there's no point trying (and it may cause
10963 a crash, if e.g. we wind up asking for last_set_value of a
10964 SUBREG of the return value register). */
10968 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
10971 /* If a SUBREG has the promoted bit set, it is in fact a property of the
10972 register present in the SUBREG, so for each such SUBREG go back and
10973 adjust nonzero and sign bit information of the registers that are
10974 known to have some zero/sign bits set.
10976 This is needed because when combine blows the SUBREGs away, the
10977 information on zero/sign bits is lost and further combines can be
10978 missed because of that. */
10981 record_promoted_value (rtx insn
, rtx subreg
)
10984 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
10985 enum machine_mode mode
= GET_MODE (subreg
);
10987 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
10990 for (links
= LOG_LINKS (insn
); links
;)
10992 insn
= XEXP (links
, 0);
10993 set
= single_set (insn
);
10995 if (! set
|| !REG_P (SET_DEST (set
))
10996 || REGNO (SET_DEST (set
)) != regno
10997 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
10999 links
= XEXP (links
, 1);
11003 if (reg_stat
[regno
].last_set
== insn
)
11005 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11006 reg_stat
[regno
].last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
11009 if (REG_P (SET_SRC (set
)))
11011 regno
= REGNO (SET_SRC (set
));
11012 links
= LOG_LINKS (insn
);
11019 /* Scan X for promoted SUBREGs. For each one found,
11020 note what it implies to the registers used in it. */
11023 check_promoted_subreg (rtx insn
, rtx x
)
11025 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11026 && REG_P (SUBREG_REG (x
)))
11027 record_promoted_value (insn
, x
);
11030 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11033 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11037 check_promoted_subreg (insn
, XEXP (x
, i
));
11041 if (XVEC (x
, i
) != 0)
11042 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11043 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11049 /* Utility routine for the following function. Verify that all the registers
11050 mentioned in *LOC are valid when *LOC was part of a value set when
11051 label_tick == TICK. Return 0 if some are not.
11053 If REPLACE is nonzero, replace the invalid reference with
11054 (clobber (const_int 0)) and return 1. This replacement is useful because
11055 we often can get useful information about the form of a value (e.g., if
11056 it was produced by a shift that always produces -1 or 0) even though
11057 we don't know exactly what registers it was produced from. */
11060 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11063 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11064 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11069 unsigned int regno
= REGNO (x
);
11070 unsigned int endregno
11071 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11072 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11075 for (j
= regno
; j
< endregno
; j
++)
11076 if (reg_stat
[j
].last_set_invalid
11077 /* If this is a pseudo-register that was only set once and not
11078 live at the beginning of the function, it is always valid. */
11079 || (! (regno
>= FIRST_PSEUDO_REGISTER
11080 && REG_N_SETS (regno
) == 1
11081 && (! REGNO_REG_SET_P
11082 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11083 && reg_stat
[j
].last_set_label
> tick
))
11086 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11092 /* If this is a memory reference, make sure that there were
11093 no stores after it that might have clobbered the value. We don't
11094 have alias info, so we assume any store invalidates it. */
11095 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
11096 && INSN_CUID (insn
) <= mem_last_set
)
11099 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11103 for (i
= 0; i
< len
; i
++)
11107 /* Check for identical subexpressions. If x contains
11108 identical subexpression we only have to traverse one of
11110 if (i
== 1 && ARITHMETIC_P (x
))
11112 /* Note that at this point x0 has already been checked
11113 and found valid. */
11114 rtx x0
= XEXP (x
, 0);
11115 rtx x1
= XEXP (x
, 1);
11117 /* If x0 and x1 are identical then x is also valid. */
11121 /* If x1 is identical to a subexpression of x0 then
11122 while checking x0, x1 has already been checked. Thus
11123 it is valid and so as x. */
11124 if (ARITHMETIC_P (x0
)
11125 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11128 /* If x0 is identical to a subexpression of x1 then x is
11129 valid iff the rest of x1 is valid. */
11130 if (ARITHMETIC_P (x1
)
11131 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11133 get_last_value_validate (&XEXP (x1
,
11134 x0
== XEXP (x1
, 0) ? 1 : 0),
11135 insn
, tick
, replace
);
11138 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11142 /* Don't bother with these. They shouldn't occur anyway. */
11143 else if (fmt
[i
] == 'E')
11147 /* If we haven't found a reason for it to be invalid, it is valid. */
11151 /* Get the last value assigned to X, if known. Some registers
11152 in the value may be replaced with (clobber (const_int 0)) if their value
11153 is known longer known reliably. */
11156 get_last_value (rtx x
)
11158 unsigned int regno
;
11161 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11162 then convert it to the desired mode. If this is a paradoxical SUBREG,
11163 we cannot predict what values the "extra" bits might have. */
11164 if (GET_CODE (x
) == SUBREG
11165 && subreg_lowpart_p (x
)
11166 && (GET_MODE_SIZE (GET_MODE (x
))
11167 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11168 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11169 return gen_lowpart (GET_MODE (x
), value
);
11175 value
= reg_stat
[regno
].last_set_value
;
11177 /* If we don't have a value, or if it isn't for this basic block and
11178 it's either a hard register, set more than once, or it's a live
11179 at the beginning of the function, return 0.
11181 Because if it's not live at the beginning of the function then the reg
11182 is always set before being used (is never used without being set).
11183 And, if it's set only once, and it's always set before use, then all
11184 uses must have the same last value, even if it's not from this basic
11188 || (reg_stat
[regno
].last_set_label
!= label_tick
11189 && (regno
< FIRST_PSEUDO_REGISTER
11190 || REG_N_SETS (regno
) != 1
11191 || (REGNO_REG_SET_P
11192 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11195 /* If the value was set in a later insn than the ones we are processing,
11196 we can't use it even if the register was only set once. */
11197 if (INSN_CUID (reg_stat
[regno
].last_set
) >= subst_low_cuid
)
11200 /* If the value has all its registers valid, return it. */
11201 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11202 reg_stat
[regno
].last_set_label
, 0))
11205 /* Otherwise, make a copy and replace any invalid register with
11206 (clobber (const_int 0)). If that fails for some reason, return 0. */
11208 value
= copy_rtx (value
);
11209 if (get_last_value_validate (&value
, reg_stat
[regno
].last_set
,
11210 reg_stat
[regno
].last_set_label
, 1))
11216 /* Return nonzero if expression X refers to a REG or to memory
11217 that is set in an instruction more recent than FROM_CUID. */
11220 use_crosses_set_p (rtx x
, int from_cuid
)
11224 enum rtx_code code
= GET_CODE (x
);
11228 unsigned int regno
= REGNO (x
);
11229 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11230 ? hard_regno_nregs
[regno
][GET_MODE (x
)] : 1);
11232 #ifdef PUSH_ROUNDING
11233 /* Don't allow uses of the stack pointer to be moved,
11234 because we don't know whether the move crosses a push insn. */
11235 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11238 for (; regno
< endreg
; regno
++)
11239 if (reg_stat
[regno
].last_set
11240 && INSN_CUID (reg_stat
[regno
].last_set
) > from_cuid
)
11245 if (code
== MEM
&& mem_last_set
> from_cuid
)
11248 fmt
= GET_RTX_FORMAT (code
);
11250 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11255 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11256 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11259 else if (fmt
[i
] == 'e'
11260 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11266 /* Define three variables used for communication between the following
11269 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11270 static int reg_dead_flag
;
11272 /* Function called via note_stores from reg_dead_at_p.
11274 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11275 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11278 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11280 unsigned int regno
, endregno
;
11285 regno
= REGNO (dest
);
11286 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11287 ? hard_regno_nregs
[regno
][GET_MODE (dest
)] : 1);
11289 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11290 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11293 /* Return nonzero if REG is known to be dead at INSN.
11295 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11296 referencing REG, it is dead. If we hit a SET referencing REG, it is
11297 live. Otherwise, see if it is live or dead at the start of the basic
11298 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11299 must be assumed to be always live. */
11302 reg_dead_at_p (rtx reg
, rtx insn
)
11307 /* Set variables for reg_dead_at_p_1. */
11308 reg_dead_regno
= REGNO (reg
);
11309 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11310 ? hard_regno_nregs
[reg_dead_regno
]
11316 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11317 we allow the machine description to decide whether use-and-clobber
11318 patterns are OK. */
11319 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11321 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11322 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11326 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11327 beginning of function. */
11328 for (; insn
&& !LABEL_P (insn
) && !BARRIER_P (insn
);
11329 insn
= prev_nonnote_insn (insn
))
11331 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11333 return reg_dead_flag
== 1 ? 1 : 0;
11335 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11339 /* Get the basic block that we were in. */
11341 block
= ENTRY_BLOCK_PTR
->next_bb
;
11344 FOR_EACH_BB (block
)
11345 if (insn
== BB_HEAD (block
))
11348 if (block
== EXIT_BLOCK_PTR
)
11352 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11353 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
11359 /* Note hard registers in X that are used. This code is similar to
11360 that in flow.c, but much simpler since we don't care about pseudos. */
11363 mark_used_regs_combine (rtx x
)
11365 RTX_CODE code
= GET_CODE (x
);
11366 unsigned int regno
;
11379 case ADDR_DIFF_VEC
:
11382 /* CC0 must die in the insn after it is set, so we don't need to take
11383 special note of it here. */
11389 /* If we are clobbering a MEM, mark any hard registers inside the
11390 address as used. */
11391 if (MEM_P (XEXP (x
, 0)))
11392 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11397 /* A hard reg in a wide mode may really be multiple registers.
11398 If so, mark all of them just like the first. */
11399 if (regno
< FIRST_PSEUDO_REGISTER
)
11401 unsigned int endregno
, r
;
11403 /* None of this applies to the stack, frame or arg pointers. */
11404 if (regno
== STACK_POINTER_REGNUM
11405 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11406 || regno
== HARD_FRAME_POINTER_REGNUM
11408 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11409 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11411 || regno
== FRAME_POINTER_REGNUM
)
11414 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11415 for (r
= regno
; r
< endregno
; r
++)
11416 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11422 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11424 rtx testreg
= SET_DEST (x
);
11426 while (GET_CODE (testreg
) == SUBREG
11427 || GET_CODE (testreg
) == ZERO_EXTRACT
11428 || GET_CODE (testreg
) == SIGN_EXTRACT
11429 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11430 testreg
= XEXP (testreg
, 0);
11432 if (MEM_P (testreg
))
11433 mark_used_regs_combine (XEXP (testreg
, 0));
11435 mark_used_regs_combine (SET_SRC (x
));
11443 /* Recursively scan the operands of this expression. */
11446 const char *fmt
= GET_RTX_FORMAT (code
);
11448 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11451 mark_used_regs_combine (XEXP (x
, i
));
11452 else if (fmt
[i
] == 'E')
11456 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11457 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11463 /* Remove register number REGNO from the dead registers list of INSN.
11465 Return the note used to record the death, if there was one. */
11468 remove_death (unsigned int regno
, rtx insn
)
11470 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11474 REG_N_DEATHS (regno
)--;
11475 remove_note (insn
, note
);
11481 /* For each register (hardware or pseudo) used within expression X, if its
11482 death is in an instruction with cuid between FROM_CUID (inclusive) and
11483 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11484 list headed by PNOTES.
11486 That said, don't move registers killed by maybe_kill_insn.
11488 This is done when X is being merged by combination into TO_INSN. These
11489 notes will then be distributed as needed. */
11492 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
11497 enum rtx_code code
= GET_CODE (x
);
11501 unsigned int regno
= REGNO (x
);
11502 rtx where_dead
= reg_stat
[regno
].last_death
;
11503 rtx before_dead
, after_dead
;
11505 /* Don't move the register if it gets killed in between from and to. */
11506 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11507 && ! reg_referenced_p (x
, maybe_kill_insn
))
11510 /* WHERE_DEAD could be a USE insn made by combine, so first we
11511 make sure that we have insns with valid INSN_CUID values. */
11512 before_dead
= where_dead
;
11513 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11514 before_dead
= PREV_INSN (before_dead
);
11516 after_dead
= where_dead
;
11517 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11518 after_dead
= NEXT_INSN (after_dead
);
11520 if (before_dead
&& after_dead
11521 && INSN_CUID (before_dead
) >= from_cuid
11522 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11523 || (where_dead
!= after_dead
11524 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11526 rtx note
= remove_death (regno
, where_dead
);
11528 /* It is possible for the call above to return 0. This can occur
11529 when last_death points to I2 or I1 that we combined with.
11530 In that case make a new note.
11532 We must also check for the case where X is a hard register
11533 and NOTE is a death note for a range of hard registers
11534 including X. In that case, we must put REG_DEAD notes for
11535 the remaining registers in place of NOTE. */
11537 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11538 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11539 > GET_MODE_SIZE (GET_MODE (x
))))
11541 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11542 unsigned int deadend
11543 = (deadregno
+ hard_regno_nregs
[deadregno
]
11544 [GET_MODE (XEXP (note
, 0))]);
11545 unsigned int ourend
11546 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11549 for (i
= deadregno
; i
< deadend
; i
++)
11550 if (i
< regno
|| i
>= ourend
)
11551 REG_NOTES (where_dead
)
11552 = gen_rtx_EXPR_LIST (REG_DEAD
,
11554 REG_NOTES (where_dead
));
11557 /* If we didn't find any note, or if we found a REG_DEAD note that
11558 covers only part of the given reg, and we have a multi-reg hard
11559 register, then to be safe we must check for REG_DEAD notes
11560 for each register other than the first. They could have
11561 their own REG_DEAD notes lying around. */
11562 else if ((note
== 0
11564 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11565 < GET_MODE_SIZE (GET_MODE (x
)))))
11566 && regno
< FIRST_PSEUDO_REGISTER
11567 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
11569 unsigned int ourend
11570 = regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11571 unsigned int i
, offset
;
11575 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
11579 for (i
= regno
+ offset
; i
< ourend
; i
++)
11580 move_deaths (regno_reg_rtx
[i
],
11581 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11584 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11586 XEXP (note
, 1) = *pnotes
;
11590 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11592 REG_N_DEATHS (regno
)++;
11598 else if (GET_CODE (x
) == SET
)
11600 rtx dest
= SET_DEST (x
);
11602 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11604 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11605 that accesses one word of a multi-word item, some
11606 piece of everything register in the expression is used by
11607 this insn, so remove any old death. */
11608 /* ??? So why do we test for equality of the sizes? */
11610 if (GET_CODE (dest
) == ZERO_EXTRACT
11611 || GET_CODE (dest
) == STRICT_LOW_PART
11612 || (GET_CODE (dest
) == SUBREG
11613 && (((GET_MODE_SIZE (GET_MODE (dest
))
11614 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11615 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11616 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11618 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11622 /* If this is some other SUBREG, we know it replaces the entire
11623 value, so use that as the destination. */
11624 if (GET_CODE (dest
) == SUBREG
)
11625 dest
= SUBREG_REG (dest
);
11627 /* If this is a MEM, adjust deaths of anything used in the address.
11628 For a REG (the only other possibility), the entire value is
11629 being replaced so the old value is not used in this insn. */
11632 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11637 else if (GET_CODE (x
) == CLOBBER
)
11640 len
= GET_RTX_LENGTH (code
);
11641 fmt
= GET_RTX_FORMAT (code
);
11643 for (i
= 0; i
< len
; i
++)
11648 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11649 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11652 else if (fmt
[i
] == 'e')
11653 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11657 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11658 pattern of an insn. X must be a REG. */
11661 reg_bitfield_target_p (rtx x
, rtx body
)
11665 if (GET_CODE (body
) == SET
)
11667 rtx dest
= SET_DEST (body
);
11669 unsigned int regno
, tregno
, endregno
, endtregno
;
11671 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11672 target
= XEXP (dest
, 0);
11673 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11674 target
= SUBREG_REG (XEXP (dest
, 0));
11678 if (GET_CODE (target
) == SUBREG
)
11679 target
= SUBREG_REG (target
);
11681 if (!REG_P (target
))
11684 tregno
= REGNO (target
), regno
= REGNO (x
);
11685 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11686 return target
== x
;
11688 endtregno
= tregno
+ hard_regno_nregs
[tregno
][GET_MODE (target
)];
11689 endregno
= regno
+ hard_regno_nregs
[regno
][GET_MODE (x
)];
11691 return endregno
> tregno
&& regno
< endtregno
;
11694 else if (GET_CODE (body
) == PARALLEL
)
11695 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11696 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11702 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11703 as appropriate. I3 and I2 are the insns resulting from the combination
11704 insns including FROM (I2 may be zero).
11706 Each note in the list is either ignored or placed on some insns, depending
11707 on the type of note. */
11710 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
11712 rtx note
, next_note
;
11715 for (note
= notes
; note
; note
= next_note
)
11717 rtx place
= 0, place2
= 0;
11719 /* If this NOTE references a pseudo register, ensure it references
11720 the latest copy of that register. */
11721 if (XEXP (note
, 0) && REG_P (XEXP (note
, 0))
11722 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
11723 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
11725 next_note
= XEXP (note
, 1);
11726 switch (REG_NOTE_KIND (note
))
11730 /* Doesn't matter much where we put this, as long as it's somewhere.
11731 It is preferable to keep these notes on branches, which is most
11732 likely to be i3. */
11736 case REG_VALUE_PROFILE
:
11737 /* Just get rid of this note, as it is unused later anyway. */
11740 case REG_NON_LOCAL_GOTO
:
11745 gcc_assert (i2
&& JUMP_P (i2
));
11750 case REG_EH_REGION
:
11751 /* These notes must remain with the call or trapping instruction. */
11754 else if (i2
&& CALL_P (i2
))
11758 gcc_assert (flag_non_call_exceptions
);
11759 if (may_trap_p (i3
))
11761 else if (i2
&& may_trap_p (i2
))
11763 /* ??? Otherwise assume we've combined things such that we
11764 can now prove that the instructions can't trap. Drop the
11765 note in this case. */
11769 case REG_ALWAYS_RETURN
:
11772 /* These notes must remain with the call. It should not be
11773 possible for both I2 and I3 to be a call. */
11778 gcc_assert (i2
&& CALL_P (i2
));
11784 /* Any clobbers for i3 may still exist, and so we must process
11785 REG_UNUSED notes from that insn.
11787 Any clobbers from i2 or i1 can only exist if they were added by
11788 recog_for_combine. In that case, recog_for_combine created the
11789 necessary REG_UNUSED notes. Trying to keep any original
11790 REG_UNUSED notes from these insns can cause incorrect output
11791 if it is for the same register as the original i3 dest.
11792 In that case, we will notice that the register is set in i3,
11793 and then add a REG_UNUSED note for the destination of i3, which
11794 is wrong. However, it is possible to have REG_UNUSED notes from
11795 i2 or i1 for register which were both used and clobbered, so
11796 we keep notes from i2 or i1 if they will turn into REG_DEAD
11799 /* If this register is set or clobbered in I3, put the note there
11800 unless there is one already. */
11801 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
11803 if (from_insn
!= i3
)
11806 if (! (REG_P (XEXP (note
, 0))
11807 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
11808 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
11811 /* Otherwise, if this register is used by I3, then this register
11812 now dies here, so we must put a REG_DEAD note here unless there
11814 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
11815 && ! (REG_P (XEXP (note
, 0))
11816 ? find_regno_note (i3
, REG_DEAD
,
11817 REGNO (XEXP (note
, 0)))
11818 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
11820 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
11828 /* These notes say something about results of an insn. We can
11829 only support them if they used to be on I3 in which case they
11830 remain on I3. Otherwise they are ignored.
11832 If the note refers to an expression that is not a constant, we
11833 must also ignore the note since we cannot tell whether the
11834 equivalence is still true. It might be possible to do
11835 slightly better than this (we only have a problem if I2DEST
11836 or I1DEST is present in the expression), but it doesn't
11837 seem worth the trouble. */
11839 if (from_insn
== i3
11840 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
11845 case REG_NO_CONFLICT
:
11846 /* These notes say something about how a register is used. They must
11847 be present on any use of the register in I2 or I3. */
11848 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
11851 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
11861 /* This can show up in several ways -- either directly in the
11862 pattern, or hidden off in the constant pool with (or without?)
11863 a REG_EQUAL note. */
11864 /* ??? Ignore the without-reg_equal-note problem for now. */
11865 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
11866 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
11867 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
11868 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
11872 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
11873 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
11874 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
11875 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
11883 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
11884 a JUMP_LABEL instead or decrement LABEL_NUSES. */
11885 if (place
&& JUMP_P (place
))
11887 rtx label
= JUMP_LABEL (place
);
11890 JUMP_LABEL (place
) = XEXP (note
, 0);
11893 gcc_assert (label
== XEXP (note
, 0));
11894 if (LABEL_P (label
))
11895 LABEL_NUSES (label
)--;
11899 if (place2
&& JUMP_P (place2
))
11901 rtx label
= JUMP_LABEL (place2
);
11904 JUMP_LABEL (place2
) = XEXP (note
, 0);
11907 gcc_assert (label
== XEXP (note
, 0));
11908 if (LABEL_P (label
))
11909 LABEL_NUSES (label
)--;
11916 /* This note says something about the value of a register prior
11917 to the execution of an insn. It is too much trouble to see
11918 if the note is still correct in all situations. It is better
11919 to simply delete it. */
11923 /* If the insn previously containing this note still exists,
11924 put it back where it was. Otherwise move it to the previous
11925 insn. Adjust the corresponding REG_LIBCALL note. */
11926 if (!NOTE_P (from_insn
))
11930 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
11931 place
= prev_real_insn (from_insn
);
11933 XEXP (tem
, 0) = place
;
11934 /* If we're deleting the last remaining instruction of a
11935 libcall sequence, don't add the notes. */
11936 else if (XEXP (note
, 0) == from_insn
)
11938 /* Don't add the dangling REG_RETVAL note. */
11945 /* This is handled similarly to REG_RETVAL. */
11946 if (!NOTE_P (from_insn
))
11950 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
11951 place
= next_real_insn (from_insn
);
11953 XEXP (tem
, 0) = place
;
11954 /* If we're deleting the last remaining instruction of a
11955 libcall sequence, don't add the notes. */
11956 else if (XEXP (note
, 0) == from_insn
)
11958 /* Don't add the dangling REG_LIBCALL note. */
11965 /* If the register is used as an input in I3, it dies there.
11966 Similarly for I2, if it is nonzero and adjacent to I3.
11968 If the register is not used as an input in either I3 or I2
11969 and it is not one of the registers we were supposed to eliminate,
11970 there are two possibilities. We might have a non-adjacent I2
11971 or we might have somehow eliminated an additional register
11972 from a computation. For example, we might have had A & B where
11973 we discover that B will always be zero. In this case we will
11974 eliminate the reference to A.
11976 In both cases, we must search to see if we can find a previous
11977 use of A and put the death note there. */
11980 && CALL_P (from_insn
)
11981 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
11983 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
11985 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
11986 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
11991 basic_block bb
= this_basic_block
;
11993 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
11995 if (! INSN_P (tem
))
11997 if (tem
== BB_HEAD (bb
))
12002 /* If the register is being set at TEM, see if that is all
12003 TEM is doing. If so, delete TEM. Otherwise, make this
12004 into a REG_UNUSED note instead. Don't delete sets to
12005 global register vars. */
12006 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
12007 || !global_regs
[REGNO (XEXP (note
, 0))])
12008 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12010 rtx set
= single_set (tem
);
12011 rtx inner_dest
= 0;
12013 rtx cc0_setter
= NULL_RTX
;
12017 for (inner_dest
= SET_DEST (set
);
12018 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12019 || GET_CODE (inner_dest
) == SUBREG
12020 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12021 inner_dest
= XEXP (inner_dest
, 0))
12024 /* Verify that it was the set, and not a clobber that
12025 modified the register.
12027 CC0 targets must be careful to maintain setter/user
12028 pairs. If we cannot delete the setter due to side
12029 effects, mark the user with an UNUSED note instead
12032 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12033 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12035 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12036 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12037 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12041 /* Move the notes and links of TEM elsewhere.
12042 This might delete other dead insns recursively.
12043 First set the pattern to something that won't use
12045 rtx old_notes
= REG_NOTES (tem
);
12047 PATTERN (tem
) = pc_rtx
;
12048 REG_NOTES (tem
) = NULL
;
12050 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
);
12051 distribute_links (LOG_LINKS (tem
));
12053 SET_INSN_DELETED (tem
);
12056 /* Delete the setter too. */
12059 PATTERN (cc0_setter
) = pc_rtx
;
12060 old_notes
= REG_NOTES (cc0_setter
);
12061 REG_NOTES (cc0_setter
) = NULL
;
12063 distribute_notes (old_notes
, cc0_setter
,
12064 cc0_setter
, NULL_RTX
);
12065 distribute_links (LOG_LINKS (cc0_setter
));
12067 SET_INSN_DELETED (cc0_setter
);
12073 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12075 /* If there isn't already a REG_UNUSED note, put one
12076 here. Do not place a REG_DEAD note, even if
12077 the register is also used here; that would not
12078 match the algorithm used in lifetime analysis
12079 and can cause the consistency check in the
12080 scheduler to fail. */
12081 if (! find_regno_note (tem
, REG_UNUSED
,
12082 REGNO (XEXP (note
, 0))))
12087 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12089 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12093 /* If we are doing a 3->2 combination, and we have a
12094 register which formerly died in i3 and was not used
12095 by i2, which now no longer dies in i3 and is used in
12096 i2 but does not die in i2, and place is between i2
12097 and i3, then we may need to move a link from place to
12099 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12100 && INSN_CUID (place
) > INSN_CUID (i2
)
12102 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12103 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12105 rtx links
= LOG_LINKS (place
);
12106 LOG_LINKS (place
) = 0;
12107 distribute_links (links
);
12112 if (tem
== BB_HEAD (bb
))
12116 /* We haven't found an insn for the death note and it
12117 is still a REG_DEAD note, but we have hit the beginning
12118 of the block. If the existing life info says the reg
12119 was dead, there's nothing left to do. Otherwise, we'll
12120 need to do a global life update after combine. */
12121 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12122 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12123 REGNO (XEXP (note
, 0))))
12124 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12127 /* If the register is set or already dead at PLACE, we needn't do
12128 anything with this note if it is still a REG_DEAD note.
12129 We check here if it is set at all, not if is it totally replaced,
12130 which is what `dead_or_set_p' checks, so also check for it being
12133 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12135 unsigned int regno
= REGNO (XEXP (note
, 0));
12137 /* Similarly, if the instruction on which we want to place
12138 the note is a noop, we'll need do a global live update
12139 after we remove them in delete_noop_moves. */
12140 if (noop_move_p (place
))
12141 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12143 if (dead_or_set_p (place
, XEXP (note
, 0))
12144 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12146 /* Unless the register previously died in PLACE, clear
12147 last_death. [I no longer understand why this is
12149 if (reg_stat
[regno
].last_death
!= place
)
12150 reg_stat
[regno
].last_death
= 0;
12154 reg_stat
[regno
].last_death
= place
;
12156 /* If this is a death note for a hard reg that is occupying
12157 multiple registers, ensure that we are still using all
12158 parts of the object. If we find a piece of the object
12159 that is unused, we must arrange for an appropriate REG_DEAD
12160 note to be added for it. However, we can't just emit a USE
12161 and tag the note to it, since the register might actually
12162 be dead; so we recourse, and the recursive call then finds
12163 the previous insn that used this register. */
12165 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12166 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
12168 unsigned int endregno
12169 = regno
+ hard_regno_nregs
[regno
]
12170 [GET_MODE (XEXP (note
, 0))];
12174 for (i
= regno
; i
< endregno
; i
++)
12175 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12176 && ! find_regno_fusage (place
, USE
, i
))
12177 || dead_or_set_regno_p (place
, i
))
12182 /* Put only REG_DEAD notes for pieces that are
12183 not already dead or set. */
12185 for (i
= regno
; i
< endregno
;
12186 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
12188 rtx piece
= regno_reg_rtx
[i
];
12189 basic_block bb
= this_basic_block
;
12191 if (! dead_or_set_p (place
, piece
)
12192 && ! reg_bitfield_target_p (piece
,
12196 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12198 distribute_notes (new_note
, place
, place
,
12201 else if (! refers_to_regno_p (i
, i
+ 1,
12202 PATTERN (place
), 0)
12203 && ! find_regno_fusage (place
, USE
, i
))
12204 for (tem
= PREV_INSN (place
); ;
12205 tem
= PREV_INSN (tem
))
12207 if (! INSN_P (tem
))
12209 if (tem
== BB_HEAD (bb
))
12211 SET_BIT (refresh_blocks
,
12212 this_basic_block
->index
);
12217 if (dead_or_set_p (tem
, piece
)
12218 || reg_bitfield_target_p (piece
,
12222 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12237 /* Any other notes should not be present at this point in the
12239 gcc_unreachable ();
12244 XEXP (note
, 1) = REG_NOTES (place
);
12245 REG_NOTES (place
) = note
;
12247 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12248 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12249 && REG_P (XEXP (note
, 0)))
12250 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12254 if ((REG_NOTE_KIND (note
) == REG_DEAD
12255 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12256 && REG_P (XEXP (note
, 0)))
12257 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12259 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12260 REG_NOTE_KIND (note
),
12262 REG_NOTES (place2
));
12267 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12268 I3, I2, and I1 to new locations. This is also called to add a link
12269 pointing at I3 when I3's destination is changed. */
12272 distribute_links (rtx links
)
12274 rtx link
, next_link
;
12276 for (link
= links
; link
; link
= next_link
)
12282 next_link
= XEXP (link
, 1);
12284 /* If the insn that this link points to is a NOTE or isn't a single
12285 set, ignore it. In the latter case, it isn't clear what we
12286 can do other than ignore the link, since we can't tell which
12287 register it was for. Such links wouldn't be used by combine
12290 It is not possible for the destination of the target of the link to
12291 have been changed by combine. The only potential of this is if we
12292 replace I3, I2, and I1 by I3 and I2. But in that case the
12293 destination of I2 also remains unchanged. */
12295 if (NOTE_P (XEXP (link
, 0))
12296 || (set
= single_set (XEXP (link
, 0))) == 0)
12299 reg
= SET_DEST (set
);
12300 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12301 || GET_CODE (reg
) == SIGN_EXTRACT
12302 || GET_CODE (reg
) == STRICT_LOW_PART
)
12303 reg
= XEXP (reg
, 0);
12305 /* A LOG_LINK is defined as being placed on the first insn that uses
12306 a register and points to the insn that sets the register. Start
12307 searching at the next insn after the target of the link and stop
12308 when we reach a set of the register or the end of the basic block.
12310 Note that this correctly handles the link that used to point from
12311 I3 to I2. Also note that not much searching is typically done here
12312 since most links don't point very far away. */
12314 for (insn
= NEXT_INSN (XEXP (link
, 0));
12315 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12316 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12317 insn
= NEXT_INSN (insn
))
12318 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12320 if (reg_referenced_p (reg
, PATTERN (insn
)))
12324 else if (CALL_P (insn
)
12325 && find_reg_fusage (insn
, USE
, reg
))
12330 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12333 /* If we found a place to put the link, place it there unless there
12334 is already a link to the same insn as LINK at that point. */
12340 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12341 if (XEXP (link2
, 0) == XEXP (link
, 0))
12346 XEXP (link
, 1) = LOG_LINKS (place
);
12347 LOG_LINKS (place
) = link
;
12349 /* Set added_links_insn to the earliest insn we added a
12351 if (added_links_insn
== 0
12352 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12353 added_links_insn
= place
;
12359 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12360 Check whether the expression pointer to by LOC is a register or
12361 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12362 Otherwise return zero. */
12365 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
12370 && (REG_P (x
) || MEM_P (x
))
12371 && ! reg_mentioned_p (x
, (rtx
) expr
))
12376 /* Check for any register or memory mentioned in EQUIV that is not
12377 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12378 of EXPR where some registers may have been replaced by constants. */
12381 unmentioned_reg_p (rtx equiv
, rtx expr
)
12383 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
12386 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12389 insn_cuid (rtx insn
)
12391 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12392 && NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
)
12393 insn
= NEXT_INSN (insn
);
12395 gcc_assert (INSN_UID (insn
) <= max_uid_cuid
);
12397 return INSN_CUID (insn
);
12401 dump_combine_stats (FILE *file
)
12405 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12406 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12410 dump_combine_total_stats (FILE *file
)
12414 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12415 total_attempts
, total_merges
, total_extras
, total_successes
);