1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts
;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges
;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras
;
110 /* Number of instructions combined in this function. */
112 static int combine_successes
;
114 /* Totals over entire compilation. */
116 static int total_attempts
, total_merges
, total_extras
, total_successes
;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid
;
127 static int max_uid_cuid
;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 #define nonzero_bits(X, M) \
141 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
143 #define num_sign_bit_copies(X, M) \
144 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
146 /* Maximum register number, which is the size of the tables below. */
148 static unsigned int combine_max_regno
;
150 /* Record last point of death of (hard or pseudo) register n. */
152 static rtx
*reg_last_death
;
154 /* Record last point of modification of (hard or pseudo) register n. */
156 static rtx
*reg_last_set
;
158 /* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
161 static int mem_last_set
;
163 /* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
166 static int last_call_cuid
;
168 /* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
174 static rtx subst_insn
;
176 /* This is the lowest CUID that `subst' is currently dealing with.
177 get_last_value will not return a value if the register was set at or
178 after this CUID. If not for this mechanism, we could get confused if
179 I2 or I1 in try_combine were an insn that used the old value of a register
180 to obtain a new value. In that case, we might erroneously get the
181 new value of the register when we wanted the old one. */
183 static int subst_low_cuid
;
185 /* This contains any hard registers that are used in newpat; reg_dead_at_p
186 must consider all these registers to be always live. */
188 static HARD_REG_SET newpat_used_regs
;
190 /* This is an insn to which a LOG_LINKS entry has been added. If this
191 insn is the earlier than I2 or I3, combine should rescan starting at
194 static rtx added_links_insn
;
196 /* Basic block in which we are performing combines. */
197 static basic_block this_basic_block
;
199 /* A bitmap indicating which blocks had registers go dead at entry.
200 After combine, we'll need to re-do global life analysis with
201 those blocks as starting points. */
202 static sbitmap refresh_blocks
;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if an
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to nonzero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is nonzero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set nonzero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx
*reg_last_set_value
;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label
;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick
;
262 /* Set nonzero if references to register n in expressions should not be
265 static char *reg_last_set_invalid
;
267 /* Incremented for each label. */
269 static int label_tick
;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode
;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies
;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid
;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode
*reg_last_set_mode
;
306 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
307 static char *reg_last_set_sign_bit_copies
;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r
; int i
;} old_contents
;
318 union {rtx
*r
; int *i
;} where
;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf
;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences
;
341 static void do_SUBST (rtx
*, rtx
);
342 static void do_SUBST_INT (int *, int);
343 static void init_reg_last_arrays (void);
344 static void setup_incoming_promotions (void);
345 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
346 static int cant_combine_insn_p (rtx
);
347 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
348 static int sets_function_arg_p (rtx
);
349 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
350 static int contains_muldiv (rtx
);
351 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
352 static void undo_all (void);
353 static void undo_commit (void);
354 static rtx
*find_split_point (rtx
*, rtx
);
355 static rtx
subst (rtx
, rtx
, rtx
, int, int);
356 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
357 static rtx
simplify_if_then_else (rtx
);
358 static rtx
simplify_set (rtx
);
359 static rtx
simplify_logical (rtx
, int);
360 static rtx
expand_compound_operation (rtx
);
361 static rtx
expand_field_assignment (rtx
);
362 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
363 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
364 static rtx
extract_left_shift (rtx
, int);
365 static rtx
make_compound_operation (rtx
, enum rtx_code
);
366 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
367 unsigned HOST_WIDE_INT
*);
368 static rtx
force_to_mode (rtx
, enum machine_mode
,
369 unsigned HOST_WIDE_INT
, rtx
, int);
370 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
371 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
372 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
373 static rtx
make_field_assignment (rtx
);
374 static rtx
apply_distributive_law (rtx
);
375 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
376 unsigned HOST_WIDE_INT
);
377 static unsigned HOST_WIDE_INT
cached_nonzero_bits (rtx
, enum machine_mode
,
378 rtx
, enum machine_mode
,
379 unsigned HOST_WIDE_INT
);
380 static unsigned HOST_WIDE_INT
nonzero_bits1 (rtx
, enum machine_mode
, rtx
,
382 unsigned HOST_WIDE_INT
);
383 static unsigned int cached_num_sign_bit_copies (rtx
, enum machine_mode
, rtx
,
386 static unsigned int num_sign_bit_copies1 (rtx
, enum machine_mode
, rtx
,
387 enum machine_mode
, unsigned int);
388 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
389 HOST_WIDE_INT
, enum machine_mode
, int *);
390 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
392 static int recog_for_combine (rtx
*, rtx
, rtx
*);
393 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
394 static rtx
gen_binary (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
395 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
396 static void update_table_tick (rtx
);
397 static void record_value_for_reg (rtx
, rtx
, rtx
);
398 static void check_promoted_subreg (rtx
, rtx
);
399 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
400 static void record_dead_and_set_regs (rtx
);
401 static int get_last_value_validate (rtx
*, rtx
, int, int);
402 static rtx
get_last_value (rtx
);
403 static int use_crosses_set_p (rtx
, int);
404 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
405 static int reg_dead_at_p (rtx
, rtx
);
406 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
407 static int reg_bitfield_target_p (rtx
, rtx
);
408 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
409 static void distribute_links (rtx
);
410 static void mark_used_regs_combine (rtx
);
411 static int insn_cuid (rtx
);
412 static void record_promoted_value (rtx
, rtx
);
413 static rtx
reversed_comparison (rtx
, enum machine_mode
, rtx
, rtx
);
414 static enum rtx_code
combine_reversed_comparison_code (rtx
);
416 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
417 insn. The substitution can be undone by undo_all. If INTO is already
418 set to NEWVAL, do not record this change. Because computing NEWVAL might
419 also call SUBST, we have to compute it before we put anything into
423 do_SUBST (rtx
*into
, rtx newval
)
428 if (oldval
== newval
)
431 /* We'd like to catch as many invalid transformations here as
432 possible. Unfortunately, there are way too many mode changes
433 that are perfectly valid, so we'd waste too much effort for
434 little gain doing the checks here. Focus on catching invalid
435 transformations involving integer constants. */
436 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
437 && GET_CODE (newval
) == CONST_INT
)
439 /* Sanity check that we're replacing oldval with a CONST_INT
440 that is a valid sign-extension for the original mode. */
441 if (INTVAL (newval
) != trunc_int_for_mode (INTVAL (newval
),
445 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
446 CONST_INT is not valid, because after the replacement, the
447 original mode would be gone. Unfortunately, we can't tell
448 when do_SUBST is called to replace the operand thereof, so we
449 perform this test on oldval instead, checking whether an
450 invalid replacement took place before we got here. */
451 if ((GET_CODE (oldval
) == SUBREG
452 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
)
453 || (GET_CODE (oldval
) == ZERO_EXTEND
454 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
))
459 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
461 buf
= xmalloc (sizeof (struct undo
));
465 buf
->old_contents
.r
= oldval
;
468 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
471 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
473 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
474 for the value of a HOST_WIDE_INT value (including CONST_INT) is
478 do_SUBST_INT (int *into
, int newval
)
483 if (oldval
== newval
)
487 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
489 buf
= xmalloc (sizeof (struct undo
));
493 buf
->old_contents
.i
= oldval
;
496 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
499 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
501 /* Main entry point for combiner. F is the first insn of the function.
502 NREGS is the first unused pseudo-reg number.
504 Return nonzero if the combiner has turned an indirect jump
505 instruction into a direct jump. */
507 combine_instructions (rtx f
, unsigned int nregs
)
514 rtx links
, nextlinks
;
516 int new_direct_jump_p
= 0;
518 combine_attempts
= 0;
521 combine_successes
= 0;
523 combine_max_regno
= nregs
;
525 reg_nonzero_bits
= xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
));
526 reg_sign_bit_copies
= xcalloc (nregs
, sizeof (unsigned char));
528 reg_last_death
= xmalloc (nregs
* sizeof (rtx
));
529 reg_last_set
= xmalloc (nregs
* sizeof (rtx
));
530 reg_last_set_value
= xmalloc (nregs
* sizeof (rtx
));
531 reg_last_set_table_tick
= xmalloc (nregs
* sizeof (int));
532 reg_last_set_label
= xmalloc (nregs
* sizeof (int));
533 reg_last_set_invalid
= xmalloc (nregs
* sizeof (char));
534 reg_last_set_mode
= xmalloc (nregs
* sizeof (enum machine_mode
));
535 reg_last_set_nonzero_bits
= xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
536 reg_last_set_sign_bit_copies
= xmalloc (nregs
* sizeof (char));
538 init_reg_last_arrays ();
540 init_recog_no_volatile ();
542 /* Compute maximum uid value so uid_cuid can be allocated. */
544 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
545 if (INSN_UID (insn
) > i
)
548 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
551 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
553 /* Don't use reg_nonzero_bits when computing it. This can cause problems
554 when, for example, we have j <<= 1 in a loop. */
556 nonzero_sign_valid
= 0;
558 /* Compute the mapping from uids to cuids.
559 Cuids are numbers assigned to insns, like uids,
560 except that cuids increase monotonically through the code.
562 Scan all SETs and see if we can deduce anything about what
563 bits are known to be zero for some registers and how many copies
564 of the sign bit are known to exist for those registers.
566 Also set any known values so that we can use it while searching
567 for what bits are known to be set. */
571 setup_incoming_promotions ();
573 refresh_blocks
= sbitmap_alloc (last_basic_block
);
574 sbitmap_zero (refresh_blocks
);
576 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
578 uid_cuid
[INSN_UID (insn
)] = ++i
;
584 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
586 record_dead_and_set_regs (insn
);
589 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
590 if (REG_NOTE_KIND (links
) == REG_INC
)
591 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
596 if (GET_CODE (insn
) == CODE_LABEL
)
600 nonzero_sign_valid
= 1;
602 /* Now scan all the insns in forward order. */
607 init_reg_last_arrays ();
608 setup_incoming_promotions ();
610 FOR_EACH_BB (this_basic_block
)
612 for (insn
= this_basic_block
->head
;
613 insn
!= NEXT_INSN (this_basic_block
->end
);
614 insn
= next
? next
: NEXT_INSN (insn
))
618 if (GET_CODE (insn
) == CODE_LABEL
)
621 else if (INSN_P (insn
))
623 /* See if we know about function return values before this
624 insn based upon SUBREG flags. */
625 check_promoted_subreg (insn
, PATTERN (insn
));
627 /* Try this insn with each insn it links back to. */
629 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
630 if ((next
= try_combine (insn
, XEXP (links
, 0),
631 NULL_RTX
, &new_direct_jump_p
)) != 0)
634 /* Try each sequence of three linked insns ending with this one. */
636 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
638 rtx link
= XEXP (links
, 0);
640 /* If the linked insn has been replaced by a note, then there
641 is no point in pursuing this chain any further. */
642 if (GET_CODE (link
) == NOTE
)
645 for (nextlinks
= LOG_LINKS (link
);
647 nextlinks
= XEXP (nextlinks
, 1))
648 if ((next
= try_combine (insn
, link
,
650 &new_direct_jump_p
)) != 0)
655 /* Try to combine a jump insn that uses CC0
656 with a preceding insn that sets CC0, and maybe with its
657 logical predecessor as well.
658 This is how we make decrement-and-branch insns.
659 We need this special code because data flow connections
660 via CC0 do not get entered in LOG_LINKS. */
662 if (GET_CODE (insn
) == JUMP_INSN
663 && (prev
= prev_nonnote_insn (insn
)) != 0
664 && GET_CODE (prev
) == INSN
665 && sets_cc0_p (PATTERN (prev
)))
667 if ((next
= try_combine (insn
, prev
,
668 NULL_RTX
, &new_direct_jump_p
)) != 0)
671 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
672 nextlinks
= XEXP (nextlinks
, 1))
673 if ((next
= try_combine (insn
, prev
,
675 &new_direct_jump_p
)) != 0)
679 /* Do the same for an insn that explicitly references CC0. */
680 if (GET_CODE (insn
) == INSN
681 && (prev
= prev_nonnote_insn (insn
)) != 0
682 && GET_CODE (prev
) == INSN
683 && sets_cc0_p (PATTERN (prev
))
684 && GET_CODE (PATTERN (insn
)) == SET
685 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
687 if ((next
= try_combine (insn
, prev
,
688 NULL_RTX
, &new_direct_jump_p
)) != 0)
691 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
692 nextlinks
= XEXP (nextlinks
, 1))
693 if ((next
= try_combine (insn
, prev
,
695 &new_direct_jump_p
)) != 0)
699 /* Finally, see if any of the insns that this insn links to
700 explicitly references CC0. If so, try this insn, that insn,
701 and its predecessor if it sets CC0. */
702 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
703 if (GET_CODE (XEXP (links
, 0)) == INSN
704 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
705 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
706 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
707 && GET_CODE (prev
) == INSN
708 && sets_cc0_p (PATTERN (prev
))
709 && (next
= try_combine (insn
, XEXP (links
, 0),
710 prev
, &new_direct_jump_p
)) != 0)
714 /* Try combining an insn with two different insns whose results it
716 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
717 for (nextlinks
= XEXP (links
, 1); nextlinks
;
718 nextlinks
= XEXP (nextlinks
, 1))
719 if ((next
= try_combine (insn
, XEXP (links
, 0),
721 &new_direct_jump_p
)) != 0)
724 if (GET_CODE (insn
) != NOTE
)
725 record_dead_and_set_regs (insn
);
734 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
735 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
736 new_direct_jump_p
|= purge_all_dead_edges (0);
737 delete_noop_moves (f
);
739 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
740 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
741 | PROP_KILL_DEAD_CODE
);
744 sbitmap_free (refresh_blocks
);
745 free (reg_nonzero_bits
);
746 free (reg_sign_bit_copies
);
747 free (reg_last_death
);
749 free (reg_last_set_value
);
750 free (reg_last_set_table_tick
);
751 free (reg_last_set_label
);
752 free (reg_last_set_invalid
);
753 free (reg_last_set_mode
);
754 free (reg_last_set_nonzero_bits
);
755 free (reg_last_set_sign_bit_copies
);
759 struct undo
*undo
, *next
;
760 for (undo
= undobuf
.frees
; undo
; undo
= next
)
768 total_attempts
+= combine_attempts
;
769 total_merges
+= combine_merges
;
770 total_extras
+= combine_extras
;
771 total_successes
+= combine_successes
;
773 nonzero_sign_valid
= 0;
775 /* Make recognizer allow volatile MEMs again. */
778 return new_direct_jump_p
;
781 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
784 init_reg_last_arrays (void)
786 unsigned int nregs
= combine_max_regno
;
788 memset (reg_last_death
, 0, nregs
* sizeof (rtx
));
789 memset (reg_last_set
, 0, nregs
* sizeof (rtx
));
790 memset (reg_last_set_value
, 0, nregs
* sizeof (rtx
));
791 memset (reg_last_set_table_tick
, 0, nregs
* sizeof (int));
792 memset (reg_last_set_label
, 0, nregs
* sizeof (int));
793 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
794 memset (reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
795 memset (reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
796 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
799 /* Set up any promoted values for incoming argument registers. */
802 setup_incoming_promotions (void)
806 enum machine_mode mode
;
808 rtx first
= get_insns ();
810 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
812 #ifndef OUTGOING_REGNO
813 #define OUTGOING_REGNO(N) N
815 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
816 /* Check whether this register can hold an incoming pointer
817 argument. FUNCTION_ARG_REGNO_P tests outgoing register
818 numbers, so translate if necessary due to register windows. */
819 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
820 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
823 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
826 gen_rtx_CLOBBER (mode
, const0_rtx
)));
831 /* Called via note_stores. If X is a pseudo that is narrower than
832 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
834 If we are setting only a portion of X and we can't figure out what
835 portion, assume all bits will be used since we don't know what will
838 Similarly, set how many bits of X are known to be copies of the sign bit
839 at all locations in the function. This is the smallest number implied
843 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
844 void *data ATTRIBUTE_UNUSED
)
848 if (GET_CODE (x
) == REG
849 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
850 /* If this register is undefined at the start of the file, we can't
851 say what its contents were. */
852 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
853 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
855 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
857 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
858 reg_sign_bit_copies
[REGNO (x
)] = 1;
862 /* If this is a complex assignment, see if we can convert it into a
863 simple assignment. */
864 set
= expand_field_assignment (set
);
866 /* If this is a simple assignment, or we have a paradoxical SUBREG,
867 set what we know about X. */
869 if (SET_DEST (set
) == x
870 || (GET_CODE (SET_DEST (set
)) == SUBREG
871 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
872 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
873 && SUBREG_REG (SET_DEST (set
)) == x
))
875 rtx src
= SET_SRC (set
);
877 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
878 /* If X is narrower than a word and SRC is a non-negative
879 constant that would appear negative in the mode of X,
880 sign-extend it for use in reg_nonzero_bits because some
881 machines (maybe most) will actually do the sign-extension
882 and this is the conservative approach.
884 ??? For 2.5, try to tighten up the MD files in this regard
885 instead of this kludge. */
887 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
888 && GET_CODE (src
) == CONST_INT
890 && 0 != (INTVAL (src
)
892 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
893 src
= GEN_INT (INTVAL (src
)
894 | ((HOST_WIDE_INT
) (-1)
895 << GET_MODE_BITSIZE (GET_MODE (x
))));
898 /* Don't call nonzero_bits if it cannot change anything. */
899 if (reg_nonzero_bits
[REGNO (x
)] != ~(unsigned HOST_WIDE_INT
) 0)
900 reg_nonzero_bits
[REGNO (x
)]
901 |= nonzero_bits (src
, nonzero_bits_mode
);
902 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
903 if (reg_sign_bit_copies
[REGNO (x
)] == 0
904 || reg_sign_bit_copies
[REGNO (x
)] > num
)
905 reg_sign_bit_copies
[REGNO (x
)] = num
;
909 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
910 reg_sign_bit_copies
[REGNO (x
)] = 1;
915 /* See if INSN can be combined into I3. PRED and SUCC are optionally
916 insns that were previously combined into I3 or that will be combined
917 into the merger of INSN and I3.
919 Return 0 if the combination is not allowed for any reason.
921 If the combination is allowed, *PDEST will be set to the single
922 destination of INSN and *PSRC to the single source, and this function
926 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
927 rtx
*pdest
, rtx
*psrc
)
930 rtx set
= 0, src
, dest
;
935 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
936 && next_active_insn (succ
) == i3
)
937 : next_active_insn (insn
) == i3
);
939 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
940 or a PARALLEL consisting of such a SET and CLOBBERs.
942 If INSN has CLOBBER parallel parts, ignore them for our processing.
943 By definition, these happen during the execution of the insn. When it
944 is merged with another insn, all bets are off. If they are, in fact,
945 needed and aren't also supplied in I3, they may be added by
946 recog_for_combine. Otherwise, it won't match.
948 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
951 Get the source and destination of INSN. If more than one, can't
954 if (GET_CODE (PATTERN (insn
)) == SET
)
955 set
= PATTERN (insn
);
956 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
957 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
959 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
961 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
963 switch (GET_CODE (elt
))
965 /* This is important to combine floating point insns
968 /* Combining an isolated USE doesn't make sense.
969 We depend here on combinable_i3pat to reject them. */
970 /* The code below this loop only verifies that the inputs of
971 the SET in INSN do not change. We call reg_set_between_p
972 to verify that the REG in the USE does not change between
974 If the USE in INSN was for a pseudo register, the matching
975 insn pattern will likely match any register; combining this
976 with any other USE would only be safe if we knew that the
977 used registers have identical values, or if there was
978 something to tell them apart, e.g. different modes. For
979 now, we forgo such complicated tests and simply disallow
980 combining of USES of pseudo registers with any other USE. */
981 if (GET_CODE (XEXP (elt
, 0)) == REG
982 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
984 rtx i3pat
= PATTERN (i3
);
985 int i
= XVECLEN (i3pat
, 0) - 1;
986 unsigned int regno
= REGNO (XEXP (elt
, 0));
990 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
992 if (GET_CODE (i3elt
) == USE
993 && GET_CODE (XEXP (i3elt
, 0)) == REG
994 && (REGNO (XEXP (i3elt
, 0)) == regno
995 ? reg_set_between_p (XEXP (elt
, 0),
996 PREV_INSN (insn
), i3
)
997 : regno
>= FIRST_PSEUDO_REGISTER
))
1004 /* We can ignore CLOBBERs. */
1009 /* Ignore SETs whose result isn't used but not those that
1010 have side-effects. */
1011 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1012 && ! side_effects_p (elt
))
1015 /* If we have already found a SET, this is a second one and
1016 so we cannot combine with this insn. */
1024 /* Anything else means we can't combine. */
1030 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1031 so don't do anything with it. */
1032 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1041 set
= expand_field_assignment (set
);
1042 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1044 /* Don't eliminate a store in the stack pointer. */
1045 if (dest
== stack_pointer_rtx
1046 /* Don't combine with an insn that sets a register to itself if it has
1047 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1048 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1049 /* Can't merge an ASM_OPERANDS. */
1050 || GET_CODE (src
) == ASM_OPERANDS
1051 /* Can't merge a function call. */
1052 || GET_CODE (src
) == CALL
1053 /* Don't eliminate a function call argument. */
1054 || (GET_CODE (i3
) == CALL_INSN
1055 && (find_reg_fusage (i3
, USE
, dest
)
1056 || (GET_CODE (dest
) == REG
1057 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1058 && global_regs
[REGNO (dest
)])))
1059 /* Don't substitute into an incremented register. */
1060 || FIND_REG_INC_NOTE (i3
, dest
)
1061 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1063 /* Don't combine the end of a libcall into anything. */
1064 /* ??? This gives worse code, and appears to be unnecessary, since no
1065 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1066 use REG_RETVAL notes for noconflict blocks, but other code here
1067 makes sure that those insns don't disappear. */
1068 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1070 /* Make sure that DEST is not used after SUCC but before I3. */
1071 || (succ
&& ! all_adjacent
1072 && reg_used_between_p (dest
, succ
, i3
))
1073 /* Make sure that the value that is to be substituted for the register
1074 does not use any registers whose values alter in between. However,
1075 If the insns are adjacent, a use can't cross a set even though we
1076 think it might (this can happen for a sequence of insns each setting
1077 the same destination; reg_last_set of that register might point to
1078 a NOTE). If INSN has a REG_EQUIV note, the register is always
1079 equivalent to the memory so the substitution is valid even if there
1080 are intervening stores. Also, don't move a volatile asm or
1081 UNSPEC_VOLATILE across any other insns. */
1083 && (((GET_CODE (src
) != MEM
1084 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1085 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1086 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1087 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1088 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1089 better register allocation by not doing the combine. */
1090 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1091 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1092 /* Don't combine across a CALL_INSN, because that would possibly
1093 change whether the life span of some REGs crosses calls or not,
1094 and it is a pain to update that information.
1095 Exception: if source is a constant, moving it later can't hurt.
1096 Accept that special case, because it helps -fforce-addr a lot. */
1097 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1100 /* DEST must either be a REG or CC0. */
1101 if (GET_CODE (dest
) == REG
)
1103 /* If register alignment is being enforced for multi-word items in all
1104 cases except for parameters, it is possible to have a register copy
1105 insn referencing a hard register that is not allowed to contain the
1106 mode being copied and which would not be valid as an operand of most
1107 insns. Eliminate this problem by not combining with such an insn.
1109 Also, on some machines we don't want to extend the life of a hard
1112 if (GET_CODE (src
) == REG
1113 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1114 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1115 /* Don't extend the life of a hard register unless it is
1116 user variable (if we have few registers) or it can't
1117 fit into the desired register (meaning something special
1119 Also avoid substituting a return register into I3, because
1120 reload can't handle a conflict with constraints of other
1122 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1123 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1126 else if (GET_CODE (dest
) != CC0
)
1129 /* Don't substitute for a register intended as a clobberable operand.
1130 Similarly, don't substitute an expression containing a register that
1131 will be clobbered in I3. */
1132 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1133 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1134 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1135 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1137 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1140 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1141 or not), reject, unless nothing volatile comes between it and I3 */
1143 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1145 /* Make sure succ doesn't contain a volatile reference. */
1146 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1149 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1150 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1154 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1155 to be an explicit register variable, and was chosen for a reason. */
1157 if (GET_CODE (src
) == ASM_OPERANDS
1158 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1161 /* If there are any volatile insns between INSN and I3, reject, because
1162 they might affect machine state. */
1164 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1165 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1168 /* If INSN or I2 contains an autoincrement or autodecrement,
1169 make sure that register is not used between there and I3,
1170 and not already used in I3 either.
1171 Also insist that I3 not be a jump; if it were one
1172 and the incremented register were spilled, we would lose. */
1175 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1176 if (REG_NOTE_KIND (link
) == REG_INC
1177 && (GET_CODE (i3
) == JUMP_INSN
1178 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1179 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1184 /* Don't combine an insn that follows a CC0-setting insn.
1185 An insn that uses CC0 must not be separated from the one that sets it.
1186 We do, however, allow I2 to follow a CC0-setting insn if that insn
1187 is passed as I1; in that case it will be deleted also.
1188 We also allow combining in this case if all the insns are adjacent
1189 because that would leave the two CC0 insns adjacent as well.
1190 It would be more logical to test whether CC0 occurs inside I1 or I2,
1191 but that would be much slower, and this ought to be equivalent. */
1193 p
= prev_nonnote_insn (insn
);
1194 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1199 /* If we get here, we have passed all the tests and the combination is
1208 /* Check if PAT is an insn - or a part of it - used to set up an
1209 argument for a function in a hard register. */
1212 sets_function_arg_p (rtx pat
)
1217 switch (GET_CODE (pat
))
1220 return sets_function_arg_p (PATTERN (pat
));
1223 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1224 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1230 inner_dest
= SET_DEST (pat
);
1231 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1232 || GET_CODE (inner_dest
) == SUBREG
1233 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1234 inner_dest
= XEXP (inner_dest
, 0);
1236 return (GET_CODE (inner_dest
) == REG
1237 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1238 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1247 /* LOC is the location within I3 that contains its pattern or the component
1248 of a PARALLEL of the pattern. We validate that it is valid for combining.
1250 One problem is if I3 modifies its output, as opposed to replacing it
1251 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1252 so would produce an insn that is not equivalent to the original insns.
1256 (set (reg:DI 101) (reg:DI 100))
1257 (set (subreg:SI (reg:DI 101) 0) <foo>)
1259 This is NOT equivalent to:
1261 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1262 (set (reg:DI 101) (reg:DI 100))])
1264 Not only does this modify 100 (in which case it might still be valid
1265 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1267 We can also run into a problem if I2 sets a register that I1
1268 uses and I1 gets directly substituted into I3 (not via I2). In that
1269 case, we would be getting the wrong value of I2DEST into I3, so we
1270 must reject the combination. This case occurs when I2 and I1 both
1271 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1272 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1273 of a SET must prevent combination from occurring.
1275 Before doing the above check, we first try to expand a field assignment
1276 into a set of logical operations.
1278 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1279 we place a register that is both set and used within I3. If more than one
1280 such register is detected, we fail.
1282 Return 1 if the combination is valid, zero otherwise. */
1285 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1286 int i1_not_in_src
, rtx
*pi3dest_killed
)
1290 if (GET_CODE (x
) == SET
)
1293 rtx dest
= SET_DEST (set
);
1294 rtx src
= SET_SRC (set
);
1295 rtx inner_dest
= dest
;
1297 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1298 || GET_CODE (inner_dest
) == SUBREG
1299 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1300 inner_dest
= XEXP (inner_dest
, 0);
1302 /* Check for the case where I3 modifies its output, as discussed
1303 above. We don't want to prevent pseudos from being combined
1304 into the address of a MEM, so only prevent the combination if
1305 i1 or i2 set the same MEM. */
1306 if ((inner_dest
!= dest
&&
1307 (GET_CODE (inner_dest
) != MEM
1308 || rtx_equal_p (i2dest
, inner_dest
)
1309 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1310 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1311 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1313 /* This is the same test done in can_combine_p except we can't test
1314 all_adjacent; we don't have to, since this instruction will stay
1315 in place, thus we are not considering increasing the lifetime of
1318 Also, if this insn sets a function argument, combining it with
1319 something that might need a spill could clobber a previous
1320 function argument; the all_adjacent test in can_combine_p also
1321 checks this; here, we do a more specific test for this case. */
1323 || (GET_CODE (inner_dest
) == REG
1324 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1325 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1326 GET_MODE (inner_dest
))))
1327 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1330 /* If DEST is used in I3, it is being killed in this insn,
1331 so record that for later.
1332 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1333 STACK_POINTER_REGNUM, since these are always considered to be
1334 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1335 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1336 && reg_referenced_p (dest
, PATTERN (i3
))
1337 && REGNO (dest
) != FRAME_POINTER_REGNUM
1338 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1339 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1341 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1342 && (REGNO (dest
) != ARG_POINTER_REGNUM
1343 || ! fixed_regs
[REGNO (dest
)])
1345 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1347 if (*pi3dest_killed
)
1350 *pi3dest_killed
= dest
;
1354 else if (GET_CODE (x
) == PARALLEL
)
1358 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1359 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1360 i1_not_in_src
, pi3dest_killed
))
1367 /* Return 1 if X is an arithmetic expression that contains a multiplication
1368 and division. We don't count multiplications by powers of two here. */
1371 contains_muldiv (rtx x
)
1373 switch (GET_CODE (x
))
1375 case MOD
: case DIV
: case UMOD
: case UDIV
:
1379 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1380 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1382 switch (GET_RTX_CLASS (GET_CODE (x
)))
1384 case 'c': case '<': case '2':
1385 return contains_muldiv (XEXP (x
, 0))
1386 || contains_muldiv (XEXP (x
, 1));
1389 return contains_muldiv (XEXP (x
, 0));
1397 /* Determine whether INSN can be used in a combination. Return nonzero if
1398 not. This is used in try_combine to detect early some cases where we
1399 can't perform combinations. */
1402 cant_combine_insn_p (rtx insn
)
1407 /* If this isn't really an insn, we can't do anything.
1408 This can occur when flow deletes an insn that it has merged into an
1409 auto-increment address. */
1410 if (! INSN_P (insn
))
1413 /* Never combine loads and stores involving hard regs that are likely
1414 to be spilled. The register allocator can usually handle such
1415 reg-reg moves by tying. If we allow the combiner to make
1416 substitutions of likely-spilled regs, we may abort in reload.
1417 As an exception, we allow combinations involving fixed regs; these are
1418 not available to the register allocator so there's no risk involved. */
1420 set
= single_set (insn
);
1423 src
= SET_SRC (set
);
1424 dest
= SET_DEST (set
);
1425 if (GET_CODE (src
) == SUBREG
)
1426 src
= SUBREG_REG (src
);
1427 if (GET_CODE (dest
) == SUBREG
)
1428 dest
= SUBREG_REG (dest
);
1429 if (REG_P (src
) && REG_P (dest
)
1430 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1431 && ! fixed_regs
[REGNO (src
)]
1432 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1433 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1434 && ! fixed_regs
[REGNO (dest
)]
1435 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1441 /* Adjust INSN after we made a change to its destination.
1443 Changing the destination can invalidate notes that say something about
1444 the results of the insn and a LOG_LINK pointing to the insn. */
1447 adjust_for_new_dest (rtx insn
)
1451 /* For notes, be conservative and simply remove them. */
1452 loc
= ®_NOTES (insn
);
1455 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1456 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1457 *loc
= XEXP (*loc
, 1);
1459 loc
= &XEXP (*loc
, 1);
1462 /* The new insn will have a destination that was previously the destination
1463 of an insn just above it. Call distribute_links to make a LOG_LINK from
1464 the next use of that destination. */
1465 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1468 /* Try to combine the insns I1 and I2 into I3.
1469 Here I1 and I2 appear earlier than I3.
1470 I1 can be zero; then we combine just I2 into I3.
1472 If we are combining three insns and the resulting insn is not recognized,
1473 try splitting it into two insns. If that happens, I2 and I3 are retained
1474 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1477 Return 0 if the combination does not work. Then nothing is changed.
1478 If we did the combination, return the insn at which combine should
1481 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1482 new direct jump instruction. */
1485 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1487 /* New patterns for I3 and I2, respectively. */
1488 rtx newpat
, newi2pat
= 0;
1489 int substed_i2
= 0, substed_i1
= 0;
1490 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1491 int added_sets_1
, added_sets_2
;
1492 /* Total number of SETs to put into I3. */
1494 /* Nonzero is I2's body now appears in I3. */
1496 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1497 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1498 /* Contains I3 if the destination of I3 is used in its source, which means
1499 that the old life of I3 is being killed. If that usage is placed into
1500 I2 and not in I3, a REG_DEAD note must be made. */
1501 rtx i3dest_killed
= 0;
1502 /* SET_DEST and SET_SRC of I2 and I1. */
1503 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1504 /* PATTERN (I2), or a copy of it in certain cases. */
1506 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1507 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1508 int i1_feeds_i3
= 0;
1509 /* Notes that must be added to REG_NOTES in I3 and I2. */
1510 rtx new_i3_notes
, new_i2_notes
;
1511 /* Notes that we substituted I3 into I2 instead of the normal case. */
1512 int i3_subst_into_i2
= 0;
1513 /* Notes that I1, I2 or I3 is a MULT operation. */
1521 /* Exit early if one of the insns involved can't be used for
1523 if (cant_combine_insn_p (i3
)
1524 || cant_combine_insn_p (i2
)
1525 || (i1
&& cant_combine_insn_p (i1
))
1526 /* We also can't do anything if I3 has a
1527 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1530 /* ??? This gives worse code, and appears to be unnecessary, since no
1531 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1532 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1538 undobuf
.other_insn
= 0;
1540 /* Reset the hard register usage information. */
1541 CLEAR_HARD_REG_SET (newpat_used_regs
);
1543 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1544 code below, set I1 to be the earlier of the two insns. */
1545 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1546 temp
= i1
, i1
= i2
, i2
= temp
;
1548 added_links_insn
= 0;
1550 /* First check for one important special-case that the code below will
1551 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1552 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1553 we may be able to replace that destination with the destination of I3.
1554 This occurs in the common code where we compute both a quotient and
1555 remainder into a structure, in which case we want to do the computation
1556 directly into the structure to avoid register-register copies.
1558 Note that this case handles both multiple sets in I2 and also
1559 cases where I2 has a number of CLOBBER or PARALLELs.
1561 We make very conservative checks below and only try to handle the
1562 most common cases of this. For example, we only handle the case
1563 where I2 and I3 are adjacent to avoid making difficult register
1566 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1567 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1568 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1569 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1570 && GET_CODE (PATTERN (i2
)) == PARALLEL
1571 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1572 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1573 below would need to check what is inside (and reg_overlap_mentioned_p
1574 doesn't support those codes anyway). Don't allow those destinations;
1575 the resulting insn isn't likely to be recognized anyway. */
1576 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1577 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1578 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1579 SET_DEST (PATTERN (i3
)))
1580 && next_real_insn (i2
) == i3
)
1582 rtx p2
= PATTERN (i2
);
1584 /* Make sure that the destination of I3,
1585 which we are going to substitute into one output of I2,
1586 is not used within another output of I2. We must avoid making this:
1587 (parallel [(set (mem (reg 69)) ...)
1588 (set (reg 69) ...)])
1589 which is not well-defined as to order of actions.
1590 (Besides, reload can't handle output reloads for this.)
1592 The problem can also happen if the dest of I3 is a memory ref,
1593 if another dest in I2 is an indirect memory ref. */
1594 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1595 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1596 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1597 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1598 SET_DEST (XVECEXP (p2
, 0, i
))))
1601 if (i
== XVECLEN (p2
, 0))
1602 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1603 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1604 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1605 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1610 subst_low_cuid
= INSN_CUID (i2
);
1612 added_sets_2
= added_sets_1
= 0;
1613 i2dest
= SET_SRC (PATTERN (i3
));
1615 /* Replace the dest in I2 with our dest and make the resulting
1616 insn the new pattern for I3. Then skip to where we
1617 validate the pattern. Everything was set up above. */
1618 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1619 SET_DEST (PATTERN (i3
)));
1622 i3_subst_into_i2
= 1;
1623 goto validate_replacement
;
1627 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1628 one of those words to another constant, merge them by making a new
1631 && (temp
= single_set (i2
)) != 0
1632 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1633 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1634 && GET_CODE (SET_DEST (temp
)) == REG
1635 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1636 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1637 && GET_CODE (PATTERN (i3
)) == SET
1638 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1639 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1640 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1641 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1642 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1644 HOST_WIDE_INT lo
, hi
;
1646 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1647 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1650 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1651 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1654 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1656 /* We don't handle the case of the target word being wider
1657 than a host wide int. */
1658 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1661 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1662 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1663 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1665 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1666 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1667 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1669 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1670 >> (HOST_BITS_PER_WIDE_INT
- 1));
1672 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1673 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1674 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1675 (INTVAL (SET_SRC (PATTERN (i3
)))));
1677 hi
= lo
< 0 ? -1 : 0;
1680 /* We don't handle the case of the higher word not fitting
1681 entirely in either hi or lo. */
1686 subst_low_cuid
= INSN_CUID (i2
);
1687 added_sets_2
= added_sets_1
= 0;
1688 i2dest
= SET_DEST (temp
);
1690 SUBST (SET_SRC (temp
),
1691 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1693 newpat
= PATTERN (i2
);
1694 goto validate_replacement
;
1698 /* If we have no I1 and I2 looks like:
1699 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1701 make up a dummy I1 that is
1704 (set (reg:CC X) (compare:CC Y (const_int 0)))
1706 (We can ignore any trailing CLOBBERs.)
1708 This undoes a previous combination and allows us to match a branch-and-
1711 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1712 && XVECLEN (PATTERN (i2
), 0) >= 2
1713 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1714 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1716 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1717 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1718 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1719 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1720 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1721 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1723 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1724 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1729 /* We make I1 with the same INSN_UID as I2. This gives it
1730 the same INSN_CUID for value tracking. Our fake I1 will
1731 never appear in the insn stream so giving it the same INSN_UID
1732 as I2 will not cause a problem. */
1734 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1735 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1736 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1739 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1740 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1741 SET_DEST (PATTERN (i1
)));
1746 /* Verify that I2 and I1 are valid for combining. */
1747 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1748 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1754 /* Record whether I2DEST is used in I2SRC and similarly for the other
1755 cases. Knowing this will help in register status updating below. */
1756 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1757 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1758 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1760 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1762 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1764 /* Ensure that I3's pattern can be the destination of combines. */
1765 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1766 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1773 /* See if any of the insns is a MULT operation. Unless one is, we will
1774 reject a combination that is, since it must be slower. Be conservative
1776 if (GET_CODE (i2src
) == MULT
1777 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1778 || (GET_CODE (PATTERN (i3
)) == SET
1779 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1782 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1783 We used to do this EXCEPT in one case: I3 has a post-inc in an
1784 output operand. However, that exception can give rise to insns like
1786 which is a famous insn on the PDP-11 where the value of r3 used as the
1787 source was model-dependent. Avoid this sort of thing. */
1790 if (!(GET_CODE (PATTERN (i3
)) == SET
1791 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1792 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1793 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1794 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1795 /* It's not the exception. */
1798 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1799 if (REG_NOTE_KIND (link
) == REG_INC
1800 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1802 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1809 /* See if the SETs in I1 or I2 need to be kept around in the merged
1810 instruction: whenever the value set there is still needed past I3.
1811 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1813 For the SET in I1, we have two cases: If I1 and I2 independently
1814 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1815 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1816 in I1 needs to be kept around unless I1DEST dies or is set in either
1817 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1818 I1DEST. If so, we know I1 feeds into I2. */
1820 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1823 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1824 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1826 /* If the set in I2 needs to be kept around, we must make a copy of
1827 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1828 PATTERN (I2), we are only substituting for the original I1DEST, not into
1829 an already-substituted copy. This also prevents making self-referential
1830 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1833 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1834 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1838 i2pat
= copy_rtx (i2pat
);
1842 /* Substitute in the latest insn for the regs set by the earlier ones. */
1844 maxreg
= max_reg_num ();
1848 /* It is possible that the source of I2 or I1 may be performing an
1849 unneeded operation, such as a ZERO_EXTEND of something that is known
1850 to have the high part zero. Handle that case by letting subst look at
1851 the innermost one of them.
1853 Another way to do this would be to have a function that tries to
1854 simplify a single insn instead of merging two or more insns. We don't
1855 do this because of the potential of infinite loops and because
1856 of the potential extra memory required. However, doing it the way
1857 we are is a bit of a kludge and doesn't catch all cases.
1859 But only do this if -fexpensive-optimizations since it slows things down
1860 and doesn't usually win. */
1862 if (flag_expensive_optimizations
)
1864 /* Pass pc_rtx so no substitutions are done, just simplifications.
1865 The cases that we are interested in here do not involve the few
1866 cases were is_replaced is checked. */
1869 subst_low_cuid
= INSN_CUID (i1
);
1870 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1874 subst_low_cuid
= INSN_CUID (i2
);
1875 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1880 /* Many machines that don't use CC0 have insns that can both perform an
1881 arithmetic operation and set the condition code. These operations will
1882 be represented as a PARALLEL with the first element of the vector
1883 being a COMPARE of an arithmetic operation with the constant zero.
1884 The second element of the vector will set some pseudo to the result
1885 of the same arithmetic operation. If we simplify the COMPARE, we won't
1886 match such a pattern and so will generate an extra insn. Here we test
1887 for this case, where both the comparison and the operation result are
1888 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1889 I2SRC. Later we will make the PARALLEL that contains I2. */
1891 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1892 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1893 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1894 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1896 #ifdef EXTRA_CC_MODES
1898 enum machine_mode compare_mode
;
1901 newpat
= PATTERN (i3
);
1902 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1906 #ifdef EXTRA_CC_MODES
1907 /* See if a COMPARE with the operand we substituted in should be done
1908 with the mode that is currently being used. If not, do the same
1909 processing we do in `subst' for a SET; namely, if the destination
1910 is used only once, try to replace it with a register of the proper
1911 mode and also replace the COMPARE. */
1912 if (undobuf
.other_insn
== 0
1913 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1914 &undobuf
.other_insn
))
1915 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1917 != GET_MODE (SET_DEST (newpat
))))
1919 unsigned int regno
= REGNO (SET_DEST (newpat
));
1920 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1922 if (regno
< FIRST_PSEUDO_REGISTER
1923 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1924 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1926 if (regno
>= FIRST_PSEUDO_REGISTER
)
1927 SUBST (regno_reg_rtx
[regno
], new_dest
);
1929 SUBST (SET_DEST (newpat
), new_dest
);
1930 SUBST (XEXP (*cc_use
, 0), new_dest
);
1931 SUBST (SET_SRC (newpat
),
1932 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1935 undobuf
.other_insn
= 0;
1942 n_occurrences
= 0; /* `subst' counts here */
1944 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1945 need to make a unique copy of I2SRC each time we substitute it
1946 to avoid self-referential rtl. */
1948 subst_low_cuid
= INSN_CUID (i2
);
1949 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1950 ! i1_feeds_i3
&& i1dest_in_i1src
);
1953 /* Record whether i2's body now appears within i3's body. */
1954 i2_is_used
= n_occurrences
;
1957 /* If we already got a failure, don't try to do more. Otherwise,
1958 try to substitute in I1 if we have it. */
1960 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1962 /* Before we can do this substitution, we must redo the test done
1963 above (see detailed comments there) that ensures that I1DEST
1964 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1966 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1974 subst_low_cuid
= INSN_CUID (i1
);
1975 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1979 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1980 to count all the ways that I2SRC and I1SRC can be used. */
1981 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1982 && i2_is_used
+ added_sets_2
> 1)
1983 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1984 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1986 /* Fail if we tried to make a new register (we used to abort, but there's
1987 really no reason to). */
1988 || max_reg_num () != maxreg
1989 /* Fail if we couldn't do something and have a CLOBBER. */
1990 || GET_CODE (newpat
) == CLOBBER
1991 /* Fail if this new pattern is a MULT and we didn't have one before
1992 at the outer level. */
1993 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2000 /* If the actions of the earlier insns must be kept
2001 in addition to substituting them into the latest one,
2002 we must make a new PARALLEL for the latest insn
2003 to hold additional the SETs. */
2005 if (added_sets_1
|| added_sets_2
)
2009 if (GET_CODE (newpat
) == PARALLEL
)
2011 rtvec old
= XVEC (newpat
, 0);
2012 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2013 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2014 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
2015 sizeof (old
->elem
[0]) * old
->num_elem
);
2020 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2021 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2022 XVECEXP (newpat
, 0, 0) = old
;
2026 XVECEXP (newpat
, 0, --total_sets
)
2027 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2028 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2032 /* If there is no I1, use I2's body as is. We used to also not do
2033 the subst call below if I2 was substituted into I3,
2034 but that could lose a simplification. */
2036 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2038 /* See comment where i2pat is assigned. */
2039 XVECEXP (newpat
, 0, --total_sets
)
2040 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2044 /* We come here when we are replacing a destination in I2 with the
2045 destination of I3. */
2046 validate_replacement
:
2048 /* Note which hard regs this insn has as inputs. */
2049 mark_used_regs_combine (newpat
);
2051 /* Is the result of combination a valid instruction? */
2052 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2054 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2055 the second SET's destination is a register that is unused. In that case,
2056 we just need the first SET. This can occur when simplifying a divmod
2057 insn. We *must* test for this case here because the code below that
2058 splits two independent SETs doesn't handle this case correctly when it
2059 updates the register status. Also check the case where the first
2060 SET's destination is unused. That would not cause incorrect code, but
2061 does cause an unneeded insn to remain. */
2063 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2064 && XVECLEN (newpat
, 0) == 2
2065 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2066 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2067 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2068 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2069 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2070 && asm_noperands (newpat
) < 0)
2072 newpat
= XVECEXP (newpat
, 0, 0);
2073 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2076 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2077 && XVECLEN (newpat
, 0) == 2
2078 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2079 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2080 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2081 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2082 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2083 && asm_noperands (newpat
) < 0)
2085 newpat
= XVECEXP (newpat
, 0, 1);
2086 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2088 if (insn_code_number
>= 0)
2090 /* If we will be able to accept this, we have made a change to the
2091 destination of I3. This requires us to do a few adjustments. */
2092 PATTERN (i3
) = newpat
;
2093 adjust_for_new_dest (i3
);
2097 /* If we were combining three insns and the result is a simple SET
2098 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2099 insns. There are two ways to do this. It can be split using a
2100 machine-specific method (like when you have an addition of a large
2101 constant) or by combine in the function find_split_point. */
2103 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2104 && asm_noperands (newpat
) < 0)
2106 rtx m_split
, *split
;
2107 rtx ni2dest
= i2dest
;
2109 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2110 use I2DEST as a scratch register will help. In the latter case,
2111 convert I2DEST to the mode of the source of NEWPAT if we can. */
2113 m_split
= split_insns (newpat
, i3
);
2115 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2116 inputs of NEWPAT. */
2118 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2119 possible to try that as a scratch reg. This would require adding
2120 more code to make it work though. */
2122 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2124 /* If I2DEST is a hard register or the only use of a pseudo,
2125 we can change its mode. */
2126 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2127 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2128 && GET_CODE (i2dest
) == REG
2129 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2130 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2131 && ! REG_USERVAR_P (i2dest
))))
2132 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2135 m_split
= split_insns (gen_rtx_PARALLEL
2137 gen_rtvec (2, newpat
,
2138 gen_rtx_CLOBBER (VOIDmode
,
2141 /* If the split with the mode-changed register didn't work, try
2142 the original register. */
2143 if (! m_split
&& ni2dest
!= i2dest
)
2146 m_split
= split_insns (gen_rtx_PARALLEL
2148 gen_rtvec (2, newpat
,
2149 gen_rtx_CLOBBER (VOIDmode
,
2155 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2157 m_split
= PATTERN (m_split
);
2158 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2159 if (insn_code_number
>= 0)
2162 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2163 && (next_real_insn (i2
) == i3
2164 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2167 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2168 newi2pat
= PATTERN (m_split
);
2170 i3set
= single_set (NEXT_INSN (m_split
));
2171 i2set
= single_set (m_split
);
2173 /* In case we changed the mode of I2DEST, replace it in the
2174 pseudo-register table here. We can't do it above in case this
2175 code doesn't get executed and we do a split the other way. */
2177 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2178 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2180 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2182 /* If I2 or I3 has multiple SETs, we won't know how to track
2183 register status, so don't use these insns. If I2's destination
2184 is used between I2 and I3, we also can't use these insns. */
2186 if (i2_code_number
>= 0 && i2set
&& i3set
2187 && (next_real_insn (i2
) == i3
2188 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2189 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2191 if (insn_code_number
>= 0)
2194 /* It is possible that both insns now set the destination of I3.
2195 If so, we must show an extra use of it. */
2197 if (insn_code_number
>= 0)
2199 rtx new_i3_dest
= SET_DEST (i3set
);
2200 rtx new_i2_dest
= SET_DEST (i2set
);
2202 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2203 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2204 || GET_CODE (new_i3_dest
) == SUBREG
)
2205 new_i3_dest
= XEXP (new_i3_dest
, 0);
2207 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2208 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2209 || GET_CODE (new_i2_dest
) == SUBREG
)
2210 new_i2_dest
= XEXP (new_i2_dest
, 0);
2212 if (GET_CODE (new_i3_dest
) == REG
2213 && GET_CODE (new_i2_dest
) == REG
2214 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2215 REG_N_SETS (REGNO (new_i2_dest
))++;
2219 /* If we can split it and use I2DEST, go ahead and see if that
2220 helps things be recognized. Verify that none of the registers
2221 are set between I2 and I3. */
2222 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2224 && GET_CODE (i2dest
) == REG
2226 /* We need I2DEST in the proper mode. If it is a hard register
2227 or the only use of a pseudo, we can change its mode. */
2228 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2229 || GET_MODE (*split
) == VOIDmode
2230 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2231 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2232 && ! REG_USERVAR_P (i2dest
)))
2233 && (next_real_insn (i2
) == i3
2234 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2235 /* We can't overwrite I2DEST if its value is still used by
2237 && ! reg_referenced_p (i2dest
, newpat
))
2239 rtx newdest
= i2dest
;
2240 enum rtx_code split_code
= GET_CODE (*split
);
2241 enum machine_mode split_mode
= GET_MODE (*split
);
2243 /* Get NEWDEST as a register in the proper mode. We have already
2244 validated that we can do this. */
2245 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2247 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2249 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2250 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2253 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2254 an ASHIFT. This can occur if it was inside a PLUS and hence
2255 appeared to be a memory address. This is a kludge. */
2256 if (split_code
== MULT
2257 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2258 && INTVAL (XEXP (*split
, 1)) > 0
2259 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2261 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2262 XEXP (*split
, 0), GEN_INT (i
)));
2263 /* Update split_code because we may not have a multiply
2265 split_code
= GET_CODE (*split
);
2268 #ifdef INSN_SCHEDULING
2269 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2270 be written as a ZERO_EXTEND. */
2271 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2273 #ifdef LOAD_EXTEND_OP
2274 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2275 what it really is. */
2276 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2278 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2279 SUBREG_REG (*split
)));
2282 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2283 SUBREG_REG (*split
)));
2287 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2288 SUBST (*split
, newdest
);
2289 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2291 /* If the split point was a MULT and we didn't have one before,
2292 don't use one now. */
2293 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2294 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2298 /* Check for a case where we loaded from memory in a narrow mode and
2299 then sign extended it, but we need both registers. In that case,
2300 we have a PARALLEL with both loads from the same memory location.
2301 We can split this into a load from memory followed by a register-register
2302 copy. This saves at least one insn, more if register allocation can
2305 We cannot do this if the destination of the first assignment is a
2306 condition code register or cc0. We eliminate this case by making sure
2307 the SET_DEST and SET_SRC have the same mode.
2309 We cannot do this if the destination of the second assignment is
2310 a register that we have already assumed is zero-extended. Similarly
2311 for a SUBREG of such a register. */
2313 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2314 && GET_CODE (newpat
) == PARALLEL
2315 && XVECLEN (newpat
, 0) == 2
2316 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2317 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2318 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2319 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2320 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2321 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2322 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2323 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2325 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2326 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2327 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2328 (GET_CODE (temp
) == REG
2329 && reg_nonzero_bits
[REGNO (temp
)] != 0
2330 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2331 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2332 && (reg_nonzero_bits
[REGNO (temp
)]
2333 != GET_MODE_MASK (word_mode
))))
2334 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2335 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2336 (GET_CODE (temp
) == REG
2337 && reg_nonzero_bits
[REGNO (temp
)] != 0
2338 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2339 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2340 && (reg_nonzero_bits
[REGNO (temp
)]
2341 != GET_MODE_MASK (word_mode
)))))
2342 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2343 SET_SRC (XVECEXP (newpat
, 0, 1)))
2344 && ! find_reg_note (i3
, REG_UNUSED
,
2345 SET_DEST (XVECEXP (newpat
, 0, 0))))
2349 newi2pat
= XVECEXP (newpat
, 0, 0);
2350 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2351 newpat
= XVECEXP (newpat
, 0, 1);
2352 SUBST (SET_SRC (newpat
),
2353 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2354 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2356 if (i2_code_number
>= 0)
2357 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2359 if (insn_code_number
>= 0)
2364 /* If we will be able to accept this, we have made a change to the
2365 destination of I3. This requires us to do a few adjustments. */
2366 PATTERN (i3
) = newpat
;
2367 adjust_for_new_dest (i3
);
2369 /* I3 now uses what used to be its destination and which is
2370 now I2's destination. That means we need a LOG_LINK from
2371 I3 to I2. But we used to have one, so we still will.
2373 However, some later insn might be using I2's dest and have
2374 a LOG_LINK pointing at I3. We must remove this link.
2375 The simplest way to remove the link is to point it at I1,
2376 which we know will be a NOTE. */
2378 for (insn
= NEXT_INSN (i3
);
2379 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2380 || insn
!= this_basic_block
->next_bb
->head
);
2381 insn
= NEXT_INSN (insn
))
2383 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2385 for (link
= LOG_LINKS (insn
); link
;
2386 link
= XEXP (link
, 1))
2387 if (XEXP (link
, 0) == i3
)
2388 XEXP (link
, 0) = i1
;
2396 /* Similarly, check for a case where we have a PARALLEL of two independent
2397 SETs but we started with three insns. In this case, we can do the sets
2398 as two separate insns. This case occurs when some SET allows two
2399 other insns to combine, but the destination of that SET is still live. */
2401 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2402 && GET_CODE (newpat
) == PARALLEL
2403 && XVECLEN (newpat
, 0) == 2
2404 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2405 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2406 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2407 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2408 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2409 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2410 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2412 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2413 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2414 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2415 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2416 XVECEXP (newpat
, 0, 0))
2417 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2418 XVECEXP (newpat
, 0, 1))
2419 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2420 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2422 /* Normally, it doesn't matter which of the two is done first,
2423 but it does if one references cc0. In that case, it has to
2426 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2428 newi2pat
= XVECEXP (newpat
, 0, 0);
2429 newpat
= XVECEXP (newpat
, 0, 1);
2434 newi2pat
= XVECEXP (newpat
, 0, 1);
2435 newpat
= XVECEXP (newpat
, 0, 0);
2438 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2440 if (i2_code_number
>= 0)
2441 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2444 /* If it still isn't recognized, fail and change things back the way they
2446 if ((insn_code_number
< 0
2447 /* Is the result a reasonable ASM_OPERANDS? */
2448 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2454 /* If we had to change another insn, make sure it is valid also. */
2455 if (undobuf
.other_insn
)
2457 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2458 rtx new_other_notes
;
2461 CLEAR_HARD_REG_SET (newpat_used_regs
);
2463 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2466 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2472 PATTERN (undobuf
.other_insn
) = other_pat
;
2474 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2475 are still valid. Then add any non-duplicate notes added by
2476 recog_for_combine. */
2477 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2479 next
= XEXP (note
, 1);
2481 if (REG_NOTE_KIND (note
) == REG_UNUSED
2482 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2484 if (GET_CODE (XEXP (note
, 0)) == REG
)
2485 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2487 remove_note (undobuf
.other_insn
, note
);
2491 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2492 if (GET_CODE (XEXP (note
, 0)) == REG
)
2493 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2495 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2496 undobuf
.other_insn
, NULL_RTX
);
2499 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2500 they are adjacent to each other or not. */
2502 rtx p
= prev_nonnote_insn (i3
);
2503 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2504 && sets_cc0_p (newi2pat
))
2512 /* We now know that we can do this combination. Merge the insns and
2513 update the status of registers and LOG_LINKS. */
2516 rtx i3notes
, i2notes
, i1notes
= 0;
2517 rtx i3links
, i2links
, i1links
= 0;
2521 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2523 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2524 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2526 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2528 /* Ensure that we do not have something that should not be shared but
2529 occurs multiple times in the new insns. Check this by first
2530 resetting all the `used' flags and then copying anything is shared. */
2532 reset_used_flags (i3notes
);
2533 reset_used_flags (i2notes
);
2534 reset_used_flags (i1notes
);
2535 reset_used_flags (newpat
);
2536 reset_used_flags (newi2pat
);
2537 if (undobuf
.other_insn
)
2538 reset_used_flags (PATTERN (undobuf
.other_insn
));
2540 i3notes
= copy_rtx_if_shared (i3notes
);
2541 i2notes
= copy_rtx_if_shared (i2notes
);
2542 i1notes
= copy_rtx_if_shared (i1notes
);
2543 newpat
= copy_rtx_if_shared (newpat
);
2544 newi2pat
= copy_rtx_if_shared (newi2pat
);
2545 if (undobuf
.other_insn
)
2546 reset_used_flags (PATTERN (undobuf
.other_insn
));
2548 INSN_CODE (i3
) = insn_code_number
;
2549 PATTERN (i3
) = newpat
;
2551 if (GET_CODE (i3
) == CALL_INSN
&& CALL_INSN_FUNCTION_USAGE (i3
))
2553 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2555 reset_used_flags (call_usage
);
2556 call_usage
= copy_rtx (call_usage
);
2559 replace_rtx (call_usage
, i2dest
, i2src
);
2562 replace_rtx (call_usage
, i1dest
, i1src
);
2564 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2567 if (undobuf
.other_insn
)
2568 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2570 /* We had one special case above where I2 had more than one set and
2571 we replaced a destination of one of those sets with the destination
2572 of I3. In that case, we have to update LOG_LINKS of insns later
2573 in this basic block. Note that this (expensive) case is rare.
2575 Also, in this case, we must pretend that all REG_NOTEs for I2
2576 actually came from I3, so that REG_UNUSED notes from I2 will be
2577 properly handled. */
2579 if (i3_subst_into_i2
)
2581 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2582 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2583 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2584 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2585 && ! find_reg_note (i2
, REG_UNUSED
,
2586 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2587 for (temp
= NEXT_INSN (i2
);
2588 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2589 || this_basic_block
->head
!= temp
);
2590 temp
= NEXT_INSN (temp
))
2591 if (temp
!= i3
&& INSN_P (temp
))
2592 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2593 if (XEXP (link
, 0) == i2
)
2594 XEXP (link
, 0) = i3
;
2599 while (XEXP (link
, 1))
2600 link
= XEXP (link
, 1);
2601 XEXP (link
, 1) = i2notes
;
2615 INSN_CODE (i2
) = i2_code_number
;
2616 PATTERN (i2
) = newi2pat
;
2620 PUT_CODE (i2
, NOTE
);
2621 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2622 NOTE_SOURCE_FILE (i2
) = 0;
2629 PUT_CODE (i1
, NOTE
);
2630 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2631 NOTE_SOURCE_FILE (i1
) = 0;
2634 /* Get death notes for everything that is now used in either I3 or
2635 I2 and used to die in a previous insn. If we built two new
2636 patterns, move from I1 to I2 then I2 to I3 so that we get the
2637 proper movement on registers that I2 modifies. */
2641 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2642 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2645 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2648 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2650 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2652 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2654 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2656 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2658 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2659 know these are REG_UNUSED and want them to go to the desired insn,
2660 so we always pass it as i3. We have not counted the notes in
2661 reg_n_deaths yet, so we need to do so now. */
2663 if (newi2pat
&& new_i2_notes
)
2665 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2666 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2667 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2669 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2674 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2675 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2676 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2678 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2681 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2682 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2683 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2684 in that case, it might delete I2. Similarly for I2 and I1.
2685 Show an additional death due to the REG_DEAD note we make here. If
2686 we discard it in distribute_notes, we will decrement it again. */
2690 if (GET_CODE (i3dest_killed
) == REG
)
2691 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2693 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2694 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2696 NULL_RTX
, i2
, NULL_RTX
);
2698 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2700 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2703 if (i2dest_in_i2src
)
2705 if (GET_CODE (i2dest
) == REG
)
2706 REG_N_DEATHS (REGNO (i2dest
))++;
2708 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2709 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2710 NULL_RTX
, i2
, NULL_RTX
);
2712 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2713 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2716 if (i1dest_in_i1src
)
2718 if (GET_CODE (i1dest
) == REG
)
2719 REG_N_DEATHS (REGNO (i1dest
))++;
2721 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2722 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2723 NULL_RTX
, i2
, NULL_RTX
);
2725 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2726 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2729 distribute_links (i3links
);
2730 distribute_links (i2links
);
2731 distribute_links (i1links
);
2733 if (GET_CODE (i2dest
) == REG
)
2736 rtx i2_insn
= 0, i2_val
= 0, set
;
2738 /* The insn that used to set this register doesn't exist, and
2739 this life of the register may not exist either. See if one of
2740 I3's links points to an insn that sets I2DEST. If it does,
2741 that is now the last known value for I2DEST. If we don't update
2742 this and I2 set the register to a value that depended on its old
2743 contents, we will get confused. If this insn is used, thing
2744 will be set correctly in combine_instructions. */
2746 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2747 if ((set
= single_set (XEXP (link
, 0))) != 0
2748 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2749 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2751 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2753 /* If the reg formerly set in I2 died only once and that was in I3,
2754 zero its use count so it won't make `reload' do any work. */
2756 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2757 && ! i2dest_in_i2src
)
2759 regno
= REGNO (i2dest
);
2760 REG_N_SETS (regno
)--;
2764 if (i1
&& GET_CODE (i1dest
) == REG
)
2767 rtx i1_insn
= 0, i1_val
= 0, set
;
2769 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2770 if ((set
= single_set (XEXP (link
, 0))) != 0
2771 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2772 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2774 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2776 regno
= REGNO (i1dest
);
2777 if (! added_sets_1
&& ! i1dest_in_i1src
)
2778 REG_N_SETS (regno
)--;
2781 /* Update reg_nonzero_bits et al for any changes that may have been made
2782 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2783 important. Because newi2pat can affect nonzero_bits of newpat */
2785 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2786 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2788 /* Set new_direct_jump_p if a new return or simple jump instruction
2791 If I3 is now an unconditional jump, ensure that it has a
2792 BARRIER following it since it may have initially been a
2793 conditional jump. It may also be the last nonnote insn. */
2795 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2797 *new_direct_jump_p
= 1;
2798 mark_jump_label (PATTERN (i3
), i3
, 0);
2800 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2801 || GET_CODE (temp
) != BARRIER
)
2802 emit_barrier_after (i3
);
2805 if (undobuf
.other_insn
!= NULL_RTX
2806 && (returnjump_p (undobuf
.other_insn
)
2807 || any_uncondjump_p (undobuf
.other_insn
)))
2809 *new_direct_jump_p
= 1;
2811 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2812 || GET_CODE (temp
) != BARRIER
)
2813 emit_barrier_after (undobuf
.other_insn
);
2816 /* An NOOP jump does not need barrier, but it does need cleaning up
2818 if (GET_CODE (newpat
) == SET
2819 && SET_SRC (newpat
) == pc_rtx
2820 && SET_DEST (newpat
) == pc_rtx
)
2821 *new_direct_jump_p
= 1;
2824 combine_successes
++;
2827 if (added_links_insn
2828 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2829 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2830 return added_links_insn
;
2832 return newi2pat
? i2
: i3
;
2835 /* Undo all the modifications recorded in undobuf. */
2840 struct undo
*undo
, *next
;
2842 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2846 *undo
->where
.i
= undo
->old_contents
.i
;
2848 *undo
->where
.r
= undo
->old_contents
.r
;
2850 undo
->next
= undobuf
.frees
;
2851 undobuf
.frees
= undo
;
2857 /* We've committed to accepting the changes we made. Move all
2858 of the undos to the free list. */
2863 struct undo
*undo
, *next
;
2865 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2868 undo
->next
= undobuf
.frees
;
2869 undobuf
.frees
= undo
;
2875 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2876 where we have an arithmetic expression and return that point. LOC will
2879 try_combine will call this function to see if an insn can be split into
2883 find_split_point (rtx
*loc
, rtx insn
)
2886 enum rtx_code code
= GET_CODE (x
);
2888 unsigned HOST_WIDE_INT len
= 0;
2889 HOST_WIDE_INT pos
= 0;
2891 rtx inner
= NULL_RTX
;
2893 /* First special-case some codes. */
2897 #ifdef INSN_SCHEDULING
2898 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2900 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2903 return find_split_point (&SUBREG_REG (x
), insn
);
2907 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2908 using LO_SUM and HIGH. */
2909 if (GET_CODE (XEXP (x
, 0)) == CONST
2910 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2913 gen_rtx_LO_SUM (Pmode
,
2914 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2916 return &XEXP (XEXP (x
, 0), 0);
2920 /* If we have a PLUS whose second operand is a constant and the
2921 address is not valid, perhaps will can split it up using
2922 the machine-specific way to split large constants. We use
2923 the first pseudo-reg (one of the virtual regs) as a placeholder;
2924 it will not remain in the result. */
2925 if (GET_CODE (XEXP (x
, 0)) == PLUS
2926 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2927 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2929 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2930 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2933 /* This should have produced two insns, each of which sets our
2934 placeholder. If the source of the second is a valid address,
2935 we can make put both sources together and make a split point
2939 && NEXT_INSN (seq
) != NULL_RTX
2940 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
2941 && GET_CODE (seq
) == INSN
2942 && GET_CODE (PATTERN (seq
)) == SET
2943 && SET_DEST (PATTERN (seq
)) == reg
2944 && ! reg_mentioned_p (reg
,
2945 SET_SRC (PATTERN (seq
)))
2946 && GET_CODE (NEXT_INSN (seq
)) == INSN
2947 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
2948 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
2949 && memory_address_p (GET_MODE (x
),
2950 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
2952 rtx src1
= SET_SRC (PATTERN (seq
));
2953 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
2955 /* Replace the placeholder in SRC2 with SRC1. If we can
2956 find where in SRC2 it was placed, that can become our
2957 split point and we can replace this address with SRC2.
2958 Just try two obvious places. */
2960 src2
= replace_rtx (src2
, reg
, src1
);
2962 if (XEXP (src2
, 0) == src1
)
2963 split
= &XEXP (src2
, 0);
2964 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2965 && XEXP (XEXP (src2
, 0), 0) == src1
)
2966 split
= &XEXP (XEXP (src2
, 0), 0);
2970 SUBST (XEXP (x
, 0), src2
);
2975 /* If that didn't work, perhaps the first operand is complex and
2976 needs to be computed separately, so make a split point there.
2977 This will occur on machines that just support REG + CONST
2978 and have a constant moved through some previous computation. */
2980 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2981 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2982 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2984 return &XEXP (XEXP (x
, 0), 0);
2990 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2991 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2992 we need to put the operand into a register. So split at that
2995 if (SET_DEST (x
) == cc0_rtx
2996 && GET_CODE (SET_SRC (x
)) != COMPARE
2997 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2998 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2999 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
3000 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
3001 return &SET_SRC (x
);
3004 /* See if we can split SET_SRC as it stands. */
3005 split
= find_split_point (&SET_SRC (x
), insn
);
3006 if (split
&& split
!= &SET_SRC (x
))
3009 /* See if we can split SET_DEST as it stands. */
3010 split
= find_split_point (&SET_DEST (x
), insn
);
3011 if (split
&& split
!= &SET_DEST (x
))
3014 /* See if this is a bitfield assignment with everything constant. If
3015 so, this is an IOR of an AND, so split it into that. */
3016 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
3017 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
3018 <= HOST_BITS_PER_WIDE_INT
)
3019 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
3020 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
3021 && GET_CODE (SET_SRC (x
)) == CONST_INT
3022 && ((INTVAL (XEXP (SET_DEST (x
), 1))
3023 + INTVAL (XEXP (SET_DEST (x
), 2)))
3024 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
3025 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
3027 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
3028 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
3029 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
3030 rtx dest
= XEXP (SET_DEST (x
), 0);
3031 enum machine_mode mode
= GET_MODE (dest
);
3032 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3034 if (BITS_BIG_ENDIAN
)
3035 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3039 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3042 gen_binary (IOR
, mode
,
3043 gen_binary (AND
, mode
, dest
,
3044 gen_int_mode (~(mask
<< pos
),
3046 GEN_INT (src
<< pos
)));
3048 SUBST (SET_DEST (x
), dest
);
3050 split
= find_split_point (&SET_SRC (x
), insn
);
3051 if (split
&& split
!= &SET_SRC (x
))
3055 /* Otherwise, see if this is an operation that we can split into two.
3056 If so, try to split that. */
3057 code
= GET_CODE (SET_SRC (x
));
3062 /* If we are AND'ing with a large constant that is only a single
3063 bit and the result is only being used in a context where we
3064 need to know if it is zero or nonzero, replace it with a bit
3065 extraction. This will avoid the large constant, which might
3066 have taken more than one insn to make. If the constant were
3067 not a valid argument to the AND but took only one insn to make,
3068 this is no worse, but if it took more than one insn, it will
3071 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3072 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3073 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3074 && GET_CODE (SET_DEST (x
)) == REG
3075 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3076 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3077 && XEXP (*split
, 0) == SET_DEST (x
)
3078 && XEXP (*split
, 1) == const0_rtx
)
3080 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3081 XEXP (SET_SRC (x
), 0),
3082 pos
, NULL_RTX
, 1, 1, 0, 0);
3083 if (extraction
!= 0)
3085 SUBST (SET_SRC (x
), extraction
);
3086 return find_split_point (loc
, insn
);
3092 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3093 is known to be on, this can be converted into a NEG of a shift. */
3094 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3095 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3096 && 1 <= (pos
= exact_log2
3097 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3098 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3100 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3104 gen_rtx_LSHIFTRT (mode
,
3105 XEXP (SET_SRC (x
), 0),
3108 split
= find_split_point (&SET_SRC (x
), insn
);
3109 if (split
&& split
!= &SET_SRC (x
))
3115 inner
= XEXP (SET_SRC (x
), 0);
3117 /* We can't optimize if either mode is a partial integer
3118 mode as we don't know how many bits are significant
3120 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3121 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3125 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3131 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3132 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3134 inner
= XEXP (SET_SRC (x
), 0);
3135 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3136 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3138 if (BITS_BIG_ENDIAN
)
3139 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3140 unsignedp
= (code
== ZERO_EXTRACT
);
3148 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3150 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3152 /* For unsigned, we have a choice of a shift followed by an
3153 AND or two shifts. Use two shifts for field sizes where the
3154 constant might be too large. We assume here that we can
3155 always at least get 8-bit constants in an AND insn, which is
3156 true for every current RISC. */
3158 if (unsignedp
&& len
<= 8)
3163 (mode
, gen_lowpart_for_combine (mode
, inner
),
3165 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3167 split
= find_split_point (&SET_SRC (x
), insn
);
3168 if (split
&& split
!= &SET_SRC (x
))
3175 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3176 gen_rtx_ASHIFT (mode
,
3177 gen_lowpart_for_combine (mode
, inner
),
3178 GEN_INT (GET_MODE_BITSIZE (mode
)
3180 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3182 split
= find_split_point (&SET_SRC (x
), insn
);
3183 if (split
&& split
!= &SET_SRC (x
))
3188 /* See if this is a simple operation with a constant as the second
3189 operand. It might be that this constant is out of range and hence
3190 could be used as a split point. */
3191 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3192 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3193 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3194 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3195 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3196 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3197 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3199 return &XEXP (SET_SRC (x
), 1);
3201 /* Finally, see if this is a simple operation with its first operand
3202 not in a register. The operation might require this operand in a
3203 register, so return it as a split point. We can always do this
3204 because if the first operand were another operation, we would have
3205 already found it as a split point. */
3206 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3207 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3208 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3209 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3210 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3211 return &XEXP (SET_SRC (x
), 0);
3217 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3218 it is better to write this as (not (ior A B)) so we can split it.
3219 Similarly for IOR. */
3220 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3223 gen_rtx_NOT (GET_MODE (x
),
3224 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3226 XEXP (XEXP (x
, 0), 0),
3227 XEXP (XEXP (x
, 1), 0))));
3228 return find_split_point (loc
, insn
);
3231 /* Many RISC machines have a large set of logical insns. If the
3232 second operand is a NOT, put it first so we will try to split the
3233 other operand first. */
3234 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3236 rtx tem
= XEXP (x
, 0);
3237 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3238 SUBST (XEXP (x
, 1), tem
);
3246 /* Otherwise, select our actions depending on our rtx class. */
3247 switch (GET_RTX_CLASS (code
))
3249 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3251 split
= find_split_point (&XEXP (x
, 2), insn
);
3254 /* ... fall through ... */
3258 split
= find_split_point (&XEXP (x
, 1), insn
);
3261 /* ... fall through ... */
3263 /* Some machines have (and (shift ...) ...) insns. If X is not
3264 an AND, but XEXP (X, 0) is, use it as our split point. */
3265 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3266 return &XEXP (x
, 0);
3268 split
= find_split_point (&XEXP (x
, 0), insn
);
3274 /* Otherwise, we don't have a split point. */
3278 /* Throughout X, replace FROM with TO, and return the result.
3279 The result is TO if X is FROM;
3280 otherwise the result is X, but its contents may have been modified.
3281 If they were modified, a record was made in undobuf so that
3282 undo_all will (among other things) return X to its original state.
3284 If the number of changes necessary is too much to record to undo,
3285 the excess changes are not made, so the result is invalid.
3286 The changes already made can still be undone.
3287 undobuf.num_undo is incremented for such changes, so by testing that
3288 the caller can tell whether the result is valid.
3290 `n_occurrences' is incremented each time FROM is replaced.
3292 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3294 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3295 by copying if `n_occurrences' is nonzero. */
3298 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3300 enum rtx_code code
= GET_CODE (x
);
3301 enum machine_mode op0_mode
= VOIDmode
;
3306 /* Two expressions are equal if they are identical copies of a shared
3307 RTX or if they are both registers with the same register number
3310 #define COMBINE_RTX_EQUAL_P(X,Y) \
3312 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3313 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3315 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3318 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3321 /* If X and FROM are the same register but different modes, they will
3322 not have been seen as equal above. However, flow.c will make a
3323 LOG_LINKS entry for that case. If we do nothing, we will try to
3324 rerecognize our original insn and, when it succeeds, we will
3325 delete the feeding insn, which is incorrect.
3327 So force this insn not to match in this (rare) case. */
3328 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3329 && REGNO (x
) == REGNO (from
))
3330 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3332 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3333 of which may contain things that can be combined. */
3334 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3337 /* It is possible to have a subexpression appear twice in the insn.
3338 Suppose that FROM is a register that appears within TO.
3339 Then, after that subexpression has been scanned once by `subst',
3340 the second time it is scanned, TO may be found. If we were
3341 to scan TO here, we would find FROM within it and create a
3342 self-referent rtl structure which is completely wrong. */
3343 if (COMBINE_RTX_EQUAL_P (x
, to
))
3346 /* Parallel asm_operands need special attention because all of the
3347 inputs are shared across the arms. Furthermore, unsharing the
3348 rtl results in recognition failures. Failure to handle this case
3349 specially can result in circular rtl.
3351 Solve this by doing a normal pass across the first entry of the
3352 parallel, and only processing the SET_DESTs of the subsequent
3355 if (code
== PARALLEL
3356 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3357 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3359 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3361 /* If this substitution failed, this whole thing fails. */
3362 if (GET_CODE (new) == CLOBBER
3363 && XEXP (new, 0) == const0_rtx
)
3366 SUBST (XVECEXP (x
, 0, 0), new);
3368 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3370 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3372 if (GET_CODE (dest
) != REG
3373 && GET_CODE (dest
) != CC0
3374 && GET_CODE (dest
) != PC
)
3376 new = subst (dest
, from
, to
, 0, unique_copy
);
3378 /* If this substitution failed, this whole thing fails. */
3379 if (GET_CODE (new) == CLOBBER
3380 && XEXP (new, 0) == const0_rtx
)
3383 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3389 len
= GET_RTX_LENGTH (code
);
3390 fmt
= GET_RTX_FORMAT (code
);
3392 /* We don't need to process a SET_DEST that is a register, CC0,
3393 or PC, so set up to skip this common case. All other cases
3394 where we want to suppress replacing something inside a
3395 SET_SRC are handled via the IN_DEST operand. */
3397 && (GET_CODE (SET_DEST (x
)) == REG
3398 || GET_CODE (SET_DEST (x
)) == CC0
3399 || GET_CODE (SET_DEST (x
)) == PC
))
3402 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3405 op0_mode
= GET_MODE (XEXP (x
, 0));
3407 for (i
= 0; i
< len
; i
++)
3412 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3414 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3416 new = (unique_copy
&& n_occurrences
3417 ? copy_rtx (to
) : to
);
3422 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3425 /* If this substitution failed, this whole thing
3427 if (GET_CODE (new) == CLOBBER
3428 && XEXP (new, 0) == const0_rtx
)
3432 SUBST (XVECEXP (x
, i
, j
), new);
3435 else if (fmt
[i
] == 'e')
3437 /* If this is a register being set, ignore it. */
3440 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3441 || code
== ZERO_EXTRACT
)
3443 && GET_CODE (new) == REG
)
3446 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3448 /* In general, don't install a subreg involving two
3449 modes not tieable. It can worsen register
3450 allocation, and can even make invalid reload
3451 insns, since the reg inside may need to be copied
3452 from in the outside mode, and that may be invalid
3453 if it is an fp reg copied in integer mode.
3455 We allow two exceptions to this: It is valid if
3456 it is inside another SUBREG and the mode of that
3457 SUBREG and the mode of the inside of TO is
3458 tieable and it is valid if X is a SET that copies
3461 if (GET_CODE (to
) == SUBREG
3462 && ! MODES_TIEABLE_P (GET_MODE (to
),
3463 GET_MODE (SUBREG_REG (to
)))
3464 && ! (code
== SUBREG
3465 && MODES_TIEABLE_P (GET_MODE (x
),
3466 GET_MODE (SUBREG_REG (to
))))
3468 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3471 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3473 #ifdef CANNOT_CHANGE_MODE_CLASS
3475 && GET_CODE (to
) == REG
3476 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3477 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3480 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3483 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3487 /* If we are in a SET_DEST, suppress most cases unless we
3488 have gone inside a MEM, in which case we want to
3489 simplify the address. We assume here that things that
3490 are actually part of the destination have their inner
3491 parts in the first expression. This is true for SUBREG,
3492 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3493 things aside from REG and MEM that should appear in a
3495 new = subst (XEXP (x
, i
), from
, to
,
3497 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3498 || code
== ZERO_EXTRACT
))
3500 && i
== 0), unique_copy
);
3502 /* If we found that we will have to reject this combination,
3503 indicate that by returning the CLOBBER ourselves, rather than
3504 an expression containing it. This will speed things up as
3505 well as prevent accidents where two CLOBBERs are considered
3506 to be equal, thus producing an incorrect simplification. */
3508 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3511 if (GET_CODE (x
) == SUBREG
3512 && (GET_CODE (new) == CONST_INT
3513 || GET_CODE (new) == CONST_DOUBLE
))
3515 enum machine_mode mode
= GET_MODE (x
);
3517 x
= simplify_subreg (GET_MODE (x
), new,
3518 GET_MODE (SUBREG_REG (x
)),
3521 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3523 else if (GET_CODE (new) == CONST_INT
3524 && GET_CODE (x
) == ZERO_EXTEND
)
3526 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3527 new, GET_MODE (XEXP (x
, 0)));
3532 SUBST (XEXP (x
, i
), new);
3537 /* Try to simplify X. If the simplification changed the code, it is likely
3538 that further simplification will help, so loop, but limit the number
3539 of repetitions that will be performed. */
3541 for (i
= 0; i
< 4; i
++)
3543 /* If X is sufficiently simple, don't bother trying to do anything
3545 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3546 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3548 if (GET_CODE (x
) == code
)
3551 code
= GET_CODE (x
);
3553 /* We no longer know the original mode of operand 0 since we
3554 have changed the form of X) */
3555 op0_mode
= VOIDmode
;
3561 /* Simplify X, a piece of RTL. We just operate on the expression at the
3562 outer level; call `subst' to simplify recursively. Return the new
3565 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3566 will be the iteration even if an expression with a code different from
3567 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3570 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int last
,
3573 enum rtx_code code
= GET_CODE (x
);
3574 enum machine_mode mode
= GET_MODE (x
);
3579 /* If this is a commutative operation, put a constant last and a complex
3580 expression first. We don't need to do this for comparisons here. */
3581 if (GET_RTX_CLASS (code
) == 'c'
3582 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3585 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3586 SUBST (XEXP (x
, 1), temp
);
3589 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3590 sign extension of a PLUS with a constant, reverse the order of the sign
3591 extension and the addition. Note that this not the same as the original
3592 code, but overflow is undefined for signed values. Also note that the
3593 PLUS will have been partially moved "inside" the sign-extension, so that
3594 the first operand of X will really look like:
3595 (ashiftrt (plus (ashift A C4) C5) C4).
3597 (plus (ashiftrt (ashift A C4) C2) C4)
3598 and replace the first operand of X with that expression. Later parts
3599 of this function may simplify the expression further.
3601 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3602 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3603 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3605 We do this to simplify address expressions. */
3607 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3608 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3609 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3610 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3611 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3612 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3613 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3614 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3615 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3616 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3617 XEXP (XEXP (x
, 0), 1))) != 0)
3620 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3621 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3622 INTVAL (XEXP (XEXP (x
, 0), 1)));
3624 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3625 INTVAL (XEXP (XEXP (x
, 0), 1)));
3627 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3630 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3631 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3632 things. Check for cases where both arms are testing the same
3635 Don't do anything if all operands are very simple. */
3637 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3638 || GET_RTX_CLASS (code
) == '<')
3639 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3640 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3641 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3643 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3644 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3645 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3647 || (GET_RTX_CLASS (code
) == '1'
3648 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3649 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3650 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3653 rtx cond
, true_rtx
, false_rtx
;
3655 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3657 /* If everything is a comparison, what we have is highly unlikely
3658 to be simpler, so don't use it. */
3659 && ! (GET_RTX_CLASS (code
) == '<'
3660 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3661 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3663 rtx cop1
= const0_rtx
;
3664 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3666 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3669 /* Simplify the alternative arms; this may collapse the true and
3670 false arms to store-flag values. Be careful to use copy_rtx
3671 here since true_rtx or false_rtx might share RTL with x as a
3672 result of the if_then_else_cond call above. */
3673 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3674 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3676 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3677 is unlikely to be simpler. */
3678 if (general_operand (true_rtx
, VOIDmode
)
3679 && general_operand (false_rtx
, VOIDmode
))
3681 enum rtx_code reversed
;
3683 /* Restarting if we generate a store-flag expression will cause
3684 us to loop. Just drop through in this case. */
3686 /* If the result values are STORE_FLAG_VALUE and zero, we can
3687 just make the comparison operation. */
3688 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3689 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3690 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3691 && ((reversed
= reversed_comparison_code_parts
3692 (cond_code
, cond
, cop1
, NULL
))
3694 x
= gen_binary (reversed
, mode
, cond
, cop1
);
3696 /* Likewise, we can make the negate of a comparison operation
3697 if the result values are - STORE_FLAG_VALUE and zero. */
3698 else if (GET_CODE (true_rtx
) == CONST_INT
3699 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3700 && false_rtx
== const0_rtx
)
3701 x
= simplify_gen_unary (NEG
, mode
,
3702 gen_binary (cond_code
, mode
, cond
,
3705 else if (GET_CODE (false_rtx
) == CONST_INT
3706 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3707 && true_rtx
== const0_rtx
3708 && ((reversed
= reversed_comparison_code_parts
3709 (cond_code
, cond
, cop1
, NULL
))
3711 x
= simplify_gen_unary (NEG
, mode
,
3712 gen_binary (reversed
, mode
,
3716 return gen_rtx_IF_THEN_ELSE (mode
,
3717 gen_binary (cond_code
, VOIDmode
,
3719 true_rtx
, false_rtx
);
3721 code
= GET_CODE (x
);
3722 op0_mode
= VOIDmode
;
3727 /* Try to fold this expression in case we have constants that weren't
3730 switch (GET_RTX_CLASS (code
))
3733 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3737 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3738 if (cmp_mode
== VOIDmode
)
3740 cmp_mode
= GET_MODE (XEXP (x
, 1));
3741 if (cmp_mode
== VOIDmode
)
3742 cmp_mode
= op0_mode
;
3744 temp
= simplify_relational_operation (code
, cmp_mode
,
3745 XEXP (x
, 0), XEXP (x
, 1));
3747 #ifdef FLOAT_STORE_FLAG_VALUE
3748 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3750 if (temp
== const0_rtx
)
3751 temp
= CONST0_RTX (mode
);
3753 temp
= CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode
),
3760 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3764 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3765 XEXP (x
, 1), XEXP (x
, 2));
3772 code
= GET_CODE (temp
);
3773 op0_mode
= VOIDmode
;
3774 mode
= GET_MODE (temp
);
3777 /* First see if we can apply the inverse distributive law. */
3778 if (code
== PLUS
|| code
== MINUS
3779 || code
== AND
|| code
== IOR
|| code
== XOR
)
3781 x
= apply_distributive_law (x
);
3782 code
= GET_CODE (x
);
3783 op0_mode
= VOIDmode
;
3786 /* If CODE is an associative operation not otherwise handled, see if we
3787 can associate some operands. This can win if they are constants or
3788 if they are logically related (i.e. (a & b) & a). */
3789 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3790 || code
== AND
|| code
== IOR
|| code
== XOR
3791 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3792 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3793 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3795 if (GET_CODE (XEXP (x
, 0)) == code
)
3797 rtx other
= XEXP (XEXP (x
, 0), 0);
3798 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3799 rtx inner_op1
= XEXP (x
, 1);
3802 /* Make sure we pass the constant operand if any as the second
3803 one if this is a commutative operation. */
3804 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3806 rtx tem
= inner_op0
;
3807 inner_op0
= inner_op1
;
3810 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3811 : code
== DIV
? MULT
3813 mode
, inner_op0
, inner_op1
);
3815 /* For commutative operations, try the other pair if that one
3817 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3819 other
= XEXP (XEXP (x
, 0), 1);
3820 inner
= simplify_binary_operation (code
, mode
,
3821 XEXP (XEXP (x
, 0), 0),
3826 return gen_binary (code
, mode
, other
, inner
);
3830 /* A little bit of algebraic simplification here. */
3834 /* Ensure that our address has any ASHIFTs converted to MULT in case
3835 address-recognizing predicates are called later. */
3836 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3837 SUBST (XEXP (x
, 0), temp
);
3841 if (op0_mode
== VOIDmode
)
3842 op0_mode
= GET_MODE (SUBREG_REG (x
));
3844 /* simplify_subreg can't use gen_lowpart_for_combine. */
3845 if (CONSTANT_P (SUBREG_REG (x
))
3846 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3847 /* Don't call gen_lowpart_for_combine if the inner mode
3848 is VOIDmode and we cannot simplify it, as SUBREG without
3849 inner mode is invalid. */
3850 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3851 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3852 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3854 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3858 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3864 /* Don't change the mode of the MEM if that would change the meaning
3866 if (GET_CODE (SUBREG_REG (x
)) == MEM
3867 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3868 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3869 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3871 /* Note that we cannot do any narrowing for non-constants since
3872 we might have been counting on using the fact that some bits were
3873 zero. We now do this in the SET. */
3878 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3879 && subreg_lowpart_p (XEXP (x
, 0))
3880 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3881 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3882 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3883 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3885 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3887 x
= gen_rtx_ROTATE (inner_mode
,
3888 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3890 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3891 return gen_lowpart_for_combine (mode
, x
);
3894 /* Apply De Morgan's laws to reduce number of patterns for machines
3895 with negating logical insns (and-not, nand, etc.). If result has
3896 only one NOT, put it first, since that is how the patterns are
3899 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3901 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3902 enum machine_mode op_mode
;
3904 op_mode
= GET_MODE (in1
);
3905 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3907 op_mode
= GET_MODE (in2
);
3908 if (op_mode
== VOIDmode
)
3910 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3912 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3915 in2
= in1
; in1
= tem
;
3918 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3924 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3925 if (GET_CODE (XEXP (x
, 0)) == XOR
3926 && XEXP (XEXP (x
, 0), 1) == const1_rtx
3927 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3928 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3930 temp
= expand_compound_operation (XEXP (x
, 0));
3932 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3933 replaced by (lshiftrt X C). This will convert
3934 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3936 if (GET_CODE (temp
) == ASHIFTRT
3937 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3938 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3939 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3940 INTVAL (XEXP (temp
, 1)));
3942 /* If X has only a single bit that might be nonzero, say, bit I, convert
3943 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3944 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3945 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3946 or a SUBREG of one since we'd be making the expression more
3947 complex if it was just a register. */
3949 if (GET_CODE (temp
) != REG
3950 && ! (GET_CODE (temp
) == SUBREG
3951 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3952 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3954 rtx temp1
= simplify_shift_const
3955 (NULL_RTX
, ASHIFTRT
, mode
,
3956 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3957 GET_MODE_BITSIZE (mode
) - 1 - i
),
3958 GET_MODE_BITSIZE (mode
) - 1 - i
);
3960 /* If all we did was surround TEMP with the two shifts, we
3961 haven't improved anything, so don't use it. Otherwise,
3962 we are better off with TEMP1. */
3963 if (GET_CODE (temp1
) != ASHIFTRT
3964 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3965 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3971 /* We can't handle truncation to a partial integer mode here
3972 because we don't know the real bitsize of the partial
3974 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3977 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3978 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3979 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3981 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3982 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3984 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3985 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3986 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3987 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3988 return XEXP (XEXP (x
, 0), 0);
3990 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3991 (OP:SI foo:SI) if OP is NEG or ABS. */
3992 if ((GET_CODE (XEXP (x
, 0)) == ABS
3993 || GET_CODE (XEXP (x
, 0)) == NEG
)
3994 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
3995 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
3996 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3997 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
3998 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4000 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4002 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4003 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4004 && subreg_lowpart_p (XEXP (x
, 0)))
4005 return SUBREG_REG (XEXP (x
, 0));
4007 /* If we know that the value is already truncated, we can
4008 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4009 is nonzero for the corresponding modes. But don't do this
4010 for an (LSHIFTRT (MULT ...)) since this will cause problems
4011 with the umulXi3_highpart patterns. */
4012 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4013 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4014 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4015 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
4016 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4017 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4018 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4020 /* A truncate of a comparison can be replaced with a subreg if
4021 STORE_FLAG_VALUE permits. This is like the previous test,
4022 but it works even if the comparison is done in a mode larger
4023 than HOST_BITS_PER_WIDE_INT. */
4024 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4025 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4026 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4027 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4029 /* Similarly, a truncate of a register whose value is a
4030 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4032 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4033 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4034 && (temp
= get_last_value (XEXP (x
, 0)))
4035 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4036 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4040 case FLOAT_TRUNCATE
:
4041 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4042 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4043 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4044 return XEXP (XEXP (x
, 0), 0);
4046 /* (float_truncate:SF (float_truncate:DF foo:XF))
4047 = (float_truncate:SF foo:XF).
4048 This may eliminate double rounding, so it is unsafe.
4050 (float_truncate:SF (float_extend:XF foo:DF))
4051 = (float_truncate:SF foo:DF).
4053 (float_truncate:DF (float_extend:XF foo:SF))
4054 = (float_extend:SF foo:DF). */
4055 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4056 && flag_unsafe_math_optimizations
)
4057 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4058 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4060 > GET_MODE_SIZE (mode
)
4061 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4063 XEXP (XEXP (x
, 0), 0), mode
);
4065 /* (float_truncate (float x)) is (float x) */
4066 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4067 && (flag_unsafe_math_optimizations
4068 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4069 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4070 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4071 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4072 return simplify_gen_unary (FLOAT
, mode
,
4073 XEXP (XEXP (x
, 0), 0),
4074 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4076 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4077 (OP:SF foo:SF) if OP is NEG or ABS. */
4078 if ((GET_CODE (XEXP (x
, 0)) == ABS
4079 || GET_CODE (XEXP (x
, 0)) == NEG
)
4080 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4081 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4082 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4083 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4085 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4086 is (float_truncate:SF x). */
4087 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4088 && subreg_lowpart_p (XEXP (x
, 0))
4089 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4090 return SUBREG_REG (XEXP (x
, 0));
4093 /* (float_extend (float_extend x)) is (float_extend x)
4095 (float_extend (float x)) is (float x) assuming that double
4096 rounding can't happen.
4098 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4099 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4100 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4101 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4102 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4103 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4104 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4105 XEXP (XEXP (x
, 0), 0),
4106 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4111 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4112 using cc0, in which case we want to leave it as a COMPARE
4113 so we can distinguish it from a register-register-copy. */
4114 if (XEXP (x
, 1) == const0_rtx
)
4117 /* x - 0 is the same as x unless x's mode has signed zeros and
4118 allows rounding towards -infinity. Under those conditions,
4120 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4121 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4122 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4128 /* (const (const X)) can become (const X). Do it this way rather than
4129 returning the inner CONST since CONST can be shared with a
4131 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4132 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4137 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4138 can add in an offset. find_split_point will split this address up
4139 again if it doesn't match. */
4140 if (GET_CODE (XEXP (x
, 0)) == HIGH
4141 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4147 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4149 if (GET_CODE (XEXP (x
, 0)) == MULT
4150 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4154 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4155 in2
= XEXP (XEXP (x
, 0), 1);
4156 return gen_binary (MINUS
, mode
, XEXP (x
, 1),
4157 gen_binary (MULT
, mode
, in1
, in2
));
4160 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4161 outermost. That's because that's the way indexed addresses are
4162 supposed to appear. This code used to check many more cases, but
4163 they are now checked elsewhere. */
4164 if (GET_CODE (XEXP (x
, 0)) == PLUS
4165 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4166 return gen_binary (PLUS
, mode
,
4167 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4169 XEXP (XEXP (x
, 0), 1));
4171 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4172 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4173 bit-field and can be replaced by either a sign_extend or a
4174 sign_extract. The `and' may be a zero_extend and the two
4175 <c>, -<c> constants may be reversed. */
4176 if (GET_CODE (XEXP (x
, 0)) == XOR
4177 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4178 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4179 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4180 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4181 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4182 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4183 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4184 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4185 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4186 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4187 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4188 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4189 == (unsigned int) i
+ 1))))
4190 return simplify_shift_const
4191 (NULL_RTX
, ASHIFTRT
, mode
,
4192 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4193 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4194 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4195 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4197 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4198 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4199 is 1. This produces better code than the alternative immediately
4201 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4202 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4203 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4204 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4205 XEXP (XEXP (x
, 0), 0),
4206 XEXP (XEXP (x
, 0), 1))))
4208 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4210 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4211 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4212 the bitsize of the mode - 1. This allows simplification of
4213 "a = (b & 8) == 0;" */
4214 if (XEXP (x
, 1) == constm1_rtx
4215 && GET_CODE (XEXP (x
, 0)) != REG
4216 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4217 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4218 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4219 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4220 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4221 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4222 GET_MODE_BITSIZE (mode
) - 1),
4223 GET_MODE_BITSIZE (mode
) - 1);
4225 /* If we are adding two things that have no bits in common, convert
4226 the addition into an IOR. This will often be further simplified,
4227 for example in cases like ((a & 1) + (a & 2)), which can
4230 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4231 && (nonzero_bits (XEXP (x
, 0), mode
)
4232 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4234 /* Try to simplify the expression further. */
4235 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4236 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4238 /* If we could, great. If not, do not go ahead with the IOR
4239 replacement, since PLUS appears in many special purpose
4240 address arithmetic instructions. */
4241 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4247 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4248 by reversing the comparison code if valid. */
4249 if (STORE_FLAG_VALUE
== 1
4250 && XEXP (x
, 0) == const1_rtx
4251 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4252 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4253 XEXP (XEXP (x
, 1), 0),
4254 XEXP (XEXP (x
, 1), 1))))
4257 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4258 (and <foo> (const_int pow2-1)) */
4259 if (GET_CODE (XEXP (x
, 1)) == AND
4260 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4261 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4262 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4263 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4264 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4266 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4268 if (GET_CODE (XEXP (x
, 1)) == MULT
4269 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4273 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4274 in2
= XEXP (XEXP (x
, 1), 1);
4275 return gen_binary (PLUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4279 /* Canonicalize (minus (neg A) (mult B C)) to
4280 (minus (mult (neg B) C) A). */
4281 if (GET_CODE (XEXP (x
, 1)) == MULT
4282 && GET_CODE (XEXP (x
, 0)) == NEG
)
4286 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4287 in2
= XEXP (XEXP (x
, 1), 1);
4288 return gen_binary (MINUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4289 XEXP (XEXP (x
, 0), 0));
4292 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4294 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4295 return gen_binary (MINUS
, mode
,
4296 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4297 XEXP (XEXP (x
, 1), 0)),
4298 XEXP (XEXP (x
, 1), 1));
4302 /* If we have (mult (plus A B) C), apply the distributive law and then
4303 the inverse distributive law to see if things simplify. This
4304 occurs mostly in addresses, often when unrolling loops. */
4306 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4308 x
= apply_distributive_law
4309 (gen_binary (PLUS
, mode
,
4310 gen_binary (MULT
, mode
,
4311 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4312 gen_binary (MULT
, mode
,
4313 XEXP (XEXP (x
, 0), 1),
4314 copy_rtx (XEXP (x
, 1)))));
4316 if (GET_CODE (x
) != MULT
)
4319 /* Try simplify a*(b/c) as (a*b)/c. */
4320 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4321 && GET_CODE (XEXP (x
, 0)) == DIV
)
4323 rtx tem
= simplify_binary_operation (MULT
, mode
,
4324 XEXP (XEXP (x
, 0), 0),
4327 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4332 /* If this is a divide by a power of two, treat it as a shift if
4333 its first operand is a shift. */
4334 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4335 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4336 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4337 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4338 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4339 || GET_CODE (XEXP (x
, 0)) == ROTATE
4340 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4341 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4345 case GT
: case GTU
: case GE
: case GEU
:
4346 case LT
: case LTU
: case LE
: case LEU
:
4347 case UNEQ
: case LTGT
:
4348 case UNGT
: case UNGE
:
4349 case UNLT
: case UNLE
:
4350 case UNORDERED
: case ORDERED
:
4351 /* If the first operand is a condition code, we can't do anything
4353 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4354 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4355 && ! CC0_P (XEXP (x
, 0))))
4357 rtx op0
= XEXP (x
, 0);
4358 rtx op1
= XEXP (x
, 1);
4359 enum rtx_code new_code
;
4361 if (GET_CODE (op0
) == COMPARE
)
4362 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4364 /* Simplify our comparison, if possible. */
4365 new_code
= simplify_comparison (code
, &op0
, &op1
);
4367 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4368 if only the low-order bit is possibly nonzero in X (such as when
4369 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4370 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4371 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4374 Remove any ZERO_EXTRACT we made when thinking this was a
4375 comparison. It may now be simpler to use, e.g., an AND. If a
4376 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4377 the call to make_compound_operation in the SET case. */
4379 if (STORE_FLAG_VALUE
== 1
4380 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4381 && op1
== const0_rtx
4382 && mode
== GET_MODE (op0
)
4383 && nonzero_bits (op0
, mode
) == 1)
4384 return gen_lowpart_for_combine (mode
,
4385 expand_compound_operation (op0
));
4387 else if (STORE_FLAG_VALUE
== 1
4388 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4389 && op1
== const0_rtx
4390 && mode
== GET_MODE (op0
)
4391 && (num_sign_bit_copies (op0
, mode
)
4392 == GET_MODE_BITSIZE (mode
)))
4394 op0
= expand_compound_operation (op0
);
4395 return simplify_gen_unary (NEG
, mode
,
4396 gen_lowpart_for_combine (mode
, op0
),
4400 else if (STORE_FLAG_VALUE
== 1
4401 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4402 && op1
== const0_rtx
4403 && mode
== GET_MODE (op0
)
4404 && nonzero_bits (op0
, mode
) == 1)
4406 op0
= expand_compound_operation (op0
);
4407 return gen_binary (XOR
, mode
,
4408 gen_lowpart_for_combine (mode
, op0
),
4412 else if (STORE_FLAG_VALUE
== 1
4413 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4414 && op1
== const0_rtx
4415 && mode
== GET_MODE (op0
)
4416 && (num_sign_bit_copies (op0
, mode
)
4417 == GET_MODE_BITSIZE (mode
)))
4419 op0
= expand_compound_operation (op0
);
4420 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4423 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4425 if (STORE_FLAG_VALUE
== -1
4426 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4427 && op1
== const0_rtx
4428 && (num_sign_bit_copies (op0
, mode
)
4429 == GET_MODE_BITSIZE (mode
)))
4430 return gen_lowpart_for_combine (mode
,
4431 expand_compound_operation (op0
));
4433 else if (STORE_FLAG_VALUE
== -1
4434 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4435 && op1
== const0_rtx
4436 && mode
== GET_MODE (op0
)
4437 && nonzero_bits (op0
, mode
) == 1)
4439 op0
= expand_compound_operation (op0
);
4440 return simplify_gen_unary (NEG
, mode
,
4441 gen_lowpart_for_combine (mode
, op0
),
4445 else if (STORE_FLAG_VALUE
== -1
4446 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4447 && op1
== const0_rtx
4448 && mode
== GET_MODE (op0
)
4449 && (num_sign_bit_copies (op0
, mode
)
4450 == GET_MODE_BITSIZE (mode
)))
4452 op0
= expand_compound_operation (op0
);
4453 return simplify_gen_unary (NOT
, mode
,
4454 gen_lowpart_for_combine (mode
, op0
),
4458 /* If X is 0/1, (eq X 0) is X-1. */
4459 else if (STORE_FLAG_VALUE
== -1
4460 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4461 && op1
== const0_rtx
4462 && mode
== GET_MODE (op0
)
4463 && nonzero_bits (op0
, mode
) == 1)
4465 op0
= expand_compound_operation (op0
);
4466 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4469 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4470 one bit that might be nonzero, we can convert (ne x 0) to
4471 (ashift x c) where C puts the bit in the sign bit. Remove any
4472 AND with STORE_FLAG_VALUE when we are done, since we are only
4473 going to test the sign bit. */
4474 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4475 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4476 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4477 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4478 && op1
== const0_rtx
4479 && mode
== GET_MODE (op0
)
4480 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4482 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4483 expand_compound_operation (op0
),
4484 GET_MODE_BITSIZE (mode
) - 1 - i
);
4485 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4491 /* If the code changed, return a whole new comparison. */
4492 if (new_code
!= code
)
4493 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4495 /* Otherwise, keep this operation, but maybe change its operands.
4496 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4497 SUBST (XEXP (x
, 0), op0
);
4498 SUBST (XEXP (x
, 1), op1
);
4503 return simplify_if_then_else (x
);
4509 /* If we are processing SET_DEST, we are done. */
4513 return expand_compound_operation (x
);
4516 return simplify_set (x
);
4521 return simplify_logical (x
, last
);
4524 /* (abs (neg <foo>)) -> (abs <foo>) */
4525 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4526 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4528 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4530 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4533 /* If operand is something known to be positive, ignore the ABS. */
4534 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4535 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4536 <= HOST_BITS_PER_WIDE_INT
)
4537 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4538 & ((HOST_WIDE_INT
) 1
4539 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4543 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4544 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4545 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4550 /* (ffs (*_extend <X>)) = (ffs <X>) */
4551 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4552 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4553 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4558 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4559 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4560 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4564 /* (float (sign_extend <X>)) = (float <X>). */
4565 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4566 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4574 /* If this is a shift by a constant amount, simplify it. */
4575 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4576 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4577 INTVAL (XEXP (x
, 1)));
4579 #ifdef SHIFT_COUNT_TRUNCATED
4580 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4582 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4584 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4593 rtx op0
= XEXP (x
, 0);
4594 rtx op1
= XEXP (x
, 1);
4597 if (GET_CODE (op1
) != PARALLEL
)
4599 len
= XVECLEN (op1
, 0);
4601 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4602 && GET_CODE (op0
) == VEC_CONCAT
)
4604 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4606 /* Try to find the element in the VEC_CONCAT. */
4609 if (GET_MODE (op0
) == GET_MODE (x
))
4611 if (GET_CODE (op0
) == VEC_CONCAT
)
4613 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4614 if (op0_size
< offset
)
4615 op0
= XEXP (op0
, 0);
4619 op0
= XEXP (op0
, 1);
4637 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4640 simplify_if_then_else (rtx x
)
4642 enum machine_mode mode
= GET_MODE (x
);
4643 rtx cond
= XEXP (x
, 0);
4644 rtx true_rtx
= XEXP (x
, 1);
4645 rtx false_rtx
= XEXP (x
, 2);
4646 enum rtx_code true_code
= GET_CODE (cond
);
4647 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4650 enum rtx_code false_code
;
4653 /* Simplify storing of the truth value. */
4654 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4655 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4657 /* Also when the truth value has to be reversed. */
4659 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4660 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4664 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4665 in it is being compared against certain values. Get the true and false
4666 comparisons and see if that says anything about the value of each arm. */
4669 && ((false_code
= combine_reversed_comparison_code (cond
))
4671 && GET_CODE (XEXP (cond
, 0)) == REG
)
4674 rtx from
= XEXP (cond
, 0);
4675 rtx true_val
= XEXP (cond
, 1);
4676 rtx false_val
= true_val
;
4679 /* If FALSE_CODE is EQ, swap the codes and arms. */
4681 if (false_code
== EQ
)
4683 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4684 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4687 /* If we are comparing against zero and the expression being tested has
4688 only a single bit that might be nonzero, that is its value when it is
4689 not equal to zero. Similarly if it is known to be -1 or 0. */
4691 if (true_code
== EQ
&& true_val
== const0_rtx
4692 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4693 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4694 else if (true_code
== EQ
&& true_val
== const0_rtx
4695 && (num_sign_bit_copies (from
, GET_MODE (from
))
4696 == GET_MODE_BITSIZE (GET_MODE (from
))))
4697 false_code
= EQ
, false_val
= constm1_rtx
;
4699 /* Now simplify an arm if we know the value of the register in the
4700 branch and it is used in the arm. Be careful due to the potential
4701 of locally-shared RTL. */
4703 if (reg_mentioned_p (from
, true_rtx
))
4704 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4706 pc_rtx
, pc_rtx
, 0, 0);
4707 if (reg_mentioned_p (from
, false_rtx
))
4708 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4710 pc_rtx
, pc_rtx
, 0, 0);
4712 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4713 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4715 true_rtx
= XEXP (x
, 1);
4716 false_rtx
= XEXP (x
, 2);
4717 true_code
= GET_CODE (cond
);
4720 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4721 reversed, do so to avoid needing two sets of patterns for
4722 subtract-and-branch insns. Similarly if we have a constant in the true
4723 arm, the false arm is the same as the first operand of the comparison, or
4724 the false arm is more complicated than the true arm. */
4727 && combine_reversed_comparison_code (cond
) != UNKNOWN
4728 && (true_rtx
== pc_rtx
4729 || (CONSTANT_P (true_rtx
)
4730 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4731 || true_rtx
== const0_rtx
4732 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4733 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4734 || (GET_CODE (true_rtx
) == SUBREG
4735 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4736 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4737 || reg_mentioned_p (true_rtx
, false_rtx
)
4738 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4740 true_code
= reversed_comparison_code (cond
, NULL
);
4742 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4745 SUBST (XEXP (x
, 1), false_rtx
);
4746 SUBST (XEXP (x
, 2), true_rtx
);
4748 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4751 /* It is possible that the conditional has been simplified out. */
4752 true_code
= GET_CODE (cond
);
4753 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4756 /* If the two arms are identical, we don't need the comparison. */
4758 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4761 /* Convert a == b ? b : a to "a". */
4762 if (true_code
== EQ
&& ! side_effects_p (cond
)
4763 && !HONOR_NANS (mode
)
4764 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4765 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4767 else if (true_code
== NE
&& ! side_effects_p (cond
)
4768 && !HONOR_NANS (mode
)
4769 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4770 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4773 /* Look for cases where we have (abs x) or (neg (abs X)). */
4775 if (GET_MODE_CLASS (mode
) == MODE_INT
4776 && GET_CODE (false_rtx
) == NEG
4777 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4779 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4780 && ! side_effects_p (true_rtx
))
4785 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4789 simplify_gen_unary (NEG
, mode
,
4790 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4796 /* Look for MIN or MAX. */
4798 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4800 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4801 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4802 && ! side_effects_p (cond
))
4807 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4810 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4813 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4816 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4821 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4822 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4823 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4824 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4825 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4826 neither 1 or -1, but it isn't worth checking for. */
4828 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4830 && GET_MODE_CLASS (mode
) == MODE_INT
4831 && ! side_effects_p (x
))
4833 rtx t
= make_compound_operation (true_rtx
, SET
);
4834 rtx f
= make_compound_operation (false_rtx
, SET
);
4835 rtx cond_op0
= XEXP (cond
, 0);
4836 rtx cond_op1
= XEXP (cond
, 1);
4837 enum rtx_code op
= NIL
, extend_op
= NIL
;
4838 enum machine_mode m
= mode
;
4839 rtx z
= 0, c1
= NULL_RTX
;
4841 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4842 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4843 || GET_CODE (t
) == ASHIFT
4844 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4845 && rtx_equal_p (XEXP (t
, 0), f
))
4846 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4848 /* If an identity-zero op is commutative, check whether there
4849 would be a match if we swapped the operands. */
4850 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4851 || GET_CODE (t
) == XOR
)
4852 && rtx_equal_p (XEXP (t
, 1), f
))
4853 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4854 else if (GET_CODE (t
) == SIGN_EXTEND
4855 && (GET_CODE (XEXP (t
, 0)) == PLUS
4856 || GET_CODE (XEXP (t
, 0)) == MINUS
4857 || GET_CODE (XEXP (t
, 0)) == IOR
4858 || GET_CODE (XEXP (t
, 0)) == XOR
4859 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4860 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4861 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4862 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4863 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4864 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4865 && (num_sign_bit_copies (f
, GET_MODE (f
))
4867 (GET_MODE_BITSIZE (mode
)
4868 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4870 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4871 extend_op
= SIGN_EXTEND
;
4872 m
= GET_MODE (XEXP (t
, 0));
4874 else if (GET_CODE (t
) == SIGN_EXTEND
4875 && (GET_CODE (XEXP (t
, 0)) == PLUS
4876 || GET_CODE (XEXP (t
, 0)) == IOR
4877 || GET_CODE (XEXP (t
, 0)) == XOR
)
4878 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4879 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4880 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4881 && (num_sign_bit_copies (f
, GET_MODE (f
))
4883 (GET_MODE_BITSIZE (mode
)
4884 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4886 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4887 extend_op
= SIGN_EXTEND
;
4888 m
= GET_MODE (XEXP (t
, 0));
4890 else if (GET_CODE (t
) == ZERO_EXTEND
4891 && (GET_CODE (XEXP (t
, 0)) == PLUS
4892 || GET_CODE (XEXP (t
, 0)) == MINUS
4893 || GET_CODE (XEXP (t
, 0)) == IOR
4894 || GET_CODE (XEXP (t
, 0)) == XOR
4895 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4896 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4897 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4898 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4899 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4900 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4901 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4902 && ((nonzero_bits (f
, GET_MODE (f
))
4903 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4906 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4907 extend_op
= ZERO_EXTEND
;
4908 m
= GET_MODE (XEXP (t
, 0));
4910 else if (GET_CODE (t
) == ZERO_EXTEND
4911 && (GET_CODE (XEXP (t
, 0)) == PLUS
4912 || GET_CODE (XEXP (t
, 0)) == IOR
4913 || GET_CODE (XEXP (t
, 0)) == XOR
)
4914 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4915 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4916 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4917 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4918 && ((nonzero_bits (f
, GET_MODE (f
))
4919 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4922 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4923 extend_op
= ZERO_EXTEND
;
4924 m
= GET_MODE (XEXP (t
, 0));
4929 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4930 pc_rtx
, pc_rtx
, 0, 0);
4931 temp
= gen_binary (MULT
, m
, temp
,
4932 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4933 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4934 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4936 if (extend_op
!= NIL
)
4937 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4943 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4944 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4945 negation of a single bit, we can convert this operation to a shift. We
4946 can actually do this more generally, but it doesn't seem worth it. */
4948 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4949 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4950 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4951 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4952 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4953 == GET_MODE_BITSIZE (mode
))
4954 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4956 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4957 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4959 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4960 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4961 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4962 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
4963 == nonzero_bits (XEXP (cond
, 0), mode
)
4964 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
4965 return XEXP (cond
, 0);
4970 /* Simplify X, a SET expression. Return the new expression. */
4973 simplify_set (rtx x
)
4975 rtx src
= SET_SRC (x
);
4976 rtx dest
= SET_DEST (x
);
4977 enum machine_mode mode
4978 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4982 /* (set (pc) (return)) gets written as (return). */
4983 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4986 /* Now that we know for sure which bits of SRC we are using, see if we can
4987 simplify the expression for the object knowing that we only need the
4990 if (GET_MODE_CLASS (mode
) == MODE_INT
4991 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4993 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4994 SUBST (SET_SRC (x
), src
);
4997 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4998 the comparison result and try to simplify it unless we already have used
4999 undobuf.other_insn. */
5000 if ((GET_MODE_CLASS (mode
) == MODE_CC
5001 || GET_CODE (src
) == COMPARE
5003 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
5004 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
5005 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
5006 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
5008 enum rtx_code old_code
= GET_CODE (*cc_use
);
5009 enum rtx_code new_code
;
5011 int other_changed
= 0;
5012 enum machine_mode compare_mode
= GET_MODE (dest
);
5013 enum machine_mode tmp_mode
;
5015 if (GET_CODE (src
) == COMPARE
)
5016 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5018 op0
= src
, op1
= const0_rtx
;
5020 /* Check whether the comparison is known at compile time. */
5021 if (GET_MODE (op0
) != VOIDmode
)
5022 tmp_mode
= GET_MODE (op0
);
5023 else if (GET_MODE (op1
) != VOIDmode
)
5024 tmp_mode
= GET_MODE (op1
);
5026 tmp_mode
= compare_mode
;
5027 tmp
= simplify_relational_operation (old_code
, tmp_mode
, op0
, op1
);
5028 if (tmp
!= NULL_RTX
)
5030 rtx pat
= PATTERN (other_insn
);
5031 undobuf
.other_insn
= other_insn
;
5032 SUBST (*cc_use
, tmp
);
5034 /* Attempt to simplify CC user. */
5035 if (GET_CODE (pat
) == SET
)
5037 rtx
new = simplify_rtx (SET_SRC (pat
));
5038 if (new != NULL_RTX
)
5039 SUBST (SET_SRC (pat
), new);
5042 /* Convert X into a no-op move. */
5043 SUBST (SET_DEST (x
), pc_rtx
);
5044 SUBST (SET_SRC (x
), pc_rtx
);
5048 /* Simplify our comparison, if possible. */
5049 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5051 #ifdef EXTRA_CC_MODES
5052 /* If this machine has CC modes other than CCmode, check to see if we
5053 need to use a different CC mode here. */
5054 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5055 #endif /* EXTRA_CC_MODES */
5057 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5058 /* If the mode changed, we have to change SET_DEST, the mode in the
5059 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5060 a hard register, just build new versions with the proper mode. If it
5061 is a pseudo, we lose unless it is only time we set the pseudo, in
5062 which case we can safely change its mode. */
5063 if (compare_mode
!= GET_MODE (dest
))
5065 unsigned int regno
= REGNO (dest
);
5066 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5068 if (regno
< FIRST_PSEUDO_REGISTER
5069 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5071 if (regno
>= FIRST_PSEUDO_REGISTER
)
5072 SUBST (regno_reg_rtx
[regno
], new_dest
);
5074 SUBST (SET_DEST (x
), new_dest
);
5075 SUBST (XEXP (*cc_use
, 0), new_dest
);
5083 /* If the code changed, we have to build a new comparison in
5084 undobuf.other_insn. */
5085 if (new_code
!= old_code
)
5087 unsigned HOST_WIDE_INT mask
;
5089 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5092 /* If the only change we made was to change an EQ into an NE or
5093 vice versa, OP0 has only one bit that might be nonzero, and OP1
5094 is zero, check if changing the user of the condition code will
5095 produce a valid insn. If it won't, we can keep the original code
5096 in that insn by surrounding our operation with an XOR. */
5098 if (((old_code
== NE
&& new_code
== EQ
)
5099 || (old_code
== EQ
&& new_code
== NE
))
5100 && ! other_changed
&& op1
== const0_rtx
5101 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5102 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5104 rtx pat
= PATTERN (other_insn
), note
= 0;
5106 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5107 && ! check_asm_operands (pat
)))
5109 PUT_CODE (*cc_use
, old_code
);
5112 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5120 undobuf
.other_insn
= other_insn
;
5123 /* If we are now comparing against zero, change our source if
5124 needed. If we do not use cc0, we always have a COMPARE. */
5125 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5127 SUBST (SET_SRC (x
), op0
);
5133 /* Otherwise, if we didn't previously have a COMPARE in the
5134 correct mode, we need one. */
5135 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5137 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5142 /* Otherwise, update the COMPARE if needed. */
5143 SUBST (XEXP (src
, 0), op0
);
5144 SUBST (XEXP (src
, 1), op1
);
5149 /* Get SET_SRC in a form where we have placed back any
5150 compound expressions. Then do the checks below. */
5151 src
= make_compound_operation (src
, SET
);
5152 SUBST (SET_SRC (x
), src
);
5155 #ifdef WORD_REGISTER_OPERATIONS
5156 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5157 and X being a REG or (subreg (reg)), we may be able to convert this to
5158 (set (subreg:m2 x) (op)).
5160 On a machine where WORD_REGISTER_OPERATIONS is defined, this
5161 transformation is safe as long as M1 and M2 have the same number
5164 However, on a machine without WORD_REGISTER_OPERATIONS defined,
5165 we cannot apply this transformation because it would create a
5166 paradoxical subreg in SET_DEST. */
5168 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5169 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5170 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5172 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5173 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5174 #ifdef CANNOT_CHANGE_MODE_CLASS
5175 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5176 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5177 GET_MODE (SUBREG_REG (src
)),
5180 && (GET_CODE (dest
) == REG
5181 || (GET_CODE (dest
) == SUBREG
5182 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5184 SUBST (SET_DEST (x
),
5185 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5187 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5189 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5194 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5197 && GET_CODE (src
) == SUBREG
5198 && subreg_lowpart_p (src
)
5199 && (GET_MODE_BITSIZE (GET_MODE (src
))
5200 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5202 rtx inner
= SUBREG_REG (src
);
5203 enum machine_mode inner_mode
= GET_MODE (inner
);
5205 /* Here we make sure that we don't have a sign bit on. */
5206 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5207 && (nonzero_bits (inner
, inner_mode
)
5208 < ((unsigned HOST_WIDE_INT
) 1
5209 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5211 SUBST (SET_SRC (x
), inner
);
5217 #ifdef LOAD_EXTEND_OP
5218 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5219 would require a paradoxical subreg. Replace the subreg with a
5220 zero_extend to avoid the reload that would otherwise be required. */
5222 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5223 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5224 && SUBREG_BYTE (src
) == 0
5225 && (GET_MODE_SIZE (GET_MODE (src
))
5226 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5227 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5230 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5231 GET_MODE (src
), SUBREG_REG (src
)));
5237 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5238 are comparing an item known to be 0 or -1 against 0, use a logical
5239 operation instead. Check for one of the arms being an IOR of the other
5240 arm with some value. We compute three terms to be IOR'ed together. In
5241 practice, at most two will be nonzero. Then we do the IOR's. */
5243 if (GET_CODE (dest
) != PC
5244 && GET_CODE (src
) == IF_THEN_ELSE
5245 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5246 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5247 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5248 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5249 #ifdef HAVE_conditional_move
5250 && ! can_conditionally_move_p (GET_MODE (src
))
5252 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5253 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5254 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5255 && ! side_effects_p (src
))
5257 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5258 ? XEXP (src
, 1) : XEXP (src
, 2));
5259 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5260 ? XEXP (src
, 2) : XEXP (src
, 1));
5261 rtx term1
= const0_rtx
, term2
, term3
;
5263 if (GET_CODE (true_rtx
) == IOR
5264 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5265 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5266 else if (GET_CODE (true_rtx
) == IOR
5267 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5268 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5269 else if (GET_CODE (false_rtx
) == IOR
5270 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5271 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5272 else if (GET_CODE (false_rtx
) == IOR
5273 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5274 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5276 term2
= gen_binary (AND
, GET_MODE (src
),
5277 XEXP (XEXP (src
, 0), 0), true_rtx
);
5278 term3
= gen_binary (AND
, GET_MODE (src
),
5279 simplify_gen_unary (NOT
, GET_MODE (src
),
5280 XEXP (XEXP (src
, 0), 0),
5285 gen_binary (IOR
, GET_MODE (src
),
5286 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5292 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5293 whole thing fail. */
5294 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5296 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5299 /* Convert this into a field assignment operation, if possible. */
5300 return make_field_assignment (x
);
5303 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5304 result. LAST is nonzero if this is the last retry. */
5307 simplify_logical (rtx x
, int last
)
5309 enum machine_mode mode
= GET_MODE (x
);
5310 rtx op0
= XEXP (x
, 0);
5311 rtx op1
= XEXP (x
, 1);
5314 switch (GET_CODE (x
))
5317 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5318 insn (and may simplify more). */
5319 if (GET_CODE (op0
) == XOR
5320 && rtx_equal_p (XEXP (op0
, 0), op1
)
5321 && ! side_effects_p (op1
))
5322 x
= gen_binary (AND
, mode
,
5323 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5326 if (GET_CODE (op0
) == XOR
5327 && rtx_equal_p (XEXP (op0
, 1), op1
)
5328 && ! side_effects_p (op1
))
5329 x
= gen_binary (AND
, mode
,
5330 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5333 /* Similarly for (~(A ^ B)) & A. */
5334 if (GET_CODE (op0
) == NOT
5335 && GET_CODE (XEXP (op0
, 0)) == XOR
5336 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5337 && ! side_effects_p (op1
))
5338 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5340 if (GET_CODE (op0
) == NOT
5341 && GET_CODE (XEXP (op0
, 0)) == XOR
5342 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5343 && ! side_effects_p (op1
))
5344 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5346 /* We can call simplify_and_const_int only if we don't lose
5347 any (sign) bits when converting INTVAL (op1) to
5348 "unsigned HOST_WIDE_INT". */
5349 if (GET_CODE (op1
) == CONST_INT
5350 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5351 || INTVAL (op1
) > 0))
5353 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5355 /* If we have (ior (and (X C1) C2)) and the next restart would be
5356 the last, simplify this by making C1 as small as possible
5359 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5360 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5361 && GET_CODE (op1
) == CONST_INT
)
5362 return gen_binary (IOR
, mode
,
5363 gen_binary (AND
, mode
, XEXP (op0
, 0),
5364 GEN_INT (INTVAL (XEXP (op0
, 1))
5365 & ~INTVAL (op1
))), op1
);
5367 if (GET_CODE (x
) != AND
)
5370 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5371 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5372 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5375 /* Convert (A | B) & A to A. */
5376 if (GET_CODE (op0
) == IOR
5377 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5378 || rtx_equal_p (XEXP (op0
, 1), op1
))
5379 && ! side_effects_p (XEXP (op0
, 0))
5380 && ! side_effects_p (XEXP (op0
, 1)))
5383 /* In the following group of tests (and those in case IOR below),
5384 we start with some combination of logical operations and apply
5385 the distributive law followed by the inverse distributive law.
5386 Most of the time, this results in no change. However, if some of
5387 the operands are the same or inverses of each other, simplifications
5390 For example, (and (ior A B) (not B)) can occur as the result of
5391 expanding a bit field assignment. When we apply the distributive
5392 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5393 which then simplifies to (and (A (not B))).
5395 If we have (and (ior A B) C), apply the distributive law and then
5396 the inverse distributive law to see if things simplify. */
5398 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5400 x
= apply_distributive_law
5401 (gen_binary (GET_CODE (op0
), mode
,
5402 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5403 gen_binary (AND
, mode
, XEXP (op0
, 1),
5405 if (GET_CODE (x
) != AND
)
5409 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5410 return apply_distributive_law
5411 (gen_binary (GET_CODE (op1
), mode
,
5412 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5413 gen_binary (AND
, mode
, XEXP (op1
, 1),
5416 /* Similarly, taking advantage of the fact that
5417 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5419 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5420 return apply_distributive_law
5421 (gen_binary (XOR
, mode
,
5422 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5423 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5426 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5427 return apply_distributive_law
5428 (gen_binary (XOR
, mode
,
5429 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5430 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5434 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5435 if (GET_CODE (op1
) == CONST_INT
5436 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5437 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5440 /* Convert (A & B) | A to A. */
5441 if (GET_CODE (op0
) == AND
5442 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5443 || rtx_equal_p (XEXP (op0
, 1), op1
))
5444 && ! side_effects_p (XEXP (op0
, 0))
5445 && ! side_effects_p (XEXP (op0
, 1)))
5448 /* If we have (ior (and A B) C), apply the distributive law and then
5449 the inverse distributive law to see if things simplify. */
5451 if (GET_CODE (op0
) == AND
)
5453 x
= apply_distributive_law
5454 (gen_binary (AND
, mode
,
5455 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5456 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5459 if (GET_CODE (x
) != IOR
)
5463 if (GET_CODE (op1
) == AND
)
5465 x
= apply_distributive_law
5466 (gen_binary (AND
, mode
,
5467 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5468 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5471 if (GET_CODE (x
) != IOR
)
5475 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5476 mode size to (rotate A CX). */
5478 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5479 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5480 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5481 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5482 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5483 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5484 == GET_MODE_BITSIZE (mode
)))
5485 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5486 (GET_CODE (op0
) == ASHIFT
5487 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5489 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5490 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5491 does not affect any of the bits in OP1, it can really be done
5492 as a PLUS and we can associate. We do this by seeing if OP1
5493 can be safely shifted left C bits. */
5494 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5495 && GET_CODE (XEXP (op0
, 0)) == PLUS
5496 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5497 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5498 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5500 int count
= INTVAL (XEXP (op0
, 1));
5501 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5503 if (mask
>> count
== INTVAL (op1
)
5504 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5506 SUBST (XEXP (XEXP (op0
, 0), 1),
5507 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5514 /* If we are XORing two things that have no bits in common,
5515 convert them into an IOR. This helps to detect rotation encoded
5516 using those methods and possibly other simplifications. */
5518 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5519 && (nonzero_bits (op0
, mode
)
5520 & nonzero_bits (op1
, mode
)) == 0)
5521 return (gen_binary (IOR
, mode
, op0
, op1
));
5523 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5524 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5527 int num_negated
= 0;
5529 if (GET_CODE (op0
) == NOT
)
5530 num_negated
++, op0
= XEXP (op0
, 0);
5531 if (GET_CODE (op1
) == NOT
)
5532 num_negated
++, op1
= XEXP (op1
, 0);
5534 if (num_negated
== 2)
5536 SUBST (XEXP (x
, 0), op0
);
5537 SUBST (XEXP (x
, 1), op1
);
5539 else if (num_negated
== 1)
5541 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5545 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5546 correspond to a machine insn or result in further simplifications
5547 if B is a constant. */
5549 if (GET_CODE (op0
) == AND
5550 && rtx_equal_p (XEXP (op0
, 1), op1
)
5551 && ! side_effects_p (op1
))
5552 return gen_binary (AND
, mode
,
5553 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5556 else if (GET_CODE (op0
) == AND
5557 && rtx_equal_p (XEXP (op0
, 0), op1
)
5558 && ! side_effects_p (op1
))
5559 return gen_binary (AND
, mode
,
5560 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5563 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5564 comparison if STORE_FLAG_VALUE is 1. */
5565 if (STORE_FLAG_VALUE
== 1
5566 && op1
== const1_rtx
5567 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5568 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5572 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5573 is (lt foo (const_int 0)), so we can perform the above
5574 simplification if STORE_FLAG_VALUE is 1. */
5576 if (STORE_FLAG_VALUE
== 1
5577 && op1
== const1_rtx
5578 && GET_CODE (op0
) == LSHIFTRT
5579 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5580 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5581 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5583 /* (xor (comparison foo bar) (const_int sign-bit))
5584 when STORE_FLAG_VALUE is the sign bit. */
5585 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5586 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5587 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5588 && op1
== const_true_rtx
5589 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5590 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5603 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5604 operations" because they can be replaced with two more basic operations.
5605 ZERO_EXTEND is also considered "compound" because it can be replaced with
5606 an AND operation, which is simpler, though only one operation.
5608 The function expand_compound_operation is called with an rtx expression
5609 and will convert it to the appropriate shifts and AND operations,
5610 simplifying at each stage.
5612 The function make_compound_operation is called to convert an expression
5613 consisting of shifts and ANDs into the equivalent compound expression.
5614 It is the inverse of this function, loosely speaking. */
5617 expand_compound_operation (rtx x
)
5619 unsigned HOST_WIDE_INT pos
= 0, len
;
5621 unsigned int modewidth
;
5624 switch (GET_CODE (x
))
5629 /* We can't necessarily use a const_int for a multiword mode;
5630 it depends on implicitly extending the value.
5631 Since we don't know the right way to extend it,
5632 we can't tell whether the implicit way is right.
5634 Even for a mode that is no wider than a const_int,
5635 we can't win, because we need to sign extend one of its bits through
5636 the rest of it, and we don't know which bit. */
5637 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5640 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5641 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5642 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5643 reloaded. If not for that, MEM's would very rarely be safe.
5645 Reject MODEs bigger than a word, because we might not be able
5646 to reference a two-register group starting with an arbitrary register
5647 (and currently gen_lowpart might crash for a SUBREG). */
5649 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5652 /* Reject MODEs that aren't scalar integers because turning vector
5653 or complex modes into shifts causes problems. */
5655 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5658 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5659 /* If the inner object has VOIDmode (the only way this can happen
5660 is if it is an ASM_OPERANDS), we can't do anything since we don't
5661 know how much masking to do. */
5670 /* If the operand is a CLOBBER, just return it. */
5671 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5674 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5675 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5676 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5679 /* Reject MODEs that aren't scalar integers because turning vector
5680 or complex modes into shifts causes problems. */
5682 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5685 len
= INTVAL (XEXP (x
, 1));
5686 pos
= INTVAL (XEXP (x
, 2));
5688 /* If this goes outside the object being extracted, replace the object
5689 with a (use (mem ...)) construct that only combine understands
5690 and is used only for this purpose. */
5691 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5692 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5694 if (BITS_BIG_ENDIAN
)
5695 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5702 /* Convert sign extension to zero extension, if we know that the high
5703 bit is not set, as this is easier to optimize. It will be converted
5704 back to cheaper alternative in make_extraction. */
5705 if (GET_CODE (x
) == SIGN_EXTEND
5706 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5707 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5708 & ~(((unsigned HOST_WIDE_INT
)
5709 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5713 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5714 rtx temp2
= expand_compound_operation (temp
);
5716 /* Make sure this is a profitable operation. */
5717 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5719 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5725 /* We can optimize some special cases of ZERO_EXTEND. */
5726 if (GET_CODE (x
) == ZERO_EXTEND
)
5728 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5729 know that the last value didn't have any inappropriate bits
5731 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5732 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5733 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5734 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5735 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5736 return XEXP (XEXP (x
, 0), 0);
5738 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5739 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5740 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5741 && subreg_lowpart_p (XEXP (x
, 0))
5742 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5743 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5744 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5745 return SUBREG_REG (XEXP (x
, 0));
5747 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5748 is a comparison and STORE_FLAG_VALUE permits. This is like
5749 the first case, but it works even when GET_MODE (x) is larger
5750 than HOST_WIDE_INT. */
5751 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5752 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5753 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5754 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5755 <= HOST_BITS_PER_WIDE_INT
)
5756 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5757 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5758 return XEXP (XEXP (x
, 0), 0);
5760 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5761 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5762 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5763 && subreg_lowpart_p (XEXP (x
, 0))
5764 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5765 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5766 <= HOST_BITS_PER_WIDE_INT
)
5767 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5768 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5769 return SUBREG_REG (XEXP (x
, 0));
5773 /* If we reach here, we want to return a pair of shifts. The inner
5774 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5775 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5776 logical depending on the value of UNSIGNEDP.
5778 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5779 converted into an AND of a shift.
5781 We must check for the case where the left shift would have a negative
5782 count. This can happen in a case like (x >> 31) & 255 on machines
5783 that can't shift by a constant. On those machines, we would first
5784 combine the shift with the AND to produce a variable-position
5785 extraction. Then the constant of 31 would be substituted in to produce
5786 a such a position. */
5788 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5789 if (modewidth
+ len
>= pos
)
5790 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5792 simplify_shift_const (NULL_RTX
, ASHIFT
,
5795 modewidth
- pos
- len
),
5798 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5799 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5800 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5803 ((HOST_WIDE_INT
) 1 << len
) - 1);
5805 /* Any other cases we can't handle. */
5808 /* If we couldn't do this for some reason, return the original
5810 if (GET_CODE (tem
) == CLOBBER
)
5816 /* X is a SET which contains an assignment of one object into
5817 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5818 or certain SUBREGS). If possible, convert it into a series of
5821 We half-heartedly support variable positions, but do not at all
5822 support variable lengths. */
5825 expand_field_assignment (rtx x
)
5828 rtx pos
; /* Always counts from low bit. */
5831 enum machine_mode compute_mode
;
5833 /* Loop until we find something we can't simplify. */
5836 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5837 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5839 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5840 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5841 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5843 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5844 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5846 inner
= XEXP (SET_DEST (x
), 0);
5847 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5848 pos
= XEXP (SET_DEST (x
), 2);
5850 /* If the position is constant and spans the width of INNER,
5851 surround INNER with a USE to indicate this. */
5852 if (GET_CODE (pos
) == CONST_INT
5853 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5854 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5856 if (BITS_BIG_ENDIAN
)
5858 if (GET_CODE (pos
) == CONST_INT
)
5859 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5861 else if (GET_CODE (pos
) == MINUS
5862 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5863 && (INTVAL (XEXP (pos
, 1))
5864 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5865 /* If position is ADJUST - X, new position is X. */
5866 pos
= XEXP (pos
, 0);
5868 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5869 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5875 /* A SUBREG between two modes that occupy the same numbers of words
5876 can be done by moving the SUBREG to the source. */
5877 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5878 /* We need SUBREGs to compute nonzero_bits properly. */
5879 && nonzero_sign_valid
5880 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5881 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5882 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5883 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5885 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5886 gen_lowpart_for_combine
5887 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5894 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5895 inner
= SUBREG_REG (inner
);
5897 compute_mode
= GET_MODE (inner
);
5899 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5900 if (! SCALAR_INT_MODE_P (compute_mode
))
5902 enum machine_mode imode
;
5904 /* Don't do anything for vector or complex integral types. */
5905 if (! FLOAT_MODE_P (compute_mode
))
5908 /* Try to find an integral mode to pun with. */
5909 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5910 if (imode
== BLKmode
)
5913 compute_mode
= imode
;
5914 inner
= gen_lowpart_for_combine (imode
, inner
);
5917 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5918 if (len
< HOST_BITS_PER_WIDE_INT
)
5919 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5923 /* Now compute the equivalent expression. Make a copy of INNER
5924 for the SET_DEST in case it is a MEM into which we will substitute;
5925 we don't want shared RTL in that case. */
5927 (VOIDmode
, copy_rtx (inner
),
5928 gen_binary (IOR
, compute_mode
,
5929 gen_binary (AND
, compute_mode
,
5930 simplify_gen_unary (NOT
, compute_mode
,
5936 gen_binary (ASHIFT
, compute_mode
,
5937 gen_binary (AND
, compute_mode
,
5938 gen_lowpart_for_combine
5939 (compute_mode
, SET_SRC (x
)),
5947 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5948 it is an RTX that represents a variable starting position; otherwise,
5949 POS is the (constant) starting bit position (counted from the LSB).
5951 INNER may be a USE. This will occur when we started with a bitfield
5952 that went outside the boundary of the object in memory, which is
5953 allowed on most machines. To isolate this case, we produce a USE
5954 whose mode is wide enough and surround the MEM with it. The only
5955 code that understands the USE is this routine. If it is not removed,
5956 it will cause the resulting insn not to match.
5958 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5961 IN_DEST is nonzero if this is a reference in the destination of a
5962 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5963 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5966 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5967 ZERO_EXTRACT should be built even for bits starting at bit 0.
5969 MODE is the desired mode of the result (if IN_DEST == 0).
5971 The result is an RTX for the extraction or NULL_RTX if the target
5975 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
5976 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
5977 int in_dest
, int in_compare
)
5979 /* This mode describes the size of the storage area
5980 to fetch the overall value from. Within that, we
5981 ignore the POS lowest bits, etc. */
5982 enum machine_mode is_mode
= GET_MODE (inner
);
5983 enum machine_mode inner_mode
;
5984 enum machine_mode wanted_inner_mode
= byte_mode
;
5985 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5986 enum machine_mode pos_mode
= word_mode
;
5987 enum machine_mode extraction_mode
= word_mode
;
5988 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5991 rtx orig_pos_rtx
= pos_rtx
;
5992 HOST_WIDE_INT orig_pos
;
5994 /* Get some information about INNER and get the innermost object. */
5995 if (GET_CODE (inner
) == USE
)
5996 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5997 /* We don't need to adjust the position because we set up the USE
5998 to pretend that it was a full-word object. */
5999 spans_byte
= 1, inner
= XEXP (inner
, 0);
6000 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6002 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6003 consider just the QI as the memory to extract from.
6004 The subreg adds or removes high bits; its mode is
6005 irrelevant to the meaning of this extraction,
6006 since POS and LEN count from the lsb. */
6007 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
6008 is_mode
= GET_MODE (SUBREG_REG (inner
));
6009 inner
= SUBREG_REG (inner
);
6011 else if (GET_CODE (inner
) == ASHIFT
6012 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
6013 && pos_rtx
== 0 && pos
== 0
6014 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
6016 /* We're extracting the least significant bits of an rtx
6017 (ashift X (const_int C)), where LEN > C. Extract the
6018 least significant (LEN - C) bits of X, giving an rtx
6019 whose mode is MODE, then shift it left C times. */
6020 new = make_extraction (mode
, XEXP (inner
, 0),
6021 0, 0, len
- INTVAL (XEXP (inner
, 1)),
6022 unsignedp
, in_dest
, in_compare
);
6024 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
6027 inner_mode
= GET_MODE (inner
);
6029 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6030 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6032 /* See if this can be done without an extraction. We never can if the
6033 width of the field is not the same as that of some integer mode. For
6034 registers, we can only avoid the extraction if the position is at the
6035 low-order bit and this is either not in the destination or we have the
6036 appropriate STRICT_LOW_PART operation available.
6038 For MEM, we can avoid an extract if the field starts on an appropriate
6039 boundary and we can change the mode of the memory reference. However,
6040 we cannot directly access the MEM if we have a USE and the underlying
6041 MEM is not TMODE. This combination means that MEM was being used in a
6042 context where bits outside its mode were being referenced; that is only
6043 valid in bit-field insns. */
6045 if (tmode
!= BLKmode
6046 && ! (spans_byte
&& inner_mode
!= tmode
)
6047 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6048 && GET_CODE (inner
) != MEM
6050 || (GET_CODE (inner
) == REG
6051 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6052 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6054 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6055 : BITS_PER_UNIT
)) == 0
6056 /* We can't do this if we are widening INNER_MODE (it
6057 may not be aligned, for one thing). */
6058 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6059 && (inner_mode
== tmode
6060 || (! mode_dependent_address_p (XEXP (inner
, 0))
6061 && ! MEM_VOLATILE_P (inner
))))))
6063 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6064 field. If the original and current mode are the same, we need not
6065 adjust the offset. Otherwise, we do if bytes big endian.
6067 If INNER is not a MEM, get a piece consisting of just the field
6068 of interest (in this case POS % BITS_PER_WORD must be 0). */
6070 if (GET_CODE (inner
) == MEM
)
6072 HOST_WIDE_INT offset
;
6074 /* POS counts from lsb, but make OFFSET count in memory order. */
6075 if (BYTES_BIG_ENDIAN
)
6076 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6078 offset
= pos
/ BITS_PER_UNIT
;
6080 new = adjust_address_nv (inner
, tmode
, offset
);
6082 else if (GET_CODE (inner
) == REG
)
6084 if (tmode
!= inner_mode
)
6088 /* We can't call gen_lowpart_for_combine here since we always want
6089 a SUBREG and it would sometimes return a new hard register. */
6090 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6092 if (WORDS_BIG_ENDIAN
6093 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6094 final_word
= ((GET_MODE_SIZE (inner_mode
)
6095 - GET_MODE_SIZE (tmode
))
6096 / UNITS_PER_WORD
) - final_word
;
6098 final_word
*= UNITS_PER_WORD
;
6099 if (BYTES_BIG_ENDIAN
&&
6100 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6101 final_word
+= (GET_MODE_SIZE (inner_mode
)
6102 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6104 /* Avoid creating invalid subregs, for example when
6105 simplifying (x>>32)&255. */
6106 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6109 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6112 new = gen_lowpart_for_combine (tmode
, inner
);
6118 new = force_to_mode (inner
, tmode
,
6119 len
>= HOST_BITS_PER_WIDE_INT
6120 ? ~(unsigned HOST_WIDE_INT
) 0
6121 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6124 /* If this extraction is going into the destination of a SET,
6125 make a STRICT_LOW_PART unless we made a MEM. */
6128 return (GET_CODE (new) == MEM
? new
6129 : (GET_CODE (new) != SUBREG
6130 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6131 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6136 if (GET_CODE (new) == CONST_INT
)
6137 return gen_int_mode (INTVAL (new), mode
);
6139 /* If we know that no extraneous bits are set, and that the high
6140 bit is not set, convert the extraction to the cheaper of
6141 sign and zero extension, that are equivalent in these cases. */
6142 if (flag_expensive_optimizations
6143 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6144 && ((nonzero_bits (new, tmode
)
6145 & ~(((unsigned HOST_WIDE_INT
)
6146 GET_MODE_MASK (tmode
))
6150 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6151 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6153 /* Prefer ZERO_EXTENSION, since it gives more information to
6155 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6160 /* Otherwise, sign- or zero-extend unless we already are in the
6163 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6167 /* Unless this is a COMPARE or we have a funny memory reference,
6168 don't do anything with zero-extending field extracts starting at
6169 the low-order bit since they are simple AND operations. */
6170 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6171 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6174 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6175 we would be spanning bytes or if the position is not a constant and the
6176 length is not 1. In all other cases, we would only be going outside
6177 our object in cases when an original shift would have been
6179 if (! spans_byte
&& GET_CODE (inner
) == MEM
6180 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6181 || (pos_rtx
!= 0 && len
!= 1)))
6184 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6185 and the mode for the result. */
6186 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6188 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6189 pos_mode
= mode_for_extraction (EP_insv
, 2);
6190 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6193 if (! in_dest
&& unsignedp
6194 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6196 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6197 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6198 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6201 if (! in_dest
&& ! unsignedp
6202 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6204 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6205 pos_mode
= mode_for_extraction (EP_extv
, 3);
6206 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6209 /* Never narrow an object, since that might not be safe. */
6211 if (mode
!= VOIDmode
6212 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6213 extraction_mode
= mode
;
6215 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6216 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6217 pos_mode
= GET_MODE (pos_rtx
);
6219 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6220 if we have to change the mode of memory and cannot, the desired mode is
6222 if (GET_CODE (inner
) != MEM
)
6223 wanted_inner_mode
= wanted_inner_reg_mode
;
6224 else if (inner_mode
!= wanted_inner_mode
6225 && (mode_dependent_address_p (XEXP (inner
, 0))
6226 || MEM_VOLATILE_P (inner
)))
6227 wanted_inner_mode
= extraction_mode
;
6231 if (BITS_BIG_ENDIAN
)
6233 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6234 BITS_BIG_ENDIAN style. If position is constant, compute new
6235 position. Otherwise, build subtraction.
6236 Note that POS is relative to the mode of the original argument.
6237 If it's a MEM we need to recompute POS relative to that.
6238 However, if we're extracting from (or inserting into) a register,
6239 we want to recompute POS relative to wanted_inner_mode. */
6240 int width
= (GET_CODE (inner
) == MEM
6241 ? GET_MODE_BITSIZE (is_mode
)
6242 : GET_MODE_BITSIZE (wanted_inner_mode
));
6245 pos
= width
- len
- pos
;
6248 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6249 /* POS may be less than 0 now, but we check for that below.
6250 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6253 /* If INNER has a wider mode, make it smaller. If this is a constant
6254 extract, try to adjust the byte to point to the byte containing
6256 if (wanted_inner_mode
!= VOIDmode
6257 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6258 && ((GET_CODE (inner
) == MEM
6259 && (inner_mode
== wanted_inner_mode
6260 || (! mode_dependent_address_p (XEXP (inner
, 0))
6261 && ! MEM_VOLATILE_P (inner
))))))
6265 /* The computations below will be correct if the machine is big
6266 endian in both bits and bytes or little endian in bits and bytes.
6267 If it is mixed, we must adjust. */
6269 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6270 adjust OFFSET to compensate. */
6271 if (BYTES_BIG_ENDIAN
6273 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6274 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6276 /* If this is a constant position, we can move to the desired byte. */
6279 offset
+= pos
/ BITS_PER_UNIT
;
6280 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6283 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6285 && is_mode
!= wanted_inner_mode
)
6286 offset
= (GET_MODE_SIZE (is_mode
)
6287 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6289 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6290 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6293 /* If INNER is not memory, we can always get it into the proper mode. If we
6294 are changing its mode, POS must be a constant and smaller than the size
6296 else if (GET_CODE (inner
) != MEM
)
6298 if (GET_MODE (inner
) != wanted_inner_mode
6300 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6303 inner
= force_to_mode (inner
, wanted_inner_mode
,
6305 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6306 ? ~(unsigned HOST_WIDE_INT
) 0
6307 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6312 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6313 have to zero extend. Otherwise, we can just use a SUBREG. */
6315 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6317 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6319 /* If we know that no extraneous bits are set, and that the high
6320 bit is not set, convert extraction to cheaper one - either
6321 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6323 if (flag_expensive_optimizations
6324 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6325 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6326 & ~(((unsigned HOST_WIDE_INT
)
6327 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6331 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6333 /* Prefer ZERO_EXTENSION, since it gives more information to
6335 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6340 else if (pos_rtx
!= 0
6341 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6342 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6344 /* Make POS_RTX unless we already have it and it is correct. If we don't
6345 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6347 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6348 pos_rtx
= orig_pos_rtx
;
6350 else if (pos_rtx
== 0)
6351 pos_rtx
= GEN_INT (pos
);
6353 /* Make the required operation. See if we can use existing rtx. */
6354 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6355 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6357 new = gen_lowpart_for_combine (mode
, new);
6362 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6363 with any other operations in X. Return X without that shift if so. */
6366 extract_left_shift (rtx x
, int count
)
6368 enum rtx_code code
= GET_CODE (x
);
6369 enum machine_mode mode
= GET_MODE (x
);
6375 /* This is the shift itself. If it is wide enough, we will return
6376 either the value being shifted if the shift count is equal to
6377 COUNT or a shift for the difference. */
6378 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6379 && INTVAL (XEXP (x
, 1)) >= count
)
6380 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6381 INTVAL (XEXP (x
, 1)) - count
);
6385 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6386 return simplify_gen_unary (code
, mode
, tem
, mode
);
6390 case PLUS
: case IOR
: case XOR
: case AND
:
6391 /* If we can safely shift this constant and we find the inner shift,
6392 make a new operation. */
6393 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6394 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6395 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6396 return gen_binary (code
, mode
, tem
,
6397 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6408 /* Look at the expression rooted at X. Look for expressions
6409 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6410 Form these expressions.
6412 Return the new rtx, usually just X.
6414 Also, for machines like the VAX that don't have logical shift insns,
6415 try to convert logical to arithmetic shift operations in cases where
6416 they are equivalent. This undoes the canonicalizations to logical
6417 shifts done elsewhere.
6419 We try, as much as possible, to re-use rtl expressions to save memory.
6421 IN_CODE says what kind of expression we are processing. Normally, it is
6422 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6423 being kludges), it is MEM. When processing the arguments of a comparison
6424 or a COMPARE against zero, it is COMPARE. */
6427 make_compound_operation (rtx x
, enum rtx_code in_code
)
6429 enum rtx_code code
= GET_CODE (x
);
6430 enum machine_mode mode
= GET_MODE (x
);
6431 int mode_width
= GET_MODE_BITSIZE (mode
);
6433 enum rtx_code next_code
;
6439 /* Select the code to be used in recursive calls. Once we are inside an
6440 address, we stay there. If we have a comparison, set to COMPARE,
6441 but once inside, go back to our default of SET. */
6443 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6444 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6445 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6446 : in_code
== COMPARE
? SET
: in_code
);
6448 /* Process depending on the code of this operation. If NEW is set
6449 nonzero, it will be returned. */
6454 /* Convert shifts by constants into multiplications if inside
6456 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6457 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6458 && INTVAL (XEXP (x
, 1)) >= 0)
6460 new = make_compound_operation (XEXP (x
, 0), next_code
);
6461 new = gen_rtx_MULT (mode
, new,
6462 GEN_INT ((HOST_WIDE_INT
) 1
6463 << INTVAL (XEXP (x
, 1))));
6468 /* If the second operand is not a constant, we can't do anything
6470 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6473 /* If the constant is a power of two minus one and the first operand
6474 is a logical right shift, make an extraction. */
6475 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6476 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6478 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6479 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6480 0, in_code
== COMPARE
);
6483 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6484 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6485 && subreg_lowpart_p (XEXP (x
, 0))
6486 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6487 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6489 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6491 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6492 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6493 0, in_code
== COMPARE
);
6495 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6496 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6497 || GET_CODE (XEXP (x
, 0)) == IOR
)
6498 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6499 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6500 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6502 /* Apply the distributive law, and then try to make extractions. */
6503 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6504 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6506 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6508 new = make_compound_operation (new, in_code
);
6511 /* If we are have (and (rotate X C) M) and C is larger than the number
6512 of bits in M, this is an extraction. */
6514 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6515 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6516 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6517 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6519 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6520 new = make_extraction (mode
, new,
6521 (GET_MODE_BITSIZE (mode
)
6522 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6523 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6526 /* On machines without logical shifts, if the operand of the AND is
6527 a logical shift and our mask turns off all the propagated sign
6528 bits, we can replace the logical shift with an arithmetic shift. */
6529 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6530 && !have_insn_for (LSHIFTRT
, mode
)
6531 && have_insn_for (ASHIFTRT
, mode
)
6532 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6533 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6534 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6535 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6537 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6539 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6540 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6542 gen_rtx_ASHIFTRT (mode
,
6543 make_compound_operation
6544 (XEXP (XEXP (x
, 0), 0), next_code
),
6545 XEXP (XEXP (x
, 0), 1)));
6548 /* If the constant is one less than a power of two, this might be
6549 representable by an extraction even if no shift is present.
6550 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6551 we are in a COMPARE. */
6552 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6553 new = make_extraction (mode
,
6554 make_compound_operation (XEXP (x
, 0),
6556 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6558 /* If we are in a comparison and this is an AND with a power of two,
6559 convert this into the appropriate bit extract. */
6560 else if (in_code
== COMPARE
6561 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6562 new = make_extraction (mode
,
6563 make_compound_operation (XEXP (x
, 0),
6565 i
, NULL_RTX
, 1, 1, 0, 1);
6570 /* If the sign bit is known to be zero, replace this with an
6571 arithmetic shift. */
6572 if (have_insn_for (ASHIFTRT
, mode
)
6573 && ! have_insn_for (LSHIFTRT
, mode
)
6574 && mode_width
<= HOST_BITS_PER_WIDE_INT
6575 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6577 new = gen_rtx_ASHIFTRT (mode
,
6578 make_compound_operation (XEXP (x
, 0),
6584 /* ... fall through ... */
6590 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6591 this is a SIGN_EXTRACT. */
6592 if (GET_CODE (rhs
) == CONST_INT
6593 && GET_CODE (lhs
) == ASHIFT
6594 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6595 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6597 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6598 new = make_extraction (mode
, new,
6599 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6600 NULL_RTX
, mode_width
- INTVAL (rhs
),
6601 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6605 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6606 If so, try to merge the shifts into a SIGN_EXTEND. We could
6607 also do this for some cases of SIGN_EXTRACT, but it doesn't
6608 seem worth the effort; the case checked for occurs on Alpha. */
6610 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6611 && ! (GET_CODE (lhs
) == SUBREG
6612 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6613 && GET_CODE (rhs
) == CONST_INT
6614 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6615 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6616 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6617 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6618 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6623 /* Call ourselves recursively on the inner expression. If we are
6624 narrowing the object and it has a different RTL code from
6625 what it originally did, do this SUBREG as a force_to_mode. */
6627 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6628 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6629 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6630 && subreg_lowpart_p (x
))
6632 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6635 /* If we have something other than a SUBREG, we might have
6636 done an expansion, so rerun ourselves. */
6637 if (GET_CODE (newer
) != SUBREG
)
6638 newer
= make_compound_operation (newer
, in_code
);
6643 /* If this is a paradoxical subreg, and the new code is a sign or
6644 zero extension, omit the subreg and widen the extension. If it
6645 is a regular subreg, we can still get rid of the subreg by not
6646 widening so much, or in fact removing the extension entirely. */
6647 if ((GET_CODE (tem
) == SIGN_EXTEND
6648 || GET_CODE (tem
) == ZERO_EXTEND
)
6649 && subreg_lowpart_p (x
))
6651 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6652 || (GET_MODE_SIZE (mode
) >
6653 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6655 if (! SCALAR_INT_MODE_P (mode
))
6657 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6660 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6671 x
= gen_lowpart_for_combine (mode
, new);
6672 code
= GET_CODE (x
);
6675 /* Now recursively process each operand of this operation. */
6676 fmt
= GET_RTX_FORMAT (code
);
6677 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6680 new = make_compound_operation (XEXP (x
, i
), next_code
);
6681 SUBST (XEXP (x
, i
), new);
6687 /* Given M see if it is a value that would select a field of bits
6688 within an item, but not the entire word. Return -1 if not.
6689 Otherwise, return the starting position of the field, where 0 is the
6692 *PLEN is set to the length of the field. */
6695 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6697 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6698 int pos
= exact_log2 (m
& -m
);
6704 /* Now shift off the low-order zero bits and see if we have a power of
6706 len
= exact_log2 ((m
>> pos
) + 1);
6715 /* See if X can be simplified knowing that we will only refer to it in
6716 MODE and will only refer to those bits that are nonzero in MASK.
6717 If other bits are being computed or if masking operations are done
6718 that select a superset of the bits in MASK, they can sometimes be
6721 Return a possibly simplified expression, but always convert X to
6722 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6724 Also, if REG is nonzero and X is a register equal in value to REG,
6727 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6728 are all off in X. This is used when X will be complemented, by either
6729 NOT, NEG, or XOR. */
6732 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6733 rtx reg
, int just_select
)
6735 enum rtx_code code
= GET_CODE (x
);
6736 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6737 enum machine_mode op_mode
;
6738 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6741 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6742 code below will do the wrong thing since the mode of such an
6743 expression is VOIDmode.
6745 Also do nothing if X is a CLOBBER; this can happen if X was
6746 the return value from a call to gen_lowpart_for_combine. */
6747 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6750 /* We want to perform the operation is its present mode unless we know
6751 that the operation is valid in MODE, in which case we do the operation
6753 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6754 && have_insn_for (code
, mode
))
6755 ? mode
: GET_MODE (x
));
6757 /* It is not valid to do a right-shift in a narrower mode
6758 than the one it came in with. */
6759 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6760 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6761 op_mode
= GET_MODE (x
);
6763 /* Truncate MASK to fit OP_MODE. */
6765 mask
&= GET_MODE_MASK (op_mode
);
6767 /* When we have an arithmetic operation, or a shift whose count we
6768 do not know, we need to assume that all bits up to the highest-order
6769 bit in MASK will be needed. This is how we form such a mask. */
6770 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6771 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6773 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6776 /* Determine what bits of X are guaranteed to be (non)zero. */
6777 nonzero
= nonzero_bits (x
, mode
);
6779 /* If none of the bits in X are needed, return a zero. */
6780 if (! just_select
&& (nonzero
& mask
) == 0)
6783 /* If X is a CONST_INT, return a new one. Do this here since the
6784 test below will fail. */
6785 if (GET_CODE (x
) == CONST_INT
)
6787 if (SCALAR_INT_MODE_P (mode
))
6788 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6791 x
= GEN_INT (INTVAL (x
) & mask
);
6792 return gen_lowpart_common (mode
, x
);
6796 /* If X is narrower than MODE and we want all the bits in X's mode, just
6797 get X in the proper mode. */
6798 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6799 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6800 return gen_lowpart_for_combine (mode
, x
);
6802 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6803 MASK are already known to be zero in X, we need not do anything. */
6804 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6810 /* If X is a (clobber (const_int)), return it since we know we are
6811 generating something that won't match. */
6815 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6816 spanned the boundary of the MEM. If we are now masking so it is
6817 within that boundary, we don't need the USE any more. */
6818 if (! BITS_BIG_ENDIAN
6819 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6820 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6827 x
= expand_compound_operation (x
);
6828 if (GET_CODE (x
) != code
)
6829 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6833 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6834 || rtx_equal_p (reg
, get_last_value (x
))))
6839 if (subreg_lowpart_p (x
)
6840 /* We can ignore the effect of this SUBREG if it narrows the mode or
6841 if the constant masks to zero all the bits the mode doesn't
6843 && ((GET_MODE_SIZE (GET_MODE (x
))
6844 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6846 & GET_MODE_MASK (GET_MODE (x
))
6847 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6848 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6852 /* If this is an AND with a constant, convert it into an AND
6853 whose constant is the AND of that constant with MASK. If it
6854 remains an AND of MASK, delete it since it is redundant. */
6856 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6858 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6859 mask
& INTVAL (XEXP (x
, 1)));
6861 /* If X is still an AND, see if it is an AND with a mask that
6862 is just some low-order bits. If so, and it is MASK, we don't
6865 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6866 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6870 /* If it remains an AND, try making another AND with the bits
6871 in the mode mask that aren't in MASK turned on. If the
6872 constant in the AND is wide enough, this might make a
6873 cheaper constant. */
6875 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6876 && GET_MODE_MASK (GET_MODE (x
)) != mask
6877 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6879 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6880 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6881 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6884 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6885 number, sign extend it. */
6886 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6887 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6888 cval
|= (HOST_WIDE_INT
) -1 << width
;
6890 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6891 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6901 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6902 low-order bits (as in an alignment operation) and FOO is already
6903 aligned to that boundary, mask C1 to that boundary as well.
6904 This may eliminate that PLUS and, later, the AND. */
6907 unsigned int width
= GET_MODE_BITSIZE (mode
);
6908 unsigned HOST_WIDE_INT smask
= mask
;
6910 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6911 number, sign extend it. */
6913 if (width
< HOST_BITS_PER_WIDE_INT
6914 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6915 smask
|= (HOST_WIDE_INT
) -1 << width
;
6917 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6918 && exact_log2 (- smask
) >= 0
6919 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6920 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6921 return force_to_mode (plus_constant (XEXP (x
, 0),
6922 (INTVAL (XEXP (x
, 1)) & smask
)),
6923 mode
, smask
, reg
, next_select
);
6926 /* ... fall through ... */
6929 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6930 most significant bit in MASK since carries from those bits will
6931 affect the bits we are interested in. */
6936 /* If X is (minus C Y) where C's least set bit is larger than any bit
6937 in the mask, then we may replace with (neg Y). */
6938 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6939 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6940 & -INTVAL (XEXP (x
, 0))))
6943 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6945 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6948 /* Similarly, if C contains every bit in the fuller_mask, then we may
6949 replace with (not Y). */
6950 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6951 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
6952 == INTVAL (XEXP (x
, 0))))
6954 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6955 XEXP (x
, 1), GET_MODE (x
));
6956 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6964 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6965 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6966 operation which may be a bitfield extraction. Ensure that the
6967 constant we form is not wider than the mode of X. */
6969 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6970 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6971 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6972 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6973 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6974 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6975 + floor_log2 (INTVAL (XEXP (x
, 1))))
6976 < GET_MODE_BITSIZE (GET_MODE (x
)))
6977 && (INTVAL (XEXP (x
, 1))
6978 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6980 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6981 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6982 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6983 XEXP (XEXP (x
, 0), 0), temp
);
6984 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6985 XEXP (XEXP (x
, 0), 1));
6986 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6990 /* For most binary operations, just propagate into the operation and
6991 change the mode if we have an operation of that mode. */
6993 op0
= gen_lowpart_for_combine (op_mode
,
6994 force_to_mode (XEXP (x
, 0), mode
, mask
,
6996 op1
= gen_lowpart_for_combine (op_mode
,
6997 force_to_mode (XEXP (x
, 1), mode
, mask
,
7000 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7001 x
= gen_binary (code
, op_mode
, op0
, op1
);
7005 /* For left shifts, do the same, but just for the first operand.
7006 However, we cannot do anything with shifts where we cannot
7007 guarantee that the counts are smaller than the size of the mode
7008 because such a count will have a different meaning in a
7011 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7012 && INTVAL (XEXP (x
, 1)) >= 0
7013 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7014 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7015 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7016 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7019 /* If the shift count is a constant and we can do arithmetic in
7020 the mode of the shift, refine which bits we need. Otherwise, use the
7021 conservative form of the mask. */
7022 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7023 && INTVAL (XEXP (x
, 1)) >= 0
7024 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7025 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7026 mask
>>= INTVAL (XEXP (x
, 1));
7030 op0
= gen_lowpart_for_combine (op_mode
,
7031 force_to_mode (XEXP (x
, 0), op_mode
,
7032 mask
, reg
, next_select
));
7034 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7035 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7039 /* Here we can only do something if the shift count is a constant,
7040 this shift constant is valid for the host, and we can do arithmetic
7043 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7044 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7045 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7047 rtx inner
= XEXP (x
, 0);
7048 unsigned HOST_WIDE_INT inner_mask
;
7050 /* Select the mask of the bits we need for the shift operand. */
7051 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7053 /* We can only change the mode of the shift if we can do arithmetic
7054 in the mode of the shift and INNER_MASK is no wider than the
7055 width of OP_MODE. */
7056 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7057 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7058 op_mode
= GET_MODE (x
);
7060 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7062 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7063 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7066 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7067 shift and AND produces only copies of the sign bit (C2 is one less
7068 than a power of two), we can do this with just a shift. */
7070 if (GET_CODE (x
) == LSHIFTRT
7071 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7072 /* The shift puts one of the sign bit copies in the least significant
7074 && ((INTVAL (XEXP (x
, 1))
7075 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7076 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7077 && exact_log2 (mask
+ 1) >= 0
7078 /* Number of bits left after the shift must be more than the mask
7080 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7081 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7082 /* Must be more sign bit copies than the mask needs. */
7083 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7084 >= exact_log2 (mask
+ 1)))
7085 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7086 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7087 - exact_log2 (mask
+ 1)));
7092 /* If we are just looking for the sign bit, we don't need this shift at
7093 all, even if it has a variable count. */
7094 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7095 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7096 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7097 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7099 /* If this is a shift by a constant, get a mask that contains those bits
7100 that are not copies of the sign bit. We then have two cases: If
7101 MASK only includes those bits, this can be a logical shift, which may
7102 allow simplifications. If MASK is a single-bit field not within
7103 those bits, we are requesting a copy of the sign bit and hence can
7104 shift the sign bit to the appropriate location. */
7106 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7107 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7111 /* If the considered data is wider than HOST_WIDE_INT, we can't
7112 represent a mask for all its bits in a single scalar.
7113 But we only care about the lower bits, so calculate these. */
7115 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7117 nonzero
= ~(HOST_WIDE_INT
) 0;
7119 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7120 is the number of bits a full-width mask would have set.
7121 We need only shift if these are fewer than nonzero can
7122 hold. If not, we must keep all bits set in nonzero. */
7124 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7125 < HOST_BITS_PER_WIDE_INT
)
7126 nonzero
>>= INTVAL (XEXP (x
, 1))
7127 + HOST_BITS_PER_WIDE_INT
7128 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7132 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7133 nonzero
>>= INTVAL (XEXP (x
, 1));
7136 if ((mask
& ~nonzero
) == 0
7137 || (i
= exact_log2 (mask
)) >= 0)
7139 x
= simplify_shift_const
7140 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7141 i
< 0 ? INTVAL (XEXP (x
, 1))
7142 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7144 if (GET_CODE (x
) != ASHIFTRT
)
7145 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7149 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7150 even if the shift count isn't a constant. */
7152 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7156 /* If this is a zero- or sign-extension operation that just affects bits
7157 we don't care about, remove it. Be sure the call above returned
7158 something that is still a shift. */
7160 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7161 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7162 && INTVAL (XEXP (x
, 1)) >= 0
7163 && (INTVAL (XEXP (x
, 1))
7164 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7165 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7166 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7167 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7174 /* If the shift count is constant and we can do computations
7175 in the mode of X, compute where the bits we care about are.
7176 Otherwise, we can't do anything. Don't change the mode of
7177 the shift or propagate MODE into the shift, though. */
7178 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7179 && INTVAL (XEXP (x
, 1)) >= 0)
7181 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7182 GET_MODE (x
), GEN_INT (mask
),
7184 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7186 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7187 INTVAL (temp
), reg
, next_select
));
7192 /* If we just want the low-order bit, the NEG isn't needed since it
7193 won't change the low-order bit. */
7195 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7197 /* We need any bits less significant than the most significant bit in
7198 MASK since carries from those bits will affect the bits we are
7204 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7205 same as the XOR case above. Ensure that the constant we form is not
7206 wider than the mode of X. */
7208 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7209 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7210 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7211 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7212 < GET_MODE_BITSIZE (GET_MODE (x
)))
7213 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7215 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7217 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7218 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7220 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7223 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7224 use the full mask inside the NOT. */
7228 op0
= gen_lowpart_for_combine (op_mode
,
7229 force_to_mode (XEXP (x
, 0), mode
, mask
,
7231 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7232 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7236 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7237 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7238 which is equal to STORE_FLAG_VALUE. */
7239 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7240 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7241 && (nonzero_bits (XEXP (x
, 0), mode
)
7242 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7243 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7248 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7249 written in a narrower mode. We play it safe and do not do so. */
7252 gen_lowpart_for_combine (GET_MODE (x
),
7253 force_to_mode (XEXP (x
, 1), mode
,
7254 mask
, reg
, next_select
)));
7256 gen_lowpart_for_combine (GET_MODE (x
),
7257 force_to_mode (XEXP (x
, 2), mode
,
7258 mask
, reg
, next_select
)));
7265 /* Ensure we return a value of the proper mode. */
7266 return gen_lowpart_for_combine (mode
, x
);
7269 /* Return nonzero if X is an expression that has one of two values depending on
7270 whether some other value is zero or nonzero. In that case, we return the
7271 value that is being tested, *PTRUE is set to the value if the rtx being
7272 returned has a nonzero value, and *PFALSE is set to the other alternative.
7274 If we return zero, we set *PTRUE and *PFALSE to X. */
7277 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7279 enum machine_mode mode
= GET_MODE (x
);
7280 enum rtx_code code
= GET_CODE (x
);
7281 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7282 unsigned HOST_WIDE_INT nz
;
7284 /* If we are comparing a value against zero, we are done. */
7285 if ((code
== NE
|| code
== EQ
)
7286 && XEXP (x
, 1) == const0_rtx
)
7288 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7289 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7293 /* If this is a unary operation whose operand has one of two values, apply
7294 our opcode to compute those values. */
7295 else if (GET_RTX_CLASS (code
) == '1'
7296 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7298 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7299 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7300 GET_MODE (XEXP (x
, 0)));
7304 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7305 make can't possibly match and would suppress other optimizations. */
7306 else if (code
== COMPARE
)
7309 /* If this is a binary operation, see if either side has only one of two
7310 values. If either one does or if both do and they are conditional on
7311 the same value, compute the new true and false values. */
7312 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7313 || GET_RTX_CLASS (code
) == '<')
7315 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7316 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7318 if ((cond0
!= 0 || cond1
!= 0)
7319 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7321 /* If if_then_else_cond returned zero, then true/false are the
7322 same rtl. We must copy one of them to prevent invalid rtl
7325 true0
= copy_rtx (true0
);
7326 else if (cond1
== 0)
7327 true1
= copy_rtx (true1
);
7329 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7330 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7331 return cond0
? cond0
: cond1
;
7334 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7335 operands is zero when the other is nonzero, and vice-versa,
7336 and STORE_FLAG_VALUE is 1 or -1. */
7338 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7339 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7341 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7343 rtx op0
= XEXP (XEXP (x
, 0), 1);
7344 rtx op1
= XEXP (XEXP (x
, 1), 1);
7346 cond0
= XEXP (XEXP (x
, 0), 0);
7347 cond1
= XEXP (XEXP (x
, 1), 0);
7349 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7350 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7351 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7352 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7353 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7354 || ((swap_condition (GET_CODE (cond0
))
7355 == combine_reversed_comparison_code (cond1
))
7356 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7357 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7358 && ! side_effects_p (x
))
7360 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7361 *pfalse
= gen_binary (MULT
, mode
,
7363 ? simplify_gen_unary (NEG
, mode
, op1
,
7371 /* Similarly for MULT, AND and UMIN, except that for these the result
7373 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7374 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7375 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7377 cond0
= XEXP (XEXP (x
, 0), 0);
7378 cond1
= XEXP (XEXP (x
, 1), 0);
7380 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7381 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7382 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7383 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7384 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7385 || ((swap_condition (GET_CODE (cond0
))
7386 == combine_reversed_comparison_code (cond1
))
7387 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7388 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7389 && ! side_effects_p (x
))
7391 *ptrue
= *pfalse
= const0_rtx
;
7397 else if (code
== IF_THEN_ELSE
)
7399 /* If we have IF_THEN_ELSE already, extract the condition and
7400 canonicalize it if it is NE or EQ. */
7401 cond0
= XEXP (x
, 0);
7402 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7403 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7404 return XEXP (cond0
, 0);
7405 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7407 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7408 return XEXP (cond0
, 0);
7414 /* If X is a SUBREG, we can narrow both the true and false values
7415 if the inner expression, if there is a condition. */
7416 else if (code
== SUBREG
7417 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7420 *ptrue
= simplify_gen_subreg (mode
, true0
,
7421 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7422 *pfalse
= simplify_gen_subreg (mode
, false0
,
7423 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7428 /* If X is a constant, this isn't special and will cause confusions
7429 if we treat it as such. Likewise if it is equivalent to a constant. */
7430 else if (CONSTANT_P (x
)
7431 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7434 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7435 will be least confusing to the rest of the compiler. */
7436 else if (mode
== BImode
)
7438 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7442 /* If X is known to be either 0 or -1, those are the true and
7443 false values when testing X. */
7444 else if (x
== constm1_rtx
|| x
== const0_rtx
7445 || (mode
!= VOIDmode
7446 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7448 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7452 /* Likewise for 0 or a single bit. */
7453 else if (SCALAR_INT_MODE_P (mode
)
7454 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7455 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7457 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7461 /* Otherwise fail; show no condition with true and false values the same. */
7462 *ptrue
= *pfalse
= x
;
7466 /* Return the value of expression X given the fact that condition COND
7467 is known to be true when applied to REG as its first operand and VAL
7468 as its second. X is known to not be shared and so can be modified in
7471 We only handle the simplest cases, and specifically those cases that
7472 arise with IF_THEN_ELSE expressions. */
7475 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7477 enum rtx_code code
= GET_CODE (x
);
7482 if (side_effects_p (x
))
7485 /* If either operand of the condition is a floating point value,
7486 then we have to avoid collapsing an EQ comparison. */
7488 && rtx_equal_p (x
, reg
)
7489 && ! FLOAT_MODE_P (GET_MODE (x
))
7490 && ! FLOAT_MODE_P (GET_MODE (val
)))
7493 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7496 /* If X is (abs REG) and we know something about REG's relationship
7497 with zero, we may be able to simplify this. */
7499 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7502 case GE
: case GT
: case EQ
:
7505 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7507 GET_MODE (XEXP (x
, 0)));
7512 /* The only other cases we handle are MIN, MAX, and comparisons if the
7513 operands are the same as REG and VAL. */
7515 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7517 if (rtx_equal_p (XEXP (x
, 0), val
))
7518 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7520 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7522 if (GET_RTX_CLASS (code
) == '<')
7524 if (comparison_dominates_p (cond
, code
))
7525 return const_true_rtx
;
7527 code
= combine_reversed_comparison_code (x
);
7529 && comparison_dominates_p (cond
, code
))
7534 else if (code
== SMAX
|| code
== SMIN
7535 || code
== UMIN
|| code
== UMAX
)
7537 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7539 /* Do not reverse the condition when it is NE or EQ.
7540 This is because we cannot conclude anything about
7541 the value of 'SMAX (x, y)' when x is not equal to y,
7542 but we can when x equals y. */
7543 if ((code
== SMAX
|| code
== UMAX
)
7544 && ! (cond
== EQ
|| cond
== NE
))
7545 cond
= reverse_condition (cond
);
7550 return unsignedp
? x
: XEXP (x
, 1);
7552 return unsignedp
? x
: XEXP (x
, 0);
7554 return unsignedp
? XEXP (x
, 1) : x
;
7556 return unsignedp
? XEXP (x
, 0) : x
;
7563 else if (code
== SUBREG
)
7565 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7566 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7568 if (SUBREG_REG (x
) != r
)
7570 /* We must simplify subreg here, before we lose track of the
7571 original inner_mode. */
7572 new = simplify_subreg (GET_MODE (x
), r
,
7573 inner_mode
, SUBREG_BYTE (x
));
7577 SUBST (SUBREG_REG (x
), r
);
7582 /* We don't have to handle SIGN_EXTEND here, because even in the
7583 case of replacing something with a modeless CONST_INT, a
7584 CONST_INT is already (supposed to be) a valid sign extension for
7585 its narrower mode, which implies it's already properly
7586 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7587 story is different. */
7588 else if (code
== ZERO_EXTEND
)
7590 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7591 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7593 if (XEXP (x
, 0) != r
)
7595 /* We must simplify the zero_extend here, before we lose
7596 track of the original inner_mode. */
7597 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7602 SUBST (XEXP (x
, 0), r
);
7608 fmt
= GET_RTX_FORMAT (code
);
7609 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7612 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7613 else if (fmt
[i
] == 'E')
7614 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7615 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7622 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7623 assignment as a field assignment. */
7626 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7628 if (x
== y
|| rtx_equal_p (x
, y
))
7631 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7634 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7635 Note that all SUBREGs of MEM are paradoxical; otherwise they
7636 would have been rewritten. */
7637 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7638 && GET_CODE (SUBREG_REG (y
)) == MEM
7639 && rtx_equal_p (SUBREG_REG (y
),
7640 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7643 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7644 && GET_CODE (SUBREG_REG (x
)) == MEM
7645 && rtx_equal_p (SUBREG_REG (x
),
7646 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7649 /* We used to see if get_last_value of X and Y were the same but that's
7650 not correct. In one direction, we'll cause the assignment to have
7651 the wrong destination and in the case, we'll import a register into this
7652 insn that might have already have been dead. So fail if none of the
7653 above cases are true. */
7657 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7658 Return that assignment if so.
7660 We only handle the most common cases. */
7663 make_field_assignment (rtx x
)
7665 rtx dest
= SET_DEST (x
);
7666 rtx src
= SET_SRC (x
);
7671 unsigned HOST_WIDE_INT len
;
7673 enum machine_mode mode
;
7675 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7676 a clear of a one-bit field. We will have changed it to
7677 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7680 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7681 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7682 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7683 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7685 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7688 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7692 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7693 && subreg_lowpart_p (XEXP (src
, 0))
7694 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7695 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7696 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7697 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7698 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7699 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7701 assign
= make_extraction (VOIDmode
, dest
, 0,
7702 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7705 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7709 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7711 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7712 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7713 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7715 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7718 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7722 /* The other case we handle is assignments into a constant-position
7723 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7724 a mask that has all one bits except for a group of zero bits and
7725 OTHER is known to have zeros where C1 has ones, this is such an
7726 assignment. Compute the position and length from C1. Shift OTHER
7727 to the appropriate position, force it to the required mode, and
7728 make the extraction. Check for the AND in both operands. */
7730 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7733 rhs
= expand_compound_operation (XEXP (src
, 0));
7734 lhs
= expand_compound_operation (XEXP (src
, 1));
7736 if (GET_CODE (rhs
) == AND
7737 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7738 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7739 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7740 else if (GET_CODE (lhs
) == AND
7741 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7742 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7743 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7747 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7748 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7749 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7750 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7753 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7757 /* The mode to use for the source is the mode of the assignment, or of
7758 what is inside a possible STRICT_LOW_PART. */
7759 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7760 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7762 /* Shift OTHER right POS places and make it the source, restricting it
7763 to the proper length and mode. */
7765 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7766 GET_MODE (src
), other
, pos
),
7768 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7769 ? ~(unsigned HOST_WIDE_INT
) 0
7770 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7773 /* If SRC is masked by an AND that does not make a difference in
7774 the value being stored, strip it. */
7775 if (GET_CODE (assign
) == ZERO_EXTRACT
7776 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7777 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7778 && GET_CODE (src
) == AND
7779 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7780 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7781 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7782 src
= XEXP (src
, 0);
7784 return gen_rtx_SET (VOIDmode
, assign
, src
);
7787 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7791 apply_distributive_law (rtx x
)
7793 enum rtx_code code
= GET_CODE (x
);
7794 enum rtx_code inner_code
;
7795 rtx lhs
, rhs
, other
;
7798 /* Distributivity is not true for floating point as it can change the
7799 value. So we don't do it unless -funsafe-math-optimizations. */
7800 if (FLOAT_MODE_P (GET_MODE (x
))
7801 && ! flag_unsafe_math_optimizations
)
7804 /* The outer operation can only be one of the following: */
7805 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7806 && code
!= PLUS
&& code
!= MINUS
)
7812 /* If either operand is a primitive we can't do anything, so get out
7814 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7815 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7818 lhs
= expand_compound_operation (lhs
);
7819 rhs
= expand_compound_operation (rhs
);
7820 inner_code
= GET_CODE (lhs
);
7821 if (inner_code
!= GET_CODE (rhs
))
7824 /* See if the inner and outer operations distribute. */
7831 /* These all distribute except over PLUS. */
7832 if (code
== PLUS
|| code
== MINUS
)
7837 if (code
!= PLUS
&& code
!= MINUS
)
7842 /* This is also a multiply, so it distributes over everything. */
7846 /* Non-paradoxical SUBREGs distributes over all operations, provided
7847 the inner modes and byte offsets are the same, this is an extraction
7848 of a low-order part, we don't convert an fp operation to int or
7849 vice versa, and we would not be converting a single-word
7850 operation into a multi-word operation. The latter test is not
7851 required, but it prevents generating unneeded multi-word operations.
7852 Some of the previous tests are redundant given the latter test, but
7853 are retained because they are required for correctness.
7855 We produce the result slightly differently in this case. */
7857 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7858 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7859 || ! subreg_lowpart_p (lhs
)
7860 || (GET_MODE_CLASS (GET_MODE (lhs
))
7861 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7862 || (GET_MODE_SIZE (GET_MODE (lhs
))
7863 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7864 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7867 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7868 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7869 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7875 /* Set LHS and RHS to the inner operands (A and B in the example
7876 above) and set OTHER to the common operand (C in the example).
7877 These is only one way to do this unless the inner operation is
7879 if (GET_RTX_CLASS (inner_code
) == 'c'
7880 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7881 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7882 else if (GET_RTX_CLASS (inner_code
) == 'c'
7883 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7884 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7885 else if (GET_RTX_CLASS (inner_code
) == 'c'
7886 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7887 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7888 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7889 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7893 /* Form the new inner operation, seeing if it simplifies first. */
7894 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7896 /* There is one exception to the general way of distributing:
7897 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7898 if (code
== XOR
&& inner_code
== IOR
)
7901 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7904 /* We may be able to continuing distributing the result, so call
7905 ourselves recursively on the inner operation before forming the
7906 outer operation, which we return. */
7907 return gen_binary (inner_code
, GET_MODE (x
),
7908 apply_distributive_law (tem
), other
);
7911 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7914 Return an equivalent form, if different from X. Otherwise, return X. If
7915 X is zero, we are to always construct the equivalent form. */
7918 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
7919 unsigned HOST_WIDE_INT constop
)
7921 unsigned HOST_WIDE_INT nonzero
;
7924 /* Simplify VAROP knowing that we will be only looking at some of the
7927 Note by passing in CONSTOP, we guarantee that the bits not set in
7928 CONSTOP are not significant and will never be examined. We must
7929 ensure that is the case by explicitly masking out those bits
7930 before returning. */
7931 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7933 /* If VAROP is a CLOBBER, we will fail so return it. */
7934 if (GET_CODE (varop
) == CLOBBER
)
7937 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7938 to VAROP and return the new constant. */
7939 if (GET_CODE (varop
) == CONST_INT
)
7940 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
7942 /* See what bits may be nonzero in VAROP. Unlike the general case of
7943 a call to nonzero_bits, here we don't care about bits outside
7946 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7948 /* Turn off all bits in the constant that are known to already be zero.
7949 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7950 which is tested below. */
7954 /* If we don't have any bits left, return zero. */
7958 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7959 a power of two, we can replace this with an ASHIFT. */
7960 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7961 && (i
= exact_log2 (constop
)) >= 0)
7962 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7964 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7965 or XOR, then try to apply the distributive law. This may eliminate
7966 operations if either branch can be simplified because of the AND.
7967 It may also make some cases more complex, but those cases probably
7968 won't match a pattern either with or without this. */
7970 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7972 gen_lowpart_for_combine
7974 apply_distributive_law
7975 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7976 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7977 XEXP (varop
, 0), constop
),
7978 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7979 XEXP (varop
, 1), constop
))));
7981 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7982 the AND and see if one of the operands simplifies to zero. If so, we
7983 may eliminate it. */
7985 if (GET_CODE (varop
) == PLUS
7986 && exact_log2 (constop
+ 1) >= 0)
7990 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
7991 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
7992 if (o0
== const0_rtx
)
7994 if (o1
== const0_rtx
)
7998 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7999 if we already had one (just check for the simplest cases). */
8000 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
8001 && GET_MODE (XEXP (x
, 0)) == mode
8002 && SUBREG_REG (XEXP (x
, 0)) == varop
)
8003 varop
= XEXP (x
, 0);
8005 varop
= gen_lowpart_for_combine (mode
, varop
);
8007 /* If we can't make the SUBREG, try to return what we were given. */
8008 if (GET_CODE (varop
) == CLOBBER
)
8009 return x
? x
: varop
;
8011 /* If we are only masking insignificant bits, return VAROP. */
8012 if (constop
== nonzero
)
8016 /* Otherwise, return an AND. */
8017 constop
= trunc_int_for_mode (constop
, mode
);
8018 /* See how much, if any, of X we can use. */
8019 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
8020 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
8024 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8025 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
8026 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8028 SUBST (XEXP (x
, 0), varop
);
8035 #define nonzero_bits_with_known(X, MODE) \
8036 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8038 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8039 It avoids exponential behavior in nonzero_bits1 when X has
8040 identical subexpressions on the first or the second level. */
8042 static unsigned HOST_WIDE_INT
8043 cached_nonzero_bits (rtx x
, enum machine_mode mode
, rtx known_x
,
8044 enum machine_mode known_mode
,
8045 unsigned HOST_WIDE_INT known_ret
)
8047 if (x
== known_x
&& mode
== known_mode
)
8050 /* Try to find identical subexpressions. If found call
8051 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8052 precomputed value for the subexpression as KNOWN_RET. */
8054 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8055 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8057 rtx x0
= XEXP (x
, 0);
8058 rtx x1
= XEXP (x
, 1);
8060 /* Check the first level. */
8062 return nonzero_bits1 (x
, mode
, x0
, mode
,
8063 nonzero_bits_with_known (x0
, mode
));
8065 /* Check the second level. */
8066 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8067 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8068 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8069 return nonzero_bits1 (x
, mode
, x1
, mode
,
8070 nonzero_bits_with_known (x1
, mode
));
8072 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8073 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8074 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8075 return nonzero_bits1 (x
, mode
, x0
, mode
,
8076 nonzero_bits_with_known (x0
, mode
));
8079 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
8082 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8083 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8084 is less useful. We can't allow both, because that results in exponential
8085 run time recursion. There is a nullstone testcase that triggered
8086 this. This macro avoids accidental uses of num_sign_bit_copies. */
8087 #define cached_num_sign_bit_copies()
8089 /* Given an expression, X, compute which bits in X can be nonzero.
8090 We don't care about bits outside of those defined in MODE.
8092 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8093 a shift, AND, or zero_extract, we can do better. */
8095 static unsigned HOST_WIDE_INT
8096 nonzero_bits1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8097 enum machine_mode known_mode
,
8098 unsigned HOST_WIDE_INT known_ret
)
8100 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8101 unsigned HOST_WIDE_INT inner_nz
;
8103 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8106 /* For floating-point values, assume all bits are needed. */
8107 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8110 /* If X is wider than MODE, use its mode instead. */
8111 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8113 mode
= GET_MODE (x
);
8114 nonzero
= GET_MODE_MASK (mode
);
8115 mode_width
= GET_MODE_BITSIZE (mode
);
8118 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8119 /* Our only callers in this case look for single bit values. So
8120 just return the mode mask. Those tests will then be false. */
8123 #ifndef WORD_REGISTER_OPERATIONS
8124 /* If MODE is wider than X, but both are a single word for both the host
8125 and target machines, we can compute this from which bits of the
8126 object might be nonzero in its own mode, taking into account the fact
8127 that on many CISC machines, accessing an object in a wider mode
8128 causes the high-order bits to become undefined. So they are
8129 not known to be zero. */
8131 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8132 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8133 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8134 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8136 nonzero
&= nonzero_bits_with_known (x
, GET_MODE (x
));
8137 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8142 code
= GET_CODE (x
);
8146 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8147 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8148 all the bits above ptr_mode are known to be zero. */
8149 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8151 nonzero
&= GET_MODE_MASK (ptr_mode
);
8154 /* Include declared information about alignment of pointers. */
8155 /* ??? We don't properly preserve REG_POINTER changes across
8156 pointer-to-integer casts, so we can't trust it except for
8157 things that we know must be pointers. See execute/960116-1.c. */
8158 if ((x
== stack_pointer_rtx
8159 || x
== frame_pointer_rtx
8160 || x
== arg_pointer_rtx
)
8161 && REGNO_POINTER_ALIGN (REGNO (x
)))
8163 unsigned HOST_WIDE_INT alignment
8164 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
8166 #ifdef PUSH_ROUNDING
8167 /* If PUSH_ROUNDING is defined, it is possible for the
8168 stack to be momentarily aligned only to that amount,
8169 so we pick the least alignment. */
8170 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
8171 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
8175 nonzero
&= ~(alignment
- 1);
8178 /* If X is a register whose nonzero bits value is current, use it.
8179 Otherwise, if X is a register whose value we can find, use that
8180 value. Otherwise, use the previously-computed global nonzero bits
8181 for this register. */
8183 if (reg_last_set_value
[REGNO (x
)] != 0
8184 && (reg_last_set_mode
[REGNO (x
)] == mode
8185 || (GET_MODE_CLASS (reg_last_set_mode
[REGNO (x
)]) == MODE_INT
8186 && GET_MODE_CLASS (mode
) == MODE_INT
))
8187 && (reg_last_set_label
[REGNO (x
)] == label_tick
8188 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8189 && REG_N_SETS (REGNO (x
)) == 1
8190 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8192 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8193 return reg_last_set_nonzero_bits
[REGNO (x
)] & nonzero
;
8195 tem
= get_last_value (x
);
8199 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8200 /* If X is narrower than MODE and TEM is a non-negative
8201 constant that would appear negative in the mode of X,
8202 sign-extend it for use in reg_nonzero_bits because some
8203 machines (maybe most) will actually do the sign-extension
8204 and this is the conservative approach.
8206 ??? For 2.5, try to tighten up the MD files in this regard
8207 instead of this kludge. */
8209 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8210 && GET_CODE (tem
) == CONST_INT
8212 && 0 != (INTVAL (tem
)
8213 & ((HOST_WIDE_INT
) 1
8214 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8215 tem
= GEN_INT (INTVAL (tem
)
8216 | ((HOST_WIDE_INT
) (-1)
8217 << GET_MODE_BITSIZE (GET_MODE (x
))));
8219 return nonzero_bits_with_known (tem
, mode
) & nonzero
;
8221 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8223 unsigned HOST_WIDE_INT mask
= reg_nonzero_bits
[REGNO (x
)];
8225 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
)
8226 /* We don't know anything about the upper bits. */
8227 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8228 return nonzero
& mask
;
8234 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8235 /* If X is negative in MODE, sign-extend the value. */
8236 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8237 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8238 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8244 #ifdef LOAD_EXTEND_OP
8245 /* In many, if not most, RISC machines, reading a byte from memory
8246 zeros the rest of the register. Noticing that fact saves a lot
8247 of extra zero-extends. */
8248 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8249 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8254 case UNEQ
: case LTGT
:
8255 case GT
: case GTU
: case UNGT
:
8256 case LT
: case LTU
: case UNLT
:
8257 case GE
: case GEU
: case UNGE
:
8258 case LE
: case LEU
: case UNLE
:
8259 case UNORDERED
: case ORDERED
:
8261 /* If this produces an integer result, we know which bits are set.
8262 Code here used to clear bits outside the mode of X, but that is
8265 if (GET_MODE_CLASS (mode
) == MODE_INT
8266 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8267 nonzero
= STORE_FLAG_VALUE
;
8272 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8273 and num_sign_bit_copies. */
8274 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8275 == GET_MODE_BITSIZE (GET_MODE (x
)))
8279 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8280 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8285 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8286 and num_sign_bit_copies. */
8287 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8288 == GET_MODE_BITSIZE (GET_MODE (x
)))
8294 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8295 & GET_MODE_MASK (mode
));
8299 nonzero
&= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8300 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8301 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8305 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8306 Otherwise, show all the bits in the outer mode but not the inner
8308 inner_nz
= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8309 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8311 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8313 & (((HOST_WIDE_INT
) 1
8314 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8315 inner_nz
|= (GET_MODE_MASK (mode
)
8316 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8319 nonzero
&= inner_nz
;
8323 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8324 & nonzero_bits_with_known (XEXP (x
, 1), mode
));
8328 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8330 unsigned HOST_WIDE_INT nonzero0
=
8331 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8333 /* Don't call nonzero_bits for the second time if it cannot change
8335 if ((nonzero
& nonzero0
) != nonzero
)
8336 nonzero
&= (nonzero0
8337 | nonzero_bits_with_known (XEXP (x
, 1), mode
));
8341 case PLUS
: case MINUS
:
8343 case DIV
: case UDIV
:
8344 case MOD
: case UMOD
:
8345 /* We can apply the rules of arithmetic to compute the number of
8346 high- and low-order zero bits of these operations. We start by
8347 computing the width (position of the highest-order nonzero bit)
8348 and the number of low-order zero bits for each value. */
8350 unsigned HOST_WIDE_INT nz0
=
8351 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8352 unsigned HOST_WIDE_INT nz1
=
8353 nonzero_bits_with_known (XEXP (x
, 1), mode
);
8354 int sign_index
= GET_MODE_BITSIZE (GET_MODE (x
)) - 1;
8355 int width0
= floor_log2 (nz0
) + 1;
8356 int width1
= floor_log2 (nz1
) + 1;
8357 int low0
= floor_log2 (nz0
& -nz0
);
8358 int low1
= floor_log2 (nz1
& -nz1
);
8359 HOST_WIDE_INT op0_maybe_minusp
8360 = (nz0
& ((HOST_WIDE_INT
) 1 << sign_index
));
8361 HOST_WIDE_INT op1_maybe_minusp
8362 = (nz1
& ((HOST_WIDE_INT
) 1 << sign_index
));
8363 unsigned int result_width
= mode_width
;
8369 result_width
= MAX (width0
, width1
) + 1;
8370 result_low
= MIN (low0
, low1
);
8373 result_low
= MIN (low0
, low1
);
8376 result_width
= width0
+ width1
;
8377 result_low
= low0
+ low1
;
8382 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8383 result_width
= width0
;
8388 result_width
= width0
;
8393 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8394 result_width
= MIN (width0
, width1
);
8395 result_low
= MIN (low0
, low1
);
8400 result_width
= MIN (width0
, width1
);
8401 result_low
= MIN (low0
, low1
);
8407 if (result_width
< mode_width
)
8408 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8411 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8413 #ifdef POINTERS_EXTEND_UNSIGNED
8414 /* If pointers extend unsigned and this is an addition or subtraction
8415 to a pointer in Pmode, all the bits above ptr_mode are known to be
8417 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8418 && (code
== PLUS
|| code
== MINUS
)
8419 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8420 nonzero
&= GET_MODE_MASK (ptr_mode
);
8426 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8427 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8428 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8432 /* If this is a SUBREG formed for a promoted variable that has
8433 been zero-extended, we know that at least the high-order bits
8434 are zero, though others might be too. */
8436 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
) > 0)
8437 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8438 & nonzero_bits_with_known (SUBREG_REG (x
), GET_MODE (x
)));
8440 /* If the inner mode is a single word for both the host and target
8441 machines, we can compute this from which bits of the inner
8442 object might be nonzero. */
8443 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8444 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8445 <= HOST_BITS_PER_WIDE_INT
))
8447 nonzero
&= nonzero_bits_with_known (SUBREG_REG (x
), mode
);
8449 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8450 /* If this is a typical RISC machine, we only have to worry
8451 about the way loads are extended. */
8452 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8454 & (((unsigned HOST_WIDE_INT
) 1
8455 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8457 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8458 || GET_CODE (SUBREG_REG (x
)) != MEM
)
8461 /* On many CISC machines, accessing an object in a wider mode
8462 causes the high-order bits to become undefined. So they are
8463 not known to be zero. */
8464 if (GET_MODE_SIZE (GET_MODE (x
))
8465 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8466 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8467 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8476 /* The nonzero bits are in two classes: any bits within MODE
8477 that aren't in GET_MODE (x) are always significant. The rest of the
8478 nonzero bits are those that are significant in the operand of
8479 the shift when shifted the appropriate number of bits. This
8480 shows that high-order bits are cleared by the right shift and
8481 low-order bits by left shifts. */
8482 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8483 && INTVAL (XEXP (x
, 1)) >= 0
8484 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8486 enum machine_mode inner_mode
= GET_MODE (x
);
8487 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8488 int count
= INTVAL (XEXP (x
, 1));
8489 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8490 unsigned HOST_WIDE_INT op_nonzero
=
8491 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8492 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8493 unsigned HOST_WIDE_INT outer
= 0;
8495 if (mode_width
> width
)
8496 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8498 if (code
== LSHIFTRT
)
8500 else if (code
== ASHIFTRT
)
8504 /* If the sign bit may have been nonzero before the shift, we
8505 need to mark all the places it could have been copied to
8506 by the shift as possibly nonzero. */
8507 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8508 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8510 else if (code
== ASHIFT
)
8513 inner
= ((inner
<< (count
% width
)
8514 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8516 nonzero
&= (outer
| inner
);
8522 /* This is at most the number of bits in the mode. */
8523 nonzero
= ((HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
8527 /* If CLZ has a known value at zero, then the nonzero bits are
8528 that value, plus the number of bits in the mode minus one. */
8529 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8530 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8536 /* If CTZ has a known value at zero, then the nonzero bits are
8537 that value, plus the number of bits in the mode minus one. */
8538 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8539 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8549 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 1), mode
)
8550 | nonzero_bits_with_known (XEXP (x
, 2), mode
));
8560 /* See the macro definition above. */
8561 #undef cached_num_sign_bit_copies
8563 #define num_sign_bit_copies_with_known(X, M) \
8564 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8566 /* The function cached_num_sign_bit_copies is a wrapper around
8567 num_sign_bit_copies1. It avoids exponential behavior in
8568 num_sign_bit_copies1 when X has identical subexpressions on the
8569 first or the second level. */
8572 cached_num_sign_bit_copies (rtx x
, enum machine_mode mode
, rtx known_x
,
8573 enum machine_mode known_mode
,
8574 unsigned int known_ret
)
8576 if (x
== known_x
&& mode
== known_mode
)
8579 /* Try to find identical subexpressions. If found call
8580 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8581 the precomputed value for the subexpression as KNOWN_RET. */
8583 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8584 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8586 rtx x0
= XEXP (x
, 0);
8587 rtx x1
= XEXP (x
, 1);
8589 /* Check the first level. */
8592 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8593 num_sign_bit_copies_with_known (x0
, mode
));
8595 /* Check the second level. */
8596 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8597 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8598 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8600 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
8601 num_sign_bit_copies_with_known (x1
, mode
));
8603 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8604 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8605 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8607 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8608 num_sign_bit_copies_with_known (x0
, mode
));
8611 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
8614 /* Return the number of bits at the high-order end of X that are known to
8615 be equal to the sign bit. X will be used in mode MODE; if MODE is
8616 VOIDmode, X will be used in its own mode. The returned value will always
8617 be between 1 and the number of bits in MODE. */
8620 num_sign_bit_copies1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8621 enum machine_mode known_mode
,
8622 unsigned int known_ret
)
8624 enum rtx_code code
= GET_CODE (x
);
8625 unsigned int bitwidth
;
8626 int num0
, num1
, result
;
8627 unsigned HOST_WIDE_INT nonzero
;
8630 /* If we weren't given a mode, use the mode of X. If the mode is still
8631 VOIDmode, we don't know anything. Likewise if one of the modes is
8634 if (mode
== VOIDmode
)
8635 mode
= GET_MODE (x
);
8637 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8640 bitwidth
= GET_MODE_BITSIZE (mode
);
8642 /* For a smaller object, just ignore the high bits. */
8643 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8645 num0
= num_sign_bit_copies_with_known (x
, GET_MODE (x
));
8647 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8650 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8652 #ifndef WORD_REGISTER_OPERATIONS
8653 /* If this machine does not do all register operations on the entire
8654 register and MODE is wider than the mode of X, we can say nothing
8655 at all about the high-order bits. */
8658 /* Likewise on machines that do, if the mode of the object is smaller
8659 than a word and loads of that size don't sign extend, we can say
8660 nothing about the high order bits. */
8661 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8662 #ifdef LOAD_EXTEND_OP
8663 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8674 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8675 /* If pointers extend signed and this is a pointer in Pmode, say that
8676 all the bits above ptr_mode are known to be sign bit copies. */
8677 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8679 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8682 if (reg_last_set_value
[REGNO (x
)] != 0
8683 && reg_last_set_mode
[REGNO (x
)] == mode
8684 && (reg_last_set_label
[REGNO (x
)] == label_tick
8685 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8686 && REG_N_SETS (REGNO (x
)) == 1
8687 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8689 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8690 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8692 tem
= get_last_value (x
);
8694 return num_sign_bit_copies_with_known (tem
, mode
);
8696 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0
8697 && GET_MODE_BITSIZE (GET_MODE (x
)) == bitwidth
)
8698 return reg_sign_bit_copies
[REGNO (x
)];
8702 #ifdef LOAD_EXTEND_OP
8703 /* Some RISC machines sign-extend all loads of smaller than a word. */
8704 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8705 return MAX (1, ((int) bitwidth
8706 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8711 /* If the constant is negative, take its 1's complement and remask.
8712 Then see how many zero bits we have. */
8713 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8714 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8715 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8716 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8718 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8721 /* If this is a SUBREG for a promoted object that is sign-extended
8722 and we are looking at it in a wider mode, we know that at least the
8723 high-order bits are known to be sign bit copies. */
8725 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8727 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8728 return MAX ((int) bitwidth
8729 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8733 /* For a smaller object, just ignore the high bits. */
8734 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8736 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), VOIDmode
);
8737 return MAX (1, (num0
8738 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8742 #ifdef WORD_REGISTER_OPERATIONS
8743 #ifdef LOAD_EXTEND_OP
8744 /* For paradoxical SUBREGs on machines where all register operations
8745 affect the entire register, just look inside. Note that we are
8746 passing MODE to the recursive call, so the number of sign bit copies
8747 will remain relative to that mode, not the inner mode. */
8749 /* This works only if loads sign extend. Otherwise, if we get a
8750 reload for the inner part, it may be loaded from the stack, and
8751 then we lose all sign bit copies that existed before the store
8754 if ((GET_MODE_SIZE (GET_MODE (x
))
8755 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8756 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8757 && GET_CODE (SUBREG_REG (x
)) == MEM
)
8758 return num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8764 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8765 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8769 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8770 + num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
));
8773 /* For a smaller object, just ignore the high bits. */
8774 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
);
8775 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8779 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8781 case ROTATE
: case ROTATERT
:
8782 /* If we are rotating left by a number of bits less than the number
8783 of sign bit copies, we can just subtract that amount from the
8785 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8786 && INTVAL (XEXP (x
, 1)) >= 0
8787 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8789 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8790 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8791 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8796 /* In general, this subtracts one sign bit copy. But if the value
8797 is known to be positive, the number of sign bit copies is the
8798 same as that of the input. Finally, if the input has just one bit
8799 that might be nonzero, all the bits are copies of the sign bit. */
8800 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8801 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8802 return num0
> 1 ? num0
- 1 : 1;
8804 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8809 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8814 case IOR
: case AND
: case XOR
:
8815 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8816 /* Logical operations will preserve the number of sign-bit copies.
8817 MIN and MAX operations always return one of the operands. */
8818 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8819 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8820 return MIN (num0
, num1
);
8822 case PLUS
: case MINUS
:
8823 /* For addition and subtraction, we can have a 1-bit carry. However,
8824 if we are subtracting 1 from a positive number, there will not
8825 be such a carry. Furthermore, if the positive number is known to
8826 be 0 or 1, we know the result is either -1 or 0. */
8828 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8829 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8831 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8832 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8833 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8834 : bitwidth
- floor_log2 (nonzero
) - 1);
8837 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8838 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8839 result
= MAX (1, MIN (num0
, num1
) - 1);
8841 #ifdef POINTERS_EXTEND_UNSIGNED
8842 /* If pointers extend signed and this is an addition or subtraction
8843 to a pointer in Pmode, all the bits above ptr_mode are known to be
8845 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8846 && (code
== PLUS
|| code
== MINUS
)
8847 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8848 result
= MAX ((int) (GET_MODE_BITSIZE (Pmode
)
8849 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8855 /* The number of bits of the product is the sum of the number of
8856 bits of both terms. However, unless one of the terms if known
8857 to be positive, we must allow for an additional bit since negating
8858 a negative number can remove one sign bit copy. */
8860 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8861 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8863 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8865 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8866 || (((nonzero_bits (XEXP (x
, 0), mode
)
8867 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8868 && ((nonzero_bits (XEXP (x
, 1), mode
)
8869 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8872 return MAX (1, result
);
8875 /* The result must be <= the first operand. If the first operand
8876 has the high bit set, we know nothing about the number of sign
8878 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8880 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8881 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8884 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8887 /* The result must be <= the second operand. */
8888 return num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8891 /* Similar to unsigned division, except that we have to worry about
8892 the case where the divisor is negative, in which case we have
8894 result
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8896 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8897 || (nonzero_bits (XEXP (x
, 1), mode
)
8898 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8904 result
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8906 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8907 || (nonzero_bits (XEXP (x
, 1), mode
)
8908 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8914 /* Shifts by a constant add to the number of bits equal to the
8916 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8917 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8918 && INTVAL (XEXP (x
, 1)) > 0)
8919 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8924 /* Left shifts destroy copies. */
8925 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8926 || INTVAL (XEXP (x
, 1)) < 0
8927 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8930 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8931 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8934 num0
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8935 num1
= num_sign_bit_copies_with_known (XEXP (x
, 2), mode
);
8936 return MIN (num0
, num1
);
8938 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8939 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8940 case GEU
: case GTU
: case LEU
: case LTU
:
8941 case UNORDERED
: case ORDERED
:
8942 /* If the constant is negative, take its 1's complement and remask.
8943 Then see how many zero bits we have. */
8944 nonzero
= STORE_FLAG_VALUE
;
8945 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8946 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8947 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8949 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8956 /* If we haven't been able to figure it out by one of the above rules,
8957 see if some of the high-order bits are known to be zero. If so,
8958 count those bits and return one less than that amount. If we can't
8959 safely compute the mask for this mode, always return BITWIDTH. */
8961 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8964 nonzero
= nonzero_bits (x
, mode
);
8965 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8966 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8969 /* Return the number of "extended" bits there are in X, when interpreted
8970 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8971 unsigned quantities, this is the number of high-order zero bits.
8972 For signed quantities, this is the number of copies of the sign bit
8973 minus 1. In both case, this function returns the number of "spare"
8974 bits. For example, if two quantities for which this function returns
8975 at least 1 are added, the addition is known not to overflow.
8977 This function will always return 0 unless called during combine, which
8978 implies that it must be called from a define_split. */
8981 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8983 if (nonzero_sign_valid
== 0)
8987 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8988 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8989 - floor_log2 (nonzero_bits (x
, mode
)))
8991 : num_sign_bit_copies (x
, mode
) - 1);
8994 /* This function is called from `simplify_shift_const' to merge two
8995 outer operations. Specifically, we have already found that we need
8996 to perform operation *POP0 with constant *PCONST0 at the outermost
8997 position. We would now like to also perform OP1 with constant CONST1
8998 (with *POP0 being done last).
9000 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9001 the resulting operation. *PCOMP_P is set to 1 if we would need to
9002 complement the innermost operand, otherwise it is unchanged.
9004 MODE is the mode in which the operation will be done. No bits outside
9005 the width of this mode matter. It is assumed that the width of this mode
9006 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9008 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
9009 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9010 result is simply *PCONST0.
9012 If the resulting operation cannot be expressed as one operation, we
9013 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9016 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9018 enum rtx_code op0
= *pop0
;
9019 HOST_WIDE_INT const0
= *pconst0
;
9021 const0
&= GET_MODE_MASK (mode
);
9022 const1
&= GET_MODE_MASK (mode
);
9024 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9028 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9031 if (op1
== NIL
|| op0
== SET
)
9034 else if (op0
== NIL
)
9035 op0
= op1
, const0
= const1
;
9037 else if (op0
== op1
)
9061 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9062 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9065 /* If the two constants aren't the same, we can't do anything. The
9066 remaining six cases can all be done. */
9067 else if (const0
!= const1
)
9075 /* (a & b) | b == b */
9077 else /* op1 == XOR */
9078 /* (a ^ b) | b == a | b */
9084 /* (a & b) ^ b == (~a) & b */
9085 op0
= AND
, *pcomp_p
= 1;
9086 else /* op1 == IOR */
9087 /* (a | b) ^ b == a & ~b */
9088 op0
= AND
, const0
= ~const0
;
9093 /* (a | b) & b == b */
9095 else /* op1 == XOR */
9096 /* (a ^ b) & b) == (~a) & b */
9103 /* Check for NO-OP cases. */
9104 const0
&= GET_MODE_MASK (mode
);
9106 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9108 else if (const0
== 0 && op0
== AND
)
9110 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9114 /* ??? Slightly redundant with the above mask, but not entirely.
9115 Moving this above means we'd have to sign-extend the mode mask
9116 for the final test. */
9117 const0
= trunc_int_for_mode (const0
, mode
);
9125 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9126 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9127 that we started with.
9129 The shift is normally computed in the widest mode we find in VAROP, as
9130 long as it isn't a different number of words than RESULT_MODE. Exceptions
9131 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9134 simplify_shift_const (rtx x
, enum rtx_code code
,
9135 enum machine_mode result_mode
, rtx varop
,
9138 enum rtx_code orig_code
= code
;
9141 enum machine_mode mode
= result_mode
;
9142 enum machine_mode shift_mode
, tmode
;
9143 unsigned int mode_words
9144 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9145 /* We form (outer_op (code varop count) (outer_const)). */
9146 enum rtx_code outer_op
= NIL
;
9147 HOST_WIDE_INT outer_const
= 0;
9149 int complement_p
= 0;
9152 /* Make sure and truncate the "natural" shift on the way in. We don't
9153 want to do this inside the loop as it makes it more difficult to
9155 #ifdef SHIFT_COUNT_TRUNCATED
9156 if (SHIFT_COUNT_TRUNCATED
)
9157 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9160 /* If we were given an invalid count, don't do anything except exactly
9161 what was requested. */
9163 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9168 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
9173 /* Unless one of the branches of the `if' in this loop does a `continue',
9174 we will `break' the loop after the `if'. */
9178 /* If we have an operand of (clobber (const_int 0)), just return that
9180 if (GET_CODE (varop
) == CLOBBER
)
9183 /* If we discovered we had to complement VAROP, leave. Making a NOT
9184 here would cause an infinite loop. */
9188 /* Convert ROTATERT to ROTATE. */
9189 if (code
== ROTATERT
)
9191 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9193 if (VECTOR_MODE_P (result_mode
))
9194 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9196 count
= bitsize
- count
;
9199 /* We need to determine what mode we will do the shift in. If the
9200 shift is a right shift or a ROTATE, we must always do it in the mode
9201 it was originally done in. Otherwise, we can do it in MODE, the
9202 widest mode encountered. */
9204 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9205 ? result_mode
: mode
);
9207 /* Handle cases where the count is greater than the size of the mode
9208 minus 1. For ASHIFT, use the size minus one as the count (this can
9209 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9210 take the count modulo the size. For other shifts, the result is
9213 Since these shifts are being produced by the compiler by combining
9214 multiple operations, each of which are defined, we know what the
9215 result is supposed to be. */
9217 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
9219 if (code
== ASHIFTRT
)
9220 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9221 else if (code
== ROTATE
|| code
== ROTATERT
)
9222 count
%= GET_MODE_BITSIZE (shift_mode
);
9225 /* We can't simply return zero because there may be an
9233 /* An arithmetic right shift of a quantity known to be -1 or 0
9235 if (code
== ASHIFTRT
9236 && (num_sign_bit_copies (varop
, shift_mode
)
9237 == GET_MODE_BITSIZE (shift_mode
)))
9243 /* If we are doing an arithmetic right shift and discarding all but
9244 the sign bit copies, this is equivalent to doing a shift by the
9245 bitsize minus one. Convert it into that shift because it will often
9246 allow other simplifications. */
9248 if (code
== ASHIFTRT
9249 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9250 >= GET_MODE_BITSIZE (shift_mode
)))
9251 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9253 /* We simplify the tests below and elsewhere by converting
9254 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9255 `make_compound_operation' will convert it to an ASHIFTRT for
9256 those machines (such as VAX) that don't have an LSHIFTRT. */
9257 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9259 && ((nonzero_bits (varop
, shift_mode
)
9260 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9264 if (code
== LSHIFTRT
9265 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9266 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9269 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9270 && !((nonzero_bits (varop
, shift_mode
) << count
)
9271 & GET_MODE_MASK (shift_mode
)))
9274 switch (GET_CODE (varop
))
9280 new = expand_compound_operation (varop
);
9289 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9290 minus the width of a smaller mode, we can do this with a
9291 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9292 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9293 && ! mode_dependent_address_p (XEXP (varop
, 0))
9294 && ! MEM_VOLATILE_P (varop
)
9295 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9296 MODE_INT
, 1)) != BLKmode
)
9298 new = adjust_address_nv (varop
, tmode
,
9299 BYTES_BIG_ENDIAN
? 0
9300 : count
/ BITS_PER_UNIT
);
9302 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9303 : ZERO_EXTEND
, mode
, new);
9310 /* Similar to the case above, except that we can only do this if
9311 the resulting mode is the same as that of the underlying
9312 MEM and adjust the address depending on the *bits* endianness
9313 because of the way that bit-field extract insns are defined. */
9314 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9315 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9316 MODE_INT
, 1)) != BLKmode
9317 && tmode
== GET_MODE (XEXP (varop
, 0)))
9319 if (BITS_BIG_ENDIAN
)
9320 new = XEXP (varop
, 0);
9323 new = copy_rtx (XEXP (varop
, 0));
9324 SUBST (XEXP (new, 0),
9325 plus_constant (XEXP (new, 0),
9326 count
/ BITS_PER_UNIT
));
9329 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9330 : ZERO_EXTEND
, mode
, new);
9337 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9338 the same number of words as what we've seen so far. Then store
9339 the widest mode in MODE. */
9340 if (subreg_lowpart_p (varop
)
9341 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9342 > GET_MODE_SIZE (GET_MODE (varop
)))
9343 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9344 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9347 varop
= SUBREG_REG (varop
);
9348 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9349 mode
= GET_MODE (varop
);
9355 /* Some machines use MULT instead of ASHIFT because MULT
9356 is cheaper. But it is still better on those machines to
9357 merge two shifts into one. */
9358 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9359 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9362 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9363 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9369 /* Similar, for when divides are cheaper. */
9370 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9371 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9374 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9375 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9381 /* If we are extracting just the sign bit of an arithmetic
9382 right shift, that shift is not needed. However, the sign
9383 bit of a wider mode may be different from what would be
9384 interpreted as the sign bit in a narrower mode, so, if
9385 the result is narrower, don't discard the shift. */
9386 if (code
== LSHIFTRT
9387 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9388 && (GET_MODE_BITSIZE (result_mode
)
9389 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9391 varop
= XEXP (varop
, 0);
9395 /* ... fall through ... */
9400 /* Here we have two nested shifts. The result is usually the
9401 AND of a new shift with a mask. We compute the result below. */
9402 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9403 && INTVAL (XEXP (varop
, 1)) >= 0
9404 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9405 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9406 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9408 enum rtx_code first_code
= GET_CODE (varop
);
9409 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9410 unsigned HOST_WIDE_INT mask
;
9413 /* We have one common special case. We can't do any merging if
9414 the inner code is an ASHIFTRT of a smaller mode. However, if
9415 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9416 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9417 we can convert it to
9418 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9419 This simplifies certain SIGN_EXTEND operations. */
9420 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9421 && count
== (unsigned int)
9422 (GET_MODE_BITSIZE (result_mode
)
9423 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9425 /* C3 has the low-order C1 bits zero. */
9427 mask
= (GET_MODE_MASK (mode
)
9428 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9430 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9431 XEXP (varop
, 0), mask
);
9432 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9434 count
= first_count
;
9439 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9440 than C1 high-order bits equal to the sign bit, we can convert
9441 this to either an ASHIFT or an ASHIFTRT depending on the
9444 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9446 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9447 && GET_MODE (varop
) == shift_mode
9448 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9451 varop
= XEXP (varop
, 0);
9453 signed_count
= count
- first_count
;
9454 if (signed_count
< 0)
9455 count
= -signed_count
, code
= ASHIFT
;
9457 count
= signed_count
;
9462 /* There are some cases we can't do. If CODE is ASHIFTRT,
9463 we can only do this if FIRST_CODE is also ASHIFTRT.
9465 We can't do the case when CODE is ROTATE and FIRST_CODE is
9468 If the mode of this shift is not the mode of the outer shift,
9469 we can't do this if either shift is a right shift or ROTATE.
9471 Finally, we can't do any of these if the mode is too wide
9472 unless the codes are the same.
9474 Handle the case where the shift codes are the same
9477 if (code
== first_code
)
9479 if (GET_MODE (varop
) != result_mode
9480 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9484 count
+= first_count
;
9485 varop
= XEXP (varop
, 0);
9489 if (code
== ASHIFTRT
9490 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9491 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9492 || (GET_MODE (varop
) != result_mode
9493 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9494 || first_code
== ROTATE
9495 || code
== ROTATE
)))
9498 /* To compute the mask to apply after the shift, shift the
9499 nonzero bits of the inner shift the same way the
9500 outer shift will. */
9502 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9505 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9508 /* Give up if we can't compute an outer operation to use. */
9510 || GET_CODE (mask_rtx
) != CONST_INT
9511 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9513 result_mode
, &complement_p
))
9516 /* If the shifts are in the same direction, we add the
9517 counts. Otherwise, we subtract them. */
9518 signed_count
= count
;
9519 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9520 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9521 signed_count
+= first_count
;
9523 signed_count
-= first_count
;
9525 /* If COUNT is positive, the new shift is usually CODE,
9526 except for the two exceptions below, in which case it is
9527 FIRST_CODE. If the count is negative, FIRST_CODE should
9529 if (signed_count
> 0
9530 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9531 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9532 code
= first_code
, count
= signed_count
;
9533 else if (signed_count
< 0)
9534 code
= first_code
, count
= -signed_count
;
9536 count
= signed_count
;
9538 varop
= XEXP (varop
, 0);
9542 /* If we have (A << B << C) for any shift, we can convert this to
9543 (A << C << B). This wins if A is a constant. Only try this if
9544 B is not a constant. */
9546 else if (GET_CODE (varop
) == code
9547 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9549 = simplify_binary_operation (code
, mode
,
9553 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9560 /* Make this fit the case below. */
9561 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9562 GEN_INT (GET_MODE_MASK (mode
)));
9568 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9569 with C the size of VAROP - 1 and the shift is logical if
9570 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9571 we have an (le X 0) operation. If we have an arithmetic shift
9572 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9573 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9575 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9576 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9577 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9578 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9579 && count
== (unsigned int)
9580 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9581 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9584 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9587 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9588 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9593 /* If we have (shift (logical)), move the logical to the outside
9594 to allow it to possibly combine with another logical and the
9595 shift to combine with another shift. This also canonicalizes to
9596 what a ZERO_EXTRACT looks like. Also, some machines have
9597 (and (shift)) insns. */
9599 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9600 && (new = simplify_binary_operation (code
, result_mode
,
9602 GEN_INT (count
))) != 0
9603 && GET_CODE (new) == CONST_INT
9604 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9605 INTVAL (new), result_mode
, &complement_p
))
9607 varop
= XEXP (varop
, 0);
9611 /* If we can't do that, try to simplify the shift in each arm of the
9612 logical expression, make a new logical expression, and apply
9613 the inverse distributive law. */
9615 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9616 XEXP (varop
, 0), count
);
9617 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9618 XEXP (varop
, 1), count
);
9620 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9621 varop
= apply_distributive_law (varop
);
9628 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9629 says that the sign bit can be tested, FOO has mode MODE, C is
9630 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9631 that may be nonzero. */
9632 if (code
== LSHIFTRT
9633 && XEXP (varop
, 1) == const0_rtx
9634 && GET_MODE (XEXP (varop
, 0)) == result_mode
9635 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9636 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9637 && ((STORE_FLAG_VALUE
9638 & ((HOST_WIDE_INT
) 1
9639 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9640 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9641 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9642 (HOST_WIDE_INT
) 1, result_mode
,
9645 varop
= XEXP (varop
, 0);
9652 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9653 than the number of bits in the mode is equivalent to A. */
9654 if (code
== LSHIFTRT
9655 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9656 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9658 varop
= XEXP (varop
, 0);
9663 /* NEG commutes with ASHIFT since it is multiplication. Move the
9664 NEG outside to allow shifts to combine. */
9666 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9667 (HOST_WIDE_INT
) 0, result_mode
,
9670 varop
= XEXP (varop
, 0);
9676 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9677 is one less than the number of bits in the mode is
9678 equivalent to (xor A 1). */
9679 if (code
== LSHIFTRT
9680 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9681 && XEXP (varop
, 1) == constm1_rtx
9682 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9683 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9684 (HOST_WIDE_INT
) 1, result_mode
,
9688 varop
= XEXP (varop
, 0);
9692 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9693 that might be nonzero in BAR are those being shifted out and those
9694 bits are known zero in FOO, we can replace the PLUS with FOO.
9695 Similarly in the other operand order. This code occurs when
9696 we are computing the size of a variable-size array. */
9698 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9699 && count
< HOST_BITS_PER_WIDE_INT
9700 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9701 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9702 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9704 varop
= XEXP (varop
, 0);
9707 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9708 && count
< HOST_BITS_PER_WIDE_INT
9709 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9710 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9712 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9713 & nonzero_bits (XEXP (varop
, 1),
9716 varop
= XEXP (varop
, 1);
9720 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9722 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9723 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9725 GEN_INT (count
))) != 0
9726 && GET_CODE (new) == CONST_INT
9727 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9728 INTVAL (new), result_mode
, &complement_p
))
9730 varop
= XEXP (varop
, 0);
9736 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9737 with C the size of VAROP - 1 and the shift is logical if
9738 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9739 we have a (gt X 0) operation. If the shift is arithmetic with
9740 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9741 we have a (neg (gt X 0)) operation. */
9743 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9744 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9745 && count
== (unsigned int)
9746 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9747 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9748 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9749 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9751 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9754 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9757 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9758 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9765 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9766 if the truncate does not affect the value. */
9767 if (code
== LSHIFTRT
9768 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9769 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9770 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9771 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9772 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9774 rtx varop_inner
= XEXP (varop
, 0);
9777 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9778 XEXP (varop_inner
, 0),
9780 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9781 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9794 /* We need to determine what mode to do the shift in. If the shift is
9795 a right shift or ROTATE, we must always do it in the mode it was
9796 originally done in. Otherwise, we can do it in MODE, the widest mode
9797 encountered. The code we care about is that of the shift that will
9798 actually be done, not the shift that was originally requested. */
9800 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9801 ? result_mode
: mode
);
9803 /* We have now finished analyzing the shift. The result should be
9804 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9805 OUTER_OP is non-NIL, it is an operation that needs to be applied
9806 to the result of the shift. OUTER_CONST is the relevant constant,
9807 but we must turn off all bits turned off in the shift.
9809 If we were passed a value for X, see if we can use any pieces of
9810 it. If not, make new rtx. */
9812 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9813 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9814 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9815 const_rtx
= XEXP (x
, 1);
9817 const_rtx
= GEN_INT (count
);
9819 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9820 && GET_MODE (XEXP (x
, 0)) == shift_mode
9821 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9822 varop
= XEXP (x
, 0);
9823 else if (GET_MODE (varop
) != shift_mode
)
9824 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9826 /* If we can't make the SUBREG, try to return what we were given. */
9827 if (GET_CODE (varop
) == CLOBBER
)
9828 return x
? x
: varop
;
9830 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9834 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9836 /* If we have an outer operation and we just made a shift, it is
9837 possible that we could have simplified the shift were it not
9838 for the outer operation. So try to do the simplification
9841 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9842 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9843 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9844 INTVAL (XEXP (x
, 1)));
9846 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9847 turn off all the bits that the shift would have turned off. */
9848 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9849 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9850 GET_MODE_MASK (result_mode
) >> orig_count
);
9852 /* Do the remainder of the processing in RESULT_MODE. */
9853 x
= gen_lowpart_for_combine (result_mode
, x
);
9855 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9858 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9860 if (outer_op
!= NIL
)
9862 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9863 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9865 if (outer_op
== AND
)
9866 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9867 else if (outer_op
== SET
)
9868 /* This means that we have determined that the result is
9869 equivalent to a constant. This should be rare. */
9870 x
= GEN_INT (outer_const
);
9871 else if (GET_RTX_CLASS (outer_op
) == '1')
9872 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9874 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9880 /* Like recog, but we receive the address of a pointer to a new pattern.
9881 We try to match the rtx that the pointer points to.
9882 If that fails, we may try to modify or replace the pattern,
9883 storing the replacement into the same pointer object.
9885 Modifications include deletion or addition of CLOBBERs.
9887 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9888 the CLOBBERs are placed.
9890 The value is the final insn code from the pattern ultimately matched,
9894 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9897 int insn_code_number
;
9898 int num_clobbers_to_add
= 0;
9903 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9904 we use to indicate that something didn't match. If we find such a
9905 thing, force rejection. */
9906 if (GET_CODE (pat
) == PARALLEL
)
9907 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9908 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9909 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9912 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9913 instruction for pattern recognition. */
9914 dummy_insn
= shallow_copy_rtx (insn
);
9915 PATTERN (dummy_insn
) = pat
;
9916 REG_NOTES (dummy_insn
) = 0;
9918 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
9920 /* If it isn't, there is the possibility that we previously had an insn
9921 that clobbered some register as a side effect, but the combined
9922 insn doesn't need to do that. So try once more without the clobbers
9923 unless this represents an ASM insn. */
9925 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9926 && GET_CODE (pat
) == PARALLEL
)
9930 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9931 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9934 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9938 SUBST_INT (XVECLEN (pat
, 0), pos
);
9941 pat
= XVECEXP (pat
, 0, 0);
9943 PATTERN (dummy_insn
) = pat
;
9944 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
9947 /* Recognize all noop sets, these will be killed by followup pass. */
9948 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9949 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9951 /* If we had any clobbers to add, make a new pattern than contains
9952 them. Then check to make sure that all of them are dead. */
9953 if (num_clobbers_to_add
)
9955 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9956 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9958 + num_clobbers_to_add
)
9959 : num_clobbers_to_add
+ 1));
9961 if (GET_CODE (pat
) == PARALLEL
)
9962 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9963 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9965 XVECEXP (newpat
, 0, 0) = pat
;
9967 add_clobbers (newpat
, insn_code_number
);
9969 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9970 i
< XVECLEN (newpat
, 0); i
++)
9972 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9973 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9975 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9976 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9984 return insn_code_number
;
9987 /* Like gen_lowpart but for use by combine. In combine it is not possible
9988 to create any new pseudoregs. However, it is safe to create
9989 invalid memory addresses, because combine will try to recognize
9990 them and all they will do is make the combine attempt fail.
9992 If for some reason this cannot do its job, an rtx
9993 (clobber (const_int 0)) is returned.
9994 An insn containing that will not be recognized. */
9999 gen_lowpart_for_combine (enum machine_mode mode
, rtx x
)
10003 if (GET_MODE (x
) == mode
)
10006 /* Return identity if this is a CONST or symbolic
10009 && (GET_CODE (x
) == CONST
10010 || GET_CODE (x
) == SYMBOL_REF
10011 || GET_CODE (x
) == LABEL_REF
))
10014 /* We can only support MODE being wider than a word if X is a
10015 constant integer or has a mode the same size. */
10017 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
10018 && ! ((GET_MODE (x
) == VOIDmode
10019 && (GET_CODE (x
) == CONST_INT
10020 || GET_CODE (x
) == CONST_DOUBLE
))
10021 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
10022 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10024 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10025 won't know what to do. So we will strip off the SUBREG here and
10026 process normally. */
10027 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
10029 x
= SUBREG_REG (x
);
10030 if (GET_MODE (x
) == mode
)
10034 result
= gen_lowpart_common (mode
, x
);
10035 #ifdef CANNOT_CHANGE_MODE_CLASS
10037 && GET_CODE (result
) == SUBREG
10038 && GET_CODE (SUBREG_REG (result
)) == REG
10039 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
)
10040 bitmap_set_bit (&subregs_of_mode
, REGNO (SUBREG_REG (result
))
10042 + GET_MODE (result
));
10048 if (GET_CODE (x
) == MEM
)
10052 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10054 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10055 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10057 /* If we want to refer to something bigger than the original memref,
10058 generate a perverse subreg instead. That will force a reload
10059 of the original memref X. */
10060 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
10061 return gen_rtx_SUBREG (mode
, x
, 0);
10063 if (WORDS_BIG_ENDIAN
)
10064 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
10065 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
10067 if (BYTES_BIG_ENDIAN
)
10069 /* Adjust the address so that the address-after-the-data is
10071 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
10072 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
10075 return adjust_address_nv (x
, mode
, offset
);
10078 /* If X is a comparison operator, rewrite it in a new mode. This
10079 probably won't match, but may allow further simplifications. */
10080 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
10081 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
10083 /* If we couldn't simplify X any other way, just enclose it in a
10084 SUBREG. Normally, this SUBREG won't match, but some patterns may
10085 include an explicit SUBREG or we may simplify it further in combine. */
10090 enum machine_mode sub_mode
= GET_MODE (x
);
10092 offset
= subreg_lowpart_offset (mode
, sub_mode
);
10093 if (sub_mode
== VOIDmode
)
10095 sub_mode
= int_mode_for_mode (mode
);
10096 x
= gen_lowpart_common (sub_mode
, x
);
10098 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
10100 res
= simplify_gen_subreg (mode
, x
, sub_mode
, offset
);
10103 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10107 /* These routines make binary and unary operations by first seeing if they
10108 fold; if not, a new expression is allocated. */
10111 gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
, rtx op1
)
10116 if (GET_CODE (op0
) == CLOBBER
)
10118 else if (GET_CODE (op1
) == CLOBBER
)
10121 if (GET_RTX_CLASS (code
) == 'c'
10122 && swap_commutative_operands_p (op0
, op1
))
10123 tem
= op0
, op0
= op1
, op1
= tem
;
10125 if (GET_RTX_CLASS (code
) == '<')
10127 enum machine_mode op_mode
= GET_MODE (op0
);
10129 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10130 just (REL_OP X Y). */
10131 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
10133 op1
= XEXP (op0
, 1);
10134 op0
= XEXP (op0
, 0);
10135 op_mode
= GET_MODE (op0
);
10138 if (op_mode
== VOIDmode
)
10139 op_mode
= GET_MODE (op1
);
10140 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
10143 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10148 /* Put complex operands first and constants second. */
10149 if (GET_RTX_CLASS (code
) == 'c'
10150 && swap_commutative_operands_p (op0
, op1
))
10151 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
10153 /* If we are turning off bits already known off in OP0, we need not do
10155 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10156 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10157 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10160 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
10163 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10164 comparison code that will be tested.
10166 The result is a possibly different comparison code to use. *POP0 and
10167 *POP1 may be updated.
10169 It is possible that we might detect that a comparison is either always
10170 true or always false. However, we do not perform general constant
10171 folding in combine, so this knowledge isn't useful. Such tautologies
10172 should have been detected earlier. Hence we ignore all such cases. */
10174 static enum rtx_code
10175 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10181 enum machine_mode mode
, tmode
;
10183 /* Try a few ways of applying the same transformation to both operands. */
10186 #ifndef WORD_REGISTER_OPERATIONS
10187 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10188 so check specially. */
10189 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10190 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10191 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10192 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10193 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10194 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10195 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10196 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10197 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10198 && XEXP (op0
, 1) == XEXP (op1
, 1)
10199 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10200 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10201 && (INTVAL (XEXP (op0
, 1))
10202 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10203 - (GET_MODE_BITSIZE
10204 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10206 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10207 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10211 /* If both operands are the same constant shift, see if we can ignore the
10212 shift. We can if the shift is a rotate or if the bits shifted out of
10213 this shift are known to be zero for both inputs and if the type of
10214 comparison is compatible with the shift. */
10215 if (GET_CODE (op0
) == GET_CODE (op1
)
10216 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10217 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10218 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10219 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10220 || (GET_CODE (op0
) == ASHIFTRT
10221 && (code
!= GTU
&& code
!= LTU
10222 && code
!= GEU
&& code
!= LEU
)))
10223 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10224 && INTVAL (XEXP (op0
, 1)) >= 0
10225 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10226 && XEXP (op0
, 1) == XEXP (op1
, 1))
10228 enum machine_mode mode
= GET_MODE (op0
);
10229 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10230 int shift_count
= INTVAL (XEXP (op0
, 1));
10232 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10233 mask
&= (mask
>> shift_count
) << shift_count
;
10234 else if (GET_CODE (op0
) == ASHIFT
)
10235 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10237 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10238 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10239 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10244 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10245 SUBREGs are of the same mode, and, in both cases, the AND would
10246 be redundant if the comparison was done in the narrower mode,
10247 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10248 and the operand's possibly nonzero bits are 0xffffff01; in that case
10249 if we only care about QImode, we don't need the AND). This case
10250 occurs if the output mode of an scc insn is not SImode and
10251 STORE_FLAG_VALUE == 1 (e.g., the 386).
10253 Similarly, check for a case where the AND's are ZERO_EXTEND
10254 operations from some narrower mode even though a SUBREG is not
10257 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10258 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10259 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10261 rtx inner_op0
= XEXP (op0
, 0);
10262 rtx inner_op1
= XEXP (op1
, 0);
10263 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10264 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10267 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10268 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10269 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10270 && (GET_MODE (SUBREG_REG (inner_op0
))
10271 == GET_MODE (SUBREG_REG (inner_op1
)))
10272 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10273 <= HOST_BITS_PER_WIDE_INT
)
10274 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10275 GET_MODE (SUBREG_REG (inner_op0
)))))
10276 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10277 GET_MODE (SUBREG_REG (inner_op1
))))))
10279 op0
= SUBREG_REG (inner_op0
);
10280 op1
= SUBREG_REG (inner_op1
);
10282 /* The resulting comparison is always unsigned since we masked
10283 off the original sign bit. */
10284 code
= unsigned_condition (code
);
10290 for (tmode
= GET_CLASS_NARROWEST_MODE
10291 (GET_MODE_CLASS (GET_MODE (op0
)));
10292 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10293 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10295 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
10296 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
10297 code
= unsigned_condition (code
);
10306 /* If both operands are NOT, we can strip off the outer operation
10307 and adjust the comparison code for swapped operands; similarly for
10308 NEG, except that this must be an equality comparison. */
10309 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10310 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10311 && (code
== EQ
|| code
== NE
)))
10312 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10318 /* If the first operand is a constant, swap the operands and adjust the
10319 comparison code appropriately, but don't do this if the second operand
10320 is already a constant integer. */
10321 if (swap_commutative_operands_p (op0
, op1
))
10323 tem
= op0
, op0
= op1
, op1
= tem
;
10324 code
= swap_condition (code
);
10327 /* We now enter a loop during which we will try to simplify the comparison.
10328 For the most part, we only are concerned with comparisons with zero,
10329 but some things may really be comparisons with zero but not start
10330 out looking that way. */
10332 while (GET_CODE (op1
) == CONST_INT
)
10334 enum machine_mode mode
= GET_MODE (op0
);
10335 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10336 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10337 int equality_comparison_p
;
10338 int sign_bit_comparison_p
;
10339 int unsigned_comparison_p
;
10340 HOST_WIDE_INT const_op
;
10342 /* We only want to handle integral modes. This catches VOIDmode,
10343 CCmode, and the floating-point modes. An exception is that we
10344 can handle VOIDmode if OP0 is a COMPARE or a comparison
10347 if (GET_MODE_CLASS (mode
) != MODE_INT
10348 && ! (mode
== VOIDmode
10349 && (GET_CODE (op0
) == COMPARE
10350 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10353 /* Get the constant we are comparing against and turn off all bits
10354 not on in our mode. */
10355 const_op
= INTVAL (op1
);
10356 if (mode
!= VOIDmode
)
10357 const_op
= trunc_int_for_mode (const_op
, mode
);
10358 op1
= GEN_INT (const_op
);
10360 /* If we are comparing against a constant power of two and the value
10361 being compared can only have that single bit nonzero (e.g., it was
10362 `and'ed with that bit), we can replace this with a comparison
10365 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10366 || code
== LT
|| code
== LTU
)
10367 && mode_width
<= HOST_BITS_PER_WIDE_INT
10368 && exact_log2 (const_op
) >= 0
10369 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10371 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10372 op1
= const0_rtx
, const_op
= 0;
10375 /* Similarly, if we are comparing a value known to be either -1 or
10376 0 with -1, change it to the opposite comparison against zero. */
10379 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10380 || code
== GEU
|| code
== LTU
)
10381 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10383 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10384 op1
= const0_rtx
, const_op
= 0;
10387 /* Do some canonicalizations based on the comparison code. We prefer
10388 comparisons against zero and then prefer equality comparisons.
10389 If we can reduce the size of a constant, we will do that too. */
10394 /* < C is equivalent to <= (C - 1) */
10398 op1
= GEN_INT (const_op
);
10400 /* ... fall through to LE case below. */
10406 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10410 op1
= GEN_INT (const_op
);
10414 /* If we are doing a <= 0 comparison on a value known to have
10415 a zero sign bit, we can replace this with == 0. */
10416 else if (const_op
== 0
10417 && mode_width
<= HOST_BITS_PER_WIDE_INT
10418 && (nonzero_bits (op0
, mode
)
10419 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10424 /* >= C is equivalent to > (C - 1). */
10428 op1
= GEN_INT (const_op
);
10430 /* ... fall through to GT below. */
10436 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10440 op1
= GEN_INT (const_op
);
10444 /* If we are doing a > 0 comparison on a value known to have
10445 a zero sign bit, we can replace this with != 0. */
10446 else if (const_op
== 0
10447 && mode_width
<= HOST_BITS_PER_WIDE_INT
10448 && (nonzero_bits (op0
, mode
)
10449 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10454 /* < C is equivalent to <= (C - 1). */
10458 op1
= GEN_INT (const_op
);
10460 /* ... fall through ... */
10463 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10464 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10465 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10467 const_op
= 0, op1
= const0_rtx
;
10475 /* unsigned <= 0 is equivalent to == 0 */
10479 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10480 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10481 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10483 const_op
= 0, op1
= const0_rtx
;
10489 /* >= C is equivalent to < (C - 1). */
10493 op1
= GEN_INT (const_op
);
10495 /* ... fall through ... */
10498 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10499 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10500 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10502 const_op
= 0, op1
= const0_rtx
;
10510 /* unsigned > 0 is equivalent to != 0 */
10514 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10515 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10516 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10518 const_op
= 0, op1
= const0_rtx
;
10527 /* Compute some predicates to simplify code below. */
10529 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10530 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10531 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10534 /* If this is a sign bit comparison and we can do arithmetic in
10535 MODE, say that we will only be needing the sign bit of OP0. */
10536 if (sign_bit_comparison_p
10537 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10538 op0
= force_to_mode (op0
, mode
,
10540 << (GET_MODE_BITSIZE (mode
) - 1)),
10543 /* Now try cases based on the opcode of OP0. If none of the cases
10544 does a "continue", we exit this loop immediately after the
10547 switch (GET_CODE (op0
))
10550 /* If we are extracting a single bit from a variable position in
10551 a constant that has only a single bit set and are comparing it
10552 with zero, we can convert this into an equality comparison
10553 between the position and the location of the single bit. */
10555 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10556 && XEXP (op0
, 1) == const1_rtx
10557 && equality_comparison_p
&& const_op
== 0
10558 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10560 if (BITS_BIG_ENDIAN
)
10562 enum machine_mode new_mode
10563 = mode_for_extraction (EP_extzv
, 1);
10564 if (new_mode
== MAX_MACHINE_MODE
)
10565 i
= BITS_PER_WORD
- 1 - i
;
10569 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10573 op0
= XEXP (op0
, 2);
10577 /* Result is nonzero iff shift count is equal to I. */
10578 code
= reverse_condition (code
);
10582 /* ... fall through ... */
10585 tem
= expand_compound_operation (op0
);
10594 /* If testing for equality, we can take the NOT of the constant. */
10595 if (equality_comparison_p
10596 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10598 op0
= XEXP (op0
, 0);
10603 /* If just looking at the sign bit, reverse the sense of the
10605 if (sign_bit_comparison_p
)
10607 op0
= XEXP (op0
, 0);
10608 code
= (code
== GE
? LT
: GE
);
10614 /* If testing for equality, we can take the NEG of the constant. */
10615 if (equality_comparison_p
10616 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10618 op0
= XEXP (op0
, 0);
10623 /* The remaining cases only apply to comparisons with zero. */
10627 /* When X is ABS or is known positive,
10628 (neg X) is < 0 if and only if X != 0. */
10630 if (sign_bit_comparison_p
10631 && (GET_CODE (XEXP (op0
, 0)) == ABS
10632 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10633 && (nonzero_bits (XEXP (op0
, 0), mode
)
10634 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10636 op0
= XEXP (op0
, 0);
10637 code
= (code
== LT
? NE
: EQ
);
10641 /* If we have NEG of something whose two high-order bits are the
10642 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10643 if (num_sign_bit_copies (op0
, mode
) >= 2)
10645 op0
= XEXP (op0
, 0);
10646 code
= swap_condition (code
);
10652 /* If we are testing equality and our count is a constant, we
10653 can perform the inverse operation on our RHS. */
10654 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10655 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10656 op1
, XEXP (op0
, 1))) != 0)
10658 op0
= XEXP (op0
, 0);
10663 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10664 a particular bit. Convert it to an AND of a constant of that
10665 bit. This will be converted into a ZERO_EXTRACT. */
10666 if (const_op
== 0 && sign_bit_comparison_p
10667 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10668 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10670 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10673 - INTVAL (XEXP (op0
, 1)))));
10674 code
= (code
== LT
? NE
: EQ
);
10678 /* Fall through. */
10681 /* ABS is ignorable inside an equality comparison with zero. */
10682 if (const_op
== 0 && equality_comparison_p
)
10684 op0
= XEXP (op0
, 0);
10690 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10691 to (compare FOO CONST) if CONST fits in FOO's mode and we
10692 are either testing inequality or have an unsigned comparison
10693 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10694 if (! unsigned_comparison_p
10695 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10696 <= HOST_BITS_PER_WIDE_INT
)
10697 && ((unsigned HOST_WIDE_INT
) const_op
10698 < (((unsigned HOST_WIDE_INT
) 1
10699 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10701 op0
= XEXP (op0
, 0);
10707 /* Check for the case where we are comparing A - C1 with C2,
10708 both constants are smaller than 1/2 the maximum positive
10709 value in MODE, and the comparison is equality or unsigned.
10710 In that case, if A is either zero-extended to MODE or has
10711 sufficient sign bits so that the high-order bit in MODE
10712 is a copy of the sign in the inner mode, we can prove that it is
10713 safe to do the operation in the wider mode. This simplifies
10714 many range checks. */
10716 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10717 && subreg_lowpart_p (op0
)
10718 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10719 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10720 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10721 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10722 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10723 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10724 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10725 GET_MODE (SUBREG_REG (op0
)))
10726 & ~GET_MODE_MASK (mode
))
10727 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10728 GET_MODE (SUBREG_REG (op0
)))
10730 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10731 - GET_MODE_BITSIZE (mode
)))))
10733 op0
= SUBREG_REG (op0
);
10737 /* If the inner mode is narrower and we are extracting the low part,
10738 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10739 if (subreg_lowpart_p (op0
)
10740 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10741 /* Fall through */ ;
10745 /* ... fall through ... */
10748 if ((unsigned_comparison_p
|| equality_comparison_p
)
10749 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10750 <= HOST_BITS_PER_WIDE_INT
)
10751 && ((unsigned HOST_WIDE_INT
) const_op
10752 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10754 op0
= XEXP (op0
, 0);
10760 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10761 this for equality comparisons due to pathological cases involving
10763 if (equality_comparison_p
10764 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10765 op1
, XEXP (op0
, 1))))
10767 op0
= XEXP (op0
, 0);
10772 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10773 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10774 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10776 op0
= XEXP (XEXP (op0
, 0), 0);
10777 code
= (code
== LT
? EQ
: NE
);
10783 /* We used to optimize signed comparisons against zero, but that
10784 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10785 arrive here as equality comparisons, or (GEU, LTU) are
10786 optimized away. No need to special-case them. */
10788 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10789 (eq B (minus A C)), whichever simplifies. We can only do
10790 this for equality comparisons due to pathological cases involving
10792 if (equality_comparison_p
10793 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10794 XEXP (op0
, 1), op1
)))
10796 op0
= XEXP (op0
, 0);
10801 if (equality_comparison_p
10802 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10803 XEXP (op0
, 0), op1
)))
10805 op0
= XEXP (op0
, 1);
10810 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10811 of bits in X minus 1, is one iff X > 0. */
10812 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10813 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10814 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10816 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10818 op0
= XEXP (op0
, 1);
10819 code
= (code
== GE
? LE
: GT
);
10825 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10826 if C is zero or B is a constant. */
10827 if (equality_comparison_p
10828 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10829 XEXP (op0
, 1), op1
)))
10831 op0
= XEXP (op0
, 0);
10838 case UNEQ
: case LTGT
:
10839 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10840 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10841 case UNORDERED
: case ORDERED
:
10842 /* We can't do anything if OP0 is a condition code value, rather
10843 than an actual data value. */
10845 || CC0_P (XEXP (op0
, 0))
10846 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10849 /* Get the two operands being compared. */
10850 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10851 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10853 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10855 /* Check for the cases where we simply want the result of the
10856 earlier test or the opposite of that result. */
10857 if (code
== NE
|| code
== EQ
10858 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10859 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10860 && (STORE_FLAG_VALUE
10861 & (((HOST_WIDE_INT
) 1
10862 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10863 && (code
== LT
|| code
== GE
)))
10865 enum rtx_code new_code
;
10866 if (code
== LT
|| code
== NE
)
10867 new_code
= GET_CODE (op0
);
10869 new_code
= combine_reversed_comparison_code (op0
);
10871 if (new_code
!= UNKNOWN
)
10882 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10884 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10885 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10886 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10888 op0
= XEXP (op0
, 1);
10889 code
= (code
== GE
? GT
: LE
);
10895 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10896 will be converted to a ZERO_EXTRACT later. */
10897 if (const_op
== 0 && equality_comparison_p
10898 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10899 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10901 op0
= simplify_and_const_int
10902 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10904 XEXP (XEXP (op0
, 0), 1)),
10905 (HOST_WIDE_INT
) 1);
10909 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10910 zero and X is a comparison and C1 and C2 describe only bits set
10911 in STORE_FLAG_VALUE, we can compare with X. */
10912 if (const_op
== 0 && equality_comparison_p
10913 && mode_width
<= HOST_BITS_PER_WIDE_INT
10914 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10915 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10916 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10917 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10918 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10920 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10921 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10922 if ((~STORE_FLAG_VALUE
& mask
) == 0
10923 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10924 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10925 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10927 op0
= XEXP (XEXP (op0
, 0), 0);
10932 /* If we are doing an equality comparison of an AND of a bit equal
10933 to the sign bit, replace this with a LT or GE comparison of
10934 the underlying value. */
10935 if (equality_comparison_p
10937 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10938 && mode_width
<= HOST_BITS_PER_WIDE_INT
10939 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10940 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10942 op0
= XEXP (op0
, 0);
10943 code
= (code
== EQ
? GE
: LT
);
10947 /* If this AND operation is really a ZERO_EXTEND from a narrower
10948 mode, the constant fits within that mode, and this is either an
10949 equality or unsigned comparison, try to do this comparison in
10950 the narrower mode. */
10951 if ((equality_comparison_p
|| unsigned_comparison_p
)
10952 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10953 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10954 & GET_MODE_MASK (mode
))
10956 && const_op
>> i
== 0
10957 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10959 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10963 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10964 fits in both M1 and M2 and the SUBREG is either paradoxical
10965 or represents the low part, permute the SUBREG and the AND
10967 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10969 unsigned HOST_WIDE_INT c1
;
10970 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10971 /* Require an integral mode, to avoid creating something like
10973 if (SCALAR_INT_MODE_P (tmode
)
10974 /* It is unsafe to commute the AND into the SUBREG if the
10975 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10976 not defined. As originally written the upper bits
10977 have a defined value due to the AND operation.
10978 However, if we commute the AND inside the SUBREG then
10979 they no longer have defined values and the meaning of
10980 the code has been changed. */
10982 #ifdef WORD_REGISTER_OPERATIONS
10983 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10984 && mode_width
<= BITS_PER_WORD
)
10986 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10987 && subreg_lowpart_p (XEXP (op0
, 0))))
10988 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10989 && mode_width
<= HOST_BITS_PER_WIDE_INT
10990 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10991 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10992 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10994 && c1
!= GET_MODE_MASK (tmode
))
10996 op0
= gen_binary (AND
, tmode
,
10997 SUBREG_REG (XEXP (op0
, 0)),
10998 gen_int_mode (c1
, tmode
));
10999 op0
= gen_lowpart_for_combine (mode
, op0
);
11004 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11005 if (const_op
== 0 && equality_comparison_p
11006 && XEXP (op0
, 1) == const1_rtx
11007 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11009 op0
= simplify_and_const_int
11010 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
11011 code
= (code
== NE
? EQ
: NE
);
11015 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11016 (eq (and (lshiftrt X) 1) 0).
11017 Also handle the case where (not X) is expressed using xor. */
11018 if (const_op
== 0 && equality_comparison_p
11019 && XEXP (op0
, 1) == const1_rtx
11020 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11022 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11023 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11025 if (GET_CODE (shift_op
) == NOT
11026 || (GET_CODE (shift_op
) == XOR
11027 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
11028 && GET_CODE (shift_count
) == CONST_INT
11029 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
11030 && (INTVAL (XEXP (shift_op
, 1))
11031 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
11033 op0
= simplify_and_const_int
11035 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
11036 (HOST_WIDE_INT
) 1);
11037 code
= (code
== NE
? EQ
: NE
);
11044 /* If we have (compare (ashift FOO N) (const_int C)) and
11045 the high order N bits of FOO (N+1 if an inequality comparison)
11046 are known to be zero, we can do this by comparing FOO with C
11047 shifted right N bits so long as the low-order N bits of C are
11049 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11050 && INTVAL (XEXP (op0
, 1)) >= 0
11051 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11052 < HOST_BITS_PER_WIDE_INT
)
11054 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
11055 && mode_width
<= HOST_BITS_PER_WIDE_INT
11056 && (nonzero_bits (XEXP (op0
, 0), mode
)
11057 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11058 + ! equality_comparison_p
))) == 0)
11060 /* We must perform a logical shift, not an arithmetic one,
11061 as we want the top N bits of C to be zero. */
11062 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11064 temp
>>= INTVAL (XEXP (op0
, 1));
11065 op1
= gen_int_mode (temp
, mode
);
11066 op0
= XEXP (op0
, 0);
11070 /* If we are doing a sign bit comparison, it means we are testing
11071 a particular bit. Convert it to the appropriate AND. */
11072 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
11073 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11075 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11078 - INTVAL (XEXP (op0
, 1)))));
11079 code
= (code
== LT
? NE
: EQ
);
11083 /* If this an equality comparison with zero and we are shifting
11084 the low bit to the sign bit, we can convert this to an AND of the
11086 if (const_op
== 0 && equality_comparison_p
11087 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11088 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11091 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11092 (HOST_WIDE_INT
) 1);
11098 /* If this is an equality comparison with zero, we can do this
11099 as a logical shift, which might be much simpler. */
11100 if (equality_comparison_p
&& const_op
== 0
11101 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
11103 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11105 INTVAL (XEXP (op0
, 1)));
11109 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11110 do the comparison in a narrower mode. */
11111 if (! unsigned_comparison_p
11112 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11113 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11114 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11115 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11116 MODE_INT
, 1)) != BLKmode
11117 && (((unsigned HOST_WIDE_INT
) const_op
11118 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11119 <= GET_MODE_MASK (tmode
)))
11121 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
11125 /* Likewise if OP0 is a PLUS of a sign extension with a
11126 constant, which is usually represented with the PLUS
11127 between the shifts. */
11128 if (! unsigned_comparison_p
11129 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11130 && GET_CODE (XEXP (op0
, 0)) == PLUS
11131 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11132 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11133 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11134 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11135 MODE_INT
, 1)) != BLKmode
11136 && (((unsigned HOST_WIDE_INT
) const_op
11137 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11138 <= GET_MODE_MASK (tmode
)))
11140 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11141 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11142 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11145 op0
= gen_binary (PLUS
, tmode
,
11146 gen_lowpart_for_combine (tmode
, inner
),
11151 /* ... fall through ... */
11153 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11154 the low order N bits of FOO are known to be zero, we can do this
11155 by comparing FOO with C shifted left N bits so long as no
11156 overflow occurs. */
11157 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11158 && INTVAL (XEXP (op0
, 1)) >= 0
11159 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11160 && mode_width
<= HOST_BITS_PER_WIDE_INT
11161 && (nonzero_bits (XEXP (op0
, 0), mode
)
11162 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11163 && (((unsigned HOST_WIDE_INT
) const_op
11164 + (GET_CODE (op0
) != LSHIFTRT
11165 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11168 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11170 /* If the shift was logical, then we must make the condition
11172 if (GET_CODE (op0
) == LSHIFTRT
)
11173 code
= unsigned_condition (code
);
11175 const_op
<<= INTVAL (XEXP (op0
, 1));
11176 op1
= GEN_INT (const_op
);
11177 op0
= XEXP (op0
, 0);
11181 /* If we are using this shift to extract just the sign bit, we
11182 can replace this with an LT or GE comparison. */
11184 && (equality_comparison_p
|| sign_bit_comparison_p
)
11185 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11186 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11189 op0
= XEXP (op0
, 0);
11190 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11202 /* Now make any compound operations involved in this comparison. Then,
11203 check for an outmost SUBREG on OP0 that is not doing anything or is
11204 paradoxical. The latter transformation must only be performed when
11205 it is known that the "extra" bits will be the same in op0 and op1 or
11206 that they don't matter. There are three cases to consider:
11208 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11209 care bits and we can assume they have any convenient value. So
11210 making the transformation is safe.
11212 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11213 In this case the upper bits of op0 are undefined. We should not make
11214 the simplification in that case as we do not know the contents of
11217 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11218 NIL. In that case we know those bits are zeros or ones. We must
11219 also be sure that they are the same as the upper bits of op1.
11221 We can never remove a SUBREG for a non-equality comparison because
11222 the sign bit is in a different place in the underlying object. */
11224 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11225 op1
= make_compound_operation (op1
, SET
);
11227 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11228 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11229 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11230 && (code
== NE
|| code
== EQ
))
11232 if (GET_MODE_SIZE (GET_MODE (op0
))
11233 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11235 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11237 if (GET_CODE (SUBREG_REG (op0
)) == REG
)
11239 op0
= SUBREG_REG (op0
);
11240 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
11243 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11244 <= HOST_BITS_PER_WIDE_INT
)
11245 && (nonzero_bits (SUBREG_REG (op0
),
11246 GET_MODE (SUBREG_REG (op0
)))
11247 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11249 tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)), op1
);
11251 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11252 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11253 op0
= SUBREG_REG (op0
), op1
= tem
;
11257 /* We now do the opposite procedure: Some machines don't have compare
11258 insns in all modes. If OP0's mode is an integer mode smaller than a
11259 word and we can't do a compare in that mode, see if there is a larger
11260 mode for which we can do the compare. There are a number of cases in
11261 which we can use the wider mode. */
11263 mode
= GET_MODE (op0
);
11264 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11265 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11266 && ! have_insn_for (COMPARE
, mode
))
11267 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11269 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11270 tmode
= GET_MODE_WIDER_MODE (tmode
))
11271 if (have_insn_for (COMPARE
, tmode
))
11275 /* If the only nonzero bits in OP0 and OP1 are those in the
11276 narrower mode and this is an equality or unsigned comparison,
11277 we can use the wider mode. Similarly for sign-extended
11278 values, in which case it is true for all comparisons. */
11279 zero_extended
= ((code
== EQ
|| code
== NE
11280 || code
== GEU
|| code
== GTU
11281 || code
== LEU
|| code
== LTU
)
11282 && (nonzero_bits (op0
, tmode
)
11283 & ~GET_MODE_MASK (mode
)) == 0
11284 && ((GET_CODE (op1
) == CONST_INT
11285 || (nonzero_bits (op1
, tmode
)
11286 & ~GET_MODE_MASK (mode
)) == 0)));
11289 || ((num_sign_bit_copies (op0
, tmode
)
11290 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11291 - GET_MODE_BITSIZE (mode
)))
11292 && (num_sign_bit_copies (op1
, tmode
)
11293 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11294 - GET_MODE_BITSIZE (mode
)))))
11296 /* If OP0 is an AND and we don't have an AND in MODE either,
11297 make a new AND in the proper mode. */
11298 if (GET_CODE (op0
) == AND
11299 && !have_insn_for (AND
, mode
))
11300 op0
= gen_binary (AND
, tmode
,
11301 gen_lowpart_for_combine (tmode
,
11303 gen_lowpart_for_combine (tmode
,
11306 op0
= gen_lowpart_for_combine (tmode
, op0
);
11307 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11308 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11309 op1
= gen_lowpart_for_combine (tmode
, op1
);
11313 /* If this is a test for negative, we can make an explicit
11314 test of the sign bit. */
11316 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11317 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11319 op0
= gen_binary (AND
, tmode
,
11320 gen_lowpart_for_combine (tmode
, op0
),
11321 GEN_INT ((HOST_WIDE_INT
) 1
11322 << (GET_MODE_BITSIZE (mode
) - 1)));
11323 code
= (code
== LT
) ? NE
: EQ
;
11328 #ifdef CANONICALIZE_COMPARISON
11329 /* If this machine only supports a subset of valid comparisons, see if we
11330 can convert an unsupported one into a supported one. */
11331 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11340 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11341 searching backward. */
11342 static enum rtx_code
11343 combine_reversed_comparison_code (rtx exp
)
11345 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11348 if (code1
!= UNKNOWN
11349 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11351 /* Otherwise try and find where the condition codes were last set and
11353 x
= get_last_value (XEXP (exp
, 0));
11354 if (!x
|| GET_CODE (x
) != COMPARE
)
11356 return reversed_comparison_code_parts (GET_CODE (exp
),
11357 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11360 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11361 Return NULL_RTX in case we fail to do the reversal. */
11363 reversed_comparison (rtx exp
, enum machine_mode mode
, rtx op0
, rtx op1
)
11365 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11366 if (reversed_code
== UNKNOWN
)
11369 return gen_binary (reversed_code
, mode
, op0
, op1
);
11372 /* Utility function for following routine. Called when X is part of a value
11373 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11374 for each register mentioned. Similar to mention_regs in cse.c */
11377 update_table_tick (rtx x
)
11379 enum rtx_code code
= GET_CODE (x
);
11380 const char *fmt
= GET_RTX_FORMAT (code
);
11385 unsigned int regno
= REGNO (x
);
11386 unsigned int endregno
11387 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11388 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11391 for (r
= regno
; r
< endregno
; r
++)
11392 reg_last_set_table_tick
[r
] = label_tick
;
11397 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11398 /* Note that we can't have an "E" in values stored; see
11399 get_last_value_validate. */
11402 /* Check for identical subexpressions. If x contains
11403 identical subexpression we only have to traverse one of
11406 && (GET_RTX_CLASS (code
) == '2'
11407 || GET_RTX_CLASS (code
) == 'c'))
11409 /* Note that at this point x1 has already been
11411 rtx x0
= XEXP (x
, 0);
11412 rtx x1
= XEXP (x
, 1);
11414 /* If x0 and x1 are identical then there is no need to
11419 /* If x0 is identical to a subexpression of x1 then while
11420 processing x1, x0 has already been processed. Thus we
11421 are done with x. */
11422 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11423 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11424 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11427 /* If x1 is identical to a subexpression of x0 then we
11428 still have to process the rest of x0. */
11429 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11430 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11431 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11433 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
11438 update_table_tick (XEXP (x
, i
));
11442 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11443 are saying that the register is clobbered and we no longer know its
11444 value. If INSN is zero, don't update reg_last_set; this is only permitted
11445 with VALUE also zero and is used to invalidate the register. */
11448 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
11450 unsigned int regno
= REGNO (reg
);
11451 unsigned int endregno
11452 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11453 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11456 /* If VALUE contains REG and we have a previous value for REG, substitute
11457 the previous value. */
11458 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11462 /* Set things up so get_last_value is allowed to see anything set up to
11464 subst_low_cuid
= INSN_CUID (insn
);
11465 tem
= get_last_value (reg
);
11467 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11468 it isn't going to be useful and will take a lot of time to process,
11469 so just use the CLOBBER. */
11473 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11474 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11475 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11476 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11477 tem
= XEXP (tem
, 0);
11479 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11483 /* For each register modified, show we don't know its value, that
11484 we don't know about its bitwise content, that its value has been
11485 updated, and that we don't know the location of the death of the
11487 for (i
= regno
; i
< endregno
; i
++)
11490 reg_last_set
[i
] = insn
;
11492 reg_last_set_value
[i
] = 0;
11493 reg_last_set_mode
[i
] = 0;
11494 reg_last_set_nonzero_bits
[i
] = 0;
11495 reg_last_set_sign_bit_copies
[i
] = 0;
11496 reg_last_death
[i
] = 0;
11499 /* Mark registers that are being referenced in this value. */
11501 update_table_tick (value
);
11503 /* Now update the status of each register being set.
11504 If someone is using this register in this block, set this register
11505 to invalid since we will get confused between the two lives in this
11506 basic block. This makes using this register always invalid. In cse, we
11507 scan the table to invalidate all entries using this register, but this
11508 is too much work for us. */
11510 for (i
= regno
; i
< endregno
; i
++)
11512 reg_last_set_label
[i
] = label_tick
;
11513 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11514 reg_last_set_invalid
[i
] = 1;
11516 reg_last_set_invalid
[i
] = 0;
11519 /* The value being assigned might refer to X (like in "x++;"). In that
11520 case, we must replace it with (clobber (const_int 0)) to prevent
11522 if (value
&& ! get_last_value_validate (&value
, insn
,
11523 reg_last_set_label
[regno
], 0))
11525 value
= copy_rtx (value
);
11526 if (! get_last_value_validate (&value
, insn
,
11527 reg_last_set_label
[regno
], 1))
11531 /* For the main register being modified, update the value, the mode, the
11532 nonzero bits, and the number of sign bit copies. */
11534 reg_last_set_value
[regno
] = value
;
11538 enum machine_mode mode
= GET_MODE (reg
);
11539 subst_low_cuid
= INSN_CUID (insn
);
11540 reg_last_set_mode
[regno
] = mode
;
11541 if (GET_MODE_CLASS (mode
) == MODE_INT
11542 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11543 mode
= nonzero_bits_mode
;
11544 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, mode
);
11545 reg_last_set_sign_bit_copies
[regno
]
11546 = num_sign_bit_copies (value
, GET_MODE (reg
));
11550 /* Called via note_stores from record_dead_and_set_regs to handle one
11551 SET or CLOBBER in an insn. DATA is the instruction in which the
11552 set is occurring. */
11555 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
11557 rtx record_dead_insn
= (rtx
) data
;
11559 if (GET_CODE (dest
) == SUBREG
)
11560 dest
= SUBREG_REG (dest
);
11562 if (GET_CODE (dest
) == REG
)
11564 /* If we are setting the whole register, we know its value. Otherwise
11565 show that we don't know the value. We can handle SUBREG in
11567 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11568 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11569 else if (GET_CODE (setter
) == SET
11570 && GET_CODE (SET_DEST (setter
)) == SUBREG
11571 && SUBREG_REG (SET_DEST (setter
)) == dest
11572 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11573 && subreg_lowpart_p (SET_DEST (setter
)))
11574 record_value_for_reg (dest
, record_dead_insn
,
11575 gen_lowpart_for_combine (GET_MODE (dest
),
11576 SET_SRC (setter
)));
11578 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11580 else if (GET_CODE (dest
) == MEM
11581 /* Ignore pushes, they clobber nothing. */
11582 && ! push_operand (dest
, GET_MODE (dest
)))
11583 mem_last_set
= INSN_CUID (record_dead_insn
);
11586 /* Update the records of when each REG was most recently set or killed
11587 for the things done by INSN. This is the last thing done in processing
11588 INSN in the combiner loop.
11590 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11591 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11592 and also the similar information mem_last_set (which insn most recently
11593 modified memory) and last_call_cuid (which insn was the most recent
11594 subroutine call). */
11597 record_dead_and_set_regs (rtx insn
)
11602 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11604 if (REG_NOTE_KIND (link
) == REG_DEAD
11605 && GET_CODE (XEXP (link
, 0)) == REG
)
11607 unsigned int regno
= REGNO (XEXP (link
, 0));
11608 unsigned int endregno
11609 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11610 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11613 for (i
= regno
; i
< endregno
; i
++)
11614 reg_last_death
[i
] = insn
;
11616 else if (REG_NOTE_KIND (link
) == REG_INC
)
11617 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11620 if (GET_CODE (insn
) == CALL_INSN
)
11622 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11623 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11625 reg_last_set_value
[i
] = 0;
11626 reg_last_set_mode
[i
] = 0;
11627 reg_last_set_nonzero_bits
[i
] = 0;
11628 reg_last_set_sign_bit_copies
[i
] = 0;
11629 reg_last_death
[i
] = 0;
11632 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11634 /* Don't bother recording what this insn does. It might set the
11635 return value register, but we can't combine into a call
11636 pattern anyway, so there's no point trying (and it may cause
11637 a crash, if e.g. we wind up asking for last_set_value of a
11638 SUBREG of the return value register). */
11642 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11645 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11646 register present in the SUBREG, so for each such SUBREG go back and
11647 adjust nonzero and sign bit information of the registers that are
11648 known to have some zero/sign bits set.
11650 This is needed because when combine blows the SUBREGs away, the
11651 information on zero/sign bits is lost and further combines can be
11652 missed because of that. */
11655 record_promoted_value (rtx insn
, rtx subreg
)
11658 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11659 enum machine_mode mode
= GET_MODE (subreg
);
11661 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11664 for (links
= LOG_LINKS (insn
); links
;)
11666 insn
= XEXP (links
, 0);
11667 set
= single_set (insn
);
11669 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11670 || REGNO (SET_DEST (set
)) != regno
11671 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11673 links
= XEXP (links
, 1);
11677 if (reg_last_set
[regno
] == insn
)
11679 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11680 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11683 if (GET_CODE (SET_SRC (set
)) == REG
)
11685 regno
= REGNO (SET_SRC (set
));
11686 links
= LOG_LINKS (insn
);
11693 /* Scan X for promoted SUBREGs. For each one found,
11694 note what it implies to the registers used in it. */
11697 check_promoted_subreg (rtx insn
, rtx x
)
11699 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11700 && GET_CODE (SUBREG_REG (x
)) == REG
)
11701 record_promoted_value (insn
, x
);
11704 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11707 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11711 check_promoted_subreg (insn
, XEXP (x
, i
));
11715 if (XVEC (x
, i
) != 0)
11716 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11717 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11723 /* Utility routine for the following function. Verify that all the registers
11724 mentioned in *LOC are valid when *LOC was part of a value set when
11725 label_tick == TICK. Return 0 if some are not.
11727 If REPLACE is nonzero, replace the invalid reference with
11728 (clobber (const_int 0)) and return 1. This replacement is useful because
11729 we often can get useful information about the form of a value (e.g., if
11730 it was produced by a shift that always produces -1 or 0) even though
11731 we don't know exactly what registers it was produced from. */
11734 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11737 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11738 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11741 if (GET_CODE (x
) == REG
)
11743 unsigned int regno
= REGNO (x
);
11744 unsigned int endregno
11745 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11746 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11749 for (j
= regno
; j
< endregno
; j
++)
11750 if (reg_last_set_invalid
[j
]
11751 /* If this is a pseudo-register that was only set once and not
11752 live at the beginning of the function, it is always valid. */
11753 || (! (regno
>= FIRST_PSEUDO_REGISTER
11754 && REG_N_SETS (regno
) == 1
11755 && (! REGNO_REG_SET_P
11756 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11757 && reg_last_set_label
[j
] > tick
))
11760 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11766 /* If this is a memory reference, make sure that there were
11767 no stores after it that might have clobbered the value. We don't
11768 have alias info, so we assume any store invalidates it. */
11769 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11770 && INSN_CUID (insn
) <= mem_last_set
)
11773 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11777 for (i
= 0; i
< len
; i
++)
11781 /* Check for identical subexpressions. If x contains
11782 identical subexpression we only have to traverse one of
11785 && (GET_RTX_CLASS (GET_CODE (x
)) == '2'
11786 || GET_RTX_CLASS (GET_CODE (x
)) == 'c'))
11788 /* Note that at this point x0 has already been checked
11789 and found valid. */
11790 rtx x0
= XEXP (x
, 0);
11791 rtx x1
= XEXP (x
, 1);
11793 /* If x0 and x1 are identical then x is also valid. */
11797 /* If x1 is identical to a subexpression of x0 then
11798 while checking x0, x1 has already been checked. Thus
11799 it is valid and so as x. */
11800 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11801 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11802 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11805 /* If x0 is identical to a subexpression of x1 then x is
11806 valid iff the rest of x1 is valid. */
11807 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11808 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11809 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11811 get_last_value_validate (&XEXP (x1
,
11812 x0
== XEXP (x1
, 0) ? 1 : 0),
11813 insn
, tick
, replace
);
11816 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11820 /* Don't bother with these. They shouldn't occur anyway. */
11821 else if (fmt
[i
] == 'E')
11825 /* If we haven't found a reason for it to be invalid, it is valid. */
11829 /* Get the last value assigned to X, if known. Some registers
11830 in the value may be replaced with (clobber (const_int 0)) if their value
11831 is known longer known reliably. */
11834 get_last_value (rtx x
)
11836 unsigned int regno
;
11839 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11840 then convert it to the desired mode. If this is a paradoxical SUBREG,
11841 we cannot predict what values the "extra" bits might have. */
11842 if (GET_CODE (x
) == SUBREG
11843 && subreg_lowpart_p (x
)
11844 && (GET_MODE_SIZE (GET_MODE (x
))
11845 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11846 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11847 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11849 if (GET_CODE (x
) != REG
)
11853 value
= reg_last_set_value
[regno
];
11855 /* If we don't have a value, or if it isn't for this basic block and
11856 it's either a hard register, set more than once, or it's a live
11857 at the beginning of the function, return 0.
11859 Because if it's not live at the beginning of the function then the reg
11860 is always set before being used (is never used without being set).
11861 And, if it's set only once, and it's always set before use, then all
11862 uses must have the same last value, even if it's not from this basic
11866 || (reg_last_set_label
[regno
] != label_tick
11867 && (regno
< FIRST_PSEUDO_REGISTER
11868 || REG_N_SETS (regno
) != 1
11869 || (REGNO_REG_SET_P
11870 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11873 /* If the value was set in a later insn than the ones we are processing,
11874 we can't use it even if the register was only set once. */
11875 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11878 /* If the value has all its registers valid, return it. */
11879 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11880 reg_last_set_label
[regno
], 0))
11883 /* Otherwise, make a copy and replace any invalid register with
11884 (clobber (const_int 0)). If that fails for some reason, return 0. */
11886 value
= copy_rtx (value
);
11887 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11888 reg_last_set_label
[regno
], 1))
11894 /* Return nonzero if expression X refers to a REG or to memory
11895 that is set in an instruction more recent than FROM_CUID. */
11898 use_crosses_set_p (rtx x
, int from_cuid
)
11902 enum rtx_code code
= GET_CODE (x
);
11906 unsigned int regno
= REGNO (x
);
11907 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11908 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11910 #ifdef PUSH_ROUNDING
11911 /* Don't allow uses of the stack pointer to be moved,
11912 because we don't know whether the move crosses a push insn. */
11913 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11916 for (; regno
< endreg
; regno
++)
11917 if (reg_last_set
[regno
]
11918 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11923 if (code
== MEM
&& mem_last_set
> from_cuid
)
11926 fmt
= GET_RTX_FORMAT (code
);
11928 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11933 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11934 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11937 else if (fmt
[i
] == 'e'
11938 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11944 /* Define three variables used for communication between the following
11947 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11948 static int reg_dead_flag
;
11950 /* Function called via note_stores from reg_dead_at_p.
11952 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11953 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11956 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11958 unsigned int regno
, endregno
;
11960 if (GET_CODE (dest
) != REG
)
11963 regno
= REGNO (dest
);
11964 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11965 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11967 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11968 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11971 /* Return nonzero if REG is known to be dead at INSN.
11973 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11974 referencing REG, it is dead. If we hit a SET referencing REG, it is
11975 live. Otherwise, see if it is live or dead at the start of the basic
11976 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11977 must be assumed to be always live. */
11980 reg_dead_at_p (rtx reg
, rtx insn
)
11985 /* Set variables for reg_dead_at_p_1. */
11986 reg_dead_regno
= REGNO (reg
);
11987 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11988 ? HARD_REGNO_NREGS (reg_dead_regno
,
11994 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11995 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11997 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11998 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12002 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
12003 beginning of function. */
12004 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
12005 insn
= prev_nonnote_insn (insn
))
12007 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12009 return reg_dead_flag
== 1 ? 1 : 0;
12011 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12015 /* Get the basic block that we were in. */
12017 block
= ENTRY_BLOCK_PTR
->next_bb
;
12020 FOR_EACH_BB (block
)
12021 if (insn
== block
->head
)
12024 if (block
== EXIT_BLOCK_PTR
)
12028 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12029 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
12035 /* Note hard registers in X that are used. This code is similar to
12036 that in flow.c, but much simpler since we don't care about pseudos. */
12039 mark_used_regs_combine (rtx x
)
12041 RTX_CODE code
= GET_CODE (x
);
12042 unsigned int regno
;
12055 case ADDR_DIFF_VEC
:
12058 /* CC0 must die in the insn after it is set, so we don't need to take
12059 special note of it here. */
12065 /* If we are clobbering a MEM, mark any hard registers inside the
12066 address as used. */
12067 if (GET_CODE (XEXP (x
, 0)) == MEM
)
12068 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12073 /* A hard reg in a wide mode may really be multiple registers.
12074 If so, mark all of them just like the first. */
12075 if (regno
< FIRST_PSEUDO_REGISTER
)
12077 unsigned int endregno
, r
;
12079 /* None of this applies to the stack, frame or arg pointers. */
12080 if (regno
== STACK_POINTER_REGNUM
12081 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12082 || regno
== HARD_FRAME_POINTER_REGNUM
12084 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12085 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12087 || regno
== FRAME_POINTER_REGNUM
)
12090 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12091 for (r
= regno
; r
< endregno
; r
++)
12092 SET_HARD_REG_BIT (newpat_used_regs
, r
);
12098 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12100 rtx testreg
= SET_DEST (x
);
12102 while (GET_CODE (testreg
) == SUBREG
12103 || GET_CODE (testreg
) == ZERO_EXTRACT
12104 || GET_CODE (testreg
) == SIGN_EXTRACT
12105 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12106 testreg
= XEXP (testreg
, 0);
12108 if (GET_CODE (testreg
) == MEM
)
12109 mark_used_regs_combine (XEXP (testreg
, 0));
12111 mark_used_regs_combine (SET_SRC (x
));
12119 /* Recursively scan the operands of this expression. */
12122 const char *fmt
= GET_RTX_FORMAT (code
);
12124 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12127 mark_used_regs_combine (XEXP (x
, i
));
12128 else if (fmt
[i
] == 'E')
12132 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12133 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12139 /* Remove register number REGNO from the dead registers list of INSN.
12141 Return the note used to record the death, if there was one. */
12144 remove_death (unsigned int regno
, rtx insn
)
12146 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12150 REG_N_DEATHS (regno
)--;
12151 remove_note (insn
, note
);
12157 /* For each register (hardware or pseudo) used within expression X, if its
12158 death is in an instruction with cuid between FROM_CUID (inclusive) and
12159 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12160 list headed by PNOTES.
12162 That said, don't move registers killed by maybe_kill_insn.
12164 This is done when X is being merged by combination into TO_INSN. These
12165 notes will then be distributed as needed. */
12168 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
12173 enum rtx_code code
= GET_CODE (x
);
12177 unsigned int regno
= REGNO (x
);
12178 rtx where_dead
= reg_last_death
[regno
];
12179 rtx before_dead
, after_dead
;
12181 /* Don't move the register if it gets killed in between from and to. */
12182 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12183 && ! reg_referenced_p (x
, maybe_kill_insn
))
12186 /* WHERE_DEAD could be a USE insn made by combine, so first we
12187 make sure that we have insns with valid INSN_CUID values. */
12188 before_dead
= where_dead
;
12189 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
12190 before_dead
= PREV_INSN (before_dead
);
12192 after_dead
= where_dead
;
12193 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
12194 after_dead
= NEXT_INSN (after_dead
);
12196 if (before_dead
&& after_dead
12197 && INSN_CUID (before_dead
) >= from_cuid
12198 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
12199 || (where_dead
!= after_dead
12200 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
12202 rtx note
= remove_death (regno
, where_dead
);
12204 /* It is possible for the call above to return 0. This can occur
12205 when reg_last_death points to I2 or I1 that we combined with.
12206 In that case make a new note.
12208 We must also check for the case where X is a hard register
12209 and NOTE is a death note for a range of hard registers
12210 including X. In that case, we must put REG_DEAD notes for
12211 the remaining registers in place of NOTE. */
12213 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12214 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12215 > GET_MODE_SIZE (GET_MODE (x
))))
12217 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12218 unsigned int deadend
12219 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
12220 GET_MODE (XEXP (note
, 0))));
12221 unsigned int ourend
12222 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12225 for (i
= deadregno
; i
< deadend
; i
++)
12226 if (i
< regno
|| i
>= ourend
)
12227 REG_NOTES (where_dead
)
12228 = gen_rtx_EXPR_LIST (REG_DEAD
,
12230 REG_NOTES (where_dead
));
12233 /* If we didn't find any note, or if we found a REG_DEAD note that
12234 covers only part of the given reg, and we have a multi-reg hard
12235 register, then to be safe we must check for REG_DEAD notes
12236 for each register other than the first. They could have
12237 their own REG_DEAD notes lying around. */
12238 else if ((note
== 0
12240 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12241 < GET_MODE_SIZE (GET_MODE (x
)))))
12242 && regno
< FIRST_PSEUDO_REGISTER
12243 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
12245 unsigned int ourend
12246 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12247 unsigned int i
, offset
;
12251 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
12255 for (i
= regno
+ offset
; i
< ourend
; i
++)
12256 move_deaths (regno_reg_rtx
[i
],
12257 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12260 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12262 XEXP (note
, 1) = *pnotes
;
12266 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12268 REG_N_DEATHS (regno
)++;
12274 else if (GET_CODE (x
) == SET
)
12276 rtx dest
= SET_DEST (x
);
12278 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12280 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12281 that accesses one word of a multi-word item, some
12282 piece of everything register in the expression is used by
12283 this insn, so remove any old death. */
12284 /* ??? So why do we test for equality of the sizes? */
12286 if (GET_CODE (dest
) == ZERO_EXTRACT
12287 || GET_CODE (dest
) == STRICT_LOW_PART
12288 || (GET_CODE (dest
) == SUBREG
12289 && (((GET_MODE_SIZE (GET_MODE (dest
))
12290 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12291 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12292 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12294 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12298 /* If this is some other SUBREG, we know it replaces the entire
12299 value, so use that as the destination. */
12300 if (GET_CODE (dest
) == SUBREG
)
12301 dest
= SUBREG_REG (dest
);
12303 /* If this is a MEM, adjust deaths of anything used in the address.
12304 For a REG (the only other possibility), the entire value is
12305 being replaced so the old value is not used in this insn. */
12307 if (GET_CODE (dest
) == MEM
)
12308 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12313 else if (GET_CODE (x
) == CLOBBER
)
12316 len
= GET_RTX_LENGTH (code
);
12317 fmt
= GET_RTX_FORMAT (code
);
12319 for (i
= 0; i
< len
; i
++)
12324 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12325 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12328 else if (fmt
[i
] == 'e')
12329 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12333 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12334 pattern of an insn. X must be a REG. */
12337 reg_bitfield_target_p (rtx x
, rtx body
)
12341 if (GET_CODE (body
) == SET
)
12343 rtx dest
= SET_DEST (body
);
12345 unsigned int regno
, tregno
, endregno
, endtregno
;
12347 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12348 target
= XEXP (dest
, 0);
12349 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12350 target
= SUBREG_REG (XEXP (dest
, 0));
12354 if (GET_CODE (target
) == SUBREG
)
12355 target
= SUBREG_REG (target
);
12357 if (GET_CODE (target
) != REG
)
12360 tregno
= REGNO (target
), regno
= REGNO (x
);
12361 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12362 return target
== x
;
12364 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
12365 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12367 return endregno
> tregno
&& regno
< endtregno
;
12370 else if (GET_CODE (body
) == PARALLEL
)
12371 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12372 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12378 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12379 as appropriate. I3 and I2 are the insns resulting from the combination
12380 insns including FROM (I2 may be zero).
12382 Each note in the list is either ignored or placed on some insns, depending
12383 on the type of note. */
12386 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
12388 rtx note
, next_note
;
12391 for (note
= notes
; note
; note
= next_note
)
12393 rtx place
= 0, place2
= 0;
12395 /* If this NOTE references a pseudo register, ensure it references
12396 the latest copy of that register. */
12397 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12398 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12399 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12401 next_note
= XEXP (note
, 1);
12402 switch (REG_NOTE_KIND (note
))
12406 /* Doesn't matter much where we put this, as long as it's somewhere.
12407 It is preferable to keep these notes on branches, which is most
12408 likely to be i3. */
12412 case REG_VALUE_PROFILE
:
12413 /* Just get rid of this note, as it is unused later anyway. */
12416 case REG_VTABLE_REF
:
12417 /* ??? Should remain with *a particular* memory load. Given the
12418 nature of vtable data, the last insn seems relatively safe. */
12422 case REG_NON_LOCAL_GOTO
:
12423 if (GET_CODE (i3
) == JUMP_INSN
)
12425 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12431 case REG_EH_REGION
:
12432 /* These notes must remain with the call or trapping instruction. */
12433 if (GET_CODE (i3
) == CALL_INSN
)
12435 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12437 else if (flag_non_call_exceptions
)
12439 if (may_trap_p (i3
))
12441 else if (i2
&& may_trap_p (i2
))
12443 /* ??? Otherwise assume we've combined things such that we
12444 can now prove that the instructions can't trap. Drop the
12445 note in this case. */
12451 case REG_ALWAYS_RETURN
:
12454 /* These notes must remain with the call. It should not be
12455 possible for both I2 and I3 to be a call. */
12456 if (GET_CODE (i3
) == CALL_INSN
)
12458 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12465 /* Any clobbers for i3 may still exist, and so we must process
12466 REG_UNUSED notes from that insn.
12468 Any clobbers from i2 or i1 can only exist if they were added by
12469 recog_for_combine. In that case, recog_for_combine created the
12470 necessary REG_UNUSED notes. Trying to keep any original
12471 REG_UNUSED notes from these insns can cause incorrect output
12472 if it is for the same register as the original i3 dest.
12473 In that case, we will notice that the register is set in i3,
12474 and then add a REG_UNUSED note for the destination of i3, which
12475 is wrong. However, it is possible to have REG_UNUSED notes from
12476 i2 or i1 for register which were both used and clobbered, so
12477 we keep notes from i2 or i1 if they will turn into REG_DEAD
12480 /* If this register is set or clobbered in I3, put the note there
12481 unless there is one already. */
12482 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12484 if (from_insn
!= i3
)
12487 if (! (GET_CODE (XEXP (note
, 0)) == REG
12488 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12489 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12492 /* Otherwise, if this register is used by I3, then this register
12493 now dies here, so we must put a REG_DEAD note here unless there
12495 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12496 && ! (GET_CODE (XEXP (note
, 0)) == REG
12497 ? find_regno_note (i3
, REG_DEAD
,
12498 REGNO (XEXP (note
, 0)))
12499 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12501 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12509 /* These notes say something about results of an insn. We can
12510 only support them if they used to be on I3 in which case they
12511 remain on I3. Otherwise they are ignored.
12513 If the note refers to an expression that is not a constant, we
12514 must also ignore the note since we cannot tell whether the
12515 equivalence is still true. It might be possible to do
12516 slightly better than this (we only have a problem if I2DEST
12517 or I1DEST is present in the expression), but it doesn't
12518 seem worth the trouble. */
12520 if (from_insn
== i3
12521 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12526 case REG_NO_CONFLICT
:
12527 /* These notes say something about how a register is used. They must
12528 be present on any use of the register in I2 or I3. */
12529 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12532 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12542 /* This can show up in several ways -- either directly in the
12543 pattern, or hidden off in the constant pool with (or without?)
12544 a REG_EQUAL note. */
12545 /* ??? Ignore the without-reg_equal-note problem for now. */
12546 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12547 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12548 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12549 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12553 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12554 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12555 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12556 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12564 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12565 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12566 if (place
&& GET_CODE (place
) == JUMP_INSN
&& JUMP_LABEL (place
))
12568 if (JUMP_LABEL (place
) != XEXP (note
, 0))
12570 if (GET_CODE (JUMP_LABEL (place
)) == CODE_LABEL
)
12571 LABEL_NUSES (JUMP_LABEL (place
))--;
12574 if (place2
&& GET_CODE (place2
) == JUMP_INSN
&& JUMP_LABEL (place2
))
12576 if (JUMP_LABEL (place2
) != XEXP (note
, 0))
12578 if (GET_CODE (JUMP_LABEL (place2
)) == CODE_LABEL
)
12579 LABEL_NUSES (JUMP_LABEL (place2
))--;
12585 /* This note says something about the value of a register prior
12586 to the execution of an insn. It is too much trouble to see
12587 if the note is still correct in all situations. It is better
12588 to simply delete it. */
12592 /* If the insn previously containing this note still exists,
12593 put it back where it was. Otherwise move it to the previous
12594 insn. Adjust the corresponding REG_LIBCALL note. */
12595 if (GET_CODE (from_insn
) != NOTE
)
12599 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12600 place
= prev_real_insn (from_insn
);
12602 XEXP (tem
, 0) = place
;
12603 /* If we're deleting the last remaining instruction of a
12604 libcall sequence, don't add the notes. */
12605 else if (XEXP (note
, 0) == from_insn
)
12611 /* This is handled similarly to REG_RETVAL. */
12612 if (GET_CODE (from_insn
) != NOTE
)
12616 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12617 place
= next_real_insn (from_insn
);
12619 XEXP (tem
, 0) = place
;
12620 /* If we're deleting the last remaining instruction of a
12621 libcall sequence, don't add the notes. */
12622 else if (XEXP (note
, 0) == from_insn
)
12628 /* If the register is used as an input in I3, it dies there.
12629 Similarly for I2, if it is nonzero and adjacent to I3.
12631 If the register is not used as an input in either I3 or I2
12632 and it is not one of the registers we were supposed to eliminate,
12633 there are two possibilities. We might have a non-adjacent I2
12634 or we might have somehow eliminated an additional register
12635 from a computation. For example, we might have had A & B where
12636 we discover that B will always be zero. In this case we will
12637 eliminate the reference to A.
12639 In both cases, we must search to see if we can find a previous
12640 use of A and put the death note there. */
12643 && GET_CODE (from_insn
) == CALL_INSN
12644 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12646 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12648 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12649 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12654 basic_block bb
= this_basic_block
;
12656 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12658 if (! INSN_P (tem
))
12660 if (tem
== bb
->head
)
12665 /* If the register is being set at TEM, see if that is all
12666 TEM is doing. If so, delete TEM. Otherwise, make this
12667 into a REG_UNUSED note instead. */
12668 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12670 rtx set
= single_set (tem
);
12671 rtx inner_dest
= 0;
12673 rtx cc0_setter
= NULL_RTX
;
12677 for (inner_dest
= SET_DEST (set
);
12678 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12679 || GET_CODE (inner_dest
) == SUBREG
12680 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12681 inner_dest
= XEXP (inner_dest
, 0))
12684 /* Verify that it was the set, and not a clobber that
12685 modified the register.
12687 CC0 targets must be careful to maintain setter/user
12688 pairs. If we cannot delete the setter due to side
12689 effects, mark the user with an UNUSED note instead
12692 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12693 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12695 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12696 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12697 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12701 /* Move the notes and links of TEM elsewhere.
12702 This might delete other dead insns recursively.
12703 First set the pattern to something that won't use
12706 PATTERN (tem
) = pc_rtx
;
12708 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12710 distribute_links (LOG_LINKS (tem
));
12712 PUT_CODE (tem
, NOTE
);
12713 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12714 NOTE_SOURCE_FILE (tem
) = 0;
12717 /* Delete the setter too. */
12720 PATTERN (cc0_setter
) = pc_rtx
;
12722 distribute_notes (REG_NOTES (cc0_setter
),
12723 cc0_setter
, cc0_setter
,
12725 distribute_links (LOG_LINKS (cc0_setter
));
12727 PUT_CODE (cc0_setter
, NOTE
);
12728 NOTE_LINE_NUMBER (cc0_setter
)
12729 = NOTE_INSN_DELETED
;
12730 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12734 /* If the register is both set and used here, put the
12735 REG_DEAD note here, but place a REG_UNUSED note
12736 here too unless there already is one. */
12737 else if (reg_referenced_p (XEXP (note
, 0),
12742 if (! find_regno_note (tem
, REG_UNUSED
,
12743 REGNO (XEXP (note
, 0))))
12745 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12750 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12752 /* If there isn't already a REG_UNUSED note, put one
12754 if (! find_regno_note (tem
, REG_UNUSED
,
12755 REGNO (XEXP (note
, 0))))
12760 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12761 || (GET_CODE (tem
) == CALL_INSN
12762 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12766 /* If we are doing a 3->2 combination, and we have a
12767 register which formerly died in i3 and was not used
12768 by i2, which now no longer dies in i3 and is used in
12769 i2 but does not die in i2, and place is between i2
12770 and i3, then we may need to move a link from place to
12772 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12773 && INSN_CUID (place
) > INSN_CUID (i2
)
12775 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12776 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12778 rtx links
= LOG_LINKS (place
);
12779 LOG_LINKS (place
) = 0;
12780 distribute_links (links
);
12785 if (tem
== bb
->head
)
12789 /* We haven't found an insn for the death note and it
12790 is still a REG_DEAD note, but we have hit the beginning
12791 of the block. If the existing life info says the reg
12792 was dead, there's nothing left to do. Otherwise, we'll
12793 need to do a global life update after combine. */
12794 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12795 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12796 REGNO (XEXP (note
, 0))))
12797 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12800 /* If the register is set or already dead at PLACE, we needn't do
12801 anything with this note if it is still a REG_DEAD note.
12802 We can here if it is set at all, not if is it totally replace,
12803 which is what `dead_or_set_p' checks, so also check for it being
12806 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12808 unsigned int regno
= REGNO (XEXP (note
, 0));
12810 /* Similarly, if the instruction on which we want to place
12811 the note is a noop, we'll need do a global live update
12812 after we remove them in delete_noop_moves. */
12813 if (noop_move_p (place
))
12814 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12816 if (dead_or_set_p (place
, XEXP (note
, 0))
12817 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12819 /* Unless the register previously died in PLACE, clear
12820 reg_last_death. [I no longer understand why this is
12822 if (reg_last_death
[regno
] != place
)
12823 reg_last_death
[regno
] = 0;
12827 reg_last_death
[regno
] = place
;
12829 /* If this is a death note for a hard reg that is occupying
12830 multiple registers, ensure that we are still using all
12831 parts of the object. If we find a piece of the object
12832 that is unused, we must arrange for an appropriate REG_DEAD
12833 note to be added for it. However, we can't just emit a USE
12834 and tag the note to it, since the register might actually
12835 be dead; so we recourse, and the recursive call then finds
12836 the previous insn that used this register. */
12838 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12839 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12841 unsigned int endregno
12842 = regno
+ HARD_REGNO_NREGS (regno
,
12843 GET_MODE (XEXP (note
, 0)));
12847 for (i
= regno
; i
< endregno
; i
++)
12848 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12849 && ! find_regno_fusage (place
, USE
, i
))
12850 || dead_or_set_regno_p (place
, i
))
12855 /* Put only REG_DEAD notes for pieces that are
12856 not already dead or set. */
12858 for (i
= regno
; i
< endregno
;
12859 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12861 rtx piece
= regno_reg_rtx
[i
];
12862 basic_block bb
= this_basic_block
;
12864 if (! dead_or_set_p (place
, piece
)
12865 && ! reg_bitfield_target_p (piece
,
12869 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12871 distribute_notes (new_note
, place
, place
,
12874 else if (! refers_to_regno_p (i
, i
+ 1,
12875 PATTERN (place
), 0)
12876 && ! find_regno_fusage (place
, USE
, i
))
12877 for (tem
= PREV_INSN (place
); ;
12878 tem
= PREV_INSN (tem
))
12880 if (! INSN_P (tem
))
12882 if (tem
== bb
->head
)
12884 SET_BIT (refresh_blocks
,
12885 this_basic_block
->index
);
12890 if (dead_or_set_p (tem
, piece
)
12891 || reg_bitfield_target_p (piece
,
12895 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12910 /* Any other notes should not be present at this point in the
12917 XEXP (note
, 1) = REG_NOTES (place
);
12918 REG_NOTES (place
) = note
;
12920 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12921 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12922 && GET_CODE (XEXP (note
, 0)) == REG
)
12923 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12927 if ((REG_NOTE_KIND (note
) == REG_DEAD
12928 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12929 && GET_CODE (XEXP (note
, 0)) == REG
)
12930 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12932 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12933 REG_NOTE_KIND (note
),
12935 REG_NOTES (place2
));
12940 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12941 I3, I2, and I1 to new locations. This is also called to add a link
12942 pointing at I3 when I3's destination is changed. */
12945 distribute_links (rtx links
)
12947 rtx link
, next_link
;
12949 for (link
= links
; link
; link
= next_link
)
12955 next_link
= XEXP (link
, 1);
12957 /* If the insn that this link points to is a NOTE or isn't a single
12958 set, ignore it. In the latter case, it isn't clear what we
12959 can do other than ignore the link, since we can't tell which
12960 register it was for. Such links wouldn't be used by combine
12963 It is not possible for the destination of the target of the link to
12964 have been changed by combine. The only potential of this is if we
12965 replace I3, I2, and I1 by I3 and I2. But in that case the
12966 destination of I2 also remains unchanged. */
12968 if (GET_CODE (XEXP (link
, 0)) == NOTE
12969 || (set
= single_set (XEXP (link
, 0))) == 0)
12972 reg
= SET_DEST (set
);
12973 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12974 || GET_CODE (reg
) == SIGN_EXTRACT
12975 || GET_CODE (reg
) == STRICT_LOW_PART
)
12976 reg
= XEXP (reg
, 0);
12978 /* A LOG_LINK is defined as being placed on the first insn that uses
12979 a register and points to the insn that sets the register. Start
12980 searching at the next insn after the target of the link and stop
12981 when we reach a set of the register or the end of the basic block.
12983 Note that this correctly handles the link that used to point from
12984 I3 to I2. Also note that not much searching is typically done here
12985 since most links don't point very far away. */
12987 for (insn
= NEXT_INSN (XEXP (link
, 0));
12988 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12989 || this_basic_block
->next_bb
->head
!= insn
));
12990 insn
= NEXT_INSN (insn
))
12991 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12993 if (reg_referenced_p (reg
, PATTERN (insn
)))
12997 else if (GET_CODE (insn
) == CALL_INSN
12998 && find_reg_fusage (insn
, USE
, reg
))
13003 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13006 /* If we found a place to put the link, place it there unless there
13007 is already a link to the same insn as LINK at that point. */
13013 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
13014 if (XEXP (link2
, 0) == XEXP (link
, 0))
13019 XEXP (link
, 1) = LOG_LINKS (place
);
13020 LOG_LINKS (place
) = link
;
13022 /* Set added_links_insn to the earliest insn we added a
13024 if (added_links_insn
== 0
13025 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
13026 added_links_insn
= place
;
13032 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13035 insn_cuid (rtx insn
)
13037 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
13038 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
13039 insn
= NEXT_INSN (insn
);
13041 if (INSN_UID (insn
) > max_uid_cuid
)
13044 return INSN_CUID (insn
);
13048 dump_combine_stats (FILE *file
)
13052 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13053 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13057 dump_combine_total_stats (FILE *file
)
13061 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13062 total_attempts
, total_merges
, total_extras
, total_successes
);