1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-flags.h"
90 #include "insn-codes.h"
91 #include "insn-attr.h"
96 #ifndef ACCUMULATE_OUTGOING_ARGS
97 #define ACCUMULATE_OUTGOING_ARGS 0
100 /* Supply a default definition for PUSH_ARGS. */
103 #define PUSH_ARGS !ACCUMULATE_OUTGOING_ARGS
109 /* It is not safe to use ordinary gen_lowpart in combine.
110 Use gen_lowpart_for_combine instead. See comments there. */
111 #define gen_lowpart dont_use_gen_lowpart_you_dummy
113 /* Number of attempts to combine instructions in this function. */
115 static int combine_attempts
;
117 /* Number of attempts that got as far as substitution in this function. */
119 static int combine_merges
;
121 /* Number of instructions combined with added SETs in this function. */
123 static int combine_extras
;
125 /* Number of instructions combined in this function. */
127 static int combine_successes
;
129 /* Totals over entire compilation. */
131 static int total_attempts
, total_merges
, total_extras
, total_successes
;
134 /* Vector mapping INSN_UIDs to cuids.
135 The cuids are like uids but increase monotonically always.
136 Combine always uses cuids so that it can compare them.
137 But actually renumbering the uids, which we used to do,
138 proves to be a bad idea because it makes it hard to compare
139 the dumps produced by earlier passes with those from later passes. */
141 static int *uid_cuid
;
142 static int max_uid_cuid
;
144 /* Get the cuid of an insn. */
146 #define INSN_CUID(INSN) \
147 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
149 /* Maximum register number, which is the size of the tables below. */
151 static unsigned int combine_max_regno
;
153 /* Record last point of death of (hard or pseudo) register n. */
155 static rtx
*reg_last_death
;
157 /* Record last point of modification of (hard or pseudo) register n. */
159 static rtx
*reg_last_set
;
161 /* Record the cuid of the last insn that invalidated memory
162 (anything that writes memory, and subroutine calls, but not pushes). */
164 static int mem_last_set
;
166 /* Record the cuid of the last CALL_INSN
167 so we can tell whether a potential combination crosses any calls. */
169 static int last_call_cuid
;
171 /* When `subst' is called, this is the insn that is being modified
172 (by combining in a previous insn). The PATTERN of this insn
173 is still the old pattern partially modified and it should not be
174 looked at, but this may be used to examine the successors of the insn
175 to judge whether a simplification is valid. */
177 static rtx subst_insn
;
179 /* This is an insn that belongs before subst_insn, but is not currently
180 on the insn chain. */
182 static rtx subst_prev_insn
;
184 /* This is the lowest CUID that `subst' is currently dealing with.
185 get_last_value will not return a value if the register was set at or
186 after this CUID. If not for this mechanism, we could get confused if
187 I2 or I1 in try_combine were an insn that used the old value of a register
188 to obtain a new value. In that case, we might erroneously get the
189 new value of the register when we wanted the old one. */
191 static int subst_low_cuid
;
193 /* This contains any hard registers that are used in newpat; reg_dead_at_p
194 must consider all these registers to be always live. */
196 static HARD_REG_SET newpat_used_regs
;
198 /* This is an insn to which a LOG_LINKS entry has been added. If this
199 insn is the earlier than I2 or I3, combine should rescan starting at
202 static rtx added_links_insn
;
204 /* Basic block number of the block in which we are performing combines. */
205 static int this_basic_block
;
207 /* A bitmap indicating which blocks had registers go dead at entry.
208 After combine, we'll need to re-do global life analysis with
209 those blocks as starting points. */
210 static sbitmap refresh_blocks
;
211 static int need_refresh
;
213 /* The next group of arrays allows the recording of the last value assigned
214 to (hard or pseudo) register n. We use this information to see if a
215 operation being processed is redundant given a prior operation performed
216 on the register. For example, an `and' with a constant is redundant if
217 all the zero bits are already known to be turned off.
219 We use an approach similar to that used by cse, but change it in the
222 (1) We do not want to reinitialize at each label.
223 (2) It is useful, but not critical, to know the actual value assigned
224 to a register. Often just its form is helpful.
226 Therefore, we maintain the following arrays:
228 reg_last_set_value the last value assigned
229 reg_last_set_label records the value of label_tick when the
230 register was assigned
231 reg_last_set_table_tick records the value of label_tick when a
232 value using the register is assigned
233 reg_last_set_invalid set to non-zero when it is not valid
234 to use the value of this register in some
237 To understand the usage of these tables, it is important to understand
238 the distinction between the value in reg_last_set_value being valid
239 and the register being validly contained in some other expression in the
242 Entry I in reg_last_set_value is valid if it is non-zero, and either
243 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
245 Register I may validly appear in any expression returned for the value
246 of another register if reg_n_sets[i] is 1. It may also appear in the
247 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
248 reg_last_set_invalid[j] is zero.
250 If an expression is found in the table containing a register which may
251 not validly appear in an expression, the register is replaced by
252 something that won't match, (clobber (const_int 0)).
254 reg_last_set_invalid[i] is set non-zero when register I is being assigned
255 to and reg_last_set_table_tick[i] == label_tick. */
257 /* Record last value assigned to (hard or pseudo) register n. */
259 static rtx
*reg_last_set_value
;
261 /* Record the value of label_tick when the value for register n is placed in
262 reg_last_set_value[n]. */
264 static int *reg_last_set_label
;
266 /* Record the value of label_tick when an expression involving register n
267 is placed in reg_last_set_value. */
269 static int *reg_last_set_table_tick
;
271 /* Set non-zero if references to register n in expressions should not be
274 static char *reg_last_set_invalid
;
276 /* Incremented for each label. */
278 static int label_tick
;
280 /* Some registers that are set more than once and used in more than one
281 basic block are nevertheless always set in similar ways. For example,
282 a QImode register may be loaded from memory in two places on a machine
283 where byte loads zero extend.
285 We record in the following array what we know about the nonzero
286 bits of a register, specifically which bits are known to be zero.
288 If an entry is zero, it means that we don't know anything special. */
290 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
292 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
293 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
295 static enum machine_mode nonzero_bits_mode
;
297 /* Nonzero if we know that a register has some leading bits that are always
298 equal to the sign bit. */
300 static unsigned char *reg_sign_bit_copies
;
302 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
303 It is zero while computing them and after combine has completed. This
304 former test prevents propagating values based on previously set values,
305 which can be incorrect if a variable is modified in a loop. */
307 static int nonzero_sign_valid
;
309 /* These arrays are maintained in parallel with reg_last_set_value
310 and are used to store the mode in which the register was last set,
311 the bits that were known to be zero when it was last set, and the
312 number of sign bits copies it was known to have when it was last set. */
314 static enum machine_mode
*reg_last_set_mode
;
315 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
316 static char *reg_last_set_sign_bit_copies
;
318 /* Record one modification to rtl structure
319 to be undone by storing old_contents into *where.
320 is_int is 1 if the contents are an int. */
326 union {rtx r
; unsigned int i
;} old_contents
;
327 union {rtx
*r
; unsigned int *i
;} where
;
330 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
331 num_undo says how many are currently recorded.
333 other_insn is nonzero if we have modified some other insn in the process
334 of working on subst_insn. It must be verified too.
336 previous_undos is the value of undobuf.undos when we started processing
337 this substitution. This will prevent gen_rtx_combine from re-used a piece
338 from the previous expression. Doing so can produce circular rtl
345 struct undo
*previous_undos
;
349 static struct undobuf undobuf
;
351 /* Number of times the pseudo being substituted for
352 was found and replaced. */
354 static int n_occurrences
;
356 static void do_SUBST
PARAMS ((rtx
*, rtx
));
357 static void do_SUBST_INT
PARAMS ((unsigned int *,
359 static void init_reg_last_arrays
PARAMS ((void));
360 static void setup_incoming_promotions
PARAMS ((void));
361 static void set_nonzero_bits_and_sign_copies
PARAMS ((rtx
, rtx
, void *));
362 static int cant_combine_insn_p
PARAMS ((rtx
));
363 static int can_combine_p
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
364 static int sets_function_arg_p
PARAMS ((rtx
));
365 static int combinable_i3pat
PARAMS ((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
366 static int contains_muldiv
PARAMS ((rtx
));
367 static rtx try_combine
PARAMS ((rtx
, rtx
, rtx
, int *));
368 static void undo_all
PARAMS ((void));
369 static void undo_commit
PARAMS ((void));
370 static rtx
*find_split_point
PARAMS ((rtx
*, rtx
));
371 static rtx subst
PARAMS ((rtx
, rtx
, rtx
, int, int));
372 static rtx combine_simplify_rtx
PARAMS ((rtx
, enum machine_mode
, int, int));
373 static rtx simplify_if_then_else
PARAMS ((rtx
));
374 static rtx simplify_set
PARAMS ((rtx
));
375 static rtx simplify_logical
PARAMS ((rtx
, int));
376 static rtx expand_compound_operation
PARAMS ((rtx
));
377 static rtx expand_field_assignment
PARAMS ((rtx
));
378 static rtx make_extraction
PARAMS ((enum machine_mode
, rtx
, HOST_WIDE_INT
,
379 rtx
, unsigned HOST_WIDE_INT
, int,
381 static rtx extract_left_shift
PARAMS ((rtx
, int));
382 static rtx make_compound_operation
PARAMS ((rtx
, enum rtx_code
));
383 static int get_pos_from_mask
PARAMS ((unsigned HOST_WIDE_INT
,
384 unsigned HOST_WIDE_INT
*));
385 static rtx force_to_mode
PARAMS ((rtx
, enum machine_mode
,
386 unsigned HOST_WIDE_INT
, rtx
, int));
387 static rtx if_then_else_cond
PARAMS ((rtx
, rtx
*, rtx
*));
388 static rtx known_cond
PARAMS ((rtx
, enum rtx_code
, rtx
, rtx
));
389 static int rtx_equal_for_field_assignment_p
PARAMS ((rtx
, rtx
));
390 static rtx make_field_assignment
PARAMS ((rtx
));
391 static rtx apply_distributive_law
PARAMS ((rtx
));
392 static rtx simplify_and_const_int
PARAMS ((rtx
, enum machine_mode
, rtx
,
393 unsigned HOST_WIDE_INT
));
394 static unsigned HOST_WIDE_INT nonzero_bits
PARAMS ((rtx
, enum machine_mode
));
395 static unsigned int num_sign_bit_copies
PARAMS ((rtx
, enum machine_mode
));
396 static int merge_outer_ops
PARAMS ((enum rtx_code
*, HOST_WIDE_INT
*,
397 enum rtx_code
, HOST_WIDE_INT
,
398 enum machine_mode
, int *));
399 static rtx simplify_shift_const
PARAMS ((rtx
, enum rtx_code
, enum machine_mode
,
401 static int recog_for_combine
PARAMS ((rtx
*, rtx
, rtx
*));
402 static rtx gen_lowpart_for_combine
PARAMS ((enum machine_mode
, rtx
));
403 static rtx gen_rtx_combine
PARAMS ((enum rtx_code code
, enum machine_mode mode
,
405 static rtx gen_binary
PARAMS ((enum rtx_code
, enum machine_mode
,
407 static rtx gen_unary
PARAMS ((enum rtx_code
, enum machine_mode
,
408 enum machine_mode
, rtx
));
409 static enum rtx_code simplify_comparison
PARAMS ((enum rtx_code
, rtx
*, rtx
*));
410 static void update_table_tick
PARAMS ((rtx
));
411 static void record_value_for_reg
PARAMS ((rtx
, rtx
, rtx
));
412 static void check_promoted_subreg
PARAMS ((rtx
, rtx
));
413 static void record_dead_and_set_regs_1
PARAMS ((rtx
, rtx
, void *));
414 static void record_dead_and_set_regs
PARAMS ((rtx
));
415 static int get_last_value_validate
PARAMS ((rtx
*, rtx
, int, int));
416 static rtx get_last_value
PARAMS ((rtx
));
417 static int use_crosses_set_p
PARAMS ((rtx
, int));
418 static void reg_dead_at_p_1
PARAMS ((rtx
, rtx
, void *));
419 static int reg_dead_at_p
PARAMS ((rtx
, rtx
));
420 static void move_deaths
PARAMS ((rtx
, rtx
, int, rtx
, rtx
*));
421 static int reg_bitfield_target_p
PARAMS ((rtx
, rtx
));
422 static void distribute_notes
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
423 static void distribute_links
PARAMS ((rtx
));
424 static void mark_used_regs_combine
PARAMS ((rtx
));
425 static int insn_cuid
PARAMS ((rtx
));
426 static void record_promoted_value
PARAMS ((rtx
, rtx
));
427 static rtx reversed_comparison
PARAMS ((rtx
, enum machine_mode
, rtx
, rtx
));
428 static enum rtx_code combine_reversed_comparison_code
PARAMS ((rtx
));
430 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
431 insn. The substitution can be undone by undo_all. If INTO is already
432 set to NEWVAL, do not record this change. Because computing NEWVAL might
433 also call SUBST, we have to compute it before we put anything into
437 do_SUBST (into
, newval
)
443 if (oldval
== newval
)
447 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
449 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
453 buf
->old_contents
.r
= oldval
;
456 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
459 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
461 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
462 for the value of a HOST_WIDE_INT value (including CONST_INT) is
466 do_SUBST_INT (into
, newval
)
467 unsigned int *into
, newval
;
470 unsigned int oldval
= *into
;
472 if (oldval
== newval
)
476 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
478 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
482 buf
->old_contents
.i
= oldval
;
485 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
488 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
490 /* Main entry point for combiner. F is the first insn of the function.
491 NREGS is the first unused pseudo-reg number.
493 Return non-zero if the combiner has turned an indirect jump
494 instruction into a direct jump. */
496 combine_instructions (f
, nregs
)
500 register rtx insn
, next
;
505 register rtx links
, nextlinks
;
507 int new_direct_jump_p
= 0;
509 combine_attempts
= 0;
512 combine_successes
= 0;
514 combine_max_regno
= nregs
;
516 reg_nonzero_bits
= ((unsigned HOST_WIDE_INT
*)
517 xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
)));
519 = (unsigned char *) xcalloc (nregs
, sizeof (unsigned char));
521 reg_last_death
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
522 reg_last_set
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
523 reg_last_set_value
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
524 reg_last_set_table_tick
= (int *) xmalloc (nregs
* sizeof (int));
525 reg_last_set_label
= (int *) xmalloc (nregs
* sizeof (int));
526 reg_last_set_invalid
= (char *) xmalloc (nregs
* sizeof (char));
528 = (enum machine_mode
*) xmalloc (nregs
* sizeof (enum machine_mode
));
529 reg_last_set_nonzero_bits
530 = (unsigned HOST_WIDE_INT
*) xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
531 reg_last_set_sign_bit_copies
532 = (char *) xmalloc (nregs
* sizeof (char));
534 init_reg_last_arrays ();
536 init_recog_no_volatile ();
538 /* Compute maximum uid value so uid_cuid can be allocated. */
540 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
541 if (INSN_UID (insn
) > i
)
544 uid_cuid
= (int *) xmalloc ((i
+ 1) * sizeof (int));
547 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
549 /* Don't use reg_nonzero_bits when computing it. This can cause problems
550 when, for example, we have j <<= 1 in a loop. */
552 nonzero_sign_valid
= 0;
554 /* Compute the mapping from uids to cuids.
555 Cuids are numbers assigned to insns, like uids,
556 except that cuids increase monotonically through the code.
558 Scan all SETs and see if we can deduce anything about what
559 bits are known to be zero for some registers and how many copies
560 of the sign bit are known to exist for those registers.
562 Also set any known values so that we can use it while searching
563 for what bits are known to be set. */
567 /* We need to initialize it here, because record_dead_and_set_regs may call
569 subst_prev_insn
= NULL_RTX
;
571 setup_incoming_promotions ();
573 refresh_blocks
= sbitmap_alloc (n_basic_blocks
);
574 sbitmap_zero (refresh_blocks
);
577 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
579 uid_cuid
[INSN_UID (insn
)] = ++i
;
585 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
587 record_dead_and_set_regs (insn
);
590 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
591 if (REG_NOTE_KIND (links
) == REG_INC
)
592 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
597 if (GET_CODE (insn
) == CODE_LABEL
)
601 nonzero_sign_valid
= 1;
603 /* Now scan all the insns in forward order. */
605 this_basic_block
= -1;
609 init_reg_last_arrays ();
610 setup_incoming_promotions ();
612 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
616 /* If INSN starts a new basic block, update our basic block number. */
617 if (this_basic_block
+ 1 < n_basic_blocks
618 && BLOCK_HEAD (this_basic_block
+ 1) == insn
)
621 if (GET_CODE (insn
) == CODE_LABEL
)
624 else if (INSN_P (insn
))
626 /* See if we know about function return values before this
627 insn based upon SUBREG flags. */
628 check_promoted_subreg (insn
, PATTERN (insn
));
630 /* Try this insn with each insn it links back to. */
632 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
633 if ((next
= try_combine (insn
, XEXP (links
, 0),
634 NULL_RTX
, &new_direct_jump_p
)) != 0)
637 /* Try each sequence of three linked insns ending with this one. */
639 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
641 rtx link
= XEXP (links
, 0);
643 /* If the linked insn has been replaced by a note, then there
644 is no point in persuing this chain any further. */
645 if (GET_CODE (link
) == NOTE
)
648 for (nextlinks
= LOG_LINKS (link
);
650 nextlinks
= XEXP (nextlinks
, 1))
651 if ((next
= try_combine (insn
, XEXP (links
, 0),
653 &new_direct_jump_p
)) != 0)
658 /* Try to combine a jump insn that uses CC0
659 with a preceding insn that sets CC0, and maybe with its
660 logical predecessor as well.
661 This is how we make decrement-and-branch insns.
662 We need this special code because data flow connections
663 via CC0 do not get entered in LOG_LINKS. */
665 if (GET_CODE (insn
) == JUMP_INSN
666 && (prev
= prev_nonnote_insn (insn
)) != 0
667 && GET_CODE (prev
) == INSN
668 && sets_cc0_p (PATTERN (prev
)))
670 if ((next
= try_combine (insn
, prev
,
671 NULL_RTX
, &new_direct_jump_p
)) != 0)
674 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
675 nextlinks
= XEXP (nextlinks
, 1))
676 if ((next
= try_combine (insn
, prev
,
678 &new_direct_jump_p
)) != 0)
682 /* Do the same for an insn that explicitly references CC0. */
683 if (GET_CODE (insn
) == INSN
684 && (prev
= prev_nonnote_insn (insn
)) != 0
685 && GET_CODE (prev
) == INSN
686 && sets_cc0_p (PATTERN (prev
))
687 && GET_CODE (PATTERN (insn
)) == SET
688 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
690 if ((next
= try_combine (insn
, prev
,
691 NULL_RTX
, &new_direct_jump_p
)) != 0)
694 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
695 nextlinks
= XEXP (nextlinks
, 1))
696 if ((next
= try_combine (insn
, prev
,
698 &new_direct_jump_p
)) != 0)
702 /* Finally, see if any of the insns that this insn links to
703 explicitly references CC0. If so, try this insn, that insn,
704 and its predecessor if it sets CC0. */
705 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
706 if (GET_CODE (XEXP (links
, 0)) == INSN
707 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
708 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
709 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
710 && GET_CODE (prev
) == INSN
711 && sets_cc0_p (PATTERN (prev
))
712 && (next
= try_combine (insn
, XEXP (links
, 0),
713 prev
, &new_direct_jump_p
)) != 0)
717 /* Try combining an insn with two different insns whose results it
719 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
720 for (nextlinks
= XEXP (links
, 1); nextlinks
;
721 nextlinks
= XEXP (nextlinks
, 1))
722 if ((next
= try_combine (insn
, XEXP (links
, 0),
724 &new_direct_jump_p
)) != 0)
727 if (GET_CODE (insn
) != NOTE
)
728 record_dead_and_set_regs (insn
);
737 compute_bb_for_insn (get_max_uid ());
738 update_life_info (refresh_blocks
, UPDATE_LIFE_GLOBAL_RM_NOTES
,
743 sbitmap_free (refresh_blocks
);
744 free (reg_nonzero_bits
);
745 free (reg_sign_bit_copies
);
746 free (reg_last_death
);
748 free (reg_last_set_value
);
749 free (reg_last_set_table_tick
);
750 free (reg_last_set_label
);
751 free (reg_last_set_invalid
);
752 free (reg_last_set_mode
);
753 free (reg_last_set_nonzero_bits
);
754 free (reg_last_set_sign_bit_copies
);
758 struct undo
*undo
, *next
;
759 for (undo
= undobuf
.frees
; undo
; undo
= next
)
767 total_attempts
+= combine_attempts
;
768 total_merges
+= combine_merges
;
769 total_extras
+= combine_extras
;
770 total_successes
+= combine_successes
;
772 nonzero_sign_valid
= 0;
774 /* Make recognizer allow volatile MEMs again. */
777 return new_direct_jump_p
;
780 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
783 init_reg_last_arrays ()
785 unsigned int nregs
= combine_max_regno
;
787 memset ((char *) reg_last_death
, 0, nregs
* sizeof (rtx
));
788 memset ((char *) reg_last_set
, 0, nregs
* sizeof (rtx
));
789 memset ((char *) reg_last_set_value
, 0, nregs
* sizeof (rtx
));
790 memset ((char *) reg_last_set_table_tick
, 0, nregs
* sizeof (int));
791 memset ((char *) reg_last_set_label
, 0, nregs
* sizeof (int));
792 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
793 memset ((char *) reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
794 memset ((char *) reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
795 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
798 /* Set up any promoted values for incoming argument registers. */
801 setup_incoming_promotions ()
803 #ifdef PROMOTE_FUNCTION_ARGS
806 enum machine_mode mode
;
808 rtx first
= get_insns ();
810 #ifndef OUTGOING_REGNO
811 #define OUTGOING_REGNO(N) N
813 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
814 /* Check whether this register can hold an incoming pointer
815 argument. FUNCTION_ARG_REGNO_P tests outgoing register
816 numbers, so translate if necessary due to register windows. */
817 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
818 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
821 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
824 gen_rtx_CLOBBER (mode
, const0_rtx
)));
829 /* Called via note_stores. If X is a pseudo that is narrower than
830 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
832 If we are setting only a portion of X and we can't figure out what
833 portion, assume all bits will be used since we don't know what will
836 Similarly, set how many bits of X are known to be copies of the sign bit
837 at all locations in the function. This is the smallest number implied
841 set_nonzero_bits_and_sign_copies (x
, set
, data
)
844 void *data ATTRIBUTE_UNUSED
;
848 if (GET_CODE (x
) == REG
849 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
850 /* If this register is undefined at the start of the file, we can't
851 say what its contents were. */
852 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, REGNO (x
))
853 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
855 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
857 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
858 reg_sign_bit_copies
[REGNO (x
)] = 1;
862 /* If this is a complex assignment, see if we can convert it into a
863 simple assignment. */
864 set
= expand_field_assignment (set
);
866 /* If this is a simple assignment, or we have a paradoxical SUBREG,
867 set what we know about X. */
869 if (SET_DEST (set
) == x
870 || (GET_CODE (SET_DEST (set
)) == SUBREG
871 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
872 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
873 && SUBREG_REG (SET_DEST (set
)) == x
))
875 rtx src
= SET_SRC (set
);
877 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
878 /* If X is narrower than a word and SRC is a non-negative
879 constant that would appear negative in the mode of X,
880 sign-extend it for use in reg_nonzero_bits because some
881 machines (maybe most) will actually do the sign-extension
882 and this is the conservative approach.
884 ??? For 2.5, try to tighten up the MD files in this regard
885 instead of this kludge. */
887 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
888 && GET_CODE (src
) == CONST_INT
890 && 0 != (INTVAL (src
)
892 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
893 src
= GEN_INT (INTVAL (src
)
894 | ((HOST_WIDE_INT
) (-1)
895 << GET_MODE_BITSIZE (GET_MODE (x
))));
898 reg_nonzero_bits
[REGNO (x
)]
899 |= nonzero_bits (src
, nonzero_bits_mode
);
900 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
901 if (reg_sign_bit_copies
[REGNO (x
)] == 0
902 || reg_sign_bit_copies
[REGNO (x
)] > num
)
903 reg_sign_bit_copies
[REGNO (x
)] = num
;
907 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
908 reg_sign_bit_copies
[REGNO (x
)] = 1;
913 /* See if INSN can be combined into I3. PRED and SUCC are optionally
914 insns that were previously combined into I3 or that will be combined
915 into the merger of INSN and I3.
917 Return 0 if the combination is not allowed for any reason.
919 If the combination is allowed, *PDEST will be set to the single
920 destination of INSN and *PSRC to the single source, and this function
924 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
927 rtx pred ATTRIBUTE_UNUSED
;
932 rtx set
= 0, src
, dest
;
937 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
938 && next_active_insn (succ
) == i3
)
939 : next_active_insn (insn
) == i3
);
941 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
942 or a PARALLEL consisting of such a SET and CLOBBERs.
944 If INSN has CLOBBER parallel parts, ignore them for our processing.
945 By definition, these happen during the execution of the insn. When it
946 is merged with another insn, all bets are off. If they are, in fact,
947 needed and aren't also supplied in I3, they may be added by
948 recog_for_combine. Otherwise, it won't match.
950 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
953 Get the source and destination of INSN. If more than one, can't
956 if (GET_CODE (PATTERN (insn
)) == SET
)
957 set
= PATTERN (insn
);
958 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
959 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
961 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
963 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
965 switch (GET_CODE (elt
))
967 /* This is important to combine floating point insns
970 /* Combining an isolated USE doesn't make sense.
971 We depend here on combinable_i3_pat to reject them. */
972 /* The code below this loop only verifies that the inputs of
973 the SET in INSN do not change. We call reg_set_between_p
974 to verify that the REG in the USE does not change betweeen
976 If the USE in INSN was for a pseudo register, the matching
977 insn pattern will likely match any register; combining this
978 with any other USE would only be safe if we knew that the
979 used registers have identical values, or if there was
980 something to tell them apart, e.g. different modes. For
981 now, we forgo such compilcated tests and simply disallow
982 combining of USES of pseudo registers with any other USE. */
983 if (GET_CODE (XEXP (elt
, 0)) == REG
984 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
986 rtx i3pat
= PATTERN (i3
);
987 int i
= XVECLEN (i3pat
, 0) - 1;
988 unsigned int regno
= REGNO (XEXP (elt
, 0));
992 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
994 if (GET_CODE (i3elt
) == USE
995 && GET_CODE (XEXP (i3elt
, 0)) == REG
996 && (REGNO (XEXP (i3elt
, 0)) == regno
997 ? reg_set_between_p (XEXP (elt
, 0),
998 PREV_INSN (insn
), i3
)
999 : regno
>= FIRST_PSEUDO_REGISTER
))
1006 /* We can ignore CLOBBERs. */
1011 /* Ignore SETs whose result isn't used but not those that
1012 have side-effects. */
1013 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1014 && ! side_effects_p (elt
))
1017 /* If we have already found a SET, this is a second one and
1018 so we cannot combine with this insn. */
1026 /* Anything else means we can't combine. */
1032 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1033 so don't do anything with it. */
1034 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1043 set
= expand_field_assignment (set
);
1044 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1046 /* Don't eliminate a store in the stack pointer. */
1047 if (dest
== stack_pointer_rtx
1048 /* If we couldn't eliminate a field assignment, we can't combine. */
1049 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
1050 /* Don't combine with an insn that sets a register to itself if it has
1051 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1052 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1053 /* Can't merge an ASM_OPERANDS. */
1054 || GET_CODE (src
) == ASM_OPERANDS
1055 /* Can't merge a function call. */
1056 || GET_CODE (src
) == CALL
1057 /* Don't eliminate a function call argument. */
1058 || (GET_CODE (i3
) == CALL_INSN
1059 && (find_reg_fusage (i3
, USE
, dest
)
1060 || (GET_CODE (dest
) == REG
1061 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1062 && global_regs
[REGNO (dest
)])))
1063 /* Don't substitute into an incremented register. */
1064 || FIND_REG_INC_NOTE (i3
, dest
)
1065 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1067 /* Don't combine the end of a libcall into anything. */
1068 /* ??? This gives worse code, and appears to be unnecessary, since no
1069 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1070 use REG_RETVAL notes for noconflict blocks, but other code here
1071 makes sure that those insns don't disappear. */
1072 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1074 /* Make sure that DEST is not used after SUCC but before I3. */
1075 || (succ
&& ! all_adjacent
1076 && reg_used_between_p (dest
, succ
, i3
))
1077 /* Make sure that the value that is to be substituted for the register
1078 does not use any registers whose values alter in between. However,
1079 If the insns are adjacent, a use can't cross a set even though we
1080 think it might (this can happen for a sequence of insns each setting
1081 the same destination; reg_last_set of that register might point to
1082 a NOTE). If INSN has a REG_EQUIV note, the register is always
1083 equivalent to the memory so the substitution is valid even if there
1084 are intervening stores. Also, don't move a volatile asm or
1085 UNSPEC_VOLATILE across any other insns. */
1087 && (((GET_CODE (src
) != MEM
1088 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1089 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1090 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1091 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1092 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1093 better register allocation by not doing the combine. */
1094 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1095 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1096 /* Don't combine across a CALL_INSN, because that would possibly
1097 change whether the life span of some REGs crosses calls or not,
1098 and it is a pain to update that information.
1099 Exception: if source is a constant, moving it later can't hurt.
1100 Accept that special case, because it helps -fforce-addr a lot. */
1101 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1104 /* DEST must either be a REG or CC0. */
1105 if (GET_CODE (dest
) == REG
)
1107 /* If register alignment is being enforced for multi-word items in all
1108 cases except for parameters, it is possible to have a register copy
1109 insn referencing a hard register that is not allowed to contain the
1110 mode being copied and which would not be valid as an operand of most
1111 insns. Eliminate this problem by not combining with such an insn.
1113 Also, on some machines we don't want to extend the life of a hard
1116 if (GET_CODE (src
) == REG
1117 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1118 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1119 /* Don't extend the life of a hard register unless it is
1120 user variable (if we have few registers) or it can't
1121 fit into the desired register (meaning something special
1123 Also avoid substituting a return register into I3, because
1124 reload can't handle a conflict with constraints of other
1126 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1127 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1130 else if (GET_CODE (dest
) != CC0
)
1133 /* Don't substitute for a register intended as a clobberable operand.
1134 Similarly, don't substitute an expression containing a register that
1135 will be clobbered in I3. */
1136 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1137 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1138 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1139 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1141 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1144 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1145 or not), reject, unless nothing volatile comes between it and I3 */
1147 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1149 /* Make sure succ doesn't contain a volatile reference. */
1150 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1153 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1154 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1158 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1159 to be an explicit register variable, and was chosen for a reason. */
1161 if (GET_CODE (src
) == ASM_OPERANDS
1162 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1165 /* If there are any volatile insns between INSN and I3, reject, because
1166 they might affect machine state. */
1168 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1169 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1172 /* If INSN or I2 contains an autoincrement or autodecrement,
1173 make sure that register is not used between there and I3,
1174 and not already used in I3 either.
1175 Also insist that I3 not be a jump; if it were one
1176 and the incremented register were spilled, we would lose. */
1179 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1180 if (REG_NOTE_KIND (link
) == REG_INC
1181 && (GET_CODE (i3
) == JUMP_INSN
1182 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1183 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1188 /* Don't combine an insn that follows a CC0-setting insn.
1189 An insn that uses CC0 must not be separated from the one that sets it.
1190 We do, however, allow I2 to follow a CC0-setting insn if that insn
1191 is passed as I1; in that case it will be deleted also.
1192 We also allow combining in this case if all the insns are adjacent
1193 because that would leave the two CC0 insns adjacent as well.
1194 It would be more logical to test whether CC0 occurs inside I1 or I2,
1195 but that would be much slower, and this ought to be equivalent. */
1197 p
= prev_nonnote_insn (insn
);
1198 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1203 /* If we get here, we have passed all the tests and the combination is
1212 /* Check if PAT is an insn - or a part of it - used to set up an
1213 argument for a function in a hard register. */
1216 sets_function_arg_p (pat
)
1222 switch (GET_CODE (pat
))
1225 return sets_function_arg_p (PATTERN (pat
));
1228 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1229 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1235 inner_dest
= SET_DEST (pat
);
1236 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1237 || GET_CODE (inner_dest
) == SUBREG
1238 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1239 inner_dest
= XEXP (inner_dest
, 0);
1241 return (GET_CODE (inner_dest
) == REG
1242 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1243 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1252 /* LOC is the location within I3 that contains its pattern or the component
1253 of a PARALLEL of the pattern. We validate that it is valid for combining.
1255 One problem is if I3 modifies its output, as opposed to replacing it
1256 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1257 so would produce an insn that is not equivalent to the original insns.
1261 (set (reg:DI 101) (reg:DI 100))
1262 (set (subreg:SI (reg:DI 101) 0) <foo>)
1264 This is NOT equivalent to:
1266 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1267 (set (reg:DI 101) (reg:DI 100))])
1269 Not only does this modify 100 (in which case it might still be valid
1270 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1272 We can also run into a problem if I2 sets a register that I1
1273 uses and I1 gets directly substituted into I3 (not via I2). In that
1274 case, we would be getting the wrong value of I2DEST into I3, so we
1275 must reject the combination. This case occurs when I2 and I1 both
1276 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1277 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1278 of a SET must prevent combination from occurring.
1280 Before doing the above check, we first try to expand a field assignment
1281 into a set of logical operations.
1283 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1284 we place a register that is both set and used within I3. If more than one
1285 such register is detected, we fail.
1287 Return 1 if the combination is valid, zero otherwise. */
1290 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1296 rtx
*pi3dest_killed
;
1300 if (GET_CODE (x
) == SET
)
1302 rtx set
= expand_field_assignment (x
);
1303 rtx dest
= SET_DEST (set
);
1304 rtx src
= SET_SRC (set
);
1305 rtx inner_dest
= dest
;
1308 rtx inner_src
= src
;
1313 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1314 || GET_CODE (inner_dest
) == SUBREG
1315 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1316 inner_dest
= XEXP (inner_dest
, 0);
1318 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1321 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1322 || GET_CODE (inner_src
) == SUBREG
1323 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1324 inner_src
= XEXP (inner_src
, 0);
1326 /* If it is better that two different modes keep two different pseudos,
1327 avoid combining them. This avoids producing the following pattern
1329 (set (subreg:SI (reg/v:QI 21) 0)
1330 (lshiftrt:SI (reg/v:SI 20)
1332 If that were made, reload could not handle the pair of
1333 reg 20/21, since it would try to get any GENERAL_REGS
1334 but some of them don't handle QImode. */
1336 if (rtx_equal_p (inner_src
, i2dest
)
1337 && GET_CODE (inner_dest
) == REG
1338 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1342 /* Check for the case where I3 modifies its output, as
1344 if ((inner_dest
!= dest
1345 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1346 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1348 /* This is the same test done in can_combine_p except we can't test
1349 all_adjacent; we don't have to, since this instruction will stay
1350 in place, thus we are not considering increasing the lifetime of
1353 Also, if this insn sets a function argument, combining it with
1354 something that might need a spill could clobber a previous
1355 function argument; the all_adjacent test in can_combine_p also
1356 checks this; here, we do a more specific test for this case. */
1358 || (GET_CODE (inner_dest
) == REG
1359 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1360 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1361 GET_MODE (inner_dest
))))
1362 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1365 /* If DEST is used in I3, it is being killed in this insn,
1366 so record that for later.
1367 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1368 STACK_POINTER_REGNUM, since these are always considered to be
1369 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1370 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1371 && reg_referenced_p (dest
, PATTERN (i3
))
1372 && REGNO (dest
) != FRAME_POINTER_REGNUM
1373 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1374 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1376 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1377 && (REGNO (dest
) != ARG_POINTER_REGNUM
1378 || ! fixed_regs
[REGNO (dest
)])
1380 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1382 if (*pi3dest_killed
)
1385 *pi3dest_killed
= dest
;
1389 else if (GET_CODE (x
) == PARALLEL
)
1393 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1394 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1395 i1_not_in_src
, pi3dest_killed
))
1402 /* Return 1 if X is an arithmetic expression that contains a multiplication
1403 and division. We don't count multiplications by powers of two here. */
1409 switch (GET_CODE (x
))
1411 case MOD
: case DIV
: case UMOD
: case UDIV
:
1415 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1416 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1418 switch (GET_RTX_CLASS (GET_CODE (x
)))
1420 case 'c': case '<': case '2':
1421 return contains_muldiv (XEXP (x
, 0))
1422 || contains_muldiv (XEXP (x
, 1));
1425 return contains_muldiv (XEXP (x
, 0));
1433 /* Determine whether INSN can be used in a combination. Return nonzero if
1434 not. This is used in try_combine to detect early some cases where we
1435 can't perform combinations. */
1438 cant_combine_insn_p (insn
)
1444 /* If this isn't really an insn, we can't do anything.
1445 This can occur when flow deletes an insn that it has merged into an
1446 auto-increment address. */
1447 if (! INSN_P (insn
))
1450 /* Never combine loads and stores involving hard regs. The register
1451 allocator can usually handle such reg-reg moves by tying. If we allow
1452 the combiner to make substitutions of hard regs, we risk aborting in
1453 reload on machines that have SMALL_REGISTER_CLASSES.
1454 As an exception, we allow combinations involving fixed regs; these are
1455 not available to the register allocator so there's no risk involved. */
1457 set
= single_set (insn
);
1460 src
= SET_SRC (set
);
1461 dest
= SET_DEST (set
);
1462 if (GET_CODE (src
) == SUBREG
)
1463 src
= SUBREG_REG (src
);
1464 if (GET_CODE (dest
) == SUBREG
)
1465 dest
= SUBREG_REG (dest
);
1466 if (REG_P (src
) && REG_P (dest
)
1467 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1468 && ! fixed_regs
[REGNO (src
)])
1469 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1470 && ! fixed_regs
[REGNO (dest
)])))
1476 /* Try to combine the insns I1 and I2 into I3.
1477 Here I1 and I2 appear earlier than I3.
1478 I1 can be zero; then we combine just I2 into I3.
1480 It we are combining three insns and the resulting insn is not recognized,
1481 try splitting it into two insns. If that happens, I2 and I3 are retained
1482 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1485 Return 0 if the combination does not work. Then nothing is changed.
1486 If we did the combination, return the insn at which combine should
1489 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1490 new direct jump instruction. */
1493 try_combine (i3
, i2
, i1
, new_direct_jump_p
)
1494 register rtx i3
, i2
, i1
;
1495 register int *new_direct_jump_p
;
1497 /* New patterns for I3 and I2, respectively. */
1498 rtx newpat
, newi2pat
= 0;
1499 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1500 int added_sets_1
, added_sets_2
;
1501 /* Total number of SETs to put into I3. */
1503 /* Nonzero is I2's body now appears in I3. */
1505 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1506 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1507 /* Contains I3 if the destination of I3 is used in its source, which means
1508 that the old life of I3 is being killed. If that usage is placed into
1509 I2 and not in I3, a REG_DEAD note must be made. */
1510 rtx i3dest_killed
= 0;
1511 /* SET_DEST and SET_SRC of I2 and I1. */
1512 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1513 /* PATTERN (I2), or a copy of it in certain cases. */
1515 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1516 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1517 int i1_feeds_i3
= 0;
1518 /* Notes that must be added to REG_NOTES in I3 and I2. */
1519 rtx new_i3_notes
, new_i2_notes
;
1520 /* Notes that we substituted I3 into I2 instead of the normal case. */
1521 int i3_subst_into_i2
= 0;
1522 /* Notes that I1, I2 or I3 is a MULT operation. */
1530 /* Exit early if one of the insns involved can't be used for
1532 if (cant_combine_insn_p (i3
)
1533 || cant_combine_insn_p (i2
)
1534 || (i1
&& cant_combine_insn_p (i1
))
1535 /* We also can't do anything if I3 has a
1536 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1539 /* ??? This gives worse code, and appears to be unnecessary, since no
1540 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1541 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1547 undobuf
.other_insn
= 0;
1549 /* Reset the hard register usage information. */
1550 CLEAR_HARD_REG_SET (newpat_used_regs
);
1552 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1553 code below, set I1 to be the earlier of the two insns. */
1554 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1555 temp
= i1
, i1
= i2
, i2
= temp
;
1557 added_links_insn
= 0;
1559 /* First check for one important special-case that the code below will
1560 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1561 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1562 we may be able to replace that destination with the destination of I3.
1563 This occurs in the common code where we compute both a quotient and
1564 remainder into a structure, in which case we want to do the computation
1565 directly into the structure to avoid register-register copies.
1567 Note that this case handles both multiple sets in I2 and also
1568 cases where I2 has a number of CLOBBER or PARALLELs.
1570 We make very conservative checks below and only try to handle the
1571 most common cases of this. For example, we only handle the case
1572 where I2 and I3 are adjacent to avoid making difficult register
1575 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1576 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1577 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1578 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1579 && GET_CODE (PATTERN (i2
)) == PARALLEL
1580 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1581 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1582 below would need to check what is inside (and reg_overlap_mentioned_p
1583 doesn't support those codes anyway). Don't allow those destinations;
1584 the resulting insn isn't likely to be recognized anyway. */
1585 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1586 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1587 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1588 SET_DEST (PATTERN (i3
)))
1589 && next_real_insn (i2
) == i3
)
1591 rtx p2
= PATTERN (i2
);
1593 /* Make sure that the destination of I3,
1594 which we are going to substitute into one output of I2,
1595 is not used within another output of I2. We must avoid making this:
1596 (parallel [(set (mem (reg 69)) ...)
1597 (set (reg 69) ...)])
1598 which is not well-defined as to order of actions.
1599 (Besides, reload can't handle output reloads for this.)
1601 The problem can also happen if the dest of I3 is a memory ref,
1602 if another dest in I2 is an indirect memory ref. */
1603 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1604 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1605 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1606 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1607 SET_DEST (XVECEXP (p2
, 0, i
))))
1610 if (i
== XVECLEN (p2
, 0))
1611 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1612 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1613 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1614 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1619 subst_low_cuid
= INSN_CUID (i2
);
1621 added_sets_2
= added_sets_1
= 0;
1622 i2dest
= SET_SRC (PATTERN (i3
));
1624 /* Replace the dest in I2 with our dest and make the resulting
1625 insn the new pattern for I3. Then skip to where we
1626 validate the pattern. Everything was set up above. */
1627 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1628 SET_DEST (PATTERN (i3
)));
1631 i3_subst_into_i2
= 1;
1632 goto validate_replacement
;
1636 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1637 one of those words to another constant, merge them by making a new
1640 && (temp
= single_set (i2
)) != 0
1641 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1642 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1643 && GET_CODE (SET_DEST (temp
)) == REG
1644 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1645 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1646 && GET_CODE (PATTERN (i3
)) == SET
1647 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1648 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1649 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1650 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1651 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1653 HOST_WIDE_INT lo
, hi
;
1655 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1656 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1659 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1660 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1663 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1665 /* We don't handle the case of the target word being wider
1666 than a host wide int. */
1667 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1670 lo
&= ~(((unsigned HOST_WIDE_INT
)1 << BITS_PER_WORD
) - 1);
1671 lo
|= INTVAL (SET_SRC (PATTERN (i3
)));
1673 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1674 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1675 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1677 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1678 >> (HOST_BITS_PER_WIDE_INT
- 1));
1680 lo
&= ~((((unsigned HOST_WIDE_INT
)1 << BITS_PER_WORD
) - 1)
1682 lo
|= INTVAL (SET_SRC (PATTERN (i3
))) << BITS_PER_WORD
;
1684 hi
= lo
< 0 ? -1 : 0;
1687 /* We don't handle the case of the higher word not fitting
1688 entirely in either hi or lo. */
1693 subst_low_cuid
= INSN_CUID (i2
);
1694 added_sets_2
= added_sets_1
= 0;
1695 i2dest
= SET_DEST (temp
);
1697 SUBST (SET_SRC (temp
),
1698 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1700 newpat
= PATTERN (i2
);
1701 goto validate_replacement
;
1705 /* If we have no I1 and I2 looks like:
1706 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1708 make up a dummy I1 that is
1711 (set (reg:CC X) (compare:CC Y (const_int 0)))
1713 (We can ignore any trailing CLOBBERs.)
1715 This undoes a previous combination and allows us to match a branch-and-
1718 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1719 && XVECLEN (PATTERN (i2
), 0) >= 2
1720 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1721 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1723 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1724 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1725 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1726 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1727 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1728 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1730 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1731 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1736 /* We make I1 with the same INSN_UID as I2. This gives it
1737 the same INSN_CUID for value tracking. Our fake I1 will
1738 never appear in the insn stream so giving it the same INSN_UID
1739 as I2 will not cause a problem. */
1741 subst_prev_insn
= i1
1742 = gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1743 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1746 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1747 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1748 SET_DEST (PATTERN (i1
)));
1753 /* Verify that I2 and I1 are valid for combining. */
1754 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1755 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1761 /* Record whether I2DEST is used in I2SRC and similarly for the other
1762 cases. Knowing this will help in register status updating below. */
1763 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1764 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1765 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1767 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1769 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1771 /* Ensure that I3's pattern can be the destination of combines. */
1772 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1773 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1780 /* See if any of the insns is a MULT operation. Unless one is, we will
1781 reject a combination that is, since it must be slower. Be conservative
1783 if (GET_CODE (i2src
) == MULT
1784 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1785 || (GET_CODE (PATTERN (i3
)) == SET
1786 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1789 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1790 We used to do this EXCEPT in one case: I3 has a post-inc in an
1791 output operand. However, that exception can give rise to insns like
1793 which is a famous insn on the PDP-11 where the value of r3 used as the
1794 source was model-dependent. Avoid this sort of thing. */
1797 if (!(GET_CODE (PATTERN (i3
)) == SET
1798 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1799 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1800 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1801 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1802 /* It's not the exception. */
1805 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1806 if (REG_NOTE_KIND (link
) == REG_INC
1807 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1809 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1816 /* See if the SETs in I1 or I2 need to be kept around in the merged
1817 instruction: whenever the value set there is still needed past I3.
1818 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1820 For the SET in I1, we have two cases: If I1 and I2 independently
1821 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1822 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1823 in I1 needs to be kept around unless I1DEST dies or is set in either
1824 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1825 I1DEST. If so, we know I1 feeds into I2. */
1827 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1830 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1831 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1833 /* If the set in I2 needs to be kept around, we must make a copy of
1834 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1835 PATTERN (I2), we are only substituting for the original I1DEST, not into
1836 an already-substituted copy. This also prevents making self-referential
1837 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1840 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1841 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1845 i2pat
= copy_rtx (i2pat
);
1849 /* Substitute in the latest insn for the regs set by the earlier ones. */
1851 maxreg
= max_reg_num ();
1855 /* It is possible that the source of I2 or I1 may be performing an
1856 unneeded operation, such as a ZERO_EXTEND of something that is known
1857 to have the high part zero. Handle that case by letting subst look at
1858 the innermost one of them.
1860 Another way to do this would be to have a function that tries to
1861 simplify a single insn instead of merging two or more insns. We don't
1862 do this because of the potential of infinite loops and because
1863 of the potential extra memory required. However, doing it the way
1864 we are is a bit of a kludge and doesn't catch all cases.
1866 But only do this if -fexpensive-optimizations since it slows things down
1867 and doesn't usually win. */
1869 if (flag_expensive_optimizations
)
1871 /* Pass pc_rtx so no substitutions are done, just simplifications.
1872 The cases that we are interested in here do not involve the few
1873 cases were is_replaced is checked. */
1876 subst_low_cuid
= INSN_CUID (i1
);
1877 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1881 subst_low_cuid
= INSN_CUID (i2
);
1882 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1885 undobuf
.previous_undos
= undobuf
.undos
;
1889 /* Many machines that don't use CC0 have insns that can both perform an
1890 arithmetic operation and set the condition code. These operations will
1891 be represented as a PARALLEL with the first element of the vector
1892 being a COMPARE of an arithmetic operation with the constant zero.
1893 The second element of the vector will set some pseudo to the result
1894 of the same arithmetic operation. If we simplify the COMPARE, we won't
1895 match such a pattern and so will generate an extra insn. Here we test
1896 for this case, where both the comparison and the operation result are
1897 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1898 I2SRC. Later we will make the PARALLEL that contains I2. */
1900 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1901 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1902 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1903 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1905 #ifdef EXTRA_CC_MODES
1907 enum machine_mode compare_mode
;
1910 newpat
= PATTERN (i3
);
1911 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1915 #ifdef EXTRA_CC_MODES
1916 /* See if a COMPARE with the operand we substituted in should be done
1917 with the mode that is currently being used. If not, do the same
1918 processing we do in `subst' for a SET; namely, if the destination
1919 is used only once, try to replace it with a register of the proper
1920 mode and also replace the COMPARE. */
1921 if (undobuf
.other_insn
== 0
1922 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1923 &undobuf
.other_insn
))
1924 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1926 != GET_MODE (SET_DEST (newpat
))))
1928 unsigned int regno
= REGNO (SET_DEST (newpat
));
1929 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1931 if (regno
< FIRST_PSEUDO_REGISTER
1932 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1933 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1935 if (regno
>= FIRST_PSEUDO_REGISTER
)
1936 SUBST (regno_reg_rtx
[regno
], new_dest
);
1938 SUBST (SET_DEST (newpat
), new_dest
);
1939 SUBST (XEXP (*cc_use
, 0), new_dest
);
1940 SUBST (SET_SRC (newpat
),
1941 gen_rtx_combine (COMPARE
, compare_mode
,
1942 i2src
, const0_rtx
));
1945 undobuf
.other_insn
= 0;
1952 n_occurrences
= 0; /* `subst' counts here */
1954 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1955 need to make a unique copy of I2SRC each time we substitute it
1956 to avoid self-referential rtl. */
1958 subst_low_cuid
= INSN_CUID (i2
);
1959 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1960 ! i1_feeds_i3
&& i1dest_in_i1src
);
1961 undobuf
.previous_undos
= undobuf
.undos
;
1963 /* Record whether i2's body now appears within i3's body. */
1964 i2_is_used
= n_occurrences
;
1967 /* If we already got a failure, don't try to do more. Otherwise,
1968 try to substitute in I1 if we have it. */
1970 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1972 /* Before we can do this substitution, we must redo the test done
1973 above (see detailed comments there) that ensures that I1DEST
1974 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1976 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1984 subst_low_cuid
= INSN_CUID (i1
);
1985 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1986 undobuf
.previous_undos
= undobuf
.undos
;
1989 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1990 to count all the ways that I2SRC and I1SRC can be used. */
1991 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1992 && i2_is_used
+ added_sets_2
> 1)
1993 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1994 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1996 /* Fail if we tried to make a new register (we used to abort, but there's
1997 really no reason to). */
1998 || max_reg_num () != maxreg
1999 /* Fail if we couldn't do something and have a CLOBBER. */
2000 || GET_CODE (newpat
) == CLOBBER
2001 /* Fail if this new pattern is a MULT and we didn't have one before
2002 at the outer level. */
2003 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
2010 /* If the actions of the earlier insns must be kept
2011 in addition to substituting them into the latest one,
2012 we must make a new PARALLEL for the latest insn
2013 to hold additional the SETs. */
2015 if (added_sets_1
|| added_sets_2
)
2019 if (GET_CODE (newpat
) == PARALLEL
)
2021 rtvec old
= XVEC (newpat
, 0);
2022 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
2023 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2024 bcopy ((char *) &old
->elem
[0], (char *) XVEC (newpat
, 0)->elem
,
2025 sizeof (old
->elem
[0]) * old
->num_elem
);
2030 total_sets
= 1 + added_sets_1
+ added_sets_2
;
2031 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
2032 XVECEXP (newpat
, 0, 0) = old
;
2036 XVECEXP (newpat
, 0, --total_sets
)
2037 = (GET_CODE (PATTERN (i1
)) == PARALLEL
2038 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
2042 /* If there is no I1, use I2's body as is. We used to also not do
2043 the subst call below if I2 was substituted into I3,
2044 but that could lose a simplification. */
2046 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
2048 /* See comment where i2pat is assigned. */
2049 XVECEXP (newpat
, 0, --total_sets
)
2050 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2054 /* We come here when we are replacing a destination in I2 with the
2055 destination of I3. */
2056 validate_replacement
:
2058 /* Note which hard regs this insn has as inputs. */
2059 mark_used_regs_combine (newpat
);
2061 /* Is the result of combination a valid instruction? */
2062 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2064 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2065 the second SET's destination is a register that is unused. In that case,
2066 we just need the first SET. This can occur when simplifying a divmod
2067 insn. We *must* test for this case here because the code below that
2068 splits two independent SETs doesn't handle this case correctly when it
2069 updates the register status. Also check the case where the first
2070 SET's destination is unused. That would not cause incorrect code, but
2071 does cause an unneeded insn to remain. */
2073 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2074 && XVECLEN (newpat
, 0) == 2
2075 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2076 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2077 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2078 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2079 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2080 && asm_noperands (newpat
) < 0)
2082 newpat
= XVECEXP (newpat
, 0, 0);
2083 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2086 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2087 && XVECLEN (newpat
, 0) == 2
2088 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2089 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2090 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2091 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2092 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2093 && asm_noperands (newpat
) < 0)
2095 newpat
= XVECEXP (newpat
, 0, 1);
2096 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2099 /* If we were combining three insns and the result is a simple SET
2100 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2101 insns. There are two ways to do this. It can be split using a
2102 machine-specific method (like when you have an addition of a large
2103 constant) or by combine in the function find_split_point. */
2105 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2106 && asm_noperands (newpat
) < 0)
2108 rtx m_split
, *split
;
2109 rtx ni2dest
= i2dest
;
2111 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2112 use I2DEST as a scratch register will help. In the latter case,
2113 convert I2DEST to the mode of the source of NEWPAT if we can. */
2115 m_split
= split_insns (newpat
, i3
);
2117 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2118 inputs of NEWPAT. */
2120 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2121 possible to try that as a scratch reg. This would require adding
2122 more code to make it work though. */
2124 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2126 /* If I2DEST is a hard register or the only use of a pseudo,
2127 we can change its mode. */
2128 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2129 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2130 && GET_CODE (i2dest
) == REG
2131 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2132 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2133 && ! REG_USERVAR_P (i2dest
))))
2134 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2137 m_split
= split_insns (gen_rtx_PARALLEL
2139 gen_rtvec (2, newpat
,
2140 gen_rtx_CLOBBER (VOIDmode
,
2145 if (m_split
&& GET_CODE (m_split
) != SEQUENCE
)
2147 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2148 if (insn_code_number
>= 0)
2151 else if (m_split
&& GET_CODE (m_split
) == SEQUENCE
2152 && XVECLEN (m_split
, 0) == 2
2153 && (next_real_insn (i2
) == i3
2154 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
2158 rtx newi3pat
= PATTERN (XVECEXP (m_split
, 0, 1));
2159 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
2161 i3set
= single_set (XVECEXP (m_split
, 0, 1));
2162 i2set
= single_set (XVECEXP (m_split
, 0, 0));
2164 /* In case we changed the mode of I2DEST, replace it in the
2165 pseudo-register table here. We can't do it above in case this
2166 code doesn't get executed and we do a split the other way. */
2168 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2169 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2171 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2173 /* If I2 or I3 has multiple SETs, we won't know how to track
2174 register status, so don't use these insns. If I2's destination
2175 is used between I2 and I3, we also can't use these insns. */
2177 if (i2_code_number
>= 0 && i2set
&& i3set
2178 && (next_real_insn (i2
) == i3
2179 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2180 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2182 if (insn_code_number
>= 0)
2185 /* It is possible that both insns now set the destination of I3.
2186 If so, we must show an extra use of it. */
2188 if (insn_code_number
>= 0)
2190 rtx new_i3_dest
= SET_DEST (i3set
);
2191 rtx new_i2_dest
= SET_DEST (i2set
);
2193 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2194 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2195 || GET_CODE (new_i3_dest
) == SUBREG
)
2196 new_i3_dest
= XEXP (new_i3_dest
, 0);
2198 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2199 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2200 || GET_CODE (new_i2_dest
) == SUBREG
)
2201 new_i2_dest
= XEXP (new_i2_dest
, 0);
2203 if (GET_CODE (new_i3_dest
) == REG
2204 && GET_CODE (new_i2_dest
) == REG
2205 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2206 REG_N_SETS (REGNO (new_i2_dest
))++;
2210 /* If we can split it and use I2DEST, go ahead and see if that
2211 helps things be recognized. Verify that none of the registers
2212 are set between I2 and I3. */
2213 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2215 && GET_CODE (i2dest
) == REG
2217 /* We need I2DEST in the proper mode. If it is a hard register
2218 or the only use of a pseudo, we can change its mode. */
2219 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2220 || GET_MODE (*split
) == VOIDmode
2221 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2222 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2223 && ! REG_USERVAR_P (i2dest
)))
2224 && (next_real_insn (i2
) == i3
2225 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2226 /* We can't overwrite I2DEST if its value is still used by
2228 && ! reg_referenced_p (i2dest
, newpat
))
2230 rtx newdest
= i2dest
;
2231 enum rtx_code split_code
= GET_CODE (*split
);
2232 enum machine_mode split_mode
= GET_MODE (*split
);
2234 /* Get NEWDEST as a register in the proper mode. We have already
2235 validated that we can do this. */
2236 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2238 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2240 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2241 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2244 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2245 an ASHIFT. This can occur if it was inside a PLUS and hence
2246 appeared to be a memory address. This is a kludge. */
2247 if (split_code
== MULT
2248 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2249 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2251 SUBST (*split
, gen_rtx_combine (ASHIFT
, split_mode
,
2252 XEXP (*split
, 0), GEN_INT (i
)));
2253 /* Update split_code because we may not have a multiply
2255 split_code
= GET_CODE (*split
);
2258 #ifdef INSN_SCHEDULING
2259 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2260 be written as a ZERO_EXTEND. */
2261 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2262 SUBST (*split
, gen_rtx_combine (ZERO_EXTEND
, split_mode
,
2266 newi2pat
= gen_rtx_combine (SET
, VOIDmode
, newdest
, *split
);
2267 SUBST (*split
, newdest
);
2268 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2270 /* If the split point was a MULT and we didn't have one before,
2271 don't use one now. */
2272 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2273 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2277 /* Check for a case where we loaded from memory in a narrow mode and
2278 then sign extended it, but we need both registers. In that case,
2279 we have a PARALLEL with both loads from the same memory location.
2280 We can split this into a load from memory followed by a register-register
2281 copy. This saves at least one insn, more if register allocation can
2284 We cannot do this if the destination of the second assignment is
2285 a register that we have already assumed is zero-extended. Similarly
2286 for a SUBREG of such a register. */
2288 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2289 && GET_CODE (newpat
) == PARALLEL
2290 && XVECLEN (newpat
, 0) == 2
2291 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2292 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2293 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2294 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2295 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2296 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2298 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2299 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2300 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2301 (GET_CODE (temp
) == REG
2302 && reg_nonzero_bits
[REGNO (temp
)] != 0
2303 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2304 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2305 && (reg_nonzero_bits
[REGNO (temp
)]
2306 != GET_MODE_MASK (word_mode
))))
2307 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2308 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2309 (GET_CODE (temp
) == REG
2310 && reg_nonzero_bits
[REGNO (temp
)] != 0
2311 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2312 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2313 && (reg_nonzero_bits
[REGNO (temp
)]
2314 != GET_MODE_MASK (word_mode
)))))
2315 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2316 SET_SRC (XVECEXP (newpat
, 0, 1)))
2317 && ! find_reg_note (i3
, REG_UNUSED
,
2318 SET_DEST (XVECEXP (newpat
, 0, 0))))
2322 newi2pat
= XVECEXP (newpat
, 0, 0);
2323 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2324 newpat
= XVECEXP (newpat
, 0, 1);
2325 SUBST (SET_SRC (newpat
),
2326 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2327 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2329 if (i2_code_number
>= 0)
2330 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2332 if (insn_code_number
>= 0)
2337 /* If we will be able to accept this, we have made a change to the
2338 destination of I3. This can invalidate a LOG_LINKS pointing
2339 to I3. No other part of combine.c makes such a transformation.
2341 The new I3 will have a destination that was previously the
2342 destination of I1 or I2 and which was used in i2 or I3. Call
2343 distribute_links to make a LOG_LINK from the next use of
2344 that destination. */
2346 PATTERN (i3
) = newpat
;
2347 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2349 /* I3 now uses what used to be its destination and which is
2350 now I2's destination. That means we need a LOG_LINK from
2351 I3 to I2. But we used to have one, so we still will.
2353 However, some later insn might be using I2's dest and have
2354 a LOG_LINK pointing at I3. We must remove this link.
2355 The simplest way to remove the link is to point it at I1,
2356 which we know will be a NOTE. */
2358 for (insn
= NEXT_INSN (i3
);
2359 insn
&& (this_basic_block
== n_basic_blocks
- 1
2360 || insn
!= BLOCK_HEAD (this_basic_block
+ 1));
2361 insn
= NEXT_INSN (insn
))
2363 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2365 for (link
= LOG_LINKS (insn
); link
;
2366 link
= XEXP (link
, 1))
2367 if (XEXP (link
, 0) == i3
)
2368 XEXP (link
, 0) = i1
;
2376 /* Similarly, check for a case where we have a PARALLEL of two independent
2377 SETs but we started with three insns. In this case, we can do the sets
2378 as two separate insns. This case occurs when some SET allows two
2379 other insns to combine, but the destination of that SET is still live. */
2381 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2382 && GET_CODE (newpat
) == PARALLEL
2383 && XVECLEN (newpat
, 0) == 2
2384 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2385 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2386 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2387 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2388 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2389 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2390 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2392 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2393 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2394 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2395 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2396 XVECEXP (newpat
, 0, 0))
2397 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2398 XVECEXP (newpat
, 0, 1))
2399 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2400 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2402 /* Normally, it doesn't matter which of the two is done first,
2403 but it does if one references cc0. In that case, it has to
2406 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2408 newi2pat
= XVECEXP (newpat
, 0, 0);
2409 newpat
= XVECEXP (newpat
, 0, 1);
2414 newi2pat
= XVECEXP (newpat
, 0, 1);
2415 newpat
= XVECEXP (newpat
, 0, 0);
2418 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2420 if (i2_code_number
>= 0)
2421 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2424 /* If it still isn't recognized, fail and change things back the way they
2426 if ((insn_code_number
< 0
2427 /* Is the result a reasonable ASM_OPERANDS? */
2428 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2434 /* If we had to change another insn, make sure it is valid also. */
2435 if (undobuf
.other_insn
)
2437 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2438 rtx new_other_notes
;
2441 CLEAR_HARD_REG_SET (newpat_used_regs
);
2443 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2446 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2452 PATTERN (undobuf
.other_insn
) = other_pat
;
2454 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2455 are still valid. Then add any non-duplicate notes added by
2456 recog_for_combine. */
2457 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2459 next
= XEXP (note
, 1);
2461 if (REG_NOTE_KIND (note
) == REG_UNUSED
2462 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2464 if (GET_CODE (XEXP (note
, 0)) == REG
)
2465 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2467 remove_note (undobuf
.other_insn
, note
);
2471 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2472 if (GET_CODE (XEXP (note
, 0)) == REG
)
2473 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2475 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2476 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2479 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2480 they are adjacent to each other or not. */
2482 rtx p
= prev_nonnote_insn (i3
);
2483 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2484 && sets_cc0_p (newi2pat
))
2492 /* We now know that we can do this combination. Merge the insns and
2493 update the status of registers and LOG_LINKS. */
2496 rtx i3notes
, i2notes
, i1notes
= 0;
2497 rtx i3links
, i2links
, i1links
= 0;
2500 /* Compute which registers we expect to eliminate. newi2pat may be setting
2501 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2502 same as i3dest, in which case newi2pat may be setting i1dest. */
2503 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2504 || i2dest_in_i2src
|| i2dest_in_i1src
2506 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2507 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2510 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2512 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2513 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2515 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2517 /* Ensure that we do not have something that should not be shared but
2518 occurs multiple times in the new insns. Check this by first
2519 resetting all the `used' flags and then copying anything is shared. */
2521 reset_used_flags (i3notes
);
2522 reset_used_flags (i2notes
);
2523 reset_used_flags (i1notes
);
2524 reset_used_flags (newpat
);
2525 reset_used_flags (newi2pat
);
2526 if (undobuf
.other_insn
)
2527 reset_used_flags (PATTERN (undobuf
.other_insn
));
2529 i3notes
= copy_rtx_if_shared (i3notes
);
2530 i2notes
= copy_rtx_if_shared (i2notes
);
2531 i1notes
= copy_rtx_if_shared (i1notes
);
2532 newpat
= copy_rtx_if_shared (newpat
);
2533 newi2pat
= copy_rtx_if_shared (newi2pat
);
2534 if (undobuf
.other_insn
)
2535 reset_used_flags (PATTERN (undobuf
.other_insn
));
2537 INSN_CODE (i3
) = insn_code_number
;
2538 PATTERN (i3
) = newpat
;
2539 if (undobuf
.other_insn
)
2540 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2542 /* We had one special case above where I2 had more than one set and
2543 we replaced a destination of one of those sets with the destination
2544 of I3. In that case, we have to update LOG_LINKS of insns later
2545 in this basic block. Note that this (expensive) case is rare.
2547 Also, in this case, we must pretend that all REG_NOTEs for I2
2548 actually came from I3, so that REG_UNUSED notes from I2 will be
2549 properly handled. */
2551 if (i3_subst_into_i2
)
2553 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2554 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2555 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2556 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2557 && ! find_reg_note (i2
, REG_UNUSED
,
2558 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2559 for (temp
= NEXT_INSN (i2
);
2560 temp
&& (this_basic_block
== n_basic_blocks
- 1
2561 || BLOCK_HEAD (this_basic_block
) != temp
);
2562 temp
= NEXT_INSN (temp
))
2563 if (temp
!= i3
&& INSN_P (temp
))
2564 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2565 if (XEXP (link
, 0) == i2
)
2566 XEXP (link
, 0) = i3
;
2571 while (XEXP (link
, 1))
2572 link
= XEXP (link
, 1);
2573 XEXP (link
, 1) = i2notes
;
2587 INSN_CODE (i2
) = i2_code_number
;
2588 PATTERN (i2
) = newi2pat
;
2592 PUT_CODE (i2
, NOTE
);
2593 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2594 NOTE_SOURCE_FILE (i2
) = 0;
2601 PUT_CODE (i1
, NOTE
);
2602 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2603 NOTE_SOURCE_FILE (i1
) = 0;
2606 /* Get death notes for everything that is now used in either I3 or
2607 I2 and used to die in a previous insn. If we built two new
2608 patterns, move from I1 to I2 then I2 to I3 so that we get the
2609 proper movement on registers that I2 modifies. */
2613 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2614 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2617 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2620 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2622 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2625 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2628 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2631 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2634 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2635 know these are REG_UNUSED and want them to go to the desired insn,
2636 so we always pass it as i3. We have not counted the notes in
2637 reg_n_deaths yet, so we need to do so now. */
2639 if (newi2pat
&& new_i2_notes
)
2641 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2642 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2643 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2645 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2650 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2651 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2652 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2654 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2657 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2658 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2659 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2660 in that case, it might delete I2. Similarly for I2 and I1.
2661 Show an additional death due to the REG_DEAD note we make here. If
2662 we discard it in distribute_notes, we will decrement it again. */
2666 if (GET_CODE (i3dest_killed
) == REG
)
2667 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2669 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2670 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2672 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2674 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2676 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2680 if (i2dest_in_i2src
)
2682 if (GET_CODE (i2dest
) == REG
)
2683 REG_N_DEATHS (REGNO (i2dest
))++;
2685 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2686 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2687 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2689 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2690 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2691 NULL_RTX
, NULL_RTX
);
2694 if (i1dest_in_i1src
)
2696 if (GET_CODE (i1dest
) == REG
)
2697 REG_N_DEATHS (REGNO (i1dest
))++;
2699 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2700 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2701 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2703 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2704 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2705 NULL_RTX
, NULL_RTX
);
2708 distribute_links (i3links
);
2709 distribute_links (i2links
);
2710 distribute_links (i1links
);
2712 if (GET_CODE (i2dest
) == REG
)
2715 rtx i2_insn
= 0, i2_val
= 0, set
;
2717 /* The insn that used to set this register doesn't exist, and
2718 this life of the register may not exist either. See if one of
2719 I3's links points to an insn that sets I2DEST. If it does,
2720 that is now the last known value for I2DEST. If we don't update
2721 this and I2 set the register to a value that depended on its old
2722 contents, we will get confused. If this insn is used, thing
2723 will be set correctly in combine_instructions. */
2725 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2726 if ((set
= single_set (XEXP (link
, 0))) != 0
2727 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2728 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2730 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2732 /* If the reg formerly set in I2 died only once and that was in I3,
2733 zero its use count so it won't make `reload' do any work. */
2735 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2736 && ! i2dest_in_i2src
)
2738 regno
= REGNO (i2dest
);
2739 REG_N_SETS (regno
)--;
2743 if (i1
&& GET_CODE (i1dest
) == REG
)
2746 rtx i1_insn
= 0, i1_val
= 0, set
;
2748 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2749 if ((set
= single_set (XEXP (link
, 0))) != 0
2750 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2751 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2753 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2755 regno
= REGNO (i1dest
);
2756 if (! added_sets_1
&& ! i1dest_in_i1src
)
2757 REG_N_SETS (regno
)--;
2760 /* Update reg_nonzero_bits et al for any changes that may have been made
2761 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2762 important. Because newi2pat can affect nonzero_bits of newpat */
2764 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2765 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2767 /* Set new_direct_jump_p if a new return or simple jump instruction
2770 If I3 is now an unconditional jump, ensure that it has a
2771 BARRIER following it since it may have initially been a
2772 conditional jump. It may also be the last nonnote insn. */
2774 if (GET_CODE (newpat
) == RETURN
|| any_uncondjump_p (i3
))
2776 *new_direct_jump_p
= 1;
2778 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2779 || GET_CODE (temp
) != BARRIER
)
2780 emit_barrier_after (i3
);
2784 combine_successes
++;
2787 /* Clear this here, so that subsequent get_last_value calls are not
2789 subst_prev_insn
= NULL_RTX
;
2791 if (added_links_insn
2792 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2793 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2794 return added_links_insn
;
2796 return newi2pat
? i2
: i3
;
2799 /* Undo all the modifications recorded in undobuf. */
2804 struct undo
*undo
, *next
;
2806 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2810 *undo
->where
.i
= undo
->old_contents
.i
;
2812 *undo
->where
.r
= undo
->old_contents
.r
;
2814 undo
->next
= undobuf
.frees
;
2815 undobuf
.frees
= undo
;
2818 undobuf
.undos
= undobuf
.previous_undos
= 0;
2820 /* Clear this here, so that subsequent get_last_value calls are not
2822 subst_prev_insn
= NULL_RTX
;
2825 /* We've committed to accepting the changes we made. Move all
2826 of the undos to the free list. */
2831 struct undo
*undo
, *next
;
2833 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2836 undo
->next
= undobuf
.frees
;
2837 undobuf
.frees
= undo
;
2839 undobuf
.undos
= undobuf
.previous_undos
= 0;
2843 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2844 where we have an arithmetic expression and return that point. LOC will
2847 try_combine will call this function to see if an insn can be split into
2851 find_split_point (loc
, insn
)
2856 enum rtx_code code
= GET_CODE (x
);
2858 unsigned HOST_WIDE_INT len
= 0;
2859 HOST_WIDE_INT pos
= 0;
2861 rtx inner
= NULL_RTX
;
2863 /* First special-case some codes. */
2867 #ifdef INSN_SCHEDULING
2868 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2870 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2873 return find_split_point (&SUBREG_REG (x
), insn
);
2877 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2878 using LO_SUM and HIGH. */
2879 if (GET_CODE (XEXP (x
, 0)) == CONST
2880 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2883 gen_rtx_combine (LO_SUM
, Pmode
,
2884 gen_rtx_combine (HIGH
, Pmode
, XEXP (x
, 0)),
2886 return &XEXP (XEXP (x
, 0), 0);
2890 /* If we have a PLUS whose second operand is a constant and the
2891 address is not valid, perhaps will can split it up using
2892 the machine-specific way to split large constants. We use
2893 the first pseudo-reg (one of the virtual regs) as a placeholder;
2894 it will not remain in the result. */
2895 if (GET_CODE (XEXP (x
, 0)) == PLUS
2896 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2897 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2899 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2900 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2903 /* This should have produced two insns, each of which sets our
2904 placeholder. If the source of the second is a valid address,
2905 we can make put both sources together and make a split point
2908 if (seq
&& XVECLEN (seq
, 0) == 2
2909 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
2910 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
2911 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
2912 && ! reg_mentioned_p (reg
,
2913 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
2914 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
2915 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
2916 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
2917 && memory_address_p (GET_MODE (x
),
2918 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
2920 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
2921 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
2923 /* Replace the placeholder in SRC2 with SRC1. If we can
2924 find where in SRC2 it was placed, that can become our
2925 split point and we can replace this address with SRC2.
2926 Just try two obvious places. */
2928 src2
= replace_rtx (src2
, reg
, src1
);
2930 if (XEXP (src2
, 0) == src1
)
2931 split
= &XEXP (src2
, 0);
2932 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2933 && XEXP (XEXP (src2
, 0), 0) == src1
)
2934 split
= &XEXP (XEXP (src2
, 0), 0);
2938 SUBST (XEXP (x
, 0), src2
);
2943 /* If that didn't work, perhaps the first operand is complex and
2944 needs to be computed separately, so make a split point there.
2945 This will occur on machines that just support REG + CONST
2946 and have a constant moved through some previous computation. */
2948 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2949 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2950 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2952 return &XEXP (XEXP (x
, 0), 0);
2958 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2959 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2960 we need to put the operand into a register. So split at that
2963 if (SET_DEST (x
) == cc0_rtx
2964 && GET_CODE (SET_SRC (x
)) != COMPARE
2965 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2966 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2967 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2968 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2969 return &SET_SRC (x
);
2972 /* See if we can split SET_SRC as it stands. */
2973 split
= find_split_point (&SET_SRC (x
), insn
);
2974 if (split
&& split
!= &SET_SRC (x
))
2977 /* See if we can split SET_DEST as it stands. */
2978 split
= find_split_point (&SET_DEST (x
), insn
);
2979 if (split
&& split
!= &SET_DEST (x
))
2982 /* See if this is a bitfield assignment with everything constant. If
2983 so, this is an IOR of an AND, so split it into that. */
2984 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2985 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2986 <= HOST_BITS_PER_WIDE_INT
)
2987 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2988 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2989 && GET_CODE (SET_SRC (x
)) == CONST_INT
2990 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2991 + INTVAL (XEXP (SET_DEST (x
), 2)))
2992 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2993 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2995 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2996 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
2997 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
2998 rtx dest
= XEXP (SET_DEST (x
), 0);
2999 enum machine_mode mode
= GET_MODE (dest
);
3000 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3002 if (BITS_BIG_ENDIAN
)
3003 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3007 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3010 gen_binary (IOR
, mode
,
3011 gen_binary (AND
, mode
, dest
,
3012 GEN_INT (~(mask
<< pos
)
3013 & GET_MODE_MASK (mode
))),
3014 GEN_INT (src
<< pos
)));
3016 SUBST (SET_DEST (x
), dest
);
3018 split
= find_split_point (&SET_SRC (x
), insn
);
3019 if (split
&& split
!= &SET_SRC (x
))
3023 /* Otherwise, see if this is an operation that we can split into two.
3024 If so, try to split that. */
3025 code
= GET_CODE (SET_SRC (x
));
3030 /* If we are AND'ing with a large constant that is only a single
3031 bit and the result is only being used in a context where we
3032 need to know if it is zero or non-zero, replace it with a bit
3033 extraction. This will avoid the large constant, which might
3034 have taken more than one insn to make. If the constant were
3035 not a valid argument to the AND but took only one insn to make,
3036 this is no worse, but if it took more than one insn, it will
3039 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3040 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3041 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3042 && GET_CODE (SET_DEST (x
)) == REG
3043 && (split
= find_single_use (SET_DEST (x
), insn
, NULL_PTR
)) != 0
3044 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3045 && XEXP (*split
, 0) == SET_DEST (x
)
3046 && XEXP (*split
, 1) == const0_rtx
)
3048 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3049 XEXP (SET_SRC (x
), 0),
3050 pos
, NULL_RTX
, 1, 1, 0, 0);
3051 if (extraction
!= 0)
3053 SUBST (SET_SRC (x
), extraction
);
3054 return find_split_point (loc
, insn
);
3060 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3061 is known to be on, this can be converted into a NEG of a shift. */
3062 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3063 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3064 && 1 <= (pos
= exact_log2
3065 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3066 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3068 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3071 gen_rtx_combine (NEG
, mode
,
3072 gen_rtx_combine (LSHIFTRT
, mode
,
3073 XEXP (SET_SRC (x
), 0),
3076 split
= find_split_point (&SET_SRC (x
), insn
);
3077 if (split
&& split
!= &SET_SRC (x
))
3083 inner
= XEXP (SET_SRC (x
), 0);
3085 /* We can't optimize if either mode is a partial integer
3086 mode as we don't know how many bits are significant
3088 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3089 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3093 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3099 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3100 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3102 inner
= XEXP (SET_SRC (x
), 0);
3103 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3104 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3106 if (BITS_BIG_ENDIAN
)
3107 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3108 unsignedp
= (code
== ZERO_EXTRACT
);
3116 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3118 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3120 /* For unsigned, we have a choice of a shift followed by an
3121 AND or two shifts. Use two shifts for field sizes where the
3122 constant might be too large. We assume here that we can
3123 always at least get 8-bit constants in an AND insn, which is
3124 true for every current RISC. */
3126 if (unsignedp
&& len
<= 8)
3131 gen_rtx_combine (LSHIFTRT
, mode
,
3132 gen_lowpart_for_combine (mode
, inner
),
3134 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3136 split
= find_split_point (&SET_SRC (x
), insn
);
3137 if (split
&& split
!= &SET_SRC (x
))
3144 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3145 gen_rtx_combine (ASHIFT
, mode
,
3146 gen_lowpart_for_combine (mode
, inner
),
3147 GEN_INT (GET_MODE_BITSIZE (mode
)
3149 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3151 split
= find_split_point (&SET_SRC (x
), insn
);
3152 if (split
&& split
!= &SET_SRC (x
))
3157 /* See if this is a simple operation with a constant as the second
3158 operand. It might be that this constant is out of range and hence
3159 could be used as a split point. */
3160 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3161 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3162 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3163 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3164 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3165 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3166 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3168 return &XEXP (SET_SRC (x
), 1);
3170 /* Finally, see if this is a simple operation with its first operand
3171 not in a register. The operation might require this operand in a
3172 register, so return it as a split point. We can always do this
3173 because if the first operand were another operation, we would have
3174 already found it as a split point. */
3175 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3176 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3177 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3178 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3179 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3180 return &XEXP (SET_SRC (x
), 0);
3186 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3187 it is better to write this as (not (ior A B)) so we can split it.
3188 Similarly for IOR. */
3189 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3192 gen_rtx_combine (NOT
, GET_MODE (x
),
3193 gen_rtx_combine (code
== IOR
? AND
: IOR
,
3195 XEXP (XEXP (x
, 0), 0),
3196 XEXP (XEXP (x
, 1), 0))));
3197 return find_split_point (loc
, insn
);
3200 /* Many RISC machines have a large set of logical insns. If the
3201 second operand is a NOT, put it first so we will try to split the
3202 other operand first. */
3203 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3205 rtx tem
= XEXP (x
, 0);
3206 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3207 SUBST (XEXP (x
, 1), tem
);
3215 /* Otherwise, select our actions depending on our rtx class. */
3216 switch (GET_RTX_CLASS (code
))
3218 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3220 split
= find_split_point (&XEXP (x
, 2), insn
);
3223 /* ... fall through ... */
3227 split
= find_split_point (&XEXP (x
, 1), insn
);
3230 /* ... fall through ... */
3232 /* Some machines have (and (shift ...) ...) insns. If X is not
3233 an AND, but XEXP (X, 0) is, use it as our split point. */
3234 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3235 return &XEXP (x
, 0);
3237 split
= find_split_point (&XEXP (x
, 0), insn
);
3243 /* Otherwise, we don't have a split point. */
3247 /* Throughout X, replace FROM with TO, and return the result.
3248 The result is TO if X is FROM;
3249 otherwise the result is X, but its contents may have been modified.
3250 If they were modified, a record was made in undobuf so that
3251 undo_all will (among other things) return X to its original state.
3253 If the number of changes necessary is too much to record to undo,
3254 the excess changes are not made, so the result is invalid.
3255 The changes already made can still be undone.
3256 undobuf.num_undo is incremented for such changes, so by testing that
3257 the caller can tell whether the result is valid.
3259 `n_occurrences' is incremented each time FROM is replaced.
3261 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3263 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3264 by copying if `n_occurrences' is non-zero. */
3267 subst (x
, from
, to
, in_dest
, unique_copy
)
3268 register rtx x
, from
, to
;
3272 register enum rtx_code code
= GET_CODE (x
);
3273 enum machine_mode op0_mode
= VOIDmode
;
3274 register const char *fmt
;
3275 register int len
, i
;
3278 /* Two expressions are equal if they are identical copies of a shared
3279 RTX or if they are both registers with the same register number
3282 #define COMBINE_RTX_EQUAL_P(X,Y) \
3284 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3285 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3287 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3290 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3293 /* If X and FROM are the same register but different modes, they will
3294 not have been seen as equal above. However, flow.c will make a
3295 LOG_LINKS entry for that case. If we do nothing, we will try to
3296 rerecognize our original insn and, when it succeeds, we will
3297 delete the feeding insn, which is incorrect.
3299 So force this insn not to match in this (rare) case. */
3300 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3301 && REGNO (x
) == REGNO (from
))
3302 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3304 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3305 of which may contain things that can be combined. */
3306 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3309 /* It is possible to have a subexpression appear twice in the insn.
3310 Suppose that FROM is a register that appears within TO.
3311 Then, after that subexpression has been scanned once by `subst',
3312 the second time it is scanned, TO may be found. If we were
3313 to scan TO here, we would find FROM within it and create a
3314 self-referent rtl structure which is completely wrong. */
3315 if (COMBINE_RTX_EQUAL_P (x
, to
))
3318 /* Parallel asm_operands need special attention because all of the
3319 inputs are shared across the arms. Furthermore, unsharing the
3320 rtl results in recognition failures. Failure to handle this case
3321 specially can result in circular rtl.
3323 Solve this by doing a normal pass across the first entry of the
3324 parallel, and only processing the SET_DESTs of the subsequent
3327 if (code
== PARALLEL
3328 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3329 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3331 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3333 /* If this substitution failed, this whole thing fails. */
3334 if (GET_CODE (new) == CLOBBER
3335 && XEXP (new, 0) == const0_rtx
)
3338 SUBST (XVECEXP (x
, 0, 0), new);
3340 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3342 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3344 if (GET_CODE (dest
) != REG
3345 && GET_CODE (dest
) != CC0
3346 && GET_CODE (dest
) != PC
)
3348 new = subst (dest
, from
, to
, 0, unique_copy
);
3350 /* If this substitution failed, this whole thing fails. */
3351 if (GET_CODE (new) == CLOBBER
3352 && XEXP (new, 0) == const0_rtx
)
3355 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3361 len
= GET_RTX_LENGTH (code
);
3362 fmt
= GET_RTX_FORMAT (code
);
3364 /* We don't need to process a SET_DEST that is a register, CC0,
3365 or PC, so set up to skip this common case. All other cases
3366 where we want to suppress replacing something inside a
3367 SET_SRC are handled via the IN_DEST operand. */
3369 && (GET_CODE (SET_DEST (x
)) == REG
3370 || GET_CODE (SET_DEST (x
)) == CC0
3371 || GET_CODE (SET_DEST (x
)) == PC
))
3374 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3377 op0_mode
= GET_MODE (XEXP (x
, 0));
3379 for (i
= 0; i
< len
; i
++)
3384 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3386 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3388 new = (unique_copy
&& n_occurrences
3389 ? copy_rtx (to
) : to
);
3394 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3397 /* If this substitution failed, this whole thing
3399 if (GET_CODE (new) == CLOBBER
3400 && XEXP (new, 0) == const0_rtx
)
3404 SUBST (XVECEXP (x
, i
, j
), new);
3407 else if (fmt
[i
] == 'e')
3409 if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3411 /* In general, don't install a subreg involving two
3412 modes not tieable. It can worsen register
3413 allocation, and can even make invalid reload
3414 insns, since the reg inside may need to be copied
3415 from in the outside mode, and that may be invalid
3416 if it is an fp reg copied in integer mode.
3418 We allow two exceptions to this: It is valid if
3419 it is inside another SUBREG and the mode of that
3420 SUBREG and the mode of the inside of TO is
3421 tieable and it is valid if X is a SET that copies
3424 if (GET_CODE (to
) == SUBREG
3425 && ! MODES_TIEABLE_P (GET_MODE (to
),
3426 GET_MODE (SUBREG_REG (to
)))
3427 && ! (code
== SUBREG
3428 && MODES_TIEABLE_P (GET_MODE (x
),
3429 GET_MODE (SUBREG_REG (to
))))
3431 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3434 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3436 #ifdef CLASS_CANNOT_CHANGE_MODE
3438 && GET_CODE (to
) == REG
3439 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3440 && (TEST_HARD_REG_BIT
3441 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
3443 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to
),
3445 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3448 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3452 /* If we are in a SET_DEST, suppress most cases unless we
3453 have gone inside a MEM, in which case we want to
3454 simplify the address. We assume here that things that
3455 are actually part of the destination have their inner
3456 parts in the first expression. This is true for SUBREG,
3457 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3458 things aside from REG and MEM that should appear in a
3460 new = subst (XEXP (x
, i
), from
, to
,
3462 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3463 || code
== ZERO_EXTRACT
))
3465 && i
== 0), unique_copy
);
3467 /* If we found that we will have to reject this combination,
3468 indicate that by returning the CLOBBER ourselves, rather than
3469 an expression containing it. This will speed things up as
3470 well as prevent accidents where two CLOBBERs are considered
3471 to be equal, thus producing an incorrect simplification. */
3473 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3476 SUBST (XEXP (x
, i
), new);
3481 /* Try to simplify X. If the simplification changed the code, it is likely
3482 that further simplification will help, so loop, but limit the number
3483 of repetitions that will be performed. */
3485 for (i
= 0; i
< 4; i
++)
3487 /* If X is sufficiently simple, don't bother trying to do anything
3489 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3490 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3492 if (GET_CODE (x
) == code
)
3495 code
= GET_CODE (x
);
3497 /* We no longer know the original mode of operand 0 since we
3498 have changed the form of X) */
3499 op0_mode
= VOIDmode
;
3505 /* Simplify X, a piece of RTL. We just operate on the expression at the
3506 outer level; call `subst' to simplify recursively. Return the new
3509 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3510 will be the iteration even if an expression with a code different from
3511 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3514 combine_simplify_rtx (x
, op0_mode
, last
, in_dest
)
3516 enum machine_mode op0_mode
;
3520 enum rtx_code code
= GET_CODE (x
);
3521 enum machine_mode mode
= GET_MODE (x
);
3526 /* If this is a commutative operation, put a constant last and a complex
3527 expression first. We don't need to do this for comparisons here. */
3528 if (GET_RTX_CLASS (code
) == 'c'
3529 && ((CONSTANT_P (XEXP (x
, 0)) && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3530 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == 'o'
3531 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')
3532 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3533 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == 'o'
3534 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')))
3537 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3538 SUBST (XEXP (x
, 1), temp
);
3541 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3542 sign extension of a PLUS with a constant, reverse the order of the sign
3543 extension and the addition. Note that this not the same as the original
3544 code, but overflow is undefined for signed values. Also note that the
3545 PLUS will have been partially moved "inside" the sign-extension, so that
3546 the first operand of X will really look like:
3547 (ashiftrt (plus (ashift A C4) C5) C4).
3549 (plus (ashiftrt (ashift A C4) C2) C4)
3550 and replace the first operand of X with that expression. Later parts
3551 of this function may simplify the expression further.
3553 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3554 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3555 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3557 We do this to simplify address expressions. */
3559 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3560 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3561 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3562 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3563 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3564 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3565 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3566 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3567 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3568 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3569 XEXP (XEXP (x
, 0), 1))) != 0)
3572 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3573 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3574 INTVAL (XEXP (XEXP (x
, 0), 1)));
3576 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3577 INTVAL (XEXP (XEXP (x
, 0), 1)));
3579 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3582 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3583 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3584 things. Check for cases where both arms are testing the same
3587 Don't do anything if all operands are very simple. */
3589 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3590 || GET_RTX_CLASS (code
) == '<')
3591 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3592 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3593 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3595 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3596 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3597 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3599 || (GET_RTX_CLASS (code
) == '1'
3600 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3601 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3602 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3605 rtx cond
, true, false;
3607 cond
= if_then_else_cond (x
, &true, &false);
3609 /* If everything is a comparison, what we have is highly unlikely
3610 to be simpler, so don't use it. */
3611 && ! (GET_RTX_CLASS (code
) == '<'
3612 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3613 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3615 rtx cop1
= const0_rtx
;
3616 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3618 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3621 /* Simplify the alternative arms; this may collapse the true and
3622 false arms to store-flag values. */
3623 true = subst (true, pc_rtx
, pc_rtx
, 0, 0);
3624 false = subst (false, pc_rtx
, pc_rtx
, 0, 0);
3626 /* If true and false are not general_operands, an if_then_else
3627 is unlikely to be simpler. */
3628 if (general_operand (true, VOIDmode
)
3629 && general_operand (false, VOIDmode
))
3631 /* Restarting if we generate a store-flag expression will cause
3632 us to loop. Just drop through in this case. */
3634 /* If the result values are STORE_FLAG_VALUE and zero, we can
3635 just make the comparison operation. */
3636 if (true == const_true_rtx
&& false == const0_rtx
)
3637 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3638 else if (true == const0_rtx
&& false == const_true_rtx
)
3639 x
= gen_binary (reverse_condition (cond_code
),
3642 /* Likewise, we can make the negate of a comparison operation
3643 if the result values are - STORE_FLAG_VALUE and zero. */
3644 else if (GET_CODE (true) == CONST_INT
3645 && INTVAL (true) == - STORE_FLAG_VALUE
3646 && false == const0_rtx
)
3647 x
= gen_unary (NEG
, mode
, mode
,
3648 gen_binary (cond_code
, mode
, cond
, cop1
));
3649 else if (GET_CODE (false) == CONST_INT
3650 && INTVAL (false) == - STORE_FLAG_VALUE
3651 && true == const0_rtx
)
3652 x
= gen_unary (NEG
, mode
, mode
,
3653 gen_binary (reverse_condition (cond_code
),
3656 return gen_rtx_IF_THEN_ELSE (mode
,
3657 gen_binary (cond_code
, VOIDmode
,
3661 code
= GET_CODE (x
);
3662 op0_mode
= VOIDmode
;
3667 /* Try to fold this expression in case we have constants that weren't
3670 switch (GET_RTX_CLASS (code
))
3673 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3677 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3678 if (cmp_mode
== VOIDmode
)
3680 cmp_mode
= GET_MODE (XEXP (x
, 1));
3681 if (cmp_mode
== VOIDmode
)
3682 cmp_mode
= op0_mode
;
3684 temp
= simplify_relational_operation (code
, cmp_mode
,
3685 XEXP (x
, 0), XEXP (x
, 1));
3687 #ifdef FLOAT_STORE_FLAG_VALUE
3688 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3690 if (temp
== const0_rtx
)
3691 temp
= CONST0_RTX (mode
);
3693 temp
= immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode
), mode
);
3699 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3703 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3704 XEXP (x
, 1), XEXP (x
, 2));
3709 x
= temp
, code
= GET_CODE (temp
);
3711 /* First see if we can apply the inverse distributive law. */
3712 if (code
== PLUS
|| code
== MINUS
3713 || code
== AND
|| code
== IOR
|| code
== XOR
)
3715 x
= apply_distributive_law (x
);
3716 code
= GET_CODE (x
);
3719 /* If CODE is an associative operation not otherwise handled, see if we
3720 can associate some operands. This can win if they are constants or
3721 if they are logically related (i.e. (a & b) & a. */
3722 if ((code
== PLUS
|| code
== MINUS
3723 || code
== MULT
|| code
== AND
|| code
== IOR
|| code
== XOR
3724 || code
== DIV
|| code
== UDIV
3725 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3726 && INTEGRAL_MODE_P (mode
))
3728 if (GET_CODE (XEXP (x
, 0)) == code
)
3730 rtx other
= XEXP (XEXP (x
, 0), 0);
3731 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3732 rtx inner_op1
= XEXP (x
, 1);
3735 /* Make sure we pass the constant operand if any as the second
3736 one if this is a commutative operation. */
3737 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3739 rtx tem
= inner_op0
;
3740 inner_op0
= inner_op1
;
3743 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3744 : code
== DIV
? MULT
3745 : code
== UDIV
? MULT
3747 mode
, inner_op0
, inner_op1
);
3749 /* For commutative operations, try the other pair if that one
3751 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3753 other
= XEXP (XEXP (x
, 0), 1);
3754 inner
= simplify_binary_operation (code
, mode
,
3755 XEXP (XEXP (x
, 0), 0),
3760 return gen_binary (code
, mode
, other
, inner
);
3764 /* A little bit of algebraic simplification here. */
3768 /* Ensure that our address has any ASHIFTs converted to MULT in case
3769 address-recognizing predicates are called later. */
3770 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3771 SUBST (XEXP (x
, 0), temp
);
3775 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3776 is paradoxical. If we can't do that safely, then it becomes
3777 something nonsensical so that this combination won't take place. */
3779 if (GET_CODE (SUBREG_REG (x
)) == MEM
3780 && (GET_MODE_SIZE (mode
)
3781 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
3783 rtx inner
= SUBREG_REG (x
);
3784 int endian_offset
= 0;
3785 /* Don't change the mode of the MEM
3786 if that would change the meaning of the address. */
3787 if (MEM_VOLATILE_P (SUBREG_REG (x
))
3788 || mode_dependent_address_p (XEXP (inner
, 0)))
3789 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3791 if (BYTES_BIG_ENDIAN
)
3793 if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
3794 endian_offset
+= UNITS_PER_WORD
- GET_MODE_SIZE (mode
);
3795 if (GET_MODE_SIZE (GET_MODE (inner
)) < UNITS_PER_WORD
)
3796 endian_offset
-= (UNITS_PER_WORD
3797 - GET_MODE_SIZE (GET_MODE (inner
)));
3799 /* Note if the plus_constant doesn't make a valid address
3800 then this combination won't be accepted. */
3801 x
= gen_rtx_MEM (mode
,
3802 plus_constant (XEXP (inner
, 0),
3803 (SUBREG_WORD (x
) * UNITS_PER_WORD
3805 MEM_COPY_ATTRIBUTES (x
, inner
);
3809 /* If we are in a SET_DEST, these other cases can't apply. */
3813 /* Changing mode twice with SUBREG => just change it once,
3814 or not at all if changing back to starting mode. */
3815 if (GET_CODE (SUBREG_REG (x
)) == SUBREG
)
3817 if (mode
== GET_MODE (SUBREG_REG (SUBREG_REG (x
)))
3818 && SUBREG_WORD (x
) == 0 && SUBREG_WORD (SUBREG_REG (x
)) == 0)
3819 return SUBREG_REG (SUBREG_REG (x
));
3821 SUBST_INT (SUBREG_WORD (x
),
3822 SUBREG_WORD (x
) + SUBREG_WORD (SUBREG_REG (x
)));
3823 SUBST (SUBREG_REG (x
), SUBREG_REG (SUBREG_REG (x
)));
3826 /* SUBREG of a hard register => just change the register number
3827 and/or mode. If the hard register is not valid in that mode,
3828 suppress this combination. If the hard register is the stack,
3829 frame, or argument pointer, leave this as a SUBREG. */
3831 if (GET_CODE (SUBREG_REG (x
)) == REG
3832 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
3833 && REGNO (SUBREG_REG (x
)) != FRAME_POINTER_REGNUM
3834 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3835 && REGNO (SUBREG_REG (x
)) != HARD_FRAME_POINTER_REGNUM
3837 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3838 && REGNO (SUBREG_REG (x
)) != ARG_POINTER_REGNUM
3840 && REGNO (SUBREG_REG (x
)) != STACK_POINTER_REGNUM
)
3842 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
),
3844 return gen_rtx_REG (mode
,
3845 REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
));
3847 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3850 /* For a constant, try to pick up the part we want. Handle a full
3851 word and low-order part. Only do this if we are narrowing
3852 the constant; if it is being widened, we have no idea what
3853 the extra bits will have been set to. */
3855 if (CONSTANT_P (SUBREG_REG (x
)) && op0_mode
!= VOIDmode
3856 && GET_MODE_SIZE (mode
) == UNITS_PER_WORD
3857 && GET_MODE_SIZE (op0_mode
) > UNITS_PER_WORD
3858 && GET_MODE_CLASS (mode
) == MODE_INT
)
3860 temp
= operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
),
3866 /* If we want a subreg of a constant, at offset 0,
3867 take the low bits. On a little-endian machine, that's
3868 always valid. On a big-endian machine, it's valid
3869 only if the constant's mode fits in one word. Note that we
3870 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3871 if (CONSTANT_P (SUBREG_REG (x
))
3872 && ((GET_MODE_SIZE (op0_mode
) <= UNITS_PER_WORD
3873 || ! WORDS_BIG_ENDIAN
)
3874 ? SUBREG_WORD (x
) == 0
3876 == ((GET_MODE_SIZE (op0_mode
)
3877 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
3879 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (op0_mode
)
3880 && (! WORDS_BIG_ENDIAN
3881 || GET_MODE_BITSIZE (op0_mode
) <= BITS_PER_WORD
))
3882 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3884 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3885 since we are saying that the high bits don't matter. */
3886 if (CONSTANT_P (SUBREG_REG (x
)) && GET_MODE (SUBREG_REG (x
)) == VOIDmode
3887 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (op0_mode
))
3889 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))) > UNITS_PER_WORD
3890 && (WORDS_BIG_ENDIAN
|| SUBREG_WORD (x
) != 0))
3891 return operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
), 0, mode
);
3892 return SUBREG_REG (x
);
3895 /* Note that we cannot do any narrowing for non-constants since
3896 we might have been counting on using the fact that some bits were
3897 zero. We now do this in the SET. */
3902 /* (not (plus X -1)) can become (neg X). */
3903 if (GET_CODE (XEXP (x
, 0)) == PLUS
3904 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3905 return gen_rtx_combine (NEG
, mode
, XEXP (XEXP (x
, 0), 0));
3907 /* Similarly, (not (neg X)) is (plus X -1). */
3908 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3909 return gen_rtx_combine (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
3912 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3913 if (GET_CODE (XEXP (x
, 0)) == XOR
3914 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3915 && (temp
= simplify_unary_operation (NOT
, mode
,
3916 XEXP (XEXP (x
, 0), 1),
3918 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3920 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3921 other than 1, but that is not valid. We could do a similar
3922 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3923 but this doesn't seem common enough to bother with. */
3924 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3925 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3926 return gen_rtx_ROTATE (mode
, gen_unary (NOT
, mode
, mode
, const1_rtx
),
3927 XEXP (XEXP (x
, 0), 1));
3929 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3930 && subreg_lowpart_p (XEXP (x
, 0))
3931 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3932 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3933 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3934 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3936 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3938 x
= gen_rtx_ROTATE (inner_mode
,
3939 gen_unary (NOT
, inner_mode
, inner_mode
,
3941 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3942 return gen_lowpart_for_combine (mode
, x
);
3945 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3946 reversing the comparison code if valid. */
3947 if (STORE_FLAG_VALUE
== -1
3948 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3949 && (reversed
= reversed_comparison (x
, mode
, XEXP (XEXP (x
, 0), 0),
3950 XEXP (XEXP (x
, 0), 1))))
3953 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3954 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3955 perform the above simplification. */
3957 if (STORE_FLAG_VALUE
== -1
3958 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3959 && XEXP (x
, 1) == const1_rtx
3960 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3961 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3962 return gen_rtx_combine (GE
, mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3964 /* Apply De Morgan's laws to reduce number of patterns for machines
3965 with negating logical insns (and-not, nand, etc.). If result has
3966 only one NOT, put it first, since that is how the patterns are
3969 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3971 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3972 enum machine_mode op_mode
;
3974 op_mode
= GET_MODE (in1
);
3975 in1
= gen_unary (NOT
, op_mode
, op_mode
, in1
);
3977 op_mode
= GET_MODE (in2
);
3978 if (op_mode
== VOIDmode
)
3980 in2
= gen_unary (NOT
, op_mode
, op_mode
, in2
);
3982 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3985 in2
= in1
; in1
= tem
;
3988 return gen_rtx_combine (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3994 /* (neg (plus X 1)) can become (not X). */
3995 if (GET_CODE (XEXP (x
, 0)) == PLUS
3996 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3997 return gen_rtx_combine (NOT
, mode
, XEXP (XEXP (x
, 0), 0));
3999 /* Similarly, (neg (not X)) is (plus X 1). */
4000 if (GET_CODE (XEXP (x
, 0)) == NOT
)
4001 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
4003 /* (neg (minus X Y)) can become (minus Y X). */
4004 if (GET_CODE (XEXP (x
, 0)) == MINUS
4005 && (! FLOAT_MODE_P (mode
)
4006 /* x-y != -(y-x) with IEEE floating point. */
4007 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
4009 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
4010 XEXP (XEXP (x
, 0), 0));
4012 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4013 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
4014 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
4015 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
4017 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4018 if we can then eliminate the NEG (e.g.,
4019 if the operand is a constant). */
4021 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
4023 temp
= simplify_unary_operation (NEG
, mode
,
4024 XEXP (XEXP (x
, 0), 0), mode
);
4027 SUBST (XEXP (XEXP (x
, 0), 0), temp
);
4032 temp
= expand_compound_operation (XEXP (x
, 0));
4034 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4035 replaced by (lshiftrt X C). This will convert
4036 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4038 if (GET_CODE (temp
) == ASHIFTRT
4039 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
4040 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
4041 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
4042 INTVAL (XEXP (temp
, 1)));
4044 /* If X has only a single bit that might be nonzero, say, bit I, convert
4045 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4046 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4047 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4048 or a SUBREG of one since we'd be making the expression more
4049 complex if it was just a register. */
4051 if (GET_CODE (temp
) != REG
4052 && ! (GET_CODE (temp
) == SUBREG
4053 && GET_CODE (SUBREG_REG (temp
)) == REG
)
4054 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
4056 rtx temp1
= simplify_shift_const
4057 (NULL_RTX
, ASHIFTRT
, mode
,
4058 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
4059 GET_MODE_BITSIZE (mode
) - 1 - i
),
4060 GET_MODE_BITSIZE (mode
) - 1 - i
);
4062 /* If all we did was surround TEMP with the two shifts, we
4063 haven't improved anything, so don't use it. Otherwise,
4064 we are better off with TEMP1. */
4065 if (GET_CODE (temp1
) != ASHIFTRT
4066 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
4067 || XEXP (XEXP (temp1
, 0), 0) != temp
)
4073 /* We can't handle truncation to a partial integer mode here
4074 because we don't know the real bitsize of the partial
4076 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
4079 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4080 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4081 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
4083 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
4084 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4086 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4087 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4088 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4089 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4090 return XEXP (XEXP (x
, 0), 0);
4092 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4093 (OP:SI foo:SI) if OP is NEG or ABS. */
4094 if ((GET_CODE (XEXP (x
, 0)) == ABS
4095 || GET_CODE (XEXP (x
, 0)) == NEG
)
4096 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4097 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4098 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4099 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
4100 XEXP (XEXP (XEXP (x
, 0), 0), 0));
4102 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4104 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4105 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4106 && subreg_lowpart_p (XEXP (x
, 0)))
4107 return SUBREG_REG (XEXP (x
, 0));
4109 /* If we know that the value is already truncated, we can
4110 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4111 is nonzero for the corresponding modes. But don't do this
4112 for an (LSHIFTRT (MULT ...)) since this will cause problems
4113 with the umulXi3_highpart patterns. */
4114 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4115 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4116 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4117 >= GET_MODE_BITSIZE (mode
) + 1
4118 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4119 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4120 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4122 /* A truncate of a comparison can be replaced with a subreg if
4123 STORE_FLAG_VALUE permits. This is like the previous test,
4124 but it works even if the comparison is done in a mode larger
4125 than HOST_BITS_PER_WIDE_INT. */
4126 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4127 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4128 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
4129 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4131 /* Similarly, a truncate of a register whose value is a
4132 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4134 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4135 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4136 && (temp
= get_last_value (XEXP (x
, 0)))
4137 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4138 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4142 case FLOAT_TRUNCATE
:
4143 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4144 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4145 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4146 return XEXP (XEXP (x
, 0), 0);
4148 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4149 (OP:SF foo:SF) if OP is NEG or ABS. */
4150 if ((GET_CODE (XEXP (x
, 0)) == ABS
4151 || GET_CODE (XEXP (x
, 0)) == NEG
)
4152 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4153 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4154 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
4155 XEXP (XEXP (XEXP (x
, 0), 0), 0));
4157 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4158 is (float_truncate:SF x). */
4159 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4160 && subreg_lowpart_p (XEXP (x
, 0))
4161 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4162 return SUBREG_REG (XEXP (x
, 0));
4167 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4168 using cc0, in which case we want to leave it as a COMPARE
4169 so we can distinguish it from a register-register-copy. */
4170 if (XEXP (x
, 1) == const0_rtx
)
4173 /* In IEEE floating point, x-0 is not the same as x. */
4174 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
4175 || ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0)))
4177 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4183 /* (const (const X)) can become (const X). Do it this way rather than
4184 returning the inner CONST since CONST can be shared with a
4186 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4187 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4192 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4193 can add in an offset. find_split_point will split this address up
4194 again if it doesn't match. */
4195 if (GET_CODE (XEXP (x
, 0)) == HIGH
4196 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4202 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4203 outermost. That's because that's the way indexed addresses are
4204 supposed to appear. This code used to check many more cases, but
4205 they are now checked elsewhere. */
4206 if (GET_CODE (XEXP (x
, 0)) == PLUS
4207 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4208 return gen_binary (PLUS
, mode
,
4209 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4211 XEXP (XEXP (x
, 0), 1));
4213 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4214 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4215 bit-field and can be replaced by either a sign_extend or a
4216 sign_extract. The `and' may be a zero_extend and the two
4217 <c>, -<c> constants may be reversed. */
4218 if (GET_CODE (XEXP (x
, 0)) == XOR
4219 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4220 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4221 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4222 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4223 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4224 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4225 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4226 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4227 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4228 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4229 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4230 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4231 == (unsigned int) i
+ 1))))
4232 return simplify_shift_const
4233 (NULL_RTX
, ASHIFTRT
, mode
,
4234 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4235 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4236 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4237 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4239 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4240 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4241 is 1. This produces better code than the alternative immediately
4243 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4244 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4245 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4246 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4247 XEXP (XEXP (x
, 0), 0),
4248 XEXP (XEXP (x
, 0), 1))))
4250 gen_unary (NEG
, mode
, mode
, reversed
);
4252 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4253 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4254 the bitsize of the mode - 1. This allows simplification of
4255 "a = (b & 8) == 0;" */
4256 if (XEXP (x
, 1) == constm1_rtx
4257 && GET_CODE (XEXP (x
, 0)) != REG
4258 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
4259 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4260 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4261 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4262 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4263 gen_rtx_combine (XOR
, mode
,
4264 XEXP (x
, 0), const1_rtx
),
4265 GET_MODE_BITSIZE (mode
) - 1),
4266 GET_MODE_BITSIZE (mode
) - 1);
4268 /* If we are adding two things that have no bits in common, convert
4269 the addition into an IOR. This will often be further simplified,
4270 for example in cases like ((a & 1) + (a & 2)), which can
4273 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4274 && (nonzero_bits (XEXP (x
, 0), mode
)
4275 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4277 /* Try to simplify the expression further. */
4278 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4279 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4281 /* If we could, great. If not, do not go ahead with the IOR
4282 replacement, since PLUS appears in many special purpose
4283 address arithmetic instructions. */
4284 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4290 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4291 by reversing the comparison code if valid. */
4292 if (STORE_FLAG_VALUE
== 1
4293 && XEXP (x
, 0) == const1_rtx
4294 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4295 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4296 XEXP (XEXP (x
, 1), 0),
4297 XEXP (XEXP (x
, 1), 1))))
4300 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4301 (and <foo> (const_int pow2-1)) */
4302 if (GET_CODE (XEXP (x
, 1)) == AND
4303 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4304 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4305 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4306 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4307 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4309 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4311 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4312 return gen_binary (MINUS
, mode
,
4313 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4314 XEXP (XEXP (x
, 1), 0)),
4315 XEXP (XEXP (x
, 1), 1));
4319 /* If we have (mult (plus A B) C), apply the distributive law and then
4320 the inverse distributive law to see if things simplify. This
4321 occurs mostly in addresses, often when unrolling loops. */
4323 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4325 x
= apply_distributive_law
4326 (gen_binary (PLUS
, mode
,
4327 gen_binary (MULT
, mode
,
4328 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4329 gen_binary (MULT
, mode
,
4330 XEXP (XEXP (x
, 0), 1),
4331 copy_rtx (XEXP (x
, 1)))));
4333 if (GET_CODE (x
) != MULT
)
4339 /* If this is a divide by a power of two, treat it as a shift if
4340 its first operand is a shift. */
4341 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4342 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4343 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4344 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4345 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4346 || GET_CODE (XEXP (x
, 0)) == ROTATE
4347 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4348 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4352 case GT
: case GTU
: case GE
: case GEU
:
4353 case LT
: case LTU
: case LE
: case LEU
:
4354 case UNEQ
: case LTGT
:
4355 case UNGT
: case UNGE
:
4356 case UNLT
: case UNLE
:
4357 case UNORDERED
: case ORDERED
:
4358 /* If the first operand is a condition code, we can't do anything
4360 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4361 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4363 && XEXP (x
, 0) != cc0_rtx
4367 rtx op0
= XEXP (x
, 0);
4368 rtx op1
= XEXP (x
, 1);
4369 enum rtx_code new_code
;
4371 if (GET_CODE (op0
) == COMPARE
)
4372 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4374 /* Simplify our comparison, if possible. */
4375 new_code
= simplify_comparison (code
, &op0
, &op1
);
4377 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4378 if only the low-order bit is possibly nonzero in X (such as when
4379 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4380 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4381 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4384 Remove any ZERO_EXTRACT we made when thinking this was a
4385 comparison. It may now be simpler to use, e.g., an AND. If a
4386 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4387 the call to make_compound_operation in the SET case. */
4389 if (STORE_FLAG_VALUE
== 1
4390 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4391 && op1
== const0_rtx
4392 && mode
== GET_MODE (op0
)
4393 && nonzero_bits (op0
, mode
) == 1)
4394 return gen_lowpart_for_combine (mode
,
4395 expand_compound_operation (op0
));
4397 else if (STORE_FLAG_VALUE
== 1
4398 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4399 && op1
== const0_rtx
4400 && mode
== GET_MODE (op0
)
4401 && (num_sign_bit_copies (op0
, mode
)
4402 == GET_MODE_BITSIZE (mode
)))
4404 op0
= expand_compound_operation (op0
);
4405 return gen_unary (NEG
, mode
, mode
,
4406 gen_lowpart_for_combine (mode
, op0
));
4409 else if (STORE_FLAG_VALUE
== 1
4410 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4411 && op1
== const0_rtx
4412 && mode
== GET_MODE (op0
)
4413 && nonzero_bits (op0
, mode
) == 1)
4415 op0
= expand_compound_operation (op0
);
4416 return gen_binary (XOR
, mode
,
4417 gen_lowpart_for_combine (mode
, op0
),
4421 else if (STORE_FLAG_VALUE
== 1
4422 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4423 && op1
== const0_rtx
4424 && mode
== GET_MODE (op0
)
4425 && (num_sign_bit_copies (op0
, mode
)
4426 == GET_MODE_BITSIZE (mode
)))
4428 op0
= expand_compound_operation (op0
);
4429 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4432 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4434 if (STORE_FLAG_VALUE
== -1
4435 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4436 && op1
== const0_rtx
4437 && (num_sign_bit_copies (op0
, mode
)
4438 == GET_MODE_BITSIZE (mode
)))
4439 return gen_lowpart_for_combine (mode
,
4440 expand_compound_operation (op0
));
4442 else if (STORE_FLAG_VALUE
== -1
4443 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4444 && op1
== const0_rtx
4445 && mode
== GET_MODE (op0
)
4446 && nonzero_bits (op0
, mode
) == 1)
4448 op0
= expand_compound_operation (op0
);
4449 return gen_unary (NEG
, mode
, mode
,
4450 gen_lowpart_for_combine (mode
, op0
));
4453 else if (STORE_FLAG_VALUE
== -1
4454 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4455 && op1
== const0_rtx
4456 && mode
== GET_MODE (op0
)
4457 && (num_sign_bit_copies (op0
, mode
)
4458 == GET_MODE_BITSIZE (mode
)))
4460 op0
= expand_compound_operation (op0
);
4461 return gen_unary (NOT
, mode
, mode
,
4462 gen_lowpart_for_combine (mode
, op0
));
4465 /* If X is 0/1, (eq X 0) is X-1. */
4466 else if (STORE_FLAG_VALUE
== -1
4467 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4468 && op1
== const0_rtx
4469 && mode
== GET_MODE (op0
)
4470 && nonzero_bits (op0
, mode
) == 1)
4472 op0
= expand_compound_operation (op0
);
4473 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4476 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4477 one bit that might be nonzero, we can convert (ne x 0) to
4478 (ashift x c) where C puts the bit in the sign bit. Remove any
4479 AND with STORE_FLAG_VALUE when we are done, since we are only
4480 going to test the sign bit. */
4481 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4482 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4483 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4484 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE(mode
)-1))
4485 && op1
== const0_rtx
4486 && mode
== GET_MODE (op0
)
4487 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4489 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4490 expand_compound_operation (op0
),
4491 GET_MODE_BITSIZE (mode
) - 1 - i
);
4492 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4498 /* If the code changed, return a whole new comparison. */
4499 if (new_code
!= code
)
4500 return gen_rtx_combine (new_code
, mode
, op0
, op1
);
4502 /* Otherwise, keep this operation, but maybe change its operands.
4503 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4504 SUBST (XEXP (x
, 0), op0
);
4505 SUBST (XEXP (x
, 1), op1
);
4510 return simplify_if_then_else (x
);
4516 /* If we are processing SET_DEST, we are done. */
4520 return expand_compound_operation (x
);
4523 return simplify_set (x
);
4528 return simplify_logical (x
, last
);
4531 /* (abs (neg <foo>)) -> (abs <foo>) */
4532 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4533 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4535 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4537 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4540 /* If operand is something known to be positive, ignore the ABS. */
4541 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4542 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4543 <= HOST_BITS_PER_WIDE_INT
)
4544 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4545 & ((HOST_WIDE_INT
) 1
4546 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4550 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4551 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4552 return gen_rtx_combine (NEG
, mode
, XEXP (x
, 0));
4557 /* (ffs (*_extend <X>)) = (ffs <X>) */
4558 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4559 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4560 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4564 /* (float (sign_extend <X>)) = (float <X>). */
4565 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4566 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4574 /* If this is a shift by a constant amount, simplify it. */
4575 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4576 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4577 INTVAL (XEXP (x
, 1)));
4579 #ifdef SHIFT_COUNT_TRUNCATED
4580 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4582 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
4584 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4593 rtx op0
= XEXP (x
, 0);
4594 rtx op1
= XEXP (x
, 1);
4597 if (GET_CODE (op1
) != PARALLEL
)
4599 len
= XVECLEN (op1
, 0);
4601 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4602 && GET_CODE (op0
) == VEC_CONCAT
)
4604 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4606 /* Try to find the element in the VEC_CONCAT. */
4609 if (GET_MODE (op0
) == GET_MODE (x
))
4611 if (GET_CODE (op0
) == VEC_CONCAT
)
4613 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4614 if (op0_size
< offset
)
4615 op0
= XEXP (op0
, 0);
4619 op0
= XEXP (op0
, 1);
4637 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4640 simplify_if_then_else (x
)
4643 enum machine_mode mode
= GET_MODE (x
);
4644 rtx cond
= XEXP (x
, 0);
4645 rtx
true = XEXP (x
, 1);
4646 rtx
false = XEXP (x
, 2);
4647 enum rtx_code true_code
= GET_CODE (cond
);
4648 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4651 enum rtx_code false_code
;
4654 /* Simplify storing of the truth value. */
4655 if (comparison_p
&& true == const_true_rtx
&& false == const0_rtx
)
4656 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4658 /* Also when the truth value has to be reversed. */
4660 && true == const0_rtx
&& false == const_true_rtx
4661 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4665 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4666 in it is being compared against certain values. Get the true and false
4667 comparisons and see if that says anything about the value of each arm. */
4670 && ((false_code
= combine_reversed_comparison_code (cond
))
4672 && GET_CODE (XEXP (cond
, 0)) == REG
)
4675 rtx from
= XEXP (cond
, 0);
4676 rtx true_val
= XEXP (cond
, 1);
4677 rtx false_val
= true_val
;
4680 /* If FALSE_CODE is EQ, swap the codes and arms. */
4682 if (false_code
== EQ
)
4684 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4685 temp
= true, true = false, false = temp
;
4688 /* If we are comparing against zero and the expression being tested has
4689 only a single bit that might be nonzero, that is its value when it is
4690 not equal to zero. Similarly if it is known to be -1 or 0. */
4692 if (true_code
== EQ
&& true_val
== const0_rtx
4693 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4694 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4695 else if (true_code
== EQ
&& true_val
== const0_rtx
4696 && (num_sign_bit_copies (from
, GET_MODE (from
))
4697 == GET_MODE_BITSIZE (GET_MODE (from
))))
4698 false_code
= EQ
, false_val
= constm1_rtx
;
4700 /* Now simplify an arm if we know the value of the register in the
4701 branch and it is used in the arm. Be careful due to the potential
4702 of locally-shared RTL. */
4704 if (reg_mentioned_p (from
, true))
4705 true = subst (known_cond (copy_rtx (true), true_code
, from
, true_val
),
4706 pc_rtx
, pc_rtx
, 0, 0);
4707 if (reg_mentioned_p (from
, false))
4708 false = subst (known_cond (copy_rtx (false), false_code
,
4710 pc_rtx
, pc_rtx
, 0, 0);
4712 SUBST (XEXP (x
, 1), swapped
? false : true);
4713 SUBST (XEXP (x
, 2), swapped
? true : false);
4715 true = XEXP (x
, 1), false = XEXP (x
, 2), true_code
= GET_CODE (cond
);
4718 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4719 reversed, do so to avoid needing two sets of patterns for
4720 subtract-and-branch insns. Similarly if we have a constant in the true
4721 arm, the false arm is the same as the first operand of the comparison, or
4722 the false arm is more complicated than the true arm. */
4725 && combine_reversed_comparison_code (cond
) != UNKNOWN
4727 || (CONSTANT_P (true)
4728 && GET_CODE (false) != CONST_INT
&& false != pc_rtx
)
4729 || true == const0_rtx
4730 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4731 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4732 || (GET_CODE (true) == SUBREG
4733 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4734 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4735 || reg_mentioned_p (true, false)
4736 || rtx_equal_p (false, XEXP (cond
, 0))))
4738 true_code
= reversed_comparison_code (cond
, NULL
);
4740 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4743 SUBST (XEXP (x
, 1), false);
4744 SUBST (XEXP (x
, 2), true);
4746 temp
= true, true = false, false = temp
, cond
= XEXP (x
, 0);
4748 /* It is possible that the conditional has been simplified out. */
4749 true_code
= GET_CODE (cond
);
4750 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4753 /* If the two arms are identical, we don't need the comparison. */
4755 if (rtx_equal_p (true, false) && ! side_effects_p (cond
))
4758 /* Convert a == b ? b : a to "a". */
4759 if (true_code
== EQ
&& ! side_effects_p (cond
)
4760 && (! FLOAT_MODE_P (mode
) || flag_fast_math
)
4761 && rtx_equal_p (XEXP (cond
, 0), false)
4762 && rtx_equal_p (XEXP (cond
, 1), true))
4764 else if (true_code
== NE
&& ! side_effects_p (cond
)
4765 && (! FLOAT_MODE_P (mode
) || flag_fast_math
)
4766 && rtx_equal_p (XEXP (cond
, 0), true)
4767 && rtx_equal_p (XEXP (cond
, 1), false))
4770 /* Look for cases where we have (abs x) or (neg (abs X)). */
4772 if (GET_MODE_CLASS (mode
) == MODE_INT
4773 && GET_CODE (false) == NEG
4774 && rtx_equal_p (true, XEXP (false, 0))
4776 && rtx_equal_p (true, XEXP (cond
, 0))
4777 && ! side_effects_p (true))
4782 return gen_unary (ABS
, mode
, mode
, true);
4785 return gen_unary (NEG
, mode
, mode
, gen_unary (ABS
, mode
, mode
, true));
4790 /* Look for MIN or MAX. */
4792 if ((! FLOAT_MODE_P (mode
) || flag_fast_math
)
4794 && rtx_equal_p (XEXP (cond
, 0), true)
4795 && rtx_equal_p (XEXP (cond
, 1), false)
4796 && ! side_effects_p (cond
))
4801 return gen_binary (SMAX
, mode
, true, false);
4804 return gen_binary (SMIN
, mode
, true, false);
4807 return gen_binary (UMAX
, mode
, true, false);
4810 return gen_binary (UMIN
, mode
, true, false);
4815 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4816 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4817 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4818 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4819 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4820 neither 1 or -1, but it isn't worth checking for. */
4822 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4823 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4825 rtx t
= make_compound_operation (true, SET
);
4826 rtx f
= make_compound_operation (false, SET
);
4827 rtx cond_op0
= XEXP (cond
, 0);
4828 rtx cond_op1
= XEXP (cond
, 1);
4829 enum rtx_code op
= NIL
, extend_op
= NIL
;
4830 enum machine_mode m
= mode
;
4831 rtx z
= 0, c1
= NULL_RTX
;
4833 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4834 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4835 || GET_CODE (t
) == ASHIFT
4836 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4837 && rtx_equal_p (XEXP (t
, 0), f
))
4838 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4840 /* If an identity-zero op is commutative, check whether there
4841 would be a match if we swapped the operands. */
4842 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4843 || GET_CODE (t
) == XOR
)
4844 && rtx_equal_p (XEXP (t
, 1), f
))
4845 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4846 else if (GET_CODE (t
) == SIGN_EXTEND
4847 && (GET_CODE (XEXP (t
, 0)) == PLUS
4848 || GET_CODE (XEXP (t
, 0)) == MINUS
4849 || GET_CODE (XEXP (t
, 0)) == IOR
4850 || GET_CODE (XEXP (t
, 0)) == XOR
4851 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4852 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4853 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4854 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4855 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4856 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4857 && (num_sign_bit_copies (f
, GET_MODE (f
))
4858 > (GET_MODE_BITSIZE (mode
)
4859 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4861 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4862 extend_op
= SIGN_EXTEND
;
4863 m
= GET_MODE (XEXP (t
, 0));
4865 else if (GET_CODE (t
) == SIGN_EXTEND
4866 && (GET_CODE (XEXP (t
, 0)) == PLUS
4867 || GET_CODE (XEXP (t
, 0)) == IOR
4868 || GET_CODE (XEXP (t
, 0)) == XOR
)
4869 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4870 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4871 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4872 && (num_sign_bit_copies (f
, GET_MODE (f
))
4873 > (GET_MODE_BITSIZE (mode
)
4874 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4876 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4877 extend_op
= SIGN_EXTEND
;
4878 m
= GET_MODE (XEXP (t
, 0));
4880 else if (GET_CODE (t
) == ZERO_EXTEND
4881 && (GET_CODE (XEXP (t
, 0)) == PLUS
4882 || GET_CODE (XEXP (t
, 0)) == MINUS
4883 || GET_CODE (XEXP (t
, 0)) == IOR
4884 || GET_CODE (XEXP (t
, 0)) == XOR
4885 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4886 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4887 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4888 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4889 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4890 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4891 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4892 && ((nonzero_bits (f
, GET_MODE (f
))
4893 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4896 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4897 extend_op
= ZERO_EXTEND
;
4898 m
= GET_MODE (XEXP (t
, 0));
4900 else if (GET_CODE (t
) == ZERO_EXTEND
4901 && (GET_CODE (XEXP (t
, 0)) == PLUS
4902 || GET_CODE (XEXP (t
, 0)) == IOR
4903 || GET_CODE (XEXP (t
, 0)) == XOR
)
4904 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4905 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4906 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4907 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4908 && ((nonzero_bits (f
, GET_MODE (f
))
4909 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4912 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4913 extend_op
= ZERO_EXTEND
;
4914 m
= GET_MODE (XEXP (t
, 0));
4919 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4920 pc_rtx
, pc_rtx
, 0, 0);
4921 temp
= gen_binary (MULT
, m
, temp
,
4922 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4923 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4924 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4926 if (extend_op
!= NIL
)
4927 temp
= gen_unary (extend_op
, mode
, m
, temp
);
4933 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4934 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4935 negation of a single bit, we can convert this operation to a shift. We
4936 can actually do this more generally, but it doesn't seem worth it. */
4938 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4939 && false == const0_rtx
&& GET_CODE (true) == CONST_INT
4940 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4941 && (i
= exact_log2 (INTVAL (true))) >= 0)
4942 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4943 == GET_MODE_BITSIZE (mode
))
4944 && (i
= exact_log2 (-INTVAL (true))) >= 0)))
4946 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4947 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4952 /* Simplify X, a SET expression. Return the new expression. */
4958 rtx src
= SET_SRC (x
);
4959 rtx dest
= SET_DEST (x
);
4960 enum machine_mode mode
4961 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4965 /* (set (pc) (return)) gets written as (return). */
4966 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4969 /* Now that we know for sure which bits of SRC we are using, see if we can
4970 simplify the expression for the object knowing that we only need the
4973 if (GET_MODE_CLASS (mode
) == MODE_INT
)
4975 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4976 SUBST (SET_SRC (x
), src
);
4979 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4980 the comparison result and try to simplify it unless we already have used
4981 undobuf.other_insn. */
4982 if ((GET_CODE (src
) == COMPARE
4987 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4988 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4989 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4990 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4992 enum rtx_code old_code
= GET_CODE (*cc_use
);
4993 enum rtx_code new_code
;
4995 int other_changed
= 0;
4996 enum machine_mode compare_mode
= GET_MODE (dest
);
4998 if (GET_CODE (src
) == COMPARE
)
4999 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
5001 op0
= src
, op1
= const0_rtx
;
5003 /* Simplify our comparison, if possible. */
5004 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5006 #ifdef EXTRA_CC_MODES
5007 /* If this machine has CC modes other than CCmode, check to see if we
5008 need to use a different CC mode here. */
5009 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5010 #endif /* EXTRA_CC_MODES */
5012 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5013 /* If the mode changed, we have to change SET_DEST, the mode in the
5014 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5015 a hard register, just build new versions with the proper mode. If it
5016 is a pseudo, we lose unless it is only time we set the pseudo, in
5017 which case we can safely change its mode. */
5018 if (compare_mode
!= GET_MODE (dest
))
5020 unsigned int regno
= REGNO (dest
);
5021 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5023 if (regno
< FIRST_PSEUDO_REGISTER
5024 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5026 if (regno
>= FIRST_PSEUDO_REGISTER
)
5027 SUBST (regno_reg_rtx
[regno
], new_dest
);
5029 SUBST (SET_DEST (x
), new_dest
);
5030 SUBST (XEXP (*cc_use
, 0), new_dest
);
5038 /* If the code changed, we have to build a new comparison in
5039 undobuf.other_insn. */
5040 if (new_code
!= old_code
)
5042 unsigned HOST_WIDE_INT mask
;
5044 SUBST (*cc_use
, gen_rtx_combine (new_code
, GET_MODE (*cc_use
),
5047 /* If the only change we made was to change an EQ into an NE or
5048 vice versa, OP0 has only one bit that might be nonzero, and OP1
5049 is zero, check if changing the user of the condition code will
5050 produce a valid insn. If it won't, we can keep the original code
5051 in that insn by surrounding our operation with an XOR. */
5053 if (((old_code
== NE
&& new_code
== EQ
)
5054 || (old_code
== EQ
&& new_code
== NE
))
5055 && ! other_changed
&& op1
== const0_rtx
5056 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5057 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5059 rtx pat
= PATTERN (other_insn
), note
= 0;
5061 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5062 && ! check_asm_operands (pat
)))
5064 PUT_CODE (*cc_use
, old_code
);
5067 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5075 undobuf
.other_insn
= other_insn
;
5078 /* If we are now comparing against zero, change our source if
5079 needed. If we do not use cc0, we always have a COMPARE. */
5080 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5082 SUBST (SET_SRC (x
), op0
);
5088 /* Otherwise, if we didn't previously have a COMPARE in the
5089 correct mode, we need one. */
5090 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5093 gen_rtx_combine (COMPARE
, compare_mode
, op0
, op1
));
5098 /* Otherwise, update the COMPARE if needed. */
5099 SUBST (XEXP (src
, 0), op0
);
5100 SUBST (XEXP (src
, 1), op1
);
5105 /* Get SET_SRC in a form where we have placed back any
5106 compound expressions. Then do the checks below. */
5107 src
= make_compound_operation (src
, SET
);
5108 SUBST (SET_SRC (x
), src
);
5111 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5112 and X being a REG or (subreg (reg)), we may be able to convert this to
5113 (set (subreg:m2 x) (op)).
5115 We can always do this if M1 is narrower than M2 because that means that
5116 we only care about the low bits of the result.
5118 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5119 perform a narrower operation than requested since the high-order bits will
5120 be undefined. On machine where it is defined, this transformation is safe
5121 as long as M1 and M2 have the same number of words. */
5123 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5124 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5125 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5127 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5128 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5129 #ifndef WORD_REGISTER_OPERATIONS
5130 && (GET_MODE_SIZE (GET_MODE (src
))
5131 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5133 #ifdef CLASS_CANNOT_CHANGE_MODE
5134 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5135 && (TEST_HARD_REG_BIT
5136 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
5138 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src
),
5139 GET_MODE (SUBREG_REG (src
))))
5141 && (GET_CODE (dest
) == REG
5142 || (GET_CODE (dest
) == SUBREG
5143 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5145 SUBST (SET_DEST (x
),
5146 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5148 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5150 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5153 #ifdef LOAD_EXTEND_OP
5154 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5155 would require a paradoxical subreg. Replace the subreg with a
5156 zero_extend to avoid the reload that would otherwise be required. */
5158 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5159 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5160 && SUBREG_WORD (src
) == 0
5161 && (GET_MODE_SIZE (GET_MODE (src
))
5162 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5163 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5166 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5167 GET_MODE (src
), XEXP (src
, 0)));
5173 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5174 are comparing an item known to be 0 or -1 against 0, use a logical
5175 operation instead. Check for one of the arms being an IOR of the other
5176 arm with some value. We compute three terms to be IOR'ed together. In
5177 practice, at most two will be nonzero. Then we do the IOR's. */
5179 if (GET_CODE (dest
) != PC
5180 && GET_CODE (src
) == IF_THEN_ELSE
5181 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5182 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5183 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5184 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5185 #ifdef HAVE_conditional_move
5186 && ! can_conditionally_move_p (GET_MODE (src
))
5188 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5189 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5190 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5191 && ! side_effects_p (src
))
5193 rtx
true = (GET_CODE (XEXP (src
, 0)) == NE
5194 ? XEXP (src
, 1) : XEXP (src
, 2));
5195 rtx
false = (GET_CODE (XEXP (src
, 0)) == NE
5196 ? XEXP (src
, 2) : XEXP (src
, 1));
5197 rtx term1
= const0_rtx
, term2
, term3
;
5199 if (GET_CODE (true) == IOR
&& rtx_equal_p (XEXP (true, 0), false))
5200 term1
= false, true = XEXP (true, 1), false = const0_rtx
;
5201 else if (GET_CODE (true) == IOR
5202 && rtx_equal_p (XEXP (true, 1), false))
5203 term1
= false, true = XEXP (true, 0), false = const0_rtx
;
5204 else if (GET_CODE (false) == IOR
5205 && rtx_equal_p (XEXP (false, 0), true))
5206 term1
= true, false = XEXP (false, 1), true = const0_rtx
;
5207 else if (GET_CODE (false) == IOR
5208 && rtx_equal_p (XEXP (false, 1), true))
5209 term1
= true, false = XEXP (false, 0), true = const0_rtx
;
5211 term2
= gen_binary (AND
, GET_MODE (src
), XEXP (XEXP (src
, 0), 0), true);
5212 term3
= gen_binary (AND
, GET_MODE (src
),
5213 gen_unary (NOT
, GET_MODE (src
), GET_MODE (src
),
5214 XEXP (XEXP (src
, 0), 0)),
5218 gen_binary (IOR
, GET_MODE (src
),
5219 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5225 #ifdef HAVE_conditional_arithmetic
5226 /* If we have conditional arithmetic and the operand of a SET is
5227 a conditional expression, replace this with an IF_THEN_ELSE.
5228 We can either have a conditional expression or a MULT of that expression
5230 if ((GET_RTX_CLASS (GET_CODE (src
)) == '1'
5231 || GET_RTX_CLASS (GET_CODE (src
)) == '2'
5232 || GET_RTX_CLASS (GET_CODE (src
)) == 'c')
5233 && (GET_RTX_CLASS (GET_CODE (XEXP (src
, 0))) == '<'
5234 || (GET_CODE (XEXP (src
, 0)) == MULT
5235 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src
, 0), 0))) == '<'
5236 && GET_CODE (XEXP (XEXP (src
, 0), 1)) == CONST_INT
)))
5238 rtx cond
= XEXP (src
, 0);
5239 rtx true_val
= const1_rtx
;
5240 rtx false_arm
, true_arm
;
5243 if (GET_CODE (cond
) == MULT
)
5245 true_val
= XEXP (cond
, 1);
5246 cond
= XEXP (cond
, 0);
5249 if (GET_RTX_CLASS (GET_CODE (src
)) == '1')
5251 true_arm
= gen_unary (GET_CODE (src
), GET_MODE (src
),
5252 GET_MODE (XEXP (src
, 0)), true_val
);
5253 false_arm
= gen_unary (GET_CODE (src
), GET_MODE (src
),
5254 GET_MODE (XEXP (src
, 0)), const0_rtx
);
5258 true_arm
= gen_binary (GET_CODE (src
), GET_MODE (src
),
5259 true_val
, XEXP (src
, 1));
5260 false_arm
= gen_binary (GET_CODE (src
), GET_MODE (src
),
5261 const0_rtx
, XEXP (src
, 1));
5264 /* Canonicalize if true_arm is the simpler one. */
5265 if (GET_RTX_CLASS (GET_CODE (true_arm
)) == 'o'
5266 && GET_RTX_CLASS (GET_CODE (false_arm
)) != 'o'
5267 && (reversed
= reversed_comparison_code (cond
, GET_MODE (cond
),
5271 rtx temp
= true_arm
;
5273 true_arm
= false_arm
;
5279 src
= gen_rtx_combine (IF_THEN_ELSE
, GET_MODE (src
),
5280 gen_rtx_combine (GET_CODE (cond
), VOIDmode
,
5283 true_arm
, false_arm
);
5284 SUBST (SET_SRC (x
), src
);
5288 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5289 whole thing fail. */
5290 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5292 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5295 /* Convert this into a field assignment operation, if possible. */
5296 return make_field_assignment (x
);
5299 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5300 result. LAST is nonzero if this is the last retry. */
5303 simplify_logical (x
, last
)
5307 enum machine_mode mode
= GET_MODE (x
);
5308 rtx op0
= XEXP (x
, 0);
5309 rtx op1
= XEXP (x
, 1);
5312 switch (GET_CODE (x
))
5315 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5316 insn (and may simplify more). */
5317 if (GET_CODE (op0
) == XOR
5318 && rtx_equal_p (XEXP (op0
, 0), op1
)
5319 && ! side_effects_p (op1
))
5320 x
= gen_binary (AND
, mode
,
5321 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)), op1
);
5323 if (GET_CODE (op0
) == XOR
5324 && rtx_equal_p (XEXP (op0
, 1), op1
)
5325 && ! side_effects_p (op1
))
5326 x
= gen_binary (AND
, mode
,
5327 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)), op1
);
5329 /* Similarly for (~(A ^ B)) & A. */
5330 if (GET_CODE (op0
) == NOT
5331 && GET_CODE (XEXP (op0
, 0)) == XOR
5332 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5333 && ! side_effects_p (op1
))
5334 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5336 if (GET_CODE (op0
) == NOT
5337 && GET_CODE (XEXP (op0
, 0)) == XOR
5338 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5339 && ! side_effects_p (op1
))
5340 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5342 /* We can call simplify_and_const_int only if we don't lose
5343 any (sign) bits when converting INTVAL (op1) to
5344 "unsigned HOST_WIDE_INT". */
5345 if (GET_CODE (op1
) == CONST_INT
5346 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5347 || INTVAL (op1
) > 0))
5349 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5351 /* If we have (ior (and (X C1) C2)) and the next restart would be
5352 the last, simplify this by making C1 as small as possible
5355 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5356 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5357 && GET_CODE (op1
) == CONST_INT
)
5358 return gen_binary (IOR
, mode
,
5359 gen_binary (AND
, mode
, XEXP (op0
, 0),
5360 GEN_INT (INTVAL (XEXP (op0
, 1))
5361 & ~INTVAL (op1
))), op1
);
5363 if (GET_CODE (x
) != AND
)
5366 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5367 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5368 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5371 /* Convert (A | B) & A to A. */
5372 if (GET_CODE (op0
) == IOR
5373 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5374 || rtx_equal_p (XEXP (op0
, 1), op1
))
5375 && ! side_effects_p (XEXP (op0
, 0))
5376 && ! side_effects_p (XEXP (op0
, 1)))
5379 /* In the following group of tests (and those in case IOR below),
5380 we start with some combination of logical operations and apply
5381 the distributive law followed by the inverse distributive law.
5382 Most of the time, this results in no change. However, if some of
5383 the operands are the same or inverses of each other, simplifications
5386 For example, (and (ior A B) (not B)) can occur as the result of
5387 expanding a bit field assignment. When we apply the distributive
5388 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5389 which then simplifies to (and (A (not B))).
5391 If we have (and (ior A B) C), apply the distributive law and then
5392 the inverse distributive law to see if things simplify. */
5394 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5396 x
= apply_distributive_law
5397 (gen_binary (GET_CODE (op0
), mode
,
5398 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5399 gen_binary (AND
, mode
, XEXP (op0
, 1),
5401 if (GET_CODE (x
) != AND
)
5405 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5406 return apply_distributive_law
5407 (gen_binary (GET_CODE (op1
), mode
,
5408 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5409 gen_binary (AND
, mode
, XEXP (op1
, 1),
5412 /* Similarly, taking advantage of the fact that
5413 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5415 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5416 return apply_distributive_law
5417 (gen_binary (XOR
, mode
,
5418 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5419 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5422 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5423 return apply_distributive_law
5424 (gen_binary (XOR
, mode
,
5425 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5426 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5430 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5431 if (GET_CODE (op1
) == CONST_INT
5432 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5433 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5436 /* Convert (A & B) | A to A. */
5437 if (GET_CODE (op0
) == AND
5438 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5439 || rtx_equal_p (XEXP (op0
, 1), op1
))
5440 && ! side_effects_p (XEXP (op0
, 0))
5441 && ! side_effects_p (XEXP (op0
, 1)))
5444 /* If we have (ior (and A B) C), apply the distributive law and then
5445 the inverse distributive law to see if things simplify. */
5447 if (GET_CODE (op0
) == AND
)
5449 x
= apply_distributive_law
5450 (gen_binary (AND
, mode
,
5451 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5452 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5455 if (GET_CODE (x
) != IOR
)
5459 if (GET_CODE (op1
) == AND
)
5461 x
= apply_distributive_law
5462 (gen_binary (AND
, mode
,
5463 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5464 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5467 if (GET_CODE (x
) != IOR
)
5471 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5472 mode size to (rotate A CX). */
5474 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5475 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5476 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5477 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5478 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5479 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5480 == GET_MODE_BITSIZE (mode
)))
5481 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5482 (GET_CODE (op0
) == ASHIFT
5483 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5485 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5486 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5487 does not affect any of the bits in OP1, it can really be done
5488 as a PLUS and we can associate. We do this by seeing if OP1
5489 can be safely shifted left C bits. */
5490 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5491 && GET_CODE (XEXP (op0
, 0)) == PLUS
5492 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5493 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5494 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5496 int count
= INTVAL (XEXP (op0
, 1));
5497 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5499 if (mask
>> count
== INTVAL (op1
)
5500 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5502 SUBST (XEXP (XEXP (op0
, 0), 1),
5503 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5510 /* If we are XORing two things that have no bits in common,
5511 convert them into an IOR. This helps to detect rotation encoded
5512 using those methods and possibly other simplifications. */
5514 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5515 && (nonzero_bits (op0
, mode
)
5516 & nonzero_bits (op1
, mode
)) == 0)
5517 return (gen_binary (IOR
, mode
, op0
, op1
));
5519 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5520 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5523 int num_negated
= 0;
5525 if (GET_CODE (op0
) == NOT
)
5526 num_negated
++, op0
= XEXP (op0
, 0);
5527 if (GET_CODE (op1
) == NOT
)
5528 num_negated
++, op1
= XEXP (op1
, 0);
5530 if (num_negated
== 2)
5532 SUBST (XEXP (x
, 0), op0
);
5533 SUBST (XEXP (x
, 1), op1
);
5535 else if (num_negated
== 1)
5536 return gen_unary (NOT
, mode
, mode
, gen_binary (XOR
, mode
, op0
, op1
));
5539 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5540 correspond to a machine insn or result in further simplifications
5541 if B is a constant. */
5543 if (GET_CODE (op0
) == AND
5544 && rtx_equal_p (XEXP (op0
, 1), op1
)
5545 && ! side_effects_p (op1
))
5546 return gen_binary (AND
, mode
,
5547 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)),
5550 else if (GET_CODE (op0
) == AND
5551 && rtx_equal_p (XEXP (op0
, 0), op1
)
5552 && ! side_effects_p (op1
))
5553 return gen_binary (AND
, mode
,
5554 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)),
5557 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5558 comparison if STORE_FLAG_VALUE is 1. */
5559 if (STORE_FLAG_VALUE
== 1
5560 && op1
== const1_rtx
5561 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5562 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5566 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5567 is (lt foo (const_int 0)), so we can perform the above
5568 simplification if STORE_FLAG_VALUE is 1. */
5570 if (STORE_FLAG_VALUE
== 1
5571 && op1
== const1_rtx
5572 && GET_CODE (op0
) == LSHIFTRT
5573 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5574 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5575 return gen_rtx_combine (GE
, mode
, XEXP (op0
, 0), const0_rtx
);
5577 /* (xor (comparison foo bar) (const_int sign-bit))
5578 when STORE_FLAG_VALUE is the sign bit. */
5579 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5580 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5581 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5582 && op1
== const_true_rtx
5583 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5584 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5597 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5598 operations" because they can be replaced with two more basic operations.
5599 ZERO_EXTEND is also considered "compound" because it can be replaced with
5600 an AND operation, which is simpler, though only one operation.
5602 The function expand_compound_operation is called with an rtx expression
5603 and will convert it to the appropriate shifts and AND operations,
5604 simplifying at each stage.
5606 The function make_compound_operation is called to convert an expression
5607 consisting of shifts and ANDs into the equivalent compound expression.
5608 It is the inverse of this function, loosely speaking. */
5611 expand_compound_operation (x
)
5614 unsigned HOST_WIDE_INT pos
= 0, len
;
5616 unsigned int modewidth
;
5619 switch (GET_CODE (x
))
5624 /* We can't necessarily use a const_int for a multiword mode;
5625 it depends on implicitly extending the value.
5626 Since we don't know the right way to extend it,
5627 we can't tell whether the implicit way is right.
5629 Even for a mode that is no wider than a const_int,
5630 we can't win, because we need to sign extend one of its bits through
5631 the rest of it, and we don't know which bit. */
5632 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5635 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5636 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5637 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5638 reloaded. If not for that, MEM's would very rarely be safe.
5640 Reject MODEs bigger than a word, because we might not be able
5641 to reference a two-register group starting with an arbitrary register
5642 (and currently gen_lowpart might crash for a SUBREG). */
5644 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5647 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5648 /* If the inner object has VOIDmode (the only way this can happen
5649 is if it is a ASM_OPERANDS), we can't do anything since we don't
5650 know how much masking to do. */
5659 /* If the operand is a CLOBBER, just return it. */
5660 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5663 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5664 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5665 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5668 len
= INTVAL (XEXP (x
, 1));
5669 pos
= INTVAL (XEXP (x
, 2));
5671 /* If this goes outside the object being extracted, replace the object
5672 with a (use (mem ...)) construct that only combine understands
5673 and is used only for this purpose. */
5674 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5675 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5677 if (BITS_BIG_ENDIAN
)
5678 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5685 /* Convert sign extension to zero extension, if we know that the high
5686 bit is not set, as this is easier to optimize. It will be converted
5687 back to cheaper alternative in make_extraction. */
5688 if (GET_CODE (x
) == SIGN_EXTEND
5689 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5690 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5691 & ~(((unsigned HOST_WIDE_INT
)
5692 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5696 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5697 return expand_compound_operation (temp
);
5700 /* We can optimize some special cases of ZERO_EXTEND. */
5701 if (GET_CODE (x
) == ZERO_EXTEND
)
5703 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5704 know that the last value didn't have any inappropriate bits
5706 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5707 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5708 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5709 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5710 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5711 return XEXP (XEXP (x
, 0), 0);
5713 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5714 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5715 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5716 && subreg_lowpart_p (XEXP (x
, 0))
5717 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5718 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5719 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5720 return SUBREG_REG (XEXP (x
, 0));
5722 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5723 is a comparison and STORE_FLAG_VALUE permits. This is like
5724 the first case, but it works even when GET_MODE (x) is larger
5725 than HOST_WIDE_INT. */
5726 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5727 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5728 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5729 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5730 <= HOST_BITS_PER_WIDE_INT
)
5731 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5732 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5733 return XEXP (XEXP (x
, 0), 0);
5735 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5736 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5737 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5738 && subreg_lowpart_p (XEXP (x
, 0))
5739 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5740 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5741 <= HOST_BITS_PER_WIDE_INT
)
5742 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5743 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5744 return SUBREG_REG (XEXP (x
, 0));
5748 /* If we reach here, we want to return a pair of shifts. The inner
5749 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5750 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5751 logical depending on the value of UNSIGNEDP.
5753 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5754 converted into an AND of a shift.
5756 We must check for the case where the left shift would have a negative
5757 count. This can happen in a case like (x >> 31) & 255 on machines
5758 that can't shift by a constant. On those machines, we would first
5759 combine the shift with the AND to produce a variable-position
5760 extraction. Then the constant of 31 would be substituted in to produce
5761 a such a position. */
5763 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5764 if (modewidth
+ len
>= pos
)
5765 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5767 simplify_shift_const (NULL_RTX
, ASHIFT
,
5770 modewidth
- pos
- len
),
5773 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5774 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5775 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5778 ((HOST_WIDE_INT
) 1 << len
) - 1);
5780 /* Any other cases we can't handle. */
5783 /* If we couldn't do this for some reason, return the original
5785 if (GET_CODE (tem
) == CLOBBER
)
5791 /* X is a SET which contains an assignment of one object into
5792 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5793 or certain SUBREGS). If possible, convert it into a series of
5796 We half-heartedly support variable positions, but do not at all
5797 support variable lengths. */
5800 expand_field_assignment (x
)
5804 rtx pos
; /* Always counts from low bit. */
5807 enum machine_mode compute_mode
;
5809 /* Loop until we find something we can't simplify. */
5812 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5813 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5815 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5816 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5817 pos
= GEN_INT (BITS_PER_WORD
* SUBREG_WORD (XEXP (SET_DEST (x
), 0)));
5819 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5820 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5822 inner
= XEXP (SET_DEST (x
), 0);
5823 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5824 pos
= XEXP (SET_DEST (x
), 2);
5826 /* If the position is constant and spans the width of INNER,
5827 surround INNER with a USE to indicate this. */
5828 if (GET_CODE (pos
) == CONST_INT
5829 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5830 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5832 if (BITS_BIG_ENDIAN
)
5834 if (GET_CODE (pos
) == CONST_INT
)
5835 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5837 else if (GET_CODE (pos
) == MINUS
5838 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5839 && (INTVAL (XEXP (pos
, 1))
5840 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5841 /* If position is ADJUST - X, new position is X. */
5842 pos
= XEXP (pos
, 0);
5844 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5845 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5851 /* A SUBREG between two modes that occupy the same numbers of words
5852 can be done by moving the SUBREG to the source. */
5853 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5854 /* We need SUBREGs to compute nonzero_bits properly. */
5855 && nonzero_sign_valid
5856 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5857 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5858 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5859 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5861 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5862 gen_lowpart_for_combine
5863 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5870 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5871 inner
= SUBREG_REG (inner
);
5873 compute_mode
= GET_MODE (inner
);
5875 /* Don't attempt bitwise arithmetic on non-integral modes. */
5876 if (! INTEGRAL_MODE_P (compute_mode
))
5878 enum machine_mode imode
;
5880 /* Something is probably seriously wrong if this matches. */
5881 if (! FLOAT_MODE_P (compute_mode
))
5884 /* Try to find an integral mode to pun with. */
5885 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5886 if (imode
== BLKmode
)
5889 compute_mode
= imode
;
5890 inner
= gen_lowpart_for_combine (imode
, inner
);
5893 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5894 if (len
< HOST_BITS_PER_WIDE_INT
)
5895 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5899 /* Now compute the equivalent expression. Make a copy of INNER
5900 for the SET_DEST in case it is a MEM into which we will substitute;
5901 we don't want shared RTL in that case. */
5903 (VOIDmode
, copy_rtx (inner
),
5904 gen_binary (IOR
, compute_mode
,
5905 gen_binary (AND
, compute_mode
,
5906 gen_unary (NOT
, compute_mode
,
5912 gen_binary (ASHIFT
, compute_mode
,
5913 gen_binary (AND
, compute_mode
,
5914 gen_lowpart_for_combine
5915 (compute_mode
, SET_SRC (x
)),
5923 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5924 it is an RTX that represents a variable starting position; otherwise,
5925 POS is the (constant) starting bit position (counted from the LSB).
5927 INNER may be a USE. This will occur when we started with a bitfield
5928 that went outside the boundary of the object in memory, which is
5929 allowed on most machines. To isolate this case, we produce a USE
5930 whose mode is wide enough and surround the MEM with it. The only
5931 code that understands the USE is this routine. If it is not removed,
5932 it will cause the resulting insn not to match.
5934 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5937 IN_DEST is non-zero if this is a reference in the destination of a
5938 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5939 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5942 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5943 ZERO_EXTRACT should be built even for bits starting at bit 0.
5945 MODE is the desired mode of the result (if IN_DEST == 0).
5947 The result is an RTX for the extraction or NULL_RTX if the target
5951 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
5952 unsignedp
, in_dest
, in_compare
)
5953 enum machine_mode mode
;
5957 unsigned HOST_WIDE_INT len
;
5959 int in_dest
, in_compare
;
5961 /* This mode describes the size of the storage area
5962 to fetch the overall value from. Within that, we
5963 ignore the POS lowest bits, etc. */
5964 enum machine_mode is_mode
= GET_MODE (inner
);
5965 enum machine_mode inner_mode
;
5966 enum machine_mode wanted_inner_mode
= byte_mode
;
5967 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5968 enum machine_mode pos_mode
= word_mode
;
5969 enum machine_mode extraction_mode
= word_mode
;
5970 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5973 rtx orig_pos_rtx
= pos_rtx
;
5974 HOST_WIDE_INT orig_pos
;
5976 /* Get some information about INNER and get the innermost object. */
5977 if (GET_CODE (inner
) == USE
)
5978 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5979 /* We don't need to adjust the position because we set up the USE
5980 to pretend that it was a full-word object. */
5981 spans_byte
= 1, inner
= XEXP (inner
, 0);
5982 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5984 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5985 consider just the QI as the memory to extract from.
5986 The subreg adds or removes high bits; its mode is
5987 irrelevant to the meaning of this extraction,
5988 since POS and LEN count from the lsb. */
5989 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5990 is_mode
= GET_MODE (SUBREG_REG (inner
));
5991 inner
= SUBREG_REG (inner
);
5994 inner_mode
= GET_MODE (inner
);
5996 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5997 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5999 /* See if this can be done without an extraction. We never can if the
6000 width of the field is not the same as that of some integer mode. For
6001 registers, we can only avoid the extraction if the position is at the
6002 low-order bit and this is either not in the destination or we have the
6003 appropriate STRICT_LOW_PART operation available.
6005 For MEM, we can avoid an extract if the field starts on an appropriate
6006 boundary and we can change the mode of the memory reference. However,
6007 we cannot directly access the MEM if we have a USE and the underlying
6008 MEM is not TMODE. This combination means that MEM was being used in a
6009 context where bits outside its mode were being referenced; that is only
6010 valid in bit-field insns. */
6012 if (tmode
!= BLKmode
6013 && ! (spans_byte
&& inner_mode
!= tmode
)
6014 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6015 && GET_CODE (inner
) != MEM
6017 || (GET_CODE (inner
) == REG
6018 && (movstrict_optab
->handlers
[(int) tmode
].insn_code
6019 != CODE_FOR_nothing
))))
6020 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6022 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6023 : BITS_PER_UNIT
)) == 0
6024 /* We can't do this if we are widening INNER_MODE (it
6025 may not be aligned, for one thing). */
6026 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6027 && (inner_mode
== tmode
6028 || (! mode_dependent_address_p (XEXP (inner
, 0))
6029 && ! MEM_VOLATILE_P (inner
))))))
6031 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6032 field. If the original and current mode are the same, we need not
6033 adjust the offset. Otherwise, we do if bytes big endian.
6035 If INNER is not a MEM, get a piece consisting of just the field
6036 of interest (in this case POS % BITS_PER_WORD must be 0). */
6038 if (GET_CODE (inner
) == MEM
)
6041 /* POS counts from lsb, but make OFFSET count in memory order. */
6042 if (BYTES_BIG_ENDIAN
)
6043 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6045 offset
= pos
/ BITS_PER_UNIT
;
6047 new = gen_rtx_MEM (tmode
, plus_constant (XEXP (inner
, 0), offset
));
6048 MEM_COPY_ATTRIBUTES (new, inner
);
6050 else if (GET_CODE (inner
) == REG
)
6052 /* We can't call gen_lowpart_for_combine here since we always want
6053 a SUBREG and it would sometimes return a new hard register. */
6054 if (tmode
!= inner_mode
)
6055 new = gen_rtx_SUBREG (tmode
, inner
,
6057 && (GET_MODE_SIZE (inner_mode
)
6059 ? (((GET_MODE_SIZE (inner_mode
)
6060 - GET_MODE_SIZE (tmode
))
6062 - pos
/ BITS_PER_WORD
)
6063 : pos
/ BITS_PER_WORD
));
6068 new = force_to_mode (inner
, tmode
,
6069 len
>= HOST_BITS_PER_WIDE_INT
6070 ? ~(unsigned HOST_WIDE_INT
) 0
6071 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6074 /* If this extraction is going into the destination of a SET,
6075 make a STRICT_LOW_PART unless we made a MEM. */
6078 return (GET_CODE (new) == MEM
? new
6079 : (GET_CODE (new) != SUBREG
6080 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6081 : gen_rtx_combine (STRICT_LOW_PART
, VOIDmode
, new)));
6086 /* If we know that no extraneous bits are set, and that the high
6087 bit is not set, convert the extraction to the cheaper of
6088 sign and zero extension, that are equivalent in these cases. */
6089 if (flag_expensive_optimizations
6090 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6091 && ((nonzero_bits (new, tmode
)
6092 & ~(((unsigned HOST_WIDE_INT
)
6093 GET_MODE_MASK (tmode
))
6097 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6098 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6100 /* Prefer ZERO_EXTENSION, since it gives more information to
6102 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6107 /* Otherwise, sign- or zero-extend unless we already are in the
6110 return (gen_rtx_combine (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6114 /* Unless this is a COMPARE or we have a funny memory reference,
6115 don't do anything with zero-extending field extracts starting at
6116 the low-order bit since they are simple AND operations. */
6117 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6118 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6121 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6122 we would be spanning bytes or if the position is not a constant and the
6123 length is not 1. In all other cases, we would only be going outside
6124 our object in cases when an original shift would have been
6126 if (! spans_byte
&& GET_CODE (inner
) == MEM
6127 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6128 || (pos_rtx
!= 0 && len
!= 1)))
6131 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6132 and the mode for the result. */
6136 wanted_inner_reg_mode
6137 = insn_data
[(int) CODE_FOR_insv
].operand
[0].mode
;
6138 if (wanted_inner_reg_mode
== VOIDmode
)
6139 wanted_inner_reg_mode
= word_mode
;
6141 pos_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[2].mode
;
6142 if (pos_mode
== VOIDmode
)
6143 pos_mode
= word_mode
;
6145 extraction_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[3].mode
;
6146 if (extraction_mode
== VOIDmode
)
6147 extraction_mode
= word_mode
;
6152 if (! in_dest
&& unsignedp
)
6154 wanted_inner_reg_mode
6155 = insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
6156 if (wanted_inner_reg_mode
== VOIDmode
)
6157 wanted_inner_reg_mode
= word_mode
;
6159 pos_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[3].mode
;
6160 if (pos_mode
== VOIDmode
)
6161 pos_mode
= word_mode
;
6163 extraction_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[0].mode
;
6164 if (extraction_mode
== VOIDmode
)
6165 extraction_mode
= word_mode
;
6170 if (! in_dest
&& ! unsignedp
)
6172 wanted_inner_reg_mode
6173 = insn_data
[(int) CODE_FOR_extv
].operand
[1].mode
;
6174 if (wanted_inner_reg_mode
== VOIDmode
)
6175 wanted_inner_reg_mode
= word_mode
;
6177 pos_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[3].mode
;
6178 if (pos_mode
== VOIDmode
)
6179 pos_mode
= word_mode
;
6181 extraction_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[0].mode
;
6182 if (extraction_mode
== VOIDmode
)
6183 extraction_mode
= word_mode
;
6187 /* Never narrow an object, since that might not be safe. */
6189 if (mode
!= VOIDmode
6190 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6191 extraction_mode
= mode
;
6193 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6194 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6195 pos_mode
= GET_MODE (pos_rtx
);
6197 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6198 if we have to change the mode of memory and cannot, the desired mode is
6200 if (GET_CODE (inner
) != MEM
)
6201 wanted_inner_mode
= wanted_inner_reg_mode
;
6202 else if (inner_mode
!= wanted_inner_mode
6203 && (mode_dependent_address_p (XEXP (inner
, 0))
6204 || MEM_VOLATILE_P (inner
)))
6205 wanted_inner_mode
= extraction_mode
;
6209 if (BITS_BIG_ENDIAN
)
6211 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6212 BITS_BIG_ENDIAN style. If position is constant, compute new
6213 position. Otherwise, build subtraction.
6214 Note that POS is relative to the mode of the original argument.
6215 If it's a MEM we need to recompute POS relative to that.
6216 However, if we're extracting from (or inserting into) a register,
6217 we want to recompute POS relative to wanted_inner_mode. */
6218 int width
= (GET_CODE (inner
) == MEM
6219 ? GET_MODE_BITSIZE (is_mode
)
6220 : GET_MODE_BITSIZE (wanted_inner_mode
));
6223 pos
= width
- len
- pos
;
6226 = gen_rtx_combine (MINUS
, GET_MODE (pos_rtx
),
6227 GEN_INT (width
- len
), pos_rtx
);
6228 /* POS may be less than 0 now, but we check for that below.
6229 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6232 /* If INNER has a wider mode, make it smaller. If this is a constant
6233 extract, try to adjust the byte to point to the byte containing
6235 if (wanted_inner_mode
!= VOIDmode
6236 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6237 && ((GET_CODE (inner
) == MEM
6238 && (inner_mode
== wanted_inner_mode
6239 || (! mode_dependent_address_p (XEXP (inner
, 0))
6240 && ! MEM_VOLATILE_P (inner
))))))
6244 /* The computations below will be correct if the machine is big
6245 endian in both bits and bytes or little endian in bits and bytes.
6246 If it is mixed, we must adjust. */
6248 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6249 adjust OFFSET to compensate. */
6250 if (BYTES_BIG_ENDIAN
6252 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6253 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6255 /* If this is a constant position, we can move to the desired byte. */
6258 offset
+= pos
/ BITS_PER_UNIT
;
6259 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6262 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6264 && is_mode
!= wanted_inner_mode
)
6265 offset
= (GET_MODE_SIZE (is_mode
)
6266 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6268 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6270 rtx newmem
= gen_rtx_MEM (wanted_inner_mode
,
6271 plus_constant (XEXP (inner
, 0), offset
));
6273 MEM_COPY_ATTRIBUTES (newmem
, inner
);
6278 /* If INNER is not memory, we can always get it into the proper mode. If we
6279 are changing its mode, POS must be a constant and smaller than the size
6281 else if (GET_CODE (inner
) != MEM
)
6283 if (GET_MODE (inner
) != wanted_inner_mode
6285 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6288 inner
= force_to_mode (inner
, wanted_inner_mode
,
6290 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6291 ? ~(unsigned HOST_WIDE_INT
) 0
6292 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6297 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6298 have to zero extend. Otherwise, we can just use a SUBREG. */
6300 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6302 rtx temp
= gen_rtx_combine (ZERO_EXTEND
, pos_mode
, pos_rtx
);
6304 /* If we know that no extraneous bits are set, and that the high
6305 bit is not set, convert extraction to cheaper one - eighter
6306 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6308 if (flag_expensive_optimizations
6309 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6310 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6311 & ~(((unsigned HOST_WIDE_INT
)
6312 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6316 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6318 /* Prefer ZERO_EXTENSION, since it gives more information to
6320 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6325 else if (pos_rtx
!= 0
6326 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6327 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6329 /* Make POS_RTX unless we already have it and it is correct. If we don't
6330 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6332 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6333 pos_rtx
= orig_pos_rtx
;
6335 else if (pos_rtx
== 0)
6336 pos_rtx
= GEN_INT (pos
);
6338 /* Make the required operation. See if we can use existing rtx. */
6339 new = gen_rtx_combine (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6340 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6342 new = gen_lowpart_for_combine (mode
, new);
6347 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6348 with any other operations in X. Return X without that shift if so. */
6351 extract_left_shift (x
, count
)
6355 enum rtx_code code
= GET_CODE (x
);
6356 enum machine_mode mode
= GET_MODE (x
);
6362 /* This is the shift itself. If it is wide enough, we will return
6363 either the value being shifted if the shift count is equal to
6364 COUNT or a shift for the difference. */
6365 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6366 && INTVAL (XEXP (x
, 1)) >= count
)
6367 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6368 INTVAL (XEXP (x
, 1)) - count
);
6372 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6373 return gen_unary (code
, mode
, mode
, tem
);
6377 case PLUS
: case IOR
: case XOR
: case AND
:
6378 /* If we can safely shift this constant and we find the inner shift,
6379 make a new operation. */
6380 if (GET_CODE (XEXP (x
,1)) == CONST_INT
6381 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6382 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6383 return gen_binary (code
, mode
, tem
,
6384 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6395 /* Look at the expression rooted at X. Look for expressions
6396 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6397 Form these expressions.
6399 Return the new rtx, usually just X.
6401 Also, for machines like the Vax that don't have logical shift insns,
6402 try to convert logical to arithmetic shift operations in cases where
6403 they are equivalent. This undoes the canonicalizations to logical
6404 shifts done elsewhere.
6406 We try, as much as possible, to re-use rtl expressions to save memory.
6408 IN_CODE says what kind of expression we are processing. Normally, it is
6409 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6410 being kludges), it is MEM. When processing the arguments of a comparison
6411 or a COMPARE against zero, it is COMPARE. */
6414 make_compound_operation (x
, in_code
)
6416 enum rtx_code in_code
;
6418 enum rtx_code code
= GET_CODE (x
);
6419 enum machine_mode mode
= GET_MODE (x
);
6420 int mode_width
= GET_MODE_BITSIZE (mode
);
6422 enum rtx_code next_code
;
6428 /* Select the code to be used in recursive calls. Once we are inside an
6429 address, we stay there. If we have a comparison, set to COMPARE,
6430 but once inside, go back to our default of SET. */
6432 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6433 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6434 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6435 : in_code
== COMPARE
? SET
: in_code
);
6437 /* Process depending on the code of this operation. If NEW is set
6438 non-zero, it will be returned. */
6443 /* Convert shifts by constants into multiplications if inside
6445 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6446 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6447 && INTVAL (XEXP (x
, 1)) >= 0)
6449 new = make_compound_operation (XEXP (x
, 0), next_code
);
6450 new = gen_rtx_combine (MULT
, mode
, new,
6451 GEN_INT ((HOST_WIDE_INT
) 1
6452 << INTVAL (XEXP (x
, 1))));
6457 /* If the second operand is not a constant, we can't do anything
6459 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6462 /* If the constant is a power of two minus one and the first operand
6463 is a logical right shift, make an extraction. */
6464 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6465 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6467 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6468 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6469 0, in_code
== COMPARE
);
6472 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6473 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6474 && subreg_lowpart_p (XEXP (x
, 0))
6475 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6476 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6478 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6480 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6481 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6482 0, in_code
== COMPARE
);
6484 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6485 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6486 || GET_CODE (XEXP (x
, 0)) == IOR
)
6487 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6488 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6489 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6491 /* Apply the distributive law, and then try to make extractions. */
6492 new = gen_rtx_combine (GET_CODE (XEXP (x
, 0)), mode
,
6493 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6495 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6497 new = make_compound_operation (new, in_code
);
6500 /* If we are have (and (rotate X C) M) and C is larger than the number
6501 of bits in M, this is an extraction. */
6503 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6504 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6505 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6506 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6508 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6509 new = make_extraction (mode
, new,
6510 (GET_MODE_BITSIZE (mode
)
6511 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6512 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6515 /* On machines without logical shifts, if the operand of the AND is
6516 a logical shift and our mask turns off all the propagated sign
6517 bits, we can replace the logical shift with an arithmetic shift. */
6518 else if (ashr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6519 && (lshr_optab
->handlers
[(int) mode
].insn_code
6520 == CODE_FOR_nothing
)
6521 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6522 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6523 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6524 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6525 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6527 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6529 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6530 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6532 gen_rtx_combine (ASHIFTRT
, mode
,
6533 make_compound_operation (XEXP (XEXP (x
, 0), 0),
6535 XEXP (XEXP (x
, 0), 1)));
6538 /* If the constant is one less than a power of two, this might be
6539 representable by an extraction even if no shift is present.
6540 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6541 we are in a COMPARE. */
6542 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6543 new = make_extraction (mode
,
6544 make_compound_operation (XEXP (x
, 0),
6546 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6548 /* If we are in a comparison and this is an AND with a power of two,
6549 convert this into the appropriate bit extract. */
6550 else if (in_code
== COMPARE
6551 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6552 new = make_extraction (mode
,
6553 make_compound_operation (XEXP (x
, 0),
6555 i
, NULL_RTX
, 1, 1, 0, 1);
6560 /* If the sign bit is known to be zero, replace this with an
6561 arithmetic shift. */
6562 if (ashr_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
6563 && lshr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6564 && mode_width
<= HOST_BITS_PER_WIDE_INT
6565 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6567 new = gen_rtx_combine (ASHIFTRT
, mode
,
6568 make_compound_operation (XEXP (x
, 0),
6574 /* ... fall through ... */
6580 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6581 this is a SIGN_EXTRACT. */
6582 if (GET_CODE (rhs
) == CONST_INT
6583 && GET_CODE (lhs
) == ASHIFT
6584 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6585 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6587 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6588 new = make_extraction (mode
, new,
6589 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6590 NULL_RTX
, mode_width
- INTVAL (rhs
),
6591 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6595 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6596 If so, try to merge the shifts into a SIGN_EXTEND. We could
6597 also do this for some cases of SIGN_EXTRACT, but it doesn't
6598 seem worth the effort; the case checked for occurs on Alpha. */
6600 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6601 && ! (GET_CODE (lhs
) == SUBREG
6602 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6603 && GET_CODE (rhs
) == CONST_INT
6604 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6605 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6606 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6607 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6608 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6613 /* Call ourselves recursively on the inner expression. If we are
6614 narrowing the object and it has a different RTL code from
6615 what it originally did, do this SUBREG as a force_to_mode. */
6617 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6618 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6619 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6620 && subreg_lowpart_p (x
))
6622 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6625 /* If we have something other than a SUBREG, we might have
6626 done an expansion, so rerun outselves. */
6627 if (GET_CODE (newer
) != SUBREG
)
6628 newer
= make_compound_operation (newer
, in_code
);
6633 /* If this is a paradoxical subreg, and the new code is a sign or
6634 zero extension, omit the subreg and widen the extension. If it
6635 is a regular subreg, we can still get rid of the subreg by not
6636 widening so much, or in fact removing the extension entirely. */
6637 if ((GET_CODE (tem
) == SIGN_EXTEND
6638 || GET_CODE (tem
) == ZERO_EXTEND
)
6639 && subreg_lowpart_p (x
))
6641 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6642 || (GET_MODE_SIZE (mode
) >
6643 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6644 tem
= gen_rtx_combine (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6646 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6657 x
= gen_lowpart_for_combine (mode
, new);
6658 code
= GET_CODE (x
);
6661 /* Now recursively process each operand of this operation. */
6662 fmt
= GET_RTX_FORMAT (code
);
6663 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6666 new = make_compound_operation (XEXP (x
, i
), next_code
);
6667 SUBST (XEXP (x
, i
), new);
6673 /* Given M see if it is a value that would select a field of bits
6674 within an item, but not the entire word. Return -1 if not.
6675 Otherwise, return the starting position of the field, where 0 is the
6678 *PLEN is set to the length of the field. */
6681 get_pos_from_mask (m
, plen
)
6682 unsigned HOST_WIDE_INT m
;
6683 unsigned HOST_WIDE_INT
*plen
;
6685 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6686 int pos
= exact_log2 (m
& -m
);
6692 /* Now shift off the low-order zero bits and see if we have a power of
6694 len
= exact_log2 ((m
>> pos
) + 1);
6703 /* See if X can be simplified knowing that we will only refer to it in
6704 MODE and will only refer to those bits that are nonzero in MASK.
6705 If other bits are being computed or if masking operations are done
6706 that select a superset of the bits in MASK, they can sometimes be
6709 Return a possibly simplified expression, but always convert X to
6710 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6712 Also, if REG is non-zero and X is a register equal in value to REG,
6715 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6716 are all off in X. This is used when X will be complemented, by either
6717 NOT, NEG, or XOR. */
6720 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6722 enum machine_mode mode
;
6723 unsigned HOST_WIDE_INT mask
;
6727 enum rtx_code code
= GET_CODE (x
);
6728 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6729 enum machine_mode op_mode
;
6730 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6733 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6734 code below will do the wrong thing since the mode of such an
6735 expression is VOIDmode.
6737 Also do nothing if X is a CLOBBER; this can happen if X was
6738 the return value from a call to gen_lowpart_for_combine. */
6739 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6742 /* We want to perform the operation is its present mode unless we know
6743 that the operation is valid in MODE, in which case we do the operation
6745 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6746 && code_to_optab
[(int) code
] != 0
6747 && (code_to_optab
[(int) code
]->handlers
[(int) mode
].insn_code
6748 != CODE_FOR_nothing
))
6749 ? mode
: GET_MODE (x
));
6751 /* It is not valid to do a right-shift in a narrower mode
6752 than the one it came in with. */
6753 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6754 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6755 op_mode
= GET_MODE (x
);
6757 /* Truncate MASK to fit OP_MODE. */
6759 mask
&= GET_MODE_MASK (op_mode
);
6761 /* When we have an arithmetic operation, or a shift whose count we
6762 do not know, we need to assume that all bit the up to the highest-order
6763 bit in MASK will be needed. This is how we form such a mask. */
6765 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6766 ? GET_MODE_MASK (op_mode
)
6767 : (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6770 fuller_mask
= ~(HOST_WIDE_INT
) 0;
6772 /* Determine what bits of X are guaranteed to be (non)zero. */
6773 nonzero
= nonzero_bits (x
, mode
);
6775 /* If none of the bits in X are needed, return a zero. */
6776 if (! just_select
&& (nonzero
& mask
) == 0)
6779 /* If X is a CONST_INT, return a new one. Do this here since the
6780 test below will fail. */
6781 if (GET_CODE (x
) == CONST_INT
)
6783 HOST_WIDE_INT cval
= INTVAL (x
) & mask
;
6784 int width
= GET_MODE_BITSIZE (mode
);
6786 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6787 number, sign extend it. */
6788 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6789 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6790 cval
|= (HOST_WIDE_INT
) -1 << width
;
6792 return GEN_INT (cval
);
6795 /* If X is narrower than MODE and we want all the bits in X's mode, just
6796 get X in the proper mode. */
6797 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6798 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6799 return gen_lowpart_for_combine (mode
, x
);
6801 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6802 MASK are already known to be zero in X, we need not do anything. */
6803 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6809 /* If X is a (clobber (const_int)), return it since we know we are
6810 generating something that won't match. */
6814 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6815 spanned the boundary of the MEM. If we are now masking so it is
6816 within that boundary, we don't need the USE any more. */
6817 if (! BITS_BIG_ENDIAN
6818 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6819 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6826 x
= expand_compound_operation (x
);
6827 if (GET_CODE (x
) != code
)
6828 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6832 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6833 || rtx_equal_p (reg
, get_last_value (x
))))
6838 if (subreg_lowpart_p (x
)
6839 /* We can ignore the effect of this SUBREG if it narrows the mode or
6840 if the constant masks to zero all the bits the mode doesn't
6842 && ((GET_MODE_SIZE (GET_MODE (x
))
6843 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6845 & GET_MODE_MASK (GET_MODE (x
))
6846 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6847 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6851 /* If this is an AND with a constant, convert it into an AND
6852 whose constant is the AND of that constant with MASK. If it
6853 remains an AND of MASK, delete it since it is redundant. */
6855 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6857 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6858 mask
& INTVAL (XEXP (x
, 1)));
6860 /* If X is still an AND, see if it is an AND with a mask that
6861 is just some low-order bits. If so, and it is MASK, we don't
6864 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6865 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == mask
)
6868 /* If it remains an AND, try making another AND with the bits
6869 in the mode mask that aren't in MASK turned on. If the
6870 constant in the AND is wide enough, this might make a
6871 cheaper constant. */
6873 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6874 && GET_MODE_MASK (GET_MODE (x
)) != mask
6875 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6877 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6878 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6879 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6882 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6883 number, sign extend it. */
6884 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6885 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6886 cval
|= (HOST_WIDE_INT
) -1 << width
;
6888 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6889 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6899 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6900 low-order bits (as in an alignment operation) and FOO is already
6901 aligned to that boundary, mask C1 to that boundary as well.
6902 This may eliminate that PLUS and, later, the AND. */
6905 unsigned int width
= GET_MODE_BITSIZE (mode
);
6906 unsigned HOST_WIDE_INT smask
= mask
;
6908 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6909 number, sign extend it. */
6911 if (width
< HOST_BITS_PER_WIDE_INT
6912 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6913 smask
|= (HOST_WIDE_INT
) -1 << width
;
6915 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6916 && exact_log2 (- smask
) >= 0)
6920 && (XEXP (x
, 0) == stack_pointer_rtx
6921 || XEXP (x
, 0) == frame_pointer_rtx
))
6923 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6924 unsigned HOST_WIDE_INT sp_mask
= GET_MODE_MASK (mode
);
6926 sp_mask
&= ~(sp_alignment
- 1);
6927 if ((sp_mask
& ~smask
) == 0
6928 && ((INTVAL (XEXP (x
, 1)) - STACK_BIAS
) & ~smask
) != 0)
6929 return force_to_mode (plus_constant (XEXP (x
, 0),
6930 ((INTVAL (XEXP (x
, 1)) -
6931 STACK_BIAS
) & smask
)
6933 mode
, smask
, reg
, next_select
);
6936 if ((nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6937 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6938 return force_to_mode (plus_constant (XEXP (x
, 0),
6939 (INTVAL (XEXP (x
, 1))
6941 mode
, smask
, reg
, next_select
);
6945 /* ... fall through ... */
6948 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6949 most significant bit in MASK since carries from those bits will
6950 affect the bits we are interested in. */
6955 /* If X is (minus C Y) where C's least set bit is larger than any bit
6956 in the mask, then we may replace with (neg Y). */
6957 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6958 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6959 & -INTVAL (XEXP (x
, 0))))
6962 x
= gen_unary (NEG
, GET_MODE (x
), GET_MODE (x
), XEXP (x
, 1));
6963 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6966 /* Similarly, if C contains every bit in the mask, then we may
6967 replace with (not Y). */
6968 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6969 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) mask
)
6970 == INTVAL (XEXP (x
, 0))))
6972 x
= gen_unary (NOT
, GET_MODE (x
), GET_MODE (x
), XEXP (x
, 1));
6973 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6981 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6982 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6983 operation which may be a bitfield extraction. Ensure that the
6984 constant we form is not wider than the mode of X. */
6986 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6987 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6988 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6989 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6990 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6991 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6992 + floor_log2 (INTVAL (XEXP (x
, 1))))
6993 < GET_MODE_BITSIZE (GET_MODE (x
)))
6994 && (INTVAL (XEXP (x
, 1))
6995 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6997 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6998 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6999 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
7000 XEXP (XEXP (x
, 0), 0), temp
);
7001 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
7002 XEXP (XEXP (x
, 0), 1));
7003 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7007 /* For most binary operations, just propagate into the operation and
7008 change the mode if we have an operation of that mode. */
7010 op0
= gen_lowpart_for_combine (op_mode
,
7011 force_to_mode (XEXP (x
, 0), mode
, mask
,
7013 op1
= gen_lowpart_for_combine (op_mode
,
7014 force_to_mode (XEXP (x
, 1), mode
, mask
,
7017 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
7018 MASK since OP1 might have been sign-extended but we never want
7019 to turn on extra bits, since combine might have previously relied
7020 on them being off. */
7021 if (GET_CODE (op1
) == CONST_INT
&& (code
== IOR
|| code
== XOR
)
7022 && (INTVAL (op1
) & mask
) != 0)
7023 op1
= GEN_INT (INTVAL (op1
) & mask
);
7025 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7026 x
= gen_binary (code
, op_mode
, op0
, op1
);
7030 /* For left shifts, do the same, but just for the first operand.
7031 However, we cannot do anything with shifts where we cannot
7032 guarantee that the counts are smaller than the size of the mode
7033 because such a count will have a different meaning in a
7036 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
7037 && INTVAL (XEXP (x
, 1)) >= 0
7038 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
7039 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
7040 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
7041 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
7044 /* If the shift count is a constant and we can do arithmetic in
7045 the mode of the shift, refine which bits we need. Otherwise, use the
7046 conservative form of the mask. */
7047 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7048 && INTVAL (XEXP (x
, 1)) >= 0
7049 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
7050 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7051 mask
>>= INTVAL (XEXP (x
, 1));
7055 op0
= gen_lowpart_for_combine (op_mode
,
7056 force_to_mode (XEXP (x
, 0), op_mode
,
7057 mask
, reg
, next_select
));
7059 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7060 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7064 /* Here we can only do something if the shift count is a constant,
7065 this shift constant is valid for the host, and we can do arithmetic
7068 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7069 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7070 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7072 rtx inner
= XEXP (x
, 0);
7073 unsigned HOST_WIDE_INT inner_mask
;
7075 /* Select the mask of the bits we need for the shift operand. */
7076 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7078 /* We can only change the mode of the shift if we can do arithmetic
7079 in the mode of the shift and INNER_MASK is no wider than the
7080 width of OP_MODE. */
7081 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7082 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7083 op_mode
= GET_MODE (x
);
7085 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7087 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7088 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7091 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7092 shift and AND produces only copies of the sign bit (C2 is one less
7093 than a power of two), we can do this with just a shift. */
7095 if (GET_CODE (x
) == LSHIFTRT
7096 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7097 /* The shift puts one of the sign bit copies in the least significant
7099 && ((INTVAL (XEXP (x
, 1))
7100 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7101 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7102 && exact_log2 (mask
+ 1) >= 0
7103 /* Number of bits left after the shift must be more than the mask
7105 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7106 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7107 /* Must be more sign bit copies than the mask needs. */
7108 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7109 >= exact_log2 (mask
+ 1)))
7110 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7111 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7112 - exact_log2 (mask
+ 1)));
7117 /* If we are just looking for the sign bit, we don't need this shift at
7118 all, even if it has a variable count. */
7119 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7120 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7121 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7122 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7124 /* If this is a shift by a constant, get a mask that contains those bits
7125 that are not copies of the sign bit. We then have two cases: If
7126 MASK only includes those bits, this can be a logical shift, which may
7127 allow simplifications. If MASK is a single-bit field not within
7128 those bits, we are requesting a copy of the sign bit and hence can
7129 shift the sign bit to the appropriate location. */
7131 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7132 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7136 /* If the considered data is wider then HOST_WIDE_INT, we can't
7137 represent a mask for all its bits in a single scalar.
7138 But we only care about the lower bits, so calculate these. */
7140 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7142 nonzero
= ~(HOST_WIDE_INT
) 0;
7144 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7145 is the number of bits a full-width mask would have set.
7146 We need only shift if these are fewer than nonzero can
7147 hold. If not, we must keep all bits set in nonzero. */
7149 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7150 < HOST_BITS_PER_WIDE_INT
)
7151 nonzero
>>= INTVAL (XEXP (x
, 1))
7152 + HOST_BITS_PER_WIDE_INT
7153 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7157 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7158 nonzero
>>= INTVAL (XEXP (x
, 1));
7161 if ((mask
& ~nonzero
) == 0
7162 || (i
= exact_log2 (mask
)) >= 0)
7164 x
= simplify_shift_const
7165 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7166 i
< 0 ? INTVAL (XEXP (x
, 1))
7167 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7169 if (GET_CODE (x
) != ASHIFTRT
)
7170 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7174 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7175 even if the shift count isn't a constant. */
7177 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7181 /* If this is a zero- or sign-extension operation that just affects bits
7182 we don't care about, remove it. Be sure the call above returned
7183 something that is still a shift. */
7185 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7186 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7187 && INTVAL (XEXP (x
, 1)) >= 0
7188 && (INTVAL (XEXP (x
, 1))
7189 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7190 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7191 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7192 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
7193 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7200 /* If the shift count is constant and we can do computations
7201 in the mode of X, compute where the bits we care about are.
7202 Otherwise, we can't do anything. Don't change the mode of
7203 the shift or propagate MODE into the shift, though. */
7204 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7205 && INTVAL (XEXP (x
, 1)) >= 0)
7207 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7208 GET_MODE (x
), GEN_INT (mask
),
7210 if (temp
&& GET_CODE(temp
) == CONST_INT
)
7212 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7213 INTVAL (temp
), reg
, next_select
));
7218 /* If we just want the low-order bit, the NEG isn't needed since it
7219 won't change the low-order bit. */
7221 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7223 /* We need any bits less significant than the most significant bit in
7224 MASK since carries from those bits will affect the bits we are
7230 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7231 same as the XOR case above. Ensure that the constant we form is not
7232 wider than the mode of X. */
7234 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7235 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7236 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7237 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7238 < GET_MODE_BITSIZE (GET_MODE (x
)))
7239 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7241 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
7242 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7243 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7245 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7248 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7249 use the full mask inside the NOT. */
7253 op0
= gen_lowpart_for_combine (op_mode
,
7254 force_to_mode (XEXP (x
, 0), mode
, mask
,
7256 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7257 x
= gen_unary (code
, op_mode
, op_mode
, op0
);
7261 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7262 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7263 which is equal to STORE_FLAG_VALUE. */
7264 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7265 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7266 && nonzero_bits (XEXP (x
, 0), mode
) == STORE_FLAG_VALUE
)
7267 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7272 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7273 written in a narrower mode. We play it safe and do not do so. */
7276 gen_lowpart_for_combine (GET_MODE (x
),
7277 force_to_mode (XEXP (x
, 1), mode
,
7278 mask
, reg
, next_select
)));
7280 gen_lowpart_for_combine (GET_MODE (x
),
7281 force_to_mode (XEXP (x
, 2), mode
,
7282 mask
, reg
,next_select
)));
7289 /* Ensure we return a value of the proper mode. */
7290 return gen_lowpart_for_combine (mode
, x
);
7293 /* Return nonzero if X is an expression that has one of two values depending on
7294 whether some other value is zero or nonzero. In that case, we return the
7295 value that is being tested, *PTRUE is set to the value if the rtx being
7296 returned has a nonzero value, and *PFALSE is set to the other alternative.
7298 If we return zero, we set *PTRUE and *PFALSE to X. */
7301 if_then_else_cond (x
, ptrue
, pfalse
)
7303 rtx
*ptrue
, *pfalse
;
7305 enum machine_mode mode
= GET_MODE (x
);
7306 enum rtx_code code
= GET_CODE (x
);
7307 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7308 unsigned HOST_WIDE_INT nz
;
7310 /* If we are comparing a value against zero, we are done. */
7311 if ((code
== NE
|| code
== EQ
)
7312 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 0)
7314 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7315 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7319 /* If this is a unary operation whose operand has one of two values, apply
7320 our opcode to compute those values. */
7321 else if (GET_RTX_CLASS (code
) == '1'
7322 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7324 *ptrue
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), true0
);
7325 *pfalse
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), false0
);
7329 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7330 make can't possibly match and would suppress other optimizations. */
7331 else if (code
== COMPARE
)
7334 /* If this is a binary operation, see if either side has only one of two
7335 values. If either one does or if both do and they are conditional on
7336 the same value, compute the new true and false values. */
7337 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7338 || GET_RTX_CLASS (code
) == '<')
7340 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7341 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7343 if ((cond0
!= 0 || cond1
!= 0)
7344 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7346 /* If if_then_else_cond returned zero, then true/false are the
7347 same rtl. We must copy one of them to prevent invalid rtl
7350 true0
= copy_rtx (true0
);
7351 else if (cond1
== 0)
7352 true1
= copy_rtx (true1
);
7354 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7355 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7356 return cond0
? cond0
: cond1
;
7359 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7360 operands is zero when the other is non-zero, and vice-versa,
7361 and STORE_FLAG_VALUE is 1 or -1. */
7363 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7364 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7366 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7368 rtx op0
= XEXP (XEXP (x
, 0), 1);
7369 rtx op1
= XEXP (XEXP (x
, 1), 1);
7371 cond0
= XEXP (XEXP (x
, 0), 0);
7372 cond1
= XEXP (XEXP (x
, 1), 0);
7374 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7375 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7376 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7377 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7378 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7379 || ((swap_condition (GET_CODE (cond0
))
7380 == combine_reversed_comparison_code (cond1
))
7381 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7382 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7383 && ! side_effects_p (x
))
7385 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7386 *pfalse
= gen_binary (MULT
, mode
,
7388 ? gen_unary (NEG
, mode
, mode
, op1
) : op1
),
7394 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7396 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7397 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7398 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7400 cond0
= XEXP (XEXP (x
, 0), 0);
7401 cond1
= XEXP (XEXP (x
, 1), 0);
7403 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7404 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7405 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7406 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7407 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7408 || ((swap_condition (GET_CODE (cond0
))
7409 == combine_reversed_comparison_code (cond1
))
7410 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7411 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7412 && ! side_effects_p (x
))
7414 *ptrue
= *pfalse
= const0_rtx
;
7420 else if (code
== IF_THEN_ELSE
)
7422 /* If we have IF_THEN_ELSE already, extract the condition and
7423 canonicalize it if it is NE or EQ. */
7424 cond0
= XEXP (x
, 0);
7425 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7426 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7427 return XEXP (cond0
, 0);
7428 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7430 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7431 return XEXP (cond0
, 0);
7437 /* If X is a normal SUBREG with both inner and outer modes integral,
7438 we can narrow both the true and false values of the inner expression,
7439 if there is a condition. */
7440 else if (code
== SUBREG
&& GET_MODE_CLASS (mode
) == MODE_INT
7441 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_INT
7442 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))
7443 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7446 if ((GET_CODE (SUBREG_REG (x
)) == REG
7447 || GET_CODE (SUBREG_REG (x
)) == MEM
7448 || CONSTANT_P (SUBREG_REG (x
)))
7449 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))) > UNITS_PER_WORD
7450 && (WORDS_BIG_ENDIAN
|| SUBREG_WORD (x
) != 0))
7452 true0
= operand_subword (true0
, SUBREG_WORD (x
), 0,
7453 GET_MODE (SUBREG_REG (x
)));
7454 false0
= operand_subword (false0
, SUBREG_WORD (x
), 0,
7455 GET_MODE (SUBREG_REG (x
)));
7457 *ptrue
= force_to_mode (true0
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
7459 = force_to_mode (false0
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
7464 /* If X is a constant, this isn't special and will cause confusions
7465 if we treat it as such. Likewise if it is equivalent to a constant. */
7466 else if (CONSTANT_P (x
)
7467 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7470 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7471 will be least confusing to the rest of the compiler. */
7472 else if (mode
== BImode
)
7474 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7478 /* If X is known to be either 0 or -1, those are the true and
7479 false values when testing X. */
7480 else if (x
== constm1_rtx
|| x
== const0_rtx
7481 || (mode
!= VOIDmode
7482 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7484 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7488 /* Likewise for 0 or a single bit. */
7489 else if (mode
!= VOIDmode
7490 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7491 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7493 *ptrue
= GEN_INT (nz
), *pfalse
= const0_rtx
;
7497 /* Otherwise fail; show no condition with true and false values the same. */
7498 *ptrue
= *pfalse
= x
;
7502 /* Return the value of expression X given the fact that condition COND
7503 is known to be true when applied to REG as its first operand and VAL
7504 as its second. X is known to not be shared and so can be modified in
7507 We only handle the simplest cases, and specifically those cases that
7508 arise with IF_THEN_ELSE expressions. */
7511 known_cond (x
, cond
, reg
, val
)
7516 enum rtx_code code
= GET_CODE (x
);
7521 if (side_effects_p (x
))
7524 if (cond
== EQ
&& rtx_equal_p (x
, reg
) && !FLOAT_MODE_P (cond
))
7526 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7529 /* If X is (abs REG) and we know something about REG's relationship
7530 with zero, we may be able to simplify this. */
7532 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7535 case GE
: case GT
: case EQ
:
7538 return gen_unary (NEG
, GET_MODE (XEXP (x
, 0)), GET_MODE (XEXP (x
, 0)),
7544 /* The only other cases we handle are MIN, MAX, and comparisons if the
7545 operands are the same as REG and VAL. */
7547 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7549 if (rtx_equal_p (XEXP (x
, 0), val
))
7550 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7552 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7554 if (GET_RTX_CLASS (code
) == '<')
7556 if (comparison_dominates_p (cond
, code
))
7557 return const_true_rtx
;
7559 code
= combine_reversed_comparison_code (x
);
7561 && comparison_dominates_p (cond
, code
))
7566 else if (code
== SMAX
|| code
== SMIN
7567 || code
== UMIN
|| code
== UMAX
)
7569 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7571 if (code
== SMAX
|| code
== UMAX
)
7572 cond
= reverse_condition (cond
);
7577 return unsignedp
? x
: XEXP (x
, 1);
7579 return unsignedp
? x
: XEXP (x
, 0);
7581 return unsignedp
? XEXP (x
, 1) : x
;
7583 return unsignedp
? XEXP (x
, 0) : x
;
7591 fmt
= GET_RTX_FORMAT (code
);
7592 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7595 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7596 else if (fmt
[i
] == 'E')
7597 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7598 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7605 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7606 assignment as a field assignment. */
7609 rtx_equal_for_field_assignment_p (x
, y
)
7613 if (x
== y
|| rtx_equal_p (x
, y
))
7616 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7619 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7620 Note that all SUBREGs of MEM are paradoxical; otherwise they
7621 would have been rewritten. */
7622 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7623 && GET_CODE (SUBREG_REG (y
)) == MEM
7624 && rtx_equal_p (SUBREG_REG (y
),
7625 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7628 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7629 && GET_CODE (SUBREG_REG (x
)) == MEM
7630 && rtx_equal_p (SUBREG_REG (x
),
7631 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7634 /* We used to see if get_last_value of X and Y were the same but that's
7635 not correct. In one direction, we'll cause the assignment to have
7636 the wrong destination and in the case, we'll import a register into this
7637 insn that might have already have been dead. So fail if none of the
7638 above cases are true. */
7642 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7643 Return that assignment if so.
7645 We only handle the most common cases. */
7648 make_field_assignment (x
)
7651 rtx dest
= SET_DEST (x
);
7652 rtx src
= SET_SRC (x
);
7657 unsigned HOST_WIDE_INT len
;
7659 enum machine_mode mode
;
7661 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7662 a clear of a one-bit field. We will have changed it to
7663 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7666 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7667 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7668 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7669 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7671 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7674 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7678 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7679 && subreg_lowpart_p (XEXP (src
, 0))
7680 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7681 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7682 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7683 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7684 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7686 assign
= make_extraction (VOIDmode
, dest
, 0,
7687 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7690 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7694 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7696 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7697 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7698 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7700 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7703 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7707 /* The other case we handle is assignments into a constant-position
7708 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7709 a mask that has all one bits except for a group of zero bits and
7710 OTHER is known to have zeros where C1 has ones, this is such an
7711 assignment. Compute the position and length from C1. Shift OTHER
7712 to the appropriate position, force it to the required mode, and
7713 make the extraction. Check for the AND in both operands. */
7715 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7718 rhs
= expand_compound_operation (XEXP (src
, 0));
7719 lhs
= expand_compound_operation (XEXP (src
, 1));
7721 if (GET_CODE (rhs
) == AND
7722 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7723 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7724 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7725 else if (GET_CODE (lhs
) == AND
7726 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7727 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7728 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7732 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7733 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7734 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7735 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7738 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7742 /* The mode to use for the source is the mode of the assignment, or of
7743 what is inside a possible STRICT_LOW_PART. */
7744 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7745 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7747 /* Shift OTHER right POS places and make it the source, restricting it
7748 to the proper length and mode. */
7750 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7751 GET_MODE (src
), other
, pos
),
7753 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7754 ? ~(unsigned HOST_WIDE_INT
) 0
7755 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7758 return gen_rtx_combine (SET
, VOIDmode
, assign
, src
);
7761 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7765 apply_distributive_law (x
)
7768 enum rtx_code code
= GET_CODE (x
);
7769 rtx lhs
, rhs
, other
;
7771 enum rtx_code inner_code
;
7773 /* Distributivity is not true for floating point.
7774 It can change the value. So don't do it.
7775 -- rms and moshier@world.std.com. */
7776 if (FLOAT_MODE_P (GET_MODE (x
)))
7779 /* The outer operation can only be one of the following: */
7780 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7781 && code
!= PLUS
&& code
!= MINUS
)
7784 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7786 /* If either operand is a primitive we can't do anything, so get out
7788 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7789 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7792 lhs
= expand_compound_operation (lhs
);
7793 rhs
= expand_compound_operation (rhs
);
7794 inner_code
= GET_CODE (lhs
);
7795 if (inner_code
!= GET_CODE (rhs
))
7798 /* See if the inner and outer operations distribute. */
7805 /* These all distribute except over PLUS. */
7806 if (code
== PLUS
|| code
== MINUS
)
7811 if (code
!= PLUS
&& code
!= MINUS
)
7816 /* This is also a multiply, so it distributes over everything. */
7820 /* Non-paradoxical SUBREGs distributes over all operations, provided
7821 the inner modes and word numbers are the same, this is an extraction
7822 of a low-order part, we don't convert an fp operation to int or
7823 vice versa, and we would not be converting a single-word
7824 operation into a multi-word operation. The latter test is not
7825 required, but it prevents generating unneeded multi-word operations.
7826 Some of the previous tests are redundant given the latter test, but
7827 are retained because they are required for correctness.
7829 We produce the result slightly differently in this case. */
7831 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7832 || SUBREG_WORD (lhs
) != SUBREG_WORD (rhs
)
7833 || ! subreg_lowpart_p (lhs
)
7834 || (GET_MODE_CLASS (GET_MODE (lhs
))
7835 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7836 || (GET_MODE_SIZE (GET_MODE (lhs
))
7837 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7838 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7841 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7842 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7843 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7849 /* Set LHS and RHS to the inner operands (A and B in the example
7850 above) and set OTHER to the common operand (C in the example).
7851 These is only one way to do this unless the inner operation is
7853 if (GET_RTX_CLASS (inner_code
) == 'c'
7854 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7855 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7856 else if (GET_RTX_CLASS (inner_code
) == 'c'
7857 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7858 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7859 else if (GET_RTX_CLASS (inner_code
) == 'c'
7860 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7861 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7862 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7863 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7867 /* Form the new inner operation, seeing if it simplifies first. */
7868 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7870 /* There is one exception to the general way of distributing:
7871 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7872 if (code
== XOR
&& inner_code
== IOR
)
7875 other
= gen_unary (NOT
, GET_MODE (x
), GET_MODE (x
), other
);
7878 /* We may be able to continuing distributing the result, so call
7879 ourselves recursively on the inner operation before forming the
7880 outer operation, which we return. */
7881 return gen_binary (inner_code
, GET_MODE (x
),
7882 apply_distributive_law (tem
), other
);
7885 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7888 Return an equivalent form, if different from X. Otherwise, return X. If
7889 X is zero, we are to always construct the equivalent form. */
7892 simplify_and_const_int (x
, mode
, varop
, constop
)
7894 enum machine_mode mode
;
7896 unsigned HOST_WIDE_INT constop
;
7898 unsigned HOST_WIDE_INT nonzero
;
7901 /* Simplify VAROP knowing that we will be only looking at some of the
7903 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7905 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7906 CONST_INT, we are done. */
7907 if (GET_CODE (varop
) == CLOBBER
|| GET_CODE (varop
) == CONST_INT
)
7910 /* See what bits may be nonzero in VAROP. Unlike the general case of
7911 a call to nonzero_bits, here we don't care about bits outside
7914 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7915 nonzero
= trunc_int_for_mode (nonzero
, mode
);
7917 /* Turn off all bits in the constant that are known to already be zero.
7918 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7919 which is tested below. */
7923 /* If we don't have any bits left, return zero. */
7927 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7928 a power of two, we can replace this with a ASHIFT. */
7929 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7930 && (i
= exact_log2 (constop
)) >= 0)
7931 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7933 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7934 or XOR, then try to apply the distributive law. This may eliminate
7935 operations if either branch can be simplified because of the AND.
7936 It may also make some cases more complex, but those cases probably
7937 won't match a pattern either with or without this. */
7939 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7941 gen_lowpart_for_combine
7943 apply_distributive_law
7944 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7945 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7946 XEXP (varop
, 0), constop
),
7947 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7948 XEXP (varop
, 1), constop
))));
7950 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7951 if we already had one (just check for the simplest cases). */
7952 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7953 && GET_MODE (XEXP (x
, 0)) == mode
7954 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7955 varop
= XEXP (x
, 0);
7957 varop
= gen_lowpart_for_combine (mode
, varop
);
7959 /* If we can't make the SUBREG, try to return what we were given. */
7960 if (GET_CODE (varop
) == CLOBBER
)
7961 return x
? x
: varop
;
7963 /* If we are only masking insignificant bits, return VAROP. */
7964 if (constop
== nonzero
)
7967 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7968 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7969 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7973 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7974 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7975 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7977 SUBST (XEXP (x
, 0), varop
);
7983 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7984 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7985 is less useful. We can't allow both, because that results in exponential
7986 run time recursion. There is a nullstone testcase that triggered
7987 this. This macro avoids accidental uses of num_sign_bit_copies. */
7988 #define num_sign_bit_copies()
7990 /* Given an expression, X, compute which bits in X can be non-zero.
7991 We don't care about bits outside of those defined in MODE.
7993 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7994 a shift, AND, or zero_extract, we can do better. */
7996 static unsigned HOST_WIDE_INT
7997 nonzero_bits (x
, mode
)
7999 enum machine_mode mode
;
8001 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8002 unsigned HOST_WIDE_INT inner_nz
;
8004 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8007 /* For floating-point values, assume all bits are needed. */
8008 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8011 /* If X is wider than MODE, use its mode instead. */
8012 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8014 mode
= GET_MODE (x
);
8015 nonzero
= GET_MODE_MASK (mode
);
8016 mode_width
= GET_MODE_BITSIZE (mode
);
8019 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8020 /* Our only callers in this case look for single bit values. So
8021 just return the mode mask. Those tests will then be false. */
8024 #ifndef WORD_REGISTER_OPERATIONS
8025 /* If MODE is wider than X, but both are a single word for both the host
8026 and target machines, we can compute this from which bits of the
8027 object might be nonzero in its own mode, taking into account the fact
8028 that on many CISC machines, accessing an object in a wider mode
8029 causes the high-order bits to become undefined. So they are
8030 not known to be zero. */
8032 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8033 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8034 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8035 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8037 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
8038 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8043 code
= GET_CODE (x
);
8047 #ifdef POINTERS_EXTEND_UNSIGNED
8048 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8049 all the bits above ptr_mode are known to be zero. */
8050 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8052 nonzero
&= GET_MODE_MASK (ptr_mode
);
8055 #ifdef STACK_BOUNDARY
8056 /* If this is the stack pointer, we may know something about its
8057 alignment. If PUSH_ROUNDING is defined, it is possible for the
8058 stack to be momentarily aligned only to that amount, so we pick
8059 the least alignment. */
8061 /* We can't check for arg_pointer_rtx here, because it is not
8062 guaranteed to have as much alignment as the stack pointer.
8063 In particular, in the Irix6 n64 ABI, the stack has 128 bit
8064 alignment but the argument pointer has only 64 bit alignment. */
8066 if ((x
== frame_pointer_rtx
8067 || x
== stack_pointer_rtx
8068 || x
== hard_frame_pointer_rtx
8069 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
8070 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
))
8076 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
8078 #ifdef PUSH_ROUNDING
8079 if (REGNO (x
) == STACK_POINTER_REGNUM
&& PUSH_ARGS
)
8080 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
8083 /* We must return here, otherwise we may get a worse result from
8084 one of the choices below. There is nothing useful below as
8085 far as the stack pointer is concerned. */
8086 return nonzero
&= ~(sp_alignment
- 1);
8090 /* If X is a register whose nonzero bits value is current, use it.
8091 Otherwise, if X is a register whose value we can find, use that
8092 value. Otherwise, use the previously-computed global nonzero bits
8093 for this register. */
8095 if (reg_last_set_value
[REGNO (x
)] != 0
8096 && reg_last_set_mode
[REGNO (x
)] == mode
8097 && (reg_last_set_label
[REGNO (x
)] == label_tick
8098 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8099 && REG_N_SETS (REGNO (x
)) == 1
8100 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8102 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8103 return reg_last_set_nonzero_bits
[REGNO (x
)];
8105 tem
= get_last_value (x
);
8109 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8110 /* If X is narrower than MODE and TEM is a non-negative
8111 constant that would appear negative in the mode of X,
8112 sign-extend it for use in reg_nonzero_bits because some
8113 machines (maybe most) will actually do the sign-extension
8114 and this is the conservative approach.
8116 ??? For 2.5, try to tighten up the MD files in this regard
8117 instead of this kludge. */
8119 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8120 && GET_CODE (tem
) == CONST_INT
8122 && 0 != (INTVAL (tem
)
8123 & ((HOST_WIDE_INT
) 1
8124 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8125 tem
= GEN_INT (INTVAL (tem
)
8126 | ((HOST_WIDE_INT
) (-1)
8127 << GET_MODE_BITSIZE (GET_MODE (x
))));
8129 return nonzero_bits (tem
, mode
);
8131 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8132 return reg_nonzero_bits
[REGNO (x
)] & nonzero
;
8137 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8138 /* If X is negative in MODE, sign-extend the value. */
8139 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8140 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8141 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8147 #ifdef LOAD_EXTEND_OP
8148 /* In many, if not most, RISC machines, reading a byte from memory
8149 zeros the rest of the register. Noticing that fact saves a lot
8150 of extra zero-extends. */
8151 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8152 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8157 case UNEQ
: case LTGT
:
8158 case GT
: case GTU
: case UNGT
:
8159 case LT
: case LTU
: case UNLT
:
8160 case GE
: case GEU
: case UNGE
:
8161 case LE
: case LEU
: case UNLE
:
8162 case UNORDERED
: case ORDERED
:
8164 /* If this produces an integer result, we know which bits are set.
8165 Code here used to clear bits outside the mode of X, but that is
8168 if (GET_MODE_CLASS (mode
) == MODE_INT
8169 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8170 nonzero
= STORE_FLAG_VALUE
;
8175 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8176 and num_sign_bit_copies. */
8177 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8178 == GET_MODE_BITSIZE (GET_MODE (x
)))
8182 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8183 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8188 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8189 and num_sign_bit_copies. */
8190 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8191 == GET_MODE_BITSIZE (GET_MODE (x
)))
8197 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
8201 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
8202 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8203 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8207 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8208 Otherwise, show all the bits in the outer mode but not the inner
8210 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
8211 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8213 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8215 & (((HOST_WIDE_INT
) 1
8216 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8217 inner_nz
|= (GET_MODE_MASK (mode
)
8218 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8221 nonzero
&= inner_nz
;
8225 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8226 & nonzero_bits (XEXP (x
, 1), mode
));
8230 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8231 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8232 | nonzero_bits (XEXP (x
, 1), mode
));
8235 case PLUS
: case MINUS
:
8237 case DIV
: case UDIV
:
8238 case MOD
: case UMOD
:
8239 /* We can apply the rules of arithmetic to compute the number of
8240 high- and low-order zero bits of these operations. We start by
8241 computing the width (position of the highest-order non-zero bit)
8242 and the number of low-order zero bits for each value. */
8244 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
8245 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
8246 int width0
= floor_log2 (nz0
) + 1;
8247 int width1
= floor_log2 (nz1
) + 1;
8248 int low0
= floor_log2 (nz0
& -nz0
);
8249 int low1
= floor_log2 (nz1
& -nz1
);
8250 HOST_WIDE_INT op0_maybe_minusp
8251 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8252 HOST_WIDE_INT op1_maybe_minusp
8253 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8254 unsigned int result_width
= mode_width
;
8262 && (XEXP (x
, 0) == stack_pointer_rtx
8263 || XEXP (x
, 0) == frame_pointer_rtx
)
8264 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8266 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
8268 nz0
= (GET_MODE_MASK (mode
) & ~(sp_alignment
- 1));
8269 nz1
= INTVAL (XEXP (x
, 1)) - STACK_BIAS
;
8270 width0
= floor_log2 (nz0
) + 1;
8271 width1
= floor_log2 (nz1
) + 1;
8272 low0
= floor_log2 (nz0
& -nz0
);
8273 low1
= floor_log2 (nz1
& -nz1
);
8276 result_width
= MAX (width0
, width1
) + 1;
8277 result_low
= MIN (low0
, low1
);
8280 result_low
= MIN (low0
, low1
);
8283 result_width
= width0
+ width1
;
8284 result_low
= low0
+ low1
;
8287 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8288 result_width
= width0
;
8291 result_width
= width0
;
8294 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8295 result_width
= MIN (width0
, width1
);
8296 result_low
= MIN (low0
, low1
);
8299 result_width
= MIN (width0
, width1
);
8300 result_low
= MIN (low0
, low1
);
8306 if (result_width
< mode_width
)
8307 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8310 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8315 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8316 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8317 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8321 /* If this is a SUBREG formed for a promoted variable that has
8322 been zero-extended, we know that at least the high-order bits
8323 are zero, though others might be too. */
8325 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
8326 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8327 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
8329 /* If the inner mode is a single word for both the host and target
8330 machines, we can compute this from which bits of the inner
8331 object might be nonzero. */
8332 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8333 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8334 <= HOST_BITS_PER_WIDE_INT
))
8336 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
8338 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8339 /* If this is a typical RISC machine, we only have to worry
8340 about the way loads are extended. */
8341 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8343 & (((unsigned HOST_WIDE_INT
) 1
8344 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8346 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8349 /* On many CISC machines, accessing an object in a wider mode
8350 causes the high-order bits to become undefined. So they are
8351 not known to be zero. */
8352 if (GET_MODE_SIZE (GET_MODE (x
))
8353 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8354 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8355 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8364 /* The nonzero bits are in two classes: any bits within MODE
8365 that aren't in GET_MODE (x) are always significant. The rest of the
8366 nonzero bits are those that are significant in the operand of
8367 the shift when shifted the appropriate number of bits. This
8368 shows that high-order bits are cleared by the right shift and
8369 low-order bits by left shifts. */
8370 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8371 && INTVAL (XEXP (x
, 1)) >= 0
8372 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8374 enum machine_mode inner_mode
= GET_MODE (x
);
8375 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8376 int count
= INTVAL (XEXP (x
, 1));
8377 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8378 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8379 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8380 unsigned HOST_WIDE_INT outer
= 0;
8382 if (mode_width
> width
)
8383 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8385 if (code
== LSHIFTRT
)
8387 else if (code
== ASHIFTRT
)
8391 /* If the sign bit may have been nonzero before the shift, we
8392 need to mark all the places it could have been copied to
8393 by the shift as possibly nonzero. */
8394 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8395 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8397 else if (code
== ASHIFT
)
8400 inner
= ((inner
<< (count
% width
)
8401 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8403 nonzero
&= (outer
| inner
);
8408 /* This is at most the number of bits in the mode. */
8409 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
8413 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
8414 | nonzero_bits (XEXP (x
, 2), mode
));
8424 /* See the macro definition above. */
8425 #undef num_sign_bit_copies
8427 /* Return the number of bits at the high-order end of X that are known to
8428 be equal to the sign bit. X will be used in mode MODE; if MODE is
8429 VOIDmode, X will be used in its own mode. The returned value will always
8430 be between 1 and the number of bits in MODE. */
8433 num_sign_bit_copies (x
, mode
)
8435 enum machine_mode mode
;
8437 enum rtx_code code
= GET_CODE (x
);
8438 unsigned int bitwidth
;
8439 int num0
, num1
, result
;
8440 unsigned HOST_WIDE_INT nonzero
;
8443 /* If we weren't given a mode, use the mode of X. If the mode is still
8444 VOIDmode, we don't know anything. Likewise if one of the modes is
8447 if (mode
== VOIDmode
)
8448 mode
= GET_MODE (x
);
8450 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8453 bitwidth
= GET_MODE_BITSIZE (mode
);
8455 /* For a smaller object, just ignore the high bits. */
8456 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8458 num0
= num_sign_bit_copies (x
, GET_MODE (x
));
8460 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8463 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8465 #ifndef WORD_REGISTER_OPERATIONS
8466 /* If this machine does not do all register operations on the entire
8467 register and MODE is wider than the mode of X, we can say nothing
8468 at all about the high-order bits. */
8471 /* Likewise on machines that do, if the mode of the object is smaller
8472 than a word and loads of that size don't sign extend, we can say
8473 nothing about the high order bits. */
8474 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8475 #ifdef LOAD_EXTEND_OP
8476 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8487 #ifdef POINTERS_EXTEND_UNSIGNED
8488 /* If pointers extend signed and this is a pointer in Pmode, say that
8489 all the bits above ptr_mode are known to be sign bit copies. */
8490 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8492 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8495 if (reg_last_set_value
[REGNO (x
)] != 0
8496 && reg_last_set_mode
[REGNO (x
)] == mode
8497 && (reg_last_set_label
[REGNO (x
)] == label_tick
8498 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8499 && REG_N_SETS (REGNO (x
)) == 1
8500 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8502 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8503 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8505 tem
= get_last_value (x
);
8507 return num_sign_bit_copies (tem
, mode
);
8509 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0)
8510 return reg_sign_bit_copies
[REGNO (x
)];
8514 #ifdef LOAD_EXTEND_OP
8515 /* Some RISC machines sign-extend all loads of smaller than a word. */
8516 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8517 return MAX (1, ((int) bitwidth
8518 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8523 /* If the constant is negative, take its 1's complement and remask.
8524 Then see how many zero bits we have. */
8525 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8526 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8527 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8528 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8530 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8533 /* If this is a SUBREG for a promoted object that is sign-extended
8534 and we are looking at it in a wider mode, we know that at least the
8535 high-order bits are known to be sign bit copies. */
8537 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8539 num0
= num_sign_bit_copies (SUBREG_REG (x
), mode
);
8540 return MAX ((int) bitwidth
8541 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8545 /* For a smaller object, just ignore the high bits. */
8546 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8548 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
8549 return MAX (1, (num0
8550 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8554 #ifdef WORD_REGISTER_OPERATIONS
8555 #ifdef LOAD_EXTEND_OP
8556 /* For paradoxical SUBREGs on machines where all register operations
8557 affect the entire register, just look inside. Note that we are
8558 passing MODE to the recursive call, so the number of sign bit copies
8559 will remain relative to that mode, not the inner mode. */
8561 /* This works only if loads sign extend. Otherwise, if we get a
8562 reload for the inner part, it may be loaded from the stack, and
8563 then we lose all sign bit copies that existed before the store
8566 if ((GET_MODE_SIZE (GET_MODE (x
))
8567 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8568 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
)
8569 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
8575 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8576 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8580 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8581 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
8584 /* For a smaller object, just ignore the high bits. */
8585 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
8586 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8590 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8592 case ROTATE
: case ROTATERT
:
8593 /* If we are rotating left by a number of bits less than the number
8594 of sign bit copies, we can just subtract that amount from the
8596 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8597 && INTVAL (XEXP (x
, 1)) >= 0 && INTVAL (XEXP (x
, 1)) < bitwidth
)
8599 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8600 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8601 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8606 /* In general, this subtracts one sign bit copy. But if the value
8607 is known to be positive, the number of sign bit copies is the
8608 same as that of the input. Finally, if the input has just one bit
8609 that might be nonzero, all the bits are copies of the sign bit. */
8610 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8611 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8612 return num0
> 1 ? num0
- 1 : 1;
8614 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8619 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8624 case IOR
: case AND
: case XOR
:
8625 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8626 /* Logical operations will preserve the number of sign-bit copies.
8627 MIN and MAX operations always return one of the operands. */
8628 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8629 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8630 return MIN (num0
, num1
);
8632 case PLUS
: case MINUS
:
8633 /* For addition and subtraction, we can have a 1-bit carry. However,
8634 if we are subtracting 1 from a positive number, there will not
8635 be such a carry. Furthermore, if the positive number is known to
8636 be 0 or 1, we know the result is either -1 or 0. */
8638 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8639 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8641 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8642 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8643 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8644 : bitwidth
- floor_log2 (nonzero
) - 1);
8647 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8648 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8649 return MAX (1, MIN (num0
, num1
) - 1);
8652 /* The number of bits of the product is the sum of the number of
8653 bits of both terms. However, unless one of the terms if known
8654 to be positive, we must allow for an additional bit since negating
8655 a negative number can remove one sign bit copy. */
8657 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8658 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8660 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8662 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8663 || (((nonzero_bits (XEXP (x
, 0), mode
)
8664 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8665 && ((nonzero_bits (XEXP (x
, 1), mode
)
8666 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8669 return MAX (1, result
);
8672 /* The result must be <= the first operand. If the first operand
8673 has the high bit set, we know nothing about the number of sign
8675 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8677 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8678 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8681 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8684 /* The result must be <= the scond operand. */
8685 return num_sign_bit_copies (XEXP (x
, 1), mode
);
8688 /* Similar to unsigned division, except that we have to worry about
8689 the case where the divisor is negative, in which case we have
8691 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8693 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8694 || (nonzero_bits (XEXP (x
, 1), mode
)
8695 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8701 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8703 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8704 || (nonzero_bits (XEXP (x
, 1), mode
)
8705 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8711 /* Shifts by a constant add to the number of bits equal to the
8713 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8714 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8715 && INTVAL (XEXP (x
, 1)) > 0)
8716 num0
= MIN (bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8721 /* Left shifts destroy copies. */
8722 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8723 || INTVAL (XEXP (x
, 1)) < 0
8724 || INTVAL (XEXP (x
, 1)) >= bitwidth
)
8727 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8728 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8731 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8732 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
8733 return MIN (num0
, num1
);
8735 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8736 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8737 case GEU
: case GTU
: case LEU
: case LTU
:
8738 case UNORDERED
: case ORDERED
:
8739 /* If the constant is negative, take its 1's complement and remask.
8740 Then see how many zero bits we have. */
8741 nonzero
= STORE_FLAG_VALUE
;
8742 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8743 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8744 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8746 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8753 /* If we haven't been able to figure it out by one of the above rules,
8754 see if some of the high-order bits are known to be zero. If so,
8755 count those bits and return one less than that amount. If we can't
8756 safely compute the mask for this mode, always return BITWIDTH. */
8758 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8761 nonzero
= nonzero_bits (x
, mode
);
8762 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8763 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8766 /* Return the number of "extended" bits there are in X, when interpreted
8767 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8768 unsigned quantities, this is the number of high-order zero bits.
8769 For signed quantities, this is the number of copies of the sign bit
8770 minus 1. In both case, this function returns the number of "spare"
8771 bits. For example, if two quantities for which this function returns
8772 at least 1 are added, the addition is known not to overflow.
8774 This function will always return 0 unless called during combine, which
8775 implies that it must be called from a define_split. */
8778 extended_count (x
, mode
, unsignedp
)
8780 enum machine_mode mode
;
8783 if (nonzero_sign_valid
== 0)
8787 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8788 ? (GET_MODE_BITSIZE (mode
) - 1
8789 - floor_log2 (nonzero_bits (x
, mode
)))
8791 : num_sign_bit_copies (x
, mode
) - 1);
8794 /* This function is called from `simplify_shift_const' to merge two
8795 outer operations. Specifically, we have already found that we need
8796 to perform operation *POP0 with constant *PCONST0 at the outermost
8797 position. We would now like to also perform OP1 with constant CONST1
8798 (with *POP0 being done last).
8800 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8801 the resulting operation. *PCOMP_P is set to 1 if we would need to
8802 complement the innermost operand, otherwise it is unchanged.
8804 MODE is the mode in which the operation will be done. No bits outside
8805 the width of this mode matter. It is assumed that the width of this mode
8806 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8808 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8809 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8810 result is simply *PCONST0.
8812 If the resulting operation cannot be expressed as one operation, we
8813 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8816 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
8817 enum rtx_code
*pop0
;
8818 HOST_WIDE_INT
*pconst0
;
8820 HOST_WIDE_INT const1
;
8821 enum machine_mode mode
;
8824 enum rtx_code op0
= *pop0
;
8825 HOST_WIDE_INT const0
= *pconst0
;
8827 const0
&= GET_MODE_MASK (mode
);
8828 const1
&= GET_MODE_MASK (mode
);
8830 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8834 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8837 if (op1
== NIL
|| op0
== SET
)
8840 else if (op0
== NIL
)
8841 op0
= op1
, const0
= const1
;
8843 else if (op0
== op1
)
8867 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8868 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8871 /* If the two constants aren't the same, we can't do anything. The
8872 remaining six cases can all be done. */
8873 else if (const0
!= const1
)
8881 /* (a & b) | b == b */
8883 else /* op1 == XOR */
8884 /* (a ^ b) | b == a | b */
8890 /* (a & b) ^ b == (~a) & b */
8891 op0
= AND
, *pcomp_p
= 1;
8892 else /* op1 == IOR */
8893 /* (a | b) ^ b == a & ~b */
8894 op0
= AND
, *pconst0
= ~const0
;
8899 /* (a | b) & b == b */
8901 else /* op1 == XOR */
8902 /* (a ^ b) & b) == (~a) & b */
8909 /* Check for NO-OP cases. */
8910 const0
&= GET_MODE_MASK (mode
);
8912 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8914 else if (const0
== 0 && op0
== AND
)
8916 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8920 /* ??? Slightly redundant with the above mask, but not entirely.
8921 Moving this above means we'd have to sign-extend the mode mask
8922 for the final test. */
8923 const0
= trunc_int_for_mode (const0
, mode
);
8931 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8932 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8933 that we started with.
8935 The shift is normally computed in the widest mode we find in VAROP, as
8936 long as it isn't a different number of words than RESULT_MODE. Exceptions
8937 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8940 simplify_shift_const (x
, code
, result_mode
, varop
, input_count
)
8943 enum machine_mode result_mode
;
8947 enum rtx_code orig_code
= code
;
8948 int orig_count
= input_count
;
8951 enum machine_mode mode
= result_mode
;
8952 enum machine_mode shift_mode
, tmode
;
8953 unsigned int mode_words
8954 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8955 /* We form (outer_op (code varop count) (outer_const)). */
8956 enum rtx_code outer_op
= NIL
;
8957 HOST_WIDE_INT outer_const
= 0;
8959 int complement_p
= 0;
8962 /* If we were given an invalid count, don't do anything except exactly
8963 what was requested. */
8965 if (input_count
< 0 || input_count
> (int) GET_MODE_BITSIZE (mode
))
8970 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (input_count
));
8973 count
= input_count
;
8975 /* Make sure and truncate the "natural" shift on the way in. We don't
8976 want to do this inside the loop as it makes it more difficult to
8978 #ifdef SHIFT_COUNT_TRUNCATED
8979 if (SHIFT_COUNT_TRUNCATED
)
8980 count
%= GET_MODE_BITSIZE (mode
);
8983 /* Unless one of the branches of the `if' in this loop does a `continue',
8984 we will `break' the loop after the `if'. */
8988 /* If we have an operand of (clobber (const_int 0)), just return that
8990 if (GET_CODE (varop
) == CLOBBER
)
8993 /* If we discovered we had to complement VAROP, leave. Making a NOT
8994 here would cause an infinite loop. */
8998 /* Convert ROTATERT to ROTATE. */
8999 if (code
== ROTATERT
)
9000 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
9002 /* We need to determine what mode we will do the shift in. If the
9003 shift is a right shift or a ROTATE, we must always do it in the mode
9004 it was originally done in. Otherwise, we can do it in MODE, the
9005 widest mode encountered. */
9007 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9008 ? result_mode
: mode
);
9010 /* Handle cases where the count is greater than the size of the mode
9011 minus 1. For ASHIFT, use the size minus one as the count (this can
9012 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9013 take the count modulo the size. For other shifts, the result is
9016 Since these shifts are being produced by the compiler by combining
9017 multiple operations, each of which are defined, we know what the
9018 result is supposed to be. */
9020 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
9022 if (code
== ASHIFTRT
)
9023 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9024 else if (code
== ROTATE
|| code
== ROTATERT
)
9025 count
%= GET_MODE_BITSIZE (shift_mode
);
9028 /* We can't simply return zero because there may be an
9036 /* An arithmetic right shift of a quantity known to be -1 or 0
9038 if (code
== ASHIFTRT
9039 && (num_sign_bit_copies (varop
, shift_mode
)
9040 == GET_MODE_BITSIZE (shift_mode
)))
9046 /* If we are doing an arithmetic right shift and discarding all but
9047 the sign bit copies, this is equivalent to doing a shift by the
9048 bitsize minus one. Convert it into that shift because it will often
9049 allow other simplifications. */
9051 if (code
== ASHIFTRT
9052 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9053 >= GET_MODE_BITSIZE (shift_mode
)))
9054 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9056 /* We simplify the tests below and elsewhere by converting
9057 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9058 `make_compound_operation' will convert it to a ASHIFTRT for
9059 those machines (such as Vax) that don't have a LSHIFTRT. */
9060 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9062 && ((nonzero_bits (varop
, shift_mode
)
9063 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9067 switch (GET_CODE (varop
))
9073 new = expand_compound_operation (varop
);
9082 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9083 minus the width of a smaller mode, we can do this with a
9084 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9085 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9086 && ! mode_dependent_address_p (XEXP (varop
, 0))
9087 && ! MEM_VOLATILE_P (varop
)
9088 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9089 MODE_INT
, 1)) != BLKmode
)
9091 if (BYTES_BIG_ENDIAN
)
9092 new = gen_rtx_MEM (tmode
, XEXP (varop
, 0));
9094 new = gen_rtx_MEM (tmode
,
9095 plus_constant (XEXP (varop
, 0),
9096 count
/ BITS_PER_UNIT
));
9098 MEM_COPY_ATTRIBUTES (new, varop
);
9099 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
9100 : ZERO_EXTEND
, mode
, new);
9107 /* Similar to the case above, except that we can only do this if
9108 the resulting mode is the same as that of the underlying
9109 MEM and adjust the address depending on the *bits* endianness
9110 because of the way that bit-field extract insns are defined. */
9111 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9112 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9113 MODE_INT
, 1)) != BLKmode
9114 && tmode
== GET_MODE (XEXP (varop
, 0)))
9116 if (BITS_BIG_ENDIAN
)
9117 new = XEXP (varop
, 0);
9120 new = copy_rtx (XEXP (varop
, 0));
9121 SUBST (XEXP (new, 0),
9122 plus_constant (XEXP (new, 0),
9123 count
/ BITS_PER_UNIT
));
9126 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
9127 : ZERO_EXTEND
, mode
, new);
9134 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9135 the same number of words as what we've seen so far. Then store
9136 the widest mode in MODE. */
9137 if (subreg_lowpart_p (varop
)
9138 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9139 > GET_MODE_SIZE (GET_MODE (varop
)))
9140 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9141 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9144 varop
= SUBREG_REG (varop
);
9145 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9146 mode
= GET_MODE (varop
);
9152 /* Some machines use MULT instead of ASHIFT because MULT
9153 is cheaper. But it is still better on those machines to
9154 merge two shifts into one. */
9155 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9156 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9159 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9160 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9166 /* Similar, for when divides are cheaper. */
9167 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9168 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9171 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9172 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9178 /* If we are extracting just the sign bit of an arithmetic
9179 right shift, that shift is not needed. However, the sign
9180 bit of a wider mode may be different from what would be
9181 interpreted as the sign bit in a narrower mode, so, if
9182 the result is narrower, don't discard the shift. */
9183 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9184 && (GET_MODE_BITSIZE (result_mode
)
9185 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9187 varop
= XEXP (varop
, 0);
9191 /* ... fall through ... */
9196 /* Here we have two nested shifts. The result is usually the
9197 AND of a new shift with a mask. We compute the result below. */
9198 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9199 && INTVAL (XEXP (varop
, 1)) >= 0
9200 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9201 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9202 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9204 enum rtx_code first_code
= GET_CODE (varop
);
9205 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9206 unsigned HOST_WIDE_INT mask
;
9209 /* We have one common special case. We can't do any merging if
9210 the inner code is an ASHIFTRT of a smaller mode. However, if
9211 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9212 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9213 we can convert it to
9214 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9215 This simplifies certain SIGN_EXTEND operations. */
9216 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9217 && (GET_MODE_BITSIZE (result_mode
)
9218 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
9220 /* C3 has the low-order C1 bits zero. */
9222 mask
= (GET_MODE_MASK (mode
)
9223 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9225 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9226 XEXP (varop
, 0), mask
);
9227 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9229 count
= first_count
;
9234 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9235 than C1 high-order bits equal to the sign bit, we can convert
9236 this to either an ASHIFT or a ASHIFTRT depending on the
9239 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9241 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9242 && GET_MODE (varop
) == shift_mode
9243 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9246 varop
= XEXP (varop
, 0);
9248 signed_count
= count
- first_count
;
9249 if (signed_count
< 0)
9250 count
= -signed_count
, code
= ASHIFT
;
9252 count
= signed_count
;
9257 /* There are some cases we can't do. If CODE is ASHIFTRT,
9258 we can only do this if FIRST_CODE is also ASHIFTRT.
9260 We can't do the case when CODE is ROTATE and FIRST_CODE is
9263 If the mode of this shift is not the mode of the outer shift,
9264 we can't do this if either shift is a right shift or ROTATE.
9266 Finally, we can't do any of these if the mode is too wide
9267 unless the codes are the same.
9269 Handle the case where the shift codes are the same
9272 if (code
== first_code
)
9274 if (GET_MODE (varop
) != result_mode
9275 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9279 count
+= first_count
;
9280 varop
= XEXP (varop
, 0);
9284 if (code
== ASHIFTRT
9285 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9286 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9287 || (GET_MODE (varop
) != result_mode
9288 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9289 || first_code
== ROTATE
9290 || code
== ROTATE
)))
9293 /* To compute the mask to apply after the shift, shift the
9294 nonzero bits of the inner shift the same way the
9295 outer shift will. */
9297 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9300 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9303 /* Give up if we can't compute an outer operation to use. */
9305 || GET_CODE (mask_rtx
) != CONST_INT
9306 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9308 result_mode
, &complement_p
))
9311 /* If the shifts are in the same direction, we add the
9312 counts. Otherwise, we subtract them. */
9313 signed_count
= count
;
9314 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9315 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9316 signed_count
+= first_count
;
9318 signed_count
-= first_count
;
9320 /* If COUNT is positive, the new shift is usually CODE,
9321 except for the two exceptions below, in which case it is
9322 FIRST_CODE. If the count is negative, FIRST_CODE should
9324 if (signed_count
> 0
9325 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9326 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9327 code
= first_code
, count
= signed_count
;
9328 else if (signed_count
< 0)
9329 code
= first_code
, count
= -signed_count
;
9331 count
= signed_count
;
9333 varop
= XEXP (varop
, 0);
9337 /* If we have (A << B << C) for any shift, we can convert this to
9338 (A << C << B). This wins if A is a constant. Only try this if
9339 B is not a constant. */
9341 else if (GET_CODE (varop
) == code
9342 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9344 = simplify_binary_operation (code
, mode
,
9348 varop
= gen_rtx_combine (code
, mode
, new, XEXP (varop
, 1));
9355 /* Make this fit the case below. */
9356 varop
= gen_rtx_combine (XOR
, mode
, XEXP (varop
, 0),
9357 GEN_INT (GET_MODE_MASK (mode
)));
9363 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9364 with C the size of VAROP - 1 and the shift is logical if
9365 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9366 we have an (le X 0) operation. If we have an arithmetic shift
9367 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9368 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9370 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9371 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9372 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9373 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9374 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9375 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9378 varop
= gen_rtx_combine (LE
, GET_MODE (varop
), XEXP (varop
, 1),
9381 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9382 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
9387 /* If we have (shift (logical)), move the logical to the outside
9388 to allow it to possibly combine with another logical and the
9389 shift to combine with another shift. This also canonicalizes to
9390 what a ZERO_EXTRACT looks like. Also, some machines have
9391 (and (shift)) insns. */
9393 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9394 && (new = simplify_binary_operation (code
, result_mode
,
9396 GEN_INT (count
))) != 0
9397 && GET_CODE (new) == CONST_INT
9398 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9399 INTVAL (new), result_mode
, &complement_p
))
9401 varop
= XEXP (varop
, 0);
9405 /* If we can't do that, try to simplify the shift in each arm of the
9406 logical expression, make a new logical expression, and apply
9407 the inverse distributive law. */
9409 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9410 XEXP (varop
, 0), count
);
9411 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9412 XEXP (varop
, 1), count
);
9414 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9415 varop
= apply_distributive_law (varop
);
9422 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9423 says that the sign bit can be tested, FOO has mode MODE, C is
9424 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9425 that may be nonzero. */
9426 if (code
== LSHIFTRT
9427 && XEXP (varop
, 1) == const0_rtx
9428 && GET_MODE (XEXP (varop
, 0)) == result_mode
9429 && count
== GET_MODE_BITSIZE (result_mode
) - 1
9430 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9431 && ((STORE_FLAG_VALUE
9432 & ((HOST_WIDE_INT
) 1
9433 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9434 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9435 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9436 (HOST_WIDE_INT
) 1, result_mode
,
9439 varop
= XEXP (varop
, 0);
9446 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9447 than the number of bits in the mode is equivalent to A. */
9448 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9449 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9451 varop
= XEXP (varop
, 0);
9456 /* NEG commutes with ASHIFT since it is multiplication. Move the
9457 NEG outside to allow shifts to combine. */
9459 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9460 (HOST_WIDE_INT
) 0, result_mode
,
9463 varop
= XEXP (varop
, 0);
9469 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9470 is one less than the number of bits in the mode is
9471 equivalent to (xor A 1). */
9472 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9473 && XEXP (varop
, 1) == constm1_rtx
9474 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9475 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9476 (HOST_WIDE_INT
) 1, result_mode
,
9480 varop
= XEXP (varop
, 0);
9484 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9485 that might be nonzero in BAR are those being shifted out and those
9486 bits are known zero in FOO, we can replace the PLUS with FOO.
9487 Similarly in the other operand order. This code occurs when
9488 we are computing the size of a variable-size array. */
9490 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9491 && count
< HOST_BITS_PER_WIDE_INT
9492 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9493 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9494 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9496 varop
= XEXP (varop
, 0);
9499 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9500 && count
< HOST_BITS_PER_WIDE_INT
9501 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9502 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9504 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9505 & nonzero_bits (XEXP (varop
, 1),
9508 varop
= XEXP (varop
, 1);
9512 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9514 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9515 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9517 GEN_INT (count
))) != 0
9518 && GET_CODE (new) == CONST_INT
9519 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9520 INTVAL (new), result_mode
, &complement_p
))
9522 varop
= XEXP (varop
, 0);
9528 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9529 with C the size of VAROP - 1 and the shift is logical if
9530 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9531 we have a (gt X 0) operation. If the shift is arithmetic with
9532 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9533 we have a (neg (gt X 0)) operation. */
9535 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9536 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9537 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9538 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9539 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9540 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9541 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9544 varop
= gen_rtx_combine (GT
, GET_MODE (varop
), XEXP (varop
, 1),
9547 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9548 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
9555 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9556 if the truncate does not affect the value. */
9557 if (code
== LSHIFTRT
9558 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9559 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9560 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9561 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9562 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9564 rtx varop_inner
= XEXP (varop
, 0);
9567 = gen_rtx_combine (LSHIFTRT
, GET_MODE (varop_inner
),
9568 XEXP (varop_inner
, 0),
9570 + INTVAL (XEXP (varop_inner
, 1))));
9571 varop
= gen_rtx_combine (TRUNCATE
, GET_MODE (varop
),
9585 /* We need to determine what mode to do the shift in. If the shift is
9586 a right shift or ROTATE, we must always do it in the mode it was
9587 originally done in. Otherwise, we can do it in MODE, the widest mode
9588 encountered. The code we care about is that of the shift that will
9589 actually be done, not the shift that was originally requested. */
9591 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9592 ? result_mode
: mode
);
9594 /* We have now finished analyzing the shift. The result should be
9595 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9596 OUTER_OP is non-NIL, it is an operation that needs to be applied
9597 to the result of the shift. OUTER_CONST is the relevant constant,
9598 but we must turn off all bits turned off in the shift.
9600 If we were passed a value for X, see if we can use any pieces of
9601 it. If not, make new rtx. */
9603 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9604 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9605 && INTVAL (XEXP (x
, 1)) == count
)
9606 const_rtx
= XEXP (x
, 1);
9608 const_rtx
= GEN_INT (count
);
9610 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9611 && GET_MODE (XEXP (x
, 0)) == shift_mode
9612 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9613 varop
= XEXP (x
, 0);
9614 else if (GET_MODE (varop
) != shift_mode
)
9615 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9617 /* If we can't make the SUBREG, try to return what we were given. */
9618 if (GET_CODE (varop
) == CLOBBER
)
9619 return x
? x
: varop
;
9621 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9626 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
9627 x
= gen_rtx_combine (code
, shift_mode
, varop
, const_rtx
);
9629 SUBST (XEXP (x
, 0), varop
);
9630 SUBST (XEXP (x
, 1), const_rtx
);
9633 /* If we have an outer operation and we just made a shift, it is
9634 possible that we could have simplified the shift were it not
9635 for the outer operation. So try to do the simplification
9638 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9639 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9640 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9641 INTVAL (XEXP (x
, 1)));
9643 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9644 turn off all the bits that the shift would have turned off. */
9645 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9646 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9647 GET_MODE_MASK (result_mode
) >> orig_count
);
9649 /* Do the remainder of the processing in RESULT_MODE. */
9650 x
= gen_lowpart_for_combine (result_mode
, x
);
9652 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9655 x
= gen_unary (NOT
, result_mode
, result_mode
, x
);
9657 if (outer_op
!= NIL
)
9659 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9660 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9662 if (outer_op
== AND
)
9663 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9664 else if (outer_op
== SET
)
9665 /* This means that we have determined that the result is
9666 equivalent to a constant. This should be rare. */
9667 x
= GEN_INT (outer_const
);
9668 else if (GET_RTX_CLASS (outer_op
) == '1')
9669 x
= gen_unary (outer_op
, result_mode
, result_mode
, x
);
9671 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9677 /* Like recog, but we receive the address of a pointer to a new pattern.
9678 We try to match the rtx that the pointer points to.
9679 If that fails, we may try to modify or replace the pattern,
9680 storing the replacement into the same pointer object.
9682 Modifications include deletion or addition of CLOBBERs.
9684 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9685 the CLOBBERs are placed.
9687 The value is the final insn code from the pattern ultimately matched,
9691 recog_for_combine (pnewpat
, insn
, pnotes
)
9696 register rtx pat
= *pnewpat
;
9697 int insn_code_number
;
9698 int num_clobbers_to_add
= 0;
9703 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9704 we use to indicate that something didn't match. If we find such a
9705 thing, force rejection. */
9706 if (GET_CODE (pat
) == PARALLEL
)
9707 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9708 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9709 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9712 /* Remove the old notes prior to trying to recognize the new pattern. */
9713 old_notes
= REG_NOTES (insn
);
9714 REG_NOTES (insn
) = 0;
9716 /* Is the result of combination a valid instruction? */
9717 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9719 /* If it isn't, there is the possibility that we previously had an insn
9720 that clobbered some register as a side effect, but the combined
9721 insn doesn't need to do that. So try once more without the clobbers
9722 unless this represents an ASM insn. */
9724 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9725 && GET_CODE (pat
) == PARALLEL
)
9729 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9730 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9733 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9737 SUBST_INT (XVECLEN (pat
, 0), pos
);
9740 pat
= XVECEXP (pat
, 0, 0);
9742 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9745 REG_NOTES (insn
) = old_notes
;
9747 /* If we had any clobbers to add, make a new pattern than contains
9748 them. Then check to make sure that all of them are dead. */
9749 if (num_clobbers_to_add
)
9751 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9752 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9754 + num_clobbers_to_add
)
9755 : num_clobbers_to_add
+ 1));
9757 if (GET_CODE (pat
) == PARALLEL
)
9758 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9759 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9761 XVECEXP (newpat
, 0, 0) = pat
;
9763 add_clobbers (newpat
, insn_code_number
);
9765 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9766 i
< XVECLEN (newpat
, 0); i
++)
9768 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9769 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9771 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9772 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9780 return insn_code_number
;
9783 /* Like gen_lowpart but for use by combine. In combine it is not possible
9784 to create any new pseudoregs. However, it is safe to create
9785 invalid memory addresses, because combine will try to recognize
9786 them and all they will do is make the combine attempt fail.
9788 If for some reason this cannot do its job, an rtx
9789 (clobber (const_int 0)) is returned.
9790 An insn containing that will not be recognized. */
9795 gen_lowpart_for_combine (mode
, x
)
9796 enum machine_mode mode
;
9801 if (GET_MODE (x
) == mode
)
9804 /* We can only support MODE being wider than a word if X is a
9805 constant integer or has a mode the same size. */
9807 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9808 && ! ((GET_MODE (x
) == VOIDmode
9809 && (GET_CODE (x
) == CONST_INT
9810 || GET_CODE (x
) == CONST_DOUBLE
))
9811 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9812 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9814 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9815 won't know what to do. So we will strip off the SUBREG here and
9816 process normally. */
9817 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9820 if (GET_MODE (x
) == mode
)
9824 result
= gen_lowpart_common (mode
, x
);
9825 #ifdef CLASS_CANNOT_CHANGE_MODE
9827 && GET_CODE (result
) == SUBREG
9828 && GET_CODE (SUBREG_REG (result
)) == REG
9829 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
9830 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result
),
9831 GET_MODE (SUBREG_REG (result
))))
9832 REG_CHANGES_MODE (REGNO (SUBREG_REG (result
))) = 1;
9838 if (GET_CODE (x
) == MEM
)
9840 register int offset
= 0;
9843 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9845 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9846 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9848 /* If we want to refer to something bigger than the original memref,
9849 generate a perverse subreg instead. That will force a reload
9850 of the original memref X. */
9851 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9852 return gen_rtx_SUBREG (mode
, x
, 0);
9854 if (WORDS_BIG_ENDIAN
)
9855 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9856 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9858 if (BYTES_BIG_ENDIAN
)
9860 /* Adjust the address so that the address-after-the-data is
9862 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9863 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9865 new = gen_rtx_MEM (mode
, plus_constant (XEXP (x
, 0), offset
));
9866 MEM_COPY_ATTRIBUTES (new, x
);
9870 /* If X is a comparison operator, rewrite it in a new mode. This
9871 probably won't match, but may allow further simplifications. */
9872 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
9873 return gen_rtx_combine (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9875 /* If we couldn't simplify X any other way, just enclose it in a
9876 SUBREG. Normally, this SUBREG won't match, but some patterns may
9877 include an explicit SUBREG or we may simplify it further in combine. */
9882 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
9883 word
= ((GET_MODE_SIZE (GET_MODE (x
))
9884 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
9886 return gen_rtx_SUBREG (mode
, x
, word
);
9890 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9891 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9893 If the identical expression was previously in the insn (in the undobuf),
9894 it will be returned. Only if it is not found will a new expression
9899 gen_rtx_combine
VPARAMS ((enum rtx_code code
, enum machine_mode mode
, ...))
9901 #ifndef ANSI_PROTOTYPES
9903 enum machine_mode mode
;
9915 #ifndef ANSI_PROTOTYPES
9916 code
= va_arg (p
, enum rtx_code
);
9917 mode
= va_arg (p
, enum machine_mode
);
9920 n_args
= GET_RTX_LENGTH (code
);
9921 fmt
= GET_RTX_FORMAT (code
);
9923 if (n_args
== 0 || n_args
> 3)
9926 /* Get each arg and verify that it is supposed to be an expression. */
9927 for (j
= 0; j
< n_args
; j
++)
9932 args
[j
] = va_arg (p
, rtx
);
9937 /* See if this is in undobuf. Be sure we don't use objects that came
9938 from another insn; this could produce circular rtl structures. */
9940 for (undo
= undobuf
.undos
; undo
!= undobuf
.previous_undos
; undo
= undo
->next
)
9942 && GET_CODE (undo
->old_contents
.r
) == code
9943 && GET_MODE (undo
->old_contents
.r
) == mode
)
9945 for (j
= 0; j
< n_args
; j
++)
9946 if (XEXP (undo
->old_contents
.r
, j
) != args
[j
])
9950 return undo
->old_contents
.r
;
9953 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9954 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9955 rt
= rtx_alloc (code
);
9956 PUT_MODE (rt
, mode
);
9957 XEXP (rt
, 0) = args
[0];
9960 XEXP (rt
, 1) = args
[1];
9962 XEXP (rt
, 2) = args
[2];
9967 /* These routines make binary and unary operations by first seeing if they
9968 fold; if not, a new expression is allocated. */
9971 gen_binary (code
, mode
, op0
, op1
)
9973 enum machine_mode mode
;
9979 if (GET_RTX_CLASS (code
) == 'c'
9980 && (GET_CODE (op0
) == CONST_INT
9981 || (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)))
9982 tem
= op0
, op0
= op1
, op1
= tem
;
9984 if (GET_RTX_CLASS (code
) == '<')
9986 enum machine_mode op_mode
= GET_MODE (op0
);
9988 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9989 just (REL_OP X Y). */
9990 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
9992 op1
= XEXP (op0
, 1);
9993 op0
= XEXP (op0
, 0);
9994 op_mode
= GET_MODE (op0
);
9997 if (op_mode
== VOIDmode
)
9998 op_mode
= GET_MODE (op1
);
9999 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
10002 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10007 /* Put complex operands first and constants second. */
10008 if (GET_RTX_CLASS (code
) == 'c'
10009 && ((CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
10010 || (GET_RTX_CLASS (GET_CODE (op0
)) == 'o'
10011 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')
10012 || (GET_CODE (op0
) == SUBREG
10013 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0
))) == 'o'
10014 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')))
10015 return gen_rtx_combine (code
, mode
, op1
, op0
);
10017 /* If we are turning off bits already known off in OP0, we need not do
10019 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10020 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10021 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10024 return gen_rtx_combine (code
, mode
, op0
, op1
);
10028 gen_unary (code
, mode
, op0_mode
, op0
)
10029 enum rtx_code code
;
10030 enum machine_mode mode
, op0_mode
;
10033 rtx result
= simplify_unary_operation (code
, mode
, op0
, op0_mode
);
10038 return gen_rtx_combine (code
, mode
, op0
);
10041 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10042 comparison code that will be tested.
10044 The result is a possibly different comparison code to use. *POP0 and
10045 *POP1 may be updated.
10047 It is possible that we might detect that a comparison is either always
10048 true or always false. However, we do not perform general constant
10049 folding in combine, so this knowledge isn't useful. Such tautologies
10050 should have been detected earlier. Hence we ignore all such cases. */
10052 static enum rtx_code
10053 simplify_comparison (code
, pop0
, pop1
)
10054 enum rtx_code code
;
10062 enum machine_mode mode
, tmode
;
10064 /* Try a few ways of applying the same transformation to both operands. */
10067 #ifndef WORD_REGISTER_OPERATIONS
10068 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10069 so check specially. */
10070 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10071 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10072 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10073 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10074 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10075 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10076 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10077 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10078 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10079 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
10080 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10081 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
10082 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
10083 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
10084 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
10085 && (INTVAL (XEXP (op0
, 1))
10086 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10087 - (GET_MODE_BITSIZE
10088 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10090 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10091 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10095 /* If both operands are the same constant shift, see if we can ignore the
10096 shift. We can if the shift is a rotate or if the bits shifted out of
10097 this shift are known to be zero for both inputs and if the type of
10098 comparison is compatible with the shift. */
10099 if (GET_CODE (op0
) == GET_CODE (op1
)
10100 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10101 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10102 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10103 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10104 || (GET_CODE (op0
) == ASHIFTRT
10105 && (code
!= GTU
&& code
!= LTU
10106 && code
!= GEU
&& code
!= GEU
)))
10107 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10108 && INTVAL (XEXP (op0
, 1)) >= 0
10109 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10110 && XEXP (op0
, 1) == XEXP (op1
, 1))
10112 enum machine_mode mode
= GET_MODE (op0
);
10113 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10114 int shift_count
= INTVAL (XEXP (op0
, 1));
10116 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10117 mask
&= (mask
>> shift_count
) << shift_count
;
10118 else if (GET_CODE (op0
) == ASHIFT
)
10119 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10121 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10122 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10123 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10128 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10129 SUBREGs are of the same mode, and, in both cases, the AND would
10130 be redundant if the comparison was done in the narrower mode,
10131 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10132 and the operand's possibly nonzero bits are 0xffffff01; in that case
10133 if we only care about QImode, we don't need the AND). This case
10134 occurs if the output mode of an scc insn is not SImode and
10135 STORE_FLAG_VALUE == 1 (e.g., the 386).
10137 Similarly, check for a case where the AND's are ZERO_EXTEND
10138 operations from some narrower mode even though a SUBREG is not
10141 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10142 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10143 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10145 rtx inner_op0
= XEXP (op0
, 0);
10146 rtx inner_op1
= XEXP (op1
, 0);
10147 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10148 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10151 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10152 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10153 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10154 && (GET_MODE (SUBREG_REG (inner_op0
))
10155 == GET_MODE (SUBREG_REG (inner_op1
)))
10156 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10157 <= HOST_BITS_PER_WIDE_INT
)
10158 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10159 GET_MODE (SUBREG_REG (inner_op0
)))))
10160 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10161 GET_MODE (SUBREG_REG (inner_op1
))))))
10163 op0
= SUBREG_REG (inner_op0
);
10164 op1
= SUBREG_REG (inner_op1
);
10166 /* The resulting comparison is always unsigned since we masked
10167 off the original sign bit. */
10168 code
= unsigned_condition (code
);
10174 for (tmode
= GET_CLASS_NARROWEST_MODE
10175 (GET_MODE_CLASS (GET_MODE (op0
)));
10176 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10177 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10179 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
10180 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
10181 code
= unsigned_condition (code
);
10190 /* If both operands are NOT, we can strip off the outer operation
10191 and adjust the comparison code for swapped operands; similarly for
10192 NEG, except that this must be an equality comparison. */
10193 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10194 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10195 && (code
== EQ
|| code
== NE
)))
10196 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10202 /* If the first operand is a constant, swap the operands and adjust the
10203 comparison code appropriately, but don't do this if the second operand
10204 is already a constant integer. */
10205 if (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
10207 tem
= op0
, op0
= op1
, op1
= tem
;
10208 code
= swap_condition (code
);
10211 /* We now enter a loop during which we will try to simplify the comparison.
10212 For the most part, we only are concerned with comparisons with zero,
10213 but some things may really be comparisons with zero but not start
10214 out looking that way. */
10216 while (GET_CODE (op1
) == CONST_INT
)
10218 enum machine_mode mode
= GET_MODE (op0
);
10219 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10220 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10221 int equality_comparison_p
;
10222 int sign_bit_comparison_p
;
10223 int unsigned_comparison_p
;
10224 HOST_WIDE_INT const_op
;
10226 /* We only want to handle integral modes. This catches VOIDmode,
10227 CCmode, and the floating-point modes. An exception is that we
10228 can handle VOIDmode if OP0 is a COMPARE or a comparison
10231 if (GET_MODE_CLASS (mode
) != MODE_INT
10232 && ! (mode
== VOIDmode
10233 && (GET_CODE (op0
) == COMPARE
10234 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10237 /* Get the constant we are comparing against and turn off all bits
10238 not on in our mode. */
10239 const_op
= trunc_int_for_mode (INTVAL (op1
), mode
);
10241 /* If we are comparing against a constant power of two and the value
10242 being compared can only have that single bit nonzero (e.g., it was
10243 `and'ed with that bit), we can replace this with a comparison
10246 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10247 || code
== LT
|| code
== LTU
)
10248 && mode_width
<= HOST_BITS_PER_WIDE_INT
10249 && exact_log2 (const_op
) >= 0
10250 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10252 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10253 op1
= const0_rtx
, const_op
= 0;
10256 /* Similarly, if we are comparing a value known to be either -1 or
10257 0 with -1, change it to the opposite comparison against zero. */
10260 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10261 || code
== GEU
|| code
== LTU
)
10262 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10264 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10265 op1
= const0_rtx
, const_op
= 0;
10268 /* Do some canonicalizations based on the comparison code. We prefer
10269 comparisons against zero and then prefer equality comparisons.
10270 If we can reduce the size of a constant, we will do that too. */
10275 /* < C is equivalent to <= (C - 1) */
10279 op1
= GEN_INT (const_op
);
10281 /* ... fall through to LE case below. */
10287 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10291 op1
= GEN_INT (const_op
);
10295 /* If we are doing a <= 0 comparison on a value known to have
10296 a zero sign bit, we can replace this with == 0. */
10297 else if (const_op
== 0
10298 && mode_width
<= HOST_BITS_PER_WIDE_INT
10299 && (nonzero_bits (op0
, mode
)
10300 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10305 /* >= C is equivalent to > (C - 1). */
10309 op1
= GEN_INT (const_op
);
10311 /* ... fall through to GT below. */
10317 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10321 op1
= GEN_INT (const_op
);
10325 /* If we are doing a > 0 comparison on a value known to have
10326 a zero sign bit, we can replace this with != 0. */
10327 else if (const_op
== 0
10328 && mode_width
<= HOST_BITS_PER_WIDE_INT
10329 && (nonzero_bits (op0
, mode
)
10330 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10335 /* < C is equivalent to <= (C - 1). */
10339 op1
= GEN_INT (const_op
);
10341 /* ... fall through ... */
10344 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10345 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10346 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10348 const_op
= 0, op1
= const0_rtx
;
10356 /* unsigned <= 0 is equivalent to == 0 */
10360 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10361 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10362 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10364 const_op
= 0, op1
= const0_rtx
;
10370 /* >= C is equivalent to < (C - 1). */
10374 op1
= GEN_INT (const_op
);
10376 /* ... fall through ... */
10379 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10380 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10381 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10383 const_op
= 0, op1
= const0_rtx
;
10391 /* unsigned > 0 is equivalent to != 0 */
10395 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10396 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10397 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10399 const_op
= 0, op1
= const0_rtx
;
10408 /* Compute some predicates to simplify code below. */
10410 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10411 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10412 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10415 /* If this is a sign bit comparison and we can do arithmetic in
10416 MODE, say that we will only be needing the sign bit of OP0. */
10417 if (sign_bit_comparison_p
10418 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10419 op0
= force_to_mode (op0
, mode
,
10421 << (GET_MODE_BITSIZE (mode
) - 1)),
10424 /* Now try cases based on the opcode of OP0. If none of the cases
10425 does a "continue", we exit this loop immediately after the
10428 switch (GET_CODE (op0
))
10431 /* If we are extracting a single bit from a variable position in
10432 a constant that has only a single bit set and are comparing it
10433 with zero, we can convert this into an equality comparison
10434 between the position and the location of the single bit. */
10436 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10437 && XEXP (op0
, 1) == const1_rtx
10438 && equality_comparison_p
&& const_op
== 0
10439 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10441 if (BITS_BIG_ENDIAN
)
10444 mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
10445 if (mode
== VOIDmode
)
10447 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10449 i
= BITS_PER_WORD
- 1 - i
;
10453 op0
= XEXP (op0
, 2);
10457 /* Result is nonzero iff shift count is equal to I. */
10458 code
= reverse_condition (code
);
10462 /* ... fall through ... */
10465 tem
= expand_compound_operation (op0
);
10474 /* If testing for equality, we can take the NOT of the constant. */
10475 if (equality_comparison_p
10476 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10478 op0
= XEXP (op0
, 0);
10483 /* If just looking at the sign bit, reverse the sense of the
10485 if (sign_bit_comparison_p
)
10487 op0
= XEXP (op0
, 0);
10488 code
= (code
== GE
? LT
: GE
);
10494 /* If testing for equality, we can take the NEG of the constant. */
10495 if (equality_comparison_p
10496 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10498 op0
= XEXP (op0
, 0);
10503 /* The remaining cases only apply to comparisons with zero. */
10507 /* When X is ABS or is known positive,
10508 (neg X) is < 0 if and only if X != 0. */
10510 if (sign_bit_comparison_p
10511 && (GET_CODE (XEXP (op0
, 0)) == ABS
10512 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10513 && (nonzero_bits (XEXP (op0
, 0), mode
)
10514 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10516 op0
= XEXP (op0
, 0);
10517 code
= (code
== LT
? NE
: EQ
);
10521 /* If we have NEG of something whose two high-order bits are the
10522 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10523 if (num_sign_bit_copies (op0
, mode
) >= 2)
10525 op0
= XEXP (op0
, 0);
10526 code
= swap_condition (code
);
10532 /* If we are testing equality and our count is a constant, we
10533 can perform the inverse operation on our RHS. */
10534 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10535 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10536 op1
, XEXP (op0
, 1))) != 0)
10538 op0
= XEXP (op0
, 0);
10543 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10544 a particular bit. Convert it to an AND of a constant of that
10545 bit. This will be converted into a ZERO_EXTRACT. */
10546 if (const_op
== 0 && sign_bit_comparison_p
10547 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10548 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10550 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10553 - INTVAL (XEXP (op0
, 1)))));
10554 code
= (code
== LT
? NE
: EQ
);
10558 /* Fall through. */
10561 /* ABS is ignorable inside an equality comparison with zero. */
10562 if (const_op
== 0 && equality_comparison_p
)
10564 op0
= XEXP (op0
, 0);
10570 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10571 to (compare FOO CONST) if CONST fits in FOO's mode and we
10572 are either testing inequality or have an unsigned comparison
10573 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10574 if (! unsigned_comparison_p
10575 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10576 <= HOST_BITS_PER_WIDE_INT
)
10577 && ((unsigned HOST_WIDE_INT
) const_op
10578 < (((unsigned HOST_WIDE_INT
) 1
10579 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10581 op0
= XEXP (op0
, 0);
10587 /* Check for the case where we are comparing A - C1 with C2,
10588 both constants are smaller than 1/2 the maximum positive
10589 value in MODE, and the comparison is equality or unsigned.
10590 In that case, if A is either zero-extended to MODE or has
10591 sufficient sign bits so that the high-order bit in MODE
10592 is a copy of the sign in the inner mode, we can prove that it is
10593 safe to do the operation in the wider mode. This simplifies
10594 many range checks. */
10596 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10597 && subreg_lowpart_p (op0
)
10598 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10599 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10600 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10601 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10602 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10603 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10604 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10605 GET_MODE (SUBREG_REG (op0
)))
10606 & ~GET_MODE_MASK (mode
))
10607 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10608 GET_MODE (SUBREG_REG (op0
)))
10609 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10610 - GET_MODE_BITSIZE (mode
)))))
10612 op0
= SUBREG_REG (op0
);
10616 /* If the inner mode is narrower and we are extracting the low part,
10617 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10618 if (subreg_lowpart_p (op0
)
10619 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10620 /* Fall through */ ;
10624 /* ... fall through ... */
10627 if ((unsigned_comparison_p
|| equality_comparison_p
)
10628 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10629 <= HOST_BITS_PER_WIDE_INT
)
10630 && ((unsigned HOST_WIDE_INT
) const_op
10631 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10633 op0
= XEXP (op0
, 0);
10639 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10640 this for equality comparisons due to pathological cases involving
10642 if (equality_comparison_p
10643 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10644 op1
, XEXP (op0
, 1))))
10646 op0
= XEXP (op0
, 0);
10651 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10652 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10653 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10655 op0
= XEXP (XEXP (op0
, 0), 0);
10656 code
= (code
== LT
? EQ
: NE
);
10662 /* We used to optimize signed comparisons against zero, but that
10663 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10664 arrive here as equality comparisons, or (GEU, LTU) are
10665 optimized away. No need to special-case them. */
10667 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10668 (eq B (minus A C)), whichever simplifies. We can only do
10669 this for equality comparisons due to pathological cases involving
10671 if (equality_comparison_p
10672 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10673 XEXP (op0
, 1), op1
)))
10675 op0
= XEXP (op0
, 0);
10680 if (equality_comparison_p
10681 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10682 XEXP (op0
, 0), op1
)))
10684 op0
= XEXP (op0
, 1);
10689 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10690 of bits in X minus 1, is one iff X > 0. */
10691 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10692 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10693 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
10694 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10696 op0
= XEXP (op0
, 1);
10697 code
= (code
== GE
? LE
: GT
);
10703 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10704 if C is zero or B is a constant. */
10705 if (equality_comparison_p
10706 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10707 XEXP (op0
, 1), op1
)))
10709 op0
= XEXP (op0
, 0);
10716 case UNEQ
: case LTGT
:
10717 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10718 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10719 case UNORDERED
: case ORDERED
:
10720 /* We can't do anything if OP0 is a condition code value, rather
10721 than an actual data value. */
10724 || XEXP (op0
, 0) == cc0_rtx
10726 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10729 /* Get the two operands being compared. */
10730 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10731 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10733 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10735 /* Check for the cases where we simply want the result of the
10736 earlier test or the opposite of that result. */
10737 if (code
== NE
|| code
== EQ
10738 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10739 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10740 && (STORE_FLAG_VALUE
10741 & (((HOST_WIDE_INT
) 1
10742 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10743 && (code
== LT
|| code
== GE
)))
10745 enum rtx_code new_code
;
10746 if (code
== LT
|| code
== NE
)
10747 new_code
= GET_CODE (op0
);
10749 new_code
= combine_reversed_comparison_code (op0
);
10751 if (new_code
!= UNKNOWN
)
10762 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10764 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10765 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10766 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10768 op0
= XEXP (op0
, 1);
10769 code
= (code
== GE
? GT
: LE
);
10775 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10776 will be converted to a ZERO_EXTRACT later. */
10777 if (const_op
== 0 && equality_comparison_p
10778 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10779 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10781 op0
= simplify_and_const_int
10782 (op0
, mode
, gen_rtx_combine (LSHIFTRT
, mode
,
10784 XEXP (XEXP (op0
, 0), 1)),
10785 (HOST_WIDE_INT
) 1);
10789 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10790 zero and X is a comparison and C1 and C2 describe only bits set
10791 in STORE_FLAG_VALUE, we can compare with X. */
10792 if (const_op
== 0 && equality_comparison_p
10793 && mode_width
<= HOST_BITS_PER_WIDE_INT
10794 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10795 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10796 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10797 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10798 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10800 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10801 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10802 if ((~STORE_FLAG_VALUE
& mask
) == 0
10803 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10804 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10805 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10807 op0
= XEXP (XEXP (op0
, 0), 0);
10812 /* If we are doing an equality comparison of an AND of a bit equal
10813 to the sign bit, replace this with a LT or GE comparison of
10814 the underlying value. */
10815 if (equality_comparison_p
10817 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10818 && mode_width
<= HOST_BITS_PER_WIDE_INT
10819 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10820 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10822 op0
= XEXP (op0
, 0);
10823 code
= (code
== EQ
? GE
: LT
);
10827 /* If this AND operation is really a ZERO_EXTEND from a narrower
10828 mode, the constant fits within that mode, and this is either an
10829 equality or unsigned comparison, try to do this comparison in
10830 the narrower mode. */
10831 if ((equality_comparison_p
|| unsigned_comparison_p
)
10832 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10833 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10834 & GET_MODE_MASK (mode
))
10836 && const_op
>> i
== 0
10837 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10839 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10843 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10844 in both M1 and M2 and the SUBREG is either paradoxical or
10845 represents the low part, permute the SUBREG and the AND and
10847 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
10849 #ifdef WORD_REGISTER_OPERATIONS
10851 > (GET_MODE_BITSIZE
10852 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10853 && mode_width
<= BITS_PER_WORD
)
10856 <= (GET_MODE_BITSIZE
10857 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10858 && subreg_lowpart_p (XEXP (op0
, 0))))
10859 #ifndef WORD_REGISTER_OPERATIONS
10860 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10861 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10862 As originally written the upper bits have a defined value
10863 due to the AND operation. However, if we commute the AND
10864 inside the SUBREG then they no longer have defined values
10865 and the meaning of the code has been changed. */
10866 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
10867 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10869 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10870 && mode_width
<= HOST_BITS_PER_WIDE_INT
10871 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10872 <= HOST_BITS_PER_WIDE_INT
)
10873 && (INTVAL (XEXP (op0
, 1)) & ~mask
) == 0
10874 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10875 & INTVAL (XEXP (op0
, 1)))
10876 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
10877 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10878 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10882 = gen_lowpart_for_combine
10884 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
10885 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
10889 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10890 (eq (and (lshiftrt X) 1) 0). */
10891 if (const_op
== 0 && equality_comparison_p
10892 && XEXP (op0
, 1) == const1_rtx
10893 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10894 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == NOT
)
10896 op0
= simplify_and_const_int
10897 (op0
, mode
, gen_rtx_combine (LSHIFTRT
, mode
,
10898 XEXP (XEXP (XEXP (op0
, 0), 0), 0),
10899 XEXP (XEXP (op0
, 0), 1)),
10900 (HOST_WIDE_INT
) 1);
10901 code
= (code
== NE
? EQ
: NE
);
10907 /* If we have (compare (ashift FOO N) (const_int C)) and
10908 the high order N bits of FOO (N+1 if an inequality comparison)
10909 are known to be zero, we can do this by comparing FOO with C
10910 shifted right N bits so long as the low-order N bits of C are
10912 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10913 && INTVAL (XEXP (op0
, 1)) >= 0
10914 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10915 < HOST_BITS_PER_WIDE_INT
)
10917 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10918 && mode_width
<= HOST_BITS_PER_WIDE_INT
10919 && (nonzero_bits (XEXP (op0
, 0), mode
)
10920 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
10921 + ! equality_comparison_p
))) == 0)
10923 /* We must perform a logical shift, not an arithmetic one,
10924 as we want the top N bits of C to be zero. */
10925 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10927 temp
>>= INTVAL (XEXP (op0
, 1));
10928 op1
= GEN_INT (trunc_int_for_mode (temp
, mode
));
10929 op0
= XEXP (op0
, 0);
10933 /* If we are doing a sign bit comparison, it means we are testing
10934 a particular bit. Convert it to the appropriate AND. */
10935 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10936 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10938 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10941 - INTVAL (XEXP (op0
, 1)))));
10942 code
= (code
== LT
? NE
: EQ
);
10946 /* If this an equality comparison with zero and we are shifting
10947 the low bit to the sign bit, we can convert this to an AND of the
10949 if (const_op
== 0 && equality_comparison_p
10950 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10951 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10953 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10954 (HOST_WIDE_INT
) 1);
10960 /* If this is an equality comparison with zero, we can do this
10961 as a logical shift, which might be much simpler. */
10962 if (equality_comparison_p
&& const_op
== 0
10963 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10965 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10967 INTVAL (XEXP (op0
, 1)));
10971 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10972 do the comparison in a narrower mode. */
10973 if (! unsigned_comparison_p
10974 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10975 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10976 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10977 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10978 MODE_INT
, 1)) != BLKmode
10979 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10980 || ((unsigned HOST_WIDE_INT
) -const_op
10981 <= GET_MODE_MASK (tmode
))))
10983 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
10987 /* Likewise if OP0 is a PLUS of a sign extension with a
10988 constant, which is usually represented with the PLUS
10989 between the shifts. */
10990 if (! unsigned_comparison_p
10991 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10992 && GET_CODE (XEXP (op0
, 0)) == PLUS
10993 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10994 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10995 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10996 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10997 MODE_INT
, 1)) != BLKmode
10998 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10999 || ((unsigned HOST_WIDE_INT
) -const_op
11000 <= GET_MODE_MASK (tmode
))))
11002 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11003 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11004 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11007 op0
= gen_binary (PLUS
, tmode
,
11008 gen_lowpart_for_combine (tmode
, inner
),
11013 /* ... fall through ... */
11015 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11016 the low order N bits of FOO are known to be zero, we can do this
11017 by comparing FOO with C shifted left N bits so long as no
11018 overflow occurs. */
11019 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11020 && INTVAL (XEXP (op0
, 1)) >= 0
11021 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11022 && mode_width
<= HOST_BITS_PER_WIDE_INT
11023 && (nonzero_bits (XEXP (op0
, 0), mode
)
11024 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11026 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
11029 const_op
<<= INTVAL (XEXP (op0
, 1));
11030 op1
= GEN_INT (const_op
);
11031 op0
= XEXP (op0
, 0);
11035 /* If we are using this shift to extract just the sign bit, we
11036 can replace this with an LT or GE comparison. */
11038 && (equality_comparison_p
|| sign_bit_comparison_p
)
11039 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11040 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11042 op0
= XEXP (op0
, 0);
11043 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11055 /* Now make any compound operations involved in this comparison. Then,
11056 check for an outmost SUBREG on OP0 that is not doing anything or is
11057 paradoxical. The latter case can only occur when it is known that the
11058 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
11059 We can never remove a SUBREG for a non-equality comparison because the
11060 sign bit is in a different place in the underlying object. */
11062 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11063 op1
= make_compound_operation (op1
, SET
);
11065 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11066 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11067 && (code
== NE
|| code
== EQ
)
11068 && ((GET_MODE_SIZE (GET_MODE (op0
))
11069 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
11071 op0
= SUBREG_REG (op0
);
11072 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
11075 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11076 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11077 && (code
== NE
|| code
== EQ
)
11078 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11079 <= HOST_BITS_PER_WIDE_INT
)
11080 && (nonzero_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
11081 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0
11082 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
11084 (nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11085 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0))
11086 op0
= SUBREG_REG (op0
), op1
= tem
;
11088 /* We now do the opposite procedure: Some machines don't have compare
11089 insns in all modes. If OP0's mode is an integer mode smaller than a
11090 word and we can't do a compare in that mode, see if there is a larger
11091 mode for which we can do the compare. There are a number of cases in
11092 which we can use the wider mode. */
11094 mode
= GET_MODE (op0
);
11095 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11096 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11097 && cmp_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
)
11098 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11100 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11101 tmode
= GET_MODE_WIDER_MODE (tmode
))
11102 if (cmp_optab
->handlers
[(int) tmode
].insn_code
!= CODE_FOR_nothing
)
11104 /* If the only nonzero bits in OP0 and OP1 are those in the
11105 narrower mode and this is an equality or unsigned comparison,
11106 we can use the wider mode. Similarly for sign-extended
11107 values, in which case it is true for all comparisons. */
11108 if (((code
== EQ
|| code
== NE
11109 || code
== GEU
|| code
== GTU
|| code
== LEU
|| code
== LTU
)
11110 && (nonzero_bits (op0
, tmode
) & ~GET_MODE_MASK (mode
)) == 0
11111 && (nonzero_bits (op1
, tmode
) & ~GET_MODE_MASK (mode
)) == 0)
11112 || ((num_sign_bit_copies (op0
, tmode
)
11113 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))
11114 && (num_sign_bit_copies (op1
, tmode
)
11115 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))))
11117 /* If OP0 is an AND and we don't have an AND in MODE either,
11118 make a new AND in the proper mode. */
11119 if (GET_CODE (op0
) == AND
11120 && (add_optab
->handlers
[(int) mode
].insn_code
11121 == CODE_FOR_nothing
))
11122 op0
= gen_binary (AND
, tmode
,
11123 gen_lowpart_for_combine (tmode
,
11125 gen_lowpart_for_combine (tmode
,
11128 op0
= gen_lowpart_for_combine (tmode
, op0
);
11129 op1
= gen_lowpart_for_combine (tmode
, op1
);
11133 /* If this is a test for negative, we can make an explicit
11134 test of the sign bit. */
11136 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11137 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11139 op0
= gen_binary (AND
, tmode
,
11140 gen_lowpart_for_combine (tmode
, op0
),
11141 GEN_INT ((HOST_WIDE_INT
) 1
11142 << (GET_MODE_BITSIZE (mode
) - 1)));
11143 code
= (code
== LT
) ? NE
: EQ
;
11148 #ifdef CANONICALIZE_COMPARISON
11149 /* If this machine only supports a subset of valid comparisons, see if we
11150 can convert an unsupported one into a supported one. */
11151 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11160 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11161 searching backward. */
11162 static enum rtx_code
11163 combine_reversed_comparison_code (exp
)
11166 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11169 if (code1
!= UNKNOWN
11170 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11172 /* Otherwise try and find where the condition codes were last set and
11174 x
= get_last_value (XEXP (exp
, 0));
11175 if (!x
|| GET_CODE (x
) != COMPARE
)
11177 return reversed_comparison_code_parts (GET_CODE (exp
),
11178 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11180 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11181 Return NULL_RTX in case we fail to do the reversal. */
11183 reversed_comparison (exp
, mode
, op0
, op1
)
11185 enum machine_mode mode
;
11187 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11188 if (reversed_code
== UNKNOWN
)
11191 return gen_binary (reversed_code
, mode
, op0
, op1
);
11194 /* Utility function for following routine. Called when X is part of a value
11195 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11196 for each register mentioned. Similar to mention_regs in cse.c */
11199 update_table_tick (x
)
11202 register enum rtx_code code
= GET_CODE (x
);
11203 register const char *fmt
= GET_RTX_FORMAT (code
);
11208 unsigned int regno
= REGNO (x
);
11209 unsigned int endregno
11210 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11211 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11214 for (r
= regno
; r
< endregno
; r
++)
11215 reg_last_set_table_tick
[r
] = label_tick
;
11220 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11221 /* Note that we can't have an "E" in values stored; see
11222 get_last_value_validate. */
11224 update_table_tick (XEXP (x
, i
));
11227 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11228 are saying that the register is clobbered and we no longer know its
11229 value. If INSN is zero, don't update reg_last_set; this is only permitted
11230 with VALUE also zero and is used to invalidate the register. */
11233 record_value_for_reg (reg
, insn
, value
)
11238 unsigned int regno
= REGNO (reg
);
11239 unsigned int endregno
11240 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11241 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11244 /* If VALUE contains REG and we have a previous value for REG, substitute
11245 the previous value. */
11246 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11250 /* Set things up so get_last_value is allowed to see anything set up to
11252 subst_low_cuid
= INSN_CUID (insn
);
11253 tem
= get_last_value (reg
);
11255 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11256 it isn't going to be useful and will take a lot of time to process,
11257 so just use the CLOBBER. */
11261 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11262 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11263 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11264 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11265 tem
= XEXP (tem
, 0);
11267 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11271 /* For each register modified, show we don't know its value, that
11272 we don't know about its bitwise content, that its value has been
11273 updated, and that we don't know the location of the death of the
11275 for (i
= regno
; i
< endregno
; i
++)
11278 reg_last_set
[i
] = insn
;
11280 reg_last_set_value
[i
] = 0;
11281 reg_last_set_mode
[i
] = 0;
11282 reg_last_set_nonzero_bits
[i
] = 0;
11283 reg_last_set_sign_bit_copies
[i
] = 0;
11284 reg_last_death
[i
] = 0;
11287 /* Mark registers that are being referenced in this value. */
11289 update_table_tick (value
);
11291 /* Now update the status of each register being set.
11292 If someone is using this register in this block, set this register
11293 to invalid since we will get confused between the two lives in this
11294 basic block. This makes using this register always invalid. In cse, we
11295 scan the table to invalidate all entries using this register, but this
11296 is too much work for us. */
11298 for (i
= regno
; i
< endregno
; i
++)
11300 reg_last_set_label
[i
] = label_tick
;
11301 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11302 reg_last_set_invalid
[i
] = 1;
11304 reg_last_set_invalid
[i
] = 0;
11307 /* The value being assigned might refer to X (like in "x++;"). In that
11308 case, we must replace it with (clobber (const_int 0)) to prevent
11310 if (value
&& ! get_last_value_validate (&value
, insn
,
11311 reg_last_set_label
[regno
], 0))
11313 value
= copy_rtx (value
);
11314 if (! get_last_value_validate (&value
, insn
,
11315 reg_last_set_label
[regno
], 1))
11319 /* For the main register being modified, update the value, the mode, the
11320 nonzero bits, and the number of sign bit copies. */
11322 reg_last_set_value
[regno
] = value
;
11326 subst_low_cuid
= INSN_CUID (insn
);
11327 reg_last_set_mode
[regno
] = GET_MODE (reg
);
11328 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, GET_MODE (reg
));
11329 reg_last_set_sign_bit_copies
[regno
]
11330 = num_sign_bit_copies (value
, GET_MODE (reg
));
11334 /* Called via note_stores from record_dead_and_set_regs to handle one
11335 SET or CLOBBER in an insn. DATA is the instruction in which the
11336 set is occurring. */
11339 record_dead_and_set_regs_1 (dest
, setter
, data
)
11343 rtx record_dead_insn
= (rtx
) data
;
11345 if (GET_CODE (dest
) == SUBREG
)
11346 dest
= SUBREG_REG (dest
);
11348 if (GET_CODE (dest
) == REG
)
11350 /* If we are setting the whole register, we know its value. Otherwise
11351 show that we don't know the value. We can handle SUBREG in
11353 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11354 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11355 else if (GET_CODE (setter
) == SET
11356 && GET_CODE (SET_DEST (setter
)) == SUBREG
11357 && SUBREG_REG (SET_DEST (setter
)) == dest
11358 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11359 && subreg_lowpart_p (SET_DEST (setter
)))
11360 record_value_for_reg (dest
, record_dead_insn
,
11361 gen_lowpart_for_combine (GET_MODE (dest
),
11362 SET_SRC (setter
)));
11364 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11366 else if (GET_CODE (dest
) == MEM
11367 /* Ignore pushes, they clobber nothing. */
11368 && ! push_operand (dest
, GET_MODE (dest
)))
11369 mem_last_set
= INSN_CUID (record_dead_insn
);
11372 /* Update the records of when each REG was most recently set or killed
11373 for the things done by INSN. This is the last thing done in processing
11374 INSN in the combiner loop.
11376 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11377 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11378 and also the similar information mem_last_set (which insn most recently
11379 modified memory) and last_call_cuid (which insn was the most recent
11380 subroutine call). */
11383 record_dead_and_set_regs (insn
)
11389 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11391 if (REG_NOTE_KIND (link
) == REG_DEAD
11392 && GET_CODE (XEXP (link
, 0)) == REG
)
11394 unsigned int regno
= REGNO (XEXP (link
, 0));
11395 unsigned int endregno
11396 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11397 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11400 for (i
= regno
; i
< endregno
; i
++)
11401 reg_last_death
[i
] = insn
;
11403 else if (REG_NOTE_KIND (link
) == REG_INC
)
11404 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11407 if (GET_CODE (insn
) == CALL_INSN
)
11409 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11410 if (call_used_regs
[i
])
11412 reg_last_set_value
[i
] = 0;
11413 reg_last_set_mode
[i
] = 0;
11414 reg_last_set_nonzero_bits
[i
] = 0;
11415 reg_last_set_sign_bit_copies
[i
] = 0;
11416 reg_last_death
[i
] = 0;
11419 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11422 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11425 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11426 register present in the SUBREG, so for each such SUBREG go back and
11427 adjust nonzero and sign bit information of the registers that are
11428 known to have some zero/sign bits set.
11430 This is needed because when combine blows the SUBREGs away, the
11431 information on zero/sign bits is lost and further combines can be
11432 missed because of that. */
11435 record_promoted_value (insn
, subreg
)
11440 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11441 enum machine_mode mode
= GET_MODE (subreg
);
11443 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11446 for (links
= LOG_LINKS (insn
); links
;)
11448 insn
= XEXP (links
, 0);
11449 set
= single_set (insn
);
11451 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11452 || REGNO (SET_DEST (set
)) != regno
11453 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11455 links
= XEXP (links
, 1);
11459 if (reg_last_set
[regno
] == insn
)
11461 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
11462 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11465 if (GET_CODE (SET_SRC (set
)) == REG
)
11467 regno
= REGNO (SET_SRC (set
));
11468 links
= LOG_LINKS (insn
);
11475 /* Scan X for promoted SUBREGs. For each one found,
11476 note what it implies to the registers used in it. */
11479 check_promoted_subreg (insn
, x
)
11483 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11484 && GET_CODE (SUBREG_REG (x
)) == REG
)
11485 record_promoted_value (insn
, x
);
11488 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11491 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11495 check_promoted_subreg (insn
, XEXP (x
, i
));
11499 if (XVEC (x
, i
) != 0)
11500 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11501 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11507 /* Utility routine for the following function. Verify that all the registers
11508 mentioned in *LOC are valid when *LOC was part of a value set when
11509 label_tick == TICK. Return 0 if some are not.
11511 If REPLACE is non-zero, replace the invalid reference with
11512 (clobber (const_int 0)) and return 1. This replacement is useful because
11513 we often can get useful information about the form of a value (e.g., if
11514 it was produced by a shift that always produces -1 or 0) even though
11515 we don't know exactly what registers it was produced from. */
11518 get_last_value_validate (loc
, insn
, tick
, replace
)
11525 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11526 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11529 if (GET_CODE (x
) == REG
)
11531 unsigned int regno
= REGNO (x
);
11532 unsigned int endregno
11533 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11534 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11537 for (j
= regno
; j
< endregno
; j
++)
11538 if (reg_last_set_invalid
[j
]
11539 /* If this is a pseudo-register that was only set once and not
11540 live at the beginning of the function, it is always valid. */
11541 || (! (regno
>= FIRST_PSEUDO_REGISTER
11542 && REG_N_SETS (regno
) == 1
11543 && (! REGNO_REG_SET_P
11544 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))
11545 && reg_last_set_label
[j
] > tick
))
11548 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11554 /* If this is a memory reference, make sure that there were
11555 no stores after it that might have clobbered the value. We don't
11556 have alias info, so we assume any store invalidates it. */
11557 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11558 && INSN_CUID (insn
) <= mem_last_set
)
11561 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11565 for (i
= 0; i
< len
; i
++)
11567 && get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
) == 0)
11568 /* Don't bother with these. They shouldn't occur anyway. */
11572 /* If we haven't found a reason for it to be invalid, it is valid. */
11576 /* Get the last value assigned to X, if known. Some registers
11577 in the value may be replaced with (clobber (const_int 0)) if their value
11578 is known longer known reliably. */
11584 unsigned int regno
;
11587 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11588 then convert it to the desired mode. If this is a paradoxical SUBREG,
11589 we cannot predict what values the "extra" bits might have. */
11590 if (GET_CODE (x
) == SUBREG
11591 && subreg_lowpart_p (x
)
11592 && (GET_MODE_SIZE (GET_MODE (x
))
11593 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11594 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11595 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11597 if (GET_CODE (x
) != REG
)
11601 value
= reg_last_set_value
[regno
];
11603 /* If we don't have a value, or if it isn't for this basic block and
11604 it's either a hard register, set more than once, or it's a live
11605 at the beginning of the function, return 0.
11607 Because if it's not live at the beginnning of the function then the reg
11608 is always set before being used (is never used without being set).
11609 And, if it's set only once, and it's always set before use, then all
11610 uses must have the same last value, even if it's not from this basic
11614 || (reg_last_set_label
[regno
] != label_tick
11615 && (regno
< FIRST_PSEUDO_REGISTER
11616 || REG_N_SETS (regno
) != 1
11617 || (REGNO_REG_SET_P
11618 (BASIC_BLOCK (0)->global_live_at_start
, regno
)))))
11621 /* If the value was set in a later insn than the ones we are processing,
11622 we can't use it even if the register was only set once. */
11623 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11626 /* If the value has all its registers valid, return it. */
11627 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11628 reg_last_set_label
[regno
], 0))
11631 /* Otherwise, make a copy and replace any invalid register with
11632 (clobber (const_int 0)). If that fails for some reason, return 0. */
11634 value
= copy_rtx (value
);
11635 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11636 reg_last_set_label
[regno
], 1))
11642 /* Return nonzero if expression X refers to a REG or to memory
11643 that is set in an instruction more recent than FROM_CUID. */
11646 use_crosses_set_p (x
, from_cuid
)
11650 register const char *fmt
;
11652 register enum rtx_code code
= GET_CODE (x
);
11656 unsigned int regno
= REGNO (x
);
11657 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11658 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11660 #ifdef PUSH_ROUNDING
11661 /* Don't allow uses of the stack pointer to be moved,
11662 because we don't know whether the move crosses a push insn. */
11663 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11666 for (; regno
< endreg
; regno
++)
11667 if (reg_last_set
[regno
]
11668 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11673 if (code
== MEM
&& mem_last_set
> from_cuid
)
11676 fmt
= GET_RTX_FORMAT (code
);
11678 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11683 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11684 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11687 else if (fmt
[i
] == 'e'
11688 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11694 /* Define three variables used for communication between the following
11697 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11698 static int reg_dead_flag
;
11700 /* Function called via note_stores from reg_dead_at_p.
11702 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11703 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11706 reg_dead_at_p_1 (dest
, x
, data
)
11709 void *data ATTRIBUTE_UNUSED
;
11711 unsigned int regno
, endregno
;
11713 if (GET_CODE (dest
) != REG
)
11716 regno
= REGNO (dest
);
11717 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11718 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11720 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11721 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11724 /* Return non-zero if REG is known to be dead at INSN.
11726 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11727 referencing REG, it is dead. If we hit a SET referencing REG, it is
11728 live. Otherwise, see if it is live or dead at the start of the basic
11729 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11730 must be assumed to be always live. */
11733 reg_dead_at_p (reg
, insn
)
11740 /* Set variables for reg_dead_at_p_1. */
11741 reg_dead_regno
= REGNO (reg
);
11742 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11743 ? HARD_REGNO_NREGS (reg_dead_regno
,
11749 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11750 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11752 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11753 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11757 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11758 beginning of function. */
11759 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11760 insn
= prev_nonnote_insn (insn
))
11762 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11764 return reg_dead_flag
== 1 ? 1 : 0;
11766 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11770 /* Get the basic block number that we were in. */
11775 for (block
= 0; block
< n_basic_blocks
; block
++)
11776 if (insn
== BLOCK_HEAD (block
))
11779 if (block
== n_basic_blocks
)
11783 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11784 if (REGNO_REG_SET_P (BASIC_BLOCK (block
)->global_live_at_start
, i
))
11790 /* Note hard registers in X that are used. This code is similar to
11791 that in flow.c, but much simpler since we don't care about pseudos. */
11794 mark_used_regs_combine (x
)
11797 RTX_CODE code
= GET_CODE (x
);
11798 unsigned int regno
;
11810 case ADDR_DIFF_VEC
:
11813 /* CC0 must die in the insn after it is set, so we don't need to take
11814 special note of it here. */
11820 /* If we are clobbering a MEM, mark any hard registers inside the
11821 address as used. */
11822 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11823 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11828 /* A hard reg in a wide mode may really be multiple registers.
11829 If so, mark all of them just like the first. */
11830 if (regno
< FIRST_PSEUDO_REGISTER
)
11832 unsigned int endregno
, r
;
11834 /* None of this applies to the stack, frame or arg pointers */
11835 if (regno
== STACK_POINTER_REGNUM
11836 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11837 || regno
== HARD_FRAME_POINTER_REGNUM
11839 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11840 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11842 || regno
== FRAME_POINTER_REGNUM
)
11845 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11846 for (r
= regno
; r
< endregno
; r
++)
11847 SET_HARD_REG_BIT (newpat_used_regs
, r
);
11853 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11855 register rtx testreg
= SET_DEST (x
);
11857 while (GET_CODE (testreg
) == SUBREG
11858 || GET_CODE (testreg
) == ZERO_EXTRACT
11859 || GET_CODE (testreg
) == SIGN_EXTRACT
11860 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11861 testreg
= XEXP (testreg
, 0);
11863 if (GET_CODE (testreg
) == MEM
)
11864 mark_used_regs_combine (XEXP (testreg
, 0));
11866 mark_used_regs_combine (SET_SRC (x
));
11874 /* Recursively scan the operands of this expression. */
11877 register const char *fmt
= GET_RTX_FORMAT (code
);
11879 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11882 mark_used_regs_combine (XEXP (x
, i
));
11883 else if (fmt
[i
] == 'E')
11887 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11888 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11894 /* Remove register number REGNO from the dead registers list of INSN.
11896 Return the note used to record the death, if there was one. */
11899 remove_death (regno
, insn
)
11900 unsigned int regno
;
11903 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11907 REG_N_DEATHS (regno
)--;
11908 remove_note (insn
, note
);
11914 /* For each register (hardware or pseudo) used within expression X, if its
11915 death is in an instruction with cuid between FROM_CUID (inclusive) and
11916 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11917 list headed by PNOTES.
11919 That said, don't move registers killed by maybe_kill_insn.
11921 This is done when X is being merged by combination into TO_INSN. These
11922 notes will then be distributed as needed. */
11925 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
11927 rtx maybe_kill_insn
;
11932 register const char *fmt
;
11933 register int len
, i
;
11934 register enum rtx_code code
= GET_CODE (x
);
11938 unsigned int regno
= REGNO (x
);
11939 register rtx where_dead
= reg_last_death
[regno
];
11940 register rtx before_dead
, after_dead
;
11942 /* Don't move the register if it gets killed in between from and to */
11943 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11944 && ! reg_referenced_p (x
, maybe_kill_insn
))
11947 /* WHERE_DEAD could be a USE insn made by combine, so first we
11948 make sure that we have insns with valid INSN_CUID values. */
11949 before_dead
= where_dead
;
11950 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11951 before_dead
= PREV_INSN (before_dead
);
11953 after_dead
= where_dead
;
11954 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11955 after_dead
= NEXT_INSN (after_dead
);
11957 if (before_dead
&& after_dead
11958 && INSN_CUID (before_dead
) >= from_cuid
11959 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11960 || (where_dead
!= after_dead
11961 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11963 rtx note
= remove_death (regno
, where_dead
);
11965 /* It is possible for the call above to return 0. This can occur
11966 when reg_last_death points to I2 or I1 that we combined with.
11967 In that case make a new note.
11969 We must also check for the case where X is a hard register
11970 and NOTE is a death note for a range of hard registers
11971 including X. In that case, we must put REG_DEAD notes for
11972 the remaining registers in place of NOTE. */
11974 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11975 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11976 > GET_MODE_SIZE (GET_MODE (x
))))
11978 unsigned int deadregno
= REGNO (XEXP (note
, 0));
11979 unsigned int deadend
11980 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
11981 GET_MODE (XEXP (note
, 0))));
11982 unsigned int ourend
11983 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11986 for (i
= deadregno
; i
< deadend
; i
++)
11987 if (i
< regno
|| i
>= ourend
)
11988 REG_NOTES (where_dead
)
11989 = gen_rtx_EXPR_LIST (REG_DEAD
,
11990 gen_rtx_REG (reg_raw_mode
[i
], i
),
11991 REG_NOTES (where_dead
));
11994 /* If we didn't find any note, or if we found a REG_DEAD note that
11995 covers only part of the given reg, and we have a multi-reg hard
11996 register, then to be safe we must check for REG_DEAD notes
11997 for each register other than the first. They could have
11998 their own REG_DEAD notes lying around. */
11999 else if ((note
== 0
12001 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12002 < GET_MODE_SIZE (GET_MODE (x
)))))
12003 && regno
< FIRST_PSEUDO_REGISTER
12004 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
12006 unsigned int ourend
12007 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12008 unsigned int i
, offset
;
12012 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
12016 for (i
= regno
+ offset
; i
< ourend
; i
++)
12017 move_deaths (gen_rtx_REG (reg_raw_mode
[i
], i
),
12018 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12021 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12023 XEXP (note
, 1) = *pnotes
;
12027 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12029 REG_N_DEATHS (regno
)++;
12035 else if (GET_CODE (x
) == SET
)
12037 rtx dest
= SET_DEST (x
);
12039 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12041 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12042 that accesses one word of a multi-word item, some
12043 piece of everything register in the expression is used by
12044 this insn, so remove any old death. */
12046 if (GET_CODE (dest
) == ZERO_EXTRACT
12047 || GET_CODE (dest
) == STRICT_LOW_PART
12048 || (GET_CODE (dest
) == SUBREG
12049 && (((GET_MODE_SIZE (GET_MODE (dest
))
12050 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12051 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12052 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12054 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12058 /* If this is some other SUBREG, we know it replaces the entire
12059 value, so use that as the destination. */
12060 if (GET_CODE (dest
) == SUBREG
)
12061 dest
= SUBREG_REG (dest
);
12063 /* If this is a MEM, adjust deaths of anything used in the address.
12064 For a REG (the only other possibility), the entire value is
12065 being replaced so the old value is not used in this insn. */
12067 if (GET_CODE (dest
) == MEM
)
12068 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12073 else if (GET_CODE (x
) == CLOBBER
)
12076 len
= GET_RTX_LENGTH (code
);
12077 fmt
= GET_RTX_FORMAT (code
);
12079 for (i
= 0; i
< len
; i
++)
12084 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12085 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12088 else if (fmt
[i
] == 'e')
12089 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12093 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12094 pattern of an insn. X must be a REG. */
12097 reg_bitfield_target_p (x
, body
)
12103 if (GET_CODE (body
) == SET
)
12105 rtx dest
= SET_DEST (body
);
12107 unsigned int regno
, tregno
, endregno
, endtregno
;
12109 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12110 target
= XEXP (dest
, 0);
12111 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12112 target
= SUBREG_REG (XEXP (dest
, 0));
12116 if (GET_CODE (target
) == SUBREG
)
12117 target
= SUBREG_REG (target
);
12119 if (GET_CODE (target
) != REG
)
12122 tregno
= REGNO (target
), regno
= REGNO (x
);
12123 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12124 return target
== x
;
12126 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
12127 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12129 return endregno
> tregno
&& regno
< endtregno
;
12132 else if (GET_CODE (body
) == PARALLEL
)
12133 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12134 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12140 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12141 as appropriate. I3 and I2 are the insns resulting from the combination
12142 insns including FROM (I2 may be zero).
12144 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12145 not need REG_DEAD notes because they are being substituted for. This
12146 saves searching in the most common cases.
12148 Each note in the list is either ignored or placed on some insns, depending
12149 on the type of note. */
12152 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
12156 rtx elim_i2
, elim_i1
;
12158 rtx note
, next_note
;
12161 for (note
= notes
; note
; note
= next_note
)
12163 rtx place
= 0, place2
= 0;
12165 /* If this NOTE references a pseudo register, ensure it references
12166 the latest copy of that register. */
12167 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12168 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12169 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12171 next_note
= XEXP (note
, 1);
12172 switch (REG_NOTE_KIND (note
))
12175 case REG_EXEC_COUNT
:
12176 /* Doesn't matter much where we put this, as long as it's somewhere.
12177 It is preferable to keep these notes on branches, which is most
12178 likely to be i3. */
12182 case REG_NON_LOCAL_GOTO
:
12183 if (GET_CODE (i3
) == JUMP_INSN
)
12185 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12191 case REG_EH_REGION
:
12192 case REG_EH_RETHROW
:
12194 /* These notes must remain with the call. It should not be
12195 possible for both I2 and I3 to be a call. */
12196 if (GET_CODE (i3
) == CALL_INSN
)
12198 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12205 /* Any clobbers for i3 may still exist, and so we must process
12206 REG_UNUSED notes from that insn.
12208 Any clobbers from i2 or i1 can only exist if they were added by
12209 recog_for_combine. In that case, recog_for_combine created the
12210 necessary REG_UNUSED notes. Trying to keep any original
12211 REG_UNUSED notes from these insns can cause incorrect output
12212 if it is for the same register as the original i3 dest.
12213 In that case, we will notice that the register is set in i3,
12214 and then add a REG_UNUSED note for the destination of i3, which
12215 is wrong. However, it is possible to have REG_UNUSED notes from
12216 i2 or i1 for register which were both used and clobbered, so
12217 we keep notes from i2 or i1 if they will turn into REG_DEAD
12220 /* If this register is set or clobbered in I3, put the note there
12221 unless there is one already. */
12222 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12224 if (from_insn
!= i3
)
12227 if (! (GET_CODE (XEXP (note
, 0)) == REG
12228 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12229 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12232 /* Otherwise, if this register is used by I3, then this register
12233 now dies here, so we must put a REG_DEAD note here unless there
12235 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12236 && ! (GET_CODE (XEXP (note
, 0)) == REG
12237 ? find_regno_note (i3
, REG_DEAD
,
12238 REGNO (XEXP (note
, 0)))
12239 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12241 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12249 /* These notes say something about results of an insn. We can
12250 only support them if they used to be on I3 in which case they
12251 remain on I3. Otherwise they are ignored.
12253 If the note refers to an expression that is not a constant, we
12254 must also ignore the note since we cannot tell whether the
12255 equivalence is still true. It might be possible to do
12256 slightly better than this (we only have a problem if I2DEST
12257 or I1DEST is present in the expression), but it doesn't
12258 seem worth the trouble. */
12260 if (from_insn
== i3
12261 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12266 case REG_NO_CONFLICT
:
12267 /* These notes say something about how a register is used. They must
12268 be present on any use of the register in I2 or I3. */
12269 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12272 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12282 /* This can show up in several ways -- either directly in the
12283 pattern, or hidden off in the constant pool with (or without?)
12284 a REG_EQUAL note. */
12285 /* ??? Ignore the without-reg_equal-note problem for now. */
12286 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12287 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12288 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12289 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12293 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12294 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12295 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12296 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12307 /* These notes say something about the value of a register prior
12308 to the execution of an insn. It is too much trouble to see
12309 if the note is still correct in all situations. It is better
12310 to simply delete it. */
12314 /* If the insn previously containing this note still exists,
12315 put it back where it was. Otherwise move it to the previous
12316 insn. Adjust the corresponding REG_LIBCALL note. */
12317 if (GET_CODE (from_insn
) != NOTE
)
12321 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12322 place
= prev_real_insn (from_insn
);
12324 XEXP (tem
, 0) = place
;
12325 /* If we're deleting the last remaining instruction of a
12326 libcall sequence, don't add the notes. */
12327 else if (XEXP (note
, 0) == from_insn
)
12333 /* This is handled similarly to REG_RETVAL. */
12334 if (GET_CODE (from_insn
) != NOTE
)
12338 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12339 place
= next_real_insn (from_insn
);
12341 XEXP (tem
, 0) = place
;
12342 /* If we're deleting the last remaining instruction of a
12343 libcall sequence, don't add the notes. */
12344 else if (XEXP (note
, 0) == from_insn
)
12350 /* If the register is used as an input in I3, it dies there.
12351 Similarly for I2, if it is non-zero and adjacent to I3.
12353 If the register is not used as an input in either I3 or I2
12354 and it is not one of the registers we were supposed to eliminate,
12355 there are two possibilities. We might have a non-adjacent I2
12356 or we might have somehow eliminated an additional register
12357 from a computation. For example, we might have had A & B where
12358 we discover that B will always be zero. In this case we will
12359 eliminate the reference to A.
12361 In both cases, we must search to see if we can find a previous
12362 use of A and put the death note there. */
12365 && GET_CODE (from_insn
) == CALL_INSN
12366 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12368 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12370 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12371 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12374 if (rtx_equal_p (XEXP (note
, 0), elim_i2
)
12375 || rtx_equal_p (XEXP (note
, 0), elim_i1
))
12380 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12382 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12384 if (! INSN_P (tem
))
12386 if (tem
== bb
->head
)
12391 /* If the register is being set at TEM, see if that is all
12392 TEM is doing. If so, delete TEM. Otherwise, make this
12393 into a REG_UNUSED note instead. */
12394 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12396 rtx set
= single_set (tem
);
12397 rtx inner_dest
= 0;
12399 rtx cc0_setter
= NULL_RTX
;
12403 for (inner_dest
= SET_DEST (set
);
12404 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12405 || GET_CODE (inner_dest
) == SUBREG
12406 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12407 inner_dest
= XEXP (inner_dest
, 0))
12410 /* Verify that it was the set, and not a clobber that
12411 modified the register.
12413 CC0 targets must be careful to maintain setter/user
12414 pairs. If we cannot delete the setter due to side
12415 effects, mark the user with an UNUSED note instead
12418 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12419 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12421 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12422 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12423 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12427 /* Move the notes and links of TEM elsewhere.
12428 This might delete other dead insns recursively.
12429 First set the pattern to something that won't use
12432 PATTERN (tem
) = pc_rtx
;
12434 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12435 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12436 distribute_links (LOG_LINKS (tem
));
12438 PUT_CODE (tem
, NOTE
);
12439 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12440 NOTE_SOURCE_FILE (tem
) = 0;
12443 /* Delete the setter too. */
12446 PATTERN (cc0_setter
) = pc_rtx
;
12448 distribute_notes (REG_NOTES (cc0_setter
),
12449 cc0_setter
, cc0_setter
,
12450 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12451 distribute_links (LOG_LINKS (cc0_setter
));
12453 PUT_CODE (cc0_setter
, NOTE
);
12454 NOTE_LINE_NUMBER (cc0_setter
)
12455 = NOTE_INSN_DELETED
;
12456 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12460 /* If the register is both set and used here, put the
12461 REG_DEAD note here, but place a REG_UNUSED note
12462 here too unless there already is one. */
12463 else if (reg_referenced_p (XEXP (note
, 0),
12468 if (! find_regno_note (tem
, REG_UNUSED
,
12469 REGNO (XEXP (note
, 0))))
12471 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12476 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12478 /* If there isn't already a REG_UNUSED note, put one
12480 if (! find_regno_note (tem
, REG_UNUSED
,
12481 REGNO (XEXP (note
, 0))))
12486 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12487 || (GET_CODE (tem
) == CALL_INSN
12488 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12492 /* If we are doing a 3->2 combination, and we have a
12493 register which formerly died in i3 and was not used
12494 by i2, which now no longer dies in i3 and is used in
12495 i2 but does not die in i2, and place is between i2
12496 and i3, then we may need to move a link from place to
12498 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12499 && INSN_CUID (place
) > INSN_CUID (i2
)
12501 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12502 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12504 rtx links
= LOG_LINKS (place
);
12505 LOG_LINKS (place
) = 0;
12506 distribute_links (links
);
12511 if (tem
== bb
->head
)
12515 /* We haven't found an insn for the death note and it
12516 is still a REG_DEAD note, but we have hit the beginning
12517 of the block. If the existing life info says the reg
12518 was dead, there's nothing left to do. Otherwise, we'll
12519 need to do a global life update after combine. */
12520 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12521 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12522 REGNO (XEXP (note
, 0))))
12524 SET_BIT (refresh_blocks
, this_basic_block
);
12529 /* If the register is set or already dead at PLACE, we needn't do
12530 anything with this note if it is still a REG_DEAD note.
12531 We can here if it is set at all, not if is it totally replace,
12532 which is what `dead_or_set_p' checks, so also check for it being
12535 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12537 unsigned int regno
= REGNO (XEXP (note
, 0));
12539 if (dead_or_set_p (place
, XEXP (note
, 0))
12540 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12542 /* Unless the register previously died in PLACE, clear
12543 reg_last_death. [I no longer understand why this is
12545 if (reg_last_death
[regno
] != place
)
12546 reg_last_death
[regno
] = 0;
12550 reg_last_death
[regno
] = place
;
12552 /* If this is a death note for a hard reg that is occupying
12553 multiple registers, ensure that we are still using all
12554 parts of the object. If we find a piece of the object
12555 that is unused, we must arrange for an appropriate REG_DEAD
12556 note to be added for it. However, we can't just emit a USE
12557 and tag the note to it, since the register might actually
12558 be dead; so we recourse, and the recursive call then finds
12559 the previous insn that used this register. */
12561 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12562 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12564 unsigned int endregno
12565 = regno
+ HARD_REGNO_NREGS (regno
,
12566 GET_MODE (XEXP (note
, 0)));
12570 for (i
= regno
; i
< endregno
; i
++)
12571 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12572 && ! find_regno_fusage (place
, USE
, i
))
12573 || dead_or_set_regno_p (place
, i
))
12578 /* Put only REG_DEAD notes for pieces that are
12579 not already dead or set. */
12581 for (i
= regno
; i
< endregno
;
12582 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12584 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
12585 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12587 if (! dead_or_set_p (place
, piece
)
12588 && ! reg_bitfield_target_p (piece
,
12592 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12594 distribute_notes (new_note
, place
, place
,
12595 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12597 else if (! refers_to_regno_p (i
, i
+ 1,
12598 PATTERN (place
), 0)
12599 && ! find_regno_fusage (place
, USE
, i
))
12600 for (tem
= PREV_INSN (place
); ;
12601 tem
= PREV_INSN (tem
))
12603 if (! INSN_P (tem
))
12605 if (tem
== bb
->head
)
12607 SET_BIT (refresh_blocks
,
12614 if (dead_or_set_p (tem
, piece
)
12615 || reg_bitfield_target_p (piece
,
12619 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12634 /* Any other notes should not be present at this point in the
12641 XEXP (note
, 1) = REG_NOTES (place
);
12642 REG_NOTES (place
) = note
;
12644 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12645 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12646 && GET_CODE (XEXP (note
, 0)) == REG
)
12647 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12651 if ((REG_NOTE_KIND (note
) == REG_DEAD
12652 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12653 && GET_CODE (XEXP (note
, 0)) == REG
)
12654 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12656 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12657 REG_NOTE_KIND (note
),
12659 REG_NOTES (place2
));
12664 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12665 I3, I2, and I1 to new locations. This is also called in one case to
12666 add a link pointing at I3 when I3's destination is changed. */
12669 distribute_links (links
)
12672 rtx link
, next_link
;
12674 for (link
= links
; link
; link
= next_link
)
12680 next_link
= XEXP (link
, 1);
12682 /* If the insn that this link points to is a NOTE or isn't a single
12683 set, ignore it. In the latter case, it isn't clear what we
12684 can do other than ignore the link, since we can't tell which
12685 register it was for. Such links wouldn't be used by combine
12688 It is not possible for the destination of the target of the link to
12689 have been changed by combine. The only potential of this is if we
12690 replace I3, I2, and I1 by I3 and I2. But in that case the
12691 destination of I2 also remains unchanged. */
12693 if (GET_CODE (XEXP (link
, 0)) == NOTE
12694 || (set
= single_set (XEXP (link
, 0))) == 0)
12697 reg
= SET_DEST (set
);
12698 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12699 || GET_CODE (reg
) == SIGN_EXTRACT
12700 || GET_CODE (reg
) == STRICT_LOW_PART
)
12701 reg
= XEXP (reg
, 0);
12703 /* A LOG_LINK is defined as being placed on the first insn that uses
12704 a register and points to the insn that sets the register. Start
12705 searching at the next insn after the target of the link and stop
12706 when we reach a set of the register or the end of the basic block.
12708 Note that this correctly handles the link that used to point from
12709 I3 to I2. Also note that not much searching is typically done here
12710 since most links don't point very far away. */
12712 for (insn
= NEXT_INSN (XEXP (link
, 0));
12713 (insn
&& (this_basic_block
== n_basic_blocks
- 1
12714 || BLOCK_HEAD (this_basic_block
+ 1) != insn
));
12715 insn
= NEXT_INSN (insn
))
12716 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12718 if (reg_referenced_p (reg
, PATTERN (insn
)))
12722 else if (GET_CODE (insn
) == CALL_INSN
12723 && find_reg_fusage (insn
, USE
, reg
))
12729 /* If we found a place to put the link, place it there unless there
12730 is already a link to the same insn as LINK at that point. */
12736 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12737 if (XEXP (link2
, 0) == XEXP (link
, 0))
12742 XEXP (link
, 1) = LOG_LINKS (place
);
12743 LOG_LINKS (place
) = link
;
12745 /* Set added_links_insn to the earliest insn we added a
12747 if (added_links_insn
== 0
12748 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12749 added_links_insn
= place
;
12755 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12761 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12762 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12763 insn
= NEXT_INSN (insn
);
12765 if (INSN_UID (insn
) > max_uid_cuid
)
12768 return INSN_CUID (insn
);
12772 dump_combine_stats (file
)
12777 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12778 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12782 dump_combine_total_stats (file
)
12787 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12788 total_attempts
, total_merges
, total_extras
, total_successes
);