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1af1688b RK |
1 | /* This file contains the definitions and documentation for the |
2 | Register Transfer Expressions (rtx's) that make up the | |
3 | Register Transfer Language (rtl) used in the Back End of the GNU compiler. | |
ad616de1 | 4 | Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004, |
2d593c86 | 5 | 2005, 2006, 2007, 2008 |
c5c76735 | 6 | Free Software Foundation, Inc. |
1af1688b | 7 | |
1322177d | 8 | This file is part of GCC. |
1af1688b | 9 | |
1322177d LB |
10 | GCC is free software; you can redistribute it and/or modify it under |
11 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 12 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 13 | version. |
1af1688b | 14 | |
1322177d LB |
15 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
16 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
18 | for more details. | |
1af1688b RK |
19 | |
20 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
21 | along with GCC; see the file COPYING3. If not see |
22 | <http://www.gnu.org/licenses/>. */ | |
1af1688b RK |
23 | |
24 | ||
25 | /* Expression definitions and descriptions for all targets are in this file. | |
26 | Some will not be used for some targets. | |
27 | ||
28 | The fields in the cpp macro call "DEF_RTL_EXPR()" | |
29 | are used to create declarations in the C source of the compiler. | |
30 | ||
31 | The fields are: | |
32 | ||
33 | 1. The internal name of the rtx used in the C source. | |
34 | It is a tag in the enumeration "enum rtx_code" defined in "rtl.h". | |
35 | By convention these are in UPPER_CASE. | |
36 | ||
37 | 2. The name of the rtx in the external ASCII format read by | |
38 | read_rtx(), and printed by print_rtx(). | |
39 | These names are stored in rtx_name[]. | |
40 | By convention these are the internal (field 1) names in lower_case. | |
41 | ||
e1de1560 | 42 | 3. The print format, and type of each rtx->u.fld[] (field) in this rtx. |
1af1688b RK |
43 | These formats are stored in rtx_format[]. |
44 | The meaning of the formats is documented in front of this array in rtl.c | |
45 | ||
46 | 4. The class of the rtx. These are stored in rtx_class and are accessed | |
47 | via the GET_RTX_CLASS macro. They are defined as follows: | |
48 | ||
ec8e098d PB |
49 | RTX_CONST_OBJ |
50 | an rtx code that can be used to represent a constant object | |
51 | (e.g, CONST_INT) | |
52 | RTX_OBJ | |
53 | an rtx code that can be used to represent an object (e.g, REG, MEM) | |
54 | RTX_COMPARE | |
55 | an rtx code for a comparison (e.g, LT, GT) | |
56 | RTX_COMM_COMPARE | |
57 | an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED) | |
58 | RTX_UNARY | |
59 | an rtx code for a unary arithmetic expression (e.g, NEG, NOT) | |
60 | RTX_COMM_ARITH | |
61 | an rtx code for a commutative binary operation (e.g,, PLUS, MULT) | |
62 | RTX_TERNARY | |
63 | an rtx code for a non-bitfield three input operation (IF_THEN_ELSE) | |
64 | RTX_BIN_ARITH | |
65 | an rtx code for a non-commutative binary operation (e.g., MINUS, DIV) | |
66 | RTX_BITFIELD_OPS | |
67 | an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT) | |
68 | RTX_INSN | |
69 | an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) | |
70 | RTX_MATCH | |
71 | an rtx code for something that matches in insns (e.g, MATCH_DUP) | |
72 | RTX_AUTOINC | |
73 | an rtx code for autoincrement addressing modes (e.g. POST_DEC) | |
74 | RTX_EXTRA | |
75 | everything else | |
1af1688b | 76 | |
b5c2f1d1 ZW |
77 | All of the expressions that appear only in machine descriptions, |
78 | not in RTL used by the compiler itself, are at the end of the file. */ | |
1af1688b | 79 | |
b5c2f1d1 ZW |
80 | /* Unknown, or no such operation; the enumeration constant should have |
81 | value zero. */ | |
ec8e098d | 82 | DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA) |
1af1688b | 83 | |
1af1688b RK |
84 | /* --------------------------------------------------------------------- |
85 | Expressions used in constructing lists. | |
86 | --------------------------------------------------------------------- */ | |
87 | ||
88 | /* a linked list of expressions */ | |
ec8e098d | 89 | DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA) |
1af1688b RK |
90 | |
91 | /* a linked list of instructions. | |
92 | The insns are represented in print by their uids. */ | |
ec8e098d | 93 | DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA) |
1af1688b | 94 | |
b5c2f1d1 ZW |
95 | /* SEQUENCE appears in the result of a `gen_...' function |
96 | for a DEFINE_EXPAND that wants to make several insns. | |
97 | Its elements are the bodies of the insns that should be made. | |
98 | `emit_insn' takes the SEQUENCE apart and makes separate insns. */ | |
99 | DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA) | |
1af1688b | 100 | |
b5c2f1d1 ZW |
101 | /* Refers to the address of its argument. This is only used in alias.c. */ |
102 | DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH) | |
1af1688b | 103 | |
b5c2f1d1 ZW |
104 | /* ---------------------------------------------------------------------- |
105 | Expression types used for things in the instruction chain. | |
1af1688b | 106 | |
b5c2f1d1 ZW |
107 | All formats must start with "iuu" to handle the chain. |
108 | Each insn expression holds an rtl instruction and its semantics | |
109 | during back-end processing. | |
110 | See macros's in "rtl.h" for the meaning of each rtx->u.fld[]. | |
1af1688b | 111 | |
b5c2f1d1 | 112 | ---------------------------------------------------------------------- */ |
1af1688b | 113 | |
b5c2f1d1 | 114 | /* An instruction that cannot jump. */ |
6fb5fa3c | 115 | DEF_RTL_EXPR(INSN, "insn", "iuuBieie", RTX_INSN) |
1af1688b | 116 | |
b5c2f1d1 ZW |
117 | /* An instruction that can possibly jump. |
118 | Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ | |
6fb5fa3c | 119 | DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieie0", RTX_INSN) |
1af1688b | 120 | |
b5c2f1d1 ZW |
121 | /* An instruction that can possibly call a subroutine |
122 | but which will not change which instruction comes next | |
123 | in the current function. | |
6fb5fa3c | 124 | Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE. |
b5c2f1d1 | 125 | All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ |
6fb5fa3c | 126 | DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieiee", RTX_INSN) |
1af1688b | 127 | |
b5c2f1d1 | 128 | /* A marker that indicates that control will not flow through. */ |
6fb5fa3c | 129 | DEF_RTL_EXPR(BARRIER, "barrier", "iuu00000", RTX_EXTRA) |
1af1688b | 130 | |
b5c2f1d1 ZW |
131 | /* Holds a label that is followed by instructions. |
132 | Operand: | |
133 | 4: is used in jump.c for the use-count of the label. | |
6fb5fa3c | 134 | 5: is used in the sh backend. |
b5c2f1d1 ZW |
135 | 6: is a number that is unique in the entire compilation. |
136 | 7: is the user-given name of the label, if any. */ | |
137 | DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA) | |
1af1688b | 138 | |
b5c2f1d1 ZW |
139 | /* Say where in the code a source line starts, for symbol table's sake. |
140 | Operand: | |
a38e7aa5 | 141 | 4: note-specific data |
28cc8a50 UB |
142 | 5: enum insn_note |
143 | 6: unique number if insn_note == note_insn_deleted_label. */ | |
144 | DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA) | |
1af1688b | 145 | |
b5c2f1d1 ZW |
146 | /* ---------------------------------------------------------------------- |
147 | Top level constituents of INSN, JUMP_INSN and CALL_INSN. | |
148 | ---------------------------------------------------------------------- */ | |
149 | ||
150 | /* Conditionally execute code. | |
151 | Operand 0 is the condition that if true, the code is executed. | |
152 | Operand 1 is the code to be executed (typically a SET). | |
1af1688b | 153 | |
b5c2f1d1 ZW |
154 | Semantics are that there are no side effects if the condition |
155 | is false. This pattern is created automatically by the if_convert | |
156 | pass run after reload or by target-specific splitters. */ | |
157 | DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA) | |
1af1688b | 158 | |
b5c2f1d1 ZW |
159 | /* Several operations to be done in parallel (perhaps under COND_EXEC). */ |
160 | DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA) | |
ae3c61fa | 161 | |
b5c2f1d1 ZW |
162 | /* A string that is passed through to the assembler as input. |
163 | One can obviously pass comments through by using the | |
164 | assembler comment syntax. | |
165 | These occur in an insn all by themselves as the PATTERN. | |
166 | They also appear inside an ASM_OPERANDS | |
167 | as a convenient way to hold a string. */ | |
bff4b63d | 168 | DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA) |
e543e219 | 169 | |
b5c2f1d1 ZW |
170 | /* An assembler instruction with operands. |
171 | 1st operand is the instruction template. | |
172 | 2nd operand is the constraint for the output. | |
173 | 3rd operand is the number of the output this expression refers to. | |
174 | When an insn stores more than one value, a separate ASM_OPERANDS | |
175 | is made for each output; this integer distinguishes them. | |
176 | 4th is a vector of values of input operands. | |
177 | 5th is a vector of modes and constraints for the input operands. | |
178 | Each element is an ASM_INPUT containing a constraint string | |
179 | and whose mode indicates the mode of the input operand. | |
180 | 6th is the source line number. */ | |
181 | DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA) | |
e543e219 | 182 | |
b5c2f1d1 ZW |
183 | /* A machine-specific operation. |
184 | 1st operand is a vector of operands being used by the operation so that | |
185 | any needed reloads can be done. | |
186 | 2nd operand is a unique value saying which of a number of machine-specific | |
187 | operations is to be performed. | |
188 | (Note that the vector must be the first operand because of the way that | |
189 | genrecog.c record positions within an insn.) | |
e3ceb300 SP |
190 | |
191 | UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL, | |
192 | or inside an expression. | |
193 | UNSPEC by itself or as a component of a PARALLEL | |
194 | is currently considered not deletable. | |
195 | ||
196 | FIXME: Replace all uses of UNSPEC that appears by itself or as a component | |
197 | of a PARALLEL with USE. | |
198 | */ | |
b5c2f1d1 | 199 | DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA) |
1af1688b | 200 | |
b5c2f1d1 ZW |
201 | /* Similar, but a volatile operation and one which may trap. */ |
202 | DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA) | |
1af1688b | 203 | |
b5c2f1d1 ZW |
204 | /* Vector of addresses, stored as full words. */ |
205 | /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */ | |
206 | DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA) | |
1af1688b | 207 | |
b5c2f1d1 ZW |
208 | /* Vector of address differences X0 - BASE, X1 - BASE, ... |
209 | First operand is BASE; the vector contains the X's. | |
210 | The machine mode of this rtx says how much space to leave | |
211 | for each difference and is adjusted by branch shortening if | |
212 | CASE_VECTOR_SHORTEN_MODE is defined. | |
213 | The third and fourth operands store the target labels with the | |
214 | minimum and maximum addresses respectively. | |
215 | The fifth operand stores flags for use by branch shortening. | |
216 | Set at the start of shorten_branches: | |
217 | min_align: the minimum alignment for any of the target labels. | |
218 | base_after_vec: true iff BASE is after the ADDR_DIFF_VEC. | |
219 | min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC. | |
220 | max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC. | |
221 | min_after_base: true iff minimum address target label is after BASE. | |
222 | max_after_base: true iff maximum address target label is after BASE. | |
223 | Set by the actual branch shortening process: | |
224 | offset_unsigned: true iff offsets have to be treated as unsigned. | |
225 | scale: scaling that is necessary to make offsets fit into the mode. | |
c88c0d42 | 226 | |
b5c2f1d1 ZW |
227 | The third, fourth and fifth operands are only valid when |
228 | CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing | |
229 | compilations. */ | |
230 | ||
231 | DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA) | |
ede7cd44 | 232 | |
b5c2f1d1 ZW |
233 | /* Memory prefetch, with attributes supported on some targets. |
234 | Operand 1 is the address of the memory to fetch. | |
235 | Operand 2 is 1 for a write access, 0 otherwise. | |
236 | Operand 3 is the level of temporal locality; 0 means there is no | |
237 | temporal locality and 1, 2, and 3 are for increasing levels of temporal | |
238 | locality. | |
1af1688b | 239 | |
b5c2f1d1 ZW |
240 | The attributes specified by operands 2 and 3 are ignored for targets |
241 | whose prefetch instructions do not support them. */ | |
242 | DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA) | |
1af1688b | 243 | |
b5c2f1d1 ZW |
244 | /* ---------------------------------------------------------------------- |
245 | At the top level of an instruction (perhaps under PARALLEL). | |
246 | ---------------------------------------------------------------------- */ | |
1af1688b | 247 | |
b5c2f1d1 ZW |
248 | /* Assignment. |
249 | Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to. | |
250 | Operand 2 is the value stored there. | |
251 | ALL assignment must use SET. | |
252 | Instructions that do multiple assignments must use multiple SET, | |
253 | under PARALLEL. */ | |
254 | DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA) | |
3262c1f5 | 255 | |
b5c2f1d1 ZW |
256 | /* Indicate something is used in a way that we don't want to explain. |
257 | For example, subroutine calls will use the register | |
e3ceb300 SP |
258 | in which the static chain is passed. |
259 | ||
260 | USE can not appear as an operand of other rtx except for PARALLEL. | |
261 | USE is not deletable, as it indicates that the operand | |
262 | is used in some unknown way. */ | |
b5c2f1d1 | 263 | DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA) |
3262c1f5 | 264 | |
b5c2f1d1 ZW |
265 | /* Indicate something is clobbered in a way that we don't want to explain. |
266 | For example, subroutine calls will clobber some physical registers | |
e3ceb300 SP |
267 | (the ones that are by convention not saved). |
268 | ||
269 | CLOBBER can not appear as an operand of other rtx except for PARALLEL. | |
270 | CLOBBER of a hard register appearing by itself (not within PARALLEL) | |
271 | is considered undeletable before reload. */ | |
b5c2f1d1 | 272 | DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA) |
e543e219 | 273 | |
b5c2f1d1 ZW |
274 | /* Call a subroutine. |
275 | Operand 1 is the address to call. | |
276 | Operand 2 is the number of arguments. */ | |
e543e219 | 277 | |
b5c2f1d1 | 278 | DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA) |
1af1688b | 279 | |
b5c2f1d1 ZW |
280 | /* Return from a subroutine. */ |
281 | ||
282 | DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA) | |
283 | ||
cd9c1ca8 RH |
284 | /* Special for EH return from subroutine. */ |
285 | ||
286 | DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA) | |
287 | ||
b5c2f1d1 ZW |
288 | /* Conditional trap. |
289 | Operand 1 is the condition. | |
290 | Operand 2 is the trap code. | |
291 | For an unconditional trap, make the condition (const_int 1). */ | |
292 | DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA) | |
293 | ||
294 | /* Placeholder for _Unwind_Resume before we know if a function call | |
295 | or a branch is needed. Operand 1 is the exception region from | |
296 | which control is flowing. */ | |
297 | DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA) | |
1af1688b | 298 | |
fae15c93 | 299 | /* ---------------------------------------------------------------------- |
b5c2f1d1 | 300 | Primitive values for use in expressions. |
fae15c93 VM |
301 | ---------------------------------------------------------------------- */ |
302 | ||
b5c2f1d1 ZW |
303 | /* numeric integer constant */ |
304 | DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ) | |
fae15c93 | 305 | |
091a3ac7 CF |
306 | /* fixed-point constant */ |
307 | DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ) | |
308 | ||
b5c2f1d1 ZW |
309 | /* numeric floating point constant. |
310 | Operands hold the value. They are all 'w' and there may be from 2 to 6; | |
311 | see real.h. */ | |
312 | DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ) | |
fae15c93 | 313 | |
b5c2f1d1 | 314 | /* Describes a vector constant. */ |
f4770271 | 315 | DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ) |
fae15c93 | 316 | |
b5c2f1d1 ZW |
317 | /* String constant. Used for attributes in machine descriptions and |
318 | for special cases in DWARF2 debug output. NOT used for source- | |
319 | language string constants. */ | |
320 | DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ) | |
fae15c93 | 321 | |
b5c2f1d1 ZW |
322 | /* This is used to encapsulate an expression whose value is constant |
323 | (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be | |
324 | recognized as a constant operand rather than by arithmetic instructions. */ | |
fae15c93 | 325 | |
b5c2f1d1 | 326 | DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ) |
30028c85 | 327 | |
b5c2f1d1 ZW |
328 | /* program counter. Ordinary jumps are represented |
329 | by a SET whose first operand is (PC). */ | |
330 | DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ) | |
30028c85 | 331 | |
d67fb775 SB |
332 | /* Used in the cselib routines to describe a value. Objects of this |
333 | kind are only allocated in cselib.c, in an alloc pool instead of | |
334 | in GC memory. The only operand of a VALUE is a cselib_val_struct. */ | |
b5c2f1d1 | 335 | DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ) |
30028c85 | 336 | |
b5c2f1d1 ZW |
337 | /* A register. The "operand" is the register number, accessed with |
338 | the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER | |
339 | than a hardware register is being referred to. The second operand | |
340 | holds the original register number - this will be different for a | |
18b3a02a GK |
341 | pseudo register that got turned into a hard register. The third |
342 | operand points to a reg_attrs structure. | |
b5c2f1d1 ZW |
343 | This rtx needs to have as many (or more) fields as a MEM, since we |
344 | can change REG rtx's into MEMs during reload. */ | |
345 | DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ) | |
30028c85 | 346 | |
b5c2f1d1 ZW |
347 | /* A scratch register. This represents a register used only within a |
348 | single insn. It will be turned into a REG during register allocation | |
349 | or reload unless the constraint indicates that the register won't be | |
350 | needed, in which case it can remain a SCRATCH. This code is | |
351 | marked as having one operand so it can be turned into a REG. */ | |
352 | DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ) | |
fae15c93 | 353 | |
38ae7651 RS |
354 | /* A reference to a part of another value. The first operand is the |
355 | complete value and the second is the byte offset of the selected part. */ | |
b5c2f1d1 | 356 | DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA) |
30028c85 | 357 | |
b5c2f1d1 ZW |
358 | /* This one-argument rtx is used for move instructions |
359 | that are guaranteed to alter only the low part of a destination. | |
360 | Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...)) | |
361 | has an unspecified effect on the high part of REG, | |
362 | but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...)) | |
363 | is guaranteed to alter only the bits of REG that are in HImode. | |
30028c85 | 364 | |
b5c2f1d1 ZW |
365 | The actual instruction used is probably the same in both cases, |
366 | but the register constraints may be tighter when STRICT_LOW_PART | |
367 | is in use. */ | |
30028c85 | 368 | |
b5c2f1d1 | 369 | DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA) |
30028c85 | 370 | |
b5c2f1d1 ZW |
371 | /* (CONCAT a b) represents the virtual concatenation of a and b |
372 | to make a value that has as many bits as a and b put together. | |
373 | This is used for complex values. Normally it appears only | |
374 | in DECL_RTLs and during RTL generation, but not in the insn chain. */ | |
375 | DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ) | |
30028c85 | 376 | |
e53a16e7 ILT |
377 | /* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of |
378 | all An to make a value. This is an extension of CONCAT to larger | |
379 | number of components. Like CONCAT, it should not appear in the | |
380 | insn chain. Every element of the CONCATN is the same size. */ | |
381 | DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ) | |
382 | ||
b5c2f1d1 ZW |
383 | /* A memory location; operand is the address. The second operand is the |
384 | alias set to which this MEM belongs. We use `0' instead of `w' for this | |
385 | field so that the field need not be specified in machine descriptions. */ | |
386 | DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ) | |
30028c85 | 387 | |
b5c2f1d1 | 388 | /* Reference to an assembler label in the code for this function. |
fc6c490e SB |
389 | The operand is a CODE_LABEL found in the insn chain. */ |
390 | DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ) | |
30028c85 | 391 | |
b5c2f1d1 ZW |
392 | /* Reference to a named label: |
393 | Operand 0: label name | |
394 | Operand 1: flags (see SYMBOL_FLAG_* in rtl.h) | |
395 | Operand 2: tree from which this symbol is derived, or null. | |
396 | This is either a DECL node, or some kind of constant. */ | |
397 | DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ) | |
30028c85 | 398 | |
b5c2f1d1 ZW |
399 | /* The condition code register is represented, in our imagination, |
400 | as a register holding a value that can be compared to zero. | |
401 | In fact, the machine has already compared them and recorded the | |
402 | results; but instructions that look at the condition code | |
403 | pretend to be looking at the entire value and comparing it. */ | |
404 | DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ) | |
30028c85 | 405 | |
b5c2f1d1 ZW |
406 | /* ---------------------------------------------------------------------- |
407 | Expressions for operators in an rtl pattern | |
408 | ---------------------------------------------------------------------- */ | |
fae15c93 | 409 | |
b5c2f1d1 ZW |
410 | /* if_then_else. This is used in representing ordinary |
411 | conditional jump instructions. | |
412 | Operand: | |
413 | 0: condition | |
414 | 1: then expr | |
415 | 2: else expr */ | |
416 | DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY) | |
fae15c93 | 417 | |
b5c2f1d1 ZW |
418 | /* Comparison, produces a condition code result. */ |
419 | DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH) | |
fae15c93 | 420 | |
b5c2f1d1 ZW |
421 | /* plus */ |
422 | DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH) | |
fae15c93 | 423 | |
b5c2f1d1 ZW |
424 | /* Operand 0 minus operand 1. */ |
425 | DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH) | |
e3c8eb86 | 426 | |
b5c2f1d1 ZW |
427 | /* Minus operand 0. */ |
428 | DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY) | |
fae15c93 | 429 | |
b5c2f1d1 | 430 | DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH) |
dfa849f3 | 431 | |
091a3ac7 CF |
432 | /* Multiplication with signed saturation */ |
433 | DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH) | |
434 | /* Multiplication with unsigned saturation */ | |
435 | DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH) | |
436 | ||
b5c2f1d1 ZW |
437 | /* Operand 0 divided by operand 1. */ |
438 | DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH) | |
091a3ac7 CF |
439 | /* Division with signed saturation */ |
440 | DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH) | |
441 | /* Division with unsigned saturation */ | |
442 | DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH) | |
443 | ||
b5c2f1d1 ZW |
444 | /* Remainder of operand 0 divided by operand 1. */ |
445 | DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH) | |
fae15c93 | 446 | |
b5c2f1d1 ZW |
447 | /* Unsigned divide and remainder. */ |
448 | DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH) | |
449 | DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH) | |
fae15c93 | 450 | |
b5c2f1d1 ZW |
451 | /* Bitwise operations. */ |
452 | DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH) | |
b5c2f1d1 | 453 | DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH) |
b5c2f1d1 | 454 | DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH) |
b5c2f1d1 | 455 | DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY) |
fae15c93 | 456 | |
b5c2f1d1 ZW |
457 | /* Operand: |
458 | 0: value to be shifted. | |
459 | 1: number of bits. */ | |
460 | DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */ | |
461 | DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */ | |
462 | DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */ | |
463 | DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */ | |
464 | DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */ | |
fae15c93 | 465 | |
b5c2f1d1 ZW |
466 | /* Minimum and maximum values of two operands. We need both signed and |
467 | unsigned forms. (We cannot use MIN for SMIN because it conflicts | |
7ae4d8d4 RH |
468 | with a macro of the same name.) The signed variants should be used |
469 | with floating point. Further, if both operands are zeros, or if either | |
470 | operand is NaN, then it is unspecified which of the two operands is | |
471 | returned as the result. */ | |
fae15c93 | 472 | |
b5c2f1d1 ZW |
473 | DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH) |
474 | DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH) | |
475 | DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH) | |
476 | DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH) | |
fae15c93 | 477 | |
b5c2f1d1 ZW |
478 | /* These unary operations are used to represent incrementation |
479 | and decrementation as they occur in memory addresses. | |
480 | The amount of increment or decrement are not represented | |
481 | because they can be understood from the machine-mode of the | |
482 | containing MEM. These operations exist in only two cases: | |
483 | 1. pushes onto the stack. | |
484 | 2. created automatically by the life_analysis pass in flow.c. */ | |
485 | DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC) | |
486 | DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC) | |
487 | DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC) | |
488 | DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC) | |
fae15c93 | 489 | |
b5c2f1d1 ZW |
490 | /* These binary operations are used to represent generic address |
491 | side-effects in memory addresses, except for simple incrementation | |
492 | or decrementation which use the above operations. They are | |
493 | created automatically by the life_analysis pass in flow.c. | |
494 | The first operand is a REG which is used as the address. | |
495 | The second operand is an expression that is assigned to the | |
496 | register, either before (PRE_MODIFY) or after (POST_MODIFY) | |
497 | evaluating the address. | |
498 | Currently, the compiler can only handle second operands of the | |
499 | form (plus (reg) (reg)) and (plus (reg) (const_int)), where | |
500 | the first operand of the PLUS has to be the same register as | |
501 | the first operand of the *_MODIFY. */ | |
502 | DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC) | |
503 | DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC) | |
fae15c93 | 504 | |
b5c2f1d1 ZW |
505 | /* Comparison operations. The ordered comparisons exist in two |
506 | flavors, signed and unsigned. */ | |
507 | DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE) | |
508 | DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE) | |
509 | DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE) | |
510 | DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE) | |
511 | DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE) | |
512 | DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE) | |
513 | DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE) | |
514 | DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE) | |
515 | DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE) | |
516 | DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE) | |
fae15c93 | 517 | |
b5c2f1d1 ZW |
518 | /* Additional floating point unordered comparison flavors. */ |
519 | DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE) | |
520 | DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE) | |
fae15c93 | 521 | |
b5c2f1d1 ZW |
522 | /* These are equivalent to unordered or ... */ |
523 | DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE) | |
524 | DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE) | |
525 | DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE) | |
526 | DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE) | |
527 | DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE) | |
fae15c93 | 528 | |
b5c2f1d1 ZW |
529 | /* This is an ordered NE, ie !UNEQ, ie false for NaN. */ |
530 | DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE) | |
fae15c93 | 531 | |
b5c2f1d1 ZW |
532 | /* Represents the result of sign-extending the sole operand. |
533 | The machine modes of the operand and of the SIGN_EXTEND expression | |
534 | determine how much sign-extension is going on. */ | |
535 | DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY) | |
1af1688b | 536 | |
b5c2f1d1 ZW |
537 | /* Similar for zero-extension (such as unsigned short to int). */ |
538 | DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY) | |
1af1688b | 539 | |
b5c2f1d1 ZW |
540 | /* Similar but here the operand has a wider mode. */ |
541 | DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY) | |
1af1688b | 542 | |
b5c2f1d1 ZW |
543 | /* Similar for extending floating-point values (such as SFmode to DFmode). */ |
544 | DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY) | |
545 | DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY) | |
1af1688b | 546 | |
b5c2f1d1 ZW |
547 | /* Conversion of fixed point operand to floating point value. */ |
548 | DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY) | |
1af1688b | 549 | |
b5c2f1d1 ZW |
550 | /* With fixed-point machine mode: |
551 | Conversion of floating point operand to fixed point value. | |
552 | Value is defined only when the operand's value is an integer. | |
553 | With floating-point machine mode (and operand with same mode): | |
554 | Operand is rounded toward zero to produce an integer value | |
555 | represented in floating point. */ | |
556 | DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY) | |
1af1688b | 557 | |
b5c2f1d1 ZW |
558 | /* Conversion of unsigned fixed point operand to floating point value. */ |
559 | DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY) | |
1af1688b | 560 | |
b5c2f1d1 ZW |
561 | /* With fixed-point machine mode: |
562 | Conversion of floating point operand to *unsigned* fixed point value. | |
563 | Value is defined only when the operand's value is an integer. */ | |
564 | DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY) | |
1af1688b | 565 | |
091a3ac7 CF |
566 | /* Conversions involving fractional fixed-point types without saturation, |
567 | including: | |
568 | fractional to fractional (of different precision), | |
569 | signed integer to fractional, | |
570 | fractional to signed integer, | |
571 | floating point to fractional, | |
572 | fractional to floating point. | |
573 | NOTE: fractional can be either signed or unsigned for conversions. */ | |
574 | DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY) | |
575 | ||
576 | /* Conversions involving fractional fixed-point types and unsigned integer | |
577 | without saturation, including: | |
578 | unsigned integer to fractional, | |
579 | fractional to unsigned integer. | |
580 | NOTE: fractional can be either signed or unsigned for conversions. */ | |
581 | DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY) | |
582 | ||
583 | /* Conversions involving fractional fixed-point types with saturation, | |
584 | including: | |
585 | fractional to fractional (of different precision), | |
586 | signed integer to fractional, | |
587 | floating point to fractional. | |
588 | NOTE: fractional can be either signed or unsigned for conversions. */ | |
589 | DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY) | |
590 | ||
591 | /* Conversions involving fractional fixed-point types and unsigned integer | |
592 | with saturation, including: | |
593 | unsigned integer to fractional. | |
594 | NOTE: fractional can be either signed or unsigned for conversions. */ | |
595 | DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY) | |
596 | ||
b5c2f1d1 ZW |
597 | /* Absolute value */ |
598 | DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY) | |
1af1688b | 599 | |
b5c2f1d1 ZW |
600 | /* Square root */ |
601 | DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY) | |
8653a1ed | 602 | |
167fa32c EC |
603 | /* Swap bytes. */ |
604 | DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY) | |
605 | ||
b5c2f1d1 ZW |
606 | /* Find first bit that is set. |
607 | Value is 1 + number of trailing zeros in the arg., | |
608 | or 0 if arg is 0. */ | |
609 | DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY) | |
417a6986 | 610 | |
b5c2f1d1 ZW |
611 | /* Count leading zeros. */ |
612 | DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY) | |
417a6986 | 613 | |
b5c2f1d1 ZW |
614 | /* Count trailing zeros. */ |
615 | DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY) | |
417a6986 | 616 | |
b5c2f1d1 ZW |
617 | /* Population count (number of 1 bits). */ |
618 | DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY) | |
417a6986 | 619 | |
b5c2f1d1 ZW |
620 | /* Population parity (number of 1 bits modulo 2). */ |
621 | DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY) | |
1af1688b | 622 | |
b5c2f1d1 ZW |
623 | /* Reference to a signed bit-field of specified size and position. |
624 | Operand 0 is the memory unit (usually SImode or QImode) which | |
625 | contains the field's first bit. Operand 1 is the width, in bits. | |
626 | Operand 2 is the number of bits in the memory unit before the | |
627 | first bit of this field. | |
628 | If BITS_BIG_ENDIAN is defined, the first bit is the msb and | |
629 | operand 2 counts from the msb of the memory unit. | |
630 | Otherwise, the first bit is the lsb and operand 2 counts from | |
46d096a3 SB |
631 | the lsb of the memory unit. |
632 | This kind of expression can not appear as an lvalue in RTL. */ | |
b5c2f1d1 | 633 | DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS) |
1af1688b | 634 | |
46d096a3 SB |
635 | /* Similar for unsigned bit-field. |
636 | But note! This kind of expression _can_ appear as an lvalue. */ | |
b5c2f1d1 | 637 | DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS) |
1af1688b | 638 | |
b5c2f1d1 | 639 | /* For RISC machines. These save memory when splitting insns. */ |
1af1688b | 640 | |
b5c2f1d1 ZW |
641 | /* HIGH are the high-order bits of a constant expression. */ |
642 | DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ) | |
1af1688b | 643 | |
b5c2f1d1 ZW |
644 | /* LO_SUM is the sum of a register and the low-order bits |
645 | of a constant expression. */ | |
646 | DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ) | |
1af1688b | 647 | |
b5c2f1d1 ZW |
648 | /* Describes a merge operation between two vector values. |
649 | Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask | |
650 | that specifies where the parts of the result are taken from. Set bits | |
651 | indicate operand 0, clear bits indicate operand 1. The parts are defined | |
652 | by the mode of the vectors. */ | |
653 | DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY) | |
6b29b0e2 | 654 | |
b5c2f1d1 ZW |
655 | /* Describes an operation that selects parts of a vector. |
656 | Operands 0 is the source vector, operand 1 is a PARALLEL that contains | |
657 | a CONST_INT for each of the subparts of the result vector, giving the | |
658 | number of the source subpart that should be stored into it. */ | |
659 | DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH) | |
1af1688b | 660 | |
b5c2f1d1 ZW |
661 | /* Describes a vector concat operation. Operands 0 and 1 are the source |
662 | vectors, the result is a vector that is as long as operands 0 and 1 | |
663 | combined and is the concatenation of the two source vectors. */ | |
664 | DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH) | |
1af1688b | 665 | |
b5c2f1d1 ZW |
666 | /* Describes an operation that converts a small vector into a larger one by |
667 | duplicating the input values. The output vector mode must have the same | |
668 | submodes as the input vector mode, and the number of output parts must be | |
669 | an integer multiple of the number of input parts. */ | |
670 | DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY) | |
671 | ||
672 | /* Addition with signed saturation */ | |
673 | DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH) | |
1af1688b | 674 | |
b5c2f1d1 ZW |
675 | /* Addition with unsigned saturation */ |
676 | DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH) | |
1fcea2b0 | 677 | |
b5c2f1d1 ZW |
678 | /* Operand 0 minus operand 1, with signed saturation. */ |
679 | DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH) | |
1fcea2b0 | 680 | |
e551ad26 BS |
681 | /* Negation with signed saturation. */ |
682 | DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY) | |
091a3ac7 CF |
683 | /* Negation with unsigned saturation. */ |
684 | DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY) | |
e551ad26 | 685 | |
26c5953d BS |
686 | /* Absolute value with signed saturation. */ |
687 | DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY) | |
688 | ||
e551ad26 BS |
689 | /* Shift left with signed saturation. */ |
690 | DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH) | |
691 | ||
091a3ac7 CF |
692 | /* Shift left with unsigned saturation. */ |
693 | DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH) | |
694 | ||
b5c2f1d1 ZW |
695 | /* Operand 0 minus operand 1, with unsigned saturation. */ |
696 | DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH) | |
1af1688b | 697 | |
b5c2f1d1 ZW |
698 | /* Signed saturating truncate. */ |
699 | DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY) | |
33f7f353 | 700 | |
b5c2f1d1 ZW |
701 | /* Unsigned saturating truncate. */ |
702 | DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY) | |
1af1688b | 703 | |
b5c2f1d1 | 704 | /* Information about the variable and its location. */ |
62760ffd CT |
705 | /* Changed 'te' to 'tei'; the 'i' field is for recording |
706 | initialization status of variables. */ | |
707 | DEF_RTL_EXPR(VAR_LOCATION, "var_location", "tei", RTX_EXTRA) | |
21b8482a | 708 | |
b5c2f1d1 ZW |
709 | /* All expressions from this point forward appear only in machine |
710 | descriptions. */ | |
9e995780 | 711 | #ifdef GENERATOR_FILE |
21b8482a | 712 | |
b5c2f1d1 ZW |
713 | /* Include a secondary machine-description file at this point. */ |
714 | DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA) | |
1af1688b | 715 | |
b5c2f1d1 | 716 | /* Pattern-matching operators: */ |
1af1688b | 717 | |
b5c2f1d1 ZW |
718 | /* Use the function named by the second arg (the string) |
719 | as a predicate; if matched, store the structure that was matched | |
720 | in the operand table at index specified by the first arg (the integer). | |
721 | If the second arg is the null string, the structure is just stored. | |
1af1688b | 722 | |
b5c2f1d1 ZW |
723 | A third string argument indicates to the register allocator restrictions |
724 | on where the operand can be allocated. | |
1af1688b | 725 | |
b5c2f1d1 ZW |
726 | If the target needs no restriction on any instruction this field should |
727 | be the null string. | |
1af1688b | 728 | |
b5c2f1d1 ZW |
729 | The string is prepended by: |
730 | '=' to indicate the operand is only written to. | |
731 | '+' to indicate the operand is both read and written to. | |
1af1688b | 732 | |
b5c2f1d1 ZW |
733 | Each character in the string represents an allocable class for an operand. |
734 | 'g' indicates the operand can be any valid class. | |
735 | 'i' indicates the operand can be immediate (in the instruction) data. | |
736 | 'r' indicates the operand can be in a register. | |
737 | 'm' indicates the operand can be in memory. | |
738 | 'o' a subset of the 'm' class. Those memory addressing modes that | |
739 | can be offset at compile time (have a constant added to them). | |
1af1688b | 740 | |
b5c2f1d1 ZW |
741 | Other characters indicate target dependent operand classes and |
742 | are described in each target's machine description. | |
1af1688b | 743 | |
b5c2f1d1 ZW |
744 | For instructions with more than one operand, sets of classes can be |
745 | separated by a comma to indicate the appropriate multi-operand constraints. | |
746 | There must be a 1 to 1 correspondence between these sets of classes in | |
747 | all operands for an instruction. | |
748 | */ | |
749 | DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH) | |
1af1688b | 750 | |
b5c2f1d1 ZW |
751 | /* Match a SCRATCH or a register. When used to generate rtl, a |
752 | SCRATCH is generated. As for MATCH_OPERAND, the mode specifies | |
753 | the desired mode and the first argument is the operand number. | |
754 | The second argument is the constraint. */ | |
755 | DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH) | |
52a11cbf | 756 | |
b5c2f1d1 ZW |
757 | /* Apply a predicate, AND match recursively the operands of the rtx. |
758 | Operand 0 is the operand-number, as in match_operand. | |
759 | Operand 1 is a predicate to apply (as a string, a function name). | |
760 | Operand 2 is a vector of expressions, each of which must match | |
761 | one subexpression of the rtx this construct is matching. */ | |
762 | DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH) | |
1af1688b | 763 | |
b5c2f1d1 ZW |
764 | /* Match a PARALLEL of arbitrary length. The predicate is applied |
765 | to the PARALLEL and the initial expressions in the PARALLEL are matched. | |
766 | Operand 0 is the operand-number, as in match_operand. | |
767 | Operand 1 is a predicate to apply to the PARALLEL. | |
768 | Operand 2 is a vector of expressions, each of which must match the | |
769 | corresponding element in the PARALLEL. */ | |
770 | DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH) | |
1af1688b | 771 | |
b5c2f1d1 ZW |
772 | /* Match only something equal to what is stored in the operand table |
773 | at the index specified by the argument. Use with MATCH_OPERAND. */ | |
774 | DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH) | |
1af1688b | 775 | |
b5c2f1d1 ZW |
776 | /* Match only something equal to what is stored in the operand table |
777 | at the index specified by the argument. Use with MATCH_OPERATOR. */ | |
778 | DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH) | |
69ef87e2 | 779 | |
b5c2f1d1 ZW |
780 | /* Match only something equal to what is stored in the operand table |
781 | at the index specified by the argument. Use with MATCH_PARALLEL. */ | |
782 | DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH) | |
1af1688b | 783 | |
b5c2f1d1 ZW |
784 | /* Appears only in define_predicate/define_special_predicate |
785 | expressions. Evaluates true only if the operand has an RTX code | |
6e7a4706 ZW |
786 | from the set given by the argument (a comma-separated list). If the |
787 | second argument is present and nonempty, it is a sequence of digits | |
788 | and/or letters which indicates the subexpression to test, using the | |
789 | same syntax as genextract/genrecog's location strings: 0-9 for | |
790 | XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to | |
791 | the result of the one before it. */ | |
792 | DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH) | |
1af1688b | 793 | |
b5c2f1d1 ZW |
794 | /* Appears only in define_predicate/define_special_predicate |
795 | expressions. The argument is a C expression to be injected at this | |
796 | point in the predicate formula. */ | |
797 | DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH) | |
c5c76735 | 798 | |
b5c2f1d1 | 799 | /* Insn (and related) definitions. */ |
1af1688b | 800 | |
b5c2f1d1 ZW |
801 | /* Definition of the pattern for one kind of instruction. |
802 | Operand: | |
803 | 0: names this instruction. | |
804 | If the name is the null string, the instruction is in the | |
805 | machine description just to be recognized, and will never be emitted by | |
806 | the tree to rtl expander. | |
807 | 1: is the pattern. | |
808 | 2: is a string which is a C expression | |
809 | giving an additional condition for recognizing this pattern. | |
810 | A null string means no extra condition. | |
811 | 3: is the action to execute if this pattern is matched. | |
812 | If this assembler code template starts with a * then it is a fragment of | |
813 | C code to run to decide on a template to use. Otherwise, it is the | |
814 | template to use. | |
815 | 4: optionally, a vector of attributes for this insn. | |
816 | */ | |
817 | DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA) | |
eab5c70a | 818 | |
b5c2f1d1 ZW |
819 | /* Definition of a peephole optimization. |
820 | 1st operand: vector of insn patterns to match | |
821 | 2nd operand: C expression that must be true | |
822 | 3rd operand: template or C code to produce assembler output. | |
823 | 4: optionally, a vector of attributes for this insn. | |
1af1688b | 824 | |
b5c2f1d1 ZW |
825 | This form is deprecated; use define_peephole2 instead. */ |
826 | DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA) | |
1af1688b | 827 | |
b5c2f1d1 ZW |
828 | /* Definition of a split operation. |
829 | 1st operand: insn pattern to match | |
830 | 2nd operand: C expression that must be true | |
831 | 3rd operand: vector of insn patterns to place into a SEQUENCE | |
832 | 4th operand: optionally, some C code to execute before generating the | |
833 | insns. This might, for example, create some RTX's and store them in | |
834 | elements of `recog_data.operand' for use by the vector of | |
835 | insn-patterns. | |
836 | (`operands' is an alias here for `recog_data.operand'). */ | |
837 | DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA) | |
838 | ||
839 | /* Definition of an insn and associated split. | |
840 | This is the concatenation, with a few modifications, of a define_insn | |
841 | and a define_split which share the same pattern. | |
842 | Operand: | |
843 | 0: names this instruction. | |
844 | If the name is the null string, the instruction is in the | |
845 | machine description just to be recognized, and will never be emitted by | |
846 | the tree to rtl expander. | |
847 | 1: is the pattern. | |
848 | 2: is a string which is a C expression | |
849 | giving an additional condition for recognizing this pattern. | |
850 | A null string means no extra condition. | |
851 | 3: is the action to execute if this pattern is matched. | |
852 | If this assembler code template starts with a * then it is a fragment of | |
853 | C code to run to decide on a template to use. Otherwise, it is the | |
854 | template to use. | |
855 | 4: C expression that must be true for split. This may start with "&&" | |
856 | in which case the split condition is the logical and of the insn | |
857 | condition and what follows the "&&" of this operand. | |
858 | 5: vector of insn patterns to place into a SEQUENCE | |
859 | 6: optionally, some C code to execute before generating the | |
860 | insns. This might, for example, create some RTX's and store them in | |
861 | elements of `recog_data.operand' for use by the vector of | |
862 | insn-patterns. | |
863 | (`operands' is an alias here for `recog_data.operand'). | |
864 | 7: optionally, a vector of attributes for this insn. */ | |
865 | DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA) | |
866 | ||
867 | /* Definition of an RTL peephole operation. | |
868 | Follows the same arguments as define_split. */ | |
869 | DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA) | |
870 | ||
871 | /* Define how to generate multiple insns for a standard insn name. | |
872 | 1st operand: the insn name. | |
873 | 2nd operand: vector of insn-patterns. | |
874 | Use match_operand to substitute an element of `recog_data.operand'. | |
875 | 3rd operand: C expression that must be true for this to be available. | |
876 | This may not test any operands. | |
877 | 4th operand: Extra C code to execute before generating the insns. | |
878 | This might, for example, create some RTX's and store them in | |
879 | elements of `recog_data.operand' for use by the vector of | |
880 | insn-patterns. | |
881 | (`operands' is an alias here for `recog_data.operand'). */ | |
882 | DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA) | |
883 | ||
884 | /* Define a requirement for delay slots. | |
885 | 1st operand: Condition involving insn attributes that, if true, | |
886 | indicates that the insn requires the number of delay slots | |
887 | shown. | |
888 | 2nd operand: Vector whose length is the three times the number of delay | |
889 | slots required. | |
890 | Each entry gives three conditions, each involving attributes. | |
891 | The first must be true for an insn to occupy that delay slot | |
892 | location. The second is true for all insns that can be | |
893 | annulled if the branch is true and the third is true for all | |
894 | insns that can be annulled if the branch is false. | |
1af1688b | 895 | |
b5c2f1d1 ZW |
896 | Multiple DEFINE_DELAYs may be present. They indicate differing |
897 | requirements for delay slots. */ | |
898 | DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA) | |
1af1688b | 899 | |
b5c2f1d1 ZW |
900 | /* Define attribute computation for `asm' instructions. */ |
901 | DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA) | |
1af1688b | 902 | |
b5c2f1d1 ZW |
903 | /* Definition of a conditional execution meta operation. Automatically |
904 | generates new instances of DEFINE_INSN, selected by having attribute | |
905 | "predicable" true. The new pattern will contain a COND_EXEC and the | |
906 | predicate at top-level. | |
1af1688b | 907 | |
b5c2f1d1 ZW |
908 | Operand: |
909 | 0: The predicate pattern. The top-level form should match a | |
910 | relational operator. Operands should have only one alternative. | |
911 | 1: A C expression giving an additional condition for recognizing | |
912 | the generated pattern. | |
913 | 2: A template or C code to produce assembler output. */ | |
914 | DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA) | |
1af1688b | 915 | |
b5c2f1d1 ZW |
916 | /* Definition of an operand predicate. The difference between |
917 | DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will | |
918 | not warn about a match_operand with no mode if it has a predicate | |
919 | defined with DEFINE_SPECIAL_PREDICATE. | |
ea8fbf8a | 920 | |
b5c2f1d1 ZW |
921 | Operand: |
922 | 0: The name of the predicate. | |
923 | 1: A boolean expression which computes whether or not the predicate | |
924 | matches. This expression can use IOR, AND, NOT, MATCH_OPERAND, | |
925 | MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog | |
926 | can calculate the set of RTX codes that can possibly match. | |
927 | 2: A C function body which must return true for the predicate to match. | |
928 | Optional. Use this when the test is too complicated to fit into a | |
929 | match_test expression. */ | |
930 | DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA) | |
931 | DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA) | |
1af1688b | 932 | |
f38840db ZW |
933 | /* Definition of a register operand constraint. This simply maps the |
934 | constraint string to a register class. | |
935 | ||
936 | Operand: | |
937 | 0: The name of the constraint (often, but not always, a single letter). | |
938 | 1: A C expression which evaluates to the appropriate register class for | |
939 | this constraint. If this is not just a constant, it should look only | |
940 | at -m switches and the like. | |
941 | 2: A docstring for this constraint, in Texinfo syntax; not currently | |
942 | used, in future will be incorporated into the manual's list of | |
943 | machine-specific operand constraints. */ | |
944 | DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA) | |
945 | ||
946 | /* Definition of a non-register operand constraint. These look at the | |
947 | operand and decide whether it fits the constraint. | |
948 | ||
949 | DEFINE_CONSTRAINT gets no special treatment if it fails to match. | |
950 | It is appropriate for constant-only constraints, and most others. | |
951 | ||
952 | DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made | |
953 | to match, if it doesn't already, by converting the operand to the form | |
954 | (mem (reg X)) where X is a base register. It is suitable for constraints | |
955 | that describe a subset of all memory references. | |
956 | ||
957 | DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made | |
958 | to match, if it doesn't already, by converting the operand to the form | |
959 | (reg X) where X is a base register. It is suitable for constraints that | |
960 | describe a subset of all address references. | |
961 | ||
962 | When in doubt, use plain DEFINE_CONSTRAINT. | |
963 | ||
964 | Operand: | |
965 | 0: The name of the constraint (often, but not always, a single letter). | |
966 | 1: A docstring for this constraint, in Texinfo syntax; not currently | |
967 | used, in future will be incorporated into the manual's list of | |
968 | machine-specific operand constraints. | |
969 | 2: A boolean expression which computes whether or not the constraint | |
970 | matches. It should follow the same rules as a define_predicate | |
971 | expression, including the bit about specifying the set of RTX codes | |
972 | that could possibly match. MATCH_TEST subexpressions may make use of | |
973 | these variables: | |
974 | `op' - the RTL object defining the operand. | |
975 | `mode' - the mode of `op'. | |
976 | `ival' - INTVAL(op), if op is a CONST_INT. | |
977 | `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE. | |
978 | `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE. | |
979 | `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point | |
980 | CONST_DOUBLE. | |
981 | Do not use ival/hval/lval/rval if op is not the appropriate kind of | |
982 | RTL object. */ | |
983 | DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA) | |
984 | DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA) | |
985 | DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA) | |
986 | ||
987 | ||
b5c2f1d1 | 988 | /* Constructions for CPU pipeline description described by NDFAs. */ |
1af1688b | 989 | |
b5c2f1d1 ZW |
990 | /* (define_cpu_unit string [string]) describes cpu functional |
991 | units (separated by comma). | |
1af1688b | 992 | |
b5c2f1d1 ZW |
993 | 1st operand: Names of cpu functional units. |
994 | 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON). | |
1af1688b | 995 | |
b5c2f1d1 ZW |
996 | All define_reservations, define_cpu_units, and |
997 | define_query_cpu_units should have unique names which may not be | |
998 | "nothing". */ | |
999 | DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA) | |
1af1688b | 1000 | |
b5c2f1d1 ZW |
1001 | /* (define_query_cpu_unit string [string]) describes cpu functional |
1002 | units analogously to define_cpu_unit. The reservation of such | |
1003 | units can be queried for automaton state. */ | |
1004 | DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA) | |
1af1688b | 1005 | |
b5c2f1d1 ZW |
1006 | /* (exclusion_set string string) means that each CPU functional unit |
1007 | in the first string can not be reserved simultaneously with any | |
1008 | unit whose name is in the second string and vise versa. CPU units | |
1009 | in the string are separated by commas. For example, it is useful | |
1010 | for description CPU with fully pipelined floating point functional | |
1011 | unit which can execute simultaneously only single floating point | |
1012 | insns or only double floating point insns. All CPU functional | |
1013 | units in a set should belong to the same automaton. */ | |
1014 | DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA) | |
1af1688b | 1015 | |
b5c2f1d1 ZW |
1016 | /* (presence_set string string) means that each CPU functional unit in |
1017 | the first string can not be reserved unless at least one of pattern | |
1018 | of units whose names are in the second string is reserved. This is | |
1019 | an asymmetric relation. CPU units or unit patterns in the strings | |
1020 | are separated by commas. Pattern is one unit name or unit names | |
1021 | separated by white-spaces. | |
1022 | ||
1023 | For example, it is useful for description that slot1 is reserved | |
1024 | after slot0 reservation for a VLIW processor. We could describe it | |
1025 | by the following construction | |
1af1688b | 1026 | |
b5c2f1d1 | 1027 | (presence_set "slot1" "slot0") |
1af1688b | 1028 | |
b5c2f1d1 ZW |
1029 | Or slot1 is reserved only after slot0 and unit b0 reservation. In |
1030 | this case we could write | |
1af1688b | 1031 | |
b5c2f1d1 | 1032 | (presence_set "slot1" "slot0 b0") |
1af1688b | 1033 | |
b5c2f1d1 ZW |
1034 | All CPU functional units in a set should belong to the same |
1035 | automaton. */ | |
1036 | DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA) | |
1af1688b | 1037 | |
b5c2f1d1 ZW |
1038 | /* (final_presence_set string string) is analogous to `presence_set'. |
1039 | The difference between them is when checking is done. When an | |
1040 | instruction is issued in given automaton state reflecting all | |
1041 | current and planned unit reservations, the automaton state is | |
1042 | changed. The first state is a source state, the second one is a | |
1043 | result state. Checking for `presence_set' is done on the source | |
1044 | state reservation, checking for `final_presence_set' is done on the | |
1045 | result reservation. This construction is useful to describe a | |
1046 | reservation which is actually two subsequent reservations. For | |
1047 | example, if we use | |
1af1688b | 1048 | |
b5c2f1d1 | 1049 | (presence_set "slot1" "slot0") |
1af1688b | 1050 | |
b5c2f1d1 ZW |
1051 | the following insn will be never issued (because slot1 requires |
1052 | slot0 which is absent in the source state). | |
1af1688b | 1053 | |
b5c2f1d1 | 1054 | (define_reservation "insn_and_nop" "slot0 + slot1") |
1af1688b | 1055 | |
b5c2f1d1 ZW |
1056 | but it can be issued if we use analogous `final_presence_set'. */ |
1057 | DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA) | |
1af1688b | 1058 | |
b5c2f1d1 ZW |
1059 | /* (absence_set string string) means that each CPU functional unit in |
1060 | the first string can be reserved only if each pattern of units | |
1061 | whose names are in the second string is not reserved. This is an | |
1062 | asymmetric relation (actually exclusion set is analogous to this | |
1063 | one but it is symmetric). CPU units or unit patterns in the string | |
1064 | are separated by commas. Pattern is one unit name or unit names | |
1065 | separated by white-spaces. | |
1af1688b | 1066 | |
b5c2f1d1 ZW |
1067 | For example, it is useful for description that slot0 can not be |
1068 | reserved after slot1 or slot2 reservation for a VLIW processor. We | |
1069 | could describe it by the following construction | |
1af1688b | 1070 | |
b5c2f1d1 | 1071 | (absence_set "slot2" "slot0, slot1") |
1af1688b | 1072 | |
b5c2f1d1 ZW |
1073 | Or slot2 can not be reserved if slot0 and unit b0 are reserved or |
1074 | slot1 and unit b1 are reserved . In this case we could write | |
1af1688b | 1075 | |
b5c2f1d1 | 1076 | (absence_set "slot2" "slot0 b0, slot1 b1") |
1af1688b | 1077 | |
b5c2f1d1 ZW |
1078 | All CPU functional units in a set should to belong the same |
1079 | automaton. */ | |
1080 | DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA) | |
1af1688b | 1081 | |
b5c2f1d1 ZW |
1082 | /* (final_absence_set string string) is analogous to `absence_set' but |
1083 | checking is done on the result (state) reservation. See comments | |
1084 | for `final_presence_set'. */ | |
1085 | DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA) | |
b18cfc28 | 1086 | |
b5c2f1d1 ZW |
1087 | /* (define_bypass number out_insn_names in_insn_names) names bypass |
1088 | with given latency (the first number) from insns given by the first | |
1089 | string (see define_insn_reservation) into insns given by the second | |
1090 | string. Insn names in the strings are separated by commas. The | |
1091 | third operand is optional name of function which is additional | |
1092 | guard for the bypass. The function will get the two insns as | |
1093 | parameters. If the function returns zero the bypass will be | |
1094 | ignored for this case. Additional guard is necessary to recognize | |
20a07f44 VM |
1095 | complicated bypasses, e.g. when consumer is load address. If there |
1096 | are more one bypass with the same output and input insns, the | |
1097 | chosen bypass is the first bypass with a guard in description whose | |
1098 | guard function returns nonzero. If there is no such bypass, then | |
1099 | bypass without the guard function is chosen. */ | |
b5c2f1d1 | 1100 | DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA) |
1af1688b | 1101 | |
b5c2f1d1 ZW |
1102 | /* (define_automaton string) describes names of automata generated and |
1103 | used for pipeline hazards recognition. The names are separated by | |
1104 | comma. Actually it is possibly to generate the single automaton | |
1105 | but unfortunately it can be very large. If we use more one | |
1106 | automata, the summary size of the automata usually is less than the | |
1107 | single one. The automaton name is used in define_cpu_unit and | |
1108 | define_query_cpu_unit. All automata should have unique names. */ | |
1109 | DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA) | |
1eb8759b | 1110 | |
b5c2f1d1 ZW |
1111 | /* (automata_option string) describes option for generation of |
1112 | automata. Currently there are the following options: | |
1eb8759b | 1113 | |
b5c2f1d1 ZW |
1114 | o "no-minimization" which makes no minimization of automata. This |
1115 | is only worth to do when we are debugging the description and | |
1116 | need to look more accurately at reservations of states. | |
7913f3d0 | 1117 | |
b5c2f1d1 ZW |
1118 | o "time" which means printing additional time statistics about |
1119 | generation of automata. | |
1120 | ||
1121 | o "v" which means generation of file describing the result | |
1122 | automata. The file has suffix `.dfa' and can be used for the | |
1123 | description verification and debugging. | |
1af1688b | 1124 | |
b5c2f1d1 ZW |
1125 | o "w" which means generation of warning instead of error for |
1126 | non-critical errors. | |
1af1688b | 1127 | |
b5c2f1d1 | 1128 | o "ndfa" which makes nondeterministic finite state automata. |
1af1688b | 1129 | |
b5c2f1d1 ZW |
1130 | o "progress" which means output of a progress bar showing how many |
1131 | states were generated so far for automaton being processed. */ | |
1132 | DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA) | |
1af1688b | 1133 | |
b5c2f1d1 ZW |
1134 | /* (define_reservation string string) names reservation (the first |
1135 | string) of cpu functional units (the 2nd string). Sometimes unit | |
1136 | reservations for different insns contain common parts. In such | |
1137 | case, you can describe common part and use its name (the 1st | |
1138 | parameter) in regular expression in define_insn_reservation. All | |
1139 | define_reservations, define_cpu_units, and define_query_cpu_units | |
1140 | should have unique names which may not be "nothing". */ | |
1141 | DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA) | |
1af1688b | 1142 | |
b5c2f1d1 ZW |
1143 | /* (define_insn_reservation name default_latency condition regexpr) |
1144 | describes reservation of cpu functional units (the 3nd operand) for | |
1145 | instruction which is selected by the condition (the 2nd parameter). | |
1146 | The first parameter is used for output of debugging information. | |
1147 | The reservations are described by a regular expression according | |
1148 | the following syntax: | |
1af1688b | 1149 | |
b5c2f1d1 ZW |
1150 | regexp = regexp "," oneof |
1151 | | oneof | |
1af1688b | 1152 | |
b5c2f1d1 ZW |
1153 | oneof = oneof "|" allof |
1154 | | allof | |
1af1688b | 1155 | |
b5c2f1d1 ZW |
1156 | allof = allof "+" repeat |
1157 | | repeat | |
1158 | ||
1159 | repeat = element "*" number | |
1160 | | element | |
1af1688b | 1161 | |
b5c2f1d1 ZW |
1162 | element = cpu_function_unit_name |
1163 | | reservation_name | |
1164 | | result_name | |
1165 | | "nothing" | |
1166 | | "(" regexp ")" | |
1af1688b | 1167 | |
b5c2f1d1 ZW |
1168 | 1. "," is used for describing start of the next cycle in |
1169 | reservation. | |
1af1688b | 1170 | |
b5c2f1d1 ZW |
1171 | 2. "|" is used for describing the reservation described by the |
1172 | first regular expression *or* the reservation described by the | |
1173 | second regular expression *or* etc. | |
2928cd7a | 1174 | |
b5c2f1d1 ZW |
1175 | 3. "+" is used for describing the reservation described by the |
1176 | first regular expression *and* the reservation described by the | |
1177 | second regular expression *and* etc. | |
2928cd7a | 1178 | |
b5c2f1d1 ZW |
1179 | 4. "*" is used for convenience and simply means sequence in |
1180 | which the regular expression are repeated NUMBER times with | |
1181 | cycle advancing (see ","). | |
2928cd7a | 1182 | |
b5c2f1d1 | 1183 | 5. cpu functional unit name which means its reservation. |
2928cd7a | 1184 | |
b5c2f1d1 | 1185 | 6. reservation name -- see define_reservation. |
1af1688b | 1186 | |
b5c2f1d1 | 1187 | 7. string "nothing" means no units reservation. */ |
1af1688b | 1188 | |
b5c2f1d1 | 1189 | DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA) |
1af1688b | 1190 | |
b5c2f1d1 | 1191 | /* Expressions used for insn attributes. */ |
1af1688b | 1192 | |
b5c2f1d1 ZW |
1193 | /* Definition of an insn attribute. |
1194 | 1st operand: name of the attribute | |
1195 | 2nd operand: comma-separated list of possible attribute values | |
1196 | 3rd operand: expression for the default value of the attribute. */ | |
1197 | DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA) | |
1af1688b | 1198 | |
b5c2f1d1 ZW |
1199 | /* Marker for the name of an attribute. */ |
1200 | DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA) | |
0dfa1860 | 1201 | |
b5c2f1d1 ZW |
1202 | /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and |
1203 | in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that | |
1204 | pattern. | |
0dfa1860 | 1205 | |
b5c2f1d1 ZW |
1206 | (set_attr "name" "value") is equivalent to |
1207 | (set (attr "name") (const_string "value")) */ | |
1208 | DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA) | |
0dfa1860 | 1209 | |
b5c2f1d1 ZW |
1210 | /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to |
1211 | specify that attribute values are to be assigned according to the | |
1212 | alternative matched. | |
0dfa1860 | 1213 | |
b5c2f1d1 | 1214 | The following three expressions are equivalent: |
f9f27ee5 | 1215 | |
b5c2f1d1 ZW |
1216 | (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1") |
1217 | (eq_attrq "alternative" "2") (const_string "a2")] | |
1218 | (const_string "a3"))) | |
1219 | (set_attr_alternative "att" [(const_string "a1") (const_string "a2") | |
1220 | (const_string "a3")]) | |
1221 | (set_attr "att" "a1,a2,a3") | |
1222 | */ | |
1223 | DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA) | |
f9f27ee5 | 1224 | |
b5c2f1d1 ZW |
1225 | /* A conditional expression true if the value of the specified attribute of |
1226 | the current insn equals the specified value. The first operand is the | |
1227 | attribute name and the second is the comparison value. */ | |
1228 | DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA) | |
f9f27ee5 | 1229 | |
b5c2f1d1 ZW |
1230 | /* A special case of the above representing a set of alternatives. The first |
1231 | operand is bitmap of the set, the second one is the default value. */ | |
1232 | DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA) | |
f9f27ee5 | 1233 | |
b5c2f1d1 ZW |
1234 | /* A conditional expression which is true if the specified flag is |
1235 | true for the insn being scheduled in reorg. | |
f9f27ee5 | 1236 | |
b5c2f1d1 ZW |
1237 | genattr.c defines the following flags which can be tested by |
1238 | (attr_flag "foo") expressions in eligible_for_delay. | |
f9f27ee5 | 1239 | |
b5c2f1d1 | 1240 | forward, backward, very_likely, likely, very_unlikely, and unlikely. */ |
f9f27ee5 | 1241 | |
b5c2f1d1 | 1242 | DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA) |
f9f27ee5 | 1243 | |
b5c2f1d1 ZW |
1244 | /* General conditional. The first operand is a vector composed of pairs of |
1245 | expressions. The first element of each pair is evaluated, in turn. | |
1246 | The value of the conditional is the second expression of the first pair | |
1247 | whose first expression evaluates nonzero. If none of the expressions is | |
1248 | true, the second operand will be used as the value of the conditional. */ | |
1249 | DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA) | |
f9f27ee5 | 1250 | |
9e995780 | 1251 | #endif /* GENERATOR_FILE */ |
d9d4fb43 | 1252 | |
1af1688b RK |
1253 | /* |
1254 | Local variables: | |
1255 | mode:c | |
1af1688b RK |
1256 | End: |
1257 | */ |