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1af1688b RK |
1 | /* This file contains the definitions and documentation for the |
2 | Register Transfer Expressions (rtx's) that make up the | |
3 | Register Transfer Language (rtl) used in the Back End of the GNU compiler. | |
0a1c58a2 | 4 | Copyright (C) 1987, 88, 92, 94, 95, 97, 98, 1999, 2000 |
c5c76735 | 5 | Free Software Foundation, Inc. |
1af1688b | 6 | |
1322177d | 7 | This file is part of GCC. |
1af1688b | 8 | |
1322177d LB |
9 | GCC is free software; you can redistribute it and/or modify it under |
10 | the terms of the GNU General Public License as published by the Free | |
11 | Software Foundation; either version 2, or (at your option) any later | |
12 | version. | |
1af1688b | 13 | |
1322177d LB |
14 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
15 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | for more details. | |
1af1688b RK |
18 | |
19 | You should have received a copy of the GNU General Public License | |
1322177d LB |
20 | along with GCC; see the file COPYING. If not, write to the Free |
21 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
22 | 02111-1307, USA. */ | |
1af1688b RK |
23 | |
24 | ||
25 | /* Expression definitions and descriptions for all targets are in this file. | |
26 | Some will not be used for some targets. | |
27 | ||
28 | The fields in the cpp macro call "DEF_RTL_EXPR()" | |
29 | are used to create declarations in the C source of the compiler. | |
30 | ||
31 | The fields are: | |
32 | ||
33 | 1. The internal name of the rtx used in the C source. | |
34 | It is a tag in the enumeration "enum rtx_code" defined in "rtl.h". | |
35 | By convention these are in UPPER_CASE. | |
36 | ||
37 | 2. The name of the rtx in the external ASCII format read by | |
38 | read_rtx(), and printed by print_rtx(). | |
39 | These names are stored in rtx_name[]. | |
40 | By convention these are the internal (field 1) names in lower_case. | |
41 | ||
42 | 3. The print format, and type of each rtx->fld[] (field) in this rtx. | |
43 | These formats are stored in rtx_format[]. | |
44 | The meaning of the formats is documented in front of this array in rtl.c | |
45 | ||
46 | 4. The class of the rtx. These are stored in rtx_class and are accessed | |
47 | via the GET_RTX_CLASS macro. They are defined as follows: | |
48 | ||
49 | "o" an rtx code that can be used to represent an object (e.g, REG, MEM) | |
50 | "<" an rtx code for a comparison (e.g, EQ, NE, LT) | |
51 | "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT) | |
52 | "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT) | |
53 | "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE) | |
54 | "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV) | |
55 | "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT) | |
56 | "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) | |
57 | "m" an rtx code for something that matches in insns (e.g, MATCH_DUP) | |
693e265f | 58 | "g" an rtx code for grouping insns together (e.g, GROUP_PARALLEL) |
4b983fdc | 59 | "a" an rtx code for autoincrement addressing modes (e.g. POST_DEC) |
1af1688b RK |
60 | "x" everything else |
61 | ||
62 | */ | |
63 | ||
64 | /* --------------------------------------------------------------------- | |
65 | Expressions (and "meta" expressions) used for structuring the | |
66 | rtl representation of a program. | |
67 | --------------------------------------------------------------------- */ | |
68 | ||
69 | /* an expression code name unknown to the reader */ | |
70 | DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x') | |
71 | ||
72 | /* (NIL) is used by rtl reader and printer to represent a null pointer. */ | |
73 | ||
74 | DEF_RTL_EXPR(NIL, "nil", "*", 'x') | |
75 | ||
76 | /* --------------------------------------------------------------------- | |
77 | Expressions used in constructing lists. | |
78 | --------------------------------------------------------------------- */ | |
79 | ||
80 | /* a linked list of expressions */ | |
81 | DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x') | |
82 | ||
83 | /* a linked list of instructions. | |
84 | The insns are represented in print by their uids. */ | |
85 | DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x') | |
86 | ||
87 | /* ---------------------------------------------------------------------- | |
6dc42e49 | 88 | Expression types for machine descriptions. |
1af1688b RK |
89 | These do not appear in actual rtl code in the compiler. |
90 | ---------------------------------------------------------------------- */ | |
91 | ||
92 | /* Appears only in machine descriptions. | |
93 | Means use the function named by the second arg (the string) | |
94 | as a predicate; if matched, store the structure that was matched | |
95 | in the operand table at index specified by the first arg (the integer). | |
96 | If the second arg is the null string, the structure is just stored. | |
97 | ||
98 | A third string argument indicates to the register allocator restrictions | |
99 | on where the operand can be allocated. | |
100 | ||
101 | If the target needs no restriction on any instruction this field should | |
102 | be the null string. | |
103 | ||
104 | The string is prepended by: | |
105 | '=' to indicate the operand is only written to. | |
106 | '+' to indicate the operand is both read and written to. | |
107 | ||
956d6950 | 108 | Each character in the string represents an allocable class for an operand. |
1af1688b RK |
109 | 'g' indicates the operand can be any valid class. |
110 | 'i' indicates the operand can be immediate (in the instruction) data. | |
111 | 'r' indicates the operand can be in a register. | |
112 | 'm' indicates the operand can be in memory. | |
113 | 'o' a subset of the 'm' class. Those memory addressing modes that | |
114 | can be offset at compile time (have a constant added to them). | |
115 | ||
116 | Other characters indicate target dependent operand classes and | |
117 | are described in each target's machine description. | |
118 | ||
119 | For instructions with more than one operand, sets of classes can be | |
120 | separated by a comma to indicate the appropriate multi-operand constraints. | |
121 | There must be a 1 to 1 correspondence between these sets of classes in | |
122 | all operands for an instruction. | |
123 | */ | |
124 | DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm') | |
125 | ||
126 | /* Appears only in machine descriptions. | |
127 | Means match a SCRATCH or a register. When used to generate rtl, a | |
128 | SCRATCH is generated. As for MATCH_OPERAND, the mode specifies | |
129 | the desired mode and the first argument is the operand number. | |
130 | The second argument is the constraint. */ | |
131 | DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm') | |
132 | ||
133 | /* Appears only in machine descriptions. | |
134 | Means match only something equal to what is stored in the operand table | |
135 | at the index specified by the argument. */ | |
136 | DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm') | |
137 | ||
138 | /* Appears only in machine descriptions. | |
139 | Means apply a predicate, AND match recursively the operands of the rtx. | |
140 | Operand 0 is the operand-number, as in match_operand. | |
141 | Operand 1 is a predicate to apply (as a string, a function name). | |
142 | Operand 2 is a vector of expressions, each of which must match | |
143 | one subexpression of the rtx this construct is matching. */ | |
144 | DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm') | |
145 | ||
146 | /* Appears only in machine descriptions. | |
147 | Means to match a PARALLEL of arbitrary length. The predicate is applied | |
148 | to the PARALLEL and the initial expressions in the PARALLEL are matched. | |
149 | Operand 0 is the operand-number, as in match_operand. | |
150 | Operand 1 is a predicate to apply to the PARALLEL. | |
151 | Operand 2 is a vector of expressions, each of which must match the | |
152 | corresponding element in the PARALLEL. */ | |
153 | DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm') | |
154 | ||
155 | /* Appears only in machine descriptions. | |
156 | Means match only something equal to what is stored in the operand table | |
157 | at the index specified by the argument. For MATCH_OPERATOR. */ | |
158 | DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm') | |
159 | ||
ae3c61fa RK |
160 | /* Appears only in machine descriptions. |
161 | Means match only something equal to what is stored in the operand table | |
162 | at the index specified by the argument. For MATCH_PARALLEL. */ | |
163 | DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm') | |
164 | ||
693e265f MM |
165 | /* Appears only in machine descriptions. |
166 | Operand 0 is the operand number, as in match_operand. | |
167 | Operand 1 is the predicate to apply to the insn. */ | |
a669dbf8 | 168 | DEF_RTL_EXPR(MATCH_INSN, "match_insn", "is", 'm') |
693e265f | 169 | |
1af1688b RK |
170 | /* Appears only in machine descriptions. |
171 | Defines the pattern for one kind of instruction. | |
172 | Operand: | |
173 | 0: names this instruction. | |
174 | If the name is the null string, the instruction is in the | |
175 | machine description just to be recognized, and will never be emitted by | |
176 | the tree to rtl expander. | |
177 | 1: is the pattern. | |
178 | 2: is a string which is a C expression | |
179 | giving an additional condition for recognizing this pattern. | |
180 | A null string means no extra condition. | |
181 | 3: is the action to execute if this pattern is matched. | |
182 | If this assembler code template starts with a * then it is a fragment of | |
183 | C code to run to decide on a template to use. Otherwise, it is the | |
184 | template to use. | |
185 | 4: optionally, a vector of attributes for this insn. | |
186 | */ | |
1f3b37a3 | 187 | DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", 'x') |
1af1688b RK |
188 | |
189 | /* Definition of a peephole optimization. | |
190 | 1st operand: vector of insn patterns to match | |
191 | 2nd operand: C expression that must be true | |
192 | 3rd operand: template or C code to produce assembler output. | |
193 | 4: optionally, a vector of attributes for this insn. | |
194 | */ | |
1f3b37a3 | 195 | DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", 'x') |
1af1688b RK |
196 | |
197 | /* Definition of a split operation. | |
198 | 1st operand: insn pattern to match | |
199 | 2nd operand: C expression that must be true | |
200 | 3rd operand: vector of insn patterns to place into a SEQUENCE | |
201 | 4th operand: optionally, some C code to execute before generating the | |
202 | insns. This might, for example, create some RTX's and store them in | |
203 | elements of `recog_operand' for use by the vector of insn-patterns. | |
204 | (`operands' is an alias here for `recog_operand'). */ | |
205 | DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x') | |
206 | ||
c88c0d42 CP |
207 | /* Definition of an insn and associated split. |
208 | This is the concatenation, with a few modifications, of a define_insn | |
209 | and a define_split which share the same pattern. | |
210 | Operand: | |
211 | 0: names this instruction. | |
212 | If the name is the null string, the instruction is in the | |
213 | machine description just to be recognized, and will never be emitted by | |
214 | the tree to rtl expander. | |
215 | 1: is the pattern. | |
216 | 2: is a string which is a C expression | |
217 | giving an additional condition for recognizing this pattern. | |
218 | A null string means no extra condition. | |
219 | 3: is the action to execute if this pattern is matched. | |
220 | If this assembler code template starts with a * then it is a fragment of | |
221 | C code to run to decide on a template to use. Otherwise, it is the | |
222 | template to use. | |
223 | 4: C expression that must be true for split. This may start with "&&" | |
224 | in which case the split condition is the logical and of the insn | |
225 | condition and what follows the "&&" of this operand. | |
226 | 5: vector of insn patterns to place into a SEQUENCE | |
227 | 6: optionally, some C code to execute before generating the | |
228 | insns. This might, for example, create some RTX's and store them in | |
229 | elements of `recog_operand' for use by the vector of insn-patterns. | |
230 | (`operands' is an alias here for `recog_operand'). | |
231 | 7: optionally, a vector of attributes for this insn. */ | |
1f3b37a3 | 232 | DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", 'x') |
c88c0d42 | 233 | |
ede7cd44 RH |
234 | /* Definition of an RTL peephole operation. |
235 | Follows the same arguments as define_split. */ | |
236 | DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", 'x') | |
237 | ||
1af1688b RK |
238 | /* Definition of a combiner pattern. |
239 | Operands not defined yet. */ | |
240 | DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x') | |
241 | ||
242 | /* Define how to generate multiple insns for a standard insn name. | |
243 | 1st operand: the insn name. | |
244 | 2nd operand: vector of insn-patterns. | |
245 | Use match_operand to substitute an element of `recog_operand'. | |
246 | 3rd operand: C expression that must be true for this to be available. | |
247 | This may not test any operands. | |
248 | 4th operand: Extra C code to execute before generating the insns. | |
249 | This might, for example, create some RTX's and store them in | |
250 | elements of `recog_operand' for use by the vector of insn-patterns. | |
251 | (`operands' is an alias here for `recog_operand'). */ | |
252 | DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x') | |
253 | ||
254 | /* Define a requirement for delay slots. | |
255 | 1st operand: Condition involving insn attributes that, if true, | |
256 | indicates that the insn requires the number of delay slots | |
257 | shown. | |
258 | 2nd operand: Vector whose length is the three times the number of delay | |
259 | slots required. | |
260 | Each entry gives three conditions, each involving attributes. | |
261 | The first must be true for an insn to occupy that delay slot | |
262 | location. The second is true for all insns that can be | |
263 | annulled if the branch is true and the third is true for all | |
264 | insns that can be annulled if the branch is false. | |
265 | ||
266 | Multiple DEFINE_DELAYs may be present. They indicate differing | |
267 | requirements for delay slots. */ | |
268 | DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x') | |
269 | ||
270 | /* Define a set of insns that requires a function unit. This means that | |
271 | these insns produce their result after a delay and that there may be | |
272 | restrictions on the number of insns of this type that can be scheduled | |
273 | simultaneously. | |
274 | ||
275 | More than one DEFINE_FUNCTION_UNIT can be specified for a function unit. | |
276 | Each gives a set of operations and associated delays. The first three | |
277 | operands must be the same for each operation for the same function unit. | |
278 | ||
f6601f3a | 279 | All delays are specified in cycles. |
1af1688b RK |
280 | |
281 | 1st operand: Name of function unit (mostly for documentation) | |
282 | 2nd operand: Number of identical function units in CPU | |
283 | 3rd operand: Total number of simultaneous insns that can execute on this | |
284 | function unit; 0 if unlimited. | |
285 | 4th operand: Condition involving insn attribute, that, if true, specifies | |
286 | those insns that this expression applies to. | |
287 | 5th operand: Constant delay after which insn result will be | |
288 | available. | |
289 | 6th operand: Delay until next insn can be scheduled on the function unit | |
290 | executing this operation. The meaning depends on whether or | |
291 | not the next operand is supplied. | |
292 | 7th operand: If this operand is not specified, the 6th operand gives the | |
f6601f3a TW |
293 | number of cycles after the instruction matching the 4th |
294 | operand begins using the function unit until a subsequent | |
295 | insn can begin. A value of zero should be used for a | |
296 | unit with no issue constraints. If only one operation can | |
297 | be executed a time and the unit is busy for the entire time, | |
298 | the 3rd operand should be specified as 1, the 6th operand | |
956d6950 | 299 | should be specified as 0, and the 7th operand should not |
f6601f3a | 300 | be specified. |
1af1688b RK |
301 | |
302 | If this operand is specified, it is a list of attribute | |
303 | expressions. If an insn for which any of these expressions | |
304 | is true is currently executing on the function unit, the | |
f6601f3a TW |
305 | issue delay will be given by the 6th operand. Otherwise, |
306 | the insn can be immediately scheduled (subject to the limit | |
307 | on the number of simultaneous operations executing on the | |
1af1688b RK |
308 | unit.) */ |
309 | DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x') | |
310 | ||
311 | /* Define attribute computation for `asm' instructions. */ | |
312 | DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' ) | |
313 | ||
3262c1f5 RH |
314 | /* Definition of a conditional execution meta operation. Automatically |
315 | generates new instances of DEFINE_INSN, selected by having attribute | |
316 | "predicable" true. The new pattern will contain a COND_EXEC and the | |
317 | predicate at top-level. | |
318 | ||
319 | Operand: | |
320 | 0: The predicate pattern. The top-level form should match a | |
321 | relational operator. Operands should have only one alternative. | |
322 | 1: A C expression giving an additional condition for recognizing | |
323 | the generated pattern. | |
324 | 2: A template or C code to produce assembler output. */ | |
325 | DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", 'x') | |
326 | ||
1af1688b RK |
327 | /* SEQUENCE appears in the result of a `gen_...' function |
328 | for a DEFINE_EXPAND that wants to make several insns. | |
329 | Its elements are the bodies of the insns that should be made. | |
330 | `emit_insn' takes the SEQUENCE apart and makes separate insns. */ | |
331 | DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x') | |
332 | ||
f0f61682 | 333 | /* Refers to the address of its argument. This is only used in alias.c. */ |
1af1688b RK |
334 | DEF_RTL_EXPR(ADDRESS, "address", "e", 'm') |
335 | ||
336 | /* ---------------------------------------------------------------------- | |
337 | Expressions used for insn attributes. These also do not appear in | |
338 | actual rtl code in the compiler. | |
339 | ---------------------------------------------------------------------- */ | |
340 | ||
341 | /* Definition of an insn attribute. | |
342 | 1st operand: name of the attribute | |
343 | 2nd operand: comma-separated list of possible attribute values | |
344 | 3rd operand: expression for the default value of the attribute. */ | |
345 | DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x') | |
346 | ||
347 | /* Marker for the name of an attribute. */ | |
348 | DEF_RTL_EXPR(ATTR, "attr", "s", 'x') | |
349 | ||
350 | /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and | |
351 | in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that | |
352 | pattern. | |
353 | ||
354 | (set_attr "name" "value") is equivalent to | |
355 | (set (attr "name") (const_string "value")) */ | |
356 | DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x') | |
357 | ||
358 | /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to | |
359 | specify that attribute values are to be assigned according to the | |
360 | alternative matched. | |
361 | ||
362 | The following three expressions are equivalent: | |
363 | ||
364 | (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1") | |
365 | (eq_attrq "alternative" "2") (const_string "a2")] | |
366 | (const_string "a3"))) | |
367 | (set_attr_alternative "att" [(const_string "a1") (const_string "a2") | |
368 | (const_string "a3")]) | |
369 | (set_attr "att" "a1,a2,a3") | |
370 | */ | |
371 | DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x') | |
372 | ||
373 | /* A conditional expression true if the value of the specified attribute of | |
374 | the current insn equals the specified value. The first operand is the | |
375 | attribute name and the second is the comparison value. */ | |
376 | DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x') | |
377 | ||
417a6986 JL |
378 | /* A conditional expression which is true if the specified flag is |
379 | true for the insn being scheduled in reorg. | |
380 | ||
381 | genattr.c defines the following flags which can be tested by | |
382 | (attr_flag "foo") expressions in eligible_for_delay. | |
383 | ||
384 | forward, backward, very_likely, likely, very_unlikely, and unlikely. */ | |
385 | ||
386 | DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", 'x') | |
387 | ||
1af1688b RK |
388 | /* ---------------------------------------------------------------------- |
389 | Expression types used for things in the instruction chain. | |
390 | ||
391 | All formats must start with "iuu" to handle the chain. | |
392 | Each insn expression holds an rtl instruction and its semantics | |
393 | during back-end processing. | |
394 | See macros's in "rtl.h" for the meaning of each rtx->fld[]. | |
395 | ||
396 | ---------------------------------------------------------------------- */ | |
397 | ||
398 | /* An instruction that cannot jump. */ | |
399 | DEF_RTL_EXPR(INSN, "insn", "iuueiee", 'i') | |
400 | ||
401 | /* An instruction that can possibly jump. | |
402 | Fields ( rtx->fld[] ) have exact same meaning as INSN's. */ | |
403 | DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuueiee0", 'i') | |
404 | ||
405 | /* An instruction that can possibly call a subroutine | |
406 | but which will not change which instruction comes next | |
407 | in the current function. | |
cc867704 RK |
408 | Field ( rtx->fld[7] ) is CALL_INSN_FUNCTION_USAGE. |
409 | All other fields ( rtx->fld[] ) have exact same meaning as INSN's. */ | |
410 | DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuueieee", 'i') | |
1af1688b RK |
411 | |
412 | /* A marker that indicates that control will not flow through. */ | |
413 | DEF_RTL_EXPR(BARRIER, "barrier", "iuu", 'x') | |
414 | ||
415 | /* Holds a label that is followed by instructions. | |
416 | Operand: | |
be1bb652 RH |
417 | 3: is used in jump.c for the use-count of the label. |
418 | 4: is used in flow.c to point to the chain of label_ref's to this label. | |
419 | 5: is a number that is unique in the entire compilation. | |
420 | 6: is the user-given name of the label, if any. | |
8cd0faaf | 421 | 7: is the alternate label name. */ |
be1bb652 | 422 | DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuu00iss", 'x') |
1af1688b RK |
423 | |
424 | /* Say where in the code a source line starts, for symbol table's sake. | |
f5540cd4 RH |
425 | Operand: |
426 | 3: filename, if line number > 0, note-specific data otherwise. | |
427 | 4: line number if > 0, enum note_insn otherwise. | |
428 | 5: unique number if line number == note_insn_deleted_label. */ | |
429 | DEF_RTL_EXPR(NOTE, "note", "iuu0ni", 'x') | |
1af1688b | 430 | |
1af1688b RK |
431 | /* ---------------------------------------------------------------------- |
432 | Top level constituents of INSN, JUMP_INSN and CALL_INSN. | |
433 | ---------------------------------------------------------------------- */ | |
434 | ||
6b29b0e2 JW |
435 | /* Conditionally execute code. |
436 | Operand 0 is the condition that if true, the code is executed. | |
437 | Operand 1 is the code to be executed (typically a SET). | |
438 | ||
439 | Semantics are that there are no side effects if the condition | |
440 | is false. This pattern is created automatically by the if_convert | |
441 | pass run after reload or by target-specific splitters. */ | |
442 | DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", 'x') | |
443 | ||
444 | /* Several operations to be done in parallel (perhaps under COND_EXEC). */ | |
1af1688b RK |
445 | DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x') |
446 | ||
447 | /* A string that is passed through to the assembler as input. | |
448 | One can obviously pass comments through by using the | |
449 | assembler comment syntax. | |
450 | These occur in an insn all by themselves as the PATTERN. | |
451 | They also appear inside an ASM_OPERANDS | |
452 | as a convenient way to hold a string. */ | |
453 | DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x') | |
454 | ||
455 | /* An assembler instruction with operands. | |
456 | 1st operand is the instruction template. | |
457 | 2nd operand is the constraint for the output. | |
458 | 3rd operand is the number of the output this expression refers to. | |
459 | When an insn stores more than one value, a separate ASM_OPERANDS | |
460 | is made for each output; this integer distinguishes them. | |
461 | 4th is a vector of values of input operands. | |
462 | 5th is a vector of modes and constraints for the input operands. | |
463 | Each element is an ASM_INPUT containing a constraint string | |
464 | and whose mode indicates the mode of the input operand. | |
465 | 6th is the name of the containing source file. | |
466 | 7th is the source line number. */ | |
467 | DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x') | |
468 | ||
1fcea2b0 RK |
469 | /* A machine-specific operation. |
470 | 1st operand is a vector of operands being used by the operation so that | |
471 | any needed reloads can be done. | |
472 | 2nd operand is a unique value saying which of a number of machine-specific | |
473 | operations is to be performed. | |
474 | (Note that the vector must be the first operand because of the way that | |
475 | genrecog.c record positions within an insn.) | |
476 | This can occur all by itself in a PATTERN, as a component of a PARALLEL, | |
477 | or inside an expression. */ | |
478 | DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", 'x') | |
479 | ||
6dc42e49 | 480 | /* Similar, but a volatile operation and one which may trap. */ |
1fcea2b0 RK |
481 | DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", 'x') |
482 | ||
1af1688b RK |
483 | /* Vector of addresses, stored as full words. */ |
484 | /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */ | |
485 | DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x') | |
486 | ||
487 | /* Vector of address differences X0 - BASE, X1 - BASE, ... | |
488 | First operand is BASE; the vector contains the X's. | |
489 | The machine mode of this rtx says how much space to leave | |
33f7f353 JR |
490 | for each difference and is adjusted by branch shortening if |
491 | CASE_VECTOR_SHORTEN_MODE is defined. | |
492 | The third and fourth operands store the target labels with the | |
493 | minimum and maximum addresses respectively. | |
494 | The fifth operand stores flags for use by branch shortening. | |
495 | Set at the start of shorten_branches: | |
496 | min_align: the minimum alignment for any of the target labels. | |
497 | base_after_vec: true iff BASE is after the ADDR_DIFF_VEC. | |
498 | min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC. | |
499 | max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC. | |
500 | min_after_base: true iff minimum address target label is after BASE. | |
501 | max_after_base: true iff maximum address target label is after BASE. | |
502 | Set by the actual branch shortening process: | |
503 | offset_unsigned: true iff offsets have to be treated as unsigned. | |
504 | scale: scaling that is necessary to make offsets fit into the mode. | |
505 | ||
506 | The third, fourth and fifth operands are only valid when | |
507 | CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing | |
508 | compilations. */ | |
509 | ||
8f985ec4 | 510 | DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", 'x') |
1af1688b RK |
511 | |
512 | /* ---------------------------------------------------------------------- | |
513 | At the top level of an instruction (perhaps under PARALLEL). | |
514 | ---------------------------------------------------------------------- */ | |
515 | ||
516 | /* Assignment. | |
517 | Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to. | |
518 | Operand 2 is the value stored there. | |
519 | ALL assignment must use SET. | |
520 | Instructions that do multiple assignments must use multiple SET, | |
521 | under PARALLEL. */ | |
522 | DEF_RTL_EXPR(SET, "set", "ee", 'x') | |
523 | ||
524 | /* Indicate something is used in a way that we don't want to explain. | |
525 | For example, subroutine calls will use the register | |
526 | in which the static chain is passed. */ | |
527 | DEF_RTL_EXPR(USE, "use", "e", 'x') | |
528 | ||
529 | /* Indicate something is clobbered in a way that we don't want to explain. | |
530 | For example, subroutine calls will clobber some physical registers | |
531 | (the ones that are by convention not saved). */ | |
532 | DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x') | |
533 | ||
534 | /* Call a subroutine. | |
535 | Operand 1 is the address to call. | |
536 | Operand 2 is the number of arguments. */ | |
537 | ||
538 | DEF_RTL_EXPR(CALL, "call", "ee", 'x') | |
539 | ||
540 | /* Return from a subroutine. */ | |
541 | ||
542 | DEF_RTL_EXPR(RETURN, "return", "", 'x') | |
543 | ||
544 | /* Conditional trap. | |
545 | Operand 1 is the condition. | |
546 | Operand 2 is the trap code. | |
547 | For an unconditional trap, make the condition (const_int 1). */ | |
e0cd0770 | 548 | DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", 'x') |
1af1688b | 549 | |
52a11cbf RH |
550 | /* Placeholder for _Unwind_Resume before we know if a function call |
551 | or a branch is needed. Operand 1 is the exception region from | |
552 | which control is flowing. */ | |
553 | DEF_RTL_EXPR(RESX, "resx", "i", 'x') | |
554 | ||
1af1688b RK |
555 | /* ---------------------------------------------------------------------- |
556 | Primitive values for use in expressions. | |
557 | ---------------------------------------------------------------------- */ | |
558 | ||
559 | /* numeric integer constant */ | |
5f4f0e22 | 560 | DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o') |
1af1688b | 561 | |
aa0b4465 ZW |
562 | /* numeric floating point constant. |
563 | Operand 0 ('e') is the MEM that stores this constant in memory, or | |
564 | various other things (see comments at immed_double_const in | |
565 | varasm.c). | |
566 | Operand 1 ('0') is a chain of all CONST_DOUBLEs in use in the | |
567 | current function. | |
568 | Remaining operands hold the actual value. They are all 'w' and | |
569 | there may be from 1 to 4; see rtl.c. */ | |
570 | DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, 'o') | |
1af1688b RK |
571 | |
572 | /* String constant. Used only for attributes right now. */ | |
573 | DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o') | |
574 | ||
575 | /* This is used to encapsulate an expression whose value is constant | |
576 | (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be | |
577 | recognized as a constant operand rather than by arithmetic instructions. */ | |
1af1688b | 578 | |
bcb33994 | 579 | DEF_RTL_EXPR(CONST, "const", "e", 'o') |
c5c76735 | 580 | |
1af1688b RK |
581 | /* program counter. Ordinary jumps are represented |
582 | by a SET whose first operand is (PC). */ | |
583 | DEF_RTL_EXPR(PC, "pc", "", 'o') | |
584 | ||
eab5c70a BS |
585 | /* Used in the cselib routines to describe a value. */ |
586 | DEF_RTL_EXPR(VALUE, "value", "0", 'o') | |
587 | ||
41472af8 MM |
588 | /* A register. The "operand" is the register number, accessed with |
589 | the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER | |
590 | than a hardware register is being referred to. The second operand | |
08394eef BS |
591 | holds the original register number - this will be different for a |
592 | pseudo register that got turned into a hard register. | |
593 | This rtx needs to have as many (or more) fields as a MEM, since we | |
594 | can change REG rtx's into MEMs during reload. */ | |
41472af8 | 595 | DEF_RTL_EXPR(REG, "reg", "i0", 'o') |
1af1688b RK |
596 | |
597 | /* A scratch register. This represents a register used only within a | |
598 | single insn. It will be turned into a REG during register allocation | |
599 | or reload unless the constraint indicates that the register won't be | |
600 | needed, in which case it can remain a SCRATCH. This code is | |
601 | marked as having one operand so it can be turned into a REG. */ | |
602 | DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o') | |
603 | ||
604 | /* One word of a multi-word value. | |
605 | The first operand is the complete value; the second says which word. | |
606 | The WORDS_BIG_ENDIAN flag controls whether word number 0 | |
607 | (as numbered in a SUBREG) is the most or least significant word. | |
608 | ||
609 | This is also used to refer to a value in a different machine mode. | |
610 | For example, it can be used to refer to a SImode value as if it were | |
611 | Qimode, or vice versa. Then the word number is always 0. */ | |
612 | DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x') | |
613 | ||
614 | /* This one-argument rtx is used for move instructions | |
615 | that are guaranteed to alter only the low part of a destination. | |
616 | Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...)) | |
617 | has an unspecified effect on the high part of REG, | |
618 | but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...)) | |
619 | is guaranteed to alter only the bits of REG that are in HImode. | |
620 | ||
621 | The actual instruction used is probably the same in both cases, | |
622 | but the register constraints may be tighter when STRICT_LOW_PART | |
623 | is in use. */ | |
624 | ||
625 | DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x') | |
626 | ||
ea8fbf8a RS |
627 | /* (CONCAT a b) represents the virtual concatenation of a and b |
628 | to make a value that has as many bits as a and b put together. | |
629 | This is used for complex values. Normally it appears only | |
630 | in DECL_RTLs and during RTL generation, but not in the insn chain. */ | |
631 | DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o') | |
632 | ||
41472af8 MM |
633 | /* A memory location; operand is the address. Can be nested inside a |
634 | VOLATILE. The second operand is the alias set to which this MEM | |
3bdf5ad1 | 635 | belongs. We use `0' instead of `w' for this field so that the |
41472af8 MM |
636 | field need not be specified in machine descriptions. */ |
637 | DEF_RTL_EXPR(MEM, "mem", "e0", 'o') | |
1af1688b RK |
638 | |
639 | /* Reference to an assembler label in the code for this function. | |
640 | The operand is a CODE_LABEL found in the insn chain. | |
641 | The unprinted fields 1 and 2 are used in flow.c for the | |
642 | LABEL_NEXTREF and CONTAINING_INSN. */ | |
643 | DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o') | |
644 | ||
645 | /* Reference to a named label: the string that is the first operand, | |
646 | with `_' added implicitly in front. | |
647 | Exception: if the first character explicitly given is `*', | |
648 | to give it to the assembler, remove the `*' and do not add `_'. */ | |
649 | DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s", 'o') | |
650 | ||
651 | /* The condition code register is represented, in our imagination, | |
652 | as a register holding a value that can be compared to zero. | |
653 | In fact, the machine has already compared them and recorded the | |
654 | results; but instructions that look at the condition code | |
655 | pretend to be looking at the entire value and comparing it. */ | |
656 | DEF_RTL_EXPR(CC0, "cc0", "", 'o') | |
657 | ||
f754c4a1 JL |
658 | /* Reference to the address of a register. Removed by purge_addressof after |
659 | CSE has elided as many as possible. | |
660 | 1st operand: the register we may need the address of. | |
661 | 2nd operand: the original pseudo regno we were generated for. | |
662 | 3rd operand: the decl for the object in the register, for | |
663 | put_reg_in_stack. */ | |
664 | ||
8f985ec4 | 665 | DEF_RTL_EXPR(ADDRESSOF, "addressof", "eit", 'o') |
f754c4a1 | 666 | |
1af1688b RK |
667 | /* ===================================================================== |
668 | A QUEUED expression really points to a member of the queue of instructions | |
669 | to be output later for postincrement/postdecrement. | |
670 | QUEUED expressions never become part of instructions. | |
671 | When a QUEUED expression would be put into an instruction, | |
672 | instead either the incremented variable or a copy of its previous | |
673 | value is used. | |
674 | ||
675 | Operands are: | |
676 | 0. the variable to be incremented (a REG rtx). | |
677 | 1. the incrementing instruction, or 0 if it hasn't been output yet. | |
678 | 2. A REG rtx for a copy of the old value of the variable, or 0 if none yet. | |
679 | 3. the body to use for the incrementing instruction | |
680 | 4. the next QUEUED expression in the queue. | |
681 | ====================================================================== */ | |
682 | ||
683 | DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x') | |
684 | ||
685 | /* ---------------------------------------------------------------------- | |
686 | Expressions for operators in an rtl pattern | |
687 | ---------------------------------------------------------------------- */ | |
688 | ||
689 | /* if_then_else. This is used in representing ordinary | |
690 | conditional jump instructions. | |
691 | Operand: | |
692 | 0: condition | |
693 | 1: then expr | |
694 | 2: else expr */ | |
695 | DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3') | |
696 | ||
697 | /* General conditional. The first operand is a vector composed of pairs of | |
698 | expressions. The first element of each pair is evaluated, in turn. | |
699 | The value of the conditional is the second expression of the first pair | |
700 | whose first expression evaluates non-zero. If none of the expressions is | |
701 | true, the second operand will be used as the value of the conditional. | |
702 | ||
703 | This should be replaced with use of IF_THEN_ELSE. */ | |
704 | DEF_RTL_EXPR(COND, "cond", "Ee", 'x') | |
705 | ||
706 | /* Comparison, produces a condition code result. */ | |
707 | DEF_RTL_EXPR(COMPARE, "compare", "ee", '2') | |
708 | ||
709 | /* plus */ | |
710 | DEF_RTL_EXPR(PLUS, "plus", "ee", 'c') | |
711 | ||
712 | /* Operand 0 minus operand 1. */ | |
713 | DEF_RTL_EXPR(MINUS, "minus", "ee", '2') | |
714 | ||
715 | /* Minus operand 0. */ | |
716 | DEF_RTL_EXPR(NEG, "neg", "e", '1') | |
717 | ||
718 | DEF_RTL_EXPR(MULT, "mult", "ee", 'c') | |
719 | ||
720 | /* Operand 0 divided by operand 1. */ | |
721 | DEF_RTL_EXPR(DIV, "div", "ee", '2') | |
722 | /* Remainder of operand 0 divided by operand 1. */ | |
723 | DEF_RTL_EXPR(MOD, "mod", "ee", '2') | |
724 | ||
725 | /* Unsigned divide and remainder. */ | |
726 | DEF_RTL_EXPR(UDIV, "udiv", "ee", '2') | |
727 | DEF_RTL_EXPR(UMOD, "umod", "ee", '2') | |
728 | ||
729 | /* Bitwise operations. */ | |
730 | DEF_RTL_EXPR(AND, "and", "ee", 'c') | |
731 | ||
732 | DEF_RTL_EXPR(IOR, "ior", "ee", 'c') | |
733 | ||
734 | DEF_RTL_EXPR(XOR, "xor", "ee", 'c') | |
735 | ||
736 | DEF_RTL_EXPR(NOT, "not", "e", '1') | |
737 | ||
738 | /* Operand: | |
739 | 0: value to be shifted. | |
160d4f27 | 740 | 1: number of bits. */ |
4b7ee615 NS |
741 | DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2') /* shift left */ |
742 | DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2') /* rotate left */ | |
743 | DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2') /* arithmetic shift right */ | |
744 | DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2') /* logical shift right */ | |
745 | DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2') /* rotate right */ | |
1af1688b RK |
746 | |
747 | /* Minimum and maximum values of two operands. We need both signed and | |
748 | unsigned forms. (We cannot use MIN for SMIN because it conflicts | |
749 | with a macro of the same name.) */ | |
750 | ||
751 | DEF_RTL_EXPR(SMIN, "smin", "ee", 'c') | |
752 | DEF_RTL_EXPR(SMAX, "smax", "ee", 'c') | |
753 | DEF_RTL_EXPR(UMIN, "umin", "ee", 'c') | |
754 | DEF_RTL_EXPR(UMAX, "umax", "ee", 'c') | |
755 | ||
756 | /* These unary operations are used to represent incrementation | |
757 | and decrementation as they occur in memory addresses. | |
758 | The amount of increment or decrement are not represented | |
759 | because they can be understood from the machine-mode of the | |
760 | containing MEM. These operations exist in only two cases: | |
761 | 1. pushes onto the stack. | |
762 | 2. created automatically by the life_analysis pass in flow.c. */ | |
4b983fdc RH |
763 | DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'a') |
764 | DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'a') | |
765 | DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'a') | |
766 | DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'a') | |
1af1688b | 767 | |
b18cfc28 MH |
768 | /* These binary operations are used to represent generic address |
769 | side-effects in memory addresses, except for simple incrementation | |
770 | or decrementation which use the above operations. They are | |
4b983fdc RH |
771 | created automatically by the life_analysis pass in flow.c. |
772 | The first operand is a REG which is used as the address. | |
773 | The second operand is an expression that is assigned to the | |
774 | register, either before (PRE_MODIFY) or after (POST_MODIFY) | |
775 | evaluating the address. | |
776 | Currently, the compiler can only handle second operands of the | |
777 | form (plus (reg) (reg)) and (plus (reg) (const_int)), where | |
778 | the first operand of the PLUS has to be the same register as | |
779 | the first operand of the *_MODIFY. */ | |
780 | DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'a') | |
781 | DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'a') | |
b18cfc28 | 782 | |
1af1688b RK |
783 | /* Comparison operations. The ordered comparisons exist in two |
784 | flavors, signed and unsigned. */ | |
785 | DEF_RTL_EXPR(NE, "ne", "ee", '<') | |
786 | DEF_RTL_EXPR(EQ, "eq", "ee", '<') | |
787 | DEF_RTL_EXPR(GE, "ge", "ee", '<') | |
788 | DEF_RTL_EXPR(GT, "gt", "ee", '<') | |
789 | DEF_RTL_EXPR(LE, "le", "ee", '<') | |
790 | DEF_RTL_EXPR(LT, "lt", "ee", '<') | |
791 | DEF_RTL_EXPR(GEU, "geu", "ee", '<') | |
792 | DEF_RTL_EXPR(GTU, "gtu", "ee", '<') | |
793 | DEF_RTL_EXPR(LEU, "leu", "ee", '<') | |
794 | DEF_RTL_EXPR(LTU, "ltu", "ee", '<') | |
795 | ||
1eb8759b RH |
796 | /* Additional floating point unordered comparision flavors. */ |
797 | DEF_RTL_EXPR(UNORDERED, "unordered", "ee", '<') | |
798 | DEF_RTL_EXPR(ORDERED, "ordered", "ee", '<') | |
799 | ||
800 | /* These are equivalent to unordered or ... */ | |
1eb8759b RH |
801 | DEF_RTL_EXPR(UNEQ, "uneq", "ee", '<') |
802 | DEF_RTL_EXPR(UNGE, "unge", "ee", '<') | |
803 | DEF_RTL_EXPR(UNGT, "ungt", "ee", '<') | |
804 | DEF_RTL_EXPR(UNLE, "unle", "ee", '<') | |
805 | DEF_RTL_EXPR(UNLT, "unlt", "ee", '<') | |
806 | ||
7913f3d0 RH |
807 | /* This is an ordered NE, ie !UNEQ, ie false for NaN. */ |
808 | DEF_RTL_EXPR(LTGT, "ltgt", "ee", '<') | |
809 | ||
1af1688b RK |
810 | /* Represents the result of sign-extending the sole operand. |
811 | The machine modes of the operand and of the SIGN_EXTEND expression | |
812 | determine how much sign-extension is going on. */ | |
813 | DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1') | |
814 | ||
815 | /* Similar for zero-extension (such as unsigned short to int). */ | |
816 | DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1') | |
817 | ||
818 | /* Similar but here the operand has a wider mode. */ | |
819 | DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1') | |
820 | ||
821 | /* Similar for extending floating-point values (such as SFmode to DFmode). */ | |
822 | DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1') | |
823 | DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1') | |
824 | ||
825 | /* Conversion of fixed point operand to floating point value. */ | |
826 | DEF_RTL_EXPR(FLOAT, "float", "e", '1') | |
827 | ||
828 | /* With fixed-point machine mode: | |
829 | Conversion of floating point operand to fixed point value. | |
830 | Value is defined only when the operand's value is an integer. | |
831 | With floating-point machine mode (and operand with same mode): | |
832 | Operand is rounded toward zero to produce an integer value | |
833 | represented in floating point. */ | |
834 | DEF_RTL_EXPR(FIX, "fix", "e", '1') | |
835 | ||
836 | /* Conversion of unsigned fixed point operand to floating point value. */ | |
837 | DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1') | |
838 | ||
839 | /* With fixed-point machine mode: | |
840 | Conversion of floating point operand to *unsigned* fixed point value. | |
841 | Value is defined only when the operand's value is an integer. */ | |
842 | DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1') | |
843 | ||
844 | /* Absolute value */ | |
845 | DEF_RTL_EXPR(ABS, "abs", "e", '1') | |
846 | ||
847 | /* Square root */ | |
848 | DEF_RTL_EXPR(SQRT, "sqrt", "e", '1') | |
849 | ||
850 | /* Find first bit that is set. | |
851 | Value is 1 + number of trailing zeros in the arg., | |
852 | or 0 if arg is 0. */ | |
853 | DEF_RTL_EXPR(FFS, "ffs", "e", '1') | |
854 | ||
855 | /* Reference to a signed bit-field of specified size and position. | |
856 | Operand 0 is the memory unit (usually SImode or QImode) which | |
857 | contains the field's first bit. Operand 1 is the width, in bits. | |
858 | Operand 2 is the number of bits in the memory unit before the | |
859 | first bit of this field. | |
860 | If BITS_BIG_ENDIAN is defined, the first bit is the msb and | |
861 | operand 2 counts from the msb of the memory unit. | |
862 | Otherwise, the first bit is the lsb and operand 2 counts from | |
863 | the lsb of the memory unit. */ | |
864 | DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b') | |
865 | ||
866 | /* Similar for unsigned bit-field. */ | |
867 | DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b') | |
868 | ||
869 | /* For RISC machines. These save memory when splitting insns. */ | |
870 | ||
871 | /* HIGH are the high-order bits of a constant expression. */ | |
872 | DEF_RTL_EXPR(HIGH, "high", "e", 'o') | |
873 | ||
874 | /* LO_SUM is the sum of a register and the low-order bits | |
875 | of a constant expression. */ | |
876 | DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o') | |
877 | ||
b3b42a4d | 878 | /* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn. |
0dfa1860 MM |
879 | Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of |
880 | the registers that can be substituted within this range. Operand 3 is the | |
881 | number of calls in the range. Operand 4 is the number of insns in the | |
882 | range. Operand 5 is the unique range number for this range. Operand 6 is | |
883 | the basic block # of the start of the live range. Operand 7 is the basic | |
884 | block # of the end of the live range. Operand 8 is the loop depth. Operand | |
885 | 9 is a bitmap of the registers live at the start of the range. Operand 10 | |
886 | is a bitmap of the registers live at the end of the range. Operand 11 is | |
887 | marker number for the start of the range. Operand 12 is the marker number | |
888 | for the end of the range. */ | |
889 | DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", 'x') | |
890 | ||
891 | /* Registers that can be substituted within the range. Operand 0 is the | |
892 | original pseudo register number. Operand 1 will be filled in with the | |
893 | pseudo register the value is copied for the duration of the range. Operand | |
894 | 2 is the number of references within the range to the register. Operand 3 | |
895 | is the number of sets or clobbers of the register in the range. Operand 4 | |
896 | is the number of deaths the register has. Operand 5 is the copy flags that | |
897 | give the status of whether a copy is needed from the original register to | |
898 | the new register at the beginning of the range, or whether a copy from the | |
899 | new register back to the original at the end of the range. Operand 6 is the | |
900 | live length. Operand 7 is the number of calls that this register is live | |
901 | across. Operand 8 is the symbol node of the variable if the register is a | |
902 | user variable. Operand 9 is the block node that the variable is declared | |
903 | in if the register is a user variable. */ | |
904 | DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", 'x') | |
905 | ||
906 | /* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of | |
907 | the different ranges a variable is in where it is copied to a different | |
908 | pseudo register. Operand 1 is the block that the variable is declared in. | |
909 | Operand 2 is the number of distinct ranges. */ | |
910 | DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", 'x') | |
911 | ||
912 | /* Information about the registers that are live at the current point. Operand | |
913 | 0 is the live bitmap. Operand 1 is the original block number. */ | |
914 | DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", 'x') | |
915 | ||
bcb33994 BS |
916 | /* A unary `__builtin_constant_p' expression. These are only emitted |
917 | during RTL generation, and then only if optimize > 0. They are | |
918 | eliminated by the first CSE pass. */ | |
919 | DEF_RTL_EXPR(CONSTANT_P_RTX, "constant_p_rtx", "e", 'x') | |
920 | ||
09554da9 JL |
921 | /* A placeholder for a CALL_INSN which may be turned into a normal call, |
922 | a sibling (tail) call or tail recursion. | |
923 | ||
924 | Immediately after RTL generation, this placeholder will be replaced | |
925 | by the insns to perform the call, sibcall or tail recursion. | |
926 | ||
927 | This RTX has 4 operands. The first three are lists of instructions to | |
928 | perform the call as a normal call, sibling call and tail recursion | |
929 | respectively. The latter two lists may be NULL, the first may never | |
930 | be NULL. | |
931 | ||
932 | The last operand is the tail recursion CODE_LABEL, which may be NULL if no | |
933 | potential tail recursive calls were found. | |
934 | ||
935 | The tail recursion label is needed so that we can clear LABEL_PRESERVE_P | |
0a1c58a2 JL |
936 | after we select a call method. |
937 | ||
938 | This method of tail-call elimination is intended to be replaced by | |
939 | tree-based optimizations once front-end conversions are complete. */ | |
09554da9 JL |
940 | DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x') |
941 | ||
f9f27ee5 BS |
942 | /* Describes a merge operation between two vector values. |
943 | Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask | |
944 | that specifies where the parts of the result are taken from. Set bits | |
945 | indicate operand 0, clear bits indicate operand 1. The parts are defined | |
946 | by the mode of the vectors. */ | |
947 | DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", 'x') | |
948 | ||
949 | /* Describes an operation that selects parts of a vector. | |
950 | Operands 0 is the source vector, operand 1 is a PARALLEL that contains | |
951 | a CONST_INT for each of the subparts of the result vector, giving the | |
952 | number of the source subpart that should be stored into it. */ | |
953 | DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", 'x') | |
954 | ||
955 | /* Describes a vector concat operation. Operands 0 and 1 are the source | |
956 | vectors, the result is a vector that is as long as operands 0 and 1 | |
957 | combined and is the concatenation of the two source vectors. */ | |
958 | DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", 'x') | |
959 | ||
960 | /* Describes a vector constant. Each part of the PARALLEL that is operand 0 | |
961 | describes a constant for one of the subparts. */ | |
962 | DEF_RTL_EXPR(VEC_CONST, "vec_const", "e", 'x') | |
963 | ||
964 | /* Describes an operation that converts a small vector into a larger one by | |
965 | duplicating the input values. The output vector mode must have the same | |
966 | submodes as the input vector mode, and the number of output parts must be | |
967 | an integer multiple of the number of input parts. */ | |
968 | DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", 'x') | |
969 | ||
970 | /* Addition with signed saturation */ | |
971 | DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", 'c') | |
972 | ||
973 | /* Addition with unsigned saturation */ | |
974 | DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", 'c') | |
975 | ||
976 | /* Operand 0 minus operand 1, with signed saturation. */ | |
977 | DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", '2') | |
978 | ||
979 | /* Operand 0 minus operand 1, with unsigned saturation. */ | |
980 | DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", '2') | |
981 | ||
982 | /* Signed saturating truncate. */ | |
983 | DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", '1') | |
984 | ||
985 | /* Unsigned saturating truncate. */ | |
986 | DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", '1') | |
987 | ||
d9d4fb43 AS |
988 | /* The SSA phi operator. |
989 | ||
990 | The argument is a vector of 2N rtxes. Element 2N+1 is a CONST_INT | |
991 | containing the block number of the predecessor through which control | |
992 | has passed when the register at element 2N is used. | |
993 | ||
994 | Note that PHI may only appear at the beginning of a basic block. | |
995 | ||
996 | ??? There may be multiple PHI insns, but they are all evaluated | |
997 | in parallel. This probably ought to be changed to use a real | |
998 | PARALLEL, as that would be less confusing and more in the spirit | |
999 | of canonical RTL. It is, however, easier to manipulate this way. */ | |
1000 | DEF_RTL_EXPR(PHI, "phi", "E", 'x') | |
1001 | ||
1002 | ||
1af1688b RK |
1003 | /* |
1004 | Local variables: | |
1005 | mode:c | |
1af1688b RK |
1006 | End: |
1007 | */ |