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1af1688b RK |
1 | /* This file contains the definitions and documentation for the |
2 | Register Transfer Expressions (rtx's) that make up the | |
3 | Register Transfer Language (rtl) used in the Back End of the GNU compiler. | |
0a1c58a2 | 4 | Copyright (C) 1987, 88, 92, 94, 95, 97, 98, 1999, 2000 |
c5c76735 | 5 | Free Software Foundation, Inc. |
1af1688b | 6 | |
1322177d | 7 | This file is part of GCC. |
1af1688b | 8 | |
1322177d LB |
9 | GCC is free software; you can redistribute it and/or modify it under |
10 | the terms of the GNU General Public License as published by the Free | |
11 | Software Foundation; either version 2, or (at your option) any later | |
12 | version. | |
1af1688b | 13 | |
1322177d LB |
14 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
15 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | for more details. | |
1af1688b RK |
18 | |
19 | You should have received a copy of the GNU General Public License | |
1322177d LB |
20 | along with GCC; see the file COPYING. If not, write to the Free |
21 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
22 | 02111-1307, USA. */ | |
1af1688b RK |
23 | |
24 | ||
25 | /* Expression definitions and descriptions for all targets are in this file. | |
26 | Some will not be used for some targets. | |
27 | ||
28 | The fields in the cpp macro call "DEF_RTL_EXPR()" | |
29 | are used to create declarations in the C source of the compiler. | |
30 | ||
31 | The fields are: | |
32 | ||
33 | 1. The internal name of the rtx used in the C source. | |
34 | It is a tag in the enumeration "enum rtx_code" defined in "rtl.h". | |
35 | By convention these are in UPPER_CASE. | |
36 | ||
37 | 2. The name of the rtx in the external ASCII format read by | |
38 | read_rtx(), and printed by print_rtx(). | |
39 | These names are stored in rtx_name[]. | |
40 | By convention these are the internal (field 1) names in lower_case. | |
41 | ||
e1de1560 | 42 | 3. The print format, and type of each rtx->u.fld[] (field) in this rtx. |
1af1688b RK |
43 | These formats are stored in rtx_format[]. |
44 | The meaning of the formats is documented in front of this array in rtl.c | |
45 | ||
46 | 4. The class of the rtx. These are stored in rtx_class and are accessed | |
47 | via the GET_RTX_CLASS macro. They are defined as follows: | |
48 | ||
49 | "o" an rtx code that can be used to represent an object (e.g, REG, MEM) | |
50 | "<" an rtx code for a comparison (e.g, EQ, NE, LT) | |
51 | "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT) | |
52 | "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT) | |
53 | "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE) | |
54 | "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV) | |
55 | "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT) | |
56 | "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) | |
57 | "m" an rtx code for something that matches in insns (e.g, MATCH_DUP) | |
693e265f | 58 | "g" an rtx code for grouping insns together (e.g, GROUP_PARALLEL) |
4b983fdc | 59 | "a" an rtx code for autoincrement addressing modes (e.g. POST_DEC) |
1af1688b RK |
60 | "x" everything else |
61 | ||
62 | */ | |
63 | ||
64 | /* --------------------------------------------------------------------- | |
65 | Expressions (and "meta" expressions) used for structuring the | |
66 | rtl representation of a program. | |
67 | --------------------------------------------------------------------- */ | |
68 | ||
69 | /* an expression code name unknown to the reader */ | |
70 | DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x') | |
71 | ||
72 | /* (NIL) is used by rtl reader and printer to represent a null pointer. */ | |
73 | ||
74 | DEF_RTL_EXPR(NIL, "nil", "*", 'x') | |
75 | ||
04d8aa70 AM |
76 | |
77 | /* include a file */ | |
78 | ||
79 | DEF_RTL_EXPR(INCLUDE, "include", "s", 'x') | |
80 | ||
1af1688b RK |
81 | /* --------------------------------------------------------------------- |
82 | Expressions used in constructing lists. | |
83 | --------------------------------------------------------------------- */ | |
84 | ||
85 | /* a linked list of expressions */ | |
86 | DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x') | |
87 | ||
88 | /* a linked list of instructions. | |
89 | The insns are represented in print by their uids. */ | |
90 | DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x') | |
91 | ||
92 | /* ---------------------------------------------------------------------- | |
6dc42e49 | 93 | Expression types for machine descriptions. |
1af1688b RK |
94 | These do not appear in actual rtl code in the compiler. |
95 | ---------------------------------------------------------------------- */ | |
96 | ||
97 | /* Appears only in machine descriptions. | |
98 | Means use the function named by the second arg (the string) | |
99 | as a predicate; if matched, store the structure that was matched | |
100 | in the operand table at index specified by the first arg (the integer). | |
101 | If the second arg is the null string, the structure is just stored. | |
102 | ||
103 | A third string argument indicates to the register allocator restrictions | |
104 | on where the operand can be allocated. | |
105 | ||
106 | If the target needs no restriction on any instruction this field should | |
107 | be the null string. | |
108 | ||
109 | The string is prepended by: | |
110 | '=' to indicate the operand is only written to. | |
111 | '+' to indicate the operand is both read and written to. | |
112 | ||
956d6950 | 113 | Each character in the string represents an allocable class for an operand. |
1af1688b RK |
114 | 'g' indicates the operand can be any valid class. |
115 | 'i' indicates the operand can be immediate (in the instruction) data. | |
116 | 'r' indicates the operand can be in a register. | |
117 | 'm' indicates the operand can be in memory. | |
118 | 'o' a subset of the 'm' class. Those memory addressing modes that | |
119 | can be offset at compile time (have a constant added to them). | |
120 | ||
121 | Other characters indicate target dependent operand classes and | |
122 | are described in each target's machine description. | |
123 | ||
124 | For instructions with more than one operand, sets of classes can be | |
125 | separated by a comma to indicate the appropriate multi-operand constraints. | |
126 | There must be a 1 to 1 correspondence between these sets of classes in | |
127 | all operands for an instruction. | |
128 | */ | |
129 | DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm') | |
130 | ||
131 | /* Appears only in machine descriptions. | |
132 | Means match a SCRATCH or a register. When used to generate rtl, a | |
133 | SCRATCH is generated. As for MATCH_OPERAND, the mode specifies | |
134 | the desired mode and the first argument is the operand number. | |
135 | The second argument is the constraint. */ | |
136 | DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm') | |
137 | ||
138 | /* Appears only in machine descriptions. | |
139 | Means match only something equal to what is stored in the operand table | |
140 | at the index specified by the argument. */ | |
141 | DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm') | |
142 | ||
143 | /* Appears only in machine descriptions. | |
144 | Means apply a predicate, AND match recursively the operands of the rtx. | |
145 | Operand 0 is the operand-number, as in match_operand. | |
146 | Operand 1 is a predicate to apply (as a string, a function name). | |
147 | Operand 2 is a vector of expressions, each of which must match | |
148 | one subexpression of the rtx this construct is matching. */ | |
149 | DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm') | |
150 | ||
151 | /* Appears only in machine descriptions. | |
152 | Means to match a PARALLEL of arbitrary length. The predicate is applied | |
153 | to the PARALLEL and the initial expressions in the PARALLEL are matched. | |
154 | Operand 0 is the operand-number, as in match_operand. | |
155 | Operand 1 is a predicate to apply to the PARALLEL. | |
156 | Operand 2 is a vector of expressions, each of which must match the | |
157 | corresponding element in the PARALLEL. */ | |
158 | DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm') | |
159 | ||
160 | /* Appears only in machine descriptions. | |
161 | Means match only something equal to what is stored in the operand table | |
162 | at the index specified by the argument. For MATCH_OPERATOR. */ | |
163 | DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm') | |
164 | ||
ae3c61fa RK |
165 | /* Appears only in machine descriptions. |
166 | Means match only something equal to what is stored in the operand table | |
167 | at the index specified by the argument. For MATCH_PARALLEL. */ | |
168 | DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm') | |
169 | ||
693e265f MM |
170 | /* Appears only in machine descriptions. |
171 | Operand 0 is the operand number, as in match_operand. | |
172 | Operand 1 is the predicate to apply to the insn. */ | |
a669dbf8 | 173 | DEF_RTL_EXPR(MATCH_INSN, "match_insn", "is", 'm') |
693e265f | 174 | |
1af1688b RK |
175 | /* Appears only in machine descriptions. |
176 | Defines the pattern for one kind of instruction. | |
177 | Operand: | |
178 | 0: names this instruction. | |
179 | If the name is the null string, the instruction is in the | |
180 | machine description just to be recognized, and will never be emitted by | |
181 | the tree to rtl expander. | |
182 | 1: is the pattern. | |
183 | 2: is a string which is a C expression | |
184 | giving an additional condition for recognizing this pattern. | |
185 | A null string means no extra condition. | |
186 | 3: is the action to execute if this pattern is matched. | |
187 | If this assembler code template starts with a * then it is a fragment of | |
188 | C code to run to decide on a template to use. Otherwise, it is the | |
189 | template to use. | |
190 | 4: optionally, a vector of attributes for this insn. | |
191 | */ | |
1f3b37a3 | 192 | DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", 'x') |
1af1688b RK |
193 | |
194 | /* Definition of a peephole optimization. | |
195 | 1st operand: vector of insn patterns to match | |
196 | 2nd operand: C expression that must be true | |
197 | 3rd operand: template or C code to produce assembler output. | |
198 | 4: optionally, a vector of attributes for this insn. | |
199 | */ | |
1f3b37a3 | 200 | DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", 'x') |
1af1688b RK |
201 | |
202 | /* Definition of a split operation. | |
203 | 1st operand: insn pattern to match | |
204 | 2nd operand: C expression that must be true | |
205 | 3rd operand: vector of insn patterns to place into a SEQUENCE | |
206 | 4th operand: optionally, some C code to execute before generating the | |
207 | insns. This might, for example, create some RTX's and store them in | |
37bef197 TC |
208 | elements of `recog_data.operand' for use by the vector of |
209 | insn-patterns. | |
991b6592 | 210 | (`operands' is an alias here for `recog_data.operand'). */ |
1af1688b RK |
211 | DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x') |
212 | ||
c88c0d42 CP |
213 | /* Definition of an insn and associated split. |
214 | This is the concatenation, with a few modifications, of a define_insn | |
215 | and a define_split which share the same pattern. | |
216 | Operand: | |
217 | 0: names this instruction. | |
218 | If the name is the null string, the instruction is in the | |
219 | machine description just to be recognized, and will never be emitted by | |
220 | the tree to rtl expander. | |
221 | 1: is the pattern. | |
222 | 2: is a string which is a C expression | |
223 | giving an additional condition for recognizing this pattern. | |
224 | A null string means no extra condition. | |
225 | 3: is the action to execute if this pattern is matched. | |
226 | If this assembler code template starts with a * then it is a fragment of | |
227 | C code to run to decide on a template to use. Otherwise, it is the | |
228 | template to use. | |
229 | 4: C expression that must be true for split. This may start with "&&" | |
230 | in which case the split condition is the logical and of the insn | |
231 | condition and what follows the "&&" of this operand. | |
232 | 5: vector of insn patterns to place into a SEQUENCE | |
233 | 6: optionally, some C code to execute before generating the | |
234 | insns. This might, for example, create some RTX's and store them in | |
37bef197 TC |
235 | elements of `recog_data.operand' for use by the vector of |
236 | insn-patterns. | |
237 | (`operands' is an alias here for `recog_data.operand'). | |
c88c0d42 | 238 | 7: optionally, a vector of attributes for this insn. */ |
1f3b37a3 | 239 | DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", 'x') |
c88c0d42 | 240 | |
ede7cd44 RH |
241 | /* Definition of an RTL peephole operation. |
242 | Follows the same arguments as define_split. */ | |
243 | DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", 'x') | |
244 | ||
1af1688b RK |
245 | /* Definition of a combiner pattern. |
246 | Operands not defined yet. */ | |
247 | DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x') | |
248 | ||
249 | /* Define how to generate multiple insns for a standard insn name. | |
250 | 1st operand: the insn name. | |
251 | 2nd operand: vector of insn-patterns. | |
37bef197 | 252 | Use match_operand to substitute an element of `recog_data.operand'. |
1af1688b RK |
253 | 3rd operand: C expression that must be true for this to be available. |
254 | This may not test any operands. | |
255 | 4th operand: Extra C code to execute before generating the insns. | |
256 | This might, for example, create some RTX's and store them in | |
37bef197 TC |
257 | elements of `recog_data.operand' for use by the vector of |
258 | insn-patterns. | |
259 | (`operands' is an alias here for `recog_data.operand'). */ | |
1af1688b RK |
260 | DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x') |
261 | ||
262 | /* Define a requirement for delay slots. | |
263 | 1st operand: Condition involving insn attributes that, if true, | |
264 | indicates that the insn requires the number of delay slots | |
265 | shown. | |
266 | 2nd operand: Vector whose length is the three times the number of delay | |
267 | slots required. | |
268 | Each entry gives three conditions, each involving attributes. | |
269 | The first must be true for an insn to occupy that delay slot | |
270 | location. The second is true for all insns that can be | |
271 | annulled if the branch is true and the third is true for all | |
272 | insns that can be annulled if the branch is false. | |
273 | ||
274 | Multiple DEFINE_DELAYs may be present. They indicate differing | |
275 | requirements for delay slots. */ | |
276 | DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x') | |
277 | ||
278 | /* Define a set of insns that requires a function unit. This means that | |
279 | these insns produce their result after a delay and that there may be | |
280 | restrictions on the number of insns of this type that can be scheduled | |
281 | simultaneously. | |
282 | ||
283 | More than one DEFINE_FUNCTION_UNIT can be specified for a function unit. | |
284 | Each gives a set of operations and associated delays. The first three | |
285 | operands must be the same for each operation for the same function unit. | |
286 | ||
f6601f3a | 287 | All delays are specified in cycles. |
1af1688b RK |
288 | |
289 | 1st operand: Name of function unit (mostly for documentation) | |
290 | 2nd operand: Number of identical function units in CPU | |
291 | 3rd operand: Total number of simultaneous insns that can execute on this | |
292 | function unit; 0 if unlimited. | |
293 | 4th operand: Condition involving insn attribute, that, if true, specifies | |
294 | those insns that this expression applies to. | |
295 | 5th operand: Constant delay after which insn result will be | |
296 | available. | |
297 | 6th operand: Delay until next insn can be scheduled on the function unit | |
298 | executing this operation. The meaning depends on whether or | |
299 | not the next operand is supplied. | |
300 | 7th operand: If this operand is not specified, the 6th operand gives the | |
f6601f3a TW |
301 | number of cycles after the instruction matching the 4th |
302 | operand begins using the function unit until a subsequent | |
303 | insn can begin. A value of zero should be used for a | |
304 | unit with no issue constraints. If only one operation can | |
305 | be executed a time and the unit is busy for the entire time, | |
306 | the 3rd operand should be specified as 1, the 6th operand | |
956d6950 | 307 | should be specified as 0, and the 7th operand should not |
f6601f3a | 308 | be specified. |
1af1688b RK |
309 | |
310 | If this operand is specified, it is a list of attribute | |
311 | expressions. If an insn for which any of these expressions | |
312 | is true is currently executing on the function unit, the | |
f6601f3a TW |
313 | issue delay will be given by the 6th operand. Otherwise, |
314 | the insn can be immediately scheduled (subject to the limit | |
315 | on the number of simultaneous operations executing on the | |
1af1688b RK |
316 | unit.) */ |
317 | DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x') | |
318 | ||
319 | /* Define attribute computation for `asm' instructions. */ | |
320 | DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' ) | |
321 | ||
3262c1f5 RH |
322 | /* Definition of a conditional execution meta operation. Automatically |
323 | generates new instances of DEFINE_INSN, selected by having attribute | |
324 | "predicable" true. The new pattern will contain a COND_EXEC and the | |
325 | predicate at top-level. | |
326 | ||
327 | Operand: | |
328 | 0: The predicate pattern. The top-level form should match a | |
329 | relational operator. Operands should have only one alternative. | |
330 | 1: A C expression giving an additional condition for recognizing | |
331 | the generated pattern. | |
332 | 2: A template or C code to produce assembler output. */ | |
333 | DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", 'x') | |
334 | ||
1af1688b RK |
335 | /* SEQUENCE appears in the result of a `gen_...' function |
336 | for a DEFINE_EXPAND that wants to make several insns. | |
337 | Its elements are the bodies of the insns that should be made. | |
338 | `emit_insn' takes the SEQUENCE apart and makes separate insns. */ | |
339 | DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x') | |
340 | ||
f0f61682 | 341 | /* Refers to the address of its argument. This is only used in alias.c. */ |
1af1688b RK |
342 | DEF_RTL_EXPR(ADDRESS, "address", "e", 'm') |
343 | ||
fae15c93 VM |
344 | /* ---------------------------------------------------------------------- |
345 | Constructions for CPU pipeline description described by NDFAs. | |
346 | These do not appear in actual rtl code in the compiler. | |
347 | ---------------------------------------------------------------------- */ | |
348 | ||
349 | /* (define_cpu_unit string [string]) describes cpu functional | |
350 | units (separated by comma). | |
351 | ||
352 | 1st operand: Names of cpu functional units. | |
353 | 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON). | |
354 | ||
355 | All define_reservations, define_cpu_units, and | |
356 | define_query_cpu_units should have unique names which may not be | |
357 | "nothing". */ | |
358 | DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", 'x') | |
359 | ||
360 | /* (define_query_cpu_unit string [string]) describes cpu functional | |
30028c85 VM |
361 | units analogously to define_cpu_unit. The reservation of such |
362 | units can be queried for automaton state. */ | |
fae15c93 VM |
363 | DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", 'x') |
364 | ||
365 | /* (exclusion_set string string) means that each CPU functional unit | |
366 | in the first string can not be reserved simultaneously with any | |
367 | unit whose name is in the second string and vise versa. CPU units | |
368 | in the string are separated by commas. For example, it is useful | |
369 | for description CPU with fully pipelined floating point functional | |
370 | unit which can execute simultaneously only single floating point | |
371 | insns or only double floating point insns. All CPU functional | |
30028c85 | 372 | units in a set should belong to the same automaton. */ |
fae15c93 VM |
373 | DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", 'x') |
374 | ||
375 | /* (presence_set string string) means that each CPU functional unit in | |
30028c85 VM |
376 | the first string can not be reserved unless at least one of pattern |
377 | of units whose names are in the second string is reserved. This is | |
378 | an asymmetric relation. CPU units or unit patterns in the strings | |
379 | are separated by commas. Pattern is one unit name or unit names | |
380 | separated by white-spaces. | |
381 | ||
382 | For example, it is useful for description that slot1 is reserved | |
383 | after slot0 reservation for a VLIW processor. We could describe it | |
384 | by the following construction | |
385 | ||
386 | (presence_set "slot1" "slot0") | |
387 | ||
388 | Or slot1 is reserved only after slot0 and unit b0 reservation. In | |
389 | this case we could write | |
390 | ||
391 | (presence_set "slot1" "slot0 b0") | |
392 | ||
393 | All CPU functional units in a set should belong to the same | |
394 | automaton. */ | |
fae15c93 VM |
395 | DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", 'x') |
396 | ||
30028c85 VM |
397 | /* (final_presence_set string string) is analogous to `presence_set'. |
398 | The difference between them is when checking is done. When an | |
399 | instruction is issued in given automaton state reflecting all | |
400 | current and planned unit reservations, the automaton state is | |
401 | changed. The first state is a source state, the second one is a | |
402 | result state. Checking for `presence_set' is done on the source | |
403 | state reservation, checking for `final_presence_set' is done on the | |
404 | result reservation. This construction is useful to describe a | |
405 | reservation which is actually two subsequent reservations. For | |
406 | example, if we use | |
407 | ||
408 | (presence_set "slot1" "slot0") | |
409 | ||
410 | the following insn will be never issued (because slot1 requires | |
411 | slot0 which is absent in the source state). | |
412 | ||
413 | (define_reservation "insn_and_nop" "slot0 + slot1") | |
414 | ||
415 | but it can be issued if we use analogous `final_presence_set'. */ | |
416 | DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", 'x') | |
417 | ||
fae15c93 | 418 | /* (absence_set string string) means that each CPU functional unit in |
30028c85 VM |
419 | the first string can be reserved only if each pattern of units |
420 | whose names are in the second string is not reserved. This is an | |
421 | asymmetric relation (actually exclusion set is analogous to this | |
422 | one but it is symmetric). CPU units or unit patterns in the string | |
423 | are separated by commas. Pattern is one unit name or unit names | |
424 | separated by white-spaces. | |
425 | ||
426 | For example, it is useful for description that slot0 can not be | |
427 | reserved after slot1 or slot2 reservation for a VLIW processor. We | |
428 | could describe it by the following construction | |
429 | ||
430 | (absence_set "slot2" "slot0, slot1") | |
431 | ||
432 | Or slot2 can not be reserved if slot0 and unit b0 are reserved or | |
433 | slot1 and unit b1 are reserved . In this case we could write | |
434 | ||
435 | (absence_set "slot2" "slot0 b0, slot1 b1") | |
436 | ||
437 | All CPU functional units in a set should to belong the same | |
438 | automaton. */ | |
fae15c93 VM |
439 | DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", 'x') |
440 | ||
30028c85 VM |
441 | /* (final_absence_set string string) is analogous to `absence_set' but |
442 | checking is done on the result (state) reservation. See comments | |
443 | for `final_presence_set'. */ | |
444 | DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", 'x') | |
445 | ||
fae15c93 VM |
446 | /* (define_bypass number out_insn_names in_insn_names) names bypass |
447 | with given latency (the first number) from insns given by the first | |
448 | string (see define_insn_reservation) into insns given by the second | |
449 | string. Insn names in the strings are separated by commas. The | |
450 | third operand is optional name of function which is additional | |
451 | guard for the bypass. The function will get the two insns as | |
452 | parameters. If the function returns zero the bypass will be | |
453 | ignored for this case. Additional guard is necessary to recognize | |
454 | complicated bypasses, e.g. when consumer is load address. */ | |
455 | DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", 'x') | |
456 | ||
457 | /* (define_automaton string) describes names of automata generated and | |
458 | used for pipeline hazards recognition. The names are separated by | |
459 | comma. Actually it is possibly to generate the single automaton | |
460 | but unfortunately it can be very large. If we use more one | |
461 | automata, the summary size of the automata usually is less than the | |
462 | single one. The automaton name is used in define_cpu_unit and | |
463 | define_query_cpu_unit. All automata should have unique names. */ | |
464 | DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", 'x') | |
465 | ||
466 | /* (automata_option string) describes option for generation of | |
467 | automata. Currently there are the following options: | |
468 | ||
469 | o "no-minimization" which makes no minimization of automata. This | |
30028c85 VM |
470 | is only worth to do when we are debugging the description and |
471 | need to look more accurately at reservations of states. | |
fae15c93 | 472 | |
e3c8eb86 VM |
473 | o "time" which means printing additional time statistics about |
474 | generation of automata. | |
475 | ||
476 | o "v" which means generation of file describing the result | |
477 | automata. The file has suffix `.dfa' and can be used for the | |
478 | description verification and debugging. | |
479 | ||
480 | o "w" which means generation of warning instead of error for | |
481 | non-critical errors. | |
fae15c93 VM |
482 | |
483 | o "ndfa" which makes nondeterministic finite state automata. */ | |
484 | DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", 'x') | |
485 | ||
486 | /* (define_reservation string string) names reservation (the first | |
487 | string) of cpu functional units (the 2nd string). Sometimes unit | |
488 | reservations for different insns contain common parts. In such | |
489 | case, you can describe common part and use its name (the 1st | |
490 | parameter) in regular expression in define_insn_reservation. All | |
491 | define_reservations, define_cpu_units, and define_query_cpu_units | |
492 | should have unique names which may not be "nothing". */ | |
493 | DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", 'x') | |
494 | ||
495 | /* (define_insn_reservation name default_latency condition regexpr) | |
496 | describes reservation of cpu functional units (the 3nd operand) for | |
497 | instruction which is selected by the condition (the 2nd parameter). | |
498 | The first parameter is used for output of debugging information. | |
499 | The reservations are described by a regular expression according | |
500 | the following syntax: | |
501 | ||
502 | regexp = regexp "," oneof | |
503 | | oneof | |
504 | ||
505 | oneof = oneof "|" allof | |
506 | | allof | |
507 | ||
508 | allof = allof "+" repeat | |
509 | | repeat | |
510 | ||
511 | repeat = element "*" number | |
512 | | element | |
513 | ||
514 | element = cpu_function_unit_name | |
515 | | reservation_name | |
516 | | result_name | |
517 | | "nothing" | |
518 | | "(" regexp ")" | |
519 | ||
520 | 1. "," is used for describing start of the next cycle in | |
521 | reservation. | |
522 | ||
523 | 2. "|" is used for describing the reservation described by the | |
524 | first regular expression *or* the reservation described by the | |
525 | second regular expression *or* etc. | |
526 | ||
527 | 3. "+" is used for describing the reservation described by the | |
528 | first regular expression *and* the reservation described by the | |
529 | second regular expression *and* etc. | |
530 | ||
4d6922ee | 531 | 4. "*" is used for convenience and simply means sequence in |
fae15c93 VM |
532 | which the regular expression are repeated NUMBER times with |
533 | cycle advancing (see ","). | |
534 | ||
535 | 5. cpu functional unit name which means its reservation. | |
536 | ||
537 | 6. reservation name -- see define_reservation. | |
538 | ||
539 | 7. string "nothing" means no units reservation. */ | |
540 | ||
541 | DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", 'x') | |
542 | ||
1af1688b RK |
543 | /* ---------------------------------------------------------------------- |
544 | Expressions used for insn attributes. These also do not appear in | |
545 | actual rtl code in the compiler. | |
546 | ---------------------------------------------------------------------- */ | |
547 | ||
548 | /* Definition of an insn attribute. | |
549 | 1st operand: name of the attribute | |
550 | 2nd operand: comma-separated list of possible attribute values | |
991b6592 | 551 | 3rd operand: expression for the default value of the attribute. */ |
1af1688b RK |
552 | DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x') |
553 | ||
991b6592 | 554 | /* Marker for the name of an attribute. */ |
1af1688b RK |
555 | DEF_RTL_EXPR(ATTR, "attr", "s", 'x') |
556 | ||
557 | /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and | |
558 | in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that | |
559 | pattern. | |
560 | ||
561 | (set_attr "name" "value") is equivalent to | |
562 | (set (attr "name") (const_string "value")) */ | |
563 | DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x') | |
564 | ||
565 | /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to | |
566 | specify that attribute values are to be assigned according to the | |
567 | alternative matched. | |
568 | ||
569 | The following three expressions are equivalent: | |
570 | ||
571 | (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1") | |
572 | (eq_attrq "alternative" "2") (const_string "a2")] | |
573 | (const_string "a3"))) | |
574 | (set_attr_alternative "att" [(const_string "a1") (const_string "a2") | |
575 | (const_string "a3")]) | |
576 | (set_attr "att" "a1,a2,a3") | |
577 | */ | |
578 | DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x') | |
579 | ||
580 | /* A conditional expression true if the value of the specified attribute of | |
581 | the current insn equals the specified value. The first operand is the | |
582 | attribute name and the second is the comparison value. */ | |
583 | DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x') | |
584 | ||
417a6986 JL |
585 | /* A conditional expression which is true if the specified flag is |
586 | true for the insn being scheduled in reorg. | |
587 | ||
588 | genattr.c defines the following flags which can be tested by | |
589 | (attr_flag "foo") expressions in eligible_for_delay. | |
590 | ||
591 | forward, backward, very_likely, likely, very_unlikely, and unlikely. */ | |
592 | ||
593 | DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", 'x') | |
594 | ||
1af1688b RK |
595 | /* ---------------------------------------------------------------------- |
596 | Expression types used for things in the instruction chain. | |
597 | ||
598 | All formats must start with "iuu" to handle the chain. | |
599 | Each insn expression holds an rtl instruction and its semantics | |
600 | during back-end processing. | |
e1de1560 | 601 | See macros's in "rtl.h" for the meaning of each rtx->u.fld[]. |
1af1688b RK |
602 | |
603 | ---------------------------------------------------------------------- */ | |
604 | ||
605 | /* An instruction that cannot jump. */ | |
0435312e | 606 | DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", 'i') |
1af1688b RK |
607 | |
608 | /* An instruction that can possibly jump. | |
e1de1560 | 609 | Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ |
0435312e | 610 | DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", 'i') |
1af1688b RK |
611 | |
612 | /* An instruction that can possibly call a subroutine | |
613 | but which will not change which instruction comes next | |
614 | in the current function. | |
e1de1560 RS |
615 | Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE. |
616 | All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ | |
0435312e | 617 | DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", 'i') |
1af1688b RK |
618 | |
619 | /* A marker that indicates that control will not flow through. */ | |
d1f1cc6a | 620 | DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", 'x') |
1af1688b RK |
621 | |
622 | /* Holds a label that is followed by instructions. | |
623 | Operand: | |
d1f1cc6a RH |
624 | 5: is used in jump.c for the use-count of the label. |
625 | 6: is used in flow.c to point to the chain of label_ref's to this label. | |
626 | 7: is a number that is unique in the entire compilation. | |
627 | 8: is the user-given name of the label, if any. */ | |
0dc36574 ZW |
628 | DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", 'x') |
629 | ||
1af1688b | 630 | /* Say where in the code a source line starts, for symbol table's sake. |
f5540cd4 | 631 | Operand: |
d1f1cc6a RH |
632 | 5: filename, if line number > 0, note-specific data otherwise. |
633 | 6: line number if > 0, enum note_insn otherwise. | |
80fa0b4c DN |
634 | 7: unique number if line number == note_insn_deleted_label. */ |
635 | DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", 'x') | |
1af1688b | 636 | |
1af1688b RK |
637 | /* ---------------------------------------------------------------------- |
638 | Top level constituents of INSN, JUMP_INSN and CALL_INSN. | |
639 | ---------------------------------------------------------------------- */ | |
640 | ||
6b29b0e2 JW |
641 | /* Conditionally execute code. |
642 | Operand 0 is the condition that if true, the code is executed. | |
643 | Operand 1 is the code to be executed (typically a SET). | |
644 | ||
645 | Semantics are that there are no side effects if the condition | |
646 | is false. This pattern is created automatically by the if_convert | |
647 | pass run after reload or by target-specific splitters. */ | |
648 | DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", 'x') | |
649 | ||
650 | /* Several operations to be done in parallel (perhaps under COND_EXEC). */ | |
1af1688b RK |
651 | DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x') |
652 | ||
653 | /* A string that is passed through to the assembler as input. | |
654 | One can obviously pass comments through by using the | |
655 | assembler comment syntax. | |
656 | These occur in an insn all by themselves as the PATTERN. | |
657 | They also appear inside an ASM_OPERANDS | |
658 | as a convenient way to hold a string. */ | |
659 | DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x') | |
660 | ||
661 | /* An assembler instruction with operands. | |
662 | 1st operand is the instruction template. | |
663 | 2nd operand is the constraint for the output. | |
664 | 3rd operand is the number of the output this expression refers to. | |
665 | When an insn stores more than one value, a separate ASM_OPERANDS | |
666 | is made for each output; this integer distinguishes them. | |
667 | 4th is a vector of values of input operands. | |
668 | 5th is a vector of modes and constraints for the input operands. | |
669 | Each element is an ASM_INPUT containing a constraint string | |
670 | and whose mode indicates the mode of the input operand. | |
671 | 6th is the name of the containing source file. | |
672 | 7th is the source line number. */ | |
673 | DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x') | |
674 | ||
1fcea2b0 RK |
675 | /* A machine-specific operation. |
676 | 1st operand is a vector of operands being used by the operation so that | |
677 | any needed reloads can be done. | |
678 | 2nd operand is a unique value saying which of a number of machine-specific | |
679 | operations is to be performed. | |
680 | (Note that the vector must be the first operand because of the way that | |
681 | genrecog.c record positions within an insn.) | |
682 | This can occur all by itself in a PATTERN, as a component of a PARALLEL, | |
683 | or inside an expression. */ | |
684 | DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", 'x') | |
685 | ||
6dc42e49 | 686 | /* Similar, but a volatile operation and one which may trap. */ |
1fcea2b0 RK |
687 | DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", 'x') |
688 | ||
1af1688b RK |
689 | /* Vector of addresses, stored as full words. */ |
690 | /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */ | |
691 | DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x') | |
692 | ||
693 | /* Vector of address differences X0 - BASE, X1 - BASE, ... | |
694 | First operand is BASE; the vector contains the X's. | |
695 | The machine mode of this rtx says how much space to leave | |
33f7f353 JR |
696 | for each difference and is adjusted by branch shortening if |
697 | CASE_VECTOR_SHORTEN_MODE is defined. | |
698 | The third and fourth operands store the target labels with the | |
699 | minimum and maximum addresses respectively. | |
700 | The fifth operand stores flags for use by branch shortening. | |
701 | Set at the start of shorten_branches: | |
702 | min_align: the minimum alignment for any of the target labels. | |
703 | base_after_vec: true iff BASE is after the ADDR_DIFF_VEC. | |
704 | min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC. | |
705 | max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC. | |
706 | min_after_base: true iff minimum address target label is after BASE. | |
707 | max_after_base: true iff maximum address target label is after BASE. | |
708 | Set by the actual branch shortening process: | |
709 | offset_unsigned: true iff offsets have to be treated as unsigned. | |
710 | scale: scaling that is necessary to make offsets fit into the mode. | |
711 | ||
712 | The third, fourth and fifth operands are only valid when | |
713 | CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing | |
714 | compilations. */ | |
715 | ||
8f985ec4 | 716 | DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", 'x') |
1af1688b | 717 | |
21b8482a JJ |
718 | /* Memory prefetch, with attributes supported on some targets. |
719 | Operand 1 is the address of the memory to fetch. | |
720 | Operand 2 is 1 for a write access, 0 otherwise. | |
721 | Operand 3 is the level of temporal locality; 0 means there is no | |
722 | temporal locality and 1, 2, and 3 are for increasing levels of temporal | |
723 | locality. | |
724 | ||
725 | The attributes specified by operands 2 and 3 are ignored for targets | |
726 | whose prefetch instructions do not support them. */ | |
727 | DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", 'x') | |
728 | ||
1af1688b RK |
729 | /* ---------------------------------------------------------------------- |
730 | At the top level of an instruction (perhaps under PARALLEL). | |
731 | ---------------------------------------------------------------------- */ | |
732 | ||
733 | /* Assignment. | |
734 | Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to. | |
735 | Operand 2 is the value stored there. | |
736 | ALL assignment must use SET. | |
737 | Instructions that do multiple assignments must use multiple SET, | |
738 | under PARALLEL. */ | |
739 | DEF_RTL_EXPR(SET, "set", "ee", 'x') | |
740 | ||
741 | /* Indicate something is used in a way that we don't want to explain. | |
742 | For example, subroutine calls will use the register | |
743 | in which the static chain is passed. */ | |
744 | DEF_RTL_EXPR(USE, "use", "e", 'x') | |
745 | ||
746 | /* Indicate something is clobbered in a way that we don't want to explain. | |
747 | For example, subroutine calls will clobber some physical registers | |
748 | (the ones that are by convention not saved). */ | |
749 | DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x') | |
750 | ||
751 | /* Call a subroutine. | |
752 | Operand 1 is the address to call. | |
753 | Operand 2 is the number of arguments. */ | |
754 | ||
755 | DEF_RTL_EXPR(CALL, "call", "ee", 'x') | |
756 | ||
757 | /* Return from a subroutine. */ | |
758 | ||
759 | DEF_RTL_EXPR(RETURN, "return", "", 'x') | |
760 | ||
761 | /* Conditional trap. | |
762 | Operand 1 is the condition. | |
763 | Operand 2 is the trap code. | |
764 | For an unconditional trap, make the condition (const_int 1). */ | |
e0cd0770 | 765 | DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", 'x') |
1af1688b | 766 | |
52a11cbf RH |
767 | /* Placeholder for _Unwind_Resume before we know if a function call |
768 | or a branch is needed. Operand 1 is the exception region from | |
769 | which control is flowing. */ | |
770 | DEF_RTL_EXPR(RESX, "resx", "i", 'x') | |
771 | ||
1af1688b RK |
772 | /* ---------------------------------------------------------------------- |
773 | Primitive values for use in expressions. | |
774 | ---------------------------------------------------------------------- */ | |
775 | ||
776 | /* numeric integer constant */ | |
5f4f0e22 | 777 | DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o') |
1af1688b | 778 | |
aa0b4465 | 779 | /* numeric floating point constant. |
43194145 JZ |
780 | Operands hold the value. They are all 'w' and there may be from 2 to 6; |
781 | see real.h. */ | |
aa0b4465 | 782 | DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, 'o') |
1af1688b | 783 | |
69ef87e2 AH |
784 | /* Describes a vector constant. */ |
785 | DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", 'x') | |
786 | ||
1af1688b RK |
787 | /* String constant. Used only for attributes right now. */ |
788 | DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o') | |
789 | ||
790 | /* This is used to encapsulate an expression whose value is constant | |
791 | (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be | |
792 | recognized as a constant operand rather than by arithmetic instructions. */ | |
1af1688b | 793 | |
bcb33994 | 794 | DEF_RTL_EXPR(CONST, "const", "e", 'o') |
c5c76735 | 795 | |
1af1688b RK |
796 | /* program counter. Ordinary jumps are represented |
797 | by a SET whose first operand is (PC). */ | |
798 | DEF_RTL_EXPR(PC, "pc", "", 'o') | |
799 | ||
eab5c70a BS |
800 | /* Used in the cselib routines to describe a value. */ |
801 | DEF_RTL_EXPR(VALUE, "value", "0", 'o') | |
802 | ||
41472af8 MM |
803 | /* A register. The "operand" is the register number, accessed with |
804 | the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER | |
805 | than a hardware register is being referred to. The second operand | |
08394eef BS |
806 | holds the original register number - this will be different for a |
807 | pseudo register that got turned into a hard register. | |
808 | This rtx needs to have as many (or more) fields as a MEM, since we | |
809 | can change REG rtx's into MEMs during reload. */ | |
a560d4d4 | 810 | DEF_RTL_EXPR(REG, "reg", "i00", 'o') |
1af1688b RK |
811 | |
812 | /* A scratch register. This represents a register used only within a | |
813 | single insn. It will be turned into a REG during register allocation | |
814 | or reload unless the constraint indicates that the register won't be | |
815 | needed, in which case it can remain a SCRATCH. This code is | |
816 | marked as having one operand so it can be turned into a REG. */ | |
817 | DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o') | |
818 | ||
819 | /* One word of a multi-word value. | |
820 | The first operand is the complete value; the second says which word. | |
821 | The WORDS_BIG_ENDIAN flag controls whether word number 0 | |
822 | (as numbered in a SUBREG) is the most or least significant word. | |
823 | ||
824 | This is also used to refer to a value in a different machine mode. | |
825 | For example, it can be used to refer to a SImode value as if it were | |
826 | Qimode, or vice versa. Then the word number is always 0. */ | |
827 | DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x') | |
828 | ||
829 | /* This one-argument rtx is used for move instructions | |
830 | that are guaranteed to alter only the low part of a destination. | |
831 | Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...)) | |
832 | has an unspecified effect on the high part of REG, | |
833 | but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...)) | |
834 | is guaranteed to alter only the bits of REG that are in HImode. | |
835 | ||
836 | The actual instruction used is probably the same in both cases, | |
837 | but the register constraints may be tighter when STRICT_LOW_PART | |
838 | is in use. */ | |
839 | ||
840 | DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x') | |
841 | ||
ea8fbf8a RS |
842 | /* (CONCAT a b) represents the virtual concatenation of a and b |
843 | to make a value that has as many bits as a and b put together. | |
844 | This is used for complex values. Normally it appears only | |
845 | in DECL_RTLs and during RTL generation, but not in the insn chain. */ | |
846 | DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o') | |
847 | ||
a0fd557a RK |
848 | /* A memory location; operand is the address. The second operand is the |
849 | alias set to which this MEM belongs. We use `0' instead of `w' for this | |
850 | field so that the field need not be specified in machine descriptions. */ | |
41472af8 | 851 | DEF_RTL_EXPR(MEM, "mem", "e0", 'o') |
1af1688b RK |
852 | |
853 | /* Reference to an assembler label in the code for this function. | |
854 | The operand is a CODE_LABEL found in the insn chain. | |
855 | The unprinted fields 1 and 2 are used in flow.c for the | |
856 | LABEL_NEXTREF and CONTAINING_INSN. */ | |
857 | DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o') | |
858 | ||
52859c77 RH |
859 | /* Reference to a named label: |
860 | Operand 0: label name | |
861 | Operand 1: flags (see SYMBOL_FLAG_* in rtl.h) | |
32a61907 ZW |
862 | Operand 2: tree from which this symbol is derived, or null. |
863 | This is either a DECL node, or some kind of constant. */ | |
52859c77 | 864 | DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", 'o') |
1af1688b RK |
865 | |
866 | /* The condition code register is represented, in our imagination, | |
867 | as a register holding a value that can be compared to zero. | |
868 | In fact, the machine has already compared them and recorded the | |
869 | results; but instructions that look at the condition code | |
870 | pretend to be looking at the entire value and comparing it. */ | |
871 | DEF_RTL_EXPR(CC0, "cc0", "", 'o') | |
872 | ||
f754c4a1 JL |
873 | /* Reference to the address of a register. Removed by purge_addressof after |
874 | CSE has elided as many as possible. | |
875 | 1st operand: the register we may need the address of. | |
876 | 2nd operand: the original pseudo regno we were generated for. | |
877 | 3rd operand: the decl for the object in the register, for | |
878 | put_reg_in_stack. */ | |
879 | ||
8f985ec4 | 880 | DEF_RTL_EXPR(ADDRESSOF, "addressof", "eit", 'o') |
f754c4a1 | 881 | |
1af1688b RK |
882 | /* ===================================================================== |
883 | A QUEUED expression really points to a member of the queue of instructions | |
884 | to be output later for postincrement/postdecrement. | |
885 | QUEUED expressions never become part of instructions. | |
886 | When a QUEUED expression would be put into an instruction, | |
887 | instead either the incremented variable or a copy of its previous | |
888 | value is used. | |
889 | ||
890 | Operands are: | |
891 | 0. the variable to be incremented (a REG rtx). | |
892 | 1. the incrementing instruction, or 0 if it hasn't been output yet. | |
893 | 2. A REG rtx for a copy of the old value of the variable, or 0 if none yet. | |
894 | 3. the body to use for the incrementing instruction | |
895 | 4. the next QUEUED expression in the queue. | |
896 | ====================================================================== */ | |
897 | ||
898 | DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x') | |
899 | ||
900 | /* ---------------------------------------------------------------------- | |
901 | Expressions for operators in an rtl pattern | |
902 | ---------------------------------------------------------------------- */ | |
903 | ||
904 | /* if_then_else. This is used in representing ordinary | |
905 | conditional jump instructions. | |
906 | Operand: | |
907 | 0: condition | |
908 | 1: then expr | |
909 | 2: else expr */ | |
910 | DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3') | |
911 | ||
912 | /* General conditional. The first operand is a vector composed of pairs of | |
913 | expressions. The first element of each pair is evaluated, in turn. | |
914 | The value of the conditional is the second expression of the first pair | |
0e9e1e0a | 915 | whose first expression evaluates nonzero. If none of the expressions is |
1af1688b RK |
916 | true, the second operand will be used as the value of the conditional. |
917 | ||
918 | This should be replaced with use of IF_THEN_ELSE. */ | |
919 | DEF_RTL_EXPR(COND, "cond", "Ee", 'x') | |
920 | ||
921 | /* Comparison, produces a condition code result. */ | |
922 | DEF_RTL_EXPR(COMPARE, "compare", "ee", '2') | |
923 | ||
924 | /* plus */ | |
925 | DEF_RTL_EXPR(PLUS, "plus", "ee", 'c') | |
926 | ||
927 | /* Operand 0 minus operand 1. */ | |
928 | DEF_RTL_EXPR(MINUS, "minus", "ee", '2') | |
929 | ||
930 | /* Minus operand 0. */ | |
931 | DEF_RTL_EXPR(NEG, "neg", "e", '1') | |
932 | ||
933 | DEF_RTL_EXPR(MULT, "mult", "ee", 'c') | |
934 | ||
935 | /* Operand 0 divided by operand 1. */ | |
936 | DEF_RTL_EXPR(DIV, "div", "ee", '2') | |
937 | /* Remainder of operand 0 divided by operand 1. */ | |
938 | DEF_RTL_EXPR(MOD, "mod", "ee", '2') | |
939 | ||
940 | /* Unsigned divide and remainder. */ | |
941 | DEF_RTL_EXPR(UDIV, "udiv", "ee", '2') | |
942 | DEF_RTL_EXPR(UMOD, "umod", "ee", '2') | |
943 | ||
944 | /* Bitwise operations. */ | |
945 | DEF_RTL_EXPR(AND, "and", "ee", 'c') | |
946 | ||
947 | DEF_RTL_EXPR(IOR, "ior", "ee", 'c') | |
948 | ||
949 | DEF_RTL_EXPR(XOR, "xor", "ee", 'c') | |
950 | ||
951 | DEF_RTL_EXPR(NOT, "not", "e", '1') | |
952 | ||
953 | /* Operand: | |
954 | 0: value to be shifted. | |
160d4f27 | 955 | 1: number of bits. */ |
4b7ee615 NS |
956 | DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2') /* shift left */ |
957 | DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2') /* rotate left */ | |
958 | DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2') /* arithmetic shift right */ | |
959 | DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2') /* logical shift right */ | |
960 | DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2') /* rotate right */ | |
1af1688b RK |
961 | |
962 | /* Minimum and maximum values of two operands. We need both signed and | |
963 | unsigned forms. (We cannot use MIN for SMIN because it conflicts | |
964 | with a macro of the same name.) */ | |
965 | ||
966 | DEF_RTL_EXPR(SMIN, "smin", "ee", 'c') | |
967 | DEF_RTL_EXPR(SMAX, "smax", "ee", 'c') | |
968 | DEF_RTL_EXPR(UMIN, "umin", "ee", 'c') | |
969 | DEF_RTL_EXPR(UMAX, "umax", "ee", 'c') | |
970 | ||
971 | /* These unary operations are used to represent incrementation | |
972 | and decrementation as they occur in memory addresses. | |
973 | The amount of increment or decrement are not represented | |
974 | because they can be understood from the machine-mode of the | |
975 | containing MEM. These operations exist in only two cases: | |
976 | 1. pushes onto the stack. | |
977 | 2. created automatically by the life_analysis pass in flow.c. */ | |
4b983fdc RH |
978 | DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'a') |
979 | DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'a') | |
980 | DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'a') | |
981 | DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'a') | |
1af1688b | 982 | |
b18cfc28 MH |
983 | /* These binary operations are used to represent generic address |
984 | side-effects in memory addresses, except for simple incrementation | |
985 | or decrementation which use the above operations. They are | |
4b983fdc RH |
986 | created automatically by the life_analysis pass in flow.c. |
987 | The first operand is a REG which is used as the address. | |
988 | The second operand is an expression that is assigned to the | |
989 | register, either before (PRE_MODIFY) or after (POST_MODIFY) | |
990 | evaluating the address. | |
991 | Currently, the compiler can only handle second operands of the | |
992 | form (plus (reg) (reg)) and (plus (reg) (const_int)), where | |
993 | the first operand of the PLUS has to be the same register as | |
994 | the first operand of the *_MODIFY. */ | |
995 | DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'a') | |
996 | DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'a') | |
b18cfc28 | 997 | |
1af1688b RK |
998 | /* Comparison operations. The ordered comparisons exist in two |
999 | flavors, signed and unsigned. */ | |
1000 | DEF_RTL_EXPR(NE, "ne", "ee", '<') | |
1001 | DEF_RTL_EXPR(EQ, "eq", "ee", '<') | |
1002 | DEF_RTL_EXPR(GE, "ge", "ee", '<') | |
1003 | DEF_RTL_EXPR(GT, "gt", "ee", '<') | |
1004 | DEF_RTL_EXPR(LE, "le", "ee", '<') | |
1005 | DEF_RTL_EXPR(LT, "lt", "ee", '<') | |
1006 | DEF_RTL_EXPR(GEU, "geu", "ee", '<') | |
1007 | DEF_RTL_EXPR(GTU, "gtu", "ee", '<') | |
1008 | DEF_RTL_EXPR(LEU, "leu", "ee", '<') | |
1009 | DEF_RTL_EXPR(LTU, "ltu", "ee", '<') | |
1010 | ||
14b493d6 | 1011 | /* Additional floating point unordered comparison flavors. */ |
1eb8759b RH |
1012 | DEF_RTL_EXPR(UNORDERED, "unordered", "ee", '<') |
1013 | DEF_RTL_EXPR(ORDERED, "ordered", "ee", '<') | |
1014 | ||
991b6592 | 1015 | /* These are equivalent to unordered or ... */ |
1eb8759b RH |
1016 | DEF_RTL_EXPR(UNEQ, "uneq", "ee", '<') |
1017 | DEF_RTL_EXPR(UNGE, "unge", "ee", '<') | |
1018 | DEF_RTL_EXPR(UNGT, "ungt", "ee", '<') | |
1019 | DEF_RTL_EXPR(UNLE, "unle", "ee", '<') | |
1020 | DEF_RTL_EXPR(UNLT, "unlt", "ee", '<') | |
1021 | ||
7913f3d0 RH |
1022 | /* This is an ordered NE, ie !UNEQ, ie false for NaN. */ |
1023 | DEF_RTL_EXPR(LTGT, "ltgt", "ee", '<') | |
1024 | ||
1af1688b RK |
1025 | /* Represents the result of sign-extending the sole operand. |
1026 | The machine modes of the operand and of the SIGN_EXTEND expression | |
1027 | determine how much sign-extension is going on. */ | |
1028 | DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1') | |
1029 | ||
1030 | /* Similar for zero-extension (such as unsigned short to int). */ | |
1031 | DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1') | |
1032 | ||
1033 | /* Similar but here the operand has a wider mode. */ | |
1034 | DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1') | |
1035 | ||
1036 | /* Similar for extending floating-point values (such as SFmode to DFmode). */ | |
1037 | DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1') | |
1038 | DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1') | |
1039 | ||
1040 | /* Conversion of fixed point operand to floating point value. */ | |
1041 | DEF_RTL_EXPR(FLOAT, "float", "e", '1') | |
1042 | ||
1043 | /* With fixed-point machine mode: | |
1044 | Conversion of floating point operand to fixed point value. | |
1045 | Value is defined only when the operand's value is an integer. | |
1046 | With floating-point machine mode (and operand with same mode): | |
1047 | Operand is rounded toward zero to produce an integer value | |
1048 | represented in floating point. */ | |
1049 | DEF_RTL_EXPR(FIX, "fix", "e", '1') | |
1050 | ||
1051 | /* Conversion of unsigned fixed point operand to floating point value. */ | |
1052 | DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1') | |
1053 | ||
1054 | /* With fixed-point machine mode: | |
1055 | Conversion of floating point operand to *unsigned* fixed point value. | |
1056 | Value is defined only when the operand's value is an integer. */ | |
1057 | DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1') | |
1058 | ||
1059 | /* Absolute value */ | |
1060 | DEF_RTL_EXPR(ABS, "abs", "e", '1') | |
1061 | ||
1062 | /* Square root */ | |
1063 | DEF_RTL_EXPR(SQRT, "sqrt", "e", '1') | |
1064 | ||
1065 | /* Find first bit that is set. | |
1066 | Value is 1 + number of trailing zeros in the arg., | |
1067 | or 0 if arg is 0. */ | |
1068 | DEF_RTL_EXPR(FFS, "ffs", "e", '1') | |
1069 | ||
2928cd7a RH |
1070 | /* Count leading zeros. */ |
1071 | DEF_RTL_EXPR(CLZ, "clz", "e", '1') | |
1072 | ||
1073 | /* Count trailing zeros. */ | |
1074 | DEF_RTL_EXPR(CTZ, "ctz", "e", '1') | |
1075 | ||
1076 | /* Population count (number of 1 bits). */ | |
1077 | DEF_RTL_EXPR(POPCOUNT, "popcount", "e", '1') | |
1078 | ||
1079 | /* Population parity (number of 1 bits modulo 2). */ | |
1080 | DEF_RTL_EXPR(PARITY, "parity", "e", '1') | |
1081 | ||
1af1688b RK |
1082 | /* Reference to a signed bit-field of specified size and position. |
1083 | Operand 0 is the memory unit (usually SImode or QImode) which | |
1084 | contains the field's first bit. Operand 1 is the width, in bits. | |
1085 | Operand 2 is the number of bits in the memory unit before the | |
1086 | first bit of this field. | |
1087 | If BITS_BIG_ENDIAN is defined, the first bit is the msb and | |
1088 | operand 2 counts from the msb of the memory unit. | |
1089 | Otherwise, the first bit is the lsb and operand 2 counts from | |
1090 | the lsb of the memory unit. */ | |
1091 | DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b') | |
1092 | ||
1093 | /* Similar for unsigned bit-field. */ | |
1094 | DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b') | |
1095 | ||
1096 | /* For RISC machines. These save memory when splitting insns. */ | |
1097 | ||
1098 | /* HIGH are the high-order bits of a constant expression. */ | |
1099 | DEF_RTL_EXPR(HIGH, "high", "e", 'o') | |
1100 | ||
1101 | /* LO_SUM is the sum of a register and the low-order bits | |
1102 | of a constant expression. */ | |
1103 | DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o') | |
1104 | ||
b3b42a4d | 1105 | /* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn. |
0dfa1860 MM |
1106 | Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of |
1107 | the registers that can be substituted within this range. Operand 3 is the | |
1108 | number of calls in the range. Operand 4 is the number of insns in the | |
1109 | range. Operand 5 is the unique range number for this range. Operand 6 is | |
1110 | the basic block # of the start of the live range. Operand 7 is the basic | |
1111 | block # of the end of the live range. Operand 8 is the loop depth. Operand | |
1112 | 9 is a bitmap of the registers live at the start of the range. Operand 10 | |
1113 | is a bitmap of the registers live at the end of the range. Operand 11 is | |
1114 | marker number for the start of the range. Operand 12 is the marker number | |
1115 | for the end of the range. */ | |
1116 | DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", 'x') | |
1117 | ||
1118 | /* Registers that can be substituted within the range. Operand 0 is the | |
1119 | original pseudo register number. Operand 1 will be filled in with the | |
1120 | pseudo register the value is copied for the duration of the range. Operand | |
1121 | 2 is the number of references within the range to the register. Operand 3 | |
1122 | is the number of sets or clobbers of the register in the range. Operand 4 | |
1123 | is the number of deaths the register has. Operand 5 is the copy flags that | |
1124 | give the status of whether a copy is needed from the original register to | |
1125 | the new register at the beginning of the range, or whether a copy from the | |
1126 | new register back to the original at the end of the range. Operand 6 is the | |
1127 | live length. Operand 7 is the number of calls that this register is live | |
1128 | across. Operand 8 is the symbol node of the variable if the register is a | |
1129 | user variable. Operand 9 is the block node that the variable is declared | |
991b6592 | 1130 | in if the register is a user variable. */ |
0dfa1860 MM |
1131 | DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", 'x') |
1132 | ||
1133 | /* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of | |
1134 | the different ranges a variable is in where it is copied to a different | |
1135 | pseudo register. Operand 1 is the block that the variable is declared in. | |
1136 | Operand 2 is the number of distinct ranges. */ | |
1137 | DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", 'x') | |
1138 | ||
1139 | /* Information about the registers that are live at the current point. Operand | |
1140 | 0 is the live bitmap. Operand 1 is the original block number. */ | |
1141 | DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", 'x') | |
1142 | ||
bcb33994 BS |
1143 | /* A unary `__builtin_constant_p' expression. These are only emitted |
1144 | during RTL generation, and then only if optimize > 0. They are | |
991b6592 | 1145 | eliminated by the first CSE pass. */ |
bcb33994 BS |
1146 | DEF_RTL_EXPR(CONSTANT_P_RTX, "constant_p_rtx", "e", 'x') |
1147 | ||
09554da9 JL |
1148 | /* A placeholder for a CALL_INSN which may be turned into a normal call, |
1149 | a sibling (tail) call or tail recursion. | |
1150 | ||
1151 | Immediately after RTL generation, this placeholder will be replaced | |
1152 | by the insns to perform the call, sibcall or tail recursion. | |
1153 | ||
1154 | This RTX has 4 operands. The first three are lists of instructions to | |
1155 | perform the call as a normal call, sibling call and tail recursion | |
1156 | respectively. The latter two lists may be NULL, the first may never | |
1157 | be NULL. | |
1158 | ||
1159 | The last operand is the tail recursion CODE_LABEL, which may be NULL if no | |
1160 | potential tail recursive calls were found. | |
1161 | ||
1162 | The tail recursion label is needed so that we can clear LABEL_PRESERVE_P | |
0a1c58a2 JL |
1163 | after we select a call method. |
1164 | ||
1165 | This method of tail-call elimination is intended to be replaced by | |
1166 | tree-based optimizations once front-end conversions are complete. */ | |
09554da9 JL |
1167 | DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x') |
1168 | ||
f9f27ee5 BS |
1169 | /* Describes a merge operation between two vector values. |
1170 | Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask | |
1171 | that specifies where the parts of the result are taken from. Set bits | |
1172 | indicate operand 0, clear bits indicate operand 1. The parts are defined | |
1173 | by the mode of the vectors. */ | |
d9deed68 | 1174 | DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", '3') |
f9f27ee5 BS |
1175 | |
1176 | /* Describes an operation that selects parts of a vector. | |
1177 | Operands 0 is the source vector, operand 1 is a PARALLEL that contains | |
1178 | a CONST_INT for each of the subparts of the result vector, giving the | |
1179 | number of the source subpart that should be stored into it. */ | |
d9deed68 | 1180 | DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", '2') |
f9f27ee5 BS |
1181 | |
1182 | /* Describes a vector concat operation. Operands 0 and 1 are the source | |
1183 | vectors, the result is a vector that is as long as operands 0 and 1 | |
1184 | combined and is the concatenation of the two source vectors. */ | |
d9deed68 | 1185 | DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", '2') |
f9f27ee5 | 1186 | |
f9f27ee5 BS |
1187 | /* Describes an operation that converts a small vector into a larger one by |
1188 | duplicating the input values. The output vector mode must have the same | |
1189 | submodes as the input vector mode, and the number of output parts must be | |
1190 | an integer multiple of the number of input parts. */ | |
d9deed68 | 1191 | DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", '1') |
f9f27ee5 BS |
1192 | |
1193 | /* Addition with signed saturation */ | |
1194 | DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", 'c') | |
1195 | ||
1196 | /* Addition with unsigned saturation */ | |
1197 | DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", 'c') | |
1198 | ||
1199 | /* Operand 0 minus operand 1, with signed saturation. */ | |
1200 | DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", '2') | |
1201 | ||
1202 | /* Operand 0 minus operand 1, with unsigned saturation. */ | |
1203 | DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", '2') | |
1204 | ||
1205 | /* Signed saturating truncate. */ | |
1206 | DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", '1') | |
1207 | ||
1208 | /* Unsigned saturating truncate. */ | |
1209 | DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", '1') | |
1210 | ||
d9d4fb43 | 1211 | |
1af1688b RK |
1212 | /* |
1213 | Local variables: | |
1214 | mode:c | |
1af1688b RK |
1215 | End: |
1216 | */ |