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6a73406e | 1 | /* Definitions for computing resource usage of specific insns. |
e146f815 | 2 | Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004 |
0c20a65f | 3 | Free Software Foundation, Inc. |
6a73406e | 4 | |
1322177d | 5 | This file is part of GCC. |
6a73406e | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
6a73406e | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
6a73406e RH |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
6a73406e | 21 | |
ca545bb5 | 22 | #include "config.h" |
8ce25479 | 23 | #include "system.h" |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
01198c2f | 26 | #include "toplev.h" |
ca545bb5 | 27 | #include "rtl.h" |
6baf1cc8 | 28 | #include "tm_p.h" |
ca545bb5 | 29 | #include "hard-reg-set.h" |
ca545bb5 | 30 | #include "basic-block.h" |
49ad7cfa | 31 | #include "function.h" |
ca545bb5 BM |
32 | #include "regs.h" |
33 | #include "flags.h" | |
34 | #include "output.h" | |
35 | #include "resource.h" | |
d80eb1e1 | 36 | #include "except.h" |
7bdb32b9 | 37 | #include "insn-attr.h" |
d5d063d7 | 38 | #include "params.h" |
ca545bb5 BM |
39 | |
40 | /* This structure is used to record liveness information at the targets or | |
41 | fallthrough insns of branches. We will most likely need the information | |
42 | at targets again, so save them in a hash table rather than recomputing them | |
43 | each time. */ | |
44 | ||
45 | struct target_info | |
46 | { | |
47 | int uid; /* INSN_UID of target. */ | |
48 | struct target_info *next; /* Next info for same hash bucket. */ | |
49 | HARD_REG_SET live_regs; /* Registers live at target. */ | |
50 | int block; /* Basic block number containing target. */ | |
51 | int bb_tick; /* Generation count of basic block info. */ | |
52 | }; | |
53 | ||
54 | #define TARGET_HASH_PRIME 257 | |
55 | ||
56 | /* Indicates what resources are required at the beginning of the epilogue. */ | |
57 | static struct resources start_of_epilogue_needs; | |
58 | ||
59 | /* Indicates what resources are required at function end. */ | |
60 | static struct resources end_of_function_needs; | |
61 | ||
62 | /* Define the hash table itself. */ | |
63 | static struct target_info **target_hash_table = NULL; | |
64 | ||
65 | /* For each basic block, we maintain a generation number of its basic | |
66 | block info, which is updated each time we move an insn from the | |
67 | target of a jump. This is the generation number indexed by block | |
68 | number. */ | |
69 | ||
70 | static int *bb_ticks; | |
71 | ||
72 | /* Marks registers possibly live at the current place being scanned by | |
d5d063d7 | 73 | mark_target_live_regs. Also used by update_live_status. */ |
ca545bb5 BM |
74 | |
75 | static HARD_REG_SET current_live_regs; | |
76 | ||
77 | /* Marks registers for which we have seen a REG_DEAD note but no assignment. | |
78 | Also only used by the next two functions. */ | |
79 | ||
80 | static HARD_REG_SET pending_dead_regs; | |
6a73406e | 81 | \f |
0c20a65f AJ |
82 | static void update_live_status (rtx, rtx, void *); |
83 | static int find_basic_block (rtx, int); | |
84 | static rtx next_insn_no_annul (rtx); | |
85 | static rtx find_dead_or_set_registers (rtx, struct resources*, | |
86 | rtx*, int, struct resources, | |
87 | struct resources); | |
6a73406e | 88 | \f |
ca545bb5 BM |
89 | /* Utility function called from mark_target_live_regs via note_stores. |
90 | It deadens any CLOBBERed registers and livens any SET registers. */ | |
91 | ||
92 | static void | |
0c20a65f | 93 | update_live_status (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED) |
ca545bb5 BM |
94 | { |
95 | int first_regno, last_regno; | |
96 | int i; | |
97 | ||
f8cfc6aa JQ |
98 | if (!REG_P (dest) |
99 | && (GET_CODE (dest) != SUBREG || !REG_P (SUBREG_REG (dest)))) | |
ca545bb5 BM |
100 | return; |
101 | ||
102 | if (GET_CODE (dest) == SUBREG) | |
ddef6bc7 | 103 | first_regno = subreg_regno (dest); |
ca545bb5 BM |
104 | else |
105 | first_regno = REGNO (dest); | |
106 | ||
66fd46b6 | 107 | last_regno = first_regno + hard_regno_nregs[first_regno][GET_MODE (dest)]; |
ca545bb5 BM |
108 | |
109 | if (GET_CODE (x) == CLOBBER) | |
110 | for (i = first_regno; i < last_regno; i++) | |
111 | CLEAR_HARD_REG_BIT (current_live_regs, i); | |
112 | else | |
113 | for (i = first_regno; i < last_regno; i++) | |
114 | { | |
115 | SET_HARD_REG_BIT (current_live_regs, i); | |
116 | CLEAR_HARD_REG_BIT (pending_dead_regs, i); | |
117 | } | |
118 | } | |
d5d063d7 JO |
119 | |
120 | /* Find the number of the basic block with correct live register | |
121 | information that starts closest to INSN. Return -1 if we couldn't | |
122 | find such a basic block or the beginning is more than | |
123 | SEARCH_LIMIT instructions before INSN. Use SEARCH_LIMIT = -1 for | |
124 | an unlimited search. | |
125 | ||
126 | The delay slot filling code destroys the control-flow graph so, | |
127 | instead of finding the basic block containing INSN, we search | |
128 | backwards toward a BARRIER where the live register information is | |
129 | correct. */ | |
925fa227 RH |
130 | |
131 | static int | |
0c20a65f | 132 | find_basic_block (rtx insn, int search_limit) |
925fa227 | 133 | { |
e0082a72 | 134 | basic_block bb; |
925fa227 RH |
135 | |
136 | /* Scan backwards to the previous BARRIER. Then see if we can find a | |
137 | label that starts a basic block. Return the basic block number. */ | |
925fa227 | 138 | for (insn = prev_nonnote_insn (insn); |
d5d063d7 JO |
139 | insn && GET_CODE (insn) != BARRIER && search_limit != 0; |
140 | insn = prev_nonnote_insn (insn), --search_limit) | |
925fa227 RH |
141 | ; |
142 | ||
d5d063d7 JO |
143 | /* The closest BARRIER is too far away. */ |
144 | if (search_limit == 0) | |
145 | return -1; | |
146 | ||
f6366fc7 | 147 | /* The start of the function. */ |
d5d063d7 | 148 | else if (insn == 0) |
f6366fc7 | 149 | return ENTRY_BLOCK_PTR->next_bb->index; |
925fa227 RH |
150 | |
151 | /* See if any of the upcoming CODE_LABELs start a basic block. If we reach | |
152 | anything other than a CODE_LABEL or note, we can't find this code. */ | |
153 | for (insn = next_nonnote_insn (insn); | |
154 | insn && GET_CODE (insn) == CODE_LABEL; | |
155 | insn = next_nonnote_insn (insn)) | |
156 | { | |
e0082a72 | 157 | FOR_EACH_BB (bb) |
a813c111 | 158 | if (insn == BB_HEAD (bb)) |
e0082a72 | 159 | return bb->index; |
925fa227 RH |
160 | } |
161 | ||
162 | return -1; | |
163 | } | |
ca545bb5 BM |
164 | \f |
165 | /* Similar to next_insn, but ignores insns in the delay slots of | |
166 | an annulled branch. */ | |
167 | ||
168 | static rtx | |
0c20a65f | 169 | next_insn_no_annul (rtx insn) |
ca545bb5 BM |
170 | { |
171 | if (insn) | |
172 | { | |
173 | /* If INSN is an annulled branch, skip any insns from the target | |
174 | of the branch. */ | |
7440af14 DM |
175 | if ((GET_CODE (insn) == JUMP_INSN |
176 | || GET_CODE (insn) == CALL_INSN | |
177 | || GET_CODE (insn) == INSN) | |
cf40ea15 | 178 | && INSN_ANNULLED_BRANCH_P (insn) |
ca545bb5 | 179 | && NEXT_INSN (PREV_INSN (insn)) != insn) |
cf40ea15 DM |
180 | { |
181 | rtx next = NEXT_INSN (insn); | |
182 | enum rtx_code code = GET_CODE (next); | |
183 | ||
184 | while ((code == INSN || code == JUMP_INSN || code == CALL_INSN) | |
185 | && INSN_FROM_TARGET_P (next)) | |
186 | { | |
187 | insn = next; | |
188 | next = NEXT_INSN (insn); | |
189 | code = GET_CODE (next); | |
190 | } | |
191 | } | |
ca545bb5 BM |
192 | |
193 | insn = NEXT_INSN (insn); | |
194 | if (insn && GET_CODE (insn) == INSN | |
195 | && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
196 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
197 | } | |
198 | ||
199 | return insn; | |
200 | } | |
201 | \f | |
202 | /* Given X, some rtl, and RES, a pointer to a `struct resource', mark | |
f5df2e8c | 203 | which resources are referenced by the insn. If INCLUDE_DELAYED_EFFECTS |
ca545bb5 BM |
204 | is TRUE, resources used by the called routine will be included for |
205 | CALL_INSNs. */ | |
206 | ||
207 | void | |
0c20a65f AJ |
208 | mark_referenced_resources (rtx x, struct resources *res, |
209 | int include_delayed_effects) | |
ca545bb5 | 210 | { |
770ae6cc RK |
211 | enum rtx_code code = GET_CODE (x); |
212 | int i, j; | |
213 | unsigned int r; | |
b3694847 | 214 | const char *format_ptr; |
ca545bb5 BM |
215 | |
216 | /* Handle leaf items for which we set resource flags. Also, special-case | |
217 | CALL, SET and CLOBBER operators. */ | |
218 | switch (code) | |
219 | { | |
220 | case CONST: | |
221 | case CONST_INT: | |
222 | case CONST_DOUBLE: | |
69ef87e2 | 223 | case CONST_VECTOR: |
ca545bb5 BM |
224 | case PC: |
225 | case SYMBOL_REF: | |
226 | case LABEL_REF: | |
227 | return; | |
228 | ||
229 | case SUBREG: | |
f8cfc6aa | 230 | if (!REG_P (SUBREG_REG (x))) |
ca545bb5 BM |
231 | mark_referenced_resources (SUBREG_REG (x), res, 0); |
232 | else | |
233 | { | |
ddef6bc7 | 234 | unsigned int regno = subreg_regno (x); |
770ae6cc | 235 | unsigned int last_regno |
66fd46b6 | 236 | = regno + hard_regno_nregs[regno][GET_MODE (x)]; |
770ae6cc | 237 | |
1d2215fe AO |
238 | if (last_regno > FIRST_PSEUDO_REGISTER) |
239 | abort (); | |
770ae6cc RK |
240 | for (r = regno; r < last_regno; r++) |
241 | SET_HARD_REG_BIT (res->regs, r); | |
ca545bb5 BM |
242 | } |
243 | return; | |
244 | ||
245 | case REG: | |
1d2215fe AO |
246 | { |
247 | unsigned int regno = REGNO (x); | |
248 | unsigned int last_regno | |
66fd46b6 | 249 | = regno + hard_regno_nregs[regno][GET_MODE (x)]; |
1d2215fe AO |
250 | |
251 | if (last_regno > FIRST_PSEUDO_REGISTER) | |
252 | abort (); | |
253 | for (r = regno; r < last_regno; r++) | |
254 | SET_HARD_REG_BIT (res->regs, r); | |
255 | } | |
ca545bb5 BM |
256 | return; |
257 | ||
258 | case MEM: | |
259 | /* If this memory shouldn't change, it really isn't referencing | |
260 | memory. */ | |
261 | if (RTX_UNCHANGING_P (x)) | |
262 | res->unch_memory = 1; | |
263 | else | |
264 | res->memory = 1; | |
a5045352 | 265 | res->volatil |= MEM_VOLATILE_P (x); |
ca545bb5 BM |
266 | |
267 | /* Mark registers used to access memory. */ | |
268 | mark_referenced_resources (XEXP (x, 0), res, 0); | |
269 | return; | |
270 | ||
271 | case CC0: | |
272 | res->cc = 1; | |
273 | return; | |
274 | ||
275 | case UNSPEC_VOLATILE: | |
276 | case ASM_INPUT: | |
277 | /* Traditional asm's are always volatile. */ | |
278 | res->volatil = 1; | |
279 | return; | |
280 | ||
281 | case TRAP_IF: | |
282 | res->volatil = 1; | |
283 | break; | |
284 | ||
285 | case ASM_OPERANDS: | |
a5045352 | 286 | res->volatil |= MEM_VOLATILE_P (x); |
ca545bb5 BM |
287 | |
288 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
289 | We can not just fall through here since then we would be confused | |
290 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate | |
291 | traditional asms unlike their normal usage. */ | |
a6a2274a | 292 | |
ca545bb5 BM |
293 | for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) |
294 | mark_referenced_resources (ASM_OPERANDS_INPUT (x, i), res, 0); | |
295 | return; | |
296 | ||
297 | case CALL: | |
298 | /* The first operand will be a (MEM (xxx)) but doesn't really reference | |
299 | memory. The second operand may be referenced, though. */ | |
300 | mark_referenced_resources (XEXP (XEXP (x, 0), 0), res, 0); | |
301 | mark_referenced_resources (XEXP (x, 1), res, 0); | |
302 | return; | |
303 | ||
304 | case SET: | |
305 | /* Usually, the first operand of SET is set, not referenced. But | |
306 | registers used to access memory are referenced. SET_DEST is | |
307 | also referenced if it is a ZERO_EXTRACT or SIGN_EXTRACT. */ | |
308 | ||
309 | mark_referenced_resources (SET_SRC (x), res, 0); | |
310 | ||
311 | x = SET_DEST (x); | |
07570c39 AO |
312 | if (GET_CODE (x) == SIGN_EXTRACT |
313 | || GET_CODE (x) == ZERO_EXTRACT | |
314 | || GET_CODE (x) == STRICT_LOW_PART) | |
ca545bb5 BM |
315 | mark_referenced_resources (x, res, 0); |
316 | else if (GET_CODE (x) == SUBREG) | |
317 | x = SUBREG_REG (x); | |
3c0cb5de | 318 | if (MEM_P (x)) |
ca545bb5 BM |
319 | mark_referenced_resources (XEXP (x, 0), res, 0); |
320 | return; | |
321 | ||
322 | case CLOBBER: | |
323 | return; | |
324 | ||
325 | case CALL_INSN: | |
326 | if (include_delayed_effects) | |
327 | { | |
328 | /* A CALL references memory, the frame pointer if it exists, the | |
329 | stack pointer, any global registers and any registers given in | |
330 | USE insns immediately in front of the CALL. | |
331 | ||
332 | However, we may have moved some of the parameter loading insns | |
333 | into the delay slot of this CALL. If so, the USE's for them | |
334 | don't count and should be skipped. */ | |
335 | rtx insn = PREV_INSN (x); | |
336 | rtx sequence = 0; | |
337 | int seq_size = 0; | |
ca545bb5 BM |
338 | int i; |
339 | ||
340 | /* If we are part of a delay slot sequence, point at the SEQUENCE. */ | |
341 | if (NEXT_INSN (insn) != x) | |
342 | { | |
ca545bb5 BM |
343 | sequence = PATTERN (NEXT_INSN (insn)); |
344 | seq_size = XVECLEN (sequence, 0); | |
345 | if (GET_CODE (sequence) != SEQUENCE) | |
346 | abort (); | |
347 | } | |
348 | ||
349 | res->memory = 1; | |
350 | SET_HARD_REG_BIT (res->regs, STACK_POINTER_REGNUM); | |
351 | if (frame_pointer_needed) | |
352 | { | |
353 | SET_HARD_REG_BIT (res->regs, FRAME_POINTER_REGNUM); | |
354 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
355 | SET_HARD_REG_BIT (res->regs, HARD_FRAME_POINTER_REGNUM); | |
356 | #endif | |
357 | } | |
358 | ||
359 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
360 | if (global_regs[i]) | |
361 | SET_HARD_REG_BIT (res->regs, i); | |
362 | ||
570a98eb | 363 | /* Check for a REG_SETJMP. If it exists, then we must |
ca545bb5 BM |
364 | assume that this call can need any register. |
365 | ||
366 | This is done to be more conservative about how we handle setjmp. | |
367 | We assume that they both use and set all registers. Using all | |
368 | registers ensures that a register will not be considered dead | |
369 | just because it crosses a setjmp call. A register should be | |
40f03658 | 370 | considered dead only if the setjmp call returns nonzero. */ |
570a98eb | 371 | if (find_reg_note (x, REG_SETJMP, NULL)) |
ca545bb5 BM |
372 | SET_HARD_REG_SET (res->regs); |
373 | ||
374 | { | |
375 | rtx link; | |
376 | ||
377 | for (link = CALL_INSN_FUNCTION_USAGE (x); | |
378 | link; | |
379 | link = XEXP (link, 1)) | |
380 | if (GET_CODE (XEXP (link, 0)) == USE) | |
381 | { | |
382 | for (i = 1; i < seq_size; i++) | |
383 | { | |
384 | rtx slot_pat = PATTERN (XVECEXP (sequence, 0, i)); | |
385 | if (GET_CODE (slot_pat) == SET | |
386 | && rtx_equal_p (SET_DEST (slot_pat), | |
0cb5d81c | 387 | XEXP (XEXP (link, 0), 0))) |
ca545bb5 BM |
388 | break; |
389 | } | |
390 | if (i >= seq_size) | |
0cb5d81c | 391 | mark_referenced_resources (XEXP (XEXP (link, 0), 0), |
ca545bb5 BM |
392 | res, 0); |
393 | } | |
394 | } | |
395 | } | |
396 | ||
397 | /* ... fall through to other INSN processing ... */ | |
398 | ||
399 | case INSN: | |
400 | case JUMP_INSN: | |
401 | ||
402 | #ifdef INSN_REFERENCES_ARE_DELAYED | |
403 | if (! include_delayed_effects | |
404 | && INSN_REFERENCES_ARE_DELAYED (x)) | |
405 | return; | |
406 | #endif | |
407 | ||
408 | /* No special processing, just speed up. */ | |
409 | mark_referenced_resources (PATTERN (x), res, include_delayed_effects); | |
410 | return; | |
411 | ||
412 | default: | |
413 | break; | |
414 | } | |
415 | ||
416 | /* Process each sub-expression and flag what it needs. */ | |
417 | format_ptr = GET_RTX_FORMAT (code); | |
418 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
419 | switch (*format_ptr++) | |
420 | { | |
421 | case 'e': | |
422 | mark_referenced_resources (XEXP (x, i), res, include_delayed_effects); | |
423 | break; | |
424 | ||
425 | case 'E': | |
426 | for (j = 0; j < XVECLEN (x, i); j++) | |
427 | mark_referenced_resources (XVECEXP (x, i, j), res, | |
428 | include_delayed_effects); | |
429 | break; | |
430 | } | |
431 | } | |
432 | \f | |
433 | /* A subroutine of mark_target_live_regs. Search forward from TARGET | |
a6a2274a | 434 | looking for registers that are set before they are used. These are dead. |
ca545bb5 BM |
435 | Stop after passing a few conditional jumps, and/or a small |
436 | number of unconditional branches. */ | |
437 | ||
438 | static rtx | |
0c20a65f AJ |
439 | find_dead_or_set_registers (rtx target, struct resources *res, |
440 | rtx *jump_target, int jump_count, | |
441 | struct resources set, struct resources needed) | |
ca545bb5 BM |
442 | { |
443 | HARD_REG_SET scratch; | |
444 | rtx insn, next; | |
445 | rtx jump_insn = 0; | |
446 | int i; | |
447 | ||
448 | for (insn = target; insn; insn = next) | |
449 | { | |
450 | rtx this_jump_insn = insn; | |
451 | ||
452 | next = NEXT_INSN (insn); | |
0519ce30 MM |
453 | |
454 | /* If this instruction can throw an exception, then we don't | |
455 | know where we might end up next. That means that we have to | |
456 | assume that whatever we have already marked as live really is | |
457 | live. */ | |
54590688 | 458 | if (can_throw_internal (insn)) |
0519ce30 MM |
459 | break; |
460 | ||
ca545bb5 BM |
461 | switch (GET_CODE (insn)) |
462 | { | |
463 | case CODE_LABEL: | |
464 | /* After a label, any pending dead registers that weren't yet | |
465 | used can be made dead. */ | |
466 | AND_COMPL_HARD_REG_SET (pending_dead_regs, needed.regs); | |
467 | AND_COMPL_HARD_REG_SET (res->regs, pending_dead_regs); | |
468 | CLEAR_HARD_REG_SET (pending_dead_regs); | |
469 | ||
470 | continue; | |
471 | ||
472 | case BARRIER: | |
473 | case NOTE: | |
474 | continue; | |
475 | ||
476 | case INSN: | |
477 | if (GET_CODE (PATTERN (insn)) == USE) | |
478 | { | |
479 | /* If INSN is a USE made by update_block, we care about the | |
480 | underlying insn. Any registers set by the underlying insn | |
481 | are live since the insn is being done somewhere else. */ | |
2c3c49de | 482 | if (INSN_P (XEXP (PATTERN (insn), 0))) |
73780b74 SC |
483 | mark_set_resources (XEXP (PATTERN (insn), 0), res, 0, |
484 | MARK_SRC_DEST_CALL); | |
ca545bb5 BM |
485 | |
486 | /* All other USE insns are to be ignored. */ | |
487 | continue; | |
488 | } | |
489 | else if (GET_CODE (PATTERN (insn)) == CLOBBER) | |
490 | continue; | |
491 | else if (GET_CODE (PATTERN (insn)) == SEQUENCE) | |
492 | { | |
493 | /* An unconditional jump can be used to fill the delay slot | |
494 | of a call, so search for a JUMP_INSN in any position. */ | |
495 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
496 | { | |
497 | this_jump_insn = XVECEXP (PATTERN (insn), 0, i); | |
498 | if (GET_CODE (this_jump_insn) == JUMP_INSN) | |
499 | break; | |
500 | } | |
501 | } | |
502 | ||
503 | default: | |
504 | break; | |
505 | } | |
506 | ||
507 | if (GET_CODE (this_jump_insn) == JUMP_INSN) | |
508 | { | |
509 | if (jump_count++ < 10) | |
510 | { | |
7f1c097d | 511 | if (any_uncondjump_p (this_jump_insn) |
ca545bb5 BM |
512 | || GET_CODE (PATTERN (this_jump_insn)) == RETURN) |
513 | { | |
514 | next = JUMP_LABEL (this_jump_insn); | |
515 | if (jump_insn == 0) | |
516 | { | |
517 | jump_insn = insn; | |
518 | if (jump_target) | |
519 | *jump_target = JUMP_LABEL (this_jump_insn); | |
520 | } | |
521 | } | |
7f1c097d | 522 | else if (any_condjump_p (this_jump_insn)) |
ca545bb5 BM |
523 | { |
524 | struct resources target_set, target_res; | |
525 | struct resources fallthrough_res; | |
526 | ||
527 | /* We can handle conditional branches here by following | |
528 | both paths, and then IOR the results of the two paths | |
529 | together, which will give us registers that are dead | |
530 | on both paths. Since this is expensive, we give it | |
531 | a much higher cost than unconditional branches. The | |
532 | cost was chosen so that we will follow at most 1 | |
533 | conditional branch. */ | |
534 | ||
535 | jump_count += 4; | |
536 | if (jump_count >= 10) | |
537 | break; | |
538 | ||
539 | mark_referenced_resources (insn, &needed, 1); | |
540 | ||
541 | /* For an annulled branch, mark_set_resources ignores slots | |
542 | filled by instructions from the target. This is correct | |
543 | if the branch is not taken. Since we are following both | |
544 | paths from the branch, we must also compute correct info | |
545 | if the branch is taken. We do this by inverting all of | |
546 | the INSN_FROM_TARGET_P bits, calling mark_set_resources, | |
547 | and then inverting the INSN_FROM_TARGET_P bits again. */ | |
548 | ||
549 | if (GET_CODE (PATTERN (insn)) == SEQUENCE | |
550 | && INSN_ANNULLED_BRANCH_P (this_jump_insn)) | |
551 | { | |
552 | for (i = 1; i < XVECLEN (PATTERN (insn), 0); i++) | |
553 | INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i)) | |
554 | = ! INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i)); | |
555 | ||
556 | target_set = set; | |
73780b74 SC |
557 | mark_set_resources (insn, &target_set, 0, |
558 | MARK_SRC_DEST_CALL); | |
ca545bb5 BM |
559 | |
560 | for (i = 1; i < XVECLEN (PATTERN (insn), 0); i++) | |
561 | INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i)) | |
562 | = ! INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn), 0, i)); | |
563 | ||
73780b74 | 564 | mark_set_resources (insn, &set, 0, MARK_SRC_DEST_CALL); |
ca545bb5 BM |
565 | } |
566 | else | |
567 | { | |
73780b74 | 568 | mark_set_resources (insn, &set, 0, MARK_SRC_DEST_CALL); |
ca545bb5 BM |
569 | target_set = set; |
570 | } | |
571 | ||
572 | target_res = *res; | |
573 | COPY_HARD_REG_SET (scratch, target_set.regs); | |
574 | AND_COMPL_HARD_REG_SET (scratch, needed.regs); | |
575 | AND_COMPL_HARD_REG_SET (target_res.regs, scratch); | |
576 | ||
577 | fallthrough_res = *res; | |
578 | COPY_HARD_REG_SET (scratch, set.regs); | |
579 | AND_COMPL_HARD_REG_SET (scratch, needed.regs); | |
580 | AND_COMPL_HARD_REG_SET (fallthrough_res.regs, scratch); | |
581 | ||
582 | find_dead_or_set_registers (JUMP_LABEL (this_jump_insn), | |
583 | &target_res, 0, jump_count, | |
584 | target_set, needed); | |
585 | find_dead_or_set_registers (next, | |
586 | &fallthrough_res, 0, jump_count, | |
587 | set, needed); | |
588 | IOR_HARD_REG_SET (fallthrough_res.regs, target_res.regs); | |
589 | AND_HARD_REG_SET (res->regs, fallthrough_res.regs); | |
590 | break; | |
591 | } | |
592 | else | |
593 | break; | |
594 | } | |
595 | else | |
596 | { | |
597 | /* Don't try this optimization if we expired our jump count | |
598 | above, since that would mean there may be an infinite loop | |
599 | in the function being compiled. */ | |
600 | jump_insn = 0; | |
601 | break; | |
602 | } | |
603 | } | |
604 | ||
605 | mark_referenced_resources (insn, &needed, 1); | |
73780b74 | 606 | mark_set_resources (insn, &set, 0, MARK_SRC_DEST_CALL); |
ca545bb5 BM |
607 | |
608 | COPY_HARD_REG_SET (scratch, set.regs); | |
609 | AND_COMPL_HARD_REG_SET (scratch, needed.regs); | |
610 | AND_COMPL_HARD_REG_SET (res->regs, scratch); | |
611 | } | |
612 | ||
613 | return jump_insn; | |
614 | } | |
615 | \f | |
616 | /* Given X, a part of an insn, and a pointer to a `struct resource', | |
617 | RES, indicate which resources are modified by the insn. If | |
73780b74 | 618 | MARK_TYPE is MARK_SRC_DEST_CALL, also mark resources potentially |
73fb6466 | 619 | set by the called routine. |
ca545bb5 BM |
620 | |
621 | If IN_DEST is nonzero, it means we are inside a SET. Otherwise, | |
622 | objects are being referenced instead of set. | |
623 | ||
624 | We never mark the insn as modifying the condition code unless it explicitly | |
625 | SETs CC0 even though this is not totally correct. The reason for this is | |
626 | that we require a SET of CC0 to immediately precede the reference to CC0. | |
627 | So if some other insn sets CC0 as a side-effect, we know it cannot affect | |
6d2f8887 | 628 | our computation and thus may be placed in a delay slot. */ |
ca545bb5 BM |
629 | |
630 | void | |
0c20a65f AJ |
631 | mark_set_resources (rtx x, struct resources *res, int in_dest, |
632 | enum mark_resource_type mark_type) | |
ca545bb5 | 633 | { |
770ae6cc RK |
634 | enum rtx_code code; |
635 | int i, j; | |
636 | unsigned int r; | |
637 | const char *format_ptr; | |
ca545bb5 BM |
638 | |
639 | restart: | |
640 | ||
641 | code = GET_CODE (x); | |
642 | ||
643 | switch (code) | |
644 | { | |
645 | case NOTE: | |
646 | case BARRIER: | |
647 | case CODE_LABEL: | |
648 | case USE: | |
649 | case CONST_INT: | |
650 | case CONST_DOUBLE: | |
69ef87e2 | 651 | case CONST_VECTOR: |
ca545bb5 BM |
652 | case LABEL_REF: |
653 | case SYMBOL_REF: | |
654 | case CONST: | |
655 | case PC: | |
656 | /* These don't set any resources. */ | |
657 | return; | |
658 | ||
659 | case CC0: | |
660 | if (in_dest) | |
661 | res->cc = 1; | |
662 | return; | |
663 | ||
664 | case CALL_INSN: | |
665 | /* Called routine modifies the condition code, memory, any registers | |
666 | that aren't saved across calls, global registers and anything | |
667 | explicitly CLOBBERed immediately after the CALL_INSN. */ | |
668 | ||
73780b74 | 669 | if (mark_type == MARK_SRC_DEST_CALL) |
ca545bb5 | 670 | { |
ca545bb5 BM |
671 | rtx link; |
672 | ||
673 | res->cc = res->memory = 1; | |
770ae6cc RK |
674 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
675 | if (call_used_regs[r] || global_regs[r]) | |
676 | SET_HARD_REG_BIT (res->regs, r); | |
ca545bb5 | 677 | |
ca545bb5 BM |
678 | for (link = CALL_INSN_FUNCTION_USAGE (x); |
679 | link; link = XEXP (link, 1)) | |
680 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
73780b74 SC |
681 | mark_set_resources (SET_DEST (XEXP (link, 0)), res, 1, |
682 | MARK_SRC_DEST); | |
ca545bb5 | 683 | |
570a98eb | 684 | /* Check for a REG_SETJMP. If it exists, then we must |
ca545bb5 | 685 | assume that this call can clobber any register. */ |
570a98eb | 686 | if (find_reg_note (x, REG_SETJMP, NULL)) |
ca545bb5 BM |
687 | SET_HARD_REG_SET (res->regs); |
688 | } | |
689 | ||
690 | /* ... and also what its RTL says it modifies, if anything. */ | |
691 | ||
692 | case JUMP_INSN: | |
693 | case INSN: | |
694 | ||
695 | /* An insn consisting of just a CLOBBER (or USE) is just for flow | |
696 | and doesn't actually do anything, so we ignore it. */ | |
697 | ||
698 | #ifdef INSN_SETS_ARE_DELAYED | |
73780b74 | 699 | if (mark_type != MARK_SRC_DEST_CALL |
ca545bb5 BM |
700 | && INSN_SETS_ARE_DELAYED (x)) |
701 | return; | |
702 | #endif | |
703 | ||
704 | x = PATTERN (x); | |
705 | if (GET_CODE (x) != USE && GET_CODE (x) != CLOBBER) | |
706 | goto restart; | |
707 | return; | |
708 | ||
709 | case SET: | |
710 | /* If the source of a SET is a CALL, this is actually done by | |
711 | the called routine. So only include it if we are to include the | |
712 | effects of the calling routine. */ | |
713 | ||
714 | mark_set_resources (SET_DEST (x), res, | |
73780b74 | 715 | (mark_type == MARK_SRC_DEST_CALL |
ca545bb5 | 716 | || GET_CODE (SET_SRC (x)) != CALL), |
73780b74 | 717 | mark_type); |
ca545bb5 | 718 | |
73fb6466 | 719 | mark_set_resources (SET_SRC (x), res, 0, MARK_SRC_DEST); |
ca545bb5 BM |
720 | return; |
721 | ||
722 | case CLOBBER: | |
73780b74 | 723 | mark_set_resources (XEXP (x, 0), res, 1, MARK_SRC_DEST); |
ca545bb5 | 724 | return; |
a6a2274a | 725 | |
ca545bb5 BM |
726 | case SEQUENCE: |
727 | for (i = 0; i < XVECLEN (x, 0); i++) | |
728 | if (! (INSN_ANNULLED_BRANCH_P (XVECEXP (x, 0, 0)) | |
729 | && INSN_FROM_TARGET_P (XVECEXP (x, 0, i)))) | |
73780b74 | 730 | mark_set_resources (XVECEXP (x, 0, i), res, 0, mark_type); |
ca545bb5 BM |
731 | return; |
732 | ||
733 | case POST_INC: | |
734 | case PRE_INC: | |
735 | case POST_DEC: | |
736 | case PRE_DEC: | |
73780b74 | 737 | mark_set_resources (XEXP (x, 0), res, 1, MARK_SRC_DEST); |
ca545bb5 BM |
738 | return; |
739 | ||
4b983fdc RH |
740 | case PRE_MODIFY: |
741 | case POST_MODIFY: | |
1fb9c5cd MH |
742 | mark_set_resources (XEXP (x, 0), res, 1, MARK_SRC_DEST); |
743 | mark_set_resources (XEXP (XEXP (x, 1), 0), res, 0, MARK_SRC_DEST); | |
744 | mark_set_resources (XEXP (XEXP (x, 1), 1), res, 0, MARK_SRC_DEST); | |
4b983fdc RH |
745 | return; |
746 | ||
73780b74 | 747 | case SIGN_EXTRACT: |
ca545bb5 | 748 | case ZERO_EXTRACT: |
73fb6466 HPN |
749 | mark_set_resources (XEXP (x, 0), res, in_dest, MARK_SRC_DEST); |
750 | mark_set_resources (XEXP (x, 1), res, 0, MARK_SRC_DEST); | |
751 | mark_set_resources (XEXP (x, 2), res, 0, MARK_SRC_DEST); | |
ca545bb5 BM |
752 | return; |
753 | ||
754 | case MEM: | |
755 | if (in_dest) | |
756 | { | |
757 | res->memory = 1; | |
a5045352 MM |
758 | res->unch_memory |= RTX_UNCHANGING_P (x); |
759 | res->volatil |= MEM_VOLATILE_P (x); | |
ca545bb5 BM |
760 | } |
761 | ||
73780b74 | 762 | mark_set_resources (XEXP (x, 0), res, 0, MARK_SRC_DEST); |
ca545bb5 BM |
763 | return; |
764 | ||
765 | case SUBREG: | |
766 | if (in_dest) | |
767 | { | |
f8cfc6aa | 768 | if (!REG_P (SUBREG_REG (x))) |
73780b74 | 769 | mark_set_resources (SUBREG_REG (x), res, in_dest, mark_type); |
ca545bb5 BM |
770 | else |
771 | { | |
ddef6bc7 | 772 | unsigned int regno = subreg_regno (x); |
770ae6cc | 773 | unsigned int last_regno |
66fd46b6 | 774 | = regno + hard_regno_nregs[regno][GET_MODE (x)]; |
770ae6cc | 775 | |
1d2215fe AO |
776 | if (last_regno > FIRST_PSEUDO_REGISTER) |
777 | abort (); | |
770ae6cc RK |
778 | for (r = regno; r < last_regno; r++) |
779 | SET_HARD_REG_BIT (res->regs, r); | |
ca545bb5 BM |
780 | } |
781 | } | |
782 | return; | |
783 | ||
784 | case REG: | |
785 | if (in_dest) | |
1d2215fe AO |
786 | { |
787 | unsigned int regno = REGNO (x); | |
788 | unsigned int last_regno | |
66fd46b6 | 789 | = regno + hard_regno_nregs[regno][GET_MODE (x)]; |
1d2215fe AO |
790 | |
791 | if (last_regno > FIRST_PSEUDO_REGISTER) | |
792 | abort (); | |
793 | for (r = regno; r < last_regno; r++) | |
794 | SET_HARD_REG_BIT (res->regs, r); | |
795 | } | |
ca545bb5 BM |
796 | return; |
797 | ||
3d298f8f MM |
798 | case UNSPEC_VOLATILE: |
799 | case ASM_INPUT: | |
800 | /* Traditional asm's are always volatile. */ | |
801 | res->volatil = 1; | |
802 | return; | |
803 | ||
804 | case TRAP_IF: | |
805 | res->volatil = 1; | |
806 | break; | |
807 | ||
808 | case ASM_OPERANDS: | |
a5045352 | 809 | res->volatil |= MEM_VOLATILE_P (x); |
3d298f8f MM |
810 | |
811 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
812 | We can not just fall through here since then we would be confused | |
813 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate | |
814 | traditional asms unlike their normal usage. */ | |
a6a2274a | 815 | |
3d298f8f | 816 | for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) |
73780b74 SC |
817 | mark_set_resources (ASM_OPERANDS_INPUT (x, i), res, in_dest, |
818 | MARK_SRC_DEST); | |
3d298f8f MM |
819 | return; |
820 | ||
ca545bb5 BM |
821 | default: |
822 | break; | |
823 | } | |
824 | ||
825 | /* Process each sub-expression and flag what it needs. */ | |
826 | format_ptr = GET_RTX_FORMAT (code); | |
827 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
828 | switch (*format_ptr++) | |
829 | { | |
830 | case 'e': | |
73780b74 | 831 | mark_set_resources (XEXP (x, i), res, in_dest, mark_type); |
ca545bb5 BM |
832 | break; |
833 | ||
834 | case 'E': | |
835 | for (j = 0; j < XVECLEN (x, i); j++) | |
73780b74 | 836 | mark_set_resources (XVECEXP (x, i, j), res, in_dest, mark_type); |
ca545bb5 BM |
837 | break; |
838 | } | |
839 | } | |
840 | \f | |
841 | /* Set the resources that are live at TARGET. | |
842 | ||
843 | If TARGET is zero, we refer to the end of the current function and can | |
844 | return our precomputed value. | |
845 | ||
846 | Otherwise, we try to find out what is live by consulting the basic block | |
847 | information. This is tricky, because we must consider the actions of | |
848 | reload and jump optimization, which occur after the basic block information | |
849 | has been computed. | |
850 | ||
851 | Accordingly, we proceed as follows:: | |
852 | ||
853 | We find the previous BARRIER and look at all immediately following labels | |
854 | (with no intervening active insns) to see if any of them start a basic | |
855 | block. If we hit the start of the function first, we use block 0. | |
856 | ||
857 | Once we have found a basic block and a corresponding first insns, we can | |
858 | accurately compute the live status from basic_block_live_regs and | |
859 | reg_renumber. (By starting at a label following a BARRIER, we are immune | |
860 | to actions taken by reload and jump.) Then we scan all insns between | |
861 | that point and our target. For each CLOBBER (or for call-clobbered regs | |
862 | when we pass a CALL_INSN), mark the appropriate registers are dead. For | |
863 | a SET, mark them as live. | |
864 | ||
865 | We have to be careful when using REG_DEAD notes because they are not | |
866 | updated by such things as find_equiv_reg. So keep track of registers | |
867 | marked as dead that haven't been assigned to, and mark them dead at the | |
868 | next CODE_LABEL since reload and jump won't propagate values across labels. | |
869 | ||
870 | If we cannot find the start of a basic block (should be a very rare | |
871 | case, if it can happen at all), mark everything as potentially live. | |
872 | ||
873 | Next, scan forward from TARGET looking for things set or clobbered | |
874 | before they are used. These are not live. | |
875 | ||
876 | Because we can be called many times on the same target, save our results | |
877 | in a hash table indexed by INSN_UID. This is only done if the function | |
878 | init_resource_info () was invoked before we are called. */ | |
879 | ||
880 | void | |
0c20a65f | 881 | mark_target_live_regs (rtx insns, rtx target, struct resources *res) |
ca545bb5 BM |
882 | { |
883 | int b = -1; | |
5197bd50 | 884 | unsigned int i; |
ca545bb5 BM |
885 | struct target_info *tinfo = NULL; |
886 | rtx insn; | |
887 | rtx jump_insn = 0; | |
888 | rtx jump_target; | |
889 | HARD_REG_SET scratch; | |
890 | struct resources set, needed; | |
891 | ||
892 | /* Handle end of function. */ | |
893 | if (target == 0) | |
894 | { | |
895 | *res = end_of_function_needs; | |
896 | return; | |
897 | } | |
898 | ||
899 | /* We have to assume memory is needed, but the CC isn't. */ | |
900 | res->memory = 1; | |
901 | res->volatil = res->unch_memory = 0; | |
902 | res->cc = 0; | |
903 | ||
904 | /* See if we have computed this value already. */ | |
905 | if (target_hash_table != NULL) | |
906 | { | |
907 | for (tinfo = target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME]; | |
908 | tinfo; tinfo = tinfo->next) | |
909 | if (tinfo->uid == INSN_UID (target)) | |
910 | break; | |
911 | ||
912 | /* Start by getting the basic block number. If we have saved | |
913 | information, we can get it from there unless the insn at the | |
914 | start of the basic block has been deleted. */ | |
915 | if (tinfo && tinfo->block != -1 | |
a813c111 | 916 | && ! INSN_DELETED_P (BB_HEAD (BASIC_BLOCK (tinfo->block)))) |
ca545bb5 BM |
917 | b = tinfo->block; |
918 | } | |
919 | ||
925fa227 | 920 | if (b == -1) |
d5d063d7 | 921 | b = find_basic_block (target, MAX_DELAY_SLOT_LIVE_SEARCH); |
ca545bb5 BM |
922 | |
923 | if (target_hash_table != NULL) | |
924 | { | |
925 | if (tinfo) | |
926 | { | |
927 | /* If the information is up-to-date, use it. Otherwise, we will | |
928 | update it below. */ | |
929 | if (b == tinfo->block && b != -1 && tinfo->bb_tick == bb_ticks[b]) | |
930 | { | |
931 | COPY_HARD_REG_SET (res->regs, tinfo->live_regs); | |
932 | return; | |
933 | } | |
934 | } | |
935 | else | |
936 | { | |
a6a2274a | 937 | /* Allocate a place to put our results and chain it into the |
ca545bb5 | 938 | hash table. */ |
703ad42b | 939 | tinfo = xmalloc (sizeof (struct target_info)); |
ca545bb5 BM |
940 | tinfo->uid = INSN_UID (target); |
941 | tinfo->block = b; | |
5197bd50 RK |
942 | tinfo->next |
943 | = target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME]; | |
ca545bb5 BM |
944 | target_hash_table[INSN_UID (target) % TARGET_HASH_PRIME] = tinfo; |
945 | } | |
946 | } | |
947 | ||
948 | CLEAR_HARD_REG_SET (pending_dead_regs); | |
949 | ||
950 | /* If we found a basic block, get the live registers from it and update | |
951 | them with anything set or killed between its start and the insn before | |
952 | TARGET. Otherwise, we must assume everything is live. */ | |
953 | if (b != -1) | |
954 | { | |
e881bb1b | 955 | regset regs_live = BASIC_BLOCK (b)->global_live_at_start; |
770ae6cc RK |
956 | unsigned int j; |
957 | unsigned int regno; | |
ca545bb5 BM |
958 | rtx start_insn, stop_insn; |
959 | ||
960 | /* Compute hard regs live at start of block -- this is the real hard regs | |
961 | marked live, plus live pseudo regs that have been renumbered to | |
962 | hard regs. */ | |
963 | ||
964 | REG_SET_TO_HARD_REG_SET (current_live_regs, regs_live); | |
965 | ||
966 | EXECUTE_IF_SET_IN_REG_SET | |
967 | (regs_live, FIRST_PSEUDO_REGISTER, i, | |
968 | { | |
770ae6cc RK |
969 | if (reg_renumber[i] >= 0) |
970 | { | |
971 | regno = reg_renumber[i]; | |
972 | for (j = regno; | |
66fd46b6 JH |
973 | j < regno + hard_regno_nregs[regno] |
974 | [PSEUDO_REGNO_MODE (i)]; | |
770ae6cc RK |
975 | j++) |
976 | SET_HARD_REG_BIT (current_live_regs, j); | |
977 | } | |
ca545bb5 BM |
978 | }); |
979 | ||
980 | /* Get starting and ending insn, handling the case where each might | |
981 | be a SEQUENCE. */ | |
a813c111 | 982 | start_insn = (b == 0 ? insns : BB_HEAD (BASIC_BLOCK (b))); |
ca545bb5 BM |
983 | stop_insn = target; |
984 | ||
985 | if (GET_CODE (start_insn) == INSN | |
986 | && GET_CODE (PATTERN (start_insn)) == SEQUENCE) | |
987 | start_insn = XVECEXP (PATTERN (start_insn), 0, 0); | |
988 | ||
989 | if (GET_CODE (stop_insn) == INSN | |
990 | && GET_CODE (PATTERN (stop_insn)) == SEQUENCE) | |
991 | stop_insn = next_insn (PREV_INSN (stop_insn)); | |
992 | ||
993 | for (insn = start_insn; insn != stop_insn; | |
994 | insn = next_insn_no_annul (insn)) | |
995 | { | |
996 | rtx link; | |
997 | rtx real_insn = insn; | |
cf40ea15 | 998 | enum rtx_code code = GET_CODE (insn); |
ca545bb5 BM |
999 | |
1000 | /* If this insn is from the target of a branch, it isn't going to | |
1001 | be used in the sequel. If it is used in both cases, this | |
1002 | test will not be true. */ | |
cf40ea15 DM |
1003 | if ((code == INSN || code == JUMP_INSN || code == CALL_INSN) |
1004 | && INSN_FROM_TARGET_P (insn)) | |
ca545bb5 BM |
1005 | continue; |
1006 | ||
1007 | /* If this insn is a USE made by update_block, we care about the | |
1008 | underlying insn. */ | |
cf40ea15 | 1009 | if (code == INSN && GET_CODE (PATTERN (insn)) == USE |
2c3c49de | 1010 | && INSN_P (XEXP (PATTERN (insn), 0))) |
ca545bb5 BM |
1011 | real_insn = XEXP (PATTERN (insn), 0); |
1012 | ||
1013 | if (GET_CODE (real_insn) == CALL_INSN) | |
1014 | { | |
1015 | /* CALL clobbers all call-used regs that aren't fixed except | |
1016 | sp, ap, and fp. Do this before setting the result of the | |
1017 | call live. */ | |
12beba6f RH |
1018 | AND_COMPL_HARD_REG_SET (current_live_regs, |
1019 | regs_invalidated_by_call); | |
ca545bb5 BM |
1020 | |
1021 | /* A CALL_INSN sets any global register live, since it may | |
1022 | have been modified by the call. */ | |
1023 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1024 | if (global_regs[i]) | |
1025 | SET_HARD_REG_BIT (current_live_regs, i); | |
1026 | } | |
1027 | ||
1028 | /* Mark anything killed in an insn to be deadened at the next | |
1029 | label. Ignore USE insns; the only REG_DEAD notes will be for | |
1030 | parameters. But they might be early. A CALL_INSN will usually | |
1031 | clobber registers used for parameters. It isn't worth bothering | |
1032 | with the unlikely case when it won't. */ | |
1033 | if ((GET_CODE (real_insn) == INSN | |
1034 | && GET_CODE (PATTERN (real_insn)) != USE | |
1035 | && GET_CODE (PATTERN (real_insn)) != CLOBBER) | |
1036 | || GET_CODE (real_insn) == JUMP_INSN | |
1037 | || GET_CODE (real_insn) == CALL_INSN) | |
1038 | { | |
1039 | for (link = REG_NOTES (real_insn); link; link = XEXP (link, 1)) | |
1040 | if (REG_NOTE_KIND (link) == REG_DEAD | |
f8cfc6aa | 1041 | && REG_P (XEXP (link, 0)) |
ca545bb5 BM |
1042 | && REGNO (XEXP (link, 0)) < FIRST_PSEUDO_REGISTER) |
1043 | { | |
5197bd50 RK |
1044 | unsigned int first_regno = REGNO (XEXP (link, 0)); |
1045 | unsigned int last_regno | |
ca545bb5 | 1046 | = (first_regno |
66fd46b6 JH |
1047 | + hard_regno_nregs[first_regno] |
1048 | [GET_MODE (XEXP (link, 0))]); | |
a6a2274a | 1049 | |
ca545bb5 BM |
1050 | for (i = first_regno; i < last_regno; i++) |
1051 | SET_HARD_REG_BIT (pending_dead_regs, i); | |
1052 | } | |
1053 | ||
84832317 | 1054 | note_stores (PATTERN (real_insn), update_live_status, NULL); |
ca545bb5 BM |
1055 | |
1056 | /* If any registers were unused after this insn, kill them. | |
1057 | These notes will always be accurate. */ | |
1058 | for (link = REG_NOTES (real_insn); link; link = XEXP (link, 1)) | |
1059 | if (REG_NOTE_KIND (link) == REG_UNUSED | |
f8cfc6aa | 1060 | && REG_P (XEXP (link, 0)) |
ca545bb5 BM |
1061 | && REGNO (XEXP (link, 0)) < FIRST_PSEUDO_REGISTER) |
1062 | { | |
5197bd50 RK |
1063 | unsigned int first_regno = REGNO (XEXP (link, 0)); |
1064 | unsigned int last_regno | |
ca545bb5 | 1065 | = (first_regno |
66fd46b6 JH |
1066 | + hard_regno_nregs[first_regno] |
1067 | [GET_MODE (XEXP (link, 0))]); | |
a6a2274a | 1068 | |
ca545bb5 BM |
1069 | for (i = first_regno; i < last_regno; i++) |
1070 | CLEAR_HARD_REG_BIT (current_live_regs, i); | |
1071 | } | |
1072 | } | |
1073 | ||
1074 | else if (GET_CODE (real_insn) == CODE_LABEL) | |
1075 | { | |
1076 | /* A label clobbers the pending dead registers since neither | |
1077 | reload nor jump will propagate a value across a label. */ | |
1078 | AND_COMPL_HARD_REG_SET (current_live_regs, pending_dead_regs); | |
1079 | CLEAR_HARD_REG_SET (pending_dead_regs); | |
1080 | } | |
1081 | ||
1082 | /* The beginning of the epilogue corresponds to the end of the | |
1083 | RTL chain when there are no epilogue insns. Certain resources | |
1084 | are implicitly required at that point. */ | |
1085 | else if (GET_CODE (real_insn) == NOTE | |
a6a2274a | 1086 | && NOTE_LINE_NUMBER (real_insn) == NOTE_INSN_EPILOGUE_BEG) |
ca545bb5 BM |
1087 | IOR_HARD_REG_SET (current_live_regs, start_of_epilogue_needs.regs); |
1088 | } | |
1089 | ||
1090 | COPY_HARD_REG_SET (res->regs, current_live_regs); | |
1091 | if (tinfo != NULL) | |
1092 | { | |
1093 | tinfo->block = b; | |
1094 | tinfo->bb_tick = bb_ticks[b]; | |
1095 | } | |
1096 | } | |
1097 | else | |
1098 | /* We didn't find the start of a basic block. Assume everything | |
1099 | in use. This should happen only extremely rarely. */ | |
1100 | SET_HARD_REG_SET (res->regs); | |
1101 | ||
1102 | CLEAR_RESOURCE (&set); | |
1103 | CLEAR_RESOURCE (&needed); | |
1104 | ||
1105 | jump_insn = find_dead_or_set_registers (target, res, &jump_target, 0, | |
1106 | set, needed); | |
1107 | ||
1108 | /* If we hit an unconditional branch, we have another way of finding out | |
1109 | what is live: we can see what is live at the branch target and include | |
96e9c98d | 1110 | anything used but not set before the branch. We add the live |
dc297297 | 1111 | resources found using the test below to those found until now. */ |
ca545bb5 BM |
1112 | |
1113 | if (jump_insn) | |
1114 | { | |
1115 | struct resources new_resources; | |
1116 | rtx stop_insn = next_active_insn (jump_insn); | |
1117 | ||
1118 | mark_target_live_regs (insns, next_active_insn (jump_target), | |
1119 | &new_resources); | |
1120 | CLEAR_RESOURCE (&set); | |
1121 | CLEAR_RESOURCE (&needed); | |
1122 | ||
1123 | /* Include JUMP_INSN in the needed registers. */ | |
1124 | for (insn = target; insn != stop_insn; insn = next_active_insn (insn)) | |
1125 | { | |
1126 | mark_referenced_resources (insn, &needed, 1); | |
1127 | ||
1128 | COPY_HARD_REG_SET (scratch, needed.regs); | |
1129 | AND_COMPL_HARD_REG_SET (scratch, set.regs); | |
1130 | IOR_HARD_REG_SET (new_resources.regs, scratch); | |
1131 | ||
73780b74 | 1132 | mark_set_resources (insn, &set, 0, MARK_SRC_DEST_CALL); |
ca545bb5 BM |
1133 | } |
1134 | ||
96e9c98d | 1135 | IOR_HARD_REG_SET (res->regs, new_resources.regs); |
ca545bb5 BM |
1136 | } |
1137 | ||
1138 | if (tinfo != NULL) | |
1139 | { | |
1140 | COPY_HARD_REG_SET (tinfo->live_regs, res->regs); | |
1141 | } | |
1142 | } | |
1143 | \f | |
1144 | /* Initialize the resources required by mark_target_live_regs (). | |
1145 | This should be invoked before the first call to mark_target_live_regs. */ | |
1146 | ||
1147 | void | |
0c20a65f | 1148 | init_resource_info (rtx epilogue_insn) |
ca545bb5 BM |
1149 | { |
1150 | int i; | |
1151 | ||
1152 | /* Indicate what resources are required to be valid at the end of the current | |
1153 | function. The condition code never is and memory always is. If the | |
1154 | frame pointer is needed, it is and so is the stack pointer unless | |
40f03658 | 1155 | EXIT_IGNORE_STACK is nonzero. If the frame pointer is not needed, the |
ca545bb5 BM |
1156 | stack pointer is. Registers used to return the function value are |
1157 | needed. Registers holding global variables are needed. */ | |
1158 | ||
1159 | end_of_function_needs.cc = 0; | |
1160 | end_of_function_needs.memory = 1; | |
1161 | end_of_function_needs.unch_memory = 0; | |
1162 | CLEAR_HARD_REG_SET (end_of_function_needs.regs); | |
1163 | ||
1164 | if (frame_pointer_needed) | |
1165 | { | |
1166 | SET_HARD_REG_BIT (end_of_function_needs.regs, FRAME_POINTER_REGNUM); | |
1167 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
1168 | SET_HARD_REG_BIT (end_of_function_needs.regs, HARD_FRAME_POINTER_REGNUM); | |
1169 | #endif | |
ca545bb5 BM |
1170 | if (! EXIT_IGNORE_STACK |
1171 | || current_function_sp_is_unchanging) | |
ca545bb5 BM |
1172 | SET_HARD_REG_BIT (end_of_function_needs.regs, STACK_POINTER_REGNUM); |
1173 | } | |
1174 | else | |
1175 | SET_HARD_REG_BIT (end_of_function_needs.regs, STACK_POINTER_REGNUM); | |
1176 | ||
1177 | if (current_function_return_rtx != 0) | |
1178 | mark_referenced_resources (current_function_return_rtx, | |
1179 | &end_of_function_needs, 1); | |
1180 | ||
1181 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1182 | if (global_regs[i] | |
1183 | #ifdef EPILOGUE_USES | |
1184 | || EPILOGUE_USES (i) | |
1185 | #endif | |
1186 | ) | |
1187 | SET_HARD_REG_BIT (end_of_function_needs.regs, i); | |
1188 | ||
1189 | /* The registers required to be live at the end of the function are | |
1190 | represented in the flow information as being dead just prior to | |
1191 | reaching the end of the function. For example, the return of a value | |
1192 | might be represented by a USE of the return register immediately | |
1193 | followed by an unconditional jump to the return label where the | |
1194 | return label is the end of the RTL chain. The end of the RTL chain | |
1195 | is then taken to mean that the return register is live. | |
1196 | ||
1197 | This sequence is no longer maintained when epilogue instructions are | |
1198 | added to the RTL chain. To reconstruct the original meaning, the | |
1199 | start of the epilogue (NOTE_INSN_EPILOGUE_BEG) is regarded as the | |
1200 | point where these registers become live (start_of_epilogue_needs). | |
1201 | If epilogue instructions are present, the registers set by those | |
1202 | instructions won't have been processed by flow. Thus, those | |
1203 | registers are additionally required at the end of the RTL chain | |
1204 | (end_of_function_needs). */ | |
1205 | ||
1206 | start_of_epilogue_needs = end_of_function_needs; | |
1207 | ||
1208 | while ((epilogue_insn = next_nonnote_insn (epilogue_insn))) | |
73780b74 SC |
1209 | mark_set_resources (epilogue_insn, &end_of_function_needs, 0, |
1210 | MARK_SRC_DEST_CALL); | |
ca545bb5 BM |
1211 | |
1212 | /* Allocate and initialize the tables used by mark_target_live_regs. */ | |
703ad42b KG |
1213 | target_hash_table = xcalloc (TARGET_HASH_PRIME, sizeof (struct target_info *)); |
1214 | bb_ticks = xcalloc (last_basic_block, sizeof (int)); | |
ca545bb5 BM |
1215 | } |
1216 | \f | |
14b493d6 | 1217 | /* Free up the resources allocated to mark_target_live_regs (). This |
ca545bb5 BM |
1218 | should be invoked after the last call to mark_target_live_regs (). */ |
1219 | ||
1220 | void | |
0c20a65f | 1221 | free_resource_info (void) |
ca545bb5 BM |
1222 | { |
1223 | if (target_hash_table != NULL) | |
1224 | { | |
1f8f4a0b | 1225 | int i; |
a6a2274a KH |
1226 | |
1227 | for (i = 0; i < TARGET_HASH_PRIME; ++i) | |
1f8f4a0b MM |
1228 | { |
1229 | struct target_info *ti = target_hash_table[i]; | |
1230 | ||
a6a2274a | 1231 | while (ti) |
1f8f4a0b MM |
1232 | { |
1233 | struct target_info *next = ti->next; | |
1234 | free (ti); | |
1235 | ti = next; | |
1236 | } | |
1237 | } | |
1238 | ||
ca545bb5 BM |
1239 | free (target_hash_table); |
1240 | target_hash_table = NULL; | |
1241 | } | |
1242 | ||
1243 | if (bb_ticks != NULL) | |
1244 | { | |
1245 | free (bb_ticks); | |
1246 | bb_ticks = NULL; | |
1247 | } | |
1248 | } | |
1249 | \f | |
1250 | /* Clear any hashed information that we have stored for INSN. */ | |
1251 | ||
1252 | void | |
0c20a65f | 1253 | clear_hashed_info_for_insn (rtx insn) |
ca545bb5 BM |
1254 | { |
1255 | struct target_info *tinfo; | |
a6a2274a | 1256 | |
ca545bb5 BM |
1257 | if (target_hash_table != NULL) |
1258 | { | |
1259 | for (tinfo = target_hash_table[INSN_UID (insn) % TARGET_HASH_PRIME]; | |
1260 | tinfo; tinfo = tinfo->next) | |
1261 | if (tinfo->uid == INSN_UID (insn)) | |
1262 | break; | |
1263 | ||
1264 | if (tinfo) | |
1265 | tinfo->block = -1; | |
1266 | } | |
1267 | } | |
1268 | \f | |
1269 | /* Increment the tick count for the basic block that contains INSN. */ | |
1270 | ||
1271 | void | |
0c20a65f | 1272 | incr_ticks_for_insn (rtx insn) |
ca545bb5 | 1273 | { |
d5d063d7 | 1274 | int b = find_basic_block (insn, MAX_DELAY_SLOT_LIVE_SEARCH); |
ca545bb5 BM |
1275 | |
1276 | if (b != -1) | |
1277 | bb_ticks[b]++; | |
1278 | } | |
1279 | \f | |
1280 | /* Add TRIAL to the set of resources used at the end of the current | |
dc297297 | 1281 | function. */ |
ca545bb5 | 1282 | void |
0c20a65f | 1283 | mark_end_of_function_resources (rtx trial, int include_delayed_effects) |
ca545bb5 BM |
1284 | { |
1285 | mark_referenced_resources (trial, &end_of_function_needs, | |
1286 | include_delayed_effects); | |
1287 | } |