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32131a9c | 1 | /* Reload pseudo regs into hard regs for insns that require hard regs. |
af841dbd | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
66647d44 | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
4c9034c5 | 4 | Free Software Foundation, Inc. |
32131a9c | 5 | |
1322177d | 6 | This file is part of GCC. |
32131a9c | 7 | |
1322177d LB |
8 | GCC is free software; you can redistribute it and/or modify it under |
9 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 10 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 11 | version. |
32131a9c | 12 | |
1322177d LB |
13 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | for more details. | |
32131a9c RK |
17 | |
18 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
32131a9c | 21 | |
32131a9c | 22 | #include "config.h" |
670ee920 | 23 | #include "system.h" |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
cab634f2 KG |
26 | |
27 | #include "machmode.h" | |
28 | #include "hard-reg-set.h" | |
32131a9c | 29 | #include "rtl.h" |
6baf1cc8 | 30 | #include "tm_p.h" |
32131a9c RK |
31 | #include "obstack.h" |
32 | #include "insn-config.h" | |
32131a9c | 33 | #include "flags.h" |
49ad7cfa | 34 | #include "function.h" |
32131a9c | 35 | #include "expr.h" |
e78d8e51 | 36 | #include "optabs.h" |
32131a9c | 37 | #include "regs.h" |
c4963a0a | 38 | #include "addresses.h" |
cad6f7d0 | 39 | #include "basic-block.h" |
32131a9c RK |
40 | #include "reload.h" |
41 | #include "recog.h" | |
32131a9c | 42 | #include "output.h" |
a9c366bf | 43 | #include "real.h" |
10f0ad3d | 44 | #include "toplev.h" |
39f95a2c | 45 | #include "except.h" |
a20fd5ac | 46 | #include "tree.h" |
058e97ec | 47 | #include "ira.h" |
6fb5fa3c | 48 | #include "df.h" |
8a99f6f9 | 49 | #include "target.h" |
f6129d66 | 50 | #include "emit-rtl.h" |
32131a9c RK |
51 | |
52 | /* This file contains the reload pass of the compiler, which is | |
53 | run after register allocation has been done. It checks that | |
54 | each insn is valid (operands required to be in registers really | |
55 | are in registers of the proper class) and fixes up invalid ones | |
56 | by copying values temporarily into registers for the insns | |
57 | that need them. | |
58 | ||
59 | The results of register allocation are described by the vector | |
60 | reg_renumber; the insns still contain pseudo regs, but reg_renumber | |
61 | can be used to find which hard reg, if any, a pseudo reg is in. | |
62 | ||
63 | The technique we always use is to free up a few hard regs that are | |
64 | called ``reload regs'', and for each place where a pseudo reg | |
65 | must be in a hard reg, copy it temporarily into one of the reload regs. | |
66 | ||
03acd8f8 BS |
67 | Reload regs are allocated locally for every instruction that needs |
68 | reloads. When there are pseudos which are allocated to a register that | |
69 | has been chosen as a reload reg, such pseudos must be ``spilled''. | |
70 | This means that they go to other hard regs, or to stack slots if no other | |
32131a9c RK |
71 | available hard regs can be found. Spilling can invalidate more |
72 | insns, requiring additional need for reloads, so we must keep checking | |
73 | until the process stabilizes. | |
74 | ||
75 | For machines with different classes of registers, we must keep track | |
76 | of the register class needed for each reload, and make sure that | |
77 | we allocate enough reload registers of each class. | |
78 | ||
79 | The file reload.c contains the code that checks one insn for | |
80 | validity and reports the reloads that it needs. This file | |
81 | is in charge of scanning the entire rtl code, accumulating the | |
82 | reload needs, spilling, assigning reload registers to use for | |
83 | fixing up each insn, and generating the new insns to copy values | |
84 | into the reload registers. */ | |
85 | \f | |
86 | /* During reload_as_needed, element N contains a REG rtx for the hard reg | |
0f41302f | 87 | into which reg N has been reloaded (perhaps for a previous insn). */ |
32131a9c RK |
88 | static rtx *reg_last_reload_reg; |
89 | ||
90 | /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn | |
91 | for an output reload that stores into reg N. */ | |
2c61f5f1 | 92 | static regset_head reg_has_output_reload; |
32131a9c RK |
93 | |
94 | /* Indicates which hard regs are reload-registers for an output reload | |
95 | in the current insn. */ | |
96 | static HARD_REG_SET reg_is_output_reload; | |
97 | ||
98 | /* Element N is the constant value to which pseudo reg N is equivalent, | |
99 | or zero if pseudo reg N is not equivalent to a constant. | |
100 | find_reloads looks at this in order to replace pseudo reg N | |
101 | with the constant it stands for. */ | |
102 | rtx *reg_equiv_constant; | |
103 | ||
ab156144 RH |
104 | /* Element N is an invariant value to which pseudo reg N is equivalent. |
105 | eliminate_regs_in_insn uses this to replace pseudos in particular | |
106 | contexts. */ | |
107 | rtx *reg_equiv_invariant; | |
108 | ||
32131a9c RK |
109 | /* Element N is a memory location to which pseudo reg N is equivalent, |
110 | prior to any register elimination (such as frame pointer to stack | |
111 | pointer). Depending on whether or not it is a valid address, this value | |
112 | is transferred to either reg_equiv_address or reg_equiv_mem. */ | |
4803a34a | 113 | rtx *reg_equiv_memory_loc; |
32131a9c | 114 | |
965ccc5a R |
115 | /* We allocate reg_equiv_memory_loc inside a varray so that the garbage |
116 | collector can keep track of what is inside. */ | |
43b373a2 | 117 | VEC(rtx,gc) *reg_equiv_memory_loc_vec; |
965ccc5a | 118 | |
32131a9c RK |
119 | /* Element N is the address of stack slot to which pseudo reg N is equivalent. |
120 | This is used when the address is not valid as a memory address | |
121 | (because its displacement is too big for the machine.) */ | |
122 | rtx *reg_equiv_address; | |
123 | ||
124 | /* Element N is the memory slot to which pseudo reg N is equivalent, | |
125 | or zero if pseudo reg N is not equivalent to a memory slot. */ | |
126 | rtx *reg_equiv_mem; | |
127 | ||
3f1e3e70 AO |
128 | /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with |
129 | alternate representations of the location of pseudo reg N. */ | |
130 | rtx *reg_equiv_alt_mem_list; | |
131 | ||
32131a9c | 132 | /* Widest width in which each pseudo reg is referred to (via subreg). */ |
770ae6cc | 133 | static unsigned int *reg_max_ref_width; |
32131a9c | 134 | |
135eb61c | 135 | /* Element N is the list of insns that initialized reg N from its equivalent |
32131a9c | 136 | constant or memory slot. */ |
d7f88d86 BS |
137 | rtx *reg_equiv_init; |
138 | int reg_equiv_init_size; | |
32131a9c | 139 | |
03acd8f8 BS |
140 | /* Vector to remember old contents of reg_renumber before spilling. */ |
141 | static short *reg_old_renumber; | |
142 | ||
e6e52be0 | 143 | /* During reload_as_needed, element N contains the last pseudo regno reloaded |
03acd8f8 | 144 | into hard register N. If that pseudo reg occupied more than one register, |
32131a9c RK |
145 | reg_reloaded_contents points to that pseudo for each spill register in |
146 | use; all of these must remain set for an inheritance to occur. */ | |
147 | static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; | |
148 | ||
149 | /* During reload_as_needed, element N contains the insn for which | |
e6e52be0 R |
150 | hard register N was last used. Its contents are significant only |
151 | when reg_reloaded_valid is set for this register. */ | |
32131a9c RK |
152 | static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; |
153 | ||
3eae4643 | 154 | /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */ |
e6e52be0 R |
155 | static HARD_REG_SET reg_reloaded_valid; |
156 | /* Indicate if the register was dead at the end of the reload. | |
157 | This is only valid if reg_reloaded_contents is set and valid. */ | |
158 | static HARD_REG_SET reg_reloaded_dead; | |
159 | ||
e3e9336f DJ |
160 | /* Indicate whether the register's current value is one that is not |
161 | safe to retain across a call, even for registers that are normally | |
fb959f72 | 162 | call-saved. This is only meaningful for members of reg_reloaded_valid. */ |
e3e9336f DJ |
163 | static HARD_REG_SET reg_reloaded_call_part_clobbered; |
164 | ||
32131a9c RK |
165 | /* Number of spill-regs so far; number of valid elements of spill_regs. */ |
166 | static int n_spills; | |
167 | ||
168 | /* In parallel with spill_regs, contains REG rtx's for those regs. | |
169 | Holds the last rtx used for any given reg, or 0 if it has never | |
170 | been used for spilling yet. This rtx is reused, provided it has | |
171 | the proper mode. */ | |
172 | static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
173 | ||
174 | /* In parallel with spill_regs, contains nonzero for a spill reg | |
175 | that was stored after the last time it was used. | |
176 | The precise value is the insn generated to do the store. */ | |
177 | static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
178 | ||
cb2afeb3 R |
179 | /* This is the register that was stored with spill_reg_store. This is a |
180 | copy of reload_out / reload_out_reg when the value was stored; if | |
181 | reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */ | |
182 | static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; | |
183 | ||
32131a9c RK |
184 | /* This table is the inverse mapping of spill_regs: |
185 | indexed by hard reg number, | |
186 | it contains the position of that reg in spill_regs, | |
05d10675 | 187 | or -1 for something that is not in spill_regs. |
13c8e8e3 JL |
188 | |
189 | ?!? This is no longer accurate. */ | |
32131a9c RK |
190 | static short spill_reg_order[FIRST_PSEUDO_REGISTER]; |
191 | ||
03acd8f8 BS |
192 | /* This reg set indicates registers that can't be used as spill registers for |
193 | the currently processed insn. These are the hard registers which are live | |
194 | during the insn, but not allocated to pseudos, as well as fixed | |
195 | registers. */ | |
32131a9c RK |
196 | static HARD_REG_SET bad_spill_regs; |
197 | ||
03acd8f8 BS |
198 | /* These are the hard registers that can't be used as spill register for any |
199 | insn. This includes registers used for user variables and registers that | |
200 | we can't eliminate. A register that appears in this set also can't be used | |
201 | to retry register allocation. */ | |
202 | static HARD_REG_SET bad_spill_regs_global; | |
203 | ||
32131a9c | 204 | /* Describes order of use of registers for reloading |
03acd8f8 BS |
205 | of spilled pseudo-registers. `n_spills' is the number of |
206 | elements that are actually valid; new ones are added at the end. | |
207 | ||
208 | Both spill_regs and spill_reg_order are used on two occasions: | |
209 | once during find_reload_regs, where they keep track of the spill registers | |
210 | for a single insn, but also during reload_as_needed where they show all | |
211 | the registers ever used by reload. For the latter case, the information | |
212 | is calculated during finish_spills. */ | |
32131a9c RK |
213 | static short spill_regs[FIRST_PSEUDO_REGISTER]; |
214 | ||
03acd8f8 BS |
215 | /* This vector of reg sets indicates, for each pseudo, which hard registers |
216 | may not be used for retrying global allocation because the register was | |
217 | formerly spilled from one of them. If we allowed reallocating a pseudo to | |
218 | a register that it was already allocated to, reload might not | |
219 | terminate. */ | |
220 | static HARD_REG_SET *pseudo_previous_regs; | |
221 | ||
222 | /* This vector of reg sets indicates, for each pseudo, which hard | |
223 | registers may not be used for retrying global allocation because they | |
224 | are used as spill registers during one of the insns in which the | |
225 | pseudo is live. */ | |
226 | static HARD_REG_SET *pseudo_forbidden_regs; | |
227 | ||
228 | /* All hard regs that have been used as spill registers for any insn are | |
229 | marked in this set. */ | |
230 | static HARD_REG_SET used_spill_regs; | |
8b4f9969 | 231 | |
4079cd63 JW |
232 | /* Index of last register assigned as a spill register. We allocate in |
233 | a round-robin fashion. */ | |
4079cd63 JW |
234 | static int last_spill_reg; |
235 | ||
32131a9c RK |
236 | /* Nonzero if indirect addressing is supported on the machine; this means |
237 | that spilling (REG n) does not require reloading it into a register in | |
238 | order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The | |
239 | value indicates the level of indirect addressing supported, e.g., two | |
240 | means that (MEM (MEM (REG n))) is also valid if (REG n) does not get | |
241 | a hard register. */ | |
32131a9c RK |
242 | static char spill_indirect_levels; |
243 | ||
244 | /* Nonzero if indirect addressing is supported when the innermost MEM is | |
245 | of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to | |
6d2f8887 | 246 | which these are valid is the same as spill_indirect_levels, above. */ |
98af7219 | 247 | char indirect_symref_ok; |
32131a9c RK |
248 | |
249 | /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ | |
32131a9c RK |
250 | char double_reg_address_ok; |
251 | ||
252 | /* Record the stack slot for each spilled hard register. */ | |
32131a9c RK |
253 | static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; |
254 | ||
255 | /* Width allocated so far for that stack slot. */ | |
770ae6cc | 256 | static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; |
32131a9c | 257 | |
7609e720 | 258 | /* Record which pseudos needed to be spilled. */ |
f5d8c9f4 BS |
259 | static regset_head spilled_pseudos; |
260 | ||
058e97ec VM |
261 | /* Record which pseudos changed their allocation in finish_spills. */ |
262 | static regset_head changed_allocation_pseudos; | |
263 | ||
f5d8c9f4 BS |
264 | /* Used for communication between order_regs_for_reload and count_pseudo. |
265 | Used to avoid counting one pseudo twice. */ | |
266 | static regset_head pseudos_counted; | |
7609e720 | 267 | |
32131a9c RK |
268 | /* First uid used by insns created by reload in this function. |
269 | Used in find_equiv_reg. */ | |
270 | int reload_first_uid; | |
271 | ||
272 | /* Flag set by local-alloc or global-alloc if anything is live in | |
273 | a call-clobbered reg across calls. */ | |
32131a9c RK |
274 | int caller_save_needed; |
275 | ||
276 | /* Set to 1 while reload_as_needed is operating. | |
277 | Required by some machines to handle any generated moves differently. */ | |
32131a9c RK |
278 | int reload_in_progress = 0; |
279 | ||
280 | /* These arrays record the insn_code of insns that may be needed to | |
281 | perform input and output reloads of special objects. They provide a | |
282 | place to pass a scratch register. */ | |
32131a9c RK |
283 | enum insn_code reload_in_optab[NUM_MACHINE_MODES]; |
284 | enum insn_code reload_out_optab[NUM_MACHINE_MODES]; | |
285 | ||
d45cf215 | 286 | /* This obstack is used for allocation of rtl during register elimination. |
32131a9c RK |
287 | The allocated storage can be freed once find_reloads has processed the |
288 | insn. */ | |
5983a90e | 289 | static struct obstack reload_obstack; |
cad6f7d0 BS |
290 | |
291 | /* Points to the beginning of the reload_obstack. All insn_chain structures | |
292 | are allocated first. */ | |
cf0fa607 | 293 | static char *reload_startobj; |
cad6f7d0 BS |
294 | |
295 | /* The point after all insn_chain structures. Used to quickly deallocate | |
f5d8c9f4 | 296 | memory allocated in copy_reloads during calculate_needs_all_insns. */ |
cf0fa607 | 297 | static char *reload_firstobj; |
32131a9c | 298 | |
f5d8c9f4 BS |
299 | /* This points before all local rtl generated by register elimination. |
300 | Used to quickly free all memory after processing one insn. */ | |
301 | static char *reload_insn_firstobj; | |
302 | ||
cad6f7d0 BS |
303 | /* List of insn_chain instructions, one for every insn that reload needs to |
304 | examine. */ | |
305 | struct insn_chain *reload_insn_chain; | |
7609e720 | 306 | |
03acd8f8 | 307 | /* List of all insns needing reloads. */ |
7609e720 | 308 | static struct insn_chain *insns_need_reload; |
32131a9c RK |
309 | \f |
310 | /* This structure is used to record information about register eliminations. | |
311 | Each array entry describes one possible way of eliminating a register | |
312 | in favor of another. If there is more than one way of eliminating a | |
313 | particular register, the most preferred should be specified first. */ | |
314 | ||
590cf94d | 315 | struct elim_table |
32131a9c | 316 | { |
0f41302f MS |
317 | int from; /* Register number to be eliminated. */ |
318 | int to; /* Register number used as replacement. */ | |
b19ee4bd | 319 | HOST_WIDE_INT initial_offset; /* Initial difference between values. */ |
272d0bee | 320 | int can_eliminate; /* Nonzero if this elimination can be done. */ |
32131a9c | 321 | int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over |
0f41302f | 322 | insns made by reload. */ |
b19ee4bd JJ |
323 | HOST_WIDE_INT offset; /* Current offset between the two regs. */ |
324 | HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */ | |
0f41302f | 325 | int ref_outside_mem; /* "to" has been referenced outside a MEM. */ |
32131a9c RK |
326 | rtx from_rtx; /* REG rtx for the register to be eliminated. |
327 | We cannot simply compare the number since | |
328 | we might then spuriously replace a hard | |
329 | register corresponding to a pseudo | |
0f41302f MS |
330 | assigned to the reg to be eliminated. */ |
331 | rtx to_rtx; /* REG rtx for the replacement. */ | |
590cf94d KG |
332 | }; |
333 | ||
1d7254c5 | 334 | static struct elim_table *reg_eliminate = 0; |
590cf94d KG |
335 | |
336 | /* This is an intermediate structure to initialize the table. It has | |
1d7254c5 | 337 | exactly the members provided by ELIMINABLE_REGS. */ |
0b5826ac | 338 | static const struct elim_table_1 |
590cf94d | 339 | { |
0b5826ac KG |
340 | const int from; |
341 | const int to; | |
590cf94d | 342 | } reg_eliminate_1[] = |
32131a9c RK |
343 | |
344 | /* If a set of eliminable registers was specified, define the table from it. | |
345 | Otherwise, default to the normal case of the frame pointer being | |
346 | replaced by the stack pointer. */ | |
347 | ||
348 | #ifdef ELIMINABLE_REGS | |
349 | ELIMINABLE_REGS; | |
350 | #else | |
351 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; | |
352 | #endif | |
353 | ||
b6a1cbae | 354 | #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1) |
32131a9c RK |
355 | |
356 | /* Record the number of pending eliminations that have an offset not equal | |
40f03658 | 357 | to their initial offset. If nonzero, we use a new copy of each |
32131a9c | 358 | replacement result in any insns encountered. */ |
cb2afeb3 | 359 | int num_not_at_initial_offset; |
32131a9c RK |
360 | |
361 | /* Count the number of registers that we may be able to eliminate. */ | |
362 | static int num_eliminable; | |
2b49ee39 R |
363 | /* And the number of registers that are equivalent to a constant that |
364 | can be eliminated to frame_pointer / arg_pointer + constant. */ | |
365 | static int num_eliminable_invariants; | |
32131a9c RK |
366 | |
367 | /* For each label, we record the offset of each elimination. If we reach | |
368 | a label by more than one path and an offset differs, we cannot do the | |
4cc0fdd2 JDA |
369 | elimination. This information is indexed by the difference of the |
370 | number of the label and the first label number. We can't offset the | |
371 | pointer itself as this can cause problems on machines with segmented | |
372 | memory. The first table is an array of flags that records whether we | |
373 | have yet encountered a label and the second table is an array of arrays, | |
374 | one entry in the latter array for each elimination. */ | |
375 | ||
376 | static int first_label_num; | |
32131a9c | 377 | static char *offsets_known_at; |
b19ee4bd | 378 | static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS]; |
32131a9c RK |
379 | |
380 | /* Number of labels in the current function. */ | |
381 | ||
382 | static int num_labels; | |
383 | \f | |
0c20a65f AJ |
384 | static void replace_pseudos_in (rtx *, enum machine_mode, rtx); |
385 | static void maybe_fix_stack_asms (void); | |
386 | static void copy_reloads (struct insn_chain *); | |
387 | static void calculate_needs_all_insns (int); | |
388 | static int find_reg (struct insn_chain *, int); | |
389 | static void find_reload_regs (struct insn_chain *); | |
390 | static void select_reload_regs (void); | |
391 | static void delete_caller_save_insns (void); | |
392 | ||
393 | static void spill_failure (rtx, enum reg_class); | |
394 | static void count_spilled_pseudo (int, int, int); | |
395 | static void delete_dead_insn (rtx); | |
058e97ec | 396 | static void alter_reg (int, int, bool); |
0c20a65f AJ |
397 | static void set_label_offsets (rtx, rtx, int); |
398 | static void check_eliminable_occurrences (rtx); | |
399 | static void elimination_effects (rtx, enum machine_mode); | |
400 | static int eliminate_regs_in_insn (rtx, int); | |
401 | static void update_eliminable_offsets (void); | |
7bc980e1 | 402 | static void mark_not_eliminable (rtx, const_rtx, void *); |
0c20a65f | 403 | static void set_initial_elim_offsets (void); |
9f938de1 | 404 | static bool verify_initial_elim_offsets (void); |
0c20a65f AJ |
405 | static void set_initial_label_offsets (void); |
406 | static void set_offsets_for_label (rtx); | |
407 | static void init_elim_table (void); | |
408 | static void update_eliminables (HARD_REG_SET *); | |
409 | static void spill_hard_reg (unsigned int, int); | |
410 | static int finish_spills (int); | |
0c20a65f AJ |
411 | static void scan_paradoxical_subregs (rtx); |
412 | static void count_pseudo (int); | |
413 | static void order_regs_for_reload (struct insn_chain *); | |
414 | static void reload_as_needed (int); | |
7bc980e1 | 415 | static void forget_old_reloads_1 (rtx, const_rtx, void *); |
db4c7386 | 416 | static void forget_marked_reloads (regset); |
0c20a65f AJ |
417 | static int reload_reg_class_lower (const void *, const void *); |
418 | static void mark_reload_reg_in_use (unsigned int, int, enum reload_type, | |
419 | enum machine_mode); | |
420 | static void clear_reload_reg_in_use (unsigned int, int, enum reload_type, | |
421 | enum machine_mode); | |
422 | static int reload_reg_free_p (unsigned int, int, enum reload_type); | |
423 | static int reload_reg_free_for_value_p (int, int, int, enum reload_type, | |
424 | rtx, rtx, int, int); | |
425 | static int free_for_value_p (int, enum machine_mode, int, enum reload_type, | |
426 | rtx, rtx, int, int); | |
427 | static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type); | |
428 | static int allocate_reload_reg (struct insn_chain *, int, int); | |
429 | static int conflicts_with_override (rtx); | |
430 | static void failed_reload (rtx, int); | |
431 | static int set_reload_reg (int, int); | |
432 | static void choose_reload_regs_init (struct insn_chain *, rtx *); | |
433 | static void choose_reload_regs (struct insn_chain *); | |
434 | static void merge_assigned_reloads (rtx); | |
435 | static void emit_input_reload_insns (struct insn_chain *, struct reload *, | |
436 | rtx, int); | |
437 | static void emit_output_reload_insns (struct insn_chain *, struct reload *, | |
438 | int); | |
439 | static void do_input_reload (struct insn_chain *, struct reload *, int); | |
440 | static void do_output_reload (struct insn_chain *, struct reload *, int); | |
441 | static void emit_reload_insns (struct insn_chain *); | |
fb959f72 | 442 | static void delete_output_reload (rtx, int, int, rtx); |
0c20a65f AJ |
443 | static void delete_address_reloads (rtx, rtx); |
444 | static void delete_address_reloads_1 (rtx, rtx, rtx); | |
445 | static rtx inc_for_reload (rtx, rtx, rtx, int); | |
2dfa9a87 | 446 | #ifdef AUTO_INC_DEC |
0c20a65f | 447 | static void add_auto_inc_notes (rtx, rtx); |
2dfa9a87 | 448 | #endif |
0c20a65f | 449 | static void copy_eh_notes (rtx, rtx); |
058e97ec VM |
450 | static void substitute (rtx *, const_rtx, rtx); |
451 | static bool gen_reload_chain_without_interm_reg_p (int, int); | |
bf9a0db3 KH |
452 | static int reloads_conflict (int, int); |
453 | static rtx gen_reload (rtx, rtx, int, enum reload_type); | |
ff0d9879 | 454 | static rtx emit_insn_if_valid_for_reload (rtx); |
32131a9c | 455 | \f |
b5deb7b6 SL |
456 | /* Initialize the reload pass. This is called at the beginning of compilation |
457 | and may be called again if the target is reinitialized. */ | |
546b63fb | 458 | |
32131a9c | 459 | void |
0c20a65f | 460 | init_reload (void) |
32131a9c | 461 | { |
b3694847 | 462 | int i; |
32131a9c RK |
463 | |
464 | /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. | |
465 | Set spill_indirect_levels to the number of levels such addressing is | |
466 | permitted, zero if it is not permitted at all. */ | |
467 | ||
b3694847 | 468 | rtx tem |
38a448ca RH |
469 | = gen_rtx_MEM (Pmode, |
470 | gen_rtx_PLUS (Pmode, | |
c5c76735 JL |
471 | gen_rtx_REG (Pmode, |
472 | LAST_VIRTUAL_REGISTER + 1), | |
38a448ca | 473 | GEN_INT (4))); |
32131a9c RK |
474 | spill_indirect_levels = 0; |
475 | ||
476 | while (memory_address_p (QImode, tem)) | |
477 | { | |
478 | spill_indirect_levels++; | |
38a448ca | 479 | tem = gen_rtx_MEM (Pmode, tem); |
32131a9c RK |
480 | } |
481 | ||
482 | /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ | |
483 | ||
38a448ca | 484 | tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo")); |
32131a9c RK |
485 | indirect_symref_ok = memory_address_p (QImode, tem); |
486 | ||
487 | /* See if reg+reg is a valid (and offsettable) address. */ | |
488 | ||
65701fd2 | 489 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
57caa638 | 490 | { |
38a448ca RH |
491 | tem = gen_rtx_PLUS (Pmode, |
492 | gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), | |
493 | gen_rtx_REG (Pmode, i)); | |
c5c76735 | 494 | |
57caa638 RS |
495 | /* This way, we make sure that reg+reg is an offsettable address. */ |
496 | tem = plus_constant (tem, 4); | |
497 | ||
498 | if (memory_address_p (QImode, tem)) | |
499 | { | |
500 | double_reg_address_ok = 1; | |
501 | break; | |
502 | } | |
503 | } | |
32131a9c | 504 | |
0f41302f | 505 | /* Initialize obstack for our rtl allocation. */ |
32131a9c | 506 | gcc_obstack_init (&reload_obstack); |
1634b18f | 507 | reload_startobj = XOBNEWVAR (&reload_obstack, char, 0); |
f5d8c9f4 BS |
508 | |
509 | INIT_REG_SET (&spilled_pseudos); | |
058e97ec | 510 | INIT_REG_SET (&changed_allocation_pseudos); |
f5d8c9f4 | 511 | INIT_REG_SET (&pseudos_counted); |
32131a9c RK |
512 | } |
513 | ||
cad6f7d0 BS |
514 | /* List of insn chains that are currently unused. */ |
515 | static struct insn_chain *unused_insn_chains = 0; | |
516 | ||
517 | /* Allocate an empty insn_chain structure. */ | |
518 | struct insn_chain * | |
0c20a65f | 519 | new_insn_chain (void) |
cad6f7d0 BS |
520 | { |
521 | struct insn_chain *c; | |
522 | ||
523 | if (unused_insn_chains == 0) | |
524 | { | |
1634b18f | 525 | c = XOBNEW (&reload_obstack, struct insn_chain); |
239a0f5b BS |
526 | INIT_REG_SET (&c->live_throughout); |
527 | INIT_REG_SET (&c->dead_or_set); | |
cad6f7d0 BS |
528 | } |
529 | else | |
530 | { | |
531 | c = unused_insn_chains; | |
532 | unused_insn_chains = c->next; | |
533 | } | |
534 | c->is_caller_save_insn = 0; | |
03acd8f8 | 535 | c->need_operand_change = 0; |
cad6f7d0 BS |
536 | c->need_reload = 0; |
537 | c->need_elim = 0; | |
538 | return c; | |
539 | } | |
540 | ||
7609e720 BS |
541 | /* Small utility function to set all regs in hard reg set TO which are |
542 | allocated to pseudos in regset FROM. */ | |
770ae6cc | 543 | |
7609e720 | 544 | void |
0c20a65f | 545 | compute_use_by_pseudos (HARD_REG_SET *to, regset from) |
7609e720 | 546 | { |
770ae6cc | 547 | unsigned int regno; |
a2041967 | 548 | reg_set_iterator rsi; |
770ae6cc | 549 | |
a2041967 KH |
550 | EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi) |
551 | { | |
552 | int r = reg_renumber[regno]; | |
a2041967 KH |
553 | |
554 | if (r < 0) | |
555 | { | |
058e97ec VM |
556 | /* reload_combine uses the information from DF_LIVE_IN, |
557 | which might still contain registers that have not | |
558 | actually been allocated since they have an | |
559 | equivalence. */ | |
2af2dbdc | 560 | gcc_assert (ira_conflicts_p || reload_completed); |
a2041967 KH |
561 | } |
562 | else | |
09e18274 | 563 | add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r); |
a2041967 | 564 | } |
7609e720 | 565 | } |
f474c6f8 AO |
566 | |
567 | /* Replace all pseudos found in LOC with their corresponding | |
568 | equivalences. */ | |
569 | ||
570 | static void | |
0c20a65f | 571 | replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage) |
f474c6f8 AO |
572 | { |
573 | rtx x = *loc; | |
574 | enum rtx_code code; | |
575 | const char *fmt; | |
576 | int i, j; | |
577 | ||
578 | if (! x) | |
579 | return; | |
174fa2c4 | 580 | |
f474c6f8 AO |
581 | code = GET_CODE (x); |
582 | if (code == REG) | |
583 | { | |
ae0ed63a | 584 | unsigned int regno = REGNO (x); |
086fef9e AO |
585 | |
586 | if (regno < FIRST_PSEUDO_REGISTER) | |
f474c6f8 AO |
587 | return; |
588 | ||
589 | x = eliminate_regs (x, mem_mode, usage); | |
590 | if (x != *loc) | |
591 | { | |
592 | *loc = x; | |
ee960939 | 593 | replace_pseudos_in (loc, mem_mode, usage); |
f474c6f8 AO |
594 | return; |
595 | } | |
596 | ||
086fef9e AO |
597 | if (reg_equiv_constant[regno]) |
598 | *loc = reg_equiv_constant[regno]; | |
599 | else if (reg_equiv_mem[regno]) | |
600 | *loc = reg_equiv_mem[regno]; | |
601 | else if (reg_equiv_address[regno]) | |
602 | *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]); | |
f474c6f8 | 603 | else |
41374e13 NS |
604 | { |
605 | gcc_assert (!REG_P (regno_reg_rtx[regno]) | |
606 | || REGNO (regno_reg_rtx[regno]) != regno); | |
607 | *loc = regno_reg_rtx[regno]; | |
608 | } | |
f474c6f8 AO |
609 | |
610 | return; | |
611 | } | |
612 | else if (code == MEM) | |
613 | { | |
ee960939 | 614 | replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage); |
f474c6f8 AO |
615 | return; |
616 | } | |
174fa2c4 | 617 | |
f474c6f8 AO |
618 | /* Process each of our operands recursively. */ |
619 | fmt = GET_RTX_FORMAT (code); | |
620 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
621 | if (*fmt == 'e') | |
ee960939 | 622 | replace_pseudos_in (&XEXP (x, i), mem_mode, usage); |
f474c6f8 AO |
623 | else if (*fmt == 'E') |
624 | for (j = 0; j < XVECLEN (x, i); j++) | |
ee960939 | 625 | replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage); |
f474c6f8 AO |
626 | } |
627 | ||
ecaebb9e NS |
628 | /* Determine if the current function has an exception receiver block |
629 | that reaches the exit block via non-exceptional edges */ | |
630 | ||
631 | static bool | |
632 | has_nonexceptional_receiver (void) | |
633 | { | |
634 | edge e; | |
635 | edge_iterator ei; | |
636 | basic_block *tos, *worklist, bb; | |
637 | ||
638 | /* If we're not optimizing, then just err on the safe side. */ | |
639 | if (!optimize) | |
640 | return true; | |
641 | ||
642 | /* First determine which blocks can reach exit via normal paths. */ | |
1634b18f | 643 | tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1); |
ecaebb9e NS |
644 | |
645 | FOR_EACH_BB (bb) | |
646 | bb->flags &= ~BB_REACHABLE; | |
647 | ||
648 | /* Place the exit block on our worklist. */ | |
649 | EXIT_BLOCK_PTR->flags |= BB_REACHABLE; | |
650 | *tos++ = EXIT_BLOCK_PTR; | |
651 | ||
652 | /* Iterate: find everything reachable from what we've already seen. */ | |
653 | while (tos != worklist) | |
654 | { | |
655 | bb = *--tos; | |
656 | ||
657 | FOR_EACH_EDGE (e, ei, bb->preds) | |
658 | if (!(e->flags & EDGE_ABNORMAL)) | |
659 | { | |
660 | basic_block src = e->src; | |
661 | ||
662 | if (!(src->flags & BB_REACHABLE)) | |
663 | { | |
664 | src->flags |= BB_REACHABLE; | |
665 | *tos++ = src; | |
666 | } | |
667 | } | |
668 | } | |
669 | free (worklist); | |
670 | ||
671 | /* Now see if there's a reachable block with an exceptional incoming | |
672 | edge. */ | |
673 | FOR_EACH_BB (bb) | |
674 | if (bb->flags & BB_REACHABLE) | |
675 | FOR_EACH_EDGE (e, ei, bb->preds) | |
676 | if (e->flags & EDGE_ABNORMAL) | |
677 | return true; | |
678 | ||
679 | /* No exceptional block reached exit unexceptionally. */ | |
680 | return false; | |
681 | } | |
682 | ||
03acd8f8 | 683 | \f |
1e5bd841 BS |
684 | /* Global variables used by reload and its subroutines. */ |
685 | ||
1e5bd841 BS |
686 | /* Set during calculate_needs if an insn needs register elimination. */ |
687 | static int something_needs_elimination; | |
cb2afeb3 | 688 | /* Set during calculate_needs if an insn needs an operand changed. */ |
cf0fa607 | 689 | static int something_needs_operands_changed; |
1e5bd841 | 690 | |
1e5bd841 BS |
691 | /* Nonzero means we couldn't get enough spill regs. */ |
692 | static int failure; | |
693 | ||
058e97ec VM |
694 | /* Temporary array of pseudo-register number. */ |
695 | static int *temp_pseudo_reg_arr; | |
696 | ||
546b63fb | 697 | /* Main entry point for the reload pass. |
32131a9c RK |
698 | |
699 | FIRST is the first insn of the function being compiled. | |
700 | ||
701 | GLOBAL nonzero means we were called from global_alloc | |
702 | and should attempt to reallocate any pseudoregs that we | |
703 | displace from hard regs we will use for reloads. | |
704 | If GLOBAL is zero, we do not have enough information to do that, | |
705 | so any pseudo reg that is spilled must go to the stack. | |
706 | ||
5352b11a RS |
707 | Return value is nonzero if reload failed |
708 | and we must not do any more for this function. */ | |
709 | ||
710 | int | |
0c20a65f | 711 | reload (rtx first, int global) |
32131a9c | 712 | { |
058e97ec | 713 | int i, n; |
ba4807a0 | 714 | rtx insn; |
b3694847 | 715 | struct elim_table *ep; |
e0082a72 | 716 | basic_block bb; |
32131a9c | 717 | |
32131a9c RK |
718 | /* Make sure even insns with volatile mem refs are recognizable. */ |
719 | init_recog (); | |
720 | ||
1e5bd841 BS |
721 | failure = 0; |
722 | ||
1634b18f | 723 | reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0); |
cad6f7d0 | 724 | |
437a710d BS |
725 | /* Make sure that the last insn in the chain |
726 | is not something that needs reloading. */ | |
2e040219 | 727 | emit_note (NOTE_INSN_DELETED); |
437a710d | 728 | |
32131a9c RK |
729 | /* Enable find_equiv_reg to distinguish insns made by reload. */ |
730 | reload_first_uid = get_max_uid (); | |
731 | ||
0dadecf6 RK |
732 | #ifdef SECONDARY_MEMORY_NEEDED |
733 | /* Initialize the secondary memory table. */ | |
734 | clear_secondary_mem (); | |
735 | #endif | |
736 | ||
32131a9c | 737 | /* We don't have a stack slot for any spill reg yet. */ |
703ad42b KG |
738 | memset (spill_stack_slot, 0, sizeof spill_stack_slot); |
739 | memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width); | |
32131a9c | 740 | |
a8efe40d RK |
741 | /* Initialize the save area information for caller-save, in case some |
742 | are needed. */ | |
743 | init_save_areas (); | |
a8fdc208 | 744 | |
32131a9c RK |
745 | /* Compute which hard registers are now in use |
746 | as homes for pseudo registers. | |
747 | This is done here rather than (eg) in global_alloc | |
748 | because this point is reached even if not optimizing. */ | |
32131a9c RK |
749 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
750 | mark_home_live (i); | |
751 | ||
ecaebb9e NS |
752 | /* A function that has a nonlocal label that can reach the exit |
753 | block via non-exceptional paths must save all call-saved | |
8dddd002 | 754 | registers. */ |
e3b5732b | 755 | if (cfun->has_nonlocal_label |
215161e2 | 756 | && has_nonexceptional_receiver ()) |
e3b5732b | 757 | crtl->saves_all_registers = 1; |
215161e2 | 758 | |
e3b5732b | 759 | if (crtl->saves_all_registers) |
8dddd002 | 760 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
2a3e384f | 761 | if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) |
6fb5fa3c | 762 | df_set_regs_ever_live (i, true); |
8dddd002 | 763 | |
32131a9c RK |
764 | /* Find all the pseudo registers that didn't get hard regs |
765 | but do have known equivalent constants or memory slots. | |
766 | These include parameters (known equivalent to parameter slots) | |
767 | and cse'd or loop-moved constant memory addresses. | |
768 | ||
769 | Record constant equivalents in reg_equiv_constant | |
770 | so they will be substituted by find_reloads. | |
771 | Record memory equivalents in reg_mem_equiv so they can | |
772 | be substituted eventually by altering the REG-rtx's. */ | |
773 | ||
5ed6ace5 MD |
774 | reg_equiv_constant = XCNEWVEC (rtx, max_regno); |
775 | reg_equiv_invariant = XCNEWVEC (rtx, max_regno); | |
776 | reg_equiv_mem = XCNEWVEC (rtx, max_regno); | |
3f1e3e70 | 777 | reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno); |
5ed6ace5 MD |
778 | reg_equiv_address = XCNEWVEC (rtx, max_regno); |
779 | reg_max_ref_width = XCNEWVEC (unsigned int, max_regno); | |
780 | reg_old_renumber = XCNEWVEC (short, max_regno); | |
4e135bdd | 781 | memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short)); |
5ed6ace5 MD |
782 | pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno); |
783 | pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno); | |
32131a9c | 784 | |
03acd8f8 | 785 | CLEAR_HARD_REG_SET (bad_spill_regs_global); |
56f58d3a | 786 | |
d754127f ILT |
787 | /* Look for REG_EQUIV notes; record what each pseudo is equivalent |
788 | to. Also find all paradoxical subregs and find largest such for | |
789 | each pseudo. */ | |
32131a9c | 790 | |
2b49ee39 | 791 | num_eliminable_invariants = 0; |
32131a9c RK |
792 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
793 | { | |
794 | rtx set = single_set (insn); | |
795 | ||
3d17d93d AO |
796 | /* We may introduce USEs that we want to remove at the end, so |
797 | we'll mark them with QImode. Make sure there are no | |
798 | previously-marked insns left by say regmove. */ | |
799 | if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE | |
800 | && GET_MODE (insn) != VOIDmode) | |
801 | PUT_MODE (insn, VOIDmode); | |
802 | ||
d7f88d86 BS |
803 | if (INSN_P (insn)) |
804 | scan_paradoxical_subregs (PATTERN (insn)); | |
805 | ||
f8cfc6aa | 806 | if (set != 0 && REG_P (SET_DEST (set))) |
32131a9c | 807 | { |
fb3821f7 | 808 | rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
d7f88d86 BS |
809 | rtx x; |
810 | ||
811 | if (! note) | |
812 | continue; | |
813 | ||
814 | i = REGNO (SET_DEST (set)); | |
815 | x = XEXP (note, 0); | |
816 | ||
817 | if (i <= LAST_VIRTUAL_REGISTER) | |
818 | continue; | |
819 | ||
820 | if (! function_invariant_p (x) | |
821 | || ! flag_pic | |
822 | /* A function invariant is often CONSTANT_P but may | |
823 | include a register. We promise to only pass | |
824 | CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ | |
825 | || (CONSTANT_P (x) | |
826 | && LEGITIMATE_PIC_OPERAND_P (x))) | |
32131a9c | 827 | { |
d7f88d86 BS |
828 | /* It can happen that a REG_EQUIV note contains a MEM |
829 | that is not a legitimate memory operand. As later | |
830 | stages of reload assume that all addresses found | |
831 | in the reg_equiv_* arrays were originally legitimate, | |
832 | we ignore such REG_EQUIV notes. */ | |
833 | if (memory_operand (x, VOIDmode)) | |
32131a9c | 834 | { |
d7f88d86 BS |
835 | /* Always unshare the equivalence, so we can |
836 | substitute into this insn without touching the | |
837 | equivalence. */ | |
838 | reg_equiv_memory_loc[i] = copy_rtx (x); | |
839 | } | |
840 | else if (function_invariant_p (x)) | |
841 | { | |
842 | if (GET_CODE (x) == PLUS) | |
956d6950 | 843 | { |
d7f88d86 BS |
844 | /* This is PLUS of frame pointer and a constant, |
845 | and might be shared. Unshare it. */ | |
ab156144 | 846 | reg_equiv_invariant[i] = copy_rtx (x); |
d7f88d86 | 847 | num_eliminable_invariants++; |
956d6950 | 848 | } |
ab156144 | 849 | else if (x == frame_pointer_rtx || x == arg_pointer_rtx) |
32131a9c | 850 | { |
ab156144 | 851 | reg_equiv_invariant[i] = x; |
d7f88d86 | 852 | num_eliminable_invariants++; |
32131a9c | 853 | } |
d7f88d86 BS |
854 | else if (LEGITIMATE_CONSTANT_P (x)) |
855 | reg_equiv_constant[i] = x; | |
32131a9c | 856 | else |
d7f88d86 BS |
857 | { |
858 | reg_equiv_memory_loc[i] | |
859 | = force_const_mem (GET_MODE (SET_DEST (set)), x); | |
860 | if (! reg_equiv_memory_loc[i]) | |
861 | reg_equiv_init[i] = NULL_RTX; | |
862 | } | |
863 | } | |
864 | else | |
865 | { | |
866 | reg_equiv_init[i] = NULL_RTX; | |
867 | continue; | |
32131a9c RK |
868 | } |
869 | } | |
d7f88d86 BS |
870 | else |
871 | reg_equiv_init[i] = NULL_RTX; | |
32131a9c | 872 | } |
32131a9c RK |
873 | } |
874 | ||
d7f88d86 BS |
875 | if (dump_file) |
876 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
877 | if (reg_equiv_init[i]) | |
878 | { | |
879 | fprintf (dump_file, "init_insns for %u: ", i); | |
880 | print_inline_rtx (dump_file, reg_equiv_init[i], 20); | |
881 | fprintf (dump_file, "\n"); | |
882 | } | |
883 | ||
09dd1133 | 884 | init_elim_table (); |
32131a9c | 885 | |
4cc0fdd2 JDA |
886 | first_label_num = get_first_label_num (); |
887 | num_labels = max_label_num () - first_label_num; | |
32131a9c RK |
888 | |
889 | /* Allocate the tables used to store offset information at labels. */ | |
a68d4b75 BK |
890 | /* We used to use alloca here, but the size of what it would try to |
891 | allocate would occasionally cause it to exceed the stack limit and | |
892 | cause a core dump. */ | |
5ed6ace5 MD |
893 | offsets_known_at = XNEWVEC (char, num_labels); |
894 | offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT)); | |
32131a9c | 895 | |
058e97ec VM |
896 | /* Alter each pseudo-reg rtx to contain its hard reg number. Assign |
897 | stack slots to the pseudos that lack hard regs or equivalents. | |
32131a9c RK |
898 | Do not touch virtual registers. */ |
899 | ||
058e97ec VM |
900 | temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1); |
901 | for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) | |
902 | temp_pseudo_reg_arr[n++] = i; | |
903 | ||
2af2dbdc | 904 | if (ira_conflicts_p) |
058e97ec VM |
905 | /* Ask IRA to order pseudo-registers for better stack slot |
906 | sharing. */ | |
907 | ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width); | |
908 | ||
909 | for (i = 0; i < n; i++) | |
910 | alter_reg (temp_pseudo_reg_arr[i], -1, false); | |
32131a9c | 911 | |
32131a9c RK |
912 | /* If we have some registers we think can be eliminated, scan all insns to |
913 | see if there is an insn that sets one of these registers to something | |
914 | other than itself plus a constant. If so, the register cannot be | |
915 | eliminated. Doing this scan here eliminates an extra pass through the | |
916 | main reload loop in the most common case where register elimination | |
917 | cannot be done. */ | |
918 | for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) | |
4b4bf941 | 919 | if (INSN_P (insn)) |
84832317 | 920 | note_stores (PATTERN (insn), mark_not_eliminable, NULL); |
32131a9c | 921 | |
18a90182 BS |
922 | maybe_fix_stack_asms (); |
923 | ||
03acd8f8 BS |
924 | insns_need_reload = 0; |
925 | something_needs_elimination = 0; | |
05d10675 | 926 | |
4079cd63 JW |
927 | /* Initialize to -1, which means take the first spill register. */ |
928 | last_spill_reg = -1; | |
929 | ||
32131a9c | 930 | /* Spill any hard regs that we know we can't eliminate. */ |
03acd8f8 | 931 | CLEAR_HARD_REG_SET (used_spill_regs); |
4ab51fb5 R |
932 | /* There can be multiple ways to eliminate a register; |
933 | they should be listed adjacently. | |
934 | Elimination for any register fails only if all possible ways fail. */ | |
935 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ) | |
936 | { | |
937 | int from = ep->from; | |
938 | int can_eliminate = 0; | |
939 | do | |
940 | { | |
941 | can_eliminate |= ep->can_eliminate; | |
942 | ep++; | |
943 | } | |
944 | while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from); | |
945 | if (! can_eliminate) | |
946 | spill_hard_reg (from, 1); | |
947 | } | |
9ff3516a RK |
948 | |
949 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
950 | if (frame_pointer_needed) | |
e04ca094 | 951 | spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1); |
9ff3516a | 952 | #endif |
e04ca094 | 953 | finish_spills (global); |
7609e720 | 954 | |
f1db3576 JL |
955 | /* From now on, we may need to generate moves differently. We may also |
956 | allow modifications of insns which cause them to not be recognized. | |
957 | Any such modifications will be cleaned up during reload itself. */ | |
b2f15f94 RK |
958 | reload_in_progress = 1; |
959 | ||
32131a9c RK |
960 | /* This loop scans the entire function each go-round |
961 | and repeats until one repetition spills no additional hard regs. */ | |
03acd8f8 | 962 | for (;;) |
32131a9c | 963 | { |
03acd8f8 BS |
964 | int something_changed; |
965 | int did_spill; | |
03acd8f8 | 966 | HOST_WIDE_INT starting_frame_size; |
32131a9c | 967 | |
7657bf2f JW |
968 | starting_frame_size = get_frame_size (); |
969 | ||
09dd1133 | 970 | set_initial_elim_offsets (); |
1f3b1e1a | 971 | set_initial_label_offsets (); |
03acd8f8 | 972 | |
32131a9c RK |
973 | /* For each pseudo register that has an equivalent location defined, |
974 | try to eliminate any eliminable registers (such as the frame pointer) | |
975 | assuming initial offsets for the replacement register, which | |
976 | is the normal case. | |
977 | ||
978 | If the resulting location is directly addressable, substitute | |
979 | the MEM we just got directly for the old REG. | |
980 | ||
981 | If it is not addressable but is a constant or the sum of a hard reg | |
982 | and constant, it is probably not addressable because the constant is | |
983 | out of range, in that case record the address; we will generate | |
984 | hairy code to compute the address in a register each time it is | |
6491dbbb RK |
985 | needed. Similarly if it is a hard register, but one that is not |
986 | valid as an address register. | |
32131a9c RK |
987 | |
988 | If the location is not addressable, but does not have one of the | |
989 | above forms, assign a stack slot. We have to do this to avoid the | |
990 | potential of producing lots of reloads if, e.g., a location involves | |
991 | a pseudo that didn't get a hard register and has an equivalent memory | |
992 | location that also involves a pseudo that didn't get a hard register. | |
993 | ||
994 | Perhaps at some point we will improve reload_when_needed handling | |
995 | so this problem goes away. But that's very hairy. */ | |
996 | ||
997 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
998 | if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) | |
999 | { | |
1914f5da | 1000 | rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX); |
32131a9c RK |
1001 | |
1002 | if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]), | |
1003 | XEXP (x, 0))) | |
1004 | reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; | |
1f663989 | 1005 | else if (CONSTANT_P (XEXP (x, 0)) |
f8cfc6aa | 1006 | || (REG_P (XEXP (x, 0)) |
6491dbbb | 1007 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) |
32131a9c | 1008 | || (GET_CODE (XEXP (x, 0)) == PLUS |
f8cfc6aa | 1009 | && REG_P (XEXP (XEXP (x, 0), 0)) |
32131a9c RK |
1010 | && (REGNO (XEXP (XEXP (x, 0), 0)) |
1011 | < FIRST_PSEUDO_REGISTER) | |
1f663989 | 1012 | && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) |
32131a9c RK |
1013 | reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; |
1014 | else | |
1015 | { | |
1016 | /* Make a new stack slot. Then indicate that something | |
a8fdc208 | 1017 | changed so we go back and recompute offsets for |
32131a9c RK |
1018 | eliminable registers because the allocation of memory |
1019 | below might change some offset. reg_equiv_{mem,address} | |
1020 | will be set up for this pseudo on the next pass around | |
1021 | the loop. */ | |
1022 | reg_equiv_memory_loc[i] = 0; | |
1023 | reg_equiv_init[i] = 0; | |
058e97ec | 1024 | alter_reg (i, -1, true); |
32131a9c RK |
1025 | } |
1026 | } | |
a8fdc208 | 1027 | |
437a710d BS |
1028 | if (caller_save_needed) |
1029 | setup_save_areas (); | |
1030 | ||
03acd8f8 | 1031 | /* If we allocated another stack slot, redo elimination bookkeeping. */ |
437a710d | 1032 | if (starting_frame_size != get_frame_size ()) |
32131a9c | 1033 | continue; |
cb91fab0 | 1034 | if (starting_frame_size && crtl->stack_alignment_needed) |
970af867 NS |
1035 | { |
1036 | /* If we have a stack frame, we must align it now. The | |
1037 | stack size may be a part of the offset computation for | |
1038 | register elimination. So if this changes the stack size, | |
1039 | then repeat the elimination bookkeeping. We don't | |
1040 | realign when there is no stack, as that will cause a | |
1041 | stack frame when none is needed should | |
1042 | STARTING_FRAME_OFFSET not be already aligned to | |
1043 | STACK_BOUNDARY. */ | |
cb91fab0 | 1044 | assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed); |
970af867 NS |
1045 | if (starting_frame_size != get_frame_size ()) |
1046 | continue; | |
1047 | } | |
32131a9c | 1048 | |
437a710d | 1049 | if (caller_save_needed) |
a8efe40d | 1050 | { |
437a710d BS |
1051 | save_call_clobbered_regs (); |
1052 | /* That might have allocated new insn_chain structures. */ | |
1634b18f | 1053 | reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0); |
a8efe40d RK |
1054 | } |
1055 | ||
03acd8f8 BS |
1056 | calculate_needs_all_insns (global); |
1057 | ||
2af2dbdc | 1058 | if (! ira_conflicts_p) |
058e97ec VM |
1059 | /* Don't do it for IRA. We need this info because we don't |
1060 | change live_throughout and dead_or_set for chains when IRA | |
1061 | is used. */ | |
1062 | CLEAR_REG_SET (&spilled_pseudos); | |
1063 | ||
03acd8f8 BS |
1064 | did_spill = 0; |
1065 | ||
1066 | something_changed = 0; | |
32131a9c | 1067 | |
0dadecf6 RK |
1068 | /* If we allocated any new memory locations, make another pass |
1069 | since it might have changed elimination offsets. */ | |
1070 | if (starting_frame_size != get_frame_size ()) | |
1071 | something_changed = 1; | |
1072 | ||
9f938de1 UW |
1073 | /* Even if the frame size remained the same, we might still have |
1074 | changed elimination offsets, e.g. if find_reloads called | |
1075 | force_const_mem requiring the back end to allocate a constant | |
1076 | pool base register that needs to be saved on the stack. */ | |
1077 | else if (!verify_initial_elim_offsets ()) | |
1078 | something_changed = 1; | |
1079 | ||
09dd1133 BS |
1080 | { |
1081 | HARD_REG_SET to_spill; | |
1082 | CLEAR_HARD_REG_SET (to_spill); | |
1083 | update_eliminables (&to_spill); | |
247140ea | 1084 | AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill); |
184f4c56 | 1085 | |
09dd1133 BS |
1086 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1087 | if (TEST_HARD_REG_BIT (to_spill, i)) | |
32131a9c | 1088 | { |
e04ca094 | 1089 | spill_hard_reg (i, 1); |
03acd8f8 | 1090 | did_spill = 1; |
8f5db3c1 JL |
1091 | |
1092 | /* Regardless of the state of spills, if we previously had | |
e591c83d | 1093 | a register that we thought we could eliminate, but now can |
8f5db3c1 JL |
1094 | not eliminate, we must run another pass. |
1095 | ||
1096 | Consider pseudos which have an entry in reg_equiv_* which | |
1097 | reference an eliminable register. We must make another pass | |
1098 | to update reg_equiv_* so that we do not substitute in the | |
1099 | old value from when we thought the elimination could be | |
1100 | performed. */ | |
1101 | something_changed = 1; | |
32131a9c | 1102 | } |
09dd1133 | 1103 | } |
9ff3516a | 1104 | |
e04ca094 | 1105 | select_reload_regs (); |
e483bf9c BS |
1106 | if (failure) |
1107 | goto failed; | |
437a710d | 1108 | |
e483bf9c | 1109 | if (insns_need_reload != 0 || did_spill) |
e04ca094 | 1110 | something_changed |= finish_spills (global); |
7609e720 | 1111 | |
03acd8f8 BS |
1112 | if (! something_changed) |
1113 | break; | |
1114 | ||
1115 | if (caller_save_needed) | |
7609e720 | 1116 | delete_caller_save_insns (); |
f5d8c9f4 BS |
1117 | |
1118 | obstack_free (&reload_obstack, reload_firstobj); | |
32131a9c RK |
1119 | } |
1120 | ||
1121 | /* If global-alloc was run, notify it of any register eliminations we have | |
1122 | done. */ | |
1123 | if (global) | |
1124 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1125 | if (ep->can_eliminate) | |
1126 | mark_elimination (ep->from, ep->to); | |
1127 | ||
32131a9c RK |
1128 | /* If a pseudo has no hard reg, delete the insns that made the equivalence. |
1129 | If that insn didn't set the register (i.e., it copied the register to | |
1130 | memory), just delete that insn instead of the equivalencing insn plus | |
1131 | anything now dead. If we call delete_dead_insn on that insn, we may | |
135eb61c | 1132 | delete the insn that actually sets the register if the register dies |
32131a9c RK |
1133 | there and that is incorrect. */ |
1134 | ||
1135 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
135eb61c R |
1136 | { |
1137 | if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0) | |
1138 | { | |
1139 | rtx list; | |
1140 | for (list = reg_equiv_init[i]; list; list = XEXP (list, 1)) | |
1141 | { | |
1142 | rtx equiv_insn = XEXP (list, 0); | |
78571511 RK |
1143 | |
1144 | /* If we already deleted the insn or if it may trap, we can't | |
1145 | delete it. The latter case shouldn't happen, but can | |
1146 | if an insn has a variable address, gets a REG_EH_REGION | |
569b7f6a | 1147 | note added to it, and then gets converted into a load |
78571511 | 1148 | from a constant address. */ |
4b4bf941 | 1149 | if (NOTE_P (equiv_insn) |
78571511 RK |
1150 | || can_throw_internal (equiv_insn)) |
1151 | ; | |
1152 | else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn))) | |
135eb61c R |
1153 | delete_dead_insn (equiv_insn); |
1154 | else | |
6773e15f | 1155 | SET_INSN_DELETED (equiv_insn); |
135eb61c R |
1156 | } |
1157 | } | |
1158 | } | |
32131a9c RK |
1159 | |
1160 | /* Use the reload registers where necessary | |
1161 | by generating move instructions to move the must-be-register | |
1162 | values into or out of the reload registers. */ | |
1163 | ||
03acd8f8 BS |
1164 | if (insns_need_reload != 0 || something_needs_elimination |
1165 | || something_needs_operands_changed) | |
c47f5ea5 | 1166 | { |
102870fb | 1167 | HOST_WIDE_INT old_frame_size = get_frame_size (); |
c47f5ea5 | 1168 | |
e04ca094 | 1169 | reload_as_needed (global); |
c47f5ea5 | 1170 | |
41374e13 | 1171 | gcc_assert (old_frame_size == get_frame_size ()); |
c47f5ea5 | 1172 | |
9f938de1 | 1173 | gcc_assert (verify_initial_elim_offsets ()); |
c47f5ea5 | 1174 | } |
32131a9c | 1175 | |
2a1f8b6b | 1176 | /* If we were able to eliminate the frame pointer, show that it is no |
546b63fb | 1177 | longer live at the start of any basic block. If it ls live by |
2a1f8b6b RK |
1178 | virtue of being in a pseudo, that pseudo will be marked live |
1179 | and hence the frame pointer will be known to be live via that | |
1180 | pseudo. */ | |
1181 | ||
1182 | if (! frame_pointer_needed) | |
e0082a72 | 1183 | FOR_EACH_BB (bb) |
ba49cb7b | 1184 | bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM); |
6fb5fa3c | 1185 | |
0e61db61 NS |
1186 | /* Come here (with failure set nonzero) if we can't get enough spill |
1187 | regs. */ | |
5352b11a RS |
1188 | failed: |
1189 | ||
058e97ec | 1190 | CLEAR_REG_SET (&changed_allocation_pseudos); |
f5d8c9f4 | 1191 | CLEAR_REG_SET (&spilled_pseudos); |
a3ec87a8 RS |
1192 | reload_in_progress = 0; |
1193 | ||
32131a9c RK |
1194 | /* Now eliminate all pseudo regs by modifying them into |
1195 | their equivalent memory references. | |
1196 | The REG-rtx's for the pseudos are modified in place, | |
1197 | so all insns that used to refer to them now refer to memory. | |
1198 | ||
1199 | For a reg that has a reg_equiv_address, all those insns | |
1200 | were changed by reloading so that no insns refer to it any longer; | |
1201 | but the DECL_RTL of a variable decl may refer to it, | |
1202 | and if so this causes the debugging info to mention the variable. */ | |
1203 | ||
1204 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1205 | { | |
1206 | rtx addr = 0; | |
9ec36da5 JL |
1207 | |
1208 | if (reg_equiv_mem[i]) | |
1209 | addr = XEXP (reg_equiv_mem[i], 0); | |
1210 | ||
32131a9c RK |
1211 | if (reg_equiv_address[i]) |
1212 | addr = reg_equiv_address[i]; | |
9ec36da5 | 1213 | |
32131a9c RK |
1214 | if (addr) |
1215 | { | |
1216 | if (reg_renumber[i] < 0) | |
1217 | { | |
1218 | rtx reg = regno_reg_rtx[i]; | |
173b24b9 | 1219 | |
5a63e069 | 1220 | REG_USERVAR_P (reg) = 0; |
ef178af3 | 1221 | PUT_CODE (reg, MEM); |
32131a9c | 1222 | XEXP (reg, 0) = addr; |
173b24b9 RK |
1223 | if (reg_equiv_memory_loc[i]) |
1224 | MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]); | |
1225 | else | |
1226 | { | |
389fdba0 | 1227 | MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0; |
173b24b9 RK |
1228 | MEM_ATTRS (reg) = 0; |
1229 | } | |
be0c514c | 1230 | MEM_NOTRAP_P (reg) = 1; |
32131a9c RK |
1231 | } |
1232 | else if (reg_equiv_mem[i]) | |
1233 | XEXP (reg_equiv_mem[i], 0) = addr; | |
1234 | } | |
1235 | } | |
1236 | ||
2ae74651 JL |
1237 | /* We must set reload_completed now since the cleanup_subreg_operands call |
1238 | below will re-recognize each insn and reload may have generated insns | |
1239 | which are only valid during and after reload. */ | |
1240 | reload_completed = 1; | |
1241 | ||
bd695e1e RH |
1242 | /* Make a pass over all the insns and delete all USEs which we inserted |
1243 | only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED | |
41e34bab DJ |
1244 | notes. Delete all CLOBBER insns, except those that refer to the return |
1245 | value and the special mem:BLK CLOBBERs added to prevent the scheduler | |
1246 | from misarranging variable-array code, and simplify (subreg (reg)) | |
4a8cae83 SB |
1247 | operands. Strip and regenerate REG_INC notes that may have been moved |
1248 | around. */ | |
32131a9c | 1249 | |
ba4807a0 LB |
1250 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
1251 | if (INSN_P (insn)) | |
1252 | { | |
1253 | rtx *pnote; | |
1254 | ||
1255 | if (CALL_P (insn)) | |
1256 | replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn), | |
1257 | VOIDmode, CALL_INSN_FUNCTION_USAGE (insn)); | |
1258 | ||
1259 | if ((GET_CODE (PATTERN (insn)) == USE | |
1260 | /* We mark with QImode USEs introduced by reload itself. */ | |
1261 | && (GET_MODE (insn) == QImode | |
1262 | || find_reg_note (insn, REG_EQUAL, NULL_RTX))) | |
1263 | || (GET_CODE (PATTERN (insn)) == CLOBBER | |
1264 | && (!MEM_P (XEXP (PATTERN (insn), 0)) | |
1265 | || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode | |
1266 | || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH | |
1267 | && XEXP (XEXP (PATTERN (insn), 0), 0) | |
1268 | != stack_pointer_rtx)) | |
1269 | && (!REG_P (XEXP (PATTERN (insn), 0)) | |
1270 | || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0))))) | |
1271 | { | |
1272 | delete_insn (insn); | |
1273 | continue; | |
1274 | } | |
1275 | ||
1276 | /* Some CLOBBERs may survive until here and still reference unassigned | |
1277 | pseudos with const equivalent, which may in turn cause ICE in later | |
1278 | passes if the reference remains in place. */ | |
1279 | if (GET_CODE (PATTERN (insn)) == CLOBBER) | |
1280 | replace_pseudos_in (& XEXP (PATTERN (insn), 0), | |
1281 | VOIDmode, PATTERN (insn)); | |
1282 | ||
1283 | /* Discard obvious no-ops, even without -O. This optimization | |
1284 | is fast and doesn't interfere with debugging. */ | |
1285 | if (NONJUMP_INSN_P (insn) | |
1286 | && GET_CODE (PATTERN (insn)) == SET | |
1287 | && REG_P (SET_SRC (PATTERN (insn))) | |
1288 | && REG_P (SET_DEST (PATTERN (insn))) | |
1289 | && (REGNO (SET_SRC (PATTERN (insn))) | |
1290 | == REGNO (SET_DEST (PATTERN (insn))))) | |
1291 | { | |
1292 | delete_insn (insn); | |
1293 | continue; | |
1294 | } | |
1295 | ||
1296 | pnote = ®_NOTES (insn); | |
1297 | while (*pnote != 0) | |
1298 | { | |
1299 | if (REG_NOTE_KIND (*pnote) == REG_DEAD | |
1300 | || REG_NOTE_KIND (*pnote) == REG_UNUSED | |
4a8cae83 | 1301 | || REG_NOTE_KIND (*pnote) == REG_INC) |
ba4807a0 LB |
1302 | *pnote = XEXP (*pnote, 1); |
1303 | else | |
1304 | pnote = &XEXP (*pnote, 1); | |
1305 | } | |
0304f787 | 1306 | |
2dfa9a87 | 1307 | #ifdef AUTO_INC_DEC |
ba4807a0 | 1308 | add_auto_inc_notes (insn, PATTERN (insn)); |
2dfa9a87 MH |
1309 | #endif |
1310 | ||
ba4807a0 LB |
1311 | /* Simplify (subreg (reg)) if it appears as an operand. */ |
1312 | cleanup_subreg_operands (insn); | |
1313 | ||
1314 | /* Clean up invalid ASMs so that they don't confuse later passes. | |
1315 | See PR 21299. */ | |
1316 | if (asm_noperands (PATTERN (insn)) >= 0) | |
1317 | { | |
1318 | extract_insn (insn); | |
1319 | if (!constrain_operands (1)) | |
1320 | { | |
1321 | error_for_asm (insn, | |
1322 | "%<asm%> operand has impossible constraints"); | |
1323 | delete_insn (insn); | |
1324 | continue; | |
1325 | } | |
1326 | } | |
1327 | } | |
32131a9c | 1328 | |
b38f3813 EB |
1329 | /* If we are doing generic stack checking, give a warning if this |
1330 | function's frame size is larger than we expect. */ | |
1331 | if (flag_stack_check == GENERIC_STACK_CHECK) | |
ab87f8c8 JL |
1332 | { |
1333 | HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; | |
05d10675 BS |
1334 | static int verbose_warned = 0; |
1335 | ||
ab87f8c8 | 1336 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
6fb5fa3c | 1337 | if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i]) |
ab87f8c8 JL |
1338 | size += UNITS_PER_WORD; |
1339 | ||
1340 | if (size > STACK_CHECK_MAX_FRAME_SIZE) | |
05d10675 | 1341 | { |
d4ee4d25 | 1342 | warning (0, "frame size too large for reliable stack checking"); |
ab87f8c8 JL |
1343 | if (! verbose_warned) |
1344 | { | |
d4ee4d25 | 1345 | warning (0, "try reducing the number of local variables"); |
ab87f8c8 JL |
1346 | verbose_warned = 1; |
1347 | } | |
1348 | } | |
1349 | } | |
1350 | ||
32131a9c | 1351 | /* Indicate that we no longer have known memory locations or constants. */ |
58d9f9d9 JL |
1352 | if (reg_equiv_constant) |
1353 | free (reg_equiv_constant); | |
ab156144 RH |
1354 | if (reg_equiv_invariant) |
1355 | free (reg_equiv_invariant); | |
32131a9c | 1356 | reg_equiv_constant = 0; |
ab156144 | 1357 | reg_equiv_invariant = 0; |
43b373a2 | 1358 | VEC_free (rtx, gc, reg_equiv_memory_loc_vec); |
32131a9c | 1359 | reg_equiv_memory_loc = 0; |
5352b11a | 1360 | |
058e97ec VM |
1361 | free (temp_pseudo_reg_arr); |
1362 | ||
4cc0fdd2 JDA |
1363 | if (offsets_known_at) |
1364 | free (offsets_known_at); | |
1365 | if (offsets_at) | |
1366 | free (offsets_at); | |
a68d4b75 | 1367 | |
3f1e3e70 AO |
1368 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1369 | if (reg_equiv_alt_mem_list[i]) | |
1370 | free_EXPR_LIST_list (®_equiv_alt_mem_list[i]); | |
1371 | free (reg_equiv_alt_mem_list); | |
1372 | ||
56a65848 | 1373 | free (reg_equiv_mem); |
d7f88d86 | 1374 | reg_equiv_init = 0; |
56a65848 DB |
1375 | free (reg_equiv_address); |
1376 | free (reg_max_ref_width); | |
03acd8f8 BS |
1377 | free (reg_old_renumber); |
1378 | free (pseudo_previous_regs); | |
1379 | free (pseudo_forbidden_regs); | |
56a65848 | 1380 | |
8b4f9969 JW |
1381 | CLEAR_HARD_REG_SET (used_spill_regs); |
1382 | for (i = 0; i < n_spills; i++) | |
1383 | SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]); | |
1384 | ||
7609e720 BS |
1385 | /* Free all the insn_chain structures at once. */ |
1386 | obstack_free (&reload_obstack, reload_startobj); | |
1387 | unused_insn_chains = 0; | |
f1330226 | 1388 | fixup_abnormal_edges (); |
7609e720 | 1389 | |
e16e3291 UW |
1390 | /* Replacing pseudos with their memory equivalents might have |
1391 | created shared rtx. Subsequent passes would get confused | |
1392 | by this, so unshare everything here. */ | |
1393 | unshare_all_rtl_again (first); | |
1394 | ||
b483cfb7 EB |
1395 | #ifdef STACK_BOUNDARY |
1396 | /* init_emit has set the alignment of the hard frame pointer | |
1397 | to STACK_BOUNDARY. It is very likely no longer valid if | |
1398 | the hard frame pointer was used for register allocation. */ | |
1399 | if (!frame_pointer_needed) | |
1400 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; | |
1401 | #endif | |
1402 | ||
5352b11a | 1403 | return failure; |
32131a9c | 1404 | } |
1e5bd841 | 1405 | |
18a90182 BS |
1406 | /* Yet another special case. Unfortunately, reg-stack forces people to |
1407 | write incorrect clobbers in asm statements. These clobbers must not | |
1408 | cause the register to appear in bad_spill_regs, otherwise we'll call | |
1409 | fatal_insn later. We clear the corresponding regnos in the live | |
1410 | register sets to avoid this. | |
1411 | The whole thing is rather sick, I'm afraid. */ | |
efc9bd41 | 1412 | |
18a90182 | 1413 | static void |
0c20a65f | 1414 | maybe_fix_stack_asms (void) |
18a90182 BS |
1415 | { |
1416 | #ifdef STACK_REGS | |
392dccb7 | 1417 | const char *constraints[MAX_RECOG_OPERANDS]; |
18a90182 BS |
1418 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
1419 | struct insn_chain *chain; | |
1420 | ||
1421 | for (chain = reload_insn_chain; chain != 0; chain = chain->next) | |
1422 | { | |
1423 | int i, noperands; | |
1424 | HARD_REG_SET clobbered, allowed; | |
1425 | rtx pat; | |
1426 | ||
2c3c49de | 1427 | if (! INSN_P (chain->insn) |
18a90182 BS |
1428 | || (noperands = asm_noperands (PATTERN (chain->insn))) < 0) |
1429 | continue; | |
1430 | pat = PATTERN (chain->insn); | |
1431 | if (GET_CODE (pat) != PARALLEL) | |
1432 | continue; | |
1433 | ||
1434 | CLEAR_HARD_REG_SET (clobbered); | |
1435 | CLEAR_HARD_REG_SET (allowed); | |
1436 | ||
1437 | /* First, make a mask of all stack regs that are clobbered. */ | |
1438 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
1439 | { | |
1440 | rtx t = XVECEXP (pat, 0, i); | |
1441 | if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0))) | |
1442 | SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0))); | |
1443 | } | |
1444 | ||
1445 | /* Get the operand values and constraints out of the insn. */ | |
1ccbefce | 1446 | decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc, |
bff4b63d | 1447 | constraints, operand_mode, NULL); |
18a90182 BS |
1448 | |
1449 | /* For every operand, see what registers are allowed. */ | |
1450 | for (i = 0; i < noperands; i++) | |
1451 | { | |
6b9c6f4f | 1452 | const char *p = constraints[i]; |
18a90182 BS |
1453 | /* For every alternative, we compute the class of registers allowed |
1454 | for reloading in CLS, and merge its contents into the reg set | |
1455 | ALLOWED. */ | |
1456 | int cls = (int) NO_REGS; | |
1457 | ||
1458 | for (;;) | |
1459 | { | |
97488870 | 1460 | char c = *p; |
18a90182 BS |
1461 | |
1462 | if (c == '\0' || c == ',' || c == '#') | |
1463 | { | |
1464 | /* End of one alternative - mark the regs in the current | |
1465 | class, and reset the class. */ | |
1466 | IOR_HARD_REG_SET (allowed, reg_class_contents[cls]); | |
1467 | cls = NO_REGS; | |
97488870 | 1468 | p++; |
18a90182 BS |
1469 | if (c == '#') |
1470 | do { | |
1471 | c = *p++; | |
1472 | } while (c != '\0' && c != ','); | |
1473 | if (c == '\0') | |
1474 | break; | |
1475 | continue; | |
1476 | } | |
1477 | ||
1478 | switch (c) | |
1479 | { | |
1480 | case '=': case '+': case '*': case '%': case '?': case '!': | |
a4edaf83 AK |
1481 | case '0': case '1': case '2': case '3': case '4': case '<': |
1482 | case '>': case 'V': case 'o': case '&': case 'E': case 'F': | |
1483 | case 's': case 'i': case 'n': case 'X': case 'I': case 'J': | |
1484 | case 'K': case 'L': case 'M': case 'N': case 'O': case 'P': | |
1485 | case TARGET_MEM_CONSTRAINT: | |
18a90182 BS |
1486 | break; |
1487 | ||
1488 | case 'p': | |
3dcc68a4 | 1489 | cls = (int) reg_class_subunion[cls] |
c4963a0a | 1490 | [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; |
18a90182 BS |
1491 | break; |
1492 | ||
1493 | case 'g': | |
1494 | case 'r': | |
1495 | cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS]; | |
1496 | break; | |
1497 | ||
1498 | default: | |
97488870 | 1499 | if (EXTRA_ADDRESS_CONSTRAINT (c, p)) |
ccfc6cc8 | 1500 | cls = (int) reg_class_subunion[cls] |
c4963a0a | 1501 | [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; |
ccfc6cc8 UW |
1502 | else |
1503 | cls = (int) reg_class_subunion[cls] | |
97488870 | 1504 | [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]; |
18a90182 | 1505 | } |
97488870 | 1506 | p += CONSTRAINT_LEN (c, p); |
18a90182 BS |
1507 | } |
1508 | } | |
1509 | /* Those of the registers which are clobbered, but allowed by the | |
1510 | constraints, must be usable as reload registers. So clear them | |
1511 | out of the life information. */ | |
1512 | AND_HARD_REG_SET (allowed, clobbered); | |
1513 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1514 | if (TEST_HARD_REG_BIT (allowed, i)) | |
1515 | { | |
239a0f5b BS |
1516 | CLEAR_REGNO_REG_SET (&chain->live_throughout, i); |
1517 | CLEAR_REGNO_REG_SET (&chain->dead_or_set, i); | |
18a90182 BS |
1518 | } |
1519 | } | |
1520 | ||
1521 | #endif | |
1522 | } | |
03acd8f8 | 1523 | \f |
f5d8c9f4 BS |
1524 | /* Copy the global variables n_reloads and rld into the corresponding elts |
1525 | of CHAIN. */ | |
1526 | static void | |
0c20a65f | 1527 | copy_reloads (struct insn_chain *chain) |
f5d8c9f4 BS |
1528 | { |
1529 | chain->n_reloads = n_reloads; | |
1634b18f | 1530 | chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads); |
f5d8c9f4 | 1531 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); |
1634b18f | 1532 | reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0); |
f5d8c9f4 BS |
1533 | } |
1534 | ||
03acd8f8 BS |
1535 | /* Walk the chain of insns, and determine for each whether it needs reloads |
1536 | and/or eliminations. Build the corresponding insns_need_reload list, and | |
1537 | set something_needs_elimination as appropriate. */ | |
1538 | static void | |
0c20a65f | 1539 | calculate_needs_all_insns (int global) |
1e5bd841 | 1540 | { |
7609e720 | 1541 | struct insn_chain **pprev_reload = &insns_need_reload; |
462561b7 | 1542 | struct insn_chain *chain, *next = 0; |
1e5bd841 | 1543 | |
03acd8f8 BS |
1544 | something_needs_elimination = 0; |
1545 | ||
1634b18f | 1546 | reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0); |
462561b7 | 1547 | for (chain = reload_insn_chain; chain != 0; chain = next) |
1e5bd841 | 1548 | { |
67e61fe7 | 1549 | rtx insn = chain->insn; |
03acd8f8 | 1550 | |
462561b7 JJ |
1551 | next = chain->next; |
1552 | ||
f5d8c9f4 BS |
1553 | /* Clear out the shortcuts. */ |
1554 | chain->n_reloads = 0; | |
67e61fe7 BS |
1555 | chain->need_elim = 0; |
1556 | chain->need_reload = 0; | |
1557 | chain->need_operand_change = 0; | |
1e5bd841 | 1558 | |
03acd8f8 | 1559 | /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might |
cf7c4aa6 HPN |
1560 | include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see |
1561 | what effects this has on the known offsets at labels. */ | |
1e5bd841 | 1562 | |
4b4bf941 | 1563 | if (LABEL_P (insn) || JUMP_P (insn) |
2c3c49de | 1564 | || (INSN_P (insn) && REG_NOTES (insn) != 0)) |
1e5bd841 BS |
1565 | set_label_offsets (insn, insn, 0); |
1566 | ||
2c3c49de | 1567 | if (INSN_P (insn)) |
1e5bd841 BS |
1568 | { |
1569 | rtx old_body = PATTERN (insn); | |
1570 | int old_code = INSN_CODE (insn); | |
1571 | rtx old_notes = REG_NOTES (insn); | |
1572 | int did_elimination = 0; | |
cb2afeb3 | 1573 | int operands_changed = 0; |
2b49ee39 R |
1574 | rtx set = single_set (insn); |
1575 | ||
1576 | /* Skip insns that only set an equivalence. */ | |
f8cfc6aa | 1577 | if (set && REG_P (SET_DEST (set)) |
2b49ee39 | 1578 | && reg_renumber[REGNO (SET_DEST (set))] < 0 |
ab156144 RH |
1579 | && (reg_equiv_constant[REGNO (SET_DEST (set))] |
1580 | || (reg_equiv_invariant[REGNO (SET_DEST (set))])) | |
1581 | && reg_equiv_init[REGNO (SET_DEST (set))]) | |
67e61fe7 | 1582 | continue; |
1e5bd841 | 1583 | |
1e5bd841 | 1584 | /* If needed, eliminate any eliminable registers. */ |
2b49ee39 | 1585 | if (num_eliminable || num_eliminable_invariants) |
1e5bd841 BS |
1586 | did_elimination = eliminate_regs_in_insn (insn, 0); |
1587 | ||
1588 | /* Analyze the instruction. */ | |
cb2afeb3 R |
1589 | operands_changed = find_reloads (insn, 0, spill_indirect_levels, |
1590 | global, spill_reg_order); | |
1591 | ||
1592 | /* If a no-op set needs more than one reload, this is likely | |
1593 | to be something that needs input address reloads. We | |
1594 | can't get rid of this cleanly later, and it is of no use | |
1595 | anyway, so discard it now. | |
1596 | We only do this when expensive_optimizations is enabled, | |
1597 | since this complements reload inheritance / output | |
1598 | reload deletion, and it can make debugging harder. */ | |
1599 | if (flag_expensive_optimizations && n_reloads > 1) | |
1600 | { | |
1601 | rtx set = single_set (insn); | |
1602 | if (set | |
058e97ec VM |
1603 | && |
1604 | ((SET_SRC (set) == SET_DEST (set) | |
1605 | && REG_P (SET_SRC (set)) | |
1606 | && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) | |
1607 | || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set)) | |
1608 | && reg_renumber[REGNO (SET_SRC (set))] < 0 | |
1609 | && reg_renumber[REGNO (SET_DEST (set))] < 0 | |
1610 | && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL | |
1611 | && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL | |
1612 | && rtx_equal_p (reg_equiv_memory_loc | |
1613 | [REGNO (SET_SRC (set))], | |
1614 | reg_equiv_memory_loc | |
1615 | [REGNO (SET_DEST (set))])))) | |
cb2afeb3 | 1616 | { |
2af2dbdc | 1617 | if (ira_conflicts_p) |
058e97ec VM |
1618 | /* Inform IRA about the insn deletion. */ |
1619 | ira_mark_memory_move_deletion (REGNO (SET_DEST (set)), | |
1620 | REGNO (SET_SRC (set))); | |
ca6c03ca | 1621 | delete_insn (insn); |
3eae4643 | 1622 | /* Delete it from the reload chain. */ |
462561b7 JJ |
1623 | if (chain->prev) |
1624 | chain->prev->next = next; | |
1625 | else | |
1626 | reload_insn_chain = next; | |
1627 | if (next) | |
1628 | next->prev = chain->prev; | |
1629 | chain->next = unused_insn_chains; | |
1630 | unused_insn_chains = chain; | |
cb2afeb3 R |
1631 | continue; |
1632 | } | |
1633 | } | |
1634 | if (num_eliminable) | |
1635 | update_eliminable_offsets (); | |
1e5bd841 BS |
1636 | |
1637 | /* Remember for later shortcuts which insns had any reloads or | |
7609e720 BS |
1638 | register eliminations. */ |
1639 | chain->need_elim = did_elimination; | |
03acd8f8 BS |
1640 | chain->need_reload = n_reloads > 0; |
1641 | chain->need_operand_change = operands_changed; | |
1e5bd841 BS |
1642 | |
1643 | /* Discard any register replacements done. */ | |
1644 | if (did_elimination) | |
1645 | { | |
f5d8c9f4 | 1646 | obstack_free (&reload_obstack, reload_insn_firstobj); |
1e5bd841 BS |
1647 | PATTERN (insn) = old_body; |
1648 | INSN_CODE (insn) = old_code; | |
1649 | REG_NOTES (insn) = old_notes; | |
1650 | something_needs_elimination = 1; | |
1651 | } | |
1652 | ||
cb2afeb3 R |
1653 | something_needs_operands_changed |= operands_changed; |
1654 | ||
437a710d | 1655 | if (n_reloads != 0) |
7609e720 | 1656 | { |
f5d8c9f4 | 1657 | copy_reloads (chain); |
7609e720 BS |
1658 | *pprev_reload = chain; |
1659 | pprev_reload = &chain->next_need_reload; | |
7609e720 | 1660 | } |
1e5bd841 | 1661 | } |
1e5bd841 | 1662 | } |
7609e720 | 1663 | *pprev_reload = 0; |
1e5bd841 | 1664 | } |
f5d8c9f4 BS |
1665 | \f |
1666 | /* Comparison function for qsort to decide which of two reloads | |
1667 | should be handled first. *P1 and *P2 are the reload numbers. */ | |
1e5bd841 | 1668 | |
f5d8c9f4 | 1669 | static int |
0c20a65f | 1670 | reload_reg_class_lower (const void *r1p, const void *r2p) |
1e5bd841 | 1671 | { |
b3694847 SS |
1672 | int r1 = *(const short *) r1p, r2 = *(const short *) r2p; |
1673 | int t; | |
1e5bd841 | 1674 | |
f5d8c9f4 BS |
1675 | /* Consider required reloads before optional ones. */ |
1676 | t = rld[r1].optional - rld[r2].optional; | |
1677 | if (t != 0) | |
1678 | return t; | |
1e5bd841 | 1679 | |
f5d8c9f4 | 1680 | /* Count all solitary classes before non-solitary ones. */ |
48c54229 KG |
1681 | t = ((reg_class_size[(int) rld[r2].rclass] == 1) |
1682 | - (reg_class_size[(int) rld[r1].rclass] == 1)); | |
f5d8c9f4 BS |
1683 | if (t != 0) |
1684 | return t; | |
1e5bd841 | 1685 | |
f5d8c9f4 BS |
1686 | /* Aside from solitaires, consider all multi-reg groups first. */ |
1687 | t = rld[r2].nregs - rld[r1].nregs; | |
1688 | if (t != 0) | |
1689 | return t; | |
1e5bd841 | 1690 | |
f5d8c9f4 | 1691 | /* Consider reloads in order of increasing reg-class number. */ |
48c54229 | 1692 | t = (int) rld[r1].rclass - (int) rld[r2].rclass; |
f5d8c9f4 BS |
1693 | if (t != 0) |
1694 | return t; | |
1e5bd841 | 1695 | |
f5d8c9f4 BS |
1696 | /* If reloads are equally urgent, sort by reload number, |
1697 | so that the results of qsort leave nothing to chance. */ | |
1698 | return r1 - r2; | |
1699 | } | |
1700 | \f | |
1701 | /* The cost of spilling each hard reg. */ | |
1702 | static int spill_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1703 | |
f5d8c9f4 BS |
1704 | /* When spilling multiple hard registers, we use SPILL_COST for the first |
1705 | spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST | |
1706 | only the first hard reg for a multi-reg pseudo. */ | |
1707 | static int spill_add_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1708 | |
058e97ec VM |
1709 | /* Map of hard regno to pseudo regno currently occupying the hard |
1710 | reg. */ | |
1711 | static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER]; | |
1712 | ||
f5d8c9f4 | 1713 | /* Update the spill cost arrays, considering that pseudo REG is live. */ |
770ae6cc | 1714 | |
f5d8c9f4 | 1715 | static void |
0c20a65f | 1716 | count_pseudo (int reg) |
f5d8c9f4 | 1717 | { |
b2aec5c0 | 1718 | int freq = REG_FREQ (reg); |
f5d8c9f4 BS |
1719 | int r = reg_renumber[reg]; |
1720 | int nregs; | |
1e5bd841 | 1721 | |
f5d8c9f4 | 1722 | if (REGNO_REG_SET_P (&pseudos_counted, reg) |
058e97ec VM |
1723 | || REGNO_REG_SET_P (&spilled_pseudos, reg) |
1724 | /* Ignore spilled pseudo-registers which can be here only if IRA | |
1725 | is used. */ | |
2af2dbdc | 1726 | || (ira_conflicts_p && r < 0)) |
f5d8c9f4 | 1727 | return; |
1e5bd841 | 1728 | |
f5d8c9f4 | 1729 | SET_REGNO_REG_SET (&pseudos_counted, reg); |
1e5bd841 | 1730 | |
41374e13 | 1731 | gcc_assert (r >= 0); |
1d7254c5 | 1732 | |
b2aec5c0 | 1733 | spill_add_cost[r] += freq; |
66fd46b6 | 1734 | nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)]; |
f5d8c9f4 | 1735 | while (nregs-- > 0) |
058e97ec VM |
1736 | { |
1737 | hard_regno_to_pseudo_regno[r + nregs] = reg; | |
1738 | spill_cost[r + nregs] += freq; | |
1739 | } | |
f5d8c9f4 | 1740 | } |
1e5bd841 | 1741 | |
f5d8c9f4 BS |
1742 | /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the |
1743 | contents of BAD_SPILL_REGS for the insn described by CHAIN. */ | |
efc9bd41 | 1744 | |
f5d8c9f4 | 1745 | static void |
0c20a65f | 1746 | order_regs_for_reload (struct insn_chain *chain) |
f5d8c9f4 | 1747 | { |
3cd8c58a | 1748 | unsigned i; |
efc9bd41 RK |
1749 | HARD_REG_SET used_by_pseudos; |
1750 | HARD_REG_SET used_by_pseudos2; | |
a2041967 | 1751 | reg_set_iterator rsi; |
1e5bd841 | 1752 | |
efc9bd41 | 1753 | COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set); |
1e5bd841 | 1754 | |
f5d8c9f4 BS |
1755 | memset (spill_cost, 0, sizeof spill_cost); |
1756 | memset (spill_add_cost, 0, sizeof spill_add_cost); | |
058e97ec VM |
1757 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1758 | hard_regno_to_pseudo_regno[i] = -1; | |
1e5bd841 | 1759 | |
f5d8c9f4 | 1760 | /* Count number of uses of each hard reg by pseudo regs allocated to it |
efc9bd41 RK |
1761 | and then order them by decreasing use. First exclude hard registers |
1762 | that are live in or across this insn. */ | |
1763 | ||
1764 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); | |
1765 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
1766 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos); | |
1767 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2); | |
1e5bd841 | 1768 | |
f5d8c9f4 BS |
1769 | /* Now find out which pseudos are allocated to it, and update |
1770 | hard_reg_n_uses. */ | |
1771 | CLEAR_REG_SET (&pseudos_counted); | |
1e5bd841 | 1772 | |
f5d8c9f4 | 1773 | EXECUTE_IF_SET_IN_REG_SET |
a2041967 KH |
1774 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi) |
1775 | { | |
1776 | count_pseudo (i); | |
1777 | } | |
f5d8c9f4 | 1778 | EXECUTE_IF_SET_IN_REG_SET |
a2041967 KH |
1779 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi) |
1780 | { | |
1781 | count_pseudo (i); | |
1782 | } | |
f5d8c9f4 | 1783 | CLEAR_REG_SET (&pseudos_counted); |
1e5bd841 | 1784 | } |
03acd8f8 | 1785 | \f |
f5d8c9f4 BS |
1786 | /* Vector of reload-numbers showing the order in which the reloads should |
1787 | be processed. */ | |
1788 | static short reload_order[MAX_RELOADS]; | |
1e5bd841 | 1789 | |
f5d8c9f4 BS |
1790 | /* This is used to keep track of the spill regs used in one insn. */ |
1791 | static HARD_REG_SET used_spill_regs_local; | |
03acd8f8 | 1792 | |
f5d8c9f4 BS |
1793 | /* We decided to spill hard register SPILLED, which has a size of |
1794 | SPILLED_NREGS. Determine how pseudo REG, which is live during the insn, | |
1795 | is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will | |
1796 | update SPILL_COST/SPILL_ADD_COST. */ | |
770ae6cc | 1797 | |
03acd8f8 | 1798 | static void |
0c20a65f | 1799 | count_spilled_pseudo (int spilled, int spilled_nregs, int reg) |
1e5bd841 | 1800 | { |
058e97ec | 1801 | int freq = REG_FREQ (reg); |
f5d8c9f4 | 1802 | int r = reg_renumber[reg]; |
66fd46b6 | 1803 | int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)]; |
1e5bd841 | 1804 | |
058e97ec VM |
1805 | /* Ignore spilled pseudo-registers which can be here only if IRA is |
1806 | used. */ | |
2af2dbdc | 1807 | if ((ira_conflicts_p && r < 0) |
058e97ec | 1808 | || REGNO_REG_SET_P (&spilled_pseudos, reg) |
f5d8c9f4 BS |
1809 | || spilled + spilled_nregs <= r || r + nregs <= spilled) |
1810 | return; | |
1e5bd841 | 1811 | |
f5d8c9f4 | 1812 | SET_REGNO_REG_SET (&spilled_pseudos, reg); |
1e5bd841 | 1813 | |
058e97ec | 1814 | spill_add_cost[r] -= freq; |
f5d8c9f4 | 1815 | while (nregs-- > 0) |
058e97ec VM |
1816 | { |
1817 | hard_regno_to_pseudo_regno[r + nregs] = -1; | |
1818 | spill_cost[r + nregs] -= freq; | |
1819 | } | |
1e5bd841 BS |
1820 | } |
1821 | ||
f5d8c9f4 | 1822 | /* Find reload register to use for reload number ORDER. */ |
03acd8f8 | 1823 | |
f5d8c9f4 | 1824 | static int |
0c20a65f | 1825 | find_reg (struct insn_chain *chain, int order) |
1e5bd841 | 1826 | { |
f5d8c9f4 BS |
1827 | int rnum = reload_order[order]; |
1828 | struct reload *rl = rld + rnum; | |
1829 | int best_cost = INT_MAX; | |
1830 | int best_reg = -1; | |
058e97ec | 1831 | unsigned int i, j, n; |
770ae6cc | 1832 | int k; |
f5d8c9f4 BS |
1833 | HARD_REG_SET not_usable; |
1834 | HARD_REG_SET used_by_other_reload; | |
a2041967 | 1835 | reg_set_iterator rsi; |
058e97ec VM |
1836 | static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER]; |
1837 | static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1838 | |
f5d8c9f4 BS |
1839 | COPY_HARD_REG_SET (not_usable, bad_spill_regs); |
1840 | IOR_HARD_REG_SET (not_usable, bad_spill_regs_global); | |
48c54229 | 1841 | IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]); |
f5d8c9f4 BS |
1842 | |
1843 | CLEAR_HARD_REG_SET (used_by_other_reload); | |
770ae6cc | 1844 | for (k = 0; k < order; k++) |
1e5bd841 | 1845 | { |
770ae6cc RK |
1846 | int other = reload_order[k]; |
1847 | ||
f5d8c9f4 BS |
1848 | if (rld[other].regno >= 0 && reloads_conflict (other, rnum)) |
1849 | for (j = 0; j < rld[other].nregs; j++) | |
1850 | SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j); | |
1851 | } | |
1e5bd841 | 1852 | |
f5d8c9f4 BS |
1853 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1854 | { | |
058e97ec VM |
1855 | #ifdef REG_ALLOC_ORDER |
1856 | unsigned int regno = reg_alloc_order[i]; | |
1857 | #else | |
770ae6cc | 1858 | unsigned int regno = i; |
058e97ec | 1859 | #endif |
770ae6cc | 1860 | |
f5d8c9f4 BS |
1861 | if (! TEST_HARD_REG_BIT (not_usable, regno) |
1862 | && ! TEST_HARD_REG_BIT (used_by_other_reload, regno) | |
1863 | && HARD_REGNO_MODE_OK (regno, rl->mode)) | |
1e5bd841 | 1864 | { |
f5d8c9f4 BS |
1865 | int this_cost = spill_cost[regno]; |
1866 | int ok = 1; | |
66fd46b6 | 1867 | unsigned int this_nregs = hard_regno_nregs[regno][rl->mode]; |
1e5bd841 | 1868 | |
f5d8c9f4 BS |
1869 | for (j = 1; j < this_nregs; j++) |
1870 | { | |
1871 | this_cost += spill_add_cost[regno + j]; | |
1872 | if ((TEST_HARD_REG_BIT (not_usable, regno + j)) | |
1873 | || TEST_HARD_REG_BIT (used_by_other_reload, regno + j)) | |
1874 | ok = 0; | |
1875 | } | |
1876 | if (! ok) | |
1877 | continue; | |
058e97ec | 1878 | |
2af2dbdc | 1879 | if (ira_conflicts_p) |
058e97ec VM |
1880 | { |
1881 | /* Ask IRA to find a better pseudo-register for | |
1882 | spilling. */ | |
1883 | for (n = j = 0; j < this_nregs; j++) | |
1884 | { | |
1885 | int r = hard_regno_to_pseudo_regno[regno + j]; | |
1886 | ||
1887 | if (r < 0) | |
1888 | continue; | |
1889 | if (n == 0 || regno_pseudo_regs[n - 1] != r) | |
1890 | regno_pseudo_regs[n++] = r; | |
1891 | } | |
1892 | regno_pseudo_regs[n++] = -1; | |
1893 | if (best_reg < 0 | |
1894 | || ira_better_spill_reload_regno_p (regno_pseudo_regs, | |
1895 | best_regno_pseudo_regs, | |
1896 | rl->in, rl->out, | |
1897 | chain->insn)) | |
1898 | { | |
1899 | best_reg = regno; | |
1900 | for (j = 0;; j++) | |
1901 | { | |
1902 | best_regno_pseudo_regs[j] = regno_pseudo_regs[j]; | |
1903 | if (regno_pseudo_regs[j] < 0) | |
1904 | break; | |
1905 | } | |
1906 | } | |
1907 | continue; | |
1908 | } | |
1909 | ||
f8cfc6aa | 1910 | if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno) |
f5d8c9f4 | 1911 | this_cost--; |
f8cfc6aa | 1912 | if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno) |
f5d8c9f4 BS |
1913 | this_cost--; |
1914 | if (this_cost < best_cost | |
1915 | /* Among registers with equal cost, prefer caller-saved ones, or | |
1916 | use REG_ALLOC_ORDER if it is defined. */ | |
1917 | || (this_cost == best_cost | |
1918 | #ifdef REG_ALLOC_ORDER | |
1919 | && (inv_reg_alloc_order[regno] | |
1920 | < inv_reg_alloc_order[best_reg]) | |
1921 | #else | |
1922 | && call_used_regs[regno] | |
1923 | && ! call_used_regs[best_reg] | |
1924 | #endif | |
1925 | )) | |
1926 | { | |
1927 | best_reg = regno; | |
1928 | best_cost = this_cost; | |
1e5bd841 BS |
1929 | } |
1930 | } | |
1931 | } | |
f5d8c9f4 BS |
1932 | if (best_reg == -1) |
1933 | return 0; | |
770ae6cc | 1934 | |
c263766c RH |
1935 | if (dump_file) |
1936 | fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum); | |
770ae6cc | 1937 | |
66fd46b6 | 1938 | rl->nregs = hard_regno_nregs[best_reg][rl->mode]; |
f5d8c9f4 | 1939 | rl->regno = best_reg; |
1e5bd841 | 1940 | |
f5d8c9f4 | 1941 | EXECUTE_IF_SET_IN_REG_SET |
a2041967 KH |
1942 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi) |
1943 | { | |
1944 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1945 | } | |
770ae6cc | 1946 | |
f5d8c9f4 | 1947 | EXECUTE_IF_SET_IN_REG_SET |
a2041967 KH |
1948 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi) |
1949 | { | |
1950 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1951 | } | |
03acd8f8 | 1952 | |
f5d8c9f4 BS |
1953 | for (i = 0; i < rl->nregs; i++) |
1954 | { | |
41374e13 NS |
1955 | gcc_assert (spill_cost[best_reg + i] == 0); |
1956 | gcc_assert (spill_add_cost[best_reg + i] == 0); | |
058e97ec | 1957 | gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1); |
f5d8c9f4 BS |
1958 | SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i); |
1959 | } | |
1960 | return 1; | |
03acd8f8 BS |
1961 | } |
1962 | ||
1963 | /* Find more reload regs to satisfy the remaining need of an insn, which | |
1964 | is given by CHAIN. | |
1e5bd841 BS |
1965 | Do it by ascending class number, since otherwise a reg |
1966 | might be spilled for a big class and might fail to count | |
f5d8c9f4 | 1967 | for a smaller class even though it belongs to that class. */ |
1e5bd841 | 1968 | |
03acd8f8 | 1969 | static void |
0c20a65f | 1970 | find_reload_regs (struct insn_chain *chain) |
1e5bd841 | 1971 | { |
f5d8c9f4 | 1972 | int i; |
1e5bd841 | 1973 | |
f5d8c9f4 BS |
1974 | /* In order to be certain of getting the registers we need, |
1975 | we must sort the reloads into order of increasing register class. | |
1976 | Then our grabbing of reload registers will parallel the process | |
1977 | that provided the reload registers. */ | |
1978 | for (i = 0; i < chain->n_reloads; i++) | |
1e5bd841 | 1979 | { |
f5d8c9f4 BS |
1980 | /* Show whether this reload already has a hard reg. */ |
1981 | if (chain->rld[i].reg_rtx) | |
1e5bd841 | 1982 | { |
f5d8c9f4 BS |
1983 | int regno = REGNO (chain->rld[i].reg_rtx); |
1984 | chain->rld[i].regno = regno; | |
770ae6cc | 1985 | chain->rld[i].nregs |
66fd46b6 | 1986 | = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)]; |
1e5bd841 | 1987 | } |
f5d8c9f4 BS |
1988 | else |
1989 | chain->rld[i].regno = -1; | |
1990 | reload_order[i] = i; | |
1991 | } | |
1e5bd841 | 1992 | |
f5d8c9f4 BS |
1993 | n_reloads = chain->n_reloads; |
1994 | memcpy (rld, chain->rld, n_reloads * sizeof (struct reload)); | |
1e5bd841 | 1995 | |
f5d8c9f4 | 1996 | CLEAR_HARD_REG_SET (used_spill_regs_local); |
03acd8f8 | 1997 | |
c263766c RH |
1998 | if (dump_file) |
1999 | fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn)); | |
1e5bd841 | 2000 | |
f5d8c9f4 | 2001 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); |
1e5bd841 | 2002 | |
f5d8c9f4 | 2003 | /* Compute the order of preference for hard registers to spill. */ |
1e5bd841 | 2004 | |
f5d8c9f4 | 2005 | order_regs_for_reload (chain); |
1e5bd841 | 2006 | |
f5d8c9f4 BS |
2007 | for (i = 0; i < n_reloads; i++) |
2008 | { | |
2009 | int r = reload_order[i]; | |
1e5bd841 | 2010 | |
f5d8c9f4 BS |
2011 | /* Ignore reloads that got marked inoperative. */ |
2012 | if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p) | |
2013 | && ! rld[r].optional | |
2014 | && rld[r].regno == -1) | |
e04ca094 | 2015 | if (! find_reg (chain, i)) |
f5d8c9f4 | 2016 | { |
ff182b5c | 2017 | if (dump_file) |
247140ea | 2018 | fprintf (dump_file, "reload failure for reload %d\n", r); |
48c54229 | 2019 | spill_failure (chain->insn, rld[r].rclass); |
f5d8c9f4 | 2020 | failure = 1; |
03acd8f8 | 2021 | return; |
f5d8c9f4 | 2022 | } |
1e5bd841 | 2023 | } |
05d10675 | 2024 | |
f5d8c9f4 BS |
2025 | COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local); |
2026 | IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local); | |
03acd8f8 | 2027 | |
f5d8c9f4 | 2028 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); |
1e5bd841 BS |
2029 | } |
2030 | ||
f5d8c9f4 | 2031 | static void |
0c20a65f | 2032 | select_reload_regs (void) |
09dd1133 | 2033 | { |
f5d8c9f4 | 2034 | struct insn_chain *chain; |
09dd1133 | 2035 | |
f5d8c9f4 BS |
2036 | /* Try to satisfy the needs for each insn. */ |
2037 | for (chain = insns_need_reload; chain != 0; | |
2038 | chain = chain->next_need_reload) | |
e04ca094 | 2039 | find_reload_regs (chain); |
09dd1133 | 2040 | } |
32131a9c | 2041 | \f |
437a710d BS |
2042 | /* Delete all insns that were inserted by emit_caller_save_insns during |
2043 | this iteration. */ | |
2044 | static void | |
0c20a65f | 2045 | delete_caller_save_insns (void) |
437a710d | 2046 | { |
7609e720 | 2047 | struct insn_chain *c = reload_insn_chain; |
437a710d | 2048 | |
7609e720 | 2049 | while (c != 0) |
437a710d | 2050 | { |
7609e720 | 2051 | while (c != 0 && c->is_caller_save_insn) |
437a710d | 2052 | { |
7609e720 BS |
2053 | struct insn_chain *next = c->next; |
2054 | rtx insn = c->insn; | |
2055 | ||
7609e720 BS |
2056 | if (c == reload_insn_chain) |
2057 | reload_insn_chain = next; | |
ca6c03ca | 2058 | delete_insn (insn); |
7609e720 BS |
2059 | |
2060 | if (next) | |
2061 | next->prev = c->prev; | |
2062 | if (c->prev) | |
2063 | c->prev->next = next; | |
2064 | c->next = unused_insn_chains; | |
2065 | unused_insn_chains = c; | |
2066 | c = next; | |
437a710d | 2067 | } |
7609e720 BS |
2068 | if (c != 0) |
2069 | c = c->next; | |
437a710d BS |
2070 | } |
2071 | } | |
2072 | \f | |
5352b11a RS |
2073 | /* Handle the failure to find a register to spill. |
2074 | INSN should be one of the insns which needed this particular spill reg. */ | |
2075 | ||
2076 | static void | |
55d796da | 2077 | spill_failure (rtx insn, enum reg_class rclass) |
5352b11a RS |
2078 | { |
2079 | if (asm_noperands (PATTERN (insn)) >= 0) | |
971801ff JM |
2080 | error_for_asm (insn, "can't find a register in class %qs while " |
2081 | "reloading %<asm%>", | |
55d796da | 2082 | reg_class_names[rclass]); |
5352b11a | 2083 | else |
ecf3151a | 2084 | { |
971801ff | 2085 | error ("unable to find a register to spill in class %qs", |
55d796da | 2086 | reg_class_names[rclass]); |
ff182b5c DD |
2087 | |
2088 | if (dump_file) | |
2089 | { | |
2090 | fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn)); | |
2091 | debug_reload_to_stream (dump_file); | |
2092 | } | |
1f978f5f | 2093 | fatal_insn ("this is the insn:", insn); |
ecf3151a | 2094 | } |
5352b11a | 2095 | } |
32131a9c RK |
2096 | \f |
2097 | /* Delete an unneeded INSN and any previous insns who sole purpose is loading | |
2098 | data that is dead in INSN. */ | |
2099 | ||
2100 | static void | |
0c20a65f | 2101 | delete_dead_insn (rtx insn) |
32131a9c RK |
2102 | { |
2103 | rtx prev = prev_real_insn (insn); | |
2104 | rtx prev_dest; | |
2105 | ||
2106 | /* If the previous insn sets a register that dies in our insn, delete it | |
2107 | too. */ | |
2108 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
f8cfc6aa | 2109 | && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest)) |
32131a9c | 2110 | && reg_mentioned_p (prev_dest, PATTERN (insn)) |
b294ca38 R |
2111 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) |
2112 | && ! side_effects_p (SET_SRC (PATTERN (prev)))) | |
32131a9c RK |
2113 | delete_dead_insn (prev); |
2114 | ||
6773e15f | 2115 | SET_INSN_DELETED (insn); |
32131a9c RK |
2116 | } |
2117 | ||
2118 | /* Modify the home of pseudo-reg I. | |
2119 | The new home is present in reg_renumber[I]. | |
2120 | ||
2121 | FROM_REG may be the hard reg that the pseudo-reg is being spilled from; | |
2122 | or it may be -1, meaning there is none or it is not relevant. | |
2123 | This is used so that all pseudos spilled from a given hard reg | |
2124 | can share one stack slot. */ | |
2125 | ||
2126 | static void | |
058e97ec | 2127 | alter_reg (int i, int from_reg, bool dont_share_p) |
32131a9c RK |
2128 | { |
2129 | /* When outputting an inline function, this can happen | |
2130 | for a reg that isn't actually used. */ | |
2131 | if (regno_reg_rtx[i] == 0) | |
2132 | return; | |
2133 | ||
2134 | /* If the reg got changed to a MEM at rtl-generation time, | |
2135 | ignore it. */ | |
f8cfc6aa | 2136 | if (!REG_P (regno_reg_rtx[i])) |
32131a9c RK |
2137 | return; |
2138 | ||
2139 | /* Modify the reg-rtx to contain the new hard reg | |
2140 | number or else to contain its pseudo reg number. */ | |
6fb5fa3c DB |
2141 | SET_REGNO (regno_reg_rtx[i], |
2142 | reg_renumber[i] >= 0 ? reg_renumber[i] : i); | |
32131a9c RK |
2143 | |
2144 | /* If we have a pseudo that is needed but has no hard reg or equivalent, | |
2145 | allocate a stack slot for it. */ | |
2146 | ||
2147 | if (reg_renumber[i] < 0 | |
b1f21e0a | 2148 | && REG_N_REFS (i) > 0 |
32131a9c | 2149 | && reg_equiv_constant[i] == 0 |
ab156144 | 2150 | && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0) |
32131a9c RK |
2151 | && reg_equiv_memory_loc[i] == 0) |
2152 | { | |
f6129d66 | 2153 | rtx x = NULL_RTX; |
63a7a62b | 2154 | enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); |
770ae6cc | 2155 | unsigned int inherent_size = PSEUDO_REGNO_BYTES (i); |
63a7a62b | 2156 | unsigned int inherent_align = GET_MODE_ALIGNMENT (mode); |
770ae6cc | 2157 | unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]); |
63a7a62b | 2158 | unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT; |
32131a9c | 2159 | int adjust = 0; |
058e97ec | 2160 | |
2af2dbdc | 2161 | if (ira_conflicts_p) |
f6129d66 RH |
2162 | { |
2163 | /* Mark the spill for IRA. */ | |
2164 | SET_REGNO_REG_SET (&spilled_pseudos, i); | |
2165 | if (!dont_share_p) | |
2166 | x = ira_reuse_stack_slot (i, inherent_size, total_size); | |
2167 | } | |
2168 | ||
058e97ec | 2169 | if (x) |
f6129d66 RH |
2170 | ; |
2171 | ||
32131a9c RK |
2172 | /* Each pseudo reg has an inherent size which comes from its own mode, |
2173 | and a total size which provides room for paradoxical subregs | |
2174 | which refer to the pseudo reg in wider modes. | |
2175 | ||
2176 | We can use a slot already allocated if it provides both | |
2177 | enough inherent space and enough total space. | |
2178 | Otherwise, we allocate a new slot, making sure that it has no less | |
2179 | inherent space, and no less total space, then the previous slot. */ | |
2af2dbdc | 2180 | else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p)) |
32131a9c | 2181 | { |
13d7e8af | 2182 | rtx stack_slot; |
6fb5fa3c | 2183 | |
32131a9c | 2184 | /* No known place to spill from => no slot to reuse. */ |
63a7a62b RS |
2185 | x = assign_stack_local (mode, total_size, |
2186 | min_align > inherent_align | |
2187 | || total_size > inherent_size ? -1 : 0); | |
13d7e8af JL |
2188 | |
2189 | stack_slot = x; | |
2190 | ||
f6129d66 RH |
2191 | /* Cancel the big-endian correction done in assign_stack_local. |
2192 | Get the address of the beginning of the slot. This is so we | |
2193 | can do a big-endian correction unconditionally below. */ | |
f76b9db2 | 2194 | if (BYTES_BIG_ENDIAN) |
6b5676ce | 2195 | { |
6b5676ce JL |
2196 | adjust = inherent_size - total_size; |
2197 | if (adjust) | |
2198 | stack_slot | |
2199 | = adjust_address_nv (x, mode_for_size (total_size | |
2200 | * BITS_PER_UNIT, | |
2201 | MODE_INT, 1), | |
2202 | adjust); | |
2203 | } | |
02db8dd0 | 2204 | |
2af2dbdc | 2205 | if (! dont_share_p && ira_conflicts_p) |
058e97ec | 2206 | /* Inform IRA about allocation a new stack slot. */ |
13d7e8af | 2207 | ira_mark_new_stack_slot (stack_slot, i, total_size); |
32131a9c | 2208 | } |
3bdf5ad1 | 2209 | |
32131a9c RK |
2210 | /* Reuse a stack slot if possible. */ |
2211 | else if (spill_stack_slot[from_reg] != 0 | |
2212 | && spill_stack_slot_width[from_reg] >= total_size | |
2213 | && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
63a7a62b RS |
2214 | >= inherent_size) |
2215 | && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align) | |
32131a9c | 2216 | x = spill_stack_slot[from_reg]; |
f6129d66 | 2217 | |
32131a9c RK |
2218 | /* Allocate a bigger slot. */ |
2219 | else | |
2220 | { | |
2221 | /* Compute maximum size needed, both for inherent size | |
2222 | and for total size. */ | |
4f2d3674 | 2223 | rtx stack_slot; |
3bdf5ad1 | 2224 | |
32131a9c RK |
2225 | if (spill_stack_slot[from_reg]) |
2226 | { | |
2227 | if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
2228 | > inherent_size) | |
2229 | mode = GET_MODE (spill_stack_slot[from_reg]); | |
2230 | if (spill_stack_slot_width[from_reg] > total_size) | |
2231 | total_size = spill_stack_slot_width[from_reg]; | |
63a7a62b RS |
2232 | if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align) |
2233 | min_align = MEM_ALIGN (spill_stack_slot[from_reg]); | |
32131a9c | 2234 | } |
3bdf5ad1 | 2235 | |
32131a9c | 2236 | /* Make a slot with that size. */ |
cabcf079 | 2237 | x = assign_stack_local (mode, total_size, |
63a7a62b RS |
2238 | min_align > inherent_align |
2239 | || total_size > inherent_size ? -1 : 0); | |
4f2d3674 | 2240 | stack_slot = x; |
3bdf5ad1 | 2241 | |
f6129d66 RH |
2242 | /* Cancel the big-endian correction done in assign_stack_local. |
2243 | Get the address of the beginning of the slot. This is so we | |
2244 | can do a big-endian correction unconditionally below. */ | |
f76b9db2 ILT |
2245 | if (BYTES_BIG_ENDIAN) |
2246 | { | |
f76b9db2 | 2247 | adjust = GET_MODE_SIZE (mode) - total_size; |
4f2d3674 | 2248 | if (adjust) |
8ac61af7 RK |
2249 | stack_slot |
2250 | = adjust_address_nv (x, mode_for_size (total_size | |
38a448ca RH |
2251 | * BITS_PER_UNIT, |
2252 | MODE_INT, 1), | |
8ac61af7 | 2253 | adjust); |
f76b9db2 | 2254 | } |
3bdf5ad1 | 2255 | |
4f2d3674 | 2256 | spill_stack_slot[from_reg] = stack_slot; |
32131a9c RK |
2257 | spill_stack_slot_width[from_reg] = total_size; |
2258 | } | |
2259 | ||
32131a9c RK |
2260 | /* On a big endian machine, the "address" of the slot |
2261 | is the address of the low part that fits its inherent mode. */ | |
f76b9db2 | 2262 | if (BYTES_BIG_ENDIAN && inherent_size < total_size) |
32131a9c | 2263 | adjust += (total_size - inherent_size); |
32131a9c RK |
2264 | |
2265 | /* If we have any adjustment to make, or if the stack slot is the | |
2266 | wrong mode, make a new stack slot. */ | |
1285011e RK |
2267 | x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust); |
2268 | ||
f6129d66 RH |
2269 | /* Set all of the memory attributes as appropriate for a spill. */ |
2270 | set_mem_attrs_for_spill (x); | |
32131a9c | 2271 | |
6d2f8887 | 2272 | /* Save the stack slot for later. */ |
32131a9c RK |
2273 | reg_equiv_memory_loc[i] = x; |
2274 | } | |
2275 | } | |
2276 | ||
6fb5fa3c DB |
2277 | /* Mark the slots in regs_ever_live for the hard regs used by |
2278 | pseudo-reg number REGNO, accessed in MODE. */ | |
32131a9c | 2279 | |
6fb5fa3c DB |
2280 | static void |
2281 | mark_home_live_1 (int regno, enum machine_mode mode) | |
32131a9c | 2282 | { |
b3694847 | 2283 | int i, lim; |
770ae6cc | 2284 | |
32131a9c RK |
2285 | i = reg_renumber[regno]; |
2286 | if (i < 0) | |
2287 | return; | |
b0384c54 | 2288 | lim = end_hard_regno (mode, i); |
32131a9c | 2289 | while (i < lim) |
6fb5fa3c DB |
2290 | df_set_regs_ever_live(i++, true); |
2291 | } | |
2292 | ||
2293 | /* Mark the slots in regs_ever_live for the hard regs | |
2294 | used by pseudo-reg number REGNO. */ | |
2295 | ||
2296 | void | |
2297 | mark_home_live (int regno) | |
2298 | { | |
2299 | if (reg_renumber[regno] >= 0) | |
2300 | mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno)); | |
32131a9c RK |
2301 | } |
2302 | \f | |
2303 | /* This function handles the tracking of elimination offsets around branches. | |
2304 | ||
2305 | X is a piece of RTL being scanned. | |
2306 | ||
2307 | INSN is the insn that it came from, if any. | |
2308 | ||
40f03658 | 2309 | INITIAL_P is nonzero if we are to set the offset to be the initial |
32131a9c RK |
2310 | offset and zero if we are setting the offset of the label to be the |
2311 | current offset. */ | |
2312 | ||
2313 | static void | |
0c20a65f | 2314 | set_label_offsets (rtx x, rtx insn, int initial_p) |
32131a9c RK |
2315 | { |
2316 | enum rtx_code code = GET_CODE (x); | |
2317 | rtx tem; | |
e51712db | 2318 | unsigned int i; |
32131a9c RK |
2319 | struct elim_table *p; |
2320 | ||
2321 | switch (code) | |
2322 | { | |
2323 | case LABEL_REF: | |
8be386d9 RS |
2324 | if (LABEL_REF_NONLOCAL_P (x)) |
2325 | return; | |
2326 | ||
32131a9c RK |
2327 | x = XEXP (x, 0); |
2328 | ||
0f41302f | 2329 | /* ... fall through ... */ |
32131a9c RK |
2330 | |
2331 | case CODE_LABEL: | |
2332 | /* If we know nothing about this label, set the desired offsets. Note | |
2333 | that this sets the offset at a label to be the offset before a label | |
2334 | if we don't know anything about the label. This is not correct for | |
2335 | the label after a BARRIER, but is the best guess we can make. If | |
2336 | we guessed wrong, we will suppress an elimination that might have | |
2337 | been possible had we been able to guess correctly. */ | |
2338 | ||
4cc0fdd2 | 2339 | if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num]) |
32131a9c RK |
2340 | { |
2341 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
4cc0fdd2 | 2342 | offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i] |
32131a9c RK |
2343 | = (initial_p ? reg_eliminate[i].initial_offset |
2344 | : reg_eliminate[i].offset); | |
4cc0fdd2 | 2345 | offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1; |
32131a9c RK |
2346 | } |
2347 | ||
2348 | /* Otherwise, if this is the definition of a label and it is | |
d45cf215 | 2349 | preceded by a BARRIER, set our offsets to the known offset of |
32131a9c RK |
2350 | that label. */ |
2351 | ||
2352 | else if (x == insn | |
2353 | && (tem = prev_nonnote_insn (insn)) != 0 | |
4b4bf941 | 2354 | && BARRIER_P (tem)) |
1f3b1e1a | 2355 | set_offsets_for_label (insn); |
32131a9c RK |
2356 | else |
2357 | /* If neither of the above cases is true, compare each offset | |
2358 | with those previously recorded and suppress any eliminations | |
2359 | where the offsets disagree. */ | |
a8fdc208 | 2360 | |
32131a9c | 2361 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) |
4cc0fdd2 | 2362 | if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i] |
32131a9c RK |
2363 | != (initial_p ? reg_eliminate[i].initial_offset |
2364 | : reg_eliminate[i].offset)) | |
2365 | reg_eliminate[i].can_eliminate = 0; | |
2366 | ||
2367 | return; | |
2368 | ||
2369 | case JUMP_INSN: | |
2370 | set_label_offsets (PATTERN (insn), insn, initial_p); | |
2371 | ||
0f41302f | 2372 | /* ... fall through ... */ |
32131a9c RK |
2373 | |
2374 | case INSN: | |
2375 | case CALL_INSN: | |
cf7c4aa6 HPN |
2376 | /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched |
2377 | to indirectly and hence must have all eliminations at their | |
2378 | initial offsets. */ | |
32131a9c | 2379 | for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) |
cf7c4aa6 | 2380 | if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND) |
32131a9c RK |
2381 | set_label_offsets (XEXP (tem, 0), insn, 1); |
2382 | return; | |
2383 | ||
0c0ba09c | 2384 | case PARALLEL: |
32131a9c RK |
2385 | case ADDR_VEC: |
2386 | case ADDR_DIFF_VEC: | |
0c0ba09c JJ |
2387 | /* Each of the labels in the parallel or address vector must be |
2388 | at their initial offsets. We want the first field for PARALLEL | |
2389 | and ADDR_VEC and the second field for ADDR_DIFF_VEC. */ | |
32131a9c | 2390 | |
e51712db | 2391 | for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++) |
32131a9c RK |
2392 | set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), |
2393 | insn, initial_p); | |
2394 | return; | |
2395 | ||
2396 | case SET: | |
2397 | /* We only care about setting PC. If the source is not RETURN, | |
2398 | IF_THEN_ELSE, or a label, disable any eliminations not at | |
2399 | their initial offsets. Similarly if any arm of the IF_THEN_ELSE | |
2400 | isn't one of those possibilities. For branches to a label, | |
2401 | call ourselves recursively. | |
2402 | ||
2403 | Note that this can disable elimination unnecessarily when we have | |
2404 | a non-local goto since it will look like a non-constant jump to | |
2405 | someplace in the current function. This isn't a significant | |
2406 | problem since such jumps will normally be when all elimination | |
2407 | pairs are back to their initial offsets. */ | |
2408 | ||
2409 | if (SET_DEST (x) != pc_rtx) | |
2410 | return; | |
2411 | ||
2412 | switch (GET_CODE (SET_SRC (x))) | |
2413 | { | |
2414 | case PC: | |
2415 | case RETURN: | |
2416 | return; | |
2417 | ||
2418 | case LABEL_REF: | |
8f235343 | 2419 | set_label_offsets (SET_SRC (x), insn, initial_p); |
32131a9c RK |
2420 | return; |
2421 | ||
2422 | case IF_THEN_ELSE: | |
2423 | tem = XEXP (SET_SRC (x), 1); | |
2424 | if (GET_CODE (tem) == LABEL_REF) | |
2425 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2426 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2427 | break; | |
2428 | ||
2429 | tem = XEXP (SET_SRC (x), 2); | |
2430 | if (GET_CODE (tem) == LABEL_REF) | |
2431 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2432 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2433 | break; | |
2434 | return; | |
e9a25f70 JL |
2435 | |
2436 | default: | |
2437 | break; | |
32131a9c RK |
2438 | } |
2439 | ||
2440 | /* If we reach here, all eliminations must be at their initial | |
2441 | offset because we are doing a jump to a variable address. */ | |
2442 | for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) | |
2443 | if (p->offset != p->initial_offset) | |
2444 | p->can_eliminate = 0; | |
e9a25f70 | 2445 | break; |
05d10675 | 2446 | |
e9a25f70 JL |
2447 | default: |
2448 | break; | |
32131a9c RK |
2449 | } |
2450 | } | |
2451 | \f | |
a8fdc208 | 2452 | /* Scan X and replace any eliminable registers (such as fp) with a |
32131a9c RK |
2453 | replacement (such as sp), plus an offset. |
2454 | ||
2455 | MEM_MODE is the mode of an enclosing MEM. We need this to know how | |
2456 | much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a | |
2457 | MEM, we are allowed to replace a sum of a register and the constant zero | |
2458 | with the register, which we cannot do outside a MEM. In addition, we need | |
2459 | to record the fact that a register is referenced outside a MEM. | |
2460 | ||
ff32812a | 2461 | If INSN is an insn, it is the insn containing X. If we replace a REG |
40f03658 | 2462 | in a SET_DEST with an equivalent MEM and INSN is nonzero, write a |
32131a9c | 2463 | CLOBBER of the pseudo after INSN so find_equiv_regs will know that |
38e01259 | 2464 | the REG is being modified. |
32131a9c | 2465 | |
ff32812a RS |
2466 | Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST). |
2467 | That's used when we eliminate in expressions stored in notes. | |
2468 | This means, do not set ref_outside_mem even if the reference | |
2469 | is outside of MEMs. | |
2470 | ||
32131a9c RK |
2471 | REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had |
2472 | replacements done assuming all offsets are at their initial values. If | |
2473 | they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we | |
2474 | encounter, return the actual location so that find_reloads will do | |
2475 | the proper thing. */ | |
2476 | ||
ab156144 RH |
2477 | static rtx |
2478 | eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn, | |
2479 | bool may_use_invariant) | |
32131a9c RK |
2480 | { |
2481 | enum rtx_code code = GET_CODE (x); | |
2482 | struct elim_table *ep; | |
2483 | int regno; | |
55d796da | 2484 | rtx new_rtx; |
32131a9c | 2485 | int i, j; |
6f7d635c | 2486 | const char *fmt; |
32131a9c RK |
2487 | int copied = 0; |
2488 | ||
d6633f01 NS |
2489 | if (! current_function_decl) |
2490 | return x; | |
9969bb2c | 2491 | |
32131a9c RK |
2492 | switch (code) |
2493 | { | |
2494 | case CONST_INT: | |
2495 | case CONST_DOUBLE: | |
091a3ac7 | 2496 | case CONST_FIXED: |
69ef87e2 | 2497 | case CONST_VECTOR: |
32131a9c RK |
2498 | case CONST: |
2499 | case SYMBOL_REF: | |
2500 | case CODE_LABEL: | |
2501 | case PC: | |
2502 | case CC0: | |
2503 | case ASM_INPUT: | |
2504 | case ADDR_VEC: | |
2505 | case ADDR_DIFF_VEC: | |
2506 | case RETURN: | |
2507 | return x; | |
2508 | ||
2509 | case REG: | |
2510 | regno = REGNO (x); | |
2511 | ||
2512 | /* First handle the case where we encounter a bare register that | |
2513 | is eliminable. Replace it with a PLUS. */ | |
2514 | if (regno < FIRST_PSEUDO_REGISTER) | |
2515 | { | |
2516 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2517 | ep++) | |
2518 | if (ep->from_rtx == x && ep->can_eliminate) | |
dfac187e | 2519 | return plus_constant (ep->to_rtx, ep->previous_offset); |
32131a9c RK |
2520 | |
2521 | } | |
cd7c9015 | 2522 | else if (reg_renumber && reg_renumber[regno] < 0 |
ab156144 RH |
2523 | && reg_equiv_invariant && reg_equiv_invariant[regno]) |
2524 | { | |
2525 | if (may_use_invariant) | |
2526 | return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]), | |
2527 | mem_mode, insn, true); | |
2528 | /* There exists at least one use of REGNO that cannot be | |
2529 | eliminated. Prevent the defining insn from being deleted. */ | |
2530 | reg_equiv_init[regno] = NULL_RTX; | |
058e97ec | 2531 | alter_reg (regno, -1, true); |
ab156144 | 2532 | } |
32131a9c RK |
2533 | return x; |
2534 | ||
c5c76735 JL |
2535 | /* You might think handling MINUS in a manner similar to PLUS is a |
2536 | good idea. It is not. It has been tried multiple times and every | |
2537 | time the change has had to have been reverted. | |
2538 | ||
2539 | Other parts of reload know a PLUS is special (gen_reload for example) | |
2540 | and require special code to handle code a reloaded PLUS operand. | |
2541 | ||
2542 | Also consider backends where the flags register is clobbered by a | |
a457ee07 | 2543 | MINUS, but we can emit a PLUS that does not clobber flags (IA-32, |
c5c76735 JL |
2544 | lea instruction comes to mind). If we try to reload a MINUS, we |
2545 | may kill the flags register that was holding a useful value. | |
2546 | ||
2547 | So, please before trying to handle MINUS, consider reload as a | |
2548 | whole instead of this little section as well as the backend issues. */ | |
32131a9c RK |
2549 | case PLUS: |
2550 | /* If this is the sum of an eliminable register and a constant, rework | |
6d2f8887 | 2551 | the sum. */ |
f8cfc6aa | 2552 | if (REG_P (XEXP (x, 0)) |
32131a9c RK |
2553 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER |
2554 | && CONSTANT_P (XEXP (x, 1))) | |
2555 | { | |
2556 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2557 | ep++) | |
2558 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2559 | { | |
32131a9c RK |
2560 | /* The only time we want to replace a PLUS with a REG (this |
2561 | occurs when the constant operand of the PLUS is the negative | |
2562 | of the offset) is when we are inside a MEM. We won't want | |
2563 | to do so at other times because that would change the | |
2564 | structure of the insn in a way that reload can't handle. | |
2565 | We special-case the commonest situation in | |
2566 | eliminate_regs_in_insn, so just replace a PLUS with a | |
2567 | PLUS here, unless inside a MEM. */ | |
a23b64d5 | 2568 | if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT |
32131a9c RK |
2569 | && INTVAL (XEXP (x, 1)) == - ep->previous_offset) |
2570 | return ep->to_rtx; | |
2571 | else | |
38a448ca RH |
2572 | return gen_rtx_PLUS (Pmode, ep->to_rtx, |
2573 | plus_constant (XEXP (x, 1), | |
2574 | ep->previous_offset)); | |
32131a9c RK |
2575 | } |
2576 | ||
2577 | /* If the register is not eliminable, we are done since the other | |
2578 | operand is a constant. */ | |
2579 | return x; | |
2580 | } | |
2581 | ||
2582 | /* If this is part of an address, we want to bring any constant to the | |
2583 | outermost PLUS. We will do this by doing register replacement in | |
2584 | our operands and seeing if a constant shows up in one of them. | |
2585 | ||
dfac187e BS |
2586 | Note that there is no risk of modifying the structure of the insn, |
2587 | since we only get called for its operands, thus we are either | |
2588 | modifying the address inside a MEM, or something like an address | |
2589 | operand of a load-address insn. */ | |
32131a9c RK |
2590 | |
2591 | { | |
ab156144 RH |
2592 | rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true); |
2593 | rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true); | |
32131a9c | 2594 | |
cd7c9015 | 2595 | if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))) |
32131a9c RK |
2596 | { |
2597 | /* If one side is a PLUS and the other side is a pseudo that | |
a8fdc208 | 2598 | didn't get a hard register but has a reg_equiv_constant, |
32131a9c RK |
2599 | we must replace the constant here since it may no longer |
2600 | be in the position of any operand. */ | |
f8cfc6aa | 2601 | if (GET_CODE (new0) == PLUS && REG_P (new1) |
32131a9c RK |
2602 | && REGNO (new1) >= FIRST_PSEUDO_REGISTER |
2603 | && reg_renumber[REGNO (new1)] < 0 | |
2604 | && reg_equiv_constant != 0 | |
2605 | && reg_equiv_constant[REGNO (new1)] != 0) | |
2606 | new1 = reg_equiv_constant[REGNO (new1)]; | |
f8cfc6aa | 2607 | else if (GET_CODE (new1) == PLUS && REG_P (new0) |
32131a9c RK |
2608 | && REGNO (new0) >= FIRST_PSEUDO_REGISTER |
2609 | && reg_renumber[REGNO (new0)] < 0 | |
2610 | && reg_equiv_constant[REGNO (new0)] != 0) | |
2611 | new0 = reg_equiv_constant[REGNO (new0)]; | |
2612 | ||
55d796da | 2613 | new_rtx = form_sum (new0, new1); |
32131a9c RK |
2614 | |
2615 | /* As above, if we are not inside a MEM we do not want to | |
2616 | turn a PLUS into something else. We might try to do so here | |
2617 | for an addition of 0 if we aren't optimizing. */ | |
55d796da KG |
2618 | if (! mem_mode && GET_CODE (new_rtx) != PLUS) |
2619 | return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx); | |
32131a9c | 2620 | else |
55d796da | 2621 | return new_rtx; |
32131a9c RK |
2622 | } |
2623 | } | |
2624 | return x; | |
2625 | ||
981c7390 | 2626 | case MULT: |
05d10675 | 2627 | /* If this is the product of an eliminable register and a |
981c7390 RK |
2628 | constant, apply the distribute law and move the constant out |
2629 | so that we have (plus (mult ..) ..). This is needed in order | |
9faa82d8 | 2630 | to keep load-address insns valid. This case is pathological. |
981c7390 | 2631 | We ignore the possibility of overflow here. */ |
f8cfc6aa | 2632 | if (REG_P (XEXP (x, 0)) |
981c7390 RK |
2633 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER |
2634 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2635 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2636 | ep++) | |
2637 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2638 | { | |
2639 | if (! mem_mode | |
2640 | /* Refs inside notes don't count for this purpose. */ | |
2641 | && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST | |
2642 | || GET_CODE (insn) == INSN_LIST))) | |
2643 | ep->ref_outside_mem = 1; | |
2644 | ||
2645 | return | |
38a448ca | 2646 | plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)), |
981c7390 RK |
2647 | ep->previous_offset * INTVAL (XEXP (x, 1))); |
2648 | } | |
32131a9c | 2649 | |
0f41302f | 2650 | /* ... fall through ... */ |
32131a9c | 2651 | |
32131a9c RK |
2652 | case CALL: |
2653 | case COMPARE: | |
c5c76735 | 2654 | /* See comments before PLUS about handling MINUS. */ |
930aeef3 | 2655 | case MINUS: |
32131a9c RK |
2656 | case DIV: case UDIV: |
2657 | case MOD: case UMOD: | |
2658 | case AND: case IOR: case XOR: | |
45620ed4 RK |
2659 | case ROTATERT: case ROTATE: |
2660 | case ASHIFTRT: case LSHIFTRT: case ASHIFT: | |
32131a9c RK |
2661 | case NE: case EQ: |
2662 | case GE: case GT: case GEU: case GTU: | |
2663 | case LE: case LT: case LEU: case LTU: | |
2664 | { | |
ab156144 RH |
2665 | rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false); |
2666 | rtx new1 = XEXP (x, 1) | |
2667 | ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0; | |
32131a9c RK |
2668 | |
2669 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
38a448ca | 2670 | return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); |
32131a9c RK |
2671 | } |
2672 | return x; | |
2673 | ||
981c7390 RK |
2674 | case EXPR_LIST: |
2675 | /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ | |
2676 | if (XEXP (x, 0)) | |
2677 | { | |
55d796da KG |
2678 | new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true); |
2679 | if (new_rtx != XEXP (x, 0)) | |
13bb79d4 R |
2680 | { |
2681 | /* If this is a REG_DEAD note, it is not valid anymore. | |
2682 | Using the eliminated version could result in creating a | |
2683 | REG_DEAD note for the stack or frame pointer. */ | |
e0c68ce9 | 2684 | if (REG_NOTE_KIND (x) == REG_DEAD) |
13bb79d4 | 2685 | return (XEXP (x, 1) |
ab156144 | 2686 | ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true) |
13bb79d4 R |
2687 | : NULL_RTX); |
2688 | ||
55d796da | 2689 | x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1)); |
13bb79d4 | 2690 | } |
981c7390 RK |
2691 | } |
2692 | ||
0f41302f | 2693 | /* ... fall through ... */ |
981c7390 RK |
2694 | |
2695 | case INSN_LIST: | |
2696 | /* Now do eliminations in the rest of the chain. If this was | |
2697 | an EXPR_LIST, this might result in allocating more memory than is | |
2698 | strictly needed, but it simplifies the code. */ | |
2699 | if (XEXP (x, 1)) | |
2700 | { | |
55d796da KG |
2701 | new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true); |
2702 | if (new_rtx != XEXP (x, 1)) | |
cd7c9015 | 2703 | return |
55d796da | 2704 | gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx); |
981c7390 RK |
2705 | } |
2706 | return x; | |
2707 | ||
32131a9c RK |
2708 | case PRE_INC: |
2709 | case POST_INC: | |
2710 | case PRE_DEC: | |
2711 | case POST_DEC: | |
b098aaf2 UW |
2712 | /* We do not support elimination of a register that is modified. |
2713 | elimination_effects has already make sure that this does not | |
2714 | happen. */ | |
2715 | return x; | |
2716 | ||
2717 | case PRE_MODIFY: | |
2718 | case POST_MODIFY: | |
2719 | /* We do not support elimination of a register that is modified. | |
2720 | elimination_effects has already make sure that this does not | |
2721 | happen. The only remaining case we need to consider here is | |
2722 | that the increment value may be an eliminable register. */ | |
2723 | if (GET_CODE (XEXP (x, 1)) == PLUS | |
2724 | && XEXP (XEXP (x, 1), 0) == XEXP (x, 0)) | |
2725 | { | |
55d796da | 2726 | rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode, |
b098aaf2 UW |
2727 | insn, true); |
2728 | ||
55d796da | 2729 | if (new_rtx != XEXP (XEXP (x, 1), 1)) |
b098aaf2 UW |
2730 | return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0), |
2731 | gen_rtx_PLUS (GET_MODE (x), | |
55d796da | 2732 | XEXP (x, 0), new_rtx)); |
b098aaf2 UW |
2733 | } |
2734 | return x; | |
2735 | ||
32131a9c RK |
2736 | case STRICT_LOW_PART: |
2737 | case NEG: case NOT: | |
2738 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2739 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2740 | case FLOAT: case FIX: | |
2741 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2742 | case ABS: | |
2743 | case SQRT: | |
2744 | case FFS: | |
2928cd7a RH |
2745 | case CLZ: |
2746 | case CTZ: | |
2747 | case POPCOUNT: | |
2748 | case PARITY: | |
167fa32c | 2749 | case BSWAP: |
55d796da KG |
2750 | new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false); |
2751 | if (new_rtx != XEXP (x, 0)) | |
2752 | return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx); | |
32131a9c RK |
2753 | return x; |
2754 | ||
2755 | case SUBREG: | |
ddef6bc7 | 2756 | /* Similar to above processing, but preserve SUBREG_BYTE. |
32131a9c RK |
2757 | Convert (subreg (mem)) to (mem) if not paradoxical. |
2758 | Also, if we have a non-paradoxical (subreg (pseudo)) and the | |
2759 | pseudo didn't get a hard reg, we must replace this with the | |
bd235d86 | 2760 | eliminated version of the memory location because push_reload |
32131a9c | 2761 | may do the replacement in certain circumstances. */ |
f8cfc6aa | 2762 | if (REG_P (SUBREG_REG (x)) |
32131a9c RK |
2763 | && (GET_MODE_SIZE (GET_MODE (x)) |
2764 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2765 | && reg_equiv_memory_loc != 0 | |
2766 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2767 | { | |
55d796da | 2768 | new_rtx = SUBREG_REG (x); |
32131a9c RK |
2769 | } |
2770 | else | |
55d796da | 2771 | new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false); |
32131a9c | 2772 | |
55d796da | 2773 | if (new_rtx != SUBREG_REG (x)) |
32131a9c | 2774 | { |
29ae5012 | 2775 | int x_size = GET_MODE_SIZE (GET_MODE (x)); |
55d796da | 2776 | int new_size = GET_MODE_SIZE (GET_MODE (new_rtx)); |
29ae5012 | 2777 | |
55d796da | 2778 | if (MEM_P (new_rtx) |
6d49a073 | 2779 | && ((x_size < new_size |
1914f5da | 2780 | #ifdef WORD_REGISTER_OPERATIONS |
6d49a073 JW |
2781 | /* On these machines, combine can create rtl of the form |
2782 | (set (subreg:m1 (reg:m2 R) 0) ...) | |
05d10675 | 2783 | where m1 < m2, and expects something interesting to |
6d49a073 JW |
2784 | happen to the entire word. Moreover, it will use the |
2785 | (reg:m2 R) later, expecting all bits to be preserved. | |
05d10675 | 2786 | So if the number of words is the same, preserve the |
bd235d86 | 2787 | subreg so that push_reload can see it. */ |
5d9669fd RK |
2788 | && ! ((x_size - 1) / UNITS_PER_WORD |
2789 | == (new_size -1 ) / UNITS_PER_WORD) | |
1914f5da | 2790 | #endif |
6d49a073 | 2791 | ) |
5d9669fd | 2792 | || x_size == new_size) |
1914f5da | 2793 | ) |
55d796da | 2794 | return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x)); |
32131a9c | 2795 | else |
55d796da | 2796 | return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x)); |
32131a9c RK |
2797 | } |
2798 | ||
2799 | return x; | |
2800 | ||
32131a9c RK |
2801 | case MEM: |
2802 | /* Our only special processing is to pass the mode of the MEM to our | |
2803 | recursive call and copy the flags. While we are here, handle this | |
2804 | case more efficiently. */ | |
f1ec5147 RK |
2805 | return |
2806 | replace_equiv_address_nv (x, | |
ab156144 RH |
2807 | eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), |
2808 | insn, true)); | |
05d10675 | 2809 | |
dfac187e | 2810 | case USE: |
055c7759 | 2811 | /* Handle insn_list USE that a call to a pure function may generate. */ |
55d796da KG |
2812 | new_rtx = eliminate_regs_1 (XEXP (x, 0), 0, insn, false); |
2813 | if (new_rtx != XEXP (x, 0)) | |
2814 | return gen_rtx_USE (GET_MODE (x), new_rtx); | |
055c7759 JDA |
2815 | return x; |
2816 | ||
dfac187e BS |
2817 | case CLOBBER: |
2818 | case ASM_OPERANDS: | |
2819 | case SET: | |
41374e13 | 2820 | gcc_unreachable (); |
dfac187e | 2821 | |
e9a25f70 JL |
2822 | default: |
2823 | break; | |
32131a9c RK |
2824 | } |
2825 | ||
2826 | /* Process each of our operands recursively. If any have changed, make a | |
2827 | copy of the rtx. */ | |
2828 | fmt = GET_RTX_FORMAT (code); | |
2829 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2830 | { | |
2831 | if (*fmt == 'e') | |
2832 | { | |
55d796da KG |
2833 | new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false); |
2834 | if (new_rtx != XEXP (x, i) && ! copied) | |
32131a9c | 2835 | { |
aacd3885 | 2836 | x = shallow_copy_rtx (x); |
32131a9c RK |
2837 | copied = 1; |
2838 | } | |
55d796da | 2839 | XEXP (x, i) = new_rtx; |
32131a9c RK |
2840 | } |
2841 | else if (*fmt == 'E') | |
2842 | { | |
2843 | int copied_vec = 0; | |
2844 | for (j = 0; j < XVECLEN (x, i); j++) | |
2845 | { | |
55d796da KG |
2846 | new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false); |
2847 | if (new_rtx != XVECEXP (x, i, j) && ! copied_vec) | |
32131a9c | 2848 | { |
8f985ec4 ZW |
2849 | rtvec new_v = gen_rtvec_v (XVECLEN (x, i), |
2850 | XVEC (x, i)->elem); | |
32131a9c RK |
2851 | if (! copied) |
2852 | { | |
aacd3885 | 2853 | x = shallow_copy_rtx (x); |
32131a9c RK |
2854 | copied = 1; |
2855 | } | |
2856 | XVEC (x, i) = new_v; | |
2857 | copied_vec = 1; | |
2858 | } | |
55d796da | 2859 | XVECEXP (x, i, j) = new_rtx; |
32131a9c RK |
2860 | } |
2861 | } | |
2862 | } | |
2863 | ||
2864 | return x; | |
2865 | } | |
dfac187e | 2866 | |
ab156144 RH |
2867 | rtx |
2868 | eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn) | |
2869 | { | |
2870 | return eliminate_regs_1 (x, mem_mode, insn, false); | |
2871 | } | |
2872 | ||
dfac187e BS |
2873 | /* Scan rtx X for modifications of elimination target registers. Update |
2874 | the table of eliminables to reflect the changed state. MEM_MODE is | |
2875 | the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */ | |
2876 | ||
2877 | static void | |
0c20a65f | 2878 | elimination_effects (rtx x, enum machine_mode mem_mode) |
dfac187e BS |
2879 | { |
2880 | enum rtx_code code = GET_CODE (x); | |
2881 | struct elim_table *ep; | |
2882 | int regno; | |
2883 | int i, j; | |
2884 | const char *fmt; | |
2885 | ||
2886 | switch (code) | |
2887 | { | |
2888 | case CONST_INT: | |
2889 | case CONST_DOUBLE: | |
091a3ac7 | 2890 | case CONST_FIXED: |
69ef87e2 | 2891 | case CONST_VECTOR: |
dfac187e BS |
2892 | case CONST: |
2893 | case SYMBOL_REF: | |
2894 | case CODE_LABEL: | |
2895 | case PC: | |
2896 | case CC0: | |
2897 | case ASM_INPUT: | |
2898 | case ADDR_VEC: | |
2899 | case ADDR_DIFF_VEC: | |
2900 | case RETURN: | |
2901 | return; | |
2902 | ||
dfac187e BS |
2903 | case REG: |
2904 | regno = REGNO (x); | |
2905 | ||
2906 | /* First handle the case where we encounter a bare register that | |
2907 | is eliminable. Replace it with a PLUS. */ | |
2908 | if (regno < FIRST_PSEUDO_REGISTER) | |
2909 | { | |
2910 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2911 | ep++) | |
2912 | if (ep->from_rtx == x && ep->can_eliminate) | |
2913 | { | |
2914 | if (! mem_mode) | |
2915 | ep->ref_outside_mem = 1; | |
2916 | return; | |
2917 | } | |
2918 | ||
2919 | } | |
2920 | else if (reg_renumber[regno] < 0 && reg_equiv_constant | |
2921 | && reg_equiv_constant[regno] | |
92a21141 | 2922 | && ! function_invariant_p (reg_equiv_constant[regno])) |
dfac187e BS |
2923 | elimination_effects (reg_equiv_constant[regno], mem_mode); |
2924 | return; | |
2925 | ||
2926 | case PRE_INC: | |
2927 | case POST_INC: | |
2928 | case PRE_DEC: | |
2929 | case POST_DEC: | |
4b983fdc RH |
2930 | case POST_MODIFY: |
2931 | case PRE_MODIFY: | |
b098aaf2 UW |
2932 | /* If we modify the source of an elimination rule, disable it. */ |
2933 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2934 | if (ep->from_rtx == XEXP (x, 0)) | |
2935 | ep->can_eliminate = 0; | |
2936 | ||
2937 | /* If we modify the target of an elimination rule by adding a constant, | |
2938 | update its offset. If we modify the target in any other way, we'll | |
2939 | have to disable the rule as well. */ | |
dfac187e BS |
2940 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
2941 | if (ep->to_rtx == XEXP (x, 0)) | |
2942 | { | |
2943 | int size = GET_MODE_SIZE (mem_mode); | |
2944 | ||
2945 | /* If more bytes than MEM_MODE are pushed, account for them. */ | |
2946 | #ifdef PUSH_ROUNDING | |
2947 | if (ep->to_rtx == stack_pointer_rtx) | |
2948 | size = PUSH_ROUNDING (size); | |
2949 | #endif | |
2950 | if (code == PRE_DEC || code == POST_DEC) | |
2951 | ep->offset += size; | |
4b983fdc | 2952 | else if (code == PRE_INC || code == POST_INC) |
dfac187e | 2953 | ep->offset -= size; |
b098aaf2 UW |
2954 | else if (code == PRE_MODIFY || code == POST_MODIFY) |
2955 | { | |
2956 | if (GET_CODE (XEXP (x, 1)) == PLUS | |
2957 | && XEXP (x, 0) == XEXP (XEXP (x, 1), 0) | |
2958 | && CONST_INT_P (XEXP (XEXP (x, 1), 1))) | |
2959 | ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1)); | |
2960 | else | |
2961 | ep->can_eliminate = 0; | |
2962 | } | |
dfac187e BS |
2963 | } |
2964 | ||
4b983fdc RH |
2965 | /* These two aren't unary operators. */ |
2966 | if (code == POST_MODIFY || code == PRE_MODIFY) | |
2967 | break; | |
2968 | ||
dfac187e BS |
2969 | /* Fall through to generic unary operation case. */ |
2970 | case STRICT_LOW_PART: | |
2971 | case NEG: case NOT: | |
2972 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2973 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2974 | case FLOAT: case FIX: | |
2975 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2976 | case ABS: | |
2977 | case SQRT: | |
2978 | case FFS: | |
2928cd7a RH |
2979 | case CLZ: |
2980 | case CTZ: | |
2981 | case POPCOUNT: | |
2982 | case PARITY: | |
167fa32c | 2983 | case BSWAP: |
dfac187e BS |
2984 | elimination_effects (XEXP (x, 0), mem_mode); |
2985 | return; | |
2986 | ||
2987 | case SUBREG: | |
f8cfc6aa | 2988 | if (REG_P (SUBREG_REG (x)) |
dfac187e BS |
2989 | && (GET_MODE_SIZE (GET_MODE (x)) |
2990 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2991 | && reg_equiv_memory_loc != 0 | |
2992 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2993 | return; | |
2994 | ||
2995 | elimination_effects (SUBREG_REG (x), mem_mode); | |
2996 | return; | |
2997 | ||
2998 | case USE: | |
2999 | /* If using a register that is the source of an eliminate we still | |
3000 | think can be performed, note it cannot be performed since we don't | |
3001 | know how this register is used. */ | |
3002 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3003 | if (ep->from_rtx == XEXP (x, 0)) | |
3004 | ep->can_eliminate = 0; | |
3005 | ||
3006 | elimination_effects (XEXP (x, 0), mem_mode); | |
3007 | return; | |
3008 | ||
3009 | case CLOBBER: | |
3010 | /* If clobbering a register that is the replacement register for an | |
3011 | elimination we still think can be performed, note that it cannot | |
3012 | be performed. Otherwise, we need not be concerned about it. */ | |
3013 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3014 | if (ep->to_rtx == XEXP (x, 0)) | |
3015 | ep->can_eliminate = 0; | |
3016 | ||
3017 | elimination_effects (XEXP (x, 0), mem_mode); | |
3018 | return; | |
3019 | ||
3020 | case SET: | |
3021 | /* Check for setting a register that we know about. */ | |
f8cfc6aa | 3022 | if (REG_P (SET_DEST (x))) |
dfac187e BS |
3023 | { |
3024 | /* See if this is setting the replacement register for an | |
3025 | elimination. | |
3026 | ||
3027 | If DEST is the hard frame pointer, we do nothing because we | |
3028 | assume that all assignments to the frame pointer are for | |
3029 | non-local gotos and are being done at a time when they are valid | |
3030 | and do not disturb anything else. Some machines want to | |
3031 | eliminate a fake argument pointer (or even a fake frame pointer) | |
3032 | with either the real frame or the stack pointer. Assignments to | |
3033 | the hard frame pointer must not prevent this elimination. */ | |
3034 | ||
3035 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
3036 | ep++) | |
3037 | if (ep->to_rtx == SET_DEST (x) | |
3038 | && SET_DEST (x) != hard_frame_pointer_rtx) | |
3039 | { | |
3040 | /* If it is being incremented, adjust the offset. Otherwise, | |
3041 | this elimination can't be done. */ | |
3042 | rtx src = SET_SRC (x); | |
3043 | ||
3044 | if (GET_CODE (src) == PLUS | |
3045 | && XEXP (src, 0) == SET_DEST (x) | |
3046 | && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
3047 | ep->offset -= INTVAL (XEXP (src, 1)); | |
3048 | else | |
3049 | ep->can_eliminate = 0; | |
3050 | } | |
3051 | } | |
3052 | ||
3053 | elimination_effects (SET_DEST (x), 0); | |
3054 | elimination_effects (SET_SRC (x), 0); | |
3055 | return; | |
3056 | ||
3057 | case MEM: | |
dfac187e BS |
3058 | /* Our only special processing is to pass the mode of the MEM to our |
3059 | recursive call. */ | |
3060 | elimination_effects (XEXP (x, 0), GET_MODE (x)); | |
3061 | return; | |
3062 | ||
3063 | default: | |
3064 | break; | |
3065 | } | |
3066 | ||
3067 | fmt = GET_RTX_FORMAT (code); | |
3068 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
3069 | { | |
3070 | if (*fmt == 'e') | |
3071 | elimination_effects (XEXP (x, i), mem_mode); | |
3072 | else if (*fmt == 'E') | |
3073 | for (j = 0; j < XVECLEN (x, i); j++) | |
3074 | elimination_effects (XVECEXP (x, i, j), mem_mode); | |
3075 | } | |
3076 | } | |
3077 | ||
3078 | /* Descend through rtx X and verify that no references to eliminable registers | |
3079 | remain. If any do remain, mark the involved register as not | |
3080 | eliminable. */ | |
1d813780 | 3081 | |
dfac187e | 3082 | static void |
0c20a65f | 3083 | check_eliminable_occurrences (rtx x) |
dfac187e BS |
3084 | { |
3085 | const char *fmt; | |
3086 | int i; | |
3087 | enum rtx_code code; | |
3088 | ||
3089 | if (x == 0) | |
3090 | return; | |
1d7254c5 | 3091 | |
dfac187e BS |
3092 | code = GET_CODE (x); |
3093 | ||
3094 | if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
3095 | { | |
3096 | struct elim_table *ep; | |
3097 | ||
3098 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
761fa0f7 | 3099 | if (ep->from_rtx == x) |
dfac187e BS |
3100 | ep->can_eliminate = 0; |
3101 | return; | |
3102 | } | |
1d7254c5 | 3103 | |
dfac187e BS |
3104 | fmt = GET_RTX_FORMAT (code); |
3105 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
3106 | { | |
3107 | if (*fmt == 'e') | |
3108 | check_eliminable_occurrences (XEXP (x, i)); | |
3109 | else if (*fmt == 'E') | |
3110 | { | |
3111 | int j; | |
3112 | for (j = 0; j < XVECLEN (x, i); j++) | |
3113 | check_eliminable_occurrences (XVECEXP (x, i, j)); | |
3114 | } | |
3115 | } | |
3116 | } | |
32131a9c RK |
3117 | \f |
3118 | /* Scan INSN and eliminate all eliminable registers in it. | |
3119 | ||
3120 | If REPLACE is nonzero, do the replacement destructively. Also | |
3121 | delete the insn as dead it if it is setting an eliminable register. | |
3122 | ||
3123 | If REPLACE is zero, do all our allocations in reload_obstack. | |
3124 | ||
3125 | If no eliminations were done and this insn doesn't require any elimination | |
3126 | processing (these are not identical conditions: it might be updating sp, | |
3127 | but not referencing fp; this needs to be seen during reload_as_needed so | |
3128 | that the offset between fp and sp can be taken into consideration), zero | |
3129 | is returned. Otherwise, 1 is returned. */ | |
3130 | ||
3131 | static int | |
0c20a65f | 3132 | eliminate_regs_in_insn (rtx insn, int replace) |
32131a9c | 3133 | { |
dfac187e | 3134 | int icode = recog_memoized (insn); |
32131a9c | 3135 | rtx old_body = PATTERN (insn); |
dfac187e | 3136 | int insn_is_asm = asm_noperands (old_body) >= 0; |
774672d2 | 3137 | rtx old_set = single_set (insn); |
32131a9c RK |
3138 | rtx new_body; |
3139 | int val = 0; | |
4977bab6 | 3140 | int i; |
dfac187e BS |
3141 | rtx substed_operand[MAX_RECOG_OPERANDS]; |
3142 | rtx orig_operand[MAX_RECOG_OPERANDS]; | |
32131a9c | 3143 | struct elim_table *ep; |
ab156144 | 3144 | rtx plus_src, plus_cst_src; |
32131a9c | 3145 | |
dfac187e BS |
3146 | if (! insn_is_asm && icode < 0) |
3147 | { | |
41374e13 NS |
3148 | gcc_assert (GET_CODE (PATTERN (insn)) == USE |
3149 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
3150 | || GET_CODE (PATTERN (insn)) == ADDR_VEC | |
3151 | || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | |
3152 | || GET_CODE (PATTERN (insn)) == ASM_INPUT); | |
3153 | return 0; | |
dfac187e BS |
3154 | } |
3155 | ||
f8cfc6aa | 3156 | if (old_set != 0 && REG_P (SET_DEST (old_set)) |
774672d2 | 3157 | && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) |
32131a9c RK |
3158 | { |
3159 | /* Check for setting an eliminable register. */ | |
3160 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
774672d2 | 3161 | if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) |
32131a9c | 3162 | { |
dd1eab0a RK |
3163 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
3164 | /* If this is setting the frame pointer register to the | |
3165 | hardware frame pointer register and this is an elimination | |
3166 | that will be done (tested above), this insn is really | |
3167 | adjusting the frame pointer downward to compensate for | |
3168 | the adjustment done before a nonlocal goto. */ | |
3169 | if (ep->from == FRAME_POINTER_REGNUM | |
3170 | && ep->to == HARD_FRAME_POINTER_REGNUM) | |
3171 | { | |
75eefe3f UW |
3172 | rtx base = SET_SRC (old_set); |
3173 | rtx base_insn = insn; | |
b19ee4bd | 3174 | HOST_WIDE_INT offset = 0; |
75eefe3f UW |
3175 | |
3176 | while (base != ep->to_rtx) | |
8026ebba | 3177 | { |
75eefe3f UW |
3178 | rtx prev_insn, prev_set; |
3179 | ||
3180 | if (GET_CODE (base) == PLUS | |
3181 | && GET_CODE (XEXP (base, 1)) == CONST_INT) | |
3182 | { | |
3183 | offset += INTVAL (XEXP (base, 1)); | |
3184 | base = XEXP (base, 0); | |
3185 | } | |
3186 | else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0 | |
3187 | && (prev_set = single_set (prev_insn)) != 0 | |
3188 | && rtx_equal_p (SET_DEST (prev_set), base)) | |
3189 | { | |
3190 | base = SET_SRC (prev_set); | |
3191 | base_insn = prev_insn; | |
3192 | } | |
3193 | else | |
3194 | break; | |
8026ebba | 3195 | } |
dd1eab0a | 3196 | |
75eefe3f | 3197 | if (base == ep->to_rtx) |
dd1eab0a | 3198 | { |
c77fbfbe GK |
3199 | rtx src |
3200 | = plus_constant (ep->to_rtx, offset - ep->offset); | |
3201 | ||
3202 | new_body = old_body; | |
3203 | if (! replace) | |
3204 | { | |
3205 | new_body = copy_insn (old_body); | |
3206 | if (REG_NOTES (insn)) | |
3207 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3208 | } | |
3209 | PATTERN (insn) = new_body; | |
3210 | old_set = single_set (insn); | |
3211 | ||
3212 | /* First see if this insn remains valid when we | |
3213 | make the change. If not, keep the INSN_CODE | |
3214 | the same and let reload fit it up. */ | |
3215 | validate_change (insn, &SET_SRC (old_set), src, 1); | |
3216 | validate_change (insn, &SET_DEST (old_set), | |
3217 | ep->to_rtx, 1); | |
3218 | if (! apply_change_group ()) | |
dd1eab0a | 3219 | { |
c77fbfbe GK |
3220 | SET_SRC (old_set) = src; |
3221 | SET_DEST (old_set) = ep->to_rtx; | |
dd1eab0a RK |
3222 | } |
3223 | ||
3224 | val = 1; | |
3225 | goto done; | |
3226 | } | |
3227 | } | |
3228 | #endif | |
3229 | ||
32131a9c RK |
3230 | /* In this case this insn isn't serving a useful purpose. We |
3231 | will delete it in reload_as_needed once we know that this | |
3232 | elimination is, in fact, being done. | |
3233 | ||
abc95ed3 | 3234 | If REPLACE isn't set, we can't delete this insn, but needn't |
32131a9c RK |
3235 | process it since it won't be used unless something changes. */ |
3236 | if (replace) | |
8a34409d | 3237 | { |
1d7254c5 | 3238 | delete_dead_insn (insn); |
8a34409d RH |
3239 | return 1; |
3240 | } | |
32131a9c RK |
3241 | val = 1; |
3242 | goto done; | |
3243 | } | |
aa5524a9 | 3244 | } |
32131a9c | 3245 | |
aa5524a9 | 3246 | /* We allow one special case which happens to work on all machines we |
ace3ffcd KH |
3247 | currently support: a single set with the source or a REG_EQUAL |
3248 | note being a PLUS of an eliminable register and a constant. */ | |
ab156144 | 3249 | plus_src = plus_cst_src = 0; |
f8cfc6aa | 3250 | if (old_set && REG_P (SET_DEST (old_set))) |
aa5524a9 | 3251 | { |
ab156144 | 3252 | if (GET_CODE (SET_SRC (old_set)) == PLUS) |
ace3ffcd | 3253 | plus_src = SET_SRC (old_set); |
7efd40b5 | 3254 | /* First see if the source is of the form (plus (...) CST). */ |
ab156144 | 3255 | if (plus_src |
7efd40b5 | 3256 | && GET_CODE (XEXP (plus_src, 1)) == CONST_INT) |
ab156144 RH |
3257 | plus_cst_src = plus_src; |
3258 | else if (REG_P (SET_SRC (old_set)) | |
3259 | || plus_src) | |
ace3ffcd KH |
3260 | { |
3261 | /* Otherwise, see if we have a REG_EQUAL note of the form | |
7efd40b5 | 3262 | (plus (...) CST). */ |
ace3ffcd KH |
3263 | rtx links; |
3264 | for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) | |
3265 | { | |
7c11b28c BS |
3266 | if ((REG_NOTE_KIND (links) == REG_EQUAL |
3267 | || REG_NOTE_KIND (links) == REG_EQUIV) | |
ace3ffcd | 3268 | && GET_CODE (XEXP (links, 0)) == PLUS |
7efd40b5 | 3269 | && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT) |
ace3ffcd | 3270 | { |
ab156144 | 3271 | plus_cst_src = XEXP (links, 0); |
ace3ffcd KH |
3272 | break; |
3273 | } | |
3274 | } | |
3275 | } | |
7efd40b5 UW |
3276 | |
3277 | /* Check that the first operand of the PLUS is a hard reg or | |
3278 | the lowpart subreg of one. */ | |
3279 | if (plus_cst_src) | |
3280 | { | |
3281 | rtx reg = XEXP (plus_cst_src, 0); | |
3282 | if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg)) | |
3283 | reg = SUBREG_REG (reg); | |
3284 | ||
3285 | if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER) | |
3286 | plus_cst_src = 0; | |
3287 | } | |
ace3ffcd | 3288 | } |
ab156144 | 3289 | if (plus_cst_src) |
ace3ffcd | 3290 | { |
ab156144 RH |
3291 | rtx reg = XEXP (plus_cst_src, 0); |
3292 | HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1)); | |
32131a9c | 3293 | |
7efd40b5 UW |
3294 | if (GET_CODE (reg) == SUBREG) |
3295 | reg = SUBREG_REG (reg); | |
3296 | ||
aa5524a9 BS |
3297 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3298 | if (ep->from_rtx == reg && ep->can_eliminate) | |
3299 | { | |
7efd40b5 | 3300 | rtx to_rtx = ep->to_rtx; |
aa5524a9 | 3301 | offset += ep->offset; |
231a1e52 | 3302 | offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src)); |
32131a9c | 3303 | |
7efd40b5 UW |
3304 | if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG) |
3305 | to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)), | |
3306 | to_rtx); | |
8c1249f9 PB |
3307 | /* If we have a nonzero offset, and the source is already |
3308 | a simple REG, the following transformation would | |
3309 | increase the cost of the insn by replacing a simple REG | |
3310 | with (plus (reg sp) CST). So try only when we already | |
3311 | had a PLUS before. */ | |
551d6929 | 3312 | if (offset == 0 || plus_src) |
8c1249f9 | 3313 | { |
551d6929 UW |
3314 | rtx new_src = plus_constant (to_rtx, offset); |
3315 | ||
8c1249f9 PB |
3316 | new_body = old_body; |
3317 | if (! replace) | |
3318 | { | |
3319 | new_body = copy_insn (old_body); | |
3320 | if (REG_NOTES (insn)) | |
3321 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3322 | } | |
3323 | PATTERN (insn) = new_body; | |
3324 | old_set = single_set (insn); | |
3325 | ||
551d6929 UW |
3326 | /* First see if this insn remains valid when we make the |
3327 | change. If not, try to replace the whole pattern with | |
3328 | a simple set (this may help if the original insn was a | |
3329 | PARALLEL that was only recognized as single_set due to | |
3330 | REG_UNUSED notes). If this isn't valid either, keep | |
3331 | the INSN_CODE the same and let reload fix it up. */ | |
3332 | if (!validate_change (insn, &SET_SRC (old_set), new_src, 0)) | |
3333 | { | |
3334 | rtx new_pat = gen_rtx_SET (VOIDmode, | |
3335 | SET_DEST (old_set), new_src); | |
3336 | ||
3337 | if (!validate_change (insn, &PATTERN (insn), new_pat, 0)) | |
3338 | SET_SRC (old_set) = new_src; | |
3339 | } | |
8c1249f9 | 3340 | } |
ace3ffcd KH |
3341 | else |
3342 | break; | |
3343 | ||
aa5524a9 BS |
3344 | val = 1; |
3345 | /* This can't have an effect on elimination offsets, so skip right | |
3346 | to the end. */ | |
3347 | goto done; | |
3348 | } | |
32131a9c RK |
3349 | } |
3350 | ||
dfac187e BS |
3351 | /* Determine the effects of this insn on elimination offsets. */ |
3352 | elimination_effects (old_body, 0); | |
3353 | ||
3354 | /* Eliminate all eliminable registers occurring in operands that | |
3355 | can be handled by reload. */ | |
3356 | extract_insn (insn); | |
dfac187e BS |
3357 | for (i = 0; i < recog_data.n_operands; i++) |
3358 | { | |
3359 | orig_operand[i] = recog_data.operand[i]; | |
3360 | substed_operand[i] = recog_data.operand[i]; | |
3361 | ||
3362 | /* For an asm statement, every operand is eliminable. */ | |
3363 | if (insn_is_asm || insn_data[icode].operand[i].eliminable) | |
3364 | { | |
ab156144 RH |
3365 | bool is_set_src, in_plus; |
3366 | ||
dfac187e BS |
3367 | /* Check for setting a register that we know about. */ |
3368 | if (recog_data.operand_type[i] != OP_IN | |
f8cfc6aa | 3369 | && REG_P (orig_operand[i])) |
dfac187e BS |
3370 | { |
3371 | /* If we are assigning to a register that can be eliminated, it | |
3372 | must be as part of a PARALLEL, since the code above handles | |
3373 | single SETs. We must indicate that we can no longer | |
3374 | eliminate this reg. */ | |
3375 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
3376 | ep++) | |
761fa0f7 | 3377 | if (ep->from_rtx == orig_operand[i]) |
dfac187e BS |
3378 | ep->can_eliminate = 0; |
3379 | } | |
3380 | ||
ab156144 RH |
3381 | /* Companion to the above plus substitution, we can allow |
3382 | invariants as the source of a plain move. */ | |
3383 | is_set_src = false; | |
3384 | if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set)) | |
3385 | is_set_src = true; | |
3386 | in_plus = false; | |
3387 | if (plus_src | |
3388 | && (recog_data.operand_loc[i] == &XEXP (plus_src, 0) | |
3389 | || recog_data.operand_loc[i] == &XEXP (plus_src, 1))) | |
3390 | in_plus = true; | |
3391 | ||
3392 | substed_operand[i] | |
3393 | = eliminate_regs_1 (recog_data.operand[i], 0, | |
3394 | replace ? insn : NULL_RTX, | |
3395 | is_set_src || in_plus); | |
dfac187e | 3396 | if (substed_operand[i] != orig_operand[i]) |
4977bab6 | 3397 | val = 1; |
dfac187e BS |
3398 | /* Terminate the search in check_eliminable_occurrences at |
3399 | this point. */ | |
3400 | *recog_data.operand_loc[i] = 0; | |
3401 | ||
c41c1387 RS |
3402 | /* If an output operand changed from a REG to a MEM and INSN is an |
3403 | insn, write a CLOBBER insn. */ | |
dfac187e | 3404 | if (recog_data.operand_type[i] != OP_IN |
f8cfc6aa | 3405 | && REG_P (orig_operand[i]) |
3c0cb5de | 3406 | && MEM_P (substed_operand[i]) |
dfac187e | 3407 | && replace) |
c41c1387 | 3408 | emit_insn_after (gen_clobber (orig_operand[i]), insn); |
dfac187e BS |
3409 | } |
3410 | } | |
3411 | ||
3412 | for (i = 0; i < recog_data.n_dups; i++) | |
3413 | *recog_data.dup_loc[i] | |
1d7254c5 | 3414 | = *recog_data.operand_loc[(int) recog_data.dup_num[i]]; |
dfac187e BS |
3415 | |
3416 | /* If any eliminable remain, they aren't eliminable anymore. */ | |
3417 | check_eliminable_occurrences (old_body); | |
32131a9c | 3418 | |
dfac187e BS |
3419 | /* Substitute the operands; the new values are in the substed_operand |
3420 | array. */ | |
3421 | for (i = 0; i < recog_data.n_operands; i++) | |
3422 | *recog_data.operand_loc[i] = substed_operand[i]; | |
3423 | for (i = 0; i < recog_data.n_dups; i++) | |
1d7254c5 | 3424 | *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]]; |
32131a9c | 3425 | |
dfac187e | 3426 | /* If we are replacing a body that was a (set X (plus Y Z)), try to |
32131a9c RK |
3427 | re-recognize the insn. We do this in case we had a simple addition |
3428 | but now can do this as a load-address. This saves an insn in this | |
dfac187e BS |
3429 | common case. |
3430 | If re-recognition fails, the old insn code number will still be used, | |
3431 | and some register operands may have changed into PLUS expressions. | |
3432 | These will be handled by find_reloads by loading them into a register | |
1d7254c5 | 3433 | again. */ |
32131a9c | 3434 | |
dfac187e | 3435 | if (val) |
32131a9c | 3436 | { |
7c791b13 RK |
3437 | /* If we aren't replacing things permanently and we changed something, |
3438 | make another copy to ensure that all the RTL is new. Otherwise | |
3439 | things can go wrong if find_reload swaps commutative operands | |
0f41302f | 3440 | and one is inside RTL that has been copied while the other is not. */ |
dfac187e BS |
3441 | new_body = old_body; |
3442 | if (! replace) | |
1b3b5765 BS |
3443 | { |
3444 | new_body = copy_insn (old_body); | |
3445 | if (REG_NOTES (insn)) | |
3446 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3447 | } | |
dfac187e | 3448 | PATTERN (insn) = new_body; |
7c791b13 | 3449 | |
774672d2 RK |
3450 | /* If we had a move insn but now we don't, rerecognize it. This will |
3451 | cause spurious re-recognition if the old move had a PARALLEL since | |
3452 | the new one still will, but we can't call single_set without | |
3453 | having put NEW_BODY into the insn and the re-recognition won't | |
3454 | hurt in this rare case. */ | |
dfac187e BS |
3455 | /* ??? Why this huge if statement - why don't we just rerecognize the |
3456 | thing always? */ | |
3457 | if (! insn_is_asm | |
3458 | && old_set != 0 | |
f8cfc6aa | 3459 | && ((REG_P (SET_SRC (old_set)) |
774672d2 | 3460 | && (GET_CODE (new_body) != SET |
f8cfc6aa | 3461 | || !REG_P (SET_SRC (new_body)))) |
774672d2 | 3462 | /* If this was a load from or store to memory, compare |
1ccbefce RH |
3463 | the MEM in recog_data.operand to the one in the insn. |
3464 | If they are not equal, then rerecognize the insn. */ | |
774672d2 | 3465 | || (old_set != 0 |
3c0cb5de | 3466 | && ((MEM_P (SET_SRC (old_set)) |
1ccbefce | 3467 | && SET_SRC (old_set) != recog_data.operand[1]) |
3c0cb5de | 3468 | || (MEM_P (SET_DEST (old_set)) |
1ccbefce | 3469 | && SET_DEST (old_set) != recog_data.operand[0]))) |
774672d2 RK |
3470 | /* If this was an add insn before, rerecognize. */ |
3471 | || GET_CODE (SET_SRC (old_set)) == PLUS)) | |
4a5d0fb5 | 3472 | { |
dfac187e | 3473 | int new_icode = recog (PATTERN (insn), insn, 0); |
a5ee7cba AM |
3474 | if (new_icode >= 0) |
3475 | INSN_CODE (insn) = new_icode; | |
4a5d0fb5 | 3476 | } |
dfac187e | 3477 | } |
32131a9c | 3478 | |
dfac187e BS |
3479 | /* Restore the old body. If there were any changes to it, we made a copy |
3480 | of it while the changes were still in place, so we'll correctly return | |
3481 | a modified insn below. */ | |
3482 | if (! replace) | |
3483 | { | |
3484 | /* Restore the old body. */ | |
3485 | for (i = 0; i < recog_data.n_operands; i++) | |
3486 | *recog_data.operand_loc[i] = orig_operand[i]; | |
3487 | for (i = 0; i < recog_data.n_dups; i++) | |
1d7254c5 | 3488 | *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]]; |
32131a9c | 3489 | } |
a8fdc208 | 3490 | |
dfac187e BS |
3491 | /* Update all elimination pairs to reflect the status after the current |
3492 | insn. The changes we make were determined by the earlier call to | |
3493 | elimination_effects. | |
a8efe40d | 3494 | |
423adbb9 | 3495 | We also detect cases where register elimination cannot be done, |
32131a9c RK |
3496 | namely, if a register would be both changed and referenced outside a MEM |
3497 | in the resulting insn since such an insn is often undefined and, even if | |
3498 | not, we cannot know what meaning will be given to it. Note that it is | |
3499 | valid to have a register used in an address in an insn that changes it | |
3500 | (presumably with a pre- or post-increment or decrement). | |
3501 | ||
3502 | If anything changes, return nonzero. */ | |
3503 | ||
32131a9c RK |
3504 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3505 | { | |
3506 | if (ep->previous_offset != ep->offset && ep->ref_outside_mem) | |
3507 | ep->can_eliminate = 0; | |
3508 | ||
3509 | ep->ref_outside_mem = 0; | |
3510 | ||
3511 | if (ep->previous_offset != ep->offset) | |
3512 | val = 1; | |
32131a9c RK |
3513 | } |
3514 | ||
3515 | done: | |
9faa82d8 | 3516 | /* If we changed something, perform elimination in REG_NOTES. This is |
05b4c365 RK |
3517 | needed even when REPLACE is zero because a REG_DEAD note might refer |
3518 | to a register that we eliminate and could cause a different number | |
3519 | of spill registers to be needed in the final reload pass than in | |
3520 | the pre-passes. */ | |
20748cab | 3521 | if (val && REG_NOTES (insn) != 0) |
ab156144 RH |
3522 | REG_NOTES (insn) |
3523 | = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true); | |
05b4c365 | 3524 | |
32131a9c RK |
3525 | return val; |
3526 | } | |
3527 | ||
cb2afeb3 R |
3528 | /* Loop through all elimination pairs. |
3529 | Recalculate the number not at initial offset. | |
3530 | ||
3531 | Compute the maximum offset (minimum offset if the stack does not | |
3532 | grow downward) for each elimination pair. */ | |
3533 | ||
3534 | static void | |
0c20a65f | 3535 | update_eliminable_offsets (void) |
cb2afeb3 R |
3536 | { |
3537 | struct elim_table *ep; | |
3538 | ||
3539 | num_not_at_initial_offset = 0; | |
3540 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3541 | { | |
3542 | ep->previous_offset = ep->offset; | |
3543 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3544 | num_not_at_initial_offset++; | |
cb2afeb3 R |
3545 | } |
3546 | } | |
3547 | ||
32131a9c RK |
3548 | /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register |
3549 | replacement we currently believe is valid, mark it as not eliminable if X | |
3550 | modifies DEST in any way other than by adding a constant integer to it. | |
3551 | ||
3552 | If DEST is the frame pointer, we do nothing because we assume that | |
3ec2ea3e DE |
3553 | all assignments to the hard frame pointer are nonlocal gotos and are being |
3554 | done at a time when they are valid and do not disturb anything else. | |
32131a9c | 3555 | Some machines want to eliminate a fake argument pointer with either the |
3ec2ea3e DE |
3556 | frame or stack pointer. Assignments to the hard frame pointer must not |
3557 | prevent this elimination. | |
32131a9c RK |
3558 | |
3559 | Called via note_stores from reload before starting its passes to scan | |
3560 | the insns of the function. */ | |
3561 | ||
3562 | static void | |
7bc980e1 | 3563 | mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED) |
32131a9c | 3564 | { |
b3694847 | 3565 | unsigned int i; |
32131a9c RK |
3566 | |
3567 | /* A SUBREG of a hard register here is just changing its mode. We should | |
3568 | not see a SUBREG of an eliminable hard register, but check just in | |
3569 | case. */ | |
3570 | if (GET_CODE (dest) == SUBREG) | |
3571 | dest = SUBREG_REG (dest); | |
3572 | ||
3ec2ea3e | 3573 | if (dest == hard_frame_pointer_rtx) |
32131a9c RK |
3574 | return; |
3575 | ||
3576 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3577 | if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx | |
3578 | && (GET_CODE (x) != SET | |
3579 | || GET_CODE (SET_SRC (x)) != PLUS | |
3580 | || XEXP (SET_SRC (x), 0) != dest | |
3581 | || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT)) | |
3582 | { | |
3583 | reg_eliminate[i].can_eliminate_previous | |
3584 | = reg_eliminate[i].can_eliminate = 0; | |
3585 | num_eliminable--; | |
3586 | } | |
3587 | } | |
09dd1133 | 3588 | |
c47f5ea5 BS |
3589 | /* Verify that the initial elimination offsets did not change since the |
3590 | last call to set_initial_elim_offsets. This is used to catch cases | |
3591 | where something illegal happened during reload_as_needed that could | |
3592 | cause incorrect code to be generated if we did not check for it. */ | |
c8d8ed65 | 3593 | |
9f938de1 | 3594 | static bool |
0c20a65f | 3595 | verify_initial_elim_offsets (void) |
c47f5ea5 | 3596 | { |
b19ee4bd | 3597 | HOST_WIDE_INT t; |
c47f5ea5 | 3598 | |
9f938de1 UW |
3599 | if (!num_eliminable) |
3600 | return true; | |
3601 | ||
c47f5ea5 | 3602 | #ifdef ELIMINABLE_REGS |
67730e23 ILT |
3603 | { |
3604 | struct elim_table *ep; | |
3605 | ||
3606 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3607 | { | |
3608 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t); | |
3609 | if (t != ep->initial_offset) | |
3610 | return false; | |
3611 | } | |
3612 | } | |
c47f5ea5 BS |
3613 | #else |
3614 | INITIAL_FRAME_POINTER_OFFSET (t); | |
9f938de1 UW |
3615 | if (t != reg_eliminate[0].initial_offset) |
3616 | return false; | |
05d10675 | 3617 | #endif |
9f938de1 UW |
3618 | |
3619 | return true; | |
c47f5ea5 BS |
3620 | } |
3621 | ||
09dd1133 | 3622 | /* Reset all offsets on eliminable registers to their initial values. */ |
1d813780 | 3623 | |
09dd1133 | 3624 | static void |
0c20a65f | 3625 | set_initial_elim_offsets (void) |
09dd1133 | 3626 | { |
1f3b1e1a | 3627 | struct elim_table *ep = reg_eliminate; |
09dd1133 BS |
3628 | |
3629 | #ifdef ELIMINABLE_REGS | |
1f3b1e1a | 3630 | for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
09dd1133 BS |
3631 | { |
3632 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); | |
1f3b1e1a | 3633 | ep->previous_offset = ep->offset = ep->initial_offset; |
09dd1133 BS |
3634 | } |
3635 | #else | |
1f3b1e1a JL |
3636 | INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset); |
3637 | ep->previous_offset = ep->offset = ep->initial_offset; | |
09dd1133 BS |
3638 | #endif |
3639 | ||
3640 | num_not_at_initial_offset = 0; | |
1f3b1e1a | 3641 | } |
09dd1133 | 3642 | |
58767f00 RH |
3643 | /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */ |
3644 | ||
3645 | static void | |
3646 | set_initial_eh_label_offset (rtx label) | |
3647 | { | |
3648 | set_label_offsets (label, NULL_RTX, 1); | |
3649 | } | |
3650 | ||
1f3b1e1a JL |
3651 | /* Initialize the known label offsets. |
3652 | Set a known offset for each forced label to be at the initial offset | |
3653 | of each elimination. We do this because we assume that all | |
3654 | computed jumps occur from a location where each elimination is | |
3655 | at its initial offset. | |
3656 | For all other labels, show that we don't know the offsets. */ | |
09dd1133 | 3657 | |
1f3b1e1a | 3658 | static void |
0c20a65f | 3659 | set_initial_label_offsets (void) |
1f3b1e1a JL |
3660 | { |
3661 | rtx x; | |
4cc0fdd2 | 3662 | memset (offsets_known_at, 0, num_labels); |
09dd1133 BS |
3663 | |
3664 | for (x = forced_labels; x; x = XEXP (x, 1)) | |
3665 | if (XEXP (x, 0)) | |
3666 | set_label_offsets (XEXP (x, 0), NULL_RTX, 1); | |
58767f00 RH |
3667 | |
3668 | for_each_eh_label (set_initial_eh_label_offset); | |
09dd1133 BS |
3669 | } |
3670 | ||
1f3b1e1a JL |
3671 | /* Set all elimination offsets to the known values for the code label given |
3672 | by INSN. */ | |
1d813780 | 3673 | |
1f3b1e1a | 3674 | static void |
0c20a65f | 3675 | set_offsets_for_label (rtx insn) |
1f3b1e1a | 3676 | { |
973838fd | 3677 | unsigned int i; |
1f3b1e1a JL |
3678 | int label_nr = CODE_LABEL_NUMBER (insn); |
3679 | struct elim_table *ep; | |
3680 | ||
3681 | num_not_at_initial_offset = 0; | |
3682 | for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++) | |
3683 | { | |
4cc0fdd2 JDA |
3684 | ep->offset = ep->previous_offset |
3685 | = offsets_at[label_nr - first_label_num][i]; | |
1f3b1e1a JL |
3686 | if (ep->can_eliminate && ep->offset != ep->initial_offset) |
3687 | num_not_at_initial_offset++; | |
3688 | } | |
3689 | } | |
3690 | ||
09dd1133 | 3691 | /* See if anything that happened changes which eliminations are valid. |
981f6289 | 3692 | For example, on the SPARC, whether or not the frame pointer can |
09dd1133 BS |
3693 | be eliminated can depend on what registers have been used. We need |
3694 | not check some conditions again (such as flag_omit_frame_pointer) | |
3695 | since they can't have changed. */ | |
3696 | ||
3697 | static void | |
0c20a65f | 3698 | update_eliminables (HARD_REG_SET *pset) |
09dd1133 | 3699 | { |
09dd1133 | 3700 | int previous_frame_pointer_needed = frame_pointer_needed; |
09dd1133 BS |
3701 | struct elim_table *ep; |
3702 | ||
3703 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3704 | if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED) | |
3705 | #ifdef ELIMINABLE_REGS | |
3706 | || ! CAN_ELIMINATE (ep->from, ep->to) | |
3707 | #endif | |
3708 | ) | |
3709 | ep->can_eliminate = 0; | |
3710 | ||
3711 | /* Look for the case where we have discovered that we can't replace | |
3712 | register A with register B and that means that we will now be | |
3713 | trying to replace register A with register C. This means we can | |
3714 | no longer replace register C with register B and we need to disable | |
3715 | such an elimination, if it exists. This occurs often with A == ap, | |
3716 | B == sp, and C == fp. */ | |
3717 | ||
3718 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3719 | { | |
3720 | struct elim_table *op; | |
b3694847 | 3721 | int new_to = -1; |
09dd1133 BS |
3722 | |
3723 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3724 | { | |
3725 | /* Find the current elimination for ep->from, if there is a | |
3726 | new one. */ | |
3727 | for (op = reg_eliminate; | |
3728 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3729 | if (op->from == ep->from && op->can_eliminate) | |
3730 | { | |
3731 | new_to = op->to; | |
3732 | break; | |
3733 | } | |
3734 | ||
3735 | /* See if there is an elimination of NEW_TO -> EP->TO. If so, | |
3736 | disable it. */ | |
3737 | for (op = reg_eliminate; | |
3738 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3739 | if (op->from == new_to && op->to == ep->to) | |
3740 | op->can_eliminate = 0; | |
3741 | } | |
3742 | } | |
3743 | ||
3744 | /* See if any registers that we thought we could eliminate the previous | |
3745 | time are no longer eliminable. If so, something has changed and we | |
3746 | must spill the register. Also, recompute the number of eliminable | |
3747 | registers and see if the frame pointer is needed; it is if there is | |
3748 | no elimination of the frame pointer that we can perform. */ | |
3749 | ||
3750 | frame_pointer_needed = 1; | |
3751 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3752 | { | |
2e3f842f L |
3753 | if (ep->can_eliminate |
3754 | && ep->from == FRAME_POINTER_REGNUM | |
3755 | && ep->to != HARD_FRAME_POINTER_REGNUM | |
3756 | && (! SUPPORTS_STACK_ALIGNMENT | |
3757 | || ! crtl->stack_realign_needed)) | |
09dd1133 BS |
3758 | frame_pointer_needed = 0; |
3759 | ||
3760 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3761 | { | |
3762 | ep->can_eliminate_previous = 0; | |
3763 | SET_HARD_REG_BIT (*pset, ep->from); | |
3764 | num_eliminable--; | |
3765 | } | |
3766 | } | |
3767 | ||
09dd1133 BS |
3768 | /* If we didn't need a frame pointer last time, but we do now, spill |
3769 | the hard frame pointer. */ | |
3770 | if (frame_pointer_needed && ! previous_frame_pointer_needed) | |
3771 | SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM); | |
09dd1133 BS |
3772 | } |
3773 | ||
8c74fb06 RS |
3774 | /* Return true if X is used as the target register of an elimination. */ |
3775 | ||
3776 | bool | |
3777 | elimination_target_reg_p (rtx x) | |
3778 | { | |
3779 | struct elim_table *ep; | |
3780 | ||
3781 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3782 | if (ep->to_rtx == x && ep->can_eliminate) | |
3783 | return true; | |
3784 | ||
3785 | return false; | |
3786 | } | |
3787 | ||
38aa4d08 JY |
3788 | /* Initialize the table of registers to eliminate. |
3789 | Pre-condition: global flag frame_pointer_needed has been set before | |
3790 | calling this function. */ | |
1d813780 | 3791 | |
09dd1133 | 3792 | static void |
0c20a65f | 3793 | init_elim_table (void) |
09dd1133 BS |
3794 | { |
3795 | struct elim_table *ep; | |
590cf94d | 3796 | #ifdef ELIMINABLE_REGS |
0b5826ac | 3797 | const struct elim_table_1 *ep1; |
590cf94d | 3798 | #endif |
09dd1133 | 3799 | |
590cf94d | 3800 | if (!reg_eliminate) |
1634b18f | 3801 | reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS); |
05d10675 | 3802 | |
09dd1133 BS |
3803 | num_eliminable = 0; |
3804 | ||
3805 | #ifdef ELIMINABLE_REGS | |
590cf94d KG |
3806 | for (ep = reg_eliminate, ep1 = reg_eliminate_1; |
3807 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++) | |
09dd1133 | 3808 | { |
590cf94d KG |
3809 | ep->from = ep1->from; |
3810 | ep->to = ep1->to; | |
09dd1133 BS |
3811 | ep->can_eliminate = ep->can_eliminate_previous |
3812 | = (CAN_ELIMINATE (ep->from, ep->to) | |
2e3f842f L |
3813 | && ! (ep->to == STACK_POINTER_REGNUM |
3814 | && frame_pointer_needed | |
3815 | && (! SUPPORTS_STACK_ALIGNMENT | |
3816 | || ! stack_realign_fp))); | |
09dd1133 BS |
3817 | } |
3818 | #else | |
590cf94d KG |
3819 | reg_eliminate[0].from = reg_eliminate_1[0].from; |
3820 | reg_eliminate[0].to = reg_eliminate_1[0].to; | |
09dd1133 BS |
3821 | reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous |
3822 | = ! frame_pointer_needed; | |
3823 | #endif | |
3824 | ||
3825 | /* Count the number of eliminable registers and build the FROM and TO | |
2fb00d7f | 3826 | REG rtx's. Note that code in gen_rtx_REG will cause, e.g., |
f84d109f | 3827 | gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. |
09dd1133 BS |
3828 | We depend on this. */ |
3829 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3830 | { | |
3831 | num_eliminable += ep->can_eliminate; | |
3832 | ep->from_rtx = gen_rtx_REG (Pmode, ep->from); | |
3833 | ep->to_rtx = gen_rtx_REG (Pmode, ep->to); | |
3834 | } | |
3835 | } | |
32131a9c RK |
3836 | \f |
3837 | /* Kick all pseudos out of hard register REGNO. | |
32131a9c RK |
3838 | |
3839 | If CANT_ELIMINATE is nonzero, it means that we are doing this spill | |
3840 | because we found we can't eliminate some register. In the case, no pseudos | |
3841 | are allowed to be in the register, even if they are only in a block that | |
3842 | doesn't require spill registers, unlike the case when we are spilling this | |
3843 | hard reg to produce another spill register. | |
3844 | ||
3845 | Return nonzero if any pseudos needed to be kicked out. */ | |
3846 | ||
03acd8f8 | 3847 | static void |
0c20a65f | 3848 | spill_hard_reg (unsigned int regno, int cant_eliminate) |
32131a9c | 3849 | { |
b3694847 | 3850 | int i; |
32131a9c | 3851 | |
9ff3516a | 3852 | if (cant_eliminate) |
03acd8f8 BS |
3853 | { |
3854 | SET_HARD_REG_BIT (bad_spill_regs_global, regno); | |
6fb5fa3c | 3855 | df_set_regs_ever_live (regno, true); |
03acd8f8 | 3856 | } |
9ff3516a | 3857 | |
32131a9c RK |
3858 | /* Spill every pseudo reg that was allocated to this reg |
3859 | or to something that overlaps this reg. */ | |
3860 | ||
3861 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3862 | if (reg_renumber[i] >= 0 | |
770ae6cc | 3863 | && (unsigned int) reg_renumber[i] <= regno |
09e18274 | 3864 | && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno) |
f5d8c9f4 | 3865 | SET_REGNO_REG_SET (&spilled_pseudos, i); |
03acd8f8 | 3866 | } |
32131a9c | 3867 | |
03acd8f8 BS |
3868 | /* After find_reload_regs has been run for all insn that need reloads, |
3869 | and/or spill_hard_regs was called, this function is used to actually | |
3870 | spill pseudo registers and try to reallocate them. It also sets up the | |
3871 | spill_regs array for use by choose_reload_regs. */ | |
a8fdc208 | 3872 | |
03acd8f8 | 3873 | static int |
0c20a65f | 3874 | finish_spills (int global) |
03acd8f8 BS |
3875 | { |
3876 | struct insn_chain *chain; | |
3877 | int something_changed = 0; | |
3cd8c58a | 3878 | unsigned i; |
a2041967 | 3879 | reg_set_iterator rsi; |
03acd8f8 BS |
3880 | |
3881 | /* Build the spill_regs array for the function. */ | |
3882 | /* If there are some registers still to eliminate and one of the spill regs | |
3883 | wasn't ever used before, additional stack space may have to be | |
3884 | allocated to store this register. Thus, we may have changed the offset | |
3885 | between the stack and frame pointers, so mark that something has changed. | |
32131a9c | 3886 | |
03acd8f8 BS |
3887 | One might think that we need only set VAL to 1 if this is a call-used |
3888 | register. However, the set of registers that must be saved by the | |
3889 | prologue is not identical to the call-used set. For example, the | |
3890 | register used by the call insn for the return PC is a call-used register, | |
3891 | but must be saved by the prologue. */ | |
3892 | ||
3893 | n_spills = 0; | |
3894 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3895 | if (TEST_HARD_REG_BIT (used_spill_regs, i)) | |
3896 | { | |
3897 | spill_reg_order[i] = n_spills; | |
3898 | spill_regs[n_spills++] = i; | |
6fb5fa3c | 3899 | if (num_eliminable && ! df_regs_ever_live_p (i)) |
03acd8f8 | 3900 | something_changed = 1; |
6fb5fa3c | 3901 | df_set_regs_ever_live (i, true); |
03acd8f8 BS |
3902 | } |
3903 | else | |
3904 | spill_reg_order[i] = -1; | |
3905 | ||
a2041967 | 3906 | EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi) |
2af2dbdc | 3907 | if (! ira_conflicts_p || reg_renumber[i] >= 0) |
058e97ec VM |
3908 | { |
3909 | /* Record the current hard register the pseudo is allocated to | |
3910 | in pseudo_previous_regs so we avoid reallocating it to the | |
3911 | same hard reg in a later pass. */ | |
3912 | gcc_assert (reg_renumber[i] >= 0); | |
3913 | ||
3914 | SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]); | |
3915 | /* Mark it as no longer having a hard register home. */ | |
3916 | reg_renumber[i] = -1; | |
2af2dbdc | 3917 | if (ira_conflicts_p) |
058e97ec VM |
3918 | /* Inform IRA about the change. */ |
3919 | ira_mark_allocation_change (i); | |
3920 | /* We will need to scan everything again. */ | |
3921 | something_changed = 1; | |
3922 | } | |
7609e720 | 3923 | |
03acd8f8 | 3924 | /* Retry global register allocation if possible. */ |
2af2dbdc | 3925 | if (global && ira_conflicts_p) |
03acd8f8 | 3926 | { |
2af2dbdc VM |
3927 | unsigned int n; |
3928 | ||
703ad42b | 3929 | memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET)); |
03acd8f8 BS |
3930 | /* For every insn that needs reloads, set the registers used as spill |
3931 | regs in pseudo_forbidden_regs for every pseudo live across the | |
3932 | insn. */ | |
3933 | for (chain = insns_need_reload; chain; chain = chain->next_need_reload) | |
3934 | { | |
3935 | EXECUTE_IF_SET_IN_REG_SET | |
a2041967 KH |
3936 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi) |
3937 | { | |
00268eb3 KH |
3938 | IOR_HARD_REG_SET (pseudo_forbidden_regs[i], |
3939 | chain->used_spill_regs); | |
a2041967 | 3940 | } |
03acd8f8 | 3941 | EXECUTE_IF_SET_IN_REG_SET |
a2041967 KH |
3942 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi) |
3943 | { | |
00268eb3 KH |
3944 | IOR_HARD_REG_SET (pseudo_forbidden_regs[i], |
3945 | chain->used_spill_regs); | |
a2041967 | 3946 | } |
03acd8f8 | 3947 | } |
7609e720 | 3948 | |
2af2dbdc VM |
3949 | /* Retry allocating the pseudos spilled in IRA and the |
3950 | reload. For each reg, merge the various reg sets that | |
3951 | indicate which hard regs can't be used, and call | |
3952 | ira_reassign_pseudos. */ | |
3953 | for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++) | |
3954 | if (reg_old_renumber[i] != reg_renumber[i]) | |
3955 | { | |
3956 | if (reg_renumber[i] < 0) | |
3957 | temp_pseudo_reg_arr[n++] = i; | |
3958 | else | |
3959 | CLEAR_REGNO_REG_SET (&spilled_pseudos, i); | |
3960 | } | |
3961 | if (ira_reassign_pseudos (temp_pseudo_reg_arr, n, | |
3962 | bad_spill_regs_global, | |
3963 | pseudo_forbidden_regs, pseudo_previous_regs, | |
3964 | &spilled_pseudos)) | |
3965 | something_changed = 1; | |
03acd8f8 | 3966 | } |
03acd8f8 BS |
3967 | /* Fix up the register information in the insn chain. |
3968 | This involves deleting those of the spilled pseudos which did not get | |
3969 | a new hard register home from the live_{before,after} sets. */ | |
7609e720 BS |
3970 | for (chain = reload_insn_chain; chain; chain = chain->next) |
3971 | { | |
03acd8f8 BS |
3972 | HARD_REG_SET used_by_pseudos; |
3973 | HARD_REG_SET used_by_pseudos2; | |
3974 | ||
2af2dbdc | 3975 | if (! ira_conflicts_p) |
058e97ec VM |
3976 | { |
3977 | /* Don't do it for IRA because IRA and the reload still can | |
3978 | assign hard registers to the spilled pseudos on next | |
3979 | reload iterations. */ | |
3980 | AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos); | |
3981 | AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos); | |
3982 | } | |
03acd8f8 BS |
3983 | /* Mark any unallocated hard regs as available for spills. That |
3984 | makes inheritance work somewhat better. */ | |
3985 | if (chain->need_reload) | |
3986 | { | |
239a0f5b BS |
3987 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); |
3988 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
03acd8f8 BS |
3989 | IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2); |
3990 | ||
239a0f5b BS |
3991 | compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout); |
3992 | compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set); | |
058e97ec VM |
3993 | /* Value of chain->used_spill_regs from previous iteration |
3994 | may be not included in the value calculated here because | |
3995 | of possible removing caller-saves insns (see function | |
3996 | delete_caller_save_insns. */ | |
03acd8f8 BS |
3997 | COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos); |
3998 | AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs); | |
03acd8f8 | 3999 | } |
7609e720 | 4000 | } |
03acd8f8 | 4001 | |
058e97ec | 4002 | CLEAR_REG_SET (&changed_allocation_pseudos); |
03acd8f8 | 4003 | /* Let alter_reg modify the reg rtx's for the modified pseudos. */ |
3cd8c58a | 4004 | for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++) |
03acd8f8 BS |
4005 | { |
4006 | int regno = reg_renumber[i]; | |
4007 | if (reg_old_renumber[i] == regno) | |
4008 | continue; | |
05d10675 | 4009 | |
058e97ec VM |
4010 | SET_REGNO_REG_SET (&changed_allocation_pseudos, i); |
4011 | ||
4012 | alter_reg (i, reg_old_renumber[i], false); | |
03acd8f8 | 4013 | reg_old_renumber[i] = regno; |
c263766c | 4014 | if (dump_file) |
03acd8f8 BS |
4015 | { |
4016 | if (regno == -1) | |
c263766c | 4017 | fprintf (dump_file, " Register %d now on stack.\n\n", i); |
03acd8f8 | 4018 | else |
c263766c | 4019 | fprintf (dump_file, " Register %d now in %d.\n\n", |
03acd8f8 BS |
4020 | i, reg_renumber[i]); |
4021 | } | |
4022 | } | |
4023 | ||
4024 | return something_changed; | |
7609e720 | 4025 | } |
32131a9c | 4026 | \f |
d754127f | 4027 | /* Find all paradoxical subregs within X and update reg_max_ref_width. */ |
32131a9c RK |
4028 | |
4029 | static void | |
0c20a65f | 4030 | scan_paradoxical_subregs (rtx x) |
32131a9c | 4031 | { |
b3694847 SS |
4032 | int i; |
4033 | const char *fmt; | |
4034 | enum rtx_code code = GET_CODE (x); | |
32131a9c RK |
4035 | |
4036 | switch (code) | |
4037 | { | |
56f58d3a | 4038 | case REG: |
32131a9c RK |
4039 | case CONST_INT: |
4040 | case CONST: | |
4041 | case SYMBOL_REF: | |
4042 | case LABEL_REF: | |
4043 | case CONST_DOUBLE: | |
091a3ac7 | 4044 | case CONST_FIXED: |
69ef87e2 | 4045 | case CONST_VECTOR: /* shouldn't happen, but just in case. */ |
32131a9c RK |
4046 | case CC0: |
4047 | case PC: | |
32131a9c RK |
4048 | case USE: |
4049 | case CLOBBER: | |
4050 | return; | |
4051 | ||
4052 | case SUBREG: | |
f8cfc6aa | 4053 | if (REG_P (SUBREG_REG (x)) |
63a7a62b RS |
4054 | && (GET_MODE_SIZE (GET_MODE (x)) |
4055 | > reg_max_ref_width[REGNO (SUBREG_REG (x))])) | |
6fb5fa3c DB |
4056 | { |
4057 | reg_max_ref_width[REGNO (SUBREG_REG (x))] | |
4058 | = GET_MODE_SIZE (GET_MODE (x)); | |
4059 | mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x)); | |
4060 | } | |
32131a9c | 4061 | return; |
05d10675 | 4062 | |
e9a25f70 JL |
4063 | default: |
4064 | break; | |
32131a9c RK |
4065 | } |
4066 | ||
4067 | fmt = GET_RTX_FORMAT (code); | |
4068 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
4069 | { | |
4070 | if (fmt[i] == 'e') | |
4071 | scan_paradoxical_subregs (XEXP (x, i)); | |
4072 | else if (fmt[i] == 'E') | |
4073 | { | |
b3694847 | 4074 | int j; |
1d7254c5 | 4075 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
32131a9c RK |
4076 | scan_paradoxical_subregs (XVECEXP (x, i, j)); |
4077 | } | |
4078 | } | |
4079 | } | |
4080 | \f | |
be0c514c RH |
4081 | /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note, |
4082 | examine all of the reload insns between PREV and NEXT exclusive, and | |
4083 | annotate all that may trap. */ | |
4084 | ||
4085 | static void | |
4086 | fixup_eh_region_note (rtx insn, rtx prev, rtx next) | |
4087 | { | |
4088 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
be0c514c RH |
4089 | rtx i; |
4090 | ||
4091 | if (note == NULL) | |
4092 | return; | |
4093 | ||
d3aa398e JL |
4094 | if (! may_trap_p (PATTERN (insn))) |
4095 | remove_note (insn, note); | |
be0c514c | 4096 | |
ba4807a0 | 4097 | for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i)) |
be0c514c | 4098 | if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i))) |
d3aa398e | 4099 | add_reg_note (i, REG_EH_REGION, XEXP (note, 0)); |
be0c514c RH |
4100 | } |
4101 | ||
32131a9c RK |
4102 | /* Reload pseudo-registers into hard regs around each insn as needed. |
4103 | Additional register load insns are output before the insn that needs it | |
4104 | and perhaps store insns after insns that modify the reloaded pseudo reg. | |
4105 | ||
4106 | reg_last_reload_reg and reg_reloaded_contents keep track of | |
d08ea79f | 4107 | which registers are already available in reload registers. |
32131a9c RK |
4108 | We update these for the reloads that we perform, |
4109 | as the insns are scanned. */ | |
4110 | ||
4111 | static void | |
0c20a65f | 4112 | reload_as_needed (int live_known) |
32131a9c | 4113 | { |
7609e720 | 4114 | struct insn_chain *chain; |
553687c9 | 4115 | #if defined (AUTO_INC_DEC) |
b3694847 | 4116 | int i; |
973838fd | 4117 | #endif |
32131a9c | 4118 | rtx x; |
32131a9c | 4119 | |
703ad42b KG |
4120 | memset (spill_reg_rtx, 0, sizeof spill_reg_rtx); |
4121 | memset (spill_reg_store, 0, sizeof spill_reg_store); | |
5ed6ace5 | 4122 | reg_last_reload_reg = XCNEWVEC (rtx, max_regno); |
2c61f5f1 | 4123 | INIT_REG_SET (®_has_output_reload); |
e6e52be0 | 4124 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
e3e9336f | 4125 | CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered); |
32131a9c | 4126 | |
1f3b1e1a | 4127 | set_initial_elim_offsets (); |
32131a9c | 4128 | |
7609e720 | 4129 | for (chain = reload_insn_chain; chain; chain = chain->next) |
32131a9c | 4130 | { |
0334ef47 | 4131 | rtx prev = 0; |
7609e720 BS |
4132 | rtx insn = chain->insn; |
4133 | rtx old_next = NEXT_INSN (insn); | |
bf8ba8ab VM |
4134 | #ifdef AUTO_INC_DEC |
4135 | rtx old_prev = PREV_INSN (insn); | |
4136 | #endif | |
32131a9c RK |
4137 | |
4138 | /* If we pass a label, copy the offsets from the label information | |
4139 | into the current offsets of each elimination. */ | |
4b4bf941 | 4140 | if (LABEL_P (insn)) |
1f3b1e1a | 4141 | set_offsets_for_label (insn); |
32131a9c | 4142 | |
2c3c49de | 4143 | else if (INSN_P (insn)) |
32131a9c | 4144 | { |
db4c7386 JH |
4145 | regset_head regs_to_forget; |
4146 | INIT_REG_SET (®s_to_forget); | |
4147 | note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget); | |
7ffaaddc | 4148 | |
2758481d RS |
4149 | /* If this is a USE and CLOBBER of a MEM, ensure that any |
4150 | references to eliminable registers have been removed. */ | |
4151 | ||
4152 | if ((GET_CODE (PATTERN (insn)) == USE | |
4153 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
3c0cb5de | 4154 | && MEM_P (XEXP (PATTERN (insn), 0))) |
2758481d RS |
4155 | XEXP (XEXP (PATTERN (insn), 0), 0) |
4156 | = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), | |
29ae5012 | 4157 | GET_MODE (XEXP (PATTERN (insn), 0)), |
1914f5da | 4158 | NULL_RTX); |
2758481d | 4159 | |
32131a9c RK |
4160 | /* If we need to do register elimination processing, do so. |
4161 | This might delete the insn, in which case we are done. */ | |
2b49ee39 | 4162 | if ((num_eliminable || num_eliminable_invariants) && chain->need_elim) |
32131a9c RK |
4163 | { |
4164 | eliminate_regs_in_insn (insn, 1); | |
4b4bf941 | 4165 | if (NOTE_P (insn)) |
cb2afeb3 R |
4166 | { |
4167 | update_eliminable_offsets (); | |
db4c7386 | 4168 | CLEAR_REG_SET (®s_to_forget); |
cb2afeb3 R |
4169 | continue; |
4170 | } | |
32131a9c RK |
4171 | } |
4172 | ||
7609e720 BS |
4173 | /* If need_elim is nonzero but need_reload is zero, one might think |
4174 | that we could simply set n_reloads to 0. However, find_reloads | |
4175 | could have done some manipulation of the insn (such as swapping | |
4176 | commutative operands), and these manipulations are lost during | |
4177 | the first pass for every insn that needs register elimination. | |
4178 | So the actions of find_reloads must be redone here. */ | |
4179 | ||
03acd8f8 BS |
4180 | if (! chain->need_elim && ! chain->need_reload |
4181 | && ! chain->need_operand_change) | |
32131a9c RK |
4182 | n_reloads = 0; |
4183 | /* First find the pseudo regs that must be reloaded for this insn. | |
4184 | This info is returned in the tables reload_... (see reload.h). | |
4185 | Also modify the body of INSN by substituting RELOAD | |
4186 | rtx's for those pseudo regs. */ | |
4187 | else | |
4188 | { | |
2c61f5f1 | 4189 | CLEAR_REG_SET (®_has_output_reload); |
32131a9c RK |
4190 | CLEAR_HARD_REG_SET (reg_is_output_reload); |
4191 | ||
4192 | find_reloads (insn, 1, spill_indirect_levels, live_known, | |
4193 | spill_reg_order); | |
4194 | } | |
4195 | ||
4196 | if (n_reloads > 0) | |
4197 | { | |
cb2afeb3 | 4198 | rtx next = NEXT_INSN (insn); |
3c3eeea6 | 4199 | rtx p; |
32131a9c | 4200 | |
cb2afeb3 R |
4201 | prev = PREV_INSN (insn); |
4202 | ||
32131a9c RK |
4203 | /* Now compute which reload regs to reload them into. Perhaps |
4204 | reusing reload regs from previous insns, or else output | |
4205 | load insns to reload them. Maybe output store insns too. | |
4206 | Record the choices of reload reg in reload_reg_rtx. */ | |
03acd8f8 | 4207 | choose_reload_regs (chain); |
32131a9c | 4208 | |
05d10675 | 4209 | /* Merge any reloads that we didn't combine for fear of |
546b63fb RK |
4210 | increasing the number of spill registers needed but now |
4211 | discover can be safely merged. */ | |
f95182a4 ILT |
4212 | if (SMALL_REGISTER_CLASSES) |
4213 | merge_assigned_reloads (insn); | |
546b63fb | 4214 | |
32131a9c RK |
4215 | /* Generate the insns to reload operands into or out of |
4216 | their reload regs. */ | |
e04ca094 | 4217 | emit_reload_insns (chain); |
32131a9c RK |
4218 | |
4219 | /* Substitute the chosen reload regs from reload_reg_rtx | |
4220 | into the insn's body (or perhaps into the bodies of other | |
4221 | load and store insn that we just made for reloading | |
4222 | and that we moved the structure into). */ | |
f759eb8b | 4223 | subst_reloads (insn); |
3c3eeea6 | 4224 | |
be0c514c | 4225 | /* Adjust the exception region notes for loads and stores. */ |
e3947b34 | 4226 | if (flag_non_call_exceptions && !CALL_P (insn)) |
be0c514c RH |
4227 | fixup_eh_region_note (insn, prev, next); |
4228 | ||
3c3eeea6 RK |
4229 | /* If this was an ASM, make sure that all the reload insns |
4230 | we have generated are valid. If not, give an error | |
4231 | and delete them. */ | |
3c3eeea6 RK |
4232 | if (asm_noperands (PATTERN (insn)) >= 0) |
4233 | for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) | |
2c3c49de | 4234 | if (p != insn && INSN_P (p) |
00dcfe80 | 4235 | && GET_CODE (PATTERN (p)) != USE |
3c3eeea6 | 4236 | && (recog_memoized (p) < 0 |
0eadeb15 | 4237 | || (extract_insn (p), ! constrain_operands (1)))) |
3c3eeea6 RK |
4238 | { |
4239 | error_for_asm (insn, | |
971801ff JM |
4240 | "%<asm%> operand requires " |
4241 | "impossible reload"); | |
ca6c03ca | 4242 | delete_insn (p); |
3c3eeea6 | 4243 | } |
32131a9c | 4244 | } |
5d7ef82a BS |
4245 | |
4246 | if (num_eliminable && chain->need_elim) | |
4247 | update_eliminable_offsets (); | |
4248 | ||
32131a9c RK |
4249 | /* Any previously reloaded spilled pseudo reg, stored in this insn, |
4250 | is no longer validly lying around to save a future reload. | |
4251 | Note that this does not detect pseudos that were reloaded | |
4252 | for this insn in order to be stored in | |
4253 | (obeying register constraints). That is correct; such reload | |
4254 | registers ARE still valid. */ | |
db4c7386 JH |
4255 | forget_marked_reloads (®s_to_forget); |
4256 | CLEAR_REG_SET (®s_to_forget); | |
32131a9c RK |
4257 | |
4258 | /* There may have been CLOBBER insns placed after INSN. So scan | |
4259 | between INSN and NEXT and use them to forget old reloads. */ | |
7609e720 | 4260 | for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x)) |
4b4bf941 | 4261 | if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER) |
84832317 | 4262 | note_stores (PATTERN (x), forget_old_reloads_1, NULL); |
32131a9c RK |
4263 | |
4264 | #ifdef AUTO_INC_DEC | |
cb2afeb3 R |
4265 | /* Likewise for regs altered by auto-increment in this insn. |
4266 | REG_INC notes have been changed by reloading: | |
4267 | find_reloads_address_1 records substitutions for them, | |
4268 | which have been performed by subst_reloads above. */ | |
4269 | for (i = n_reloads - 1; i >= 0; i--) | |
4270 | { | |
eceef4c9 | 4271 | rtx in_reg = rld[i].in_reg; |
cb2afeb3 R |
4272 | if (in_reg) |
4273 | { | |
4274 | enum rtx_code code = GET_CODE (in_reg); | |
4275 | /* PRE_INC / PRE_DEC will have the reload register ending up | |
4276 | with the same value as the stack slot, but that doesn't | |
4277 | hold true for POST_INC / POST_DEC. Either we have to | |
4278 | convert the memory access to a true POST_INC / POST_DEC, | |
4279 | or we can't use the reload register for inheritance. */ | |
4280 | if ((code == POST_INC || code == POST_DEC) | |
4281 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 4282 | REGNO (rld[i].reg_rtx)) |
04bbb0c5 JW |
4283 | /* Make sure it is the inc/dec pseudo, and not |
4284 | some other (e.g. output operand) pseudo. */ | |
fc555370 | 4285 | && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
04bbb0c5 | 4286 | == REGNO (XEXP (in_reg, 0)))) |
05d10675 | 4287 | |
cb2afeb3 | 4288 | { |
eceef4c9 | 4289 | rtx reload_reg = rld[i].reg_rtx; |
cb2afeb3 R |
4290 | enum machine_mode mode = GET_MODE (reload_reg); |
4291 | int n = 0; | |
4292 | rtx p; | |
4293 | ||
4294 | for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p)) | |
4295 | { | |
4296 | /* We really want to ignore REG_INC notes here, so | |
4297 | use PATTERN (p) as argument to reg_set_p . */ | |
4298 | if (reg_set_p (reload_reg, PATTERN (p))) | |
4299 | break; | |
4b983fdc | 4300 | n = count_occurrences (PATTERN (p), reload_reg, 0); |
cb2afeb3 R |
4301 | if (! n) |
4302 | continue; | |
4303 | if (n == 1) | |
f67c2384 JL |
4304 | { |
4305 | n = validate_replace_rtx (reload_reg, | |
2fb00d7f KH |
4306 | gen_rtx_fmt_e (code, |
4307 | mode, | |
4308 | reload_reg), | |
f67c2384 JL |
4309 | p); |
4310 | ||
4311 | /* We must also verify that the constraints | |
4312 | are met after the replacement. */ | |
4313 | extract_insn (p); | |
4314 | if (n) | |
4315 | n = constrain_operands (1); | |
4316 | else | |
4317 | break; | |
4318 | ||
4319 | /* If the constraints were not met, then | |
4320 | undo the replacement. */ | |
4321 | if (!n) | |
4322 | { | |
2fb00d7f KH |
4323 | validate_replace_rtx (gen_rtx_fmt_e (code, |
4324 | mode, | |
4325 | reload_reg), | |
f67c2384 JL |
4326 | reload_reg, p); |
4327 | break; | |
4328 | } | |
05d10675 | 4329 | |
f67c2384 | 4330 | } |
cb2afeb3 R |
4331 | break; |
4332 | } | |
4333 | if (n == 1) | |
02eb1393 | 4334 | { |
65c5f2a6 | 4335 | add_reg_note (p, REG_INC, reload_reg); |
02eb1393 R |
4336 | /* Mark this as having an output reload so that the |
4337 | REG_INC processing code below won't invalidate | |
4338 | the reload for inheritance. */ | |
4339 | SET_HARD_REG_BIT (reg_is_output_reload, | |
4340 | REGNO (reload_reg)); | |
2c61f5f1 JH |
4341 | SET_REGNO_REG_SET (®_has_output_reload, |
4342 | REGNO (XEXP (in_reg, 0))); | |
02eb1393 | 4343 | } |
cb2afeb3 | 4344 | else |
1d7254c5 | 4345 | forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX, |
84832317 | 4346 | NULL); |
cb2afeb3 | 4347 | } |
02eb1393 R |
4348 | else if ((code == PRE_INC || code == PRE_DEC) |
4349 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 4350 | REGNO (rld[i].reg_rtx)) |
02eb1393 R |
4351 | /* Make sure it is the inc/dec pseudo, and not |
4352 | some other (e.g. output operand) pseudo. */ | |
fc555370 | 4353 | && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
02eb1393 R |
4354 | == REGNO (XEXP (in_reg, 0)))) |
4355 | { | |
4356 | SET_HARD_REG_BIT (reg_is_output_reload, | |
eceef4c9 | 4357 | REGNO (rld[i].reg_rtx)); |
2c61f5f1 JH |
4358 | SET_REGNO_REG_SET (®_has_output_reload, |
4359 | REGNO (XEXP (in_reg, 0))); | |
02eb1393 | 4360 | } |
d5f89b53 VM |
4361 | else if (code == PRE_INC || code == PRE_DEC |
4362 | || code == POST_INC || code == POST_DEC) | |
bf8ba8ab | 4363 | { |
bf8ba8ab VM |
4364 | int in_regno = REGNO (XEXP (in_reg, 0)); |
4365 | ||
4366 | if (reg_last_reload_reg[in_regno] != NULL_RTX) | |
4367 | { | |
d5f89b53 VM |
4368 | int in_hard_regno; |
4369 | bool forget_p = true; | |
4370 | ||
bf8ba8ab | 4371 | in_hard_regno = REGNO (reg_last_reload_reg[in_regno]); |
d5f89b53 VM |
4372 | if (TEST_HARD_REG_BIT (reg_reloaded_valid, |
4373 | in_hard_regno)) | |
4374 | { | |
4375 | for (x = old_prev ? NEXT_INSN (old_prev) : insn; | |
4376 | x != old_next; | |
4377 | x = NEXT_INSN (x)) | |
4378 | if (x == reg_reloaded_insn[in_hard_regno]) | |
4379 | { | |
4380 | forget_p = false; | |
4381 | break; | |
4382 | } | |
4383 | } | |
bf8ba8ab VM |
4384 | /* If for some reasons, we didn't set up |
4385 | reg_last_reload_reg in this insn, | |
4386 | invalidate inheritance from previous | |
4387 | insns for the incremented/decremented | |
4388 | register. Such registers will be not in | |
d5f89b53 VM |
4389 | reg_has_output_reload. Invalidate it |
4390 | also if the corresponding element in | |
4391 | reg_reloaded_insn is also | |
4392 | invalidated. */ | |
4393 | if (forget_p) | |
bf8ba8ab VM |
4394 | forget_old_reloads_1 (XEXP (in_reg, 0), |
4395 | NULL_RTX, NULL); | |
4396 | } | |
4397 | } | |
cb2afeb3 R |
4398 | } |
4399 | } | |
02eb1393 R |
4400 | /* If a pseudo that got a hard register is auto-incremented, |
4401 | we must purge records of copying it into pseudos without | |
4402 | hard registers. */ | |
32131a9c RK |
4403 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) |
4404 | if (REG_NOTE_KIND (x) == REG_INC) | |
4405 | { | |
4406 | /* See if this pseudo reg was reloaded in this insn. | |
4407 | If so, its last-reload info is still valid | |
4408 | because it is based on this insn's reload. */ | |
4409 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 4410 | if (rld[i].out == XEXP (x, 0)) |
32131a9c RK |
4411 | break; |
4412 | ||
08fb99fa | 4413 | if (i == n_reloads) |
84832317 | 4414 | forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL); |
32131a9c RK |
4415 | } |
4416 | #endif | |
4417 | } | |
4418 | /* A reload reg's contents are unknown after a label. */ | |
4b4bf941 | 4419 | if (LABEL_P (insn)) |
e6e52be0 | 4420 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
32131a9c RK |
4421 | |
4422 | /* Don't assume a reload reg is still good after a call insn | |
e3e9336f DJ |
4423 | if it is a call-used reg, or if it contains a value that will |
4424 | be partially clobbered by the call. */ | |
4b4bf941 | 4425 | else if (CALL_P (insn)) |
e3e9336f | 4426 | { |
058e97ec VM |
4427 | AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set); |
4428 | AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered); | |
e3e9336f | 4429 | } |
32131a9c | 4430 | } |
ff154f78 MM |
4431 | |
4432 | /* Clean up. */ | |
4433 | free (reg_last_reload_reg); | |
2c61f5f1 | 4434 | CLEAR_REG_SET (®_has_output_reload); |
32131a9c RK |
4435 | } |
4436 | ||
4437 | /* Discard all record of any value reloaded from X, | |
4438 | or reloaded in X from someplace else; | |
4439 | unless X is an output reload reg of the current insn. | |
4440 | ||
4441 | X may be a hard reg (the reload reg) | |
db4c7386 JH |
4442 | or it may be a pseudo reg that was reloaded from. |
4443 | ||
4444 | When DATA is non-NULL just mark the registers in regset | |
4445 | to be forgotten later. */ | |
32131a9c RK |
4446 | |
4447 | static void | |
7bc980e1 | 4448 | forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED, |
db4c7386 | 4449 | void *data) |
32131a9c | 4450 | { |
770ae6cc RK |
4451 | unsigned int regno; |
4452 | unsigned int nr; | |
db4c7386 | 4453 | regset regs = (regset) data; |
0a2e51a9 | 4454 | |
ddef6bc7 | 4455 | /* note_stores does give us subregs of hard regs, |
0e61db61 | 4456 | subreg_regno_offset requires a hard reg. */ |
0a2e51a9 RS |
4457 | while (GET_CODE (x) == SUBREG) |
4458 | { | |
fefac463 AH |
4459 | /* We ignore the subreg offset when calculating the regno, |
4460 | because we are using the entire underlying hard register | |
4461 | below. */ | |
0a2e51a9 RS |
4462 | x = SUBREG_REG (x); |
4463 | } | |
32131a9c | 4464 | |
f8cfc6aa | 4465 | if (!REG_P (x)) |
32131a9c RK |
4466 | return; |
4467 | ||
fefac463 | 4468 | regno = REGNO (x); |
32131a9c RK |
4469 | |
4470 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4471 | nr = 1; | |
4472 | else | |
4473 | { | |
770ae6cc RK |
4474 | unsigned int i; |
4475 | ||
66fd46b6 | 4476 | nr = hard_regno_nregs[regno][GET_MODE (x)]; |
32131a9c RK |
4477 | /* Storing into a spilled-reg invalidates its contents. |
4478 | This can happen if a block-local pseudo is allocated to that reg | |
4479 | and it wasn't spilled because this block's total need is 0. | |
4480 | Then some insn might have an optional reload and use this reg. */ | |
db4c7386 JH |
4481 | if (!regs) |
4482 | for (i = 0; i < nr; i++) | |
4483 | /* But don't do this if the reg actually serves as an output | |
4484 | reload reg in the current instruction. */ | |
4485 | if (n_reloads == 0 | |
4486 | || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)) | |
4487 | { | |
4488 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i); | |
db4c7386 JH |
4489 | spill_reg_store[regno + i] = 0; |
4490 | } | |
32131a9c RK |
4491 | } |
4492 | ||
db4c7386 JH |
4493 | if (regs) |
4494 | while (nr-- > 0) | |
4495 | SET_REGNO_REG_SET (regs, regno + nr); | |
4496 | else | |
4497 | { | |
4498 | /* Since value of X has changed, | |
4499 | forget any value previously copied from it. */ | |
4500 | ||
4501 | while (nr-- > 0) | |
4502 | /* But don't forget a copy if this is the output reload | |
4503 | that establishes the copy's validity. */ | |
2c61f5f1 JH |
4504 | if (n_reloads == 0 |
4505 | || !REGNO_REG_SET_P (®_has_output_reload, regno + nr)) | |
db4c7386 JH |
4506 | reg_last_reload_reg[regno + nr] = 0; |
4507 | } | |
4508 | } | |
32131a9c | 4509 | |
db4c7386 JH |
4510 | /* Forget the reloads marked in regset by previous function. */ |
4511 | static void | |
4512 | forget_marked_reloads (regset regs) | |
4513 | { | |
4514 | unsigned int reg; | |
4515 | reg_set_iterator rsi; | |
4516 | EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi) | |
4517 | { | |
4518 | if (reg < FIRST_PSEUDO_REGISTER | |
4519 | /* But don't do this if the reg actually serves as an output | |
4520 | reload reg in the current instruction. */ | |
4521 | && (n_reloads == 0 | |
4522 | || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg))) | |
4523 | { | |
4524 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg); | |
db4c7386 JH |
4525 | spill_reg_store[reg] = 0; |
4526 | } | |
2c61f5f1 JH |
4527 | if (n_reloads == 0 |
4528 | || !REGNO_REG_SET_P (®_has_output_reload, reg)) | |
db4c7386 JH |
4529 | reg_last_reload_reg[reg] = 0; |
4530 | } | |
32131a9c RK |
4531 | } |
4532 | \f | |
32131a9c RK |
4533 | /* The following HARD_REG_SETs indicate when each hard register is |
4534 | used for a reload of various parts of the current insn. */ | |
4535 | ||
9e3a9cf2 BS |
4536 | /* If reg is unavailable for all reloads. */ |
4537 | static HARD_REG_SET reload_reg_unavailable; | |
32131a9c RK |
4538 | /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ |
4539 | static HARD_REG_SET reload_reg_used; | |
546b63fb RK |
4540 | /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ |
4541 | static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4542 | /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */ |
4543 | static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4544 | /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ |
4545 | static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4546 | /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */ |
4547 | static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4548 | /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ |
4549 | static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; | |
4550 | /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ | |
4551 | static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; | |
32131a9c RK |
4552 | /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ |
4553 | static HARD_REG_SET reload_reg_used_in_op_addr; | |
893bc853 RK |
4554 | /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */ |
4555 | static HARD_REG_SET reload_reg_used_in_op_addr_reload; | |
546b63fb RK |
4556 | /* If reg is in use for a RELOAD_FOR_INSN reload. */ |
4557 | static HARD_REG_SET reload_reg_used_in_insn; | |
4558 | /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ | |
4559 | static HARD_REG_SET reload_reg_used_in_other_addr; | |
32131a9c RK |
4560 | |
4561 | /* If reg is in use as a reload reg for any sort of reload. */ | |
4562 | static HARD_REG_SET reload_reg_used_at_all; | |
4563 | ||
be7ae2a4 RK |
4564 | /* If reg is use as an inherited reload. We just mark the first register |
4565 | in the group. */ | |
4566 | static HARD_REG_SET reload_reg_used_for_inherit; | |
4567 | ||
f1db3576 JL |
4568 | /* Records which hard regs are used in any way, either as explicit use or |
4569 | by being allocated to a pseudo during any point of the current insn. */ | |
4570 | static HARD_REG_SET reg_used_in_insn; | |
297927a8 | 4571 | |
546b63fb RK |
4572 | /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and |
4573 | TYPE. MODE is used to indicate how many consecutive regs are | |
4574 | actually used. */ | |
32131a9c RK |
4575 | |
4576 | static void | |
0c20a65f AJ |
4577 | mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type, |
4578 | enum machine_mode mode) | |
32131a9c | 4579 | { |
66fd46b6 | 4580 | unsigned int nregs = hard_regno_nregs[regno][mode]; |
770ae6cc | 4581 | unsigned int i; |
32131a9c RK |
4582 | |
4583 | for (i = regno; i < nregs + regno; i++) | |
4584 | { | |
546b63fb | 4585 | switch (type) |
32131a9c RK |
4586 | { |
4587 | case RELOAD_OTHER: | |
4588 | SET_HARD_REG_BIT (reload_reg_used, i); | |
4589 | break; | |
4590 | ||
546b63fb RK |
4591 | case RELOAD_FOR_INPUT_ADDRESS: |
4592 | SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); | |
32131a9c RK |
4593 | break; |
4594 | ||
47c8cf91 ILT |
4595 | case RELOAD_FOR_INPADDR_ADDRESS: |
4596 | SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i); | |
4597 | break; | |
4598 | ||
546b63fb RK |
4599 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4600 | SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); | |
32131a9c RK |
4601 | break; |
4602 | ||
47c8cf91 ILT |
4603 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4604 | SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i); | |
4605 | break; | |
4606 | ||
32131a9c RK |
4607 | case RELOAD_FOR_OPERAND_ADDRESS: |
4608 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); | |
4609 | break; | |
4610 | ||
893bc853 RK |
4611 | case RELOAD_FOR_OPADDR_ADDR: |
4612 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i); | |
4613 | break; | |
4614 | ||
546b63fb RK |
4615 | case RELOAD_FOR_OTHER_ADDRESS: |
4616 | SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i); | |
4617 | break; | |
4618 | ||
32131a9c | 4619 | case RELOAD_FOR_INPUT: |
546b63fb | 4620 | SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); |
32131a9c RK |
4621 | break; |
4622 | ||
4623 | case RELOAD_FOR_OUTPUT: | |
546b63fb RK |
4624 | SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); |
4625 | break; | |
4626 | ||
4627 | case RELOAD_FOR_INSN: | |
4628 | SET_HARD_REG_BIT (reload_reg_used_in_insn, i); | |
32131a9c RK |
4629 | break; |
4630 | } | |
4631 | ||
4632 | SET_HARD_REG_BIT (reload_reg_used_at_all, i); | |
4633 | } | |
4634 | } | |
4635 | ||
be7ae2a4 RK |
4636 | /* Similarly, but show REGNO is no longer in use for a reload. */ |
4637 | ||
4638 | static void | |
0c20a65f AJ |
4639 | clear_reload_reg_in_use (unsigned int regno, int opnum, |
4640 | enum reload_type type, enum machine_mode mode) | |
be7ae2a4 | 4641 | { |
66fd46b6 | 4642 | unsigned int nregs = hard_regno_nregs[regno][mode]; |
770ae6cc | 4643 | unsigned int start_regno, end_regno, r; |
be7ae2a4 | 4644 | int i; |
cb2afeb3 R |
4645 | /* A complication is that for some reload types, inheritance might |
4646 | allow multiple reloads of the same types to share a reload register. | |
4647 | We set check_opnum if we have to check only reloads with the same | |
4648 | operand number, and check_any if we have to check all reloads. */ | |
4649 | int check_opnum = 0; | |
4650 | int check_any = 0; | |
4651 | HARD_REG_SET *used_in_set; | |
be7ae2a4 | 4652 | |
cb2afeb3 | 4653 | switch (type) |
be7ae2a4 | 4654 | { |
cb2afeb3 R |
4655 | case RELOAD_OTHER: |
4656 | used_in_set = &reload_reg_used; | |
4657 | break; | |
be7ae2a4 | 4658 | |
cb2afeb3 R |
4659 | case RELOAD_FOR_INPUT_ADDRESS: |
4660 | used_in_set = &reload_reg_used_in_input_addr[opnum]; | |
4661 | break; | |
be7ae2a4 | 4662 | |
cb2afeb3 R |
4663 | case RELOAD_FOR_INPADDR_ADDRESS: |
4664 | check_opnum = 1; | |
4665 | used_in_set = &reload_reg_used_in_inpaddr_addr[opnum]; | |
4666 | break; | |
47c8cf91 | 4667 | |
cb2afeb3 R |
4668 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4669 | used_in_set = &reload_reg_used_in_output_addr[opnum]; | |
4670 | break; | |
be7ae2a4 | 4671 | |
cb2afeb3 R |
4672 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4673 | check_opnum = 1; | |
4674 | used_in_set = &reload_reg_used_in_outaddr_addr[opnum]; | |
4675 | break; | |
47c8cf91 | 4676 | |
cb2afeb3 R |
4677 | case RELOAD_FOR_OPERAND_ADDRESS: |
4678 | used_in_set = &reload_reg_used_in_op_addr; | |
4679 | break; | |
be7ae2a4 | 4680 | |
cb2afeb3 R |
4681 | case RELOAD_FOR_OPADDR_ADDR: |
4682 | check_any = 1; | |
4683 | used_in_set = &reload_reg_used_in_op_addr_reload; | |
4684 | break; | |
893bc853 | 4685 | |
cb2afeb3 R |
4686 | case RELOAD_FOR_OTHER_ADDRESS: |
4687 | used_in_set = &reload_reg_used_in_other_addr; | |
4688 | check_any = 1; | |
4689 | break; | |
be7ae2a4 | 4690 | |
cb2afeb3 R |
4691 | case RELOAD_FOR_INPUT: |
4692 | used_in_set = &reload_reg_used_in_input[opnum]; | |
4693 | break; | |
be7ae2a4 | 4694 | |
cb2afeb3 R |
4695 | case RELOAD_FOR_OUTPUT: |
4696 | used_in_set = &reload_reg_used_in_output[opnum]; | |
4697 | break; | |
be7ae2a4 | 4698 | |
cb2afeb3 R |
4699 | case RELOAD_FOR_INSN: |
4700 | used_in_set = &reload_reg_used_in_insn; | |
4701 | break; | |
4702 | default: | |
41374e13 | 4703 | gcc_unreachable (); |
cb2afeb3 R |
4704 | } |
4705 | /* We resolve conflicts with remaining reloads of the same type by | |
68e82b83 | 4706 | excluding the intervals of reload registers by them from the |
cb2afeb3 R |
4707 | interval of freed reload registers. Since we only keep track of |
4708 | one set of interval bounds, we might have to exclude somewhat | |
3e92902c | 4709 | more than what would be necessary if we used a HARD_REG_SET here. |
cb2afeb3 R |
4710 | But this should only happen very infrequently, so there should |
4711 | be no reason to worry about it. */ | |
05d10675 | 4712 | |
cb2afeb3 R |
4713 | start_regno = regno; |
4714 | end_regno = regno + nregs; | |
4715 | if (check_opnum || check_any) | |
4716 | { | |
4717 | for (i = n_reloads - 1; i >= 0; i--) | |
4718 | { | |
eceef4c9 BS |
4719 | if (rld[i].when_needed == type |
4720 | && (check_any || rld[i].opnum == opnum) | |
4721 | && rld[i].reg_rtx) | |
cb2afeb3 | 4722 | { |
770ae6cc RK |
4723 | unsigned int conflict_start = true_regnum (rld[i].reg_rtx); |
4724 | unsigned int conflict_end | |
09e18274 | 4725 | = end_hard_regno (rld[i].mode, conflict_start); |
cb2afeb3 R |
4726 | |
4727 | /* If there is an overlap with the first to-be-freed register, | |
4728 | adjust the interval start. */ | |
4729 | if (conflict_start <= start_regno && conflict_end > start_regno) | |
4730 | start_regno = conflict_end; | |
4731 | /* Otherwise, if there is a conflict with one of the other | |
4732 | to-be-freed registers, adjust the interval end. */ | |
4733 | if (conflict_start > start_regno && conflict_start < end_regno) | |
4734 | end_regno = conflict_start; | |
4735 | } | |
be7ae2a4 RK |
4736 | } |
4737 | } | |
770ae6cc RK |
4738 | |
4739 | for (r = start_regno; r < end_regno; r++) | |
4740 | CLEAR_HARD_REG_BIT (*used_in_set, r); | |
be7ae2a4 RK |
4741 | } |
4742 | ||
32131a9c | 4743 | /* 1 if reg REGNO is free as a reload reg for a reload of the sort |
546b63fb | 4744 | specified by OPNUM and TYPE. */ |
32131a9c RK |
4745 | |
4746 | static int | |
0c20a65f | 4747 | reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type) |
32131a9c | 4748 | { |
546b63fb RK |
4749 | int i; |
4750 | ||
2edc8d65 | 4751 | /* In use for a RELOAD_OTHER means it's not available for anything. */ |
9e3a9cf2 BS |
4752 | if (TEST_HARD_REG_BIT (reload_reg_used, regno) |
4753 | || TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) | |
32131a9c | 4754 | return 0; |
546b63fb RK |
4755 | |
4756 | switch (type) | |
32131a9c RK |
4757 | { |
4758 | case RELOAD_OTHER: | |
2edc8d65 RK |
4759 | /* In use for anything means we can't use it for RELOAD_OTHER. */ |
4760 | if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) | |
224f1d71 | 4761 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
808ededc | 4762 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno) |
224f1d71 RK |
4763 | || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) |
4764 | return 0; | |
4765 | ||
4766 | for (i = 0; i < reload_n_operands; i++) | |
4767 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4768 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
224f1d71 | 4769 | || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
47c8cf91 | 4770 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
224f1d71 RK |
4771 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) |
4772 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4773 | return 0; | |
4774 | ||
4775 | return 1; | |
32131a9c | 4776 | |
32131a9c | 4777 | case RELOAD_FOR_INPUT: |
546b63fb RK |
4778 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) |
4779 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) | |
4780 | return 0; | |
4781 | ||
893bc853 RK |
4782 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4783 | return 0; | |
4784 | ||
546b63fb RK |
4785 | /* If it is used for some other input, can't use it. */ |
4786 | for (i = 0; i < reload_n_operands; i++) | |
4787 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4788 | return 0; | |
4789 | ||
4790 | /* If it is used in a later operand's address, can't use it. */ | |
4791 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4792 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4793 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4794 | return 0; |
4795 | ||
4796 | return 1; | |
4797 | ||
4798 | case RELOAD_FOR_INPUT_ADDRESS: | |
4799 | /* Can't use a register if it is used for an input address for this | |
4800 | operand or used as an input in an earlier one. */ | |
47c8cf91 ILT |
4801 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno) |
4802 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) | |
4803 | return 0; | |
4804 | ||
4805 | for (i = 0; i < opnum; i++) | |
4806 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4807 | return 0; | |
4808 | ||
4809 | return 1; | |
4810 | ||
4811 | case RELOAD_FOR_INPADDR_ADDRESS: | |
4812 | /* Can't use a register if it is used for an input address | |
05d10675 BS |
4813 | for this operand or used as an input in an earlier |
4814 | one. */ | |
47c8cf91 | 4815 | if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) |
546b63fb RK |
4816 | return 0; |
4817 | ||
4818 | for (i = 0; i < opnum; i++) | |
4819 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4820 | return 0; | |
4821 | ||
4822 | return 1; | |
4823 | ||
4824 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
4825 | /* Can't use a register if it is used for an output address for this | |
d1d18b46 DJ |
4826 | operand or used as an output in this or a later operand. Note |
4827 | that multiple output operands are emitted in reverse order, so | |
4828 | the conflicting ones are those with lower indices. */ | |
546b63fb RK |
4829 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) |
4830 | return 0; | |
4831 | ||
d1d18b46 | 4832 | for (i = 0; i <= opnum; i++) |
546b63fb RK |
4833 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4834 | return 0; | |
4835 | ||
4836 | return 1; | |
4837 | ||
47c8cf91 ILT |
4838 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4839 | /* Can't use a register if it is used for an output address | |
05d10675 | 4840 | for this operand or used as an output in this or a |
d1d18b46 DJ |
4841 | later operand. Note that multiple output operands are |
4842 | emitted in reverse order, so the conflicting ones are | |
4843 | those with lower indices. */ | |
47c8cf91 ILT |
4844 | if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) |
4845 | return 0; | |
4846 | ||
d1d18b46 | 4847 | for (i = 0; i <= opnum; i++) |
47c8cf91 ILT |
4848 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4849 | return 0; | |
4850 | ||
4851 | return 1; | |
4852 | ||
32131a9c | 4853 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4854 | for (i = 0; i < reload_n_operands; i++) |
4855 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4856 | return 0; | |
4857 | ||
4858 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4859 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4860 | ||
893bc853 RK |
4861 | case RELOAD_FOR_OPADDR_ADDR: |
4862 | for (i = 0; i < reload_n_operands; i++) | |
05d10675 BS |
4863 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4864 | return 0; | |
893bc853 | 4865 | |
a94ce333 | 4866 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)); |
893bc853 | 4867 | |
32131a9c | 4868 | case RELOAD_FOR_OUTPUT: |
546b63fb | 4869 | /* This cannot share a register with RELOAD_FOR_INSN reloads, other |
d1d18b46 DJ |
4870 | outputs, or an operand address for this or an earlier output. |
4871 | Note that multiple output operands are emitted in reverse order, | |
4872 | so the conflicting ones are those with higher indices. */ | |
546b63fb RK |
4873 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) |
4874 | return 0; | |
4875 | ||
4876 | for (i = 0; i < reload_n_operands; i++) | |
4877 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4878 | return 0; | |
4879 | ||
d1d18b46 | 4880 | for (i = opnum; i < reload_n_operands; i++) |
47c8cf91 ILT |
4881 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4882 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4883 | return 0; |
4884 | ||
4885 | return 1; | |
4886 | ||
4887 | case RELOAD_FOR_INSN: | |
4888 | for (i = 0; i < reload_n_operands; i++) | |
4889 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) | |
4890 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4891 | return 0; | |
4892 | ||
4893 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4894 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4895 | ||
4896 | case RELOAD_FOR_OTHER_ADDRESS: | |
4897 | return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); | |
41374e13 NS |
4898 | |
4899 | default: | |
4900 | gcc_unreachable (); | |
32131a9c | 4901 | } |
32131a9c RK |
4902 | } |
4903 | ||
32131a9c | 4904 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
546b63fb | 4905 | needed for the part of the insn specified by OPNUM and TYPE, |
32131a9c RK |
4906 | is still available in REGNO at the end of the insn. |
4907 | ||
4908 | We can assume that the reload reg was already tested for availability | |
4909 | at the time it is needed, and we should not check this again, | |
4910 | in case the reg has already been marked in use. */ | |
4911 | ||
4912 | static int | |
0c20a65f | 4913 | reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type) |
32131a9c | 4914 | { |
546b63fb RK |
4915 | int i; |
4916 | ||
4917 | switch (type) | |
32131a9c RK |
4918 | { |
4919 | case RELOAD_OTHER: | |
4920 | /* Since a RELOAD_OTHER reload claims the reg for the entire insn, | |
4921 | its value must reach the end. */ | |
4922 | return 1; | |
4923 | ||
4924 | /* If this use is for part of the insn, | |
05d10675 | 4925 | its value reaches if no subsequent part uses the same register. |
546b63fb RK |
4926 | Just like the above function, don't try to do this with lots |
4927 | of fallthroughs. */ | |
4928 | ||
4929 | case RELOAD_FOR_OTHER_ADDRESS: | |
4930 | /* Here we check for everything else, since these don't conflict | |
4931 | with anything else and everything comes later. */ | |
4932 | ||
4933 | for (i = 0; i < reload_n_operands; i++) | |
4934 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4935 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4936 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) |
4937 | || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4938 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4939 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4940 | return 0; | |
4941 | ||
4942 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) | |
808ededc | 4943 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno) |
546b63fb RK |
4944 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) |
4945 | && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
4946 | ||
4947 | case RELOAD_FOR_INPUT_ADDRESS: | |
47c8cf91 | 4948 | case RELOAD_FOR_INPADDR_ADDRESS: |
546b63fb RK |
4949 | /* Similar, except that we check only for this and subsequent inputs |
4950 | and the address of only subsequent inputs and we do not need | |
4951 | to check for RELOAD_OTHER objects since they are known not to | |
4952 | conflict. */ | |
4953 | ||
4954 | for (i = opnum; i < reload_n_operands; i++) | |
4955 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4956 | return 0; | |
4957 | ||
4958 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4959 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4960 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4961 | return 0; |
4962 | ||
4963 | for (i = 0; i < reload_n_operands; i++) | |
4964 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4965 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4966 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4967 | return 0; | |
4968 | ||
893bc853 RK |
4969 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4970 | return 0; | |
4971 | ||
2af88768 GK |
4972 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4973 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4974 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
546b63fb | 4975 | |
32131a9c | 4976 | case RELOAD_FOR_INPUT: |
546b63fb | 4977 | /* Similar to input address, except we start at the next operand for |
05d10675 | 4978 | both input and input address and we do not check for |
546b63fb RK |
4979 | RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these |
4980 | would conflict. */ | |
4981 | ||
4982 | for (i = opnum + 1; i < reload_n_operands; i++) | |
4983 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4984 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4985 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4986 | return 0; | |
4987 | ||
0f41302f | 4988 | /* ... fall through ... */ |
546b63fb | 4989 | |
32131a9c | 4990 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4991 | /* Check outputs and their addresses. */ |
4992 | ||
4993 | for (i = 0; i < reload_n_operands; i++) | |
4994 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4995 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4996 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4997 | return 0; | |
4998 | ||
2af88768 | 4999 | return (!TEST_HARD_REG_BIT (reload_reg_used, regno)); |
546b63fb | 5000 | |
893bc853 RK |
5001 | case RELOAD_FOR_OPADDR_ADDR: |
5002 | for (i = 0; i < reload_n_operands; i++) | |
5003 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 5004 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
893bc853 RK |
5005 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
5006 | return 0; | |
5007 | ||
2af88768 GK |
5008 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
5009 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
5010 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
893bc853 | 5011 | |
546b63fb | 5012 | case RELOAD_FOR_INSN: |
893bc853 | 5013 | /* These conflict with other outputs with RELOAD_OTHER. So |
546b63fb RK |
5014 | we need only check for output addresses. */ |
5015 | ||
d1d18b46 | 5016 | opnum = reload_n_operands; |
546b63fb | 5017 | |
0f41302f | 5018 | /* ... fall through ... */ |
546b63fb | 5019 | |
32131a9c | 5020 | case RELOAD_FOR_OUTPUT: |
546b63fb | 5021 | case RELOAD_FOR_OUTPUT_ADDRESS: |
47c8cf91 | 5022 | case RELOAD_FOR_OUTADDR_ADDRESS: |
546b63fb | 5023 | /* We already know these can't conflict with a later output. So the |
d1d18b46 DJ |
5024 | only thing to check are later output addresses. |
5025 | Note that multiple output operands are emitted in reverse order, | |
5026 | so the conflicting ones are those with lower indices. */ | |
5027 | for (i = 0; i < opnum; i++) | |
47c8cf91 ILT |
5028 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
5029 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
5030 | return 0; |
5031 | ||
32131a9c | 5032 | return 1; |
546b63fb | 5033 | |
41374e13 NS |
5034 | default: |
5035 | gcc_unreachable (); | |
5036 | } | |
32131a9c | 5037 | } |
fb959f72 RS |
5038 | |
5039 | /* Like reload_reg_reaches_end_p, but check that the condition holds for | |
5040 | every register in the range [REGNO, REGNO + NREGS). */ | |
5041 | ||
5042 | static bool | |
5043 | reload_regs_reach_end_p (unsigned int regno, int nregs, | |
5044 | int opnum, enum reload_type type) | |
5045 | { | |
5046 | int i; | |
5047 | ||
5048 | for (i = 0; i < nregs; i++) | |
5049 | if (!reload_reg_reaches_end_p (regno + i, opnum, type)) | |
5050 | return false; | |
5051 | return true; | |
5052 | } | |
32131a9c | 5053 | \f |
d2c9375a DD |
5054 | |
5055 | /* Returns whether R1 and R2 are uniquely chained: the value of one | |
5056 | is used by the other, and that value is not used by any other | |
5057 | reload for this insn. This is used to partially undo the decision | |
5058 | made in find_reloads when in the case of multiple | |
5059 | RELOAD_FOR_OPERAND_ADDRESS reloads it converts all | |
5060 | RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS | |
5061 | reloads. This code tries to avoid the conflict created by that | |
5062 | change. It might be cleaner to explicitly keep track of which | |
5063 | RELOAD_FOR_OPADDR_ADDR reload is associated with which | |
5064 | RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect | |
5065 | this after the fact. */ | |
5066 | static bool | |
5067 | reloads_unique_chain_p (int r1, int r2) | |
5068 | { | |
5069 | int i; | |
5070 | ||
5071 | /* We only check input reloads. */ | |
5072 | if (! rld[r1].in || ! rld[r2].in) | |
5073 | return false; | |
5074 | ||
5075 | /* Avoid anything with output reloads. */ | |
5076 | if (rld[r1].out || rld[r2].out) | |
5077 | return false; | |
5078 | ||
5079 | /* "chained" means one reload is a component of the other reload, | |
5080 | not the same as the other reload. */ | |
5081 | if (rld[r1].opnum != rld[r2].opnum | |
5082 | || rtx_equal_p (rld[r1].in, rld[r2].in) | |
5083 | || rld[r1].optional || rld[r2].optional | |
5084 | || ! (reg_mentioned_p (rld[r1].in, rld[r2].in) | |
5085 | || reg_mentioned_p (rld[r2].in, rld[r1].in))) | |
5086 | return false; | |
5087 | ||
5088 | for (i = 0; i < n_reloads; i ++) | |
5089 | /* Look for input reloads that aren't our two */ | |
5090 | if (i != r1 && i != r2 && rld[i].in) | |
5091 | { | |
5092 | /* If our reload is mentioned at all, it isn't a simple chain. */ | |
5093 | if (reg_mentioned_p (rld[r1].in, rld[i].in)) | |
5094 | return false; | |
5095 | } | |
5096 | return true; | |
5097 | } | |
5098 | ||
058e97ec VM |
5099 | |
5100 | /* The recursive function change all occurrences of WHAT in *WHERE | |
5101 | onto REPL. */ | |
5102 | static void | |
5103 | substitute (rtx *where, const_rtx what, rtx repl) | |
5104 | { | |
5105 | const char *fmt; | |
5106 | int i; | |
5107 | enum rtx_code code; | |
5108 | ||
5109 | if (*where == 0) | |
5110 | return; | |
5111 | ||
5112 | if (*where == what || rtx_equal_p (*where, what)) | |
5113 | { | |
5114 | *where = repl; | |
5115 | return; | |
5116 | } | |
5117 | ||
5118 | code = GET_CODE (*where); | |
5119 | fmt = GET_RTX_FORMAT (code); | |
5120 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5121 | { | |
5122 | if (fmt[i] == 'E') | |
5123 | { | |
5124 | int j; | |
5125 | ||
5126 | for (j = XVECLEN (*where, i) - 1; j >= 0; j--) | |
5127 | substitute (&XVECEXP (*where, i, j), what, repl); | |
5128 | } | |
5129 | else if (fmt[i] == 'e') | |
5130 | substitute (&XEXP (*where, i), what, repl); | |
5131 | } | |
5132 | } | |
5133 | ||
5134 | /* The function returns TRUE if chain of reload R1 and R2 (in any | |
5135 | order) can be evaluated without usage of intermediate register for | |
5136 | the reload containing another reload. It is important to see | |
5137 | gen_reload to understand what the function is trying to do. As an | |
5138 | example, let us have reload chain | |
5139 | ||
5140 | r2: const | |
5141 | r1: <something> + const | |
5142 | ||
5143 | and reload R2 got reload reg HR. The function returns true if | |
5144 | there is a correct insn HR = HR + <something>. Otherwise, | |
5145 | gen_reload will use intermediate register (and this is the reload | |
5146 | reg for R1) to reload <something>. | |
5147 | ||
5148 | We need this function to find a conflict for chain reloads. In our | |
5149 | example, if HR = HR + <something> is incorrect insn, then we cannot | |
5150 | use HR as a reload register for R2. If we do use it then we get a | |
5151 | wrong code: | |
5152 | ||
5153 | HR = const | |
5154 | HR = <something> | |
5155 | HR = HR + HR | |
5156 | ||
5157 | */ | |
5158 | static bool | |
5159 | gen_reload_chain_without_interm_reg_p (int r1, int r2) | |
5160 | { | |
5161 | bool result; | |
5162 | int regno, n, code; | |
5163 | rtx out, in, tem, insn; | |
5164 | rtx last = get_last_insn (); | |
5165 | ||
5166 | /* Make r2 a component of r1. */ | |
5167 | if (reg_mentioned_p (rld[r1].in, rld[r2].in)) | |
5168 | { | |
5169 | n = r1; | |
5170 | r1 = r2; | |
5171 | r2 = n; | |
5172 | } | |
5173 | gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in)); | |
5174 | regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno; | |
5175 | gcc_assert (regno >= 0); | |
5176 | out = gen_rtx_REG (rld[r1].mode, regno); | |
5177 | in = copy_rtx (rld[r1].in); | |
5178 | substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno)); | |
5179 | ||
5180 | /* If IN is a paradoxical SUBREG, remove it and try to put the | |
5181 | opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ | |
5182 | if (GET_CODE (in) == SUBREG | |
5183 | && (GET_MODE_SIZE (GET_MODE (in)) | |
5184 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
5185 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0) | |
5186 | in = SUBREG_REG (in), out = tem; | |
5187 | ||
5188 | if (GET_CODE (in) == PLUS | |
5189 | && (REG_P (XEXP (in, 0)) | |
5190 | || GET_CODE (XEXP (in, 0)) == SUBREG | |
5191 | || MEM_P (XEXP (in, 0))) | |
5192 | && (REG_P (XEXP (in, 1)) | |
5193 | || GET_CODE (XEXP (in, 1)) == SUBREG | |
5194 | || CONSTANT_P (XEXP (in, 1)) | |
5195 | || MEM_P (XEXP (in, 1)))) | |
5196 | { | |
5197 | insn = emit_insn (gen_rtx_SET (VOIDmode, out, in)); | |
5198 | code = recog_memoized (insn); | |
5199 | result = false; | |
5200 | ||
5201 | if (code >= 0) | |
5202 | { | |
5203 | extract_insn (insn); | |
5204 | /* We want constrain operands to treat this insn strictly in | |
5205 | its validity determination, i.e., the way it would after | |
5206 | reload has completed. */ | |
5207 | result = constrain_operands (1); | |
5208 | } | |
5209 | ||
5210 | delete_insns_since (last); | |
5211 | return result; | |
5212 | } | |
5213 | ||
5214 | /* It looks like other cases in gen_reload are not possible for | |
5215 | chain reloads or do need an intermediate hard registers. */ | |
5216 | return true; | |
5217 | } | |
5218 | ||
351aa1c1 RK |
5219 | /* Return 1 if the reloads denoted by R1 and R2 cannot share a register. |
5220 | Return 0 otherwise. | |
5221 | ||
5222 | This function uses the same algorithm as reload_reg_free_p above. */ | |
5223 | ||
bf9a0db3 | 5224 | static int |
0c20a65f | 5225 | reloads_conflict (int r1, int r2) |
351aa1c1 | 5226 | { |
eceef4c9 BS |
5227 | enum reload_type r1_type = rld[r1].when_needed; |
5228 | enum reload_type r2_type = rld[r2].when_needed; | |
5229 | int r1_opnum = rld[r1].opnum; | |
5230 | int r2_opnum = rld[r2].opnum; | |
351aa1c1 | 5231 | |
2edc8d65 RK |
5232 | /* RELOAD_OTHER conflicts with everything. */ |
5233 | if (r2_type == RELOAD_OTHER) | |
351aa1c1 RK |
5234 | return 1; |
5235 | ||
5236 | /* Otherwise, check conflicts differently for each type. */ | |
5237 | ||
5238 | switch (r1_type) | |
5239 | { | |
5240 | case RELOAD_FOR_INPUT: | |
05d10675 | 5241 | return (r2_type == RELOAD_FOR_INSN |
351aa1c1 | 5242 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS |
893bc853 | 5243 | || r2_type == RELOAD_FOR_OPADDR_ADDR |
351aa1c1 | 5244 | || r2_type == RELOAD_FOR_INPUT |
47c8cf91 ILT |
5245 | || ((r2_type == RELOAD_FOR_INPUT_ADDRESS |
5246 | || r2_type == RELOAD_FOR_INPADDR_ADDRESS) | |
5247 | && r2_opnum > r1_opnum)); | |
351aa1c1 RK |
5248 | |
5249 | case RELOAD_FOR_INPUT_ADDRESS: | |
5250 | return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum) | |
5251 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
5252 | ||
47c8cf91 ILT |
5253 | case RELOAD_FOR_INPADDR_ADDRESS: |
5254 | return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum) | |
5255 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
5256 | ||
351aa1c1 RK |
5257 | case RELOAD_FOR_OUTPUT_ADDRESS: |
5258 | return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum) | |
d1d18b46 | 5259 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); |
351aa1c1 | 5260 | |
47c8cf91 ILT |
5261 | case RELOAD_FOR_OUTADDR_ADDRESS: |
5262 | return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum) | |
d1d18b46 | 5263 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); |
47c8cf91 | 5264 | |
351aa1c1 RK |
5265 | case RELOAD_FOR_OPERAND_ADDRESS: |
5266 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN | |
d2c9375a | 5267 | || (r2_type == RELOAD_FOR_OPERAND_ADDRESS |
058e97ec VM |
5268 | && (!reloads_unique_chain_p (r1, r2) |
5269 | || !gen_reload_chain_without_interm_reg_p (r1, r2)))); | |
351aa1c1 | 5270 | |
893bc853 | 5271 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 | 5272 | return (r2_type == RELOAD_FOR_INPUT |
a94ce333 | 5273 | || r2_type == RELOAD_FOR_OPADDR_ADDR); |
893bc853 | 5274 | |
351aa1c1 RK |
5275 | case RELOAD_FOR_OUTPUT: |
5276 | return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT | |
47c8cf91 ILT |
5277 | || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS |
5278 | || r2_type == RELOAD_FOR_OUTADDR_ADDRESS) | |
d1d18b46 | 5279 | && r2_opnum >= r1_opnum)); |
351aa1c1 RK |
5280 | |
5281 | case RELOAD_FOR_INSN: | |
5282 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT | |
5283 | || r2_type == RELOAD_FOR_INSN | |
5284 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); | |
5285 | ||
5286 | case RELOAD_FOR_OTHER_ADDRESS: | |
5287 | return r2_type == RELOAD_FOR_OTHER_ADDRESS; | |
5288 | ||
adab4fc5 | 5289 | case RELOAD_OTHER: |
2edc8d65 | 5290 | return 1; |
adab4fc5 | 5291 | |
351aa1c1 | 5292 | default: |
41374e13 | 5293 | gcc_unreachable (); |
351aa1c1 RK |
5294 | } |
5295 | } | |
5296 | \f | |
32131a9c RK |
5297 | /* Indexed by reload number, 1 if incoming value |
5298 | inherited from previous insns. */ | |
cf0fa607 | 5299 | static char reload_inherited[MAX_RELOADS]; |
32131a9c RK |
5300 | |
5301 | /* For an inherited reload, this is the insn the reload was inherited from, | |
5302 | if we know it. Otherwise, this is 0. */ | |
cf0fa607 | 5303 | static rtx reload_inheritance_insn[MAX_RELOADS]; |
32131a9c | 5304 | |
40f03658 | 5305 | /* If nonzero, this is a place to get the value of the reload, |
32131a9c | 5306 | rather than using reload_in. */ |
cf0fa607 | 5307 | static rtx reload_override_in[MAX_RELOADS]; |
32131a9c | 5308 | |
e6e52be0 R |
5309 | /* For each reload, the hard register number of the register used, |
5310 | or -1 if we did not need a register for this reload. */ | |
cf0fa607 | 5311 | static int reload_spill_index[MAX_RELOADS]; |
32131a9c | 5312 | |
fb959f72 RS |
5313 | /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */ |
5314 | static rtx reload_reg_rtx_for_input[MAX_RELOADS]; | |
5315 | ||
5316 | /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */ | |
5317 | static rtx reload_reg_rtx_for_output[MAX_RELOADS]; | |
5318 | ||
304a22dd R |
5319 | /* Subroutine of free_for_value_p, used to check a single register. |
5320 | START_REGNO is the starting regno of the full reload register | |
5321 | (possibly comprising multiple hard registers) that we are considering. */ | |
f5470689 | 5322 | |
6e684430 | 5323 | static int |
0c20a65f AJ |
5324 | reload_reg_free_for_value_p (int start_regno, int regno, int opnum, |
5325 | enum reload_type type, rtx value, rtx out, | |
5326 | int reloadnum, int ignore_address_reloads) | |
6e684430 R |
5327 | { |
5328 | int time1; | |
09a308fe R |
5329 | /* Set if we see an input reload that must not share its reload register |
5330 | with any new earlyclobber, but might otherwise share the reload | |
5331 | register with an output or input-output reload. */ | |
5332 | int check_earlyclobber = 0; | |
6e684430 | 5333 | int i; |
dfe96118 R |
5334 | int copy = 0; |
5335 | ||
9e3a9cf2 | 5336 | if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) |
dc8842bf AH |
5337 | return 0; |
5338 | ||
dfe96118 R |
5339 | if (out == const0_rtx) |
5340 | { | |
5341 | copy = 1; | |
5342 | out = NULL_RTX; | |
5343 | } | |
6e684430 R |
5344 | |
5345 | /* We use some pseudo 'time' value to check if the lifetimes of the | |
5346 | new register use would overlap with the one of a previous reload | |
5347 | that is not read-only or uses a different value. | |
5348 | The 'time' used doesn't have to be linear in any shape or form, just | |
5349 | monotonic. | |
5350 | Some reload types use different 'buckets' for each operand. | |
5351 | So there are MAX_RECOG_OPERANDS different time values for each | |
cecbf6e2 R |
5352 | such reload type. |
5353 | We compute TIME1 as the time when the register for the prospective | |
5354 | new reload ceases to be live, and TIME2 for each existing | |
5355 | reload as the time when that the reload register of that reload | |
5356 | becomes live. | |
5357 | Where there is little to be gained by exact lifetime calculations, | |
5358 | we just make conservative assumptions, i.e. a longer lifetime; | |
5359 | this is done in the 'default:' cases. */ | |
6e684430 R |
5360 | switch (type) |
5361 | { | |
5362 | case RELOAD_FOR_OTHER_ADDRESS: | |
203588e7 | 5363 | /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */ |
c2b4b171 | 5364 | time1 = copy ? 0 : 1; |
6e684430 | 5365 | break; |
dfe96118 R |
5366 | case RELOAD_OTHER: |
5367 | time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5; | |
5368 | break; | |
05d10675 BS |
5369 | /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS, |
5370 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 , | |
5371 | respectively, to the time values for these, we get distinct time | |
5372 | values. To get distinct time values for each operand, we have to | |
5373 | multiply opnum by at least three. We round that up to four because | |
5374 | multiply by four is often cheaper. */ | |
6e684430 | 5375 | case RELOAD_FOR_INPADDR_ADDRESS: |
dfe96118 | 5376 | time1 = opnum * 4 + 2; |
6e684430 R |
5377 | break; |
5378 | case RELOAD_FOR_INPUT_ADDRESS: | |
dfe96118 R |
5379 | time1 = opnum * 4 + 3; |
5380 | break; | |
5381 | case RELOAD_FOR_INPUT: | |
5382 | /* All RELOAD_FOR_INPUT reloads remain live till the instruction | |
5383 | executes (inclusive). */ | |
5384 | time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3; | |
6e684430 | 5385 | break; |
cb2afeb3 | 5386 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 BS |
5387 | /* opnum * 4 + 4 |
5388 | <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */ | |
cb2afeb3 R |
5389 | time1 = MAX_RECOG_OPERANDS * 4 + 1; |
5390 | break; | |
5391 | case RELOAD_FOR_OPERAND_ADDRESS: | |
5392 | /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn | |
5393 | is executed. */ | |
dfe96118 R |
5394 | time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3; |
5395 | break; | |
5396 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
5397 | time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum; | |
6e684430 | 5398 | break; |
6e684430 | 5399 | case RELOAD_FOR_OUTPUT_ADDRESS: |
dfe96118 | 5400 | time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum; |
6e684430 R |
5401 | break; |
5402 | default: | |
dfe96118 | 5403 | time1 = MAX_RECOG_OPERANDS * 5 + 5; |
6e684430 R |
5404 | } |
5405 | ||
5406 | for (i = 0; i < n_reloads; i++) | |
5407 | { | |
eceef4c9 | 5408 | rtx reg = rld[i].reg_rtx; |
f8cfc6aa | 5409 | if (reg && REG_P (reg) |
6e684430 | 5410 | && ((unsigned) regno - true_regnum (reg) |
66fd46b6 | 5411 | <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1) |
f5470689 | 5412 | && i != reloadnum) |
6e684430 | 5413 | { |
304a22dd R |
5414 | rtx other_input = rld[i].in; |
5415 | ||
5416 | /* If the other reload loads the same input value, that | |
5417 | will not cause a conflict only if it's loading it into | |
5418 | the same register. */ | |
5419 | if (true_regnum (reg) != start_regno) | |
5420 | other_input = NULL_RTX; | |
5421 | if (! other_input || ! rtx_equal_p (other_input, value) | |
eceef4c9 | 5422 | || rld[i].out || out) |
6e684430 | 5423 | { |
09a308fe | 5424 | int time2; |
eceef4c9 | 5425 | switch (rld[i].when_needed) |
f5470689 R |
5426 | { |
5427 | case RELOAD_FOR_OTHER_ADDRESS: | |
5428 | time2 = 0; | |
5429 | break; | |
5430 | case RELOAD_FOR_INPADDR_ADDRESS: | |
cb2afeb3 R |
5431 | /* find_reloads makes sure that a |
5432 | RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used | |
5433 | by at most one - the first - | |
5434 | RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the | |
5435 | address reload is inherited, the address address reload | |
5436 | goes away, so we can ignore this conflict. */ | |
dfe96118 R |
5437 | if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1 |
5438 | && ignore_address_reloads | |
5439 | /* Unless the RELOAD_FOR_INPUT is an auto_inc expression. | |
5440 | Then the address address is still needed to store | |
5441 | back the new address. */ | |
eceef4c9 | 5442 | && ! rld[reloadnum].out) |
cb2afeb3 | 5443 | continue; |
dfe96118 R |
5444 | /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its |
5445 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS | |
5446 | reloads go away. */ | |
eceef4c9 | 5447 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 R |
5448 | && ignore_address_reloads |
5449 | /* Unless we are reloading an auto_inc expression. */ | |
eceef4c9 | 5450 | && ! rld[reloadnum].out) |
dfe96118 | 5451 | continue; |
eceef4c9 | 5452 | time2 = rld[i].opnum * 4 + 2; |
f5470689 R |
5453 | break; |
5454 | case RELOAD_FOR_INPUT_ADDRESS: | |
eceef4c9 | 5455 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 | 5456 | && ignore_address_reloads |
eceef4c9 | 5457 | && ! rld[reloadnum].out) |
dfe96118 | 5458 | continue; |
eceef4c9 | 5459 | time2 = rld[i].opnum * 4 + 3; |
f5470689 R |
5460 | break; |
5461 | case RELOAD_FOR_INPUT: | |
eceef4c9 | 5462 | time2 = rld[i].opnum * 4 + 4; |
09a308fe | 5463 | check_earlyclobber = 1; |
f5470689 | 5464 | break; |
eceef4c9 | 5465 | /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4 |
05d10675 | 5466 | == MAX_RECOG_OPERAND * 4 */ |
cb2afeb3 | 5467 | case RELOAD_FOR_OPADDR_ADDR: |
dfe96118 R |
5468 | if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1 |
5469 | && ignore_address_reloads | |
eceef4c9 | 5470 | && ! rld[reloadnum].out) |
cb2afeb3 | 5471 | continue; |
dfe96118 | 5472 | time2 = MAX_RECOG_OPERANDS * 4 + 1; |
cb2afeb3 R |
5473 | break; |
5474 | case RELOAD_FOR_OPERAND_ADDRESS: | |
dfe96118 | 5475 | time2 = MAX_RECOG_OPERANDS * 4 + 2; |
09a308fe | 5476 | check_earlyclobber = 1; |
dfe96118 R |
5477 | break; |
5478 | case RELOAD_FOR_INSN: | |
5479 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
cb2afeb3 | 5480 | break; |
f5470689 | 5481 | case RELOAD_FOR_OUTPUT: |
05d10675 BS |
5482 | /* All RELOAD_FOR_OUTPUT reloads become live just after the |
5483 | instruction is executed. */ | |
dfe96118 | 5484 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
f5470689 | 5485 | break; |
05d10675 BS |
5486 | /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with |
5487 | the RELOAD_FOR_OUTPUT reloads, so assign it the same time | |
5488 | value. */ | |
cb2afeb3 | 5489 | case RELOAD_FOR_OUTADDR_ADDRESS: |
dfe96118 R |
5490 | if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1 |
5491 | && ignore_address_reloads | |
eceef4c9 | 5492 | && ! rld[reloadnum].out) |
cb2afeb3 | 5493 | continue; |
eceef4c9 | 5494 | time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum; |
dfe96118 | 5495 | break; |
f5470689 | 5496 | case RELOAD_FOR_OUTPUT_ADDRESS: |
eceef4c9 | 5497 | time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum; |
f5470689 R |
5498 | break; |
5499 | case RELOAD_OTHER: | |
dfe96118 R |
5500 | /* If there is no conflict in the input part, handle this |
5501 | like an output reload. */ | |
304a22dd | 5502 | if (! rld[i].in || rtx_equal_p (other_input, value)) |
f5470689 | 5503 | { |
dfe96118 | 5504 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
57850c85 | 5505 | /* Earlyclobbered outputs must conflict with inputs. */ |
09a308fe R |
5506 | if (earlyclobber_operand_p (rld[i].out)) |
5507 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
1d7254c5 | 5508 | |
f5470689 R |
5509 | break; |
5510 | } | |
dfe96118 R |
5511 | time2 = 1; |
5512 | /* RELOAD_OTHER might be live beyond instruction execution, | |
5513 | but this is not obvious when we set time2 = 1. So check | |
5514 | here if there might be a problem with the new reload | |
5515 | clobbering the register used by the RELOAD_OTHER. */ | |
5516 | if (out) | |
5517 | return 0; | |
5518 | break; | |
f5470689 | 5519 | default: |
dfe96118 | 5520 | return 0; |
f5470689 | 5521 | } |
25963977 | 5522 | if ((time1 >= time2 |
eceef4c9 | 5523 | && (! rld[i].in || rld[i].out |
304a22dd | 5524 | || ! rtx_equal_p (other_input, value))) |
eceef4c9 | 5525 | || (out && rld[reloadnum].out_reg |
701d55e8 | 5526 | && time2 >= MAX_RECOG_OPERANDS * 4 + 3)) |
f5470689 | 5527 | return 0; |
6e684430 | 5528 | } |
6e684430 R |
5529 | } |
5530 | } | |
09a308fe R |
5531 | |
5532 | /* Earlyclobbered outputs must conflict with inputs. */ | |
5533 | if (check_earlyclobber && out && earlyclobber_operand_p (out)) | |
5534 | return 0; | |
5535 | ||
6e684430 R |
5536 | return 1; |
5537 | } | |
5538 | ||
c02cad8f BS |
5539 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
5540 | needed for the part of the insn specified by OPNUM and TYPE, | |
5541 | may be used to load VALUE into it. | |
5542 | ||
5543 | MODE is the mode in which the register is used, this is needed to | |
5544 | determine how many hard regs to test. | |
5545 | ||
5546 | Other read-only reloads with the same value do not conflict | |
40f03658 | 5547 | unless OUT is nonzero and these other reloads have to live while |
c02cad8f BS |
5548 | output reloads live. |
5549 | If OUT is CONST0_RTX, this is a special case: it means that the | |
5550 | test should not be for using register REGNO as reload register, but | |
5551 | for copying from register REGNO into the reload register. | |
5552 | ||
5553 | RELOADNUM is the number of the reload we want to load this value for; | |
5554 | a reload does not conflict with itself. | |
5555 | ||
5556 | When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with | |
5557 | reloads that load an address for the very reload we are considering. | |
5558 | ||
5559 | The caller has to make sure that there is no conflict with the return | |
5560 | register. */ | |
5561 | ||
5562 | static int | |
0c20a65f AJ |
5563 | free_for_value_p (int regno, enum machine_mode mode, int opnum, |
5564 | enum reload_type type, rtx value, rtx out, int reloadnum, | |
5565 | int ignore_address_reloads) | |
c02cad8f | 5566 | { |
66fd46b6 | 5567 | int nregs = hard_regno_nregs[regno][mode]; |
c02cad8f | 5568 | while (nregs-- > 0) |
304a22dd R |
5569 | if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type, |
5570 | value, out, reloadnum, | |
5571 | ignore_address_reloads)) | |
c02cad8f BS |
5572 | return 0; |
5573 | return 1; | |
5574 | } | |
5575 | ||
86caf04d | 5576 | /* Return nonzero if the rtx X is invariant over the current function. */ |
0e61db61 NS |
5577 | /* ??? Actually, the places where we use this expect exactly what is |
5578 | tested here, and not everything that is function invariant. In | |
5579 | particular, the frame pointer and arg pointer are special cased; | |
5580 | pic_offset_table_rtx is not, and we must not spill these things to | |
5581 | memory. */ | |
86caf04d | 5582 | |
5fffc382 | 5583 | int |
4f588890 | 5584 | function_invariant_p (const_rtx x) |
86caf04d PB |
5585 | { |
5586 | if (CONSTANT_P (x)) | |
5587 | return 1; | |
5588 | if (x == frame_pointer_rtx || x == arg_pointer_rtx) | |
5589 | return 1; | |
5590 | if (GET_CODE (x) == PLUS | |
5591 | && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx) | |
5592 | && CONSTANT_P (XEXP (x, 1))) | |
5593 | return 1; | |
5594 | return 0; | |
5595 | } | |
5596 | ||
ff6534ad BS |
5597 | /* Determine whether the reload reg X overlaps any rtx'es used for |
5598 | overriding inheritance. Return nonzero if so. */ | |
5599 | ||
5600 | static int | |
0c20a65f | 5601 | conflicts_with_override (rtx x) |
ff6534ad BS |
5602 | { |
5603 | int i; | |
5604 | for (i = 0; i < n_reloads; i++) | |
5605 | if (reload_override_in[i] | |
5606 | && reg_overlap_mentioned_p (x, reload_override_in[i])) | |
5607 | return 1; | |
5608 | return 0; | |
5609 | } | |
5610 | \f | |
67e61fe7 BS |
5611 | /* Give an error message saying we failed to find a reload for INSN, |
5612 | and clear out reload R. */ | |
5613 | static void | |
0c20a65f | 5614 | failed_reload (rtx insn, int r) |
67e61fe7 BS |
5615 | { |
5616 | if (asm_noperands (PATTERN (insn)) < 0) | |
5617 | /* It's the compiler's fault. */ | |
1f978f5f | 5618 | fatal_insn ("could not find a spill register", insn); |
67e61fe7 BS |
5619 | |
5620 | /* It's the user's fault; the operand's mode and constraint | |
5621 | don't match. Disable this reload so we don't crash in final. */ | |
5622 | error_for_asm (insn, | |
971801ff | 5623 | "%<asm%> operand constraint incompatible with operand size"); |
67e61fe7 BS |
5624 | rld[r].in = 0; |
5625 | rld[r].out = 0; | |
5626 | rld[r].reg_rtx = 0; | |
5627 | rld[r].optional = 1; | |
5628 | rld[r].secondary_p = 1; | |
5629 | } | |
5630 | ||
5631 | /* I is the index in SPILL_REG_RTX of the reload register we are to allocate | |
5632 | for reload R. If it's valid, get an rtx for it. Return nonzero if | |
5633 | successful. */ | |
5634 | static int | |
0c20a65f | 5635 | set_reload_reg (int i, int r) |
67e61fe7 BS |
5636 | { |
5637 | int regno; | |
5638 | rtx reg = spill_reg_rtx[i]; | |
5639 | ||
5640 | if (reg == 0 || GET_MODE (reg) != rld[r].mode) | |
5641 | spill_reg_rtx[i] = reg | |
5642 | = gen_rtx_REG (rld[r].mode, spill_regs[i]); | |
5643 | ||
5644 | regno = true_regnum (reg); | |
5645 | ||
5646 | /* Detect when the reload reg can't hold the reload mode. | |
5647 | This used to be one `if', but Sequent compiler can't handle that. */ | |
5648 | if (HARD_REGNO_MODE_OK (regno, rld[r].mode)) | |
5649 | { | |
5650 | enum machine_mode test_mode = VOIDmode; | |
5651 | if (rld[r].in) | |
5652 | test_mode = GET_MODE (rld[r].in); | |
5653 | /* If rld[r].in has VOIDmode, it means we will load it | |
5654 | in whatever mode the reload reg has: to wit, rld[r].mode. | |
5655 | We have already tested that for validity. */ | |
5656 | /* Aside from that, we need to test that the expressions | |
5657 | to reload from or into have modes which are valid for this | |
5658 | reload register. Otherwise the reload insns would be invalid. */ | |
5659 | if (! (rld[r].in != 0 && test_mode != VOIDmode | |
5660 | && ! HARD_REGNO_MODE_OK (regno, test_mode))) | |
5661 | if (! (rld[r].out != 0 | |
5662 | && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out)))) | |
5663 | { | |
5664 | /* The reg is OK. */ | |
5665 | last_spill_reg = i; | |
5666 | ||
5667 | /* Mark as in use for this insn the reload regs we use | |
5668 | for this. */ | |
5669 | mark_reload_reg_in_use (spill_regs[i], rld[r].opnum, | |
5670 | rld[r].when_needed, rld[r].mode); | |
5671 | ||
5672 | rld[r].reg_rtx = reg; | |
5673 | reload_spill_index[r] = spill_regs[i]; | |
5674 | return 1; | |
5675 | } | |
5676 | } | |
5677 | return 0; | |
5678 | } | |
5679 | ||
32131a9c | 5680 | /* Find a spill register to use as a reload register for reload R. |
40f03658 | 5681 | LAST_RELOAD is nonzero if this is the last reload for the insn being |
32131a9c RK |
5682 | processed. |
5683 | ||
eceef4c9 | 5684 | Set rld[R].reg_rtx to the register allocated. |
32131a9c | 5685 | |
f5d8c9f4 BS |
5686 | We return 1 if successful, or 0 if we couldn't find a spill reg and |
5687 | we didn't change anything. */ | |
32131a9c RK |
5688 | |
5689 | static int | |
0c20a65f AJ |
5690 | allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r, |
5691 | int last_reload) | |
32131a9c | 5692 | { |
67e61fe7 | 5693 | int i, pass, count; |
32131a9c RK |
5694 | |
5695 | /* If we put this reload ahead, thinking it is a group, | |
5696 | then insist on finding a group. Otherwise we can grab a | |
a8fdc208 | 5697 | reg that some other reload needs. |
32131a9c RK |
5698 | (That can happen when we have a 68000 DATA_OR_FP_REG |
5699 | which is a group of data regs or one fp reg.) | |
5700 | We need not be so restrictive if there are no more reloads | |
5701 | for this insn. | |
5702 | ||
5703 | ??? Really it would be nicer to have smarter handling | |
5704 | for that kind of reg class, where a problem like this is normal. | |
5705 | Perhaps those classes should be avoided for reloading | |
5706 | by use of more alternatives. */ | |
5707 | ||
8ec450a4 | 5708 | int force_group = rld[r].nregs > 1 && ! last_reload; |
32131a9c RK |
5709 | |
5710 | /* If we want a single register and haven't yet found one, | |
5711 | take any reg in the right class and not in use. | |
5712 | If we want a consecutive group, here is where we look for it. | |
5713 | ||
5714 | We use two passes so we can first look for reload regs to | |
5715 | reuse, which are already in use for other reloads in this insn, | |
5716 | and only then use additional registers. | |
5717 | I think that maximizing reuse is needed to make sure we don't | |
5718 | run out of reload regs. Suppose we have three reloads, and | |
5719 | reloads A and B can share regs. These need two regs. | |
5720 | Suppose A and B are given different regs. | |
5721 | That leaves none for C. */ | |
5722 | for (pass = 0; pass < 2; pass++) | |
5723 | { | |
5724 | /* I is the index in spill_regs. | |
5725 | We advance it round-robin between insns to use all spill regs | |
5726 | equally, so that inherited reloads have a chance | |
f5d8c9f4 BS |
5727 | of leapfrogging each other. */ |
5728 | ||
5729 | i = last_spill_reg; | |
05d10675 | 5730 | |
a5339699 | 5731 | for (count = 0; count < n_spills; count++) |
32131a9c | 5732 | { |
48c54229 | 5733 | int rclass = (int) rld[r].rclass; |
03acd8f8 | 5734 | int regnum; |
32131a9c | 5735 | |
03acd8f8 BS |
5736 | i++; |
5737 | if (i >= n_spills) | |
5738 | i -= n_spills; | |
5739 | regnum = spill_regs[i]; | |
32131a9c | 5740 | |
eceef4c9 BS |
5741 | if ((reload_reg_free_p (regnum, rld[r].opnum, |
5742 | rld[r].when_needed) | |
5743 | || (rld[r].in | |
05d10675 BS |
5744 | /* We check reload_reg_used to make sure we |
5745 | don't clobber the return register. */ | |
03acd8f8 | 5746 | && ! TEST_HARD_REG_BIT (reload_reg_used, regnum) |
c02cad8f BS |
5747 | && free_for_value_p (regnum, rld[r].mode, rld[r].opnum, |
5748 | rld[r].when_needed, rld[r].in, | |
5749 | rld[r].out, r, 1))) | |
55d796da | 5750 | && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum) |
8ec450a4 | 5751 | && HARD_REGNO_MODE_OK (regnum, rld[r].mode) |
be7ae2a4 RK |
5752 | /* Look first for regs to share, then for unshared. But |
5753 | don't share regs used for inherited reloads; they are | |
5754 | the ones we want to preserve. */ | |
5755 | && (pass | |
5756 | || (TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
03acd8f8 | 5757 | regnum) |
be7ae2a4 | 5758 | && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, |
03acd8f8 | 5759 | regnum)))) |
32131a9c | 5760 | { |
66fd46b6 | 5761 | int nr = hard_regno_nregs[regnum][rld[r].mode]; |
32131a9c RK |
5762 | /* Avoid the problem where spilling a GENERAL_OR_FP_REG |
5763 | (on 68000) got us two FP regs. If NR is 1, | |
5764 | we would reject both of them. */ | |
5765 | if (force_group) | |
67e61fe7 | 5766 | nr = rld[r].nregs; |
32131a9c RK |
5767 | /* If we need only one reg, we have already won. */ |
5768 | if (nr == 1) | |
5769 | { | |
5770 | /* But reject a single reg if we demand a group. */ | |
5771 | if (force_group) | |
5772 | continue; | |
5773 | break; | |
5774 | } | |
5775 | /* Otherwise check that as many consecutive regs as we need | |
f5d8c9f4 BS |
5776 | are available here. */ |
5777 | while (nr > 1) | |
5778 | { | |
5779 | int regno = regnum + nr - 1; | |
55d796da | 5780 | if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno) |
f5d8c9f4 BS |
5781 | && spill_reg_order[regno] >= 0 |
5782 | && reload_reg_free_p (regno, rld[r].opnum, | |
5783 | rld[r].when_needed))) | |
5784 | break; | |
5785 | nr--; | |
5786 | } | |
32131a9c RK |
5787 | if (nr == 1) |
5788 | break; | |
5789 | } | |
5790 | } | |
5791 | ||
5792 | /* If we found something on pass 1, omit pass 2. */ | |
5793 | if (count < n_spills) | |
5794 | break; | |
5795 | } | |
1d7254c5 | 5796 | |
32131a9c | 5797 | /* We should have found a spill register by now. */ |
f5d8c9f4 | 5798 | if (count >= n_spills) |
32131a9c RK |
5799 | return 0; |
5800 | ||
f5d8c9f4 BS |
5801 | /* I is the index in SPILL_REG_RTX of the reload register we are to |
5802 | allocate. Get an rtx for it and find its register number. */ | |
32131a9c | 5803 | |
f5d8c9f4 | 5804 | return set_reload_reg (i, r); |
32131a9c RK |
5805 | } |
5806 | \f | |
67e61fe7 BS |
5807 | /* Initialize all the tables needed to allocate reload registers. |
5808 | CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX | |
5809 | is the array we use to restore the reg_rtx field for every reload. */ | |
efc9bd41 | 5810 | |
32131a9c | 5811 | static void |
0c20a65f | 5812 | choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx) |
32131a9c | 5813 | { |
67e61fe7 | 5814 | int i; |
32131a9c | 5815 | |
67e61fe7 BS |
5816 | for (i = 0; i < n_reloads; i++) |
5817 | rld[i].reg_rtx = save_reload_reg_rtx[i]; | |
32131a9c | 5818 | |
961192e1 | 5819 | memset (reload_inherited, 0, MAX_RELOADS); |
703ad42b KG |
5820 | memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx)); |
5821 | memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx)); | |
32131a9c RK |
5822 | |
5823 | CLEAR_HARD_REG_SET (reload_reg_used); | |
5824 | CLEAR_HARD_REG_SET (reload_reg_used_at_all); | |
32131a9c | 5825 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); |
893bc853 | 5826 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload); |
546b63fb RK |
5827 | CLEAR_HARD_REG_SET (reload_reg_used_in_insn); |
5828 | CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); | |
32131a9c | 5829 | |
f1db3576 JL |
5830 | CLEAR_HARD_REG_SET (reg_used_in_insn); |
5831 | { | |
5832 | HARD_REG_SET tmp; | |
239a0f5b | 5833 | REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout); |
f1db3576 | 5834 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b | 5835 | REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set); |
f1db3576 | 5836 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b BS |
5837 | compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout); |
5838 | compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set); | |
f1db3576 | 5839 | } |
efc9bd41 | 5840 | |
546b63fb RK |
5841 | for (i = 0; i < reload_n_operands; i++) |
5842 | { | |
5843 | CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); | |
5844 | CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); | |
5845 | CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); | |
47c8cf91 | 5846 | CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]); |
546b63fb | 5847 | CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); |
47c8cf91 | 5848 | CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]); |
546b63fb | 5849 | } |
32131a9c | 5850 | |
9e3a9cf2 | 5851 | COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs); |
05d10675 | 5852 | |
67e61fe7 | 5853 | CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); |
32131a9c | 5854 | |
67e61fe7 BS |
5855 | for (i = 0; i < n_reloads; i++) |
5856 | /* If we have already decided to use a certain register, | |
5857 | don't use it in another way. */ | |
5858 | if (rld[i].reg_rtx) | |
5859 | mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum, | |
5860 | rld[i].when_needed, rld[i].mode); | |
5861 | } | |
32131a9c | 5862 | |
67e61fe7 BS |
5863 | /* Assign hard reg targets for the pseudo-registers we must reload |
5864 | into hard regs for this insn. | |
5865 | Also output the instructions to copy them in and out of the hard regs. | |
5866 | ||
5867 | For machines with register classes, we are responsible for | |
5868 | finding a reload reg in the proper class. */ | |
5869 | ||
5870 | static void | |
0c20a65f | 5871 | choose_reload_regs (struct insn_chain *chain) |
67e61fe7 BS |
5872 | { |
5873 | rtx insn = chain->insn; | |
b3694847 | 5874 | int i, j; |
770ae6cc | 5875 | unsigned int max_group_size = 1; |
67e61fe7 | 5876 | enum reg_class group_class = NO_REGS; |
f5d8c9f4 | 5877 | int pass, win, inheritance; |
67e61fe7 BS |
5878 | |
5879 | rtx save_reload_reg_rtx[MAX_RELOADS]; | |
32131a9c | 5880 | |
32131a9c RK |
5881 | /* In order to be certain of getting the registers we need, |
5882 | we must sort the reloads into order of increasing register class. | |
5883 | Then our grabbing of reload registers will parallel the process | |
a8fdc208 | 5884 | that provided the reload registers. |
32131a9c RK |
5885 | |
5886 | Also note whether any of the reloads wants a consecutive group of regs. | |
5887 | If so, record the maximum size of the group desired and what | |
5888 | register class contains all the groups needed by this insn. */ | |
5889 | ||
5890 | for (j = 0; j < n_reloads; j++) | |
5891 | { | |
5892 | reload_order[j] = j; | |
374d961c BS |
5893 | if (rld[j].reg_rtx != NULL_RTX) |
5894 | { | |
5895 | gcc_assert (REG_P (rld[j].reg_rtx) | |
5896 | && HARD_REGISTER_P (rld[j].reg_rtx)); | |
5897 | reload_spill_index[j] = REGNO (rld[j].reg_rtx); | |
5898 | } | |
5899 | else | |
5900 | reload_spill_index[j] = -1; | |
32131a9c | 5901 | |
8ec450a4 | 5902 | if (rld[j].nregs > 1) |
32131a9c | 5903 | { |
8ec450a4 | 5904 | max_group_size = MAX (rld[j].nregs, max_group_size); |
770ae6cc | 5905 | group_class |
48c54229 | 5906 | = reg_class_superunion[(int) rld[j].rclass][(int) group_class]; |
32131a9c RK |
5907 | } |
5908 | ||
eceef4c9 | 5909 | save_reload_reg_rtx[j] = rld[j].reg_rtx; |
32131a9c RK |
5910 | } |
5911 | ||
5912 | if (n_reloads > 1) | |
5913 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); | |
5914 | ||
58b1581b RS |
5915 | /* If -O, try first with inheritance, then turning it off. |
5916 | If not -O, don't do inheritance. | |
5917 | Using inheritance when not optimizing leads to paradoxes | |
5918 | with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves | |
5919 | because one side of the comparison might be inherited. */ | |
f5d8c9f4 | 5920 | win = 0; |
58b1581b | 5921 | for (inheritance = optimize > 0; inheritance >= 0; inheritance--) |
32131a9c | 5922 | { |
67e61fe7 BS |
5923 | choose_reload_regs_init (chain, save_reload_reg_rtx); |
5924 | ||
32131a9c RK |
5925 | /* Process the reloads in order of preference just found. |
5926 | Beyond this point, subregs can be found in reload_reg_rtx. | |
5927 | ||
770ae6cc RK |
5928 | This used to look for an existing reloaded home for all of the |
5929 | reloads, and only then perform any new reloads. But that could lose | |
5930 | if the reloads were done out of reg-class order because a later | |
5931 | reload with a looser constraint might have an old home in a register | |
5932 | needed by an earlier reload with a tighter constraint. | |
32131a9c RK |
5933 | |
5934 | To solve this, we make two passes over the reloads, in the order | |
5935 | described above. In the first pass we try to inherit a reload | |
5936 | from a previous insn. If there is a later reload that needs a | |
5937 | class that is a proper subset of the class being processed, we must | |
5938 | also allocate a spill register during the first pass. | |
5939 | ||
5940 | Then make a second pass over the reloads to allocate any reloads | |
5941 | that haven't been given registers yet. */ | |
5942 | ||
5943 | for (j = 0; j < n_reloads; j++) | |
5944 | { | |
b3694847 | 5945 | int r = reload_order[j]; |
8593b745 | 5946 | rtx search_equiv = NULL_RTX; |
32131a9c RK |
5947 | |
5948 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 BS |
5949 | if (rld[r].out == 0 && rld[r].in == 0 |
5950 | && ! rld[r].secondary_p) | |
32131a9c RK |
5951 | continue; |
5952 | ||
b29514ee | 5953 | /* If find_reloads chose to use reload_in or reload_out as a reload |
b080c137 RK |
5954 | register, we don't need to chose one. Otherwise, try even if it |
5955 | found one since we might save an insn if we find the value lying | |
b29514ee R |
5956 | around. |
5957 | Try also when reload_in is a pseudo without a hard reg. */ | |
eceef4c9 BS |
5958 | if (rld[r].in != 0 && rld[r].reg_rtx != 0 |
5959 | && (rtx_equal_p (rld[r].in, rld[r].reg_rtx) | |
5960 | || (rtx_equal_p (rld[r].out, rld[r].reg_rtx) | |
3c0cb5de | 5961 | && !MEM_P (rld[r].in) |
eceef4c9 | 5962 | && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER))) |
32131a9c RK |
5963 | continue; |
5964 | ||
5965 | #if 0 /* No longer needed for correct operation. | |
5966 | It might give better code, or might not; worth an experiment? */ | |
5967 | /* If this is an optional reload, we can't inherit from earlier insns | |
5968 | until we are sure that any non-optional reloads have been allocated. | |
5969 | The following code takes advantage of the fact that optional reloads | |
5970 | are at the end of reload_order. */ | |
eceef4c9 | 5971 | if (rld[r].optional != 0) |
32131a9c | 5972 | for (i = 0; i < j; i++) |
eceef4c9 BS |
5973 | if ((rld[reload_order[i]].out != 0 |
5974 | || rld[reload_order[i]].in != 0 | |
5975 | || rld[reload_order[i]].secondary_p) | |
5976 | && ! rld[reload_order[i]].optional | |
5977 | && rld[reload_order[i]].reg_rtx == 0) | |
f5d8c9f4 | 5978 | allocate_reload_reg (chain, reload_order[i], 0); |
32131a9c RK |
5979 | #endif |
5980 | ||
5981 | /* First see if this pseudo is already available as reloaded | |
5982 | for a previous insn. We cannot try to inherit for reloads | |
5983 | that are smaller than the maximum number of registers needed | |
5984 | for groups unless the register we would allocate cannot be used | |
5985 | for the groups. | |
5986 | ||
5987 | We could check here to see if this is a secondary reload for | |
5988 | an object that is already in a register of the desired class. | |
5989 | This would avoid the need for the secondary reload register. | |
5990 | But this is complex because we can't easily determine what | |
b080c137 RK |
5991 | objects might want to be loaded via this reload. So let a |
5992 | register be allocated here. In `emit_reload_insns' we suppress | |
5993 | one of the loads in the case described above. */ | |
32131a9c RK |
5994 | |
5995 | if (inheritance) | |
5996 | { | |
ddef6bc7 | 5997 | int byte = 0; |
b3694847 | 5998 | int regno = -1; |
6a651371 | 5999 | enum machine_mode mode = VOIDmode; |
32131a9c | 6000 | |
eceef4c9 | 6001 | if (rld[r].in == 0) |
32131a9c | 6002 | ; |
f8cfc6aa | 6003 | else if (REG_P (rld[r].in)) |
db660765 | 6004 | { |
eceef4c9 BS |
6005 | regno = REGNO (rld[r].in); |
6006 | mode = GET_MODE (rld[r].in); | |
db660765 | 6007 | } |
f8cfc6aa | 6008 | else if (REG_P (rld[r].in_reg)) |
db660765 | 6009 | { |
eceef4c9 BS |
6010 | regno = REGNO (rld[r].in_reg); |
6011 | mode = GET_MODE (rld[r].in_reg); | |
db660765 | 6012 | } |
eceef4c9 | 6013 | else if (GET_CODE (rld[r].in_reg) == SUBREG |
f8cfc6aa | 6014 | && REG_P (SUBREG_REG (rld[r].in_reg))) |
b60a8416 | 6015 | { |
eceef4c9 | 6016 | regno = REGNO (SUBREG_REG (rld[r].in_reg)); |
cb2afeb3 | 6017 | if (regno < FIRST_PSEUDO_REGISTER) |
ddef6bc7 | 6018 | regno = subreg_regno (rld[r].in_reg); |
15447fae RIL |
6019 | else |
6020 | byte = SUBREG_BYTE (rld[r].in_reg); | |
eceef4c9 | 6021 | mode = GET_MODE (rld[r].in_reg); |
cb2afeb3 R |
6022 | } |
6023 | #ifdef AUTO_INC_DEC | |
67f07489 | 6024 | else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC |
f8cfc6aa | 6025 | && REG_P (XEXP (rld[r].in_reg, 0))) |
cb2afeb3 | 6026 | { |
eceef4c9 BS |
6027 | regno = REGNO (XEXP (rld[r].in_reg, 0)); |
6028 | mode = GET_MODE (XEXP (rld[r].in_reg, 0)); | |
6029 | rld[r].out = rld[r].in; | |
b60a8416 | 6030 | } |
cb2afeb3 | 6031 | #endif |
32131a9c RK |
6032 | #if 0 |
6033 | /* This won't work, since REGNO can be a pseudo reg number. | |
6034 | Also, it takes much more hair to keep track of all the things | |
6035 | that can invalidate an inherited reload of part of a pseudoreg. */ | |
eceef4c9 | 6036 | else if (GET_CODE (rld[r].in) == SUBREG |
f8cfc6aa | 6037 | && REG_P (SUBREG_REG (rld[r].in))) |
ddef6bc7 | 6038 | regno = subreg_regno (rld[r].in); |
32131a9c RK |
6039 | #endif |
6040 | ||
21f14ff9 DD |
6041 | if (regno >= 0 |
6042 | && reg_last_reload_reg[regno] != 0 | |
6043 | #ifdef CANNOT_CHANGE_MODE_CLASS | |
6044 | /* Verify that the register it's in can be used in | |
6045 | mode MODE. */ | |
6046 | && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]), | |
6047 | GET_MODE (reg_last_reload_reg[regno]), | |
6048 | mode) | |
6049 | #endif | |
6050 | ) | |
32131a9c | 6051 | { |
48c54229 | 6052 | enum reg_class rclass = rld[r].rclass, last_class; |
cb2afeb3 | 6053 | rtx last_reg = reg_last_reload_reg[regno]; |
02188693 | 6054 | enum machine_mode need_mode; |
05d10675 | 6055 | |
ddef6bc7 JJ |
6056 | i = REGNO (last_reg); |
6057 | i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode); | |
cb2afeb3 | 6058 | last_class = REGNO_REG_CLASS (i); |
02188693 | 6059 | |
ddef6bc7 | 6060 | if (byte == 0) |
ce701d1b BS |
6061 | need_mode = mode; |
6062 | else | |
6063 | need_mode | |
7db7ed3c VM |
6064 | = smallest_mode_for_size |
6065 | (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT, | |
6066 | GET_MODE_CLASS (mode) == MODE_PARTIAL_INT | |
6067 | ? MODE_INT : GET_MODE_CLASS (mode)); | |
02188693 | 6068 | |
1de80b0e | 6069 | if ((GET_MODE_SIZE (GET_MODE (last_reg)) |
02188693 | 6070 | >= GET_MODE_SIZE (need_mode)) |
cb2afeb3 | 6071 | && reg_reloaded_contents[i] == regno |
e6e52be0 | 6072 | && TEST_HARD_REG_BIT (reg_reloaded_valid, i) |
8ec450a4 | 6073 | && HARD_REGNO_MODE_OK (i, rld[r].mode) |
55d796da | 6074 | && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i) |
cb2afeb3 R |
6075 | /* Even if we can't use this register as a reload |
6076 | register, we might use it for reload_override_in, | |
6077 | if copying it to the desired class is cheap | |
6078 | enough. */ | |
55d796da KG |
6079 | || ((REGISTER_MOVE_COST (mode, last_class, rclass) |
6080 | < MEMORY_MOVE_COST (mode, rclass, 1)) | |
6081 | && (secondary_reload_class (1, rclass, mode, | |
8a99f6f9 | 6082 | last_reg) |
cb2afeb3 | 6083 | == NO_REGS) |
cb2afeb3 | 6084 | #ifdef SECONDARY_MEMORY_NEEDED |
55d796da | 6085 | && ! SECONDARY_MEMORY_NEEDED (last_class, rclass, |
cb2afeb3 R |
6086 | mode) |
6087 | #endif | |
6088 | )) | |
6089 | ||
8ec450a4 | 6090 | && (rld[r].nregs == max_group_size |
32131a9c | 6091 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], |
e6e52be0 | 6092 | i)) |
c02cad8f BS |
6093 | && free_for_value_p (i, rld[r].mode, rld[r].opnum, |
6094 | rld[r].when_needed, rld[r].in, | |
6095 | const0_rtx, r, 1)) | |
32131a9c RK |
6096 | { |
6097 | /* If a group is needed, verify that all the subsequent | |
0f41302f | 6098 | registers still have their values intact. */ |
66fd46b6 | 6099 | int nr = hard_regno_nregs[i][rld[r].mode]; |
32131a9c RK |
6100 | int k; |
6101 | ||
6102 | for (k = 1; k < nr; k++) | |
e6e52be0 R |
6103 | if (reg_reloaded_contents[i + k] != regno |
6104 | || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k)) | |
32131a9c RK |
6105 | break; |
6106 | ||
6107 | if (k == nr) | |
6108 | { | |
c74fa651 | 6109 | int i1; |
eb4d554e | 6110 | int bad_for_class; |
c74fa651 | 6111 | |
cb2afeb3 R |
6112 | last_reg = (GET_MODE (last_reg) == mode |
6113 | ? last_reg : gen_rtx_REG (mode, i)); | |
6114 | ||
eb4d554e GK |
6115 | bad_for_class = 0; |
6116 | for (k = 0; k < nr; k++) | |
48c54229 | 6117 | bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass], |
eb4d554e GK |
6118 | i+k); |
6119 | ||
c74fa651 RS |
6120 | /* We found a register that contains the |
6121 | value we need. If this register is the | |
6122 | same as an `earlyclobber' operand of the | |
6123 | current insn, just mark it as a place to | |
6124 | reload from since we can't use it as the | |
6125 | reload register itself. */ | |
6126 | ||
6127 | for (i1 = 0; i1 < n_earlyclobbers; i1++) | |
6128 | if (reg_overlap_mentioned_for_reload_p | |
6129 | (reg_last_reload_reg[regno], | |
6130 | reload_earlyclobbers[i1])) | |
6131 | break; | |
6132 | ||
8908158d | 6133 | if (i1 != n_earlyclobbers |
c02cad8f BS |
6134 | || ! (free_for_value_p (i, rld[r].mode, |
6135 | rld[r].opnum, | |
6136 | rld[r].when_needed, rld[r].in, | |
6137 | rld[r].out, r, 1)) | |
e6e52be0 | 6138 | /* Don't use it if we'd clobber a pseudo reg. */ |
f1db3576 | 6139 | || (TEST_HARD_REG_BIT (reg_used_in_insn, i) |
eceef4c9 | 6140 | && rld[r].out |
e6e52be0 | 6141 | && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i)) |
0c7f2259 | 6142 | /* Don't clobber the frame pointer. */ |
1d7254c5 | 6143 | || (i == HARD_FRAME_POINTER_REGNUM |
2f460a0a | 6144 | && frame_pointer_needed |
1d7254c5 | 6145 | && rld[r].out) |
8908158d RS |
6146 | /* Don't really use the inherited spill reg |
6147 | if we need it wider than we've got it. */ | |
8ec450a4 | 6148 | || (GET_MODE_SIZE (rld[r].mode) |
b29514ee | 6149 | > GET_MODE_SIZE (mode)) |
eb4d554e | 6150 | || bad_for_class |
cb2afeb3 | 6151 | |
b29514ee R |
6152 | /* If find_reloads chose reload_out as reload |
6153 | register, stay with it - that leaves the | |
6154 | inherited register for subsequent reloads. */ | |
eceef4c9 | 6155 | || (rld[r].out && rld[r].reg_rtx |
67e61fe7 | 6156 | && rtx_equal_p (rld[r].out, rld[r].reg_rtx))) |
cb2afeb3 | 6157 | { |
4c3a2649 BS |
6158 | if (! rld[r].optional) |
6159 | { | |
6160 | reload_override_in[r] = last_reg; | |
6161 | reload_inheritance_insn[r] | |
6162 | = reg_reloaded_insn[i]; | |
6163 | } | |
cb2afeb3 | 6164 | } |
c74fa651 RS |
6165 | else |
6166 | { | |
54c40e68 | 6167 | int k; |
c74fa651 RS |
6168 | /* We can use this as a reload reg. */ |
6169 | /* Mark the register as in use for this part of | |
6170 | the insn. */ | |
e6e52be0 | 6171 | mark_reload_reg_in_use (i, |
eceef4c9 BS |
6172 | rld[r].opnum, |
6173 | rld[r].when_needed, | |
8ec450a4 | 6174 | rld[r].mode); |
eceef4c9 | 6175 | rld[r].reg_rtx = last_reg; |
c74fa651 RS |
6176 | reload_inherited[r] = 1; |
6177 | reload_inheritance_insn[r] | |
6178 | = reg_reloaded_insn[i]; | |
6179 | reload_spill_index[r] = i; | |
54c40e68 RS |
6180 | for (k = 0; k < nr; k++) |
6181 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, | |
e6e52be0 | 6182 | i + k); |
c74fa651 | 6183 | } |
32131a9c RK |
6184 | } |
6185 | } | |
6186 | } | |
6187 | } | |
6188 | ||
6189 | /* Here's another way to see if the value is already lying around. */ | |
6190 | if (inheritance | |
eceef4c9 | 6191 | && rld[r].in != 0 |
32131a9c | 6192 | && ! reload_inherited[r] |
eceef4c9 BS |
6193 | && rld[r].out == 0 |
6194 | && (CONSTANT_P (rld[r].in) | |
6195 | || GET_CODE (rld[r].in) == PLUS | |
f8cfc6aa | 6196 | || REG_P (rld[r].in) |
3c0cb5de | 6197 | || MEM_P (rld[r].in)) |
8ec450a4 | 6198 | && (rld[r].nregs == max_group_size |
48c54229 | 6199 | || ! reg_classes_intersect_p (rld[r].rclass, group_class))) |
eceef4c9 | 6200 | search_equiv = rld[r].in; |
8593b745 R |
6201 | /* If this is an output reload from a simple move insn, look |
6202 | if an equivalence for the input is available. */ | |
eceef4c9 | 6203 | else if (inheritance && rld[r].in == 0 && rld[r].out != 0) |
8593b745 R |
6204 | { |
6205 | rtx set = single_set (insn); | |
6206 | ||
6207 | if (set | |
eceef4c9 | 6208 | && rtx_equal_p (rld[r].out, SET_DEST (set)) |
8593b745 R |
6209 | && CONSTANT_P (SET_SRC (set))) |
6210 | search_equiv = SET_SRC (set); | |
6211 | } | |
6212 | ||
6213 | if (search_equiv) | |
32131a9c | 6214 | { |
b3694847 | 6215 | rtx equiv |
48c54229 | 6216 | = find_equiv_reg (search_equiv, insn, rld[r].rclass, |
9714cf43 | 6217 | -1, NULL, 0, rld[r].mode); |
f428f252 | 6218 | int regno = 0; |
32131a9c RK |
6219 | |
6220 | if (equiv != 0) | |
6221 | { | |
f8cfc6aa | 6222 | if (REG_P (equiv)) |
32131a9c | 6223 | regno = REGNO (equiv); |
41374e13 | 6224 | else |
32131a9c | 6225 | { |
f8a9e02b RK |
6226 | /* This must be a SUBREG of a hard register. |
6227 | Make a new REG since this might be used in an | |
6228 | address and not all machines support SUBREGs | |
6229 | there. */ | |
41374e13 | 6230 | gcc_assert (GET_CODE (equiv) == SUBREG); |
ddef6bc7 | 6231 | regno = subreg_regno (equiv); |
8ec450a4 | 6232 | equiv = gen_rtx_REG (rld[r].mode, regno); |
9c0a30c3 EB |
6233 | /* If we choose EQUIV as the reload register, but the |
6234 | loop below decides to cancel the inheritance, we'll | |
6235 | end up reloading EQUIV in rld[r].mode, not the mode | |
6236 | it had originally. That isn't safe when EQUIV isn't | |
6237 | available as a spill register since its value might | |
6238 | still be live at this point. */ | |
6239 | for (i = regno; i < regno + (int) rld[r].nregs; i++) | |
6240 | if (TEST_HARD_REG_BIT (reload_reg_unavailable, i)) | |
6241 | equiv = 0; | |
32131a9c | 6242 | } |
32131a9c RK |
6243 | } |
6244 | ||
6245 | /* If we found a spill reg, reject it unless it is free | |
6246 | and of the desired class. */ | |
f58d8c95 JW |
6247 | if (equiv != 0) |
6248 | { | |
6249 | int regs_used = 0; | |
6250 | int bad_for_class = 0; | |
6251 | int max_regno = regno + rld[r].nregs; | |
6252 | ||
6253 | for (i = regno; i < max_regno; i++) | |
6254 | { | |
6255 | regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
6256 | i); | |
48c54229 | 6257 | bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass], |
f58d8c95 JW |
6258 | i); |
6259 | } | |
6260 | ||
6261 | if ((regs_used | |
c02cad8f BS |
6262 | && ! free_for_value_p (regno, rld[r].mode, |
6263 | rld[r].opnum, rld[r].when_needed, | |
6264 | rld[r].in, rld[r].out, r, 1)) | |
f58d8c95 JW |
6265 | || bad_for_class) |
6266 | equiv = 0; | |
6267 | } | |
32131a9c | 6268 | |
8ec450a4 | 6269 | if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode)) |
32131a9c RK |
6270 | equiv = 0; |
6271 | ||
6272 | /* We found a register that contains the value we need. | |
6273 | If this register is the same as an `earlyclobber' operand | |
6274 | of the current insn, just mark it as a place to reload from | |
6275 | since we can't use it as the reload register itself. */ | |
6276 | ||
6277 | if (equiv != 0) | |
6278 | for (i = 0; i < n_earlyclobbers; i++) | |
bfa30b22 RK |
6279 | if (reg_overlap_mentioned_for_reload_p (equiv, |
6280 | reload_earlyclobbers[i])) | |
32131a9c | 6281 | { |
4c3a2649 BS |
6282 | if (! rld[r].optional) |
6283 | reload_override_in[r] = equiv; | |
32131a9c RK |
6284 | equiv = 0; |
6285 | break; | |
6286 | } | |
6287 | ||
3c785e47 R |
6288 | /* If the equiv register we have found is explicitly clobbered |
6289 | in the current insn, it depends on the reload type if we | |
6290 | can use it, use it for reload_override_in, or not at all. | |
6291 | In particular, we then can't use EQUIV for a | |
6292 | RELOAD_FOR_OUTPUT_ADDRESS reload. */ | |
32131a9c | 6293 | |
9532e31f | 6294 | if (equiv != 0) |
174fa2c4 | 6295 | { |
d0236c3b | 6296 | if (regno_clobbered_p (regno, insn, rld[r].mode, 2)) |
9532e31f BS |
6297 | switch (rld[r].when_needed) |
6298 | { | |
6299 | case RELOAD_FOR_OTHER_ADDRESS: | |
6300 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6301 | case RELOAD_FOR_INPUT_ADDRESS: | |
6302 | case RELOAD_FOR_OPADDR_ADDR: | |
6303 | break; | |
6304 | case RELOAD_OTHER: | |
6305 | case RELOAD_FOR_INPUT: | |
6306 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6307 | if (! rld[r].optional) | |
6308 | reload_override_in[r] = equiv; | |
6309 | /* Fall through. */ | |
6310 | default: | |
6311 | equiv = 0; | |
6312 | break; | |
6313 | } | |
6314 | else if (regno_clobbered_p (regno, insn, rld[r].mode, 1)) | |
6315 | switch (rld[r].when_needed) | |
6316 | { | |
6317 | case RELOAD_FOR_OTHER_ADDRESS: | |
6318 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6319 | case RELOAD_FOR_INPUT_ADDRESS: | |
6320 | case RELOAD_FOR_OPADDR_ADDR: | |
6321 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6322 | case RELOAD_FOR_INPUT: | |
6323 | break; | |
6324 | case RELOAD_OTHER: | |
6325 | if (! rld[r].optional) | |
6326 | reload_override_in[r] = equiv; | |
6327 | /* Fall through. */ | |
6328 | default: | |
6329 | equiv = 0; | |
6330 | break; | |
6331 | } | |
32131a9c RK |
6332 | } |
6333 | ||
6334 | /* If we found an equivalent reg, say no code need be generated | |
6335 | to load it, and use it as our reload reg. */ | |
a6a2274a KH |
6336 | if (equiv != 0 |
6337 | && (regno != HARD_FRAME_POINTER_REGNUM | |
2f460a0a | 6338 | || !frame_pointer_needed)) |
32131a9c | 6339 | { |
66fd46b6 | 6340 | int nr = hard_regno_nregs[regno][rld[r].mode]; |
100338df | 6341 | int k; |
eceef4c9 | 6342 | rld[r].reg_rtx = equiv; |
a2a6f3cf | 6343 | reload_spill_index[r] = regno; |
32131a9c | 6344 | reload_inherited[r] = 1; |
100338df | 6345 | |
91d7e7ac R |
6346 | /* If reg_reloaded_valid is not set for this register, |
6347 | there might be a stale spill_reg_store lying around. | |
6348 | We must clear it, since otherwise emit_reload_insns | |
6349 | might delete the store. */ | |
6350 | if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno)) | |
6351 | spill_reg_store[regno] = NULL_RTX; | |
100338df JL |
6352 | /* If any of the hard registers in EQUIV are spill |
6353 | registers, mark them as in use for this insn. */ | |
6354 | for (k = 0; k < nr; k++) | |
be7ae2a4 | 6355 | { |
100338df JL |
6356 | i = spill_reg_order[regno + k]; |
6357 | if (i >= 0) | |
6358 | { | |
eceef4c9 BS |
6359 | mark_reload_reg_in_use (regno, rld[r].opnum, |
6360 | rld[r].when_needed, | |
8ec450a4 | 6361 | rld[r].mode); |
100338df JL |
6362 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, |
6363 | regno + k); | |
6364 | } | |
be7ae2a4 | 6365 | } |
32131a9c RK |
6366 | } |
6367 | } | |
6368 | ||
6369 | /* If we found a register to use already, or if this is an optional | |
6370 | reload, we are done. */ | |
eceef4c9 | 6371 | if (rld[r].reg_rtx != 0 || rld[r].optional != 0) |
32131a9c RK |
6372 | continue; |
6373 | ||
1d7254c5 KH |
6374 | #if 0 |
6375 | /* No longer needed for correct operation. Might or might | |
6376 | not give better code on the average. Want to experiment? */ | |
32131a9c RK |
6377 | |
6378 | /* See if there is a later reload that has a class different from our | |
6379 | class that intersects our class or that requires less register | |
6380 | than our reload. If so, we must allocate a register to this | |
6381 | reload now, since that reload might inherit a previous reload | |
6382 | and take the only available register in our class. Don't do this | |
6383 | for optional reloads since they will force all previous reloads | |
6384 | to be allocated. Also don't do this for reloads that have been | |
6385 | turned off. */ | |
6386 | ||
6387 | for (i = j + 1; i < n_reloads; i++) | |
6388 | { | |
6389 | int s = reload_order[i]; | |
6390 | ||
eceef4c9 BS |
6391 | if ((rld[s].in == 0 && rld[s].out == 0 |
6392 | && ! rld[s].secondary_p) | |
6393 | || rld[s].optional) | |
32131a9c RK |
6394 | continue; |
6395 | ||
48c54229 KG |
6396 | if ((rld[s].rclass != rld[r].rclass |
6397 | && reg_classes_intersect_p (rld[r].rclass, | |
6398 | rld[s].rclass)) | |
8ec450a4 | 6399 | || rld[s].nregs < rld[r].nregs) |
05d10675 | 6400 | break; |
32131a9c RK |
6401 | } |
6402 | ||
6403 | if (i == n_reloads) | |
6404 | continue; | |
6405 | ||
f5d8c9f4 | 6406 | allocate_reload_reg (chain, r, j == n_reloads - 1); |
32131a9c RK |
6407 | #endif |
6408 | } | |
6409 | ||
6410 | /* Now allocate reload registers for anything non-optional that | |
6411 | didn't get one yet. */ | |
6412 | for (j = 0; j < n_reloads; j++) | |
6413 | { | |
b3694847 | 6414 | int r = reload_order[j]; |
32131a9c RK |
6415 | |
6416 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 | 6417 | if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p) |
32131a9c RK |
6418 | continue; |
6419 | ||
6420 | /* Skip reloads that already have a register allocated or are | |
0f41302f | 6421 | optional. */ |
eceef4c9 | 6422 | if (rld[r].reg_rtx != 0 || rld[r].optional) |
32131a9c RK |
6423 | continue; |
6424 | ||
f5d8c9f4 | 6425 | if (! allocate_reload_reg (chain, r, j == n_reloads - 1)) |
32131a9c RK |
6426 | break; |
6427 | } | |
6428 | ||
6429 | /* If that loop got all the way, we have won. */ | |
6430 | if (j == n_reloads) | |
f5d8c9f4 BS |
6431 | { |
6432 | win = 1; | |
6433 | break; | |
6434 | } | |
32131a9c | 6435 | |
32131a9c | 6436 | /* Loop around and try without any inheritance. */ |
32131a9c RK |
6437 | } |
6438 | ||
f5d8c9f4 BS |
6439 | if (! win) |
6440 | { | |
6441 | /* First undo everything done by the failed attempt | |
6442 | to allocate with inheritance. */ | |
6443 | choose_reload_regs_init (chain, save_reload_reg_rtx); | |
6444 | ||
6445 | /* Some sanity tests to verify that the reloads found in the first | |
6446 | pass are identical to the ones we have now. */ | |
41374e13 | 6447 | gcc_assert (chain->n_reloads == n_reloads); |
f5d8c9f4 BS |
6448 | |
6449 | for (i = 0; i < n_reloads; i++) | |
6450 | { | |
6451 | if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0) | |
6452 | continue; | |
41374e13 | 6453 | gcc_assert (chain->rld[i].when_needed == rld[i].when_needed); |
f5d8c9f4 BS |
6454 | for (j = 0; j < n_spills; j++) |
6455 | if (spill_regs[j] == chain->rld[i].regno) | |
6456 | if (! set_reload_reg (j, i)) | |
6457 | failed_reload (chain->insn, i); | |
6458 | } | |
6459 | } | |
6460 | ||
32131a9c RK |
6461 | /* If we thought we could inherit a reload, because it seemed that |
6462 | nothing else wanted the same reload register earlier in the insn, | |
cb2afeb3 R |
6463 | verify that assumption, now that all reloads have been assigned. |
6464 | Likewise for reloads where reload_override_in has been set. */ | |
32131a9c | 6465 | |
cb2afeb3 R |
6466 | /* If doing expensive optimizations, do one preliminary pass that doesn't |
6467 | cancel any inheritance, but removes reloads that have been needed only | |
6468 | for reloads that we know can be inherited. */ | |
6469 | for (pass = flag_expensive_optimizations; pass >= 0; pass--) | |
32131a9c | 6470 | { |
cb2afeb3 | 6471 | for (j = 0; j < n_reloads; j++) |
029b38ff | 6472 | { |
b3694847 | 6473 | int r = reload_order[j]; |
cb2afeb3 | 6474 | rtx check_reg; |
eceef4c9 BS |
6475 | if (reload_inherited[r] && rld[r].reg_rtx) |
6476 | check_reg = rld[r].reg_rtx; | |
cb2afeb3 | 6477 | else if (reload_override_in[r] |
f8cfc6aa | 6478 | && (REG_P (reload_override_in[r]) |
05d10675 | 6479 | || GET_CODE (reload_override_in[r]) == SUBREG)) |
cb2afeb3 R |
6480 | check_reg = reload_override_in[r]; |
6481 | else | |
6482 | continue; | |
c02cad8f BS |
6483 | if (! free_for_value_p (true_regnum (check_reg), rld[r].mode, |
6484 | rld[r].opnum, rld[r].when_needed, rld[r].in, | |
6485 | (reload_inherited[r] | |
6486 | ? rld[r].out : const0_rtx), | |
6487 | r, 1)) | |
029b38ff | 6488 | { |
cb2afeb3 R |
6489 | if (pass) |
6490 | continue; | |
6491 | reload_inherited[r] = 0; | |
6492 | reload_override_in[r] = 0; | |
029b38ff | 6493 | } |
cb2afeb3 R |
6494 | /* If we can inherit a RELOAD_FOR_INPUT, or can use a |
6495 | reload_override_in, then we do not need its related | |
6496 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads; | |
6497 | likewise for other reload types. | |
6498 | We handle this by removing a reload when its only replacement | |
6499 | is mentioned in reload_in of the reload we are going to inherit. | |
6500 | A special case are auto_inc expressions; even if the input is | |
6501 | inherited, we still need the address for the output. We can | |
fe92fe26 | 6502 | recognize them because they have RELOAD_OUT set to RELOAD_IN. |
eaec9b3d | 6503 | If we succeeded removing some reload and we are doing a preliminary |
cb2afeb3 R |
6504 | pass just to remove such reloads, make another pass, since the |
6505 | removal of one reload might allow us to inherit another one. */ | |
eceef4c9 BS |
6506 | else if (rld[r].in |
6507 | && rld[r].out != rld[r].in | |
6508 | && remove_address_replacements (rld[r].in) && pass) | |
cb2afeb3 | 6509 | pass = 2; |
32131a9c RK |
6510 | } |
6511 | } | |
6512 | ||
6513 | /* Now that reload_override_in is known valid, | |
6514 | actually override reload_in. */ | |
6515 | for (j = 0; j < n_reloads; j++) | |
6516 | if (reload_override_in[j]) | |
eceef4c9 | 6517 | rld[j].in = reload_override_in[j]; |
32131a9c | 6518 | |
272d0bee | 6519 | /* If this reload won't be done because it has been canceled or is |
32131a9c RK |
6520 | optional and not inherited, clear reload_reg_rtx so other |
6521 | routines (such as subst_reloads) don't get confused. */ | |
6522 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
6523 | if (rld[j].reg_rtx != 0 |
6524 | && ((rld[j].optional && ! reload_inherited[j]) | |
6525 | || (rld[j].in == 0 && rld[j].out == 0 | |
6526 | && ! rld[j].secondary_p))) | |
be7ae2a4 | 6527 | { |
eceef4c9 | 6528 | int regno = true_regnum (rld[j].reg_rtx); |
be7ae2a4 RK |
6529 | |
6530 | if (spill_reg_order[regno] >= 0) | |
eceef4c9 | 6531 | clear_reload_reg_in_use (regno, rld[j].opnum, |
8ec450a4 | 6532 | rld[j].when_needed, rld[j].mode); |
eceef4c9 | 6533 | rld[j].reg_rtx = 0; |
c0029be5 | 6534 | reload_spill_index[j] = -1; |
be7ae2a4 | 6535 | } |
32131a9c RK |
6536 | |
6537 | /* Record which pseudos and which spill regs have output reloads. */ | |
6538 | for (j = 0; j < n_reloads; j++) | |
6539 | { | |
b3694847 | 6540 | int r = reload_order[j]; |
32131a9c RK |
6541 | |
6542 | i = reload_spill_index[r]; | |
6543 | ||
e6e52be0 | 6544 | /* I is nonneg if this reload uses a register. |
eceef4c9 | 6545 | If rld[r].reg_rtx is 0, this is an optional reload |
32131a9c | 6546 | that we opted to ignore. */ |
f8cfc6aa | 6547 | if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg) |
eceef4c9 | 6548 | && rld[r].reg_rtx != 0) |
32131a9c | 6549 | { |
b3694847 | 6550 | int nregno = REGNO (rld[r].out_reg); |
372e033b RS |
6551 | int nr = 1; |
6552 | ||
6553 | if (nregno < FIRST_PSEUDO_REGISTER) | |
66fd46b6 | 6554 | nr = hard_regno_nregs[nregno][rld[r].mode]; |
32131a9c RK |
6555 | |
6556 | while (--nr >= 0) | |
2c61f5f1 JH |
6557 | SET_REGNO_REG_SET (®_has_output_reload, |
6558 | nregno + nr); | |
372e033b RS |
6559 | |
6560 | if (i >= 0) | |
32131a9c | 6561 | { |
66fd46b6 | 6562 | nr = hard_regno_nregs[i][rld[r].mode]; |
372e033b | 6563 | while (--nr >= 0) |
e6e52be0 | 6564 | SET_HARD_REG_BIT (reg_is_output_reload, i + nr); |
32131a9c RK |
6565 | } |
6566 | ||
41374e13 NS |
6567 | gcc_assert (rld[r].when_needed == RELOAD_OTHER |
6568 | || rld[r].when_needed == RELOAD_FOR_OUTPUT | |
6569 | || rld[r].when_needed == RELOAD_FOR_INSN); | |
32131a9c RK |
6570 | } |
6571 | } | |
6572 | } | |
cb2afeb3 R |
6573 | |
6574 | /* Deallocate the reload register for reload R. This is called from | |
6575 | remove_address_replacements. */ | |
1d813780 | 6576 | |
cb2afeb3 | 6577 | void |
0c20a65f | 6578 | deallocate_reload_reg (int r) |
cb2afeb3 R |
6579 | { |
6580 | int regno; | |
6581 | ||
eceef4c9 | 6582 | if (! rld[r].reg_rtx) |
cb2afeb3 | 6583 | return; |
eceef4c9 BS |
6584 | regno = true_regnum (rld[r].reg_rtx); |
6585 | rld[r].reg_rtx = 0; | |
cb2afeb3 | 6586 | if (spill_reg_order[regno] >= 0) |
eceef4c9 | 6587 | clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed, |
8ec450a4 | 6588 | rld[r].mode); |
cb2afeb3 R |
6589 | reload_spill_index[r] = -1; |
6590 | } | |
32131a9c | 6591 | \f |
40f03658 | 6592 | /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two |
546b63fb RK |
6593 | reloads of the same item for fear that we might not have enough reload |
6594 | registers. However, normally they will get the same reload register | |
05d10675 | 6595 | and hence actually need not be loaded twice. |
546b63fb RK |
6596 | |
6597 | Here we check for the most common case of this phenomenon: when we have | |
6598 | a number of reloads for the same object, each of which were allocated | |
6599 | the same reload_reg_rtx, that reload_reg_rtx is not used for any other | |
6600 | reload, and is not modified in the insn itself. If we find such, | |
6601 | merge all the reloads and set the resulting reload to RELOAD_OTHER. | |
6602 | This will not increase the number of spill registers needed and will | |
6603 | prevent redundant code. */ | |
6604 | ||
546b63fb | 6605 | static void |
0c20a65f | 6606 | merge_assigned_reloads (rtx insn) |
546b63fb RK |
6607 | { |
6608 | int i, j; | |
6609 | ||
6610 | /* Scan all the reloads looking for ones that only load values and | |
6611 | are not already RELOAD_OTHER and ones whose reload_reg_rtx are | |
6612 | assigned and not modified by INSN. */ | |
6613 | ||
6614 | for (i = 0; i < n_reloads; i++) | |
6615 | { | |
d668e863 R |
6616 | int conflicting_input = 0; |
6617 | int max_input_address_opnum = -1; | |
6618 | int min_conflicting_input_opnum = MAX_RECOG_OPERANDS; | |
6619 | ||
eceef4c9 BS |
6620 | if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER |
6621 | || rld[i].out != 0 || rld[i].reg_rtx == 0 | |
6622 | || reg_set_p (rld[i].reg_rtx, insn)) | |
546b63fb RK |
6623 | continue; |
6624 | ||
6625 | /* Look at all other reloads. Ensure that the only use of this | |
6626 | reload_reg_rtx is in a reload that just loads the same value | |
6627 | as we do. Note that any secondary reloads must be of the identical | |
6628 | class since the values, modes, and result registers are the | |
6629 | same, so we need not do anything with any secondary reloads. */ | |
6630 | ||
6631 | for (j = 0; j < n_reloads; j++) | |
6632 | { | |
eceef4c9 BS |
6633 | if (i == j || rld[j].reg_rtx == 0 |
6634 | || ! reg_overlap_mentioned_p (rld[j].reg_rtx, | |
6635 | rld[i].reg_rtx)) | |
546b63fb RK |
6636 | continue; |
6637 | ||
eceef4c9 BS |
6638 | if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6639 | && rld[j].opnum > max_input_address_opnum) | |
6640 | max_input_address_opnum = rld[j].opnum; | |
d668e863 | 6641 | |
546b63fb | 6642 | /* If the reload regs aren't exactly the same (e.g, different modes) |
d668e863 R |
6643 | or if the values are different, we can't merge this reload. |
6644 | But if it is an input reload, we might still merge | |
6645 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */ | |
546b63fb | 6646 | |
eceef4c9 BS |
6647 | if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) |
6648 | || rld[j].out != 0 || rld[j].in == 0 | |
6649 | || ! rtx_equal_p (rld[i].in, rld[j].in)) | |
d668e863 | 6650 | { |
eceef4c9 BS |
6651 | if (rld[j].when_needed != RELOAD_FOR_INPUT |
6652 | || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS | |
6653 | || rld[i].opnum > rld[j].opnum) | |
6654 | && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS)) | |
d668e863 R |
6655 | break; |
6656 | conflicting_input = 1; | |
eceef4c9 BS |
6657 | if (min_conflicting_input_opnum > rld[j].opnum) |
6658 | min_conflicting_input_opnum = rld[j].opnum; | |
d668e863 | 6659 | } |
546b63fb RK |
6660 | } |
6661 | ||
6662 | /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if | |
6663 | we, in fact, found any matching reloads. */ | |
6664 | ||
d668e863 R |
6665 | if (j == n_reloads |
6666 | && max_input_address_opnum <= min_conflicting_input_opnum) | |
546b63fb | 6667 | { |
3f27846b DJ |
6668 | gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT); |
6669 | ||
546b63fb | 6670 | for (j = 0; j < n_reloads; j++) |
eceef4c9 BS |
6671 | if (i != j && rld[j].reg_rtx != 0 |
6672 | && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) | |
d668e863 | 6673 | && (! conflicting_input |
eceef4c9 BS |
6674 | || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6675 | || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS)) | |
546b63fb | 6676 | { |
eceef4c9 BS |
6677 | rld[i].when_needed = RELOAD_OTHER; |
6678 | rld[j].in = 0; | |
efdb3590 | 6679 | reload_spill_index[j] = -1; |
546b63fb RK |
6680 | transfer_replacements (i, j); |
6681 | } | |
6682 | ||
b883ab57 HMC |
6683 | /* If this is now RELOAD_OTHER, look for any reloads that |
6684 | load parts of this operand and set them to | |
6685 | RELOAD_FOR_OTHER_ADDRESS if they were for inputs, | |
6686 | RELOAD_OTHER for outputs. Note that this test is | |
6687 | equivalent to looking for reloads for this operand | |
6688 | number. | |
6689 | ||
6690 | We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; | |
6691 | it may share registers with a RELOAD_FOR_INPUT, so we can | |
6692 | not change it to RELOAD_FOR_OTHER_ADDRESS. We should | |
6693 | never need to, since we do not modify RELOAD_FOR_OUTPUT. | |
6694 | ||
6695 | It is possible that the RELOAD_FOR_OPERAND_ADDRESS | |
6696 | instruction is assigned the same register as the earlier | |
6697 | RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two | |
6698 | instructions will cause the RELOAD_FOR_OTHER_ADDRESS | |
6699 | instruction to be deleted later on. */ | |
546b63fb | 6700 | |
eceef4c9 | 6701 | if (rld[i].when_needed == RELOAD_OTHER) |
546b63fb | 6702 | for (j = 0; j < n_reloads; j++) |
eceef4c9 | 6703 | if (rld[j].in != 0 |
91667711 | 6704 | && rld[j].when_needed != RELOAD_OTHER |
dec0798e | 6705 | && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS |
3f27846b | 6706 | && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS |
b883ab57 | 6707 | && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS |
dec0798e R |
6708 | && (! conflicting_input |
6709 | || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
6710 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
eceef4c9 BS |
6711 | && reg_overlap_mentioned_for_reload_p (rld[j].in, |
6712 | rld[i].in)) | |
c15c18c5 JW |
6713 | { |
6714 | int k; | |
6715 | ||
6716 | rld[j].when_needed | |
6717 | = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
6718 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
6719 | ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER); | |
6720 | ||
0e61db61 NS |
6721 | /* Check to see if we accidentally converted two |
6722 | reloads that use the same reload register with | |
6723 | different inputs to the same type. If so, the | |
6724 | resulting code won't work. */ | |
c15c18c5 JW |
6725 | if (rld[j].reg_rtx) |
6726 | for (k = 0; k < j; k++) | |
41374e13 NS |
6727 | gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0 |
6728 | || rld[k].when_needed != rld[j].when_needed | |
6729 | || !rtx_equal_p (rld[k].reg_rtx, | |
6730 | rld[j].reg_rtx) | |
6731 | || rtx_equal_p (rld[k].in, | |
6732 | rld[j].in)); | |
c15c18c5 | 6733 | } |
546b63fb RK |
6734 | } |
6735 | } | |
05d10675 | 6736 | } |
546b63fb | 6737 | \f |
367b1cf5 BS |
6738 | /* These arrays are filled by emit_reload_insns and its subroutines. */ |
6739 | static rtx input_reload_insns[MAX_RECOG_OPERANDS]; | |
6740 | static rtx other_input_address_reload_insns = 0; | |
6741 | static rtx other_input_reload_insns = 0; | |
6742 | static rtx input_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6743 | static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6744 | static rtx output_reload_insns[MAX_RECOG_OPERANDS]; | |
6745 | static rtx output_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6746 | static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6747 | static rtx operand_reload_insns = 0; | |
6748 | static rtx other_operand_reload_insns = 0; | |
6749 | static rtx other_output_reload_insns[MAX_RECOG_OPERANDS]; | |
6750 | ||
6751 | /* Values to be put in spill_reg_store are put here first. */ | |
6752 | static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
6753 | static HARD_REG_SET reg_reloaded_died; | |
6754 | ||
8a99f6f9 R |
6755 | /* Check if *RELOAD_REG is suitable as an intermediate or scratch register |
6756 | of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg | |
6757 | is nonzero, if that is suitable. On success, change *RELOAD_REG to the | |
6758 | adjusted register, and return true. Otherwise, return false. */ | |
6759 | static bool | |
6760 | reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg, | |
6761 | enum reg_class new_class, | |
6762 | enum machine_mode new_mode) | |
6763 | ||
6764 | { | |
6765 | rtx reg; | |
6766 | ||
6767 | for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0) | |
6768 | { | |
6769 | unsigned regno = REGNO (reg); | |
6770 | ||
6771 | if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno)) | |
6772 | continue; | |
6773 | if (GET_MODE (reg) != new_mode) | |
6774 | { | |
6775 | if (!HARD_REGNO_MODE_OK (regno, new_mode)) | |
6776 | continue; | |
6777 | if (hard_regno_nregs[regno][new_mode] | |
6778 | > hard_regno_nregs[regno][GET_MODE (reg)]) | |
6779 | continue; | |
6780 | reg = reload_adjust_reg_for_mode (reg, new_mode); | |
6781 | } | |
6782 | *reload_reg = reg; | |
6783 | return true; | |
6784 | } | |
6785 | return false; | |
6786 | } | |
6787 | ||
6788 | /* Check if *RELOAD_REG is suitable as a scratch register for the reload | |
6789 | pattern with insn_code ICODE, or alternatively, if alt_reload_reg is | |
6790 | nonzero, if that is suitable. On success, change *RELOAD_REG to the | |
6791 | adjusted register, and return true. Otherwise, return false. */ | |
6792 | static bool | |
6793 | reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg, | |
6794 | enum insn_code icode) | |
6795 | ||
6796 | { | |
6797 | enum reg_class new_class = scratch_reload_class (icode); | |
6798 | enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode; | |
6799 | ||
6800 | return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg, | |
6801 | new_class, new_mode); | |
6802 | } | |
6803 | ||
367b1cf5 BS |
6804 | /* Generate insns to perform reload RL, which is for the insn in CHAIN and |
6805 | has the number J. OLD contains the value to be used as input. */ | |
770ae6cc | 6806 | |
32131a9c | 6807 | static void |
0c20a65f AJ |
6808 | emit_input_reload_insns (struct insn_chain *chain, struct reload *rl, |
6809 | rtx old, int j) | |
32131a9c | 6810 | { |
7609e720 | 6811 | rtx insn = chain->insn; |
fb959f72 | 6812 | rtx reloadreg; |
367b1cf5 BS |
6813 | rtx oldequiv_reg = 0; |
6814 | rtx oldequiv = 0; | |
6815 | int special = 0; | |
6816 | enum machine_mode mode; | |
6817 | rtx *where; | |
6818 | ||
367b1cf5 BS |
6819 | /* delete_output_reload is only invoked properly if old contains |
6820 | the original pseudo register. Since this is replaced with a | |
6821 | hard reg when RELOAD_OVERRIDE_IN is set, see if we can | |
6822 | find the pseudo in RELOAD_IN_REG. */ | |
75803b85 | 6823 | if (reload_override_in[j] |
f8cfc6aa | 6824 | && REG_P (rl->in_reg)) |
367b1cf5 BS |
6825 | { |
6826 | oldequiv = old; | |
6827 | old = rl->in_reg; | |
6828 | } | |
6829 | if (oldequiv == 0) | |
6830 | oldequiv = old; | |
f8cfc6aa | 6831 | else if (REG_P (oldequiv)) |
367b1cf5 BS |
6832 | oldequiv_reg = oldequiv; |
6833 | else if (GET_CODE (oldequiv) == SUBREG) | |
6834 | oldequiv_reg = SUBREG_REG (oldequiv); | |
6835 | ||
fb959f72 RS |
6836 | reloadreg = reload_reg_rtx_for_input[j]; |
6837 | mode = GET_MODE (reloadreg); | |
6838 | ||
367b1cf5 BS |
6839 | /* If we are reloading from a register that was recently stored in |
6840 | with an output-reload, see if we can prove there was | |
6841 | actually no need to store the old value in it. */ | |
6842 | ||
f8cfc6aa | 6843 | if (optimize && REG_P (oldequiv) |
367b1cf5 BS |
6844 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER |
6845 | && spill_reg_store[REGNO (oldequiv)] | |
f8cfc6aa | 6846 | && REG_P (old) |
367b1cf5 BS |
6847 | && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) |
6848 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6849 | rl->out_reg))) | |
fb959f72 | 6850 | delete_output_reload (insn, j, REGNO (oldequiv), reloadreg); |
367b1cf5 | 6851 | |
fb959f72 RS |
6852 | /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from |
6853 | OLDEQUIV. */ | |
367b1cf5 | 6854 | |
367b1cf5 BS |
6855 | while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) |
6856 | oldequiv = SUBREG_REG (oldequiv); | |
6857 | if (GET_MODE (oldequiv) != VOIDmode | |
6858 | && mode != GET_MODE (oldequiv)) | |
ddef6bc7 | 6859 | oldequiv = gen_lowpart_SUBREG (mode, oldequiv); |
367b1cf5 BS |
6860 | |
6861 | /* Switch to the right place to emit the reload insns. */ | |
6862 | switch (rl->when_needed) | |
6863 | { | |
6864 | case RELOAD_OTHER: | |
6865 | where = &other_input_reload_insns; | |
6866 | break; | |
6867 | case RELOAD_FOR_INPUT: | |
6868 | where = &input_reload_insns[rl->opnum]; | |
6869 | break; | |
6870 | case RELOAD_FOR_INPUT_ADDRESS: | |
6871 | where = &input_address_reload_insns[rl->opnum]; | |
6872 | break; | |
6873 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6874 | where = &inpaddr_address_reload_insns[rl->opnum]; | |
6875 | break; | |
6876 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
6877 | where = &output_address_reload_insns[rl->opnum]; | |
6878 | break; | |
6879 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
6880 | where = &outaddr_address_reload_insns[rl->opnum]; | |
6881 | break; | |
6882 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6883 | where = &operand_reload_insns; | |
6884 | break; | |
6885 | case RELOAD_FOR_OPADDR_ADDR: | |
6886 | where = &other_operand_reload_insns; | |
6887 | break; | |
6888 | case RELOAD_FOR_OTHER_ADDRESS: | |
6889 | where = &other_input_address_reload_insns; | |
6890 | break; | |
6891 | default: | |
41374e13 | 6892 | gcc_unreachable (); |
367b1cf5 | 6893 | } |
546b63fb | 6894 | |
367b1cf5 | 6895 | push_to_sequence (*where); |
32131a9c | 6896 | |
367b1cf5 BS |
6897 | /* Auto-increment addresses must be reloaded in a special way. */ |
6898 | if (rl->out && ! rl->out_reg) | |
32131a9c | 6899 | { |
367b1cf5 BS |
6900 | /* We are not going to bother supporting the case where a |
6901 | incremented register can't be copied directly from | |
6902 | OLDEQUIV since this seems highly unlikely. */ | |
41374e13 | 6903 | gcc_assert (rl->secondary_in_reload < 0); |
32131a9c | 6904 | |
367b1cf5 BS |
6905 | if (reload_inherited[j]) |
6906 | oldequiv = reloadreg; | |
cb2afeb3 | 6907 | |
367b1cf5 | 6908 | old = XEXP (rl->in_reg, 0); |
32131a9c | 6909 | |
f8cfc6aa | 6910 | if (optimize && REG_P (oldequiv) |
367b1cf5 BS |
6911 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER |
6912 | && spill_reg_store[REGNO (oldequiv)] | |
f8cfc6aa | 6913 | && REG_P (old) |
367b1cf5 BS |
6914 | && (dead_or_set_p (insn, |
6915 | spill_reg_stored_to[REGNO (oldequiv)]) | |
6916 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6917 | old))) | |
fb959f72 | 6918 | delete_output_reload (insn, j, REGNO (oldequiv), reloadreg); |
367b1cf5 BS |
6919 | |
6920 | /* Prevent normal processing of this reload. */ | |
6921 | special = 1; | |
6922 | /* Output a special code sequence for this case. */ | |
6923 | new_spill_reg_store[REGNO (reloadreg)] | |
6924 | = inc_for_reload (reloadreg, oldequiv, rl->out, | |
6925 | rl->inc); | |
6926 | } | |
32131a9c | 6927 | |
367b1cf5 BS |
6928 | /* If we are reloading a pseudo-register that was set by the previous |
6929 | insn, see if we can get rid of that pseudo-register entirely | |
6930 | by redirecting the previous insn into our reload register. */ | |
6931 | ||
f8cfc6aa | 6932 | else if (optimize && REG_P (old) |
367b1cf5 BS |
6933 | && REGNO (old) >= FIRST_PSEUDO_REGISTER |
6934 | && dead_or_set_p (insn, old) | |
6935 | /* This is unsafe if some other reload | |
6936 | uses the same reg first. */ | |
ff6534ad | 6937 | && ! conflicts_with_override (reloadreg) |
c02cad8f BS |
6938 | && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum, |
6939 | rl->when_needed, old, rl->out, j, 0)) | |
367b1cf5 BS |
6940 | { |
6941 | rtx temp = PREV_INSN (insn); | |
4b4bf941 | 6942 | while (temp && NOTE_P (temp)) |
367b1cf5 BS |
6943 | temp = PREV_INSN (temp); |
6944 | if (temp | |
4b4bf941 | 6945 | && NONJUMP_INSN_P (temp) |
367b1cf5 BS |
6946 | && GET_CODE (PATTERN (temp)) == SET |
6947 | && SET_DEST (PATTERN (temp)) == old | |
6948 | /* Make sure we can access insn_operand_constraint. */ | |
6949 | && asm_noperands (PATTERN (temp)) < 0 | |
367b1cf5 BS |
6950 | /* This is unsafe if operand occurs more than once in current |
6951 | insn. Perhaps some occurrences aren't reloaded. */ | |
10d1bb36 | 6952 | && count_occurrences (PATTERN (insn), old, 0) == 1) |
367b1cf5 | 6953 | { |
10d1bb36 | 6954 | rtx old = SET_DEST (PATTERN (temp)); |
367b1cf5 BS |
6955 | /* Store into the reload register instead of the pseudo. */ |
6956 | SET_DEST (PATTERN (temp)) = reloadreg; | |
6957 | ||
10d1bb36 JH |
6958 | /* Verify that resulting insn is valid. */ |
6959 | extract_insn (temp); | |
6960 | if (constrain_operands (1)) | |
32131a9c | 6961 | { |
10d1bb36 JH |
6962 | /* If the previous insn is an output reload, the source is |
6963 | a reload register, and its spill_reg_store entry will | |
6964 | contain the previous destination. This is now | |
6965 | invalid. */ | |
f8cfc6aa | 6966 | if (REG_P (SET_SRC (PATTERN (temp))) |
10d1bb36 JH |
6967 | && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER) |
6968 | { | |
6969 | spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0; | |
6970 | spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; | |
6971 | } | |
32131a9c | 6972 | |
10d1bb36 JH |
6973 | /* If these are the only uses of the pseudo reg, |
6974 | pretend for GDB it lives in the reload reg we used. */ | |
6975 | if (REG_N_DEATHS (REGNO (old)) == 1 | |
6976 | && REG_N_SETS (REGNO (old)) == 1) | |
6977 | { | |
fb959f72 | 6978 | reg_renumber[REGNO (old)] = REGNO (reloadreg); |
2af2dbdc | 6979 | if (ira_conflicts_p) |
058e97ec VM |
6980 | /* Inform IRA about the change. */ |
6981 | ira_mark_allocation_change (REGNO (old)); | |
6982 | alter_reg (REGNO (old), -1, false); | |
10d1bb36 JH |
6983 | } |
6984 | special = 1; | |
6985 | } | |
6986 | else | |
cb2afeb3 | 6987 | { |
10d1bb36 | 6988 | SET_DEST (PATTERN (temp)) = old; |
32131a9c | 6989 | } |
367b1cf5 BS |
6990 | } |
6991 | } | |
32131a9c | 6992 | |
367b1cf5 | 6993 | /* We can't do that, so output an insn to load RELOADREG. */ |
32131a9c | 6994 | |
367b1cf5 BS |
6995 | /* If we have a secondary reload, pick up the secondary register |
6996 | and icode, if any. If OLDEQUIV and OLD are different or | |
6997 | if this is an in-out reload, recompute whether or not we | |
6998 | still need a secondary register and what the icode should | |
6999 | be. If we still need a secondary register and the class or | |
7000 | icode is different, go back to reloading from OLD if using | |
7001 | OLDEQUIV means that we got the wrong type of register. We | |
7002 | cannot have different class or icode due to an in-out reload | |
7003 | because we don't make such reloads when both the input and | |
7004 | output need secondary reload registers. */ | |
7005 | ||
07875628 | 7006 | if (! special && rl->secondary_in_reload >= 0) |
367b1cf5 BS |
7007 | { |
7008 | rtx second_reload_reg = 0; | |
8a99f6f9 | 7009 | rtx third_reload_reg = 0; |
367b1cf5 BS |
7010 | int secondary_reload = rl->secondary_in_reload; |
7011 | rtx real_oldequiv = oldequiv; | |
7012 | rtx real_old = old; | |
7013 | rtx tmp; | |
7014 | enum insn_code icode; | |
8a99f6f9 | 7015 | enum insn_code tertiary_icode = CODE_FOR_nothing; |
367b1cf5 BS |
7016 | |
7017 | /* If OLDEQUIV is a pseudo with a MEM, get the real MEM | |
7018 | and similarly for OLD. | |
7019 | See comments in get_secondary_reload in reload.c. */ | |
7020 | /* If it is a pseudo that cannot be replaced with its | |
7021 | equivalent MEM, we must fall back to reload_in, which | |
7022 | will have all the necessary substitutions registered. | |
7023 | Likewise for a pseudo that can't be replaced with its | |
7024 | equivalent constant. | |
7025 | ||
7026 | Take extra care for subregs of such pseudos. Note that | |
7027 | we cannot use reg_equiv_mem in this case because it is | |
7028 | not in the right mode. */ | |
7029 | ||
7030 | tmp = oldequiv; | |
7031 | if (GET_CODE (tmp) == SUBREG) | |
7032 | tmp = SUBREG_REG (tmp); | |
f8cfc6aa | 7033 | if (REG_P (tmp) |
367b1cf5 BS |
7034 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER |
7035 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
7036 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
7037 | { | |
7038 | if (! reg_equiv_mem[REGNO (tmp)] | |
7039 | || num_not_at_initial_offset | |
7040 | || GET_CODE (oldequiv) == SUBREG) | |
7041 | real_oldequiv = rl->in; | |
7042 | else | |
7043 | real_oldequiv = reg_equiv_mem[REGNO (tmp)]; | |
7044 | } | |
32131a9c | 7045 | |
367b1cf5 BS |
7046 | tmp = old; |
7047 | if (GET_CODE (tmp) == SUBREG) | |
7048 | tmp = SUBREG_REG (tmp); | |
f8cfc6aa | 7049 | if (REG_P (tmp) |
367b1cf5 BS |
7050 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER |
7051 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
7052 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
7053 | { | |
7054 | if (! reg_equiv_mem[REGNO (tmp)] | |
7055 | || num_not_at_initial_offset | |
7056 | || GET_CODE (old) == SUBREG) | |
7057 | real_old = rl->in; | |
7058 | else | |
7059 | real_old = reg_equiv_mem[REGNO (tmp)]; | |
7060 | } | |
7061 | ||
7062 | second_reload_reg = rld[secondary_reload].reg_rtx; | |
8a99f6f9 R |
7063 | if (rld[secondary_reload].secondary_in_reload >= 0) |
7064 | { | |
7065 | int tertiary_reload = rld[secondary_reload].secondary_in_reload; | |
7066 | ||
7067 | third_reload_reg = rld[tertiary_reload].reg_rtx; | |
7068 | tertiary_icode = rld[secondary_reload].secondary_in_icode; | |
7069 | /* We'd have to add more code for quartary reloads. */ | |
7070 | gcc_assert (rld[tertiary_reload].secondary_in_reload < 0); | |
7071 | } | |
367b1cf5 BS |
7072 | icode = rl->secondary_in_icode; |
7073 | ||
7074 | if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) | |
7075 | || (rl->in != 0 && rl->out != 0)) | |
7076 | { | |
8a99f6f9 R |
7077 | secondary_reload_info sri, sri2; |
7078 | enum reg_class new_class, new_t_class; | |
367b1cf5 | 7079 | |
8a99f6f9 R |
7080 | sri.icode = CODE_FOR_nothing; |
7081 | sri.prev_sri = NULL; | |
48c54229 | 7082 | new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass, |
8a99f6f9 R |
7083 | mode, &sri); |
7084 | ||
7085 | if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing) | |
367b1cf5 | 7086 | second_reload_reg = 0; |
8a99f6f9 | 7087 | else if (new_class == NO_REGS) |
32131a9c | 7088 | { |
8a99f6f9 R |
7089 | if (reload_adjust_reg_for_icode (&second_reload_reg, |
7090 | third_reload_reg, sri.icode)) | |
7091 | icode = sri.icode, third_reload_reg = 0; | |
367b1cf5 | 7092 | else |
8a99f6f9 R |
7093 | oldequiv = old, real_oldequiv = real_old; |
7094 | } | |
7095 | else if (sri.icode != CODE_FOR_nothing) | |
7096 | /* We currently lack a way to express this in reloads. */ | |
7097 | gcc_unreachable (); | |
7098 | else | |
7099 | { | |
7100 | sri2.icode = CODE_FOR_nothing; | |
7101 | sri2.prev_sri = &sri; | |
7102 | new_t_class = targetm.secondary_reload (1, real_oldequiv, | |
7103 | new_class, mode, &sri); | |
7104 | if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing) | |
32131a9c | 7105 | { |
8a99f6f9 R |
7106 | if (reload_adjust_reg_for_temp (&second_reload_reg, |
7107 | third_reload_reg, | |
7108 | new_class, mode)) | |
7109 | third_reload_reg = 0, tertiary_icode = sri2.icode; | |
367b1cf5 | 7110 | else |
8a99f6f9 R |
7111 | oldequiv = old, real_oldequiv = real_old; |
7112 | } | |
7113 | else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing) | |
7114 | { | |
7115 | rtx intermediate = second_reload_reg; | |
d30e8ef0 | 7116 | |
8a99f6f9 R |
7117 | if (reload_adjust_reg_for_temp (&intermediate, NULL, |
7118 | new_class, mode) | |
7119 | && reload_adjust_reg_for_icode (&third_reload_reg, NULL, | |
7120 | sri2.icode)) | |
32131a9c | 7121 | { |
8a99f6f9 R |
7122 | second_reload_reg = intermediate; |
7123 | tertiary_icode = sri2.icode; | |
7124 | } | |
7125 | else | |
7126 | oldequiv = old, real_oldequiv = real_old; | |
7127 | } | |
7128 | else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing) | |
7129 | { | |
7130 | rtx intermediate = second_reload_reg; | |
7131 | ||
7132 | if (reload_adjust_reg_for_temp (&intermediate, NULL, | |
7133 | new_class, mode) | |
7134 | && reload_adjust_reg_for_temp (&third_reload_reg, NULL, | |
7135 | new_t_class, mode)) | |
7136 | { | |
7137 | second_reload_reg = intermediate; | |
7138 | tertiary_icode = sri2.icode; | |
32131a9c | 7139 | } |
8a99f6f9 R |
7140 | else |
7141 | oldequiv = old, real_oldequiv = real_old; | |
32131a9c | 7142 | } |
8a99f6f9 R |
7143 | else |
7144 | /* This could be handled more intelligently too. */ | |
7145 | oldequiv = old, real_oldequiv = real_old; | |
32131a9c | 7146 | } |
367b1cf5 | 7147 | } |
32131a9c | 7148 | |
367b1cf5 BS |
7149 | /* If we still need a secondary reload register, check |
7150 | to see if it is being used as a scratch or intermediate | |
7151 | register and generate code appropriately. If we need | |
7152 | a scratch register, use REAL_OLDEQUIV since the form of | |
7153 | the insn may depend on the actual address if it is | |
7154 | a MEM. */ | |
546b63fb | 7155 | |
367b1cf5 BS |
7156 | if (second_reload_reg) |
7157 | { | |
7158 | if (icode != CODE_FOR_nothing) | |
32131a9c | 7159 | { |
8a99f6f9 R |
7160 | /* We'd have to add extra code to handle this case. */ |
7161 | gcc_assert (!third_reload_reg); | |
7162 | ||
367b1cf5 BS |
7163 | emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, |
7164 | second_reload_reg)); | |
07875628 | 7165 | special = 1; |
367b1cf5 BS |
7166 | } |
7167 | else | |
7168 | { | |
7169 | /* See if we need a scratch register to load the | |
7170 | intermediate register (a tertiary reload). */ | |
367b1cf5 BS |
7171 | if (tertiary_icode != CODE_FOR_nothing) |
7172 | { | |
367b1cf5 BS |
7173 | emit_insn ((GEN_FCN (tertiary_icode) |
7174 | (second_reload_reg, real_oldequiv, | |
7175 | third_reload_reg))); | |
7176 | } | |
8a99f6f9 R |
7177 | else if (third_reload_reg) |
7178 | { | |
7179 | gen_reload (third_reload_reg, real_oldequiv, | |
7180 | rl->opnum, | |
7181 | rl->when_needed); | |
7182 | gen_reload (second_reload_reg, third_reload_reg, | |
7183 | rl->opnum, | |
7184 | rl->when_needed); | |
7185 | } | |
367b1cf5 BS |
7186 | else |
7187 | gen_reload (second_reload_reg, real_oldequiv, | |
7188 | rl->opnum, | |
7189 | rl->when_needed); | |
32131a9c | 7190 | |
367b1cf5 BS |
7191 | oldequiv = second_reload_reg; |
7192 | } | |
7193 | } | |
7194 | } | |
32131a9c | 7195 | |
07875628 | 7196 | if (! special && ! rtx_equal_p (reloadreg, oldequiv)) |
367b1cf5 BS |
7197 | { |
7198 | rtx real_oldequiv = oldequiv; | |
7199 | ||
f8cfc6aa | 7200 | if ((REG_P (oldequiv) |
367b1cf5 BS |
7201 | && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER |
7202 | && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0 | |
7203 | || reg_equiv_constant[REGNO (oldequiv)] != 0)) | |
7204 | || (GET_CODE (oldequiv) == SUBREG | |
f8cfc6aa | 7205 | && REG_P (SUBREG_REG (oldequiv)) |
367b1cf5 BS |
7206 | && (REGNO (SUBREG_REG (oldequiv)) |
7207 | >= FIRST_PSEUDO_REGISTER) | |
7208 | && ((reg_equiv_memory_loc | |
7209 | [REGNO (SUBREG_REG (oldequiv))] != 0) | |
7210 | || (reg_equiv_constant | |
716120a7 JJ |
7211 | [REGNO (SUBREG_REG (oldequiv))] != 0))) |
7212 | || (CONSTANT_P (oldequiv) | |
019d2e99 AS |
7213 | && (PREFERRED_RELOAD_CLASS (oldequiv, |
7214 | REGNO_REG_CLASS (REGNO (reloadreg))) | |
7215 | == NO_REGS))) | |
367b1cf5 BS |
7216 | real_oldequiv = rl->in; |
7217 | gen_reload (reloadreg, real_oldequiv, rl->opnum, | |
7218 | rl->when_needed); | |
7219 | } | |
32131a9c | 7220 | |
94bd63e5 AH |
7221 | if (flag_non_call_exceptions) |
7222 | copy_eh_notes (insn, get_insns ()); | |
7223 | ||
367b1cf5 BS |
7224 | /* End this sequence. */ |
7225 | *where = get_insns (); | |
7226 | end_sequence (); | |
a6a2274a | 7227 | |
367b1cf5 BS |
7228 | /* Update reload_override_in so that delete_address_reloads_1 |
7229 | can see the actual register usage. */ | |
7230 | if (oldequiv_reg) | |
7231 | reload_override_in[j] = oldequiv; | |
7232 | } | |
32131a9c | 7233 | |
367b1cf5 BS |
7234 | /* Generate insns to for the output reload RL, which is for the insn described |
7235 | by CHAIN and has the number J. */ | |
7236 | static void | |
0c20a65f AJ |
7237 | emit_output_reload_insns (struct insn_chain *chain, struct reload *rl, |
7238 | int j) | |
367b1cf5 | 7239 | { |
fb959f72 | 7240 | rtx reloadreg; |
367b1cf5 BS |
7241 | rtx insn = chain->insn; |
7242 | int special = 0; | |
7243 | rtx old = rl->out; | |
fb959f72 | 7244 | enum machine_mode mode; |
367b1cf5 | 7245 | rtx p; |
fb959f72 | 7246 | rtx rl_reg_rtx; |
32131a9c | 7247 | |
367b1cf5 BS |
7248 | if (rl->when_needed == RELOAD_OTHER) |
7249 | start_sequence (); | |
7250 | else | |
7251 | push_to_sequence (output_reload_insns[rl->opnum]); | |
32131a9c | 7252 | |
fb959f72 RS |
7253 | rl_reg_rtx = reload_reg_rtx_for_output[j]; |
7254 | mode = GET_MODE (rl_reg_rtx); | |
546b63fb | 7255 | |
fb959f72 | 7256 | reloadreg = rl_reg_rtx; |
32131a9c | 7257 | |
367b1cf5 BS |
7258 | /* If we need two reload regs, set RELOADREG to the intermediate |
7259 | one, since it will be stored into OLD. We might need a secondary | |
7260 | register only for an input reload, so check again here. */ | |
32131a9c | 7261 | |
367b1cf5 BS |
7262 | if (rl->secondary_out_reload >= 0) |
7263 | { | |
7264 | rtx real_old = old; | |
8a99f6f9 R |
7265 | int secondary_reload = rl->secondary_out_reload; |
7266 | int tertiary_reload = rld[secondary_reload].secondary_out_reload; | |
cb2afeb3 | 7267 | |
f8cfc6aa | 7268 | if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER |
367b1cf5 BS |
7269 | && reg_equiv_mem[REGNO (old)] != 0) |
7270 | real_old = reg_equiv_mem[REGNO (old)]; | |
32131a9c | 7271 | |
48c54229 | 7272 | if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS) |
b60a8416 | 7273 | { |
367b1cf5 | 7274 | rtx second_reloadreg = reloadreg; |
8a99f6f9 | 7275 | reloadreg = rld[secondary_reload].reg_rtx; |
32131a9c | 7276 | |
367b1cf5 BS |
7277 | /* See if RELOADREG is to be used as a scratch register |
7278 | or as an intermediate register. */ | |
7279 | if (rl->secondary_out_icode != CODE_FOR_nothing) | |
7280 | { | |
8a99f6f9 R |
7281 | /* We'd have to add extra code to handle this case. */ |
7282 | gcc_assert (tertiary_reload < 0); | |
7283 | ||
367b1cf5 BS |
7284 | emit_insn ((GEN_FCN (rl->secondary_out_icode) |
7285 | (real_old, second_reloadreg, reloadreg))); | |
7286 | special = 1; | |
7287 | } | |
7288 | else | |
7289 | { | |
7290 | /* See if we need both a scratch and intermediate reload | |
7291 | register. */ | |
32131a9c | 7292 | |
367b1cf5 BS |
7293 | enum insn_code tertiary_icode |
7294 | = rld[secondary_reload].secondary_out_icode; | |
32131a9c | 7295 | |
8a99f6f9 R |
7296 | /* We'd have to add more code for quartary reloads. */ |
7297 | gcc_assert (tertiary_reload < 0 | |
7298 | || rld[tertiary_reload].secondary_out_reload < 0); | |
7299 | ||
367b1cf5 | 7300 | if (GET_MODE (reloadreg) != mode) |
f12448c8 | 7301 | reloadreg = reload_adjust_reg_for_mode (reloadreg, mode); |
cb2afeb3 | 7302 | |
367b1cf5 BS |
7303 | if (tertiary_icode != CODE_FOR_nothing) |
7304 | { | |
8a99f6f9 | 7305 | rtx third_reloadreg = rld[tertiary_reload].reg_rtx; |
367b1cf5 BS |
7306 | rtx tem; |
7307 | ||
7308 | /* Copy primary reload reg to secondary reload reg. | |
7309 | (Note that these have been swapped above, then | |
78adc5a0 | 7310 | secondary reload reg to OLD using our insn.) */ |
367b1cf5 BS |
7311 | |
7312 | /* If REAL_OLD is a paradoxical SUBREG, remove it | |
7313 | and try to put the opposite SUBREG on | |
7314 | RELOADREG. */ | |
7315 | if (GET_CODE (real_old) == SUBREG | |
7316 | && (GET_MODE_SIZE (GET_MODE (real_old)) | |
7317 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old)))) | |
7318 | && 0 != (tem = gen_lowpart_common | |
7319 | (GET_MODE (SUBREG_REG (real_old)), | |
7320 | reloadreg))) | |
7321 | real_old = SUBREG_REG (real_old), reloadreg = tem; | |
7322 | ||
7323 | gen_reload (reloadreg, second_reloadreg, | |
7324 | rl->opnum, rl->when_needed); | |
7325 | emit_insn ((GEN_FCN (tertiary_icode) | |
7326 | (real_old, reloadreg, third_reloadreg))); | |
7327 | special = 1; | |
7328 | } | |
05d10675 | 7329 | |
367b1cf5 | 7330 | else |
8a99f6f9 R |
7331 | { |
7332 | /* Copy between the reload regs here and then to | |
7333 | OUT later. */ | |
7334 | ||
7335 | gen_reload (reloadreg, second_reloadreg, | |
7336 | rl->opnum, rl->when_needed); | |
7337 | if (tertiary_reload >= 0) | |
7338 | { | |
7339 | rtx third_reloadreg = rld[tertiary_reload].reg_rtx; | |
cb2afeb3 | 7340 | |
8a99f6f9 R |
7341 | gen_reload (third_reloadreg, reloadreg, |
7342 | rl->opnum, rl->when_needed); | |
7343 | reloadreg = third_reloadreg; | |
7344 | } | |
7345 | } | |
a7911cd2 | 7346 | } |
367b1cf5 BS |
7347 | } |
7348 | } | |
32131a9c | 7349 | |
367b1cf5 BS |
7350 | /* Output the last reload insn. */ |
7351 | if (! special) | |
7352 | { | |
7353 | rtx set; | |
7354 | ||
7355 | /* Don't output the last reload if OLD is not the dest of | |
1d7254c5 | 7356 | INSN and is in the src and is clobbered by INSN. */ |
367b1cf5 | 7357 | if (! flag_expensive_optimizations |
f8cfc6aa | 7358 | || !REG_P (old) |
367b1cf5 BS |
7359 | || !(set = single_set (insn)) |
7360 | || rtx_equal_p (old, SET_DEST (set)) | |
7361 | || !reg_mentioned_p (old, SET_SRC (set)) | |
2ca39620 KK |
7362 | || !((REGNO (old) < FIRST_PSEUDO_REGISTER) |
7363 | && regno_clobbered_p (REGNO (old), insn, rl->mode, 0))) | |
367b1cf5 BS |
7364 | gen_reload (old, reloadreg, rl->opnum, |
7365 | rl->when_needed); | |
7366 | } | |
32131a9c | 7367 | |
367b1cf5 BS |
7368 | /* Look at all insns we emitted, just to be safe. */ |
7369 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2c3c49de | 7370 | if (INSN_P (p)) |
367b1cf5 BS |
7371 | { |
7372 | rtx pat = PATTERN (p); | |
546b63fb | 7373 | |
367b1cf5 BS |
7374 | /* If this output reload doesn't come from a spill reg, |
7375 | clear any memory of reloaded copies of the pseudo reg. | |
7376 | If this output reload comes from a spill reg, | |
7377 | reg_has_output_reload will make this do nothing. */ | |
7378 | note_stores (pat, forget_old_reloads_1, NULL); | |
cb2afeb3 | 7379 | |
fb959f72 | 7380 | if (reg_mentioned_p (rl_reg_rtx, pat)) |
367b1cf5 BS |
7381 | { |
7382 | rtx set = single_set (insn); | |
7383 | if (reload_spill_index[j] < 0 | |
7384 | && set | |
fb959f72 | 7385 | && SET_SRC (set) == rl_reg_rtx) |
367b1cf5 BS |
7386 | { |
7387 | int src = REGNO (SET_SRC (set)); | |
32131a9c | 7388 | |
367b1cf5 BS |
7389 | reload_spill_index[j] = src; |
7390 | SET_HARD_REG_BIT (reg_is_output_reload, src); | |
7391 | if (find_regno_note (insn, REG_DEAD, src)) | |
7392 | SET_HARD_REG_BIT (reg_reloaded_died, src); | |
7393 | } | |
fb959f72 | 7394 | if (HARD_REGISTER_P (rl_reg_rtx)) |
367b1cf5 BS |
7395 | { |
7396 | int s = rl->secondary_out_reload; | |
7397 | set = single_set (p); | |
7398 | /* If this reload copies only to the secondary reload | |
7399 | register, the secondary reload does the actual | |
7400 | store. */ | |
7401 | if (s >= 0 && set == NULL_RTX) | |
1d7254c5 KH |
7402 | /* We can't tell what function the secondary reload |
7403 | has and where the actual store to the pseudo is | |
7404 | made; leave new_spill_reg_store alone. */ | |
7405 | ; | |
367b1cf5 | 7406 | else if (s >= 0 |
fb959f72 | 7407 | && SET_SRC (set) == rl_reg_rtx |
367b1cf5 BS |
7408 | && SET_DEST (set) == rld[s].reg_rtx) |
7409 | { | |
7410 | /* Usually the next instruction will be the | |
7411 | secondary reload insn; if we can confirm | |
7412 | that it is, setting new_spill_reg_store to | |
7413 | that insn will allow an extra optimization. */ | |
7414 | rtx s_reg = rld[s].reg_rtx; | |
7415 | rtx next = NEXT_INSN (p); | |
7416 | rld[s].out = rl->out; | |
7417 | rld[s].out_reg = rl->out_reg; | |
7418 | set = single_set (next); | |
7419 | if (set && SET_SRC (set) == s_reg | |
7420 | && ! new_spill_reg_store[REGNO (s_reg)]) | |
7421 | { | |
7422 | SET_HARD_REG_BIT (reg_is_output_reload, | |
7423 | REGNO (s_reg)); | |
7424 | new_spill_reg_store[REGNO (s_reg)] = next; | |
7425 | } | |
7426 | } | |
7427 | else | |
fb959f72 | 7428 | new_spill_reg_store[REGNO (rl_reg_rtx)] = p; |
367b1cf5 BS |
7429 | } |
7430 | } | |
7431 | } | |
32131a9c | 7432 | |
367b1cf5 BS |
7433 | if (rl->when_needed == RELOAD_OTHER) |
7434 | { | |
2f937369 | 7435 | emit_insn (other_output_reload_insns[rl->opnum]); |
367b1cf5 BS |
7436 | other_output_reload_insns[rl->opnum] = get_insns (); |
7437 | } | |
7438 | else | |
7439 | output_reload_insns[rl->opnum] = get_insns (); | |
32131a9c | 7440 | |
94bd63e5 AH |
7441 | if (flag_non_call_exceptions) |
7442 | copy_eh_notes (insn, get_insns ()); | |
7443 | ||
1d7254c5 | 7444 | end_sequence (); |
367b1cf5 | 7445 | } |
32131a9c | 7446 | |
367b1cf5 BS |
7447 | /* Do input reloading for reload RL, which is for the insn described by CHAIN |
7448 | and has the number J. */ | |
7449 | static void | |
0c20a65f | 7450 | do_input_reload (struct insn_chain *chain, struct reload *rl, int j) |
367b1cf5 | 7451 | { |
367b1cf5 | 7452 | rtx insn = chain->insn; |
3c0cb5de | 7453 | rtx old = (rl->in && MEM_P (rl->in) |
367b1cf5 | 7454 | ? rl->in_reg : rl->in); |
fb959f72 RS |
7455 | rtx reg_rtx = rl->reg_rtx; |
7456 | ||
7457 | if (old && reg_rtx) | |
7458 | { | |
7459 | enum machine_mode mode; | |
7460 | ||
7461 | /* Determine the mode to reload in. | |
7462 | This is very tricky because we have three to choose from. | |
7463 | There is the mode the insn operand wants (rl->inmode). | |
7464 | There is the mode of the reload register RELOADREG. | |
7465 | There is the intrinsic mode of the operand, which we could find | |
7466 | by stripping some SUBREGs. | |
7467 | It turns out that RELOADREG's mode is irrelevant: | |
7468 | we can change that arbitrarily. | |
7469 | ||
7470 | Consider (SUBREG:SI foo:QI) as an operand that must be SImode; | |
7471 | then the reload reg may not support QImode moves, so use SImode. | |
7472 | If foo is in memory due to spilling a pseudo reg, this is safe, | |
7473 | because the QImode value is in the least significant part of a | |
7474 | slot big enough for a SImode. If foo is some other sort of | |
7475 | memory reference, then it is impossible to reload this case, | |
7476 | so previous passes had better make sure this never happens. | |
7477 | ||
7478 | Then consider a one-word union which has SImode and one of its | |
7479 | members is a float, being fetched as (SUBREG:SF union:SI). | |
7480 | We must fetch that as SFmode because we could be loading into | |
7481 | a float-only register. In this case OLD's mode is correct. | |
7482 | ||
7483 | Consider an immediate integer: it has VOIDmode. Here we need | |
7484 | to get a mode from something else. | |
7485 | ||
7486 | In some cases, there is a fourth mode, the operand's | |
7487 | containing mode. If the insn specifies a containing mode for | |
7488 | this operand, it overrides all others. | |
7489 | ||
7490 | I am not sure whether the algorithm here is always right, | |
7491 | but it does the right things in those cases. */ | |
7492 | ||
7493 | mode = GET_MODE (old); | |
7494 | if (mode == VOIDmode) | |
7495 | mode = rl->inmode; | |
7496 | ||
7497 | /* We cannot use gen_lowpart_common since it can do the wrong thing | |
7498 | when REG_RTX has a multi-word mode. Note that REG_RTX must | |
7499 | always be a REG here. */ | |
7500 | if (GET_MODE (reg_rtx) != mode) | |
7501 | reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode); | |
7502 | } | |
7503 | reload_reg_rtx_for_input[j] = reg_rtx; | |
367b1cf5 BS |
7504 | |
7505 | if (old != 0 | |
7506 | /* AUTO_INC reloads need to be handled even if inherited. We got an | |
7507 | AUTO_INC reload if reload_out is set but reload_out_reg isn't. */ | |
7508 | && (! reload_inherited[j] || (rl->out && ! rl->out_reg)) | |
fb959f72 RS |
7509 | && ! rtx_equal_p (reg_rtx, old) |
7510 | && reg_rtx != 0) | |
1d813780 | 7511 | emit_input_reload_insns (chain, rld + j, old, j); |
32131a9c | 7512 | |
367b1cf5 BS |
7513 | /* When inheriting a wider reload, we have a MEM in rl->in, |
7514 | e.g. inheriting a SImode output reload for | |
7515 | (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */ | |
7516 | if (optimize && reload_inherited[j] && rl->in | |
3c0cb5de JQ |
7517 | && MEM_P (rl->in) |
7518 | && MEM_P (rl->in_reg) | |
367b1cf5 BS |
7519 | && reload_spill_index[j] >= 0 |
7520 | && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j])) | |
4977bab6 | 7521 | rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]]; |
32131a9c | 7522 | |
367b1cf5 BS |
7523 | /* If we are reloading a register that was recently stored in with an |
7524 | output-reload, see if we can prove there was | |
7525 | actually no need to store the old value in it. */ | |
32131a9c | 7526 | |
367b1cf5 BS |
7527 | if (optimize |
7528 | && (reload_inherited[j] || reload_override_in[j]) | |
fb959f72 RS |
7529 | && reg_rtx |
7530 | && REG_P (reg_rtx) | |
7531 | && spill_reg_store[REGNO (reg_rtx)] != 0 | |
367b1cf5 BS |
7532 | #if 0 |
7533 | /* There doesn't seem to be any reason to restrict this to pseudos | |
7534 | and doing so loses in the case where we are copying from a | |
7535 | register of the wrong class. */ | |
fb959f72 | 7536 | && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) |
367b1cf5 BS |
7537 | #endif |
7538 | /* The insn might have already some references to stackslots | |
7539 | replaced by MEMs, while reload_out_reg still names the | |
7540 | original pseudo. */ | |
fb959f72 RS |
7541 | && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) |
7542 | || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg))) | |
7543 | delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx); | |
367b1cf5 | 7544 | } |
32131a9c | 7545 | |
367b1cf5 BS |
7546 | /* Do output reloading for reload RL, which is for the insn described by |
7547 | CHAIN and has the number J. | |
7548 | ??? At some point we need to support handling output reloads of | |
7549 | JUMP_INSNs or insns that set cc0. */ | |
7550 | static void | |
0c20a65f | 7551 | do_output_reload (struct insn_chain *chain, struct reload *rl, int j) |
367b1cf5 BS |
7552 | { |
7553 | rtx note, old; | |
7554 | rtx insn = chain->insn; | |
7555 | /* If this is an output reload that stores something that is | |
7556 | not loaded in this same reload, see if we can eliminate a previous | |
7557 | store. */ | |
7558 | rtx pseudo = rl->out_reg; | |
fb959f72 RS |
7559 | rtx reg_rtx = rl->reg_rtx; |
7560 | ||
7561 | if (rl->out && reg_rtx) | |
7562 | { | |
7563 | enum machine_mode mode; | |
7564 | ||
7565 | /* Determine the mode to reload in. | |
7566 | See comments above (for input reloading). */ | |
7567 | mode = GET_MODE (rl->out); | |
7568 | if (mode == VOIDmode) | |
7569 | { | |
7570 | /* VOIDmode should never happen for an output. */ | |
7571 | if (asm_noperands (PATTERN (insn)) < 0) | |
7572 | /* It's the compiler's fault. */ | |
7573 | fatal_insn ("VOIDmode on an output", insn); | |
7574 | error_for_asm (insn, "output operand is constant in %<asm%>"); | |
7575 | /* Prevent crash--use something we know is valid. */ | |
7576 | mode = word_mode; | |
7577 | rl->out = gen_rtx_REG (mode, REGNO (reg_rtx)); | |
7578 | } | |
7579 | if (GET_MODE (reg_rtx) != mode) | |
7580 | reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode); | |
7581 | } | |
7582 | reload_reg_rtx_for_output[j] = reg_rtx; | |
367b1cf5 BS |
7583 | |
7584 | if (pseudo | |
159d5964 | 7585 | && optimize |
f8cfc6aa | 7586 | && REG_P (pseudo) |
367b1cf5 BS |
7587 | && ! rtx_equal_p (rl->in_reg, pseudo) |
7588 | && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER | |
7589 | && reg_last_reload_reg[REGNO (pseudo)]) | |
7590 | { | |
7591 | int pseudo_no = REGNO (pseudo); | |
7592 | int last_regno = REGNO (reg_last_reload_reg[pseudo_no]); | |
7593 | ||
7594 | /* We don't need to test full validity of last_regno for | |
7595 | inherit here; we only want to know if the store actually | |
7596 | matches the pseudo. */ | |
60ef417d GK |
7597 | if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno) |
7598 | && reg_reloaded_contents[last_regno] == pseudo_no | |
367b1cf5 BS |
7599 | && spill_reg_store[last_regno] |
7600 | && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) | |
fb959f72 | 7601 | delete_output_reload (insn, j, last_regno, reg_rtx); |
367b1cf5 | 7602 | } |
5e03c156 | 7603 | |
367b1cf5 BS |
7604 | old = rl->out_reg; |
7605 | if (old == 0 | |
fb959f72 RS |
7606 | || reg_rtx == 0 |
7607 | || rtx_equal_p (old, reg_rtx)) | |
367b1cf5 | 7608 | return; |
32131a9c | 7609 | |
367b1cf5 BS |
7610 | /* An output operand that dies right away does need a reload, |
7611 | but need not be copied from it. Show the new location in the | |
7612 | REG_UNUSED note. */ | |
f8cfc6aa | 7613 | if ((REG_P (old) || GET_CODE (old) == SCRATCH) |
367b1cf5 BS |
7614 | && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) |
7615 | { | |
fb959f72 | 7616 | XEXP (note, 0) = reg_rtx; |
367b1cf5 BS |
7617 | return; |
7618 | } | |
7619 | /* Likewise for a SUBREG of an operand that dies. */ | |
7620 | else if (GET_CODE (old) == SUBREG | |
f8cfc6aa | 7621 | && REG_P (SUBREG_REG (old)) |
367b1cf5 BS |
7622 | && 0 != (note = find_reg_note (insn, REG_UNUSED, |
7623 | SUBREG_REG (old)))) | |
7624 | { | |
fb959f72 | 7625 | XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx); |
367b1cf5 BS |
7626 | return; |
7627 | } | |
7628 | else if (GET_CODE (old) == SCRATCH) | |
7629 | /* If we aren't optimizing, there won't be a REG_UNUSED note, | |
7630 | but we don't want to make an output reload. */ | |
7631 | return; | |
1554c2c6 | 7632 | |
367b1cf5 | 7633 | /* If is a JUMP_INSN, we can't support output reloads yet. */ |
ce99549f | 7634 | gcc_assert (NONJUMP_INSN_P (insn)); |
5e03c156 | 7635 | |
367b1cf5 BS |
7636 | emit_output_reload_insns (chain, rld + j, j); |
7637 | } | |
1554c2c6 | 7638 | |
fb959f72 RS |
7639 | /* A reload copies values of MODE from register SRC to register DEST. |
7640 | Return true if it can be treated for inheritance purposes like a | |
7641 | group of reloads, each one reloading a single hard register. The | |
7642 | caller has already checked that (reg:MODE SRC) and (reg:MODE DEST) | |
7643 | occupy the same number of hard registers. */ | |
b5ba341f RS |
7644 | |
7645 | static bool | |
fb959f72 RS |
7646 | inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED, |
7647 | int src ATTRIBUTE_UNUSED, | |
7648 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
b5ba341f RS |
7649 | { |
7650 | #ifdef CANNOT_CHANGE_MODE_CLASS | |
fb959f72 RS |
7651 | return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest]) |
7652 | && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src])); | |
b5ba341f RS |
7653 | #else |
7654 | return true; | |
7655 | #endif | |
7656 | } | |
7657 | ||
367b1cf5 | 7658 | /* Output insns to reload values in and out of the chosen reload regs. */ |
32131a9c | 7659 | |
367b1cf5 | 7660 | static void |
0c20a65f | 7661 | emit_reload_insns (struct insn_chain *chain) |
367b1cf5 BS |
7662 | { |
7663 | rtx insn = chain->insn; | |
32131a9c | 7664 | |
b3694847 | 7665 | int j; |
e6e52be0 | 7666 | |
367b1cf5 | 7667 | CLEAR_HARD_REG_SET (reg_reloaded_died); |
e6e52be0 | 7668 | |
367b1cf5 BS |
7669 | for (j = 0; j < reload_n_operands; j++) |
7670 | input_reload_insns[j] = input_address_reload_insns[j] | |
7671 | = inpaddr_address_reload_insns[j] | |
7672 | = output_reload_insns[j] = output_address_reload_insns[j] | |
7673 | = outaddr_address_reload_insns[j] | |
7674 | = other_output_reload_insns[j] = 0; | |
7675 | other_input_address_reload_insns = 0; | |
7676 | other_input_reload_insns = 0; | |
7677 | operand_reload_insns = 0; | |
7678 | other_operand_reload_insns = 0; | |
32131a9c | 7679 | |
850aac53 | 7680 | /* Dump reloads into the dump file. */ |
c263766c | 7681 | if (dump_file) |
850aac53 | 7682 | { |
c263766c RH |
7683 | fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn)); |
7684 | debug_reload_to_stream (dump_file); | |
850aac53 JL |
7685 | } |
7686 | ||
367b1cf5 BS |
7687 | /* Now output the instructions to copy the data into and out of the |
7688 | reload registers. Do these in the order that the reloads were reported, | |
7689 | since reloads of base and index registers precede reloads of operands | |
7690 | and the operands may need the base and index registers reloaded. */ | |
32131a9c | 7691 | |
367b1cf5 BS |
7692 | for (j = 0; j < n_reloads; j++) |
7693 | { | |
fb959f72 RS |
7694 | if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx)) |
7695 | { | |
7696 | unsigned int i; | |
7697 | ||
7698 | for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++) | |
7699 | new_spill_reg_store[i] = 0; | |
7700 | } | |
d7e0324f | 7701 | |
367b1cf5 BS |
7702 | do_input_reload (chain, rld + j, j); |
7703 | do_output_reload (chain, rld + j, j); | |
32131a9c RK |
7704 | } |
7705 | ||
546b63fb RK |
7706 | /* Now write all the insns we made for reloads in the order expected by |
7707 | the allocation functions. Prior to the insn being reloaded, we write | |
7708 | the following reloads: | |
7709 | ||
7710 | RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. | |
7711 | ||
2edc8d65 | 7712 | RELOAD_OTHER reloads. |
546b63fb | 7713 | |
47c8cf91 ILT |
7714 | For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed |
7715 | by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the | |
7716 | RELOAD_FOR_INPUT reload for the operand. | |
546b63fb | 7717 | |
893bc853 RK |
7718 | RELOAD_FOR_OPADDR_ADDRS reloads. |
7719 | ||
546b63fb RK |
7720 | RELOAD_FOR_OPERAND_ADDRESS reloads. |
7721 | ||
7722 | After the insn being reloaded, we write the following: | |
7723 | ||
47c8cf91 ILT |
7724 | For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed |
7725 | by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the | |
7726 | RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output | |
7727 | reloads for the operand. The RELOAD_OTHER output reloads are | |
7728 | output in descending order by reload number. */ | |
546b63fb | 7729 | |
a7102479 JH |
7730 | emit_insn_before (other_input_address_reload_insns, insn); |
7731 | emit_insn_before (other_input_reload_insns, insn); | |
546b63fb RK |
7732 | |
7733 | for (j = 0; j < reload_n_operands; j++) | |
7734 | { | |
a7102479 JH |
7735 | emit_insn_before (inpaddr_address_reload_insns[j], insn); |
7736 | emit_insn_before (input_address_reload_insns[j], insn); | |
7737 | emit_insn_before (input_reload_insns[j], insn); | |
546b63fb RK |
7738 | } |
7739 | ||
a7102479 JH |
7740 | emit_insn_before (other_operand_reload_insns, insn); |
7741 | emit_insn_before (operand_reload_insns, insn); | |
546b63fb RK |
7742 | |
7743 | for (j = 0; j < reload_n_operands; j++) | |
7744 | { | |
a7102479 JH |
7745 | rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn); |
7746 | x = emit_insn_after (output_address_reload_insns[j], x); | |
7747 | x = emit_insn_after (output_reload_insns[j], x); | |
7748 | emit_insn_after (other_output_reload_insns[j], x); | |
546b63fb RK |
7749 | } |
7750 | ||
32131a9c RK |
7751 | /* For all the spill regs newly reloaded in this instruction, |
7752 | record what they were reloaded from, so subsequent instructions | |
d445b551 RK |
7753 | can inherit the reloads. |
7754 | ||
7755 | Update spill_reg_store for the reloads of this insn. | |
e9e79d69 | 7756 | Copy the elements that were updated in the loop above. */ |
32131a9c RK |
7757 | |
7758 | for (j = 0; j < n_reloads; j++) | |
7759 | { | |
b3694847 SS |
7760 | int r = reload_order[j]; |
7761 | int i = reload_spill_index[r]; | |
32131a9c | 7762 | |
78a2bc08 | 7763 | /* If this is a non-inherited input reload from a pseudo, we must |
05d10675 BS |
7764 | clear any memory of a previous store to the same pseudo. Only do |
7765 | something if there will not be an output reload for the pseudo | |
7766 | being reloaded. */ | |
eceef4c9 | 7767 | if (rld[r].in_reg != 0 |
05d10675 BS |
7768 | && ! (reload_inherited[r] || reload_override_in[r])) |
7769 | { | |
eceef4c9 | 7770 | rtx reg = rld[r].in_reg; |
78a2bc08 | 7771 | |
05d10675 | 7772 | if (GET_CODE (reg) == SUBREG) |
78a2bc08 | 7773 | reg = SUBREG_REG (reg); |
05d10675 | 7774 | |
f8cfc6aa | 7775 | if (REG_P (reg) |
78a2bc08 | 7776 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER |
2c61f5f1 | 7777 | && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg))) |
78a2bc08 R |
7778 | { |
7779 | int nregno = REGNO (reg); | |
7780 | ||
7781 | if (reg_last_reload_reg[nregno]) | |
05d10675 BS |
7782 | { |
7783 | int last_regno = REGNO (reg_last_reload_reg[nregno]); | |
78a2bc08 | 7784 | |
05d10675 | 7785 | if (reg_reloaded_contents[last_regno] == nregno) |
78a2bc08 | 7786 | spill_reg_store[last_regno] = 0; |
05d10675 | 7787 | } |
78a2bc08 R |
7788 | } |
7789 | } | |
05d10675 | 7790 | |
e6e52be0 | 7791 | /* I is nonneg if this reload used a register. |
eceef4c9 | 7792 | If rld[r].reg_rtx is 0, this is an optional reload |
51f0c3b7 | 7793 | that we opted to ignore. */ |
d445b551 | 7794 | |
eceef4c9 | 7795 | if (i >= 0 && rld[r].reg_rtx != 0) |
32131a9c | 7796 | { |
66fd46b6 | 7797 | int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)]; |
32131a9c RK |
7798 | int k; |
7799 | ||
51f0c3b7 JW |
7800 | /* For a multi register reload, we need to check if all or part |
7801 | of the value lives to the end. */ | |
32131a9c | 7802 | for (k = 0; k < nr; k++) |
fb959f72 RS |
7803 | if (reload_reg_reaches_end_p (i + k, rld[r].opnum, |
7804 | rld[r].when_needed)) | |
7805 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
32131a9c | 7806 | |
fb959f72 RS |
7807 | /* Maybe the spill reg contains a copy of reload_out. */ |
7808 | if (rld[r].out != 0 | |
7809 | && (REG_P (rld[r].out) | |
cb2afeb3 | 7810 | #ifdef AUTO_INC_DEC |
fb959f72 | 7811 | || ! rld[r].out_reg |
cb2afeb3 | 7812 | #endif |
fb959f72 RS |
7813 | || REG_P (rld[r].out_reg))) |
7814 | { | |
7815 | rtx reg; | |
7816 | enum machine_mode mode; | |
7817 | int regno, nregs; | |
7818 | ||
7819 | reg = reload_reg_rtx_for_output[r]; | |
7820 | mode = GET_MODE (reg); | |
7821 | regno = REGNO (reg); | |
7822 | nregs = hard_regno_nregs[regno][mode]; | |
7823 | if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum, | |
7824 | rld[r].when_needed)) | |
51f0c3b7 | 7825 | { |
f8cfc6aa | 7826 | rtx out = (REG_P (rld[r].out) |
eceef4c9 BS |
7827 | ? rld[r].out |
7828 | : rld[r].out_reg | |
7829 | ? rld[r].out_reg | |
7830 | /* AUTO_INC */ : XEXP (rld[r].in_reg, 0)); | |
fb959f72 RS |
7831 | int out_regno = REGNO (out); |
7832 | int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1 | |
7833 | : hard_regno_nregs[out_regno][mode]); | |
b5ba341f | 7834 | bool piecemeal; |
51f0c3b7 | 7835 | |
fb959f72 RS |
7836 | spill_reg_store[regno] = new_spill_reg_store[regno]; |
7837 | spill_reg_stored_to[regno] = out; | |
7838 | reg_last_reload_reg[out_regno] = reg; | |
51f0c3b7 | 7839 | |
fb959f72 RS |
7840 | piecemeal = (HARD_REGISTER_NUM_P (out_regno) |
7841 | && nregs == out_nregs | |
7842 | && inherit_piecemeal_p (out_regno, regno, mode)); | |
b5ba341f | 7843 | |
fb959f72 | 7844 | /* If OUT_REGNO is a hard register, it may occupy more than |
05d10675 | 7845 | one register. If it does, say what is in the |
51f0c3b7 JW |
7846 | rest of the registers assuming that both registers |
7847 | agree on how many words the object takes. If not, | |
7848 | invalidate the subsequent registers. */ | |
7849 | ||
fb959f72 RS |
7850 | if (HARD_REGISTER_NUM_P (out_regno)) |
7851 | for (k = 1; k < out_nregs; k++) | |
7852 | reg_last_reload_reg[out_regno + k] | |
7853 | = (piecemeal ? regno_reg_rtx[regno + k] : 0); | |
51f0c3b7 JW |
7854 | |
7855 | /* Now do the inverse operation. */ | |
fb959f72 | 7856 | for (k = 0; k < nregs; k++) |
51f0c3b7 | 7857 | { |
fb959f72 RS |
7858 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k); |
7859 | reg_reloaded_contents[regno + k] | |
7860 | = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal | |
7861 | ? out_regno | |
7862 | : out_regno + k); | |
7863 | reg_reloaded_insn[regno + k] = insn; | |
7864 | SET_HARD_REG_BIT (reg_reloaded_valid, regno + k); | |
7865 | if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode)) | |
7866 | SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, | |
7867 | regno + k); | |
7868 | else | |
7869 | CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, | |
7870 | regno + k); | |
51f0c3b7 JW |
7871 | } |
7872 | } | |
fb959f72 RS |
7873 | } |
7874 | /* Maybe the spill reg contains a copy of reload_in. Only do | |
7875 | something if there will not be an output reload for | |
7876 | the register being reloaded. */ | |
7877 | else if (rld[r].out_reg == 0 | |
7878 | && rld[r].in != 0 | |
7879 | && ((REG_P (rld[r].in) | |
7880 | && !HARD_REGISTER_P (rld[r].in) | |
7881 | && !REGNO_REG_SET_P (®_has_output_reload, | |
7882 | REGNO (rld[r].in))) | |
7883 | || (REG_P (rld[r].in_reg) | |
7884 | && !REGNO_REG_SET_P (®_has_output_reload, | |
7885 | REGNO (rld[r].in_reg)))) | |
7886 | && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn))) | |
7887 | { | |
7888 | rtx reg; | |
7889 | enum machine_mode mode; | |
7890 | int regno, nregs; | |
7891 | ||
7892 | reg = reload_reg_rtx_for_input[r]; | |
7893 | mode = GET_MODE (reg); | |
7894 | regno = REGNO (reg); | |
7895 | nregs = hard_regno_nregs[regno][mode]; | |
7896 | if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum, | |
7897 | rld[r].when_needed)) | |
51f0c3b7 | 7898 | { |
fb959f72 RS |
7899 | int in_regno; |
7900 | int in_nregs; | |
e3e9336f | 7901 | rtx in; |
b5ba341f | 7902 | bool piecemeal; |
d445b551 | 7903 | |
f8cfc6aa | 7904 | if (REG_P (rld[r].in) |
eceef4c9 | 7905 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER) |
e3e9336f | 7906 | in = rld[r].in; |
f8cfc6aa | 7907 | else if (REG_P (rld[r].in_reg)) |
e3e9336f | 7908 | in = rld[r].in_reg; |
cb2afeb3 | 7909 | else |
e3e9336f | 7910 | in = XEXP (rld[r].in_reg, 0); |
fb959f72 | 7911 | in_regno = REGNO (in); |
d08ea79f | 7912 | |
fb959f72 RS |
7913 | in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1 |
7914 | : hard_regno_nregs[in_regno][mode]); | |
05d10675 | 7915 | |
fb959f72 | 7916 | reg_last_reload_reg[in_regno] = reg; |
51f0c3b7 | 7917 | |
fb959f72 RS |
7918 | piecemeal = (HARD_REGISTER_NUM_P (in_regno) |
7919 | && nregs == in_nregs | |
7920 | && inherit_piecemeal_p (regno, in_regno, mode)); | |
b5ba341f | 7921 | |
fb959f72 RS |
7922 | if (HARD_REGISTER_NUM_P (in_regno)) |
7923 | for (k = 1; k < in_nregs; k++) | |
7924 | reg_last_reload_reg[in_regno + k] | |
7925 | = (piecemeal ? regno_reg_rtx[regno + k] : 0); | |
51f0c3b7 JW |
7926 | |
7927 | /* Unless we inherited this reload, show we haven't | |
cb2afeb3 R |
7928 | recently done a store. |
7929 | Previous stores of inherited auto_inc expressions | |
7930 | also have to be discarded. */ | |
7931 | if (! reload_inherited[r] | |
eceef4c9 | 7932 | || (rld[r].out && ! rld[r].out_reg)) |
fb959f72 | 7933 | spill_reg_store[regno] = 0; |
51f0c3b7 | 7934 | |
fb959f72 | 7935 | for (k = 0; k < nregs; k++) |
51f0c3b7 | 7936 | { |
fb959f72 RS |
7937 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k); |
7938 | reg_reloaded_contents[regno + k] | |
7939 | = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal | |
7940 | ? in_regno | |
7941 | : in_regno + k); | |
7942 | reg_reloaded_insn[regno + k] = insn; | |
7943 | SET_HARD_REG_BIT (reg_reloaded_valid, regno + k); | |
7944 | if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode)) | |
7945 | SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, | |
7946 | regno + k); | |
7947 | else | |
7948 | CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, | |
7949 | regno + k); | |
51f0c3b7 JW |
7950 | } |
7951 | } | |
7952 | } | |
32131a9c RK |
7953 | } |
7954 | ||
7955 | /* The following if-statement was #if 0'd in 1.34 (or before...). | |
7956 | It's reenabled in 1.35 because supposedly nothing else | |
7957 | deals with this problem. */ | |
7958 | ||
7959 | /* If a register gets output-reloaded from a non-spill register, | |
7960 | that invalidates any previous reloaded copy of it. | |
7961 | But forget_old_reloads_1 won't get to see it, because | |
b81ac288 PB |
7962 | it thinks only about the original insn. So invalidate it here. |
7963 | Also do the same thing for RELOAD_OTHER constraints where the | |
7964 | output is discarded. */ | |
fb959f72 | 7965 | if (i < 0 |
b81ac288 PB |
7966 | && ((rld[r].out != 0 |
7967 | && (REG_P (rld[r].out) | |
7968 | || (MEM_P (rld[r].out) | |
7969 | && REG_P (rld[r].out_reg)))) | |
7970 | || (rld[r].out == 0 && rld[r].out_reg | |
f8cfc6aa | 7971 | && REG_P (rld[r].out_reg)))) |
32131a9c | 7972 | { |
b81ac288 | 7973 | rtx out = ((rld[r].out && REG_P (rld[r].out)) |
eceef4c9 | 7974 | ? rld[r].out : rld[r].out_reg); |
fb959f72 RS |
7975 | int out_regno = REGNO (out); |
7976 | enum machine_mode mode = GET_MODE (out); | |
92d54592 RS |
7977 | |
7978 | /* REG_RTX is now set or clobbered by the main instruction. | |
7979 | As the comment above explains, forget_old_reloads_1 only | |
7980 | sees the original instruction, and there is no guarantee | |
7981 | that the original instruction also clobbered REG_RTX. | |
7982 | For example, if find_reloads sees that the input side of | |
7983 | a matched operand pair dies in this instruction, it may | |
7984 | use the input register as the reload register. | |
7985 | ||
7986 | Calling forget_old_reloads_1 is a waste of effort if | |
7987 | REG_RTX is also the output register. | |
7988 | ||
7989 | If we know that REG_RTX holds the value of a pseudo | |
7990 | register, the code after the call will record that fact. */ | |
7991 | if (rld[r].reg_rtx && rld[r].reg_rtx != out) | |
7992 | forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL); | |
7993 | ||
fb959f72 | 7994 | if (!HARD_REGISTER_NUM_P (out_regno)) |
cb2afeb3 | 7995 | { |
6a651371 | 7996 | rtx src_reg, store_insn = NULL_RTX; |
cb2afeb3 | 7997 | |
fb959f72 | 7998 | reg_last_reload_reg[out_regno] = 0; |
cb2afeb3 R |
7999 | |
8000 | /* If we can find a hard register that is stored, record | |
8001 | the storing insn so that we may delete this insn with | |
8002 | delete_output_reload. */ | |
fb959f72 | 8003 | src_reg = reload_reg_rtx_for_output[r]; |
cb2afeb3 R |
8004 | |
8005 | /* If this is an optional reload, try to find the source reg | |
8006 | from an input reload. */ | |
8007 | if (! src_reg) | |
8008 | { | |
8009 | rtx set = single_set (insn); | |
eceef4c9 | 8010 | if (set && SET_DEST (set) == rld[r].out) |
cb2afeb3 R |
8011 | { |
8012 | int k; | |
8013 | ||
8014 | src_reg = SET_SRC (set); | |
8015 | store_insn = insn; | |
8016 | for (k = 0; k < n_reloads; k++) | |
8017 | { | |
eceef4c9 | 8018 | if (rld[k].in == src_reg) |
cb2afeb3 | 8019 | { |
fb959f72 | 8020 | src_reg = reload_reg_rtx_for_input[k]; |
cb2afeb3 R |
8021 | break; |
8022 | } | |
8023 | } | |
8024 | } | |
8025 | } | |
8026 | else | |
8027 | store_insn = new_spill_reg_store[REGNO (src_reg)]; | |
f8cfc6aa | 8028 | if (src_reg && REG_P (src_reg) |
cb2afeb3 R |
8029 | && REGNO (src_reg) < FIRST_PSEUDO_REGISTER) |
8030 | { | |
fb959f72 RS |
8031 | int src_regno, src_nregs, k; |
8032 | rtx note; | |
8033 | ||
8034 | gcc_assert (GET_MODE (src_reg) == mode); | |
8035 | src_regno = REGNO (src_reg); | |
8036 | src_nregs = hard_regno_nregs[src_regno][mode]; | |
cb2afeb3 R |
8037 | /* The place where to find a death note varies with |
8038 | PRESERVE_DEATH_INFO_REGNO_P . The condition is not | |
8039 | necessarily checked exactly in the code that moves | |
8040 | notes, so just check both locations. */ | |
fb959f72 | 8041 | note = find_regno_note (insn, REG_DEAD, src_regno); |
1558b970 | 8042 | if (! note && store_insn) |
cb2afeb3 | 8043 | note = find_regno_note (store_insn, REG_DEAD, src_regno); |
fb959f72 | 8044 | for (k = 0; k < src_nregs; k++) |
cb2afeb3 | 8045 | { |
fb959f72 RS |
8046 | spill_reg_store[src_regno + k] = store_insn; |
8047 | spill_reg_stored_to[src_regno + k] = out; | |
8048 | reg_reloaded_contents[src_regno + k] = out_regno; | |
8049 | reg_reloaded_insn[src_regno + k] = store_insn; | |
8050 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k); | |
8051 | SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k); | |
8052 | if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k, | |
8053 | mode)) | |
e3e9336f | 8054 | SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, |
fb959f72 RS |
8055 | src_regno + k); |
8056 | else | |
8057 | CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, | |
8058 | src_regno + k); | |
8059 | SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k); | |
cb2afeb3 R |
8060 | if (note) |
8061 | SET_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
8062 | else | |
8063 | CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
8064 | } | |
fb959f72 | 8065 | reg_last_reload_reg[out_regno] = src_reg; |
9532c14f UW |
8066 | /* We have to set reg_has_output_reload here, or else |
8067 | forget_old_reloads_1 will clear reg_last_reload_reg | |
8068 | right away. */ | |
2c61f5f1 | 8069 | SET_REGNO_REG_SET (®_has_output_reload, |
fb959f72 | 8070 | out_regno); |
cb2afeb3 R |
8071 | } |
8072 | } | |
c7093272 RK |
8073 | else |
8074 | { | |
fb959f72 | 8075 | int k, out_nregs = hard_regno_nregs[out_regno][mode]; |
36281332 | 8076 | |
fb959f72 RS |
8077 | for (k = 0; k < out_nregs; k++) |
8078 | reg_last_reload_reg[out_regno + k] = 0; | |
c7093272 | 8079 | } |
32131a9c RK |
8080 | } |
8081 | } | |
e6e52be0 | 8082 | IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died); |
32131a9c RK |
8083 | } |
8084 | \f | |
ff0d9879 HPN |
8085 | /* Go through the motions to emit INSN and test if it is strictly valid. |
8086 | Return the emitted insn if valid, else return NULL. */ | |
8087 | ||
8088 | static rtx | |
8089 | emit_insn_if_valid_for_reload (rtx insn) | |
8090 | { | |
8091 | rtx last = get_last_insn (); | |
8092 | int code; | |
8093 | ||
8094 | insn = emit_insn (insn); | |
8095 | code = recog_memoized (insn); | |
8096 | ||
8097 | if (code >= 0) | |
8098 | { | |
8099 | extract_insn (insn); | |
8100 | /* We want constrain operands to treat this insn strictly in its | |
8101 | validity determination, i.e., the way it would after reload has | |
8102 | completed. */ | |
8103 | if (constrain_operands (1)) | |
8104 | return insn; | |
8105 | } | |
8106 | ||
8107 | delete_insns_since (last); | |
8108 | return NULL; | |
8109 | } | |
8110 | ||
5e03c156 RK |
8111 | /* Emit code to perform a reload from IN (which may be a reload register) to |
8112 | OUT (which may also be a reload register). IN or OUT is from operand | |
05d10675 | 8113 | OPNUM with reload type TYPE. |
546b63fb | 8114 | |
3c3eeea6 | 8115 | Returns first insn emitted. */ |
32131a9c | 8116 | |
bf9a0db3 | 8117 | static rtx |
0c20a65f | 8118 | gen_reload (rtx out, rtx in, int opnum, enum reload_type type) |
32131a9c | 8119 | { |
546b63fb | 8120 | rtx last = get_last_insn (); |
7a5b18b0 RK |
8121 | rtx tem; |
8122 | ||
8123 | /* If IN is a paradoxical SUBREG, remove it and try to put the | |
8124 | opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ | |
8125 | if (GET_CODE (in) == SUBREG | |
8126 | && (GET_MODE_SIZE (GET_MODE (in)) | |
8127 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
8128 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0) | |
8129 | in = SUBREG_REG (in), out = tem; | |
8130 | else if (GET_CODE (out) == SUBREG | |
eceef4c9 BS |
8131 | && (GET_MODE_SIZE (GET_MODE (out)) |
8132 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) | |
8133 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0) | |
7a5b18b0 | 8134 | out = SUBREG_REG (out), in = tem; |
32131a9c | 8135 | |
a8fdc208 | 8136 | /* How to do this reload can get quite tricky. Normally, we are being |
32131a9c RK |
8137 | asked to reload a simple operand, such as a MEM, a constant, or a pseudo |
8138 | register that didn't get a hard register. In that case we can just | |
8139 | call emit_move_insn. | |
8140 | ||
a7fd196c JW |
8141 | We can also be asked to reload a PLUS that adds a register or a MEM to |
8142 | another register, constant or MEM. This can occur during frame pointer | |
8143 | elimination and while reloading addresses. This case is handled by | |
8144 | trying to emit a single insn to perform the add. If it is not valid, | |
8145 | we use a two insn sequence. | |
32131a9c | 8146 | |
ff0d9879 HPN |
8147 | Or we can be asked to reload an unary operand that was a fragment of |
8148 | an addressing mode, into a register. If it isn't recognized as-is, | |
8149 | we try making the unop operand and the reload-register the same: | |
8150 | (set reg:X (unop:X expr:Y)) | |
8151 | -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)). | |
8152 | ||
32131a9c RK |
8153 | Finally, we could be called to handle an 'o' constraint by putting |
8154 | an address into a register. In that case, we first try to do this | |
8155 | with a named pattern of "reload_load_address". If no such pattern | |
8156 | exists, we just emit a SET insn and hope for the best (it will normally | |
8157 | be valid on machines that use 'o'). | |
8158 | ||
8159 | This entire process is made complex because reload will never | |
8160 | process the insns we generate here and so we must ensure that | |
8161 | they will fit their constraints and also by the fact that parts of | |
8162 | IN might be being reloaded separately and replaced with spill registers. | |
8163 | Because of this, we are, in some sense, just guessing the right approach | |
8164 | here. The one listed above seems to work. | |
8165 | ||
8166 | ??? At some point, this whole thing needs to be rethought. */ | |
8167 | ||
8168 | if (GET_CODE (in) == PLUS | |
f8cfc6aa | 8169 | && (REG_P (XEXP (in, 0)) |
5c6b1bd2 | 8170 | || GET_CODE (XEXP (in, 0)) == SUBREG |
3c0cb5de | 8171 | || MEM_P (XEXP (in, 0))) |
f8cfc6aa | 8172 | && (REG_P (XEXP (in, 1)) |
5c6b1bd2 | 8173 | || GET_CODE (XEXP (in, 1)) == SUBREG |
a7fd196c | 8174 | || CONSTANT_P (XEXP (in, 1)) |
3c0cb5de | 8175 | || MEM_P (XEXP (in, 1)))) |
32131a9c | 8176 | { |
a7fd196c JW |
8177 | /* We need to compute the sum of a register or a MEM and another |
8178 | register, constant, or MEM, and put it into the reload | |
3002e160 JW |
8179 | register. The best possible way of doing this is if the machine |
8180 | has a three-operand ADD insn that accepts the required operands. | |
32131a9c RK |
8181 | |
8182 | The simplest approach is to try to generate such an insn and see if it | |
8183 | is recognized and matches its constraints. If so, it can be used. | |
8184 | ||
8185 | It might be better not to actually emit the insn unless it is valid, | |
0009eff2 | 8186 | but we need to pass the insn as an operand to `recog' and |
0eadeb15 | 8187 | `extract_insn' and it is simpler to emit and then delete the insn if |
0009eff2 | 8188 | not valid than to dummy things up. */ |
a8fdc208 | 8189 | |
af929c62 | 8190 | rtx op0, op1, tem, insn; |
32131a9c | 8191 | int code; |
a8fdc208 | 8192 | |
af929c62 RK |
8193 | op0 = find_replacement (&XEXP (in, 0)); |
8194 | op1 = find_replacement (&XEXP (in, 1)); | |
8195 | ||
32131a9c RK |
8196 | /* Since constraint checking is strict, commutativity won't be |
8197 | checked, so we need to do that here to avoid spurious failure | |
8198 | if the add instruction is two-address and the second operand | |
8199 | of the add is the same as the reload reg, which is frequently | |
8200 | the case. If the insn would be A = B + A, rearrange it so | |
0f41302f | 8201 | it will be A = A + B as constrain_operands expects. */ |
a8fdc208 | 8202 | |
f8cfc6aa | 8203 | if (REG_P (XEXP (in, 1)) |
5e03c156 | 8204 | && REGNO (out) == REGNO (XEXP (in, 1))) |
af929c62 RK |
8205 | tem = op0, op0 = op1, op1 = tem; |
8206 | ||
8207 | if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) | |
38a448ca | 8208 | in = gen_rtx_PLUS (GET_MODE (in), op0, op1); |
32131a9c | 8209 | |
ff0d9879 HPN |
8210 | insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in)); |
8211 | if (insn) | |
8212 | return insn; | |
32131a9c RK |
8213 | |
8214 | /* If that failed, we must use a conservative two-insn sequence. | |
09522f21 FS |
8215 | |
8216 | Use a move to copy one operand into the reload register. Prefer | |
8217 | to reload a constant, MEM or pseudo since the move patterns can | |
8218 | handle an arbitrary operand. If OP1 is not a constant, MEM or | |
8219 | pseudo and OP1 is not a valid operand for an add instruction, then | |
8220 | reload OP1. | |
8221 | ||
8222 | After reloading one of the operands into the reload register, add | |
8223 | the reload register to the output register. | |
32131a9c RK |
8224 | |
8225 | If there is another way to do this for a specific machine, a | |
8226 | DEFINE_PEEPHOLE should be specified that recognizes the sequence | |
8227 | we emit below. */ | |
8228 | ||
166cdb08 | 8229 | code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code; |
09522f21 | 8230 | |
3c0cb5de | 8231 | if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG |
f8cfc6aa | 8232 | || (REG_P (op1) |
09522f21 FS |
8233 | && REGNO (op1) >= FIRST_PSEUDO_REGISTER) |
8234 | || (code != CODE_FOR_nothing | |
a995e389 RH |
8235 | && ! ((*insn_data[code].operand[2].predicate) |
8236 | (op1, insn_data[code].operand[2].mode)))) | |
af929c62 | 8237 | tem = op0, op0 = op1, op1 = tem; |
32131a9c | 8238 | |
5c6b1bd2 | 8239 | gen_reload (out, op0, opnum, type); |
39b56c2a | 8240 | |
5e03c156 | 8241 | /* If OP0 and OP1 are the same, we can use OUT for OP1. |
39b56c2a RK |
8242 | This fixes a problem on the 32K where the stack pointer cannot |
8243 | be used as an operand of an add insn. */ | |
8244 | ||
8245 | if (rtx_equal_p (op0, op1)) | |
5e03c156 | 8246 | op1 = out; |
39b56c2a | 8247 | |
ff0d9879 HPN |
8248 | insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1)); |
8249 | if (insn) | |
c77c9766 | 8250 | { |
ff0d9879 | 8251 | /* Add a REG_EQUIV note so that find_equiv_reg can find it. */ |
a31830a7 | 8252 | set_unique_reg_note (insn, REG_EQUIV, in); |
ff0d9879 | 8253 | return insn; |
c77c9766 RK |
8254 | } |
8255 | ||
ff0d9879 HPN |
8256 | /* If that failed, copy the address register to the reload register. |
8257 | Then add the constant to the reload register. */ | |
c77c9766 | 8258 | |
8c74fb06 | 8259 | gcc_assert (!reg_overlap_mentioned_p (out, op0)); |
5c6b1bd2 | 8260 | gen_reload (out, op1, opnum, type); |
4117a96b | 8261 | insn = emit_insn (gen_add2_insn (out, op0)); |
a31830a7 | 8262 | set_unique_reg_note (insn, REG_EQUIV, in); |
32131a9c RK |
8263 | } |
8264 | ||
0dadecf6 RK |
8265 | #ifdef SECONDARY_MEMORY_NEEDED |
8266 | /* If we need a memory location to do the move, do it that way. */ | |
d47c3b4e AP |
8267 | else if ((REG_P (in) |
8268 | || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in)))) | |
344b78b8 | 8269 | && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER |
d47c3b4e AP |
8270 | && (REG_P (out) |
8271 | || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out)))) | |
344b78b8 JH |
8272 | && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER |
8273 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)), | |
8274 | REGNO_REG_CLASS (reg_or_subregno (out)), | |
5e03c156 | 8275 | GET_MODE (out))) |
0dadecf6 RK |
8276 | { |
8277 | /* Get the memory to use and rewrite both registers to its mode. */ | |
5e03c156 | 8278 | rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type); |
0dadecf6 | 8279 | |
5e03c156 | 8280 | if (GET_MODE (loc) != GET_MODE (out)) |
38a448ca | 8281 | out = gen_rtx_REG (GET_MODE (loc), REGNO (out)); |
0dadecf6 RK |
8282 | |
8283 | if (GET_MODE (loc) != GET_MODE (in)) | |
38a448ca | 8284 | in = gen_rtx_REG (GET_MODE (loc), REGNO (in)); |
0dadecf6 | 8285 | |
5c6b1bd2 RK |
8286 | gen_reload (loc, in, opnum, type); |
8287 | gen_reload (out, loc, opnum, type); | |
0dadecf6 RK |
8288 | } |
8289 | #endif | |
ff0d9879 HPN |
8290 | else if (REG_P (out) && UNARY_P (in)) |
8291 | { | |
8292 | rtx insn; | |
8293 | rtx op1; | |
8294 | rtx out_moded; | |
8295 | rtx set; | |
0dadecf6 | 8296 | |
d0ab13fd R |
8297 | op1 = find_replacement (&XEXP (in, 0)); |
8298 | if (op1 != XEXP (in, 0)) | |
8299 | in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1); | |
8300 | ||
ff0d9879 HPN |
8301 | /* First, try a plain SET. */ |
8302 | set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in)); | |
8303 | if (set) | |
8304 | return set; | |
8305 | ||
8306 | /* If that failed, move the inner operand to the reload | |
8307 | register, and try the same unop with the inner expression | |
8308 | replaced with the reload register. */ | |
ff0d9879 HPN |
8309 | |
8310 | if (GET_MODE (op1) != GET_MODE (out)) | |
8311 | out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out)); | |
8312 | else | |
8313 | out_moded = out; | |
8314 | ||
8315 | gen_reload (out_moded, op1, opnum, type); | |
8316 | ||
8317 | insn | |
8318 | = gen_rtx_SET (VOIDmode, out, | |
8319 | gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), | |
8320 | out_moded)); | |
8321 | insn = emit_insn_if_valid_for_reload (insn); | |
8322 | if (insn) | |
8323 | { | |
a31830a7 | 8324 | set_unique_reg_note (insn, REG_EQUIV, in); |
ff0d9879 HPN |
8325 | return insn; |
8326 | } | |
8327 | ||
8328 | fatal_insn ("Failure trying to reload:", set); | |
8329 | } | |
32131a9c | 8330 | /* If IN is a simple operand, use gen_move_insn. */ |
ec8e098d | 8331 | else if (OBJECT_P (in) || GET_CODE (in) == SUBREG) |
8c339083 RS |
8332 | { |
8333 | tem = emit_insn (gen_move_insn (out, in)); | |
cf7c4aa6 | 8334 | /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */ |
8c339083 RS |
8335 | mark_jump_label (in, tem, 0); |
8336 | } | |
32131a9c RK |
8337 | |
8338 | #ifdef HAVE_reload_load_address | |
8339 | else if (HAVE_reload_load_address) | |
5e03c156 | 8340 | emit_insn (gen_reload_load_address (out, in)); |
32131a9c RK |
8341 | #endif |
8342 | ||
5e03c156 | 8343 | /* Otherwise, just write (set OUT IN) and hope for the best. */ |
32131a9c | 8344 | else |
38a448ca | 8345 | emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
32131a9c RK |
8346 | |
8347 | /* Return the first insn emitted. | |
546b63fb | 8348 | We can not just return get_last_insn, because there may have |
32131a9c RK |
8349 | been multiple instructions emitted. Also note that gen_move_insn may |
8350 | emit more than one insn itself, so we can not assume that there is one | |
8351 | insn emitted per emit_insn_before call. */ | |
8352 | ||
546b63fb | 8353 | return last ? NEXT_INSN (last) : get_insns (); |
32131a9c RK |
8354 | } |
8355 | \f | |
cda94cbb RH |
8356 | /* Delete a previously made output-reload whose result we now believe |
8357 | is not needed. First we double-check. | |
32131a9c RK |
8358 | |
8359 | INSN is the insn now being processed. | |
cb2afeb3 R |
8360 | LAST_RELOAD_REG is the hard register number for which we want to delete |
8361 | the last output reload. | |
8362 | J is the reload-number that originally used REG. The caller has made | |
fb959f72 RS |
8363 | certain that reload J doesn't use REG any longer for input. |
8364 | NEW_RELOAD_REG is reload register that reload J is using for REG. */ | |
32131a9c RK |
8365 | |
8366 | static void | |
fb959f72 | 8367 | delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg) |
32131a9c | 8368 | { |
cb2afeb3 R |
8369 | rtx output_reload_insn = spill_reg_store[last_reload_reg]; |
8370 | rtx reg = spill_reg_stored_to[last_reload_reg]; | |
8371 | int k; | |
8372 | int n_occurrences; | |
8373 | int n_inherited = 0; | |
b3694847 | 8374 | rtx i1; |
cb2afeb3 | 8375 | rtx substed; |
05d10675 | 8376 | |
068f5dea JH |
8377 | /* It is possible that this reload has been only used to set another reload |
8378 | we eliminated earlier and thus deleted this instruction too. */ | |
8379 | if (INSN_DELETED_P (output_reload_insn)) | |
8380 | return; | |
8381 | ||
32131a9c RK |
8382 | /* Get the raw pseudo-register referred to. */ |
8383 | ||
32131a9c RK |
8384 | while (GET_CODE (reg) == SUBREG) |
8385 | reg = SUBREG_REG (reg); | |
cb2afeb3 R |
8386 | substed = reg_equiv_memory_loc[REGNO (reg)]; |
8387 | ||
8388 | /* This is unsafe if the operand occurs more often in the current | |
8389 | insn than it is inherited. */ | |
8390 | for (k = n_reloads - 1; k >= 0; k--) | |
8391 | { | |
eceef4c9 | 8392 | rtx reg2 = rld[k].in; |
cb2afeb3 R |
8393 | if (! reg2) |
8394 | continue; | |
3c0cb5de | 8395 | if (MEM_P (reg2) || reload_override_in[k]) |
eceef4c9 | 8396 | reg2 = rld[k].in_reg; |
cb2afeb3 | 8397 | #ifdef AUTO_INC_DEC |
eceef4c9 BS |
8398 | if (rld[k].out && ! rld[k].out_reg) |
8399 | reg2 = XEXP (rld[k].in_reg, 0); | |
cb2afeb3 R |
8400 | #endif |
8401 | while (GET_CODE (reg2) == SUBREG) | |
8402 | reg2 = SUBREG_REG (reg2); | |
8403 | if (rtx_equal_p (reg2, reg)) | |
2eb6dac7 AS |
8404 | { |
8405 | if (reload_inherited[k] || reload_override_in[k] || k == j) | |
f2eb49dc | 8406 | n_inherited++; |
2eb6dac7 AS |
8407 | else |
8408 | return; | |
8409 | } | |
cb2afeb3 | 8410 | } |
4b983fdc | 8411 | n_occurrences = count_occurrences (PATTERN (insn), reg, 0); |
2372a062 BS |
8412 | if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn)) |
8413 | n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn), | |
8414 | reg, 0); | |
cb2afeb3 | 8415 | if (substed) |
5d7ef82a BS |
8416 | n_occurrences += count_occurrences (PATTERN (insn), |
8417 | eliminate_regs (substed, 0, | |
8418 | NULL_RTX), 0); | |
058e97ec | 8419 | for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1)) |
3f1e3e70 AO |
8420 | { |
8421 | gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed)); | |
8422 | n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0); | |
8423 | } | |
cb2afeb3 R |
8424 | if (n_occurrences > n_inherited) |
8425 | return; | |
32131a9c RK |
8426 | |
8427 | /* If the pseudo-reg we are reloading is no longer referenced | |
8428 | anywhere between the store into it and here, | |
0149f412 HPN |
8429 | and we're within the same basic block, then the value can only |
8430 | pass through the reload reg and end up here. | |
32131a9c RK |
8431 | Otherwise, give up--return. */ |
8432 | for (i1 = NEXT_INSN (output_reload_insn); | |
8433 | i1 != insn; i1 = NEXT_INSN (i1)) | |
8434 | { | |
0149f412 | 8435 | if (NOTE_INSN_BASIC_BLOCK_P (i1)) |
32131a9c | 8436 | return; |
4b4bf941 | 8437 | if ((NONJUMP_INSN_P (i1) || CALL_P (i1)) |
32131a9c | 8438 | && reg_mentioned_p (reg, PATTERN (i1))) |
aa6498c2 | 8439 | { |
cb2afeb3 R |
8440 | /* If this is USE in front of INSN, we only have to check that |
8441 | there are no more references than accounted for by inheritance. */ | |
4b4bf941 | 8442 | while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE) |
aa6498c2 | 8443 | { |
cb2afeb3 | 8444 | n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0; |
aa6498c2 R |
8445 | i1 = NEXT_INSN (i1); |
8446 | } | |
cb2afeb3 | 8447 | if (n_occurrences <= n_inherited && i1 == insn) |
aa6498c2 R |
8448 | break; |
8449 | return; | |
8450 | } | |
32131a9c RK |
8451 | } |
8452 | ||
cda94cbb | 8453 | /* We will be deleting the insn. Remove the spill reg information. */ |
66fd46b6 | 8454 | for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; ) |
cda94cbb RH |
8455 | { |
8456 | spill_reg_store[last_reload_reg + k] = 0; | |
8457 | spill_reg_stored_to[last_reload_reg + k] = 0; | |
8458 | } | |
8459 | ||
aa6498c2 | 8460 | /* The caller has already checked that REG dies or is set in INSN. |
cda94cbb | 8461 | It has also checked that we are optimizing, and thus some |
14b493d6 | 8462 | inaccuracies in the debugging information are acceptable. |
cda94cbb RH |
8463 | So we could just delete output_reload_insn. But in some cases |
8464 | we can improve the debugging information without sacrificing | |
8465 | optimization - maybe even improving the code: See if the pseudo | |
8466 | reg has been completely replaced with reload regs. If so, delete | |
8467 | the store insn and forget we had a stack slot for the pseudo. */ | |
eceef4c9 | 8468 | if (rld[j].out != rld[j].in |
aa6498c2 | 8469 | && REG_N_DEATHS (REGNO (reg)) == 1 |
a3a24aa6 | 8470 | && REG_N_SETS (REGNO (reg)) == 1 |
6fb5fa3c | 8471 | && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS |
aa6498c2 | 8472 | && find_regno_note (insn, REG_DEAD, REGNO (reg))) |
32131a9c | 8473 | { |
ba4807a0 | 8474 | rtx i2; |
32131a9c | 8475 | |
cda94cbb RH |
8476 | /* We know that it was used only between here and the beginning of |
8477 | the current basic block. (We also know that the last use before | |
8478 | INSN was the output reload we are thinking of deleting, but never | |
8479 | mind that.) Search that range; see if any ref remains. */ | |
ba4807a0 | 8480 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) |
32131a9c | 8481 | { |
ba4807a0 | 8482 | rtx set = single_set (i2); |
d445b551 | 8483 | |
32131a9c RK |
8484 | /* Uses which just store in the pseudo don't count, |
8485 | since if they are the only uses, they are dead. */ | |
d445b551 | 8486 | if (set != 0 && SET_DEST (set) == reg) |
32131a9c | 8487 | continue; |
4b4bf941 JQ |
8488 | if (LABEL_P (i2) |
8489 | || JUMP_P (i2)) | |
32131a9c | 8490 | break; |
4b4bf941 | 8491 | if ((NONJUMP_INSN_P (i2) || CALL_P (i2)) |
32131a9c | 8492 | && reg_mentioned_p (reg, PATTERN (i2))) |
aa6498c2 R |
8493 | { |
8494 | /* Some other ref remains; just delete the output reload we | |
8495 | know to be dead. */ | |
cb2afeb3 | 8496 | delete_address_reloads (output_reload_insn, insn); |
ca6c03ca | 8497 | delete_insn (output_reload_insn); |
aa6498c2 R |
8498 | return; |
8499 | } | |
32131a9c RK |
8500 | } |
8501 | ||
cda94cbb RH |
8502 | /* Delete the now-dead stores into this pseudo. Note that this |
8503 | loop also takes care of deleting output_reload_insn. */ | |
ba4807a0 | 8504 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) |
32131a9c | 8505 | { |
ba4807a0 | 8506 | rtx set = single_set (i2); |
d445b551 RK |
8507 | |
8508 | if (set != 0 && SET_DEST (set) == reg) | |
5507b94b | 8509 | { |
cb2afeb3 | 8510 | delete_address_reloads (i2, insn); |
ca6c03ca | 8511 | delete_insn (i2); |
5507b94b | 8512 | } |
4b4bf941 JQ |
8513 | if (LABEL_P (i2) |
8514 | || JUMP_P (i2)) | |
32131a9c RK |
8515 | break; |
8516 | } | |
8517 | ||
cda94cbb | 8518 | /* For the debugging info, say the pseudo lives in this reload reg. */ |
fb959f72 | 8519 | reg_renumber[REGNO (reg)] = REGNO (new_reload_reg); |
2af2dbdc | 8520 | if (ira_conflicts_p) |
058e97ec VM |
8521 | /* Inform IRA about the change. */ |
8522 | ira_mark_allocation_change (REGNO (reg)); | |
8523 | alter_reg (REGNO (reg), -1, false); | |
32131a9c | 8524 | } |
cda94cbb RH |
8525 | else |
8526 | { | |
8527 | delete_address_reloads (output_reload_insn, insn); | |
8528 | delete_insn (output_reload_insn); | |
8529 | } | |
cb2afeb3 R |
8530 | } |
8531 | ||
8532 | /* We are going to delete DEAD_INSN. Recursively delete loads of | |
8533 | reload registers used in DEAD_INSN that are not used till CURRENT_INSN. | |
8534 | CURRENT_INSN is being reloaded, so we have to check its reloads too. */ | |
8535 | static void | |
0c20a65f | 8536 | delete_address_reloads (rtx dead_insn, rtx current_insn) |
cb2afeb3 R |
8537 | { |
8538 | rtx set = single_set (dead_insn); | |
8539 | rtx set2, dst, prev, next; | |
8540 | if (set) | |
8541 | { | |
8542 | rtx dst = SET_DEST (set); | |
3c0cb5de | 8543 | if (MEM_P (dst)) |
cb2afeb3 R |
8544 | delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn); |
8545 | } | |
8546 | /* If we deleted the store from a reloaded post_{in,de}c expression, | |
8547 | we can delete the matching adds. */ | |
8548 | prev = PREV_INSN (dead_insn); | |
8549 | next = NEXT_INSN (dead_insn); | |
8550 | if (! prev || ! next) | |
8551 | return; | |
8552 | set = single_set (next); | |
8553 | set2 = single_set (prev); | |
8554 | if (! set || ! set2 | |
8555 | || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS | |
8556 | || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT | |
8557 | || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT) | |
8558 | return; | |
8559 | dst = SET_DEST (set); | |
8560 | if (! rtx_equal_p (dst, SET_DEST (set2)) | |
8561 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0)) | |
8562 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0)) | |
8563 | || (INTVAL (XEXP (SET_SRC (set), 1)) | |
1d7254c5 | 8564 | != -INTVAL (XEXP (SET_SRC (set2), 1)))) |
cb2afeb3 | 8565 | return; |
53c17031 JH |
8566 | delete_related_insns (prev); |
8567 | delete_related_insns (next); | |
cb2afeb3 R |
8568 | } |
8569 | ||
8570 | /* Subfunction of delete_address_reloads: process registers found in X. */ | |
8571 | static void | |
0c20a65f | 8572 | delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn) |
cb2afeb3 R |
8573 | { |
8574 | rtx prev, set, dst, i2; | |
8575 | int i, j; | |
8576 | enum rtx_code code = GET_CODE (x); | |
8577 | ||
8578 | if (code != REG) | |
8579 | { | |
1d7254c5 | 8580 | const char *fmt = GET_RTX_FORMAT (code); |
cb2afeb3 R |
8581 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
8582 | { | |
8583 | if (fmt[i] == 'e') | |
8584 | delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn); | |
8585 | else if (fmt[i] == 'E') | |
8586 | { | |
1d7254c5 | 8587 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
cb2afeb3 R |
8588 | delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j), |
8589 | current_insn); | |
8590 | } | |
8591 | } | |
8592 | return; | |
8593 | } | |
8594 | ||
8595 | if (spill_reg_order[REGNO (x)] < 0) | |
8596 | return; | |
aa6498c2 | 8597 | |
cb2afeb3 R |
8598 | /* Scan backwards for the insn that sets x. This might be a way back due |
8599 | to inheritance. */ | |
8600 | for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev)) | |
8601 | { | |
8602 | code = GET_CODE (prev); | |
8603 | if (code == CODE_LABEL || code == JUMP_INSN) | |
8604 | return; | |
ec8e098d | 8605 | if (!INSN_P (prev)) |
cb2afeb3 R |
8606 | continue; |
8607 | if (reg_set_p (x, PATTERN (prev))) | |
8608 | break; | |
8609 | if (reg_referenced_p (x, PATTERN (prev))) | |
8610 | return; | |
8611 | } | |
8612 | if (! prev || INSN_UID (prev) < reload_first_uid) | |
8613 | return; | |
8614 | /* Check that PREV only sets the reload register. */ | |
8615 | set = single_set (prev); | |
8616 | if (! set) | |
8617 | return; | |
8618 | dst = SET_DEST (set); | |
f8cfc6aa | 8619 | if (!REG_P (dst) |
cb2afeb3 R |
8620 | || ! rtx_equal_p (dst, x)) |
8621 | return; | |
8622 | if (! reg_set_p (dst, PATTERN (dead_insn))) | |
8623 | { | |
8624 | /* Check if DST was used in a later insn - | |
8625 | it might have been inherited. */ | |
8626 | for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2)) | |
8627 | { | |
4b4bf941 | 8628 | if (LABEL_P (i2)) |
cb2afeb3 | 8629 | break; |
2c3c49de | 8630 | if (! INSN_P (i2)) |
cb2afeb3 R |
8631 | continue; |
8632 | if (reg_referenced_p (dst, PATTERN (i2))) | |
8633 | { | |
8634 | /* If there is a reference to the register in the current insn, | |
8635 | it might be loaded in a non-inherited reload. If no other | |
8636 | reload uses it, that means the register is set before | |
8637 | referenced. */ | |
8638 | if (i2 == current_insn) | |
8639 | { | |
8640 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 8641 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
8642 | || reload_override_in[j] == dst) |
8643 | return; | |
8644 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 8645 | if (rld[j].in && rld[j].reg_rtx == dst) |
cb2afeb3 R |
8646 | break; |
8647 | if (j >= 0) | |
8648 | break; | |
8649 | } | |
8650 | return; | |
8651 | } | |
4b4bf941 | 8652 | if (JUMP_P (i2)) |
cb2afeb3 | 8653 | break; |
cb2afeb3 | 8654 | /* If DST is still live at CURRENT_INSN, check if it is used for |
3900dc09 R |
8655 | any reload. Note that even if CURRENT_INSN sets DST, we still |
8656 | have to check the reloads. */ | |
cb2afeb3 R |
8657 | if (i2 == current_insn) |
8658 | { | |
8659 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 8660 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
8661 | || reload_override_in[j] == dst) |
8662 | return; | |
8663 | /* ??? We can't finish the loop here, because dst might be | |
8664 | allocated to a pseudo in this block if no reload in this | |
14b493d6 | 8665 | block needs any of the classes containing DST - see |
cb2afeb3 R |
8666 | spill_hard_reg. There is no easy way to tell this, so we |
8667 | have to scan till the end of the basic block. */ | |
8668 | } | |
3900dc09 R |
8669 | if (reg_set_p (dst, PATTERN (i2))) |
8670 | break; | |
cb2afeb3 R |
8671 | } |
8672 | } | |
8673 | delete_address_reloads_1 (prev, SET_SRC (set), current_insn); | |
8674 | reg_reloaded_contents[REGNO (dst)] = -1; | |
ca6c03ca | 8675 | delete_insn (prev); |
32131a9c | 8676 | } |
32131a9c | 8677 | \f |
a8fdc208 | 8678 | /* Output reload-insns to reload VALUE into RELOADREG. |
858a47b1 | 8679 | VALUE is an autoincrement or autodecrement RTX whose operand |
32131a9c RK |
8680 | is a register or memory location; |
8681 | so reloading involves incrementing that location. | |
cb2afeb3 | 8682 | IN is either identical to VALUE, or some cheaper place to reload from. |
32131a9c RK |
8683 | |
8684 | INC_AMOUNT is the number to increment or decrement by (always positive). | |
cb2afeb3 | 8685 | This cannot be deduced from VALUE. |
32131a9c | 8686 | |
cb2afeb3 R |
8687 | Return the instruction that stores into RELOADREG. */ |
8688 | ||
8689 | static rtx | |
0c20a65f | 8690 | inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount) |
32131a9c RK |
8691 | { |
8692 | /* REG or MEM to be copied and incremented. */ | |
4b7b277a | 8693 | rtx incloc = find_replacement (&XEXP (value, 0)); |
32131a9c | 8694 | /* Nonzero if increment after copying. */ |
67f07489 PB |
8695 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC |
8696 | || GET_CODE (value) == POST_MODIFY); | |
546b63fb | 8697 | rtx last; |
0009eff2 RK |
8698 | rtx inc; |
8699 | rtx add_insn; | |
8700 | int code; | |
cb2afeb3 | 8701 | rtx store; |
4b7b277a | 8702 | rtx real_in = in == value ? incloc : in; |
32131a9c RK |
8703 | |
8704 | /* No hard register is equivalent to this register after | |
40f03658 | 8705 | inc/dec operation. If REG_LAST_RELOAD_REG were nonzero, |
32131a9c RK |
8706 | we could inc/dec that register as well (maybe even using it for |
8707 | the source), but I'm not sure it's worth worrying about. */ | |
f8cfc6aa | 8708 | if (REG_P (incloc)) |
32131a9c RK |
8709 | reg_last_reload_reg[REGNO (incloc)] = 0; |
8710 | ||
67f07489 PB |
8711 | if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) |
8712 | { | |
8713 | gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS); | |
4b7b277a | 8714 | inc = find_replacement (&XEXP (XEXP (value, 1), 1)); |
67f07489 PB |
8715 | } |
8716 | else | |
8717 | { | |
8718 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
8719 | inc_amount = -inc_amount; | |
32131a9c | 8720 | |
67f07489 PB |
8721 | inc = GEN_INT (inc_amount); |
8722 | } | |
0009eff2 RK |
8723 | |
8724 | /* If this is post-increment, first copy the location to the reload reg. */ | |
cb2afeb3 R |
8725 | if (post && real_in != reloadreg) |
8726 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
0009eff2 | 8727 | |
cb2afeb3 R |
8728 | if (in == value) |
8729 | { | |
8730 | /* See if we can directly increment INCLOC. Use a method similar to | |
8731 | that in gen_reload. */ | |
0009eff2 | 8732 | |
cb2afeb3 R |
8733 | last = get_last_insn (); |
8734 | add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc, | |
8735 | gen_rtx_PLUS (GET_MODE (incloc), | |
8736 | incloc, inc))); | |
05d10675 | 8737 | |
cb2afeb3 R |
8738 | code = recog_memoized (add_insn); |
8739 | if (code >= 0) | |
32131a9c | 8740 | { |
0eadeb15 BS |
8741 | extract_insn (add_insn); |
8742 | if (constrain_operands (1)) | |
cb2afeb3 R |
8743 | { |
8744 | /* If this is a pre-increment and we have incremented the value | |
8745 | where it lives, copy the incremented value to RELOADREG to | |
8746 | be used as an address. */ | |
0009eff2 | 8747 | |
cb2afeb3 R |
8748 | if (! post) |
8749 | emit_insn (gen_move_insn (reloadreg, incloc)); | |
546b63fb | 8750 | |
cb2afeb3 R |
8751 | return add_insn; |
8752 | } | |
32131a9c | 8753 | } |
cb2afeb3 | 8754 | delete_insns_since (last); |
32131a9c | 8755 | } |
0009eff2 | 8756 | |
0009eff2 RK |
8757 | /* If couldn't do the increment directly, must increment in RELOADREG. |
8758 | The way we do this depends on whether this is pre- or post-increment. | |
8759 | For pre-increment, copy INCLOC to the reload register, increment it | |
8760 | there, then save back. */ | |
8761 | ||
8762 | if (! post) | |
8763 | { | |
cb2afeb3 R |
8764 | if (in != reloadreg) |
8765 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
546b63fb | 8766 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 8767 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
0009eff2 | 8768 | } |
32131a9c RK |
8769 | else |
8770 | { | |
0009eff2 RK |
8771 | /* Postincrement. |
8772 | Because this might be a jump insn or a compare, and because RELOADREG | |
8773 | may not be available after the insn in an input reload, we must do | |
8774 | the incrementation before the insn being reloaded for. | |
8775 | ||
cb2afeb3 | 8776 | We have already copied IN to RELOADREG. Increment the copy in |
0009eff2 RK |
8777 | RELOADREG, save that back, then decrement RELOADREG so it has |
8778 | the original value. */ | |
8779 | ||
546b63fb | 8780 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 8781 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
67f07489 | 8782 | if (GET_CODE (inc) == CONST_INT) |
247140ea | 8783 | emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc)))); |
67f07489 PB |
8784 | else |
8785 | emit_insn (gen_sub2_insn (reloadreg, inc)); | |
32131a9c | 8786 | } |
0009eff2 | 8787 | |
cb2afeb3 | 8788 | return store; |
32131a9c RK |
8789 | } |
8790 | \f | |
2dfa9a87 MH |
8791 | #ifdef AUTO_INC_DEC |
8792 | static void | |
0c20a65f | 8793 | add_auto_inc_notes (rtx insn, rtx x) |
2dfa9a87 MH |
8794 | { |
8795 | enum rtx_code code = GET_CODE (x); | |
6f7d635c | 8796 | const char *fmt; |
2dfa9a87 MH |
8797 | int i, j; |
8798 | ||
8799 | if (code == MEM && auto_inc_p (XEXP (x, 0))) | |
8800 | { | |
65c5f2a6 | 8801 | add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0)); |
2dfa9a87 MH |
8802 | return; |
8803 | } | |
8804 | ||
8805 | /* Scan all the operand sub-expressions. */ | |
8806 | fmt = GET_RTX_FORMAT (code); | |
8807 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
8808 | { | |
8809 | if (fmt[i] == 'e') | |
8810 | add_auto_inc_notes (insn, XEXP (x, i)); | |
8811 | else if (fmt[i] == 'E') | |
8812 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
8813 | add_auto_inc_notes (insn, XVECEXP (x, i, j)); | |
8814 | } | |
8815 | } | |
8816 | #endif | |
94bd63e5 AH |
8817 | |
8818 | /* Copy EH notes from an insn to its reloads. */ | |
8819 | static void | |
0c20a65f | 8820 | copy_eh_notes (rtx insn, rtx x) |
94bd63e5 AH |
8821 | { |
8822 | rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
8823 | if (eh_note) | |
8824 | { | |
8825 | for (; x != 0; x = NEXT_INSN (x)) | |
8826 | { | |
8827 | if (may_trap_p (PATTERN (x))) | |
65c5f2a6 | 8828 | add_reg_note (x, REG_EH_REGION, XEXP (eh_note, 0)); |
94bd63e5 AH |
8829 | } |
8830 | } | |
8831 | } | |
8832 | ||
f1330226 JH |
8833 | /* This is used by reload pass, that does emit some instructions after |
8834 | abnormal calls moving basic block end, but in fact it wants to emit | |
8835 | them on the edge. Looks for abnormal call edges, find backward the | |
8836 | proper call and fix the damage. | |
a6a2274a | 8837 | |
f1330226 | 8838 | Similar handle instructions throwing exceptions internally. */ |
068473ec | 8839 | void |
0c20a65f | 8840 | fixup_abnormal_edges (void) |
f1330226 | 8841 | { |
f1330226 | 8842 | bool inserted = false; |
e0082a72 | 8843 | basic_block bb; |
f1330226 | 8844 | |
e0082a72 | 8845 | FOR_EACH_BB (bb) |
f1330226 | 8846 | { |
f1330226 | 8847 | edge e; |
628f6a4e | 8848 | edge_iterator ei; |
f1330226 | 8849 | |
09da1532 | 8850 | /* Look for cases we are interested in - calls or instructions causing |
f1330226 | 8851 | exceptions. */ |
628f6a4e | 8852 | FOR_EACH_EDGE (e, ei, bb->succs) |
f1330226 JH |
8853 | { |
8854 | if (e->flags & EDGE_ABNORMAL_CALL) | |
8855 | break; | |
8856 | if ((e->flags & (EDGE_ABNORMAL | EDGE_EH)) | |
8857 | == (EDGE_ABNORMAL | EDGE_EH)) | |
8858 | break; | |
8859 | } | |
4b4bf941 | 8860 | if (e && !CALL_P (BB_END (bb)) |
a813c111 | 8861 | && !can_throw_internal (BB_END (bb))) |
f1330226 | 8862 | { |
be0c514c RH |
8863 | rtx insn; |
8864 | ||
8865 | /* Get past the new insns generated. Allow notes, as the insns | |
8866 | may be already deleted. */ | |
8867 | insn = BB_END (bb); | |
4b4bf941 | 8868 | while ((NONJUMP_INSN_P (insn) || NOTE_P (insn)) |
39f95a2c | 8869 | && !can_throw_internal (insn) |
a813c111 | 8870 | && insn != BB_HEAD (bb)) |
f1330226 | 8871 | insn = PREV_INSN (insn); |
be0c514c RH |
8872 | |
8873 | if (CALL_P (insn) || can_throw_internal (insn)) | |
f1330226 | 8874 | { |
be0c514c RH |
8875 | rtx stop, next; |
8876 | ||
8877 | stop = NEXT_INSN (BB_END (bb)); | |
8878 | BB_END (bb) = insn; | |
8879 | insn = NEXT_INSN (insn); | |
8880 | ||
8881 | FOR_EACH_EDGE (e, ei, bb->succs) | |
8882 | if (e->flags & EDGE_FALLTHRU) | |
8883 | break; | |
8884 | ||
8885 | while (insn && insn != stop) | |
0c4992b0 | 8886 | { |
be0c514c RH |
8887 | next = NEXT_INSN (insn); |
8888 | if (INSN_P (insn)) | |
ed8d2920 | 8889 | { |
36808d08 | 8890 | delete_insn (insn); |
be0c514c RH |
8891 | |
8892 | /* Sometimes there's still the return value USE. | |
8893 | If it's placed after a trapping call (i.e. that | |
8894 | call is the last insn anyway), we have no fallthru | |
8895 | edge. Simply delete this use and don't try to insert | |
8896 | on the non-existent edge. */ | |
8897 | if (GET_CODE (PATTERN (insn)) != USE) | |
8898 | { | |
8899 | /* We're not deleting it, we're moving it. */ | |
8900 | INSN_DELETED_P (insn) = 0; | |
8901 | PREV_INSN (insn) = NULL_RTX; | |
8902 | NEXT_INSN (insn) = NULL_RTX; | |
f8ed1958 | 8903 | |
be0c514c RH |
8904 | insert_insn_on_edge (insn, e); |
8905 | inserted = true; | |
8906 | } | |
ed8d2920 | 8907 | } |
36808d08 EB |
8908 | else if (!BARRIER_P (insn)) |
8909 | set_block_for_insn (insn, NULL); | |
be0c514c | 8910 | insn = next; |
0c4992b0 | 8911 | } |
f1330226 | 8912 | } |
be0c514c RH |
8913 | |
8914 | /* It may be that we don't find any such trapping insn. In this | |
8915 | case we discovered quite late that the insn that had been | |
8916 | marked as can_throw_internal in fact couldn't trap at all. | |
8917 | So we should in fact delete the EH edges out of the block. */ | |
8918 | else | |
8919 | purge_dead_edges (bb); | |
f1330226 JH |
8920 | } |
8921 | } | |
be0c514c | 8922 | |
b735f45d AK |
8923 | /* We've possibly turned single trapping insn into multiple ones. */ |
8924 | if (flag_non_call_exceptions) | |
8925 | { | |
8926 | sbitmap blocks; | |
8927 | blocks = sbitmap_alloc (last_basic_block); | |
8928 | sbitmap_ones (blocks); | |
8929 | find_many_sub_basic_blocks (blocks); | |
639d3040 | 8930 | sbitmap_free (blocks); |
b735f45d AK |
8931 | } |
8932 | ||
f1330226 JH |
8933 | if (inserted) |
8934 | commit_edge_insertions (); | |
be0c514c RH |
8935 | |
8936 | #ifdef ENABLE_CHECKING | |
8937 | /* Verify that we didn't turn one trapping insn into many, and that | |
8938 | we found and corrected all of the problems wrt fixups on the | |
8939 | fallthru edge. */ | |
8940 | verify_flow_info (); | |
8941 | #endif | |
f1330226 | 8942 | } |