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32131a9c | 1 | /* Reload pseudo regs into hard regs for insns that require hard regs. |
a8efe40d | 2 | Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc. |
32131a9c RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
19 | ||
20 | ||
ff2da9fc | 21 | #include <stdio.h> |
32131a9c RK |
22 | #include "config.h" |
23 | #include "rtl.h" | |
24 | #include "obstack.h" | |
25 | #include "insn-config.h" | |
26 | #include "insn-flags.h" | |
27 | #include "insn-codes.h" | |
28 | #include "flags.h" | |
29 | #include "expr.h" | |
30 | #include "regs.h" | |
31 | #include "hard-reg-set.h" | |
32 | #include "reload.h" | |
33 | #include "recog.h" | |
34 | #include "basic-block.h" | |
35 | #include "output.h" | |
32131a9c RK |
36 | |
37 | /* This file contains the reload pass of the compiler, which is | |
38 | run after register allocation has been done. It checks that | |
39 | each insn is valid (operands required to be in registers really | |
40 | are in registers of the proper class) and fixes up invalid ones | |
41 | by copying values temporarily into registers for the insns | |
42 | that need them. | |
43 | ||
44 | The results of register allocation are described by the vector | |
45 | reg_renumber; the insns still contain pseudo regs, but reg_renumber | |
46 | can be used to find which hard reg, if any, a pseudo reg is in. | |
47 | ||
48 | The technique we always use is to free up a few hard regs that are | |
49 | called ``reload regs'', and for each place where a pseudo reg | |
50 | must be in a hard reg, copy it temporarily into one of the reload regs. | |
51 | ||
52 | All the pseudos that were formerly allocated to the hard regs that | |
53 | are now in use as reload regs must be ``spilled''. This means | |
54 | that they go to other hard regs, or to stack slots if no other | |
55 | available hard regs can be found. Spilling can invalidate more | |
56 | insns, requiring additional need for reloads, so we must keep checking | |
57 | until the process stabilizes. | |
58 | ||
59 | For machines with different classes of registers, we must keep track | |
60 | of the register class needed for each reload, and make sure that | |
61 | we allocate enough reload registers of each class. | |
62 | ||
63 | The file reload.c contains the code that checks one insn for | |
64 | validity and reports the reloads that it needs. This file | |
65 | is in charge of scanning the entire rtl code, accumulating the | |
66 | reload needs, spilling, assigning reload registers to use for | |
67 | fixing up each insn, and generating the new insns to copy values | |
68 | into the reload registers. */ | |
69 | \f | |
70 | /* During reload_as_needed, element N contains a REG rtx for the hard reg | |
71 | into which pseudo reg N has been reloaded (perhaps for a previous insn). */ | |
72 | static rtx *reg_last_reload_reg; | |
73 | ||
74 | /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn | |
75 | for an output reload that stores into reg N. */ | |
76 | static char *reg_has_output_reload; | |
77 | ||
78 | /* Indicates which hard regs are reload-registers for an output reload | |
79 | in the current insn. */ | |
80 | static HARD_REG_SET reg_is_output_reload; | |
81 | ||
82 | /* Element N is the constant value to which pseudo reg N is equivalent, | |
83 | or zero if pseudo reg N is not equivalent to a constant. | |
84 | find_reloads looks at this in order to replace pseudo reg N | |
85 | with the constant it stands for. */ | |
86 | rtx *reg_equiv_constant; | |
87 | ||
88 | /* Element N is a memory location to which pseudo reg N is equivalent, | |
89 | prior to any register elimination (such as frame pointer to stack | |
90 | pointer). Depending on whether or not it is a valid address, this value | |
91 | is transferred to either reg_equiv_address or reg_equiv_mem. */ | |
4803a34a | 92 | rtx *reg_equiv_memory_loc; |
32131a9c RK |
93 | |
94 | /* Element N is the address of stack slot to which pseudo reg N is equivalent. | |
95 | This is used when the address is not valid as a memory address | |
96 | (because its displacement is too big for the machine.) */ | |
97 | rtx *reg_equiv_address; | |
98 | ||
99 | /* Element N is the memory slot to which pseudo reg N is equivalent, | |
100 | or zero if pseudo reg N is not equivalent to a memory slot. */ | |
101 | rtx *reg_equiv_mem; | |
102 | ||
103 | /* Widest width in which each pseudo reg is referred to (via subreg). */ | |
104 | static int *reg_max_ref_width; | |
105 | ||
106 | /* Element N is the insn that initialized reg N from its equivalent | |
107 | constant or memory slot. */ | |
108 | static rtx *reg_equiv_init; | |
109 | ||
110 | /* During reload_as_needed, element N contains the last pseudo regno | |
111 | reloaded into the Nth reload register. This vector is in parallel | |
112 | with spill_regs. If that pseudo reg occupied more than one register, | |
113 | reg_reloaded_contents points to that pseudo for each spill register in | |
114 | use; all of these must remain set for an inheritance to occur. */ | |
115 | static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; | |
116 | ||
117 | /* During reload_as_needed, element N contains the insn for which | |
118 | the Nth reload register was last used. This vector is in parallel | |
119 | with spill_regs, and its contents are significant only when | |
120 | reg_reloaded_contents is significant. */ | |
121 | static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; | |
122 | ||
123 | /* Number of spill-regs so far; number of valid elements of spill_regs. */ | |
124 | static int n_spills; | |
125 | ||
126 | /* In parallel with spill_regs, contains REG rtx's for those regs. | |
127 | Holds the last rtx used for any given reg, or 0 if it has never | |
128 | been used for spilling yet. This rtx is reused, provided it has | |
129 | the proper mode. */ | |
130 | static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
131 | ||
132 | /* In parallel with spill_regs, contains nonzero for a spill reg | |
133 | that was stored after the last time it was used. | |
134 | The precise value is the insn generated to do the store. */ | |
135 | static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
136 | ||
137 | /* This table is the inverse mapping of spill_regs: | |
138 | indexed by hard reg number, | |
139 | it contains the position of that reg in spill_regs, | |
140 | or -1 for something that is not in spill_regs. */ | |
141 | static short spill_reg_order[FIRST_PSEUDO_REGISTER]; | |
142 | ||
143 | /* This reg set indicates registers that may not be used for retrying global | |
144 | allocation. The registers that may not be used include all spill registers | |
145 | and the frame pointer (if we are using one). */ | |
146 | HARD_REG_SET forbidden_regs; | |
147 | ||
148 | /* This reg set indicates registers that are not good for spill registers. | |
149 | They will not be used to complete groups of spill registers. This includes | |
150 | all fixed registers, registers that may be eliminated, and registers | |
151 | explicitly used in the rtl. | |
152 | ||
153 | (spill_reg_order prevents these registers from being used to start a | |
154 | group.) */ | |
155 | static HARD_REG_SET bad_spill_regs; | |
156 | ||
157 | /* Describes order of use of registers for reloading | |
158 | of spilled pseudo-registers. `spills' is the number of | |
159 | elements that are actually valid; new ones are added at the end. */ | |
160 | static short spill_regs[FIRST_PSEUDO_REGISTER]; | |
161 | ||
162 | /* Describes order of preference for putting regs into spill_regs. | |
163 | Contains the numbers of all the hard regs, in order most preferred first. | |
164 | This order is different for each function. | |
165 | It is set up by order_regs_for_reload. | |
166 | Empty elements at the end contain -1. */ | |
167 | static short potential_reload_regs[FIRST_PSEUDO_REGISTER]; | |
168 | ||
169 | /* 1 for a hard register that appears explicitly in the rtl | |
170 | (for example, function value registers, special registers | |
171 | used by insns, structure value pointer registers). */ | |
172 | static char regs_explicitly_used[FIRST_PSEUDO_REGISTER]; | |
173 | ||
174 | /* Indicates if a register was counted against the need for | |
175 | groups. 0 means it can count against max_nongroup instead. */ | |
176 | static HARD_REG_SET counted_for_groups; | |
177 | ||
178 | /* Indicates if a register was counted against the need for | |
179 | non-groups. 0 means it can become part of a new group. | |
180 | During choose_reload_regs, 1 here means don't use this reg | |
181 | as part of a group, even if it seems to be otherwise ok. */ | |
182 | static HARD_REG_SET counted_for_nongroups; | |
183 | ||
184 | /* Nonzero if indirect addressing is supported on the machine; this means | |
185 | that spilling (REG n) does not require reloading it into a register in | |
186 | order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The | |
187 | value indicates the level of indirect addressing supported, e.g., two | |
188 | means that (MEM (MEM (REG n))) is also valid if (REG n) does not get | |
189 | a hard register. */ | |
190 | ||
191 | static char spill_indirect_levels; | |
192 | ||
193 | /* Nonzero if indirect addressing is supported when the innermost MEM is | |
194 | of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to | |
195 | which these are valid is the same as spill_indirect_levels, above. */ | |
196 | ||
197 | char indirect_symref_ok; | |
198 | ||
199 | /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ | |
200 | ||
201 | char double_reg_address_ok; | |
202 | ||
203 | /* Record the stack slot for each spilled hard register. */ | |
204 | ||
205 | static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; | |
206 | ||
207 | /* Width allocated so far for that stack slot. */ | |
208 | ||
209 | static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; | |
210 | ||
211 | /* Indexed by register class and basic block number, nonzero if there is | |
212 | any need for a spill register of that class in that basic block. | |
213 | The pointer is 0 if we did stupid allocation and don't know | |
214 | the structure of basic blocks. */ | |
215 | ||
216 | char *basic_block_needs[N_REG_CLASSES]; | |
217 | ||
218 | /* First uid used by insns created by reload in this function. | |
219 | Used in find_equiv_reg. */ | |
220 | int reload_first_uid; | |
221 | ||
222 | /* Flag set by local-alloc or global-alloc if anything is live in | |
223 | a call-clobbered reg across calls. */ | |
224 | ||
225 | int caller_save_needed; | |
226 | ||
227 | /* Set to 1 while reload_as_needed is operating. | |
228 | Required by some machines to handle any generated moves differently. */ | |
229 | ||
230 | int reload_in_progress = 0; | |
231 | ||
232 | /* These arrays record the insn_code of insns that may be needed to | |
233 | perform input and output reloads of special objects. They provide a | |
234 | place to pass a scratch register. */ | |
235 | ||
236 | enum insn_code reload_in_optab[NUM_MACHINE_MODES]; | |
237 | enum insn_code reload_out_optab[NUM_MACHINE_MODES]; | |
238 | ||
d45cf215 | 239 | /* This obstack is used for allocation of rtl during register elimination. |
32131a9c RK |
240 | The allocated storage can be freed once find_reloads has processed the |
241 | insn. */ | |
242 | ||
243 | struct obstack reload_obstack; | |
244 | char *reload_firstobj; | |
245 | ||
246 | #define obstack_chunk_alloc xmalloc | |
247 | #define obstack_chunk_free free | |
248 | ||
32131a9c RK |
249 | /* List of labels that must never be deleted. */ |
250 | extern rtx forced_labels; | |
251 | \f | |
252 | /* This structure is used to record information about register eliminations. | |
253 | Each array entry describes one possible way of eliminating a register | |
254 | in favor of another. If there is more than one way of eliminating a | |
255 | particular register, the most preferred should be specified first. */ | |
256 | ||
257 | static struct elim_table | |
258 | { | |
259 | int from; /* Register number to be eliminated. */ | |
260 | int to; /* Register number used as replacement. */ | |
261 | int initial_offset; /* Initial difference between values. */ | |
262 | int can_eliminate; /* Non-zero if this elimination can be done. */ | |
263 | int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over | |
264 | insns made by reload. */ | |
265 | int offset; /* Current offset between the two regs. */ | |
a8efe40d | 266 | int max_offset; /* Maximum offset between the two regs. */ |
32131a9c RK |
267 | int previous_offset; /* Offset at end of previous insn. */ |
268 | int ref_outside_mem; /* "to" has been referenced outside a MEM. */ | |
269 | rtx from_rtx; /* REG rtx for the register to be eliminated. | |
270 | We cannot simply compare the number since | |
271 | we might then spuriously replace a hard | |
272 | register corresponding to a pseudo | |
273 | assigned to the reg to be eliminated. */ | |
274 | rtx to_rtx; /* REG rtx for the replacement. */ | |
275 | } reg_eliminate[] = | |
276 | ||
277 | /* If a set of eliminable registers was specified, define the table from it. | |
278 | Otherwise, default to the normal case of the frame pointer being | |
279 | replaced by the stack pointer. */ | |
280 | ||
281 | #ifdef ELIMINABLE_REGS | |
282 | ELIMINABLE_REGS; | |
283 | #else | |
284 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; | |
285 | #endif | |
286 | ||
287 | #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0]) | |
288 | ||
289 | /* Record the number of pending eliminations that have an offset not equal | |
290 | to their initial offset. If non-zero, we use a new copy of each | |
291 | replacement result in any insns encountered. */ | |
292 | static int num_not_at_initial_offset; | |
293 | ||
294 | /* Count the number of registers that we may be able to eliminate. */ | |
295 | static int num_eliminable; | |
296 | ||
297 | /* For each label, we record the offset of each elimination. If we reach | |
298 | a label by more than one path and an offset differs, we cannot do the | |
299 | elimination. This information is indexed by the number of the label. | |
300 | The first table is an array of flags that records whether we have yet | |
301 | encountered a label and the second table is an array of arrays, one | |
302 | entry in the latter array for each elimination. */ | |
303 | ||
304 | static char *offsets_known_at; | |
305 | static int (*offsets_at)[NUM_ELIMINABLE_REGS]; | |
306 | ||
307 | /* Number of labels in the current function. */ | |
308 | ||
309 | static int num_labels; | |
310 | \f | |
311 | void mark_home_live (); | |
312 | static void count_possible_groups (); | |
313 | static int possible_group_p (); | |
314 | static void scan_paradoxical_subregs (); | |
315 | static void reload_as_needed (); | |
316 | static int modes_equiv_for_class_p (); | |
317 | static void alter_reg (); | |
318 | static void delete_dead_insn (); | |
5352b11a | 319 | static void spill_failure (); |
32131a9c RK |
320 | static int new_spill_reg(); |
321 | static void set_label_offsets (); | |
322 | static int eliminate_regs_in_insn (); | |
323 | static void mark_not_eliminable (); | |
324 | static int spill_hard_reg (); | |
325 | static void choose_reload_regs (); | |
326 | static void emit_reload_insns (); | |
327 | static void delete_output_reload (); | |
328 | static void forget_old_reloads_1 (); | |
329 | static void order_regs_for_reload (); | |
330 | static rtx inc_for_reload (); | |
331 | static int constraint_accepts_reg_p (); | |
332 | static int count_occurrences (); | |
333 | ||
334 | extern void remove_death (); | |
335 | extern rtx adj_offsettable_operand (); | |
336 | extern rtx form_sum (); | |
337 | \f | |
338 | void | |
339 | init_reload () | |
340 | { | |
341 | register int i; | |
342 | ||
343 | /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. | |
344 | Set spill_indirect_levels to the number of levels such addressing is | |
345 | permitted, zero if it is not permitted at all. */ | |
346 | ||
347 | register rtx tem | |
348 | = gen_rtx (MEM, Pmode, | |
349 | gen_rtx (PLUS, Pmode, | |
350 | gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1), | |
fb3821f7 | 351 | GEN_INT (4))); |
32131a9c RK |
352 | spill_indirect_levels = 0; |
353 | ||
354 | while (memory_address_p (QImode, tem)) | |
355 | { | |
356 | spill_indirect_levels++; | |
357 | tem = gen_rtx (MEM, Pmode, tem); | |
358 | } | |
359 | ||
360 | /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ | |
361 | ||
362 | tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo")); | |
363 | indirect_symref_ok = memory_address_p (QImode, tem); | |
364 | ||
365 | /* See if reg+reg is a valid (and offsettable) address. */ | |
366 | ||
65701fd2 | 367 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
57caa638 RS |
368 | { |
369 | tem = gen_rtx (PLUS, Pmode, | |
370 | gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM), | |
371 | gen_rtx (REG, Pmode, i)); | |
372 | /* This way, we make sure that reg+reg is an offsettable address. */ | |
373 | tem = plus_constant (tem, 4); | |
374 | ||
375 | if (memory_address_p (QImode, tem)) | |
376 | { | |
377 | double_reg_address_ok = 1; | |
378 | break; | |
379 | } | |
380 | } | |
32131a9c RK |
381 | |
382 | /* Initialize obstack for our rtl allocation. */ | |
383 | gcc_obstack_init (&reload_obstack); | |
384 | reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); | |
385 | ||
386 | #ifdef HAVE_SECONDARY_RELOADS | |
387 | ||
388 | /* Initialize the optabs for doing special input and output reloads. */ | |
389 | ||
390 | for (i = 0; i < NUM_MACHINE_MODES; i++) | |
391 | reload_in_optab[i] = reload_out_optab[i] = CODE_FOR_nothing; | |
392 | ||
393 | #ifdef HAVE_reload_inqi | |
394 | if (HAVE_reload_inqi) | |
395 | reload_in_optab[(int) QImode] = CODE_FOR_reload_inqi; | |
396 | #endif | |
397 | #ifdef HAVE_reload_inhi | |
398 | if (HAVE_reload_inhi) | |
399 | reload_in_optab[(int) HImode] = CODE_FOR_reload_inhi; | |
400 | #endif | |
401 | #ifdef HAVE_reload_insi | |
402 | if (HAVE_reload_insi) | |
403 | reload_in_optab[(int) SImode] = CODE_FOR_reload_insi; | |
404 | #endif | |
405 | #ifdef HAVE_reload_indi | |
406 | if (HAVE_reload_indi) | |
407 | reload_in_optab[(int) DImode] = CODE_FOR_reload_indi; | |
408 | #endif | |
409 | #ifdef HAVE_reload_inti | |
410 | if (HAVE_reload_inti) | |
411 | reload_in_optab[(int) TImode] = CODE_FOR_reload_inti; | |
412 | #endif | |
213062d0 RS |
413 | #ifdef HAVE_reload_inqf |
414 | if (HAVE_reload_inqf) | |
415 | reload_in_optab[(int) QFmode] = CODE_FOR_reload_inqf; | |
416 | #endif | |
417 | #ifdef HAVE_reload_inhf | |
418 | if (HAVE_reload_inhf) | |
419 | reload_in_optab[(int) HFmode] = CODE_FOR_reload_inhf; | |
420 | #endif | |
32131a9c RK |
421 | #ifdef HAVE_reload_insf |
422 | if (HAVE_reload_insf) | |
423 | reload_in_optab[(int) SFmode] = CODE_FOR_reload_insf; | |
424 | #endif | |
425 | #ifdef HAVE_reload_indf | |
426 | if (HAVE_reload_indf) | |
427 | reload_in_optab[(int) DFmode] = CODE_FOR_reload_indf; | |
428 | #endif | |
429 | #ifdef HAVE_reload_inxf | |
430 | if (HAVE_reload_inxf) | |
431 | reload_in_optab[(int) XFmode] = CODE_FOR_reload_inxf; | |
432 | #endif | |
433 | #ifdef HAVE_reload_intf | |
434 | if (HAVE_reload_intf) | |
435 | reload_in_optab[(int) TFmode] = CODE_FOR_reload_intf; | |
436 | #endif | |
437 | ||
438 | #ifdef HAVE_reload_outqi | |
439 | if (HAVE_reload_outqi) | |
440 | reload_out_optab[(int) QImode] = CODE_FOR_reload_outqi; | |
441 | #endif | |
442 | #ifdef HAVE_reload_outhi | |
443 | if (HAVE_reload_outhi) | |
444 | reload_out_optab[(int) HImode] = CODE_FOR_reload_outhi; | |
445 | #endif | |
446 | #ifdef HAVE_reload_outsi | |
447 | if (HAVE_reload_outsi) | |
448 | reload_out_optab[(int) SImode] = CODE_FOR_reload_outsi; | |
449 | #endif | |
450 | #ifdef HAVE_reload_outdi | |
451 | if (HAVE_reload_outdi) | |
452 | reload_out_optab[(int) DImode] = CODE_FOR_reload_outdi; | |
453 | #endif | |
454 | #ifdef HAVE_reload_outti | |
455 | if (HAVE_reload_outti) | |
456 | reload_out_optab[(int) TImode] = CODE_FOR_reload_outti; | |
457 | #endif | |
213062d0 RS |
458 | #ifdef HAVE_reload_outqf |
459 | if (HAVE_reload_outqf) | |
460 | reload_out_optab[(int) QFmode] = CODE_FOR_reload_outqf; | |
461 | #endif | |
462 | #ifdef HAVE_reload_outhf | |
463 | if (HAVE_reload_outhf) | |
464 | reload_out_optab[(int) HFmode] = CODE_FOR_reload_outhf; | |
465 | #endif | |
32131a9c RK |
466 | #ifdef HAVE_reload_outsf |
467 | if (HAVE_reload_outsf) | |
468 | reload_out_optab[(int) SFmode] = CODE_FOR_reload_outsf; | |
469 | #endif | |
470 | #ifdef HAVE_reload_outdf | |
471 | if (HAVE_reload_outdf) | |
472 | reload_out_optab[(int) DFmode] = CODE_FOR_reload_outdf; | |
473 | #endif | |
474 | #ifdef HAVE_reload_outxf | |
475 | if (HAVE_reload_outxf) | |
476 | reload_out_optab[(int) XFmode] = CODE_FOR_reload_outxf; | |
477 | #endif | |
478 | #ifdef HAVE_reload_outtf | |
479 | if (HAVE_reload_outtf) | |
480 | reload_out_optab[(int) TFmode] = CODE_FOR_reload_outtf; | |
481 | #endif | |
482 | ||
483 | #endif /* HAVE_SECONDARY_RELOADS */ | |
484 | ||
485 | } | |
486 | ||
487 | /* Main entry point for the reload pass, and only entry point | |
488 | in this file. | |
489 | ||
490 | FIRST is the first insn of the function being compiled. | |
491 | ||
492 | GLOBAL nonzero means we were called from global_alloc | |
493 | and should attempt to reallocate any pseudoregs that we | |
494 | displace from hard regs we will use for reloads. | |
495 | If GLOBAL is zero, we do not have enough information to do that, | |
496 | so any pseudo reg that is spilled must go to the stack. | |
497 | ||
498 | DUMPFILE is the global-reg debugging dump file stream, or 0. | |
499 | If it is nonzero, messages are written to it to describe | |
500 | which registers are seized as reload regs, which pseudo regs | |
5352b11a | 501 | are spilled from them, and where the pseudo regs are reallocated to. |
32131a9c | 502 | |
5352b11a RS |
503 | Return value is nonzero if reload failed |
504 | and we must not do any more for this function. */ | |
505 | ||
506 | int | |
32131a9c RK |
507 | reload (first, global, dumpfile) |
508 | rtx first; | |
509 | int global; | |
510 | FILE *dumpfile; | |
511 | { | |
512 | register int class; | |
513 | register int i; | |
514 | register rtx insn; | |
515 | register struct elim_table *ep; | |
516 | ||
517 | int something_changed; | |
518 | int something_needs_reloads; | |
519 | int something_needs_elimination; | |
520 | int new_basic_block_needs; | |
a8efe40d RK |
521 | enum reg_class caller_save_spill_class = NO_REGS; |
522 | int caller_save_group_size = 1; | |
32131a9c | 523 | |
5352b11a RS |
524 | /* Nonzero means we couldn't get enough spill regs. */ |
525 | int failure = 0; | |
526 | ||
32131a9c RK |
527 | /* The basic block number currently being processed for INSN. */ |
528 | int this_block; | |
529 | ||
530 | /* Make sure even insns with volatile mem refs are recognizable. */ | |
531 | init_recog (); | |
532 | ||
533 | /* Enable find_equiv_reg to distinguish insns made by reload. */ | |
534 | reload_first_uid = get_max_uid (); | |
535 | ||
536 | for (i = 0; i < N_REG_CLASSES; i++) | |
537 | basic_block_needs[i] = 0; | |
538 | ||
0dadecf6 RK |
539 | #ifdef SECONDARY_MEMORY_NEEDED |
540 | /* Initialize the secondary memory table. */ | |
541 | clear_secondary_mem (); | |
542 | #endif | |
543 | ||
32131a9c RK |
544 | /* Remember which hard regs appear explicitly |
545 | before we merge into `regs_ever_live' the ones in which | |
546 | pseudo regs have been allocated. */ | |
547 | bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live); | |
548 | ||
549 | /* We don't have a stack slot for any spill reg yet. */ | |
550 | bzero (spill_stack_slot, sizeof spill_stack_slot); | |
551 | bzero (spill_stack_slot_width, sizeof spill_stack_slot_width); | |
552 | ||
a8efe40d RK |
553 | /* Initialize the save area information for caller-save, in case some |
554 | are needed. */ | |
555 | init_save_areas (); | |
a8fdc208 | 556 | |
32131a9c RK |
557 | /* Compute which hard registers are now in use |
558 | as homes for pseudo registers. | |
559 | This is done here rather than (eg) in global_alloc | |
560 | because this point is reached even if not optimizing. */ | |
561 | ||
562 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
563 | mark_home_live (i); | |
564 | ||
565 | /* Make sure that the last insn in the chain | |
566 | is not something that needs reloading. */ | |
fb3821f7 | 567 | emit_note (NULL_PTR, NOTE_INSN_DELETED); |
32131a9c RK |
568 | |
569 | /* Find all the pseudo registers that didn't get hard regs | |
570 | but do have known equivalent constants or memory slots. | |
571 | These include parameters (known equivalent to parameter slots) | |
572 | and cse'd or loop-moved constant memory addresses. | |
573 | ||
574 | Record constant equivalents in reg_equiv_constant | |
575 | so they will be substituted by find_reloads. | |
576 | Record memory equivalents in reg_mem_equiv so they can | |
577 | be substituted eventually by altering the REG-rtx's. */ | |
578 | ||
579 | reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx)); | |
580 | bzero (reg_equiv_constant, max_regno * sizeof (rtx)); | |
581 | reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx)); | |
582 | bzero (reg_equiv_memory_loc, max_regno * sizeof (rtx)); | |
583 | reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx)); | |
584 | bzero (reg_equiv_mem, max_regno * sizeof (rtx)); | |
585 | reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx)); | |
586 | bzero (reg_equiv_init, max_regno * sizeof (rtx)); | |
587 | reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx)); | |
588 | bzero (reg_equiv_address, max_regno * sizeof (rtx)); | |
589 | reg_max_ref_width = (int *) alloca (max_regno * sizeof (int)); | |
590 | bzero (reg_max_ref_width, max_regno * sizeof (int)); | |
591 | ||
592 | /* Look for REG_EQUIV notes; record what each pseudo is equivalent to. | |
593 | Also find all paradoxical subregs | |
594 | and find largest such for each pseudo. */ | |
595 | ||
596 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
597 | { | |
598 | rtx set = single_set (insn); | |
599 | ||
600 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG) | |
601 | { | |
fb3821f7 | 602 | rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
a8efe40d RK |
603 | if (note |
604 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
a8fdc208 | 605 | && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic |
a8efe40d RK |
606 | || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))) |
607 | #endif | |
608 | ) | |
32131a9c RK |
609 | { |
610 | rtx x = XEXP (note, 0); | |
611 | i = REGNO (SET_DEST (set)); | |
612 | if (i > LAST_VIRTUAL_REGISTER) | |
613 | { | |
614 | if (GET_CODE (x) == MEM) | |
615 | reg_equiv_memory_loc[i] = x; | |
616 | else if (CONSTANT_P (x)) | |
617 | { | |
618 | if (LEGITIMATE_CONSTANT_P (x)) | |
619 | reg_equiv_constant[i] = x; | |
620 | else | |
621 | reg_equiv_memory_loc[i] | |
d445b551 | 622 | = force_const_mem (GET_MODE (SET_DEST (set)), x); |
32131a9c RK |
623 | } |
624 | else | |
625 | continue; | |
626 | ||
627 | /* If this register is being made equivalent to a MEM | |
628 | and the MEM is not SET_SRC, the equivalencing insn | |
629 | is one with the MEM as a SET_DEST and it occurs later. | |
630 | So don't mark this insn now. */ | |
631 | if (GET_CODE (x) != MEM | |
632 | || rtx_equal_p (SET_SRC (set), x)) | |
633 | reg_equiv_init[i] = insn; | |
634 | } | |
635 | } | |
636 | } | |
637 | ||
638 | /* If this insn is setting a MEM from a register equivalent to it, | |
639 | this is the equivalencing insn. */ | |
640 | else if (set && GET_CODE (SET_DEST (set)) == MEM | |
641 | && GET_CODE (SET_SRC (set)) == REG | |
642 | && reg_equiv_memory_loc[REGNO (SET_SRC (set))] | |
643 | && rtx_equal_p (SET_DEST (set), | |
644 | reg_equiv_memory_loc[REGNO (SET_SRC (set))])) | |
645 | reg_equiv_init[REGNO (SET_SRC (set))] = insn; | |
646 | ||
647 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
648 | scan_paradoxical_subregs (PATTERN (insn)); | |
649 | } | |
650 | ||
651 | /* Does this function require a frame pointer? */ | |
652 | ||
653 | frame_pointer_needed = (! flag_omit_frame_pointer | |
654 | #ifdef EXIT_IGNORE_STACK | |
655 | /* ?? If EXIT_IGNORE_STACK is set, we will not save | |
656 | and restore sp for alloca. So we can't eliminate | |
657 | the frame pointer in that case. At some point, | |
658 | we should improve this by emitting the | |
659 | sp-adjusting insns for this case. */ | |
660 | || (current_function_calls_alloca | |
661 | && EXIT_IGNORE_STACK) | |
662 | #endif | |
663 | || FRAME_POINTER_REQUIRED); | |
664 | ||
665 | num_eliminable = 0; | |
666 | ||
667 | /* Initialize the table of registers to eliminate. The way we do this | |
668 | depends on how the eliminable registers were defined. */ | |
669 | #ifdef ELIMINABLE_REGS | |
670 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
671 | { | |
672 | ep->can_eliminate = ep->can_eliminate_previous | |
673 | = (CAN_ELIMINATE (ep->from, ep->to) | |
674 | && (ep->from != FRAME_POINTER_REGNUM || ! frame_pointer_needed)); | |
675 | } | |
676 | #else | |
677 | reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous | |
678 | = ! frame_pointer_needed; | |
679 | #endif | |
680 | ||
681 | /* Count the number of eliminable registers and build the FROM and TO | |
a8fdc208 | 682 | REG rtx's. Note that code in gen_rtx will cause, e.g., |
32131a9c RK |
683 | gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. |
684 | We depend on this. */ | |
685 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
686 | { | |
687 | num_eliminable += ep->can_eliminate; | |
688 | ep->from_rtx = gen_rtx (REG, Pmode, ep->from); | |
689 | ep->to_rtx = gen_rtx (REG, Pmode, ep->to); | |
690 | } | |
691 | ||
692 | num_labels = max_label_num () - get_first_label_num (); | |
693 | ||
694 | /* Allocate the tables used to store offset information at labels. */ | |
695 | offsets_known_at = (char *) alloca (num_labels); | |
696 | offsets_at | |
697 | = (int (*)[NUM_ELIMINABLE_REGS]) | |
698 | alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int)); | |
699 | ||
700 | offsets_known_at -= get_first_label_num (); | |
701 | offsets_at -= get_first_label_num (); | |
702 | ||
703 | /* Alter each pseudo-reg rtx to contain its hard reg number. | |
704 | Assign stack slots to the pseudos that lack hard regs or equivalents. | |
705 | Do not touch virtual registers. */ | |
706 | ||
707 | for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) | |
708 | alter_reg (i, -1); | |
709 | ||
710 | /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here | |
711 | because the stack size may be a part of the offset computation for | |
712 | register elimination. */ | |
713 | assign_stack_local (BLKmode, 0, 0); | |
714 | ||
715 | /* If we have some registers we think can be eliminated, scan all insns to | |
716 | see if there is an insn that sets one of these registers to something | |
717 | other than itself plus a constant. If so, the register cannot be | |
718 | eliminated. Doing this scan here eliminates an extra pass through the | |
719 | main reload loop in the most common case where register elimination | |
720 | cannot be done. */ | |
721 | for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) | |
722 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN | |
723 | || GET_CODE (insn) == CALL_INSN) | |
724 | note_stores (PATTERN (insn), mark_not_eliminable); | |
725 | ||
726 | #ifndef REGISTER_CONSTRAINTS | |
727 | /* If all the pseudo regs have hard regs, | |
728 | except for those that are never referenced, | |
729 | we know that no reloads are needed. */ | |
730 | /* But that is not true if there are register constraints, since | |
731 | in that case some pseudos might be in the wrong kind of hard reg. */ | |
732 | ||
733 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
734 | if (reg_renumber[i] == -1 && reg_n_refs[i] != 0) | |
735 | break; | |
736 | ||
b8093d02 | 737 | if (i == max_regno && num_eliminable == 0 && ! caller_save_needed) |
32131a9c RK |
738 | return; |
739 | #endif | |
740 | ||
741 | /* Compute the order of preference for hard registers to spill. | |
742 | Store them by decreasing preference in potential_reload_regs. */ | |
743 | ||
744 | order_regs_for_reload (); | |
745 | ||
746 | /* So far, no hard regs have been spilled. */ | |
747 | n_spills = 0; | |
748 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
749 | spill_reg_order[i] = -1; | |
750 | ||
751 | /* On most machines, we can't use any register explicitly used in the | |
752 | rtl as a spill register. But on some, we have to. Those will have | |
753 | taken care to keep the life of hard regs as short as possible. */ | |
754 | ||
755 | #ifdef SMALL_REGISTER_CLASSES | |
756 | CLEAR_HARD_REG_SET (forbidden_regs); | |
757 | #else | |
758 | COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs); | |
759 | #endif | |
760 | ||
761 | /* Spill any hard regs that we know we can't eliminate. */ | |
762 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
763 | if (! ep->can_eliminate) | |
764 | { | |
765 | spill_hard_reg (ep->from, global, dumpfile, 1); | |
766 | regs_ever_live[ep->from] = 1; | |
767 | } | |
768 | ||
769 | if (global) | |
770 | for (i = 0; i < N_REG_CLASSES; i++) | |
771 | { | |
772 | basic_block_needs[i] = (char *)alloca (n_basic_blocks); | |
773 | bzero (basic_block_needs[i], n_basic_blocks); | |
774 | } | |
775 | ||
b2f15f94 RK |
776 | /* From now on, we need to emit any moves without making new pseudos. */ |
777 | reload_in_progress = 1; | |
778 | ||
32131a9c RK |
779 | /* This loop scans the entire function each go-round |
780 | and repeats until one repetition spills no additional hard regs. */ | |
781 | ||
d45cf215 | 782 | /* This flag is set when a pseudo reg is spilled, |
32131a9c RK |
783 | to require another pass. Note that getting an additional reload |
784 | reg does not necessarily imply any pseudo reg was spilled; | |
785 | sometimes we find a reload reg that no pseudo reg was allocated in. */ | |
786 | something_changed = 1; | |
787 | /* This flag is set if there are any insns that require reloading. */ | |
788 | something_needs_reloads = 0; | |
789 | /* This flag is set if there are any insns that require register | |
790 | eliminations. */ | |
791 | something_needs_elimination = 0; | |
792 | while (something_changed) | |
793 | { | |
794 | rtx after_call = 0; | |
795 | ||
796 | /* For each class, number of reload regs needed in that class. | |
797 | This is the maximum over all insns of the needs in that class | |
798 | of the individual insn. */ | |
799 | int max_needs[N_REG_CLASSES]; | |
800 | /* For each class, size of group of consecutive regs | |
801 | that is needed for the reloads of this class. */ | |
802 | int group_size[N_REG_CLASSES]; | |
803 | /* For each class, max number of consecutive groups needed. | |
804 | (Each group contains group_size[CLASS] consecutive registers.) */ | |
805 | int max_groups[N_REG_CLASSES]; | |
806 | /* For each class, max number needed of regs that don't belong | |
807 | to any of the groups. */ | |
808 | int max_nongroups[N_REG_CLASSES]; | |
809 | /* For each class, the machine mode which requires consecutive | |
810 | groups of regs of that class. | |
811 | If two different modes ever require groups of one class, | |
812 | they must be the same size and equally restrictive for that class, | |
813 | otherwise we can't handle the complexity. */ | |
814 | enum machine_mode group_mode[N_REG_CLASSES]; | |
5352b11a RS |
815 | /* Record the insn where each maximum need is first found. */ |
816 | rtx max_needs_insn[N_REG_CLASSES]; | |
817 | rtx max_groups_insn[N_REG_CLASSES]; | |
818 | rtx max_nongroups_insn[N_REG_CLASSES]; | |
32131a9c | 819 | rtx x; |
0dadecf6 | 820 | int starting_frame_size = get_frame_size (); |
e404a39a | 821 | static char *reg_class_names[] = REG_CLASS_NAMES; |
32131a9c RK |
822 | |
823 | something_changed = 0; | |
824 | bzero (max_needs, sizeof max_needs); | |
825 | bzero (max_groups, sizeof max_groups); | |
826 | bzero (max_nongroups, sizeof max_nongroups); | |
5352b11a RS |
827 | bzero (max_needs_insn, sizeof max_needs_insn); |
828 | bzero (max_groups_insn, sizeof max_groups_insn); | |
829 | bzero (max_nongroups_insn, sizeof max_nongroups_insn); | |
32131a9c RK |
830 | bzero (group_size, sizeof group_size); |
831 | for (i = 0; i < N_REG_CLASSES; i++) | |
832 | group_mode[i] = VOIDmode; | |
833 | ||
834 | /* Keep track of which basic blocks are needing the reloads. */ | |
835 | this_block = 0; | |
836 | ||
837 | /* Remember whether any element of basic_block_needs | |
838 | changes from 0 to 1 in this pass. */ | |
839 | new_basic_block_needs = 0; | |
840 | ||
841 | /* Reset all offsets on eliminable registers to their initial values. */ | |
842 | #ifdef ELIMINABLE_REGS | |
843 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
844 | { | |
845 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); | |
a8efe40d RK |
846 | ep->previous_offset = ep->offset |
847 | = ep->max_offset = ep->initial_offset; | |
32131a9c RK |
848 | } |
849 | #else | |
850 | #ifdef INITIAL_FRAME_POINTER_OFFSET | |
851 | INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset); | |
852 | #else | |
853 | if (!FRAME_POINTER_REQUIRED) | |
854 | abort (); | |
855 | reg_eliminate[0].initial_offset = 0; | |
856 | #endif | |
a8efe40d | 857 | reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset |
32131a9c RK |
858 | = reg_eliminate[0].offset = reg_eliminate[0].initial_offset; |
859 | #endif | |
860 | ||
861 | num_not_at_initial_offset = 0; | |
862 | ||
863 | bzero (&offsets_known_at[get_first_label_num ()], num_labels); | |
864 | ||
865 | /* Set a known offset for each forced label to be at the initial offset | |
866 | of each elimination. We do this because we assume that all | |
867 | computed jumps occur from a location where each elimination is | |
868 | at its initial offset. */ | |
869 | ||
870 | for (x = forced_labels; x; x = XEXP (x, 1)) | |
871 | if (XEXP (x, 0)) | |
fb3821f7 | 872 | set_label_offsets (XEXP (x, 0), NULL_RTX, 1); |
32131a9c RK |
873 | |
874 | /* For each pseudo register that has an equivalent location defined, | |
875 | try to eliminate any eliminable registers (such as the frame pointer) | |
876 | assuming initial offsets for the replacement register, which | |
877 | is the normal case. | |
878 | ||
879 | If the resulting location is directly addressable, substitute | |
880 | the MEM we just got directly for the old REG. | |
881 | ||
882 | If it is not addressable but is a constant or the sum of a hard reg | |
883 | and constant, it is probably not addressable because the constant is | |
884 | out of range, in that case record the address; we will generate | |
885 | hairy code to compute the address in a register each time it is | |
a8fdc208 | 886 | needed. |
32131a9c RK |
887 | |
888 | If the location is not addressable, but does not have one of the | |
889 | above forms, assign a stack slot. We have to do this to avoid the | |
890 | potential of producing lots of reloads if, e.g., a location involves | |
891 | a pseudo that didn't get a hard register and has an equivalent memory | |
892 | location that also involves a pseudo that didn't get a hard register. | |
893 | ||
894 | Perhaps at some point we will improve reload_when_needed handling | |
895 | so this problem goes away. But that's very hairy. */ | |
896 | ||
897 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
898 | if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) | |
899 | { | |
fb3821f7 | 900 | rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX); |
32131a9c RK |
901 | |
902 | if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]), | |
903 | XEXP (x, 0))) | |
904 | reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; | |
905 | else if (CONSTANT_P (XEXP (x, 0)) | |
906 | || (GET_CODE (XEXP (x, 0)) == PLUS | |
907 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
908 | && (REGNO (XEXP (XEXP (x, 0), 0)) | |
909 | < FIRST_PSEUDO_REGISTER) | |
910 | && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) | |
911 | reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; | |
912 | else | |
913 | { | |
914 | /* Make a new stack slot. Then indicate that something | |
a8fdc208 | 915 | changed so we go back and recompute offsets for |
32131a9c RK |
916 | eliminable registers because the allocation of memory |
917 | below might change some offset. reg_equiv_{mem,address} | |
918 | will be set up for this pseudo on the next pass around | |
919 | the loop. */ | |
920 | reg_equiv_memory_loc[i] = 0; | |
921 | reg_equiv_init[i] = 0; | |
922 | alter_reg (i, -1); | |
923 | something_changed = 1; | |
924 | } | |
925 | } | |
a8fdc208 | 926 | |
d45cf215 | 927 | /* If we allocated another pseudo to the stack, redo elimination |
32131a9c RK |
928 | bookkeeping. */ |
929 | if (something_changed) | |
930 | continue; | |
931 | ||
a8efe40d RK |
932 | /* If caller-saves needs a group, initialize the group to include |
933 | the size and mode required for caller-saves. */ | |
934 | ||
935 | if (caller_save_group_size > 1) | |
936 | { | |
937 | group_mode[(int) caller_save_spill_class] = Pmode; | |
938 | group_size[(int) caller_save_spill_class] = caller_save_group_size; | |
939 | } | |
940 | ||
32131a9c RK |
941 | /* Compute the most additional registers needed by any instruction. |
942 | Collect information separately for each class of regs. */ | |
943 | ||
944 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
945 | { | |
946 | if (global && this_block + 1 < n_basic_blocks | |
947 | && insn == basic_block_head[this_block+1]) | |
948 | ++this_block; | |
949 | ||
950 | /* If this is a label, a JUMP_INSN, or has REG_NOTES (which | |
951 | might include REG_LABEL), we need to see what effects this | |
952 | has on the known offsets at labels. */ | |
953 | ||
954 | if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN | |
955 | || (GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
956 | && REG_NOTES (insn) != 0)) | |
957 | set_label_offsets (insn, insn, 0); | |
958 | ||
959 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
960 | { | |
961 | /* Nonzero means don't use a reload reg that overlaps | |
962 | the place where a function value can be returned. */ | |
963 | rtx avoid_return_reg = 0; | |
964 | ||
965 | rtx old_body = PATTERN (insn); | |
966 | int old_code = INSN_CODE (insn); | |
967 | rtx old_notes = REG_NOTES (insn); | |
968 | int did_elimination = 0; | |
969 | ||
970 | /* Initially, count RELOAD_OTHER reloads. | |
971 | Later, merge in the other kinds. */ | |
972 | int insn_needs[N_REG_CLASSES]; | |
973 | int insn_groups[N_REG_CLASSES]; | |
974 | int insn_total_groups = 0; | |
975 | ||
976 | /* Count RELOAD_FOR_INPUT_RELOAD_ADDRESS reloads. */ | |
977 | int insn_needs_for_inputs[N_REG_CLASSES]; | |
978 | int insn_groups_for_inputs[N_REG_CLASSES]; | |
979 | int insn_total_groups_for_inputs = 0; | |
980 | ||
981 | /* Count RELOAD_FOR_OUTPUT_RELOAD_ADDRESS reloads. */ | |
982 | int insn_needs_for_outputs[N_REG_CLASSES]; | |
983 | int insn_groups_for_outputs[N_REG_CLASSES]; | |
984 | int insn_total_groups_for_outputs = 0; | |
985 | ||
986 | /* Count RELOAD_FOR_OPERAND_ADDRESS reloads. */ | |
987 | int insn_needs_for_operands[N_REG_CLASSES]; | |
988 | int insn_groups_for_operands[N_REG_CLASSES]; | |
989 | int insn_total_groups_for_operands = 0; | |
990 | ||
32131a9c RK |
991 | #if 0 /* This wouldn't work nowadays, since optimize_bit_field |
992 | looks for non-strict memory addresses. */ | |
993 | /* Optimization: a bit-field instruction whose field | |
994 | happens to be a byte or halfword in memory | |
995 | can be changed to a move instruction. */ | |
996 | ||
997 | if (GET_CODE (PATTERN (insn)) == SET) | |
998 | { | |
999 | rtx dest = SET_DEST (PATTERN (insn)); | |
1000 | rtx src = SET_SRC (PATTERN (insn)); | |
1001 | ||
1002 | if (GET_CODE (dest) == ZERO_EXTRACT | |
1003 | || GET_CODE (dest) == SIGN_EXTRACT) | |
1004 | optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem); | |
1005 | if (GET_CODE (src) == ZERO_EXTRACT | |
1006 | || GET_CODE (src) == SIGN_EXTRACT) | |
1007 | optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem); | |
1008 | } | |
1009 | #endif | |
1010 | ||
1011 | /* If needed, eliminate any eliminable registers. */ | |
1012 | if (num_eliminable) | |
1013 | did_elimination = eliminate_regs_in_insn (insn, 0); | |
1014 | ||
1015 | #ifdef SMALL_REGISTER_CLASSES | |
1016 | /* Set avoid_return_reg if this is an insn | |
1017 | that might use the value of a function call. */ | |
1018 | if (GET_CODE (insn) == CALL_INSN) | |
1019 | { | |
1020 | if (GET_CODE (PATTERN (insn)) == SET) | |
1021 | after_call = SET_DEST (PATTERN (insn)); | |
1022 | else if (GET_CODE (PATTERN (insn)) == PARALLEL | |
1023 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) | |
1024 | after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0)); | |
1025 | else | |
1026 | after_call = 0; | |
1027 | } | |
1028 | else if (after_call != 0 | |
1029 | && !(GET_CODE (PATTERN (insn)) == SET | |
1030 | && SET_DEST (PATTERN (insn)) == stack_pointer_rtx)) | |
1031 | { | |
1032 | if (reg_mentioned_p (after_call, PATTERN (insn))) | |
1033 | avoid_return_reg = after_call; | |
1034 | after_call = 0; | |
1035 | } | |
1036 | #endif /* SMALL_REGISTER_CLASSES */ | |
1037 | ||
1038 | /* Analyze the instruction. */ | |
1039 | find_reloads (insn, 0, spill_indirect_levels, global, | |
1040 | spill_reg_order); | |
1041 | ||
1042 | /* Remember for later shortcuts which insns had any reloads or | |
1043 | register eliminations. | |
1044 | ||
1045 | One might think that it would be worthwhile to mark insns | |
1046 | that need register replacements but not reloads, but this is | |
1047 | not safe because find_reloads may do some manipulation of | |
1048 | the insn (such as swapping commutative operands), which would | |
1049 | be lost when we restore the old pattern after register | |
1050 | replacement. So the actions of find_reloads must be redone in | |
1051 | subsequent passes or in reload_as_needed. | |
1052 | ||
1053 | However, it is safe to mark insns that need reloads | |
1054 | but not register replacement. */ | |
1055 | ||
1056 | PUT_MODE (insn, (did_elimination ? QImode | |
1057 | : n_reloads ? HImode | |
1058 | : VOIDmode)); | |
1059 | ||
1060 | /* Discard any register replacements done. */ | |
1061 | if (did_elimination) | |
1062 | { | |
1063 | obstack_free (&reload_obstack, reload_firstobj); | |
1064 | PATTERN (insn) = old_body; | |
1065 | INSN_CODE (insn) = old_code; | |
1066 | REG_NOTES (insn) = old_notes; | |
1067 | something_needs_elimination = 1; | |
1068 | } | |
1069 | ||
a8efe40d | 1070 | /* If this insn has no reloads, we need not do anything except |
a8fdc208 | 1071 | in the case of a CALL_INSN when we have caller-saves and |
a8efe40d RK |
1072 | caller-save needs reloads. */ |
1073 | ||
1074 | if (n_reloads == 0 | |
1075 | && ! (GET_CODE (insn) == CALL_INSN | |
1076 | && caller_save_spill_class != NO_REGS)) | |
32131a9c RK |
1077 | continue; |
1078 | ||
1079 | something_needs_reloads = 1; | |
1080 | ||
a8efe40d RK |
1081 | for (i = 0; i < N_REG_CLASSES; i++) |
1082 | { | |
1083 | insn_needs[i] = 0, insn_groups[i] = 0; | |
1084 | insn_needs_for_inputs[i] = 0, insn_groups_for_inputs[i] = 0; | |
1085 | insn_needs_for_outputs[i] = 0, insn_groups_for_outputs[i] = 0; | |
1086 | insn_needs_for_operands[i] = 0, insn_groups_for_operands[i] = 0; | |
1087 | } | |
1088 | ||
32131a9c RK |
1089 | /* Count each reload once in every class |
1090 | containing the reload's own class. */ | |
1091 | ||
1092 | for (i = 0; i < n_reloads; i++) | |
1093 | { | |
1094 | register enum reg_class *p; | |
e85ddd99 | 1095 | enum reg_class class = reload_reg_class[i]; |
32131a9c RK |
1096 | int size; |
1097 | enum machine_mode mode; | |
1098 | int *this_groups; | |
1099 | int *this_needs; | |
1100 | int *this_total_groups; | |
1101 | ||
1102 | /* Don't count the dummy reloads, for which one of the | |
1103 | regs mentioned in the insn can be used for reloading. | |
1104 | Don't count optional reloads. | |
1105 | Don't count reloads that got combined with others. */ | |
1106 | if (reload_reg_rtx[i] != 0 | |
1107 | || reload_optional[i] != 0 | |
1108 | || (reload_out[i] == 0 && reload_in[i] == 0 | |
1109 | && ! reload_secondary_p[i])) | |
1110 | continue; | |
1111 | ||
e85ddd99 RK |
1112 | /* Show that a reload register of this class is needed |
1113 | in this basic block. We do not use insn_needs and | |
1114 | insn_groups because they are overly conservative for | |
1115 | this purpose. */ | |
1116 | if (global && ! basic_block_needs[(int) class][this_block]) | |
1117 | { | |
1118 | basic_block_needs[(int) class][this_block] = 1; | |
1119 | new_basic_block_needs = 1; | |
1120 | } | |
1121 | ||
32131a9c RK |
1122 | /* Decide which time-of-use to count this reload for. */ |
1123 | switch (reload_when_needed[i]) | |
1124 | { | |
1125 | case RELOAD_OTHER: | |
1126 | case RELOAD_FOR_OUTPUT: | |
1127 | case RELOAD_FOR_INPUT: | |
1128 | this_needs = insn_needs; | |
1129 | this_groups = insn_groups; | |
1130 | this_total_groups = &insn_total_groups; | |
1131 | break; | |
1132 | ||
1133 | case RELOAD_FOR_INPUT_RELOAD_ADDRESS: | |
1134 | this_needs = insn_needs_for_inputs; | |
1135 | this_groups = insn_groups_for_inputs; | |
1136 | this_total_groups = &insn_total_groups_for_inputs; | |
1137 | break; | |
1138 | ||
1139 | case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS: | |
1140 | this_needs = insn_needs_for_outputs; | |
1141 | this_groups = insn_groups_for_outputs; | |
1142 | this_total_groups = &insn_total_groups_for_outputs; | |
1143 | break; | |
1144 | ||
1145 | case RELOAD_FOR_OPERAND_ADDRESS: | |
1146 | this_needs = insn_needs_for_operands; | |
1147 | this_groups = insn_groups_for_operands; | |
1148 | this_total_groups = &insn_total_groups_for_operands; | |
1149 | break; | |
1150 | } | |
1151 | ||
1152 | mode = reload_inmode[i]; | |
1153 | if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode)) | |
1154 | mode = reload_outmode[i]; | |
e85ddd99 | 1155 | size = CLASS_MAX_NREGS (class, mode); |
32131a9c RK |
1156 | if (size > 1) |
1157 | { | |
1158 | enum machine_mode other_mode, allocate_mode; | |
1159 | ||
1160 | /* Count number of groups needed separately from | |
1161 | number of individual regs needed. */ | |
e85ddd99 RK |
1162 | this_groups[(int) class]++; |
1163 | p = reg_class_superclasses[(int) class]; | |
32131a9c RK |
1164 | while (*p != LIM_REG_CLASSES) |
1165 | this_groups[(int) *p++]++; | |
1166 | (*this_total_groups)++; | |
1167 | ||
1168 | /* Record size and mode of a group of this class. */ | |
1169 | /* If more than one size group is needed, | |
1170 | make all groups the largest needed size. */ | |
e85ddd99 | 1171 | if (group_size[(int) class] < size) |
32131a9c | 1172 | { |
e85ddd99 | 1173 | other_mode = group_mode[(int) class]; |
32131a9c RK |
1174 | allocate_mode = mode; |
1175 | ||
e85ddd99 RK |
1176 | group_size[(int) class] = size; |
1177 | group_mode[(int) class] = mode; | |
32131a9c RK |
1178 | } |
1179 | else | |
1180 | { | |
1181 | other_mode = mode; | |
e85ddd99 | 1182 | allocate_mode = group_mode[(int) class]; |
32131a9c RK |
1183 | } |
1184 | ||
1185 | /* Crash if two dissimilar machine modes both need | |
1186 | groups of consecutive regs of the same class. */ | |
1187 | ||
1188 | if (other_mode != VOIDmode | |
1189 | && other_mode != allocate_mode | |
1190 | && ! modes_equiv_for_class_p (allocate_mode, | |
1191 | other_mode, | |
e85ddd99 | 1192 | class)) |
32131a9c RK |
1193 | abort (); |
1194 | } | |
1195 | else if (size == 1) | |
1196 | { | |
e85ddd99 RK |
1197 | this_needs[(int) class] += 1; |
1198 | p = reg_class_superclasses[(int) class]; | |
32131a9c RK |
1199 | while (*p != LIM_REG_CLASSES) |
1200 | this_needs[(int) *p++] += 1; | |
1201 | } | |
1202 | else | |
1203 | abort (); | |
1204 | } | |
1205 | ||
1206 | /* All reloads have been counted for this insn; | |
1207 | now merge the various times of use. | |
1208 | This sets insn_needs, etc., to the maximum total number | |
1209 | of registers needed at any point in this insn. */ | |
1210 | ||
1211 | for (i = 0; i < N_REG_CLASSES; i++) | |
1212 | { | |
1213 | int this_max; | |
1214 | this_max = insn_needs_for_inputs[i]; | |
1215 | if (insn_needs_for_outputs[i] > this_max) | |
1216 | this_max = insn_needs_for_outputs[i]; | |
1217 | if (insn_needs_for_operands[i] > this_max) | |
1218 | this_max = insn_needs_for_operands[i]; | |
1219 | insn_needs[i] += this_max; | |
1220 | this_max = insn_groups_for_inputs[i]; | |
1221 | if (insn_groups_for_outputs[i] > this_max) | |
1222 | this_max = insn_groups_for_outputs[i]; | |
1223 | if (insn_groups_for_operands[i] > this_max) | |
1224 | this_max = insn_groups_for_operands[i]; | |
1225 | insn_groups[i] += this_max; | |
32131a9c | 1226 | } |
a8efe40d | 1227 | |
32131a9c RK |
1228 | insn_total_groups += MAX (insn_total_groups_for_inputs, |
1229 | MAX (insn_total_groups_for_outputs, | |
1230 | insn_total_groups_for_operands)); | |
1231 | ||
a8efe40d RK |
1232 | /* If this is a CALL_INSN and caller-saves will need |
1233 | a spill register, act as if the spill register is | |
1234 | needed for this insn. However, the spill register | |
1235 | can be used by any reload of this insn, so we only | |
1236 | need do something if no need for that class has | |
a8fdc208 | 1237 | been recorded. |
a8efe40d RK |
1238 | |
1239 | The assumption that every CALL_INSN will trigger a | |
1240 | caller-save is highly conservative, however, the number | |
1241 | of cases where caller-saves will need a spill register but | |
1242 | a block containing a CALL_INSN won't need a spill register | |
1243 | of that class should be quite rare. | |
1244 | ||
1245 | If a group is needed, the size and mode of the group will | |
d45cf215 | 1246 | have been set up at the beginning of this loop. */ |
a8efe40d RK |
1247 | |
1248 | if (GET_CODE (insn) == CALL_INSN | |
1249 | && caller_save_spill_class != NO_REGS) | |
1250 | { | |
1251 | int *caller_save_needs | |
1252 | = (caller_save_group_size > 1 ? insn_groups : insn_needs); | |
1253 | ||
1254 | if (caller_save_needs[(int) caller_save_spill_class] == 0) | |
1255 | { | |
1256 | register enum reg_class *p | |
1257 | = reg_class_superclasses[(int) caller_save_spill_class]; | |
1258 | ||
1259 | caller_save_needs[(int) caller_save_spill_class]++; | |
1260 | ||
1261 | while (*p != LIM_REG_CLASSES) | |
0aaa6af8 | 1262 | caller_save_needs[(int) *p++] += 1; |
a8efe40d RK |
1263 | } |
1264 | ||
1265 | if (caller_save_group_size > 1) | |
1266 | insn_total_groups = MAX (insn_total_groups, 1); | |
d1c1397e RS |
1267 | |
1268 | ||
1269 | /* Show that this basic block will need a register of | |
1270 | this class. */ | |
1271 | ||
1272 | if (global | |
1273 | && ! (basic_block_needs[(int) caller_save_spill_class] | |
1274 | [this_block])) | |
1275 | { | |
1276 | basic_block_needs[(int) caller_save_spill_class] | |
1277 | [this_block] = 1; | |
1278 | new_basic_block_needs = 1; | |
1279 | } | |
a8efe40d RK |
1280 | } |
1281 | ||
32131a9c RK |
1282 | #ifdef SMALL_REGISTER_CLASSES |
1283 | /* If this insn stores the value of a function call, | |
1284 | and that value is in a register that has been spilled, | |
1285 | and if the insn needs a reload in a class | |
1286 | that might use that register as the reload register, | |
1287 | then add add an extra need in that class. | |
1288 | This makes sure we have a register available that does | |
1289 | not overlap the return value. */ | |
1290 | if (avoid_return_reg) | |
1291 | { | |
1292 | int regno = REGNO (avoid_return_reg); | |
1293 | int nregs | |
1294 | = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg)); | |
1295 | int r; | |
1296 | int inc_groups = 0; | |
1297 | for (r = regno; r < regno + nregs; r++) | |
1298 | if (spill_reg_order[r] >= 0) | |
1299 | for (i = 0; i < N_REG_CLASSES; i++) | |
1300 | if (TEST_HARD_REG_BIT (reg_class_contents[i], r)) | |
1301 | { | |
9e859f7e RS |
1302 | /* ??? It's not clear what is really |
1303 | right to do if this insn needs a group. | |
1304 | But maybe that cannot happen. */ | |
1305 | if (insn_needs[i] > 0 || insn_groups[i] > 0) | |
32131a9c | 1306 | insn_needs[i]++; |
32131a9c | 1307 | } |
32131a9c RK |
1308 | } |
1309 | #endif /* SMALL_REGISTER_CLASSES */ | |
1310 | ||
1311 | /* For each class, collect maximum need of any insn. */ | |
1312 | ||
1313 | for (i = 0; i < N_REG_CLASSES; i++) | |
1314 | { | |
1315 | if (max_needs[i] < insn_needs[i]) | |
5352b11a RS |
1316 | { |
1317 | max_needs[i] = insn_needs[i]; | |
1318 | max_needs_insn[i] = insn; | |
1319 | } | |
32131a9c | 1320 | if (max_groups[i] < insn_groups[i]) |
5352b11a RS |
1321 | { |
1322 | max_groups[i] = insn_groups[i]; | |
1323 | max_groups_insn[i] = insn; | |
1324 | } | |
32131a9c RK |
1325 | if (insn_total_groups > 0) |
1326 | if (max_nongroups[i] < insn_needs[i]) | |
5352b11a RS |
1327 | { |
1328 | max_nongroups[i] = insn_needs[i]; | |
1329 | max_nongroups_insn[i] = insn; | |
1330 | } | |
32131a9c RK |
1331 | } |
1332 | } | |
1333 | /* Note that there is a continue statement above. */ | |
1334 | } | |
1335 | ||
0dadecf6 RK |
1336 | /* If we allocated any new memory locations, make another pass |
1337 | since it might have changed elimination offsets. */ | |
1338 | if (starting_frame_size != get_frame_size ()) | |
1339 | something_changed = 1; | |
1340 | ||
e404a39a RK |
1341 | if (dumpfile) |
1342 | for (i = 0; i < N_REG_CLASSES; i++) | |
1343 | { | |
1344 | if (max_needs[i] > 0) | |
1345 | fprintf (dumpfile, | |
1346 | ";; Need %d reg%s of class %s (for insn %d).\n", | |
1347 | max_needs[i], max_needs[i] == 1 ? "" : "s", | |
1348 | reg_class_names[i], INSN_UID (max_needs_insn[i])); | |
1349 | if (max_nongroups[i] > 0) | |
1350 | fprintf (dumpfile, | |
1351 | ";; Need %d nongroup reg%s of class %s (for insn %d).\n", | |
1352 | max_nongroups[i], max_nongroups[i] == 1 ? "" : "s", | |
1353 | reg_class_names[i], INSN_UID (max_nongroups_insn[i])); | |
1354 | if (max_groups[i] > 0) | |
1355 | fprintf (dumpfile, | |
1356 | ";; Need %d group%s (%smode) of class %s (for insn %d).\n", | |
1357 | max_groups[i], max_groups[i] == 1 ? "" : "s", | |
1358 | mode_name[(int) group_mode[i]], | |
1359 | reg_class_names[i], INSN_UID (max_groups_insn[i])); | |
1360 | } | |
1361 | ||
d445b551 | 1362 | /* If we have caller-saves, set up the save areas and see if caller-save |
a8efe40d | 1363 | will need a spill register. */ |
32131a9c | 1364 | |
d445b551 | 1365 | if (caller_save_needed |
a8efe40d RK |
1366 | && ! setup_save_areas (&something_changed) |
1367 | && caller_save_spill_class == NO_REGS) | |
32131a9c | 1368 | { |
a8efe40d RK |
1369 | /* The class we will need depends on whether the machine |
1370 | supports the sum of two registers for an address; see | |
1371 | find_address_reloads for details. */ | |
1372 | ||
a8fdc208 | 1373 | caller_save_spill_class |
a8efe40d RK |
1374 | = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS; |
1375 | caller_save_group_size | |
1376 | = CLASS_MAX_NREGS (caller_save_spill_class, Pmode); | |
1377 | something_changed = 1; | |
32131a9c RK |
1378 | } |
1379 | ||
1380 | /* Now deduct from the needs for the registers already | |
1381 | available (already spilled). */ | |
1382 | ||
1383 | CLEAR_HARD_REG_SET (counted_for_groups); | |
1384 | CLEAR_HARD_REG_SET (counted_for_nongroups); | |
1385 | ||
1386 | /* First find all regs alone in their class | |
1387 | and count them (if desired) for non-groups. | |
1388 | We would be screwed if a group took the only reg in a class | |
d445b551 | 1389 | for which a non-group reload is needed. |
32131a9c RK |
1390 | (Note there is still a bug; if a class has 2 regs, |
1391 | both could be stolen by groups and we would lose the same way. | |
1392 | With luck, no machine will need a nongroup in a 2-reg class.) */ | |
1393 | ||
1394 | for (i = 0; i < n_spills; i++) | |
1395 | { | |
1396 | register enum reg_class *p; | |
1397 | class = (int) REGNO_REG_CLASS (spill_regs[i]); | |
1398 | ||
1399 | if (reg_class_size[class] == 1 && max_nongroups[class] > 0) | |
1400 | { | |
1401 | max_needs[class]--; | |
1402 | p = reg_class_superclasses[class]; | |
1403 | while (*p != LIM_REG_CLASSES) | |
1404 | max_needs[(int) *p++]--; | |
1405 | ||
1406 | SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]); | |
1407 | max_nongroups[class]--; | |
1408 | p = reg_class_superclasses[class]; | |
1409 | while (*p != LIM_REG_CLASSES) | |
1410 | { | |
1411 | if (max_nongroups[(int) *p] > 0) | |
1412 | SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]); | |
1413 | max_nongroups[(int) *p++]--; | |
1414 | } | |
1415 | } | |
1416 | } | |
1417 | ||
1418 | /* Now find all consecutive groups of spilled registers | |
1419 | and mark each group off against the need for such groups. | |
1420 | But don't count them against ordinary need, yet. */ | |
1421 | ||
1422 | count_possible_groups (group_size, group_mode, max_groups); | |
1423 | ||
1424 | /* Now count all spill regs against the individual need, | |
a8fdc208 | 1425 | This includes those counted above for groups, |
32131a9c RK |
1426 | but not those previously counted for nongroups. |
1427 | ||
1428 | Those that weren't counted_for_groups can also count against | |
1429 | the not-in-group need. */ | |
1430 | ||
1431 | for (i = 0; i < n_spills; i++) | |
1432 | { | |
1433 | register enum reg_class *p; | |
1434 | class = (int) REGNO_REG_CLASS (spill_regs[i]); | |
1435 | ||
1436 | /* Those counted at the beginning shouldn't be counted twice. */ | |
1437 | if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i])) | |
1438 | { | |
1439 | max_needs[class]--; | |
1440 | p = reg_class_superclasses[class]; | |
1441 | while (*p != LIM_REG_CLASSES) | |
1442 | max_needs[(int) *p++]--; | |
1443 | ||
1444 | if (! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i])) | |
1445 | { | |
1446 | if (max_nongroups[class] > 0) | |
1447 | SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]); | |
1448 | max_nongroups[class]--; | |
1449 | p = reg_class_superclasses[class]; | |
1450 | while (*p != LIM_REG_CLASSES) | |
1451 | { | |
1452 | if (max_nongroups[(int) *p] > 0) | |
1453 | SET_HARD_REG_BIT (counted_for_nongroups, | |
1454 | spill_regs[i]); | |
1455 | max_nongroups[(int) *p++]--; | |
1456 | } | |
1457 | } | |
1458 | } | |
1459 | } | |
1460 | ||
5c23c401 RK |
1461 | /* See if anything that happened changes which eliminations are valid. |
1462 | For example, on the Sparc, whether or not the frame pointer can | |
1463 | be eliminated can depend on what registers have been used. We need | |
1464 | not check some conditions again (such as flag_omit_frame_pointer) | |
1465 | since they can't have changed. */ | |
1466 | ||
1467 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1468 | if ((ep->from == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED) | |
1469 | #ifdef ELIMINABLE_REGS | |
1470 | || ! CAN_ELIMINATE (ep->from, ep->to) | |
1471 | #endif | |
1472 | ) | |
1473 | ep->can_eliminate = 0; | |
1474 | ||
32131a9c RK |
1475 | /* Look for the case where we have discovered that we can't replace |
1476 | register A with register B and that means that we will now be | |
1477 | trying to replace register A with register C. This means we can | |
1478 | no longer replace register C with register B and we need to disable | |
1479 | such an elimination, if it exists. This occurs often with A == ap, | |
1480 | B == sp, and C == fp. */ | |
a8fdc208 | 1481 | |
32131a9c RK |
1482 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
1483 | { | |
1484 | struct elim_table *op; | |
1485 | register int new_to = -1; | |
1486 | ||
1487 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
1488 | { | |
1489 | /* Find the current elimination for ep->from, if there is a | |
1490 | new one. */ | |
1491 | for (op = reg_eliminate; | |
1492 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
1493 | if (op->from == ep->from && op->can_eliminate) | |
1494 | { | |
1495 | new_to = op->to; | |
1496 | break; | |
1497 | } | |
1498 | ||
1499 | /* See if there is an elimination of NEW_TO -> EP->TO. If so, | |
1500 | disable it. */ | |
1501 | for (op = reg_eliminate; | |
1502 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
1503 | if (op->from == new_to && op->to == ep->to) | |
1504 | op->can_eliminate = 0; | |
1505 | } | |
1506 | } | |
1507 | ||
1508 | /* See if any registers that we thought we could eliminate the previous | |
1509 | time are no longer eliminable. If so, something has changed and we | |
1510 | must spill the register. Also, recompute the number of eliminable | |
1511 | registers and see if the frame pointer is needed; it is if there is | |
1512 | no elimination of the frame pointer that we can perform. */ | |
1513 | ||
1514 | frame_pointer_needed = 1; | |
1515 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1516 | { | |
1517 | if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM) | |
1518 | frame_pointer_needed = 0; | |
1519 | ||
1520 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
1521 | { | |
1522 | ep->can_eliminate_previous = 0; | |
1523 | spill_hard_reg (ep->from, global, dumpfile, 1); | |
1524 | regs_ever_live[ep->from] = 1; | |
1525 | something_changed = 1; | |
1526 | num_eliminable--; | |
1527 | } | |
1528 | } | |
1529 | ||
1530 | /* If all needs are met, we win. */ | |
1531 | ||
1532 | for (i = 0; i < N_REG_CLASSES; i++) | |
1533 | if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0) | |
1534 | break; | |
1535 | if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed) | |
1536 | break; | |
1537 | ||
1538 | /* Not all needs are met; must spill more hard regs. */ | |
1539 | ||
1540 | /* If any element of basic_block_needs changed from 0 to 1, | |
1541 | re-spill all the regs already spilled. This may spill | |
1542 | additional pseudos that didn't spill before. */ | |
1543 | ||
1544 | if (new_basic_block_needs) | |
1545 | for (i = 0; i < n_spills; i++) | |
1546 | something_changed | |
1547 | |= spill_hard_reg (spill_regs[i], global, dumpfile, 0); | |
1548 | ||
1549 | /* Now find more reload regs to satisfy the remaining need | |
1550 | Do it by ascending class number, since otherwise a reg | |
1551 | might be spilled for a big class and might fail to count | |
1552 | for a smaller class even though it belongs to that class. | |
1553 | ||
1554 | Count spilled regs in `spills', and add entries to | |
1555 | `spill_regs' and `spill_reg_order'. | |
1556 | ||
1557 | ??? Note there is a problem here. | |
1558 | When there is a need for a group in a high-numbered class, | |
1559 | and also need for non-group regs that come from a lower class, | |
1560 | the non-group regs are chosen first. If there aren't many regs, | |
1561 | they might leave no room for a group. | |
1562 | ||
1563 | This was happening on the 386. To fix it, we added the code | |
1564 | that calls possible_group_p, so that the lower class won't | |
1565 | break up the last possible group. | |
1566 | ||
1567 | Really fixing the problem would require changes above | |
1568 | in counting the regs already spilled, and in choose_reload_regs. | |
1569 | It might be hard to avoid introducing bugs there. */ | |
1570 | ||
1571 | for (class = 0; class < N_REG_CLASSES; class++) | |
1572 | { | |
1573 | /* First get the groups of registers. | |
1574 | If we got single registers first, we might fragment | |
1575 | possible groups. */ | |
1576 | while (max_groups[class] > 0) | |
1577 | { | |
1578 | /* If any single spilled regs happen to form groups, | |
1579 | count them now. Maybe we don't really need | |
1580 | to spill another group. */ | |
1581 | count_possible_groups (group_size, group_mode, max_groups); | |
1582 | ||
1583 | /* Groups of size 2 (the only groups used on most machines) | |
1584 | are treated specially. */ | |
1585 | if (group_size[class] == 2) | |
1586 | { | |
1587 | /* First, look for a register that will complete a group. */ | |
1588 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1589 | { | |
1590 | int j = potential_reload_regs[i]; | |
1591 | int other; | |
1592 | if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j) | |
1593 | && | |
1594 | ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0) | |
1595 | && TEST_HARD_REG_BIT (reg_class_contents[class], j) | |
1596 | && TEST_HARD_REG_BIT (reg_class_contents[class], other) | |
1597 | && HARD_REGNO_MODE_OK (other, group_mode[class]) | |
1598 | && ! TEST_HARD_REG_BIT (counted_for_nongroups, | |
1599 | other) | |
1600 | /* We don't want one part of another group. | |
1601 | We could get "two groups" that overlap! */ | |
1602 | && ! TEST_HARD_REG_BIT (counted_for_groups, other)) | |
1603 | || | |
1604 | (j < FIRST_PSEUDO_REGISTER - 1 | |
1605 | && (other = j + 1, spill_reg_order[other] >= 0) | |
1606 | && TEST_HARD_REG_BIT (reg_class_contents[class], j) | |
1607 | && TEST_HARD_REG_BIT (reg_class_contents[class], other) | |
1608 | && HARD_REGNO_MODE_OK (j, group_mode[class]) | |
1609 | && ! TEST_HARD_REG_BIT (counted_for_nongroups, | |
1610 | other) | |
1611 | && ! TEST_HARD_REG_BIT (counted_for_groups, | |
1612 | other)))) | |
1613 | { | |
1614 | register enum reg_class *p; | |
1615 | ||
1616 | /* We have found one that will complete a group, | |
1617 | so count off one group as provided. */ | |
1618 | max_groups[class]--; | |
1619 | p = reg_class_superclasses[class]; | |
1620 | while (*p != LIM_REG_CLASSES) | |
1621 | max_groups[(int) *p++]--; | |
1622 | ||
1623 | /* Indicate both these regs are part of a group. */ | |
1624 | SET_HARD_REG_BIT (counted_for_groups, j); | |
1625 | SET_HARD_REG_BIT (counted_for_groups, other); | |
1626 | break; | |
1627 | } | |
1628 | } | |
1629 | /* We can't complete a group, so start one. */ | |
1630 | if (i == FIRST_PSEUDO_REGISTER) | |
1631 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1632 | { | |
1633 | int j = potential_reload_regs[i]; | |
1634 | if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER | |
1635 | && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0 | |
1636 | && TEST_HARD_REG_BIT (reg_class_contents[class], j) | |
1637 | && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1) | |
1638 | && HARD_REGNO_MODE_OK (j, group_mode[class]) | |
1639 | && ! TEST_HARD_REG_BIT (counted_for_nongroups, | |
1640 | j + 1)) | |
1641 | break; | |
1642 | } | |
1643 | ||
1644 | /* I should be the index in potential_reload_regs | |
1645 | of the new reload reg we have found. */ | |
1646 | ||
5352b11a RS |
1647 | if (i >= FIRST_PSEUDO_REGISTER) |
1648 | { | |
1649 | /* There are no groups left to spill. */ | |
1650 | spill_failure (max_groups_insn[class]); | |
1651 | failure = 1; | |
1652 | goto failed; | |
1653 | } | |
1654 | else | |
1655 | something_changed | |
fb3821f7 | 1656 | |= new_spill_reg (i, class, max_needs, NULL_PTR, |
5352b11a | 1657 | global, dumpfile); |
32131a9c RK |
1658 | } |
1659 | else | |
1660 | { | |
1661 | /* For groups of more than 2 registers, | |
1662 | look for a sufficient sequence of unspilled registers, | |
1663 | and spill them all at once. */ | |
1664 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1665 | { | |
1666 | int j = potential_reload_regs[i]; | |
1667 | int k; | |
9d1a4667 RS |
1668 | if (j >= 0 |
1669 | && j + group_size[class] <= FIRST_PSEUDO_REGISTER | |
32131a9c RK |
1670 | && HARD_REGNO_MODE_OK (j, group_mode[class])) |
1671 | { | |
1672 | /* Check each reg in the sequence. */ | |
1673 | for (k = 0; k < group_size[class]; k++) | |
1674 | if (! (spill_reg_order[j + k] < 0 | |
1675 | && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k) | |
1676 | && TEST_HARD_REG_BIT (reg_class_contents[class], j + k))) | |
1677 | break; | |
1678 | /* We got a full sequence, so spill them all. */ | |
1679 | if (k == group_size[class]) | |
1680 | { | |
1681 | register enum reg_class *p; | |
1682 | for (k = 0; k < group_size[class]; k++) | |
1683 | { | |
1684 | int idx; | |
1685 | SET_HARD_REG_BIT (counted_for_groups, j + k); | |
1686 | for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) | |
1687 | if (potential_reload_regs[idx] == j + k) | |
1688 | break; | |
9d1a4667 RS |
1689 | something_changed |
1690 | |= new_spill_reg (idx, class, | |
1691 | max_needs, NULL_PTR, | |
1692 | global, dumpfile); | |
32131a9c RK |
1693 | } |
1694 | ||
1695 | /* We have found one that will complete a group, | |
1696 | so count off one group as provided. */ | |
1697 | max_groups[class]--; | |
1698 | p = reg_class_superclasses[class]; | |
1699 | while (*p != LIM_REG_CLASSES) | |
1700 | max_groups[(int) *p++]--; | |
1701 | ||
1702 | break; | |
1703 | } | |
1704 | } | |
1705 | } | |
fa52261e | 1706 | /* We couldn't find any registers for this reload. |
9d1a4667 RS |
1707 | Avoid going into an infinite loop. */ |
1708 | if (i >= FIRST_PSEUDO_REGISTER) | |
1709 | { | |
1710 | /* There are no groups left. */ | |
1711 | spill_failure (max_groups_insn[class]); | |
1712 | failure = 1; | |
1713 | goto failed; | |
1714 | } | |
32131a9c RK |
1715 | } |
1716 | } | |
1717 | ||
1718 | /* Now similarly satisfy all need for single registers. */ | |
1719 | ||
1720 | while (max_needs[class] > 0 || max_nongroups[class] > 0) | |
1721 | { | |
1722 | /* Consider the potential reload regs that aren't | |
1723 | yet in use as reload regs, in order of preference. | |
1724 | Find the most preferred one that's in this class. */ | |
1725 | ||
1726 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1727 | if (potential_reload_regs[i] >= 0 | |
1728 | && TEST_HARD_REG_BIT (reg_class_contents[class], | |
1729 | potential_reload_regs[i]) | |
1730 | /* If this reg will not be available for groups, | |
1731 | pick one that does not foreclose possible groups. | |
1732 | This is a kludge, and not very general, | |
1733 | but it should be sufficient to make the 386 work, | |
1734 | and the problem should not occur on machines with | |
1735 | more registers. */ | |
1736 | && (max_nongroups[class] == 0 | |
1737 | || possible_group_p (potential_reload_regs[i], max_groups))) | |
1738 | break; | |
1739 | ||
e404a39a RK |
1740 | /* If we couldn't get a register, try to get one even if we |
1741 | might foreclose possible groups. This may cause problems | |
1742 | later, but that's better than aborting now, since it is | |
1743 | possible that we will, in fact, be able to form the needed | |
1744 | group even with this allocation. */ | |
1745 | ||
1746 | if (i >= FIRST_PSEUDO_REGISTER | |
1747 | && (asm_noperands (max_needs[class] > 0 | |
1748 | ? max_needs_insn[class] | |
1749 | : max_nongroups_insn[class]) | |
1750 | < 0)) | |
1751 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1752 | if (potential_reload_regs[i] >= 0 | |
1753 | && TEST_HARD_REG_BIT (reg_class_contents[class], | |
1754 | potential_reload_regs[i])) | |
1755 | break; | |
1756 | ||
32131a9c RK |
1757 | /* I should be the index in potential_reload_regs |
1758 | of the new reload reg we have found. */ | |
1759 | ||
5352b11a RS |
1760 | if (i >= FIRST_PSEUDO_REGISTER) |
1761 | { | |
1762 | /* There are no possible registers left to spill. */ | |
1763 | spill_failure (max_needs[class] > 0 ? max_needs_insn[class] | |
1764 | : max_nongroups_insn[class]); | |
1765 | failure = 1; | |
1766 | goto failed; | |
1767 | } | |
1768 | else | |
1769 | something_changed | |
1770 | |= new_spill_reg (i, class, max_needs, max_nongroups, | |
1771 | global, dumpfile); | |
32131a9c RK |
1772 | } |
1773 | } | |
1774 | } | |
1775 | ||
1776 | /* If global-alloc was run, notify it of any register eliminations we have | |
1777 | done. */ | |
1778 | if (global) | |
1779 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1780 | if (ep->can_eliminate) | |
1781 | mark_elimination (ep->from, ep->to); | |
1782 | ||
32131a9c | 1783 | /* Insert code to save and restore call-clobbered hard regs |
a8efe40d RK |
1784 | around calls. Tell if what mode to use so that we will process |
1785 | those insns in reload_as_needed if we have to. */ | |
32131a9c RK |
1786 | |
1787 | if (caller_save_needed) | |
a8efe40d RK |
1788 | save_call_clobbered_regs (num_eliminable ? QImode |
1789 | : caller_save_spill_class != NO_REGS ? HImode | |
1790 | : VOIDmode); | |
32131a9c RK |
1791 | |
1792 | /* If a pseudo has no hard reg, delete the insns that made the equivalence. | |
1793 | If that insn didn't set the register (i.e., it copied the register to | |
1794 | memory), just delete that insn instead of the equivalencing insn plus | |
1795 | anything now dead. If we call delete_dead_insn on that insn, we may | |
1796 | delete the insn that actually sets the register if the register die | |
1797 | there and that is incorrect. */ | |
1798 | ||
1799 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1800 | if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0 | |
1801 | && GET_CODE (reg_equiv_init[i]) != NOTE) | |
1802 | { | |
1803 | if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i]))) | |
1804 | delete_dead_insn (reg_equiv_init[i]); | |
1805 | else | |
1806 | { | |
1807 | PUT_CODE (reg_equiv_init[i], NOTE); | |
1808 | NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0; | |
1809 | NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED; | |
1810 | } | |
1811 | } | |
1812 | ||
1813 | /* Use the reload registers where necessary | |
1814 | by generating move instructions to move the must-be-register | |
1815 | values into or out of the reload registers. */ | |
1816 | ||
a8efe40d RK |
1817 | if (something_needs_reloads || something_needs_elimination |
1818 | || (caller_save_needed && num_eliminable) | |
1819 | || caller_save_spill_class != NO_REGS) | |
32131a9c RK |
1820 | reload_as_needed (first, global); |
1821 | ||
2a1f8b6b | 1822 | /* If we were able to eliminate the frame pointer, show that it is no |
33edf7f2 | 1823 | longer live at the start of any basic block. If it is live by |
2a1f8b6b RK |
1824 | virtue of being in a pseudo, that pseudo will be marked live |
1825 | and hence the frame pointer will be known to be live via that | |
1826 | pseudo. */ | |
1827 | ||
1828 | if (! frame_pointer_needed) | |
1829 | for (i = 0; i < n_basic_blocks; i++) | |
1830 | basic_block_live_at_start[i][FRAME_POINTER_REGNUM / REGSET_ELT_BITS] | |
1831 | &= ~ ((REGSET_ELT_TYPE) 1 << (FRAME_POINTER_REGNUM % REGSET_ELT_BITS)); | |
1832 | ||
32131a9c RK |
1833 | reload_in_progress = 0; |
1834 | ||
5352b11a RS |
1835 | /* Come here (with failure set nonzero) if we can't get enough spill regs |
1836 | and we decide not to abort about it. */ | |
1837 | failed: | |
1838 | ||
32131a9c RK |
1839 | /* Now eliminate all pseudo regs by modifying them into |
1840 | their equivalent memory references. | |
1841 | The REG-rtx's for the pseudos are modified in place, | |
1842 | so all insns that used to refer to them now refer to memory. | |
1843 | ||
1844 | For a reg that has a reg_equiv_address, all those insns | |
1845 | were changed by reloading so that no insns refer to it any longer; | |
1846 | but the DECL_RTL of a variable decl may refer to it, | |
1847 | and if so this causes the debugging info to mention the variable. */ | |
1848 | ||
1849 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1850 | { | |
1851 | rtx addr = 0; | |
ab1fd483 | 1852 | int in_struct = 0; |
32131a9c | 1853 | if (reg_equiv_mem[i]) |
ab1fd483 RS |
1854 | { |
1855 | addr = XEXP (reg_equiv_mem[i], 0); | |
1856 | in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]); | |
1857 | } | |
32131a9c RK |
1858 | if (reg_equiv_address[i]) |
1859 | addr = reg_equiv_address[i]; | |
1860 | if (addr) | |
1861 | { | |
1862 | if (reg_renumber[i] < 0) | |
1863 | { | |
1864 | rtx reg = regno_reg_rtx[i]; | |
1865 | XEXP (reg, 0) = addr; | |
1866 | REG_USERVAR_P (reg) = 0; | |
ab1fd483 | 1867 | MEM_IN_STRUCT_P (reg) = in_struct; |
32131a9c RK |
1868 | PUT_CODE (reg, MEM); |
1869 | } | |
1870 | else if (reg_equiv_mem[i]) | |
1871 | XEXP (reg_equiv_mem[i], 0) = addr; | |
1872 | } | |
1873 | } | |
1874 | ||
1875 | #ifdef PRESERVE_DEATH_INFO_REGNO_P | |
1876 | /* Make a pass over all the insns and remove death notes for things that | |
1877 | are no longer registers or no longer die in the insn (e.g., an input | |
1878 | and output pseudo being tied). */ | |
1879 | ||
1880 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
1881 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
1882 | { | |
1883 | rtx note, next; | |
1884 | ||
1885 | for (note = REG_NOTES (insn); note; note = next) | |
1886 | { | |
1887 | next = XEXP (note, 1); | |
1888 | if (REG_NOTE_KIND (note) == REG_DEAD | |
1889 | && (GET_CODE (XEXP (note, 0)) != REG | |
1890 | || reg_set_p (XEXP (note, 0), PATTERN (insn)))) | |
1891 | remove_note (insn, note); | |
1892 | } | |
1893 | } | |
1894 | #endif | |
1895 | ||
1896 | /* Indicate that we no longer have known memory locations or constants. */ | |
1897 | reg_equiv_constant = 0; | |
1898 | reg_equiv_memory_loc = 0; | |
5352b11a RS |
1899 | |
1900 | return failure; | |
32131a9c RK |
1901 | } |
1902 | \f | |
1903 | /* Nonzero if, after spilling reg REGNO for non-groups, | |
1904 | it will still be possible to find a group if we still need one. */ | |
1905 | ||
1906 | static int | |
1907 | possible_group_p (regno, max_groups) | |
1908 | int regno; | |
1909 | int *max_groups; | |
1910 | { | |
1911 | int i; | |
1912 | int class = (int) NO_REGS; | |
1913 | ||
1914 | for (i = 0; i < (int) N_REG_CLASSES; i++) | |
1915 | if (max_groups[i] > 0) | |
1916 | { | |
1917 | class = i; | |
1918 | break; | |
1919 | } | |
1920 | ||
1921 | if (class == (int) NO_REGS) | |
1922 | return 1; | |
1923 | ||
1924 | /* Consider each pair of consecutive registers. */ | |
1925 | for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++) | |
1926 | { | |
1927 | /* Ignore pairs that include reg REGNO. */ | |
1928 | if (i == regno || i + 1 == regno) | |
1929 | continue; | |
1930 | ||
1931 | /* Ignore pairs that are outside the class that needs the group. | |
1932 | ??? Here we fail to handle the case where two different classes | |
1933 | independently need groups. But this never happens with our | |
1934 | current machine descriptions. */ | |
1935 | if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i) | |
1936 | && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1))) | |
1937 | continue; | |
1938 | ||
1939 | /* A pair of consecutive regs we can still spill does the trick. */ | |
1940 | if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0 | |
1941 | && ! TEST_HARD_REG_BIT (bad_spill_regs, i) | |
1942 | && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)) | |
1943 | return 1; | |
1944 | ||
1945 | /* A pair of one already spilled and one we can spill does it | |
1946 | provided the one already spilled is not otherwise reserved. */ | |
1947 | if (spill_reg_order[i] < 0 | |
1948 | && ! TEST_HARD_REG_BIT (bad_spill_regs, i) | |
1949 | && spill_reg_order[i + 1] >= 0 | |
1950 | && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1) | |
1951 | && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1)) | |
1952 | return 1; | |
1953 | if (spill_reg_order[i + 1] < 0 | |
1954 | && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1) | |
1955 | && spill_reg_order[i] >= 0 | |
1956 | && ! TEST_HARD_REG_BIT (counted_for_groups, i) | |
1957 | && ! TEST_HARD_REG_BIT (counted_for_nongroups, i)) | |
1958 | return 1; | |
1959 | } | |
1960 | ||
1961 | return 0; | |
1962 | } | |
1963 | \f | |
1964 | /* Count any groups that can be formed from the registers recently spilled. | |
1965 | This is done class by class, in order of ascending class number. */ | |
1966 | ||
1967 | static void | |
1968 | count_possible_groups (group_size, group_mode, max_groups) | |
1969 | int *group_size, *max_groups; | |
1970 | enum machine_mode *group_mode; | |
1971 | { | |
1972 | int i; | |
1973 | /* Now find all consecutive groups of spilled registers | |
1974 | and mark each group off against the need for such groups. | |
1975 | But don't count them against ordinary need, yet. */ | |
1976 | ||
1977 | for (i = 0; i < N_REG_CLASSES; i++) | |
1978 | if (group_size[i] > 1) | |
1979 | { | |
1980 | char regmask[FIRST_PSEUDO_REGISTER]; | |
1981 | int j; | |
1982 | ||
1983 | bzero (regmask, sizeof regmask); | |
1984 | /* Make a mask of all the regs that are spill regs in class I. */ | |
1985 | for (j = 0; j < n_spills; j++) | |
1986 | if (TEST_HARD_REG_BIT (reg_class_contents[i], spill_regs[j]) | |
1987 | && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[j]) | |
1988 | && ! TEST_HARD_REG_BIT (counted_for_nongroups, | |
1989 | spill_regs[j])) | |
1990 | regmask[spill_regs[j]] = 1; | |
1991 | /* Find each consecutive group of them. */ | |
1992 | for (j = 0; j < FIRST_PSEUDO_REGISTER && max_groups[i] > 0; j++) | |
1993 | if (regmask[j] && j + group_size[i] <= FIRST_PSEUDO_REGISTER | |
1994 | /* Next line in case group-mode for this class | |
1995 | demands an even-odd pair. */ | |
1996 | && HARD_REGNO_MODE_OK (j, group_mode[i])) | |
1997 | { | |
1998 | int k; | |
1999 | for (k = 1; k < group_size[i]; k++) | |
2000 | if (! regmask[j + k]) | |
2001 | break; | |
2002 | if (k == group_size[i]) | |
2003 | { | |
2004 | /* We found a group. Mark it off against this class's | |
2005 | need for groups, and against each superclass too. */ | |
2006 | register enum reg_class *p; | |
2007 | max_groups[i]--; | |
2008 | p = reg_class_superclasses[i]; | |
2009 | while (*p != LIM_REG_CLASSES) | |
2010 | max_groups[(int) *p++]--; | |
a8fdc208 | 2011 | /* Don't count these registers again. */ |
32131a9c RK |
2012 | for (k = 0; k < group_size[i]; k++) |
2013 | SET_HARD_REG_BIT (counted_for_groups, j + k); | |
2014 | } | |
fa52261e RS |
2015 | /* Skip to the last reg in this group. When j is incremented |
2016 | above, it will then point to the first reg of the next | |
2017 | possible group. */ | |
2018 | j += k - 1; | |
32131a9c RK |
2019 | } |
2020 | } | |
2021 | ||
2022 | } | |
2023 | \f | |
2024 | /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is | |
2025 | another mode that needs to be reloaded for the same register class CLASS. | |
2026 | If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail. | |
2027 | ALLOCATE_MODE will never be smaller than OTHER_MODE. | |
2028 | ||
2029 | This code used to also fail if any reg in CLASS allows OTHER_MODE but not | |
2030 | ALLOCATE_MODE. This test is unnecessary, because we will never try to put | |
2031 | something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this | |
2032 | causes unnecessary failures on machines requiring alignment of register | |
2033 | groups when the two modes are different sizes, because the larger mode has | |
2034 | more strict alignment rules than the smaller mode. */ | |
2035 | ||
2036 | static int | |
2037 | modes_equiv_for_class_p (allocate_mode, other_mode, class) | |
2038 | enum machine_mode allocate_mode, other_mode; | |
2039 | enum reg_class class; | |
2040 | { | |
2041 | register int regno; | |
2042 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
2043 | { | |
2044 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno) | |
2045 | && HARD_REGNO_MODE_OK (regno, allocate_mode) | |
2046 | && ! HARD_REGNO_MODE_OK (regno, other_mode)) | |
2047 | return 0; | |
2048 | } | |
2049 | return 1; | |
2050 | } | |
2051 | ||
5352b11a RS |
2052 | /* Handle the failure to find a register to spill. |
2053 | INSN should be one of the insns which needed this particular spill reg. */ | |
2054 | ||
2055 | static void | |
2056 | spill_failure (insn) | |
2057 | rtx insn; | |
2058 | { | |
2059 | if (asm_noperands (PATTERN (insn)) >= 0) | |
2060 | error_for_asm (insn, "`asm' needs too many reloads"); | |
2061 | else | |
2062 | abort (); | |
2063 | } | |
2064 | ||
32131a9c RK |
2065 | /* Add a new register to the tables of available spill-registers |
2066 | (as well as spilling all pseudos allocated to the register). | |
2067 | I is the index of this register in potential_reload_regs. | |
2068 | CLASS is the regclass whose need is being satisfied. | |
2069 | MAX_NEEDS and MAX_NONGROUPS are the vectors of needs, | |
2070 | so that this register can count off against them. | |
2071 | MAX_NONGROUPS is 0 if this register is part of a group. | |
2072 | GLOBAL and DUMPFILE are the same as the args that `reload' got. */ | |
2073 | ||
2074 | static int | |
2075 | new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile) | |
2076 | int i; | |
2077 | int class; | |
2078 | int *max_needs; | |
2079 | int *max_nongroups; | |
2080 | int global; | |
2081 | FILE *dumpfile; | |
2082 | { | |
2083 | register enum reg_class *p; | |
2084 | int val; | |
2085 | int regno = potential_reload_regs[i]; | |
2086 | ||
2087 | if (i >= FIRST_PSEUDO_REGISTER) | |
2088 | abort (); /* Caller failed to find any register. */ | |
2089 | ||
2090 | if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno)) | |
2091 | fatal ("fixed or forbidden register was spilled.\n\ | |
2092 | This may be due to a compiler bug or to impossible asm statements."); | |
2093 | ||
2094 | /* Make reg REGNO an additional reload reg. */ | |
2095 | ||
2096 | potential_reload_regs[i] = -1; | |
2097 | spill_regs[n_spills] = regno; | |
2098 | spill_reg_order[regno] = n_spills; | |
2099 | if (dumpfile) | |
2100 | fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]); | |
2101 | ||
2102 | /* Clear off the needs we just satisfied. */ | |
2103 | ||
2104 | max_needs[class]--; | |
2105 | p = reg_class_superclasses[class]; | |
2106 | while (*p != LIM_REG_CLASSES) | |
2107 | max_needs[(int) *p++]--; | |
2108 | ||
2109 | if (max_nongroups && max_nongroups[class] > 0) | |
2110 | { | |
2111 | SET_HARD_REG_BIT (counted_for_nongroups, regno); | |
2112 | max_nongroups[class]--; | |
2113 | p = reg_class_superclasses[class]; | |
2114 | while (*p != LIM_REG_CLASSES) | |
2115 | max_nongroups[(int) *p++]--; | |
2116 | } | |
2117 | ||
2118 | /* Spill every pseudo reg that was allocated to this reg | |
2119 | or to something that overlaps this reg. */ | |
2120 | ||
2121 | val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0); | |
2122 | ||
2123 | /* If there are some registers still to eliminate and this register | |
2124 | wasn't ever used before, additional stack space may have to be | |
2125 | allocated to store this register. Thus, we may have changed the offset | |
2126 | between the stack and frame pointers, so mark that something has changed. | |
2127 | (If new pseudos were spilled, thus requiring more space, VAL would have | |
2128 | been set non-zero by the call to spill_hard_reg above since additional | |
2129 | reloads may be needed in that case. | |
2130 | ||
2131 | One might think that we need only set VAL to 1 if this is a call-used | |
2132 | register. However, the set of registers that must be saved by the | |
2133 | prologue is not identical to the call-used set. For example, the | |
2134 | register used by the call insn for the return PC is a call-used register, | |
2135 | but must be saved by the prologue. */ | |
2136 | if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]]) | |
2137 | val = 1; | |
2138 | ||
2139 | regs_ever_live[spill_regs[n_spills]] = 1; | |
2140 | n_spills++; | |
2141 | ||
2142 | return val; | |
2143 | } | |
2144 | \f | |
2145 | /* Delete an unneeded INSN and any previous insns who sole purpose is loading | |
2146 | data that is dead in INSN. */ | |
2147 | ||
2148 | static void | |
2149 | delete_dead_insn (insn) | |
2150 | rtx insn; | |
2151 | { | |
2152 | rtx prev = prev_real_insn (insn); | |
2153 | rtx prev_dest; | |
2154 | ||
2155 | /* If the previous insn sets a register that dies in our insn, delete it | |
2156 | too. */ | |
2157 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
2158 | && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG) | |
2159 | && reg_mentioned_p (prev_dest, PATTERN (insn)) | |
2160 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))) | |
2161 | delete_dead_insn (prev); | |
2162 | ||
2163 | PUT_CODE (insn, NOTE); | |
2164 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
2165 | NOTE_SOURCE_FILE (insn) = 0; | |
2166 | } | |
2167 | ||
2168 | /* Modify the home of pseudo-reg I. | |
2169 | The new home is present in reg_renumber[I]. | |
2170 | ||
2171 | FROM_REG may be the hard reg that the pseudo-reg is being spilled from; | |
2172 | or it may be -1, meaning there is none or it is not relevant. | |
2173 | This is used so that all pseudos spilled from a given hard reg | |
2174 | can share one stack slot. */ | |
2175 | ||
2176 | static void | |
2177 | alter_reg (i, from_reg) | |
2178 | register int i; | |
2179 | int from_reg; | |
2180 | { | |
2181 | /* When outputting an inline function, this can happen | |
2182 | for a reg that isn't actually used. */ | |
2183 | if (regno_reg_rtx[i] == 0) | |
2184 | return; | |
2185 | ||
2186 | /* If the reg got changed to a MEM at rtl-generation time, | |
2187 | ignore it. */ | |
2188 | if (GET_CODE (regno_reg_rtx[i]) != REG) | |
2189 | return; | |
2190 | ||
2191 | /* Modify the reg-rtx to contain the new hard reg | |
2192 | number or else to contain its pseudo reg number. */ | |
2193 | REGNO (regno_reg_rtx[i]) | |
2194 | = reg_renumber[i] >= 0 ? reg_renumber[i] : i; | |
2195 | ||
2196 | /* If we have a pseudo that is needed but has no hard reg or equivalent, | |
2197 | allocate a stack slot for it. */ | |
2198 | ||
2199 | if (reg_renumber[i] < 0 | |
2200 | && reg_n_refs[i] > 0 | |
2201 | && reg_equiv_constant[i] == 0 | |
2202 | && reg_equiv_memory_loc[i] == 0) | |
2203 | { | |
2204 | register rtx x; | |
2205 | int inherent_size = PSEUDO_REGNO_BYTES (i); | |
2206 | int total_size = MAX (inherent_size, reg_max_ref_width[i]); | |
2207 | int adjust = 0; | |
2208 | ||
2209 | /* Each pseudo reg has an inherent size which comes from its own mode, | |
2210 | and a total size which provides room for paradoxical subregs | |
2211 | which refer to the pseudo reg in wider modes. | |
2212 | ||
2213 | We can use a slot already allocated if it provides both | |
2214 | enough inherent space and enough total space. | |
2215 | Otherwise, we allocate a new slot, making sure that it has no less | |
2216 | inherent space, and no less total space, then the previous slot. */ | |
2217 | if (from_reg == -1) | |
2218 | { | |
2219 | /* No known place to spill from => no slot to reuse. */ | |
2220 | x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1); | |
2221 | #if BYTES_BIG_ENDIAN | |
2222 | /* Cancel the big-endian correction done in assign_stack_local. | |
2223 | Get the address of the beginning of the slot. | |
2224 | This is so we can do a big-endian correction unconditionally | |
2225 | below. */ | |
2226 | adjust = inherent_size - total_size; | |
2227 | #endif | |
2228 | } | |
2229 | /* Reuse a stack slot if possible. */ | |
2230 | else if (spill_stack_slot[from_reg] != 0 | |
2231 | && spill_stack_slot_width[from_reg] >= total_size | |
2232 | && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
2233 | >= inherent_size)) | |
2234 | x = spill_stack_slot[from_reg]; | |
2235 | /* Allocate a bigger slot. */ | |
2236 | else | |
2237 | { | |
2238 | /* Compute maximum size needed, both for inherent size | |
2239 | and for total size. */ | |
2240 | enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); | |
2241 | if (spill_stack_slot[from_reg]) | |
2242 | { | |
2243 | if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
2244 | > inherent_size) | |
2245 | mode = GET_MODE (spill_stack_slot[from_reg]); | |
2246 | if (spill_stack_slot_width[from_reg] > total_size) | |
2247 | total_size = spill_stack_slot_width[from_reg]; | |
2248 | } | |
2249 | /* Make a slot with that size. */ | |
2250 | x = assign_stack_local (mode, total_size, -1); | |
2251 | #if BYTES_BIG_ENDIAN | |
2252 | /* Cancel the big-endian correction done in assign_stack_local. | |
2253 | Get the address of the beginning of the slot. | |
2254 | This is so we can do a big-endian correction unconditionally | |
2255 | below. */ | |
2256 | adjust = GET_MODE_SIZE (mode) - total_size; | |
2257 | #endif | |
2258 | spill_stack_slot[from_reg] = x; | |
2259 | spill_stack_slot_width[from_reg] = total_size; | |
2260 | } | |
2261 | ||
2262 | #if BYTES_BIG_ENDIAN | |
2263 | /* On a big endian machine, the "address" of the slot | |
2264 | is the address of the low part that fits its inherent mode. */ | |
2265 | if (inherent_size < total_size) | |
2266 | adjust += (total_size - inherent_size); | |
2267 | #endif /* BYTES_BIG_ENDIAN */ | |
2268 | ||
2269 | /* If we have any adjustment to make, or if the stack slot is the | |
2270 | wrong mode, make a new stack slot. */ | |
2271 | if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i])) | |
2272 | { | |
2273 | x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]), | |
2274 | plus_constant (XEXP (x, 0), adjust)); | |
2275 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]); | |
2276 | } | |
2277 | ||
2278 | /* Save the stack slot for later. */ | |
2279 | reg_equiv_memory_loc[i] = x; | |
2280 | } | |
2281 | } | |
2282 | ||
2283 | /* Mark the slots in regs_ever_live for the hard regs | |
2284 | used by pseudo-reg number REGNO. */ | |
2285 | ||
2286 | void | |
2287 | mark_home_live (regno) | |
2288 | int regno; | |
2289 | { | |
2290 | register int i, lim; | |
2291 | i = reg_renumber[regno]; | |
2292 | if (i < 0) | |
2293 | return; | |
2294 | lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno)); | |
2295 | while (i < lim) | |
2296 | regs_ever_live[i++] = 1; | |
2297 | } | |
2298 | \f | |
2299 | /* This function handles the tracking of elimination offsets around branches. | |
2300 | ||
2301 | X is a piece of RTL being scanned. | |
2302 | ||
2303 | INSN is the insn that it came from, if any. | |
2304 | ||
2305 | INITIAL_P is non-zero if we are to set the offset to be the initial | |
2306 | offset and zero if we are setting the offset of the label to be the | |
2307 | current offset. */ | |
2308 | ||
2309 | static void | |
2310 | set_label_offsets (x, insn, initial_p) | |
2311 | rtx x; | |
2312 | rtx insn; | |
2313 | int initial_p; | |
2314 | { | |
2315 | enum rtx_code code = GET_CODE (x); | |
2316 | rtx tem; | |
2317 | int i; | |
2318 | struct elim_table *p; | |
2319 | ||
2320 | switch (code) | |
2321 | { | |
2322 | case LABEL_REF: | |
8be386d9 RS |
2323 | if (LABEL_REF_NONLOCAL_P (x)) |
2324 | return; | |
2325 | ||
32131a9c RK |
2326 | x = XEXP (x, 0); |
2327 | ||
2328 | /* ... fall through ... */ | |
2329 | ||
2330 | case CODE_LABEL: | |
2331 | /* If we know nothing about this label, set the desired offsets. Note | |
2332 | that this sets the offset at a label to be the offset before a label | |
2333 | if we don't know anything about the label. This is not correct for | |
2334 | the label after a BARRIER, but is the best guess we can make. If | |
2335 | we guessed wrong, we will suppress an elimination that might have | |
2336 | been possible had we been able to guess correctly. */ | |
2337 | ||
2338 | if (! offsets_known_at[CODE_LABEL_NUMBER (x)]) | |
2339 | { | |
2340 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
2341 | offsets_at[CODE_LABEL_NUMBER (x)][i] | |
2342 | = (initial_p ? reg_eliminate[i].initial_offset | |
2343 | : reg_eliminate[i].offset); | |
2344 | offsets_known_at[CODE_LABEL_NUMBER (x)] = 1; | |
2345 | } | |
2346 | ||
2347 | /* Otherwise, if this is the definition of a label and it is | |
d45cf215 | 2348 | preceded by a BARRIER, set our offsets to the known offset of |
32131a9c RK |
2349 | that label. */ |
2350 | ||
2351 | else if (x == insn | |
2352 | && (tem = prev_nonnote_insn (insn)) != 0 | |
2353 | && GET_CODE (tem) == BARRIER) | |
2a4b5f3b RK |
2354 | { |
2355 | num_not_at_initial_offset = 0; | |
2356 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
2357 | { | |
2358 | reg_eliminate[i].offset = reg_eliminate[i].previous_offset | |
2359 | = offsets_at[CODE_LABEL_NUMBER (x)][i]; | |
1d0d98f3 RK |
2360 | if (reg_eliminate[i].can_eliminate |
2361 | && (reg_eliminate[i].offset | |
2362 | != reg_eliminate[i].initial_offset)) | |
2a4b5f3b RK |
2363 | num_not_at_initial_offset++; |
2364 | } | |
2365 | } | |
32131a9c RK |
2366 | |
2367 | else | |
2368 | /* If neither of the above cases is true, compare each offset | |
2369 | with those previously recorded and suppress any eliminations | |
2370 | where the offsets disagree. */ | |
a8fdc208 | 2371 | |
32131a9c RK |
2372 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) |
2373 | if (offsets_at[CODE_LABEL_NUMBER (x)][i] | |
2374 | != (initial_p ? reg_eliminate[i].initial_offset | |
2375 | : reg_eliminate[i].offset)) | |
2376 | reg_eliminate[i].can_eliminate = 0; | |
2377 | ||
2378 | return; | |
2379 | ||
2380 | case JUMP_INSN: | |
2381 | set_label_offsets (PATTERN (insn), insn, initial_p); | |
2382 | ||
2383 | /* ... fall through ... */ | |
2384 | ||
2385 | case INSN: | |
2386 | case CALL_INSN: | |
2387 | /* Any labels mentioned in REG_LABEL notes can be branched to indirectly | |
2388 | and hence must have all eliminations at their initial offsets. */ | |
2389 | for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) | |
2390 | if (REG_NOTE_KIND (tem) == REG_LABEL) | |
2391 | set_label_offsets (XEXP (tem, 0), insn, 1); | |
2392 | return; | |
2393 | ||
2394 | case ADDR_VEC: | |
2395 | case ADDR_DIFF_VEC: | |
2396 | /* Each of the labels in the address vector must be at their initial | |
2397 | offsets. We want the first first for ADDR_VEC and the second | |
2398 | field for ADDR_DIFF_VEC. */ | |
2399 | ||
2400 | for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++) | |
2401 | set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), | |
2402 | insn, initial_p); | |
2403 | return; | |
2404 | ||
2405 | case SET: | |
2406 | /* We only care about setting PC. If the source is not RETURN, | |
2407 | IF_THEN_ELSE, or a label, disable any eliminations not at | |
2408 | their initial offsets. Similarly if any arm of the IF_THEN_ELSE | |
2409 | isn't one of those possibilities. For branches to a label, | |
2410 | call ourselves recursively. | |
2411 | ||
2412 | Note that this can disable elimination unnecessarily when we have | |
2413 | a non-local goto since it will look like a non-constant jump to | |
2414 | someplace in the current function. This isn't a significant | |
2415 | problem since such jumps will normally be when all elimination | |
2416 | pairs are back to their initial offsets. */ | |
2417 | ||
2418 | if (SET_DEST (x) != pc_rtx) | |
2419 | return; | |
2420 | ||
2421 | switch (GET_CODE (SET_SRC (x))) | |
2422 | { | |
2423 | case PC: | |
2424 | case RETURN: | |
2425 | return; | |
2426 | ||
2427 | case LABEL_REF: | |
2428 | set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p); | |
2429 | return; | |
2430 | ||
2431 | case IF_THEN_ELSE: | |
2432 | tem = XEXP (SET_SRC (x), 1); | |
2433 | if (GET_CODE (tem) == LABEL_REF) | |
2434 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2435 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2436 | break; | |
2437 | ||
2438 | tem = XEXP (SET_SRC (x), 2); | |
2439 | if (GET_CODE (tem) == LABEL_REF) | |
2440 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2441 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2442 | break; | |
2443 | return; | |
2444 | } | |
2445 | ||
2446 | /* If we reach here, all eliminations must be at their initial | |
2447 | offset because we are doing a jump to a variable address. */ | |
2448 | for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) | |
2449 | if (p->offset != p->initial_offset) | |
2450 | p->can_eliminate = 0; | |
2451 | } | |
2452 | } | |
2453 | \f | |
2454 | /* Used for communication between the next two function to properly share | |
2455 | the vector for an ASM_OPERANDS. */ | |
2456 | ||
2457 | static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec; | |
2458 | ||
a8fdc208 | 2459 | /* Scan X and replace any eliminable registers (such as fp) with a |
32131a9c RK |
2460 | replacement (such as sp), plus an offset. |
2461 | ||
2462 | MEM_MODE is the mode of an enclosing MEM. We need this to know how | |
2463 | much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a | |
2464 | MEM, we are allowed to replace a sum of a register and the constant zero | |
2465 | with the register, which we cannot do outside a MEM. In addition, we need | |
2466 | to record the fact that a register is referenced outside a MEM. | |
2467 | ||
2468 | If INSN is nonzero, it is the insn containing X. If we replace a REG | |
2469 | in a SET_DEST with an equivalent MEM and INSN is non-zero, write a | |
2470 | CLOBBER of the pseudo after INSN so find_equiv_regs will know that | |
2471 | that the REG is being modified. | |
2472 | ||
2473 | If we see a modification to a register we know about, take the | |
2474 | appropriate action (see case SET, below). | |
2475 | ||
2476 | REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had | |
2477 | replacements done assuming all offsets are at their initial values. If | |
2478 | they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we | |
2479 | encounter, return the actual location so that find_reloads will do | |
2480 | the proper thing. */ | |
2481 | ||
2482 | rtx | |
2483 | eliminate_regs (x, mem_mode, insn) | |
2484 | rtx x; | |
2485 | enum machine_mode mem_mode; | |
2486 | rtx insn; | |
2487 | { | |
2488 | enum rtx_code code = GET_CODE (x); | |
2489 | struct elim_table *ep; | |
2490 | int regno; | |
2491 | rtx new; | |
2492 | int i, j; | |
2493 | char *fmt; | |
2494 | int copied = 0; | |
2495 | ||
2496 | switch (code) | |
2497 | { | |
2498 | case CONST_INT: | |
2499 | case CONST_DOUBLE: | |
2500 | case CONST: | |
2501 | case SYMBOL_REF: | |
2502 | case CODE_LABEL: | |
2503 | case PC: | |
2504 | case CC0: | |
2505 | case ASM_INPUT: | |
2506 | case ADDR_VEC: | |
2507 | case ADDR_DIFF_VEC: | |
2508 | case RETURN: | |
2509 | return x; | |
2510 | ||
2511 | case REG: | |
2512 | regno = REGNO (x); | |
2513 | ||
2514 | /* First handle the case where we encounter a bare register that | |
2515 | is eliminable. Replace it with a PLUS. */ | |
2516 | if (regno < FIRST_PSEUDO_REGISTER) | |
2517 | { | |
2518 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2519 | ep++) | |
2520 | if (ep->from_rtx == x && ep->can_eliminate) | |
2521 | { | |
2522 | if (! mem_mode) | |
2523 | ep->ref_outside_mem = 1; | |
2524 | return plus_constant (ep->to_rtx, ep->previous_offset); | |
2525 | } | |
2526 | ||
2527 | } | |
2528 | else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno] | |
2529 | && (reg_equiv_address[regno] || num_not_at_initial_offset)) | |
2530 | { | |
2531 | /* In this case, find_reloads would attempt to either use an | |
2532 | incorrect address (if something is not at its initial offset) | |
2533 | or substitute an replaced address into an insn (which loses | |
2534 | if the offset is changed by some later action). So we simply | |
2535 | return the replaced stack slot (assuming it is changed by | |
2536 | elimination) and ignore the fact that this is actually a | |
2537 | reference to the pseudo. Ensure we make a copy of the | |
2538 | address in case it is shared. */ | |
fb3821f7 CH |
2539 | new = eliminate_regs (reg_equiv_memory_loc[regno], |
2540 | mem_mode, NULL_RTX); | |
32131a9c RK |
2541 | if (new != reg_equiv_memory_loc[regno]) |
2542 | return copy_rtx (new); | |
2543 | } | |
2544 | return x; | |
2545 | ||
2546 | case PLUS: | |
2547 | /* If this is the sum of an eliminable register and a constant, rework | |
2548 | the sum. */ | |
2549 | if (GET_CODE (XEXP (x, 0)) == REG | |
2550 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2551 | && CONSTANT_P (XEXP (x, 1))) | |
2552 | { | |
2553 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2554 | ep++) | |
2555 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2556 | { | |
2557 | if (! mem_mode) | |
2558 | ep->ref_outside_mem = 1; | |
2559 | ||
2560 | /* The only time we want to replace a PLUS with a REG (this | |
2561 | occurs when the constant operand of the PLUS is the negative | |
2562 | of the offset) is when we are inside a MEM. We won't want | |
2563 | to do so at other times because that would change the | |
2564 | structure of the insn in a way that reload can't handle. | |
2565 | We special-case the commonest situation in | |
2566 | eliminate_regs_in_insn, so just replace a PLUS with a | |
2567 | PLUS here, unless inside a MEM. */ | |
a23b64d5 | 2568 | if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT |
32131a9c RK |
2569 | && INTVAL (XEXP (x, 1)) == - ep->previous_offset) |
2570 | return ep->to_rtx; | |
2571 | else | |
2572 | return gen_rtx (PLUS, Pmode, ep->to_rtx, | |
2573 | plus_constant (XEXP (x, 1), | |
2574 | ep->previous_offset)); | |
2575 | } | |
2576 | ||
2577 | /* If the register is not eliminable, we are done since the other | |
2578 | operand is a constant. */ | |
2579 | return x; | |
2580 | } | |
2581 | ||
2582 | /* If this is part of an address, we want to bring any constant to the | |
2583 | outermost PLUS. We will do this by doing register replacement in | |
2584 | our operands and seeing if a constant shows up in one of them. | |
2585 | ||
2586 | We assume here this is part of an address (or a "load address" insn) | |
2587 | since an eliminable register is not likely to appear in any other | |
2588 | context. | |
2589 | ||
2590 | If we have (plus (eliminable) (reg)), we want to produce | |
2591 | (plus (plus (replacement) (reg) (const))). If this was part of a | |
2592 | normal add insn, (plus (replacement) (reg)) will be pushed as a | |
2593 | reload. This is the desired action. */ | |
2594 | ||
2595 | { | |
fb3821f7 CH |
2596 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX); |
2597 | rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX); | |
32131a9c RK |
2598 | |
2599 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
2600 | { | |
2601 | /* If one side is a PLUS and the other side is a pseudo that | |
a8fdc208 | 2602 | didn't get a hard register but has a reg_equiv_constant, |
32131a9c RK |
2603 | we must replace the constant here since it may no longer |
2604 | be in the position of any operand. */ | |
2605 | if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG | |
2606 | && REGNO (new1) >= FIRST_PSEUDO_REGISTER | |
2607 | && reg_renumber[REGNO (new1)] < 0 | |
2608 | && reg_equiv_constant != 0 | |
2609 | && reg_equiv_constant[REGNO (new1)] != 0) | |
2610 | new1 = reg_equiv_constant[REGNO (new1)]; | |
2611 | else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG | |
2612 | && REGNO (new0) >= FIRST_PSEUDO_REGISTER | |
2613 | && reg_renumber[REGNO (new0)] < 0 | |
2614 | && reg_equiv_constant[REGNO (new0)] != 0) | |
2615 | new0 = reg_equiv_constant[REGNO (new0)]; | |
2616 | ||
2617 | new = form_sum (new0, new1); | |
2618 | ||
2619 | /* As above, if we are not inside a MEM we do not want to | |
2620 | turn a PLUS into something else. We might try to do so here | |
2621 | for an addition of 0 if we aren't optimizing. */ | |
2622 | if (! mem_mode && GET_CODE (new) != PLUS) | |
2623 | return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx); | |
2624 | else | |
2625 | return new; | |
2626 | } | |
2627 | } | |
2628 | return x; | |
2629 | ||
2630 | case EXPR_LIST: | |
2631 | /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ | |
2632 | if (XEXP (x, 0)) | |
2633 | { | |
fb3821f7 | 2634 | new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX); |
32131a9c RK |
2635 | if (new != XEXP (x, 0)) |
2636 | x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1)); | |
2637 | } | |
2638 | ||
2639 | /* ... fall through ... */ | |
2640 | ||
2641 | case INSN_LIST: | |
2642 | /* Now do eliminations in the rest of the chain. If this was | |
2643 | an EXPR_LIST, this might result in allocating more memory than is | |
2644 | strictly needed, but it simplifies the code. */ | |
2645 | if (XEXP (x, 1)) | |
2646 | { | |
fb3821f7 | 2647 | new = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX); |
32131a9c RK |
2648 | if (new != XEXP (x, 1)) |
2649 | return gen_rtx (INSN_LIST, GET_MODE (x), XEXP (x, 0), new); | |
2650 | } | |
2651 | return x; | |
2652 | ||
2653 | case CALL: | |
2654 | case COMPARE: | |
2655 | case MINUS: | |
2656 | case MULT: | |
2657 | case DIV: case UDIV: | |
2658 | case MOD: case UMOD: | |
2659 | case AND: case IOR: case XOR: | |
2660 | case LSHIFT: case ASHIFT: case ROTATE: | |
2661 | case ASHIFTRT: case LSHIFTRT: case ROTATERT: | |
2662 | case NE: case EQ: | |
2663 | case GE: case GT: case GEU: case GTU: | |
2664 | case LE: case LT: case LEU: case LTU: | |
2665 | { | |
fb3821f7 CH |
2666 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX); |
2667 | rtx new1 | |
2668 | = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX) : 0; | |
32131a9c RK |
2669 | |
2670 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
2671 | return gen_rtx (code, GET_MODE (x), new0, new1); | |
2672 | } | |
2673 | return x; | |
2674 | ||
2675 | case PRE_INC: | |
2676 | case POST_INC: | |
2677 | case PRE_DEC: | |
2678 | case POST_DEC: | |
2679 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2680 | if (ep->to_rtx == XEXP (x, 0)) | |
2681 | { | |
2682 | if (code == PRE_DEC || code == POST_DEC) | |
2683 | ep->offset += GET_MODE_SIZE (mem_mode); | |
2684 | else | |
2685 | ep->offset -= GET_MODE_SIZE (mem_mode); | |
2686 | } | |
2687 | ||
2688 | /* Fall through to generic unary operation case. */ | |
2689 | case USE: | |
2690 | case STRICT_LOW_PART: | |
2691 | case NEG: case NOT: | |
2692 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2693 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2694 | case FLOAT: case FIX: | |
2695 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2696 | case ABS: | |
2697 | case SQRT: | |
2698 | case FFS: | |
fb3821f7 | 2699 | new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX); |
32131a9c RK |
2700 | if (new != XEXP (x, 0)) |
2701 | return gen_rtx (code, GET_MODE (x), new); | |
2702 | return x; | |
2703 | ||
2704 | case SUBREG: | |
2705 | /* Similar to above processing, but preserve SUBREG_WORD. | |
2706 | Convert (subreg (mem)) to (mem) if not paradoxical. | |
2707 | Also, if we have a non-paradoxical (subreg (pseudo)) and the | |
2708 | pseudo didn't get a hard reg, we must replace this with the | |
2709 | eliminated version of the memory location because push_reloads | |
2710 | may do the replacement in certain circumstances. */ | |
2711 | if (GET_CODE (SUBREG_REG (x)) == REG | |
2712 | && (GET_MODE_SIZE (GET_MODE (x)) | |
2713 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2714 | && reg_equiv_memory_loc != 0 | |
2715 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2716 | { | |
2717 | new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))], | |
fb3821f7 | 2718 | mem_mode, NULL_RTX); |
32131a9c RK |
2719 | |
2720 | /* If we didn't change anything, we must retain the pseudo. */ | |
2721 | if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))]) | |
2722 | new = XEXP (x, 0); | |
2723 | else | |
2724 | /* Otherwise, ensure NEW isn't shared in case we have to reload | |
2725 | it. */ | |
2726 | new = copy_rtx (new); | |
2727 | } | |
2728 | else | |
fb3821f7 | 2729 | new = eliminate_regs (SUBREG_REG (x), mem_mode, NULL_RTX); |
32131a9c RK |
2730 | |
2731 | if (new != XEXP (x, 0)) | |
2732 | { | |
2733 | if (GET_CODE (new) == MEM | |
2734 | && (GET_MODE_SIZE (GET_MODE (x)) | |
2735 | <= GET_MODE_SIZE (GET_MODE (new)))) | |
2736 | { | |
2737 | int offset = SUBREG_WORD (x) * UNITS_PER_WORD; | |
2738 | enum machine_mode mode = GET_MODE (x); | |
2739 | ||
2740 | #if BYTES_BIG_ENDIAN | |
2741 | offset += (MIN (UNITS_PER_WORD, | |
2742 | GET_MODE_SIZE (GET_MODE (new))) | |
2743 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))); | |
2744 | #endif | |
2745 | ||
2746 | PUT_MODE (new, mode); | |
2747 | XEXP (new, 0) = plus_constant (XEXP (new, 0), offset); | |
2748 | return new; | |
2749 | } | |
2750 | else | |
2751 | return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x)); | |
2752 | } | |
2753 | ||
2754 | return x; | |
2755 | ||
2756 | case CLOBBER: | |
2757 | /* If clobbering a register that is the replacement register for an | |
d45cf215 | 2758 | elimination we still think can be performed, note that it cannot |
32131a9c RK |
2759 | be performed. Otherwise, we need not be concerned about it. */ |
2760 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2761 | if (ep->to_rtx == XEXP (x, 0)) | |
2762 | ep->can_eliminate = 0; | |
2763 | ||
2764 | return x; | |
2765 | ||
2766 | case ASM_OPERANDS: | |
2767 | { | |
2768 | rtx *temp_vec; | |
2769 | /* Properly handle sharing input and constraint vectors. */ | |
2770 | if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec) | |
2771 | { | |
2772 | /* When we come to a new vector not seen before, | |
2773 | scan all its elements; keep the old vector if none | |
2774 | of them changes; otherwise, make a copy. */ | |
2775 | old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x); | |
2776 | temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx)); | |
2777 | for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) | |
2778 | temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i), | |
fb3821f7 | 2779 | mem_mode, NULL_RTX); |
32131a9c RK |
2780 | |
2781 | for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) | |
2782 | if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i)) | |
2783 | break; | |
2784 | ||
2785 | if (i == ASM_OPERANDS_INPUT_LENGTH (x)) | |
2786 | new_asm_operands_vec = old_asm_operands_vec; | |
2787 | else | |
2788 | new_asm_operands_vec | |
2789 | = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec); | |
2790 | } | |
2791 | ||
2792 | /* If we had to copy the vector, copy the entire ASM_OPERANDS. */ | |
2793 | if (new_asm_operands_vec == old_asm_operands_vec) | |
2794 | return x; | |
2795 | ||
2796 | new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x), | |
2797 | ASM_OPERANDS_OUTPUT_CONSTRAINT (x), | |
2798 | ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec, | |
2799 | ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x), | |
2800 | ASM_OPERANDS_SOURCE_FILE (x), | |
2801 | ASM_OPERANDS_SOURCE_LINE (x)); | |
2802 | new->volatil = x->volatil; | |
2803 | return new; | |
2804 | } | |
2805 | ||
2806 | case SET: | |
2807 | /* Check for setting a register that we know about. */ | |
2808 | if (GET_CODE (SET_DEST (x)) == REG) | |
2809 | { | |
2810 | /* See if this is setting the replacement register for an | |
a8fdc208 | 2811 | elimination. |
32131a9c RK |
2812 | |
2813 | If DEST is the frame pointer, we do nothing because we assume that | |
2814 | all assignments to the frame pointer are for non-local gotos and | |
2815 | are being done at a time when they are valid and do not disturb | |
2816 | anything else. Some machines want to eliminate a fake argument | |
2817 | pointer with either the frame or stack pointer. Assignments to | |
2818 | the frame pointer must not prevent this elimination. */ | |
2819 | ||
2820 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2821 | ep++) | |
2822 | if (ep->to_rtx == SET_DEST (x) | |
2823 | && SET_DEST (x) != frame_pointer_rtx) | |
2824 | { | |
6dc42e49 | 2825 | /* If it is being incremented, adjust the offset. Otherwise, |
32131a9c RK |
2826 | this elimination can't be done. */ |
2827 | rtx src = SET_SRC (x); | |
2828 | ||
2829 | if (GET_CODE (src) == PLUS | |
2830 | && XEXP (src, 0) == SET_DEST (x) | |
2831 | && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
2832 | ep->offset -= INTVAL (XEXP (src, 1)); | |
2833 | else | |
2834 | ep->can_eliminate = 0; | |
2835 | } | |
2836 | ||
2837 | /* Now check to see we are assigning to a register that can be | |
2838 | eliminated. If so, it must be as part of a PARALLEL, since we | |
2839 | will not have been called if this is a single SET. So indicate | |
2840 | that we can no longer eliminate this reg. */ | |
2841 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2842 | ep++) | |
2843 | if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate) | |
2844 | ep->can_eliminate = 0; | |
2845 | } | |
2846 | ||
2847 | /* Now avoid the loop below in this common case. */ | |
2848 | { | |
fb3821f7 CH |
2849 | rtx new0 = eliminate_regs (SET_DEST (x), 0, NULL_RTX); |
2850 | rtx new1 = eliminate_regs (SET_SRC (x), 0, NULL_RTX); | |
32131a9c RK |
2851 | |
2852 | /* If SET_DEST changed from a REG to a MEM and INSN is non-zero, | |
2853 | write a CLOBBER insn. */ | |
2854 | if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM | |
2855 | && insn != 0) | |
2856 | emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn); | |
2857 | ||
2858 | if (new0 != SET_DEST (x) || new1 != SET_SRC (x)) | |
2859 | return gen_rtx (SET, VOIDmode, new0, new1); | |
2860 | } | |
2861 | ||
2862 | return x; | |
2863 | ||
2864 | case MEM: | |
2865 | /* Our only special processing is to pass the mode of the MEM to our | |
2866 | recursive call and copy the flags. While we are here, handle this | |
2867 | case more efficiently. */ | |
fb3821f7 | 2868 | new = eliminate_regs (XEXP (x, 0), GET_MODE (x), NULL_RTX); |
32131a9c RK |
2869 | if (new != XEXP (x, 0)) |
2870 | { | |
2871 | new = gen_rtx (MEM, GET_MODE (x), new); | |
2872 | new->volatil = x->volatil; | |
2873 | new->unchanging = x->unchanging; | |
2874 | new->in_struct = x->in_struct; | |
2875 | return new; | |
2876 | } | |
2877 | else | |
2878 | return x; | |
2879 | } | |
2880 | ||
2881 | /* Process each of our operands recursively. If any have changed, make a | |
2882 | copy of the rtx. */ | |
2883 | fmt = GET_RTX_FORMAT (code); | |
2884 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2885 | { | |
2886 | if (*fmt == 'e') | |
2887 | { | |
fb3821f7 | 2888 | new = eliminate_regs (XEXP (x, i), mem_mode, NULL_RTX); |
32131a9c RK |
2889 | if (new != XEXP (x, i) && ! copied) |
2890 | { | |
2891 | rtx new_x = rtx_alloc (code); | |
2892 | bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld) | |
2893 | + (sizeof (new_x->fld[0]) | |
2894 | * GET_RTX_LENGTH (code)))); | |
2895 | x = new_x; | |
2896 | copied = 1; | |
2897 | } | |
2898 | XEXP (x, i) = new; | |
2899 | } | |
2900 | else if (*fmt == 'E') | |
2901 | { | |
2902 | int copied_vec = 0; | |
2903 | for (j = 0; j < XVECLEN (x, i); j++) | |
2904 | { | |
2905 | new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn); | |
2906 | if (new != XVECEXP (x, i, j) && ! copied_vec) | |
2907 | { | |
2908 | rtvec new_v = gen_rtvec_v (XVECLEN (x, i), | |
2909 | &XVECEXP (x, i, 0)); | |
2910 | if (! copied) | |
2911 | { | |
2912 | rtx new_x = rtx_alloc (code); | |
2913 | bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld) | |
2914 | + (sizeof (new_x->fld[0]) | |
2915 | * GET_RTX_LENGTH (code)))); | |
2916 | x = new_x; | |
2917 | copied = 1; | |
2918 | } | |
2919 | XVEC (x, i) = new_v; | |
2920 | copied_vec = 1; | |
2921 | } | |
2922 | XVECEXP (x, i, j) = new; | |
2923 | } | |
2924 | } | |
2925 | } | |
2926 | ||
2927 | return x; | |
2928 | } | |
2929 | \f | |
2930 | /* Scan INSN and eliminate all eliminable registers in it. | |
2931 | ||
2932 | If REPLACE is nonzero, do the replacement destructively. Also | |
2933 | delete the insn as dead it if it is setting an eliminable register. | |
2934 | ||
2935 | If REPLACE is zero, do all our allocations in reload_obstack. | |
2936 | ||
2937 | If no eliminations were done and this insn doesn't require any elimination | |
2938 | processing (these are not identical conditions: it might be updating sp, | |
2939 | but not referencing fp; this needs to be seen during reload_as_needed so | |
2940 | that the offset between fp and sp can be taken into consideration), zero | |
2941 | is returned. Otherwise, 1 is returned. */ | |
2942 | ||
2943 | static int | |
2944 | eliminate_regs_in_insn (insn, replace) | |
2945 | rtx insn; | |
2946 | int replace; | |
2947 | { | |
2948 | rtx old_body = PATTERN (insn); | |
2949 | rtx new_body; | |
2950 | int val = 0; | |
2951 | struct elim_table *ep; | |
2952 | ||
2953 | if (! replace) | |
2954 | push_obstacks (&reload_obstack, &reload_obstack); | |
2955 | ||
2956 | if (GET_CODE (old_body) == SET && GET_CODE (SET_DEST (old_body)) == REG | |
2957 | && REGNO (SET_DEST (old_body)) < FIRST_PSEUDO_REGISTER) | |
2958 | { | |
2959 | /* Check for setting an eliminable register. */ | |
2960 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2961 | if (ep->from_rtx == SET_DEST (old_body) && ep->can_eliminate) | |
2962 | { | |
2963 | /* In this case this insn isn't serving a useful purpose. We | |
2964 | will delete it in reload_as_needed once we know that this | |
2965 | elimination is, in fact, being done. | |
2966 | ||
2967 | If REPLACE isn't set, we can't delete this insn, but neededn't | |
2968 | process it since it won't be used unless something changes. */ | |
2969 | if (replace) | |
2970 | delete_dead_insn (insn); | |
2971 | val = 1; | |
2972 | goto done; | |
2973 | } | |
2974 | ||
2975 | /* Check for (set (reg) (plus (reg from) (offset))) where the offset | |
2976 | in the insn is the negative of the offset in FROM. Substitute | |
2977 | (set (reg) (reg to)) for the insn and change its code. | |
2978 | ||
2979 | We have to do this here, rather than in eliminate_regs, do that we can | |
2980 | change the insn code. */ | |
2981 | ||
2982 | if (GET_CODE (SET_SRC (old_body)) == PLUS | |
2983 | && GET_CODE (XEXP (SET_SRC (old_body), 0)) == REG | |
2984 | && GET_CODE (XEXP (SET_SRC (old_body), 1)) == CONST_INT) | |
2985 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2986 | ep++) | |
2987 | if (ep->from_rtx == XEXP (SET_SRC (old_body), 0) | |
2988 | && ep->can_eliminate | |
2989 | && ep->offset == - INTVAL (XEXP (SET_SRC (old_body), 1))) | |
2990 | { | |
2991 | PATTERN (insn) = gen_rtx (SET, VOIDmode, | |
2992 | SET_DEST (old_body), ep->to_rtx); | |
2993 | INSN_CODE (insn) = -1; | |
2994 | val = 1; | |
2995 | goto done; | |
2996 | } | |
2997 | } | |
2998 | ||
2999 | old_asm_operands_vec = 0; | |
3000 | ||
3001 | /* Replace the body of this insn with a substituted form. If we changed | |
3002 | something, return non-zero. If this is the final call for this | |
3003 | insn (REPLACE is non-zero), do the elimination in REG_NOTES as well. | |
3004 | ||
3005 | If we are replacing a body that was a (set X (plus Y Z)), try to | |
3006 | re-recognize the insn. We do this in case we had a simple addition | |
3007 | but now can do this as a load-address. This saves an insn in this | |
3008 | common case. */ | |
3009 | ||
fb3821f7 | 3010 | new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX); |
32131a9c RK |
3011 | if (new_body != old_body) |
3012 | { | |
7c791b13 RK |
3013 | /* If we aren't replacing things permanently and we changed something, |
3014 | make another copy to ensure that all the RTL is new. Otherwise | |
3015 | things can go wrong if find_reload swaps commutative operands | |
3016 | and one is inside RTL that has been copied while the other is not. */ | |
3017 | ||
4d411872 RS |
3018 | /* Don't copy an asm_operands because (1) there's no need and (2) |
3019 | copy_rtx can't do it properly when there are multiple outputs. */ | |
b84f9d9c | 3020 | if (! replace && asm_noperands (old_body) < 0) |
7c791b13 RK |
3021 | new_body = copy_rtx (new_body); |
3022 | ||
4a5d0fb5 | 3023 | /* If we had a move insn but now we don't, rerecognize it. */ |
0ba846c7 RS |
3024 | if ((GET_CODE (old_body) == SET && GET_CODE (SET_SRC (old_body)) == REG |
3025 | && (GET_CODE (new_body) != SET | |
3026 | || GET_CODE (SET_SRC (new_body)) != REG)) | |
3027 | /* If this was an add insn before, rerecognize. */ | |
3028 | || | |
3029 | (GET_CODE (old_body) == SET | |
3030 | && GET_CODE (SET_SRC (old_body)) == PLUS)) | |
4a5d0fb5 RS |
3031 | { |
3032 | if (! validate_change (insn, &PATTERN (insn), new_body, 0)) | |
0ba846c7 RS |
3033 | /* If recognition fails, store the new body anyway. |
3034 | It's normal to have recognition failures here | |
3035 | due to bizarre memory addresses; reloading will fix them. */ | |
3036 | PATTERN (insn) = new_body; | |
4a5d0fb5 | 3037 | } |
0ba846c7 | 3038 | else |
32131a9c RK |
3039 | PATTERN (insn) = new_body; |
3040 | ||
3041 | if (replace && REG_NOTES (insn)) | |
fb3821f7 | 3042 | REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, NULL_RTX); |
32131a9c RK |
3043 | val = 1; |
3044 | } | |
a8fdc208 | 3045 | |
32131a9c RK |
3046 | /* Loop through all elimination pairs. See if any have changed and |
3047 | recalculate the number not at initial offset. | |
3048 | ||
a8efe40d RK |
3049 | Compute the maximum offset (minimum offset if the stack does not |
3050 | grow downward) for each elimination pair. | |
3051 | ||
32131a9c RK |
3052 | We also detect a cases where register elimination cannot be done, |
3053 | namely, if a register would be both changed and referenced outside a MEM | |
3054 | in the resulting insn since such an insn is often undefined and, even if | |
3055 | not, we cannot know what meaning will be given to it. Note that it is | |
3056 | valid to have a register used in an address in an insn that changes it | |
3057 | (presumably with a pre- or post-increment or decrement). | |
3058 | ||
3059 | If anything changes, return nonzero. */ | |
3060 | ||
3061 | num_not_at_initial_offset = 0; | |
3062 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3063 | { | |
3064 | if (ep->previous_offset != ep->offset && ep->ref_outside_mem) | |
3065 | ep->can_eliminate = 0; | |
3066 | ||
3067 | ep->ref_outside_mem = 0; | |
3068 | ||
3069 | if (ep->previous_offset != ep->offset) | |
3070 | val = 1; | |
3071 | ||
3072 | ep->previous_offset = ep->offset; | |
3073 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3074 | num_not_at_initial_offset++; | |
a8efe40d RK |
3075 | |
3076 | #ifdef STACK_GROWS_DOWNWARD | |
3077 | ep->max_offset = MAX (ep->max_offset, ep->offset); | |
3078 | #else | |
3079 | ep->max_offset = MIN (ep->max_offset, ep->offset); | |
3080 | #endif | |
32131a9c RK |
3081 | } |
3082 | ||
3083 | done: | |
3084 | if (! replace) | |
3085 | pop_obstacks (); | |
3086 | ||
3087 | return val; | |
3088 | } | |
3089 | ||
3090 | /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register | |
3091 | replacement we currently believe is valid, mark it as not eliminable if X | |
3092 | modifies DEST in any way other than by adding a constant integer to it. | |
3093 | ||
3094 | If DEST is the frame pointer, we do nothing because we assume that | |
3095 | all assignments to the frame pointer are nonlocal gotos and are being done | |
3096 | at a time when they are valid and do not disturb anything else. | |
3097 | Some machines want to eliminate a fake argument pointer with either the | |
3098 | frame or stack pointer. Assignments to the frame pointer must not prevent | |
3099 | this elimination. | |
3100 | ||
3101 | Called via note_stores from reload before starting its passes to scan | |
3102 | the insns of the function. */ | |
3103 | ||
3104 | static void | |
3105 | mark_not_eliminable (dest, x) | |
3106 | rtx dest; | |
3107 | rtx x; | |
3108 | { | |
3109 | register int i; | |
3110 | ||
3111 | /* A SUBREG of a hard register here is just changing its mode. We should | |
3112 | not see a SUBREG of an eliminable hard register, but check just in | |
3113 | case. */ | |
3114 | if (GET_CODE (dest) == SUBREG) | |
3115 | dest = SUBREG_REG (dest); | |
3116 | ||
3117 | if (dest == frame_pointer_rtx) | |
3118 | return; | |
3119 | ||
3120 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3121 | if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx | |
3122 | && (GET_CODE (x) != SET | |
3123 | || GET_CODE (SET_SRC (x)) != PLUS | |
3124 | || XEXP (SET_SRC (x), 0) != dest | |
3125 | || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT)) | |
3126 | { | |
3127 | reg_eliminate[i].can_eliminate_previous | |
3128 | = reg_eliminate[i].can_eliminate = 0; | |
3129 | num_eliminable--; | |
3130 | } | |
3131 | } | |
3132 | \f | |
3133 | /* Kick all pseudos out of hard register REGNO. | |
3134 | If GLOBAL is nonzero, try to find someplace else to put them. | |
3135 | If DUMPFILE is nonzero, log actions taken on that file. | |
3136 | ||
3137 | If CANT_ELIMINATE is nonzero, it means that we are doing this spill | |
3138 | because we found we can't eliminate some register. In the case, no pseudos | |
3139 | are allowed to be in the register, even if they are only in a block that | |
3140 | doesn't require spill registers, unlike the case when we are spilling this | |
3141 | hard reg to produce another spill register. | |
3142 | ||
3143 | Return nonzero if any pseudos needed to be kicked out. */ | |
3144 | ||
3145 | static int | |
3146 | spill_hard_reg (regno, global, dumpfile, cant_eliminate) | |
3147 | register int regno; | |
3148 | int global; | |
3149 | FILE *dumpfile; | |
3150 | int cant_eliminate; | |
3151 | { | |
3152 | int something_changed = 0; | |
3153 | register int i; | |
3154 | ||
3155 | SET_HARD_REG_BIT (forbidden_regs, regno); | |
3156 | ||
3157 | /* Spill every pseudo reg that was allocated to this reg | |
3158 | or to something that overlaps this reg. */ | |
3159 | ||
3160 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3161 | if (reg_renumber[i] >= 0 | |
3162 | && reg_renumber[i] <= regno | |
a8fdc208 | 3163 | && (reg_renumber[i] |
32131a9c RK |
3164 | + HARD_REGNO_NREGS (reg_renumber[i], |
3165 | PSEUDO_REGNO_MODE (i)) | |
3166 | > regno)) | |
3167 | { | |
3168 | enum reg_class class = REGNO_REG_CLASS (regno); | |
3169 | ||
3170 | /* If this register belongs solely to a basic block which needed no | |
3171 | spilling of any class that this register is contained in, | |
3172 | leave it be, unless we are spilling this register because | |
3173 | it was a hard register that can't be eliminated. */ | |
3174 | ||
3175 | if (! cant_eliminate | |
3176 | && basic_block_needs[0] | |
3177 | && reg_basic_block[i] >= 0 | |
3178 | && basic_block_needs[(int) class][reg_basic_block[i]] == 0) | |
3179 | { | |
3180 | enum reg_class *p; | |
3181 | ||
3182 | for (p = reg_class_superclasses[(int) class]; | |
3183 | *p != LIM_REG_CLASSES; p++) | |
3184 | if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0) | |
3185 | break; | |
a8fdc208 | 3186 | |
32131a9c RK |
3187 | if (*p == LIM_REG_CLASSES) |
3188 | continue; | |
3189 | } | |
3190 | ||
3191 | /* Mark it as no longer having a hard register home. */ | |
3192 | reg_renumber[i] = -1; | |
3193 | /* We will need to scan everything again. */ | |
3194 | something_changed = 1; | |
3195 | if (global) | |
3196 | retry_global_alloc (i, forbidden_regs); | |
3197 | ||
3198 | alter_reg (i, regno); | |
3199 | if (dumpfile) | |
3200 | { | |
3201 | if (reg_renumber[i] == -1) | |
3202 | fprintf (dumpfile, " Register %d now on stack.\n\n", i); | |
3203 | else | |
3204 | fprintf (dumpfile, " Register %d now in %d.\n\n", | |
3205 | i, reg_renumber[i]); | |
3206 | } | |
3207 | } | |
3208 | ||
3209 | return something_changed; | |
3210 | } | |
3211 | \f | |
3212 | /* Find all paradoxical subregs within X and update reg_max_ref_width. */ | |
3213 | ||
3214 | static void | |
3215 | scan_paradoxical_subregs (x) | |
3216 | register rtx x; | |
3217 | { | |
3218 | register int i; | |
3219 | register char *fmt; | |
3220 | register enum rtx_code code = GET_CODE (x); | |
3221 | ||
3222 | switch (code) | |
3223 | { | |
3224 | case CONST_INT: | |
3225 | case CONST: | |
3226 | case SYMBOL_REF: | |
3227 | case LABEL_REF: | |
3228 | case CONST_DOUBLE: | |
3229 | case CC0: | |
3230 | case PC: | |
3231 | case REG: | |
3232 | case USE: | |
3233 | case CLOBBER: | |
3234 | return; | |
3235 | ||
3236 | case SUBREG: | |
3237 | if (GET_CODE (SUBREG_REG (x)) == REG | |
3238 | && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
3239 | reg_max_ref_width[REGNO (SUBREG_REG (x))] | |
3240 | = GET_MODE_SIZE (GET_MODE (x)); | |
3241 | return; | |
3242 | } | |
3243 | ||
3244 | fmt = GET_RTX_FORMAT (code); | |
3245 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3246 | { | |
3247 | if (fmt[i] == 'e') | |
3248 | scan_paradoxical_subregs (XEXP (x, i)); | |
3249 | else if (fmt[i] == 'E') | |
3250 | { | |
3251 | register int j; | |
3252 | for (j = XVECLEN (x, i) - 1; j >=0; j--) | |
3253 | scan_paradoxical_subregs (XVECEXP (x, i, j)); | |
3254 | } | |
3255 | } | |
3256 | } | |
3257 | \f | |
3258 | struct hard_reg_n_uses { int regno; int uses; }; | |
3259 | ||
3260 | static int | |
3261 | hard_reg_use_compare (p1, p2) | |
3262 | struct hard_reg_n_uses *p1, *p2; | |
3263 | { | |
3264 | int tem = p1->uses - p2->uses; | |
3265 | if (tem != 0) return tem; | |
3266 | /* If regs are equally good, sort by regno, | |
3267 | so that the results of qsort leave nothing to chance. */ | |
3268 | return p1->regno - p2->regno; | |
3269 | } | |
3270 | ||
3271 | /* Choose the order to consider regs for use as reload registers | |
3272 | based on how much trouble would be caused by spilling one. | |
3273 | Store them in order of decreasing preference in potential_reload_regs. */ | |
3274 | ||
3275 | static void | |
3276 | order_regs_for_reload () | |
3277 | { | |
3278 | register int i; | |
3279 | register int o = 0; | |
3280 | int large = 0; | |
3281 | ||
3282 | struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER]; | |
3283 | ||
3284 | CLEAR_HARD_REG_SET (bad_spill_regs); | |
3285 | ||
3286 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3287 | potential_reload_regs[i] = -1; | |
3288 | ||
3289 | /* Count number of uses of each hard reg by pseudo regs allocated to it | |
3290 | and then order them by decreasing use. */ | |
3291 | ||
3292 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3293 | { | |
3294 | hard_reg_n_uses[i].uses = 0; | |
3295 | hard_reg_n_uses[i].regno = i; | |
3296 | } | |
3297 | ||
3298 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3299 | { | |
3300 | int regno = reg_renumber[i]; | |
3301 | if (regno >= 0) | |
3302 | { | |
3303 | int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i)); | |
3304 | while (regno < lim) | |
3305 | hard_reg_n_uses[regno++].uses += reg_n_refs[i]; | |
3306 | } | |
3307 | large += reg_n_refs[i]; | |
3308 | } | |
3309 | ||
3310 | /* Now fixed registers (which cannot safely be used for reloading) | |
3311 | get a very high use count so they will be considered least desirable. | |
3312 | Registers used explicitly in the rtl code are almost as bad. */ | |
3313 | ||
3314 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3315 | { | |
3316 | if (fixed_regs[i]) | |
3317 | { | |
3318 | hard_reg_n_uses[i].uses += 2 * large + 2; | |
3319 | SET_HARD_REG_BIT (bad_spill_regs, i); | |
3320 | } | |
3321 | else if (regs_explicitly_used[i]) | |
3322 | { | |
3323 | hard_reg_n_uses[i].uses += large + 1; | |
3324 | /* ??? We are doing this here because of the potential that | |
3325 | bad code may be generated if a register explicitly used in | |
3326 | an insn was used as a spill register for that insn. But | |
3327 | not using these are spill registers may lose on some machine. | |
3328 | We'll have to see how this works out. */ | |
3329 | SET_HARD_REG_BIT (bad_spill_regs, i); | |
3330 | } | |
3331 | } | |
3332 | hard_reg_n_uses[FRAME_POINTER_REGNUM].uses += 2 * large + 2; | |
3333 | SET_HARD_REG_BIT (bad_spill_regs, FRAME_POINTER_REGNUM); | |
3334 | ||
3335 | #ifdef ELIMINABLE_REGS | |
3336 | /* If registers other than the frame pointer are eliminable, mark them as | |
3337 | poor choices. */ | |
3338 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3339 | { | |
3340 | hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2; | |
3341 | SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from); | |
3342 | } | |
3343 | #endif | |
3344 | ||
3345 | /* Prefer registers not so far used, for use in temporary loading. | |
3346 | Among them, if REG_ALLOC_ORDER is defined, use that order. | |
3347 | Otherwise, prefer registers not preserved by calls. */ | |
3348 | ||
3349 | #ifdef REG_ALLOC_ORDER | |
3350 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3351 | { | |
3352 | int regno = reg_alloc_order[i]; | |
3353 | ||
3354 | if (hard_reg_n_uses[regno].uses == 0) | |
3355 | potential_reload_regs[o++] = regno; | |
3356 | } | |
3357 | #else | |
3358 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3359 | { | |
3360 | if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i]) | |
3361 | potential_reload_regs[o++] = i; | |
3362 | } | |
3363 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3364 | { | |
3365 | if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i]) | |
3366 | potential_reload_regs[o++] = i; | |
3367 | } | |
3368 | #endif | |
3369 | ||
3370 | qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER, | |
3371 | sizeof hard_reg_n_uses[0], hard_reg_use_compare); | |
3372 | ||
3373 | /* Now add the regs that are already used, | |
3374 | preferring those used less often. The fixed and otherwise forbidden | |
3375 | registers will be at the end of this list. */ | |
3376 | ||
3377 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3378 | if (hard_reg_n_uses[i].uses != 0) | |
3379 | potential_reload_regs[o++] = hard_reg_n_uses[i].regno; | |
3380 | } | |
3381 | \f | |
3382 | /* Reload pseudo-registers into hard regs around each insn as needed. | |
3383 | Additional register load insns are output before the insn that needs it | |
3384 | and perhaps store insns after insns that modify the reloaded pseudo reg. | |
3385 | ||
3386 | reg_last_reload_reg and reg_reloaded_contents keep track of | |
3387 | which pseudo-registers are already available in reload registers. | |
3388 | We update these for the reloads that we perform, | |
3389 | as the insns are scanned. */ | |
3390 | ||
3391 | static void | |
3392 | reload_as_needed (first, live_known) | |
3393 | rtx first; | |
3394 | int live_known; | |
3395 | { | |
3396 | register rtx insn; | |
3397 | register int i; | |
3398 | int this_block = 0; | |
3399 | rtx x; | |
3400 | rtx after_call = 0; | |
3401 | ||
3402 | bzero (spill_reg_rtx, sizeof spill_reg_rtx); | |
3403 | reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx)); | |
3404 | bzero (reg_last_reload_reg, max_regno * sizeof (rtx)); | |
3405 | reg_has_output_reload = (char *) alloca (max_regno); | |
3406 | for (i = 0; i < n_spills; i++) | |
3407 | { | |
3408 | reg_reloaded_contents[i] = -1; | |
3409 | reg_reloaded_insn[i] = 0; | |
3410 | } | |
3411 | ||
3412 | /* Reset all offsets on eliminable registers to their initial values. */ | |
3413 | #ifdef ELIMINABLE_REGS | |
3414 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3415 | { | |
3416 | INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to, | |
510dd77e | 3417 | reg_eliminate[i].initial_offset); |
32131a9c RK |
3418 | reg_eliminate[i].previous_offset |
3419 | = reg_eliminate[i].offset = reg_eliminate[i].initial_offset; | |
3420 | } | |
3421 | #else | |
3422 | INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset); | |
3423 | reg_eliminate[0].previous_offset | |
3424 | = reg_eliminate[0].offset = reg_eliminate[0].initial_offset; | |
3425 | #endif | |
3426 | ||
3427 | num_not_at_initial_offset = 0; | |
3428 | ||
3429 | for (insn = first; insn;) | |
3430 | { | |
3431 | register rtx next = NEXT_INSN (insn); | |
3432 | ||
3433 | /* Notice when we move to a new basic block. */ | |
aa2c50d6 | 3434 | if (live_known && this_block + 1 < n_basic_blocks |
32131a9c RK |
3435 | && insn == basic_block_head[this_block+1]) |
3436 | ++this_block; | |
3437 | ||
3438 | /* If we pass a label, copy the offsets from the label information | |
3439 | into the current offsets of each elimination. */ | |
3440 | if (GET_CODE (insn) == CODE_LABEL) | |
2a4b5f3b RK |
3441 | { |
3442 | num_not_at_initial_offset = 0; | |
3443 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3444 | { | |
3445 | reg_eliminate[i].offset = reg_eliminate[i].previous_offset | |
3446 | = offsets_at[CODE_LABEL_NUMBER (insn)][i]; | |
1d0d98f3 RK |
3447 | if (reg_eliminate[i].can_eliminate |
3448 | && (reg_eliminate[i].offset | |
3449 | != reg_eliminate[i].initial_offset)) | |
2a4b5f3b RK |
3450 | num_not_at_initial_offset++; |
3451 | } | |
3452 | } | |
32131a9c RK |
3453 | |
3454 | else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
3455 | { | |
3456 | rtx avoid_return_reg = 0; | |
3457 | ||
3458 | #ifdef SMALL_REGISTER_CLASSES | |
3459 | /* Set avoid_return_reg if this is an insn | |
3460 | that might use the value of a function call. */ | |
3461 | if (GET_CODE (insn) == CALL_INSN) | |
3462 | { | |
3463 | if (GET_CODE (PATTERN (insn)) == SET) | |
3464 | after_call = SET_DEST (PATTERN (insn)); | |
3465 | else if (GET_CODE (PATTERN (insn)) == PARALLEL | |
3466 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) | |
3467 | after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0)); | |
3468 | else | |
3469 | after_call = 0; | |
3470 | } | |
3471 | else if (after_call != 0 | |
3472 | && !(GET_CODE (PATTERN (insn)) == SET | |
3473 | && SET_DEST (PATTERN (insn)) == stack_pointer_rtx)) | |
3474 | { | |
3475 | if (reg_mentioned_p (after_call, PATTERN (insn))) | |
3476 | avoid_return_reg = after_call; | |
3477 | after_call = 0; | |
3478 | } | |
3479 | #endif /* SMALL_REGISTER_CLASSES */ | |
3480 | ||
2758481d RS |
3481 | /* If this is a USE and CLOBBER of a MEM, ensure that any |
3482 | references to eliminable registers have been removed. */ | |
3483 | ||
3484 | if ((GET_CODE (PATTERN (insn)) == USE | |
3485 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
3486 | && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM) | |
3487 | XEXP (XEXP (PATTERN (insn), 0), 0) | |
3488 | = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), | |
fb3821f7 | 3489 | GET_MODE (XEXP (PATTERN (insn), 0)), NULL_RTX); |
2758481d | 3490 | |
32131a9c RK |
3491 | /* If we need to do register elimination processing, do so. |
3492 | This might delete the insn, in which case we are done. */ | |
3493 | if (num_eliminable && GET_MODE (insn) == QImode) | |
3494 | { | |
3495 | eliminate_regs_in_insn (insn, 1); | |
3496 | if (GET_CODE (insn) == NOTE) | |
3497 | { | |
3498 | insn = next; | |
3499 | continue; | |
3500 | } | |
3501 | } | |
3502 | ||
3503 | if (GET_MODE (insn) == VOIDmode) | |
3504 | n_reloads = 0; | |
3505 | /* First find the pseudo regs that must be reloaded for this insn. | |
3506 | This info is returned in the tables reload_... (see reload.h). | |
3507 | Also modify the body of INSN by substituting RELOAD | |
3508 | rtx's for those pseudo regs. */ | |
3509 | else | |
3510 | { | |
3511 | bzero (reg_has_output_reload, max_regno); | |
3512 | CLEAR_HARD_REG_SET (reg_is_output_reload); | |
3513 | ||
3514 | find_reloads (insn, 1, spill_indirect_levels, live_known, | |
3515 | spill_reg_order); | |
3516 | } | |
3517 | ||
3518 | if (n_reloads > 0) | |
3519 | { | |
3c3eeea6 RK |
3520 | rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn); |
3521 | rtx p; | |
32131a9c RK |
3522 | int class; |
3523 | ||
3524 | /* If this block has not had spilling done for a | |
a8fdc208 | 3525 | particular class, deactivate any optional reloads |
32131a9c RK |
3526 | of that class lest they try to use a spill-reg which isn't |
3527 | available here. If we have any non-optionals that need a | |
3528 | spill reg, abort. */ | |
3529 | ||
3530 | for (class = 0; class < N_REG_CLASSES; class++) | |
3531 | if (basic_block_needs[class] != 0 | |
3532 | && basic_block_needs[class][this_block] == 0) | |
3533 | for (i = 0; i < n_reloads; i++) | |
3534 | if (class == (int) reload_reg_class[i]) | |
3535 | { | |
3536 | if (reload_optional[i]) | |
b07ef7b9 RK |
3537 | { |
3538 | reload_in[i] = reload_out[i] = 0; | |
3539 | reload_secondary_p[i] = 0; | |
3540 | } | |
3541 | else if (reload_reg_rtx[i] == 0 | |
3542 | && (reload_in[i] != 0 || reload_out[i] != 0 | |
3543 | || reload_secondary_p[i] != 0)) | |
32131a9c RK |
3544 | abort (); |
3545 | } | |
3546 | ||
3547 | /* Now compute which reload regs to reload them into. Perhaps | |
3548 | reusing reload regs from previous insns, or else output | |
3549 | load insns to reload them. Maybe output store insns too. | |
3550 | Record the choices of reload reg in reload_reg_rtx. */ | |
3551 | choose_reload_regs (insn, avoid_return_reg); | |
3552 | ||
3553 | /* Generate the insns to reload operands into or out of | |
3554 | their reload regs. */ | |
3555 | emit_reload_insns (insn); | |
3556 | ||
3557 | /* Substitute the chosen reload regs from reload_reg_rtx | |
3558 | into the insn's body (or perhaps into the bodies of other | |
3559 | load and store insn that we just made for reloading | |
3560 | and that we moved the structure into). */ | |
3561 | subst_reloads (); | |
3c3eeea6 RK |
3562 | |
3563 | /* If this was an ASM, make sure that all the reload insns | |
3564 | we have generated are valid. If not, give an error | |
3565 | and delete them. */ | |
3566 | ||
3567 | if (asm_noperands (PATTERN (insn)) >= 0) | |
3568 | for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) | |
3569 | if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i' | |
3570 | && (recog_memoized (p) < 0 | |
3571 | || (insn_extract (p), | |
3572 | ! constrain_operands (INSN_CODE (p), 1)))) | |
3573 | { | |
3574 | error_for_asm (insn, | |
3575 | "`asm' operand requires impossible reload"); | |
3576 | PUT_CODE (p, NOTE); | |
3577 | NOTE_SOURCE_FILE (p) = 0; | |
3578 | NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED; | |
3579 | } | |
32131a9c RK |
3580 | } |
3581 | /* Any previously reloaded spilled pseudo reg, stored in this insn, | |
3582 | is no longer validly lying around to save a future reload. | |
3583 | Note that this does not detect pseudos that were reloaded | |
3584 | for this insn in order to be stored in | |
3585 | (obeying register constraints). That is correct; such reload | |
3586 | registers ARE still valid. */ | |
3587 | note_stores (PATTERN (insn), forget_old_reloads_1); | |
3588 | ||
3589 | /* There may have been CLOBBER insns placed after INSN. So scan | |
3590 | between INSN and NEXT and use them to forget old reloads. */ | |
3591 | for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x)) | |
3592 | if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER) | |
3593 | note_stores (PATTERN (x), forget_old_reloads_1); | |
3594 | ||
3595 | #ifdef AUTO_INC_DEC | |
3596 | /* Likewise for regs altered by auto-increment in this insn. | |
3597 | But note that the reg-notes are not changed by reloading: | |
3598 | they still contain the pseudo-regs, not the spill regs. */ | |
3599 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) | |
3600 | if (REG_NOTE_KIND (x) == REG_INC) | |
3601 | { | |
3602 | /* See if this pseudo reg was reloaded in this insn. | |
3603 | If so, its last-reload info is still valid | |
3604 | because it is based on this insn's reload. */ | |
3605 | for (i = 0; i < n_reloads; i++) | |
3606 | if (reload_out[i] == XEXP (x, 0)) | |
3607 | break; | |
3608 | ||
3609 | if (i != n_reloads) | |
3610 | forget_old_reloads_1 (XEXP (x, 0)); | |
3611 | } | |
3612 | #endif | |
3613 | } | |
3614 | /* A reload reg's contents are unknown after a label. */ | |
3615 | if (GET_CODE (insn) == CODE_LABEL) | |
3616 | for (i = 0; i < n_spills; i++) | |
3617 | { | |
3618 | reg_reloaded_contents[i] = -1; | |
3619 | reg_reloaded_insn[i] = 0; | |
3620 | } | |
3621 | ||
3622 | /* Don't assume a reload reg is still good after a call insn | |
3623 | if it is a call-used reg. */ | |
3624 | if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == CALL_INSN) | |
3625 | for (i = 0; i < n_spills; i++) | |
3626 | if (call_used_regs[spill_regs[i]]) | |
3627 | { | |
3628 | reg_reloaded_contents[i] = -1; | |
3629 | reg_reloaded_insn[i] = 0; | |
3630 | } | |
3631 | ||
3632 | /* In case registers overlap, allow certain insns to invalidate | |
3633 | particular hard registers. */ | |
3634 | ||
3635 | #ifdef INSN_CLOBBERS_REGNO_P | |
3636 | for (i = 0 ; i < n_spills ; i++) | |
3637 | if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i])) | |
3638 | { | |
3639 | reg_reloaded_contents[i] = -1; | |
3640 | reg_reloaded_insn[i] = 0; | |
3641 | } | |
3642 | #endif | |
3643 | ||
3644 | insn = next; | |
3645 | ||
3646 | #ifdef USE_C_ALLOCA | |
3647 | alloca (0); | |
3648 | #endif | |
3649 | } | |
3650 | } | |
3651 | ||
3652 | /* Discard all record of any value reloaded from X, | |
3653 | or reloaded in X from someplace else; | |
3654 | unless X is an output reload reg of the current insn. | |
3655 | ||
3656 | X may be a hard reg (the reload reg) | |
3657 | or it may be a pseudo reg that was reloaded from. */ | |
3658 | ||
3659 | static void | |
3660 | forget_old_reloads_1 (x) | |
3661 | rtx x; | |
3662 | { | |
3663 | register int regno; | |
3664 | int nr; | |
0a2e51a9 RS |
3665 | int offset = 0; |
3666 | ||
3667 | /* note_stores does give us subregs of hard regs. */ | |
3668 | while (GET_CODE (x) == SUBREG) | |
3669 | { | |
3670 | offset += SUBREG_WORD (x); | |
3671 | x = SUBREG_REG (x); | |
3672 | } | |
32131a9c RK |
3673 | |
3674 | if (GET_CODE (x) != REG) | |
3675 | return; | |
3676 | ||
0a2e51a9 | 3677 | regno = REGNO (x) + offset; |
32131a9c RK |
3678 | |
3679 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3680 | nr = 1; | |
3681 | else | |
3682 | { | |
3683 | int i; | |
3684 | nr = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
3685 | /* Storing into a spilled-reg invalidates its contents. | |
3686 | This can happen if a block-local pseudo is allocated to that reg | |
3687 | and it wasn't spilled because this block's total need is 0. | |
3688 | Then some insn might have an optional reload and use this reg. */ | |
3689 | for (i = 0; i < nr; i++) | |
3690 | if (spill_reg_order[regno + i] >= 0 | |
3691 | /* But don't do this if the reg actually serves as an output | |
3692 | reload reg in the current instruction. */ | |
3693 | && (n_reloads == 0 | |
3694 | || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))) | |
3695 | { | |
3696 | reg_reloaded_contents[spill_reg_order[regno + i]] = -1; | |
3697 | reg_reloaded_insn[spill_reg_order[regno + i]] = 0; | |
3698 | } | |
3699 | } | |
3700 | ||
3701 | /* Since value of X has changed, | |
3702 | forget any value previously copied from it. */ | |
3703 | ||
3704 | while (nr-- > 0) | |
3705 | /* But don't forget a copy if this is the output reload | |
3706 | that establishes the copy's validity. */ | |
3707 | if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0) | |
3708 | reg_last_reload_reg[regno + nr] = 0; | |
3709 | } | |
3710 | \f | |
3711 | /* For each reload, the mode of the reload register. */ | |
3712 | static enum machine_mode reload_mode[MAX_RELOADS]; | |
3713 | ||
3714 | /* For each reload, the largest number of registers it will require. */ | |
3715 | static int reload_nregs[MAX_RELOADS]; | |
3716 | ||
3717 | /* Comparison function for qsort to decide which of two reloads | |
3718 | should be handled first. *P1 and *P2 are the reload numbers. */ | |
3719 | ||
3720 | static int | |
3721 | reload_reg_class_lower (p1, p2) | |
3722 | short *p1, *p2; | |
3723 | { | |
3724 | register int r1 = *p1, r2 = *p2; | |
3725 | register int t; | |
a8fdc208 | 3726 | |
32131a9c RK |
3727 | /* Consider required reloads before optional ones. */ |
3728 | t = reload_optional[r1] - reload_optional[r2]; | |
3729 | if (t != 0) | |
3730 | return t; | |
3731 | ||
3732 | /* Count all solitary classes before non-solitary ones. */ | |
3733 | t = ((reg_class_size[(int) reload_reg_class[r2]] == 1) | |
3734 | - (reg_class_size[(int) reload_reg_class[r1]] == 1)); | |
3735 | if (t != 0) | |
3736 | return t; | |
3737 | ||
3738 | /* Aside from solitaires, consider all multi-reg groups first. */ | |
3739 | t = reload_nregs[r2] - reload_nregs[r1]; | |
3740 | if (t != 0) | |
3741 | return t; | |
3742 | ||
3743 | /* Consider reloads in order of increasing reg-class number. */ | |
3744 | t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2]; | |
3745 | if (t != 0) | |
3746 | return t; | |
3747 | ||
3748 | /* If reloads are equally urgent, sort by reload number, | |
3749 | so that the results of qsort leave nothing to chance. */ | |
3750 | return r1 - r2; | |
3751 | } | |
3752 | \f | |
3753 | /* The following HARD_REG_SETs indicate when each hard register is | |
3754 | used for a reload of various parts of the current insn. */ | |
3755 | ||
3756 | /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ | |
3757 | static HARD_REG_SET reload_reg_used; | |
3758 | /* If reg is in use for a RELOAD_FOR_INPUT_RELOAD_ADDRESS reload. */ | |
3759 | static HARD_REG_SET reload_reg_used_in_input_addr; | |
3760 | /* If reg is in use for a RELOAD_FOR_OUTPUT_RELOAD_ADDRESS reload. */ | |
3761 | static HARD_REG_SET reload_reg_used_in_output_addr; | |
3762 | /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ | |
3763 | static HARD_REG_SET reload_reg_used_in_op_addr; | |
3764 | /* If reg is in use for a RELOAD_FOR_INPUT reload. */ | |
3765 | static HARD_REG_SET reload_reg_used_in_input; | |
3766 | /* If reg is in use for a RELOAD_FOR_OUTPUT reload. */ | |
3767 | static HARD_REG_SET reload_reg_used_in_output; | |
3768 | ||
3769 | /* If reg is in use as a reload reg for any sort of reload. */ | |
3770 | static HARD_REG_SET reload_reg_used_at_all; | |
3771 | ||
3772 | /* Mark reg REGNO as in use for a reload of the sort spec'd by WHEN_NEEDED. | |
3773 | MODE is used to indicate how many consecutive regs are actually used. */ | |
3774 | ||
3775 | static void | |
3776 | mark_reload_reg_in_use (regno, when_needed, mode) | |
3777 | int regno; | |
3778 | enum reload_when_needed when_needed; | |
3779 | enum machine_mode mode; | |
3780 | { | |
3781 | int nregs = HARD_REGNO_NREGS (regno, mode); | |
3782 | int i; | |
3783 | ||
3784 | for (i = regno; i < nregs + regno; i++) | |
3785 | { | |
3786 | switch (when_needed) | |
3787 | { | |
3788 | case RELOAD_OTHER: | |
3789 | SET_HARD_REG_BIT (reload_reg_used, i); | |
3790 | break; | |
3791 | ||
3792 | case RELOAD_FOR_INPUT_RELOAD_ADDRESS: | |
3793 | SET_HARD_REG_BIT (reload_reg_used_in_input_addr, i); | |
3794 | break; | |
3795 | ||
3796 | case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS: | |
3797 | SET_HARD_REG_BIT (reload_reg_used_in_output_addr, i); | |
3798 | break; | |
3799 | ||
3800 | case RELOAD_FOR_OPERAND_ADDRESS: | |
3801 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); | |
3802 | break; | |
3803 | ||
3804 | case RELOAD_FOR_INPUT: | |
3805 | SET_HARD_REG_BIT (reload_reg_used_in_input, i); | |
3806 | break; | |
3807 | ||
3808 | case RELOAD_FOR_OUTPUT: | |
3809 | SET_HARD_REG_BIT (reload_reg_used_in_output, i); | |
3810 | break; | |
3811 | } | |
3812 | ||
3813 | SET_HARD_REG_BIT (reload_reg_used_at_all, i); | |
3814 | } | |
3815 | } | |
3816 | ||
3817 | /* 1 if reg REGNO is free as a reload reg for a reload of the sort | |
3818 | specified by WHEN_NEEDED. */ | |
3819 | ||
3820 | static int | |
3821 | reload_reg_free_p (regno, when_needed) | |
3822 | int regno; | |
3823 | enum reload_when_needed when_needed; | |
3824 | { | |
3825 | /* In use for a RELOAD_OTHER means it's not available for anything. */ | |
3826 | if (TEST_HARD_REG_BIT (reload_reg_used, regno)) | |
3827 | return 0; | |
3828 | switch (when_needed) | |
3829 | { | |
3830 | case RELOAD_OTHER: | |
3831 | /* In use for anything means not available for a RELOAD_OTHER. */ | |
3832 | return ! TEST_HARD_REG_BIT (reload_reg_used_at_all, regno); | |
3833 | ||
3834 | /* The other kinds of use can sometimes share a register. */ | |
3835 | case RELOAD_FOR_INPUT: | |
3836 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno) | |
3837 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) | |
3838 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno)); | |
3839 | case RELOAD_FOR_INPUT_RELOAD_ADDRESS: | |
3840 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno) | |
3841 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno)); | |
3842 | case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS: | |
3843 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno) | |
3844 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno)); | |
3845 | case RELOAD_FOR_OPERAND_ADDRESS: | |
3846 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) | |
3847 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno) | |
3848 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno)); | |
3849 | case RELOAD_FOR_OUTPUT: | |
3850 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) | |
3851 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno) | |
3852 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno)); | |
3853 | } | |
3854 | abort (); | |
3855 | } | |
3856 | ||
3857 | /* Return 1 if the value in reload reg REGNO, as used by a reload | |
3858 | needed for the part of the insn specified by WHEN_NEEDED, | |
3859 | is not in use for a reload in any prior part of the insn. | |
3860 | ||
3861 | We can assume that the reload reg was already tested for availability | |
3862 | at the time it is needed, and we should not check this again, | |
3863 | in case the reg has already been marked in use. */ | |
3864 | ||
3865 | static int | |
3866 | reload_reg_free_before_p (regno, when_needed) | |
3867 | int regno; | |
3868 | enum reload_when_needed when_needed; | |
3869 | { | |
3870 | switch (when_needed) | |
3871 | { | |
3872 | case RELOAD_OTHER: | |
3873 | /* Since a RELOAD_OTHER reload claims the reg for the entire insn, | |
3874 | its use starts from the beginning, so nothing can use it earlier. */ | |
3875 | return 1; | |
3876 | ||
3877 | /* If this use is for part of the insn, | |
3878 | check the reg is not in use for any prior part. */ | |
3879 | case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS: | |
3880 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) | |
3881 | return 0; | |
3882 | case RELOAD_FOR_OUTPUT: | |
3883 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input, regno)) | |
3884 | return 0; | |
3885 | case RELOAD_FOR_OPERAND_ADDRESS: | |
3886 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno)) | |
3887 | return 0; | |
3888 | case RELOAD_FOR_INPUT_RELOAD_ADDRESS: | |
3889 | case RELOAD_FOR_INPUT: | |
3890 | return 1; | |
3891 | } | |
3892 | abort (); | |
3893 | } | |
3894 | ||
3895 | /* Return 1 if the value in reload reg REGNO, as used by a reload | |
3896 | needed for the part of the insn specified by WHEN_NEEDED, | |
3897 | is still available in REGNO at the end of the insn. | |
3898 | ||
3899 | We can assume that the reload reg was already tested for availability | |
3900 | at the time it is needed, and we should not check this again, | |
3901 | in case the reg has already been marked in use. */ | |
3902 | ||
3903 | static int | |
3904 | reload_reg_reaches_end_p (regno, when_needed) | |
3905 | int regno; | |
3906 | enum reload_when_needed when_needed; | |
3907 | { | |
3908 | switch (when_needed) | |
3909 | { | |
3910 | case RELOAD_OTHER: | |
3911 | /* Since a RELOAD_OTHER reload claims the reg for the entire insn, | |
3912 | its value must reach the end. */ | |
3913 | return 1; | |
3914 | ||
3915 | /* If this use is for part of the insn, | |
3916 | its value reaches if no subsequent part uses the same register. */ | |
3917 | case RELOAD_FOR_INPUT_RELOAD_ADDRESS: | |
3918 | case RELOAD_FOR_INPUT: | |
3919 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) | |
3920 | || TEST_HARD_REG_BIT (reload_reg_used_in_output, regno)) | |
3921 | return 0; | |
3922 | case RELOAD_FOR_OPERAND_ADDRESS: | |
3923 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno)) | |
3924 | return 0; | |
3925 | case RELOAD_FOR_OUTPUT: | |
3926 | case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS: | |
3927 | return 1; | |
3928 | } | |
3929 | abort (); | |
3930 | } | |
3931 | \f | |
3932 | /* Vector of reload-numbers showing the order in which the reloads should | |
3933 | be processed. */ | |
3934 | short reload_order[MAX_RELOADS]; | |
3935 | ||
3936 | /* Indexed by reload number, 1 if incoming value | |
3937 | inherited from previous insns. */ | |
3938 | char reload_inherited[MAX_RELOADS]; | |
3939 | ||
3940 | /* For an inherited reload, this is the insn the reload was inherited from, | |
3941 | if we know it. Otherwise, this is 0. */ | |
3942 | rtx reload_inheritance_insn[MAX_RELOADS]; | |
3943 | ||
3944 | /* If non-zero, this is a place to get the value of the reload, | |
3945 | rather than using reload_in. */ | |
3946 | rtx reload_override_in[MAX_RELOADS]; | |
3947 | ||
3948 | /* For each reload, the index in spill_regs of the spill register used, | |
3949 | or -1 if we did not need one of the spill registers for this reload. */ | |
3950 | int reload_spill_index[MAX_RELOADS]; | |
3951 | ||
3952 | /* Index of last register assigned as a spill register. We allocate in | |
3953 | a round-robin fashio. */ | |
3954 | ||
3955 | static last_spill_reg = 0; | |
3956 | ||
3957 | /* Find a spill register to use as a reload register for reload R. | |
3958 | LAST_RELOAD is non-zero if this is the last reload for the insn being | |
3959 | processed. | |
3960 | ||
3961 | Set reload_reg_rtx[R] to the register allocated. | |
3962 | ||
3963 | If NOERROR is nonzero, we return 1 if successful, | |
3964 | or 0 if we couldn't find a spill reg and we didn't change anything. */ | |
3965 | ||
3966 | static int | |
3967 | allocate_reload_reg (r, insn, last_reload, noerror) | |
3968 | int r; | |
3969 | rtx insn; | |
3970 | int last_reload; | |
3971 | int noerror; | |
3972 | { | |
3973 | int i; | |
3974 | int pass; | |
3975 | int count; | |
3976 | rtx new; | |
3977 | int regno; | |
3978 | ||
3979 | /* If we put this reload ahead, thinking it is a group, | |
3980 | then insist on finding a group. Otherwise we can grab a | |
a8fdc208 | 3981 | reg that some other reload needs. |
32131a9c RK |
3982 | (That can happen when we have a 68000 DATA_OR_FP_REG |
3983 | which is a group of data regs or one fp reg.) | |
3984 | We need not be so restrictive if there are no more reloads | |
3985 | for this insn. | |
3986 | ||
3987 | ??? Really it would be nicer to have smarter handling | |
3988 | for that kind of reg class, where a problem like this is normal. | |
3989 | Perhaps those classes should be avoided for reloading | |
3990 | by use of more alternatives. */ | |
3991 | ||
3992 | int force_group = reload_nregs[r] > 1 && ! last_reload; | |
3993 | ||
3994 | /* If we want a single register and haven't yet found one, | |
3995 | take any reg in the right class and not in use. | |
3996 | If we want a consecutive group, here is where we look for it. | |
3997 | ||
3998 | We use two passes so we can first look for reload regs to | |
3999 | reuse, which are already in use for other reloads in this insn, | |
4000 | and only then use additional registers. | |
4001 | I think that maximizing reuse is needed to make sure we don't | |
4002 | run out of reload regs. Suppose we have three reloads, and | |
4003 | reloads A and B can share regs. These need two regs. | |
4004 | Suppose A and B are given different regs. | |
4005 | That leaves none for C. */ | |
4006 | for (pass = 0; pass < 2; pass++) | |
4007 | { | |
4008 | /* I is the index in spill_regs. | |
4009 | We advance it round-robin between insns to use all spill regs | |
4010 | equally, so that inherited reloads have a chance | |
4011 | of leapfrogging each other. */ | |
4012 | ||
4013 | for (count = 0, i = last_spill_reg; count < n_spills; count++) | |
4014 | { | |
4015 | int class = (int) reload_reg_class[r]; | |
4016 | ||
4017 | i = (i + 1) % n_spills; | |
4018 | ||
4019 | if (reload_reg_free_p (spill_regs[i], reload_when_needed[r]) | |
4020 | && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i]) | |
4021 | && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r]) | |
4022 | /* Look first for regs to share, then for unshared. */ | |
4023 | && (pass || TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
4024 | spill_regs[i]))) | |
4025 | { | |
4026 | int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]); | |
4027 | /* Avoid the problem where spilling a GENERAL_OR_FP_REG | |
4028 | (on 68000) got us two FP regs. If NR is 1, | |
4029 | we would reject both of them. */ | |
4030 | if (force_group) | |
4031 | nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]); | |
4032 | /* If we need only one reg, we have already won. */ | |
4033 | if (nr == 1) | |
4034 | { | |
4035 | /* But reject a single reg if we demand a group. */ | |
4036 | if (force_group) | |
4037 | continue; | |
4038 | break; | |
4039 | } | |
4040 | /* Otherwise check that as many consecutive regs as we need | |
4041 | are available here. | |
4042 | Also, don't use for a group registers that are | |
4043 | needed for nongroups. */ | |
4044 | if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i])) | |
4045 | while (nr > 1) | |
4046 | { | |
4047 | regno = spill_regs[i] + nr - 1; | |
4048 | if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
4049 | && spill_reg_order[regno] >= 0 | |
4050 | && reload_reg_free_p (regno, reload_when_needed[r]) | |
4051 | && ! TEST_HARD_REG_BIT (counted_for_nongroups, | |
4052 | regno))) | |
4053 | break; | |
4054 | nr--; | |
4055 | } | |
4056 | if (nr == 1) | |
4057 | break; | |
4058 | } | |
4059 | } | |
4060 | ||
4061 | /* If we found something on pass 1, omit pass 2. */ | |
4062 | if (count < n_spills) | |
4063 | break; | |
4064 | } | |
4065 | ||
4066 | /* We should have found a spill register by now. */ | |
4067 | if (count == n_spills) | |
4068 | { | |
4069 | if (noerror) | |
4070 | return 0; | |
139fc12e | 4071 | goto failure; |
32131a9c RK |
4072 | } |
4073 | ||
4074 | last_spill_reg = i; | |
4075 | ||
4076 | /* Mark as in use for this insn the reload regs we use for this. */ | |
4077 | mark_reload_reg_in_use (spill_regs[i], reload_when_needed[r], | |
4078 | reload_mode[r]); | |
4079 | ||
4080 | new = spill_reg_rtx[i]; | |
4081 | ||
4082 | if (new == 0 || GET_MODE (new) != reload_mode[r]) | |
4083 | spill_reg_rtx[i] = new = gen_rtx (REG, reload_mode[r], spill_regs[i]); | |
4084 | ||
4085 | reload_reg_rtx[r] = new; | |
4086 | reload_spill_index[r] = i; | |
4087 | regno = true_regnum (new); | |
4088 | ||
4089 | /* Detect when the reload reg can't hold the reload mode. | |
4090 | This used to be one `if', but Sequent compiler can't handle that. */ | |
4091 | if (HARD_REGNO_MODE_OK (regno, reload_mode[r])) | |
4092 | { | |
4093 | enum machine_mode test_mode = VOIDmode; | |
4094 | if (reload_in[r]) | |
4095 | test_mode = GET_MODE (reload_in[r]); | |
4096 | /* If reload_in[r] has VOIDmode, it means we will load it | |
4097 | in whatever mode the reload reg has: to wit, reload_mode[r]. | |
4098 | We have already tested that for validity. */ | |
4099 | /* Aside from that, we need to test that the expressions | |
4100 | to reload from or into have modes which are valid for this | |
4101 | reload register. Otherwise the reload insns would be invalid. */ | |
4102 | if (! (reload_in[r] != 0 && test_mode != VOIDmode | |
4103 | && ! HARD_REGNO_MODE_OK (regno, test_mode))) | |
4104 | if (! (reload_out[r] != 0 | |
4105 | && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r])))) | |
4106 | /* The reg is OK. */ | |
4107 | return 1; | |
4108 | } | |
4109 | ||
4110 | /* The reg is not OK. */ | |
4111 | if (noerror) | |
4112 | return 0; | |
4113 | ||
139fc12e | 4114 | failure: |
32131a9c RK |
4115 | if (asm_noperands (PATTERN (insn)) < 0) |
4116 | /* It's the compiler's fault. */ | |
4117 | abort (); | |
4118 | ||
4119 | /* It's the user's fault; the operand's mode and constraint | |
4120 | don't match. Disable this reload so we don't crash in final. */ | |
4121 | error_for_asm (insn, | |
4122 | "`asm' operand constraint incompatible with operand size"); | |
4123 | reload_in[r] = 0; | |
4124 | reload_out[r] = 0; | |
4125 | reload_reg_rtx[r] = 0; | |
4126 | reload_optional[r] = 1; | |
4127 | reload_secondary_p[r] = 1; | |
4128 | ||
4129 | return 1; | |
4130 | } | |
4131 | \f | |
4132 | /* Assign hard reg targets for the pseudo-registers we must reload | |
4133 | into hard regs for this insn. | |
4134 | Also output the instructions to copy them in and out of the hard regs. | |
4135 | ||
4136 | For machines with register classes, we are responsible for | |
4137 | finding a reload reg in the proper class. */ | |
4138 | ||
4139 | static void | |
4140 | choose_reload_regs (insn, avoid_return_reg) | |
4141 | rtx insn; | |
4142 | /* This argument is currently ignored. */ | |
4143 | rtx avoid_return_reg; | |
4144 | { | |
4145 | register int i, j; | |
4146 | int max_group_size = 1; | |
4147 | enum reg_class group_class = NO_REGS; | |
4148 | int inheritance; | |
4149 | ||
4150 | rtx save_reload_reg_rtx[MAX_RELOADS]; | |
4151 | char save_reload_inherited[MAX_RELOADS]; | |
4152 | rtx save_reload_inheritance_insn[MAX_RELOADS]; | |
4153 | rtx save_reload_override_in[MAX_RELOADS]; | |
4154 | int save_reload_spill_index[MAX_RELOADS]; | |
4155 | HARD_REG_SET save_reload_reg_used; | |
4156 | HARD_REG_SET save_reload_reg_used_in_input_addr; | |
4157 | HARD_REG_SET save_reload_reg_used_in_output_addr; | |
4158 | HARD_REG_SET save_reload_reg_used_in_op_addr; | |
4159 | HARD_REG_SET save_reload_reg_used_in_input; | |
4160 | HARD_REG_SET save_reload_reg_used_in_output; | |
4161 | HARD_REG_SET save_reload_reg_used_at_all; | |
4162 | ||
4163 | bzero (reload_inherited, MAX_RELOADS); | |
4164 | bzero (reload_inheritance_insn, MAX_RELOADS * sizeof (rtx)); | |
4165 | bzero (reload_override_in, MAX_RELOADS * sizeof (rtx)); | |
4166 | ||
4167 | CLEAR_HARD_REG_SET (reload_reg_used); | |
4168 | CLEAR_HARD_REG_SET (reload_reg_used_at_all); | |
4169 | CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr); | |
4170 | CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr); | |
4171 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); | |
4172 | CLEAR_HARD_REG_SET (reload_reg_used_in_output); | |
4173 | CLEAR_HARD_REG_SET (reload_reg_used_in_input); | |
4174 | ||
4175 | /* Distinguish output-only and input-only reloads | |
4176 | because they can overlap with other things. */ | |
4177 | for (j = 0; j < n_reloads; j++) | |
4178 | if (reload_when_needed[j] == RELOAD_OTHER | |
4179 | && ! reload_needed_for_multiple[j]) | |
4180 | { | |
4181 | if (reload_in[j] == 0) | |
4182 | { | |
4183 | /* But earlyclobber operands must stay as RELOAD_OTHER. */ | |
4184 | for (i = 0; i < n_earlyclobbers; i++) | |
4185 | if (rtx_equal_p (reload_out[j], reload_earlyclobbers[i])) | |
4186 | break; | |
4187 | if (i == n_earlyclobbers) | |
4188 | reload_when_needed[j] = RELOAD_FOR_OUTPUT; | |
4189 | } | |
4190 | if (reload_out[j] == 0) | |
4191 | reload_when_needed[j] = RELOAD_FOR_INPUT; | |
4192 | ||
4193 | if (reload_secondary_reload[j] >= 0 | |
4194 | && ! reload_needed_for_multiple[reload_secondary_reload[j]]) | |
4195 | reload_when_needed[reload_secondary_reload[j]] | |
4196 | = reload_when_needed[j]; | |
4197 | } | |
4198 | ||
4199 | #ifdef SMALL_REGISTER_CLASSES | |
4200 | /* Don't bother with avoiding the return reg | |
4201 | if we have no mandatory reload that could use it. */ | |
4202 | if (avoid_return_reg) | |
4203 | { | |
4204 | int do_avoid = 0; | |
4205 | int regno = REGNO (avoid_return_reg); | |
4206 | int nregs | |
4207 | = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg)); | |
4208 | int r; | |
4209 | ||
4210 | for (r = regno; r < regno + nregs; r++) | |
4211 | if (spill_reg_order[r] >= 0) | |
4212 | for (j = 0; j < n_reloads; j++) | |
4213 | if (!reload_optional[j] && reload_reg_rtx[j] == 0 | |
4214 | && (reload_in[j] != 0 || reload_out[j] != 0 | |
4215 | || reload_secondary_p[j]) | |
4216 | && | |
4217 | TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r)) | |
4218 | do_avoid = 1; | |
4219 | if (!do_avoid) | |
4220 | avoid_return_reg = 0; | |
4221 | } | |
4222 | #endif /* SMALL_REGISTER_CLASSES */ | |
4223 | ||
4224 | #if 0 /* Not needed, now that we can always retry without inheritance. */ | |
4225 | /* See if we have more mandatory reloads than spill regs. | |
4226 | If so, then we cannot risk optimizations that could prevent | |
a8fdc208 | 4227 | reloads from sharing one spill register. |
32131a9c RK |
4228 | |
4229 | Since we will try finding a better register than reload_reg_rtx | |
4230 | unless it is equal to reload_in or reload_out, count such reloads. */ | |
4231 | ||
4232 | { | |
4233 | int tem = 0; | |
4234 | #ifdef SMALL_REGISTER_CLASSES | |
4235 | int tem = (avoid_return_reg != 0); | |
a8fdc208 | 4236 | #endif |
32131a9c RK |
4237 | for (j = 0; j < n_reloads; j++) |
4238 | if (! reload_optional[j] | |
4239 | && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j]) | |
4240 | && (reload_reg_rtx[j] == 0 | |
4241 | || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j]) | |
4242 | && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j])))) | |
4243 | tem++; | |
4244 | if (tem > n_spills) | |
4245 | must_reuse = 1; | |
4246 | } | |
4247 | #endif | |
4248 | ||
4249 | #ifdef SMALL_REGISTER_CLASSES | |
4250 | /* Don't use the subroutine call return reg for a reload | |
4251 | if we are supposed to avoid it. */ | |
4252 | if (avoid_return_reg) | |
4253 | { | |
4254 | int regno = REGNO (avoid_return_reg); | |
4255 | int nregs | |
4256 | = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg)); | |
4257 | int r; | |
4258 | ||
4259 | for (r = regno; r < regno + nregs; r++) | |
4260 | if (spill_reg_order[r] >= 0) | |
4261 | SET_HARD_REG_BIT (reload_reg_used, r); | |
4262 | } | |
4263 | #endif /* SMALL_REGISTER_CLASSES */ | |
4264 | ||
4265 | /* In order to be certain of getting the registers we need, | |
4266 | we must sort the reloads into order of increasing register class. | |
4267 | Then our grabbing of reload registers will parallel the process | |
a8fdc208 | 4268 | that provided the reload registers. |
32131a9c RK |
4269 | |
4270 | Also note whether any of the reloads wants a consecutive group of regs. | |
4271 | If so, record the maximum size of the group desired and what | |
4272 | register class contains all the groups needed by this insn. */ | |
4273 | ||
4274 | for (j = 0; j < n_reloads; j++) | |
4275 | { | |
4276 | reload_order[j] = j; | |
4277 | reload_spill_index[j] = -1; | |
4278 | ||
4279 | reload_mode[j] | |
4280 | = (reload_strict_low[j] && reload_out[j] | |
4281 | ? GET_MODE (SUBREG_REG (reload_out[j])) | |
4282 | : (reload_inmode[j] == VOIDmode | |
4283 | || (GET_MODE_SIZE (reload_outmode[j]) | |
4284 | > GET_MODE_SIZE (reload_inmode[j]))) | |
4285 | ? reload_outmode[j] : reload_inmode[j]); | |
4286 | ||
4287 | reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]); | |
4288 | ||
4289 | if (reload_nregs[j] > 1) | |
4290 | { | |
4291 | max_group_size = MAX (reload_nregs[j], max_group_size); | |
4292 | group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class]; | |
4293 | } | |
4294 | ||
4295 | /* If we have already decided to use a certain register, | |
4296 | don't use it in another way. */ | |
4297 | if (reload_reg_rtx[j]) | |
4298 | mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), | |
4299 | reload_when_needed[j], reload_mode[j]); | |
4300 | } | |
4301 | ||
4302 | if (n_reloads > 1) | |
4303 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); | |
4304 | ||
4305 | bcopy (reload_reg_rtx, save_reload_reg_rtx, sizeof reload_reg_rtx); | |
4306 | bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited); | |
4307 | bcopy (reload_inheritance_insn, save_reload_inheritance_insn, | |
4308 | sizeof reload_inheritance_insn); | |
4309 | bcopy (reload_override_in, save_reload_override_in, | |
4310 | sizeof reload_override_in); | |
4311 | bcopy (reload_spill_index, save_reload_spill_index, | |
4312 | sizeof reload_spill_index); | |
4313 | COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used); | |
4314 | COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all); | |
4315 | COPY_HARD_REG_SET (save_reload_reg_used_in_output, | |
4316 | reload_reg_used_in_output); | |
4317 | COPY_HARD_REG_SET (save_reload_reg_used_in_input, | |
4318 | reload_reg_used_in_input); | |
4319 | COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr, | |
4320 | reload_reg_used_in_input_addr); | |
4321 | COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr, | |
4322 | reload_reg_used_in_output_addr); | |
4323 | COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr, | |
4324 | reload_reg_used_in_op_addr); | |
4325 | ||
58b1581b RS |
4326 | /* If -O, try first with inheritance, then turning it off. |
4327 | If not -O, don't do inheritance. | |
4328 | Using inheritance when not optimizing leads to paradoxes | |
4329 | with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves | |
4330 | because one side of the comparison might be inherited. */ | |
32131a9c | 4331 | |
58b1581b | 4332 | for (inheritance = optimize > 0; inheritance >= 0; inheritance--) |
32131a9c RK |
4333 | { |
4334 | /* Process the reloads in order of preference just found. | |
4335 | Beyond this point, subregs can be found in reload_reg_rtx. | |
4336 | ||
4337 | This used to look for an existing reloaded home for all | |
4338 | of the reloads, and only then perform any new reloads. | |
4339 | But that could lose if the reloads were done out of reg-class order | |
4340 | because a later reload with a looser constraint might have an old | |
4341 | home in a register needed by an earlier reload with a tighter constraint. | |
4342 | ||
4343 | To solve this, we make two passes over the reloads, in the order | |
4344 | described above. In the first pass we try to inherit a reload | |
4345 | from a previous insn. If there is a later reload that needs a | |
4346 | class that is a proper subset of the class being processed, we must | |
4347 | also allocate a spill register during the first pass. | |
4348 | ||
4349 | Then make a second pass over the reloads to allocate any reloads | |
4350 | that haven't been given registers yet. */ | |
4351 | ||
4352 | for (j = 0; j < n_reloads; j++) | |
4353 | { | |
4354 | register int r = reload_order[j]; | |
4355 | ||
4356 | /* Ignore reloads that got marked inoperative. */ | |
4357 | if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r]) | |
4358 | continue; | |
4359 | ||
4360 | /* If find_reloads chose a to use reload_in or reload_out as a reload | |
4361 | register, we don't need to chose one. Otherwise, try even if it found | |
4362 | one since we might save an insn if we find the value lying around. */ | |
4363 | if (reload_in[r] != 0 && reload_reg_rtx[r] != 0 | |
4364 | && (rtx_equal_p (reload_in[r], reload_reg_rtx[r]) | |
4365 | || rtx_equal_p (reload_out[r], reload_reg_rtx[r]))) | |
4366 | continue; | |
4367 | ||
4368 | #if 0 /* No longer needed for correct operation. | |
4369 | It might give better code, or might not; worth an experiment? */ | |
4370 | /* If this is an optional reload, we can't inherit from earlier insns | |
4371 | until we are sure that any non-optional reloads have been allocated. | |
4372 | The following code takes advantage of the fact that optional reloads | |
4373 | are at the end of reload_order. */ | |
4374 | if (reload_optional[r] != 0) | |
4375 | for (i = 0; i < j; i++) | |
4376 | if ((reload_out[reload_order[i]] != 0 | |
4377 | || reload_in[reload_order[i]] != 0 | |
4378 | || reload_secondary_p[reload_order[i]]) | |
4379 | && ! reload_optional[reload_order[i]] | |
4380 | && reload_reg_rtx[reload_order[i]] == 0) | |
4381 | allocate_reload_reg (reload_order[i], insn, 0, inheritance); | |
4382 | #endif | |
4383 | ||
4384 | /* First see if this pseudo is already available as reloaded | |
4385 | for a previous insn. We cannot try to inherit for reloads | |
4386 | that are smaller than the maximum number of registers needed | |
4387 | for groups unless the register we would allocate cannot be used | |
4388 | for the groups. | |
4389 | ||
4390 | We could check here to see if this is a secondary reload for | |
4391 | an object that is already in a register of the desired class. | |
4392 | This would avoid the need for the secondary reload register. | |
4393 | But this is complex because we can't easily determine what | |
4394 | objects might want to be loaded via this reload. So let a register | |
4395 | be allocated here. In `emit_reload_insns' we suppress one of the | |
4396 | loads in the case described above. */ | |
4397 | ||
4398 | if (inheritance) | |
4399 | { | |
4400 | register int regno = -1; | |
db660765 | 4401 | enum machine_mode mode; |
32131a9c RK |
4402 | |
4403 | if (reload_in[r] == 0) | |
4404 | ; | |
4405 | else if (GET_CODE (reload_in[r]) == REG) | |
db660765 TW |
4406 | { |
4407 | regno = REGNO (reload_in[r]); | |
4408 | mode = GET_MODE (reload_in[r]); | |
4409 | } | |
32131a9c | 4410 | else if (GET_CODE (reload_in_reg[r]) == REG) |
db660765 TW |
4411 | { |
4412 | regno = REGNO (reload_in_reg[r]); | |
4413 | mode = GET_MODE (reload_in_reg[r]); | |
4414 | } | |
32131a9c RK |
4415 | #if 0 |
4416 | /* This won't work, since REGNO can be a pseudo reg number. | |
4417 | Also, it takes much more hair to keep track of all the things | |
4418 | that can invalidate an inherited reload of part of a pseudoreg. */ | |
4419 | else if (GET_CODE (reload_in[r]) == SUBREG | |
4420 | && GET_CODE (SUBREG_REG (reload_in[r])) == REG) | |
4421 | regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]); | |
4422 | #endif | |
4423 | ||
4424 | if (regno >= 0 && reg_last_reload_reg[regno] != 0) | |
4425 | { | |
4426 | i = spill_reg_order[REGNO (reg_last_reload_reg[regno])]; | |
4427 | ||
4428 | if (reg_reloaded_contents[i] == regno | |
db660765 TW |
4429 | && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno])) |
4430 | >= GET_MODE_SIZE (mode)) | |
32131a9c RK |
4431 | && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r]) |
4432 | && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]], | |
4433 | spill_regs[i]) | |
4434 | && (reload_nregs[r] == max_group_size | |
4435 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], | |
4436 | spill_regs[i])) | |
4437 | && reload_reg_free_p (spill_regs[i], reload_when_needed[r]) | |
4438 | && reload_reg_free_before_p (spill_regs[i], | |
4439 | reload_when_needed[r])) | |
4440 | { | |
4441 | /* If a group is needed, verify that all the subsequent | |
4442 | registers still have their values intact. */ | |
4443 | int nr | |
4444 | = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]); | |
4445 | int k; | |
4446 | ||
4447 | for (k = 1; k < nr; k++) | |
4448 | if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] | |
4449 | != regno) | |
4450 | break; | |
4451 | ||
4452 | if (k == nr) | |
4453 | { | |
4454 | /* Mark the register as in use for this part of | |
4455 | the insn. */ | |
4456 | mark_reload_reg_in_use (spill_regs[i], | |
4457 | reload_when_needed[r], | |
4458 | reload_mode[r]); | |
4459 | reload_reg_rtx[r] = reg_last_reload_reg[regno]; | |
4460 | reload_inherited[r] = 1; | |
4461 | reload_inheritance_insn[r] = reg_reloaded_insn[i]; | |
4462 | reload_spill_index[r] = i; | |
4463 | } | |
4464 | } | |
4465 | } | |
4466 | } | |
4467 | ||
4468 | /* Here's another way to see if the value is already lying around. */ | |
4469 | if (inheritance | |
4470 | && reload_in[r] != 0 | |
4471 | && ! reload_inherited[r] | |
4472 | && reload_out[r] == 0 | |
4473 | && (CONSTANT_P (reload_in[r]) | |
4474 | || GET_CODE (reload_in[r]) == PLUS | |
4475 | || GET_CODE (reload_in[r]) == REG | |
4476 | || GET_CODE (reload_in[r]) == MEM) | |
4477 | && (reload_nregs[r] == max_group_size | |
4478 | || ! reg_classes_intersect_p (reload_reg_class[r], group_class))) | |
4479 | { | |
4480 | register rtx equiv | |
4481 | = find_equiv_reg (reload_in[r], insn, reload_reg_class[r], | |
fb3821f7 | 4482 | -1, NULL_PTR, 0, reload_mode[r]); |
32131a9c RK |
4483 | int regno; |
4484 | ||
4485 | if (equiv != 0) | |
4486 | { | |
4487 | if (GET_CODE (equiv) == REG) | |
4488 | regno = REGNO (equiv); | |
4489 | else if (GET_CODE (equiv) == SUBREG) | |
4490 | { | |
4491 | regno = REGNO (SUBREG_REG (equiv)); | |
4492 | if (regno < FIRST_PSEUDO_REGISTER) | |
4493 | regno += SUBREG_WORD (equiv); | |
4494 | } | |
4495 | else | |
4496 | abort (); | |
4497 | } | |
4498 | ||
4499 | /* If we found a spill reg, reject it unless it is free | |
4500 | and of the desired class. */ | |
4501 | if (equiv != 0 | |
4502 | && ((spill_reg_order[regno] >= 0 | |
4503 | && ! reload_reg_free_before_p (regno, | |
4504 | reload_when_needed[r])) | |
4505 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]], | |
4506 | regno))) | |
4507 | equiv = 0; | |
4508 | ||
4509 | if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)) | |
4510 | equiv = 0; | |
4511 | ||
4512 | if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r])) | |
4513 | equiv = 0; | |
4514 | ||
4515 | /* We found a register that contains the value we need. | |
4516 | If this register is the same as an `earlyclobber' operand | |
4517 | of the current insn, just mark it as a place to reload from | |
4518 | since we can't use it as the reload register itself. */ | |
4519 | ||
4520 | if (equiv != 0) | |
4521 | for (i = 0; i < n_earlyclobbers; i++) | |
bfa30b22 RK |
4522 | if (reg_overlap_mentioned_for_reload_p (equiv, |
4523 | reload_earlyclobbers[i])) | |
32131a9c RK |
4524 | { |
4525 | reload_override_in[r] = equiv; | |
4526 | equiv = 0; | |
4527 | break; | |
4528 | } | |
4529 | ||
4530 | /* JRV: If the equiv register we have found is explicitly | |
4531 | clobbered in the current insn, mark but don't use, as above. */ | |
4532 | ||
4533 | if (equiv != 0 && regno_clobbered_p (regno, insn)) | |
4534 | { | |
4535 | reload_override_in[r] = equiv; | |
4536 | equiv = 0; | |
4537 | } | |
4538 | ||
4539 | /* If we found an equivalent reg, say no code need be generated | |
4540 | to load it, and use it as our reload reg. */ | |
4541 | if (equiv != 0 && regno != FRAME_POINTER_REGNUM) | |
4542 | { | |
4543 | reload_reg_rtx[r] = equiv; | |
4544 | reload_inherited[r] = 1; | |
4545 | /* If it is a spill reg, | |
4546 | mark the spill reg as in use for this insn. */ | |
4547 | i = spill_reg_order[regno]; | |
4548 | if (i >= 0) | |
4549 | mark_reload_reg_in_use (regno, reload_when_needed[r], | |
4550 | reload_mode[r]); | |
4551 | } | |
4552 | } | |
4553 | ||
4554 | /* If we found a register to use already, or if this is an optional | |
4555 | reload, we are done. */ | |
4556 | if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0) | |
4557 | continue; | |
4558 | ||
4559 | #if 0 /* No longer needed for correct operation. Might or might not | |
4560 | give better code on the average. Want to experiment? */ | |
4561 | ||
4562 | /* See if there is a later reload that has a class different from our | |
4563 | class that intersects our class or that requires less register | |
4564 | than our reload. If so, we must allocate a register to this | |
4565 | reload now, since that reload might inherit a previous reload | |
4566 | and take the only available register in our class. Don't do this | |
4567 | for optional reloads since they will force all previous reloads | |
4568 | to be allocated. Also don't do this for reloads that have been | |
4569 | turned off. */ | |
4570 | ||
4571 | for (i = j + 1; i < n_reloads; i++) | |
4572 | { | |
4573 | int s = reload_order[i]; | |
4574 | ||
d45cf215 RS |
4575 | if ((reload_in[s] == 0 && reload_out[s] == 0 |
4576 | && ! reload_secondary_p[s]) | |
32131a9c RK |
4577 | || reload_optional[s]) |
4578 | continue; | |
4579 | ||
4580 | if ((reload_reg_class[s] != reload_reg_class[r] | |
4581 | && reg_classes_intersect_p (reload_reg_class[r], | |
4582 | reload_reg_class[s])) | |
4583 | || reload_nregs[s] < reload_nregs[r]) | |
4584 | break; | |
4585 | } | |
4586 | ||
4587 | if (i == n_reloads) | |
4588 | continue; | |
4589 | ||
4590 | allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance); | |
4591 | #endif | |
4592 | } | |
4593 | ||
4594 | /* Now allocate reload registers for anything non-optional that | |
4595 | didn't get one yet. */ | |
4596 | for (j = 0; j < n_reloads; j++) | |
4597 | { | |
4598 | register int r = reload_order[j]; | |
4599 | ||
4600 | /* Ignore reloads that got marked inoperative. */ | |
4601 | if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r]) | |
4602 | continue; | |
4603 | ||
4604 | /* Skip reloads that already have a register allocated or are | |
4605 | optional. */ | |
4606 | if (reload_reg_rtx[r] != 0 || reload_optional[r]) | |
4607 | continue; | |
4608 | ||
4609 | if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance)) | |
4610 | break; | |
4611 | } | |
4612 | ||
4613 | /* If that loop got all the way, we have won. */ | |
4614 | if (j == n_reloads) | |
4615 | break; | |
4616 | ||
4617 | fail: | |
4618 | /* Loop around and try without any inheritance. */ | |
4619 | /* First undo everything done by the failed attempt | |
4620 | to allocate with inheritance. */ | |
4621 | bcopy (save_reload_reg_rtx, reload_reg_rtx, sizeof reload_reg_rtx); | |
4622 | bcopy (save_reload_inherited, reload_inherited, sizeof reload_inherited); | |
4623 | bcopy (save_reload_inheritance_insn, reload_inheritance_insn, | |
4624 | sizeof reload_inheritance_insn); | |
4625 | bcopy (save_reload_override_in, reload_override_in, | |
4626 | sizeof reload_override_in); | |
4627 | bcopy (save_reload_spill_index, reload_spill_index, | |
4628 | sizeof reload_spill_index); | |
4629 | COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used); | |
4630 | COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all); | |
4631 | COPY_HARD_REG_SET (reload_reg_used_in_input, | |
4632 | save_reload_reg_used_in_input); | |
4633 | COPY_HARD_REG_SET (reload_reg_used_in_output, | |
4634 | save_reload_reg_used_in_output); | |
4635 | COPY_HARD_REG_SET (reload_reg_used_in_input_addr, | |
4636 | save_reload_reg_used_in_input_addr); | |
4637 | COPY_HARD_REG_SET (reload_reg_used_in_output_addr, | |
4638 | save_reload_reg_used_in_output_addr); | |
4639 | COPY_HARD_REG_SET (reload_reg_used_in_op_addr, | |
4640 | save_reload_reg_used_in_op_addr); | |
4641 | } | |
4642 | ||
4643 | /* If we thought we could inherit a reload, because it seemed that | |
4644 | nothing else wanted the same reload register earlier in the insn, | |
4645 | verify that assumption, now that all reloads have been assigned. */ | |
4646 | ||
4647 | for (j = 0; j < n_reloads; j++) | |
4648 | { | |
4649 | register int r = reload_order[j]; | |
4650 | ||
4651 | if (reload_inherited[r] && reload_reg_rtx[r] != 0 | |
4652 | && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]), | |
4653 | reload_when_needed[r])) | |
4654 | reload_inherited[r] = 0; | |
4655 | ||
4656 | /* If we found a better place to reload from, | |
4657 | validate it in the same fashion, if it is a reload reg. */ | |
4658 | if (reload_override_in[r] | |
4659 | && (GET_CODE (reload_override_in[r]) == REG | |
4660 | || GET_CODE (reload_override_in[r]) == SUBREG)) | |
4661 | { | |
4662 | int regno = true_regnum (reload_override_in[r]); | |
4663 | if (spill_reg_order[regno] >= 0 | |
4664 | && ! reload_reg_free_before_p (regno, reload_when_needed[r])) | |
4665 | reload_override_in[r] = 0; | |
4666 | } | |
4667 | } | |
4668 | ||
4669 | /* Now that reload_override_in is known valid, | |
4670 | actually override reload_in. */ | |
4671 | for (j = 0; j < n_reloads; j++) | |
4672 | if (reload_override_in[j]) | |
4673 | reload_in[j] = reload_override_in[j]; | |
4674 | ||
4675 | /* If this reload won't be done because it has been cancelled or is | |
4676 | optional and not inherited, clear reload_reg_rtx so other | |
4677 | routines (such as subst_reloads) don't get confused. */ | |
4678 | for (j = 0; j < n_reloads; j++) | |
4679 | if ((reload_optional[j] && ! reload_inherited[j]) | |
4680 | || (reload_in[j] == 0 && reload_out[j] == 0 | |
4681 | && ! reload_secondary_p[j])) | |
4682 | reload_reg_rtx[j] = 0; | |
4683 | ||
4684 | /* Record which pseudos and which spill regs have output reloads. */ | |
4685 | for (j = 0; j < n_reloads; j++) | |
4686 | { | |
4687 | register int r = reload_order[j]; | |
4688 | ||
4689 | i = reload_spill_index[r]; | |
4690 | ||
4691 | /* I is nonneg if this reload used one of the spill regs. | |
4692 | If reload_reg_rtx[r] is 0, this is an optional reload | |
4693 | that we opted to ignore. */ | |
4694 | if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG | |
4695 | && reload_reg_rtx[r] != 0) | |
4696 | { | |
4697 | register int nregno = REGNO (reload_out[r]); | |
372e033b RS |
4698 | int nr = 1; |
4699 | ||
4700 | if (nregno < FIRST_PSEUDO_REGISTER) | |
4701 | nr = HARD_REGNO_NREGS (nregno, reload_mode[r]); | |
32131a9c RK |
4702 | |
4703 | while (--nr >= 0) | |
372e033b RS |
4704 | reg_has_output_reload[nregno + nr] = 1; |
4705 | ||
4706 | if (i >= 0) | |
32131a9c | 4707 | { |
372e033b RS |
4708 | nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]); |
4709 | while (--nr >= 0) | |
32131a9c RK |
4710 | SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr); |
4711 | } | |
4712 | ||
4713 | if (reload_when_needed[r] != RELOAD_OTHER | |
4714 | && reload_when_needed[r] != RELOAD_FOR_OUTPUT) | |
4715 | abort (); | |
4716 | } | |
4717 | } | |
4718 | } | |
4719 | \f | |
4720 | /* Output insns to reload values in and out of the chosen reload regs. */ | |
4721 | ||
4722 | static void | |
4723 | emit_reload_insns (insn) | |
4724 | rtx insn; | |
4725 | { | |
4726 | register int j; | |
4727 | rtx following_insn = NEXT_INSN (insn); | |
a8efe40d | 4728 | rtx before_insn = insn; |
32131a9c RK |
4729 | rtx first_output_reload_insn = NEXT_INSN (insn); |
4730 | rtx first_other_reload_insn = insn; | |
4731 | rtx first_operand_address_reload_insn = insn; | |
4732 | int special; | |
4733 | /* Values to be put in spill_reg_store are put here first. */ | |
4734 | rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
4735 | ||
d45cf215 | 4736 | /* If this is a CALL_INSN preceded by USE insns, any reload insns |
a8efe40d RK |
4737 | must go in front of the first USE insn, not in front of INSN. */ |
4738 | ||
4739 | if (GET_CODE (insn) == CALL_INSN && GET_CODE (PREV_INSN (insn)) == INSN | |
4740 | && GET_CODE (PATTERN (PREV_INSN (insn))) == USE) | |
4741 | while (GET_CODE (PREV_INSN (before_insn)) == INSN | |
4742 | && GET_CODE (PATTERN (PREV_INSN (before_insn))) == USE) | |
4743 | first_other_reload_insn = first_operand_address_reload_insn | |
4744 | = before_insn = PREV_INSN (before_insn); | |
4745 | ||
32131a9c RK |
4746 | /* Now output the instructions to copy the data into and out of the |
4747 | reload registers. Do these in the order that the reloads were reported, | |
4748 | since reloads of base and index registers precede reloads of operands | |
4749 | and the operands may need the base and index registers reloaded. */ | |
4750 | ||
4751 | for (j = 0; j < n_reloads; j++) | |
4752 | { | |
4753 | register rtx old; | |
4754 | rtx oldequiv_reg = 0; | |
4755 | rtx this_reload_insn = 0; | |
4756 | rtx store_insn = 0; | |
4757 | ||
4758 | old = reload_in[j]; | |
4759 | if (old != 0 && ! reload_inherited[j] | |
4760 | && ! rtx_equal_p (reload_reg_rtx[j], old) | |
4761 | && reload_reg_rtx[j] != 0) | |
4762 | { | |
4763 | register rtx reloadreg = reload_reg_rtx[j]; | |
4764 | rtx oldequiv = 0; | |
4765 | enum machine_mode mode; | |
4766 | rtx where; | |
d445b551 | 4767 | rtx reload_insn; |
32131a9c RK |
4768 | |
4769 | /* Determine the mode to reload in. | |
4770 | This is very tricky because we have three to choose from. | |
4771 | There is the mode the insn operand wants (reload_inmode[J]). | |
4772 | There is the mode of the reload register RELOADREG. | |
4773 | There is the intrinsic mode of the operand, which we could find | |
4774 | by stripping some SUBREGs. | |
4775 | It turns out that RELOADREG's mode is irrelevant: | |
4776 | we can change that arbitrarily. | |
4777 | ||
4778 | Consider (SUBREG:SI foo:QI) as an operand that must be SImode; | |
4779 | then the reload reg may not support QImode moves, so use SImode. | |
4780 | If foo is in memory due to spilling a pseudo reg, this is safe, | |
4781 | because the QImode value is in the least significant part of a | |
4782 | slot big enough for a SImode. If foo is some other sort of | |
4783 | memory reference, then it is impossible to reload this case, | |
4784 | so previous passes had better make sure this never happens. | |
4785 | ||
4786 | Then consider a one-word union which has SImode and one of its | |
4787 | members is a float, being fetched as (SUBREG:SF union:SI). | |
4788 | We must fetch that as SFmode because we could be loading into | |
4789 | a float-only register. In this case OLD's mode is correct. | |
4790 | ||
4791 | Consider an immediate integer: it has VOIDmode. Here we need | |
4792 | to get a mode from something else. | |
4793 | ||
4794 | In some cases, there is a fourth mode, the operand's | |
4795 | containing mode. If the insn specifies a containing mode for | |
4796 | this operand, it overrides all others. | |
4797 | ||
4798 | I am not sure whether the algorithm here is always right, | |
4799 | but it does the right things in those cases. */ | |
4800 | ||
4801 | mode = GET_MODE (old); | |
4802 | if (mode == VOIDmode) | |
4803 | mode = reload_inmode[j]; | |
4804 | if (reload_strict_low[j]) | |
4805 | mode = GET_MODE (SUBREG_REG (reload_in[j])); | |
4806 | ||
4807 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
4808 | /* If we need a secondary register for this operation, see if | |
4809 | the value is already in a register in that class. Don't | |
4810 | do this if the secondary register will be used as a scratch | |
4811 | register. */ | |
4812 | ||
4813 | if (reload_secondary_reload[j] >= 0 | |
58b1581b RS |
4814 | && reload_secondary_icode[j] == CODE_FOR_nothing |
4815 | && optimize) | |
32131a9c RK |
4816 | oldequiv |
4817 | = find_equiv_reg (old, insn, | |
4818 | reload_reg_class[reload_secondary_reload[j]], | |
fb3821f7 | 4819 | -1, NULL_PTR, 0, mode); |
32131a9c RK |
4820 | #endif |
4821 | ||
4822 | /* If reloading from memory, see if there is a register | |
4823 | that already holds the same value. If so, reload from there. | |
4824 | We can pass 0 as the reload_reg_p argument because | |
4825 | any other reload has either already been emitted, | |
4826 | in which case find_equiv_reg will see the reload-insn, | |
4827 | or has yet to be emitted, in which case it doesn't matter | |
4828 | because we will use this equiv reg right away. */ | |
4829 | ||
58b1581b | 4830 | if (oldequiv == 0 && optimize |
32131a9c RK |
4831 | && (GET_CODE (old) == MEM |
4832 | || (GET_CODE (old) == REG | |
4833 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
4834 | && reg_renumber[REGNO (old)] < 0))) | |
4835 | oldequiv = find_equiv_reg (old, insn, GENERAL_REGS, | |
fb3821f7 | 4836 | -1, NULL_PTR, 0, mode); |
32131a9c RK |
4837 | |
4838 | if (oldequiv) | |
4839 | { | |
4840 | int regno = true_regnum (oldequiv); | |
4841 | ||
4842 | /* If OLDEQUIV is a spill register, don't use it for this | |
4843 | if any other reload needs it at an earlier stage of this insn | |
a8fdc208 | 4844 | or at this stage. */ |
32131a9c RK |
4845 | if (spill_reg_order[regno] >= 0 |
4846 | && (! reload_reg_free_p (regno, reload_when_needed[j]) | |
4847 | || ! reload_reg_free_before_p (regno, | |
4848 | reload_when_needed[j]))) | |
4849 | oldequiv = 0; | |
4850 | ||
4851 | /* If OLDEQUIV is not a spill register, | |
4852 | don't use it if any other reload wants it. */ | |
4853 | if (spill_reg_order[regno] < 0) | |
4854 | { | |
4855 | int k; | |
4856 | for (k = 0; k < n_reloads; k++) | |
4857 | if (reload_reg_rtx[k] != 0 && k != j | |
bfa30b22 RK |
4858 | && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k], |
4859 | oldequiv)) | |
32131a9c RK |
4860 | { |
4861 | oldequiv = 0; | |
4862 | break; | |
4863 | } | |
4864 | } | |
4865 | } | |
4866 | ||
4867 | if (oldequiv == 0) | |
4868 | oldequiv = old; | |
4869 | else if (GET_CODE (oldequiv) == REG) | |
4870 | oldequiv_reg = oldequiv; | |
4871 | else if (GET_CODE (oldequiv) == SUBREG) | |
4872 | oldequiv_reg = SUBREG_REG (oldequiv); | |
4873 | ||
4874 | /* Encapsulate both RELOADREG and OLDEQUIV into that mode, | |
4875 | then load RELOADREG from OLDEQUIV. */ | |
4876 | ||
4877 | if (GET_MODE (reloadreg) != mode) | |
b6983ae3 | 4878 | reloadreg = gen_lowpart_common (mode, reloadreg); |
32131a9c RK |
4879 | while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) |
4880 | oldequiv = SUBREG_REG (oldequiv); | |
4881 | if (GET_MODE (oldequiv) != VOIDmode | |
4882 | && mode != GET_MODE (oldequiv)) | |
4883 | oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0); | |
4884 | ||
4885 | /* Decide where to put reload insn for this reload. */ | |
4886 | switch (reload_when_needed[j]) | |
4887 | { | |
4888 | case RELOAD_FOR_INPUT: | |
4889 | case RELOAD_OTHER: | |
4890 | where = first_operand_address_reload_insn; | |
4891 | break; | |
4892 | case RELOAD_FOR_INPUT_RELOAD_ADDRESS: | |
4893 | where = first_other_reload_insn; | |
4894 | break; | |
4895 | case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS: | |
4896 | where = first_output_reload_insn; | |
4897 | break; | |
4898 | case RELOAD_FOR_OPERAND_ADDRESS: | |
a8efe40d | 4899 | where = before_insn; |
32131a9c RK |
4900 | } |
4901 | ||
4902 | special = 0; | |
4903 | ||
4904 | /* Auto-increment addresses must be reloaded in a special way. */ | |
4905 | if (GET_CODE (oldequiv) == POST_INC | |
4906 | || GET_CODE (oldequiv) == POST_DEC | |
4907 | || GET_CODE (oldequiv) == PRE_INC | |
4908 | || GET_CODE (oldequiv) == PRE_DEC) | |
4909 | { | |
4910 | /* We are not going to bother supporting the case where a | |
4911 | incremented register can't be copied directly from | |
4912 | OLDEQUIV since this seems highly unlikely. */ | |
4913 | if (reload_secondary_reload[j] >= 0) | |
4914 | abort (); | |
4915 | /* Prevent normal processing of this reload. */ | |
4916 | special = 1; | |
4917 | /* Output a special code sequence for this case. */ | |
4918 | this_reload_insn | |
4919 | = inc_for_reload (reloadreg, oldequiv, reload_inc[j], where); | |
4920 | } | |
4921 | ||
4922 | /* If we are reloading a pseudo-register that was set by the previous | |
4923 | insn, see if we can get rid of that pseudo-register entirely | |
4924 | by redirecting the previous insn into our reload register. */ | |
4925 | ||
4926 | else if (optimize && GET_CODE (old) == REG | |
4927 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
4928 | && dead_or_set_p (insn, old) | |
4929 | /* This is unsafe if some other reload | |
4930 | uses the same reg first. */ | |
4931 | && (reload_when_needed[j] == RELOAD_OTHER | |
4932 | || reload_when_needed[j] == RELOAD_FOR_INPUT | |
4933 | || reload_when_needed[j] == RELOAD_FOR_INPUT_RELOAD_ADDRESS)) | |
4934 | { | |
4935 | rtx temp = PREV_INSN (insn); | |
4936 | while (temp && GET_CODE (temp) == NOTE) | |
4937 | temp = PREV_INSN (temp); | |
4938 | if (temp | |
4939 | && GET_CODE (temp) == INSN | |
4940 | && GET_CODE (PATTERN (temp)) == SET | |
4941 | && SET_DEST (PATTERN (temp)) == old | |
4942 | /* Make sure we can access insn_operand_constraint. */ | |
4943 | && asm_noperands (PATTERN (temp)) < 0 | |
4944 | /* This is unsafe if prev insn rejects our reload reg. */ | |
4945 | && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0], | |
4946 | reloadreg) | |
4947 | /* This is unsafe if operand occurs more than once in current | |
4948 | insn. Perhaps some occurrences aren't reloaded. */ | |
4949 | && count_occurrences (PATTERN (insn), old) == 1 | |
4950 | /* Don't risk splitting a matching pair of operands. */ | |
4951 | && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp)))) | |
4952 | { | |
4953 | /* Store into the reload register instead of the pseudo. */ | |
4954 | SET_DEST (PATTERN (temp)) = reloadreg; | |
4955 | /* If these are the only uses of the pseudo reg, | |
4956 | pretend for GDB it lives in the reload reg we used. */ | |
4957 | if (reg_n_deaths[REGNO (old)] == 1 | |
4958 | && reg_n_sets[REGNO (old)] == 1) | |
4959 | { | |
4960 | reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]); | |
4961 | alter_reg (REGNO (old), -1); | |
4962 | } | |
4963 | special = 1; | |
4964 | } | |
4965 | } | |
4966 | ||
4967 | /* We can't do that, so output an insn to load RELOADREG. | |
4968 | Keep them in the following order: | |
4969 | all reloads for input reload addresses, | |
4970 | all reloads for ordinary input operands, | |
4971 | all reloads for addresses of non-reloaded operands, | |
4972 | the insn being reloaded, | |
4973 | all reloads for addresses of output reloads, | |
4974 | the output reloads. */ | |
4975 | if (! special) | |
4976 | { | |
4977 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
4978 | rtx second_reload_reg = 0; | |
4979 | enum insn_code icode; | |
4980 | ||
4981 | /* If we have a secondary reload, pick up the secondary register | |
d445b551 RK |
4982 | and icode, if any. If OLDEQUIV and OLD are different or |
4983 | if this is an in-out reload, recompute whether or not we | |
4984 | still need a secondary register and what the icode should | |
4985 | be. If we still need a secondary register and the class or | |
4986 | icode is different, go back to reloading from OLD if using | |
4987 | OLDEQUIV means that we got the wrong type of register. We | |
4988 | cannot have different class or icode due to an in-out reload | |
4989 | because we don't make such reloads when both the input and | |
4990 | output need secondary reload registers. */ | |
32131a9c RK |
4991 | |
4992 | if (reload_secondary_reload[j] >= 0) | |
4993 | { | |
4994 | int secondary_reload = reload_secondary_reload[j]; | |
1554c2c6 RK |
4995 | rtx real_oldequiv = oldequiv; |
4996 | rtx real_old = old; | |
4997 | ||
4998 | /* If OLDEQUIV is a pseudo with a MEM, get the real MEM | |
4999 | and similarly for OLD. | |
5000 | See comments in find_secondary_reload in reload.c. */ | |
5001 | if (GET_CODE (oldequiv) == REG | |
5002 | && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER | |
5003 | && reg_equiv_mem[REGNO (oldequiv)] != 0) | |
5004 | real_oldequiv = reg_equiv_mem[REGNO (oldequiv)]; | |
5005 | ||
5006 | if (GET_CODE (old) == REG | |
5007 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
5008 | && reg_equiv_mem[REGNO (old)] != 0) | |
5009 | real_old = reg_equiv_mem[REGNO (old)]; | |
5010 | ||
32131a9c RK |
5011 | second_reload_reg = reload_reg_rtx[secondary_reload]; |
5012 | icode = reload_secondary_icode[j]; | |
5013 | ||
d445b551 RK |
5014 | if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) |
5015 | || (reload_in[j] != 0 && reload_out[j] != 0)) | |
32131a9c RK |
5016 | { |
5017 | enum reg_class new_class | |
5018 | = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j], | |
1554c2c6 | 5019 | mode, real_oldequiv); |
32131a9c RK |
5020 | |
5021 | if (new_class == NO_REGS) | |
5022 | second_reload_reg = 0; | |
5023 | else | |
5024 | { | |
5025 | enum insn_code new_icode; | |
5026 | enum machine_mode new_mode; | |
5027 | ||
5028 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], | |
5029 | REGNO (second_reload_reg))) | |
1554c2c6 | 5030 | oldequiv = old, real_oldequiv = real_old; |
32131a9c RK |
5031 | else |
5032 | { | |
5033 | new_icode = reload_in_optab[(int) mode]; | |
5034 | if (new_icode != CODE_FOR_nothing | |
5035 | && ((insn_operand_predicate[(int) new_icode][0] | |
a8fdc208 | 5036 | && ! ((*insn_operand_predicate[(int) new_icode][0]) |
32131a9c | 5037 | (reloadreg, mode))) |
a8fdc208 RS |
5038 | || (insn_operand_predicate[(int) new_icode][1] |
5039 | && ! ((*insn_operand_predicate[(int) new_icode][1]) | |
1554c2c6 | 5040 | (real_oldequiv, mode))))) |
32131a9c RK |
5041 | new_icode = CODE_FOR_nothing; |
5042 | ||
5043 | if (new_icode == CODE_FOR_nothing) | |
5044 | new_mode = mode; | |
5045 | else | |
5046 | new_mode = insn_operand_mode[new_icode][2]; | |
5047 | ||
5048 | if (GET_MODE (second_reload_reg) != new_mode) | |
5049 | { | |
5050 | if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg), | |
5051 | new_mode)) | |
1554c2c6 | 5052 | oldequiv = old, real_oldequiv = real_old; |
32131a9c RK |
5053 | else |
5054 | second_reload_reg | |
3aaa90c7 MM |
5055 | = gen_rtx (REG, new_mode, |
5056 | REGNO (second_reload_reg)); | |
32131a9c RK |
5057 | } |
5058 | } | |
5059 | } | |
5060 | } | |
5061 | ||
5062 | /* If we still need a secondary reload register, check | |
5063 | to see if it is being used as a scratch or intermediate | |
1554c2c6 RK |
5064 | register and generate code appropriately. If we need |
5065 | a scratch register, use REAL_OLDEQUIV since the form of | |
5066 | the insn may depend on the actual address if it is | |
5067 | a MEM. */ | |
32131a9c RK |
5068 | |
5069 | if (second_reload_reg) | |
5070 | { | |
5071 | if (icode != CODE_FOR_nothing) | |
5072 | { | |
d445b551 | 5073 | reload_insn = emit_insn_before (GEN_FCN (icode) |
1554c2c6 RK |
5074 | (reloadreg, |
5075 | real_oldequiv, | |
d445b551 RK |
5076 | second_reload_reg), |
5077 | where); | |
5078 | if (this_reload_insn == 0) | |
5079 | this_reload_insn = reload_insn; | |
32131a9c RK |
5080 | special = 1; |
5081 | } | |
5082 | else | |
5083 | { | |
5084 | /* See if we need a scratch register to load the | |
5085 | intermediate register (a tertiary reload). */ | |
5086 | enum insn_code tertiary_icode | |
5087 | = reload_secondary_icode[secondary_reload]; | |
5088 | ||
5089 | if (tertiary_icode != CODE_FOR_nothing) | |
5090 | { | |
5091 | rtx third_reload_reg | |
5092 | = reload_reg_rtx[reload_secondary_reload[secondary_reload]]; | |
5093 | ||
d445b551 RK |
5094 | reload_insn |
5095 | = emit_insn_before ((GEN_FCN (tertiary_icode) | |
5096 | (second_reload_reg, | |
1554c2c6 | 5097 | real_oldequiv, |
d445b551 RK |
5098 | third_reload_reg)), |
5099 | where); | |
5100 | if (this_reload_insn == 0) | |
5101 | this_reload_insn = reload_insn; | |
32131a9c RK |
5102 | } |
5103 | else | |
5104 | { | |
d445b551 RK |
5105 | reload_insn |
5106 | = gen_input_reload (second_reload_reg, | |
fe751ebf | 5107 | oldequiv, where); |
d445b551 RK |
5108 | if (this_reload_insn == 0) |
5109 | this_reload_insn = reload_insn; | |
32131a9c RK |
5110 | oldequiv = second_reload_reg; |
5111 | } | |
5112 | } | |
5113 | } | |
5114 | } | |
5115 | #endif | |
5116 | ||
5117 | if (! special) | |
d445b551 | 5118 | { |
3c3eeea6 | 5119 | reload_insn = gen_input_reload (reloadreg, oldequiv, where); |
d445b551 RK |
5120 | if (this_reload_insn == 0) |
5121 | this_reload_insn = reload_insn; | |
5122 | } | |
32131a9c RK |
5123 | |
5124 | #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P) | |
5125 | /* We may have to make a REG_DEAD note for the secondary reload | |
5126 | register in the insns we just made. Find the last insn that | |
5127 | mentioned the register. */ | |
5128 | if (! special && second_reload_reg | |
5129 | && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg))) | |
5130 | { | |
5131 | rtx prev; | |
5132 | ||
5133 | for (prev = where; | |
5134 | prev != PREV_INSN (this_reload_insn); | |
5135 | prev = PREV_INSN (prev)) | |
5136 | if (GET_RTX_CLASS (GET_CODE (prev) == 'i') | |
bfa30b22 RK |
5137 | && reg_overlap_mentioned_for_reload_p (second_reload_reg, |
5138 | PATTERN (prev))) | |
32131a9c RK |
5139 | { |
5140 | REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD, | |
5141 | second_reload_reg, | |
5142 | REG_NOTES (prev)); | |
5143 | break; | |
5144 | } | |
5145 | } | |
5146 | #endif | |
5147 | } | |
5148 | ||
5149 | /* Update where to put other reload insns. */ | |
5150 | if (this_reload_insn) | |
5151 | switch (reload_when_needed[j]) | |
5152 | { | |
5153 | case RELOAD_FOR_INPUT: | |
5154 | case RELOAD_OTHER: | |
5155 | if (first_other_reload_insn == first_operand_address_reload_insn) | |
5156 | first_other_reload_insn = this_reload_insn; | |
5157 | break; | |
5158 | case RELOAD_FOR_OPERAND_ADDRESS: | |
a8efe40d | 5159 | if (first_operand_address_reload_insn == before_insn) |
32131a9c | 5160 | first_operand_address_reload_insn = this_reload_insn; |
a8efe40d | 5161 | if (first_other_reload_insn == before_insn) |
32131a9c RK |
5162 | first_other_reload_insn = this_reload_insn; |
5163 | } | |
5164 | ||
5165 | /* reload_inc[j] was formerly processed here. */ | |
5166 | } | |
5167 | ||
5168 | /* Add a note saying the input reload reg | |
5169 | dies in this insn, if anyone cares. */ | |
5170 | #ifdef PRESERVE_DEATH_INFO_REGNO_P | |
5171 | if (old != 0 | |
5172 | && reload_reg_rtx[j] != old | |
5173 | && reload_reg_rtx[j] != 0 | |
5174 | && reload_out[j] == 0 | |
5175 | && ! reload_inherited[j] | |
5176 | && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))) | |
5177 | { | |
5178 | register rtx reloadreg = reload_reg_rtx[j]; | |
5179 | ||
a8fdc208 | 5180 | #if 0 |
32131a9c RK |
5181 | /* We can't abort here because we need to support this for sched.c. |
5182 | It's not terrible to miss a REG_DEAD note, but we should try | |
5183 | to figure out how to do this correctly. */ | |
5184 | /* The code below is incorrect for address-only reloads. */ | |
5185 | if (reload_when_needed[j] != RELOAD_OTHER | |
5186 | && reload_when_needed[j] != RELOAD_FOR_INPUT) | |
5187 | abort (); | |
5188 | #endif | |
5189 | ||
5190 | /* Add a death note to this insn, for an input reload. */ | |
5191 | ||
5192 | if ((reload_when_needed[j] == RELOAD_OTHER | |
5193 | || reload_when_needed[j] == RELOAD_FOR_INPUT) | |
5194 | && ! dead_or_set_p (insn, reloadreg)) | |
5195 | REG_NOTES (insn) | |
5196 | = gen_rtx (EXPR_LIST, REG_DEAD, | |
5197 | reloadreg, REG_NOTES (insn)); | |
5198 | } | |
5199 | ||
5200 | /* When we inherit a reload, the last marked death of the reload reg | |
5201 | may no longer really be a death. */ | |
5202 | if (reload_reg_rtx[j] != 0 | |
5203 | && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])) | |
5204 | && reload_inherited[j]) | |
5205 | { | |
5206 | /* Handle inheriting an output reload. | |
5207 | Remove the death note from the output reload insn. */ | |
5208 | if (reload_spill_index[j] >= 0 | |
5209 | && GET_CODE (reload_in[j]) == REG | |
5210 | && spill_reg_store[reload_spill_index[j]] != 0 | |
5211 | && find_regno_note (spill_reg_store[reload_spill_index[j]], | |
5212 | REG_DEAD, REGNO (reload_reg_rtx[j]))) | |
5213 | remove_death (REGNO (reload_reg_rtx[j]), | |
5214 | spill_reg_store[reload_spill_index[j]]); | |
5215 | /* Likewise for input reloads that were inherited. */ | |
5216 | else if (reload_spill_index[j] >= 0 | |
5217 | && GET_CODE (reload_in[j]) == REG | |
5218 | && spill_reg_store[reload_spill_index[j]] == 0 | |
5219 | && reload_inheritance_insn[j] != 0 | |
a8fdc208 | 5220 | && find_regno_note (reload_inheritance_insn[j], REG_DEAD, |
32131a9c RK |
5221 | REGNO (reload_reg_rtx[j]))) |
5222 | remove_death (REGNO (reload_reg_rtx[j]), | |
5223 | reload_inheritance_insn[j]); | |
5224 | else | |
5225 | { | |
5226 | rtx prev; | |
5227 | ||
5228 | /* We got this register from find_equiv_reg. | |
5229 | Search back for its last death note and get rid of it. | |
5230 | But don't search back too far. | |
5231 | Don't go past a place where this reg is set, | |
5232 | since a death note before that remains valid. */ | |
5233 | for (prev = PREV_INSN (insn); | |
5234 | prev && GET_CODE (prev) != CODE_LABEL; | |
5235 | prev = PREV_INSN (prev)) | |
5236 | if (GET_RTX_CLASS (GET_CODE (prev)) == 'i' | |
5237 | && dead_or_set_p (prev, reload_reg_rtx[j])) | |
5238 | { | |
5239 | if (find_regno_note (prev, REG_DEAD, | |
5240 | REGNO (reload_reg_rtx[j]))) | |
5241 | remove_death (REGNO (reload_reg_rtx[j]), prev); | |
5242 | break; | |
5243 | } | |
5244 | } | |
5245 | } | |
5246 | ||
5247 | /* We might have used find_equiv_reg above to choose an alternate | |
5248 | place from which to reload. If so, and it died, we need to remove | |
5249 | that death and move it to one of the insns we just made. */ | |
5250 | ||
5251 | if (oldequiv_reg != 0 | |
5252 | && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg))) | |
5253 | { | |
5254 | rtx prev, prev1; | |
5255 | ||
5256 | for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL; | |
5257 | prev = PREV_INSN (prev)) | |
5258 | if (GET_RTX_CLASS (GET_CODE (prev)) == 'i' | |
5259 | && dead_or_set_p (prev, oldequiv_reg)) | |
5260 | { | |
5261 | if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg))) | |
5262 | { | |
5263 | for (prev1 = this_reload_insn; | |
5264 | prev1; prev1 = PREV_INSN (prev1)) | |
5265 | if (GET_RTX_CLASS (GET_CODE (prev1) == 'i') | |
bfa30b22 RK |
5266 | && reg_overlap_mentioned_for_reload_p (oldequiv_reg, |
5267 | PATTERN (prev1))) | |
32131a9c RK |
5268 | { |
5269 | REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD, | |
5270 | oldequiv_reg, | |
5271 | REG_NOTES (prev1)); | |
5272 | break; | |
5273 | } | |
5274 | remove_death (REGNO (oldequiv_reg), prev); | |
5275 | } | |
5276 | break; | |
5277 | } | |
5278 | } | |
5279 | #endif | |
5280 | ||
5281 | /* If we are reloading a register that was recently stored in with an | |
5282 | output-reload, see if we can prove there was | |
5283 | actually no need to store the old value in it. */ | |
5284 | ||
5285 | if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0 | |
5286 | /* This is unsafe if some other reload uses the same reg first. */ | |
5287 | && (reload_when_needed[j] == RELOAD_OTHER | |
5288 | || reload_when_needed[j] == RELOAD_FOR_INPUT | |
5289 | || reload_when_needed[j] == RELOAD_FOR_INPUT_RELOAD_ADDRESS) | |
5290 | && GET_CODE (reload_in[j]) == REG | |
5291 | #if 0 | |
5292 | /* There doesn't seem to be any reason to restrict this to pseudos | |
5293 | and doing so loses in the case where we are copying from a | |
5294 | register of the wrong class. */ | |
5295 | && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER | |
5296 | #endif | |
5297 | && spill_reg_store[reload_spill_index[j]] != 0 | |
5298 | && dead_or_set_p (insn, reload_in[j]) | |
5299 | /* This is unsafe if operand occurs more than once in current | |
5300 | insn. Perhaps some occurrences weren't reloaded. */ | |
5301 | && count_occurrences (PATTERN (insn), reload_in[j]) == 1) | |
5302 | delete_output_reload (insn, j, | |
5303 | spill_reg_store[reload_spill_index[j]]); | |
5304 | ||
5305 | /* Input-reloading is done. Now do output-reloading, | |
5306 | storing the value from the reload-register after the main insn | |
5307 | if reload_out[j] is nonzero. | |
5308 | ||
5309 | ??? At some point we need to support handling output reloads of | |
5310 | JUMP_INSNs or insns that set cc0. */ | |
5311 | old = reload_out[j]; | |
5312 | if (old != 0 | |
5313 | && reload_reg_rtx[j] != old | |
5314 | && reload_reg_rtx[j] != 0) | |
5315 | { | |
5316 | register rtx reloadreg = reload_reg_rtx[j]; | |
5317 | register rtx second_reloadreg = 0; | |
5318 | rtx prev_insn = PREV_INSN (first_output_reload_insn); | |
5319 | rtx note, p; | |
5320 | enum machine_mode mode; | |
5321 | int special = 0; | |
5322 | ||
5323 | /* An output operand that dies right away does need a reload, | |
5324 | but need not be copied from it. Show the new location in the | |
5325 | REG_UNUSED note. */ | |
5326 | if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH) | |
5327 | && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) | |
5328 | { | |
5329 | XEXP (note, 0) = reload_reg_rtx[j]; | |
5330 | continue; | |
5331 | } | |
5332 | else if (GET_CODE (old) == SCRATCH) | |
5333 | /* If we aren't optimizing, there won't be a REG_UNUSED note, | |
5334 | but we don't want to make an output reload. */ | |
5335 | continue; | |
5336 | ||
5337 | #if 0 | |
5338 | /* Strip off of OLD any size-increasing SUBREGs such as | |
5339 | (SUBREG:SI foo:QI 0). */ | |
5340 | ||
5341 | while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0 | |
5342 | && (GET_MODE_SIZE (GET_MODE (old)) | |
5343 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old))))) | |
5344 | old = SUBREG_REG (old); | |
5345 | #endif | |
5346 | ||
5347 | /* If is a JUMP_INSN, we can't support output reloads yet. */ | |
5348 | if (GET_CODE (insn) == JUMP_INSN) | |
5349 | abort (); | |
5350 | ||
5351 | /* Determine the mode to reload in. | |
5352 | See comments above (for input reloading). */ | |
5353 | ||
5354 | mode = GET_MODE (old); | |
5355 | if (mode == VOIDmode) | |
79a365a7 RS |
5356 | { |
5357 | /* VOIDmode should never happen for an output. */ | |
5358 | if (asm_noperands (PATTERN (insn)) < 0) | |
5359 | /* It's the compiler's fault. */ | |
5360 | abort (); | |
5361 | error_for_asm (insn, "output operand is constant in `asm'"); | |
5362 | /* Prevent crash--use something we know is valid. */ | |
5363 | mode = word_mode; | |
5364 | old = gen_rtx (REG, mode, REGNO (reloadreg)); | |
5365 | } | |
32131a9c RK |
5366 | |
5367 | /* A strict-low-part output operand needs to be reloaded | |
5368 | in the mode of the entire value. */ | |
5369 | if (reload_strict_low[j]) | |
5370 | { | |
5371 | mode = GET_MODE (SUBREG_REG (reload_out[j])); | |
5372 | /* Encapsulate OLD into that mode. */ | |
5373 | /* If OLD is a subreg, then strip it, since the subreg will | |
5374 | be altered by this very reload. */ | |
5375 | while (GET_CODE (old) == SUBREG && GET_MODE (old) != mode) | |
5376 | old = SUBREG_REG (old); | |
5377 | if (GET_MODE (old) != VOIDmode | |
5378 | && mode != GET_MODE (old)) | |
5379 | old = gen_rtx (SUBREG, mode, old, 0); | |
5380 | } | |
5381 | ||
5382 | if (GET_MODE (reloadreg) != mode) | |
b6983ae3 | 5383 | reloadreg = gen_lowpart_common (mode, reloadreg); |
32131a9c RK |
5384 | |
5385 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
5386 | ||
5387 | /* If we need two reload regs, set RELOADREG to the intermediate | |
5388 | one, since it will be stored into OUT. We might need a secondary | |
5389 | register only for an input reload, so check again here. */ | |
5390 | ||
1554c2c6 | 5391 | if (reload_secondary_reload[j] >= 0) |
32131a9c | 5392 | { |
1554c2c6 | 5393 | rtx real_old = old; |
32131a9c | 5394 | |
1554c2c6 RK |
5395 | if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER |
5396 | && reg_equiv_mem[REGNO (old)] != 0) | |
5397 | real_old = reg_equiv_mem[REGNO (old)]; | |
32131a9c | 5398 | |
1554c2c6 RK |
5399 | if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j], |
5400 | mode, real_old) | |
5401 | != NO_REGS)) | |
5402 | { | |
5403 | second_reloadreg = reloadreg; | |
5404 | reloadreg = reload_reg_rtx[reload_secondary_reload[j]]; | |
32131a9c | 5405 | |
1554c2c6 RK |
5406 | /* See if RELOADREG is to be used as a scratch register |
5407 | or as an intermediate register. */ | |
5408 | if (reload_secondary_icode[j] != CODE_FOR_nothing) | |
32131a9c | 5409 | { |
1554c2c6 RK |
5410 | emit_insn_before ((GEN_FCN (reload_secondary_icode[j]) |
5411 | (real_old, second_reloadreg, | |
5412 | reloadreg)), | |
5413 | first_output_reload_insn); | |
5414 | special = 1; | |
32131a9c RK |
5415 | } |
5416 | else | |
1554c2c6 RK |
5417 | { |
5418 | /* See if we need both a scratch and intermediate reload | |
5419 | register. */ | |
5420 | int secondary_reload = reload_secondary_reload[j]; | |
5421 | enum insn_code tertiary_icode | |
5422 | = reload_secondary_icode[secondary_reload]; | |
5423 | rtx pat; | |
32131a9c | 5424 | |
1554c2c6 RK |
5425 | if (GET_MODE (reloadreg) != mode) |
5426 | reloadreg = gen_rtx (REG, mode, REGNO (reloadreg)); | |
5427 | ||
5428 | if (tertiary_icode != CODE_FOR_nothing) | |
5429 | { | |
5430 | rtx third_reloadreg | |
5431 | = reload_reg_rtx[reload_secondary_reload[secondary_reload]]; | |
5432 | pat = (GEN_FCN (tertiary_icode) | |
5433 | (reloadreg, second_reloadreg, third_reloadreg)); | |
5434 | } | |
9ad5f9f6 JW |
5435 | #ifdef SECONDARY_MEMORY_NEEDED |
5436 | /* If we need a memory location to do the move, do it that way. */ | |
5437 | else if (GET_CODE (reloadreg) == REG | |
5438 | && REGNO (reloadreg) < FIRST_PSEUDO_REGISTER | |
5439 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (reloadreg)), | |
5440 | REGNO_REG_CLASS (REGNO (second_reloadreg)), | |
5441 | GET_MODE (second_reloadreg))) | |
5442 | { | |
5443 | /* Get the memory to use and rewrite both registers | |
5444 | to its mode. */ | |
5445 | rtx loc = get_secondary_mem (reloadreg, | |
5446 | GET_MODE (second_reloadreg)); | |
5447 | rtx tmp_reloadreg; | |
5448 | ||
5449 | if (GET_MODE (loc) != GET_MODE (second_reloadreg)) | |
5450 | second_reloadreg = gen_rtx (REG, GET_MODE (loc), | |
5451 | REGNO (second_reloadreg)); | |
5452 | ||
5453 | if (GET_MODE (loc) != GET_MODE (reloadreg)) | |
5454 | tmp_reloadreg = gen_rtx (REG, GET_MODE (loc), | |
5455 | REGNO (reloadreg)); | |
5456 | else | |
5457 | tmp_reloadreg = reloadreg; | |
5458 | ||
5459 | emit_insn_before (gen_move_insn (loc, second_reloadreg), | |
5460 | first_output_reload_insn); | |
5461 | pat = gen_move_insn (tmp_reloadreg, loc); | |
5462 | } | |
5463 | #endif | |
1554c2c6 RK |
5464 | else |
5465 | pat = gen_move_insn (reloadreg, second_reloadreg); | |
5466 | ||
5467 | emit_insn_before (pat, first_output_reload_insn); | |
5468 | } | |
32131a9c RK |
5469 | } |
5470 | } | |
5471 | #endif | |
5472 | ||
5473 | /* Output the last reload insn. */ | |
5474 | if (! special) | |
0dadecf6 RK |
5475 | { |
5476 | #ifdef SECONDARY_MEMORY_NEEDED | |
5477 | /* If we need a memory location to do the move, do it that way. */ | |
5478 | if (GET_CODE (old) == REG && REGNO (old) < FIRST_PSEUDO_REGISTER | |
5479 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (old)), | |
5480 | REGNO_REG_CLASS (REGNO (reloadreg)), | |
5481 | GET_MODE (reloadreg))) | |
5482 | { | |
5483 | /* Get the memory to use and rewrite both registers to | |
5484 | its mode. */ | |
5485 | rtx loc = get_secondary_mem (old, GET_MODE (reloadreg)); | |
5486 | ||
5487 | if (GET_MODE (loc) != GET_MODE (reloadreg)) | |
5488 | reloadreg = gen_rtx (REG, GET_MODE (loc), | |
5489 | REGNO (reloadreg)); | |
5490 | ||
5491 | if (GET_MODE (loc) != GET_MODE (old)) | |
5492 | old = gen_rtx (REG, GET_MODE (loc), REGNO (old)); | |
5493 | ||
5494 | emit_insn_before (gen_move_insn (loc, reloadreg), | |
5495 | first_output_reload_insn); | |
5496 | emit_insn_before (gen_move_insn (old, loc), | |
5497 | first_output_reload_insn); | |
5498 | } | |
5499 | else | |
5500 | #endif | |
5501 | emit_insn_before (gen_move_insn (old, reloadreg), | |
5502 | first_output_reload_insn); | |
5503 | } | |
32131a9c RK |
5504 | |
5505 | #ifdef PRESERVE_DEATH_INFO_REGNO_P | |
5506 | /* If final will look at death notes for this reg, | |
5507 | put one on the last output-reload insn to use it. Similarly | |
5508 | for any secondary register. */ | |
5509 | if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg))) | |
5510 | for (p = PREV_INSN (first_output_reload_insn); | |
5511 | p != prev_insn; p = PREV_INSN (p)) | |
5512 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i' | |
bfa30b22 RK |
5513 | && reg_overlap_mentioned_for_reload_p (reloadreg, |
5514 | PATTERN (p))) | |
32131a9c RK |
5515 | REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD, |
5516 | reloadreg, REG_NOTES (p)); | |
5517 | ||
5518 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS | |
5519 | if (! special | |
5520 | && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg))) | |
5521 | for (p = PREV_INSN (first_output_reload_insn); | |
5522 | p != prev_insn; p = PREV_INSN (p)) | |
5523 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i' | |
bfa30b22 RK |
5524 | && reg_overlap_mentioned_for_reload_p (second_reloadreg, |
5525 | PATTERN (p))) | |
32131a9c RK |
5526 | REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD, |
5527 | second_reloadreg, REG_NOTES (p)); | |
5528 | #endif | |
5529 | #endif | |
5530 | /* Look at all insns we emitted, just to be safe. */ | |
5531 | for (p = NEXT_INSN (prev_insn); p != first_output_reload_insn; | |
5532 | p = NEXT_INSN (p)) | |
5533 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') | |
5534 | { | |
5535 | /* If this output reload doesn't come from a spill reg, | |
5536 | clear any memory of reloaded copies of the pseudo reg. | |
5537 | If this output reload comes from a spill reg, | |
5538 | reg_has_output_reload will make this do nothing. */ | |
5539 | note_stores (PATTERN (p), forget_old_reloads_1); | |
5540 | ||
5541 | if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p))) | |
5542 | store_insn = p; | |
5543 | } | |
5544 | ||
5545 | first_output_reload_insn = NEXT_INSN (prev_insn); | |
5546 | } | |
5547 | ||
5548 | if (reload_spill_index[j] >= 0) | |
5549 | new_spill_reg_store[reload_spill_index[j]] = store_insn; | |
5550 | } | |
5551 | ||
32131a9c RK |
5552 | /* Move death notes from INSN |
5553 | to output-operand-address and output reload insns. */ | |
5554 | #ifdef PRESERVE_DEATH_INFO_REGNO_P | |
5555 | { | |
5556 | rtx insn1; | |
5557 | /* Loop over those insns, last ones first. */ | |
5558 | for (insn1 = PREV_INSN (following_insn); insn1 != insn; | |
5559 | insn1 = PREV_INSN (insn1)) | |
5560 | if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET) | |
5561 | { | |
5562 | rtx source = SET_SRC (PATTERN (insn1)); | |
5563 | rtx dest = SET_DEST (PATTERN (insn1)); | |
5564 | ||
5565 | /* The note we will examine next. */ | |
5566 | rtx reg_notes = REG_NOTES (insn); | |
5567 | /* The place that pointed to this note. */ | |
5568 | rtx *prev_reg_note = ®_NOTES (insn); | |
5569 | ||
5570 | /* If the note is for something used in the source of this | |
5571 | reload insn, or in the output address, move the note. */ | |
5572 | while (reg_notes) | |
5573 | { | |
5574 | rtx next_reg_notes = XEXP (reg_notes, 1); | |
5575 | if (REG_NOTE_KIND (reg_notes) == REG_DEAD | |
5576 | && GET_CODE (XEXP (reg_notes, 0)) == REG | |
5577 | && ((GET_CODE (dest) != REG | |
bfa30b22 RK |
5578 | && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0), |
5579 | dest)) | |
5580 | || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0), | |
5581 | source))) | |
32131a9c RK |
5582 | { |
5583 | *prev_reg_note = next_reg_notes; | |
5584 | XEXP (reg_notes, 1) = REG_NOTES (insn1); | |
5585 | REG_NOTES (insn1) = reg_notes; | |
5586 | } | |
5587 | else | |
5588 | prev_reg_note = &XEXP (reg_notes, 1); | |
5589 | ||
5590 | reg_notes = next_reg_notes; | |
5591 | } | |
5592 | } | |
5593 | } | |
5594 | #endif | |
5595 | ||
5596 | /* For all the spill regs newly reloaded in this instruction, | |
5597 | record what they were reloaded from, so subsequent instructions | |
d445b551 RK |
5598 | can inherit the reloads. |
5599 | ||
5600 | Update spill_reg_store for the reloads of this insn. | |
e9e79d69 | 5601 | Copy the elements that were updated in the loop above. */ |
32131a9c RK |
5602 | |
5603 | for (j = 0; j < n_reloads; j++) | |
5604 | { | |
5605 | register int r = reload_order[j]; | |
5606 | register int i = reload_spill_index[r]; | |
5607 | ||
5608 | /* I is nonneg if this reload used one of the spill regs. | |
5609 | If reload_reg_rtx[r] is 0, this is an optional reload | |
5610 | that we opted to ignore. */ | |
d445b551 | 5611 | |
32131a9c RK |
5612 | if (i >= 0 && reload_reg_rtx[r] != 0) |
5613 | { | |
5614 | /* First, clear out memory of what used to be in this spill reg. | |
5615 | If consecutive registers are used, clear them all. */ | |
5616 | int nr | |
5617 | = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r])); | |
5618 | int k; | |
5619 | ||
5620 | for (k = 0; k < nr; k++) | |
5621 | { | |
5622 | reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1; | |
5623 | reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0; | |
5624 | } | |
5625 | ||
5626 | /* Maybe the spill reg contains a copy of reload_out. */ | |
5627 | if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG) | |
5628 | { | |
5629 | register int nregno = REGNO (reload_out[r]); | |
d445b551 RK |
5630 | |
5631 | spill_reg_store[i] = new_spill_reg_store[i]; | |
32131a9c | 5632 | reg_last_reload_reg[nregno] = reload_reg_rtx[r]; |
d445b551 | 5633 | |
32131a9c RK |
5634 | for (k = 0; k < nr; k++) |
5635 | { | |
5636 | reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] | |
5637 | = nregno; | |
5638 | reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn; | |
5639 | } | |
5640 | } | |
d445b551 | 5641 | |
32131a9c RK |
5642 | /* Maybe the spill reg contains a copy of reload_in. */ |
5643 | else if (reload_out[r] == 0 | |
5644 | && reload_in[r] != 0 | |
5645 | && (GET_CODE (reload_in[r]) == REG | |
5646 | || GET_CODE (reload_in_reg[r]) == REG)) | |
5647 | { | |
5648 | register int nregno; | |
5649 | if (GET_CODE (reload_in[r]) == REG) | |
5650 | nregno = REGNO (reload_in[r]); | |
5651 | else | |
5652 | nregno = REGNO (reload_in_reg[r]); | |
5653 | ||
5654 | /* If there are two separate reloads (one in and one out) | |
5655 | for the same (hard or pseudo) reg, | |
a8fdc208 | 5656 | leave reg_last_reload_reg set |
32131a9c RK |
5657 | based on the output reload. |
5658 | Otherwise, set it from this input reload. */ | |
5659 | if (!reg_has_output_reload[nregno] | |
5660 | /* But don't do so if another input reload | |
5661 | will clobber this one's value. */ | |
5662 | && reload_reg_reaches_end_p (spill_regs[i], | |
5663 | reload_when_needed[r])) | |
5664 | { | |
5665 | reg_last_reload_reg[nregno] = reload_reg_rtx[r]; | |
d445b551 RK |
5666 | |
5667 | /* Unless we inherited this reload, show we haven't | |
5668 | recently done a store. */ | |
5669 | if (! reload_inherited[r]) | |
5670 | spill_reg_store[i] = 0; | |
5671 | ||
32131a9c RK |
5672 | for (k = 0; k < nr; k++) |
5673 | { | |
5674 | reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] | |
5675 | = nregno; | |
5676 | reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] | |
5677 | = insn; | |
5678 | } | |
5679 | } | |
5680 | } | |
5681 | } | |
5682 | ||
5683 | /* The following if-statement was #if 0'd in 1.34 (or before...). | |
5684 | It's reenabled in 1.35 because supposedly nothing else | |
5685 | deals with this problem. */ | |
5686 | ||
5687 | /* If a register gets output-reloaded from a non-spill register, | |
5688 | that invalidates any previous reloaded copy of it. | |
5689 | But forget_old_reloads_1 won't get to see it, because | |
5690 | it thinks only about the original insn. So invalidate it here. */ | |
5691 | if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG) | |
5692 | { | |
5693 | register int nregno = REGNO (reload_out[r]); | |
5694 | reg_last_reload_reg[nregno] = 0; | |
5695 | } | |
5696 | } | |
5697 | } | |
5698 | \f | |
5699 | /* Emit code before BEFORE_INSN to perform an input reload of IN to RELOADREG. | |
3c3eeea6 | 5700 | Returns first insn emitted. */ |
32131a9c RK |
5701 | |
5702 | rtx | |
3c3eeea6 | 5703 | gen_input_reload (reloadreg, in, before_insn) |
32131a9c RK |
5704 | rtx reloadreg; |
5705 | rtx in; | |
5706 | rtx before_insn; | |
5707 | { | |
5708 | register rtx prev_insn = PREV_INSN (before_insn); | |
5709 | ||
a8fdc208 | 5710 | /* How to do this reload can get quite tricky. Normally, we are being |
32131a9c RK |
5711 | asked to reload a simple operand, such as a MEM, a constant, or a pseudo |
5712 | register that didn't get a hard register. In that case we can just | |
5713 | call emit_move_insn. | |
5714 | ||
3002e160 JW |
5715 | We can also be asked to reload a PLUS that adds either two registers, or |
5716 | a register and a constant or MEM, or a MEM and a constant. This can | |
5717 | occur during frame pointer elimination and while reloading addresses. | |
5718 | This case is handled by trying to emit a single insn | |
32131a9c RK |
5719 | to perform the add. If it is not valid, we use a two insn sequence. |
5720 | ||
5721 | Finally, we could be called to handle an 'o' constraint by putting | |
5722 | an address into a register. In that case, we first try to do this | |
5723 | with a named pattern of "reload_load_address". If no such pattern | |
5724 | exists, we just emit a SET insn and hope for the best (it will normally | |
5725 | be valid on machines that use 'o'). | |
5726 | ||
5727 | This entire process is made complex because reload will never | |
5728 | process the insns we generate here and so we must ensure that | |
5729 | they will fit their constraints and also by the fact that parts of | |
5730 | IN might be being reloaded separately and replaced with spill registers. | |
5731 | Because of this, we are, in some sense, just guessing the right approach | |
5732 | here. The one listed above seems to work. | |
5733 | ||
5734 | ??? At some point, this whole thing needs to be rethought. */ | |
5735 | ||
5736 | if (GET_CODE (in) == PLUS | |
3002e160 JW |
5737 | && ((GET_CODE (XEXP (in, 0)) == REG |
5738 | && (GET_CODE (XEXP (in, 1)) == REG | |
5739 | || CONSTANT_P (XEXP (in, 1)) | |
5740 | || GET_CODE (XEXP (in, 1)) == MEM)) | |
5741 | || (GET_CODE (XEXP (in, 0)) == MEM | |
5742 | && CONSTANT_P (XEXP (in, 1))))) | |
32131a9c RK |
5743 | { |
5744 | /* We need to compute the sum of what is either a register and a | |
3002e160 JW |
5745 | constant, a register and memory, a hard register and a pseudo |
5746 | register, or memory and a constant and put it into the reload | |
5747 | register. The best possible way of doing this is if the machine | |
5748 | has a three-operand ADD insn that accepts the required operands. | |
32131a9c RK |
5749 | |
5750 | The simplest approach is to try to generate such an insn and see if it | |
5751 | is recognized and matches its constraints. If so, it can be used. | |
5752 | ||
5753 | It might be better not to actually emit the insn unless it is valid, | |
0009eff2 | 5754 | but we need to pass the insn as an operand to `recog' and |
b36d7dd7 | 5755 | `insn_extract' and it is simpler to emit and then delete the insn if |
0009eff2 | 5756 | not valid than to dummy things up. */ |
a8fdc208 | 5757 | |
af929c62 | 5758 | rtx op0, op1, tem, insn; |
32131a9c | 5759 | int code; |
a8fdc208 | 5760 | |
af929c62 RK |
5761 | op0 = find_replacement (&XEXP (in, 0)); |
5762 | op1 = find_replacement (&XEXP (in, 1)); | |
5763 | ||
32131a9c RK |
5764 | /* Since constraint checking is strict, commutativity won't be |
5765 | checked, so we need to do that here to avoid spurious failure | |
5766 | if the add instruction is two-address and the second operand | |
5767 | of the add is the same as the reload reg, which is frequently | |
5768 | the case. If the insn would be A = B + A, rearrange it so | |
5769 | it will be A = A + B as constrain_operands expects. */ | |
a8fdc208 | 5770 | |
32131a9c RK |
5771 | if (GET_CODE (XEXP (in, 1)) == REG |
5772 | && REGNO (reloadreg) == REGNO (XEXP (in, 1))) | |
af929c62 RK |
5773 | tem = op0, op0 = op1, op1 = tem; |
5774 | ||
5775 | if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) | |
5776 | in = gen_rtx (PLUS, GET_MODE (in), op0, op1); | |
32131a9c RK |
5777 | |
5778 | insn = emit_insn_before (gen_rtx (SET, VOIDmode, reloadreg, in), | |
5779 | before_insn); | |
5780 | code = recog_memoized (insn); | |
5781 | ||
5782 | if (code >= 0) | |
5783 | { | |
5784 | insn_extract (insn); | |
5785 | /* We want constrain operands to treat this insn strictly in | |
5786 | its validity determination, i.e., the way it would after reload | |
5787 | has completed. */ | |
5788 | if (constrain_operands (code, 1)) | |
5789 | return insn; | |
5790 | } | |
5791 | ||
5792 | if (PREV_INSN (insn)) | |
5793 | NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); | |
5794 | if (NEXT_INSN (insn)) | |
5795 | PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); | |
5796 | ||
5797 | /* If that failed, we must use a conservative two-insn sequence. | |
5798 | use move to copy constant, MEM, or pseudo register to the reload | |
af929c62 RK |
5799 | register since "move" will be able to handle an arbitrary operand, |
5800 | unlike add which can't, in general. Then add the registers. | |
32131a9c RK |
5801 | |
5802 | If there is another way to do this for a specific machine, a | |
5803 | DEFINE_PEEPHOLE should be specified that recognizes the sequence | |
5804 | we emit below. */ | |
5805 | ||
af929c62 RK |
5806 | if (CONSTANT_P (op1) || GET_CODE (op1) == MEM |
5807 | || (GET_CODE (op1) == REG | |
5808 | && REGNO (op1) >= FIRST_PSEUDO_REGISTER)) | |
5809 | tem = op0, op0 = op1, op1 = tem; | |
32131a9c | 5810 | |
af929c62 | 5811 | emit_insn_before (gen_move_insn (reloadreg, op0), before_insn); |
39b56c2a RK |
5812 | |
5813 | /* If OP0 and OP1 are the same, we can use RELOADREG for OP1. | |
5814 | This fixes a problem on the 32K where the stack pointer cannot | |
5815 | be used as an operand of an add insn. */ | |
5816 | ||
5817 | if (rtx_equal_p (op0, op1)) | |
5818 | op1 = reloadreg; | |
5819 | ||
af929c62 | 5820 | emit_insn_before (gen_add2_insn (reloadreg, op1), before_insn); |
32131a9c RK |
5821 | } |
5822 | ||
0dadecf6 RK |
5823 | #ifdef SECONDARY_MEMORY_NEEDED |
5824 | /* If we need a memory location to do the move, do it that way. */ | |
5825 | else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER | |
5826 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), | |
5827 | REGNO_REG_CLASS (REGNO (reloadreg)), | |
5828 | GET_MODE (reloadreg))) | |
5829 | { | |
5830 | /* Get the memory to use and rewrite both registers to its mode. */ | |
5831 | rtx loc = get_secondary_mem (in, GET_MODE (reloadreg)); | |
5832 | ||
5833 | if (GET_MODE (loc) != GET_MODE (reloadreg)) | |
5834 | reloadreg = gen_rtx (REG, GET_MODE (loc), REGNO (reloadreg)); | |
5835 | ||
5836 | if (GET_MODE (loc) != GET_MODE (in)) | |
5837 | in = gen_rtx (REG, GET_MODE (loc), REGNO (in)); | |
5838 | ||
0dadecf6 | 5839 | emit_insn_before (gen_move_insn (loc, in), before_insn); |
58c8c593 | 5840 | emit_insn_before (gen_move_insn (reloadreg, loc), before_insn); |
0dadecf6 RK |
5841 | } |
5842 | #endif | |
5843 | ||
32131a9c RK |
5844 | /* If IN is a simple operand, use gen_move_insn. */ |
5845 | else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG) | |
3c3eeea6 | 5846 | emit_insn_before (gen_move_insn (reloadreg, in), before_insn); |
32131a9c RK |
5847 | |
5848 | #ifdef HAVE_reload_load_address | |
5849 | else if (HAVE_reload_load_address) | |
3c3eeea6 | 5850 | emit_insn_before (gen_reload_load_address (reloadreg, in), before_insn); |
32131a9c RK |
5851 | #endif |
5852 | ||
5853 | /* Otherwise, just write (set REGLOADREG IN) and hope for the best. */ | |
5854 | else | |
3c3eeea6 | 5855 | emit_insn_before (gen_rtx (SET, VOIDmode, reloadreg, in), before_insn); |
32131a9c RK |
5856 | |
5857 | /* Return the first insn emitted. | |
5858 | We can not just return PREV_INSN (before_insn), because there may have | |
5859 | been multiple instructions emitted. Also note that gen_move_insn may | |
5860 | emit more than one insn itself, so we can not assume that there is one | |
5861 | insn emitted per emit_insn_before call. */ | |
5862 | ||
5863 | return NEXT_INSN (prev_insn); | |
5864 | } | |
5865 | \f | |
5866 | /* Delete a previously made output-reload | |
5867 | whose result we now believe is not needed. | |
5868 | First we double-check. | |
5869 | ||
5870 | INSN is the insn now being processed. | |
5871 | OUTPUT_RELOAD_INSN is the insn of the output reload. | |
5872 | J is the reload-number for this insn. */ | |
5873 | ||
5874 | static void | |
5875 | delete_output_reload (insn, j, output_reload_insn) | |
5876 | rtx insn; | |
5877 | int j; | |
5878 | rtx output_reload_insn; | |
5879 | { | |
5880 | register rtx i1; | |
5881 | ||
5882 | /* Get the raw pseudo-register referred to. */ | |
5883 | ||
5884 | rtx reg = reload_in[j]; | |
5885 | while (GET_CODE (reg) == SUBREG) | |
5886 | reg = SUBREG_REG (reg); | |
5887 | ||
5888 | /* If the pseudo-reg we are reloading is no longer referenced | |
5889 | anywhere between the store into it and here, | |
5890 | and no jumps or labels intervene, then the value can get | |
5891 | here through the reload reg alone. | |
5892 | Otherwise, give up--return. */ | |
5893 | for (i1 = NEXT_INSN (output_reload_insn); | |
5894 | i1 != insn; i1 = NEXT_INSN (i1)) | |
5895 | { | |
5896 | if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN) | |
5897 | return; | |
5898 | if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN) | |
5899 | && reg_mentioned_p (reg, PATTERN (i1))) | |
5900 | return; | |
5901 | } | |
5902 | ||
5903 | /* If this insn will store in the pseudo again, | |
5904 | the previous store can be removed. */ | |
5905 | if (reload_out[j] == reload_in[j]) | |
5906 | delete_insn (output_reload_insn); | |
5907 | ||
5908 | /* See if the pseudo reg has been completely replaced | |
5909 | with reload regs. If so, delete the store insn | |
5910 | and forget we had a stack slot for the pseudo. */ | |
5911 | else if (reg_n_deaths[REGNO (reg)] == 1 | |
5912 | && reg_basic_block[REGNO (reg)] >= 0 | |
5913 | && find_regno_note (insn, REG_DEAD, REGNO (reg))) | |
5914 | { | |
5915 | rtx i2; | |
5916 | ||
5917 | /* We know that it was used only between here | |
5918 | and the beginning of the current basic block. | |
5919 | (We also know that the last use before INSN was | |
5920 | the output reload we are thinking of deleting, but never mind that.) | |
5921 | Search that range; see if any ref remains. */ | |
5922 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) | |
5923 | { | |
d445b551 RK |
5924 | rtx set = single_set (i2); |
5925 | ||
32131a9c RK |
5926 | /* Uses which just store in the pseudo don't count, |
5927 | since if they are the only uses, they are dead. */ | |
d445b551 | 5928 | if (set != 0 && SET_DEST (set) == reg) |
32131a9c RK |
5929 | continue; |
5930 | if (GET_CODE (i2) == CODE_LABEL | |
5931 | || GET_CODE (i2) == JUMP_INSN) | |
5932 | break; | |
5933 | if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN) | |
5934 | && reg_mentioned_p (reg, PATTERN (i2))) | |
5935 | /* Some other ref remains; | |
5936 | we can't do anything. */ | |
5937 | return; | |
5938 | } | |
5939 | ||
5940 | /* Delete the now-dead stores into this pseudo. */ | |
5941 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) | |
5942 | { | |
d445b551 RK |
5943 | rtx set = single_set (i2); |
5944 | ||
5945 | if (set != 0 && SET_DEST (set) == reg) | |
32131a9c RK |
5946 | delete_insn (i2); |
5947 | if (GET_CODE (i2) == CODE_LABEL | |
5948 | || GET_CODE (i2) == JUMP_INSN) | |
5949 | break; | |
5950 | } | |
5951 | ||
5952 | /* For the debugging info, | |
5953 | say the pseudo lives in this reload reg. */ | |
5954 | reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]); | |
5955 | alter_reg (REGNO (reg), -1); | |
5956 | } | |
5957 | } | |
5958 | ||
5959 | \f | |
a8fdc208 | 5960 | /* Output reload-insns to reload VALUE into RELOADREG. |
858a47b1 | 5961 | VALUE is an autoincrement or autodecrement RTX whose operand |
32131a9c RK |
5962 | is a register or memory location; |
5963 | so reloading involves incrementing that location. | |
5964 | ||
5965 | INC_AMOUNT is the number to increment or decrement by (always positive). | |
5966 | This cannot be deduced from VALUE. | |
5967 | ||
5968 | INSN is the insn before which the new insns should be emitted. | |
5969 | ||
5970 | The return value is the first of the insns emitted. */ | |
5971 | ||
5972 | static rtx | |
5973 | inc_for_reload (reloadreg, value, inc_amount, insn) | |
5974 | rtx reloadreg; | |
5975 | rtx value; | |
5976 | int inc_amount; | |
5977 | rtx insn; | |
5978 | { | |
5979 | /* REG or MEM to be copied and incremented. */ | |
5980 | rtx incloc = XEXP (value, 0); | |
5981 | /* Nonzero if increment after copying. */ | |
5982 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC); | |
0009eff2 RK |
5983 | rtx prev = PREV_INSN (insn); |
5984 | rtx inc; | |
5985 | rtx add_insn; | |
5986 | int code; | |
32131a9c RK |
5987 | |
5988 | /* No hard register is equivalent to this register after | |
5989 | inc/dec operation. If REG_LAST_RELOAD_REG were non-zero, | |
5990 | we could inc/dec that register as well (maybe even using it for | |
5991 | the source), but I'm not sure it's worth worrying about. */ | |
5992 | if (GET_CODE (incloc) == REG) | |
5993 | reg_last_reload_reg[REGNO (incloc)] = 0; | |
5994 | ||
5995 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
5996 | inc_amount = - inc_amount; | |
5997 | ||
fb3821f7 | 5998 | inc = GEN_INT (inc_amount); |
0009eff2 RK |
5999 | |
6000 | /* If this is post-increment, first copy the location to the reload reg. */ | |
6001 | if (post) | |
6002 | emit_insn_before (gen_move_insn (reloadreg, incloc), insn); | |
6003 | ||
6004 | /* See if we can directly increment INCLOC. Use a method similar to that | |
6005 | in gen_input_reload. */ | |
6006 | ||
6007 | add_insn = emit_insn_before (gen_rtx (SET, VOIDmode, incloc, | |
6008 | gen_rtx (PLUS, GET_MODE (incloc), | |
6009 | incloc, inc)), insn); | |
6010 | ||
6011 | code = recog_memoized (add_insn); | |
6012 | if (code >= 0) | |
32131a9c | 6013 | { |
0009eff2 RK |
6014 | insn_extract (add_insn); |
6015 | if (constrain_operands (code, 1)) | |
32131a9c | 6016 | { |
0009eff2 RK |
6017 | /* If this is a pre-increment and we have incremented the value |
6018 | where it lives, copy the incremented value to RELOADREG to | |
6019 | be used as an address. */ | |
6020 | ||
6021 | if (! post) | |
6022 | emit_insn_before (gen_move_insn (reloadreg, incloc), insn); | |
6023 | return NEXT_INSN (prev); | |
32131a9c RK |
6024 | } |
6025 | } | |
0009eff2 RK |
6026 | |
6027 | if (PREV_INSN (add_insn)) | |
6028 | NEXT_INSN (PREV_INSN (add_insn)) = NEXT_INSN (add_insn); | |
6029 | if (NEXT_INSN (add_insn)) | |
6030 | PREV_INSN (NEXT_INSN (add_insn)) = PREV_INSN (add_insn); | |
6031 | ||
6032 | /* If couldn't do the increment directly, must increment in RELOADREG. | |
6033 | The way we do this depends on whether this is pre- or post-increment. | |
6034 | For pre-increment, copy INCLOC to the reload register, increment it | |
6035 | there, then save back. */ | |
6036 | ||
6037 | if (! post) | |
6038 | { | |
6039 | emit_insn_before (gen_move_insn (reloadreg, incloc), insn); | |
6040 | emit_insn_before (gen_add2_insn (reloadreg, inc), insn); | |
6041 | emit_insn_before (gen_move_insn (incloc, reloadreg), insn); | |
6042 | } | |
32131a9c RK |
6043 | else |
6044 | { | |
0009eff2 RK |
6045 | /* Postincrement. |
6046 | Because this might be a jump insn or a compare, and because RELOADREG | |
6047 | may not be available after the insn in an input reload, we must do | |
6048 | the incrementation before the insn being reloaded for. | |
6049 | ||
6050 | We have already copied INCLOC to RELOADREG. Increment the copy in | |
6051 | RELOADREG, save that back, then decrement RELOADREG so it has | |
6052 | the original value. */ | |
6053 | ||
6054 | emit_insn_before (gen_add2_insn (reloadreg, inc), insn); | |
6055 | emit_insn_before (gen_move_insn (incloc, reloadreg), insn); | |
fb3821f7 | 6056 | emit_insn_before (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)), |
0009eff2 | 6057 | insn); |
32131a9c | 6058 | } |
0009eff2 RK |
6059 | |
6060 | return NEXT_INSN (prev); | |
32131a9c RK |
6061 | } |
6062 | \f | |
6063 | /* Return 1 if we are certain that the constraint-string STRING allows | |
6064 | the hard register REG. Return 0 if we can't be sure of this. */ | |
6065 | ||
6066 | static int | |
6067 | constraint_accepts_reg_p (string, reg) | |
6068 | char *string; | |
6069 | rtx reg; | |
6070 | { | |
6071 | int value = 0; | |
6072 | int regno = true_regnum (reg); | |
6073 | int c; | |
6074 | ||
6075 | /* Initialize for first alternative. */ | |
6076 | value = 0; | |
6077 | /* Check that each alternative contains `g' or `r'. */ | |
6078 | while (1) | |
6079 | switch (c = *string++) | |
6080 | { | |
6081 | case 0: | |
6082 | /* If an alternative lacks `g' or `r', we lose. */ | |
6083 | return value; | |
6084 | case ',': | |
6085 | /* If an alternative lacks `g' or `r', we lose. */ | |
6086 | if (value == 0) | |
6087 | return 0; | |
6088 | /* Initialize for next alternative. */ | |
6089 | value = 0; | |
6090 | break; | |
6091 | case 'g': | |
6092 | case 'r': | |
6093 | /* Any general reg wins for this alternative. */ | |
6094 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno)) | |
6095 | value = 1; | |
6096 | break; | |
6097 | default: | |
6098 | /* Any reg in specified class wins for this alternative. */ | |
6099 | { | |
0009eff2 | 6100 | enum reg_class class = REG_CLASS_FROM_LETTER (c); |
32131a9c | 6101 | |
0009eff2 | 6102 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)) |
32131a9c RK |
6103 | value = 1; |
6104 | } | |
6105 | } | |
6106 | } | |
6107 | \f | |
d445b551 RK |
6108 | /* Return the number of places FIND appears within X, but don't count |
6109 | an occurrence if some SET_DEST is FIND. */ | |
32131a9c RK |
6110 | |
6111 | static int | |
6112 | count_occurrences (x, find) | |
6113 | register rtx x, find; | |
6114 | { | |
6115 | register int i, j; | |
6116 | register enum rtx_code code; | |
6117 | register char *format_ptr; | |
6118 | int count; | |
6119 | ||
6120 | if (x == find) | |
6121 | return 1; | |
6122 | if (x == 0) | |
6123 | return 0; | |
6124 | ||
6125 | code = GET_CODE (x); | |
6126 | ||
6127 | switch (code) | |
6128 | { | |
6129 | case REG: | |
6130 | case QUEUED: | |
6131 | case CONST_INT: | |
6132 | case CONST_DOUBLE: | |
6133 | case SYMBOL_REF: | |
6134 | case CODE_LABEL: | |
6135 | case PC: | |
6136 | case CC0: | |
6137 | return 0; | |
d445b551 RK |
6138 | |
6139 | case SET: | |
6140 | if (SET_DEST (x) == find) | |
6141 | return count_occurrences (SET_SRC (x), find); | |
6142 | break; | |
32131a9c RK |
6143 | } |
6144 | ||
6145 | format_ptr = GET_RTX_FORMAT (code); | |
6146 | count = 0; | |
6147 | ||
6148 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
6149 | { | |
6150 | switch (*format_ptr++) | |
6151 | { | |
6152 | case 'e': | |
6153 | count += count_occurrences (XEXP (x, i), find); | |
6154 | break; | |
6155 | ||
6156 | case 'E': | |
6157 | if (XVEC (x, i) != NULL) | |
6158 | { | |
6159 | for (j = 0; j < XVECLEN (x, i); j++) | |
6160 | count += count_occurrences (XVECEXP (x, i, j), find); | |
6161 | } | |
6162 | break; | |
6163 | } | |
6164 | } | |
6165 | return count; | |
6166 | } |