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32131a9c | 1 | /* Reload pseudo regs into hard regs for insns that require hard regs. |
a5cad800 | 2 | Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc. |
32131a9c RK |
3 | |
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
19 | Boston, MA 02111-1307, USA. */ | |
32131a9c RK |
20 | |
21 | ||
22 | #include "config.h" | |
670ee920 | 23 | #include "system.h" |
cab634f2 KG |
24 | |
25 | #include "machmode.h" | |
26 | #include "hard-reg-set.h" | |
32131a9c | 27 | #include "rtl.h" |
6baf1cc8 | 28 | #include "tm_p.h" |
32131a9c RK |
29 | #include "obstack.h" |
30 | #include "insn-config.h" | |
31 | #include "insn-flags.h" | |
32 | #include "insn-codes.h" | |
33 | #include "flags.h" | |
49ad7cfa | 34 | #include "function.h" |
32131a9c RK |
35 | #include "expr.h" |
36 | #include "regs.h" | |
cad6f7d0 | 37 | #include "basic-block.h" |
32131a9c RK |
38 | #include "reload.h" |
39 | #include "recog.h" | |
32131a9c | 40 | #include "output.h" |
a9c366bf | 41 | #include "real.h" |
10f0ad3d | 42 | #include "toplev.h" |
32131a9c | 43 | |
65954bd8 JL |
44 | #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY |
45 | #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY | |
46 | #endif | |
47 | ||
32131a9c RK |
48 | /* This file contains the reload pass of the compiler, which is |
49 | run after register allocation has been done. It checks that | |
50 | each insn is valid (operands required to be in registers really | |
51 | are in registers of the proper class) and fixes up invalid ones | |
52 | by copying values temporarily into registers for the insns | |
53 | that need them. | |
54 | ||
55 | The results of register allocation are described by the vector | |
56 | reg_renumber; the insns still contain pseudo regs, but reg_renumber | |
57 | can be used to find which hard reg, if any, a pseudo reg is in. | |
58 | ||
59 | The technique we always use is to free up a few hard regs that are | |
60 | called ``reload regs'', and for each place where a pseudo reg | |
61 | must be in a hard reg, copy it temporarily into one of the reload regs. | |
62 | ||
03acd8f8 BS |
63 | Reload regs are allocated locally for every instruction that needs |
64 | reloads. When there are pseudos which are allocated to a register that | |
65 | has been chosen as a reload reg, such pseudos must be ``spilled''. | |
66 | This means that they go to other hard regs, or to stack slots if no other | |
32131a9c RK |
67 | available hard regs can be found. Spilling can invalidate more |
68 | insns, requiring additional need for reloads, so we must keep checking | |
69 | until the process stabilizes. | |
70 | ||
71 | For machines with different classes of registers, we must keep track | |
72 | of the register class needed for each reload, and make sure that | |
73 | we allocate enough reload registers of each class. | |
74 | ||
75 | The file reload.c contains the code that checks one insn for | |
76 | validity and reports the reloads that it needs. This file | |
77 | is in charge of scanning the entire rtl code, accumulating the | |
78 | reload needs, spilling, assigning reload registers to use for | |
79 | fixing up each insn, and generating the new insns to copy values | |
80 | into the reload registers. */ | |
546b63fb RK |
81 | |
82 | ||
83 | #ifndef REGISTER_MOVE_COST | |
84 | #define REGISTER_MOVE_COST(x, y) 2 | |
85 | #endif | |
32131a9c RK |
86 | \f |
87 | /* During reload_as_needed, element N contains a REG rtx for the hard reg | |
0f41302f | 88 | into which reg N has been reloaded (perhaps for a previous insn). */ |
32131a9c RK |
89 | static rtx *reg_last_reload_reg; |
90 | ||
91 | /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn | |
92 | for an output reload that stores into reg N. */ | |
93 | static char *reg_has_output_reload; | |
94 | ||
95 | /* Indicates which hard regs are reload-registers for an output reload | |
96 | in the current insn. */ | |
97 | static HARD_REG_SET reg_is_output_reload; | |
98 | ||
99 | /* Element N is the constant value to which pseudo reg N is equivalent, | |
100 | or zero if pseudo reg N is not equivalent to a constant. | |
101 | find_reloads looks at this in order to replace pseudo reg N | |
102 | with the constant it stands for. */ | |
103 | rtx *reg_equiv_constant; | |
104 | ||
105 | /* Element N is a memory location to which pseudo reg N is equivalent, | |
106 | prior to any register elimination (such as frame pointer to stack | |
107 | pointer). Depending on whether or not it is a valid address, this value | |
108 | is transferred to either reg_equiv_address or reg_equiv_mem. */ | |
4803a34a | 109 | rtx *reg_equiv_memory_loc; |
32131a9c RK |
110 | |
111 | /* Element N is the address of stack slot to which pseudo reg N is equivalent. | |
112 | This is used when the address is not valid as a memory address | |
113 | (because its displacement is too big for the machine.) */ | |
114 | rtx *reg_equiv_address; | |
115 | ||
116 | /* Element N is the memory slot to which pseudo reg N is equivalent, | |
117 | or zero if pseudo reg N is not equivalent to a memory slot. */ | |
118 | rtx *reg_equiv_mem; | |
119 | ||
120 | /* Widest width in which each pseudo reg is referred to (via subreg). */ | |
121 | static int *reg_max_ref_width; | |
122 | ||
135eb61c | 123 | /* Element N is the list of insns that initialized reg N from its equivalent |
32131a9c RK |
124 | constant or memory slot. */ |
125 | static rtx *reg_equiv_init; | |
126 | ||
03acd8f8 BS |
127 | /* Vector to remember old contents of reg_renumber before spilling. */ |
128 | static short *reg_old_renumber; | |
129 | ||
e6e52be0 | 130 | /* During reload_as_needed, element N contains the last pseudo regno reloaded |
03acd8f8 | 131 | into hard register N. If that pseudo reg occupied more than one register, |
32131a9c RK |
132 | reg_reloaded_contents points to that pseudo for each spill register in |
133 | use; all of these must remain set for an inheritance to occur. */ | |
134 | static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; | |
135 | ||
136 | /* During reload_as_needed, element N contains the insn for which | |
e6e52be0 R |
137 | hard register N was last used. Its contents are significant only |
138 | when reg_reloaded_valid is set for this register. */ | |
32131a9c RK |
139 | static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; |
140 | ||
e6e52be0 R |
141 | /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */ |
142 | static HARD_REG_SET reg_reloaded_valid; | |
143 | /* Indicate if the register was dead at the end of the reload. | |
144 | This is only valid if reg_reloaded_contents is set and valid. */ | |
145 | static HARD_REG_SET reg_reloaded_dead; | |
146 | ||
32131a9c RK |
147 | /* Number of spill-regs so far; number of valid elements of spill_regs. */ |
148 | static int n_spills; | |
149 | ||
150 | /* In parallel with spill_regs, contains REG rtx's for those regs. | |
151 | Holds the last rtx used for any given reg, or 0 if it has never | |
152 | been used for spilling yet. This rtx is reused, provided it has | |
153 | the proper mode. */ | |
154 | static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
155 | ||
156 | /* In parallel with spill_regs, contains nonzero for a spill reg | |
157 | that was stored after the last time it was used. | |
158 | The precise value is the insn generated to do the store. */ | |
159 | static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
160 | ||
cb2afeb3 R |
161 | /* This is the register that was stored with spill_reg_store. This is a |
162 | copy of reload_out / reload_out_reg when the value was stored; if | |
163 | reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */ | |
164 | static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; | |
165 | ||
32131a9c RK |
166 | /* This table is the inverse mapping of spill_regs: |
167 | indexed by hard reg number, | |
168 | it contains the position of that reg in spill_regs, | |
05d10675 | 169 | or -1 for something that is not in spill_regs. |
13c8e8e3 JL |
170 | |
171 | ?!? This is no longer accurate. */ | |
32131a9c RK |
172 | static short spill_reg_order[FIRST_PSEUDO_REGISTER]; |
173 | ||
03acd8f8 BS |
174 | /* This reg set indicates registers that can't be used as spill registers for |
175 | the currently processed insn. These are the hard registers which are live | |
176 | during the insn, but not allocated to pseudos, as well as fixed | |
177 | registers. */ | |
32131a9c RK |
178 | static HARD_REG_SET bad_spill_regs; |
179 | ||
03acd8f8 BS |
180 | /* These are the hard registers that can't be used as spill register for any |
181 | insn. This includes registers used for user variables and registers that | |
182 | we can't eliminate. A register that appears in this set also can't be used | |
183 | to retry register allocation. */ | |
184 | static HARD_REG_SET bad_spill_regs_global; | |
185 | ||
32131a9c | 186 | /* Describes order of use of registers for reloading |
03acd8f8 BS |
187 | of spilled pseudo-registers. `n_spills' is the number of |
188 | elements that are actually valid; new ones are added at the end. | |
189 | ||
190 | Both spill_regs and spill_reg_order are used on two occasions: | |
191 | once during find_reload_regs, where they keep track of the spill registers | |
192 | for a single insn, but also during reload_as_needed where they show all | |
193 | the registers ever used by reload. For the latter case, the information | |
194 | is calculated during finish_spills. */ | |
32131a9c RK |
195 | static short spill_regs[FIRST_PSEUDO_REGISTER]; |
196 | ||
03acd8f8 BS |
197 | /* This vector of reg sets indicates, for each pseudo, which hard registers |
198 | may not be used for retrying global allocation because the register was | |
199 | formerly spilled from one of them. If we allowed reallocating a pseudo to | |
200 | a register that it was already allocated to, reload might not | |
201 | terminate. */ | |
202 | static HARD_REG_SET *pseudo_previous_regs; | |
203 | ||
204 | /* This vector of reg sets indicates, for each pseudo, which hard | |
205 | registers may not be used for retrying global allocation because they | |
206 | are used as spill registers during one of the insns in which the | |
207 | pseudo is live. */ | |
208 | static HARD_REG_SET *pseudo_forbidden_regs; | |
209 | ||
210 | /* All hard regs that have been used as spill registers for any insn are | |
211 | marked in this set. */ | |
212 | static HARD_REG_SET used_spill_regs; | |
8b4f9969 | 213 | |
4079cd63 JW |
214 | /* Index of last register assigned as a spill register. We allocate in |
215 | a round-robin fashion. */ | |
4079cd63 JW |
216 | static int last_spill_reg; |
217 | ||
32131a9c RK |
218 | /* Nonzero if indirect addressing is supported on the machine; this means |
219 | that spilling (REG n) does not require reloading it into a register in | |
220 | order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The | |
221 | value indicates the level of indirect addressing supported, e.g., two | |
222 | means that (MEM (MEM (REG n))) is also valid if (REG n) does not get | |
223 | a hard register. */ | |
32131a9c RK |
224 | static char spill_indirect_levels; |
225 | ||
226 | /* Nonzero if indirect addressing is supported when the innermost MEM is | |
227 | of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to | |
228 | which these are valid is the same as spill_indirect_levels, above. */ | |
32131a9c RK |
229 | char indirect_symref_ok; |
230 | ||
231 | /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ | |
32131a9c RK |
232 | char double_reg_address_ok; |
233 | ||
234 | /* Record the stack slot for each spilled hard register. */ | |
32131a9c RK |
235 | static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; |
236 | ||
237 | /* Width allocated so far for that stack slot. */ | |
32131a9c RK |
238 | static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; |
239 | ||
7609e720 | 240 | /* Record which pseudos needed to be spilled. */ |
f5d8c9f4 BS |
241 | static regset_head spilled_pseudos; |
242 | ||
243 | /* Used for communication between order_regs_for_reload and count_pseudo. | |
244 | Used to avoid counting one pseudo twice. */ | |
245 | static regset_head pseudos_counted; | |
7609e720 | 246 | |
32131a9c RK |
247 | /* First uid used by insns created by reload in this function. |
248 | Used in find_equiv_reg. */ | |
249 | int reload_first_uid; | |
250 | ||
251 | /* Flag set by local-alloc or global-alloc if anything is live in | |
252 | a call-clobbered reg across calls. */ | |
32131a9c RK |
253 | int caller_save_needed; |
254 | ||
255 | /* Set to 1 while reload_as_needed is operating. | |
256 | Required by some machines to handle any generated moves differently. */ | |
32131a9c RK |
257 | int reload_in_progress = 0; |
258 | ||
259 | /* These arrays record the insn_code of insns that may be needed to | |
260 | perform input and output reloads of special objects. They provide a | |
261 | place to pass a scratch register. */ | |
32131a9c RK |
262 | enum insn_code reload_in_optab[NUM_MACHINE_MODES]; |
263 | enum insn_code reload_out_optab[NUM_MACHINE_MODES]; | |
264 | ||
d45cf215 | 265 | /* This obstack is used for allocation of rtl during register elimination. |
32131a9c RK |
266 | The allocated storage can be freed once find_reloads has processed the |
267 | insn. */ | |
32131a9c | 268 | struct obstack reload_obstack; |
cad6f7d0 BS |
269 | |
270 | /* Points to the beginning of the reload_obstack. All insn_chain structures | |
271 | are allocated first. */ | |
272 | char *reload_startobj; | |
273 | ||
274 | /* The point after all insn_chain structures. Used to quickly deallocate | |
f5d8c9f4 | 275 | memory allocated in copy_reloads during calculate_needs_all_insns. */ |
32131a9c RK |
276 | char *reload_firstobj; |
277 | ||
f5d8c9f4 BS |
278 | /* This points before all local rtl generated by register elimination. |
279 | Used to quickly free all memory after processing one insn. */ | |
280 | static char *reload_insn_firstobj; | |
281 | ||
32131a9c RK |
282 | #define obstack_chunk_alloc xmalloc |
283 | #define obstack_chunk_free free | |
284 | ||
cad6f7d0 BS |
285 | /* List of insn_chain instructions, one for every insn that reload needs to |
286 | examine. */ | |
287 | struct insn_chain *reload_insn_chain; | |
7609e720 | 288 | |
dfb7c80f JL |
289 | #ifdef TREE_CODE |
290 | extern tree current_function_decl; | |
291 | #else | |
122a860e | 292 | extern union tree_node *current_function_decl; |
dfb7c80f JL |
293 | #endif |
294 | ||
03acd8f8 | 295 | /* List of all insns needing reloads. */ |
7609e720 | 296 | static struct insn_chain *insns_need_reload; |
32131a9c RK |
297 | \f |
298 | /* This structure is used to record information about register eliminations. | |
299 | Each array entry describes one possible way of eliminating a register | |
300 | in favor of another. If there is more than one way of eliminating a | |
301 | particular register, the most preferred should be specified first. */ | |
302 | ||
590cf94d | 303 | struct elim_table |
32131a9c | 304 | { |
0f41302f MS |
305 | int from; /* Register number to be eliminated. */ |
306 | int to; /* Register number used as replacement. */ | |
307 | int initial_offset; /* Initial difference between values. */ | |
308 | int can_eliminate; /* Non-zero if this elimination can be done. */ | |
32131a9c | 309 | int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over |
0f41302f MS |
310 | insns made by reload. */ |
311 | int offset; /* Current offset between the two regs. */ | |
0f41302f MS |
312 | int previous_offset; /* Offset at end of previous insn. */ |
313 | int ref_outside_mem; /* "to" has been referenced outside a MEM. */ | |
32131a9c RK |
314 | rtx from_rtx; /* REG rtx for the register to be eliminated. |
315 | We cannot simply compare the number since | |
316 | we might then spuriously replace a hard | |
317 | register corresponding to a pseudo | |
0f41302f MS |
318 | assigned to the reg to be eliminated. */ |
319 | rtx to_rtx; /* REG rtx for the replacement. */ | |
590cf94d KG |
320 | }; |
321 | ||
322 | static struct elim_table * reg_eliminate = 0; | |
323 | ||
324 | /* This is an intermediate structure to initialize the table. It has | |
325 | exactly the members provided by ELIMINABLE_REGS. */ | |
326 | static struct elim_table_1 | |
327 | { | |
328 | int from; | |
329 | int to; | |
330 | } reg_eliminate_1[] = | |
32131a9c RK |
331 | |
332 | /* If a set of eliminable registers was specified, define the table from it. | |
333 | Otherwise, default to the normal case of the frame pointer being | |
334 | replaced by the stack pointer. */ | |
335 | ||
336 | #ifdef ELIMINABLE_REGS | |
337 | ELIMINABLE_REGS; | |
338 | #else | |
339 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; | |
340 | #endif | |
341 | ||
590cf94d | 342 | #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0]) |
32131a9c RK |
343 | |
344 | /* Record the number of pending eliminations that have an offset not equal | |
345 | to their initial offset. If non-zero, we use a new copy of each | |
346 | replacement result in any insns encountered. */ | |
cb2afeb3 | 347 | int num_not_at_initial_offset; |
32131a9c RK |
348 | |
349 | /* Count the number of registers that we may be able to eliminate. */ | |
350 | static int num_eliminable; | |
2b49ee39 R |
351 | /* And the number of registers that are equivalent to a constant that |
352 | can be eliminated to frame_pointer / arg_pointer + constant. */ | |
353 | static int num_eliminable_invariants; | |
32131a9c RK |
354 | |
355 | /* For each label, we record the offset of each elimination. If we reach | |
356 | a label by more than one path and an offset differs, we cannot do the | |
357 | elimination. This information is indexed by the number of the label. | |
358 | The first table is an array of flags that records whether we have yet | |
359 | encountered a label and the second table is an array of arrays, one | |
360 | entry in the latter array for each elimination. */ | |
361 | ||
362 | static char *offsets_known_at; | |
363 | static int (*offsets_at)[NUM_ELIMINABLE_REGS]; | |
364 | ||
365 | /* Number of labels in the current function. */ | |
366 | ||
367 | static int num_labels; | |
368 | \f | |
18a90182 | 369 | static void maybe_fix_stack_asms PROTO((void)); |
f5d8c9f4 | 370 | static void copy_reloads PROTO((struct insn_chain *)); |
03acd8f8 | 371 | static void calculate_needs_all_insns PROTO((int)); |
f5d8c9f4 | 372 | static int find_reg PROTO((struct insn_chain *, int, |
03acd8f8 | 373 | FILE *)); |
f5d8c9f4 BS |
374 | static void find_reload_regs PROTO((struct insn_chain *, FILE *)); |
375 | static void select_reload_regs PROTO((FILE *)); | |
7609e720 | 376 | static void delete_caller_save_insns PROTO((void)); |
03acd8f8 | 377 | |
ecf3151a | 378 | static void spill_failure PROTO((rtx, enum reg_class)); |
f5d8c9f4 | 379 | static void count_spilled_pseudo PROTO((int, int, int)); |
546b63fb RK |
380 | static void delete_dead_insn PROTO((rtx)); |
381 | static void alter_reg PROTO((int, int)); | |
382 | static void set_label_offsets PROTO((rtx, rtx, int)); | |
dfac187e BS |
383 | static void check_eliminable_occurrences PROTO((rtx)); |
384 | static void elimination_effects PROTO((rtx, enum machine_mode)); | |
546b63fb | 385 | static int eliminate_regs_in_insn PROTO((rtx, int)); |
cb2afeb3 | 386 | static void update_eliminable_offsets PROTO((void)); |
84832317 | 387 | static void mark_not_eliminable PROTO((rtx, rtx, void *)); |
09dd1133 | 388 | static void set_initial_elim_offsets PROTO((void)); |
c47f5ea5 | 389 | static void verify_initial_elim_offsets PROTO((void)); |
1f3b1e1a JL |
390 | static void set_initial_label_offsets PROTO((void)); |
391 | static void set_offsets_for_label PROTO((rtx)); | |
09dd1133 BS |
392 | static void init_elim_table PROTO((void)); |
393 | static void update_eliminables PROTO((HARD_REG_SET *)); | |
03acd8f8 BS |
394 | static void spill_hard_reg PROTO((int, FILE *, int)); |
395 | static int finish_spills PROTO((int, FILE *)); | |
396 | static void ior_hard_reg_set PROTO((HARD_REG_SET *, HARD_REG_SET *)); | |
546b63fb | 397 | static void scan_paradoxical_subregs PROTO((rtx)); |
f5d8c9f4 | 398 | static void count_pseudo PROTO((int)); |
03acd8f8 | 399 | static void order_regs_for_reload PROTO((struct insn_chain *)); |
7609e720 | 400 | static void reload_as_needed PROTO((int)); |
84832317 | 401 | static void forget_old_reloads_1 PROTO((rtx, rtx, void *)); |
e1b6684c | 402 | static int reload_reg_class_lower PROTO((const PTR, const PTR)); |
546b63fb RK |
403 | static void mark_reload_reg_in_use PROTO((int, int, enum reload_type, |
404 | enum machine_mode)); | |
be7ae2a4 RK |
405 | static void clear_reload_reg_in_use PROTO((int, int, enum reload_type, |
406 | enum machine_mode)); | |
546b63fb | 407 | static int reload_reg_free_p PROTO((int, int, enum reload_type)); |
f5d8c9f4 BS |
408 | static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, |
409 | rtx, rtx, int, int)); | |
546b63fb | 410 | static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type)); |
f5d8c9f4 BS |
411 | static int allocate_reload_reg PROTO((struct insn_chain *, int, int)); |
412 | static void failed_reload PROTO((rtx, int)); | |
413 | static int set_reload_reg PROTO((int, int)); | |
67e61fe7 | 414 | static void choose_reload_regs_init PROTO((struct insn_chain *, rtx *)); |
03acd8f8 | 415 | static void choose_reload_regs PROTO((struct insn_chain *)); |
546b63fb | 416 | static void merge_assigned_reloads PROTO((rtx)); |
367b1cf5 BS |
417 | static void emit_input_reload_insns PROTO((struct insn_chain *, |
418 | struct reload *, rtx, int)); | |
419 | static void emit_output_reload_insns PROTO((struct insn_chain *, | |
420 | struct reload *, int)); | |
421 | static void do_input_reload PROTO((struct insn_chain *, | |
422 | struct reload *, int)); | |
423 | static void do_output_reload PROTO((struct insn_chain *, | |
424 | struct reload *, int)); | |
7609e720 | 425 | static void emit_reload_insns PROTO((struct insn_chain *)); |
cb2afeb3 R |
426 | static void delete_output_reload PROTO((rtx, int, int)); |
427 | static void delete_address_reloads PROTO((rtx, rtx)); | |
428 | static void delete_address_reloads_1 PROTO((rtx, rtx, rtx)); | |
429 | static rtx inc_for_reload PROTO((rtx, rtx, rtx, int)); | |
9b3142b3 | 430 | static int constraint_accepts_reg_p PROTO((const char *, rtx)); |
5adf6da0 | 431 | static void reload_cse_regs_1 PROTO((rtx)); |
2a9fb548 | 432 | static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int)); |
cbfc3ad3 | 433 | static int reload_cse_mem_conflict_p PROTO((rtx, rtx)); |
2a9fb548 | 434 | static void reload_cse_invalidate_mem PROTO((rtx)); |
84832317 | 435 | static void reload_cse_invalidate_rtx PROTO((rtx, rtx, void *)); |
2a9fb548 | 436 | static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode)); |
31418d35 | 437 | static int reload_cse_noop_set_p PROTO((rtx, rtx)); |
e9a25f70 JL |
438 | static int reload_cse_simplify_set PROTO((rtx, rtx)); |
439 | static int reload_cse_simplify_operands PROTO((rtx)); | |
84832317 | 440 | static void reload_cse_check_clobber PROTO((rtx, rtx, void *)); |
2a9fb548 | 441 | static void reload_cse_record_set PROTO((rtx, rtx)); |
5adf6da0 R |
442 | static void reload_combine PROTO((void)); |
443 | static void reload_combine_note_use PROTO((rtx *, rtx)); | |
84832317 | 444 | static void reload_combine_note_store PROTO((rtx, rtx, void *)); |
5adf6da0 | 445 | static void reload_cse_move2add PROTO((rtx)); |
84832317 | 446 | static void move2add_note_store PROTO((rtx, rtx, void *)); |
2dfa9a87 MH |
447 | #ifdef AUTO_INC_DEC |
448 | static void add_auto_inc_notes PROTO((rtx, rtx)); | |
449 | #endif | |
f428f252 KG |
450 | static rtx gen_mode_int PROTO((enum machine_mode, |
451 | HOST_WIDE_INT)); | |
a8f227e7 KG |
452 | static void failed_reload PROTO((rtx, int)); |
453 | static int set_reload_reg PROTO((int, int)); | |
f428f252 | 454 | extern void dump_needs PROTO((struct insn_chain *, FILE *)); |
32131a9c | 455 | \f |
546b63fb RK |
456 | /* Initialize the reload pass once per compilation. */ |
457 | ||
32131a9c RK |
458 | void |
459 | init_reload () | |
460 | { | |
461 | register int i; | |
462 | ||
463 | /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. | |
464 | Set spill_indirect_levels to the number of levels such addressing is | |
465 | permitted, zero if it is not permitted at all. */ | |
466 | ||
467 | register rtx tem | |
38a448ca RH |
468 | = gen_rtx_MEM (Pmode, |
469 | gen_rtx_PLUS (Pmode, | |
c5c76735 JL |
470 | gen_rtx_REG (Pmode, |
471 | LAST_VIRTUAL_REGISTER + 1), | |
38a448ca | 472 | GEN_INT (4))); |
32131a9c RK |
473 | spill_indirect_levels = 0; |
474 | ||
475 | while (memory_address_p (QImode, tem)) | |
476 | { | |
477 | spill_indirect_levels++; | |
38a448ca | 478 | tem = gen_rtx_MEM (Pmode, tem); |
32131a9c RK |
479 | } |
480 | ||
481 | /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ | |
482 | ||
38a448ca | 483 | tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo")); |
32131a9c RK |
484 | indirect_symref_ok = memory_address_p (QImode, tem); |
485 | ||
486 | /* See if reg+reg is a valid (and offsettable) address. */ | |
487 | ||
65701fd2 | 488 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
57caa638 | 489 | { |
38a448ca RH |
490 | tem = gen_rtx_PLUS (Pmode, |
491 | gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), | |
492 | gen_rtx_REG (Pmode, i)); | |
c5c76735 | 493 | |
57caa638 RS |
494 | /* This way, we make sure that reg+reg is an offsettable address. */ |
495 | tem = plus_constant (tem, 4); | |
496 | ||
497 | if (memory_address_p (QImode, tem)) | |
498 | { | |
499 | double_reg_address_ok = 1; | |
500 | break; | |
501 | } | |
502 | } | |
32131a9c | 503 | |
0f41302f | 504 | /* Initialize obstack for our rtl allocation. */ |
32131a9c | 505 | gcc_obstack_init (&reload_obstack); |
cad6f7d0 | 506 | reload_startobj = (char *) obstack_alloc (&reload_obstack, 0); |
f5d8c9f4 BS |
507 | |
508 | INIT_REG_SET (&spilled_pseudos); | |
509 | INIT_REG_SET (&pseudos_counted); | |
32131a9c RK |
510 | } |
511 | ||
cad6f7d0 BS |
512 | /* List of insn chains that are currently unused. */ |
513 | static struct insn_chain *unused_insn_chains = 0; | |
514 | ||
515 | /* Allocate an empty insn_chain structure. */ | |
516 | struct insn_chain * | |
517 | new_insn_chain () | |
518 | { | |
519 | struct insn_chain *c; | |
520 | ||
521 | if (unused_insn_chains == 0) | |
522 | { | |
8db99db2 KG |
523 | c = (struct insn_chain *) |
524 | obstack_alloc (&reload_obstack, sizeof (struct insn_chain)); | |
239a0f5b BS |
525 | INIT_REG_SET (&c->live_throughout); |
526 | INIT_REG_SET (&c->dead_or_set); | |
cad6f7d0 BS |
527 | } |
528 | else | |
529 | { | |
530 | c = unused_insn_chains; | |
531 | unused_insn_chains = c->next; | |
532 | } | |
533 | c->is_caller_save_insn = 0; | |
03acd8f8 | 534 | c->need_operand_change = 0; |
cad6f7d0 BS |
535 | c->need_reload = 0; |
536 | c->need_elim = 0; | |
537 | return c; | |
538 | } | |
539 | ||
7609e720 BS |
540 | /* Small utility function to set all regs in hard reg set TO which are |
541 | allocated to pseudos in regset FROM. */ | |
542 | void | |
543 | compute_use_by_pseudos (to, from) | |
544 | HARD_REG_SET *to; | |
545 | regset from; | |
546 | { | |
547 | int regno; | |
548 | EXECUTE_IF_SET_IN_REG_SET | |
549 | (from, FIRST_PSEUDO_REGISTER, regno, | |
550 | { | |
551 | int r = reg_renumber[regno]; | |
552 | int nregs; | |
553 | if (r < 0) | |
404d95c4 R |
554 | { |
555 | /* reload_combine uses the information from | |
e881bb1b RH |
556 | BASIC_BLOCK->global_live_at_start, which might still |
557 | contain registers that have not actually been allocated | |
558 | since they have an equivalence. */ | |
404d95c4 R |
559 | if (! reload_completed) |
560 | abort (); | |
561 | } | |
562 | else | |
563 | { | |
564 | nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno)); | |
565 | while (nregs-- > 0) | |
566 | SET_HARD_REG_BIT (*to, r + nregs); | |
567 | } | |
7609e720 BS |
568 | }); |
569 | } | |
03acd8f8 | 570 | \f |
1e5bd841 BS |
571 | /* Global variables used by reload and its subroutines. */ |
572 | ||
1e5bd841 BS |
573 | /* Set during calculate_needs if an insn needs register elimination. */ |
574 | static int something_needs_elimination; | |
cb2afeb3 R |
575 | /* Set during calculate_needs if an insn needs an operand changed. */ |
576 | int something_needs_operands_changed; | |
1e5bd841 | 577 | |
1e5bd841 BS |
578 | /* Nonzero means we couldn't get enough spill regs. */ |
579 | static int failure; | |
580 | ||
546b63fb | 581 | /* Main entry point for the reload pass. |
32131a9c RK |
582 | |
583 | FIRST is the first insn of the function being compiled. | |
584 | ||
585 | GLOBAL nonzero means we were called from global_alloc | |
586 | and should attempt to reallocate any pseudoregs that we | |
587 | displace from hard regs we will use for reloads. | |
588 | If GLOBAL is zero, we do not have enough information to do that, | |
589 | so any pseudo reg that is spilled must go to the stack. | |
590 | ||
591 | DUMPFILE is the global-reg debugging dump file stream, or 0. | |
592 | If it is nonzero, messages are written to it to describe | |
593 | which registers are seized as reload regs, which pseudo regs | |
5352b11a | 594 | are spilled from them, and where the pseudo regs are reallocated to. |
32131a9c | 595 | |
5352b11a RS |
596 | Return value is nonzero if reload failed |
597 | and we must not do any more for this function. */ | |
598 | ||
599 | int | |
32131a9c RK |
600 | reload (first, global, dumpfile) |
601 | rtx first; | |
602 | int global; | |
603 | FILE *dumpfile; | |
604 | { | |
03acd8f8 | 605 | register int i; |
32131a9c RK |
606 | register rtx insn; |
607 | register struct elim_table *ep; | |
608 | ||
a68d4b75 BK |
609 | /* The two pointers used to track the true location of the memory used |
610 | for label offsets. */ | |
611 | char *real_known_ptr = NULL_PTR; | |
612 | int (*real_at_ptr)[NUM_ELIMINABLE_REGS]; | |
613 | ||
32131a9c RK |
614 | /* Make sure even insns with volatile mem refs are recognizable. */ |
615 | init_recog (); | |
616 | ||
1e5bd841 BS |
617 | failure = 0; |
618 | ||
cad6f7d0 BS |
619 | reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); |
620 | ||
437a710d BS |
621 | /* Make sure that the last insn in the chain |
622 | is not something that needs reloading. */ | |
623 | emit_note (NULL_PTR, NOTE_INSN_DELETED); | |
624 | ||
32131a9c RK |
625 | /* Enable find_equiv_reg to distinguish insns made by reload. */ |
626 | reload_first_uid = get_max_uid (); | |
627 | ||
0dadecf6 RK |
628 | #ifdef SECONDARY_MEMORY_NEEDED |
629 | /* Initialize the secondary memory table. */ | |
630 | clear_secondary_mem (); | |
631 | #endif | |
632 | ||
32131a9c | 633 | /* We don't have a stack slot for any spill reg yet. */ |
4c9a05bc RK |
634 | bzero ((char *) spill_stack_slot, sizeof spill_stack_slot); |
635 | bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width); | |
32131a9c | 636 | |
a8efe40d RK |
637 | /* Initialize the save area information for caller-save, in case some |
638 | are needed. */ | |
639 | init_save_areas (); | |
a8fdc208 | 640 | |
32131a9c RK |
641 | /* Compute which hard registers are now in use |
642 | as homes for pseudo registers. | |
643 | This is done here rather than (eg) in global_alloc | |
644 | because this point is reached even if not optimizing. */ | |
32131a9c RK |
645 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
646 | mark_home_live (i); | |
647 | ||
8dddd002 RK |
648 | /* A function that receives a nonlocal goto must save all call-saved |
649 | registers. */ | |
650 | if (current_function_has_nonlocal_label) | |
651 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
652 | { | |
653 | if (! call_used_regs[i] && ! fixed_regs[i]) | |
654 | regs_ever_live[i] = 1; | |
655 | } | |
656 | ||
32131a9c RK |
657 | /* Find all the pseudo registers that didn't get hard regs |
658 | but do have known equivalent constants or memory slots. | |
659 | These include parameters (known equivalent to parameter slots) | |
660 | and cse'd or loop-moved constant memory addresses. | |
661 | ||
662 | Record constant equivalents in reg_equiv_constant | |
663 | so they will be substituted by find_reloads. | |
664 | Record memory equivalents in reg_mem_equiv so they can | |
665 | be substituted eventually by altering the REG-rtx's. */ | |
666 | ||
ad85216e KG |
667 | reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx)); |
668 | reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
669 | reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
670 | reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
671 | reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
672 | reg_max_ref_width = (int *) xcalloc (max_regno, sizeof (int)); | |
673 | reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short)); | |
47c3ed98 | 674 | bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short)); |
03acd8f8 BS |
675 | pseudo_forbidden_regs |
676 | = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET)); | |
677 | pseudo_previous_regs | |
ad85216e | 678 | = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET)); |
32131a9c | 679 | |
03acd8f8 | 680 | CLEAR_HARD_REG_SET (bad_spill_regs_global); |
56f58d3a | 681 | |
32131a9c | 682 | /* Look for REG_EQUIV notes; record what each pseudo is equivalent to. |
56f58d3a RK |
683 | Also find all paradoxical subregs and find largest such for each pseudo. |
684 | On machines with small register classes, record hard registers that | |
05d10675 | 685 | are used for user variables. These can never be used for spills. |
b453cb0b RK |
686 | Also look for a "constant" NOTE_INSN_SETJMP. This means that all |
687 | caller-saved registers must be marked live. */ | |
32131a9c | 688 | |
2b49ee39 | 689 | num_eliminable_invariants = 0; |
32131a9c RK |
690 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
691 | { | |
692 | rtx set = single_set (insn); | |
693 | ||
b453cb0b RK |
694 | if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn) |
695 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP) | |
696 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
697 | if (! call_used_regs[i]) | |
698 | regs_ever_live[i] = 1; | |
699 | ||
32131a9c RK |
700 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG) |
701 | { | |
fb3821f7 | 702 | rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
a8efe40d RK |
703 | if (note |
704 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
2b49ee39 R |
705 | && (! function_invariant_p (XEXP (note, 0)) |
706 | || ! flag_pic | |
a8efe40d RK |
707 | || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))) |
708 | #endif | |
709 | ) | |
32131a9c RK |
710 | { |
711 | rtx x = XEXP (note, 0); | |
712 | i = REGNO (SET_DEST (set)); | |
713 | if (i > LAST_VIRTUAL_REGISTER) | |
714 | { | |
715 | if (GET_CODE (x) == MEM) | |
956d6950 JL |
716 | { |
717 | /* If the operand is a PLUS, the MEM may be shared, | |
718 | so make sure we have an unshared copy here. */ | |
719 | if (GET_CODE (XEXP (x, 0)) == PLUS) | |
720 | x = copy_rtx (x); | |
721 | ||
722 | reg_equiv_memory_loc[i] = x; | |
723 | } | |
2b49ee39 | 724 | else if (function_invariant_p (x)) |
32131a9c | 725 | { |
2b49ee39 R |
726 | if (GET_CODE (x) == PLUS) |
727 | { | |
728 | /* This is PLUS of frame pointer and a constant, | |
729 | and might be shared. Unshare it. */ | |
730 | reg_equiv_constant[i] = copy_rtx (x); | |
731 | num_eliminable_invariants++; | |
732 | } | |
733 | else if (x == frame_pointer_rtx | |
734 | || x == arg_pointer_rtx) | |
735 | { | |
736 | reg_equiv_constant[i] = x; | |
737 | num_eliminable_invariants++; | |
738 | } | |
739 | else if (LEGITIMATE_CONSTANT_P (x)) | |
32131a9c RK |
740 | reg_equiv_constant[i] = x; |
741 | else | |
742 | reg_equiv_memory_loc[i] | |
d445b551 | 743 | = force_const_mem (GET_MODE (SET_DEST (set)), x); |
32131a9c RK |
744 | } |
745 | else | |
746 | continue; | |
747 | ||
748 | /* If this register is being made equivalent to a MEM | |
749 | and the MEM is not SET_SRC, the equivalencing insn | |
750 | is one with the MEM as a SET_DEST and it occurs later. | |
751 | So don't mark this insn now. */ | |
752 | if (GET_CODE (x) != MEM | |
753 | || rtx_equal_p (SET_SRC (set), x)) | |
135eb61c R |
754 | reg_equiv_init[i] |
755 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]); | |
32131a9c RK |
756 | } |
757 | } | |
758 | } | |
759 | ||
760 | /* If this insn is setting a MEM from a register equivalent to it, | |
761 | this is the equivalencing insn. */ | |
762 | else if (set && GET_CODE (SET_DEST (set)) == MEM | |
763 | && GET_CODE (SET_SRC (set)) == REG | |
764 | && reg_equiv_memory_loc[REGNO (SET_SRC (set))] | |
765 | && rtx_equal_p (SET_DEST (set), | |
766 | reg_equiv_memory_loc[REGNO (SET_SRC (set))])) | |
135eb61c R |
767 | reg_equiv_init[REGNO (SET_SRC (set))] |
768 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
769 | reg_equiv_init[REGNO (SET_SRC (set))]); | |
32131a9c RK |
770 | |
771 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
772 | scan_paradoxical_subregs (PATTERN (insn)); | |
773 | } | |
774 | ||
09dd1133 | 775 | init_elim_table (); |
32131a9c RK |
776 | |
777 | num_labels = max_label_num () - get_first_label_num (); | |
778 | ||
779 | /* Allocate the tables used to store offset information at labels. */ | |
a68d4b75 BK |
780 | /* We used to use alloca here, but the size of what it would try to |
781 | allocate would occasionally cause it to exceed the stack limit and | |
782 | cause a core dump. */ | |
783 | real_known_ptr = xmalloc (num_labels); | |
784 | real_at_ptr | |
32131a9c | 785 | = (int (*)[NUM_ELIMINABLE_REGS]) |
a68d4b75 | 786 | xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int)); |
32131a9c | 787 | |
a68d4b75 BK |
788 | offsets_known_at = real_known_ptr - get_first_label_num (); |
789 | offsets_at | |
790 | = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ()); | |
32131a9c RK |
791 | |
792 | /* Alter each pseudo-reg rtx to contain its hard reg number. | |
793 | Assign stack slots to the pseudos that lack hard regs or equivalents. | |
794 | Do not touch virtual registers. */ | |
795 | ||
796 | for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) | |
797 | alter_reg (i, -1); | |
798 | ||
32131a9c RK |
799 | /* If we have some registers we think can be eliminated, scan all insns to |
800 | see if there is an insn that sets one of these registers to something | |
801 | other than itself plus a constant. If so, the register cannot be | |
802 | eliminated. Doing this scan here eliminates an extra pass through the | |
803 | main reload loop in the most common case where register elimination | |
804 | cannot be done. */ | |
805 | for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) | |
806 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN | |
807 | || GET_CODE (insn) == CALL_INSN) | |
84832317 | 808 | note_stores (PATTERN (insn), mark_not_eliminable, NULL); |
32131a9c | 809 | |
18a90182 BS |
810 | maybe_fix_stack_asms (); |
811 | ||
03acd8f8 BS |
812 | insns_need_reload = 0; |
813 | something_needs_elimination = 0; | |
05d10675 | 814 | |
4079cd63 JW |
815 | /* Initialize to -1, which means take the first spill register. */ |
816 | last_spill_reg = -1; | |
817 | ||
32131a9c | 818 | /* Spill any hard regs that we know we can't eliminate. */ |
03acd8f8 | 819 | CLEAR_HARD_REG_SET (used_spill_regs); |
32131a9c RK |
820 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
821 | if (! ep->can_eliminate) | |
03acd8f8 | 822 | spill_hard_reg (ep->from, dumpfile, 1); |
9ff3516a RK |
823 | |
824 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
825 | if (frame_pointer_needed) | |
03acd8f8 | 826 | spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1); |
9ff3516a | 827 | #endif |
7609e720 BS |
828 | finish_spills (global, dumpfile); |
829 | ||
f1db3576 JL |
830 | /* From now on, we may need to generate moves differently. We may also |
831 | allow modifications of insns which cause them to not be recognized. | |
832 | Any such modifications will be cleaned up during reload itself. */ | |
b2f15f94 RK |
833 | reload_in_progress = 1; |
834 | ||
32131a9c RK |
835 | /* This loop scans the entire function each go-round |
836 | and repeats until one repetition spills no additional hard regs. */ | |
03acd8f8 | 837 | for (;;) |
32131a9c | 838 | { |
03acd8f8 BS |
839 | int something_changed; |
840 | int did_spill; | |
32131a9c | 841 | |
03acd8f8 | 842 | HOST_WIDE_INT starting_frame_size; |
32131a9c | 843 | |
7657bf2f JW |
844 | /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done |
845 | here because the stack size may be a part of the offset computation | |
846 | for register elimination, and there might have been new stack slots | |
847 | created in the last iteration of this loop. */ | |
848 | assign_stack_local (BLKmode, 0, 0); | |
849 | ||
850 | starting_frame_size = get_frame_size (); | |
851 | ||
09dd1133 | 852 | set_initial_elim_offsets (); |
1f3b1e1a | 853 | set_initial_label_offsets (); |
03acd8f8 | 854 | |
32131a9c RK |
855 | /* For each pseudo register that has an equivalent location defined, |
856 | try to eliminate any eliminable registers (such as the frame pointer) | |
857 | assuming initial offsets for the replacement register, which | |
858 | is the normal case. | |
859 | ||
860 | If the resulting location is directly addressable, substitute | |
861 | the MEM we just got directly for the old REG. | |
862 | ||
863 | If it is not addressable but is a constant or the sum of a hard reg | |
864 | and constant, it is probably not addressable because the constant is | |
865 | out of range, in that case record the address; we will generate | |
866 | hairy code to compute the address in a register each time it is | |
6491dbbb RK |
867 | needed. Similarly if it is a hard register, but one that is not |
868 | valid as an address register. | |
32131a9c RK |
869 | |
870 | If the location is not addressable, but does not have one of the | |
871 | above forms, assign a stack slot. We have to do this to avoid the | |
872 | potential of producing lots of reloads if, e.g., a location involves | |
873 | a pseudo that didn't get a hard register and has an equivalent memory | |
874 | location that also involves a pseudo that didn't get a hard register. | |
875 | ||
876 | Perhaps at some point we will improve reload_when_needed handling | |
877 | so this problem goes away. But that's very hairy. */ | |
878 | ||
879 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
880 | if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) | |
881 | { | |
1914f5da | 882 | rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX); |
32131a9c RK |
883 | |
884 | if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]), | |
885 | XEXP (x, 0))) | |
886 | reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; | |
887 | else if (CONSTANT_P (XEXP (x, 0)) | |
6491dbbb RK |
888 | || (GET_CODE (XEXP (x, 0)) == REG |
889 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
32131a9c RK |
890 | || (GET_CODE (XEXP (x, 0)) == PLUS |
891 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
892 | && (REGNO (XEXP (XEXP (x, 0), 0)) | |
893 | < FIRST_PSEUDO_REGISTER) | |
894 | && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) | |
895 | reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; | |
896 | else | |
897 | { | |
898 | /* Make a new stack slot. Then indicate that something | |
a8fdc208 | 899 | changed so we go back and recompute offsets for |
32131a9c RK |
900 | eliminable registers because the allocation of memory |
901 | below might change some offset. reg_equiv_{mem,address} | |
902 | will be set up for this pseudo on the next pass around | |
903 | the loop. */ | |
904 | reg_equiv_memory_loc[i] = 0; | |
905 | reg_equiv_init[i] = 0; | |
906 | alter_reg (i, -1); | |
32131a9c RK |
907 | } |
908 | } | |
a8fdc208 | 909 | |
437a710d BS |
910 | if (caller_save_needed) |
911 | setup_save_areas (); | |
912 | ||
03acd8f8 | 913 | /* If we allocated another stack slot, redo elimination bookkeeping. */ |
437a710d | 914 | if (starting_frame_size != get_frame_size ()) |
32131a9c RK |
915 | continue; |
916 | ||
437a710d | 917 | if (caller_save_needed) |
a8efe40d | 918 | { |
437a710d BS |
919 | save_call_clobbered_regs (); |
920 | /* That might have allocated new insn_chain structures. */ | |
921 | reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); | |
a8efe40d RK |
922 | } |
923 | ||
03acd8f8 BS |
924 | calculate_needs_all_insns (global); |
925 | ||
f5d8c9f4 | 926 | CLEAR_REG_SET (&spilled_pseudos); |
03acd8f8 BS |
927 | did_spill = 0; |
928 | ||
929 | something_changed = 0; | |
32131a9c | 930 | |
0dadecf6 RK |
931 | /* If we allocated any new memory locations, make another pass |
932 | since it might have changed elimination offsets. */ | |
933 | if (starting_frame_size != get_frame_size ()) | |
934 | something_changed = 1; | |
935 | ||
09dd1133 BS |
936 | { |
937 | HARD_REG_SET to_spill; | |
938 | CLEAR_HARD_REG_SET (to_spill); | |
939 | update_eliminables (&to_spill); | |
940 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
941 | if (TEST_HARD_REG_BIT (to_spill, i)) | |
32131a9c | 942 | { |
03acd8f8 BS |
943 | spill_hard_reg (i, dumpfile, 1); |
944 | did_spill = 1; | |
8f5db3c1 JL |
945 | |
946 | /* Regardless of the state of spills, if we previously had | |
947 | a register that we thought we could eliminate, but no can | |
948 | not eliminate, we must run another pass. | |
949 | ||
950 | Consider pseudos which have an entry in reg_equiv_* which | |
951 | reference an eliminable register. We must make another pass | |
952 | to update reg_equiv_* so that we do not substitute in the | |
953 | old value from when we thought the elimination could be | |
954 | performed. */ | |
955 | something_changed = 1; | |
32131a9c | 956 | } |
09dd1133 | 957 | } |
9ff3516a | 958 | |
e483bf9c BS |
959 | select_reload_regs (dumpfile); |
960 | if (failure) | |
961 | goto failed; | |
437a710d | 962 | |
e483bf9c BS |
963 | if (insns_need_reload != 0 || did_spill) |
964 | something_changed |= finish_spills (global, dumpfile); | |
7609e720 | 965 | |
03acd8f8 BS |
966 | if (! something_changed) |
967 | break; | |
968 | ||
969 | if (caller_save_needed) | |
7609e720 | 970 | delete_caller_save_insns (); |
f5d8c9f4 BS |
971 | |
972 | obstack_free (&reload_obstack, reload_firstobj); | |
32131a9c RK |
973 | } |
974 | ||
975 | /* If global-alloc was run, notify it of any register eliminations we have | |
976 | done. */ | |
977 | if (global) | |
978 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
979 | if (ep->can_eliminate) | |
980 | mark_elimination (ep->from, ep->to); | |
981 | ||
32131a9c RK |
982 | /* If a pseudo has no hard reg, delete the insns that made the equivalence. |
983 | If that insn didn't set the register (i.e., it copied the register to | |
984 | memory), just delete that insn instead of the equivalencing insn plus | |
985 | anything now dead. If we call delete_dead_insn on that insn, we may | |
135eb61c | 986 | delete the insn that actually sets the register if the register dies |
32131a9c RK |
987 | there and that is incorrect. */ |
988 | ||
989 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
135eb61c R |
990 | { |
991 | if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0) | |
992 | { | |
993 | rtx list; | |
994 | for (list = reg_equiv_init[i]; list; list = XEXP (list, 1)) | |
995 | { | |
996 | rtx equiv_insn = XEXP (list, 0); | |
997 | if (GET_CODE (equiv_insn) == NOTE) | |
998 | continue; | |
999 | if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn))) | |
1000 | delete_dead_insn (equiv_insn); | |
1001 | else | |
1002 | { | |
1003 | PUT_CODE (equiv_insn, NOTE); | |
1004 | NOTE_SOURCE_FILE (equiv_insn) = 0; | |
1005 | NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; | |
1006 | } | |
1007 | } | |
1008 | } | |
1009 | } | |
32131a9c RK |
1010 | |
1011 | /* Use the reload registers where necessary | |
1012 | by generating move instructions to move the must-be-register | |
1013 | values into or out of the reload registers. */ | |
1014 | ||
03acd8f8 BS |
1015 | if (insns_need_reload != 0 || something_needs_elimination |
1016 | || something_needs_operands_changed) | |
c47f5ea5 BS |
1017 | { |
1018 | int old_frame_size = get_frame_size (); | |
1019 | ||
1020 | reload_as_needed (global); | |
1021 | ||
1022 | if (old_frame_size != get_frame_size ()) | |
1023 | abort (); | |
1024 | ||
1025 | if (num_eliminable) | |
1026 | verify_initial_elim_offsets (); | |
1027 | } | |
32131a9c | 1028 | |
2a1f8b6b | 1029 | /* If we were able to eliminate the frame pointer, show that it is no |
546b63fb | 1030 | longer live at the start of any basic block. If it ls live by |
2a1f8b6b RK |
1031 | virtue of being in a pseudo, that pseudo will be marked live |
1032 | and hence the frame pointer will be known to be live via that | |
1033 | pseudo. */ | |
1034 | ||
1035 | if (! frame_pointer_needed) | |
1036 | for (i = 0; i < n_basic_blocks; i++) | |
e881bb1b | 1037 | CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start, |
8e08106d | 1038 | HARD_FRAME_POINTER_REGNUM); |
2a1f8b6b | 1039 | |
5352b11a RS |
1040 | /* Come here (with failure set nonzero) if we can't get enough spill regs |
1041 | and we decide not to abort about it. */ | |
1042 | failed: | |
1043 | ||
f5d8c9f4 | 1044 | CLEAR_REG_SET (&spilled_pseudos); |
a3ec87a8 RS |
1045 | reload_in_progress = 0; |
1046 | ||
32131a9c RK |
1047 | /* Now eliminate all pseudo regs by modifying them into |
1048 | their equivalent memory references. | |
1049 | The REG-rtx's for the pseudos are modified in place, | |
1050 | so all insns that used to refer to them now refer to memory. | |
1051 | ||
1052 | For a reg that has a reg_equiv_address, all those insns | |
1053 | were changed by reloading so that no insns refer to it any longer; | |
1054 | but the DECL_RTL of a variable decl may refer to it, | |
1055 | and if so this causes the debugging info to mention the variable. */ | |
1056 | ||
1057 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1058 | { | |
1059 | rtx addr = 0; | |
ab1fd483 | 1060 | int in_struct = 0; |
6a651371 | 1061 | int is_scalar = 0; |
9ec36da5 JL |
1062 | int is_readonly = 0; |
1063 | ||
1064 | if (reg_equiv_memory_loc[i]) | |
ab1fd483 | 1065 | { |
9ec36da5 | 1066 | in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]); |
c6df88cb | 1067 | is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]); |
9ec36da5 | 1068 | is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]); |
ab1fd483 | 1069 | } |
9ec36da5 JL |
1070 | |
1071 | if (reg_equiv_mem[i]) | |
1072 | addr = XEXP (reg_equiv_mem[i], 0); | |
1073 | ||
32131a9c RK |
1074 | if (reg_equiv_address[i]) |
1075 | addr = reg_equiv_address[i]; | |
9ec36da5 | 1076 | |
32131a9c RK |
1077 | if (addr) |
1078 | { | |
1079 | if (reg_renumber[i] < 0) | |
1080 | { | |
1081 | rtx reg = regno_reg_rtx[i]; | |
ef178af3 | 1082 | PUT_CODE (reg, MEM); |
32131a9c RK |
1083 | XEXP (reg, 0) = addr; |
1084 | REG_USERVAR_P (reg) = 0; | |
9ec36da5 | 1085 | RTX_UNCHANGING_P (reg) = is_readonly; |
ab1fd483 | 1086 | MEM_IN_STRUCT_P (reg) = in_struct; |
c6df88cb | 1087 | MEM_SCALAR_P (reg) = is_scalar; |
41472af8 MM |
1088 | /* We have no alias information about this newly created |
1089 | MEM. */ | |
1090 | MEM_ALIAS_SET (reg) = 0; | |
32131a9c RK |
1091 | } |
1092 | else if (reg_equiv_mem[i]) | |
1093 | XEXP (reg_equiv_mem[i], 0) = addr; | |
1094 | } | |
1095 | } | |
1096 | ||
2ae74651 JL |
1097 | /* We must set reload_completed now since the cleanup_subreg_operands call |
1098 | below will re-recognize each insn and reload may have generated insns | |
1099 | which are only valid during and after reload. */ | |
1100 | reload_completed = 1; | |
1101 | ||
bd695e1e RH |
1102 | /* Make a pass over all the insns and delete all USEs which we inserted |
1103 | only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED | |
1104 | notes. Delete all CLOBBER insns that don't refer to the return value | |
1105 | and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and | |
1106 | REG_LIBCALL notes since they are no longer useful or accurate. Strip | |
1107 | and regenerate REG_INC notes that may have been moved around. */ | |
32131a9c RK |
1108 | |
1109 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
1110 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
1111 | { | |
6764d250 | 1112 | rtx *pnote; |
32131a9c | 1113 | |
0304f787 JL |
1114 | if ((GET_CODE (PATTERN (insn)) == USE |
1115 | && find_reg_note (insn, REG_EQUAL, NULL_RTX)) | |
bd695e1e RH |
1116 | || (GET_CODE (PATTERN (insn)) == CLOBBER |
1117 | && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG | |
1118 | || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0))))) | |
b60a8416 R |
1119 | { |
1120 | PUT_CODE (insn, NOTE); | |
1121 | NOTE_SOURCE_FILE (insn) = 0; | |
1122 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
1123 | continue; | |
1124 | } | |
6764d250 BS |
1125 | |
1126 | pnote = ®_NOTES (insn); | |
1127 | while (*pnote != 0) | |
32131a9c | 1128 | { |
6764d250 | 1129 | if (REG_NOTE_KIND (*pnote) == REG_DEAD |
80599fd9 | 1130 | || REG_NOTE_KIND (*pnote) == REG_UNUSED |
2dfa9a87 | 1131 | || REG_NOTE_KIND (*pnote) == REG_INC |
80599fd9 NC |
1132 | || REG_NOTE_KIND (*pnote) == REG_RETVAL |
1133 | || REG_NOTE_KIND (*pnote) == REG_LIBCALL) | |
6764d250 BS |
1134 | *pnote = XEXP (*pnote, 1); |
1135 | else | |
1136 | pnote = &XEXP (*pnote, 1); | |
32131a9c | 1137 | } |
0304f787 | 1138 | |
2dfa9a87 MH |
1139 | #ifdef AUTO_INC_DEC |
1140 | add_auto_inc_notes (insn, PATTERN (insn)); | |
1141 | #endif | |
1142 | ||
0304f787 JL |
1143 | /* And simplify (subreg (reg)) if it appears as an operand. */ |
1144 | cleanup_subreg_operands (insn); | |
b60a8416 | 1145 | } |
32131a9c | 1146 | |
ab87f8c8 JL |
1147 | /* If we are doing stack checking, give a warning if this function's |
1148 | frame size is larger than we expect. */ | |
1149 | if (flag_stack_check && ! STACK_CHECK_BUILTIN) | |
1150 | { | |
1151 | HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; | |
05d10675 BS |
1152 | static int verbose_warned = 0; |
1153 | ||
ab87f8c8 JL |
1154 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1155 | if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i]) | |
1156 | size += UNITS_PER_WORD; | |
1157 | ||
1158 | if (size > STACK_CHECK_MAX_FRAME_SIZE) | |
05d10675 | 1159 | { |
ab87f8c8 JL |
1160 | warning ("frame size too large for reliable stack checking"); |
1161 | if (! verbose_warned) | |
1162 | { | |
1163 | warning ("try reducing the number of local variables"); | |
1164 | verbose_warned = 1; | |
1165 | } | |
1166 | } | |
1167 | } | |
1168 | ||
32131a9c | 1169 | /* Indicate that we no longer have known memory locations or constants. */ |
58d9f9d9 JL |
1170 | if (reg_equiv_constant) |
1171 | free (reg_equiv_constant); | |
32131a9c | 1172 | reg_equiv_constant = 0; |
58d9f9d9 JL |
1173 | if (reg_equiv_memory_loc) |
1174 | free (reg_equiv_memory_loc); | |
32131a9c | 1175 | reg_equiv_memory_loc = 0; |
5352b11a | 1176 | |
a68d4b75 BK |
1177 | if (real_known_ptr) |
1178 | free (real_known_ptr); | |
1179 | if (real_at_ptr) | |
1180 | free (real_at_ptr); | |
1181 | ||
56a65848 DB |
1182 | free (reg_equiv_mem); |
1183 | free (reg_equiv_init); | |
1184 | free (reg_equiv_address); | |
1185 | free (reg_max_ref_width); | |
03acd8f8 BS |
1186 | free (reg_old_renumber); |
1187 | free (pseudo_previous_regs); | |
1188 | free (pseudo_forbidden_regs); | |
56a65848 | 1189 | |
8b4f9969 JW |
1190 | CLEAR_HARD_REG_SET (used_spill_regs); |
1191 | for (i = 0; i < n_spills; i++) | |
1192 | SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]); | |
1193 | ||
7609e720 BS |
1194 | /* Free all the insn_chain structures at once. */ |
1195 | obstack_free (&reload_obstack, reload_startobj); | |
1196 | unused_insn_chains = 0; | |
1197 | ||
5352b11a | 1198 | return failure; |
32131a9c | 1199 | } |
1e5bd841 | 1200 | |
18a90182 BS |
1201 | /* Yet another special case. Unfortunately, reg-stack forces people to |
1202 | write incorrect clobbers in asm statements. These clobbers must not | |
1203 | cause the register to appear in bad_spill_regs, otherwise we'll call | |
1204 | fatal_insn later. We clear the corresponding regnos in the live | |
1205 | register sets to avoid this. | |
1206 | The whole thing is rather sick, I'm afraid. */ | |
1207 | static void | |
1208 | maybe_fix_stack_asms () | |
1209 | { | |
1210 | #ifdef STACK_REGS | |
392dccb7 | 1211 | const char *constraints[MAX_RECOG_OPERANDS]; |
18a90182 BS |
1212 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
1213 | struct insn_chain *chain; | |
1214 | ||
1215 | for (chain = reload_insn_chain; chain != 0; chain = chain->next) | |
1216 | { | |
1217 | int i, noperands; | |
1218 | HARD_REG_SET clobbered, allowed; | |
1219 | rtx pat; | |
1220 | ||
1221 | if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i' | |
1222 | || (noperands = asm_noperands (PATTERN (chain->insn))) < 0) | |
1223 | continue; | |
1224 | pat = PATTERN (chain->insn); | |
1225 | if (GET_CODE (pat) != PARALLEL) | |
1226 | continue; | |
1227 | ||
1228 | CLEAR_HARD_REG_SET (clobbered); | |
1229 | CLEAR_HARD_REG_SET (allowed); | |
1230 | ||
1231 | /* First, make a mask of all stack regs that are clobbered. */ | |
1232 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
1233 | { | |
1234 | rtx t = XVECEXP (pat, 0, i); | |
1235 | if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0))) | |
1236 | SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0))); | |
1237 | } | |
1238 | ||
1239 | /* Get the operand values and constraints out of the insn. */ | |
1ccbefce | 1240 | decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc, |
18a90182 BS |
1241 | constraints, operand_mode); |
1242 | ||
1243 | /* For every operand, see what registers are allowed. */ | |
1244 | for (i = 0; i < noperands; i++) | |
1245 | { | |
6b9c6f4f | 1246 | const char *p = constraints[i]; |
18a90182 BS |
1247 | /* For every alternative, we compute the class of registers allowed |
1248 | for reloading in CLS, and merge its contents into the reg set | |
1249 | ALLOWED. */ | |
1250 | int cls = (int) NO_REGS; | |
1251 | ||
1252 | for (;;) | |
1253 | { | |
1254 | char c = *p++; | |
1255 | ||
1256 | if (c == '\0' || c == ',' || c == '#') | |
1257 | { | |
1258 | /* End of one alternative - mark the regs in the current | |
1259 | class, and reset the class. */ | |
1260 | IOR_HARD_REG_SET (allowed, reg_class_contents[cls]); | |
1261 | cls = NO_REGS; | |
1262 | if (c == '#') | |
1263 | do { | |
1264 | c = *p++; | |
1265 | } while (c != '\0' && c != ','); | |
1266 | if (c == '\0') | |
1267 | break; | |
1268 | continue; | |
1269 | } | |
1270 | ||
1271 | switch (c) | |
1272 | { | |
1273 | case '=': case '+': case '*': case '%': case '?': case '!': | |
1274 | case '0': case '1': case '2': case '3': case '4': case 'm': | |
1275 | case '<': case '>': case 'V': case 'o': case '&': case 'E': | |
1276 | case 'F': case 's': case 'i': case 'n': case 'X': case 'I': | |
1277 | case 'J': case 'K': case 'L': case 'M': case 'N': case 'O': | |
1278 | case 'P': | |
1279 | #ifdef EXTRA_CONSTRAINT | |
1280 | case 'Q': case 'R': case 'S': case 'T': case 'U': | |
1281 | #endif | |
1282 | break; | |
1283 | ||
1284 | case 'p': | |
1285 | cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS]; | |
1286 | break; | |
1287 | ||
1288 | case 'g': | |
1289 | case 'r': | |
1290 | cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS]; | |
1291 | break; | |
1292 | ||
1293 | default: | |
1294 | cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)]; | |
05d10675 | 1295 | |
18a90182 BS |
1296 | } |
1297 | } | |
1298 | } | |
1299 | /* Those of the registers which are clobbered, but allowed by the | |
1300 | constraints, must be usable as reload registers. So clear them | |
1301 | out of the life information. */ | |
1302 | AND_HARD_REG_SET (allowed, clobbered); | |
1303 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1304 | if (TEST_HARD_REG_BIT (allowed, i)) | |
1305 | { | |
239a0f5b BS |
1306 | CLEAR_REGNO_REG_SET (&chain->live_throughout, i); |
1307 | CLEAR_REGNO_REG_SET (&chain->dead_or_set, i); | |
18a90182 BS |
1308 | } |
1309 | } | |
1310 | ||
1311 | #endif | |
1312 | } | |
03acd8f8 | 1313 | \f |
f5d8c9f4 BS |
1314 | /* Copy the global variables n_reloads and rld into the corresponding elts |
1315 | of CHAIN. */ | |
1316 | static void | |
1317 | copy_reloads (chain) | |
1318 | struct insn_chain *chain; | |
1319 | { | |
1320 | chain->n_reloads = n_reloads; | |
1321 | chain->rld | |
1322 | = (struct reload *) obstack_alloc (&reload_obstack, | |
1323 | n_reloads * sizeof (struct reload)); | |
1324 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); | |
1325 | reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0); | |
1326 | } | |
1327 | ||
03acd8f8 BS |
1328 | /* Walk the chain of insns, and determine for each whether it needs reloads |
1329 | and/or eliminations. Build the corresponding insns_need_reload list, and | |
1330 | set something_needs_elimination as appropriate. */ | |
1331 | static void | |
7609e720 | 1332 | calculate_needs_all_insns (global) |
1e5bd841 BS |
1333 | int global; |
1334 | { | |
7609e720 | 1335 | struct insn_chain **pprev_reload = &insns_need_reload; |
67e61fe7 | 1336 | struct insn_chain *chain; |
1e5bd841 | 1337 | |
03acd8f8 BS |
1338 | something_needs_elimination = 0; |
1339 | ||
f5d8c9f4 | 1340 | reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0); |
67e61fe7 | 1341 | for (chain = reload_insn_chain; chain != 0; chain = chain->next) |
1e5bd841 | 1342 | { |
67e61fe7 | 1343 | rtx insn = chain->insn; |
03acd8f8 | 1344 | |
f5d8c9f4 BS |
1345 | /* Clear out the shortcuts. */ |
1346 | chain->n_reloads = 0; | |
67e61fe7 BS |
1347 | chain->need_elim = 0; |
1348 | chain->need_reload = 0; | |
1349 | chain->need_operand_change = 0; | |
1e5bd841 | 1350 | |
03acd8f8 BS |
1351 | /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might |
1352 | include REG_LABEL), we need to see what effects this has on the | |
1353 | known offsets at labels. */ | |
1e5bd841 BS |
1354 | |
1355 | if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN | |
1356 | || (GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
1357 | && REG_NOTES (insn) != 0)) | |
1358 | set_label_offsets (insn, insn, 0); | |
1359 | ||
1360 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
1361 | { | |
1362 | rtx old_body = PATTERN (insn); | |
1363 | int old_code = INSN_CODE (insn); | |
1364 | rtx old_notes = REG_NOTES (insn); | |
1365 | int did_elimination = 0; | |
cb2afeb3 | 1366 | int operands_changed = 0; |
2b49ee39 R |
1367 | rtx set = single_set (insn); |
1368 | ||
1369 | /* Skip insns that only set an equivalence. */ | |
1370 | if (set && GET_CODE (SET_DEST (set)) == REG | |
1371 | && reg_renumber[REGNO (SET_DEST (set))] < 0 | |
1372 | && reg_equiv_constant[REGNO (SET_DEST (set))]) | |
67e61fe7 | 1373 | continue; |
1e5bd841 | 1374 | |
1e5bd841 | 1375 | /* If needed, eliminate any eliminable registers. */ |
2b49ee39 | 1376 | if (num_eliminable || num_eliminable_invariants) |
1e5bd841 BS |
1377 | did_elimination = eliminate_regs_in_insn (insn, 0); |
1378 | ||
1379 | /* Analyze the instruction. */ | |
cb2afeb3 R |
1380 | operands_changed = find_reloads (insn, 0, spill_indirect_levels, |
1381 | global, spill_reg_order); | |
1382 | ||
1383 | /* If a no-op set needs more than one reload, this is likely | |
1384 | to be something that needs input address reloads. We | |
1385 | can't get rid of this cleanly later, and it is of no use | |
1386 | anyway, so discard it now. | |
1387 | We only do this when expensive_optimizations is enabled, | |
1388 | since this complements reload inheritance / output | |
1389 | reload deletion, and it can make debugging harder. */ | |
1390 | if (flag_expensive_optimizations && n_reloads > 1) | |
1391 | { | |
1392 | rtx set = single_set (insn); | |
1393 | if (set | |
1394 | && SET_SRC (set) == SET_DEST (set) | |
1395 | && GET_CODE (SET_SRC (set)) == REG | |
1396 | && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) | |
1397 | { | |
1398 | PUT_CODE (insn, NOTE); | |
1399 | NOTE_SOURCE_FILE (insn) = 0; | |
1400 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
1401 | continue; | |
1402 | } | |
1403 | } | |
1404 | if (num_eliminable) | |
1405 | update_eliminable_offsets (); | |
1e5bd841 BS |
1406 | |
1407 | /* Remember for later shortcuts which insns had any reloads or | |
7609e720 BS |
1408 | register eliminations. */ |
1409 | chain->need_elim = did_elimination; | |
03acd8f8 BS |
1410 | chain->need_reload = n_reloads > 0; |
1411 | chain->need_operand_change = operands_changed; | |
1e5bd841 BS |
1412 | |
1413 | /* Discard any register replacements done. */ | |
1414 | if (did_elimination) | |
1415 | { | |
f5d8c9f4 | 1416 | obstack_free (&reload_obstack, reload_insn_firstobj); |
1e5bd841 BS |
1417 | PATTERN (insn) = old_body; |
1418 | INSN_CODE (insn) = old_code; | |
1419 | REG_NOTES (insn) = old_notes; | |
1420 | something_needs_elimination = 1; | |
1421 | } | |
1422 | ||
cb2afeb3 R |
1423 | something_needs_operands_changed |= operands_changed; |
1424 | ||
437a710d | 1425 | if (n_reloads != 0) |
7609e720 | 1426 | { |
f5d8c9f4 | 1427 | copy_reloads (chain); |
7609e720 BS |
1428 | *pprev_reload = chain; |
1429 | pprev_reload = &chain->next_need_reload; | |
7609e720 | 1430 | } |
1e5bd841 | 1431 | } |
1e5bd841 | 1432 | } |
7609e720 | 1433 | *pprev_reload = 0; |
1e5bd841 | 1434 | } |
f5d8c9f4 BS |
1435 | \f |
1436 | /* Comparison function for qsort to decide which of two reloads | |
1437 | should be handled first. *P1 and *P2 are the reload numbers. */ | |
1e5bd841 | 1438 | |
f5d8c9f4 BS |
1439 | static int |
1440 | reload_reg_class_lower (r1p, r2p) | |
1441 | const PTR r1p; | |
1442 | const PTR r2p; | |
1e5bd841 | 1443 | { |
272df862 | 1444 | register int r1 = *(const short *)r1p, r2 = *(const short *)r2p; |
f5d8c9f4 | 1445 | register int t; |
1e5bd841 | 1446 | |
f5d8c9f4 BS |
1447 | /* Consider required reloads before optional ones. */ |
1448 | t = rld[r1].optional - rld[r2].optional; | |
1449 | if (t != 0) | |
1450 | return t; | |
1e5bd841 | 1451 | |
f5d8c9f4 BS |
1452 | /* Count all solitary classes before non-solitary ones. */ |
1453 | t = ((reg_class_size[(int) rld[r2].class] == 1) | |
1454 | - (reg_class_size[(int) rld[r1].class] == 1)); | |
1455 | if (t != 0) | |
1456 | return t; | |
1e5bd841 | 1457 | |
f5d8c9f4 BS |
1458 | /* Aside from solitaires, consider all multi-reg groups first. */ |
1459 | t = rld[r2].nregs - rld[r1].nregs; | |
1460 | if (t != 0) | |
1461 | return t; | |
1e5bd841 | 1462 | |
f5d8c9f4 BS |
1463 | /* Consider reloads in order of increasing reg-class number. */ |
1464 | t = (int) rld[r1].class - (int) rld[r2].class; | |
1465 | if (t != 0) | |
1466 | return t; | |
1e5bd841 | 1467 | |
f5d8c9f4 BS |
1468 | /* If reloads are equally urgent, sort by reload number, |
1469 | so that the results of qsort leave nothing to chance. */ | |
1470 | return r1 - r2; | |
1471 | } | |
1472 | \f | |
1473 | /* The cost of spilling each hard reg. */ | |
1474 | static int spill_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1475 | |
f5d8c9f4 BS |
1476 | /* When spilling multiple hard registers, we use SPILL_COST for the first |
1477 | spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST | |
1478 | only the first hard reg for a multi-reg pseudo. */ | |
1479 | static int spill_add_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1480 | |
f5d8c9f4 BS |
1481 | /* Update the spill cost arrays, considering that pseudo REG is live. */ |
1482 | static void | |
1483 | count_pseudo (reg) | |
1484 | int reg; | |
1485 | { | |
1486 | int n_refs = REG_N_REFS (reg); | |
1487 | int r = reg_renumber[reg]; | |
1488 | int nregs; | |
1e5bd841 | 1489 | |
f5d8c9f4 BS |
1490 | if (REGNO_REG_SET_P (&pseudos_counted, reg) |
1491 | || REGNO_REG_SET_P (&spilled_pseudos, reg)) | |
1492 | return; | |
1e5bd841 | 1493 | |
f5d8c9f4 | 1494 | SET_REGNO_REG_SET (&pseudos_counted, reg); |
1e5bd841 | 1495 | |
f5d8c9f4 BS |
1496 | if (r < 0) |
1497 | abort (); | |
1498 | ||
1499 | spill_add_cost[r] += n_refs; | |
1e5bd841 | 1500 | |
f5d8c9f4 BS |
1501 | nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); |
1502 | while (nregs-- > 0) | |
1503 | spill_cost[r + nregs] += n_refs; | |
1504 | } | |
1e5bd841 | 1505 | |
f5d8c9f4 BS |
1506 | /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the |
1507 | contents of BAD_SPILL_REGS for the insn described by CHAIN. */ | |
1508 | static void | |
1509 | order_regs_for_reload (chain) | |
1510 | struct insn_chain *chain; | |
1511 | { | |
1512 | register int i, j; | |
1e5bd841 | 1513 | |
f5d8c9f4 | 1514 | COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global); |
1e5bd841 | 1515 | |
f5d8c9f4 BS |
1516 | memset (spill_cost, 0, sizeof spill_cost); |
1517 | memset (spill_add_cost, 0, sizeof spill_add_cost); | |
1e5bd841 | 1518 | |
f5d8c9f4 BS |
1519 | /* Count number of uses of each hard reg by pseudo regs allocated to it |
1520 | and then order them by decreasing use. */ | |
1e5bd841 | 1521 | |
f5d8c9f4 BS |
1522 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1523 | { | |
1524 | /* Test the various reasons why we can't use a register for | |
1525 | spilling in this insn. */ | |
1526 | if (fixed_regs[i] | |
239a0f5b BS |
1527 | || REGNO_REG_SET_P (&chain->live_throughout, i) |
1528 | || REGNO_REG_SET_P (&chain->dead_or_set, i)) | |
f5d8c9f4 | 1529 | SET_HARD_REG_BIT (bad_spill_regs, i); |
1e5bd841 | 1530 | } |
f5d8c9f4 BS |
1531 | /* Now find out which pseudos are allocated to it, and update |
1532 | hard_reg_n_uses. */ | |
1533 | CLEAR_REG_SET (&pseudos_counted); | |
1e5bd841 | 1534 | |
f5d8c9f4 | 1535 | EXECUTE_IF_SET_IN_REG_SET |
239a0f5b | 1536 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, |
f5d8c9f4 BS |
1537 | { |
1538 | count_pseudo (j); | |
1539 | }); | |
1540 | EXECUTE_IF_SET_IN_REG_SET | |
239a0f5b | 1541 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, |
f5d8c9f4 BS |
1542 | { |
1543 | count_pseudo (j); | |
1544 | }); | |
1545 | CLEAR_REG_SET (&pseudos_counted); | |
1e5bd841 | 1546 | } |
03acd8f8 | 1547 | \f |
f5d8c9f4 BS |
1548 | /* Vector of reload-numbers showing the order in which the reloads should |
1549 | be processed. */ | |
1550 | static short reload_order[MAX_RELOADS]; | |
1e5bd841 | 1551 | |
f5d8c9f4 BS |
1552 | /* This is used to keep track of the spill regs used in one insn. */ |
1553 | static HARD_REG_SET used_spill_regs_local; | |
03acd8f8 | 1554 | |
f5d8c9f4 BS |
1555 | /* We decided to spill hard register SPILLED, which has a size of |
1556 | SPILLED_NREGS. Determine how pseudo REG, which is live during the insn, | |
1557 | is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will | |
1558 | update SPILL_COST/SPILL_ADD_COST. */ | |
03acd8f8 | 1559 | static void |
f5d8c9f4 BS |
1560 | count_spilled_pseudo (spilled, spilled_nregs, reg) |
1561 | int spilled, spilled_nregs, reg; | |
1e5bd841 | 1562 | { |
f5d8c9f4 BS |
1563 | int r = reg_renumber[reg]; |
1564 | int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); | |
1e5bd841 | 1565 | |
f5d8c9f4 BS |
1566 | if (REGNO_REG_SET_P (&spilled_pseudos, reg) |
1567 | || spilled + spilled_nregs <= r || r + nregs <= spilled) | |
1568 | return; | |
1e5bd841 | 1569 | |
f5d8c9f4 | 1570 | SET_REGNO_REG_SET (&spilled_pseudos, reg); |
1e5bd841 | 1571 | |
f5d8c9f4 BS |
1572 | spill_add_cost[r] -= REG_N_REFS (reg); |
1573 | while (nregs-- > 0) | |
1574 | spill_cost[r + nregs] -= REG_N_REFS (reg); | |
1e5bd841 BS |
1575 | } |
1576 | ||
f5d8c9f4 | 1577 | /* Find reload register to use for reload number ORDER. */ |
03acd8f8 | 1578 | |
f5d8c9f4 BS |
1579 | static int |
1580 | find_reg (chain, order, dumpfile) | |
03acd8f8 | 1581 | struct insn_chain *chain; |
f5d8c9f4 | 1582 | int order; |
1e5bd841 BS |
1583 | FILE *dumpfile; |
1584 | { | |
f5d8c9f4 BS |
1585 | int rnum = reload_order[order]; |
1586 | struct reload *rl = rld + rnum; | |
1587 | int best_cost = INT_MAX; | |
1588 | int best_reg = -1; | |
1589 | int i, j; | |
1590 | HARD_REG_SET not_usable; | |
1591 | HARD_REG_SET used_by_other_reload; | |
1e5bd841 | 1592 | |
f5d8c9f4 BS |
1593 | COPY_HARD_REG_SET (not_usable, bad_spill_regs); |
1594 | IOR_HARD_REG_SET (not_usable, bad_spill_regs_global); | |
1595 | IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]); | |
1596 | ||
1597 | CLEAR_HARD_REG_SET (used_by_other_reload); | |
1598 | for (i = 0; i < order; i++) | |
1e5bd841 | 1599 | { |
f5d8c9f4 BS |
1600 | int other = reload_order[i]; |
1601 | if (rld[other].regno >= 0 && reloads_conflict (other, rnum)) | |
1602 | for (j = 0; j < rld[other].nregs; j++) | |
1603 | SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j); | |
1604 | } | |
1e5bd841 | 1605 | |
f5d8c9f4 BS |
1606 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1607 | { | |
1608 | int regno = i; | |
1609 | if (! TEST_HARD_REG_BIT (not_usable, regno) | |
1610 | && ! TEST_HARD_REG_BIT (used_by_other_reload, regno) | |
1611 | && HARD_REGNO_MODE_OK (regno, rl->mode)) | |
1e5bd841 | 1612 | { |
f5d8c9f4 BS |
1613 | int this_cost = spill_cost[regno]; |
1614 | int ok = 1; | |
1615 | int this_nregs = HARD_REGNO_NREGS (regno, rl->mode); | |
1e5bd841 | 1616 | |
f5d8c9f4 BS |
1617 | for (j = 1; j < this_nregs; j++) |
1618 | { | |
1619 | this_cost += spill_add_cost[regno + j]; | |
1620 | if ((TEST_HARD_REG_BIT (not_usable, regno + j)) | |
1621 | || TEST_HARD_REG_BIT (used_by_other_reload, regno + j)) | |
1622 | ok = 0; | |
1623 | } | |
1624 | if (! ok) | |
1625 | continue; | |
1626 | if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno) | |
1627 | this_cost--; | |
1628 | if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno) | |
1629 | this_cost--; | |
1630 | if (this_cost < best_cost | |
1631 | /* Among registers with equal cost, prefer caller-saved ones, or | |
1632 | use REG_ALLOC_ORDER if it is defined. */ | |
1633 | || (this_cost == best_cost | |
1634 | #ifdef REG_ALLOC_ORDER | |
1635 | && (inv_reg_alloc_order[regno] | |
1636 | < inv_reg_alloc_order[best_reg]) | |
1637 | #else | |
1638 | && call_used_regs[regno] | |
1639 | && ! call_used_regs[best_reg] | |
1640 | #endif | |
1641 | )) | |
1642 | { | |
1643 | best_reg = regno; | |
1644 | best_cost = this_cost; | |
1e5bd841 BS |
1645 | } |
1646 | } | |
1647 | } | |
f5d8c9f4 BS |
1648 | if (best_reg == -1) |
1649 | return 0; | |
1650 | if (dumpfile) | |
1651 | fprintf (dumpfile, "Using reg %d for reload %d\n", best_reg, rnum); | |
1652 | rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode); | |
1653 | rl->regno = best_reg; | |
1e5bd841 | 1654 | |
f5d8c9f4 | 1655 | EXECUTE_IF_SET_IN_REG_SET |
239a0f5b | 1656 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, |
f5d8c9f4 BS |
1657 | { |
1658 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1659 | }); | |
1660 | EXECUTE_IF_SET_IN_REG_SET | |
239a0f5b | 1661 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, |
f5d8c9f4 BS |
1662 | { |
1663 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1664 | }); | |
03acd8f8 | 1665 | |
f5d8c9f4 BS |
1666 | for (i = 0; i < rl->nregs; i++) |
1667 | { | |
1668 | if (spill_cost[best_reg + i] != 0 | |
1669 | || spill_add_cost[best_reg + i] != 0) | |
1670 | abort (); | |
1671 | SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i); | |
1672 | } | |
1673 | return 1; | |
03acd8f8 BS |
1674 | } |
1675 | ||
1676 | /* Find more reload regs to satisfy the remaining need of an insn, which | |
1677 | is given by CHAIN. | |
1e5bd841 BS |
1678 | Do it by ascending class number, since otherwise a reg |
1679 | might be spilled for a big class and might fail to count | |
f5d8c9f4 | 1680 | for a smaller class even though it belongs to that class. */ |
1e5bd841 | 1681 | |
03acd8f8 BS |
1682 | static void |
1683 | find_reload_regs (chain, dumpfile) | |
1684 | struct insn_chain *chain; | |
1e5bd841 BS |
1685 | FILE *dumpfile; |
1686 | { | |
f5d8c9f4 | 1687 | int i; |
1e5bd841 | 1688 | |
f5d8c9f4 BS |
1689 | /* In order to be certain of getting the registers we need, |
1690 | we must sort the reloads into order of increasing register class. | |
1691 | Then our grabbing of reload registers will parallel the process | |
1692 | that provided the reload registers. */ | |
1693 | for (i = 0; i < chain->n_reloads; i++) | |
1e5bd841 | 1694 | { |
f5d8c9f4 BS |
1695 | /* Show whether this reload already has a hard reg. */ |
1696 | if (chain->rld[i].reg_rtx) | |
1e5bd841 | 1697 | { |
f5d8c9f4 BS |
1698 | int regno = REGNO (chain->rld[i].reg_rtx); |
1699 | chain->rld[i].regno = regno; | |
1700 | chain->rld[i].nregs = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx)); | |
1e5bd841 | 1701 | } |
f5d8c9f4 BS |
1702 | else |
1703 | chain->rld[i].regno = -1; | |
1704 | reload_order[i] = i; | |
1705 | } | |
1e5bd841 | 1706 | |
f5d8c9f4 BS |
1707 | n_reloads = chain->n_reloads; |
1708 | memcpy (rld, chain->rld, n_reloads * sizeof (struct reload)); | |
1e5bd841 | 1709 | |
f5d8c9f4 | 1710 | CLEAR_HARD_REG_SET (used_spill_regs_local); |
03acd8f8 | 1711 | |
f5d8c9f4 BS |
1712 | if (dumpfile) |
1713 | fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn)); | |
1e5bd841 | 1714 | |
f5d8c9f4 | 1715 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); |
1e5bd841 | 1716 | |
f5d8c9f4 | 1717 | /* Compute the order of preference for hard registers to spill. */ |
1e5bd841 | 1718 | |
f5d8c9f4 | 1719 | order_regs_for_reload (chain); |
1e5bd841 | 1720 | |
f5d8c9f4 BS |
1721 | for (i = 0; i < n_reloads; i++) |
1722 | { | |
1723 | int r = reload_order[i]; | |
1e5bd841 | 1724 | |
f5d8c9f4 BS |
1725 | /* Ignore reloads that got marked inoperative. */ |
1726 | if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p) | |
1727 | && ! rld[r].optional | |
1728 | && rld[r].regno == -1) | |
1729 | if (! find_reg (chain, i, dumpfile)) | |
1730 | { | |
ecf3151a | 1731 | spill_failure (chain->insn, rld[r].class); |
f5d8c9f4 | 1732 | failure = 1; |
03acd8f8 | 1733 | return; |
f5d8c9f4 | 1734 | } |
1e5bd841 | 1735 | } |
05d10675 | 1736 | |
f5d8c9f4 BS |
1737 | COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local); |
1738 | IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local); | |
03acd8f8 | 1739 | |
f5d8c9f4 | 1740 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); |
1e5bd841 BS |
1741 | } |
1742 | ||
f5d8c9f4 BS |
1743 | static void |
1744 | select_reload_regs (dumpfile) | |
09dd1133 BS |
1745 | FILE *dumpfile; |
1746 | { | |
f5d8c9f4 | 1747 | struct insn_chain *chain; |
09dd1133 | 1748 | |
f5d8c9f4 BS |
1749 | /* Try to satisfy the needs for each insn. */ |
1750 | for (chain = insns_need_reload; chain != 0; | |
1751 | chain = chain->next_need_reload) | |
1752 | find_reload_regs (chain, dumpfile); | |
09dd1133 | 1753 | } |
32131a9c | 1754 | \f |
437a710d BS |
1755 | /* Delete all insns that were inserted by emit_caller_save_insns during |
1756 | this iteration. */ | |
1757 | static void | |
7609e720 | 1758 | delete_caller_save_insns () |
437a710d | 1759 | { |
7609e720 | 1760 | struct insn_chain *c = reload_insn_chain; |
437a710d | 1761 | |
7609e720 | 1762 | while (c != 0) |
437a710d | 1763 | { |
7609e720 | 1764 | while (c != 0 && c->is_caller_save_insn) |
437a710d | 1765 | { |
7609e720 BS |
1766 | struct insn_chain *next = c->next; |
1767 | rtx insn = c->insn; | |
1768 | ||
3b413743 RH |
1769 | if (insn == BLOCK_HEAD (c->block)) |
1770 | BLOCK_HEAD (c->block) = NEXT_INSN (insn); | |
1771 | if (insn == BLOCK_END (c->block)) | |
1772 | BLOCK_END (c->block) = PREV_INSN (insn); | |
7609e720 BS |
1773 | if (c == reload_insn_chain) |
1774 | reload_insn_chain = next; | |
1775 | ||
1776 | if (NEXT_INSN (insn) != 0) | |
1777 | PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); | |
1778 | if (PREV_INSN (insn) != 0) | |
1779 | NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); | |
1780 | ||
1781 | if (next) | |
1782 | next->prev = c->prev; | |
1783 | if (c->prev) | |
1784 | c->prev->next = next; | |
1785 | c->next = unused_insn_chains; | |
1786 | unused_insn_chains = c; | |
1787 | c = next; | |
437a710d | 1788 | } |
7609e720 BS |
1789 | if (c != 0) |
1790 | c = c->next; | |
437a710d BS |
1791 | } |
1792 | } | |
1793 | \f | |
5352b11a RS |
1794 | /* Handle the failure to find a register to spill. |
1795 | INSN should be one of the insns which needed this particular spill reg. */ | |
1796 | ||
1797 | static void | |
ecf3151a | 1798 | spill_failure (insn, class) |
5352b11a | 1799 | rtx insn; |
ecf3151a | 1800 | enum reg_class class; |
5352b11a | 1801 | { |
ecf3151a | 1802 | static const char *const reg_class_names[] = REG_CLASS_NAMES; |
5352b11a | 1803 | if (asm_noperands (PATTERN (insn)) >= 0) |
ecf3151a BS |
1804 | error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.", |
1805 | reg_class_names[class]); | |
5352b11a | 1806 | else |
ecf3151a BS |
1807 | { |
1808 | error ("Unable to find a register to spill in class `%s'.", | |
1809 | reg_class_names[class]); | |
1810 | fatal_insn ("This is the insn:", insn); | |
1811 | } | |
5352b11a | 1812 | } |
32131a9c RK |
1813 | \f |
1814 | /* Delete an unneeded INSN and any previous insns who sole purpose is loading | |
1815 | data that is dead in INSN. */ | |
1816 | ||
1817 | static void | |
1818 | delete_dead_insn (insn) | |
1819 | rtx insn; | |
1820 | { | |
1821 | rtx prev = prev_real_insn (insn); | |
1822 | rtx prev_dest; | |
1823 | ||
1824 | /* If the previous insn sets a register that dies in our insn, delete it | |
1825 | too. */ | |
1826 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
1827 | && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG) | |
1828 | && reg_mentioned_p (prev_dest, PATTERN (insn)) | |
b294ca38 R |
1829 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) |
1830 | && ! side_effects_p (SET_SRC (PATTERN (prev)))) | |
32131a9c RK |
1831 | delete_dead_insn (prev); |
1832 | ||
1833 | PUT_CODE (insn, NOTE); | |
1834 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
1835 | NOTE_SOURCE_FILE (insn) = 0; | |
1836 | } | |
1837 | ||
1838 | /* Modify the home of pseudo-reg I. | |
1839 | The new home is present in reg_renumber[I]. | |
1840 | ||
1841 | FROM_REG may be the hard reg that the pseudo-reg is being spilled from; | |
1842 | or it may be -1, meaning there is none or it is not relevant. | |
1843 | This is used so that all pseudos spilled from a given hard reg | |
1844 | can share one stack slot. */ | |
1845 | ||
1846 | static void | |
1847 | alter_reg (i, from_reg) | |
1848 | register int i; | |
1849 | int from_reg; | |
1850 | { | |
1851 | /* When outputting an inline function, this can happen | |
1852 | for a reg that isn't actually used. */ | |
1853 | if (regno_reg_rtx[i] == 0) | |
1854 | return; | |
1855 | ||
1856 | /* If the reg got changed to a MEM at rtl-generation time, | |
1857 | ignore it. */ | |
1858 | if (GET_CODE (regno_reg_rtx[i]) != REG) | |
1859 | return; | |
1860 | ||
1861 | /* Modify the reg-rtx to contain the new hard reg | |
1862 | number or else to contain its pseudo reg number. */ | |
1863 | REGNO (regno_reg_rtx[i]) | |
1864 | = reg_renumber[i] >= 0 ? reg_renumber[i] : i; | |
1865 | ||
1866 | /* If we have a pseudo that is needed but has no hard reg or equivalent, | |
1867 | allocate a stack slot for it. */ | |
1868 | ||
1869 | if (reg_renumber[i] < 0 | |
b1f21e0a | 1870 | && REG_N_REFS (i) > 0 |
32131a9c RK |
1871 | && reg_equiv_constant[i] == 0 |
1872 | && reg_equiv_memory_loc[i] == 0) | |
1873 | { | |
1874 | register rtx x; | |
1875 | int inherent_size = PSEUDO_REGNO_BYTES (i); | |
1876 | int total_size = MAX (inherent_size, reg_max_ref_width[i]); | |
1877 | int adjust = 0; | |
1878 | ||
1879 | /* Each pseudo reg has an inherent size which comes from its own mode, | |
1880 | and a total size which provides room for paradoxical subregs | |
1881 | which refer to the pseudo reg in wider modes. | |
1882 | ||
1883 | We can use a slot already allocated if it provides both | |
1884 | enough inherent space and enough total space. | |
1885 | Otherwise, we allocate a new slot, making sure that it has no less | |
1886 | inherent space, and no less total space, then the previous slot. */ | |
1887 | if (from_reg == -1) | |
1888 | { | |
1889 | /* No known place to spill from => no slot to reuse. */ | |
cabcf079 ILT |
1890 | x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, |
1891 | inherent_size == total_size ? 0 : -1); | |
f76b9db2 | 1892 | if (BYTES_BIG_ENDIAN) |
02db8dd0 RK |
1893 | /* Cancel the big-endian correction done in assign_stack_local. |
1894 | Get the address of the beginning of the slot. | |
1895 | This is so we can do a big-endian correction unconditionally | |
1896 | below. */ | |
1897 | adjust = inherent_size - total_size; | |
1898 | ||
1899 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]); | |
32131a9c RK |
1900 | } |
1901 | /* Reuse a stack slot if possible. */ | |
1902 | else if (spill_stack_slot[from_reg] != 0 | |
1903 | && spill_stack_slot_width[from_reg] >= total_size | |
1904 | && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
1905 | >= inherent_size)) | |
1906 | x = spill_stack_slot[from_reg]; | |
1907 | /* Allocate a bigger slot. */ | |
1908 | else | |
1909 | { | |
1910 | /* Compute maximum size needed, both for inherent size | |
1911 | and for total size. */ | |
1912 | enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); | |
4f2d3674 | 1913 | rtx stack_slot; |
32131a9c RK |
1914 | if (spill_stack_slot[from_reg]) |
1915 | { | |
1916 | if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
1917 | > inherent_size) | |
1918 | mode = GET_MODE (spill_stack_slot[from_reg]); | |
1919 | if (spill_stack_slot_width[from_reg] > total_size) | |
1920 | total_size = spill_stack_slot_width[from_reg]; | |
1921 | } | |
1922 | /* Make a slot with that size. */ | |
cabcf079 ILT |
1923 | x = assign_stack_local (mode, total_size, |
1924 | inherent_size == total_size ? 0 : -1); | |
4f2d3674 | 1925 | stack_slot = x; |
f76b9db2 ILT |
1926 | if (BYTES_BIG_ENDIAN) |
1927 | { | |
1928 | /* Cancel the big-endian correction done in assign_stack_local. | |
1929 | Get the address of the beginning of the slot. | |
1930 | This is so we can do a big-endian correction unconditionally | |
1931 | below. */ | |
1932 | adjust = GET_MODE_SIZE (mode) - total_size; | |
4f2d3674 | 1933 | if (adjust) |
38a448ca RH |
1934 | stack_slot = gen_rtx_MEM (mode_for_size (total_size |
1935 | * BITS_PER_UNIT, | |
1936 | MODE_INT, 1), | |
05d10675 | 1937 | plus_constant (XEXP (x, 0), adjust)); |
f76b9db2 | 1938 | } |
4f2d3674 | 1939 | spill_stack_slot[from_reg] = stack_slot; |
32131a9c RK |
1940 | spill_stack_slot_width[from_reg] = total_size; |
1941 | } | |
1942 | ||
32131a9c RK |
1943 | /* On a big endian machine, the "address" of the slot |
1944 | is the address of the low part that fits its inherent mode. */ | |
f76b9db2 | 1945 | if (BYTES_BIG_ENDIAN && inherent_size < total_size) |
32131a9c | 1946 | adjust += (total_size - inherent_size); |
32131a9c RK |
1947 | |
1948 | /* If we have any adjustment to make, or if the stack slot is the | |
1949 | wrong mode, make a new stack slot. */ | |
1950 | if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i])) | |
1951 | { | |
38a448ca | 1952 | x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]), |
05d10675 | 1953 | plus_constant (XEXP (x, 0), adjust)); |
9ec36da5 JL |
1954 | |
1955 | /* If this was shared among registers, must ensure we never | |
1956 | set it readonly since that can cause scheduling | |
1957 | problems. Note we would only have in this adjustment | |
1958 | case in any event, since the code above doesn't set it. */ | |
1959 | ||
1960 | if (from_reg == -1) | |
1961 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]); | |
32131a9c RK |
1962 | } |
1963 | ||
1964 | /* Save the stack slot for later. */ | |
1965 | reg_equiv_memory_loc[i] = x; | |
1966 | } | |
1967 | } | |
1968 | ||
1969 | /* Mark the slots in regs_ever_live for the hard regs | |
1970 | used by pseudo-reg number REGNO. */ | |
1971 | ||
1972 | void | |
1973 | mark_home_live (regno) | |
1974 | int regno; | |
1975 | { | |
1976 | register int i, lim; | |
1977 | i = reg_renumber[regno]; | |
1978 | if (i < 0) | |
1979 | return; | |
1980 | lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno)); | |
1981 | while (i < lim) | |
1982 | regs_ever_live[i++] = 1; | |
1983 | } | |
1984 | \f | |
1985 | /* This function handles the tracking of elimination offsets around branches. | |
1986 | ||
1987 | X is a piece of RTL being scanned. | |
1988 | ||
1989 | INSN is the insn that it came from, if any. | |
1990 | ||
1991 | INITIAL_P is non-zero if we are to set the offset to be the initial | |
1992 | offset and zero if we are setting the offset of the label to be the | |
1993 | current offset. */ | |
1994 | ||
1995 | static void | |
1996 | set_label_offsets (x, insn, initial_p) | |
1997 | rtx x; | |
1998 | rtx insn; | |
1999 | int initial_p; | |
2000 | { | |
2001 | enum rtx_code code = GET_CODE (x); | |
2002 | rtx tem; | |
e51712db | 2003 | unsigned int i; |
32131a9c RK |
2004 | struct elim_table *p; |
2005 | ||
2006 | switch (code) | |
2007 | { | |
2008 | case LABEL_REF: | |
8be386d9 RS |
2009 | if (LABEL_REF_NONLOCAL_P (x)) |
2010 | return; | |
2011 | ||
32131a9c RK |
2012 | x = XEXP (x, 0); |
2013 | ||
0f41302f | 2014 | /* ... fall through ... */ |
32131a9c RK |
2015 | |
2016 | case CODE_LABEL: | |
2017 | /* If we know nothing about this label, set the desired offsets. Note | |
2018 | that this sets the offset at a label to be the offset before a label | |
2019 | if we don't know anything about the label. This is not correct for | |
2020 | the label after a BARRIER, but is the best guess we can make. If | |
2021 | we guessed wrong, we will suppress an elimination that might have | |
2022 | been possible had we been able to guess correctly. */ | |
2023 | ||
2024 | if (! offsets_known_at[CODE_LABEL_NUMBER (x)]) | |
2025 | { | |
2026 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
2027 | offsets_at[CODE_LABEL_NUMBER (x)][i] | |
2028 | = (initial_p ? reg_eliminate[i].initial_offset | |
2029 | : reg_eliminate[i].offset); | |
2030 | offsets_known_at[CODE_LABEL_NUMBER (x)] = 1; | |
2031 | } | |
2032 | ||
2033 | /* Otherwise, if this is the definition of a label and it is | |
d45cf215 | 2034 | preceded by a BARRIER, set our offsets to the known offset of |
32131a9c RK |
2035 | that label. */ |
2036 | ||
2037 | else if (x == insn | |
2038 | && (tem = prev_nonnote_insn (insn)) != 0 | |
2039 | && GET_CODE (tem) == BARRIER) | |
1f3b1e1a | 2040 | set_offsets_for_label (insn); |
32131a9c RK |
2041 | else |
2042 | /* If neither of the above cases is true, compare each offset | |
2043 | with those previously recorded and suppress any eliminations | |
2044 | where the offsets disagree. */ | |
a8fdc208 | 2045 | |
32131a9c RK |
2046 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) |
2047 | if (offsets_at[CODE_LABEL_NUMBER (x)][i] | |
2048 | != (initial_p ? reg_eliminate[i].initial_offset | |
2049 | : reg_eliminate[i].offset)) | |
2050 | reg_eliminate[i].can_eliminate = 0; | |
2051 | ||
2052 | return; | |
2053 | ||
2054 | case JUMP_INSN: | |
2055 | set_label_offsets (PATTERN (insn), insn, initial_p); | |
2056 | ||
0f41302f | 2057 | /* ... fall through ... */ |
32131a9c RK |
2058 | |
2059 | case INSN: | |
2060 | case CALL_INSN: | |
2061 | /* Any labels mentioned in REG_LABEL notes can be branched to indirectly | |
2062 | and hence must have all eliminations at their initial offsets. */ | |
2063 | for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) | |
2064 | if (REG_NOTE_KIND (tem) == REG_LABEL) | |
2065 | set_label_offsets (XEXP (tem, 0), insn, 1); | |
2066 | return; | |
2067 | ||
2068 | case ADDR_VEC: | |
2069 | case ADDR_DIFF_VEC: | |
2070 | /* Each of the labels in the address vector must be at their initial | |
38e01259 | 2071 | offsets. We want the first field for ADDR_VEC and the second |
32131a9c RK |
2072 | field for ADDR_DIFF_VEC. */ |
2073 | ||
e51712db | 2074 | for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++) |
32131a9c RK |
2075 | set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), |
2076 | insn, initial_p); | |
2077 | return; | |
2078 | ||
2079 | case SET: | |
2080 | /* We only care about setting PC. If the source is not RETURN, | |
2081 | IF_THEN_ELSE, or a label, disable any eliminations not at | |
2082 | their initial offsets. Similarly if any arm of the IF_THEN_ELSE | |
2083 | isn't one of those possibilities. For branches to a label, | |
2084 | call ourselves recursively. | |
2085 | ||
2086 | Note that this can disable elimination unnecessarily when we have | |
2087 | a non-local goto since it will look like a non-constant jump to | |
2088 | someplace in the current function. This isn't a significant | |
2089 | problem since such jumps will normally be when all elimination | |
2090 | pairs are back to their initial offsets. */ | |
2091 | ||
2092 | if (SET_DEST (x) != pc_rtx) | |
2093 | return; | |
2094 | ||
2095 | switch (GET_CODE (SET_SRC (x))) | |
2096 | { | |
2097 | case PC: | |
2098 | case RETURN: | |
2099 | return; | |
2100 | ||
2101 | case LABEL_REF: | |
2102 | set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p); | |
2103 | return; | |
2104 | ||
2105 | case IF_THEN_ELSE: | |
2106 | tem = XEXP (SET_SRC (x), 1); | |
2107 | if (GET_CODE (tem) == LABEL_REF) | |
2108 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2109 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2110 | break; | |
2111 | ||
2112 | tem = XEXP (SET_SRC (x), 2); | |
2113 | if (GET_CODE (tem) == LABEL_REF) | |
2114 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2115 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2116 | break; | |
2117 | return; | |
e9a25f70 JL |
2118 | |
2119 | default: | |
2120 | break; | |
32131a9c RK |
2121 | } |
2122 | ||
2123 | /* If we reach here, all eliminations must be at their initial | |
2124 | offset because we are doing a jump to a variable address. */ | |
2125 | for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) | |
2126 | if (p->offset != p->initial_offset) | |
2127 | p->can_eliminate = 0; | |
e9a25f70 | 2128 | break; |
05d10675 | 2129 | |
e9a25f70 JL |
2130 | default: |
2131 | break; | |
32131a9c RK |
2132 | } |
2133 | } | |
2134 | \f | |
a8fdc208 | 2135 | /* Scan X and replace any eliminable registers (such as fp) with a |
32131a9c RK |
2136 | replacement (such as sp), plus an offset. |
2137 | ||
2138 | MEM_MODE is the mode of an enclosing MEM. We need this to know how | |
2139 | much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a | |
2140 | MEM, we are allowed to replace a sum of a register and the constant zero | |
2141 | with the register, which we cannot do outside a MEM. In addition, we need | |
2142 | to record the fact that a register is referenced outside a MEM. | |
2143 | ||
ff32812a | 2144 | If INSN is an insn, it is the insn containing X. If we replace a REG |
32131a9c RK |
2145 | in a SET_DEST with an equivalent MEM and INSN is non-zero, write a |
2146 | CLOBBER of the pseudo after INSN so find_equiv_regs will know that | |
38e01259 | 2147 | the REG is being modified. |
32131a9c | 2148 | |
ff32812a RS |
2149 | Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST). |
2150 | That's used when we eliminate in expressions stored in notes. | |
2151 | This means, do not set ref_outside_mem even if the reference | |
2152 | is outside of MEMs. | |
2153 | ||
32131a9c RK |
2154 | REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had |
2155 | replacements done assuming all offsets are at their initial values. If | |
2156 | they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we | |
2157 | encounter, return the actual location so that find_reloads will do | |
2158 | the proper thing. */ | |
2159 | ||
2160 | rtx | |
1914f5da | 2161 | eliminate_regs (x, mem_mode, insn) |
32131a9c RK |
2162 | rtx x; |
2163 | enum machine_mode mem_mode; | |
2164 | rtx insn; | |
2165 | { | |
2166 | enum rtx_code code = GET_CODE (x); | |
2167 | struct elim_table *ep; | |
2168 | int regno; | |
2169 | rtx new; | |
2170 | int i, j; | |
6f7d635c | 2171 | const char *fmt; |
32131a9c RK |
2172 | int copied = 0; |
2173 | ||
d6633f01 NS |
2174 | if (! current_function_decl) |
2175 | return x; | |
9969bb2c | 2176 | |
32131a9c RK |
2177 | switch (code) |
2178 | { | |
2179 | case CONST_INT: | |
2180 | case CONST_DOUBLE: | |
2181 | case CONST: | |
2182 | case SYMBOL_REF: | |
2183 | case CODE_LABEL: | |
2184 | case PC: | |
2185 | case CC0: | |
2186 | case ASM_INPUT: | |
2187 | case ADDR_VEC: | |
2188 | case ADDR_DIFF_VEC: | |
2189 | case RETURN: | |
2190 | return x; | |
2191 | ||
e9a25f70 JL |
2192 | case ADDRESSOF: |
2193 | /* This is only for the benefit of the debugging backends, which call | |
2194 | eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are | |
2195 | removed after CSE. */ | |
1914f5da | 2196 | new = eliminate_regs (XEXP (x, 0), 0, insn); |
e9a25f70 JL |
2197 | if (GET_CODE (new) == MEM) |
2198 | return XEXP (new, 0); | |
2199 | return x; | |
2200 | ||
32131a9c RK |
2201 | case REG: |
2202 | regno = REGNO (x); | |
2203 | ||
2204 | /* First handle the case where we encounter a bare register that | |
2205 | is eliminable. Replace it with a PLUS. */ | |
2206 | if (regno < FIRST_PSEUDO_REGISTER) | |
2207 | { | |
2208 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2209 | ep++) | |
2210 | if (ep->from_rtx == x && ep->can_eliminate) | |
dfac187e | 2211 | return plus_constant (ep->to_rtx, ep->previous_offset); |
32131a9c RK |
2212 | |
2213 | } | |
2b49ee39 R |
2214 | else if (reg_renumber[regno] < 0 && reg_equiv_constant |
2215 | && reg_equiv_constant[regno] | |
2216 | && ! CONSTANT_P (reg_equiv_constant[regno])) | |
2217 | return eliminate_regs (copy_rtx (reg_equiv_constant[regno]), | |
2218 | mem_mode, insn); | |
32131a9c RK |
2219 | return x; |
2220 | ||
c5c76735 JL |
2221 | /* You might think handling MINUS in a manner similar to PLUS is a |
2222 | good idea. It is not. It has been tried multiple times and every | |
2223 | time the change has had to have been reverted. | |
2224 | ||
2225 | Other parts of reload know a PLUS is special (gen_reload for example) | |
2226 | and require special code to handle code a reloaded PLUS operand. | |
2227 | ||
2228 | Also consider backends where the flags register is clobbered by a | |
2229 | MINUS, but we can emit a PLUS that does not clobber flags (ia32, | |
2230 | lea instruction comes to mind). If we try to reload a MINUS, we | |
2231 | may kill the flags register that was holding a useful value. | |
2232 | ||
2233 | So, please before trying to handle MINUS, consider reload as a | |
2234 | whole instead of this little section as well as the backend issues. */ | |
32131a9c RK |
2235 | case PLUS: |
2236 | /* If this is the sum of an eliminable register and a constant, rework | |
2237 | the sum. */ | |
2238 | if (GET_CODE (XEXP (x, 0)) == REG | |
2239 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2240 | && CONSTANT_P (XEXP (x, 1))) | |
2241 | { | |
2242 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2243 | ep++) | |
2244 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2245 | { | |
32131a9c RK |
2246 | /* The only time we want to replace a PLUS with a REG (this |
2247 | occurs when the constant operand of the PLUS is the negative | |
2248 | of the offset) is when we are inside a MEM. We won't want | |
2249 | to do so at other times because that would change the | |
2250 | structure of the insn in a way that reload can't handle. | |
2251 | We special-case the commonest situation in | |
2252 | eliminate_regs_in_insn, so just replace a PLUS with a | |
2253 | PLUS here, unless inside a MEM. */ | |
a23b64d5 | 2254 | if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT |
32131a9c RK |
2255 | && INTVAL (XEXP (x, 1)) == - ep->previous_offset) |
2256 | return ep->to_rtx; | |
2257 | else | |
38a448ca RH |
2258 | return gen_rtx_PLUS (Pmode, ep->to_rtx, |
2259 | plus_constant (XEXP (x, 1), | |
2260 | ep->previous_offset)); | |
32131a9c RK |
2261 | } |
2262 | ||
2263 | /* If the register is not eliminable, we are done since the other | |
2264 | operand is a constant. */ | |
2265 | return x; | |
2266 | } | |
2267 | ||
2268 | /* If this is part of an address, we want to bring any constant to the | |
2269 | outermost PLUS. We will do this by doing register replacement in | |
2270 | our operands and seeing if a constant shows up in one of them. | |
2271 | ||
dfac187e BS |
2272 | Note that there is no risk of modifying the structure of the insn, |
2273 | since we only get called for its operands, thus we are either | |
2274 | modifying the address inside a MEM, or something like an address | |
2275 | operand of a load-address insn. */ | |
32131a9c RK |
2276 | |
2277 | { | |
1914f5da RH |
2278 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
2279 | rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn); | |
32131a9c RK |
2280 | |
2281 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
2282 | { | |
2283 | /* If one side is a PLUS and the other side is a pseudo that | |
a8fdc208 | 2284 | didn't get a hard register but has a reg_equiv_constant, |
32131a9c RK |
2285 | we must replace the constant here since it may no longer |
2286 | be in the position of any operand. */ | |
2287 | if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG | |
2288 | && REGNO (new1) >= FIRST_PSEUDO_REGISTER | |
2289 | && reg_renumber[REGNO (new1)] < 0 | |
2290 | && reg_equiv_constant != 0 | |
2291 | && reg_equiv_constant[REGNO (new1)] != 0) | |
2292 | new1 = reg_equiv_constant[REGNO (new1)]; | |
2293 | else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG | |
2294 | && REGNO (new0) >= FIRST_PSEUDO_REGISTER | |
2295 | && reg_renumber[REGNO (new0)] < 0 | |
2296 | && reg_equiv_constant[REGNO (new0)] != 0) | |
2297 | new0 = reg_equiv_constant[REGNO (new0)]; | |
2298 | ||
2299 | new = form_sum (new0, new1); | |
2300 | ||
2301 | /* As above, if we are not inside a MEM we do not want to | |
2302 | turn a PLUS into something else. We might try to do so here | |
2303 | for an addition of 0 if we aren't optimizing. */ | |
2304 | if (! mem_mode && GET_CODE (new) != PLUS) | |
38a448ca | 2305 | return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx); |
32131a9c RK |
2306 | else |
2307 | return new; | |
2308 | } | |
2309 | } | |
2310 | return x; | |
2311 | ||
981c7390 | 2312 | case MULT: |
05d10675 | 2313 | /* If this is the product of an eliminable register and a |
981c7390 RK |
2314 | constant, apply the distribute law and move the constant out |
2315 | so that we have (plus (mult ..) ..). This is needed in order | |
9faa82d8 | 2316 | to keep load-address insns valid. This case is pathological. |
981c7390 RK |
2317 | We ignore the possibility of overflow here. */ |
2318 | if (GET_CODE (XEXP (x, 0)) == REG | |
2319 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2320 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2321 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2322 | ep++) | |
2323 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2324 | { | |
2325 | if (! mem_mode | |
2326 | /* Refs inside notes don't count for this purpose. */ | |
2327 | && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST | |
2328 | || GET_CODE (insn) == INSN_LIST))) | |
2329 | ep->ref_outside_mem = 1; | |
2330 | ||
2331 | return | |
38a448ca | 2332 | plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)), |
981c7390 RK |
2333 | ep->previous_offset * INTVAL (XEXP (x, 1))); |
2334 | } | |
32131a9c | 2335 | |
0f41302f | 2336 | /* ... fall through ... */ |
32131a9c | 2337 | |
32131a9c RK |
2338 | case CALL: |
2339 | case COMPARE: | |
c5c76735 | 2340 | /* See comments before PLUS about handling MINUS. */ |
930aeef3 | 2341 | case MINUS: |
32131a9c RK |
2342 | case DIV: case UDIV: |
2343 | case MOD: case UMOD: | |
2344 | case AND: case IOR: case XOR: | |
45620ed4 RK |
2345 | case ROTATERT: case ROTATE: |
2346 | case ASHIFTRT: case LSHIFTRT: case ASHIFT: | |
32131a9c RK |
2347 | case NE: case EQ: |
2348 | case GE: case GT: case GEU: case GTU: | |
2349 | case LE: case LT: case LEU: case LTU: | |
2350 | { | |
1914f5da | 2351 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
fb3821f7 | 2352 | rtx new1 |
1914f5da | 2353 | = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0; |
32131a9c RK |
2354 | |
2355 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
38a448ca | 2356 | return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); |
32131a9c RK |
2357 | } |
2358 | return x; | |
2359 | ||
981c7390 RK |
2360 | case EXPR_LIST: |
2361 | /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ | |
2362 | if (XEXP (x, 0)) | |
2363 | { | |
1914f5da | 2364 | new = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
981c7390 | 2365 | if (new != XEXP (x, 0)) |
13bb79d4 R |
2366 | { |
2367 | /* If this is a REG_DEAD note, it is not valid anymore. | |
2368 | Using the eliminated version could result in creating a | |
2369 | REG_DEAD note for the stack or frame pointer. */ | |
2370 | if (GET_MODE (x) == REG_DEAD) | |
2371 | return (XEXP (x, 1) | |
2372 | ? eliminate_regs (XEXP (x, 1), mem_mode, insn) | |
2373 | : NULL_RTX); | |
2374 | ||
2375 | x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1)); | |
2376 | } | |
981c7390 RK |
2377 | } |
2378 | ||
0f41302f | 2379 | /* ... fall through ... */ |
981c7390 RK |
2380 | |
2381 | case INSN_LIST: | |
2382 | /* Now do eliminations in the rest of the chain. If this was | |
2383 | an EXPR_LIST, this might result in allocating more memory than is | |
2384 | strictly needed, but it simplifies the code. */ | |
2385 | if (XEXP (x, 1)) | |
2386 | { | |
1914f5da | 2387 | new = eliminate_regs (XEXP (x, 1), mem_mode, insn); |
981c7390 | 2388 | if (new != XEXP (x, 1)) |
38a448ca | 2389 | return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new); |
981c7390 RK |
2390 | } |
2391 | return x; | |
2392 | ||
32131a9c RK |
2393 | case PRE_INC: |
2394 | case POST_INC: | |
2395 | case PRE_DEC: | |
2396 | case POST_DEC: | |
32131a9c RK |
2397 | case STRICT_LOW_PART: |
2398 | case NEG: case NOT: | |
2399 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2400 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2401 | case FLOAT: case FIX: | |
2402 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2403 | case ABS: | |
2404 | case SQRT: | |
2405 | case FFS: | |
1914f5da | 2406 | new = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
32131a9c | 2407 | if (new != XEXP (x, 0)) |
38a448ca | 2408 | return gen_rtx_fmt_e (code, GET_MODE (x), new); |
32131a9c RK |
2409 | return x; |
2410 | ||
2411 | case SUBREG: | |
2412 | /* Similar to above processing, but preserve SUBREG_WORD. | |
2413 | Convert (subreg (mem)) to (mem) if not paradoxical. | |
2414 | Also, if we have a non-paradoxical (subreg (pseudo)) and the | |
2415 | pseudo didn't get a hard reg, we must replace this with the | |
2416 | eliminated version of the memory location because push_reloads | |
2417 | may do the replacement in certain circumstances. */ | |
2418 | if (GET_CODE (SUBREG_REG (x)) == REG | |
2419 | && (GET_MODE_SIZE (GET_MODE (x)) | |
2420 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2421 | && reg_equiv_memory_loc != 0 | |
2422 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2423 | { | |
cb2afeb3 | 2424 | new = SUBREG_REG (x); |
32131a9c RK |
2425 | } |
2426 | else | |
1914f5da | 2427 | new = eliminate_regs (SUBREG_REG (x), mem_mode, insn); |
32131a9c RK |
2428 | |
2429 | if (new != XEXP (x, 0)) | |
2430 | { | |
29ae5012 RK |
2431 | int x_size = GET_MODE_SIZE (GET_MODE (x)); |
2432 | int new_size = GET_MODE_SIZE (GET_MODE (new)); | |
2433 | ||
1914f5da | 2434 | if (GET_CODE (new) == MEM |
6d49a073 | 2435 | && ((x_size < new_size |
1914f5da | 2436 | #ifdef WORD_REGISTER_OPERATIONS |
6d49a073 JW |
2437 | /* On these machines, combine can create rtl of the form |
2438 | (set (subreg:m1 (reg:m2 R) 0) ...) | |
05d10675 | 2439 | where m1 < m2, and expects something interesting to |
6d49a073 JW |
2440 | happen to the entire word. Moreover, it will use the |
2441 | (reg:m2 R) later, expecting all bits to be preserved. | |
05d10675 | 2442 | So if the number of words is the same, preserve the |
6d49a073 JW |
2443 | subreg so that push_reloads can see it. */ |
2444 | && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD) | |
1914f5da | 2445 | #endif |
6d49a073 JW |
2446 | ) |
2447 | || (x_size == new_size)) | |
1914f5da | 2448 | ) |
32131a9c RK |
2449 | { |
2450 | int offset = SUBREG_WORD (x) * UNITS_PER_WORD; | |
2451 | enum machine_mode mode = GET_MODE (x); | |
2452 | ||
f76b9db2 ILT |
2453 | if (BYTES_BIG_ENDIAN) |
2454 | offset += (MIN (UNITS_PER_WORD, | |
2455 | GET_MODE_SIZE (GET_MODE (new))) | |
2456 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))); | |
32131a9c RK |
2457 | |
2458 | PUT_MODE (new, mode); | |
2459 | XEXP (new, 0) = plus_constant (XEXP (new, 0), offset); | |
2460 | return new; | |
2461 | } | |
2462 | else | |
38a448ca | 2463 | return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x)); |
32131a9c RK |
2464 | } |
2465 | ||
2466 | return x; | |
2467 | ||
32131a9c | 2468 | case MEM: |
e9a25f70 JL |
2469 | /* This is only for the benefit of the debugging backends, which call |
2470 | eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are | |
2471 | removed after CSE. */ | |
2472 | if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) | |
1914f5da | 2473 | return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn); |
e9a25f70 | 2474 | |
32131a9c RK |
2475 | /* Our only special processing is to pass the mode of the MEM to our |
2476 | recursive call and copy the flags. While we are here, handle this | |
2477 | case more efficiently. */ | |
1914f5da | 2478 | new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn); |
32131a9c RK |
2479 | if (new != XEXP (x, 0)) |
2480 | { | |
38a448ca | 2481 | new = gen_rtx_MEM (GET_MODE (x), new); |
32131a9c RK |
2482 | new->volatil = x->volatil; |
2483 | new->unchanging = x->unchanging; | |
2484 | new->in_struct = x->in_struct; | |
2485 | return new; | |
2486 | } | |
2487 | else | |
2488 | return x; | |
05d10675 | 2489 | |
dfac187e BS |
2490 | case USE: |
2491 | case CLOBBER: | |
2492 | case ASM_OPERANDS: | |
2493 | case SET: | |
2494 | abort (); | |
2495 | ||
e9a25f70 JL |
2496 | default: |
2497 | break; | |
32131a9c RK |
2498 | } |
2499 | ||
2500 | /* Process each of our operands recursively. If any have changed, make a | |
2501 | copy of the rtx. */ | |
2502 | fmt = GET_RTX_FORMAT (code); | |
2503 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2504 | { | |
2505 | if (*fmt == 'e') | |
2506 | { | |
1914f5da | 2507 | new = eliminate_regs (XEXP (x, i), mem_mode, insn); |
32131a9c RK |
2508 | if (new != XEXP (x, i) && ! copied) |
2509 | { | |
2510 | rtx new_x = rtx_alloc (code); | |
4c9a05bc RK |
2511 | bcopy ((char *) x, (char *) new_x, |
2512 | (sizeof (*new_x) - sizeof (new_x->fld) | |
2513 | + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code))); | |
32131a9c RK |
2514 | x = new_x; |
2515 | copied = 1; | |
2516 | } | |
2517 | XEXP (x, i) = new; | |
2518 | } | |
2519 | else if (*fmt == 'E') | |
2520 | { | |
2521 | int copied_vec = 0; | |
2522 | for (j = 0; j < XVECLEN (x, i); j++) | |
2523 | { | |
1914f5da | 2524 | new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn); |
32131a9c RK |
2525 | if (new != XVECEXP (x, i, j) && ! copied_vec) |
2526 | { | |
8f985ec4 ZW |
2527 | rtvec new_v = gen_rtvec_v (XVECLEN (x, i), |
2528 | XVEC (x, i)->elem); | |
32131a9c RK |
2529 | if (! copied) |
2530 | { | |
2531 | rtx new_x = rtx_alloc (code); | |
4c9a05bc RK |
2532 | bcopy ((char *) x, (char *) new_x, |
2533 | (sizeof (*new_x) - sizeof (new_x->fld) | |
2534 | + (sizeof (new_x->fld[0]) | |
2535 | * GET_RTX_LENGTH (code)))); | |
32131a9c RK |
2536 | x = new_x; |
2537 | copied = 1; | |
2538 | } | |
2539 | XVEC (x, i) = new_v; | |
2540 | copied_vec = 1; | |
2541 | } | |
2542 | XVECEXP (x, i, j) = new; | |
2543 | } | |
2544 | } | |
2545 | } | |
2546 | ||
2547 | return x; | |
2548 | } | |
dfac187e BS |
2549 | |
2550 | /* Scan rtx X for modifications of elimination target registers. Update | |
2551 | the table of eliminables to reflect the changed state. MEM_MODE is | |
2552 | the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */ | |
2553 | ||
2554 | static void | |
2555 | elimination_effects (x, mem_mode) | |
2556 | rtx x; | |
2557 | enum machine_mode mem_mode; | |
2558 | ||
2559 | { | |
2560 | enum rtx_code code = GET_CODE (x); | |
2561 | struct elim_table *ep; | |
2562 | int regno; | |
2563 | int i, j; | |
2564 | const char *fmt; | |
2565 | ||
2566 | switch (code) | |
2567 | { | |
2568 | case CONST_INT: | |
2569 | case CONST_DOUBLE: | |
2570 | case CONST: | |
2571 | case SYMBOL_REF: | |
2572 | case CODE_LABEL: | |
2573 | case PC: | |
2574 | case CC0: | |
2575 | case ASM_INPUT: | |
2576 | case ADDR_VEC: | |
2577 | case ADDR_DIFF_VEC: | |
2578 | case RETURN: | |
2579 | return; | |
2580 | ||
2581 | case ADDRESSOF: | |
2582 | abort (); | |
2583 | ||
2584 | case REG: | |
2585 | regno = REGNO (x); | |
2586 | ||
2587 | /* First handle the case where we encounter a bare register that | |
2588 | is eliminable. Replace it with a PLUS. */ | |
2589 | if (regno < FIRST_PSEUDO_REGISTER) | |
2590 | { | |
2591 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2592 | ep++) | |
2593 | if (ep->from_rtx == x && ep->can_eliminate) | |
2594 | { | |
2595 | if (! mem_mode) | |
2596 | ep->ref_outside_mem = 1; | |
2597 | return; | |
2598 | } | |
2599 | ||
2600 | } | |
2601 | else if (reg_renumber[regno] < 0 && reg_equiv_constant | |
2602 | && reg_equiv_constant[regno] | |
2603 | && ! CONSTANT_P (reg_equiv_constant[regno])) | |
2604 | elimination_effects (reg_equiv_constant[regno], mem_mode); | |
2605 | return; | |
2606 | ||
2607 | case PRE_INC: | |
2608 | case POST_INC: | |
2609 | case PRE_DEC: | |
2610 | case POST_DEC: | |
2611 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2612 | if (ep->to_rtx == XEXP (x, 0)) | |
2613 | { | |
2614 | int size = GET_MODE_SIZE (mem_mode); | |
2615 | ||
2616 | /* If more bytes than MEM_MODE are pushed, account for them. */ | |
2617 | #ifdef PUSH_ROUNDING | |
2618 | if (ep->to_rtx == stack_pointer_rtx) | |
2619 | size = PUSH_ROUNDING (size); | |
2620 | #endif | |
2621 | if (code == PRE_DEC || code == POST_DEC) | |
2622 | ep->offset += size; | |
2623 | else | |
2624 | ep->offset -= size; | |
2625 | } | |
2626 | ||
2627 | /* Fall through to generic unary operation case. */ | |
2628 | case STRICT_LOW_PART: | |
2629 | case NEG: case NOT: | |
2630 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2631 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2632 | case FLOAT: case FIX: | |
2633 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2634 | case ABS: | |
2635 | case SQRT: | |
2636 | case FFS: | |
2637 | elimination_effects (XEXP (x, 0), mem_mode); | |
2638 | return; | |
2639 | ||
2640 | case SUBREG: | |
2641 | if (GET_CODE (SUBREG_REG (x)) == REG | |
2642 | && (GET_MODE_SIZE (GET_MODE (x)) | |
2643 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2644 | && reg_equiv_memory_loc != 0 | |
2645 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2646 | return; | |
2647 | ||
2648 | elimination_effects (SUBREG_REG (x), mem_mode); | |
2649 | return; | |
2650 | ||
2651 | case USE: | |
2652 | /* If using a register that is the source of an eliminate we still | |
2653 | think can be performed, note it cannot be performed since we don't | |
2654 | know how this register is used. */ | |
2655 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2656 | if (ep->from_rtx == XEXP (x, 0)) | |
2657 | ep->can_eliminate = 0; | |
2658 | ||
2659 | elimination_effects (XEXP (x, 0), mem_mode); | |
2660 | return; | |
2661 | ||
2662 | case CLOBBER: | |
2663 | /* If clobbering a register that is the replacement register for an | |
2664 | elimination we still think can be performed, note that it cannot | |
2665 | be performed. Otherwise, we need not be concerned about it. */ | |
2666 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2667 | if (ep->to_rtx == XEXP (x, 0)) | |
2668 | ep->can_eliminate = 0; | |
2669 | ||
2670 | elimination_effects (XEXP (x, 0), mem_mode); | |
2671 | return; | |
2672 | ||
2673 | case SET: | |
2674 | /* Check for setting a register that we know about. */ | |
2675 | if (GET_CODE (SET_DEST (x)) == REG) | |
2676 | { | |
2677 | /* See if this is setting the replacement register for an | |
2678 | elimination. | |
2679 | ||
2680 | If DEST is the hard frame pointer, we do nothing because we | |
2681 | assume that all assignments to the frame pointer are for | |
2682 | non-local gotos and are being done at a time when they are valid | |
2683 | and do not disturb anything else. Some machines want to | |
2684 | eliminate a fake argument pointer (or even a fake frame pointer) | |
2685 | with either the real frame or the stack pointer. Assignments to | |
2686 | the hard frame pointer must not prevent this elimination. */ | |
2687 | ||
2688 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2689 | ep++) | |
2690 | if (ep->to_rtx == SET_DEST (x) | |
2691 | && SET_DEST (x) != hard_frame_pointer_rtx) | |
2692 | { | |
2693 | /* If it is being incremented, adjust the offset. Otherwise, | |
2694 | this elimination can't be done. */ | |
2695 | rtx src = SET_SRC (x); | |
2696 | ||
2697 | if (GET_CODE (src) == PLUS | |
2698 | && XEXP (src, 0) == SET_DEST (x) | |
2699 | && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
2700 | ep->offset -= INTVAL (XEXP (src, 1)); | |
2701 | else | |
2702 | ep->can_eliminate = 0; | |
2703 | } | |
2704 | } | |
2705 | ||
2706 | elimination_effects (SET_DEST (x), 0); | |
2707 | elimination_effects (SET_SRC (x), 0); | |
2708 | return; | |
2709 | ||
2710 | case MEM: | |
2711 | if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) | |
2712 | abort (); | |
2713 | ||
2714 | /* Our only special processing is to pass the mode of the MEM to our | |
2715 | recursive call. */ | |
2716 | elimination_effects (XEXP (x, 0), GET_MODE (x)); | |
2717 | return; | |
2718 | ||
2719 | default: | |
2720 | break; | |
2721 | } | |
2722 | ||
2723 | fmt = GET_RTX_FORMAT (code); | |
2724 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2725 | { | |
2726 | if (*fmt == 'e') | |
2727 | elimination_effects (XEXP (x, i), mem_mode); | |
2728 | else if (*fmt == 'E') | |
2729 | for (j = 0; j < XVECLEN (x, i); j++) | |
2730 | elimination_effects (XVECEXP (x, i, j), mem_mode); | |
2731 | } | |
2732 | } | |
2733 | ||
2734 | /* Descend through rtx X and verify that no references to eliminable registers | |
2735 | remain. If any do remain, mark the involved register as not | |
2736 | eliminable. */ | |
2737 | static void | |
2738 | check_eliminable_occurrences (x) | |
2739 | rtx x; | |
2740 | { | |
2741 | const char *fmt; | |
2742 | int i; | |
2743 | enum rtx_code code; | |
2744 | ||
2745 | if (x == 0) | |
2746 | return; | |
2747 | ||
2748 | code = GET_CODE (x); | |
2749 | ||
2750 | if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
2751 | { | |
2752 | struct elim_table *ep; | |
2753 | ||
2754 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2755 | if (ep->from_rtx == x && ep->can_eliminate) | |
2756 | ep->can_eliminate = 0; | |
2757 | return; | |
2758 | } | |
2759 | ||
2760 | fmt = GET_RTX_FORMAT (code); | |
2761 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2762 | { | |
2763 | if (*fmt == 'e') | |
2764 | check_eliminable_occurrences (XEXP (x, i)); | |
2765 | else if (*fmt == 'E') | |
2766 | { | |
2767 | int j; | |
2768 | for (j = 0; j < XVECLEN (x, i); j++) | |
2769 | check_eliminable_occurrences (XVECEXP (x, i, j)); | |
2770 | } | |
2771 | } | |
2772 | } | |
32131a9c RK |
2773 | \f |
2774 | /* Scan INSN and eliminate all eliminable registers in it. | |
2775 | ||
2776 | If REPLACE is nonzero, do the replacement destructively. Also | |
2777 | delete the insn as dead it if it is setting an eliminable register. | |
2778 | ||
2779 | If REPLACE is zero, do all our allocations in reload_obstack. | |
2780 | ||
2781 | If no eliminations were done and this insn doesn't require any elimination | |
2782 | processing (these are not identical conditions: it might be updating sp, | |
2783 | but not referencing fp; this needs to be seen during reload_as_needed so | |
2784 | that the offset between fp and sp can be taken into consideration), zero | |
2785 | is returned. Otherwise, 1 is returned. */ | |
2786 | ||
2787 | static int | |
2788 | eliminate_regs_in_insn (insn, replace) | |
2789 | rtx insn; | |
2790 | int replace; | |
2791 | { | |
dfac187e | 2792 | int icode = recog_memoized (insn); |
32131a9c | 2793 | rtx old_body = PATTERN (insn); |
dfac187e | 2794 | int insn_is_asm = asm_noperands (old_body) >= 0; |
774672d2 | 2795 | rtx old_set = single_set (insn); |
32131a9c RK |
2796 | rtx new_body; |
2797 | int val = 0; | |
dfac187e BS |
2798 | int i, any_changes; |
2799 | rtx substed_operand[MAX_RECOG_OPERANDS]; | |
2800 | rtx orig_operand[MAX_RECOG_OPERANDS]; | |
32131a9c RK |
2801 | struct elim_table *ep; |
2802 | ||
dfac187e BS |
2803 | if (! insn_is_asm && icode < 0) |
2804 | { | |
2805 | if (GET_CODE (PATTERN (insn)) == USE | |
2806 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
2807 | || GET_CODE (PATTERN (insn)) == ADDR_VEC | |
2808 | || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | |
2809 | || GET_CODE (PATTERN (insn)) == ASM_INPUT) | |
2810 | return 0; | |
2811 | abort (); | |
2812 | } | |
2813 | ||
32131a9c RK |
2814 | if (! replace) |
2815 | push_obstacks (&reload_obstack, &reload_obstack); | |
2816 | ||
774672d2 RK |
2817 | if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG |
2818 | && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) | |
32131a9c RK |
2819 | { |
2820 | /* Check for setting an eliminable register. */ | |
2821 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
774672d2 | 2822 | if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) |
32131a9c | 2823 | { |
dd1eab0a RK |
2824 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
2825 | /* If this is setting the frame pointer register to the | |
2826 | hardware frame pointer register and this is an elimination | |
2827 | that will be done (tested above), this insn is really | |
2828 | adjusting the frame pointer downward to compensate for | |
2829 | the adjustment done before a nonlocal goto. */ | |
2830 | if (ep->from == FRAME_POINTER_REGNUM | |
2831 | && ep->to == HARD_FRAME_POINTER_REGNUM) | |
2832 | { | |
2833 | rtx src = SET_SRC (old_set); | |
973838fd | 2834 | int offset = 0, ok = 0; |
8026ebba | 2835 | rtx prev_insn, prev_set; |
dd1eab0a RK |
2836 | |
2837 | if (src == ep->to_rtx) | |
2838 | offset = 0, ok = 1; | |
2839 | else if (GET_CODE (src) == PLUS | |
bb22893c JW |
2840 | && GET_CODE (XEXP (src, 0)) == CONST_INT |
2841 | && XEXP (src, 1) == ep->to_rtx) | |
dd1eab0a | 2842 | offset = INTVAL (XEXP (src, 0)), ok = 1; |
bb22893c JW |
2843 | else if (GET_CODE (src) == PLUS |
2844 | && GET_CODE (XEXP (src, 1)) == CONST_INT | |
2845 | && XEXP (src, 0) == ep->to_rtx) | |
2846 | offset = INTVAL (XEXP (src, 1)), ok = 1; | |
8026ebba ILT |
2847 | else if ((prev_insn = prev_nonnote_insn (insn)) != 0 |
2848 | && (prev_set = single_set (prev_insn)) != 0 | |
2849 | && rtx_equal_p (SET_DEST (prev_set), src)) | |
2850 | { | |
2851 | src = SET_SRC (prev_set); | |
2852 | if (src == ep->to_rtx) | |
2853 | offset = 0, ok = 1; | |
2854 | else if (GET_CODE (src) == PLUS | |
2855 | && GET_CODE (XEXP (src, 0)) == CONST_INT | |
2856 | && XEXP (src, 1) == ep->to_rtx) | |
2857 | offset = INTVAL (XEXP (src, 0)), ok = 1; | |
2858 | else if (GET_CODE (src) == PLUS | |
2859 | && GET_CODE (XEXP (src, 1)) == CONST_INT | |
2860 | && XEXP (src, 0) == ep->to_rtx) | |
2861 | offset = INTVAL (XEXP (src, 1)), ok = 1; | |
2862 | } | |
dd1eab0a RK |
2863 | |
2864 | if (ok) | |
2865 | { | |
2866 | if (replace) | |
2867 | { | |
2868 | rtx src | |
2869 | = plus_constant (ep->to_rtx, offset - ep->offset); | |
2870 | ||
2871 | /* First see if this insn remains valid when we | |
2872 | make the change. If not, keep the INSN_CODE | |
2873 | the same and let reload fit it up. */ | |
2874 | validate_change (insn, &SET_SRC (old_set), src, 1); | |
2875 | validate_change (insn, &SET_DEST (old_set), | |
2876 | ep->to_rtx, 1); | |
2877 | if (! apply_change_group ()) | |
2878 | { | |
2879 | SET_SRC (old_set) = src; | |
2880 | SET_DEST (old_set) = ep->to_rtx; | |
2881 | } | |
2882 | } | |
2883 | ||
2884 | val = 1; | |
2885 | goto done; | |
2886 | } | |
2887 | } | |
2888 | #endif | |
2889 | ||
32131a9c RK |
2890 | /* In this case this insn isn't serving a useful purpose. We |
2891 | will delete it in reload_as_needed once we know that this | |
2892 | elimination is, in fact, being done. | |
2893 | ||
abc95ed3 | 2894 | If REPLACE isn't set, we can't delete this insn, but needn't |
32131a9c RK |
2895 | process it since it won't be used unless something changes. */ |
2896 | if (replace) | |
8a34409d RH |
2897 | { |
2898 | delete_dead_insn (insn); | |
2899 | return 1; | |
2900 | } | |
32131a9c RK |
2901 | val = 1; |
2902 | goto done; | |
2903 | } | |
2904 | ||
2905 | /* Check for (set (reg) (plus (reg from) (offset))) where the offset | |
2906 | in the insn is the negative of the offset in FROM. Substitute | |
2907 | (set (reg) (reg to)) for the insn and change its code. | |
2908 | ||
cb2afeb3 | 2909 | We have to do this here, rather than in eliminate_regs, so that we can |
32131a9c RK |
2910 | change the insn code. */ |
2911 | ||
774672d2 RK |
2912 | if (GET_CODE (SET_SRC (old_set)) == PLUS |
2913 | && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG | |
2914 | && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT) | |
32131a9c RK |
2915 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; |
2916 | ep++) | |
774672d2 | 2917 | if (ep->from_rtx == XEXP (SET_SRC (old_set), 0) |
922d9d40 | 2918 | && ep->can_eliminate) |
32131a9c | 2919 | { |
922d9d40 RK |
2920 | /* We must stop at the first elimination that will be used. |
2921 | If this one would replace the PLUS with a REG, do it | |
2922 | now. Otherwise, quit the loop and let eliminate_regs | |
2923 | do its normal replacement. */ | |
774672d2 | 2924 | if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1))) |
922d9d40 | 2925 | { |
774672d2 RK |
2926 | /* We assume here that we don't need a PARALLEL of |
2927 | any CLOBBERs for this assignment. There's not | |
2928 | much we can do if we do need it. */ | |
38a448ca RH |
2929 | PATTERN (insn) = gen_rtx_SET (VOIDmode, |
2930 | SET_DEST (old_set), | |
2931 | ep->to_rtx); | |
922d9d40 RK |
2932 | INSN_CODE (insn) = -1; |
2933 | val = 1; | |
2934 | goto done; | |
2935 | } | |
2936 | ||
2937 | break; | |
32131a9c RK |
2938 | } |
2939 | } | |
2940 | ||
dfac187e BS |
2941 | /* Determine the effects of this insn on elimination offsets. */ |
2942 | elimination_effects (old_body, 0); | |
2943 | ||
2944 | /* Eliminate all eliminable registers occurring in operands that | |
2945 | can be handled by reload. */ | |
2946 | extract_insn (insn); | |
2947 | any_changes = 0; | |
2948 | for (i = 0; i < recog_data.n_operands; i++) | |
2949 | { | |
2950 | orig_operand[i] = recog_data.operand[i]; | |
2951 | substed_operand[i] = recog_data.operand[i]; | |
2952 | ||
2953 | /* For an asm statement, every operand is eliminable. */ | |
2954 | if (insn_is_asm || insn_data[icode].operand[i].eliminable) | |
2955 | { | |
2956 | /* Check for setting a register that we know about. */ | |
2957 | if (recog_data.operand_type[i] != OP_IN | |
2958 | && GET_CODE (orig_operand[i]) == REG) | |
2959 | { | |
2960 | /* If we are assigning to a register that can be eliminated, it | |
2961 | must be as part of a PARALLEL, since the code above handles | |
2962 | single SETs. We must indicate that we can no longer | |
2963 | eliminate this reg. */ | |
2964 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2965 | ep++) | |
2966 | if (ep->from_rtx == orig_operand[i] && ep->can_eliminate) | |
2967 | ep->can_eliminate = 0; | |
2968 | } | |
2969 | ||
2970 | substed_operand[i] = eliminate_regs (recog_data.operand[i], 0, | |
2971 | replace ? insn : NULL_RTX); | |
2972 | if (substed_operand[i] != orig_operand[i]) | |
2973 | val = any_changes = 1; | |
2974 | /* Terminate the search in check_eliminable_occurrences at | |
2975 | this point. */ | |
2976 | *recog_data.operand_loc[i] = 0; | |
2977 | ||
2978 | /* If an output operand changed from a REG to a MEM and INSN is an | |
2979 | insn, write a CLOBBER insn. */ | |
2980 | if (recog_data.operand_type[i] != OP_IN | |
2981 | && GET_CODE (orig_operand[i]) == REG | |
2982 | && GET_CODE (substed_operand[i]) == MEM | |
2983 | && replace) | |
2984 | emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]), | |
2985 | insn); | |
2986 | } | |
2987 | } | |
2988 | ||
2989 | for (i = 0; i < recog_data.n_dups; i++) | |
2990 | *recog_data.dup_loc[i] | |
2991 | = *recog_data.operand_loc[(int)recog_data.dup_num[i]]; | |
2992 | ||
2993 | /* If any eliminable remain, they aren't eliminable anymore. */ | |
2994 | check_eliminable_occurrences (old_body); | |
32131a9c | 2995 | |
dfac187e BS |
2996 | /* Substitute the operands; the new values are in the substed_operand |
2997 | array. */ | |
2998 | for (i = 0; i < recog_data.n_operands; i++) | |
2999 | *recog_data.operand_loc[i] = substed_operand[i]; | |
3000 | for (i = 0; i < recog_data.n_dups; i++) | |
3001 | *recog_data.dup_loc[i] = substed_operand[(int)recog_data.dup_num[i]]; | |
32131a9c | 3002 | |
dfac187e | 3003 | /* If we are replacing a body that was a (set X (plus Y Z)), try to |
32131a9c RK |
3004 | re-recognize the insn. We do this in case we had a simple addition |
3005 | but now can do this as a load-address. This saves an insn in this | |
dfac187e BS |
3006 | common case. |
3007 | If re-recognition fails, the old insn code number will still be used, | |
3008 | and some register operands may have changed into PLUS expressions. | |
3009 | These will be handled by find_reloads by loading them into a register | |
3010 | again.*/ | |
32131a9c | 3011 | |
dfac187e | 3012 | if (val) |
32131a9c | 3013 | { |
7c791b13 RK |
3014 | /* If we aren't replacing things permanently and we changed something, |
3015 | make another copy to ensure that all the RTL is new. Otherwise | |
3016 | things can go wrong if find_reload swaps commutative operands | |
0f41302f | 3017 | and one is inside RTL that has been copied while the other is not. */ |
dfac187e BS |
3018 | new_body = old_body; |
3019 | if (! replace) | |
1b3b5765 BS |
3020 | { |
3021 | new_body = copy_insn (old_body); | |
3022 | if (REG_NOTES (insn)) | |
3023 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3024 | } | |
dfac187e | 3025 | PATTERN (insn) = new_body; |
7c791b13 | 3026 | |
774672d2 RK |
3027 | /* If we had a move insn but now we don't, rerecognize it. This will |
3028 | cause spurious re-recognition if the old move had a PARALLEL since | |
3029 | the new one still will, but we can't call single_set without | |
3030 | having put NEW_BODY into the insn and the re-recognition won't | |
3031 | hurt in this rare case. */ | |
dfac187e BS |
3032 | /* ??? Why this huge if statement - why don't we just rerecognize the |
3033 | thing always? */ | |
3034 | if (! insn_is_asm | |
3035 | && old_set != 0 | |
774672d2 RK |
3036 | && ((GET_CODE (SET_SRC (old_set)) == REG |
3037 | && (GET_CODE (new_body) != SET | |
3038 | || GET_CODE (SET_SRC (new_body)) != REG)) | |
3039 | /* If this was a load from or store to memory, compare | |
1ccbefce RH |
3040 | the MEM in recog_data.operand to the one in the insn. |
3041 | If they are not equal, then rerecognize the insn. */ | |
774672d2 RK |
3042 | || (old_set != 0 |
3043 | && ((GET_CODE (SET_SRC (old_set)) == MEM | |
1ccbefce | 3044 | && SET_SRC (old_set) != recog_data.operand[1]) |
774672d2 | 3045 | || (GET_CODE (SET_DEST (old_set)) == MEM |
1ccbefce | 3046 | && SET_DEST (old_set) != recog_data.operand[0]))) |
774672d2 RK |
3047 | /* If this was an add insn before, rerecognize. */ |
3048 | || GET_CODE (SET_SRC (old_set)) == PLUS)) | |
4a5d0fb5 | 3049 | { |
dfac187e BS |
3050 | int new_icode = recog (PATTERN (insn), insn, 0); |
3051 | if (new_icode < 0) | |
3052 | INSN_CODE (insn) = icode; | |
4a5d0fb5 | 3053 | } |
dfac187e | 3054 | } |
32131a9c | 3055 | |
dfac187e BS |
3056 | /* Restore the old body. If there were any changes to it, we made a copy |
3057 | of it while the changes were still in place, so we'll correctly return | |
3058 | a modified insn below. */ | |
3059 | if (! replace) | |
3060 | { | |
3061 | /* Restore the old body. */ | |
3062 | for (i = 0; i < recog_data.n_operands; i++) | |
3063 | *recog_data.operand_loc[i] = orig_operand[i]; | |
3064 | for (i = 0; i < recog_data.n_dups; i++) | |
3065 | *recog_data.dup_loc[i] = orig_operand[(int)recog_data.dup_num[i]]; | |
32131a9c | 3066 | } |
a8fdc208 | 3067 | |
dfac187e BS |
3068 | /* Update all elimination pairs to reflect the status after the current |
3069 | insn. The changes we make were determined by the earlier call to | |
3070 | elimination_effects. | |
a8efe40d | 3071 | |
32131a9c RK |
3072 | We also detect a cases where register elimination cannot be done, |
3073 | namely, if a register would be both changed and referenced outside a MEM | |
3074 | in the resulting insn since such an insn is often undefined and, even if | |
3075 | not, we cannot know what meaning will be given to it. Note that it is | |
3076 | valid to have a register used in an address in an insn that changes it | |
3077 | (presumably with a pre- or post-increment or decrement). | |
3078 | ||
3079 | If anything changes, return nonzero. */ | |
3080 | ||
32131a9c RK |
3081 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3082 | { | |
3083 | if (ep->previous_offset != ep->offset && ep->ref_outside_mem) | |
3084 | ep->can_eliminate = 0; | |
3085 | ||
3086 | ep->ref_outside_mem = 0; | |
3087 | ||
3088 | if (ep->previous_offset != ep->offset) | |
3089 | val = 1; | |
32131a9c RK |
3090 | } |
3091 | ||
3092 | done: | |
9faa82d8 | 3093 | /* If we changed something, perform elimination in REG_NOTES. This is |
05b4c365 RK |
3094 | needed even when REPLACE is zero because a REG_DEAD note might refer |
3095 | to a register that we eliminate and could cause a different number | |
3096 | of spill registers to be needed in the final reload pass than in | |
3097 | the pre-passes. */ | |
20748cab | 3098 | if (val && REG_NOTES (insn) != 0) |
1914f5da | 3099 | REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn)); |
05b4c365 | 3100 | |
32131a9c RK |
3101 | if (! replace) |
3102 | pop_obstacks (); | |
3103 | ||
3104 | return val; | |
3105 | } | |
3106 | ||
cb2afeb3 R |
3107 | /* Loop through all elimination pairs. |
3108 | Recalculate the number not at initial offset. | |
3109 | ||
3110 | Compute the maximum offset (minimum offset if the stack does not | |
3111 | grow downward) for each elimination pair. */ | |
3112 | ||
3113 | static void | |
3114 | update_eliminable_offsets () | |
3115 | { | |
3116 | struct elim_table *ep; | |
3117 | ||
3118 | num_not_at_initial_offset = 0; | |
3119 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3120 | { | |
3121 | ep->previous_offset = ep->offset; | |
3122 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3123 | num_not_at_initial_offset++; | |
cb2afeb3 R |
3124 | } |
3125 | } | |
3126 | ||
32131a9c RK |
3127 | /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register |
3128 | replacement we currently believe is valid, mark it as not eliminable if X | |
3129 | modifies DEST in any way other than by adding a constant integer to it. | |
3130 | ||
3131 | If DEST is the frame pointer, we do nothing because we assume that | |
3ec2ea3e DE |
3132 | all assignments to the hard frame pointer are nonlocal gotos and are being |
3133 | done at a time when they are valid and do not disturb anything else. | |
32131a9c | 3134 | Some machines want to eliminate a fake argument pointer with either the |
3ec2ea3e DE |
3135 | frame or stack pointer. Assignments to the hard frame pointer must not |
3136 | prevent this elimination. | |
32131a9c RK |
3137 | |
3138 | Called via note_stores from reload before starting its passes to scan | |
3139 | the insns of the function. */ | |
3140 | ||
3141 | static void | |
84832317 | 3142 | mark_not_eliminable (dest, x, data) |
32131a9c RK |
3143 | rtx dest; |
3144 | rtx x; | |
84832317 | 3145 | void *data ATTRIBUTE_UNUSED; |
32131a9c | 3146 | { |
e51712db | 3147 | register unsigned int i; |
32131a9c RK |
3148 | |
3149 | /* A SUBREG of a hard register here is just changing its mode. We should | |
3150 | not see a SUBREG of an eliminable hard register, but check just in | |
3151 | case. */ | |
3152 | if (GET_CODE (dest) == SUBREG) | |
3153 | dest = SUBREG_REG (dest); | |
3154 | ||
3ec2ea3e | 3155 | if (dest == hard_frame_pointer_rtx) |
32131a9c RK |
3156 | return; |
3157 | ||
3158 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3159 | if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx | |
3160 | && (GET_CODE (x) != SET | |
3161 | || GET_CODE (SET_SRC (x)) != PLUS | |
3162 | || XEXP (SET_SRC (x), 0) != dest | |
3163 | || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT)) | |
3164 | { | |
3165 | reg_eliminate[i].can_eliminate_previous | |
3166 | = reg_eliminate[i].can_eliminate = 0; | |
3167 | num_eliminable--; | |
3168 | } | |
3169 | } | |
09dd1133 | 3170 | |
c47f5ea5 BS |
3171 | /* Verify that the initial elimination offsets did not change since the |
3172 | last call to set_initial_elim_offsets. This is used to catch cases | |
3173 | where something illegal happened during reload_as_needed that could | |
3174 | cause incorrect code to be generated if we did not check for it. */ | |
3175 | static void | |
3176 | verify_initial_elim_offsets () | |
3177 | { | |
3178 | int t; | |
3179 | ||
3180 | #ifdef ELIMINABLE_REGS | |
3181 | struct elim_table *ep; | |
3182 | ||
3183 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3184 | { | |
3185 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t); | |
3186 | if (t != ep->initial_offset) | |
3187 | abort (); | |
3188 | } | |
3189 | #else | |
3190 | INITIAL_FRAME_POINTER_OFFSET (t); | |
3191 | if (t != reg_eliminate[0].initial_offset) | |
3192 | abort (); | |
05d10675 | 3193 | #endif |
c47f5ea5 BS |
3194 | } |
3195 | ||
09dd1133 BS |
3196 | /* Reset all offsets on eliminable registers to their initial values. */ |
3197 | static void | |
3198 | set_initial_elim_offsets () | |
3199 | { | |
1f3b1e1a | 3200 | struct elim_table *ep = reg_eliminate; |
09dd1133 BS |
3201 | |
3202 | #ifdef ELIMINABLE_REGS | |
1f3b1e1a | 3203 | for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
09dd1133 BS |
3204 | { |
3205 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); | |
1f3b1e1a | 3206 | ep->previous_offset = ep->offset = ep->initial_offset; |
09dd1133 BS |
3207 | } |
3208 | #else | |
1f3b1e1a JL |
3209 | INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset); |
3210 | ep->previous_offset = ep->offset = ep->initial_offset; | |
09dd1133 BS |
3211 | #endif |
3212 | ||
3213 | num_not_at_initial_offset = 0; | |
1f3b1e1a | 3214 | } |
09dd1133 | 3215 | |
1f3b1e1a JL |
3216 | /* Initialize the known label offsets. |
3217 | Set a known offset for each forced label to be at the initial offset | |
3218 | of each elimination. We do this because we assume that all | |
3219 | computed jumps occur from a location where each elimination is | |
3220 | at its initial offset. | |
3221 | For all other labels, show that we don't know the offsets. */ | |
09dd1133 | 3222 | |
1f3b1e1a JL |
3223 | static void |
3224 | set_initial_label_offsets () | |
3225 | { | |
3226 | rtx x; | |
3227 | bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels); | |
09dd1133 BS |
3228 | |
3229 | for (x = forced_labels; x; x = XEXP (x, 1)) | |
3230 | if (XEXP (x, 0)) | |
3231 | set_label_offsets (XEXP (x, 0), NULL_RTX, 1); | |
3232 | } | |
3233 | ||
1f3b1e1a JL |
3234 | /* Set all elimination offsets to the known values for the code label given |
3235 | by INSN. */ | |
3236 | static void | |
3237 | set_offsets_for_label (insn) | |
3238 | rtx insn; | |
3239 | { | |
973838fd | 3240 | unsigned int i; |
1f3b1e1a JL |
3241 | int label_nr = CODE_LABEL_NUMBER (insn); |
3242 | struct elim_table *ep; | |
3243 | ||
3244 | num_not_at_initial_offset = 0; | |
3245 | for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++) | |
3246 | { | |
3247 | ep->offset = ep->previous_offset = offsets_at[label_nr][i]; | |
3248 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3249 | num_not_at_initial_offset++; | |
3250 | } | |
3251 | } | |
3252 | ||
09dd1133 BS |
3253 | /* See if anything that happened changes which eliminations are valid. |
3254 | For example, on the Sparc, whether or not the frame pointer can | |
3255 | be eliminated can depend on what registers have been used. We need | |
3256 | not check some conditions again (such as flag_omit_frame_pointer) | |
3257 | since they can't have changed. */ | |
3258 | ||
3259 | static void | |
3260 | update_eliminables (pset) | |
3261 | HARD_REG_SET *pset; | |
3262 | { | |
3263 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
3264 | int previous_frame_pointer_needed = frame_pointer_needed; | |
3265 | #endif | |
3266 | struct elim_table *ep; | |
3267 | ||
3268 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3269 | if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED) | |
3270 | #ifdef ELIMINABLE_REGS | |
3271 | || ! CAN_ELIMINATE (ep->from, ep->to) | |
3272 | #endif | |
3273 | ) | |
3274 | ep->can_eliminate = 0; | |
3275 | ||
3276 | /* Look for the case where we have discovered that we can't replace | |
3277 | register A with register B and that means that we will now be | |
3278 | trying to replace register A with register C. This means we can | |
3279 | no longer replace register C with register B and we need to disable | |
3280 | such an elimination, if it exists. This occurs often with A == ap, | |
3281 | B == sp, and C == fp. */ | |
3282 | ||
3283 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3284 | { | |
3285 | struct elim_table *op; | |
3286 | register int new_to = -1; | |
3287 | ||
3288 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3289 | { | |
3290 | /* Find the current elimination for ep->from, if there is a | |
3291 | new one. */ | |
3292 | for (op = reg_eliminate; | |
3293 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3294 | if (op->from == ep->from && op->can_eliminate) | |
3295 | { | |
3296 | new_to = op->to; | |
3297 | break; | |
3298 | } | |
3299 | ||
3300 | /* See if there is an elimination of NEW_TO -> EP->TO. If so, | |
3301 | disable it. */ | |
3302 | for (op = reg_eliminate; | |
3303 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3304 | if (op->from == new_to && op->to == ep->to) | |
3305 | op->can_eliminate = 0; | |
3306 | } | |
3307 | } | |
3308 | ||
3309 | /* See if any registers that we thought we could eliminate the previous | |
3310 | time are no longer eliminable. If so, something has changed and we | |
3311 | must spill the register. Also, recompute the number of eliminable | |
3312 | registers and see if the frame pointer is needed; it is if there is | |
3313 | no elimination of the frame pointer that we can perform. */ | |
3314 | ||
3315 | frame_pointer_needed = 1; | |
3316 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3317 | { | |
3318 | if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM | |
3319 | && ep->to != HARD_FRAME_POINTER_REGNUM) | |
3320 | frame_pointer_needed = 0; | |
3321 | ||
3322 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3323 | { | |
3324 | ep->can_eliminate_previous = 0; | |
3325 | SET_HARD_REG_BIT (*pset, ep->from); | |
3326 | num_eliminable--; | |
3327 | } | |
3328 | } | |
3329 | ||
3330 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
3331 | /* If we didn't need a frame pointer last time, but we do now, spill | |
3332 | the hard frame pointer. */ | |
3333 | if (frame_pointer_needed && ! previous_frame_pointer_needed) | |
3334 | SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM); | |
3335 | #endif | |
3336 | } | |
3337 | ||
3338 | /* Initialize the table of registers to eliminate. */ | |
3339 | static void | |
3340 | init_elim_table () | |
3341 | { | |
3342 | struct elim_table *ep; | |
590cf94d KG |
3343 | #ifdef ELIMINABLE_REGS |
3344 | struct elim_table_1 *ep1; | |
3345 | #endif | |
09dd1133 | 3346 | |
590cf94d | 3347 | if (!reg_eliminate) |
ad85216e KG |
3348 | reg_eliminate = (struct elim_table *) |
3349 | xcalloc(sizeof(struct elim_table), NUM_ELIMINABLE_REGS); | |
05d10675 | 3350 | |
09dd1133 BS |
3351 | /* Does this function require a frame pointer? */ |
3352 | ||
3353 | frame_pointer_needed = (! flag_omit_frame_pointer | |
3354 | #ifdef EXIT_IGNORE_STACK | |
3355 | /* ?? If EXIT_IGNORE_STACK is set, we will not save | |
3356 | and restore sp for alloca. So we can't eliminate | |
3357 | the frame pointer in that case. At some point, | |
3358 | we should improve this by emitting the | |
3359 | sp-adjusting insns for this case. */ | |
3360 | || (current_function_calls_alloca | |
3361 | && EXIT_IGNORE_STACK) | |
3362 | #endif | |
3363 | || FRAME_POINTER_REQUIRED); | |
3364 | ||
3365 | num_eliminable = 0; | |
3366 | ||
3367 | #ifdef ELIMINABLE_REGS | |
590cf94d KG |
3368 | for (ep = reg_eliminate, ep1 = reg_eliminate_1; |
3369 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++) | |
09dd1133 | 3370 | { |
590cf94d KG |
3371 | ep->from = ep1->from; |
3372 | ep->to = ep1->to; | |
09dd1133 BS |
3373 | ep->can_eliminate = ep->can_eliminate_previous |
3374 | = (CAN_ELIMINATE (ep->from, ep->to) | |
3375 | && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed)); | |
3376 | } | |
3377 | #else | |
590cf94d KG |
3378 | reg_eliminate[0].from = reg_eliminate_1[0].from; |
3379 | reg_eliminate[0].to = reg_eliminate_1[0].to; | |
09dd1133 BS |
3380 | reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous |
3381 | = ! frame_pointer_needed; | |
3382 | #endif | |
3383 | ||
3384 | /* Count the number of eliminable registers and build the FROM and TO | |
3385 | REG rtx's. Note that code in gen_rtx will cause, e.g., | |
3386 | gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. | |
3387 | We depend on this. */ | |
3388 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3389 | { | |
3390 | num_eliminable += ep->can_eliminate; | |
3391 | ep->from_rtx = gen_rtx_REG (Pmode, ep->from); | |
3392 | ep->to_rtx = gen_rtx_REG (Pmode, ep->to); | |
3393 | } | |
3394 | } | |
32131a9c RK |
3395 | \f |
3396 | /* Kick all pseudos out of hard register REGNO. | |
32131a9c RK |
3397 | If DUMPFILE is nonzero, log actions taken on that file. |
3398 | ||
3399 | If CANT_ELIMINATE is nonzero, it means that we are doing this spill | |
3400 | because we found we can't eliminate some register. In the case, no pseudos | |
3401 | are allowed to be in the register, even if they are only in a block that | |
3402 | doesn't require spill registers, unlike the case when we are spilling this | |
3403 | hard reg to produce another spill register. | |
3404 | ||
3405 | Return nonzero if any pseudos needed to be kicked out. */ | |
3406 | ||
03acd8f8 BS |
3407 | static void |
3408 | spill_hard_reg (regno, dumpfile, cant_eliminate) | |
32131a9c | 3409 | register int regno; |
6a651371 | 3410 | FILE *dumpfile ATTRIBUTE_UNUSED; |
32131a9c RK |
3411 | int cant_eliminate; |
3412 | { | |
32131a9c RK |
3413 | register int i; |
3414 | ||
9ff3516a | 3415 | if (cant_eliminate) |
03acd8f8 BS |
3416 | { |
3417 | SET_HARD_REG_BIT (bad_spill_regs_global, regno); | |
3418 | regs_ever_live[regno] = 1; | |
3419 | } | |
9ff3516a | 3420 | |
32131a9c RK |
3421 | /* Spill every pseudo reg that was allocated to this reg |
3422 | or to something that overlaps this reg. */ | |
3423 | ||
3424 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3425 | if (reg_renumber[i] >= 0 | |
3426 | && reg_renumber[i] <= regno | |
a8fdc208 | 3427 | && (reg_renumber[i] |
32131a9c RK |
3428 | + HARD_REGNO_NREGS (reg_renumber[i], |
3429 | PSEUDO_REGNO_MODE (i)) | |
3430 | > regno)) | |
f5d8c9f4 | 3431 | SET_REGNO_REG_SET (&spilled_pseudos, i); |
03acd8f8 | 3432 | } |
32131a9c | 3433 | |
03acd8f8 BS |
3434 | /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET |
3435 | from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */ | |
3436 | static void | |
3437 | ior_hard_reg_set (set1, set2) | |
3438 | HARD_REG_SET *set1, *set2; | |
3439 | { | |
3440 | IOR_HARD_REG_SET (*set1, *set2); | |
3441 | } | |
05d10675 | 3442 | |
03acd8f8 BS |
3443 | /* After find_reload_regs has been run for all insn that need reloads, |
3444 | and/or spill_hard_regs was called, this function is used to actually | |
3445 | spill pseudo registers and try to reallocate them. It also sets up the | |
3446 | spill_regs array for use by choose_reload_regs. */ | |
a8fdc208 | 3447 | |
03acd8f8 BS |
3448 | static int |
3449 | finish_spills (global, dumpfile) | |
3450 | int global; | |
3451 | FILE *dumpfile; | |
3452 | { | |
3453 | struct insn_chain *chain; | |
3454 | int something_changed = 0; | |
3455 | int i; | |
3456 | ||
3457 | /* Build the spill_regs array for the function. */ | |
3458 | /* If there are some registers still to eliminate and one of the spill regs | |
3459 | wasn't ever used before, additional stack space may have to be | |
3460 | allocated to store this register. Thus, we may have changed the offset | |
3461 | between the stack and frame pointers, so mark that something has changed. | |
32131a9c | 3462 | |
03acd8f8 BS |
3463 | One might think that we need only set VAL to 1 if this is a call-used |
3464 | register. However, the set of registers that must be saved by the | |
3465 | prologue is not identical to the call-used set. For example, the | |
3466 | register used by the call insn for the return PC is a call-used register, | |
3467 | but must be saved by the prologue. */ | |
3468 | ||
3469 | n_spills = 0; | |
3470 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3471 | if (TEST_HARD_REG_BIT (used_spill_regs, i)) | |
3472 | { | |
3473 | spill_reg_order[i] = n_spills; | |
3474 | spill_regs[n_spills++] = i; | |
3475 | if (num_eliminable && ! regs_ever_live[i]) | |
3476 | something_changed = 1; | |
3477 | regs_ever_live[i] = 1; | |
3478 | } | |
3479 | else | |
3480 | spill_reg_order[i] = -1; | |
3481 | ||
3482 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
f5d8c9f4 | 3483 | if (REGNO_REG_SET_P (&spilled_pseudos, i)) |
03acd8f8 BS |
3484 | { |
3485 | /* Record the current hard register the pseudo is allocated to in | |
3486 | pseudo_previous_regs so we avoid reallocating it to the same | |
3487 | hard reg in a later pass. */ | |
3488 | if (reg_renumber[i] < 0) | |
3489 | abort (); | |
3490 | SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]); | |
32131a9c RK |
3491 | /* Mark it as no longer having a hard register home. */ |
3492 | reg_renumber[i] = -1; | |
3493 | /* We will need to scan everything again. */ | |
3494 | something_changed = 1; | |
03acd8f8 | 3495 | } |
7609e720 | 3496 | |
03acd8f8 BS |
3497 | /* Retry global register allocation if possible. */ |
3498 | if (global) | |
3499 | { | |
3500 | bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET)); | |
3501 | /* For every insn that needs reloads, set the registers used as spill | |
3502 | regs in pseudo_forbidden_regs for every pseudo live across the | |
3503 | insn. */ | |
3504 | for (chain = insns_need_reload; chain; chain = chain->next_need_reload) | |
3505 | { | |
3506 | EXECUTE_IF_SET_IN_REG_SET | |
239a0f5b | 3507 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, |
03acd8f8 BS |
3508 | { |
3509 | ior_hard_reg_set (pseudo_forbidden_regs + i, | |
3510 | &chain->used_spill_regs); | |
3511 | }); | |
3512 | EXECUTE_IF_SET_IN_REG_SET | |
239a0f5b | 3513 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, |
03acd8f8 BS |
3514 | { |
3515 | ior_hard_reg_set (pseudo_forbidden_regs + i, | |
3516 | &chain->used_spill_regs); | |
3517 | }); | |
3518 | } | |
7609e720 | 3519 | |
03acd8f8 BS |
3520 | /* Retry allocating the spilled pseudos. For each reg, merge the |
3521 | various reg sets that indicate which hard regs can't be used, | |
3522 | and call retry_global_alloc. | |
05d10675 | 3523 | We change spill_pseudos here to only contain pseudos that did not |
03acd8f8 BS |
3524 | get a new hard register. */ |
3525 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3526 | if (reg_old_renumber[i] != reg_renumber[i]) | |
32131a9c | 3527 | { |
03acd8f8 BS |
3528 | HARD_REG_SET forbidden; |
3529 | COPY_HARD_REG_SET (forbidden, bad_spill_regs_global); | |
3530 | IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]); | |
3531 | IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]); | |
3532 | retry_global_alloc (i, forbidden); | |
3533 | if (reg_renumber[i] >= 0) | |
f5d8c9f4 | 3534 | CLEAR_REGNO_REG_SET (&spilled_pseudos, i); |
32131a9c | 3535 | } |
03acd8f8 | 3536 | } |
7609e720 | 3537 | |
03acd8f8 BS |
3538 | /* Fix up the register information in the insn chain. |
3539 | This involves deleting those of the spilled pseudos which did not get | |
3540 | a new hard register home from the live_{before,after} sets. */ | |
7609e720 BS |
3541 | for (chain = reload_insn_chain; chain; chain = chain->next) |
3542 | { | |
03acd8f8 BS |
3543 | HARD_REG_SET used_by_pseudos; |
3544 | HARD_REG_SET used_by_pseudos2; | |
3545 | ||
239a0f5b BS |
3546 | AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos); |
3547 | AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos); | |
03acd8f8 BS |
3548 | |
3549 | /* Mark any unallocated hard regs as available for spills. That | |
3550 | makes inheritance work somewhat better. */ | |
3551 | if (chain->need_reload) | |
3552 | { | |
239a0f5b BS |
3553 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); |
3554 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
03acd8f8 BS |
3555 | IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2); |
3556 | ||
3557 | /* Save the old value for the sanity test below. */ | |
3558 | COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs); | |
3559 | ||
239a0f5b BS |
3560 | compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout); |
3561 | compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set); | |
03acd8f8 BS |
3562 | COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos); |
3563 | AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs); | |
3564 | ||
3565 | /* Make sure we only enlarge the set. */ | |
3566 | GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok); | |
3567 | abort (); | |
3568 | ok:; | |
3569 | } | |
7609e720 | 3570 | } |
03acd8f8 BS |
3571 | |
3572 | /* Let alter_reg modify the reg rtx's for the modified pseudos. */ | |
3573 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3574 | { | |
3575 | int regno = reg_renumber[i]; | |
3576 | if (reg_old_renumber[i] == regno) | |
3577 | continue; | |
05d10675 | 3578 | |
03acd8f8 BS |
3579 | alter_reg (i, reg_old_renumber[i]); |
3580 | reg_old_renumber[i] = regno; | |
3581 | if (dumpfile) | |
3582 | { | |
3583 | if (regno == -1) | |
3584 | fprintf (dumpfile, " Register %d now on stack.\n\n", i); | |
3585 | else | |
3586 | fprintf (dumpfile, " Register %d now in %d.\n\n", | |
3587 | i, reg_renumber[i]); | |
3588 | } | |
3589 | } | |
3590 | ||
3591 | return something_changed; | |
7609e720 | 3592 | } |
32131a9c | 3593 | \f |
05d10675 | 3594 | /* Find all paradoxical subregs within X and update reg_max_ref_width. |
56f58d3a RK |
3595 | Also mark any hard registers used to store user variables as |
3596 | forbidden from being used for spill registers. */ | |
32131a9c RK |
3597 | |
3598 | static void | |
3599 | scan_paradoxical_subregs (x) | |
3600 | register rtx x; | |
3601 | { | |
3602 | register int i; | |
6f7d635c | 3603 | register const char *fmt; |
32131a9c RK |
3604 | register enum rtx_code code = GET_CODE (x); |
3605 | ||
3606 | switch (code) | |
3607 | { | |
56f58d3a | 3608 | case REG: |
03acd8f8 | 3609 | #if 0 |
e9a25f70 | 3610 | if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER |
f95182a4 | 3611 | && REG_USERVAR_P (x)) |
03acd8f8 BS |
3612 | SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x)); |
3613 | #endif | |
56f58d3a RK |
3614 | return; |
3615 | ||
32131a9c RK |
3616 | case CONST_INT: |
3617 | case CONST: | |
3618 | case SYMBOL_REF: | |
3619 | case LABEL_REF: | |
3620 | case CONST_DOUBLE: | |
3621 | case CC0: | |
3622 | case PC: | |
32131a9c RK |
3623 | case USE: |
3624 | case CLOBBER: | |
3625 | return; | |
3626 | ||
3627 | case SUBREG: | |
3628 | if (GET_CODE (SUBREG_REG (x)) == REG | |
3629 | && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
3630 | reg_max_ref_width[REGNO (SUBREG_REG (x))] | |
3631 | = GET_MODE_SIZE (GET_MODE (x)); | |
3632 | return; | |
05d10675 | 3633 | |
e9a25f70 JL |
3634 | default: |
3635 | break; | |
32131a9c RK |
3636 | } |
3637 | ||
3638 | fmt = GET_RTX_FORMAT (code); | |
3639 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3640 | { | |
3641 | if (fmt[i] == 'e') | |
3642 | scan_paradoxical_subregs (XEXP (x, i)); | |
3643 | else if (fmt[i] == 'E') | |
3644 | { | |
3645 | register int j; | |
3646 | for (j = XVECLEN (x, i) - 1; j >=0; j--) | |
3647 | scan_paradoxical_subregs (XVECEXP (x, i, j)); | |
3648 | } | |
3649 | } | |
3650 | } | |
3651 | \f | |
32131a9c RK |
3652 | /* Reload pseudo-registers into hard regs around each insn as needed. |
3653 | Additional register load insns are output before the insn that needs it | |
3654 | and perhaps store insns after insns that modify the reloaded pseudo reg. | |
3655 | ||
3656 | reg_last_reload_reg and reg_reloaded_contents keep track of | |
d08ea79f | 3657 | which registers are already available in reload registers. |
32131a9c RK |
3658 | We update these for the reloads that we perform, |
3659 | as the insns are scanned. */ | |
3660 | ||
3661 | static void | |
7609e720 | 3662 | reload_as_needed (live_known) |
32131a9c RK |
3663 | int live_known; |
3664 | { | |
7609e720 | 3665 | struct insn_chain *chain; |
553687c9 | 3666 | #if defined (AUTO_INC_DEC) |
32131a9c | 3667 | register int i; |
973838fd | 3668 | #endif |
32131a9c | 3669 | rtx x; |
32131a9c | 3670 | |
4c9a05bc RK |
3671 | bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx); |
3672 | bzero ((char *) spill_reg_store, sizeof spill_reg_store); | |
ff154f78 MM |
3673 | reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx)); |
3674 | reg_has_output_reload = (char *) xmalloc (max_regno); | |
e6e52be0 | 3675 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
32131a9c | 3676 | |
1f3b1e1a | 3677 | set_initial_elim_offsets (); |
32131a9c | 3678 | |
7609e720 | 3679 | for (chain = reload_insn_chain; chain; chain = chain->next) |
32131a9c | 3680 | { |
03acd8f8 | 3681 | rtx prev; |
7609e720 BS |
3682 | rtx insn = chain->insn; |
3683 | rtx old_next = NEXT_INSN (insn); | |
32131a9c RK |
3684 | |
3685 | /* If we pass a label, copy the offsets from the label information | |
3686 | into the current offsets of each elimination. */ | |
3687 | if (GET_CODE (insn) == CODE_LABEL) | |
1f3b1e1a | 3688 | set_offsets_for_label (insn); |
32131a9c RK |
3689 | |
3690 | else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
3691 | { | |
0639444f | 3692 | rtx oldpat = PATTERN (insn); |
32131a9c | 3693 | |
2758481d RS |
3694 | /* If this is a USE and CLOBBER of a MEM, ensure that any |
3695 | references to eliminable registers have been removed. */ | |
3696 | ||
3697 | if ((GET_CODE (PATTERN (insn)) == USE | |
3698 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
3699 | && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM) | |
3700 | XEXP (XEXP (PATTERN (insn), 0), 0) | |
3701 | = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), | |
29ae5012 | 3702 | GET_MODE (XEXP (PATTERN (insn), 0)), |
1914f5da | 3703 | NULL_RTX); |
2758481d | 3704 | |
32131a9c RK |
3705 | /* If we need to do register elimination processing, do so. |
3706 | This might delete the insn, in which case we are done. */ | |
2b49ee39 | 3707 | if ((num_eliminable || num_eliminable_invariants) && chain->need_elim) |
32131a9c RK |
3708 | { |
3709 | eliminate_regs_in_insn (insn, 1); | |
3710 | if (GET_CODE (insn) == NOTE) | |
cb2afeb3 R |
3711 | { |
3712 | update_eliminable_offsets (); | |
3713 | continue; | |
3714 | } | |
32131a9c RK |
3715 | } |
3716 | ||
7609e720 BS |
3717 | /* If need_elim is nonzero but need_reload is zero, one might think |
3718 | that we could simply set n_reloads to 0. However, find_reloads | |
3719 | could have done some manipulation of the insn (such as swapping | |
3720 | commutative operands), and these manipulations are lost during | |
3721 | the first pass for every insn that needs register elimination. | |
3722 | So the actions of find_reloads must be redone here. */ | |
3723 | ||
03acd8f8 BS |
3724 | if (! chain->need_elim && ! chain->need_reload |
3725 | && ! chain->need_operand_change) | |
32131a9c RK |
3726 | n_reloads = 0; |
3727 | /* First find the pseudo regs that must be reloaded for this insn. | |
3728 | This info is returned in the tables reload_... (see reload.h). | |
3729 | Also modify the body of INSN by substituting RELOAD | |
3730 | rtx's for those pseudo regs. */ | |
3731 | else | |
3732 | { | |
3733 | bzero (reg_has_output_reload, max_regno); | |
3734 | CLEAR_HARD_REG_SET (reg_is_output_reload); | |
3735 | ||
3736 | find_reloads (insn, 1, spill_indirect_levels, live_known, | |
3737 | spill_reg_order); | |
3738 | } | |
3739 | ||
dd6acd1b | 3740 | if (num_eliminable && chain->need_elim) |
cb2afeb3 R |
3741 | update_eliminable_offsets (); |
3742 | ||
32131a9c RK |
3743 | if (n_reloads > 0) |
3744 | { | |
cb2afeb3 | 3745 | rtx next = NEXT_INSN (insn); |
3c3eeea6 | 3746 | rtx p; |
32131a9c | 3747 | |
cb2afeb3 R |
3748 | prev = PREV_INSN (insn); |
3749 | ||
32131a9c RK |
3750 | /* Now compute which reload regs to reload them into. Perhaps |
3751 | reusing reload regs from previous insns, or else output | |
3752 | load insns to reload them. Maybe output store insns too. | |
3753 | Record the choices of reload reg in reload_reg_rtx. */ | |
03acd8f8 | 3754 | choose_reload_regs (chain); |
32131a9c | 3755 | |
05d10675 | 3756 | /* Merge any reloads that we didn't combine for fear of |
546b63fb RK |
3757 | increasing the number of spill registers needed but now |
3758 | discover can be safely merged. */ | |
f95182a4 ILT |
3759 | if (SMALL_REGISTER_CLASSES) |
3760 | merge_assigned_reloads (insn); | |
546b63fb | 3761 | |
32131a9c RK |
3762 | /* Generate the insns to reload operands into or out of |
3763 | their reload regs. */ | |
7609e720 | 3764 | emit_reload_insns (chain); |
32131a9c RK |
3765 | |
3766 | /* Substitute the chosen reload regs from reload_reg_rtx | |
3767 | into the insn's body (or perhaps into the bodies of other | |
3768 | load and store insn that we just made for reloading | |
3769 | and that we moved the structure into). */ | |
3770 | subst_reloads (); | |
3c3eeea6 RK |
3771 | |
3772 | /* If this was an ASM, make sure that all the reload insns | |
3773 | we have generated are valid. If not, give an error | |
3774 | and delete them. */ | |
3775 | ||
3776 | if (asm_noperands (PATTERN (insn)) >= 0) | |
3777 | for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) | |
3778 | if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i' | |
3779 | && (recog_memoized (p) < 0 | |
0eadeb15 | 3780 | || (extract_insn (p), ! constrain_operands (1)))) |
3c3eeea6 RK |
3781 | { |
3782 | error_for_asm (insn, | |
3783 | "`asm' operand requires impossible reload"); | |
3784 | PUT_CODE (p, NOTE); | |
3785 | NOTE_SOURCE_FILE (p) = 0; | |
3786 | NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED; | |
3787 | } | |
32131a9c RK |
3788 | } |
3789 | /* Any previously reloaded spilled pseudo reg, stored in this insn, | |
3790 | is no longer validly lying around to save a future reload. | |
3791 | Note that this does not detect pseudos that were reloaded | |
3792 | for this insn in order to be stored in | |
3793 | (obeying register constraints). That is correct; such reload | |
3794 | registers ARE still valid. */ | |
84832317 | 3795 | note_stores (oldpat, forget_old_reloads_1, NULL); |
32131a9c RK |
3796 | |
3797 | /* There may have been CLOBBER insns placed after INSN. So scan | |
3798 | between INSN and NEXT and use them to forget old reloads. */ | |
7609e720 | 3799 | for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x)) |
32131a9c | 3800 | if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER) |
84832317 | 3801 | note_stores (PATTERN (x), forget_old_reloads_1, NULL); |
32131a9c RK |
3802 | |
3803 | #ifdef AUTO_INC_DEC | |
cb2afeb3 R |
3804 | /* Likewise for regs altered by auto-increment in this insn. |
3805 | REG_INC notes have been changed by reloading: | |
3806 | find_reloads_address_1 records substitutions for them, | |
3807 | which have been performed by subst_reloads above. */ | |
3808 | for (i = n_reloads - 1; i >= 0; i--) | |
3809 | { | |
eceef4c9 | 3810 | rtx in_reg = rld[i].in_reg; |
cb2afeb3 R |
3811 | if (in_reg) |
3812 | { | |
3813 | enum rtx_code code = GET_CODE (in_reg); | |
3814 | /* PRE_INC / PRE_DEC will have the reload register ending up | |
3815 | with the same value as the stack slot, but that doesn't | |
3816 | hold true for POST_INC / POST_DEC. Either we have to | |
3817 | convert the memory access to a true POST_INC / POST_DEC, | |
3818 | or we can't use the reload register for inheritance. */ | |
3819 | if ((code == POST_INC || code == POST_DEC) | |
3820 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 3821 | REGNO (rld[i].reg_rtx)) |
04bbb0c5 JW |
3822 | /* Make sure it is the inc/dec pseudo, and not |
3823 | some other (e.g. output operand) pseudo. */ | |
eceef4c9 | 3824 | && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
04bbb0c5 | 3825 | == REGNO (XEXP (in_reg, 0)))) |
05d10675 | 3826 | |
cb2afeb3 | 3827 | { |
eceef4c9 | 3828 | rtx reload_reg = rld[i].reg_rtx; |
cb2afeb3 R |
3829 | enum machine_mode mode = GET_MODE (reload_reg); |
3830 | int n = 0; | |
3831 | rtx p; | |
3832 | ||
3833 | for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p)) | |
3834 | { | |
3835 | /* We really want to ignore REG_INC notes here, so | |
3836 | use PATTERN (p) as argument to reg_set_p . */ | |
3837 | if (reg_set_p (reload_reg, PATTERN (p))) | |
3838 | break; | |
3839 | n = count_occurrences (PATTERN (p), reload_reg); | |
3840 | if (! n) | |
3841 | continue; | |
3842 | if (n == 1) | |
f67c2384 JL |
3843 | { |
3844 | n = validate_replace_rtx (reload_reg, | |
3845 | gen_rtx (code, mode, | |
3846 | reload_reg), | |
3847 | p); | |
3848 | ||
3849 | /* We must also verify that the constraints | |
3850 | are met after the replacement. */ | |
3851 | extract_insn (p); | |
3852 | if (n) | |
3853 | n = constrain_operands (1); | |
3854 | else | |
3855 | break; | |
3856 | ||
3857 | /* If the constraints were not met, then | |
3858 | undo the replacement. */ | |
3859 | if (!n) | |
3860 | { | |
3861 | validate_replace_rtx (gen_rtx (code, mode, | |
3862 | reload_reg), | |
3863 | reload_reg, p); | |
3864 | break; | |
3865 | } | |
05d10675 | 3866 | |
f67c2384 | 3867 | } |
cb2afeb3 R |
3868 | break; |
3869 | } | |
3870 | if (n == 1) | |
02eb1393 R |
3871 | { |
3872 | REG_NOTES (p) | |
3873 | = gen_rtx_EXPR_LIST (REG_INC, reload_reg, | |
3874 | REG_NOTES (p)); | |
3875 | /* Mark this as having an output reload so that the | |
3876 | REG_INC processing code below won't invalidate | |
3877 | the reload for inheritance. */ | |
3878 | SET_HARD_REG_BIT (reg_is_output_reload, | |
3879 | REGNO (reload_reg)); | |
3880 | reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; | |
3881 | } | |
cb2afeb3 | 3882 | else |
84832317 MM |
3883 | forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX, |
3884 | NULL); | |
cb2afeb3 | 3885 | } |
02eb1393 R |
3886 | else if ((code == PRE_INC || code == PRE_DEC) |
3887 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 3888 | REGNO (rld[i].reg_rtx)) |
02eb1393 R |
3889 | /* Make sure it is the inc/dec pseudo, and not |
3890 | some other (e.g. output operand) pseudo. */ | |
eceef4c9 | 3891 | && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
02eb1393 R |
3892 | == REGNO (XEXP (in_reg, 0)))) |
3893 | { | |
3894 | SET_HARD_REG_BIT (reg_is_output_reload, | |
eceef4c9 | 3895 | REGNO (rld[i].reg_rtx)); |
02eb1393 R |
3896 | reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; |
3897 | } | |
cb2afeb3 R |
3898 | } |
3899 | } | |
02eb1393 R |
3900 | /* If a pseudo that got a hard register is auto-incremented, |
3901 | we must purge records of copying it into pseudos without | |
3902 | hard registers. */ | |
32131a9c RK |
3903 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) |
3904 | if (REG_NOTE_KIND (x) == REG_INC) | |
3905 | { | |
3906 | /* See if this pseudo reg was reloaded in this insn. | |
3907 | If so, its last-reload info is still valid | |
3908 | because it is based on this insn's reload. */ | |
3909 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 3910 | if (rld[i].out == XEXP (x, 0)) |
32131a9c RK |
3911 | break; |
3912 | ||
08fb99fa | 3913 | if (i == n_reloads) |
84832317 | 3914 | forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL); |
32131a9c RK |
3915 | } |
3916 | #endif | |
3917 | } | |
3918 | /* A reload reg's contents are unknown after a label. */ | |
3919 | if (GET_CODE (insn) == CODE_LABEL) | |
e6e52be0 | 3920 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
32131a9c RK |
3921 | |
3922 | /* Don't assume a reload reg is still good after a call insn | |
3923 | if it is a call-used reg. */ | |
546b63fb | 3924 | else if (GET_CODE (insn) == CALL_INSN) |
e6e52be0 | 3925 | AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set); |
32131a9c | 3926 | } |
ff154f78 MM |
3927 | |
3928 | /* Clean up. */ | |
3929 | free (reg_last_reload_reg); | |
3930 | free (reg_has_output_reload); | |
32131a9c RK |
3931 | } |
3932 | ||
3933 | /* Discard all record of any value reloaded from X, | |
3934 | or reloaded in X from someplace else; | |
3935 | unless X is an output reload reg of the current insn. | |
3936 | ||
3937 | X may be a hard reg (the reload reg) | |
3938 | or it may be a pseudo reg that was reloaded from. */ | |
3939 | ||
3940 | static void | |
84832317 | 3941 | forget_old_reloads_1 (x, ignored, data) |
32131a9c | 3942 | rtx x; |
487a6e06 | 3943 | rtx ignored ATTRIBUTE_UNUSED; |
84832317 | 3944 | void *data ATTRIBUTE_UNUSED; |
32131a9c RK |
3945 | { |
3946 | register int regno; | |
3947 | int nr; | |
0a2e51a9 RS |
3948 | int offset = 0; |
3949 | ||
3950 | /* note_stores does give us subregs of hard regs. */ | |
3951 | while (GET_CODE (x) == SUBREG) | |
3952 | { | |
3953 | offset += SUBREG_WORD (x); | |
3954 | x = SUBREG_REG (x); | |
3955 | } | |
32131a9c RK |
3956 | |
3957 | if (GET_CODE (x) != REG) | |
3958 | return; | |
3959 | ||
0a2e51a9 | 3960 | regno = REGNO (x) + offset; |
32131a9c RK |
3961 | |
3962 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3963 | nr = 1; | |
3964 | else | |
3965 | { | |
3966 | int i; | |
3967 | nr = HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
3968 | /* Storing into a spilled-reg invalidates its contents. | |
3969 | This can happen if a block-local pseudo is allocated to that reg | |
3970 | and it wasn't spilled because this block's total need is 0. | |
3971 | Then some insn might have an optional reload and use this reg. */ | |
3972 | for (i = 0; i < nr; i++) | |
e6e52be0 R |
3973 | /* But don't do this if the reg actually serves as an output |
3974 | reload reg in the current instruction. */ | |
3975 | if (n_reloads == 0 | |
3976 | || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)) | |
3977 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i); | |
32131a9c RK |
3978 | } |
3979 | ||
3980 | /* Since value of X has changed, | |
3981 | forget any value previously copied from it. */ | |
3982 | ||
3983 | while (nr-- > 0) | |
3984 | /* But don't forget a copy if this is the output reload | |
3985 | that establishes the copy's validity. */ | |
3986 | if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0) | |
3987 | reg_last_reload_reg[regno + nr] = 0; | |
3988 | } | |
3989 | \f | |
32131a9c RK |
3990 | /* The following HARD_REG_SETs indicate when each hard register is |
3991 | used for a reload of various parts of the current insn. */ | |
3992 | ||
9e3a9cf2 BS |
3993 | /* If reg is unavailable for all reloads. */ |
3994 | static HARD_REG_SET reload_reg_unavailable; | |
32131a9c RK |
3995 | /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ |
3996 | static HARD_REG_SET reload_reg_used; | |
546b63fb RK |
3997 | /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ |
3998 | static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
3999 | /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */ |
4000 | static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4001 | /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ |
4002 | static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4003 | /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */ |
4004 | static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4005 | /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ |
4006 | static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; | |
4007 | /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ | |
4008 | static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; | |
32131a9c RK |
4009 | /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ |
4010 | static HARD_REG_SET reload_reg_used_in_op_addr; | |
893bc853 RK |
4011 | /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */ |
4012 | static HARD_REG_SET reload_reg_used_in_op_addr_reload; | |
546b63fb RK |
4013 | /* If reg is in use for a RELOAD_FOR_INSN reload. */ |
4014 | static HARD_REG_SET reload_reg_used_in_insn; | |
4015 | /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ | |
4016 | static HARD_REG_SET reload_reg_used_in_other_addr; | |
32131a9c RK |
4017 | |
4018 | /* If reg is in use as a reload reg for any sort of reload. */ | |
4019 | static HARD_REG_SET reload_reg_used_at_all; | |
4020 | ||
be7ae2a4 RK |
4021 | /* If reg is use as an inherited reload. We just mark the first register |
4022 | in the group. */ | |
4023 | static HARD_REG_SET reload_reg_used_for_inherit; | |
4024 | ||
f1db3576 JL |
4025 | /* Records which hard regs are used in any way, either as explicit use or |
4026 | by being allocated to a pseudo during any point of the current insn. */ | |
4027 | static HARD_REG_SET reg_used_in_insn; | |
297927a8 | 4028 | |
546b63fb RK |
4029 | /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and |
4030 | TYPE. MODE is used to indicate how many consecutive regs are | |
4031 | actually used. */ | |
32131a9c RK |
4032 | |
4033 | static void | |
546b63fb | 4034 | mark_reload_reg_in_use (regno, opnum, type, mode) |
32131a9c | 4035 | int regno; |
546b63fb RK |
4036 | int opnum; |
4037 | enum reload_type type; | |
32131a9c RK |
4038 | enum machine_mode mode; |
4039 | { | |
4040 | int nregs = HARD_REGNO_NREGS (regno, mode); | |
4041 | int i; | |
4042 | ||
4043 | for (i = regno; i < nregs + regno; i++) | |
4044 | { | |
546b63fb | 4045 | switch (type) |
32131a9c RK |
4046 | { |
4047 | case RELOAD_OTHER: | |
4048 | SET_HARD_REG_BIT (reload_reg_used, i); | |
4049 | break; | |
4050 | ||
546b63fb RK |
4051 | case RELOAD_FOR_INPUT_ADDRESS: |
4052 | SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); | |
32131a9c RK |
4053 | break; |
4054 | ||
47c8cf91 ILT |
4055 | case RELOAD_FOR_INPADDR_ADDRESS: |
4056 | SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i); | |
4057 | break; | |
4058 | ||
546b63fb RK |
4059 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4060 | SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); | |
32131a9c RK |
4061 | break; |
4062 | ||
47c8cf91 ILT |
4063 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4064 | SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i); | |
4065 | break; | |
4066 | ||
32131a9c RK |
4067 | case RELOAD_FOR_OPERAND_ADDRESS: |
4068 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); | |
4069 | break; | |
4070 | ||
893bc853 RK |
4071 | case RELOAD_FOR_OPADDR_ADDR: |
4072 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i); | |
4073 | break; | |
4074 | ||
546b63fb RK |
4075 | case RELOAD_FOR_OTHER_ADDRESS: |
4076 | SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i); | |
4077 | break; | |
4078 | ||
32131a9c | 4079 | case RELOAD_FOR_INPUT: |
546b63fb | 4080 | SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); |
32131a9c RK |
4081 | break; |
4082 | ||
4083 | case RELOAD_FOR_OUTPUT: | |
546b63fb RK |
4084 | SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); |
4085 | break; | |
4086 | ||
4087 | case RELOAD_FOR_INSN: | |
4088 | SET_HARD_REG_BIT (reload_reg_used_in_insn, i); | |
32131a9c RK |
4089 | break; |
4090 | } | |
4091 | ||
4092 | SET_HARD_REG_BIT (reload_reg_used_at_all, i); | |
4093 | } | |
4094 | } | |
4095 | ||
be7ae2a4 RK |
4096 | /* Similarly, but show REGNO is no longer in use for a reload. */ |
4097 | ||
4098 | static void | |
4099 | clear_reload_reg_in_use (regno, opnum, type, mode) | |
4100 | int regno; | |
4101 | int opnum; | |
4102 | enum reload_type type; | |
4103 | enum machine_mode mode; | |
4104 | { | |
4105 | int nregs = HARD_REGNO_NREGS (regno, mode); | |
cb2afeb3 | 4106 | int start_regno, end_regno; |
be7ae2a4 | 4107 | int i; |
cb2afeb3 R |
4108 | /* A complication is that for some reload types, inheritance might |
4109 | allow multiple reloads of the same types to share a reload register. | |
4110 | We set check_opnum if we have to check only reloads with the same | |
4111 | operand number, and check_any if we have to check all reloads. */ | |
4112 | int check_opnum = 0; | |
4113 | int check_any = 0; | |
4114 | HARD_REG_SET *used_in_set; | |
be7ae2a4 | 4115 | |
cb2afeb3 | 4116 | switch (type) |
be7ae2a4 | 4117 | { |
cb2afeb3 R |
4118 | case RELOAD_OTHER: |
4119 | used_in_set = &reload_reg_used; | |
4120 | break; | |
be7ae2a4 | 4121 | |
cb2afeb3 R |
4122 | case RELOAD_FOR_INPUT_ADDRESS: |
4123 | used_in_set = &reload_reg_used_in_input_addr[opnum]; | |
4124 | break; | |
be7ae2a4 | 4125 | |
cb2afeb3 R |
4126 | case RELOAD_FOR_INPADDR_ADDRESS: |
4127 | check_opnum = 1; | |
4128 | used_in_set = &reload_reg_used_in_inpaddr_addr[opnum]; | |
4129 | break; | |
47c8cf91 | 4130 | |
cb2afeb3 R |
4131 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4132 | used_in_set = &reload_reg_used_in_output_addr[opnum]; | |
4133 | break; | |
be7ae2a4 | 4134 | |
cb2afeb3 R |
4135 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4136 | check_opnum = 1; | |
4137 | used_in_set = &reload_reg_used_in_outaddr_addr[opnum]; | |
4138 | break; | |
47c8cf91 | 4139 | |
cb2afeb3 R |
4140 | case RELOAD_FOR_OPERAND_ADDRESS: |
4141 | used_in_set = &reload_reg_used_in_op_addr; | |
4142 | break; | |
be7ae2a4 | 4143 | |
cb2afeb3 R |
4144 | case RELOAD_FOR_OPADDR_ADDR: |
4145 | check_any = 1; | |
4146 | used_in_set = &reload_reg_used_in_op_addr_reload; | |
4147 | break; | |
893bc853 | 4148 | |
cb2afeb3 R |
4149 | case RELOAD_FOR_OTHER_ADDRESS: |
4150 | used_in_set = &reload_reg_used_in_other_addr; | |
4151 | check_any = 1; | |
4152 | break; | |
be7ae2a4 | 4153 | |
cb2afeb3 R |
4154 | case RELOAD_FOR_INPUT: |
4155 | used_in_set = &reload_reg_used_in_input[opnum]; | |
4156 | break; | |
be7ae2a4 | 4157 | |
cb2afeb3 R |
4158 | case RELOAD_FOR_OUTPUT: |
4159 | used_in_set = &reload_reg_used_in_output[opnum]; | |
4160 | break; | |
be7ae2a4 | 4161 | |
cb2afeb3 R |
4162 | case RELOAD_FOR_INSN: |
4163 | used_in_set = &reload_reg_used_in_insn; | |
4164 | break; | |
4165 | default: | |
4166 | abort (); | |
4167 | } | |
4168 | /* We resolve conflicts with remaining reloads of the same type by | |
4169 | excluding the intervals of of reload registers by them from the | |
4170 | interval of freed reload registers. Since we only keep track of | |
4171 | one set of interval bounds, we might have to exclude somewhat | |
4172 | more then what would be necessary if we used a HARD_REG_SET here. | |
4173 | But this should only happen very infrequently, so there should | |
4174 | be no reason to worry about it. */ | |
05d10675 | 4175 | |
cb2afeb3 R |
4176 | start_regno = regno; |
4177 | end_regno = regno + nregs; | |
4178 | if (check_opnum || check_any) | |
4179 | { | |
4180 | for (i = n_reloads - 1; i >= 0; i--) | |
4181 | { | |
eceef4c9 BS |
4182 | if (rld[i].when_needed == type |
4183 | && (check_any || rld[i].opnum == opnum) | |
4184 | && rld[i].reg_rtx) | |
cb2afeb3 | 4185 | { |
eceef4c9 | 4186 | int conflict_start = true_regnum (rld[i].reg_rtx); |
cb2afeb3 R |
4187 | int conflict_end |
4188 | = (conflict_start | |
8ec450a4 | 4189 | + HARD_REGNO_NREGS (conflict_start, rld[i].mode)); |
cb2afeb3 R |
4190 | |
4191 | /* If there is an overlap with the first to-be-freed register, | |
4192 | adjust the interval start. */ | |
4193 | if (conflict_start <= start_regno && conflict_end > start_regno) | |
4194 | start_regno = conflict_end; | |
4195 | /* Otherwise, if there is a conflict with one of the other | |
4196 | to-be-freed registers, adjust the interval end. */ | |
4197 | if (conflict_start > start_regno && conflict_start < end_regno) | |
4198 | end_regno = conflict_start; | |
4199 | } | |
be7ae2a4 RK |
4200 | } |
4201 | } | |
cb2afeb3 R |
4202 | for (i = start_regno; i < end_regno; i++) |
4203 | CLEAR_HARD_REG_BIT (*used_in_set, i); | |
be7ae2a4 RK |
4204 | } |
4205 | ||
32131a9c | 4206 | /* 1 if reg REGNO is free as a reload reg for a reload of the sort |
546b63fb | 4207 | specified by OPNUM and TYPE. */ |
32131a9c RK |
4208 | |
4209 | static int | |
546b63fb | 4210 | reload_reg_free_p (regno, opnum, type) |
32131a9c | 4211 | int regno; |
546b63fb RK |
4212 | int opnum; |
4213 | enum reload_type type; | |
32131a9c | 4214 | { |
546b63fb RK |
4215 | int i; |
4216 | ||
2edc8d65 | 4217 | /* In use for a RELOAD_OTHER means it's not available for anything. */ |
9e3a9cf2 BS |
4218 | if (TEST_HARD_REG_BIT (reload_reg_used, regno) |
4219 | || TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) | |
32131a9c | 4220 | return 0; |
546b63fb RK |
4221 | |
4222 | switch (type) | |
32131a9c RK |
4223 | { |
4224 | case RELOAD_OTHER: | |
2edc8d65 RK |
4225 | /* In use for anything means we can't use it for RELOAD_OTHER. */ |
4226 | if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) | |
224f1d71 RK |
4227 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4228 | || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) | |
4229 | return 0; | |
4230 | ||
4231 | for (i = 0; i < reload_n_operands; i++) | |
4232 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4233 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
224f1d71 | 4234 | || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
47c8cf91 | 4235 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
224f1d71 RK |
4236 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) |
4237 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4238 | return 0; | |
4239 | ||
4240 | return 1; | |
32131a9c | 4241 | |
32131a9c | 4242 | case RELOAD_FOR_INPUT: |
546b63fb RK |
4243 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) |
4244 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) | |
4245 | return 0; | |
4246 | ||
893bc853 RK |
4247 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4248 | return 0; | |
4249 | ||
546b63fb RK |
4250 | /* If it is used for some other input, can't use it. */ |
4251 | for (i = 0; i < reload_n_operands; i++) | |
4252 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4253 | return 0; | |
4254 | ||
4255 | /* If it is used in a later operand's address, can't use it. */ | |
4256 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4257 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4258 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4259 | return 0; |
4260 | ||
4261 | return 1; | |
4262 | ||
4263 | case RELOAD_FOR_INPUT_ADDRESS: | |
4264 | /* Can't use a register if it is used for an input address for this | |
4265 | operand or used as an input in an earlier one. */ | |
47c8cf91 ILT |
4266 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno) |
4267 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) | |
4268 | return 0; | |
4269 | ||
4270 | for (i = 0; i < opnum; i++) | |
4271 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4272 | return 0; | |
4273 | ||
4274 | return 1; | |
4275 | ||
4276 | case RELOAD_FOR_INPADDR_ADDRESS: | |
4277 | /* Can't use a register if it is used for an input address | |
05d10675 BS |
4278 | for this operand or used as an input in an earlier |
4279 | one. */ | |
47c8cf91 | 4280 | if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) |
546b63fb RK |
4281 | return 0; |
4282 | ||
4283 | for (i = 0; i < opnum; i++) | |
4284 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4285 | return 0; | |
4286 | ||
4287 | return 1; | |
4288 | ||
4289 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
4290 | /* Can't use a register if it is used for an output address for this | |
4291 | operand or used as an output in this or a later operand. */ | |
4292 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) | |
4293 | return 0; | |
4294 | ||
4295 | for (i = opnum; i < reload_n_operands; i++) | |
4296 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4297 | return 0; | |
4298 | ||
4299 | return 1; | |
4300 | ||
47c8cf91 ILT |
4301 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4302 | /* Can't use a register if it is used for an output address | |
05d10675 BS |
4303 | for this operand or used as an output in this or a |
4304 | later operand. */ | |
47c8cf91 ILT |
4305 | if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) |
4306 | return 0; | |
4307 | ||
4308 | for (i = opnum; i < reload_n_operands; i++) | |
4309 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4310 | return 0; | |
4311 | ||
4312 | return 1; | |
4313 | ||
32131a9c | 4314 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4315 | for (i = 0; i < reload_n_operands; i++) |
4316 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4317 | return 0; | |
4318 | ||
4319 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4320 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4321 | ||
893bc853 RK |
4322 | case RELOAD_FOR_OPADDR_ADDR: |
4323 | for (i = 0; i < reload_n_operands; i++) | |
05d10675 BS |
4324 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4325 | return 0; | |
893bc853 | 4326 | |
a94ce333 | 4327 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)); |
893bc853 | 4328 | |
32131a9c | 4329 | case RELOAD_FOR_OUTPUT: |
546b63fb RK |
4330 | /* This cannot share a register with RELOAD_FOR_INSN reloads, other |
4331 | outputs, or an operand address for this or an earlier output. */ | |
4332 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) | |
4333 | return 0; | |
4334 | ||
4335 | for (i = 0; i < reload_n_operands; i++) | |
4336 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4337 | return 0; | |
4338 | ||
4339 | for (i = 0; i <= opnum; i++) | |
47c8cf91 ILT |
4340 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4341 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4342 | return 0; |
4343 | ||
4344 | return 1; | |
4345 | ||
4346 | case RELOAD_FOR_INSN: | |
4347 | for (i = 0; i < reload_n_operands; i++) | |
4348 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) | |
4349 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4350 | return 0; | |
4351 | ||
4352 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4353 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4354 | ||
4355 | case RELOAD_FOR_OTHER_ADDRESS: | |
4356 | return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); | |
32131a9c RK |
4357 | } |
4358 | abort (); | |
4359 | } | |
4360 | ||
32131a9c | 4361 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
546b63fb | 4362 | needed for the part of the insn specified by OPNUM and TYPE, |
32131a9c RK |
4363 | is still available in REGNO at the end of the insn. |
4364 | ||
4365 | We can assume that the reload reg was already tested for availability | |
4366 | at the time it is needed, and we should not check this again, | |
4367 | in case the reg has already been marked in use. */ | |
4368 | ||
4369 | static int | |
546b63fb | 4370 | reload_reg_reaches_end_p (regno, opnum, type) |
32131a9c | 4371 | int regno; |
546b63fb RK |
4372 | int opnum; |
4373 | enum reload_type type; | |
32131a9c | 4374 | { |
546b63fb RK |
4375 | int i; |
4376 | ||
4377 | switch (type) | |
32131a9c RK |
4378 | { |
4379 | case RELOAD_OTHER: | |
4380 | /* Since a RELOAD_OTHER reload claims the reg for the entire insn, | |
4381 | its value must reach the end. */ | |
4382 | return 1; | |
4383 | ||
4384 | /* If this use is for part of the insn, | |
05d10675 | 4385 | its value reaches if no subsequent part uses the same register. |
546b63fb RK |
4386 | Just like the above function, don't try to do this with lots |
4387 | of fallthroughs. */ | |
4388 | ||
4389 | case RELOAD_FOR_OTHER_ADDRESS: | |
4390 | /* Here we check for everything else, since these don't conflict | |
4391 | with anything else and everything comes later. */ | |
4392 | ||
4393 | for (i = 0; i < reload_n_operands; i++) | |
4394 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4395 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4396 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) |
4397 | || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4398 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4399 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4400 | return 0; | |
4401 | ||
4402 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) | |
4403 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4404 | && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
4405 | ||
4406 | case RELOAD_FOR_INPUT_ADDRESS: | |
47c8cf91 | 4407 | case RELOAD_FOR_INPADDR_ADDRESS: |
546b63fb RK |
4408 | /* Similar, except that we check only for this and subsequent inputs |
4409 | and the address of only subsequent inputs and we do not need | |
4410 | to check for RELOAD_OTHER objects since they are known not to | |
4411 | conflict. */ | |
4412 | ||
4413 | for (i = opnum; i < reload_n_operands; i++) | |
4414 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4415 | return 0; | |
4416 | ||
4417 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4418 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4419 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4420 | return 0; |
4421 | ||
4422 | for (i = 0; i < reload_n_operands; i++) | |
4423 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4424 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4425 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4426 | return 0; | |
4427 | ||
893bc853 RK |
4428 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4429 | return 0; | |
4430 | ||
546b63fb RK |
4431 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4432 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)); | |
4433 | ||
32131a9c | 4434 | case RELOAD_FOR_INPUT: |
546b63fb | 4435 | /* Similar to input address, except we start at the next operand for |
05d10675 | 4436 | both input and input address and we do not check for |
546b63fb RK |
4437 | RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these |
4438 | would conflict. */ | |
4439 | ||
4440 | for (i = opnum + 1; i < reload_n_operands; i++) | |
4441 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4442 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4443 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4444 | return 0; | |
4445 | ||
0f41302f | 4446 | /* ... fall through ... */ |
546b63fb | 4447 | |
32131a9c | 4448 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4449 | /* Check outputs and their addresses. */ |
4450 | ||
4451 | for (i = 0; i < reload_n_operands; i++) | |
4452 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4453 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4454 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4455 | return 0; | |
4456 | ||
4457 | return 1; | |
4458 | ||
893bc853 RK |
4459 | case RELOAD_FOR_OPADDR_ADDR: |
4460 | for (i = 0; i < reload_n_operands; i++) | |
4461 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4462 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
893bc853 RK |
4463 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4464 | return 0; | |
4465 | ||
a94ce333 JW |
4466 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4467 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)); | |
893bc853 | 4468 | |
546b63fb | 4469 | case RELOAD_FOR_INSN: |
893bc853 | 4470 | /* These conflict with other outputs with RELOAD_OTHER. So |
546b63fb RK |
4471 | we need only check for output addresses. */ |
4472 | ||
4473 | opnum = -1; | |
4474 | ||
0f41302f | 4475 | /* ... fall through ... */ |
546b63fb | 4476 | |
32131a9c | 4477 | case RELOAD_FOR_OUTPUT: |
546b63fb | 4478 | case RELOAD_FOR_OUTPUT_ADDRESS: |
47c8cf91 | 4479 | case RELOAD_FOR_OUTADDR_ADDRESS: |
546b63fb RK |
4480 | /* We already know these can't conflict with a later output. So the |
4481 | only thing to check are later output addresses. */ | |
4482 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4483 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4484 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4485 | return 0; |
4486 | ||
32131a9c RK |
4487 | return 1; |
4488 | } | |
546b63fb | 4489 | |
32131a9c RK |
4490 | abort (); |
4491 | } | |
4492 | \f | |
351aa1c1 RK |
4493 | /* Return 1 if the reloads denoted by R1 and R2 cannot share a register. |
4494 | Return 0 otherwise. | |
4495 | ||
4496 | This function uses the same algorithm as reload_reg_free_p above. */ | |
4497 | ||
f5963e61 | 4498 | int |
351aa1c1 RK |
4499 | reloads_conflict (r1, r2) |
4500 | int r1, r2; | |
4501 | { | |
eceef4c9 BS |
4502 | enum reload_type r1_type = rld[r1].when_needed; |
4503 | enum reload_type r2_type = rld[r2].when_needed; | |
4504 | int r1_opnum = rld[r1].opnum; | |
4505 | int r2_opnum = rld[r2].opnum; | |
351aa1c1 | 4506 | |
2edc8d65 RK |
4507 | /* RELOAD_OTHER conflicts with everything. */ |
4508 | if (r2_type == RELOAD_OTHER) | |
351aa1c1 RK |
4509 | return 1; |
4510 | ||
4511 | /* Otherwise, check conflicts differently for each type. */ | |
4512 | ||
4513 | switch (r1_type) | |
4514 | { | |
4515 | case RELOAD_FOR_INPUT: | |
05d10675 | 4516 | return (r2_type == RELOAD_FOR_INSN |
351aa1c1 | 4517 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS |
893bc853 | 4518 | || r2_type == RELOAD_FOR_OPADDR_ADDR |
351aa1c1 | 4519 | || r2_type == RELOAD_FOR_INPUT |
47c8cf91 ILT |
4520 | || ((r2_type == RELOAD_FOR_INPUT_ADDRESS |
4521 | || r2_type == RELOAD_FOR_INPADDR_ADDRESS) | |
4522 | && r2_opnum > r1_opnum)); | |
351aa1c1 RK |
4523 | |
4524 | case RELOAD_FOR_INPUT_ADDRESS: | |
4525 | return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum) | |
4526 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
4527 | ||
47c8cf91 ILT |
4528 | case RELOAD_FOR_INPADDR_ADDRESS: |
4529 | return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum) | |
4530 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
4531 | ||
351aa1c1 RK |
4532 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4533 | return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum) | |
4534 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum)); | |
4535 | ||
47c8cf91 ILT |
4536 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4537 | return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum) | |
4538 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum)); | |
4539 | ||
351aa1c1 RK |
4540 | case RELOAD_FOR_OPERAND_ADDRESS: |
4541 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN | |
a94ce333 | 4542 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); |
351aa1c1 | 4543 | |
893bc853 | 4544 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 | 4545 | return (r2_type == RELOAD_FOR_INPUT |
a94ce333 | 4546 | || r2_type == RELOAD_FOR_OPADDR_ADDR); |
893bc853 | 4547 | |
351aa1c1 RK |
4548 | case RELOAD_FOR_OUTPUT: |
4549 | return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT | |
47c8cf91 ILT |
4550 | || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS |
4551 | || r2_type == RELOAD_FOR_OUTADDR_ADDRESS) | |
ca1a4af1 | 4552 | && r2_opnum <= r1_opnum)); |
351aa1c1 RK |
4553 | |
4554 | case RELOAD_FOR_INSN: | |
4555 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT | |
4556 | || r2_type == RELOAD_FOR_INSN | |
4557 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); | |
4558 | ||
4559 | case RELOAD_FOR_OTHER_ADDRESS: | |
4560 | return r2_type == RELOAD_FOR_OTHER_ADDRESS; | |
4561 | ||
adab4fc5 | 4562 | case RELOAD_OTHER: |
2edc8d65 | 4563 | return 1; |
adab4fc5 | 4564 | |
351aa1c1 RK |
4565 | default: |
4566 | abort (); | |
4567 | } | |
4568 | } | |
4569 | \f | |
32131a9c RK |
4570 | /* Indexed by reload number, 1 if incoming value |
4571 | inherited from previous insns. */ | |
4572 | char reload_inherited[MAX_RELOADS]; | |
4573 | ||
4574 | /* For an inherited reload, this is the insn the reload was inherited from, | |
4575 | if we know it. Otherwise, this is 0. */ | |
4576 | rtx reload_inheritance_insn[MAX_RELOADS]; | |
4577 | ||
4578 | /* If non-zero, this is a place to get the value of the reload, | |
4579 | rather than using reload_in. */ | |
4580 | rtx reload_override_in[MAX_RELOADS]; | |
4581 | ||
e6e52be0 R |
4582 | /* For each reload, the hard register number of the register used, |
4583 | or -1 if we did not need a register for this reload. */ | |
32131a9c RK |
4584 | int reload_spill_index[MAX_RELOADS]; |
4585 | ||
6e684430 R |
4586 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
4587 | needed for the part of the insn specified by OPNUM and TYPE, | |
4588 | may be used to load VALUE into it. | |
f5470689 R |
4589 | |
4590 | Other read-only reloads with the same value do not conflict | |
4591 | unless OUT is non-zero and these other reloads have to live while | |
4592 | output reloads live. | |
dfe96118 R |
4593 | If OUT is CONST0_RTX, this is a special case: it means that the |
4594 | test should not be for using register REGNO as reload register, but | |
4595 | for copying from register REGNO into the reload register. | |
f5470689 R |
4596 | |
4597 | RELOADNUM is the number of the reload we want to load this value for; | |
4598 | a reload does not conflict with itself. | |
4599 | ||
dfe96118 R |
4600 | When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with |
4601 | reloads that load an address for the very reload we are considering. | |
4602 | ||
6e684430 R |
4603 | The caller has to make sure that there is no conflict with the return |
4604 | register. */ | |
4605 | static int | |
dfe96118 | 4606 | reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum, |
05d10675 | 4607 | ignore_address_reloads) |
6e684430 R |
4608 | int regno; |
4609 | int opnum; | |
4610 | enum reload_type type; | |
f5470689 R |
4611 | rtx value, out; |
4612 | int reloadnum; | |
5828374f | 4613 | int ignore_address_reloads; |
6e684430 R |
4614 | { |
4615 | int time1; | |
09a308fe R |
4616 | /* Set if we see an input reload that must not share its reload register |
4617 | with any new earlyclobber, but might otherwise share the reload | |
4618 | register with an output or input-output reload. */ | |
4619 | int check_earlyclobber = 0; | |
6e684430 | 4620 | int i; |
dfe96118 R |
4621 | int copy = 0; |
4622 | ||
9e3a9cf2 | 4623 | if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) |
dc8842bf AH |
4624 | return 0; |
4625 | ||
dfe96118 R |
4626 | if (out == const0_rtx) |
4627 | { | |
4628 | copy = 1; | |
4629 | out = NULL_RTX; | |
4630 | } | |
6e684430 R |
4631 | |
4632 | /* We use some pseudo 'time' value to check if the lifetimes of the | |
4633 | new register use would overlap with the one of a previous reload | |
4634 | that is not read-only or uses a different value. | |
4635 | The 'time' used doesn't have to be linear in any shape or form, just | |
4636 | monotonic. | |
4637 | Some reload types use different 'buckets' for each operand. | |
4638 | So there are MAX_RECOG_OPERANDS different time values for each | |
cecbf6e2 R |
4639 | such reload type. |
4640 | We compute TIME1 as the time when the register for the prospective | |
4641 | new reload ceases to be live, and TIME2 for each existing | |
4642 | reload as the time when that the reload register of that reload | |
4643 | becomes live. | |
4644 | Where there is little to be gained by exact lifetime calculations, | |
4645 | we just make conservative assumptions, i.e. a longer lifetime; | |
4646 | this is done in the 'default:' cases. */ | |
6e684430 R |
4647 | switch (type) |
4648 | { | |
4649 | case RELOAD_FOR_OTHER_ADDRESS: | |
203588e7 | 4650 | /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */ |
c2b4b171 | 4651 | time1 = copy ? 0 : 1; |
6e684430 | 4652 | break; |
dfe96118 R |
4653 | case RELOAD_OTHER: |
4654 | time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5; | |
4655 | break; | |
05d10675 BS |
4656 | /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS, |
4657 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 , | |
4658 | respectively, to the time values for these, we get distinct time | |
4659 | values. To get distinct time values for each operand, we have to | |
4660 | multiply opnum by at least three. We round that up to four because | |
4661 | multiply by four is often cheaper. */ | |
6e684430 | 4662 | case RELOAD_FOR_INPADDR_ADDRESS: |
dfe96118 | 4663 | time1 = opnum * 4 + 2; |
6e684430 R |
4664 | break; |
4665 | case RELOAD_FOR_INPUT_ADDRESS: | |
dfe96118 R |
4666 | time1 = opnum * 4 + 3; |
4667 | break; | |
4668 | case RELOAD_FOR_INPUT: | |
4669 | /* All RELOAD_FOR_INPUT reloads remain live till the instruction | |
4670 | executes (inclusive). */ | |
4671 | time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3; | |
6e684430 | 4672 | break; |
cb2afeb3 | 4673 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 BS |
4674 | /* opnum * 4 + 4 |
4675 | <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */ | |
cb2afeb3 R |
4676 | time1 = MAX_RECOG_OPERANDS * 4 + 1; |
4677 | break; | |
4678 | case RELOAD_FOR_OPERAND_ADDRESS: | |
4679 | /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn | |
4680 | is executed. */ | |
dfe96118 R |
4681 | time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3; |
4682 | break; | |
4683 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
4684 | time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum; | |
6e684430 | 4685 | break; |
6e684430 | 4686 | case RELOAD_FOR_OUTPUT_ADDRESS: |
dfe96118 | 4687 | time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum; |
6e684430 R |
4688 | break; |
4689 | default: | |
dfe96118 | 4690 | time1 = MAX_RECOG_OPERANDS * 5 + 5; |
6e684430 R |
4691 | } |
4692 | ||
4693 | for (i = 0; i < n_reloads; i++) | |
4694 | { | |
eceef4c9 | 4695 | rtx reg = rld[i].reg_rtx; |
6e684430 R |
4696 | if (reg && GET_CODE (reg) == REG |
4697 | && ((unsigned) regno - true_regnum (reg) | |
83e0821b | 4698 | <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1) |
f5470689 | 4699 | && i != reloadnum) |
6e684430 | 4700 | { |
eceef4c9 BS |
4701 | if (! rld[i].in || ! rtx_equal_p (rld[i].in, value) |
4702 | || rld[i].out || out) | |
6e684430 | 4703 | { |
09a308fe | 4704 | int time2; |
eceef4c9 | 4705 | switch (rld[i].when_needed) |
f5470689 R |
4706 | { |
4707 | case RELOAD_FOR_OTHER_ADDRESS: | |
4708 | time2 = 0; | |
4709 | break; | |
4710 | case RELOAD_FOR_INPADDR_ADDRESS: | |
cb2afeb3 R |
4711 | /* find_reloads makes sure that a |
4712 | RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used | |
4713 | by at most one - the first - | |
4714 | RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the | |
4715 | address reload is inherited, the address address reload | |
4716 | goes away, so we can ignore this conflict. */ | |
dfe96118 R |
4717 | if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1 |
4718 | && ignore_address_reloads | |
4719 | /* Unless the RELOAD_FOR_INPUT is an auto_inc expression. | |
4720 | Then the address address is still needed to store | |
4721 | back the new address. */ | |
eceef4c9 | 4722 | && ! rld[reloadnum].out) |
cb2afeb3 | 4723 | continue; |
dfe96118 R |
4724 | /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its |
4725 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS | |
4726 | reloads go away. */ | |
eceef4c9 | 4727 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 R |
4728 | && ignore_address_reloads |
4729 | /* Unless we are reloading an auto_inc expression. */ | |
eceef4c9 | 4730 | && ! rld[reloadnum].out) |
dfe96118 | 4731 | continue; |
eceef4c9 | 4732 | time2 = rld[i].opnum * 4 + 2; |
f5470689 R |
4733 | break; |
4734 | case RELOAD_FOR_INPUT_ADDRESS: | |
eceef4c9 | 4735 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 | 4736 | && ignore_address_reloads |
eceef4c9 | 4737 | && ! rld[reloadnum].out) |
dfe96118 | 4738 | continue; |
eceef4c9 | 4739 | time2 = rld[i].opnum * 4 + 3; |
f5470689 R |
4740 | break; |
4741 | case RELOAD_FOR_INPUT: | |
eceef4c9 | 4742 | time2 = rld[i].opnum * 4 + 4; |
09a308fe | 4743 | check_earlyclobber = 1; |
f5470689 | 4744 | break; |
eceef4c9 | 4745 | /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4 |
05d10675 | 4746 | == MAX_RECOG_OPERAND * 4 */ |
cb2afeb3 | 4747 | case RELOAD_FOR_OPADDR_ADDR: |
dfe96118 R |
4748 | if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1 |
4749 | && ignore_address_reloads | |
eceef4c9 | 4750 | && ! rld[reloadnum].out) |
cb2afeb3 | 4751 | continue; |
dfe96118 | 4752 | time2 = MAX_RECOG_OPERANDS * 4 + 1; |
cb2afeb3 R |
4753 | break; |
4754 | case RELOAD_FOR_OPERAND_ADDRESS: | |
dfe96118 | 4755 | time2 = MAX_RECOG_OPERANDS * 4 + 2; |
09a308fe | 4756 | check_earlyclobber = 1; |
dfe96118 R |
4757 | break; |
4758 | case RELOAD_FOR_INSN: | |
4759 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
cb2afeb3 | 4760 | break; |
f5470689 | 4761 | case RELOAD_FOR_OUTPUT: |
05d10675 BS |
4762 | /* All RELOAD_FOR_OUTPUT reloads become live just after the |
4763 | instruction is executed. */ | |
dfe96118 | 4764 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
f5470689 | 4765 | break; |
05d10675 BS |
4766 | /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with |
4767 | the RELOAD_FOR_OUTPUT reloads, so assign it the same time | |
4768 | value. */ | |
cb2afeb3 | 4769 | case RELOAD_FOR_OUTADDR_ADDRESS: |
dfe96118 R |
4770 | if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1 |
4771 | && ignore_address_reloads | |
eceef4c9 | 4772 | && ! rld[reloadnum].out) |
cb2afeb3 | 4773 | continue; |
eceef4c9 | 4774 | time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum; |
dfe96118 | 4775 | break; |
f5470689 | 4776 | case RELOAD_FOR_OUTPUT_ADDRESS: |
eceef4c9 | 4777 | time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum; |
f5470689 R |
4778 | break; |
4779 | case RELOAD_OTHER: | |
dfe96118 R |
4780 | /* If there is no conflict in the input part, handle this |
4781 | like an output reload. */ | |
eceef4c9 | 4782 | if (! rld[i].in || rtx_equal_p (rld[i].in, value)) |
f5470689 | 4783 | { |
dfe96118 | 4784 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
57850c85 | 4785 | /* Earlyclobbered outputs must conflict with inputs. */ |
09a308fe R |
4786 | if (earlyclobber_operand_p (rld[i].out)) |
4787 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
57850c85 | 4788 | |
f5470689 R |
4789 | break; |
4790 | } | |
dfe96118 R |
4791 | time2 = 1; |
4792 | /* RELOAD_OTHER might be live beyond instruction execution, | |
4793 | but this is not obvious when we set time2 = 1. So check | |
4794 | here if there might be a problem with the new reload | |
4795 | clobbering the register used by the RELOAD_OTHER. */ | |
4796 | if (out) | |
4797 | return 0; | |
4798 | break; | |
f5470689 | 4799 | default: |
dfe96118 | 4800 | return 0; |
f5470689 | 4801 | } |
25963977 | 4802 | if ((time1 >= time2 |
eceef4c9 BS |
4803 | && (! rld[i].in || rld[i].out |
4804 | || ! rtx_equal_p (rld[i].in, value))) | |
4805 | || (out && rld[reloadnum].out_reg | |
701d55e8 | 4806 | && time2 >= MAX_RECOG_OPERANDS * 4 + 3)) |
f5470689 | 4807 | return 0; |
6e684430 | 4808 | } |
6e684430 R |
4809 | } |
4810 | } | |
09a308fe R |
4811 | |
4812 | /* Earlyclobbered outputs must conflict with inputs. */ | |
4813 | if (check_earlyclobber && out && earlyclobber_operand_p (out)) | |
4814 | return 0; | |
4815 | ||
6e684430 R |
4816 | return 1; |
4817 | } | |
4818 | ||
67e61fe7 BS |
4819 | /* Give an error message saying we failed to find a reload for INSN, |
4820 | and clear out reload R. */ | |
4821 | static void | |
4822 | failed_reload (insn, r) | |
4823 | rtx insn; | |
4824 | int r; | |
4825 | { | |
4826 | if (asm_noperands (PATTERN (insn)) < 0) | |
4827 | /* It's the compiler's fault. */ | |
4828 | fatal_insn ("Could not find a spill register", insn); | |
4829 | ||
4830 | /* It's the user's fault; the operand's mode and constraint | |
4831 | don't match. Disable this reload so we don't crash in final. */ | |
4832 | error_for_asm (insn, | |
4833 | "`asm' operand constraint incompatible with operand size"); | |
4834 | rld[r].in = 0; | |
4835 | rld[r].out = 0; | |
4836 | rld[r].reg_rtx = 0; | |
4837 | rld[r].optional = 1; | |
4838 | rld[r].secondary_p = 1; | |
4839 | } | |
4840 | ||
4841 | /* I is the index in SPILL_REG_RTX of the reload register we are to allocate | |
4842 | for reload R. If it's valid, get an rtx for it. Return nonzero if | |
4843 | successful. */ | |
4844 | static int | |
4845 | set_reload_reg (i, r) | |
4846 | int i, r; | |
4847 | { | |
4848 | int regno; | |
4849 | rtx reg = spill_reg_rtx[i]; | |
4850 | ||
4851 | if (reg == 0 || GET_MODE (reg) != rld[r].mode) | |
4852 | spill_reg_rtx[i] = reg | |
4853 | = gen_rtx_REG (rld[r].mode, spill_regs[i]); | |
4854 | ||
4855 | regno = true_regnum (reg); | |
4856 | ||
4857 | /* Detect when the reload reg can't hold the reload mode. | |
4858 | This used to be one `if', but Sequent compiler can't handle that. */ | |
4859 | if (HARD_REGNO_MODE_OK (regno, rld[r].mode)) | |
4860 | { | |
4861 | enum machine_mode test_mode = VOIDmode; | |
4862 | if (rld[r].in) | |
4863 | test_mode = GET_MODE (rld[r].in); | |
4864 | /* If rld[r].in has VOIDmode, it means we will load it | |
4865 | in whatever mode the reload reg has: to wit, rld[r].mode. | |
4866 | We have already tested that for validity. */ | |
4867 | /* Aside from that, we need to test that the expressions | |
4868 | to reload from or into have modes which are valid for this | |
4869 | reload register. Otherwise the reload insns would be invalid. */ | |
4870 | if (! (rld[r].in != 0 && test_mode != VOIDmode | |
4871 | && ! HARD_REGNO_MODE_OK (regno, test_mode))) | |
4872 | if (! (rld[r].out != 0 | |
4873 | && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out)))) | |
4874 | { | |
4875 | /* The reg is OK. */ | |
4876 | last_spill_reg = i; | |
4877 | ||
4878 | /* Mark as in use for this insn the reload regs we use | |
4879 | for this. */ | |
4880 | mark_reload_reg_in_use (spill_regs[i], rld[r].opnum, | |
4881 | rld[r].when_needed, rld[r].mode); | |
4882 | ||
4883 | rld[r].reg_rtx = reg; | |
4884 | reload_spill_index[r] = spill_regs[i]; | |
4885 | return 1; | |
4886 | } | |
4887 | } | |
4888 | return 0; | |
4889 | } | |
4890 | ||
32131a9c RK |
4891 | /* Find a spill register to use as a reload register for reload R. |
4892 | LAST_RELOAD is non-zero if this is the last reload for the insn being | |
4893 | processed. | |
4894 | ||
eceef4c9 | 4895 | Set rld[R].reg_rtx to the register allocated. |
32131a9c | 4896 | |
f5d8c9f4 BS |
4897 | We return 1 if successful, or 0 if we couldn't find a spill reg and |
4898 | we didn't change anything. */ | |
32131a9c RK |
4899 | |
4900 | static int | |
f5d8c9f4 | 4901 | allocate_reload_reg (chain, r, last_reload) |
272df862 | 4902 | struct insn_chain *chain ATTRIBUTE_UNUSED; |
32131a9c | 4903 | int r; |
32131a9c | 4904 | int last_reload; |
32131a9c | 4905 | { |
67e61fe7 | 4906 | int i, pass, count; |
32131a9c RK |
4907 | |
4908 | /* If we put this reload ahead, thinking it is a group, | |
4909 | then insist on finding a group. Otherwise we can grab a | |
a8fdc208 | 4910 | reg that some other reload needs. |
32131a9c RK |
4911 | (That can happen when we have a 68000 DATA_OR_FP_REG |
4912 | which is a group of data regs or one fp reg.) | |
4913 | We need not be so restrictive if there are no more reloads | |
4914 | for this insn. | |
4915 | ||
4916 | ??? Really it would be nicer to have smarter handling | |
4917 | for that kind of reg class, where a problem like this is normal. | |
4918 | Perhaps those classes should be avoided for reloading | |
4919 | by use of more alternatives. */ | |
4920 | ||
8ec450a4 | 4921 | int force_group = rld[r].nregs > 1 && ! last_reload; |
32131a9c RK |
4922 | |
4923 | /* If we want a single register and haven't yet found one, | |
4924 | take any reg in the right class and not in use. | |
4925 | If we want a consecutive group, here is where we look for it. | |
4926 | ||
4927 | We use two passes so we can first look for reload regs to | |
4928 | reuse, which are already in use for other reloads in this insn, | |
4929 | and only then use additional registers. | |
4930 | I think that maximizing reuse is needed to make sure we don't | |
4931 | run out of reload regs. Suppose we have three reloads, and | |
4932 | reloads A and B can share regs. These need two regs. | |
4933 | Suppose A and B are given different regs. | |
4934 | That leaves none for C. */ | |
4935 | for (pass = 0; pass < 2; pass++) | |
4936 | { | |
4937 | /* I is the index in spill_regs. | |
4938 | We advance it round-robin between insns to use all spill regs | |
4939 | equally, so that inherited reloads have a chance | |
f5d8c9f4 BS |
4940 | of leapfrogging each other. */ |
4941 | ||
4942 | i = last_spill_reg; | |
05d10675 | 4943 | |
a5339699 | 4944 | for (count = 0; count < n_spills; count++) |
32131a9c | 4945 | { |
eceef4c9 | 4946 | int class = (int) rld[r].class; |
03acd8f8 | 4947 | int regnum; |
32131a9c | 4948 | |
03acd8f8 BS |
4949 | i++; |
4950 | if (i >= n_spills) | |
4951 | i -= n_spills; | |
4952 | regnum = spill_regs[i]; | |
32131a9c | 4953 | |
eceef4c9 BS |
4954 | if ((reload_reg_free_p (regnum, rld[r].opnum, |
4955 | rld[r].when_needed) | |
4956 | || (rld[r].in | |
05d10675 BS |
4957 | /* We check reload_reg_used to make sure we |
4958 | don't clobber the return register. */ | |
03acd8f8 BS |
4959 | && ! TEST_HARD_REG_BIT (reload_reg_used, regnum) |
4960 | && reload_reg_free_for_value_p (regnum, | |
eceef4c9 BS |
4961 | rld[r].opnum, |
4962 | rld[r].when_needed, | |
4963 | rld[r].in, | |
4964 | rld[r].out, r, 1))) | |
03acd8f8 | 4965 | && TEST_HARD_REG_BIT (reg_class_contents[class], regnum) |
8ec450a4 | 4966 | && HARD_REGNO_MODE_OK (regnum, rld[r].mode) |
be7ae2a4 RK |
4967 | /* Look first for regs to share, then for unshared. But |
4968 | don't share regs used for inherited reloads; they are | |
4969 | the ones we want to preserve. */ | |
4970 | && (pass | |
4971 | || (TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
03acd8f8 | 4972 | regnum) |
be7ae2a4 | 4973 | && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, |
03acd8f8 | 4974 | regnum)))) |
32131a9c | 4975 | { |
8ec450a4 | 4976 | int nr = HARD_REGNO_NREGS (regnum, rld[r].mode); |
32131a9c RK |
4977 | /* Avoid the problem where spilling a GENERAL_OR_FP_REG |
4978 | (on 68000) got us two FP regs. If NR is 1, | |
4979 | we would reject both of them. */ | |
4980 | if (force_group) | |
67e61fe7 | 4981 | nr = rld[r].nregs; |
32131a9c RK |
4982 | /* If we need only one reg, we have already won. */ |
4983 | if (nr == 1) | |
4984 | { | |
4985 | /* But reject a single reg if we demand a group. */ | |
4986 | if (force_group) | |
4987 | continue; | |
4988 | break; | |
4989 | } | |
4990 | /* Otherwise check that as many consecutive regs as we need | |
f5d8c9f4 BS |
4991 | are available here. */ |
4992 | while (nr > 1) | |
4993 | { | |
4994 | int regno = regnum + nr - 1; | |
4995 | if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
4996 | && spill_reg_order[regno] >= 0 | |
4997 | && reload_reg_free_p (regno, rld[r].opnum, | |
4998 | rld[r].when_needed))) | |
4999 | break; | |
5000 | nr--; | |
5001 | } | |
32131a9c RK |
5002 | if (nr == 1) |
5003 | break; | |
5004 | } | |
5005 | } | |
5006 | ||
5007 | /* If we found something on pass 1, omit pass 2. */ | |
5008 | if (count < n_spills) | |
5009 | break; | |
5010 | } | |
f5d8c9f4 | 5011 | |
32131a9c | 5012 | /* We should have found a spill register by now. */ |
f5d8c9f4 | 5013 | if (count >= n_spills) |
32131a9c RK |
5014 | return 0; |
5015 | ||
f5d8c9f4 BS |
5016 | /* I is the index in SPILL_REG_RTX of the reload register we are to |
5017 | allocate. Get an rtx for it and find its register number. */ | |
32131a9c | 5018 | |
f5d8c9f4 | 5019 | return set_reload_reg (i, r); |
32131a9c RK |
5020 | } |
5021 | \f | |
67e61fe7 BS |
5022 | /* Initialize all the tables needed to allocate reload registers. |
5023 | CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX | |
5024 | is the array we use to restore the reg_rtx field for every reload. */ | |
32131a9c | 5025 | static void |
67e61fe7 | 5026 | choose_reload_regs_init (chain, save_reload_reg_rtx) |
7609e720 | 5027 | struct insn_chain *chain; |
67e61fe7 | 5028 | rtx *save_reload_reg_rtx; |
32131a9c | 5029 | { |
67e61fe7 | 5030 | int i; |
32131a9c | 5031 | |
67e61fe7 BS |
5032 | for (i = 0; i < n_reloads; i++) |
5033 | rld[i].reg_rtx = save_reload_reg_rtx[i]; | |
32131a9c RK |
5034 | |
5035 | bzero (reload_inherited, MAX_RELOADS); | |
4c9a05bc RK |
5036 | bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx)); |
5037 | bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx)); | |
32131a9c RK |
5038 | |
5039 | CLEAR_HARD_REG_SET (reload_reg_used); | |
5040 | CLEAR_HARD_REG_SET (reload_reg_used_at_all); | |
32131a9c | 5041 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); |
893bc853 | 5042 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload); |
546b63fb RK |
5043 | CLEAR_HARD_REG_SET (reload_reg_used_in_insn); |
5044 | CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); | |
32131a9c | 5045 | |
f1db3576 JL |
5046 | CLEAR_HARD_REG_SET (reg_used_in_insn); |
5047 | { | |
5048 | HARD_REG_SET tmp; | |
239a0f5b | 5049 | REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout); |
f1db3576 | 5050 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b | 5051 | REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set); |
f1db3576 | 5052 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b BS |
5053 | compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout); |
5054 | compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set); | |
f1db3576 | 5055 | } |
546b63fb RK |
5056 | for (i = 0; i < reload_n_operands; i++) |
5057 | { | |
5058 | CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); | |
5059 | CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); | |
5060 | CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); | |
47c8cf91 | 5061 | CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]); |
546b63fb | 5062 | CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); |
47c8cf91 | 5063 | CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]); |
546b63fb | 5064 | } |
32131a9c | 5065 | |
9e3a9cf2 | 5066 | COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs); |
05d10675 | 5067 | |
67e61fe7 | 5068 | CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); |
32131a9c | 5069 | |
67e61fe7 BS |
5070 | for (i = 0; i < n_reloads; i++) |
5071 | /* If we have already decided to use a certain register, | |
5072 | don't use it in another way. */ | |
5073 | if (rld[i].reg_rtx) | |
5074 | mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum, | |
5075 | rld[i].when_needed, rld[i].mode); | |
5076 | } | |
32131a9c | 5077 | |
67e61fe7 BS |
5078 | /* Assign hard reg targets for the pseudo-registers we must reload |
5079 | into hard regs for this insn. | |
5080 | Also output the instructions to copy them in and out of the hard regs. | |
5081 | ||
5082 | For machines with register classes, we are responsible for | |
5083 | finding a reload reg in the proper class. */ | |
5084 | ||
5085 | static void | |
5086 | choose_reload_regs (chain) | |
5087 | struct insn_chain *chain; | |
5088 | { | |
5089 | rtx insn = chain->insn; | |
5090 | register int i, j; | |
5091 | int max_group_size = 1; | |
5092 | enum reg_class group_class = NO_REGS; | |
f5d8c9f4 | 5093 | int pass, win, inheritance; |
67e61fe7 BS |
5094 | |
5095 | rtx save_reload_reg_rtx[MAX_RELOADS]; | |
32131a9c | 5096 | |
32131a9c RK |
5097 | /* In order to be certain of getting the registers we need, |
5098 | we must sort the reloads into order of increasing register class. | |
5099 | Then our grabbing of reload registers will parallel the process | |
a8fdc208 | 5100 | that provided the reload registers. |
32131a9c RK |
5101 | |
5102 | Also note whether any of the reloads wants a consecutive group of regs. | |
5103 | If so, record the maximum size of the group desired and what | |
5104 | register class contains all the groups needed by this insn. */ | |
5105 | ||
5106 | for (j = 0; j < n_reloads; j++) | |
5107 | { | |
5108 | reload_order[j] = j; | |
5109 | reload_spill_index[j] = -1; | |
5110 | ||
8ec450a4 | 5111 | if (rld[j].nregs > 1) |
32131a9c | 5112 | { |
8ec450a4 | 5113 | max_group_size = MAX (rld[j].nregs, max_group_size); |
eceef4c9 | 5114 | group_class = reg_class_superunion[(int)rld[j].class][(int)group_class]; |
32131a9c RK |
5115 | } |
5116 | ||
eceef4c9 | 5117 | save_reload_reg_rtx[j] = rld[j].reg_rtx; |
32131a9c RK |
5118 | } |
5119 | ||
5120 | if (n_reloads > 1) | |
5121 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); | |
5122 | ||
58b1581b RS |
5123 | /* If -O, try first with inheritance, then turning it off. |
5124 | If not -O, don't do inheritance. | |
5125 | Using inheritance when not optimizing leads to paradoxes | |
5126 | with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves | |
5127 | because one side of the comparison might be inherited. */ | |
f5d8c9f4 | 5128 | win = 0; |
58b1581b | 5129 | for (inheritance = optimize > 0; inheritance >= 0; inheritance--) |
32131a9c | 5130 | { |
67e61fe7 BS |
5131 | choose_reload_regs_init (chain, save_reload_reg_rtx); |
5132 | ||
32131a9c RK |
5133 | /* Process the reloads in order of preference just found. |
5134 | Beyond this point, subregs can be found in reload_reg_rtx. | |
5135 | ||
5136 | This used to look for an existing reloaded home for all | |
5137 | of the reloads, and only then perform any new reloads. | |
5138 | But that could lose if the reloads were done out of reg-class order | |
5139 | because a later reload with a looser constraint might have an old | |
5140 | home in a register needed by an earlier reload with a tighter constraint. | |
5141 | ||
5142 | To solve this, we make two passes over the reloads, in the order | |
5143 | described above. In the first pass we try to inherit a reload | |
5144 | from a previous insn. If there is a later reload that needs a | |
5145 | class that is a proper subset of the class being processed, we must | |
5146 | also allocate a spill register during the first pass. | |
5147 | ||
5148 | Then make a second pass over the reloads to allocate any reloads | |
5149 | that haven't been given registers yet. */ | |
5150 | ||
5151 | for (j = 0; j < n_reloads; j++) | |
5152 | { | |
5153 | register int r = reload_order[j]; | |
8593b745 | 5154 | rtx search_equiv = NULL_RTX; |
32131a9c RK |
5155 | |
5156 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 BS |
5157 | if (rld[r].out == 0 && rld[r].in == 0 |
5158 | && ! rld[r].secondary_p) | |
32131a9c RK |
5159 | continue; |
5160 | ||
b29514ee | 5161 | /* If find_reloads chose to use reload_in or reload_out as a reload |
b080c137 RK |
5162 | register, we don't need to chose one. Otherwise, try even if it |
5163 | found one since we might save an insn if we find the value lying | |
b29514ee R |
5164 | around. |
5165 | Try also when reload_in is a pseudo without a hard reg. */ | |
eceef4c9 BS |
5166 | if (rld[r].in != 0 && rld[r].reg_rtx != 0 |
5167 | && (rtx_equal_p (rld[r].in, rld[r].reg_rtx) | |
5168 | || (rtx_equal_p (rld[r].out, rld[r].reg_rtx) | |
5169 | && GET_CODE (rld[r].in) != MEM | |
5170 | && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER))) | |
32131a9c RK |
5171 | continue; |
5172 | ||
5173 | #if 0 /* No longer needed for correct operation. | |
5174 | It might give better code, or might not; worth an experiment? */ | |
5175 | /* If this is an optional reload, we can't inherit from earlier insns | |
5176 | until we are sure that any non-optional reloads have been allocated. | |
5177 | The following code takes advantage of the fact that optional reloads | |
5178 | are at the end of reload_order. */ | |
eceef4c9 | 5179 | if (rld[r].optional != 0) |
32131a9c | 5180 | for (i = 0; i < j; i++) |
eceef4c9 BS |
5181 | if ((rld[reload_order[i]].out != 0 |
5182 | || rld[reload_order[i]].in != 0 | |
5183 | || rld[reload_order[i]].secondary_p) | |
5184 | && ! rld[reload_order[i]].optional | |
5185 | && rld[reload_order[i]].reg_rtx == 0) | |
f5d8c9f4 | 5186 | allocate_reload_reg (chain, reload_order[i], 0); |
32131a9c RK |
5187 | #endif |
5188 | ||
5189 | /* First see if this pseudo is already available as reloaded | |
5190 | for a previous insn. We cannot try to inherit for reloads | |
5191 | that are smaller than the maximum number of registers needed | |
5192 | for groups unless the register we would allocate cannot be used | |
5193 | for the groups. | |
5194 | ||
5195 | We could check here to see if this is a secondary reload for | |
5196 | an object that is already in a register of the desired class. | |
5197 | This would avoid the need for the secondary reload register. | |
5198 | But this is complex because we can't easily determine what | |
b080c137 RK |
5199 | objects might want to be loaded via this reload. So let a |
5200 | register be allocated here. In `emit_reload_insns' we suppress | |
5201 | one of the loads in the case described above. */ | |
32131a9c RK |
5202 | |
5203 | if (inheritance) | |
5204 | { | |
cb2afeb3 | 5205 | int word = 0; |
32131a9c | 5206 | register int regno = -1; |
6a651371 | 5207 | enum machine_mode mode = VOIDmode; |
32131a9c | 5208 | |
eceef4c9 | 5209 | if (rld[r].in == 0) |
32131a9c | 5210 | ; |
eceef4c9 | 5211 | else if (GET_CODE (rld[r].in) == REG) |
db660765 | 5212 | { |
eceef4c9 BS |
5213 | regno = REGNO (rld[r].in); |
5214 | mode = GET_MODE (rld[r].in); | |
db660765 | 5215 | } |
eceef4c9 | 5216 | else if (GET_CODE (rld[r].in_reg) == REG) |
db660765 | 5217 | { |
eceef4c9 BS |
5218 | regno = REGNO (rld[r].in_reg); |
5219 | mode = GET_MODE (rld[r].in_reg); | |
db660765 | 5220 | } |
eceef4c9 BS |
5221 | else if (GET_CODE (rld[r].in_reg) == SUBREG |
5222 | && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG) | |
b60a8416 | 5223 | { |
eceef4c9 BS |
5224 | word = SUBREG_WORD (rld[r].in_reg); |
5225 | regno = REGNO (SUBREG_REG (rld[r].in_reg)); | |
cb2afeb3 R |
5226 | if (regno < FIRST_PSEUDO_REGISTER) |
5227 | regno += word; | |
eceef4c9 | 5228 | mode = GET_MODE (rld[r].in_reg); |
cb2afeb3 R |
5229 | } |
5230 | #ifdef AUTO_INC_DEC | |
eceef4c9 BS |
5231 | else if ((GET_CODE (rld[r].in_reg) == PRE_INC |
5232 | || GET_CODE (rld[r].in_reg) == PRE_DEC | |
5233 | || GET_CODE (rld[r].in_reg) == POST_INC | |
5234 | || GET_CODE (rld[r].in_reg) == POST_DEC) | |
5235 | && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG) | |
cb2afeb3 | 5236 | { |
eceef4c9 BS |
5237 | regno = REGNO (XEXP (rld[r].in_reg, 0)); |
5238 | mode = GET_MODE (XEXP (rld[r].in_reg, 0)); | |
5239 | rld[r].out = rld[r].in; | |
b60a8416 | 5240 | } |
cb2afeb3 | 5241 | #endif |
32131a9c RK |
5242 | #if 0 |
5243 | /* This won't work, since REGNO can be a pseudo reg number. | |
5244 | Also, it takes much more hair to keep track of all the things | |
5245 | that can invalidate an inherited reload of part of a pseudoreg. */ | |
eceef4c9 BS |
5246 | else if (GET_CODE (rld[r].in) == SUBREG |
5247 | && GET_CODE (SUBREG_REG (rld[r].in)) == REG) | |
5248 | regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in); | |
32131a9c RK |
5249 | #endif |
5250 | ||
5251 | if (regno >= 0 && reg_last_reload_reg[regno] != 0) | |
5252 | { | |
eceef4c9 | 5253 | enum reg_class class = rld[r].class, last_class; |
cb2afeb3 | 5254 | rtx last_reg = reg_last_reload_reg[regno]; |
05d10675 | 5255 | |
cb2afeb3 R |
5256 | i = REGNO (last_reg) + word; |
5257 | last_class = REGNO_REG_CLASS (i); | |
5258 | if ((GET_MODE_SIZE (GET_MODE (last_reg)) | |
5259 | >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD) | |
5260 | && reg_reloaded_contents[i] == regno | |
e6e52be0 | 5261 | && TEST_HARD_REG_BIT (reg_reloaded_valid, i) |
8ec450a4 | 5262 | && HARD_REGNO_MODE_OK (i, rld[r].mode) |
cb2afeb3 R |
5263 | && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i) |
5264 | /* Even if we can't use this register as a reload | |
5265 | register, we might use it for reload_override_in, | |
5266 | if copying it to the desired class is cheap | |
5267 | enough. */ | |
5268 | || ((REGISTER_MOVE_COST (last_class, class) | |
5269 | < MEMORY_MOVE_COST (mode, class, 1)) | |
5270 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
5271 | && (SECONDARY_INPUT_RELOAD_CLASS (class, mode, | |
5272 | last_reg) | |
5273 | == NO_REGS) | |
5274 | #endif | |
5275 | #ifdef SECONDARY_MEMORY_NEEDED | |
5276 | && ! SECONDARY_MEMORY_NEEDED (last_class, class, | |
5277 | mode) | |
5278 | #endif | |
5279 | )) | |
5280 | ||
8ec450a4 | 5281 | && (rld[r].nregs == max_group_size |
32131a9c | 5282 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], |
e6e52be0 | 5283 | i)) |
eceef4c9 BS |
5284 | && reload_reg_free_for_value_p (i, rld[r].opnum, |
5285 | rld[r].when_needed, | |
5286 | rld[r].in, | |
dfe96118 | 5287 | const0_rtx, r, 1)) |
32131a9c RK |
5288 | { |
5289 | /* If a group is needed, verify that all the subsequent | |
0f41302f | 5290 | registers still have their values intact. */ |
32131a9c | 5291 | int nr |
8ec450a4 | 5292 | = HARD_REGNO_NREGS (i, rld[r].mode); |
32131a9c RK |
5293 | int k; |
5294 | ||
5295 | for (k = 1; k < nr; k++) | |
e6e52be0 R |
5296 | if (reg_reloaded_contents[i + k] != regno |
5297 | || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k)) | |
32131a9c RK |
5298 | break; |
5299 | ||
5300 | if (k == nr) | |
5301 | { | |
c74fa651 RS |
5302 | int i1; |
5303 | ||
cb2afeb3 R |
5304 | last_reg = (GET_MODE (last_reg) == mode |
5305 | ? last_reg : gen_rtx_REG (mode, i)); | |
5306 | ||
c74fa651 RS |
5307 | /* We found a register that contains the |
5308 | value we need. If this register is the | |
5309 | same as an `earlyclobber' operand of the | |
5310 | current insn, just mark it as a place to | |
5311 | reload from since we can't use it as the | |
5312 | reload register itself. */ | |
5313 | ||
5314 | for (i1 = 0; i1 < n_earlyclobbers; i1++) | |
5315 | if (reg_overlap_mentioned_for_reload_p | |
5316 | (reg_last_reload_reg[regno], | |
5317 | reload_earlyclobbers[i1])) | |
5318 | break; | |
5319 | ||
8908158d | 5320 | if (i1 != n_earlyclobbers |
dfe96118 | 5321 | || ! (reload_reg_free_for_value_p |
eceef4c9 BS |
5322 | (i, rld[r].opnum, rld[r].when_needed, |
5323 | rld[r].in, rld[r].out, r, 1)) | |
e6e52be0 | 5324 | /* Don't use it if we'd clobber a pseudo reg. */ |
f1db3576 | 5325 | || (TEST_HARD_REG_BIT (reg_used_in_insn, i) |
eceef4c9 | 5326 | && rld[r].out |
e6e52be0 | 5327 | && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i)) |
0c7f2259 | 5328 | /* Don't clobber the frame pointer. */ |
67e61fe7 | 5329 | || (i == HARD_FRAME_POINTER_REGNUM && rld[r].out) |
8908158d RS |
5330 | /* Don't really use the inherited spill reg |
5331 | if we need it wider than we've got it. */ | |
8ec450a4 | 5332 | || (GET_MODE_SIZE (rld[r].mode) |
b29514ee | 5333 | > GET_MODE_SIZE (mode)) |
eceef4c9 | 5334 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], |
cb2afeb3 R |
5335 | i) |
5336 | ||
b29514ee R |
5337 | /* If find_reloads chose reload_out as reload |
5338 | register, stay with it - that leaves the | |
5339 | inherited register for subsequent reloads. */ | |
eceef4c9 | 5340 | || (rld[r].out && rld[r].reg_rtx |
67e61fe7 | 5341 | && rtx_equal_p (rld[r].out, rld[r].reg_rtx))) |
cb2afeb3 R |
5342 | { |
5343 | reload_override_in[r] = last_reg; | |
5344 | reload_inheritance_insn[r] | |
5345 | = reg_reloaded_insn[i]; | |
5346 | } | |
c74fa651 RS |
5347 | else |
5348 | { | |
54c40e68 | 5349 | int k; |
c74fa651 RS |
5350 | /* We can use this as a reload reg. */ |
5351 | /* Mark the register as in use for this part of | |
5352 | the insn. */ | |
e6e52be0 | 5353 | mark_reload_reg_in_use (i, |
eceef4c9 BS |
5354 | rld[r].opnum, |
5355 | rld[r].when_needed, | |
8ec450a4 | 5356 | rld[r].mode); |
eceef4c9 | 5357 | rld[r].reg_rtx = last_reg; |
c74fa651 RS |
5358 | reload_inherited[r] = 1; |
5359 | reload_inheritance_insn[r] | |
5360 | = reg_reloaded_insn[i]; | |
5361 | reload_spill_index[r] = i; | |
54c40e68 RS |
5362 | for (k = 0; k < nr; k++) |
5363 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, | |
e6e52be0 | 5364 | i + k); |
c74fa651 | 5365 | } |
32131a9c RK |
5366 | } |
5367 | } | |
5368 | } | |
5369 | } | |
5370 | ||
5371 | /* Here's another way to see if the value is already lying around. */ | |
5372 | if (inheritance | |
eceef4c9 | 5373 | && rld[r].in != 0 |
32131a9c | 5374 | && ! reload_inherited[r] |
eceef4c9 BS |
5375 | && rld[r].out == 0 |
5376 | && (CONSTANT_P (rld[r].in) | |
5377 | || GET_CODE (rld[r].in) == PLUS | |
5378 | || GET_CODE (rld[r].in) == REG | |
5379 | || GET_CODE (rld[r].in) == MEM) | |
8ec450a4 | 5380 | && (rld[r].nregs == max_group_size |
eceef4c9 BS |
5381 | || ! reg_classes_intersect_p (rld[r].class, group_class))) |
5382 | search_equiv = rld[r].in; | |
8593b745 R |
5383 | /* If this is an output reload from a simple move insn, look |
5384 | if an equivalence for the input is available. */ | |
eceef4c9 | 5385 | else if (inheritance && rld[r].in == 0 && rld[r].out != 0) |
8593b745 R |
5386 | { |
5387 | rtx set = single_set (insn); | |
5388 | ||
5389 | if (set | |
eceef4c9 | 5390 | && rtx_equal_p (rld[r].out, SET_DEST (set)) |
8593b745 R |
5391 | && CONSTANT_P (SET_SRC (set))) |
5392 | search_equiv = SET_SRC (set); | |
5393 | } | |
5394 | ||
5395 | if (search_equiv) | |
32131a9c RK |
5396 | { |
5397 | register rtx equiv | |
eceef4c9 | 5398 | = find_equiv_reg (search_equiv, insn, rld[r].class, |
8ec450a4 | 5399 | -1, NULL_PTR, 0, rld[r].mode); |
f428f252 | 5400 | int regno = 0; |
32131a9c RK |
5401 | |
5402 | if (equiv != 0) | |
5403 | { | |
5404 | if (GET_CODE (equiv) == REG) | |
5405 | regno = REGNO (equiv); | |
5406 | else if (GET_CODE (equiv) == SUBREG) | |
5407 | { | |
f8a9e02b RK |
5408 | /* This must be a SUBREG of a hard register. |
5409 | Make a new REG since this might be used in an | |
5410 | address and not all machines support SUBREGs | |
5411 | there. */ | |
5412 | regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv); | |
8ec450a4 | 5413 | equiv = gen_rtx_REG (rld[r].mode, regno); |
32131a9c RK |
5414 | } |
5415 | else | |
5416 | abort (); | |
5417 | } | |
5418 | ||
5419 | /* If we found a spill reg, reject it unless it is free | |
5420 | and of the desired class. */ | |
5421 | if (equiv != 0 | |
cb2afeb3 | 5422 | && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno) |
eceef4c9 BS |
5423 | && ! reload_reg_free_for_value_p (regno, rld[r].opnum, |
5424 | rld[r].when_needed, | |
5425 | rld[r].in, | |
5426 | rld[r].out, r, 1)) | |
5427 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], | |
32131a9c RK |
5428 | regno))) |
5429 | equiv = 0; | |
5430 | ||
8ec450a4 | 5431 | if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode)) |
32131a9c RK |
5432 | equiv = 0; |
5433 | ||
5434 | /* We found a register that contains the value we need. | |
5435 | If this register is the same as an `earlyclobber' operand | |
5436 | of the current insn, just mark it as a place to reload from | |
5437 | since we can't use it as the reload register itself. */ | |
5438 | ||
5439 | if (equiv != 0) | |
5440 | for (i = 0; i < n_earlyclobbers; i++) | |
bfa30b22 RK |
5441 | if (reg_overlap_mentioned_for_reload_p (equiv, |
5442 | reload_earlyclobbers[i])) | |
32131a9c RK |
5443 | { |
5444 | reload_override_in[r] = equiv; | |
5445 | equiv = 0; | |
5446 | break; | |
5447 | } | |
5448 | ||
3c785e47 R |
5449 | /* If the equiv register we have found is explicitly clobbered |
5450 | in the current insn, it depends on the reload type if we | |
5451 | can use it, use it for reload_override_in, or not at all. | |
5452 | In particular, we then can't use EQUIV for a | |
5453 | RELOAD_FOR_OUTPUT_ADDRESS reload. */ | |
32131a9c RK |
5454 | |
5455 | if (equiv != 0 && regno_clobbered_p (regno, insn)) | |
5456 | { | |
eceef4c9 | 5457 | switch (rld[r].when_needed) |
3c785e47 R |
5458 | { |
5459 | case RELOAD_FOR_OTHER_ADDRESS: | |
5460 | case RELOAD_FOR_INPADDR_ADDRESS: | |
5461 | case RELOAD_FOR_INPUT_ADDRESS: | |
5462 | case RELOAD_FOR_OPADDR_ADDR: | |
5463 | break; | |
5464 | case RELOAD_OTHER: | |
5465 | case RELOAD_FOR_INPUT: | |
5466 | case RELOAD_FOR_OPERAND_ADDRESS: | |
5467 | reload_override_in[r] = equiv; | |
5468 | /* Fall through. */ | |
5469 | default: | |
5470 | equiv = 0; | |
5471 | break; | |
5472 | } | |
32131a9c RK |
5473 | } |
5474 | ||
5475 | /* If we found an equivalent reg, say no code need be generated | |
5476 | to load it, and use it as our reload reg. */ | |
3ec2ea3e | 5477 | if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM) |
32131a9c | 5478 | { |
8ec450a4 | 5479 | int nr = HARD_REGNO_NREGS (regno, rld[r].mode); |
100338df | 5480 | int k; |
eceef4c9 | 5481 | rld[r].reg_rtx = equiv; |
32131a9c | 5482 | reload_inherited[r] = 1; |
100338df | 5483 | |
91d7e7ac R |
5484 | /* If reg_reloaded_valid is not set for this register, |
5485 | there might be a stale spill_reg_store lying around. | |
5486 | We must clear it, since otherwise emit_reload_insns | |
5487 | might delete the store. */ | |
5488 | if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno)) | |
5489 | spill_reg_store[regno] = NULL_RTX; | |
100338df JL |
5490 | /* If any of the hard registers in EQUIV are spill |
5491 | registers, mark them as in use for this insn. */ | |
5492 | for (k = 0; k < nr; k++) | |
be7ae2a4 | 5493 | { |
100338df JL |
5494 | i = spill_reg_order[regno + k]; |
5495 | if (i >= 0) | |
5496 | { | |
eceef4c9 BS |
5497 | mark_reload_reg_in_use (regno, rld[r].opnum, |
5498 | rld[r].when_needed, | |
8ec450a4 | 5499 | rld[r].mode); |
100338df JL |
5500 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, |
5501 | regno + k); | |
5502 | } | |
be7ae2a4 | 5503 | } |
32131a9c RK |
5504 | } |
5505 | } | |
5506 | ||
5507 | /* If we found a register to use already, or if this is an optional | |
5508 | reload, we are done. */ | |
eceef4c9 | 5509 | if (rld[r].reg_rtx != 0 || rld[r].optional != 0) |
32131a9c RK |
5510 | continue; |
5511 | ||
5512 | #if 0 /* No longer needed for correct operation. Might or might not | |
5513 | give better code on the average. Want to experiment? */ | |
5514 | ||
5515 | /* See if there is a later reload that has a class different from our | |
5516 | class that intersects our class or that requires less register | |
5517 | than our reload. If so, we must allocate a register to this | |
5518 | reload now, since that reload might inherit a previous reload | |
5519 | and take the only available register in our class. Don't do this | |
5520 | for optional reloads since they will force all previous reloads | |
5521 | to be allocated. Also don't do this for reloads that have been | |
5522 | turned off. */ | |
5523 | ||
5524 | for (i = j + 1; i < n_reloads; i++) | |
5525 | { | |
5526 | int s = reload_order[i]; | |
5527 | ||
eceef4c9 BS |
5528 | if ((rld[s].in == 0 && rld[s].out == 0 |
5529 | && ! rld[s].secondary_p) | |
5530 | || rld[s].optional) | |
32131a9c RK |
5531 | continue; |
5532 | ||
eceef4c9 BS |
5533 | if ((rld[s].class != rld[r].class |
5534 | && reg_classes_intersect_p (rld[r].class, | |
5535 | rld[s].class)) | |
8ec450a4 | 5536 | || rld[s].nregs < rld[r].nregs) |
05d10675 | 5537 | break; |
32131a9c RK |
5538 | } |
5539 | ||
5540 | if (i == n_reloads) | |
5541 | continue; | |
5542 | ||
f5d8c9f4 | 5543 | allocate_reload_reg (chain, r, j == n_reloads - 1); |
32131a9c RK |
5544 | #endif |
5545 | } | |
5546 | ||
5547 | /* Now allocate reload registers for anything non-optional that | |
5548 | didn't get one yet. */ | |
5549 | for (j = 0; j < n_reloads; j++) | |
5550 | { | |
5551 | register int r = reload_order[j]; | |
5552 | ||
5553 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 | 5554 | if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p) |
32131a9c RK |
5555 | continue; |
5556 | ||
5557 | /* Skip reloads that already have a register allocated or are | |
0f41302f | 5558 | optional. */ |
eceef4c9 | 5559 | if (rld[r].reg_rtx != 0 || rld[r].optional) |
32131a9c RK |
5560 | continue; |
5561 | ||
f5d8c9f4 | 5562 | if (! allocate_reload_reg (chain, r, j == n_reloads - 1)) |
32131a9c RK |
5563 | break; |
5564 | } | |
5565 | ||
5566 | /* If that loop got all the way, we have won. */ | |
5567 | if (j == n_reloads) | |
f5d8c9f4 BS |
5568 | { |
5569 | win = 1; | |
5570 | break; | |
5571 | } | |
32131a9c | 5572 | |
32131a9c | 5573 | /* Loop around and try without any inheritance. */ |
32131a9c RK |
5574 | } |
5575 | ||
f5d8c9f4 BS |
5576 | if (! win) |
5577 | { | |
5578 | /* First undo everything done by the failed attempt | |
5579 | to allocate with inheritance. */ | |
5580 | choose_reload_regs_init (chain, save_reload_reg_rtx); | |
5581 | ||
5582 | /* Some sanity tests to verify that the reloads found in the first | |
5583 | pass are identical to the ones we have now. */ | |
5584 | if (chain->n_reloads != n_reloads) | |
5585 | abort (); | |
5586 | ||
5587 | for (i = 0; i < n_reloads; i++) | |
5588 | { | |
5589 | if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0) | |
5590 | continue; | |
5591 | if (chain->rld[i].when_needed != rld[i].when_needed) | |
5592 | abort (); | |
5593 | for (j = 0; j < n_spills; j++) | |
5594 | if (spill_regs[j] == chain->rld[i].regno) | |
5595 | if (! set_reload_reg (j, i)) | |
5596 | failed_reload (chain->insn, i); | |
5597 | } | |
5598 | } | |
5599 | ||
32131a9c RK |
5600 | /* If we thought we could inherit a reload, because it seemed that |
5601 | nothing else wanted the same reload register earlier in the insn, | |
cb2afeb3 R |
5602 | verify that assumption, now that all reloads have been assigned. |
5603 | Likewise for reloads where reload_override_in has been set. */ | |
32131a9c | 5604 | |
cb2afeb3 R |
5605 | /* If doing expensive optimizations, do one preliminary pass that doesn't |
5606 | cancel any inheritance, but removes reloads that have been needed only | |
5607 | for reloads that we know can be inherited. */ | |
5608 | for (pass = flag_expensive_optimizations; pass >= 0; pass--) | |
32131a9c | 5609 | { |
cb2afeb3 | 5610 | for (j = 0; j < n_reloads; j++) |
029b38ff | 5611 | { |
cb2afeb3 R |
5612 | register int r = reload_order[j]; |
5613 | rtx check_reg; | |
eceef4c9 BS |
5614 | if (reload_inherited[r] && rld[r].reg_rtx) |
5615 | check_reg = rld[r].reg_rtx; | |
cb2afeb3 R |
5616 | else if (reload_override_in[r] |
5617 | && (GET_CODE (reload_override_in[r]) == REG | |
05d10675 | 5618 | || GET_CODE (reload_override_in[r]) == SUBREG)) |
cb2afeb3 R |
5619 | check_reg = reload_override_in[r]; |
5620 | else | |
5621 | continue; | |
dfe96118 | 5622 | if (! reload_reg_free_for_value_p (true_regnum (check_reg), |
eceef4c9 BS |
5623 | rld[r].opnum, |
5624 | rld[r].when_needed, | |
5625 | rld[r].in, | |
05d10675 | 5626 | (reload_inherited[r] |
eceef4c9 | 5627 | ? rld[r].out : const0_rtx), |
dfe96118 | 5628 | r, 1)) |
029b38ff | 5629 | { |
cb2afeb3 R |
5630 | if (pass) |
5631 | continue; | |
5632 | reload_inherited[r] = 0; | |
5633 | reload_override_in[r] = 0; | |
029b38ff | 5634 | } |
cb2afeb3 R |
5635 | /* If we can inherit a RELOAD_FOR_INPUT, or can use a |
5636 | reload_override_in, then we do not need its related | |
5637 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads; | |
5638 | likewise for other reload types. | |
5639 | We handle this by removing a reload when its only replacement | |
5640 | is mentioned in reload_in of the reload we are going to inherit. | |
5641 | A special case are auto_inc expressions; even if the input is | |
5642 | inherited, we still need the address for the output. We can | |
fe92fe26 | 5643 | recognize them because they have RELOAD_OUT set to RELOAD_IN. |
cb2afeb3 R |
5644 | If we suceeded removing some reload and we are doing a preliminary |
5645 | pass just to remove such reloads, make another pass, since the | |
5646 | removal of one reload might allow us to inherit another one. */ | |
eceef4c9 BS |
5647 | else if (rld[r].in |
5648 | && rld[r].out != rld[r].in | |
5649 | && remove_address_replacements (rld[r].in) && pass) | |
cb2afeb3 | 5650 | pass = 2; |
32131a9c RK |
5651 | } |
5652 | } | |
5653 | ||
5654 | /* Now that reload_override_in is known valid, | |
5655 | actually override reload_in. */ | |
5656 | for (j = 0; j < n_reloads; j++) | |
5657 | if (reload_override_in[j]) | |
eceef4c9 | 5658 | rld[j].in = reload_override_in[j]; |
32131a9c RK |
5659 | |
5660 | /* If this reload won't be done because it has been cancelled or is | |
5661 | optional and not inherited, clear reload_reg_rtx so other | |
5662 | routines (such as subst_reloads) don't get confused. */ | |
5663 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
5664 | if (rld[j].reg_rtx != 0 |
5665 | && ((rld[j].optional && ! reload_inherited[j]) | |
5666 | || (rld[j].in == 0 && rld[j].out == 0 | |
5667 | && ! rld[j].secondary_p))) | |
be7ae2a4 | 5668 | { |
eceef4c9 | 5669 | int regno = true_regnum (rld[j].reg_rtx); |
be7ae2a4 RK |
5670 | |
5671 | if (spill_reg_order[regno] >= 0) | |
eceef4c9 | 5672 | clear_reload_reg_in_use (regno, rld[j].opnum, |
8ec450a4 | 5673 | rld[j].when_needed, rld[j].mode); |
eceef4c9 | 5674 | rld[j].reg_rtx = 0; |
c0029be5 | 5675 | reload_spill_index[j] = -1; |
be7ae2a4 | 5676 | } |
32131a9c RK |
5677 | |
5678 | /* Record which pseudos and which spill regs have output reloads. */ | |
5679 | for (j = 0; j < n_reloads; j++) | |
5680 | { | |
5681 | register int r = reload_order[j]; | |
5682 | ||
5683 | i = reload_spill_index[r]; | |
5684 | ||
e6e52be0 | 5685 | /* I is nonneg if this reload uses a register. |
eceef4c9 | 5686 | If rld[r].reg_rtx is 0, this is an optional reload |
32131a9c | 5687 | that we opted to ignore. */ |
eceef4c9 BS |
5688 | if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG |
5689 | && rld[r].reg_rtx != 0) | |
32131a9c | 5690 | { |
eceef4c9 | 5691 | register int nregno = REGNO (rld[r].out_reg); |
372e033b RS |
5692 | int nr = 1; |
5693 | ||
5694 | if (nregno < FIRST_PSEUDO_REGISTER) | |
8ec450a4 | 5695 | nr = HARD_REGNO_NREGS (nregno, rld[r].mode); |
32131a9c RK |
5696 | |
5697 | while (--nr >= 0) | |
372e033b RS |
5698 | reg_has_output_reload[nregno + nr] = 1; |
5699 | ||
5700 | if (i >= 0) | |
32131a9c | 5701 | { |
8ec450a4 | 5702 | nr = HARD_REGNO_NREGS (i, rld[r].mode); |
372e033b | 5703 | while (--nr >= 0) |
e6e52be0 | 5704 | SET_HARD_REG_BIT (reg_is_output_reload, i + nr); |
32131a9c RK |
5705 | } |
5706 | ||
eceef4c9 BS |
5707 | if (rld[r].when_needed != RELOAD_OTHER |
5708 | && rld[r].when_needed != RELOAD_FOR_OUTPUT | |
5709 | && rld[r].when_needed != RELOAD_FOR_INSN) | |
32131a9c RK |
5710 | abort (); |
5711 | } | |
5712 | } | |
5713 | } | |
cb2afeb3 R |
5714 | |
5715 | /* Deallocate the reload register for reload R. This is called from | |
5716 | remove_address_replacements. */ | |
5717 | void | |
5718 | deallocate_reload_reg (r) | |
5719 | int r; | |
5720 | { | |
5721 | int regno; | |
5722 | ||
eceef4c9 | 5723 | if (! rld[r].reg_rtx) |
cb2afeb3 | 5724 | return; |
eceef4c9 BS |
5725 | regno = true_regnum (rld[r].reg_rtx); |
5726 | rld[r].reg_rtx = 0; | |
cb2afeb3 | 5727 | if (spill_reg_order[regno] >= 0) |
eceef4c9 | 5728 | clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed, |
8ec450a4 | 5729 | rld[r].mode); |
cb2afeb3 R |
5730 | reload_spill_index[r] = -1; |
5731 | } | |
32131a9c | 5732 | \f |
e9a25f70 | 5733 | /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two |
546b63fb RK |
5734 | reloads of the same item for fear that we might not have enough reload |
5735 | registers. However, normally they will get the same reload register | |
05d10675 | 5736 | and hence actually need not be loaded twice. |
546b63fb RK |
5737 | |
5738 | Here we check for the most common case of this phenomenon: when we have | |
5739 | a number of reloads for the same object, each of which were allocated | |
5740 | the same reload_reg_rtx, that reload_reg_rtx is not used for any other | |
5741 | reload, and is not modified in the insn itself. If we find such, | |
5742 | merge all the reloads and set the resulting reload to RELOAD_OTHER. | |
5743 | This will not increase the number of spill registers needed and will | |
5744 | prevent redundant code. */ | |
5745 | ||
546b63fb RK |
5746 | static void |
5747 | merge_assigned_reloads (insn) | |
5748 | rtx insn; | |
5749 | { | |
5750 | int i, j; | |
5751 | ||
5752 | /* Scan all the reloads looking for ones that only load values and | |
5753 | are not already RELOAD_OTHER and ones whose reload_reg_rtx are | |
5754 | assigned and not modified by INSN. */ | |
5755 | ||
5756 | for (i = 0; i < n_reloads; i++) | |
5757 | { | |
d668e863 R |
5758 | int conflicting_input = 0; |
5759 | int max_input_address_opnum = -1; | |
5760 | int min_conflicting_input_opnum = MAX_RECOG_OPERANDS; | |
5761 | ||
eceef4c9 BS |
5762 | if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER |
5763 | || rld[i].out != 0 || rld[i].reg_rtx == 0 | |
5764 | || reg_set_p (rld[i].reg_rtx, insn)) | |
546b63fb RK |
5765 | continue; |
5766 | ||
5767 | /* Look at all other reloads. Ensure that the only use of this | |
5768 | reload_reg_rtx is in a reload that just loads the same value | |
5769 | as we do. Note that any secondary reloads must be of the identical | |
5770 | class since the values, modes, and result registers are the | |
5771 | same, so we need not do anything with any secondary reloads. */ | |
5772 | ||
5773 | for (j = 0; j < n_reloads; j++) | |
5774 | { | |
eceef4c9 BS |
5775 | if (i == j || rld[j].reg_rtx == 0 |
5776 | || ! reg_overlap_mentioned_p (rld[j].reg_rtx, | |
5777 | rld[i].reg_rtx)) | |
546b63fb RK |
5778 | continue; |
5779 | ||
eceef4c9 BS |
5780 | if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
5781 | && rld[j].opnum > max_input_address_opnum) | |
5782 | max_input_address_opnum = rld[j].opnum; | |
d668e863 | 5783 | |
546b63fb | 5784 | /* If the reload regs aren't exactly the same (e.g, different modes) |
d668e863 R |
5785 | or if the values are different, we can't merge this reload. |
5786 | But if it is an input reload, we might still merge | |
5787 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */ | |
546b63fb | 5788 | |
eceef4c9 BS |
5789 | if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) |
5790 | || rld[j].out != 0 || rld[j].in == 0 | |
5791 | || ! rtx_equal_p (rld[i].in, rld[j].in)) | |
d668e863 | 5792 | { |
eceef4c9 BS |
5793 | if (rld[j].when_needed != RELOAD_FOR_INPUT |
5794 | || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS | |
5795 | || rld[i].opnum > rld[j].opnum) | |
5796 | && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS)) | |
d668e863 R |
5797 | break; |
5798 | conflicting_input = 1; | |
eceef4c9 BS |
5799 | if (min_conflicting_input_opnum > rld[j].opnum) |
5800 | min_conflicting_input_opnum = rld[j].opnum; | |
d668e863 | 5801 | } |
546b63fb RK |
5802 | } |
5803 | ||
5804 | /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if | |
5805 | we, in fact, found any matching reloads. */ | |
5806 | ||
d668e863 R |
5807 | if (j == n_reloads |
5808 | && max_input_address_opnum <= min_conflicting_input_opnum) | |
546b63fb RK |
5809 | { |
5810 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
5811 | if (i != j && rld[j].reg_rtx != 0 |
5812 | && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) | |
d668e863 | 5813 | && (! conflicting_input |
eceef4c9 BS |
5814 | || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
5815 | || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS)) | |
546b63fb | 5816 | { |
eceef4c9 BS |
5817 | rld[i].when_needed = RELOAD_OTHER; |
5818 | rld[j].in = 0; | |
efdb3590 | 5819 | reload_spill_index[j] = -1; |
546b63fb RK |
5820 | transfer_replacements (i, j); |
5821 | } | |
5822 | ||
5823 | /* If this is now RELOAD_OTHER, look for any reloads that load | |
5824 | parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS | |
5825 | if they were for inputs, RELOAD_OTHER for outputs. Note that | |
5826 | this test is equivalent to looking for reloads for this operand | |
5827 | number. */ | |
5828 | ||
eceef4c9 | 5829 | if (rld[i].when_needed == RELOAD_OTHER) |
546b63fb | 5830 | for (j = 0; j < n_reloads; j++) |
eceef4c9 BS |
5831 | if (rld[j].in != 0 |
5832 | && rld[i].when_needed != RELOAD_OTHER | |
5833 | && reg_overlap_mentioned_for_reload_p (rld[j].in, | |
5834 | rld[i].in)) | |
5835 | rld[j].when_needed | |
5836 | = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
5837 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
47c8cf91 | 5838 | ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER); |
546b63fb RK |
5839 | } |
5840 | } | |
05d10675 | 5841 | } |
e9a25f70 | 5842 | |
546b63fb | 5843 | \f |
367b1cf5 BS |
5844 | /* These arrays are filled by emit_reload_insns and its subroutines. */ |
5845 | static rtx input_reload_insns[MAX_RECOG_OPERANDS]; | |
5846 | static rtx other_input_address_reload_insns = 0; | |
5847 | static rtx other_input_reload_insns = 0; | |
5848 | static rtx input_address_reload_insns[MAX_RECOG_OPERANDS]; | |
5849 | static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
5850 | static rtx output_reload_insns[MAX_RECOG_OPERANDS]; | |
5851 | static rtx output_address_reload_insns[MAX_RECOG_OPERANDS]; | |
5852 | static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
5853 | static rtx operand_reload_insns = 0; | |
5854 | static rtx other_operand_reload_insns = 0; | |
5855 | static rtx other_output_reload_insns[MAX_RECOG_OPERANDS]; | |
5856 | ||
5857 | /* Values to be put in spill_reg_store are put here first. */ | |
5858 | static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
5859 | static HARD_REG_SET reg_reloaded_died; | |
5860 | ||
5861 | /* Generate insns to perform reload RL, which is for the insn in CHAIN and | |
5862 | has the number J. OLD contains the value to be used as input. */ | |
32131a9c | 5863 | static void |
367b1cf5 | 5864 | emit_input_reload_insns (chain, rl, old, j) |
7609e720 | 5865 | struct insn_chain *chain; |
367b1cf5 BS |
5866 | struct reload *rl; |
5867 | rtx old; | |
5868 | int j; | |
32131a9c | 5869 | { |
7609e720 | 5870 | rtx insn = chain->insn; |
367b1cf5 BS |
5871 | register rtx reloadreg = rl->reg_rtx; |
5872 | rtx oldequiv_reg = 0; | |
5873 | rtx oldequiv = 0; | |
5874 | int special = 0; | |
5875 | enum machine_mode mode; | |
5876 | rtx *where; | |
5877 | ||
5878 | /* Determine the mode to reload in. | |
5879 | This is very tricky because we have three to choose from. | |
5880 | There is the mode the insn operand wants (rl->inmode). | |
5881 | There is the mode of the reload register RELOADREG. | |
5882 | There is the intrinsic mode of the operand, which we could find | |
5883 | by stripping some SUBREGs. | |
5884 | It turns out that RELOADREG's mode is irrelevant: | |
5885 | we can change that arbitrarily. | |
5886 | ||
5887 | Consider (SUBREG:SI foo:QI) as an operand that must be SImode; | |
5888 | then the reload reg may not support QImode moves, so use SImode. | |
5889 | If foo is in memory due to spilling a pseudo reg, this is safe, | |
5890 | because the QImode value is in the least significant part of a | |
5891 | slot big enough for a SImode. If foo is some other sort of | |
5892 | memory reference, then it is impossible to reload this case, | |
5893 | so previous passes had better make sure this never happens. | |
5894 | ||
5895 | Then consider a one-word union which has SImode and one of its | |
5896 | members is a float, being fetched as (SUBREG:SF union:SI). | |
5897 | We must fetch that as SFmode because we could be loading into | |
5898 | a float-only register. In this case OLD's mode is correct. | |
5899 | ||
5900 | Consider an immediate integer: it has VOIDmode. Here we need | |
5901 | to get a mode from something else. | |
5902 | ||
5903 | In some cases, there is a fourth mode, the operand's | |
5904 | containing mode. If the insn specifies a containing mode for | |
5905 | this operand, it overrides all others. | |
5906 | ||
5907 | I am not sure whether the algorithm here is always right, | |
5908 | but it does the right things in those cases. */ | |
5909 | ||
5910 | mode = GET_MODE (old); | |
5911 | if (mode == VOIDmode) | |
5912 | mode = rl->inmode; | |
7609e720 | 5913 | |
367b1cf5 BS |
5914 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
5915 | /* If we need a secondary register for this operation, see if | |
5916 | the value is already in a register in that class. Don't | |
5917 | do this if the secondary register will be used as a scratch | |
5918 | register. */ | |
5919 | ||
5920 | if (rl->secondary_in_reload >= 0 | |
5921 | && rl->secondary_in_icode == CODE_FOR_nothing | |
5922 | && optimize) | |
5923 | oldequiv | |
5924 | = find_equiv_reg (old, insn, | |
5925 | rld[rl->secondary_in_reload].class, | |
5926 | -1, NULL_PTR, 0, mode); | |
5927 | #endif | |
e6e52be0 | 5928 | |
367b1cf5 BS |
5929 | /* If reloading from memory, see if there is a register |
5930 | that already holds the same value. If so, reload from there. | |
5931 | We can pass 0 as the reload_reg_p argument because | |
5932 | any other reload has either already been emitted, | |
5933 | in which case find_equiv_reg will see the reload-insn, | |
5934 | or has yet to be emitted, in which case it doesn't matter | |
5935 | because we will use this equiv reg right away. */ | |
5936 | ||
5937 | if (oldequiv == 0 && optimize | |
5938 | && (GET_CODE (old) == MEM | |
5939 | || (GET_CODE (old) == REG | |
5940 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
5941 | && reg_renumber[REGNO (old)] < 0))) | |
5942 | oldequiv = find_equiv_reg (old, insn, ALL_REGS, | |
5943 | -1, NULL_PTR, 0, mode); | |
5944 | ||
5945 | if (oldequiv) | |
5946 | { | |
5947 | int regno = true_regnum (oldequiv); | |
5948 | ||
5949 | /* Don't use OLDEQUIV if any other reload changes it at an | |
5950 | earlier stage of this insn or at this stage. */ | |
5951 | if (! reload_reg_free_for_value_p (regno, rl->opnum, | |
5952 | rl->when_needed, | |
5953 | rl->in, const0_rtx, j, | |
5954 | 0)) | |
5955 | oldequiv = 0; | |
5956 | ||
5957 | /* If it is no cheaper to copy from OLDEQUIV into the | |
5958 | reload register than it would be to move from memory, | |
5959 | don't use it. Likewise, if we need a secondary register | |
5960 | or memory. */ | |
5961 | ||
5962 | if (oldequiv != 0 | |
5963 | && ((REGNO_REG_CLASS (regno) != rl->class | |
5964 | && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno), | |
5965 | rl->class) | |
5966 | >= MEMORY_MOVE_COST (mode, rl->class, 1))) | |
5967 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
5968 | || (SECONDARY_INPUT_RELOAD_CLASS (rl->class, | |
5969 | mode, oldequiv) | |
5970 | != NO_REGS) | |
5971 | #endif | |
5972 | #ifdef SECONDARY_MEMORY_NEEDED | |
5973 | || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno), | |
5974 | rl->class, | |
5975 | mode) | |
5976 | #endif | |
5977 | )) | |
5978 | oldequiv = 0; | |
5979 | } | |
32131a9c | 5980 | |
367b1cf5 BS |
5981 | /* delete_output_reload is only invoked properly if old contains |
5982 | the original pseudo register. Since this is replaced with a | |
5983 | hard reg when RELOAD_OVERRIDE_IN is set, see if we can | |
5984 | find the pseudo in RELOAD_IN_REG. */ | |
5985 | if (oldequiv == 0 | |
5986 | && reload_override_in[j] | |
5987 | && GET_CODE (rl->in_reg) == REG) | |
5988 | { | |
5989 | oldequiv = old; | |
5990 | old = rl->in_reg; | |
5991 | } | |
5992 | if (oldequiv == 0) | |
5993 | oldequiv = old; | |
5994 | else if (GET_CODE (oldequiv) == REG) | |
5995 | oldequiv_reg = oldequiv; | |
5996 | else if (GET_CODE (oldequiv) == SUBREG) | |
5997 | oldequiv_reg = SUBREG_REG (oldequiv); | |
5998 | ||
5999 | /* If we are reloading from a register that was recently stored in | |
6000 | with an output-reload, see if we can prove there was | |
6001 | actually no need to store the old value in it. */ | |
6002 | ||
6003 | if (optimize && GET_CODE (oldequiv) == REG | |
6004 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER | |
6005 | && spill_reg_store[REGNO (oldequiv)] | |
6006 | && GET_CODE (old) == REG | |
6007 | && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) | |
6008 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6009 | rl->out_reg))) | |
6010 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6011 | ||
6012 | /* Encapsulate both RELOADREG and OLDEQUIV into that mode, | |
6013 | then load RELOADREG from OLDEQUIV. Note that we cannot use | |
6014 | gen_lowpart_common since it can do the wrong thing when | |
6015 | RELOADREG has a multi-word mode. Note that RELOADREG | |
6016 | must always be a REG here. */ | |
6017 | ||
6018 | if (GET_MODE (reloadreg) != mode) | |
6019 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
6020 | while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) | |
6021 | oldequiv = SUBREG_REG (oldequiv); | |
6022 | if (GET_MODE (oldequiv) != VOIDmode | |
6023 | && mode != GET_MODE (oldequiv)) | |
6024 | oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0); | |
6025 | ||
6026 | /* Switch to the right place to emit the reload insns. */ | |
6027 | switch (rl->when_needed) | |
6028 | { | |
6029 | case RELOAD_OTHER: | |
6030 | where = &other_input_reload_insns; | |
6031 | break; | |
6032 | case RELOAD_FOR_INPUT: | |
6033 | where = &input_reload_insns[rl->opnum]; | |
6034 | break; | |
6035 | case RELOAD_FOR_INPUT_ADDRESS: | |
6036 | where = &input_address_reload_insns[rl->opnum]; | |
6037 | break; | |
6038 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6039 | where = &inpaddr_address_reload_insns[rl->opnum]; | |
6040 | break; | |
6041 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
6042 | where = &output_address_reload_insns[rl->opnum]; | |
6043 | break; | |
6044 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
6045 | where = &outaddr_address_reload_insns[rl->opnum]; | |
6046 | break; | |
6047 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6048 | where = &operand_reload_insns; | |
6049 | break; | |
6050 | case RELOAD_FOR_OPADDR_ADDR: | |
6051 | where = &other_operand_reload_insns; | |
6052 | break; | |
6053 | case RELOAD_FOR_OTHER_ADDRESS: | |
6054 | where = &other_input_address_reload_insns; | |
6055 | break; | |
6056 | default: | |
6057 | abort (); | |
6058 | } | |
546b63fb | 6059 | |
367b1cf5 | 6060 | push_to_sequence (*where); |
32131a9c | 6061 | |
367b1cf5 BS |
6062 | /* Auto-increment addresses must be reloaded in a special way. */ |
6063 | if (rl->out && ! rl->out_reg) | |
32131a9c | 6064 | { |
367b1cf5 BS |
6065 | /* We are not going to bother supporting the case where a |
6066 | incremented register can't be copied directly from | |
6067 | OLDEQUIV since this seems highly unlikely. */ | |
6068 | if (rl->secondary_in_reload >= 0) | |
6069 | abort (); | |
32131a9c | 6070 | |
367b1cf5 BS |
6071 | if (reload_inherited[j]) |
6072 | oldequiv = reloadreg; | |
cb2afeb3 | 6073 | |
367b1cf5 | 6074 | old = XEXP (rl->in_reg, 0); |
32131a9c | 6075 | |
367b1cf5 BS |
6076 | if (optimize && GET_CODE (oldequiv) == REG |
6077 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER | |
6078 | && spill_reg_store[REGNO (oldequiv)] | |
6079 | && GET_CODE (old) == REG | |
6080 | && (dead_or_set_p (insn, | |
6081 | spill_reg_stored_to[REGNO (oldequiv)]) | |
6082 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6083 | old))) | |
6084 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6085 | ||
6086 | /* Prevent normal processing of this reload. */ | |
6087 | special = 1; | |
6088 | /* Output a special code sequence for this case. */ | |
6089 | new_spill_reg_store[REGNO (reloadreg)] | |
6090 | = inc_for_reload (reloadreg, oldequiv, rl->out, | |
6091 | rl->inc); | |
6092 | } | |
32131a9c | 6093 | |
367b1cf5 BS |
6094 | /* If we are reloading a pseudo-register that was set by the previous |
6095 | insn, see if we can get rid of that pseudo-register entirely | |
6096 | by redirecting the previous insn into our reload register. */ | |
6097 | ||
6098 | else if (optimize && GET_CODE (old) == REG | |
6099 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
6100 | && dead_or_set_p (insn, old) | |
6101 | /* This is unsafe if some other reload | |
6102 | uses the same reg first. */ | |
6103 | && reload_reg_free_for_value_p (REGNO (reloadreg), | |
6104 | rl->opnum, | |
6105 | rl->when_needed, | |
6106 | old, rl->out, | |
6107 | j, 0)) | |
6108 | { | |
6109 | rtx temp = PREV_INSN (insn); | |
6110 | while (temp && GET_CODE (temp) == NOTE) | |
6111 | temp = PREV_INSN (temp); | |
6112 | if (temp | |
6113 | && GET_CODE (temp) == INSN | |
6114 | && GET_CODE (PATTERN (temp)) == SET | |
6115 | && SET_DEST (PATTERN (temp)) == old | |
6116 | /* Make sure we can access insn_operand_constraint. */ | |
6117 | && asm_noperands (PATTERN (temp)) < 0 | |
6118 | /* This is unsafe if prev insn rejects our reload reg. */ | |
6119 | && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint, | |
6120 | reloadreg) | |
6121 | /* This is unsafe if operand occurs more than once in current | |
6122 | insn. Perhaps some occurrences aren't reloaded. */ | |
6123 | && count_occurrences (PATTERN (insn), old) == 1 | |
6124 | /* Don't risk splitting a matching pair of operands. */ | |
6125 | && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp)))) | |
6126 | { | |
6127 | /* Store into the reload register instead of the pseudo. */ | |
6128 | SET_DEST (PATTERN (temp)) = reloadreg; | |
6129 | ||
6130 | /* If the previous insn is an output reload, the source is | |
6131 | a reload register, and its spill_reg_store entry will | |
6132 | contain the previous destination. This is now | |
6133 | invalid. */ | |
6134 | if (GET_CODE (SET_SRC (PATTERN (temp))) == REG | |
6135 | && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER) | |
32131a9c | 6136 | { |
367b1cf5 BS |
6137 | spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0; |
6138 | spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; | |
32131a9c RK |
6139 | } |
6140 | ||
367b1cf5 BS |
6141 | /* If these are the only uses of the pseudo reg, |
6142 | pretend for GDB it lives in the reload reg we used. */ | |
6143 | if (REG_N_DEATHS (REGNO (old)) == 1 | |
6144 | && REG_N_SETS (REGNO (old)) == 1) | |
cb2afeb3 | 6145 | { |
367b1cf5 BS |
6146 | reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx); |
6147 | alter_reg (REGNO (old), -1); | |
32131a9c | 6148 | } |
07875628 | 6149 | special = 1; |
367b1cf5 BS |
6150 | } |
6151 | } | |
32131a9c | 6152 | |
367b1cf5 | 6153 | /* We can't do that, so output an insn to load RELOADREG. */ |
32131a9c | 6154 | |
367b1cf5 BS |
6155 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
6156 | /* If we have a secondary reload, pick up the secondary register | |
6157 | and icode, if any. If OLDEQUIV and OLD are different or | |
6158 | if this is an in-out reload, recompute whether or not we | |
6159 | still need a secondary register and what the icode should | |
6160 | be. If we still need a secondary register and the class or | |
6161 | icode is different, go back to reloading from OLD if using | |
6162 | OLDEQUIV means that we got the wrong type of register. We | |
6163 | cannot have different class or icode due to an in-out reload | |
6164 | because we don't make such reloads when both the input and | |
6165 | output need secondary reload registers. */ | |
6166 | ||
07875628 | 6167 | if (! special && rl->secondary_in_reload >= 0) |
367b1cf5 BS |
6168 | { |
6169 | rtx second_reload_reg = 0; | |
6170 | int secondary_reload = rl->secondary_in_reload; | |
6171 | rtx real_oldequiv = oldequiv; | |
6172 | rtx real_old = old; | |
6173 | rtx tmp; | |
6174 | enum insn_code icode; | |
6175 | ||
6176 | /* If OLDEQUIV is a pseudo with a MEM, get the real MEM | |
6177 | and similarly for OLD. | |
6178 | See comments in get_secondary_reload in reload.c. */ | |
6179 | /* If it is a pseudo that cannot be replaced with its | |
6180 | equivalent MEM, we must fall back to reload_in, which | |
6181 | will have all the necessary substitutions registered. | |
6182 | Likewise for a pseudo that can't be replaced with its | |
6183 | equivalent constant. | |
6184 | ||
6185 | Take extra care for subregs of such pseudos. Note that | |
6186 | we cannot use reg_equiv_mem in this case because it is | |
6187 | not in the right mode. */ | |
6188 | ||
6189 | tmp = oldequiv; | |
6190 | if (GET_CODE (tmp) == SUBREG) | |
6191 | tmp = SUBREG_REG (tmp); | |
6192 | if (GET_CODE (tmp) == REG | |
6193 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER | |
6194 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6195 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6196 | { | |
6197 | if (! reg_equiv_mem[REGNO (tmp)] | |
6198 | || num_not_at_initial_offset | |
6199 | || GET_CODE (oldequiv) == SUBREG) | |
6200 | real_oldequiv = rl->in; | |
6201 | else | |
6202 | real_oldequiv = reg_equiv_mem[REGNO (tmp)]; | |
6203 | } | |
32131a9c | 6204 | |
367b1cf5 BS |
6205 | tmp = old; |
6206 | if (GET_CODE (tmp) == SUBREG) | |
6207 | tmp = SUBREG_REG (tmp); | |
6208 | if (GET_CODE (tmp) == REG | |
6209 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER | |
6210 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6211 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6212 | { | |
6213 | if (! reg_equiv_mem[REGNO (tmp)] | |
6214 | || num_not_at_initial_offset | |
6215 | || GET_CODE (old) == SUBREG) | |
6216 | real_old = rl->in; | |
6217 | else | |
6218 | real_old = reg_equiv_mem[REGNO (tmp)]; | |
6219 | } | |
6220 | ||
6221 | second_reload_reg = rld[secondary_reload].reg_rtx; | |
6222 | icode = rl->secondary_in_icode; | |
6223 | ||
6224 | if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) | |
6225 | || (rl->in != 0 && rl->out != 0)) | |
6226 | { | |
6227 | enum reg_class new_class | |
6228 | = SECONDARY_INPUT_RELOAD_CLASS (rl->class, | |
6229 | mode, real_oldequiv); | |
6230 | ||
6231 | if (new_class == NO_REGS) | |
6232 | second_reload_reg = 0; | |
6233 | else | |
32131a9c | 6234 | { |
367b1cf5 BS |
6235 | enum insn_code new_icode; |
6236 | enum machine_mode new_mode; | |
6237 | ||
6238 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], | |
6239 | REGNO (second_reload_reg))) | |
6240 | oldequiv = old, real_oldequiv = real_old; | |
6241 | else | |
32131a9c | 6242 | { |
367b1cf5 BS |
6243 | new_icode = reload_in_optab[(int) mode]; |
6244 | if (new_icode != CODE_FOR_nothing | |
6245 | && ((insn_data[(int) new_icode].operand[0].predicate | |
6246 | && ! ((*insn_data[(int) new_icode].operand[0].predicate) | |
6247 | (reloadreg, mode))) | |
6248 | || (insn_data[(int) new_icode].operand[1].predicate | |
6249 | && ! ((*insn_data[(int) new_icode].operand[1].predicate) | |
6250 | (real_oldequiv, mode))))) | |
6251 | new_icode = CODE_FOR_nothing; | |
6252 | ||
6253 | if (new_icode == CODE_FOR_nothing) | |
6254 | new_mode = mode; | |
6255 | else | |
6256 | new_mode = insn_data[(int) new_icode].operand[2].mode; | |
d30e8ef0 | 6257 | |
367b1cf5 | 6258 | if (GET_MODE (second_reload_reg) != new_mode) |
32131a9c | 6259 | { |
367b1cf5 BS |
6260 | if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg), |
6261 | new_mode)) | |
6262 | oldequiv = old, real_oldequiv = real_old; | |
6263 | else | |
6264 | second_reload_reg | |
6265 | = gen_rtx_REG (new_mode, | |
6266 | REGNO (second_reload_reg)); | |
32131a9c | 6267 | } |
32131a9c RK |
6268 | } |
6269 | } | |
367b1cf5 | 6270 | } |
32131a9c | 6271 | |
367b1cf5 BS |
6272 | /* If we still need a secondary reload register, check |
6273 | to see if it is being used as a scratch or intermediate | |
6274 | register and generate code appropriately. If we need | |
6275 | a scratch register, use REAL_OLDEQUIV since the form of | |
6276 | the insn may depend on the actual address if it is | |
6277 | a MEM. */ | |
546b63fb | 6278 | |
367b1cf5 BS |
6279 | if (second_reload_reg) |
6280 | { | |
6281 | if (icode != CODE_FOR_nothing) | |
32131a9c | 6282 | { |
367b1cf5 BS |
6283 | emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, |
6284 | second_reload_reg)); | |
07875628 | 6285 | special = 1; |
367b1cf5 BS |
6286 | } |
6287 | else | |
6288 | { | |
6289 | /* See if we need a scratch register to load the | |
6290 | intermediate register (a tertiary reload). */ | |
6291 | enum insn_code tertiary_icode | |
6292 | = rld[secondary_reload].secondary_in_icode; | |
1554c2c6 | 6293 | |
367b1cf5 BS |
6294 | if (tertiary_icode != CODE_FOR_nothing) |
6295 | { | |
6296 | rtx third_reload_reg | |
6297 | = rld[rld[secondary_reload].secondary_in_reload].reg_rtx; | |
1554c2c6 | 6298 | |
367b1cf5 BS |
6299 | emit_insn ((GEN_FCN (tertiary_icode) |
6300 | (second_reload_reg, real_oldequiv, | |
6301 | third_reload_reg))); | |
6302 | } | |
6303 | else | |
6304 | gen_reload (second_reload_reg, real_oldequiv, | |
6305 | rl->opnum, | |
6306 | rl->when_needed); | |
32131a9c | 6307 | |
367b1cf5 BS |
6308 | oldequiv = second_reload_reg; |
6309 | } | |
6310 | } | |
6311 | } | |
6312 | #endif | |
32131a9c | 6313 | |
07875628 | 6314 | if (! special && ! rtx_equal_p (reloadreg, oldequiv)) |
367b1cf5 BS |
6315 | { |
6316 | rtx real_oldequiv = oldequiv; | |
6317 | ||
6318 | if ((GET_CODE (oldequiv) == REG | |
6319 | && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER | |
6320 | && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0 | |
6321 | || reg_equiv_constant[REGNO (oldequiv)] != 0)) | |
6322 | || (GET_CODE (oldequiv) == SUBREG | |
6323 | && GET_CODE (SUBREG_REG (oldequiv)) == REG | |
6324 | && (REGNO (SUBREG_REG (oldequiv)) | |
6325 | >= FIRST_PSEUDO_REGISTER) | |
6326 | && ((reg_equiv_memory_loc | |
6327 | [REGNO (SUBREG_REG (oldequiv))] != 0) | |
6328 | || (reg_equiv_constant | |
6329 | [REGNO (SUBREG_REG (oldequiv))] != 0)))) | |
6330 | real_oldequiv = rl->in; | |
6331 | gen_reload (reloadreg, real_oldequiv, rl->opnum, | |
6332 | rl->when_needed); | |
6333 | } | |
32131a9c | 6334 | |
367b1cf5 BS |
6335 | /* End this sequence. */ |
6336 | *where = get_insns (); | |
6337 | end_sequence (); | |
32131a9c | 6338 | |
367b1cf5 BS |
6339 | /* Update reload_override_in so that delete_address_reloads_1 |
6340 | can see the actual register usage. */ | |
6341 | if (oldequiv_reg) | |
6342 | reload_override_in[j] = oldequiv; | |
6343 | } | |
32131a9c | 6344 | |
367b1cf5 BS |
6345 | /* Generate insns to for the output reload RL, which is for the insn described |
6346 | by CHAIN and has the number J. */ | |
6347 | static void | |
6348 | emit_output_reload_insns (chain, rl, j) | |
6349 | struct insn_chain *chain; | |
6350 | struct reload *rl; | |
6351 | int j; | |
6352 | { | |
6353 | rtx reloadreg = rl->reg_rtx; | |
6354 | rtx insn = chain->insn; | |
6355 | int special = 0; | |
6356 | rtx old = rl->out; | |
6357 | enum machine_mode mode = GET_MODE (old); | |
6358 | rtx p; | |
32131a9c | 6359 | |
367b1cf5 BS |
6360 | if (rl->when_needed == RELOAD_OTHER) |
6361 | start_sequence (); | |
6362 | else | |
6363 | push_to_sequence (output_reload_insns[rl->opnum]); | |
32131a9c | 6364 | |
367b1cf5 BS |
6365 | /* Determine the mode to reload in. |
6366 | See comments above (for input reloading). */ | |
32131a9c | 6367 | |
367b1cf5 BS |
6368 | if (mode == VOIDmode) |
6369 | { | |
6370 | /* VOIDmode should never happen for an output. */ | |
6371 | if (asm_noperands (PATTERN (insn)) < 0) | |
6372 | /* It's the compiler's fault. */ | |
6373 | fatal_insn ("VOIDmode on an output", insn); | |
6374 | error_for_asm (insn, "output operand is constant in `asm'"); | |
6375 | /* Prevent crash--use something we know is valid. */ | |
6376 | mode = word_mode; | |
6377 | old = gen_rtx_REG (mode, REGNO (reloadreg)); | |
6378 | } | |
546b63fb | 6379 | |
367b1cf5 BS |
6380 | if (GET_MODE (reloadreg) != mode) |
6381 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
32131a9c | 6382 | |
367b1cf5 | 6383 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
32131a9c | 6384 | |
367b1cf5 BS |
6385 | /* If we need two reload regs, set RELOADREG to the intermediate |
6386 | one, since it will be stored into OLD. We might need a secondary | |
6387 | register only for an input reload, so check again here. */ | |
32131a9c | 6388 | |
367b1cf5 BS |
6389 | if (rl->secondary_out_reload >= 0) |
6390 | { | |
6391 | rtx real_old = old; | |
cb2afeb3 | 6392 | |
367b1cf5 BS |
6393 | if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER |
6394 | && reg_equiv_mem[REGNO (old)] != 0) | |
6395 | real_old = reg_equiv_mem[REGNO (old)]; | |
32131a9c | 6396 | |
367b1cf5 BS |
6397 | if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class, |
6398 | mode, real_old) | |
6399 | != NO_REGS)) | |
b60a8416 | 6400 | { |
367b1cf5 BS |
6401 | rtx second_reloadreg = reloadreg; |
6402 | reloadreg = rld[rl->secondary_out_reload].reg_rtx; | |
32131a9c | 6403 | |
367b1cf5 BS |
6404 | /* See if RELOADREG is to be used as a scratch register |
6405 | or as an intermediate register. */ | |
6406 | if (rl->secondary_out_icode != CODE_FOR_nothing) | |
6407 | { | |
6408 | emit_insn ((GEN_FCN (rl->secondary_out_icode) | |
6409 | (real_old, second_reloadreg, reloadreg))); | |
6410 | special = 1; | |
6411 | } | |
6412 | else | |
6413 | { | |
6414 | /* See if we need both a scratch and intermediate reload | |
6415 | register. */ | |
32131a9c | 6416 | |
367b1cf5 BS |
6417 | int secondary_reload = rl->secondary_out_reload; |
6418 | enum insn_code tertiary_icode | |
6419 | = rld[secondary_reload].secondary_out_icode; | |
32131a9c | 6420 | |
367b1cf5 BS |
6421 | if (GET_MODE (reloadreg) != mode) |
6422 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
cb2afeb3 | 6423 | |
367b1cf5 BS |
6424 | if (tertiary_icode != CODE_FOR_nothing) |
6425 | { | |
6426 | rtx third_reloadreg | |
6427 | = rld[rld[secondary_reload].secondary_out_reload].reg_rtx; | |
6428 | rtx tem; | |
6429 | ||
6430 | /* Copy primary reload reg to secondary reload reg. | |
6431 | (Note that these have been swapped above, then | |
6432 | secondary reload reg to OLD using our insn. */ | |
6433 | ||
6434 | /* If REAL_OLD is a paradoxical SUBREG, remove it | |
6435 | and try to put the opposite SUBREG on | |
6436 | RELOADREG. */ | |
6437 | if (GET_CODE (real_old) == SUBREG | |
6438 | && (GET_MODE_SIZE (GET_MODE (real_old)) | |
6439 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old)))) | |
6440 | && 0 != (tem = gen_lowpart_common | |
6441 | (GET_MODE (SUBREG_REG (real_old)), | |
6442 | reloadreg))) | |
6443 | real_old = SUBREG_REG (real_old), reloadreg = tem; | |
6444 | ||
6445 | gen_reload (reloadreg, second_reloadreg, | |
6446 | rl->opnum, rl->when_needed); | |
6447 | emit_insn ((GEN_FCN (tertiary_icode) | |
6448 | (real_old, reloadreg, third_reloadreg))); | |
6449 | special = 1; | |
6450 | } | |
05d10675 | 6451 | |
367b1cf5 BS |
6452 | else |
6453 | /* Copy between the reload regs here and then to | |
6454 | OUT later. */ | |
cb2afeb3 | 6455 | |
367b1cf5 BS |
6456 | gen_reload (reloadreg, second_reloadreg, |
6457 | rl->opnum, rl->when_needed); | |
a7911cd2 | 6458 | } |
367b1cf5 BS |
6459 | } |
6460 | } | |
32131a9c RK |
6461 | #endif |
6462 | ||
367b1cf5 BS |
6463 | /* Output the last reload insn. */ |
6464 | if (! special) | |
6465 | { | |
6466 | rtx set; | |
6467 | ||
6468 | /* Don't output the last reload if OLD is not the dest of | |
6469 | INSN and is in the src and is clobbered by INSN. */ | |
6470 | if (! flag_expensive_optimizations | |
6471 | || GET_CODE (old) != REG | |
6472 | || !(set = single_set (insn)) | |
6473 | || rtx_equal_p (old, SET_DEST (set)) | |
6474 | || !reg_mentioned_p (old, SET_SRC (set)) | |
6475 | || !regno_clobbered_p (REGNO (old), insn)) | |
6476 | gen_reload (old, reloadreg, rl->opnum, | |
6477 | rl->when_needed); | |
6478 | } | |
32131a9c | 6479 | |
367b1cf5 BS |
6480 | /* Look at all insns we emitted, just to be safe. */ |
6481 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
6482 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') | |
6483 | { | |
6484 | rtx pat = PATTERN (p); | |
546b63fb | 6485 | |
367b1cf5 BS |
6486 | /* If this output reload doesn't come from a spill reg, |
6487 | clear any memory of reloaded copies of the pseudo reg. | |
6488 | If this output reload comes from a spill reg, | |
6489 | reg_has_output_reload will make this do nothing. */ | |
6490 | note_stores (pat, forget_old_reloads_1, NULL); | |
cb2afeb3 | 6491 | |
367b1cf5 BS |
6492 | if (reg_mentioned_p (rl->reg_rtx, pat)) |
6493 | { | |
6494 | rtx set = single_set (insn); | |
6495 | if (reload_spill_index[j] < 0 | |
6496 | && set | |
6497 | && SET_SRC (set) == rl->reg_rtx) | |
6498 | { | |
6499 | int src = REGNO (SET_SRC (set)); | |
32131a9c | 6500 | |
367b1cf5 BS |
6501 | reload_spill_index[j] = src; |
6502 | SET_HARD_REG_BIT (reg_is_output_reload, src); | |
6503 | if (find_regno_note (insn, REG_DEAD, src)) | |
6504 | SET_HARD_REG_BIT (reg_reloaded_died, src); | |
6505 | } | |
6506 | if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER) | |
6507 | { | |
6508 | int s = rl->secondary_out_reload; | |
6509 | set = single_set (p); | |
6510 | /* If this reload copies only to the secondary reload | |
6511 | register, the secondary reload does the actual | |
6512 | store. */ | |
6513 | if (s >= 0 && set == NULL_RTX) | |
6514 | ; /* We can't tell what function the secondary reload | |
6515 | has and where the actual store to the pseudo is | |
6516 | made; leave new_spill_reg_store alone. */ | |
6517 | else if (s >= 0 | |
6518 | && SET_SRC (set) == rl->reg_rtx | |
6519 | && SET_DEST (set) == rld[s].reg_rtx) | |
6520 | { | |
6521 | /* Usually the next instruction will be the | |
6522 | secondary reload insn; if we can confirm | |
6523 | that it is, setting new_spill_reg_store to | |
6524 | that insn will allow an extra optimization. */ | |
6525 | rtx s_reg = rld[s].reg_rtx; | |
6526 | rtx next = NEXT_INSN (p); | |
6527 | rld[s].out = rl->out; | |
6528 | rld[s].out_reg = rl->out_reg; | |
6529 | set = single_set (next); | |
6530 | if (set && SET_SRC (set) == s_reg | |
6531 | && ! new_spill_reg_store[REGNO (s_reg)]) | |
6532 | { | |
6533 | SET_HARD_REG_BIT (reg_is_output_reload, | |
6534 | REGNO (s_reg)); | |
6535 | new_spill_reg_store[REGNO (s_reg)] = next; | |
6536 | } | |
6537 | } | |
6538 | else | |
6539 | new_spill_reg_store[REGNO (rl->reg_rtx)] = p; | |
6540 | } | |
6541 | } | |
6542 | } | |
32131a9c | 6543 | |
367b1cf5 BS |
6544 | if (rl->when_needed == RELOAD_OTHER) |
6545 | { | |
6546 | emit_insns (other_output_reload_insns[rl->opnum]); | |
6547 | other_output_reload_insns[rl->opnum] = get_insns (); | |
6548 | } | |
6549 | else | |
6550 | output_reload_insns[rl->opnum] = get_insns (); | |
32131a9c | 6551 | |
367b1cf5 BS |
6552 | end_sequence (); |
6553 | } | |
32131a9c | 6554 | |
367b1cf5 BS |
6555 | /* Do input reloading for reload RL, which is for the insn described by CHAIN |
6556 | and has the number J. */ | |
6557 | static void | |
6558 | do_input_reload (chain, rl, j) | |
6559 | struct insn_chain *chain; | |
6560 | struct reload *rl; | |
6561 | int j; | |
6562 | { | |
6563 | int expect_occurrences = 1; | |
6564 | rtx insn = chain->insn; | |
6565 | rtx old = (rl->in && GET_CODE (rl->in) == MEM | |
6566 | ? rl->in_reg : rl->in); | |
6567 | ||
6568 | if (old != 0 | |
6569 | /* AUTO_INC reloads need to be handled even if inherited. We got an | |
6570 | AUTO_INC reload if reload_out is set but reload_out_reg isn't. */ | |
6571 | && (! reload_inherited[j] || (rl->out && ! rl->out_reg)) | |
6572 | && ! rtx_equal_p (rl->reg_rtx, old) | |
6573 | && rl->reg_rtx != 0) | |
6574 | { | |
6575 | emit_input_reload_insns (chain, rld + j, old, j); | |
6576 | } | |
32131a9c | 6577 | |
367b1cf5 BS |
6578 | /* When inheriting a wider reload, we have a MEM in rl->in, |
6579 | e.g. inheriting a SImode output reload for | |
6580 | (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */ | |
6581 | if (optimize && reload_inherited[j] && rl->in | |
6582 | && GET_CODE (rl->in) == MEM | |
6583 | && GET_CODE (rl->in_reg) == MEM | |
6584 | && reload_spill_index[j] >= 0 | |
6585 | && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j])) | |
6586 | { | |
6587 | expect_occurrences | |
6588 | = count_occurrences (PATTERN (insn), rl->in) == 1 ? 0 : -1; | |
6589 | rl->in | |
6590 | = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]]; | |
6591 | } | |
32131a9c | 6592 | |
367b1cf5 BS |
6593 | /* If we are reloading a register that was recently stored in with an |
6594 | output-reload, see if we can prove there was | |
6595 | actually no need to store the old value in it. */ | |
32131a9c | 6596 | |
367b1cf5 BS |
6597 | if (optimize |
6598 | && (reload_inherited[j] || reload_override_in[j]) | |
6599 | && rl->reg_rtx | |
6600 | && GET_CODE (rl->reg_rtx) == REG | |
6601 | && spill_reg_store[REGNO (rl->reg_rtx)] != 0 | |
6602 | #if 0 | |
6603 | /* There doesn't seem to be any reason to restrict this to pseudos | |
6604 | and doing so loses in the case where we are copying from a | |
6605 | register of the wrong class. */ | |
6606 | && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
6607 | >= FIRST_PSEUDO_REGISTER) | |
6608 | #endif | |
6609 | /* The insn might have already some references to stackslots | |
6610 | replaced by MEMs, while reload_out_reg still names the | |
6611 | original pseudo. */ | |
6612 | && (dead_or_set_p (insn, | |
6613 | spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
6614 | || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)], | |
6615 | rl->out_reg))) | |
6616 | delete_output_reload (insn, j, REGNO (rl->reg_rtx)); | |
6617 | } | |
32131a9c | 6618 | |
367b1cf5 BS |
6619 | /* Do output reloading for reload RL, which is for the insn described by |
6620 | CHAIN and has the number J. | |
6621 | ??? At some point we need to support handling output reloads of | |
6622 | JUMP_INSNs or insns that set cc0. */ | |
6623 | static void | |
6624 | do_output_reload (chain, rl, j) | |
6625 | struct insn_chain *chain; | |
6626 | struct reload *rl; | |
6627 | int j; | |
6628 | { | |
6629 | rtx note, old; | |
6630 | rtx insn = chain->insn; | |
6631 | /* If this is an output reload that stores something that is | |
6632 | not loaded in this same reload, see if we can eliminate a previous | |
6633 | store. */ | |
6634 | rtx pseudo = rl->out_reg; | |
6635 | ||
6636 | if (pseudo | |
6637 | && GET_CODE (pseudo) == REG | |
6638 | && ! rtx_equal_p (rl->in_reg, pseudo) | |
6639 | && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER | |
6640 | && reg_last_reload_reg[REGNO (pseudo)]) | |
6641 | { | |
6642 | int pseudo_no = REGNO (pseudo); | |
6643 | int last_regno = REGNO (reg_last_reload_reg[pseudo_no]); | |
6644 | ||
6645 | /* We don't need to test full validity of last_regno for | |
6646 | inherit here; we only want to know if the store actually | |
6647 | matches the pseudo. */ | |
6648 | if (reg_reloaded_contents[last_regno] == pseudo_no | |
6649 | && spill_reg_store[last_regno] | |
6650 | && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) | |
6651 | delete_output_reload (insn, j, last_regno); | |
6652 | } | |
5e03c156 | 6653 | |
367b1cf5 BS |
6654 | old = rl->out_reg; |
6655 | if (old == 0 | |
6656 | || rl->reg_rtx == old | |
6657 | || rl->reg_rtx == 0) | |
6658 | return; | |
32131a9c | 6659 | |
367b1cf5 BS |
6660 | /* An output operand that dies right away does need a reload, |
6661 | but need not be copied from it. Show the new location in the | |
6662 | REG_UNUSED note. */ | |
6663 | if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH) | |
6664 | && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) | |
6665 | { | |
6666 | XEXP (note, 0) = rl->reg_rtx; | |
6667 | return; | |
6668 | } | |
6669 | /* Likewise for a SUBREG of an operand that dies. */ | |
6670 | else if (GET_CODE (old) == SUBREG | |
6671 | && GET_CODE (SUBREG_REG (old)) == REG | |
6672 | && 0 != (note = find_reg_note (insn, REG_UNUSED, | |
6673 | SUBREG_REG (old)))) | |
6674 | { | |
6675 | XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), | |
6676 | rl->reg_rtx); | |
6677 | return; | |
6678 | } | |
6679 | else if (GET_CODE (old) == SCRATCH) | |
6680 | /* If we aren't optimizing, there won't be a REG_UNUSED note, | |
6681 | but we don't want to make an output reload. */ | |
6682 | return; | |
1554c2c6 | 6683 | |
367b1cf5 BS |
6684 | /* If is a JUMP_INSN, we can't support output reloads yet. */ |
6685 | if (GET_CODE (insn) == JUMP_INSN) | |
6686 | abort (); | |
5e03c156 | 6687 | |
367b1cf5 BS |
6688 | emit_output_reload_insns (chain, rld + j, j); |
6689 | } | |
1554c2c6 | 6690 | |
367b1cf5 | 6691 | /* Output insns to reload values in and out of the chosen reload regs. */ |
32131a9c | 6692 | |
367b1cf5 BS |
6693 | static void |
6694 | emit_reload_insns (chain) | |
6695 | struct insn_chain *chain; | |
6696 | { | |
6697 | rtx insn = chain->insn; | |
32131a9c | 6698 | |
367b1cf5 BS |
6699 | register int j; |
6700 | rtx following_insn = NEXT_INSN (insn); | |
6701 | rtx before_insn = PREV_INSN (insn); | |
e6e52be0 | 6702 | |
367b1cf5 | 6703 | CLEAR_HARD_REG_SET (reg_reloaded_died); |
e6e52be0 | 6704 | |
367b1cf5 BS |
6705 | for (j = 0; j < reload_n_operands; j++) |
6706 | input_reload_insns[j] = input_address_reload_insns[j] | |
6707 | = inpaddr_address_reload_insns[j] | |
6708 | = output_reload_insns[j] = output_address_reload_insns[j] | |
6709 | = outaddr_address_reload_insns[j] | |
6710 | = other_output_reload_insns[j] = 0; | |
6711 | other_input_address_reload_insns = 0; | |
6712 | other_input_reload_insns = 0; | |
6713 | operand_reload_insns = 0; | |
6714 | other_operand_reload_insns = 0; | |
32131a9c | 6715 | |
367b1cf5 BS |
6716 | /* Now output the instructions to copy the data into and out of the |
6717 | reload registers. Do these in the order that the reloads were reported, | |
6718 | since reloads of base and index registers precede reloads of operands | |
6719 | and the operands may need the base and index registers reloaded. */ | |
32131a9c | 6720 | |
367b1cf5 BS |
6721 | for (j = 0; j < n_reloads; j++) |
6722 | { | |
6723 | if (rld[j].reg_rtx | |
6724 | && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER) | |
6725 | new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0; | |
d7e0324f | 6726 | |
367b1cf5 BS |
6727 | do_input_reload (chain, rld + j, j); |
6728 | do_output_reload (chain, rld + j, j); | |
32131a9c RK |
6729 | } |
6730 | ||
546b63fb RK |
6731 | /* Now write all the insns we made for reloads in the order expected by |
6732 | the allocation functions. Prior to the insn being reloaded, we write | |
6733 | the following reloads: | |
6734 | ||
6735 | RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. | |
6736 | ||
2edc8d65 | 6737 | RELOAD_OTHER reloads. |
546b63fb | 6738 | |
47c8cf91 ILT |
6739 | For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed |
6740 | by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the | |
6741 | RELOAD_FOR_INPUT reload for the operand. | |
546b63fb | 6742 | |
893bc853 RK |
6743 | RELOAD_FOR_OPADDR_ADDRS reloads. |
6744 | ||
546b63fb RK |
6745 | RELOAD_FOR_OPERAND_ADDRESS reloads. |
6746 | ||
6747 | After the insn being reloaded, we write the following: | |
6748 | ||
47c8cf91 ILT |
6749 | For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed |
6750 | by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the | |
6751 | RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output | |
6752 | reloads for the operand. The RELOAD_OTHER output reloads are | |
6753 | output in descending order by reload number. */ | |
546b63fb | 6754 | |
c93b03c2 RH |
6755 | emit_insns_before (other_input_address_reload_insns, insn); |
6756 | emit_insns_before (other_input_reload_insns, insn); | |
546b63fb RK |
6757 | |
6758 | for (j = 0; j < reload_n_operands; j++) | |
6759 | { | |
c93b03c2 RH |
6760 | emit_insns_before (inpaddr_address_reload_insns[j], insn); |
6761 | emit_insns_before (input_address_reload_insns[j], insn); | |
6762 | emit_insns_before (input_reload_insns[j], insn); | |
546b63fb RK |
6763 | } |
6764 | ||
c93b03c2 RH |
6765 | emit_insns_before (other_operand_reload_insns, insn); |
6766 | emit_insns_before (operand_reload_insns, insn); | |
546b63fb RK |
6767 | |
6768 | for (j = 0; j < reload_n_operands; j++) | |
6769 | { | |
47c8cf91 | 6770 | emit_insns_before (outaddr_address_reload_insns[j], following_insn); |
546b63fb RK |
6771 | emit_insns_before (output_address_reload_insns[j], following_insn); |
6772 | emit_insns_before (output_reload_insns[j], following_insn); | |
befa01b9 | 6773 | emit_insns_before (other_output_reload_insns[j], following_insn); |
c93b03c2 RH |
6774 | } |
6775 | ||
6776 | /* Keep basic block info up to date. */ | |
6777 | if (n_basic_blocks) | |
6778 | { | |
3b413743 | 6779 | if (BLOCK_HEAD (chain->block) == insn) |
05d10675 | 6780 | BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn); |
3b413743 | 6781 | if (BLOCK_END (chain->block) == insn) |
05d10675 | 6782 | BLOCK_END (chain->block) = PREV_INSN (following_insn); |
546b63fb RK |
6783 | } |
6784 | ||
32131a9c RK |
6785 | /* For all the spill regs newly reloaded in this instruction, |
6786 | record what they were reloaded from, so subsequent instructions | |
d445b551 RK |
6787 | can inherit the reloads. |
6788 | ||
6789 | Update spill_reg_store for the reloads of this insn. | |
e9e79d69 | 6790 | Copy the elements that were updated in the loop above. */ |
32131a9c RK |
6791 | |
6792 | for (j = 0; j < n_reloads; j++) | |
6793 | { | |
6794 | register int r = reload_order[j]; | |
6795 | register int i = reload_spill_index[r]; | |
6796 | ||
78a2bc08 | 6797 | /* If this is a non-inherited input reload from a pseudo, we must |
05d10675 BS |
6798 | clear any memory of a previous store to the same pseudo. Only do |
6799 | something if there will not be an output reload for the pseudo | |
6800 | being reloaded. */ | |
eceef4c9 | 6801 | if (rld[r].in_reg != 0 |
05d10675 BS |
6802 | && ! (reload_inherited[r] || reload_override_in[r])) |
6803 | { | |
eceef4c9 | 6804 | rtx reg = rld[r].in_reg; |
78a2bc08 | 6805 | |
05d10675 | 6806 | if (GET_CODE (reg) == SUBREG) |
78a2bc08 | 6807 | reg = SUBREG_REG (reg); |
05d10675 BS |
6808 | |
6809 | if (GET_CODE (reg) == REG | |
78a2bc08 R |
6810 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER |
6811 | && ! reg_has_output_reload[REGNO (reg)]) | |
6812 | { | |
6813 | int nregno = REGNO (reg); | |
6814 | ||
6815 | if (reg_last_reload_reg[nregno]) | |
05d10675 BS |
6816 | { |
6817 | int last_regno = REGNO (reg_last_reload_reg[nregno]); | |
78a2bc08 | 6818 | |
05d10675 | 6819 | if (reg_reloaded_contents[last_regno] == nregno) |
78a2bc08 | 6820 | spill_reg_store[last_regno] = 0; |
05d10675 | 6821 | } |
78a2bc08 R |
6822 | } |
6823 | } | |
05d10675 | 6824 | |
e6e52be0 | 6825 | /* I is nonneg if this reload used a register. |
eceef4c9 | 6826 | If rld[r].reg_rtx is 0, this is an optional reload |
51f0c3b7 | 6827 | that we opted to ignore. */ |
d445b551 | 6828 | |
eceef4c9 | 6829 | if (i >= 0 && rld[r].reg_rtx != 0) |
32131a9c | 6830 | { |
32131a9c | 6831 | int nr |
eceef4c9 | 6832 | = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx)); |
32131a9c | 6833 | int k; |
51f0c3b7 JW |
6834 | int part_reaches_end = 0; |
6835 | int all_reaches_end = 1; | |
32131a9c | 6836 | |
51f0c3b7 JW |
6837 | /* For a multi register reload, we need to check if all or part |
6838 | of the value lives to the end. */ | |
32131a9c RK |
6839 | for (k = 0; k < nr; k++) |
6840 | { | |
eceef4c9 BS |
6841 | if (reload_reg_reaches_end_p (i + k, rld[r].opnum, |
6842 | rld[r].when_needed)) | |
51f0c3b7 JW |
6843 | part_reaches_end = 1; |
6844 | else | |
6845 | all_reaches_end = 0; | |
32131a9c RK |
6846 | } |
6847 | ||
51f0c3b7 JW |
6848 | /* Ignore reloads that don't reach the end of the insn in |
6849 | entirety. */ | |
6850 | if (all_reaches_end) | |
32131a9c | 6851 | { |
51f0c3b7 JW |
6852 | /* First, clear out memory of what used to be in this spill reg. |
6853 | If consecutive registers are used, clear them all. */ | |
d08ea79f | 6854 | |
32131a9c | 6855 | for (k = 0; k < nr; k++) |
e6e52be0 | 6856 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
d08ea79f | 6857 | |
51f0c3b7 | 6858 | /* Maybe the spill reg contains a copy of reload_out. */ |
eceef4c9 BS |
6859 | if (rld[r].out != 0 |
6860 | && (GET_CODE (rld[r].out) == REG | |
cb2afeb3 | 6861 | #ifdef AUTO_INC_DEC |
eceef4c9 | 6862 | || ! rld[r].out_reg |
cb2afeb3 | 6863 | #endif |
eceef4c9 | 6864 | || GET_CODE (rld[r].out_reg) == REG)) |
51f0c3b7 | 6865 | { |
eceef4c9 BS |
6866 | rtx out = (GET_CODE (rld[r].out) == REG |
6867 | ? rld[r].out | |
6868 | : rld[r].out_reg | |
6869 | ? rld[r].out_reg | |
6870 | /* AUTO_INC */ : XEXP (rld[r].in_reg, 0)); | |
cb2afeb3 | 6871 | register int nregno = REGNO (out); |
51f0c3b7 JW |
6872 | int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
6873 | : HARD_REGNO_NREGS (nregno, | |
eceef4c9 | 6874 | GET_MODE (rld[r].reg_rtx))); |
51f0c3b7 JW |
6875 | |
6876 | spill_reg_store[i] = new_spill_reg_store[i]; | |
cb2afeb3 | 6877 | spill_reg_stored_to[i] = out; |
eceef4c9 | 6878 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
51f0c3b7 JW |
6879 | |
6880 | /* If NREGNO is a hard register, it may occupy more than | |
05d10675 | 6881 | one register. If it does, say what is in the |
51f0c3b7 JW |
6882 | rest of the registers assuming that both registers |
6883 | agree on how many words the object takes. If not, | |
6884 | invalidate the subsequent registers. */ | |
6885 | ||
6886 | if (nregno < FIRST_PSEUDO_REGISTER) | |
6887 | for (k = 1; k < nnr; k++) | |
6888 | reg_last_reload_reg[nregno + k] | |
6889 | = (nr == nnr | |
eceef4c9 BS |
6890 | ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k], |
6891 | REGNO (rld[r].reg_rtx) + k) | |
51f0c3b7 JW |
6892 | : 0); |
6893 | ||
6894 | /* Now do the inverse operation. */ | |
6895 | for (k = 0; k < nr; k++) | |
6896 | { | |
e6e52be0 R |
6897 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
6898 | reg_reloaded_contents[i + k] | |
51f0c3b7 JW |
6899 | = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr |
6900 | ? nregno | |
6901 | : nregno + k); | |
e6e52be0 R |
6902 | reg_reloaded_insn[i + k] = insn; |
6903 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
51f0c3b7 JW |
6904 | } |
6905 | } | |
d08ea79f | 6906 | |
51f0c3b7 JW |
6907 | /* Maybe the spill reg contains a copy of reload_in. Only do |
6908 | something if there will not be an output reload for | |
6909 | the register being reloaded. */ | |
eceef4c9 BS |
6910 | else if (rld[r].out_reg == 0 |
6911 | && rld[r].in != 0 | |
6912 | && ((GET_CODE (rld[r].in) == REG | |
6913 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER | |
6914 | && ! reg_has_output_reload[REGNO (rld[r].in)]) | |
6915 | || (GET_CODE (rld[r].in_reg) == REG | |
6916 | && ! reg_has_output_reload[REGNO (rld[r].in_reg)])) | |
6917 | && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn))) | |
51f0c3b7 JW |
6918 | { |
6919 | register int nregno; | |
6920 | int nnr; | |
d445b551 | 6921 | |
eceef4c9 BS |
6922 | if (GET_CODE (rld[r].in) == REG |
6923 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER) | |
6924 | nregno = REGNO (rld[r].in); | |
6925 | else if (GET_CODE (rld[r].in_reg) == REG) | |
6926 | nregno = REGNO (rld[r].in_reg); | |
cb2afeb3 | 6927 | else |
eceef4c9 | 6928 | nregno = REGNO (XEXP (rld[r].in_reg, 0)); |
d08ea79f | 6929 | |
51f0c3b7 JW |
6930 | nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
6931 | : HARD_REGNO_NREGS (nregno, | |
eceef4c9 | 6932 | GET_MODE (rld[r].reg_rtx))); |
05d10675 | 6933 | |
eceef4c9 | 6934 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
51f0c3b7 JW |
6935 | |
6936 | if (nregno < FIRST_PSEUDO_REGISTER) | |
6937 | for (k = 1; k < nnr; k++) | |
6938 | reg_last_reload_reg[nregno + k] | |
6939 | = (nr == nnr | |
eceef4c9 BS |
6940 | ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k], |
6941 | REGNO (rld[r].reg_rtx) + k) | |
51f0c3b7 JW |
6942 | : 0); |
6943 | ||
6944 | /* Unless we inherited this reload, show we haven't | |
cb2afeb3 R |
6945 | recently done a store. |
6946 | Previous stores of inherited auto_inc expressions | |
6947 | also have to be discarded. */ | |
6948 | if (! reload_inherited[r] | |
eceef4c9 | 6949 | || (rld[r].out && ! rld[r].out_reg)) |
51f0c3b7 JW |
6950 | spill_reg_store[i] = 0; |
6951 | ||
6952 | for (k = 0; k < nr; k++) | |
6953 | { | |
e6e52be0 R |
6954 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
6955 | reg_reloaded_contents[i + k] | |
51f0c3b7 JW |
6956 | = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr |
6957 | ? nregno | |
6958 | : nregno + k); | |
e6e52be0 R |
6959 | reg_reloaded_insn[i + k] = insn; |
6960 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
51f0c3b7 JW |
6961 | } |
6962 | } | |
6963 | } | |
d445b551 | 6964 | |
51f0c3b7 JW |
6965 | /* However, if part of the reload reaches the end, then we must |
6966 | invalidate the old info for the part that survives to the end. */ | |
6967 | else if (part_reaches_end) | |
6968 | { | |
546b63fb | 6969 | for (k = 0; k < nr; k++) |
e6e52be0 | 6970 | if (reload_reg_reaches_end_p (i + k, |
eceef4c9 BS |
6971 | rld[r].opnum, |
6972 | rld[r].when_needed)) | |
e6e52be0 | 6973 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
32131a9c RK |
6974 | } |
6975 | } | |
6976 | ||
6977 | /* The following if-statement was #if 0'd in 1.34 (or before...). | |
6978 | It's reenabled in 1.35 because supposedly nothing else | |
6979 | deals with this problem. */ | |
6980 | ||
6981 | /* If a register gets output-reloaded from a non-spill register, | |
6982 | that invalidates any previous reloaded copy of it. | |
6983 | But forget_old_reloads_1 won't get to see it, because | |
6984 | it thinks only about the original insn. So invalidate it here. */ | |
eceef4c9 BS |
6985 | if (i < 0 && rld[r].out != 0 |
6986 | && (GET_CODE (rld[r].out) == REG | |
6987 | || (GET_CODE (rld[r].out) == MEM | |
6988 | && GET_CODE (rld[r].out_reg) == REG))) | |
32131a9c | 6989 | { |
eceef4c9 BS |
6990 | rtx out = (GET_CODE (rld[r].out) == REG |
6991 | ? rld[r].out : rld[r].out_reg); | |
cb2afeb3 | 6992 | register int nregno = REGNO (out); |
c7093272 | 6993 | if (nregno >= FIRST_PSEUDO_REGISTER) |
cb2afeb3 | 6994 | { |
6a651371 | 6995 | rtx src_reg, store_insn = NULL_RTX; |
cb2afeb3 R |
6996 | |
6997 | reg_last_reload_reg[nregno] = 0; | |
6998 | ||
6999 | /* If we can find a hard register that is stored, record | |
7000 | the storing insn so that we may delete this insn with | |
7001 | delete_output_reload. */ | |
eceef4c9 | 7002 | src_reg = rld[r].reg_rtx; |
cb2afeb3 R |
7003 | |
7004 | /* If this is an optional reload, try to find the source reg | |
7005 | from an input reload. */ | |
7006 | if (! src_reg) | |
7007 | { | |
7008 | rtx set = single_set (insn); | |
eceef4c9 | 7009 | if (set && SET_DEST (set) == rld[r].out) |
cb2afeb3 R |
7010 | { |
7011 | int k; | |
7012 | ||
7013 | src_reg = SET_SRC (set); | |
7014 | store_insn = insn; | |
7015 | for (k = 0; k < n_reloads; k++) | |
7016 | { | |
eceef4c9 | 7017 | if (rld[k].in == src_reg) |
cb2afeb3 | 7018 | { |
eceef4c9 | 7019 | src_reg = rld[k].reg_rtx; |
cb2afeb3 R |
7020 | break; |
7021 | } | |
7022 | } | |
7023 | } | |
7024 | } | |
7025 | else | |
7026 | store_insn = new_spill_reg_store[REGNO (src_reg)]; | |
7027 | if (src_reg && GET_CODE (src_reg) == REG | |
7028 | && REGNO (src_reg) < FIRST_PSEUDO_REGISTER) | |
7029 | { | |
7030 | int src_regno = REGNO (src_reg); | |
8ec450a4 | 7031 | int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode); |
cb2afeb3 R |
7032 | /* The place where to find a death note varies with |
7033 | PRESERVE_DEATH_INFO_REGNO_P . The condition is not | |
7034 | necessarily checked exactly in the code that moves | |
7035 | notes, so just check both locations. */ | |
7036 | rtx note = find_regno_note (insn, REG_DEAD, src_regno); | |
7037 | if (! note) | |
7038 | note = find_regno_note (store_insn, REG_DEAD, src_regno); | |
7039 | while (nr-- > 0) | |
7040 | { | |
7041 | spill_reg_store[src_regno + nr] = store_insn; | |
7042 | spill_reg_stored_to[src_regno + nr] = out; | |
7043 | reg_reloaded_contents[src_regno + nr] = nregno; | |
7044 | reg_reloaded_insn[src_regno + nr] = store_insn; | |
00f9f1bc | 7045 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr); |
cb2afeb3 R |
7046 | SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr); |
7047 | SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr); | |
7048 | if (note) | |
7049 | SET_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7050 | else | |
7051 | CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7052 | } | |
7053 | reg_last_reload_reg[nregno] = src_reg; | |
7054 | } | |
7055 | } | |
c7093272 RK |
7056 | else |
7057 | { | |
eceef4c9 | 7058 | int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (rld[r].out)); |
36281332 | 7059 | |
c7093272 RK |
7060 | while (num_regs-- > 0) |
7061 | reg_last_reload_reg[nregno + num_regs] = 0; | |
7062 | } | |
32131a9c RK |
7063 | } |
7064 | } | |
e6e52be0 | 7065 | IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died); |
32131a9c RK |
7066 | } |
7067 | \f | |
5e03c156 RK |
7068 | /* Emit code to perform a reload from IN (which may be a reload register) to |
7069 | OUT (which may also be a reload register). IN or OUT is from operand | |
05d10675 | 7070 | OPNUM with reload type TYPE. |
546b63fb | 7071 | |
3c3eeea6 | 7072 | Returns first insn emitted. */ |
32131a9c RK |
7073 | |
7074 | rtx | |
5e03c156 RK |
7075 | gen_reload (out, in, opnum, type) |
7076 | rtx out; | |
32131a9c | 7077 | rtx in; |
546b63fb RK |
7078 | int opnum; |
7079 | enum reload_type type; | |
32131a9c | 7080 | { |
546b63fb | 7081 | rtx last = get_last_insn (); |
7a5b18b0 RK |
7082 | rtx tem; |
7083 | ||
7084 | /* If IN is a paradoxical SUBREG, remove it and try to put the | |
7085 | opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ | |
7086 | if (GET_CODE (in) == SUBREG | |
7087 | && (GET_MODE_SIZE (GET_MODE (in)) | |
7088 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
7089 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0) | |
7090 | in = SUBREG_REG (in), out = tem; | |
7091 | else if (GET_CODE (out) == SUBREG | |
eceef4c9 BS |
7092 | && (GET_MODE_SIZE (GET_MODE (out)) |
7093 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) | |
7094 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0) | |
7a5b18b0 | 7095 | out = SUBREG_REG (out), in = tem; |
32131a9c | 7096 | |
a8fdc208 | 7097 | /* How to do this reload can get quite tricky. Normally, we are being |
32131a9c RK |
7098 | asked to reload a simple operand, such as a MEM, a constant, or a pseudo |
7099 | register that didn't get a hard register. In that case we can just | |
7100 | call emit_move_insn. | |
7101 | ||
a7fd196c JW |
7102 | We can also be asked to reload a PLUS that adds a register or a MEM to |
7103 | another register, constant or MEM. This can occur during frame pointer | |
7104 | elimination and while reloading addresses. This case is handled by | |
7105 | trying to emit a single insn to perform the add. If it is not valid, | |
7106 | we use a two insn sequence. | |
32131a9c RK |
7107 | |
7108 | Finally, we could be called to handle an 'o' constraint by putting | |
7109 | an address into a register. In that case, we first try to do this | |
7110 | with a named pattern of "reload_load_address". If no such pattern | |
7111 | exists, we just emit a SET insn and hope for the best (it will normally | |
7112 | be valid on machines that use 'o'). | |
7113 | ||
7114 | This entire process is made complex because reload will never | |
7115 | process the insns we generate here and so we must ensure that | |
7116 | they will fit their constraints and also by the fact that parts of | |
7117 | IN might be being reloaded separately and replaced with spill registers. | |
7118 | Because of this, we are, in some sense, just guessing the right approach | |
7119 | here. The one listed above seems to work. | |
7120 | ||
7121 | ??? At some point, this whole thing needs to be rethought. */ | |
7122 | ||
7123 | if (GET_CODE (in) == PLUS | |
a7fd196c | 7124 | && (GET_CODE (XEXP (in, 0)) == REG |
5c6b1bd2 | 7125 | || GET_CODE (XEXP (in, 0)) == SUBREG |
a7fd196c JW |
7126 | || GET_CODE (XEXP (in, 0)) == MEM) |
7127 | && (GET_CODE (XEXP (in, 1)) == REG | |
5c6b1bd2 | 7128 | || GET_CODE (XEXP (in, 1)) == SUBREG |
a7fd196c JW |
7129 | || CONSTANT_P (XEXP (in, 1)) |
7130 | || GET_CODE (XEXP (in, 1)) == MEM)) | |
32131a9c | 7131 | { |
a7fd196c JW |
7132 | /* We need to compute the sum of a register or a MEM and another |
7133 | register, constant, or MEM, and put it into the reload | |
3002e160 JW |
7134 | register. The best possible way of doing this is if the machine |
7135 | has a three-operand ADD insn that accepts the required operands. | |
32131a9c RK |
7136 | |
7137 | The simplest approach is to try to generate such an insn and see if it | |
7138 | is recognized and matches its constraints. If so, it can be used. | |
7139 | ||
7140 | It might be better not to actually emit the insn unless it is valid, | |
0009eff2 | 7141 | but we need to pass the insn as an operand to `recog' and |
0eadeb15 | 7142 | `extract_insn' and it is simpler to emit and then delete the insn if |
0009eff2 | 7143 | not valid than to dummy things up. */ |
a8fdc208 | 7144 | |
af929c62 | 7145 | rtx op0, op1, tem, insn; |
32131a9c | 7146 | int code; |
a8fdc208 | 7147 | |
af929c62 RK |
7148 | op0 = find_replacement (&XEXP (in, 0)); |
7149 | op1 = find_replacement (&XEXP (in, 1)); | |
7150 | ||
32131a9c RK |
7151 | /* Since constraint checking is strict, commutativity won't be |
7152 | checked, so we need to do that here to avoid spurious failure | |
7153 | if the add instruction is two-address and the second operand | |
7154 | of the add is the same as the reload reg, which is frequently | |
7155 | the case. If the insn would be A = B + A, rearrange it so | |
0f41302f | 7156 | it will be A = A + B as constrain_operands expects. */ |
a8fdc208 | 7157 | |
32131a9c | 7158 | if (GET_CODE (XEXP (in, 1)) == REG |
5e03c156 | 7159 | && REGNO (out) == REGNO (XEXP (in, 1))) |
af929c62 RK |
7160 | tem = op0, op0 = op1, op1 = tem; |
7161 | ||
7162 | if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) | |
38a448ca | 7163 | in = gen_rtx_PLUS (GET_MODE (in), op0, op1); |
32131a9c | 7164 | |
38a448ca | 7165 | insn = emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
32131a9c RK |
7166 | code = recog_memoized (insn); |
7167 | ||
7168 | if (code >= 0) | |
7169 | { | |
0eadeb15 | 7170 | extract_insn (insn); |
32131a9c RK |
7171 | /* We want constrain operands to treat this insn strictly in |
7172 | its validity determination, i.e., the way it would after reload | |
7173 | has completed. */ | |
0eadeb15 | 7174 | if (constrain_operands (1)) |
32131a9c RK |
7175 | return insn; |
7176 | } | |
7177 | ||
546b63fb | 7178 | delete_insns_since (last); |
32131a9c RK |
7179 | |
7180 | /* If that failed, we must use a conservative two-insn sequence. | |
09522f21 FS |
7181 | |
7182 | Use a move to copy one operand into the reload register. Prefer | |
7183 | to reload a constant, MEM or pseudo since the move patterns can | |
7184 | handle an arbitrary operand. If OP1 is not a constant, MEM or | |
7185 | pseudo and OP1 is not a valid operand for an add instruction, then | |
7186 | reload OP1. | |
7187 | ||
7188 | After reloading one of the operands into the reload register, add | |
7189 | the reload register to the output register. | |
32131a9c RK |
7190 | |
7191 | If there is another way to do this for a specific machine, a | |
7192 | DEFINE_PEEPHOLE should be specified that recognizes the sequence | |
7193 | we emit below. */ | |
7194 | ||
09522f21 FS |
7195 | code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code; |
7196 | ||
5c6b1bd2 | 7197 | if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG |
af929c62 | 7198 | || (GET_CODE (op1) == REG |
09522f21 FS |
7199 | && REGNO (op1) >= FIRST_PSEUDO_REGISTER) |
7200 | || (code != CODE_FOR_nothing | |
a995e389 RH |
7201 | && ! ((*insn_data[code].operand[2].predicate) |
7202 | (op1, insn_data[code].operand[2].mode)))) | |
af929c62 | 7203 | tem = op0, op0 = op1, op1 = tem; |
32131a9c | 7204 | |
5c6b1bd2 | 7205 | gen_reload (out, op0, opnum, type); |
39b56c2a | 7206 | |
5e03c156 | 7207 | /* If OP0 and OP1 are the same, we can use OUT for OP1. |
39b56c2a RK |
7208 | This fixes a problem on the 32K where the stack pointer cannot |
7209 | be used as an operand of an add insn. */ | |
7210 | ||
7211 | if (rtx_equal_p (op0, op1)) | |
5e03c156 | 7212 | op1 = out; |
39b56c2a | 7213 | |
5e03c156 | 7214 | insn = emit_insn (gen_add2_insn (out, op1)); |
c77c9766 RK |
7215 | |
7216 | /* If that failed, copy the address register to the reload register. | |
0f41302f | 7217 | Then add the constant to the reload register. */ |
c77c9766 RK |
7218 | |
7219 | code = recog_memoized (insn); | |
7220 | ||
7221 | if (code >= 0) | |
7222 | { | |
0eadeb15 | 7223 | extract_insn (insn); |
c77c9766 RK |
7224 | /* We want constrain operands to treat this insn strictly in |
7225 | its validity determination, i.e., the way it would after reload | |
7226 | has completed. */ | |
0eadeb15 | 7227 | if (constrain_operands (1)) |
4117a96b R |
7228 | { |
7229 | /* Add a REG_EQUIV note so that find_equiv_reg can find it. */ | |
7230 | REG_NOTES (insn) | |
9e6a5703 | 7231 | = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); |
4117a96b R |
7232 | return insn; |
7233 | } | |
c77c9766 RK |
7234 | } |
7235 | ||
7236 | delete_insns_since (last); | |
7237 | ||
5c6b1bd2 | 7238 | gen_reload (out, op1, opnum, type); |
4117a96b | 7239 | insn = emit_insn (gen_add2_insn (out, op0)); |
9e6a5703 | 7240 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); |
32131a9c RK |
7241 | } |
7242 | ||
0dadecf6 RK |
7243 | #ifdef SECONDARY_MEMORY_NEEDED |
7244 | /* If we need a memory location to do the move, do it that way. */ | |
7245 | else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER | |
5e03c156 | 7246 | && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER |
0dadecf6 | 7247 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), |
5e03c156 RK |
7248 | REGNO_REG_CLASS (REGNO (out)), |
7249 | GET_MODE (out))) | |
0dadecf6 RK |
7250 | { |
7251 | /* Get the memory to use and rewrite both registers to its mode. */ | |
5e03c156 | 7252 | rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type); |
0dadecf6 | 7253 | |
5e03c156 | 7254 | if (GET_MODE (loc) != GET_MODE (out)) |
38a448ca | 7255 | out = gen_rtx_REG (GET_MODE (loc), REGNO (out)); |
0dadecf6 RK |
7256 | |
7257 | if (GET_MODE (loc) != GET_MODE (in)) | |
38a448ca | 7258 | in = gen_rtx_REG (GET_MODE (loc), REGNO (in)); |
0dadecf6 | 7259 | |
5c6b1bd2 RK |
7260 | gen_reload (loc, in, opnum, type); |
7261 | gen_reload (out, loc, opnum, type); | |
0dadecf6 RK |
7262 | } |
7263 | #endif | |
7264 | ||
32131a9c RK |
7265 | /* If IN is a simple operand, use gen_move_insn. */ |
7266 | else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG) | |
5e03c156 | 7267 | emit_insn (gen_move_insn (out, in)); |
32131a9c RK |
7268 | |
7269 | #ifdef HAVE_reload_load_address | |
7270 | else if (HAVE_reload_load_address) | |
5e03c156 | 7271 | emit_insn (gen_reload_load_address (out, in)); |
32131a9c RK |
7272 | #endif |
7273 | ||
5e03c156 | 7274 | /* Otherwise, just write (set OUT IN) and hope for the best. */ |
32131a9c | 7275 | else |
38a448ca | 7276 | emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
32131a9c RK |
7277 | |
7278 | /* Return the first insn emitted. | |
546b63fb | 7279 | We can not just return get_last_insn, because there may have |
32131a9c RK |
7280 | been multiple instructions emitted. Also note that gen_move_insn may |
7281 | emit more than one insn itself, so we can not assume that there is one | |
7282 | insn emitted per emit_insn_before call. */ | |
7283 | ||
546b63fb | 7284 | return last ? NEXT_INSN (last) : get_insns (); |
32131a9c RK |
7285 | } |
7286 | \f | |
7287 | /* Delete a previously made output-reload | |
7288 | whose result we now believe is not needed. | |
7289 | First we double-check. | |
7290 | ||
7291 | INSN is the insn now being processed. | |
cb2afeb3 R |
7292 | LAST_RELOAD_REG is the hard register number for which we want to delete |
7293 | the last output reload. | |
7294 | J is the reload-number that originally used REG. The caller has made | |
7295 | certain that reload J doesn't use REG any longer for input. */ | |
32131a9c RK |
7296 | |
7297 | static void | |
cb2afeb3 | 7298 | delete_output_reload (insn, j, last_reload_reg) |
32131a9c RK |
7299 | rtx insn; |
7300 | int j; | |
cb2afeb3 | 7301 | int last_reload_reg; |
32131a9c | 7302 | { |
cb2afeb3 R |
7303 | rtx output_reload_insn = spill_reg_store[last_reload_reg]; |
7304 | rtx reg = spill_reg_stored_to[last_reload_reg]; | |
7305 | int k; | |
7306 | int n_occurrences; | |
7307 | int n_inherited = 0; | |
32131a9c | 7308 | register rtx i1; |
cb2afeb3 | 7309 | rtx substed; |
05d10675 | 7310 | |
32131a9c RK |
7311 | /* Get the raw pseudo-register referred to. */ |
7312 | ||
32131a9c RK |
7313 | while (GET_CODE (reg) == SUBREG) |
7314 | reg = SUBREG_REG (reg); | |
cb2afeb3 R |
7315 | substed = reg_equiv_memory_loc[REGNO (reg)]; |
7316 | ||
7317 | /* This is unsafe if the operand occurs more often in the current | |
7318 | insn than it is inherited. */ | |
7319 | for (k = n_reloads - 1; k >= 0; k--) | |
7320 | { | |
eceef4c9 | 7321 | rtx reg2 = rld[k].in; |
cb2afeb3 R |
7322 | if (! reg2) |
7323 | continue; | |
7324 | if (GET_CODE (reg2) == MEM || reload_override_in[k]) | |
eceef4c9 | 7325 | reg2 = rld[k].in_reg; |
cb2afeb3 | 7326 | #ifdef AUTO_INC_DEC |
eceef4c9 BS |
7327 | if (rld[k].out && ! rld[k].out_reg) |
7328 | reg2 = XEXP (rld[k].in_reg, 0); | |
cb2afeb3 R |
7329 | #endif |
7330 | while (GET_CODE (reg2) == SUBREG) | |
7331 | reg2 = SUBREG_REG (reg2); | |
7332 | if (rtx_equal_p (reg2, reg)) | |
2eb6dac7 AS |
7333 | { |
7334 | if (reload_inherited[k] || reload_override_in[k] || k == j) | |
7335 | { | |
cb2afeb3 | 7336 | n_inherited++; |
eceef4c9 | 7337 | reg2 = rld[k].out_reg; |
2eb6dac7 AS |
7338 | if (! reg2) |
7339 | continue; | |
7340 | while (GET_CODE (reg2) == SUBREG) | |
7341 | reg2 = XEXP (reg2, 0); | |
7342 | if (rtx_equal_p (reg2, reg)) | |
7343 | n_inherited++; | |
7344 | } | |
7345 | else | |
7346 | return; | |
7347 | } | |
cb2afeb3 R |
7348 | } |
7349 | n_occurrences = count_occurrences (PATTERN (insn), reg); | |
7350 | if (substed) | |
7351 | n_occurrences += count_occurrences (PATTERN (insn), substed); | |
7352 | if (n_occurrences > n_inherited) | |
7353 | return; | |
32131a9c RK |
7354 | |
7355 | /* If the pseudo-reg we are reloading is no longer referenced | |
7356 | anywhere between the store into it and here, | |
7357 | and no jumps or labels intervene, then the value can get | |
7358 | here through the reload reg alone. | |
7359 | Otherwise, give up--return. */ | |
7360 | for (i1 = NEXT_INSN (output_reload_insn); | |
7361 | i1 != insn; i1 = NEXT_INSN (i1)) | |
7362 | { | |
7363 | if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN) | |
7364 | return; | |
7365 | if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN) | |
7366 | && reg_mentioned_p (reg, PATTERN (i1))) | |
aa6498c2 | 7367 | { |
cb2afeb3 R |
7368 | /* If this is USE in front of INSN, we only have to check that |
7369 | there are no more references than accounted for by inheritance. */ | |
7370 | while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE) | |
aa6498c2 | 7371 | { |
cb2afeb3 | 7372 | n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0; |
aa6498c2 R |
7373 | i1 = NEXT_INSN (i1); |
7374 | } | |
cb2afeb3 | 7375 | if (n_occurrences <= n_inherited && i1 == insn) |
aa6498c2 R |
7376 | break; |
7377 | return; | |
7378 | } | |
32131a9c RK |
7379 | } |
7380 | ||
aa6498c2 R |
7381 | /* The caller has already checked that REG dies or is set in INSN. |
7382 | It has also checked that we are optimizing, and thus some inaccurancies | |
7383 | in the debugging information are acceptable. | |
7384 | So we could just delete output_reload_insn. | |
7385 | But in some cases we can improve the debugging information without | |
7386 | sacrificing optimization - maybe even improving the code: | |
7387 | See if the pseudo reg has been completely replaced | |
32131a9c RK |
7388 | with reload regs. If so, delete the store insn |
7389 | and forget we had a stack slot for the pseudo. */ | |
eceef4c9 | 7390 | if (rld[j].out != rld[j].in |
aa6498c2 | 7391 | && REG_N_DEATHS (REGNO (reg)) == 1 |
a3a24aa6 | 7392 | && REG_N_SETS (REGNO (reg)) == 1 |
aa6498c2 R |
7393 | && REG_BASIC_BLOCK (REGNO (reg)) >= 0 |
7394 | && find_regno_note (insn, REG_DEAD, REGNO (reg))) | |
32131a9c RK |
7395 | { |
7396 | rtx i2; | |
7397 | ||
7398 | /* We know that it was used only between here | |
7399 | and the beginning of the current basic block. | |
7400 | (We also know that the last use before INSN was | |
7401 | the output reload we are thinking of deleting, but never mind that.) | |
7402 | Search that range; see if any ref remains. */ | |
7403 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) | |
7404 | { | |
d445b551 RK |
7405 | rtx set = single_set (i2); |
7406 | ||
32131a9c RK |
7407 | /* Uses which just store in the pseudo don't count, |
7408 | since if they are the only uses, they are dead. */ | |
d445b551 | 7409 | if (set != 0 && SET_DEST (set) == reg) |
32131a9c RK |
7410 | continue; |
7411 | if (GET_CODE (i2) == CODE_LABEL | |
7412 | || GET_CODE (i2) == JUMP_INSN) | |
7413 | break; | |
7414 | if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN) | |
7415 | && reg_mentioned_p (reg, PATTERN (i2))) | |
aa6498c2 R |
7416 | { |
7417 | /* Some other ref remains; just delete the output reload we | |
7418 | know to be dead. */ | |
cb2afeb3 R |
7419 | delete_address_reloads (output_reload_insn, insn); |
7420 | PUT_CODE (output_reload_insn, NOTE); | |
7421 | NOTE_SOURCE_FILE (output_reload_insn) = 0; | |
7422 | NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED; | |
aa6498c2 R |
7423 | return; |
7424 | } | |
32131a9c RK |
7425 | } |
7426 | ||
7427 | /* Delete the now-dead stores into this pseudo. */ | |
7428 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) | |
7429 | { | |
d445b551 RK |
7430 | rtx set = single_set (i2); |
7431 | ||
7432 | if (set != 0 && SET_DEST (set) == reg) | |
5507b94b | 7433 | { |
cb2afeb3 | 7434 | delete_address_reloads (i2, insn); |
5507b94b RK |
7435 | /* This might be a basic block head, |
7436 | thus don't use delete_insn. */ | |
7437 | PUT_CODE (i2, NOTE); | |
7438 | NOTE_SOURCE_FILE (i2) = 0; | |
7439 | NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED; | |
7440 | } | |
32131a9c RK |
7441 | if (GET_CODE (i2) == CODE_LABEL |
7442 | || GET_CODE (i2) == JUMP_INSN) | |
7443 | break; | |
7444 | } | |
7445 | ||
7446 | /* For the debugging info, | |
7447 | say the pseudo lives in this reload reg. */ | |
eceef4c9 | 7448 | reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx); |
32131a9c RK |
7449 | alter_reg (REGNO (reg), -1); |
7450 | } | |
cb2afeb3 R |
7451 | delete_address_reloads (output_reload_insn, insn); |
7452 | PUT_CODE (output_reload_insn, NOTE); | |
7453 | NOTE_SOURCE_FILE (output_reload_insn) = 0; | |
7454 | NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED; | |
7455 | ||
7456 | } | |
7457 | ||
7458 | /* We are going to delete DEAD_INSN. Recursively delete loads of | |
7459 | reload registers used in DEAD_INSN that are not used till CURRENT_INSN. | |
7460 | CURRENT_INSN is being reloaded, so we have to check its reloads too. */ | |
7461 | static void | |
7462 | delete_address_reloads (dead_insn, current_insn) | |
7463 | rtx dead_insn, current_insn; | |
7464 | { | |
7465 | rtx set = single_set (dead_insn); | |
7466 | rtx set2, dst, prev, next; | |
7467 | if (set) | |
7468 | { | |
7469 | rtx dst = SET_DEST (set); | |
7470 | if (GET_CODE (dst) == MEM) | |
7471 | delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn); | |
7472 | } | |
7473 | /* If we deleted the store from a reloaded post_{in,de}c expression, | |
7474 | we can delete the matching adds. */ | |
7475 | prev = PREV_INSN (dead_insn); | |
7476 | next = NEXT_INSN (dead_insn); | |
7477 | if (! prev || ! next) | |
7478 | return; | |
7479 | set = single_set (next); | |
7480 | set2 = single_set (prev); | |
7481 | if (! set || ! set2 | |
7482 | || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS | |
7483 | || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT | |
7484 | || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT) | |
7485 | return; | |
7486 | dst = SET_DEST (set); | |
7487 | if (! rtx_equal_p (dst, SET_DEST (set2)) | |
7488 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0)) | |
7489 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0)) | |
7490 | || (INTVAL (XEXP (SET_SRC (set), 1)) | |
7491 | != - INTVAL (XEXP (SET_SRC (set2), 1)))) | |
7492 | return; | |
7493 | delete_insn (prev); | |
7494 | delete_insn (next); | |
7495 | } | |
7496 | ||
7497 | /* Subfunction of delete_address_reloads: process registers found in X. */ | |
7498 | static void | |
7499 | delete_address_reloads_1 (dead_insn, x, current_insn) | |
7500 | rtx dead_insn, x, current_insn; | |
7501 | { | |
7502 | rtx prev, set, dst, i2; | |
7503 | int i, j; | |
7504 | enum rtx_code code = GET_CODE (x); | |
7505 | ||
7506 | if (code != REG) | |
7507 | { | |
6f7d635c | 7508 | const char *fmt= GET_RTX_FORMAT (code); |
cb2afeb3 R |
7509 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
7510 | { | |
7511 | if (fmt[i] == 'e') | |
7512 | delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn); | |
7513 | else if (fmt[i] == 'E') | |
7514 | { | |
7515 | for (j = XVECLEN (x, i) - 1; j >=0; j--) | |
7516 | delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j), | |
7517 | current_insn); | |
7518 | } | |
7519 | } | |
7520 | return; | |
7521 | } | |
7522 | ||
7523 | if (spill_reg_order[REGNO (x)] < 0) | |
7524 | return; | |
aa6498c2 | 7525 | |
cb2afeb3 R |
7526 | /* Scan backwards for the insn that sets x. This might be a way back due |
7527 | to inheritance. */ | |
7528 | for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev)) | |
7529 | { | |
7530 | code = GET_CODE (prev); | |
7531 | if (code == CODE_LABEL || code == JUMP_INSN) | |
7532 | return; | |
7533 | if (GET_RTX_CLASS (code) != 'i') | |
7534 | continue; | |
7535 | if (reg_set_p (x, PATTERN (prev))) | |
7536 | break; | |
7537 | if (reg_referenced_p (x, PATTERN (prev))) | |
7538 | return; | |
7539 | } | |
7540 | if (! prev || INSN_UID (prev) < reload_first_uid) | |
7541 | return; | |
7542 | /* Check that PREV only sets the reload register. */ | |
7543 | set = single_set (prev); | |
7544 | if (! set) | |
7545 | return; | |
7546 | dst = SET_DEST (set); | |
7547 | if (GET_CODE (dst) != REG | |
7548 | || ! rtx_equal_p (dst, x)) | |
7549 | return; | |
7550 | if (! reg_set_p (dst, PATTERN (dead_insn))) | |
7551 | { | |
7552 | /* Check if DST was used in a later insn - | |
7553 | it might have been inherited. */ | |
7554 | for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2)) | |
7555 | { | |
7556 | if (GET_CODE (i2) == CODE_LABEL) | |
7557 | break; | |
7558 | if (GET_RTX_CLASS (GET_CODE (i2)) != 'i') | |
7559 | continue; | |
7560 | if (reg_referenced_p (dst, PATTERN (i2))) | |
7561 | { | |
7562 | /* If there is a reference to the register in the current insn, | |
7563 | it might be loaded in a non-inherited reload. If no other | |
7564 | reload uses it, that means the register is set before | |
7565 | referenced. */ | |
7566 | if (i2 == current_insn) | |
7567 | { | |
7568 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7569 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
7570 | || reload_override_in[j] == dst) |
7571 | return; | |
7572 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7573 | if (rld[j].in && rld[j].reg_rtx == dst) |
cb2afeb3 R |
7574 | break; |
7575 | if (j >= 0) | |
7576 | break; | |
7577 | } | |
7578 | return; | |
7579 | } | |
7580 | if (GET_CODE (i2) == JUMP_INSN) | |
7581 | break; | |
cb2afeb3 | 7582 | /* If DST is still live at CURRENT_INSN, check if it is used for |
3900dc09 R |
7583 | any reload. Note that even if CURRENT_INSN sets DST, we still |
7584 | have to check the reloads. */ | |
cb2afeb3 R |
7585 | if (i2 == current_insn) |
7586 | { | |
7587 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7588 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
7589 | || reload_override_in[j] == dst) |
7590 | return; | |
7591 | /* ??? We can't finish the loop here, because dst might be | |
7592 | allocated to a pseudo in this block if no reload in this | |
7593 | block needs any of the clsses containing DST - see | |
7594 | spill_hard_reg. There is no easy way to tell this, so we | |
7595 | have to scan till the end of the basic block. */ | |
7596 | } | |
3900dc09 R |
7597 | if (reg_set_p (dst, PATTERN (i2))) |
7598 | break; | |
cb2afeb3 R |
7599 | } |
7600 | } | |
7601 | delete_address_reloads_1 (prev, SET_SRC (set), current_insn); | |
7602 | reg_reloaded_contents[REGNO (dst)] = -1; | |
7603 | /* Can't use delete_insn here because PREV might be a basic block head. */ | |
7604 | PUT_CODE (prev, NOTE); | |
7605 | NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED; | |
7606 | NOTE_SOURCE_FILE (prev) = 0; | |
32131a9c | 7607 | } |
32131a9c | 7608 | \f |
a8fdc208 | 7609 | /* Output reload-insns to reload VALUE into RELOADREG. |
858a47b1 | 7610 | VALUE is an autoincrement or autodecrement RTX whose operand |
32131a9c RK |
7611 | is a register or memory location; |
7612 | so reloading involves incrementing that location. | |
cb2afeb3 | 7613 | IN is either identical to VALUE, or some cheaper place to reload from. |
32131a9c RK |
7614 | |
7615 | INC_AMOUNT is the number to increment or decrement by (always positive). | |
cb2afeb3 | 7616 | This cannot be deduced from VALUE. |
32131a9c | 7617 | |
cb2afeb3 R |
7618 | Return the instruction that stores into RELOADREG. */ |
7619 | ||
7620 | static rtx | |
7621 | inc_for_reload (reloadreg, in, value, inc_amount) | |
32131a9c | 7622 | rtx reloadreg; |
cb2afeb3 | 7623 | rtx in, value; |
32131a9c | 7624 | int inc_amount; |
32131a9c RK |
7625 | { |
7626 | /* REG or MEM to be copied and incremented. */ | |
7627 | rtx incloc = XEXP (value, 0); | |
7628 | /* Nonzero if increment after copying. */ | |
7629 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC); | |
546b63fb | 7630 | rtx last; |
0009eff2 RK |
7631 | rtx inc; |
7632 | rtx add_insn; | |
7633 | int code; | |
cb2afeb3 R |
7634 | rtx store; |
7635 | rtx real_in = in == value ? XEXP (in, 0) : in; | |
32131a9c RK |
7636 | |
7637 | /* No hard register is equivalent to this register after | |
7638 | inc/dec operation. If REG_LAST_RELOAD_REG were non-zero, | |
7639 | we could inc/dec that register as well (maybe even using it for | |
7640 | the source), but I'm not sure it's worth worrying about. */ | |
7641 | if (GET_CODE (incloc) == REG) | |
7642 | reg_last_reload_reg[REGNO (incloc)] = 0; | |
7643 | ||
7644 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
7645 | inc_amount = - inc_amount; | |
7646 | ||
fb3821f7 | 7647 | inc = GEN_INT (inc_amount); |
0009eff2 RK |
7648 | |
7649 | /* If this is post-increment, first copy the location to the reload reg. */ | |
cb2afeb3 R |
7650 | if (post && real_in != reloadreg) |
7651 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
0009eff2 | 7652 | |
cb2afeb3 R |
7653 | if (in == value) |
7654 | { | |
7655 | /* See if we can directly increment INCLOC. Use a method similar to | |
7656 | that in gen_reload. */ | |
0009eff2 | 7657 | |
cb2afeb3 R |
7658 | last = get_last_insn (); |
7659 | add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc, | |
7660 | gen_rtx_PLUS (GET_MODE (incloc), | |
7661 | incloc, inc))); | |
05d10675 | 7662 | |
cb2afeb3 R |
7663 | code = recog_memoized (add_insn); |
7664 | if (code >= 0) | |
32131a9c | 7665 | { |
0eadeb15 BS |
7666 | extract_insn (add_insn); |
7667 | if (constrain_operands (1)) | |
cb2afeb3 R |
7668 | { |
7669 | /* If this is a pre-increment and we have incremented the value | |
7670 | where it lives, copy the incremented value to RELOADREG to | |
7671 | be used as an address. */ | |
0009eff2 | 7672 | |
cb2afeb3 R |
7673 | if (! post) |
7674 | emit_insn (gen_move_insn (reloadreg, incloc)); | |
546b63fb | 7675 | |
cb2afeb3 R |
7676 | return add_insn; |
7677 | } | |
32131a9c | 7678 | } |
cb2afeb3 | 7679 | delete_insns_since (last); |
32131a9c | 7680 | } |
0009eff2 | 7681 | |
0009eff2 RK |
7682 | /* If couldn't do the increment directly, must increment in RELOADREG. |
7683 | The way we do this depends on whether this is pre- or post-increment. | |
7684 | For pre-increment, copy INCLOC to the reload register, increment it | |
7685 | there, then save back. */ | |
7686 | ||
7687 | if (! post) | |
7688 | { | |
cb2afeb3 R |
7689 | if (in != reloadreg) |
7690 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
546b63fb | 7691 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 7692 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
0009eff2 | 7693 | } |
32131a9c RK |
7694 | else |
7695 | { | |
0009eff2 RK |
7696 | /* Postincrement. |
7697 | Because this might be a jump insn or a compare, and because RELOADREG | |
7698 | may not be available after the insn in an input reload, we must do | |
7699 | the incrementation before the insn being reloaded for. | |
7700 | ||
cb2afeb3 | 7701 | We have already copied IN to RELOADREG. Increment the copy in |
0009eff2 RK |
7702 | RELOADREG, save that back, then decrement RELOADREG so it has |
7703 | the original value. */ | |
7704 | ||
546b63fb | 7705 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 7706 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
546b63fb | 7707 | emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount))); |
32131a9c | 7708 | } |
0009eff2 | 7709 | |
cb2afeb3 | 7710 | return store; |
32131a9c RK |
7711 | } |
7712 | \f | |
7713 | /* Return 1 if we are certain that the constraint-string STRING allows | |
7714 | the hard register REG. Return 0 if we can't be sure of this. */ | |
7715 | ||
7716 | static int | |
7717 | constraint_accepts_reg_p (string, reg) | |
9b3142b3 | 7718 | const char *string; |
32131a9c RK |
7719 | rtx reg; |
7720 | { | |
7721 | int value = 0; | |
7722 | int regno = true_regnum (reg); | |
7723 | int c; | |
7724 | ||
7725 | /* Initialize for first alternative. */ | |
7726 | value = 0; | |
7727 | /* Check that each alternative contains `g' or `r'. */ | |
7728 | while (1) | |
7729 | switch (c = *string++) | |
7730 | { | |
7731 | case 0: | |
7732 | /* If an alternative lacks `g' or `r', we lose. */ | |
7733 | return value; | |
7734 | case ',': | |
7735 | /* If an alternative lacks `g' or `r', we lose. */ | |
7736 | if (value == 0) | |
7737 | return 0; | |
7738 | /* Initialize for next alternative. */ | |
7739 | value = 0; | |
7740 | break; | |
7741 | case 'g': | |
7742 | case 'r': | |
7743 | /* Any general reg wins for this alternative. */ | |
7744 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno)) | |
7745 | value = 1; | |
7746 | break; | |
7747 | default: | |
7748 | /* Any reg in specified class wins for this alternative. */ | |
7749 | { | |
0009eff2 | 7750 | enum reg_class class = REG_CLASS_FROM_LETTER (c); |
32131a9c | 7751 | |
0009eff2 | 7752 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)) |
32131a9c RK |
7753 | value = 1; |
7754 | } | |
7755 | } | |
7756 | } | |
7757 | \f | |
d445b551 RK |
7758 | /* Return the number of places FIND appears within X, but don't count |
7759 | an occurrence if some SET_DEST is FIND. */ | |
32131a9c | 7760 | |
184bb750 | 7761 | int |
32131a9c RK |
7762 | count_occurrences (x, find) |
7763 | register rtx x, find; | |
7764 | { | |
7765 | register int i, j; | |
7766 | register enum rtx_code code; | |
6f7d635c | 7767 | register const char *format_ptr; |
32131a9c RK |
7768 | int count; |
7769 | ||
7770 | if (x == find) | |
7771 | return 1; | |
7772 | if (x == 0) | |
7773 | return 0; | |
7774 | ||
7775 | code = GET_CODE (x); | |
7776 | ||
7777 | switch (code) | |
7778 | { | |
7779 | case REG: | |
7780 | case QUEUED: | |
7781 | case CONST_INT: | |
7782 | case CONST_DOUBLE: | |
7783 | case SYMBOL_REF: | |
7784 | case CODE_LABEL: | |
7785 | case PC: | |
7786 | case CC0: | |
7787 | return 0; | |
d445b551 | 7788 | |
cb2afeb3 R |
7789 | case MEM: |
7790 | if (GET_CODE (find) == MEM && rtx_equal_p (x, find)) | |
7791 | return 1; | |
7792 | break; | |
d445b551 RK |
7793 | case SET: |
7794 | if (SET_DEST (x) == find) | |
7795 | return count_occurrences (SET_SRC (x), find); | |
7796 | break; | |
05d10675 | 7797 | |
e9a25f70 JL |
7798 | default: |
7799 | break; | |
32131a9c RK |
7800 | } |
7801 | ||
7802 | format_ptr = GET_RTX_FORMAT (code); | |
7803 | count = 0; | |
7804 | ||
7805 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
7806 | { | |
7807 | switch (*format_ptr++) | |
7808 | { | |
7809 | case 'e': | |
7810 | count += count_occurrences (XEXP (x, i), find); | |
7811 | break; | |
7812 | ||
7813 | case 'E': | |
7814 | if (XVEC (x, i) != NULL) | |
7815 | { | |
7816 | for (j = 0; j < XVECLEN (x, i); j++) | |
7817 | count += count_occurrences (XVECEXP (x, i, j), find); | |
7818 | } | |
7819 | break; | |
7820 | } | |
7821 | } | |
7822 | return count; | |
7823 | } | |
2a9fb548 ILT |
7824 | \f |
7825 | /* This array holds values which are equivalent to a hard register | |
7826 | during reload_cse_regs. Each array element is an EXPR_LIST of | |
7827 | values. Each time a hard register is set, we set the corresponding | |
7828 | array element to the value. Each time a hard register is copied | |
7829 | into memory, we add the memory location to the corresponding array | |
7830 | element. We don't store values or memory addresses with side | |
7831 | effects in this array. | |
7832 | ||
7833 | If the value is a CONST_INT, then the mode of the containing | |
7834 | EXPR_LIST is the mode in which that CONST_INT was referenced. | |
7835 | ||
7836 | We sometimes clobber a specific entry in a list. In that case, we | |
7837 | just set XEXP (list-entry, 0) to 0. */ | |
7838 | ||
7839 | static rtx *reg_values; | |
7840 | ||
ba325eba ILT |
7841 | /* This is a preallocated REG rtx which we use as a temporary in |
7842 | reload_cse_invalidate_regno, so that we don't need to allocate a | |
7843 | new one each time through a loop in that function. */ | |
7844 | ||
7845 | static rtx invalidate_regno_rtx; | |
7846 | ||
2a9fb548 ILT |
7847 | /* Invalidate any entries in reg_values which depend on REGNO, |
7848 | including those for REGNO itself. This is called if REGNO is | |
7849 | changing. If CLOBBER is true, then always forget anything we | |
7850 | currently know about REGNO. MODE is the mode of the assignment to | |
7851 | REGNO, which is used to determine how many hard registers are being | |
7852 | changed. If MODE is VOIDmode, then only REGNO is being changed; | |
7853 | this is used when invalidating call clobbered registers across a | |
7854 | call. */ | |
7855 | ||
7856 | static void | |
7857 | reload_cse_invalidate_regno (regno, mode, clobber) | |
7858 | int regno; | |
7859 | enum machine_mode mode; | |
7860 | int clobber; | |
7861 | { | |
7862 | int endregno; | |
7863 | register int i; | |
7864 | ||
7865 | /* Our callers don't always go through true_regnum; we may see a | |
7866 | pseudo-register here from a CLOBBER or the like. We probably | |
7867 | won't ever see a pseudo-register that has a real register number, | |
7868 | for we check anyhow for safety. */ | |
7869 | if (regno >= FIRST_PSEUDO_REGISTER) | |
7870 | regno = reg_renumber[regno]; | |
7871 | if (regno < 0) | |
7872 | return; | |
7873 | ||
7874 | if (mode == VOIDmode) | |
7875 | endregno = regno + 1; | |
7876 | else | |
7877 | endregno = regno + HARD_REGNO_NREGS (regno, mode); | |
7878 | ||
7879 | if (clobber) | |
7880 | for (i = regno; i < endregno; i++) | |
7881 | reg_values[i] = 0; | |
7882 | ||
7883 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7884 | { | |
7885 | rtx x; | |
7886 | ||
7887 | for (x = reg_values[i]; x; x = XEXP (x, 1)) | |
7888 | { | |
7889 | if (XEXP (x, 0) != 0 | |
9e148ceb | 7890 | && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR)) |
2a9fb548 ILT |
7891 | { |
7892 | /* If this is the only entry on the list, clear | |
05d10675 BS |
7893 | reg_values[i]. Otherwise, just clear this entry on |
7894 | the list. */ | |
2a9fb548 ILT |
7895 | if (XEXP (x, 1) == 0 && x == reg_values[i]) |
7896 | { | |
7897 | reg_values[i] = 0; | |
7898 | break; | |
7899 | } | |
7900 | XEXP (x, 0) = 0; | |
7901 | } | |
7902 | } | |
7903 | } | |
ba325eba ILT |
7904 | |
7905 | /* We must look at earlier registers, in case REGNO is part of a | |
7906 | multi word value but is not the first register. If an earlier | |
7907 | register has a value in a mode which overlaps REGNO, then we must | |
7908 | invalidate that earlier register. Note that we do not need to | |
7909 | check REGNO or later registers (we must not check REGNO itself, | |
7910 | because we would incorrectly conclude that there was a conflict). */ | |
7911 | ||
7912 | for (i = 0; i < regno; i++) | |
7913 | { | |
7914 | rtx x; | |
7915 | ||
7916 | for (x = reg_values[i]; x; x = XEXP (x, 1)) | |
7917 | { | |
7918 | if (XEXP (x, 0) != 0) | |
7919 | { | |
dbd7556e | 7920 | PUT_MODE (invalidate_regno_rtx, GET_MODE (x)); |
ba325eba ILT |
7921 | REGNO (invalidate_regno_rtx) = i; |
7922 | if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx, | |
7923 | NULL_PTR)) | |
7924 | { | |
7925 | reload_cse_invalidate_regno (i, VOIDmode, 1); | |
7926 | break; | |
7927 | } | |
7928 | } | |
7929 | } | |
7930 | } | |
2a9fb548 ILT |
7931 | } |
7932 | ||
866aa3b6 DE |
7933 | /* The memory at address MEM_BASE is being changed. |
7934 | Return whether this change will invalidate VAL. */ | |
2a9fb548 ILT |
7935 | |
7936 | static int | |
cbfc3ad3 | 7937 | reload_cse_mem_conflict_p (mem_base, val) |
2a9fb548 | 7938 | rtx mem_base; |
2a9fb548 ILT |
7939 | rtx val; |
7940 | { | |
7941 | enum rtx_code code; | |
6f7d635c | 7942 | const char *fmt; |
2a9fb548 ILT |
7943 | int i; |
7944 | ||
7945 | code = GET_CODE (val); | |
7946 | switch (code) | |
7947 | { | |
7948 | /* Get rid of a few simple cases quickly. */ | |
7949 | case REG: | |
2a9fb548 ILT |
7950 | case PC: |
7951 | case CC0: | |
7952 | case SCRATCH: | |
7953 | case CONST: | |
7954 | case CONST_INT: | |
7955 | case CONST_DOUBLE: | |
7956 | case SYMBOL_REF: | |
7957 | case LABEL_REF: | |
7958 | return 0; | |
7959 | ||
7960 | case MEM: | |
866aa3b6 DE |
7961 | if (GET_MODE (mem_base) == BLKmode |
7962 | || GET_MODE (val) == BLKmode) | |
7963 | return 1; | |
e9a25f70 JL |
7964 | if (anti_dependence (val, mem_base)) |
7965 | return 1; | |
7966 | /* The address may contain nested MEMs. */ | |
7967 | break; | |
2a9fb548 ILT |
7968 | |
7969 | default: | |
7970 | break; | |
7971 | } | |
7972 | ||
7973 | fmt = GET_RTX_FORMAT (code); | |
7974 | ||
7975 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
7976 | { | |
7977 | if (fmt[i] == 'e') | |
7978 | { | |
cbfc3ad3 | 7979 | if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i))) |
2a9fb548 ILT |
7980 | return 1; |
7981 | } | |
7982 | else if (fmt[i] == 'E') | |
7983 | { | |
7984 | int j; | |
7985 | ||
7986 | for (j = 0; j < XVECLEN (val, i); j++) | |
cbfc3ad3 | 7987 | if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j))) |
2a9fb548 ILT |
7988 | return 1; |
7989 | } | |
7990 | } | |
7991 | ||
7992 | return 0; | |
7993 | } | |
7994 | ||
7995 | /* Invalidate any entries in reg_values which are changed because of a | |
7996 | store to MEM_RTX. If this is called because of a non-const call | |
7997 | instruction, MEM_RTX is (mem:BLK const0_rtx). */ | |
7998 | ||
7999 | static void | |
8000 | reload_cse_invalidate_mem (mem_rtx) | |
8001 | rtx mem_rtx; | |
8002 | { | |
8003 | register int i; | |
2a9fb548 ILT |
8004 | |
8005 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
8006 | { | |
8007 | rtx x; | |
8008 | ||
8009 | for (x = reg_values[i]; x; x = XEXP (x, 1)) | |
8010 | { | |
8011 | if (XEXP (x, 0) != 0 | |
cbfc3ad3 | 8012 | && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0))) |
2a9fb548 ILT |
8013 | { |
8014 | /* If this is the only entry on the list, clear | |
05d10675 BS |
8015 | reg_values[i]. Otherwise, just clear this entry on |
8016 | the list. */ | |
2a9fb548 ILT |
8017 | if (XEXP (x, 1) == 0 && x == reg_values[i]) |
8018 | { | |
8019 | reg_values[i] = 0; | |
8020 | break; | |
8021 | } | |
8022 | XEXP (x, 0) = 0; | |
8023 | } | |
8024 | } | |
8025 | } | |
8026 | } | |
8027 | ||
8028 | /* Invalidate DEST, which is being assigned to or clobbered. The | |
8029 | second parameter exists so that this function can be passed to | |
8030 | note_stores; it is ignored. */ | |
8031 | ||
8032 | static void | |
84832317 | 8033 | reload_cse_invalidate_rtx (dest, ignore, data) |
2a9fb548 | 8034 | rtx dest; |
487a6e06 | 8035 | rtx ignore ATTRIBUTE_UNUSED; |
84832317 | 8036 | void *data ATTRIBUTE_UNUSED; |
2a9fb548 ILT |
8037 | { |
8038 | while (GET_CODE (dest) == STRICT_LOW_PART | |
8039 | || GET_CODE (dest) == SIGN_EXTRACT | |
8040 | || GET_CODE (dest) == ZERO_EXTRACT | |
8041 | || GET_CODE (dest) == SUBREG) | |
8042 | dest = XEXP (dest, 0); | |
8043 | ||
8044 | if (GET_CODE (dest) == REG) | |
8045 | reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1); | |
8046 | else if (GET_CODE (dest) == MEM) | |
8047 | reload_cse_invalidate_mem (dest); | |
8048 | } | |
8049 | ||
8050 | /* Do a very simple CSE pass over the hard registers. | |
8051 | ||
8052 | This function detects no-op moves where we happened to assign two | |
8053 | different pseudo-registers to the same hard register, and then | |
8054 | copied one to the other. Reload will generate a useless | |
8055 | instruction copying a register to itself. | |
8056 | ||
8057 | This function also detects cases where we load a value from memory | |
8058 | into two different registers, and (if memory is more expensive than | |
8059 | registers) changes it to simply copy the first register into the | |
05d10675 | 8060 | second register. |
e9a25f70 JL |
8061 | |
8062 | Another optimization is performed that scans the operands of each | |
8063 | instruction to see whether the value is already available in a | |
8064 | hard register. It then replaces the operand with the hard register | |
8065 | if possible, much like an optional reload would. */ | |
2a9fb548 | 8066 | |
5adf6da0 R |
8067 | static void |
8068 | reload_cse_regs_1 (first) | |
2a9fb548 ILT |
8069 | rtx first; |
8070 | { | |
8071 | char *firstobj; | |
8072 | rtx callmem; | |
8073 | register int i; | |
8074 | rtx insn; | |
8075 | ||
cbfc3ad3 RK |
8076 | init_alias_analysis (); |
8077 | ||
2a9fb548 | 8078 | reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx)); |
e016950d | 8079 | bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx)); |
2a9fb548 ILT |
8080 | |
8081 | /* Create our EXPR_LIST structures on reload_obstack, so that we can | |
8082 | free them when we are done. */ | |
8083 | push_obstacks (&reload_obstack, &reload_obstack); | |
8084 | firstobj = (char *) obstack_alloc (&reload_obstack, 0); | |
8085 | ||
8086 | /* We pass this to reload_cse_invalidate_mem to invalidate all of | |
8087 | memory for a non-const call instruction. */ | |
38a448ca | 8088 | callmem = gen_rtx_MEM (BLKmode, const0_rtx); |
2a9fb548 | 8089 | |
ba325eba ILT |
8090 | /* This is used in reload_cse_invalidate_regno to avoid consing a |
8091 | new REG in a loop in that function. */ | |
38a448ca | 8092 | invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0); |
ba325eba | 8093 | |
2a9fb548 ILT |
8094 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
8095 | { | |
8096 | rtx body; | |
8097 | ||
8098 | if (GET_CODE (insn) == CODE_LABEL) | |
8099 | { | |
8100 | /* Forget all the register values at a code label. We don't | |
05d10675 | 8101 | try to do anything clever around jumps. */ |
2a9fb548 ILT |
8102 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
8103 | reg_values[i] = 0; | |
8104 | ||
8105 | continue; | |
8106 | } | |
8107 | ||
05d10675 | 8108 | #ifdef NON_SAVING_SETJMP |
2a9fb548 ILT |
8109 | if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE |
8110 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP) | |
8111 | { | |
8112 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
8113 | reg_values[i] = 0; | |
8114 | ||
8115 | continue; | |
8116 | } | |
8117 | #endif | |
8118 | ||
8119 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
8120 | continue; | |
8121 | ||
8122 | /* If this is a call instruction, forget anything stored in a | |
8123 | call clobbered register, or, if this is not a const call, in | |
8124 | memory. */ | |
8125 | if (GET_CODE (insn) == CALL_INSN) | |
8126 | { | |
8127 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
8128 | if (call_used_regs[i]) | |
8129 | reload_cse_invalidate_regno (i, VOIDmode, 1); | |
8130 | ||
8131 | if (! CONST_CALL_P (insn)) | |
8132 | reload_cse_invalidate_mem (callmem); | |
8133 | } | |
8134 | ||
05d10675 | 8135 | |
01e752d3 JL |
8136 | /* Forget all the register values at a volatile asm. */ |
8137 | if (GET_CODE (insn) == INSN | |
8138 | && GET_CODE (PATTERN (insn)) == ASM_OPERANDS | |
8139 | && MEM_VOLATILE_P (PATTERN (insn))) | |
8140 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
8141 | reg_values[i] = 0; | |
8142 | ||
2a9fb548 ILT |
8143 | body = PATTERN (insn); |
8144 | if (GET_CODE (body) == SET) | |
8145 | { | |
e9a25f70 | 8146 | int count = 0; |
31418d35 | 8147 | if (reload_cse_noop_set_p (body, insn)) |
2a9fb548 | 8148 | { |
54e89d25 R |
8149 | /* If this sets the return value of the function, we must keep |
8150 | a USE around, in case this is in a different basic block | |
8151 | than the final USE. Otherwise, we could loose important | |
8152 | register lifeness information on SMALL_REGISTER_CLASSES | |
8153 | machines, where return registers might be used as spills: | |
8154 | subsequent passes assume that spill registers are dead at | |
8155 | the end of a basic block. */ | |
8156 | if (REG_FUNCTION_VALUE_P (SET_DEST (body))) | |
8157 | { | |
8158 | pop_obstacks (); | |
8159 | PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body)); | |
8160 | INSN_CODE (insn) = -1; | |
8161 | REG_NOTES (insn) = NULL_RTX; | |
8162 | push_obstacks (&reload_obstack, &reload_obstack); | |
8163 | } | |
8164 | else | |
8165 | { | |
8166 | PUT_CODE (insn, NOTE); | |
8167 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
8168 | NOTE_SOURCE_FILE (insn) = 0; | |
8169 | } | |
2a9fb548 ILT |
8170 | |
8171 | /* We're done with this insn. */ | |
8172 | continue; | |
8173 | } | |
8174 | ||
e9a25f70 | 8175 | /* It's not a no-op, but we can try to simplify it. */ |
e9a25f70 JL |
8176 | count += reload_cse_simplify_set (body, insn); |
8177 | ||
6764d250 BS |
8178 | if (count > 0) |
8179 | apply_change_group (); | |
121315ea | 8180 | else |
6764d250 | 8181 | reload_cse_simplify_operands (insn); |
05d10675 | 8182 | |
2a9fb548 ILT |
8183 | reload_cse_record_set (body, body); |
8184 | } | |
8185 | else if (GET_CODE (body) == PARALLEL) | |
8186 | { | |
e9a25f70 | 8187 | int count = 0; |
54e89d25 | 8188 | rtx value = NULL_RTX; |
2a9fb548 ILT |
8189 | |
8190 | /* If every action in a PARALLEL is a noop, we can delete | |
05d10675 | 8191 | the entire PARALLEL. */ |
2a9fb548 | 8192 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) |
54e89d25 R |
8193 | { |
8194 | rtx part = XVECEXP (body, 0, i); | |
8195 | if (GET_CODE (part) == SET) | |
8196 | { | |
8197 | if (! reload_cse_noop_set_p (part, insn)) | |
8198 | break; | |
8199 | if (REG_FUNCTION_VALUE_P (SET_DEST (part))) | |
8200 | { | |
8201 | if (value) | |
8202 | break; | |
8203 | value = SET_DEST (part); | |
8204 | } | |
8205 | } | |
8206 | else if (GET_CODE (part) != CLOBBER) | |
8207 | break; | |
8208 | } | |
2a9fb548 ILT |
8209 | if (i < 0) |
8210 | { | |
54e89d25 R |
8211 | if (value) |
8212 | { | |
8213 | pop_obstacks (); | |
8214 | PATTERN (insn) = gen_rtx_USE (VOIDmode, value); | |
8215 | INSN_CODE (insn) = -1; | |
8216 | REG_NOTES (insn) = NULL_RTX; | |
8217 | push_obstacks (&reload_obstack, &reload_obstack); | |
8218 | } | |
8219 | else | |
8220 | { | |
8221 | PUT_CODE (insn, NOTE); | |
8222 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
8223 | NOTE_SOURCE_FILE (insn) = 0; | |
8224 | } | |
2a9fb548 ILT |
8225 | |
8226 | /* We're done with this insn. */ | |
8227 | continue; | |
8228 | } | |
05d10675 | 8229 | |
e9a25f70 | 8230 | /* It's not a no-op, but we can try to simplify it. */ |
e9a25f70 JL |
8231 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) |
8232 | if (GET_CODE (XVECEXP (body, 0, i)) == SET) | |
8233 | count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn); | |
8234 | ||
6764d250 BS |
8235 | if (count > 0) |
8236 | apply_change_group (); | |
121315ea | 8237 | else |
6764d250 | 8238 | reload_cse_simplify_operands (insn); |
2a9fb548 ILT |
8239 | |
8240 | /* Look through the PARALLEL and record the values being | |
05d10675 | 8241 | set, if possible. Also handle any CLOBBERs. */ |
2a9fb548 ILT |
8242 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) |
8243 | { | |
8244 | rtx x = XVECEXP (body, 0, i); | |
8245 | ||
8246 | if (GET_CODE (x) == SET) | |
8247 | reload_cse_record_set (x, body); | |
8248 | else | |
84832317 | 8249 | note_stores (x, reload_cse_invalidate_rtx, NULL); |
2a9fb548 ILT |
8250 | } |
8251 | } | |
8252 | else | |
84832317 | 8253 | note_stores (body, reload_cse_invalidate_rtx, NULL); |
2a9fb548 ILT |
8254 | |
8255 | #ifdef AUTO_INC_DEC | |
8256 | /* Clobber any registers which appear in REG_INC notes. We | |
05d10675 BS |
8257 | could keep track of the changes to their values, but it is |
8258 | unlikely to help. */ | |
2a9fb548 ILT |
8259 | { |
8260 | rtx x; | |
8261 | ||
8262 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) | |
8263 | if (REG_NOTE_KIND (x) == REG_INC) | |
84832317 | 8264 | reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX, NULL); |
2a9fb548 ILT |
8265 | } |
8266 | #endif | |
8267 | ||
8268 | /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only | |
05d10675 | 8269 | after we have processed the insn. */ |
2a9fb548 ILT |
8270 | if (GET_CODE (insn) == CALL_INSN) |
8271 | { | |
8272 | rtx x; | |
8273 | ||
8274 | for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1)) | |
8275 | if (GET_CODE (XEXP (x, 0)) == CLOBBER) | |
84832317 MM |
8276 | reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX, |
8277 | NULL); | |
2a9fb548 ILT |
8278 | } |
8279 | } | |
8280 | ||
e05e2395 MM |
8281 | /* Clean up. */ |
8282 | end_alias_analysis (); | |
8283 | ||
2a9fb548 ILT |
8284 | /* Free all the temporary structures we created, and go back to the |
8285 | regular obstacks. */ | |
8286 | obstack_free (&reload_obstack, firstobj); | |
8287 | pop_obstacks (); | |
8288 | } | |
8289 | ||
5adf6da0 R |
8290 | /* Call cse / combine like post-reload optimization phases. |
8291 | FIRST is the first instruction. */ | |
8292 | void | |
8293 | reload_cse_regs (first) | |
8294 | rtx first; | |
8295 | { | |
8296 | reload_cse_regs_1 (first); | |
8297 | reload_combine (); | |
8298 | reload_cse_move2add (first); | |
8299 | if (flag_expensive_optimizations) | |
8300 | reload_cse_regs_1 (first); | |
8301 | } | |
8302 | ||
2a9fb548 ILT |
8303 | /* Return whether the values known for REGNO are equal to VAL. MODE |
8304 | is the mode of the object that VAL is being copied to; this matters | |
8305 | if VAL is a CONST_INT. */ | |
8306 | ||
8307 | static int | |
8308 | reload_cse_regno_equal_p (regno, val, mode) | |
8309 | int regno; | |
8310 | rtx val; | |
8311 | enum machine_mode mode; | |
8312 | { | |
8313 | rtx x; | |
8314 | ||
8315 | if (val == 0) | |
8316 | return 0; | |
8317 | ||
8318 | for (x = reg_values[regno]; x; x = XEXP (x, 1)) | |
8319 | if (XEXP (x, 0) != 0 | |
8320 | && rtx_equal_p (XEXP (x, 0), val) | |
bb173ade RK |
8321 | && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM |
8322 | || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT) | |
2a9fb548 ILT |
8323 | && (GET_CODE (val) != CONST_INT |
8324 | || mode == GET_MODE (x) | |
8325 | || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x)) | |
6e848450 RK |
8326 | /* On a big endian machine if the value spans more than |
8327 | one register then this register holds the high part of | |
8328 | it and we can't use it. | |
8329 | ||
8330 | ??? We should also compare with the high part of the | |
8331 | value. */ | |
8332 | && !(WORDS_BIG_ENDIAN | |
8333 | && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1) | |
2a9fb548 ILT |
8334 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), |
8335 | GET_MODE_BITSIZE (GET_MODE (x)))))) | |
8336 | return 1; | |
8337 | ||
8338 | return 0; | |
8339 | } | |
8340 | ||
31418d35 ILT |
8341 | /* See whether a single set is a noop. SET is the set instruction we |
8342 | are should check, and INSN is the instruction from which it came. */ | |
2a9fb548 ILT |
8343 | |
8344 | static int | |
31418d35 | 8345 | reload_cse_noop_set_p (set, insn) |
2a9fb548 | 8346 | rtx set; |
6a651371 | 8347 | rtx insn ATTRIBUTE_UNUSED; |
2a9fb548 ILT |
8348 | { |
8349 | rtx src, dest; | |
8350 | enum machine_mode dest_mode; | |
8351 | int dreg, sreg; | |
31418d35 | 8352 | int ret; |
2a9fb548 ILT |
8353 | |
8354 | src = SET_SRC (set); | |
8355 | dest = SET_DEST (set); | |
8356 | dest_mode = GET_MODE (dest); | |
8357 | ||
8358 | if (side_effects_p (src)) | |
8359 | return 0; | |
8360 | ||
8361 | dreg = true_regnum (dest); | |
8362 | sreg = true_regnum (src); | |
8363 | ||
31418d35 ILT |
8364 | /* Check for setting a register to itself. In this case, we don't |
8365 | have to worry about REG_DEAD notes. */ | |
8366 | if (dreg >= 0 && dreg == sreg) | |
8367 | return 1; | |
8368 | ||
8369 | ret = 0; | |
2a9fb548 ILT |
8370 | if (dreg >= 0) |
8371 | { | |
8372 | /* Check for setting a register to itself. */ | |
8373 | if (dreg == sreg) | |
31418d35 | 8374 | ret = 1; |
2a9fb548 ILT |
8375 | |
8376 | /* Check for setting a register to a value which we already know | |
05d10675 | 8377 | is in the register. */ |
31418d35 ILT |
8378 | else if (reload_cse_regno_equal_p (dreg, src, dest_mode)) |
8379 | ret = 1; | |
2a9fb548 ILT |
8380 | |
8381 | /* Check for setting a register DREG to another register SREG | |
05d10675 | 8382 | where SREG is equal to a value which is already in DREG. */ |
31418d35 | 8383 | else if (sreg >= 0) |
2a9fb548 ILT |
8384 | { |
8385 | rtx x; | |
8386 | ||
8387 | for (x = reg_values[sreg]; x; x = XEXP (x, 1)) | |
31418d35 | 8388 | { |
99c2b71f ILT |
8389 | rtx tmp; |
8390 | ||
8391 | if (XEXP (x, 0) == 0) | |
8392 | continue; | |
8393 | ||
8394 | if (dest_mode == GET_MODE (x)) | |
8395 | tmp = XEXP (x, 0); | |
8396 | else if (GET_MODE_BITSIZE (dest_mode) | |
8397 | < GET_MODE_BITSIZE (GET_MODE (x))) | |
8398 | tmp = gen_lowpart_common (dest_mode, XEXP (x, 0)); | |
8399 | else | |
8400 | continue; | |
8401 | ||
8402 | if (tmp | |
8403 | && reload_cse_regno_equal_p (dreg, tmp, dest_mode)) | |
31418d35 ILT |
8404 | { |
8405 | ret = 1; | |
8406 | break; | |
8407 | } | |
8408 | } | |
2a9fb548 ILT |
8409 | } |
8410 | } | |
8411 | else if (GET_CODE (dest) == MEM) | |
8412 | { | |
8413 | /* Check for storing a register to memory when we know that the | |
05d10675 | 8414 | register is equivalent to the memory location. */ |
2a9fb548 ILT |
8415 | if (sreg >= 0 |
8416 | && reload_cse_regno_equal_p (sreg, dest, dest_mode) | |
8417 | && ! side_effects_p (dest)) | |
31418d35 | 8418 | ret = 1; |
2a9fb548 ILT |
8419 | } |
8420 | ||
31418d35 | 8421 | return ret; |
2a9fb548 ILT |
8422 | } |
8423 | ||
8424 | /* Try to simplify a single SET instruction. SET is the set pattern. | |
e9a25f70 JL |
8425 | INSN is the instruction it came from. |
8426 | This function only handles one case: if we set a register to a value | |
8427 | which is not a register, we try to find that value in some other register | |
8428 | and change the set into a register copy. */ | |
2a9fb548 | 8429 | |
e9a25f70 | 8430 | static int |
2a9fb548 ILT |
8431 | reload_cse_simplify_set (set, insn) |
8432 | rtx set; | |
8433 | rtx insn; | |
8434 | { | |
8435 | int dreg; | |
8436 | rtx src; | |
8437 | enum machine_mode dest_mode; | |
8438 | enum reg_class dclass; | |
8439 | register int i; | |
8440 | ||
2a9fb548 ILT |
8441 | dreg = true_regnum (SET_DEST (set)); |
8442 | if (dreg < 0) | |
e9a25f70 | 8443 | return 0; |
2a9fb548 ILT |
8444 | |
8445 | src = SET_SRC (set); | |
8446 | if (side_effects_p (src) || true_regnum (src) >= 0) | |
e9a25f70 | 8447 | return 0; |
2a9fb548 | 8448 | |
cbd5b9a2 KR |
8449 | dclass = REGNO_REG_CLASS (dreg); |
8450 | ||
33ab8de0 | 8451 | /* If memory loads are cheaper than register copies, don't change them. */ |
cbd5b9a2 KR |
8452 | if (GET_CODE (src) == MEM |
8453 | && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2) | |
e9a25f70 | 8454 | return 0; |
2a9fb548 | 8455 | |
0254c561 JC |
8456 | /* If the constant is cheaper than a register, don't change it. */ |
8457 | if (CONSTANT_P (src) | |
8458 | && rtx_cost (src, SET) < 2) | |
8459 | return 0; | |
8460 | ||
2a9fb548 | 8461 | dest_mode = GET_MODE (SET_DEST (set)); |
2a9fb548 ILT |
8462 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
8463 | { | |
8464 | if (i != dreg | |
8465 | && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2 | |
8466 | && reload_cse_regno_equal_p (i, src, dest_mode)) | |
8467 | { | |
8468 | int validated; | |
8469 | ||
8470 | /* Pop back to the real obstacks while changing the insn. */ | |
8471 | pop_obstacks (); | |
8472 | ||
8473 | validated = validate_change (insn, &SET_SRC (set), | |
38a448ca | 8474 | gen_rtx_REG (dest_mode, i), 1); |
2a9fb548 ILT |
8475 | |
8476 | /* Go back to the obstack we are using for temporary | |
05d10675 | 8477 | storage. */ |
2a9fb548 ILT |
8478 | push_obstacks (&reload_obstack, &reload_obstack); |
8479 | ||
6764d250 BS |
8480 | if (validated) |
8481 | return 1; | |
e9a25f70 JL |
8482 | } |
8483 | } | |
8484 | return 0; | |
8485 | } | |
8486 | ||
8487 | /* Try to replace operands in INSN with equivalent values that are already | |
05d10675 BS |
8488 | in registers. This can be viewed as optional reloading. |
8489 | ||
e9a25f70 JL |
8490 | For each non-register operand in the insn, see if any hard regs are |
8491 | known to be equivalent to that operand. Record the alternatives which | |
8492 | can accept these hard registers. Among all alternatives, select the | |
8493 | ones which are better or equal to the one currently matching, where | |
8494 | "better" is in terms of '?' and '!' constraints. Among the remaining | |
8495 | alternatives, select the one which replaces most operands with | |
8496 | hard registers. */ | |
8497 | ||
8498 | static int | |
8499 | reload_cse_simplify_operands (insn) | |
8500 | rtx insn; | |
8501 | { | |
e9a25f70 JL |
8502 | int i,j; |
8503 | ||
9b3142b3 | 8504 | const char *constraints[MAX_RECOG_OPERANDS]; |
05d10675 | 8505 | |
e9a25f70 JL |
8506 | /* Vector recording how bad an alternative is. */ |
8507 | int *alternative_reject; | |
8508 | /* Vector recording how many registers can be introduced by choosing | |
8509 | this alternative. */ | |
8510 | int *alternative_nregs; | |
8511 | /* Array of vectors recording, for each operand and each alternative, | |
8512 | which hard register to substitute, or -1 if the operand should be | |
8513 | left as it is. */ | |
8514 | int *op_alt_regno[MAX_RECOG_OPERANDS]; | |
8515 | /* Array of alternatives, sorted in order of decreasing desirability. */ | |
8516 | int *alternative_order; | |
0254c561 | 8517 | rtx reg = gen_rtx_REG (VOIDmode, -1); |
05d10675 | 8518 | |
0eadeb15 | 8519 | extract_insn (insn); |
e9a25f70 | 8520 | |
1ccbefce | 8521 | if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0) |
1d300e19 | 8522 | return 0; |
e9a25f70 JL |
8523 | |
8524 | /* Figure out which alternative currently matches. */ | |
0eadeb15 | 8525 | if (! constrain_operands (1)) |
b8705408 | 8526 | fatal_insn_not_found (insn); |
e9a25f70 | 8527 | |
1ccbefce RH |
8528 | alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int)); |
8529 | alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int)); | |
8530 | alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int)); | |
8531 | bzero ((char *)alternative_reject, recog_data.n_alternatives * sizeof (int)); | |
8532 | bzero ((char *)alternative_nregs, recog_data.n_alternatives * sizeof (int)); | |
e9a25f70 | 8533 | |
1ccbefce | 8534 | for (i = 0; i < recog_data.n_operands; i++) |
e9a25f70 JL |
8535 | { |
8536 | enum machine_mode mode; | |
8537 | int regno; | |
9b3142b3 | 8538 | const char *p; |
e9a25f70 | 8539 | |
1ccbefce RH |
8540 | op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int)); |
8541 | for (j = 0; j < recog_data.n_alternatives; j++) | |
e9a25f70 JL |
8542 | op_alt_regno[i][j] = -1; |
8543 | ||
1ccbefce RH |
8544 | p = constraints[i] = recog_data.constraints[i]; |
8545 | mode = recog_data.operand_mode[i]; | |
e9a25f70 JL |
8546 | |
8547 | /* Add the reject values for each alternative given by the constraints | |
8548 | for this operand. */ | |
8549 | j = 0; | |
8550 | while (*p != '\0') | |
8551 | { | |
8552 | char c = *p++; | |
8553 | if (c == ',') | |
8554 | j++; | |
8555 | else if (c == '?') | |
8556 | alternative_reject[j] += 3; | |
8557 | else if (c == '!') | |
8558 | alternative_reject[j] += 300; | |
8559 | } | |
8560 | ||
8561 | /* We won't change operands which are already registers. We | |
8562 | also don't want to modify output operands. */ | |
1ccbefce | 8563 | regno = true_regnum (recog_data.operand[i]); |
e9a25f70 JL |
8564 | if (regno >= 0 |
8565 | || constraints[i][0] == '=' | |
8566 | || constraints[i][0] == '+') | |
8567 | continue; | |
8568 | ||
8569 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
8570 | { | |
8571 | int class = (int) NO_REGS; | |
8572 | ||
1ccbefce | 8573 | if (! reload_cse_regno_equal_p (regno, recog_data.operand[i], mode)) |
e9a25f70 JL |
8574 | continue; |
8575 | ||
0254c561 JC |
8576 | REGNO (reg) = regno; |
8577 | PUT_MODE (reg, mode); | |
8578 | ||
e9a25f70 JL |
8579 | /* We found a register equal to this operand. Now look for all |
8580 | alternatives that can accept this register and have not been | |
8581 | assigned a register they can use yet. */ | |
8582 | j = 0; | |
8583 | p = constraints[i]; | |
8584 | for (;;) | |
31418d35 | 8585 | { |
e9a25f70 | 8586 | char c = *p++; |
05d10675 | 8587 | |
e9a25f70 | 8588 | switch (c) |
31418d35 | 8589 | { |
e9a25f70 JL |
8590 | case '=': case '+': case '?': |
8591 | case '#': case '&': case '!': | |
05d10675 | 8592 | case '*': case '%': |
e9a25f70 | 8593 | case '0': case '1': case '2': case '3': case '4': |
c5c76735 | 8594 | case '5': case '6': case '7': case '8': case '9': |
e9a25f70 JL |
8595 | case 'm': case '<': case '>': case 'V': case 'o': |
8596 | case 'E': case 'F': case 'G': case 'H': | |
8597 | case 's': case 'i': case 'n': | |
8598 | case 'I': case 'J': case 'K': case 'L': | |
8599 | case 'M': case 'N': case 'O': case 'P': | |
8600 | #ifdef EXTRA_CONSTRAINT | |
8601 | case 'Q': case 'R': case 'S': case 'T': case 'U': | |
8602 | #endif | |
8603 | case 'p': case 'X': | |
8604 | /* These don't say anything we care about. */ | |
8605 | break; | |
8606 | ||
8607 | case 'g': case 'r': | |
8608 | class = reg_class_subunion[(int) class][(int) GENERAL_REGS]; | |
8609 | break; | |
8610 | ||
8611 | default: | |
8612 | class | |
e51712db | 8613 | = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)]; |
e9a25f70 | 8614 | break; |
31418d35 | 8615 | |
e9a25f70 JL |
8616 | case ',': case '\0': |
8617 | /* See if REGNO fits this alternative, and set it up as the | |
8618 | replacement register if we don't have one for this | |
0254c561 JC |
8619 | alternative yet and the operand being replaced is not |
8620 | a cheap CONST_INT. */ | |
e9a25f70 | 8621 | if (op_alt_regno[i][j] == -1 |
0254c561 | 8622 | && reg_fits_class_p (reg, class, 0, mode) |
1ccbefce RH |
8623 | && (GET_CODE (recog_data.operand[i]) != CONST_INT |
8624 | || (rtx_cost (recog_data.operand[i], SET) | |
8625 | > rtx_cost (reg, SET)))) | |
31418d35 | 8626 | { |
e9a25f70 JL |
8627 | alternative_nregs[j]++; |
8628 | op_alt_regno[i][j] = regno; | |
31418d35 | 8629 | } |
e9a25f70 JL |
8630 | j++; |
8631 | break; | |
31418d35 ILT |
8632 | } |
8633 | ||
e9a25f70 JL |
8634 | if (c == '\0') |
8635 | break; | |
8636 | } | |
8637 | } | |
8638 | } | |
8639 | ||
8640 | /* Record all alternatives which are better or equal to the currently | |
8641 | matching one in the alternative_order array. */ | |
1ccbefce | 8642 | for (i = j = 0; i < recog_data.n_alternatives; i++) |
e9a25f70 JL |
8643 | if (alternative_reject[i] <= alternative_reject[which_alternative]) |
8644 | alternative_order[j++] = i; | |
1ccbefce | 8645 | recog_data.n_alternatives = j; |
e9a25f70 JL |
8646 | |
8647 | /* Sort it. Given a small number of alternatives, a dumb algorithm | |
8648 | won't hurt too much. */ | |
1ccbefce | 8649 | for (i = 0; i < recog_data.n_alternatives - 1; i++) |
e9a25f70 JL |
8650 | { |
8651 | int best = i; | |
8652 | int best_reject = alternative_reject[alternative_order[i]]; | |
8653 | int best_nregs = alternative_nregs[alternative_order[i]]; | |
8654 | int tmp; | |
8655 | ||
1ccbefce | 8656 | for (j = i + 1; j < recog_data.n_alternatives; j++) |
e9a25f70 JL |
8657 | { |
8658 | int this_reject = alternative_reject[alternative_order[j]]; | |
8659 | int this_nregs = alternative_nregs[alternative_order[j]]; | |
8660 | ||
8661 | if (this_reject < best_reject | |
8662 | || (this_reject == best_reject && this_nregs < best_nregs)) | |
8663 | { | |
8664 | best = j; | |
8665 | best_reject = this_reject; | |
8666 | best_nregs = this_nregs; | |
31418d35 | 8667 | } |
2a9fb548 | 8668 | } |
05d10675 | 8669 | |
e9a25f70 JL |
8670 | tmp = alternative_order[best]; |
8671 | alternative_order[best] = alternative_order[i]; | |
8672 | alternative_order[i] = tmp; | |
8673 | } | |
05d10675 | 8674 | |
e9a25f70 JL |
8675 | /* Substitute the operands as determined by op_alt_regno for the best |
8676 | alternative. */ | |
8677 | j = alternative_order[0]; | |
e9a25f70 JL |
8678 | |
8679 | /* Pop back to the real obstacks while changing the insn. */ | |
8680 | pop_obstacks (); | |
8681 | ||
1ccbefce | 8682 | for (i = 0; i < recog_data.n_operands; i++) |
e9a25f70 | 8683 | { |
1ccbefce | 8684 | enum machine_mode mode = recog_data.operand_mode[i]; |
e9a25f70 JL |
8685 | if (op_alt_regno[i][j] == -1) |
8686 | continue; | |
8687 | ||
1ccbefce | 8688 | validate_change (insn, recog_data.operand_loc[i], |
38a448ca | 8689 | gen_rtx_REG (mode, op_alt_regno[i][j]), 1); |
e9a25f70 JL |
8690 | } |
8691 | ||
1ccbefce | 8692 | for (i = recog_data.n_dups - 1; i >= 0; i--) |
e9a25f70 | 8693 | { |
1ccbefce RH |
8694 | int op = recog_data.dup_num[i]; |
8695 | enum machine_mode mode = recog_data.operand_mode[op]; | |
e9a25f70 JL |
8696 | |
8697 | if (op_alt_regno[op][j] == -1) | |
8698 | continue; | |
8699 | ||
1ccbefce | 8700 | validate_change (insn, recog_data.dup_loc[i], |
38a448ca | 8701 | gen_rtx_REG (mode, op_alt_regno[op][j]), 1); |
2a9fb548 | 8702 | } |
e9a25f70 JL |
8703 | |
8704 | /* Go back to the obstack we are using for temporary | |
8705 | storage. */ | |
8706 | push_obstacks (&reload_obstack, &reload_obstack); | |
8707 | ||
8708 | return apply_change_group (); | |
2a9fb548 ILT |
8709 | } |
8710 | ||
8711 | /* These two variables are used to pass information from | |
8712 | reload_cse_record_set to reload_cse_check_clobber. */ | |
8713 | ||
8714 | static int reload_cse_check_clobbered; | |
8715 | static rtx reload_cse_check_src; | |
8716 | ||
8717 | /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set | |
8718 | RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The | |
8719 | second argument, which is passed by note_stores, is ignored. */ | |
8720 | ||
8721 | static void | |
84832317 | 8722 | reload_cse_check_clobber (dest, ignore, data) |
2a9fb548 | 8723 | rtx dest; |
487a6e06 | 8724 | rtx ignore ATTRIBUTE_UNUSED; |
84832317 | 8725 | void *data ATTRIBUTE_UNUSED; |
2a9fb548 ILT |
8726 | { |
8727 | if (reg_overlap_mentioned_p (dest, reload_cse_check_src)) | |
8728 | reload_cse_check_clobbered = 1; | |
8729 | } | |
8730 | ||
8731 | /* Record the result of a SET instruction. SET is the set pattern. | |
8732 | BODY is the pattern of the insn that it came from. */ | |
8733 | ||
8734 | static void | |
8735 | reload_cse_record_set (set, body) | |
8736 | rtx set; | |
8737 | rtx body; | |
8738 | { | |
9e148ceb | 8739 | rtx dest, src, x; |
2a9fb548 ILT |
8740 | int dreg, sreg; |
8741 | enum machine_mode dest_mode; | |
8742 | ||
8743 | dest = SET_DEST (set); | |
8744 | src = SET_SRC (set); | |
8745 | dreg = true_regnum (dest); | |
8746 | sreg = true_regnum (src); | |
8747 | dest_mode = GET_MODE (dest); | |
8748 | ||
9e148ceb ILT |
8749 | /* Some machines don't define AUTO_INC_DEC, but they still use push |
8750 | instructions. We need to catch that case here in order to | |
8751 | invalidate the stack pointer correctly. Note that invalidating | |
8752 | the stack pointer is different from invalidating DEST. */ | |
8753 | x = dest; | |
8754 | while (GET_CODE (x) == SUBREG | |
8755 | || GET_CODE (x) == ZERO_EXTRACT | |
8756 | || GET_CODE (x) == SIGN_EXTRACT | |
8757 | || GET_CODE (x) == STRICT_LOW_PART) | |
8758 | x = XEXP (x, 0); | |
8759 | if (push_operand (x, GET_MODE (x))) | |
8760 | { | |
84832317 MM |
8761 | reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX, NULL); |
8762 | reload_cse_invalidate_rtx (dest, NULL_RTX, NULL); | |
9e148ceb ILT |
8763 | return; |
8764 | } | |
8765 | ||
2a9fb548 ILT |
8766 | /* We can only handle an assignment to a register, or a store of a |
8767 | register to a memory location. For other cases, we just clobber | |
8768 | the destination. We also have to just clobber if there are side | |
8769 | effects in SRC or DEST. */ | |
8770 | if ((dreg < 0 && GET_CODE (dest) != MEM) | |
8771 | || side_effects_p (src) | |
8772 | || side_effects_p (dest)) | |
8773 | { | |
84832317 | 8774 | reload_cse_invalidate_rtx (dest, NULL_RTX, NULL); |
2a9fb548 ILT |
8775 | return; |
8776 | } | |
8777 | ||
8778 | #ifdef HAVE_cc0 | |
8779 | /* We don't try to handle values involving CC, because it's a pain | |
8780 | to keep track of when they have to be invalidated. */ | |
8781 | if (reg_mentioned_p (cc0_rtx, src) | |
8782 | || reg_mentioned_p (cc0_rtx, dest)) | |
8783 | { | |
84832317 | 8784 | reload_cse_invalidate_rtx (dest, NULL_RTX, NULL); |
2a9fb548 ILT |
8785 | return; |
8786 | } | |
8787 | #endif | |
8788 | ||
8789 | /* If BODY is a PARALLEL, then we need to see whether the source of | |
8790 | SET is clobbered by some other instruction in the PARALLEL. */ | |
8791 | if (GET_CODE (body) == PARALLEL) | |
8792 | { | |
8793 | int i; | |
8794 | ||
8795 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
8796 | { | |
8797 | rtx x; | |
8798 | ||
8799 | x = XVECEXP (body, 0, i); | |
8800 | if (x == set) | |
8801 | continue; | |
8802 | ||
8803 | reload_cse_check_clobbered = 0; | |
8804 | reload_cse_check_src = src; | |
84832317 | 8805 | note_stores (x, reload_cse_check_clobber, NULL); |
2a9fb548 ILT |
8806 | if (reload_cse_check_clobbered) |
8807 | { | |
84832317 | 8808 | reload_cse_invalidate_rtx (dest, NULL_RTX, NULL); |
2a9fb548 ILT |
8809 | return; |
8810 | } | |
8811 | } | |
8812 | } | |
8813 | ||
8814 | if (dreg >= 0) | |
8815 | { | |
8816 | int i; | |
8817 | ||
8818 | /* This is an assignment to a register. Update the value we | |
05d10675 | 8819 | have stored for the register. */ |
2a9fb548 | 8820 | if (sreg >= 0) |
ad578014 ILT |
8821 | { |
8822 | rtx x; | |
8823 | ||
8824 | /* This is a copy from one register to another. Any values | |
8825 | which were valid for SREG are now valid for DREG. If the | |
8826 | mode changes, we use gen_lowpart_common to extract only | |
8827 | the part of the value that is copied. */ | |
8828 | reg_values[dreg] = 0; | |
8829 | for (x = reg_values[sreg]; x; x = XEXP (x, 1)) | |
8830 | { | |
8831 | rtx tmp; | |
8832 | ||
8833 | if (XEXP (x, 0) == 0) | |
8834 | continue; | |
8835 | if (dest_mode == GET_MODE (XEXP (x, 0))) | |
8836 | tmp = XEXP (x, 0); | |
23e7786b | 8837 | else if (GET_MODE_BITSIZE (dest_mode) |
05d10675 | 8838 | > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) |
23e7786b | 8839 | continue; |
ad578014 ILT |
8840 | else |
8841 | tmp = gen_lowpart_common (dest_mode, XEXP (x, 0)); | |
8842 | if (tmp) | |
38a448ca RH |
8843 | reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp, |
8844 | reg_values[dreg]); | |
05d10675 | 8845 | } |
ad578014 | 8846 | } |
2a9fb548 | 8847 | else |
38a448ca | 8848 | reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX); |
2a9fb548 ILT |
8849 | |
8850 | /* We've changed DREG, so invalidate any values held by other | |
05d10675 | 8851 | registers that depend upon it. */ |
2a9fb548 ILT |
8852 | reload_cse_invalidate_regno (dreg, dest_mode, 0); |
8853 | ||
8854 | /* If this assignment changes more than one hard register, | |
05d10675 | 8855 | forget anything we know about the others. */ |
2a9fb548 ILT |
8856 | for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++) |
8857 | reg_values[dreg + i] = 0; | |
8858 | } | |
8859 | else if (GET_CODE (dest) == MEM) | |
8860 | { | |
8861 | /* Invalidate conflicting memory locations. */ | |
8862 | reload_cse_invalidate_mem (dest); | |
8863 | ||
8864 | /* If we're storing a register to memory, add DEST to the list | |
05d10675 | 8865 | in REG_VALUES. */ |
2a9fb548 | 8866 | if (sreg >= 0 && ! side_effects_p (dest)) |
38a448ca | 8867 | reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest, |
2a9fb548 ILT |
8868 | reg_values[sreg]); |
8869 | } | |
8870 | else | |
8871 | { | |
8872 | /* We should have bailed out earlier. */ | |
8873 | abort (); | |
8874 | } | |
8875 | } | |
5adf6da0 R |
8876 | \f |
8877 | /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg | |
8878 | addressing now. | |
8879 | This code might also be useful when reload gave up on reg+reg addresssing | |
8880 | because of clashes between the return register and INDEX_REG_CLASS. */ | |
8881 | ||
8882 | /* The maximum number of uses of a register we can keep track of to | |
8883 | replace them with reg+reg addressing. */ | |
8884 | #define RELOAD_COMBINE_MAX_USES 6 | |
8885 | ||
8886 | /* INSN is the insn where a register has ben used, and USEP points to the | |
8887 | location of the register within the rtl. */ | |
8888 | struct reg_use { rtx insn, *usep; }; | |
8889 | ||
8890 | /* If the register is used in some unknown fashion, USE_INDEX is negative. | |
8891 | If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID | |
8892 | indicates where it becomes live again. | |
8893 | Otherwise, USE_INDEX is the index of the last encountered use of the | |
8894 | register (which is first among these we have seen since we scan backwards), | |
8895 | OFFSET contains the constant offset that is added to the register in | |
8896 | all encountered uses, and USE_RUID indicates the first encountered, i.e. | |
ed937a19 R |
8897 | last, of these uses. |
8898 | STORE_RUID is always meaningful if we only want to use a value in a | |
8899 | register in a different place: it denotes the next insn in the insn | |
8900 | stream (i.e. the last ecountered) that sets or clobbers the register. */ | |
5adf6da0 R |
8901 | static struct |
8902 | { | |
8903 | struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; | |
8904 | int use_index; | |
8905 | rtx offset; | |
8906 | int store_ruid; | |
8907 | int use_ruid; | |
8908 | } reg_state[FIRST_PSEUDO_REGISTER]; | |
8909 | ||
8910 | /* Reverse linear uid. This is increased in reload_combine while scanning | |
8911 | the instructions from last to first. It is used to set last_label_ruid | |
8912 | and the store_ruid / use_ruid fields in reg_state. */ | |
8913 | static int reload_combine_ruid; | |
8914 | ||
b0634509 R |
8915 | #define LABEL_LIVE(LABEL) \ |
8916 | (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) | |
8917 | ||
5adf6da0 R |
8918 | static void |
8919 | reload_combine () | |
8920 | { | |
8921 | rtx insn, set; | |
8922 | int first_index_reg = 1, last_index_reg = 0; | |
8923 | int i; | |
8924 | int last_label_ruid; | |
b0634509 R |
8925 | int min_labelno, n_labels; |
8926 | HARD_REG_SET ever_live_at_start, *label_live; | |
5adf6da0 R |
8927 | |
8928 | /* If reg+reg can be used in offsetable memory adresses, the main chunk of | |
8929 | reload has already used it where appropriate, so there is no use in | |
8930 | trying to generate it now. */ | |
03acd8f8 | 8931 | if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS) |
5adf6da0 R |
8932 | return; |
8933 | ||
8934 | /* To avoid wasting too much time later searching for an index register, | |
8935 | determine the minimum and maximum index register numbers. */ | |
8936 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i) | |
8937 | { | |
8938 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)) | |
8939 | { | |
8940 | if (! last_index_reg) | |
8941 | last_index_reg = i; | |
8942 | first_index_reg = i; | |
8943 | } | |
8944 | } | |
8945 | /* If no index register is available, we can quit now. */ | |
8946 | if (first_index_reg > last_index_reg) | |
8947 | return; | |
8948 | ||
b0634509 R |
8949 | /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime |
8950 | information is a bit fuzzy immediately after reload, but it's | |
8951 | still good enough to determine which registers are live at a jump | |
8952 | destination. */ | |
8953 | min_labelno = get_first_label_num (); | |
8954 | n_labels = max_label_num () - min_labelno; | |
8955 | label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET)); | |
8956 | CLEAR_HARD_REG_SET (ever_live_at_start); | |
8957 | for (i = n_basic_blocks - 1; i >= 0; i--) | |
8958 | { | |
3b413743 | 8959 | insn = BLOCK_HEAD (i); |
b0634509 R |
8960 | if (GET_CODE (insn) == CODE_LABEL) |
8961 | { | |
8962 | HARD_REG_SET live; | |
8963 | ||
e881bb1b RH |
8964 | REG_SET_TO_HARD_REG_SET (live, BASIC_BLOCK (i)->global_live_at_start); |
8965 | compute_use_by_pseudos (&live, BASIC_BLOCK (i)->global_live_at_start); | |
b0634509 R |
8966 | COPY_HARD_REG_SET (LABEL_LIVE (insn), live); |
8967 | IOR_HARD_REG_SET (ever_live_at_start, live); | |
8968 | } | |
8969 | } | |
8970 | ||
5adf6da0 R |
8971 | /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ |
8972 | last_label_ruid = reload_combine_ruid = 0; | |
8973 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i) | |
8974 | { | |
ed937a19 | 8975 | reg_state[i].store_ruid = reload_combine_ruid; |
5adf6da0 R |
8976 | if (fixed_regs[i]) |
8977 | reg_state[i].use_index = -1; | |
8978 | else | |
ed937a19 | 8979 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; |
5adf6da0 R |
8980 | } |
8981 | ||
8982 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
8983 | { | |
8984 | rtx note; | |
8985 | ||
8986 | /* We cannot do our optimization across labels. Invalidating all the use | |
8987 | information we have would be costly, so we just note where the label | |
05d10675 | 8988 | is and then later disable any optimization that would cross it. */ |
5adf6da0 R |
8989 | if (GET_CODE (insn) == CODE_LABEL) |
8990 | last_label_ruid = reload_combine_ruid; | |
b0634509 R |
8991 | if (GET_CODE (insn) == BARRIER) |
8992 | { | |
8993 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i) | |
8994 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | |
8995 | } | |
5adf6da0 R |
8996 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') |
8997 | continue; | |
8998 | reload_combine_ruid++; | |
8999 | ||
9000 | /* Look for (set (REGX) (CONST_INT)) | |
eceef4c9 BS |
9001 | (set (REGX) (PLUS (REGX) (REGY))) |
9002 | ... | |
9003 | ... (MEM (REGX)) ... | |
5adf6da0 | 9004 | and convert it to |
eceef4c9 BS |
9005 | (set (REGZ) (CONST_INT)) |
9006 | ... | |
9007 | ... (MEM (PLUS (REGZ) (REGY)))... . | |
5adf6da0 R |
9008 | |
9009 | First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | |
9010 | and that we know all uses of REGX before it dies. */ | |
2abbc1bd R |
9011 | set = single_set (insn); |
9012 | if (set != NULL_RTX | |
5adf6da0 R |
9013 | && GET_CODE (SET_DEST (set)) == REG |
9014 | && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)), | |
9015 | GET_MODE (SET_DEST (set))) | |
9016 | == 1) | |
9017 | && GET_CODE (SET_SRC (set)) == PLUS | |
9018 | && GET_CODE (XEXP (SET_SRC (set), 1)) == REG | |
9019 | && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set)) | |
9020 | && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid) | |
9021 | { | |
9022 | rtx reg = SET_DEST (set); | |
9023 | rtx plus = SET_SRC (set); | |
9024 | rtx base = XEXP (plus, 1); | |
9025 | rtx prev = prev_nonnote_insn (insn); | |
9026 | rtx prev_set = prev ? single_set (prev) : NULL_RTX; | |
9027 | int regno = REGNO (reg); | |
6a651371 | 9028 | rtx const_reg = NULL_RTX; |
5adf6da0 R |
9029 | rtx reg_sum = NULL_RTX; |
9030 | ||
9031 | /* Now, we need an index register. | |
9032 | We'll set index_reg to this index register, const_reg to the | |
9033 | register that is to be loaded with the constant | |
9034 | (denoted as REGZ in the substitution illustration above), | |
9035 | and reg_sum to the register-register that we want to use to | |
9036 | substitute uses of REG (typically in MEMs) with. | |
9037 | First check REG and BASE for being index registers; | |
9038 | we can use them even if they are not dead. */ | |
9039 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | |
9040 | || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | |
9041 | REGNO (base))) | |
9042 | { | |
9043 | const_reg = reg; | |
9044 | reg_sum = plus; | |
9045 | } | |
9046 | else | |
9047 | { | |
05d10675 BS |
9048 | /* Otherwise, look for a free index register. Since we have |
9049 | checked above that neiter REG nor BASE are index registers, | |
9050 | if we find anything at all, it will be different from these | |
9051 | two registers. */ | |
9052 | for (i = first_index_reg; i <= last_index_reg; i++) | |
5adf6da0 R |
9053 | { |
9054 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i) | |
9055 | && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES | |
9056 | && reg_state[i].store_ruid <= reg_state[regno].use_ruid | |
9057 | && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1) | |
9058 | { | |
9059 | rtx index_reg = gen_rtx_REG (GET_MODE (reg), i); | |
9060 | const_reg = index_reg; | |
9061 | reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | |
9062 | break; | |
9063 | } | |
9064 | } | |
9065 | } | |
ed937a19 R |
9066 | /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that |
9067 | (REGY), i.e. BASE, is not clobbered before the last use we'll | |
9068 | create. */ | |
5adf6da0 R |
9069 | if (prev_set |
9070 | && GET_CODE (SET_SRC (prev_set)) == CONST_INT | |
9071 | && rtx_equal_p (SET_DEST (prev_set), reg) | |
9072 | && reg_state[regno].use_index >= 0 | |
ed937a19 | 9073 | && reg_state[REGNO (base)].store_ruid <= reg_state[regno].use_ruid |
5adf6da0 R |
9074 | && reg_sum) |
9075 | { | |
9076 | int i; | |
9077 | ||
9078 | /* Change destination register and - if necessary - the | |
9079 | constant value in PREV, the constant loading instruction. */ | |
9080 | validate_change (prev, &SET_DEST (prev_set), const_reg, 1); | |
9081 | if (reg_state[regno].offset != const0_rtx) | |
9082 | validate_change (prev, | |
9083 | &SET_SRC (prev_set), | |
9084 | GEN_INT (INTVAL (SET_SRC (prev_set)) | |
9085 | + INTVAL (reg_state[regno].offset)), | |
9086 | 1); | |
9087 | /* Now for every use of REG that we have recorded, replace REG | |
9088 | with REG_SUM. */ | |
9089 | for (i = reg_state[regno].use_index; | |
9090 | i < RELOAD_COMBINE_MAX_USES; i++) | |
9091 | validate_change (reg_state[regno].reg_use[i].insn, | |
9092 | reg_state[regno].reg_use[i].usep, | |
9093 | reg_sum, 1); | |
9094 | ||
9095 | if (apply_change_group ()) | |
9096 | { | |
9097 | rtx *np; | |
9098 | ||
9099 | /* Delete the reg-reg addition. */ | |
9100 | PUT_CODE (insn, NOTE); | |
9101 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
9102 | NOTE_SOURCE_FILE (insn) = 0; | |
9103 | ||
9104 | if (reg_state[regno].offset != const0_rtx) | |
9105 | { | |
9106 | /* Previous REG_EQUIV / REG_EQUAL notes for PREV | |
9107 | are now invalid. */ | |
9108 | for (np = ®_NOTES (prev); *np; ) | |
9109 | { | |
9110 | if (REG_NOTE_KIND (*np) == REG_EQUAL | |
9111 | || REG_NOTE_KIND (*np) == REG_EQUIV) | |
9112 | *np = XEXP (*np, 1); | |
9113 | else | |
9114 | np = &XEXP (*np, 1); | |
9115 | } | |
9116 | } | |
9117 | reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; | |
9118 | reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid; | |
9119 | continue; | |
9120 | } | |
9121 | } | |
9122 | } | |
84832317 | 9123 | note_stores (PATTERN (insn), reload_combine_note_store, NULL); |
5adf6da0 R |
9124 | if (GET_CODE (insn) == CALL_INSN) |
9125 | { | |
9126 | rtx link; | |
9127 | ||
9128 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i) | |
9129 | { | |
9130 | if (call_used_regs[i]) | |
9131 | { | |
9132 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | |
9133 | reg_state[i].store_ruid = reload_combine_ruid; | |
9134 | } | |
9135 | } | |
9136 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; | |
9137 | link = XEXP (link, 1)) | |
9138 | { | |
9139 | rtx use = XEXP (link, 0); | |
9140 | int regno = REGNO (XEXP (use, 0)); | |
9141 | if (GET_CODE (use) == CLOBBER) | |
9142 | { | |
9143 | reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; | |
9144 | reg_state[regno].store_ruid = reload_combine_ruid; | |
9145 | } | |
9146 | else | |
9147 | reg_state[regno].use_index = -1; | |
9148 | } | |
9149 | } | |
b0634509 | 9150 | if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) != RETURN) |
5adf6da0 R |
9151 | { |
9152 | /* Non-spill registers might be used at the call destination in | |
9153 | some unknown fashion, so we have to mark the unknown use. */ | |
b0634509 R |
9154 | HARD_REG_SET *live; |
9155 | if ((condjump_p (insn) || condjump_in_parallel_p (insn)) | |
9156 | && JUMP_LABEL (insn)) | |
9157 | live = &LABEL_LIVE (JUMP_LABEL (insn)); | |
9158 | else | |
9159 | live = &ever_live_at_start; | |
5adf6da0 R |
9160 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i) |
9161 | { | |
b0634509 | 9162 | if (TEST_HARD_REG_BIT (*live, i)) |
5adf6da0 R |
9163 | reg_state[i].use_index = -1; |
9164 | } | |
9165 | } | |
9166 | reload_combine_note_use (&PATTERN (insn), insn); | |
9167 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
9168 | { | |
9169 | if (REG_NOTE_KIND (note) == REG_INC | |
9170 | && GET_CODE (XEXP (note, 0)) == REG) | |
ed937a19 R |
9171 | { |
9172 | int regno = REGNO (XEXP (note, 0)); | |
9173 | ||
9174 | reg_state[regno].store_ruid = reload_combine_ruid; | |
9175 | reg_state[regno].use_index = -1; | |
9176 | } | |
5adf6da0 R |
9177 | } |
9178 | } | |
b0634509 | 9179 | free (label_live); |
5adf6da0 R |
9180 | } |
9181 | ||
9182 | /* Check if DST is a register or a subreg of a register; if it is, | |
9183 | update reg_state[regno].store_ruid and reg_state[regno].use_index | |
f93233bb | 9184 | accordingly. Called via note_stores from reload_combine. */ |
5adf6da0 | 9185 | static void |
84832317 | 9186 | reload_combine_note_store (dst, set, data) |
f93233bb | 9187 | rtx dst, set; |
84832317 | 9188 | void *data ATTRIBUTE_UNUSED; |
5adf6da0 R |
9189 | { |
9190 | int regno = 0; | |
9191 | int i; | |
9192 | unsigned size = GET_MODE_SIZE (GET_MODE (dst)); | |
9193 | ||
9194 | if (GET_CODE (dst) == SUBREG) | |
9195 | { | |
9196 | regno = SUBREG_WORD (dst); | |
9197 | dst = SUBREG_REG (dst); | |
9198 | } | |
9199 | if (GET_CODE (dst) != REG) | |
9200 | return; | |
9201 | regno += REGNO (dst); | |
54ca6ffa | 9202 | |
5adf6da0 | 9203 | /* note_stores might have stripped a STRICT_LOW_PART, so we have to be |
05d10675 | 9204 | careful with registers / register parts that are not full words. |
54ca6ffa JL |
9205 | |
9206 | Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */ | |
9207 | if (GET_CODE (set) != SET | |
9208 | || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT | |
9209 | || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT | |
9210 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) | |
ed937a19 | 9211 | { |
43f854cf | 9212 | for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--) |
f93233bb JL |
9213 | { |
9214 | reg_state[i].use_index = -1; | |
9215 | reg_state[i].store_ruid = reload_combine_ruid; | |
9216 | } | |
ed937a19 | 9217 | } |
5adf6da0 R |
9218 | else |
9219 | { | |
43f854cf | 9220 | for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--) |
5adf6da0 R |
9221 | { |
9222 | reg_state[i].store_ruid = reload_combine_ruid; | |
9223 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | |
9224 | } | |
9225 | } | |
9226 | } | |
9227 | ||
9228 | /* XP points to a piece of rtl that has to be checked for any uses of | |
9229 | registers. | |
9230 | *XP is the pattern of INSN, or a part of it. | |
9231 | Called from reload_combine, and recursively by itself. */ | |
9232 | static void | |
9233 | reload_combine_note_use (xp, insn) | |
9234 | rtx *xp, insn; | |
9235 | { | |
9236 | rtx x = *xp; | |
9237 | enum rtx_code code = x->code; | |
6f7d635c | 9238 | const char *fmt; |
5adf6da0 R |
9239 | int i, j; |
9240 | rtx offset = const0_rtx; /* For the REG case below. */ | |
9241 | ||
9242 | switch (code) | |
9243 | { | |
9244 | case SET: | |
9245 | if (GET_CODE (SET_DEST (x)) == REG) | |
9246 | { | |
9247 | reload_combine_note_use (&SET_SRC (x), insn); | |
9248 | return; | |
9249 | } | |
9250 | break; | |
9251 | ||
9252 | case CLOBBER: | |
9253 | if (GET_CODE (SET_DEST (x)) == REG) | |
9254 | return; | |
9255 | break; | |
9256 | ||
9257 | case PLUS: | |
9258 | /* We are interested in (plus (reg) (const_int)) . */ | |
9259 | if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT) | |
9260 | break; | |
9261 | offset = XEXP (x, 1); | |
9262 | x = XEXP (x, 0); | |
05d10675 | 9263 | /* Fall through. */ |
5adf6da0 R |
9264 | case REG: |
9265 | { | |
9266 | int regno = REGNO (x); | |
9267 | int use_index; | |
9268 | ||
9269 | /* Some spurious USEs of pseudo registers might remain. | |
9270 | Just ignore them. */ | |
9271 | if (regno >= FIRST_PSEUDO_REGISTER) | |
9272 | return; | |
9273 | ||
9274 | /* If this register is already used in some unknown fashion, we | |
9275 | can't do anything. | |
9276 | If we decrement the index from zero to -1, we can't store more | |
9277 | uses, so this register becomes used in an unknown fashion. */ | |
9278 | use_index = --reg_state[regno].use_index; | |
9279 | if (use_index < 0) | |
9280 | return; | |
9281 | ||
9282 | if (use_index != RELOAD_COMBINE_MAX_USES - 1) | |
9283 | { | |
9284 | /* We have found another use for a register that is already | |
9285 | used later. Check if the offsets match; if not, mark the | |
9286 | register as used in an unknown fashion. */ | |
9287 | if (! rtx_equal_p (offset, reg_state[regno].offset)) | |
9288 | { | |
9289 | reg_state[regno].use_index = -1; | |
9290 | return; | |
9291 | } | |
9292 | } | |
9293 | else | |
9294 | { | |
9295 | /* This is the first use of this register we have seen since we | |
9296 | marked it as dead. */ | |
9297 | reg_state[regno].offset = offset; | |
9298 | reg_state[regno].use_ruid = reload_combine_ruid; | |
9299 | } | |
9300 | reg_state[regno].reg_use[use_index].insn = insn; | |
9301 | reg_state[regno].reg_use[use_index].usep = xp; | |
9302 | return; | |
9303 | } | |
9304 | ||
9305 | default: | |
9306 | break; | |
9307 | } | |
9308 | ||
9309 | /* Recursively process the components of X. */ | |
9310 | fmt = GET_RTX_FORMAT (code); | |
9311 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
9312 | { | |
9313 | if (fmt[i] == 'e') | |
9314 | reload_combine_note_use (&XEXP (x, i), insn); | |
9315 | else if (fmt[i] == 'E') | |
9316 | { | |
9317 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
9318 | reload_combine_note_use (&XVECEXP (x, i, j), insn); | |
9319 | } | |
9320 | } | |
9321 | } | |
9322 | \f | |
9323 | /* See if we can reduce the cost of a constant by replacing a move with | |
9324 | an add. */ | |
9325 | /* We cannot do our optimization across labels. Invalidating all the | |
9326 | information about register contents we have would be costly, so we | |
9327 | use last_label_luid (local variable of reload_cse_move2add) to note | |
9328 | where the label is and then later disable any optimization that would | |
9329 | cross it. | |
9330 | reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if | |
9331 | reg_set_luid[n] is larger than last_label_luid[n] . */ | |
9332 | static int reg_set_luid[FIRST_PSEUDO_REGISTER]; | |
9333 | /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] / | |
9334 | reg_mode[n] to be valid. | |
9335 | If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n | |
9336 | has been set to reg_offset[n] in mode reg_mode[n] . | |
9337 | If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative, | |
9338 | register n has been set to the sum of reg_offset[n] and register | |
9339 | reg_base_reg[n], calculated in mode reg_mode[n] . */ | |
9340 | static rtx reg_offset[FIRST_PSEUDO_REGISTER]; | |
9341 | static int reg_base_reg[FIRST_PSEUDO_REGISTER]; | |
9342 | static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; | |
9343 | /* move2add_luid is linearily increased while scanning the instructions | |
9344 | from first to last. It is used to set reg_set_luid in | |
6764d250 | 9345 | reload_cse_move2add and move2add_note_store. */ |
5adf6da0 R |
9346 | static int move2add_luid; |
9347 | ||
ccc4ae07 AS |
9348 | /* Generate a CONST_INT and force it in the range of MODE. */ |
9349 | static rtx | |
9350 | gen_mode_int (mode, value) | |
9351 | enum machine_mode mode; | |
9352 | HOST_WIDE_INT value; | |
9353 | { | |
9354 | HOST_WIDE_INT cval = value & GET_MODE_MASK (mode); | |
9355 | int width = GET_MODE_BITSIZE (mode); | |
9356 | ||
9357 | /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number, | |
9358 | sign extend it. */ | |
9359 | if (width > 0 && width < HOST_BITS_PER_WIDE_INT | |
9360 | && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) | |
9361 | cval |= (HOST_WIDE_INT) -1 << width; | |
9362 | ||
9363 | return GEN_INT (cval); | |
9364 | } | |
9365 | ||
5adf6da0 R |
9366 | static void |
9367 | reload_cse_move2add (first) | |
9368 | rtx first; | |
9369 | { | |
9370 | int i; | |
9371 | rtx insn; | |
9372 | int last_label_luid; | |
5adf6da0 R |
9373 | |
9374 | for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--) | |
6764d250 BS |
9375 | reg_set_luid[i] = 0; |
9376 | ||
5adf6da0 R |
9377 | last_label_luid = 0; |
9378 | move2add_luid = 1; | |
9379 | for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++) | |
9380 | { | |
9381 | rtx pat, note; | |
9382 | ||
9383 | if (GET_CODE (insn) == CODE_LABEL) | |
9384 | last_label_luid = move2add_luid; | |
9385 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
9386 | continue; | |
9387 | pat = PATTERN (insn); | |
9388 | /* For simplicity, we only perform this optimization on | |
9389 | straightforward SETs. */ | |
9390 | if (GET_CODE (pat) == SET | |
9391 | && GET_CODE (SET_DEST (pat)) == REG) | |
9392 | { | |
9393 | rtx reg = SET_DEST (pat); | |
9394 | int regno = REGNO (reg); | |
9395 | rtx src = SET_SRC (pat); | |
9396 | ||
9397 | /* Check if we have valid information on the contents of this | |
9398 | register in the mode of REG. */ | |
9399 | /* ??? We don't know how zero / sign extension is handled, hence | |
9400 | we can't go from a narrower to a wider mode. */ | |
9401 | if (reg_set_luid[regno] > last_label_luid | |
05d10675 BS |
9402 | && (GET_MODE_SIZE (GET_MODE (reg)) |
9403 | <= GET_MODE_SIZE (reg_mode[regno])) | |
9404 | && GET_CODE (reg_offset[regno]) == CONST_INT) | |
5adf6da0 R |
9405 | { |
9406 | /* Try to transform (set (REGX) (CONST_INT A)) | |
9407 | ... | |
9408 | (set (REGX) (CONST_INT B)) | |
9409 | to | |
9410 | (set (REGX) (CONST_INT A)) | |
9411 | ... | |
9412 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
9413 | ||
9414 | if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0) | |
9415 | { | |
9416 | int success = 0; | |
ccc4ae07 AS |
9417 | rtx new_src |
9418 | = gen_mode_int (GET_MODE (reg), | |
9419 | INTVAL (src) - INTVAL (reg_offset[regno])); | |
5adf6da0 R |
9420 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; |
9421 | use (set (reg) (reg)) instead. | |
9422 | We don't delete this insn, nor do we convert it into a | |
9423 | note, to avoid losing register notes or the return | |
9424 | value flag. jump2 already knowns how to get rid of | |
9425 | no-op moves. */ | |
9426 | if (new_src == const0_rtx) | |
9427 | success = validate_change (insn, &SET_SRC (pat), reg, 0); | |
9428 | else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET) | |
9429 | && have_add2_insn (GET_MODE (reg))) | |
9430 | success = validate_change (insn, &PATTERN (insn), | |
9431 | gen_add2_insn (reg, new_src), 0); | |
5adf6da0 R |
9432 | reg_set_luid[regno] = move2add_luid; |
9433 | reg_mode[regno] = GET_MODE (reg); | |
9434 | reg_offset[regno] = src; | |
9435 | continue; | |
9436 | } | |
9437 | ||
9438 | /* Try to transform (set (REGX) (REGY)) | |
9439 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
9440 | ... | |
9441 | (set (REGX) (REGY)) | |
9442 | (set (REGX) (PLUS (REGX) (CONST_INT B))) | |
9443 | to | |
9444 | (REGX) (REGY)) | |
9445 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
9446 | ... | |
9447 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
9448 | else if (GET_CODE (src) == REG | |
9449 | && reg_base_reg[regno] == REGNO (src) | |
9450 | && reg_set_luid[regno] > reg_set_luid[REGNO (src)]) | |
9451 | { | |
9452 | rtx next = next_nonnote_insn (insn); | |
6a651371 | 9453 | rtx set = NULL_RTX; |
5adf6da0 R |
9454 | if (next) |
9455 | set = single_set (next); | |
9456 | if (next | |
9457 | && set | |
9458 | && SET_DEST (set) == reg | |
9459 | && GET_CODE (SET_SRC (set)) == PLUS | |
9460 | && XEXP (SET_SRC (set), 0) == reg | |
9461 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT) | |
9462 | { | |
5adf6da0 | 9463 | rtx src3 = XEXP (SET_SRC (set), 1); |
ccc4ae07 AS |
9464 | rtx new_src |
9465 | = gen_mode_int (GET_MODE (reg), | |
9466 | INTVAL (src3) | |
9467 | - INTVAL (reg_offset[regno])); | |
5adf6da0 R |
9468 | int success = 0; |
9469 | ||
9470 | if (new_src == const0_rtx) | |
9471 | /* See above why we create (set (reg) (reg)) here. */ | |
9472 | success | |
9473 | = validate_change (next, &SET_SRC (set), reg, 0); | |
9474 | else if ((rtx_cost (new_src, PLUS) | |
9475 | < 2 + rtx_cost (src3, SET)) | |
9476 | && have_add2_insn (GET_MODE (reg))) | |
9477 | success | |
9478 | = validate_change (next, &PATTERN (next), | |
9479 | gen_add2_insn (reg, new_src), 0); | |
9480 | if (success) | |
9481 | { | |
5adf6da0 R |
9482 | /* INSN might be the first insn in a basic block |
9483 | if the preceding insn is a conditional jump | |
9484 | or a possible-throwing call. */ | |
9485 | PUT_CODE (insn, NOTE); | |
9486 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
9487 | NOTE_SOURCE_FILE (insn) = 0; | |
9488 | } | |
9489 | insn = next; | |
9490 | reg_set_luid[regno] = move2add_luid; | |
9491 | reg_mode[regno] = GET_MODE (reg); | |
9492 | reg_offset[regno] = src3; | |
9493 | continue; | |
9494 | } | |
9495 | } | |
9496 | } | |
9497 | } | |
9498 | ||
9499 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
9500 | { | |
9501 | if (REG_NOTE_KIND (note) == REG_INC | |
9502 | && GET_CODE (XEXP (note, 0)) == REG) | |
9503 | { | |
9504 | /* Indicate that this register has been recently written to, | |
9505 | but the exact contents are not available. */ | |
9506 | int regno = REGNO (XEXP (note, 0)); | |
9507 | if (regno < FIRST_PSEUDO_REGISTER) | |
9508 | { | |
9509 | reg_set_luid[regno] = move2add_luid; | |
9510 | reg_offset[regno] = note; | |
9511 | } | |
9512 | } | |
5adf6da0 | 9513 | } |
84832317 | 9514 | note_stores (PATTERN (insn), move2add_note_store, NULL); |
5adf6da0 R |
9515 | /* If this is a CALL_INSN, all call used registers are stored with |
9516 | unknown values. */ | |
9517 | if (GET_CODE (insn) == CALL_INSN) | |
9518 | { | |
9519 | for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--) | |
9520 | { | |
9521 | if (call_used_regs[i]) | |
9522 | { | |
9523 | reg_set_luid[i] = move2add_luid; | |
9524 | reg_offset[i] = insn; /* Invalidate contents. */ | |
9525 | } | |
9526 | } | |
9527 | } | |
9528 | } | |
9529 | } | |
9530 | ||
9531 | /* SET is a SET or CLOBBER that sets DST. | |
9532 | Update reg_set_luid, reg_offset and reg_base_reg accordingly. | |
9533 | Called from reload_cse_move2add via note_stores. */ | |
9534 | static void | |
84832317 | 9535 | move2add_note_store (dst, set, data) |
5adf6da0 | 9536 | rtx dst, set; |
84832317 | 9537 | void *data ATTRIBUTE_UNUSED; |
5adf6da0 R |
9538 | { |
9539 | int regno = 0; | |
9540 | int i; | |
9541 | ||
9542 | enum machine_mode mode = GET_MODE (dst); | |
9543 | if (GET_CODE (dst) == SUBREG) | |
9544 | { | |
9545 | regno = SUBREG_WORD (dst); | |
9546 | dst = SUBREG_REG (dst); | |
9547 | } | |
9548 | if (GET_CODE (dst) != REG) | |
9549 | return; | |
9550 | ||
9551 | regno += REGNO (dst); | |
9552 | ||
f93233bb JL |
9553 | if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET |
9554 | && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT | |
9555 | && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT | |
9556 | && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) | |
5adf6da0 R |
9557 | { |
9558 | rtx src = SET_SRC (set); | |
9559 | ||
9560 | reg_mode[regno] = mode; | |
9561 | switch (GET_CODE (src)) | |
9562 | { | |
9563 | case PLUS: | |
9564 | { | |
9565 | rtx src0 = XEXP (src, 0); | |
9566 | if (GET_CODE (src0) == REG) | |
9567 | { | |
9568 | if (REGNO (src0) != regno | |
9569 | || reg_offset[regno] != const0_rtx) | |
9570 | { | |
9571 | reg_base_reg[regno] = REGNO (src0); | |
9572 | reg_set_luid[regno] = move2add_luid; | |
9573 | } | |
9574 | reg_offset[regno] = XEXP (src, 1); | |
9575 | break; | |
9576 | } | |
9577 | reg_set_luid[regno] = move2add_luid; | |
9578 | reg_offset[regno] = set; /* Invalidate contents. */ | |
9579 | break; | |
9580 | } | |
9581 | ||
9582 | case REG: | |
9583 | reg_base_reg[regno] = REGNO (SET_SRC (set)); | |
9584 | reg_offset[regno] = const0_rtx; | |
9585 | reg_set_luid[regno] = move2add_luid; | |
9586 | break; | |
9587 | ||
9588 | default: | |
9589 | reg_base_reg[regno] = -1; | |
9590 | reg_offset[regno] = SET_SRC (set); | |
9591 | reg_set_luid[regno] = move2add_luid; | |
9592 | break; | |
9593 | } | |
9594 | } | |
9595 | else | |
9596 | { | |
9597 | for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--) | |
9598 | { | |
9599 | /* Indicate that this register has been recently written to, | |
9600 | but the exact contents are not available. */ | |
9601 | reg_set_luid[i] = move2add_luid; | |
9602 | reg_offset[i] = dst; | |
9603 | } | |
9604 | } | |
9605 | } | |
2dfa9a87 MH |
9606 | |
9607 | #ifdef AUTO_INC_DEC | |
9608 | static void | |
9609 | add_auto_inc_notes (insn, x) | |
9610 | rtx insn; | |
9611 | rtx x; | |
9612 | { | |
9613 | enum rtx_code code = GET_CODE (x); | |
6f7d635c | 9614 | const char *fmt; |
2dfa9a87 MH |
9615 | int i, j; |
9616 | ||
9617 | if (code == MEM && auto_inc_p (XEXP (x, 0))) | |
9618 | { | |
9619 | REG_NOTES (insn) | |
9620 | = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn)); | |
9621 | return; | |
9622 | } | |
9623 | ||
9624 | /* Scan all the operand sub-expressions. */ | |
9625 | fmt = GET_RTX_FORMAT (code); | |
9626 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
9627 | { | |
9628 | if (fmt[i] == 'e') | |
9629 | add_auto_inc_notes (insn, XEXP (x, i)); | |
9630 | else if (fmt[i] == 'E') | |
9631 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
9632 | add_auto_inc_notes (insn, XVECEXP (x, i, j)); | |
9633 | } | |
9634 | } | |
9635 | #endif |