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32131a9c | 1 | /* Reload pseudo regs into hard regs for insns that require hard regs. |
af841dbd | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
e56b4594 | 3 | 1999, 2000, 2001 Free Software Foundation, Inc. |
32131a9c | 4 | |
1322177d | 5 | This file is part of GCC. |
32131a9c | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
32131a9c | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
32131a9c RK |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
32131a9c | 21 | |
32131a9c | 22 | #include "config.h" |
670ee920 | 23 | #include "system.h" |
cab634f2 KG |
24 | |
25 | #include "machmode.h" | |
26 | #include "hard-reg-set.h" | |
32131a9c | 27 | #include "rtl.h" |
6baf1cc8 | 28 | #include "tm_p.h" |
32131a9c RK |
29 | #include "obstack.h" |
30 | #include "insn-config.h" | |
32131a9c | 31 | #include "flags.h" |
49ad7cfa | 32 | #include "function.h" |
32131a9c | 33 | #include "expr.h" |
e78d8e51 | 34 | #include "optabs.h" |
32131a9c | 35 | #include "regs.h" |
cad6f7d0 | 36 | #include "basic-block.h" |
32131a9c RK |
37 | #include "reload.h" |
38 | #include "recog.h" | |
32131a9c | 39 | #include "output.h" |
eab5c70a | 40 | #include "cselib.h" |
a9c366bf | 41 | #include "real.h" |
10f0ad3d | 42 | #include "toplev.h" |
39f95a2c | 43 | #include "except.h" |
32131a9c RK |
44 | |
45 | /* This file contains the reload pass of the compiler, which is | |
46 | run after register allocation has been done. It checks that | |
47 | each insn is valid (operands required to be in registers really | |
48 | are in registers of the proper class) and fixes up invalid ones | |
49 | by copying values temporarily into registers for the insns | |
50 | that need them. | |
51 | ||
52 | The results of register allocation are described by the vector | |
53 | reg_renumber; the insns still contain pseudo regs, but reg_renumber | |
54 | can be used to find which hard reg, if any, a pseudo reg is in. | |
55 | ||
56 | The technique we always use is to free up a few hard regs that are | |
57 | called ``reload regs'', and for each place where a pseudo reg | |
58 | must be in a hard reg, copy it temporarily into one of the reload regs. | |
59 | ||
03acd8f8 BS |
60 | Reload regs are allocated locally for every instruction that needs |
61 | reloads. When there are pseudos which are allocated to a register that | |
62 | has been chosen as a reload reg, such pseudos must be ``spilled''. | |
63 | This means that they go to other hard regs, or to stack slots if no other | |
32131a9c RK |
64 | available hard regs can be found. Spilling can invalidate more |
65 | insns, requiring additional need for reloads, so we must keep checking | |
66 | until the process stabilizes. | |
67 | ||
68 | For machines with different classes of registers, we must keep track | |
69 | of the register class needed for each reload, and make sure that | |
70 | we allocate enough reload registers of each class. | |
71 | ||
72 | The file reload.c contains the code that checks one insn for | |
73 | validity and reports the reloads that it needs. This file | |
74 | is in charge of scanning the entire rtl code, accumulating the | |
75 | reload needs, spilling, assigning reload registers to use for | |
76 | fixing up each insn, and generating the new insns to copy values | |
77 | into the reload registers. */ | |
546b63fb | 78 | |
546b63fb | 79 | #ifndef REGISTER_MOVE_COST |
e56b4594 | 80 | #define REGISTER_MOVE_COST(m, x, y) 2 |
546b63fb | 81 | #endif |
2a3e384f RH |
82 | |
83 | #ifndef LOCAL_REGNO | |
84 | #define LOCAL_REGNO(REGNO) 0 | |
85 | #endif | |
32131a9c RK |
86 | \f |
87 | /* During reload_as_needed, element N contains a REG rtx for the hard reg | |
0f41302f | 88 | into which reg N has been reloaded (perhaps for a previous insn). */ |
32131a9c RK |
89 | static rtx *reg_last_reload_reg; |
90 | ||
91 | /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn | |
92 | for an output reload that stores into reg N. */ | |
93 | static char *reg_has_output_reload; | |
94 | ||
95 | /* Indicates which hard regs are reload-registers for an output reload | |
96 | in the current insn. */ | |
97 | static HARD_REG_SET reg_is_output_reload; | |
98 | ||
99 | /* Element N is the constant value to which pseudo reg N is equivalent, | |
100 | or zero if pseudo reg N is not equivalent to a constant. | |
101 | find_reloads looks at this in order to replace pseudo reg N | |
102 | with the constant it stands for. */ | |
103 | rtx *reg_equiv_constant; | |
104 | ||
105 | /* Element N is a memory location to which pseudo reg N is equivalent, | |
106 | prior to any register elimination (such as frame pointer to stack | |
107 | pointer). Depending on whether or not it is a valid address, this value | |
108 | is transferred to either reg_equiv_address or reg_equiv_mem. */ | |
4803a34a | 109 | rtx *reg_equiv_memory_loc; |
32131a9c RK |
110 | |
111 | /* Element N is the address of stack slot to which pseudo reg N is equivalent. | |
112 | This is used when the address is not valid as a memory address | |
113 | (because its displacement is too big for the machine.) */ | |
114 | rtx *reg_equiv_address; | |
115 | ||
116 | /* Element N is the memory slot to which pseudo reg N is equivalent, | |
117 | or zero if pseudo reg N is not equivalent to a memory slot. */ | |
118 | rtx *reg_equiv_mem; | |
119 | ||
120 | /* Widest width in which each pseudo reg is referred to (via subreg). */ | |
770ae6cc | 121 | static unsigned int *reg_max_ref_width; |
32131a9c | 122 | |
135eb61c | 123 | /* Element N is the list of insns that initialized reg N from its equivalent |
32131a9c RK |
124 | constant or memory slot. */ |
125 | static rtx *reg_equiv_init; | |
126 | ||
03acd8f8 BS |
127 | /* Vector to remember old contents of reg_renumber before spilling. */ |
128 | static short *reg_old_renumber; | |
129 | ||
e6e52be0 | 130 | /* During reload_as_needed, element N contains the last pseudo regno reloaded |
03acd8f8 | 131 | into hard register N. If that pseudo reg occupied more than one register, |
32131a9c RK |
132 | reg_reloaded_contents points to that pseudo for each spill register in |
133 | use; all of these must remain set for an inheritance to occur. */ | |
134 | static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; | |
135 | ||
136 | /* During reload_as_needed, element N contains the insn for which | |
e6e52be0 R |
137 | hard register N was last used. Its contents are significant only |
138 | when reg_reloaded_valid is set for this register. */ | |
32131a9c RK |
139 | static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; |
140 | ||
e6e52be0 R |
141 | /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */ |
142 | static HARD_REG_SET reg_reloaded_valid; | |
143 | /* Indicate if the register was dead at the end of the reload. | |
144 | This is only valid if reg_reloaded_contents is set and valid. */ | |
145 | static HARD_REG_SET reg_reloaded_dead; | |
146 | ||
32131a9c RK |
147 | /* Number of spill-regs so far; number of valid elements of spill_regs. */ |
148 | static int n_spills; | |
149 | ||
150 | /* In parallel with spill_regs, contains REG rtx's for those regs. | |
151 | Holds the last rtx used for any given reg, or 0 if it has never | |
152 | been used for spilling yet. This rtx is reused, provided it has | |
153 | the proper mode. */ | |
154 | static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
155 | ||
156 | /* In parallel with spill_regs, contains nonzero for a spill reg | |
157 | that was stored after the last time it was used. | |
158 | The precise value is the insn generated to do the store. */ | |
159 | static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
160 | ||
cb2afeb3 R |
161 | /* This is the register that was stored with spill_reg_store. This is a |
162 | copy of reload_out / reload_out_reg when the value was stored; if | |
163 | reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */ | |
164 | static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; | |
165 | ||
32131a9c RK |
166 | /* This table is the inverse mapping of spill_regs: |
167 | indexed by hard reg number, | |
168 | it contains the position of that reg in spill_regs, | |
05d10675 | 169 | or -1 for something that is not in spill_regs. |
13c8e8e3 JL |
170 | |
171 | ?!? This is no longer accurate. */ | |
32131a9c RK |
172 | static short spill_reg_order[FIRST_PSEUDO_REGISTER]; |
173 | ||
03acd8f8 BS |
174 | /* This reg set indicates registers that can't be used as spill registers for |
175 | the currently processed insn. These are the hard registers which are live | |
176 | during the insn, but not allocated to pseudos, as well as fixed | |
177 | registers. */ | |
32131a9c RK |
178 | static HARD_REG_SET bad_spill_regs; |
179 | ||
03acd8f8 BS |
180 | /* These are the hard registers that can't be used as spill register for any |
181 | insn. This includes registers used for user variables and registers that | |
182 | we can't eliminate. A register that appears in this set also can't be used | |
183 | to retry register allocation. */ | |
184 | static HARD_REG_SET bad_spill_regs_global; | |
185 | ||
32131a9c | 186 | /* Describes order of use of registers for reloading |
03acd8f8 BS |
187 | of spilled pseudo-registers. `n_spills' is the number of |
188 | elements that are actually valid; new ones are added at the end. | |
189 | ||
190 | Both spill_regs and spill_reg_order are used on two occasions: | |
191 | once during find_reload_regs, where they keep track of the spill registers | |
192 | for a single insn, but also during reload_as_needed where they show all | |
193 | the registers ever used by reload. For the latter case, the information | |
194 | is calculated during finish_spills. */ | |
32131a9c RK |
195 | static short spill_regs[FIRST_PSEUDO_REGISTER]; |
196 | ||
03acd8f8 BS |
197 | /* This vector of reg sets indicates, for each pseudo, which hard registers |
198 | may not be used for retrying global allocation because the register was | |
199 | formerly spilled from one of them. If we allowed reallocating a pseudo to | |
200 | a register that it was already allocated to, reload might not | |
201 | terminate. */ | |
202 | static HARD_REG_SET *pseudo_previous_regs; | |
203 | ||
204 | /* This vector of reg sets indicates, for each pseudo, which hard | |
205 | registers may not be used for retrying global allocation because they | |
206 | are used as spill registers during one of the insns in which the | |
207 | pseudo is live. */ | |
208 | static HARD_REG_SET *pseudo_forbidden_regs; | |
209 | ||
210 | /* All hard regs that have been used as spill registers for any insn are | |
211 | marked in this set. */ | |
212 | static HARD_REG_SET used_spill_regs; | |
8b4f9969 | 213 | |
4079cd63 JW |
214 | /* Index of last register assigned as a spill register. We allocate in |
215 | a round-robin fashion. */ | |
4079cd63 JW |
216 | static int last_spill_reg; |
217 | ||
32131a9c RK |
218 | /* Nonzero if indirect addressing is supported on the machine; this means |
219 | that spilling (REG n) does not require reloading it into a register in | |
220 | order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The | |
221 | value indicates the level of indirect addressing supported, e.g., two | |
222 | means that (MEM (MEM (REG n))) is also valid if (REG n) does not get | |
223 | a hard register. */ | |
32131a9c RK |
224 | static char spill_indirect_levels; |
225 | ||
226 | /* Nonzero if indirect addressing is supported when the innermost MEM is | |
227 | of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to | |
6d2f8887 | 228 | which these are valid is the same as spill_indirect_levels, above. */ |
32131a9c RK |
229 | char indirect_symref_ok; |
230 | ||
231 | /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ | |
32131a9c RK |
232 | char double_reg_address_ok; |
233 | ||
234 | /* Record the stack slot for each spilled hard register. */ | |
32131a9c RK |
235 | static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; |
236 | ||
237 | /* Width allocated so far for that stack slot. */ | |
770ae6cc | 238 | static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; |
32131a9c | 239 | |
7609e720 | 240 | /* Record which pseudos needed to be spilled. */ |
f5d8c9f4 BS |
241 | static regset_head spilled_pseudos; |
242 | ||
243 | /* Used for communication between order_regs_for_reload and count_pseudo. | |
244 | Used to avoid counting one pseudo twice. */ | |
245 | static regset_head pseudos_counted; | |
7609e720 | 246 | |
32131a9c RK |
247 | /* First uid used by insns created by reload in this function. |
248 | Used in find_equiv_reg. */ | |
249 | int reload_first_uid; | |
250 | ||
251 | /* Flag set by local-alloc or global-alloc if anything is live in | |
252 | a call-clobbered reg across calls. */ | |
32131a9c RK |
253 | int caller_save_needed; |
254 | ||
255 | /* Set to 1 while reload_as_needed is operating. | |
256 | Required by some machines to handle any generated moves differently. */ | |
32131a9c RK |
257 | int reload_in_progress = 0; |
258 | ||
259 | /* These arrays record the insn_code of insns that may be needed to | |
260 | perform input and output reloads of special objects. They provide a | |
261 | place to pass a scratch register. */ | |
32131a9c RK |
262 | enum insn_code reload_in_optab[NUM_MACHINE_MODES]; |
263 | enum insn_code reload_out_optab[NUM_MACHINE_MODES]; | |
264 | ||
d45cf215 | 265 | /* This obstack is used for allocation of rtl during register elimination. |
32131a9c RK |
266 | The allocated storage can be freed once find_reloads has processed the |
267 | insn. */ | |
32131a9c | 268 | struct obstack reload_obstack; |
cad6f7d0 BS |
269 | |
270 | /* Points to the beginning of the reload_obstack. All insn_chain structures | |
271 | are allocated first. */ | |
272 | char *reload_startobj; | |
273 | ||
274 | /* The point after all insn_chain structures. Used to quickly deallocate | |
f5d8c9f4 | 275 | memory allocated in copy_reloads during calculate_needs_all_insns. */ |
32131a9c RK |
276 | char *reload_firstobj; |
277 | ||
f5d8c9f4 BS |
278 | /* This points before all local rtl generated by register elimination. |
279 | Used to quickly free all memory after processing one insn. */ | |
280 | static char *reload_insn_firstobj; | |
281 | ||
32131a9c RK |
282 | #define obstack_chunk_alloc xmalloc |
283 | #define obstack_chunk_free free | |
284 | ||
cad6f7d0 BS |
285 | /* List of insn_chain instructions, one for every insn that reload needs to |
286 | examine. */ | |
287 | struct insn_chain *reload_insn_chain; | |
7609e720 | 288 | |
dfb7c80f JL |
289 | #ifdef TREE_CODE |
290 | extern tree current_function_decl; | |
291 | #else | |
122a860e | 292 | extern union tree_node *current_function_decl; |
dfb7c80f JL |
293 | #endif |
294 | ||
03acd8f8 | 295 | /* List of all insns needing reloads. */ |
7609e720 | 296 | static struct insn_chain *insns_need_reload; |
32131a9c RK |
297 | \f |
298 | /* This structure is used to record information about register eliminations. | |
299 | Each array entry describes one possible way of eliminating a register | |
300 | in favor of another. If there is more than one way of eliminating a | |
301 | particular register, the most preferred should be specified first. */ | |
302 | ||
590cf94d | 303 | struct elim_table |
32131a9c | 304 | { |
0f41302f MS |
305 | int from; /* Register number to be eliminated. */ |
306 | int to; /* Register number used as replacement. */ | |
307 | int initial_offset; /* Initial difference between values. */ | |
308 | int can_eliminate; /* Non-zero if this elimination can be done. */ | |
32131a9c | 309 | int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over |
0f41302f MS |
310 | insns made by reload. */ |
311 | int offset; /* Current offset between the two regs. */ | |
0f41302f MS |
312 | int previous_offset; /* Offset at end of previous insn. */ |
313 | int ref_outside_mem; /* "to" has been referenced outside a MEM. */ | |
32131a9c RK |
314 | rtx from_rtx; /* REG rtx for the register to be eliminated. |
315 | We cannot simply compare the number since | |
316 | we might then spuriously replace a hard | |
317 | register corresponding to a pseudo | |
0f41302f MS |
318 | assigned to the reg to be eliminated. */ |
319 | rtx to_rtx; /* REG rtx for the replacement. */ | |
590cf94d KG |
320 | }; |
321 | ||
1d7254c5 | 322 | static struct elim_table *reg_eliminate = 0; |
590cf94d KG |
323 | |
324 | /* This is an intermediate structure to initialize the table. It has | |
1d7254c5 | 325 | exactly the members provided by ELIMINABLE_REGS. */ |
590cf94d KG |
326 | static struct elim_table_1 |
327 | { | |
328 | int from; | |
329 | int to; | |
330 | } reg_eliminate_1[] = | |
32131a9c RK |
331 | |
332 | /* If a set of eliminable registers was specified, define the table from it. | |
333 | Otherwise, default to the normal case of the frame pointer being | |
334 | replaced by the stack pointer. */ | |
335 | ||
336 | #ifdef ELIMINABLE_REGS | |
337 | ELIMINABLE_REGS; | |
338 | #else | |
339 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; | |
340 | #endif | |
341 | ||
b6a1cbae | 342 | #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1) |
32131a9c RK |
343 | |
344 | /* Record the number of pending eliminations that have an offset not equal | |
345 | to their initial offset. If non-zero, we use a new copy of each | |
346 | replacement result in any insns encountered. */ | |
cb2afeb3 | 347 | int num_not_at_initial_offset; |
32131a9c RK |
348 | |
349 | /* Count the number of registers that we may be able to eliminate. */ | |
350 | static int num_eliminable; | |
2b49ee39 R |
351 | /* And the number of registers that are equivalent to a constant that |
352 | can be eliminated to frame_pointer / arg_pointer + constant. */ | |
353 | static int num_eliminable_invariants; | |
32131a9c RK |
354 | |
355 | /* For each label, we record the offset of each elimination. If we reach | |
356 | a label by more than one path and an offset differs, we cannot do the | |
357 | elimination. This information is indexed by the number of the label. | |
358 | The first table is an array of flags that records whether we have yet | |
359 | encountered a label and the second table is an array of arrays, one | |
360 | entry in the latter array for each elimination. */ | |
361 | ||
362 | static char *offsets_known_at; | |
363 | static int (*offsets_at)[NUM_ELIMINABLE_REGS]; | |
364 | ||
365 | /* Number of labels in the current function. */ | |
366 | ||
367 | static int num_labels; | |
368 | \f | |
174fa2c4 AJ |
369 | static void replace_pseudos_in_call_usage PARAMS((rtx *, |
370 | enum machine_mode, | |
371 | rtx)); | |
cdadb1dd KG |
372 | static void maybe_fix_stack_asms PARAMS ((void)); |
373 | static void copy_reloads PARAMS ((struct insn_chain *)); | |
374 | static void calculate_needs_all_insns PARAMS ((int)); | |
e04ca094 JL |
375 | static int find_reg PARAMS ((struct insn_chain *, int)); |
376 | static void find_reload_regs PARAMS ((struct insn_chain *)); | |
377 | static void select_reload_regs PARAMS ((void)); | |
cdadb1dd KG |
378 | static void delete_caller_save_insns PARAMS ((void)); |
379 | ||
380 | static void spill_failure PARAMS ((rtx, enum reg_class)); | |
381 | static void count_spilled_pseudo PARAMS ((int, int, int)); | |
382 | static void delete_dead_insn PARAMS ((rtx)); | |
174fa2c4 | 383 | static void alter_reg PARAMS ((int, int)); |
cdadb1dd KG |
384 | static void set_label_offsets PARAMS ((rtx, rtx, int)); |
385 | static void check_eliminable_occurrences PARAMS ((rtx)); | |
386 | static void elimination_effects PARAMS ((rtx, enum machine_mode)); | |
387 | static int eliminate_regs_in_insn PARAMS ((rtx, int)); | |
388 | static void update_eliminable_offsets PARAMS ((void)); | |
389 | static void mark_not_eliminable PARAMS ((rtx, rtx, void *)); | |
390 | static void set_initial_elim_offsets PARAMS ((void)); | |
391 | static void verify_initial_elim_offsets PARAMS ((void)); | |
392 | static void set_initial_label_offsets PARAMS ((void)); | |
393 | static void set_offsets_for_label PARAMS ((rtx)); | |
394 | static void init_elim_table PARAMS ((void)); | |
395 | static void update_eliminables PARAMS ((HARD_REG_SET *)); | |
e04ca094 JL |
396 | static void spill_hard_reg PARAMS ((unsigned int, int)); |
397 | static int finish_spills PARAMS ((int)); | |
cdadb1dd KG |
398 | static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *)); |
399 | static void scan_paradoxical_subregs PARAMS ((rtx)); | |
400 | static void count_pseudo PARAMS ((int)); | |
401 | static void order_regs_for_reload PARAMS ((struct insn_chain *)); | |
e04ca094 | 402 | static void reload_as_needed PARAMS ((int)); |
cdadb1dd KG |
403 | static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *)); |
404 | static int reload_reg_class_lower PARAMS ((const PTR, const PTR)); | |
770ae6cc RK |
405 | static void mark_reload_reg_in_use PARAMS ((unsigned int, int, |
406 | enum reload_type, | |
407 | enum machine_mode)); | |
408 | static void clear_reload_reg_in_use PARAMS ((unsigned int, int, | |
409 | enum reload_type, | |
410 | enum machine_mode)); | |
411 | static int reload_reg_free_p PARAMS ((unsigned int, int, | |
412 | enum reload_type)); | |
304a22dd R |
413 | static int reload_reg_free_for_value_p PARAMS ((int, int, int, |
414 | enum reload_type, | |
770ae6cc | 415 | rtx, rtx, int, int)); |
c02cad8f BS |
416 | static int free_for_value_p PARAMS ((int, enum machine_mode, int, |
417 | enum reload_type, rtx, rtx, | |
418 | int, int)); | |
770ae6cc RK |
419 | static int reload_reg_reaches_end_p PARAMS ((unsigned int, int, |
420 | enum reload_type)); | |
421 | static int allocate_reload_reg PARAMS ((struct insn_chain *, int, | |
422 | int)); | |
ff6534ad | 423 | static int conflicts_with_override PARAMS ((rtx)); |
cdadb1dd KG |
424 | static void failed_reload PARAMS ((rtx, int)); |
425 | static int set_reload_reg PARAMS ((int, int)); | |
426 | static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *)); | |
427 | static void choose_reload_regs PARAMS ((struct insn_chain *)); | |
428 | static void merge_assigned_reloads PARAMS ((rtx)); | |
429 | static void emit_input_reload_insns PARAMS ((struct insn_chain *, | |
770ae6cc | 430 | struct reload *, rtx, int)); |
cdadb1dd | 431 | static void emit_output_reload_insns PARAMS ((struct insn_chain *, |
770ae6cc | 432 | struct reload *, int)); |
cdadb1dd | 433 | static void do_input_reload PARAMS ((struct insn_chain *, |
770ae6cc | 434 | struct reload *, int)); |
cdadb1dd | 435 | static void do_output_reload PARAMS ((struct insn_chain *, |
770ae6cc | 436 | struct reload *, int)); |
e04ca094 | 437 | static void emit_reload_insns PARAMS ((struct insn_chain *)); |
cdadb1dd KG |
438 | static void delete_output_reload PARAMS ((rtx, int, int)); |
439 | static void delete_address_reloads PARAMS ((rtx, rtx)); | |
440 | static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx)); | |
441 | static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int)); | |
442 | static int constraint_accepts_reg_p PARAMS ((const char *, rtx)); | |
443 | static void reload_cse_regs_1 PARAMS ((rtx)); | |
eab5c70a | 444 | static int reload_cse_noop_set_p PARAMS ((rtx)); |
cdadb1dd KG |
445 | static int reload_cse_simplify_set PARAMS ((rtx, rtx)); |
446 | static int reload_cse_simplify_operands PARAMS ((rtx)); | |
770ae6cc RK |
447 | static void reload_combine PARAMS ((void)); |
448 | static void reload_combine_note_use PARAMS ((rtx *, rtx)); | |
449 | static void reload_combine_note_store PARAMS ((rtx, rtx, void *)); | |
450 | static void reload_cse_move2add PARAMS ((rtx)); | |
451 | static void move2add_note_store PARAMS ((rtx, rtx, void *)); | |
2dfa9a87 | 452 | #ifdef AUTO_INC_DEC |
770ae6cc | 453 | static void add_auto_inc_notes PARAMS ((rtx, rtx)); |
2dfa9a87 | 454 | #endif |
94bd63e5 | 455 | static void copy_eh_notes PARAMS ((rtx, rtx)); |
61f5625b | 456 | static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode, |
770ae6cc | 457 | HOST_WIDE_INT)); |
cdadb1dd KG |
458 | static void failed_reload PARAMS ((rtx, int)); |
459 | static int set_reload_reg PARAMS ((int, int)); | |
e77d72cb KG |
460 | static void reload_cse_delete_noop_set PARAMS ((rtx, rtx)); |
461 | static void reload_cse_simplify PARAMS ((rtx)); | |
f1330226 | 462 | static void fixup_abnormal_edges PARAMS ((void)); |
e04ca094 | 463 | extern void dump_needs PARAMS ((struct insn_chain *)); |
32131a9c | 464 | \f |
546b63fb RK |
465 | /* Initialize the reload pass once per compilation. */ |
466 | ||
32131a9c RK |
467 | void |
468 | init_reload () | |
469 | { | |
b3694847 | 470 | int i; |
32131a9c RK |
471 | |
472 | /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. | |
473 | Set spill_indirect_levels to the number of levels such addressing is | |
474 | permitted, zero if it is not permitted at all. */ | |
475 | ||
b3694847 | 476 | rtx tem |
38a448ca RH |
477 | = gen_rtx_MEM (Pmode, |
478 | gen_rtx_PLUS (Pmode, | |
c5c76735 JL |
479 | gen_rtx_REG (Pmode, |
480 | LAST_VIRTUAL_REGISTER + 1), | |
38a448ca | 481 | GEN_INT (4))); |
32131a9c RK |
482 | spill_indirect_levels = 0; |
483 | ||
484 | while (memory_address_p (QImode, tem)) | |
485 | { | |
486 | spill_indirect_levels++; | |
38a448ca | 487 | tem = gen_rtx_MEM (Pmode, tem); |
32131a9c RK |
488 | } |
489 | ||
490 | /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ | |
491 | ||
38a448ca | 492 | tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo")); |
32131a9c RK |
493 | indirect_symref_ok = memory_address_p (QImode, tem); |
494 | ||
495 | /* See if reg+reg is a valid (and offsettable) address. */ | |
496 | ||
65701fd2 | 497 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
57caa638 | 498 | { |
38a448ca RH |
499 | tem = gen_rtx_PLUS (Pmode, |
500 | gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), | |
501 | gen_rtx_REG (Pmode, i)); | |
c5c76735 | 502 | |
57caa638 RS |
503 | /* This way, we make sure that reg+reg is an offsettable address. */ |
504 | tem = plus_constant (tem, 4); | |
505 | ||
506 | if (memory_address_p (QImode, tem)) | |
507 | { | |
508 | double_reg_address_ok = 1; | |
509 | break; | |
510 | } | |
511 | } | |
32131a9c | 512 | |
0f41302f | 513 | /* Initialize obstack for our rtl allocation. */ |
32131a9c | 514 | gcc_obstack_init (&reload_obstack); |
cad6f7d0 | 515 | reload_startobj = (char *) obstack_alloc (&reload_obstack, 0); |
f5d8c9f4 BS |
516 | |
517 | INIT_REG_SET (&spilled_pseudos); | |
518 | INIT_REG_SET (&pseudos_counted); | |
32131a9c RK |
519 | } |
520 | ||
cad6f7d0 BS |
521 | /* List of insn chains that are currently unused. */ |
522 | static struct insn_chain *unused_insn_chains = 0; | |
523 | ||
524 | /* Allocate an empty insn_chain structure. */ | |
525 | struct insn_chain * | |
526 | new_insn_chain () | |
527 | { | |
528 | struct insn_chain *c; | |
529 | ||
530 | if (unused_insn_chains == 0) | |
531 | { | |
8db99db2 KG |
532 | c = (struct insn_chain *) |
533 | obstack_alloc (&reload_obstack, sizeof (struct insn_chain)); | |
239a0f5b BS |
534 | INIT_REG_SET (&c->live_throughout); |
535 | INIT_REG_SET (&c->dead_or_set); | |
cad6f7d0 BS |
536 | } |
537 | else | |
538 | { | |
539 | c = unused_insn_chains; | |
540 | unused_insn_chains = c->next; | |
541 | } | |
542 | c->is_caller_save_insn = 0; | |
03acd8f8 | 543 | c->need_operand_change = 0; |
cad6f7d0 BS |
544 | c->need_reload = 0; |
545 | c->need_elim = 0; | |
546 | return c; | |
547 | } | |
548 | ||
7609e720 BS |
549 | /* Small utility function to set all regs in hard reg set TO which are |
550 | allocated to pseudos in regset FROM. */ | |
770ae6cc | 551 | |
7609e720 BS |
552 | void |
553 | compute_use_by_pseudos (to, from) | |
554 | HARD_REG_SET *to; | |
555 | regset from; | |
556 | { | |
770ae6cc RK |
557 | unsigned int regno; |
558 | ||
7609e720 BS |
559 | EXECUTE_IF_SET_IN_REG_SET |
560 | (from, FIRST_PSEUDO_REGISTER, regno, | |
561 | { | |
562 | int r = reg_renumber[regno]; | |
563 | int nregs; | |
770ae6cc | 564 | |
7609e720 | 565 | if (r < 0) |
404d95c4 R |
566 | { |
567 | /* reload_combine uses the information from | |
e881bb1b RH |
568 | BASIC_BLOCK->global_live_at_start, which might still |
569 | contain registers that have not actually been allocated | |
570 | since they have an equivalence. */ | |
404d95c4 R |
571 | if (! reload_completed) |
572 | abort (); | |
573 | } | |
574 | else | |
575 | { | |
576 | nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno)); | |
577 | while (nregs-- > 0) | |
578 | SET_HARD_REG_BIT (*to, r + nregs); | |
579 | } | |
7609e720 BS |
580 | }); |
581 | } | |
f474c6f8 AO |
582 | |
583 | /* Replace all pseudos found in LOC with their corresponding | |
584 | equivalences. */ | |
585 | ||
586 | static void | |
587 | replace_pseudos_in_call_usage (loc, mem_mode, usage) | |
588 | rtx *loc; | |
589 | enum machine_mode mem_mode; | |
590 | rtx usage; | |
591 | { | |
592 | rtx x = *loc; | |
593 | enum rtx_code code; | |
594 | const char *fmt; | |
595 | int i, j; | |
596 | ||
597 | if (! x) | |
598 | return; | |
174fa2c4 | 599 | |
f474c6f8 AO |
600 | code = GET_CODE (x); |
601 | if (code == REG) | |
602 | { | |
ae0ed63a | 603 | unsigned int regno = REGNO (x); |
086fef9e AO |
604 | |
605 | if (regno < FIRST_PSEUDO_REGISTER) | |
f474c6f8 AO |
606 | return; |
607 | ||
608 | x = eliminate_regs (x, mem_mode, usage); | |
609 | if (x != *loc) | |
610 | { | |
611 | *loc = x; | |
612 | replace_pseudos_in_call_usage (loc, mem_mode, usage); | |
613 | return; | |
614 | } | |
615 | ||
086fef9e AO |
616 | if (reg_equiv_constant[regno]) |
617 | *loc = reg_equiv_constant[regno]; | |
618 | else if (reg_equiv_mem[regno]) | |
619 | *loc = reg_equiv_mem[regno]; | |
620 | else if (reg_equiv_address[regno]) | |
621 | *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]); | |
622 | else if (GET_CODE (regno_reg_rtx[regno]) != REG | |
623 | || REGNO (regno_reg_rtx[regno]) != regno) | |
624 | *loc = regno_reg_rtx[regno]; | |
f474c6f8 AO |
625 | else |
626 | abort (); | |
627 | ||
628 | return; | |
629 | } | |
630 | else if (code == MEM) | |
631 | { | |
632 | replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage); | |
633 | return; | |
634 | } | |
174fa2c4 | 635 | |
f474c6f8 AO |
636 | /* Process each of our operands recursively. */ |
637 | fmt = GET_RTX_FORMAT (code); | |
638 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
639 | if (*fmt == 'e') | |
640 | replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage); | |
641 | else if (*fmt == 'E') | |
642 | for (j = 0; j < XVECLEN (x, i); j++) | |
643 | replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage); | |
644 | } | |
645 | ||
03acd8f8 | 646 | \f |
1e5bd841 BS |
647 | /* Global variables used by reload and its subroutines. */ |
648 | ||
1e5bd841 BS |
649 | /* Set during calculate_needs if an insn needs register elimination. */ |
650 | static int something_needs_elimination; | |
cb2afeb3 R |
651 | /* Set during calculate_needs if an insn needs an operand changed. */ |
652 | int something_needs_operands_changed; | |
1e5bd841 | 653 | |
1e5bd841 BS |
654 | /* Nonzero means we couldn't get enough spill regs. */ |
655 | static int failure; | |
656 | ||
546b63fb | 657 | /* Main entry point for the reload pass. |
32131a9c RK |
658 | |
659 | FIRST is the first insn of the function being compiled. | |
660 | ||
661 | GLOBAL nonzero means we were called from global_alloc | |
662 | and should attempt to reallocate any pseudoregs that we | |
663 | displace from hard regs we will use for reloads. | |
664 | If GLOBAL is zero, we do not have enough information to do that, | |
665 | so any pseudo reg that is spilled must go to the stack. | |
666 | ||
5352b11a RS |
667 | Return value is nonzero if reload failed |
668 | and we must not do any more for this function. */ | |
669 | ||
670 | int | |
e04ca094 | 671 | reload (first, global) |
32131a9c RK |
672 | rtx first; |
673 | int global; | |
32131a9c | 674 | { |
b3694847 SS |
675 | int i; |
676 | rtx insn; | |
677 | struct elim_table *ep; | |
32131a9c | 678 | |
a68d4b75 BK |
679 | /* The two pointers used to track the true location of the memory used |
680 | for label offsets. */ | |
9714cf43 | 681 | char *real_known_ptr = NULL; |
a68d4b75 BK |
682 | int (*real_at_ptr)[NUM_ELIMINABLE_REGS]; |
683 | ||
32131a9c RK |
684 | /* Make sure even insns with volatile mem refs are recognizable. */ |
685 | init_recog (); | |
686 | ||
1e5bd841 BS |
687 | failure = 0; |
688 | ||
cad6f7d0 BS |
689 | reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); |
690 | ||
437a710d BS |
691 | /* Make sure that the last insn in the chain |
692 | is not something that needs reloading. */ | |
6496a589 | 693 | emit_note (NULL, NOTE_INSN_DELETED); |
437a710d | 694 | |
32131a9c RK |
695 | /* Enable find_equiv_reg to distinguish insns made by reload. */ |
696 | reload_first_uid = get_max_uid (); | |
697 | ||
0dadecf6 RK |
698 | #ifdef SECONDARY_MEMORY_NEEDED |
699 | /* Initialize the secondary memory table. */ | |
700 | clear_secondary_mem (); | |
701 | #endif | |
702 | ||
32131a9c | 703 | /* We don't have a stack slot for any spill reg yet. */ |
961192e1 JM |
704 | memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot); |
705 | memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width); | |
32131a9c | 706 | |
a8efe40d RK |
707 | /* Initialize the save area information for caller-save, in case some |
708 | are needed. */ | |
709 | init_save_areas (); | |
a8fdc208 | 710 | |
32131a9c RK |
711 | /* Compute which hard registers are now in use |
712 | as homes for pseudo registers. | |
713 | This is done here rather than (eg) in global_alloc | |
714 | because this point is reached even if not optimizing. */ | |
32131a9c RK |
715 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
716 | mark_home_live (i); | |
717 | ||
8dddd002 RK |
718 | /* A function that receives a nonlocal goto must save all call-saved |
719 | registers. */ | |
720 | if (current_function_has_nonlocal_label) | |
721 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2a3e384f RH |
722 | if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) |
723 | regs_ever_live[i] = 1; | |
8dddd002 | 724 | |
32131a9c RK |
725 | /* Find all the pseudo registers that didn't get hard regs |
726 | but do have known equivalent constants or memory slots. | |
727 | These include parameters (known equivalent to parameter slots) | |
728 | and cse'd or loop-moved constant memory addresses. | |
729 | ||
730 | Record constant equivalents in reg_equiv_constant | |
731 | so they will be substituted by find_reloads. | |
732 | Record memory equivalents in reg_mem_equiv so they can | |
733 | be substituted eventually by altering the REG-rtx's. */ | |
734 | ||
ad85216e | 735 | reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx)); |
ad85216e KG |
736 | reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx)); |
737 | reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
738 | reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
f9e158c3 | 739 | reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int)); |
ad85216e | 740 | reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short)); |
4e135bdd | 741 | memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short)); |
03acd8f8 BS |
742 | pseudo_forbidden_regs |
743 | = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET)); | |
744 | pseudo_previous_regs | |
ad85216e | 745 | = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET)); |
32131a9c | 746 | |
03acd8f8 | 747 | CLEAR_HARD_REG_SET (bad_spill_regs_global); |
56f58d3a | 748 | |
32131a9c | 749 | /* Look for REG_EQUIV notes; record what each pseudo is equivalent to. |
56f58d3a RK |
750 | Also find all paradoxical subregs and find largest such for each pseudo. |
751 | On machines with small register classes, record hard registers that | |
05d10675 | 752 | are used for user variables. These can never be used for spills. |
570a98eb | 753 | Also look for a "constant" REG_SETJMP. This means that all |
b453cb0b | 754 | caller-saved registers must be marked live. */ |
32131a9c | 755 | |
2b49ee39 | 756 | num_eliminable_invariants = 0; |
32131a9c RK |
757 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
758 | { | |
759 | rtx set = single_set (insn); | |
760 | ||
3d17d93d AO |
761 | /* We may introduce USEs that we want to remove at the end, so |
762 | we'll mark them with QImode. Make sure there are no | |
763 | previously-marked insns left by say regmove. */ | |
764 | if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE | |
765 | && GET_MODE (insn) != VOIDmode) | |
766 | PUT_MODE (insn, VOIDmode); | |
767 | ||
19652adf ZW |
768 | if (GET_CODE (insn) == CALL_INSN |
769 | && find_reg_note (insn, REG_SETJMP, NULL)) | |
b453cb0b RK |
770 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
771 | if (! call_used_regs[i]) | |
772 | regs_ever_live[i] = 1; | |
773 | ||
32131a9c RK |
774 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG) |
775 | { | |
fb3821f7 | 776 | rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
a8efe40d RK |
777 | if (note |
778 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
2b49ee39 R |
779 | && (! function_invariant_p (XEXP (note, 0)) |
780 | || ! flag_pic | |
129c0899 HPN |
781 | /* A function invariant is often CONSTANT_P but may |
782 | include a register. We promise to only pass | |
783 | CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ | |
784 | || (CONSTANT_P (XEXP (note, 0)) | |
785 | && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))) | |
a8efe40d RK |
786 | #endif |
787 | ) | |
32131a9c RK |
788 | { |
789 | rtx x = XEXP (note, 0); | |
790 | i = REGNO (SET_DEST (set)); | |
791 | if (i > LAST_VIRTUAL_REGISTER) | |
792 | { | |
793 | if (GET_CODE (x) == MEM) | |
956d6950 | 794 | { |
cf728d61 HPN |
795 | /* Always unshare the equivalence, so we can |
796 | substitute into this insn without touching the | |
2ba84f36 | 797 | equivalence. */ |
cf728d61 | 798 | reg_equiv_memory_loc[i] = copy_rtx (x); |
956d6950 | 799 | } |
2b49ee39 | 800 | else if (function_invariant_p (x)) |
32131a9c | 801 | { |
2b49ee39 R |
802 | if (GET_CODE (x) == PLUS) |
803 | { | |
804 | /* This is PLUS of frame pointer and a constant, | |
805 | and might be shared. Unshare it. */ | |
806 | reg_equiv_constant[i] = copy_rtx (x); | |
807 | num_eliminable_invariants++; | |
808 | } | |
809 | else if (x == frame_pointer_rtx | |
810 | || x == arg_pointer_rtx) | |
811 | { | |
812 | reg_equiv_constant[i] = x; | |
813 | num_eliminable_invariants++; | |
814 | } | |
815 | else if (LEGITIMATE_CONSTANT_P (x)) | |
32131a9c RK |
816 | reg_equiv_constant[i] = x; |
817 | else | |
818 | reg_equiv_memory_loc[i] | |
d445b551 | 819 | = force_const_mem (GET_MODE (SET_DEST (set)), x); |
32131a9c RK |
820 | } |
821 | else | |
822 | continue; | |
823 | ||
824 | /* If this register is being made equivalent to a MEM | |
825 | and the MEM is not SET_SRC, the equivalencing insn | |
826 | is one with the MEM as a SET_DEST and it occurs later. | |
827 | So don't mark this insn now. */ | |
828 | if (GET_CODE (x) != MEM | |
829 | || rtx_equal_p (SET_SRC (set), x)) | |
135eb61c R |
830 | reg_equiv_init[i] |
831 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]); | |
32131a9c RK |
832 | } |
833 | } | |
834 | } | |
835 | ||
836 | /* If this insn is setting a MEM from a register equivalent to it, | |
837 | this is the equivalencing insn. */ | |
838 | else if (set && GET_CODE (SET_DEST (set)) == MEM | |
839 | && GET_CODE (SET_SRC (set)) == REG | |
840 | && reg_equiv_memory_loc[REGNO (SET_SRC (set))] | |
841 | && rtx_equal_p (SET_DEST (set), | |
842 | reg_equiv_memory_loc[REGNO (SET_SRC (set))])) | |
135eb61c R |
843 | reg_equiv_init[REGNO (SET_SRC (set))] |
844 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
845 | reg_equiv_init[REGNO (SET_SRC (set))]); | |
32131a9c | 846 | |
2c3c49de | 847 | if (INSN_P (insn)) |
32131a9c RK |
848 | scan_paradoxical_subregs (PATTERN (insn)); |
849 | } | |
850 | ||
09dd1133 | 851 | init_elim_table (); |
32131a9c RK |
852 | |
853 | num_labels = max_label_num () - get_first_label_num (); | |
854 | ||
855 | /* Allocate the tables used to store offset information at labels. */ | |
a68d4b75 BK |
856 | /* We used to use alloca here, but the size of what it would try to |
857 | allocate would occasionally cause it to exceed the stack limit and | |
858 | cause a core dump. */ | |
859 | real_known_ptr = xmalloc (num_labels); | |
860 | real_at_ptr | |
32131a9c | 861 | = (int (*)[NUM_ELIMINABLE_REGS]) |
a68d4b75 | 862 | xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int)); |
32131a9c | 863 | |
a68d4b75 BK |
864 | offsets_known_at = real_known_ptr - get_first_label_num (); |
865 | offsets_at | |
866 | = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ()); | |
32131a9c RK |
867 | |
868 | /* Alter each pseudo-reg rtx to contain its hard reg number. | |
869 | Assign stack slots to the pseudos that lack hard regs or equivalents. | |
870 | Do not touch virtual registers. */ | |
871 | ||
872 | for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) | |
873 | alter_reg (i, -1); | |
874 | ||
32131a9c RK |
875 | /* If we have some registers we think can be eliminated, scan all insns to |
876 | see if there is an insn that sets one of these registers to something | |
877 | other than itself plus a constant. If so, the register cannot be | |
878 | eliminated. Doing this scan here eliminates an extra pass through the | |
879 | main reload loop in the most common case where register elimination | |
880 | cannot be done. */ | |
881 | for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) | |
882 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN | |
883 | || GET_CODE (insn) == CALL_INSN) | |
84832317 | 884 | note_stores (PATTERN (insn), mark_not_eliminable, NULL); |
32131a9c | 885 | |
18a90182 BS |
886 | maybe_fix_stack_asms (); |
887 | ||
03acd8f8 BS |
888 | insns_need_reload = 0; |
889 | something_needs_elimination = 0; | |
05d10675 | 890 | |
4079cd63 JW |
891 | /* Initialize to -1, which means take the first spill register. */ |
892 | last_spill_reg = -1; | |
893 | ||
32131a9c | 894 | /* Spill any hard regs that we know we can't eliminate. */ |
03acd8f8 | 895 | CLEAR_HARD_REG_SET (used_spill_regs); |
32131a9c RK |
896 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
897 | if (! ep->can_eliminate) | |
e04ca094 | 898 | spill_hard_reg (ep->from, 1); |
9ff3516a RK |
899 | |
900 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
901 | if (frame_pointer_needed) | |
e04ca094 | 902 | spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1); |
9ff3516a | 903 | #endif |
e04ca094 | 904 | finish_spills (global); |
7609e720 | 905 | |
f1db3576 JL |
906 | /* From now on, we may need to generate moves differently. We may also |
907 | allow modifications of insns which cause them to not be recognized. | |
908 | Any such modifications will be cleaned up during reload itself. */ | |
b2f15f94 RK |
909 | reload_in_progress = 1; |
910 | ||
32131a9c RK |
911 | /* This loop scans the entire function each go-round |
912 | and repeats until one repetition spills no additional hard regs. */ | |
03acd8f8 | 913 | for (;;) |
32131a9c | 914 | { |
03acd8f8 BS |
915 | int something_changed; |
916 | int did_spill; | |
32131a9c | 917 | |
03acd8f8 | 918 | HOST_WIDE_INT starting_frame_size; |
32131a9c | 919 | |
665792eb | 920 | /* Round size of stack frame to stack_alignment_needed. This must be done |
7657bf2f JW |
921 | here because the stack size may be a part of the offset computation |
922 | for register elimination, and there might have been new stack slots | |
6d2f8887 | 923 | created in the last iteration of this loop. */ |
665792eb JH |
924 | if (cfun->stack_alignment_needed) |
925 | assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed); | |
7657bf2f JW |
926 | |
927 | starting_frame_size = get_frame_size (); | |
928 | ||
09dd1133 | 929 | set_initial_elim_offsets (); |
1f3b1e1a | 930 | set_initial_label_offsets (); |
03acd8f8 | 931 | |
32131a9c RK |
932 | /* For each pseudo register that has an equivalent location defined, |
933 | try to eliminate any eliminable registers (such as the frame pointer) | |
934 | assuming initial offsets for the replacement register, which | |
935 | is the normal case. | |
936 | ||
937 | If the resulting location is directly addressable, substitute | |
938 | the MEM we just got directly for the old REG. | |
939 | ||
940 | If it is not addressable but is a constant or the sum of a hard reg | |
941 | and constant, it is probably not addressable because the constant is | |
942 | out of range, in that case record the address; we will generate | |
943 | hairy code to compute the address in a register each time it is | |
6491dbbb RK |
944 | needed. Similarly if it is a hard register, but one that is not |
945 | valid as an address register. | |
32131a9c RK |
946 | |
947 | If the location is not addressable, but does not have one of the | |
948 | above forms, assign a stack slot. We have to do this to avoid the | |
949 | potential of producing lots of reloads if, e.g., a location involves | |
950 | a pseudo that didn't get a hard register and has an equivalent memory | |
951 | location that also involves a pseudo that didn't get a hard register. | |
952 | ||
953 | Perhaps at some point we will improve reload_when_needed handling | |
954 | so this problem goes away. But that's very hairy. */ | |
955 | ||
956 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
957 | if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) | |
958 | { | |
1914f5da | 959 | rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX); |
32131a9c RK |
960 | |
961 | if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]), | |
962 | XEXP (x, 0))) | |
963 | reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; | |
964 | else if (CONSTANT_P (XEXP (x, 0)) | |
6491dbbb RK |
965 | || (GET_CODE (XEXP (x, 0)) == REG |
966 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
32131a9c RK |
967 | || (GET_CODE (XEXP (x, 0)) == PLUS |
968 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
969 | && (REGNO (XEXP (XEXP (x, 0), 0)) | |
970 | < FIRST_PSEUDO_REGISTER) | |
971 | && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) | |
972 | reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; | |
973 | else | |
974 | { | |
975 | /* Make a new stack slot. Then indicate that something | |
a8fdc208 | 976 | changed so we go back and recompute offsets for |
32131a9c RK |
977 | eliminable registers because the allocation of memory |
978 | below might change some offset. reg_equiv_{mem,address} | |
979 | will be set up for this pseudo on the next pass around | |
980 | the loop. */ | |
981 | reg_equiv_memory_loc[i] = 0; | |
982 | reg_equiv_init[i] = 0; | |
983 | alter_reg (i, -1); | |
32131a9c RK |
984 | } |
985 | } | |
a8fdc208 | 986 | |
437a710d BS |
987 | if (caller_save_needed) |
988 | setup_save_areas (); | |
989 | ||
03acd8f8 | 990 | /* If we allocated another stack slot, redo elimination bookkeeping. */ |
437a710d | 991 | if (starting_frame_size != get_frame_size ()) |
32131a9c RK |
992 | continue; |
993 | ||
437a710d | 994 | if (caller_save_needed) |
a8efe40d | 995 | { |
437a710d BS |
996 | save_call_clobbered_regs (); |
997 | /* That might have allocated new insn_chain structures. */ | |
998 | reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); | |
a8efe40d RK |
999 | } |
1000 | ||
03acd8f8 BS |
1001 | calculate_needs_all_insns (global); |
1002 | ||
f5d8c9f4 | 1003 | CLEAR_REG_SET (&spilled_pseudos); |
03acd8f8 BS |
1004 | did_spill = 0; |
1005 | ||
1006 | something_changed = 0; | |
32131a9c | 1007 | |
0dadecf6 RK |
1008 | /* If we allocated any new memory locations, make another pass |
1009 | since it might have changed elimination offsets. */ | |
1010 | if (starting_frame_size != get_frame_size ()) | |
1011 | something_changed = 1; | |
1012 | ||
09dd1133 BS |
1013 | { |
1014 | HARD_REG_SET to_spill; | |
1015 | CLEAR_HARD_REG_SET (to_spill); | |
1016 | update_eliminables (&to_spill); | |
1017 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1018 | if (TEST_HARD_REG_BIT (to_spill, i)) | |
32131a9c | 1019 | { |
e04ca094 | 1020 | spill_hard_reg (i, 1); |
03acd8f8 | 1021 | did_spill = 1; |
8f5db3c1 JL |
1022 | |
1023 | /* Regardless of the state of spills, if we previously had | |
1024 | a register that we thought we could eliminate, but no can | |
1025 | not eliminate, we must run another pass. | |
1026 | ||
1027 | Consider pseudos which have an entry in reg_equiv_* which | |
1028 | reference an eliminable register. We must make another pass | |
1029 | to update reg_equiv_* so that we do not substitute in the | |
1030 | old value from when we thought the elimination could be | |
1031 | performed. */ | |
1032 | something_changed = 1; | |
32131a9c | 1033 | } |
09dd1133 | 1034 | } |
9ff3516a | 1035 | |
e04ca094 | 1036 | select_reload_regs (); |
e483bf9c BS |
1037 | if (failure) |
1038 | goto failed; | |
437a710d | 1039 | |
e483bf9c | 1040 | if (insns_need_reload != 0 || did_spill) |
e04ca094 | 1041 | something_changed |= finish_spills (global); |
7609e720 | 1042 | |
03acd8f8 BS |
1043 | if (! something_changed) |
1044 | break; | |
1045 | ||
1046 | if (caller_save_needed) | |
7609e720 | 1047 | delete_caller_save_insns (); |
f5d8c9f4 BS |
1048 | |
1049 | obstack_free (&reload_obstack, reload_firstobj); | |
32131a9c RK |
1050 | } |
1051 | ||
1052 | /* If global-alloc was run, notify it of any register eliminations we have | |
1053 | done. */ | |
1054 | if (global) | |
1055 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
1056 | if (ep->can_eliminate) | |
1057 | mark_elimination (ep->from, ep->to); | |
1058 | ||
32131a9c RK |
1059 | /* If a pseudo has no hard reg, delete the insns that made the equivalence. |
1060 | If that insn didn't set the register (i.e., it copied the register to | |
1061 | memory), just delete that insn instead of the equivalencing insn plus | |
1062 | anything now dead. If we call delete_dead_insn on that insn, we may | |
135eb61c | 1063 | delete the insn that actually sets the register if the register dies |
32131a9c RK |
1064 | there and that is incorrect. */ |
1065 | ||
1066 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
135eb61c R |
1067 | { |
1068 | if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0) | |
1069 | { | |
1070 | rtx list; | |
1071 | for (list = reg_equiv_init[i]; list; list = XEXP (list, 1)) | |
1072 | { | |
1073 | rtx equiv_insn = XEXP (list, 0); | |
1074 | if (GET_CODE (equiv_insn) == NOTE) | |
1075 | continue; | |
1076 | if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn))) | |
1077 | delete_dead_insn (equiv_insn); | |
1078 | else | |
1079 | { | |
1080 | PUT_CODE (equiv_insn, NOTE); | |
1081 | NOTE_SOURCE_FILE (equiv_insn) = 0; | |
1082 | NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; | |
1083 | } | |
1084 | } | |
1085 | } | |
1086 | } | |
32131a9c RK |
1087 | |
1088 | /* Use the reload registers where necessary | |
1089 | by generating move instructions to move the must-be-register | |
1090 | values into or out of the reload registers. */ | |
1091 | ||
03acd8f8 BS |
1092 | if (insns_need_reload != 0 || something_needs_elimination |
1093 | || something_needs_operands_changed) | |
c47f5ea5 | 1094 | { |
102870fb | 1095 | HOST_WIDE_INT old_frame_size = get_frame_size (); |
c47f5ea5 | 1096 | |
e04ca094 | 1097 | reload_as_needed (global); |
c47f5ea5 BS |
1098 | |
1099 | if (old_frame_size != get_frame_size ()) | |
1100 | abort (); | |
1101 | ||
1102 | if (num_eliminable) | |
1103 | verify_initial_elim_offsets (); | |
1104 | } | |
32131a9c | 1105 | |
2a1f8b6b | 1106 | /* If we were able to eliminate the frame pointer, show that it is no |
546b63fb | 1107 | longer live at the start of any basic block. If it ls live by |
2a1f8b6b RK |
1108 | virtue of being in a pseudo, that pseudo will be marked live |
1109 | and hence the frame pointer will be known to be live via that | |
1110 | pseudo. */ | |
1111 | ||
1112 | if (! frame_pointer_needed) | |
1113 | for (i = 0; i < n_basic_blocks; i++) | |
e881bb1b | 1114 | CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start, |
8e08106d | 1115 | HARD_FRAME_POINTER_REGNUM); |
2a1f8b6b | 1116 | |
5352b11a RS |
1117 | /* Come here (with failure set nonzero) if we can't get enough spill regs |
1118 | and we decide not to abort about it. */ | |
1119 | failed: | |
1120 | ||
f5d8c9f4 | 1121 | CLEAR_REG_SET (&spilled_pseudos); |
a3ec87a8 RS |
1122 | reload_in_progress = 0; |
1123 | ||
32131a9c RK |
1124 | /* Now eliminate all pseudo regs by modifying them into |
1125 | their equivalent memory references. | |
1126 | The REG-rtx's for the pseudos are modified in place, | |
1127 | so all insns that used to refer to them now refer to memory. | |
1128 | ||
1129 | For a reg that has a reg_equiv_address, all those insns | |
1130 | were changed by reloading so that no insns refer to it any longer; | |
1131 | but the DECL_RTL of a variable decl may refer to it, | |
1132 | and if so this causes the debugging info to mention the variable. */ | |
1133 | ||
1134 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1135 | { | |
1136 | rtx addr = 0; | |
9ec36da5 JL |
1137 | |
1138 | if (reg_equiv_mem[i]) | |
1139 | addr = XEXP (reg_equiv_mem[i], 0); | |
1140 | ||
32131a9c RK |
1141 | if (reg_equiv_address[i]) |
1142 | addr = reg_equiv_address[i]; | |
9ec36da5 | 1143 | |
32131a9c RK |
1144 | if (addr) |
1145 | { | |
1146 | if (reg_renumber[i] < 0) | |
1147 | { | |
1148 | rtx reg = regno_reg_rtx[i]; | |
173b24b9 | 1149 | |
ef178af3 | 1150 | PUT_CODE (reg, MEM); |
32131a9c RK |
1151 | XEXP (reg, 0) = addr; |
1152 | REG_USERVAR_P (reg) = 0; | |
173b24b9 RK |
1153 | if (reg_equiv_memory_loc[i]) |
1154 | MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]); | |
1155 | else | |
1156 | { | |
1157 | RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg) | |
1158 | = MEM_SCALAR_P (reg) = 0; | |
1159 | MEM_ATTRS (reg) = 0; | |
1160 | } | |
32131a9c RK |
1161 | } |
1162 | else if (reg_equiv_mem[i]) | |
1163 | XEXP (reg_equiv_mem[i], 0) = addr; | |
1164 | } | |
1165 | } | |
1166 | ||
2ae74651 JL |
1167 | /* We must set reload_completed now since the cleanup_subreg_operands call |
1168 | below will re-recognize each insn and reload may have generated insns | |
1169 | which are only valid during and after reload. */ | |
1170 | reload_completed = 1; | |
1171 | ||
bd695e1e RH |
1172 | /* Make a pass over all the insns and delete all USEs which we inserted |
1173 | only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED | |
1174 | notes. Delete all CLOBBER insns that don't refer to the return value | |
1175 | and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and | |
1176 | REG_LIBCALL notes since they are no longer useful or accurate. Strip | |
1177 | and regenerate REG_INC notes that may have been moved around. */ | |
32131a9c RK |
1178 | |
1179 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
2c3c49de | 1180 | if (INSN_P (insn)) |
32131a9c | 1181 | { |
6764d250 | 1182 | rtx *pnote; |
32131a9c | 1183 | |
f474c6f8 AO |
1184 | if (GET_CODE (insn) == CALL_INSN) |
1185 | replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn), | |
1186 | VOIDmode, | |
1187 | CALL_INSN_FUNCTION_USAGE (insn)); | |
1188 | ||
0304f787 | 1189 | if ((GET_CODE (PATTERN (insn)) == USE |
3d17d93d AO |
1190 | /* We mark with QImode USEs introduced by reload itself. */ |
1191 | && (GET_MODE (insn) == QImode | |
1192 | || find_reg_note (insn, REG_EQUAL, NULL_RTX))) | |
bd695e1e RH |
1193 | || (GET_CODE (PATTERN (insn)) == CLOBBER |
1194 | && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG | |
1195 | || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0))))) | |
b60a8416 | 1196 | { |
e5eac8ef | 1197 | delete_insn (insn); |
b60a8416 R |
1198 | continue; |
1199 | } | |
6764d250 BS |
1200 | |
1201 | pnote = ®_NOTES (insn); | |
1202 | while (*pnote != 0) | |
32131a9c | 1203 | { |
6764d250 | 1204 | if (REG_NOTE_KIND (*pnote) == REG_DEAD |
80599fd9 | 1205 | || REG_NOTE_KIND (*pnote) == REG_UNUSED |
2dfa9a87 | 1206 | || REG_NOTE_KIND (*pnote) == REG_INC |
80599fd9 NC |
1207 | || REG_NOTE_KIND (*pnote) == REG_RETVAL |
1208 | || REG_NOTE_KIND (*pnote) == REG_LIBCALL) | |
6764d250 BS |
1209 | *pnote = XEXP (*pnote, 1); |
1210 | else | |
1211 | pnote = &XEXP (*pnote, 1); | |
32131a9c | 1212 | } |
0304f787 | 1213 | |
2dfa9a87 MH |
1214 | #ifdef AUTO_INC_DEC |
1215 | add_auto_inc_notes (insn, PATTERN (insn)); | |
1216 | #endif | |
1217 | ||
0304f787 JL |
1218 | /* And simplify (subreg (reg)) if it appears as an operand. */ |
1219 | cleanup_subreg_operands (insn); | |
b60a8416 | 1220 | } |
32131a9c | 1221 | |
ab87f8c8 JL |
1222 | /* If we are doing stack checking, give a warning if this function's |
1223 | frame size is larger than we expect. */ | |
1224 | if (flag_stack_check && ! STACK_CHECK_BUILTIN) | |
1225 | { | |
1226 | HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; | |
05d10675 BS |
1227 | static int verbose_warned = 0; |
1228 | ||
ab87f8c8 JL |
1229 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1230 | if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i]) | |
1231 | size += UNITS_PER_WORD; | |
1232 | ||
1233 | if (size > STACK_CHECK_MAX_FRAME_SIZE) | |
05d10675 | 1234 | { |
ab87f8c8 JL |
1235 | warning ("frame size too large for reliable stack checking"); |
1236 | if (! verbose_warned) | |
1237 | { | |
1238 | warning ("try reducing the number of local variables"); | |
1239 | verbose_warned = 1; | |
1240 | } | |
1241 | } | |
1242 | } | |
1243 | ||
32131a9c | 1244 | /* Indicate that we no longer have known memory locations or constants. */ |
58d9f9d9 JL |
1245 | if (reg_equiv_constant) |
1246 | free (reg_equiv_constant); | |
32131a9c | 1247 | reg_equiv_constant = 0; |
58d9f9d9 JL |
1248 | if (reg_equiv_memory_loc) |
1249 | free (reg_equiv_memory_loc); | |
32131a9c | 1250 | reg_equiv_memory_loc = 0; |
5352b11a | 1251 | |
a68d4b75 BK |
1252 | if (real_known_ptr) |
1253 | free (real_known_ptr); | |
1254 | if (real_at_ptr) | |
1255 | free (real_at_ptr); | |
1256 | ||
56a65848 DB |
1257 | free (reg_equiv_mem); |
1258 | free (reg_equiv_init); | |
1259 | free (reg_equiv_address); | |
1260 | free (reg_max_ref_width); | |
03acd8f8 BS |
1261 | free (reg_old_renumber); |
1262 | free (pseudo_previous_regs); | |
1263 | free (pseudo_forbidden_regs); | |
56a65848 | 1264 | |
8b4f9969 JW |
1265 | CLEAR_HARD_REG_SET (used_spill_regs); |
1266 | for (i = 0; i < n_spills; i++) | |
1267 | SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]); | |
1268 | ||
7609e720 BS |
1269 | /* Free all the insn_chain structures at once. */ |
1270 | obstack_free (&reload_obstack, reload_startobj); | |
1271 | unused_insn_chains = 0; | |
f1330226 | 1272 | fixup_abnormal_edges (); |
7609e720 | 1273 | |
5352b11a | 1274 | return failure; |
32131a9c | 1275 | } |
1e5bd841 | 1276 | |
18a90182 BS |
1277 | /* Yet another special case. Unfortunately, reg-stack forces people to |
1278 | write incorrect clobbers in asm statements. These clobbers must not | |
1279 | cause the register to appear in bad_spill_regs, otherwise we'll call | |
1280 | fatal_insn later. We clear the corresponding regnos in the live | |
1281 | register sets to avoid this. | |
1282 | The whole thing is rather sick, I'm afraid. */ | |
efc9bd41 | 1283 | |
18a90182 BS |
1284 | static void |
1285 | maybe_fix_stack_asms () | |
1286 | { | |
1287 | #ifdef STACK_REGS | |
392dccb7 | 1288 | const char *constraints[MAX_RECOG_OPERANDS]; |
18a90182 BS |
1289 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
1290 | struct insn_chain *chain; | |
1291 | ||
1292 | for (chain = reload_insn_chain; chain != 0; chain = chain->next) | |
1293 | { | |
1294 | int i, noperands; | |
1295 | HARD_REG_SET clobbered, allowed; | |
1296 | rtx pat; | |
1297 | ||
2c3c49de | 1298 | if (! INSN_P (chain->insn) |
18a90182 BS |
1299 | || (noperands = asm_noperands (PATTERN (chain->insn))) < 0) |
1300 | continue; | |
1301 | pat = PATTERN (chain->insn); | |
1302 | if (GET_CODE (pat) != PARALLEL) | |
1303 | continue; | |
1304 | ||
1305 | CLEAR_HARD_REG_SET (clobbered); | |
1306 | CLEAR_HARD_REG_SET (allowed); | |
1307 | ||
1308 | /* First, make a mask of all stack regs that are clobbered. */ | |
1309 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
1310 | { | |
1311 | rtx t = XVECEXP (pat, 0, i); | |
1312 | if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0))) | |
1313 | SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0))); | |
1314 | } | |
1315 | ||
1316 | /* Get the operand values and constraints out of the insn. */ | |
1ccbefce | 1317 | decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc, |
18a90182 BS |
1318 | constraints, operand_mode); |
1319 | ||
1320 | /* For every operand, see what registers are allowed. */ | |
1321 | for (i = 0; i < noperands; i++) | |
1322 | { | |
6b9c6f4f | 1323 | const char *p = constraints[i]; |
18a90182 BS |
1324 | /* For every alternative, we compute the class of registers allowed |
1325 | for reloading in CLS, and merge its contents into the reg set | |
1326 | ALLOWED. */ | |
1327 | int cls = (int) NO_REGS; | |
1328 | ||
1329 | for (;;) | |
1330 | { | |
1331 | char c = *p++; | |
1332 | ||
1333 | if (c == '\0' || c == ',' || c == '#') | |
1334 | { | |
1335 | /* End of one alternative - mark the regs in the current | |
1336 | class, and reset the class. */ | |
1337 | IOR_HARD_REG_SET (allowed, reg_class_contents[cls]); | |
1338 | cls = NO_REGS; | |
1339 | if (c == '#') | |
1340 | do { | |
1341 | c = *p++; | |
1342 | } while (c != '\0' && c != ','); | |
1343 | if (c == '\0') | |
1344 | break; | |
1345 | continue; | |
1346 | } | |
1347 | ||
1348 | switch (c) | |
1349 | { | |
1350 | case '=': case '+': case '*': case '%': case '?': case '!': | |
1351 | case '0': case '1': case '2': case '3': case '4': case 'm': | |
1352 | case '<': case '>': case 'V': case 'o': case '&': case 'E': | |
1353 | case 'F': case 's': case 'i': case 'n': case 'X': case 'I': | |
1354 | case 'J': case 'K': case 'L': case 'M': case 'N': case 'O': | |
1355 | case 'P': | |
18a90182 BS |
1356 | break; |
1357 | ||
1358 | case 'p': | |
1359 | cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS]; | |
1360 | break; | |
1361 | ||
1362 | case 'g': | |
1363 | case 'r': | |
1364 | cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS]; | |
1365 | break; | |
1366 | ||
1367 | default: | |
1368 | cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)]; | |
05d10675 | 1369 | |
18a90182 BS |
1370 | } |
1371 | } | |
1372 | } | |
1373 | /* Those of the registers which are clobbered, but allowed by the | |
1374 | constraints, must be usable as reload registers. So clear them | |
1375 | out of the life information. */ | |
1376 | AND_HARD_REG_SET (allowed, clobbered); | |
1377 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1378 | if (TEST_HARD_REG_BIT (allowed, i)) | |
1379 | { | |
239a0f5b BS |
1380 | CLEAR_REGNO_REG_SET (&chain->live_throughout, i); |
1381 | CLEAR_REGNO_REG_SET (&chain->dead_or_set, i); | |
18a90182 BS |
1382 | } |
1383 | } | |
1384 | ||
1385 | #endif | |
1386 | } | |
03acd8f8 | 1387 | \f |
f5d8c9f4 BS |
1388 | /* Copy the global variables n_reloads and rld into the corresponding elts |
1389 | of CHAIN. */ | |
1390 | static void | |
1391 | copy_reloads (chain) | |
1392 | struct insn_chain *chain; | |
1393 | { | |
1394 | chain->n_reloads = n_reloads; | |
1395 | chain->rld | |
1396 | = (struct reload *) obstack_alloc (&reload_obstack, | |
1397 | n_reloads * sizeof (struct reload)); | |
1398 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); | |
1399 | reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0); | |
1400 | } | |
1401 | ||
03acd8f8 BS |
1402 | /* Walk the chain of insns, and determine for each whether it needs reloads |
1403 | and/or eliminations. Build the corresponding insns_need_reload list, and | |
1404 | set something_needs_elimination as appropriate. */ | |
1405 | static void | |
7609e720 | 1406 | calculate_needs_all_insns (global) |
1e5bd841 BS |
1407 | int global; |
1408 | { | |
7609e720 | 1409 | struct insn_chain **pprev_reload = &insns_need_reload; |
462561b7 | 1410 | struct insn_chain *chain, *next = 0; |
1e5bd841 | 1411 | |
03acd8f8 BS |
1412 | something_needs_elimination = 0; |
1413 | ||
f5d8c9f4 | 1414 | reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0); |
462561b7 | 1415 | for (chain = reload_insn_chain; chain != 0; chain = next) |
1e5bd841 | 1416 | { |
67e61fe7 | 1417 | rtx insn = chain->insn; |
03acd8f8 | 1418 | |
462561b7 JJ |
1419 | next = chain->next; |
1420 | ||
f5d8c9f4 BS |
1421 | /* Clear out the shortcuts. */ |
1422 | chain->n_reloads = 0; | |
67e61fe7 BS |
1423 | chain->need_elim = 0; |
1424 | chain->need_reload = 0; | |
1425 | chain->need_operand_change = 0; | |
1e5bd841 | 1426 | |
03acd8f8 BS |
1427 | /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might |
1428 | include REG_LABEL), we need to see what effects this has on the | |
1429 | known offsets at labels. */ | |
1e5bd841 BS |
1430 | |
1431 | if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN | |
2c3c49de | 1432 | || (INSN_P (insn) && REG_NOTES (insn) != 0)) |
1e5bd841 BS |
1433 | set_label_offsets (insn, insn, 0); |
1434 | ||
2c3c49de | 1435 | if (INSN_P (insn)) |
1e5bd841 BS |
1436 | { |
1437 | rtx old_body = PATTERN (insn); | |
1438 | int old_code = INSN_CODE (insn); | |
1439 | rtx old_notes = REG_NOTES (insn); | |
1440 | int did_elimination = 0; | |
cb2afeb3 | 1441 | int operands_changed = 0; |
2b49ee39 R |
1442 | rtx set = single_set (insn); |
1443 | ||
1444 | /* Skip insns that only set an equivalence. */ | |
1445 | if (set && GET_CODE (SET_DEST (set)) == REG | |
1446 | && reg_renumber[REGNO (SET_DEST (set))] < 0 | |
1447 | && reg_equiv_constant[REGNO (SET_DEST (set))]) | |
67e61fe7 | 1448 | continue; |
1e5bd841 | 1449 | |
1e5bd841 | 1450 | /* If needed, eliminate any eliminable registers. */ |
2b49ee39 | 1451 | if (num_eliminable || num_eliminable_invariants) |
1e5bd841 BS |
1452 | did_elimination = eliminate_regs_in_insn (insn, 0); |
1453 | ||
1454 | /* Analyze the instruction. */ | |
cb2afeb3 R |
1455 | operands_changed = find_reloads (insn, 0, spill_indirect_levels, |
1456 | global, spill_reg_order); | |
1457 | ||
1458 | /* If a no-op set needs more than one reload, this is likely | |
1459 | to be something that needs input address reloads. We | |
1460 | can't get rid of this cleanly later, and it is of no use | |
1461 | anyway, so discard it now. | |
1462 | We only do this when expensive_optimizations is enabled, | |
1463 | since this complements reload inheritance / output | |
1464 | reload deletion, and it can make debugging harder. */ | |
1465 | if (flag_expensive_optimizations && n_reloads > 1) | |
1466 | { | |
1467 | rtx set = single_set (insn); | |
1468 | if (set | |
1469 | && SET_SRC (set) == SET_DEST (set) | |
1470 | && GET_CODE (SET_SRC (set)) == REG | |
1471 | && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) | |
1472 | { | |
ca6c03ca | 1473 | delete_insn (insn); |
462561b7 JJ |
1474 | /* Delete it from the reload chain */ |
1475 | if (chain->prev) | |
1476 | chain->prev->next = next; | |
1477 | else | |
1478 | reload_insn_chain = next; | |
1479 | if (next) | |
1480 | next->prev = chain->prev; | |
1481 | chain->next = unused_insn_chains; | |
1482 | unused_insn_chains = chain; | |
cb2afeb3 R |
1483 | continue; |
1484 | } | |
1485 | } | |
1486 | if (num_eliminable) | |
1487 | update_eliminable_offsets (); | |
1e5bd841 BS |
1488 | |
1489 | /* Remember for later shortcuts which insns had any reloads or | |
7609e720 BS |
1490 | register eliminations. */ |
1491 | chain->need_elim = did_elimination; | |
03acd8f8 BS |
1492 | chain->need_reload = n_reloads > 0; |
1493 | chain->need_operand_change = operands_changed; | |
1e5bd841 BS |
1494 | |
1495 | /* Discard any register replacements done. */ | |
1496 | if (did_elimination) | |
1497 | { | |
f5d8c9f4 | 1498 | obstack_free (&reload_obstack, reload_insn_firstobj); |
1e5bd841 BS |
1499 | PATTERN (insn) = old_body; |
1500 | INSN_CODE (insn) = old_code; | |
1501 | REG_NOTES (insn) = old_notes; | |
1502 | something_needs_elimination = 1; | |
1503 | } | |
1504 | ||
cb2afeb3 R |
1505 | something_needs_operands_changed |= operands_changed; |
1506 | ||
437a710d | 1507 | if (n_reloads != 0) |
7609e720 | 1508 | { |
f5d8c9f4 | 1509 | copy_reloads (chain); |
7609e720 BS |
1510 | *pprev_reload = chain; |
1511 | pprev_reload = &chain->next_need_reload; | |
7609e720 | 1512 | } |
1e5bd841 | 1513 | } |
1e5bd841 | 1514 | } |
7609e720 | 1515 | *pprev_reload = 0; |
1e5bd841 | 1516 | } |
f5d8c9f4 BS |
1517 | \f |
1518 | /* Comparison function for qsort to decide which of two reloads | |
1519 | should be handled first. *P1 and *P2 are the reload numbers. */ | |
1e5bd841 | 1520 | |
f5d8c9f4 BS |
1521 | static int |
1522 | reload_reg_class_lower (r1p, r2p) | |
1523 | const PTR r1p; | |
1524 | const PTR r2p; | |
1e5bd841 | 1525 | { |
b3694847 SS |
1526 | int r1 = *(const short *) r1p, r2 = *(const short *) r2p; |
1527 | int t; | |
1e5bd841 | 1528 | |
f5d8c9f4 BS |
1529 | /* Consider required reloads before optional ones. */ |
1530 | t = rld[r1].optional - rld[r2].optional; | |
1531 | if (t != 0) | |
1532 | return t; | |
1e5bd841 | 1533 | |
f5d8c9f4 BS |
1534 | /* Count all solitary classes before non-solitary ones. */ |
1535 | t = ((reg_class_size[(int) rld[r2].class] == 1) | |
1536 | - (reg_class_size[(int) rld[r1].class] == 1)); | |
1537 | if (t != 0) | |
1538 | return t; | |
1e5bd841 | 1539 | |
f5d8c9f4 BS |
1540 | /* Aside from solitaires, consider all multi-reg groups first. */ |
1541 | t = rld[r2].nregs - rld[r1].nregs; | |
1542 | if (t != 0) | |
1543 | return t; | |
1e5bd841 | 1544 | |
f5d8c9f4 BS |
1545 | /* Consider reloads in order of increasing reg-class number. */ |
1546 | t = (int) rld[r1].class - (int) rld[r2].class; | |
1547 | if (t != 0) | |
1548 | return t; | |
1e5bd841 | 1549 | |
f5d8c9f4 BS |
1550 | /* If reloads are equally urgent, sort by reload number, |
1551 | so that the results of qsort leave nothing to chance. */ | |
1552 | return r1 - r2; | |
1553 | } | |
1554 | \f | |
1555 | /* The cost of spilling each hard reg. */ | |
1556 | static int spill_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1557 | |
f5d8c9f4 BS |
1558 | /* When spilling multiple hard registers, we use SPILL_COST for the first |
1559 | spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST | |
1560 | only the first hard reg for a multi-reg pseudo. */ | |
1561 | static int spill_add_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1562 | |
f5d8c9f4 | 1563 | /* Update the spill cost arrays, considering that pseudo REG is live. */ |
770ae6cc | 1564 | |
f5d8c9f4 BS |
1565 | static void |
1566 | count_pseudo (reg) | |
1567 | int reg; | |
1568 | { | |
b2aec5c0 | 1569 | int freq = REG_FREQ (reg); |
f5d8c9f4 BS |
1570 | int r = reg_renumber[reg]; |
1571 | int nregs; | |
1e5bd841 | 1572 | |
f5d8c9f4 BS |
1573 | if (REGNO_REG_SET_P (&pseudos_counted, reg) |
1574 | || REGNO_REG_SET_P (&spilled_pseudos, reg)) | |
1575 | return; | |
1e5bd841 | 1576 | |
f5d8c9f4 | 1577 | SET_REGNO_REG_SET (&pseudos_counted, reg); |
1e5bd841 | 1578 | |
f5d8c9f4 BS |
1579 | if (r < 0) |
1580 | abort (); | |
1d7254c5 | 1581 | |
b2aec5c0 | 1582 | spill_add_cost[r] += freq; |
1e5bd841 | 1583 | |
f5d8c9f4 BS |
1584 | nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); |
1585 | while (nregs-- > 0) | |
b2aec5c0 | 1586 | spill_cost[r + nregs] += freq; |
f5d8c9f4 | 1587 | } |
1e5bd841 | 1588 | |
f5d8c9f4 BS |
1589 | /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the |
1590 | contents of BAD_SPILL_REGS for the insn described by CHAIN. */ | |
efc9bd41 | 1591 | |
f5d8c9f4 BS |
1592 | static void |
1593 | order_regs_for_reload (chain) | |
1594 | struct insn_chain *chain; | |
1595 | { | |
fbd40359 | 1596 | int i; |
efc9bd41 RK |
1597 | HARD_REG_SET used_by_pseudos; |
1598 | HARD_REG_SET used_by_pseudos2; | |
1e5bd841 | 1599 | |
efc9bd41 | 1600 | COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set); |
1e5bd841 | 1601 | |
f5d8c9f4 BS |
1602 | memset (spill_cost, 0, sizeof spill_cost); |
1603 | memset (spill_add_cost, 0, sizeof spill_add_cost); | |
1e5bd841 | 1604 | |
f5d8c9f4 | 1605 | /* Count number of uses of each hard reg by pseudo regs allocated to it |
efc9bd41 RK |
1606 | and then order them by decreasing use. First exclude hard registers |
1607 | that are live in or across this insn. */ | |
1608 | ||
1609 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); | |
1610 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
1611 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos); | |
1612 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2); | |
1e5bd841 | 1613 | |
f5d8c9f4 BS |
1614 | /* Now find out which pseudos are allocated to it, and update |
1615 | hard_reg_n_uses. */ | |
1616 | CLEAR_REG_SET (&pseudos_counted); | |
1e5bd841 | 1617 | |
f5d8c9f4 | 1618 | EXECUTE_IF_SET_IN_REG_SET |
fbd40359 | 1619 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, |
f5d8c9f4 | 1620 | { |
fbd40359 | 1621 | count_pseudo (i); |
f5d8c9f4 BS |
1622 | }); |
1623 | EXECUTE_IF_SET_IN_REG_SET | |
fbd40359 | 1624 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, |
f5d8c9f4 | 1625 | { |
fbd40359 | 1626 | count_pseudo (i); |
f5d8c9f4 BS |
1627 | }); |
1628 | CLEAR_REG_SET (&pseudos_counted); | |
1e5bd841 | 1629 | } |
03acd8f8 | 1630 | \f |
f5d8c9f4 BS |
1631 | /* Vector of reload-numbers showing the order in which the reloads should |
1632 | be processed. */ | |
1633 | static short reload_order[MAX_RELOADS]; | |
1e5bd841 | 1634 | |
f5d8c9f4 BS |
1635 | /* This is used to keep track of the spill regs used in one insn. */ |
1636 | static HARD_REG_SET used_spill_regs_local; | |
03acd8f8 | 1637 | |
f5d8c9f4 BS |
1638 | /* We decided to spill hard register SPILLED, which has a size of |
1639 | SPILLED_NREGS. Determine how pseudo REG, which is live during the insn, | |
1640 | is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will | |
1641 | update SPILL_COST/SPILL_ADD_COST. */ | |
770ae6cc | 1642 | |
03acd8f8 | 1643 | static void |
f5d8c9f4 BS |
1644 | count_spilled_pseudo (spilled, spilled_nregs, reg) |
1645 | int spilled, spilled_nregs, reg; | |
1e5bd841 | 1646 | { |
f5d8c9f4 BS |
1647 | int r = reg_renumber[reg]; |
1648 | int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); | |
1e5bd841 | 1649 | |
f5d8c9f4 BS |
1650 | if (REGNO_REG_SET_P (&spilled_pseudos, reg) |
1651 | || spilled + spilled_nregs <= r || r + nregs <= spilled) | |
1652 | return; | |
1e5bd841 | 1653 | |
f5d8c9f4 | 1654 | SET_REGNO_REG_SET (&spilled_pseudos, reg); |
1e5bd841 | 1655 | |
b2aec5c0 | 1656 | spill_add_cost[r] -= REG_FREQ (reg); |
f5d8c9f4 | 1657 | while (nregs-- > 0) |
b2aec5c0 | 1658 | spill_cost[r + nregs] -= REG_FREQ (reg); |
1e5bd841 BS |
1659 | } |
1660 | ||
f5d8c9f4 | 1661 | /* Find reload register to use for reload number ORDER. */ |
03acd8f8 | 1662 | |
f5d8c9f4 | 1663 | static int |
e04ca094 | 1664 | find_reg (chain, order) |
03acd8f8 | 1665 | struct insn_chain *chain; |
f5d8c9f4 | 1666 | int order; |
1e5bd841 | 1667 | { |
f5d8c9f4 BS |
1668 | int rnum = reload_order[order]; |
1669 | struct reload *rl = rld + rnum; | |
1670 | int best_cost = INT_MAX; | |
1671 | int best_reg = -1; | |
770ae6cc RK |
1672 | unsigned int i, j; |
1673 | int k; | |
f5d8c9f4 BS |
1674 | HARD_REG_SET not_usable; |
1675 | HARD_REG_SET used_by_other_reload; | |
1e5bd841 | 1676 | |
f5d8c9f4 BS |
1677 | COPY_HARD_REG_SET (not_usable, bad_spill_regs); |
1678 | IOR_HARD_REG_SET (not_usable, bad_spill_regs_global); | |
1679 | IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]); | |
1680 | ||
1681 | CLEAR_HARD_REG_SET (used_by_other_reload); | |
770ae6cc | 1682 | for (k = 0; k < order; k++) |
1e5bd841 | 1683 | { |
770ae6cc RK |
1684 | int other = reload_order[k]; |
1685 | ||
f5d8c9f4 BS |
1686 | if (rld[other].regno >= 0 && reloads_conflict (other, rnum)) |
1687 | for (j = 0; j < rld[other].nregs; j++) | |
1688 | SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j); | |
1689 | } | |
1e5bd841 | 1690 | |
f5d8c9f4 BS |
1691 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1692 | { | |
770ae6cc RK |
1693 | unsigned int regno = i; |
1694 | ||
f5d8c9f4 BS |
1695 | if (! TEST_HARD_REG_BIT (not_usable, regno) |
1696 | && ! TEST_HARD_REG_BIT (used_by_other_reload, regno) | |
1697 | && HARD_REGNO_MODE_OK (regno, rl->mode)) | |
1e5bd841 | 1698 | { |
f5d8c9f4 BS |
1699 | int this_cost = spill_cost[regno]; |
1700 | int ok = 1; | |
770ae6cc | 1701 | unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode); |
1e5bd841 | 1702 | |
f5d8c9f4 BS |
1703 | for (j = 1; j < this_nregs; j++) |
1704 | { | |
1705 | this_cost += spill_add_cost[regno + j]; | |
1706 | if ((TEST_HARD_REG_BIT (not_usable, regno + j)) | |
1707 | || TEST_HARD_REG_BIT (used_by_other_reload, regno + j)) | |
1708 | ok = 0; | |
1709 | } | |
1710 | if (! ok) | |
1711 | continue; | |
1712 | if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno) | |
1713 | this_cost--; | |
1714 | if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno) | |
1715 | this_cost--; | |
1716 | if (this_cost < best_cost | |
1717 | /* Among registers with equal cost, prefer caller-saved ones, or | |
1718 | use REG_ALLOC_ORDER if it is defined. */ | |
1719 | || (this_cost == best_cost | |
1720 | #ifdef REG_ALLOC_ORDER | |
1721 | && (inv_reg_alloc_order[regno] | |
1722 | < inv_reg_alloc_order[best_reg]) | |
1723 | #else | |
1724 | && call_used_regs[regno] | |
1725 | && ! call_used_regs[best_reg] | |
1726 | #endif | |
1727 | )) | |
1728 | { | |
1729 | best_reg = regno; | |
1730 | best_cost = this_cost; | |
1e5bd841 BS |
1731 | } |
1732 | } | |
1733 | } | |
f5d8c9f4 BS |
1734 | if (best_reg == -1) |
1735 | return 0; | |
770ae6cc | 1736 | |
e04ca094 JL |
1737 | if (rtl_dump_file) |
1738 | fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum); | |
770ae6cc | 1739 | |
f5d8c9f4 BS |
1740 | rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode); |
1741 | rl->regno = best_reg; | |
1e5bd841 | 1742 | |
f5d8c9f4 | 1743 | EXECUTE_IF_SET_IN_REG_SET |
239a0f5b | 1744 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, |
f5d8c9f4 BS |
1745 | { |
1746 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1747 | }); | |
770ae6cc | 1748 | |
f5d8c9f4 | 1749 | EXECUTE_IF_SET_IN_REG_SET |
239a0f5b | 1750 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, |
f5d8c9f4 BS |
1751 | { |
1752 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1753 | }); | |
03acd8f8 | 1754 | |
f5d8c9f4 BS |
1755 | for (i = 0; i < rl->nregs; i++) |
1756 | { | |
1757 | if (spill_cost[best_reg + i] != 0 | |
1758 | || spill_add_cost[best_reg + i] != 0) | |
1759 | abort (); | |
1760 | SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i); | |
1761 | } | |
1762 | return 1; | |
03acd8f8 BS |
1763 | } |
1764 | ||
1765 | /* Find more reload regs to satisfy the remaining need of an insn, which | |
1766 | is given by CHAIN. | |
1e5bd841 BS |
1767 | Do it by ascending class number, since otherwise a reg |
1768 | might be spilled for a big class and might fail to count | |
f5d8c9f4 | 1769 | for a smaller class even though it belongs to that class. */ |
1e5bd841 | 1770 | |
03acd8f8 | 1771 | static void |
e04ca094 | 1772 | find_reload_regs (chain) |
03acd8f8 | 1773 | struct insn_chain *chain; |
1e5bd841 | 1774 | { |
f5d8c9f4 | 1775 | int i; |
1e5bd841 | 1776 | |
f5d8c9f4 BS |
1777 | /* In order to be certain of getting the registers we need, |
1778 | we must sort the reloads into order of increasing register class. | |
1779 | Then our grabbing of reload registers will parallel the process | |
1780 | that provided the reload registers. */ | |
1781 | for (i = 0; i < chain->n_reloads; i++) | |
1e5bd841 | 1782 | { |
f5d8c9f4 BS |
1783 | /* Show whether this reload already has a hard reg. */ |
1784 | if (chain->rld[i].reg_rtx) | |
1e5bd841 | 1785 | { |
f5d8c9f4 BS |
1786 | int regno = REGNO (chain->rld[i].reg_rtx); |
1787 | chain->rld[i].regno = regno; | |
770ae6cc RK |
1788 | chain->rld[i].nregs |
1789 | = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx)); | |
1e5bd841 | 1790 | } |
f5d8c9f4 BS |
1791 | else |
1792 | chain->rld[i].regno = -1; | |
1793 | reload_order[i] = i; | |
1794 | } | |
1e5bd841 | 1795 | |
f5d8c9f4 BS |
1796 | n_reloads = chain->n_reloads; |
1797 | memcpy (rld, chain->rld, n_reloads * sizeof (struct reload)); | |
1e5bd841 | 1798 | |
f5d8c9f4 | 1799 | CLEAR_HARD_REG_SET (used_spill_regs_local); |
03acd8f8 | 1800 | |
e04ca094 JL |
1801 | if (rtl_dump_file) |
1802 | fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn)); | |
1e5bd841 | 1803 | |
f5d8c9f4 | 1804 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); |
1e5bd841 | 1805 | |
f5d8c9f4 | 1806 | /* Compute the order of preference for hard registers to spill. */ |
1e5bd841 | 1807 | |
f5d8c9f4 | 1808 | order_regs_for_reload (chain); |
1e5bd841 | 1809 | |
f5d8c9f4 BS |
1810 | for (i = 0; i < n_reloads; i++) |
1811 | { | |
1812 | int r = reload_order[i]; | |
1e5bd841 | 1813 | |
f5d8c9f4 BS |
1814 | /* Ignore reloads that got marked inoperative. */ |
1815 | if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p) | |
1816 | && ! rld[r].optional | |
1817 | && rld[r].regno == -1) | |
e04ca094 | 1818 | if (! find_reg (chain, i)) |
f5d8c9f4 | 1819 | { |
ecf3151a | 1820 | spill_failure (chain->insn, rld[r].class); |
f5d8c9f4 | 1821 | failure = 1; |
03acd8f8 | 1822 | return; |
f5d8c9f4 | 1823 | } |
1e5bd841 | 1824 | } |
05d10675 | 1825 | |
f5d8c9f4 BS |
1826 | COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local); |
1827 | IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local); | |
03acd8f8 | 1828 | |
f5d8c9f4 | 1829 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); |
1e5bd841 BS |
1830 | } |
1831 | ||
f5d8c9f4 | 1832 | static void |
e04ca094 | 1833 | select_reload_regs () |
09dd1133 | 1834 | { |
f5d8c9f4 | 1835 | struct insn_chain *chain; |
09dd1133 | 1836 | |
f5d8c9f4 BS |
1837 | /* Try to satisfy the needs for each insn. */ |
1838 | for (chain = insns_need_reload; chain != 0; | |
1839 | chain = chain->next_need_reload) | |
e04ca094 | 1840 | find_reload_regs (chain); |
09dd1133 | 1841 | } |
32131a9c | 1842 | \f |
437a710d BS |
1843 | /* Delete all insns that were inserted by emit_caller_save_insns during |
1844 | this iteration. */ | |
1845 | static void | |
7609e720 | 1846 | delete_caller_save_insns () |
437a710d | 1847 | { |
7609e720 | 1848 | struct insn_chain *c = reload_insn_chain; |
437a710d | 1849 | |
7609e720 | 1850 | while (c != 0) |
437a710d | 1851 | { |
7609e720 | 1852 | while (c != 0 && c->is_caller_save_insn) |
437a710d | 1853 | { |
7609e720 BS |
1854 | struct insn_chain *next = c->next; |
1855 | rtx insn = c->insn; | |
1856 | ||
7609e720 BS |
1857 | if (c == reload_insn_chain) |
1858 | reload_insn_chain = next; | |
ca6c03ca | 1859 | delete_insn (insn); |
7609e720 BS |
1860 | |
1861 | if (next) | |
1862 | next->prev = c->prev; | |
1863 | if (c->prev) | |
1864 | c->prev->next = next; | |
1865 | c->next = unused_insn_chains; | |
1866 | unused_insn_chains = c; | |
1867 | c = next; | |
437a710d | 1868 | } |
7609e720 BS |
1869 | if (c != 0) |
1870 | c = c->next; | |
437a710d BS |
1871 | } |
1872 | } | |
1873 | \f | |
5352b11a RS |
1874 | /* Handle the failure to find a register to spill. |
1875 | INSN should be one of the insns which needed this particular spill reg. */ | |
1876 | ||
1877 | static void | |
ecf3151a | 1878 | spill_failure (insn, class) |
5352b11a | 1879 | rtx insn; |
ecf3151a | 1880 | enum reg_class class; |
5352b11a | 1881 | { |
ecf3151a | 1882 | static const char *const reg_class_names[] = REG_CLASS_NAMES; |
5352b11a | 1883 | if (asm_noperands (PATTERN (insn)) >= 0) |
ecf3151a BS |
1884 | error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.", |
1885 | reg_class_names[class]); | |
5352b11a | 1886 | else |
ecf3151a BS |
1887 | { |
1888 | error ("Unable to find a register to spill in class `%s'.", | |
1889 | reg_class_names[class]); | |
1890 | fatal_insn ("This is the insn:", insn); | |
1891 | } | |
5352b11a | 1892 | } |
32131a9c RK |
1893 | \f |
1894 | /* Delete an unneeded INSN and any previous insns who sole purpose is loading | |
1895 | data that is dead in INSN. */ | |
1896 | ||
1897 | static void | |
1898 | delete_dead_insn (insn) | |
1899 | rtx insn; | |
1900 | { | |
1901 | rtx prev = prev_real_insn (insn); | |
1902 | rtx prev_dest; | |
1903 | ||
1904 | /* If the previous insn sets a register that dies in our insn, delete it | |
1905 | too. */ | |
1906 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
1907 | && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG) | |
1908 | && reg_mentioned_p (prev_dest, PATTERN (insn)) | |
b294ca38 R |
1909 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) |
1910 | && ! side_effects_p (SET_SRC (PATTERN (prev)))) | |
32131a9c RK |
1911 | delete_dead_insn (prev); |
1912 | ||
1913 | PUT_CODE (insn, NOTE); | |
1914 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
1915 | NOTE_SOURCE_FILE (insn) = 0; | |
1916 | } | |
1917 | ||
1918 | /* Modify the home of pseudo-reg I. | |
1919 | The new home is present in reg_renumber[I]. | |
1920 | ||
1921 | FROM_REG may be the hard reg that the pseudo-reg is being spilled from; | |
1922 | or it may be -1, meaning there is none or it is not relevant. | |
1923 | This is used so that all pseudos spilled from a given hard reg | |
1924 | can share one stack slot. */ | |
1925 | ||
1926 | static void | |
1927 | alter_reg (i, from_reg) | |
b3694847 | 1928 | int i; |
32131a9c RK |
1929 | int from_reg; |
1930 | { | |
1931 | /* When outputting an inline function, this can happen | |
1932 | for a reg that isn't actually used. */ | |
1933 | if (regno_reg_rtx[i] == 0) | |
1934 | return; | |
1935 | ||
1936 | /* If the reg got changed to a MEM at rtl-generation time, | |
1937 | ignore it. */ | |
1938 | if (GET_CODE (regno_reg_rtx[i]) != REG) | |
1939 | return; | |
1940 | ||
1941 | /* Modify the reg-rtx to contain the new hard reg | |
1942 | number or else to contain its pseudo reg number. */ | |
1943 | REGNO (regno_reg_rtx[i]) | |
1944 | = reg_renumber[i] >= 0 ? reg_renumber[i] : i; | |
1945 | ||
1946 | /* If we have a pseudo that is needed but has no hard reg or equivalent, | |
1947 | allocate a stack slot for it. */ | |
1948 | ||
1949 | if (reg_renumber[i] < 0 | |
b1f21e0a | 1950 | && REG_N_REFS (i) > 0 |
32131a9c RK |
1951 | && reg_equiv_constant[i] == 0 |
1952 | && reg_equiv_memory_loc[i] == 0) | |
1953 | { | |
b3694847 | 1954 | rtx x; |
770ae6cc RK |
1955 | unsigned int inherent_size = PSEUDO_REGNO_BYTES (i); |
1956 | unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]); | |
32131a9c RK |
1957 | int adjust = 0; |
1958 | ||
1959 | /* Each pseudo reg has an inherent size which comes from its own mode, | |
1960 | and a total size which provides room for paradoxical subregs | |
1961 | which refer to the pseudo reg in wider modes. | |
1962 | ||
1963 | We can use a slot already allocated if it provides both | |
1964 | enough inherent space and enough total space. | |
1965 | Otherwise, we allocate a new slot, making sure that it has no less | |
1966 | inherent space, and no less total space, then the previous slot. */ | |
1967 | if (from_reg == -1) | |
1968 | { | |
1969 | /* No known place to spill from => no slot to reuse. */ | |
cabcf079 ILT |
1970 | x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, |
1971 | inherent_size == total_size ? 0 : -1); | |
f76b9db2 | 1972 | if (BYTES_BIG_ENDIAN) |
02db8dd0 RK |
1973 | /* Cancel the big-endian correction done in assign_stack_local. |
1974 | Get the address of the beginning of the slot. | |
1975 | This is so we can do a big-endian correction unconditionally | |
1976 | below. */ | |
1977 | adjust = inherent_size - total_size; | |
1978 | ||
1979 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]); | |
3bdf5ad1 RK |
1980 | |
1981 | /* Nothing can alias this slot except this pseudo. */ | |
ba4828e0 | 1982 | set_mem_alias_set (x, new_alias_set ()); |
32131a9c | 1983 | } |
3bdf5ad1 | 1984 | |
32131a9c RK |
1985 | /* Reuse a stack slot if possible. */ |
1986 | else if (spill_stack_slot[from_reg] != 0 | |
1987 | && spill_stack_slot_width[from_reg] >= total_size | |
1988 | && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
1989 | >= inherent_size)) | |
1990 | x = spill_stack_slot[from_reg]; | |
3bdf5ad1 | 1991 | |
32131a9c RK |
1992 | /* Allocate a bigger slot. */ |
1993 | else | |
1994 | { | |
1995 | /* Compute maximum size needed, both for inherent size | |
1996 | and for total size. */ | |
1997 | enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); | |
4f2d3674 | 1998 | rtx stack_slot; |
3bdf5ad1 | 1999 | |
32131a9c RK |
2000 | if (spill_stack_slot[from_reg]) |
2001 | { | |
2002 | if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
2003 | > inherent_size) | |
2004 | mode = GET_MODE (spill_stack_slot[from_reg]); | |
2005 | if (spill_stack_slot_width[from_reg] > total_size) | |
2006 | total_size = spill_stack_slot_width[from_reg]; | |
2007 | } | |
3bdf5ad1 | 2008 | |
32131a9c | 2009 | /* Make a slot with that size. */ |
cabcf079 ILT |
2010 | x = assign_stack_local (mode, total_size, |
2011 | inherent_size == total_size ? 0 : -1); | |
4f2d3674 | 2012 | stack_slot = x; |
3bdf5ad1 RK |
2013 | |
2014 | /* All pseudos mapped to this slot can alias each other. */ | |
2015 | if (spill_stack_slot[from_reg]) | |
ba4828e0 | 2016 | set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg])); |
3bdf5ad1 | 2017 | else |
ba4828e0 | 2018 | set_mem_alias_set (x, new_alias_set ()); |
3bdf5ad1 | 2019 | |
f76b9db2 ILT |
2020 | if (BYTES_BIG_ENDIAN) |
2021 | { | |
2022 | /* Cancel the big-endian correction done in assign_stack_local. | |
2023 | Get the address of the beginning of the slot. | |
2024 | This is so we can do a big-endian correction unconditionally | |
2025 | below. */ | |
2026 | adjust = GET_MODE_SIZE (mode) - total_size; | |
4f2d3674 | 2027 | if (adjust) |
8ac61af7 RK |
2028 | stack_slot |
2029 | = adjust_address_nv (x, mode_for_size (total_size | |
38a448ca RH |
2030 | * BITS_PER_UNIT, |
2031 | MODE_INT, 1), | |
8ac61af7 | 2032 | adjust); |
f76b9db2 | 2033 | } |
3bdf5ad1 | 2034 | |
4f2d3674 | 2035 | spill_stack_slot[from_reg] = stack_slot; |
32131a9c RK |
2036 | spill_stack_slot_width[from_reg] = total_size; |
2037 | } | |
2038 | ||
32131a9c RK |
2039 | /* On a big endian machine, the "address" of the slot |
2040 | is the address of the low part that fits its inherent mode. */ | |
f76b9db2 | 2041 | if (BYTES_BIG_ENDIAN && inherent_size < total_size) |
32131a9c | 2042 | adjust += (total_size - inherent_size); |
32131a9c RK |
2043 | |
2044 | /* If we have any adjustment to make, or if the stack slot is the | |
2045 | wrong mode, make a new stack slot. */ | |
2046 | if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i])) | |
f1ec5147 | 2047 | x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust); |
32131a9c | 2048 | |
6d2f8887 | 2049 | /* Save the stack slot for later. */ |
32131a9c RK |
2050 | reg_equiv_memory_loc[i] = x; |
2051 | } | |
2052 | } | |
2053 | ||
2054 | /* Mark the slots in regs_ever_live for the hard regs | |
2055 | used by pseudo-reg number REGNO. */ | |
2056 | ||
2057 | void | |
2058 | mark_home_live (regno) | |
2059 | int regno; | |
2060 | { | |
b3694847 | 2061 | int i, lim; |
770ae6cc | 2062 | |
32131a9c RK |
2063 | i = reg_renumber[regno]; |
2064 | if (i < 0) | |
2065 | return; | |
2066 | lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno)); | |
2067 | while (i < lim) | |
2068 | regs_ever_live[i++] = 1; | |
2069 | } | |
2070 | \f | |
2071 | /* This function handles the tracking of elimination offsets around branches. | |
2072 | ||
2073 | X is a piece of RTL being scanned. | |
2074 | ||
2075 | INSN is the insn that it came from, if any. | |
2076 | ||
2077 | INITIAL_P is non-zero if we are to set the offset to be the initial | |
2078 | offset and zero if we are setting the offset of the label to be the | |
2079 | current offset. */ | |
2080 | ||
2081 | static void | |
2082 | set_label_offsets (x, insn, initial_p) | |
2083 | rtx x; | |
2084 | rtx insn; | |
2085 | int initial_p; | |
2086 | { | |
2087 | enum rtx_code code = GET_CODE (x); | |
2088 | rtx tem; | |
e51712db | 2089 | unsigned int i; |
32131a9c RK |
2090 | struct elim_table *p; |
2091 | ||
2092 | switch (code) | |
2093 | { | |
2094 | case LABEL_REF: | |
8be386d9 RS |
2095 | if (LABEL_REF_NONLOCAL_P (x)) |
2096 | return; | |
2097 | ||
32131a9c RK |
2098 | x = XEXP (x, 0); |
2099 | ||
0f41302f | 2100 | /* ... fall through ... */ |
32131a9c RK |
2101 | |
2102 | case CODE_LABEL: | |
2103 | /* If we know nothing about this label, set the desired offsets. Note | |
2104 | that this sets the offset at a label to be the offset before a label | |
2105 | if we don't know anything about the label. This is not correct for | |
2106 | the label after a BARRIER, but is the best guess we can make. If | |
2107 | we guessed wrong, we will suppress an elimination that might have | |
2108 | been possible had we been able to guess correctly. */ | |
2109 | ||
2110 | if (! offsets_known_at[CODE_LABEL_NUMBER (x)]) | |
2111 | { | |
2112 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
2113 | offsets_at[CODE_LABEL_NUMBER (x)][i] | |
2114 | = (initial_p ? reg_eliminate[i].initial_offset | |
2115 | : reg_eliminate[i].offset); | |
2116 | offsets_known_at[CODE_LABEL_NUMBER (x)] = 1; | |
2117 | } | |
2118 | ||
2119 | /* Otherwise, if this is the definition of a label and it is | |
d45cf215 | 2120 | preceded by a BARRIER, set our offsets to the known offset of |
32131a9c RK |
2121 | that label. */ |
2122 | ||
2123 | else if (x == insn | |
2124 | && (tem = prev_nonnote_insn (insn)) != 0 | |
2125 | && GET_CODE (tem) == BARRIER) | |
1f3b1e1a | 2126 | set_offsets_for_label (insn); |
32131a9c RK |
2127 | else |
2128 | /* If neither of the above cases is true, compare each offset | |
2129 | with those previously recorded and suppress any eliminations | |
2130 | where the offsets disagree. */ | |
a8fdc208 | 2131 | |
32131a9c RK |
2132 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) |
2133 | if (offsets_at[CODE_LABEL_NUMBER (x)][i] | |
2134 | != (initial_p ? reg_eliminate[i].initial_offset | |
2135 | : reg_eliminate[i].offset)) | |
2136 | reg_eliminate[i].can_eliminate = 0; | |
2137 | ||
2138 | return; | |
2139 | ||
2140 | case JUMP_INSN: | |
2141 | set_label_offsets (PATTERN (insn), insn, initial_p); | |
2142 | ||
0f41302f | 2143 | /* ... fall through ... */ |
32131a9c RK |
2144 | |
2145 | case INSN: | |
2146 | case CALL_INSN: | |
2147 | /* Any labels mentioned in REG_LABEL notes can be branched to indirectly | |
2148 | and hence must have all eliminations at their initial offsets. */ | |
2149 | for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) | |
2150 | if (REG_NOTE_KIND (tem) == REG_LABEL) | |
2151 | set_label_offsets (XEXP (tem, 0), insn, 1); | |
2152 | return; | |
2153 | ||
0c0ba09c | 2154 | case PARALLEL: |
32131a9c RK |
2155 | case ADDR_VEC: |
2156 | case ADDR_DIFF_VEC: | |
0c0ba09c JJ |
2157 | /* Each of the labels in the parallel or address vector must be |
2158 | at their initial offsets. We want the first field for PARALLEL | |
2159 | and ADDR_VEC and the second field for ADDR_DIFF_VEC. */ | |
32131a9c | 2160 | |
e51712db | 2161 | for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++) |
32131a9c RK |
2162 | set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), |
2163 | insn, initial_p); | |
2164 | return; | |
2165 | ||
2166 | case SET: | |
2167 | /* We only care about setting PC. If the source is not RETURN, | |
2168 | IF_THEN_ELSE, or a label, disable any eliminations not at | |
2169 | their initial offsets. Similarly if any arm of the IF_THEN_ELSE | |
2170 | isn't one of those possibilities. For branches to a label, | |
2171 | call ourselves recursively. | |
2172 | ||
2173 | Note that this can disable elimination unnecessarily when we have | |
2174 | a non-local goto since it will look like a non-constant jump to | |
2175 | someplace in the current function. This isn't a significant | |
2176 | problem since such jumps will normally be when all elimination | |
2177 | pairs are back to their initial offsets. */ | |
2178 | ||
2179 | if (SET_DEST (x) != pc_rtx) | |
2180 | return; | |
2181 | ||
2182 | switch (GET_CODE (SET_SRC (x))) | |
2183 | { | |
2184 | case PC: | |
2185 | case RETURN: | |
2186 | return; | |
2187 | ||
2188 | case LABEL_REF: | |
2189 | set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p); | |
2190 | return; | |
2191 | ||
2192 | case IF_THEN_ELSE: | |
2193 | tem = XEXP (SET_SRC (x), 1); | |
2194 | if (GET_CODE (tem) == LABEL_REF) | |
2195 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2196 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2197 | break; | |
2198 | ||
2199 | tem = XEXP (SET_SRC (x), 2); | |
2200 | if (GET_CODE (tem) == LABEL_REF) | |
2201 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2202 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2203 | break; | |
2204 | return; | |
e9a25f70 JL |
2205 | |
2206 | default: | |
2207 | break; | |
32131a9c RK |
2208 | } |
2209 | ||
2210 | /* If we reach here, all eliminations must be at their initial | |
2211 | offset because we are doing a jump to a variable address. */ | |
2212 | for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) | |
2213 | if (p->offset != p->initial_offset) | |
2214 | p->can_eliminate = 0; | |
e9a25f70 | 2215 | break; |
05d10675 | 2216 | |
e9a25f70 JL |
2217 | default: |
2218 | break; | |
32131a9c RK |
2219 | } |
2220 | } | |
2221 | \f | |
a8fdc208 | 2222 | /* Scan X and replace any eliminable registers (such as fp) with a |
32131a9c RK |
2223 | replacement (such as sp), plus an offset. |
2224 | ||
2225 | MEM_MODE is the mode of an enclosing MEM. We need this to know how | |
2226 | much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a | |
2227 | MEM, we are allowed to replace a sum of a register and the constant zero | |
2228 | with the register, which we cannot do outside a MEM. In addition, we need | |
2229 | to record the fact that a register is referenced outside a MEM. | |
2230 | ||
ff32812a | 2231 | If INSN is an insn, it is the insn containing X. If we replace a REG |
32131a9c RK |
2232 | in a SET_DEST with an equivalent MEM and INSN is non-zero, write a |
2233 | CLOBBER of the pseudo after INSN so find_equiv_regs will know that | |
38e01259 | 2234 | the REG is being modified. |
32131a9c | 2235 | |
ff32812a RS |
2236 | Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST). |
2237 | That's used when we eliminate in expressions stored in notes. | |
2238 | This means, do not set ref_outside_mem even if the reference | |
2239 | is outside of MEMs. | |
2240 | ||
32131a9c RK |
2241 | REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had |
2242 | replacements done assuming all offsets are at their initial values. If | |
2243 | they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we | |
2244 | encounter, return the actual location so that find_reloads will do | |
2245 | the proper thing. */ | |
2246 | ||
2247 | rtx | |
1914f5da | 2248 | eliminate_regs (x, mem_mode, insn) |
32131a9c RK |
2249 | rtx x; |
2250 | enum machine_mode mem_mode; | |
2251 | rtx insn; | |
2252 | { | |
2253 | enum rtx_code code = GET_CODE (x); | |
2254 | struct elim_table *ep; | |
2255 | int regno; | |
2256 | rtx new; | |
2257 | int i, j; | |
6f7d635c | 2258 | const char *fmt; |
32131a9c RK |
2259 | int copied = 0; |
2260 | ||
d6633f01 NS |
2261 | if (! current_function_decl) |
2262 | return x; | |
9969bb2c | 2263 | |
32131a9c RK |
2264 | switch (code) |
2265 | { | |
2266 | case CONST_INT: | |
2267 | case CONST_DOUBLE: | |
2268 | case CONST: | |
2269 | case SYMBOL_REF: | |
2270 | case CODE_LABEL: | |
2271 | case PC: | |
2272 | case CC0: | |
2273 | case ASM_INPUT: | |
2274 | case ADDR_VEC: | |
2275 | case ADDR_DIFF_VEC: | |
2276 | case RETURN: | |
2277 | return x; | |
2278 | ||
e9a25f70 JL |
2279 | case ADDRESSOF: |
2280 | /* This is only for the benefit of the debugging backends, which call | |
2281 | eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are | |
2282 | removed after CSE. */ | |
1914f5da | 2283 | new = eliminate_regs (XEXP (x, 0), 0, insn); |
e9a25f70 JL |
2284 | if (GET_CODE (new) == MEM) |
2285 | return XEXP (new, 0); | |
2286 | return x; | |
2287 | ||
32131a9c RK |
2288 | case REG: |
2289 | regno = REGNO (x); | |
2290 | ||
2291 | /* First handle the case where we encounter a bare register that | |
2292 | is eliminable. Replace it with a PLUS. */ | |
2293 | if (regno < FIRST_PSEUDO_REGISTER) | |
2294 | { | |
2295 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2296 | ep++) | |
2297 | if (ep->from_rtx == x && ep->can_eliminate) | |
dfac187e | 2298 | return plus_constant (ep->to_rtx, ep->previous_offset); |
32131a9c RK |
2299 | |
2300 | } | |
2b49ee39 R |
2301 | else if (reg_renumber[regno] < 0 && reg_equiv_constant |
2302 | && reg_equiv_constant[regno] | |
2303 | && ! CONSTANT_P (reg_equiv_constant[regno])) | |
2304 | return eliminate_regs (copy_rtx (reg_equiv_constant[regno]), | |
2305 | mem_mode, insn); | |
32131a9c RK |
2306 | return x; |
2307 | ||
c5c76735 JL |
2308 | /* You might think handling MINUS in a manner similar to PLUS is a |
2309 | good idea. It is not. It has been tried multiple times and every | |
2310 | time the change has had to have been reverted. | |
2311 | ||
2312 | Other parts of reload know a PLUS is special (gen_reload for example) | |
2313 | and require special code to handle code a reloaded PLUS operand. | |
2314 | ||
2315 | Also consider backends where the flags register is clobbered by a | |
2316 | MINUS, but we can emit a PLUS that does not clobber flags (ia32, | |
2317 | lea instruction comes to mind). If we try to reload a MINUS, we | |
2318 | may kill the flags register that was holding a useful value. | |
2319 | ||
2320 | So, please before trying to handle MINUS, consider reload as a | |
2321 | whole instead of this little section as well as the backend issues. */ | |
32131a9c RK |
2322 | case PLUS: |
2323 | /* If this is the sum of an eliminable register and a constant, rework | |
6d2f8887 | 2324 | the sum. */ |
32131a9c RK |
2325 | if (GET_CODE (XEXP (x, 0)) == REG |
2326 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2327 | && CONSTANT_P (XEXP (x, 1))) | |
2328 | { | |
2329 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2330 | ep++) | |
2331 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2332 | { | |
32131a9c RK |
2333 | /* The only time we want to replace a PLUS with a REG (this |
2334 | occurs when the constant operand of the PLUS is the negative | |
2335 | of the offset) is when we are inside a MEM. We won't want | |
2336 | to do so at other times because that would change the | |
2337 | structure of the insn in a way that reload can't handle. | |
2338 | We special-case the commonest situation in | |
2339 | eliminate_regs_in_insn, so just replace a PLUS with a | |
2340 | PLUS here, unless inside a MEM. */ | |
a23b64d5 | 2341 | if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT |
32131a9c RK |
2342 | && INTVAL (XEXP (x, 1)) == - ep->previous_offset) |
2343 | return ep->to_rtx; | |
2344 | else | |
38a448ca RH |
2345 | return gen_rtx_PLUS (Pmode, ep->to_rtx, |
2346 | plus_constant (XEXP (x, 1), | |
2347 | ep->previous_offset)); | |
32131a9c RK |
2348 | } |
2349 | ||
2350 | /* If the register is not eliminable, we are done since the other | |
2351 | operand is a constant. */ | |
2352 | return x; | |
2353 | } | |
2354 | ||
2355 | /* If this is part of an address, we want to bring any constant to the | |
2356 | outermost PLUS. We will do this by doing register replacement in | |
2357 | our operands and seeing if a constant shows up in one of them. | |
2358 | ||
dfac187e BS |
2359 | Note that there is no risk of modifying the structure of the insn, |
2360 | since we only get called for its operands, thus we are either | |
2361 | modifying the address inside a MEM, or something like an address | |
2362 | operand of a load-address insn. */ | |
32131a9c RK |
2363 | |
2364 | { | |
1914f5da RH |
2365 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
2366 | rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn); | |
32131a9c RK |
2367 | |
2368 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
2369 | { | |
2370 | /* If one side is a PLUS and the other side is a pseudo that | |
a8fdc208 | 2371 | didn't get a hard register but has a reg_equiv_constant, |
32131a9c RK |
2372 | we must replace the constant here since it may no longer |
2373 | be in the position of any operand. */ | |
2374 | if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG | |
2375 | && REGNO (new1) >= FIRST_PSEUDO_REGISTER | |
2376 | && reg_renumber[REGNO (new1)] < 0 | |
2377 | && reg_equiv_constant != 0 | |
2378 | && reg_equiv_constant[REGNO (new1)] != 0) | |
2379 | new1 = reg_equiv_constant[REGNO (new1)]; | |
2380 | else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG | |
2381 | && REGNO (new0) >= FIRST_PSEUDO_REGISTER | |
2382 | && reg_renumber[REGNO (new0)] < 0 | |
2383 | && reg_equiv_constant[REGNO (new0)] != 0) | |
2384 | new0 = reg_equiv_constant[REGNO (new0)]; | |
2385 | ||
2386 | new = form_sum (new0, new1); | |
2387 | ||
2388 | /* As above, if we are not inside a MEM we do not want to | |
2389 | turn a PLUS into something else. We might try to do so here | |
2390 | for an addition of 0 if we aren't optimizing. */ | |
2391 | if (! mem_mode && GET_CODE (new) != PLUS) | |
38a448ca | 2392 | return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx); |
32131a9c RK |
2393 | else |
2394 | return new; | |
2395 | } | |
2396 | } | |
2397 | return x; | |
2398 | ||
981c7390 | 2399 | case MULT: |
05d10675 | 2400 | /* If this is the product of an eliminable register and a |
981c7390 RK |
2401 | constant, apply the distribute law and move the constant out |
2402 | so that we have (plus (mult ..) ..). This is needed in order | |
9faa82d8 | 2403 | to keep load-address insns valid. This case is pathological. |
981c7390 RK |
2404 | We ignore the possibility of overflow here. */ |
2405 | if (GET_CODE (XEXP (x, 0)) == REG | |
2406 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2407 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2408 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2409 | ep++) | |
2410 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2411 | { | |
2412 | if (! mem_mode | |
2413 | /* Refs inside notes don't count for this purpose. */ | |
2414 | && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST | |
2415 | || GET_CODE (insn) == INSN_LIST))) | |
2416 | ep->ref_outside_mem = 1; | |
2417 | ||
2418 | return | |
38a448ca | 2419 | plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)), |
981c7390 RK |
2420 | ep->previous_offset * INTVAL (XEXP (x, 1))); |
2421 | } | |
32131a9c | 2422 | |
0f41302f | 2423 | /* ... fall through ... */ |
32131a9c | 2424 | |
32131a9c RK |
2425 | case CALL: |
2426 | case COMPARE: | |
c5c76735 | 2427 | /* See comments before PLUS about handling MINUS. */ |
930aeef3 | 2428 | case MINUS: |
32131a9c RK |
2429 | case DIV: case UDIV: |
2430 | case MOD: case UMOD: | |
2431 | case AND: case IOR: case XOR: | |
45620ed4 RK |
2432 | case ROTATERT: case ROTATE: |
2433 | case ASHIFTRT: case LSHIFTRT: case ASHIFT: | |
32131a9c RK |
2434 | case NE: case EQ: |
2435 | case GE: case GT: case GEU: case GTU: | |
2436 | case LE: case LT: case LEU: case LTU: | |
2437 | { | |
1914f5da | 2438 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
fb3821f7 | 2439 | rtx new1 |
1914f5da | 2440 | = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0; |
32131a9c RK |
2441 | |
2442 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
38a448ca | 2443 | return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); |
32131a9c RK |
2444 | } |
2445 | return x; | |
2446 | ||
981c7390 RK |
2447 | case EXPR_LIST: |
2448 | /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ | |
2449 | if (XEXP (x, 0)) | |
2450 | { | |
1914f5da | 2451 | new = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
981c7390 | 2452 | if (new != XEXP (x, 0)) |
13bb79d4 R |
2453 | { |
2454 | /* If this is a REG_DEAD note, it is not valid anymore. | |
2455 | Using the eliminated version could result in creating a | |
2456 | REG_DEAD note for the stack or frame pointer. */ | |
2457 | if (GET_MODE (x) == REG_DEAD) | |
2458 | return (XEXP (x, 1) | |
2459 | ? eliminate_regs (XEXP (x, 1), mem_mode, insn) | |
2460 | : NULL_RTX); | |
2461 | ||
2462 | x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1)); | |
2463 | } | |
981c7390 RK |
2464 | } |
2465 | ||
0f41302f | 2466 | /* ... fall through ... */ |
981c7390 RK |
2467 | |
2468 | case INSN_LIST: | |
2469 | /* Now do eliminations in the rest of the chain. If this was | |
2470 | an EXPR_LIST, this might result in allocating more memory than is | |
2471 | strictly needed, but it simplifies the code. */ | |
2472 | if (XEXP (x, 1)) | |
2473 | { | |
1914f5da | 2474 | new = eliminate_regs (XEXP (x, 1), mem_mode, insn); |
981c7390 | 2475 | if (new != XEXP (x, 1)) |
38a448ca | 2476 | return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new); |
981c7390 RK |
2477 | } |
2478 | return x; | |
2479 | ||
32131a9c RK |
2480 | case PRE_INC: |
2481 | case POST_INC: | |
2482 | case PRE_DEC: | |
2483 | case POST_DEC: | |
32131a9c RK |
2484 | case STRICT_LOW_PART: |
2485 | case NEG: case NOT: | |
2486 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2487 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2488 | case FLOAT: case FIX: | |
2489 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2490 | case ABS: | |
2491 | case SQRT: | |
2492 | case FFS: | |
1914f5da | 2493 | new = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
32131a9c | 2494 | if (new != XEXP (x, 0)) |
38a448ca | 2495 | return gen_rtx_fmt_e (code, GET_MODE (x), new); |
32131a9c RK |
2496 | return x; |
2497 | ||
2498 | case SUBREG: | |
ddef6bc7 | 2499 | /* Similar to above processing, but preserve SUBREG_BYTE. |
32131a9c RK |
2500 | Convert (subreg (mem)) to (mem) if not paradoxical. |
2501 | Also, if we have a non-paradoxical (subreg (pseudo)) and the | |
2502 | pseudo didn't get a hard reg, we must replace this with the | |
2503 | eliminated version of the memory location because push_reloads | |
2504 | may do the replacement in certain circumstances. */ | |
2505 | if (GET_CODE (SUBREG_REG (x)) == REG | |
2506 | && (GET_MODE_SIZE (GET_MODE (x)) | |
2507 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2508 | && reg_equiv_memory_loc != 0 | |
2509 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2510 | { | |
cb2afeb3 | 2511 | new = SUBREG_REG (x); |
32131a9c RK |
2512 | } |
2513 | else | |
1914f5da | 2514 | new = eliminate_regs (SUBREG_REG (x), mem_mode, insn); |
32131a9c | 2515 | |
ddef6bc7 | 2516 | if (new != SUBREG_REG (x)) |
32131a9c | 2517 | { |
29ae5012 RK |
2518 | int x_size = GET_MODE_SIZE (GET_MODE (x)); |
2519 | int new_size = GET_MODE_SIZE (GET_MODE (new)); | |
2520 | ||
1914f5da | 2521 | if (GET_CODE (new) == MEM |
6d49a073 | 2522 | && ((x_size < new_size |
1914f5da | 2523 | #ifdef WORD_REGISTER_OPERATIONS |
6d49a073 JW |
2524 | /* On these machines, combine can create rtl of the form |
2525 | (set (subreg:m1 (reg:m2 R) 0) ...) | |
05d10675 | 2526 | where m1 < m2, and expects something interesting to |
6d49a073 JW |
2527 | happen to the entire word. Moreover, it will use the |
2528 | (reg:m2 R) later, expecting all bits to be preserved. | |
05d10675 | 2529 | So if the number of words is the same, preserve the |
6d49a073 | 2530 | subreg so that push_reloads can see it. */ |
5d9669fd RK |
2531 | && ! ((x_size - 1) / UNITS_PER_WORD |
2532 | == (new_size -1 ) / UNITS_PER_WORD) | |
1914f5da | 2533 | #endif |
6d49a073 | 2534 | ) |
5d9669fd | 2535 | || x_size == new_size) |
1914f5da | 2536 | ) |
32131a9c | 2537 | { |
ddef6bc7 | 2538 | int offset = SUBREG_BYTE (x); |
32131a9c RK |
2539 | enum machine_mode mode = GET_MODE (x); |
2540 | ||
32131a9c RK |
2541 | PUT_MODE (new, mode); |
2542 | XEXP (new, 0) = plus_constant (XEXP (new, 0), offset); | |
2543 | return new; | |
2544 | } | |
2545 | else | |
ddef6bc7 | 2546 | return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x)); |
32131a9c RK |
2547 | } |
2548 | ||
2549 | return x; | |
2550 | ||
32131a9c | 2551 | case MEM: |
e9a25f70 JL |
2552 | /* This is only for the benefit of the debugging backends, which call |
2553 | eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are | |
2554 | removed after CSE. */ | |
2555 | if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) | |
1914f5da | 2556 | return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn); |
e9a25f70 | 2557 | |
32131a9c RK |
2558 | /* Our only special processing is to pass the mode of the MEM to our |
2559 | recursive call and copy the flags. While we are here, handle this | |
2560 | case more efficiently. */ | |
f1ec5147 RK |
2561 | return |
2562 | replace_equiv_address_nv (x, | |
2563 | eliminate_regs (XEXP (x, 0), | |
2564 | GET_MODE (x), insn)); | |
05d10675 | 2565 | |
dfac187e | 2566 | case USE: |
055c7759 JDA |
2567 | /* Handle insn_list USE that a call to a pure function may generate. */ |
2568 | new = eliminate_regs (XEXP (x, 0), 0, insn); | |
2569 | if (new != XEXP (x, 0)) | |
2570 | return gen_rtx_USE (GET_MODE (x), new); | |
2571 | return x; | |
2572 | ||
dfac187e BS |
2573 | case CLOBBER: |
2574 | case ASM_OPERANDS: | |
2575 | case SET: | |
2576 | abort (); | |
2577 | ||
e9a25f70 JL |
2578 | default: |
2579 | break; | |
32131a9c RK |
2580 | } |
2581 | ||
2582 | /* Process each of our operands recursively. If any have changed, make a | |
2583 | copy of the rtx. */ | |
2584 | fmt = GET_RTX_FORMAT (code); | |
2585 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2586 | { | |
2587 | if (*fmt == 'e') | |
2588 | { | |
1914f5da | 2589 | new = eliminate_regs (XEXP (x, i), mem_mode, insn); |
32131a9c RK |
2590 | if (new != XEXP (x, i) && ! copied) |
2591 | { | |
2592 | rtx new_x = rtx_alloc (code); | |
4e135bdd KG |
2593 | memcpy (new_x, x, |
2594 | (sizeof (*new_x) - sizeof (new_x->fld) | |
2595 | + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code))); | |
32131a9c RK |
2596 | x = new_x; |
2597 | copied = 1; | |
2598 | } | |
2599 | XEXP (x, i) = new; | |
2600 | } | |
2601 | else if (*fmt == 'E') | |
2602 | { | |
2603 | int copied_vec = 0; | |
2604 | for (j = 0; j < XVECLEN (x, i); j++) | |
2605 | { | |
1914f5da | 2606 | new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn); |
32131a9c RK |
2607 | if (new != XVECEXP (x, i, j) && ! copied_vec) |
2608 | { | |
8f985ec4 ZW |
2609 | rtvec new_v = gen_rtvec_v (XVECLEN (x, i), |
2610 | XVEC (x, i)->elem); | |
32131a9c RK |
2611 | if (! copied) |
2612 | { | |
2613 | rtx new_x = rtx_alloc (code); | |
4e135bdd KG |
2614 | memcpy (new_x, x, |
2615 | (sizeof (*new_x) - sizeof (new_x->fld) | |
2616 | + (sizeof (new_x->fld[0]) | |
2617 | * GET_RTX_LENGTH (code)))); | |
32131a9c RK |
2618 | x = new_x; |
2619 | copied = 1; | |
2620 | } | |
2621 | XVEC (x, i) = new_v; | |
2622 | copied_vec = 1; | |
2623 | } | |
2624 | XVECEXP (x, i, j) = new; | |
2625 | } | |
2626 | } | |
2627 | } | |
2628 | ||
2629 | return x; | |
2630 | } | |
dfac187e BS |
2631 | |
2632 | /* Scan rtx X for modifications of elimination target registers. Update | |
2633 | the table of eliminables to reflect the changed state. MEM_MODE is | |
2634 | the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */ | |
2635 | ||
2636 | static void | |
2637 | elimination_effects (x, mem_mode) | |
2638 | rtx x; | |
2639 | enum machine_mode mem_mode; | |
2640 | ||
2641 | { | |
2642 | enum rtx_code code = GET_CODE (x); | |
2643 | struct elim_table *ep; | |
2644 | int regno; | |
2645 | int i, j; | |
2646 | const char *fmt; | |
2647 | ||
2648 | switch (code) | |
2649 | { | |
2650 | case CONST_INT: | |
2651 | case CONST_DOUBLE: | |
2652 | case CONST: | |
2653 | case SYMBOL_REF: | |
2654 | case CODE_LABEL: | |
2655 | case PC: | |
2656 | case CC0: | |
2657 | case ASM_INPUT: | |
2658 | case ADDR_VEC: | |
2659 | case ADDR_DIFF_VEC: | |
2660 | case RETURN: | |
2661 | return; | |
2662 | ||
2663 | case ADDRESSOF: | |
2664 | abort (); | |
2665 | ||
2666 | case REG: | |
2667 | regno = REGNO (x); | |
2668 | ||
2669 | /* First handle the case where we encounter a bare register that | |
2670 | is eliminable. Replace it with a PLUS. */ | |
2671 | if (regno < FIRST_PSEUDO_REGISTER) | |
2672 | { | |
2673 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2674 | ep++) | |
2675 | if (ep->from_rtx == x && ep->can_eliminate) | |
2676 | { | |
2677 | if (! mem_mode) | |
2678 | ep->ref_outside_mem = 1; | |
2679 | return; | |
2680 | } | |
2681 | ||
2682 | } | |
2683 | else if (reg_renumber[regno] < 0 && reg_equiv_constant | |
2684 | && reg_equiv_constant[regno] | |
2685 | && ! CONSTANT_P (reg_equiv_constant[regno])) | |
2686 | elimination_effects (reg_equiv_constant[regno], mem_mode); | |
2687 | return; | |
2688 | ||
2689 | case PRE_INC: | |
2690 | case POST_INC: | |
2691 | case PRE_DEC: | |
2692 | case POST_DEC: | |
4b983fdc RH |
2693 | case POST_MODIFY: |
2694 | case PRE_MODIFY: | |
dfac187e BS |
2695 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
2696 | if (ep->to_rtx == XEXP (x, 0)) | |
2697 | { | |
2698 | int size = GET_MODE_SIZE (mem_mode); | |
2699 | ||
2700 | /* If more bytes than MEM_MODE are pushed, account for them. */ | |
2701 | #ifdef PUSH_ROUNDING | |
2702 | if (ep->to_rtx == stack_pointer_rtx) | |
2703 | size = PUSH_ROUNDING (size); | |
2704 | #endif | |
2705 | if (code == PRE_DEC || code == POST_DEC) | |
2706 | ep->offset += size; | |
4b983fdc | 2707 | else if (code == PRE_INC || code == POST_INC) |
dfac187e | 2708 | ep->offset -= size; |
4b983fdc RH |
2709 | else if ((code == PRE_MODIFY || code == POST_MODIFY) |
2710 | && GET_CODE (XEXP (x, 1)) == PLUS | |
2711 | && XEXP (x, 0) == XEXP (XEXP (x, 1), 0) | |
2712 | && CONSTANT_P (XEXP (XEXP (x, 1), 1))) | |
2713 | ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1)); | |
dfac187e BS |
2714 | } |
2715 | ||
4b983fdc RH |
2716 | /* These two aren't unary operators. */ |
2717 | if (code == POST_MODIFY || code == PRE_MODIFY) | |
2718 | break; | |
2719 | ||
dfac187e BS |
2720 | /* Fall through to generic unary operation case. */ |
2721 | case STRICT_LOW_PART: | |
2722 | case NEG: case NOT: | |
2723 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2724 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2725 | case FLOAT: case FIX: | |
2726 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2727 | case ABS: | |
2728 | case SQRT: | |
2729 | case FFS: | |
2730 | elimination_effects (XEXP (x, 0), mem_mode); | |
2731 | return; | |
2732 | ||
2733 | case SUBREG: | |
2734 | if (GET_CODE (SUBREG_REG (x)) == REG | |
2735 | && (GET_MODE_SIZE (GET_MODE (x)) | |
2736 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2737 | && reg_equiv_memory_loc != 0 | |
2738 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2739 | return; | |
2740 | ||
2741 | elimination_effects (SUBREG_REG (x), mem_mode); | |
2742 | return; | |
2743 | ||
2744 | case USE: | |
2745 | /* If using a register that is the source of an eliminate we still | |
2746 | think can be performed, note it cannot be performed since we don't | |
2747 | know how this register is used. */ | |
2748 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2749 | if (ep->from_rtx == XEXP (x, 0)) | |
2750 | ep->can_eliminate = 0; | |
2751 | ||
2752 | elimination_effects (XEXP (x, 0), mem_mode); | |
2753 | return; | |
2754 | ||
2755 | case CLOBBER: | |
2756 | /* If clobbering a register that is the replacement register for an | |
2757 | elimination we still think can be performed, note that it cannot | |
2758 | be performed. Otherwise, we need not be concerned about it. */ | |
2759 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2760 | if (ep->to_rtx == XEXP (x, 0)) | |
2761 | ep->can_eliminate = 0; | |
2762 | ||
2763 | elimination_effects (XEXP (x, 0), mem_mode); | |
2764 | return; | |
2765 | ||
2766 | case SET: | |
2767 | /* Check for setting a register that we know about. */ | |
2768 | if (GET_CODE (SET_DEST (x)) == REG) | |
2769 | { | |
2770 | /* See if this is setting the replacement register for an | |
2771 | elimination. | |
2772 | ||
2773 | If DEST is the hard frame pointer, we do nothing because we | |
2774 | assume that all assignments to the frame pointer are for | |
2775 | non-local gotos and are being done at a time when they are valid | |
2776 | and do not disturb anything else. Some machines want to | |
2777 | eliminate a fake argument pointer (or even a fake frame pointer) | |
2778 | with either the real frame or the stack pointer. Assignments to | |
2779 | the hard frame pointer must not prevent this elimination. */ | |
2780 | ||
2781 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2782 | ep++) | |
2783 | if (ep->to_rtx == SET_DEST (x) | |
2784 | && SET_DEST (x) != hard_frame_pointer_rtx) | |
2785 | { | |
2786 | /* If it is being incremented, adjust the offset. Otherwise, | |
2787 | this elimination can't be done. */ | |
2788 | rtx src = SET_SRC (x); | |
2789 | ||
2790 | if (GET_CODE (src) == PLUS | |
2791 | && XEXP (src, 0) == SET_DEST (x) | |
2792 | && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
2793 | ep->offset -= INTVAL (XEXP (src, 1)); | |
2794 | else | |
2795 | ep->can_eliminate = 0; | |
2796 | } | |
2797 | } | |
2798 | ||
2799 | elimination_effects (SET_DEST (x), 0); | |
2800 | elimination_effects (SET_SRC (x), 0); | |
2801 | return; | |
2802 | ||
2803 | case MEM: | |
2804 | if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) | |
2805 | abort (); | |
2806 | ||
2807 | /* Our only special processing is to pass the mode of the MEM to our | |
2808 | recursive call. */ | |
2809 | elimination_effects (XEXP (x, 0), GET_MODE (x)); | |
2810 | return; | |
2811 | ||
2812 | default: | |
2813 | break; | |
2814 | } | |
2815 | ||
2816 | fmt = GET_RTX_FORMAT (code); | |
2817 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2818 | { | |
2819 | if (*fmt == 'e') | |
2820 | elimination_effects (XEXP (x, i), mem_mode); | |
2821 | else if (*fmt == 'E') | |
2822 | for (j = 0; j < XVECLEN (x, i); j++) | |
2823 | elimination_effects (XVECEXP (x, i, j), mem_mode); | |
2824 | } | |
2825 | } | |
2826 | ||
2827 | /* Descend through rtx X and verify that no references to eliminable registers | |
2828 | remain. If any do remain, mark the involved register as not | |
2829 | eliminable. */ | |
1d813780 | 2830 | |
dfac187e BS |
2831 | static void |
2832 | check_eliminable_occurrences (x) | |
2833 | rtx x; | |
2834 | { | |
2835 | const char *fmt; | |
2836 | int i; | |
2837 | enum rtx_code code; | |
2838 | ||
2839 | if (x == 0) | |
2840 | return; | |
1d7254c5 | 2841 | |
dfac187e BS |
2842 | code = GET_CODE (x); |
2843 | ||
2844 | if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
2845 | { | |
2846 | struct elim_table *ep; | |
2847 | ||
2848 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2849 | if (ep->from_rtx == x && ep->can_eliminate) | |
2850 | ep->can_eliminate = 0; | |
2851 | return; | |
2852 | } | |
1d7254c5 | 2853 | |
dfac187e BS |
2854 | fmt = GET_RTX_FORMAT (code); |
2855 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2856 | { | |
2857 | if (*fmt == 'e') | |
2858 | check_eliminable_occurrences (XEXP (x, i)); | |
2859 | else if (*fmt == 'E') | |
2860 | { | |
2861 | int j; | |
2862 | for (j = 0; j < XVECLEN (x, i); j++) | |
2863 | check_eliminable_occurrences (XVECEXP (x, i, j)); | |
2864 | } | |
2865 | } | |
2866 | } | |
32131a9c RK |
2867 | \f |
2868 | /* Scan INSN and eliminate all eliminable registers in it. | |
2869 | ||
2870 | If REPLACE is nonzero, do the replacement destructively. Also | |
2871 | delete the insn as dead it if it is setting an eliminable register. | |
2872 | ||
2873 | If REPLACE is zero, do all our allocations in reload_obstack. | |
2874 | ||
2875 | If no eliminations were done and this insn doesn't require any elimination | |
2876 | processing (these are not identical conditions: it might be updating sp, | |
2877 | but not referencing fp; this needs to be seen during reload_as_needed so | |
2878 | that the offset between fp and sp can be taken into consideration), zero | |
2879 | is returned. Otherwise, 1 is returned. */ | |
2880 | ||
2881 | static int | |
2882 | eliminate_regs_in_insn (insn, replace) | |
2883 | rtx insn; | |
2884 | int replace; | |
2885 | { | |
dfac187e | 2886 | int icode = recog_memoized (insn); |
32131a9c | 2887 | rtx old_body = PATTERN (insn); |
dfac187e | 2888 | int insn_is_asm = asm_noperands (old_body) >= 0; |
774672d2 | 2889 | rtx old_set = single_set (insn); |
32131a9c RK |
2890 | rtx new_body; |
2891 | int val = 0; | |
dfac187e BS |
2892 | int i, any_changes; |
2893 | rtx substed_operand[MAX_RECOG_OPERANDS]; | |
2894 | rtx orig_operand[MAX_RECOG_OPERANDS]; | |
32131a9c RK |
2895 | struct elim_table *ep; |
2896 | ||
dfac187e BS |
2897 | if (! insn_is_asm && icode < 0) |
2898 | { | |
2899 | if (GET_CODE (PATTERN (insn)) == USE | |
2900 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
2901 | || GET_CODE (PATTERN (insn)) == ADDR_VEC | |
2902 | || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | |
2903 | || GET_CODE (PATTERN (insn)) == ASM_INPUT) | |
2904 | return 0; | |
2905 | abort (); | |
2906 | } | |
2907 | ||
774672d2 RK |
2908 | if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG |
2909 | && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) | |
32131a9c RK |
2910 | { |
2911 | /* Check for setting an eliminable register. */ | |
2912 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
774672d2 | 2913 | if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) |
32131a9c | 2914 | { |
dd1eab0a RK |
2915 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
2916 | /* If this is setting the frame pointer register to the | |
2917 | hardware frame pointer register and this is an elimination | |
2918 | that will be done (tested above), this insn is really | |
2919 | adjusting the frame pointer downward to compensate for | |
2920 | the adjustment done before a nonlocal goto. */ | |
2921 | if (ep->from == FRAME_POINTER_REGNUM | |
2922 | && ep->to == HARD_FRAME_POINTER_REGNUM) | |
2923 | { | |
2924 | rtx src = SET_SRC (old_set); | |
973838fd | 2925 | int offset = 0, ok = 0; |
8026ebba | 2926 | rtx prev_insn, prev_set; |
dd1eab0a RK |
2927 | |
2928 | if (src == ep->to_rtx) | |
2929 | offset = 0, ok = 1; | |
2930 | else if (GET_CODE (src) == PLUS | |
bb22893c JW |
2931 | && GET_CODE (XEXP (src, 0)) == CONST_INT |
2932 | && XEXP (src, 1) == ep->to_rtx) | |
dd1eab0a | 2933 | offset = INTVAL (XEXP (src, 0)), ok = 1; |
bb22893c JW |
2934 | else if (GET_CODE (src) == PLUS |
2935 | && GET_CODE (XEXP (src, 1)) == CONST_INT | |
2936 | && XEXP (src, 0) == ep->to_rtx) | |
2937 | offset = INTVAL (XEXP (src, 1)), ok = 1; | |
8026ebba ILT |
2938 | else if ((prev_insn = prev_nonnote_insn (insn)) != 0 |
2939 | && (prev_set = single_set (prev_insn)) != 0 | |
2940 | && rtx_equal_p (SET_DEST (prev_set), src)) | |
2941 | { | |
2942 | src = SET_SRC (prev_set); | |
2943 | if (src == ep->to_rtx) | |
2944 | offset = 0, ok = 1; | |
2945 | else if (GET_CODE (src) == PLUS | |
2946 | && GET_CODE (XEXP (src, 0)) == CONST_INT | |
2947 | && XEXP (src, 1) == ep->to_rtx) | |
2948 | offset = INTVAL (XEXP (src, 0)), ok = 1; | |
2949 | else if (GET_CODE (src) == PLUS | |
2950 | && GET_CODE (XEXP (src, 1)) == CONST_INT | |
2951 | && XEXP (src, 0) == ep->to_rtx) | |
2952 | offset = INTVAL (XEXP (src, 1)), ok = 1; | |
2953 | } | |
dd1eab0a RK |
2954 | |
2955 | if (ok) | |
2956 | { | |
c77fbfbe GK |
2957 | rtx src |
2958 | = plus_constant (ep->to_rtx, offset - ep->offset); | |
2959 | ||
2960 | new_body = old_body; | |
2961 | if (! replace) | |
2962 | { | |
2963 | new_body = copy_insn (old_body); | |
2964 | if (REG_NOTES (insn)) | |
2965 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
2966 | } | |
2967 | PATTERN (insn) = new_body; | |
2968 | old_set = single_set (insn); | |
2969 | ||
2970 | /* First see if this insn remains valid when we | |
2971 | make the change. If not, keep the INSN_CODE | |
2972 | the same and let reload fit it up. */ | |
2973 | validate_change (insn, &SET_SRC (old_set), src, 1); | |
2974 | validate_change (insn, &SET_DEST (old_set), | |
2975 | ep->to_rtx, 1); | |
2976 | if (! apply_change_group ()) | |
dd1eab0a | 2977 | { |
c77fbfbe GK |
2978 | SET_SRC (old_set) = src; |
2979 | SET_DEST (old_set) = ep->to_rtx; | |
dd1eab0a RK |
2980 | } |
2981 | ||
2982 | val = 1; | |
2983 | goto done; | |
2984 | } | |
2985 | } | |
2986 | #endif | |
2987 | ||
32131a9c RK |
2988 | /* In this case this insn isn't serving a useful purpose. We |
2989 | will delete it in reload_as_needed once we know that this | |
2990 | elimination is, in fact, being done. | |
2991 | ||
abc95ed3 | 2992 | If REPLACE isn't set, we can't delete this insn, but needn't |
32131a9c RK |
2993 | process it since it won't be used unless something changes. */ |
2994 | if (replace) | |
8a34409d | 2995 | { |
1d7254c5 | 2996 | delete_dead_insn (insn); |
8a34409d RH |
2997 | return 1; |
2998 | } | |
32131a9c RK |
2999 | val = 1; |
3000 | goto done; | |
3001 | } | |
aa5524a9 | 3002 | } |
32131a9c | 3003 | |
aa5524a9 BS |
3004 | /* We allow one special case which happens to work on all machines we |
3005 | currently support: a single set with the source being a PLUS of an | |
3006 | eliminable register and a constant. */ | |
3007 | if (old_set | |
1abdf5e7 | 3008 | && GET_CODE (SET_DEST (old_set)) == REG |
aa5524a9 BS |
3009 | && GET_CODE (SET_SRC (old_set)) == PLUS |
3010 | && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG | |
3011 | && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT | |
3012 | && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER) | |
3013 | { | |
3014 | rtx reg = XEXP (SET_SRC (old_set), 0); | |
3015 | int offset = INTVAL (XEXP (SET_SRC (old_set), 1)); | |
32131a9c | 3016 | |
aa5524a9 BS |
3017 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3018 | if (ep->from_rtx == reg && ep->can_eliminate) | |
3019 | { | |
3020 | offset += ep->offset; | |
32131a9c | 3021 | |
aa5524a9 BS |
3022 | if (offset == 0) |
3023 | { | |
f34c06e5 R |
3024 | int num_clobbers; |
3025 | /* We assume here that if we need a PARALLEL with | |
3026 | CLOBBERs for this assignment, we can do with the | |
3027 | MATCH_SCRATCHes that add_clobbers allocates. | |
3028 | There's not much we can do if that doesn't work. */ | |
aa5524a9 BS |
3029 | PATTERN (insn) = gen_rtx_SET (VOIDmode, |
3030 | SET_DEST (old_set), | |
3031 | ep->to_rtx); | |
f34c06e5 R |
3032 | num_clobbers = 0; |
3033 | INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers); | |
3034 | if (num_clobbers) | |
3035 | { | |
3036 | rtvec vec = rtvec_alloc (num_clobbers + 1); | |
3037 | ||
3038 | vec->elem[0] = PATTERN (insn); | |
3039 | PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec); | |
3040 | add_clobbers (PATTERN (insn), INSN_CODE (insn)); | |
3041 | } | |
aa5524a9 BS |
3042 | if (INSN_CODE (insn) < 0) |
3043 | abort (); | |
3044 | } | |
3045 | else | |
3046 | { | |
3047 | new_body = old_body; | |
3048 | if (! replace) | |
3049 | { | |
3050 | new_body = copy_insn (old_body); | |
3051 | if (REG_NOTES (insn)) | |
3052 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3053 | } | |
3054 | PATTERN (insn) = new_body; | |
3055 | old_set = single_set (insn); | |
922d9d40 | 3056 | |
aa5524a9 BS |
3057 | XEXP (SET_SRC (old_set), 0) = ep->to_rtx; |
3058 | XEXP (SET_SRC (old_set), 1) = GEN_INT (offset); | |
3059 | } | |
3060 | val = 1; | |
3061 | /* This can't have an effect on elimination offsets, so skip right | |
3062 | to the end. */ | |
3063 | goto done; | |
3064 | } | |
32131a9c RK |
3065 | } |
3066 | ||
dfac187e BS |
3067 | /* Determine the effects of this insn on elimination offsets. */ |
3068 | elimination_effects (old_body, 0); | |
3069 | ||
3070 | /* Eliminate all eliminable registers occurring in operands that | |
3071 | can be handled by reload. */ | |
3072 | extract_insn (insn); | |
3073 | any_changes = 0; | |
3074 | for (i = 0; i < recog_data.n_operands; i++) | |
3075 | { | |
3076 | orig_operand[i] = recog_data.operand[i]; | |
3077 | substed_operand[i] = recog_data.operand[i]; | |
3078 | ||
3079 | /* For an asm statement, every operand is eliminable. */ | |
3080 | if (insn_is_asm || insn_data[icode].operand[i].eliminable) | |
3081 | { | |
3082 | /* Check for setting a register that we know about. */ | |
3083 | if (recog_data.operand_type[i] != OP_IN | |
3084 | && GET_CODE (orig_operand[i]) == REG) | |
3085 | { | |
3086 | /* If we are assigning to a register that can be eliminated, it | |
3087 | must be as part of a PARALLEL, since the code above handles | |
3088 | single SETs. We must indicate that we can no longer | |
3089 | eliminate this reg. */ | |
3090 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
3091 | ep++) | |
3092 | if (ep->from_rtx == orig_operand[i] && ep->can_eliminate) | |
3093 | ep->can_eliminate = 0; | |
3094 | } | |
3095 | ||
3096 | substed_operand[i] = eliminate_regs (recog_data.operand[i], 0, | |
3097 | replace ? insn : NULL_RTX); | |
3098 | if (substed_operand[i] != orig_operand[i]) | |
3099 | val = any_changes = 1; | |
3100 | /* Terminate the search in check_eliminable_occurrences at | |
3101 | this point. */ | |
3102 | *recog_data.operand_loc[i] = 0; | |
3103 | ||
3104 | /* If an output operand changed from a REG to a MEM and INSN is an | |
3105 | insn, write a CLOBBER insn. */ | |
3106 | if (recog_data.operand_type[i] != OP_IN | |
3107 | && GET_CODE (orig_operand[i]) == REG | |
3108 | && GET_CODE (substed_operand[i]) == MEM | |
3109 | && replace) | |
3110 | emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]), | |
3111 | insn); | |
3112 | } | |
3113 | } | |
3114 | ||
3115 | for (i = 0; i < recog_data.n_dups; i++) | |
3116 | *recog_data.dup_loc[i] | |
1d7254c5 | 3117 | = *recog_data.operand_loc[(int) recog_data.dup_num[i]]; |
dfac187e BS |
3118 | |
3119 | /* If any eliminable remain, they aren't eliminable anymore. */ | |
3120 | check_eliminable_occurrences (old_body); | |
32131a9c | 3121 | |
dfac187e BS |
3122 | /* Substitute the operands; the new values are in the substed_operand |
3123 | array. */ | |
3124 | for (i = 0; i < recog_data.n_operands; i++) | |
3125 | *recog_data.operand_loc[i] = substed_operand[i]; | |
3126 | for (i = 0; i < recog_data.n_dups; i++) | |
1d7254c5 | 3127 | *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]]; |
32131a9c | 3128 | |
dfac187e | 3129 | /* If we are replacing a body that was a (set X (plus Y Z)), try to |
32131a9c RK |
3130 | re-recognize the insn. We do this in case we had a simple addition |
3131 | but now can do this as a load-address. This saves an insn in this | |
dfac187e BS |
3132 | common case. |
3133 | If re-recognition fails, the old insn code number will still be used, | |
3134 | and some register operands may have changed into PLUS expressions. | |
3135 | These will be handled by find_reloads by loading them into a register | |
1d7254c5 | 3136 | again. */ |
32131a9c | 3137 | |
dfac187e | 3138 | if (val) |
32131a9c | 3139 | { |
7c791b13 RK |
3140 | /* If we aren't replacing things permanently and we changed something, |
3141 | make another copy to ensure that all the RTL is new. Otherwise | |
3142 | things can go wrong if find_reload swaps commutative operands | |
0f41302f | 3143 | and one is inside RTL that has been copied while the other is not. */ |
dfac187e BS |
3144 | new_body = old_body; |
3145 | if (! replace) | |
1b3b5765 BS |
3146 | { |
3147 | new_body = copy_insn (old_body); | |
3148 | if (REG_NOTES (insn)) | |
3149 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3150 | } | |
dfac187e | 3151 | PATTERN (insn) = new_body; |
7c791b13 | 3152 | |
774672d2 RK |
3153 | /* If we had a move insn but now we don't, rerecognize it. This will |
3154 | cause spurious re-recognition if the old move had a PARALLEL since | |
3155 | the new one still will, but we can't call single_set without | |
3156 | having put NEW_BODY into the insn and the re-recognition won't | |
3157 | hurt in this rare case. */ | |
dfac187e BS |
3158 | /* ??? Why this huge if statement - why don't we just rerecognize the |
3159 | thing always? */ | |
3160 | if (! insn_is_asm | |
3161 | && old_set != 0 | |
774672d2 RK |
3162 | && ((GET_CODE (SET_SRC (old_set)) == REG |
3163 | && (GET_CODE (new_body) != SET | |
3164 | || GET_CODE (SET_SRC (new_body)) != REG)) | |
3165 | /* If this was a load from or store to memory, compare | |
1ccbefce RH |
3166 | the MEM in recog_data.operand to the one in the insn. |
3167 | If they are not equal, then rerecognize the insn. */ | |
774672d2 RK |
3168 | || (old_set != 0 |
3169 | && ((GET_CODE (SET_SRC (old_set)) == MEM | |
1ccbefce | 3170 | && SET_SRC (old_set) != recog_data.operand[1]) |
774672d2 | 3171 | || (GET_CODE (SET_DEST (old_set)) == MEM |
1ccbefce | 3172 | && SET_DEST (old_set) != recog_data.operand[0]))) |
774672d2 RK |
3173 | /* If this was an add insn before, rerecognize. */ |
3174 | || GET_CODE (SET_SRC (old_set)) == PLUS)) | |
4a5d0fb5 | 3175 | { |
dfac187e BS |
3176 | int new_icode = recog (PATTERN (insn), insn, 0); |
3177 | if (new_icode < 0) | |
3178 | INSN_CODE (insn) = icode; | |
4a5d0fb5 | 3179 | } |
dfac187e | 3180 | } |
32131a9c | 3181 | |
dfac187e BS |
3182 | /* Restore the old body. If there were any changes to it, we made a copy |
3183 | of it while the changes were still in place, so we'll correctly return | |
3184 | a modified insn below. */ | |
3185 | if (! replace) | |
3186 | { | |
3187 | /* Restore the old body. */ | |
3188 | for (i = 0; i < recog_data.n_operands; i++) | |
3189 | *recog_data.operand_loc[i] = orig_operand[i]; | |
3190 | for (i = 0; i < recog_data.n_dups; i++) | |
1d7254c5 | 3191 | *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]]; |
32131a9c | 3192 | } |
a8fdc208 | 3193 | |
dfac187e BS |
3194 | /* Update all elimination pairs to reflect the status after the current |
3195 | insn. The changes we make were determined by the earlier call to | |
3196 | elimination_effects. | |
a8efe40d | 3197 | |
32131a9c RK |
3198 | We also detect a cases where register elimination cannot be done, |
3199 | namely, if a register would be both changed and referenced outside a MEM | |
3200 | in the resulting insn since such an insn is often undefined and, even if | |
3201 | not, we cannot know what meaning will be given to it. Note that it is | |
3202 | valid to have a register used in an address in an insn that changes it | |
3203 | (presumably with a pre- or post-increment or decrement). | |
3204 | ||
3205 | If anything changes, return nonzero. */ | |
3206 | ||
32131a9c RK |
3207 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3208 | { | |
3209 | if (ep->previous_offset != ep->offset && ep->ref_outside_mem) | |
3210 | ep->can_eliminate = 0; | |
3211 | ||
3212 | ep->ref_outside_mem = 0; | |
3213 | ||
3214 | if (ep->previous_offset != ep->offset) | |
3215 | val = 1; | |
32131a9c RK |
3216 | } |
3217 | ||
3218 | done: | |
9faa82d8 | 3219 | /* If we changed something, perform elimination in REG_NOTES. This is |
05b4c365 RK |
3220 | needed even when REPLACE is zero because a REG_DEAD note might refer |
3221 | to a register that we eliminate and could cause a different number | |
3222 | of spill registers to be needed in the final reload pass than in | |
3223 | the pre-passes. */ | |
20748cab | 3224 | if (val && REG_NOTES (insn) != 0) |
1914f5da | 3225 | REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn)); |
05b4c365 | 3226 | |
32131a9c RK |
3227 | return val; |
3228 | } | |
3229 | ||
cb2afeb3 R |
3230 | /* Loop through all elimination pairs. |
3231 | Recalculate the number not at initial offset. | |
3232 | ||
3233 | Compute the maximum offset (minimum offset if the stack does not | |
3234 | grow downward) for each elimination pair. */ | |
3235 | ||
3236 | static void | |
3237 | update_eliminable_offsets () | |
3238 | { | |
3239 | struct elim_table *ep; | |
3240 | ||
3241 | num_not_at_initial_offset = 0; | |
3242 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3243 | { | |
3244 | ep->previous_offset = ep->offset; | |
3245 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3246 | num_not_at_initial_offset++; | |
cb2afeb3 R |
3247 | } |
3248 | } | |
3249 | ||
32131a9c RK |
3250 | /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register |
3251 | replacement we currently believe is valid, mark it as not eliminable if X | |
3252 | modifies DEST in any way other than by adding a constant integer to it. | |
3253 | ||
3254 | If DEST is the frame pointer, we do nothing because we assume that | |
3ec2ea3e DE |
3255 | all assignments to the hard frame pointer are nonlocal gotos and are being |
3256 | done at a time when they are valid and do not disturb anything else. | |
32131a9c | 3257 | Some machines want to eliminate a fake argument pointer with either the |
3ec2ea3e DE |
3258 | frame or stack pointer. Assignments to the hard frame pointer must not |
3259 | prevent this elimination. | |
32131a9c RK |
3260 | |
3261 | Called via note_stores from reload before starting its passes to scan | |
3262 | the insns of the function. */ | |
3263 | ||
3264 | static void | |
84832317 | 3265 | mark_not_eliminable (dest, x, data) |
32131a9c RK |
3266 | rtx dest; |
3267 | rtx x; | |
84832317 | 3268 | void *data ATTRIBUTE_UNUSED; |
32131a9c | 3269 | { |
b3694847 | 3270 | unsigned int i; |
32131a9c RK |
3271 | |
3272 | /* A SUBREG of a hard register here is just changing its mode. We should | |
3273 | not see a SUBREG of an eliminable hard register, but check just in | |
3274 | case. */ | |
3275 | if (GET_CODE (dest) == SUBREG) | |
3276 | dest = SUBREG_REG (dest); | |
3277 | ||
3ec2ea3e | 3278 | if (dest == hard_frame_pointer_rtx) |
32131a9c RK |
3279 | return; |
3280 | ||
3281 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3282 | if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx | |
3283 | && (GET_CODE (x) != SET | |
3284 | || GET_CODE (SET_SRC (x)) != PLUS | |
3285 | || XEXP (SET_SRC (x), 0) != dest | |
3286 | || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT)) | |
3287 | { | |
3288 | reg_eliminate[i].can_eliminate_previous | |
3289 | = reg_eliminate[i].can_eliminate = 0; | |
3290 | num_eliminable--; | |
3291 | } | |
3292 | } | |
09dd1133 | 3293 | |
c47f5ea5 BS |
3294 | /* Verify that the initial elimination offsets did not change since the |
3295 | last call to set_initial_elim_offsets. This is used to catch cases | |
3296 | where something illegal happened during reload_as_needed that could | |
3297 | cause incorrect code to be generated if we did not check for it. */ | |
c8d8ed65 | 3298 | |
c47f5ea5 BS |
3299 | static void |
3300 | verify_initial_elim_offsets () | |
3301 | { | |
3302 | int t; | |
3303 | ||
3304 | #ifdef ELIMINABLE_REGS | |
3305 | struct elim_table *ep; | |
3306 | ||
3307 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3308 | { | |
3309 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t); | |
3310 | if (t != ep->initial_offset) | |
3311 | abort (); | |
3312 | } | |
3313 | #else | |
3314 | INITIAL_FRAME_POINTER_OFFSET (t); | |
3315 | if (t != reg_eliminate[0].initial_offset) | |
3316 | abort (); | |
05d10675 | 3317 | #endif |
c47f5ea5 BS |
3318 | } |
3319 | ||
09dd1133 | 3320 | /* Reset all offsets on eliminable registers to their initial values. */ |
1d813780 | 3321 | |
09dd1133 BS |
3322 | static void |
3323 | set_initial_elim_offsets () | |
3324 | { | |
1f3b1e1a | 3325 | struct elim_table *ep = reg_eliminate; |
09dd1133 BS |
3326 | |
3327 | #ifdef ELIMINABLE_REGS | |
1f3b1e1a | 3328 | for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
09dd1133 BS |
3329 | { |
3330 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); | |
1f3b1e1a | 3331 | ep->previous_offset = ep->offset = ep->initial_offset; |
09dd1133 BS |
3332 | } |
3333 | #else | |
1f3b1e1a JL |
3334 | INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset); |
3335 | ep->previous_offset = ep->offset = ep->initial_offset; | |
09dd1133 BS |
3336 | #endif |
3337 | ||
3338 | num_not_at_initial_offset = 0; | |
1f3b1e1a | 3339 | } |
09dd1133 | 3340 | |
1f3b1e1a JL |
3341 | /* Initialize the known label offsets. |
3342 | Set a known offset for each forced label to be at the initial offset | |
3343 | of each elimination. We do this because we assume that all | |
3344 | computed jumps occur from a location where each elimination is | |
3345 | at its initial offset. | |
3346 | For all other labels, show that we don't know the offsets. */ | |
09dd1133 | 3347 | |
1f3b1e1a JL |
3348 | static void |
3349 | set_initial_label_offsets () | |
3350 | { | |
3351 | rtx x; | |
961192e1 | 3352 | memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels); |
09dd1133 BS |
3353 | |
3354 | for (x = forced_labels; x; x = XEXP (x, 1)) | |
3355 | if (XEXP (x, 0)) | |
3356 | set_label_offsets (XEXP (x, 0), NULL_RTX, 1); | |
3357 | } | |
3358 | ||
1f3b1e1a JL |
3359 | /* Set all elimination offsets to the known values for the code label given |
3360 | by INSN. */ | |
1d813780 | 3361 | |
1f3b1e1a JL |
3362 | static void |
3363 | set_offsets_for_label (insn) | |
3364 | rtx insn; | |
3365 | { | |
973838fd | 3366 | unsigned int i; |
1f3b1e1a JL |
3367 | int label_nr = CODE_LABEL_NUMBER (insn); |
3368 | struct elim_table *ep; | |
3369 | ||
3370 | num_not_at_initial_offset = 0; | |
3371 | for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++) | |
3372 | { | |
3373 | ep->offset = ep->previous_offset = offsets_at[label_nr][i]; | |
3374 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3375 | num_not_at_initial_offset++; | |
3376 | } | |
3377 | } | |
3378 | ||
09dd1133 BS |
3379 | /* See if anything that happened changes which eliminations are valid. |
3380 | For example, on the Sparc, whether or not the frame pointer can | |
3381 | be eliminated can depend on what registers have been used. We need | |
3382 | not check some conditions again (such as flag_omit_frame_pointer) | |
3383 | since they can't have changed. */ | |
3384 | ||
3385 | static void | |
3386 | update_eliminables (pset) | |
3387 | HARD_REG_SET *pset; | |
3388 | { | |
3389 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
3390 | int previous_frame_pointer_needed = frame_pointer_needed; | |
3391 | #endif | |
3392 | struct elim_table *ep; | |
3393 | ||
3394 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3395 | if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED) | |
3396 | #ifdef ELIMINABLE_REGS | |
3397 | || ! CAN_ELIMINATE (ep->from, ep->to) | |
3398 | #endif | |
3399 | ) | |
3400 | ep->can_eliminate = 0; | |
3401 | ||
3402 | /* Look for the case where we have discovered that we can't replace | |
3403 | register A with register B and that means that we will now be | |
3404 | trying to replace register A with register C. This means we can | |
3405 | no longer replace register C with register B and we need to disable | |
3406 | such an elimination, if it exists. This occurs often with A == ap, | |
3407 | B == sp, and C == fp. */ | |
3408 | ||
3409 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3410 | { | |
3411 | struct elim_table *op; | |
b3694847 | 3412 | int new_to = -1; |
09dd1133 BS |
3413 | |
3414 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3415 | { | |
3416 | /* Find the current elimination for ep->from, if there is a | |
3417 | new one. */ | |
3418 | for (op = reg_eliminate; | |
3419 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3420 | if (op->from == ep->from && op->can_eliminate) | |
3421 | { | |
3422 | new_to = op->to; | |
3423 | break; | |
3424 | } | |
3425 | ||
3426 | /* See if there is an elimination of NEW_TO -> EP->TO. If so, | |
3427 | disable it. */ | |
3428 | for (op = reg_eliminate; | |
3429 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3430 | if (op->from == new_to && op->to == ep->to) | |
3431 | op->can_eliminate = 0; | |
3432 | } | |
3433 | } | |
3434 | ||
3435 | /* See if any registers that we thought we could eliminate the previous | |
3436 | time are no longer eliminable. If so, something has changed and we | |
3437 | must spill the register. Also, recompute the number of eliminable | |
3438 | registers and see if the frame pointer is needed; it is if there is | |
3439 | no elimination of the frame pointer that we can perform. */ | |
3440 | ||
3441 | frame_pointer_needed = 1; | |
3442 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3443 | { | |
3444 | if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM | |
3445 | && ep->to != HARD_FRAME_POINTER_REGNUM) | |
3446 | frame_pointer_needed = 0; | |
3447 | ||
3448 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3449 | { | |
3450 | ep->can_eliminate_previous = 0; | |
3451 | SET_HARD_REG_BIT (*pset, ep->from); | |
3452 | num_eliminable--; | |
3453 | } | |
3454 | } | |
3455 | ||
3456 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
3457 | /* If we didn't need a frame pointer last time, but we do now, spill | |
3458 | the hard frame pointer. */ | |
3459 | if (frame_pointer_needed && ! previous_frame_pointer_needed) | |
3460 | SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM); | |
3461 | #endif | |
3462 | } | |
3463 | ||
3464 | /* Initialize the table of registers to eliminate. */ | |
1d813780 | 3465 | |
09dd1133 BS |
3466 | static void |
3467 | init_elim_table () | |
3468 | { | |
3469 | struct elim_table *ep; | |
590cf94d KG |
3470 | #ifdef ELIMINABLE_REGS |
3471 | struct elim_table_1 *ep1; | |
3472 | #endif | |
09dd1133 | 3473 | |
590cf94d | 3474 | if (!reg_eliminate) |
ad85216e | 3475 | reg_eliminate = (struct elim_table *) |
1d7254c5 | 3476 | xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS); |
05d10675 | 3477 | |
09dd1133 BS |
3478 | /* Does this function require a frame pointer? */ |
3479 | ||
3480 | frame_pointer_needed = (! flag_omit_frame_pointer | |
3481 | #ifdef EXIT_IGNORE_STACK | |
3482 | /* ?? If EXIT_IGNORE_STACK is set, we will not save | |
3483 | and restore sp for alloca. So we can't eliminate | |
3484 | the frame pointer in that case. At some point, | |
3485 | we should improve this by emitting the | |
3486 | sp-adjusting insns for this case. */ | |
3487 | || (current_function_calls_alloca | |
3488 | && EXIT_IGNORE_STACK) | |
3489 | #endif | |
3490 | || FRAME_POINTER_REQUIRED); | |
3491 | ||
3492 | num_eliminable = 0; | |
3493 | ||
3494 | #ifdef ELIMINABLE_REGS | |
590cf94d KG |
3495 | for (ep = reg_eliminate, ep1 = reg_eliminate_1; |
3496 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++) | |
09dd1133 | 3497 | { |
590cf94d KG |
3498 | ep->from = ep1->from; |
3499 | ep->to = ep1->to; | |
09dd1133 BS |
3500 | ep->can_eliminate = ep->can_eliminate_previous |
3501 | = (CAN_ELIMINATE (ep->from, ep->to) | |
3502 | && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed)); | |
3503 | } | |
3504 | #else | |
590cf94d KG |
3505 | reg_eliminate[0].from = reg_eliminate_1[0].from; |
3506 | reg_eliminate[0].to = reg_eliminate_1[0].to; | |
09dd1133 BS |
3507 | reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous |
3508 | = ! frame_pointer_needed; | |
3509 | #endif | |
3510 | ||
3511 | /* Count the number of eliminable registers and build the FROM and TO | |
3512 | REG rtx's. Note that code in gen_rtx will cause, e.g., | |
3513 | gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. | |
3514 | We depend on this. */ | |
3515 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3516 | { | |
3517 | num_eliminable += ep->can_eliminate; | |
3518 | ep->from_rtx = gen_rtx_REG (Pmode, ep->from); | |
3519 | ep->to_rtx = gen_rtx_REG (Pmode, ep->to); | |
3520 | } | |
3521 | } | |
32131a9c RK |
3522 | \f |
3523 | /* Kick all pseudos out of hard register REGNO. | |
32131a9c RK |
3524 | |
3525 | If CANT_ELIMINATE is nonzero, it means that we are doing this spill | |
3526 | because we found we can't eliminate some register. In the case, no pseudos | |
3527 | are allowed to be in the register, even if they are only in a block that | |
3528 | doesn't require spill registers, unlike the case when we are spilling this | |
3529 | hard reg to produce another spill register. | |
3530 | ||
3531 | Return nonzero if any pseudos needed to be kicked out. */ | |
3532 | ||
03acd8f8 | 3533 | static void |
e04ca094 | 3534 | spill_hard_reg (regno, cant_eliminate) |
770ae6cc | 3535 | unsigned int regno; |
32131a9c RK |
3536 | int cant_eliminate; |
3537 | { | |
b3694847 | 3538 | int i; |
32131a9c | 3539 | |
9ff3516a | 3540 | if (cant_eliminate) |
03acd8f8 BS |
3541 | { |
3542 | SET_HARD_REG_BIT (bad_spill_regs_global, regno); | |
3543 | regs_ever_live[regno] = 1; | |
3544 | } | |
9ff3516a | 3545 | |
32131a9c RK |
3546 | /* Spill every pseudo reg that was allocated to this reg |
3547 | or to something that overlaps this reg. */ | |
3548 | ||
3549 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3550 | if (reg_renumber[i] >= 0 | |
770ae6cc RK |
3551 | && (unsigned int) reg_renumber[i] <= regno |
3552 | && ((unsigned int) reg_renumber[i] | |
3553 | + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i], | |
32131a9c RK |
3554 | PSEUDO_REGNO_MODE (i)) |
3555 | > regno)) | |
f5d8c9f4 | 3556 | SET_REGNO_REG_SET (&spilled_pseudos, i); |
03acd8f8 | 3557 | } |
32131a9c | 3558 | |
03acd8f8 BS |
3559 | /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET |
3560 | from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */ | |
770ae6cc | 3561 | |
03acd8f8 BS |
3562 | static void |
3563 | ior_hard_reg_set (set1, set2) | |
3564 | HARD_REG_SET *set1, *set2; | |
3565 | { | |
3566 | IOR_HARD_REG_SET (*set1, *set2); | |
3567 | } | |
05d10675 | 3568 | |
03acd8f8 BS |
3569 | /* After find_reload_regs has been run for all insn that need reloads, |
3570 | and/or spill_hard_regs was called, this function is used to actually | |
3571 | spill pseudo registers and try to reallocate them. It also sets up the | |
3572 | spill_regs array for use by choose_reload_regs. */ | |
a8fdc208 | 3573 | |
03acd8f8 | 3574 | static int |
e04ca094 | 3575 | finish_spills (global) |
03acd8f8 | 3576 | int global; |
03acd8f8 BS |
3577 | { |
3578 | struct insn_chain *chain; | |
3579 | int something_changed = 0; | |
3580 | int i; | |
3581 | ||
3582 | /* Build the spill_regs array for the function. */ | |
3583 | /* If there are some registers still to eliminate and one of the spill regs | |
3584 | wasn't ever used before, additional stack space may have to be | |
3585 | allocated to store this register. Thus, we may have changed the offset | |
3586 | between the stack and frame pointers, so mark that something has changed. | |
32131a9c | 3587 | |
03acd8f8 BS |
3588 | One might think that we need only set VAL to 1 if this is a call-used |
3589 | register. However, the set of registers that must be saved by the | |
3590 | prologue is not identical to the call-used set. For example, the | |
3591 | register used by the call insn for the return PC is a call-used register, | |
3592 | but must be saved by the prologue. */ | |
3593 | ||
3594 | n_spills = 0; | |
3595 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3596 | if (TEST_HARD_REG_BIT (used_spill_regs, i)) | |
3597 | { | |
3598 | spill_reg_order[i] = n_spills; | |
3599 | spill_regs[n_spills++] = i; | |
3600 | if (num_eliminable && ! regs_ever_live[i]) | |
3601 | something_changed = 1; | |
3602 | regs_ever_live[i] = 1; | |
3603 | } | |
3604 | else | |
3605 | spill_reg_order[i] = -1; | |
3606 | ||
efc9bd41 RK |
3607 | EXECUTE_IF_SET_IN_REG_SET |
3608 | (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, | |
3609 | { | |
3610 | /* Record the current hard register the pseudo is allocated to in | |
3611 | pseudo_previous_regs so we avoid reallocating it to the same | |
3612 | hard reg in a later pass. */ | |
3613 | if (reg_renumber[i] < 0) | |
3614 | abort (); | |
3615 | ||
3616 | SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]); | |
3617 | /* Mark it as no longer having a hard register home. */ | |
3618 | reg_renumber[i] = -1; | |
3619 | /* We will need to scan everything again. */ | |
3620 | something_changed = 1; | |
3621 | }); | |
7609e720 | 3622 | |
03acd8f8 BS |
3623 | /* Retry global register allocation if possible. */ |
3624 | if (global) | |
3625 | { | |
961192e1 | 3626 | memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET)); |
03acd8f8 BS |
3627 | /* For every insn that needs reloads, set the registers used as spill |
3628 | regs in pseudo_forbidden_regs for every pseudo live across the | |
3629 | insn. */ | |
3630 | for (chain = insns_need_reload; chain; chain = chain->next_need_reload) | |
3631 | { | |
3632 | EXECUTE_IF_SET_IN_REG_SET | |
239a0f5b | 3633 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, |
03acd8f8 BS |
3634 | { |
3635 | ior_hard_reg_set (pseudo_forbidden_regs + i, | |
3636 | &chain->used_spill_regs); | |
3637 | }); | |
3638 | EXECUTE_IF_SET_IN_REG_SET | |
239a0f5b | 3639 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, |
03acd8f8 BS |
3640 | { |
3641 | ior_hard_reg_set (pseudo_forbidden_regs + i, | |
3642 | &chain->used_spill_regs); | |
3643 | }); | |
3644 | } | |
7609e720 | 3645 | |
03acd8f8 BS |
3646 | /* Retry allocating the spilled pseudos. For each reg, merge the |
3647 | various reg sets that indicate which hard regs can't be used, | |
3648 | and call retry_global_alloc. | |
05d10675 | 3649 | We change spill_pseudos here to only contain pseudos that did not |
03acd8f8 BS |
3650 | get a new hard register. */ |
3651 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3652 | if (reg_old_renumber[i] != reg_renumber[i]) | |
32131a9c | 3653 | { |
03acd8f8 BS |
3654 | HARD_REG_SET forbidden; |
3655 | COPY_HARD_REG_SET (forbidden, bad_spill_regs_global); | |
3656 | IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]); | |
3657 | IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]); | |
3658 | retry_global_alloc (i, forbidden); | |
3659 | if (reg_renumber[i] >= 0) | |
f5d8c9f4 | 3660 | CLEAR_REGNO_REG_SET (&spilled_pseudos, i); |
32131a9c | 3661 | } |
03acd8f8 | 3662 | } |
7609e720 | 3663 | |
03acd8f8 BS |
3664 | /* Fix up the register information in the insn chain. |
3665 | This involves deleting those of the spilled pseudos which did not get | |
3666 | a new hard register home from the live_{before,after} sets. */ | |
7609e720 BS |
3667 | for (chain = reload_insn_chain; chain; chain = chain->next) |
3668 | { | |
03acd8f8 BS |
3669 | HARD_REG_SET used_by_pseudos; |
3670 | HARD_REG_SET used_by_pseudos2; | |
3671 | ||
239a0f5b BS |
3672 | AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos); |
3673 | AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos); | |
03acd8f8 BS |
3674 | |
3675 | /* Mark any unallocated hard regs as available for spills. That | |
3676 | makes inheritance work somewhat better. */ | |
3677 | if (chain->need_reload) | |
3678 | { | |
239a0f5b BS |
3679 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); |
3680 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
03acd8f8 BS |
3681 | IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2); |
3682 | ||
3683 | /* Save the old value for the sanity test below. */ | |
3684 | COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs); | |
3685 | ||
239a0f5b BS |
3686 | compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout); |
3687 | compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set); | |
03acd8f8 BS |
3688 | COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos); |
3689 | AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs); | |
3690 | ||
3691 | /* Make sure we only enlarge the set. */ | |
3692 | GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok); | |
3693 | abort (); | |
3694 | ok:; | |
3695 | } | |
7609e720 | 3696 | } |
03acd8f8 BS |
3697 | |
3698 | /* Let alter_reg modify the reg rtx's for the modified pseudos. */ | |
3699 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3700 | { | |
3701 | int regno = reg_renumber[i]; | |
3702 | if (reg_old_renumber[i] == regno) | |
3703 | continue; | |
05d10675 | 3704 | |
03acd8f8 BS |
3705 | alter_reg (i, reg_old_renumber[i]); |
3706 | reg_old_renumber[i] = regno; | |
e04ca094 | 3707 | if (rtl_dump_file) |
03acd8f8 BS |
3708 | { |
3709 | if (regno == -1) | |
e04ca094 | 3710 | fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i); |
03acd8f8 | 3711 | else |
e04ca094 | 3712 | fprintf (rtl_dump_file, " Register %d now in %d.\n\n", |
03acd8f8 BS |
3713 | i, reg_renumber[i]); |
3714 | } | |
3715 | } | |
3716 | ||
3717 | return something_changed; | |
7609e720 | 3718 | } |
32131a9c | 3719 | \f |
05d10675 | 3720 | /* Find all paradoxical subregs within X and update reg_max_ref_width. |
56f58d3a RK |
3721 | Also mark any hard registers used to store user variables as |
3722 | forbidden from being used for spill registers. */ | |
32131a9c RK |
3723 | |
3724 | static void | |
3725 | scan_paradoxical_subregs (x) | |
b3694847 | 3726 | rtx x; |
32131a9c | 3727 | { |
b3694847 SS |
3728 | int i; |
3729 | const char *fmt; | |
3730 | enum rtx_code code = GET_CODE (x); | |
32131a9c RK |
3731 | |
3732 | switch (code) | |
3733 | { | |
56f58d3a | 3734 | case REG: |
03acd8f8 | 3735 | #if 0 |
e9a25f70 | 3736 | if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER |
f95182a4 | 3737 | && REG_USERVAR_P (x)) |
03acd8f8 BS |
3738 | SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x)); |
3739 | #endif | |
56f58d3a RK |
3740 | return; |
3741 | ||
32131a9c RK |
3742 | case CONST_INT: |
3743 | case CONST: | |
3744 | case SYMBOL_REF: | |
3745 | case LABEL_REF: | |
3746 | case CONST_DOUBLE: | |
3747 | case CC0: | |
3748 | case PC: | |
32131a9c RK |
3749 | case USE: |
3750 | case CLOBBER: | |
3751 | return; | |
3752 | ||
3753 | case SUBREG: | |
3754 | if (GET_CODE (SUBREG_REG (x)) == REG | |
3755 | && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
3756 | reg_max_ref_width[REGNO (SUBREG_REG (x))] | |
3757 | = GET_MODE_SIZE (GET_MODE (x)); | |
3758 | return; | |
05d10675 | 3759 | |
e9a25f70 JL |
3760 | default: |
3761 | break; | |
32131a9c RK |
3762 | } |
3763 | ||
3764 | fmt = GET_RTX_FORMAT (code); | |
3765 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3766 | { | |
3767 | if (fmt[i] == 'e') | |
3768 | scan_paradoxical_subregs (XEXP (x, i)); | |
3769 | else if (fmt[i] == 'E') | |
3770 | { | |
b3694847 | 3771 | int j; |
1d7254c5 | 3772 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
32131a9c RK |
3773 | scan_paradoxical_subregs (XVECEXP (x, i, j)); |
3774 | } | |
3775 | } | |
3776 | } | |
3777 | \f | |
32131a9c RK |
3778 | /* Reload pseudo-registers into hard regs around each insn as needed. |
3779 | Additional register load insns are output before the insn that needs it | |
3780 | and perhaps store insns after insns that modify the reloaded pseudo reg. | |
3781 | ||
3782 | reg_last_reload_reg and reg_reloaded_contents keep track of | |
d08ea79f | 3783 | which registers are already available in reload registers. |
32131a9c RK |
3784 | We update these for the reloads that we perform, |
3785 | as the insns are scanned. */ | |
3786 | ||
3787 | static void | |
e04ca094 | 3788 | reload_as_needed (live_known) |
32131a9c RK |
3789 | int live_known; |
3790 | { | |
7609e720 | 3791 | struct insn_chain *chain; |
553687c9 | 3792 | #if defined (AUTO_INC_DEC) |
b3694847 | 3793 | int i; |
973838fd | 3794 | #endif |
32131a9c | 3795 | rtx x; |
32131a9c | 3796 | |
961192e1 JM |
3797 | memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx); |
3798 | memset ((char *) spill_reg_store, 0, sizeof spill_reg_store); | |
ff154f78 MM |
3799 | reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx)); |
3800 | reg_has_output_reload = (char *) xmalloc (max_regno); | |
e6e52be0 | 3801 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
32131a9c | 3802 | |
1f3b1e1a | 3803 | set_initial_elim_offsets (); |
32131a9c | 3804 | |
7609e720 | 3805 | for (chain = reload_insn_chain; chain; chain = chain->next) |
32131a9c | 3806 | { |
03acd8f8 | 3807 | rtx prev; |
7609e720 BS |
3808 | rtx insn = chain->insn; |
3809 | rtx old_next = NEXT_INSN (insn); | |
32131a9c RK |
3810 | |
3811 | /* If we pass a label, copy the offsets from the label information | |
3812 | into the current offsets of each elimination. */ | |
3813 | if (GET_CODE (insn) == CODE_LABEL) | |
1f3b1e1a | 3814 | set_offsets_for_label (insn); |
32131a9c | 3815 | |
2c3c49de | 3816 | else if (INSN_P (insn)) |
32131a9c | 3817 | { |
0639444f | 3818 | rtx oldpat = PATTERN (insn); |
32131a9c | 3819 | |
2758481d RS |
3820 | /* If this is a USE and CLOBBER of a MEM, ensure that any |
3821 | references to eliminable registers have been removed. */ | |
3822 | ||
3823 | if ((GET_CODE (PATTERN (insn)) == USE | |
3824 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
3825 | && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM) | |
3826 | XEXP (XEXP (PATTERN (insn), 0), 0) | |
3827 | = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), | |
29ae5012 | 3828 | GET_MODE (XEXP (PATTERN (insn), 0)), |
1914f5da | 3829 | NULL_RTX); |
2758481d | 3830 | |
32131a9c RK |
3831 | /* If we need to do register elimination processing, do so. |
3832 | This might delete the insn, in which case we are done. */ | |
2b49ee39 | 3833 | if ((num_eliminable || num_eliminable_invariants) && chain->need_elim) |
32131a9c RK |
3834 | { |
3835 | eliminate_regs_in_insn (insn, 1); | |
3836 | if (GET_CODE (insn) == NOTE) | |
cb2afeb3 R |
3837 | { |
3838 | update_eliminable_offsets (); | |
3839 | continue; | |
3840 | } | |
32131a9c RK |
3841 | } |
3842 | ||
7609e720 BS |
3843 | /* If need_elim is nonzero but need_reload is zero, one might think |
3844 | that we could simply set n_reloads to 0. However, find_reloads | |
3845 | could have done some manipulation of the insn (such as swapping | |
3846 | commutative operands), and these manipulations are lost during | |
3847 | the first pass for every insn that needs register elimination. | |
3848 | So the actions of find_reloads must be redone here. */ | |
3849 | ||
03acd8f8 BS |
3850 | if (! chain->need_elim && ! chain->need_reload |
3851 | && ! chain->need_operand_change) | |
32131a9c RK |
3852 | n_reloads = 0; |
3853 | /* First find the pseudo regs that must be reloaded for this insn. | |
3854 | This info is returned in the tables reload_... (see reload.h). | |
3855 | Also modify the body of INSN by substituting RELOAD | |
3856 | rtx's for those pseudo regs. */ | |
3857 | else | |
3858 | { | |
961192e1 | 3859 | memset (reg_has_output_reload, 0, max_regno); |
32131a9c RK |
3860 | CLEAR_HARD_REG_SET (reg_is_output_reload); |
3861 | ||
3862 | find_reloads (insn, 1, spill_indirect_levels, live_known, | |
3863 | spill_reg_order); | |
3864 | } | |
3865 | ||
3866 | if (n_reloads > 0) | |
3867 | { | |
cb2afeb3 | 3868 | rtx next = NEXT_INSN (insn); |
3c3eeea6 | 3869 | rtx p; |
32131a9c | 3870 | |
cb2afeb3 R |
3871 | prev = PREV_INSN (insn); |
3872 | ||
32131a9c RK |
3873 | /* Now compute which reload regs to reload them into. Perhaps |
3874 | reusing reload regs from previous insns, or else output | |
3875 | load insns to reload them. Maybe output store insns too. | |
3876 | Record the choices of reload reg in reload_reg_rtx. */ | |
03acd8f8 | 3877 | choose_reload_regs (chain); |
32131a9c | 3878 | |
05d10675 | 3879 | /* Merge any reloads that we didn't combine for fear of |
546b63fb RK |
3880 | increasing the number of spill registers needed but now |
3881 | discover can be safely merged. */ | |
f95182a4 ILT |
3882 | if (SMALL_REGISTER_CLASSES) |
3883 | merge_assigned_reloads (insn); | |
546b63fb | 3884 | |
32131a9c RK |
3885 | /* Generate the insns to reload operands into or out of |
3886 | their reload regs. */ | |
e04ca094 | 3887 | emit_reload_insns (chain); |
32131a9c RK |
3888 | |
3889 | /* Substitute the chosen reload regs from reload_reg_rtx | |
3890 | into the insn's body (or perhaps into the bodies of other | |
3891 | load and store insn that we just made for reloading | |
3892 | and that we moved the structure into). */ | |
f759eb8b | 3893 | subst_reloads (insn); |
3c3eeea6 RK |
3894 | |
3895 | /* If this was an ASM, make sure that all the reload insns | |
3896 | we have generated are valid. If not, give an error | |
3897 | and delete them. */ | |
3898 | ||
3899 | if (asm_noperands (PATTERN (insn)) >= 0) | |
3900 | for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) | |
2c3c49de | 3901 | if (p != insn && INSN_P (p) |
3c3eeea6 | 3902 | && (recog_memoized (p) < 0 |
0eadeb15 | 3903 | || (extract_insn (p), ! constrain_operands (1)))) |
3c3eeea6 RK |
3904 | { |
3905 | error_for_asm (insn, | |
3906 | "`asm' operand requires impossible reload"); | |
ca6c03ca | 3907 | delete_insn (p); |
3c3eeea6 | 3908 | } |
32131a9c | 3909 | } |
5d7ef82a BS |
3910 | |
3911 | if (num_eliminable && chain->need_elim) | |
3912 | update_eliminable_offsets (); | |
3913 | ||
32131a9c RK |
3914 | /* Any previously reloaded spilled pseudo reg, stored in this insn, |
3915 | is no longer validly lying around to save a future reload. | |
3916 | Note that this does not detect pseudos that were reloaded | |
3917 | for this insn in order to be stored in | |
3918 | (obeying register constraints). That is correct; such reload | |
3919 | registers ARE still valid. */ | |
84832317 | 3920 | note_stores (oldpat, forget_old_reloads_1, NULL); |
32131a9c RK |
3921 | |
3922 | /* There may have been CLOBBER insns placed after INSN. So scan | |
3923 | between INSN and NEXT and use them to forget old reloads. */ | |
7609e720 | 3924 | for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x)) |
32131a9c | 3925 | if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER) |
84832317 | 3926 | note_stores (PATTERN (x), forget_old_reloads_1, NULL); |
32131a9c RK |
3927 | |
3928 | #ifdef AUTO_INC_DEC | |
cb2afeb3 R |
3929 | /* Likewise for regs altered by auto-increment in this insn. |
3930 | REG_INC notes have been changed by reloading: | |
3931 | find_reloads_address_1 records substitutions for them, | |
3932 | which have been performed by subst_reloads above. */ | |
3933 | for (i = n_reloads - 1; i >= 0; i--) | |
3934 | { | |
eceef4c9 | 3935 | rtx in_reg = rld[i].in_reg; |
cb2afeb3 R |
3936 | if (in_reg) |
3937 | { | |
3938 | enum rtx_code code = GET_CODE (in_reg); | |
3939 | /* PRE_INC / PRE_DEC will have the reload register ending up | |
3940 | with the same value as the stack slot, but that doesn't | |
3941 | hold true for POST_INC / POST_DEC. Either we have to | |
3942 | convert the memory access to a true POST_INC / POST_DEC, | |
3943 | or we can't use the reload register for inheritance. */ | |
3944 | if ((code == POST_INC || code == POST_DEC) | |
3945 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 3946 | REGNO (rld[i].reg_rtx)) |
04bbb0c5 JW |
3947 | /* Make sure it is the inc/dec pseudo, and not |
3948 | some other (e.g. output operand) pseudo. */ | |
eceef4c9 | 3949 | && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
04bbb0c5 | 3950 | == REGNO (XEXP (in_reg, 0)))) |
05d10675 | 3951 | |
cb2afeb3 | 3952 | { |
eceef4c9 | 3953 | rtx reload_reg = rld[i].reg_rtx; |
cb2afeb3 R |
3954 | enum machine_mode mode = GET_MODE (reload_reg); |
3955 | int n = 0; | |
3956 | rtx p; | |
3957 | ||
3958 | for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p)) | |
3959 | { | |
3960 | /* We really want to ignore REG_INC notes here, so | |
3961 | use PATTERN (p) as argument to reg_set_p . */ | |
3962 | if (reg_set_p (reload_reg, PATTERN (p))) | |
3963 | break; | |
4b983fdc | 3964 | n = count_occurrences (PATTERN (p), reload_reg, 0); |
cb2afeb3 R |
3965 | if (! n) |
3966 | continue; | |
3967 | if (n == 1) | |
f67c2384 JL |
3968 | { |
3969 | n = validate_replace_rtx (reload_reg, | |
3970 | gen_rtx (code, mode, | |
3971 | reload_reg), | |
3972 | p); | |
3973 | ||
3974 | /* We must also verify that the constraints | |
3975 | are met after the replacement. */ | |
3976 | extract_insn (p); | |
3977 | if (n) | |
3978 | n = constrain_operands (1); | |
3979 | else | |
3980 | break; | |
3981 | ||
3982 | /* If the constraints were not met, then | |
3983 | undo the replacement. */ | |
3984 | if (!n) | |
3985 | { | |
3986 | validate_replace_rtx (gen_rtx (code, mode, | |
3987 | reload_reg), | |
3988 | reload_reg, p); | |
3989 | break; | |
3990 | } | |
05d10675 | 3991 | |
f67c2384 | 3992 | } |
cb2afeb3 R |
3993 | break; |
3994 | } | |
3995 | if (n == 1) | |
02eb1393 R |
3996 | { |
3997 | REG_NOTES (p) | |
3998 | = gen_rtx_EXPR_LIST (REG_INC, reload_reg, | |
3999 | REG_NOTES (p)); | |
4000 | /* Mark this as having an output reload so that the | |
4001 | REG_INC processing code below won't invalidate | |
4002 | the reload for inheritance. */ | |
4003 | SET_HARD_REG_BIT (reg_is_output_reload, | |
4004 | REGNO (reload_reg)); | |
4005 | reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; | |
4006 | } | |
cb2afeb3 | 4007 | else |
1d7254c5 | 4008 | forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX, |
84832317 | 4009 | NULL); |
cb2afeb3 | 4010 | } |
02eb1393 R |
4011 | else if ((code == PRE_INC || code == PRE_DEC) |
4012 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 4013 | REGNO (rld[i].reg_rtx)) |
02eb1393 R |
4014 | /* Make sure it is the inc/dec pseudo, and not |
4015 | some other (e.g. output operand) pseudo. */ | |
eceef4c9 | 4016 | && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
02eb1393 R |
4017 | == REGNO (XEXP (in_reg, 0)))) |
4018 | { | |
4019 | SET_HARD_REG_BIT (reg_is_output_reload, | |
eceef4c9 | 4020 | REGNO (rld[i].reg_rtx)); |
02eb1393 R |
4021 | reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; |
4022 | } | |
cb2afeb3 R |
4023 | } |
4024 | } | |
02eb1393 R |
4025 | /* If a pseudo that got a hard register is auto-incremented, |
4026 | we must purge records of copying it into pseudos without | |
4027 | hard registers. */ | |
32131a9c RK |
4028 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) |
4029 | if (REG_NOTE_KIND (x) == REG_INC) | |
4030 | { | |
4031 | /* See if this pseudo reg was reloaded in this insn. | |
4032 | If so, its last-reload info is still valid | |
4033 | because it is based on this insn's reload. */ | |
4034 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 4035 | if (rld[i].out == XEXP (x, 0)) |
32131a9c RK |
4036 | break; |
4037 | ||
08fb99fa | 4038 | if (i == n_reloads) |
84832317 | 4039 | forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL); |
32131a9c RK |
4040 | } |
4041 | #endif | |
4042 | } | |
4043 | /* A reload reg's contents are unknown after a label. */ | |
4044 | if (GET_CODE (insn) == CODE_LABEL) | |
e6e52be0 | 4045 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
32131a9c RK |
4046 | |
4047 | /* Don't assume a reload reg is still good after a call insn | |
4048 | if it is a call-used reg. */ | |
546b63fb | 4049 | else if (GET_CODE (insn) == CALL_INSN) |
e6e52be0 | 4050 | AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set); |
32131a9c | 4051 | } |
ff154f78 MM |
4052 | |
4053 | /* Clean up. */ | |
4054 | free (reg_last_reload_reg); | |
4055 | free (reg_has_output_reload); | |
32131a9c RK |
4056 | } |
4057 | ||
4058 | /* Discard all record of any value reloaded from X, | |
4059 | or reloaded in X from someplace else; | |
4060 | unless X is an output reload reg of the current insn. | |
4061 | ||
4062 | X may be a hard reg (the reload reg) | |
4063 | or it may be a pseudo reg that was reloaded from. */ | |
4064 | ||
4065 | static void | |
84832317 | 4066 | forget_old_reloads_1 (x, ignored, data) |
32131a9c | 4067 | rtx x; |
487a6e06 | 4068 | rtx ignored ATTRIBUTE_UNUSED; |
84832317 | 4069 | void *data ATTRIBUTE_UNUSED; |
32131a9c | 4070 | { |
770ae6cc RK |
4071 | unsigned int regno; |
4072 | unsigned int nr; | |
0a2e51a9 RS |
4073 | int offset = 0; |
4074 | ||
ddef6bc7 JJ |
4075 | /* note_stores does give us subregs of hard regs, |
4076 | subreg_regno_offset will abort if it is not a hard reg. */ | |
0a2e51a9 RS |
4077 | while (GET_CODE (x) == SUBREG) |
4078 | { | |
ddef6bc7 JJ |
4079 | offset += subreg_regno_offset (REGNO (SUBREG_REG (x)), |
4080 | GET_MODE (SUBREG_REG (x)), | |
4081 | SUBREG_BYTE (x), | |
4082 | GET_MODE (x)); | |
0a2e51a9 RS |
4083 | x = SUBREG_REG (x); |
4084 | } | |
32131a9c RK |
4085 | |
4086 | if (GET_CODE (x) != REG) | |
4087 | return; | |
4088 | ||
0a2e51a9 | 4089 | regno = REGNO (x) + offset; |
32131a9c RK |
4090 | |
4091 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4092 | nr = 1; | |
4093 | else | |
4094 | { | |
770ae6cc RK |
4095 | unsigned int i; |
4096 | ||
32131a9c RK |
4097 | nr = HARD_REGNO_NREGS (regno, GET_MODE (x)); |
4098 | /* Storing into a spilled-reg invalidates its contents. | |
4099 | This can happen if a block-local pseudo is allocated to that reg | |
4100 | and it wasn't spilled because this block's total need is 0. | |
4101 | Then some insn might have an optional reload and use this reg. */ | |
4102 | for (i = 0; i < nr; i++) | |
e6e52be0 R |
4103 | /* But don't do this if the reg actually serves as an output |
4104 | reload reg in the current instruction. */ | |
4105 | if (n_reloads == 0 | |
4106 | || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)) | |
5d77a50c BS |
4107 | { |
4108 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i); | |
4109 | spill_reg_store[regno + i] = 0; | |
4110 | } | |
32131a9c RK |
4111 | } |
4112 | ||
4113 | /* Since value of X has changed, | |
4114 | forget any value previously copied from it. */ | |
4115 | ||
4116 | while (nr-- > 0) | |
4117 | /* But don't forget a copy if this is the output reload | |
4118 | that establishes the copy's validity. */ | |
4119 | if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0) | |
4120 | reg_last_reload_reg[regno + nr] = 0; | |
4121 | } | |
4122 | \f | |
32131a9c RK |
4123 | /* The following HARD_REG_SETs indicate when each hard register is |
4124 | used for a reload of various parts of the current insn. */ | |
4125 | ||
9e3a9cf2 BS |
4126 | /* If reg is unavailable for all reloads. */ |
4127 | static HARD_REG_SET reload_reg_unavailable; | |
32131a9c RK |
4128 | /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ |
4129 | static HARD_REG_SET reload_reg_used; | |
546b63fb RK |
4130 | /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ |
4131 | static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4132 | /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */ |
4133 | static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4134 | /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ |
4135 | static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4136 | /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */ |
4137 | static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4138 | /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ |
4139 | static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; | |
4140 | /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ | |
4141 | static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; | |
32131a9c RK |
4142 | /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ |
4143 | static HARD_REG_SET reload_reg_used_in_op_addr; | |
893bc853 RK |
4144 | /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */ |
4145 | static HARD_REG_SET reload_reg_used_in_op_addr_reload; | |
546b63fb RK |
4146 | /* If reg is in use for a RELOAD_FOR_INSN reload. */ |
4147 | static HARD_REG_SET reload_reg_used_in_insn; | |
4148 | /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ | |
4149 | static HARD_REG_SET reload_reg_used_in_other_addr; | |
32131a9c RK |
4150 | |
4151 | /* If reg is in use as a reload reg for any sort of reload. */ | |
4152 | static HARD_REG_SET reload_reg_used_at_all; | |
4153 | ||
be7ae2a4 RK |
4154 | /* If reg is use as an inherited reload. We just mark the first register |
4155 | in the group. */ | |
4156 | static HARD_REG_SET reload_reg_used_for_inherit; | |
4157 | ||
f1db3576 JL |
4158 | /* Records which hard regs are used in any way, either as explicit use or |
4159 | by being allocated to a pseudo during any point of the current insn. */ | |
4160 | static HARD_REG_SET reg_used_in_insn; | |
297927a8 | 4161 | |
546b63fb RK |
4162 | /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and |
4163 | TYPE. MODE is used to indicate how many consecutive regs are | |
4164 | actually used. */ | |
32131a9c RK |
4165 | |
4166 | static void | |
546b63fb | 4167 | mark_reload_reg_in_use (regno, opnum, type, mode) |
770ae6cc | 4168 | unsigned int regno; |
546b63fb RK |
4169 | int opnum; |
4170 | enum reload_type type; | |
32131a9c RK |
4171 | enum machine_mode mode; |
4172 | { | |
770ae6cc RK |
4173 | unsigned int nregs = HARD_REGNO_NREGS (regno, mode); |
4174 | unsigned int i; | |
32131a9c RK |
4175 | |
4176 | for (i = regno; i < nregs + regno; i++) | |
4177 | { | |
546b63fb | 4178 | switch (type) |
32131a9c RK |
4179 | { |
4180 | case RELOAD_OTHER: | |
4181 | SET_HARD_REG_BIT (reload_reg_used, i); | |
4182 | break; | |
4183 | ||
546b63fb RK |
4184 | case RELOAD_FOR_INPUT_ADDRESS: |
4185 | SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); | |
32131a9c RK |
4186 | break; |
4187 | ||
47c8cf91 ILT |
4188 | case RELOAD_FOR_INPADDR_ADDRESS: |
4189 | SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i); | |
4190 | break; | |
4191 | ||
546b63fb RK |
4192 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4193 | SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); | |
32131a9c RK |
4194 | break; |
4195 | ||
47c8cf91 ILT |
4196 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4197 | SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i); | |
4198 | break; | |
4199 | ||
32131a9c RK |
4200 | case RELOAD_FOR_OPERAND_ADDRESS: |
4201 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); | |
4202 | break; | |
4203 | ||
893bc853 RK |
4204 | case RELOAD_FOR_OPADDR_ADDR: |
4205 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i); | |
4206 | break; | |
4207 | ||
546b63fb RK |
4208 | case RELOAD_FOR_OTHER_ADDRESS: |
4209 | SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i); | |
4210 | break; | |
4211 | ||
32131a9c | 4212 | case RELOAD_FOR_INPUT: |
546b63fb | 4213 | SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); |
32131a9c RK |
4214 | break; |
4215 | ||
4216 | case RELOAD_FOR_OUTPUT: | |
546b63fb RK |
4217 | SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); |
4218 | break; | |
4219 | ||
4220 | case RELOAD_FOR_INSN: | |
4221 | SET_HARD_REG_BIT (reload_reg_used_in_insn, i); | |
32131a9c RK |
4222 | break; |
4223 | } | |
4224 | ||
4225 | SET_HARD_REG_BIT (reload_reg_used_at_all, i); | |
4226 | } | |
4227 | } | |
4228 | ||
be7ae2a4 RK |
4229 | /* Similarly, but show REGNO is no longer in use for a reload. */ |
4230 | ||
4231 | static void | |
4232 | clear_reload_reg_in_use (regno, opnum, type, mode) | |
770ae6cc | 4233 | unsigned int regno; |
be7ae2a4 RK |
4234 | int opnum; |
4235 | enum reload_type type; | |
4236 | enum machine_mode mode; | |
4237 | { | |
770ae6cc RK |
4238 | unsigned int nregs = HARD_REGNO_NREGS (regno, mode); |
4239 | unsigned int start_regno, end_regno, r; | |
be7ae2a4 | 4240 | int i; |
cb2afeb3 R |
4241 | /* A complication is that for some reload types, inheritance might |
4242 | allow multiple reloads of the same types to share a reload register. | |
4243 | We set check_opnum if we have to check only reloads with the same | |
4244 | operand number, and check_any if we have to check all reloads. */ | |
4245 | int check_opnum = 0; | |
4246 | int check_any = 0; | |
4247 | HARD_REG_SET *used_in_set; | |
be7ae2a4 | 4248 | |
cb2afeb3 | 4249 | switch (type) |
be7ae2a4 | 4250 | { |
cb2afeb3 R |
4251 | case RELOAD_OTHER: |
4252 | used_in_set = &reload_reg_used; | |
4253 | break; | |
be7ae2a4 | 4254 | |
cb2afeb3 R |
4255 | case RELOAD_FOR_INPUT_ADDRESS: |
4256 | used_in_set = &reload_reg_used_in_input_addr[opnum]; | |
4257 | break; | |
be7ae2a4 | 4258 | |
cb2afeb3 R |
4259 | case RELOAD_FOR_INPADDR_ADDRESS: |
4260 | check_opnum = 1; | |
4261 | used_in_set = &reload_reg_used_in_inpaddr_addr[opnum]; | |
4262 | break; | |
47c8cf91 | 4263 | |
cb2afeb3 R |
4264 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4265 | used_in_set = &reload_reg_used_in_output_addr[opnum]; | |
4266 | break; | |
be7ae2a4 | 4267 | |
cb2afeb3 R |
4268 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4269 | check_opnum = 1; | |
4270 | used_in_set = &reload_reg_used_in_outaddr_addr[opnum]; | |
4271 | break; | |
47c8cf91 | 4272 | |
cb2afeb3 R |
4273 | case RELOAD_FOR_OPERAND_ADDRESS: |
4274 | used_in_set = &reload_reg_used_in_op_addr; | |
4275 | break; | |
be7ae2a4 | 4276 | |
cb2afeb3 R |
4277 | case RELOAD_FOR_OPADDR_ADDR: |
4278 | check_any = 1; | |
4279 | used_in_set = &reload_reg_used_in_op_addr_reload; | |
4280 | break; | |
893bc853 | 4281 | |
cb2afeb3 R |
4282 | case RELOAD_FOR_OTHER_ADDRESS: |
4283 | used_in_set = &reload_reg_used_in_other_addr; | |
4284 | check_any = 1; | |
4285 | break; | |
be7ae2a4 | 4286 | |
cb2afeb3 R |
4287 | case RELOAD_FOR_INPUT: |
4288 | used_in_set = &reload_reg_used_in_input[opnum]; | |
4289 | break; | |
be7ae2a4 | 4290 | |
cb2afeb3 R |
4291 | case RELOAD_FOR_OUTPUT: |
4292 | used_in_set = &reload_reg_used_in_output[opnum]; | |
4293 | break; | |
be7ae2a4 | 4294 | |
cb2afeb3 R |
4295 | case RELOAD_FOR_INSN: |
4296 | used_in_set = &reload_reg_used_in_insn; | |
4297 | break; | |
4298 | default: | |
4299 | abort (); | |
4300 | } | |
4301 | /* We resolve conflicts with remaining reloads of the same type by | |
4302 | excluding the intervals of of reload registers by them from the | |
4303 | interval of freed reload registers. Since we only keep track of | |
4304 | one set of interval bounds, we might have to exclude somewhat | |
4305 | more then what would be necessary if we used a HARD_REG_SET here. | |
4306 | But this should only happen very infrequently, so there should | |
4307 | be no reason to worry about it. */ | |
05d10675 | 4308 | |
cb2afeb3 R |
4309 | start_regno = regno; |
4310 | end_regno = regno + nregs; | |
4311 | if (check_opnum || check_any) | |
4312 | { | |
4313 | for (i = n_reloads - 1; i >= 0; i--) | |
4314 | { | |
eceef4c9 BS |
4315 | if (rld[i].when_needed == type |
4316 | && (check_any || rld[i].opnum == opnum) | |
4317 | && rld[i].reg_rtx) | |
cb2afeb3 | 4318 | { |
770ae6cc RK |
4319 | unsigned int conflict_start = true_regnum (rld[i].reg_rtx); |
4320 | unsigned int conflict_end | |
cb2afeb3 | 4321 | = (conflict_start |
8ec450a4 | 4322 | + HARD_REGNO_NREGS (conflict_start, rld[i].mode)); |
cb2afeb3 R |
4323 | |
4324 | /* If there is an overlap with the first to-be-freed register, | |
4325 | adjust the interval start. */ | |
4326 | if (conflict_start <= start_regno && conflict_end > start_regno) | |
4327 | start_regno = conflict_end; | |
4328 | /* Otherwise, if there is a conflict with one of the other | |
4329 | to-be-freed registers, adjust the interval end. */ | |
4330 | if (conflict_start > start_regno && conflict_start < end_regno) | |
4331 | end_regno = conflict_start; | |
4332 | } | |
be7ae2a4 RK |
4333 | } |
4334 | } | |
770ae6cc RK |
4335 | |
4336 | for (r = start_regno; r < end_regno; r++) | |
4337 | CLEAR_HARD_REG_BIT (*used_in_set, r); | |
be7ae2a4 RK |
4338 | } |
4339 | ||
32131a9c | 4340 | /* 1 if reg REGNO is free as a reload reg for a reload of the sort |
546b63fb | 4341 | specified by OPNUM and TYPE. */ |
32131a9c RK |
4342 | |
4343 | static int | |
546b63fb | 4344 | reload_reg_free_p (regno, opnum, type) |
770ae6cc | 4345 | unsigned int regno; |
546b63fb RK |
4346 | int opnum; |
4347 | enum reload_type type; | |
32131a9c | 4348 | { |
546b63fb RK |
4349 | int i; |
4350 | ||
2edc8d65 | 4351 | /* In use for a RELOAD_OTHER means it's not available for anything. */ |
9e3a9cf2 BS |
4352 | if (TEST_HARD_REG_BIT (reload_reg_used, regno) |
4353 | || TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) | |
32131a9c | 4354 | return 0; |
546b63fb RK |
4355 | |
4356 | switch (type) | |
32131a9c RK |
4357 | { |
4358 | case RELOAD_OTHER: | |
2edc8d65 RK |
4359 | /* In use for anything means we can't use it for RELOAD_OTHER. */ |
4360 | if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) | |
224f1d71 RK |
4361 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4362 | || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) | |
4363 | return 0; | |
4364 | ||
4365 | for (i = 0; i < reload_n_operands; i++) | |
4366 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4367 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
224f1d71 | 4368 | || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
47c8cf91 | 4369 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
224f1d71 RK |
4370 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) |
4371 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4372 | return 0; | |
4373 | ||
4374 | return 1; | |
32131a9c | 4375 | |
32131a9c | 4376 | case RELOAD_FOR_INPUT: |
546b63fb RK |
4377 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) |
4378 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) | |
4379 | return 0; | |
4380 | ||
893bc853 RK |
4381 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4382 | return 0; | |
4383 | ||
546b63fb RK |
4384 | /* If it is used for some other input, can't use it. */ |
4385 | for (i = 0; i < reload_n_operands; i++) | |
4386 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4387 | return 0; | |
4388 | ||
4389 | /* If it is used in a later operand's address, can't use it. */ | |
4390 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4391 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4392 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4393 | return 0; |
4394 | ||
4395 | return 1; | |
4396 | ||
4397 | case RELOAD_FOR_INPUT_ADDRESS: | |
4398 | /* Can't use a register if it is used for an input address for this | |
4399 | operand or used as an input in an earlier one. */ | |
47c8cf91 ILT |
4400 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno) |
4401 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) | |
4402 | return 0; | |
4403 | ||
4404 | for (i = 0; i < opnum; i++) | |
4405 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4406 | return 0; | |
4407 | ||
4408 | return 1; | |
4409 | ||
4410 | case RELOAD_FOR_INPADDR_ADDRESS: | |
4411 | /* Can't use a register if it is used for an input address | |
05d10675 BS |
4412 | for this operand or used as an input in an earlier |
4413 | one. */ | |
47c8cf91 | 4414 | if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) |
546b63fb RK |
4415 | return 0; |
4416 | ||
4417 | for (i = 0; i < opnum; i++) | |
4418 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4419 | return 0; | |
4420 | ||
4421 | return 1; | |
4422 | ||
4423 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
4424 | /* Can't use a register if it is used for an output address for this | |
d1d18b46 DJ |
4425 | operand or used as an output in this or a later operand. Note |
4426 | that multiple output operands are emitted in reverse order, so | |
4427 | the conflicting ones are those with lower indices. */ | |
546b63fb RK |
4428 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) |
4429 | return 0; | |
4430 | ||
d1d18b46 | 4431 | for (i = 0; i <= opnum; i++) |
546b63fb RK |
4432 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4433 | return 0; | |
4434 | ||
4435 | return 1; | |
4436 | ||
47c8cf91 ILT |
4437 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4438 | /* Can't use a register if it is used for an output address | |
05d10675 | 4439 | for this operand or used as an output in this or a |
d1d18b46 DJ |
4440 | later operand. Note that multiple output operands are |
4441 | emitted in reverse order, so the conflicting ones are | |
4442 | those with lower indices. */ | |
47c8cf91 ILT |
4443 | if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) |
4444 | return 0; | |
4445 | ||
d1d18b46 | 4446 | for (i = 0; i <= opnum; i++) |
47c8cf91 ILT |
4447 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4448 | return 0; | |
4449 | ||
4450 | return 1; | |
4451 | ||
32131a9c | 4452 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4453 | for (i = 0; i < reload_n_operands; i++) |
4454 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4455 | return 0; | |
4456 | ||
4457 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4458 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4459 | ||
893bc853 RK |
4460 | case RELOAD_FOR_OPADDR_ADDR: |
4461 | for (i = 0; i < reload_n_operands; i++) | |
05d10675 BS |
4462 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4463 | return 0; | |
893bc853 | 4464 | |
a94ce333 | 4465 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)); |
893bc853 | 4466 | |
32131a9c | 4467 | case RELOAD_FOR_OUTPUT: |
546b63fb | 4468 | /* This cannot share a register with RELOAD_FOR_INSN reloads, other |
d1d18b46 DJ |
4469 | outputs, or an operand address for this or an earlier output. |
4470 | Note that multiple output operands are emitted in reverse order, | |
4471 | so the conflicting ones are those with higher indices. */ | |
546b63fb RK |
4472 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) |
4473 | return 0; | |
4474 | ||
4475 | for (i = 0; i < reload_n_operands; i++) | |
4476 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4477 | return 0; | |
4478 | ||
d1d18b46 | 4479 | for (i = opnum; i < reload_n_operands; i++) |
47c8cf91 ILT |
4480 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4481 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4482 | return 0; |
4483 | ||
4484 | return 1; | |
4485 | ||
4486 | case RELOAD_FOR_INSN: | |
4487 | for (i = 0; i < reload_n_operands; i++) | |
4488 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) | |
4489 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4490 | return 0; | |
4491 | ||
4492 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4493 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4494 | ||
4495 | case RELOAD_FOR_OTHER_ADDRESS: | |
4496 | return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); | |
32131a9c RK |
4497 | } |
4498 | abort (); | |
4499 | } | |
4500 | ||
32131a9c | 4501 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
546b63fb | 4502 | needed for the part of the insn specified by OPNUM and TYPE, |
32131a9c RK |
4503 | is still available in REGNO at the end of the insn. |
4504 | ||
4505 | We can assume that the reload reg was already tested for availability | |
4506 | at the time it is needed, and we should not check this again, | |
4507 | in case the reg has already been marked in use. */ | |
4508 | ||
4509 | static int | |
546b63fb | 4510 | reload_reg_reaches_end_p (regno, opnum, type) |
770ae6cc | 4511 | unsigned int regno; |
546b63fb RK |
4512 | int opnum; |
4513 | enum reload_type type; | |
32131a9c | 4514 | { |
546b63fb RK |
4515 | int i; |
4516 | ||
4517 | switch (type) | |
32131a9c RK |
4518 | { |
4519 | case RELOAD_OTHER: | |
4520 | /* Since a RELOAD_OTHER reload claims the reg for the entire insn, | |
4521 | its value must reach the end. */ | |
4522 | return 1; | |
4523 | ||
4524 | /* If this use is for part of the insn, | |
05d10675 | 4525 | its value reaches if no subsequent part uses the same register. |
546b63fb RK |
4526 | Just like the above function, don't try to do this with lots |
4527 | of fallthroughs. */ | |
4528 | ||
4529 | case RELOAD_FOR_OTHER_ADDRESS: | |
4530 | /* Here we check for everything else, since these don't conflict | |
4531 | with anything else and everything comes later. */ | |
4532 | ||
4533 | for (i = 0; i < reload_n_operands; i++) | |
4534 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4535 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4536 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) |
4537 | || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4538 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4539 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4540 | return 0; | |
4541 | ||
4542 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) | |
4543 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4544 | && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
4545 | ||
4546 | case RELOAD_FOR_INPUT_ADDRESS: | |
47c8cf91 | 4547 | case RELOAD_FOR_INPADDR_ADDRESS: |
546b63fb RK |
4548 | /* Similar, except that we check only for this and subsequent inputs |
4549 | and the address of only subsequent inputs and we do not need | |
4550 | to check for RELOAD_OTHER objects since they are known not to | |
4551 | conflict. */ | |
4552 | ||
4553 | for (i = opnum; i < reload_n_operands; i++) | |
4554 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4555 | return 0; | |
4556 | ||
4557 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4558 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4559 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4560 | return 0; |
4561 | ||
4562 | for (i = 0; i < reload_n_operands; i++) | |
4563 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4564 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4565 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4566 | return 0; | |
4567 | ||
893bc853 RK |
4568 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4569 | return 0; | |
4570 | ||
2af88768 GK |
4571 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4572 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4573 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
546b63fb | 4574 | |
32131a9c | 4575 | case RELOAD_FOR_INPUT: |
546b63fb | 4576 | /* Similar to input address, except we start at the next operand for |
05d10675 | 4577 | both input and input address and we do not check for |
546b63fb RK |
4578 | RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these |
4579 | would conflict. */ | |
4580 | ||
4581 | for (i = opnum + 1; i < reload_n_operands; i++) | |
4582 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4583 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4584 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4585 | return 0; | |
4586 | ||
0f41302f | 4587 | /* ... fall through ... */ |
546b63fb | 4588 | |
32131a9c | 4589 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4590 | /* Check outputs and their addresses. */ |
4591 | ||
4592 | for (i = 0; i < reload_n_operands; i++) | |
4593 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4594 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4595 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4596 | return 0; | |
4597 | ||
2af88768 | 4598 | return (!TEST_HARD_REG_BIT (reload_reg_used, regno)); |
546b63fb | 4599 | |
893bc853 RK |
4600 | case RELOAD_FOR_OPADDR_ADDR: |
4601 | for (i = 0; i < reload_n_operands; i++) | |
4602 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4603 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
893bc853 RK |
4604 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4605 | return 0; | |
4606 | ||
2af88768 GK |
4607 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4608 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4609 | && !TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
893bc853 | 4610 | |
546b63fb | 4611 | case RELOAD_FOR_INSN: |
893bc853 | 4612 | /* These conflict with other outputs with RELOAD_OTHER. So |
546b63fb RK |
4613 | we need only check for output addresses. */ |
4614 | ||
d1d18b46 | 4615 | opnum = reload_n_operands; |
546b63fb | 4616 | |
0f41302f | 4617 | /* ... fall through ... */ |
546b63fb | 4618 | |
32131a9c | 4619 | case RELOAD_FOR_OUTPUT: |
546b63fb | 4620 | case RELOAD_FOR_OUTPUT_ADDRESS: |
47c8cf91 | 4621 | case RELOAD_FOR_OUTADDR_ADDRESS: |
546b63fb | 4622 | /* We already know these can't conflict with a later output. So the |
d1d18b46 DJ |
4623 | only thing to check are later output addresses. |
4624 | Note that multiple output operands are emitted in reverse order, | |
4625 | so the conflicting ones are those with lower indices. */ | |
4626 | for (i = 0; i < opnum; i++) | |
47c8cf91 ILT |
4627 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4628 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4629 | return 0; |
4630 | ||
32131a9c RK |
4631 | return 1; |
4632 | } | |
546b63fb | 4633 | |
32131a9c RK |
4634 | abort (); |
4635 | } | |
4636 | \f | |
351aa1c1 RK |
4637 | /* Return 1 if the reloads denoted by R1 and R2 cannot share a register. |
4638 | Return 0 otherwise. | |
4639 | ||
4640 | This function uses the same algorithm as reload_reg_free_p above. */ | |
4641 | ||
f5963e61 | 4642 | int |
351aa1c1 RK |
4643 | reloads_conflict (r1, r2) |
4644 | int r1, r2; | |
4645 | { | |
eceef4c9 BS |
4646 | enum reload_type r1_type = rld[r1].when_needed; |
4647 | enum reload_type r2_type = rld[r2].when_needed; | |
4648 | int r1_opnum = rld[r1].opnum; | |
4649 | int r2_opnum = rld[r2].opnum; | |
351aa1c1 | 4650 | |
2edc8d65 RK |
4651 | /* RELOAD_OTHER conflicts with everything. */ |
4652 | if (r2_type == RELOAD_OTHER) | |
351aa1c1 RK |
4653 | return 1; |
4654 | ||
4655 | /* Otherwise, check conflicts differently for each type. */ | |
4656 | ||
4657 | switch (r1_type) | |
4658 | { | |
4659 | case RELOAD_FOR_INPUT: | |
05d10675 | 4660 | return (r2_type == RELOAD_FOR_INSN |
351aa1c1 | 4661 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS |
893bc853 | 4662 | || r2_type == RELOAD_FOR_OPADDR_ADDR |
351aa1c1 | 4663 | || r2_type == RELOAD_FOR_INPUT |
47c8cf91 ILT |
4664 | || ((r2_type == RELOAD_FOR_INPUT_ADDRESS |
4665 | || r2_type == RELOAD_FOR_INPADDR_ADDRESS) | |
4666 | && r2_opnum > r1_opnum)); | |
351aa1c1 RK |
4667 | |
4668 | case RELOAD_FOR_INPUT_ADDRESS: | |
4669 | return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum) | |
4670 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
4671 | ||
47c8cf91 ILT |
4672 | case RELOAD_FOR_INPADDR_ADDRESS: |
4673 | return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum) | |
4674 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
4675 | ||
351aa1c1 RK |
4676 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4677 | return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum) | |
d1d18b46 | 4678 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); |
351aa1c1 | 4679 | |
47c8cf91 ILT |
4680 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4681 | return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum) | |
d1d18b46 | 4682 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); |
47c8cf91 | 4683 | |
351aa1c1 RK |
4684 | case RELOAD_FOR_OPERAND_ADDRESS: |
4685 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN | |
a94ce333 | 4686 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); |
351aa1c1 | 4687 | |
893bc853 | 4688 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 | 4689 | return (r2_type == RELOAD_FOR_INPUT |
a94ce333 | 4690 | || r2_type == RELOAD_FOR_OPADDR_ADDR); |
893bc853 | 4691 | |
351aa1c1 RK |
4692 | case RELOAD_FOR_OUTPUT: |
4693 | return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT | |
47c8cf91 ILT |
4694 | || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS |
4695 | || r2_type == RELOAD_FOR_OUTADDR_ADDRESS) | |
d1d18b46 | 4696 | && r2_opnum >= r1_opnum)); |
351aa1c1 RK |
4697 | |
4698 | case RELOAD_FOR_INSN: | |
4699 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT | |
4700 | || r2_type == RELOAD_FOR_INSN | |
4701 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); | |
4702 | ||
4703 | case RELOAD_FOR_OTHER_ADDRESS: | |
4704 | return r2_type == RELOAD_FOR_OTHER_ADDRESS; | |
4705 | ||
adab4fc5 | 4706 | case RELOAD_OTHER: |
2edc8d65 | 4707 | return 1; |
adab4fc5 | 4708 | |
351aa1c1 RK |
4709 | default: |
4710 | abort (); | |
4711 | } | |
4712 | } | |
4713 | \f | |
32131a9c RK |
4714 | /* Indexed by reload number, 1 if incoming value |
4715 | inherited from previous insns. */ | |
4716 | char reload_inherited[MAX_RELOADS]; | |
4717 | ||
4718 | /* For an inherited reload, this is the insn the reload was inherited from, | |
4719 | if we know it. Otherwise, this is 0. */ | |
4720 | rtx reload_inheritance_insn[MAX_RELOADS]; | |
4721 | ||
4722 | /* If non-zero, this is a place to get the value of the reload, | |
4723 | rather than using reload_in. */ | |
4724 | rtx reload_override_in[MAX_RELOADS]; | |
4725 | ||
e6e52be0 R |
4726 | /* For each reload, the hard register number of the register used, |
4727 | or -1 if we did not need a register for this reload. */ | |
32131a9c RK |
4728 | int reload_spill_index[MAX_RELOADS]; |
4729 | ||
304a22dd R |
4730 | /* Subroutine of free_for_value_p, used to check a single register. |
4731 | START_REGNO is the starting regno of the full reload register | |
4732 | (possibly comprising multiple hard registers) that we are considering. */ | |
f5470689 | 4733 | |
6e684430 | 4734 | static int |
304a22dd R |
4735 | reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out, |
4736 | reloadnum, ignore_address_reloads) | |
4737 | int start_regno, regno; | |
6e684430 R |
4738 | int opnum; |
4739 | enum reload_type type; | |
f5470689 R |
4740 | rtx value, out; |
4741 | int reloadnum; | |
5828374f | 4742 | int ignore_address_reloads; |
6e684430 R |
4743 | { |
4744 | int time1; | |
09a308fe R |
4745 | /* Set if we see an input reload that must not share its reload register |
4746 | with any new earlyclobber, but might otherwise share the reload | |
4747 | register with an output or input-output reload. */ | |
4748 | int check_earlyclobber = 0; | |
6e684430 | 4749 | int i; |
dfe96118 R |
4750 | int copy = 0; |
4751 | ||
9e3a9cf2 | 4752 | if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) |
dc8842bf AH |
4753 | return 0; |
4754 | ||
dfe96118 R |
4755 | if (out == const0_rtx) |
4756 | { | |
4757 | copy = 1; | |
4758 | out = NULL_RTX; | |
4759 | } | |
6e684430 R |
4760 | |
4761 | /* We use some pseudo 'time' value to check if the lifetimes of the | |
4762 | new register use would overlap with the one of a previous reload | |
4763 | that is not read-only or uses a different value. | |
4764 | The 'time' used doesn't have to be linear in any shape or form, just | |
4765 | monotonic. | |
4766 | Some reload types use different 'buckets' for each operand. | |
4767 | So there are MAX_RECOG_OPERANDS different time values for each | |
cecbf6e2 R |
4768 | such reload type. |
4769 | We compute TIME1 as the time when the register for the prospective | |
4770 | new reload ceases to be live, and TIME2 for each existing | |
4771 | reload as the time when that the reload register of that reload | |
4772 | becomes live. | |
4773 | Where there is little to be gained by exact lifetime calculations, | |
4774 | we just make conservative assumptions, i.e. a longer lifetime; | |
4775 | this is done in the 'default:' cases. */ | |
6e684430 R |
4776 | switch (type) |
4777 | { | |
4778 | case RELOAD_FOR_OTHER_ADDRESS: | |
203588e7 | 4779 | /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */ |
c2b4b171 | 4780 | time1 = copy ? 0 : 1; |
6e684430 | 4781 | break; |
dfe96118 R |
4782 | case RELOAD_OTHER: |
4783 | time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5; | |
4784 | break; | |
05d10675 BS |
4785 | /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS, |
4786 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 , | |
4787 | respectively, to the time values for these, we get distinct time | |
4788 | values. To get distinct time values for each operand, we have to | |
4789 | multiply opnum by at least three. We round that up to four because | |
4790 | multiply by four is often cheaper. */ | |
6e684430 | 4791 | case RELOAD_FOR_INPADDR_ADDRESS: |
dfe96118 | 4792 | time1 = opnum * 4 + 2; |
6e684430 R |
4793 | break; |
4794 | case RELOAD_FOR_INPUT_ADDRESS: | |
dfe96118 R |
4795 | time1 = opnum * 4 + 3; |
4796 | break; | |
4797 | case RELOAD_FOR_INPUT: | |
4798 | /* All RELOAD_FOR_INPUT reloads remain live till the instruction | |
4799 | executes (inclusive). */ | |
4800 | time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3; | |
6e684430 | 4801 | break; |
cb2afeb3 | 4802 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 BS |
4803 | /* opnum * 4 + 4 |
4804 | <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */ | |
cb2afeb3 R |
4805 | time1 = MAX_RECOG_OPERANDS * 4 + 1; |
4806 | break; | |
4807 | case RELOAD_FOR_OPERAND_ADDRESS: | |
4808 | /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn | |
4809 | is executed. */ | |
dfe96118 R |
4810 | time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3; |
4811 | break; | |
4812 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
4813 | time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum; | |
6e684430 | 4814 | break; |
6e684430 | 4815 | case RELOAD_FOR_OUTPUT_ADDRESS: |
dfe96118 | 4816 | time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum; |
6e684430 R |
4817 | break; |
4818 | default: | |
dfe96118 | 4819 | time1 = MAX_RECOG_OPERANDS * 5 + 5; |
6e684430 R |
4820 | } |
4821 | ||
4822 | for (i = 0; i < n_reloads; i++) | |
4823 | { | |
eceef4c9 | 4824 | rtx reg = rld[i].reg_rtx; |
6e684430 R |
4825 | if (reg && GET_CODE (reg) == REG |
4826 | && ((unsigned) regno - true_regnum (reg) | |
83e0821b | 4827 | <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1) |
f5470689 | 4828 | && i != reloadnum) |
6e684430 | 4829 | { |
304a22dd R |
4830 | rtx other_input = rld[i].in; |
4831 | ||
4832 | /* If the other reload loads the same input value, that | |
4833 | will not cause a conflict only if it's loading it into | |
4834 | the same register. */ | |
4835 | if (true_regnum (reg) != start_regno) | |
4836 | other_input = NULL_RTX; | |
4837 | if (! other_input || ! rtx_equal_p (other_input, value) | |
eceef4c9 | 4838 | || rld[i].out || out) |
6e684430 | 4839 | { |
09a308fe | 4840 | int time2; |
eceef4c9 | 4841 | switch (rld[i].when_needed) |
f5470689 R |
4842 | { |
4843 | case RELOAD_FOR_OTHER_ADDRESS: | |
4844 | time2 = 0; | |
4845 | break; | |
4846 | case RELOAD_FOR_INPADDR_ADDRESS: | |
cb2afeb3 R |
4847 | /* find_reloads makes sure that a |
4848 | RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used | |
4849 | by at most one - the first - | |
4850 | RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the | |
4851 | address reload is inherited, the address address reload | |
4852 | goes away, so we can ignore this conflict. */ | |
dfe96118 R |
4853 | if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1 |
4854 | && ignore_address_reloads | |
4855 | /* Unless the RELOAD_FOR_INPUT is an auto_inc expression. | |
4856 | Then the address address is still needed to store | |
4857 | back the new address. */ | |
eceef4c9 | 4858 | && ! rld[reloadnum].out) |
cb2afeb3 | 4859 | continue; |
dfe96118 R |
4860 | /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its |
4861 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS | |
4862 | reloads go away. */ | |
eceef4c9 | 4863 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 R |
4864 | && ignore_address_reloads |
4865 | /* Unless we are reloading an auto_inc expression. */ | |
eceef4c9 | 4866 | && ! rld[reloadnum].out) |
dfe96118 | 4867 | continue; |
eceef4c9 | 4868 | time2 = rld[i].opnum * 4 + 2; |
f5470689 R |
4869 | break; |
4870 | case RELOAD_FOR_INPUT_ADDRESS: | |
eceef4c9 | 4871 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 | 4872 | && ignore_address_reloads |
eceef4c9 | 4873 | && ! rld[reloadnum].out) |
dfe96118 | 4874 | continue; |
eceef4c9 | 4875 | time2 = rld[i].opnum * 4 + 3; |
f5470689 R |
4876 | break; |
4877 | case RELOAD_FOR_INPUT: | |
eceef4c9 | 4878 | time2 = rld[i].opnum * 4 + 4; |
09a308fe | 4879 | check_earlyclobber = 1; |
f5470689 | 4880 | break; |
eceef4c9 | 4881 | /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4 |
05d10675 | 4882 | == MAX_RECOG_OPERAND * 4 */ |
cb2afeb3 | 4883 | case RELOAD_FOR_OPADDR_ADDR: |
dfe96118 R |
4884 | if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1 |
4885 | && ignore_address_reloads | |
eceef4c9 | 4886 | && ! rld[reloadnum].out) |
cb2afeb3 | 4887 | continue; |
dfe96118 | 4888 | time2 = MAX_RECOG_OPERANDS * 4 + 1; |
cb2afeb3 R |
4889 | break; |
4890 | case RELOAD_FOR_OPERAND_ADDRESS: | |
dfe96118 | 4891 | time2 = MAX_RECOG_OPERANDS * 4 + 2; |
09a308fe | 4892 | check_earlyclobber = 1; |
dfe96118 R |
4893 | break; |
4894 | case RELOAD_FOR_INSN: | |
4895 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
cb2afeb3 | 4896 | break; |
f5470689 | 4897 | case RELOAD_FOR_OUTPUT: |
05d10675 BS |
4898 | /* All RELOAD_FOR_OUTPUT reloads become live just after the |
4899 | instruction is executed. */ | |
dfe96118 | 4900 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
f5470689 | 4901 | break; |
05d10675 BS |
4902 | /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with |
4903 | the RELOAD_FOR_OUTPUT reloads, so assign it the same time | |
4904 | value. */ | |
cb2afeb3 | 4905 | case RELOAD_FOR_OUTADDR_ADDRESS: |
dfe96118 R |
4906 | if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1 |
4907 | && ignore_address_reloads | |
eceef4c9 | 4908 | && ! rld[reloadnum].out) |
cb2afeb3 | 4909 | continue; |
eceef4c9 | 4910 | time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum; |
dfe96118 | 4911 | break; |
f5470689 | 4912 | case RELOAD_FOR_OUTPUT_ADDRESS: |
eceef4c9 | 4913 | time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum; |
f5470689 R |
4914 | break; |
4915 | case RELOAD_OTHER: | |
dfe96118 R |
4916 | /* If there is no conflict in the input part, handle this |
4917 | like an output reload. */ | |
304a22dd | 4918 | if (! rld[i].in || rtx_equal_p (other_input, value)) |
f5470689 | 4919 | { |
dfe96118 | 4920 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
57850c85 | 4921 | /* Earlyclobbered outputs must conflict with inputs. */ |
09a308fe R |
4922 | if (earlyclobber_operand_p (rld[i].out)) |
4923 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
1d7254c5 | 4924 | |
f5470689 R |
4925 | break; |
4926 | } | |
dfe96118 R |
4927 | time2 = 1; |
4928 | /* RELOAD_OTHER might be live beyond instruction execution, | |
4929 | but this is not obvious when we set time2 = 1. So check | |
4930 | here if there might be a problem with the new reload | |
4931 | clobbering the register used by the RELOAD_OTHER. */ | |
4932 | if (out) | |
4933 | return 0; | |
4934 | break; | |
f5470689 | 4935 | default: |
dfe96118 | 4936 | return 0; |
f5470689 | 4937 | } |
25963977 | 4938 | if ((time1 >= time2 |
eceef4c9 | 4939 | && (! rld[i].in || rld[i].out |
304a22dd | 4940 | || ! rtx_equal_p (other_input, value))) |
eceef4c9 | 4941 | || (out && rld[reloadnum].out_reg |
701d55e8 | 4942 | && time2 >= MAX_RECOG_OPERANDS * 4 + 3)) |
f5470689 | 4943 | return 0; |
6e684430 | 4944 | } |
6e684430 R |
4945 | } |
4946 | } | |
09a308fe R |
4947 | |
4948 | /* Earlyclobbered outputs must conflict with inputs. */ | |
4949 | if (check_earlyclobber && out && earlyclobber_operand_p (out)) | |
4950 | return 0; | |
4951 | ||
6e684430 R |
4952 | return 1; |
4953 | } | |
4954 | ||
c02cad8f BS |
4955 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
4956 | needed for the part of the insn specified by OPNUM and TYPE, | |
4957 | may be used to load VALUE into it. | |
4958 | ||
4959 | MODE is the mode in which the register is used, this is needed to | |
4960 | determine how many hard regs to test. | |
4961 | ||
4962 | Other read-only reloads with the same value do not conflict | |
4963 | unless OUT is non-zero and these other reloads have to live while | |
4964 | output reloads live. | |
4965 | If OUT is CONST0_RTX, this is a special case: it means that the | |
4966 | test should not be for using register REGNO as reload register, but | |
4967 | for copying from register REGNO into the reload register. | |
4968 | ||
4969 | RELOADNUM is the number of the reload we want to load this value for; | |
4970 | a reload does not conflict with itself. | |
4971 | ||
4972 | When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with | |
4973 | reloads that load an address for the very reload we are considering. | |
4974 | ||
4975 | The caller has to make sure that there is no conflict with the return | |
4976 | register. */ | |
4977 | ||
4978 | static int | |
4979 | free_for_value_p (regno, mode, opnum, type, value, out, reloadnum, | |
4980 | ignore_address_reloads) | |
4981 | int regno; | |
4982 | enum machine_mode mode; | |
4983 | int opnum; | |
4984 | enum reload_type type; | |
4985 | rtx value, out; | |
4986 | int reloadnum; | |
4987 | int ignore_address_reloads; | |
4988 | { | |
4989 | int nregs = HARD_REGNO_NREGS (regno, mode); | |
4990 | while (nregs-- > 0) | |
304a22dd R |
4991 | if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type, |
4992 | value, out, reloadnum, | |
4993 | ignore_address_reloads)) | |
c02cad8f BS |
4994 | return 0; |
4995 | return 1; | |
4996 | } | |
4997 | ||
ff6534ad BS |
4998 | /* Determine whether the reload reg X overlaps any rtx'es used for |
4999 | overriding inheritance. Return nonzero if so. */ | |
5000 | ||
5001 | static int | |
5002 | conflicts_with_override (x) | |
5003 | rtx x; | |
5004 | { | |
5005 | int i; | |
5006 | for (i = 0; i < n_reloads; i++) | |
5007 | if (reload_override_in[i] | |
5008 | && reg_overlap_mentioned_p (x, reload_override_in[i])) | |
5009 | return 1; | |
5010 | return 0; | |
5011 | } | |
5012 | \f | |
67e61fe7 BS |
5013 | /* Give an error message saying we failed to find a reload for INSN, |
5014 | and clear out reload R. */ | |
5015 | static void | |
5016 | failed_reload (insn, r) | |
5017 | rtx insn; | |
5018 | int r; | |
5019 | { | |
5020 | if (asm_noperands (PATTERN (insn)) < 0) | |
5021 | /* It's the compiler's fault. */ | |
5022 | fatal_insn ("Could not find a spill register", insn); | |
5023 | ||
5024 | /* It's the user's fault; the operand's mode and constraint | |
5025 | don't match. Disable this reload so we don't crash in final. */ | |
5026 | error_for_asm (insn, | |
5027 | "`asm' operand constraint incompatible with operand size"); | |
5028 | rld[r].in = 0; | |
5029 | rld[r].out = 0; | |
5030 | rld[r].reg_rtx = 0; | |
5031 | rld[r].optional = 1; | |
5032 | rld[r].secondary_p = 1; | |
5033 | } | |
5034 | ||
5035 | /* I is the index in SPILL_REG_RTX of the reload register we are to allocate | |
5036 | for reload R. If it's valid, get an rtx for it. Return nonzero if | |
5037 | successful. */ | |
5038 | static int | |
5039 | set_reload_reg (i, r) | |
5040 | int i, r; | |
5041 | { | |
5042 | int regno; | |
5043 | rtx reg = spill_reg_rtx[i]; | |
5044 | ||
5045 | if (reg == 0 || GET_MODE (reg) != rld[r].mode) | |
5046 | spill_reg_rtx[i] = reg | |
5047 | = gen_rtx_REG (rld[r].mode, spill_regs[i]); | |
5048 | ||
5049 | regno = true_regnum (reg); | |
5050 | ||
5051 | /* Detect when the reload reg can't hold the reload mode. | |
5052 | This used to be one `if', but Sequent compiler can't handle that. */ | |
5053 | if (HARD_REGNO_MODE_OK (regno, rld[r].mode)) | |
5054 | { | |
5055 | enum machine_mode test_mode = VOIDmode; | |
5056 | if (rld[r].in) | |
5057 | test_mode = GET_MODE (rld[r].in); | |
5058 | /* If rld[r].in has VOIDmode, it means we will load it | |
5059 | in whatever mode the reload reg has: to wit, rld[r].mode. | |
5060 | We have already tested that for validity. */ | |
5061 | /* Aside from that, we need to test that the expressions | |
5062 | to reload from or into have modes which are valid for this | |
5063 | reload register. Otherwise the reload insns would be invalid. */ | |
5064 | if (! (rld[r].in != 0 && test_mode != VOIDmode | |
5065 | && ! HARD_REGNO_MODE_OK (regno, test_mode))) | |
5066 | if (! (rld[r].out != 0 | |
5067 | && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out)))) | |
5068 | { | |
5069 | /* The reg is OK. */ | |
5070 | last_spill_reg = i; | |
5071 | ||
5072 | /* Mark as in use for this insn the reload regs we use | |
5073 | for this. */ | |
5074 | mark_reload_reg_in_use (spill_regs[i], rld[r].opnum, | |
5075 | rld[r].when_needed, rld[r].mode); | |
5076 | ||
5077 | rld[r].reg_rtx = reg; | |
5078 | reload_spill_index[r] = spill_regs[i]; | |
5079 | return 1; | |
5080 | } | |
5081 | } | |
5082 | return 0; | |
5083 | } | |
5084 | ||
32131a9c RK |
5085 | /* Find a spill register to use as a reload register for reload R. |
5086 | LAST_RELOAD is non-zero if this is the last reload for the insn being | |
5087 | processed. | |
5088 | ||
eceef4c9 | 5089 | Set rld[R].reg_rtx to the register allocated. |
32131a9c | 5090 | |
f5d8c9f4 BS |
5091 | We return 1 if successful, or 0 if we couldn't find a spill reg and |
5092 | we didn't change anything. */ | |
32131a9c RK |
5093 | |
5094 | static int | |
f5d8c9f4 | 5095 | allocate_reload_reg (chain, r, last_reload) |
272df862 | 5096 | struct insn_chain *chain ATTRIBUTE_UNUSED; |
32131a9c | 5097 | int r; |
32131a9c | 5098 | int last_reload; |
32131a9c | 5099 | { |
67e61fe7 | 5100 | int i, pass, count; |
32131a9c RK |
5101 | |
5102 | /* If we put this reload ahead, thinking it is a group, | |
5103 | then insist on finding a group. Otherwise we can grab a | |
a8fdc208 | 5104 | reg that some other reload needs. |
32131a9c RK |
5105 | (That can happen when we have a 68000 DATA_OR_FP_REG |
5106 | which is a group of data regs or one fp reg.) | |
5107 | We need not be so restrictive if there are no more reloads | |
5108 | for this insn. | |
5109 | ||
5110 | ??? Really it would be nicer to have smarter handling | |
5111 | for that kind of reg class, where a problem like this is normal. | |
5112 | Perhaps those classes should be avoided for reloading | |
5113 | by use of more alternatives. */ | |
5114 | ||
8ec450a4 | 5115 | int force_group = rld[r].nregs > 1 && ! last_reload; |
32131a9c RK |
5116 | |
5117 | /* If we want a single register and haven't yet found one, | |
5118 | take any reg in the right class and not in use. | |
5119 | If we want a consecutive group, here is where we look for it. | |
5120 | ||
5121 | We use two passes so we can first look for reload regs to | |
5122 | reuse, which are already in use for other reloads in this insn, | |
5123 | and only then use additional registers. | |
5124 | I think that maximizing reuse is needed to make sure we don't | |
5125 | run out of reload regs. Suppose we have three reloads, and | |
5126 | reloads A and B can share regs. These need two regs. | |
5127 | Suppose A and B are given different regs. | |
5128 | That leaves none for C. */ | |
5129 | for (pass = 0; pass < 2; pass++) | |
5130 | { | |
5131 | /* I is the index in spill_regs. | |
5132 | We advance it round-robin between insns to use all spill regs | |
5133 | equally, so that inherited reloads have a chance | |
f5d8c9f4 BS |
5134 | of leapfrogging each other. */ |
5135 | ||
5136 | i = last_spill_reg; | |
05d10675 | 5137 | |
a5339699 | 5138 | for (count = 0; count < n_spills; count++) |
32131a9c | 5139 | { |
eceef4c9 | 5140 | int class = (int) rld[r].class; |
03acd8f8 | 5141 | int regnum; |
32131a9c | 5142 | |
03acd8f8 BS |
5143 | i++; |
5144 | if (i >= n_spills) | |
5145 | i -= n_spills; | |
5146 | regnum = spill_regs[i]; | |
32131a9c | 5147 | |
eceef4c9 BS |
5148 | if ((reload_reg_free_p (regnum, rld[r].opnum, |
5149 | rld[r].when_needed) | |
5150 | || (rld[r].in | |
05d10675 BS |
5151 | /* We check reload_reg_used to make sure we |
5152 | don't clobber the return register. */ | |
03acd8f8 | 5153 | && ! TEST_HARD_REG_BIT (reload_reg_used, regnum) |
c02cad8f BS |
5154 | && free_for_value_p (regnum, rld[r].mode, rld[r].opnum, |
5155 | rld[r].when_needed, rld[r].in, | |
5156 | rld[r].out, r, 1))) | |
03acd8f8 | 5157 | && TEST_HARD_REG_BIT (reg_class_contents[class], regnum) |
8ec450a4 | 5158 | && HARD_REGNO_MODE_OK (regnum, rld[r].mode) |
be7ae2a4 RK |
5159 | /* Look first for regs to share, then for unshared. But |
5160 | don't share regs used for inherited reloads; they are | |
5161 | the ones we want to preserve. */ | |
5162 | && (pass | |
5163 | || (TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
03acd8f8 | 5164 | regnum) |
be7ae2a4 | 5165 | && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, |
03acd8f8 | 5166 | regnum)))) |
32131a9c | 5167 | { |
8ec450a4 | 5168 | int nr = HARD_REGNO_NREGS (regnum, rld[r].mode); |
32131a9c RK |
5169 | /* Avoid the problem where spilling a GENERAL_OR_FP_REG |
5170 | (on 68000) got us two FP regs. If NR is 1, | |
5171 | we would reject both of them. */ | |
5172 | if (force_group) | |
67e61fe7 | 5173 | nr = rld[r].nregs; |
32131a9c RK |
5174 | /* If we need only one reg, we have already won. */ |
5175 | if (nr == 1) | |
5176 | { | |
5177 | /* But reject a single reg if we demand a group. */ | |
5178 | if (force_group) | |
5179 | continue; | |
5180 | break; | |
5181 | } | |
5182 | /* Otherwise check that as many consecutive regs as we need | |
f5d8c9f4 BS |
5183 | are available here. */ |
5184 | while (nr > 1) | |
5185 | { | |
5186 | int regno = regnum + nr - 1; | |
5187 | if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
5188 | && spill_reg_order[regno] >= 0 | |
5189 | && reload_reg_free_p (regno, rld[r].opnum, | |
5190 | rld[r].when_needed))) | |
5191 | break; | |
5192 | nr--; | |
5193 | } | |
32131a9c RK |
5194 | if (nr == 1) |
5195 | break; | |
5196 | } | |
5197 | } | |
5198 | ||
5199 | /* If we found something on pass 1, omit pass 2. */ | |
5200 | if (count < n_spills) | |
5201 | break; | |
5202 | } | |
1d7254c5 | 5203 | |
32131a9c | 5204 | /* We should have found a spill register by now. */ |
f5d8c9f4 | 5205 | if (count >= n_spills) |
32131a9c RK |
5206 | return 0; |
5207 | ||
f5d8c9f4 BS |
5208 | /* I is the index in SPILL_REG_RTX of the reload register we are to |
5209 | allocate. Get an rtx for it and find its register number. */ | |
32131a9c | 5210 | |
f5d8c9f4 | 5211 | return set_reload_reg (i, r); |
32131a9c RK |
5212 | } |
5213 | \f | |
67e61fe7 BS |
5214 | /* Initialize all the tables needed to allocate reload registers. |
5215 | CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX | |
5216 | is the array we use to restore the reg_rtx field for every reload. */ | |
efc9bd41 | 5217 | |
32131a9c | 5218 | static void |
67e61fe7 | 5219 | choose_reload_regs_init (chain, save_reload_reg_rtx) |
7609e720 | 5220 | struct insn_chain *chain; |
67e61fe7 | 5221 | rtx *save_reload_reg_rtx; |
32131a9c | 5222 | { |
67e61fe7 | 5223 | int i; |
32131a9c | 5224 | |
67e61fe7 BS |
5225 | for (i = 0; i < n_reloads; i++) |
5226 | rld[i].reg_rtx = save_reload_reg_rtx[i]; | |
32131a9c | 5227 | |
961192e1 JM |
5228 | memset (reload_inherited, 0, MAX_RELOADS); |
5229 | memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx)); | |
5230 | memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx)); | |
32131a9c RK |
5231 | |
5232 | CLEAR_HARD_REG_SET (reload_reg_used); | |
5233 | CLEAR_HARD_REG_SET (reload_reg_used_at_all); | |
32131a9c | 5234 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); |
893bc853 | 5235 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload); |
546b63fb RK |
5236 | CLEAR_HARD_REG_SET (reload_reg_used_in_insn); |
5237 | CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); | |
32131a9c | 5238 | |
f1db3576 JL |
5239 | CLEAR_HARD_REG_SET (reg_used_in_insn); |
5240 | { | |
5241 | HARD_REG_SET tmp; | |
239a0f5b | 5242 | REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout); |
f1db3576 | 5243 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b | 5244 | REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set); |
f1db3576 | 5245 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b BS |
5246 | compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout); |
5247 | compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set); | |
f1db3576 | 5248 | } |
efc9bd41 | 5249 | |
546b63fb RK |
5250 | for (i = 0; i < reload_n_operands; i++) |
5251 | { | |
5252 | CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); | |
5253 | CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); | |
5254 | CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); | |
47c8cf91 | 5255 | CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]); |
546b63fb | 5256 | CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); |
47c8cf91 | 5257 | CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]); |
546b63fb | 5258 | } |
32131a9c | 5259 | |
9e3a9cf2 | 5260 | COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs); |
05d10675 | 5261 | |
67e61fe7 | 5262 | CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); |
32131a9c | 5263 | |
67e61fe7 BS |
5264 | for (i = 0; i < n_reloads; i++) |
5265 | /* If we have already decided to use a certain register, | |
5266 | don't use it in another way. */ | |
5267 | if (rld[i].reg_rtx) | |
5268 | mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum, | |
5269 | rld[i].when_needed, rld[i].mode); | |
5270 | } | |
32131a9c | 5271 | |
67e61fe7 BS |
5272 | /* Assign hard reg targets for the pseudo-registers we must reload |
5273 | into hard regs for this insn. | |
5274 | Also output the instructions to copy them in and out of the hard regs. | |
5275 | ||
5276 | For machines with register classes, we are responsible for | |
5277 | finding a reload reg in the proper class. */ | |
5278 | ||
5279 | static void | |
5280 | choose_reload_regs (chain) | |
5281 | struct insn_chain *chain; | |
5282 | { | |
5283 | rtx insn = chain->insn; | |
b3694847 | 5284 | int i, j; |
770ae6cc | 5285 | unsigned int max_group_size = 1; |
67e61fe7 | 5286 | enum reg_class group_class = NO_REGS; |
f5d8c9f4 | 5287 | int pass, win, inheritance; |
67e61fe7 BS |
5288 | |
5289 | rtx save_reload_reg_rtx[MAX_RELOADS]; | |
32131a9c | 5290 | |
32131a9c RK |
5291 | /* In order to be certain of getting the registers we need, |
5292 | we must sort the reloads into order of increasing register class. | |
5293 | Then our grabbing of reload registers will parallel the process | |
a8fdc208 | 5294 | that provided the reload registers. |
32131a9c RK |
5295 | |
5296 | Also note whether any of the reloads wants a consecutive group of regs. | |
5297 | If so, record the maximum size of the group desired and what | |
5298 | register class contains all the groups needed by this insn. */ | |
5299 | ||
5300 | for (j = 0; j < n_reloads; j++) | |
5301 | { | |
5302 | reload_order[j] = j; | |
5303 | reload_spill_index[j] = -1; | |
5304 | ||
8ec450a4 | 5305 | if (rld[j].nregs > 1) |
32131a9c | 5306 | { |
8ec450a4 | 5307 | max_group_size = MAX (rld[j].nregs, max_group_size); |
770ae6cc | 5308 | group_class |
1d7254c5 | 5309 | = reg_class_superunion[(int) rld[j].class][(int)group_class]; |
32131a9c RK |
5310 | } |
5311 | ||
eceef4c9 | 5312 | save_reload_reg_rtx[j] = rld[j].reg_rtx; |
32131a9c RK |
5313 | } |
5314 | ||
5315 | if (n_reloads > 1) | |
5316 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); | |
5317 | ||
58b1581b RS |
5318 | /* If -O, try first with inheritance, then turning it off. |
5319 | If not -O, don't do inheritance. | |
5320 | Using inheritance when not optimizing leads to paradoxes | |
5321 | with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves | |
5322 | because one side of the comparison might be inherited. */ | |
f5d8c9f4 | 5323 | win = 0; |
58b1581b | 5324 | for (inheritance = optimize > 0; inheritance >= 0; inheritance--) |
32131a9c | 5325 | { |
67e61fe7 BS |
5326 | choose_reload_regs_init (chain, save_reload_reg_rtx); |
5327 | ||
32131a9c RK |
5328 | /* Process the reloads in order of preference just found. |
5329 | Beyond this point, subregs can be found in reload_reg_rtx. | |
5330 | ||
770ae6cc RK |
5331 | This used to look for an existing reloaded home for all of the |
5332 | reloads, and only then perform any new reloads. But that could lose | |
5333 | if the reloads were done out of reg-class order because a later | |
5334 | reload with a looser constraint might have an old home in a register | |
5335 | needed by an earlier reload with a tighter constraint. | |
32131a9c RK |
5336 | |
5337 | To solve this, we make two passes over the reloads, in the order | |
5338 | described above. In the first pass we try to inherit a reload | |
5339 | from a previous insn. If there is a later reload that needs a | |
5340 | class that is a proper subset of the class being processed, we must | |
5341 | also allocate a spill register during the first pass. | |
5342 | ||
5343 | Then make a second pass over the reloads to allocate any reloads | |
5344 | that haven't been given registers yet. */ | |
5345 | ||
5346 | for (j = 0; j < n_reloads; j++) | |
5347 | { | |
b3694847 | 5348 | int r = reload_order[j]; |
8593b745 | 5349 | rtx search_equiv = NULL_RTX; |
32131a9c RK |
5350 | |
5351 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 BS |
5352 | if (rld[r].out == 0 && rld[r].in == 0 |
5353 | && ! rld[r].secondary_p) | |
32131a9c RK |
5354 | continue; |
5355 | ||
b29514ee | 5356 | /* If find_reloads chose to use reload_in or reload_out as a reload |
b080c137 RK |
5357 | register, we don't need to chose one. Otherwise, try even if it |
5358 | found one since we might save an insn if we find the value lying | |
b29514ee R |
5359 | around. |
5360 | Try also when reload_in is a pseudo without a hard reg. */ | |
eceef4c9 BS |
5361 | if (rld[r].in != 0 && rld[r].reg_rtx != 0 |
5362 | && (rtx_equal_p (rld[r].in, rld[r].reg_rtx) | |
5363 | || (rtx_equal_p (rld[r].out, rld[r].reg_rtx) | |
5364 | && GET_CODE (rld[r].in) != MEM | |
5365 | && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER))) | |
32131a9c RK |
5366 | continue; |
5367 | ||
5368 | #if 0 /* No longer needed for correct operation. | |
5369 | It might give better code, or might not; worth an experiment? */ | |
5370 | /* If this is an optional reload, we can't inherit from earlier insns | |
5371 | until we are sure that any non-optional reloads have been allocated. | |
5372 | The following code takes advantage of the fact that optional reloads | |
5373 | are at the end of reload_order. */ | |
eceef4c9 | 5374 | if (rld[r].optional != 0) |
32131a9c | 5375 | for (i = 0; i < j; i++) |
eceef4c9 BS |
5376 | if ((rld[reload_order[i]].out != 0 |
5377 | || rld[reload_order[i]].in != 0 | |
5378 | || rld[reload_order[i]].secondary_p) | |
5379 | && ! rld[reload_order[i]].optional | |
5380 | && rld[reload_order[i]].reg_rtx == 0) | |
f5d8c9f4 | 5381 | allocate_reload_reg (chain, reload_order[i], 0); |
32131a9c RK |
5382 | #endif |
5383 | ||
5384 | /* First see if this pseudo is already available as reloaded | |
5385 | for a previous insn. We cannot try to inherit for reloads | |
5386 | that are smaller than the maximum number of registers needed | |
5387 | for groups unless the register we would allocate cannot be used | |
5388 | for the groups. | |
5389 | ||
5390 | We could check here to see if this is a secondary reload for | |
5391 | an object that is already in a register of the desired class. | |
5392 | This would avoid the need for the secondary reload register. | |
5393 | But this is complex because we can't easily determine what | |
b080c137 RK |
5394 | objects might want to be loaded via this reload. So let a |
5395 | register be allocated here. In `emit_reload_insns' we suppress | |
5396 | one of the loads in the case described above. */ | |
32131a9c RK |
5397 | |
5398 | if (inheritance) | |
5399 | { | |
ddef6bc7 | 5400 | int byte = 0; |
b3694847 | 5401 | int regno = -1; |
6a651371 | 5402 | enum machine_mode mode = VOIDmode; |
32131a9c | 5403 | |
eceef4c9 | 5404 | if (rld[r].in == 0) |
32131a9c | 5405 | ; |
eceef4c9 | 5406 | else if (GET_CODE (rld[r].in) == REG) |
db660765 | 5407 | { |
eceef4c9 BS |
5408 | regno = REGNO (rld[r].in); |
5409 | mode = GET_MODE (rld[r].in); | |
db660765 | 5410 | } |
eceef4c9 | 5411 | else if (GET_CODE (rld[r].in_reg) == REG) |
db660765 | 5412 | { |
eceef4c9 BS |
5413 | regno = REGNO (rld[r].in_reg); |
5414 | mode = GET_MODE (rld[r].in_reg); | |
db660765 | 5415 | } |
eceef4c9 BS |
5416 | else if (GET_CODE (rld[r].in_reg) == SUBREG |
5417 | && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG) | |
b60a8416 | 5418 | { |
ddef6bc7 | 5419 | byte = SUBREG_BYTE (rld[r].in_reg); |
eceef4c9 | 5420 | regno = REGNO (SUBREG_REG (rld[r].in_reg)); |
cb2afeb3 | 5421 | if (regno < FIRST_PSEUDO_REGISTER) |
ddef6bc7 | 5422 | regno = subreg_regno (rld[r].in_reg); |
eceef4c9 | 5423 | mode = GET_MODE (rld[r].in_reg); |
cb2afeb3 R |
5424 | } |
5425 | #ifdef AUTO_INC_DEC | |
eceef4c9 BS |
5426 | else if ((GET_CODE (rld[r].in_reg) == PRE_INC |
5427 | || GET_CODE (rld[r].in_reg) == PRE_DEC | |
5428 | || GET_CODE (rld[r].in_reg) == POST_INC | |
5429 | || GET_CODE (rld[r].in_reg) == POST_DEC) | |
5430 | && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG) | |
cb2afeb3 | 5431 | { |
eceef4c9 BS |
5432 | regno = REGNO (XEXP (rld[r].in_reg, 0)); |
5433 | mode = GET_MODE (XEXP (rld[r].in_reg, 0)); | |
5434 | rld[r].out = rld[r].in; | |
b60a8416 | 5435 | } |
cb2afeb3 | 5436 | #endif |
32131a9c RK |
5437 | #if 0 |
5438 | /* This won't work, since REGNO can be a pseudo reg number. | |
5439 | Also, it takes much more hair to keep track of all the things | |
5440 | that can invalidate an inherited reload of part of a pseudoreg. */ | |
eceef4c9 BS |
5441 | else if (GET_CODE (rld[r].in) == SUBREG |
5442 | && GET_CODE (SUBREG_REG (rld[r].in)) == REG) | |
ddef6bc7 | 5443 | regno = subreg_regno (rld[r].in); |
32131a9c RK |
5444 | #endif |
5445 | ||
5446 | if (regno >= 0 && reg_last_reload_reg[regno] != 0) | |
5447 | { | |
eceef4c9 | 5448 | enum reg_class class = rld[r].class, last_class; |
cb2afeb3 | 5449 | rtx last_reg = reg_last_reload_reg[regno]; |
02188693 | 5450 | enum machine_mode need_mode; |
05d10675 | 5451 | |
ddef6bc7 JJ |
5452 | i = REGNO (last_reg); |
5453 | i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode); | |
cb2afeb3 | 5454 | last_class = REGNO_REG_CLASS (i); |
02188693 | 5455 | |
ddef6bc7 | 5456 | if (byte == 0) |
ce701d1b BS |
5457 | need_mode = mode; |
5458 | else | |
5459 | need_mode | |
ddef6bc7 | 5460 | = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte, |
ce701d1b | 5461 | GET_MODE_CLASS (mode)); |
02188693 | 5462 | |
c9d8a813 | 5463 | if ( |
02188693 | 5464 | #ifdef CLASS_CANNOT_CHANGE_MODE |
c9d8a813 | 5465 | (TEST_HARD_REG_BIT |
02188693 | 5466 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i) |
1d7254c5 | 5467 | ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg), |
02188693 | 5468 | need_mode) |
c9d8a813 | 5469 | : (GET_MODE_SIZE (GET_MODE (last_reg)) |
02188693 | 5470 | >= GET_MODE_SIZE (need_mode))) |
c9d8a813 RH |
5471 | #else |
5472 | (GET_MODE_SIZE (GET_MODE (last_reg)) | |
02188693 | 5473 | >= GET_MODE_SIZE (need_mode)) |
c9d8a813 | 5474 | #endif |
cb2afeb3 | 5475 | && reg_reloaded_contents[i] == regno |
e6e52be0 | 5476 | && TEST_HARD_REG_BIT (reg_reloaded_valid, i) |
8ec450a4 | 5477 | && HARD_REGNO_MODE_OK (i, rld[r].mode) |
cb2afeb3 R |
5478 | && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i) |
5479 | /* Even if we can't use this register as a reload | |
5480 | register, we might use it for reload_override_in, | |
5481 | if copying it to the desired class is cheap | |
5482 | enough. */ | |
e56b4594 | 5483 | || ((REGISTER_MOVE_COST (mode, last_class, class) |
cb2afeb3 R |
5484 | < MEMORY_MOVE_COST (mode, class, 1)) |
5485 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
5486 | && (SECONDARY_INPUT_RELOAD_CLASS (class, mode, | |
5487 | last_reg) | |
5488 | == NO_REGS) | |
5489 | #endif | |
5490 | #ifdef SECONDARY_MEMORY_NEEDED | |
5491 | && ! SECONDARY_MEMORY_NEEDED (last_class, class, | |
5492 | mode) | |
5493 | #endif | |
5494 | )) | |
5495 | ||
8ec450a4 | 5496 | && (rld[r].nregs == max_group_size |
32131a9c | 5497 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], |
e6e52be0 | 5498 | i)) |
c02cad8f BS |
5499 | && free_for_value_p (i, rld[r].mode, rld[r].opnum, |
5500 | rld[r].when_needed, rld[r].in, | |
5501 | const0_rtx, r, 1)) | |
32131a9c RK |
5502 | { |
5503 | /* If a group is needed, verify that all the subsequent | |
0f41302f | 5504 | registers still have their values intact. */ |
1d7254c5 | 5505 | int nr = HARD_REGNO_NREGS (i, rld[r].mode); |
32131a9c RK |
5506 | int k; |
5507 | ||
5508 | for (k = 1; k < nr; k++) | |
e6e52be0 R |
5509 | if (reg_reloaded_contents[i + k] != regno |
5510 | || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k)) | |
32131a9c RK |
5511 | break; |
5512 | ||
5513 | if (k == nr) | |
5514 | { | |
c74fa651 | 5515 | int i1; |
eb4d554e | 5516 | int bad_for_class; |
c74fa651 | 5517 | |
cb2afeb3 R |
5518 | last_reg = (GET_MODE (last_reg) == mode |
5519 | ? last_reg : gen_rtx_REG (mode, i)); | |
5520 | ||
eb4d554e GK |
5521 | bad_for_class = 0; |
5522 | for (k = 0; k < nr; k++) | |
5523 | bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], | |
5524 | i+k); | |
5525 | ||
c74fa651 RS |
5526 | /* We found a register that contains the |
5527 | value we need. If this register is the | |
5528 | same as an `earlyclobber' operand of the | |
5529 | current insn, just mark it as a place to | |
5530 | reload from since we can't use it as the | |
5531 | reload register itself. */ | |
5532 | ||
5533 | for (i1 = 0; i1 < n_earlyclobbers; i1++) | |
5534 | if (reg_overlap_mentioned_for_reload_p | |
5535 | (reg_last_reload_reg[regno], | |
5536 | reload_earlyclobbers[i1])) | |
5537 | break; | |
5538 | ||
8908158d | 5539 | if (i1 != n_earlyclobbers |
c02cad8f BS |
5540 | || ! (free_for_value_p (i, rld[r].mode, |
5541 | rld[r].opnum, | |
5542 | rld[r].when_needed, rld[r].in, | |
5543 | rld[r].out, r, 1)) | |
e6e52be0 | 5544 | /* Don't use it if we'd clobber a pseudo reg. */ |
f1db3576 | 5545 | || (TEST_HARD_REG_BIT (reg_used_in_insn, i) |
eceef4c9 | 5546 | && rld[r].out |
e6e52be0 | 5547 | && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i)) |
0c7f2259 | 5548 | /* Don't clobber the frame pointer. */ |
1d7254c5 KH |
5549 | || (i == HARD_FRAME_POINTER_REGNUM |
5550 | && rld[r].out) | |
8908158d RS |
5551 | /* Don't really use the inherited spill reg |
5552 | if we need it wider than we've got it. */ | |
8ec450a4 | 5553 | || (GET_MODE_SIZE (rld[r].mode) |
b29514ee | 5554 | > GET_MODE_SIZE (mode)) |
eb4d554e | 5555 | || bad_for_class |
cb2afeb3 | 5556 | |
b29514ee R |
5557 | /* If find_reloads chose reload_out as reload |
5558 | register, stay with it - that leaves the | |
5559 | inherited register for subsequent reloads. */ | |
eceef4c9 | 5560 | || (rld[r].out && rld[r].reg_rtx |
67e61fe7 | 5561 | && rtx_equal_p (rld[r].out, rld[r].reg_rtx))) |
cb2afeb3 | 5562 | { |
4c3a2649 BS |
5563 | if (! rld[r].optional) |
5564 | { | |
5565 | reload_override_in[r] = last_reg; | |
5566 | reload_inheritance_insn[r] | |
5567 | = reg_reloaded_insn[i]; | |
5568 | } | |
cb2afeb3 | 5569 | } |
c74fa651 RS |
5570 | else |
5571 | { | |
54c40e68 | 5572 | int k; |
c74fa651 RS |
5573 | /* We can use this as a reload reg. */ |
5574 | /* Mark the register as in use for this part of | |
5575 | the insn. */ | |
e6e52be0 | 5576 | mark_reload_reg_in_use (i, |
eceef4c9 BS |
5577 | rld[r].opnum, |
5578 | rld[r].when_needed, | |
8ec450a4 | 5579 | rld[r].mode); |
eceef4c9 | 5580 | rld[r].reg_rtx = last_reg; |
c74fa651 RS |
5581 | reload_inherited[r] = 1; |
5582 | reload_inheritance_insn[r] | |
5583 | = reg_reloaded_insn[i]; | |
5584 | reload_spill_index[r] = i; | |
54c40e68 RS |
5585 | for (k = 0; k < nr; k++) |
5586 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, | |
e6e52be0 | 5587 | i + k); |
c74fa651 | 5588 | } |
32131a9c RK |
5589 | } |
5590 | } | |
5591 | } | |
5592 | } | |
5593 | ||
5594 | /* Here's another way to see if the value is already lying around. */ | |
5595 | if (inheritance | |
eceef4c9 | 5596 | && rld[r].in != 0 |
32131a9c | 5597 | && ! reload_inherited[r] |
eceef4c9 BS |
5598 | && rld[r].out == 0 |
5599 | && (CONSTANT_P (rld[r].in) | |
5600 | || GET_CODE (rld[r].in) == PLUS | |
5601 | || GET_CODE (rld[r].in) == REG | |
5602 | || GET_CODE (rld[r].in) == MEM) | |
8ec450a4 | 5603 | && (rld[r].nregs == max_group_size |
eceef4c9 BS |
5604 | || ! reg_classes_intersect_p (rld[r].class, group_class))) |
5605 | search_equiv = rld[r].in; | |
8593b745 R |
5606 | /* If this is an output reload from a simple move insn, look |
5607 | if an equivalence for the input is available. */ | |
eceef4c9 | 5608 | else if (inheritance && rld[r].in == 0 && rld[r].out != 0) |
8593b745 R |
5609 | { |
5610 | rtx set = single_set (insn); | |
5611 | ||
5612 | if (set | |
eceef4c9 | 5613 | && rtx_equal_p (rld[r].out, SET_DEST (set)) |
8593b745 R |
5614 | && CONSTANT_P (SET_SRC (set))) |
5615 | search_equiv = SET_SRC (set); | |
5616 | } | |
5617 | ||
5618 | if (search_equiv) | |
32131a9c | 5619 | { |
b3694847 | 5620 | rtx equiv |
eceef4c9 | 5621 | = find_equiv_reg (search_equiv, insn, rld[r].class, |
9714cf43 | 5622 | -1, NULL, 0, rld[r].mode); |
f428f252 | 5623 | int regno = 0; |
32131a9c RK |
5624 | |
5625 | if (equiv != 0) | |
5626 | { | |
5627 | if (GET_CODE (equiv) == REG) | |
5628 | regno = REGNO (equiv); | |
5629 | else if (GET_CODE (equiv) == SUBREG) | |
5630 | { | |
f8a9e02b RK |
5631 | /* This must be a SUBREG of a hard register. |
5632 | Make a new REG since this might be used in an | |
5633 | address and not all machines support SUBREGs | |
5634 | there. */ | |
ddef6bc7 | 5635 | regno = subreg_regno (equiv); |
8ec450a4 | 5636 | equiv = gen_rtx_REG (rld[r].mode, regno); |
32131a9c RK |
5637 | } |
5638 | else | |
5639 | abort (); | |
5640 | } | |
5641 | ||
5642 | /* If we found a spill reg, reject it unless it is free | |
5643 | and of the desired class. */ | |
5644 | if (equiv != 0 | |
cb2afeb3 | 5645 | && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno) |
c02cad8f BS |
5646 | && ! free_for_value_p (regno, rld[r].mode, |
5647 | rld[r].opnum, rld[r].when_needed, | |
5648 | rld[r].in, rld[r].out, r, 1)) | |
eceef4c9 | 5649 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], |
32131a9c RK |
5650 | regno))) |
5651 | equiv = 0; | |
5652 | ||
8ec450a4 | 5653 | if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode)) |
32131a9c RK |
5654 | equiv = 0; |
5655 | ||
5656 | /* We found a register that contains the value we need. | |
5657 | If this register is the same as an `earlyclobber' operand | |
5658 | of the current insn, just mark it as a place to reload from | |
5659 | since we can't use it as the reload register itself. */ | |
5660 | ||
5661 | if (equiv != 0) | |
5662 | for (i = 0; i < n_earlyclobbers; i++) | |
bfa30b22 RK |
5663 | if (reg_overlap_mentioned_for_reload_p (equiv, |
5664 | reload_earlyclobbers[i])) | |
32131a9c | 5665 | { |
4c3a2649 BS |
5666 | if (! rld[r].optional) |
5667 | reload_override_in[r] = equiv; | |
32131a9c RK |
5668 | equiv = 0; |
5669 | break; | |
5670 | } | |
5671 | ||
3c785e47 R |
5672 | /* If the equiv register we have found is explicitly clobbered |
5673 | in the current insn, it depends on the reload type if we | |
5674 | can use it, use it for reload_override_in, or not at all. | |
5675 | In particular, we then can't use EQUIV for a | |
5676 | RELOAD_FOR_OUTPUT_ADDRESS reload. */ | |
32131a9c | 5677 | |
9532e31f | 5678 | if (equiv != 0) |
174fa2c4 | 5679 | { |
9532e31f BS |
5680 | if (regno_clobbered_p (regno, insn, rld[r].mode, 0)) |
5681 | switch (rld[r].when_needed) | |
5682 | { | |
5683 | case RELOAD_FOR_OTHER_ADDRESS: | |
5684 | case RELOAD_FOR_INPADDR_ADDRESS: | |
5685 | case RELOAD_FOR_INPUT_ADDRESS: | |
5686 | case RELOAD_FOR_OPADDR_ADDR: | |
5687 | break; | |
5688 | case RELOAD_OTHER: | |
5689 | case RELOAD_FOR_INPUT: | |
5690 | case RELOAD_FOR_OPERAND_ADDRESS: | |
5691 | if (! rld[r].optional) | |
5692 | reload_override_in[r] = equiv; | |
5693 | /* Fall through. */ | |
5694 | default: | |
5695 | equiv = 0; | |
5696 | break; | |
5697 | } | |
5698 | else if (regno_clobbered_p (regno, insn, rld[r].mode, 1)) | |
5699 | switch (rld[r].when_needed) | |
5700 | { | |
5701 | case RELOAD_FOR_OTHER_ADDRESS: | |
5702 | case RELOAD_FOR_INPADDR_ADDRESS: | |
5703 | case RELOAD_FOR_INPUT_ADDRESS: | |
5704 | case RELOAD_FOR_OPADDR_ADDR: | |
5705 | case RELOAD_FOR_OPERAND_ADDRESS: | |
5706 | case RELOAD_FOR_INPUT: | |
5707 | break; | |
5708 | case RELOAD_OTHER: | |
5709 | if (! rld[r].optional) | |
5710 | reload_override_in[r] = equiv; | |
5711 | /* Fall through. */ | |
5712 | default: | |
5713 | equiv = 0; | |
5714 | break; | |
5715 | } | |
32131a9c RK |
5716 | } |
5717 | ||
5718 | /* If we found an equivalent reg, say no code need be generated | |
5719 | to load it, and use it as our reload reg. */ | |
3ec2ea3e | 5720 | if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM) |
32131a9c | 5721 | { |
8ec450a4 | 5722 | int nr = HARD_REGNO_NREGS (regno, rld[r].mode); |
100338df | 5723 | int k; |
eceef4c9 | 5724 | rld[r].reg_rtx = equiv; |
32131a9c | 5725 | reload_inherited[r] = 1; |
100338df | 5726 | |
91d7e7ac R |
5727 | /* If reg_reloaded_valid is not set for this register, |
5728 | there might be a stale spill_reg_store lying around. | |
5729 | We must clear it, since otherwise emit_reload_insns | |
5730 | might delete the store. */ | |
5731 | if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno)) | |
5732 | spill_reg_store[regno] = NULL_RTX; | |
100338df JL |
5733 | /* If any of the hard registers in EQUIV are spill |
5734 | registers, mark them as in use for this insn. */ | |
5735 | for (k = 0; k < nr; k++) | |
be7ae2a4 | 5736 | { |
100338df JL |
5737 | i = spill_reg_order[regno + k]; |
5738 | if (i >= 0) | |
5739 | { | |
eceef4c9 BS |
5740 | mark_reload_reg_in_use (regno, rld[r].opnum, |
5741 | rld[r].when_needed, | |
8ec450a4 | 5742 | rld[r].mode); |
100338df JL |
5743 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, |
5744 | regno + k); | |
5745 | } | |
be7ae2a4 | 5746 | } |
32131a9c RK |
5747 | } |
5748 | } | |
5749 | ||
5750 | /* If we found a register to use already, or if this is an optional | |
5751 | reload, we are done. */ | |
eceef4c9 | 5752 | if (rld[r].reg_rtx != 0 || rld[r].optional != 0) |
32131a9c RK |
5753 | continue; |
5754 | ||
1d7254c5 KH |
5755 | #if 0 |
5756 | /* No longer needed for correct operation. Might or might | |
5757 | not give better code on the average. Want to experiment? */ | |
32131a9c RK |
5758 | |
5759 | /* See if there is a later reload that has a class different from our | |
5760 | class that intersects our class or that requires less register | |
5761 | than our reload. If so, we must allocate a register to this | |
5762 | reload now, since that reload might inherit a previous reload | |
5763 | and take the only available register in our class. Don't do this | |
5764 | for optional reloads since they will force all previous reloads | |
5765 | to be allocated. Also don't do this for reloads that have been | |
5766 | turned off. */ | |
5767 | ||
5768 | for (i = j + 1; i < n_reloads; i++) | |
5769 | { | |
5770 | int s = reload_order[i]; | |
5771 | ||
eceef4c9 BS |
5772 | if ((rld[s].in == 0 && rld[s].out == 0 |
5773 | && ! rld[s].secondary_p) | |
5774 | || rld[s].optional) | |
32131a9c RK |
5775 | continue; |
5776 | ||
eceef4c9 BS |
5777 | if ((rld[s].class != rld[r].class |
5778 | && reg_classes_intersect_p (rld[r].class, | |
5779 | rld[s].class)) | |
8ec450a4 | 5780 | || rld[s].nregs < rld[r].nregs) |
05d10675 | 5781 | break; |
32131a9c RK |
5782 | } |
5783 | ||
5784 | if (i == n_reloads) | |
5785 | continue; | |
5786 | ||
f5d8c9f4 | 5787 | allocate_reload_reg (chain, r, j == n_reloads - 1); |
32131a9c RK |
5788 | #endif |
5789 | } | |
5790 | ||
5791 | /* Now allocate reload registers for anything non-optional that | |
5792 | didn't get one yet. */ | |
5793 | for (j = 0; j < n_reloads; j++) | |
5794 | { | |
b3694847 | 5795 | int r = reload_order[j]; |
32131a9c RK |
5796 | |
5797 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 | 5798 | if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p) |
32131a9c RK |
5799 | continue; |
5800 | ||
5801 | /* Skip reloads that already have a register allocated or are | |
0f41302f | 5802 | optional. */ |
eceef4c9 | 5803 | if (rld[r].reg_rtx != 0 || rld[r].optional) |
32131a9c RK |
5804 | continue; |
5805 | ||
f5d8c9f4 | 5806 | if (! allocate_reload_reg (chain, r, j == n_reloads - 1)) |
32131a9c RK |
5807 | break; |
5808 | } | |
5809 | ||
5810 | /* If that loop got all the way, we have won. */ | |
5811 | if (j == n_reloads) | |
f5d8c9f4 BS |
5812 | { |
5813 | win = 1; | |
5814 | break; | |
5815 | } | |
32131a9c | 5816 | |
32131a9c | 5817 | /* Loop around and try without any inheritance. */ |
32131a9c RK |
5818 | } |
5819 | ||
f5d8c9f4 BS |
5820 | if (! win) |
5821 | { | |
5822 | /* First undo everything done by the failed attempt | |
5823 | to allocate with inheritance. */ | |
5824 | choose_reload_regs_init (chain, save_reload_reg_rtx); | |
5825 | ||
5826 | /* Some sanity tests to verify that the reloads found in the first | |
5827 | pass are identical to the ones we have now. */ | |
5828 | if (chain->n_reloads != n_reloads) | |
5829 | abort (); | |
5830 | ||
5831 | for (i = 0; i < n_reloads; i++) | |
5832 | { | |
5833 | if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0) | |
5834 | continue; | |
5835 | if (chain->rld[i].when_needed != rld[i].when_needed) | |
5836 | abort (); | |
5837 | for (j = 0; j < n_spills; j++) | |
5838 | if (spill_regs[j] == chain->rld[i].regno) | |
5839 | if (! set_reload_reg (j, i)) | |
5840 | failed_reload (chain->insn, i); | |
5841 | } | |
5842 | } | |
5843 | ||
32131a9c RK |
5844 | /* If we thought we could inherit a reload, because it seemed that |
5845 | nothing else wanted the same reload register earlier in the insn, | |
cb2afeb3 R |
5846 | verify that assumption, now that all reloads have been assigned. |
5847 | Likewise for reloads where reload_override_in has been set. */ | |
32131a9c | 5848 | |
cb2afeb3 R |
5849 | /* If doing expensive optimizations, do one preliminary pass that doesn't |
5850 | cancel any inheritance, but removes reloads that have been needed only | |
5851 | for reloads that we know can be inherited. */ | |
5852 | for (pass = flag_expensive_optimizations; pass >= 0; pass--) | |
32131a9c | 5853 | { |
cb2afeb3 | 5854 | for (j = 0; j < n_reloads; j++) |
029b38ff | 5855 | { |
b3694847 | 5856 | int r = reload_order[j]; |
cb2afeb3 | 5857 | rtx check_reg; |
eceef4c9 BS |
5858 | if (reload_inherited[r] && rld[r].reg_rtx) |
5859 | check_reg = rld[r].reg_rtx; | |
cb2afeb3 R |
5860 | else if (reload_override_in[r] |
5861 | && (GET_CODE (reload_override_in[r]) == REG | |
05d10675 | 5862 | || GET_CODE (reload_override_in[r]) == SUBREG)) |
cb2afeb3 R |
5863 | check_reg = reload_override_in[r]; |
5864 | else | |
5865 | continue; | |
c02cad8f BS |
5866 | if (! free_for_value_p (true_regnum (check_reg), rld[r].mode, |
5867 | rld[r].opnum, rld[r].when_needed, rld[r].in, | |
5868 | (reload_inherited[r] | |
5869 | ? rld[r].out : const0_rtx), | |
5870 | r, 1)) | |
029b38ff | 5871 | { |
cb2afeb3 R |
5872 | if (pass) |
5873 | continue; | |
5874 | reload_inherited[r] = 0; | |
5875 | reload_override_in[r] = 0; | |
029b38ff | 5876 | } |
cb2afeb3 R |
5877 | /* If we can inherit a RELOAD_FOR_INPUT, or can use a |
5878 | reload_override_in, then we do not need its related | |
5879 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads; | |
5880 | likewise for other reload types. | |
5881 | We handle this by removing a reload when its only replacement | |
5882 | is mentioned in reload_in of the reload we are going to inherit. | |
5883 | A special case are auto_inc expressions; even if the input is | |
5884 | inherited, we still need the address for the output. We can | |
fe92fe26 | 5885 | recognize them because they have RELOAD_OUT set to RELOAD_IN. |
cb2afeb3 R |
5886 | If we suceeded removing some reload and we are doing a preliminary |
5887 | pass just to remove such reloads, make another pass, since the | |
5888 | removal of one reload might allow us to inherit another one. */ | |
eceef4c9 BS |
5889 | else if (rld[r].in |
5890 | && rld[r].out != rld[r].in | |
5891 | && remove_address_replacements (rld[r].in) && pass) | |
cb2afeb3 | 5892 | pass = 2; |
32131a9c RK |
5893 | } |
5894 | } | |
5895 | ||
5896 | /* Now that reload_override_in is known valid, | |
5897 | actually override reload_in. */ | |
5898 | for (j = 0; j < n_reloads; j++) | |
5899 | if (reload_override_in[j]) | |
eceef4c9 | 5900 | rld[j].in = reload_override_in[j]; |
32131a9c RK |
5901 | |
5902 | /* If this reload won't be done because it has been cancelled or is | |
5903 | optional and not inherited, clear reload_reg_rtx so other | |
5904 | routines (such as subst_reloads) don't get confused. */ | |
5905 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
5906 | if (rld[j].reg_rtx != 0 |
5907 | && ((rld[j].optional && ! reload_inherited[j]) | |
5908 | || (rld[j].in == 0 && rld[j].out == 0 | |
5909 | && ! rld[j].secondary_p))) | |
be7ae2a4 | 5910 | { |
eceef4c9 | 5911 | int regno = true_regnum (rld[j].reg_rtx); |
be7ae2a4 RK |
5912 | |
5913 | if (spill_reg_order[regno] >= 0) | |
eceef4c9 | 5914 | clear_reload_reg_in_use (regno, rld[j].opnum, |
8ec450a4 | 5915 | rld[j].when_needed, rld[j].mode); |
eceef4c9 | 5916 | rld[j].reg_rtx = 0; |
c0029be5 | 5917 | reload_spill_index[j] = -1; |
be7ae2a4 | 5918 | } |
32131a9c RK |
5919 | |
5920 | /* Record which pseudos and which spill regs have output reloads. */ | |
5921 | for (j = 0; j < n_reloads; j++) | |
5922 | { | |
b3694847 | 5923 | int r = reload_order[j]; |
32131a9c RK |
5924 | |
5925 | i = reload_spill_index[r]; | |
5926 | ||
e6e52be0 | 5927 | /* I is nonneg if this reload uses a register. |
eceef4c9 | 5928 | If rld[r].reg_rtx is 0, this is an optional reload |
32131a9c | 5929 | that we opted to ignore. */ |
eceef4c9 BS |
5930 | if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG |
5931 | && rld[r].reg_rtx != 0) | |
32131a9c | 5932 | { |
b3694847 | 5933 | int nregno = REGNO (rld[r].out_reg); |
372e033b RS |
5934 | int nr = 1; |
5935 | ||
5936 | if (nregno < FIRST_PSEUDO_REGISTER) | |
8ec450a4 | 5937 | nr = HARD_REGNO_NREGS (nregno, rld[r].mode); |
32131a9c RK |
5938 | |
5939 | while (--nr >= 0) | |
372e033b RS |
5940 | reg_has_output_reload[nregno + nr] = 1; |
5941 | ||
5942 | if (i >= 0) | |
32131a9c | 5943 | { |
8ec450a4 | 5944 | nr = HARD_REGNO_NREGS (i, rld[r].mode); |
372e033b | 5945 | while (--nr >= 0) |
e6e52be0 | 5946 | SET_HARD_REG_BIT (reg_is_output_reload, i + nr); |
32131a9c RK |
5947 | } |
5948 | ||
eceef4c9 BS |
5949 | if (rld[r].when_needed != RELOAD_OTHER |
5950 | && rld[r].when_needed != RELOAD_FOR_OUTPUT | |
5951 | && rld[r].when_needed != RELOAD_FOR_INSN) | |
32131a9c RK |
5952 | abort (); |
5953 | } | |
5954 | } | |
5955 | } | |
cb2afeb3 R |
5956 | |
5957 | /* Deallocate the reload register for reload R. This is called from | |
5958 | remove_address_replacements. */ | |
1d813780 | 5959 | |
cb2afeb3 R |
5960 | void |
5961 | deallocate_reload_reg (r) | |
5962 | int r; | |
5963 | { | |
5964 | int regno; | |
5965 | ||
eceef4c9 | 5966 | if (! rld[r].reg_rtx) |
cb2afeb3 | 5967 | return; |
eceef4c9 BS |
5968 | regno = true_regnum (rld[r].reg_rtx); |
5969 | rld[r].reg_rtx = 0; | |
cb2afeb3 | 5970 | if (spill_reg_order[regno] >= 0) |
eceef4c9 | 5971 | clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed, |
8ec450a4 | 5972 | rld[r].mode); |
cb2afeb3 R |
5973 | reload_spill_index[r] = -1; |
5974 | } | |
32131a9c | 5975 | \f |
e9a25f70 | 5976 | /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two |
546b63fb RK |
5977 | reloads of the same item for fear that we might not have enough reload |
5978 | registers. However, normally they will get the same reload register | |
05d10675 | 5979 | and hence actually need not be loaded twice. |
546b63fb RK |
5980 | |
5981 | Here we check for the most common case of this phenomenon: when we have | |
5982 | a number of reloads for the same object, each of which were allocated | |
5983 | the same reload_reg_rtx, that reload_reg_rtx is not used for any other | |
5984 | reload, and is not modified in the insn itself. If we find such, | |
5985 | merge all the reloads and set the resulting reload to RELOAD_OTHER. | |
5986 | This will not increase the number of spill registers needed and will | |
5987 | prevent redundant code. */ | |
5988 | ||
546b63fb RK |
5989 | static void |
5990 | merge_assigned_reloads (insn) | |
5991 | rtx insn; | |
5992 | { | |
5993 | int i, j; | |
5994 | ||
5995 | /* Scan all the reloads looking for ones that only load values and | |
5996 | are not already RELOAD_OTHER and ones whose reload_reg_rtx are | |
5997 | assigned and not modified by INSN. */ | |
5998 | ||
5999 | for (i = 0; i < n_reloads; i++) | |
6000 | { | |
d668e863 R |
6001 | int conflicting_input = 0; |
6002 | int max_input_address_opnum = -1; | |
6003 | int min_conflicting_input_opnum = MAX_RECOG_OPERANDS; | |
6004 | ||
eceef4c9 BS |
6005 | if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER |
6006 | || rld[i].out != 0 || rld[i].reg_rtx == 0 | |
6007 | || reg_set_p (rld[i].reg_rtx, insn)) | |
546b63fb RK |
6008 | continue; |
6009 | ||
6010 | /* Look at all other reloads. Ensure that the only use of this | |
6011 | reload_reg_rtx is in a reload that just loads the same value | |
6012 | as we do. Note that any secondary reloads must be of the identical | |
6013 | class since the values, modes, and result registers are the | |
6014 | same, so we need not do anything with any secondary reloads. */ | |
6015 | ||
6016 | for (j = 0; j < n_reloads; j++) | |
6017 | { | |
eceef4c9 BS |
6018 | if (i == j || rld[j].reg_rtx == 0 |
6019 | || ! reg_overlap_mentioned_p (rld[j].reg_rtx, | |
6020 | rld[i].reg_rtx)) | |
546b63fb RK |
6021 | continue; |
6022 | ||
eceef4c9 BS |
6023 | if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6024 | && rld[j].opnum > max_input_address_opnum) | |
6025 | max_input_address_opnum = rld[j].opnum; | |
d668e863 | 6026 | |
546b63fb | 6027 | /* If the reload regs aren't exactly the same (e.g, different modes) |
d668e863 R |
6028 | or if the values are different, we can't merge this reload. |
6029 | But if it is an input reload, we might still merge | |
6030 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */ | |
546b63fb | 6031 | |
eceef4c9 BS |
6032 | if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) |
6033 | || rld[j].out != 0 || rld[j].in == 0 | |
6034 | || ! rtx_equal_p (rld[i].in, rld[j].in)) | |
d668e863 | 6035 | { |
eceef4c9 BS |
6036 | if (rld[j].when_needed != RELOAD_FOR_INPUT |
6037 | || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS | |
6038 | || rld[i].opnum > rld[j].opnum) | |
6039 | && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS)) | |
d668e863 R |
6040 | break; |
6041 | conflicting_input = 1; | |
eceef4c9 BS |
6042 | if (min_conflicting_input_opnum > rld[j].opnum) |
6043 | min_conflicting_input_opnum = rld[j].opnum; | |
d668e863 | 6044 | } |
546b63fb RK |
6045 | } |
6046 | ||
6047 | /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if | |
6048 | we, in fact, found any matching reloads. */ | |
6049 | ||
d668e863 R |
6050 | if (j == n_reloads |
6051 | && max_input_address_opnum <= min_conflicting_input_opnum) | |
546b63fb RK |
6052 | { |
6053 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
6054 | if (i != j && rld[j].reg_rtx != 0 |
6055 | && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) | |
d668e863 | 6056 | && (! conflicting_input |
eceef4c9 BS |
6057 | || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6058 | || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS)) | |
546b63fb | 6059 | { |
eceef4c9 BS |
6060 | rld[i].when_needed = RELOAD_OTHER; |
6061 | rld[j].in = 0; | |
efdb3590 | 6062 | reload_spill_index[j] = -1; |
546b63fb RK |
6063 | transfer_replacements (i, j); |
6064 | } | |
6065 | ||
6066 | /* If this is now RELOAD_OTHER, look for any reloads that load | |
6067 | parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS | |
6068 | if they were for inputs, RELOAD_OTHER for outputs. Note that | |
6069 | this test is equivalent to looking for reloads for this operand | |
6070 | number. */ | |
6071 | ||
eceef4c9 | 6072 | if (rld[i].when_needed == RELOAD_OTHER) |
546b63fb | 6073 | for (j = 0; j < n_reloads; j++) |
eceef4c9 | 6074 | if (rld[j].in != 0 |
91667711 | 6075 | && rld[j].when_needed != RELOAD_OTHER |
eceef4c9 BS |
6076 | && reg_overlap_mentioned_for_reload_p (rld[j].in, |
6077 | rld[i].in)) | |
6078 | rld[j].when_needed | |
91667711 SC |
6079 | = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
6080 | || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
47c8cf91 | 6081 | ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER); |
546b63fb RK |
6082 | } |
6083 | } | |
05d10675 | 6084 | } |
546b63fb | 6085 | \f |
367b1cf5 BS |
6086 | /* These arrays are filled by emit_reload_insns and its subroutines. */ |
6087 | static rtx input_reload_insns[MAX_RECOG_OPERANDS]; | |
6088 | static rtx other_input_address_reload_insns = 0; | |
6089 | static rtx other_input_reload_insns = 0; | |
6090 | static rtx input_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6091 | static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6092 | static rtx output_reload_insns[MAX_RECOG_OPERANDS]; | |
6093 | static rtx output_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6094 | static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
6095 | static rtx operand_reload_insns = 0; | |
6096 | static rtx other_operand_reload_insns = 0; | |
6097 | static rtx other_output_reload_insns[MAX_RECOG_OPERANDS]; | |
6098 | ||
6099 | /* Values to be put in spill_reg_store are put here first. */ | |
6100 | static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
6101 | static HARD_REG_SET reg_reloaded_died; | |
6102 | ||
6103 | /* Generate insns to perform reload RL, which is for the insn in CHAIN and | |
6104 | has the number J. OLD contains the value to be used as input. */ | |
770ae6cc | 6105 | |
32131a9c | 6106 | static void |
367b1cf5 | 6107 | emit_input_reload_insns (chain, rl, old, j) |
7609e720 | 6108 | struct insn_chain *chain; |
367b1cf5 BS |
6109 | struct reload *rl; |
6110 | rtx old; | |
6111 | int j; | |
32131a9c | 6112 | { |
7609e720 | 6113 | rtx insn = chain->insn; |
b3694847 | 6114 | rtx reloadreg = rl->reg_rtx; |
367b1cf5 BS |
6115 | rtx oldequiv_reg = 0; |
6116 | rtx oldequiv = 0; | |
6117 | int special = 0; | |
6118 | enum machine_mode mode; | |
6119 | rtx *where; | |
6120 | ||
6121 | /* Determine the mode to reload in. | |
6122 | This is very tricky because we have three to choose from. | |
6123 | There is the mode the insn operand wants (rl->inmode). | |
6124 | There is the mode of the reload register RELOADREG. | |
6125 | There is the intrinsic mode of the operand, which we could find | |
6126 | by stripping some SUBREGs. | |
6127 | It turns out that RELOADREG's mode is irrelevant: | |
6128 | we can change that arbitrarily. | |
6129 | ||
6130 | Consider (SUBREG:SI foo:QI) as an operand that must be SImode; | |
6131 | then the reload reg may not support QImode moves, so use SImode. | |
6132 | If foo is in memory due to spilling a pseudo reg, this is safe, | |
6133 | because the QImode value is in the least significant part of a | |
6134 | slot big enough for a SImode. If foo is some other sort of | |
6135 | memory reference, then it is impossible to reload this case, | |
6136 | so previous passes had better make sure this never happens. | |
6137 | ||
6138 | Then consider a one-word union which has SImode and one of its | |
6139 | members is a float, being fetched as (SUBREG:SF union:SI). | |
6140 | We must fetch that as SFmode because we could be loading into | |
6141 | a float-only register. In this case OLD's mode is correct. | |
6142 | ||
6143 | Consider an immediate integer: it has VOIDmode. Here we need | |
6144 | to get a mode from something else. | |
6145 | ||
6146 | In some cases, there is a fourth mode, the operand's | |
6147 | containing mode. If the insn specifies a containing mode for | |
6148 | this operand, it overrides all others. | |
6149 | ||
6150 | I am not sure whether the algorithm here is always right, | |
6151 | but it does the right things in those cases. */ | |
6152 | ||
6153 | mode = GET_MODE (old); | |
6154 | if (mode == VOIDmode) | |
6155 | mode = rl->inmode; | |
7609e720 | 6156 | |
367b1cf5 BS |
6157 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
6158 | /* If we need a secondary register for this operation, see if | |
6159 | the value is already in a register in that class. Don't | |
6160 | do this if the secondary register will be used as a scratch | |
6161 | register. */ | |
6162 | ||
6163 | if (rl->secondary_in_reload >= 0 | |
6164 | && rl->secondary_in_icode == CODE_FOR_nothing | |
6165 | && optimize) | |
6166 | oldequiv | |
6167 | = find_equiv_reg (old, insn, | |
6168 | rld[rl->secondary_in_reload].class, | |
9714cf43 | 6169 | -1, NULL, 0, mode); |
367b1cf5 | 6170 | #endif |
e6e52be0 | 6171 | |
367b1cf5 BS |
6172 | /* If reloading from memory, see if there is a register |
6173 | that already holds the same value. If so, reload from there. | |
6174 | We can pass 0 as the reload_reg_p argument because | |
6175 | any other reload has either already been emitted, | |
6176 | in which case find_equiv_reg will see the reload-insn, | |
6177 | or has yet to be emitted, in which case it doesn't matter | |
6178 | because we will use this equiv reg right away. */ | |
6179 | ||
6180 | if (oldequiv == 0 && optimize | |
6181 | && (GET_CODE (old) == MEM | |
6182 | || (GET_CODE (old) == REG | |
6183 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
6184 | && reg_renumber[REGNO (old)] < 0))) | |
9714cf43 | 6185 | oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode); |
367b1cf5 BS |
6186 | |
6187 | if (oldequiv) | |
6188 | { | |
770ae6cc | 6189 | unsigned int regno = true_regnum (oldequiv); |
367b1cf5 BS |
6190 | |
6191 | /* Don't use OLDEQUIV if any other reload changes it at an | |
6192 | earlier stage of this insn or at this stage. */ | |
c02cad8f BS |
6193 | if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed, |
6194 | rl->in, const0_rtx, j, 0)) | |
367b1cf5 BS |
6195 | oldequiv = 0; |
6196 | ||
6197 | /* If it is no cheaper to copy from OLDEQUIV into the | |
6198 | reload register than it would be to move from memory, | |
6199 | don't use it. Likewise, if we need a secondary register | |
6d2f8887 | 6200 | or memory. */ |
367b1cf5 BS |
6201 | |
6202 | if (oldequiv != 0 | |
6203 | && ((REGNO_REG_CLASS (regno) != rl->class | |
e56b4594 | 6204 | && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno), |
367b1cf5 BS |
6205 | rl->class) |
6206 | >= MEMORY_MOVE_COST (mode, rl->class, 1))) | |
6207 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
6208 | || (SECONDARY_INPUT_RELOAD_CLASS (rl->class, | |
6209 | mode, oldequiv) | |
6210 | != NO_REGS) | |
6211 | #endif | |
6212 | #ifdef SECONDARY_MEMORY_NEEDED | |
6213 | || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno), | |
6214 | rl->class, | |
6215 | mode) | |
6216 | #endif | |
6217 | )) | |
6218 | oldequiv = 0; | |
6219 | } | |
32131a9c | 6220 | |
367b1cf5 BS |
6221 | /* delete_output_reload is only invoked properly if old contains |
6222 | the original pseudo register. Since this is replaced with a | |
6223 | hard reg when RELOAD_OVERRIDE_IN is set, see if we can | |
6224 | find the pseudo in RELOAD_IN_REG. */ | |
6225 | if (oldequiv == 0 | |
6226 | && reload_override_in[j] | |
6227 | && GET_CODE (rl->in_reg) == REG) | |
6228 | { | |
6229 | oldequiv = old; | |
6230 | old = rl->in_reg; | |
6231 | } | |
6232 | if (oldequiv == 0) | |
6233 | oldequiv = old; | |
6234 | else if (GET_CODE (oldequiv) == REG) | |
6235 | oldequiv_reg = oldequiv; | |
6236 | else if (GET_CODE (oldequiv) == SUBREG) | |
6237 | oldequiv_reg = SUBREG_REG (oldequiv); | |
6238 | ||
6239 | /* If we are reloading from a register that was recently stored in | |
6240 | with an output-reload, see if we can prove there was | |
6241 | actually no need to store the old value in it. */ | |
6242 | ||
6243 | if (optimize && GET_CODE (oldequiv) == REG | |
6244 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER | |
6245 | && spill_reg_store[REGNO (oldequiv)] | |
6246 | && GET_CODE (old) == REG | |
6247 | && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) | |
6248 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6249 | rl->out_reg))) | |
6250 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6251 | ||
6252 | /* Encapsulate both RELOADREG and OLDEQUIV into that mode, | |
6253 | then load RELOADREG from OLDEQUIV. Note that we cannot use | |
6254 | gen_lowpart_common since it can do the wrong thing when | |
6255 | RELOADREG has a multi-word mode. Note that RELOADREG | |
6256 | must always be a REG here. */ | |
6257 | ||
6258 | if (GET_MODE (reloadreg) != mode) | |
6259 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
6260 | while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) | |
6261 | oldequiv = SUBREG_REG (oldequiv); | |
6262 | if (GET_MODE (oldequiv) != VOIDmode | |
6263 | && mode != GET_MODE (oldequiv)) | |
ddef6bc7 | 6264 | oldequiv = gen_lowpart_SUBREG (mode, oldequiv); |
367b1cf5 BS |
6265 | |
6266 | /* Switch to the right place to emit the reload insns. */ | |
6267 | switch (rl->when_needed) | |
6268 | { | |
6269 | case RELOAD_OTHER: | |
6270 | where = &other_input_reload_insns; | |
6271 | break; | |
6272 | case RELOAD_FOR_INPUT: | |
6273 | where = &input_reload_insns[rl->opnum]; | |
6274 | break; | |
6275 | case RELOAD_FOR_INPUT_ADDRESS: | |
6276 | where = &input_address_reload_insns[rl->opnum]; | |
6277 | break; | |
6278 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6279 | where = &inpaddr_address_reload_insns[rl->opnum]; | |
6280 | break; | |
6281 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
6282 | where = &output_address_reload_insns[rl->opnum]; | |
6283 | break; | |
6284 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
6285 | where = &outaddr_address_reload_insns[rl->opnum]; | |
6286 | break; | |
6287 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6288 | where = &operand_reload_insns; | |
6289 | break; | |
6290 | case RELOAD_FOR_OPADDR_ADDR: | |
6291 | where = &other_operand_reload_insns; | |
6292 | break; | |
6293 | case RELOAD_FOR_OTHER_ADDRESS: | |
6294 | where = &other_input_address_reload_insns; | |
6295 | break; | |
6296 | default: | |
6297 | abort (); | |
6298 | } | |
546b63fb | 6299 | |
367b1cf5 | 6300 | push_to_sequence (*where); |
32131a9c | 6301 | |
367b1cf5 BS |
6302 | /* Auto-increment addresses must be reloaded in a special way. */ |
6303 | if (rl->out && ! rl->out_reg) | |
32131a9c | 6304 | { |
367b1cf5 BS |
6305 | /* We are not going to bother supporting the case where a |
6306 | incremented register can't be copied directly from | |
6307 | OLDEQUIV since this seems highly unlikely. */ | |
6308 | if (rl->secondary_in_reload >= 0) | |
6309 | abort (); | |
32131a9c | 6310 | |
367b1cf5 BS |
6311 | if (reload_inherited[j]) |
6312 | oldequiv = reloadreg; | |
cb2afeb3 | 6313 | |
367b1cf5 | 6314 | old = XEXP (rl->in_reg, 0); |
32131a9c | 6315 | |
367b1cf5 BS |
6316 | if (optimize && GET_CODE (oldequiv) == REG |
6317 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER | |
6318 | && spill_reg_store[REGNO (oldequiv)] | |
6319 | && GET_CODE (old) == REG | |
6320 | && (dead_or_set_p (insn, | |
6321 | spill_reg_stored_to[REGNO (oldequiv)]) | |
6322 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6323 | old))) | |
6324 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6325 | ||
6326 | /* Prevent normal processing of this reload. */ | |
6327 | special = 1; | |
6328 | /* Output a special code sequence for this case. */ | |
6329 | new_spill_reg_store[REGNO (reloadreg)] | |
6330 | = inc_for_reload (reloadreg, oldequiv, rl->out, | |
6331 | rl->inc); | |
6332 | } | |
32131a9c | 6333 | |
367b1cf5 BS |
6334 | /* If we are reloading a pseudo-register that was set by the previous |
6335 | insn, see if we can get rid of that pseudo-register entirely | |
6336 | by redirecting the previous insn into our reload register. */ | |
6337 | ||
6338 | else if (optimize && GET_CODE (old) == REG | |
6339 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
6340 | && dead_or_set_p (insn, old) | |
6341 | /* This is unsafe if some other reload | |
6342 | uses the same reg first. */ | |
ff6534ad | 6343 | && ! conflicts_with_override (reloadreg) |
c02cad8f BS |
6344 | && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum, |
6345 | rl->when_needed, old, rl->out, j, 0)) | |
367b1cf5 BS |
6346 | { |
6347 | rtx temp = PREV_INSN (insn); | |
6348 | while (temp && GET_CODE (temp) == NOTE) | |
6349 | temp = PREV_INSN (temp); | |
6350 | if (temp | |
6351 | && GET_CODE (temp) == INSN | |
6352 | && GET_CODE (PATTERN (temp)) == SET | |
6353 | && SET_DEST (PATTERN (temp)) == old | |
6354 | /* Make sure we can access insn_operand_constraint. */ | |
6355 | && asm_noperands (PATTERN (temp)) < 0 | |
6356 | /* This is unsafe if prev insn rejects our reload reg. */ | |
6357 | && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint, | |
6358 | reloadreg) | |
6359 | /* This is unsafe if operand occurs more than once in current | |
6360 | insn. Perhaps some occurrences aren't reloaded. */ | |
4b983fdc | 6361 | && count_occurrences (PATTERN (insn), old, 0) == 1 |
367b1cf5 BS |
6362 | /* Don't risk splitting a matching pair of operands. */ |
6363 | && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp)))) | |
6364 | { | |
6365 | /* Store into the reload register instead of the pseudo. */ | |
6366 | SET_DEST (PATTERN (temp)) = reloadreg; | |
6367 | ||
6368 | /* If the previous insn is an output reload, the source is | |
6369 | a reload register, and its spill_reg_store entry will | |
6370 | contain the previous destination. This is now | |
6371 | invalid. */ | |
6372 | if (GET_CODE (SET_SRC (PATTERN (temp))) == REG | |
6373 | && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER) | |
32131a9c | 6374 | { |
367b1cf5 BS |
6375 | spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0; |
6376 | spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; | |
32131a9c RK |
6377 | } |
6378 | ||
367b1cf5 BS |
6379 | /* If these are the only uses of the pseudo reg, |
6380 | pretend for GDB it lives in the reload reg we used. */ | |
6381 | if (REG_N_DEATHS (REGNO (old)) == 1 | |
6382 | && REG_N_SETS (REGNO (old)) == 1) | |
cb2afeb3 | 6383 | { |
367b1cf5 BS |
6384 | reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx); |
6385 | alter_reg (REGNO (old), -1); | |
32131a9c | 6386 | } |
07875628 | 6387 | special = 1; |
367b1cf5 BS |
6388 | } |
6389 | } | |
32131a9c | 6390 | |
367b1cf5 | 6391 | /* We can't do that, so output an insn to load RELOADREG. */ |
32131a9c | 6392 | |
367b1cf5 BS |
6393 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
6394 | /* If we have a secondary reload, pick up the secondary register | |
6395 | and icode, if any. If OLDEQUIV and OLD are different or | |
6396 | if this is an in-out reload, recompute whether or not we | |
6397 | still need a secondary register and what the icode should | |
6398 | be. If we still need a secondary register and the class or | |
6399 | icode is different, go back to reloading from OLD if using | |
6400 | OLDEQUIV means that we got the wrong type of register. We | |
6401 | cannot have different class or icode due to an in-out reload | |
6402 | because we don't make such reloads when both the input and | |
6403 | output need secondary reload registers. */ | |
6404 | ||
07875628 | 6405 | if (! special && rl->secondary_in_reload >= 0) |
367b1cf5 BS |
6406 | { |
6407 | rtx second_reload_reg = 0; | |
6408 | int secondary_reload = rl->secondary_in_reload; | |
6409 | rtx real_oldequiv = oldequiv; | |
6410 | rtx real_old = old; | |
6411 | rtx tmp; | |
6412 | enum insn_code icode; | |
6413 | ||
6414 | /* If OLDEQUIV is a pseudo with a MEM, get the real MEM | |
6415 | and similarly for OLD. | |
6416 | See comments in get_secondary_reload in reload.c. */ | |
6417 | /* If it is a pseudo that cannot be replaced with its | |
6418 | equivalent MEM, we must fall back to reload_in, which | |
6419 | will have all the necessary substitutions registered. | |
6420 | Likewise for a pseudo that can't be replaced with its | |
6421 | equivalent constant. | |
6422 | ||
6423 | Take extra care for subregs of such pseudos. Note that | |
6424 | we cannot use reg_equiv_mem in this case because it is | |
6425 | not in the right mode. */ | |
6426 | ||
6427 | tmp = oldequiv; | |
6428 | if (GET_CODE (tmp) == SUBREG) | |
6429 | tmp = SUBREG_REG (tmp); | |
6430 | if (GET_CODE (tmp) == REG | |
6431 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER | |
6432 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6433 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6434 | { | |
6435 | if (! reg_equiv_mem[REGNO (tmp)] | |
6436 | || num_not_at_initial_offset | |
6437 | || GET_CODE (oldequiv) == SUBREG) | |
6438 | real_oldequiv = rl->in; | |
6439 | else | |
6440 | real_oldequiv = reg_equiv_mem[REGNO (tmp)]; | |
6441 | } | |
32131a9c | 6442 | |
367b1cf5 BS |
6443 | tmp = old; |
6444 | if (GET_CODE (tmp) == SUBREG) | |
6445 | tmp = SUBREG_REG (tmp); | |
6446 | if (GET_CODE (tmp) == REG | |
6447 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER | |
6448 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6449 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6450 | { | |
6451 | if (! reg_equiv_mem[REGNO (tmp)] | |
6452 | || num_not_at_initial_offset | |
6453 | || GET_CODE (old) == SUBREG) | |
6454 | real_old = rl->in; | |
6455 | else | |
6456 | real_old = reg_equiv_mem[REGNO (tmp)]; | |
6457 | } | |
6458 | ||
6459 | second_reload_reg = rld[secondary_reload].reg_rtx; | |
6460 | icode = rl->secondary_in_icode; | |
6461 | ||
6462 | if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) | |
6463 | || (rl->in != 0 && rl->out != 0)) | |
6464 | { | |
6465 | enum reg_class new_class | |
6466 | = SECONDARY_INPUT_RELOAD_CLASS (rl->class, | |
6467 | mode, real_oldequiv); | |
6468 | ||
6469 | if (new_class == NO_REGS) | |
6470 | second_reload_reg = 0; | |
6471 | else | |
32131a9c | 6472 | { |
367b1cf5 BS |
6473 | enum insn_code new_icode; |
6474 | enum machine_mode new_mode; | |
6475 | ||
6476 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], | |
6477 | REGNO (second_reload_reg))) | |
6478 | oldequiv = old, real_oldequiv = real_old; | |
6479 | else | |
32131a9c | 6480 | { |
367b1cf5 BS |
6481 | new_icode = reload_in_optab[(int) mode]; |
6482 | if (new_icode != CODE_FOR_nothing | |
6483 | && ((insn_data[(int) new_icode].operand[0].predicate | |
6484 | && ! ((*insn_data[(int) new_icode].operand[0].predicate) | |
6485 | (reloadreg, mode))) | |
6486 | || (insn_data[(int) new_icode].operand[1].predicate | |
6487 | && ! ((*insn_data[(int) new_icode].operand[1].predicate) | |
6488 | (real_oldequiv, mode))))) | |
6489 | new_icode = CODE_FOR_nothing; | |
6490 | ||
6491 | if (new_icode == CODE_FOR_nothing) | |
6492 | new_mode = mode; | |
6493 | else | |
6494 | new_mode = insn_data[(int) new_icode].operand[2].mode; | |
d30e8ef0 | 6495 | |
367b1cf5 | 6496 | if (GET_MODE (second_reload_reg) != new_mode) |
32131a9c | 6497 | { |
367b1cf5 BS |
6498 | if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg), |
6499 | new_mode)) | |
6500 | oldequiv = old, real_oldequiv = real_old; | |
6501 | else | |
6502 | second_reload_reg | |
6503 | = gen_rtx_REG (new_mode, | |
6504 | REGNO (second_reload_reg)); | |
32131a9c | 6505 | } |
32131a9c RK |
6506 | } |
6507 | } | |
367b1cf5 | 6508 | } |
32131a9c | 6509 | |
367b1cf5 BS |
6510 | /* If we still need a secondary reload register, check |
6511 | to see if it is being used as a scratch or intermediate | |
6512 | register and generate code appropriately. If we need | |
6513 | a scratch register, use REAL_OLDEQUIV since the form of | |
6514 | the insn may depend on the actual address if it is | |
6515 | a MEM. */ | |
546b63fb | 6516 | |
367b1cf5 BS |
6517 | if (second_reload_reg) |
6518 | { | |
6519 | if (icode != CODE_FOR_nothing) | |
32131a9c | 6520 | { |
367b1cf5 BS |
6521 | emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, |
6522 | second_reload_reg)); | |
07875628 | 6523 | special = 1; |
367b1cf5 BS |
6524 | } |
6525 | else | |
6526 | { | |
6527 | /* See if we need a scratch register to load the | |
6528 | intermediate register (a tertiary reload). */ | |
6529 | enum insn_code tertiary_icode | |
6530 | = rld[secondary_reload].secondary_in_icode; | |
1554c2c6 | 6531 | |
367b1cf5 BS |
6532 | if (tertiary_icode != CODE_FOR_nothing) |
6533 | { | |
6534 | rtx third_reload_reg | |
6535 | = rld[rld[secondary_reload].secondary_in_reload].reg_rtx; | |
1554c2c6 | 6536 | |
367b1cf5 BS |
6537 | emit_insn ((GEN_FCN (tertiary_icode) |
6538 | (second_reload_reg, real_oldequiv, | |
6539 | third_reload_reg))); | |
6540 | } | |
6541 | else | |
6542 | gen_reload (second_reload_reg, real_oldequiv, | |
6543 | rl->opnum, | |
6544 | rl->when_needed); | |
32131a9c | 6545 | |
367b1cf5 BS |
6546 | oldequiv = second_reload_reg; |
6547 | } | |
6548 | } | |
6549 | } | |
6550 | #endif | |
32131a9c | 6551 | |
07875628 | 6552 | if (! special && ! rtx_equal_p (reloadreg, oldequiv)) |
367b1cf5 BS |
6553 | { |
6554 | rtx real_oldequiv = oldequiv; | |
6555 | ||
6556 | if ((GET_CODE (oldequiv) == REG | |
6557 | && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER | |
6558 | && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0 | |
6559 | || reg_equiv_constant[REGNO (oldequiv)] != 0)) | |
6560 | || (GET_CODE (oldequiv) == SUBREG | |
6561 | && GET_CODE (SUBREG_REG (oldequiv)) == REG | |
6562 | && (REGNO (SUBREG_REG (oldequiv)) | |
6563 | >= FIRST_PSEUDO_REGISTER) | |
6564 | && ((reg_equiv_memory_loc | |
6565 | [REGNO (SUBREG_REG (oldequiv))] != 0) | |
6566 | || (reg_equiv_constant | |
716120a7 JJ |
6567 | [REGNO (SUBREG_REG (oldequiv))] != 0))) |
6568 | || (CONSTANT_P (oldequiv) | |
6569 | && PREFERRED_RELOAD_CLASS (oldequiv, | |
6570 | REGNO_REG_CLASS (REGNO (reloadreg))) == NO_REGS)) | |
367b1cf5 BS |
6571 | real_oldequiv = rl->in; |
6572 | gen_reload (reloadreg, real_oldequiv, rl->opnum, | |
6573 | rl->when_needed); | |
6574 | } | |
32131a9c | 6575 | |
94bd63e5 AH |
6576 | if (flag_non_call_exceptions) |
6577 | copy_eh_notes (insn, get_insns ()); | |
6578 | ||
367b1cf5 BS |
6579 | /* End this sequence. */ |
6580 | *where = get_insns (); | |
6581 | end_sequence (); | |
94bd63e5 | 6582 | |
367b1cf5 BS |
6583 | /* Update reload_override_in so that delete_address_reloads_1 |
6584 | can see the actual register usage. */ | |
6585 | if (oldequiv_reg) | |
6586 | reload_override_in[j] = oldequiv; | |
6587 | } | |
32131a9c | 6588 | |
367b1cf5 BS |
6589 | /* Generate insns to for the output reload RL, which is for the insn described |
6590 | by CHAIN and has the number J. */ | |
6591 | static void | |
6592 | emit_output_reload_insns (chain, rl, j) | |
6593 | struct insn_chain *chain; | |
6594 | struct reload *rl; | |
6595 | int j; | |
6596 | { | |
6597 | rtx reloadreg = rl->reg_rtx; | |
6598 | rtx insn = chain->insn; | |
6599 | int special = 0; | |
6600 | rtx old = rl->out; | |
6601 | enum machine_mode mode = GET_MODE (old); | |
6602 | rtx p; | |
32131a9c | 6603 | |
367b1cf5 BS |
6604 | if (rl->when_needed == RELOAD_OTHER) |
6605 | start_sequence (); | |
6606 | else | |
6607 | push_to_sequence (output_reload_insns[rl->opnum]); | |
32131a9c | 6608 | |
367b1cf5 BS |
6609 | /* Determine the mode to reload in. |
6610 | See comments above (for input reloading). */ | |
32131a9c | 6611 | |
367b1cf5 BS |
6612 | if (mode == VOIDmode) |
6613 | { | |
6614 | /* VOIDmode should never happen for an output. */ | |
6615 | if (asm_noperands (PATTERN (insn)) < 0) | |
6616 | /* It's the compiler's fault. */ | |
6617 | fatal_insn ("VOIDmode on an output", insn); | |
6618 | error_for_asm (insn, "output operand is constant in `asm'"); | |
6619 | /* Prevent crash--use something we know is valid. */ | |
6620 | mode = word_mode; | |
6621 | old = gen_rtx_REG (mode, REGNO (reloadreg)); | |
6622 | } | |
546b63fb | 6623 | |
367b1cf5 BS |
6624 | if (GET_MODE (reloadreg) != mode) |
6625 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
32131a9c | 6626 | |
367b1cf5 | 6627 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
32131a9c | 6628 | |
367b1cf5 BS |
6629 | /* If we need two reload regs, set RELOADREG to the intermediate |
6630 | one, since it will be stored into OLD. We might need a secondary | |
6631 | register only for an input reload, so check again here. */ | |
32131a9c | 6632 | |
367b1cf5 BS |
6633 | if (rl->secondary_out_reload >= 0) |
6634 | { | |
6635 | rtx real_old = old; | |
cb2afeb3 | 6636 | |
367b1cf5 BS |
6637 | if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER |
6638 | && reg_equiv_mem[REGNO (old)] != 0) | |
6639 | real_old = reg_equiv_mem[REGNO (old)]; | |
32131a9c | 6640 | |
367b1cf5 BS |
6641 | if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class, |
6642 | mode, real_old) | |
6643 | != NO_REGS)) | |
b60a8416 | 6644 | { |
367b1cf5 BS |
6645 | rtx second_reloadreg = reloadreg; |
6646 | reloadreg = rld[rl->secondary_out_reload].reg_rtx; | |
32131a9c | 6647 | |
367b1cf5 BS |
6648 | /* See if RELOADREG is to be used as a scratch register |
6649 | or as an intermediate register. */ | |
6650 | if (rl->secondary_out_icode != CODE_FOR_nothing) | |
6651 | { | |
6652 | emit_insn ((GEN_FCN (rl->secondary_out_icode) | |
6653 | (real_old, second_reloadreg, reloadreg))); | |
6654 | special = 1; | |
6655 | } | |
6656 | else | |
6657 | { | |
6658 | /* See if we need both a scratch and intermediate reload | |
6659 | register. */ | |
32131a9c | 6660 | |
367b1cf5 BS |
6661 | int secondary_reload = rl->secondary_out_reload; |
6662 | enum insn_code tertiary_icode | |
6663 | = rld[secondary_reload].secondary_out_icode; | |
32131a9c | 6664 | |
367b1cf5 BS |
6665 | if (GET_MODE (reloadreg) != mode) |
6666 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
cb2afeb3 | 6667 | |
367b1cf5 BS |
6668 | if (tertiary_icode != CODE_FOR_nothing) |
6669 | { | |
6670 | rtx third_reloadreg | |
6671 | = rld[rld[secondary_reload].secondary_out_reload].reg_rtx; | |
6672 | rtx tem; | |
6673 | ||
6674 | /* Copy primary reload reg to secondary reload reg. | |
6675 | (Note that these have been swapped above, then | |
78adc5a0 | 6676 | secondary reload reg to OLD using our insn.) */ |
367b1cf5 BS |
6677 | |
6678 | /* If REAL_OLD is a paradoxical SUBREG, remove it | |
6679 | and try to put the opposite SUBREG on | |
6680 | RELOADREG. */ | |
6681 | if (GET_CODE (real_old) == SUBREG | |
6682 | && (GET_MODE_SIZE (GET_MODE (real_old)) | |
6683 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old)))) | |
6684 | && 0 != (tem = gen_lowpart_common | |
6685 | (GET_MODE (SUBREG_REG (real_old)), | |
6686 | reloadreg))) | |
6687 | real_old = SUBREG_REG (real_old), reloadreg = tem; | |
6688 | ||
6689 | gen_reload (reloadreg, second_reloadreg, | |
6690 | rl->opnum, rl->when_needed); | |
6691 | emit_insn ((GEN_FCN (tertiary_icode) | |
6692 | (real_old, reloadreg, third_reloadreg))); | |
6693 | special = 1; | |
6694 | } | |
05d10675 | 6695 | |
367b1cf5 BS |
6696 | else |
6697 | /* Copy between the reload regs here and then to | |
6698 | OUT later. */ | |
cb2afeb3 | 6699 | |
367b1cf5 BS |
6700 | gen_reload (reloadreg, second_reloadreg, |
6701 | rl->opnum, rl->when_needed); | |
a7911cd2 | 6702 | } |
367b1cf5 BS |
6703 | } |
6704 | } | |
32131a9c RK |
6705 | #endif |
6706 | ||
367b1cf5 BS |
6707 | /* Output the last reload insn. */ |
6708 | if (! special) | |
6709 | { | |
6710 | rtx set; | |
6711 | ||
6712 | /* Don't output the last reload if OLD is not the dest of | |
1d7254c5 | 6713 | INSN and is in the src and is clobbered by INSN. */ |
367b1cf5 BS |
6714 | if (! flag_expensive_optimizations |
6715 | || GET_CODE (old) != REG | |
6716 | || !(set = single_set (insn)) | |
6717 | || rtx_equal_p (old, SET_DEST (set)) | |
6718 | || !reg_mentioned_p (old, SET_SRC (set)) | |
9532e31f | 6719 | || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0)) |
367b1cf5 BS |
6720 | gen_reload (old, reloadreg, rl->opnum, |
6721 | rl->when_needed); | |
6722 | } | |
32131a9c | 6723 | |
367b1cf5 BS |
6724 | /* Look at all insns we emitted, just to be safe. */ |
6725 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
2c3c49de | 6726 | if (INSN_P (p)) |
367b1cf5 BS |
6727 | { |
6728 | rtx pat = PATTERN (p); | |
546b63fb | 6729 | |
367b1cf5 BS |
6730 | /* If this output reload doesn't come from a spill reg, |
6731 | clear any memory of reloaded copies of the pseudo reg. | |
6732 | If this output reload comes from a spill reg, | |
6733 | reg_has_output_reload will make this do nothing. */ | |
6734 | note_stores (pat, forget_old_reloads_1, NULL); | |
cb2afeb3 | 6735 | |
367b1cf5 BS |
6736 | if (reg_mentioned_p (rl->reg_rtx, pat)) |
6737 | { | |
6738 | rtx set = single_set (insn); | |
6739 | if (reload_spill_index[j] < 0 | |
6740 | && set | |
6741 | && SET_SRC (set) == rl->reg_rtx) | |
6742 | { | |
6743 | int src = REGNO (SET_SRC (set)); | |
32131a9c | 6744 | |
367b1cf5 BS |
6745 | reload_spill_index[j] = src; |
6746 | SET_HARD_REG_BIT (reg_is_output_reload, src); | |
6747 | if (find_regno_note (insn, REG_DEAD, src)) | |
6748 | SET_HARD_REG_BIT (reg_reloaded_died, src); | |
6749 | } | |
6750 | if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER) | |
6751 | { | |
6752 | int s = rl->secondary_out_reload; | |
6753 | set = single_set (p); | |
6754 | /* If this reload copies only to the secondary reload | |
6755 | register, the secondary reload does the actual | |
6756 | store. */ | |
6757 | if (s >= 0 && set == NULL_RTX) | |
1d7254c5 KH |
6758 | /* We can't tell what function the secondary reload |
6759 | has and where the actual store to the pseudo is | |
6760 | made; leave new_spill_reg_store alone. */ | |
6761 | ; | |
367b1cf5 BS |
6762 | else if (s >= 0 |
6763 | && SET_SRC (set) == rl->reg_rtx | |
6764 | && SET_DEST (set) == rld[s].reg_rtx) | |
6765 | { | |
6766 | /* Usually the next instruction will be the | |
6767 | secondary reload insn; if we can confirm | |
6768 | that it is, setting new_spill_reg_store to | |
6769 | that insn will allow an extra optimization. */ | |
6770 | rtx s_reg = rld[s].reg_rtx; | |
6771 | rtx next = NEXT_INSN (p); | |
6772 | rld[s].out = rl->out; | |
6773 | rld[s].out_reg = rl->out_reg; | |
6774 | set = single_set (next); | |
6775 | if (set && SET_SRC (set) == s_reg | |
6776 | && ! new_spill_reg_store[REGNO (s_reg)]) | |
6777 | { | |
6778 | SET_HARD_REG_BIT (reg_is_output_reload, | |
6779 | REGNO (s_reg)); | |
6780 | new_spill_reg_store[REGNO (s_reg)] = next; | |
6781 | } | |
6782 | } | |
6783 | else | |
6784 | new_spill_reg_store[REGNO (rl->reg_rtx)] = p; | |
6785 | } | |
6786 | } | |
6787 | } | |
32131a9c | 6788 | |
367b1cf5 BS |
6789 | if (rl->when_needed == RELOAD_OTHER) |
6790 | { | |
6791 | emit_insns (other_output_reload_insns[rl->opnum]); | |
6792 | other_output_reload_insns[rl->opnum] = get_insns (); | |
6793 | } | |
6794 | else | |
6795 | output_reload_insns[rl->opnum] = get_insns (); | |
32131a9c | 6796 | |
94bd63e5 AH |
6797 | if (flag_non_call_exceptions) |
6798 | copy_eh_notes (insn, get_insns ()); | |
6799 | ||
1d7254c5 | 6800 | end_sequence (); |
367b1cf5 | 6801 | } |
32131a9c | 6802 | |
367b1cf5 BS |
6803 | /* Do input reloading for reload RL, which is for the insn described by CHAIN |
6804 | and has the number J. */ | |
6805 | static void | |
6806 | do_input_reload (chain, rl, j) | |
6807 | struct insn_chain *chain; | |
6808 | struct reload *rl; | |
6809 | int j; | |
6810 | { | |
6811 | int expect_occurrences = 1; | |
6812 | rtx insn = chain->insn; | |
6813 | rtx old = (rl->in && GET_CODE (rl->in) == MEM | |
6814 | ? rl->in_reg : rl->in); | |
6815 | ||
6816 | if (old != 0 | |
6817 | /* AUTO_INC reloads need to be handled even if inherited. We got an | |
6818 | AUTO_INC reload if reload_out is set but reload_out_reg isn't. */ | |
6819 | && (! reload_inherited[j] || (rl->out && ! rl->out_reg)) | |
6820 | && ! rtx_equal_p (rl->reg_rtx, old) | |
6821 | && rl->reg_rtx != 0) | |
1d813780 | 6822 | emit_input_reload_insns (chain, rld + j, old, j); |
32131a9c | 6823 | |
367b1cf5 BS |
6824 | /* When inheriting a wider reload, we have a MEM in rl->in, |
6825 | e.g. inheriting a SImode output reload for | |
6826 | (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */ | |
6827 | if (optimize && reload_inherited[j] && rl->in | |
6828 | && GET_CODE (rl->in) == MEM | |
6829 | && GET_CODE (rl->in_reg) == MEM | |
6830 | && reload_spill_index[j] >= 0 | |
6831 | && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j])) | |
6832 | { | |
6833 | expect_occurrences | |
4b983fdc | 6834 | = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1; |
1d7254c5 | 6835 | rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]]; |
367b1cf5 | 6836 | } |
32131a9c | 6837 | |
367b1cf5 BS |
6838 | /* If we are reloading a register that was recently stored in with an |
6839 | output-reload, see if we can prove there was | |
6840 | actually no need to store the old value in it. */ | |
32131a9c | 6841 | |
367b1cf5 BS |
6842 | if (optimize |
6843 | && (reload_inherited[j] || reload_override_in[j]) | |
6844 | && rl->reg_rtx | |
6845 | && GET_CODE (rl->reg_rtx) == REG | |
6846 | && spill_reg_store[REGNO (rl->reg_rtx)] != 0 | |
6847 | #if 0 | |
6848 | /* There doesn't seem to be any reason to restrict this to pseudos | |
6849 | and doing so loses in the case where we are copying from a | |
6850 | register of the wrong class. */ | |
6851 | && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
6852 | >= FIRST_PSEUDO_REGISTER) | |
6853 | #endif | |
6854 | /* The insn might have already some references to stackslots | |
6855 | replaced by MEMs, while reload_out_reg still names the | |
6856 | original pseudo. */ | |
6857 | && (dead_or_set_p (insn, | |
6858 | spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
6859 | || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)], | |
6860 | rl->out_reg))) | |
6861 | delete_output_reload (insn, j, REGNO (rl->reg_rtx)); | |
6862 | } | |
32131a9c | 6863 | |
367b1cf5 BS |
6864 | /* Do output reloading for reload RL, which is for the insn described by |
6865 | CHAIN and has the number J. | |
6866 | ??? At some point we need to support handling output reloads of | |
6867 | JUMP_INSNs or insns that set cc0. */ | |
6868 | static void | |
6869 | do_output_reload (chain, rl, j) | |
6870 | struct insn_chain *chain; | |
6871 | struct reload *rl; | |
6872 | int j; | |
6873 | { | |
6874 | rtx note, old; | |
6875 | rtx insn = chain->insn; | |
6876 | /* If this is an output reload that stores something that is | |
6877 | not loaded in this same reload, see if we can eliminate a previous | |
6878 | store. */ | |
6879 | rtx pseudo = rl->out_reg; | |
6880 | ||
6881 | if (pseudo | |
6882 | && GET_CODE (pseudo) == REG | |
6883 | && ! rtx_equal_p (rl->in_reg, pseudo) | |
6884 | && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER | |
6885 | && reg_last_reload_reg[REGNO (pseudo)]) | |
6886 | { | |
6887 | int pseudo_no = REGNO (pseudo); | |
6888 | int last_regno = REGNO (reg_last_reload_reg[pseudo_no]); | |
6889 | ||
6890 | /* We don't need to test full validity of last_regno for | |
6891 | inherit here; we only want to know if the store actually | |
6892 | matches the pseudo. */ | |
60ef417d GK |
6893 | if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno) |
6894 | && reg_reloaded_contents[last_regno] == pseudo_no | |
367b1cf5 BS |
6895 | && spill_reg_store[last_regno] |
6896 | && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) | |
6897 | delete_output_reload (insn, j, last_regno); | |
6898 | } | |
5e03c156 | 6899 | |
367b1cf5 BS |
6900 | old = rl->out_reg; |
6901 | if (old == 0 | |
6902 | || rl->reg_rtx == old | |
6903 | || rl->reg_rtx == 0) | |
6904 | return; | |
32131a9c | 6905 | |
367b1cf5 BS |
6906 | /* An output operand that dies right away does need a reload, |
6907 | but need not be copied from it. Show the new location in the | |
6908 | REG_UNUSED note. */ | |
6909 | if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH) | |
6910 | && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) | |
6911 | { | |
6912 | XEXP (note, 0) = rl->reg_rtx; | |
6913 | return; | |
6914 | } | |
6915 | /* Likewise for a SUBREG of an operand that dies. */ | |
6916 | else if (GET_CODE (old) == SUBREG | |
6917 | && GET_CODE (SUBREG_REG (old)) == REG | |
6918 | && 0 != (note = find_reg_note (insn, REG_UNUSED, | |
6919 | SUBREG_REG (old)))) | |
6920 | { | |
6921 | XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), | |
6922 | rl->reg_rtx); | |
6923 | return; | |
6924 | } | |
6925 | else if (GET_CODE (old) == SCRATCH) | |
6926 | /* If we aren't optimizing, there won't be a REG_UNUSED note, | |
6927 | but we don't want to make an output reload. */ | |
6928 | return; | |
1554c2c6 | 6929 | |
367b1cf5 BS |
6930 | /* If is a JUMP_INSN, we can't support output reloads yet. */ |
6931 | if (GET_CODE (insn) == JUMP_INSN) | |
6932 | abort (); | |
5e03c156 | 6933 | |
367b1cf5 BS |
6934 | emit_output_reload_insns (chain, rld + j, j); |
6935 | } | |
1554c2c6 | 6936 | |
367b1cf5 | 6937 | /* Output insns to reload values in and out of the chosen reload regs. */ |
32131a9c | 6938 | |
367b1cf5 | 6939 | static void |
e04ca094 | 6940 | emit_reload_insns (chain) |
367b1cf5 BS |
6941 | struct insn_chain *chain; |
6942 | { | |
6943 | rtx insn = chain->insn; | |
32131a9c | 6944 | |
b3694847 | 6945 | int j; |
e6e52be0 | 6946 | |
367b1cf5 | 6947 | CLEAR_HARD_REG_SET (reg_reloaded_died); |
e6e52be0 | 6948 | |
367b1cf5 BS |
6949 | for (j = 0; j < reload_n_operands; j++) |
6950 | input_reload_insns[j] = input_address_reload_insns[j] | |
6951 | = inpaddr_address_reload_insns[j] | |
6952 | = output_reload_insns[j] = output_address_reload_insns[j] | |
6953 | = outaddr_address_reload_insns[j] | |
6954 | = other_output_reload_insns[j] = 0; | |
6955 | other_input_address_reload_insns = 0; | |
6956 | other_input_reload_insns = 0; | |
6957 | operand_reload_insns = 0; | |
6958 | other_operand_reload_insns = 0; | |
32131a9c | 6959 | |
850aac53 | 6960 | /* Dump reloads into the dump file. */ |
e04ca094 | 6961 | if (rtl_dump_file) |
850aac53 | 6962 | { |
e04ca094 JL |
6963 | fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn)); |
6964 | debug_reload_to_stream (rtl_dump_file); | |
850aac53 JL |
6965 | } |
6966 | ||
367b1cf5 BS |
6967 | /* Now output the instructions to copy the data into and out of the |
6968 | reload registers. Do these in the order that the reloads were reported, | |
6969 | since reloads of base and index registers precede reloads of operands | |
6970 | and the operands may need the base and index registers reloaded. */ | |
32131a9c | 6971 | |
367b1cf5 BS |
6972 | for (j = 0; j < n_reloads; j++) |
6973 | { | |
6974 | if (rld[j].reg_rtx | |
6975 | && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER) | |
6976 | new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0; | |
d7e0324f | 6977 | |
367b1cf5 BS |
6978 | do_input_reload (chain, rld + j, j); |
6979 | do_output_reload (chain, rld + j, j); | |
32131a9c RK |
6980 | } |
6981 | ||
546b63fb RK |
6982 | /* Now write all the insns we made for reloads in the order expected by |
6983 | the allocation functions. Prior to the insn being reloaded, we write | |
6984 | the following reloads: | |
6985 | ||
6986 | RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. | |
6987 | ||
2edc8d65 | 6988 | RELOAD_OTHER reloads. |
546b63fb | 6989 | |
47c8cf91 ILT |
6990 | For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed |
6991 | by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the | |
6992 | RELOAD_FOR_INPUT reload for the operand. | |
546b63fb | 6993 | |
893bc853 RK |
6994 | RELOAD_FOR_OPADDR_ADDRS reloads. |
6995 | ||
546b63fb RK |
6996 | RELOAD_FOR_OPERAND_ADDRESS reloads. |
6997 | ||
6998 | After the insn being reloaded, we write the following: | |
6999 | ||
47c8cf91 ILT |
7000 | For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed |
7001 | by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the | |
7002 | RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output | |
7003 | reloads for the operand. The RELOAD_OTHER output reloads are | |
7004 | output in descending order by reload number. */ | |
546b63fb | 7005 | |
c93b03c2 RH |
7006 | emit_insns_before (other_input_address_reload_insns, insn); |
7007 | emit_insns_before (other_input_reload_insns, insn); | |
546b63fb RK |
7008 | |
7009 | for (j = 0; j < reload_n_operands; j++) | |
7010 | { | |
c93b03c2 RH |
7011 | emit_insns_before (inpaddr_address_reload_insns[j], insn); |
7012 | emit_insns_before (input_address_reload_insns[j], insn); | |
7013 | emit_insns_before (input_reload_insns[j], insn); | |
546b63fb RK |
7014 | } |
7015 | ||
c93b03c2 RH |
7016 | emit_insns_before (other_operand_reload_insns, insn); |
7017 | emit_insns_before (operand_reload_insns, insn); | |
546b63fb RK |
7018 | |
7019 | for (j = 0; j < reload_n_operands; j++) | |
7020 | { | |
ca6c03ca JH |
7021 | rtx x = emit_insns_after (outaddr_address_reload_insns[j], insn); |
7022 | x = emit_insns_after (output_address_reload_insns[j], x); | |
7023 | x = emit_insns_after (output_reload_insns[j], x); | |
7024 | emit_insns_after (other_output_reload_insns[j], x); | |
546b63fb RK |
7025 | } |
7026 | ||
32131a9c RK |
7027 | /* For all the spill regs newly reloaded in this instruction, |
7028 | record what they were reloaded from, so subsequent instructions | |
d445b551 RK |
7029 | can inherit the reloads. |
7030 | ||
7031 | Update spill_reg_store for the reloads of this insn. | |
e9e79d69 | 7032 | Copy the elements that were updated in the loop above. */ |
32131a9c RK |
7033 | |
7034 | for (j = 0; j < n_reloads; j++) | |
7035 | { | |
b3694847 SS |
7036 | int r = reload_order[j]; |
7037 | int i = reload_spill_index[r]; | |
32131a9c | 7038 | |
78a2bc08 | 7039 | /* If this is a non-inherited input reload from a pseudo, we must |
05d10675 BS |
7040 | clear any memory of a previous store to the same pseudo. Only do |
7041 | something if there will not be an output reload for the pseudo | |
7042 | being reloaded. */ | |
eceef4c9 | 7043 | if (rld[r].in_reg != 0 |
05d10675 BS |
7044 | && ! (reload_inherited[r] || reload_override_in[r])) |
7045 | { | |
eceef4c9 | 7046 | rtx reg = rld[r].in_reg; |
78a2bc08 | 7047 | |
05d10675 | 7048 | if (GET_CODE (reg) == SUBREG) |
78a2bc08 | 7049 | reg = SUBREG_REG (reg); |
05d10675 BS |
7050 | |
7051 | if (GET_CODE (reg) == REG | |
78a2bc08 R |
7052 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER |
7053 | && ! reg_has_output_reload[REGNO (reg)]) | |
7054 | { | |
7055 | int nregno = REGNO (reg); | |
7056 | ||
7057 | if (reg_last_reload_reg[nregno]) | |
05d10675 BS |
7058 | { |
7059 | int last_regno = REGNO (reg_last_reload_reg[nregno]); | |
78a2bc08 | 7060 | |
05d10675 | 7061 | if (reg_reloaded_contents[last_regno] == nregno) |
78a2bc08 | 7062 | spill_reg_store[last_regno] = 0; |
05d10675 | 7063 | } |
78a2bc08 R |
7064 | } |
7065 | } | |
05d10675 | 7066 | |
e6e52be0 | 7067 | /* I is nonneg if this reload used a register. |
eceef4c9 | 7068 | If rld[r].reg_rtx is 0, this is an optional reload |
51f0c3b7 | 7069 | that we opted to ignore. */ |
d445b551 | 7070 | |
eceef4c9 | 7071 | if (i >= 0 && rld[r].reg_rtx != 0) |
32131a9c | 7072 | { |
1d7254c5 | 7073 | int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx)); |
32131a9c | 7074 | int k; |
51f0c3b7 JW |
7075 | int part_reaches_end = 0; |
7076 | int all_reaches_end = 1; | |
32131a9c | 7077 | |
51f0c3b7 JW |
7078 | /* For a multi register reload, we need to check if all or part |
7079 | of the value lives to the end. */ | |
32131a9c RK |
7080 | for (k = 0; k < nr; k++) |
7081 | { | |
eceef4c9 BS |
7082 | if (reload_reg_reaches_end_p (i + k, rld[r].opnum, |
7083 | rld[r].when_needed)) | |
51f0c3b7 JW |
7084 | part_reaches_end = 1; |
7085 | else | |
7086 | all_reaches_end = 0; | |
32131a9c RK |
7087 | } |
7088 | ||
51f0c3b7 JW |
7089 | /* Ignore reloads that don't reach the end of the insn in |
7090 | entirety. */ | |
7091 | if (all_reaches_end) | |
32131a9c | 7092 | { |
51f0c3b7 JW |
7093 | /* First, clear out memory of what used to be in this spill reg. |
7094 | If consecutive registers are used, clear them all. */ | |
d08ea79f | 7095 | |
32131a9c | 7096 | for (k = 0; k < nr; k++) |
e6e52be0 | 7097 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
d08ea79f | 7098 | |
51f0c3b7 | 7099 | /* Maybe the spill reg contains a copy of reload_out. */ |
eceef4c9 BS |
7100 | if (rld[r].out != 0 |
7101 | && (GET_CODE (rld[r].out) == REG | |
cb2afeb3 | 7102 | #ifdef AUTO_INC_DEC |
eceef4c9 | 7103 | || ! rld[r].out_reg |
cb2afeb3 | 7104 | #endif |
eceef4c9 | 7105 | || GET_CODE (rld[r].out_reg) == REG)) |
51f0c3b7 | 7106 | { |
eceef4c9 BS |
7107 | rtx out = (GET_CODE (rld[r].out) == REG |
7108 | ? rld[r].out | |
7109 | : rld[r].out_reg | |
7110 | ? rld[r].out_reg | |
7111 | /* AUTO_INC */ : XEXP (rld[r].in_reg, 0)); | |
b3694847 | 7112 | int nregno = REGNO (out); |
51f0c3b7 JW |
7113 | int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
7114 | : HARD_REGNO_NREGS (nregno, | |
eceef4c9 | 7115 | GET_MODE (rld[r].reg_rtx))); |
51f0c3b7 JW |
7116 | |
7117 | spill_reg_store[i] = new_spill_reg_store[i]; | |
cb2afeb3 | 7118 | spill_reg_stored_to[i] = out; |
eceef4c9 | 7119 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
51f0c3b7 JW |
7120 | |
7121 | /* If NREGNO is a hard register, it may occupy more than | |
05d10675 | 7122 | one register. If it does, say what is in the |
51f0c3b7 JW |
7123 | rest of the registers assuming that both registers |
7124 | agree on how many words the object takes. If not, | |
7125 | invalidate the subsequent registers. */ | |
7126 | ||
7127 | if (nregno < FIRST_PSEUDO_REGISTER) | |
7128 | for (k = 1; k < nnr; k++) | |
7129 | reg_last_reload_reg[nregno + k] | |
7130 | = (nr == nnr | |
eceef4c9 BS |
7131 | ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k], |
7132 | REGNO (rld[r].reg_rtx) + k) | |
51f0c3b7 JW |
7133 | : 0); |
7134 | ||
7135 | /* Now do the inverse operation. */ | |
7136 | for (k = 0; k < nr; k++) | |
7137 | { | |
e6e52be0 R |
7138 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
7139 | reg_reloaded_contents[i + k] | |
51f0c3b7 JW |
7140 | = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr |
7141 | ? nregno | |
7142 | : nregno + k); | |
e6e52be0 R |
7143 | reg_reloaded_insn[i + k] = insn; |
7144 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
51f0c3b7 JW |
7145 | } |
7146 | } | |
d08ea79f | 7147 | |
51f0c3b7 JW |
7148 | /* Maybe the spill reg contains a copy of reload_in. Only do |
7149 | something if there will not be an output reload for | |
7150 | the register being reloaded. */ | |
eceef4c9 BS |
7151 | else if (rld[r].out_reg == 0 |
7152 | && rld[r].in != 0 | |
7153 | && ((GET_CODE (rld[r].in) == REG | |
7154 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER | |
7155 | && ! reg_has_output_reload[REGNO (rld[r].in)]) | |
7156 | || (GET_CODE (rld[r].in_reg) == REG | |
7157 | && ! reg_has_output_reload[REGNO (rld[r].in_reg)])) | |
7158 | && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn))) | |
51f0c3b7 | 7159 | { |
b3694847 | 7160 | int nregno; |
51f0c3b7 | 7161 | int nnr; |
d445b551 | 7162 | |
eceef4c9 BS |
7163 | if (GET_CODE (rld[r].in) == REG |
7164 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER) | |
7165 | nregno = REGNO (rld[r].in); | |
7166 | else if (GET_CODE (rld[r].in_reg) == REG) | |
7167 | nregno = REGNO (rld[r].in_reg); | |
cb2afeb3 | 7168 | else |
eceef4c9 | 7169 | nregno = REGNO (XEXP (rld[r].in_reg, 0)); |
d08ea79f | 7170 | |
51f0c3b7 JW |
7171 | nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
7172 | : HARD_REGNO_NREGS (nregno, | |
eceef4c9 | 7173 | GET_MODE (rld[r].reg_rtx))); |
05d10675 | 7174 | |
eceef4c9 | 7175 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
51f0c3b7 JW |
7176 | |
7177 | if (nregno < FIRST_PSEUDO_REGISTER) | |
7178 | for (k = 1; k < nnr; k++) | |
7179 | reg_last_reload_reg[nregno + k] | |
7180 | = (nr == nnr | |
eceef4c9 BS |
7181 | ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k], |
7182 | REGNO (rld[r].reg_rtx) + k) | |
51f0c3b7 JW |
7183 | : 0); |
7184 | ||
7185 | /* Unless we inherited this reload, show we haven't | |
cb2afeb3 R |
7186 | recently done a store. |
7187 | Previous stores of inherited auto_inc expressions | |
7188 | also have to be discarded. */ | |
7189 | if (! reload_inherited[r] | |
eceef4c9 | 7190 | || (rld[r].out && ! rld[r].out_reg)) |
51f0c3b7 JW |
7191 | spill_reg_store[i] = 0; |
7192 | ||
7193 | for (k = 0; k < nr; k++) | |
7194 | { | |
e6e52be0 R |
7195 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
7196 | reg_reloaded_contents[i + k] | |
51f0c3b7 JW |
7197 | = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr |
7198 | ? nregno | |
7199 | : nregno + k); | |
e6e52be0 R |
7200 | reg_reloaded_insn[i + k] = insn; |
7201 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
51f0c3b7 JW |
7202 | } |
7203 | } | |
7204 | } | |
d445b551 | 7205 | |
51f0c3b7 JW |
7206 | /* However, if part of the reload reaches the end, then we must |
7207 | invalidate the old info for the part that survives to the end. */ | |
7208 | else if (part_reaches_end) | |
7209 | { | |
546b63fb | 7210 | for (k = 0; k < nr; k++) |
e6e52be0 | 7211 | if (reload_reg_reaches_end_p (i + k, |
eceef4c9 BS |
7212 | rld[r].opnum, |
7213 | rld[r].when_needed)) | |
e6e52be0 | 7214 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
32131a9c RK |
7215 | } |
7216 | } | |
7217 | ||
7218 | /* The following if-statement was #if 0'd in 1.34 (or before...). | |
7219 | It's reenabled in 1.35 because supposedly nothing else | |
7220 | deals with this problem. */ | |
7221 | ||
7222 | /* If a register gets output-reloaded from a non-spill register, | |
7223 | that invalidates any previous reloaded copy of it. | |
7224 | But forget_old_reloads_1 won't get to see it, because | |
7225 | it thinks only about the original insn. So invalidate it here. */ | |
eceef4c9 BS |
7226 | if (i < 0 && rld[r].out != 0 |
7227 | && (GET_CODE (rld[r].out) == REG | |
7228 | || (GET_CODE (rld[r].out) == MEM | |
7229 | && GET_CODE (rld[r].out_reg) == REG))) | |
32131a9c | 7230 | { |
eceef4c9 BS |
7231 | rtx out = (GET_CODE (rld[r].out) == REG |
7232 | ? rld[r].out : rld[r].out_reg); | |
b3694847 | 7233 | int nregno = REGNO (out); |
c7093272 | 7234 | if (nregno >= FIRST_PSEUDO_REGISTER) |
cb2afeb3 | 7235 | { |
6a651371 | 7236 | rtx src_reg, store_insn = NULL_RTX; |
cb2afeb3 R |
7237 | |
7238 | reg_last_reload_reg[nregno] = 0; | |
7239 | ||
7240 | /* If we can find a hard register that is stored, record | |
7241 | the storing insn so that we may delete this insn with | |
7242 | delete_output_reload. */ | |
eceef4c9 | 7243 | src_reg = rld[r].reg_rtx; |
cb2afeb3 R |
7244 | |
7245 | /* If this is an optional reload, try to find the source reg | |
7246 | from an input reload. */ | |
7247 | if (! src_reg) | |
7248 | { | |
7249 | rtx set = single_set (insn); | |
eceef4c9 | 7250 | if (set && SET_DEST (set) == rld[r].out) |
cb2afeb3 R |
7251 | { |
7252 | int k; | |
7253 | ||
7254 | src_reg = SET_SRC (set); | |
7255 | store_insn = insn; | |
7256 | for (k = 0; k < n_reloads; k++) | |
7257 | { | |
eceef4c9 | 7258 | if (rld[k].in == src_reg) |
cb2afeb3 | 7259 | { |
eceef4c9 | 7260 | src_reg = rld[k].reg_rtx; |
cb2afeb3 R |
7261 | break; |
7262 | } | |
7263 | } | |
7264 | } | |
7265 | } | |
7266 | else | |
7267 | store_insn = new_spill_reg_store[REGNO (src_reg)]; | |
7268 | if (src_reg && GET_CODE (src_reg) == REG | |
7269 | && REGNO (src_reg) < FIRST_PSEUDO_REGISTER) | |
7270 | { | |
7271 | int src_regno = REGNO (src_reg); | |
8ec450a4 | 7272 | int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode); |
cb2afeb3 R |
7273 | /* The place where to find a death note varies with |
7274 | PRESERVE_DEATH_INFO_REGNO_P . The condition is not | |
7275 | necessarily checked exactly in the code that moves | |
7276 | notes, so just check both locations. */ | |
7277 | rtx note = find_regno_note (insn, REG_DEAD, src_regno); | |
1558b970 | 7278 | if (! note && store_insn) |
cb2afeb3 R |
7279 | note = find_regno_note (store_insn, REG_DEAD, src_regno); |
7280 | while (nr-- > 0) | |
7281 | { | |
7282 | spill_reg_store[src_regno + nr] = store_insn; | |
7283 | spill_reg_stored_to[src_regno + nr] = out; | |
7284 | reg_reloaded_contents[src_regno + nr] = nregno; | |
7285 | reg_reloaded_insn[src_regno + nr] = store_insn; | |
00f9f1bc | 7286 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr); |
cb2afeb3 R |
7287 | SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr); |
7288 | SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr); | |
7289 | if (note) | |
7290 | SET_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7291 | else | |
7292 | CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7293 | } | |
7294 | reg_last_reload_reg[nregno] = src_reg; | |
7295 | } | |
7296 | } | |
c7093272 RK |
7297 | else |
7298 | { | |
1d7254c5 | 7299 | int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out)); |
36281332 | 7300 | |
c7093272 RK |
7301 | while (num_regs-- > 0) |
7302 | reg_last_reload_reg[nregno + num_regs] = 0; | |
7303 | } | |
32131a9c RK |
7304 | } |
7305 | } | |
e6e52be0 | 7306 | IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died); |
32131a9c RK |
7307 | } |
7308 | \f | |
5e03c156 RK |
7309 | /* Emit code to perform a reload from IN (which may be a reload register) to |
7310 | OUT (which may also be a reload register). IN or OUT is from operand | |
05d10675 | 7311 | OPNUM with reload type TYPE. |
546b63fb | 7312 | |
3c3eeea6 | 7313 | Returns first insn emitted. */ |
32131a9c RK |
7314 | |
7315 | rtx | |
5e03c156 RK |
7316 | gen_reload (out, in, opnum, type) |
7317 | rtx out; | |
32131a9c | 7318 | rtx in; |
546b63fb RK |
7319 | int opnum; |
7320 | enum reload_type type; | |
32131a9c | 7321 | { |
546b63fb | 7322 | rtx last = get_last_insn (); |
7a5b18b0 RK |
7323 | rtx tem; |
7324 | ||
7325 | /* If IN is a paradoxical SUBREG, remove it and try to put the | |
7326 | opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ | |
7327 | if (GET_CODE (in) == SUBREG | |
7328 | && (GET_MODE_SIZE (GET_MODE (in)) | |
7329 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
7330 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0) | |
7331 | in = SUBREG_REG (in), out = tem; | |
7332 | else if (GET_CODE (out) == SUBREG | |
eceef4c9 BS |
7333 | && (GET_MODE_SIZE (GET_MODE (out)) |
7334 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) | |
7335 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0) | |
7a5b18b0 | 7336 | out = SUBREG_REG (out), in = tem; |
32131a9c | 7337 | |
a8fdc208 | 7338 | /* How to do this reload can get quite tricky. Normally, we are being |
32131a9c RK |
7339 | asked to reload a simple operand, such as a MEM, a constant, or a pseudo |
7340 | register that didn't get a hard register. In that case we can just | |
7341 | call emit_move_insn. | |
7342 | ||
a7fd196c JW |
7343 | We can also be asked to reload a PLUS that adds a register or a MEM to |
7344 | another register, constant or MEM. This can occur during frame pointer | |
7345 | elimination and while reloading addresses. This case is handled by | |
7346 | trying to emit a single insn to perform the add. If it is not valid, | |
7347 | we use a two insn sequence. | |
32131a9c RK |
7348 | |
7349 | Finally, we could be called to handle an 'o' constraint by putting | |
7350 | an address into a register. In that case, we first try to do this | |
7351 | with a named pattern of "reload_load_address". If no such pattern | |
7352 | exists, we just emit a SET insn and hope for the best (it will normally | |
7353 | be valid on machines that use 'o'). | |
7354 | ||
7355 | This entire process is made complex because reload will never | |
7356 | process the insns we generate here and so we must ensure that | |
7357 | they will fit their constraints and also by the fact that parts of | |
7358 | IN might be being reloaded separately and replaced with spill registers. | |
7359 | Because of this, we are, in some sense, just guessing the right approach | |
7360 | here. The one listed above seems to work. | |
7361 | ||
7362 | ??? At some point, this whole thing needs to be rethought. */ | |
7363 | ||
7364 | if (GET_CODE (in) == PLUS | |
a7fd196c | 7365 | && (GET_CODE (XEXP (in, 0)) == REG |
5c6b1bd2 | 7366 | || GET_CODE (XEXP (in, 0)) == SUBREG |
a7fd196c JW |
7367 | || GET_CODE (XEXP (in, 0)) == MEM) |
7368 | && (GET_CODE (XEXP (in, 1)) == REG | |
5c6b1bd2 | 7369 | || GET_CODE (XEXP (in, 1)) == SUBREG |
a7fd196c JW |
7370 | || CONSTANT_P (XEXP (in, 1)) |
7371 | || GET_CODE (XEXP (in, 1)) == MEM)) | |
32131a9c | 7372 | { |
a7fd196c JW |
7373 | /* We need to compute the sum of a register or a MEM and another |
7374 | register, constant, or MEM, and put it into the reload | |
3002e160 JW |
7375 | register. The best possible way of doing this is if the machine |
7376 | has a three-operand ADD insn that accepts the required operands. | |
32131a9c RK |
7377 | |
7378 | The simplest approach is to try to generate such an insn and see if it | |
7379 | is recognized and matches its constraints. If so, it can be used. | |
7380 | ||
7381 | It might be better not to actually emit the insn unless it is valid, | |
0009eff2 | 7382 | but we need to pass the insn as an operand to `recog' and |
0eadeb15 | 7383 | `extract_insn' and it is simpler to emit and then delete the insn if |
0009eff2 | 7384 | not valid than to dummy things up. */ |
a8fdc208 | 7385 | |
af929c62 | 7386 | rtx op0, op1, tem, insn; |
32131a9c | 7387 | int code; |
a8fdc208 | 7388 | |
af929c62 RK |
7389 | op0 = find_replacement (&XEXP (in, 0)); |
7390 | op1 = find_replacement (&XEXP (in, 1)); | |
7391 | ||
32131a9c RK |
7392 | /* Since constraint checking is strict, commutativity won't be |
7393 | checked, so we need to do that here to avoid spurious failure | |
7394 | if the add instruction is two-address and the second operand | |
7395 | of the add is the same as the reload reg, which is frequently | |
7396 | the case. If the insn would be A = B + A, rearrange it so | |
0f41302f | 7397 | it will be A = A + B as constrain_operands expects. */ |
a8fdc208 | 7398 | |
32131a9c | 7399 | if (GET_CODE (XEXP (in, 1)) == REG |
5e03c156 | 7400 | && REGNO (out) == REGNO (XEXP (in, 1))) |
af929c62 RK |
7401 | tem = op0, op0 = op1, op1 = tem; |
7402 | ||
7403 | if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) | |
38a448ca | 7404 | in = gen_rtx_PLUS (GET_MODE (in), op0, op1); |
32131a9c | 7405 | |
38a448ca | 7406 | insn = emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
32131a9c RK |
7407 | code = recog_memoized (insn); |
7408 | ||
7409 | if (code >= 0) | |
7410 | { | |
0eadeb15 | 7411 | extract_insn (insn); |
32131a9c RK |
7412 | /* We want constrain operands to treat this insn strictly in |
7413 | its validity determination, i.e., the way it would after reload | |
7414 | has completed. */ | |
0eadeb15 | 7415 | if (constrain_operands (1)) |
32131a9c RK |
7416 | return insn; |
7417 | } | |
7418 | ||
546b63fb | 7419 | delete_insns_since (last); |
32131a9c RK |
7420 | |
7421 | /* If that failed, we must use a conservative two-insn sequence. | |
09522f21 FS |
7422 | |
7423 | Use a move to copy one operand into the reload register. Prefer | |
7424 | to reload a constant, MEM or pseudo since the move patterns can | |
7425 | handle an arbitrary operand. If OP1 is not a constant, MEM or | |
7426 | pseudo and OP1 is not a valid operand for an add instruction, then | |
7427 | reload OP1. | |
7428 | ||
7429 | After reloading one of the operands into the reload register, add | |
7430 | the reload register to the output register. | |
32131a9c RK |
7431 | |
7432 | If there is another way to do this for a specific machine, a | |
7433 | DEFINE_PEEPHOLE should be specified that recognizes the sequence | |
7434 | we emit below. */ | |
7435 | ||
09522f21 FS |
7436 | code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code; |
7437 | ||
5c6b1bd2 | 7438 | if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG |
af929c62 | 7439 | || (GET_CODE (op1) == REG |
09522f21 FS |
7440 | && REGNO (op1) >= FIRST_PSEUDO_REGISTER) |
7441 | || (code != CODE_FOR_nothing | |
a995e389 RH |
7442 | && ! ((*insn_data[code].operand[2].predicate) |
7443 | (op1, insn_data[code].operand[2].mode)))) | |
af929c62 | 7444 | tem = op0, op0 = op1, op1 = tem; |
32131a9c | 7445 | |
5c6b1bd2 | 7446 | gen_reload (out, op0, opnum, type); |
39b56c2a | 7447 | |
5e03c156 | 7448 | /* If OP0 and OP1 are the same, we can use OUT for OP1. |
39b56c2a RK |
7449 | This fixes a problem on the 32K where the stack pointer cannot |
7450 | be used as an operand of an add insn. */ | |
7451 | ||
7452 | if (rtx_equal_p (op0, op1)) | |
5e03c156 | 7453 | op1 = out; |
39b56c2a | 7454 | |
5e03c156 | 7455 | insn = emit_insn (gen_add2_insn (out, op1)); |
c77c9766 RK |
7456 | |
7457 | /* If that failed, copy the address register to the reload register. | |
0f41302f | 7458 | Then add the constant to the reload register. */ |
c77c9766 RK |
7459 | |
7460 | code = recog_memoized (insn); | |
7461 | ||
7462 | if (code >= 0) | |
7463 | { | |
0eadeb15 | 7464 | extract_insn (insn); |
c77c9766 RK |
7465 | /* We want constrain operands to treat this insn strictly in |
7466 | its validity determination, i.e., the way it would after reload | |
7467 | has completed. */ | |
0eadeb15 | 7468 | if (constrain_operands (1)) |
4117a96b R |
7469 | { |
7470 | /* Add a REG_EQUIV note so that find_equiv_reg can find it. */ | |
7471 | REG_NOTES (insn) | |
9e6a5703 | 7472 | = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); |
4117a96b R |
7473 | return insn; |
7474 | } | |
c77c9766 RK |
7475 | } |
7476 | ||
7477 | delete_insns_since (last); | |
7478 | ||
5c6b1bd2 | 7479 | gen_reload (out, op1, opnum, type); |
4117a96b | 7480 | insn = emit_insn (gen_add2_insn (out, op0)); |
9e6a5703 | 7481 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); |
32131a9c RK |
7482 | } |
7483 | ||
0dadecf6 RK |
7484 | #ifdef SECONDARY_MEMORY_NEEDED |
7485 | /* If we need a memory location to do the move, do it that way. */ | |
7486 | else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER | |
5e03c156 | 7487 | && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER |
0dadecf6 | 7488 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), |
5e03c156 RK |
7489 | REGNO_REG_CLASS (REGNO (out)), |
7490 | GET_MODE (out))) | |
0dadecf6 RK |
7491 | { |
7492 | /* Get the memory to use and rewrite both registers to its mode. */ | |
5e03c156 | 7493 | rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type); |
0dadecf6 | 7494 | |
5e03c156 | 7495 | if (GET_MODE (loc) != GET_MODE (out)) |
38a448ca | 7496 | out = gen_rtx_REG (GET_MODE (loc), REGNO (out)); |
0dadecf6 RK |
7497 | |
7498 | if (GET_MODE (loc) != GET_MODE (in)) | |
38a448ca | 7499 | in = gen_rtx_REG (GET_MODE (loc), REGNO (in)); |
0dadecf6 | 7500 | |
5c6b1bd2 RK |
7501 | gen_reload (loc, in, opnum, type); |
7502 | gen_reload (out, loc, opnum, type); | |
0dadecf6 RK |
7503 | } |
7504 | #endif | |
7505 | ||
32131a9c RK |
7506 | /* If IN is a simple operand, use gen_move_insn. */ |
7507 | else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG) | |
5e03c156 | 7508 | emit_insn (gen_move_insn (out, in)); |
32131a9c RK |
7509 | |
7510 | #ifdef HAVE_reload_load_address | |
7511 | else if (HAVE_reload_load_address) | |
5e03c156 | 7512 | emit_insn (gen_reload_load_address (out, in)); |
32131a9c RK |
7513 | #endif |
7514 | ||
5e03c156 | 7515 | /* Otherwise, just write (set OUT IN) and hope for the best. */ |
32131a9c | 7516 | else |
38a448ca | 7517 | emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
32131a9c RK |
7518 | |
7519 | /* Return the first insn emitted. | |
546b63fb | 7520 | We can not just return get_last_insn, because there may have |
32131a9c RK |
7521 | been multiple instructions emitted. Also note that gen_move_insn may |
7522 | emit more than one insn itself, so we can not assume that there is one | |
7523 | insn emitted per emit_insn_before call. */ | |
7524 | ||
546b63fb | 7525 | return last ? NEXT_INSN (last) : get_insns (); |
32131a9c RK |
7526 | } |
7527 | \f | |
7528 | /* Delete a previously made output-reload | |
7529 | whose result we now believe is not needed. | |
7530 | First we double-check. | |
7531 | ||
7532 | INSN is the insn now being processed. | |
cb2afeb3 R |
7533 | LAST_RELOAD_REG is the hard register number for which we want to delete |
7534 | the last output reload. | |
7535 | J is the reload-number that originally used REG. The caller has made | |
7536 | certain that reload J doesn't use REG any longer for input. */ | |
32131a9c RK |
7537 | |
7538 | static void | |
cb2afeb3 | 7539 | delete_output_reload (insn, j, last_reload_reg) |
32131a9c RK |
7540 | rtx insn; |
7541 | int j; | |
cb2afeb3 | 7542 | int last_reload_reg; |
32131a9c | 7543 | { |
cb2afeb3 R |
7544 | rtx output_reload_insn = spill_reg_store[last_reload_reg]; |
7545 | rtx reg = spill_reg_stored_to[last_reload_reg]; | |
7546 | int k; | |
7547 | int n_occurrences; | |
7548 | int n_inherited = 0; | |
b3694847 | 7549 | rtx i1; |
cb2afeb3 | 7550 | rtx substed; |
05d10675 | 7551 | |
32131a9c RK |
7552 | /* Get the raw pseudo-register referred to. */ |
7553 | ||
32131a9c RK |
7554 | while (GET_CODE (reg) == SUBREG) |
7555 | reg = SUBREG_REG (reg); | |
cb2afeb3 R |
7556 | substed = reg_equiv_memory_loc[REGNO (reg)]; |
7557 | ||
7558 | /* This is unsafe if the operand occurs more often in the current | |
7559 | insn than it is inherited. */ | |
7560 | for (k = n_reloads - 1; k >= 0; k--) | |
7561 | { | |
eceef4c9 | 7562 | rtx reg2 = rld[k].in; |
cb2afeb3 R |
7563 | if (! reg2) |
7564 | continue; | |
7565 | if (GET_CODE (reg2) == MEM || reload_override_in[k]) | |
eceef4c9 | 7566 | reg2 = rld[k].in_reg; |
cb2afeb3 | 7567 | #ifdef AUTO_INC_DEC |
eceef4c9 BS |
7568 | if (rld[k].out && ! rld[k].out_reg) |
7569 | reg2 = XEXP (rld[k].in_reg, 0); | |
cb2afeb3 R |
7570 | #endif |
7571 | while (GET_CODE (reg2) == SUBREG) | |
7572 | reg2 = SUBREG_REG (reg2); | |
7573 | if (rtx_equal_p (reg2, reg)) | |
2eb6dac7 AS |
7574 | { |
7575 | if (reload_inherited[k] || reload_override_in[k] || k == j) | |
7576 | { | |
cb2afeb3 | 7577 | n_inherited++; |
eceef4c9 | 7578 | reg2 = rld[k].out_reg; |
2eb6dac7 AS |
7579 | if (! reg2) |
7580 | continue; | |
7581 | while (GET_CODE (reg2) == SUBREG) | |
7582 | reg2 = XEXP (reg2, 0); | |
7583 | if (rtx_equal_p (reg2, reg)) | |
7584 | n_inherited++; | |
7585 | } | |
7586 | else | |
7587 | return; | |
7588 | } | |
cb2afeb3 | 7589 | } |
4b983fdc | 7590 | n_occurrences = count_occurrences (PATTERN (insn), reg, 0); |
cb2afeb3 | 7591 | if (substed) |
5d7ef82a BS |
7592 | n_occurrences += count_occurrences (PATTERN (insn), |
7593 | eliminate_regs (substed, 0, | |
7594 | NULL_RTX), 0); | |
cb2afeb3 R |
7595 | if (n_occurrences > n_inherited) |
7596 | return; | |
32131a9c RK |
7597 | |
7598 | /* If the pseudo-reg we are reloading is no longer referenced | |
7599 | anywhere between the store into it and here, | |
7600 | and no jumps or labels intervene, then the value can get | |
7601 | here through the reload reg alone. | |
7602 | Otherwise, give up--return. */ | |
7603 | for (i1 = NEXT_INSN (output_reload_insn); | |
7604 | i1 != insn; i1 = NEXT_INSN (i1)) | |
7605 | { | |
7606 | if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN) | |
7607 | return; | |
7608 | if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN) | |
7609 | && reg_mentioned_p (reg, PATTERN (i1))) | |
aa6498c2 | 7610 | { |
cb2afeb3 R |
7611 | /* If this is USE in front of INSN, we only have to check that |
7612 | there are no more references than accounted for by inheritance. */ | |
7613 | while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE) | |
aa6498c2 | 7614 | { |
cb2afeb3 | 7615 | n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0; |
aa6498c2 R |
7616 | i1 = NEXT_INSN (i1); |
7617 | } | |
cb2afeb3 | 7618 | if (n_occurrences <= n_inherited && i1 == insn) |
aa6498c2 R |
7619 | break; |
7620 | return; | |
7621 | } | |
32131a9c RK |
7622 | } |
7623 | ||
aa6498c2 R |
7624 | /* The caller has already checked that REG dies or is set in INSN. |
7625 | It has also checked that we are optimizing, and thus some inaccurancies | |
7626 | in the debugging information are acceptable. | |
7627 | So we could just delete output_reload_insn. | |
7628 | But in some cases we can improve the debugging information without | |
7629 | sacrificing optimization - maybe even improving the code: | |
7630 | See if the pseudo reg has been completely replaced | |
32131a9c RK |
7631 | with reload regs. If so, delete the store insn |
7632 | and forget we had a stack slot for the pseudo. */ | |
eceef4c9 | 7633 | if (rld[j].out != rld[j].in |
aa6498c2 | 7634 | && REG_N_DEATHS (REGNO (reg)) == 1 |
a3a24aa6 | 7635 | && REG_N_SETS (REGNO (reg)) == 1 |
aa6498c2 R |
7636 | && REG_BASIC_BLOCK (REGNO (reg)) >= 0 |
7637 | && find_regno_note (insn, REG_DEAD, REGNO (reg))) | |
32131a9c RK |
7638 | { |
7639 | rtx i2; | |
7640 | ||
7641 | /* We know that it was used only between here | |
7642 | and the beginning of the current basic block. | |
7643 | (We also know that the last use before INSN was | |
7644 | the output reload we are thinking of deleting, but never mind that.) | |
7645 | Search that range; see if any ref remains. */ | |
7646 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) | |
7647 | { | |
d445b551 RK |
7648 | rtx set = single_set (i2); |
7649 | ||
32131a9c RK |
7650 | /* Uses which just store in the pseudo don't count, |
7651 | since if they are the only uses, they are dead. */ | |
d445b551 | 7652 | if (set != 0 && SET_DEST (set) == reg) |
32131a9c RK |
7653 | continue; |
7654 | if (GET_CODE (i2) == CODE_LABEL | |
7655 | || GET_CODE (i2) == JUMP_INSN) | |
7656 | break; | |
7657 | if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN) | |
7658 | && reg_mentioned_p (reg, PATTERN (i2))) | |
aa6498c2 R |
7659 | { |
7660 | /* Some other ref remains; just delete the output reload we | |
7661 | know to be dead. */ | |
cb2afeb3 | 7662 | delete_address_reloads (output_reload_insn, insn); |
ca6c03ca | 7663 | delete_insn (output_reload_insn); |
aa6498c2 R |
7664 | return; |
7665 | } | |
32131a9c RK |
7666 | } |
7667 | ||
7668 | /* Delete the now-dead stores into this pseudo. */ | |
7669 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) | |
7670 | { | |
d445b551 RK |
7671 | rtx set = single_set (i2); |
7672 | ||
7673 | if (set != 0 && SET_DEST (set) == reg) | |
5507b94b | 7674 | { |
cb2afeb3 | 7675 | delete_address_reloads (i2, insn); |
5507b94b RK |
7676 | /* This might be a basic block head, |
7677 | thus don't use delete_insn. */ | |
ca6c03ca | 7678 | delete_insn (i2); |
5507b94b | 7679 | } |
32131a9c RK |
7680 | if (GET_CODE (i2) == CODE_LABEL |
7681 | || GET_CODE (i2) == JUMP_INSN) | |
7682 | break; | |
7683 | } | |
7684 | ||
7685 | /* For the debugging info, | |
7686 | say the pseudo lives in this reload reg. */ | |
eceef4c9 | 7687 | reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx); |
32131a9c RK |
7688 | alter_reg (REGNO (reg), -1); |
7689 | } | |
cb2afeb3 | 7690 | delete_address_reloads (output_reload_insn, insn); |
ca6c03ca | 7691 | delete_insn (output_reload_insn); |
cb2afeb3 R |
7692 | |
7693 | } | |
7694 | ||
7695 | /* We are going to delete DEAD_INSN. Recursively delete loads of | |
7696 | reload registers used in DEAD_INSN that are not used till CURRENT_INSN. | |
7697 | CURRENT_INSN is being reloaded, so we have to check its reloads too. */ | |
7698 | static void | |
7699 | delete_address_reloads (dead_insn, current_insn) | |
7700 | rtx dead_insn, current_insn; | |
7701 | { | |
7702 | rtx set = single_set (dead_insn); | |
7703 | rtx set2, dst, prev, next; | |
7704 | if (set) | |
7705 | { | |
7706 | rtx dst = SET_DEST (set); | |
7707 | if (GET_CODE (dst) == MEM) | |
7708 | delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn); | |
7709 | } | |
7710 | /* If we deleted the store from a reloaded post_{in,de}c expression, | |
7711 | we can delete the matching adds. */ | |
7712 | prev = PREV_INSN (dead_insn); | |
7713 | next = NEXT_INSN (dead_insn); | |
7714 | if (! prev || ! next) | |
7715 | return; | |
7716 | set = single_set (next); | |
7717 | set2 = single_set (prev); | |
7718 | if (! set || ! set2 | |
7719 | || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS | |
7720 | || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT | |
7721 | || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT) | |
7722 | return; | |
7723 | dst = SET_DEST (set); | |
7724 | if (! rtx_equal_p (dst, SET_DEST (set2)) | |
7725 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0)) | |
7726 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0)) | |
7727 | || (INTVAL (XEXP (SET_SRC (set), 1)) | |
1d7254c5 | 7728 | != -INTVAL (XEXP (SET_SRC (set2), 1)))) |
cb2afeb3 | 7729 | return; |
53c17031 JH |
7730 | delete_related_insns (prev); |
7731 | delete_related_insns (next); | |
cb2afeb3 R |
7732 | } |
7733 | ||
7734 | /* Subfunction of delete_address_reloads: process registers found in X. */ | |
7735 | static void | |
7736 | delete_address_reloads_1 (dead_insn, x, current_insn) | |
7737 | rtx dead_insn, x, current_insn; | |
7738 | { | |
7739 | rtx prev, set, dst, i2; | |
7740 | int i, j; | |
7741 | enum rtx_code code = GET_CODE (x); | |
7742 | ||
7743 | if (code != REG) | |
7744 | { | |
1d7254c5 | 7745 | const char *fmt = GET_RTX_FORMAT (code); |
cb2afeb3 R |
7746 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
7747 | { | |
7748 | if (fmt[i] == 'e') | |
7749 | delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn); | |
7750 | else if (fmt[i] == 'E') | |
7751 | { | |
1d7254c5 | 7752 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
cb2afeb3 R |
7753 | delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j), |
7754 | current_insn); | |
7755 | } | |
7756 | } | |
7757 | return; | |
7758 | } | |
7759 | ||
7760 | if (spill_reg_order[REGNO (x)] < 0) | |
7761 | return; | |
aa6498c2 | 7762 | |
cb2afeb3 R |
7763 | /* Scan backwards for the insn that sets x. This might be a way back due |
7764 | to inheritance. */ | |
7765 | for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev)) | |
7766 | { | |
7767 | code = GET_CODE (prev); | |
7768 | if (code == CODE_LABEL || code == JUMP_INSN) | |
7769 | return; | |
7770 | if (GET_RTX_CLASS (code) != 'i') | |
7771 | continue; | |
7772 | if (reg_set_p (x, PATTERN (prev))) | |
7773 | break; | |
7774 | if (reg_referenced_p (x, PATTERN (prev))) | |
7775 | return; | |
7776 | } | |
7777 | if (! prev || INSN_UID (prev) < reload_first_uid) | |
7778 | return; | |
7779 | /* Check that PREV only sets the reload register. */ | |
7780 | set = single_set (prev); | |
7781 | if (! set) | |
7782 | return; | |
7783 | dst = SET_DEST (set); | |
7784 | if (GET_CODE (dst) != REG | |
7785 | || ! rtx_equal_p (dst, x)) | |
7786 | return; | |
7787 | if (! reg_set_p (dst, PATTERN (dead_insn))) | |
7788 | { | |
7789 | /* Check if DST was used in a later insn - | |
7790 | it might have been inherited. */ | |
7791 | for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2)) | |
7792 | { | |
7793 | if (GET_CODE (i2) == CODE_LABEL) | |
7794 | break; | |
2c3c49de | 7795 | if (! INSN_P (i2)) |
cb2afeb3 R |
7796 | continue; |
7797 | if (reg_referenced_p (dst, PATTERN (i2))) | |
7798 | { | |
7799 | /* If there is a reference to the register in the current insn, | |
7800 | it might be loaded in a non-inherited reload. If no other | |
7801 | reload uses it, that means the register is set before | |
7802 | referenced. */ | |
7803 | if (i2 == current_insn) | |
7804 | { | |
7805 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7806 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
7807 | || reload_override_in[j] == dst) |
7808 | return; | |
7809 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7810 | if (rld[j].in && rld[j].reg_rtx == dst) |
cb2afeb3 R |
7811 | break; |
7812 | if (j >= 0) | |
7813 | break; | |
7814 | } | |
7815 | return; | |
7816 | } | |
7817 | if (GET_CODE (i2) == JUMP_INSN) | |
7818 | break; | |
cb2afeb3 | 7819 | /* If DST is still live at CURRENT_INSN, check if it is used for |
3900dc09 R |
7820 | any reload. Note that even if CURRENT_INSN sets DST, we still |
7821 | have to check the reloads. */ | |
cb2afeb3 R |
7822 | if (i2 == current_insn) |
7823 | { | |
7824 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7825 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
7826 | || reload_override_in[j] == dst) |
7827 | return; | |
7828 | /* ??? We can't finish the loop here, because dst might be | |
7829 | allocated to a pseudo in this block if no reload in this | |
7830 | block needs any of the clsses containing DST - see | |
7831 | spill_hard_reg. There is no easy way to tell this, so we | |
7832 | have to scan till the end of the basic block. */ | |
7833 | } | |
3900dc09 R |
7834 | if (reg_set_p (dst, PATTERN (i2))) |
7835 | break; | |
cb2afeb3 R |
7836 | } |
7837 | } | |
7838 | delete_address_reloads_1 (prev, SET_SRC (set), current_insn); | |
7839 | reg_reloaded_contents[REGNO (dst)] = -1; | |
ca6c03ca | 7840 | delete_insn (prev); |
32131a9c | 7841 | } |
32131a9c | 7842 | \f |
a8fdc208 | 7843 | /* Output reload-insns to reload VALUE into RELOADREG. |
858a47b1 | 7844 | VALUE is an autoincrement or autodecrement RTX whose operand |
32131a9c RK |
7845 | is a register or memory location; |
7846 | so reloading involves incrementing that location. | |
cb2afeb3 | 7847 | IN is either identical to VALUE, or some cheaper place to reload from. |
32131a9c RK |
7848 | |
7849 | INC_AMOUNT is the number to increment or decrement by (always positive). | |
cb2afeb3 | 7850 | This cannot be deduced from VALUE. |
32131a9c | 7851 | |
cb2afeb3 R |
7852 | Return the instruction that stores into RELOADREG. */ |
7853 | ||
7854 | static rtx | |
7855 | inc_for_reload (reloadreg, in, value, inc_amount) | |
32131a9c | 7856 | rtx reloadreg; |
cb2afeb3 | 7857 | rtx in, value; |
32131a9c | 7858 | int inc_amount; |
32131a9c RK |
7859 | { |
7860 | /* REG or MEM to be copied and incremented. */ | |
7861 | rtx incloc = XEXP (value, 0); | |
7862 | /* Nonzero if increment after copying. */ | |
7863 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC); | |
546b63fb | 7864 | rtx last; |
0009eff2 RK |
7865 | rtx inc; |
7866 | rtx add_insn; | |
7867 | int code; | |
cb2afeb3 R |
7868 | rtx store; |
7869 | rtx real_in = in == value ? XEXP (in, 0) : in; | |
32131a9c RK |
7870 | |
7871 | /* No hard register is equivalent to this register after | |
7872 | inc/dec operation. If REG_LAST_RELOAD_REG were non-zero, | |
7873 | we could inc/dec that register as well (maybe even using it for | |
7874 | the source), but I'm not sure it's worth worrying about. */ | |
7875 | if (GET_CODE (incloc) == REG) | |
7876 | reg_last_reload_reg[REGNO (incloc)] = 0; | |
7877 | ||
7878 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
1d7254c5 | 7879 | inc_amount = -inc_amount; |
32131a9c | 7880 | |
fb3821f7 | 7881 | inc = GEN_INT (inc_amount); |
0009eff2 RK |
7882 | |
7883 | /* If this is post-increment, first copy the location to the reload reg. */ | |
cb2afeb3 R |
7884 | if (post && real_in != reloadreg) |
7885 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
0009eff2 | 7886 | |
cb2afeb3 R |
7887 | if (in == value) |
7888 | { | |
7889 | /* See if we can directly increment INCLOC. Use a method similar to | |
7890 | that in gen_reload. */ | |
0009eff2 | 7891 | |
cb2afeb3 R |
7892 | last = get_last_insn (); |
7893 | add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc, | |
7894 | gen_rtx_PLUS (GET_MODE (incloc), | |
7895 | incloc, inc))); | |
05d10675 | 7896 | |
cb2afeb3 R |
7897 | code = recog_memoized (add_insn); |
7898 | if (code >= 0) | |
32131a9c | 7899 | { |
0eadeb15 BS |
7900 | extract_insn (add_insn); |
7901 | if (constrain_operands (1)) | |
cb2afeb3 R |
7902 | { |
7903 | /* If this is a pre-increment and we have incremented the value | |
7904 | where it lives, copy the incremented value to RELOADREG to | |
7905 | be used as an address. */ | |
0009eff2 | 7906 | |
cb2afeb3 R |
7907 | if (! post) |
7908 | emit_insn (gen_move_insn (reloadreg, incloc)); | |
546b63fb | 7909 | |
cb2afeb3 R |
7910 | return add_insn; |
7911 | } | |
32131a9c | 7912 | } |
cb2afeb3 | 7913 | delete_insns_since (last); |
32131a9c | 7914 | } |
0009eff2 | 7915 | |
0009eff2 RK |
7916 | /* If couldn't do the increment directly, must increment in RELOADREG. |
7917 | The way we do this depends on whether this is pre- or post-increment. | |
7918 | For pre-increment, copy INCLOC to the reload register, increment it | |
7919 | there, then save back. */ | |
7920 | ||
7921 | if (! post) | |
7922 | { | |
cb2afeb3 R |
7923 | if (in != reloadreg) |
7924 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
546b63fb | 7925 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 7926 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
0009eff2 | 7927 | } |
32131a9c RK |
7928 | else |
7929 | { | |
0009eff2 RK |
7930 | /* Postincrement. |
7931 | Because this might be a jump insn or a compare, and because RELOADREG | |
7932 | may not be available after the insn in an input reload, we must do | |
7933 | the incrementation before the insn being reloaded for. | |
7934 | ||
cb2afeb3 | 7935 | We have already copied IN to RELOADREG. Increment the copy in |
0009eff2 RK |
7936 | RELOADREG, save that back, then decrement RELOADREG so it has |
7937 | the original value. */ | |
7938 | ||
546b63fb | 7939 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 7940 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
546b63fb | 7941 | emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount))); |
32131a9c | 7942 | } |
0009eff2 | 7943 | |
cb2afeb3 | 7944 | return store; |
32131a9c RK |
7945 | } |
7946 | \f | |
7947 | /* Return 1 if we are certain that the constraint-string STRING allows | |
7948 | the hard register REG. Return 0 if we can't be sure of this. */ | |
7949 | ||
7950 | static int | |
7951 | constraint_accepts_reg_p (string, reg) | |
9b3142b3 | 7952 | const char *string; |
32131a9c RK |
7953 | rtx reg; |
7954 | { | |
7955 | int value = 0; | |
7956 | int regno = true_regnum (reg); | |
7957 | int c; | |
7958 | ||
7959 | /* Initialize for first alternative. */ | |
7960 | value = 0; | |
7961 | /* Check that each alternative contains `g' or `r'. */ | |
7962 | while (1) | |
7963 | switch (c = *string++) | |
7964 | { | |
7965 | case 0: | |
7966 | /* If an alternative lacks `g' or `r', we lose. */ | |
7967 | return value; | |
7968 | case ',': | |
7969 | /* If an alternative lacks `g' or `r', we lose. */ | |
7970 | if (value == 0) | |
7971 | return 0; | |
7972 | /* Initialize for next alternative. */ | |
7973 | value = 0; | |
7974 | break; | |
7975 | case 'g': | |
7976 | case 'r': | |
7977 | /* Any general reg wins for this alternative. */ | |
7978 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno)) | |
7979 | value = 1; | |
7980 | break; | |
7981 | default: | |
7982 | /* Any reg in specified class wins for this alternative. */ | |
7983 | { | |
0009eff2 | 7984 | enum reg_class class = REG_CLASS_FROM_LETTER (c); |
32131a9c | 7985 | |
0009eff2 | 7986 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)) |
32131a9c RK |
7987 | value = 1; |
7988 | } | |
7989 | } | |
7990 | } | |
7991 | \f | |
eab5c70a BS |
7992 | /* INSN is a no-op; delete it. |
7993 | If this sets the return value of the function, we must keep a USE around, | |
7994 | in case this is in a different basic block than the final USE. Otherwise, | |
7995 | we could loose important register lifeness information on | |
7996 | SMALL_REGISTER_CLASSES machines, where return registers might be used as | |
7997 | spills: subsequent passes assume that spill registers are dead at the end | |
7998 | of a basic block. | |
7999 | VALUE must be the return value in such a case, NULL otherwise. */ | |
2a9fb548 | 8000 | static void |
eab5c70a BS |
8001 | reload_cse_delete_noop_set (insn, value) |
8002 | rtx insn, value; | |
2a9fb548 | 8003 | { |
eab5c70a | 8004 | if (value) |
2a9fb548 | 8005 | { |
eab5c70a BS |
8006 | PATTERN (insn) = gen_rtx_USE (VOIDmode, value); |
8007 | INSN_CODE (insn) = -1; | |
8008 | REG_NOTES (insn) = NULL_RTX; | |
2a9fb548 | 8009 | } |
eab5c70a | 8010 | else |
ca6c03ca | 8011 | delete_insn (insn); |
2a9fb548 ILT |
8012 | } |
8013 | ||
eab5c70a | 8014 | /* See whether a single set SET is a noop. */ |
2a9fb548 | 8015 | static int |
eab5c70a BS |
8016 | reload_cse_noop_set_p (set) |
8017 | rtx set; | |
2a9fb548 | 8018 | { |
eab5c70a BS |
8019 | return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set)); |
8020 | } | |
2a9fb548 | 8021 | |
eab5c70a BS |
8022 | /* Try to simplify INSN. */ |
8023 | static void | |
8024 | reload_cse_simplify (insn) | |
8025 | rtx insn; | |
8026 | { | |
8027 | rtx body = PATTERN (insn); | |
2a9fb548 | 8028 | |
eab5c70a | 8029 | if (GET_CODE (body) == SET) |
2a9fb548 | 8030 | { |
eab5c70a | 8031 | int count = 0; |
d5ae21aa AH |
8032 | |
8033 | /* Simplify even if we may think it is a no-op. | |
8034 | We may think a memory load of a value smaller than WORD_SIZE | |
8035 | is redundant because we haven't taken into account possible | |
8036 | implicit extension. reload_cse_simplify_set() will bring | |
8037 | this out, so it's safer to simplify before we delete. */ | |
8038 | count += reload_cse_simplify_set (body, insn); | |
8039 | ||
8040 | if (!count && reload_cse_noop_set_p (body)) | |
2a9fb548 | 8041 | { |
eab5c70a BS |
8042 | rtx value = SET_DEST (body); |
8043 | if (! REG_FUNCTION_VALUE_P (SET_DEST (body))) | |
8044 | value = 0; | |
8045 | reload_cse_delete_noop_set (insn, value); | |
8046 | return; | |
2a9fb548 | 8047 | } |
2a9fb548 | 8048 | |
eab5c70a BS |
8049 | if (count > 0) |
8050 | apply_change_group (); | |
8051 | else | |
8052 | reload_cse_simplify_operands (insn); | |
8053 | } | |
8054 | else if (GET_CODE (body) == PARALLEL) | |
2a9fb548 | 8055 | { |
eab5c70a BS |
8056 | int i; |
8057 | int count = 0; | |
8058 | rtx value = NULL_RTX; | |
2a9fb548 | 8059 | |
eab5c70a BS |
8060 | /* If every action in a PARALLEL is a noop, we can delete |
8061 | the entire PARALLEL. */ | |
8062 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
2a9fb548 | 8063 | { |
eab5c70a BS |
8064 | rtx part = XVECEXP (body, 0, i); |
8065 | if (GET_CODE (part) == SET) | |
2a9fb548 | 8066 | { |
eab5c70a BS |
8067 | if (! reload_cse_noop_set_p (part)) |
8068 | break; | |
8069 | if (REG_FUNCTION_VALUE_P (SET_DEST (part))) | |
2a9fb548 | 8070 | { |
eab5c70a BS |
8071 | if (value) |
8072 | break; | |
8073 | value = SET_DEST (part); | |
2a9fb548 | 8074 | } |
2a9fb548 | 8075 | } |
eab5c70a BS |
8076 | else if (GET_CODE (part) != CLOBBER) |
8077 | break; | |
2a9fb548 | 8078 | } |
2a9fb548 | 8079 | |
eab5c70a BS |
8080 | if (i < 0) |
8081 | { | |
8082 | reload_cse_delete_noop_set (insn, value); | |
8083 | /* We're done with this insn. */ | |
8084 | return; | |
8085 | } | |
2a9fb548 | 8086 | |
eab5c70a BS |
8087 | /* It's not a no-op, but we can try to simplify it. */ |
8088 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
8089 | if (GET_CODE (XVECEXP (body, 0, i)) == SET) | |
8090 | count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn); | |
8091 | ||
8092 | if (count > 0) | |
8093 | apply_change_group (); | |
8094 | else | |
8095 | reload_cse_simplify_operands (insn); | |
8096 | } | |
2a9fb548 ILT |
8097 | } |
8098 | ||
8099 | /* Do a very simple CSE pass over the hard registers. | |
8100 | ||
8101 | This function detects no-op moves where we happened to assign two | |
8102 | different pseudo-registers to the same hard register, and then | |
8103 | copied one to the other. Reload will generate a useless | |
8104 | instruction copying a register to itself. | |
8105 | ||
8106 | This function also detects cases where we load a value from memory | |
8107 | into two different registers, and (if memory is more expensive than | |
8108 | registers) changes it to simply copy the first register into the | |
05d10675 | 8109 | second register. |
e9a25f70 JL |
8110 | |
8111 | Another optimization is performed that scans the operands of each | |
8112 | instruction to see whether the value is already available in a | |
8113 | hard register. It then replaces the operand with the hard register | |
8114 | if possible, much like an optional reload would. */ | |
2a9fb548 | 8115 | |
5adf6da0 R |
8116 | static void |
8117 | reload_cse_regs_1 (first) | |
2a9fb548 ILT |
8118 | rtx first; |
8119 | { | |
2a9fb548 ILT |
8120 | rtx insn; |
8121 | ||
1d7254c5 | 8122 | cselib_init (); |
cbfc3ad3 RK |
8123 | init_alias_analysis (); |
8124 | ||
2a9fb548 ILT |
8125 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
8126 | { | |
2c3c49de | 8127 | if (INSN_P (insn)) |
eab5c70a | 8128 | reload_cse_simplify (insn); |
2a9fb548 | 8129 | |
eab5c70a | 8130 | cselib_process_insn (insn); |
2a9fb548 ILT |
8131 | } |
8132 | ||
e05e2395 MM |
8133 | /* Clean up. */ |
8134 | end_alias_analysis (); | |
eab5c70a | 8135 | cselib_finish (); |
2a9fb548 ILT |
8136 | } |
8137 | ||
5adf6da0 R |
8138 | /* Call cse / combine like post-reload optimization phases. |
8139 | FIRST is the first instruction. */ | |
8140 | void | |
8141 | reload_cse_regs (first) | |
8142 | rtx first; | |
8143 | { | |
8144 | reload_cse_regs_1 (first); | |
8145 | reload_combine (); | |
8146 | reload_cse_move2add (first); | |
8147 | if (flag_expensive_optimizations) | |
8148 | reload_cse_regs_1 (first); | |
8149 | } | |
8150 | ||
2a9fb548 | 8151 | /* Try to simplify a single SET instruction. SET is the set pattern. |
e9a25f70 JL |
8152 | INSN is the instruction it came from. |
8153 | This function only handles one case: if we set a register to a value | |
8154 | which is not a register, we try to find that value in some other register | |
8155 | and change the set into a register copy. */ | |
2a9fb548 | 8156 | |
e9a25f70 | 8157 | static int |
2a9fb548 ILT |
8158 | reload_cse_simplify_set (set, insn) |
8159 | rtx set; | |
8160 | rtx insn; | |
8161 | { | |
eab5c70a | 8162 | int did_change = 0; |
2a9fb548 ILT |
8163 | int dreg; |
8164 | rtx src; | |
2a9fb548 | 8165 | enum reg_class dclass; |
eab5c70a BS |
8166 | int old_cost; |
8167 | cselib_val *val; | |
8168 | struct elt_loc_list *l; | |
78adc5a0 RH |
8169 | #ifdef LOAD_EXTEND_OP |
8170 | enum rtx_code extend_op = NIL; | |
8171 | #endif | |
2a9fb548 | 8172 | |
2a9fb548 ILT |
8173 | dreg = true_regnum (SET_DEST (set)); |
8174 | if (dreg < 0) | |
e9a25f70 | 8175 | return 0; |
2a9fb548 ILT |
8176 | |
8177 | src = SET_SRC (set); | |
8178 | if (side_effects_p (src) || true_regnum (src) >= 0) | |
e9a25f70 | 8179 | return 0; |
2a9fb548 | 8180 | |
cbd5b9a2 KR |
8181 | dclass = REGNO_REG_CLASS (dreg); |
8182 | ||
78adc5a0 RH |
8183 | #ifdef LOAD_EXTEND_OP |
8184 | /* When replacing a memory with a register, we need to honor assumptions | |
8185 | that combine made wrt the contents of sign bits. We'll do this by | |
8186 | generating an extend instruction instead of a reg->reg copy. Thus | |
8187 | the destination must be a register that we can widen. */ | |
8188 | if (GET_CODE (src) == MEM | |
8189 | && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD | |
8190 | && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL | |
8191 | && GET_CODE (SET_DEST (set)) != REG) | |
8192 | return 0; | |
8193 | #endif | |
8194 | ||
33ab8de0 | 8195 | /* If memory loads are cheaper than register copies, don't change them. */ |
eab5c70a BS |
8196 | if (GET_CODE (src) == MEM) |
8197 | old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1); | |
8198 | else if (CONSTANT_P (src)) | |
8199 | old_cost = rtx_cost (src, SET); | |
8200 | else if (GET_CODE (src) == REG) | |
e56b4594 AO |
8201 | old_cost = REGISTER_MOVE_COST (GET_MODE (src), |
8202 | REGNO_REG_CLASS (REGNO (src)), dclass); | |
eab5c70a BS |
8203 | else |
8204 | /* ??? */ | |
8205 | old_cost = rtx_cost (src, SET); | |
2a9fb548 | 8206 | |
70bbeb8b | 8207 | val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0); |
eab5c70a | 8208 | if (! val) |
0254c561 | 8209 | return 0; |
eab5c70a | 8210 | for (l = val->locs; l; l = l->next) |
2a9fb548 | 8211 | { |
78adc5a0 | 8212 | rtx this_rtx = l->loc; |
eab5c70a | 8213 | int this_cost; |
78adc5a0 RH |
8214 | |
8215 | if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0)) | |
8216 | { | |
8217 | #ifdef LOAD_EXTEND_OP | |
8218 | if (extend_op != NIL) | |
8219 | { | |
8220 | HOST_WIDE_INT this_val; | |
8221 | ||
8222 | /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other | |
8223 | constants, such as SYMBOL_REF, cannot be extended. */ | |
8224 | if (GET_CODE (this_rtx) != CONST_INT) | |
8225 | continue; | |
8226 | ||
8227 | this_val = INTVAL (this_rtx); | |
8228 | switch (extend_op) | |
8229 | { | |
8230 | case ZERO_EXTEND: | |
8231 | this_val &= GET_MODE_MASK (GET_MODE (src)); | |
8232 | break; | |
8233 | case SIGN_EXTEND: | |
8234 | /* ??? In theory we're already extended. */ | |
8235 | if (this_val == trunc_int_for_mode (this_val, GET_MODE (src))) | |
8236 | break; | |
8237 | default: | |
8238 | abort (); | |
8239 | } | |
5cada064 | 8240 | this_rtx = GEN_INT (this_val); |
78adc5a0 RH |
8241 | } |
8242 | #endif | |
8243 | this_cost = rtx_cost (this_rtx, SET); | |
8244 | } | |
8245 | else if (GET_CODE (this_rtx) == REG) | |
8246 | { | |
8247 | #ifdef LOAD_EXTEND_OP | |
8248 | if (extend_op != NIL) | |
8249 | { | |
8250 | this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx); | |
8251 | this_cost = rtx_cost (this_rtx, SET); | |
8252 | } | |
8253 | else | |
8254 | #endif | |
8255 | this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx), | |
8256 | REGNO_REG_CLASS (REGNO (this_rtx)), | |
8257 | dclass); | |
8258 | } | |
eab5c70a BS |
8259 | else |
8260 | continue; | |
78adc5a0 RH |
8261 | |
8262 | /* If equal costs, prefer registers over anything else. That | |
8263 | tends to lead to smaller instructions on some machines. */ | |
8264 | if (this_cost < old_cost | |
8265 | || (this_cost == old_cost | |
8266 | && GET_CODE (this_rtx) == REG | |
8267 | && GET_CODE (SET_SRC (set)) != REG)) | |
8268 | { | |
8269 | #ifdef LOAD_EXTEND_OP | |
b216e516 JL |
8270 | if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD |
8271 | && extend_op != NIL) | |
8272 | { | |
8273 | rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set))); | |
8274 | ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set)); | |
8275 | validate_change (insn, &SET_DEST (set), wide_dest, 1); | |
8276 | } | |
78adc5a0 RH |
8277 | #endif |
8278 | ||
8279 | validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1); | |
8280 | old_cost = this_cost, did_change = 1; | |
8281 | } | |
e9a25f70 | 8282 | } |
eab5c70a BS |
8283 | |
8284 | return did_change; | |
e9a25f70 JL |
8285 | } |
8286 | ||
8287 | /* Try to replace operands in INSN with equivalent values that are already | |
05d10675 BS |
8288 | in registers. This can be viewed as optional reloading. |
8289 | ||
e9a25f70 JL |
8290 | For each non-register operand in the insn, see if any hard regs are |
8291 | known to be equivalent to that operand. Record the alternatives which | |
8292 | can accept these hard registers. Among all alternatives, select the | |
8293 | ones which are better or equal to the one currently matching, where | |
8294 | "better" is in terms of '?' and '!' constraints. Among the remaining | |
8295 | alternatives, select the one which replaces most operands with | |
8296 | hard registers. */ | |
8297 | ||
8298 | static int | |
8299 | reload_cse_simplify_operands (insn) | |
8300 | rtx insn; | |
8301 | { | |
1d7254c5 | 8302 | int i, j; |
e9a25f70 | 8303 | |
eab5c70a BS |
8304 | /* For each operand, all registers that are equivalent to it. */ |
8305 | HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS]; | |
8306 | ||
9b3142b3 | 8307 | const char *constraints[MAX_RECOG_OPERANDS]; |
05d10675 | 8308 | |
e9a25f70 JL |
8309 | /* Vector recording how bad an alternative is. */ |
8310 | int *alternative_reject; | |
8311 | /* Vector recording how many registers can be introduced by choosing | |
8312 | this alternative. */ | |
8313 | int *alternative_nregs; | |
8314 | /* Array of vectors recording, for each operand and each alternative, | |
8315 | which hard register to substitute, or -1 if the operand should be | |
8316 | left as it is. */ | |
8317 | int *op_alt_regno[MAX_RECOG_OPERANDS]; | |
8318 | /* Array of alternatives, sorted in order of decreasing desirability. */ | |
8319 | int *alternative_order; | |
0254c561 | 8320 | rtx reg = gen_rtx_REG (VOIDmode, -1); |
05d10675 | 8321 | |
0eadeb15 | 8322 | extract_insn (insn); |
e9a25f70 | 8323 | |
1ccbefce | 8324 | if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0) |
1d300e19 | 8325 | return 0; |
e9a25f70 JL |
8326 | |
8327 | /* Figure out which alternative currently matches. */ | |
0eadeb15 | 8328 | if (! constrain_operands (1)) |
b8705408 | 8329 | fatal_insn_not_found (insn); |
1d7254c5 | 8330 | |
1ccbefce RH |
8331 | alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int)); |
8332 | alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int)); | |
8333 | alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int)); | |
961192e1 JM |
8334 | memset ((char *)alternative_reject, 0, recog_data.n_alternatives * sizeof (int)); |
8335 | memset ((char *)alternative_nregs, 0, recog_data.n_alternatives * sizeof (int)); | |
e9a25f70 | 8336 | |
eab5c70a BS |
8337 | /* For each operand, find out which regs are equivalent. */ |
8338 | for (i = 0; i < recog_data.n_operands; i++) | |
8339 | { | |
8340 | cselib_val *v; | |
8341 | struct elt_loc_list *l; | |
8342 | ||
8343 | CLEAR_HARD_REG_SET (equiv_regs[i]); | |
8344 | ||
8345 | /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem | |
70bbeb8b BS |
8346 | right, so avoid the problem here. Likewise if we have a constant |
8347 | and the insn pattern doesn't tell us the mode we need. */ | |
8348 | if (GET_CODE (recog_data.operand[i]) == CODE_LABEL | |
8349 | || (CONSTANT_P (recog_data.operand[i]) | |
8350 | && recog_data.operand_mode[i] == VOIDmode)) | |
eab5c70a BS |
8351 | continue; |
8352 | ||
8353 | v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0); | |
8354 | if (! v) | |
8355 | continue; | |
8356 | ||
8357 | for (l = v->locs; l; l = l->next) | |
8358 | if (GET_CODE (l->loc) == REG) | |
8359 | SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc)); | |
8360 | } | |
8361 | ||
1ccbefce | 8362 | for (i = 0; i < recog_data.n_operands; i++) |
e9a25f70 JL |
8363 | { |
8364 | enum machine_mode mode; | |
8365 | int regno; | |
9b3142b3 | 8366 | const char *p; |
e9a25f70 | 8367 | |
1ccbefce RH |
8368 | op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int)); |
8369 | for (j = 0; j < recog_data.n_alternatives; j++) | |
e9a25f70 JL |
8370 | op_alt_regno[i][j] = -1; |
8371 | ||
1ccbefce RH |
8372 | p = constraints[i] = recog_data.constraints[i]; |
8373 | mode = recog_data.operand_mode[i]; | |
e9a25f70 JL |
8374 | |
8375 | /* Add the reject values for each alternative given by the constraints | |
8376 | for this operand. */ | |
8377 | j = 0; | |
8378 | while (*p != '\0') | |
8379 | { | |
8380 | char c = *p++; | |
8381 | if (c == ',') | |
8382 | j++; | |
8383 | else if (c == '?') | |
8384 | alternative_reject[j] += 3; | |
8385 | else if (c == '!') | |
8386 | alternative_reject[j] += 300; | |
8387 | } | |
8388 | ||
8389 | /* We won't change operands which are already registers. We | |
8390 | also don't want to modify output operands. */ | |
1ccbefce | 8391 | regno = true_regnum (recog_data.operand[i]); |
e9a25f70 JL |
8392 | if (regno >= 0 |
8393 | || constraints[i][0] == '=' | |
8394 | || constraints[i][0] == '+') | |
8395 | continue; | |
8396 | ||
8397 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
8398 | { | |
8399 | int class = (int) NO_REGS; | |
8400 | ||
eab5c70a | 8401 | if (! TEST_HARD_REG_BIT (equiv_regs[i], regno)) |
e9a25f70 JL |
8402 | continue; |
8403 | ||
0254c561 JC |
8404 | REGNO (reg) = regno; |
8405 | PUT_MODE (reg, mode); | |
8406 | ||
e9a25f70 JL |
8407 | /* We found a register equal to this operand. Now look for all |
8408 | alternatives that can accept this register and have not been | |
8409 | assigned a register they can use yet. */ | |
8410 | j = 0; | |
8411 | p = constraints[i]; | |
8412 | for (;;) | |
31418d35 | 8413 | { |
e9a25f70 | 8414 | char c = *p++; |
05d10675 | 8415 | |
e9a25f70 | 8416 | switch (c) |
31418d35 | 8417 | { |
e9a25f70 JL |
8418 | case '=': case '+': case '?': |
8419 | case '#': case '&': case '!': | |
05d10675 | 8420 | case '*': case '%': |
e9a25f70 | 8421 | case '0': case '1': case '2': case '3': case '4': |
c5c76735 | 8422 | case '5': case '6': case '7': case '8': case '9': |
e9a25f70 JL |
8423 | case 'm': case '<': case '>': case 'V': case 'o': |
8424 | case 'E': case 'F': case 'G': case 'H': | |
8425 | case 's': case 'i': case 'n': | |
8426 | case 'I': case 'J': case 'K': case 'L': | |
8427 | case 'M': case 'N': case 'O': case 'P': | |
e9a25f70 JL |
8428 | case 'p': case 'X': |
8429 | /* These don't say anything we care about. */ | |
8430 | break; | |
8431 | ||
8432 | case 'g': case 'r': | |
8433 | class = reg_class_subunion[(int) class][(int) GENERAL_REGS]; | |
8434 | break; | |
8435 | ||
8436 | default: | |
8437 | class | |
e51712db | 8438 | = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)]; |
e9a25f70 | 8439 | break; |
31418d35 | 8440 | |
e9a25f70 JL |
8441 | case ',': case '\0': |
8442 | /* See if REGNO fits this alternative, and set it up as the | |
8443 | replacement register if we don't have one for this | |
0254c561 | 8444 | alternative yet and the operand being replaced is not |
1d7254c5 | 8445 | a cheap CONST_INT. */ |
e9a25f70 | 8446 | if (op_alt_regno[i][j] == -1 |
0254c561 | 8447 | && reg_fits_class_p (reg, class, 0, mode) |
1ccbefce RH |
8448 | && (GET_CODE (recog_data.operand[i]) != CONST_INT |
8449 | || (rtx_cost (recog_data.operand[i], SET) | |
8450 | > rtx_cost (reg, SET)))) | |
31418d35 | 8451 | { |
e9a25f70 JL |
8452 | alternative_nregs[j]++; |
8453 | op_alt_regno[i][j] = regno; | |
31418d35 | 8454 | } |
e9a25f70 JL |
8455 | j++; |
8456 | break; | |
31418d35 ILT |
8457 | } |
8458 | ||
e9a25f70 JL |
8459 | if (c == '\0') |
8460 | break; | |
8461 | } | |
8462 | } | |
8463 | } | |
8464 | ||
8465 | /* Record all alternatives which are better or equal to the currently | |
8466 | matching one in the alternative_order array. */ | |
1ccbefce | 8467 | for (i = j = 0; i < recog_data.n_alternatives; i++) |
e9a25f70 JL |
8468 | if (alternative_reject[i] <= alternative_reject[which_alternative]) |
8469 | alternative_order[j++] = i; | |
1ccbefce | 8470 | recog_data.n_alternatives = j; |
e9a25f70 JL |
8471 | |
8472 | /* Sort it. Given a small number of alternatives, a dumb algorithm | |
8473 | won't hurt too much. */ | |
1ccbefce | 8474 | for (i = 0; i < recog_data.n_alternatives - 1; i++) |
e9a25f70 JL |
8475 | { |
8476 | int best = i; | |
8477 | int best_reject = alternative_reject[alternative_order[i]]; | |
8478 | int best_nregs = alternative_nregs[alternative_order[i]]; | |
8479 | int tmp; | |
8480 | ||
1ccbefce | 8481 | for (j = i + 1; j < recog_data.n_alternatives; j++) |
e9a25f70 JL |
8482 | { |
8483 | int this_reject = alternative_reject[alternative_order[j]]; | |
8484 | int this_nregs = alternative_nregs[alternative_order[j]]; | |
8485 | ||
8486 | if (this_reject < best_reject | |
8487 | || (this_reject == best_reject && this_nregs < best_nregs)) | |
8488 | { | |
8489 | best = j; | |
8490 | best_reject = this_reject; | |
8491 | best_nregs = this_nregs; | |
31418d35 | 8492 | } |
2a9fb548 | 8493 | } |
05d10675 | 8494 | |
e9a25f70 JL |
8495 | tmp = alternative_order[best]; |
8496 | alternative_order[best] = alternative_order[i]; | |
8497 | alternative_order[i] = tmp; | |
8498 | } | |
05d10675 | 8499 | |
e9a25f70 JL |
8500 | /* Substitute the operands as determined by op_alt_regno for the best |
8501 | alternative. */ | |
8502 | j = alternative_order[0]; | |
e9a25f70 | 8503 | |
1ccbefce | 8504 | for (i = 0; i < recog_data.n_operands; i++) |
e9a25f70 | 8505 | { |
1ccbefce | 8506 | enum machine_mode mode = recog_data.operand_mode[i]; |
e9a25f70 JL |
8507 | if (op_alt_regno[i][j] == -1) |
8508 | continue; | |
8509 | ||
1ccbefce | 8510 | validate_change (insn, recog_data.operand_loc[i], |
38a448ca | 8511 | gen_rtx_REG (mode, op_alt_regno[i][j]), 1); |
e9a25f70 JL |
8512 | } |
8513 | ||
1ccbefce | 8514 | for (i = recog_data.n_dups - 1; i >= 0; i--) |
e9a25f70 | 8515 | { |
1ccbefce RH |
8516 | int op = recog_data.dup_num[i]; |
8517 | enum machine_mode mode = recog_data.operand_mode[op]; | |
e9a25f70 JL |
8518 | |
8519 | if (op_alt_regno[op][j] == -1) | |
8520 | continue; | |
8521 | ||
1ccbefce | 8522 | validate_change (insn, recog_data.dup_loc[i], |
38a448ca | 8523 | gen_rtx_REG (mode, op_alt_regno[op][j]), 1); |
2a9fb548 | 8524 | } |
e9a25f70 | 8525 | |
e9a25f70 | 8526 | return apply_change_group (); |
2a9fb548 | 8527 | } |
5adf6da0 R |
8528 | \f |
8529 | /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg | |
8530 | addressing now. | |
8531 | This code might also be useful when reload gave up on reg+reg addresssing | |
8532 | because of clashes between the return register and INDEX_REG_CLASS. */ | |
8533 | ||
8534 | /* The maximum number of uses of a register we can keep track of to | |
8535 | replace them with reg+reg addressing. */ | |
8536 | #define RELOAD_COMBINE_MAX_USES 6 | |
8537 | ||
8538 | /* INSN is the insn where a register has ben used, and USEP points to the | |
8539 | location of the register within the rtl. */ | |
8540 | struct reg_use { rtx insn, *usep; }; | |
8541 | ||
8542 | /* If the register is used in some unknown fashion, USE_INDEX is negative. | |
8543 | If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID | |
8544 | indicates where it becomes live again. | |
8545 | Otherwise, USE_INDEX is the index of the last encountered use of the | |
8546 | register (which is first among these we have seen since we scan backwards), | |
8547 | OFFSET contains the constant offset that is added to the register in | |
8548 | all encountered uses, and USE_RUID indicates the first encountered, i.e. | |
ed937a19 R |
8549 | last, of these uses. |
8550 | STORE_RUID is always meaningful if we only want to use a value in a | |
8551 | register in a different place: it denotes the next insn in the insn | |
8552 | stream (i.e. the last ecountered) that sets or clobbers the register. */ | |
5adf6da0 R |
8553 | static struct |
8554 | { | |
8555 | struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; | |
8556 | int use_index; | |
8557 | rtx offset; | |
8558 | int store_ruid; | |
8559 | int use_ruid; | |
8560 | } reg_state[FIRST_PSEUDO_REGISTER]; | |
8561 | ||
8562 | /* Reverse linear uid. This is increased in reload_combine while scanning | |
8563 | the instructions from last to first. It is used to set last_label_ruid | |
8564 | and the store_ruid / use_ruid fields in reg_state. */ | |
8565 | static int reload_combine_ruid; | |
8566 | ||
b0634509 R |
8567 | #define LABEL_LIVE(LABEL) \ |
8568 | (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) | |
8569 | ||
5adf6da0 R |
8570 | static void |
8571 | reload_combine () | |
8572 | { | |
8573 | rtx insn, set; | |
ae0ed63a JM |
8574 | int first_index_reg = -1; |
8575 | int last_index_reg = 0; | |
5adf6da0 | 8576 | int i; |
f8cd4126 | 8577 | unsigned int r; |
5adf6da0 | 8578 | int last_label_ruid; |
b0634509 R |
8579 | int min_labelno, n_labels; |
8580 | HARD_REG_SET ever_live_at_start, *label_live; | |
5adf6da0 R |
8581 | |
8582 | /* If reg+reg can be used in offsetable memory adresses, the main chunk of | |
8583 | reload has already used it where appropriate, so there is no use in | |
8584 | trying to generate it now. */ | |
03acd8f8 | 8585 | if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS) |
5adf6da0 R |
8586 | return; |
8587 | ||
8588 | /* To avoid wasting too much time later searching for an index register, | |
8589 | determine the minimum and maximum index register numbers. */ | |
f8cd4126 RK |
8590 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
8591 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) | |
8592 | { | |
881a8969 | 8593 | if (first_index_reg == -1) |
4c3f1588 RK |
8594 | first_index_reg = r; |
8595 | ||
8596 | last_index_reg = r; | |
f8cd4126 RK |
8597 | } |
8598 | ||
5adf6da0 | 8599 | /* If no index register is available, we can quit now. */ |
881a8969 | 8600 | if (first_index_reg == -1) |
5adf6da0 R |
8601 | return; |
8602 | ||
b0634509 R |
8603 | /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime |
8604 | information is a bit fuzzy immediately after reload, but it's | |
8605 | still good enough to determine which registers are live at a jump | |
8606 | destination. */ | |
8607 | min_labelno = get_first_label_num (); | |
8608 | n_labels = max_label_num () - min_labelno; | |
8609 | label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET)); | |
8610 | CLEAR_HARD_REG_SET (ever_live_at_start); | |
f8cd4126 | 8611 | |
b0634509 R |
8612 | for (i = n_basic_blocks - 1; i >= 0; i--) |
8613 | { | |
3b413743 | 8614 | insn = BLOCK_HEAD (i); |
b0634509 R |
8615 | if (GET_CODE (insn) == CODE_LABEL) |
8616 | { | |
8617 | HARD_REG_SET live; | |
8618 | ||
f8cd4126 RK |
8619 | REG_SET_TO_HARD_REG_SET (live, |
8620 | BASIC_BLOCK (i)->global_live_at_start); | |
8621 | compute_use_by_pseudos (&live, | |
8622 | BASIC_BLOCK (i)->global_live_at_start); | |
b0634509 R |
8623 | COPY_HARD_REG_SET (LABEL_LIVE (insn), live); |
8624 | IOR_HARD_REG_SET (ever_live_at_start, live); | |
8625 | } | |
8626 | } | |
8627 | ||
5adf6da0 R |
8628 | /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ |
8629 | last_label_ruid = reload_combine_ruid = 0; | |
f8cd4126 | 8630 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
5adf6da0 | 8631 | { |
f8cd4126 RK |
8632 | reg_state[r].store_ruid = reload_combine_ruid; |
8633 | if (fixed_regs[r]) | |
8634 | reg_state[r].use_index = -1; | |
5adf6da0 | 8635 | else |
f8cd4126 | 8636 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; |
5adf6da0 R |
8637 | } |
8638 | ||
8639 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
8640 | { | |
8641 | rtx note; | |
8642 | ||
8643 | /* We cannot do our optimization across labels. Invalidating all the use | |
8644 | information we have would be costly, so we just note where the label | |
05d10675 | 8645 | is and then later disable any optimization that would cross it. */ |
5adf6da0 R |
8646 | if (GET_CODE (insn) == CODE_LABEL) |
8647 | last_label_ruid = reload_combine_ruid; | |
f8cd4126 RK |
8648 | else if (GET_CODE (insn) == BARRIER) |
8649 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
8650 | if (! fixed_regs[r]) | |
8651 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
8652 | ||
2c3c49de | 8653 | if (! INSN_P (insn)) |
5adf6da0 | 8654 | continue; |
f8cd4126 | 8655 | |
5adf6da0 R |
8656 | reload_combine_ruid++; |
8657 | ||
8658 | /* Look for (set (REGX) (CONST_INT)) | |
eceef4c9 BS |
8659 | (set (REGX) (PLUS (REGX) (REGY))) |
8660 | ... | |
8661 | ... (MEM (REGX)) ... | |
5adf6da0 | 8662 | and convert it to |
eceef4c9 BS |
8663 | (set (REGZ) (CONST_INT)) |
8664 | ... | |
8665 | ... (MEM (PLUS (REGZ) (REGY)))... . | |
5adf6da0 R |
8666 | |
8667 | First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | |
8668 | and that we know all uses of REGX before it dies. */ | |
2abbc1bd R |
8669 | set = single_set (insn); |
8670 | if (set != NULL_RTX | |
5adf6da0 R |
8671 | && GET_CODE (SET_DEST (set)) == REG |
8672 | && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)), | |
8673 | GET_MODE (SET_DEST (set))) | |
8674 | == 1) | |
8675 | && GET_CODE (SET_SRC (set)) == PLUS | |
8676 | && GET_CODE (XEXP (SET_SRC (set), 1)) == REG | |
8677 | && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set)) | |
8678 | && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid) | |
8679 | { | |
8680 | rtx reg = SET_DEST (set); | |
8681 | rtx plus = SET_SRC (set); | |
8682 | rtx base = XEXP (plus, 1); | |
8683 | rtx prev = prev_nonnote_insn (insn); | |
8684 | rtx prev_set = prev ? single_set (prev) : NULL_RTX; | |
f8cd4126 | 8685 | unsigned int regno = REGNO (reg); |
6a651371 | 8686 | rtx const_reg = NULL_RTX; |
5adf6da0 R |
8687 | rtx reg_sum = NULL_RTX; |
8688 | ||
8689 | /* Now, we need an index register. | |
8690 | We'll set index_reg to this index register, const_reg to the | |
8691 | register that is to be loaded with the constant | |
8692 | (denoted as REGZ in the substitution illustration above), | |
8693 | and reg_sum to the register-register that we want to use to | |
8694 | substitute uses of REG (typically in MEMs) with. | |
8695 | First check REG and BASE for being index registers; | |
8696 | we can use them even if they are not dead. */ | |
8697 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | |
8698 | || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | |
8699 | REGNO (base))) | |
8700 | { | |
8701 | const_reg = reg; | |
8702 | reg_sum = plus; | |
8703 | } | |
8704 | else | |
8705 | { | |
05d10675 BS |
8706 | /* Otherwise, look for a free index register. Since we have |
8707 | checked above that neiter REG nor BASE are index registers, | |
8708 | if we find anything at all, it will be different from these | |
8709 | two registers. */ | |
8710 | for (i = first_index_reg; i <= last_index_reg; i++) | |
5adf6da0 | 8711 | { |
f8cd4126 RK |
8712 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], |
8713 | i) | |
5adf6da0 R |
8714 | && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES |
8715 | && reg_state[i].store_ruid <= reg_state[regno].use_ruid | |
8716 | && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1) | |
8717 | { | |
8718 | rtx index_reg = gen_rtx_REG (GET_MODE (reg), i); | |
f8cd4126 | 8719 | |
5adf6da0 R |
8720 | const_reg = index_reg; |
8721 | reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | |
8722 | break; | |
8723 | } | |
8724 | } | |
8725 | } | |
f8cd4126 | 8726 | |
ed937a19 R |
8727 | /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that |
8728 | (REGY), i.e. BASE, is not clobbered before the last use we'll | |
8729 | create. */ | |
f8cd4126 | 8730 | if (prev_set != 0 |
5adf6da0 R |
8731 | && GET_CODE (SET_SRC (prev_set)) == CONST_INT |
8732 | && rtx_equal_p (SET_DEST (prev_set), reg) | |
8733 | && reg_state[regno].use_index >= 0 | |
f8cd4126 RK |
8734 | && (reg_state[REGNO (base)].store_ruid |
8735 | <= reg_state[regno].use_ruid) | |
8736 | && reg_sum != 0) | |
5adf6da0 R |
8737 | { |
8738 | int i; | |
8739 | ||
f8cd4126 | 8740 | /* Change destination register and, if necessary, the |
5adf6da0 R |
8741 | constant value in PREV, the constant loading instruction. */ |
8742 | validate_change (prev, &SET_DEST (prev_set), const_reg, 1); | |
8743 | if (reg_state[regno].offset != const0_rtx) | |
8744 | validate_change (prev, | |
8745 | &SET_SRC (prev_set), | |
8746 | GEN_INT (INTVAL (SET_SRC (prev_set)) | |
8747 | + INTVAL (reg_state[regno].offset)), | |
8748 | 1); | |
f8cd4126 | 8749 | |
5adf6da0 R |
8750 | /* Now for every use of REG that we have recorded, replace REG |
8751 | with REG_SUM. */ | |
8752 | for (i = reg_state[regno].use_index; | |
8753 | i < RELOAD_COMBINE_MAX_USES; i++) | |
8754 | validate_change (reg_state[regno].reg_use[i].insn, | |
8755 | reg_state[regno].reg_use[i].usep, | |
8756 | reg_sum, 1); | |
8757 | ||
8758 | if (apply_change_group ()) | |
8759 | { | |
8760 | rtx *np; | |
8761 | ||
8762 | /* Delete the reg-reg addition. */ | |
ca6c03ca | 8763 | delete_insn (insn); |
5adf6da0 R |
8764 | |
8765 | if (reg_state[regno].offset != const0_rtx) | |
f8cd4126 RK |
8766 | /* Previous REG_EQUIV / REG_EQUAL notes for PREV |
8767 | are now invalid. */ | |
1d7254c5 | 8768 | for (np = ®_NOTES (prev); *np;) |
f8cd4126 RK |
8769 | { |
8770 | if (REG_NOTE_KIND (*np) == REG_EQUAL | |
8771 | || REG_NOTE_KIND (*np) == REG_EQUIV) | |
8772 | *np = XEXP (*np, 1); | |
8773 | else | |
8774 | np = &XEXP (*np, 1); | |
8775 | } | |
8776 | ||
5adf6da0 | 8777 | reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; |
f8cd4126 RK |
8778 | reg_state[REGNO (const_reg)].store_ruid |
8779 | = reload_combine_ruid; | |
5adf6da0 R |
8780 | continue; |
8781 | } | |
8782 | } | |
8783 | } | |
f8cd4126 | 8784 | |
1d7254c5 | 8785 | note_stores (PATTERN (insn), reload_combine_note_store, NULL); |
f8cd4126 | 8786 | |
5adf6da0 R |
8787 | if (GET_CODE (insn) == CALL_INSN) |
8788 | { | |
8789 | rtx link; | |
8790 | ||
f8cd4126 RK |
8791 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
8792 | if (call_used_regs[r]) | |
8793 | { | |
8794 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
8795 | reg_state[r].store_ruid = reload_combine_ruid; | |
8796 | } | |
8797 | ||
5adf6da0 R |
8798 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; |
8799 | link = XEXP (link, 1)) | |
6a69653a CM |
8800 | { |
8801 | rtx usage_rtx = XEXP (XEXP (link, 0), 0); | |
8802 | if (GET_CODE (usage_rtx) == REG) | |
8803 | { | |
ae0ed63a | 8804 | unsigned int i; |
6a69653a CM |
8805 | unsigned int start_reg = REGNO (usage_rtx); |
8806 | unsigned int num_regs = | |
8807 | HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx)); | |
8808 | unsigned int end_reg = start_reg + num_regs - 1; | |
8809 | for (i = start_reg; i <= end_reg; i++) | |
8810 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
8811 | { | |
8812 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | |
8813 | reg_state[i].store_ruid = reload_combine_ruid; | |
8814 | } | |
8815 | else | |
8816 | reg_state[i].use_index = -1; | |
8817 | } | |
8818 | } | |
f8cd4126 | 8819 | |
5adf6da0 | 8820 | } |
f8cd4126 RK |
8821 | else if (GET_CODE (insn) == JUMP_INSN |
8822 | && GET_CODE (PATTERN (insn)) != RETURN) | |
5adf6da0 R |
8823 | { |
8824 | /* Non-spill registers might be used at the call destination in | |
8825 | some unknown fashion, so we have to mark the unknown use. */ | |
b0634509 | 8826 | HARD_REG_SET *live; |
f8cd4126 | 8827 | |
b0634509 R |
8828 | if ((condjump_p (insn) || condjump_in_parallel_p (insn)) |
8829 | && JUMP_LABEL (insn)) | |
8830 | live = &LABEL_LIVE (JUMP_LABEL (insn)); | |
8831 | else | |
8832 | live = &ever_live_at_start; | |
f8cd4126 | 8833 | |
5adf6da0 | 8834 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i) |
f8cd4126 RK |
8835 | if (TEST_HARD_REG_BIT (*live, i)) |
8836 | reg_state[i].use_index = -1; | |
5adf6da0 | 8837 | } |
f8cd4126 | 8838 | |
5adf6da0 R |
8839 | reload_combine_note_use (&PATTERN (insn), insn); |
8840 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
8841 | { | |
8842 | if (REG_NOTE_KIND (note) == REG_INC | |
8843 | && GET_CODE (XEXP (note, 0)) == REG) | |
ed937a19 R |
8844 | { |
8845 | int regno = REGNO (XEXP (note, 0)); | |
8846 | ||
8847 | reg_state[regno].store_ruid = reload_combine_ruid; | |
8848 | reg_state[regno].use_index = -1; | |
8849 | } | |
5adf6da0 R |
8850 | } |
8851 | } | |
f8cd4126 | 8852 | |
b0634509 | 8853 | free (label_live); |
5adf6da0 R |
8854 | } |
8855 | ||
8856 | /* Check if DST is a register or a subreg of a register; if it is, | |
8857 | update reg_state[regno].store_ruid and reg_state[regno].use_index | |
f93233bb | 8858 | accordingly. Called via note_stores from reload_combine. */ |
f8cd4126 | 8859 | |
5adf6da0 | 8860 | static void |
84832317 | 8861 | reload_combine_note_store (dst, set, data) |
f93233bb | 8862 | rtx dst, set; |
84832317 | 8863 | void *data ATTRIBUTE_UNUSED; |
5adf6da0 R |
8864 | { |
8865 | int regno = 0; | |
8866 | int i; | |
54ed0905 | 8867 | enum machine_mode mode = GET_MODE (dst); |
5adf6da0 R |
8868 | |
8869 | if (GET_CODE (dst) == SUBREG) | |
8870 | { | |
ddef6bc7 JJ |
8871 | regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), |
8872 | GET_MODE (SUBREG_REG (dst)), | |
8873 | SUBREG_BYTE (dst), | |
8874 | GET_MODE (dst)); | |
5adf6da0 R |
8875 | dst = SUBREG_REG (dst); |
8876 | } | |
8877 | if (GET_CODE (dst) != REG) | |
8878 | return; | |
8879 | regno += REGNO (dst); | |
54ca6ffa | 8880 | |
5adf6da0 | 8881 | /* note_stores might have stripped a STRICT_LOW_PART, so we have to be |
05d10675 | 8882 | careful with registers / register parts that are not full words. |
54ca6ffa JL |
8883 | |
8884 | Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */ | |
8885 | if (GET_CODE (set) != SET | |
8886 | || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT | |
8887 | || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT | |
8888 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) | |
ed937a19 | 8889 | { |
54ed0905 | 8890 | for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--) |
f93233bb JL |
8891 | { |
8892 | reg_state[i].use_index = -1; | |
8893 | reg_state[i].store_ruid = reload_combine_ruid; | |
8894 | } | |
ed937a19 | 8895 | } |
5adf6da0 R |
8896 | else |
8897 | { | |
54ed0905 | 8898 | for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--) |
5adf6da0 R |
8899 | { |
8900 | reg_state[i].store_ruid = reload_combine_ruid; | |
8901 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | |
8902 | } | |
8903 | } | |
8904 | } | |
8905 | ||
8906 | /* XP points to a piece of rtl that has to be checked for any uses of | |
8907 | registers. | |
8908 | *XP is the pattern of INSN, or a part of it. | |
8909 | Called from reload_combine, and recursively by itself. */ | |
8910 | static void | |
8911 | reload_combine_note_use (xp, insn) | |
8912 | rtx *xp, insn; | |
8913 | { | |
8914 | rtx x = *xp; | |
8915 | enum rtx_code code = x->code; | |
6f7d635c | 8916 | const char *fmt; |
5adf6da0 R |
8917 | int i, j; |
8918 | rtx offset = const0_rtx; /* For the REG case below. */ | |
8919 | ||
8920 | switch (code) | |
8921 | { | |
8922 | case SET: | |
8923 | if (GET_CODE (SET_DEST (x)) == REG) | |
8924 | { | |
8925 | reload_combine_note_use (&SET_SRC (x), insn); | |
8926 | return; | |
8927 | } | |
8928 | break; | |
8929 | ||
6ce7e0f9 R |
8930 | case USE: |
8931 | /* If this is the USE of a return value, we can't change it. */ | |
8932 | if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0))) | |
8933 | { | |
8934 | /* Mark the return register as used in an unknown fashion. */ | |
8935 | rtx reg = XEXP (x, 0); | |
8936 | int regno = REGNO (reg); | |
8937 | int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
8938 | ||
8939 | while (--nregs >= 0) | |
8940 | reg_state[regno + nregs].use_index = -1; | |
8941 | return; | |
8942 | } | |
8943 | break; | |
8944 | ||
5adf6da0 R |
8945 | case CLOBBER: |
8946 | if (GET_CODE (SET_DEST (x)) == REG) | |
3d17d93d AO |
8947 | { |
8948 | /* No spurious CLOBBERs of pseudo registers may remain. */ | |
8949 | if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER) | |
8950 | abort (); | |
8951 | return; | |
8952 | } | |
5adf6da0 R |
8953 | break; |
8954 | ||
8955 | case PLUS: | |
8956 | /* We are interested in (plus (reg) (const_int)) . */ | |
1d7254c5 KH |
8957 | if (GET_CODE (XEXP (x, 0)) != REG |
8958 | || GET_CODE (XEXP (x, 1)) != CONST_INT) | |
5adf6da0 R |
8959 | break; |
8960 | offset = XEXP (x, 1); | |
8961 | x = XEXP (x, 0); | |
05d10675 | 8962 | /* Fall through. */ |
5adf6da0 R |
8963 | case REG: |
8964 | { | |
8965 | int regno = REGNO (x); | |
8966 | int use_index; | |
6ce7e0f9 | 8967 | int nregs; |
5adf6da0 | 8968 | |
3d17d93d | 8969 | /* No spurious USEs of pseudo registers may remain. */ |
5adf6da0 | 8970 | if (regno >= FIRST_PSEUDO_REGISTER) |
3d17d93d | 8971 | abort (); |
5adf6da0 | 8972 | |
6ce7e0f9 R |
8973 | nregs = HARD_REGNO_NREGS (regno, GET_MODE (x)); |
8974 | ||
8975 | /* We can't substitute into multi-hard-reg uses. */ | |
8976 | if (nregs > 1) | |
8977 | { | |
8978 | while (--nregs >= 0) | |
8979 | reg_state[regno + nregs].use_index = -1; | |
8980 | return; | |
8981 | } | |
8982 | ||
5adf6da0 R |
8983 | /* If this register is already used in some unknown fashion, we |
8984 | can't do anything. | |
8985 | If we decrement the index from zero to -1, we can't store more | |
8986 | uses, so this register becomes used in an unknown fashion. */ | |
8987 | use_index = --reg_state[regno].use_index; | |
8988 | if (use_index < 0) | |
8989 | return; | |
8990 | ||
8991 | if (use_index != RELOAD_COMBINE_MAX_USES - 1) | |
8992 | { | |
8993 | /* We have found another use for a register that is already | |
8994 | used later. Check if the offsets match; if not, mark the | |
8995 | register as used in an unknown fashion. */ | |
8996 | if (! rtx_equal_p (offset, reg_state[regno].offset)) | |
8997 | { | |
8998 | reg_state[regno].use_index = -1; | |
8999 | return; | |
9000 | } | |
9001 | } | |
9002 | else | |
9003 | { | |
9004 | /* This is the first use of this register we have seen since we | |
9005 | marked it as dead. */ | |
9006 | reg_state[regno].offset = offset; | |
9007 | reg_state[regno].use_ruid = reload_combine_ruid; | |
9008 | } | |
9009 | reg_state[regno].reg_use[use_index].insn = insn; | |
9010 | reg_state[regno].reg_use[use_index].usep = xp; | |
9011 | return; | |
9012 | } | |
9013 | ||
9014 | default: | |
9015 | break; | |
9016 | } | |
9017 | ||
9018 | /* Recursively process the components of X. */ | |
9019 | fmt = GET_RTX_FORMAT (code); | |
9020 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
9021 | { | |
9022 | if (fmt[i] == 'e') | |
9023 | reload_combine_note_use (&XEXP (x, i), insn); | |
9024 | else if (fmt[i] == 'E') | |
9025 | { | |
9026 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
9027 | reload_combine_note_use (&XVECEXP (x, i, j), insn); | |
9028 | } | |
9029 | } | |
9030 | } | |
9031 | \f | |
61f5625b AO |
9032 | /* See if we can reduce the cost of a constant by replacing a move |
9033 | with an add. We track situations in which a register is set to a | |
9034 | constant or to a register plus a constant. */ | |
5adf6da0 R |
9035 | /* We cannot do our optimization across labels. Invalidating all the |
9036 | information about register contents we have would be costly, so we | |
61f5625b AO |
9037 | use move2add_last_label_luid to note where the label is and then |
9038 | later disable any optimization that would cross it. | |
5adf6da0 | 9039 | reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if |
61f5625b | 9040 | reg_set_luid[n] is greater than last_label_luid[n] . */ |
5adf6da0 | 9041 | static int reg_set_luid[FIRST_PSEUDO_REGISTER]; |
770ae6cc | 9042 | |
61f5625b AO |
9043 | /* If reg_base_reg[n] is negative, register n has been set to |
9044 | reg_offset[n] in mode reg_mode[n] . | |
9045 | If reg_base_reg[n] is non-negative, register n has been set to the | |
9046 | sum of reg_offset[n] and the value of register reg_base_reg[n] | |
dc297297 | 9047 | before reg_set_luid[n], calculated in mode reg_mode[n] . */ |
61f5625b | 9048 | static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; |
5adf6da0 R |
9049 | static int reg_base_reg[FIRST_PSEUDO_REGISTER]; |
9050 | static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; | |
770ae6cc | 9051 | |
5adf6da0 R |
9052 | /* move2add_luid is linearily increased while scanning the instructions |
9053 | from first to last. It is used to set reg_set_luid in | |
6764d250 | 9054 | reload_cse_move2add and move2add_note_store. */ |
5adf6da0 R |
9055 | static int move2add_luid; |
9056 | ||
61f5625b AO |
9057 | /* move2add_last_label_luid is set whenever a label is found. Labels |
9058 | invalidate all previously collected reg_offset data. */ | |
9059 | static int move2add_last_label_luid; | |
9060 | ||
ccc4ae07 | 9061 | /* Generate a CONST_INT and force it in the range of MODE. */ |
770ae6cc | 9062 | |
61f5625b AO |
9063 | static HOST_WIDE_INT |
9064 | sext_for_mode (mode, value) | |
ccc4ae07 AS |
9065 | enum machine_mode mode; |
9066 | HOST_WIDE_INT value; | |
9067 | { | |
9068 | HOST_WIDE_INT cval = value & GET_MODE_MASK (mode); | |
9069 | int width = GET_MODE_BITSIZE (mode); | |
9070 | ||
9071 | /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number, | |
9072 | sign extend it. */ | |
9073 | if (width > 0 && width < HOST_BITS_PER_WIDE_INT | |
9074 | && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) | |
9075 | cval |= (HOST_WIDE_INT) -1 << width; | |
9076 | ||
61f5625b | 9077 | return cval; |
ccc4ae07 AS |
9078 | } |
9079 | ||
61f5625b AO |
9080 | /* ??? We don't know how zero / sign extension is handled, hence we |
9081 | can't go from a narrower to a wider mode. */ | |
9082 | #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \ | |
9083 | (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \ | |
9084 | || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \ | |
9085 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \ | |
9086 | GET_MODE_BITSIZE (INMODE)))) | |
9087 | ||
5adf6da0 R |
9088 | static void |
9089 | reload_cse_move2add (first) | |
9090 | rtx first; | |
9091 | { | |
9092 | int i; | |
9093 | rtx insn; | |
5adf6da0 | 9094 | |
1d7254c5 | 9095 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) |
6764d250 BS |
9096 | reg_set_luid[i] = 0; |
9097 | ||
61f5625b AO |
9098 | move2add_last_label_luid = 0; |
9099 | move2add_luid = 2; | |
5adf6da0 R |
9100 | for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++) |
9101 | { | |
9102 | rtx pat, note; | |
9103 | ||
9104 | if (GET_CODE (insn) == CODE_LABEL) | |
61f5625b AO |
9105 | { |
9106 | move2add_last_label_luid = move2add_luid; | |
9107 | /* We're going to increment move2add_luid twice after a | |
9108 | label, so that we can use move2add_last_label_luid + 1 as | |
9109 | the luid for constants. */ | |
9110 | move2add_luid++; | |
9111 | continue; | |
9112 | } | |
2c3c49de | 9113 | if (! INSN_P (insn)) |
5adf6da0 R |
9114 | continue; |
9115 | pat = PATTERN (insn); | |
9116 | /* For simplicity, we only perform this optimization on | |
9117 | straightforward SETs. */ | |
9118 | if (GET_CODE (pat) == SET | |
9119 | && GET_CODE (SET_DEST (pat)) == REG) | |
9120 | { | |
9121 | rtx reg = SET_DEST (pat); | |
9122 | int regno = REGNO (reg); | |
9123 | rtx src = SET_SRC (pat); | |
9124 | ||
9125 | /* Check if we have valid information on the contents of this | |
9126 | register in the mode of REG. */ | |
61f5625b AO |
9127 | if (reg_set_luid[regno] > move2add_last_label_luid |
9128 | && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno])) | |
5adf6da0 R |
9129 | { |
9130 | /* Try to transform (set (REGX) (CONST_INT A)) | |
9131 | ... | |
9132 | (set (REGX) (CONST_INT B)) | |
9133 | to | |
9134 | (set (REGX) (CONST_INT A)) | |
9135 | ... | |
9136 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
9137 | ||
9138 | if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0) | |
9139 | { | |
9140 | int success = 0; | |
61f5625b AO |
9141 | rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg), |
9142 | INTVAL (src) | |
9143 | - reg_offset[regno])); | |
5adf6da0 R |
9144 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; |
9145 | use (set (reg) (reg)) instead. | |
9146 | We don't delete this insn, nor do we convert it into a | |
9147 | note, to avoid losing register notes or the return | |
9148 | value flag. jump2 already knowns how to get rid of | |
9149 | no-op moves. */ | |
9150 | if (new_src == const0_rtx) | |
9151 | success = validate_change (insn, &SET_SRC (pat), reg, 0); | |
9152 | else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET) | |
fb7e77d7 | 9153 | && have_add2_insn (reg, new_src)) |
5adf6da0 R |
9154 | success = validate_change (insn, &PATTERN (insn), |
9155 | gen_add2_insn (reg, new_src), 0); | |
5adf6da0 R |
9156 | reg_set_luid[regno] = move2add_luid; |
9157 | reg_mode[regno] = GET_MODE (reg); | |
61f5625b | 9158 | reg_offset[regno] = INTVAL (src); |
5adf6da0 R |
9159 | continue; |
9160 | } | |
9161 | ||
9162 | /* Try to transform (set (REGX) (REGY)) | |
9163 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
9164 | ... | |
9165 | (set (REGX) (REGY)) | |
9166 | (set (REGX) (PLUS (REGX) (CONST_INT B))) | |
9167 | to | |
9168 | (REGX) (REGY)) | |
9169 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
9170 | ... | |
9171 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
9172 | else if (GET_CODE (src) == REG | |
61f5625b AO |
9173 | && reg_set_luid[regno] == reg_set_luid[REGNO (src)] |
9174 | && reg_base_reg[regno] == reg_base_reg[REGNO (src)] | |
9175 | && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), | |
9176 | reg_mode[REGNO (src)])) | |
5adf6da0 R |
9177 | { |
9178 | rtx next = next_nonnote_insn (insn); | |
6a651371 | 9179 | rtx set = NULL_RTX; |
5adf6da0 R |
9180 | if (next) |
9181 | set = single_set (next); | |
61f5625b | 9182 | if (set |
5adf6da0 R |
9183 | && SET_DEST (set) == reg |
9184 | && GET_CODE (SET_SRC (set)) == PLUS | |
9185 | && XEXP (SET_SRC (set), 0) == reg | |
9186 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT) | |
9187 | { | |
5adf6da0 | 9188 | rtx src3 = XEXP (SET_SRC (set), 1); |
61f5625b AO |
9189 | HOST_WIDE_INT added_offset = INTVAL (src3); |
9190 | HOST_WIDE_INT base_offset = reg_offset[REGNO (src)]; | |
9191 | HOST_WIDE_INT regno_offset = reg_offset[regno]; | |
9192 | rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg), | |
9193 | added_offset | |
9194 | + base_offset | |
9195 | - regno_offset)); | |
5adf6da0 R |
9196 | int success = 0; |
9197 | ||
9198 | if (new_src == const0_rtx) | |
9199 | /* See above why we create (set (reg) (reg)) here. */ | |
9200 | success | |
9201 | = validate_change (next, &SET_SRC (set), reg, 0); | |
9202 | else if ((rtx_cost (new_src, PLUS) | |
b437f1a7 | 9203 | < COSTS_N_INSNS (1) + rtx_cost (src3, SET)) |
fb7e77d7 | 9204 | && have_add2_insn (reg, new_src)) |
5adf6da0 R |
9205 | success |
9206 | = validate_change (next, &PATTERN (next), | |
9207 | gen_add2_insn (reg, new_src), 0); | |
9208 | if (success) | |
ca6c03ca | 9209 | delete_insn (insn); |
5adf6da0 | 9210 | insn = next; |
5adf6da0 | 9211 | reg_mode[regno] = GET_MODE (reg); |
61f5625b AO |
9212 | reg_offset[regno] = sext_for_mode (GET_MODE (reg), |
9213 | added_offset | |
9214 | + base_offset); | |
5adf6da0 R |
9215 | continue; |
9216 | } | |
9217 | } | |
9218 | } | |
9219 | } | |
9220 | ||
9221 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
9222 | { | |
9223 | if (REG_NOTE_KIND (note) == REG_INC | |
9224 | && GET_CODE (XEXP (note, 0)) == REG) | |
9225 | { | |
61f5625b | 9226 | /* Reset the information about this register. */ |
5adf6da0 R |
9227 | int regno = REGNO (XEXP (note, 0)); |
9228 | if (regno < FIRST_PSEUDO_REGISTER) | |
61f5625b | 9229 | reg_set_luid[regno] = 0; |
5adf6da0 | 9230 | } |
5adf6da0 | 9231 | } |
84832317 | 9232 | note_stores (PATTERN (insn), move2add_note_store, NULL); |
5adf6da0 R |
9233 | /* If this is a CALL_INSN, all call used registers are stored with |
9234 | unknown values. */ | |
9235 | if (GET_CODE (insn) == CALL_INSN) | |
9236 | { | |
1d7254c5 | 9237 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) |
5adf6da0 R |
9238 | { |
9239 | if (call_used_regs[i]) | |
61f5625b AO |
9240 | /* Reset the information about this register. */ |
9241 | reg_set_luid[i] = 0; | |
5adf6da0 R |
9242 | } |
9243 | } | |
9244 | } | |
9245 | } | |
9246 | ||
9247 | /* SET is a SET or CLOBBER that sets DST. | |
9248 | Update reg_set_luid, reg_offset and reg_base_reg accordingly. | |
9249 | Called from reload_cse_move2add via note_stores. */ | |
770ae6cc | 9250 | |
5adf6da0 | 9251 | static void |
84832317 | 9252 | move2add_note_store (dst, set, data) |
5adf6da0 | 9253 | rtx dst, set; |
84832317 | 9254 | void *data ATTRIBUTE_UNUSED; |
5adf6da0 | 9255 | { |
770ae6cc RK |
9256 | unsigned int regno = 0; |
9257 | unsigned int i; | |
5adf6da0 | 9258 | enum machine_mode mode = GET_MODE (dst); |
770ae6cc | 9259 | |
5adf6da0 R |
9260 | if (GET_CODE (dst) == SUBREG) |
9261 | { | |
ddef6bc7 JJ |
9262 | regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), |
9263 | GET_MODE (SUBREG_REG (dst)), | |
9264 | SUBREG_BYTE (dst), | |
9265 | GET_MODE (dst)); | |
5adf6da0 R |
9266 | dst = SUBREG_REG (dst); |
9267 | } | |
770ae6cc | 9268 | |
19ca869b JR |
9269 | /* Some targets do argument pushes without adding REG_INC notes. */ |
9270 | ||
9271 | if (GET_CODE (dst) == MEM) | |
9272 | { | |
9273 | dst = XEXP (dst, 0); | |
52fdbf26 | 9274 | if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC |
19ca869b | 9275 | || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC) |
61f5625b | 9276 | reg_set_luid[REGNO (XEXP (dst, 0))] = 0; |
19ca869b | 9277 | return; |
174fa2c4 | 9278 | } |
5adf6da0 R |
9279 | if (GET_CODE (dst) != REG) |
9280 | return; | |
9281 | ||
9282 | regno += REGNO (dst); | |
9283 | ||
f93233bb JL |
9284 | if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET |
9285 | && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT | |
9286 | && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT | |
9287 | && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) | |
5adf6da0 R |
9288 | { |
9289 | rtx src = SET_SRC (set); | |
61f5625b AO |
9290 | rtx base_reg; |
9291 | HOST_WIDE_INT offset; | |
9292 | int base_regno; | |
9293 | /* This may be different from mode, if SET_DEST (set) is a | |
9294 | SUBREG. */ | |
9295 | enum machine_mode dst_mode = GET_MODE (dst); | |
5adf6da0 | 9296 | |
5adf6da0 R |
9297 | switch (GET_CODE (src)) |
9298 | { | |
9299 | case PLUS: | |
61f5625b AO |
9300 | if (GET_CODE (XEXP (src, 0)) == REG) |
9301 | { | |
9302 | base_reg = XEXP (src, 0); | |
9303 | ||
9304 | if (GET_CODE (XEXP (src, 1)) == CONST_INT) | |
9305 | offset = INTVAL (XEXP (src, 1)); | |
9306 | else if (GET_CODE (XEXP (src, 1)) == REG | |
9307 | && (reg_set_luid[REGNO (XEXP (src, 1))] | |
9308 | > move2add_last_label_luid) | |
9309 | && (MODES_OK_FOR_MOVE2ADD | |
9310 | (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))) | |
9311 | { | |
9312 | if (reg_base_reg[REGNO (XEXP (src, 1))] < 0) | |
9313 | offset = reg_offset[REGNO (XEXP (src, 1))]; | |
9314 | /* Maybe the first register is known to be a | |
9315 | constant. */ | |
9316 | else if (reg_set_luid[REGNO (base_reg)] | |
9317 | > move2add_last_label_luid | |
9318 | && (MODES_OK_FOR_MOVE2ADD | |
9319 | (dst_mode, reg_mode[REGNO (XEXP (src, 1))])) | |
9320 | && reg_base_reg[REGNO (base_reg)] < 0) | |
9321 | { | |
9322 | offset = reg_offset[REGNO (base_reg)]; | |
9323 | base_reg = XEXP (src, 1); | |
9324 | } | |
9325 | else | |
9326 | goto invalidate; | |
9327 | } | |
9328 | else | |
9329 | goto invalidate; | |
770ae6cc | 9330 | |
61f5625b AO |
9331 | break; |
9332 | } | |
770ae6cc | 9333 | |
61f5625b | 9334 | goto invalidate; |
5adf6da0 R |
9335 | |
9336 | case REG: | |
61f5625b AO |
9337 | base_reg = src; |
9338 | offset = 0; | |
5adf6da0 R |
9339 | break; |
9340 | ||
61f5625b AO |
9341 | case CONST_INT: |
9342 | /* Start tracking the register as a constant. */ | |
5adf6da0 | 9343 | reg_base_reg[regno] = -1; |
61f5625b AO |
9344 | reg_offset[regno] = INTVAL (SET_SRC (set)); |
9345 | /* We assign the same luid to all registers set to constants. */ | |
9346 | reg_set_luid[regno] = move2add_last_label_luid + 1; | |
9347 | reg_mode[regno] = mode; | |
9348 | return; | |
9349 | ||
9350 | default: | |
9351 | invalidate: | |
9352 | /* Invalidate the contents of the register. */ | |
9353 | reg_set_luid[regno] = 0; | |
9354 | return; | |
5adf6da0 | 9355 | } |
61f5625b AO |
9356 | |
9357 | base_regno = REGNO (base_reg); | |
9358 | /* If information about the base register is not valid, set it | |
9359 | up as a new base register, pretending its value is known | |
9360 | starting from the current insn. */ | |
9361 | if (reg_set_luid[base_regno] <= move2add_last_label_luid) | |
9362 | { | |
9363 | reg_base_reg[base_regno] = base_regno; | |
9364 | reg_offset[base_regno] = 0; | |
9365 | reg_set_luid[base_regno] = move2add_luid; | |
9366 | reg_mode[base_regno] = mode; | |
9367 | } | |
9368 | else if (! MODES_OK_FOR_MOVE2ADD (dst_mode, | |
9369 | reg_mode[base_regno])) | |
9370 | goto invalidate; | |
9371 | ||
9372 | reg_mode[regno] = mode; | |
9373 | ||
9374 | /* Copy base information from our base register. */ | |
9375 | reg_set_luid[regno] = reg_set_luid[base_regno]; | |
9376 | reg_base_reg[regno] = reg_base_reg[base_regno]; | |
9377 | ||
9378 | /* Compute the sum of the offsets or constants. */ | |
9379 | reg_offset[regno] = sext_for_mode (dst_mode, | |
9380 | offset | |
9381 | + reg_offset[base_regno]); | |
5adf6da0 R |
9382 | } |
9383 | else | |
9384 | { | |
770ae6cc RK |
9385 | unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode); |
9386 | ||
9387 | for (i = regno; i < endregno; i++) | |
61f5625b AO |
9388 | /* Reset the information about this register. */ |
9389 | reg_set_luid[i] = 0; | |
5adf6da0 R |
9390 | } |
9391 | } | |
2dfa9a87 MH |
9392 | |
9393 | #ifdef AUTO_INC_DEC | |
9394 | static void | |
9395 | add_auto_inc_notes (insn, x) | |
9396 | rtx insn; | |
9397 | rtx x; | |
9398 | { | |
9399 | enum rtx_code code = GET_CODE (x); | |
6f7d635c | 9400 | const char *fmt; |
2dfa9a87 MH |
9401 | int i, j; |
9402 | ||
9403 | if (code == MEM && auto_inc_p (XEXP (x, 0))) | |
9404 | { | |
9405 | REG_NOTES (insn) | |
9406 | = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn)); | |
9407 | return; | |
9408 | } | |
9409 | ||
9410 | /* Scan all the operand sub-expressions. */ | |
9411 | fmt = GET_RTX_FORMAT (code); | |
9412 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
9413 | { | |
9414 | if (fmt[i] == 'e') | |
9415 | add_auto_inc_notes (insn, XEXP (x, i)); | |
9416 | else if (fmt[i] == 'E') | |
9417 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
9418 | add_auto_inc_notes (insn, XVECEXP (x, i, j)); | |
9419 | } | |
9420 | } | |
9421 | #endif | |
94bd63e5 AH |
9422 | |
9423 | /* Copy EH notes from an insn to its reloads. */ | |
9424 | static void | |
9425 | copy_eh_notes (insn, x) | |
9426 | rtx insn; | |
9427 | rtx x; | |
9428 | { | |
9429 | rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
9430 | if (eh_note) | |
9431 | { | |
9432 | for (; x != 0; x = NEXT_INSN (x)) | |
9433 | { | |
9434 | if (may_trap_p (PATTERN (x))) | |
9435 | REG_NOTES (x) | |
9436 | = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0), | |
9437 | REG_NOTES (x)); | |
9438 | } | |
9439 | } | |
9440 | } | |
9441 | ||
f1330226 JH |
9442 | /* This is used by reload pass, that does emit some instructions after |
9443 | abnormal calls moving basic block end, but in fact it wants to emit | |
9444 | them on the edge. Looks for abnormal call edges, find backward the | |
9445 | proper call and fix the damage. | |
9446 | ||
9447 | Similar handle instructions throwing exceptions internally. */ | |
9448 | static void | |
9449 | fixup_abnormal_edges () | |
9450 | { | |
9451 | int i; | |
9452 | bool inserted = false; | |
9453 | ||
9454 | for (i = 0; i < n_basic_blocks; i++) | |
9455 | { | |
9456 | basic_block bb = BASIC_BLOCK (i); | |
9457 | edge e; | |
9458 | ||
9459 | /* Look for cases we are interested in - an calls or instructions causing | |
9460 | exceptions. */ | |
9461 | for (e = bb->succ; e; e = e->succ_next) | |
9462 | { | |
9463 | if (e->flags & EDGE_ABNORMAL_CALL) | |
9464 | break; | |
9465 | if ((e->flags & (EDGE_ABNORMAL | EDGE_EH)) | |
9466 | == (EDGE_ABNORMAL | EDGE_EH)) | |
9467 | break; | |
9468 | } | |
9469 | if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end)) | |
9470 | { | |
0c4992b0 | 9471 | rtx insn = bb->end, stop = NEXT_INSN (bb->end); |
f1330226 JH |
9472 | rtx next; |
9473 | for (e = bb->succ; e; e = e->succ_next) | |
9474 | if (e->flags & EDGE_FALLTHRU) | |
9475 | break; | |
39f95a2c JH |
9476 | /* Get past the new insns generated. Allow notes, as the insns may |
9477 | be already deleted. */ | |
9478 | while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE) | |
9479 | && !can_throw_internal (insn) | |
9480 | && insn != bb->head) | |
f1330226 JH |
9481 | insn = PREV_INSN (insn); |
9482 | if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn)) | |
9483 | abort (); | |
9484 | bb->end = insn; | |
9485 | inserted = true; | |
9486 | insn = NEXT_INSN (insn); | |
0c4992b0 | 9487 | while (insn && insn != stop) |
f1330226 JH |
9488 | { |
9489 | next = NEXT_INSN (insn); | |
0c4992b0 JH |
9490 | if (INSN_P (insn)) |
9491 | { | |
9492 | insert_insn_on_edge (PATTERN (insn), e); | |
53c17031 | 9493 | delete_insn (insn); |
0c4992b0 | 9494 | } |
f1330226 JH |
9495 | insn = next; |
9496 | } | |
9497 | } | |
9498 | } | |
9499 | if (inserted) | |
9500 | commit_edge_insertions (); | |
9501 | } |