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32131a9c | 1 | /* Reload pseudo regs into hard regs for insns that require hard regs. |
af841dbd JL |
2 | Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
3 | 1999, 2000 Free Software Foundation, Inc. | |
32131a9c RK |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
e99215a3 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
32131a9c RK |
21 | |
22 | ||
23 | #include "config.h" | |
670ee920 | 24 | #include "system.h" |
cab634f2 KG |
25 | |
26 | #include "machmode.h" | |
27 | #include "hard-reg-set.h" | |
32131a9c | 28 | #include "rtl.h" |
6baf1cc8 | 29 | #include "tm_p.h" |
32131a9c RK |
30 | #include "obstack.h" |
31 | #include "insn-config.h" | |
32 | #include "insn-flags.h" | |
33 | #include "insn-codes.h" | |
34 | #include "flags.h" | |
49ad7cfa | 35 | #include "function.h" |
32131a9c RK |
36 | #include "expr.h" |
37 | #include "regs.h" | |
cad6f7d0 | 38 | #include "basic-block.h" |
32131a9c RK |
39 | #include "reload.h" |
40 | #include "recog.h" | |
32131a9c | 41 | #include "output.h" |
eab5c70a | 42 | #include "cselib.h" |
a9c366bf | 43 | #include "real.h" |
10f0ad3d | 44 | #include "toplev.h" |
32131a9c | 45 | |
65954bd8 JL |
46 | #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY |
47 | #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY | |
48 | #endif | |
49 | ||
32131a9c RK |
50 | /* This file contains the reload pass of the compiler, which is |
51 | run after register allocation has been done. It checks that | |
52 | each insn is valid (operands required to be in registers really | |
53 | are in registers of the proper class) and fixes up invalid ones | |
54 | by copying values temporarily into registers for the insns | |
55 | that need them. | |
56 | ||
57 | The results of register allocation are described by the vector | |
58 | reg_renumber; the insns still contain pseudo regs, but reg_renumber | |
59 | can be used to find which hard reg, if any, a pseudo reg is in. | |
60 | ||
61 | The technique we always use is to free up a few hard regs that are | |
62 | called ``reload regs'', and for each place where a pseudo reg | |
63 | must be in a hard reg, copy it temporarily into one of the reload regs. | |
64 | ||
03acd8f8 BS |
65 | Reload regs are allocated locally for every instruction that needs |
66 | reloads. When there are pseudos which are allocated to a register that | |
67 | has been chosen as a reload reg, such pseudos must be ``spilled''. | |
68 | This means that they go to other hard regs, or to stack slots if no other | |
32131a9c RK |
69 | available hard regs can be found. Spilling can invalidate more |
70 | insns, requiring additional need for reloads, so we must keep checking | |
71 | until the process stabilizes. | |
72 | ||
73 | For machines with different classes of registers, we must keep track | |
74 | of the register class needed for each reload, and make sure that | |
75 | we allocate enough reload registers of each class. | |
76 | ||
77 | The file reload.c contains the code that checks one insn for | |
78 | validity and reports the reloads that it needs. This file | |
79 | is in charge of scanning the entire rtl code, accumulating the | |
80 | reload needs, spilling, assigning reload registers to use for | |
81 | fixing up each insn, and generating the new insns to copy values | |
82 | into the reload registers. */ | |
546b63fb RK |
83 | |
84 | ||
85 | #ifndef REGISTER_MOVE_COST | |
86 | #define REGISTER_MOVE_COST(x, y) 2 | |
87 | #endif | |
32131a9c RK |
88 | \f |
89 | /* During reload_as_needed, element N contains a REG rtx for the hard reg | |
0f41302f | 90 | into which reg N has been reloaded (perhaps for a previous insn). */ |
32131a9c RK |
91 | static rtx *reg_last_reload_reg; |
92 | ||
93 | /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn | |
94 | for an output reload that stores into reg N. */ | |
95 | static char *reg_has_output_reload; | |
96 | ||
97 | /* Indicates which hard regs are reload-registers for an output reload | |
98 | in the current insn. */ | |
99 | static HARD_REG_SET reg_is_output_reload; | |
100 | ||
101 | /* Element N is the constant value to which pseudo reg N is equivalent, | |
102 | or zero if pseudo reg N is not equivalent to a constant. | |
103 | find_reloads looks at this in order to replace pseudo reg N | |
104 | with the constant it stands for. */ | |
105 | rtx *reg_equiv_constant; | |
106 | ||
107 | /* Element N is a memory location to which pseudo reg N is equivalent, | |
108 | prior to any register elimination (such as frame pointer to stack | |
109 | pointer). Depending on whether or not it is a valid address, this value | |
110 | is transferred to either reg_equiv_address or reg_equiv_mem. */ | |
4803a34a | 111 | rtx *reg_equiv_memory_loc; |
32131a9c RK |
112 | |
113 | /* Element N is the address of stack slot to which pseudo reg N is equivalent. | |
114 | This is used when the address is not valid as a memory address | |
115 | (because its displacement is too big for the machine.) */ | |
116 | rtx *reg_equiv_address; | |
117 | ||
118 | /* Element N is the memory slot to which pseudo reg N is equivalent, | |
119 | or zero if pseudo reg N is not equivalent to a memory slot. */ | |
120 | rtx *reg_equiv_mem; | |
121 | ||
122 | /* Widest width in which each pseudo reg is referred to (via subreg). */ | |
770ae6cc | 123 | static unsigned int *reg_max_ref_width; |
32131a9c | 124 | |
135eb61c | 125 | /* Element N is the list of insns that initialized reg N from its equivalent |
32131a9c RK |
126 | constant or memory slot. */ |
127 | static rtx *reg_equiv_init; | |
128 | ||
03acd8f8 BS |
129 | /* Vector to remember old contents of reg_renumber before spilling. */ |
130 | static short *reg_old_renumber; | |
131 | ||
e6e52be0 | 132 | /* During reload_as_needed, element N contains the last pseudo regno reloaded |
03acd8f8 | 133 | into hard register N. If that pseudo reg occupied more than one register, |
32131a9c RK |
134 | reg_reloaded_contents points to that pseudo for each spill register in |
135 | use; all of these must remain set for an inheritance to occur. */ | |
136 | static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; | |
137 | ||
138 | /* During reload_as_needed, element N contains the insn for which | |
e6e52be0 R |
139 | hard register N was last used. Its contents are significant only |
140 | when reg_reloaded_valid is set for this register. */ | |
32131a9c RK |
141 | static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; |
142 | ||
e6e52be0 R |
143 | /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */ |
144 | static HARD_REG_SET reg_reloaded_valid; | |
145 | /* Indicate if the register was dead at the end of the reload. | |
146 | This is only valid if reg_reloaded_contents is set and valid. */ | |
147 | static HARD_REG_SET reg_reloaded_dead; | |
148 | ||
32131a9c RK |
149 | /* Number of spill-regs so far; number of valid elements of spill_regs. */ |
150 | static int n_spills; | |
151 | ||
152 | /* In parallel with spill_regs, contains REG rtx's for those regs. | |
153 | Holds the last rtx used for any given reg, or 0 if it has never | |
154 | been used for spilling yet. This rtx is reused, provided it has | |
155 | the proper mode. */ | |
156 | static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
157 | ||
158 | /* In parallel with spill_regs, contains nonzero for a spill reg | |
159 | that was stored after the last time it was used. | |
160 | The precise value is the insn generated to do the store. */ | |
161 | static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
162 | ||
cb2afeb3 R |
163 | /* This is the register that was stored with spill_reg_store. This is a |
164 | copy of reload_out / reload_out_reg when the value was stored; if | |
165 | reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */ | |
166 | static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; | |
167 | ||
32131a9c RK |
168 | /* This table is the inverse mapping of spill_regs: |
169 | indexed by hard reg number, | |
170 | it contains the position of that reg in spill_regs, | |
05d10675 | 171 | or -1 for something that is not in spill_regs. |
13c8e8e3 JL |
172 | |
173 | ?!? This is no longer accurate. */ | |
32131a9c RK |
174 | static short spill_reg_order[FIRST_PSEUDO_REGISTER]; |
175 | ||
03acd8f8 BS |
176 | /* This reg set indicates registers that can't be used as spill registers for |
177 | the currently processed insn. These are the hard registers which are live | |
178 | during the insn, but not allocated to pseudos, as well as fixed | |
179 | registers. */ | |
32131a9c RK |
180 | static HARD_REG_SET bad_spill_regs; |
181 | ||
03acd8f8 BS |
182 | /* These are the hard registers that can't be used as spill register for any |
183 | insn. This includes registers used for user variables and registers that | |
184 | we can't eliminate. A register that appears in this set also can't be used | |
185 | to retry register allocation. */ | |
186 | static HARD_REG_SET bad_spill_regs_global; | |
187 | ||
32131a9c | 188 | /* Describes order of use of registers for reloading |
03acd8f8 BS |
189 | of spilled pseudo-registers. `n_spills' is the number of |
190 | elements that are actually valid; new ones are added at the end. | |
191 | ||
192 | Both spill_regs and spill_reg_order are used on two occasions: | |
193 | once during find_reload_regs, where they keep track of the spill registers | |
194 | for a single insn, but also during reload_as_needed where they show all | |
195 | the registers ever used by reload. For the latter case, the information | |
196 | is calculated during finish_spills. */ | |
32131a9c RK |
197 | static short spill_regs[FIRST_PSEUDO_REGISTER]; |
198 | ||
03acd8f8 BS |
199 | /* This vector of reg sets indicates, for each pseudo, which hard registers |
200 | may not be used for retrying global allocation because the register was | |
201 | formerly spilled from one of them. If we allowed reallocating a pseudo to | |
202 | a register that it was already allocated to, reload might not | |
203 | terminate. */ | |
204 | static HARD_REG_SET *pseudo_previous_regs; | |
205 | ||
206 | /* This vector of reg sets indicates, for each pseudo, which hard | |
207 | registers may not be used for retrying global allocation because they | |
208 | are used as spill registers during one of the insns in which the | |
209 | pseudo is live. */ | |
210 | static HARD_REG_SET *pseudo_forbidden_regs; | |
211 | ||
212 | /* All hard regs that have been used as spill registers for any insn are | |
213 | marked in this set. */ | |
214 | static HARD_REG_SET used_spill_regs; | |
8b4f9969 | 215 | |
4079cd63 JW |
216 | /* Index of last register assigned as a spill register. We allocate in |
217 | a round-robin fashion. */ | |
4079cd63 JW |
218 | static int last_spill_reg; |
219 | ||
32131a9c RK |
220 | /* Nonzero if indirect addressing is supported on the machine; this means |
221 | that spilling (REG n) does not require reloading it into a register in | |
222 | order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The | |
223 | value indicates the level of indirect addressing supported, e.g., two | |
224 | means that (MEM (MEM (REG n))) is also valid if (REG n) does not get | |
225 | a hard register. */ | |
32131a9c RK |
226 | static char spill_indirect_levels; |
227 | ||
228 | /* Nonzero if indirect addressing is supported when the innermost MEM is | |
229 | of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to | |
230 | which these are valid is the same as spill_indirect_levels, above. */ | |
32131a9c RK |
231 | char indirect_symref_ok; |
232 | ||
233 | /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ | |
32131a9c RK |
234 | char double_reg_address_ok; |
235 | ||
236 | /* Record the stack slot for each spilled hard register. */ | |
32131a9c RK |
237 | static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; |
238 | ||
239 | /* Width allocated so far for that stack slot. */ | |
770ae6cc | 240 | static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; |
32131a9c | 241 | |
7609e720 | 242 | /* Record which pseudos needed to be spilled. */ |
f5d8c9f4 BS |
243 | static regset_head spilled_pseudos; |
244 | ||
245 | /* Used for communication between order_regs_for_reload and count_pseudo. | |
246 | Used to avoid counting one pseudo twice. */ | |
247 | static regset_head pseudos_counted; | |
7609e720 | 248 | |
32131a9c RK |
249 | /* First uid used by insns created by reload in this function. |
250 | Used in find_equiv_reg. */ | |
251 | int reload_first_uid; | |
252 | ||
253 | /* Flag set by local-alloc or global-alloc if anything is live in | |
254 | a call-clobbered reg across calls. */ | |
32131a9c RK |
255 | int caller_save_needed; |
256 | ||
257 | /* Set to 1 while reload_as_needed is operating. | |
258 | Required by some machines to handle any generated moves differently. */ | |
32131a9c RK |
259 | int reload_in_progress = 0; |
260 | ||
261 | /* These arrays record the insn_code of insns that may be needed to | |
262 | perform input and output reloads of special objects. They provide a | |
263 | place to pass a scratch register. */ | |
32131a9c RK |
264 | enum insn_code reload_in_optab[NUM_MACHINE_MODES]; |
265 | enum insn_code reload_out_optab[NUM_MACHINE_MODES]; | |
266 | ||
d45cf215 | 267 | /* This obstack is used for allocation of rtl during register elimination. |
32131a9c RK |
268 | The allocated storage can be freed once find_reloads has processed the |
269 | insn. */ | |
32131a9c | 270 | struct obstack reload_obstack; |
cad6f7d0 BS |
271 | |
272 | /* Points to the beginning of the reload_obstack. All insn_chain structures | |
273 | are allocated first. */ | |
274 | char *reload_startobj; | |
275 | ||
276 | /* The point after all insn_chain structures. Used to quickly deallocate | |
f5d8c9f4 | 277 | memory allocated in copy_reloads during calculate_needs_all_insns. */ |
32131a9c RK |
278 | char *reload_firstobj; |
279 | ||
f5d8c9f4 BS |
280 | /* This points before all local rtl generated by register elimination. |
281 | Used to quickly free all memory after processing one insn. */ | |
282 | static char *reload_insn_firstobj; | |
283 | ||
32131a9c RK |
284 | #define obstack_chunk_alloc xmalloc |
285 | #define obstack_chunk_free free | |
286 | ||
cad6f7d0 BS |
287 | /* List of insn_chain instructions, one for every insn that reload needs to |
288 | examine. */ | |
289 | struct insn_chain *reload_insn_chain; | |
7609e720 | 290 | |
dfb7c80f JL |
291 | #ifdef TREE_CODE |
292 | extern tree current_function_decl; | |
293 | #else | |
122a860e | 294 | extern union tree_node *current_function_decl; |
dfb7c80f JL |
295 | #endif |
296 | ||
03acd8f8 | 297 | /* List of all insns needing reloads. */ |
7609e720 | 298 | static struct insn_chain *insns_need_reload; |
32131a9c RK |
299 | \f |
300 | /* This structure is used to record information about register eliminations. | |
301 | Each array entry describes one possible way of eliminating a register | |
302 | in favor of another. If there is more than one way of eliminating a | |
303 | particular register, the most preferred should be specified first. */ | |
304 | ||
590cf94d | 305 | struct elim_table |
32131a9c | 306 | { |
0f41302f MS |
307 | int from; /* Register number to be eliminated. */ |
308 | int to; /* Register number used as replacement. */ | |
309 | int initial_offset; /* Initial difference between values. */ | |
310 | int can_eliminate; /* Non-zero if this elimination can be done. */ | |
32131a9c | 311 | int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over |
0f41302f MS |
312 | insns made by reload. */ |
313 | int offset; /* Current offset between the two regs. */ | |
0f41302f MS |
314 | int previous_offset; /* Offset at end of previous insn. */ |
315 | int ref_outside_mem; /* "to" has been referenced outside a MEM. */ | |
32131a9c RK |
316 | rtx from_rtx; /* REG rtx for the register to be eliminated. |
317 | We cannot simply compare the number since | |
318 | we might then spuriously replace a hard | |
319 | register corresponding to a pseudo | |
0f41302f MS |
320 | assigned to the reg to be eliminated. */ |
321 | rtx to_rtx; /* REG rtx for the replacement. */ | |
590cf94d KG |
322 | }; |
323 | ||
324 | static struct elim_table * reg_eliminate = 0; | |
325 | ||
326 | /* This is an intermediate structure to initialize the table. It has | |
327 | exactly the members provided by ELIMINABLE_REGS. */ | |
328 | static struct elim_table_1 | |
329 | { | |
330 | int from; | |
331 | int to; | |
332 | } reg_eliminate_1[] = | |
32131a9c RK |
333 | |
334 | /* If a set of eliminable registers was specified, define the table from it. | |
335 | Otherwise, default to the normal case of the frame pointer being | |
336 | replaced by the stack pointer. */ | |
337 | ||
338 | #ifdef ELIMINABLE_REGS | |
339 | ELIMINABLE_REGS; | |
340 | #else | |
341 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; | |
342 | #endif | |
343 | ||
590cf94d | 344 | #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0]) |
32131a9c RK |
345 | |
346 | /* Record the number of pending eliminations that have an offset not equal | |
347 | to their initial offset. If non-zero, we use a new copy of each | |
348 | replacement result in any insns encountered. */ | |
cb2afeb3 | 349 | int num_not_at_initial_offset; |
32131a9c RK |
350 | |
351 | /* Count the number of registers that we may be able to eliminate. */ | |
352 | static int num_eliminable; | |
2b49ee39 R |
353 | /* And the number of registers that are equivalent to a constant that |
354 | can be eliminated to frame_pointer / arg_pointer + constant. */ | |
355 | static int num_eliminable_invariants; | |
32131a9c RK |
356 | |
357 | /* For each label, we record the offset of each elimination. If we reach | |
358 | a label by more than one path and an offset differs, we cannot do the | |
359 | elimination. This information is indexed by the number of the label. | |
360 | The first table is an array of flags that records whether we have yet | |
361 | encountered a label and the second table is an array of arrays, one | |
362 | entry in the latter array for each elimination. */ | |
363 | ||
364 | static char *offsets_known_at; | |
365 | static int (*offsets_at)[NUM_ELIMINABLE_REGS]; | |
366 | ||
367 | /* Number of labels in the current function. */ | |
368 | ||
369 | static int num_labels; | |
370 | \f | |
cdadb1dd KG |
371 | static void maybe_fix_stack_asms PARAMS ((void)); |
372 | static void copy_reloads PARAMS ((struct insn_chain *)); | |
373 | static void calculate_needs_all_insns PARAMS ((int)); | |
374 | static int find_reg PARAMS ((struct insn_chain *, int, | |
03acd8f8 | 375 | FILE *)); |
cdadb1dd KG |
376 | static void find_reload_regs PARAMS ((struct insn_chain *, FILE *)); |
377 | static void select_reload_regs PARAMS ((FILE *)); | |
378 | static void delete_caller_save_insns PARAMS ((void)); | |
379 | ||
380 | static void spill_failure PARAMS ((rtx, enum reg_class)); | |
381 | static void count_spilled_pseudo PARAMS ((int, int, int)); | |
382 | static void delete_dead_insn PARAMS ((rtx)); | |
383 | static void alter_reg PARAMS ((int, int)); | |
384 | static void set_label_offsets PARAMS ((rtx, rtx, int)); | |
385 | static void check_eliminable_occurrences PARAMS ((rtx)); | |
386 | static void elimination_effects PARAMS ((rtx, enum machine_mode)); | |
387 | static int eliminate_regs_in_insn PARAMS ((rtx, int)); | |
388 | static void update_eliminable_offsets PARAMS ((void)); | |
389 | static void mark_not_eliminable PARAMS ((rtx, rtx, void *)); | |
390 | static void set_initial_elim_offsets PARAMS ((void)); | |
391 | static void verify_initial_elim_offsets PARAMS ((void)); | |
392 | static void set_initial_label_offsets PARAMS ((void)); | |
393 | static void set_offsets_for_label PARAMS ((rtx)); | |
394 | static void init_elim_table PARAMS ((void)); | |
395 | static void update_eliminables PARAMS ((HARD_REG_SET *)); | |
770ae6cc | 396 | static void spill_hard_reg PARAMS ((unsigned int, FILE *, int)); |
cdadb1dd KG |
397 | static int finish_spills PARAMS ((int, FILE *)); |
398 | static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *)); | |
399 | static void scan_paradoxical_subregs PARAMS ((rtx)); | |
400 | static void count_pseudo PARAMS ((int)); | |
401 | static void order_regs_for_reload PARAMS ((struct insn_chain *)); | |
402 | static void reload_as_needed PARAMS ((int)); | |
403 | static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *)); | |
404 | static int reload_reg_class_lower PARAMS ((const PTR, const PTR)); | |
770ae6cc RK |
405 | static void mark_reload_reg_in_use PARAMS ((unsigned int, int, |
406 | enum reload_type, | |
407 | enum machine_mode)); | |
408 | static void clear_reload_reg_in_use PARAMS ((unsigned int, int, | |
409 | enum reload_type, | |
410 | enum machine_mode)); | |
411 | static int reload_reg_free_p PARAMS ((unsigned int, int, | |
412 | enum reload_type)); | |
cdadb1dd | 413 | static int reload_reg_free_for_value_p PARAMS ((int, int, enum reload_type, |
770ae6cc RK |
414 | rtx, rtx, int, int)); |
415 | static int reload_reg_reaches_end_p PARAMS ((unsigned int, int, | |
416 | enum reload_type)); | |
417 | static int allocate_reload_reg PARAMS ((struct insn_chain *, int, | |
418 | int)); | |
cdadb1dd KG |
419 | static void failed_reload PARAMS ((rtx, int)); |
420 | static int set_reload_reg PARAMS ((int, int)); | |
421 | static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *)); | |
422 | static void choose_reload_regs PARAMS ((struct insn_chain *)); | |
423 | static void merge_assigned_reloads PARAMS ((rtx)); | |
424 | static void emit_input_reload_insns PARAMS ((struct insn_chain *, | |
770ae6cc | 425 | struct reload *, rtx, int)); |
cdadb1dd | 426 | static void emit_output_reload_insns PARAMS ((struct insn_chain *, |
770ae6cc | 427 | struct reload *, int)); |
cdadb1dd | 428 | static void do_input_reload PARAMS ((struct insn_chain *, |
770ae6cc | 429 | struct reload *, int)); |
cdadb1dd | 430 | static void do_output_reload PARAMS ((struct insn_chain *, |
770ae6cc | 431 | struct reload *, int)); |
cdadb1dd KG |
432 | static void emit_reload_insns PARAMS ((struct insn_chain *)); |
433 | static void delete_output_reload PARAMS ((rtx, int, int)); | |
434 | static void delete_address_reloads PARAMS ((rtx, rtx)); | |
435 | static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx)); | |
436 | static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int)); | |
437 | static int constraint_accepts_reg_p PARAMS ((const char *, rtx)); | |
438 | static void reload_cse_regs_1 PARAMS ((rtx)); | |
eab5c70a | 439 | static int reload_cse_noop_set_p PARAMS ((rtx)); |
cdadb1dd KG |
440 | static int reload_cse_simplify_set PARAMS ((rtx, rtx)); |
441 | static int reload_cse_simplify_operands PARAMS ((rtx)); | |
770ae6cc RK |
442 | static void reload_combine PARAMS ((void)); |
443 | static void reload_combine_note_use PARAMS ((rtx *, rtx)); | |
444 | static void reload_combine_note_store PARAMS ((rtx, rtx, void *)); | |
445 | static void reload_cse_move2add PARAMS ((rtx)); | |
446 | static void move2add_note_store PARAMS ((rtx, rtx, void *)); | |
2dfa9a87 | 447 | #ifdef AUTO_INC_DEC |
770ae6cc | 448 | static void add_auto_inc_notes PARAMS ((rtx, rtx)); |
2dfa9a87 | 449 | #endif |
cdadb1dd | 450 | static rtx gen_mode_int PARAMS ((enum machine_mode, |
770ae6cc | 451 | HOST_WIDE_INT)); |
cdadb1dd KG |
452 | static void failed_reload PARAMS ((rtx, int)); |
453 | static int set_reload_reg PARAMS ((int, int)); | |
e77d72cb KG |
454 | static void reload_cse_delete_noop_set PARAMS ((rtx, rtx)); |
455 | static void reload_cse_simplify PARAMS ((rtx)); | |
cdadb1dd | 456 | extern void dump_needs PARAMS ((struct insn_chain *, FILE *)); |
32131a9c | 457 | \f |
546b63fb RK |
458 | /* Initialize the reload pass once per compilation. */ |
459 | ||
32131a9c RK |
460 | void |
461 | init_reload () | |
462 | { | |
463 | register int i; | |
464 | ||
465 | /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. | |
466 | Set spill_indirect_levels to the number of levels such addressing is | |
467 | permitted, zero if it is not permitted at all. */ | |
468 | ||
469 | register rtx tem | |
38a448ca RH |
470 | = gen_rtx_MEM (Pmode, |
471 | gen_rtx_PLUS (Pmode, | |
c5c76735 JL |
472 | gen_rtx_REG (Pmode, |
473 | LAST_VIRTUAL_REGISTER + 1), | |
38a448ca | 474 | GEN_INT (4))); |
32131a9c RK |
475 | spill_indirect_levels = 0; |
476 | ||
477 | while (memory_address_p (QImode, tem)) | |
478 | { | |
479 | spill_indirect_levels++; | |
38a448ca | 480 | tem = gen_rtx_MEM (Pmode, tem); |
32131a9c RK |
481 | } |
482 | ||
483 | /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ | |
484 | ||
38a448ca | 485 | tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo")); |
32131a9c RK |
486 | indirect_symref_ok = memory_address_p (QImode, tem); |
487 | ||
488 | /* See if reg+reg is a valid (and offsettable) address. */ | |
489 | ||
65701fd2 | 490 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
57caa638 | 491 | { |
38a448ca RH |
492 | tem = gen_rtx_PLUS (Pmode, |
493 | gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), | |
494 | gen_rtx_REG (Pmode, i)); | |
c5c76735 | 495 | |
57caa638 RS |
496 | /* This way, we make sure that reg+reg is an offsettable address. */ |
497 | tem = plus_constant (tem, 4); | |
498 | ||
499 | if (memory_address_p (QImode, tem)) | |
500 | { | |
501 | double_reg_address_ok = 1; | |
502 | break; | |
503 | } | |
504 | } | |
32131a9c | 505 | |
0f41302f | 506 | /* Initialize obstack for our rtl allocation. */ |
32131a9c | 507 | gcc_obstack_init (&reload_obstack); |
cad6f7d0 | 508 | reload_startobj = (char *) obstack_alloc (&reload_obstack, 0); |
f5d8c9f4 BS |
509 | |
510 | INIT_REG_SET (&spilled_pseudos); | |
511 | INIT_REG_SET (&pseudos_counted); | |
32131a9c RK |
512 | } |
513 | ||
cad6f7d0 BS |
514 | /* List of insn chains that are currently unused. */ |
515 | static struct insn_chain *unused_insn_chains = 0; | |
516 | ||
517 | /* Allocate an empty insn_chain structure. */ | |
518 | struct insn_chain * | |
519 | new_insn_chain () | |
520 | { | |
521 | struct insn_chain *c; | |
522 | ||
523 | if (unused_insn_chains == 0) | |
524 | { | |
8db99db2 KG |
525 | c = (struct insn_chain *) |
526 | obstack_alloc (&reload_obstack, sizeof (struct insn_chain)); | |
239a0f5b BS |
527 | INIT_REG_SET (&c->live_throughout); |
528 | INIT_REG_SET (&c->dead_or_set); | |
cad6f7d0 BS |
529 | } |
530 | else | |
531 | { | |
532 | c = unused_insn_chains; | |
533 | unused_insn_chains = c->next; | |
534 | } | |
535 | c->is_caller_save_insn = 0; | |
03acd8f8 | 536 | c->need_operand_change = 0; |
cad6f7d0 BS |
537 | c->need_reload = 0; |
538 | c->need_elim = 0; | |
539 | return c; | |
540 | } | |
541 | ||
7609e720 BS |
542 | /* Small utility function to set all regs in hard reg set TO which are |
543 | allocated to pseudos in regset FROM. */ | |
770ae6cc | 544 | |
7609e720 BS |
545 | void |
546 | compute_use_by_pseudos (to, from) | |
547 | HARD_REG_SET *to; | |
548 | regset from; | |
549 | { | |
770ae6cc RK |
550 | unsigned int regno; |
551 | ||
7609e720 BS |
552 | EXECUTE_IF_SET_IN_REG_SET |
553 | (from, FIRST_PSEUDO_REGISTER, regno, | |
554 | { | |
555 | int r = reg_renumber[regno]; | |
556 | int nregs; | |
770ae6cc | 557 | |
7609e720 | 558 | if (r < 0) |
404d95c4 R |
559 | { |
560 | /* reload_combine uses the information from | |
e881bb1b RH |
561 | BASIC_BLOCK->global_live_at_start, which might still |
562 | contain registers that have not actually been allocated | |
563 | since they have an equivalence. */ | |
404d95c4 R |
564 | if (! reload_completed) |
565 | abort (); | |
566 | } | |
567 | else | |
568 | { | |
569 | nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno)); | |
570 | while (nregs-- > 0) | |
571 | SET_HARD_REG_BIT (*to, r + nregs); | |
572 | } | |
7609e720 BS |
573 | }); |
574 | } | |
03acd8f8 | 575 | \f |
1e5bd841 BS |
576 | /* Global variables used by reload and its subroutines. */ |
577 | ||
1e5bd841 BS |
578 | /* Set during calculate_needs if an insn needs register elimination. */ |
579 | static int something_needs_elimination; | |
cb2afeb3 R |
580 | /* Set during calculate_needs if an insn needs an operand changed. */ |
581 | int something_needs_operands_changed; | |
1e5bd841 | 582 | |
1e5bd841 BS |
583 | /* Nonzero means we couldn't get enough spill regs. */ |
584 | static int failure; | |
585 | ||
546b63fb | 586 | /* Main entry point for the reload pass. |
32131a9c RK |
587 | |
588 | FIRST is the first insn of the function being compiled. | |
589 | ||
590 | GLOBAL nonzero means we were called from global_alloc | |
591 | and should attempt to reallocate any pseudoregs that we | |
592 | displace from hard regs we will use for reloads. | |
593 | If GLOBAL is zero, we do not have enough information to do that, | |
594 | so any pseudo reg that is spilled must go to the stack. | |
595 | ||
596 | DUMPFILE is the global-reg debugging dump file stream, or 0. | |
597 | If it is nonzero, messages are written to it to describe | |
598 | which registers are seized as reload regs, which pseudo regs | |
5352b11a | 599 | are spilled from them, and where the pseudo regs are reallocated to. |
32131a9c | 600 | |
5352b11a RS |
601 | Return value is nonzero if reload failed |
602 | and we must not do any more for this function. */ | |
603 | ||
604 | int | |
32131a9c RK |
605 | reload (first, global, dumpfile) |
606 | rtx first; | |
607 | int global; | |
608 | FILE *dumpfile; | |
609 | { | |
03acd8f8 | 610 | register int i; |
32131a9c RK |
611 | register rtx insn; |
612 | register struct elim_table *ep; | |
613 | ||
a68d4b75 BK |
614 | /* The two pointers used to track the true location of the memory used |
615 | for label offsets. */ | |
616 | char *real_known_ptr = NULL_PTR; | |
617 | int (*real_at_ptr)[NUM_ELIMINABLE_REGS]; | |
618 | ||
32131a9c RK |
619 | /* Make sure even insns with volatile mem refs are recognizable. */ |
620 | init_recog (); | |
621 | ||
1e5bd841 BS |
622 | failure = 0; |
623 | ||
cad6f7d0 BS |
624 | reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); |
625 | ||
437a710d BS |
626 | /* Make sure that the last insn in the chain |
627 | is not something that needs reloading. */ | |
628 | emit_note (NULL_PTR, NOTE_INSN_DELETED); | |
629 | ||
32131a9c RK |
630 | /* Enable find_equiv_reg to distinguish insns made by reload. */ |
631 | reload_first_uid = get_max_uid (); | |
632 | ||
0dadecf6 RK |
633 | #ifdef SECONDARY_MEMORY_NEEDED |
634 | /* Initialize the secondary memory table. */ | |
635 | clear_secondary_mem (); | |
636 | #endif | |
637 | ||
32131a9c | 638 | /* We don't have a stack slot for any spill reg yet. */ |
4c9a05bc RK |
639 | bzero ((char *) spill_stack_slot, sizeof spill_stack_slot); |
640 | bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width); | |
32131a9c | 641 | |
a8efe40d RK |
642 | /* Initialize the save area information for caller-save, in case some |
643 | are needed. */ | |
644 | init_save_areas (); | |
a8fdc208 | 645 | |
32131a9c RK |
646 | /* Compute which hard registers are now in use |
647 | as homes for pseudo registers. | |
648 | This is done here rather than (eg) in global_alloc | |
649 | because this point is reached even if not optimizing. */ | |
32131a9c RK |
650 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) |
651 | mark_home_live (i); | |
652 | ||
8dddd002 RK |
653 | /* A function that receives a nonlocal goto must save all call-saved |
654 | registers. */ | |
655 | if (current_function_has_nonlocal_label) | |
656 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
657 | { | |
658 | if (! call_used_regs[i] && ! fixed_regs[i]) | |
659 | regs_ever_live[i] = 1; | |
660 | } | |
661 | ||
32131a9c RK |
662 | /* Find all the pseudo registers that didn't get hard regs |
663 | but do have known equivalent constants or memory slots. | |
664 | These include parameters (known equivalent to parameter slots) | |
665 | and cse'd or loop-moved constant memory addresses. | |
666 | ||
667 | Record constant equivalents in reg_equiv_constant | |
668 | so they will be substituted by find_reloads. | |
669 | Record memory equivalents in reg_mem_equiv so they can | |
670 | be substituted eventually by altering the REG-rtx's. */ | |
671 | ||
ad85216e KG |
672 | reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx)); |
673 | reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
674 | reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
675 | reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
676 | reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx)); | |
f9e158c3 | 677 | reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int)); |
ad85216e | 678 | reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short)); |
47c3ed98 | 679 | bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short)); |
03acd8f8 BS |
680 | pseudo_forbidden_regs |
681 | = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET)); | |
682 | pseudo_previous_regs | |
ad85216e | 683 | = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET)); |
32131a9c | 684 | |
03acd8f8 | 685 | CLEAR_HARD_REG_SET (bad_spill_regs_global); |
56f58d3a | 686 | |
32131a9c | 687 | /* Look for REG_EQUIV notes; record what each pseudo is equivalent to. |
56f58d3a RK |
688 | Also find all paradoxical subregs and find largest such for each pseudo. |
689 | On machines with small register classes, record hard registers that | |
05d10675 | 690 | are used for user variables. These can never be used for spills. |
b453cb0b RK |
691 | Also look for a "constant" NOTE_INSN_SETJMP. This means that all |
692 | caller-saved registers must be marked live. */ | |
32131a9c | 693 | |
2b49ee39 | 694 | num_eliminable_invariants = 0; |
32131a9c RK |
695 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
696 | { | |
697 | rtx set = single_set (insn); | |
698 | ||
b453cb0b RK |
699 | if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn) |
700 | && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP) | |
701 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
702 | if (! call_used_regs[i]) | |
703 | regs_ever_live[i] = 1; | |
704 | ||
32131a9c RK |
705 | if (set != 0 && GET_CODE (SET_DEST (set)) == REG) |
706 | { | |
fb3821f7 | 707 | rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); |
a8efe40d RK |
708 | if (note |
709 | #ifdef LEGITIMATE_PIC_OPERAND_P | |
2b49ee39 R |
710 | && (! function_invariant_p (XEXP (note, 0)) |
711 | || ! flag_pic | |
a8efe40d RK |
712 | || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))) |
713 | #endif | |
714 | ) | |
32131a9c RK |
715 | { |
716 | rtx x = XEXP (note, 0); | |
717 | i = REGNO (SET_DEST (set)); | |
718 | if (i > LAST_VIRTUAL_REGISTER) | |
719 | { | |
720 | if (GET_CODE (x) == MEM) | |
956d6950 JL |
721 | { |
722 | /* If the operand is a PLUS, the MEM may be shared, | |
723 | so make sure we have an unshared copy here. */ | |
724 | if (GET_CODE (XEXP (x, 0)) == PLUS) | |
725 | x = copy_rtx (x); | |
726 | ||
727 | reg_equiv_memory_loc[i] = x; | |
728 | } | |
2b49ee39 | 729 | else if (function_invariant_p (x)) |
32131a9c | 730 | { |
2b49ee39 R |
731 | if (GET_CODE (x) == PLUS) |
732 | { | |
733 | /* This is PLUS of frame pointer and a constant, | |
734 | and might be shared. Unshare it. */ | |
735 | reg_equiv_constant[i] = copy_rtx (x); | |
736 | num_eliminable_invariants++; | |
737 | } | |
738 | else if (x == frame_pointer_rtx | |
739 | || x == arg_pointer_rtx) | |
740 | { | |
741 | reg_equiv_constant[i] = x; | |
742 | num_eliminable_invariants++; | |
743 | } | |
744 | else if (LEGITIMATE_CONSTANT_P (x)) | |
32131a9c RK |
745 | reg_equiv_constant[i] = x; |
746 | else | |
747 | reg_equiv_memory_loc[i] | |
d445b551 | 748 | = force_const_mem (GET_MODE (SET_DEST (set)), x); |
32131a9c RK |
749 | } |
750 | else | |
751 | continue; | |
752 | ||
753 | /* If this register is being made equivalent to a MEM | |
754 | and the MEM is not SET_SRC, the equivalencing insn | |
755 | is one with the MEM as a SET_DEST and it occurs later. | |
756 | So don't mark this insn now. */ | |
757 | if (GET_CODE (x) != MEM | |
758 | || rtx_equal_p (SET_SRC (set), x)) | |
135eb61c R |
759 | reg_equiv_init[i] |
760 | = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]); | |
32131a9c RK |
761 | } |
762 | } | |
763 | } | |
764 | ||
765 | /* If this insn is setting a MEM from a register equivalent to it, | |
766 | this is the equivalencing insn. */ | |
767 | else if (set && GET_CODE (SET_DEST (set)) == MEM | |
768 | && GET_CODE (SET_SRC (set)) == REG | |
769 | && reg_equiv_memory_loc[REGNO (SET_SRC (set))] | |
770 | && rtx_equal_p (SET_DEST (set), | |
771 | reg_equiv_memory_loc[REGNO (SET_SRC (set))])) | |
135eb61c R |
772 | reg_equiv_init[REGNO (SET_SRC (set))] |
773 | = gen_rtx_INSN_LIST (VOIDmode, insn, | |
774 | reg_equiv_init[REGNO (SET_SRC (set))]); | |
32131a9c RK |
775 | |
776 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
777 | scan_paradoxical_subregs (PATTERN (insn)); | |
778 | } | |
779 | ||
09dd1133 | 780 | init_elim_table (); |
32131a9c RK |
781 | |
782 | num_labels = max_label_num () - get_first_label_num (); | |
783 | ||
784 | /* Allocate the tables used to store offset information at labels. */ | |
a68d4b75 BK |
785 | /* We used to use alloca here, but the size of what it would try to |
786 | allocate would occasionally cause it to exceed the stack limit and | |
787 | cause a core dump. */ | |
788 | real_known_ptr = xmalloc (num_labels); | |
789 | real_at_ptr | |
32131a9c | 790 | = (int (*)[NUM_ELIMINABLE_REGS]) |
a68d4b75 | 791 | xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int)); |
32131a9c | 792 | |
a68d4b75 BK |
793 | offsets_known_at = real_known_ptr - get_first_label_num (); |
794 | offsets_at | |
795 | = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ()); | |
32131a9c RK |
796 | |
797 | /* Alter each pseudo-reg rtx to contain its hard reg number. | |
798 | Assign stack slots to the pseudos that lack hard regs or equivalents. | |
799 | Do not touch virtual registers. */ | |
800 | ||
801 | for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) | |
802 | alter_reg (i, -1); | |
803 | ||
32131a9c RK |
804 | /* If we have some registers we think can be eliminated, scan all insns to |
805 | see if there is an insn that sets one of these registers to something | |
806 | other than itself plus a constant. If so, the register cannot be | |
807 | eliminated. Doing this scan here eliminates an extra pass through the | |
808 | main reload loop in the most common case where register elimination | |
809 | cannot be done. */ | |
810 | for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) | |
811 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN | |
812 | || GET_CODE (insn) == CALL_INSN) | |
84832317 | 813 | note_stores (PATTERN (insn), mark_not_eliminable, NULL); |
32131a9c | 814 | |
18a90182 BS |
815 | maybe_fix_stack_asms (); |
816 | ||
03acd8f8 BS |
817 | insns_need_reload = 0; |
818 | something_needs_elimination = 0; | |
05d10675 | 819 | |
4079cd63 JW |
820 | /* Initialize to -1, which means take the first spill register. */ |
821 | last_spill_reg = -1; | |
822 | ||
32131a9c | 823 | /* Spill any hard regs that we know we can't eliminate. */ |
03acd8f8 | 824 | CLEAR_HARD_REG_SET (used_spill_regs); |
32131a9c RK |
825 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
826 | if (! ep->can_eliminate) | |
03acd8f8 | 827 | spill_hard_reg (ep->from, dumpfile, 1); |
9ff3516a RK |
828 | |
829 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
830 | if (frame_pointer_needed) | |
03acd8f8 | 831 | spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1); |
9ff3516a | 832 | #endif |
7609e720 BS |
833 | finish_spills (global, dumpfile); |
834 | ||
f1db3576 JL |
835 | /* From now on, we may need to generate moves differently. We may also |
836 | allow modifications of insns which cause them to not be recognized. | |
837 | Any such modifications will be cleaned up during reload itself. */ | |
b2f15f94 RK |
838 | reload_in_progress = 1; |
839 | ||
32131a9c RK |
840 | /* This loop scans the entire function each go-round |
841 | and repeats until one repetition spills no additional hard regs. */ | |
03acd8f8 | 842 | for (;;) |
32131a9c | 843 | { |
03acd8f8 BS |
844 | int something_changed; |
845 | int did_spill; | |
32131a9c | 846 | |
03acd8f8 | 847 | HOST_WIDE_INT starting_frame_size; |
32131a9c | 848 | |
665792eb | 849 | /* Round size of stack frame to stack_alignment_needed. This must be done |
7657bf2f JW |
850 | here because the stack size may be a part of the offset computation |
851 | for register elimination, and there might have been new stack slots | |
852 | created in the last iteration of this loop. */ | |
665792eb JH |
853 | if (cfun->stack_alignment_needed) |
854 | assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed); | |
7657bf2f JW |
855 | |
856 | starting_frame_size = get_frame_size (); | |
857 | ||
09dd1133 | 858 | set_initial_elim_offsets (); |
1f3b1e1a | 859 | set_initial_label_offsets (); |
03acd8f8 | 860 | |
32131a9c RK |
861 | /* For each pseudo register that has an equivalent location defined, |
862 | try to eliminate any eliminable registers (such as the frame pointer) | |
863 | assuming initial offsets for the replacement register, which | |
864 | is the normal case. | |
865 | ||
866 | If the resulting location is directly addressable, substitute | |
867 | the MEM we just got directly for the old REG. | |
868 | ||
869 | If it is not addressable but is a constant or the sum of a hard reg | |
870 | and constant, it is probably not addressable because the constant is | |
871 | out of range, in that case record the address; we will generate | |
872 | hairy code to compute the address in a register each time it is | |
6491dbbb RK |
873 | needed. Similarly if it is a hard register, but one that is not |
874 | valid as an address register. | |
32131a9c RK |
875 | |
876 | If the location is not addressable, but does not have one of the | |
877 | above forms, assign a stack slot. We have to do this to avoid the | |
878 | potential of producing lots of reloads if, e.g., a location involves | |
879 | a pseudo that didn't get a hard register and has an equivalent memory | |
880 | location that also involves a pseudo that didn't get a hard register. | |
881 | ||
882 | Perhaps at some point we will improve reload_when_needed handling | |
883 | so this problem goes away. But that's very hairy. */ | |
884 | ||
885 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
886 | if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) | |
887 | { | |
1914f5da | 888 | rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX); |
32131a9c RK |
889 | |
890 | if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]), | |
891 | XEXP (x, 0))) | |
892 | reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; | |
893 | else if (CONSTANT_P (XEXP (x, 0)) | |
6491dbbb RK |
894 | || (GET_CODE (XEXP (x, 0)) == REG |
895 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) | |
32131a9c RK |
896 | || (GET_CODE (XEXP (x, 0)) == PLUS |
897 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
898 | && (REGNO (XEXP (XEXP (x, 0), 0)) | |
899 | < FIRST_PSEUDO_REGISTER) | |
900 | && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) | |
901 | reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; | |
902 | else | |
903 | { | |
904 | /* Make a new stack slot. Then indicate that something | |
a8fdc208 | 905 | changed so we go back and recompute offsets for |
32131a9c RK |
906 | eliminable registers because the allocation of memory |
907 | below might change some offset. reg_equiv_{mem,address} | |
908 | will be set up for this pseudo on the next pass around | |
909 | the loop. */ | |
910 | reg_equiv_memory_loc[i] = 0; | |
911 | reg_equiv_init[i] = 0; | |
912 | alter_reg (i, -1); | |
32131a9c RK |
913 | } |
914 | } | |
a8fdc208 | 915 | |
437a710d BS |
916 | if (caller_save_needed) |
917 | setup_save_areas (); | |
918 | ||
03acd8f8 | 919 | /* If we allocated another stack slot, redo elimination bookkeeping. */ |
437a710d | 920 | if (starting_frame_size != get_frame_size ()) |
32131a9c RK |
921 | continue; |
922 | ||
437a710d | 923 | if (caller_save_needed) |
a8efe40d | 924 | { |
437a710d BS |
925 | save_call_clobbered_regs (); |
926 | /* That might have allocated new insn_chain structures. */ | |
927 | reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); | |
a8efe40d RK |
928 | } |
929 | ||
03acd8f8 BS |
930 | calculate_needs_all_insns (global); |
931 | ||
f5d8c9f4 | 932 | CLEAR_REG_SET (&spilled_pseudos); |
03acd8f8 BS |
933 | did_spill = 0; |
934 | ||
935 | something_changed = 0; | |
32131a9c | 936 | |
0dadecf6 RK |
937 | /* If we allocated any new memory locations, make another pass |
938 | since it might have changed elimination offsets. */ | |
939 | if (starting_frame_size != get_frame_size ()) | |
940 | something_changed = 1; | |
941 | ||
09dd1133 BS |
942 | { |
943 | HARD_REG_SET to_spill; | |
944 | CLEAR_HARD_REG_SET (to_spill); | |
945 | update_eliminables (&to_spill); | |
946 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
947 | if (TEST_HARD_REG_BIT (to_spill, i)) | |
32131a9c | 948 | { |
03acd8f8 BS |
949 | spill_hard_reg (i, dumpfile, 1); |
950 | did_spill = 1; | |
8f5db3c1 JL |
951 | |
952 | /* Regardless of the state of spills, if we previously had | |
953 | a register that we thought we could eliminate, but no can | |
954 | not eliminate, we must run another pass. | |
955 | ||
956 | Consider pseudos which have an entry in reg_equiv_* which | |
957 | reference an eliminable register. We must make another pass | |
958 | to update reg_equiv_* so that we do not substitute in the | |
959 | old value from when we thought the elimination could be | |
960 | performed. */ | |
961 | something_changed = 1; | |
32131a9c | 962 | } |
09dd1133 | 963 | } |
9ff3516a | 964 | |
e483bf9c BS |
965 | select_reload_regs (dumpfile); |
966 | if (failure) | |
967 | goto failed; | |
437a710d | 968 | |
e483bf9c BS |
969 | if (insns_need_reload != 0 || did_spill) |
970 | something_changed |= finish_spills (global, dumpfile); | |
7609e720 | 971 | |
03acd8f8 BS |
972 | if (! something_changed) |
973 | break; | |
974 | ||
975 | if (caller_save_needed) | |
7609e720 | 976 | delete_caller_save_insns (); |
f5d8c9f4 BS |
977 | |
978 | obstack_free (&reload_obstack, reload_firstobj); | |
32131a9c RK |
979 | } |
980 | ||
981 | /* If global-alloc was run, notify it of any register eliminations we have | |
982 | done. */ | |
983 | if (global) | |
984 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
985 | if (ep->can_eliminate) | |
986 | mark_elimination (ep->from, ep->to); | |
987 | ||
32131a9c RK |
988 | /* If a pseudo has no hard reg, delete the insns that made the equivalence. |
989 | If that insn didn't set the register (i.e., it copied the register to | |
990 | memory), just delete that insn instead of the equivalencing insn plus | |
991 | anything now dead. If we call delete_dead_insn on that insn, we may | |
135eb61c | 992 | delete the insn that actually sets the register if the register dies |
32131a9c RK |
993 | there and that is incorrect. */ |
994 | ||
995 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
135eb61c R |
996 | { |
997 | if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0) | |
998 | { | |
999 | rtx list; | |
1000 | for (list = reg_equiv_init[i]; list; list = XEXP (list, 1)) | |
1001 | { | |
1002 | rtx equiv_insn = XEXP (list, 0); | |
1003 | if (GET_CODE (equiv_insn) == NOTE) | |
1004 | continue; | |
1005 | if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn))) | |
1006 | delete_dead_insn (equiv_insn); | |
1007 | else | |
1008 | { | |
1009 | PUT_CODE (equiv_insn, NOTE); | |
1010 | NOTE_SOURCE_FILE (equiv_insn) = 0; | |
1011 | NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; | |
1012 | } | |
1013 | } | |
1014 | } | |
1015 | } | |
32131a9c RK |
1016 | |
1017 | /* Use the reload registers where necessary | |
1018 | by generating move instructions to move the must-be-register | |
1019 | values into or out of the reload registers. */ | |
1020 | ||
03acd8f8 BS |
1021 | if (insns_need_reload != 0 || something_needs_elimination |
1022 | || something_needs_operands_changed) | |
c47f5ea5 BS |
1023 | { |
1024 | int old_frame_size = get_frame_size (); | |
1025 | ||
1026 | reload_as_needed (global); | |
1027 | ||
1028 | if (old_frame_size != get_frame_size ()) | |
1029 | abort (); | |
1030 | ||
1031 | if (num_eliminable) | |
1032 | verify_initial_elim_offsets (); | |
1033 | } | |
32131a9c | 1034 | |
2a1f8b6b | 1035 | /* If we were able to eliminate the frame pointer, show that it is no |
546b63fb | 1036 | longer live at the start of any basic block. If it ls live by |
2a1f8b6b RK |
1037 | virtue of being in a pseudo, that pseudo will be marked live |
1038 | and hence the frame pointer will be known to be live via that | |
1039 | pseudo. */ | |
1040 | ||
1041 | if (! frame_pointer_needed) | |
1042 | for (i = 0; i < n_basic_blocks; i++) | |
e881bb1b | 1043 | CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start, |
8e08106d | 1044 | HARD_FRAME_POINTER_REGNUM); |
2a1f8b6b | 1045 | |
5352b11a RS |
1046 | /* Come here (with failure set nonzero) if we can't get enough spill regs |
1047 | and we decide not to abort about it. */ | |
1048 | failed: | |
1049 | ||
f5d8c9f4 | 1050 | CLEAR_REG_SET (&spilled_pseudos); |
a3ec87a8 RS |
1051 | reload_in_progress = 0; |
1052 | ||
32131a9c RK |
1053 | /* Now eliminate all pseudo regs by modifying them into |
1054 | their equivalent memory references. | |
1055 | The REG-rtx's for the pseudos are modified in place, | |
1056 | so all insns that used to refer to them now refer to memory. | |
1057 | ||
1058 | For a reg that has a reg_equiv_address, all those insns | |
1059 | were changed by reloading so that no insns refer to it any longer; | |
1060 | but the DECL_RTL of a variable decl may refer to it, | |
1061 | and if so this causes the debugging info to mention the variable. */ | |
1062 | ||
1063 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
1064 | { | |
1065 | rtx addr = 0; | |
ab1fd483 | 1066 | int in_struct = 0; |
6a651371 | 1067 | int is_scalar = 0; |
9ec36da5 JL |
1068 | int is_readonly = 0; |
1069 | ||
1070 | if (reg_equiv_memory_loc[i]) | |
ab1fd483 | 1071 | { |
9ec36da5 | 1072 | in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]); |
c6df88cb | 1073 | is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]); |
9ec36da5 | 1074 | is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]); |
ab1fd483 | 1075 | } |
9ec36da5 JL |
1076 | |
1077 | if (reg_equiv_mem[i]) | |
1078 | addr = XEXP (reg_equiv_mem[i], 0); | |
1079 | ||
32131a9c RK |
1080 | if (reg_equiv_address[i]) |
1081 | addr = reg_equiv_address[i]; | |
9ec36da5 | 1082 | |
32131a9c RK |
1083 | if (addr) |
1084 | { | |
1085 | if (reg_renumber[i] < 0) | |
1086 | { | |
1087 | rtx reg = regno_reg_rtx[i]; | |
ef178af3 | 1088 | PUT_CODE (reg, MEM); |
32131a9c RK |
1089 | XEXP (reg, 0) = addr; |
1090 | REG_USERVAR_P (reg) = 0; | |
9ec36da5 | 1091 | RTX_UNCHANGING_P (reg) = is_readonly; |
ab1fd483 | 1092 | MEM_IN_STRUCT_P (reg) = in_struct; |
c6df88cb | 1093 | MEM_SCALAR_P (reg) = is_scalar; |
41472af8 MM |
1094 | /* We have no alias information about this newly created |
1095 | MEM. */ | |
1096 | MEM_ALIAS_SET (reg) = 0; | |
32131a9c RK |
1097 | } |
1098 | else if (reg_equiv_mem[i]) | |
1099 | XEXP (reg_equiv_mem[i], 0) = addr; | |
1100 | } | |
1101 | } | |
1102 | ||
2ae74651 JL |
1103 | /* We must set reload_completed now since the cleanup_subreg_operands call |
1104 | below will re-recognize each insn and reload may have generated insns | |
1105 | which are only valid during and after reload. */ | |
1106 | reload_completed = 1; | |
1107 | ||
bd695e1e RH |
1108 | /* Make a pass over all the insns and delete all USEs which we inserted |
1109 | only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED | |
1110 | notes. Delete all CLOBBER insns that don't refer to the return value | |
1111 | and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and | |
1112 | REG_LIBCALL notes since they are no longer useful or accurate. Strip | |
1113 | and regenerate REG_INC notes that may have been moved around. */ | |
32131a9c RK |
1114 | |
1115 | for (insn = first; insn; insn = NEXT_INSN (insn)) | |
1116 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
1117 | { | |
6764d250 | 1118 | rtx *pnote; |
32131a9c | 1119 | |
0304f787 JL |
1120 | if ((GET_CODE (PATTERN (insn)) == USE |
1121 | && find_reg_note (insn, REG_EQUAL, NULL_RTX)) | |
bd695e1e RH |
1122 | || (GET_CODE (PATTERN (insn)) == CLOBBER |
1123 | && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG | |
1124 | || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0))))) | |
b60a8416 R |
1125 | { |
1126 | PUT_CODE (insn, NOTE); | |
1127 | NOTE_SOURCE_FILE (insn) = 0; | |
1128 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
1129 | continue; | |
1130 | } | |
6764d250 BS |
1131 | |
1132 | pnote = ®_NOTES (insn); | |
1133 | while (*pnote != 0) | |
32131a9c | 1134 | { |
6764d250 | 1135 | if (REG_NOTE_KIND (*pnote) == REG_DEAD |
80599fd9 | 1136 | || REG_NOTE_KIND (*pnote) == REG_UNUSED |
2dfa9a87 | 1137 | || REG_NOTE_KIND (*pnote) == REG_INC |
80599fd9 NC |
1138 | || REG_NOTE_KIND (*pnote) == REG_RETVAL |
1139 | || REG_NOTE_KIND (*pnote) == REG_LIBCALL) | |
6764d250 BS |
1140 | *pnote = XEXP (*pnote, 1); |
1141 | else | |
1142 | pnote = &XEXP (*pnote, 1); | |
32131a9c | 1143 | } |
0304f787 | 1144 | |
2dfa9a87 MH |
1145 | #ifdef AUTO_INC_DEC |
1146 | add_auto_inc_notes (insn, PATTERN (insn)); | |
1147 | #endif | |
1148 | ||
0304f787 JL |
1149 | /* And simplify (subreg (reg)) if it appears as an operand. */ |
1150 | cleanup_subreg_operands (insn); | |
b60a8416 | 1151 | } |
32131a9c | 1152 | |
ab87f8c8 JL |
1153 | /* If we are doing stack checking, give a warning if this function's |
1154 | frame size is larger than we expect. */ | |
1155 | if (flag_stack_check && ! STACK_CHECK_BUILTIN) | |
1156 | { | |
1157 | HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; | |
05d10675 BS |
1158 | static int verbose_warned = 0; |
1159 | ||
ab87f8c8 JL |
1160 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1161 | if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i]) | |
1162 | size += UNITS_PER_WORD; | |
1163 | ||
1164 | if (size > STACK_CHECK_MAX_FRAME_SIZE) | |
05d10675 | 1165 | { |
ab87f8c8 JL |
1166 | warning ("frame size too large for reliable stack checking"); |
1167 | if (! verbose_warned) | |
1168 | { | |
1169 | warning ("try reducing the number of local variables"); | |
1170 | verbose_warned = 1; | |
1171 | } | |
1172 | } | |
1173 | } | |
1174 | ||
32131a9c | 1175 | /* Indicate that we no longer have known memory locations or constants. */ |
58d9f9d9 JL |
1176 | if (reg_equiv_constant) |
1177 | free (reg_equiv_constant); | |
32131a9c | 1178 | reg_equiv_constant = 0; |
58d9f9d9 JL |
1179 | if (reg_equiv_memory_loc) |
1180 | free (reg_equiv_memory_loc); | |
32131a9c | 1181 | reg_equiv_memory_loc = 0; |
5352b11a | 1182 | |
a68d4b75 BK |
1183 | if (real_known_ptr) |
1184 | free (real_known_ptr); | |
1185 | if (real_at_ptr) | |
1186 | free (real_at_ptr); | |
1187 | ||
56a65848 DB |
1188 | free (reg_equiv_mem); |
1189 | free (reg_equiv_init); | |
1190 | free (reg_equiv_address); | |
1191 | free (reg_max_ref_width); | |
03acd8f8 BS |
1192 | free (reg_old_renumber); |
1193 | free (pseudo_previous_regs); | |
1194 | free (pseudo_forbidden_regs); | |
56a65848 | 1195 | |
8b4f9969 JW |
1196 | CLEAR_HARD_REG_SET (used_spill_regs); |
1197 | for (i = 0; i < n_spills; i++) | |
1198 | SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]); | |
1199 | ||
7609e720 BS |
1200 | /* Free all the insn_chain structures at once. */ |
1201 | obstack_free (&reload_obstack, reload_startobj); | |
1202 | unused_insn_chains = 0; | |
1203 | ||
5352b11a | 1204 | return failure; |
32131a9c | 1205 | } |
1e5bd841 | 1206 | |
18a90182 BS |
1207 | /* Yet another special case. Unfortunately, reg-stack forces people to |
1208 | write incorrect clobbers in asm statements. These clobbers must not | |
1209 | cause the register to appear in bad_spill_regs, otherwise we'll call | |
1210 | fatal_insn later. We clear the corresponding regnos in the live | |
1211 | register sets to avoid this. | |
1212 | The whole thing is rather sick, I'm afraid. */ | |
efc9bd41 | 1213 | |
18a90182 BS |
1214 | static void |
1215 | maybe_fix_stack_asms () | |
1216 | { | |
1217 | #ifdef STACK_REGS | |
392dccb7 | 1218 | const char *constraints[MAX_RECOG_OPERANDS]; |
18a90182 BS |
1219 | enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
1220 | struct insn_chain *chain; | |
1221 | ||
1222 | for (chain = reload_insn_chain; chain != 0; chain = chain->next) | |
1223 | { | |
1224 | int i, noperands; | |
1225 | HARD_REG_SET clobbered, allowed; | |
1226 | rtx pat; | |
1227 | ||
1228 | if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i' | |
1229 | || (noperands = asm_noperands (PATTERN (chain->insn))) < 0) | |
1230 | continue; | |
1231 | pat = PATTERN (chain->insn); | |
1232 | if (GET_CODE (pat) != PARALLEL) | |
1233 | continue; | |
1234 | ||
1235 | CLEAR_HARD_REG_SET (clobbered); | |
1236 | CLEAR_HARD_REG_SET (allowed); | |
1237 | ||
1238 | /* First, make a mask of all stack regs that are clobbered. */ | |
1239 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
1240 | { | |
1241 | rtx t = XVECEXP (pat, 0, i); | |
1242 | if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0))) | |
1243 | SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0))); | |
1244 | } | |
1245 | ||
1246 | /* Get the operand values and constraints out of the insn. */ | |
1ccbefce | 1247 | decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc, |
18a90182 BS |
1248 | constraints, operand_mode); |
1249 | ||
1250 | /* For every operand, see what registers are allowed. */ | |
1251 | for (i = 0; i < noperands; i++) | |
1252 | { | |
6b9c6f4f | 1253 | const char *p = constraints[i]; |
18a90182 BS |
1254 | /* For every alternative, we compute the class of registers allowed |
1255 | for reloading in CLS, and merge its contents into the reg set | |
1256 | ALLOWED. */ | |
1257 | int cls = (int) NO_REGS; | |
1258 | ||
1259 | for (;;) | |
1260 | { | |
1261 | char c = *p++; | |
1262 | ||
1263 | if (c == '\0' || c == ',' || c == '#') | |
1264 | { | |
1265 | /* End of one alternative - mark the regs in the current | |
1266 | class, and reset the class. */ | |
1267 | IOR_HARD_REG_SET (allowed, reg_class_contents[cls]); | |
1268 | cls = NO_REGS; | |
1269 | if (c == '#') | |
1270 | do { | |
1271 | c = *p++; | |
1272 | } while (c != '\0' && c != ','); | |
1273 | if (c == '\0') | |
1274 | break; | |
1275 | continue; | |
1276 | } | |
1277 | ||
1278 | switch (c) | |
1279 | { | |
1280 | case '=': case '+': case '*': case '%': case '?': case '!': | |
1281 | case '0': case '1': case '2': case '3': case '4': case 'm': | |
1282 | case '<': case '>': case 'V': case 'o': case '&': case 'E': | |
1283 | case 'F': case 's': case 'i': case 'n': case 'X': case 'I': | |
1284 | case 'J': case 'K': case 'L': case 'M': case 'N': case 'O': | |
1285 | case 'P': | |
1286 | #ifdef EXTRA_CONSTRAINT | |
1287 | case 'Q': case 'R': case 'S': case 'T': case 'U': | |
1288 | #endif | |
1289 | break; | |
1290 | ||
1291 | case 'p': | |
1292 | cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS]; | |
1293 | break; | |
1294 | ||
1295 | case 'g': | |
1296 | case 'r': | |
1297 | cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS]; | |
1298 | break; | |
1299 | ||
1300 | default: | |
1301 | cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)]; | |
05d10675 | 1302 | |
18a90182 BS |
1303 | } |
1304 | } | |
1305 | } | |
1306 | /* Those of the registers which are clobbered, but allowed by the | |
1307 | constraints, must be usable as reload registers. So clear them | |
1308 | out of the life information. */ | |
1309 | AND_HARD_REG_SET (allowed, clobbered); | |
1310 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1311 | if (TEST_HARD_REG_BIT (allowed, i)) | |
1312 | { | |
239a0f5b BS |
1313 | CLEAR_REGNO_REG_SET (&chain->live_throughout, i); |
1314 | CLEAR_REGNO_REG_SET (&chain->dead_or_set, i); | |
18a90182 BS |
1315 | } |
1316 | } | |
1317 | ||
1318 | #endif | |
1319 | } | |
03acd8f8 | 1320 | \f |
f5d8c9f4 BS |
1321 | /* Copy the global variables n_reloads and rld into the corresponding elts |
1322 | of CHAIN. */ | |
1323 | static void | |
1324 | copy_reloads (chain) | |
1325 | struct insn_chain *chain; | |
1326 | { | |
1327 | chain->n_reloads = n_reloads; | |
1328 | chain->rld | |
1329 | = (struct reload *) obstack_alloc (&reload_obstack, | |
1330 | n_reloads * sizeof (struct reload)); | |
1331 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); | |
1332 | reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0); | |
1333 | } | |
1334 | ||
03acd8f8 BS |
1335 | /* Walk the chain of insns, and determine for each whether it needs reloads |
1336 | and/or eliminations. Build the corresponding insns_need_reload list, and | |
1337 | set something_needs_elimination as appropriate. */ | |
1338 | static void | |
7609e720 | 1339 | calculate_needs_all_insns (global) |
1e5bd841 BS |
1340 | int global; |
1341 | { | |
7609e720 | 1342 | struct insn_chain **pprev_reload = &insns_need_reload; |
67e61fe7 | 1343 | struct insn_chain *chain; |
1e5bd841 | 1344 | |
03acd8f8 BS |
1345 | something_needs_elimination = 0; |
1346 | ||
f5d8c9f4 | 1347 | reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0); |
67e61fe7 | 1348 | for (chain = reload_insn_chain; chain != 0; chain = chain->next) |
1e5bd841 | 1349 | { |
67e61fe7 | 1350 | rtx insn = chain->insn; |
03acd8f8 | 1351 | |
f5d8c9f4 BS |
1352 | /* Clear out the shortcuts. */ |
1353 | chain->n_reloads = 0; | |
67e61fe7 BS |
1354 | chain->need_elim = 0; |
1355 | chain->need_reload = 0; | |
1356 | chain->need_operand_change = 0; | |
1e5bd841 | 1357 | |
03acd8f8 BS |
1358 | /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might |
1359 | include REG_LABEL), we need to see what effects this has on the | |
1360 | known offsets at labels. */ | |
1e5bd841 BS |
1361 | |
1362 | if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN | |
1363 | || (GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
1364 | && REG_NOTES (insn) != 0)) | |
1365 | set_label_offsets (insn, insn, 0); | |
1366 | ||
1367 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
1368 | { | |
1369 | rtx old_body = PATTERN (insn); | |
1370 | int old_code = INSN_CODE (insn); | |
1371 | rtx old_notes = REG_NOTES (insn); | |
1372 | int did_elimination = 0; | |
cb2afeb3 | 1373 | int operands_changed = 0; |
2b49ee39 R |
1374 | rtx set = single_set (insn); |
1375 | ||
1376 | /* Skip insns that only set an equivalence. */ | |
1377 | if (set && GET_CODE (SET_DEST (set)) == REG | |
1378 | && reg_renumber[REGNO (SET_DEST (set))] < 0 | |
1379 | && reg_equiv_constant[REGNO (SET_DEST (set))]) | |
67e61fe7 | 1380 | continue; |
1e5bd841 | 1381 | |
1e5bd841 | 1382 | /* If needed, eliminate any eliminable registers. */ |
2b49ee39 | 1383 | if (num_eliminable || num_eliminable_invariants) |
1e5bd841 BS |
1384 | did_elimination = eliminate_regs_in_insn (insn, 0); |
1385 | ||
1386 | /* Analyze the instruction. */ | |
cb2afeb3 R |
1387 | operands_changed = find_reloads (insn, 0, spill_indirect_levels, |
1388 | global, spill_reg_order); | |
1389 | ||
1390 | /* If a no-op set needs more than one reload, this is likely | |
1391 | to be something that needs input address reloads. We | |
1392 | can't get rid of this cleanly later, and it is of no use | |
1393 | anyway, so discard it now. | |
1394 | We only do this when expensive_optimizations is enabled, | |
1395 | since this complements reload inheritance / output | |
1396 | reload deletion, and it can make debugging harder. */ | |
1397 | if (flag_expensive_optimizations && n_reloads > 1) | |
1398 | { | |
1399 | rtx set = single_set (insn); | |
1400 | if (set | |
1401 | && SET_SRC (set) == SET_DEST (set) | |
1402 | && GET_CODE (SET_SRC (set)) == REG | |
1403 | && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) | |
1404 | { | |
1405 | PUT_CODE (insn, NOTE); | |
1406 | NOTE_SOURCE_FILE (insn) = 0; | |
1407 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
1408 | continue; | |
1409 | } | |
1410 | } | |
1411 | if (num_eliminable) | |
1412 | update_eliminable_offsets (); | |
1e5bd841 BS |
1413 | |
1414 | /* Remember for later shortcuts which insns had any reloads or | |
7609e720 BS |
1415 | register eliminations. */ |
1416 | chain->need_elim = did_elimination; | |
03acd8f8 BS |
1417 | chain->need_reload = n_reloads > 0; |
1418 | chain->need_operand_change = operands_changed; | |
1e5bd841 BS |
1419 | |
1420 | /* Discard any register replacements done. */ | |
1421 | if (did_elimination) | |
1422 | { | |
f5d8c9f4 | 1423 | obstack_free (&reload_obstack, reload_insn_firstobj); |
1e5bd841 BS |
1424 | PATTERN (insn) = old_body; |
1425 | INSN_CODE (insn) = old_code; | |
1426 | REG_NOTES (insn) = old_notes; | |
1427 | something_needs_elimination = 1; | |
1428 | } | |
1429 | ||
cb2afeb3 R |
1430 | something_needs_operands_changed |= operands_changed; |
1431 | ||
437a710d | 1432 | if (n_reloads != 0) |
7609e720 | 1433 | { |
f5d8c9f4 | 1434 | copy_reloads (chain); |
7609e720 BS |
1435 | *pprev_reload = chain; |
1436 | pprev_reload = &chain->next_need_reload; | |
7609e720 | 1437 | } |
1e5bd841 | 1438 | } |
1e5bd841 | 1439 | } |
7609e720 | 1440 | *pprev_reload = 0; |
1e5bd841 | 1441 | } |
f5d8c9f4 BS |
1442 | \f |
1443 | /* Comparison function for qsort to decide which of two reloads | |
1444 | should be handled first. *P1 and *P2 are the reload numbers. */ | |
1e5bd841 | 1445 | |
f5d8c9f4 BS |
1446 | static int |
1447 | reload_reg_class_lower (r1p, r2p) | |
1448 | const PTR r1p; | |
1449 | const PTR r2p; | |
1e5bd841 | 1450 | { |
272df862 | 1451 | register int r1 = *(const short *)r1p, r2 = *(const short *)r2p; |
f5d8c9f4 | 1452 | register int t; |
1e5bd841 | 1453 | |
f5d8c9f4 BS |
1454 | /* Consider required reloads before optional ones. */ |
1455 | t = rld[r1].optional - rld[r2].optional; | |
1456 | if (t != 0) | |
1457 | return t; | |
1e5bd841 | 1458 | |
f5d8c9f4 BS |
1459 | /* Count all solitary classes before non-solitary ones. */ |
1460 | t = ((reg_class_size[(int) rld[r2].class] == 1) | |
1461 | - (reg_class_size[(int) rld[r1].class] == 1)); | |
1462 | if (t != 0) | |
1463 | return t; | |
1e5bd841 | 1464 | |
f5d8c9f4 BS |
1465 | /* Aside from solitaires, consider all multi-reg groups first. */ |
1466 | t = rld[r2].nregs - rld[r1].nregs; | |
1467 | if (t != 0) | |
1468 | return t; | |
1e5bd841 | 1469 | |
f5d8c9f4 BS |
1470 | /* Consider reloads in order of increasing reg-class number. */ |
1471 | t = (int) rld[r1].class - (int) rld[r2].class; | |
1472 | if (t != 0) | |
1473 | return t; | |
1e5bd841 | 1474 | |
f5d8c9f4 BS |
1475 | /* If reloads are equally urgent, sort by reload number, |
1476 | so that the results of qsort leave nothing to chance. */ | |
1477 | return r1 - r2; | |
1478 | } | |
1479 | \f | |
1480 | /* The cost of spilling each hard reg. */ | |
1481 | static int spill_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1482 | |
f5d8c9f4 BS |
1483 | /* When spilling multiple hard registers, we use SPILL_COST for the first |
1484 | spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST | |
1485 | only the first hard reg for a multi-reg pseudo. */ | |
1486 | static int spill_add_cost[FIRST_PSEUDO_REGISTER]; | |
1e5bd841 | 1487 | |
f5d8c9f4 | 1488 | /* Update the spill cost arrays, considering that pseudo REG is live. */ |
770ae6cc | 1489 | |
f5d8c9f4 BS |
1490 | static void |
1491 | count_pseudo (reg) | |
1492 | int reg; | |
1493 | { | |
1494 | int n_refs = REG_N_REFS (reg); | |
1495 | int r = reg_renumber[reg]; | |
1496 | int nregs; | |
1e5bd841 | 1497 | |
f5d8c9f4 BS |
1498 | if (REGNO_REG_SET_P (&pseudos_counted, reg) |
1499 | || REGNO_REG_SET_P (&spilled_pseudos, reg)) | |
1500 | return; | |
1e5bd841 | 1501 | |
f5d8c9f4 | 1502 | SET_REGNO_REG_SET (&pseudos_counted, reg); |
1e5bd841 | 1503 | |
f5d8c9f4 BS |
1504 | if (r < 0) |
1505 | abort (); | |
1506 | ||
1507 | spill_add_cost[r] += n_refs; | |
1e5bd841 | 1508 | |
f5d8c9f4 BS |
1509 | nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); |
1510 | while (nregs-- > 0) | |
1511 | spill_cost[r + nregs] += n_refs; | |
1512 | } | |
1e5bd841 | 1513 | |
f5d8c9f4 BS |
1514 | /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the |
1515 | contents of BAD_SPILL_REGS for the insn described by CHAIN. */ | |
efc9bd41 | 1516 | |
f5d8c9f4 BS |
1517 | static void |
1518 | order_regs_for_reload (chain) | |
1519 | struct insn_chain *chain; | |
1520 | { | |
fbd40359 | 1521 | int i; |
efc9bd41 RK |
1522 | HARD_REG_SET used_by_pseudos; |
1523 | HARD_REG_SET used_by_pseudos2; | |
1e5bd841 | 1524 | |
efc9bd41 | 1525 | COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set); |
1e5bd841 | 1526 | |
f5d8c9f4 BS |
1527 | memset (spill_cost, 0, sizeof spill_cost); |
1528 | memset (spill_add_cost, 0, sizeof spill_add_cost); | |
1e5bd841 | 1529 | |
f5d8c9f4 | 1530 | /* Count number of uses of each hard reg by pseudo regs allocated to it |
efc9bd41 RK |
1531 | and then order them by decreasing use. First exclude hard registers |
1532 | that are live in or across this insn. */ | |
1533 | ||
1534 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); | |
1535 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
1536 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos); | |
1537 | IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2); | |
1e5bd841 | 1538 | |
f5d8c9f4 BS |
1539 | /* Now find out which pseudos are allocated to it, and update |
1540 | hard_reg_n_uses. */ | |
1541 | CLEAR_REG_SET (&pseudos_counted); | |
1e5bd841 | 1542 | |
f5d8c9f4 | 1543 | EXECUTE_IF_SET_IN_REG_SET |
fbd40359 | 1544 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, |
f5d8c9f4 | 1545 | { |
fbd40359 | 1546 | count_pseudo (i); |
f5d8c9f4 BS |
1547 | }); |
1548 | EXECUTE_IF_SET_IN_REG_SET | |
fbd40359 | 1549 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, |
f5d8c9f4 | 1550 | { |
fbd40359 | 1551 | count_pseudo (i); |
f5d8c9f4 BS |
1552 | }); |
1553 | CLEAR_REG_SET (&pseudos_counted); | |
1e5bd841 | 1554 | } |
03acd8f8 | 1555 | \f |
f5d8c9f4 BS |
1556 | /* Vector of reload-numbers showing the order in which the reloads should |
1557 | be processed. */ | |
1558 | static short reload_order[MAX_RELOADS]; | |
1e5bd841 | 1559 | |
f5d8c9f4 BS |
1560 | /* This is used to keep track of the spill regs used in one insn. */ |
1561 | static HARD_REG_SET used_spill_regs_local; | |
03acd8f8 | 1562 | |
f5d8c9f4 BS |
1563 | /* We decided to spill hard register SPILLED, which has a size of |
1564 | SPILLED_NREGS. Determine how pseudo REG, which is live during the insn, | |
1565 | is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will | |
1566 | update SPILL_COST/SPILL_ADD_COST. */ | |
770ae6cc | 1567 | |
03acd8f8 | 1568 | static void |
f5d8c9f4 BS |
1569 | count_spilled_pseudo (spilled, spilled_nregs, reg) |
1570 | int spilled, spilled_nregs, reg; | |
1e5bd841 | 1571 | { |
f5d8c9f4 BS |
1572 | int r = reg_renumber[reg]; |
1573 | int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); | |
1e5bd841 | 1574 | |
f5d8c9f4 BS |
1575 | if (REGNO_REG_SET_P (&spilled_pseudos, reg) |
1576 | || spilled + spilled_nregs <= r || r + nregs <= spilled) | |
1577 | return; | |
1e5bd841 | 1578 | |
f5d8c9f4 | 1579 | SET_REGNO_REG_SET (&spilled_pseudos, reg); |
1e5bd841 | 1580 | |
f5d8c9f4 BS |
1581 | spill_add_cost[r] -= REG_N_REFS (reg); |
1582 | while (nregs-- > 0) | |
1583 | spill_cost[r + nregs] -= REG_N_REFS (reg); | |
1e5bd841 BS |
1584 | } |
1585 | ||
f5d8c9f4 | 1586 | /* Find reload register to use for reload number ORDER. */ |
03acd8f8 | 1587 | |
f5d8c9f4 BS |
1588 | static int |
1589 | find_reg (chain, order, dumpfile) | |
03acd8f8 | 1590 | struct insn_chain *chain; |
f5d8c9f4 | 1591 | int order; |
1e5bd841 BS |
1592 | FILE *dumpfile; |
1593 | { | |
f5d8c9f4 BS |
1594 | int rnum = reload_order[order]; |
1595 | struct reload *rl = rld + rnum; | |
1596 | int best_cost = INT_MAX; | |
1597 | int best_reg = -1; | |
770ae6cc RK |
1598 | unsigned int i, j; |
1599 | int k; | |
f5d8c9f4 BS |
1600 | HARD_REG_SET not_usable; |
1601 | HARD_REG_SET used_by_other_reload; | |
1e5bd841 | 1602 | |
f5d8c9f4 BS |
1603 | COPY_HARD_REG_SET (not_usable, bad_spill_regs); |
1604 | IOR_HARD_REG_SET (not_usable, bad_spill_regs_global); | |
1605 | IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]); | |
1606 | ||
1607 | CLEAR_HARD_REG_SET (used_by_other_reload); | |
770ae6cc | 1608 | for (k = 0; k < order; k++) |
1e5bd841 | 1609 | { |
770ae6cc RK |
1610 | int other = reload_order[k]; |
1611 | ||
f5d8c9f4 BS |
1612 | if (rld[other].regno >= 0 && reloads_conflict (other, rnum)) |
1613 | for (j = 0; j < rld[other].nregs; j++) | |
1614 | SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j); | |
1615 | } | |
1e5bd841 | 1616 | |
f5d8c9f4 BS |
1617 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
1618 | { | |
770ae6cc RK |
1619 | unsigned int regno = i; |
1620 | ||
f5d8c9f4 BS |
1621 | if (! TEST_HARD_REG_BIT (not_usable, regno) |
1622 | && ! TEST_HARD_REG_BIT (used_by_other_reload, regno) | |
1623 | && HARD_REGNO_MODE_OK (regno, rl->mode)) | |
1e5bd841 | 1624 | { |
f5d8c9f4 BS |
1625 | int this_cost = spill_cost[regno]; |
1626 | int ok = 1; | |
770ae6cc | 1627 | unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode); |
1e5bd841 | 1628 | |
f5d8c9f4 BS |
1629 | for (j = 1; j < this_nregs; j++) |
1630 | { | |
1631 | this_cost += spill_add_cost[regno + j]; | |
1632 | if ((TEST_HARD_REG_BIT (not_usable, regno + j)) | |
1633 | || TEST_HARD_REG_BIT (used_by_other_reload, regno + j)) | |
1634 | ok = 0; | |
1635 | } | |
1636 | if (! ok) | |
1637 | continue; | |
1638 | if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno) | |
1639 | this_cost--; | |
1640 | if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno) | |
1641 | this_cost--; | |
1642 | if (this_cost < best_cost | |
1643 | /* Among registers with equal cost, prefer caller-saved ones, or | |
1644 | use REG_ALLOC_ORDER if it is defined. */ | |
1645 | || (this_cost == best_cost | |
1646 | #ifdef REG_ALLOC_ORDER | |
1647 | && (inv_reg_alloc_order[regno] | |
1648 | < inv_reg_alloc_order[best_reg]) | |
1649 | #else | |
1650 | && call_used_regs[regno] | |
1651 | && ! call_used_regs[best_reg] | |
1652 | #endif | |
1653 | )) | |
1654 | { | |
1655 | best_reg = regno; | |
1656 | best_cost = this_cost; | |
1e5bd841 BS |
1657 | } |
1658 | } | |
1659 | } | |
f5d8c9f4 BS |
1660 | if (best_reg == -1) |
1661 | return 0; | |
770ae6cc | 1662 | |
f5d8c9f4 BS |
1663 | if (dumpfile) |
1664 | fprintf (dumpfile, "Using reg %d for reload %d\n", best_reg, rnum); | |
770ae6cc | 1665 | |
f5d8c9f4 BS |
1666 | rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode); |
1667 | rl->regno = best_reg; | |
1e5bd841 | 1668 | |
f5d8c9f4 | 1669 | EXECUTE_IF_SET_IN_REG_SET |
239a0f5b | 1670 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, |
f5d8c9f4 BS |
1671 | { |
1672 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1673 | }); | |
770ae6cc | 1674 | |
f5d8c9f4 | 1675 | EXECUTE_IF_SET_IN_REG_SET |
239a0f5b | 1676 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, |
f5d8c9f4 BS |
1677 | { |
1678 | count_spilled_pseudo (best_reg, rl->nregs, j); | |
1679 | }); | |
03acd8f8 | 1680 | |
f5d8c9f4 BS |
1681 | for (i = 0; i < rl->nregs; i++) |
1682 | { | |
1683 | if (spill_cost[best_reg + i] != 0 | |
1684 | || spill_add_cost[best_reg + i] != 0) | |
1685 | abort (); | |
1686 | SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i); | |
1687 | } | |
1688 | return 1; | |
03acd8f8 BS |
1689 | } |
1690 | ||
1691 | /* Find more reload regs to satisfy the remaining need of an insn, which | |
1692 | is given by CHAIN. | |
1e5bd841 BS |
1693 | Do it by ascending class number, since otherwise a reg |
1694 | might be spilled for a big class and might fail to count | |
f5d8c9f4 | 1695 | for a smaller class even though it belongs to that class. */ |
1e5bd841 | 1696 | |
03acd8f8 BS |
1697 | static void |
1698 | find_reload_regs (chain, dumpfile) | |
1699 | struct insn_chain *chain; | |
1e5bd841 BS |
1700 | FILE *dumpfile; |
1701 | { | |
f5d8c9f4 | 1702 | int i; |
1e5bd841 | 1703 | |
f5d8c9f4 BS |
1704 | /* In order to be certain of getting the registers we need, |
1705 | we must sort the reloads into order of increasing register class. | |
1706 | Then our grabbing of reload registers will parallel the process | |
1707 | that provided the reload registers. */ | |
1708 | for (i = 0; i < chain->n_reloads; i++) | |
1e5bd841 | 1709 | { |
f5d8c9f4 BS |
1710 | /* Show whether this reload already has a hard reg. */ |
1711 | if (chain->rld[i].reg_rtx) | |
1e5bd841 | 1712 | { |
f5d8c9f4 BS |
1713 | int regno = REGNO (chain->rld[i].reg_rtx); |
1714 | chain->rld[i].regno = regno; | |
770ae6cc RK |
1715 | chain->rld[i].nregs |
1716 | = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx)); | |
1e5bd841 | 1717 | } |
f5d8c9f4 BS |
1718 | else |
1719 | chain->rld[i].regno = -1; | |
1720 | reload_order[i] = i; | |
1721 | } | |
1e5bd841 | 1722 | |
f5d8c9f4 BS |
1723 | n_reloads = chain->n_reloads; |
1724 | memcpy (rld, chain->rld, n_reloads * sizeof (struct reload)); | |
1e5bd841 | 1725 | |
f5d8c9f4 | 1726 | CLEAR_HARD_REG_SET (used_spill_regs_local); |
03acd8f8 | 1727 | |
f5d8c9f4 BS |
1728 | if (dumpfile) |
1729 | fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn)); | |
1e5bd841 | 1730 | |
f5d8c9f4 | 1731 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); |
1e5bd841 | 1732 | |
f5d8c9f4 | 1733 | /* Compute the order of preference for hard registers to spill. */ |
1e5bd841 | 1734 | |
f5d8c9f4 | 1735 | order_regs_for_reload (chain); |
1e5bd841 | 1736 | |
f5d8c9f4 BS |
1737 | for (i = 0; i < n_reloads; i++) |
1738 | { | |
1739 | int r = reload_order[i]; | |
1e5bd841 | 1740 | |
f5d8c9f4 BS |
1741 | /* Ignore reloads that got marked inoperative. */ |
1742 | if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p) | |
1743 | && ! rld[r].optional | |
1744 | && rld[r].regno == -1) | |
1745 | if (! find_reg (chain, i, dumpfile)) | |
1746 | { | |
ecf3151a | 1747 | spill_failure (chain->insn, rld[r].class); |
f5d8c9f4 | 1748 | failure = 1; |
03acd8f8 | 1749 | return; |
f5d8c9f4 | 1750 | } |
1e5bd841 | 1751 | } |
05d10675 | 1752 | |
f5d8c9f4 BS |
1753 | COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local); |
1754 | IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local); | |
03acd8f8 | 1755 | |
f5d8c9f4 | 1756 | memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); |
1e5bd841 BS |
1757 | } |
1758 | ||
f5d8c9f4 BS |
1759 | static void |
1760 | select_reload_regs (dumpfile) | |
09dd1133 BS |
1761 | FILE *dumpfile; |
1762 | { | |
f5d8c9f4 | 1763 | struct insn_chain *chain; |
09dd1133 | 1764 | |
f5d8c9f4 BS |
1765 | /* Try to satisfy the needs for each insn. */ |
1766 | for (chain = insns_need_reload; chain != 0; | |
1767 | chain = chain->next_need_reload) | |
1768 | find_reload_regs (chain, dumpfile); | |
09dd1133 | 1769 | } |
32131a9c | 1770 | \f |
437a710d BS |
1771 | /* Delete all insns that were inserted by emit_caller_save_insns during |
1772 | this iteration. */ | |
1773 | static void | |
7609e720 | 1774 | delete_caller_save_insns () |
437a710d | 1775 | { |
7609e720 | 1776 | struct insn_chain *c = reload_insn_chain; |
437a710d | 1777 | |
7609e720 | 1778 | while (c != 0) |
437a710d | 1779 | { |
7609e720 | 1780 | while (c != 0 && c->is_caller_save_insn) |
437a710d | 1781 | { |
7609e720 BS |
1782 | struct insn_chain *next = c->next; |
1783 | rtx insn = c->insn; | |
1784 | ||
3b413743 RH |
1785 | if (insn == BLOCK_HEAD (c->block)) |
1786 | BLOCK_HEAD (c->block) = NEXT_INSN (insn); | |
1787 | if (insn == BLOCK_END (c->block)) | |
1788 | BLOCK_END (c->block) = PREV_INSN (insn); | |
7609e720 BS |
1789 | if (c == reload_insn_chain) |
1790 | reload_insn_chain = next; | |
1791 | ||
1792 | if (NEXT_INSN (insn) != 0) | |
1793 | PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); | |
1794 | if (PREV_INSN (insn) != 0) | |
1795 | NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); | |
1796 | ||
1797 | if (next) | |
1798 | next->prev = c->prev; | |
1799 | if (c->prev) | |
1800 | c->prev->next = next; | |
1801 | c->next = unused_insn_chains; | |
1802 | unused_insn_chains = c; | |
1803 | c = next; | |
437a710d | 1804 | } |
7609e720 BS |
1805 | if (c != 0) |
1806 | c = c->next; | |
437a710d BS |
1807 | } |
1808 | } | |
1809 | \f | |
5352b11a RS |
1810 | /* Handle the failure to find a register to spill. |
1811 | INSN should be one of the insns which needed this particular spill reg. */ | |
1812 | ||
1813 | static void | |
ecf3151a | 1814 | spill_failure (insn, class) |
5352b11a | 1815 | rtx insn; |
ecf3151a | 1816 | enum reg_class class; |
5352b11a | 1817 | { |
ecf3151a | 1818 | static const char *const reg_class_names[] = REG_CLASS_NAMES; |
5352b11a | 1819 | if (asm_noperands (PATTERN (insn)) >= 0) |
ecf3151a BS |
1820 | error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.", |
1821 | reg_class_names[class]); | |
5352b11a | 1822 | else |
ecf3151a BS |
1823 | { |
1824 | error ("Unable to find a register to spill in class `%s'.", | |
1825 | reg_class_names[class]); | |
1826 | fatal_insn ("This is the insn:", insn); | |
1827 | } | |
5352b11a | 1828 | } |
32131a9c RK |
1829 | \f |
1830 | /* Delete an unneeded INSN and any previous insns who sole purpose is loading | |
1831 | data that is dead in INSN. */ | |
1832 | ||
1833 | static void | |
1834 | delete_dead_insn (insn) | |
1835 | rtx insn; | |
1836 | { | |
1837 | rtx prev = prev_real_insn (insn); | |
1838 | rtx prev_dest; | |
1839 | ||
1840 | /* If the previous insn sets a register that dies in our insn, delete it | |
1841 | too. */ | |
1842 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
1843 | && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG) | |
1844 | && reg_mentioned_p (prev_dest, PATTERN (insn)) | |
b294ca38 R |
1845 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) |
1846 | && ! side_effects_p (SET_SRC (PATTERN (prev)))) | |
32131a9c RK |
1847 | delete_dead_insn (prev); |
1848 | ||
1849 | PUT_CODE (insn, NOTE); | |
1850 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
1851 | NOTE_SOURCE_FILE (insn) = 0; | |
1852 | } | |
1853 | ||
1854 | /* Modify the home of pseudo-reg I. | |
1855 | The new home is present in reg_renumber[I]. | |
1856 | ||
1857 | FROM_REG may be the hard reg that the pseudo-reg is being spilled from; | |
1858 | or it may be -1, meaning there is none or it is not relevant. | |
1859 | This is used so that all pseudos spilled from a given hard reg | |
1860 | can share one stack slot. */ | |
1861 | ||
1862 | static void | |
1863 | alter_reg (i, from_reg) | |
1864 | register int i; | |
1865 | int from_reg; | |
1866 | { | |
1867 | /* When outputting an inline function, this can happen | |
1868 | for a reg that isn't actually used. */ | |
1869 | if (regno_reg_rtx[i] == 0) | |
1870 | return; | |
1871 | ||
1872 | /* If the reg got changed to a MEM at rtl-generation time, | |
1873 | ignore it. */ | |
1874 | if (GET_CODE (regno_reg_rtx[i]) != REG) | |
1875 | return; | |
1876 | ||
1877 | /* Modify the reg-rtx to contain the new hard reg | |
1878 | number or else to contain its pseudo reg number. */ | |
1879 | REGNO (regno_reg_rtx[i]) | |
1880 | = reg_renumber[i] >= 0 ? reg_renumber[i] : i; | |
1881 | ||
1882 | /* If we have a pseudo that is needed but has no hard reg or equivalent, | |
1883 | allocate a stack slot for it. */ | |
1884 | ||
1885 | if (reg_renumber[i] < 0 | |
b1f21e0a | 1886 | && REG_N_REFS (i) > 0 |
32131a9c RK |
1887 | && reg_equiv_constant[i] == 0 |
1888 | && reg_equiv_memory_loc[i] == 0) | |
1889 | { | |
1890 | register rtx x; | |
770ae6cc RK |
1891 | unsigned int inherent_size = PSEUDO_REGNO_BYTES (i); |
1892 | unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]); | |
32131a9c RK |
1893 | int adjust = 0; |
1894 | ||
1895 | /* Each pseudo reg has an inherent size which comes from its own mode, | |
1896 | and a total size which provides room for paradoxical subregs | |
1897 | which refer to the pseudo reg in wider modes. | |
1898 | ||
1899 | We can use a slot already allocated if it provides both | |
1900 | enough inherent space and enough total space. | |
1901 | Otherwise, we allocate a new slot, making sure that it has no less | |
1902 | inherent space, and no less total space, then the previous slot. */ | |
1903 | if (from_reg == -1) | |
1904 | { | |
1905 | /* No known place to spill from => no slot to reuse. */ | |
cabcf079 ILT |
1906 | x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, |
1907 | inherent_size == total_size ? 0 : -1); | |
f76b9db2 | 1908 | if (BYTES_BIG_ENDIAN) |
02db8dd0 RK |
1909 | /* Cancel the big-endian correction done in assign_stack_local. |
1910 | Get the address of the beginning of the slot. | |
1911 | This is so we can do a big-endian correction unconditionally | |
1912 | below. */ | |
1913 | adjust = inherent_size - total_size; | |
1914 | ||
1915 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]); | |
3bdf5ad1 RK |
1916 | |
1917 | /* Nothing can alias this slot except this pseudo. */ | |
1918 | MEM_ALIAS_SET (x) = new_alias_set (); | |
32131a9c | 1919 | } |
3bdf5ad1 | 1920 | |
32131a9c RK |
1921 | /* Reuse a stack slot if possible. */ |
1922 | else if (spill_stack_slot[from_reg] != 0 | |
1923 | && spill_stack_slot_width[from_reg] >= total_size | |
1924 | && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
1925 | >= inherent_size)) | |
1926 | x = spill_stack_slot[from_reg]; | |
3bdf5ad1 | 1927 | |
32131a9c RK |
1928 | /* Allocate a bigger slot. */ |
1929 | else | |
1930 | { | |
1931 | /* Compute maximum size needed, both for inherent size | |
1932 | and for total size. */ | |
1933 | enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); | |
4f2d3674 | 1934 | rtx stack_slot; |
3bdf5ad1 | 1935 | |
32131a9c RK |
1936 | if (spill_stack_slot[from_reg]) |
1937 | { | |
1938 | if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) | |
1939 | > inherent_size) | |
1940 | mode = GET_MODE (spill_stack_slot[from_reg]); | |
1941 | if (spill_stack_slot_width[from_reg] > total_size) | |
1942 | total_size = spill_stack_slot_width[from_reg]; | |
1943 | } | |
3bdf5ad1 | 1944 | |
32131a9c | 1945 | /* Make a slot with that size. */ |
cabcf079 ILT |
1946 | x = assign_stack_local (mode, total_size, |
1947 | inherent_size == total_size ? 0 : -1); | |
4f2d3674 | 1948 | stack_slot = x; |
3bdf5ad1 RK |
1949 | |
1950 | /* All pseudos mapped to this slot can alias each other. */ | |
1951 | if (spill_stack_slot[from_reg]) | |
1952 | MEM_ALIAS_SET (x) = MEM_ALIAS_SET (spill_stack_slot[from_reg]); | |
1953 | else | |
1954 | MEM_ALIAS_SET (x) = new_alias_set (); | |
1955 | ||
f76b9db2 ILT |
1956 | if (BYTES_BIG_ENDIAN) |
1957 | { | |
1958 | /* Cancel the big-endian correction done in assign_stack_local. | |
1959 | Get the address of the beginning of the slot. | |
1960 | This is so we can do a big-endian correction unconditionally | |
1961 | below. */ | |
1962 | adjust = GET_MODE_SIZE (mode) - total_size; | |
4f2d3674 | 1963 | if (adjust) |
38a448ca RH |
1964 | stack_slot = gen_rtx_MEM (mode_for_size (total_size |
1965 | * BITS_PER_UNIT, | |
1966 | MODE_INT, 1), | |
05d10675 | 1967 | plus_constant (XEXP (x, 0), adjust)); |
f76b9db2 | 1968 | } |
3bdf5ad1 | 1969 | |
4f2d3674 | 1970 | spill_stack_slot[from_reg] = stack_slot; |
32131a9c RK |
1971 | spill_stack_slot_width[from_reg] = total_size; |
1972 | } | |
1973 | ||
32131a9c RK |
1974 | /* On a big endian machine, the "address" of the slot |
1975 | is the address of the low part that fits its inherent mode. */ | |
f76b9db2 | 1976 | if (BYTES_BIG_ENDIAN && inherent_size < total_size) |
32131a9c | 1977 | adjust += (total_size - inherent_size); |
32131a9c RK |
1978 | |
1979 | /* If we have any adjustment to make, or if the stack slot is the | |
1980 | wrong mode, make a new stack slot. */ | |
1981 | if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i])) | |
1982 | { | |
3bdf5ad1 RK |
1983 | rtx new = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]), |
1984 | plus_constant (XEXP (x, 0), adjust)); | |
9ec36da5 | 1985 | |
3bdf5ad1 RK |
1986 | MEM_COPY_ATTRIBUTES (new, x); |
1987 | x = new; | |
32131a9c RK |
1988 | } |
1989 | ||
1990 | /* Save the stack slot for later. */ | |
1991 | reg_equiv_memory_loc[i] = x; | |
1992 | } | |
1993 | } | |
1994 | ||
1995 | /* Mark the slots in regs_ever_live for the hard regs | |
1996 | used by pseudo-reg number REGNO. */ | |
1997 | ||
1998 | void | |
1999 | mark_home_live (regno) | |
2000 | int regno; | |
2001 | { | |
2002 | register int i, lim; | |
770ae6cc | 2003 | |
32131a9c RK |
2004 | i = reg_renumber[regno]; |
2005 | if (i < 0) | |
2006 | return; | |
2007 | lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno)); | |
2008 | while (i < lim) | |
2009 | regs_ever_live[i++] = 1; | |
2010 | } | |
2011 | \f | |
2012 | /* This function handles the tracking of elimination offsets around branches. | |
2013 | ||
2014 | X is a piece of RTL being scanned. | |
2015 | ||
2016 | INSN is the insn that it came from, if any. | |
2017 | ||
2018 | INITIAL_P is non-zero if we are to set the offset to be the initial | |
2019 | offset and zero if we are setting the offset of the label to be the | |
2020 | current offset. */ | |
2021 | ||
2022 | static void | |
2023 | set_label_offsets (x, insn, initial_p) | |
2024 | rtx x; | |
2025 | rtx insn; | |
2026 | int initial_p; | |
2027 | { | |
2028 | enum rtx_code code = GET_CODE (x); | |
2029 | rtx tem; | |
e51712db | 2030 | unsigned int i; |
32131a9c RK |
2031 | struct elim_table *p; |
2032 | ||
2033 | switch (code) | |
2034 | { | |
2035 | case LABEL_REF: | |
8be386d9 RS |
2036 | if (LABEL_REF_NONLOCAL_P (x)) |
2037 | return; | |
2038 | ||
32131a9c RK |
2039 | x = XEXP (x, 0); |
2040 | ||
0f41302f | 2041 | /* ... fall through ... */ |
32131a9c RK |
2042 | |
2043 | case CODE_LABEL: | |
2044 | /* If we know nothing about this label, set the desired offsets. Note | |
2045 | that this sets the offset at a label to be the offset before a label | |
2046 | if we don't know anything about the label. This is not correct for | |
2047 | the label after a BARRIER, but is the best guess we can make. If | |
2048 | we guessed wrong, we will suppress an elimination that might have | |
2049 | been possible had we been able to guess correctly. */ | |
2050 | ||
2051 | if (! offsets_known_at[CODE_LABEL_NUMBER (x)]) | |
2052 | { | |
2053 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
2054 | offsets_at[CODE_LABEL_NUMBER (x)][i] | |
2055 | = (initial_p ? reg_eliminate[i].initial_offset | |
2056 | : reg_eliminate[i].offset); | |
2057 | offsets_known_at[CODE_LABEL_NUMBER (x)] = 1; | |
2058 | } | |
2059 | ||
2060 | /* Otherwise, if this is the definition of a label and it is | |
d45cf215 | 2061 | preceded by a BARRIER, set our offsets to the known offset of |
32131a9c RK |
2062 | that label. */ |
2063 | ||
2064 | else if (x == insn | |
2065 | && (tem = prev_nonnote_insn (insn)) != 0 | |
2066 | && GET_CODE (tem) == BARRIER) | |
1f3b1e1a | 2067 | set_offsets_for_label (insn); |
32131a9c RK |
2068 | else |
2069 | /* If neither of the above cases is true, compare each offset | |
2070 | with those previously recorded and suppress any eliminations | |
2071 | where the offsets disagree. */ | |
a8fdc208 | 2072 | |
32131a9c RK |
2073 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) |
2074 | if (offsets_at[CODE_LABEL_NUMBER (x)][i] | |
2075 | != (initial_p ? reg_eliminate[i].initial_offset | |
2076 | : reg_eliminate[i].offset)) | |
2077 | reg_eliminate[i].can_eliminate = 0; | |
2078 | ||
2079 | return; | |
2080 | ||
2081 | case JUMP_INSN: | |
2082 | set_label_offsets (PATTERN (insn), insn, initial_p); | |
2083 | ||
0f41302f | 2084 | /* ... fall through ... */ |
32131a9c RK |
2085 | |
2086 | case INSN: | |
2087 | case CALL_INSN: | |
2088 | /* Any labels mentioned in REG_LABEL notes can be branched to indirectly | |
2089 | and hence must have all eliminations at their initial offsets. */ | |
2090 | for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) | |
2091 | if (REG_NOTE_KIND (tem) == REG_LABEL) | |
2092 | set_label_offsets (XEXP (tem, 0), insn, 1); | |
2093 | return; | |
2094 | ||
2095 | case ADDR_VEC: | |
2096 | case ADDR_DIFF_VEC: | |
2097 | /* Each of the labels in the address vector must be at their initial | |
38e01259 | 2098 | offsets. We want the first field for ADDR_VEC and the second |
32131a9c RK |
2099 | field for ADDR_DIFF_VEC. */ |
2100 | ||
e51712db | 2101 | for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++) |
32131a9c RK |
2102 | set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), |
2103 | insn, initial_p); | |
2104 | return; | |
2105 | ||
2106 | case SET: | |
2107 | /* We only care about setting PC. If the source is not RETURN, | |
2108 | IF_THEN_ELSE, or a label, disable any eliminations not at | |
2109 | their initial offsets. Similarly if any arm of the IF_THEN_ELSE | |
2110 | isn't one of those possibilities. For branches to a label, | |
2111 | call ourselves recursively. | |
2112 | ||
2113 | Note that this can disable elimination unnecessarily when we have | |
2114 | a non-local goto since it will look like a non-constant jump to | |
2115 | someplace in the current function. This isn't a significant | |
2116 | problem since such jumps will normally be when all elimination | |
2117 | pairs are back to their initial offsets. */ | |
2118 | ||
2119 | if (SET_DEST (x) != pc_rtx) | |
2120 | return; | |
2121 | ||
2122 | switch (GET_CODE (SET_SRC (x))) | |
2123 | { | |
2124 | case PC: | |
2125 | case RETURN: | |
2126 | return; | |
2127 | ||
2128 | case LABEL_REF: | |
2129 | set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p); | |
2130 | return; | |
2131 | ||
2132 | case IF_THEN_ELSE: | |
2133 | tem = XEXP (SET_SRC (x), 1); | |
2134 | if (GET_CODE (tem) == LABEL_REF) | |
2135 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2136 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2137 | break; | |
2138 | ||
2139 | tem = XEXP (SET_SRC (x), 2); | |
2140 | if (GET_CODE (tem) == LABEL_REF) | |
2141 | set_label_offsets (XEXP (tem, 0), insn, initial_p); | |
2142 | else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) | |
2143 | break; | |
2144 | return; | |
e9a25f70 JL |
2145 | |
2146 | default: | |
2147 | break; | |
32131a9c RK |
2148 | } |
2149 | ||
2150 | /* If we reach here, all eliminations must be at their initial | |
2151 | offset because we are doing a jump to a variable address. */ | |
2152 | for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) | |
2153 | if (p->offset != p->initial_offset) | |
2154 | p->can_eliminate = 0; | |
e9a25f70 | 2155 | break; |
05d10675 | 2156 | |
e9a25f70 JL |
2157 | default: |
2158 | break; | |
32131a9c RK |
2159 | } |
2160 | } | |
2161 | \f | |
a8fdc208 | 2162 | /* Scan X and replace any eliminable registers (such as fp) with a |
32131a9c RK |
2163 | replacement (such as sp), plus an offset. |
2164 | ||
2165 | MEM_MODE is the mode of an enclosing MEM. We need this to know how | |
2166 | much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a | |
2167 | MEM, we are allowed to replace a sum of a register and the constant zero | |
2168 | with the register, which we cannot do outside a MEM. In addition, we need | |
2169 | to record the fact that a register is referenced outside a MEM. | |
2170 | ||
ff32812a | 2171 | If INSN is an insn, it is the insn containing X. If we replace a REG |
32131a9c RK |
2172 | in a SET_DEST with an equivalent MEM and INSN is non-zero, write a |
2173 | CLOBBER of the pseudo after INSN so find_equiv_regs will know that | |
38e01259 | 2174 | the REG is being modified. |
32131a9c | 2175 | |
ff32812a RS |
2176 | Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST). |
2177 | That's used when we eliminate in expressions stored in notes. | |
2178 | This means, do not set ref_outside_mem even if the reference | |
2179 | is outside of MEMs. | |
2180 | ||
32131a9c RK |
2181 | REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had |
2182 | replacements done assuming all offsets are at their initial values. If | |
2183 | they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we | |
2184 | encounter, return the actual location so that find_reloads will do | |
2185 | the proper thing. */ | |
2186 | ||
2187 | rtx | |
1914f5da | 2188 | eliminate_regs (x, mem_mode, insn) |
32131a9c RK |
2189 | rtx x; |
2190 | enum machine_mode mem_mode; | |
2191 | rtx insn; | |
2192 | { | |
2193 | enum rtx_code code = GET_CODE (x); | |
2194 | struct elim_table *ep; | |
2195 | int regno; | |
2196 | rtx new; | |
2197 | int i, j; | |
6f7d635c | 2198 | const char *fmt; |
32131a9c RK |
2199 | int copied = 0; |
2200 | ||
d6633f01 NS |
2201 | if (! current_function_decl) |
2202 | return x; | |
9969bb2c | 2203 | |
32131a9c RK |
2204 | switch (code) |
2205 | { | |
2206 | case CONST_INT: | |
2207 | case CONST_DOUBLE: | |
2208 | case CONST: | |
2209 | case SYMBOL_REF: | |
2210 | case CODE_LABEL: | |
2211 | case PC: | |
2212 | case CC0: | |
2213 | case ASM_INPUT: | |
2214 | case ADDR_VEC: | |
2215 | case ADDR_DIFF_VEC: | |
2216 | case RETURN: | |
2217 | return x; | |
2218 | ||
e9a25f70 JL |
2219 | case ADDRESSOF: |
2220 | /* This is only for the benefit of the debugging backends, which call | |
2221 | eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are | |
2222 | removed after CSE. */ | |
1914f5da | 2223 | new = eliminate_regs (XEXP (x, 0), 0, insn); |
e9a25f70 JL |
2224 | if (GET_CODE (new) == MEM) |
2225 | return XEXP (new, 0); | |
2226 | return x; | |
2227 | ||
32131a9c RK |
2228 | case REG: |
2229 | regno = REGNO (x); | |
2230 | ||
2231 | /* First handle the case where we encounter a bare register that | |
2232 | is eliminable. Replace it with a PLUS. */ | |
2233 | if (regno < FIRST_PSEUDO_REGISTER) | |
2234 | { | |
2235 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2236 | ep++) | |
2237 | if (ep->from_rtx == x && ep->can_eliminate) | |
dfac187e | 2238 | return plus_constant (ep->to_rtx, ep->previous_offset); |
32131a9c RK |
2239 | |
2240 | } | |
2b49ee39 R |
2241 | else if (reg_renumber[regno] < 0 && reg_equiv_constant |
2242 | && reg_equiv_constant[regno] | |
2243 | && ! CONSTANT_P (reg_equiv_constant[regno])) | |
2244 | return eliminate_regs (copy_rtx (reg_equiv_constant[regno]), | |
2245 | mem_mode, insn); | |
32131a9c RK |
2246 | return x; |
2247 | ||
c5c76735 JL |
2248 | /* You might think handling MINUS in a manner similar to PLUS is a |
2249 | good idea. It is not. It has been tried multiple times and every | |
2250 | time the change has had to have been reverted. | |
2251 | ||
2252 | Other parts of reload know a PLUS is special (gen_reload for example) | |
2253 | and require special code to handle code a reloaded PLUS operand. | |
2254 | ||
2255 | Also consider backends where the flags register is clobbered by a | |
2256 | MINUS, but we can emit a PLUS that does not clobber flags (ia32, | |
2257 | lea instruction comes to mind). If we try to reload a MINUS, we | |
2258 | may kill the flags register that was holding a useful value. | |
2259 | ||
2260 | So, please before trying to handle MINUS, consider reload as a | |
2261 | whole instead of this little section as well as the backend issues. */ | |
32131a9c RK |
2262 | case PLUS: |
2263 | /* If this is the sum of an eliminable register and a constant, rework | |
2264 | the sum. */ | |
2265 | if (GET_CODE (XEXP (x, 0)) == REG | |
2266 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2267 | && CONSTANT_P (XEXP (x, 1))) | |
2268 | { | |
2269 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2270 | ep++) | |
2271 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2272 | { | |
32131a9c RK |
2273 | /* The only time we want to replace a PLUS with a REG (this |
2274 | occurs when the constant operand of the PLUS is the negative | |
2275 | of the offset) is when we are inside a MEM. We won't want | |
2276 | to do so at other times because that would change the | |
2277 | structure of the insn in a way that reload can't handle. | |
2278 | We special-case the commonest situation in | |
2279 | eliminate_regs_in_insn, so just replace a PLUS with a | |
2280 | PLUS here, unless inside a MEM. */ | |
a23b64d5 | 2281 | if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT |
32131a9c RK |
2282 | && INTVAL (XEXP (x, 1)) == - ep->previous_offset) |
2283 | return ep->to_rtx; | |
2284 | else | |
38a448ca RH |
2285 | return gen_rtx_PLUS (Pmode, ep->to_rtx, |
2286 | plus_constant (XEXP (x, 1), | |
2287 | ep->previous_offset)); | |
32131a9c RK |
2288 | } |
2289 | ||
2290 | /* If the register is not eliminable, we are done since the other | |
2291 | operand is a constant. */ | |
2292 | return x; | |
2293 | } | |
2294 | ||
2295 | /* If this is part of an address, we want to bring any constant to the | |
2296 | outermost PLUS. We will do this by doing register replacement in | |
2297 | our operands and seeing if a constant shows up in one of them. | |
2298 | ||
dfac187e BS |
2299 | Note that there is no risk of modifying the structure of the insn, |
2300 | since we only get called for its operands, thus we are either | |
2301 | modifying the address inside a MEM, or something like an address | |
2302 | operand of a load-address insn. */ | |
32131a9c RK |
2303 | |
2304 | { | |
1914f5da RH |
2305 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
2306 | rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn); | |
32131a9c RK |
2307 | |
2308 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
2309 | { | |
2310 | /* If one side is a PLUS and the other side is a pseudo that | |
a8fdc208 | 2311 | didn't get a hard register but has a reg_equiv_constant, |
32131a9c RK |
2312 | we must replace the constant here since it may no longer |
2313 | be in the position of any operand. */ | |
2314 | if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG | |
2315 | && REGNO (new1) >= FIRST_PSEUDO_REGISTER | |
2316 | && reg_renumber[REGNO (new1)] < 0 | |
2317 | && reg_equiv_constant != 0 | |
2318 | && reg_equiv_constant[REGNO (new1)] != 0) | |
2319 | new1 = reg_equiv_constant[REGNO (new1)]; | |
2320 | else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG | |
2321 | && REGNO (new0) >= FIRST_PSEUDO_REGISTER | |
2322 | && reg_renumber[REGNO (new0)] < 0 | |
2323 | && reg_equiv_constant[REGNO (new0)] != 0) | |
2324 | new0 = reg_equiv_constant[REGNO (new0)]; | |
2325 | ||
2326 | new = form_sum (new0, new1); | |
2327 | ||
2328 | /* As above, if we are not inside a MEM we do not want to | |
2329 | turn a PLUS into something else. We might try to do so here | |
2330 | for an addition of 0 if we aren't optimizing. */ | |
2331 | if (! mem_mode && GET_CODE (new) != PLUS) | |
38a448ca | 2332 | return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx); |
32131a9c RK |
2333 | else |
2334 | return new; | |
2335 | } | |
2336 | } | |
2337 | return x; | |
2338 | ||
981c7390 | 2339 | case MULT: |
05d10675 | 2340 | /* If this is the product of an eliminable register and a |
981c7390 RK |
2341 | constant, apply the distribute law and move the constant out |
2342 | so that we have (plus (mult ..) ..). This is needed in order | |
9faa82d8 | 2343 | to keep load-address insns valid. This case is pathological. |
981c7390 RK |
2344 | We ignore the possibility of overflow here. */ |
2345 | if (GET_CODE (XEXP (x, 0)) == REG | |
2346 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
2347 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2348 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2349 | ep++) | |
2350 | if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) | |
2351 | { | |
2352 | if (! mem_mode | |
2353 | /* Refs inside notes don't count for this purpose. */ | |
2354 | && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST | |
2355 | || GET_CODE (insn) == INSN_LIST))) | |
2356 | ep->ref_outside_mem = 1; | |
2357 | ||
2358 | return | |
38a448ca | 2359 | plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)), |
981c7390 RK |
2360 | ep->previous_offset * INTVAL (XEXP (x, 1))); |
2361 | } | |
32131a9c | 2362 | |
0f41302f | 2363 | /* ... fall through ... */ |
32131a9c | 2364 | |
32131a9c RK |
2365 | case CALL: |
2366 | case COMPARE: | |
c5c76735 | 2367 | /* See comments before PLUS about handling MINUS. */ |
930aeef3 | 2368 | case MINUS: |
32131a9c RK |
2369 | case DIV: case UDIV: |
2370 | case MOD: case UMOD: | |
2371 | case AND: case IOR: case XOR: | |
45620ed4 RK |
2372 | case ROTATERT: case ROTATE: |
2373 | case ASHIFTRT: case LSHIFTRT: case ASHIFT: | |
32131a9c RK |
2374 | case NE: case EQ: |
2375 | case GE: case GT: case GEU: case GTU: | |
2376 | case LE: case LT: case LEU: case LTU: | |
2377 | { | |
1914f5da | 2378 | rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
fb3821f7 | 2379 | rtx new1 |
1914f5da | 2380 | = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0; |
32131a9c RK |
2381 | |
2382 | if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) | |
38a448ca | 2383 | return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); |
32131a9c RK |
2384 | } |
2385 | return x; | |
2386 | ||
981c7390 RK |
2387 | case EXPR_LIST: |
2388 | /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ | |
2389 | if (XEXP (x, 0)) | |
2390 | { | |
1914f5da | 2391 | new = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
981c7390 | 2392 | if (new != XEXP (x, 0)) |
13bb79d4 R |
2393 | { |
2394 | /* If this is a REG_DEAD note, it is not valid anymore. | |
2395 | Using the eliminated version could result in creating a | |
2396 | REG_DEAD note for the stack or frame pointer. */ | |
2397 | if (GET_MODE (x) == REG_DEAD) | |
2398 | return (XEXP (x, 1) | |
2399 | ? eliminate_regs (XEXP (x, 1), mem_mode, insn) | |
2400 | : NULL_RTX); | |
2401 | ||
2402 | x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1)); | |
2403 | } | |
981c7390 RK |
2404 | } |
2405 | ||
0f41302f | 2406 | /* ... fall through ... */ |
981c7390 RK |
2407 | |
2408 | case INSN_LIST: | |
2409 | /* Now do eliminations in the rest of the chain. If this was | |
2410 | an EXPR_LIST, this might result in allocating more memory than is | |
2411 | strictly needed, but it simplifies the code. */ | |
2412 | if (XEXP (x, 1)) | |
2413 | { | |
1914f5da | 2414 | new = eliminate_regs (XEXP (x, 1), mem_mode, insn); |
981c7390 | 2415 | if (new != XEXP (x, 1)) |
38a448ca | 2416 | return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new); |
981c7390 RK |
2417 | } |
2418 | return x; | |
2419 | ||
32131a9c RK |
2420 | case PRE_INC: |
2421 | case POST_INC: | |
2422 | case PRE_DEC: | |
2423 | case POST_DEC: | |
32131a9c RK |
2424 | case STRICT_LOW_PART: |
2425 | case NEG: case NOT: | |
2426 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2427 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2428 | case FLOAT: case FIX: | |
2429 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2430 | case ABS: | |
2431 | case SQRT: | |
2432 | case FFS: | |
1914f5da | 2433 | new = eliminate_regs (XEXP (x, 0), mem_mode, insn); |
32131a9c | 2434 | if (new != XEXP (x, 0)) |
38a448ca | 2435 | return gen_rtx_fmt_e (code, GET_MODE (x), new); |
32131a9c RK |
2436 | return x; |
2437 | ||
2438 | case SUBREG: | |
2439 | /* Similar to above processing, but preserve SUBREG_WORD. | |
2440 | Convert (subreg (mem)) to (mem) if not paradoxical. | |
2441 | Also, if we have a non-paradoxical (subreg (pseudo)) and the | |
2442 | pseudo didn't get a hard reg, we must replace this with the | |
2443 | eliminated version of the memory location because push_reloads | |
2444 | may do the replacement in certain circumstances. */ | |
2445 | if (GET_CODE (SUBREG_REG (x)) == REG | |
2446 | && (GET_MODE_SIZE (GET_MODE (x)) | |
2447 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2448 | && reg_equiv_memory_loc != 0 | |
2449 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2450 | { | |
cb2afeb3 | 2451 | new = SUBREG_REG (x); |
32131a9c RK |
2452 | } |
2453 | else | |
1914f5da | 2454 | new = eliminate_regs (SUBREG_REG (x), mem_mode, insn); |
32131a9c RK |
2455 | |
2456 | if (new != XEXP (x, 0)) | |
2457 | { | |
29ae5012 RK |
2458 | int x_size = GET_MODE_SIZE (GET_MODE (x)); |
2459 | int new_size = GET_MODE_SIZE (GET_MODE (new)); | |
2460 | ||
1914f5da | 2461 | if (GET_CODE (new) == MEM |
6d49a073 | 2462 | && ((x_size < new_size |
1914f5da | 2463 | #ifdef WORD_REGISTER_OPERATIONS |
6d49a073 JW |
2464 | /* On these machines, combine can create rtl of the form |
2465 | (set (subreg:m1 (reg:m2 R) 0) ...) | |
05d10675 | 2466 | where m1 < m2, and expects something interesting to |
6d49a073 JW |
2467 | happen to the entire word. Moreover, it will use the |
2468 | (reg:m2 R) later, expecting all bits to be preserved. | |
05d10675 | 2469 | So if the number of words is the same, preserve the |
6d49a073 JW |
2470 | subreg so that push_reloads can see it. */ |
2471 | && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD) | |
1914f5da | 2472 | #endif |
6d49a073 JW |
2473 | ) |
2474 | || (x_size == new_size)) | |
1914f5da | 2475 | ) |
32131a9c RK |
2476 | { |
2477 | int offset = SUBREG_WORD (x) * UNITS_PER_WORD; | |
2478 | enum machine_mode mode = GET_MODE (x); | |
2479 | ||
f76b9db2 ILT |
2480 | if (BYTES_BIG_ENDIAN) |
2481 | offset += (MIN (UNITS_PER_WORD, | |
2482 | GET_MODE_SIZE (GET_MODE (new))) | |
2483 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))); | |
32131a9c RK |
2484 | |
2485 | PUT_MODE (new, mode); | |
2486 | XEXP (new, 0) = plus_constant (XEXP (new, 0), offset); | |
2487 | return new; | |
2488 | } | |
2489 | else | |
38a448ca | 2490 | return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x)); |
32131a9c RK |
2491 | } |
2492 | ||
2493 | return x; | |
2494 | ||
32131a9c | 2495 | case MEM: |
e9a25f70 JL |
2496 | /* This is only for the benefit of the debugging backends, which call |
2497 | eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are | |
2498 | removed after CSE. */ | |
2499 | if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) | |
1914f5da | 2500 | return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn); |
e9a25f70 | 2501 | |
32131a9c RK |
2502 | /* Our only special processing is to pass the mode of the MEM to our |
2503 | recursive call and copy the flags. While we are here, handle this | |
2504 | case more efficiently. */ | |
1914f5da | 2505 | new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn); |
32131a9c RK |
2506 | if (new != XEXP (x, 0)) |
2507 | { | |
38a448ca | 2508 | new = gen_rtx_MEM (GET_MODE (x), new); |
3bdf5ad1 | 2509 | MEM_COPY_ATTRIBUTES (new, x); |
32131a9c RK |
2510 | return new; |
2511 | } | |
2512 | else | |
2513 | return x; | |
05d10675 | 2514 | |
dfac187e BS |
2515 | case USE: |
2516 | case CLOBBER: | |
2517 | case ASM_OPERANDS: | |
2518 | case SET: | |
2519 | abort (); | |
2520 | ||
e9a25f70 JL |
2521 | default: |
2522 | break; | |
32131a9c RK |
2523 | } |
2524 | ||
2525 | /* Process each of our operands recursively. If any have changed, make a | |
2526 | copy of the rtx. */ | |
2527 | fmt = GET_RTX_FORMAT (code); | |
2528 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2529 | { | |
2530 | if (*fmt == 'e') | |
2531 | { | |
1914f5da | 2532 | new = eliminate_regs (XEXP (x, i), mem_mode, insn); |
32131a9c RK |
2533 | if (new != XEXP (x, i) && ! copied) |
2534 | { | |
2535 | rtx new_x = rtx_alloc (code); | |
4c9a05bc RK |
2536 | bcopy ((char *) x, (char *) new_x, |
2537 | (sizeof (*new_x) - sizeof (new_x->fld) | |
2538 | + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code))); | |
32131a9c RK |
2539 | x = new_x; |
2540 | copied = 1; | |
2541 | } | |
2542 | XEXP (x, i) = new; | |
2543 | } | |
2544 | else if (*fmt == 'E') | |
2545 | { | |
2546 | int copied_vec = 0; | |
2547 | for (j = 0; j < XVECLEN (x, i); j++) | |
2548 | { | |
1914f5da | 2549 | new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn); |
32131a9c RK |
2550 | if (new != XVECEXP (x, i, j) && ! copied_vec) |
2551 | { | |
8f985ec4 ZW |
2552 | rtvec new_v = gen_rtvec_v (XVECLEN (x, i), |
2553 | XVEC (x, i)->elem); | |
32131a9c RK |
2554 | if (! copied) |
2555 | { | |
2556 | rtx new_x = rtx_alloc (code); | |
4c9a05bc RK |
2557 | bcopy ((char *) x, (char *) new_x, |
2558 | (sizeof (*new_x) - sizeof (new_x->fld) | |
2559 | + (sizeof (new_x->fld[0]) | |
2560 | * GET_RTX_LENGTH (code)))); | |
32131a9c RK |
2561 | x = new_x; |
2562 | copied = 1; | |
2563 | } | |
2564 | XVEC (x, i) = new_v; | |
2565 | copied_vec = 1; | |
2566 | } | |
2567 | XVECEXP (x, i, j) = new; | |
2568 | } | |
2569 | } | |
2570 | } | |
2571 | ||
2572 | return x; | |
2573 | } | |
dfac187e BS |
2574 | |
2575 | /* Scan rtx X for modifications of elimination target registers. Update | |
2576 | the table of eliminables to reflect the changed state. MEM_MODE is | |
2577 | the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */ | |
2578 | ||
2579 | static void | |
2580 | elimination_effects (x, mem_mode) | |
2581 | rtx x; | |
2582 | enum machine_mode mem_mode; | |
2583 | ||
2584 | { | |
2585 | enum rtx_code code = GET_CODE (x); | |
2586 | struct elim_table *ep; | |
2587 | int regno; | |
2588 | int i, j; | |
2589 | const char *fmt; | |
2590 | ||
2591 | switch (code) | |
2592 | { | |
2593 | case CONST_INT: | |
2594 | case CONST_DOUBLE: | |
2595 | case CONST: | |
2596 | case SYMBOL_REF: | |
2597 | case CODE_LABEL: | |
2598 | case PC: | |
2599 | case CC0: | |
2600 | case ASM_INPUT: | |
2601 | case ADDR_VEC: | |
2602 | case ADDR_DIFF_VEC: | |
2603 | case RETURN: | |
2604 | return; | |
2605 | ||
2606 | case ADDRESSOF: | |
2607 | abort (); | |
2608 | ||
2609 | case REG: | |
2610 | regno = REGNO (x); | |
2611 | ||
2612 | /* First handle the case where we encounter a bare register that | |
2613 | is eliminable. Replace it with a PLUS. */ | |
2614 | if (regno < FIRST_PSEUDO_REGISTER) | |
2615 | { | |
2616 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2617 | ep++) | |
2618 | if (ep->from_rtx == x && ep->can_eliminate) | |
2619 | { | |
2620 | if (! mem_mode) | |
2621 | ep->ref_outside_mem = 1; | |
2622 | return; | |
2623 | } | |
2624 | ||
2625 | } | |
2626 | else if (reg_renumber[regno] < 0 && reg_equiv_constant | |
2627 | && reg_equiv_constant[regno] | |
2628 | && ! CONSTANT_P (reg_equiv_constant[regno])) | |
2629 | elimination_effects (reg_equiv_constant[regno], mem_mode); | |
2630 | return; | |
2631 | ||
2632 | case PRE_INC: | |
2633 | case POST_INC: | |
2634 | case PRE_DEC: | |
2635 | case POST_DEC: | |
2636 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2637 | if (ep->to_rtx == XEXP (x, 0)) | |
2638 | { | |
2639 | int size = GET_MODE_SIZE (mem_mode); | |
2640 | ||
2641 | /* If more bytes than MEM_MODE are pushed, account for them. */ | |
2642 | #ifdef PUSH_ROUNDING | |
2643 | if (ep->to_rtx == stack_pointer_rtx) | |
2644 | size = PUSH_ROUNDING (size); | |
2645 | #endif | |
2646 | if (code == PRE_DEC || code == POST_DEC) | |
2647 | ep->offset += size; | |
2648 | else | |
2649 | ep->offset -= size; | |
2650 | } | |
2651 | ||
2652 | /* Fall through to generic unary operation case. */ | |
2653 | case STRICT_LOW_PART: | |
2654 | case NEG: case NOT: | |
2655 | case SIGN_EXTEND: case ZERO_EXTEND: | |
2656 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: | |
2657 | case FLOAT: case FIX: | |
2658 | case UNSIGNED_FIX: case UNSIGNED_FLOAT: | |
2659 | case ABS: | |
2660 | case SQRT: | |
2661 | case FFS: | |
2662 | elimination_effects (XEXP (x, 0), mem_mode); | |
2663 | return; | |
2664 | ||
2665 | case SUBREG: | |
2666 | if (GET_CODE (SUBREG_REG (x)) == REG | |
2667 | && (GET_MODE_SIZE (GET_MODE (x)) | |
2668 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
2669 | && reg_equiv_memory_loc != 0 | |
2670 | && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) | |
2671 | return; | |
2672 | ||
2673 | elimination_effects (SUBREG_REG (x), mem_mode); | |
2674 | return; | |
2675 | ||
2676 | case USE: | |
2677 | /* If using a register that is the source of an eliminate we still | |
2678 | think can be performed, note it cannot be performed since we don't | |
2679 | know how this register is used. */ | |
2680 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2681 | if (ep->from_rtx == XEXP (x, 0)) | |
2682 | ep->can_eliminate = 0; | |
2683 | ||
2684 | elimination_effects (XEXP (x, 0), mem_mode); | |
2685 | return; | |
2686 | ||
2687 | case CLOBBER: | |
2688 | /* If clobbering a register that is the replacement register for an | |
2689 | elimination we still think can be performed, note that it cannot | |
2690 | be performed. Otherwise, we need not be concerned about it. */ | |
2691 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2692 | if (ep->to_rtx == XEXP (x, 0)) | |
2693 | ep->can_eliminate = 0; | |
2694 | ||
2695 | elimination_effects (XEXP (x, 0), mem_mode); | |
2696 | return; | |
2697 | ||
2698 | case SET: | |
2699 | /* Check for setting a register that we know about. */ | |
2700 | if (GET_CODE (SET_DEST (x)) == REG) | |
2701 | { | |
2702 | /* See if this is setting the replacement register for an | |
2703 | elimination. | |
2704 | ||
2705 | If DEST is the hard frame pointer, we do nothing because we | |
2706 | assume that all assignments to the frame pointer are for | |
2707 | non-local gotos and are being done at a time when they are valid | |
2708 | and do not disturb anything else. Some machines want to | |
2709 | eliminate a fake argument pointer (or even a fake frame pointer) | |
2710 | with either the real frame or the stack pointer. Assignments to | |
2711 | the hard frame pointer must not prevent this elimination. */ | |
2712 | ||
2713 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
2714 | ep++) | |
2715 | if (ep->to_rtx == SET_DEST (x) | |
2716 | && SET_DEST (x) != hard_frame_pointer_rtx) | |
2717 | { | |
2718 | /* If it is being incremented, adjust the offset. Otherwise, | |
2719 | this elimination can't be done. */ | |
2720 | rtx src = SET_SRC (x); | |
2721 | ||
2722 | if (GET_CODE (src) == PLUS | |
2723 | && XEXP (src, 0) == SET_DEST (x) | |
2724 | && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
2725 | ep->offset -= INTVAL (XEXP (src, 1)); | |
2726 | else | |
2727 | ep->can_eliminate = 0; | |
2728 | } | |
2729 | } | |
2730 | ||
2731 | elimination_effects (SET_DEST (x), 0); | |
2732 | elimination_effects (SET_SRC (x), 0); | |
2733 | return; | |
2734 | ||
2735 | case MEM: | |
2736 | if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) | |
2737 | abort (); | |
2738 | ||
2739 | /* Our only special processing is to pass the mode of the MEM to our | |
2740 | recursive call. */ | |
2741 | elimination_effects (XEXP (x, 0), GET_MODE (x)); | |
2742 | return; | |
2743 | ||
2744 | default: | |
2745 | break; | |
2746 | } | |
2747 | ||
2748 | fmt = GET_RTX_FORMAT (code); | |
2749 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2750 | { | |
2751 | if (*fmt == 'e') | |
2752 | elimination_effects (XEXP (x, i), mem_mode); | |
2753 | else if (*fmt == 'E') | |
2754 | for (j = 0; j < XVECLEN (x, i); j++) | |
2755 | elimination_effects (XVECEXP (x, i, j), mem_mode); | |
2756 | } | |
2757 | } | |
2758 | ||
2759 | /* Descend through rtx X and verify that no references to eliminable registers | |
2760 | remain. If any do remain, mark the involved register as not | |
2761 | eliminable. */ | |
1d813780 | 2762 | |
dfac187e BS |
2763 | static void |
2764 | check_eliminable_occurrences (x) | |
2765 | rtx x; | |
2766 | { | |
2767 | const char *fmt; | |
2768 | int i; | |
2769 | enum rtx_code code; | |
2770 | ||
2771 | if (x == 0) | |
2772 | return; | |
2773 | ||
2774 | code = GET_CODE (x); | |
2775 | ||
2776 | if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER) | |
2777 | { | |
2778 | struct elim_table *ep; | |
2779 | ||
2780 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
2781 | if (ep->from_rtx == x && ep->can_eliminate) | |
2782 | ep->can_eliminate = 0; | |
2783 | return; | |
2784 | } | |
2785 | ||
2786 | fmt = GET_RTX_FORMAT (code); | |
2787 | for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) | |
2788 | { | |
2789 | if (*fmt == 'e') | |
2790 | check_eliminable_occurrences (XEXP (x, i)); | |
2791 | else if (*fmt == 'E') | |
2792 | { | |
2793 | int j; | |
2794 | for (j = 0; j < XVECLEN (x, i); j++) | |
2795 | check_eliminable_occurrences (XVECEXP (x, i, j)); | |
2796 | } | |
2797 | } | |
2798 | } | |
32131a9c RK |
2799 | \f |
2800 | /* Scan INSN and eliminate all eliminable registers in it. | |
2801 | ||
2802 | If REPLACE is nonzero, do the replacement destructively. Also | |
2803 | delete the insn as dead it if it is setting an eliminable register. | |
2804 | ||
2805 | If REPLACE is zero, do all our allocations in reload_obstack. | |
2806 | ||
2807 | If no eliminations were done and this insn doesn't require any elimination | |
2808 | processing (these are not identical conditions: it might be updating sp, | |
2809 | but not referencing fp; this needs to be seen during reload_as_needed so | |
2810 | that the offset between fp and sp can be taken into consideration), zero | |
2811 | is returned. Otherwise, 1 is returned. */ | |
2812 | ||
2813 | static int | |
2814 | eliminate_regs_in_insn (insn, replace) | |
2815 | rtx insn; | |
2816 | int replace; | |
2817 | { | |
dfac187e | 2818 | int icode = recog_memoized (insn); |
32131a9c | 2819 | rtx old_body = PATTERN (insn); |
dfac187e | 2820 | int insn_is_asm = asm_noperands (old_body) >= 0; |
774672d2 | 2821 | rtx old_set = single_set (insn); |
32131a9c RK |
2822 | rtx new_body; |
2823 | int val = 0; | |
dfac187e BS |
2824 | int i, any_changes; |
2825 | rtx substed_operand[MAX_RECOG_OPERANDS]; | |
2826 | rtx orig_operand[MAX_RECOG_OPERANDS]; | |
32131a9c RK |
2827 | struct elim_table *ep; |
2828 | ||
dfac187e BS |
2829 | if (! insn_is_asm && icode < 0) |
2830 | { | |
2831 | if (GET_CODE (PATTERN (insn)) == USE | |
2832 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
2833 | || GET_CODE (PATTERN (insn)) == ADDR_VEC | |
2834 | || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC | |
2835 | || GET_CODE (PATTERN (insn)) == ASM_INPUT) | |
2836 | return 0; | |
2837 | abort (); | |
2838 | } | |
2839 | ||
32131a9c RK |
2840 | if (! replace) |
2841 | push_obstacks (&reload_obstack, &reload_obstack); | |
2842 | ||
774672d2 RK |
2843 | if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG |
2844 | && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) | |
32131a9c RK |
2845 | { |
2846 | /* Check for setting an eliminable register. */ | |
2847 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
774672d2 | 2848 | if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) |
32131a9c | 2849 | { |
dd1eab0a RK |
2850 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
2851 | /* If this is setting the frame pointer register to the | |
2852 | hardware frame pointer register and this is an elimination | |
2853 | that will be done (tested above), this insn is really | |
2854 | adjusting the frame pointer downward to compensate for | |
2855 | the adjustment done before a nonlocal goto. */ | |
2856 | if (ep->from == FRAME_POINTER_REGNUM | |
2857 | && ep->to == HARD_FRAME_POINTER_REGNUM) | |
2858 | { | |
2859 | rtx src = SET_SRC (old_set); | |
973838fd | 2860 | int offset = 0, ok = 0; |
8026ebba | 2861 | rtx prev_insn, prev_set; |
dd1eab0a RK |
2862 | |
2863 | if (src == ep->to_rtx) | |
2864 | offset = 0, ok = 1; | |
2865 | else if (GET_CODE (src) == PLUS | |
bb22893c JW |
2866 | && GET_CODE (XEXP (src, 0)) == CONST_INT |
2867 | && XEXP (src, 1) == ep->to_rtx) | |
dd1eab0a | 2868 | offset = INTVAL (XEXP (src, 0)), ok = 1; |
bb22893c JW |
2869 | else if (GET_CODE (src) == PLUS |
2870 | && GET_CODE (XEXP (src, 1)) == CONST_INT | |
2871 | && XEXP (src, 0) == ep->to_rtx) | |
2872 | offset = INTVAL (XEXP (src, 1)), ok = 1; | |
8026ebba ILT |
2873 | else if ((prev_insn = prev_nonnote_insn (insn)) != 0 |
2874 | && (prev_set = single_set (prev_insn)) != 0 | |
2875 | && rtx_equal_p (SET_DEST (prev_set), src)) | |
2876 | { | |
2877 | src = SET_SRC (prev_set); | |
2878 | if (src == ep->to_rtx) | |
2879 | offset = 0, ok = 1; | |
2880 | else if (GET_CODE (src) == PLUS | |
2881 | && GET_CODE (XEXP (src, 0)) == CONST_INT | |
2882 | && XEXP (src, 1) == ep->to_rtx) | |
2883 | offset = INTVAL (XEXP (src, 0)), ok = 1; | |
2884 | else if (GET_CODE (src) == PLUS | |
2885 | && GET_CODE (XEXP (src, 1)) == CONST_INT | |
2886 | && XEXP (src, 0) == ep->to_rtx) | |
2887 | offset = INTVAL (XEXP (src, 1)), ok = 1; | |
2888 | } | |
dd1eab0a RK |
2889 | |
2890 | if (ok) | |
2891 | { | |
2892 | if (replace) | |
2893 | { | |
2894 | rtx src | |
2895 | = plus_constant (ep->to_rtx, offset - ep->offset); | |
2896 | ||
2897 | /* First see if this insn remains valid when we | |
2898 | make the change. If not, keep the INSN_CODE | |
2899 | the same and let reload fit it up. */ | |
2900 | validate_change (insn, &SET_SRC (old_set), src, 1); | |
2901 | validate_change (insn, &SET_DEST (old_set), | |
2902 | ep->to_rtx, 1); | |
2903 | if (! apply_change_group ()) | |
2904 | { | |
2905 | SET_SRC (old_set) = src; | |
2906 | SET_DEST (old_set) = ep->to_rtx; | |
2907 | } | |
2908 | } | |
2909 | ||
2910 | val = 1; | |
2911 | goto done; | |
2912 | } | |
2913 | } | |
2914 | #endif | |
2915 | ||
32131a9c RK |
2916 | /* In this case this insn isn't serving a useful purpose. We |
2917 | will delete it in reload_as_needed once we know that this | |
2918 | elimination is, in fact, being done. | |
2919 | ||
abc95ed3 | 2920 | If REPLACE isn't set, we can't delete this insn, but needn't |
32131a9c RK |
2921 | process it since it won't be used unless something changes. */ |
2922 | if (replace) | |
8a34409d RH |
2923 | { |
2924 | delete_dead_insn (insn); | |
2925 | return 1; | |
2926 | } | |
32131a9c RK |
2927 | val = 1; |
2928 | goto done; | |
2929 | } | |
aa5524a9 | 2930 | } |
32131a9c | 2931 | |
aa5524a9 BS |
2932 | /* We allow one special case which happens to work on all machines we |
2933 | currently support: a single set with the source being a PLUS of an | |
2934 | eliminable register and a constant. */ | |
2935 | if (old_set | |
2936 | && GET_CODE (SET_SRC (old_set)) == PLUS | |
2937 | && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG | |
2938 | && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT | |
2939 | && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER) | |
2940 | { | |
2941 | rtx reg = XEXP (SET_SRC (old_set), 0); | |
2942 | int offset = INTVAL (XEXP (SET_SRC (old_set), 1)); | |
32131a9c | 2943 | |
aa5524a9 BS |
2944 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
2945 | if (ep->from_rtx == reg && ep->can_eliminate) | |
2946 | { | |
2947 | offset += ep->offset; | |
32131a9c | 2948 | |
aa5524a9 BS |
2949 | if (offset == 0) |
2950 | { | |
2951 | /* We assume here that we don't need a PARALLEL of | |
2952 | any CLOBBERs for this assignment. There's not | |
2953 | much we can do if we do need it. */ | |
2954 | PATTERN (insn) = gen_rtx_SET (VOIDmode, | |
2955 | SET_DEST (old_set), | |
2956 | ep->to_rtx); | |
2957 | INSN_CODE (insn) = recog (PATTERN (insn), insn, 0); | |
2958 | if (INSN_CODE (insn) < 0) | |
2959 | abort (); | |
2960 | } | |
2961 | else | |
2962 | { | |
2963 | new_body = old_body; | |
2964 | if (! replace) | |
2965 | { | |
2966 | new_body = copy_insn (old_body); | |
2967 | if (REG_NOTES (insn)) | |
2968 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
2969 | } | |
2970 | PATTERN (insn) = new_body; | |
2971 | old_set = single_set (insn); | |
922d9d40 | 2972 | |
aa5524a9 BS |
2973 | XEXP (SET_SRC (old_set), 0) = ep->to_rtx; |
2974 | XEXP (SET_SRC (old_set), 1) = GEN_INT (offset); | |
2975 | } | |
2976 | val = 1; | |
2977 | /* This can't have an effect on elimination offsets, so skip right | |
2978 | to the end. */ | |
2979 | goto done; | |
2980 | } | |
32131a9c RK |
2981 | } |
2982 | ||
dfac187e BS |
2983 | /* Determine the effects of this insn on elimination offsets. */ |
2984 | elimination_effects (old_body, 0); | |
2985 | ||
2986 | /* Eliminate all eliminable registers occurring in operands that | |
2987 | can be handled by reload. */ | |
2988 | extract_insn (insn); | |
2989 | any_changes = 0; | |
2990 | for (i = 0; i < recog_data.n_operands; i++) | |
2991 | { | |
2992 | orig_operand[i] = recog_data.operand[i]; | |
2993 | substed_operand[i] = recog_data.operand[i]; | |
2994 | ||
2995 | /* For an asm statement, every operand is eliminable. */ | |
2996 | if (insn_is_asm || insn_data[icode].operand[i].eliminable) | |
2997 | { | |
2998 | /* Check for setting a register that we know about. */ | |
2999 | if (recog_data.operand_type[i] != OP_IN | |
3000 | && GET_CODE (orig_operand[i]) == REG) | |
3001 | { | |
3002 | /* If we are assigning to a register that can be eliminated, it | |
3003 | must be as part of a PARALLEL, since the code above handles | |
3004 | single SETs. We must indicate that we can no longer | |
3005 | eliminate this reg. */ | |
3006 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; | |
3007 | ep++) | |
3008 | if (ep->from_rtx == orig_operand[i] && ep->can_eliminate) | |
3009 | ep->can_eliminate = 0; | |
3010 | } | |
3011 | ||
3012 | substed_operand[i] = eliminate_regs (recog_data.operand[i], 0, | |
3013 | replace ? insn : NULL_RTX); | |
3014 | if (substed_operand[i] != orig_operand[i]) | |
3015 | val = any_changes = 1; | |
3016 | /* Terminate the search in check_eliminable_occurrences at | |
3017 | this point. */ | |
3018 | *recog_data.operand_loc[i] = 0; | |
3019 | ||
3020 | /* If an output operand changed from a REG to a MEM and INSN is an | |
3021 | insn, write a CLOBBER insn. */ | |
3022 | if (recog_data.operand_type[i] != OP_IN | |
3023 | && GET_CODE (orig_operand[i]) == REG | |
3024 | && GET_CODE (substed_operand[i]) == MEM | |
3025 | && replace) | |
3026 | emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]), | |
3027 | insn); | |
3028 | } | |
3029 | } | |
3030 | ||
3031 | for (i = 0; i < recog_data.n_dups; i++) | |
3032 | *recog_data.dup_loc[i] | |
aa5524a9 | 3033 | = *recog_data.operand_loc[(int)recog_data.dup_num[i]]; |
dfac187e BS |
3034 | |
3035 | /* If any eliminable remain, they aren't eliminable anymore. */ | |
3036 | check_eliminable_occurrences (old_body); | |
32131a9c | 3037 | |
dfac187e BS |
3038 | /* Substitute the operands; the new values are in the substed_operand |
3039 | array. */ | |
3040 | for (i = 0; i < recog_data.n_operands; i++) | |
3041 | *recog_data.operand_loc[i] = substed_operand[i]; | |
3042 | for (i = 0; i < recog_data.n_dups; i++) | |
3043 | *recog_data.dup_loc[i] = substed_operand[(int)recog_data.dup_num[i]]; | |
32131a9c | 3044 | |
dfac187e | 3045 | /* If we are replacing a body that was a (set X (plus Y Z)), try to |
32131a9c RK |
3046 | re-recognize the insn. We do this in case we had a simple addition |
3047 | but now can do this as a load-address. This saves an insn in this | |
dfac187e BS |
3048 | common case. |
3049 | If re-recognition fails, the old insn code number will still be used, | |
3050 | and some register operands may have changed into PLUS expressions. | |
3051 | These will be handled by find_reloads by loading them into a register | |
3052 | again.*/ | |
32131a9c | 3053 | |
dfac187e | 3054 | if (val) |
32131a9c | 3055 | { |
7c791b13 RK |
3056 | /* If we aren't replacing things permanently and we changed something, |
3057 | make another copy to ensure that all the RTL is new. Otherwise | |
3058 | things can go wrong if find_reload swaps commutative operands | |
0f41302f | 3059 | and one is inside RTL that has been copied while the other is not. */ |
dfac187e BS |
3060 | new_body = old_body; |
3061 | if (! replace) | |
1b3b5765 BS |
3062 | { |
3063 | new_body = copy_insn (old_body); | |
3064 | if (REG_NOTES (insn)) | |
3065 | REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); | |
3066 | } | |
dfac187e | 3067 | PATTERN (insn) = new_body; |
7c791b13 | 3068 | |
774672d2 RK |
3069 | /* If we had a move insn but now we don't, rerecognize it. This will |
3070 | cause spurious re-recognition if the old move had a PARALLEL since | |
3071 | the new one still will, but we can't call single_set without | |
3072 | having put NEW_BODY into the insn and the re-recognition won't | |
3073 | hurt in this rare case. */ | |
dfac187e BS |
3074 | /* ??? Why this huge if statement - why don't we just rerecognize the |
3075 | thing always? */ | |
3076 | if (! insn_is_asm | |
3077 | && old_set != 0 | |
774672d2 RK |
3078 | && ((GET_CODE (SET_SRC (old_set)) == REG |
3079 | && (GET_CODE (new_body) != SET | |
3080 | || GET_CODE (SET_SRC (new_body)) != REG)) | |
3081 | /* If this was a load from or store to memory, compare | |
1ccbefce RH |
3082 | the MEM in recog_data.operand to the one in the insn. |
3083 | If they are not equal, then rerecognize the insn. */ | |
774672d2 RK |
3084 | || (old_set != 0 |
3085 | && ((GET_CODE (SET_SRC (old_set)) == MEM | |
1ccbefce | 3086 | && SET_SRC (old_set) != recog_data.operand[1]) |
774672d2 | 3087 | || (GET_CODE (SET_DEST (old_set)) == MEM |
1ccbefce | 3088 | && SET_DEST (old_set) != recog_data.operand[0]))) |
774672d2 RK |
3089 | /* If this was an add insn before, rerecognize. */ |
3090 | || GET_CODE (SET_SRC (old_set)) == PLUS)) | |
4a5d0fb5 | 3091 | { |
dfac187e BS |
3092 | int new_icode = recog (PATTERN (insn), insn, 0); |
3093 | if (new_icode < 0) | |
3094 | INSN_CODE (insn) = icode; | |
4a5d0fb5 | 3095 | } |
dfac187e | 3096 | } |
32131a9c | 3097 | |
dfac187e BS |
3098 | /* Restore the old body. If there were any changes to it, we made a copy |
3099 | of it while the changes were still in place, so we'll correctly return | |
3100 | a modified insn below. */ | |
3101 | if (! replace) | |
3102 | { | |
3103 | /* Restore the old body. */ | |
3104 | for (i = 0; i < recog_data.n_operands; i++) | |
3105 | *recog_data.operand_loc[i] = orig_operand[i]; | |
3106 | for (i = 0; i < recog_data.n_dups; i++) | |
3107 | *recog_data.dup_loc[i] = orig_operand[(int)recog_data.dup_num[i]]; | |
32131a9c | 3108 | } |
a8fdc208 | 3109 | |
dfac187e BS |
3110 | /* Update all elimination pairs to reflect the status after the current |
3111 | insn. The changes we make were determined by the earlier call to | |
3112 | elimination_effects. | |
a8efe40d | 3113 | |
32131a9c RK |
3114 | We also detect a cases where register elimination cannot be done, |
3115 | namely, if a register would be both changed and referenced outside a MEM | |
3116 | in the resulting insn since such an insn is often undefined and, even if | |
3117 | not, we cannot know what meaning will be given to it. Note that it is | |
3118 | valid to have a register used in an address in an insn that changes it | |
3119 | (presumably with a pre- or post-increment or decrement). | |
3120 | ||
3121 | If anything changes, return nonzero. */ | |
3122 | ||
32131a9c RK |
3123 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
3124 | { | |
3125 | if (ep->previous_offset != ep->offset && ep->ref_outside_mem) | |
3126 | ep->can_eliminate = 0; | |
3127 | ||
3128 | ep->ref_outside_mem = 0; | |
3129 | ||
3130 | if (ep->previous_offset != ep->offset) | |
3131 | val = 1; | |
32131a9c RK |
3132 | } |
3133 | ||
3134 | done: | |
9faa82d8 | 3135 | /* If we changed something, perform elimination in REG_NOTES. This is |
05b4c365 RK |
3136 | needed even when REPLACE is zero because a REG_DEAD note might refer |
3137 | to a register that we eliminate and could cause a different number | |
3138 | of spill registers to be needed in the final reload pass than in | |
3139 | the pre-passes. */ | |
20748cab | 3140 | if (val && REG_NOTES (insn) != 0) |
1914f5da | 3141 | REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn)); |
05b4c365 | 3142 | |
32131a9c RK |
3143 | if (! replace) |
3144 | pop_obstacks (); | |
3145 | ||
3146 | return val; | |
3147 | } | |
3148 | ||
cb2afeb3 R |
3149 | /* Loop through all elimination pairs. |
3150 | Recalculate the number not at initial offset. | |
3151 | ||
3152 | Compute the maximum offset (minimum offset if the stack does not | |
3153 | grow downward) for each elimination pair. */ | |
3154 | ||
3155 | static void | |
3156 | update_eliminable_offsets () | |
3157 | { | |
3158 | struct elim_table *ep; | |
3159 | ||
3160 | num_not_at_initial_offset = 0; | |
3161 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3162 | { | |
3163 | ep->previous_offset = ep->offset; | |
3164 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3165 | num_not_at_initial_offset++; | |
cb2afeb3 R |
3166 | } |
3167 | } | |
3168 | ||
32131a9c RK |
3169 | /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register |
3170 | replacement we currently believe is valid, mark it as not eliminable if X | |
3171 | modifies DEST in any way other than by adding a constant integer to it. | |
3172 | ||
3173 | If DEST is the frame pointer, we do nothing because we assume that | |
3ec2ea3e DE |
3174 | all assignments to the hard frame pointer are nonlocal gotos and are being |
3175 | done at a time when they are valid and do not disturb anything else. | |
32131a9c | 3176 | Some machines want to eliminate a fake argument pointer with either the |
3ec2ea3e DE |
3177 | frame or stack pointer. Assignments to the hard frame pointer must not |
3178 | prevent this elimination. | |
32131a9c RK |
3179 | |
3180 | Called via note_stores from reload before starting its passes to scan | |
3181 | the insns of the function. */ | |
3182 | ||
3183 | static void | |
84832317 | 3184 | mark_not_eliminable (dest, x, data) |
32131a9c RK |
3185 | rtx dest; |
3186 | rtx x; | |
84832317 | 3187 | void *data ATTRIBUTE_UNUSED; |
32131a9c | 3188 | { |
e51712db | 3189 | register unsigned int i; |
32131a9c RK |
3190 | |
3191 | /* A SUBREG of a hard register here is just changing its mode. We should | |
3192 | not see a SUBREG of an eliminable hard register, but check just in | |
3193 | case. */ | |
3194 | if (GET_CODE (dest) == SUBREG) | |
3195 | dest = SUBREG_REG (dest); | |
3196 | ||
3ec2ea3e | 3197 | if (dest == hard_frame_pointer_rtx) |
32131a9c RK |
3198 | return; |
3199 | ||
3200 | for (i = 0; i < NUM_ELIMINABLE_REGS; i++) | |
3201 | if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx | |
3202 | && (GET_CODE (x) != SET | |
3203 | || GET_CODE (SET_SRC (x)) != PLUS | |
3204 | || XEXP (SET_SRC (x), 0) != dest | |
3205 | || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT)) | |
3206 | { | |
3207 | reg_eliminate[i].can_eliminate_previous | |
3208 | = reg_eliminate[i].can_eliminate = 0; | |
3209 | num_eliminable--; | |
3210 | } | |
3211 | } | |
09dd1133 | 3212 | |
c47f5ea5 BS |
3213 | /* Verify that the initial elimination offsets did not change since the |
3214 | last call to set_initial_elim_offsets. This is used to catch cases | |
3215 | where something illegal happened during reload_as_needed that could | |
3216 | cause incorrect code to be generated if we did not check for it. */ | |
c8d8ed65 | 3217 | |
c47f5ea5 BS |
3218 | static void |
3219 | verify_initial_elim_offsets () | |
3220 | { | |
3221 | int t; | |
3222 | ||
3223 | #ifdef ELIMINABLE_REGS | |
3224 | struct elim_table *ep; | |
3225 | ||
3226 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3227 | { | |
3228 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t); | |
3229 | if (t != ep->initial_offset) | |
3230 | abort (); | |
3231 | } | |
3232 | #else | |
3233 | INITIAL_FRAME_POINTER_OFFSET (t); | |
3234 | if (t != reg_eliminate[0].initial_offset) | |
3235 | abort (); | |
05d10675 | 3236 | #endif |
c47f5ea5 BS |
3237 | } |
3238 | ||
09dd1133 | 3239 | /* Reset all offsets on eliminable registers to their initial values. */ |
1d813780 | 3240 | |
09dd1133 BS |
3241 | static void |
3242 | set_initial_elim_offsets () | |
3243 | { | |
1f3b1e1a | 3244 | struct elim_table *ep = reg_eliminate; |
09dd1133 BS |
3245 | |
3246 | #ifdef ELIMINABLE_REGS | |
1f3b1e1a | 3247 | for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) |
09dd1133 BS |
3248 | { |
3249 | INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); | |
1f3b1e1a | 3250 | ep->previous_offset = ep->offset = ep->initial_offset; |
09dd1133 BS |
3251 | } |
3252 | #else | |
1f3b1e1a JL |
3253 | INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset); |
3254 | ep->previous_offset = ep->offset = ep->initial_offset; | |
09dd1133 BS |
3255 | #endif |
3256 | ||
3257 | num_not_at_initial_offset = 0; | |
1f3b1e1a | 3258 | } |
09dd1133 | 3259 | |
1f3b1e1a JL |
3260 | /* Initialize the known label offsets. |
3261 | Set a known offset for each forced label to be at the initial offset | |
3262 | of each elimination. We do this because we assume that all | |
3263 | computed jumps occur from a location where each elimination is | |
3264 | at its initial offset. | |
3265 | For all other labels, show that we don't know the offsets. */ | |
09dd1133 | 3266 | |
1f3b1e1a JL |
3267 | static void |
3268 | set_initial_label_offsets () | |
3269 | { | |
3270 | rtx x; | |
3271 | bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels); | |
09dd1133 BS |
3272 | |
3273 | for (x = forced_labels; x; x = XEXP (x, 1)) | |
3274 | if (XEXP (x, 0)) | |
3275 | set_label_offsets (XEXP (x, 0), NULL_RTX, 1); | |
3276 | } | |
3277 | ||
1f3b1e1a JL |
3278 | /* Set all elimination offsets to the known values for the code label given |
3279 | by INSN. */ | |
1d813780 | 3280 | |
1f3b1e1a JL |
3281 | static void |
3282 | set_offsets_for_label (insn) | |
3283 | rtx insn; | |
3284 | { | |
973838fd | 3285 | unsigned int i; |
1f3b1e1a JL |
3286 | int label_nr = CODE_LABEL_NUMBER (insn); |
3287 | struct elim_table *ep; | |
3288 | ||
3289 | num_not_at_initial_offset = 0; | |
3290 | for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++) | |
3291 | { | |
3292 | ep->offset = ep->previous_offset = offsets_at[label_nr][i]; | |
3293 | if (ep->can_eliminate && ep->offset != ep->initial_offset) | |
3294 | num_not_at_initial_offset++; | |
3295 | } | |
3296 | } | |
3297 | ||
09dd1133 BS |
3298 | /* See if anything that happened changes which eliminations are valid. |
3299 | For example, on the Sparc, whether or not the frame pointer can | |
3300 | be eliminated can depend on what registers have been used. We need | |
3301 | not check some conditions again (such as flag_omit_frame_pointer) | |
3302 | since they can't have changed. */ | |
3303 | ||
3304 | static void | |
3305 | update_eliminables (pset) | |
3306 | HARD_REG_SET *pset; | |
3307 | { | |
3308 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
3309 | int previous_frame_pointer_needed = frame_pointer_needed; | |
3310 | #endif | |
3311 | struct elim_table *ep; | |
3312 | ||
3313 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3314 | if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED) | |
3315 | #ifdef ELIMINABLE_REGS | |
3316 | || ! CAN_ELIMINATE (ep->from, ep->to) | |
3317 | #endif | |
3318 | ) | |
3319 | ep->can_eliminate = 0; | |
3320 | ||
3321 | /* Look for the case where we have discovered that we can't replace | |
3322 | register A with register B and that means that we will now be | |
3323 | trying to replace register A with register C. This means we can | |
3324 | no longer replace register C with register B and we need to disable | |
3325 | such an elimination, if it exists. This occurs often with A == ap, | |
3326 | B == sp, and C == fp. */ | |
3327 | ||
3328 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3329 | { | |
3330 | struct elim_table *op; | |
3331 | register int new_to = -1; | |
3332 | ||
3333 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3334 | { | |
3335 | /* Find the current elimination for ep->from, if there is a | |
3336 | new one. */ | |
3337 | for (op = reg_eliminate; | |
3338 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3339 | if (op->from == ep->from && op->can_eliminate) | |
3340 | { | |
3341 | new_to = op->to; | |
3342 | break; | |
3343 | } | |
3344 | ||
3345 | /* See if there is an elimination of NEW_TO -> EP->TO. If so, | |
3346 | disable it. */ | |
3347 | for (op = reg_eliminate; | |
3348 | op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) | |
3349 | if (op->from == new_to && op->to == ep->to) | |
3350 | op->can_eliminate = 0; | |
3351 | } | |
3352 | } | |
3353 | ||
3354 | /* See if any registers that we thought we could eliminate the previous | |
3355 | time are no longer eliminable. If so, something has changed and we | |
3356 | must spill the register. Also, recompute the number of eliminable | |
3357 | registers and see if the frame pointer is needed; it is if there is | |
3358 | no elimination of the frame pointer that we can perform. */ | |
3359 | ||
3360 | frame_pointer_needed = 1; | |
3361 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3362 | { | |
3363 | if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM | |
3364 | && ep->to != HARD_FRAME_POINTER_REGNUM) | |
3365 | frame_pointer_needed = 0; | |
3366 | ||
3367 | if (! ep->can_eliminate && ep->can_eliminate_previous) | |
3368 | { | |
3369 | ep->can_eliminate_previous = 0; | |
3370 | SET_HARD_REG_BIT (*pset, ep->from); | |
3371 | num_eliminable--; | |
3372 | } | |
3373 | } | |
3374 | ||
3375 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM | |
3376 | /* If we didn't need a frame pointer last time, but we do now, spill | |
3377 | the hard frame pointer. */ | |
3378 | if (frame_pointer_needed && ! previous_frame_pointer_needed) | |
3379 | SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM); | |
3380 | #endif | |
3381 | } | |
3382 | ||
3383 | /* Initialize the table of registers to eliminate. */ | |
1d813780 | 3384 | |
09dd1133 BS |
3385 | static void |
3386 | init_elim_table () | |
3387 | { | |
3388 | struct elim_table *ep; | |
590cf94d KG |
3389 | #ifdef ELIMINABLE_REGS |
3390 | struct elim_table_1 *ep1; | |
3391 | #endif | |
09dd1133 | 3392 | |
590cf94d | 3393 | if (!reg_eliminate) |
ad85216e KG |
3394 | reg_eliminate = (struct elim_table *) |
3395 | xcalloc(sizeof(struct elim_table), NUM_ELIMINABLE_REGS); | |
05d10675 | 3396 | |
09dd1133 BS |
3397 | /* Does this function require a frame pointer? */ |
3398 | ||
3399 | frame_pointer_needed = (! flag_omit_frame_pointer | |
3400 | #ifdef EXIT_IGNORE_STACK | |
3401 | /* ?? If EXIT_IGNORE_STACK is set, we will not save | |
3402 | and restore sp for alloca. So we can't eliminate | |
3403 | the frame pointer in that case. At some point, | |
3404 | we should improve this by emitting the | |
3405 | sp-adjusting insns for this case. */ | |
3406 | || (current_function_calls_alloca | |
3407 | && EXIT_IGNORE_STACK) | |
3408 | #endif | |
3409 | || FRAME_POINTER_REQUIRED); | |
3410 | ||
3411 | num_eliminable = 0; | |
3412 | ||
3413 | #ifdef ELIMINABLE_REGS | |
590cf94d KG |
3414 | for (ep = reg_eliminate, ep1 = reg_eliminate_1; |
3415 | ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++) | |
09dd1133 | 3416 | { |
590cf94d KG |
3417 | ep->from = ep1->from; |
3418 | ep->to = ep1->to; | |
09dd1133 BS |
3419 | ep->can_eliminate = ep->can_eliminate_previous |
3420 | = (CAN_ELIMINATE (ep->from, ep->to) | |
3421 | && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed)); | |
3422 | } | |
3423 | #else | |
590cf94d KG |
3424 | reg_eliminate[0].from = reg_eliminate_1[0].from; |
3425 | reg_eliminate[0].to = reg_eliminate_1[0].to; | |
09dd1133 BS |
3426 | reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous |
3427 | = ! frame_pointer_needed; | |
3428 | #endif | |
3429 | ||
3430 | /* Count the number of eliminable registers and build the FROM and TO | |
3431 | REG rtx's. Note that code in gen_rtx will cause, e.g., | |
3432 | gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. | |
3433 | We depend on this. */ | |
3434 | for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) | |
3435 | { | |
3436 | num_eliminable += ep->can_eliminate; | |
3437 | ep->from_rtx = gen_rtx_REG (Pmode, ep->from); | |
3438 | ep->to_rtx = gen_rtx_REG (Pmode, ep->to); | |
3439 | } | |
3440 | } | |
32131a9c RK |
3441 | \f |
3442 | /* Kick all pseudos out of hard register REGNO. | |
32131a9c RK |
3443 | If DUMPFILE is nonzero, log actions taken on that file. |
3444 | ||
3445 | If CANT_ELIMINATE is nonzero, it means that we are doing this spill | |
3446 | because we found we can't eliminate some register. In the case, no pseudos | |
3447 | are allowed to be in the register, even if they are only in a block that | |
3448 | doesn't require spill registers, unlike the case when we are spilling this | |
3449 | hard reg to produce another spill register. | |
3450 | ||
3451 | Return nonzero if any pseudos needed to be kicked out. */ | |
3452 | ||
03acd8f8 BS |
3453 | static void |
3454 | spill_hard_reg (regno, dumpfile, cant_eliminate) | |
770ae6cc | 3455 | unsigned int regno; |
6a651371 | 3456 | FILE *dumpfile ATTRIBUTE_UNUSED; |
32131a9c RK |
3457 | int cant_eliminate; |
3458 | { | |
32131a9c RK |
3459 | register int i; |
3460 | ||
9ff3516a | 3461 | if (cant_eliminate) |
03acd8f8 BS |
3462 | { |
3463 | SET_HARD_REG_BIT (bad_spill_regs_global, regno); | |
3464 | regs_ever_live[regno] = 1; | |
3465 | } | |
9ff3516a | 3466 | |
32131a9c RK |
3467 | /* Spill every pseudo reg that was allocated to this reg |
3468 | or to something that overlaps this reg. */ | |
3469 | ||
3470 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3471 | if (reg_renumber[i] >= 0 | |
770ae6cc RK |
3472 | && (unsigned int) reg_renumber[i] <= regno |
3473 | && ((unsigned int) reg_renumber[i] | |
3474 | + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i], | |
32131a9c RK |
3475 | PSEUDO_REGNO_MODE (i)) |
3476 | > regno)) | |
f5d8c9f4 | 3477 | SET_REGNO_REG_SET (&spilled_pseudos, i); |
03acd8f8 | 3478 | } |
32131a9c | 3479 | |
03acd8f8 BS |
3480 | /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET |
3481 | from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */ | |
770ae6cc | 3482 | |
03acd8f8 BS |
3483 | static void |
3484 | ior_hard_reg_set (set1, set2) | |
3485 | HARD_REG_SET *set1, *set2; | |
3486 | { | |
3487 | IOR_HARD_REG_SET (*set1, *set2); | |
3488 | } | |
05d10675 | 3489 | |
03acd8f8 BS |
3490 | /* After find_reload_regs has been run for all insn that need reloads, |
3491 | and/or spill_hard_regs was called, this function is used to actually | |
3492 | spill pseudo registers and try to reallocate them. It also sets up the | |
3493 | spill_regs array for use by choose_reload_regs. */ | |
a8fdc208 | 3494 | |
03acd8f8 BS |
3495 | static int |
3496 | finish_spills (global, dumpfile) | |
3497 | int global; | |
3498 | FILE *dumpfile; | |
3499 | { | |
3500 | struct insn_chain *chain; | |
3501 | int something_changed = 0; | |
3502 | int i; | |
3503 | ||
3504 | /* Build the spill_regs array for the function. */ | |
3505 | /* If there are some registers still to eliminate and one of the spill regs | |
3506 | wasn't ever used before, additional stack space may have to be | |
3507 | allocated to store this register. Thus, we may have changed the offset | |
3508 | between the stack and frame pointers, so mark that something has changed. | |
32131a9c | 3509 | |
03acd8f8 BS |
3510 | One might think that we need only set VAL to 1 if this is a call-used |
3511 | register. However, the set of registers that must be saved by the | |
3512 | prologue is not identical to the call-used set. For example, the | |
3513 | register used by the call insn for the return PC is a call-used register, | |
3514 | but must be saved by the prologue. */ | |
3515 | ||
3516 | n_spills = 0; | |
3517 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
3518 | if (TEST_HARD_REG_BIT (used_spill_regs, i)) | |
3519 | { | |
3520 | spill_reg_order[i] = n_spills; | |
3521 | spill_regs[n_spills++] = i; | |
3522 | if (num_eliminable && ! regs_ever_live[i]) | |
3523 | something_changed = 1; | |
3524 | regs_ever_live[i] = 1; | |
3525 | } | |
3526 | else | |
3527 | spill_reg_order[i] = -1; | |
3528 | ||
efc9bd41 RK |
3529 | EXECUTE_IF_SET_IN_REG_SET |
3530 | (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, | |
3531 | { | |
3532 | /* Record the current hard register the pseudo is allocated to in | |
3533 | pseudo_previous_regs so we avoid reallocating it to the same | |
3534 | hard reg in a later pass. */ | |
3535 | if (reg_renumber[i] < 0) | |
3536 | abort (); | |
3537 | ||
3538 | SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]); | |
3539 | /* Mark it as no longer having a hard register home. */ | |
3540 | reg_renumber[i] = -1; | |
3541 | /* We will need to scan everything again. */ | |
3542 | something_changed = 1; | |
3543 | }); | |
7609e720 | 3544 | |
03acd8f8 BS |
3545 | /* Retry global register allocation if possible. */ |
3546 | if (global) | |
3547 | { | |
3548 | bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET)); | |
3549 | /* For every insn that needs reloads, set the registers used as spill | |
3550 | regs in pseudo_forbidden_regs for every pseudo live across the | |
3551 | insn. */ | |
3552 | for (chain = insns_need_reload; chain; chain = chain->next_need_reload) | |
3553 | { | |
3554 | EXECUTE_IF_SET_IN_REG_SET | |
239a0f5b | 3555 | (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, |
03acd8f8 BS |
3556 | { |
3557 | ior_hard_reg_set (pseudo_forbidden_regs + i, | |
3558 | &chain->used_spill_regs); | |
3559 | }); | |
3560 | EXECUTE_IF_SET_IN_REG_SET | |
239a0f5b | 3561 | (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, |
03acd8f8 BS |
3562 | { |
3563 | ior_hard_reg_set (pseudo_forbidden_regs + i, | |
3564 | &chain->used_spill_regs); | |
3565 | }); | |
3566 | } | |
7609e720 | 3567 | |
03acd8f8 BS |
3568 | /* Retry allocating the spilled pseudos. For each reg, merge the |
3569 | various reg sets that indicate which hard regs can't be used, | |
3570 | and call retry_global_alloc. | |
05d10675 | 3571 | We change spill_pseudos here to only contain pseudos that did not |
03acd8f8 BS |
3572 | get a new hard register. */ |
3573 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3574 | if (reg_old_renumber[i] != reg_renumber[i]) | |
32131a9c | 3575 | { |
03acd8f8 BS |
3576 | HARD_REG_SET forbidden; |
3577 | COPY_HARD_REG_SET (forbidden, bad_spill_regs_global); | |
3578 | IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]); | |
3579 | IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]); | |
3580 | retry_global_alloc (i, forbidden); | |
3581 | if (reg_renumber[i] >= 0) | |
f5d8c9f4 | 3582 | CLEAR_REGNO_REG_SET (&spilled_pseudos, i); |
32131a9c | 3583 | } |
03acd8f8 | 3584 | } |
7609e720 | 3585 | |
03acd8f8 BS |
3586 | /* Fix up the register information in the insn chain. |
3587 | This involves deleting those of the spilled pseudos which did not get | |
3588 | a new hard register home from the live_{before,after} sets. */ | |
7609e720 BS |
3589 | for (chain = reload_insn_chain; chain; chain = chain->next) |
3590 | { | |
03acd8f8 BS |
3591 | HARD_REG_SET used_by_pseudos; |
3592 | HARD_REG_SET used_by_pseudos2; | |
3593 | ||
239a0f5b BS |
3594 | AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos); |
3595 | AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos); | |
03acd8f8 BS |
3596 | |
3597 | /* Mark any unallocated hard regs as available for spills. That | |
3598 | makes inheritance work somewhat better. */ | |
3599 | if (chain->need_reload) | |
3600 | { | |
239a0f5b BS |
3601 | REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); |
3602 | REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); | |
03acd8f8 BS |
3603 | IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2); |
3604 | ||
3605 | /* Save the old value for the sanity test below. */ | |
3606 | COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs); | |
3607 | ||
239a0f5b BS |
3608 | compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout); |
3609 | compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set); | |
03acd8f8 BS |
3610 | COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos); |
3611 | AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs); | |
3612 | ||
3613 | /* Make sure we only enlarge the set. */ | |
3614 | GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok); | |
3615 | abort (); | |
3616 | ok:; | |
3617 | } | |
7609e720 | 3618 | } |
03acd8f8 BS |
3619 | |
3620 | /* Let alter_reg modify the reg rtx's for the modified pseudos. */ | |
3621 | for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) | |
3622 | { | |
3623 | int regno = reg_renumber[i]; | |
3624 | if (reg_old_renumber[i] == regno) | |
3625 | continue; | |
05d10675 | 3626 | |
03acd8f8 BS |
3627 | alter_reg (i, reg_old_renumber[i]); |
3628 | reg_old_renumber[i] = regno; | |
3629 | if (dumpfile) | |
3630 | { | |
3631 | if (regno == -1) | |
3632 | fprintf (dumpfile, " Register %d now on stack.\n\n", i); | |
3633 | else | |
3634 | fprintf (dumpfile, " Register %d now in %d.\n\n", | |
3635 | i, reg_renumber[i]); | |
3636 | } | |
3637 | } | |
3638 | ||
3639 | return something_changed; | |
7609e720 | 3640 | } |
32131a9c | 3641 | \f |
05d10675 | 3642 | /* Find all paradoxical subregs within X and update reg_max_ref_width. |
56f58d3a RK |
3643 | Also mark any hard registers used to store user variables as |
3644 | forbidden from being used for spill registers. */ | |
32131a9c RK |
3645 | |
3646 | static void | |
3647 | scan_paradoxical_subregs (x) | |
3648 | register rtx x; | |
3649 | { | |
3650 | register int i; | |
6f7d635c | 3651 | register const char *fmt; |
32131a9c RK |
3652 | register enum rtx_code code = GET_CODE (x); |
3653 | ||
3654 | switch (code) | |
3655 | { | |
56f58d3a | 3656 | case REG: |
03acd8f8 | 3657 | #if 0 |
e9a25f70 | 3658 | if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER |
f95182a4 | 3659 | && REG_USERVAR_P (x)) |
03acd8f8 BS |
3660 | SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x)); |
3661 | #endif | |
56f58d3a RK |
3662 | return; |
3663 | ||
32131a9c RK |
3664 | case CONST_INT: |
3665 | case CONST: | |
3666 | case SYMBOL_REF: | |
3667 | case LABEL_REF: | |
3668 | case CONST_DOUBLE: | |
3669 | case CC0: | |
3670 | case PC: | |
32131a9c RK |
3671 | case USE: |
3672 | case CLOBBER: | |
3673 | return; | |
3674 | ||
3675 | case SUBREG: | |
3676 | if (GET_CODE (SUBREG_REG (x)) == REG | |
3677 | && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
3678 | reg_max_ref_width[REGNO (SUBREG_REG (x))] | |
3679 | = GET_MODE_SIZE (GET_MODE (x)); | |
3680 | return; | |
05d10675 | 3681 | |
e9a25f70 JL |
3682 | default: |
3683 | break; | |
32131a9c RK |
3684 | } |
3685 | ||
3686 | fmt = GET_RTX_FORMAT (code); | |
3687 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3688 | { | |
3689 | if (fmt[i] == 'e') | |
3690 | scan_paradoxical_subregs (XEXP (x, i)); | |
3691 | else if (fmt[i] == 'E') | |
3692 | { | |
3693 | register int j; | |
3694 | for (j = XVECLEN (x, i) - 1; j >=0; j--) | |
3695 | scan_paradoxical_subregs (XVECEXP (x, i, j)); | |
3696 | } | |
3697 | } | |
3698 | } | |
3699 | \f | |
32131a9c RK |
3700 | /* Reload pseudo-registers into hard regs around each insn as needed. |
3701 | Additional register load insns are output before the insn that needs it | |
3702 | and perhaps store insns after insns that modify the reloaded pseudo reg. | |
3703 | ||
3704 | reg_last_reload_reg and reg_reloaded_contents keep track of | |
d08ea79f | 3705 | which registers are already available in reload registers. |
32131a9c RK |
3706 | We update these for the reloads that we perform, |
3707 | as the insns are scanned. */ | |
3708 | ||
3709 | static void | |
7609e720 | 3710 | reload_as_needed (live_known) |
32131a9c RK |
3711 | int live_known; |
3712 | { | |
7609e720 | 3713 | struct insn_chain *chain; |
553687c9 | 3714 | #if defined (AUTO_INC_DEC) |
32131a9c | 3715 | register int i; |
973838fd | 3716 | #endif |
32131a9c | 3717 | rtx x; |
32131a9c | 3718 | |
4c9a05bc RK |
3719 | bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx); |
3720 | bzero ((char *) spill_reg_store, sizeof spill_reg_store); | |
ff154f78 MM |
3721 | reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx)); |
3722 | reg_has_output_reload = (char *) xmalloc (max_regno); | |
e6e52be0 | 3723 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
32131a9c | 3724 | |
1f3b1e1a | 3725 | set_initial_elim_offsets (); |
32131a9c | 3726 | |
7609e720 | 3727 | for (chain = reload_insn_chain; chain; chain = chain->next) |
32131a9c | 3728 | { |
03acd8f8 | 3729 | rtx prev; |
7609e720 BS |
3730 | rtx insn = chain->insn; |
3731 | rtx old_next = NEXT_INSN (insn); | |
32131a9c RK |
3732 | |
3733 | /* If we pass a label, copy the offsets from the label information | |
3734 | into the current offsets of each elimination. */ | |
3735 | if (GET_CODE (insn) == CODE_LABEL) | |
1f3b1e1a | 3736 | set_offsets_for_label (insn); |
32131a9c RK |
3737 | |
3738 | else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
3739 | { | |
0639444f | 3740 | rtx oldpat = PATTERN (insn); |
32131a9c | 3741 | |
2758481d RS |
3742 | /* If this is a USE and CLOBBER of a MEM, ensure that any |
3743 | references to eliminable registers have been removed. */ | |
3744 | ||
3745 | if ((GET_CODE (PATTERN (insn)) == USE | |
3746 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
3747 | && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM) | |
3748 | XEXP (XEXP (PATTERN (insn), 0), 0) | |
3749 | = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), | |
29ae5012 | 3750 | GET_MODE (XEXP (PATTERN (insn), 0)), |
1914f5da | 3751 | NULL_RTX); |
2758481d | 3752 | |
32131a9c RK |
3753 | /* If we need to do register elimination processing, do so. |
3754 | This might delete the insn, in which case we are done. */ | |
2b49ee39 | 3755 | if ((num_eliminable || num_eliminable_invariants) && chain->need_elim) |
32131a9c RK |
3756 | { |
3757 | eliminate_regs_in_insn (insn, 1); | |
3758 | if (GET_CODE (insn) == NOTE) | |
cb2afeb3 R |
3759 | { |
3760 | update_eliminable_offsets (); | |
3761 | continue; | |
3762 | } | |
32131a9c RK |
3763 | } |
3764 | ||
7609e720 BS |
3765 | /* If need_elim is nonzero but need_reload is zero, one might think |
3766 | that we could simply set n_reloads to 0. However, find_reloads | |
3767 | could have done some manipulation of the insn (such as swapping | |
3768 | commutative operands), and these manipulations are lost during | |
3769 | the first pass for every insn that needs register elimination. | |
3770 | So the actions of find_reloads must be redone here. */ | |
3771 | ||
03acd8f8 BS |
3772 | if (! chain->need_elim && ! chain->need_reload |
3773 | && ! chain->need_operand_change) | |
32131a9c RK |
3774 | n_reloads = 0; |
3775 | /* First find the pseudo regs that must be reloaded for this insn. | |
3776 | This info is returned in the tables reload_... (see reload.h). | |
3777 | Also modify the body of INSN by substituting RELOAD | |
3778 | rtx's for those pseudo regs. */ | |
3779 | else | |
3780 | { | |
3781 | bzero (reg_has_output_reload, max_regno); | |
3782 | CLEAR_HARD_REG_SET (reg_is_output_reload); | |
3783 | ||
3784 | find_reloads (insn, 1, spill_indirect_levels, live_known, | |
3785 | spill_reg_order); | |
3786 | } | |
3787 | ||
dd6acd1b | 3788 | if (num_eliminable && chain->need_elim) |
cb2afeb3 R |
3789 | update_eliminable_offsets (); |
3790 | ||
32131a9c RK |
3791 | if (n_reloads > 0) |
3792 | { | |
cb2afeb3 | 3793 | rtx next = NEXT_INSN (insn); |
3c3eeea6 | 3794 | rtx p; |
32131a9c | 3795 | |
cb2afeb3 R |
3796 | prev = PREV_INSN (insn); |
3797 | ||
32131a9c RK |
3798 | /* Now compute which reload regs to reload them into. Perhaps |
3799 | reusing reload regs from previous insns, or else output | |
3800 | load insns to reload them. Maybe output store insns too. | |
3801 | Record the choices of reload reg in reload_reg_rtx. */ | |
03acd8f8 | 3802 | choose_reload_regs (chain); |
32131a9c | 3803 | |
05d10675 | 3804 | /* Merge any reloads that we didn't combine for fear of |
546b63fb RK |
3805 | increasing the number of spill registers needed but now |
3806 | discover can be safely merged. */ | |
f95182a4 ILT |
3807 | if (SMALL_REGISTER_CLASSES) |
3808 | merge_assigned_reloads (insn); | |
546b63fb | 3809 | |
32131a9c RK |
3810 | /* Generate the insns to reload operands into or out of |
3811 | their reload regs. */ | |
7609e720 | 3812 | emit_reload_insns (chain); |
32131a9c RK |
3813 | |
3814 | /* Substitute the chosen reload regs from reload_reg_rtx | |
3815 | into the insn's body (or perhaps into the bodies of other | |
3816 | load and store insn that we just made for reloading | |
3817 | and that we moved the structure into). */ | |
3818 | subst_reloads (); | |
3c3eeea6 RK |
3819 | |
3820 | /* If this was an ASM, make sure that all the reload insns | |
3821 | we have generated are valid. If not, give an error | |
3822 | and delete them. */ | |
3823 | ||
3824 | if (asm_noperands (PATTERN (insn)) >= 0) | |
3825 | for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) | |
3826 | if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i' | |
3827 | && (recog_memoized (p) < 0 | |
0eadeb15 | 3828 | || (extract_insn (p), ! constrain_operands (1)))) |
3c3eeea6 RK |
3829 | { |
3830 | error_for_asm (insn, | |
3831 | "`asm' operand requires impossible reload"); | |
3832 | PUT_CODE (p, NOTE); | |
3833 | NOTE_SOURCE_FILE (p) = 0; | |
3834 | NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED; | |
3835 | } | |
32131a9c RK |
3836 | } |
3837 | /* Any previously reloaded spilled pseudo reg, stored in this insn, | |
3838 | is no longer validly lying around to save a future reload. | |
3839 | Note that this does not detect pseudos that were reloaded | |
3840 | for this insn in order to be stored in | |
3841 | (obeying register constraints). That is correct; such reload | |
3842 | registers ARE still valid. */ | |
84832317 | 3843 | note_stores (oldpat, forget_old_reloads_1, NULL); |
32131a9c RK |
3844 | |
3845 | /* There may have been CLOBBER insns placed after INSN. So scan | |
3846 | between INSN and NEXT and use them to forget old reloads. */ | |
7609e720 | 3847 | for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x)) |
32131a9c | 3848 | if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER) |
84832317 | 3849 | note_stores (PATTERN (x), forget_old_reloads_1, NULL); |
32131a9c RK |
3850 | |
3851 | #ifdef AUTO_INC_DEC | |
cb2afeb3 R |
3852 | /* Likewise for regs altered by auto-increment in this insn. |
3853 | REG_INC notes have been changed by reloading: | |
3854 | find_reloads_address_1 records substitutions for them, | |
3855 | which have been performed by subst_reloads above. */ | |
3856 | for (i = n_reloads - 1; i >= 0; i--) | |
3857 | { | |
eceef4c9 | 3858 | rtx in_reg = rld[i].in_reg; |
cb2afeb3 R |
3859 | if (in_reg) |
3860 | { | |
3861 | enum rtx_code code = GET_CODE (in_reg); | |
3862 | /* PRE_INC / PRE_DEC will have the reload register ending up | |
3863 | with the same value as the stack slot, but that doesn't | |
3864 | hold true for POST_INC / POST_DEC. Either we have to | |
3865 | convert the memory access to a true POST_INC / POST_DEC, | |
3866 | or we can't use the reload register for inheritance. */ | |
3867 | if ((code == POST_INC || code == POST_DEC) | |
3868 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 3869 | REGNO (rld[i].reg_rtx)) |
04bbb0c5 JW |
3870 | /* Make sure it is the inc/dec pseudo, and not |
3871 | some other (e.g. output operand) pseudo. */ | |
eceef4c9 | 3872 | && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
04bbb0c5 | 3873 | == REGNO (XEXP (in_reg, 0)))) |
05d10675 | 3874 | |
cb2afeb3 | 3875 | { |
eceef4c9 | 3876 | rtx reload_reg = rld[i].reg_rtx; |
cb2afeb3 R |
3877 | enum machine_mode mode = GET_MODE (reload_reg); |
3878 | int n = 0; | |
3879 | rtx p; | |
3880 | ||
3881 | for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p)) | |
3882 | { | |
3883 | /* We really want to ignore REG_INC notes here, so | |
3884 | use PATTERN (p) as argument to reg_set_p . */ | |
3885 | if (reg_set_p (reload_reg, PATTERN (p))) | |
3886 | break; | |
3887 | n = count_occurrences (PATTERN (p), reload_reg); | |
3888 | if (! n) | |
3889 | continue; | |
3890 | if (n == 1) | |
f67c2384 JL |
3891 | { |
3892 | n = validate_replace_rtx (reload_reg, | |
3893 | gen_rtx (code, mode, | |
3894 | reload_reg), | |
3895 | p); | |
3896 | ||
3897 | /* We must also verify that the constraints | |
3898 | are met after the replacement. */ | |
3899 | extract_insn (p); | |
3900 | if (n) | |
3901 | n = constrain_operands (1); | |
3902 | else | |
3903 | break; | |
3904 | ||
3905 | /* If the constraints were not met, then | |
3906 | undo the replacement. */ | |
3907 | if (!n) | |
3908 | { | |
3909 | validate_replace_rtx (gen_rtx (code, mode, | |
3910 | reload_reg), | |
3911 | reload_reg, p); | |
3912 | break; | |
3913 | } | |
05d10675 | 3914 | |
f67c2384 | 3915 | } |
cb2afeb3 R |
3916 | break; |
3917 | } | |
3918 | if (n == 1) | |
02eb1393 R |
3919 | { |
3920 | REG_NOTES (p) | |
3921 | = gen_rtx_EXPR_LIST (REG_INC, reload_reg, | |
3922 | REG_NOTES (p)); | |
3923 | /* Mark this as having an output reload so that the | |
3924 | REG_INC processing code below won't invalidate | |
3925 | the reload for inheritance. */ | |
3926 | SET_HARD_REG_BIT (reg_is_output_reload, | |
3927 | REGNO (reload_reg)); | |
3928 | reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; | |
3929 | } | |
cb2afeb3 | 3930 | else |
84832317 MM |
3931 | forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX, |
3932 | NULL); | |
cb2afeb3 | 3933 | } |
02eb1393 R |
3934 | else if ((code == PRE_INC || code == PRE_DEC) |
3935 | && TEST_HARD_REG_BIT (reg_reloaded_valid, | |
eceef4c9 | 3936 | REGNO (rld[i].reg_rtx)) |
02eb1393 R |
3937 | /* Make sure it is the inc/dec pseudo, and not |
3938 | some other (e.g. output operand) pseudo. */ | |
eceef4c9 | 3939 | && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)] |
02eb1393 R |
3940 | == REGNO (XEXP (in_reg, 0)))) |
3941 | { | |
3942 | SET_HARD_REG_BIT (reg_is_output_reload, | |
eceef4c9 | 3943 | REGNO (rld[i].reg_rtx)); |
02eb1393 R |
3944 | reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; |
3945 | } | |
cb2afeb3 R |
3946 | } |
3947 | } | |
02eb1393 R |
3948 | /* If a pseudo that got a hard register is auto-incremented, |
3949 | we must purge records of copying it into pseudos without | |
3950 | hard registers. */ | |
32131a9c RK |
3951 | for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) |
3952 | if (REG_NOTE_KIND (x) == REG_INC) | |
3953 | { | |
3954 | /* See if this pseudo reg was reloaded in this insn. | |
3955 | If so, its last-reload info is still valid | |
3956 | because it is based on this insn's reload. */ | |
3957 | for (i = 0; i < n_reloads; i++) | |
eceef4c9 | 3958 | if (rld[i].out == XEXP (x, 0)) |
32131a9c RK |
3959 | break; |
3960 | ||
08fb99fa | 3961 | if (i == n_reloads) |
84832317 | 3962 | forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL); |
32131a9c RK |
3963 | } |
3964 | #endif | |
3965 | } | |
3966 | /* A reload reg's contents are unknown after a label. */ | |
3967 | if (GET_CODE (insn) == CODE_LABEL) | |
e6e52be0 | 3968 | CLEAR_HARD_REG_SET (reg_reloaded_valid); |
32131a9c RK |
3969 | |
3970 | /* Don't assume a reload reg is still good after a call insn | |
3971 | if it is a call-used reg. */ | |
546b63fb | 3972 | else if (GET_CODE (insn) == CALL_INSN) |
e6e52be0 | 3973 | AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set); |
32131a9c | 3974 | } |
ff154f78 MM |
3975 | |
3976 | /* Clean up. */ | |
3977 | free (reg_last_reload_reg); | |
3978 | free (reg_has_output_reload); | |
32131a9c RK |
3979 | } |
3980 | ||
3981 | /* Discard all record of any value reloaded from X, | |
3982 | or reloaded in X from someplace else; | |
3983 | unless X is an output reload reg of the current insn. | |
3984 | ||
3985 | X may be a hard reg (the reload reg) | |
3986 | or it may be a pseudo reg that was reloaded from. */ | |
3987 | ||
3988 | static void | |
84832317 | 3989 | forget_old_reloads_1 (x, ignored, data) |
32131a9c | 3990 | rtx x; |
487a6e06 | 3991 | rtx ignored ATTRIBUTE_UNUSED; |
84832317 | 3992 | void *data ATTRIBUTE_UNUSED; |
32131a9c | 3993 | { |
770ae6cc RK |
3994 | unsigned int regno; |
3995 | unsigned int nr; | |
0a2e51a9 RS |
3996 | int offset = 0; |
3997 | ||
3998 | /* note_stores does give us subregs of hard regs. */ | |
3999 | while (GET_CODE (x) == SUBREG) | |
4000 | { | |
4001 | offset += SUBREG_WORD (x); | |
4002 | x = SUBREG_REG (x); | |
4003 | } | |
32131a9c RK |
4004 | |
4005 | if (GET_CODE (x) != REG) | |
4006 | return; | |
4007 | ||
0a2e51a9 | 4008 | regno = REGNO (x) + offset; |
32131a9c RK |
4009 | |
4010 | if (regno >= FIRST_PSEUDO_REGISTER) | |
4011 | nr = 1; | |
4012 | else | |
4013 | { | |
770ae6cc RK |
4014 | unsigned int i; |
4015 | ||
32131a9c RK |
4016 | nr = HARD_REGNO_NREGS (regno, GET_MODE (x)); |
4017 | /* Storing into a spilled-reg invalidates its contents. | |
4018 | This can happen if a block-local pseudo is allocated to that reg | |
4019 | and it wasn't spilled because this block's total need is 0. | |
4020 | Then some insn might have an optional reload and use this reg. */ | |
4021 | for (i = 0; i < nr; i++) | |
e6e52be0 R |
4022 | /* But don't do this if the reg actually serves as an output |
4023 | reload reg in the current instruction. */ | |
4024 | if (n_reloads == 0 | |
4025 | || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)) | |
4026 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i); | |
32131a9c RK |
4027 | } |
4028 | ||
4029 | /* Since value of X has changed, | |
4030 | forget any value previously copied from it. */ | |
4031 | ||
4032 | while (nr-- > 0) | |
4033 | /* But don't forget a copy if this is the output reload | |
4034 | that establishes the copy's validity. */ | |
4035 | if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0) | |
4036 | reg_last_reload_reg[regno + nr] = 0; | |
4037 | } | |
4038 | \f | |
32131a9c RK |
4039 | /* The following HARD_REG_SETs indicate when each hard register is |
4040 | used for a reload of various parts of the current insn. */ | |
4041 | ||
9e3a9cf2 BS |
4042 | /* If reg is unavailable for all reloads. */ |
4043 | static HARD_REG_SET reload_reg_unavailable; | |
32131a9c RK |
4044 | /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ |
4045 | static HARD_REG_SET reload_reg_used; | |
546b63fb RK |
4046 | /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ |
4047 | static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4048 | /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */ |
4049 | static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4050 | /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ |
4051 | static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; | |
47c8cf91 ILT |
4052 | /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */ |
4053 | static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; | |
546b63fb RK |
4054 | /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ |
4055 | static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; | |
4056 | /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ | |
4057 | static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; | |
32131a9c RK |
4058 | /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ |
4059 | static HARD_REG_SET reload_reg_used_in_op_addr; | |
893bc853 RK |
4060 | /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */ |
4061 | static HARD_REG_SET reload_reg_used_in_op_addr_reload; | |
546b63fb RK |
4062 | /* If reg is in use for a RELOAD_FOR_INSN reload. */ |
4063 | static HARD_REG_SET reload_reg_used_in_insn; | |
4064 | /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ | |
4065 | static HARD_REG_SET reload_reg_used_in_other_addr; | |
32131a9c RK |
4066 | |
4067 | /* If reg is in use as a reload reg for any sort of reload. */ | |
4068 | static HARD_REG_SET reload_reg_used_at_all; | |
4069 | ||
be7ae2a4 RK |
4070 | /* If reg is use as an inherited reload. We just mark the first register |
4071 | in the group. */ | |
4072 | static HARD_REG_SET reload_reg_used_for_inherit; | |
4073 | ||
f1db3576 JL |
4074 | /* Records which hard regs are used in any way, either as explicit use or |
4075 | by being allocated to a pseudo during any point of the current insn. */ | |
4076 | static HARD_REG_SET reg_used_in_insn; | |
297927a8 | 4077 | |
546b63fb RK |
4078 | /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and |
4079 | TYPE. MODE is used to indicate how many consecutive regs are | |
4080 | actually used. */ | |
32131a9c RK |
4081 | |
4082 | static void | |
546b63fb | 4083 | mark_reload_reg_in_use (regno, opnum, type, mode) |
770ae6cc | 4084 | unsigned int regno; |
546b63fb RK |
4085 | int opnum; |
4086 | enum reload_type type; | |
32131a9c RK |
4087 | enum machine_mode mode; |
4088 | { | |
770ae6cc RK |
4089 | unsigned int nregs = HARD_REGNO_NREGS (regno, mode); |
4090 | unsigned int i; | |
32131a9c RK |
4091 | |
4092 | for (i = regno; i < nregs + regno; i++) | |
4093 | { | |
546b63fb | 4094 | switch (type) |
32131a9c RK |
4095 | { |
4096 | case RELOAD_OTHER: | |
4097 | SET_HARD_REG_BIT (reload_reg_used, i); | |
4098 | break; | |
4099 | ||
546b63fb RK |
4100 | case RELOAD_FOR_INPUT_ADDRESS: |
4101 | SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); | |
32131a9c RK |
4102 | break; |
4103 | ||
47c8cf91 ILT |
4104 | case RELOAD_FOR_INPADDR_ADDRESS: |
4105 | SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i); | |
4106 | break; | |
4107 | ||
546b63fb RK |
4108 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4109 | SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); | |
32131a9c RK |
4110 | break; |
4111 | ||
47c8cf91 ILT |
4112 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4113 | SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i); | |
4114 | break; | |
4115 | ||
32131a9c RK |
4116 | case RELOAD_FOR_OPERAND_ADDRESS: |
4117 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); | |
4118 | break; | |
4119 | ||
893bc853 RK |
4120 | case RELOAD_FOR_OPADDR_ADDR: |
4121 | SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i); | |
4122 | break; | |
4123 | ||
546b63fb RK |
4124 | case RELOAD_FOR_OTHER_ADDRESS: |
4125 | SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i); | |
4126 | break; | |
4127 | ||
32131a9c | 4128 | case RELOAD_FOR_INPUT: |
546b63fb | 4129 | SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); |
32131a9c RK |
4130 | break; |
4131 | ||
4132 | case RELOAD_FOR_OUTPUT: | |
546b63fb RK |
4133 | SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); |
4134 | break; | |
4135 | ||
4136 | case RELOAD_FOR_INSN: | |
4137 | SET_HARD_REG_BIT (reload_reg_used_in_insn, i); | |
32131a9c RK |
4138 | break; |
4139 | } | |
4140 | ||
4141 | SET_HARD_REG_BIT (reload_reg_used_at_all, i); | |
4142 | } | |
4143 | } | |
4144 | ||
be7ae2a4 RK |
4145 | /* Similarly, but show REGNO is no longer in use for a reload. */ |
4146 | ||
4147 | static void | |
4148 | clear_reload_reg_in_use (regno, opnum, type, mode) | |
770ae6cc | 4149 | unsigned int regno; |
be7ae2a4 RK |
4150 | int opnum; |
4151 | enum reload_type type; | |
4152 | enum machine_mode mode; | |
4153 | { | |
770ae6cc RK |
4154 | unsigned int nregs = HARD_REGNO_NREGS (regno, mode); |
4155 | unsigned int start_regno, end_regno, r; | |
be7ae2a4 | 4156 | int i; |
cb2afeb3 R |
4157 | /* A complication is that for some reload types, inheritance might |
4158 | allow multiple reloads of the same types to share a reload register. | |
4159 | We set check_opnum if we have to check only reloads with the same | |
4160 | operand number, and check_any if we have to check all reloads. */ | |
4161 | int check_opnum = 0; | |
4162 | int check_any = 0; | |
4163 | HARD_REG_SET *used_in_set; | |
be7ae2a4 | 4164 | |
cb2afeb3 | 4165 | switch (type) |
be7ae2a4 | 4166 | { |
cb2afeb3 R |
4167 | case RELOAD_OTHER: |
4168 | used_in_set = &reload_reg_used; | |
4169 | break; | |
be7ae2a4 | 4170 | |
cb2afeb3 R |
4171 | case RELOAD_FOR_INPUT_ADDRESS: |
4172 | used_in_set = &reload_reg_used_in_input_addr[opnum]; | |
4173 | break; | |
be7ae2a4 | 4174 | |
cb2afeb3 R |
4175 | case RELOAD_FOR_INPADDR_ADDRESS: |
4176 | check_opnum = 1; | |
4177 | used_in_set = &reload_reg_used_in_inpaddr_addr[opnum]; | |
4178 | break; | |
47c8cf91 | 4179 | |
cb2afeb3 R |
4180 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4181 | used_in_set = &reload_reg_used_in_output_addr[opnum]; | |
4182 | break; | |
be7ae2a4 | 4183 | |
cb2afeb3 R |
4184 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4185 | check_opnum = 1; | |
4186 | used_in_set = &reload_reg_used_in_outaddr_addr[opnum]; | |
4187 | break; | |
47c8cf91 | 4188 | |
cb2afeb3 R |
4189 | case RELOAD_FOR_OPERAND_ADDRESS: |
4190 | used_in_set = &reload_reg_used_in_op_addr; | |
4191 | break; | |
be7ae2a4 | 4192 | |
cb2afeb3 R |
4193 | case RELOAD_FOR_OPADDR_ADDR: |
4194 | check_any = 1; | |
4195 | used_in_set = &reload_reg_used_in_op_addr_reload; | |
4196 | break; | |
893bc853 | 4197 | |
cb2afeb3 R |
4198 | case RELOAD_FOR_OTHER_ADDRESS: |
4199 | used_in_set = &reload_reg_used_in_other_addr; | |
4200 | check_any = 1; | |
4201 | break; | |
be7ae2a4 | 4202 | |
cb2afeb3 R |
4203 | case RELOAD_FOR_INPUT: |
4204 | used_in_set = &reload_reg_used_in_input[opnum]; | |
4205 | break; | |
be7ae2a4 | 4206 | |
cb2afeb3 R |
4207 | case RELOAD_FOR_OUTPUT: |
4208 | used_in_set = &reload_reg_used_in_output[opnum]; | |
4209 | break; | |
be7ae2a4 | 4210 | |
cb2afeb3 R |
4211 | case RELOAD_FOR_INSN: |
4212 | used_in_set = &reload_reg_used_in_insn; | |
4213 | break; | |
4214 | default: | |
4215 | abort (); | |
4216 | } | |
4217 | /* We resolve conflicts with remaining reloads of the same type by | |
4218 | excluding the intervals of of reload registers by them from the | |
4219 | interval of freed reload registers. Since we only keep track of | |
4220 | one set of interval bounds, we might have to exclude somewhat | |
4221 | more then what would be necessary if we used a HARD_REG_SET here. | |
4222 | But this should only happen very infrequently, so there should | |
4223 | be no reason to worry about it. */ | |
05d10675 | 4224 | |
cb2afeb3 R |
4225 | start_regno = regno; |
4226 | end_regno = regno + nregs; | |
4227 | if (check_opnum || check_any) | |
4228 | { | |
4229 | for (i = n_reloads - 1; i >= 0; i--) | |
4230 | { | |
eceef4c9 BS |
4231 | if (rld[i].when_needed == type |
4232 | && (check_any || rld[i].opnum == opnum) | |
4233 | && rld[i].reg_rtx) | |
cb2afeb3 | 4234 | { |
770ae6cc RK |
4235 | unsigned int conflict_start = true_regnum (rld[i].reg_rtx); |
4236 | unsigned int conflict_end | |
cb2afeb3 | 4237 | = (conflict_start |
8ec450a4 | 4238 | + HARD_REGNO_NREGS (conflict_start, rld[i].mode)); |
cb2afeb3 R |
4239 | |
4240 | /* If there is an overlap with the first to-be-freed register, | |
4241 | adjust the interval start. */ | |
4242 | if (conflict_start <= start_regno && conflict_end > start_regno) | |
4243 | start_regno = conflict_end; | |
4244 | /* Otherwise, if there is a conflict with one of the other | |
4245 | to-be-freed registers, adjust the interval end. */ | |
4246 | if (conflict_start > start_regno && conflict_start < end_regno) | |
4247 | end_regno = conflict_start; | |
4248 | } | |
be7ae2a4 RK |
4249 | } |
4250 | } | |
770ae6cc RK |
4251 | |
4252 | for (r = start_regno; r < end_regno; r++) | |
4253 | CLEAR_HARD_REG_BIT (*used_in_set, r); | |
be7ae2a4 RK |
4254 | } |
4255 | ||
32131a9c | 4256 | /* 1 if reg REGNO is free as a reload reg for a reload of the sort |
546b63fb | 4257 | specified by OPNUM and TYPE. */ |
32131a9c RK |
4258 | |
4259 | static int | |
546b63fb | 4260 | reload_reg_free_p (regno, opnum, type) |
770ae6cc | 4261 | unsigned int regno; |
546b63fb RK |
4262 | int opnum; |
4263 | enum reload_type type; | |
32131a9c | 4264 | { |
546b63fb RK |
4265 | int i; |
4266 | ||
2edc8d65 | 4267 | /* In use for a RELOAD_OTHER means it's not available for anything. */ |
9e3a9cf2 BS |
4268 | if (TEST_HARD_REG_BIT (reload_reg_used, regno) |
4269 | || TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) | |
32131a9c | 4270 | return 0; |
546b63fb RK |
4271 | |
4272 | switch (type) | |
32131a9c RK |
4273 | { |
4274 | case RELOAD_OTHER: | |
2edc8d65 RK |
4275 | /* In use for anything means we can't use it for RELOAD_OTHER. */ |
4276 | if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) | |
224f1d71 RK |
4277 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4278 | || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) | |
4279 | return 0; | |
4280 | ||
4281 | for (i = 0; i < reload_n_operands; i++) | |
4282 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4283 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
224f1d71 | 4284 | || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
47c8cf91 | 4285 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
224f1d71 RK |
4286 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) |
4287 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4288 | return 0; | |
4289 | ||
4290 | return 1; | |
32131a9c | 4291 | |
32131a9c | 4292 | case RELOAD_FOR_INPUT: |
546b63fb RK |
4293 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) |
4294 | || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) | |
4295 | return 0; | |
4296 | ||
893bc853 RK |
4297 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4298 | return 0; | |
4299 | ||
546b63fb RK |
4300 | /* If it is used for some other input, can't use it. */ |
4301 | for (i = 0; i < reload_n_operands; i++) | |
4302 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4303 | return 0; | |
4304 | ||
4305 | /* If it is used in a later operand's address, can't use it. */ | |
4306 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4307 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4308 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4309 | return 0; |
4310 | ||
4311 | return 1; | |
4312 | ||
4313 | case RELOAD_FOR_INPUT_ADDRESS: | |
4314 | /* Can't use a register if it is used for an input address for this | |
4315 | operand or used as an input in an earlier one. */ | |
47c8cf91 ILT |
4316 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno) |
4317 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) | |
4318 | return 0; | |
4319 | ||
4320 | for (i = 0; i < opnum; i++) | |
4321 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4322 | return 0; | |
4323 | ||
4324 | return 1; | |
4325 | ||
4326 | case RELOAD_FOR_INPADDR_ADDRESS: | |
4327 | /* Can't use a register if it is used for an input address | |
05d10675 BS |
4328 | for this operand or used as an input in an earlier |
4329 | one. */ | |
47c8cf91 | 4330 | if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) |
546b63fb RK |
4331 | return 0; |
4332 | ||
4333 | for (i = 0; i < opnum; i++) | |
4334 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4335 | return 0; | |
4336 | ||
4337 | return 1; | |
4338 | ||
4339 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
4340 | /* Can't use a register if it is used for an output address for this | |
4341 | operand or used as an output in this or a later operand. */ | |
4342 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) | |
4343 | return 0; | |
4344 | ||
4345 | for (i = opnum; i < reload_n_operands; i++) | |
4346 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4347 | return 0; | |
4348 | ||
4349 | return 1; | |
4350 | ||
47c8cf91 ILT |
4351 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4352 | /* Can't use a register if it is used for an output address | |
05d10675 BS |
4353 | for this operand or used as an output in this or a |
4354 | later operand. */ | |
47c8cf91 ILT |
4355 | if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) |
4356 | return 0; | |
4357 | ||
4358 | for (i = opnum; i < reload_n_operands; i++) | |
4359 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4360 | return 0; | |
4361 | ||
4362 | return 1; | |
4363 | ||
32131a9c | 4364 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4365 | for (i = 0; i < reload_n_operands; i++) |
4366 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4367 | return 0; | |
4368 | ||
4369 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4370 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4371 | ||
893bc853 RK |
4372 | case RELOAD_FOR_OPADDR_ADDR: |
4373 | for (i = 0; i < reload_n_operands; i++) | |
05d10675 BS |
4374 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4375 | return 0; | |
893bc853 | 4376 | |
a94ce333 | 4377 | return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)); |
893bc853 | 4378 | |
32131a9c | 4379 | case RELOAD_FOR_OUTPUT: |
546b63fb RK |
4380 | /* This cannot share a register with RELOAD_FOR_INSN reloads, other |
4381 | outputs, or an operand address for this or an earlier output. */ | |
4382 | if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) | |
4383 | return 0; | |
4384 | ||
4385 | for (i = 0; i < reload_n_operands; i++) | |
4386 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4387 | return 0; | |
4388 | ||
4389 | for (i = 0; i <= opnum; i++) | |
47c8cf91 ILT |
4390 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4391 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4392 | return 0; |
4393 | ||
4394 | return 1; | |
4395 | ||
4396 | case RELOAD_FOR_INSN: | |
4397 | for (i = 0; i < reload_n_operands; i++) | |
4398 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) | |
4399 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) | |
4400 | return 0; | |
4401 | ||
4402 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4403 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); | |
4404 | ||
4405 | case RELOAD_FOR_OTHER_ADDRESS: | |
4406 | return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); | |
32131a9c RK |
4407 | } |
4408 | abort (); | |
4409 | } | |
4410 | ||
32131a9c | 4411 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
546b63fb | 4412 | needed for the part of the insn specified by OPNUM and TYPE, |
32131a9c RK |
4413 | is still available in REGNO at the end of the insn. |
4414 | ||
4415 | We can assume that the reload reg was already tested for availability | |
4416 | at the time it is needed, and we should not check this again, | |
4417 | in case the reg has already been marked in use. */ | |
4418 | ||
4419 | static int | |
546b63fb | 4420 | reload_reg_reaches_end_p (regno, opnum, type) |
770ae6cc | 4421 | unsigned int regno; |
546b63fb RK |
4422 | int opnum; |
4423 | enum reload_type type; | |
32131a9c | 4424 | { |
546b63fb RK |
4425 | int i; |
4426 | ||
4427 | switch (type) | |
32131a9c RK |
4428 | { |
4429 | case RELOAD_OTHER: | |
4430 | /* Since a RELOAD_OTHER reload claims the reg for the entire insn, | |
4431 | its value must reach the end. */ | |
4432 | return 1; | |
4433 | ||
4434 | /* If this use is for part of the insn, | |
05d10675 | 4435 | its value reaches if no subsequent part uses the same register. |
546b63fb RK |
4436 | Just like the above function, don't try to do this with lots |
4437 | of fallthroughs. */ | |
4438 | ||
4439 | case RELOAD_FOR_OTHER_ADDRESS: | |
4440 | /* Here we check for everything else, since these don't conflict | |
4441 | with anything else and everything comes later. */ | |
4442 | ||
4443 | for (i = 0; i < reload_n_operands; i++) | |
4444 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4445 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4446 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) |
4447 | || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4448 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4449 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4450 | return 0; | |
4451 | ||
4452 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) | |
4453 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) | |
4454 | && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); | |
4455 | ||
4456 | case RELOAD_FOR_INPUT_ADDRESS: | |
47c8cf91 | 4457 | case RELOAD_FOR_INPADDR_ADDRESS: |
546b63fb RK |
4458 | /* Similar, except that we check only for this and subsequent inputs |
4459 | and the address of only subsequent inputs and we do not need | |
4460 | to check for RELOAD_OTHER objects since they are known not to | |
4461 | conflict. */ | |
4462 | ||
4463 | for (i = opnum; i < reload_n_operands; i++) | |
4464 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) | |
4465 | return 0; | |
4466 | ||
4467 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4468 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) |
4469 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) | |
546b63fb RK |
4470 | return 0; |
4471 | ||
4472 | for (i = 0; i < reload_n_operands; i++) | |
4473 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4474 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4475 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4476 | return 0; | |
4477 | ||
893bc853 RK |
4478 | if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) |
4479 | return 0; | |
4480 | ||
546b63fb RK |
4481 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4482 | && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)); | |
4483 | ||
32131a9c | 4484 | case RELOAD_FOR_INPUT: |
546b63fb | 4485 | /* Similar to input address, except we start at the next operand for |
05d10675 | 4486 | both input and input address and we do not check for |
546b63fb RK |
4487 | RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these |
4488 | would conflict. */ | |
4489 | ||
4490 | for (i = opnum + 1; i < reload_n_operands; i++) | |
4491 | if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) | |
47c8cf91 | 4492 | || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) |
546b63fb RK |
4493 | || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) |
4494 | return 0; | |
4495 | ||
0f41302f | 4496 | /* ... fall through ... */ |
546b63fb | 4497 | |
32131a9c | 4498 | case RELOAD_FOR_OPERAND_ADDRESS: |
546b63fb RK |
4499 | /* Check outputs and their addresses. */ |
4500 | ||
4501 | for (i = 0; i < reload_n_operands; i++) | |
4502 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4503 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
546b63fb RK |
4504 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4505 | return 0; | |
4506 | ||
4507 | return 1; | |
4508 | ||
893bc853 RK |
4509 | case RELOAD_FOR_OPADDR_ADDR: |
4510 | for (i = 0; i < reload_n_operands; i++) | |
4511 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) | |
47c8cf91 | 4512 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) |
893bc853 RK |
4513 | || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) |
4514 | return 0; | |
4515 | ||
a94ce333 JW |
4516 | return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) |
4517 | && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)); | |
893bc853 | 4518 | |
546b63fb | 4519 | case RELOAD_FOR_INSN: |
893bc853 | 4520 | /* These conflict with other outputs with RELOAD_OTHER. So |
546b63fb RK |
4521 | we need only check for output addresses. */ |
4522 | ||
4523 | opnum = -1; | |
4524 | ||
0f41302f | 4525 | /* ... fall through ... */ |
546b63fb | 4526 | |
32131a9c | 4527 | case RELOAD_FOR_OUTPUT: |
546b63fb | 4528 | case RELOAD_FOR_OUTPUT_ADDRESS: |
47c8cf91 | 4529 | case RELOAD_FOR_OUTADDR_ADDRESS: |
546b63fb RK |
4530 | /* We already know these can't conflict with a later output. So the |
4531 | only thing to check are later output addresses. */ | |
4532 | for (i = opnum + 1; i < reload_n_operands; i++) | |
47c8cf91 ILT |
4533 | if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) |
4534 | || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) | |
546b63fb RK |
4535 | return 0; |
4536 | ||
32131a9c RK |
4537 | return 1; |
4538 | } | |
546b63fb | 4539 | |
32131a9c RK |
4540 | abort (); |
4541 | } | |
4542 | \f | |
351aa1c1 RK |
4543 | /* Return 1 if the reloads denoted by R1 and R2 cannot share a register. |
4544 | Return 0 otherwise. | |
4545 | ||
4546 | This function uses the same algorithm as reload_reg_free_p above. */ | |
4547 | ||
f5963e61 | 4548 | int |
351aa1c1 RK |
4549 | reloads_conflict (r1, r2) |
4550 | int r1, r2; | |
4551 | { | |
eceef4c9 BS |
4552 | enum reload_type r1_type = rld[r1].when_needed; |
4553 | enum reload_type r2_type = rld[r2].when_needed; | |
4554 | int r1_opnum = rld[r1].opnum; | |
4555 | int r2_opnum = rld[r2].opnum; | |
351aa1c1 | 4556 | |
2edc8d65 RK |
4557 | /* RELOAD_OTHER conflicts with everything. */ |
4558 | if (r2_type == RELOAD_OTHER) | |
351aa1c1 RK |
4559 | return 1; |
4560 | ||
4561 | /* Otherwise, check conflicts differently for each type. */ | |
4562 | ||
4563 | switch (r1_type) | |
4564 | { | |
4565 | case RELOAD_FOR_INPUT: | |
05d10675 | 4566 | return (r2_type == RELOAD_FOR_INSN |
351aa1c1 | 4567 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS |
893bc853 | 4568 | || r2_type == RELOAD_FOR_OPADDR_ADDR |
351aa1c1 | 4569 | || r2_type == RELOAD_FOR_INPUT |
47c8cf91 ILT |
4570 | || ((r2_type == RELOAD_FOR_INPUT_ADDRESS |
4571 | || r2_type == RELOAD_FOR_INPADDR_ADDRESS) | |
4572 | && r2_opnum > r1_opnum)); | |
351aa1c1 RK |
4573 | |
4574 | case RELOAD_FOR_INPUT_ADDRESS: | |
4575 | return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum) | |
4576 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
4577 | ||
47c8cf91 ILT |
4578 | case RELOAD_FOR_INPADDR_ADDRESS: |
4579 | return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum) | |
4580 | || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); | |
4581 | ||
351aa1c1 RK |
4582 | case RELOAD_FOR_OUTPUT_ADDRESS: |
4583 | return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum) | |
4584 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum)); | |
4585 | ||
47c8cf91 ILT |
4586 | case RELOAD_FOR_OUTADDR_ADDRESS: |
4587 | return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum) | |
4588 | || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum)); | |
4589 | ||
351aa1c1 RK |
4590 | case RELOAD_FOR_OPERAND_ADDRESS: |
4591 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN | |
a94ce333 | 4592 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); |
351aa1c1 | 4593 | |
893bc853 | 4594 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 | 4595 | return (r2_type == RELOAD_FOR_INPUT |
a94ce333 | 4596 | || r2_type == RELOAD_FOR_OPADDR_ADDR); |
893bc853 | 4597 | |
351aa1c1 RK |
4598 | case RELOAD_FOR_OUTPUT: |
4599 | return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT | |
47c8cf91 ILT |
4600 | || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS |
4601 | || r2_type == RELOAD_FOR_OUTADDR_ADDRESS) | |
ca1a4af1 | 4602 | && r2_opnum <= r1_opnum)); |
351aa1c1 RK |
4603 | |
4604 | case RELOAD_FOR_INSN: | |
4605 | return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT | |
4606 | || r2_type == RELOAD_FOR_INSN | |
4607 | || r2_type == RELOAD_FOR_OPERAND_ADDRESS); | |
4608 | ||
4609 | case RELOAD_FOR_OTHER_ADDRESS: | |
4610 | return r2_type == RELOAD_FOR_OTHER_ADDRESS; | |
4611 | ||
adab4fc5 | 4612 | case RELOAD_OTHER: |
2edc8d65 | 4613 | return 1; |
adab4fc5 | 4614 | |
351aa1c1 RK |
4615 | default: |
4616 | abort (); | |
4617 | } | |
4618 | } | |
4619 | \f | |
32131a9c RK |
4620 | /* Indexed by reload number, 1 if incoming value |
4621 | inherited from previous insns. */ | |
4622 | char reload_inherited[MAX_RELOADS]; | |
4623 | ||
4624 | /* For an inherited reload, this is the insn the reload was inherited from, | |
4625 | if we know it. Otherwise, this is 0. */ | |
4626 | rtx reload_inheritance_insn[MAX_RELOADS]; | |
4627 | ||
4628 | /* If non-zero, this is a place to get the value of the reload, | |
4629 | rather than using reload_in. */ | |
4630 | rtx reload_override_in[MAX_RELOADS]; | |
4631 | ||
e6e52be0 R |
4632 | /* For each reload, the hard register number of the register used, |
4633 | or -1 if we did not need a register for this reload. */ | |
32131a9c RK |
4634 | int reload_spill_index[MAX_RELOADS]; |
4635 | ||
6e684430 R |
4636 | /* Return 1 if the value in reload reg REGNO, as used by a reload |
4637 | needed for the part of the insn specified by OPNUM and TYPE, | |
4638 | may be used to load VALUE into it. | |
f5470689 R |
4639 | |
4640 | Other read-only reloads with the same value do not conflict | |
4641 | unless OUT is non-zero and these other reloads have to live while | |
4642 | output reloads live. | |
dfe96118 R |
4643 | If OUT is CONST0_RTX, this is a special case: it means that the |
4644 | test should not be for using register REGNO as reload register, but | |
4645 | for copying from register REGNO into the reload register. | |
f5470689 R |
4646 | |
4647 | RELOADNUM is the number of the reload we want to load this value for; | |
4648 | a reload does not conflict with itself. | |
4649 | ||
dfe96118 R |
4650 | When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with |
4651 | reloads that load an address for the very reload we are considering. | |
4652 | ||
6e684430 R |
4653 | The caller has to make sure that there is no conflict with the return |
4654 | register. */ | |
4655 | static int | |
dfe96118 | 4656 | reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum, |
05d10675 | 4657 | ignore_address_reloads) |
6e684430 R |
4658 | int regno; |
4659 | int opnum; | |
4660 | enum reload_type type; | |
f5470689 R |
4661 | rtx value, out; |
4662 | int reloadnum; | |
5828374f | 4663 | int ignore_address_reloads; |
6e684430 R |
4664 | { |
4665 | int time1; | |
09a308fe R |
4666 | /* Set if we see an input reload that must not share its reload register |
4667 | with any new earlyclobber, but might otherwise share the reload | |
4668 | register with an output or input-output reload. */ | |
4669 | int check_earlyclobber = 0; | |
6e684430 | 4670 | int i; |
dfe96118 R |
4671 | int copy = 0; |
4672 | ||
9e3a9cf2 | 4673 | if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) |
dc8842bf AH |
4674 | return 0; |
4675 | ||
dfe96118 R |
4676 | if (out == const0_rtx) |
4677 | { | |
4678 | copy = 1; | |
4679 | out = NULL_RTX; | |
4680 | } | |
6e684430 R |
4681 | |
4682 | /* We use some pseudo 'time' value to check if the lifetimes of the | |
4683 | new register use would overlap with the one of a previous reload | |
4684 | that is not read-only or uses a different value. | |
4685 | The 'time' used doesn't have to be linear in any shape or form, just | |
4686 | monotonic. | |
4687 | Some reload types use different 'buckets' for each operand. | |
4688 | So there are MAX_RECOG_OPERANDS different time values for each | |
cecbf6e2 R |
4689 | such reload type. |
4690 | We compute TIME1 as the time when the register for the prospective | |
4691 | new reload ceases to be live, and TIME2 for each existing | |
4692 | reload as the time when that the reload register of that reload | |
4693 | becomes live. | |
4694 | Where there is little to be gained by exact lifetime calculations, | |
4695 | we just make conservative assumptions, i.e. a longer lifetime; | |
4696 | this is done in the 'default:' cases. */ | |
6e684430 R |
4697 | switch (type) |
4698 | { | |
4699 | case RELOAD_FOR_OTHER_ADDRESS: | |
203588e7 | 4700 | /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */ |
c2b4b171 | 4701 | time1 = copy ? 0 : 1; |
6e684430 | 4702 | break; |
dfe96118 R |
4703 | case RELOAD_OTHER: |
4704 | time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5; | |
4705 | break; | |
05d10675 BS |
4706 | /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS, |
4707 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 , | |
4708 | respectively, to the time values for these, we get distinct time | |
4709 | values. To get distinct time values for each operand, we have to | |
4710 | multiply opnum by at least three. We round that up to four because | |
4711 | multiply by four is often cheaper. */ | |
6e684430 | 4712 | case RELOAD_FOR_INPADDR_ADDRESS: |
dfe96118 | 4713 | time1 = opnum * 4 + 2; |
6e684430 R |
4714 | break; |
4715 | case RELOAD_FOR_INPUT_ADDRESS: | |
dfe96118 R |
4716 | time1 = opnum * 4 + 3; |
4717 | break; | |
4718 | case RELOAD_FOR_INPUT: | |
4719 | /* All RELOAD_FOR_INPUT reloads remain live till the instruction | |
4720 | executes (inclusive). */ | |
4721 | time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3; | |
6e684430 | 4722 | break; |
cb2afeb3 | 4723 | case RELOAD_FOR_OPADDR_ADDR: |
05d10675 BS |
4724 | /* opnum * 4 + 4 |
4725 | <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */ | |
cb2afeb3 R |
4726 | time1 = MAX_RECOG_OPERANDS * 4 + 1; |
4727 | break; | |
4728 | case RELOAD_FOR_OPERAND_ADDRESS: | |
4729 | /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn | |
4730 | is executed. */ | |
dfe96118 R |
4731 | time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3; |
4732 | break; | |
4733 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
4734 | time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum; | |
6e684430 | 4735 | break; |
6e684430 | 4736 | case RELOAD_FOR_OUTPUT_ADDRESS: |
dfe96118 | 4737 | time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum; |
6e684430 R |
4738 | break; |
4739 | default: | |
dfe96118 | 4740 | time1 = MAX_RECOG_OPERANDS * 5 + 5; |
6e684430 R |
4741 | } |
4742 | ||
4743 | for (i = 0; i < n_reloads; i++) | |
4744 | { | |
eceef4c9 | 4745 | rtx reg = rld[i].reg_rtx; |
6e684430 R |
4746 | if (reg && GET_CODE (reg) == REG |
4747 | && ((unsigned) regno - true_regnum (reg) | |
83e0821b | 4748 | <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1) |
f5470689 | 4749 | && i != reloadnum) |
6e684430 | 4750 | { |
eceef4c9 BS |
4751 | if (! rld[i].in || ! rtx_equal_p (rld[i].in, value) |
4752 | || rld[i].out || out) | |
6e684430 | 4753 | { |
09a308fe | 4754 | int time2; |
eceef4c9 | 4755 | switch (rld[i].when_needed) |
f5470689 R |
4756 | { |
4757 | case RELOAD_FOR_OTHER_ADDRESS: | |
4758 | time2 = 0; | |
4759 | break; | |
4760 | case RELOAD_FOR_INPADDR_ADDRESS: | |
cb2afeb3 R |
4761 | /* find_reloads makes sure that a |
4762 | RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used | |
4763 | by at most one - the first - | |
4764 | RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the | |
4765 | address reload is inherited, the address address reload | |
4766 | goes away, so we can ignore this conflict. */ | |
dfe96118 R |
4767 | if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1 |
4768 | && ignore_address_reloads | |
4769 | /* Unless the RELOAD_FOR_INPUT is an auto_inc expression. | |
4770 | Then the address address is still needed to store | |
4771 | back the new address. */ | |
eceef4c9 | 4772 | && ! rld[reloadnum].out) |
cb2afeb3 | 4773 | continue; |
dfe96118 R |
4774 | /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its |
4775 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS | |
4776 | reloads go away. */ | |
eceef4c9 | 4777 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 R |
4778 | && ignore_address_reloads |
4779 | /* Unless we are reloading an auto_inc expression. */ | |
eceef4c9 | 4780 | && ! rld[reloadnum].out) |
dfe96118 | 4781 | continue; |
eceef4c9 | 4782 | time2 = rld[i].opnum * 4 + 2; |
f5470689 R |
4783 | break; |
4784 | case RELOAD_FOR_INPUT_ADDRESS: | |
eceef4c9 | 4785 | if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum |
dfe96118 | 4786 | && ignore_address_reloads |
eceef4c9 | 4787 | && ! rld[reloadnum].out) |
dfe96118 | 4788 | continue; |
eceef4c9 | 4789 | time2 = rld[i].opnum * 4 + 3; |
f5470689 R |
4790 | break; |
4791 | case RELOAD_FOR_INPUT: | |
eceef4c9 | 4792 | time2 = rld[i].opnum * 4 + 4; |
09a308fe | 4793 | check_earlyclobber = 1; |
f5470689 | 4794 | break; |
eceef4c9 | 4795 | /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4 |
05d10675 | 4796 | == MAX_RECOG_OPERAND * 4 */ |
cb2afeb3 | 4797 | case RELOAD_FOR_OPADDR_ADDR: |
dfe96118 R |
4798 | if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1 |
4799 | && ignore_address_reloads | |
eceef4c9 | 4800 | && ! rld[reloadnum].out) |
cb2afeb3 | 4801 | continue; |
dfe96118 | 4802 | time2 = MAX_RECOG_OPERANDS * 4 + 1; |
cb2afeb3 R |
4803 | break; |
4804 | case RELOAD_FOR_OPERAND_ADDRESS: | |
dfe96118 | 4805 | time2 = MAX_RECOG_OPERANDS * 4 + 2; |
09a308fe | 4806 | check_earlyclobber = 1; |
dfe96118 R |
4807 | break; |
4808 | case RELOAD_FOR_INSN: | |
4809 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
cb2afeb3 | 4810 | break; |
f5470689 | 4811 | case RELOAD_FOR_OUTPUT: |
05d10675 BS |
4812 | /* All RELOAD_FOR_OUTPUT reloads become live just after the |
4813 | instruction is executed. */ | |
dfe96118 | 4814 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
f5470689 | 4815 | break; |
05d10675 BS |
4816 | /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with |
4817 | the RELOAD_FOR_OUTPUT reloads, so assign it the same time | |
4818 | value. */ | |
cb2afeb3 | 4819 | case RELOAD_FOR_OUTADDR_ADDRESS: |
dfe96118 R |
4820 | if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1 |
4821 | && ignore_address_reloads | |
eceef4c9 | 4822 | && ! rld[reloadnum].out) |
cb2afeb3 | 4823 | continue; |
eceef4c9 | 4824 | time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum; |
dfe96118 | 4825 | break; |
f5470689 | 4826 | case RELOAD_FOR_OUTPUT_ADDRESS: |
eceef4c9 | 4827 | time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum; |
f5470689 R |
4828 | break; |
4829 | case RELOAD_OTHER: | |
dfe96118 R |
4830 | /* If there is no conflict in the input part, handle this |
4831 | like an output reload. */ | |
eceef4c9 | 4832 | if (! rld[i].in || rtx_equal_p (rld[i].in, value)) |
f5470689 | 4833 | { |
dfe96118 | 4834 | time2 = MAX_RECOG_OPERANDS * 4 + 4; |
57850c85 | 4835 | /* Earlyclobbered outputs must conflict with inputs. */ |
09a308fe R |
4836 | if (earlyclobber_operand_p (rld[i].out)) |
4837 | time2 = MAX_RECOG_OPERANDS * 4 + 3; | |
57850c85 | 4838 | |
f5470689 R |
4839 | break; |
4840 | } | |
dfe96118 R |
4841 | time2 = 1; |
4842 | /* RELOAD_OTHER might be live beyond instruction execution, | |
4843 | but this is not obvious when we set time2 = 1. So check | |
4844 | here if there might be a problem with the new reload | |
4845 | clobbering the register used by the RELOAD_OTHER. */ | |
4846 | if (out) | |
4847 | return 0; | |
4848 | break; | |
f5470689 | 4849 | default: |
dfe96118 | 4850 | return 0; |
f5470689 | 4851 | } |
25963977 | 4852 | if ((time1 >= time2 |
eceef4c9 BS |
4853 | && (! rld[i].in || rld[i].out |
4854 | || ! rtx_equal_p (rld[i].in, value))) | |
4855 | || (out && rld[reloadnum].out_reg | |
701d55e8 | 4856 | && time2 >= MAX_RECOG_OPERANDS * 4 + 3)) |
f5470689 | 4857 | return 0; |
6e684430 | 4858 | } |
6e684430 R |
4859 | } |
4860 | } | |
09a308fe R |
4861 | |
4862 | /* Earlyclobbered outputs must conflict with inputs. */ | |
4863 | if (check_earlyclobber && out && earlyclobber_operand_p (out)) | |
4864 | return 0; | |
4865 | ||
6e684430 R |
4866 | return 1; |
4867 | } | |
4868 | ||
67e61fe7 BS |
4869 | /* Give an error message saying we failed to find a reload for INSN, |
4870 | and clear out reload R. */ | |
4871 | static void | |
4872 | failed_reload (insn, r) | |
4873 | rtx insn; | |
4874 | int r; | |
4875 | { | |
4876 | if (asm_noperands (PATTERN (insn)) < 0) | |
4877 | /* It's the compiler's fault. */ | |
4878 | fatal_insn ("Could not find a spill register", insn); | |
4879 | ||
4880 | /* It's the user's fault; the operand's mode and constraint | |
4881 | don't match. Disable this reload so we don't crash in final. */ | |
4882 | error_for_asm (insn, | |
4883 | "`asm' operand constraint incompatible with operand size"); | |
4884 | rld[r].in = 0; | |
4885 | rld[r].out = 0; | |
4886 | rld[r].reg_rtx = 0; | |
4887 | rld[r].optional = 1; | |
4888 | rld[r].secondary_p = 1; | |
4889 | } | |
4890 | ||
4891 | /* I is the index in SPILL_REG_RTX of the reload register we are to allocate | |
4892 | for reload R. If it's valid, get an rtx for it. Return nonzero if | |
4893 | successful. */ | |
4894 | static int | |
4895 | set_reload_reg (i, r) | |
4896 | int i, r; | |
4897 | { | |
4898 | int regno; | |
4899 | rtx reg = spill_reg_rtx[i]; | |
4900 | ||
4901 | if (reg == 0 || GET_MODE (reg) != rld[r].mode) | |
4902 | spill_reg_rtx[i] = reg | |
4903 | = gen_rtx_REG (rld[r].mode, spill_regs[i]); | |
4904 | ||
4905 | regno = true_regnum (reg); | |
4906 | ||
4907 | /* Detect when the reload reg can't hold the reload mode. | |
4908 | This used to be one `if', but Sequent compiler can't handle that. */ | |
4909 | if (HARD_REGNO_MODE_OK (regno, rld[r].mode)) | |
4910 | { | |
4911 | enum machine_mode test_mode = VOIDmode; | |
4912 | if (rld[r].in) | |
4913 | test_mode = GET_MODE (rld[r].in); | |
4914 | /* If rld[r].in has VOIDmode, it means we will load it | |
4915 | in whatever mode the reload reg has: to wit, rld[r].mode. | |
4916 | We have already tested that for validity. */ | |
4917 | /* Aside from that, we need to test that the expressions | |
4918 | to reload from or into have modes which are valid for this | |
4919 | reload register. Otherwise the reload insns would be invalid. */ | |
4920 | if (! (rld[r].in != 0 && test_mode != VOIDmode | |
4921 | && ! HARD_REGNO_MODE_OK (regno, test_mode))) | |
4922 | if (! (rld[r].out != 0 | |
4923 | && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out)))) | |
4924 | { | |
4925 | /* The reg is OK. */ | |
4926 | last_spill_reg = i; | |
4927 | ||
4928 | /* Mark as in use for this insn the reload regs we use | |
4929 | for this. */ | |
4930 | mark_reload_reg_in_use (spill_regs[i], rld[r].opnum, | |
4931 | rld[r].when_needed, rld[r].mode); | |
4932 | ||
4933 | rld[r].reg_rtx = reg; | |
4934 | reload_spill_index[r] = spill_regs[i]; | |
4935 | return 1; | |
4936 | } | |
4937 | } | |
4938 | return 0; | |
4939 | } | |
4940 | ||
32131a9c RK |
4941 | /* Find a spill register to use as a reload register for reload R. |
4942 | LAST_RELOAD is non-zero if this is the last reload for the insn being | |
4943 | processed. | |
4944 | ||
eceef4c9 | 4945 | Set rld[R].reg_rtx to the register allocated. |
32131a9c | 4946 | |
f5d8c9f4 BS |
4947 | We return 1 if successful, or 0 if we couldn't find a spill reg and |
4948 | we didn't change anything. */ | |
32131a9c RK |
4949 | |
4950 | static int | |
f5d8c9f4 | 4951 | allocate_reload_reg (chain, r, last_reload) |
272df862 | 4952 | struct insn_chain *chain ATTRIBUTE_UNUSED; |
32131a9c | 4953 | int r; |
32131a9c | 4954 | int last_reload; |
32131a9c | 4955 | { |
67e61fe7 | 4956 | int i, pass, count; |
32131a9c RK |
4957 | |
4958 | /* If we put this reload ahead, thinking it is a group, | |
4959 | then insist on finding a group. Otherwise we can grab a | |
a8fdc208 | 4960 | reg that some other reload needs. |
32131a9c RK |
4961 | (That can happen when we have a 68000 DATA_OR_FP_REG |
4962 | which is a group of data regs or one fp reg.) | |
4963 | We need not be so restrictive if there are no more reloads | |
4964 | for this insn. | |
4965 | ||
4966 | ??? Really it would be nicer to have smarter handling | |
4967 | for that kind of reg class, where a problem like this is normal. | |
4968 | Perhaps those classes should be avoided for reloading | |
4969 | by use of more alternatives. */ | |
4970 | ||
8ec450a4 | 4971 | int force_group = rld[r].nregs > 1 && ! last_reload; |
32131a9c RK |
4972 | |
4973 | /* If we want a single register and haven't yet found one, | |
4974 | take any reg in the right class and not in use. | |
4975 | If we want a consecutive group, here is where we look for it. | |
4976 | ||
4977 | We use two passes so we can first look for reload regs to | |
4978 | reuse, which are already in use for other reloads in this insn, | |
4979 | and only then use additional registers. | |
4980 | I think that maximizing reuse is needed to make sure we don't | |
4981 | run out of reload regs. Suppose we have three reloads, and | |
4982 | reloads A and B can share regs. These need two regs. | |
4983 | Suppose A and B are given different regs. | |
4984 | That leaves none for C. */ | |
4985 | for (pass = 0; pass < 2; pass++) | |
4986 | { | |
4987 | /* I is the index in spill_regs. | |
4988 | We advance it round-robin between insns to use all spill regs | |
4989 | equally, so that inherited reloads have a chance | |
f5d8c9f4 BS |
4990 | of leapfrogging each other. */ |
4991 | ||
4992 | i = last_spill_reg; | |
05d10675 | 4993 | |
a5339699 | 4994 | for (count = 0; count < n_spills; count++) |
32131a9c | 4995 | { |
eceef4c9 | 4996 | int class = (int) rld[r].class; |
03acd8f8 | 4997 | int regnum; |
32131a9c | 4998 | |
03acd8f8 BS |
4999 | i++; |
5000 | if (i >= n_spills) | |
5001 | i -= n_spills; | |
5002 | regnum = spill_regs[i]; | |
32131a9c | 5003 | |
eceef4c9 BS |
5004 | if ((reload_reg_free_p (regnum, rld[r].opnum, |
5005 | rld[r].when_needed) | |
5006 | || (rld[r].in | |
05d10675 BS |
5007 | /* We check reload_reg_used to make sure we |
5008 | don't clobber the return register. */ | |
03acd8f8 BS |
5009 | && ! TEST_HARD_REG_BIT (reload_reg_used, regnum) |
5010 | && reload_reg_free_for_value_p (regnum, | |
eceef4c9 BS |
5011 | rld[r].opnum, |
5012 | rld[r].when_needed, | |
5013 | rld[r].in, | |
5014 | rld[r].out, r, 1))) | |
03acd8f8 | 5015 | && TEST_HARD_REG_BIT (reg_class_contents[class], regnum) |
8ec450a4 | 5016 | && HARD_REGNO_MODE_OK (regnum, rld[r].mode) |
be7ae2a4 RK |
5017 | /* Look first for regs to share, then for unshared. But |
5018 | don't share regs used for inherited reloads; they are | |
5019 | the ones we want to preserve. */ | |
5020 | && (pass | |
5021 | || (TEST_HARD_REG_BIT (reload_reg_used_at_all, | |
03acd8f8 | 5022 | regnum) |
be7ae2a4 | 5023 | && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, |
03acd8f8 | 5024 | regnum)))) |
32131a9c | 5025 | { |
8ec450a4 | 5026 | int nr = HARD_REGNO_NREGS (regnum, rld[r].mode); |
32131a9c RK |
5027 | /* Avoid the problem where spilling a GENERAL_OR_FP_REG |
5028 | (on 68000) got us two FP regs. If NR is 1, | |
5029 | we would reject both of them. */ | |
5030 | if (force_group) | |
67e61fe7 | 5031 | nr = rld[r].nregs; |
32131a9c RK |
5032 | /* If we need only one reg, we have already won. */ |
5033 | if (nr == 1) | |
5034 | { | |
5035 | /* But reject a single reg if we demand a group. */ | |
5036 | if (force_group) | |
5037 | continue; | |
5038 | break; | |
5039 | } | |
5040 | /* Otherwise check that as many consecutive regs as we need | |
f5d8c9f4 BS |
5041 | are available here. */ |
5042 | while (nr > 1) | |
5043 | { | |
5044 | int regno = regnum + nr - 1; | |
5045 | if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno) | |
5046 | && spill_reg_order[regno] >= 0 | |
5047 | && reload_reg_free_p (regno, rld[r].opnum, | |
5048 | rld[r].when_needed))) | |
5049 | break; | |
5050 | nr--; | |
5051 | } | |
32131a9c RK |
5052 | if (nr == 1) |
5053 | break; | |
5054 | } | |
5055 | } | |
5056 | ||
5057 | /* If we found something on pass 1, omit pass 2. */ | |
5058 | if (count < n_spills) | |
5059 | break; | |
5060 | } | |
f5d8c9f4 | 5061 | |
32131a9c | 5062 | /* We should have found a spill register by now. */ |
f5d8c9f4 | 5063 | if (count >= n_spills) |
32131a9c RK |
5064 | return 0; |
5065 | ||
f5d8c9f4 BS |
5066 | /* I is the index in SPILL_REG_RTX of the reload register we are to |
5067 | allocate. Get an rtx for it and find its register number. */ | |
32131a9c | 5068 | |
f5d8c9f4 | 5069 | return set_reload_reg (i, r); |
32131a9c RK |
5070 | } |
5071 | \f | |
67e61fe7 BS |
5072 | /* Initialize all the tables needed to allocate reload registers. |
5073 | CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX | |
5074 | is the array we use to restore the reg_rtx field for every reload. */ | |
efc9bd41 | 5075 | |
32131a9c | 5076 | static void |
67e61fe7 | 5077 | choose_reload_regs_init (chain, save_reload_reg_rtx) |
7609e720 | 5078 | struct insn_chain *chain; |
67e61fe7 | 5079 | rtx *save_reload_reg_rtx; |
32131a9c | 5080 | { |
67e61fe7 | 5081 | int i; |
32131a9c | 5082 | |
67e61fe7 BS |
5083 | for (i = 0; i < n_reloads; i++) |
5084 | rld[i].reg_rtx = save_reload_reg_rtx[i]; | |
32131a9c RK |
5085 | |
5086 | bzero (reload_inherited, MAX_RELOADS); | |
4c9a05bc RK |
5087 | bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx)); |
5088 | bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx)); | |
32131a9c RK |
5089 | |
5090 | CLEAR_HARD_REG_SET (reload_reg_used); | |
5091 | CLEAR_HARD_REG_SET (reload_reg_used_at_all); | |
32131a9c | 5092 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); |
893bc853 | 5093 | CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload); |
546b63fb RK |
5094 | CLEAR_HARD_REG_SET (reload_reg_used_in_insn); |
5095 | CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); | |
32131a9c | 5096 | |
f1db3576 JL |
5097 | CLEAR_HARD_REG_SET (reg_used_in_insn); |
5098 | { | |
5099 | HARD_REG_SET tmp; | |
239a0f5b | 5100 | REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout); |
f1db3576 | 5101 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b | 5102 | REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set); |
f1db3576 | 5103 | IOR_HARD_REG_SET (reg_used_in_insn, tmp); |
239a0f5b BS |
5104 | compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout); |
5105 | compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set); | |
f1db3576 | 5106 | } |
efc9bd41 | 5107 | |
546b63fb RK |
5108 | for (i = 0; i < reload_n_operands; i++) |
5109 | { | |
5110 | CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); | |
5111 | CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); | |
5112 | CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); | |
47c8cf91 | 5113 | CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]); |
546b63fb | 5114 | CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); |
47c8cf91 | 5115 | CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]); |
546b63fb | 5116 | } |
32131a9c | 5117 | |
9e3a9cf2 | 5118 | COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs); |
05d10675 | 5119 | |
67e61fe7 | 5120 | CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); |
32131a9c | 5121 | |
67e61fe7 BS |
5122 | for (i = 0; i < n_reloads; i++) |
5123 | /* If we have already decided to use a certain register, | |
5124 | don't use it in another way. */ | |
5125 | if (rld[i].reg_rtx) | |
5126 | mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum, | |
5127 | rld[i].when_needed, rld[i].mode); | |
5128 | } | |
32131a9c | 5129 | |
67e61fe7 BS |
5130 | /* Assign hard reg targets for the pseudo-registers we must reload |
5131 | into hard regs for this insn. | |
5132 | Also output the instructions to copy them in and out of the hard regs. | |
5133 | ||
5134 | For machines with register classes, we are responsible for | |
5135 | finding a reload reg in the proper class. */ | |
5136 | ||
5137 | static void | |
5138 | choose_reload_regs (chain) | |
5139 | struct insn_chain *chain; | |
5140 | { | |
5141 | rtx insn = chain->insn; | |
5142 | register int i, j; | |
770ae6cc | 5143 | unsigned int max_group_size = 1; |
67e61fe7 | 5144 | enum reg_class group_class = NO_REGS; |
f5d8c9f4 | 5145 | int pass, win, inheritance; |
67e61fe7 BS |
5146 | |
5147 | rtx save_reload_reg_rtx[MAX_RELOADS]; | |
32131a9c | 5148 | |
32131a9c RK |
5149 | /* In order to be certain of getting the registers we need, |
5150 | we must sort the reloads into order of increasing register class. | |
5151 | Then our grabbing of reload registers will parallel the process | |
a8fdc208 | 5152 | that provided the reload registers. |
32131a9c RK |
5153 | |
5154 | Also note whether any of the reloads wants a consecutive group of regs. | |
5155 | If so, record the maximum size of the group desired and what | |
5156 | register class contains all the groups needed by this insn. */ | |
5157 | ||
5158 | for (j = 0; j < n_reloads; j++) | |
5159 | { | |
5160 | reload_order[j] = j; | |
5161 | reload_spill_index[j] = -1; | |
5162 | ||
8ec450a4 | 5163 | if (rld[j].nregs > 1) |
32131a9c | 5164 | { |
8ec450a4 | 5165 | max_group_size = MAX (rld[j].nregs, max_group_size); |
770ae6cc RK |
5166 | group_class |
5167 | = reg_class_superunion[(int)rld[j].class][(int)group_class]; | |
32131a9c RK |
5168 | } |
5169 | ||
eceef4c9 | 5170 | save_reload_reg_rtx[j] = rld[j].reg_rtx; |
32131a9c RK |
5171 | } |
5172 | ||
5173 | if (n_reloads > 1) | |
5174 | qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); | |
5175 | ||
58b1581b RS |
5176 | /* If -O, try first with inheritance, then turning it off. |
5177 | If not -O, don't do inheritance. | |
5178 | Using inheritance when not optimizing leads to paradoxes | |
5179 | with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves | |
5180 | because one side of the comparison might be inherited. */ | |
f5d8c9f4 | 5181 | win = 0; |
58b1581b | 5182 | for (inheritance = optimize > 0; inheritance >= 0; inheritance--) |
32131a9c | 5183 | { |
67e61fe7 BS |
5184 | choose_reload_regs_init (chain, save_reload_reg_rtx); |
5185 | ||
32131a9c RK |
5186 | /* Process the reloads in order of preference just found. |
5187 | Beyond this point, subregs can be found in reload_reg_rtx. | |
5188 | ||
770ae6cc RK |
5189 | This used to look for an existing reloaded home for all of the |
5190 | reloads, and only then perform any new reloads. But that could lose | |
5191 | if the reloads were done out of reg-class order because a later | |
5192 | reload with a looser constraint might have an old home in a register | |
5193 | needed by an earlier reload with a tighter constraint. | |
32131a9c RK |
5194 | |
5195 | To solve this, we make two passes over the reloads, in the order | |
5196 | described above. In the first pass we try to inherit a reload | |
5197 | from a previous insn. If there is a later reload that needs a | |
5198 | class that is a proper subset of the class being processed, we must | |
5199 | also allocate a spill register during the first pass. | |
5200 | ||
5201 | Then make a second pass over the reloads to allocate any reloads | |
5202 | that haven't been given registers yet. */ | |
5203 | ||
5204 | for (j = 0; j < n_reloads; j++) | |
5205 | { | |
5206 | register int r = reload_order[j]; | |
8593b745 | 5207 | rtx search_equiv = NULL_RTX; |
32131a9c RK |
5208 | |
5209 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 BS |
5210 | if (rld[r].out == 0 && rld[r].in == 0 |
5211 | && ! rld[r].secondary_p) | |
32131a9c RK |
5212 | continue; |
5213 | ||
b29514ee | 5214 | /* If find_reloads chose to use reload_in or reload_out as a reload |
b080c137 RK |
5215 | register, we don't need to chose one. Otherwise, try even if it |
5216 | found one since we might save an insn if we find the value lying | |
b29514ee R |
5217 | around. |
5218 | Try also when reload_in is a pseudo without a hard reg. */ | |
eceef4c9 BS |
5219 | if (rld[r].in != 0 && rld[r].reg_rtx != 0 |
5220 | && (rtx_equal_p (rld[r].in, rld[r].reg_rtx) | |
5221 | || (rtx_equal_p (rld[r].out, rld[r].reg_rtx) | |
5222 | && GET_CODE (rld[r].in) != MEM | |
5223 | && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER))) | |
32131a9c RK |
5224 | continue; |
5225 | ||
5226 | #if 0 /* No longer needed for correct operation. | |
5227 | It might give better code, or might not; worth an experiment? */ | |
5228 | /* If this is an optional reload, we can't inherit from earlier insns | |
5229 | until we are sure that any non-optional reloads have been allocated. | |
5230 | The following code takes advantage of the fact that optional reloads | |
5231 | are at the end of reload_order. */ | |
eceef4c9 | 5232 | if (rld[r].optional != 0) |
32131a9c | 5233 | for (i = 0; i < j; i++) |
eceef4c9 BS |
5234 | if ((rld[reload_order[i]].out != 0 |
5235 | || rld[reload_order[i]].in != 0 | |
5236 | || rld[reload_order[i]].secondary_p) | |
5237 | && ! rld[reload_order[i]].optional | |
5238 | && rld[reload_order[i]].reg_rtx == 0) | |
f5d8c9f4 | 5239 | allocate_reload_reg (chain, reload_order[i], 0); |
32131a9c RK |
5240 | #endif |
5241 | ||
5242 | /* First see if this pseudo is already available as reloaded | |
5243 | for a previous insn. We cannot try to inherit for reloads | |
5244 | that are smaller than the maximum number of registers needed | |
5245 | for groups unless the register we would allocate cannot be used | |
5246 | for the groups. | |
5247 | ||
5248 | We could check here to see if this is a secondary reload for | |
5249 | an object that is already in a register of the desired class. | |
5250 | This would avoid the need for the secondary reload register. | |
5251 | But this is complex because we can't easily determine what | |
b080c137 RK |
5252 | objects might want to be loaded via this reload. So let a |
5253 | register be allocated here. In `emit_reload_insns' we suppress | |
5254 | one of the loads in the case described above. */ | |
32131a9c RK |
5255 | |
5256 | if (inheritance) | |
5257 | { | |
cb2afeb3 | 5258 | int word = 0; |
32131a9c | 5259 | register int regno = -1; |
6a651371 | 5260 | enum machine_mode mode = VOIDmode; |
32131a9c | 5261 | |
eceef4c9 | 5262 | if (rld[r].in == 0) |
32131a9c | 5263 | ; |
eceef4c9 | 5264 | else if (GET_CODE (rld[r].in) == REG) |
db660765 | 5265 | { |
eceef4c9 BS |
5266 | regno = REGNO (rld[r].in); |
5267 | mode = GET_MODE (rld[r].in); | |
db660765 | 5268 | } |
eceef4c9 | 5269 | else if (GET_CODE (rld[r].in_reg) == REG) |
db660765 | 5270 | { |
eceef4c9 BS |
5271 | regno = REGNO (rld[r].in_reg); |
5272 | mode = GET_MODE (rld[r].in_reg); | |
db660765 | 5273 | } |
eceef4c9 BS |
5274 | else if (GET_CODE (rld[r].in_reg) == SUBREG |
5275 | && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG) | |
b60a8416 | 5276 | { |
eceef4c9 BS |
5277 | word = SUBREG_WORD (rld[r].in_reg); |
5278 | regno = REGNO (SUBREG_REG (rld[r].in_reg)); | |
cb2afeb3 R |
5279 | if (regno < FIRST_PSEUDO_REGISTER) |
5280 | regno += word; | |
eceef4c9 | 5281 | mode = GET_MODE (rld[r].in_reg); |
cb2afeb3 R |
5282 | } |
5283 | #ifdef AUTO_INC_DEC | |
eceef4c9 BS |
5284 | else if ((GET_CODE (rld[r].in_reg) == PRE_INC |
5285 | || GET_CODE (rld[r].in_reg) == PRE_DEC | |
5286 | || GET_CODE (rld[r].in_reg) == POST_INC | |
5287 | || GET_CODE (rld[r].in_reg) == POST_DEC) | |
5288 | && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG) | |
cb2afeb3 | 5289 | { |
eceef4c9 BS |
5290 | regno = REGNO (XEXP (rld[r].in_reg, 0)); |
5291 | mode = GET_MODE (XEXP (rld[r].in_reg, 0)); | |
5292 | rld[r].out = rld[r].in; | |
b60a8416 | 5293 | } |
cb2afeb3 | 5294 | #endif |
32131a9c RK |
5295 | #if 0 |
5296 | /* This won't work, since REGNO can be a pseudo reg number. | |
5297 | Also, it takes much more hair to keep track of all the things | |
5298 | that can invalidate an inherited reload of part of a pseudoreg. */ | |
eceef4c9 BS |
5299 | else if (GET_CODE (rld[r].in) == SUBREG |
5300 | && GET_CODE (SUBREG_REG (rld[r].in)) == REG) | |
5301 | regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in); | |
32131a9c RK |
5302 | #endif |
5303 | ||
5304 | if (regno >= 0 && reg_last_reload_reg[regno] != 0) | |
5305 | { | |
eceef4c9 | 5306 | enum reg_class class = rld[r].class, last_class; |
cb2afeb3 | 5307 | rtx last_reg = reg_last_reload_reg[regno]; |
02188693 | 5308 | enum machine_mode need_mode; |
05d10675 | 5309 | |
cb2afeb3 R |
5310 | i = REGNO (last_reg) + word; |
5311 | last_class = REGNO_REG_CLASS (i); | |
02188693 RH |
5312 | |
5313 | need_mode = smallest_mode_for_size ((word+1) * UNITS_PER_WORD, | |
5314 | GET_MODE_CLASS (mode)); | |
5315 | ||
c9d8a813 | 5316 | if ( |
02188693 | 5317 | #ifdef CLASS_CANNOT_CHANGE_MODE |
c9d8a813 | 5318 | (TEST_HARD_REG_BIT |
02188693 RH |
5319 | (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i) |
5320 | ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg), | |
5321 | need_mode) | |
c9d8a813 | 5322 | : (GET_MODE_SIZE (GET_MODE (last_reg)) |
02188693 | 5323 | >= GET_MODE_SIZE (need_mode))) |
c9d8a813 RH |
5324 | #else |
5325 | (GET_MODE_SIZE (GET_MODE (last_reg)) | |
02188693 | 5326 | >= GET_MODE_SIZE (need_mode)) |
c9d8a813 | 5327 | #endif |
cb2afeb3 | 5328 | && reg_reloaded_contents[i] == regno |
e6e52be0 | 5329 | && TEST_HARD_REG_BIT (reg_reloaded_valid, i) |
8ec450a4 | 5330 | && HARD_REGNO_MODE_OK (i, rld[r].mode) |
cb2afeb3 R |
5331 | && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i) |
5332 | /* Even if we can't use this register as a reload | |
5333 | register, we might use it for reload_override_in, | |
5334 | if copying it to the desired class is cheap | |
5335 | enough. */ | |
5336 | || ((REGISTER_MOVE_COST (last_class, class) | |
5337 | < MEMORY_MOVE_COST (mode, class, 1)) | |
5338 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
5339 | && (SECONDARY_INPUT_RELOAD_CLASS (class, mode, | |
5340 | last_reg) | |
5341 | == NO_REGS) | |
5342 | #endif | |
5343 | #ifdef SECONDARY_MEMORY_NEEDED | |
5344 | && ! SECONDARY_MEMORY_NEEDED (last_class, class, | |
5345 | mode) | |
5346 | #endif | |
5347 | )) | |
5348 | ||
8ec450a4 | 5349 | && (rld[r].nregs == max_group_size |
32131a9c | 5350 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], |
e6e52be0 | 5351 | i)) |
eceef4c9 BS |
5352 | && reload_reg_free_for_value_p (i, rld[r].opnum, |
5353 | rld[r].when_needed, | |
5354 | rld[r].in, | |
dfe96118 | 5355 | const0_rtx, r, 1)) |
32131a9c RK |
5356 | { |
5357 | /* If a group is needed, verify that all the subsequent | |
0f41302f | 5358 | registers still have their values intact. */ |
32131a9c | 5359 | int nr |
8ec450a4 | 5360 | = HARD_REGNO_NREGS (i, rld[r].mode); |
32131a9c RK |
5361 | int k; |
5362 | ||
5363 | for (k = 1; k < nr; k++) | |
e6e52be0 R |
5364 | if (reg_reloaded_contents[i + k] != regno |
5365 | || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k)) | |
32131a9c RK |
5366 | break; |
5367 | ||
5368 | if (k == nr) | |
5369 | { | |
c74fa651 RS |
5370 | int i1; |
5371 | ||
cb2afeb3 R |
5372 | last_reg = (GET_MODE (last_reg) == mode |
5373 | ? last_reg : gen_rtx_REG (mode, i)); | |
5374 | ||
c74fa651 RS |
5375 | /* We found a register that contains the |
5376 | value we need. If this register is the | |
5377 | same as an `earlyclobber' operand of the | |
5378 | current insn, just mark it as a place to | |
5379 | reload from since we can't use it as the | |
5380 | reload register itself. */ | |
5381 | ||
5382 | for (i1 = 0; i1 < n_earlyclobbers; i1++) | |
5383 | if (reg_overlap_mentioned_for_reload_p | |
5384 | (reg_last_reload_reg[regno], | |
5385 | reload_earlyclobbers[i1])) | |
5386 | break; | |
5387 | ||
8908158d | 5388 | if (i1 != n_earlyclobbers |
dfe96118 | 5389 | || ! (reload_reg_free_for_value_p |
eceef4c9 BS |
5390 | (i, rld[r].opnum, rld[r].when_needed, |
5391 | rld[r].in, rld[r].out, r, 1)) | |
e6e52be0 | 5392 | /* Don't use it if we'd clobber a pseudo reg. */ |
f1db3576 | 5393 | || (TEST_HARD_REG_BIT (reg_used_in_insn, i) |
eceef4c9 | 5394 | && rld[r].out |
e6e52be0 | 5395 | && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i)) |
0c7f2259 | 5396 | /* Don't clobber the frame pointer. */ |
67e61fe7 | 5397 | || (i == HARD_FRAME_POINTER_REGNUM && rld[r].out) |
8908158d RS |
5398 | /* Don't really use the inherited spill reg |
5399 | if we need it wider than we've got it. */ | |
8ec450a4 | 5400 | || (GET_MODE_SIZE (rld[r].mode) |
b29514ee | 5401 | > GET_MODE_SIZE (mode)) |
eceef4c9 | 5402 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], |
cb2afeb3 R |
5403 | i) |
5404 | ||
b29514ee R |
5405 | /* If find_reloads chose reload_out as reload |
5406 | register, stay with it - that leaves the | |
5407 | inherited register for subsequent reloads. */ | |
eceef4c9 | 5408 | || (rld[r].out && rld[r].reg_rtx |
67e61fe7 | 5409 | && rtx_equal_p (rld[r].out, rld[r].reg_rtx))) |
cb2afeb3 R |
5410 | { |
5411 | reload_override_in[r] = last_reg; | |
5412 | reload_inheritance_insn[r] | |
5413 | = reg_reloaded_insn[i]; | |
5414 | } | |
c74fa651 RS |
5415 | else |
5416 | { | |
54c40e68 | 5417 | int k; |
c74fa651 RS |
5418 | /* We can use this as a reload reg. */ |
5419 | /* Mark the register as in use for this part of | |
5420 | the insn. */ | |
e6e52be0 | 5421 | mark_reload_reg_in_use (i, |
eceef4c9 BS |
5422 | rld[r].opnum, |
5423 | rld[r].when_needed, | |
8ec450a4 | 5424 | rld[r].mode); |
eceef4c9 | 5425 | rld[r].reg_rtx = last_reg; |
c74fa651 RS |
5426 | reload_inherited[r] = 1; |
5427 | reload_inheritance_insn[r] | |
5428 | = reg_reloaded_insn[i]; | |
5429 | reload_spill_index[r] = i; | |
54c40e68 RS |
5430 | for (k = 0; k < nr; k++) |
5431 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, | |
e6e52be0 | 5432 | i + k); |
c74fa651 | 5433 | } |
32131a9c RK |
5434 | } |
5435 | } | |
5436 | } | |
5437 | } | |
5438 | ||
5439 | /* Here's another way to see if the value is already lying around. */ | |
5440 | if (inheritance | |
eceef4c9 | 5441 | && rld[r].in != 0 |
32131a9c | 5442 | && ! reload_inherited[r] |
eceef4c9 BS |
5443 | && rld[r].out == 0 |
5444 | && (CONSTANT_P (rld[r].in) | |
5445 | || GET_CODE (rld[r].in) == PLUS | |
5446 | || GET_CODE (rld[r].in) == REG | |
5447 | || GET_CODE (rld[r].in) == MEM) | |
8ec450a4 | 5448 | && (rld[r].nregs == max_group_size |
eceef4c9 BS |
5449 | || ! reg_classes_intersect_p (rld[r].class, group_class))) |
5450 | search_equiv = rld[r].in; | |
8593b745 R |
5451 | /* If this is an output reload from a simple move insn, look |
5452 | if an equivalence for the input is available. */ | |
eceef4c9 | 5453 | else if (inheritance && rld[r].in == 0 && rld[r].out != 0) |
8593b745 R |
5454 | { |
5455 | rtx set = single_set (insn); | |
5456 | ||
5457 | if (set | |
eceef4c9 | 5458 | && rtx_equal_p (rld[r].out, SET_DEST (set)) |
8593b745 R |
5459 | && CONSTANT_P (SET_SRC (set))) |
5460 | search_equiv = SET_SRC (set); | |
5461 | } | |
5462 | ||
5463 | if (search_equiv) | |
32131a9c RK |
5464 | { |
5465 | register rtx equiv | |
eceef4c9 | 5466 | = find_equiv_reg (search_equiv, insn, rld[r].class, |
8ec450a4 | 5467 | -1, NULL_PTR, 0, rld[r].mode); |
f428f252 | 5468 | int regno = 0; |
32131a9c RK |
5469 | |
5470 | if (equiv != 0) | |
5471 | { | |
5472 | if (GET_CODE (equiv) == REG) | |
5473 | regno = REGNO (equiv); | |
5474 | else if (GET_CODE (equiv) == SUBREG) | |
5475 | { | |
f8a9e02b RK |
5476 | /* This must be a SUBREG of a hard register. |
5477 | Make a new REG since this might be used in an | |
5478 | address and not all machines support SUBREGs | |
5479 | there. */ | |
5480 | regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv); | |
8ec450a4 | 5481 | equiv = gen_rtx_REG (rld[r].mode, regno); |
32131a9c RK |
5482 | } |
5483 | else | |
5484 | abort (); | |
5485 | } | |
5486 | ||
5487 | /* If we found a spill reg, reject it unless it is free | |
5488 | and of the desired class. */ | |
5489 | if (equiv != 0 | |
cb2afeb3 | 5490 | && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno) |
eceef4c9 BS |
5491 | && ! reload_reg_free_for_value_p (regno, rld[r].opnum, |
5492 | rld[r].when_needed, | |
5493 | rld[r].in, | |
5494 | rld[r].out, r, 1)) | |
5495 | || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], | |
32131a9c RK |
5496 | regno))) |
5497 | equiv = 0; | |
5498 | ||
8ec450a4 | 5499 | if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode)) |
32131a9c RK |
5500 | equiv = 0; |
5501 | ||
5502 | /* We found a register that contains the value we need. | |
5503 | If this register is the same as an `earlyclobber' operand | |
5504 | of the current insn, just mark it as a place to reload from | |
5505 | since we can't use it as the reload register itself. */ | |
5506 | ||
5507 | if (equiv != 0) | |
5508 | for (i = 0; i < n_earlyclobbers; i++) | |
bfa30b22 RK |
5509 | if (reg_overlap_mentioned_for_reload_p (equiv, |
5510 | reload_earlyclobbers[i])) | |
32131a9c RK |
5511 | { |
5512 | reload_override_in[r] = equiv; | |
5513 | equiv = 0; | |
5514 | break; | |
5515 | } | |
5516 | ||
3c785e47 R |
5517 | /* If the equiv register we have found is explicitly clobbered |
5518 | in the current insn, it depends on the reload type if we | |
5519 | can use it, use it for reload_override_in, or not at all. | |
5520 | In particular, we then can't use EQUIV for a | |
5521 | RELOAD_FOR_OUTPUT_ADDRESS reload. */ | |
32131a9c RK |
5522 | |
5523 | if (equiv != 0 && regno_clobbered_p (regno, insn)) | |
5524 | { | |
eceef4c9 | 5525 | switch (rld[r].when_needed) |
3c785e47 R |
5526 | { |
5527 | case RELOAD_FOR_OTHER_ADDRESS: | |
5528 | case RELOAD_FOR_INPADDR_ADDRESS: | |
5529 | case RELOAD_FOR_INPUT_ADDRESS: | |
5530 | case RELOAD_FOR_OPADDR_ADDR: | |
5531 | break; | |
5532 | case RELOAD_OTHER: | |
5533 | case RELOAD_FOR_INPUT: | |
5534 | case RELOAD_FOR_OPERAND_ADDRESS: | |
5535 | reload_override_in[r] = equiv; | |
5536 | /* Fall through. */ | |
5537 | default: | |
5538 | equiv = 0; | |
5539 | break; | |
5540 | } | |
32131a9c RK |
5541 | } |
5542 | ||
5543 | /* If we found an equivalent reg, say no code need be generated | |
5544 | to load it, and use it as our reload reg. */ | |
3ec2ea3e | 5545 | if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM) |
32131a9c | 5546 | { |
8ec450a4 | 5547 | int nr = HARD_REGNO_NREGS (regno, rld[r].mode); |
100338df | 5548 | int k; |
eceef4c9 | 5549 | rld[r].reg_rtx = equiv; |
32131a9c | 5550 | reload_inherited[r] = 1; |
100338df | 5551 | |
91d7e7ac R |
5552 | /* If reg_reloaded_valid is not set for this register, |
5553 | there might be a stale spill_reg_store lying around. | |
5554 | We must clear it, since otherwise emit_reload_insns | |
5555 | might delete the store. */ | |
5556 | if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno)) | |
5557 | spill_reg_store[regno] = NULL_RTX; | |
100338df JL |
5558 | /* If any of the hard registers in EQUIV are spill |
5559 | registers, mark them as in use for this insn. */ | |
5560 | for (k = 0; k < nr; k++) | |
be7ae2a4 | 5561 | { |
100338df JL |
5562 | i = spill_reg_order[regno + k]; |
5563 | if (i >= 0) | |
5564 | { | |
eceef4c9 BS |
5565 | mark_reload_reg_in_use (regno, rld[r].opnum, |
5566 | rld[r].when_needed, | |
8ec450a4 | 5567 | rld[r].mode); |
100338df JL |
5568 | SET_HARD_REG_BIT (reload_reg_used_for_inherit, |
5569 | regno + k); | |
5570 | } | |
be7ae2a4 | 5571 | } |
32131a9c RK |
5572 | } |
5573 | } | |
5574 | ||
5575 | /* If we found a register to use already, or if this is an optional | |
5576 | reload, we are done. */ | |
eceef4c9 | 5577 | if (rld[r].reg_rtx != 0 || rld[r].optional != 0) |
32131a9c RK |
5578 | continue; |
5579 | ||
5580 | #if 0 /* No longer needed for correct operation. Might or might not | |
5581 | give better code on the average. Want to experiment? */ | |
5582 | ||
5583 | /* See if there is a later reload that has a class different from our | |
5584 | class that intersects our class or that requires less register | |
5585 | than our reload. If so, we must allocate a register to this | |
5586 | reload now, since that reload might inherit a previous reload | |
5587 | and take the only available register in our class. Don't do this | |
5588 | for optional reloads since they will force all previous reloads | |
5589 | to be allocated. Also don't do this for reloads that have been | |
5590 | turned off. */ | |
5591 | ||
5592 | for (i = j + 1; i < n_reloads; i++) | |
5593 | { | |
5594 | int s = reload_order[i]; | |
5595 | ||
eceef4c9 BS |
5596 | if ((rld[s].in == 0 && rld[s].out == 0 |
5597 | && ! rld[s].secondary_p) | |
5598 | || rld[s].optional) | |
32131a9c RK |
5599 | continue; |
5600 | ||
eceef4c9 BS |
5601 | if ((rld[s].class != rld[r].class |
5602 | && reg_classes_intersect_p (rld[r].class, | |
5603 | rld[s].class)) | |
8ec450a4 | 5604 | || rld[s].nregs < rld[r].nregs) |
05d10675 | 5605 | break; |
32131a9c RK |
5606 | } |
5607 | ||
5608 | if (i == n_reloads) | |
5609 | continue; | |
5610 | ||
f5d8c9f4 | 5611 | allocate_reload_reg (chain, r, j == n_reloads - 1); |
32131a9c RK |
5612 | #endif |
5613 | } | |
5614 | ||
5615 | /* Now allocate reload registers for anything non-optional that | |
5616 | didn't get one yet. */ | |
5617 | for (j = 0; j < n_reloads; j++) | |
5618 | { | |
5619 | register int r = reload_order[j]; | |
5620 | ||
5621 | /* Ignore reloads that got marked inoperative. */ | |
eceef4c9 | 5622 | if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p) |
32131a9c RK |
5623 | continue; |
5624 | ||
5625 | /* Skip reloads that already have a register allocated or are | |
0f41302f | 5626 | optional. */ |
eceef4c9 | 5627 | if (rld[r].reg_rtx != 0 || rld[r].optional) |
32131a9c RK |
5628 | continue; |
5629 | ||
f5d8c9f4 | 5630 | if (! allocate_reload_reg (chain, r, j == n_reloads - 1)) |
32131a9c RK |
5631 | break; |
5632 | } | |
5633 | ||
5634 | /* If that loop got all the way, we have won. */ | |
5635 | if (j == n_reloads) | |
f5d8c9f4 BS |
5636 | { |
5637 | win = 1; | |
5638 | break; | |
5639 | } | |
32131a9c | 5640 | |
32131a9c | 5641 | /* Loop around and try without any inheritance. */ |
32131a9c RK |
5642 | } |
5643 | ||
f5d8c9f4 BS |
5644 | if (! win) |
5645 | { | |
5646 | /* First undo everything done by the failed attempt | |
5647 | to allocate with inheritance. */ | |
5648 | choose_reload_regs_init (chain, save_reload_reg_rtx); | |
5649 | ||
5650 | /* Some sanity tests to verify that the reloads found in the first | |
5651 | pass are identical to the ones we have now. */ | |
5652 | if (chain->n_reloads != n_reloads) | |
5653 | abort (); | |
5654 | ||
5655 | for (i = 0; i < n_reloads; i++) | |
5656 | { | |
5657 | if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0) | |
5658 | continue; | |
5659 | if (chain->rld[i].when_needed != rld[i].when_needed) | |
5660 | abort (); | |
5661 | for (j = 0; j < n_spills; j++) | |
5662 | if (spill_regs[j] == chain->rld[i].regno) | |
5663 | if (! set_reload_reg (j, i)) | |
5664 | failed_reload (chain->insn, i); | |
5665 | } | |
5666 | } | |
5667 | ||
32131a9c RK |
5668 | /* If we thought we could inherit a reload, because it seemed that |
5669 | nothing else wanted the same reload register earlier in the insn, | |
cb2afeb3 R |
5670 | verify that assumption, now that all reloads have been assigned. |
5671 | Likewise for reloads where reload_override_in has been set. */ | |
32131a9c | 5672 | |
cb2afeb3 R |
5673 | /* If doing expensive optimizations, do one preliminary pass that doesn't |
5674 | cancel any inheritance, but removes reloads that have been needed only | |
5675 | for reloads that we know can be inherited. */ | |
5676 | for (pass = flag_expensive_optimizations; pass >= 0; pass--) | |
32131a9c | 5677 | { |
cb2afeb3 | 5678 | for (j = 0; j < n_reloads; j++) |
029b38ff | 5679 | { |
cb2afeb3 R |
5680 | register int r = reload_order[j]; |
5681 | rtx check_reg; | |
eceef4c9 BS |
5682 | if (reload_inherited[r] && rld[r].reg_rtx) |
5683 | check_reg = rld[r].reg_rtx; | |
cb2afeb3 R |
5684 | else if (reload_override_in[r] |
5685 | && (GET_CODE (reload_override_in[r]) == REG | |
05d10675 | 5686 | || GET_CODE (reload_override_in[r]) == SUBREG)) |
cb2afeb3 R |
5687 | check_reg = reload_override_in[r]; |
5688 | else | |
5689 | continue; | |
dfe96118 | 5690 | if (! reload_reg_free_for_value_p (true_regnum (check_reg), |
eceef4c9 BS |
5691 | rld[r].opnum, |
5692 | rld[r].when_needed, | |
5693 | rld[r].in, | |
05d10675 | 5694 | (reload_inherited[r] |
eceef4c9 | 5695 | ? rld[r].out : const0_rtx), |
dfe96118 | 5696 | r, 1)) |
029b38ff | 5697 | { |
cb2afeb3 R |
5698 | if (pass) |
5699 | continue; | |
5700 | reload_inherited[r] = 0; | |
5701 | reload_override_in[r] = 0; | |
029b38ff | 5702 | } |
cb2afeb3 R |
5703 | /* If we can inherit a RELOAD_FOR_INPUT, or can use a |
5704 | reload_override_in, then we do not need its related | |
5705 | RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads; | |
5706 | likewise for other reload types. | |
5707 | We handle this by removing a reload when its only replacement | |
5708 | is mentioned in reload_in of the reload we are going to inherit. | |
5709 | A special case are auto_inc expressions; even if the input is | |
5710 | inherited, we still need the address for the output. We can | |
fe92fe26 | 5711 | recognize them because they have RELOAD_OUT set to RELOAD_IN. |
cb2afeb3 R |
5712 | If we suceeded removing some reload and we are doing a preliminary |
5713 | pass just to remove such reloads, make another pass, since the | |
5714 | removal of one reload might allow us to inherit another one. */ | |
eceef4c9 BS |
5715 | else if (rld[r].in |
5716 | && rld[r].out != rld[r].in | |
5717 | && remove_address_replacements (rld[r].in) && pass) | |
cb2afeb3 | 5718 | pass = 2; |
32131a9c RK |
5719 | } |
5720 | } | |
5721 | ||
5722 | /* Now that reload_override_in is known valid, | |
5723 | actually override reload_in. */ | |
5724 | for (j = 0; j < n_reloads; j++) | |
5725 | if (reload_override_in[j]) | |
eceef4c9 | 5726 | rld[j].in = reload_override_in[j]; |
32131a9c RK |
5727 | |
5728 | /* If this reload won't be done because it has been cancelled or is | |
5729 | optional and not inherited, clear reload_reg_rtx so other | |
5730 | routines (such as subst_reloads) don't get confused. */ | |
5731 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
5732 | if (rld[j].reg_rtx != 0 |
5733 | && ((rld[j].optional && ! reload_inherited[j]) | |
5734 | || (rld[j].in == 0 && rld[j].out == 0 | |
5735 | && ! rld[j].secondary_p))) | |
be7ae2a4 | 5736 | { |
eceef4c9 | 5737 | int regno = true_regnum (rld[j].reg_rtx); |
be7ae2a4 RK |
5738 | |
5739 | if (spill_reg_order[regno] >= 0) | |
eceef4c9 | 5740 | clear_reload_reg_in_use (regno, rld[j].opnum, |
8ec450a4 | 5741 | rld[j].when_needed, rld[j].mode); |
eceef4c9 | 5742 | rld[j].reg_rtx = 0; |
c0029be5 | 5743 | reload_spill_index[j] = -1; |
be7ae2a4 | 5744 | } |
32131a9c RK |
5745 | |
5746 | /* Record which pseudos and which spill regs have output reloads. */ | |
5747 | for (j = 0; j < n_reloads; j++) | |
5748 | { | |
5749 | register int r = reload_order[j]; | |
5750 | ||
5751 | i = reload_spill_index[r]; | |
5752 | ||
e6e52be0 | 5753 | /* I is nonneg if this reload uses a register. |
eceef4c9 | 5754 | If rld[r].reg_rtx is 0, this is an optional reload |
32131a9c | 5755 | that we opted to ignore. */ |
eceef4c9 BS |
5756 | if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG |
5757 | && rld[r].reg_rtx != 0) | |
32131a9c | 5758 | { |
eceef4c9 | 5759 | register int nregno = REGNO (rld[r].out_reg); |
372e033b RS |
5760 | int nr = 1; |
5761 | ||
5762 | if (nregno < FIRST_PSEUDO_REGISTER) | |
8ec450a4 | 5763 | nr = HARD_REGNO_NREGS (nregno, rld[r].mode); |
32131a9c RK |
5764 | |
5765 | while (--nr >= 0) | |
372e033b RS |
5766 | reg_has_output_reload[nregno + nr] = 1; |
5767 | ||
5768 | if (i >= 0) | |
32131a9c | 5769 | { |
8ec450a4 | 5770 | nr = HARD_REGNO_NREGS (i, rld[r].mode); |
372e033b | 5771 | while (--nr >= 0) |
e6e52be0 | 5772 | SET_HARD_REG_BIT (reg_is_output_reload, i + nr); |
32131a9c RK |
5773 | } |
5774 | ||
eceef4c9 BS |
5775 | if (rld[r].when_needed != RELOAD_OTHER |
5776 | && rld[r].when_needed != RELOAD_FOR_OUTPUT | |
5777 | && rld[r].when_needed != RELOAD_FOR_INSN) | |
32131a9c RK |
5778 | abort (); |
5779 | } | |
5780 | } | |
5781 | } | |
cb2afeb3 R |
5782 | |
5783 | /* Deallocate the reload register for reload R. This is called from | |
5784 | remove_address_replacements. */ | |
1d813780 | 5785 | |
cb2afeb3 R |
5786 | void |
5787 | deallocate_reload_reg (r) | |
5788 | int r; | |
5789 | { | |
5790 | int regno; | |
5791 | ||
eceef4c9 | 5792 | if (! rld[r].reg_rtx) |
cb2afeb3 | 5793 | return; |
eceef4c9 BS |
5794 | regno = true_regnum (rld[r].reg_rtx); |
5795 | rld[r].reg_rtx = 0; | |
cb2afeb3 | 5796 | if (spill_reg_order[regno] >= 0) |
eceef4c9 | 5797 | clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed, |
8ec450a4 | 5798 | rld[r].mode); |
cb2afeb3 R |
5799 | reload_spill_index[r] = -1; |
5800 | } | |
32131a9c | 5801 | \f |
e9a25f70 | 5802 | /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two |
546b63fb RK |
5803 | reloads of the same item for fear that we might not have enough reload |
5804 | registers. However, normally they will get the same reload register | |
05d10675 | 5805 | and hence actually need not be loaded twice. |
546b63fb RK |
5806 | |
5807 | Here we check for the most common case of this phenomenon: when we have | |
5808 | a number of reloads for the same object, each of which were allocated | |
5809 | the same reload_reg_rtx, that reload_reg_rtx is not used for any other | |
5810 | reload, and is not modified in the insn itself. If we find such, | |
5811 | merge all the reloads and set the resulting reload to RELOAD_OTHER. | |
5812 | This will not increase the number of spill registers needed and will | |
5813 | prevent redundant code. */ | |
5814 | ||
546b63fb RK |
5815 | static void |
5816 | merge_assigned_reloads (insn) | |
5817 | rtx insn; | |
5818 | { | |
5819 | int i, j; | |
5820 | ||
5821 | /* Scan all the reloads looking for ones that only load values and | |
5822 | are not already RELOAD_OTHER and ones whose reload_reg_rtx are | |
5823 | assigned and not modified by INSN. */ | |
5824 | ||
5825 | for (i = 0; i < n_reloads; i++) | |
5826 | { | |
d668e863 R |
5827 | int conflicting_input = 0; |
5828 | int max_input_address_opnum = -1; | |
5829 | int min_conflicting_input_opnum = MAX_RECOG_OPERANDS; | |
5830 | ||
eceef4c9 BS |
5831 | if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER |
5832 | || rld[i].out != 0 || rld[i].reg_rtx == 0 | |
5833 | || reg_set_p (rld[i].reg_rtx, insn)) | |
546b63fb RK |
5834 | continue; |
5835 | ||
5836 | /* Look at all other reloads. Ensure that the only use of this | |
5837 | reload_reg_rtx is in a reload that just loads the same value | |
5838 | as we do. Note that any secondary reloads must be of the identical | |
5839 | class since the values, modes, and result registers are the | |
5840 | same, so we need not do anything with any secondary reloads. */ | |
5841 | ||
5842 | for (j = 0; j < n_reloads; j++) | |
5843 | { | |
eceef4c9 BS |
5844 | if (i == j || rld[j].reg_rtx == 0 |
5845 | || ! reg_overlap_mentioned_p (rld[j].reg_rtx, | |
5846 | rld[i].reg_rtx)) | |
546b63fb RK |
5847 | continue; |
5848 | ||
eceef4c9 BS |
5849 | if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
5850 | && rld[j].opnum > max_input_address_opnum) | |
5851 | max_input_address_opnum = rld[j].opnum; | |
d668e863 | 5852 | |
546b63fb | 5853 | /* If the reload regs aren't exactly the same (e.g, different modes) |
d668e863 R |
5854 | or if the values are different, we can't merge this reload. |
5855 | But if it is an input reload, we might still merge | |
5856 | RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */ | |
546b63fb | 5857 | |
eceef4c9 BS |
5858 | if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) |
5859 | || rld[j].out != 0 || rld[j].in == 0 | |
5860 | || ! rtx_equal_p (rld[i].in, rld[j].in)) | |
d668e863 | 5861 | { |
eceef4c9 BS |
5862 | if (rld[j].when_needed != RELOAD_FOR_INPUT |
5863 | || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS | |
5864 | || rld[i].opnum > rld[j].opnum) | |
5865 | && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS)) | |
d668e863 R |
5866 | break; |
5867 | conflicting_input = 1; | |
eceef4c9 BS |
5868 | if (min_conflicting_input_opnum > rld[j].opnum) |
5869 | min_conflicting_input_opnum = rld[j].opnum; | |
d668e863 | 5870 | } |
546b63fb RK |
5871 | } |
5872 | ||
5873 | /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if | |
5874 | we, in fact, found any matching reloads. */ | |
5875 | ||
d668e863 R |
5876 | if (j == n_reloads |
5877 | && max_input_address_opnum <= min_conflicting_input_opnum) | |
546b63fb RK |
5878 | { |
5879 | for (j = 0; j < n_reloads; j++) | |
eceef4c9 BS |
5880 | if (i != j && rld[j].reg_rtx != 0 |
5881 | && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) | |
d668e863 | 5882 | && (! conflicting_input |
eceef4c9 BS |
5883 | || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS |
5884 | || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS)) | |
546b63fb | 5885 | { |
eceef4c9 BS |
5886 | rld[i].when_needed = RELOAD_OTHER; |
5887 | rld[j].in = 0; | |
efdb3590 | 5888 | reload_spill_index[j] = -1; |
546b63fb RK |
5889 | transfer_replacements (i, j); |
5890 | } | |
5891 | ||
5892 | /* If this is now RELOAD_OTHER, look for any reloads that load | |
5893 | parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS | |
5894 | if they were for inputs, RELOAD_OTHER for outputs. Note that | |
5895 | this test is equivalent to looking for reloads for this operand | |
5896 | number. */ | |
5897 | ||
eceef4c9 | 5898 | if (rld[i].when_needed == RELOAD_OTHER) |
546b63fb | 5899 | for (j = 0; j < n_reloads; j++) |
eceef4c9 BS |
5900 | if (rld[j].in != 0 |
5901 | && rld[i].when_needed != RELOAD_OTHER | |
5902 | && reg_overlap_mentioned_for_reload_p (rld[j].in, | |
5903 | rld[i].in)) | |
5904 | rld[j].when_needed | |
5905 | = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS | |
5906 | || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS) | |
47c8cf91 | 5907 | ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER); |
546b63fb RK |
5908 | } |
5909 | } | |
05d10675 | 5910 | } |
e9a25f70 | 5911 | |
546b63fb | 5912 | \f |
367b1cf5 BS |
5913 | /* These arrays are filled by emit_reload_insns and its subroutines. */ |
5914 | static rtx input_reload_insns[MAX_RECOG_OPERANDS]; | |
5915 | static rtx other_input_address_reload_insns = 0; | |
5916 | static rtx other_input_reload_insns = 0; | |
5917 | static rtx input_address_reload_insns[MAX_RECOG_OPERANDS]; | |
5918 | static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
5919 | static rtx output_reload_insns[MAX_RECOG_OPERANDS]; | |
5920 | static rtx output_address_reload_insns[MAX_RECOG_OPERANDS]; | |
5921 | static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS]; | |
5922 | static rtx operand_reload_insns = 0; | |
5923 | static rtx other_operand_reload_insns = 0; | |
5924 | static rtx other_output_reload_insns[MAX_RECOG_OPERANDS]; | |
5925 | ||
5926 | /* Values to be put in spill_reg_store are put here first. */ | |
5927 | static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; | |
5928 | static HARD_REG_SET reg_reloaded_died; | |
5929 | ||
5930 | /* Generate insns to perform reload RL, which is for the insn in CHAIN and | |
5931 | has the number J. OLD contains the value to be used as input. */ | |
770ae6cc | 5932 | |
32131a9c | 5933 | static void |
367b1cf5 | 5934 | emit_input_reload_insns (chain, rl, old, j) |
7609e720 | 5935 | struct insn_chain *chain; |
367b1cf5 BS |
5936 | struct reload *rl; |
5937 | rtx old; | |
5938 | int j; | |
32131a9c | 5939 | { |
7609e720 | 5940 | rtx insn = chain->insn; |
367b1cf5 BS |
5941 | register rtx reloadreg = rl->reg_rtx; |
5942 | rtx oldequiv_reg = 0; | |
5943 | rtx oldequiv = 0; | |
5944 | int special = 0; | |
5945 | enum machine_mode mode; | |
5946 | rtx *where; | |
5947 | ||
5948 | /* Determine the mode to reload in. | |
5949 | This is very tricky because we have three to choose from. | |
5950 | There is the mode the insn operand wants (rl->inmode). | |
5951 | There is the mode of the reload register RELOADREG. | |
5952 | There is the intrinsic mode of the operand, which we could find | |
5953 | by stripping some SUBREGs. | |
5954 | It turns out that RELOADREG's mode is irrelevant: | |
5955 | we can change that arbitrarily. | |
5956 | ||
5957 | Consider (SUBREG:SI foo:QI) as an operand that must be SImode; | |
5958 | then the reload reg may not support QImode moves, so use SImode. | |
5959 | If foo is in memory due to spilling a pseudo reg, this is safe, | |
5960 | because the QImode value is in the least significant part of a | |
5961 | slot big enough for a SImode. If foo is some other sort of | |
5962 | memory reference, then it is impossible to reload this case, | |
5963 | so previous passes had better make sure this never happens. | |
5964 | ||
5965 | Then consider a one-word union which has SImode and one of its | |
5966 | members is a float, being fetched as (SUBREG:SF union:SI). | |
5967 | We must fetch that as SFmode because we could be loading into | |
5968 | a float-only register. In this case OLD's mode is correct. | |
5969 | ||
5970 | Consider an immediate integer: it has VOIDmode. Here we need | |
5971 | to get a mode from something else. | |
5972 | ||
5973 | In some cases, there is a fourth mode, the operand's | |
5974 | containing mode. If the insn specifies a containing mode for | |
5975 | this operand, it overrides all others. | |
5976 | ||
5977 | I am not sure whether the algorithm here is always right, | |
5978 | but it does the right things in those cases. */ | |
5979 | ||
5980 | mode = GET_MODE (old); | |
5981 | if (mode == VOIDmode) | |
5982 | mode = rl->inmode; | |
7609e720 | 5983 | |
367b1cf5 BS |
5984 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
5985 | /* If we need a secondary register for this operation, see if | |
5986 | the value is already in a register in that class. Don't | |
5987 | do this if the secondary register will be used as a scratch | |
5988 | register. */ | |
5989 | ||
5990 | if (rl->secondary_in_reload >= 0 | |
5991 | && rl->secondary_in_icode == CODE_FOR_nothing | |
5992 | && optimize) | |
5993 | oldequiv | |
5994 | = find_equiv_reg (old, insn, | |
5995 | rld[rl->secondary_in_reload].class, | |
5996 | -1, NULL_PTR, 0, mode); | |
5997 | #endif | |
e6e52be0 | 5998 | |
367b1cf5 BS |
5999 | /* If reloading from memory, see if there is a register |
6000 | that already holds the same value. If so, reload from there. | |
6001 | We can pass 0 as the reload_reg_p argument because | |
6002 | any other reload has either already been emitted, | |
6003 | in which case find_equiv_reg will see the reload-insn, | |
6004 | or has yet to be emitted, in which case it doesn't matter | |
6005 | because we will use this equiv reg right away. */ | |
6006 | ||
6007 | if (oldequiv == 0 && optimize | |
6008 | && (GET_CODE (old) == MEM | |
6009 | || (GET_CODE (old) == REG | |
6010 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
6011 | && reg_renumber[REGNO (old)] < 0))) | |
6012 | oldequiv = find_equiv_reg (old, insn, ALL_REGS, | |
6013 | -1, NULL_PTR, 0, mode); | |
6014 | ||
6015 | if (oldequiv) | |
6016 | { | |
770ae6cc | 6017 | unsigned int regno = true_regnum (oldequiv); |
367b1cf5 BS |
6018 | |
6019 | /* Don't use OLDEQUIV if any other reload changes it at an | |
6020 | earlier stage of this insn or at this stage. */ | |
6021 | if (! reload_reg_free_for_value_p (regno, rl->opnum, | |
6022 | rl->when_needed, | |
6023 | rl->in, const0_rtx, j, | |
6024 | 0)) | |
6025 | oldequiv = 0; | |
6026 | ||
6027 | /* If it is no cheaper to copy from OLDEQUIV into the | |
6028 | reload register than it would be to move from memory, | |
6029 | don't use it. Likewise, if we need a secondary register | |
6030 | or memory. */ | |
6031 | ||
6032 | if (oldequiv != 0 | |
6033 | && ((REGNO_REG_CLASS (regno) != rl->class | |
6034 | && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno), | |
6035 | rl->class) | |
6036 | >= MEMORY_MOVE_COST (mode, rl->class, 1))) | |
6037 | #ifdef SECONDARY_INPUT_RELOAD_CLASS | |
6038 | || (SECONDARY_INPUT_RELOAD_CLASS (rl->class, | |
6039 | mode, oldequiv) | |
6040 | != NO_REGS) | |
6041 | #endif | |
6042 | #ifdef SECONDARY_MEMORY_NEEDED | |
6043 | || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno), | |
6044 | rl->class, | |
6045 | mode) | |
6046 | #endif | |
6047 | )) | |
6048 | oldequiv = 0; | |
6049 | } | |
32131a9c | 6050 | |
367b1cf5 BS |
6051 | /* delete_output_reload is only invoked properly if old contains |
6052 | the original pseudo register. Since this is replaced with a | |
6053 | hard reg when RELOAD_OVERRIDE_IN is set, see if we can | |
6054 | find the pseudo in RELOAD_IN_REG. */ | |
6055 | if (oldequiv == 0 | |
6056 | && reload_override_in[j] | |
6057 | && GET_CODE (rl->in_reg) == REG) | |
6058 | { | |
6059 | oldequiv = old; | |
6060 | old = rl->in_reg; | |
6061 | } | |
6062 | if (oldequiv == 0) | |
6063 | oldequiv = old; | |
6064 | else if (GET_CODE (oldequiv) == REG) | |
6065 | oldequiv_reg = oldequiv; | |
6066 | else if (GET_CODE (oldequiv) == SUBREG) | |
6067 | oldequiv_reg = SUBREG_REG (oldequiv); | |
6068 | ||
6069 | /* If we are reloading from a register that was recently stored in | |
6070 | with an output-reload, see if we can prove there was | |
6071 | actually no need to store the old value in it. */ | |
6072 | ||
6073 | if (optimize && GET_CODE (oldequiv) == REG | |
6074 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER | |
6075 | && spill_reg_store[REGNO (oldequiv)] | |
6076 | && GET_CODE (old) == REG | |
6077 | && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) | |
6078 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6079 | rl->out_reg))) | |
6080 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6081 | ||
6082 | /* Encapsulate both RELOADREG and OLDEQUIV into that mode, | |
6083 | then load RELOADREG from OLDEQUIV. Note that we cannot use | |
6084 | gen_lowpart_common since it can do the wrong thing when | |
6085 | RELOADREG has a multi-word mode. Note that RELOADREG | |
6086 | must always be a REG here. */ | |
6087 | ||
6088 | if (GET_MODE (reloadreg) != mode) | |
6089 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
6090 | while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) | |
6091 | oldequiv = SUBREG_REG (oldequiv); | |
6092 | if (GET_MODE (oldequiv) != VOIDmode | |
6093 | && mode != GET_MODE (oldequiv)) | |
6094 | oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0); | |
6095 | ||
6096 | /* Switch to the right place to emit the reload insns. */ | |
6097 | switch (rl->when_needed) | |
6098 | { | |
6099 | case RELOAD_OTHER: | |
6100 | where = &other_input_reload_insns; | |
6101 | break; | |
6102 | case RELOAD_FOR_INPUT: | |
6103 | where = &input_reload_insns[rl->opnum]; | |
6104 | break; | |
6105 | case RELOAD_FOR_INPUT_ADDRESS: | |
6106 | where = &input_address_reload_insns[rl->opnum]; | |
6107 | break; | |
6108 | case RELOAD_FOR_INPADDR_ADDRESS: | |
6109 | where = &inpaddr_address_reload_insns[rl->opnum]; | |
6110 | break; | |
6111 | case RELOAD_FOR_OUTPUT_ADDRESS: | |
6112 | where = &output_address_reload_insns[rl->opnum]; | |
6113 | break; | |
6114 | case RELOAD_FOR_OUTADDR_ADDRESS: | |
6115 | where = &outaddr_address_reload_insns[rl->opnum]; | |
6116 | break; | |
6117 | case RELOAD_FOR_OPERAND_ADDRESS: | |
6118 | where = &operand_reload_insns; | |
6119 | break; | |
6120 | case RELOAD_FOR_OPADDR_ADDR: | |
6121 | where = &other_operand_reload_insns; | |
6122 | break; | |
6123 | case RELOAD_FOR_OTHER_ADDRESS: | |
6124 | where = &other_input_address_reload_insns; | |
6125 | break; | |
6126 | default: | |
6127 | abort (); | |
6128 | } | |
546b63fb | 6129 | |
367b1cf5 | 6130 | push_to_sequence (*where); |
32131a9c | 6131 | |
367b1cf5 BS |
6132 | /* Auto-increment addresses must be reloaded in a special way. */ |
6133 | if (rl->out && ! rl->out_reg) | |
32131a9c | 6134 | { |
367b1cf5 BS |
6135 | /* We are not going to bother supporting the case where a |
6136 | incremented register can't be copied directly from | |
6137 | OLDEQUIV since this seems highly unlikely. */ | |
6138 | if (rl->secondary_in_reload >= 0) | |
6139 | abort (); | |
32131a9c | 6140 | |
367b1cf5 BS |
6141 | if (reload_inherited[j]) |
6142 | oldequiv = reloadreg; | |
cb2afeb3 | 6143 | |
367b1cf5 | 6144 | old = XEXP (rl->in_reg, 0); |
32131a9c | 6145 | |
367b1cf5 BS |
6146 | if (optimize && GET_CODE (oldequiv) == REG |
6147 | && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER | |
6148 | && spill_reg_store[REGNO (oldequiv)] | |
6149 | && GET_CODE (old) == REG | |
6150 | && (dead_or_set_p (insn, | |
6151 | spill_reg_stored_to[REGNO (oldequiv)]) | |
6152 | || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], | |
6153 | old))) | |
6154 | delete_output_reload (insn, j, REGNO (oldequiv)); | |
6155 | ||
6156 | /* Prevent normal processing of this reload. */ | |
6157 | special = 1; | |
6158 | /* Output a special code sequence for this case. */ | |
6159 | new_spill_reg_store[REGNO (reloadreg)] | |
6160 | = inc_for_reload (reloadreg, oldequiv, rl->out, | |
6161 | rl->inc); | |
6162 | } | |
32131a9c | 6163 | |
367b1cf5 BS |
6164 | /* If we are reloading a pseudo-register that was set by the previous |
6165 | insn, see if we can get rid of that pseudo-register entirely | |
6166 | by redirecting the previous insn into our reload register. */ | |
6167 | ||
6168 | else if (optimize && GET_CODE (old) == REG | |
6169 | && REGNO (old) >= FIRST_PSEUDO_REGISTER | |
6170 | && dead_or_set_p (insn, old) | |
6171 | /* This is unsafe if some other reload | |
6172 | uses the same reg first. */ | |
6173 | && reload_reg_free_for_value_p (REGNO (reloadreg), | |
6174 | rl->opnum, | |
6175 | rl->when_needed, | |
6176 | old, rl->out, | |
6177 | j, 0)) | |
6178 | { | |
6179 | rtx temp = PREV_INSN (insn); | |
6180 | while (temp && GET_CODE (temp) == NOTE) | |
6181 | temp = PREV_INSN (temp); | |
6182 | if (temp | |
6183 | && GET_CODE (temp) == INSN | |
6184 | && GET_CODE (PATTERN (temp)) == SET | |
6185 | && SET_DEST (PATTERN (temp)) == old | |
6186 | /* Make sure we can access insn_operand_constraint. */ | |
6187 | && asm_noperands (PATTERN (temp)) < 0 | |
6188 | /* This is unsafe if prev insn rejects our reload reg. */ | |
6189 | && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint, | |
6190 | reloadreg) | |
6191 | /* This is unsafe if operand occurs more than once in current | |
6192 | insn. Perhaps some occurrences aren't reloaded. */ | |
6193 | && count_occurrences (PATTERN (insn), old) == 1 | |
6194 | /* Don't risk splitting a matching pair of operands. */ | |
6195 | && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp)))) | |
6196 | { | |
6197 | /* Store into the reload register instead of the pseudo. */ | |
6198 | SET_DEST (PATTERN (temp)) = reloadreg; | |
6199 | ||
6200 | /* If the previous insn is an output reload, the source is | |
6201 | a reload register, and its spill_reg_store entry will | |
6202 | contain the previous destination. This is now | |
6203 | invalid. */ | |
6204 | if (GET_CODE (SET_SRC (PATTERN (temp))) == REG | |
6205 | && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER) | |
32131a9c | 6206 | { |
367b1cf5 BS |
6207 | spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0; |
6208 | spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; | |
32131a9c RK |
6209 | } |
6210 | ||
367b1cf5 BS |
6211 | /* If these are the only uses of the pseudo reg, |
6212 | pretend for GDB it lives in the reload reg we used. */ | |
6213 | if (REG_N_DEATHS (REGNO (old)) == 1 | |
6214 | && REG_N_SETS (REGNO (old)) == 1) | |
cb2afeb3 | 6215 | { |
367b1cf5 BS |
6216 | reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx); |
6217 | alter_reg (REGNO (old), -1); | |
32131a9c | 6218 | } |
07875628 | 6219 | special = 1; |
367b1cf5 BS |
6220 | } |
6221 | } | |
32131a9c | 6222 | |
367b1cf5 | 6223 | /* We can't do that, so output an insn to load RELOADREG. */ |
32131a9c | 6224 | |
367b1cf5 BS |
6225 | #ifdef SECONDARY_INPUT_RELOAD_CLASS |
6226 | /* If we have a secondary reload, pick up the secondary register | |
6227 | and icode, if any. If OLDEQUIV and OLD are different or | |
6228 | if this is an in-out reload, recompute whether or not we | |
6229 | still need a secondary register and what the icode should | |
6230 | be. If we still need a secondary register and the class or | |
6231 | icode is different, go back to reloading from OLD if using | |
6232 | OLDEQUIV means that we got the wrong type of register. We | |
6233 | cannot have different class or icode due to an in-out reload | |
6234 | because we don't make such reloads when both the input and | |
6235 | output need secondary reload registers. */ | |
6236 | ||
07875628 | 6237 | if (! special && rl->secondary_in_reload >= 0) |
367b1cf5 BS |
6238 | { |
6239 | rtx second_reload_reg = 0; | |
6240 | int secondary_reload = rl->secondary_in_reload; | |
6241 | rtx real_oldequiv = oldequiv; | |
6242 | rtx real_old = old; | |
6243 | rtx tmp; | |
6244 | enum insn_code icode; | |
6245 | ||
6246 | /* If OLDEQUIV is a pseudo with a MEM, get the real MEM | |
6247 | and similarly for OLD. | |
6248 | See comments in get_secondary_reload in reload.c. */ | |
6249 | /* If it is a pseudo that cannot be replaced with its | |
6250 | equivalent MEM, we must fall back to reload_in, which | |
6251 | will have all the necessary substitutions registered. | |
6252 | Likewise for a pseudo that can't be replaced with its | |
6253 | equivalent constant. | |
6254 | ||
6255 | Take extra care for subregs of such pseudos. Note that | |
6256 | we cannot use reg_equiv_mem in this case because it is | |
6257 | not in the right mode. */ | |
6258 | ||
6259 | tmp = oldequiv; | |
6260 | if (GET_CODE (tmp) == SUBREG) | |
6261 | tmp = SUBREG_REG (tmp); | |
6262 | if (GET_CODE (tmp) == REG | |
6263 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER | |
6264 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6265 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6266 | { | |
6267 | if (! reg_equiv_mem[REGNO (tmp)] | |
6268 | || num_not_at_initial_offset | |
6269 | || GET_CODE (oldequiv) == SUBREG) | |
6270 | real_oldequiv = rl->in; | |
6271 | else | |
6272 | real_oldequiv = reg_equiv_mem[REGNO (tmp)]; | |
6273 | } | |
32131a9c | 6274 | |
367b1cf5 BS |
6275 | tmp = old; |
6276 | if (GET_CODE (tmp) == SUBREG) | |
6277 | tmp = SUBREG_REG (tmp); | |
6278 | if (GET_CODE (tmp) == REG | |
6279 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER | |
6280 | && (reg_equiv_memory_loc[REGNO (tmp)] != 0 | |
6281 | || reg_equiv_constant[REGNO (tmp)] != 0)) | |
6282 | { | |
6283 | if (! reg_equiv_mem[REGNO (tmp)] | |
6284 | || num_not_at_initial_offset | |
6285 | || GET_CODE (old) == SUBREG) | |
6286 | real_old = rl->in; | |
6287 | else | |
6288 | real_old = reg_equiv_mem[REGNO (tmp)]; | |
6289 | } | |
6290 | ||
6291 | second_reload_reg = rld[secondary_reload].reg_rtx; | |
6292 | icode = rl->secondary_in_icode; | |
6293 | ||
6294 | if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) | |
6295 | || (rl->in != 0 && rl->out != 0)) | |
6296 | { | |
6297 | enum reg_class new_class | |
6298 | = SECONDARY_INPUT_RELOAD_CLASS (rl->class, | |
6299 | mode, real_oldequiv); | |
6300 | ||
6301 | if (new_class == NO_REGS) | |
6302 | second_reload_reg = 0; | |
6303 | else | |
32131a9c | 6304 | { |
367b1cf5 BS |
6305 | enum insn_code new_icode; |
6306 | enum machine_mode new_mode; | |
6307 | ||
6308 | if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], | |
6309 | REGNO (second_reload_reg))) | |
6310 | oldequiv = old, real_oldequiv = real_old; | |
6311 | else | |
32131a9c | 6312 | { |
367b1cf5 BS |
6313 | new_icode = reload_in_optab[(int) mode]; |
6314 | if (new_icode != CODE_FOR_nothing | |
6315 | && ((insn_data[(int) new_icode].operand[0].predicate | |
6316 | && ! ((*insn_data[(int) new_icode].operand[0].predicate) | |
6317 | (reloadreg, mode))) | |
6318 | || (insn_data[(int) new_icode].operand[1].predicate | |
6319 | && ! ((*insn_data[(int) new_icode].operand[1].predicate) | |
6320 | (real_oldequiv, mode))))) | |
6321 | new_icode = CODE_FOR_nothing; | |
6322 | ||
6323 | if (new_icode == CODE_FOR_nothing) | |
6324 | new_mode = mode; | |
6325 | else | |
6326 | new_mode = insn_data[(int) new_icode].operand[2].mode; | |
d30e8ef0 | 6327 | |
367b1cf5 | 6328 | if (GET_MODE (second_reload_reg) != new_mode) |
32131a9c | 6329 | { |
367b1cf5 BS |
6330 | if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg), |
6331 | new_mode)) | |
6332 | oldequiv = old, real_oldequiv = real_old; | |
6333 | else | |
6334 | second_reload_reg | |
6335 | = gen_rtx_REG (new_mode, | |
6336 | REGNO (second_reload_reg)); | |
32131a9c | 6337 | } |
32131a9c RK |
6338 | } |
6339 | } | |
367b1cf5 | 6340 | } |
32131a9c | 6341 | |
367b1cf5 BS |
6342 | /* If we still need a secondary reload register, check |
6343 | to see if it is being used as a scratch or intermediate | |
6344 | register and generate code appropriately. If we need | |
6345 | a scratch register, use REAL_OLDEQUIV since the form of | |
6346 | the insn may depend on the actual address if it is | |
6347 | a MEM. */ | |
546b63fb | 6348 | |
367b1cf5 BS |
6349 | if (second_reload_reg) |
6350 | { | |
6351 | if (icode != CODE_FOR_nothing) | |
32131a9c | 6352 | { |
367b1cf5 BS |
6353 | emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, |
6354 | second_reload_reg)); | |
07875628 | 6355 | special = 1; |
367b1cf5 BS |
6356 | } |
6357 | else | |
6358 | { | |
6359 | /* See if we need a scratch register to load the | |
6360 | intermediate register (a tertiary reload). */ | |
6361 | enum insn_code tertiary_icode | |
6362 | = rld[secondary_reload].secondary_in_icode; | |
1554c2c6 | 6363 | |
367b1cf5 BS |
6364 | if (tertiary_icode != CODE_FOR_nothing) |
6365 | { | |
6366 | rtx third_reload_reg | |
6367 | = rld[rld[secondary_reload].secondary_in_reload].reg_rtx; | |
1554c2c6 | 6368 | |
367b1cf5 BS |
6369 | emit_insn ((GEN_FCN (tertiary_icode) |
6370 | (second_reload_reg, real_oldequiv, | |
6371 | third_reload_reg))); | |
6372 | } | |
6373 | else | |
6374 | gen_reload (second_reload_reg, real_oldequiv, | |
6375 | rl->opnum, | |
6376 | rl->when_needed); | |
32131a9c | 6377 | |
367b1cf5 BS |
6378 | oldequiv = second_reload_reg; |
6379 | } | |
6380 | } | |
6381 | } | |
6382 | #endif | |
32131a9c | 6383 | |
07875628 | 6384 | if (! special && ! rtx_equal_p (reloadreg, oldequiv)) |
367b1cf5 BS |
6385 | { |
6386 | rtx real_oldequiv = oldequiv; | |
6387 | ||
6388 | if ((GET_CODE (oldequiv) == REG | |
6389 | && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER | |
6390 | && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0 | |
6391 | || reg_equiv_constant[REGNO (oldequiv)] != 0)) | |
6392 | || (GET_CODE (oldequiv) == SUBREG | |
6393 | && GET_CODE (SUBREG_REG (oldequiv)) == REG | |
6394 | && (REGNO (SUBREG_REG (oldequiv)) | |
6395 | >= FIRST_PSEUDO_REGISTER) | |
6396 | && ((reg_equiv_memory_loc | |
6397 | [REGNO (SUBREG_REG (oldequiv))] != 0) | |
6398 | || (reg_equiv_constant | |
6399 | [REGNO (SUBREG_REG (oldequiv))] != 0)))) | |
6400 | real_oldequiv = rl->in; | |
6401 | gen_reload (reloadreg, real_oldequiv, rl->opnum, | |
6402 | rl->when_needed); | |
6403 | } | |
32131a9c | 6404 | |
367b1cf5 BS |
6405 | /* End this sequence. */ |
6406 | *where = get_insns (); | |
6407 | end_sequence (); | |
32131a9c | 6408 | |
367b1cf5 BS |
6409 | /* Update reload_override_in so that delete_address_reloads_1 |
6410 | can see the actual register usage. */ | |
6411 | if (oldequiv_reg) | |
6412 | reload_override_in[j] = oldequiv; | |
6413 | } | |
32131a9c | 6414 | |
367b1cf5 BS |
6415 | /* Generate insns to for the output reload RL, which is for the insn described |
6416 | by CHAIN and has the number J. */ | |
6417 | static void | |
6418 | emit_output_reload_insns (chain, rl, j) | |
6419 | struct insn_chain *chain; | |
6420 | struct reload *rl; | |
6421 | int j; | |
6422 | { | |
6423 | rtx reloadreg = rl->reg_rtx; | |
6424 | rtx insn = chain->insn; | |
6425 | int special = 0; | |
6426 | rtx old = rl->out; | |
6427 | enum machine_mode mode = GET_MODE (old); | |
6428 | rtx p; | |
32131a9c | 6429 | |
367b1cf5 BS |
6430 | if (rl->when_needed == RELOAD_OTHER) |
6431 | start_sequence (); | |
6432 | else | |
6433 | push_to_sequence (output_reload_insns[rl->opnum]); | |
32131a9c | 6434 | |
367b1cf5 BS |
6435 | /* Determine the mode to reload in. |
6436 | See comments above (for input reloading). */ | |
32131a9c | 6437 | |
367b1cf5 BS |
6438 | if (mode == VOIDmode) |
6439 | { | |
6440 | /* VOIDmode should never happen for an output. */ | |
6441 | if (asm_noperands (PATTERN (insn)) < 0) | |
6442 | /* It's the compiler's fault. */ | |
6443 | fatal_insn ("VOIDmode on an output", insn); | |
6444 | error_for_asm (insn, "output operand is constant in `asm'"); | |
6445 | /* Prevent crash--use something we know is valid. */ | |
6446 | mode = word_mode; | |
6447 | old = gen_rtx_REG (mode, REGNO (reloadreg)); | |
6448 | } | |
546b63fb | 6449 | |
367b1cf5 BS |
6450 | if (GET_MODE (reloadreg) != mode) |
6451 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
32131a9c | 6452 | |
367b1cf5 | 6453 | #ifdef SECONDARY_OUTPUT_RELOAD_CLASS |
32131a9c | 6454 | |
367b1cf5 BS |
6455 | /* If we need two reload regs, set RELOADREG to the intermediate |
6456 | one, since it will be stored into OLD. We might need a secondary | |
6457 | register only for an input reload, so check again here. */ | |
32131a9c | 6458 | |
367b1cf5 BS |
6459 | if (rl->secondary_out_reload >= 0) |
6460 | { | |
6461 | rtx real_old = old; | |
cb2afeb3 | 6462 | |
367b1cf5 BS |
6463 | if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER |
6464 | && reg_equiv_mem[REGNO (old)] != 0) | |
6465 | real_old = reg_equiv_mem[REGNO (old)]; | |
32131a9c | 6466 | |
367b1cf5 BS |
6467 | if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class, |
6468 | mode, real_old) | |
6469 | != NO_REGS)) | |
b60a8416 | 6470 | { |
367b1cf5 BS |
6471 | rtx second_reloadreg = reloadreg; |
6472 | reloadreg = rld[rl->secondary_out_reload].reg_rtx; | |
32131a9c | 6473 | |
367b1cf5 BS |
6474 | /* See if RELOADREG is to be used as a scratch register |
6475 | or as an intermediate register. */ | |
6476 | if (rl->secondary_out_icode != CODE_FOR_nothing) | |
6477 | { | |
6478 | emit_insn ((GEN_FCN (rl->secondary_out_icode) | |
6479 | (real_old, second_reloadreg, reloadreg))); | |
6480 | special = 1; | |
6481 | } | |
6482 | else | |
6483 | { | |
6484 | /* See if we need both a scratch and intermediate reload | |
6485 | register. */ | |
32131a9c | 6486 | |
367b1cf5 BS |
6487 | int secondary_reload = rl->secondary_out_reload; |
6488 | enum insn_code tertiary_icode | |
6489 | = rld[secondary_reload].secondary_out_icode; | |
32131a9c | 6490 | |
367b1cf5 BS |
6491 | if (GET_MODE (reloadreg) != mode) |
6492 | reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); | |
cb2afeb3 | 6493 | |
367b1cf5 BS |
6494 | if (tertiary_icode != CODE_FOR_nothing) |
6495 | { | |
6496 | rtx third_reloadreg | |
6497 | = rld[rld[secondary_reload].secondary_out_reload].reg_rtx; | |
6498 | rtx tem; | |
6499 | ||
6500 | /* Copy primary reload reg to secondary reload reg. | |
6501 | (Note that these have been swapped above, then | |
6502 | secondary reload reg to OLD using our insn. */ | |
6503 | ||
6504 | /* If REAL_OLD is a paradoxical SUBREG, remove it | |
6505 | and try to put the opposite SUBREG on | |
6506 | RELOADREG. */ | |
6507 | if (GET_CODE (real_old) == SUBREG | |
6508 | && (GET_MODE_SIZE (GET_MODE (real_old)) | |
6509 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old)))) | |
6510 | && 0 != (tem = gen_lowpart_common | |
6511 | (GET_MODE (SUBREG_REG (real_old)), | |
6512 | reloadreg))) | |
6513 | real_old = SUBREG_REG (real_old), reloadreg = tem; | |
6514 | ||
6515 | gen_reload (reloadreg, second_reloadreg, | |
6516 | rl->opnum, rl->when_needed); | |
6517 | emit_insn ((GEN_FCN (tertiary_icode) | |
6518 | (real_old, reloadreg, third_reloadreg))); | |
6519 | special = 1; | |
6520 | } | |
05d10675 | 6521 | |
367b1cf5 BS |
6522 | else |
6523 | /* Copy between the reload regs here and then to | |
6524 | OUT later. */ | |
cb2afeb3 | 6525 | |
367b1cf5 BS |
6526 | gen_reload (reloadreg, second_reloadreg, |
6527 | rl->opnum, rl->when_needed); | |
a7911cd2 | 6528 | } |
367b1cf5 BS |
6529 | } |
6530 | } | |
32131a9c RK |
6531 | #endif |
6532 | ||
367b1cf5 BS |
6533 | /* Output the last reload insn. */ |
6534 | if (! special) | |
6535 | { | |
6536 | rtx set; | |
6537 | ||
6538 | /* Don't output the last reload if OLD is not the dest of | |
6539 | INSN and is in the src and is clobbered by INSN. */ | |
6540 | if (! flag_expensive_optimizations | |
6541 | || GET_CODE (old) != REG | |
6542 | || !(set = single_set (insn)) | |
6543 | || rtx_equal_p (old, SET_DEST (set)) | |
6544 | || !reg_mentioned_p (old, SET_SRC (set)) | |
6545 | || !regno_clobbered_p (REGNO (old), insn)) | |
6546 | gen_reload (old, reloadreg, rl->opnum, | |
6547 | rl->when_needed); | |
6548 | } | |
32131a9c | 6549 | |
367b1cf5 BS |
6550 | /* Look at all insns we emitted, just to be safe. */ |
6551 | for (p = get_insns (); p; p = NEXT_INSN (p)) | |
6552 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i') | |
6553 | { | |
6554 | rtx pat = PATTERN (p); | |
546b63fb | 6555 | |
367b1cf5 BS |
6556 | /* If this output reload doesn't come from a spill reg, |
6557 | clear any memory of reloaded copies of the pseudo reg. | |
6558 | If this output reload comes from a spill reg, | |
6559 | reg_has_output_reload will make this do nothing. */ | |
6560 | note_stores (pat, forget_old_reloads_1, NULL); | |
cb2afeb3 | 6561 | |
367b1cf5 BS |
6562 | if (reg_mentioned_p (rl->reg_rtx, pat)) |
6563 | { | |
6564 | rtx set = single_set (insn); | |
6565 | if (reload_spill_index[j] < 0 | |
6566 | && set | |
6567 | && SET_SRC (set) == rl->reg_rtx) | |
6568 | { | |
6569 | int src = REGNO (SET_SRC (set)); | |
32131a9c | 6570 | |
367b1cf5 BS |
6571 | reload_spill_index[j] = src; |
6572 | SET_HARD_REG_BIT (reg_is_output_reload, src); | |
6573 | if (find_regno_note (insn, REG_DEAD, src)) | |
6574 | SET_HARD_REG_BIT (reg_reloaded_died, src); | |
6575 | } | |
6576 | if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER) | |
6577 | { | |
6578 | int s = rl->secondary_out_reload; | |
6579 | set = single_set (p); | |
6580 | /* If this reload copies only to the secondary reload | |
6581 | register, the secondary reload does the actual | |
6582 | store. */ | |
6583 | if (s >= 0 && set == NULL_RTX) | |
6584 | ; /* We can't tell what function the secondary reload | |
6585 | has and where the actual store to the pseudo is | |
6586 | made; leave new_spill_reg_store alone. */ | |
6587 | else if (s >= 0 | |
6588 | && SET_SRC (set) == rl->reg_rtx | |
6589 | && SET_DEST (set) == rld[s].reg_rtx) | |
6590 | { | |
6591 | /* Usually the next instruction will be the | |
6592 | secondary reload insn; if we can confirm | |
6593 | that it is, setting new_spill_reg_store to | |
6594 | that insn will allow an extra optimization. */ | |
6595 | rtx s_reg = rld[s].reg_rtx; | |
6596 | rtx next = NEXT_INSN (p); | |
6597 | rld[s].out = rl->out; | |
6598 | rld[s].out_reg = rl->out_reg; | |
6599 | set = single_set (next); | |
6600 | if (set && SET_SRC (set) == s_reg | |
6601 | && ! new_spill_reg_store[REGNO (s_reg)]) | |
6602 | { | |
6603 | SET_HARD_REG_BIT (reg_is_output_reload, | |
6604 | REGNO (s_reg)); | |
6605 | new_spill_reg_store[REGNO (s_reg)] = next; | |
6606 | } | |
6607 | } | |
6608 | else | |
6609 | new_spill_reg_store[REGNO (rl->reg_rtx)] = p; | |
6610 | } | |
6611 | } | |
6612 | } | |
32131a9c | 6613 | |
367b1cf5 BS |
6614 | if (rl->when_needed == RELOAD_OTHER) |
6615 | { | |
6616 | emit_insns (other_output_reload_insns[rl->opnum]); | |
6617 | other_output_reload_insns[rl->opnum] = get_insns (); | |
6618 | } | |
6619 | else | |
6620 | output_reload_insns[rl->opnum] = get_insns (); | |
32131a9c | 6621 | |
367b1cf5 BS |
6622 | end_sequence (); |
6623 | } | |
32131a9c | 6624 | |
367b1cf5 BS |
6625 | /* Do input reloading for reload RL, which is for the insn described by CHAIN |
6626 | and has the number J. */ | |
6627 | static void | |
6628 | do_input_reload (chain, rl, j) | |
6629 | struct insn_chain *chain; | |
6630 | struct reload *rl; | |
6631 | int j; | |
6632 | { | |
6633 | int expect_occurrences = 1; | |
6634 | rtx insn = chain->insn; | |
6635 | rtx old = (rl->in && GET_CODE (rl->in) == MEM | |
6636 | ? rl->in_reg : rl->in); | |
6637 | ||
6638 | if (old != 0 | |
6639 | /* AUTO_INC reloads need to be handled even if inherited. We got an | |
6640 | AUTO_INC reload if reload_out is set but reload_out_reg isn't. */ | |
6641 | && (! reload_inherited[j] || (rl->out && ! rl->out_reg)) | |
6642 | && ! rtx_equal_p (rl->reg_rtx, old) | |
6643 | && rl->reg_rtx != 0) | |
1d813780 | 6644 | emit_input_reload_insns (chain, rld + j, old, j); |
32131a9c | 6645 | |
367b1cf5 BS |
6646 | /* When inheriting a wider reload, we have a MEM in rl->in, |
6647 | e.g. inheriting a SImode output reload for | |
6648 | (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */ | |
6649 | if (optimize && reload_inherited[j] && rl->in | |
6650 | && GET_CODE (rl->in) == MEM | |
6651 | && GET_CODE (rl->in_reg) == MEM | |
6652 | && reload_spill_index[j] >= 0 | |
6653 | && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j])) | |
6654 | { | |
6655 | expect_occurrences | |
6656 | = count_occurrences (PATTERN (insn), rl->in) == 1 ? 0 : -1; | |
6657 | rl->in | |
6658 | = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]]; | |
6659 | } | |
32131a9c | 6660 | |
367b1cf5 BS |
6661 | /* If we are reloading a register that was recently stored in with an |
6662 | output-reload, see if we can prove there was | |
6663 | actually no need to store the old value in it. */ | |
32131a9c | 6664 | |
367b1cf5 BS |
6665 | if (optimize |
6666 | && (reload_inherited[j] || reload_override_in[j]) | |
6667 | && rl->reg_rtx | |
6668 | && GET_CODE (rl->reg_rtx) == REG | |
6669 | && spill_reg_store[REGNO (rl->reg_rtx)] != 0 | |
6670 | #if 0 | |
6671 | /* There doesn't seem to be any reason to restrict this to pseudos | |
6672 | and doing so loses in the case where we are copying from a | |
6673 | register of the wrong class. */ | |
6674 | && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
6675 | >= FIRST_PSEUDO_REGISTER) | |
6676 | #endif | |
6677 | /* The insn might have already some references to stackslots | |
6678 | replaced by MEMs, while reload_out_reg still names the | |
6679 | original pseudo. */ | |
6680 | && (dead_or_set_p (insn, | |
6681 | spill_reg_stored_to[REGNO (rl->reg_rtx)]) | |
6682 | || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)], | |
6683 | rl->out_reg))) | |
6684 | delete_output_reload (insn, j, REGNO (rl->reg_rtx)); | |
6685 | } | |
32131a9c | 6686 | |
367b1cf5 BS |
6687 | /* Do output reloading for reload RL, which is for the insn described by |
6688 | CHAIN and has the number J. | |
6689 | ??? At some point we need to support handling output reloads of | |
6690 | JUMP_INSNs or insns that set cc0. */ | |
6691 | static void | |
6692 | do_output_reload (chain, rl, j) | |
6693 | struct insn_chain *chain; | |
6694 | struct reload *rl; | |
6695 | int j; | |
6696 | { | |
6697 | rtx note, old; | |
6698 | rtx insn = chain->insn; | |
6699 | /* If this is an output reload that stores something that is | |
6700 | not loaded in this same reload, see if we can eliminate a previous | |
6701 | store. */ | |
6702 | rtx pseudo = rl->out_reg; | |
6703 | ||
6704 | if (pseudo | |
6705 | && GET_CODE (pseudo) == REG | |
6706 | && ! rtx_equal_p (rl->in_reg, pseudo) | |
6707 | && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER | |
6708 | && reg_last_reload_reg[REGNO (pseudo)]) | |
6709 | { | |
6710 | int pseudo_no = REGNO (pseudo); | |
6711 | int last_regno = REGNO (reg_last_reload_reg[pseudo_no]); | |
6712 | ||
6713 | /* We don't need to test full validity of last_regno for | |
6714 | inherit here; we only want to know if the store actually | |
6715 | matches the pseudo. */ | |
60ef417d GK |
6716 | if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno) |
6717 | && reg_reloaded_contents[last_regno] == pseudo_no | |
367b1cf5 BS |
6718 | && spill_reg_store[last_regno] |
6719 | && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) | |
6720 | delete_output_reload (insn, j, last_regno); | |
6721 | } | |
5e03c156 | 6722 | |
367b1cf5 BS |
6723 | old = rl->out_reg; |
6724 | if (old == 0 | |
6725 | || rl->reg_rtx == old | |
6726 | || rl->reg_rtx == 0) | |
6727 | return; | |
32131a9c | 6728 | |
367b1cf5 BS |
6729 | /* An output operand that dies right away does need a reload, |
6730 | but need not be copied from it. Show the new location in the | |
6731 | REG_UNUSED note. */ | |
6732 | if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH) | |
6733 | && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) | |
6734 | { | |
6735 | XEXP (note, 0) = rl->reg_rtx; | |
6736 | return; | |
6737 | } | |
6738 | /* Likewise for a SUBREG of an operand that dies. */ | |
6739 | else if (GET_CODE (old) == SUBREG | |
6740 | && GET_CODE (SUBREG_REG (old)) == REG | |
6741 | && 0 != (note = find_reg_note (insn, REG_UNUSED, | |
6742 | SUBREG_REG (old)))) | |
6743 | { | |
6744 | XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), | |
6745 | rl->reg_rtx); | |
6746 | return; | |
6747 | } | |
6748 | else if (GET_CODE (old) == SCRATCH) | |
6749 | /* If we aren't optimizing, there won't be a REG_UNUSED note, | |
6750 | but we don't want to make an output reload. */ | |
6751 | return; | |
1554c2c6 | 6752 | |
367b1cf5 BS |
6753 | /* If is a JUMP_INSN, we can't support output reloads yet. */ |
6754 | if (GET_CODE (insn) == JUMP_INSN) | |
6755 | abort (); | |
5e03c156 | 6756 | |
367b1cf5 BS |
6757 | emit_output_reload_insns (chain, rld + j, j); |
6758 | } | |
1554c2c6 | 6759 | |
367b1cf5 | 6760 | /* Output insns to reload values in and out of the chosen reload regs. */ |
32131a9c | 6761 | |
367b1cf5 BS |
6762 | static void |
6763 | emit_reload_insns (chain) | |
6764 | struct insn_chain *chain; | |
6765 | { | |
6766 | rtx insn = chain->insn; | |
32131a9c | 6767 | |
367b1cf5 BS |
6768 | register int j; |
6769 | rtx following_insn = NEXT_INSN (insn); | |
6770 | rtx before_insn = PREV_INSN (insn); | |
e6e52be0 | 6771 | |
367b1cf5 | 6772 | CLEAR_HARD_REG_SET (reg_reloaded_died); |
e6e52be0 | 6773 | |
367b1cf5 BS |
6774 | for (j = 0; j < reload_n_operands; j++) |
6775 | input_reload_insns[j] = input_address_reload_insns[j] | |
6776 | = inpaddr_address_reload_insns[j] | |
6777 | = output_reload_insns[j] = output_address_reload_insns[j] | |
6778 | = outaddr_address_reload_insns[j] | |
6779 | = other_output_reload_insns[j] = 0; | |
6780 | other_input_address_reload_insns = 0; | |
6781 | other_input_reload_insns = 0; | |
6782 | operand_reload_insns = 0; | |
6783 | other_operand_reload_insns = 0; | |
32131a9c | 6784 | |
367b1cf5 BS |
6785 | /* Now output the instructions to copy the data into and out of the |
6786 | reload registers. Do these in the order that the reloads were reported, | |
6787 | since reloads of base and index registers precede reloads of operands | |
6788 | and the operands may need the base and index registers reloaded. */ | |
32131a9c | 6789 | |
367b1cf5 BS |
6790 | for (j = 0; j < n_reloads; j++) |
6791 | { | |
6792 | if (rld[j].reg_rtx | |
6793 | && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER) | |
6794 | new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0; | |
d7e0324f | 6795 | |
367b1cf5 BS |
6796 | do_input_reload (chain, rld + j, j); |
6797 | do_output_reload (chain, rld + j, j); | |
32131a9c RK |
6798 | } |
6799 | ||
546b63fb RK |
6800 | /* Now write all the insns we made for reloads in the order expected by |
6801 | the allocation functions. Prior to the insn being reloaded, we write | |
6802 | the following reloads: | |
6803 | ||
6804 | RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. | |
6805 | ||
2edc8d65 | 6806 | RELOAD_OTHER reloads. |
546b63fb | 6807 | |
47c8cf91 ILT |
6808 | For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed |
6809 | by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the | |
6810 | RELOAD_FOR_INPUT reload for the operand. | |
546b63fb | 6811 | |
893bc853 RK |
6812 | RELOAD_FOR_OPADDR_ADDRS reloads. |
6813 | ||
546b63fb RK |
6814 | RELOAD_FOR_OPERAND_ADDRESS reloads. |
6815 | ||
6816 | After the insn being reloaded, we write the following: | |
6817 | ||
47c8cf91 ILT |
6818 | For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed |
6819 | by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the | |
6820 | RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output | |
6821 | reloads for the operand. The RELOAD_OTHER output reloads are | |
6822 | output in descending order by reload number. */ | |
546b63fb | 6823 | |
c93b03c2 RH |
6824 | emit_insns_before (other_input_address_reload_insns, insn); |
6825 | emit_insns_before (other_input_reload_insns, insn); | |
546b63fb RK |
6826 | |
6827 | for (j = 0; j < reload_n_operands; j++) | |
6828 | { | |
c93b03c2 RH |
6829 | emit_insns_before (inpaddr_address_reload_insns[j], insn); |
6830 | emit_insns_before (input_address_reload_insns[j], insn); | |
6831 | emit_insns_before (input_reload_insns[j], insn); | |
546b63fb RK |
6832 | } |
6833 | ||
c93b03c2 RH |
6834 | emit_insns_before (other_operand_reload_insns, insn); |
6835 | emit_insns_before (operand_reload_insns, insn); | |
546b63fb RK |
6836 | |
6837 | for (j = 0; j < reload_n_operands; j++) | |
6838 | { | |
47c8cf91 | 6839 | emit_insns_before (outaddr_address_reload_insns[j], following_insn); |
546b63fb RK |
6840 | emit_insns_before (output_address_reload_insns[j], following_insn); |
6841 | emit_insns_before (output_reload_insns[j], following_insn); | |
befa01b9 | 6842 | emit_insns_before (other_output_reload_insns[j], following_insn); |
c93b03c2 RH |
6843 | } |
6844 | ||
6845 | /* Keep basic block info up to date. */ | |
6846 | if (n_basic_blocks) | |
6847 | { | |
3b413743 | 6848 | if (BLOCK_HEAD (chain->block) == insn) |
05d10675 | 6849 | BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn); |
3b413743 | 6850 | if (BLOCK_END (chain->block) == insn) |
05d10675 | 6851 | BLOCK_END (chain->block) = PREV_INSN (following_insn); |
546b63fb RK |
6852 | } |
6853 | ||
32131a9c RK |
6854 | /* For all the spill regs newly reloaded in this instruction, |
6855 | record what they were reloaded from, so subsequent instructions | |
d445b551 RK |
6856 | can inherit the reloads. |
6857 | ||
6858 | Update spill_reg_store for the reloads of this insn. | |
e9e79d69 | 6859 | Copy the elements that were updated in the loop above. */ |
32131a9c RK |
6860 | |
6861 | for (j = 0; j < n_reloads; j++) | |
6862 | { | |
6863 | register int r = reload_order[j]; | |
6864 | register int i = reload_spill_index[r]; | |
6865 | ||
78a2bc08 | 6866 | /* If this is a non-inherited input reload from a pseudo, we must |
05d10675 BS |
6867 | clear any memory of a previous store to the same pseudo. Only do |
6868 | something if there will not be an output reload for the pseudo | |
6869 | being reloaded. */ | |
eceef4c9 | 6870 | if (rld[r].in_reg != 0 |
05d10675 BS |
6871 | && ! (reload_inherited[r] || reload_override_in[r])) |
6872 | { | |
eceef4c9 | 6873 | rtx reg = rld[r].in_reg; |
78a2bc08 | 6874 | |
05d10675 | 6875 | if (GET_CODE (reg) == SUBREG) |
78a2bc08 | 6876 | reg = SUBREG_REG (reg); |
05d10675 BS |
6877 | |
6878 | if (GET_CODE (reg) == REG | |
78a2bc08 R |
6879 | && REGNO (reg) >= FIRST_PSEUDO_REGISTER |
6880 | && ! reg_has_output_reload[REGNO (reg)]) | |
6881 | { | |
6882 | int nregno = REGNO (reg); | |
6883 | ||
6884 | if (reg_last_reload_reg[nregno]) | |
05d10675 BS |
6885 | { |
6886 | int last_regno = REGNO (reg_last_reload_reg[nregno]); | |
78a2bc08 | 6887 | |
05d10675 | 6888 | if (reg_reloaded_contents[last_regno] == nregno) |
78a2bc08 | 6889 | spill_reg_store[last_regno] = 0; |
05d10675 | 6890 | } |
78a2bc08 R |
6891 | } |
6892 | } | |
05d10675 | 6893 | |
e6e52be0 | 6894 | /* I is nonneg if this reload used a register. |
eceef4c9 | 6895 | If rld[r].reg_rtx is 0, this is an optional reload |
51f0c3b7 | 6896 | that we opted to ignore. */ |
d445b551 | 6897 | |
eceef4c9 | 6898 | if (i >= 0 && rld[r].reg_rtx != 0) |
32131a9c | 6899 | { |
32131a9c | 6900 | int nr |
eceef4c9 | 6901 | = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx)); |
32131a9c | 6902 | int k; |
51f0c3b7 JW |
6903 | int part_reaches_end = 0; |
6904 | int all_reaches_end = 1; | |
32131a9c | 6905 | |
51f0c3b7 JW |
6906 | /* For a multi register reload, we need to check if all or part |
6907 | of the value lives to the end. */ | |
32131a9c RK |
6908 | for (k = 0; k < nr; k++) |
6909 | { | |
eceef4c9 BS |
6910 | if (reload_reg_reaches_end_p (i + k, rld[r].opnum, |
6911 | rld[r].when_needed)) | |
51f0c3b7 JW |
6912 | part_reaches_end = 1; |
6913 | else | |
6914 | all_reaches_end = 0; | |
32131a9c RK |
6915 | } |
6916 | ||
51f0c3b7 JW |
6917 | /* Ignore reloads that don't reach the end of the insn in |
6918 | entirety. */ | |
6919 | if (all_reaches_end) | |
32131a9c | 6920 | { |
51f0c3b7 JW |
6921 | /* First, clear out memory of what used to be in this spill reg. |
6922 | If consecutive registers are used, clear them all. */ | |
d08ea79f | 6923 | |
32131a9c | 6924 | for (k = 0; k < nr; k++) |
e6e52be0 | 6925 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
d08ea79f | 6926 | |
51f0c3b7 | 6927 | /* Maybe the spill reg contains a copy of reload_out. */ |
eceef4c9 BS |
6928 | if (rld[r].out != 0 |
6929 | && (GET_CODE (rld[r].out) == REG | |
cb2afeb3 | 6930 | #ifdef AUTO_INC_DEC |
eceef4c9 | 6931 | || ! rld[r].out_reg |
cb2afeb3 | 6932 | #endif |
eceef4c9 | 6933 | || GET_CODE (rld[r].out_reg) == REG)) |
51f0c3b7 | 6934 | { |
eceef4c9 BS |
6935 | rtx out = (GET_CODE (rld[r].out) == REG |
6936 | ? rld[r].out | |
6937 | : rld[r].out_reg | |
6938 | ? rld[r].out_reg | |
6939 | /* AUTO_INC */ : XEXP (rld[r].in_reg, 0)); | |
cb2afeb3 | 6940 | register int nregno = REGNO (out); |
51f0c3b7 JW |
6941 | int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
6942 | : HARD_REGNO_NREGS (nregno, | |
eceef4c9 | 6943 | GET_MODE (rld[r].reg_rtx))); |
51f0c3b7 JW |
6944 | |
6945 | spill_reg_store[i] = new_spill_reg_store[i]; | |
cb2afeb3 | 6946 | spill_reg_stored_to[i] = out; |
eceef4c9 | 6947 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
51f0c3b7 JW |
6948 | |
6949 | /* If NREGNO is a hard register, it may occupy more than | |
05d10675 | 6950 | one register. If it does, say what is in the |
51f0c3b7 JW |
6951 | rest of the registers assuming that both registers |
6952 | agree on how many words the object takes. If not, | |
6953 | invalidate the subsequent registers. */ | |
6954 | ||
6955 | if (nregno < FIRST_PSEUDO_REGISTER) | |
6956 | for (k = 1; k < nnr; k++) | |
6957 | reg_last_reload_reg[nregno + k] | |
6958 | = (nr == nnr | |
eceef4c9 BS |
6959 | ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k], |
6960 | REGNO (rld[r].reg_rtx) + k) | |
51f0c3b7 JW |
6961 | : 0); |
6962 | ||
6963 | /* Now do the inverse operation. */ | |
6964 | for (k = 0; k < nr; k++) | |
6965 | { | |
e6e52be0 R |
6966 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
6967 | reg_reloaded_contents[i + k] | |
51f0c3b7 JW |
6968 | = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr |
6969 | ? nregno | |
6970 | : nregno + k); | |
e6e52be0 R |
6971 | reg_reloaded_insn[i + k] = insn; |
6972 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
51f0c3b7 JW |
6973 | } |
6974 | } | |
d08ea79f | 6975 | |
51f0c3b7 JW |
6976 | /* Maybe the spill reg contains a copy of reload_in. Only do |
6977 | something if there will not be an output reload for | |
6978 | the register being reloaded. */ | |
eceef4c9 BS |
6979 | else if (rld[r].out_reg == 0 |
6980 | && rld[r].in != 0 | |
6981 | && ((GET_CODE (rld[r].in) == REG | |
6982 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER | |
6983 | && ! reg_has_output_reload[REGNO (rld[r].in)]) | |
6984 | || (GET_CODE (rld[r].in_reg) == REG | |
6985 | && ! reg_has_output_reload[REGNO (rld[r].in_reg)])) | |
6986 | && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn))) | |
51f0c3b7 JW |
6987 | { |
6988 | register int nregno; | |
6989 | int nnr; | |
d445b551 | 6990 | |
eceef4c9 BS |
6991 | if (GET_CODE (rld[r].in) == REG |
6992 | && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER) | |
6993 | nregno = REGNO (rld[r].in); | |
6994 | else if (GET_CODE (rld[r].in_reg) == REG) | |
6995 | nregno = REGNO (rld[r].in_reg); | |
cb2afeb3 | 6996 | else |
eceef4c9 | 6997 | nregno = REGNO (XEXP (rld[r].in_reg, 0)); |
d08ea79f | 6998 | |
51f0c3b7 JW |
6999 | nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 |
7000 | : HARD_REGNO_NREGS (nregno, | |
eceef4c9 | 7001 | GET_MODE (rld[r].reg_rtx))); |
05d10675 | 7002 | |
eceef4c9 | 7003 | reg_last_reload_reg[nregno] = rld[r].reg_rtx; |
51f0c3b7 JW |
7004 | |
7005 | if (nregno < FIRST_PSEUDO_REGISTER) | |
7006 | for (k = 1; k < nnr; k++) | |
7007 | reg_last_reload_reg[nregno + k] | |
7008 | = (nr == nnr | |
eceef4c9 BS |
7009 | ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k], |
7010 | REGNO (rld[r].reg_rtx) + k) | |
51f0c3b7 JW |
7011 | : 0); |
7012 | ||
7013 | /* Unless we inherited this reload, show we haven't | |
cb2afeb3 R |
7014 | recently done a store. |
7015 | Previous stores of inherited auto_inc expressions | |
7016 | also have to be discarded. */ | |
7017 | if (! reload_inherited[r] | |
eceef4c9 | 7018 | || (rld[r].out && ! rld[r].out_reg)) |
51f0c3b7 JW |
7019 | spill_reg_store[i] = 0; |
7020 | ||
7021 | for (k = 0; k < nr; k++) | |
7022 | { | |
e6e52be0 R |
7023 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); |
7024 | reg_reloaded_contents[i + k] | |
51f0c3b7 JW |
7025 | = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr |
7026 | ? nregno | |
7027 | : nregno + k); | |
e6e52be0 R |
7028 | reg_reloaded_insn[i + k] = insn; |
7029 | SET_HARD_REG_BIT (reg_reloaded_valid, i + k); | |
51f0c3b7 JW |
7030 | } |
7031 | } | |
7032 | } | |
d445b551 | 7033 | |
51f0c3b7 JW |
7034 | /* However, if part of the reload reaches the end, then we must |
7035 | invalidate the old info for the part that survives to the end. */ | |
7036 | else if (part_reaches_end) | |
7037 | { | |
546b63fb | 7038 | for (k = 0; k < nr; k++) |
e6e52be0 | 7039 | if (reload_reg_reaches_end_p (i + k, |
eceef4c9 BS |
7040 | rld[r].opnum, |
7041 | rld[r].when_needed)) | |
e6e52be0 | 7042 | CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); |
32131a9c RK |
7043 | } |
7044 | } | |
7045 | ||
7046 | /* The following if-statement was #if 0'd in 1.34 (or before...). | |
7047 | It's reenabled in 1.35 because supposedly nothing else | |
7048 | deals with this problem. */ | |
7049 | ||
7050 | /* If a register gets output-reloaded from a non-spill register, | |
7051 | that invalidates any previous reloaded copy of it. | |
7052 | But forget_old_reloads_1 won't get to see it, because | |
7053 | it thinks only about the original insn. So invalidate it here. */ | |
eceef4c9 BS |
7054 | if (i < 0 && rld[r].out != 0 |
7055 | && (GET_CODE (rld[r].out) == REG | |
7056 | || (GET_CODE (rld[r].out) == MEM | |
7057 | && GET_CODE (rld[r].out_reg) == REG))) | |
32131a9c | 7058 | { |
eceef4c9 BS |
7059 | rtx out = (GET_CODE (rld[r].out) == REG |
7060 | ? rld[r].out : rld[r].out_reg); | |
cb2afeb3 | 7061 | register int nregno = REGNO (out); |
c7093272 | 7062 | if (nregno >= FIRST_PSEUDO_REGISTER) |
cb2afeb3 | 7063 | { |
6a651371 | 7064 | rtx src_reg, store_insn = NULL_RTX; |
cb2afeb3 R |
7065 | |
7066 | reg_last_reload_reg[nregno] = 0; | |
7067 | ||
7068 | /* If we can find a hard register that is stored, record | |
7069 | the storing insn so that we may delete this insn with | |
7070 | delete_output_reload. */ | |
eceef4c9 | 7071 | src_reg = rld[r].reg_rtx; |
cb2afeb3 R |
7072 | |
7073 | /* If this is an optional reload, try to find the source reg | |
7074 | from an input reload. */ | |
7075 | if (! src_reg) | |
7076 | { | |
7077 | rtx set = single_set (insn); | |
eceef4c9 | 7078 | if (set && SET_DEST (set) == rld[r].out) |
cb2afeb3 R |
7079 | { |
7080 | int k; | |
7081 | ||
7082 | src_reg = SET_SRC (set); | |
7083 | store_insn = insn; | |
7084 | for (k = 0; k < n_reloads; k++) | |
7085 | { | |
eceef4c9 | 7086 | if (rld[k].in == src_reg) |
cb2afeb3 | 7087 | { |
eceef4c9 | 7088 | src_reg = rld[k].reg_rtx; |
cb2afeb3 R |
7089 | break; |
7090 | } | |
7091 | } | |
7092 | } | |
7093 | } | |
7094 | else | |
7095 | store_insn = new_spill_reg_store[REGNO (src_reg)]; | |
7096 | if (src_reg && GET_CODE (src_reg) == REG | |
7097 | && REGNO (src_reg) < FIRST_PSEUDO_REGISTER) | |
7098 | { | |
7099 | int src_regno = REGNO (src_reg); | |
8ec450a4 | 7100 | int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode); |
cb2afeb3 R |
7101 | /* The place where to find a death note varies with |
7102 | PRESERVE_DEATH_INFO_REGNO_P . The condition is not | |
7103 | necessarily checked exactly in the code that moves | |
7104 | notes, so just check both locations. */ | |
7105 | rtx note = find_regno_note (insn, REG_DEAD, src_regno); | |
7106 | if (! note) | |
7107 | note = find_regno_note (store_insn, REG_DEAD, src_regno); | |
7108 | while (nr-- > 0) | |
7109 | { | |
7110 | spill_reg_store[src_regno + nr] = store_insn; | |
7111 | spill_reg_stored_to[src_regno + nr] = out; | |
7112 | reg_reloaded_contents[src_regno + nr] = nregno; | |
7113 | reg_reloaded_insn[src_regno + nr] = store_insn; | |
00f9f1bc | 7114 | CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr); |
cb2afeb3 R |
7115 | SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr); |
7116 | SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr); | |
7117 | if (note) | |
7118 | SET_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7119 | else | |
7120 | CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno); | |
7121 | } | |
7122 | reg_last_reload_reg[nregno] = src_reg; | |
7123 | } | |
7124 | } | |
c7093272 RK |
7125 | else |
7126 | { | |
eceef4c9 | 7127 | int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (rld[r].out)); |
36281332 | 7128 | |
c7093272 RK |
7129 | while (num_regs-- > 0) |
7130 | reg_last_reload_reg[nregno + num_regs] = 0; | |
7131 | } | |
32131a9c RK |
7132 | } |
7133 | } | |
e6e52be0 | 7134 | IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died); |
32131a9c RK |
7135 | } |
7136 | \f | |
5e03c156 RK |
7137 | /* Emit code to perform a reload from IN (which may be a reload register) to |
7138 | OUT (which may also be a reload register). IN or OUT is from operand | |
05d10675 | 7139 | OPNUM with reload type TYPE. |
546b63fb | 7140 | |
3c3eeea6 | 7141 | Returns first insn emitted. */ |
32131a9c RK |
7142 | |
7143 | rtx | |
5e03c156 RK |
7144 | gen_reload (out, in, opnum, type) |
7145 | rtx out; | |
32131a9c | 7146 | rtx in; |
546b63fb RK |
7147 | int opnum; |
7148 | enum reload_type type; | |
32131a9c | 7149 | { |
546b63fb | 7150 | rtx last = get_last_insn (); |
7a5b18b0 RK |
7151 | rtx tem; |
7152 | ||
7153 | /* If IN is a paradoxical SUBREG, remove it and try to put the | |
7154 | opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ | |
7155 | if (GET_CODE (in) == SUBREG | |
7156 | && (GET_MODE_SIZE (GET_MODE (in)) | |
7157 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) | |
7158 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0) | |
7159 | in = SUBREG_REG (in), out = tem; | |
7160 | else if (GET_CODE (out) == SUBREG | |
eceef4c9 BS |
7161 | && (GET_MODE_SIZE (GET_MODE (out)) |
7162 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) | |
7163 | && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0) | |
7a5b18b0 | 7164 | out = SUBREG_REG (out), in = tem; |
32131a9c | 7165 | |
a8fdc208 | 7166 | /* How to do this reload can get quite tricky. Normally, we are being |
32131a9c RK |
7167 | asked to reload a simple operand, such as a MEM, a constant, or a pseudo |
7168 | register that didn't get a hard register. In that case we can just | |
7169 | call emit_move_insn. | |
7170 | ||
a7fd196c JW |
7171 | We can also be asked to reload a PLUS that adds a register or a MEM to |
7172 | another register, constant or MEM. This can occur during frame pointer | |
7173 | elimination and while reloading addresses. This case is handled by | |
7174 | trying to emit a single insn to perform the add. If it is not valid, | |
7175 | we use a two insn sequence. | |
32131a9c RK |
7176 | |
7177 | Finally, we could be called to handle an 'o' constraint by putting | |
7178 | an address into a register. In that case, we first try to do this | |
7179 | with a named pattern of "reload_load_address". If no such pattern | |
7180 | exists, we just emit a SET insn and hope for the best (it will normally | |
7181 | be valid on machines that use 'o'). | |
7182 | ||
7183 | This entire process is made complex because reload will never | |
7184 | process the insns we generate here and so we must ensure that | |
7185 | they will fit their constraints and also by the fact that parts of | |
7186 | IN might be being reloaded separately and replaced with spill registers. | |
7187 | Because of this, we are, in some sense, just guessing the right approach | |
7188 | here. The one listed above seems to work. | |
7189 | ||
7190 | ??? At some point, this whole thing needs to be rethought. */ | |
7191 | ||
7192 | if (GET_CODE (in) == PLUS | |
a7fd196c | 7193 | && (GET_CODE (XEXP (in, 0)) == REG |
5c6b1bd2 | 7194 | || GET_CODE (XEXP (in, 0)) == SUBREG |
a7fd196c JW |
7195 | || GET_CODE (XEXP (in, 0)) == MEM) |
7196 | && (GET_CODE (XEXP (in, 1)) == REG | |
5c6b1bd2 | 7197 | || GET_CODE (XEXP (in, 1)) == SUBREG |
a7fd196c JW |
7198 | || CONSTANT_P (XEXP (in, 1)) |
7199 | || GET_CODE (XEXP (in, 1)) == MEM)) | |
32131a9c | 7200 | { |
a7fd196c JW |
7201 | /* We need to compute the sum of a register or a MEM and another |
7202 | register, constant, or MEM, and put it into the reload | |
3002e160 JW |
7203 | register. The best possible way of doing this is if the machine |
7204 | has a three-operand ADD insn that accepts the required operands. | |
32131a9c RK |
7205 | |
7206 | The simplest approach is to try to generate such an insn and see if it | |
7207 | is recognized and matches its constraints. If so, it can be used. | |
7208 | ||
7209 | It might be better not to actually emit the insn unless it is valid, | |
0009eff2 | 7210 | but we need to pass the insn as an operand to `recog' and |
0eadeb15 | 7211 | `extract_insn' and it is simpler to emit and then delete the insn if |
0009eff2 | 7212 | not valid than to dummy things up. */ |
a8fdc208 | 7213 | |
af929c62 | 7214 | rtx op0, op1, tem, insn; |
32131a9c | 7215 | int code; |
a8fdc208 | 7216 | |
af929c62 RK |
7217 | op0 = find_replacement (&XEXP (in, 0)); |
7218 | op1 = find_replacement (&XEXP (in, 1)); | |
7219 | ||
32131a9c RK |
7220 | /* Since constraint checking is strict, commutativity won't be |
7221 | checked, so we need to do that here to avoid spurious failure | |
7222 | if the add instruction is two-address and the second operand | |
7223 | of the add is the same as the reload reg, which is frequently | |
7224 | the case. If the insn would be A = B + A, rearrange it so | |
0f41302f | 7225 | it will be A = A + B as constrain_operands expects. */ |
a8fdc208 | 7226 | |
32131a9c | 7227 | if (GET_CODE (XEXP (in, 1)) == REG |
5e03c156 | 7228 | && REGNO (out) == REGNO (XEXP (in, 1))) |
af929c62 RK |
7229 | tem = op0, op0 = op1, op1 = tem; |
7230 | ||
7231 | if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) | |
38a448ca | 7232 | in = gen_rtx_PLUS (GET_MODE (in), op0, op1); |
32131a9c | 7233 | |
38a448ca | 7234 | insn = emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
32131a9c RK |
7235 | code = recog_memoized (insn); |
7236 | ||
7237 | if (code >= 0) | |
7238 | { | |
0eadeb15 | 7239 | extract_insn (insn); |
32131a9c RK |
7240 | /* We want constrain operands to treat this insn strictly in |
7241 | its validity determination, i.e., the way it would after reload | |
7242 | has completed. */ | |
0eadeb15 | 7243 | if (constrain_operands (1)) |
32131a9c RK |
7244 | return insn; |
7245 | } | |
7246 | ||
546b63fb | 7247 | delete_insns_since (last); |
32131a9c RK |
7248 | |
7249 | /* If that failed, we must use a conservative two-insn sequence. | |
09522f21 FS |
7250 | |
7251 | Use a move to copy one operand into the reload register. Prefer | |
7252 | to reload a constant, MEM or pseudo since the move patterns can | |
7253 | handle an arbitrary operand. If OP1 is not a constant, MEM or | |
7254 | pseudo and OP1 is not a valid operand for an add instruction, then | |
7255 | reload OP1. | |
7256 | ||
7257 | After reloading one of the operands into the reload register, add | |
7258 | the reload register to the output register. | |
32131a9c RK |
7259 | |
7260 | If there is another way to do this for a specific machine, a | |
7261 | DEFINE_PEEPHOLE should be specified that recognizes the sequence | |
7262 | we emit below. */ | |
7263 | ||
09522f21 FS |
7264 | code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code; |
7265 | ||
5c6b1bd2 | 7266 | if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG |
af929c62 | 7267 | || (GET_CODE (op1) == REG |
09522f21 FS |
7268 | && REGNO (op1) >= FIRST_PSEUDO_REGISTER) |
7269 | || (code != CODE_FOR_nothing | |
a995e389 RH |
7270 | && ! ((*insn_data[code].operand[2].predicate) |
7271 | (op1, insn_data[code].operand[2].mode)))) | |
af929c62 | 7272 | tem = op0, op0 = op1, op1 = tem; |
32131a9c | 7273 | |
5c6b1bd2 | 7274 | gen_reload (out, op0, opnum, type); |
39b56c2a | 7275 | |
5e03c156 | 7276 | /* If OP0 and OP1 are the same, we can use OUT for OP1. |
39b56c2a RK |
7277 | This fixes a problem on the 32K where the stack pointer cannot |
7278 | be used as an operand of an add insn. */ | |
7279 | ||
7280 | if (rtx_equal_p (op0, op1)) | |
5e03c156 | 7281 | op1 = out; |
39b56c2a | 7282 | |
5e03c156 | 7283 | insn = emit_insn (gen_add2_insn (out, op1)); |
c77c9766 RK |
7284 | |
7285 | /* If that failed, copy the address register to the reload register. | |
0f41302f | 7286 | Then add the constant to the reload register. */ |
c77c9766 RK |
7287 | |
7288 | code = recog_memoized (insn); | |
7289 | ||
7290 | if (code >= 0) | |
7291 | { | |
0eadeb15 | 7292 | extract_insn (insn); |
c77c9766 RK |
7293 | /* We want constrain operands to treat this insn strictly in |
7294 | its validity determination, i.e., the way it would after reload | |
7295 | has completed. */ | |
0eadeb15 | 7296 | if (constrain_operands (1)) |
4117a96b R |
7297 | { |
7298 | /* Add a REG_EQUIV note so that find_equiv_reg can find it. */ | |
7299 | REG_NOTES (insn) | |
9e6a5703 | 7300 | = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); |
4117a96b R |
7301 | return insn; |
7302 | } | |
c77c9766 RK |
7303 | } |
7304 | ||
7305 | delete_insns_since (last); | |
7306 | ||
5c6b1bd2 | 7307 | gen_reload (out, op1, opnum, type); |
4117a96b | 7308 | insn = emit_insn (gen_add2_insn (out, op0)); |
9e6a5703 | 7309 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); |
32131a9c RK |
7310 | } |
7311 | ||
0dadecf6 RK |
7312 | #ifdef SECONDARY_MEMORY_NEEDED |
7313 | /* If we need a memory location to do the move, do it that way. */ | |
7314 | else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER | |
5e03c156 | 7315 | && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER |
0dadecf6 | 7316 | && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), |
5e03c156 RK |
7317 | REGNO_REG_CLASS (REGNO (out)), |
7318 | GET_MODE (out))) | |
0dadecf6 RK |
7319 | { |
7320 | /* Get the memory to use and rewrite both registers to its mode. */ | |
5e03c156 | 7321 | rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type); |
0dadecf6 | 7322 | |
5e03c156 | 7323 | if (GET_MODE (loc) != GET_MODE (out)) |
38a448ca | 7324 | out = gen_rtx_REG (GET_MODE (loc), REGNO (out)); |
0dadecf6 RK |
7325 | |
7326 | if (GET_MODE (loc) != GET_MODE (in)) | |
38a448ca | 7327 | in = gen_rtx_REG (GET_MODE (loc), REGNO (in)); |
0dadecf6 | 7328 | |
5c6b1bd2 RK |
7329 | gen_reload (loc, in, opnum, type); |
7330 | gen_reload (out, loc, opnum, type); | |
0dadecf6 RK |
7331 | } |
7332 | #endif | |
7333 | ||
32131a9c RK |
7334 | /* If IN is a simple operand, use gen_move_insn. */ |
7335 | else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG) | |
5e03c156 | 7336 | emit_insn (gen_move_insn (out, in)); |
32131a9c RK |
7337 | |
7338 | #ifdef HAVE_reload_load_address | |
7339 | else if (HAVE_reload_load_address) | |
5e03c156 | 7340 | emit_insn (gen_reload_load_address (out, in)); |
32131a9c RK |
7341 | #endif |
7342 | ||
5e03c156 | 7343 | /* Otherwise, just write (set OUT IN) and hope for the best. */ |
32131a9c | 7344 | else |
38a448ca | 7345 | emit_insn (gen_rtx_SET (VOIDmode, out, in)); |
32131a9c RK |
7346 | |
7347 | /* Return the first insn emitted. | |
546b63fb | 7348 | We can not just return get_last_insn, because there may have |
32131a9c RK |
7349 | been multiple instructions emitted. Also note that gen_move_insn may |
7350 | emit more than one insn itself, so we can not assume that there is one | |
7351 | insn emitted per emit_insn_before call. */ | |
7352 | ||
546b63fb | 7353 | return last ? NEXT_INSN (last) : get_insns (); |
32131a9c RK |
7354 | } |
7355 | \f | |
7356 | /* Delete a previously made output-reload | |
7357 | whose result we now believe is not needed. | |
7358 | First we double-check. | |
7359 | ||
7360 | INSN is the insn now being processed. | |
cb2afeb3 R |
7361 | LAST_RELOAD_REG is the hard register number for which we want to delete |
7362 | the last output reload. | |
7363 | J is the reload-number that originally used REG. The caller has made | |
7364 | certain that reload J doesn't use REG any longer for input. */ | |
32131a9c RK |
7365 | |
7366 | static void | |
cb2afeb3 | 7367 | delete_output_reload (insn, j, last_reload_reg) |
32131a9c RK |
7368 | rtx insn; |
7369 | int j; | |
cb2afeb3 | 7370 | int last_reload_reg; |
32131a9c | 7371 | { |
cb2afeb3 R |
7372 | rtx output_reload_insn = spill_reg_store[last_reload_reg]; |
7373 | rtx reg = spill_reg_stored_to[last_reload_reg]; | |
7374 | int k; | |
7375 | int n_occurrences; | |
7376 | int n_inherited = 0; | |
32131a9c | 7377 | register rtx i1; |
cb2afeb3 | 7378 | rtx substed; |
05d10675 | 7379 | |
32131a9c RK |
7380 | /* Get the raw pseudo-register referred to. */ |
7381 | ||
32131a9c RK |
7382 | while (GET_CODE (reg) == SUBREG) |
7383 | reg = SUBREG_REG (reg); | |
cb2afeb3 R |
7384 | substed = reg_equiv_memory_loc[REGNO (reg)]; |
7385 | ||
7386 | /* This is unsafe if the operand occurs more often in the current | |
7387 | insn than it is inherited. */ | |
7388 | for (k = n_reloads - 1; k >= 0; k--) | |
7389 | { | |
eceef4c9 | 7390 | rtx reg2 = rld[k].in; |
cb2afeb3 R |
7391 | if (! reg2) |
7392 | continue; | |
7393 | if (GET_CODE (reg2) == MEM || reload_override_in[k]) | |
eceef4c9 | 7394 | reg2 = rld[k].in_reg; |
cb2afeb3 | 7395 | #ifdef AUTO_INC_DEC |
eceef4c9 BS |
7396 | if (rld[k].out && ! rld[k].out_reg) |
7397 | reg2 = XEXP (rld[k].in_reg, 0); | |
cb2afeb3 R |
7398 | #endif |
7399 | while (GET_CODE (reg2) == SUBREG) | |
7400 | reg2 = SUBREG_REG (reg2); | |
7401 | if (rtx_equal_p (reg2, reg)) | |
2eb6dac7 AS |
7402 | { |
7403 | if (reload_inherited[k] || reload_override_in[k] || k == j) | |
7404 | { | |
cb2afeb3 | 7405 | n_inherited++; |
eceef4c9 | 7406 | reg2 = rld[k].out_reg; |
2eb6dac7 AS |
7407 | if (! reg2) |
7408 | continue; | |
7409 | while (GET_CODE (reg2) == SUBREG) | |
7410 | reg2 = XEXP (reg2, 0); | |
7411 | if (rtx_equal_p (reg2, reg)) | |
7412 | n_inherited++; | |
7413 | } | |
7414 | else | |
7415 | return; | |
7416 | } | |
cb2afeb3 R |
7417 | } |
7418 | n_occurrences = count_occurrences (PATTERN (insn), reg); | |
7419 | if (substed) | |
7420 | n_occurrences += count_occurrences (PATTERN (insn), substed); | |
7421 | if (n_occurrences > n_inherited) | |
7422 | return; | |
32131a9c RK |
7423 | |
7424 | /* If the pseudo-reg we are reloading is no longer referenced | |
7425 | anywhere between the store into it and here, | |
7426 | and no jumps or labels intervene, then the value can get | |
7427 | here through the reload reg alone. | |
7428 | Otherwise, give up--return. */ | |
7429 | for (i1 = NEXT_INSN (output_reload_insn); | |
7430 | i1 != insn; i1 = NEXT_INSN (i1)) | |
7431 | { | |
7432 | if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN) | |
7433 | return; | |
7434 | if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN) | |
7435 | && reg_mentioned_p (reg, PATTERN (i1))) | |
aa6498c2 | 7436 | { |
cb2afeb3 R |
7437 | /* If this is USE in front of INSN, we only have to check that |
7438 | there are no more references than accounted for by inheritance. */ | |
7439 | while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE) | |
aa6498c2 | 7440 | { |
cb2afeb3 | 7441 | n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0; |
aa6498c2 R |
7442 | i1 = NEXT_INSN (i1); |
7443 | } | |
cb2afeb3 | 7444 | if (n_occurrences <= n_inherited && i1 == insn) |
aa6498c2 R |
7445 | break; |
7446 | return; | |
7447 | } | |
32131a9c RK |
7448 | } |
7449 | ||
aa6498c2 R |
7450 | /* The caller has already checked that REG dies or is set in INSN. |
7451 | It has also checked that we are optimizing, and thus some inaccurancies | |
7452 | in the debugging information are acceptable. | |
7453 | So we could just delete output_reload_insn. | |
7454 | But in some cases we can improve the debugging information without | |
7455 | sacrificing optimization - maybe even improving the code: | |
7456 | See if the pseudo reg has been completely replaced | |
32131a9c RK |
7457 | with reload regs. If so, delete the store insn |
7458 | and forget we had a stack slot for the pseudo. */ | |
eceef4c9 | 7459 | if (rld[j].out != rld[j].in |
aa6498c2 | 7460 | && REG_N_DEATHS (REGNO (reg)) == 1 |
a3a24aa6 | 7461 | && REG_N_SETS (REGNO (reg)) == 1 |
aa6498c2 R |
7462 | && REG_BASIC_BLOCK (REGNO (reg)) >= 0 |
7463 | && find_regno_note (insn, REG_DEAD, REGNO (reg))) | |
32131a9c RK |
7464 | { |
7465 | rtx i2; | |
7466 | ||
7467 | /* We know that it was used only between here | |
7468 | and the beginning of the current basic block. | |
7469 | (We also know that the last use before INSN was | |
7470 | the output reload we are thinking of deleting, but never mind that.) | |
7471 | Search that range; see if any ref remains. */ | |
7472 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) | |
7473 | { | |
d445b551 RK |
7474 | rtx set = single_set (i2); |
7475 | ||
32131a9c RK |
7476 | /* Uses which just store in the pseudo don't count, |
7477 | since if they are the only uses, they are dead. */ | |
d445b551 | 7478 | if (set != 0 && SET_DEST (set) == reg) |
32131a9c RK |
7479 | continue; |
7480 | if (GET_CODE (i2) == CODE_LABEL | |
7481 | || GET_CODE (i2) == JUMP_INSN) | |
7482 | break; | |
7483 | if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN) | |
7484 | && reg_mentioned_p (reg, PATTERN (i2))) | |
aa6498c2 R |
7485 | { |
7486 | /* Some other ref remains; just delete the output reload we | |
7487 | know to be dead. */ | |
cb2afeb3 R |
7488 | delete_address_reloads (output_reload_insn, insn); |
7489 | PUT_CODE (output_reload_insn, NOTE); | |
7490 | NOTE_SOURCE_FILE (output_reload_insn) = 0; | |
7491 | NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED; | |
aa6498c2 R |
7492 | return; |
7493 | } | |
32131a9c RK |
7494 | } |
7495 | ||
7496 | /* Delete the now-dead stores into this pseudo. */ | |
7497 | for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) | |
7498 | { | |
d445b551 RK |
7499 | rtx set = single_set (i2); |
7500 | ||
7501 | if (set != 0 && SET_DEST (set) == reg) | |
5507b94b | 7502 | { |
cb2afeb3 | 7503 | delete_address_reloads (i2, insn); |
5507b94b RK |
7504 | /* This might be a basic block head, |
7505 | thus don't use delete_insn. */ | |
7506 | PUT_CODE (i2, NOTE); | |
7507 | NOTE_SOURCE_FILE (i2) = 0; | |
7508 | NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED; | |
7509 | } | |
32131a9c RK |
7510 | if (GET_CODE (i2) == CODE_LABEL |
7511 | || GET_CODE (i2) == JUMP_INSN) | |
7512 | break; | |
7513 | } | |
7514 | ||
7515 | /* For the debugging info, | |
7516 | say the pseudo lives in this reload reg. */ | |
eceef4c9 | 7517 | reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx); |
32131a9c RK |
7518 | alter_reg (REGNO (reg), -1); |
7519 | } | |
cb2afeb3 R |
7520 | delete_address_reloads (output_reload_insn, insn); |
7521 | PUT_CODE (output_reload_insn, NOTE); | |
7522 | NOTE_SOURCE_FILE (output_reload_insn) = 0; | |
7523 | NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED; | |
7524 | ||
7525 | } | |
7526 | ||
7527 | /* We are going to delete DEAD_INSN. Recursively delete loads of | |
7528 | reload registers used in DEAD_INSN that are not used till CURRENT_INSN. | |
7529 | CURRENT_INSN is being reloaded, so we have to check its reloads too. */ | |
7530 | static void | |
7531 | delete_address_reloads (dead_insn, current_insn) | |
7532 | rtx dead_insn, current_insn; | |
7533 | { | |
7534 | rtx set = single_set (dead_insn); | |
7535 | rtx set2, dst, prev, next; | |
7536 | if (set) | |
7537 | { | |
7538 | rtx dst = SET_DEST (set); | |
7539 | if (GET_CODE (dst) == MEM) | |
7540 | delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn); | |
7541 | } | |
7542 | /* If we deleted the store from a reloaded post_{in,de}c expression, | |
7543 | we can delete the matching adds. */ | |
7544 | prev = PREV_INSN (dead_insn); | |
7545 | next = NEXT_INSN (dead_insn); | |
7546 | if (! prev || ! next) | |
7547 | return; | |
7548 | set = single_set (next); | |
7549 | set2 = single_set (prev); | |
7550 | if (! set || ! set2 | |
7551 | || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS | |
7552 | || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT | |
7553 | || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT) | |
7554 | return; | |
7555 | dst = SET_DEST (set); | |
7556 | if (! rtx_equal_p (dst, SET_DEST (set2)) | |
7557 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0)) | |
7558 | || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0)) | |
7559 | || (INTVAL (XEXP (SET_SRC (set), 1)) | |
7560 | != - INTVAL (XEXP (SET_SRC (set2), 1)))) | |
7561 | return; | |
7562 | delete_insn (prev); | |
7563 | delete_insn (next); | |
7564 | } | |
7565 | ||
7566 | /* Subfunction of delete_address_reloads: process registers found in X. */ | |
7567 | static void | |
7568 | delete_address_reloads_1 (dead_insn, x, current_insn) | |
7569 | rtx dead_insn, x, current_insn; | |
7570 | { | |
7571 | rtx prev, set, dst, i2; | |
7572 | int i, j; | |
7573 | enum rtx_code code = GET_CODE (x); | |
7574 | ||
7575 | if (code != REG) | |
7576 | { | |
6f7d635c | 7577 | const char *fmt= GET_RTX_FORMAT (code); |
cb2afeb3 R |
7578 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
7579 | { | |
7580 | if (fmt[i] == 'e') | |
7581 | delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn); | |
7582 | else if (fmt[i] == 'E') | |
7583 | { | |
7584 | for (j = XVECLEN (x, i) - 1; j >=0; j--) | |
7585 | delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j), | |
7586 | current_insn); | |
7587 | } | |
7588 | } | |
7589 | return; | |
7590 | } | |
7591 | ||
7592 | if (spill_reg_order[REGNO (x)] < 0) | |
7593 | return; | |
aa6498c2 | 7594 | |
cb2afeb3 R |
7595 | /* Scan backwards for the insn that sets x. This might be a way back due |
7596 | to inheritance. */ | |
7597 | for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev)) | |
7598 | { | |
7599 | code = GET_CODE (prev); | |
7600 | if (code == CODE_LABEL || code == JUMP_INSN) | |
7601 | return; | |
7602 | if (GET_RTX_CLASS (code) != 'i') | |
7603 | continue; | |
7604 | if (reg_set_p (x, PATTERN (prev))) | |
7605 | break; | |
7606 | if (reg_referenced_p (x, PATTERN (prev))) | |
7607 | return; | |
7608 | } | |
7609 | if (! prev || INSN_UID (prev) < reload_first_uid) | |
7610 | return; | |
7611 | /* Check that PREV only sets the reload register. */ | |
7612 | set = single_set (prev); | |
7613 | if (! set) | |
7614 | return; | |
7615 | dst = SET_DEST (set); | |
7616 | if (GET_CODE (dst) != REG | |
7617 | || ! rtx_equal_p (dst, x)) | |
7618 | return; | |
7619 | if (! reg_set_p (dst, PATTERN (dead_insn))) | |
7620 | { | |
7621 | /* Check if DST was used in a later insn - | |
7622 | it might have been inherited. */ | |
7623 | for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2)) | |
7624 | { | |
7625 | if (GET_CODE (i2) == CODE_LABEL) | |
7626 | break; | |
7627 | if (GET_RTX_CLASS (GET_CODE (i2)) != 'i') | |
7628 | continue; | |
7629 | if (reg_referenced_p (dst, PATTERN (i2))) | |
7630 | { | |
7631 | /* If there is a reference to the register in the current insn, | |
7632 | it might be loaded in a non-inherited reload. If no other | |
7633 | reload uses it, that means the register is set before | |
7634 | referenced. */ | |
7635 | if (i2 == current_insn) | |
7636 | { | |
7637 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7638 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
7639 | || reload_override_in[j] == dst) |
7640 | return; | |
7641 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7642 | if (rld[j].in && rld[j].reg_rtx == dst) |
cb2afeb3 R |
7643 | break; |
7644 | if (j >= 0) | |
7645 | break; | |
7646 | } | |
7647 | return; | |
7648 | } | |
7649 | if (GET_CODE (i2) == JUMP_INSN) | |
7650 | break; | |
cb2afeb3 | 7651 | /* If DST is still live at CURRENT_INSN, check if it is used for |
3900dc09 R |
7652 | any reload. Note that even if CURRENT_INSN sets DST, we still |
7653 | have to check the reloads. */ | |
cb2afeb3 R |
7654 | if (i2 == current_insn) |
7655 | { | |
7656 | for (j = n_reloads - 1; j >= 0; j--) | |
eceef4c9 | 7657 | if ((rld[j].reg_rtx == dst && reload_inherited[j]) |
cb2afeb3 R |
7658 | || reload_override_in[j] == dst) |
7659 | return; | |
7660 | /* ??? We can't finish the loop here, because dst might be | |
7661 | allocated to a pseudo in this block if no reload in this | |
7662 | block needs any of the clsses containing DST - see | |
7663 | spill_hard_reg. There is no easy way to tell this, so we | |
7664 | have to scan till the end of the basic block. */ | |
7665 | } | |
3900dc09 R |
7666 | if (reg_set_p (dst, PATTERN (i2))) |
7667 | break; | |
cb2afeb3 R |
7668 | } |
7669 | } | |
7670 | delete_address_reloads_1 (prev, SET_SRC (set), current_insn); | |
7671 | reg_reloaded_contents[REGNO (dst)] = -1; | |
7672 | /* Can't use delete_insn here because PREV might be a basic block head. */ | |
7673 | PUT_CODE (prev, NOTE); | |
7674 | NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED; | |
7675 | NOTE_SOURCE_FILE (prev) = 0; | |
32131a9c | 7676 | } |
32131a9c | 7677 | \f |
a8fdc208 | 7678 | /* Output reload-insns to reload VALUE into RELOADREG. |
858a47b1 | 7679 | VALUE is an autoincrement or autodecrement RTX whose operand |
32131a9c RK |
7680 | is a register or memory location; |
7681 | so reloading involves incrementing that location. | |
cb2afeb3 | 7682 | IN is either identical to VALUE, or some cheaper place to reload from. |
32131a9c RK |
7683 | |
7684 | INC_AMOUNT is the number to increment or decrement by (always positive). | |
cb2afeb3 | 7685 | This cannot be deduced from VALUE. |
32131a9c | 7686 | |
cb2afeb3 R |
7687 | Return the instruction that stores into RELOADREG. */ |
7688 | ||
7689 | static rtx | |
7690 | inc_for_reload (reloadreg, in, value, inc_amount) | |
32131a9c | 7691 | rtx reloadreg; |
cb2afeb3 | 7692 | rtx in, value; |
32131a9c | 7693 | int inc_amount; |
32131a9c RK |
7694 | { |
7695 | /* REG or MEM to be copied and incremented. */ | |
7696 | rtx incloc = XEXP (value, 0); | |
7697 | /* Nonzero if increment after copying. */ | |
7698 | int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC); | |
546b63fb | 7699 | rtx last; |
0009eff2 RK |
7700 | rtx inc; |
7701 | rtx add_insn; | |
7702 | int code; | |
cb2afeb3 R |
7703 | rtx store; |
7704 | rtx real_in = in == value ? XEXP (in, 0) : in; | |
32131a9c RK |
7705 | |
7706 | /* No hard register is equivalent to this register after | |
7707 | inc/dec operation. If REG_LAST_RELOAD_REG were non-zero, | |
7708 | we could inc/dec that register as well (maybe even using it for | |
7709 | the source), but I'm not sure it's worth worrying about. */ | |
7710 | if (GET_CODE (incloc) == REG) | |
7711 | reg_last_reload_reg[REGNO (incloc)] = 0; | |
7712 | ||
7713 | if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) | |
7714 | inc_amount = - inc_amount; | |
7715 | ||
fb3821f7 | 7716 | inc = GEN_INT (inc_amount); |
0009eff2 RK |
7717 | |
7718 | /* If this is post-increment, first copy the location to the reload reg. */ | |
cb2afeb3 R |
7719 | if (post && real_in != reloadreg) |
7720 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
0009eff2 | 7721 | |
cb2afeb3 R |
7722 | if (in == value) |
7723 | { | |
7724 | /* See if we can directly increment INCLOC. Use a method similar to | |
7725 | that in gen_reload. */ | |
0009eff2 | 7726 | |
cb2afeb3 R |
7727 | last = get_last_insn (); |
7728 | add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc, | |
7729 | gen_rtx_PLUS (GET_MODE (incloc), | |
7730 | incloc, inc))); | |
05d10675 | 7731 | |
cb2afeb3 R |
7732 | code = recog_memoized (add_insn); |
7733 | if (code >= 0) | |
32131a9c | 7734 | { |
0eadeb15 BS |
7735 | extract_insn (add_insn); |
7736 | if (constrain_operands (1)) | |
cb2afeb3 R |
7737 | { |
7738 | /* If this is a pre-increment and we have incremented the value | |
7739 | where it lives, copy the incremented value to RELOADREG to | |
7740 | be used as an address. */ | |
0009eff2 | 7741 | |
cb2afeb3 R |
7742 | if (! post) |
7743 | emit_insn (gen_move_insn (reloadreg, incloc)); | |
546b63fb | 7744 | |
cb2afeb3 R |
7745 | return add_insn; |
7746 | } | |
32131a9c | 7747 | } |
cb2afeb3 | 7748 | delete_insns_since (last); |
32131a9c | 7749 | } |
0009eff2 | 7750 | |
0009eff2 RK |
7751 | /* If couldn't do the increment directly, must increment in RELOADREG. |
7752 | The way we do this depends on whether this is pre- or post-increment. | |
7753 | For pre-increment, copy INCLOC to the reload register, increment it | |
7754 | there, then save back. */ | |
7755 | ||
7756 | if (! post) | |
7757 | { | |
cb2afeb3 R |
7758 | if (in != reloadreg) |
7759 | emit_insn (gen_move_insn (reloadreg, real_in)); | |
546b63fb | 7760 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 7761 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
0009eff2 | 7762 | } |
32131a9c RK |
7763 | else |
7764 | { | |
0009eff2 RK |
7765 | /* Postincrement. |
7766 | Because this might be a jump insn or a compare, and because RELOADREG | |
7767 | may not be available after the insn in an input reload, we must do | |
7768 | the incrementation before the insn being reloaded for. | |
7769 | ||
cb2afeb3 | 7770 | We have already copied IN to RELOADREG. Increment the copy in |
0009eff2 RK |
7771 | RELOADREG, save that back, then decrement RELOADREG so it has |
7772 | the original value. */ | |
7773 | ||
546b63fb | 7774 | emit_insn (gen_add2_insn (reloadreg, inc)); |
cb2afeb3 | 7775 | store = emit_insn (gen_move_insn (incloc, reloadreg)); |
546b63fb | 7776 | emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount))); |
32131a9c | 7777 | } |
0009eff2 | 7778 | |
cb2afeb3 | 7779 | return store; |
32131a9c RK |
7780 | } |
7781 | \f | |
7782 | /* Return 1 if we are certain that the constraint-string STRING allows | |
7783 | the hard register REG. Return 0 if we can't be sure of this. */ | |
7784 | ||
7785 | static int | |
7786 | constraint_accepts_reg_p (string, reg) | |
9b3142b3 | 7787 | const char *string; |
32131a9c RK |
7788 | rtx reg; |
7789 | { | |
7790 | int value = 0; | |
7791 | int regno = true_regnum (reg); | |
7792 | int c; | |
7793 | ||
7794 | /* Initialize for first alternative. */ | |
7795 | value = 0; | |
7796 | /* Check that each alternative contains `g' or `r'. */ | |
7797 | while (1) | |
7798 | switch (c = *string++) | |
7799 | { | |
7800 | case 0: | |
7801 | /* If an alternative lacks `g' or `r', we lose. */ | |
7802 | return value; | |
7803 | case ',': | |
7804 | /* If an alternative lacks `g' or `r', we lose. */ | |
7805 | if (value == 0) | |
7806 | return 0; | |
7807 | /* Initialize for next alternative. */ | |
7808 | value = 0; | |
7809 | break; | |
7810 | case 'g': | |
7811 | case 'r': | |
7812 | /* Any general reg wins for this alternative. */ | |
7813 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno)) | |
7814 | value = 1; | |
7815 | break; | |
7816 | default: | |
7817 | /* Any reg in specified class wins for this alternative. */ | |
7818 | { | |
0009eff2 | 7819 | enum reg_class class = REG_CLASS_FROM_LETTER (c); |
32131a9c | 7820 | |
0009eff2 | 7821 | if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)) |
32131a9c RK |
7822 | value = 1; |
7823 | } | |
7824 | } | |
7825 | } | |
7826 | \f | |
d445b551 RK |
7827 | /* Return the number of places FIND appears within X, but don't count |
7828 | an occurrence if some SET_DEST is FIND. */ | |
32131a9c | 7829 | |
184bb750 | 7830 | int |
32131a9c RK |
7831 | count_occurrences (x, find) |
7832 | register rtx x, find; | |
7833 | { | |
7834 | register int i, j; | |
7835 | register enum rtx_code code; | |
6f7d635c | 7836 | register const char *format_ptr; |
32131a9c RK |
7837 | int count; |
7838 | ||
7839 | if (x == find) | |
7840 | return 1; | |
7841 | if (x == 0) | |
7842 | return 0; | |
7843 | ||
7844 | code = GET_CODE (x); | |
7845 | ||
7846 | switch (code) | |
7847 | { | |
7848 | case REG: | |
7849 | case QUEUED: | |
7850 | case CONST_INT: | |
7851 | case CONST_DOUBLE: | |
7852 | case SYMBOL_REF: | |
7853 | case CODE_LABEL: | |
7854 | case PC: | |
7855 | case CC0: | |
7856 | return 0; | |
d445b551 | 7857 | |
cb2afeb3 R |
7858 | case MEM: |
7859 | if (GET_CODE (find) == MEM && rtx_equal_p (x, find)) | |
7860 | return 1; | |
7861 | break; | |
d445b551 RK |
7862 | case SET: |
7863 | if (SET_DEST (x) == find) | |
7864 | return count_occurrences (SET_SRC (x), find); | |
7865 | break; | |
05d10675 | 7866 | |
e9a25f70 JL |
7867 | default: |
7868 | break; | |
32131a9c RK |
7869 | } |
7870 | ||
7871 | format_ptr = GET_RTX_FORMAT (code); | |
7872 | count = 0; | |
7873 | ||
7874 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
7875 | { | |
7876 | switch (*format_ptr++) | |
7877 | { | |
7878 | case 'e': | |
7879 | count += count_occurrences (XEXP (x, i), find); | |
7880 | break; | |
7881 | ||
7882 | case 'E': | |
7883 | if (XVEC (x, i) != NULL) | |
7884 | { | |
7885 | for (j = 0; j < XVECLEN (x, i); j++) | |
7886 | count += count_occurrences (XVECEXP (x, i, j), find); | |
7887 | } | |
7888 | break; | |
7889 | } | |
7890 | } | |
7891 | return count; | |
7892 | } | |
2a9fb548 | 7893 | \f |
eab5c70a BS |
7894 | /* INSN is a no-op; delete it. |
7895 | If this sets the return value of the function, we must keep a USE around, | |
7896 | in case this is in a different basic block than the final USE. Otherwise, | |
7897 | we could loose important register lifeness information on | |
7898 | SMALL_REGISTER_CLASSES machines, where return registers might be used as | |
7899 | spills: subsequent passes assume that spill registers are dead at the end | |
7900 | of a basic block. | |
7901 | VALUE must be the return value in such a case, NULL otherwise. */ | |
2a9fb548 | 7902 | static void |
eab5c70a BS |
7903 | reload_cse_delete_noop_set (insn, value) |
7904 | rtx insn, value; | |
2a9fb548 | 7905 | { |
eab5c70a | 7906 | if (value) |
2a9fb548 | 7907 | { |
eab5c70a BS |
7908 | PATTERN (insn) = gen_rtx_USE (VOIDmode, value); |
7909 | INSN_CODE (insn) = -1; | |
7910 | REG_NOTES (insn) = NULL_RTX; | |
2a9fb548 | 7911 | } |
eab5c70a | 7912 | else |
ba325eba | 7913 | { |
eab5c70a BS |
7914 | PUT_CODE (insn, NOTE); |
7915 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
7916 | NOTE_SOURCE_FILE (insn) = 0; | |
ba325eba | 7917 | } |
2a9fb548 ILT |
7918 | } |
7919 | ||
eab5c70a | 7920 | /* See whether a single set SET is a noop. */ |
2a9fb548 | 7921 | static int |
eab5c70a BS |
7922 | reload_cse_noop_set_p (set) |
7923 | rtx set; | |
2a9fb548 | 7924 | { |
eab5c70a BS |
7925 | return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set)); |
7926 | } | |
2a9fb548 | 7927 | |
eab5c70a BS |
7928 | /* Try to simplify INSN. */ |
7929 | static void | |
7930 | reload_cse_simplify (insn) | |
7931 | rtx insn; | |
7932 | { | |
7933 | rtx body = PATTERN (insn); | |
2a9fb548 | 7934 | |
eab5c70a | 7935 | if (GET_CODE (body) == SET) |
2a9fb548 | 7936 | { |
eab5c70a BS |
7937 | int count = 0; |
7938 | if (reload_cse_noop_set_p (body)) | |
2a9fb548 | 7939 | { |
eab5c70a BS |
7940 | rtx value = SET_DEST (body); |
7941 | if (! REG_FUNCTION_VALUE_P (SET_DEST (body))) | |
7942 | value = 0; | |
7943 | reload_cse_delete_noop_set (insn, value); | |
7944 | return; | |
2a9fb548 | 7945 | } |
2a9fb548 | 7946 | |
eab5c70a BS |
7947 | /* It's not a no-op, but we can try to simplify it. */ |
7948 | count += reload_cse_simplify_set (body, insn); | |
2a9fb548 | 7949 | |
eab5c70a BS |
7950 | if (count > 0) |
7951 | apply_change_group (); | |
7952 | else | |
7953 | reload_cse_simplify_operands (insn); | |
7954 | } | |
7955 | else if (GET_CODE (body) == PARALLEL) | |
2a9fb548 | 7956 | { |
eab5c70a BS |
7957 | int i; |
7958 | int count = 0; | |
7959 | rtx value = NULL_RTX; | |
2a9fb548 | 7960 | |
eab5c70a BS |
7961 | /* If every action in a PARALLEL is a noop, we can delete |
7962 | the entire PARALLEL. */ | |
7963 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
2a9fb548 | 7964 | { |
eab5c70a BS |
7965 | rtx part = XVECEXP (body, 0, i); |
7966 | if (GET_CODE (part) == SET) | |
2a9fb548 | 7967 | { |
eab5c70a BS |
7968 | if (! reload_cse_noop_set_p (part)) |
7969 | break; | |
7970 | if (REG_FUNCTION_VALUE_P (SET_DEST (part))) | |
2a9fb548 | 7971 | { |
eab5c70a BS |
7972 | if (value) |
7973 | break; | |
7974 | value = SET_DEST (part); | |
2a9fb548 | 7975 | } |
2a9fb548 | 7976 | } |
eab5c70a BS |
7977 | else if (GET_CODE (part) != CLOBBER) |
7978 | break; | |
2a9fb548 | 7979 | } |
2a9fb548 | 7980 | |
eab5c70a BS |
7981 | if (i < 0) |
7982 | { | |
7983 | reload_cse_delete_noop_set (insn, value); | |
7984 | /* We're done with this insn. */ | |
7985 | return; | |
7986 | } | |
2a9fb548 | 7987 | |
eab5c70a BS |
7988 | /* It's not a no-op, but we can try to simplify it. */ |
7989 | for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
7990 | if (GET_CODE (XVECEXP (body, 0, i)) == SET) | |
7991 | count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn); | |
7992 | ||
7993 | if (count > 0) | |
7994 | apply_change_group (); | |
7995 | else | |
7996 | reload_cse_simplify_operands (insn); | |
7997 | } | |
2a9fb548 ILT |
7998 | } |
7999 | ||
8000 | /* Do a very simple CSE pass over the hard registers. | |
8001 | ||
8002 | This function detects no-op moves where we happened to assign two | |
8003 | different pseudo-registers to the same hard register, and then | |
8004 | copied one to the other. Reload will generate a useless | |
8005 | instruction copying a register to itself. | |
8006 | ||
8007 | This function also detects cases where we load a value from memory | |
8008 | into two different registers, and (if memory is more expensive than | |
8009 | registers) changes it to simply copy the first register into the | |
05d10675 | 8010 | second register. |
e9a25f70 JL |
8011 | |
8012 | Another optimization is performed that scans the operands of each | |
8013 | instruction to see whether the value is already available in a | |
8014 | hard register. It then replaces the operand with the hard register | |
8015 | if possible, much like an optional reload would. */ | |
2a9fb548 | 8016 | |
5adf6da0 R |
8017 | static void |
8018 | reload_cse_regs_1 (first) | |
2a9fb548 ILT |
8019 | rtx first; |
8020 | { | |
2a9fb548 ILT |
8021 | rtx insn; |
8022 | ||
eab5c70a | 8023 | cselib_init (); |
cbfc3ad3 RK |
8024 | init_alias_analysis (); |
8025 | ||
2a9fb548 ILT |
8026 | for (insn = first; insn; insn = NEXT_INSN (insn)) |
8027 | { | |
eab5c70a BS |
8028 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') |
8029 | reload_cse_simplify (insn); | |
2a9fb548 | 8030 | |
eab5c70a | 8031 | cselib_process_insn (insn); |
2a9fb548 ILT |
8032 | } |
8033 | ||
e05e2395 MM |
8034 | /* Clean up. */ |
8035 | end_alias_analysis (); | |
eab5c70a | 8036 | cselib_finish (); |
2a9fb548 ILT |
8037 | } |
8038 | ||
5adf6da0 R |
8039 | /* Call cse / combine like post-reload optimization phases. |
8040 | FIRST is the first instruction. */ | |
8041 | void | |
8042 | reload_cse_regs (first) | |
8043 | rtx first; | |
8044 | { | |
8045 | reload_cse_regs_1 (first); | |
8046 | reload_combine (); | |
8047 | reload_cse_move2add (first); | |
8048 | if (flag_expensive_optimizations) | |
8049 | reload_cse_regs_1 (first); | |
8050 | } | |
8051 | ||
2a9fb548 | 8052 | /* Try to simplify a single SET instruction. SET is the set pattern. |
e9a25f70 JL |
8053 | INSN is the instruction it came from. |
8054 | This function only handles one case: if we set a register to a value | |
8055 | which is not a register, we try to find that value in some other register | |
8056 | and change the set into a register copy. */ | |
2a9fb548 | 8057 | |
e9a25f70 | 8058 | static int |
2a9fb548 ILT |
8059 | reload_cse_simplify_set (set, insn) |
8060 | rtx set; | |
8061 | rtx insn; | |
8062 | { | |
eab5c70a | 8063 | int did_change = 0; |
2a9fb548 ILT |
8064 | int dreg; |
8065 | rtx src; | |
2a9fb548 | 8066 | enum reg_class dclass; |
eab5c70a BS |
8067 | int old_cost; |
8068 | cselib_val *val; | |
8069 | struct elt_loc_list *l; | |
2a9fb548 | 8070 | |
2a9fb548 ILT |
8071 | dreg = true_regnum (SET_DEST (set)); |
8072 | if (dreg < 0) | |
e9a25f70 | 8073 | return 0; |
2a9fb548 ILT |
8074 | |
8075 | src = SET_SRC (set); | |
8076 | if (side_effects_p (src) || true_regnum (src) >= 0) | |
e9a25f70 | 8077 | return 0; |
2a9fb548 | 8078 | |
cbd5b9a2 KR |
8079 | dclass = REGNO_REG_CLASS (dreg); |
8080 | ||
33ab8de0 | 8081 | /* If memory loads are cheaper than register copies, don't change them. */ |
eab5c70a BS |
8082 | if (GET_CODE (src) == MEM) |
8083 | old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1); | |
8084 | else if (CONSTANT_P (src)) | |
8085 | old_cost = rtx_cost (src, SET); | |
8086 | else if (GET_CODE (src) == REG) | |
8087 | old_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (src)), dclass); | |
8088 | else | |
8089 | /* ??? */ | |
8090 | old_cost = rtx_cost (src, SET); | |
2a9fb548 | 8091 | |
eab5c70a BS |
8092 | val = cselib_lookup (src, VOIDmode, 0); |
8093 | if (! val) | |
0254c561 | 8094 | return 0; |
eab5c70a | 8095 | for (l = val->locs; l; l = l->next) |
2a9fb548 | 8096 | { |
eab5c70a BS |
8097 | int this_cost; |
8098 | if (CONSTANT_P (l->loc) && ! references_value_p (l->loc, 0)) | |
8099 | this_cost = rtx_cost (l->loc, SET); | |
8100 | else if (GET_CODE (l->loc) == REG) | |
8101 | this_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (l->loc)), | |
8102 | dclass); | |
8103 | else | |
8104 | continue; | |
8105 | /* If equal costs, prefer registers over anything else. That tends to | |
8106 | lead to smaller instructions on some machines. */ | |
8107 | if ((this_cost < old_cost | |
8108 | || (this_cost == old_cost | |
8109 | && GET_CODE (l->loc) == REG | |
8110 | && GET_CODE (SET_SRC (set)) != REG)) | |
8111 | && validate_change (insn, &SET_SRC (set), copy_rtx (l->loc), 1)) | |
8112 | old_cost = this_cost, did_change = 1; | |
e9a25f70 | 8113 | } |
eab5c70a BS |
8114 | |
8115 | return did_change; | |
e9a25f70 JL |
8116 | } |
8117 | ||
8118 | /* Try to replace operands in INSN with equivalent values that are already | |
05d10675 BS |
8119 | in registers. This can be viewed as optional reloading. |
8120 | ||
e9a25f70 JL |
8121 | For each non-register operand in the insn, see if any hard regs are |
8122 | known to be equivalent to that operand. Record the alternatives which | |
8123 | can accept these hard registers. Among all alternatives, select the | |
8124 | ones which are better or equal to the one currently matching, where | |
8125 | "better" is in terms of '?' and '!' constraints. Among the remaining | |
8126 | alternatives, select the one which replaces most operands with | |
8127 | hard registers. */ | |
8128 | ||
8129 | static int | |
8130 | reload_cse_simplify_operands (insn) | |
8131 | rtx insn; | |
8132 | { | |
e9a25f70 JL |
8133 | int i,j; |
8134 | ||
eab5c70a BS |
8135 | /* For each operand, all registers that are equivalent to it. */ |
8136 | HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS]; | |
8137 | ||
9b3142b3 | 8138 | const char *constraints[MAX_RECOG_OPERANDS]; |
05d10675 | 8139 | |
e9a25f70 JL |
8140 | /* Vector recording how bad an alternative is. */ |
8141 | int *alternative_reject; | |
8142 | /* Vector recording how many registers can be introduced by choosing | |
8143 | this alternative. */ | |
8144 | int *alternative_nregs; | |
8145 | /* Array of vectors recording, for each operand and each alternative, | |
8146 | which hard register to substitute, or -1 if the operand should be | |
8147 | left as it is. */ | |
8148 | int *op_alt_regno[MAX_RECOG_OPERANDS]; | |
8149 | /* Array of alternatives, sorted in order of decreasing desirability. */ | |
8150 | int *alternative_order; | |
0254c561 | 8151 | rtx reg = gen_rtx_REG (VOIDmode, -1); |
05d10675 | 8152 | |
0eadeb15 | 8153 | extract_insn (insn); |
e9a25f70 | 8154 | |
1ccbefce | 8155 | if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0) |
1d300e19 | 8156 | return 0; |
e9a25f70 JL |
8157 | |
8158 | /* Figure out which alternative currently matches. */ | |
0eadeb15 | 8159 | if (! constrain_operands (1)) |
b8705408 | 8160 | fatal_insn_not_found (insn); |
eab5c70a | 8161 | |
1ccbefce RH |
8162 | alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int)); |
8163 | alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int)); | |
8164 | alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int)); | |
8165 | bzero ((char *)alternative_reject, recog_data.n_alternatives * sizeof (int)); | |
8166 | bzero ((char *)alternative_nregs, recog_data.n_alternatives * sizeof (int)); | |
e9a25f70 | 8167 | |
eab5c70a BS |
8168 | /* For each operand, find out which regs are equivalent. */ |
8169 | for (i = 0; i < recog_data.n_operands; i++) | |
8170 | { | |
8171 | cselib_val *v; | |
8172 | struct elt_loc_list *l; | |
8173 | ||
8174 | CLEAR_HARD_REG_SET (equiv_regs[i]); | |
8175 | ||
8176 | /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem | |
8177 | right, so avoid the problem here. */ | |
8178 | if (GET_CODE (recog_data.operand[i]) == CODE_LABEL) | |
8179 | continue; | |
8180 | ||
8181 | v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0); | |
8182 | if (! v) | |
8183 | continue; | |
8184 | ||
8185 | for (l = v->locs; l; l = l->next) | |
8186 | if (GET_CODE (l->loc) == REG) | |
8187 | SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc)); | |
8188 | } | |
8189 | ||
1ccbefce | 8190 | for (i = 0; i < recog_data.n_operands; i++) |
e9a25f70 JL |
8191 | { |
8192 | enum machine_mode mode; | |
8193 | int regno; | |
9b3142b3 | 8194 | const char *p; |
e9a25f70 | 8195 | |
1ccbefce RH |
8196 | op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int)); |
8197 | for (j = 0; j < recog_data.n_alternatives; j++) | |
e9a25f70 JL |
8198 | op_alt_regno[i][j] = -1; |
8199 | ||
1ccbefce RH |
8200 | p = constraints[i] = recog_data.constraints[i]; |
8201 | mode = recog_data.operand_mode[i]; | |
e9a25f70 JL |
8202 | |
8203 | /* Add the reject values for each alternative given by the constraints | |
8204 | for this operand. */ | |
8205 | j = 0; | |
8206 | while (*p != '\0') | |
8207 | { | |
8208 | char c = *p++; | |
8209 | if (c == ',') | |
8210 | j++; | |
8211 | else if (c == '?') | |
8212 | alternative_reject[j] += 3; | |
8213 | else if (c == '!') | |
8214 | alternative_reject[j] += 300; | |
8215 | } | |
8216 | ||
8217 | /* We won't change operands which are already registers. We | |
8218 | also don't want to modify output operands. */ | |
1ccbefce | 8219 | regno = true_regnum (recog_data.operand[i]); |
e9a25f70 JL |
8220 | if (regno >= 0 |
8221 | || constraints[i][0] == '=' | |
8222 | || constraints[i][0] == '+') | |
8223 | continue; | |
8224 | ||
8225 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
8226 | { | |
8227 | int class = (int) NO_REGS; | |
8228 | ||
eab5c70a | 8229 | if (! TEST_HARD_REG_BIT (equiv_regs[i], regno)) |
e9a25f70 JL |
8230 | continue; |
8231 | ||
0254c561 JC |
8232 | REGNO (reg) = regno; |
8233 | PUT_MODE (reg, mode); | |
8234 | ||
e9a25f70 JL |
8235 | /* We found a register equal to this operand. Now look for all |
8236 | alternatives that can accept this register and have not been | |
8237 | assigned a register they can use yet. */ | |
8238 | j = 0; | |
8239 | p = constraints[i]; | |
8240 | for (;;) | |
31418d35 | 8241 | { |
e9a25f70 | 8242 | char c = *p++; |
05d10675 | 8243 | |
e9a25f70 | 8244 | switch (c) |
31418d35 | 8245 | { |
e9a25f70 JL |
8246 | case '=': case '+': case '?': |
8247 | case '#': case '&': case '!': | |
05d10675 | 8248 | case '*': case '%': |
e9a25f70 | 8249 | case '0': case '1': case '2': case '3': case '4': |
c5c76735 | 8250 | case '5': case '6': case '7': case '8': case '9': |
e9a25f70 JL |
8251 | case 'm': case '<': case '>': case 'V': case 'o': |
8252 | case 'E': case 'F': case 'G': case 'H': | |
8253 | case 's': case 'i': case 'n': | |
8254 | case 'I': case 'J': case 'K': case 'L': | |
8255 | case 'M': case 'N': case 'O': case 'P': | |
8256 | #ifdef EXTRA_CONSTRAINT | |
8257 | case 'Q': case 'R': case 'S': case 'T': case 'U': | |
8258 | #endif | |
8259 | case 'p': case 'X': | |
8260 | /* These don't say anything we care about. */ | |
8261 | break; | |
8262 | ||
8263 | case 'g': case 'r': | |
8264 | class = reg_class_subunion[(int) class][(int) GENERAL_REGS]; | |
8265 | break; | |
8266 | ||
8267 | default: | |
8268 | class | |
e51712db | 8269 | = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)]; |
e9a25f70 | 8270 | break; |
31418d35 | 8271 | |
e9a25f70 JL |
8272 | case ',': case '\0': |
8273 | /* See if REGNO fits this alternative, and set it up as the | |
8274 | replacement register if we don't have one for this | |
0254c561 JC |
8275 | alternative yet and the operand being replaced is not |
8276 | a cheap CONST_INT. */ | |
e9a25f70 | 8277 | if (op_alt_regno[i][j] == -1 |
0254c561 | 8278 | && reg_fits_class_p (reg, class, 0, mode) |
1ccbefce RH |
8279 | && (GET_CODE (recog_data.operand[i]) != CONST_INT |
8280 | || (rtx_cost (recog_data.operand[i], SET) | |
8281 | > rtx_cost (reg, SET)))) | |
31418d35 | 8282 | { |
e9a25f70 JL |
8283 | alternative_nregs[j]++; |
8284 | op_alt_regno[i][j] = regno; | |
31418d35 | 8285 | } |
e9a25f70 JL |
8286 | j++; |
8287 | break; | |
31418d35 ILT |
8288 | } |
8289 | ||
e9a25f70 JL |
8290 | if (c == '\0') |
8291 | break; | |
8292 | } | |
8293 | } | |
8294 | } | |
8295 | ||
8296 | /* Record all alternatives which are better or equal to the currently | |
8297 | matching one in the alternative_order array. */ | |
1ccbefce | 8298 | for (i = j = 0; i < recog_data.n_alternatives; i++) |
e9a25f70 JL |
8299 | if (alternative_reject[i] <= alternative_reject[which_alternative]) |
8300 | alternative_order[j++] = i; | |
1ccbefce | 8301 | recog_data.n_alternatives = j; |
e9a25f70 JL |
8302 | |
8303 | /* Sort it. Given a small number of alternatives, a dumb algorithm | |
8304 | won't hurt too much. */ | |
1ccbefce | 8305 | for (i = 0; i < recog_data.n_alternatives - 1; i++) |
e9a25f70 JL |
8306 | { |
8307 | int best = i; | |
8308 | int best_reject = alternative_reject[alternative_order[i]]; | |
8309 | int best_nregs = alternative_nregs[alternative_order[i]]; | |
8310 | int tmp; | |
8311 | ||
1ccbefce | 8312 | for (j = i + 1; j < recog_data.n_alternatives; j++) |
e9a25f70 JL |
8313 | { |
8314 | int this_reject = alternative_reject[alternative_order[j]]; | |
8315 | int this_nregs = alternative_nregs[alternative_order[j]]; | |
8316 | ||
8317 | if (this_reject < best_reject | |
8318 | || (this_reject == best_reject && this_nregs < best_nregs)) | |
8319 | { | |
8320 | best = j; | |
8321 | best_reject = this_reject; | |
8322 | best_nregs = this_nregs; | |
31418d35 | 8323 | } |
2a9fb548 | 8324 | } |
05d10675 | 8325 | |
e9a25f70 JL |
8326 | tmp = alternative_order[best]; |
8327 | alternative_order[best] = alternative_order[i]; | |
8328 | alternative_order[i] = tmp; | |
8329 | } | |
05d10675 | 8330 | |
e9a25f70 JL |
8331 | /* Substitute the operands as determined by op_alt_regno for the best |
8332 | alternative. */ | |
8333 | j = alternative_order[0]; | |
e9a25f70 | 8334 | |
1ccbefce | 8335 | for (i = 0; i < recog_data.n_operands; i++) |
e9a25f70 | 8336 | { |
1ccbefce | 8337 | enum machine_mode mode = recog_data.operand_mode[i]; |
e9a25f70 JL |
8338 | if (op_alt_regno[i][j] == -1) |
8339 | continue; | |
8340 | ||
1ccbefce | 8341 | validate_change (insn, recog_data.operand_loc[i], |
38a448ca | 8342 | gen_rtx_REG (mode, op_alt_regno[i][j]), 1); |
e9a25f70 JL |
8343 | } |
8344 | ||
1ccbefce | 8345 | for (i = recog_data.n_dups - 1; i >= 0; i--) |
e9a25f70 | 8346 | { |
1ccbefce RH |
8347 | int op = recog_data.dup_num[i]; |
8348 | enum machine_mode mode = recog_data.operand_mode[op]; | |
e9a25f70 JL |
8349 | |
8350 | if (op_alt_regno[op][j] == -1) | |
8351 | continue; | |
8352 | ||
1ccbefce | 8353 | validate_change (insn, recog_data.dup_loc[i], |
38a448ca | 8354 | gen_rtx_REG (mode, op_alt_regno[op][j]), 1); |
2a9fb548 | 8355 | } |
e9a25f70 | 8356 | |
e9a25f70 | 8357 | return apply_change_group (); |
2a9fb548 | 8358 | } |
5adf6da0 R |
8359 | \f |
8360 | /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg | |
8361 | addressing now. | |
8362 | This code might also be useful when reload gave up on reg+reg addresssing | |
8363 | because of clashes between the return register and INDEX_REG_CLASS. */ | |
8364 | ||
8365 | /* The maximum number of uses of a register we can keep track of to | |
8366 | replace them with reg+reg addressing. */ | |
8367 | #define RELOAD_COMBINE_MAX_USES 6 | |
8368 | ||
8369 | /* INSN is the insn where a register has ben used, and USEP points to the | |
8370 | location of the register within the rtl. */ | |
8371 | struct reg_use { rtx insn, *usep; }; | |
8372 | ||
8373 | /* If the register is used in some unknown fashion, USE_INDEX is negative. | |
8374 | If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID | |
8375 | indicates where it becomes live again. | |
8376 | Otherwise, USE_INDEX is the index of the last encountered use of the | |
8377 | register (which is first among these we have seen since we scan backwards), | |
8378 | OFFSET contains the constant offset that is added to the register in | |
8379 | all encountered uses, and USE_RUID indicates the first encountered, i.e. | |
ed937a19 R |
8380 | last, of these uses. |
8381 | STORE_RUID is always meaningful if we only want to use a value in a | |
8382 | register in a different place: it denotes the next insn in the insn | |
8383 | stream (i.e. the last ecountered) that sets or clobbers the register. */ | |
5adf6da0 R |
8384 | static struct |
8385 | { | |
8386 | struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; | |
8387 | int use_index; | |
8388 | rtx offset; | |
8389 | int store_ruid; | |
8390 | int use_ruid; | |
8391 | } reg_state[FIRST_PSEUDO_REGISTER]; | |
8392 | ||
8393 | /* Reverse linear uid. This is increased in reload_combine while scanning | |
8394 | the instructions from last to first. It is used to set last_label_ruid | |
8395 | and the store_ruid / use_ruid fields in reg_state. */ | |
8396 | static int reload_combine_ruid; | |
8397 | ||
b0634509 R |
8398 | #define LABEL_LIVE(LABEL) \ |
8399 | (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) | |
8400 | ||
5adf6da0 R |
8401 | static void |
8402 | reload_combine () | |
8403 | { | |
8404 | rtx insn, set; | |
8405 | int first_index_reg = 1, last_index_reg = 0; | |
8406 | int i; | |
f8cd4126 | 8407 | unsigned int r; |
5adf6da0 | 8408 | int last_label_ruid; |
b0634509 R |
8409 | int min_labelno, n_labels; |
8410 | HARD_REG_SET ever_live_at_start, *label_live; | |
5adf6da0 R |
8411 | |
8412 | /* If reg+reg can be used in offsetable memory adresses, the main chunk of | |
8413 | reload has already used it where appropriate, so there is no use in | |
8414 | trying to generate it now. */ | |
03acd8f8 | 8415 | if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS) |
5adf6da0 R |
8416 | return; |
8417 | ||
8418 | /* To avoid wasting too much time later searching for an index register, | |
8419 | determine the minimum and maximum index register numbers. */ | |
f8cd4126 RK |
8420 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
8421 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) | |
8422 | { | |
4c3f1588 RK |
8423 | if (! first_index_reg) |
8424 | first_index_reg = r; | |
8425 | ||
8426 | last_index_reg = r; | |
f8cd4126 RK |
8427 | } |
8428 | ||
5adf6da0 R |
8429 | /* If no index register is available, we can quit now. */ |
8430 | if (first_index_reg > last_index_reg) | |
8431 | return; | |
8432 | ||
b0634509 R |
8433 | /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime |
8434 | information is a bit fuzzy immediately after reload, but it's | |
8435 | still good enough to determine which registers are live at a jump | |
8436 | destination. */ | |
8437 | min_labelno = get_first_label_num (); | |
8438 | n_labels = max_label_num () - min_labelno; | |
8439 | label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET)); | |
8440 | CLEAR_HARD_REG_SET (ever_live_at_start); | |
f8cd4126 | 8441 | |
b0634509 R |
8442 | for (i = n_basic_blocks - 1; i >= 0; i--) |
8443 | { | |
3b413743 | 8444 | insn = BLOCK_HEAD (i); |
b0634509 R |
8445 | if (GET_CODE (insn) == CODE_LABEL) |
8446 | { | |
8447 | HARD_REG_SET live; | |
8448 | ||
f8cd4126 RK |
8449 | REG_SET_TO_HARD_REG_SET (live, |
8450 | BASIC_BLOCK (i)->global_live_at_start); | |
8451 | compute_use_by_pseudos (&live, | |
8452 | BASIC_BLOCK (i)->global_live_at_start); | |
b0634509 R |
8453 | COPY_HARD_REG_SET (LABEL_LIVE (insn), live); |
8454 | IOR_HARD_REG_SET (ever_live_at_start, live); | |
8455 | } | |
8456 | } | |
8457 | ||
5adf6da0 R |
8458 | /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ |
8459 | last_label_ruid = reload_combine_ruid = 0; | |
f8cd4126 | 8460 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
5adf6da0 | 8461 | { |
f8cd4126 RK |
8462 | reg_state[r].store_ruid = reload_combine_ruid; |
8463 | if (fixed_regs[r]) | |
8464 | reg_state[r].use_index = -1; | |
5adf6da0 | 8465 | else |
f8cd4126 | 8466 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; |
5adf6da0 R |
8467 | } |
8468 | ||
8469 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) | |
8470 | { | |
8471 | rtx note; | |
8472 | ||
8473 | /* We cannot do our optimization across labels. Invalidating all the use | |
8474 | information we have would be costly, so we just note where the label | |
05d10675 | 8475 | is and then later disable any optimization that would cross it. */ |
5adf6da0 R |
8476 | if (GET_CODE (insn) == CODE_LABEL) |
8477 | last_label_ruid = reload_combine_ruid; | |
f8cd4126 RK |
8478 | else if (GET_CODE (insn) == BARRIER) |
8479 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
8480 | if (! fixed_regs[r]) | |
8481 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
8482 | ||
5adf6da0 R |
8483 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') |
8484 | continue; | |
f8cd4126 | 8485 | |
5adf6da0 R |
8486 | reload_combine_ruid++; |
8487 | ||
8488 | /* Look for (set (REGX) (CONST_INT)) | |
eceef4c9 BS |
8489 | (set (REGX) (PLUS (REGX) (REGY))) |
8490 | ... | |
8491 | ... (MEM (REGX)) ... | |
5adf6da0 | 8492 | and convert it to |
eceef4c9 BS |
8493 | (set (REGZ) (CONST_INT)) |
8494 | ... | |
8495 | ... (MEM (PLUS (REGZ) (REGY)))... . | |
5adf6da0 R |
8496 | |
8497 | First, check that we have (set (REGX) (PLUS (REGX) (REGY))) | |
8498 | and that we know all uses of REGX before it dies. */ | |
2abbc1bd R |
8499 | set = single_set (insn); |
8500 | if (set != NULL_RTX | |
5adf6da0 R |
8501 | && GET_CODE (SET_DEST (set)) == REG |
8502 | && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)), | |
8503 | GET_MODE (SET_DEST (set))) | |
8504 | == 1) | |
8505 | && GET_CODE (SET_SRC (set)) == PLUS | |
8506 | && GET_CODE (XEXP (SET_SRC (set), 1)) == REG | |
8507 | && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set)) | |
8508 | && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid) | |
8509 | { | |
8510 | rtx reg = SET_DEST (set); | |
8511 | rtx plus = SET_SRC (set); | |
8512 | rtx base = XEXP (plus, 1); | |
8513 | rtx prev = prev_nonnote_insn (insn); | |
8514 | rtx prev_set = prev ? single_set (prev) : NULL_RTX; | |
f8cd4126 | 8515 | unsigned int regno = REGNO (reg); |
6a651371 | 8516 | rtx const_reg = NULL_RTX; |
5adf6da0 R |
8517 | rtx reg_sum = NULL_RTX; |
8518 | ||
8519 | /* Now, we need an index register. | |
8520 | We'll set index_reg to this index register, const_reg to the | |
8521 | register that is to be loaded with the constant | |
8522 | (denoted as REGZ in the substitution illustration above), | |
8523 | and reg_sum to the register-register that we want to use to | |
8524 | substitute uses of REG (typically in MEMs) with. | |
8525 | First check REG and BASE for being index registers; | |
8526 | we can use them even if they are not dead. */ | |
8527 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) | |
8528 | || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], | |
8529 | REGNO (base))) | |
8530 | { | |
8531 | const_reg = reg; | |
8532 | reg_sum = plus; | |
8533 | } | |
8534 | else | |
8535 | { | |
05d10675 BS |
8536 | /* Otherwise, look for a free index register. Since we have |
8537 | checked above that neiter REG nor BASE are index registers, | |
8538 | if we find anything at all, it will be different from these | |
8539 | two registers. */ | |
8540 | for (i = first_index_reg; i <= last_index_reg; i++) | |
5adf6da0 | 8541 | { |
f8cd4126 RK |
8542 | if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], |
8543 | i) | |
5adf6da0 R |
8544 | && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES |
8545 | && reg_state[i].store_ruid <= reg_state[regno].use_ruid | |
8546 | && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1) | |
8547 | { | |
8548 | rtx index_reg = gen_rtx_REG (GET_MODE (reg), i); | |
f8cd4126 | 8549 | |
5adf6da0 R |
8550 | const_reg = index_reg; |
8551 | reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); | |
8552 | break; | |
8553 | } | |
8554 | } | |
8555 | } | |
f8cd4126 | 8556 | |
ed937a19 R |
8557 | /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that |
8558 | (REGY), i.e. BASE, is not clobbered before the last use we'll | |
8559 | create. */ | |
f8cd4126 | 8560 | if (prev_set != 0 |
5adf6da0 R |
8561 | && GET_CODE (SET_SRC (prev_set)) == CONST_INT |
8562 | && rtx_equal_p (SET_DEST (prev_set), reg) | |
8563 | && reg_state[regno].use_index >= 0 | |
f8cd4126 RK |
8564 | && (reg_state[REGNO (base)].store_ruid |
8565 | <= reg_state[regno].use_ruid) | |
8566 | && reg_sum != 0) | |
5adf6da0 R |
8567 | { |
8568 | int i; | |
8569 | ||
f8cd4126 | 8570 | /* Change destination register and, if necessary, the |
5adf6da0 R |
8571 | constant value in PREV, the constant loading instruction. */ |
8572 | validate_change (prev, &SET_DEST (prev_set), const_reg, 1); | |
8573 | if (reg_state[regno].offset != const0_rtx) | |
8574 | validate_change (prev, | |
8575 | &SET_SRC (prev_set), | |
8576 | GEN_INT (INTVAL (SET_SRC (prev_set)) | |
8577 | + INTVAL (reg_state[regno].offset)), | |
8578 | 1); | |
f8cd4126 | 8579 | |
5adf6da0 R |
8580 | /* Now for every use of REG that we have recorded, replace REG |
8581 | with REG_SUM. */ | |
8582 | for (i = reg_state[regno].use_index; | |
8583 | i < RELOAD_COMBINE_MAX_USES; i++) | |
8584 | validate_change (reg_state[regno].reg_use[i].insn, | |
8585 | reg_state[regno].reg_use[i].usep, | |
8586 | reg_sum, 1); | |
8587 | ||
8588 | if (apply_change_group ()) | |
8589 | { | |
8590 | rtx *np; | |
8591 | ||
8592 | /* Delete the reg-reg addition. */ | |
8593 | PUT_CODE (insn, NOTE); | |
8594 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
8595 | NOTE_SOURCE_FILE (insn) = 0; | |
8596 | ||
8597 | if (reg_state[regno].offset != const0_rtx) | |
f8cd4126 RK |
8598 | /* Previous REG_EQUIV / REG_EQUAL notes for PREV |
8599 | are now invalid. */ | |
8600 | for (np = ®_NOTES (prev); *np; ) | |
8601 | { | |
8602 | if (REG_NOTE_KIND (*np) == REG_EQUAL | |
8603 | || REG_NOTE_KIND (*np) == REG_EQUIV) | |
8604 | *np = XEXP (*np, 1); | |
8605 | else | |
8606 | np = &XEXP (*np, 1); | |
8607 | } | |
8608 | ||
5adf6da0 | 8609 | reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; |
f8cd4126 RK |
8610 | reg_state[REGNO (const_reg)].store_ruid |
8611 | = reload_combine_ruid; | |
5adf6da0 R |
8612 | continue; |
8613 | } | |
8614 | } | |
8615 | } | |
f8cd4126 RK |
8616 | |
8617 | note_stores (PATTERN (insn), reload_combine_note_store, NULL); | |
8618 | ||
5adf6da0 R |
8619 | if (GET_CODE (insn) == CALL_INSN) |
8620 | { | |
8621 | rtx link; | |
8622 | ||
f8cd4126 RK |
8623 | for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
8624 | if (call_used_regs[r]) | |
8625 | { | |
8626 | reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
8627 | reg_state[r].store_ruid = reload_combine_ruid; | |
8628 | } | |
8629 | ||
5adf6da0 R |
8630 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; |
8631 | link = XEXP (link, 1)) | |
f8cd4126 RK |
8632 | if (GET_CODE (XEXP (XEXP (link, 0), 0)) == REG) |
8633 | { | |
8634 | unsigned int regno = REGNO (XEXP (XEXP (link, 0), 0)); | |
8635 | ||
8636 | if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
8637 | { | |
8638 | reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; | |
8639 | reg_state[regno].store_ruid = reload_combine_ruid; | |
8640 | } | |
8641 | else | |
8642 | reg_state[regno].use_index = -1; | |
8643 | } | |
5adf6da0 | 8644 | } |
f8cd4126 RK |
8645 | |
8646 | else if (GET_CODE (insn) == JUMP_INSN | |
8647 | && GET_CODE (PATTERN (insn)) != RETURN) | |
5adf6da0 R |
8648 | { |
8649 | /* Non-spill registers might be used at the call destination in | |
8650 | some unknown fashion, so we have to mark the unknown use. */ | |
b0634509 | 8651 | HARD_REG_SET *live; |
f8cd4126 | 8652 | |
b0634509 R |
8653 | if ((condjump_p (insn) || condjump_in_parallel_p (insn)) |
8654 | && JUMP_LABEL (insn)) | |
8655 | live = &LABEL_LIVE (JUMP_LABEL (insn)); | |
8656 | else | |
8657 | live = &ever_live_at_start; | |
f8cd4126 | 8658 | |
5adf6da0 | 8659 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i) |
f8cd4126 RK |
8660 | if (TEST_HARD_REG_BIT (*live, i)) |
8661 | reg_state[i].use_index = -1; | |
5adf6da0 | 8662 | } |
f8cd4126 | 8663 | |
5adf6da0 R |
8664 | reload_combine_note_use (&PATTERN (insn), insn); |
8665 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
8666 | { | |
8667 | if (REG_NOTE_KIND (note) == REG_INC | |
8668 | && GET_CODE (XEXP (note, 0)) == REG) | |
ed937a19 R |
8669 | { |
8670 | int regno = REGNO (XEXP (note, 0)); | |
8671 | ||
8672 | reg_state[regno].store_ruid = reload_combine_ruid; | |
8673 | reg_state[regno].use_index = -1; | |
8674 | } | |
5adf6da0 R |
8675 | } |
8676 | } | |
f8cd4126 | 8677 | |
b0634509 | 8678 | free (label_live); |
5adf6da0 R |
8679 | } |
8680 | ||
8681 | /* Check if DST is a register or a subreg of a register; if it is, | |
8682 | update reg_state[regno].store_ruid and reg_state[regno].use_index | |
f93233bb | 8683 | accordingly. Called via note_stores from reload_combine. */ |
f8cd4126 | 8684 | |
5adf6da0 | 8685 | static void |
84832317 | 8686 | reload_combine_note_store (dst, set, data) |
f93233bb | 8687 | rtx dst, set; |
84832317 | 8688 | void *data ATTRIBUTE_UNUSED; |
5adf6da0 R |
8689 | { |
8690 | int regno = 0; | |
8691 | int i; | |
54ed0905 | 8692 | enum machine_mode mode = GET_MODE (dst); |
5adf6da0 R |
8693 | |
8694 | if (GET_CODE (dst) == SUBREG) | |
8695 | { | |
8696 | regno = SUBREG_WORD (dst); | |
8697 | dst = SUBREG_REG (dst); | |
8698 | } | |
8699 | if (GET_CODE (dst) != REG) | |
8700 | return; | |
8701 | regno += REGNO (dst); | |
54ca6ffa | 8702 | |
5adf6da0 | 8703 | /* note_stores might have stripped a STRICT_LOW_PART, so we have to be |
05d10675 | 8704 | careful with registers / register parts that are not full words. |
54ca6ffa JL |
8705 | |
8706 | Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */ | |
8707 | if (GET_CODE (set) != SET | |
8708 | || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT | |
8709 | || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT | |
8710 | || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) | |
ed937a19 | 8711 | { |
54ed0905 | 8712 | for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--) |
f93233bb JL |
8713 | { |
8714 | reg_state[i].use_index = -1; | |
8715 | reg_state[i].store_ruid = reload_combine_ruid; | |
8716 | } | |
ed937a19 | 8717 | } |
5adf6da0 R |
8718 | else |
8719 | { | |
54ed0905 | 8720 | for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--) |
5adf6da0 R |
8721 | { |
8722 | reg_state[i].store_ruid = reload_combine_ruid; | |
8723 | reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | |
8724 | } | |
8725 | } | |
8726 | } | |
8727 | ||
8728 | /* XP points to a piece of rtl that has to be checked for any uses of | |
8729 | registers. | |
8730 | *XP is the pattern of INSN, or a part of it. | |
8731 | Called from reload_combine, and recursively by itself. */ | |
8732 | static void | |
8733 | reload_combine_note_use (xp, insn) | |
8734 | rtx *xp, insn; | |
8735 | { | |
8736 | rtx x = *xp; | |
8737 | enum rtx_code code = x->code; | |
6f7d635c | 8738 | const char *fmt; |
5adf6da0 R |
8739 | int i, j; |
8740 | rtx offset = const0_rtx; /* For the REG case below. */ | |
8741 | ||
8742 | switch (code) | |
8743 | { | |
8744 | case SET: | |
8745 | if (GET_CODE (SET_DEST (x)) == REG) | |
8746 | { | |
8747 | reload_combine_note_use (&SET_SRC (x), insn); | |
8748 | return; | |
8749 | } | |
8750 | break; | |
8751 | ||
6ce7e0f9 R |
8752 | case USE: |
8753 | /* If this is the USE of a return value, we can't change it. */ | |
8754 | if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0))) | |
8755 | { | |
8756 | /* Mark the return register as used in an unknown fashion. */ | |
8757 | rtx reg = XEXP (x, 0); | |
8758 | int regno = REGNO (reg); | |
8759 | int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg)); | |
8760 | ||
8761 | while (--nregs >= 0) | |
8762 | reg_state[regno + nregs].use_index = -1; | |
8763 | return; | |
8764 | } | |
8765 | break; | |
8766 | ||
5adf6da0 R |
8767 | case CLOBBER: |
8768 | if (GET_CODE (SET_DEST (x)) == REG) | |
8769 | return; | |
8770 | break; | |
8771 | ||
8772 | case PLUS: | |
8773 | /* We are interested in (plus (reg) (const_int)) . */ | |
8774 | if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT) | |
8775 | break; | |
8776 | offset = XEXP (x, 1); | |
8777 | x = XEXP (x, 0); | |
05d10675 | 8778 | /* Fall through. */ |
5adf6da0 R |
8779 | case REG: |
8780 | { | |
8781 | int regno = REGNO (x); | |
8782 | int use_index; | |
6ce7e0f9 | 8783 | int nregs; |
5adf6da0 R |
8784 | |
8785 | /* Some spurious USEs of pseudo registers might remain. | |
8786 | Just ignore them. */ | |
8787 | if (regno >= FIRST_PSEUDO_REGISTER) | |
8788 | return; | |
8789 | ||
6ce7e0f9 R |
8790 | nregs = HARD_REGNO_NREGS (regno, GET_MODE (x)); |
8791 | ||
8792 | /* We can't substitute into multi-hard-reg uses. */ | |
8793 | if (nregs > 1) | |
8794 | { | |
8795 | while (--nregs >= 0) | |
8796 | reg_state[regno + nregs].use_index = -1; | |
8797 | return; | |
8798 | } | |
8799 | ||
5adf6da0 R |
8800 | /* If this register is already used in some unknown fashion, we |
8801 | can't do anything. | |
8802 | If we decrement the index from zero to -1, we can't store more | |
8803 | uses, so this register becomes used in an unknown fashion. */ | |
8804 | use_index = --reg_state[regno].use_index; | |
8805 | if (use_index < 0) | |
8806 | return; | |
8807 | ||
8808 | if (use_index != RELOAD_COMBINE_MAX_USES - 1) | |
8809 | { | |
8810 | /* We have found another use for a register that is already | |
8811 | used later. Check if the offsets match; if not, mark the | |
8812 | register as used in an unknown fashion. */ | |
8813 | if (! rtx_equal_p (offset, reg_state[regno].offset)) | |
8814 | { | |
8815 | reg_state[regno].use_index = -1; | |
8816 | return; | |
8817 | } | |
8818 | } | |
8819 | else | |
8820 | { | |
8821 | /* This is the first use of this register we have seen since we | |
8822 | marked it as dead. */ | |
8823 | reg_state[regno].offset = offset; | |
8824 | reg_state[regno].use_ruid = reload_combine_ruid; | |
8825 | } | |
8826 | reg_state[regno].reg_use[use_index].insn = insn; | |
8827 | reg_state[regno].reg_use[use_index].usep = xp; | |
8828 | return; | |
8829 | } | |
8830 | ||
8831 | default: | |
8832 | break; | |
8833 | } | |
8834 | ||
8835 | /* Recursively process the components of X. */ | |
8836 | fmt = GET_RTX_FORMAT (code); | |
8837 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
8838 | { | |
8839 | if (fmt[i] == 'e') | |
8840 | reload_combine_note_use (&XEXP (x, i), insn); | |
8841 | else if (fmt[i] == 'E') | |
8842 | { | |
8843 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
8844 | reload_combine_note_use (&XVECEXP (x, i, j), insn); | |
8845 | } | |
8846 | } | |
8847 | } | |
8848 | \f | |
8849 | /* See if we can reduce the cost of a constant by replacing a move with | |
8850 | an add. */ | |
8851 | /* We cannot do our optimization across labels. Invalidating all the | |
8852 | information about register contents we have would be costly, so we | |
8853 | use last_label_luid (local variable of reload_cse_move2add) to note | |
8854 | where the label is and then later disable any optimization that would | |
8855 | cross it. | |
8856 | reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if | |
8857 | reg_set_luid[n] is larger than last_label_luid[n] . */ | |
8858 | static int reg_set_luid[FIRST_PSEUDO_REGISTER]; | |
770ae6cc | 8859 | |
5adf6da0 R |
8860 | /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] / |
8861 | reg_mode[n] to be valid. | |
8862 | If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n | |
8863 | has been set to reg_offset[n] in mode reg_mode[n] . | |
8864 | If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative, | |
8865 | register n has been set to the sum of reg_offset[n] and register | |
8866 | reg_base_reg[n], calculated in mode reg_mode[n] . */ | |
8867 | static rtx reg_offset[FIRST_PSEUDO_REGISTER]; | |
8868 | static int reg_base_reg[FIRST_PSEUDO_REGISTER]; | |
8869 | static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; | |
770ae6cc | 8870 | |
5adf6da0 R |
8871 | /* move2add_luid is linearily increased while scanning the instructions |
8872 | from first to last. It is used to set reg_set_luid in | |
6764d250 | 8873 | reload_cse_move2add and move2add_note_store. */ |
5adf6da0 R |
8874 | static int move2add_luid; |
8875 | ||
ccc4ae07 | 8876 | /* Generate a CONST_INT and force it in the range of MODE. */ |
770ae6cc | 8877 | |
ccc4ae07 AS |
8878 | static rtx |
8879 | gen_mode_int (mode, value) | |
8880 | enum machine_mode mode; | |
8881 | HOST_WIDE_INT value; | |
8882 | { | |
8883 | HOST_WIDE_INT cval = value & GET_MODE_MASK (mode); | |
8884 | int width = GET_MODE_BITSIZE (mode); | |
8885 | ||
8886 | /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number, | |
8887 | sign extend it. */ | |
8888 | if (width > 0 && width < HOST_BITS_PER_WIDE_INT | |
8889 | && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) | |
8890 | cval |= (HOST_WIDE_INT) -1 << width; | |
8891 | ||
8892 | return GEN_INT (cval); | |
8893 | } | |
8894 | ||
5adf6da0 R |
8895 | static void |
8896 | reload_cse_move2add (first) | |
8897 | rtx first; | |
8898 | { | |
8899 | int i; | |
8900 | rtx insn; | |
8901 | int last_label_luid; | |
5adf6da0 R |
8902 | |
8903 | for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--) | |
6764d250 BS |
8904 | reg_set_luid[i] = 0; |
8905 | ||
5adf6da0 R |
8906 | last_label_luid = 0; |
8907 | move2add_luid = 1; | |
8908 | for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++) | |
8909 | { | |
8910 | rtx pat, note; | |
8911 | ||
8912 | if (GET_CODE (insn) == CODE_LABEL) | |
8913 | last_label_luid = move2add_luid; | |
8914 | if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') | |
8915 | continue; | |
8916 | pat = PATTERN (insn); | |
8917 | /* For simplicity, we only perform this optimization on | |
8918 | straightforward SETs. */ | |
8919 | if (GET_CODE (pat) == SET | |
8920 | && GET_CODE (SET_DEST (pat)) == REG) | |
8921 | { | |
8922 | rtx reg = SET_DEST (pat); | |
8923 | int regno = REGNO (reg); | |
8924 | rtx src = SET_SRC (pat); | |
8925 | ||
8926 | /* Check if we have valid information on the contents of this | |
8927 | register in the mode of REG. */ | |
8928 | /* ??? We don't know how zero / sign extension is handled, hence | |
8929 | we can't go from a narrower to a wider mode. */ | |
8930 | if (reg_set_luid[regno] > last_label_luid | |
a3afe920 R |
8931 | && ((GET_MODE_SIZE (GET_MODE (reg)) |
8932 | == GET_MODE_SIZE (reg_mode[regno])) | |
8933 | || ((GET_MODE_SIZE (GET_MODE (reg)) | |
8934 | <= GET_MODE_SIZE (reg_mode[regno])) | |
8935 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (reg)), | |
8936 | GET_MODE_BITSIZE (reg_mode[regno])))) | |
05d10675 | 8937 | && GET_CODE (reg_offset[regno]) == CONST_INT) |
5adf6da0 R |
8938 | { |
8939 | /* Try to transform (set (REGX) (CONST_INT A)) | |
8940 | ... | |
8941 | (set (REGX) (CONST_INT B)) | |
8942 | to | |
8943 | (set (REGX) (CONST_INT A)) | |
8944 | ... | |
8945 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
8946 | ||
8947 | if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0) | |
8948 | { | |
8949 | int success = 0; | |
ccc4ae07 AS |
8950 | rtx new_src |
8951 | = gen_mode_int (GET_MODE (reg), | |
8952 | INTVAL (src) - INTVAL (reg_offset[regno])); | |
5adf6da0 R |
8953 | /* (set (reg) (plus (reg) (const_int 0))) is not canonical; |
8954 | use (set (reg) (reg)) instead. | |
8955 | We don't delete this insn, nor do we convert it into a | |
8956 | note, to avoid losing register notes or the return | |
8957 | value flag. jump2 already knowns how to get rid of | |
8958 | no-op moves. */ | |
8959 | if (new_src == const0_rtx) | |
8960 | success = validate_change (insn, &SET_SRC (pat), reg, 0); | |
8961 | else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET) | |
8962 | && have_add2_insn (GET_MODE (reg))) | |
8963 | success = validate_change (insn, &PATTERN (insn), | |
8964 | gen_add2_insn (reg, new_src), 0); | |
5adf6da0 R |
8965 | reg_set_luid[regno] = move2add_luid; |
8966 | reg_mode[regno] = GET_MODE (reg); | |
8967 | reg_offset[regno] = src; | |
8968 | continue; | |
8969 | } | |
8970 | ||
8971 | /* Try to transform (set (REGX) (REGY)) | |
8972 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
8973 | ... | |
8974 | (set (REGX) (REGY)) | |
8975 | (set (REGX) (PLUS (REGX) (CONST_INT B))) | |
8976 | to | |
8977 | (REGX) (REGY)) | |
8978 | (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
8979 | ... | |
8980 | (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
8981 | else if (GET_CODE (src) == REG | |
770ae6cc | 8982 | && reg_base_reg[regno] == (int) REGNO (src) |
5adf6da0 R |
8983 | && reg_set_luid[regno] > reg_set_luid[REGNO (src)]) |
8984 | { | |
8985 | rtx next = next_nonnote_insn (insn); | |
6a651371 | 8986 | rtx set = NULL_RTX; |
5adf6da0 R |
8987 | if (next) |
8988 | set = single_set (next); | |
8989 | if (next | |
8990 | && set | |
8991 | && SET_DEST (set) == reg | |
8992 | && GET_CODE (SET_SRC (set)) == PLUS | |
8993 | && XEXP (SET_SRC (set), 0) == reg | |
8994 | && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT) | |
8995 | { | |
5adf6da0 | 8996 | rtx src3 = XEXP (SET_SRC (set), 1); |
ccc4ae07 AS |
8997 | rtx new_src |
8998 | = gen_mode_int (GET_MODE (reg), | |
8999 | INTVAL (src3) | |
9000 | - INTVAL (reg_offset[regno])); | |
5adf6da0 R |
9001 | int success = 0; |
9002 | ||
9003 | if (new_src == const0_rtx) | |
9004 | /* See above why we create (set (reg) (reg)) here. */ | |
9005 | success | |
9006 | = validate_change (next, &SET_SRC (set), reg, 0); | |
9007 | else if ((rtx_cost (new_src, PLUS) | |
9008 | < 2 + rtx_cost (src3, SET)) | |
9009 | && have_add2_insn (GET_MODE (reg))) | |
9010 | success | |
9011 | = validate_change (next, &PATTERN (next), | |
9012 | gen_add2_insn (reg, new_src), 0); | |
9013 | if (success) | |
9014 | { | |
5adf6da0 R |
9015 | /* INSN might be the first insn in a basic block |
9016 | if the preceding insn is a conditional jump | |
9017 | or a possible-throwing call. */ | |
9018 | PUT_CODE (insn, NOTE); | |
9019 | NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; | |
9020 | NOTE_SOURCE_FILE (insn) = 0; | |
9021 | } | |
9022 | insn = next; | |
9023 | reg_set_luid[regno] = move2add_luid; | |
9024 | reg_mode[regno] = GET_MODE (reg); | |
9025 | reg_offset[regno] = src3; | |
9026 | continue; | |
9027 | } | |
9028 | } | |
9029 | } | |
9030 | } | |
9031 | ||
9032 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
9033 | { | |
9034 | if (REG_NOTE_KIND (note) == REG_INC | |
9035 | && GET_CODE (XEXP (note, 0)) == REG) | |
9036 | { | |
9037 | /* Indicate that this register has been recently written to, | |
9038 | but the exact contents are not available. */ | |
9039 | int regno = REGNO (XEXP (note, 0)); | |
9040 | if (regno < FIRST_PSEUDO_REGISTER) | |
9041 | { | |
9042 | reg_set_luid[regno] = move2add_luid; | |
9043 | reg_offset[regno] = note; | |
9044 | } | |
9045 | } | |
5adf6da0 | 9046 | } |
84832317 | 9047 | note_stores (PATTERN (insn), move2add_note_store, NULL); |
5adf6da0 R |
9048 | /* If this is a CALL_INSN, all call used registers are stored with |
9049 | unknown values. */ | |
9050 | if (GET_CODE (insn) == CALL_INSN) | |
9051 | { | |
9052 | for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--) | |
9053 | { | |
9054 | if (call_used_regs[i]) | |
9055 | { | |
9056 | reg_set_luid[i] = move2add_luid; | |
9057 | reg_offset[i] = insn; /* Invalidate contents. */ | |
9058 | } | |
9059 | } | |
9060 | } | |
9061 | } | |
9062 | } | |
9063 | ||
9064 | /* SET is a SET or CLOBBER that sets DST. | |
9065 | Update reg_set_luid, reg_offset and reg_base_reg accordingly. | |
9066 | Called from reload_cse_move2add via note_stores. */ | |
770ae6cc | 9067 | |
5adf6da0 | 9068 | static void |
84832317 | 9069 | move2add_note_store (dst, set, data) |
5adf6da0 | 9070 | rtx dst, set; |
84832317 | 9071 | void *data ATTRIBUTE_UNUSED; |
5adf6da0 | 9072 | { |
770ae6cc RK |
9073 | unsigned int regno = 0; |
9074 | unsigned int i; | |
5adf6da0 | 9075 | enum machine_mode mode = GET_MODE (dst); |
770ae6cc | 9076 | |
5adf6da0 R |
9077 | if (GET_CODE (dst) == SUBREG) |
9078 | { | |
9079 | regno = SUBREG_WORD (dst); | |
9080 | dst = SUBREG_REG (dst); | |
9081 | } | |
770ae6cc | 9082 | |
5adf6da0 R |
9083 | if (GET_CODE (dst) != REG) |
9084 | return; | |
9085 | ||
9086 | regno += REGNO (dst); | |
9087 | ||
f93233bb JL |
9088 | if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET |
9089 | && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT | |
9090 | && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT | |
9091 | && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) | |
5adf6da0 R |
9092 | { |
9093 | rtx src = SET_SRC (set); | |
9094 | ||
9095 | reg_mode[regno] = mode; | |
9096 | switch (GET_CODE (src)) | |
9097 | { | |
9098 | case PLUS: | |
9099 | { | |
9100 | rtx src0 = XEXP (src, 0); | |
770ae6cc | 9101 | |
5adf6da0 R |
9102 | if (GET_CODE (src0) == REG) |
9103 | { | |
9104 | if (REGNO (src0) != regno | |
9105 | || reg_offset[regno] != const0_rtx) | |
9106 | { | |
9107 | reg_base_reg[regno] = REGNO (src0); | |
9108 | reg_set_luid[regno] = move2add_luid; | |
9109 | } | |
770ae6cc | 9110 | |
5adf6da0 R |
9111 | reg_offset[regno] = XEXP (src, 1); |
9112 | break; | |
9113 | } | |
770ae6cc | 9114 | |
5adf6da0 R |
9115 | reg_set_luid[regno] = move2add_luid; |
9116 | reg_offset[regno] = set; /* Invalidate contents. */ | |
9117 | break; | |
9118 | } | |
9119 | ||
9120 | case REG: | |
9121 | reg_base_reg[regno] = REGNO (SET_SRC (set)); | |
9122 | reg_offset[regno] = const0_rtx; | |
9123 | reg_set_luid[regno] = move2add_luid; | |
9124 | break; | |
9125 | ||
9126 | default: | |
9127 | reg_base_reg[regno] = -1; | |
9128 | reg_offset[regno] = SET_SRC (set); | |
9129 | reg_set_luid[regno] = move2add_luid; | |
9130 | break; | |
9131 | } | |
9132 | } | |
9133 | else | |
9134 | { | |
770ae6cc RK |
9135 | unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode); |
9136 | ||
9137 | for (i = regno; i < endregno; i++) | |
5adf6da0 R |
9138 | { |
9139 | /* Indicate that this register has been recently written to, | |
9140 | but the exact contents are not available. */ | |
9141 | reg_set_luid[i] = move2add_luid; | |
9142 | reg_offset[i] = dst; | |
9143 | } | |
9144 | } | |
9145 | } | |
2dfa9a87 MH |
9146 | |
9147 | #ifdef AUTO_INC_DEC | |
9148 | static void | |
9149 | add_auto_inc_notes (insn, x) | |
9150 | rtx insn; | |
9151 | rtx x; | |
9152 | { | |
9153 | enum rtx_code code = GET_CODE (x); | |
6f7d635c | 9154 | const char *fmt; |
2dfa9a87 MH |
9155 | int i, j; |
9156 | ||
9157 | if (code == MEM && auto_inc_p (XEXP (x, 0))) | |
9158 | { | |
9159 | REG_NOTES (insn) | |
9160 | = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn)); | |
9161 | return; | |
9162 | } | |
9163 | ||
9164 | /* Scan all the operand sub-expressions. */ | |
9165 | fmt = GET_RTX_FORMAT (code); | |
9166 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
9167 | { | |
9168 | if (fmt[i] == 'e') | |
9169 | add_auto_inc_notes (insn, XEXP (x, i)); | |
9170 | else if (fmt[i] == 'E') | |
9171 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
9172 | add_auto_inc_notes (insn, XVECEXP (x, i, j)); | |
9173 | } | |
9174 | } | |
9175 | #endif |